MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
gcfr_regs.h
1 
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39 
40 #ifndef _GCFR_REGS_H_
41 #define _GCFR_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t reg0;
90  __IO uint32_t reg1;
91  __IO uint32_t reg2;
92  __IO uint32_t reg3;
94 
95 /* Register offsets for module GCFR */
102  #define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL)
103  #define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL)
104  #define MXC_R_GCFR_REG2 ((uint32_t)0x00000008UL)
105  #define MXC_R_GCFR_REG3 ((uint32_t)0x0000000CUL)
114  #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS 0
115  #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS))
117  #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS 1
118  #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS))
120  #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS 2
121  #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS))
123  #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS 3
124  #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS))
134  #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS 0
135  #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS))
137  #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS 1
138  #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS))
140  #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS 2
141  #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS))
143  #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS 3
144  #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS))
154  #define MXC_F_GCFR_REG2_CNNX16_0_ISO_POS 0
155  #define MXC_F_GCFR_REG2_CNNX16_0_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_ISO_POS))
157  #define MXC_F_GCFR_REG2_CNNX16_1_ISO_POS 1
158  #define MXC_F_GCFR_REG2_CNNX16_1_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_ISO_POS))
160  #define MXC_F_GCFR_REG2_CNNX16_2_ISO_POS 2
161  #define MXC_F_GCFR_REG2_CNNX16_2_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_ISO_POS))
163  #define MXC_F_GCFR_REG2_CNNX16_3_ISO_POS 3
164  #define MXC_F_GCFR_REG2_CNNX16_3_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_ISO_POS))
174  #define MXC_F_GCFR_REG3_CNNX16_0_RST_POS 0
175  #define MXC_F_GCFR_REG3_CNNX16_0_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_0_RST_POS))
177  #define MXC_F_GCFR_REG3_CNNX16_1_RST_POS 1
178  #define MXC_F_GCFR_REG3_CNNX16_1_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_1_RST_POS))
180  #define MXC_F_GCFR_REG3_CNNX16_2_RST_POS 2
181  #define MXC_F_GCFR_REG3_CNNX16_2_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_2_RST_POS))
183  #define MXC_F_GCFR_REG3_CNNX16_3_RST_POS 3
184  #define MXC_F_GCFR_REG3_CNNX16_3_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_3_RST_POS))
188 #ifdef __cplusplus
189 }
190 #endif
191 
192 #endif /* _GCFR_REGS_H_ */
mxc_gcfr_regs_t::reg3
__IO uint32_t reg3
Definition: gcfr_regs.h:92
mxc_gcfr_regs_t
Definition: gcfr_regs.h:88
mxc_gcfr_regs_t::reg1
__IO uint32_t reg1
Definition: gcfr_regs.h:90
mxc_gcfr_regs_t::reg2
__IO uint32_t reg2
Definition: gcfr_regs.h:91
mxc_gcfr_regs_t::reg0
__IO uint32_t reg0
Definition: gcfr_regs.h:89