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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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Macros | |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL_POS 0 |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL ((uint32_t)(0x7FFFUL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL_POS)) |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL_POS 16 |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL ((uint32_t)(0x3UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL_POS)) |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN_POS 20 |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN_POS)) |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN_POS 21 |
#define | MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN_POS)) |
Receive Control Extension Register 2.
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL ((uint32_t)(0x7FFFUL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL_POS)) |
RX_CTL_EXT2_RX_ARN_INIT_VAL Mask
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL_POS 0 |
RX_CTL_EXT2_RX_ARN_INIT_VAL Position
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN_POS)) |
RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN Mask
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN_POS 21 |
RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN Position
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN_POS)) |
RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN Mask
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN_POS 20 |
RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN Position
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL ((uint32_t)(0x3UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL_POS)) |
RX_CTL_EXT2_RX_ZC_IGN_VAL Mask
#define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL_POS 16 |
RX_CTL_EXT2_RX_ZC_IGN_VAL Position