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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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Signal path control of input buffers and PGA.
#define MXC_F_AFE_ADC_ZERO_PGA_GAIN ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)) |
PGA_GAIN Mask
#define MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS 0 |
PGA_GAIN Position
#define MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)) |
PGA_SIG_PATH Mask
#define MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS 4 |
PGA_SIG_PATH Position
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_128X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_16X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_1X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_2X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_32X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_4X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_64X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS) |
PGA_GAIN_GAIN_8X Setting
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS) |
PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH Setting
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS) |
PGA_SIG_PATH_BYPASS_PATH Setting
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS) |
PGA_SIG_PATH_PGA_PATH Setting
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS) |
PGA_SIG_PATH_RESERVED Setting
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X ((uint8_t)0x7UL) |
PGA_GAIN_GAIN_128X Value
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X ((uint8_t)0x4UL) |
PGA_GAIN_GAIN_16X Value
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X ((uint8_t)0x0UL) |
PGA_GAIN_GAIN_1X Value
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X ((uint8_t)0x1UL) |
PGA_GAIN_GAIN_2X Value
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X ((uint8_t)0x5UL) |
PGA_GAIN_GAIN_32X Value
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X ((uint8_t)0x2UL) |
PGA_GAIN_GAIN_4X Value
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X ((uint8_t)0x6UL) |
PGA_GAIN_GAIN_64X Value
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X ((uint8_t)0x3UL) |
PGA_GAIN_GAIN_8X Value
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH ((uint8_t)0x0UL) |
PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH Value
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH ((uint8_t)0x1UL) |
PGA_SIG_PATH_BYPASS_PATH Value
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH ((uint8_t)0x2UL) |
PGA_SIG_PATH_PGA_PATH Value
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED ((uint8_t)0x3UL) |
PGA_SIG_PATH_RESERVED Value