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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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Peripheral Clock Disable.
#define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) |
PCLKDIS1_AES Mask
#define MXC_F_GCR_PCLKDIS1_AES_POS 15 |
PCLKDIS1_AES Position
#define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) |
PCLKDIS1_CRC Mask
#define MXC_F_GCR_PCLKDIS1_CRC_POS 14 |
PCLKDIS1_CRC Position
#define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) |
PCLKDIS1_I2C2 Mask
#define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 |
PCLKDIS1_I2C2 Position
#define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) |
PCLKDIS1_I2S Mask
#define MXC_F_GCR_PCLKDIS1_I2S_POS 23 |
PCLKDIS1_I2S Position
#define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) |
PCLKDIS1_ICC0 Mask
#define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 |
PCLKDIS1_ICC0 Position
#define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) |
PCLKDIS1_TRNG Mask
#define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 |
PCLKDIS1_TRNG Position
#define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) |
PCLKDIS1_UART2 Mask
#define MXC_F_GCR_PCLKDIS1_UART2_POS 1 |
PCLKDIS1_UART2 Position
#define MXC_F_GCR_PCLKDIS1_WWDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS)) |
PCLKDIS1_WWDT0 Mask
#define MXC_F_GCR_PCLKDIS1_WWDT0_POS 4 |
PCLKDIS1_WWDT0 Position
#define MXC_F_GCR_PCLKDIS1_WWDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS)) |
PCLKDIS1_WWDT1 Mask
#define MXC_F_GCR_PCLKDIS1_WWDT1_POS 5 |
PCLKDIS1_WWDT1 Position