MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
AFE_ADC_ZERO_PGA

Macros

#define MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS   0
 
#define MXC_F_AFE_ADC_ZERO_PGA_GAIN   ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS))
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X   ((uint8_t)0x0UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X   ((uint8_t)0x1UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X   ((uint8_t)0x2UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X   ((uint8_t)0x3UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X   ((uint8_t)0x4UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X   ((uint8_t)0x5UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X   ((uint8_t)0x6UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X   ((uint8_t)0x7UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)
 
#define MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS   4
 
#define MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH   ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS))
 
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH   ((uint8_t)0x0UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH   ((uint8_t)0x1UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH   ((uint8_t)0x2UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)
 
#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED   ((uint8_t)0x3UL)
 
#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)
 

Detailed Description

Signal path control of input buffers and PGA.

Macro Definition Documentation

◆ MXC_F_AFE_ADC_ZERO_PGA_GAIN

#define MXC_F_AFE_ADC_ZERO_PGA_GAIN   ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS))

PGA_GAIN Mask

◆ MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS

#define MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS   0

PGA_GAIN Position

◆ MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH

#define MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH   ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS))

PGA_SIG_PATH Mask

◆ MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS

#define MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS   4

PGA_SIG_PATH Position

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_128X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_16X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_1X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_2X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_32X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_4X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_64X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X

#define MXC_S_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X   (MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X << MXC_F_AFE_ADC_ZERO_PGA_GAIN_POS)

PGA_GAIN_GAIN_8X Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH

#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)

PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH

#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)

PGA_SIG_PATH_BYPASS_PATH Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH

#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)

PGA_SIG_PATH_PGA_PATH Setting

◆ MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED

#define MXC_S_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED   (MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED << MXC_F_AFE_ADC_ZERO_PGA_SIG_PATH_POS)

PGA_SIG_PATH_RESERVED Setting

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_128X   ((uint8_t)0x7UL)

PGA_GAIN_GAIN_128X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_16X   ((uint8_t)0x4UL)

PGA_GAIN_GAIN_16X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_1X   ((uint8_t)0x0UL)

PGA_GAIN_GAIN_1X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_2X   ((uint8_t)0x1UL)

PGA_GAIN_GAIN_2X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_32X   ((uint8_t)0x5UL)

PGA_GAIN_GAIN_32X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_4X   ((uint8_t)0x2UL)

PGA_GAIN_GAIN_4X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_64X   ((uint8_t)0x6UL)

PGA_GAIN_GAIN_64X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X

#define MXC_V_AFE_ADC_ZERO_PGA_GAIN_GAIN_8X   ((uint8_t)0x3UL)

PGA_GAIN_GAIN_8X Value

◆ MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH

#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH   ((uint8_t)0x0UL)

PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH Value

◆ MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH

#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_BYPASS_PATH   ((uint8_t)0x1UL)

PGA_SIG_PATH_BYPASS_PATH Value

◆ MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH

#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_PGA_PATH   ((uint8_t)0x2UL)

PGA_SIG_PATH_PGA_PATH Value

◆ MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED

#define MXC_V_AFE_ADC_ZERO_PGA_SIG_PATH_RESERVED   ((uint8_t)0x3UL)

PGA_SIG_PATH_RESERVED Value