MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
gcr_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the "Software"),
11  * to deal in the Software without restriction, including without limitation
12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13  * and/or sell copies of the Software, and to permit persons to whom the
14  * Software is furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included
17  * in all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
23  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25  * OTHER DEALINGS IN THE SOFTWARE.
26  *
27  * Except as contained in this notice, the name of Maxim Integrated
28  * Products, Inc. shall not be used except as stated in the Maxim Integrated
29  * Products, Inc. Branding Policy.
30  *
31  * The mere transfer of this software does not imply any licenses
32  * of trade secrets, proprietary technology, copyrights, patents,
33  * trademarks, maskwork rights, or any other form of intellectual
34  * property whatsoever. Maxim Integrated Products, Inc. retains all
35  * ownership rights.
36  *
37  *
38  *************************************************************************** */
39 
40 #ifndef _GCR_REGS_H_
41 #define _GCR_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t sysctrl;
90  __IO uint32_t rst0;
91  __IO uint32_t clkctrl;
92  __IO uint32_t pm;
93  __R uint32_t rsv_0x10_0x17[2];
94  __IO uint32_t pclkdiv;
95  __R uint32_t rsv_0x1c_0x23[2];
96  __IO uint32_t pclkdis0;
97  __IO uint32_t memctrl;
98  __IO uint32_t memz;
99  __R uint32_t rsv_0x30_0x3f[4];
100  __IO uint32_t sysst;
101  __IO uint32_t rst1;
102  __IO uint32_t pclkdis1;
103  __IO uint32_t eventen;
104  __I uint32_t revision;
105  __IO uint32_t sysie;
106  __R uint32_t rsv_0x58_0x63[3];
107  __IO uint32_t eccerr;
108  __IO uint32_t eccced;
109  __IO uint32_t eccie;
110  __IO uint32_t eccaddr;
112 
113 /* Register offsets for module GCR */
120  #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL)
121  #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL)
122  #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL)
123  #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL)
124  #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL)
125  #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL)
126  #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL)
127  #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL)
128  #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL)
129  #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL)
130  #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL)
131  #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL)
132  #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL)
133  #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL)
134  #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL)
135  #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL)
136  #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL)
137  #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL)
146  #define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1
147  #define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS))
148  #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL)
149  #define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS)
150  #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL)
151  #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS)
153  #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5
154  #define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS))
156  #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6
157  #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS))
159  #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12
160  #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS))
162  #define MXC_F_GCR_SYSCTRL_CCHK_POS 13
163  #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS))
165  #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14
166  #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS))
168  #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15
169  #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS))
179  #define MXC_F_GCR_RST0_DMA_POS 0
180  #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS))
182  #define MXC_F_GCR_RST0_WDT0_POS 1
183  #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS))
185  #define MXC_F_GCR_RST0_GPIO0_POS 2
186  #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS))
188  #define MXC_F_GCR_RST0_GPIO1_POS 3
189  #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS))
191  #define MXC_F_GCR_RST0_TMR0_POS 5
192  #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS))
194  #define MXC_F_GCR_RST0_TMR1_POS 6
195  #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS))
197  #define MXC_F_GCR_RST0_TMR2_POS 7
198  #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS))
200  #define MXC_F_GCR_RST0_TMR3_POS 8
201  #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS))
203  #define MXC_F_GCR_RST0_UART0_POS 11
204  #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS))
206  #define MXC_F_GCR_RST0_UART1_POS 12
207  #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS))
209  #define MXC_F_GCR_RST0_SPI0_POS 13
210  #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS))
212  #define MXC_F_GCR_RST0_SPI1_POS 14
213  #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS))
215  #define MXC_F_GCR_RST0_SPI2_POS 15
216  #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS))
218  #define MXC_F_GCR_RST0_I2C0_POS 16
219  #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS))
221  #define MXC_F_GCR_RST0_RTC_POS 17
222  #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS))
224  #define MXC_F_GCR_RST0_TRNG_POS 24
225  #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS))
227  #define MXC_F_GCR_RST0_UART2_POS 28
228  #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS))
230  #define MXC_F_GCR_RST0_SOFT_POS 29
231  #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS))
233  #define MXC_F_GCR_RST0_PERIPH_POS 30
234  #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS))
236  #define MXC_F_GCR_RST0_SYS_POS 31
237  #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS))
247  #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6
248  #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS))
249  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL)
250  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
251  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL)
252  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
253  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL)
254  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
255  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL)
256  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
257  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL)
258  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
259  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL)
260  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
261  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL)
262  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
263  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL)
264  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
266  #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9
267  #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS))
268  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL)
269  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
270  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL)
271  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
272  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL)
273  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
274  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL)
275  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
276  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL)
277  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
278  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL)
279  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
281  #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13
282  #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS))
284  #define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14
285  #define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS))
286  #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL)
287  #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)
288  #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL)
289  #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)
290  #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL)
291  #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)
292  #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL)
293  #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)
295  #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16
296  #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS))
298  #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17
299  #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS))
301  #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19
302  #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS))
304  #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20
305  #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS))
307  #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21
308  #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS))
310  #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24
311  #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS))
313  #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25
314  #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS))
316  #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27
317  #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS))
319  #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28
320  #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS))
322  #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29
323  #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS))
325  #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS 31
326  #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS))
336  #define MXC_F_GCR_PM_MODE_POS 0
337  #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS))
338  #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL)
339  #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS)
340  #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL)
341  #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS)
342  #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL)
343  #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS)
345  #define MXC_F_GCR_PM_GPIO_WE_POS 4
346  #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS))
348  #define MXC_F_GCR_PM_RTC_WE_POS 5
349  #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS))
351  #define MXC_F_GCR_PM_LPTMR0_WE_POS 6
352  #define MXC_F_GCR_PM_LPTMR0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS))
354  #define MXC_F_GCR_PM_LPTMR1_WE_POS 7
355  #define MXC_F_GCR_PM_LPTMR1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS))
357  #define MXC_F_GCR_PM_LPUART0_WE_POS 8
358  #define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS))
360  #define MXC_F_GCR_PM_ERFO_PD_POS 14
361  #define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS))
363  #define MXC_F_GCR_PM_IPO_PD_POS 16
364  #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS))
366  #define MXC_F_GCR_PM_IBRO_PD_POS 17
367  #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS))
369  #define MXC_F_GCR_PM_ERFO_BP_POS 20
370  #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS))
380  #define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 0
381  #define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS))
382  #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 ((uint32_t)0x0UL)
383  #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)
384  #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 ((uint32_t)0x1UL)
385  #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)
386  #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 ((uint32_t)0x2UL)
387  #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)
388  #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 ((uint32_t)0x3UL)
389  #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)
391  #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS 14
392  #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS))
394  #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS 16
395  #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS))
405  #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0
406  #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS))
408  #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1
409  #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS))
411  #define MXC_F_GCR_PCLKDIS0_DMA_POS 5
412  #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS))
414  #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6
415  #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS))
417  #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7
418  #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS))
420  #define MXC_F_GCR_PCLKDIS0_SPI2_POS 8
421  #define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS))
423  #define MXC_F_GCR_PCLKDIS0_UART0_POS 9
424  #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS))
426  #define MXC_F_GCR_PCLKDIS0_UART1_POS 10
427  #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS))
429  #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13
430  #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS))
432  #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15
433  #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS))
435  #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16
436  #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS))
438  #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17
439  #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS))
441  #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18
442  #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS))
444  #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28
445  #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS))
455  #define MXC_F_GCR_MEMCTRL_FWS_POS 0
456  #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS))
458  #define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4
459  #define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS))
461  #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8
462  #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS))
464  #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9
465  #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS))
467  #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10
468  #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS))
470  #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11
471  #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS))
473  #define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12
474  #define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS))
476  #define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13
477  #define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS))
487  #define MXC_F_GCR_MEMZ_RAM_POS 0
488  #define MXC_F_GCR_MEMZ_RAM ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM_POS))
490  #define MXC_F_GCR_MEMZ_RAMCB_POS 1
491  #define MXC_F_GCR_MEMZ_RAMCB ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS))
493  #define MXC_F_GCR_MEMZ_ICC0_POS 2
494  #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS))
504  #define MXC_F_GCR_SYSST_ICELOCK_POS 0
505  #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS))
515  #define MXC_F_GCR_RST1_I2C1_POS 0
516  #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))
518  #define MXC_F_GCR_RST1_WDT1_POS 8
519  #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS))
521  #define MXC_F_GCR_RST1_CRC_POS 9
522  #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS))
524  #define MXC_F_GCR_RST1_AES_POS 10
525  #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS))
527  #define MXC_F_GCR_RST1_AC_POS 14
528  #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS))
530  #define MXC_F_GCR_RST1_I2C2_POS 17
531  #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))
533  #define MXC_F_GCR_RST1_I2S_POS 23
534  #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))
544  #define MXC_F_GCR_PCLKDIS1_UART2_POS 1
545  #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS))
547  #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2
548  #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS))
550  #define MXC_F_GCR_PCLKDIS1_WWDT0_POS 4
551  #define MXC_F_GCR_PCLKDIS1_WWDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS))
553  #define MXC_F_GCR_PCLKDIS1_WWDT1_POS 5
554  #define MXC_F_GCR_PCLKDIS1_WWDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS))
556  #define MXC_F_GCR_PCLKDIS1_ICC0_POS 11
557  #define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS))
559  #define MXC_F_GCR_PCLKDIS1_CRC_POS 14
560  #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS))
562  #define MXC_F_GCR_PCLKDIS1_AES_POS 15
563  #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS))
565  #define MXC_F_GCR_PCLKDIS1_I2C2_POS 21
566  #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS))
568  #define MXC_F_GCR_PCLKDIS1_I2S_POS 23
569  #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS))
579  #define MXC_F_GCR_EVENTEN_DMA_POS 0
580  #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS))
582  #define MXC_F_GCR_EVENTEN_RX_POS 1
583  #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS))
585  #define MXC_F_GCR_EVENTEN_TX_POS 2
586  #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS))
596  #define MXC_F_GCR_REVISION_REVISION_POS 0
597  #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS))
607  #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0
608  #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS))
618  #define MXC_F_GCR_ECCERR_RAM_POS 0
619  #define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS))
621  #define MXC_F_GCR_ECCERR_ICC0_POS 1
622  #define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS))
624  #define MXC_F_GCR_ECCERR_FLASH_POS 2
625  #define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS))
635  #define MXC_F_GCR_ECCCED_RAM_POS 0
636  #define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS))
638  #define MXC_F_GCR_ECCCED_ICC0_POS 1
639  #define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS))
641  #define MXC_F_GCR_ECCCED_FLASH_POS 2
642  #define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS))
652  #define MXC_F_GCR_ECCIE_RAM_POS 0
653  #define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS))
655  #define MXC_F_GCR_ECCIE_ICC0_POS 1
656  #define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS))
658  #define MXC_F_GCR_ECCIE_FLASH_POS 2
659  #define MXC_F_GCR_ECCIE_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH_POS))
669  #define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0
670  #define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS))
672  #define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14
673  #define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS))
675  #define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15
676  #define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS))
678  #define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16
679  #define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS))
681  #define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30
682  #define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS))
684  #define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31
685  #define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS))
689 #ifdef __cplusplus
690 }
691 #endif
692 
693 #endif /* _GCR_REGS_H_ */
mxc_gcr_regs_t::eccced
__IO uint32_t eccced
Definition: gcr_regs.h:108
mxc_gcr_regs_t::sysie
__IO uint32_t sysie
Definition: gcr_regs.h:105
mxc_gcr_regs_t::rst1
__IO uint32_t rst1
Definition: gcr_regs.h:101
mxc_gcr_regs_t::pclkdiv
__IO uint32_t pclkdiv
Definition: gcr_regs.h:94
mxc_gcr_regs_t::sysst
__IO uint32_t sysst
Definition: gcr_regs.h:100
mxc_gcr_regs_t::revision
__I uint32_t revision
Definition: gcr_regs.h:104
mxc_gcr_regs_t::sysctrl
__IO uint32_t sysctrl
Definition: gcr_regs.h:89
mxc_gcr_regs_t::memctrl
__IO uint32_t memctrl
Definition: gcr_regs.h:97
mxc_gcr_regs_t::clkctrl
__IO uint32_t clkctrl
Definition: gcr_regs.h:91
mxc_gcr_regs_t::eccaddr
__IO uint32_t eccaddr
Definition: gcr_regs.h:110
mxc_gcr_regs_t::eccerr
__IO uint32_t eccerr
Definition: gcr_regs.h:107
mxc_gcr_regs_t::pclkdis1
__IO uint32_t pclkdis1
Definition: gcr_regs.h:102
mxc_gcr_regs_t::eventen
__IO uint32_t eventen
Definition: gcr_regs.h:103
mxc_gcr_regs_t::pm
__IO uint32_t pm
Definition: gcr_regs.h:92
mxc_gcr_regs_t::eccie
__IO uint32_t eccie
Definition: gcr_regs.h:109
mxc_gcr_regs_t
Definition: gcr_regs.h:88
mxc_gcr_regs_t::rst0
__IO uint32_t rst0
Definition: gcr_regs.h:90
mxc_gcr_regs_t::memz
__IO uint32_t memz
Definition: gcr_regs.h:98
mxc_gcr_regs_t::pclkdis0
__IO uint32_t pclkdis0
Definition: gcr_regs.h:96