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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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System Calibration Selection.
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS)) |
SYS_CTRL_ANA_SRC_SEL Mask
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS 0 |
SYS_CTRL_ANA_SRC_SEL Position
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC5 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC5_POS)) |
SYS_CTRL_CRC5 Mask
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC5_POS 2 |
SYS_CTRL_CRC5 Position
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC_INV ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC_INV_POS)) |
SYS_CTRL_CRC_INV Mask
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC_INV_POS 7 |
SYS_CTRL_CRC_INV Position
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_HART_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_HART_EN_POS)) |
SYS_CTRL_HART_EN Mask
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_HART_EN_POS 4 |
SYS_CTRL_HART_EN Position
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_POR_FLAG ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_POR_FLAG_POS)) |
SYS_CTRL_POR_FLAG Mask
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_POR_FLAG_POS 6 |
SYS_CTRL_POR_FLAG Position
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_SPI_ABORT_DIS ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_SPI_ABORT_DIS_POS)) |
SYS_CTRL_SPI_ABORT_DIS Mask
#define MXC_F_AFE_ADC_ONE_SYS_CTRL_SPI_ABORT_DIS_POS 5 |
SYS_CTRL_SPI_ABORT_DIS Position
#define MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC0_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC0_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
SYS_CTRL_ANA_SRC_SEL_ADC0_BANK Setting
#define MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC1_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC1_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
SYS_CTRL_ANA_SRC_SEL_ADC1_BANK Setting
#define MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_DAC12_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_DAC12_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
SYS_CTRL_ANA_SRC_SEL_DAC12_BANK Setting
#define MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_HART_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_HART_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
SYS_CTRL_ANA_SRC_SEL_HART_BANK Setting
#define MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC0_BANK ((uint8_t)0x0UL) |
SYS_CTRL_ANA_SRC_SEL_ADC0_BANK Value
#define MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC1_BANK ((uint8_t)0x1UL) |
SYS_CTRL_ANA_SRC_SEL_ADC1_BANK Value
#define MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_DAC12_BANK ((uint8_t)0x2UL) |
SYS_CTRL_ANA_SRC_SEL_DAC12_BANK Value
#define MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_HART_BANK ((uint8_t)0x3UL) |
SYS_CTRL_ANA_SRC_SEL_HART_BANK Value