MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
dma.h
1 
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38 
39 #ifndef _DMA_H_
40 #define _DMA_H_
41 
42 /* **** Includes **** */
43 #include <stdbool.h>
44 #include "mxc_device.h"
45 #include "dma_regs.h"
46 
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50 
57 /* **** Definitions **** */
58 
63 typedef enum {
69 
71 typedef enum {
99 
101 typedef enum {
107 
109 typedef enum {
119 
121 typedef enum {
122  /* Using the '_V_' define instead of the '_S_' since these same values will be used to
123  specify the DSTWD also. The API functions will shift the value the correct amount
124  prior to writing the cfg register. */
129 
135 typedef struct {
136  int ch;
140  int srcinc_en;
141  int dstinc_en;
143 
148 typedef struct {
149  int ch;
150  void* source;
151  void* dest;
152  int len;
154 
161 typedef struct {
162  int ch;
164  unsigned int reqwait_en;
167  unsigned int burst_size;
169 
175 typedef void (*mxc_dma_complete_cb_t) (void* dest);
176 
189 
190 /* **** Function Prototypes **** */
191 /*************************/
192 /* Low Level Functions */
193 /*************************/
199 int MXC_DMA_Init (void);
200 
210 int MXC_DMA_AcquireChannel (void);
211 
220 int MXC_DMA_ReleaseChannel (int ch);
221 
232 
241 
252 
260 int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t* srcdst);
261 
271 int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
272 
280 int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t* srcdstReload);
281 
304 int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
305 
316 int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
317 
326 int MXC_DMA_ChannelEnableInt (int ch, int flags);
327 
334 int MXC_DMA_ChannelDisableInt (int ch, int flags);
335 
341 int MXC_DMA_ChannelGetFlags (int ch);
342 
349 int MXC_DMA_ChannelClearFlags (int ch, int flags);
350 
358 int MXC_DMA_EnableInt (int ch);
359 
365 int MXC_DMA_DisableInt (int ch);
366 
373 int MXC_DMA_Start (int ch);
374 
380 int MXC_DMA_Stop (int ch);
381 
390 
396 void MXC_DMA_Handler();
397 
398 /*************************/
399 /* High Level Functions */
400 /*************************/
401 
414 int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
415 
433 #ifdef __cplusplus
434 }
435 #endif
436 
437 #endif /* _DMA_H_ */
mxc_dma_config_t::ch
int ch
The channel to load the configuration data into.
Definition: dma.h:136
mxc_dma_complete_cb_t
void(* mxc_dma_complete_cb_t)(void *dest)
The callback called on completion of a DMA_MemCpy() transfer.
Definition: dma.h:175
MXC_S_DMA_CTRL_REQUEST_UART0RX
#define MXC_S_DMA_CTRL_REQUEST_UART0RX
Definition: dma_regs.h:228
MXC_DMA_Stop
int MXC_DMA_Stop(int ch)
Stop DMA transfer, irrespective of status (complete or in-progress)
mxc_dma_adv_config_t
The advanced configuration options, these are optional but could be needed in cases where multiple DM...
Definition: dma.h:161
MXC_S_DMA_CTRL_TO_PER_TO64
#define MXC_S_DMA_CTRL_TO_PER_TO64
Definition: dma_regs.h:290
MXC_S_DMA_CTRL_REQUEST_I2C2RX
#define MXC_S_DMA_CTRL_REQUEST_I2C2RX
Definition: dma_regs.h:236
MXC_DMA_MemCpy
int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback)
Performs a memcpy, using DMA, optionally asynchronous.
mxc_dma_srcdst_t::source
void * source
Pointer to the source address, if applicable.
Definition: dma.h:150
MXC_S_DMA_CTRL_TO_PER_TO256
#define MXC_S_DMA_CTRL_TO_PER_TO256
Definition: dma_regs.h:294
MXC_S_DMA_CTRL_REQUEST_I2C0RX
#define MXC_S_DMA_CTRL_REQUEST_I2C0RX
Definition: dma_regs.h:232
mxc_dma_adv_config_t::burst_size
unsigned int burst_size
Number of bytes moved in a single burst.
Definition: dma.h:167
MXC_DMA_Init
int MXC_DMA_Init(void)
Initialize DMA resources.
mxc_dma_prescale_t
mxc_dma_prescale_t
Enumeration for the DMA prescaler.
Definition: dma.h:101
MXC_DMA_SetCallback
int MXC_DMA_SetCallback(int ch, void(*callback)(int, int))
Set channel interrupt callback.
MXC_DMA_SetChannelInterruptEn
int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
Set channel interrupt.
MXC_DMA_ChannelEnableInt
int MXC_DMA_ChannelEnableInt(int ch, int flags)
Enable channel interrupt.
MXC_DMA_REQUEST_CRCTX
@ MXC_DMA_REQUEST_CRCTX
CRC Transmit DMA Request Selection.
Definition: dma.h:93
MXC_DMA_ConfigChannel
int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
Configure the DMA channel.
MXC_DMA_REQUEST_AESTX
@ MXC_DMA_REQUEST_AESTX
AES Transmit DMA Request Selection.
Definition: dma.h:95
MXC_DMA_REQUEST_UART1TX
@ MXC_DMA_REQUEST_UART1TX
UART1 Transmit DMA Request Selection.
Definition: dma.h:89
mxc_dma_srcdst_t::len
int len
Number of bytes to transfer.
Definition: dma.h:152
MXC_V_DMA_CTRL_PRI_MEDHIGH
#define MXC_V_DMA_CTRL_PRI_MEDHIGH
Definition: dma_regs.h:210
MXC_DMA_DisableInt
int MXC_DMA_DisableInt(int ch)
Disable channel interrupt.
mxc_dma_adv_config_t::reqwait_en
unsigned int reqwait_en
Delay the timeout timer start until after first transfer.
Definition: dma.h:164
MXC_DMA_REQUEST_UART0RX
@ MXC_DMA_REQUEST_UART0RX
UART0 Receive DMA Request Selection.
Definition: dma.h:76
MXC_S_DMA_CTRL_REQUEST_UART0TX
#define MXC_S_DMA_CTRL_REQUEST_UART0TX
Definition: dma_regs.h:254
MXC_DMA_ChannelClearFlags
int MXC_DMA_ChannelClearFlags(int ch, int flags)
Clear channel interrupt flags.
MXC_DMA_TIMEOUT_32_CLK
@ MXC_DMA_TIMEOUT_32_CLK
DMA timeout of 32 clocks.
Definition: dma.h:113
mxc_dma_adv_config_t::tosel
mxc_dma_timeout_t tosel
Number of prescaled clocks seen by the channel before a timeout.
Definition: dma.h:165
MXC_DMA_TIMEOUT_4_CLK
@ MXC_DMA_TIMEOUT_4_CLK
DMA timeout of 4 clocks.
Definition: dma.h:110
MXC_DMA_ChannelGetFlags
int MXC_DMA_ChannelGetFlags(int ch)
Read channel interrupt flags.
MXC_DMA_TIMEOUT_8_CLK
@ MXC_DMA_TIMEOUT_8_CLK
DMA timeout of 8 clocks.
Definition: dma.h:111
MXC_DMA_REQUEST_SPI0TX
@ MXC_DMA_REQUEST_SPI0TX
SPI0 Transmit DMA Request Selection.
Definition: dma.h:85
MXC_S_DMA_CTRL_REQUEST_I2C2TX
#define MXC_S_DMA_CTRL_REQUEST_I2C2TX
Definition: dma_regs.h:262
MXC_S_DMA_CTRL_REQUEST_UART2TX
#define MXC_S_DMA_CTRL_REQUEST_UART2TX
Definition: dma_regs.h:266
MXC_DMA_ReleaseChannel
int MXC_DMA_ReleaseChannel(int ch)
Release DMA channel.
MXC_DMA_WIDTH_HALFWORD
@ MXC_DMA_WIDTH_HALFWORD
DMA transfer in 16-bit half-words.
Definition: dma.h:126
MXC_DMA_Handler
void MXC_DMA_Handler()
Interrupt handler function.
MXC_DMA_WIDTH_WORD
@ MXC_DMA_WIDTH_WORD
DMA transfer in 32-bit words.
Definition: dma.h:127
MXC_DMA_SetSrcDst
int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst)
Set channel source, destination, and count for the transfer.
MXC_DMA_REQUEST_I2C0RX
@ MXC_DMA_REQUEST_I2C0RX
I2C0 Receive DMA Request Selection.
Definition: dma.h:78
MXC_S_DMA_CTRL_REQUEST_UART3TX
#define MXC_S_DMA_CTRL_REQUEST_UART3TX
Definition: dma_regs.h:272
MXC_S_DMA_CTRL_REQUEST_MEMTOMEM
#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM
Definition: dma_regs.h:220
MXC_DMA_Start
int MXC_DMA_Start(int ch)
Start transfer.
MXC_S_DMA_CTRL_REQUEST_UART2RX
#define MXC_S_DMA_CTRL_REQUEST_UART2RX
Definition: dma_regs.h:238
MXC_DMA_REQUEST_SPI1TX
@ MXC_DMA_REQUEST_SPI1TX
SPI1 Transmit DMA Request Selection.
Definition: dma.h:86
MXC_S_DMA_CTRL_REQUEST_AESTX
#define MXC_S_DMA_CTRL_REQUEST_AESTX
Definition: dma_regs.h:270
mxc_dma_config_t::reqsel
mxc_dma_reqsel_t reqsel
The request select line to be used (mem2mem, peripheral)
Definition: dma.h:137
MXC_DMA_PRIO_HIGH
@ MXC_DMA_PRIO_HIGH
High Priority *‍/.
Definition: dma.h:64
MXC_V_DMA_CTRL_PRI_LOW
#define MXC_V_DMA_CTRL_PRI_LOW
Definition: dma_regs.h:214
MXC_DMA_REQUEST_I2C2TX
@ MXC_DMA_REQUEST_I2C2TX
I2C2 Transmit DMA Request Selection
Definition: dma.h:92
MXC_DMA_REQUEST_UART2TX
@ MXC_DMA_REQUEST_UART2TX
UART2 Transmit DMA Request Selection.
Definition: dma.h:94
mxc_dma_config_t::srcwd
mxc_dma_width_t srcwd
The source width (could be dependent on FIFO width)
Definition: dma.h:138
MXC_DMA_REQUEST_I2C2RX
@ MXC_DMA_REQUEST_I2C2RX
I2C2 Receive DMA Request Selection.
Definition: dma.h:80
MXC_DMA_TIMEOUT_64_CLK
@ MXC_DMA_TIMEOUT_64_CLK
DMA timeout of 64 clocks.
Definition: dma.h:114
MXC_S_DMA_CTRL_REQUEST_SPI1TX
#define MXC_S_DMA_CTRL_REQUEST_SPI1TX
Definition: dma_regs.h:250
MXC_DMA_WIDTH_BYTE
@ MXC_DMA_WIDTH_BYTE
DMA transfer in bytes.
Definition: dma.h:125
MXC_DMA_PRIO_MEDLOW
@ MXC_DMA_PRIO_MEDLOW
Medium Low Priority *‍/.
Definition: dma.h:66
MXC_V_DMA_CTRL_PRI_HIGH
#define MXC_V_DMA_CTRL_PRI_HIGH
Definition: dma_regs.h:208
MXC_S_DMA_CTRL_REQUEST_CRCTX
#define MXC_S_DMA_CTRL_REQUEST_CRCTX
Definition: dma_regs.h:264
MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K
Definition: dma_regs.h:305
MXC_DMA_PRESCALE_DISABLE
@ MXC_DMA_PRESCALE_DISABLE
Prescaler disabled.
Definition: dma.h:102
MXC_V_DMA_CTRL_SRCWD_WORD
#define MXC_V_DMA_CTRL_SRCWD_WORD
Definition: dma_regs.h:315
MXC_V_DMA_CTRL_SRCWD_HALFWORD
#define MXC_V_DMA_CTRL_SRCWD_HALFWORD
Definition: dma_regs.h:313
MXC_DMA_PRIO_LOW
@ MXC_DMA_PRIO_LOW
Low Priority *‍/.
Definition: dma.h:67
MXC_DMA_REQUEST_AESRX
@ MXC_DMA_REQUEST_AESRX
AES Receive DMA Request Selection.
Definition: dma.h:82
MXC_DMA_PRESCALE_DIV64K
@ MXC_DMA_PRESCALE_DIV64K
Divide by 65,536.
Definition: dma.h:104
MXC_S_DMA_CTRL_REQUEST_UART1RX
#define MXC_S_DMA_CTRL_REQUEST_UART1RX
Definition: dma_regs.h:230
mxc_dma_config_t::dstwd
mxc_dma_width_t dstwd
The destination width (could be dependent on FIFO width)
Definition: dma.h:139
MXC_S_DMA_CTRL_REQUEST_I2STX
#define MXC_S_DMA_CTRL_REQUEST_I2STX
Definition: dma_regs.h:274
MXC_DMA_REQUEST_I2STX
@ MXC_DMA_REQUEST_I2STX
I2S Transmit DMA Request Selection
Definition: dma.h:97
MXC_DMA_GetCHRegs
mxc_dma_ch_regs_t * MXC_DMA_GetCHRegs(int ch)
Get a pointer to the DMA channel registers.
MXC_DMA_TIMEOUT_16_CLK
@ MXC_DMA_TIMEOUT_16_CLK
DMA timeout of 16 clocks.
Definition: dma.h:112
MXC_S_DMA_CTRL_TO_PER_TO512
#define MXC_S_DMA_CTRL_TO_PER_TO512
Definition: dma_regs.h:296
MXC_DMA_ChannelDisableInt
int MXC_DMA_ChannelDisableInt(int ch, int flags)
Disable channel interrupt.
MXC_S_DMA_CTRL_TO_PER_TO8
#define MXC_S_DMA_CTRL_TO_PER_TO8
Definition: dma_regs.h:284
MXC_S_DMA_CTRL_REQUEST_AESRX
#define MXC_S_DMA_CTRL_REQUEST_AESRX
Definition: dma_regs.h:242
MXC_S_DMA_CTRL_REQUEST_I2SRX
#define MXC_S_DMA_CTRL_REQUEST_I2SRX
Definition: dma_regs.h:246
MXC_DMA_REQUEST_SPI0RX
@ MXC_DMA_REQUEST_SPI0RX
SPI0 Receive DMA Request Selection.
Definition: dma.h:73
MXC_DMA_PRESCALE_DIV16M
@ MXC_DMA_PRESCALE_DIV16M
Divide by 16,777,216.
Definition: dma.h:105
MXC_S_DMA_CTRL_REQUEST_SPI0TX
#define MXC_S_DMA_CTRL_REQUEST_SPI0TX
Definition: dma_regs.h:248
mxc_dma_ch_regs_t
Definition: dma_regs.h:88
MXC_S_DMA_CTRL_REQUEST_I2C1RX
#define MXC_S_DMA_CTRL_REQUEST_I2C1RX
Definition: dma_regs.h:234
MXC_DMA_AdvConfigChannel
int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
Configure the DMA channel with more advanced parameters.
mxc_dma_timeout_t
mxc_dma_timeout_t
Enumeration for the DMA timeout value.
Definition: dma.h:109
mxc_dma_width_t
mxc_dma_width_t
DMA transfer data width.
Definition: dma.h:121
MXC_S_DMA_CTRL_REQUEST_SPI0RX
#define MXC_S_DMA_CTRL_REQUEST_SPI0RX
Definition: dma_regs.h:222
MXC_DMA_SetSrcReload
int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload)
Set channel reload source, destination, and count for the transfer.
MXC_S_DMA_CTRL_REQUEST_SPI1RX
#define MXC_S_DMA_CTRL_REQUEST_SPI1RX
Definition: dma_regs.h:224
MXC_DMA_EnableInt
int MXC_DMA_EnableInt(int ch)
Enable channel interrupt.
MXC_DMA_REQUEST_UART3TX
@ MXC_DMA_REQUEST_UART3TX
UART3 Transmit DMA Request Selection
Definition: dma.h:96
MXC_V_DMA_CTRL_SRCWD_BYTE
#define MXC_V_DMA_CTRL_SRCWD_BYTE
Definition: dma_regs.h:311
MXC_S_DMA_CTRL_TO_PER_TO128
#define MXC_S_DMA_CTRL_TO_PER_TO128
Definition: dma_regs.h:292
MXC_S_DMA_CTRL_TO_PER_TO4
#define MXC_S_DMA_CTRL_TO_PER_TO4
Definition: dma_regs.h:282
MXC_DMA_REQUEST_UART3RX
@ MXC_DMA_REQUEST_UART3RX
UART3 Receive DMA Request Selection
Definition: dma.h:83
MXC_DMA_PRIO_MEDHIGH
@ MXC_DMA_PRIO_MEDHIGH
Medium High Priority *‍/.
Definition: dma.h:65
MXC_DMA_REQUEST_I2C1TX
@ MXC_DMA_REQUEST_I2C1TX
I2C1 Transmit DMA Request Selection.
Definition: dma.h:91
mxc_dma_reqsel_t
mxc_dma_reqsel_t
DMA request select.
Definition: dma.h:71
MXC_S_DMA_CTRL_TO_CLKDIV_DIS
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIS
Definition: dma_regs.h:301
MXC_S_DMA_CTRL_TO_CLKDIV_DIV256
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256
Definition: dma_regs.h:303
MXC_DMA_AcquireChannel
int MXC_DMA_AcquireChannel(void)
Request DMA channel.
mxc_dma_adv_config_t::pssel
mxc_dma_prescale_t pssel
Prescaler for the timeout timer.
Definition: dma.h:166
MXC_S_DMA_CTRL_REQUEST_UART3RX
#define MXC_S_DMA_CTRL_REQUEST_UART3RX
Definition: dma_regs.h:244
MXC_DMA_REQUEST_UART1RX
@ MXC_DMA_REQUEST_UART1RX
UART1 Receive DMA Request Selection.
Definition: dma.h:77
MXC_DMA_GetSrcDst
int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst)
Get channel source, destination, and count for transfer.
mxc_dma_priority_t
mxc_dma_priority_t
Enumeration for the DMA Channel's priority level.
Definition: dma.h:63
MXC_S_DMA_CTRL_TO_PER_TO32
#define MXC_S_DMA_CTRL_TO_PER_TO32
Definition: dma_regs.h:288
mxc_dma_srcdst_t::dest
void * dest
Pointer to the destination address, if applicable.
Definition: dma.h:151
MXC_V_DMA_CTRL_PRI_MEDLOW
#define MXC_V_DMA_CTRL_PRI_MEDLOW
Definition: dma_regs.h:212
mxc_dma_srcdst_t
The information needed to complete a DMA transfer.
Definition: dma.h:148
MXC_DMA_TIMEOUT_512_CLK
@ MXC_DMA_TIMEOUT_512_CLK
DMA timeout of 512 clocks.
Definition: dma.h:117
MXC_S_DMA_CTRL_REQUEST_SPI2RX
#define MXC_S_DMA_CTRL_REQUEST_SPI2RX
Definition: dma_regs.h:226
mxc_dma_config_t::srcinc_en
int srcinc_en
Whether to increment the source address during the transfer.
Definition: dma.h:140
MXC_DMA_GetSrcReload
int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload)
Get channel reload source, destination, and count for transfer.
mxc_dma_config_t
The basic configuration information to set up a DMA channel and prepare it for transfers.
Definition: dma.h:135
MXC_S_DMA_CTRL_REQUEST_SPI2TX
#define MXC_S_DMA_CTRL_REQUEST_SPI2TX
Definition: dma_regs.h:252
MXC_DMA_REQUEST_UART0TX
@ MXC_DMA_REQUEST_UART0TX
UART0 Transmit DMA Request Selection.
Definition: dma.h:88
MXC_DMA_REQUEST_I2C0TX
@ MXC_DMA_REQUEST_I2C0TX
I2C0 Transmit DMA Request Selection.
Definition: dma.h:90
MXC_DMA_REQUEST_SPI2TX
@ MXC_DMA_REQUEST_SPI2TX
SPI2 Transmit DMA Request Selection.
Definition: dma.h:87
mxc_dma_adv_config_t::prio
mxc_dma_priority_t prio
The DMA priority for the channel.
Definition: dma.h:163
MXC_DMA_REQUEST_MEMTOMEM
@ MXC_DMA_REQUEST_MEMTOMEM
Memory to Memory DMA Request Selection.
Definition: dma.h:72
mxc_dma_trans_chain_t
mxc_dma_srcdst_t(* mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest)
The callback called on completion of a transfer,.
Definition: dma.h:188
MXC_S_DMA_CTRL_REQUEST_UART1TX
#define MXC_S_DMA_CTRL_REQUEST_UART1TX
Definition: dma_regs.h:256
mxc_dma_config_t::dstinc_en
int dstinc_en
Whether to increment the source address during the transfer.
Definition: dma.h:141
MXC_DMA_TIMEOUT_256_CLK
@ MXC_DMA_TIMEOUT_256_CLK
DMA timeout of 256 clocks.
Definition: dma.h:116
MXC_DMA_REQUEST_UART2RX
@ MXC_DMA_REQUEST_UART2RX
UART2 Receive DMA Request Selection.
Definition: dma.h:81
MXC_S_DMA_CTRL_REQUEST_I2C0TX
#define MXC_S_DMA_CTRL_REQUEST_I2C0TX
Definition: dma_regs.h:258
MXC_DMA_REQUEST_SPI2RX
@ MXC_DMA_REQUEST_SPI2RX
SPI2 Receive DMA Request Selection.
Definition: dma.h:75
MXC_DMA_REQUEST_SPI1RX
@ MXC_DMA_REQUEST_SPI1RX
SPI1 Receive DMA Request Selection.
Definition: dma.h:74
MXC_S_DMA_CTRL_TO_PER_TO16
#define MXC_S_DMA_CTRL_TO_PER_TO16
Definition: dma_regs.h:286
MXC_S_DMA_CTRL_REQUEST_I2C1TX
#define MXC_S_DMA_CTRL_REQUEST_I2C1TX
Definition: dma_regs.h:260
MXC_DMA_REQUEST_I2C1RX
@ MXC_DMA_REQUEST_I2C1RX
I2C1 Receive DMA Request Selection.
Definition: dma.h:79
MXC_DMA_REQUEST_I2SRX
@ MXC_DMA_REQUEST_I2SRX
I2S Receive DMA Request Selection.
Definition: dma.h:84
MXC_DMA_PRESCALE_DIV256
@ MXC_DMA_PRESCALE_DIV256
Divide by 256.
Definition: dma.h:103
MXC_DMA_TIMEOUT_128_CLK
@ MXC_DMA_TIMEOUT_128_CLK
DMA timeout of 128 clocks.
Definition: dma.h:115
MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M
Definition: dma_regs.h:307
MXC_DMA_DoTransfer
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
Performs a memcpy, using DMA, optionally asynchronous.