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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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Memory Clock Control Register.
#define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) |
MEMCTRL_FWS Mask
#define MXC_F_GCR_MEMCTRL_FWS_POS 0 |
MEMCTRL_FWS Position
#define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) |
MEMCTRL_ICC0LS_EN Mask
#define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12 |
MEMCTRL_ICC0LS_EN Position
#define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) |
MEMCTRL_RAM0LS_EN Mask
#define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8 |
MEMCTRL_RAM0LS_EN Position
#define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) |
MEMCTRL_RAM1LS_EN Mask
#define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9 |
MEMCTRL_RAM1LS_EN Position
#define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) |
MEMCTRL_RAM2LS_EN Mask
#define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10 |
MEMCTRL_RAM2LS_EN Position
#define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) |
MEMCTRL_RAM3LS_EN Mask
#define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11 |
MEMCTRL_RAM3LS_EN Position
#define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) |
MEMCTRL_RAMWS_EN Mask
#define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 |
MEMCTRL_RAMWS_EN Position
#define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) |
MEMCTRL_ROMLS_EN Mask
#define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13 |
MEMCTRL_ROMLS_EN Position