MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
AFE_HART_RX_TX_CTL

Macros

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN_POS   0
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN_POS   1
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL_POS   2
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN_POS   3
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR_POS   4
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR   ((uint32_t)(0xFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT_POS   8
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT   ((uint32_t)(0xFFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT_POS   16
 
#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT   ((uint32_t)(0xFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN_POS   20
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN_POS   21
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS_POS   22
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS_POS))
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN_POS   23
 
#define MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN_POS))
 

Detailed Description

Control HART Transmit and Receive Functions.

Macro Definition Documentation

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL_POS))

RX_TX_CTL_RX_ADC_OFFSET_SEL Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL_POS

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL_POS   2

RX_TX_CTL_RX_ADC_OFFSET_SEL Position

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT   ((uint32_t)(0xFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT_POS))

RX_TX_CTL_RX_ADC_PWR_DLY_CNT Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT_POS

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT_POS   16

RX_TX_CTL_RX_ADC_PWR_DLY_CNT Position

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR   ((uint32_t)(0xFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR_POS))

RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR_POS

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR_POS   4

RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR Position

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN_POS))

RX_TX_CTL_RX_ADC_REF_EN Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN_POS

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN_POS   0

RX_TX_CTL_RX_ADC_REF_EN Position

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN_POS))

RX_TX_CTL_RX_ADC_REFBUF_EN Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN_POS

#define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN_POS   1

RX_TX_CTL_RX_ADC_REFBUF_EN Position

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT

#define MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT   ((uint32_t)(0xFFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT_POS))

RX_TX_CTL_RX_BP_SETTLE_CNT Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT_POS

#define MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT_POS   8

RX_TX_CTL_RX_BP_SETTLE_CNT Position

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN

#define MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN_POS))

RX_TX_CTL_RX_DOUT_UART_EN Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN_POS

#define MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN_POS   3

RX_TX_CTL_RX_DOUT_UART_EN Position

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN

#define MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN_POS))

RX_TX_CTL_TX_4MHZ_CLK_EN Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN_POS

#define MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN_POS   23

RX_TX_CTL_TX_4MHZ_CLK_EN Position

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN

#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN_POS))

RX_TX_CTL_TX_BUF_EN Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN_POS

#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN_POS   20

RX_TX_CTL_TX_BUF_EN Position

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN

#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN_POS))

RX_TX_CTL_TX_BUS_DCL_EN Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN_POS

#define MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN_POS   21

RX_TX_CTL_TX_BUS_DCL_EN Position

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS

#define MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS   ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS_POS))

RX_TX_CTL_TX_WS_DIS_RS Mask

◆ MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS_POS

#define MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS_POS   22

RX_TX_CTL_TX_WS_DIS_RS Position