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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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Device Status, INTB source etc. Enable Register.
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_CAL_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_CAL_RDY_IE_POS)) |
STATUS_IE_CAL_RDY_IE Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_CAL_RDY_IE_POS 2 |
STATUS_IE_CAL_RDY_IE Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_CONV_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_CONV_RDY_IE_POS)) |
STATUS_IE_CONV_RDY_IE Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_CONV_RDY_IE_POS 0 |
STATUS_IE_CONV_RDY_IE Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_DATA_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_DATA_RDY_IE_POS)) |
STATUS_IE_DATA_RDY_IE Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_DATA_RDY_IE_POS 4 |
STATUS_IE_DATA_RDY_IE Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_SEQ_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_SEQ_RDY_IE_POS)) |
STATUS_IE_SEQ_RDY_IE Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_SEQ_RDY_IE_POS 1 |
STATUS_IE_SEQ_RDY_IE Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_SYSGOR_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_SYSGOR_IE_POS)) |
STATUS_IE_SYSGOR_IE Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_SYSGOR_IE_POS 7 |
STATUS_IE_SYSGOR_IE Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_0 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_0_POS)) |
STATUS_IE_TOR_IE_0 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_0_POS 16 |
STATUS_IE_TOR_IE_0 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_1 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_1_POS)) |
STATUS_IE_TOR_IE_1 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_1_POS 17 |
STATUS_IE_TOR_IE_1 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_2 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_2_POS)) |
STATUS_IE_TOR_IE_2 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_2_POS 18 |
STATUS_IE_TOR_IE_2 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_3 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_3_POS)) |
STATUS_IE_TOR_IE_3 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_3_POS 19 |
STATUS_IE_TOR_IE_3 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_4 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_4_POS)) |
STATUS_IE_TOR_IE_4 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_4_POS 20 |
STATUS_IE_TOR_IE_4 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_5 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_5_POS)) |
STATUS_IE_TOR_IE_5 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_5_POS 21 |
STATUS_IE_TOR_IE_5 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_6 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_6_POS)) |
STATUS_IE_TOR_IE_6 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_6_POS 22 |
STATUS_IE_TOR_IE_6 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_7 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_7_POS)) |
STATUS_IE_TOR_IE_7 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TOR_IE_7_POS 23 |
STATUS_IE_TOR_IE_7 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_0 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_0_POS)) |
STATUS_IE_TUR_IE_0 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_0_POS 8 |
STATUS_IE_TUR_IE_0 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_1 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_1_POS)) |
STATUS_IE_TUR_IE_1 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_1_POS 9 |
STATUS_IE_TUR_IE_1 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_2 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_2_POS)) |
STATUS_IE_TUR_IE_2 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_2_POS 10 |
STATUS_IE_TUR_IE_2 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_3 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_3_POS)) |
STATUS_IE_TUR_IE_3 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_3_POS 11 |
STATUS_IE_TUR_IE_3 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_4 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_4_POS)) |
STATUS_IE_TUR_IE_4 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_4_POS 12 |
STATUS_IE_TUR_IE_4 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_5 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_5_POS)) |
STATUS_IE_TUR_IE_5 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_5_POS 13 |
STATUS_IE_TUR_IE_5 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_6 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_6_POS)) |
STATUS_IE_TUR_IE_6 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_6_POS 14 |
STATUS_IE_TUR_IE_6 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_7 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_7_POS)) |
STATUS_IE_TUR_IE_7 Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_TUR_IE_7_POS 15 |
STATUS_IE_TUR_IE_7 Position
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_WAIT_DONE_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_STATUS_IE_WAIT_DONE_IE_POS)) |
STATUS_IE_WAIT_DONE_IE Mask
#define MXC_F_AFE_ADC_ZERO_STATUS_IE_WAIT_DONE_IE_POS 3 |
STATUS_IE_WAIT_DONE_IE Position