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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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Low Power Control Register.
#define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) |
LPCN_BG_DIS Mask
#define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 |
LPCN_BG_DIS Position
#define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) |
LPCN_ERTCO_EN Mask
#define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 |
LPCN_ERTCO_EN Position
#define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) |
LPCN_FASTWK_EN Mask
#define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 |
LPCN_FASTWK_EN Position
#define MXC_F_PWRSEQ_LPCN_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) |
LPCN_INRO_EN Mask
#define MXC_F_PWRSEQ_LPCN_INRO_EN_POS 28 |
LPCN_INRO_EN Position
#define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) |
LPCN_LDO_DIS Mask
#define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 |
LPCN_LDO_DIS Position
#define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) |
LPCN_OVR Mask
#define MXC_F_PWRSEQ_LPCN_OVR_POS 4 |
LPCN_OVR Position
#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) |
LPCN_PORVDDMON_DIS Mask
#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS 25 |
LPCN_PORVDDMON_DIS Position
#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) |
LPCN_RAM0RET_EN Mask
#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS 0 |
LPCN_RAM0RET_EN Position
#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) |
LPCN_RAM1RET_EN Mask
#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS 1 |
LPCN_RAM1RET_EN Position
#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) |
LPCN_RAM2RET_EN Mask
#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS 2 |
LPCN_RAM2RET_EN Position
#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) |
LPCN_RAM3RET_EN Mask
#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS 3 |
LPCN_RAM3RET_EN Position
#define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) |
LPCN_RETREG_EN Mask
#define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 |
LPCN_RETREG_EN Position
#define MXC_F_PWRSEQ_LPCN_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) |
LPCN_STORAGE_EN Mask
#define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS 9 |
LPCN_STORAGE_EN Position
#define MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS)) |
LPCN_TM_LPMODE Mask
#define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30 |
LPCN_TM_LPMODE Position
#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS)) |
LPCN_TM_PWRSEQ Mask
#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31 |
LPCN_TM_PWRSEQ Position
#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) |
LPCN_VCORE_DET_BYPASS Mask
#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS 6 |
LPCN_VCORE_DET_BYPASS Position
#define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) |
LPCN_VCORE_EXT Mask
#define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 |
LPCN_VCORE_EXT Position
#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) |
LPCN_VCOREMON_DIS Mask
#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 |
LPCN_VCOREMON_DIS Position
#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) |
LPCN_VCOREPOR_DIS Mask
#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 |
LPCN_VCOREPOR_DIS Position
#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) |
LPCN_VDDAMON_DIS Mask
#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 |
LPCN_VDDAMON_DIS Position
#define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) |
LPCN_OVR_0_9V Setting
#define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) |
LPCN_OVR_1_0V Setting
#define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) |
LPCN_OVR_1_1V Setting
#define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) |
LPCN_OVR_0_9V Value
#define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) |
LPCN_OVR_1_0V Value
#define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) |
LPCN_OVR_1_1V Value