MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
mxc_sys.h
1 
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38 
39 #ifndef _MXC_MXC_SYS_H_
40 #define _MXC_MXC_SYS_H_
41 
42 #include "mxc_device.h"
43 #include "gcr_regs.h"
44 #include "mcr_regs.h"
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
51 typedef enum {
52  MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS,
53  MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS,
54  MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS,
55  MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS,
56  MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS,
57  MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS,
58  MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS,
59  MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS,
60  MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS,
61  MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS,
62  MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS,
63  MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS,
64  MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS,
65  MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS,
66  MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS,
67  MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS,
68  MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS,
69  MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS,
70  MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS,
71  MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS,
72  /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
73  MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32),
74  MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32),
75  MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32),
76  MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32),
77  MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32),
78  MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32),
79  /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
80  MXC_SYS_RESET_TMR4 = (MXC_F_MCR_RST_LPTMR0 + 64),
81  MXC_SYS_RESET_TMR5 = (MXC_F_MCR_RST_LPTMR1 + 64),
82  MXC_SYS_RESET_UART3 = (MXC_F_MCR_RST_LPUART0 + 64),
83 } mxc_sys_reset_t;
84 
86 typedef enum {
87  MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS,
88  MXC_SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PCLKDIS0_GPIO1_POS,
89  MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLKDIS0_DMA_POS,
90  MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLKDIS0_SPI0_POS,
91  MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLKDIS0_SPI1_POS,
92  MXC_SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PCLKDIS0_SPI2_POS,
93  MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLKDIS0_UART0_POS,
94  MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLKDIS0_UART1_POS,
95  MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLKDIS0_I2C0_POS,
96  MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS,
97  MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS,
98  MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS,
99  MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS,
100  MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLKDIS0_I2C1_POS,
101  /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
102  MXC_SYS_PERIPH_CLOCK_UART2 = (MXC_F_GCR_PCLKDIS1_UART2_POS + 32),
103  MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32),
104  MXC_SYS_PERIPH_CLOCK_WDT0 = (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32),
105  MXC_SYS_PERIPH_CLOCK_WDT1 = (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32),
106  MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLKDIS1_ICC0_POS + 32),
107  MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32),
108  MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32),
109  MXC_SYS_PERIPH_CLOCK_I2C2 = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32),
110  MXC_SYS_PERIPH_CLOCK_I2S = (MXC_F_GCR_PCLKDIS1_I2S_POS + 32),
111  /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
112  MXC_SYS_PERIPH_CLOCK_TMR4 = (MXC_F_MCR_CLKDIS_LPTMR0 + 64),
113  MXC_SYS_PERIPH_CLOCK_TMR5 = (MXC_F_MCR_CLKDIS_LPTMR1 + 64),
114  MXC_SYS_PERIPH_CLOCK_UART3 = (MXC_F_MCR_CLKDIS_LPUART0 + 64),
115 } mxc_sys_periph_clock_t;
116 
118 typedef enum {
119  MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO,
120  MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO,
121  MXC_SYS_CLOCK_ERFO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO,
122  MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO,
123  MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO,
124  MXC_SYS_CLOCK_EXTCLK = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
125 } mxc_sys_system_clock_t;
126 
127 /***** Function Prototypes *****/
128 
134 int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock);
135 
140 void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock);
141 
146 void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock);
147 
152 void MXC_SYS_RTCClockEnable (void);
153 
158 int MXC_SYS_RTCClockDisable();
159 
165 int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock);
166 
172 int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
173 
180 int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock);
181 
187 int MXC_SYS_Clock_Timeout (uint32_t ready);
192 void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
193 
194 #ifdef __cplusplus
195 }
196 #endif
197 
198 #endif /* _MXC_MXC_SYS_H_*/
MXC_F_GCR_RST0_PERIPH_POS
#define MXC_F_GCR_RST0_PERIPH_POS
Definition: gcr_regs.h:233
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO
Definition: gcr_regs.h:274
MXC_F_GCR_RST0_UART2_POS
#define MXC_F_GCR_RST0_UART2_POS
Definition: gcr_regs.h:227
MXC_F_MCR_CLKDIS_LPUART0
#define MXC_F_MCR_CLKDIS_LPUART0
Definition: mcr_regs.h:136
MXC_F_GCR_RST0_DMA_POS
#define MXC_F_GCR_RST0_DMA_POS
Definition: gcr_regs.h:179
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO
Definition: gcr_regs.h:272
MXC_F_GCR_RST0_I2C0_POS
#define MXC_F_GCR_RST0_I2C0_POS
Definition: gcr_regs.h:218
MXC_F_GCR_RST0_TMR3_POS
#define MXC_F_GCR_RST0_TMR3_POS
Definition: gcr_regs.h:200
MXC_F_GCR_PCLKDIS0_TMR3_POS
#define MXC_F_GCR_PCLKDIS0_TMR3_POS
Definition: gcr_regs.h:441
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO
Definition: gcr_regs.h:276
MXC_F_GCR_RST0_GPIO0_POS
#define MXC_F_GCR_RST0_GPIO0_POS
Definition: gcr_regs.h:185
MXC_F_GCR_RST0_UART1_POS
#define MXC_F_GCR_RST0_UART1_POS
Definition: gcr_regs.h:206
MXC_F_GCR_RST0_RTC_POS
#define MXC_F_GCR_RST0_RTC_POS
Definition: gcr_regs.h:221
MXC_F_GCR_RST0_SPI2_POS
#define MXC_F_GCR_RST0_SPI2_POS
Definition: gcr_regs.h:215
MXC_F_GCR_PCLKDIS1_I2C2_POS
#define MXC_F_GCR_PCLKDIS1_I2C2_POS
Definition: gcr_regs.h:565
MXC_F_GCR_PCLKDIS0_TMR0_POS
#define MXC_F_GCR_PCLKDIS0_TMR0_POS
Definition: gcr_regs.h:432
MXC_F_GCR_RST0_TMR1_POS
#define MXC_F_GCR_RST0_TMR1_POS
Definition: gcr_regs.h:194
MXC_F_GCR_RST1_I2C2_POS
#define MXC_F_GCR_RST1_I2C2_POS
Definition: gcr_regs.h:530
MXC_F_GCR_PCLKDIS1_WWDT1_POS
#define MXC_F_GCR_PCLKDIS1_WWDT1_POS
Definition: gcr_regs.h:553
MXC_F_GCR_PCLKDIS0_UART0_POS
#define MXC_F_GCR_PCLKDIS0_UART0_POS
Definition: gcr_regs.h:423
MXC_F_GCR_RST1_CRC_POS
#define MXC_F_GCR_RST1_CRC_POS
Definition: gcr_regs.h:521
MXC_F_GCR_PCLKDIS0_DMA_POS
#define MXC_F_GCR_PCLKDIS0_DMA_POS
Definition: gcr_regs.h:411
MXC_F_MCR_CLKDIS_LPTMR0
#define MXC_F_MCR_CLKDIS_LPTMR0
Definition: mcr_regs.h:130
MXC_F_GCR_RST0_SYS_POS
#define MXC_F_GCR_RST0_SYS_POS
Definition: gcr_regs.h:236
MXC_F_GCR_RST0_TRNG_POS
#define MXC_F_GCR_RST0_TRNG_POS
Definition: gcr_regs.h:224
MXC_F_GCR_PCLKDIS0_I2C1_POS
#define MXC_F_GCR_PCLKDIS0_I2C1_POS
Definition: gcr_regs.h:444
MXC_F_GCR_PCLKDIS0_UART1_POS
#define MXC_F_GCR_PCLKDIS0_UART1_POS
Definition: gcr_regs.h:426
MXC_F_GCR_RST0_SOFT_POS
#define MXC_F_GCR_RST0_SOFT_POS
Definition: gcr_regs.h:230
MXC_F_GCR_PCLKDIS1_AES_POS
#define MXC_F_GCR_PCLKDIS1_AES_POS
Definition: gcr_regs.h:562
MXC_F_MCR_RST_LPTMR1
#define MXC_F_MCR_RST_LPTMR1
Definition: mcr_regs.h:116
MXC_F_GCR_RST0_SPI1_POS
#define MXC_F_GCR_RST0_SPI1_POS
Definition: gcr_regs.h:212
MXC_F_GCR_PCLKDIS1_ICC0_POS
#define MXC_F_GCR_PCLKDIS1_ICC0_POS
Definition: gcr_regs.h:556
MXC_F_GCR_PCLKDIS1_WWDT0_POS
#define MXC_F_GCR_PCLKDIS1_WWDT0_POS
Definition: gcr_regs.h:550
MXC_F_GCR_PCLKDIS1_I2S_POS
#define MXC_F_GCR_PCLKDIS1_I2S_POS
Definition: gcr_regs.h:568
MXC_F_MCR_RST_LPUART0
#define MXC_F_MCR_RST_LPUART0
Definition: mcr_regs.h:119
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO
Definition: gcr_regs.h:268
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO
Definition: gcr_regs.h:270
MXC_F_GCR_PCLKDIS1_UART2_POS
#define MXC_F_GCR_PCLKDIS1_UART2_POS
Definition: gcr_regs.h:544
MXC_F_GCR_RST0_SPI0_POS
#define MXC_F_GCR_RST0_SPI0_POS
Definition: gcr_regs.h:209
MXC_F_GCR_PCLKDIS0_SPI2_POS
#define MXC_F_GCR_PCLKDIS0_SPI2_POS
Definition: gcr_regs.h:420
MXC_F_MCR_CLKDIS_LPTMR1
#define MXC_F_MCR_CLKDIS_LPTMR1
Definition: mcr_regs.h:133
MXC_F_GCR_PCLKDIS0_TMR2_POS
#define MXC_F_GCR_PCLKDIS0_TMR2_POS
Definition: gcr_regs.h:438
MXC_F_GCR_RST1_WDT1_POS
#define MXC_F_GCR_RST1_WDT1_POS
Definition: gcr_regs.h:518
MXC_F_GCR_PCLKDIS0_GPIO0_POS
#define MXC_F_GCR_PCLKDIS0_GPIO0_POS
Definition: gcr_regs.h:405
MXC_F_MCR_RST_LPTMR0
#define MXC_F_MCR_RST_LPTMR0
Definition: mcr_regs.h:113
MXC_F_GCR_RST0_GPIO1_POS
#define MXC_F_GCR_RST0_GPIO1_POS
Definition: gcr_regs.h:188
MXC_F_GCR_RST1_I2S_POS
#define MXC_F_GCR_RST1_I2S_POS
Definition: gcr_regs.h:533
MXC_F_GCR_RST1_I2C1_POS
#define MXC_F_GCR_RST1_I2C1_POS
Definition: gcr_regs.h:515
MXC_F_GCR_PCLKDIS0_GPIO1_POS
#define MXC_F_GCR_PCLKDIS0_GPIO1_POS
Definition: gcr_regs.h:408
MXC_F_GCR_PCLKDIS0_I2C0_POS
#define MXC_F_GCR_PCLKDIS0_I2C0_POS
Definition: gcr_regs.h:429
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
Definition: gcr_regs.h:278
MXC_F_GCR_RST0_TMR2_POS
#define MXC_F_GCR_RST0_TMR2_POS
Definition: gcr_regs.h:197
MXC_F_GCR_RST0_UART0_POS
#define MXC_F_GCR_RST0_UART0_POS
Definition: gcr_regs.h:203
MXC_F_GCR_RST1_AES_POS
#define MXC_F_GCR_RST1_AES_POS
Definition: gcr_regs.h:524
MXC_F_GCR_PCLKDIS1_CRC_POS
#define MXC_F_GCR_PCLKDIS1_CRC_POS
Definition: gcr_regs.h:559
MXC_F_GCR_RST0_TMR0_POS
#define MXC_F_GCR_RST0_TMR0_POS
Definition: gcr_regs.h:191
MXC_F_GCR_PCLKDIS0_SPI0_POS
#define MXC_F_GCR_PCLKDIS0_SPI0_POS
Definition: gcr_regs.h:414
MXC_F_GCR_PCLKDIS0_SPI1_POS
#define MXC_F_GCR_PCLKDIS0_SPI1_POS
Definition: gcr_regs.h:417
MXC_F_GCR_PCLKDIS0_TMR1_POS
#define MXC_F_GCR_PCLKDIS0_TMR1_POS
Definition: gcr_regs.h:435
MXC_F_GCR_PCLKDIS1_TRNG_POS
#define MXC_F_GCR_PCLKDIS1_TRNG_POS
Definition: gcr_regs.h:547
MXC_F_GCR_RST0_WDT0_POS
#define MXC_F_GCR_RST0_WDT0_POS
Definition: gcr_regs.h:182