MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
max32675.h
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32  * $Date: 2016-04-27 09:12:38 -0700 (Wed, 27 Apr 2016) $
33  * $Revision: 22537 $
34  *
35  ******************************************************************************/
36 #ifndef _MAX32675_REGS_H_
37 #define _MAX32675_REGS_H_
38 
39 #ifndef TARGET_NUM
40 #define TARGET_NUM 32675
41 #endif
42 
43 #define MXC_NUMCORES 1
44 
45 #include <stdint.h>
46 
47 #ifndef FALSE
48 #define FALSE (0)
49 #endif
50 
51 #ifndef TRUE
52 #define TRUE (1)
53 #endif
54 
55 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
56 #if defined ( __GNUC__ )
57 #define __weak __attribute__((weak))
58 
59 #elif defined ( __CC_ARM)
60 
61 #define inline __inline
62 #pragma anon_unions
63 
64 #endif
65 
66 typedef enum {
67  NonMaskableInt_IRQn = -14,
68  HardFault_IRQn = -13,
69  MemoryManagement_IRQn = -12,
70  BusFault_IRQn = -11,
71  UsageFault_IRQn = -10,
72  SVCall_IRQn = -5,
73  DebugMonitor_IRQn = -4,
74  PendSV_IRQn = -2,
75  SysTick_IRQn = -1,
76 
77  /* Device-specific interrupt sources (external to ARM core) */
78  /* table entry number */
79  /* |||| */
80  /* |||| table offset address */
81  /* vvvv vvvvvv */
82 
83  PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
84  WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
85  RSV02_IRQn, /* 0x12 0x0048 18: Reserved */
86  RTC_IRQn, /* 0x13 0x004C 19: RTC */
87  TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
88  TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
89  TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
90  TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
91  TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */
92  TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */
93  TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */
94  RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
95  RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
96  I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
97  UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
98  UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
99  SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */
100  SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */
101  SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */
102  RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
103  RSV20_IRQn, /* 0x24 0x0090 36: Reserved */
104  RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
105  RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */
106  FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
107  GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
108  GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO2 */
109  RSV26_IRQn, /* 0x2A 0x00A8 42: GPIO3 */
110  RSV27_IRQn, /* 0x2B 0x00AC 43: Crypto */
111  DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
112  DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
113  DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
114  DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
115  RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
116  RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
117  UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
118  RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */
119  I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
120  RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */
121  RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */
122  RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */
123  RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */
124  RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */
125  RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */
126  RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */
127  RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */
128  RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */
129  RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */
130  RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */
131  RSV48_IRQn, /* 0x40 0x0100 64: Reserved */
132  RSV49_IRQn, /* 0x41 0x0104 65: Reserved */
133  RSV50_IRQn, /* 0x42 0x0108 66: Reserved */
134  RSV51_IRQn, /* 0x43 0x010C 67: Reserved */
135  RSV52_IRQn, /* 0x44 0x0110 68: Reserved */
136  RSV53_IRQn, /* 0x45 0x0114 69: Reserved */
137  RSV54_IRQn, /* 0x46 0x0118 70: Reserved */
138  RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
139  RSV56_IRQn, /* 0x48 0x0120 72: Reserved */
140  WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */
141  RSV57_IRQn, /* 0x4A 0x0128 74: Reserved */
142  RSV58_IRQn, /* 0x4B 0x012C 75: Reserved */
143  RSV59_IRQn, /* 0x4C 0x0130 76: Reserved */
144  RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
145  I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */
146  RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */
147  RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
148  RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
149  RSV66_IRQn, /* 0x52 0x0148 82: Reserved */
150  RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */
151  DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
152  DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
153  DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
154  DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
155  DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */
156  DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */
157  DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */
158  DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */
159  DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */
160  DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */
161  DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */
162  DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */
163  RSV80_IRQn, /* 0x60 0x0180 96: Reserved */
164  RSV81_IRQn, /* 0x61 0x0184 97: Reserved */
165  ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
166  RSV83_IRQn, /* 0x63 0x018C 99: Reserved */
167  RSV84_IRQn, /* 0x64 0x0190 100: Reserved */
168  RSV85_IRQn, /* 0x65 0x0194 101: Reserved */
169  RSV86_IRQn, /* 0x66 0x0198 102: Reserved */
170  RSV87_IRQn, /* 0x67 0x019C 103: Reserved */
171  UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
172  RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */
173  RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */
174  RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */
175  RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */
176  RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */
177  RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */
178  RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */
179  RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */
180  AES_IRQn, /* 0x71 0x01C4 113: Reserved */
181  CRC_IRQn, /* 0x72 0x01C8 114: Reserved */
182  I2S_IRQn, /* 0x73 0x01CC 115: Reserved */
183  MXC_IRQ_EXT_COUNT,
184 } IRQn_Type;
185 
186 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
187 
188 
189 /* ================================================================================ */
190 /* ================ Processor and Core Peripheral Section ================ */
191 /* ================================================================================ */
192 
193 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
194 #define __CM4_REV 0x0100
195 #define __MPU_PRESENT 1
196 #define __NVIC_PRIO_BITS 3
197 #define __Vendor_SysTickConfig 0
198 #define __FPU_PRESENT 1
200 #include <core_cm4.h>
201 #include "system_max32675.h"
204 /* ================================================================================ */
205 /* ================== Device Specific Memory Section ================== */
206 /* ================================================================================ */
207 
208 #define MXC_ROM_MEM_BASE 0x00000000UL
209 #define MXC_ROM_MEM_SIZE 0x00020000UL
210 #define MXC_XIP_MEM_BASE 0x08000000UL
211 #define MXC_XIP_MEM_SIZE 0x08000000UL
212 #define MXC_FLASH0_MEM_BASE 0x10000000UL
213 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
214 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
215 #define MXC_FLASH_MEM_SIZE 0x00060000UL
216 #define MXC_INFO0_MEM_BASE 0x10800000UL
217 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
218 #define MXC_INFO_MEM_SIZE 0x00004000UL
219 #define MXC_SRAM_MEM_BASE 0x20000000UL
220 #define MXC_SRAM_MEM_SIZE 0x000BE000UL
221 #define MXC_XIP_DATA_MEM_BASE 0x80000000UL
222 #define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
223 
224 /* ================================================================================ */
225 /* ================ Device Specific Peripheral Section ================ */
226 /* ================================================================================ */
227 
228 /*
229  Base addresses and configuration settings for all MAX32675 peripheral modules.
230 */
231 
232 /******************************************************************************/
233 /* Global control */
234 #define MXC_BASE_GCR ((uint32_t)0x40000000UL)
235 #define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
236 
237 /******************************************************************************/
238 /* Non-battery backed SI Registers */
239 #define MXC_BASE_SIR ((uint32_t)0x40000400UL)
240 #define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
241 
242 /******************************************************************************/
243 /* Non-battery backed Function Control */
244 #define MXC_BASE_FCR ((uint32_t)0x40000800UL)
245 #define MXC_FCR ((mxc_fcr_regs_t*)MXC_BASE_FCR)
246 
247 /******************************************************************************/
248 /* Trim System Initalization Register */
249 #define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL)
250 #define MXC_TRIMSIR ((mxc_trimsir_regs_t*)MXC_BASE_TRIMSIR)
251 
252 /******************************************************************************/
253 /* Watchdog */
254 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
255 #define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
256 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
257 #define MXC_WDT1 ((mxc_wdt_regs_t*)MXC_BASE_WDT1)
258 
259 /******************************************************************************/
260 /* Real Time Clock */
261 #define MXC_BASE_RTC ((uint32_t)0x40106000UL)
262 #define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
263 
264 /******************************************************************************/
265 /* Power Sequencer */
266 #define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL)
267 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
268 
269 /******************************************************************************/
270 /* MISC Control */
271 #define MXC_BASE_MCR ((uint32_t)0x40106C00UL)
272 #define MXC_MCR ((mxc_mcr_regs_t*)MXC_BASE_MCR)
273 
274 
275 /******************************************************************************/
276 /* Error Correcting Code */
277 #define MXC_BASE_ECC ((uint32_t)0x40105400UL)
278 #define MXC_ECC ((mxc_ecc_regs_t*)MXC_BASE_ECC)
279 
280 
281 /******************************************************************************/
282 /* GPIO */
283 #define MXC_CFG_GPIO_INSTANCES (3)
284 #define MXC_CFG_GPIO_PINS_PORT (32)
285 
286 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
287 #define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
288 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
289 #define MXC_GPIO1 ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)
290 
291 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \
292  (p) == MXC_GPIO1 ? 1 : -1)
293 
294 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \
295  (i) == 1 ? MXC_GPIO1 : 0)
296 
297 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \
298  (i) == 1 ? GPIO1_IRQn : 0)
299 
300 /******************************************************************************/
301 
302 
303 
304 
305 #define SEC(s) (((unsigned long)s) * 1000000UL)
306 #define MSEC(ms) (ms * 1000UL)
307 #define USEC(us) (us)
308 /* Timer */
309 #define MXC_CFG_TMR_INSTANCES (6)
310 
311 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
312 #define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
313 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
314 #define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
315 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
316 #define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
317 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
318 #define MXC_TMR3 ((mxc_tmr_regs_t*)MXC_BASE_TMR3)
319 #define MXC_BASE_TMR4 ((uint32_t)0x40114000UL)
320 #define MXC_TMR4 ((mxc_tmr_regs_t*)MXC_BASE_TMR4)
321 #define MXC_BASE_TMR5 ((uint32_t)0x40115000UL)
322 #define MXC_TMR5 ((mxc_tmr_regs_t*)MXC_BASE_TMR5)
323 
324 #define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
325  (i) == 1 ? TMR1_IRQn : \
326  (i) == 2 ? TMR2_IRQn : \
327  (i) == 3 ? TMR3_IRQn : \
328  (i) == 4 ? TMR4_IRQn : \
329  (i) == 5 ? TMR5_IRQn : 0)
330 
331 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
332  (i) == 1 ? MXC_BASE_TMR1 : \
333  (i) == 2 ? MXC_BASE_TMR2 : \
334  (i) == 3 ? MXC_BASE_TMR3 : \
335  (i) == 4 ? MXC_BASE_TMR4 : \
336  (i) == 5 ? MXC_BASE_TMR5 : 0)
337 
338 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
339  (i) == 1 ? MXC_TMR1 : \
340  (i) == 2 ? MXC_TMR2 : \
341  (i) == 3 ? MXC_TMR3 : \
342  (i) == 4 ? MXC_TMR4 : \
343  (i) == 5 ? MXC_TMR5 : 0)
344 
345 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
346  (p) == MXC_TMR1 ? 1 : \
347  (p) == MXC_TMR2 ? 2 : \
348  (p) == MXC_TMR3 ? 3 : \
349  (p) == MXC_TMR4 ? 4 : \
350  (p) == MXC_TMR5 ? 5 : -1)
351 
352 /******************************************************************************/
353 /* I2C */
354 #define MXC_I2C_INSTANCES (3)
355 
356 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
357 #define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
358 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
359 #define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
360 #define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
361 #define MXC_I2C2 ((mxc_i2c_regs_t*)MXC_BASE_I2C2)
362 
363 
364 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
365  (i) == 1 ? I2C1_IRQn : \
366  (i) == 2 ? I2C2_IRQn : 0)
367 
368 #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
369  (i) == 1 ? MXC_BASE_I2C1 : \
370  (i) == 2 ? MXC_BASE_I2C2 : 0)
371 
372 #define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
373  (i) == 1 ? MXC_I2C1 : \
374  (i) == 2 ? MXC_I2C2 : 0)
375 
376 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
377  (p) == MXC_I2C1 ? 1 : \
378  (p) == MXC_I2C2 ? 2 : -1)
379 #define MXC_I2C_FIFO_DEPTH (8)
380 
381 
382 /******************************************************************************/
383 /* DMA */
384 #define MXC_DMA_CHANNELS (8)
385 
386 #define MXC_BASE_DMA ((uint32_t)0x40028000UL)
387 #define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA)
388 
389 /******************************************************************************/
390 /* FLC */
391 #define MXC_FLC_INSTANCES (1)
392 
393 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
394 #define MXC_FLC0 ((mxc_flc_regs_t*)MXC_BASE_FLC0)
395 
396 
397 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
398 
399 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0)
400 
401 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0)
402 
403 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1)
404 /******************************************************************************/
405 /* Instruction Cache */
406 
407 #define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
408 #define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC)
409 
410 /******************************************************************************/
411 /* Data Cache */
412 #define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
413 #define MXC_EMCC ((mxc_emcc_regs_t*)MXC_BASE_EMCC)
414 
415 /******************************************************************************/
416 /* XXX Actually reserved! */
417 #define MXC_BASE_RESERVED ((uint32_t)0x40035000UL)
418 
419 /******************************************************************************/
420 /* One Wire Master */
421 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
422 #define MXC_OWM ((mxc_owm_regs_t*)MXC_BASE_OWM)
423 
424 /******************************************************************************/
425 /* UART / Serial Port Interface */
426 
427 #define MXC_UART_INSTANCES (4)
428 #define MXC_UART_FIFO_DEPTH (8)
429 
430 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
431 #define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
432 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
433 #define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
434 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
435 #define MXC_UART2 ((mxc_uart_regs_t*)MXC_BASE_UART2)
436 #define MXC_BASE_UART3 ((uint32_t)0x40145000UL)
437 #define MXC_UART3 ((mxc_uart_regs_t*)MXC_BASE_UART3)
438 
439 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
440  (i) == 1 ? UART1_IRQn : \
441  (i) == 2 ? UART2_IRQn : \
442  (i) == 3 ? UART3_IRQn : 0)
443 
444 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
445  (i) == 1 ? MXC_BASE_UART1 : \
446  (i) == 2 ? MXC_BASE_UART2 : \
447  (i) == 3 ? MXC_BASE_UART3 : 0)
448 
449 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
450  (i) == 1 ? MXC_UART1 : \
451  (i) == 2 ? MXC_UART2 : \
452  (i) == 3 ? MXC_UART3 : 0)
453 
454 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
455  (p) == MXC_UART1 ? 1 : \
456  (p) == MXC_UART2 ? 2 : \
457  (p) == MXC_UART3 ? 3 : -1)
458 
459 /******************************************************************************/
460 /* SPI */
461 
462 #define MXC_SPI_INSTANCES (3)
463 #define MXC_SPI_SS_INSTANCES (4)
464 #define MXC_SPI_FIFO_DEPTH (32)
465 
466 #define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
467 #define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI0)
468 #define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
469 #define MXC_SPI1 ((mxc_spi_regs_t*)MXC_BASE_SPI1)
470 #define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
471 #define MXC_SPI2 ((mxc_spi_regs_t*)MXC_BASE_SPI2)
472 
473 
474 
475 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : \
476  (p) == MXC_SPI1 ? 1 : \
477  (p) == MXC_SPI2 ? 2 : -1)
478 
479 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
480  (i) == 1 ? MXC_BASE_SPI1 : \
481  (i) == 2 ? MXC_BASE_SPI2 : 0)
482 
483 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
484  (i) == 1 ? MXC_SPI1 : \
485  (i) == 2 ? MXC_SPI2 : 0)
486 
487 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI3_IRQn : \
488  (i) == 1 ? SPI0_IRQn : \
489  (i) == 2 ? SPI1_IRQn : 0)
490 
491 
492 /******************************************************************************/
493 /* TRNG */
494 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
495 #define MXC_TRNG ((mxc_trng_regs_t*)MXC_BASE_TRNG)
496 
497 /******************************************************************************/
498 /* AES */
499 #define MXC_BASE_AES ((uint32_t)0x40007400UL)
500 #define MXC_AES ((mxc_aes_regs_t*)MXC_BASE_AES)
501 
502 /******************************************************************************/
503 /* AES Keys */
504 #define MXC_BASE_AESKEY ((uint32_t)0x40007800UL)
505 #define MXC_AESKEY ((mxc_aes_key_regs_t*)MXC_BASE_AESKEY)
506 
507 /******************************************************************************/
508 /* CRC */
509 #define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
510 #define MXC_CRC ((mxc_crc_regs_t*)MXC_BASE_CRC)
511 
512 /******************************************************************************/
513 #define MXC_BASE_I2S ((uint32_t)0x40060000UL)
514 #define MXC_I2S ((mxc_i2s_regs_t*)MXC_BASE_I2S)
515 
516 /******************************************************************************/
517 /* BBFC */
518 #define MXC_BASE_BBFC ((uint32_t)0x40005800UL)
519 #define MXC_BBFC ((mxc_bbfc_regs_t*)MXC_BASE_BBFC)
520 
521 
522 /******************************************************************************/
523 /* Bit Shifting */
524 
525 #define MXC_F_BIT_0 (1 << 0)
526 #define MXC_F_BIT_1 (1 << 1)
527 #define MXC_F_BIT_2 (1 << 2)
528 #define MXC_F_BIT_3 (1 << 3)
529 #define MXC_F_BIT_4 (1 << 4)
530 #define MXC_F_BIT_5 (1 << 5)
531 #define MXC_F_BIT_6 (1 << 6)
532 #define MXC_F_BIT_7 (1 << 7)
533 #define MXC_F_BIT_8 (1 << 8)
534 #define MXC_F_BIT_9 (1 << 9)
535 #define MXC_F_BIT_10 (1 << 10)
536 #define MXC_F_BIT_11 (1 << 11)
537 #define MXC_F_BIT_12 (1 << 12)
538 #define MXC_F_BIT_13 (1 << 13)
539 #define MXC_F_BIT_14 (1 << 14)
540 #define MXC_F_BIT_15 (1 << 15)
541 #define MXC_F_BIT_16 (1 << 16)
542 #define MXC_F_BIT_17 (1 << 17)
543 #define MXC_F_BIT_18 (1 << 18)
544 #define MXC_F_BIT_19 (1 << 19)
545 #define MXC_F_BIT_20 (1 << 20)
546 #define MXC_F_BIT_21 (1 << 21)
547 #define MXC_F_BIT_22 (1 << 22)
548 #define MXC_F_BIT_23 (1 << 23)
549 #define MXC_F_BIT_24 (1 << 24)
550 #define MXC_F_BIT_25 (1 << 25)
551 #define MXC_F_BIT_26 (1 << 26)
552 #define MXC_F_BIT_27 (1 << 27)
553 #define MXC_F_BIT_28 (1 << 28)
554 #define MXC_F_BIT_29 (1 << 29)
555 #define MXC_F_BIT_30 (1 << 30)
556 #define MXC_F_BIT_31 (1 << 31)
557 
558 /******************************************************************************/
559 /* Bit Banding */
560 
561 
562 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
563  (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
564 
565 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
566 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
567 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
568 
569 #define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask))
570 
571 /******************************************************************************/
572 /* SCB CPACR */
573 
574 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
575 #define SCB_CPACR_CP10_Pos 20
576 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
577 #define SCB_CPACR_CP11_Pos 22
578 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
580 #endif /* _MAX32675_REGS_H_ */