MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
aes_regs.h
1 
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39 
40 #ifndef _AES_REGS_H_
41 #define _AES_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t ctrl;
90  __IO uint32_t status;
91  __IO uint32_t intfl;
92  __IO uint32_t inten;
93  __IO uint32_t fifo;
95 
96 /* Register offsets for module AES */
103  #define MXC_R_AES_CTRL ((uint32_t)0x00000000UL)
104  #define MXC_R_AES_STATUS ((uint32_t)0x00000004UL)
105  #define MXC_R_AES_INTFL ((uint32_t)0x00000008UL)
106  #define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL)
107  #define MXC_R_AES_FIFO ((uint32_t)0x00000010UL)
116  #define MXC_F_AES_CTRL_EN_POS 0
117  #define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS))
119  #define MXC_F_AES_CTRL_DMA_RX_EN_POS 1
120  #define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS))
122  #define MXC_F_AES_CTRL_DMA_TX_EN_POS 2
123  #define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS))
125  #define MXC_F_AES_CTRL_START_POS 3
126  #define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS))
128  #define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4
129  #define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS))
131  #define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5
132  #define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS))
134  #define MXC_F_AES_CTRL_KEY_SIZE_POS 6
135  #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
136  #define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL)
137  #define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS)
138  #define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL)
139  #define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS)
140  #define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL)
141  #define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS)
143  #define MXC_F_AES_CTRL_TYPE_POS 8
144  #define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS))
154  #define MXC_F_AES_STATUS_BUSY_POS 0
155  #define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS))
157  #define MXC_F_AES_STATUS_INPUT_EM_POS 1
158  #define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS))
160  #define MXC_F_AES_STATUS_INPUT_FULL_POS 2
161  #define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS))
163  #define MXC_F_AES_STATUS_OUTPUT_EM_POS 3
164  #define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS))
166  #define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4
167  #define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS))
177  #define MXC_F_AES_INTFL_DONE_POS 0
178  #define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS))
180  #define MXC_F_AES_INTFL_KEY_CHANGE_POS 1
181  #define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS))
183  #define MXC_F_AES_INTFL_KEY_ZERO_POS 2
184  #define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS))
186  #define MXC_F_AES_INTFL_OV_POS 3
187  #define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS))
197  #define MXC_F_AES_INTEN_DONE_POS 0
198  #define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS))
200  #define MXC_F_AES_INTEN_KEY_CHANGE_POS 1
201  #define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS))
203  #define MXC_F_AES_INTEN_KEY_ZERO_POS 2
204  #define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS))
206  #define MXC_F_AES_INTEN_OV_POS 3
207  #define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS))
217  #define MXC_F_AES_FIFO_DATA_POS 0
218  #define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS))
222 #ifdef __cplusplus
223 }
224 #endif
225 
226 #endif /* _AES_REGS_H_ */
mxc_aes_regs_t::fifo
__IO uint32_t fifo
Definition: aes_regs.h:93
mxc_aes_regs_t::intfl
__IO uint32_t intfl
Definition: aes_regs.h:91
mxc_aes_regs_t::status
__IO uint32_t status
Definition: aes_regs.h:90
mxc_aes_regs_t::ctrl
__IO uint32_t ctrl
Definition: aes_regs.h:89
mxc_aes_regs_t
Definition: aes_regs.h:88
mxc_aes_regs_t::inten
__IO uint32_t inten
Definition: aes_regs.h:92