MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675

Macros

#define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS   0
 
#define MXC_F_PWRSEQ_LPMEMSD_RAM0   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS   1
 
#define MXC_F_PWRSEQ_LPMEMSD_RAM1   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS   2
 
#define MXC_F_PWRSEQ_LPMEMSD_RAM2   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS   3
 
#define MXC_F_PWRSEQ_LPMEMSD_RAM3   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS))
 

Detailed Description

Low Power Memory Shutdown Control.

Macro Definition Documentation

◆ MXC_F_PWRSEQ_LPMEMSD_RAM0

#define MXC_F_PWRSEQ_LPMEMSD_RAM0   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS))

LPMEMSD_RAM0 Mask

◆ MXC_F_PWRSEQ_LPMEMSD_RAM0_POS

#define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS   0

LPMEMSD_RAM0 Position

◆ MXC_F_PWRSEQ_LPMEMSD_RAM1

#define MXC_F_PWRSEQ_LPMEMSD_RAM1   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS))

LPMEMSD_RAM1 Mask

◆ MXC_F_PWRSEQ_LPMEMSD_RAM1_POS

#define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS   1

LPMEMSD_RAM1 Position

◆ MXC_F_PWRSEQ_LPMEMSD_RAM2

#define MXC_F_PWRSEQ_LPMEMSD_RAM2   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS))

LPMEMSD_RAM2 Mask

◆ MXC_F_PWRSEQ_LPMEMSD_RAM2_POS

#define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS   2

LPMEMSD_RAM2 Position

◆ MXC_F_PWRSEQ_LPMEMSD_RAM3

#define MXC_F_PWRSEQ_LPMEMSD_RAM3   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS))

LPMEMSD_RAM3 Mask

◆ MXC_F_PWRSEQ_LPMEMSD_RAM3_POS

#define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS   3

LPMEMSD_RAM3 Position