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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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Macros | |
#define | MXC_R_AFE_ADC_ONE_PD ((uint32_t)0x00800001UL) |
#define | MXC_R_AFE_ADC_ONE_CONV_START ((uint32_t)0x00810001UL) |
#define | MXC_R_AFE_ADC_ONE_SEQ_START ((uint32_t)0x00820001UL) |
#define | MXC_R_AFE_ADC_ONE_CAL_START ((uint32_t)0x00830001UL) |
#define | MXC_R_AFE_ADC_ONE_GP0_CTRL ((uint32_t)0x00840001UL) |
#define | MXC_R_AFE_ADC_ONE_GP1_CTRL ((uint32_t)0x00850001UL) |
#define | MXC_R_AFE_ADC_ONE_GP_CONV ((uint32_t)0x00860001UL) |
#define | MXC_R_AFE_ADC_ONE_GP_SEQ_ADDR ((uint32_t)0x00870001UL) |
#define | MXC_R_AFE_ADC_ONE_FILTER ((uint32_t)0x00880001UL) |
#define | MXC_R_AFE_ADC_ONE_CTRL ((uint32_t)0x00890001UL) |
#define | MXC_R_AFE_ADC_ONE_SOURCE ((uint32_t)0x008A0001UL) |
#define | MXC_R_AFE_ADC_ONE_MUX_CTRL0 ((uint32_t)0x008B0001UL) |
#define | MXC_R_AFE_ADC_ONE_MUX_CTRL1 ((uint32_t)0x008C0001UL) |
#define | MXC_R_AFE_ADC_ONE_MUX_CTRL2 ((uint32_t)0x008D0001UL) |
#define | MXC_R_AFE_ADC_ONE_PGA ((uint32_t)0x008E0001UL) |
#define | MXC_R_AFE_ADC_ONE_WAIT_EXT ((uint32_t)0x008F0001UL) |
#define | MXC_R_AFE_ADC_ONE_WAIT_START ((uint32_t)0x00900001UL) |
#define | MXC_R_AFE_ADC_ONE_PART_ID ((uint32_t)0x00910003UL) |
#define | MXC_R_AFE_ADC_ONE_SYSC_SEL ((uint32_t)0x00920003UL) |
#define | MXC_R_AFE_ADC_ONE_SYS_OFF_A ((uint32_t)0x00930003UL) |
#define | MXC_R_AFE_ADC_ONE_SYS_OFF_B ((uint32_t)0x00940003UL) |
#define | MXC_R_AFE_ADC_ONE_SYS_GAIN_A ((uint32_t)0x00950003UL) |
#define | MXC_R_AFE_ADC_ONE_SYS_GAIN_B ((uint32_t)0x00960003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_OFF ((uint32_t)0x00970003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_1 ((uint32_t)0x00980003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_2 ((uint32_t)0x00990003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_4 ((uint32_t)0x009A0003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_8 ((uint32_t)0x009B0003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_16 ((uint32_t)0x009C0003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_32 ((uint32_t)0x009D0003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_64 ((uint32_t)0x009E0003UL) |
#define | MXC_R_AFE_ADC_ONE_SELF_GAIN_128 ((uint32_t)0x009F0003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH0 ((uint32_t)0x00A00003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH1 ((uint32_t)0x00A10003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH2 ((uint32_t)0x00A20003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH3 ((uint32_t)0x00A30003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH4 ((uint32_t)0x00A40003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH5 ((uint32_t)0x00A50003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH6 ((uint32_t)0x00A60003UL) |
#define | MXC_R_AFE_ADC_ONE_LTHRESH7 ((uint32_t)0x00A70003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH0 ((uint32_t)0x00A80003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH1 ((uint32_t)0x00A90003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH2 ((uint32_t)0x00AA0003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH3 ((uint32_t)0x00AB0003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH4 ((uint32_t)0x00AC0003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH5 ((uint32_t)0x00AD0003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH6 ((uint32_t)0x00AE0003UL) |
#define | MXC_R_AFE_ADC_ONE_UTHRESH7 ((uint32_t)0x00AF0003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA0 ((uint32_t)0x00B00003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA1 ((uint32_t)0x00B10003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA2 ((uint32_t)0x00B20003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA3 ((uint32_t)0x00B30003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA4 ((uint32_t)0x00B40003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA5 ((uint32_t)0x00B50003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA6 ((uint32_t)0x00B60003UL) |
#define | MXC_R_AFE_ADC_ONE_DATA7 ((uint32_t)0x00B70003UL) |
#define | MXC_R_AFE_ADC_ONE_STATUS ((uint32_t)0x00B80003UL) |
#define | MXC_R_AFE_ADC_ONE_STATUS_IE ((uint32_t)0x00B90003UL) |
#define | MXC_R_AFE_ADC_ONE_UC_0 ((uint32_t)0x00BA0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_1 ((uint32_t)0x00BB0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_2 ((uint32_t)0x00BC0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_3 ((uint32_t)0x00BD0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_4 ((uint32_t)0x00BE0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_5 ((uint32_t)0x00BF0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_6 ((uint32_t)0x00C00002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_7 ((uint32_t)0x00C10002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_8 ((uint32_t)0x00C20002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_9 ((uint32_t)0x00C30002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_10 ((uint32_t)0x00C40002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_11 ((uint32_t)0x00C50002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_12 ((uint32_t)0x00C60002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_13 ((uint32_t)0x00C70002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_14 ((uint32_t)0x00C80002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_15 ((uint32_t)0x00C90002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_16 ((uint32_t)0x00CA0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_17 ((uint32_t)0x00CB0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_18 ((uint32_t)0x00CC0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_19 ((uint32_t)0x00CD0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_20 ((uint32_t)0x00CE0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_21 ((uint32_t)0x00CF0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_22 ((uint32_t)0x00D00002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_23 ((uint32_t)0x00D10002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_24 ((uint32_t)0x00D20002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_25 ((uint32_t)0x00D30002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_26 ((uint32_t)0x00D40002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_27 ((uint32_t)0x00D50002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_28 ((uint32_t)0x00D60002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_29 ((uint32_t)0x00D70002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_30 ((uint32_t)0x00D80002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_31 ((uint32_t)0x00D90002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_32 ((uint32_t)0x00DA0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_33 ((uint32_t)0x00DB0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_34 ((uint32_t)0x00DC0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_35 ((uint32_t)0x00DD0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_36 ((uint32_t)0x00DE0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_37 ((uint32_t)0x00DF0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_38 ((uint32_t)0x00E00002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_39 ((uint32_t)0x00E10002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_40 ((uint32_t)0x00E20002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_41 ((uint32_t)0x00E30002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_42 ((uint32_t)0x00E40002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_43 ((uint32_t)0x00E50002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_44 ((uint32_t)0x00E60002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_45 ((uint32_t)0x00E70002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_46 ((uint32_t)0x00E80002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_47 ((uint32_t)0x00E90002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_48 ((uint32_t)0x00EA0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_49 ((uint32_t)0x00EB0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_50 ((uint32_t)0x00EC0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_51 ((uint32_t)0x00ED0002UL) |
#define | MXC_R_AFE_ADC_ONE_UC_52 ((uint32_t)0x00EE0002UL) |
#define | MXC_R_AFE_ADC_ONE_UCADDR ((uint32_t)0x00EF0001UL) |
#define | MXC_R_AFE_ADC_ONE_FT_PWORD ((uint32_t)0x00F00001UL) |
#define | MXC_R_AFE_ADC_ONE_ADC_TRIM0 ((uint32_t)0x00F70003UL) |
#define | MXC_R_AFE_ADC_ONE_ADC_TRIM1 ((uint32_t)0x00F80002UL) |
#define | MXC_R_AFE_ADC_ONE_ANA_TRIM ((uint32_t)0x00F90002UL) |
#define | MXC_R_AFE_ADC_ONE_SYS_CTRL ((uint32_t)0x00FA0001UL) |
#define | MXC_R_AFE_ADC_ONE_TS_CTRL ((uint32_t)0x00FC0001UL) |
AFE_ADC_ONE Peripheral Register Offsets from the AFE_ADC_ONE Base Peripheral Address.
#define MXC_R_AFE_ADC_ONE_ADC_TRIM0 ((uint32_t)0x00F70003UL) |
Offset from AFE_ADC_ONE Base Address: 0xF70003
#define MXC_R_AFE_ADC_ONE_ADC_TRIM1 ((uint32_t)0x00F80002UL) |
Offset from AFE_ADC_ONE Base Address: 0xF80002
#define MXC_R_AFE_ADC_ONE_ANA_TRIM ((uint32_t)0x00F90002UL) |
Offset from AFE_ADC_ONE Base Address: 0xF90002
#define MXC_R_AFE_ADC_ONE_CAL_START ((uint32_t)0x00830001UL) |
Offset from AFE_ADC_ONE Base Address: 0x830001
#define MXC_R_AFE_ADC_ONE_CONV_START ((uint32_t)0x00810001UL) |
Offset from AFE_ADC_ONE Base Address: 0x810001
#define MXC_R_AFE_ADC_ONE_CTRL ((uint32_t)0x00890001UL) |
Offset from AFE_ADC_ONE Base Address: 0x890001
#define MXC_R_AFE_ADC_ONE_DATA0 ((uint32_t)0x00B00003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB00003
#define MXC_R_AFE_ADC_ONE_DATA1 ((uint32_t)0x00B10003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB10003
#define MXC_R_AFE_ADC_ONE_DATA2 ((uint32_t)0x00B20003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB20003
#define MXC_R_AFE_ADC_ONE_DATA3 ((uint32_t)0x00B30003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB30003
#define MXC_R_AFE_ADC_ONE_DATA4 ((uint32_t)0x00B40003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB40003
#define MXC_R_AFE_ADC_ONE_DATA5 ((uint32_t)0x00B50003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB50003
#define MXC_R_AFE_ADC_ONE_DATA6 ((uint32_t)0x00B60003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB60003
#define MXC_R_AFE_ADC_ONE_DATA7 ((uint32_t)0x00B70003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB70003
#define MXC_R_AFE_ADC_ONE_FILTER ((uint32_t)0x00880001UL) |
Offset from AFE_ADC_ONE Base Address: 0x880001
#define MXC_R_AFE_ADC_ONE_FT_PWORD ((uint32_t)0x00F00001UL) |
Offset from AFE_ADC_ONE Base Address: 0xF00001
#define MXC_R_AFE_ADC_ONE_GP0_CTRL ((uint32_t)0x00840001UL) |
Offset from AFE_ADC_ONE Base Address: 0x840001
#define MXC_R_AFE_ADC_ONE_GP1_CTRL ((uint32_t)0x00850001UL) |
Offset from AFE_ADC_ONE Base Address: 0x850001
#define MXC_R_AFE_ADC_ONE_GP_CONV ((uint32_t)0x00860001UL) |
Offset from AFE_ADC_ONE Base Address: 0x860001
#define MXC_R_AFE_ADC_ONE_GP_SEQ_ADDR ((uint32_t)0x00870001UL) |
Offset from AFE_ADC_ONE Base Address: 0x870001
#define MXC_R_AFE_ADC_ONE_LTHRESH0 ((uint32_t)0x00A00003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA00003
#define MXC_R_AFE_ADC_ONE_LTHRESH1 ((uint32_t)0x00A10003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA10003
#define MXC_R_AFE_ADC_ONE_LTHRESH2 ((uint32_t)0x00A20003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA20003
#define MXC_R_AFE_ADC_ONE_LTHRESH3 ((uint32_t)0x00A30003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA30003
#define MXC_R_AFE_ADC_ONE_LTHRESH4 ((uint32_t)0x00A40003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA40003
#define MXC_R_AFE_ADC_ONE_LTHRESH5 ((uint32_t)0x00A50003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA50003
#define MXC_R_AFE_ADC_ONE_LTHRESH6 ((uint32_t)0x00A60003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA60003
#define MXC_R_AFE_ADC_ONE_LTHRESH7 ((uint32_t)0x00A70003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA70003
#define MXC_R_AFE_ADC_ONE_MUX_CTRL0 ((uint32_t)0x008B0001UL) |
Offset from AFE_ADC_ONE Base Address: 0x8B0001
#define MXC_R_AFE_ADC_ONE_MUX_CTRL1 ((uint32_t)0x008C0001UL) |
Offset from AFE_ADC_ONE Base Address: 0x8C0001
#define MXC_R_AFE_ADC_ONE_MUX_CTRL2 ((uint32_t)0x008D0001UL) |
Offset from AFE_ADC_ONE Base Address: 0x8D0001
#define MXC_R_AFE_ADC_ONE_PART_ID ((uint32_t)0x00910003UL) |
Offset from AFE_ADC_ONE Base Address: 0x910003
#define MXC_R_AFE_ADC_ONE_PD ((uint32_t)0x00800001UL) |
Offset from AFE_ADC_ONE Base Address: 0x800001
#define MXC_R_AFE_ADC_ONE_PGA ((uint32_t)0x008E0001UL) |
Offset from AFE_ADC_ONE Base Address: 0x8E0001
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_1 ((uint32_t)0x00980003UL) |
Offset from AFE_ADC_ONE Base Address: 0x980003
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_128 ((uint32_t)0x009F0003UL) |
Offset from AFE_ADC_ONE Base Address: 0x9F0003
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_16 ((uint32_t)0x009C0003UL) |
Offset from AFE_ADC_ONE Base Address: 0x9C0003
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_2 ((uint32_t)0x00990003UL) |
Offset from AFE_ADC_ONE Base Address: 0x990003
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_32 ((uint32_t)0x009D0003UL) |
Offset from AFE_ADC_ONE Base Address: 0x9D0003
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_4 ((uint32_t)0x009A0003UL) |
Offset from AFE_ADC_ONE Base Address: 0x9A0003
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_64 ((uint32_t)0x009E0003UL) |
Offset from AFE_ADC_ONE Base Address: 0x9E0003
#define MXC_R_AFE_ADC_ONE_SELF_GAIN_8 ((uint32_t)0x009B0003UL) |
Offset from AFE_ADC_ONE Base Address: 0x9B0003
#define MXC_R_AFE_ADC_ONE_SELF_OFF ((uint32_t)0x00970003UL) |
Offset from AFE_ADC_ONE Base Address: 0x970003
#define MXC_R_AFE_ADC_ONE_SEQ_START ((uint32_t)0x00820001UL) |
Offset from AFE_ADC_ONE Base Address: 0x820001
#define MXC_R_AFE_ADC_ONE_SOURCE ((uint32_t)0x008A0001UL) |
Offset from AFE_ADC_ONE Base Address: 0x8A0001
#define MXC_R_AFE_ADC_ONE_STATUS ((uint32_t)0x00B80003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB80003
#define MXC_R_AFE_ADC_ONE_STATUS_IE ((uint32_t)0x00B90003UL) |
Offset from AFE_ADC_ONE Base Address: 0xB90003
#define MXC_R_AFE_ADC_ONE_SYS_CTRL ((uint32_t)0x00FA0001UL) |
Offset from AFE_ADC_ONE Base Address: 0xFA0001
#define MXC_R_AFE_ADC_ONE_SYS_GAIN_A ((uint32_t)0x00950003UL) |
Offset from AFE_ADC_ONE Base Address: 0x950003
#define MXC_R_AFE_ADC_ONE_SYS_GAIN_B ((uint32_t)0x00960003UL) |
Offset from AFE_ADC_ONE Base Address: 0x960003
#define MXC_R_AFE_ADC_ONE_SYS_OFF_A ((uint32_t)0x00930003UL) |
Offset from AFE_ADC_ONE Base Address: 0x930003
#define MXC_R_AFE_ADC_ONE_SYS_OFF_B ((uint32_t)0x00940003UL) |
Offset from AFE_ADC_ONE Base Address: 0x940003
#define MXC_R_AFE_ADC_ONE_SYSC_SEL ((uint32_t)0x00920003UL) |
Offset from AFE_ADC_ONE Base Address: 0x920003
#define MXC_R_AFE_ADC_ONE_TS_CTRL ((uint32_t)0x00FC0001UL) |
Offset from AFE_ADC_ONE Base Address: 0xFC0001
#define MXC_R_AFE_ADC_ONE_UC_0 ((uint32_t)0x00BA0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xBA0002
#define MXC_R_AFE_ADC_ONE_UC_1 ((uint32_t)0x00BB0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xBB0002
#define MXC_R_AFE_ADC_ONE_UC_10 ((uint32_t)0x00C40002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC40002
#define MXC_R_AFE_ADC_ONE_UC_11 ((uint32_t)0x00C50002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC50002
#define MXC_R_AFE_ADC_ONE_UC_12 ((uint32_t)0x00C60002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC60002
#define MXC_R_AFE_ADC_ONE_UC_13 ((uint32_t)0x00C70002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC70002
#define MXC_R_AFE_ADC_ONE_UC_14 ((uint32_t)0x00C80002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC80002
#define MXC_R_AFE_ADC_ONE_UC_15 ((uint32_t)0x00C90002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC90002
#define MXC_R_AFE_ADC_ONE_UC_16 ((uint32_t)0x00CA0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xCA0002
#define MXC_R_AFE_ADC_ONE_UC_17 ((uint32_t)0x00CB0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xCB0002
#define MXC_R_AFE_ADC_ONE_UC_18 ((uint32_t)0x00CC0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xCC0002
#define MXC_R_AFE_ADC_ONE_UC_19 ((uint32_t)0x00CD0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xCD0002
#define MXC_R_AFE_ADC_ONE_UC_2 ((uint32_t)0x00BC0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xBC0002
#define MXC_R_AFE_ADC_ONE_UC_20 ((uint32_t)0x00CE0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xCE0002
#define MXC_R_AFE_ADC_ONE_UC_21 ((uint32_t)0x00CF0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xCF0002
#define MXC_R_AFE_ADC_ONE_UC_22 ((uint32_t)0x00D00002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD00002
#define MXC_R_AFE_ADC_ONE_UC_23 ((uint32_t)0x00D10002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD10002
#define MXC_R_AFE_ADC_ONE_UC_24 ((uint32_t)0x00D20002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD20002
#define MXC_R_AFE_ADC_ONE_UC_25 ((uint32_t)0x00D30002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD30002
#define MXC_R_AFE_ADC_ONE_UC_26 ((uint32_t)0x00D40002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD40002
#define MXC_R_AFE_ADC_ONE_UC_27 ((uint32_t)0x00D50002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD50002
#define MXC_R_AFE_ADC_ONE_UC_28 ((uint32_t)0x00D60002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD60002
#define MXC_R_AFE_ADC_ONE_UC_29 ((uint32_t)0x00D70002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD70002
#define MXC_R_AFE_ADC_ONE_UC_3 ((uint32_t)0x00BD0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xBD0002
#define MXC_R_AFE_ADC_ONE_UC_30 ((uint32_t)0x00D80002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD80002
#define MXC_R_AFE_ADC_ONE_UC_31 ((uint32_t)0x00D90002UL) |
Offset from AFE_ADC_ONE Base Address: 0xD90002
#define MXC_R_AFE_ADC_ONE_UC_32 ((uint32_t)0x00DA0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xDA0002
#define MXC_R_AFE_ADC_ONE_UC_33 ((uint32_t)0x00DB0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xDB0002
#define MXC_R_AFE_ADC_ONE_UC_34 ((uint32_t)0x00DC0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xDC0002
#define MXC_R_AFE_ADC_ONE_UC_35 ((uint32_t)0x00DD0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xDD0002
#define MXC_R_AFE_ADC_ONE_UC_36 ((uint32_t)0x00DE0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xDE0002
#define MXC_R_AFE_ADC_ONE_UC_37 ((uint32_t)0x00DF0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xDF0002
#define MXC_R_AFE_ADC_ONE_UC_38 ((uint32_t)0x00E00002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE00002
#define MXC_R_AFE_ADC_ONE_UC_39 ((uint32_t)0x00E10002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE10002
#define MXC_R_AFE_ADC_ONE_UC_4 ((uint32_t)0x00BE0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xBE0002
#define MXC_R_AFE_ADC_ONE_UC_40 ((uint32_t)0x00E20002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE20002
#define MXC_R_AFE_ADC_ONE_UC_41 ((uint32_t)0x00E30002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE30002
#define MXC_R_AFE_ADC_ONE_UC_42 ((uint32_t)0x00E40002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE40002
#define MXC_R_AFE_ADC_ONE_UC_43 ((uint32_t)0x00E50002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE50002
#define MXC_R_AFE_ADC_ONE_UC_44 ((uint32_t)0x00E60002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE60002
#define MXC_R_AFE_ADC_ONE_UC_45 ((uint32_t)0x00E70002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE70002
#define MXC_R_AFE_ADC_ONE_UC_46 ((uint32_t)0x00E80002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE80002
#define MXC_R_AFE_ADC_ONE_UC_47 ((uint32_t)0x00E90002UL) |
Offset from AFE_ADC_ONE Base Address: 0xE90002
#define MXC_R_AFE_ADC_ONE_UC_48 ((uint32_t)0x00EA0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xEA0002
#define MXC_R_AFE_ADC_ONE_UC_49 ((uint32_t)0x00EB0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xEB0002
#define MXC_R_AFE_ADC_ONE_UC_5 ((uint32_t)0x00BF0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xBF0002
#define MXC_R_AFE_ADC_ONE_UC_50 ((uint32_t)0x00EC0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xEC0002
#define MXC_R_AFE_ADC_ONE_UC_51 ((uint32_t)0x00ED0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xED0002
#define MXC_R_AFE_ADC_ONE_UC_52 ((uint32_t)0x00EE0002UL) |
Offset from AFE_ADC_ONE Base Address: 0xEE0002
#define MXC_R_AFE_ADC_ONE_UC_6 ((uint32_t)0x00C00002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC00002
#define MXC_R_AFE_ADC_ONE_UC_7 ((uint32_t)0x00C10002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC10002
#define MXC_R_AFE_ADC_ONE_UC_8 ((uint32_t)0x00C20002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC20002
#define MXC_R_AFE_ADC_ONE_UC_9 ((uint32_t)0x00C30002UL) |
Offset from AFE_ADC_ONE Base Address: 0xC30002
#define MXC_R_AFE_ADC_ONE_UCADDR ((uint32_t)0x00EF0001UL) |
Offset from AFE_ADC_ONE Base Address: 0xEF0001
#define MXC_R_AFE_ADC_ONE_UTHRESH0 ((uint32_t)0x00A80003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA80003
#define MXC_R_AFE_ADC_ONE_UTHRESH1 ((uint32_t)0x00A90003UL) |
Offset from AFE_ADC_ONE Base Address: 0xA90003
#define MXC_R_AFE_ADC_ONE_UTHRESH2 ((uint32_t)0x00AA0003UL) |
Offset from AFE_ADC_ONE Base Address: 0xAA0003
#define MXC_R_AFE_ADC_ONE_UTHRESH3 ((uint32_t)0x00AB0003UL) |
Offset from AFE_ADC_ONE Base Address: 0xAB0003
#define MXC_R_AFE_ADC_ONE_UTHRESH4 ((uint32_t)0x00AC0003UL) |
Offset from AFE_ADC_ONE Base Address: 0xAC0003
#define MXC_R_AFE_ADC_ONE_UTHRESH5 ((uint32_t)0x00AD0003UL) |
Offset from AFE_ADC_ONE Base Address: 0xAD0003
#define MXC_R_AFE_ADC_ONE_UTHRESH6 ((uint32_t)0x00AE0003UL) |
Offset from AFE_ADC_ONE Base Address: 0xAE0003
#define MXC_R_AFE_ADC_ONE_UTHRESH7 ((uint32_t)0x00AF0003UL) |
Offset from AFE_ADC_ONE Base Address: 0xAF0003
#define MXC_R_AFE_ADC_ONE_WAIT_EXT ((uint32_t)0x008F0001UL) |
Offset from AFE_ADC_ONE Base Address: 0x8F0001
#define MXC_R_AFE_ADC_ONE_WAIT_START ((uint32_t)0x00900001UL) |
Offset from AFE_ADC_ONE Base Address: 0x900001