MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
spi_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the "Software"),
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13  * and/or sell copies of the Software, and to permit persons to whom the
14  * Software is furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included
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18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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23  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25  * OTHER DEALINGS IN THE SOFTWARE.
26  *
27  * Except as contained in this notice, the name of Maxim Integrated
28  * Products, Inc. shall not be used except as stated in the Maxim Integrated
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30  *
31  * The mere transfer of this software does not imply any licenses
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39 
40 #ifndef _SPI_REGS_H_
41 #define _SPI_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  union{
90  __IO uint32_t fifo32;
91  __IO uint16_t fifo16[2];
92  __IO uint8_t fifo8[4];
93  };
94  __IO uint32_t ctrl0;
95  __IO uint32_t ctrl1;
96  __IO uint32_t ctrl2;
97  __IO uint32_t sstime;
98  __IO uint32_t clkctrl;
99  __R uint32_t rsv_0x18;
100  __IO uint32_t dma;
101  __IO uint32_t intfl;
102  __IO uint32_t inten;
103  __IO uint32_t wkfl;
104  __IO uint32_t wken;
105  __I uint32_t stat;
107 
108 /* Register offsets for module SPI */
115  #define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL)
116  #define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL)
117  #define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL)
118  #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL)
119  #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL)
120  #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL)
121  #define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL)
122  #define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL)
123  #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL)
124  #define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL)
125  #define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL)
126  #define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL)
127  #define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL)
128  #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL)
137  #define MXC_F_SPI_FIFO32_DATA_POS 0
138  #define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS))
148  #define MXC_F_SPI_FIFO16_DATA_POS 0
149  #define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS))
159  #define MXC_F_SPI_FIFO8_DATA_POS 0
160  #define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS))
170  #define MXC_F_SPI_CTRL0_EN_POS 0
171  #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS))
173  #define MXC_F_SPI_CTRL0_MST_MODE_POS 1
174  #define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS))
176  #define MXC_F_SPI_CTRL0_SS_IO_POS 4
177  #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS))
179  #define MXC_F_SPI_CTRL0_START_POS 5
180  #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS))
182  #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8
183  #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS))
185  #define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16
186  #define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS))
187  #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL)
188  #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)
189  #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL)
190  #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)
191  #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL)
192  #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)
193  #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL)
194  #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)
204  #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0
205  #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS))
207  #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16
208  #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS))
218  #define MXC_F_SPI_CTRL2_CLKPHA_POS 0
219  #define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS))
221  #define MXC_F_SPI_CTRL2_CLKPOL_POS 1
222  #define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS))
224  #define MXC_F_SPI_CTRL2_NUMBITS_POS 8
225  #define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS))
226  #define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL)
227  #define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS)
229  #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12
230  #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS))
231  #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL)
232  #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)
233  #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL)
234  #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)
235  #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL)
236  #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)
238  #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15
239  #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS))
241  #define MXC_F_SPI_CTRL2_SS_POL_POS 16
242  #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS))
243  #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL)
244  #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
245  #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL)
246  #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
247  #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL)
248  #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
249  #define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL)
250  #define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
260  #define MXC_F_SPI_SSTIME_PRE_POS 0
261  #define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS))
262  #define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL)
263  #define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS)
265  #define MXC_F_SPI_SSTIME_POST_POS 8
266  #define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS))
267  #define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL)
268  #define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS)
270  #define MXC_F_SPI_SSTIME_INACT_POS 16
271  #define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS))
272  #define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL)
273  #define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS)
283  #define MXC_F_SPI_CLKCTRL_LO_POS 0
284  #define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS))
285  #define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL)
286  #define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS)
288  #define MXC_F_SPI_CLKCTRL_HI_POS 8
289  #define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS))
290  #define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL)
291  #define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS)
293  #define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16
294  #define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS))
304  #define MXC_F_SPI_DMA_TX_THD_VAL_POS 0
305  #define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS))
307  #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6
308  #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS))
310  #define MXC_F_SPI_DMA_TX_FLUSH_POS 7
311  #define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS))
313  #define MXC_F_SPI_DMA_TX_LVL_POS 8
314  #define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS))
316  #define MXC_F_SPI_DMA_DMA_TX_EN_POS 15
317  #define MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS))
319  #define MXC_F_SPI_DMA_RX_THD_VAL_POS 16
320  #define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS))
322  #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22
323  #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS))
325  #define MXC_F_SPI_DMA_RX_FLUSH_POS 23
326  #define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS))
328  #define MXC_F_SPI_DMA_RX_LVL_POS 24
329  #define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS))
331  #define MXC_F_SPI_DMA_DMA_RX_EN_POS 31
332  #define MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS))
343  #define MXC_F_SPI_INTFL_TX_THD_POS 0
344  #define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS))
346  #define MXC_F_SPI_INTFL_TX_EM_POS 1
347  #define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS))
349  #define MXC_F_SPI_INTFL_RX_THD_POS 2
350  #define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS))
352  #define MXC_F_SPI_INTFL_RX_FULL_POS 3
353  #define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS))
355  #define MXC_F_SPI_INTFL_SSA_POS 4
356  #define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS))
358  #define MXC_F_SPI_INTFL_SSD_POS 5
359  #define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS))
361  #define MXC_F_SPI_INTFL_FAULT_POS 8
362  #define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS))
364  #define MXC_F_SPI_INTFL_ABORT_POS 9
365  #define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS))
367  #define MXC_F_SPI_INTFL_MST_DONE_POS 11
368  #define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS))
370  #define MXC_F_SPI_INTFL_TX_OV_POS 12
371  #define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS))
373  #define MXC_F_SPI_INTFL_TX_UN_POS 13
374  #define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS))
376  #define MXC_F_SPI_INTFL_RX_OV_POS 14
377  #define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS))
379  #define MXC_F_SPI_INTFL_RX_UN_POS 15
380  #define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS))
390  #define MXC_F_SPI_INTEN_TX_THD_POS 0
391  #define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS))
393  #define MXC_F_SPI_INTEN_TX_EM_POS 1
394  #define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS))
396  #define MXC_F_SPI_INTEN_RX_THD_POS 2
397  #define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS))
399  #define MXC_F_SPI_INTEN_RX_FULL_POS 3
400  #define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS))
402  #define MXC_F_SPI_INTEN_SSA_POS 4
403  #define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS))
405  #define MXC_F_SPI_INTEN_SSD_POS 5
406  #define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS))
408  #define MXC_F_SPI_INTEN_FAULT_POS 8
409  #define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS))
411  #define MXC_F_SPI_INTEN_ABORT_POS 9
412  #define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS))
414  #define MXC_F_SPI_INTEN_MST_DONE_POS 11
415  #define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS))
417  #define MXC_F_SPI_INTEN_TX_OV_POS 12
418  #define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS))
420  #define MXC_F_SPI_INTEN_TX_UN_POS 13
421  #define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS))
423  #define MXC_F_SPI_INTEN_RX_OV_POS 14
424  #define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS))
426  #define MXC_F_SPI_INTEN_RX_UN_POS 15
427  #define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS))
437  #define MXC_F_SPI_WKFL_TX_THD_POS 0
438  #define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS))
440  #define MXC_F_SPI_WKFL_TX_EM_POS 1
441  #define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS))
443  #define MXC_F_SPI_WKFL_RX_THD_POS 2
444  #define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS))
446  #define MXC_F_SPI_WKFL_RX_FULL_POS 3
447  #define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS))
457  #define MXC_F_SPI_WKEN_TX_THD_POS 0
458  #define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS))
460  #define MXC_F_SPI_WKEN_TX_EM_POS 1
461  #define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS))
463  #define MXC_F_SPI_WKEN_RX_THD_POS 2
464  #define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS))
466  #define MXC_F_SPI_WKEN_RX_FULL_POS 3
467  #define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS))
477  #define MXC_F_SPI_STAT_BUSY_POS 0
478  #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS))
482 #ifdef __cplusplus
483 }
484 #endif
485 
486 #endif /* _SPI_REGS_H_ */
mxc_spi_regs_t::wkfl
__IO uint32_t wkfl
Definition: spi_regs.h:103
mxc_spi_regs_t::fifo32
__IO uint32_t fifo32
Definition: spi_regs.h:90
mxc_spi_regs_t
Definition: spi_regs.h:88
mxc_spi_regs_t::sstime
__IO uint32_t sstime
Definition: spi_regs.h:97
mxc_spi_regs_t::ctrl1
__IO uint32_t ctrl1
Definition: spi_regs.h:95
mxc_spi_regs_t::intfl
__IO uint32_t intfl
Definition: spi_regs.h:101
mxc_spi_regs_t::ctrl2
__IO uint32_t ctrl2
Definition: spi_regs.h:96
mxc_spi_regs_t::inten
__IO uint32_t inten
Definition: spi_regs.h:102
mxc_spi_regs_t::ctrl0
__IO uint32_t ctrl0
Definition: spi_regs.h:94
mxc_spi_regs_t::stat
__I uint32_t stat
Definition: spi_regs.h:105
mxc_spi_regs_t::wken
__IO uint32_t wken
Definition: spi_regs.h:104
mxc_spi_regs_t::clkctrl
__IO uint32_t clkctrl
Definition: spi_regs.h:98
mxc_spi_regs_t::dma
__IO uint32_t dma
Definition: spi_regs.h:100