MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
dma_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the "Software"),
11  * to deal in the Software without restriction, including without limitation
12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13  * and/or sell copies of the Software, and to permit persons to whom the
14  * Software is furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included
17  * in all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
23  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25  * OTHER DEALINGS IN THE SOFTWARE.
26  *
27  * Except as contained in this notice, the name of Maxim Integrated
28  * Products, Inc. shall not be used except as stated in the Maxim Integrated
29  * Products, Inc. Branding Policy.
30  *
31  * The mere transfer of this software does not imply any licenses
32  * of trade secrets, proprietary technology, copyrights, patents,
33  * trademarks, maskwork rights, or any other form of intellectual
34  * property whatsoever. Maxim Integrated Products, Inc. retains all
35  * ownership rights.
36  *
37  *
38  *************************************************************************** */
39 
40 #ifndef _DMA_REGS_H_
41 #define _DMA_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t ctrl;
90  __IO uint32_t status;
91  __IO uint32_t src;
92  __IO uint32_t dst;
93  __IO uint32_t cnt;
94  __IO uint32_t srcrld;
95  __IO uint32_t dstrld;
96  __IO uint32_t cntrld;
98 
103 typedef struct {
104  __IO uint32_t inten;
105  __I uint32_t intfl;
106  __R uint32_t rsv_0x8_0xff[62];
107  __IO mxc_dma_ch_regs_t ch[8];
109 
110 /* Register offsets for module DMA */
117  #define MXC_R_DMA_CTRL ((uint32_t)0x00000100UL)
118  #define MXC_R_DMA_STATUS ((uint32_t)0x00000104UL)
119  #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL)
120  #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL)
121  #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL)
122  #define MXC_R_DMA_SRCRLD ((uint32_t)0x00000114UL)
123  #define MXC_R_DMA_DSTRLD ((uint32_t)0x00000118UL)
124  #define MXC_R_DMA_CNTRLD ((uint32_t)0x0000011CUL)
125  #define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL)
126  #define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL)
127  #define MXC_R_DMA_CH ((uint32_t)0x00000100UL)
136  #define MXC_F_DMA_INTEN_CH0_POS 0
137  #define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS))
139  #define MXC_F_DMA_INTEN_CH1_POS 1
140  #define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS))
142  #define MXC_F_DMA_INTEN_CH2_POS 2
143  #define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS))
145  #define MXC_F_DMA_INTEN_CH3_POS 3
146  #define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS))
148  #define MXC_F_DMA_INTEN_CH4_POS 4
149  #define MXC_F_DMA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS))
151  #define MXC_F_DMA_INTEN_CH5_POS 5
152  #define MXC_F_DMA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS))
154  #define MXC_F_DMA_INTEN_CH6_POS 6
155  #define MXC_F_DMA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS))
157  #define MXC_F_DMA_INTEN_CH7_POS 7
158  #define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS))
168  #define MXC_F_DMA_INTFL_CH0_POS 0
169  #define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS))
171  #define MXC_F_DMA_INTFL_CH1_POS 1
172  #define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS))
174  #define MXC_F_DMA_INTFL_CH2_POS 2
175  #define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS))
177  #define MXC_F_DMA_INTFL_CH3_POS 3
178  #define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS))
180  #define MXC_F_DMA_INTFL_CH4_POS 4
181  #define MXC_F_DMA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS))
183  #define MXC_F_DMA_INTFL_CH5_POS 5
184  #define MXC_F_DMA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS))
186  #define MXC_F_DMA_INTFL_CH6_POS 6
187  #define MXC_F_DMA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS))
189  #define MXC_F_DMA_INTFL_CH7_POS 7
190  #define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS))
200  #define MXC_F_DMA_CTRL_EN_POS 0
201  #define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS))
203  #define MXC_F_DMA_CTRL_RLDEN_POS 1
204  #define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS))
206  #define MXC_F_DMA_CTRL_PRI_POS 2
207  #define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS))
208  #define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL)
209  #define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS)
210  #define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL)
211  #define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS)
212  #define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL)
213  #define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS)
214  #define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL)
215  #define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS)
217  #define MXC_F_DMA_CTRL_REQUEST_POS 4
218  #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS))
219  #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL)
220  #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS)
221  #define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL)
222  #define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS)
223  #define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL)
224  #define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS)
225  #define MXC_V_DMA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL)
226  #define MXC_S_DMA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS)
227  #define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL)
228  #define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS)
229  #define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL)
230  #define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS)
231  #define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL)
232  #define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS)
233  #define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL)
234  #define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS)
235  #define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL)
236  #define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS)
237  #define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL)
238  #define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS)
239  #define MXC_V_DMA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL)
240  #define MXC_S_DMA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS)
241  #define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL)
242  #define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS)
243  #define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL)
244  #define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS)
245  #define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL)
246  #define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS)
247  #define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL)
248  #define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS)
249  #define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL)
250  #define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS)
251  #define MXC_V_DMA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL)
252  #define MXC_S_DMA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS)
253  #define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL)
254  #define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS)
255  #define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL)
256  #define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS)
257  #define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL)
258  #define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS)
259  #define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL)
260  #define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS)
261  #define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL)
262  #define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS)
263  #define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL)
264  #define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS)
265  #define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL)
266  #define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS)
267  #define MXC_V_DMA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL)
268  #define MXC_S_DMA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS)
269  #define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL)
270  #define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS)
271  #define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL)
272  #define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS)
273  #define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL)
274  #define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS)
276  #define MXC_F_DMA_CTRL_TO_WAIT_POS 10
277  #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS))
279  #define MXC_F_DMA_CTRL_TO_PER_POS 11
280  #define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS))
281  #define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL)
282  #define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS)
283  #define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL)
284  #define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS)
285  #define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL)
286  #define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS)
287  #define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL)
288  #define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS)
289  #define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL)
290  #define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS)
291  #define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL)
292  #define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS)
293  #define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL)
294  #define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS)
295  #define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL)
296  #define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS)
298  #define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14
299  #define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS))
300  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL)
301  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
302  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL)
303  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
304  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL)
305  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
306  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL)
307  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
309  #define MXC_F_DMA_CTRL_SRCWD_POS 16
310  #define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS))
311  #define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL)
312  #define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS)
313  #define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL)
314  #define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS)
315  #define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL)
316  #define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS)
318  #define MXC_F_DMA_CTRL_SRCINC_POS 18
319  #define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS))
321  #define MXC_F_DMA_CTRL_DSTWD_POS 20
322  #define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS))
323  #define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL)
324  #define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS)
325  #define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL)
326  #define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS)
327  #define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL)
328  #define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS)
330  #define MXC_F_DMA_CTRL_DSTINC_POS 22
331  #define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS))
333  #define MXC_F_DMA_CTRL_BURST_SIZE_POS 24
334  #define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS))
336  #define MXC_F_DMA_CTRL_DIS_IE_POS 30
337  #define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS))
339  #define MXC_F_DMA_CTRL_CTZ_IE_POS 31
340  #define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS))
350  #define MXC_F_DMA_STATUS_STATUS_POS 0
351  #define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS))
353  #define MXC_F_DMA_STATUS_IPEND_POS 1
354  #define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS))
356  #define MXC_F_DMA_STATUS_CTZ_IF_POS 2
357  #define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS))
359  #define MXC_F_DMA_STATUS_RLD_IF_POS 3
360  #define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS))
362  #define MXC_F_DMA_STATUS_BUS_ERR_POS 4
363  #define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS))
365  #define MXC_F_DMA_STATUS_TO_IF_POS 6
366  #define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS))
380  #define MXC_F_DMA_SRC_ADDR_POS 0
381  #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS))
395  #define MXC_F_DMA_DST_ADDR_POS 0
396  #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS))
409  #define MXC_F_DMA_CNT_CNT_POS 0
410  #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS))
421  #define MXC_F_DMA_SRCRLD_ADDR_POS 0
422  #define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS))
433  #define MXC_F_DMA_DSTRLD_ADDR_POS 0
434  #define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS))
444  #define MXC_F_DMA_CNTRLD_CNT_POS 0
445  #define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS))
447  #define MXC_F_DMA_CNTRLD_EN_POS 31
448  #define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS))
452 #ifdef __cplusplus
453 }
454 #endif
455 
456 #endif /* _DMA_REGS_H_ */
mxc_dma_ch_regs_t::dstrld
__IO uint32_t dstrld
Definition: dma_regs.h:95
mxc_dma_regs_t
Definition: dma_regs.h:103
mxc_dma_regs_t::intfl
__I uint32_t intfl
Definition: dma_regs.h:105
mxc_dma_ch_regs_t::dst
__IO uint32_t dst
Definition: dma_regs.h:92
mxc_dma_ch_regs_t
Definition: dma_regs.h:88
mxc_dma_ch_regs_t::src
__IO uint32_t src
Definition: dma_regs.h:91
mxc_dma_ch_regs_t::ctrl
__IO uint32_t ctrl
Definition: dma_regs.h:89
mxc_dma_ch_regs_t::cntrld
__IO uint32_t cntrld
Definition: dma_regs.h:96
mxc_dma_ch_regs_t::srcrld
__IO uint32_t srcrld
Definition: dma_regs.h:94
mxc_dma_ch_regs_t::cnt
__IO uint32_t cnt
Definition: dma_regs.h:93
mxc_dma_ch_regs_t::status
__IO uint32_t status
Definition: dma_regs.h:90
mxc_dma_regs_t::inten
__IO uint32_t inten
Definition: dma_regs.h:104