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MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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50 #if defined (__ICCARM__)
51 #pragma system_include
54 #if defined (__CC_ARM)
65 #define __I volatile const
71 #define __R volatile const
117 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL)
118 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL)
119 #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL)
120 #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL)
121 #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL)
122 #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL)
123 #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL)
124 #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL)
125 #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL)
126 #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL)
127 #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL)
128 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL)
129 #define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL)
130 #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL)
131 #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL)
132 #define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL)
133 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL)
134 #define MXC_R_I2C_SLAVE ((uint32_t)0x00000044UL)
135 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL)
144 #define MXC_F_I2C_CTRL_EN_POS 0
145 #define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS))
147 #define MXC_F_I2C_CTRL_MST_MODE_POS 1
148 #define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS))
150 #define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2
151 #define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS))
153 #define MXC_F_I2C_CTRL_IRXM_EN_POS 3
154 #define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS))
156 #define MXC_F_I2C_CTRL_IRXM_ACK_POS 4
157 #define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS))
159 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6
160 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS))
162 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7
163 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS))
165 #define MXC_F_I2C_CTRL_SCL_POS 8
166 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS))
168 #define MXC_F_I2C_CTRL_SDA_POS 9
169 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS))
171 #define MXC_F_I2C_CTRL_BB_MODE_POS 10
172 #define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS))
174 #define MXC_F_I2C_CTRL_READ_POS 11
175 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS))
177 #define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12
178 #define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS))
180 #define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13
181 #define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS))
183 #define MXC_F_I2C_CTRL_HS_EN_POS 15
184 #define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS))
194 #define MXC_F_I2C_STATUS_BUSY_POS 0
195 #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS))
197 #define MXC_F_I2C_STATUS_RX_EM_POS 1
198 #define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS))
200 #define MXC_F_I2C_STATUS_RX_FULL_POS 2
201 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS))
203 #define MXC_F_I2C_STATUS_TX_EM_POS 3
204 #define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS))
206 #define MXC_F_I2C_STATUS_TX_FULL_POS 4
207 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS))
209 #define MXC_F_I2C_STATUS_MST_BUSY_POS 5
210 #define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS))
220 #define MXC_F_I2C_INTFL0_DONE_POS 0
221 #define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS))
223 #define MXC_F_I2C_INTFL0_IRXM_POS 1
224 #define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS))
226 #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2
227 #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS))
229 #define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3
230 #define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS))
232 #define MXC_F_I2C_INTFL0_RX_THD_POS 4
233 #define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS))
235 #define MXC_F_I2C_INTFL0_TX_THD_POS 5
236 #define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS))
238 #define MXC_F_I2C_INTFL0_STOP_POS 6
239 #define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS))
241 #define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7
242 #define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS))
244 #define MXC_F_I2C_INTFL0_ARB_ERR_POS 8
245 #define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS))
247 #define MXC_F_I2C_INTFL0_TO_ERR_POS 9
248 #define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS))
250 #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10
251 #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS))
253 #define MXC_F_I2C_INTFL0_DATA_ERR_POS 11
254 #define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS))
256 #define MXC_F_I2C_INTFL0_DNR_ERR_POS 12
257 #define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS))
259 #define MXC_F_I2C_INTFL0_START_ERR_POS 13
260 #define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS))
262 #define MXC_F_I2C_INTFL0_STOP_ERR_POS 14
263 #define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS))
265 #define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15
266 #define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS))
268 #define MXC_F_I2C_INTFL0_MAMI_POS 16
269 #define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS))
271 #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22
272 #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS))
274 #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23
275 #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS))
285 #define MXC_F_I2C_INTEN0_DONE_POS 0
286 #define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS))
288 #define MXC_F_I2C_INTEN0_IRXM_POS 1
289 #define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS))
291 #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2
292 #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS))
294 #define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3
295 #define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS))
297 #define MXC_F_I2C_INTEN0_RX_THD_POS 4
298 #define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS))
300 #define MXC_F_I2C_INTEN0_TX_THD_POS 5
301 #define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS))
303 #define MXC_F_I2C_INTEN0_STOP_POS 6
304 #define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS))
306 #define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7
307 #define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS))
309 #define MXC_F_I2C_INTEN0_ARB_ERR_POS 8
310 #define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS))
312 #define MXC_F_I2C_INTEN0_TO_ERR_POS 9
313 #define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS))
315 #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10
316 #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS))
318 #define MXC_F_I2C_INTEN0_DATA_ERR_POS 11
319 #define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS))
321 #define MXC_F_I2C_INTEN0_DNR_ERR_POS 12
322 #define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS))
324 #define MXC_F_I2C_INTEN0_START_ERR_POS 13
325 #define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS))
327 #define MXC_F_I2C_INTEN0_STOP_ERR_POS 14
328 #define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS))
330 #define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15
331 #define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS))
333 #define MXC_F_I2C_INTEN0_MAMI_POS 16
334 #define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS))
336 #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22
337 #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS))
339 #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23
340 #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS))
350 #define MXC_F_I2C_INTFL1_RX_OV_POS 0
351 #define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS))
353 #define MXC_F_I2C_INTFL1_TX_UN_POS 1
354 #define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS))
356 #define MXC_F_I2C_INTFL1_START_POS 2
357 #define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS))
367 #define MXC_F_I2C_INTEN1_RX_OV_POS 0
368 #define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS))
370 #define MXC_F_I2C_INTEN1_TX_UN_POS 1
371 #define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS))
373 #define MXC_F_I2C_INTEN1_START_POS 2
374 #define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS))
384 #define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0
385 #define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS))
387 #define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8
388 #define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS))
398 #define MXC_F_I2C_RXCTRL0_DNR_POS 0
399 #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS))
401 #define MXC_F_I2C_RXCTRL0_FLUSH_POS 7
402 #define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS))
404 #define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8
405 #define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS))
415 #define MXC_F_I2C_RXCTRL1_CNT_POS 0
416 #define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS))
418 #define MXC_F_I2C_RXCTRL1_LVL_POS 8
419 #define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS))
429 #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0
430 #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS))
432 #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1
433 #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS))
435 #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2
436 #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS))
438 #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3
439 #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS))
441 #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4
442 #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS))
444 #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5
445 #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS))
447 #define MXC_F_I2C_TXCTRL0_FLUSH_POS 7
448 #define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS))
450 #define MXC_F_I2C_TXCTRL0_THD_LVL_POS 8
451 #define MXC_F_I2C_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_LVL_POS))
461 #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0
462 #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS))
464 #define MXC_F_I2C_TXCTRL1_LVL_POS 8
465 #define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS))
475 #define MXC_F_I2C_FIFO_DATA_POS 0
476 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS))
486 #define MXC_F_I2C_MSTCTRL_START_POS 0
487 #define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS))
489 #define MXC_F_I2C_MSTCTRL_RESTART_POS 1
490 #define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS))
492 #define MXC_F_I2C_MSTCTRL_STOP_POS 2
493 #define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS))
495 #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7
496 #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS))
506 #define MXC_F_I2C_CLKLO_LO_POS 0
507 #define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS))
517 #define MXC_F_I2C_CLKHI_HI_POS 0
518 #define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS))
528 #define MXC_F_I2C_HSCLK_LO_POS 0
529 #define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS))
531 #define MXC_F_I2C_HSCLK_HI_POS 8
532 #define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS))
542 #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0
543 #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS))
553 #define MXC_F_I2C_SLAVE_ADDR_POS 0
554 #define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS))
556 #define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15
557 #define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS))
567 #define MXC_F_I2C_DMA_TX_EN_POS 0
568 #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS))
570 #define MXC_F_I2C_DMA_RX_EN_POS 1
571 #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS))
__IO uint32_t txctrl1
Definition: i2c_regs.h:99
__IO uint32_t timeout
Definition: i2c_regs.h:105
__IO uint32_t txctrl0
Definition: i2c_regs.h:98
__IO uint32_t fifolen
Definition: i2c_regs.h:95
__IO uint32_t rxctrl0
Definition: i2c_regs.h:96
__IO uint32_t intfl0
Definition: i2c_regs.h:91
__IO uint32_t fifo
Definition: i2c_regs.h:100
__IO uint32_t status
Definition: i2c_regs.h:90
__IO uint32_t clklo
Definition: i2c_regs.h:102
__IO uint32_t rxctrl1
Definition: i2c_regs.h:97
__IO uint32_t mstctrl
Definition: i2c_regs.h:101
__IO uint32_t hsclk
Definition: i2c_regs.h:104
__IO uint32_t intfl1
Definition: i2c_regs.h:93
__IO uint32_t clkhi
Definition: i2c_regs.h:103
__IO uint32_t slave
Definition: i2c_regs.h:106
__IO uint32_t inten0
Definition: i2c_regs.h:92
__IO uint32_t dma
Definition: i2c_regs.h:107
Definition: i2c_regs.h:88
__IO uint32_t inten1
Definition: i2c_regs.h:94
__IO uint32_t ctrl
Definition: i2c_regs.h:89