![]() |
MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
|
Macros | |
#define | MXC_R_AFE_ADC_ZERO_PD ((uint32_t)0x00000001UL) |
#define | MXC_R_AFE_ADC_ZERO_CONV_START ((uint32_t)0x00010001UL) |
#define | MXC_R_AFE_ADC_ZERO_SEQ_START ((uint32_t)0x00020001UL) |
#define | MXC_R_AFE_ADC_ZERO_CAL_START ((uint32_t)0x00030001UL) |
#define | MXC_R_AFE_ADC_ZERO_GP0_CTRL ((uint32_t)0x00040001UL) |
#define | MXC_R_AFE_ADC_ZERO_GP1_CTRL ((uint32_t)0x00050001UL) |
#define | MXC_R_AFE_ADC_ZERO_GP_CONV ((uint32_t)0x00060001UL) |
#define | MXC_R_AFE_ADC_ZERO_GP_SEQ_ADDR ((uint32_t)0x00070001UL) |
#define | MXC_R_AFE_ADC_ZERO_FILTER ((uint32_t)0x00080001UL) |
#define | MXC_R_AFE_ADC_ZERO_CTRL ((uint32_t)0x00090001UL) |
#define | MXC_R_AFE_ADC_ZERO_SOURCE ((uint32_t)0x000A0001UL) |
#define | MXC_R_AFE_ADC_ZERO_MUX_CTRL0 ((uint32_t)0x000B0001UL) |
#define | MXC_R_AFE_ADC_ZERO_MUX_CTRL1 ((uint32_t)0x000C0001UL) |
#define | MXC_R_AFE_ADC_ZERO_MUX_CTRL2 ((uint32_t)0x000D0001UL) |
#define | MXC_R_AFE_ADC_ZERO_PGA ((uint32_t)0x000E0001UL) |
#define | MXC_R_AFE_ADC_ZERO_WAIT_EXT ((uint32_t)0x000F0001UL) |
#define | MXC_R_AFE_ADC_ZERO_WAIT_START ((uint32_t)0x00100001UL) |
#define | MXC_R_AFE_ADC_ZERO_PART_ID ((uint32_t)0x00110003UL) |
#define | MXC_R_AFE_ADC_ZERO_SYSC_SEL ((uint32_t)0x00120003UL) |
#define | MXC_R_AFE_ADC_ZERO_SYS_OFF_A ((uint32_t)0x00130003UL) |
#define | MXC_R_AFE_ADC_ZERO_SYS_OFF_B ((uint32_t)0x00140003UL) |
#define | MXC_R_AFE_ADC_ZERO_SYS_GAIN_A ((uint32_t)0x00150003UL) |
#define | MXC_R_AFE_ADC_ZERO_SYS_GAIN_B ((uint32_t)0x00160003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_OFF ((uint32_t)0x00170003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_1 ((uint32_t)0x00180003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_2 ((uint32_t)0x00190003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_4 ((uint32_t)0x001A0003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_8 ((uint32_t)0x001B0003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_16 ((uint32_t)0x001C0003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_32 ((uint32_t)0x001D0003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_64 ((uint32_t)0x001E0003UL) |
#define | MXC_R_AFE_ADC_ZERO_SELF_GAIN_128 ((uint32_t)0x001F0003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH0 ((uint32_t)0x00200003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH1 ((uint32_t)0x00210003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH2 ((uint32_t)0x00220003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH3 ((uint32_t)0x00230003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH4 ((uint32_t)0x00240003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH5 ((uint32_t)0x00250003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH6 ((uint32_t)0x00260003UL) |
#define | MXC_R_AFE_ADC_ZERO_LTHRESH7 ((uint32_t)0x00270003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH0 ((uint32_t)0x00280003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH1 ((uint32_t)0x00290003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH2 ((uint32_t)0x002A0003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH3 ((uint32_t)0x002B0003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH4 ((uint32_t)0x002C0003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH5 ((uint32_t)0x002D0003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH6 ((uint32_t)0x002E0003UL) |
#define | MXC_R_AFE_ADC_ZERO_UTHRESH7 ((uint32_t)0x002F0003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA0 ((uint32_t)0x00300003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA1 ((uint32_t)0x00310003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA2 ((uint32_t)0x00320003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA3 ((uint32_t)0x00330003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA4 ((uint32_t)0x00340003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA5 ((uint32_t)0x00350003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA6 ((uint32_t)0x00360003UL) |
#define | MXC_R_AFE_ADC_ZERO_DATA7 ((uint32_t)0x00370003UL) |
#define | MXC_R_AFE_ADC_ZERO_STATUS ((uint32_t)0x00380003UL) |
#define | MXC_R_AFE_ADC_ZERO_STATUS_IE ((uint32_t)0x00390003UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_0 ((uint32_t)0x003A0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_1 ((uint32_t)0x003B0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_2 ((uint32_t)0x003C0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_3 ((uint32_t)0x003D0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_4 ((uint32_t)0x003E0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_5 ((uint32_t)0x003F0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_6 ((uint32_t)0x00400002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_7 ((uint32_t)0x00410002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_8 ((uint32_t)0x00420002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_9 ((uint32_t)0x00430002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_10 ((uint32_t)0x00440002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_11 ((uint32_t)0x00450002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_12 ((uint32_t)0x00460002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_13 ((uint32_t)0x00470002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_14 ((uint32_t)0x00480002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_15 ((uint32_t)0x00490002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_16 ((uint32_t)0x004A0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_17 ((uint32_t)0x004B0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_18 ((uint32_t)0x004C0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_19 ((uint32_t)0x004D0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_20 ((uint32_t)0x004E0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_21 ((uint32_t)0x004F0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_22 ((uint32_t)0x00500002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_23 ((uint32_t)0x00510002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_24 ((uint32_t)0x00520002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_25 ((uint32_t)0x00530002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_26 ((uint32_t)0x00540002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_27 ((uint32_t)0x00550002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_28 ((uint32_t)0x00560002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_29 ((uint32_t)0x00570002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_30 ((uint32_t)0x00580002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_31 ((uint32_t)0x00590002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_32 ((uint32_t)0x005A0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_33 ((uint32_t)0x005B0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_34 ((uint32_t)0x005C0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_35 ((uint32_t)0x005D0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_36 ((uint32_t)0x005E0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_37 ((uint32_t)0x005F0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_38 ((uint32_t)0x00600002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_39 ((uint32_t)0x00610002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_40 ((uint32_t)0x00620002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_41 ((uint32_t)0x00630002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_42 ((uint32_t)0x00640002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_43 ((uint32_t)0x00650002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_44 ((uint32_t)0x00660002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_45 ((uint32_t)0x00670002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_46 ((uint32_t)0x00680002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_47 ((uint32_t)0x00690002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_48 ((uint32_t)0x006A0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_49 ((uint32_t)0x006B0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_50 ((uint32_t)0x006C0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_51 ((uint32_t)0x006D0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UC_52 ((uint32_t)0x006E0002UL) |
#define | MXC_R_AFE_ADC_ZERO_UCADDR ((uint32_t)0x006F0001UL) |
#define | MXC_R_AFE_ADC_ZERO_FT_PWORD ((uint32_t)0x00700001UL) |
#define | MXC_R_AFE_ADC_ZERO_ADC_TRIM0 ((uint32_t)0x00770003UL) |
#define | MXC_R_AFE_ADC_ZERO_ADC_TRIM1 ((uint32_t)0x00780002UL) |
#define | MXC_R_AFE_ADC_ZERO_ANA_TRIM ((uint32_t)0x00790002UL) |
#define | MXC_R_AFE_ADC_ZERO_SYS_CTRL ((uint32_t)0x007A0001UL) |
#define | MXC_R_AFE_ADC_ZERO_TS_CTRL ((uint32_t)0x007C0001UL) |
AFE_ADC_ZERO Peripheral Register Offsets from the AFE_ADC_ZERO Base Peripheral Address.
#define MXC_R_AFE_ADC_ZERO_ADC_TRIM0 ((uint32_t)0x00770003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x770003
#define MXC_R_AFE_ADC_ZERO_ADC_TRIM1 ((uint32_t)0x00780002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x780002
#define MXC_R_AFE_ADC_ZERO_ANA_TRIM ((uint32_t)0x00790002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x790002
#define MXC_R_AFE_ADC_ZERO_CAL_START ((uint32_t)0x00030001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x30001
#define MXC_R_AFE_ADC_ZERO_CONV_START ((uint32_t)0x00010001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x10001
#define MXC_R_AFE_ADC_ZERO_CTRL ((uint32_t)0x00090001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x90001
#define MXC_R_AFE_ADC_ZERO_DATA0 ((uint32_t)0x00300003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x300003
#define MXC_R_AFE_ADC_ZERO_DATA1 ((uint32_t)0x00310003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x310003
#define MXC_R_AFE_ADC_ZERO_DATA2 ((uint32_t)0x00320003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x320003
#define MXC_R_AFE_ADC_ZERO_DATA3 ((uint32_t)0x00330003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x330003
#define MXC_R_AFE_ADC_ZERO_DATA4 ((uint32_t)0x00340003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x340003
#define MXC_R_AFE_ADC_ZERO_DATA5 ((uint32_t)0x00350003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x350003
#define MXC_R_AFE_ADC_ZERO_DATA6 ((uint32_t)0x00360003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x360003
#define MXC_R_AFE_ADC_ZERO_DATA7 ((uint32_t)0x00370003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x370003
#define MXC_R_AFE_ADC_ZERO_FILTER ((uint32_t)0x00080001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x80001
#define MXC_R_AFE_ADC_ZERO_FT_PWORD ((uint32_t)0x00700001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x700001
#define MXC_R_AFE_ADC_ZERO_GP0_CTRL ((uint32_t)0x00040001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x40001
#define MXC_R_AFE_ADC_ZERO_GP1_CTRL ((uint32_t)0x00050001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x50001
#define MXC_R_AFE_ADC_ZERO_GP_CONV ((uint32_t)0x00060001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x60001
#define MXC_R_AFE_ADC_ZERO_GP_SEQ_ADDR ((uint32_t)0x00070001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x70001
#define MXC_R_AFE_ADC_ZERO_LTHRESH0 ((uint32_t)0x00200003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x200003
#define MXC_R_AFE_ADC_ZERO_LTHRESH1 ((uint32_t)0x00210003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x210003
#define MXC_R_AFE_ADC_ZERO_LTHRESH2 ((uint32_t)0x00220003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x220003
#define MXC_R_AFE_ADC_ZERO_LTHRESH3 ((uint32_t)0x00230003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x230003
#define MXC_R_AFE_ADC_ZERO_LTHRESH4 ((uint32_t)0x00240003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x240003
#define MXC_R_AFE_ADC_ZERO_LTHRESH5 ((uint32_t)0x00250003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x250003
#define MXC_R_AFE_ADC_ZERO_LTHRESH6 ((uint32_t)0x00260003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x260003
#define MXC_R_AFE_ADC_ZERO_LTHRESH7 ((uint32_t)0x00270003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x270003
#define MXC_R_AFE_ADC_ZERO_MUX_CTRL0 ((uint32_t)0x000B0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0xB0001
#define MXC_R_AFE_ADC_ZERO_MUX_CTRL1 ((uint32_t)0x000C0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0xC0001
#define MXC_R_AFE_ADC_ZERO_MUX_CTRL2 ((uint32_t)0x000D0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0xD0001
#define MXC_R_AFE_ADC_ZERO_PART_ID ((uint32_t)0x00110003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x110003
#define MXC_R_AFE_ADC_ZERO_PD ((uint32_t)0x00000001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x0001
#define MXC_R_AFE_ADC_ZERO_PGA ((uint32_t)0x000E0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0xE0001
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_1 ((uint32_t)0x00180003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x180003
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_128 ((uint32_t)0x001F0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x1F0003
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_16 ((uint32_t)0x001C0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x1C0003
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_2 ((uint32_t)0x00190003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x190003
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_32 ((uint32_t)0x001D0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x1D0003
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_4 ((uint32_t)0x001A0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x1A0003
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_64 ((uint32_t)0x001E0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x1E0003
#define MXC_R_AFE_ADC_ZERO_SELF_GAIN_8 ((uint32_t)0x001B0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x1B0003
#define MXC_R_AFE_ADC_ZERO_SELF_OFF ((uint32_t)0x00170003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x170003
#define MXC_R_AFE_ADC_ZERO_SEQ_START ((uint32_t)0x00020001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x20001
#define MXC_R_AFE_ADC_ZERO_SOURCE ((uint32_t)0x000A0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0xA0001
#define MXC_R_AFE_ADC_ZERO_STATUS ((uint32_t)0x00380003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x380003
#define MXC_R_AFE_ADC_ZERO_STATUS_IE ((uint32_t)0x00390003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x390003
#define MXC_R_AFE_ADC_ZERO_SYS_CTRL ((uint32_t)0x007A0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x7A0001
#define MXC_R_AFE_ADC_ZERO_SYS_GAIN_A ((uint32_t)0x00150003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x150003
#define MXC_R_AFE_ADC_ZERO_SYS_GAIN_B ((uint32_t)0x00160003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x160003
#define MXC_R_AFE_ADC_ZERO_SYS_OFF_A ((uint32_t)0x00130003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x130003
#define MXC_R_AFE_ADC_ZERO_SYS_OFF_B ((uint32_t)0x00140003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x140003
#define MXC_R_AFE_ADC_ZERO_SYSC_SEL ((uint32_t)0x00120003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x120003
#define MXC_R_AFE_ADC_ZERO_TS_CTRL ((uint32_t)0x007C0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x7C0001
#define MXC_R_AFE_ADC_ZERO_UC_0 ((uint32_t)0x003A0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x3A0002
#define MXC_R_AFE_ADC_ZERO_UC_1 ((uint32_t)0x003B0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x3B0002
#define MXC_R_AFE_ADC_ZERO_UC_10 ((uint32_t)0x00440002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x440002
#define MXC_R_AFE_ADC_ZERO_UC_11 ((uint32_t)0x00450002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x450002
#define MXC_R_AFE_ADC_ZERO_UC_12 ((uint32_t)0x00460002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x460002
#define MXC_R_AFE_ADC_ZERO_UC_13 ((uint32_t)0x00470002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x470002
#define MXC_R_AFE_ADC_ZERO_UC_14 ((uint32_t)0x00480002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x480002
#define MXC_R_AFE_ADC_ZERO_UC_15 ((uint32_t)0x00490002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x490002
#define MXC_R_AFE_ADC_ZERO_UC_16 ((uint32_t)0x004A0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x4A0002
#define MXC_R_AFE_ADC_ZERO_UC_17 ((uint32_t)0x004B0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x4B0002
#define MXC_R_AFE_ADC_ZERO_UC_18 ((uint32_t)0x004C0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x4C0002
#define MXC_R_AFE_ADC_ZERO_UC_19 ((uint32_t)0x004D0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x4D0002
#define MXC_R_AFE_ADC_ZERO_UC_2 ((uint32_t)0x003C0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x3C0002
#define MXC_R_AFE_ADC_ZERO_UC_20 ((uint32_t)0x004E0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x4E0002
#define MXC_R_AFE_ADC_ZERO_UC_21 ((uint32_t)0x004F0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x4F0002
#define MXC_R_AFE_ADC_ZERO_UC_22 ((uint32_t)0x00500002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x500002
#define MXC_R_AFE_ADC_ZERO_UC_23 ((uint32_t)0x00510002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x510002
#define MXC_R_AFE_ADC_ZERO_UC_24 ((uint32_t)0x00520002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x520002
#define MXC_R_AFE_ADC_ZERO_UC_25 ((uint32_t)0x00530002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x530002
#define MXC_R_AFE_ADC_ZERO_UC_26 ((uint32_t)0x00540002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x540002
#define MXC_R_AFE_ADC_ZERO_UC_27 ((uint32_t)0x00550002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x550002
#define MXC_R_AFE_ADC_ZERO_UC_28 ((uint32_t)0x00560002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x560002
#define MXC_R_AFE_ADC_ZERO_UC_29 ((uint32_t)0x00570002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x570002
#define MXC_R_AFE_ADC_ZERO_UC_3 ((uint32_t)0x003D0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x3D0002
#define MXC_R_AFE_ADC_ZERO_UC_30 ((uint32_t)0x00580002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x580002
#define MXC_R_AFE_ADC_ZERO_UC_31 ((uint32_t)0x00590002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x590002
#define MXC_R_AFE_ADC_ZERO_UC_32 ((uint32_t)0x005A0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x5A0002
#define MXC_R_AFE_ADC_ZERO_UC_33 ((uint32_t)0x005B0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x5B0002
#define MXC_R_AFE_ADC_ZERO_UC_34 ((uint32_t)0x005C0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x5C0002
#define MXC_R_AFE_ADC_ZERO_UC_35 ((uint32_t)0x005D0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x5D0002
#define MXC_R_AFE_ADC_ZERO_UC_36 ((uint32_t)0x005E0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x5E0002
#define MXC_R_AFE_ADC_ZERO_UC_37 ((uint32_t)0x005F0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x5F0002
#define MXC_R_AFE_ADC_ZERO_UC_38 ((uint32_t)0x00600002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x600002
#define MXC_R_AFE_ADC_ZERO_UC_39 ((uint32_t)0x00610002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x610002
#define MXC_R_AFE_ADC_ZERO_UC_4 ((uint32_t)0x003E0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x3E0002
#define MXC_R_AFE_ADC_ZERO_UC_40 ((uint32_t)0x00620002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x620002
#define MXC_R_AFE_ADC_ZERO_UC_41 ((uint32_t)0x00630002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x630002
#define MXC_R_AFE_ADC_ZERO_UC_42 ((uint32_t)0x00640002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x640002
#define MXC_R_AFE_ADC_ZERO_UC_43 ((uint32_t)0x00650002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x650002
#define MXC_R_AFE_ADC_ZERO_UC_44 ((uint32_t)0x00660002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x660002
#define MXC_R_AFE_ADC_ZERO_UC_45 ((uint32_t)0x00670002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x670002
#define MXC_R_AFE_ADC_ZERO_UC_46 ((uint32_t)0x00680002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x680002
#define MXC_R_AFE_ADC_ZERO_UC_47 ((uint32_t)0x00690002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x690002
#define MXC_R_AFE_ADC_ZERO_UC_48 ((uint32_t)0x006A0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x6A0002
#define MXC_R_AFE_ADC_ZERO_UC_49 ((uint32_t)0x006B0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x6B0002
#define MXC_R_AFE_ADC_ZERO_UC_5 ((uint32_t)0x003F0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x3F0002
#define MXC_R_AFE_ADC_ZERO_UC_50 ((uint32_t)0x006C0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x6C0002
#define MXC_R_AFE_ADC_ZERO_UC_51 ((uint32_t)0x006D0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x6D0002
#define MXC_R_AFE_ADC_ZERO_UC_52 ((uint32_t)0x006E0002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x6E0002
#define MXC_R_AFE_ADC_ZERO_UC_6 ((uint32_t)0x00400002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x400002
#define MXC_R_AFE_ADC_ZERO_UC_7 ((uint32_t)0x00410002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x410002
#define MXC_R_AFE_ADC_ZERO_UC_8 ((uint32_t)0x00420002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x420002
#define MXC_R_AFE_ADC_ZERO_UC_9 ((uint32_t)0x00430002UL) |
Offset from AFE_ADC_ZERO Base Address: 0x430002
#define MXC_R_AFE_ADC_ZERO_UCADDR ((uint32_t)0x006F0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x6F0001
#define MXC_R_AFE_ADC_ZERO_UTHRESH0 ((uint32_t)0x00280003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x280003
#define MXC_R_AFE_ADC_ZERO_UTHRESH1 ((uint32_t)0x00290003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x290003
#define MXC_R_AFE_ADC_ZERO_UTHRESH2 ((uint32_t)0x002A0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x2A0003
#define MXC_R_AFE_ADC_ZERO_UTHRESH3 ((uint32_t)0x002B0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x2B0003
#define MXC_R_AFE_ADC_ZERO_UTHRESH4 ((uint32_t)0x002C0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x2C0003
#define MXC_R_AFE_ADC_ZERO_UTHRESH5 ((uint32_t)0x002D0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x2D0003
#define MXC_R_AFE_ADC_ZERO_UTHRESH6 ((uint32_t)0x002E0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x2E0003
#define MXC_R_AFE_ADC_ZERO_UTHRESH7 ((uint32_t)0x002F0003UL) |
Offset from AFE_ADC_ZERO Base Address: 0x2F0003
#define MXC_R_AFE_ADC_ZERO_WAIT_EXT ((uint32_t)0x000F0001UL) |
Offset from AFE_ADC_ZERO Base Address: 0xF0001
#define MXC_R_AFE_ADC_ZERO_WAIT_START ((uint32_t)0x00100001UL) |
Offset from AFE_ADC_ZERO Base Address: 0x100001