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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros | |
#define | MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS 0 |
#define | MXC_F_EMCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS)) |
#define | MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 |
#define | MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) |
#define | MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS 2 |
#define | MXC_F_EMCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)) |
#define | MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS 16 |
#define | MXC_F_EMCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS)) |
Cache Control and Status Register.
#define MXC_F_EMCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS)) |
CACHE_CTRL_CACHE_EN Mask
#define MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS 0 |
CACHE_CTRL_CACHE_EN Position
#define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS)) |
CACHE_CTRL_CACHE_RDY Mask
#define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS 16 |
CACHE_CTRL_CACHE_RDY Position
#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)) |
CACHE_CTRL_CWFST_DIS Mask
#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS 2 |
CACHE_CTRL_CWFST_DIS Position
#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) |
CACHE_CTRL_WRITE_ALLOC_EN Mask
#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 |
CACHE_CTRL_WRITE_ALLOC_EN Position