MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
sdma_regs.h
1 
6 /* ****************************************************************************
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39 
40 #ifndef _SDMA_REGS_H_
41 #define _SDMA_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __I uint32_t ip;
90  __I uint32_t sp;
91  __I uint32_t dp0;
92  __I uint32_t dp1;
93  __I uint32_t bp;
94  __I uint32_t offs;
95  __I uint32_t lc0;
96  __I uint32_t lc1;
97  __I uint32_t a0;
98  __I uint32_t a1;
99  __I uint32_t a2;
100  __I uint32_t a3;
101  __I uint32_t wdcn;
102  __R uint32_t rsv_0x34_0x7f[19];
103  __IO uint32_t int_mux_ctrl0;
104  __IO uint32_t int_mux_ctrl1;
105  __IO uint32_t int_mux_ctrl2;
106  __IO uint32_t int_mux_ctrl3;
107  __IO uint32_t ip_addr;
108  __IO uint32_t ctrl;
109  __R uint32_t rsv_0x98_0x9f[2];
110  __IO uint32_t int_in_ctrl;
111  __IO uint32_t int_in_flag;
112  __IO uint32_t int_in_ie;
113  __R uint32_t rsv_0xac;
114  __IO uint32_t irq_flag;
115  __IO uint32_t irq_ie;
117 
118 /* Register offsets for module SDMA */
125  #define MXC_R_SDMA_IP ((uint32_t)0x00000000UL)
126  #define MXC_R_SDMA_SP ((uint32_t)0x00000004UL)
127  #define MXC_R_SDMA_DP0 ((uint32_t)0x00000008UL)
128  #define MXC_R_SDMA_DP1 ((uint32_t)0x0000000CUL)
129  #define MXC_R_SDMA_BP ((uint32_t)0x00000010UL)
130  #define MXC_R_SDMA_OFFS ((uint32_t)0x00000014UL)
131  #define MXC_R_SDMA_LC0 ((uint32_t)0x00000018UL)
132  #define MXC_R_SDMA_LC1 ((uint32_t)0x0000001CUL)
133  #define MXC_R_SDMA_A0 ((uint32_t)0x00000020UL)
134  #define MXC_R_SDMA_A1 ((uint32_t)0x00000024UL)
135  #define MXC_R_SDMA_A2 ((uint32_t)0x00000028UL)
136  #define MXC_R_SDMA_A3 ((uint32_t)0x0000002CUL)
137  #define MXC_R_SDMA_WDCN ((uint32_t)0x00000030UL)
138  #define MXC_R_SDMA_INT_MUX_CTRL0 ((uint32_t)0x00000080UL)
139  #define MXC_R_SDMA_INT_MUX_CTRL1 ((uint32_t)0x00000084UL)
140  #define MXC_R_SDMA_INT_MUX_CTRL2 ((uint32_t)0x00000088UL)
141  #define MXC_R_SDMA_INT_MUX_CTRL3 ((uint32_t)0x0000008CUL)
142  #define MXC_R_SDMA_IP_ADDR ((uint32_t)0x00000090UL)
143  #define MXC_R_SDMA_CTRL ((uint32_t)0x00000094UL)
144  #define MXC_R_SDMA_INT_IN_CTRL ((uint32_t)0x000000A0UL)
145  #define MXC_R_SDMA_INT_IN_FLAG ((uint32_t)0x000000A4UL)
146  #define MXC_R_SDMA_INT_IN_IE ((uint32_t)0x000000A8UL)
147  #define MXC_R_SDMA_IRQ_FLAG ((uint32_t)0x000000B0UL)
148  #define MXC_R_SDMA_IRQ_IE ((uint32_t)0x000000B4UL)
157  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16_POS 0
158  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16_POS))
160  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17_POS 8
161  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17_POS))
163  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18_POS 16
164  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18_POS))
166  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19_POS 24
167  #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19_POS))
177  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS 0
178  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS))
180  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS 8
181  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS))
183  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS 16
184  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS))
186  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS 24
187  #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS))
197  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24_POS 0
198  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24_POS))
200  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25_POS 8
201  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25_POS))
203  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26_POS 16
204  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26_POS))
206  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27_POS 24
207  #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27_POS))
217  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28_POS 0
218  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28_POS))
220  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29_POS 8
221  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29_POS))
223  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30_POS 16
224  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30_POS))
226  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31_POS 24
227  #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31_POS))
237  #define MXC_F_SDMA_IP_ADDR_START_IP_ADDR_POS 0
238  #define MXC_F_SDMA_IP_ADDR_START_IP_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDMA_IP_ADDR_START_IP_ADDR_POS))
248  #define MXC_F_SDMA_CTRL_EN_POS 0
249  #define MXC_F_SDMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_SDMA_CTRL_EN_POS))
259  #define MXC_F_SDMA_INT_IN_CTRL_INTSET_POS 0
260  #define MXC_F_SDMA_INT_IN_CTRL_INTSET ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_CTRL_INTSET_POS))
270  #define MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS 0
271  #define MXC_F_SDMA_INT_IN_FLAG_INTFLAG ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS))
281  #define MXC_F_SDMA_INT_IN_IE_INT_IN_EN_POS 0
282  #define MXC_F_SDMA_INT_IN_IE_INT_IN_EN ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_IE_INT_IN_EN_POS))
292  #define MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG_POS 0
293  #define MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG ((uint32_t)(0x1UL << MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG_POS))
303  #define MXC_F_SDMA_IRQ_IE_IRQ_EN_POS 0
304  #define MXC_F_SDMA_IRQ_IE_IRQ_EN ((uint32_t)(0x1UL << MXC_F_SDMA_IRQ_IE_IRQ_EN_POS))
308 #ifdef __cplusplus
309 }
310 #endif
311 
312 #endif /* _SDMA_REGS_H_ */
mxc_sdma_regs_t::int_in_ie
__IO uint32_t int_in_ie
Definition: sdma_regs.h:112
mxc_sdma_regs_t::bp
__I uint32_t bp
Definition: sdma_regs.h:93
mxc_sdma_regs_t::wdcn
__I uint32_t wdcn
Definition: sdma_regs.h:101
mxc_sdma_regs_t::int_in_ctrl
__IO uint32_t int_in_ctrl
Definition: sdma_regs.h:110
mxc_sdma_regs_t::int_in_flag
__IO uint32_t int_in_flag
Definition: sdma_regs.h:111
mxc_sdma_regs_t::ip_addr
__IO uint32_t ip_addr
Definition: sdma_regs.h:107
mxc_sdma_regs_t::int_mux_ctrl1
__IO uint32_t int_mux_ctrl1
Definition: sdma_regs.h:104
mxc_sdma_regs_t::lc1
__I uint32_t lc1
Definition: sdma_regs.h:96
mxc_sdma_regs_t::a2
__I uint32_t a2
Definition: sdma_regs.h:99
mxc_sdma_regs_t::dp1
__I uint32_t dp1
Definition: sdma_regs.h:92
mxc_sdma_regs_t
Definition: sdma_regs.h:88
mxc_sdma_regs_t::sp
__I uint32_t sp
Definition: sdma_regs.h:90
mxc_sdma_regs_t::irq_ie
__IO uint32_t irq_ie
Definition: sdma_regs.h:115
mxc_sdma_regs_t::ctrl
__IO uint32_t ctrl
Definition: sdma_regs.h:108
mxc_sdma_regs_t::a3
__I uint32_t a3
Definition: sdma_regs.h:100
mxc_sdma_regs_t::int_mux_ctrl0
__IO uint32_t int_mux_ctrl0
Definition: sdma_regs.h:103
mxc_sdma_regs_t::lc0
__I uint32_t lc0
Definition: sdma_regs.h:95
mxc_sdma_regs_t::ip
__I uint32_t ip
Definition: sdma_regs.h:89
mxc_sdma_regs_t::a1
__I uint32_t a1
Definition: sdma_regs.h:98
mxc_sdma_regs_t::a0
__I uint32_t a0
Definition: sdma_regs.h:97
mxc_sdma_regs_t::offs
__I uint32_t offs
Definition: sdma_regs.h:94
mxc_sdma_regs_t::irq_flag
__IO uint32_t irq_flag
Definition: sdma_regs.h:114
mxc_sdma_regs_t::dp0
__I uint32_t dp0
Definition: sdma_regs.h:91
mxc_sdma_regs_t::int_mux_ctrl3
__IO uint32_t int_mux_ctrl3
Definition: sdma_regs.h:106
mxc_sdma_regs_t::int_mux_ctrl2
__IO uint32_t int_mux_ctrl2
Definition: sdma_regs.h:105