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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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External Sensor Control Register.
#define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) |
EXTSCN_BUSY Mask
#define MXC_F_SMON_EXTSCN_BUSY_POS 30 |
EXTSCN_BUSY Position
#define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) |
EXTSCN_DIVCLK Mask
#define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 |
EXTSCN_DIVCLK Position
#define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) |
EXTSCN_EXTCNT Mask
#define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 |
EXTSCN_EXTCNT Position
#define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) |
EXTSCN_EXTFRQ Mask
#define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 |
EXTSCN_EXTFRQ Position
#define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) |
EXTSCN_EXTS_EN0 Mask
#define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 |
EXTSCN_EXTS_EN0 Position
#define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) |
EXTSCN_EXTS_EN1 Mask
#define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 |
EXTSCN_EXTS_EN1 Position
#define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) |
EXTSCN_EXTS_EN2 Mask
#define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 |
EXTSCN_EXTS_EN2 Position
#define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) |
EXTSCN_EXTS_EN3 Mask
#define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 |
EXTSCN_EXTS_EN3 Position
#define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) |
EXTSCN_EXTS_EN4 Mask
#define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 |
EXTSCN_EXTS_EN4 Position
#define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) |
EXTSCN_EXTS_EN5 Mask
#define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 |
EXTSCN_EXTS_EN5 Position
#define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) |
EXTSCN_LOCK Mask
#define MXC_F_SMON_EXTSCN_LOCK_POS 31 |
EXTSCN_LOCK Position
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) |
EXTSCN_DIVCLK_DIV1 Setting
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) |
EXTSCN_DIVCLK_DIV16 Setting
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) |
EXTSCN_DIVCLK_DIV2 Setting
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) |
EXTSCN_DIVCLK_DIV32 Setting
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) |
EXTSCN_DIVCLK_DIV4 Setting
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) |
EXTSCN_DIVCLK_DIV64 Setting
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) |
EXTSCN_DIVCLK_DIV8 Setting
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) |
EXTSCN_EXTFRQ_FREQ1000HZ Setting
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) |
EXTSCN_EXTFRQ_FREQ125HZ Setting
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) |
EXTSCN_EXTFRQ_FREQ2000HZ Setting
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) |
EXTSCN_EXTFRQ_FREQ250HZ Setting
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) |
EXTSCN_EXTFRQ_FREQ31HZ Setting
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) |
EXTSCN_EXTFRQ_FREQ500HZ Setting
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) |
EXTSCN_EXTFRQ_FREQ63HZ Setting
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) |
EXTSCN_DIVCLK_DIV1 Value
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) |
EXTSCN_DIVCLK_DIV16 Value
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) |
EXTSCN_DIVCLK_DIV2 Value
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) |
EXTSCN_DIVCLK_DIV32 Value
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) |
EXTSCN_DIVCLK_DIV4 Value
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) |
EXTSCN_DIVCLK_DIV64 Value
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) |
EXTSCN_DIVCLK_DIV8 Value
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) |
EXTSCN_EXTFRQ_FREQ1000HZ Value
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) |
EXTSCN_EXTFRQ_FREQ125HZ Value
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) |
EXTSCN_EXTFRQ_FREQ2000HZ Value
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) |
EXTSCN_EXTFRQ_FREQ250HZ Value
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) |
EXTSCN_EXTFRQ_FREQ31HZ Value
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) |
EXTSCN_EXTFRQ_FREQ500HZ Value
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) |
EXTSCN_EXTFRQ_FREQ63HZ Value