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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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RTC Control Register.
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) |
CTRL_BUSY Mask
#define MXC_F_RTC_CTRL_BUSY_POS 3 |
CTRL_BUSY Position
#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ENABLE_POS)) |
CTRL_ENABLE Mask
#define MXC_F_RTC_CTRL_ENABLE_POS 0 |
CTRL_ENABLE Position
#define MXC_F_RTC_CTRL_FREQ_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FREQ_SEL_POS)) |
CTRL_FREQ_SEL Mask
#define MXC_F_RTC_CTRL_FREQ_SEL_POS 9 |
CTRL_FREQ_SEL Position
#define MXC_F_RTC_CTRL_READY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_READY_POS)) |
CTRL_READY Mask
#define MXC_F_RTC_CTRL_READY_INT_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_READY_INT_EN_POS)) |
CTRL_READY_INT_EN Mask
#define MXC_F_RTC_CTRL_READY_INT_EN_POS 5 |
CTRL_READY_INT_EN Position
#define MXC_F_RTC_CTRL_READY_POS 4 |
CTRL_READY Position
#define MXC_F_RTC_CTRL_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQWOUT_EN_POS)) |
CTRL_SQWOUT_EN Mask
#define MXC_F_RTC_CTRL_SQWOUT_EN_POS 8 |
CTRL_SQWOUT_EN Position
#define MXC_F_RTC_CTRL_SSEC_ALARM_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_EN_POS)) |
CTRL_SSEC_ALARM_EN Mask
#define MXC_F_RTC_CTRL_SSEC_ALARM_EN_POS 2 |
CTRL_SSEC_ALARM_EN Position
#define MXC_F_RTC_CTRL_SSEC_ALARM_FL ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_FL_POS)) |
CTRL_SSEC_ALARM_FL Mask
#define MXC_F_RTC_CTRL_SSEC_ALARM_FL_POS 7 |
CTRL_SSEC_ALARM_FL Position
#define MXC_F_RTC_CTRL_TOD_ALARM_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_EN_POS)) |
CTRL_TOD_ALARM_EN Mask
#define MXC_F_RTC_CTRL_TOD_ALARM_EN_POS 1 |
CTRL_TOD_ALARM_EN Position
#define MXC_F_RTC_CTRL_TOD_ALARM_FL ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_FL_POS)) |
CTRL_TOD_ALARM_FL Mask
#define MXC_F_RTC_CTRL_TOD_ALARM_FL_POS 6 |
CTRL_TOD_ALARM_FL Position
#define MXC_F_RTC_CTRL_WRITE_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WRITE_EN_POS)) |
CTRL_WRITE_EN Mask
#define MXC_F_RTC_CTRL_WRITE_EN_POS 15 |
CTRL_WRITE_EN Position
#define MXC_S_RTC_CTRL_FREQ_SEL_CLKDIV8 (MXC_V_RTC_CTRL_FREQ_SEL_CLKDIV8 << MXC_F_RTC_CTRL_FREQ_SEL_POS) |
CTRL_FREQ_SEL_CLKDIV8 Setting
#define MXC_S_RTC_CTRL_FREQ_SEL_FREQ1HZ (MXC_V_RTC_CTRL_FREQ_SEL_FREQ1HZ << MXC_F_RTC_CTRL_FREQ_SEL_POS) |
CTRL_FREQ_SEL_FREQ1HZ Setting
#define MXC_S_RTC_CTRL_FREQ_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_FREQ_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_FREQ_SEL_POS) |
CTRL_FREQ_SEL_FREQ4KHZ Setting
#define MXC_S_RTC_CTRL_FREQ_SEL_FREQ512HZ (MXC_V_RTC_CTRL_FREQ_SEL_FREQ512HZ << MXC_F_RTC_CTRL_FREQ_SEL_POS) |
CTRL_FREQ_SEL_FREQ512HZ Setting
#define MXC_V_RTC_CTRL_FREQ_SEL_CLKDIV8 ((uint32_t)0x3UL) |
CTRL_FREQ_SEL_CLKDIV8 Value
#define MXC_V_RTC_CTRL_FREQ_SEL_FREQ1HZ ((uint32_t)0x0UL) |
CTRL_FREQ_SEL_FREQ1HZ Value
#define MXC_V_RTC_CTRL_FREQ_SEL_FREQ4KHZ ((uint32_t)0x2UL) |
CTRL_FREQ_SEL_FREQ4KHZ Value
#define MXC_V_RTC_CTRL_FREQ_SEL_FREQ512HZ ((uint32_t)0x1UL) |
CTRL_FREQ_SEL_FREQ512HZ Value