MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665

Macros

#define MXC_F_RPU_PWRSEQ_DMA0ACN_POS   0
 
#define MXC_F_RPU_PWRSEQ_DMA0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA0ACN_POS))
 
#define MXC_F_RPU_PWRSEQ_DMA1ACN_POS   1
 
#define MXC_F_RPU_PWRSEQ_DMA1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA1ACN_POS))
 
#define MXC_F_RPU_PWRSEQ_USBACN_POS   2
 
#define MXC_F_RPU_PWRSEQ_USBACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_USBACN_POS))
 
#define MXC_F_RPU_PWRSEQ_SYS0ACN_POS   3
 
#define MXC_F_RPU_PWRSEQ_SYS0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS0ACN_POS))
 
#define MXC_F_RPU_PWRSEQ_SYS1ACN_POS   4
 
#define MXC_F_RPU_PWRSEQ_SYS1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS1ACN_POS))
 
#define MXC_F_RPU_PWRSEQ_SDMADACN_POS   5
 
#define MXC_F_RPU_PWRSEQ_SDMADACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMADACN_POS))
 
#define MXC_F_RPU_PWRSEQ_SDMAIACN_POS   6
 
#define MXC_F_RPU_PWRSEQ_SDMAIACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMAIACN_POS))
 
#define MXC_F_RPU_PWRSEQ_CRYPTOACN_POS   7
 
#define MXC_F_RPU_PWRSEQ_CRYPTOACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_CRYPTOACN_POS))
 
#define MXC_F_RPU_PWRSEQ_SDIOACN_POS   8
 
#define MXC_F_RPU_PWRSEQ_SDIOACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDIOACN_POS))
 

Detailed Description

Power Sequencer Protection Register.

Macro Definition Documentation

◆ MXC_F_RPU_PWRSEQ_CRYPTOACN

#define MXC_F_RPU_PWRSEQ_CRYPTOACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_CRYPTOACN_POS))

PWRSEQ_CRYPTOACN Mask

◆ MXC_F_RPU_PWRSEQ_CRYPTOACN_POS

#define MXC_F_RPU_PWRSEQ_CRYPTOACN_POS   7

PWRSEQ_CRYPTOACN Position

◆ MXC_F_RPU_PWRSEQ_DMA0ACN

#define MXC_F_RPU_PWRSEQ_DMA0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA0ACN_POS))

PWRSEQ_DMA0ACN Mask

◆ MXC_F_RPU_PWRSEQ_DMA0ACN_POS

#define MXC_F_RPU_PWRSEQ_DMA0ACN_POS   0

PWRSEQ_DMA0ACN Position

◆ MXC_F_RPU_PWRSEQ_DMA1ACN

#define MXC_F_RPU_PWRSEQ_DMA1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA1ACN_POS))

PWRSEQ_DMA1ACN Mask

◆ MXC_F_RPU_PWRSEQ_DMA1ACN_POS

#define MXC_F_RPU_PWRSEQ_DMA1ACN_POS   1

PWRSEQ_DMA1ACN Position

◆ MXC_F_RPU_PWRSEQ_SDIOACN

#define MXC_F_RPU_PWRSEQ_SDIOACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDIOACN_POS))

PWRSEQ_SDIOACN Mask

◆ MXC_F_RPU_PWRSEQ_SDIOACN_POS

#define MXC_F_RPU_PWRSEQ_SDIOACN_POS   8

PWRSEQ_SDIOACN Position

◆ MXC_F_RPU_PWRSEQ_SDMADACN

#define MXC_F_RPU_PWRSEQ_SDMADACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMADACN_POS))

PWRSEQ_SDMADACN Mask

◆ MXC_F_RPU_PWRSEQ_SDMADACN_POS

#define MXC_F_RPU_PWRSEQ_SDMADACN_POS   5

PWRSEQ_SDMADACN Position

◆ MXC_F_RPU_PWRSEQ_SDMAIACN

#define MXC_F_RPU_PWRSEQ_SDMAIACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMAIACN_POS))

PWRSEQ_SDMAIACN Mask

◆ MXC_F_RPU_PWRSEQ_SDMAIACN_POS

#define MXC_F_RPU_PWRSEQ_SDMAIACN_POS   6

PWRSEQ_SDMAIACN Position

◆ MXC_F_RPU_PWRSEQ_SYS0ACN

#define MXC_F_RPU_PWRSEQ_SYS0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS0ACN_POS))

PWRSEQ_SYS0ACN Mask

◆ MXC_F_RPU_PWRSEQ_SYS0ACN_POS

#define MXC_F_RPU_PWRSEQ_SYS0ACN_POS   3

PWRSEQ_SYS0ACN Position

◆ MXC_F_RPU_PWRSEQ_SYS1ACN

#define MXC_F_RPU_PWRSEQ_SYS1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS1ACN_POS))

PWRSEQ_SYS1ACN Mask

◆ MXC_F_RPU_PWRSEQ_SYS1ACN_POS

#define MXC_F_RPU_PWRSEQ_SYS1ACN_POS   4

PWRSEQ_SYS1ACN Position

◆ MXC_F_RPU_PWRSEQ_USBACN

#define MXC_F_RPU_PWRSEQ_USBACN   ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_USBACN_POS))

PWRSEQ_USBACN Mask

◆ MXC_F_RPU_PWRSEQ_USBACN_POS

#define MXC_F_RPU_PWRSEQ_USBACN_POS   2

PWRSEQ_USBACN Position