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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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ECC Not Double Error Detect Register.
#define MXC_F_GCR_ECC_NDED_FL0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_FL0ECCNDED_POS)) |
ECC_NDED_FL0ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_FL0ECCNDED_POS 11 |
ECC_NDED_FL0ECCNDED Position
#define MXC_F_GCR_ECC_NDED_FL1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_FL1ECCNDED_POS)) |
ECC_NDED_FL1ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_FL1ECCNDED_POS 12 |
ECC_NDED_FL1ECCNDED Position
#define MXC_F_GCR_ECC_NDED_IC0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_IC0ECCNDED_POS)) |
ECC_NDED_IC0ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_IC0ECCNDED_POS 8 |
ECC_NDED_IC0ECCNDED Position
#define MXC_F_GCR_ECC_NDED_IC1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_IC1ECCNDED_POS)) |
ECC_NDED_IC1ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_IC1ECCNDED_POS 9 |
ECC_NDED_IC1ECCNDED Position
#define MXC_F_GCR_ECC_NDED_ICXIPECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_ICXIPECCNDED_POS)) |
ECC_NDED_ICXIPECCNDED Mask
#define MXC_F_GCR_ECC_NDED_ICXIPECCNDED_POS 10 |
ECC_NDED_ICXIPECCNDED Position
#define MXC_F_GCR_ECC_NDED_SYSRAM0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM0ECCNDED_POS)) |
ECC_NDED_SYSRAM0ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_SYSRAM0ECCNDED_POS 0 |
ECC_NDED_SYSRAM0ECCNDED Position
#define MXC_F_GCR_ECC_NDED_SYSRAM1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM1ECCNDED_POS)) |
ECC_NDED_SYSRAM1ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_SYSRAM1ECCNDED_POS 1 |
ECC_NDED_SYSRAM1ECCNDED Position
#define MXC_F_GCR_ECC_NDED_SYSRAM2ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM2ECCNDED_POS)) |
ECC_NDED_SYSRAM2ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_SYSRAM2ECCNDED_POS 2 |
ECC_NDED_SYSRAM2ECCNDED Position
#define MXC_F_GCR_ECC_NDED_SYSRAM3ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM3ECCNDED_POS)) |
ECC_NDED_SYSRAM3ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_SYSRAM3ECCNDED_POS 3 |
ECC_NDED_SYSRAM3ECCNDED Position
#define MXC_F_GCR_ECC_NDED_SYSRAM4ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM4ECCNDED_POS)) |
ECC_NDED_SYSRAM4ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_SYSRAM4ECCNDED_POS 4 |
ECC_NDED_SYSRAM4ECCNDED Position
#define MXC_F_GCR_ECC_NDED_SYSRAM5ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM5ECCNDED_POS)) |
ECC_NDED_SYSRAM5ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_SYSRAM5ECCNDED_POS 5 |
ECC_NDED_SYSRAM5ECCNDED Position
#define MXC_F_GCR_ECC_NDED_SYSRAM6ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM6ECCNDED_POS)) |
ECC_NDED_SYSRAM6ECCNDED Mask
#define MXC_F_GCR_ECC_NDED_SYSRAM6ECCNDED_POS 6 |
ECC_NDED_SYSRAM6ECCNDED Position