MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665

Macros

#define MXC_F_FLC_CLKDIV_CLKDIV_POS   0
 
#define MXC_F_FLC_CLKDIV_CLKDIV   ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS))
 

Detailed Description

Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.

Macro Definition Documentation

◆ MXC_F_FLC_CLKDIV_CLKDIV

#define MXC_F_FLC_CLKDIV_CLKDIV   ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS))

CLKDIV_CLKDIV Mask

◆ MXC_F_FLC_CLKDIV_CLKDIV_POS

#define MXC_F_FLC_CLKDIV_CLKDIV_POS   0

CLKDIV_CLKDIV Position