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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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50 #if defined (__ICCARM__)
51 #pragma system_include
54 #if defined (__CC_ARM)
65 #define __I volatile const
71 #define __R volatile const
97 __O uint32_t data_in[4];
98 __I uint32_t data_out[4];
103 __IO uint32_t cipher_init[4];
104 __O uint32_t cipher_key[8];
105 __IO uint32_t hash_digest[16];
106 __IO uint32_t hash_msg_sz[4];
117 #define MXC_R_TPU_CTRL ((uint32_t)0x00000000UL)
118 #define MXC_R_TPU_CIPHER_CTRL ((uint32_t)0x00000004UL)
119 #define MXC_R_TPU_HASH_CTRL ((uint32_t)0x00000008UL)
120 #define MXC_R_TPU_CRC_CTRL ((uint32_t)0x0000000CUL)
121 #define MXC_R_TPU_DMA_SRC ((uint32_t)0x00000010UL)
122 #define MXC_R_TPU_DMA_DST ((uint32_t)0x00000014UL)
123 #define MXC_R_TPU_DMA_CNT ((uint32_t)0x00000018UL)
124 #define MXC_R_TPU_MAA_CTRL ((uint32_t)0x0000001CUL)
125 #define MXC_R_TPU_DATA_IN ((uint32_t)0x00000020UL)
126 #define MXC_R_TPU_DATA_OUT ((uint32_t)0x00000030UL)
127 #define MXC_R_TPU_CRC_POLY ((uint32_t)0x00000040UL)
128 #define MXC_R_TPU_CRC_VAL ((uint32_t)0x00000044UL)
129 #define MXC_R_TPU_CRC_PRNG ((uint32_t)0x00000048UL)
130 #define MXC_R_TPU_HAM_ECC ((uint32_t)0x0000004CUL)
131 #define MXC_R_TPU_CIPHER_INIT ((uint32_t)0x00000050UL)
132 #define MXC_R_TPU_CIPHER_KEY ((uint32_t)0x00000060UL)
133 #define MXC_R_TPU_HASH_DIGEST ((uint32_t)0x00000080UL)
134 #define MXC_R_TPU_HASH_MSG_SZ ((uint32_t)0x000000C0UL)
135 #define MXC_R_TPU_MAA_MAWS ((uint32_t)0x000000D0UL)
144 #define MXC_F_TPU_CTRL_RST_POS 0
145 #define MXC_F_TPU_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RST_POS))
147 #define MXC_F_TPU_CTRL_INT_POS 1
148 #define MXC_F_TPU_CTRL_INT ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_INT_POS))
150 #define MXC_F_TPU_CTRL_SRC_POS 2
151 #define MXC_F_TPU_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_SRC_POS))
153 #define MXC_F_TPU_CTRL_BSO_POS 4
154 #define MXC_F_TPU_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSO_POS))
156 #define MXC_F_TPU_CTRL_BSI_POS 5
157 #define MXC_F_TPU_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSI_POS))
159 #define MXC_F_TPU_CTRL_WAIT_EN_POS 6
160 #define MXC_F_TPU_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_EN_POS))
162 #define MXC_F_TPU_CTRL_WAIT_POL_POS 7
163 #define MXC_F_TPU_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_POL_POS))
165 #define MXC_F_TPU_CTRL_WRSRC_POS 8
166 #define MXC_F_TPU_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_WRSRC_POS))
167 #define MXC_V_TPU_CTRL_WRSRC_NONE ((uint32_t)0x0UL)
168 #define MXC_S_TPU_CTRL_WRSRC_NONE (MXC_V_TPU_CTRL_WRSRC_NONE << MXC_F_TPU_CTRL_WRSRC_POS)
169 #define MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL)
170 #define MXC_S_TPU_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_CTRL_WRSRC_POS)
171 #define MXC_V_TPU_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL)
172 #define MXC_S_TPU_CTRL_WRSRC_READFIFO (MXC_V_TPU_CTRL_WRSRC_READFIFO << MXC_F_TPU_CTRL_WRSRC_POS)
174 #define MXC_F_TPU_CTRL_RDSRC_POS 10
175 #define MXC_F_TPU_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_RDSRC_POS))
176 #define MXC_V_TPU_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL)
177 #define MXC_S_TPU_CTRL_RDSRC_DMADISABLED (MXC_V_TPU_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_CTRL_RDSRC_POS)
178 #define MXC_V_TPU_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL)
179 #define MXC_S_TPU_CTRL_RDSRC_DMAORAPB (MXC_V_TPU_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_CTRL_RDSRC_POS)
180 #define MXC_V_TPU_CTRL_RDSRC_RNG ((uint32_t)0x2UL)
181 #define MXC_S_TPU_CTRL_RDSRC_RNG (MXC_V_TPU_CTRL_RDSRC_RNG << MXC_F_TPU_CTRL_RDSRC_POS)
183 #define MXC_F_TPU_CTRL_FLAG_MODE_POS 14
184 #define MXC_F_TPU_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_FLAG_MODE_POS))
186 #define MXC_F_TPU_CTRL_DMADNE_MSK_POS 15
187 #define MXC_F_TPU_CTRL_DMADNE_MSK ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMADNE_MSK_POS))
189 #define MXC_F_TPU_CTRL_DMA_DONE_POS 24
190 #define MXC_F_TPU_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMA_DONE_POS))
192 #define MXC_F_TPU_CTRL_GLS_DONE_POS 25
193 #define MXC_F_TPU_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_GLS_DONE_POS))
195 #define MXC_F_TPU_CTRL_HSH_DONE_POS 26
196 #define MXC_F_TPU_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_HSH_DONE_POS))
198 #define MXC_F_TPU_CTRL_CPH_DONE_POS 27
199 #define MXC_F_TPU_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_CPH_DONE_POS))
201 #define MXC_F_TPU_CTRL_MAA_DONE_POS 28
202 #define MXC_F_TPU_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_MAA_DONE_POS))
204 #define MXC_F_TPU_CTRL_ERR_POS 29
205 #define MXC_F_TPU_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_ERR_POS))
207 #define MXC_F_TPU_CTRL_RDY_POS 30
208 #define MXC_F_TPU_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RDY_POS))
210 #define MXC_F_TPU_CTRL_DONE_POS 31
211 #define MXC_F_TPU_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DONE_POS))
221 #define MXC_F_TPU_CIPHER_CTRL_ENC_POS 0
222 #define MXC_F_TPU_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_ENC_POS))
224 #define MXC_F_TPU_CIPHER_CTRL_KEY_POS 1
225 #define MXC_F_TPU_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_KEY_POS))
227 #define MXC_F_TPU_CIPHER_CTRL_SRC_POS 2
228 #define MXC_F_TPU_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_CIPHER_CTRL_SRC_POS))
229 #define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL)
230 #define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_CIPHER_CTRL_SRC_POS)
231 #define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL)
232 #define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS)
233 #define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL)
234 #define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS)
236 #define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS 4
237 #define MXC_F_TPU_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS))
238 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL)
239 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)
240 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL)
241 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)
242 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL)
243 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)
244 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL)
245 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)
246 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL)
247 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)
248 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL)
249 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)
251 #define MXC_F_TPU_CIPHER_CTRL_MODE_POS 8
252 #define MXC_F_TPU_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_MODE_POS))
253 #define MXC_V_TPU_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL)
254 #define MXC_S_TPU_CIPHER_CTRL_MODE_ECB (MXC_V_TPU_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_CIPHER_CTRL_MODE_POS)
255 #define MXC_V_TPU_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL)
256 #define MXC_S_TPU_CIPHER_CTRL_MODE_CBC (MXC_V_TPU_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_CIPHER_CTRL_MODE_POS)
257 #define MXC_V_TPU_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL)
258 #define MXC_S_TPU_CIPHER_CTRL_MODE_CFB (MXC_V_TPU_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS)
259 #define MXC_V_TPU_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL)
260 #define MXC_S_TPU_CIPHER_CTRL_MODE_OFB (MXC_V_TPU_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS)
261 #define MXC_V_TPU_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL)
262 #define MXC_S_TPU_CIPHER_CTRL_MODE_CTR (MXC_V_TPU_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_CIPHER_CTRL_MODE_POS)
272 #define MXC_F_TPU_HASH_CTRL_INIT_POS 0
273 #define MXC_F_TPU_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_INIT_POS))
275 #define MXC_F_TPU_HASH_CTRL_XOR_POS 1
276 #define MXC_F_TPU_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_XOR_POS))
278 #define MXC_F_TPU_HASH_CTRL_HASH_POS 2
279 #define MXC_F_TPU_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_TPU_HASH_CTRL_HASH_POS))
280 #define MXC_V_TPU_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL)
281 #define MXC_S_TPU_HASH_CTRL_HASH_DIS (MXC_V_TPU_HASH_CTRL_HASH_DIS << MXC_F_TPU_HASH_CTRL_HASH_POS)
282 #define MXC_V_TPU_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL)
283 #define MXC_S_TPU_HASH_CTRL_HASH_SHA1 (MXC_V_TPU_HASH_CTRL_HASH_SHA1 << MXC_F_TPU_HASH_CTRL_HASH_POS)
284 #define MXC_V_TPU_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL)
285 #define MXC_S_TPU_HASH_CTRL_HASH_SHA224 (MXC_V_TPU_HASH_CTRL_HASH_SHA224 << MXC_F_TPU_HASH_CTRL_HASH_POS)
286 #define MXC_V_TPU_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL)
287 #define MXC_S_TPU_HASH_CTRL_HASH_SHA256 (MXC_V_TPU_HASH_CTRL_HASH_SHA256 << MXC_F_TPU_HASH_CTRL_HASH_POS)
288 #define MXC_V_TPU_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL)
289 #define MXC_S_TPU_HASH_CTRL_HASH_SHA384 (MXC_V_TPU_HASH_CTRL_HASH_SHA384 << MXC_F_TPU_HASH_CTRL_HASH_POS)
290 #define MXC_V_TPU_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL)
291 #define MXC_S_TPU_HASH_CTRL_HASH_SHA512 (MXC_V_TPU_HASH_CTRL_HASH_SHA512 << MXC_F_TPU_HASH_CTRL_HASH_POS)
293 #define MXC_F_TPU_HASH_CTRL_LAST_POS 5
294 #define MXC_F_TPU_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_LAST_POS))
304 #define MXC_F_TPU_CRC_CTRL_CRC_EN_POS 0
305 #define MXC_F_TPU_CRC_CTRL_CRC_EN ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_CRC_EN_POS))
307 #define MXC_F_TPU_CRC_CTRL_MSB_POS 1
308 #define MXC_F_TPU_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_MSB_POS))
310 #define MXC_F_TPU_CRC_CTRL_PRNG_POS 2
311 #define MXC_F_TPU_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_PRNG_POS))
313 #define MXC_F_TPU_CRC_CTRL_ENT_POS 3
314 #define MXC_F_TPU_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_ENT_POS))
316 #define MXC_F_TPU_CRC_CTRL_HAM_POS 4
317 #define MXC_F_TPU_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HAM_POS))
319 #define MXC_F_TPU_CRC_CTRL_HRST_POS 5
320 #define MXC_F_TPU_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HRST_POS))
330 #define MXC_F_TPU_DMA_SRC_SRC_ADDR_POS 0
331 #define MXC_F_TPU_DMA_SRC_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_SRC_SRC_ADDR_POS))
341 #define MXC_F_TPU_DMA_DST_DST_ADDR_POS 0
342 #define MXC_F_TPU_DMA_DST_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_DST_DST_ADDR_POS))
352 #define MXC_F_TPU_DMA_CNT_COUNT_POS 0
353 #define MXC_F_TPU_DMA_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_COUNT_POS))
363 #define MXC_F_TPU_MAA_CTRL_STC_POS 0
364 #define MXC_F_TPU_MAA_CTRL_STC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_STC_POS))
366 #define MXC_F_TPU_MAA_CTRL_CLC_POS 1
367 #define MXC_F_TPU_MAA_CTRL_CLC ((uint32_t)(0x7UL << MXC_F_TPU_MAA_CTRL_CLC_POS))
368 #define MXC_V_TPU_MAA_CTRL_CLC_EXP ((uint32_t)0x0UL)
369 #define MXC_S_TPU_MAA_CTRL_CLC_EXP (MXC_V_TPU_MAA_CTRL_CLC_EXP << MXC_F_TPU_MAA_CTRL_CLC_POS)
370 #define MXC_V_TPU_MAA_CTRL_CLC_SQ ((uint32_t)0x1UL)
371 #define MXC_S_TPU_MAA_CTRL_CLC_SQ (MXC_V_TPU_MAA_CTRL_CLC_SQ << MXC_F_TPU_MAA_CTRL_CLC_POS)
372 #define MXC_V_TPU_MAA_CTRL_CLC_MUL ((uint32_t)0x2UL)
373 #define MXC_S_TPU_MAA_CTRL_CLC_MUL (MXC_V_TPU_MAA_CTRL_CLC_MUL << MXC_F_TPU_MAA_CTRL_CLC_POS)
374 #define MXC_V_TPU_MAA_CTRL_CLC_SQMUL ((uint32_t)0x3UL)
375 #define MXC_S_TPU_MAA_CTRL_CLC_SQMUL (MXC_V_TPU_MAA_CTRL_CLC_SQMUL << MXC_F_TPU_MAA_CTRL_CLC_POS)
376 #define MXC_V_TPU_MAA_CTRL_CLC_ADD ((uint32_t)0x4UL)
377 #define MXC_S_TPU_MAA_CTRL_CLC_ADD (MXC_V_TPU_MAA_CTRL_CLC_ADD << MXC_F_TPU_MAA_CTRL_CLC_POS)
378 #define MXC_V_TPU_MAA_CTRL_CLC_SUB ((uint32_t)0x5UL)
379 #define MXC_S_TPU_MAA_CTRL_CLC_SUB (MXC_V_TPU_MAA_CTRL_CLC_SUB << MXC_F_TPU_MAA_CTRL_CLC_POS)
381 #define MXC_F_TPU_MAA_CTRL_OCALC_POS 4
382 #define MXC_F_TPU_MAA_CTRL_OCALC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_OCALC_POS))
384 #define MXC_F_TPU_MAA_CTRL_MAAER_POS 7
385 #define MXC_F_TPU_MAA_CTRL_MAAER ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_MAAER_POS))
387 #define MXC_F_TPU_MAA_CTRL_AMS_POS 8
388 #define MXC_F_TPU_MAA_CTRL_AMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_AMS_POS))
390 #define MXC_F_TPU_MAA_CTRL_BMS_POS 10
391 #define MXC_F_TPU_MAA_CTRL_BMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_BMS_POS))
393 #define MXC_F_TPU_MAA_CTRL_EMS_POS 12
394 #define MXC_F_TPU_MAA_CTRL_EMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_EMS_POS))
396 #define MXC_F_TPU_MAA_CTRL_MMS_POS 14
397 #define MXC_F_TPU_MAA_CTRL_MMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_MMS_POS))
399 #define MXC_F_TPU_MAA_CTRL_AMA_POS 16
400 #define MXC_F_TPU_MAA_CTRL_AMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_AMA_POS))
402 #define MXC_F_TPU_MAA_CTRL_BMA_POS 20
403 #define MXC_F_TPU_MAA_CTRL_BMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_BMA_POS))
405 #define MXC_F_TPU_MAA_CTRL_RMA_POS 24
406 #define MXC_F_TPU_MAA_CTRL_RMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_RMA_POS))
408 #define MXC_F_TPU_MAA_CTRL_TMA_POS 28
409 #define MXC_F_TPU_MAA_CTRL_TMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_TMA_POS))
423 #define MXC_F_TPU_DATA_IN_DATA_POS 0
424 #define MXC_F_TPU_DATA_IN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DATA_IN_DATA_POS))
437 #define MXC_F_TPU_DATA_OUT_DATA_POS 0
438 #define MXC_F_TPU_DATA_OUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DATA_OUT_DATA_POS))
450 #define MXC_F_TPU_CRC_POLY_SRC_ADDR_POS 0
451 #define MXC_F_TPU_CRC_POLY_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_POLY_SRC_ADDR_POS))
463 #define MXC_F_TPU_CRC_VAL_VAL_POS 0
464 #define MXC_F_TPU_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_VAL_VAL_POS))
476 #define MXC_F_TPU_CRC_PRNG_PRNG_POS 0
477 #define MXC_F_TPU_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_PRNG_PRNG_POS))
487 #define MXC_F_TPU_HAM_ECC_ECC_POS 0
488 #define MXC_F_TPU_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_TPU_HAM_ECC_ECC_POS))
490 #define MXC_F_TPU_HAM_ECC_PAR_POS 16
491 #define MXC_F_TPU_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_TPU_HAM_ECC_PAR_POS))
504 #define MXC_F_TPU_CIPHER_INIT_IVEC_POS 0
505 #define MXC_F_TPU_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_INIT_IVEC_POS))
517 #define MXC_F_TPU_CIPHER_KEY_KEY_POS 0
518 #define MXC_F_TPU_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_KEY_KEY_POS))
529 #define MXC_F_TPU_HASH_DIGEST_HASH_POS 0
530 #define MXC_F_TPU_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_DIGEST_HASH_POS))
540 #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS 0
541 #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS))
554 #define MXC_F_TPU_MAA_MAWS_MSGSZ_POS 0
555 #define MXC_F_TPU_MAA_MAWS_MSGSZ ((uint32_t)(0xFFFUL << MXC_F_TPU_MAA_MAWS_MSGSZ_POS))
__IO uint32_t crc_ctrl
Definition: tpu_regs.h:92
__IO uint32_t maa_maws
Definition: tpu_regs.h:107
__I uint32_t crc_prng
Definition: tpu_regs.h:101
__IO uint32_t ham_ecc
Definition: tpu_regs.h:102
__IO uint32_t cipher_ctrl
Definition: tpu_regs.h:90
__IO uint32_t hash_ctrl
Definition: tpu_regs.h:91
__IO uint32_t crc_val
Definition: tpu_regs.h:100
__IO uint32_t crc_poly
Definition: tpu_regs.h:99
__IO uint32_t dma_src
Definition: tpu_regs.h:93
__IO uint32_t ctrl
Definition: tpu_regs.h:89
Definition: tpu_regs.h:88
__IO uint32_t dma_cnt
Definition: tpu_regs.h:95
__IO uint32_t dma_dst
Definition: tpu_regs.h:94
__IO uint32_t maa_ctrl
Definition: tpu_regs.h:96