MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665

Macros

#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS   0
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS   1
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS   2
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS   3
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS   4
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS   5
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS   7
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS   8
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS   9
 
#define MXC_F_PWRSEQ_LPMEMSD_SRCCSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS   10
 
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS   11
 
#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS   12
 
#define MXC_F_PWRSEQ_LPMEMSD_ROMSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS   13
 
#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS   14
 
#define MXC_F_PWRSEQ_LPMEMSD_IC1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS))
 

Detailed Description

Low Power Memory Shutdown Control.

Macro Definition Documentation

◆ MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD

#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS))

LPMEMSD_CRYPTOSD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS

#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS   10

LPMEMSD_CRYPTOSD Position

◆ MXC_F_PWRSEQ_LPMEMSD_IC1SD

#define MXC_F_PWRSEQ_LPMEMSD_IC1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS))

LPMEMSD_IC1SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS   14

LPMEMSD_IC1SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_ICACHESD

#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS))

LPMEMSD_ICACHESD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS

#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS   7

LPMEMSD_ICACHESD Position

◆ MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD

#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS))

LPMEMSD_ICACHEXIPSD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS

#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS   8

LPMEMSD_ICACHEXIPSD Position

◆ MXC_F_PWRSEQ_LPMEMSD_ROM1SD

#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS))

LPMEMSD_ROM1SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS   13

LPMEMSD_ROM1SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_ROMSD

#define MXC_F_PWRSEQ_LPMEMSD_ROMSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS))

LPMEMSD_ROMSD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS

#define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS   12

LPMEMSD_ROMSD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM0SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS))

LPMEMSD_SRAM0SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS   0

LPMEMSD_SRAM0SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM1SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS))

LPMEMSD_SRAM1SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS   1

LPMEMSD_SRAM1SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM2SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS))

LPMEMSD_SRAM2SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS   2

LPMEMSD_SRAM2SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM3SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS))

LPMEMSD_SRAM3SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS   3

LPMEMSD_SRAM3SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM4SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS))

LPMEMSD_SRAM4SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS   4

LPMEMSD_SRAM4SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM5SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS))

LPMEMSD_SRAM5SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS   5

LPMEMSD_SRAM5SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRCCSD

#define MXC_F_PWRSEQ_LPMEMSD_SRCCSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS))

LPMEMSD_SRCCSD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS   9

LPMEMSD_SRCCSD Position

◆ MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD

#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS))

LPMEMSD_USBFIFOSD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS

#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS   11

LPMEMSD_USBFIFOSD Position