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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Peripheral Clock Divider.
#define MXC_F_GCR_PCLK_DIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS)) |
PCLK_DIV_ADCFRQ Mask
#define MXC_F_GCR_PCLK_DIV_ADCFRQ_POS 10 |
PCLK_DIV_ADCFRQ Position
#define MXC_F_GCR_PCLK_DIV_AONDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLK_DIV_AONDIV_POS)) |
PCLK_DIV_AONDIV Mask
#define MXC_F_GCR_PCLK_DIV_AONDIV_POS 14 |
PCLK_DIV_AONDIV Position
#define MXC_F_GCR_PCLK_DIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCLK_DIV_PCF_POS)) |
PCLK_DIV_PCF Mask
#define MXC_F_GCR_PCLK_DIV_PCF_POS 0 |
PCLK_DIV_PCF Position
#define MXC_F_GCR_PCLK_DIV_SDHCFRQ ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS)) |
PCLK_DIV_SDHCFRQ Mask
#define MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS 7 |
PCLK_DIV_SDHCFRQ Position
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_16 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
PCLK_DIV_AONDIV_DIV_16 Setting
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_32 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
PCLK_DIV_AONDIV_DIV_32 Setting
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_4 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
PCLK_DIV_AONDIV_DIV_4 Setting
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_8 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
PCLK_DIV_AONDIV_DIV_8 Setting
#define MXC_S_GCR_PCLK_DIV_PCF_12MHZ (MXC_V_GCR_PCLK_DIV_PCF_12MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS) |
PCLK_DIV_PCF_12MHZ Setting
#define MXC_S_GCR_PCLK_DIV_PCF_24MHZ (MXC_V_GCR_PCLK_DIV_PCF_24MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS) |
PCLK_DIV_PCF_24MHZ Setting
#define MXC_S_GCR_PCLK_DIV_PCF_3MHZ (MXC_V_GCR_PCLK_DIV_PCF_3MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS) |
PCLK_DIV_PCF_3MHZ Setting
#define MXC_S_GCR_PCLK_DIV_PCF_48MHZ (MXC_V_GCR_PCLK_DIV_PCF_48MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS) |
PCLK_DIV_PCF_48MHZ Setting
#define MXC_S_GCR_PCLK_DIV_PCF_6MHZ (MXC_V_GCR_PCLK_DIV_PCF_6MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS) |
PCLK_DIV_PCF_6MHZ Setting
#define MXC_S_GCR_PCLK_DIV_PCF_96MHZ (MXC_V_GCR_PCLK_DIV_PCF_96MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS) |
PCLK_DIV_PCF_96MHZ Setting
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16 ((uint32_t)0x2UL) |
PCLK_DIV_AONDIV_DIV_16 Value
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32 ((uint32_t)0x3UL) |
PCLK_DIV_AONDIV_DIV_32 Value
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4 ((uint32_t)0x0UL) |
PCLK_DIV_AONDIV_DIV_4 Value
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8 ((uint32_t)0x1UL) |
PCLK_DIV_AONDIV_DIV_8 Value
#define MXC_V_GCR_PCLK_DIV_PCF_12MHZ ((uint32_t)0x5UL) |
PCLK_DIV_PCF_12MHZ Value
#define MXC_V_GCR_PCLK_DIV_PCF_24MHZ ((uint32_t)0x4UL) |
PCLK_DIV_PCF_24MHZ Value
#define MXC_V_GCR_PCLK_DIV_PCF_3MHZ ((uint32_t)0x7UL) |
PCLK_DIV_PCF_3MHZ Value
#define MXC_V_GCR_PCLK_DIV_PCF_48MHZ ((uint32_t)0x3UL) |
PCLK_DIV_PCF_48MHZ Value
#define MXC_V_GCR_PCLK_DIV_PCF_6MHZ ((uint32_t)0x6UL) |
PCLK_DIV_PCF_6MHZ Value
#define MXC_V_GCR_PCLK_DIV_PCF_96MHZ ((uint32_t)0x2UL) |
PCLK_DIV_PCF_96MHZ Value