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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Memory Zeroize Control.
#define MXC_F_GCR_MEM_ZERO_CRYPTOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS)) |
MEM_ZERO_CRYPTOZ Mask
#define MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS 12 |
MEM_ZERO_CRYPTOZ Position
#define MXC_F_GCR_MEM_ZERO_ICACHE0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHE0Z_POS)) |
MEM_ZERO_ICACHE0Z Mask
#define MXC_F_GCR_MEM_ZERO_ICACHE0Z_POS 8 |
MEM_ZERO_ICACHE0Z Position
#define MXC_F_GCR_MEM_ZERO_ICACHE1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHE1Z_POS)) |
MEM_ZERO_ICACHE1Z Mask
#define MXC_F_GCR_MEM_ZERO_ICACHE1Z_POS 14 |
MEM_ZERO_ICACHE1Z Position
#define MXC_F_GCR_MEM_ZERO_ICACHEXIPZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS)) |
MEM_ZERO_ICACHEXIPZ Mask
#define MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS 9 |
MEM_ZERO_ICACHEXIPZ Position
#define MXC_F_GCR_MEM_ZERO_SCACHEDATAZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS)) |
MEM_ZERO_SCACHEDATAZ Mask
#define MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS 10 |
MEM_ZERO_SCACHEDATAZ Position
#define MXC_F_GCR_MEM_ZERO_SCACHETAGZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS)) |
MEM_ZERO_SCACHETAGZ Mask
#define MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS 11 |
MEM_ZERO_SCACHETAGZ Position
#define MXC_F_GCR_MEM_ZERO_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS)) |
MEM_ZERO_SRAM0Z Mask
#define MXC_F_GCR_MEM_ZERO_SRAM0Z_POS 0 |
MEM_ZERO_SRAM0Z Position
#define MXC_F_GCR_MEM_ZERO_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS)) |
MEM_ZERO_SRAM1Z Mask
#define MXC_F_GCR_MEM_ZERO_SRAM1Z_POS 1 |
MEM_ZERO_SRAM1Z Position
#define MXC_F_GCR_MEM_ZERO_SRAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM2_POS)) |
MEM_ZERO_SRAM2 Mask
#define MXC_F_GCR_MEM_ZERO_SRAM2_POS 2 |
MEM_ZERO_SRAM2 Position
#define MXC_F_GCR_MEM_ZERO_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS)) |
MEM_ZERO_SRAM3Z Mask
#define MXC_F_GCR_MEM_ZERO_SRAM3Z_POS 3 |
MEM_ZERO_SRAM3Z Position
#define MXC_F_GCR_MEM_ZERO_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS)) |
MEM_ZERO_SRAM4Z Mask
#define MXC_F_GCR_MEM_ZERO_SRAM4Z_POS 4 |
MEM_ZERO_SRAM4Z Position
#define MXC_F_GCR_MEM_ZERO_SRAM5Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS)) |
MEM_ZERO_SRAM5Z Mask
#define MXC_F_GCR_MEM_ZERO_SRAM5Z_POS 5 |
MEM_ZERO_SRAM5Z Position
#define MXC_F_GCR_MEM_ZERO_SRAM6Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS)) |
MEM_ZERO_SRAM6Z Mask
#define MXC_F_GCR_MEM_ZERO_SRAM6Z_POS 6 |
MEM_ZERO_SRAM6Z Position
#define MXC_F_GCR_MEM_ZERO_USBFIFOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS)) |
MEM_ZERO_USBFIFOZ Mask
#define MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS 13 |
MEM_ZERO_USBFIFOZ Position