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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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50 #if defined (__ICCARM__)
51 #pragma system_include
54 #if defined (__CC_ARM)
65 #define __I volatile const
71 #define __R volatile const
93 __R uint32_t rsv_0x10_0x17[2];
95 __R uint32_t rsv_0x1c_0x23[2];
99 __R uint32_t rsv_0x30;
109 __R uint32_t rsv_0x58_0x63[3];
116 __R uint32_t rsv_0x7c;
128 #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL)
129 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL)
130 #define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL)
131 #define MXC_R_GCR_PMR ((uint32_t)0x0000000CUL)
132 #define MXC_R_GCR_PCLK_DIV ((uint32_t)0x00000018UL)
133 #define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL)
134 #define MXC_R_GCR_MEM_CLK ((uint32_t)0x00000028UL)
135 #define MXC_R_GCR_MEM_ZERO ((uint32_t)0x0000002CUL)
136 #define MXC_R_GCR_SCCK ((uint32_t)0x00000034UL)
137 #define MXC_R_GCR_MPRI0 ((uint32_t)0x00000038UL)
138 #define MXC_R_GCR_MPRI1 ((uint32_t)0x0000003CUL)
139 #define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL)
140 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL)
141 #define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL)
142 #define MXC_R_GCR_EVENT_EN ((uint32_t)0x0000004CUL)
143 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL)
144 #define MXC_R_GCR_SYS_STAT_IE ((uint32_t)0x00000054UL)
145 #define MXC_R_GCR_ECC_ER ((uint32_t)0x00000064UL)
146 #define MXC_R_GCR_ECC_NDED ((uint32_t)0x00000068UL)
147 #define MXC_R_GCR_ECC_IRQEN ((uint32_t)0x0000006CUL)
148 #define MXC_R_GCR_ECC_ERRAD ((uint32_t)0x00000070UL)
149 #define MXC_R_GCR_BTLE_LDOCR ((uint32_t)0x00000074UL)
150 #define MXC_R_GCR_BTLE_LDODCR ((uint32_t)0x00000078UL)
151 #define MXC_R_GCR_GPR0 ((uint32_t)0x00000080UL)
152 #define MXC_R_GCR_APB_ASYNC ((uint32_t)0x00000084UL)
161 #define MXC_F_GCR_SCON_BSTAPEN_POS 0
162 #define MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS))
164 #define MXC_F_GCR_SCON_SBUSARB_POS 1
165 #define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS))
166 #define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL)
167 #define MXC_S_GCR_SCON_SBUSARB_FIX (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS)
168 #define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL)
169 #define MXC_S_GCR_SCON_SBUSARB_ROUND (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS)
171 #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4
172 #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS))
174 #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6
175 #define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS))
177 #define MXC_F_GCR_SCON_DCACHE_FLUSH_POS 7
178 #define MXC_F_GCR_SCON_DCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS))
180 #define MXC_F_GCR_SCON_DCACHE_DIS_POS 9
181 #define MXC_F_GCR_SCON_DCACHE_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_DIS_POS))
183 #define MXC_F_GCR_SCON_CCHK_POS 13
184 #define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS))
186 #define MXC_F_GCR_SCON_CHKRES_POS 15
187 #define MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS))
189 #define MXC_F_GCR_SCON_OVR_POS 16
190 #define MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS))
191 #define MXC_V_GCR_SCON_OVR_0_9V ((uint32_t)0x0UL)
192 #define MXC_S_GCR_SCON_OVR_0_9V (MXC_V_GCR_SCON_OVR_0_9V << MXC_F_GCR_SCON_OVR_POS)
193 #define MXC_V_GCR_SCON_OVR_1_0V ((uint32_t)0x1UL)
194 #define MXC_S_GCR_SCON_OVR_1_0V (MXC_V_GCR_SCON_OVR_1_0V << MXC_F_GCR_SCON_OVR_POS)
195 #define MXC_V_GCR_SCON_OVR_1_1V ((uint32_t)0x2UL)
196 #define MXC_S_GCR_SCON_OVR_1_1V (MXC_V_GCR_SCON_OVR_1_1V << MXC_F_GCR_SCON_OVR_POS)
206 #define MXC_F_GCR_RST0_DMA0_POS 0
207 #define MXC_F_GCR_RST0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA0_POS))
209 #define MXC_F_GCR_RST0_WDT0_POS 1
210 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS))
212 #define MXC_F_GCR_RST0_GPIO0_POS 2
213 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS))
215 #define MXC_F_GCR_RST0_GPIO1_POS 3
216 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS))
218 #define MXC_F_GCR_RST0_TIMER0_POS 5
219 #define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS))
221 #define MXC_F_GCR_RST0_TIMER1_POS 6
222 #define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS))
224 #define MXC_F_GCR_RST0_TIMER2_POS 7
225 #define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS))
227 #define MXC_F_GCR_RST0_TIMER3_POS 8
228 #define MXC_F_GCR_RST0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER3_POS))
230 #define MXC_F_GCR_RST0_TIMER4_POS 9
231 #define MXC_F_GCR_RST0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER4_POS))
233 #define MXC_F_GCR_RST0_TIMER5_POS 10
234 #define MXC_F_GCR_RST0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER5_POS))
236 #define MXC_F_GCR_RST0_UART0_POS 11
237 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS))
239 #define MXC_F_GCR_RST0_UART1_POS 12
240 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS))
242 #define MXC_F_GCR_RST0_SPI1_POS 13
243 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS))
245 #define MXC_F_GCR_RST0_SPI2_POS 14
246 #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS))
248 #define MXC_F_GCR_RST0_I2C0_POS 16
249 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS))
251 #define MXC_F_GCR_RST0_RTC_POS 17
252 #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS))
254 #define MXC_F_GCR_RST0_CRYPTO_POS 18
255 #define MXC_F_GCR_RST0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CRYPTO_POS))
257 #define MXC_F_GCR_RST0_SMPHR_POS 22
258 #define MXC_F_GCR_RST0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SMPHR_POS))
260 #define MXC_F_GCR_RST0_USB_POS 23
261 #define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS))
263 #define MXC_F_GCR_RST0_TRNG_POS 24
264 #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS))
266 #define MXC_F_GCR_RST0_ADC_POS 26
267 #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS))
269 #define MXC_F_GCR_RST0_DMA1_POS 27
270 #define MXC_F_GCR_RST0_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA1_POS))
272 #define MXC_F_GCR_RST0_UART2_POS 28
273 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS))
275 #define MXC_F_GCR_RST0_SOFT_RST_POS 29
276 #define MXC_F_GCR_RST0_SOFT_RST ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_RST_POS))
278 #define MXC_F_GCR_RST0_PERIPH_RST_POS 30
279 #define MXC_F_GCR_RST0_PERIPH_RST ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_RST_POS))
281 #define MXC_F_GCR_RST0_SYS_RST_POS 31
282 #define MXC_F_GCR_RST0_SYS_RST ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_RST_POS))
292 #define MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS 6
293 #define MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS))
294 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 ((uint32_t)0x0UL)
295 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
296 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 ((uint32_t)0x1UL)
297 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
298 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 ((uint32_t)0x2UL)
299 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
300 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 ((uint32_t)0x3UL)
301 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
302 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 ((uint32_t)0x4UL)
303 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
304 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 ((uint32_t)0x5UL)
305 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
306 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 ((uint32_t)0x6UL)
307 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
308 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 ((uint32_t)0x7UL)
309 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)
311 #define MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS 9
312 #define MXC_F_GCR_CLK_CTRL_SYSOSC_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS))
313 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC ((uint32_t)0x0UL)
314 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)
315 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M ((uint32_t)0x2UL)
316 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)
317 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8 ((uint32_t)0x3UL)
318 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)
319 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 ((uint32_t)0x4UL)
320 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)
321 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 ((uint32_t)0x5UL)
322 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)
323 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K ((uint32_t)0x6UL)
324 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)
326 #define MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS 13
327 #define MXC_F_GCR_CLK_CTRL_SYSOSC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS))
329 #define MXC_F_GCR_CLK_CTRL_CCD_POS 15
330 #define MXC_F_GCR_CLK_CTRL_CCD ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CCD_POS))
332 #define MXC_F_GCR_CLK_CTRL_X32M_EN_POS 16
333 #define MXC_F_GCR_CLK_CTRL_X32M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32M_EN_POS))
335 #define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17
336 #define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS))
338 #define MXC_F_GCR_CLK_CTRL_HIRC60M_EN_POS 18
339 #define MXC_F_GCR_CLK_CTRL_HIRC60M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC60M_EN_POS))
341 #define MXC_F_GCR_CLK_CTRL_HIRCMM_EN_POS 19
342 #define MXC_F_GCR_CLK_CTRL_HIRCMM_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRCMM_EN_POS))
344 #define MXC_F_GCR_CLK_CTRL_HIRC8M_EN_POS 20
345 #define MXC_F_GCR_CLK_CTRL_HIRC8M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8M_EN_POS))
347 #define MXC_F_GCR_CLK_CTRL_HIRC8M_VS_POS 21
348 #define MXC_F_GCR_CLK_CTRL_HIRC8M_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8M_VS_POS))
350 #define MXC_F_GCR_CLK_CTRL_X32M_RDY_POS 24
351 #define MXC_F_GCR_CLK_CTRL_X32M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32M_RDY_POS))
353 #define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25
354 #define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS))
356 #define MXC_F_GCR_CLK_CTRL_HIRC60M_RDY_POS 26
357 #define MXC_F_GCR_CLK_CTRL_HIRC60M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC60M_RDY_POS))
359 #define MXC_F_GCR_CLK_CTRL_HIRCMM_RDY_POS 27
360 #define MXC_F_GCR_CLK_CTRL_HIRCMM_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRCMM_RDY_POS))
362 #define MXC_F_GCR_CLK_CTRL_HIRC8M_RDY_POS 28
363 #define MXC_F_GCR_CLK_CTRL_HIRC8M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8M_RDY_POS))
365 #define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29
366 #define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS))
368 #define MXC_F_GCR_CLK_CTRL_LIRC6K_RDY_POS 30
369 #define MXC_F_GCR_CLK_CTRL_LIRC6K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC6K_RDY_POS))
379 #define MXC_F_GCR_PMR_MODE_POS 0
380 #define MXC_F_GCR_PMR_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PMR_MODE_POS))
381 #define MXC_V_GCR_PMR_MODE_ACTIVE ((uint32_t)0x0UL)
382 #define MXC_S_GCR_PMR_MODE_ACTIVE (MXC_V_GCR_PMR_MODE_ACTIVE << MXC_F_GCR_PMR_MODE_POS)
383 #define MXC_V_GCR_PMR_MODE_DEEPSLEEP ((uint32_t)0x2UL)
384 #define MXC_S_GCR_PMR_MODE_DEEPSLEEP (MXC_V_GCR_PMR_MODE_DEEPSLEEP << MXC_F_GCR_PMR_MODE_POS)
385 #define MXC_V_GCR_PMR_MODE_SHUTDOWN ((uint32_t)0x3UL)
386 #define MXC_S_GCR_PMR_MODE_SHUTDOWN (MXC_V_GCR_PMR_MODE_SHUTDOWN << MXC_F_GCR_PMR_MODE_POS)
387 #define MXC_V_GCR_PMR_MODE_BACKUP ((uint32_t)0x4UL)
388 #define MXC_S_GCR_PMR_MODE_BACKUP (MXC_V_GCR_PMR_MODE_BACKUP << MXC_F_GCR_PMR_MODE_POS)
390 #define MXC_F_GCR_PMR_GPIOWKEN_POS 4
391 #define MXC_F_GCR_PMR_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_GPIOWKEN_POS))
393 #define MXC_F_GCR_PMR_RTCWKEN_POS 5
394 #define MXC_F_GCR_PMR_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_RTCWKEN_POS))
396 #define MXC_F_GCR_PMR_USBWKEN_POS 6
397 #define MXC_F_GCR_PMR_USBWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_USBWKEN_POS))
399 #define MXC_F_GCR_PMR_WUTWKEN_POS 7
400 #define MXC_F_GCR_PMR_WUTWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_WUTWKEN_POS))
402 #define MXC_F_GCR_PMR_SDMAWKEN_POS 8
403 #define MXC_F_GCR_PMR_SDMAWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_SDMAWKEN_POS))
405 #define MXC_F_GCR_PMR_COMPWKEN_POS 8
406 #define MXC_F_GCR_PMR_COMPWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_COMPWKEN_POS))
408 #define MXC_F_GCR_PMR_HIRCPD_POS 15
409 #define MXC_F_GCR_PMR_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_HIRCPD_POS))
411 #define MXC_F_GCR_PMR_HIRC96MPD_POS 16
412 #define MXC_F_GCR_PMR_HIRC96MPD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_HIRC96MPD_POS))
414 #define MXC_F_GCR_PMR_HIRC8MPD_POS 17
415 #define MXC_F_GCR_PMR_HIRC8MPD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_HIRC8MPD_POS))
417 #define MXC_F_GCR_PMR_XTALPB_POS 20
418 #define MXC_F_GCR_PMR_XTALPB ((uint32_t)(0x1UL << MXC_F_GCR_PMR_XTALPB_POS))
428 #define MXC_F_GCR_PCLK_DIV_PCF_POS 0
429 #define MXC_F_GCR_PCLK_DIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCLK_DIV_PCF_POS))
430 #define MXC_V_GCR_PCLK_DIV_PCF_96MHZ ((uint32_t)0x2UL)
431 #define MXC_S_GCR_PCLK_DIV_PCF_96MHZ (MXC_V_GCR_PCLK_DIV_PCF_96MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
432 #define MXC_V_GCR_PCLK_DIV_PCF_48MHZ ((uint32_t)0x3UL)
433 #define MXC_S_GCR_PCLK_DIV_PCF_48MHZ (MXC_V_GCR_PCLK_DIV_PCF_48MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
434 #define MXC_V_GCR_PCLK_DIV_PCF_24MHZ ((uint32_t)0x4UL)
435 #define MXC_S_GCR_PCLK_DIV_PCF_24MHZ (MXC_V_GCR_PCLK_DIV_PCF_24MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
436 #define MXC_V_GCR_PCLK_DIV_PCF_12MHZ ((uint32_t)0x5UL)
437 #define MXC_S_GCR_PCLK_DIV_PCF_12MHZ (MXC_V_GCR_PCLK_DIV_PCF_12MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
438 #define MXC_V_GCR_PCLK_DIV_PCF_6MHZ ((uint32_t)0x6UL)
439 #define MXC_S_GCR_PCLK_DIV_PCF_6MHZ (MXC_V_GCR_PCLK_DIV_PCF_6MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
440 #define MXC_V_GCR_PCLK_DIV_PCF_3MHZ ((uint32_t)0x7UL)
441 #define MXC_S_GCR_PCLK_DIV_PCF_3MHZ (MXC_V_GCR_PCLK_DIV_PCF_3MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
443 #define MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS 7
444 #define MXC_F_GCR_PCLK_DIV_SDHCFRQ ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS))
446 #define MXC_F_GCR_PCLK_DIV_ADCFRQ_POS 10
447 #define MXC_F_GCR_PCLK_DIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS))
449 #define MXC_F_GCR_PCLK_DIV_AONDIV_POS 14
450 #define MXC_F_GCR_PCLK_DIV_AONDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLK_DIV_AONDIV_POS))
451 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4 ((uint32_t)0x0UL)
452 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_4 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
453 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8 ((uint32_t)0x1UL)
454 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_8 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
455 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16 ((uint32_t)0x2UL)
456 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_16 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
457 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32 ((uint32_t)0x3UL)
458 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_32 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
468 #define MXC_F_GCR_PCLK_DIS0_GPIO0_POS 0
469 #define MXC_F_GCR_PCLK_DIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0_POS))
471 #define MXC_F_GCR_PCLK_DIS0_GPIO1_POS 1
472 #define MXC_F_GCR_PCLK_DIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO1_POS))
474 #define MXC_F_GCR_PCLK_DIS0_USB_POS 3
475 #define MXC_F_GCR_PCLK_DIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_USB_POS))
477 #define MXC_F_GCR_PCLK_DIS0_DMA0_POS 5
478 #define MXC_F_GCR_PCLK_DIS0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMA0_POS))
480 #define MXC_F_GCR_PCLK_DIS0_SPI0_POS 6
481 #define MXC_F_GCR_PCLK_DIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0_POS))
483 #define MXC_F_GCR_PCLK_DIS0_SPI1_POS 7
484 #define MXC_F_GCR_PCLK_DIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1_POS))
486 #define MXC_F_GCR_PCLK_DIS0_UART0_POS 9
487 #define MXC_F_GCR_PCLK_DIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0_POS))
489 #define MXC_F_GCR_PCLK_DIS0_UART1_POS 10
490 #define MXC_F_GCR_PCLK_DIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1_POS))
492 #define MXC_F_GCR_PCLK_DIS0_I2C0_POS 13
493 #define MXC_F_GCR_PCLK_DIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0_POS))
495 #define MXC_F_GCR_PCLK_DIS0_CRYPTO_POS 14
496 #define MXC_F_GCR_PCLK_DIS0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_CRYPTO_POS))
498 #define MXC_F_GCR_PCLK_DIS0_TIMER0_POS 15
499 #define MXC_F_GCR_PCLK_DIS0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0_POS))
501 #define MXC_F_GCR_PCLK_DIS0_TIMER1_POS 16
502 #define MXC_F_GCR_PCLK_DIS0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1_POS))
504 #define MXC_F_GCR_PCLK_DIS0_TIMER2_POS 17
505 #define MXC_F_GCR_PCLK_DIS0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2_POS))
507 #define MXC_F_GCR_PCLK_DIS0_TIMER3_POS 18
508 #define MXC_F_GCR_PCLK_DIS0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER3_POS))
510 #define MXC_F_GCR_PCLK_DIS0_TIMER4_POS 19
511 #define MXC_F_GCR_PCLK_DIS0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER4_POS))
513 #define MXC_F_GCR_PCLK_DIS0_TIMER5_POS 20
514 #define MXC_F_GCR_PCLK_DIS0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER5_POS))
516 #define MXC_F_GCR_PCLK_DIS0_ADC_POS 23
517 #define MXC_F_GCR_PCLK_DIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_ADC_POS))
519 #define MXC_F_GCR_PCLK_DIS0_I2C1_POS 28
520 #define MXC_F_GCR_PCLK_DIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1_POS))
522 #define MXC_F_GCR_PCLK_DIS0_PTD_POS 29
523 #define MXC_F_GCR_PCLK_DIS0_PTD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_PTD_POS))
525 #define MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS 30
526 #define MXC_F_GCR_PCLK_DIS0_SPIXIPF ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS))
528 #define MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS 31
529 #define MXC_F_GCR_PCLK_DIS0_SPIXIPM ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS))
539 #define MXC_F_GCR_MEM_CLK_FWS_POS 0
540 #define MXC_F_GCR_MEM_CLK_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CLK_FWS_POS))
542 #define MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS 16
543 #define MXC_F_GCR_MEM_CLK_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS))
545 #define MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS 17
546 #define MXC_F_GCR_MEM_CLK_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS))
548 #define MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS 18
549 #define MXC_F_GCR_MEM_CLK_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS))
551 #define MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS 19
552 #define MXC_F_GCR_MEM_CLK_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS))
554 #define MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS 20
555 #define MXC_F_GCR_MEM_CLK_SYSRAM4LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS))
557 #define MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS 21
558 #define MXC_F_GCR_MEM_CLK_SYSRAM5LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS))
560 #define MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS 22
561 #define MXC_F_GCR_MEM_CLK_SYSRAM6LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS))
563 #define MXC_F_GCR_MEM_CLK_ICACHE0LS_POS 24
564 #define MXC_F_GCR_MEM_CLK_ICACHE0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHE0LS_POS))
566 #define MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS 25
567 #define MXC_F_GCR_MEM_CLK_ICACHEXIPLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS))
569 #define MXC_F_GCR_MEM_CLK_SCACHELS_POS 26
570 #define MXC_F_GCR_MEM_CLK_SCACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SCACHELS_POS))
572 #define MXC_F_GCR_MEM_CLK_CRYPTOLS_POS 27
573 #define MXC_F_GCR_MEM_CLK_CRYPTOLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS))
575 #define MXC_F_GCR_MEM_CLK_USBLS_POS 28
576 #define MXC_F_GCR_MEM_CLK_USBLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_USBLS_POS))
578 #define MXC_F_GCR_MEM_CLK_ROM0LS_POS 29
579 #define MXC_F_GCR_MEM_CLK_ROM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ROM0LS_POS))
581 #define MXC_F_GCR_MEM_CLK_ROM1LS_POS 30
582 #define MXC_F_GCR_MEM_CLK_ROM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ROM1LS_POS))
584 #define MXC_F_GCR_MEM_CLK_ICACHE1LS_POS 31
585 #define MXC_F_GCR_MEM_CLK_ICACHE1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHE1LS_POS))
595 #define MXC_F_GCR_MEM_ZERO_SRAM0Z_POS 0
596 #define MXC_F_GCR_MEM_ZERO_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS))
598 #define MXC_F_GCR_MEM_ZERO_SRAM1Z_POS 1
599 #define MXC_F_GCR_MEM_ZERO_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS))
601 #define MXC_F_GCR_MEM_ZERO_SRAM2_POS 2
602 #define MXC_F_GCR_MEM_ZERO_SRAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM2_POS))
604 #define MXC_F_GCR_MEM_ZERO_SRAM3Z_POS 3
605 #define MXC_F_GCR_MEM_ZERO_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS))
607 #define MXC_F_GCR_MEM_ZERO_SRAM4Z_POS 4
608 #define MXC_F_GCR_MEM_ZERO_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS))
610 #define MXC_F_GCR_MEM_ZERO_SRAM5Z_POS 5
611 #define MXC_F_GCR_MEM_ZERO_SRAM5Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS))
613 #define MXC_F_GCR_MEM_ZERO_SRAM6Z_POS 6
614 #define MXC_F_GCR_MEM_ZERO_SRAM6Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS))
616 #define MXC_F_GCR_MEM_ZERO_ICACHE0Z_POS 8
617 #define MXC_F_GCR_MEM_ZERO_ICACHE0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHE0Z_POS))
619 #define MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS 9
620 #define MXC_F_GCR_MEM_ZERO_ICACHEXIPZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS))
622 #define MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS 10
623 #define MXC_F_GCR_MEM_ZERO_SCACHEDATAZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS))
625 #define MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS 11
626 #define MXC_F_GCR_MEM_ZERO_SCACHETAGZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS))
628 #define MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS 12
629 #define MXC_F_GCR_MEM_ZERO_CRYPTOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS))
631 #define MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS 13
632 #define MXC_F_GCR_MEM_ZERO_USBFIFOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS))
634 #define MXC_F_GCR_MEM_ZERO_ICACHE1Z_POS 14
635 #define MXC_F_GCR_MEM_ZERO_ICACHE1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHE1Z_POS))
645 #define MXC_F_GCR_SYS_STAT_ICELOCK_POS 0
646 #define MXC_F_GCR_SYS_STAT_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICELOCK_POS))
648 #define MXC_F_GCR_SYS_STAT_CODEINTERR_POS 1
649 #define MXC_F_GCR_SYS_STAT_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_CODEINTERR_POS))
651 #define MXC_F_GCR_SYS_STAT_SCMEMF_POS 5
652 #define MXC_F_GCR_SYS_STAT_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_SCMEMF_POS))
662 #define MXC_F_GCR_RST1_I2C1_POS 0
663 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))
665 #define MXC_F_GCR_RST1_PT_POS 1
666 #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))
668 #define MXC_F_GCR_RST1_SPIXIP_POS 3
669 #define MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS))
671 #define MXC_F_GCR_RST1_XSPIM_POS 4
672 #define MXC_F_GCR_RST1_XSPIM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XSPIM_POS))
674 #define MXC_F_GCR_RST1_SDHC_POS 6
675 #define MXC_F_GCR_RST1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS))
677 #define MXC_F_GCR_RST1_OWIRE_POS 7
678 #define MXC_F_GCR_RST1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS))
680 #define MXC_F_GCR_RST1_WDT1_POS 8
681 #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS))
683 #define MXC_F_GCR_RST1_SPI3_POS 9
684 #define MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS))
686 #define MXC_F_GCR_RST1_XIPR_POS 15
687 #define MXC_F_GCR_RST1_XIPR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XIPR_POS))
689 #define MXC_F_GCR_RST1_SEMA_POS 16
690 #define MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS))
692 #define MXC_F_GCR_RST1_WDT2_POS 17
693 #define MXC_F_GCR_RST1_WDT2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT2_POS))
695 #define MXC_F_GCR_RST1_BTLE_POS 18
696 #define MXC_F_GCR_RST1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_BTLE_POS))
698 #define MXC_F_GCR_RST1_AUDIO_POS 19
699 #define MXC_F_GCR_RST1_AUDIO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AUDIO_POS))
701 #define MXC_F_GCR_RST1_I2C2_POS 20
702 #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))
704 #define MXC_F_GCR_RST1_RPU_POS 21
705 #define MXC_F_GCR_RST1_RPU ((uint32_t)(0x1UL << MXC_F_GCR_RST1_RPU_POS))
707 #define MXC_F_GCR_RST1_HTMR0_POS 22
708 #define MXC_F_GCR_RST1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR0_POS))
710 #define MXC_F_GCR_RST1_HTMR1_POS 23
711 #define MXC_F_GCR_RST1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR1_POS))
713 #define MXC_F_GCR_RST1_DVS_POS 24
714 #define MXC_F_GCR_RST1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS))
716 #define MXC_F_GCR_RST1_SIMO_POS 25
717 #define MXC_F_GCR_RST1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS))
727 #define MXC_F_GCR_PCLK_DIS1_BTLE_POS 0
728 #define MXC_F_GCR_PCLK_DIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_BTLE_POS))
730 #define MXC_F_GCR_PCLK_DIS1_UART2_POS 1
731 #define MXC_F_GCR_PCLK_DIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_UART2_POS))
733 #define MXC_F_GCR_PCLK_DIS1_TRNG_POS 2
734 #define MXC_F_GCR_PCLK_DIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_TRNG_POS))
736 #define MXC_F_GCR_PCLK_DIS1_SCACHE_POS 7
737 #define MXC_F_GCR_PCLK_DIS1_SCACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SCACHE_POS))
739 #define MXC_F_GCR_PCLK_DIS1_SDMA_POS 8
740 #define MXC_F_GCR_PCLK_DIS1_SDMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDMA_POS))
742 #define MXC_F_GCR_PCLK_DIS1_SMPHR_POS 9
743 #define MXC_F_GCR_PCLK_DIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SMPHR_POS))
745 #define MXC_F_GCR_PCLK_DIS1_SDHC_POS 10
746 #define MXC_F_GCR_PCLK_DIS1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDHC_POS))
748 #define MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS 12
749 #define MXC_F_GCR_PCLK_DIS1_ICACHEXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS))
751 #define MXC_F_GCR_PCLK_DIS1_OW_POS 13
752 #define MXC_F_GCR_PCLK_DIS1_OW ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_OW_POS))
754 #define MXC_F_GCR_PCLK_DIS1_SPI3_POS 14
755 #define MXC_F_GCR_PCLK_DIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPI3_POS))
757 #define MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS 20
758 #define MXC_F_GCR_PCLK_DIS1_SPIXIPR ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS))
760 #define MXC_F_GCR_PCLK_DIS1_DMA1_POS 21
761 #define MXC_F_GCR_PCLK_DIS1_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_DMA1_POS))
763 #define MXC_F_GCR_PCLK_DIS1_AUDIO_POS 23
764 #define MXC_F_GCR_PCLK_DIS1_AUDIO ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_AUDIO_POS))
766 #define MXC_F_GCR_PCLK_DIS1_I2C2_POS 24
767 #define MXC_F_GCR_PCLK_DIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_I2C2_POS))
769 #define MXC_F_GCR_PCLK_DIS1_HTMR0_POS 25
770 #define MXC_F_GCR_PCLK_DIS1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_HTMR0_POS))
772 #define MXC_F_GCR_PCLK_DIS1_HTMR1_POS 26
773 #define MXC_F_GCR_PCLK_DIS1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_HTMR1_POS))
775 #define MXC_F_GCR_PCLK_DIS1_WDT0_POS 27
776 #define MXC_F_GCR_PCLK_DIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_WDT0_POS))
778 #define MXC_F_GCR_PCLK_DIS1_WDT1_POS 28
779 #define MXC_F_GCR_PCLK_DIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_WDT1_POS))
781 #define MXC_F_GCR_PCLK_DIS1_WDT2_POS 29
782 #define MXC_F_GCR_PCLK_DIS1_WDT2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_WDT2_POS))
784 #define MXC_F_GCR_PCLK_DIS1_CPU1_POS 31
785 #define MXC_F_GCR_PCLK_DIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_CPU1_POS))
795 #define MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT_POS 0
796 #define MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT_POS))
798 #define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS 1
799 #define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS))
801 #define MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS 2
802 #define MXC_F_GCR_EVENT_EN_CPU0TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS))
804 #define MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT_POS 3
805 #define MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT_POS))
807 #define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS 4
808 #define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS))
810 #define MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS 5
811 #define MXC_F_GCR_EVENT_EN_CPU1TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS))
821 #define MXC_F_GCR_REVISION_REVISION_POS 0
822 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS))
832 #define MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS 0
833 #define MXC_F_GCR_SYS_STAT_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS))
835 #define MXC_F_GCR_SYS_STAT_IE_CIEIE_POS 1
836 #define MXC_F_GCR_SYS_STAT_IE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_CIEIE_POS))
838 #define MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS 5
839 #define MXC_F_GCR_SYS_STAT_IE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS))
849 #define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS 0
850 #define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS))
852 #define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS 1
853 #define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS))
855 #define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS 2
856 #define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS))
858 #define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS 3
859 #define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS))
861 #define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS 4
862 #define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS))
864 #define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS 5
865 #define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS))
867 #define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS 6
868 #define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS))
870 #define MXC_F_GCR_ECC_ER_IC0ECCERR_POS 8
871 #define MXC_F_GCR_ECC_ER_IC0ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC0ECCERR_POS))
873 #define MXC_F_GCR_ECC_ER_IC1ECCERR_POS 9
874 #define MXC_F_GCR_ECC_ER_IC1ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC1ECCERR_POS))
876 #define MXC_F_GCR_ECC_ER_ICXIPECCERR_POS 10
877 #define MXC_F_GCR_ECC_ER_ICXIPECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_ICXIPECCERR_POS))
879 #define MXC_F_GCR_ECC_ER_FL0ECCERR_POS 11
880 #define MXC_F_GCR_ECC_ER_FL0ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL0ECCERR_POS))
882 #define MXC_F_GCR_ECC_ER_FL1ECCERR_POS 12
883 #define MXC_F_GCR_ECC_ER_FL1ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL1ECCERR_POS))
893 #define MXC_F_GCR_ECC_NDED_SYSRAM0ECCNDED_POS 0
894 #define MXC_F_GCR_ECC_NDED_SYSRAM0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM0ECCNDED_POS))
896 #define MXC_F_GCR_ECC_NDED_SYSRAM1ECCNDED_POS 1
897 #define MXC_F_GCR_ECC_NDED_SYSRAM1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM1ECCNDED_POS))
899 #define MXC_F_GCR_ECC_NDED_SYSRAM2ECCNDED_POS 2
900 #define MXC_F_GCR_ECC_NDED_SYSRAM2ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM2ECCNDED_POS))
902 #define MXC_F_GCR_ECC_NDED_SYSRAM3ECCNDED_POS 3
903 #define MXC_F_GCR_ECC_NDED_SYSRAM3ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM3ECCNDED_POS))
905 #define MXC_F_GCR_ECC_NDED_SYSRAM4ECCNDED_POS 4
906 #define MXC_F_GCR_ECC_NDED_SYSRAM4ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM4ECCNDED_POS))
908 #define MXC_F_GCR_ECC_NDED_SYSRAM5ECCNDED_POS 5
909 #define MXC_F_GCR_ECC_NDED_SYSRAM5ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM5ECCNDED_POS))
911 #define MXC_F_GCR_ECC_NDED_SYSRAM6ECCNDED_POS 6
912 #define MXC_F_GCR_ECC_NDED_SYSRAM6ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_SYSRAM6ECCNDED_POS))
914 #define MXC_F_GCR_ECC_NDED_IC0ECCNDED_POS 8
915 #define MXC_F_GCR_ECC_NDED_IC0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_IC0ECCNDED_POS))
917 #define MXC_F_GCR_ECC_NDED_IC1ECCNDED_POS 9
918 #define MXC_F_GCR_ECC_NDED_IC1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_IC1ECCNDED_POS))
920 #define MXC_F_GCR_ECC_NDED_ICXIPECCNDED_POS 10
921 #define MXC_F_GCR_ECC_NDED_ICXIPECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_ICXIPECCNDED_POS))
923 #define MXC_F_GCR_ECC_NDED_FL0ECCNDED_POS 11
924 #define MXC_F_GCR_ECC_NDED_FL0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_FL0ECCNDED_POS))
926 #define MXC_F_GCR_ECC_NDED_FL1ECCNDED_POS 12
927 #define MXC_F_GCR_ECC_NDED_FL1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_NDED_FL1ECCNDED_POS))
937 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM0EN_POS 0
938 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM0EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM0EN_POS))
940 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM1EN_POS 1
941 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM1EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM1EN_POS))
943 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM2EN_POS 2
944 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM2EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM2EN_POS))
946 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM3EN_POS 3
947 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM3EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM3EN_POS))
949 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM4EN_POS 4
950 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM4EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM4EN_POS))
952 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM5EN_POS 5
953 #define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM5EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM5EN_POS))
955 #define MXC_F_GCR_ECC_IRQEN_SYSRAM6ECCEN_POS 6
956 #define MXC_F_GCR_ECC_IRQEN_SYSRAM6ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM6ECCEN_POS))
958 #define MXC_F_GCR_ECC_IRQEN_EC0ECCEN_POS 8
959 #define MXC_F_GCR_ECC_IRQEN_EC0ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_EC0ECCEN_POS))
961 #define MXC_F_GCR_ECC_IRQEN_EC1ECCEN_POS 9
962 #define MXC_F_GCR_ECC_IRQEN_EC1ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_EC1ECCEN_POS))
964 #define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS 10
965 #define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS))
967 #define MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS 11
968 #define MXC_F_GCR_ECC_IRQEN_FL0ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS))
970 #define MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS 12
971 #define MXC_F_GCR_ECC_IRQEN_FL1ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS))
981 #define MXC_F_GCR_ECC_ERRAD_DATARAMADDR_POS 0
982 #define MXC_F_GCR_ECC_ERRAD_DATARAMADDR ((uint32_t)(0x1FFFUL << MXC_F_GCR_ECC_ERRAD_DATARAMADDR_POS))
984 #define MXC_F_GCR_ECC_ERRAD_DATARAMBANK_POS 14
985 #define MXC_F_GCR_ECC_ERRAD_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_DATARAMBANK_POS))
987 #define MXC_F_GCR_ECC_ERRAD_DATARAMERR_POS 15
988 #define MXC_F_GCR_ECC_ERRAD_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_DATARAMERR_POS))
990 #define MXC_F_GCR_ECC_ERRAD_TAGRAMADDR_POS 16
991 #define MXC_F_GCR_ECC_ERRAD_TAGRAMADDR ((uint32_t)(0x1FFFUL << MXC_F_GCR_ECC_ERRAD_TAGRAMADDR_POS))
993 #define MXC_F_GCR_ECC_ERRAD_TAGRAMBANK_POS 30
994 #define MXC_F_GCR_ECC_ERRAD_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_TAGRAMBANK_POS))
996 #define MXC_F_GCR_ECC_ERRAD_TAGRAMERR_POS 31
997 #define MXC_F_GCR_ECC_ERRAD_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_TAGRAMERR_POS))
1007 #define MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS 0
1008 #define MXC_F_GCR_BTLE_LDOCR_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS))
1010 #define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS 1
1011 #define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS))
1013 #define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS 2
1014 #define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS))
1015 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 ((uint32_t)0x0UL)
1016 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)
1017 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 ((uint32_t)0x1UL)
1018 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)
1019 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 ((uint32_t)0x2UL)
1020 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)
1021 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 ((uint32_t)0x3UL)
1022 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)
1024 #define MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS 4
1025 #define MXC_F_GCR_BTLE_LDOCR_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS))
1027 #define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS 5
1028 #define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS))
1030 #define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS 6
1031 #define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS))
1032 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 ((uint32_t)0x0UL)
1033 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)
1034 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 ((uint32_t)0x1UL)
1035 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)
1036 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 ((uint32_t)0x2UL)
1037 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)
1038 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 ((uint32_t)0x3UL)
1039 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)
1041 #define MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS 8
1042 #define MXC_F_GCR_BTLE_LDOCR_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS))
1044 #define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS 9
1045 #define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS))
1047 #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS 10
1048 #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS))
1050 #define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS 11
1051 #define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS))
1053 #define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS 12
1054 #define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS))
1056 #define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS 13
1057 #define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS))
1067 #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS 0
1068 #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS))
1070 #define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS 8
1071 #define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS))
1073 #define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS 20
1074 #define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS))
1084 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS 0
1085 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS))
1087 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS 1
1088 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS))
1090 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS 2
1091 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS))
1093 #define MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS 3
1094 #define MXC_F_GCR_APB_ASYNC_APBASYNCPT ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS))
__IO uint32_t btle_ldocr
Definition: gcr_regs.h:114
__IO uint32_t pclk_dis0
Definition: gcr_regs.h:96
__IO uint32_t rst1
Definition: gcr_regs.h:104
__IO uint32_t event_en
Definition: gcr_regs.h:106
__IO uint32_t mem_zero
Definition: gcr_regs.h:98
__IO uint32_t mpri0
Definition: gcr_regs.h:101
__I uint32_t revision
Definition: gcr_regs.h:107
__IO uint32_t sys_stat
Definition: gcr_regs.h:103
__IO uint32_t ecc_irqen
Definition: gcr_regs.h:112
__IO uint32_t mpri1
Definition: gcr_regs.h:102
__IO uint32_t clk_ctrl
Definition: gcr_regs.h:91
__IO uint32_t mem_clk
Definition: gcr_regs.h:97
__IO uint32_t ecc_nded
Definition: gcr_regs.h:111
__IO uint32_t gpr0
Definition: gcr_regs.h:117
__IO uint32_t scon
Definition: gcr_regs.h:89
__IO uint32_t pclk_div
Definition: gcr_regs.h:94
__IO uint32_t pclk_dis1
Definition: gcr_regs.h:105
__IO uint32_t btle_ldodcr
Definition: gcr_regs.h:115
Definition: gcr_regs.h:88
__IO uint32_t rst0
Definition: gcr_regs.h:90
__IO uint32_t sys_stat_ie
Definition: gcr_regs.h:108
__IO uint32_t ecc_er
Definition: gcr_regs.h:110
__IO uint32_t apb_async
Definition: gcr_regs.h:118
__IO uint32_t ecc_errad
Definition: gcr_regs.h:113
__IO uint32_t pmr
Definition: gcr_regs.h:92
__IO uint32_t scck
Definition: gcr_regs.h:100