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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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SPI XIP Master FIFO Protection Register.
#define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS)) |
SPIXM_FIFO_CRYPTOACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS 14 |
SPIXM_FIFO_CRYPTOACNR Position
#define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS)) |
SPIXM_FIFO_CRYPTOACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS 15 |
SPIXM_FIFO_CRYPTOACNW Position
#define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS)) |
SPIXM_FIFO_DMA0ACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS 0 |
SPIXM_FIFO_DMA0ACNR Position
#define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS)) |
SPIXM_FIFO_DMA0ACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS 1 |
SPIXM_FIFO_DMA0ACNW Position
#define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS)) |
SPIXM_FIFO_DMA1ACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS 2 |
SPIXM_FIFO_DMA1ACNR Position
#define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS)) |
SPIXM_FIFO_DMA1ACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS 3 |
SPIXM_FIFO_DMA1ACNW Position
#define MXC_F_RPU_SPIXM_FIFO_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS)) |
SPIXM_FIFO_SDIOACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS 16 |
SPIXM_FIFO_SDIOACNR Position
#define MXC_F_RPU_SPIXM_FIFO_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS)) |
SPIXM_FIFO_SDIOACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS 17 |
SPIXM_FIFO_SDIOACNW Position
#define MXC_F_RPU_SPIXM_FIFO_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS)) |
SPIXM_FIFO_SDMADACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS 10 |
SPIXM_FIFO_SDMADACNR Position
#define MXC_F_RPU_SPIXM_FIFO_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS)) |
SPIXM_FIFO_SDMADACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS 11 |
SPIXM_FIFO_SDMADACNW Position
#define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS)) |
SPIXM_FIFO_SDMAIACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS 12 |
SPIXM_FIFO_SDMAIACNR Position
#define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS)) |
SPIXM_FIFO_SDMAIACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS 13 |
SPIXM_FIFO_SDMAIACNW Position
#define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS)) |
SPIXM_FIFO_SYS0ACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS 6 |
SPIXM_FIFO_SYS0ACNR Position
#define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS)) |
SPIXM_FIFO_SYS0ACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS 7 |
SPIXM_FIFO_SYS0ACNW Position
#define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS)) |
SPIXM_FIFO_SYS1ACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS 8 |
SPIXM_FIFO_SYS1ACNR Position
#define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS)) |
SPIXM_FIFO_SYS1ACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS 9 |
SPIXM_FIFO_SYS1ACNW Position
#define MXC_F_RPU_SPIXM_FIFO_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_USBACNR_POS)) |
SPIXM_FIFO_USBACNR Mask
#define MXC_F_RPU_SPIXM_FIFO_USBACNR_POS 4 |
SPIXM_FIFO_USBACNR Position
#define MXC_F_RPU_SPIXM_FIFO_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_USBACNW_POS)) |
SPIXM_FIFO_USBACNW Mask
#define MXC_F_RPU_SPIXM_FIFO_USBACNW_POS 5 |
SPIXM_FIFO_USBACNW Position