MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665

Macros

#define MXC_F_RPU_HTIMER0_DMA0ACN_POS   0
 
#define MXC_F_RPU_HTIMER0_DMA0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_DMA0ACN_POS))
 
#define MXC_F_RPU_HTIMER0_DMA1ACN_POS   1
 
#define MXC_F_RPU_HTIMER0_DMA1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_DMA1ACN_POS))
 
#define MXC_F_RPU_HTIMER0_USBACN_POS   2
 
#define MXC_F_RPU_HTIMER0_USBACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_USBACN_POS))
 
#define MXC_F_RPU_HTIMER0_SYS0ACN_POS   3
 
#define MXC_F_RPU_HTIMER0_SYS0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SYS0ACN_POS))
 
#define MXC_F_RPU_HTIMER0_SYS1ACN_POS   4
 
#define MXC_F_RPU_HTIMER0_SYS1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SYS1ACN_POS))
 
#define MXC_F_RPU_HTIMER0_SDMADACN_POS   5
 
#define MXC_F_RPU_HTIMER0_SDMADACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDMADACN_POS))
 
#define MXC_F_RPU_HTIMER0_SDMAIACN_POS   6
 
#define MXC_F_RPU_HTIMER0_SDMAIACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDMAIACN_POS))
 
#define MXC_F_RPU_HTIMER0_CRYPTOACN_POS   7
 
#define MXC_F_RPU_HTIMER0_CRYPTOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_CRYPTOACN_POS))
 
#define MXC_F_RPU_HTIMER0_SDIOACN_POS   8
 
#define MXC_F_RPU_HTIMER0_SDIOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDIOACN_POS))
 

Detailed Description

HTimer0 Protection Register.

Macro Definition Documentation

◆ MXC_F_RPU_HTIMER0_CRYPTOACN

#define MXC_F_RPU_HTIMER0_CRYPTOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_CRYPTOACN_POS))

HTIMER0_CRYPTOACN Mask

◆ MXC_F_RPU_HTIMER0_CRYPTOACN_POS

#define MXC_F_RPU_HTIMER0_CRYPTOACN_POS   7

HTIMER0_CRYPTOACN Position

◆ MXC_F_RPU_HTIMER0_DMA0ACN

#define MXC_F_RPU_HTIMER0_DMA0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_DMA0ACN_POS))

HTIMER0_DMA0ACN Mask

◆ MXC_F_RPU_HTIMER0_DMA0ACN_POS

#define MXC_F_RPU_HTIMER0_DMA0ACN_POS   0

HTIMER0_DMA0ACN Position

◆ MXC_F_RPU_HTIMER0_DMA1ACN

#define MXC_F_RPU_HTIMER0_DMA1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_DMA1ACN_POS))

HTIMER0_DMA1ACN Mask

◆ MXC_F_RPU_HTIMER0_DMA1ACN_POS

#define MXC_F_RPU_HTIMER0_DMA1ACN_POS   1

HTIMER0_DMA1ACN Position

◆ MXC_F_RPU_HTIMER0_SDIOACN

#define MXC_F_RPU_HTIMER0_SDIOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDIOACN_POS))

HTIMER0_SDIOACN Mask

◆ MXC_F_RPU_HTIMER0_SDIOACN_POS

#define MXC_F_RPU_HTIMER0_SDIOACN_POS   8

HTIMER0_SDIOACN Position

◆ MXC_F_RPU_HTIMER0_SDMADACN

#define MXC_F_RPU_HTIMER0_SDMADACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDMADACN_POS))

HTIMER0_SDMADACN Mask

◆ MXC_F_RPU_HTIMER0_SDMADACN_POS

#define MXC_F_RPU_HTIMER0_SDMADACN_POS   5

HTIMER0_SDMADACN Position

◆ MXC_F_RPU_HTIMER0_SDMAIACN

#define MXC_F_RPU_HTIMER0_SDMAIACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDMAIACN_POS))

HTIMER0_SDMAIACN Mask

◆ MXC_F_RPU_HTIMER0_SDMAIACN_POS

#define MXC_F_RPU_HTIMER0_SDMAIACN_POS   6

HTIMER0_SDMAIACN Position

◆ MXC_F_RPU_HTIMER0_SYS0ACN

#define MXC_F_RPU_HTIMER0_SYS0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SYS0ACN_POS))

HTIMER0_SYS0ACN Mask

◆ MXC_F_RPU_HTIMER0_SYS0ACN_POS

#define MXC_F_RPU_HTIMER0_SYS0ACN_POS   3

HTIMER0_SYS0ACN Position

◆ MXC_F_RPU_HTIMER0_SYS1ACN

#define MXC_F_RPU_HTIMER0_SYS1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SYS1ACN_POS))

HTIMER0_SYS1ACN Mask

◆ MXC_F_RPU_HTIMER0_SYS1ACN_POS

#define MXC_F_RPU_HTIMER0_SYS1ACN_POS   4

HTIMER0_SYS1ACN Position

◆ MXC_F_RPU_HTIMER0_USBACN

#define MXC_F_RPU_HTIMER0_USBACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_USBACN_POS))

HTIMER0_USBACN Mask

◆ MXC_F_RPU_HTIMER0_USBACN_POS

#define MXC_F_RPU_HTIMER0_USBACN_POS   2

HTIMER0_USBACN Position