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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros | |
#define | MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT_POS 0 |
#define | MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT_POS)) |
#define | MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS 1 |
#define | MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS)) |
#define | MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS 2 |
#define | MXC_F_GCR_EVENT_EN_CPU0TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS)) |
#define | MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT_POS 3 |
#define | MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT_POS)) |
#define | MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS 4 |
#define | MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS)) |
#define | MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS 5 |
#define | MXC_F_GCR_EVENT_EN_CPU1TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS)) |
Event Enable Register.
#define MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT_POS)) |
EVENT_EN_CPU0DMA0EVENT Mask
#define MXC_F_GCR_EVENT_EN_CPU0DMA0EVENT_POS 0 |
EVENT_EN_CPU0DMA0EVENT Position
#define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS)) |
EVENT_EN_CPU0DMA1EVENT Mask
#define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS 1 |
EVENT_EN_CPU0DMA1EVENT Position
#define MXC_F_GCR_EVENT_EN_CPU0TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS)) |
EVENT_EN_CPU0TXEVENT Mask
#define MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS 2 |
EVENT_EN_CPU0TXEVENT Position
#define MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT_POS)) |
EVENT_EN_CPU1DMA0EVENT Mask
#define MXC_F_GCR_EVENT_EN_CPU1DMA0EVENT_POS 3 |
EVENT_EN_CPU1DMA0EVENT Position
#define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS)) |
EVENT_EN_CPU1DMA1EVENT Mask
#define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS 4 |
EVENT_EN_CPU1DMA1EVENT Position
#define MXC_F_GCR_EVENT_EN_CPU1TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS)) |
EVENT_EN_CPU1TXEVENT Mask
#define MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS 5 |
EVENT_EN_CPU1TXEVENT Position