MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
sdhc_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
8  *
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14  * Software is furnished to do so, subject to the following conditions:
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20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25  * OTHER DEALINGS IN THE SOFTWARE.
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31  * The mere transfer of this software does not imply any licenses
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39 
40 #ifndef _SDHC_REGS_H_
41 #define _SDHC_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t sdma;
90  __IO uint16_t blk_size;
91  __IO uint16_t blk_cnt;
92  __IO uint32_t arg_1;
93  __IO uint16_t trans;
94  __IO uint16_t cmd;
95  __IO uint32_t resp[4];
96  __IO uint32_t buffer;
97  __I uint32_t present;
98  __IO uint8_t host_cn_1;
99  __IO uint8_t pwr;
100  __IO uint8_t blk_gap;
101  __IO uint8_t wakeup;
102  __IO uint16_t clk_cn;
103  __IO uint8_t to;
104  __IO uint8_t sw_reset;
105  __IO uint16_t int_stat;
106  __IO uint16_t er_int_stat;
107  __IO uint16_t int_en;
108  __IO uint16_t er_int_en;
109  __IO uint16_t int_signal;
110  __IO uint16_t er_int_signal;
111  __IO uint16_t auto_cmd_er;
112  __IO uint16_t host_cn_2;
113  __I uint32_t cfg_0;
114  __I uint32_t cfg_1;
115  __I uint32_t max_curr_cfg;
116  __R uint32_t rsv_0x4c;
117  __O uint16_t force_cmd;
118  __IO uint16_t force_event_int_stat;
119  __IO uint8_t adma_er;
120  __R uint8_t rsv_0x55_0x57[3];
121  __IO uint32_t adma_addr_0;
122  __IO uint32_t adma_addr_1;
123  __I uint16_t preset_0;
124  __I uint16_t preset_1;
125  __I uint16_t preset_2;
126  __I uint16_t preset_3;
127  __I uint16_t preset_4;
128  __I uint16_t preset_5;
129  __I uint16_t preset_6;
130  __I uint16_t preset_7;
131  __R uint32_t rsv_0x70_0xdf[28];
132  __IO uint32_t shared_bus;
133  __R uint32_t rsv_0xe4_0xfb[6];
134  __I uint16_t slot_int;
135  __IO uint16_t host_cn_ver;
137 
138 /* Register offsets for module SDHC */
145  #define MXC_R_SDHC_SDMA ((uint32_t)0x00000000UL)
146  #define MXC_R_SDHC_BLK_SIZE ((uint32_t)0x00000004UL)
147  #define MXC_R_SDHC_BLK_CNT ((uint32_t)0x00000006UL)
148  #define MXC_R_SDHC_ARG_1 ((uint32_t)0x00000008UL)
149  #define MXC_R_SDHC_TRANS ((uint32_t)0x0000000CUL)
150  #define MXC_R_SDHC_CMD ((uint32_t)0x0000000EUL)
151  #define MXC_R_SDHC_RESP ((uint32_t)0x00000010UL)
152  #define MXC_R_SDHC_BUFFER ((uint32_t)0x00000020UL)
153  #define MXC_R_SDHC_PRESENT ((uint32_t)0x00000024UL)
154  #define MXC_R_SDHC_HOST_CN_1 ((uint32_t)0x00000028UL)
155  #define MXC_R_SDHC_PWR ((uint32_t)0x00000029UL)
156  #define MXC_R_SDHC_BLK_GAP ((uint32_t)0x0000002AUL)
157  #define MXC_R_SDHC_WAKEUP ((uint32_t)0x0000002BUL)
158  #define MXC_R_SDHC_CLK_CN ((uint32_t)0x0000002CUL)
159  #define MXC_R_SDHC_TO ((uint32_t)0x0000002EUL)
160  #define MXC_R_SDHC_SW_RESET ((uint32_t)0x0000002FUL)
161  #define MXC_R_SDHC_INT_STAT ((uint32_t)0x00000030UL)
162  #define MXC_R_SDHC_ER_INT_STAT ((uint32_t)0x00000032UL)
163  #define MXC_R_SDHC_INT_EN ((uint32_t)0x00000034UL)
164  #define MXC_R_SDHC_ER_INT_EN ((uint32_t)0x00000036UL)
165  #define MXC_R_SDHC_INT_SIGNAL ((uint32_t)0x00000038UL)
166  #define MXC_R_SDHC_ER_INT_SIGNAL ((uint32_t)0x0000003AUL)
167  #define MXC_R_SDHC_AUTO_CMD_ER ((uint32_t)0x0000003CUL)
168  #define MXC_R_SDHC_HOST_CN_2 ((uint32_t)0x0000003EUL)
169  #define MXC_R_SDHC_CFG_0 ((uint32_t)0x00000040UL)
170  #define MXC_R_SDHC_CFG_1 ((uint32_t)0x00000044UL)
171  #define MXC_R_SDHC_MAX_CURR_CFG ((uint32_t)0x00000048UL)
172  #define MXC_R_SDHC_FORCE_CMD ((uint32_t)0x00000050UL)
173  #define MXC_R_SDHC_FORCE_EVENT_INT_STAT ((uint32_t)0x00000052UL)
174  #define MXC_R_SDHC_ADMA_ER ((uint32_t)0x00000054UL)
175  #define MXC_R_SDHC_ADMA_ADDR_0 ((uint32_t)0x00000058UL)
176  #define MXC_R_SDHC_ADMA_ADDR_1 ((uint32_t)0x0000005CUL)
177  #define MXC_R_SDHC_PRESET_0 ((uint32_t)0x00000060UL)
178  #define MXC_R_SDHC_PRESET_1 ((uint32_t)0x00000062UL)
179  #define MXC_R_SDHC_PRESET_2 ((uint32_t)0x00000064UL)
180  #define MXC_R_SDHC_PRESET_3 ((uint32_t)0x00000066UL)
181  #define MXC_R_SDHC_PRESET_4 ((uint32_t)0x00000068UL)
182  #define MXC_R_SDHC_PRESET_5 ((uint32_t)0x0000006AUL)
183  #define MXC_R_SDHC_PRESET_6 ((uint32_t)0x0000006CUL)
184  #define MXC_R_SDHC_PRESET_7 ((uint32_t)0x0000006EUL)
185  #define MXC_R_SDHC_SHARED_BUS ((uint32_t)0x000000E0UL)
186  #define MXC_R_SDHC_SLOT_INT ((uint32_t)0x000000FCUL)
187  #define MXC_R_SDHC_HOST_CN_VER ((uint32_t)0x000000FEUL)
196  #define MXC_F_SDHC_SDMA_ADDR_POS 0
197  #define MXC_F_SDHC_SDMA_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_SDMA_ADDR_POS))
207  #define MXC_F_SDHC_BLK_SIZE_TRANS_POS 0
208  #define MXC_F_SDHC_BLK_SIZE_TRANS ((uint16_t)(0xFFFUL << MXC_F_SDHC_BLK_SIZE_TRANS_POS))
210  #define MXC_F_SDHC_BLK_SIZE_HOST_BUFF_POS 12
211  #define MXC_F_SDHC_BLK_SIZE_HOST_BUFF ((uint16_t)(0x7UL << MXC_F_SDHC_BLK_SIZE_HOST_BUFF_POS))
221  #define MXC_F_SDHC_BLK_CNT_COUNT_POS 0
222  #define MXC_F_SDHC_BLK_CNT_COUNT ((uint16_t)(0xFFFFUL << MXC_F_SDHC_BLK_CNT_COUNT_POS))
232  #define MXC_F_SDHC_ARG_1_CMD_POS 0
233  #define MXC_F_SDHC_ARG_1_CMD ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ARG_1_CMD_POS))
243  #define MXC_F_SDHC_TRANS_DMA_EN_POS 0
244  #define MXC_F_SDHC_TRANS_DMA_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_DMA_EN_POS))
246  #define MXC_F_SDHC_TRANS_BLK_CNT_EN_POS 1
247  #define MXC_F_SDHC_TRANS_BLK_CNT_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_BLK_CNT_EN_POS))
249  #define MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS 2
250  #define MXC_F_SDHC_TRANS_AUTO_CMD_EN ((uint16_t)(0x3UL << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS))
251  #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE ((uint16_t)0x0UL)
252  #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_DISABLE (MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS)
253  #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 ((uint16_t)0x1UL)
254  #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD12 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS)
255  #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 ((uint16_t)0x2UL)
256  #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD23 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS)
258  #define MXC_F_SDHC_TRANS_READ_WRITE_POS 4
259  #define MXC_F_SDHC_TRANS_READ_WRITE ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_READ_WRITE_POS))
261  #define MXC_F_SDHC_TRANS_MULTI_POS 5
262  #define MXC_F_SDHC_TRANS_MULTI ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_MULTI_POS))
272  #define MXC_F_SDHC_CMD_RESP_TYPE_POS 0
273  #define MXC_F_SDHC_CMD_RESP_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_RESP_TYPE_POS))
275  #define MXC_F_SDHC_CMD_CRC_CHK_EN_POS 3
276  #define MXC_F_SDHC_CMD_CRC_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_CRC_CHK_EN_POS))
278  #define MXC_F_SDHC_CMD_IDX_CHK_EN_POS 4
279  #define MXC_F_SDHC_CMD_IDX_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_IDX_CHK_EN_POS))
281  #define MXC_F_SDHC_CMD_DATA_PRES_SEL_POS 5
282  #define MXC_F_SDHC_CMD_DATA_PRES_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_DATA_PRES_SEL_POS))
284  #define MXC_F_SDHC_CMD_TYPE_POS 6
285  #define MXC_F_SDHC_CMD_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_TYPE_POS))
287  #define MXC_F_SDHC_CMD_IDX_POS 8
288  #define MXC_F_SDHC_CMD_IDX ((uint16_t)(0x3FUL << MXC_F_SDHC_CMD_IDX_POS))
298  #define MXC_F_SDHC_RESP_CMD_RESP_POS 0
299  #define MXC_F_SDHC_RESP_CMD_RESP ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_RESP_CMD_RESP_POS))
309  #define MXC_F_SDHC_BUFFER_DATA_POS 0
310  #define MXC_F_SDHC_BUFFER_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_BUFFER_DATA_POS))
320  #define MXC_F_SDHC_PRESENT_CMD_POS 0
321  #define MXC_F_SDHC_PRESENT_CMD ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_POS))
323  #define MXC_F_SDHC_PRESENT_DAT_POS 1
324  #define MXC_F_SDHC_PRESENT_DAT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_POS))
326  #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS 2
327  #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS))
329  #define MXC_F_SDHC_PRESENT_RETUNING_POS 3
330  #define MXC_F_SDHC_PRESENT_RETUNING ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_RETUNING_POS))
332  #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS 8
333  #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS))
335  #define MXC_F_SDHC_PRESENT_READ_TRANSFER_POS 9
336  #define MXC_F_SDHC_PRESENT_READ_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_READ_TRANSFER_POS))
338  #define MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS 10
339  #define MXC_F_SDHC_PRESENT_BUFFER_WRITE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS))
341  #define MXC_F_SDHC_PRESENT_BUFFER_READ_POS 11
342  #define MXC_F_SDHC_PRESENT_BUFFER_READ ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_READ_POS))
344  #define MXC_F_SDHC_PRESENT_CARD_INSERTED_POS 16
345  #define MXC_F_SDHC_PRESENT_CARD_INSERTED ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_INSERTED_POS))
347  #define MXC_F_SDHC_PRESENT_CARD_STATE_POS 17
348  #define MXC_F_SDHC_PRESENT_CARD_STATE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_STATE_POS))
350  #define MXC_F_SDHC_PRESENT_CARD_DETECT_POS 18
351  #define MXC_F_SDHC_PRESENT_CARD_DETECT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_DETECT_POS))
353  #define MXC_F_SDHC_PRESENT_WP_POS 19
354  #define MXC_F_SDHC_PRESENT_WP ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WP_POS))
356  #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS 20
357  #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL ((uint32_t)(0xFUL << MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS))
359  #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS 24
360  #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS))
370  #define MXC_F_SDHC_HOST_CN_1_LED_CN_POS 0
371  #define MXC_F_SDHC_HOST_CN_1_LED_CN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_LED_CN_POS))
373  #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS 1
374  #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS))
376  #define MXC_F_SDHC_HOST_CN_1_HS_EN_POS 2
377  #define MXC_F_SDHC_HOST_CN_1_HS_EN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_HS_EN_POS))
379  #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS 3
380  #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT ((uint8_t)(0x3UL << MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS))
382  #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS 5
383  #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS))
385  #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS 6
386  #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS))
388  #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS 7
389  #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS))
399  #define MXC_F_SDHC_PWR_BUS_POWER_POS 0
400  #define MXC_F_SDHC_PWR_BUS_POWER ((uint8_t)(0x1UL << MXC_F_SDHC_PWR_BUS_POWER_POS))
402  #define MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS 1
403  #define MXC_F_SDHC_PWR_BUS_VOLT_SEL ((uint8_t)(0x7UL << MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS))
413  #define MXC_F_SDHC_BLK_GAP_STOP_POS 0
414  #define MXC_F_SDHC_BLK_GAP_STOP ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_STOP_POS))
416  #define MXC_F_SDHC_BLK_GAP_CONT_POS 1
417  #define MXC_F_SDHC_BLK_GAP_CONT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_CONT_POS))
419  #define MXC_F_SDHC_BLK_GAP_READ_WAIT_POS 2
420  #define MXC_F_SDHC_BLK_GAP_READ_WAIT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_READ_WAIT_POS))
422  #define MXC_F_SDHC_BLK_GAP_INTR_POS 3
423  #define MXC_F_SDHC_BLK_GAP_INTR ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_INTR_POS))
433  #define MXC_F_SDHC_WAKEUP_CARD_INT_POS 0
434  #define MXC_F_SDHC_WAKEUP_CARD_INT ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INT_POS))
436  #define MXC_F_SDHC_WAKEUP_CARD_INS_POS 1
437  #define MXC_F_SDHC_WAKEUP_CARD_INS ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INS_POS))
439  #define MXC_F_SDHC_WAKEUP_CARD_REM_POS 2
440  #define MXC_F_SDHC_WAKEUP_CARD_REM ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_REM_POS))
450  #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS 0
451  #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS))
453  #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS 1
454  #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS))
456  #define MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS 2
457  #define MXC_F_SDHC_CLK_CN_SD_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS))
459  #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS 5
460  #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS))
462  #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS 6
463  #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL ((uint16_t)(0x3UL << MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS))
465  #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS 8
466  #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL ((uint16_t)(0xFFUL << MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS))
476  #define MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS 0
477  #define MXC_F_SDHC_TO_DATA_COUNT_VALUE ((uint8_t)(0x7UL << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS))
487  #define MXC_F_SDHC_SW_RESET_RESET_ALL_POS 0
488  #define MXC_F_SDHC_SW_RESET_RESET_ALL ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_ALL_POS))
490  #define MXC_F_SDHC_SW_RESET_RESET_CMD_POS 1
491  #define MXC_F_SDHC_SW_RESET_RESET_CMD ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_CMD_POS))
493  #define MXC_F_SDHC_SW_RESET_RESET_DAT_POS 2
494  #define MXC_F_SDHC_SW_RESET_RESET_DAT ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_DAT_POS))
504  #define MXC_F_SDHC_INT_STAT_CMD_COMP_POS 0
505  #define MXC_F_SDHC_INT_STAT_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CMD_COMP_POS))
507  #define MXC_F_SDHC_INT_STAT_TRANS_COMP_POS 1
508  #define MXC_F_SDHC_INT_STAT_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_TRANS_COMP_POS))
510  #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS 2
511  #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS))
513  #define MXC_F_SDHC_INT_STAT_DMA_POS 3
514  #define MXC_F_SDHC_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_DMA_POS))
516  #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS 4
517  #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS))
519  #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS 5
520  #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS))
522  #define MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS 6
523  #define MXC_F_SDHC_INT_STAT_CARD_INSERTION ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS))
525  #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS 7
526  #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS))
528  #define MXC_F_SDHC_INT_STAT_CARD_INTR_POS 8
529  #define MXC_F_SDHC_INT_STAT_CARD_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INTR_POS))
531  #define MXC_F_SDHC_INT_STAT_RETUNING_POS 12
532  #define MXC_F_SDHC_INT_STAT_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_RETUNING_POS))
534  #define MXC_F_SDHC_INT_STAT_ERR_INTR_POS 15
535  #define MXC_F_SDHC_INT_STAT_ERR_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_ERR_INTR_POS))
545  #define MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS 0
546  #define MXC_F_SDHC_ER_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS))
548  #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS 1
549  #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS))
551  #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS 2
552  #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS))
554  #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS 3
555  #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS))
557  #define MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS 4
558  #define MXC_F_SDHC_ER_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS))
560  #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS 5
561  #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS))
563  #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS 6
564  #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS))
566  #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS 7
567  #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS))
569  #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS 8
570  #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12 ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS))
572  #define MXC_F_SDHC_ER_INT_STAT_ADMA_POS 9
573  #define MXC_F_SDHC_ER_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_ADMA_POS))
575  #define MXC_F_SDHC_ER_INT_STAT_DMA_POS 12
576  #define MXC_F_SDHC_ER_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DMA_POS))
586  #define MXC_F_SDHC_INT_EN_CMD_COMP_POS 0
587  #define MXC_F_SDHC_INT_EN_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CMD_COMP_POS))
589  #define MXC_F_SDHC_INT_EN_TRANS_COMP_POS 1
590  #define MXC_F_SDHC_INT_EN_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_TRANS_COMP_POS))
592  #define MXC_F_SDHC_INT_EN_BLK_GAP_POS 2
593  #define MXC_F_SDHC_INT_EN_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BLK_GAP_POS))
595  #define MXC_F_SDHC_INT_EN_DMA_POS 3
596  #define MXC_F_SDHC_INT_EN_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_DMA_POS))
598  #define MXC_F_SDHC_INT_EN_BUFFER_WR_POS 4
599  #define MXC_F_SDHC_INT_EN_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_WR_POS))
601  #define MXC_F_SDHC_INT_EN_BUFFER_RD_POS 5
602  #define MXC_F_SDHC_INT_EN_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_RD_POS))
604  #define MXC_F_SDHC_INT_EN_CARD_INSERT_POS 6
605  #define MXC_F_SDHC_INT_EN_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INSERT_POS))
607  #define MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS 7
608  #define MXC_F_SDHC_INT_EN_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS))
610  #define MXC_F_SDHC_INT_EN_CARD_INT_POS 8
611  #define MXC_F_SDHC_INT_EN_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INT_POS))
613  #define MXC_F_SDHC_INT_EN_RETUNING_POS 12
614  #define MXC_F_SDHC_INT_EN_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_RETUNING_POS))
624  #define MXC_F_SDHC_ER_INT_EN_CMD_TO_POS 0
625  #define MXC_F_SDHC_ER_INT_EN_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_TO_POS))
627  #define MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS 1
628  #define MXC_F_SDHC_ER_INT_EN_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS))
630  #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS 2
631  #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS))
633  #define MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS 3
634  #define MXC_F_SDHC_ER_INT_EN_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS))
636  #define MXC_F_SDHC_ER_INT_EN_DATA_TO_POS 4
637  #define MXC_F_SDHC_ER_INT_EN_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_TO_POS))
639  #define MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS 5
640  #define MXC_F_SDHC_ER_INT_EN_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS))
642  #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS 6
643  #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS))
645  #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD_POS 8
646  #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_AUTO_CMD_POS))
648  #define MXC_F_SDHC_ER_INT_EN_ADMA_POS 9
649  #define MXC_F_SDHC_ER_INT_EN_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_ADMA_POS))
651  #define MXC_F_SDHC_ER_INT_EN_TUNING_POS 10
652  #define MXC_F_SDHC_ER_INT_EN_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_TUNING_POS))
654  #define MXC_F_SDHC_ER_INT_EN_VENDOR_POS 12
655  #define MXC_F_SDHC_ER_INT_EN_VENDOR ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_VENDOR_POS))
665  #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS 0
666  #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS))
668  #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS 1
669  #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS))
671  #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS 2
672  #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS))
674  #define MXC_F_SDHC_INT_SIGNAL_DMA_POS 3
675  #define MXC_F_SDHC_INT_SIGNAL_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_DMA_POS))
677  #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS 4
678  #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS))
680  #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS 5
681  #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS))
683  #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS 6
684  #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS))
686  #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS 7
687  #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS))
689  #define MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS 8
690  #define MXC_F_SDHC_INT_SIGNAL_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS))
692  #define MXC_F_SDHC_INT_SIGNAL_RETUNING_POS 12
693  #define MXC_F_SDHC_INT_SIGNAL_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_RETUNING_POS))
703  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS 0
704  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS))
706  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS 1
707  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS))
709  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS 2
710  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS))
712  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS 3
713  #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS))
715  #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS 4
716  #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS))
718  #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS 5
719  #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS))
721  #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS 6
722  #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS))
724  #define MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM_POS 7
725  #define MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM_POS))
727  #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_POS 8
728  #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_POS))
730  #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS 9
731  #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS))
733  #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS 10
734  #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS))
736  #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS 12
737  #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS))
747  #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS 0
748  #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS))
750  #define MXC_F_SDHC_AUTO_CMD_ER_TO_POS 1
751  #define MXC_F_SDHC_AUTO_CMD_ER_TO ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_TO_POS))
753  #define MXC_F_SDHC_AUTO_CMD_ER_CRC_POS 2
754  #define MXC_F_SDHC_AUTO_CMD_ER_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_CRC_POS))
756  #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS 3
757  #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS))
759  #define MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS 4
760  #define MXC_F_SDHC_AUTO_CMD_ER_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS))
762  #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS 7
763  #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS))
773  #define MXC_F_SDHC_HOST_CN_2_UHS_POS 0
774  #define MXC_F_SDHC_HOST_CN_2_UHS ((uint16_t)(0x3UL << MXC_F_SDHC_HOST_CN_2_UHS_POS))
776  #define MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8_POS 3
777  #define MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8 ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8_POS))
779  #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS 4
780  #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS))
782  #define MXC_F_SDHC_HOST_CN_2_EXCUTE_POS 6
783  #define MXC_F_SDHC_HOST_CN_2_EXCUTE ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_EXCUTE_POS))
785  #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS 7
786  #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS))
788  #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS 14
789  #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS))
791  #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS 15
792  #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS))
802  #define MXC_F_SDHC_CFG_0_CLK_FREQ_POS 0
803  #define MXC_F_SDHC_CFG_0_CLK_FREQ ((uint32_t)(0x3FUL << MXC_F_SDHC_CFG_0_CLK_FREQ_POS))
805  #define MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS 7
806  #define MXC_F_SDHC_CFG_0_TO_CLK_UNIT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS))
808  #define MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS 8
809  #define MXC_F_SDHC_CFG_0_TO_CLK_FREQ ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS))
811  #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS 16
812  #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS))
814  #define MXC_F_SDHC_CFG_0_BIT_8_POS 18
815  #define MXC_F_SDHC_CFG_0_BIT_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_8_POS))
817  #define MXC_F_SDHC_CFG_0_ADMA2_POS 19
818  #define MXC_F_SDHC_CFG_0_ADMA2 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ADMA2_POS))
820  #define MXC_F_SDHC_CFG_0_HS_POS 21
821  #define MXC_F_SDHC_CFG_0_HS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_HS_POS))
823  #define MXC_F_SDHC_CFG_0_SDMA_POS 22
824  #define MXC_F_SDHC_CFG_0_SDMA ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SDMA_POS))
826  #define MXC_F_SDHC_CFG_0_SUSPEND_POS 23
827  #define MXC_F_SDHC_CFG_0_SUSPEND ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SUSPEND_POS))
829  #define MXC_F_SDHC_CFG_0_V3_3_POS 24
830  #define MXC_F_SDHC_CFG_0_V3_3 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_3_POS))
832  #define MXC_F_SDHC_CFG_0_V3_0_POS 25
833  #define MXC_F_SDHC_CFG_0_V3_0 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_0_POS))
835  #define MXC_F_SDHC_CFG_0_V1_8_POS 26
836  #define MXC_F_SDHC_CFG_0_V1_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V1_8_POS))
838  #define MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS 28
839  #define MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS))
841  #define MXC_F_SDHC_CFG_0_ASYNC_INT_POS 29
842  #define MXC_F_SDHC_CFG_0_ASYNC_INT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ASYNC_INT_POS))
844  #define MXC_F_SDHC_CFG_0_SLOT_TYPE_POS 30
845  #define MXC_F_SDHC_CFG_0_SLOT_TYPE ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_SLOT_TYPE_POS))
855  #define MXC_F_SDHC_CFG_1_SDR50_POS 0
856  #define MXC_F_SDHC_CFG_1_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS))
858  #define MXC_F_SDHC_CFG_1_SDR104_POS 1
859  #define MXC_F_SDHC_CFG_1_SDR104 ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS))
861  #define MXC_F_SDHC_CFG_1_DDR50_POS 2
862  #define MXC_F_SDHC_CFG_1_DDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS))
864  #define MXC_F_SDHC_CFG_1_DRIVER_A_POS 4
865  #define MXC_F_SDHC_CFG_1_DRIVER_A ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS))
867  #define MXC_F_SDHC_CFG_1_DRIVER_C_POS 5
868  #define MXC_F_SDHC_CFG_1_DRIVER_C ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS))
870  #define MXC_F_SDHC_CFG_1_DRIVER_D_POS 6
871  #define MXC_F_SDHC_CFG_1_DRIVER_D ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS))
873  #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS 8
874  #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS))
876  #define MXC_F_SDHC_CFG_1_TUNING_SDR50_POS 13
877  #define MXC_F_SDHC_CFG_1_TUNING_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS))
879  #define MXC_F_SDHC_CFG_1_RETUNING_POS 14
880  #define MXC_F_SDHC_CFG_1_RETUNING ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS))
882  #define MXC_F_SDHC_CFG_1_CLK_MULTI_POS 16
883  #define MXC_F_SDHC_CFG_1_CLK_MULTI ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS))
893  #define MXC_F_SDHC_MAX_CURR_CFG_V3_3_POS 0
894  #define MXC_F_SDHC_MAX_CURR_CFG_V3_3 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V3_3_POS))
896  #define MXC_F_SDHC_MAX_CURR_CFG_V3_0_POS 8
897  #define MXC_F_SDHC_MAX_CURR_CFG_V3_0 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V3_0_POS))
899  #define MXC_F_SDHC_MAX_CURR_CFG_V1_8_POS 16
900  #define MXC_F_SDHC_MAX_CURR_CFG_V1_8 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V1_8_POS))
910  #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS 0
911  #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS))
913  #define MXC_F_SDHC_FORCE_CMD_TO_POS 1
914  #define MXC_F_SDHC_FORCE_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_TO_POS))
916  #define MXC_F_SDHC_FORCE_CMD_CRC_POS 2
917  #define MXC_F_SDHC_FORCE_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_CRC_POS))
919  #define MXC_F_SDHC_FORCE_CMD_END_BIT_POS 3
920  #define MXC_F_SDHC_FORCE_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_END_BIT_POS))
922  #define MXC_F_SDHC_FORCE_CMD_INDEX_POS 4
923  #define MXC_F_SDHC_FORCE_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_INDEX_POS))
925  #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS 7
926  #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS))
936  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS 0
937  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS))
939  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS 1
940  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS))
942  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS 2
943  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS))
945  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS 3
946  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS))
948  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS 4
949  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS))
951  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS 5
952  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS))
954  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS 6
955  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS))
957  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS 7
958  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS))
960  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS 8
961  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS))
963  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS 9
964  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS))
966  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR_POS 12
967  #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR ((uint16_t)(0x7UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR_POS))
977  #define MXC_F_SDHC_ADMA_ER_STATE_POS 0
978  #define MXC_F_SDHC_ADMA_ER_STATE ((uint8_t)(0x3UL << MXC_F_SDHC_ADMA_ER_STATE_POS))
980  #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS 2
981  #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH ((uint8_t)(0x1UL << MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS))
991  #define MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS 0
992  #define MXC_F_SDHC_ADMA_ADDR_0_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS))
1002  #define MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS 0
1003  #define MXC_F_SDHC_ADMA_ADDR_1_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS))
1013  #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS 0
1014  #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS))
1016  #define MXC_F_SDHC_PRESET_0_CLK_GEN_POS 10
1017  #define MXC_F_SDHC_PRESET_0_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_0_CLK_GEN_POS))
1019  #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS 14
1020  #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS))
1030  #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS 0
1031  #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS))
1033  #define MXC_F_SDHC_PRESET_1_CLK_GEN_POS 10
1034  #define MXC_F_SDHC_PRESET_1_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_1_CLK_GEN_POS))
1036  #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS 14
1037  #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS))
1047  #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS 0
1048  #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS))
1050  #define MXC_F_SDHC_PRESET_2_CLK_GEN_POS 10
1051  #define MXC_F_SDHC_PRESET_2_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_2_CLK_GEN_POS))
1053  #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS 14
1054  #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS))
1064  #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS 0
1065  #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS))
1067  #define MXC_F_SDHC_PRESET_3_CLK_GEN_POS 10
1068  #define MXC_F_SDHC_PRESET_3_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_3_CLK_GEN_POS))
1070  #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS 14
1071  #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS))
1081  #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS 0
1082  #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS))
1084  #define MXC_F_SDHC_PRESET_4_CLK_GEN_POS 10
1085  #define MXC_F_SDHC_PRESET_4_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_4_CLK_GEN_POS))
1087  #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS 14
1088  #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS))
1098  #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS 0
1099  #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS))
1101  #define MXC_F_SDHC_PRESET_5_CLK_GEN_POS 10
1102  #define MXC_F_SDHC_PRESET_5_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_5_CLK_GEN_POS))
1104  #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS 14
1105  #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS))
1115  #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS 0
1116  #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS))
1118  #define MXC_F_SDHC_PRESET_6_CLK_GEN_POS 10
1119  #define MXC_F_SDHC_PRESET_6_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_6_CLK_GEN_POS))
1121  #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS 14
1122  #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS))
1132  #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS 0
1133  #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS))
1135  #define MXC_F_SDHC_PRESET_7_CLK_GEN_POS 10
1136  #define MXC_F_SDHC_PRESET_7_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_7_CLK_GEN_POS))
1138  #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS 14
1139  #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS))
1149  #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS 0
1150  #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS ((uint16_t)(0x1UL << MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS))
1160  #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS 0
1161  #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS))
1163  #define MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS 8
1164  #define MXC_F_SDHC_HOST_CN_VER_VEND_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS))
1168 #ifdef __cplusplus
1169 }
1170 #endif
1171 
1172 #endif /* _SDHC_REGS_H_ */
mxc_sdhc_regs_t::sw_reset
__IO uint8_t sw_reset
Definition: sdhc_regs.h:104
mxc_sdhc_regs_t::host_cn_2
__IO uint16_t host_cn_2
Definition: sdhc_regs.h:112
mxc_sdhc_regs_t::force_cmd
__O uint16_t force_cmd
Definition: sdhc_regs.h:117
mxc_sdhc_regs_t::adma_addr_0
__IO uint32_t adma_addr_0
Definition: sdhc_regs.h:121
mxc_sdhc_regs_t::er_int_stat
__IO uint16_t er_int_stat
Definition: sdhc_regs.h:106
mxc_sdhc_regs_t::to
__IO uint8_t to
Definition: sdhc_regs.h:103
mxc_sdhc_regs_t::buffer
__IO uint32_t buffer
Definition: sdhc_regs.h:96
mxc_sdhc_regs_t::trans
__IO uint16_t trans
Definition: sdhc_regs.h:93
mxc_sdhc_regs_t::cfg_1
__I uint32_t cfg_1
Definition: sdhc_regs.h:114
mxc_sdhc_regs_t::wakeup
__IO uint8_t wakeup
Definition: sdhc_regs.h:101
mxc_sdhc_regs_t::present
__I uint32_t present
Definition: sdhc_regs.h:97
mxc_sdhc_regs_t::max_curr_cfg
__I uint32_t max_curr_cfg
Definition: sdhc_regs.h:115
mxc_sdhc_regs_t::auto_cmd_er
__IO uint16_t auto_cmd_er
Definition: sdhc_regs.h:111
mxc_sdhc_regs_t::preset_6
__I uint16_t preset_6
Definition: sdhc_regs.h:129
mxc_sdhc_regs_t::clk_cn
__IO uint16_t clk_cn
Definition: sdhc_regs.h:102
mxc_sdhc_regs_t::preset_4
__I uint16_t preset_4
Definition: sdhc_regs.h:127
mxc_sdhc_regs_t::host_cn_ver
__IO uint16_t host_cn_ver
Definition: sdhc_regs.h:135
mxc_sdhc_regs_t::er_int_en
__IO uint16_t er_int_en
Definition: sdhc_regs.h:108
mxc_sdhc_regs_t::sdma
__IO uint32_t sdma
Definition: sdhc_regs.h:89
mxc_sdhc_regs_t::adma_er
__IO uint8_t adma_er
Definition: sdhc_regs.h:119
mxc_sdhc_regs_t::host_cn_1
__IO uint8_t host_cn_1
Definition: sdhc_regs.h:98
mxc_sdhc_regs_t::er_int_signal
__IO uint16_t er_int_signal
Definition: sdhc_regs.h:110
mxc_sdhc_regs_t::int_en
__IO uint16_t int_en
Definition: sdhc_regs.h:107
mxc_sdhc_regs_t::arg_1
__IO uint32_t arg_1
Definition: sdhc_regs.h:92
mxc_sdhc_regs_t::int_signal
__IO uint16_t int_signal
Definition: sdhc_regs.h:109
mxc_sdhc_regs_t::preset_1
__I uint16_t preset_1
Definition: sdhc_regs.h:124
mxc_sdhc_regs_t
Definition: sdhc_regs.h:88
mxc_sdhc_regs_t::force_event_int_stat
__IO uint16_t force_event_int_stat
Definition: sdhc_regs.h:118
mxc_sdhc_regs_t::slot_int
__I uint16_t slot_int
Definition: sdhc_regs.h:134
mxc_sdhc_regs_t::preset_5
__I uint16_t preset_5
Definition: sdhc_regs.h:128
mxc_sdhc_regs_t::preset_0
__I uint16_t preset_0
Definition: sdhc_regs.h:123
mxc_sdhc_regs_t::shared_bus
__IO uint32_t shared_bus
Definition: sdhc_regs.h:132
mxc_sdhc_regs_t::int_stat
__IO uint16_t int_stat
Definition: sdhc_regs.h:105
mxc_sdhc_regs_t::pwr
__IO uint8_t pwr
Definition: sdhc_regs.h:99
mxc_sdhc_regs_t::preset_7
__I uint16_t preset_7
Definition: sdhc_regs.h:130
mxc_sdhc_regs_t::preset_2
__I uint16_t preset_2
Definition: sdhc_regs.h:125
mxc_sdhc_regs_t::cmd
__IO uint16_t cmd
Definition: sdhc_regs.h:94
mxc_sdhc_regs_t::preset_3
__I uint16_t preset_3
Definition: sdhc_regs.h:126
mxc_sdhc_regs_t::adma_addr_1
__IO uint32_t adma_addr_1
Definition: sdhc_regs.h:122
mxc_sdhc_regs_t::blk_cnt
__IO uint16_t blk_cnt
Definition: sdhc_regs.h:91
mxc_sdhc_regs_t::blk_gap
__IO uint8_t blk_gap
Definition: sdhc_regs.h:100
mxc_sdhc_regs_t::blk_size
__IO uint16_t blk_size
Definition: sdhc_regs.h:90
mxc_sdhc_regs_t::cfg_0
__I uint32_t cfg_0
Definition: sdhc_regs.h:113