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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Interrupt Enable Register.
#define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) |
INT_EN_BREAK Mask
#define MXC_F_UART_INT_EN_BREAK_END ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_END_POS)) |
INT_EN_BREAK_END Mask
#define MXC_F_UART_INT_EN_BREAK_END_POS 9 |
INT_EN_BREAK_END Position
#define MXC_F_UART_INT_EN_BREAK_POS 7 |
INT_EN_BREAK Position
#define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) |
INT_EN_CTS Mask
#define MXC_F_UART_INT_EN_CTS_POS 2 |
INT_EN_CTS Position
#define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) |
INT_EN_RX_FIFO_LVL Mask
#define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 |
INT_EN_RX_FIFO_LVL Position
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) |
INT_EN_RX_FRAME_ERROR Mask
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 |
INT_EN_RX_FRAME_ERROR Position
#define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) |
INT_EN_RX_OVERRUN Mask
#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 |
INT_EN_RX_OVERRUN Position
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) |
INT_EN_RX_PARITY_ERROR Mask
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 |
INT_EN_RX_PARITY_ERROR Position
#define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) |
INT_EN_RX_TO Mask
#define MXC_F_UART_INT_EN_RX_TO_POS 8 |
INT_EN_RX_TO Position
#define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) |
INT_EN_TX_FIFO_AE Mask
#define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 |
INT_EN_TX_FIFO_AE Position
#define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) |
INT_EN_TX_FIFO_LVL Mask
#define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 |
INT_EN_TX_FIFO_LVL Position