 |
MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
|
45 #include "mxc_device.h"
146 } mxc_sys_periph_clock_t;
155 } mxc_sys_system_clock_t;
157 #define MXC_SYS_SCACHE_CLK 1 // Enable SCACHE CLK
158 #define MXC_SYS_CTB_CLK 1 // Enable CTB CLK
167 int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock);
173 void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock);
179 void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock);
185 void MXC_SYS_RTCClockEnable (
void);
191 int MXC_SYS_RTCClockDisable();
198 int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock);
205 int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
213 int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock);
220 int MXC_SYS_Clock_Timeout (uint32_t ready);
226 void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
232 uint8_t MXC_SYS_GetRev (
void);
240 int MXC_SYS_GetUSN (uint8_t* serialNumber,
int len);
#define MXC_F_GCR_RST0_SOFT_RST_POS
Definition: gcr_regs.h:275
#define MXC_F_GCR_RST0_TIMER4_POS
Definition: gcr_regs.h:230
#define MXC_F_GCR_RST0_UART2_POS
Definition: gcr_regs.h:272
#define MXC_F_GCR_PCLK_DIS1_SMPHR_POS
Definition: gcr_regs.h:742
#define MXC_F_GCR_RST0_I2C0_POS
Definition: gcr_regs.h:248
#define MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS
Definition: gcr_regs.h:748
#define MXC_F_GCR_RST1_OWIRE_POS
Definition: gcr_regs.h:677
#define MXC_F_GCR_RST1_BTLE_POS
Definition: gcr_regs.h:695
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K
Definition: gcr_regs.h:323
#define MXC_F_GCR_RST0_TIMER3_POS
Definition: gcr_regs.h:227
#define MXC_F_GCR_RST0_SYS_RST_POS
Definition: gcr_regs.h:281
#define MXC_F_GCR_RST0_PERIPH_RST_POS
Definition: gcr_regs.h:278
#define MXC_F_GCR_RST1_XSPIM_POS
Definition: gcr_regs.h:671
#define MXC_F_GCR_PCLK_DIS1_HTMR0_POS
Definition: gcr_regs.h:769
#define MXC_F_GCR_RST1_XIPR_POS
Definition: gcr_regs.h:686
#define MXC_F_GCR_RST0_GPIO0_POS
Definition: gcr_regs.h:212
#define MXC_F_GCR_RST0_TIMER5_POS
Definition: gcr_regs.h:233
#define MXC_F_GCR_PCLK_DIS1_WDT2_POS
Definition: gcr_regs.h:781
#define MXC_F_GCR_RST0_UART1_POS
Definition: gcr_regs.h:239
#define MXC_F_GCR_RST0_RTC_POS
Definition: gcr_regs.h:251
#define MXC_F_GCR_PCLK_DIS1_SDHC_POS
Definition: gcr_regs.h:745
#define MXC_F_GCR_PCLK_DIS0_CRYPTO_POS
Definition: gcr_regs.h:495
#define MXC_F_GCR_RST0_SPI2_POS
Definition: gcr_regs.h:245
#define MXC_F_GCR_RST0_DMA0_POS
Definition: gcr_regs.h:206
#define MXC_F_GCR_RST0_ADC_POS
Definition: gcr_regs.h:266
#define MXC_F_GCR_PCLK_DIS0_I2C0_POS
Definition: gcr_regs.h:492
#define MXC_F_GCR_RST1_I2C2_POS
Definition: gcr_regs.h:701
#define MXC_F_GCR_RST0_DMA1_POS
Definition: gcr_regs.h:269
#define MXC_F_GCR_RST1_SPI3_POS
Definition: gcr_regs.h:683
#define MXC_F_GCR_PCLK_DIS1_SPI3_POS
Definition: gcr_regs.h:754
#define MXC_F_GCR_PCLK_DIS1_CPU1_POS
Definition: gcr_regs.h:784
#define MXC_F_GCR_PCLK_DIS1_I2C2_POS
Definition: gcr_regs.h:766
#define MXC_F_GCR_RST1_SIMO_POS
Definition: gcr_regs.h:716
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8
Definition: gcr_regs.h:317
#define MXC_F_GCR_PCLK_DIS0_ADC_POS
Definition: gcr_regs.h:516
#define MXC_F_GCR_RST0_CRYPTO_POS
Definition: gcr_regs.h:254
#define MXC_F_GCR_PCLK_DIS0_USB_POS
Definition: gcr_regs.h:474
#define MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS
Definition: gcr_regs.h:757
#define MXC_F_GCR_RST1_SPIXIP_POS
Definition: gcr_regs.h:668
#define MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS
Definition: gcr_regs.h:528
#define MXC_F_GCR_RST1_SDHC_POS
Definition: gcr_regs.h:674
#define MXC_F_GCR_RST1_DVS_POS
Definition: gcr_regs.h:713
#define MXC_F_GCR_RST0_TRNG_POS
Definition: gcr_regs.h:263
#define MXC_F_GCR_RST0_TIMER1_POS
Definition: gcr_regs.h:221
#define MXC_F_GCR_PCLK_DIS0_PTD_POS
Definition: gcr_regs.h:522
#define MXC_F_GCR_PCLK_DIS1_WDT1_POS
Definition: gcr_regs.h:778
#define MXC_F_GCR_PCLK_DIS1_SCACHE_POS
Definition: gcr_regs.h:736
#define MXC_F_GCR_RST0_SPI1_POS
Definition: gcr_regs.h:242
#define MXC_F_GCR_PCLK_DIS0_UART0_POS
Definition: gcr_regs.h:486
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8
Definition: gcr_regs.h:321
#define MXC_F_GCR_RST1_HTMR1_POS
Definition: gcr_regs.h:710
#define MXC_F_GCR_PCLK_DIS1_OW_POS
Definition: gcr_regs.h:751
#define MXC_F_GCR_PCLK_DIS0_I2C1_POS
Definition: gcr_regs.h:519
#define MXC_F_GCR_PCLK_DIS1_HTMR1_POS
Definition: gcr_regs.h:772
#define MXC_F_GCR_RST1_WDT2_POS
Definition: gcr_regs.h:692
#define MXC_F_GCR_PCLK_DIS0_GPIO1_POS
Definition: gcr_regs.h:471
#define MXC_F_GCR_PCLK_DIS0_DMA0_POS
Definition: gcr_regs.h:477
#define MXC_F_GCR_RST0_SMPHR_POS
Definition: gcr_regs.h:257
#define MXC_F_GCR_PCLK_DIS0_UART1_POS
Definition: gcr_regs.h:489
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96
Definition: gcr_regs.h:319
#define MXC_F_GCR_PCLK_DIS1_WDT0_POS
Definition: gcr_regs.h:775
#define MXC_F_GCR_RST1_PT_POS
Definition: gcr_regs.h:665
#define MXC_F_GCR_RST1_AUDIO_POS
Definition: gcr_regs.h:698
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M
Definition: gcr_regs.h:315
#define MXC_F_GCR_RST1_WDT1_POS
Definition: gcr_regs.h:680
#define MXC_F_GCR_PCLK_DIS0_TIMER0_POS
Definition: gcr_regs.h:498
#define MXC_F_GCR_RST1_RPU_POS
Definition: gcr_regs.h:704
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC
Definition: gcr_regs.h:313
#define MXC_F_GCR_PCLK_DIS1_BTLE_POS
Definition: gcr_regs.h:727
#define MXC_F_GCR_PCLK_DIS0_TIMER4_POS
Definition: gcr_regs.h:510
#define MXC_F_GCR_PCLK_DIS1_TRNG_POS
Definition: gcr_regs.h:733
#define MXC_F_GCR_PCLK_DIS1_UART2_POS
Definition: gcr_regs.h:730
#define MXC_F_GCR_RST0_USB_POS
Definition: gcr_regs.h:260
#define MXC_F_GCR_PCLK_DIS0_TIMER5_POS
Definition: gcr_regs.h:513
#define MXC_F_GCR_RST1_HTMR0_POS
Definition: gcr_regs.h:707
#define MXC_F_GCR_PCLK_DIS1_AUDIO_POS
Definition: gcr_regs.h:763
#define MXC_F_GCR_RST0_GPIO1_POS
Definition: gcr_regs.h:215
#define MXC_F_GCR_PCLK_DIS1_DMA1_POS
Definition: gcr_regs.h:760
#define MXC_F_GCR_PCLK_DIS0_SPI1_POS
Definition: gcr_regs.h:483
#define MXC_F_GCR_RST0_TIMER2_POS
Definition: gcr_regs.h:224
#define MXC_F_GCR_RST1_I2C1_POS
Definition: gcr_regs.h:662
#define MXC_F_GCR_PCLK_DIS0_GPIO0_POS
Definition: gcr_regs.h:468
#define MXC_F_GCR_PCLK_DIS0_SPI0_POS
Definition: gcr_regs.h:480
#define MXC_F_GCR_RST0_TIMER0_POS
Definition: gcr_regs.h:218
#define MXC_F_GCR_PCLK_DIS0_TIMER2_POS
Definition: gcr_regs.h:504
#define MXC_F_GCR_PCLK_DIS0_TIMER1_POS
Definition: gcr_regs.h:501
#define MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS
Definition: gcr_regs.h:525
#define MXC_F_GCR_PCLK_DIS1_SDMA_POS
Definition: gcr_regs.h:739
#define MXC_F_GCR_RST0_UART0_POS
Definition: gcr_regs.h:236
#define MXC_F_GCR_PCLK_DIS0_TIMER3_POS
Definition: gcr_regs.h:507
#define MXC_F_GCR_RST1_SEMA_POS
Definition: gcr_regs.h:689
#define MXC_F_GCR_RST0_WDT0_POS
Definition: gcr_regs.h:209