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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Peripheral Clock Disable.
#define MXC_F_GCR_PCLK_DIS1_AUDIO ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_AUDIO_POS)) |
PCLK_DIS1_AUDIO Mask
#define MXC_F_GCR_PCLK_DIS1_AUDIO_POS 23 |
PCLK_DIS1_AUDIO Position
#define MXC_F_GCR_PCLK_DIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_BTLE_POS)) |
PCLK_DIS1_BTLE Mask
#define MXC_F_GCR_PCLK_DIS1_BTLE_POS 0 |
PCLK_DIS1_BTLE Position
#define MXC_F_GCR_PCLK_DIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_CPU1_POS)) |
PCLK_DIS1_CPU1 Mask
#define MXC_F_GCR_PCLK_DIS1_CPU1_POS 31 |
PCLK_DIS1_CPU1 Position
#define MXC_F_GCR_PCLK_DIS1_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_DMA1_POS)) |
PCLK_DIS1_DMA1 Mask
#define MXC_F_GCR_PCLK_DIS1_DMA1_POS 21 |
PCLK_DIS1_DMA1 Position
#define MXC_F_GCR_PCLK_DIS1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_HTMR0_POS)) |
PCLK_DIS1_HTMR0 Mask
#define MXC_F_GCR_PCLK_DIS1_HTMR0_POS 25 |
PCLK_DIS1_HTMR0 Position
#define MXC_F_GCR_PCLK_DIS1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_HTMR1_POS)) |
PCLK_DIS1_HTMR1 Mask
#define MXC_F_GCR_PCLK_DIS1_HTMR1_POS 26 |
PCLK_DIS1_HTMR1 Position
#define MXC_F_GCR_PCLK_DIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_I2C2_POS)) |
PCLK_DIS1_I2C2 Mask
#define MXC_F_GCR_PCLK_DIS1_I2C2_POS 24 |
PCLK_DIS1_I2C2 Position
#define MXC_F_GCR_PCLK_DIS1_ICACHEXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS)) |
PCLK_DIS1_ICACHEXIP Mask
#define MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS 12 |
PCLK_DIS1_ICACHEXIP Position
#define MXC_F_GCR_PCLK_DIS1_OW ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_OW_POS)) |
PCLK_DIS1_OW Mask
#define MXC_F_GCR_PCLK_DIS1_OW_POS 13 |
PCLK_DIS1_OW Position
#define MXC_F_GCR_PCLK_DIS1_SCACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SCACHE_POS)) |
PCLK_DIS1_SCACHE Mask
#define MXC_F_GCR_PCLK_DIS1_SCACHE_POS 7 |
PCLK_DIS1_SCACHE Position
#define MXC_F_GCR_PCLK_DIS1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDHC_POS)) |
PCLK_DIS1_SDHC Mask
#define MXC_F_GCR_PCLK_DIS1_SDHC_POS 10 |
PCLK_DIS1_SDHC Position
#define MXC_F_GCR_PCLK_DIS1_SDMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDMA_POS)) |
PCLK_DIS1_SDMA Mask
#define MXC_F_GCR_PCLK_DIS1_SDMA_POS 8 |
PCLK_DIS1_SDMA Position
#define MXC_F_GCR_PCLK_DIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SMPHR_POS)) |
PCLK_DIS1_SMPHR Mask
#define MXC_F_GCR_PCLK_DIS1_SMPHR_POS 9 |
PCLK_DIS1_SMPHR Position
#define MXC_F_GCR_PCLK_DIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPI3_POS)) |
PCLK_DIS1_SPI3 Mask
#define MXC_F_GCR_PCLK_DIS1_SPI3_POS 14 |
PCLK_DIS1_SPI3 Position
#define MXC_F_GCR_PCLK_DIS1_SPIXIPR ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS)) |
PCLK_DIS1_SPIXIPR Mask
#define MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS 20 |
PCLK_DIS1_SPIXIPR Position
#define MXC_F_GCR_PCLK_DIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_TRNG_POS)) |
PCLK_DIS1_TRNG Mask
#define MXC_F_GCR_PCLK_DIS1_TRNG_POS 2 |
PCLK_DIS1_TRNG Position
#define MXC_F_GCR_PCLK_DIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_UART2_POS)) |
PCLK_DIS1_UART2 Mask
#define MXC_F_GCR_PCLK_DIS1_UART2_POS 1 |
PCLK_DIS1_UART2 Position
#define MXC_F_GCR_PCLK_DIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_WDT0_POS)) |
PCLK_DIS1_WDT0 Mask
#define MXC_F_GCR_PCLK_DIS1_WDT0_POS 27 |
PCLK_DIS1_WDT0 Position
#define MXC_F_GCR_PCLK_DIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_WDT1_POS)) |
PCLK_DIS1_WDT1 Mask
#define MXC_F_GCR_PCLK_DIS1_WDT1_POS 28 |
PCLK_DIS1_WDT1 Position
#define MXC_F_GCR_PCLK_DIS1_WDT2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_WDT2_POS)) |
PCLK_DIS1_WDT2 Mask
#define MXC_F_GCR_PCLK_DIS1_WDT2_POS 29 |
PCLK_DIS1_WDT2 Position