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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Instruction Cache XIP Protection Register.
#define MXC_F_RPU_SFCC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_CRYPTOACN_POS)) |
SFCC_CRYPTOACN Mask
#define MXC_F_RPU_SFCC_CRYPTOACN_POS 7 |
SFCC_CRYPTOACN Position
#define MXC_F_RPU_SFCC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_DMA0ACN_POS)) |
SFCC_DMA0ACN Mask
#define MXC_F_RPU_SFCC_DMA0ACN_POS 0 |
SFCC_DMA0ACN Position
#define MXC_F_RPU_SFCC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_DMA1ACN_POS)) |
SFCC_DMA1ACN Mask
#define MXC_F_RPU_SFCC_DMA1ACN_POS 1 |
SFCC_DMA1ACN Position
#define MXC_F_RPU_SFCC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDIOACN_POS)) |
SFCC_SDIOACN Mask
#define MXC_F_RPU_SFCC_SDIOACN_POS 8 |
SFCC_SDIOACN Position
#define MXC_F_RPU_SFCC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDMADACN_POS)) |
SFCC_SDMADACN Mask
#define MXC_F_RPU_SFCC_SDMADACN_POS 5 |
SFCC_SDMADACN Position
#define MXC_F_RPU_SFCC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDMAIACN_POS)) |
SFCC_SDMAIACN Mask
#define MXC_F_RPU_SFCC_SDMAIACN_POS 6 |
SFCC_SDMAIACN Position
#define MXC_F_RPU_SFCC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SYS0ACN_POS)) |
SFCC_SYS0ACN Mask
#define MXC_F_RPU_SFCC_SYS0ACN_POS 3 |
SFCC_SYS0ACN Position
#define MXC_F_RPU_SFCC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SYS1ACN_POS)) |
SFCC_SYS1ACN Mask
#define MXC_F_RPU_SFCC_SYS1ACN_POS 4 |
SFCC_SYS1ACN Position
#define MXC_F_RPU_SFCC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_USBACN_POS)) |
SFCC_USBACN Mask
#define MXC_F_RPU_SFCC_USBACN_POS 2 |
SFCC_USBACN Position