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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Clock Control.
#define MXC_F_GCR_CLK_CTRL_CCD ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CCD_POS)) |
CLK_CTRL_CCD Mask
#define MXC_F_GCR_CLK_CTRL_CCD_POS 15 |
CLK_CTRL_CCD Position
#define MXC_F_GCR_CLK_CTRL_HIRC60M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC60M_EN_POS)) |
CLK_CTRL_HIRC60M_EN Mask
#define MXC_F_GCR_CLK_CTRL_HIRC60M_EN_POS 18 |
CLK_CTRL_HIRC60M_EN Position
#define MXC_F_GCR_CLK_CTRL_HIRC60M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC60M_RDY_POS)) |
CLK_CTRL_HIRC60M_RDY Mask
#define MXC_F_GCR_CLK_CTRL_HIRC60M_RDY_POS 26 |
CLK_CTRL_HIRC60M_RDY Position
#define MXC_F_GCR_CLK_CTRL_HIRC8M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8M_EN_POS)) |
CLK_CTRL_HIRC8M_EN Mask
#define MXC_F_GCR_CLK_CTRL_HIRC8M_EN_POS 20 |
CLK_CTRL_HIRC8M_EN Position
#define MXC_F_GCR_CLK_CTRL_HIRC8M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8M_RDY_POS)) |
CLK_CTRL_HIRC8M_RDY Mask
#define MXC_F_GCR_CLK_CTRL_HIRC8M_RDY_POS 28 |
CLK_CTRL_HIRC8M_RDY Position
#define MXC_F_GCR_CLK_CTRL_HIRC8M_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8M_VS_POS)) |
CLK_CTRL_HIRC8M_VS Mask
#define MXC_F_GCR_CLK_CTRL_HIRC8M_VS_POS 21 |
CLK_CTRL_HIRC8M_VS Position
#define MXC_F_GCR_CLK_CTRL_HIRCMM_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRCMM_EN_POS)) |
CLK_CTRL_HIRCMM_EN Mask
#define MXC_F_GCR_CLK_CTRL_HIRCMM_EN_POS 19 |
CLK_CTRL_HIRCMM_EN Position
#define MXC_F_GCR_CLK_CTRL_HIRCMM_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRCMM_RDY_POS)) |
CLK_CTRL_HIRCMM_RDY Mask
#define MXC_F_GCR_CLK_CTRL_HIRCMM_RDY_POS 27 |
CLK_CTRL_HIRCMM_RDY Position
#define MXC_F_GCR_CLK_CTRL_LIRC6K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC6K_RDY_POS)) |
CLK_CTRL_LIRC6K_RDY Mask
#define MXC_F_GCR_CLK_CTRL_LIRC6K_RDY_POS 30 |
CLK_CTRL_LIRC6K_RDY Position
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) |
CLK_CTRL_LIRC8K_RDY Mask
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29 |
CLK_CTRL_LIRC8K_RDY Position
#define MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)) |
CLK_CTRL_SYSCLK_PRESCALE Mask
#define MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS 6 |
CLK_CTRL_SYSCLK_PRESCALE Position
#define MXC_F_GCR_CLK_CTRL_SYSOSC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS)) |
CLK_CTRL_SYSOSC_RDY Mask
#define MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS 13 |
CLK_CTRL_SYSOSC_RDY Position
#define MXC_F_GCR_CLK_CTRL_SYSOSC_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)) |
CLK_CTRL_SYSOSC_SEL Mask
#define MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS 9 |
CLK_CTRL_SYSOSC_SEL Position
#define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) |
CLK_CTRL_X32K_EN Mask
#define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 |
CLK_CTRL_X32K_EN Position
#define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) |
CLK_CTRL_X32K_RDY Mask
#define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 |
CLK_CTRL_X32K_RDY Position
#define MXC_F_GCR_CLK_CTRL_X32M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32M_EN_POS)) |
CLK_CTRL_X32M_EN Mask
#define MXC_F_GCR_CLK_CTRL_X32M_EN_POS 16 |
CLK_CTRL_X32M_EN Position
#define MXC_F_GCR_CLK_CTRL_X32M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32M_RDY_POS)) |
CLK_CTRL_X32M_RDY Mask
#define MXC_F_GCR_CLK_CTRL_X32M_RDY_POS 24 |
CLK_CTRL_X32M_RDY Position
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV1 Setting
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV128 Setting
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV16 Setting
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV2 Setting
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV32 Setting
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV4 Setting
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV64 Setting
#define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
CLK_CTRL_SYSCLK_PRESCALE_DIV8 Setting
#define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
CLK_CTRL_SYSOSC_SEL_HIRC Setting
#define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
CLK_CTRL_SYSOSC_SEL_HIRC8 Setting
#define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
CLK_CTRL_SYSOSC_SEL_HIRC96 Setting
#define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
CLK_CTRL_SYSOSC_SEL_LIRC8 Setting
#define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
CLK_CTRL_SYSOSC_SEL_XTAL32K Setting
#define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
CLK_CTRL_SYSOSC_SEL_XTAL32M Setting
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 ((uint32_t)0x0UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV1 Value
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 ((uint32_t)0x7UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV128 Value
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 ((uint32_t)0x4UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV16 Value
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 ((uint32_t)0x1UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV2 Value
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 ((uint32_t)0x5UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV32 Value
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 ((uint32_t)0x2UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV4 Value
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 ((uint32_t)0x6UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV64 Value
#define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 ((uint32_t)0x3UL) |
CLK_CTRL_SYSCLK_PRESCALE_DIV8 Value
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC ((uint32_t)0x0UL) |
CLK_CTRL_SYSOSC_SEL_HIRC Value
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 ((uint32_t)0x5UL) |
CLK_CTRL_SYSOSC_SEL_HIRC8 Value
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 ((uint32_t)0x4UL) |
CLK_CTRL_SYSOSC_SEL_HIRC96 Value
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8 ((uint32_t)0x3UL) |
CLK_CTRL_SYSOSC_SEL_LIRC8 Value
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K ((uint32_t)0x6UL) |
CLK_CTRL_SYSOSC_SEL_XTAL32K Value
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M ((uint32_t)0x2UL) |
CLK_CTRL_SYSOSC_SEL_XTAL32M Value