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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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50 #if defined (__ICCARM__)
51 #pragma system_include
54 #if defined (__CC_ARM)
65 #define __I volatile const
71 #define __R volatile const
93 __R uint32_t rsv_0x10_0x2f[8];
97 __R uint32_t rsv_0x3c;
101 __R uint32_t rsv_0x4c_0x53[2];
103 __R uint32_t rsv_0x58_0x5f[2];
108 __R uint32_t rsv_0x70_0x7f[4];
110 __R uint32_t rsv_0x84_0x8f[3];
112 __R uint32_t rsv_0x94_0xff[27];
114 __R uint32_t rsv_0x104_0x10f[3];
116 __R uint32_t rsv_0x114_0x11f[3];
118 __R uint32_t rsv_0x124_0x12f[3];
120 __R uint32_t rsv_0x134_0x13f[3];
122 __R uint32_t rsv_0x144_0x14f[3];
124 __R uint32_t rsv_0x154_0x1af[23];
126 __R uint32_t rsv_0x1b4_0x1bf[3];
128 __R uint32_t rsv_0x1c4_0x1cf[3];
130 __R uint32_t rsv_0x1d4_0x1df[3];
132 __R uint32_t rsv_0x1e4_0x1ef[3];
134 __R uint32_t rsv_0x1f4_0x25f[27];
136 __R uint32_t rsv_0x264_0x26f[3];
138 __R uint32_t rsv_0x274_0x27f[3];
140 __R uint32_t rsv_0x284_0x28f[3];
143 __R uint32_t rsv_0x298_0x29f[2];
146 __R uint32_t rsv_0x2a8_0x2ef[18];
148 __R uint32_t rsv_0x2f4_0x32f[15];
150 __R uint32_t rsv_0x334_0x33f[3];
152 __R uint32_t rsv_0x344_0x34f[3];
154 __R uint32_t rsv_0x354_0x35f[3];
156 __R uint32_t rsv_0x364_0x36f[3];
158 __R uint32_t rsv_0x374_0x39f[11];
160 __R uint32_t rsv_0x3a4_0x3bf[7];
162 __R uint32_t rsv_0x3c4_0x3cf[3];
164 __R uint32_t rsv_0x3d4_0x3df[3];
166 __R uint32_t rsv_0x3e4_0x41f[15];
168 __R uint32_t rsv_0x424_0x42f[3];
170 __R uint32_t rsv_0x434_0x43f[3];
172 __R uint32_t rsv_0x444_0x45f[7];
174 __R uint32_t rsv_0x464_0x47f[7];
176 __R uint32_t rsv_0x484_0x4bf[15];
178 __R uint32_t rsv_0x4c4_0x4cf[3];
180 __R uint32_t rsv_0x4d4_0x4ff[11];
182 __R uint32_t rsv_0x504_0xb0f[387];
184 __R uint32_t rsv_0xb14_0xb5f[19];
186 __R uint32_t rsv_0xb64_0xbbf[23];
188 __R uint32_t rsv_0xbc4_0xbdf[7];
190 __R uint32_t rsv_0xbe4_0xeff[199];
192 __R uint32_t rsv_0xf04_0xf0f[3];
194 __R uint32_t rsv_0xf14_0xf1f[3];
196 __R uint32_t rsv_0xf24_0xf2f[3];
198 __R uint32_t rsv_0xf34_0xf3f[3];
200 __R uint32_t rsv_0xf44_0xf4f[3];
202 __R uint32_t rsv_0xf54_0xf5f[3];
213 #define MXC_R_RPU_GCR ((uint32_t)0x00000000UL)
214 #define MXC_R_RPU_SIR ((uint32_t)0x00000004UL)
215 #define MXC_R_RPU_FCR ((uint32_t)0x00000008UL)
216 #define MXC_R_RPU_CRYPTO ((uint32_t)0x0000000CUL)
217 #define MXC_R_RPU_WDT0 ((uint32_t)0x00000030UL)
218 #define MXC_R_RPU_WDT1 ((uint32_t)0x00000034UL)
219 #define MXC_R_RPU_WDT2 ((uint32_t)0x00000038UL)
220 #define MXC_R_RPU_SMON ((uint32_t)0x00000040UL)
221 #define MXC_R_RPU_SIMO ((uint32_t)0x00000044UL)
222 #define MXC_R_RPU_DVS ((uint32_t)0x00000048UL)
223 #define MXC_R_RPU_BBSIR ((uint32_t)0x00000054UL)
224 #define MXC_R_RPU_RTC ((uint32_t)0x00000060UL)
225 #define MXC_R_RPU_WUT ((uint32_t)0x00000064UL)
226 #define MXC_R_RPU_PWRSEQ ((uint32_t)0x00000068UL)
227 #define MXC_R_RPU_MCR ((uint32_t)0x0000006CUL)
228 #define MXC_R_RPU_GPIO0 ((uint32_t)0x00000080UL)
229 #define MXC_R_RPU_GPIO1 ((uint32_t)0x00000090UL)
230 #define MXC_R_RPU_TMR0 ((uint32_t)0x00000100UL)
231 #define MXC_R_RPU_TMR1 ((uint32_t)0x00000110UL)
232 #define MXC_R_RPU_TMR2 ((uint32_t)0x00000120UL)
233 #define MXC_R_RPU_TMR3 ((uint32_t)0x00000130UL)
234 #define MXC_R_RPU_TMR4 ((uint32_t)0x00000140UL)
235 #define MXC_R_RPU_TMR5 ((uint32_t)0x00000150UL)
236 #define MXC_R_RPU_HTIMER0 ((uint32_t)0x000001B0UL)
237 #define MXC_R_RPU_HTIMER1 ((uint32_t)0x000001C0UL)
238 #define MXC_R_RPU_I2C0_BUS0 ((uint32_t)0x000001D0UL)
239 #define MXC_R_RPU_I2C1_BUS0 ((uint32_t)0x000001E0UL)
240 #define MXC_R_RPU_I2C2_BUS0 ((uint32_t)0x000001F0UL)
241 #define MXC_R_RPU_SPIXFM ((uint32_t)0x00000260UL)
242 #define MXC_R_RPU_SPIXFC ((uint32_t)0x00000270UL)
243 #define MXC_R_RPU_DMA0 ((uint32_t)0x00000280UL)
244 #define MXC_R_RPU_FLC0 ((uint32_t)0x00000290UL)
245 #define MXC_R_RPU_FLC1 ((uint32_t)0x00000294UL)
246 #define MXC_R_RPU_ICC0 ((uint32_t)0x000002A0UL)
247 #define MXC_R_RPU_ICC1 ((uint32_t)0x000002A4UL)
248 #define MXC_R_RPU_SFCC ((uint32_t)0x000002F0UL)
249 #define MXC_R_RPU_SRCC ((uint32_t)0x00000330UL)
250 #define MXC_R_RPU_ADC ((uint32_t)0x00000340UL)
251 #define MXC_R_RPU_DMA1 ((uint32_t)0x00000350UL)
252 #define MXC_R_RPU_SDMA ((uint32_t)0x00000360UL)
253 #define MXC_R_RPU_SDHCCTRL ((uint32_t)0x00000370UL)
254 #define MXC_R_RPU_SPIXR ((uint32_t)0x000003A0UL)
255 #define MXC_R_RPU_PTG_BUS0 ((uint32_t)0x000003C0UL)
256 #define MXC_R_RPU_OWM ((uint32_t)0x000003D0UL)
257 #define MXC_R_RPU_SEMA ((uint32_t)0x000003E0UL)
258 #define MXC_R_RPU_UART0 ((uint32_t)0x00000420UL)
259 #define MXC_R_RPU_UART1 ((uint32_t)0x00000430UL)
260 #define MXC_R_RPU_UART2 ((uint32_t)0x00000440UL)
261 #define MXC_R_RPU_SPI1 ((uint32_t)0x00000460UL)
262 #define MXC_R_RPU_SPI2 ((uint32_t)0x00000480UL)
263 #define MXC_R_RPU_AUDIO ((uint32_t)0x000004C0UL)
264 #define MXC_R_RPU_TRNG ((uint32_t)0x000004D0UL)
265 #define MXC_R_RPU_BTLE ((uint32_t)0x00000500UL)
266 #define MXC_R_RPU_USBHS ((uint32_t)0x00000B10UL)
267 #define MXC_R_RPU_SDIO ((uint32_t)0x00000B60UL)
268 #define MXC_R_RPU_SPIXM_FIFO ((uint32_t)0x00000BC0UL)
269 #define MXC_R_RPU_SPI0 ((uint32_t)0x00000BE0UL)
270 #define MXC_R_RPU_SYSRAM0 ((uint32_t)0x00000F00UL)
271 #define MXC_R_RPU_SYSRAM1 ((uint32_t)0x00000F10UL)
272 #define MXC_R_RPU_SYSRAM2 ((uint32_t)0x00000F20UL)
273 #define MXC_R_RPU_SYSRAM3 ((uint32_t)0x00000F30UL)
274 #define MXC_R_RPU_SYSRAM4 ((uint32_t)0x00000F40UL)
275 #define MXC_R_RPU_SYSRAM5 ((uint32_t)0x00000F50UL)
276 #define MXC_R_RPU_SYSRAM6 ((uint32_t)0x00000F60UL)
285 #define MXC_F_RPU_GCR_DMA0ACN_POS 0
286 #define MXC_F_RPU_GCR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_DMA0ACN_POS))
288 #define MXC_F_RPU_GCR_DMA1ACN_POS 1
289 #define MXC_F_RPU_GCR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_DMA1ACN_POS))
291 #define MXC_F_RPU_GCR_USBACN_POS 2
292 #define MXC_F_RPU_GCR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_USBACN_POS))
294 #define MXC_F_RPU_GCR_SYS0ACN_POS 3
295 #define MXC_F_RPU_GCR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_SYS0ACN_POS))
297 #define MXC_F_RPU_GCR_SYS1ACN_POS 4
298 #define MXC_F_RPU_GCR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_SYS1ACN_POS))
300 #define MXC_F_RPU_GCR_SDMADACN_POS 5
301 #define MXC_F_RPU_GCR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_SDMADACN_POS))
303 #define MXC_F_RPU_GCR_SDMAIACN_POS 6
304 #define MXC_F_RPU_GCR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_SDMAIACN_POS))
306 #define MXC_F_RPU_GCR_CRYPTOACN_POS 7
307 #define MXC_F_RPU_GCR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_CRYPTOACN_POS))
309 #define MXC_F_RPU_GCR_SDIOACN_POS 8
310 #define MXC_F_RPU_GCR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_GCR_SDIOACN_POS))
320 #define MXC_F_RPU_SIR_DMA0ACN_POS 0
321 #define MXC_F_RPU_SIR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_DMA0ACN_POS))
323 #define MXC_F_RPU_SIR_DMA1ACN_POS 1
324 #define MXC_F_RPU_SIR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_DMA1ACN_POS))
326 #define MXC_F_RPU_SIR_USBACN_POS 2
327 #define MXC_F_RPU_SIR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_USBACN_POS))
329 #define MXC_F_RPU_SIR_SYS0ACN_POS 3
330 #define MXC_F_RPU_SIR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_SYS0ACN_POS))
332 #define MXC_F_RPU_SIR_SYS1ACN_POS 4
333 #define MXC_F_RPU_SIR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_SYS1ACN_POS))
335 #define MXC_F_RPU_SIR_SDMADACN_POS 5
336 #define MXC_F_RPU_SIR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_SDMADACN_POS))
338 #define MXC_F_RPU_SIR_SDMAIACN_POS 6
339 #define MXC_F_RPU_SIR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_SDMAIACN_POS))
341 #define MXC_F_RPU_SIR_CRYPTOACN_POS 7
342 #define MXC_F_RPU_SIR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_CRYPTOACN_POS))
344 #define MXC_F_RPU_SIR_SDIOACN_POS 8
345 #define MXC_F_RPU_SIR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SIR_SDIOACN_POS))
355 #define MXC_F_RPU_FCR_DMA0ACN_POS 0
356 #define MXC_F_RPU_FCR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_DMA0ACN_POS))
358 #define MXC_F_RPU_FCR_DMA1ACN_POS 1
359 #define MXC_F_RPU_FCR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_DMA1ACN_POS))
361 #define MXC_F_RPU_FCR_USBACN_POS 2
362 #define MXC_F_RPU_FCR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_USBACN_POS))
364 #define MXC_F_RPU_FCR_SYS0ACN_POS 3
365 #define MXC_F_RPU_FCR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_SYS0ACN_POS))
367 #define MXC_F_RPU_FCR_SYS1ACN_POS 4
368 #define MXC_F_RPU_FCR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_SYS1ACN_POS))
370 #define MXC_F_RPU_FCR_SDMADACN_POS 5
371 #define MXC_F_RPU_FCR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_SDMADACN_POS))
373 #define MXC_F_RPU_FCR_SDMAIACN_POS 6
374 #define MXC_F_RPU_FCR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_SDMAIACN_POS))
376 #define MXC_F_RPU_FCR_CRYPTOACN_POS 7
377 #define MXC_F_RPU_FCR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_CRYPTOACN_POS))
379 #define MXC_F_RPU_FCR_SDIOACN_POS 8
380 #define MXC_F_RPU_FCR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_FCR_SDIOACN_POS))
390 #define MXC_F_RPU_CRYPTO_DMA0ACN_POS 0
391 #define MXC_F_RPU_CRYPTO_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_DMA0ACN_POS))
393 #define MXC_F_RPU_CRYPTO_DMA1ACN_POS 1
394 #define MXC_F_RPU_CRYPTO_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_DMA1ACN_POS))
396 #define MXC_F_RPU_CRYPTO_USBACN_POS 2
397 #define MXC_F_RPU_CRYPTO_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_USBACN_POS))
399 #define MXC_F_RPU_CRYPTO_SYS0ACN_POS 3
400 #define MXC_F_RPU_CRYPTO_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_SYS0ACN_POS))
402 #define MXC_F_RPU_CRYPTO_SYS1ACN_POS 4
403 #define MXC_F_RPU_CRYPTO_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_SYS1ACN_POS))
405 #define MXC_F_RPU_CRYPTO_SDMADACN_POS 5
406 #define MXC_F_RPU_CRYPTO_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_SDMADACN_POS))
408 #define MXC_F_RPU_CRYPTO_SDMAIACN_POS 6
409 #define MXC_F_RPU_CRYPTO_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_SDMAIACN_POS))
411 #define MXC_F_RPU_CRYPTO_CRYPTOACN_POS 7
412 #define MXC_F_RPU_CRYPTO_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_CRYPTOACN_POS))
414 #define MXC_F_RPU_CRYPTO_SDIOACN_POS 8
415 #define MXC_F_RPU_CRYPTO_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_CRYPTO_SDIOACN_POS))
425 #define MXC_F_RPU_WDT0_DMA0ACN_POS 0
426 #define MXC_F_RPU_WDT0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_DMA0ACN_POS))
428 #define MXC_F_RPU_WDT0_DMA1ACN_POS 1
429 #define MXC_F_RPU_WDT0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_DMA1ACN_POS))
431 #define MXC_F_RPU_WDT0_USBACN_POS 2
432 #define MXC_F_RPU_WDT0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_USBACN_POS))
434 #define MXC_F_RPU_WDT0_SYS0ACN_POS 3
435 #define MXC_F_RPU_WDT0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_SYS0ACN_POS))
437 #define MXC_F_RPU_WDT0_SYS1ACN_POS 4
438 #define MXC_F_RPU_WDT0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_SYS1ACN_POS))
440 #define MXC_F_RPU_WDT0_SDMADACN_POS 5
441 #define MXC_F_RPU_WDT0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_SDMADACN_POS))
443 #define MXC_F_RPU_WDT0_SDMAIACN_POS 6
444 #define MXC_F_RPU_WDT0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_SDMAIACN_POS))
446 #define MXC_F_RPU_WDT0_CRYPTOACN_POS 7
447 #define MXC_F_RPU_WDT0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_CRYPTOACN_POS))
449 #define MXC_F_RPU_WDT0_SDIOACN_POS 8
450 #define MXC_F_RPU_WDT0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT0_SDIOACN_POS))
460 #define MXC_F_RPU_WDT1_DMA0ACN_POS 0
461 #define MXC_F_RPU_WDT1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_DMA0ACN_POS))
463 #define MXC_F_RPU_WDT1_DMA1ACN_POS 1
464 #define MXC_F_RPU_WDT1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_DMA1ACN_POS))
466 #define MXC_F_RPU_WDT1_USBACN_POS 2
467 #define MXC_F_RPU_WDT1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_USBACN_POS))
469 #define MXC_F_RPU_WDT1_SYS0ACN_POS 3
470 #define MXC_F_RPU_WDT1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_SYS0ACN_POS))
472 #define MXC_F_RPU_WDT1_SYS1ACN_POS 4
473 #define MXC_F_RPU_WDT1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_SYS1ACN_POS))
475 #define MXC_F_RPU_WDT1_SDMADACN_POS 5
476 #define MXC_F_RPU_WDT1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_SDMADACN_POS))
478 #define MXC_F_RPU_WDT1_SDMAIACN_POS 6
479 #define MXC_F_RPU_WDT1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_SDMAIACN_POS))
481 #define MXC_F_RPU_WDT1_CRYPTOACN_POS 7
482 #define MXC_F_RPU_WDT1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_CRYPTOACN_POS))
484 #define MXC_F_RPU_WDT1_SDIOACN_POS 8
485 #define MXC_F_RPU_WDT1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT1_SDIOACN_POS))
495 #define MXC_F_RPU_WDT2_DMA0ACN_POS 0
496 #define MXC_F_RPU_WDT2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_DMA0ACN_POS))
498 #define MXC_F_RPU_WDT2_DMA1ACN_POS 1
499 #define MXC_F_RPU_WDT2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_DMA1ACN_POS))
501 #define MXC_F_RPU_WDT2_USBACN_POS 2
502 #define MXC_F_RPU_WDT2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_USBACN_POS))
504 #define MXC_F_RPU_WDT2_SYS0ACN_POS 3
505 #define MXC_F_RPU_WDT2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_SYS0ACN_POS))
507 #define MXC_F_RPU_WDT2_SYS1ACN_POS 4
508 #define MXC_F_RPU_WDT2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_SYS1ACN_POS))
510 #define MXC_F_RPU_WDT2_SDMADACN_POS 5
511 #define MXC_F_RPU_WDT2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_SDMADACN_POS))
513 #define MXC_F_RPU_WDT2_SDMAIACN_POS 6
514 #define MXC_F_RPU_WDT2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_SDMAIACN_POS))
516 #define MXC_F_RPU_WDT2_CRYPTOACN_POS 7
517 #define MXC_F_RPU_WDT2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_CRYPTOACN_POS))
519 #define MXC_F_RPU_WDT2_SDIOACN_POS 8
520 #define MXC_F_RPU_WDT2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_WDT2_SDIOACN_POS))
530 #define MXC_F_RPU_SMON_DMA0ACN_POS 0
531 #define MXC_F_RPU_SMON_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_DMA0ACN_POS))
533 #define MXC_F_RPU_SMON_DMA1ACN_POS 1
534 #define MXC_F_RPU_SMON_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_DMA1ACN_POS))
536 #define MXC_F_RPU_SMON_USBACN_POS 2
537 #define MXC_F_RPU_SMON_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_USBACN_POS))
539 #define MXC_F_RPU_SMON_SYS0ACN_POS 3
540 #define MXC_F_RPU_SMON_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_SYS0ACN_POS))
542 #define MXC_F_RPU_SMON_SYS1ACN_POS 4
543 #define MXC_F_RPU_SMON_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_SYS1ACN_POS))
545 #define MXC_F_RPU_SMON_SDMADACN_POS 5
546 #define MXC_F_RPU_SMON_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_SDMADACN_POS))
548 #define MXC_F_RPU_SMON_SDMAIACN_POS 6
549 #define MXC_F_RPU_SMON_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_SDMAIACN_POS))
551 #define MXC_F_RPU_SMON_CRYPTOACN_POS 7
552 #define MXC_F_RPU_SMON_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_CRYPTOACN_POS))
554 #define MXC_F_RPU_SMON_SDIOACN_POS 8
555 #define MXC_F_RPU_SMON_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SMON_SDIOACN_POS))
565 #define MXC_F_RPU_SIMO_DMA0ACN_POS 0
566 #define MXC_F_RPU_SIMO_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_DMA0ACN_POS))
568 #define MXC_F_RPU_SIMO_DMA1ACN_POS 1
569 #define MXC_F_RPU_SIMO_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_DMA1ACN_POS))
571 #define MXC_F_RPU_SIMO_USBACN_POS 2
572 #define MXC_F_RPU_SIMO_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_USBACN_POS))
574 #define MXC_F_RPU_SIMO_SYS0ACN_POS 3
575 #define MXC_F_RPU_SIMO_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_SYS0ACN_POS))
577 #define MXC_F_RPU_SIMO_SYS1ACN_POS 4
578 #define MXC_F_RPU_SIMO_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_SYS1ACN_POS))
580 #define MXC_F_RPU_SIMO_SDMADACN_POS 5
581 #define MXC_F_RPU_SIMO_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_SDMADACN_POS))
583 #define MXC_F_RPU_SIMO_SDMAIACN_POS 6
584 #define MXC_F_RPU_SIMO_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_SDMAIACN_POS))
586 #define MXC_F_RPU_SIMO_CRYPTOACN_POS 7
587 #define MXC_F_RPU_SIMO_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_CRYPTOACN_POS))
589 #define MXC_F_RPU_SIMO_SDIOACN_POS 8
590 #define MXC_F_RPU_SIMO_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SIMO_SDIOACN_POS))
600 #define MXC_F_RPU_DVS_DMA0ACN_POS 0
601 #define MXC_F_RPU_DVS_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_DMA0ACN_POS))
603 #define MXC_F_RPU_DVS_DMA1ACN_POS 1
604 #define MXC_F_RPU_DVS_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_DMA1ACN_POS))
606 #define MXC_F_RPU_DVS_USBACN_POS 2
607 #define MXC_F_RPU_DVS_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_USBACN_POS))
609 #define MXC_F_RPU_DVS_SYS0ACN_POS 3
610 #define MXC_F_RPU_DVS_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_SYS0ACN_POS))
612 #define MXC_F_RPU_DVS_SYS1ACN_POS 4
613 #define MXC_F_RPU_DVS_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_SYS1ACN_POS))
615 #define MXC_F_RPU_DVS_SDMADACN_POS 5
616 #define MXC_F_RPU_DVS_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_SDMADACN_POS))
618 #define MXC_F_RPU_DVS_SDMAIACN_POS 6
619 #define MXC_F_RPU_DVS_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_SDMAIACN_POS))
621 #define MXC_F_RPU_DVS_CRYPTOACN_POS 7
622 #define MXC_F_RPU_DVS_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_CRYPTOACN_POS))
624 #define MXC_F_RPU_DVS_SDIOACN_POS 8
625 #define MXC_F_RPU_DVS_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_DVS_SDIOACN_POS))
635 #define MXC_F_RPU_BBSIR_DMA0ACN_POS 0
636 #define MXC_F_RPU_BBSIR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_DMA0ACN_POS))
638 #define MXC_F_RPU_BBSIR_DMA1ACN_POS 1
639 #define MXC_F_RPU_BBSIR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_DMA1ACN_POS))
641 #define MXC_F_RPU_BBSIR_USBACN_POS 2
642 #define MXC_F_RPU_BBSIR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_USBACN_POS))
644 #define MXC_F_RPU_BBSIR_SYS0ACN_POS 3
645 #define MXC_F_RPU_BBSIR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SYS0ACN_POS))
647 #define MXC_F_RPU_BBSIR_SYS1ACN_POS 4
648 #define MXC_F_RPU_BBSIR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SYS1ACN_POS))
650 #define MXC_F_RPU_BBSIR_SDMADACN_POS 5
651 #define MXC_F_RPU_BBSIR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SDMADACN_POS))
653 #define MXC_F_RPU_BBSIR_SDMAIACN_POS 6
654 #define MXC_F_RPU_BBSIR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SDMAIACN_POS))
656 #define MXC_F_RPU_BBSIR_CRYPTOACN_POS 7
657 #define MXC_F_RPU_BBSIR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_CRYPTOACN_POS))
659 #define MXC_F_RPU_BBSIR_SDIOACN_POS 8
660 #define MXC_F_RPU_BBSIR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SDIOACN_POS))
670 #define MXC_F_RPU_RTC_DMA0ACN_POS 0
671 #define MXC_F_RPU_RTC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_DMA0ACN_POS))
673 #define MXC_F_RPU_RTC_DMA1ACN_POS 1
674 #define MXC_F_RPU_RTC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_DMA1ACN_POS))
676 #define MXC_F_RPU_RTC_USBACN_POS 2
677 #define MXC_F_RPU_RTC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_USBACN_POS))
679 #define MXC_F_RPU_RTC_SYS0ACN_POS 3
680 #define MXC_F_RPU_RTC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_SYS0ACN_POS))
682 #define MXC_F_RPU_RTC_SYS1ACN_POS 4
683 #define MXC_F_RPU_RTC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_SYS1ACN_POS))
685 #define MXC_F_RPU_RTC_SDMADACN_POS 5
686 #define MXC_F_RPU_RTC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_SDMADACN_POS))
688 #define MXC_F_RPU_RTC_SDMAIACN_POS 6
689 #define MXC_F_RPU_RTC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_SDMAIACN_POS))
691 #define MXC_F_RPU_RTC_CRYPTOACN_POS 7
692 #define MXC_F_RPU_RTC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_CRYPTOACN_POS))
694 #define MXC_F_RPU_RTC_SDIOACN_POS 8
695 #define MXC_F_RPU_RTC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_RTC_SDIOACN_POS))
705 #define MXC_F_RPU_WUT_DMA0ACN_POS 0
706 #define MXC_F_RPU_WUT_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_DMA0ACN_POS))
708 #define MXC_F_RPU_WUT_DMA1ACN_POS 1
709 #define MXC_F_RPU_WUT_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_DMA1ACN_POS))
711 #define MXC_F_RPU_WUT_USBACN_POS 2
712 #define MXC_F_RPU_WUT_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_USBACN_POS))
714 #define MXC_F_RPU_WUT_SYS0ACN_POS 3
715 #define MXC_F_RPU_WUT_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_SYS0ACN_POS))
717 #define MXC_F_RPU_WUT_SYS1ACN_POS 4
718 #define MXC_F_RPU_WUT_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_SYS1ACN_POS))
720 #define MXC_F_RPU_WUT_SDMADACN_POS 5
721 #define MXC_F_RPU_WUT_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_SDMADACN_POS))
723 #define MXC_F_RPU_WUT_SDMAIACN_POS 6
724 #define MXC_F_RPU_WUT_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_SDMAIACN_POS))
726 #define MXC_F_RPU_WUT_CRYPTOACN_POS 7
727 #define MXC_F_RPU_WUT_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_CRYPTOACN_POS))
729 #define MXC_F_RPU_WUT_SDIOACN_POS 8
730 #define MXC_F_RPU_WUT_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_WUT_SDIOACN_POS))
740 #define MXC_F_RPU_PWRSEQ_DMA0ACN_POS 0
741 #define MXC_F_RPU_PWRSEQ_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA0ACN_POS))
743 #define MXC_F_RPU_PWRSEQ_DMA1ACN_POS 1
744 #define MXC_F_RPU_PWRSEQ_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA1ACN_POS))
746 #define MXC_F_RPU_PWRSEQ_USBACN_POS 2
747 #define MXC_F_RPU_PWRSEQ_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_USBACN_POS))
749 #define MXC_F_RPU_PWRSEQ_SYS0ACN_POS 3
750 #define MXC_F_RPU_PWRSEQ_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS0ACN_POS))
752 #define MXC_F_RPU_PWRSEQ_SYS1ACN_POS 4
753 #define MXC_F_RPU_PWRSEQ_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS1ACN_POS))
755 #define MXC_F_RPU_PWRSEQ_SDMADACN_POS 5
756 #define MXC_F_RPU_PWRSEQ_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMADACN_POS))
758 #define MXC_F_RPU_PWRSEQ_SDMAIACN_POS 6
759 #define MXC_F_RPU_PWRSEQ_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMAIACN_POS))
761 #define MXC_F_RPU_PWRSEQ_CRYPTOACN_POS 7
762 #define MXC_F_RPU_PWRSEQ_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_CRYPTOACN_POS))
764 #define MXC_F_RPU_PWRSEQ_SDIOACN_POS 8
765 #define MXC_F_RPU_PWRSEQ_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDIOACN_POS))
775 #define MXC_F_RPU_MCR_DMA0ACN_POS 0
776 #define MXC_F_RPU_MCR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_DMA0ACN_POS))
778 #define MXC_F_RPU_MCR_DMA1ACN_POS 1
779 #define MXC_F_RPU_MCR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_DMA1ACN_POS))
781 #define MXC_F_RPU_MCR_USBACN_POS 2
782 #define MXC_F_RPU_MCR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_USBACN_POS))
784 #define MXC_F_RPU_MCR_SYS0ACN_POS 3
785 #define MXC_F_RPU_MCR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SYS0ACN_POS))
787 #define MXC_F_RPU_MCR_SYS1ACN_POS 4
788 #define MXC_F_RPU_MCR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SYS1ACN_POS))
790 #define MXC_F_RPU_MCR_SDMADACN_POS 5
791 #define MXC_F_RPU_MCR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SDMADACN_POS))
793 #define MXC_F_RPU_MCR_SDMAIACN_POS 6
794 #define MXC_F_RPU_MCR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SDMAIACN_POS))
796 #define MXC_F_RPU_MCR_CRYPTOACN_POS 7
797 #define MXC_F_RPU_MCR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_CRYPTOACN_POS))
799 #define MXC_F_RPU_MCR_SDIOACN_POS 8
800 #define MXC_F_RPU_MCR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SDIOACN_POS))
810 #define MXC_F_RPU_GPIO0_DMA0ACN_POS 0
811 #define MXC_F_RPU_GPIO0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_DMA0ACN_POS))
813 #define MXC_F_RPU_GPIO0_DMA1ACN_POS 1
814 #define MXC_F_RPU_GPIO0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_DMA1ACN_POS))
816 #define MXC_F_RPU_GPIO0_USBACN_POS 2
817 #define MXC_F_RPU_GPIO0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_USBACN_POS))
819 #define MXC_F_RPU_GPIO0_SYS0ACN_POS 3
820 #define MXC_F_RPU_GPIO0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_SYS0ACN_POS))
822 #define MXC_F_RPU_GPIO0_SYS1ACN_POS 4
823 #define MXC_F_RPU_GPIO0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_SYS1ACN_POS))
825 #define MXC_F_RPU_GPIO0_SDMADACN_POS 5
826 #define MXC_F_RPU_GPIO0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_SDMADACN_POS))
828 #define MXC_F_RPU_GPIO0_SDMAIACN_POS 6
829 #define MXC_F_RPU_GPIO0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_SDMAIACN_POS))
831 #define MXC_F_RPU_GPIO0_CRYPTOACN_POS 7
832 #define MXC_F_RPU_GPIO0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_CRYPTOACN_POS))
834 #define MXC_F_RPU_GPIO0_SDIOACN_POS 8
835 #define MXC_F_RPU_GPIO0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO0_SDIOACN_POS))
845 #define MXC_F_RPU_GPIO1_DMA0ACN_POS 0
846 #define MXC_F_RPU_GPIO1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_DMA0ACN_POS))
848 #define MXC_F_RPU_GPIO1_DMA1ACN_POS 1
849 #define MXC_F_RPU_GPIO1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_DMA1ACN_POS))
851 #define MXC_F_RPU_GPIO1_USBACN_POS 2
852 #define MXC_F_RPU_GPIO1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_USBACN_POS))
854 #define MXC_F_RPU_GPIO1_SYS0ACN_POS 3
855 #define MXC_F_RPU_GPIO1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_SYS0ACN_POS))
857 #define MXC_F_RPU_GPIO1_SYS1ACN_POS 4
858 #define MXC_F_RPU_GPIO1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_SYS1ACN_POS))
860 #define MXC_F_RPU_GPIO1_SDMADACN_POS 5
861 #define MXC_F_RPU_GPIO1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_SDMADACN_POS))
863 #define MXC_F_RPU_GPIO1_SDMAIACN_POS 6
864 #define MXC_F_RPU_GPIO1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_SDMAIACN_POS))
866 #define MXC_F_RPU_GPIO1_CRYPTOACN_POS 7
867 #define MXC_F_RPU_GPIO1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_CRYPTOACN_POS))
869 #define MXC_F_RPU_GPIO1_SDIOACN_POS 8
870 #define MXC_F_RPU_GPIO1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_GPIO1_SDIOACN_POS))
880 #define MXC_F_RPU_TMR0_DMA0ACN_POS 0
881 #define MXC_F_RPU_TMR0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_DMA0ACN_POS))
883 #define MXC_F_RPU_TMR0_DMA1ACN_POS 1
884 #define MXC_F_RPU_TMR0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_DMA1ACN_POS))
886 #define MXC_F_RPU_TMR0_USBACN_POS 2
887 #define MXC_F_RPU_TMR0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_USBACN_POS))
889 #define MXC_F_RPU_TMR0_SYS0ACN_POS 3
890 #define MXC_F_RPU_TMR0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_SYS0ACN_POS))
892 #define MXC_F_RPU_TMR0_SYS1ACN_POS 4
893 #define MXC_F_RPU_TMR0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_SYS1ACN_POS))
895 #define MXC_F_RPU_TMR0_SDMADACN_POS 5
896 #define MXC_F_RPU_TMR0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_SDMADACN_POS))
898 #define MXC_F_RPU_TMR0_SDMAIACN_POS 6
899 #define MXC_F_RPU_TMR0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_SDMAIACN_POS))
901 #define MXC_F_RPU_TMR0_CRYPTOACN_POS 7
902 #define MXC_F_RPU_TMR0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_CRYPTOACN_POS))
904 #define MXC_F_RPU_TMR0_SDIOACN_POS 8
905 #define MXC_F_RPU_TMR0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR0_SDIOACN_POS))
915 #define MXC_F_RPU_TMR1_DMA0ACN_POS 0
916 #define MXC_F_RPU_TMR1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_DMA0ACN_POS))
918 #define MXC_F_RPU_TMR1_DMA1ACN_POS 1
919 #define MXC_F_RPU_TMR1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_DMA1ACN_POS))
921 #define MXC_F_RPU_TMR1_USBACN_POS 2
922 #define MXC_F_RPU_TMR1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_USBACN_POS))
924 #define MXC_F_RPU_TMR1_SYS0ACN_POS 3
925 #define MXC_F_RPU_TMR1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SYS0ACN_POS))
927 #define MXC_F_RPU_TMR1_SYS1ACN_POS 4
928 #define MXC_F_RPU_TMR1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SYS1ACN_POS))
930 #define MXC_F_RPU_TMR1_SDMADACN_POS 5
931 #define MXC_F_RPU_TMR1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SDMADACN_POS))
933 #define MXC_F_RPU_TMR1_SDMAIACN_POS 6
934 #define MXC_F_RPU_TMR1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SDMAIACN_POS))
936 #define MXC_F_RPU_TMR1_CRYPTOACN_POS 7
937 #define MXC_F_RPU_TMR1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_CRYPTOACN_POS))
939 #define MXC_F_RPU_TMR1_SDIOACN_POS 8
940 #define MXC_F_RPU_TMR1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SDIOACN_POS))
950 #define MXC_F_RPU_TMR2_DMA0ACN_POS 0
951 #define MXC_F_RPU_TMR2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_DMA0ACN_POS))
953 #define MXC_F_RPU_TMR2_DMA1ACN_POS 1
954 #define MXC_F_RPU_TMR2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_DMA1ACN_POS))
956 #define MXC_F_RPU_TMR2_USBACN_POS 2
957 #define MXC_F_RPU_TMR2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_USBACN_POS))
959 #define MXC_F_RPU_TMR2_SYS0ACN_POS 3
960 #define MXC_F_RPU_TMR2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_SYS0ACN_POS))
962 #define MXC_F_RPU_TMR2_SYS1ACN_POS 4
963 #define MXC_F_RPU_TMR2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_SYS1ACN_POS))
965 #define MXC_F_RPU_TMR2_SDMADACN_POS 5
966 #define MXC_F_RPU_TMR2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_SDMADACN_POS))
968 #define MXC_F_RPU_TMR2_SDMAIACN_POS 6
969 #define MXC_F_RPU_TMR2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_SDMAIACN_POS))
971 #define MXC_F_RPU_TMR2_CRYPTOACN_POS 7
972 #define MXC_F_RPU_TMR2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_CRYPTOACN_POS))
974 #define MXC_F_RPU_TMR2_SDIOACN_POS 8
975 #define MXC_F_RPU_TMR2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR2_SDIOACN_POS))
985 #define MXC_F_RPU_TMR3_DMA0ACN_POS 0
986 #define MXC_F_RPU_TMR3_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_DMA0ACN_POS))
988 #define MXC_F_RPU_TMR3_DMA1ACN_POS 1
989 #define MXC_F_RPU_TMR3_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_DMA1ACN_POS))
991 #define MXC_F_RPU_TMR3_USBACN_POS 2
992 #define MXC_F_RPU_TMR3_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_USBACN_POS))
994 #define MXC_F_RPU_TMR3_SYS0ACN_POS 3
995 #define MXC_F_RPU_TMR3_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_SYS0ACN_POS))
997 #define MXC_F_RPU_TMR3_SYS1ACN_POS 4
998 #define MXC_F_RPU_TMR3_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_SYS1ACN_POS))
1000 #define MXC_F_RPU_TMR3_SDMADACN_POS 5
1001 #define MXC_F_RPU_TMR3_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_SDMADACN_POS))
1003 #define MXC_F_RPU_TMR3_SDMAIACN_POS 6
1004 #define MXC_F_RPU_TMR3_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_SDMAIACN_POS))
1006 #define MXC_F_RPU_TMR3_CRYPTOACN_POS 7
1007 #define MXC_F_RPU_TMR3_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_CRYPTOACN_POS))
1009 #define MXC_F_RPU_TMR3_SDIOACN_POS 8
1010 #define MXC_F_RPU_TMR3_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR3_SDIOACN_POS))
1020 #define MXC_F_RPU_TMR4_DMA0ACN_POS 0
1021 #define MXC_F_RPU_TMR4_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_DMA0ACN_POS))
1023 #define MXC_F_RPU_TMR4_DMA1ACN_POS 1
1024 #define MXC_F_RPU_TMR4_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_DMA1ACN_POS))
1026 #define MXC_F_RPU_TMR4_USBACN_POS 2
1027 #define MXC_F_RPU_TMR4_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_USBACN_POS))
1029 #define MXC_F_RPU_TMR4_SYS0ACN_POS 3
1030 #define MXC_F_RPU_TMR4_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_SYS0ACN_POS))
1032 #define MXC_F_RPU_TMR4_SYS1ACN_POS 4
1033 #define MXC_F_RPU_TMR4_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_SYS1ACN_POS))
1035 #define MXC_F_RPU_TMR4_SDMADACN_POS 5
1036 #define MXC_F_RPU_TMR4_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_SDMADACN_POS))
1038 #define MXC_F_RPU_TMR4_SDMAIACN_POS 6
1039 #define MXC_F_RPU_TMR4_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_SDMAIACN_POS))
1041 #define MXC_F_RPU_TMR4_CRYPTOACN_POS 7
1042 #define MXC_F_RPU_TMR4_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_CRYPTOACN_POS))
1044 #define MXC_F_RPU_TMR4_SDIOACN_POS 8
1045 #define MXC_F_RPU_TMR4_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR4_SDIOACN_POS))
1055 #define MXC_F_RPU_TMR5_DMA0ACN_POS 0
1056 #define MXC_F_RPU_TMR5_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_DMA0ACN_POS))
1058 #define MXC_F_RPU_TMR5_DMA1ACN_POS 1
1059 #define MXC_F_RPU_TMR5_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_DMA1ACN_POS))
1061 #define MXC_F_RPU_TMR5_USBACN_POS 2
1062 #define MXC_F_RPU_TMR5_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_USBACN_POS))
1064 #define MXC_F_RPU_TMR5_SYS0ACN_POS 3
1065 #define MXC_F_RPU_TMR5_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SYS0ACN_POS))
1067 #define MXC_F_RPU_TMR5_SYS1ACN_POS 4
1068 #define MXC_F_RPU_TMR5_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SYS1ACN_POS))
1070 #define MXC_F_RPU_TMR5_SDMADACN_POS 5
1071 #define MXC_F_RPU_TMR5_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SDMADACN_POS))
1073 #define MXC_F_RPU_TMR5_SDMAIACN_POS 6
1074 #define MXC_F_RPU_TMR5_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SDMAIACN_POS))
1076 #define MXC_F_RPU_TMR5_CRYPTOACN_POS 7
1077 #define MXC_F_RPU_TMR5_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_CRYPTOACN_POS))
1079 #define MXC_F_RPU_TMR5_SDIOACN_POS 8
1080 #define MXC_F_RPU_TMR5_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SDIOACN_POS))
1090 #define MXC_F_RPU_HTIMER0_DMA0ACN_POS 0
1091 #define MXC_F_RPU_HTIMER0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_DMA0ACN_POS))
1093 #define MXC_F_RPU_HTIMER0_DMA1ACN_POS 1
1094 #define MXC_F_RPU_HTIMER0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_DMA1ACN_POS))
1096 #define MXC_F_RPU_HTIMER0_USBACN_POS 2
1097 #define MXC_F_RPU_HTIMER0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_USBACN_POS))
1099 #define MXC_F_RPU_HTIMER0_SYS0ACN_POS 3
1100 #define MXC_F_RPU_HTIMER0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SYS0ACN_POS))
1102 #define MXC_F_RPU_HTIMER0_SYS1ACN_POS 4
1103 #define MXC_F_RPU_HTIMER0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SYS1ACN_POS))
1105 #define MXC_F_RPU_HTIMER0_SDMADACN_POS 5
1106 #define MXC_F_RPU_HTIMER0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDMADACN_POS))
1108 #define MXC_F_RPU_HTIMER0_SDMAIACN_POS 6
1109 #define MXC_F_RPU_HTIMER0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDMAIACN_POS))
1111 #define MXC_F_RPU_HTIMER0_CRYPTOACN_POS 7
1112 #define MXC_F_RPU_HTIMER0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_CRYPTOACN_POS))
1114 #define MXC_F_RPU_HTIMER0_SDIOACN_POS 8
1115 #define MXC_F_RPU_HTIMER0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER0_SDIOACN_POS))
1125 #define MXC_F_RPU_HTIMER1_DMA0ACN_POS 0
1126 #define MXC_F_RPU_HTIMER1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_DMA0ACN_POS))
1128 #define MXC_F_RPU_HTIMER1_DMA1ACN_POS 1
1129 #define MXC_F_RPU_HTIMER1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_DMA1ACN_POS))
1131 #define MXC_F_RPU_HTIMER1_USBACN_POS 2
1132 #define MXC_F_RPU_HTIMER1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_USBACN_POS))
1134 #define MXC_F_RPU_HTIMER1_SYS0ACN_POS 3
1135 #define MXC_F_RPU_HTIMER1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SYS0ACN_POS))
1137 #define MXC_F_RPU_HTIMER1_SYS1ACN_POS 4
1138 #define MXC_F_RPU_HTIMER1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SYS1ACN_POS))
1140 #define MXC_F_RPU_HTIMER1_SDMADACN_POS 5
1141 #define MXC_F_RPU_HTIMER1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDMADACN_POS))
1143 #define MXC_F_RPU_HTIMER1_SDMAIACN_POS 6
1144 #define MXC_F_RPU_HTIMER1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDMAIACN_POS))
1146 #define MXC_F_RPU_HTIMER1_CRYPTOACN_POS 7
1147 #define MXC_F_RPU_HTIMER1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_CRYPTOACN_POS))
1149 #define MXC_F_RPU_HTIMER1_SDIOACN_POS 8
1150 #define MXC_F_RPU_HTIMER1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDIOACN_POS))
1160 #define MXC_F_RPU_I2C0_BUS0_DMA0ACN_POS 0
1161 #define MXC_F_RPU_I2C0_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_DMA0ACN_POS))
1163 #define MXC_F_RPU_I2C0_BUS0_DMA1ACN_POS 1
1164 #define MXC_F_RPU_I2C0_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_DMA1ACN_POS))
1166 #define MXC_F_RPU_I2C0_BUS0_USBACN_POS 2
1167 #define MXC_F_RPU_I2C0_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_USBACN_POS))
1169 #define MXC_F_RPU_I2C0_BUS0_SYS0ACN_POS 3
1170 #define MXC_F_RPU_I2C0_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SYS0ACN_POS))
1172 #define MXC_F_RPU_I2C0_BUS0_SYS1ACN_POS 4
1173 #define MXC_F_RPU_I2C0_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SYS1ACN_POS))
1175 #define MXC_F_RPU_I2C0_BUS0_SDMADACN_POS 5
1176 #define MXC_F_RPU_I2C0_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SDMADACN_POS))
1178 #define MXC_F_RPU_I2C0_BUS0_SDMAIACN_POS 6
1179 #define MXC_F_RPU_I2C0_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SDMAIACN_POS))
1181 #define MXC_F_RPU_I2C0_BUS0_CRYPTOACN_POS 7
1182 #define MXC_F_RPU_I2C0_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_CRYPTOACN_POS))
1184 #define MXC_F_RPU_I2C0_BUS0_SDIOACN_POS 8
1185 #define MXC_F_RPU_I2C0_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SDIOACN_POS))
1195 #define MXC_F_RPU_I2C1_BUS0_DMA0ACN_POS 0
1196 #define MXC_F_RPU_I2C1_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_DMA0ACN_POS))
1198 #define MXC_F_RPU_I2C1_BUS0_DMA1ACN_POS 1
1199 #define MXC_F_RPU_I2C1_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_DMA1ACN_POS))
1201 #define MXC_F_RPU_I2C1_BUS0_USBACN_POS 2
1202 #define MXC_F_RPU_I2C1_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_USBACN_POS))
1204 #define MXC_F_RPU_I2C1_BUS0_SYS0ACN_POS 3
1205 #define MXC_F_RPU_I2C1_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SYS0ACN_POS))
1207 #define MXC_F_RPU_I2C1_BUS0_SYS1ACN_POS 4
1208 #define MXC_F_RPU_I2C1_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SYS1ACN_POS))
1210 #define MXC_F_RPU_I2C1_BUS0_SDMADACN_POS 5
1211 #define MXC_F_RPU_I2C1_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SDMADACN_POS))
1213 #define MXC_F_RPU_I2C1_BUS0_SDMAIACN_POS 6
1214 #define MXC_F_RPU_I2C1_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SDMAIACN_POS))
1216 #define MXC_F_RPU_I2C1_BUS0_CRYPTOACN_POS 7
1217 #define MXC_F_RPU_I2C1_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_CRYPTOACN_POS))
1219 #define MXC_F_RPU_I2C1_BUS0_SDIOACN_POS 8
1220 #define MXC_F_RPU_I2C1_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SDIOACN_POS))
1230 #define MXC_F_RPU_I2C2_BUS0_DMA0ACN_POS 0
1231 #define MXC_F_RPU_I2C2_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_DMA0ACN_POS))
1233 #define MXC_F_RPU_I2C2_BUS0_DMA1ACN_POS 1
1234 #define MXC_F_RPU_I2C2_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_DMA1ACN_POS))
1236 #define MXC_F_RPU_I2C2_BUS0_USBACN_POS 2
1237 #define MXC_F_RPU_I2C2_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_USBACN_POS))
1239 #define MXC_F_RPU_I2C2_BUS0_SYS0ACN_POS 3
1240 #define MXC_F_RPU_I2C2_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SYS0ACN_POS))
1242 #define MXC_F_RPU_I2C2_BUS0_SYS1ACN_POS 4
1243 #define MXC_F_RPU_I2C2_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SYS1ACN_POS))
1245 #define MXC_F_RPU_I2C2_BUS0_SDMADACN_POS 5
1246 #define MXC_F_RPU_I2C2_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SDMADACN_POS))
1248 #define MXC_F_RPU_I2C2_BUS0_SDMAIACN_POS 6
1249 #define MXC_F_RPU_I2C2_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SDMAIACN_POS))
1251 #define MXC_F_RPU_I2C2_BUS0_CRYPTOACN_POS 7
1252 #define MXC_F_RPU_I2C2_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_CRYPTOACN_POS))
1254 #define MXC_F_RPU_I2C2_BUS0_SDIOACN_POS 8
1255 #define MXC_F_RPU_I2C2_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SDIOACN_POS))
1265 #define MXC_F_RPU_SPIXFM_DMA0ACN_POS 0
1266 #define MXC_F_RPU_SPIXFM_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_DMA0ACN_POS))
1268 #define MXC_F_RPU_SPIXFM_DMA1ACN_POS 1
1269 #define MXC_F_RPU_SPIXFM_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_DMA1ACN_POS))
1271 #define MXC_F_RPU_SPIXFM_USBACN_POS 2
1272 #define MXC_F_RPU_SPIXFM_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_USBACN_POS))
1274 #define MXC_F_RPU_SPIXFM_SYS0ACN_POS 3
1275 #define MXC_F_RPU_SPIXFM_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SYS0ACN_POS))
1277 #define MXC_F_RPU_SPIXFM_SYS1ACN_POS 4
1278 #define MXC_F_RPU_SPIXFM_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SYS1ACN_POS))
1280 #define MXC_F_RPU_SPIXFM_SDMADACN_POS 5
1281 #define MXC_F_RPU_SPIXFM_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SDMADACN_POS))
1283 #define MXC_F_RPU_SPIXFM_SDMAIACN_POS 6
1284 #define MXC_F_RPU_SPIXFM_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SDMAIACN_POS))
1286 #define MXC_F_RPU_SPIXFM_CRYPTOACN_POS 7
1287 #define MXC_F_RPU_SPIXFM_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_CRYPTOACN_POS))
1289 #define MXC_F_RPU_SPIXFM_SDIOACN_POS 8
1290 #define MXC_F_RPU_SPIXFM_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SDIOACN_POS))
1300 #define MXC_F_RPU_SPIXFC_DMA0ACN_POS 0
1301 #define MXC_F_RPU_SPIXFC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_DMA0ACN_POS))
1303 #define MXC_F_RPU_SPIXFC_DMA1ACN_POS 1
1304 #define MXC_F_RPU_SPIXFC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_DMA1ACN_POS))
1306 #define MXC_F_RPU_SPIXFC_USBACN_POS 2
1307 #define MXC_F_RPU_SPIXFC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_USBACN_POS))
1309 #define MXC_F_RPU_SPIXFC_SYS0ACN_POS 3
1310 #define MXC_F_RPU_SPIXFC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SYS0ACN_POS))
1312 #define MXC_F_RPU_SPIXFC_SYS1ACN_POS 4
1313 #define MXC_F_RPU_SPIXFC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SYS1ACN_POS))
1315 #define MXC_F_RPU_SPIXFC_SDMADACN_POS 5
1316 #define MXC_F_RPU_SPIXFC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SDMADACN_POS))
1318 #define MXC_F_RPU_SPIXFC_SDMAIACN_POS 6
1319 #define MXC_F_RPU_SPIXFC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SDMAIACN_POS))
1321 #define MXC_F_RPU_SPIXFC_CRYPTOACN_POS 7
1322 #define MXC_F_RPU_SPIXFC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_CRYPTOACN_POS))
1324 #define MXC_F_RPU_SPIXFC_SDIOACN_POS 8
1325 #define MXC_F_RPU_SPIXFC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SDIOACN_POS))
1335 #define MXC_F_RPU_DMA0_DMA0ACN_POS 0
1336 #define MXC_F_RPU_DMA0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_DMA0ACN_POS))
1338 #define MXC_F_RPU_DMA0_DMA1ACN_POS 1
1339 #define MXC_F_RPU_DMA0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_DMA1ACN_POS))
1341 #define MXC_F_RPU_DMA0_USBACN_POS 2
1342 #define MXC_F_RPU_DMA0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_USBACN_POS))
1344 #define MXC_F_RPU_DMA0_SYS0ACN_POS 3
1345 #define MXC_F_RPU_DMA0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_SYS0ACN_POS))
1347 #define MXC_F_RPU_DMA0_SYS1ACN_POS 4
1348 #define MXC_F_RPU_DMA0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_SYS1ACN_POS))
1350 #define MXC_F_RPU_DMA0_SDMADACN_POS 5
1351 #define MXC_F_RPU_DMA0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_SDMADACN_POS))
1353 #define MXC_F_RPU_DMA0_SDMAIACN_POS 6
1354 #define MXC_F_RPU_DMA0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_SDMAIACN_POS))
1356 #define MXC_F_RPU_DMA0_CRYPTOACN_POS 7
1357 #define MXC_F_RPU_DMA0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_CRYPTOACN_POS))
1359 #define MXC_F_RPU_DMA0_SDIOACN_POS 8
1360 #define MXC_F_RPU_DMA0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA0_SDIOACN_POS))
1370 #define MXC_F_RPU_FLC0_DMA0ACN_POS 0
1371 #define MXC_F_RPU_FLC0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_DMA0ACN_POS))
1373 #define MXC_F_RPU_FLC0_DMA1ACN_POS 1
1374 #define MXC_F_RPU_FLC0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_DMA1ACN_POS))
1376 #define MXC_F_RPU_FLC0_USBACN_POS 2
1377 #define MXC_F_RPU_FLC0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_USBACN_POS))
1379 #define MXC_F_RPU_FLC0_SYS0ACN_POS 3
1380 #define MXC_F_RPU_FLC0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_SYS0ACN_POS))
1382 #define MXC_F_RPU_FLC0_SYS1ACN_POS 4
1383 #define MXC_F_RPU_FLC0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_SYS1ACN_POS))
1385 #define MXC_F_RPU_FLC0_SDMADACN_POS 5
1386 #define MXC_F_RPU_FLC0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_SDMADACN_POS))
1388 #define MXC_F_RPU_FLC0_SDMAIACN_POS 6
1389 #define MXC_F_RPU_FLC0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_SDMAIACN_POS))
1391 #define MXC_F_RPU_FLC0_CRYPTOACN_POS 7
1392 #define MXC_F_RPU_FLC0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_CRYPTOACN_POS))
1394 #define MXC_F_RPU_FLC0_SDIOACN_POS 8
1395 #define MXC_F_RPU_FLC0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC0_SDIOACN_POS))
1405 #define MXC_F_RPU_FLC1_DMA0ACN_POS 0
1406 #define MXC_F_RPU_FLC1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_DMA0ACN_POS))
1408 #define MXC_F_RPU_FLC1_DMA1ACN_POS 1
1409 #define MXC_F_RPU_FLC1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_DMA1ACN_POS))
1411 #define MXC_F_RPU_FLC1_USBACN_POS 2
1412 #define MXC_F_RPU_FLC1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_USBACN_POS))
1414 #define MXC_F_RPU_FLC1_SYS0ACN_POS 3
1415 #define MXC_F_RPU_FLC1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_SYS0ACN_POS))
1417 #define MXC_F_RPU_FLC1_SYS1ACN_POS 4
1418 #define MXC_F_RPU_FLC1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_SYS1ACN_POS))
1420 #define MXC_F_RPU_FLC1_SDMADACN_POS 5
1421 #define MXC_F_RPU_FLC1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_SDMADACN_POS))
1423 #define MXC_F_RPU_FLC1_SDMAIACN_POS 6
1424 #define MXC_F_RPU_FLC1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_SDMAIACN_POS))
1426 #define MXC_F_RPU_FLC1_CRYPTOACN_POS 7
1427 #define MXC_F_RPU_FLC1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_CRYPTOACN_POS))
1429 #define MXC_F_RPU_FLC1_SDIOACN_POS 8
1430 #define MXC_F_RPU_FLC1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_FLC1_SDIOACN_POS))
1440 #define MXC_F_RPU_ICC0_DMA0ACN_POS 0
1441 #define MXC_F_RPU_ICC0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_DMA0ACN_POS))
1443 #define MXC_F_RPU_ICC0_DMA1ACN_POS 1
1444 #define MXC_F_RPU_ICC0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_DMA1ACN_POS))
1446 #define MXC_F_RPU_ICC0_USBACN_POS 2
1447 #define MXC_F_RPU_ICC0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_USBACN_POS))
1449 #define MXC_F_RPU_ICC0_SYS0ACN_POS 3
1450 #define MXC_F_RPU_ICC0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SYS0ACN_POS))
1452 #define MXC_F_RPU_ICC0_SYS1ACN_POS 4
1453 #define MXC_F_RPU_ICC0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SYS1ACN_POS))
1455 #define MXC_F_RPU_ICC0_SDMADACN_POS 5
1456 #define MXC_F_RPU_ICC0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SDMADACN_POS))
1458 #define MXC_F_RPU_ICC0_SDMAIACN_POS 6
1459 #define MXC_F_RPU_ICC0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SDMAIACN_POS))
1461 #define MXC_F_RPU_ICC0_CRYPTOACN_POS 7
1462 #define MXC_F_RPU_ICC0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_CRYPTOACN_POS))
1464 #define MXC_F_RPU_ICC0_SDIOACN_POS 8
1465 #define MXC_F_RPU_ICC0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SDIOACN_POS))
1475 #define MXC_F_RPU_ICC1_DMA0ACN_POS 0
1476 #define MXC_F_RPU_ICC1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_DMA0ACN_POS))
1478 #define MXC_F_RPU_ICC1_DMA1ACN_POS 1
1479 #define MXC_F_RPU_ICC1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_DMA1ACN_POS))
1481 #define MXC_F_RPU_ICC1_USBACN_POS 2
1482 #define MXC_F_RPU_ICC1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_USBACN_POS))
1484 #define MXC_F_RPU_ICC1_SYS0ACN_POS 3
1485 #define MXC_F_RPU_ICC1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SYS0ACN_POS))
1487 #define MXC_F_RPU_ICC1_SYS1ACN_POS 4
1488 #define MXC_F_RPU_ICC1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SYS1ACN_POS))
1490 #define MXC_F_RPU_ICC1_SDMADACN_POS 5
1491 #define MXC_F_RPU_ICC1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SDMADACN_POS))
1493 #define MXC_F_RPU_ICC1_SDMAIACN_POS 6
1494 #define MXC_F_RPU_ICC1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SDMAIACN_POS))
1496 #define MXC_F_RPU_ICC1_CRYPTOACN_POS 7
1497 #define MXC_F_RPU_ICC1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_CRYPTOACN_POS))
1499 #define MXC_F_RPU_ICC1_SDIOACN_POS 8
1500 #define MXC_F_RPU_ICC1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SDIOACN_POS))
1510 #define MXC_F_RPU_SFCC_DMA0ACN_POS 0
1511 #define MXC_F_RPU_SFCC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_DMA0ACN_POS))
1513 #define MXC_F_RPU_SFCC_DMA1ACN_POS 1
1514 #define MXC_F_RPU_SFCC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_DMA1ACN_POS))
1516 #define MXC_F_RPU_SFCC_USBACN_POS 2
1517 #define MXC_F_RPU_SFCC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_USBACN_POS))
1519 #define MXC_F_RPU_SFCC_SYS0ACN_POS 3
1520 #define MXC_F_RPU_SFCC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SYS0ACN_POS))
1522 #define MXC_F_RPU_SFCC_SYS1ACN_POS 4
1523 #define MXC_F_RPU_SFCC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SYS1ACN_POS))
1525 #define MXC_F_RPU_SFCC_SDMADACN_POS 5
1526 #define MXC_F_RPU_SFCC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDMADACN_POS))
1528 #define MXC_F_RPU_SFCC_SDMAIACN_POS 6
1529 #define MXC_F_RPU_SFCC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDMAIACN_POS))
1531 #define MXC_F_RPU_SFCC_CRYPTOACN_POS 7
1532 #define MXC_F_RPU_SFCC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_CRYPTOACN_POS))
1534 #define MXC_F_RPU_SFCC_SDIOACN_POS 8
1535 #define MXC_F_RPU_SFCC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDIOACN_POS))
1545 #define MXC_F_RPU_SRCC_DMA0ACN_POS 0
1546 #define MXC_F_RPU_SRCC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_DMA0ACN_POS))
1548 #define MXC_F_RPU_SRCC_DMA1ACN_POS 1
1549 #define MXC_F_RPU_SRCC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_DMA1ACN_POS))
1551 #define MXC_F_RPU_SRCC_USBACN_POS 2
1552 #define MXC_F_RPU_SRCC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_USBACN_POS))
1554 #define MXC_F_RPU_SRCC_SYS0ACN_POS 3
1555 #define MXC_F_RPU_SRCC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SYS0ACN_POS))
1557 #define MXC_F_RPU_SRCC_SYS1ACN_POS 4
1558 #define MXC_F_RPU_SRCC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SYS1ACN_POS))
1560 #define MXC_F_RPU_SRCC_SDMADACN_POS 5
1561 #define MXC_F_RPU_SRCC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDMADACN_POS))
1563 #define MXC_F_RPU_SRCC_SDMAIACN_POS 6
1564 #define MXC_F_RPU_SRCC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDMAIACN_POS))
1566 #define MXC_F_RPU_SRCC_CRYPTOACN_POS 7
1567 #define MXC_F_RPU_SRCC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_CRYPTOACN_POS))
1569 #define MXC_F_RPU_SRCC_SDIOACN_POS 8
1570 #define MXC_F_RPU_SRCC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDIOACN_POS))
1580 #define MXC_F_RPU_ADC_DMA0ACN_POS 0
1581 #define MXC_F_RPU_ADC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_DMA0ACN_POS))
1583 #define MXC_F_RPU_ADC_DMA1ACN_POS 1
1584 #define MXC_F_RPU_ADC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_DMA1ACN_POS))
1586 #define MXC_F_RPU_ADC_USBACN_POS 2
1587 #define MXC_F_RPU_ADC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_USBACN_POS))
1589 #define MXC_F_RPU_ADC_SYS0ACN_POS 3
1590 #define MXC_F_RPU_ADC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_SYS0ACN_POS))
1592 #define MXC_F_RPU_ADC_SYS1ACN_POS 4
1593 #define MXC_F_RPU_ADC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_SYS1ACN_POS))
1595 #define MXC_F_RPU_ADC_SDMADACN_POS 5
1596 #define MXC_F_RPU_ADC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_SDMADACN_POS))
1598 #define MXC_F_RPU_ADC_SDMAIACN_POS 6
1599 #define MXC_F_RPU_ADC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_SDMAIACN_POS))
1601 #define MXC_F_RPU_ADC_CRYPTOACN_POS 7
1602 #define MXC_F_RPU_ADC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_CRYPTOACN_POS))
1604 #define MXC_F_RPU_ADC_SDIOACN_POS 8
1605 #define MXC_F_RPU_ADC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ADC_SDIOACN_POS))
1615 #define MXC_F_RPU_DMA1_DMA0ACN_POS 0
1616 #define MXC_F_RPU_DMA1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_DMA0ACN_POS))
1618 #define MXC_F_RPU_DMA1_DMA1ACN_POS 1
1619 #define MXC_F_RPU_DMA1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_DMA1ACN_POS))
1621 #define MXC_F_RPU_DMA1_USBACN_POS 2
1622 #define MXC_F_RPU_DMA1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_USBACN_POS))
1624 #define MXC_F_RPU_DMA1_SYS0ACN_POS 3
1625 #define MXC_F_RPU_DMA1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_SYS0ACN_POS))
1627 #define MXC_F_RPU_DMA1_SYS1ACN_POS 4
1628 #define MXC_F_RPU_DMA1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_SYS1ACN_POS))
1630 #define MXC_F_RPU_DMA1_SDMADACN_POS 5
1631 #define MXC_F_RPU_DMA1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_SDMADACN_POS))
1633 #define MXC_F_RPU_DMA1_SDMAIACN_POS 6
1634 #define MXC_F_RPU_DMA1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_SDMAIACN_POS))
1636 #define MXC_F_RPU_DMA1_CRYPTOACN_POS 7
1637 #define MXC_F_RPU_DMA1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_CRYPTOACN_POS))
1639 #define MXC_F_RPU_DMA1_SDIOACN_POS 8
1640 #define MXC_F_RPU_DMA1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_DMA1_SDIOACN_POS))
1650 #define MXC_F_RPU_SDMA_DMA0ACN_POS 0
1651 #define MXC_F_RPU_SDMA_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_DMA0ACN_POS))
1653 #define MXC_F_RPU_SDMA_DMA1ACN_POS 1
1654 #define MXC_F_RPU_SDMA_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_DMA1ACN_POS))
1656 #define MXC_F_RPU_SDMA_USBACN_POS 2
1657 #define MXC_F_RPU_SDMA_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_USBACN_POS))
1659 #define MXC_F_RPU_SDMA_SYS0ACN_POS 3
1660 #define MXC_F_RPU_SDMA_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_SYS0ACN_POS))
1662 #define MXC_F_RPU_SDMA_SYS1ACN_POS 4
1663 #define MXC_F_RPU_SDMA_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_SYS1ACN_POS))
1665 #define MXC_F_RPU_SDMA_SDMADACN_POS 5
1666 #define MXC_F_RPU_SDMA_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_SDMADACN_POS))
1668 #define MXC_F_RPU_SDMA_SDMAIACN_POS 6
1669 #define MXC_F_RPU_SDMA_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_SDMAIACN_POS))
1671 #define MXC_F_RPU_SDMA_CRYPTOACN_POS 7
1672 #define MXC_F_RPU_SDMA_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_CRYPTOACN_POS))
1674 #define MXC_F_RPU_SDMA_SDIOACN_POS 8
1675 #define MXC_F_RPU_SDMA_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SDMA_SDIOACN_POS))
1685 #define MXC_F_RPU_SDHCCTRL_DMA0ACN_POS 0
1686 #define MXC_F_RPU_SDHCCTRL_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_DMA0ACN_POS))
1688 #define MXC_F_RPU_SDHCCTRL_DMA1ACN_POS 1
1689 #define MXC_F_RPU_SDHCCTRL_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_DMA1ACN_POS))
1691 #define MXC_F_RPU_SDHCCTRL_USBACN_POS 2
1692 #define MXC_F_RPU_SDHCCTRL_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_USBACN_POS))
1694 #define MXC_F_RPU_SDHCCTRL_SYS0ACN_POS 3
1695 #define MXC_F_RPU_SDHCCTRL_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_SYS0ACN_POS))
1697 #define MXC_F_RPU_SDHCCTRL_SYS1ACN_POS 4
1698 #define MXC_F_RPU_SDHCCTRL_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_SYS1ACN_POS))
1700 #define MXC_F_RPU_SDHCCTRL_SDMADACN_POS 5
1701 #define MXC_F_RPU_SDHCCTRL_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_SDMADACN_POS))
1703 #define MXC_F_RPU_SDHCCTRL_SDMAIACN_POS 6
1704 #define MXC_F_RPU_SDHCCTRL_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_SDMAIACN_POS))
1706 #define MXC_F_RPU_SDHCCTRL_CRYPTOACN_POS 7
1707 #define MXC_F_RPU_SDHCCTRL_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_CRYPTOACN_POS))
1709 #define MXC_F_RPU_SDHCCTRL_SDIOACN_POS 8
1710 #define MXC_F_RPU_SDHCCTRL_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SDHCCTRL_SDIOACN_POS))
1720 #define MXC_F_RPU_SPIXR_DMA0ACN_POS 0
1721 #define MXC_F_RPU_SPIXR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_DMA0ACN_POS))
1723 #define MXC_F_RPU_SPIXR_DMA1ACN_POS 1
1724 #define MXC_F_RPU_SPIXR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_DMA1ACN_POS))
1726 #define MXC_F_RPU_SPIXR_USBACN_POS 2
1727 #define MXC_F_RPU_SPIXR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_USBACN_POS))
1729 #define MXC_F_RPU_SPIXR_SYS0ACN_POS 3
1730 #define MXC_F_RPU_SPIXR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SYS0ACN_POS))
1732 #define MXC_F_RPU_SPIXR_SYS1ACN_POS 4
1733 #define MXC_F_RPU_SPIXR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SYS1ACN_POS))
1735 #define MXC_F_RPU_SPIXR_SDMADACN_POS 5
1736 #define MXC_F_RPU_SPIXR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SDMADACN_POS))
1738 #define MXC_F_RPU_SPIXR_SDMAIACN_POS 6
1739 #define MXC_F_RPU_SPIXR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SDMAIACN_POS))
1741 #define MXC_F_RPU_SPIXR_CRYPTOACN_POS 7
1742 #define MXC_F_RPU_SPIXR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_CRYPTOACN_POS))
1744 #define MXC_F_RPU_SPIXR_SDIOACN_POS 8
1745 #define MXC_F_RPU_SPIXR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SDIOACN_POS))
1755 #define MXC_F_RPU_PTG_BUS0_DMA0ACN_POS 0
1756 #define MXC_F_RPU_PTG_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_DMA0ACN_POS))
1758 #define MXC_F_RPU_PTG_BUS0_DMA1ACN_POS 1
1759 #define MXC_F_RPU_PTG_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_DMA1ACN_POS))
1761 #define MXC_F_RPU_PTG_BUS0_USBACN_POS 2
1762 #define MXC_F_RPU_PTG_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_USBACN_POS))
1764 #define MXC_F_RPU_PTG_BUS0_SYS0ACN_POS 3
1765 #define MXC_F_RPU_PTG_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SYS0ACN_POS))
1767 #define MXC_F_RPU_PTG_BUS0_SYS1ACN_POS 4
1768 #define MXC_F_RPU_PTG_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SYS1ACN_POS))
1770 #define MXC_F_RPU_PTG_BUS0_SDMADACN_POS 5
1771 #define MXC_F_RPU_PTG_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SDMADACN_POS))
1773 #define MXC_F_RPU_PTG_BUS0_SDMAIACN_POS 6
1774 #define MXC_F_RPU_PTG_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SDMAIACN_POS))
1776 #define MXC_F_RPU_PTG_BUS0_CRYPTOACN_POS 7
1777 #define MXC_F_RPU_PTG_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_CRYPTOACN_POS))
1779 #define MXC_F_RPU_PTG_BUS0_SDIOACN_POS 8
1780 #define MXC_F_RPU_PTG_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SDIOACN_POS))
1790 #define MXC_F_RPU_OWM_DMA0ACN_POS 0
1791 #define MXC_F_RPU_OWM_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_DMA0ACN_POS))
1793 #define MXC_F_RPU_OWM_DMA1ACN_POS 1
1794 #define MXC_F_RPU_OWM_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_DMA1ACN_POS))
1796 #define MXC_F_RPU_OWM_USBACN_POS 2
1797 #define MXC_F_RPU_OWM_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_USBACN_POS))
1799 #define MXC_F_RPU_OWM_SYS0ACN_POS 3
1800 #define MXC_F_RPU_OWM_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_SYS0ACN_POS))
1802 #define MXC_F_RPU_OWM_SYS1ACN_POS 4
1803 #define MXC_F_RPU_OWM_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_SYS1ACN_POS))
1805 #define MXC_F_RPU_OWM_SDMADACN_POS 5
1806 #define MXC_F_RPU_OWM_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_SDMADACN_POS))
1808 #define MXC_F_RPU_OWM_SDMAIACN_POS 6
1809 #define MXC_F_RPU_OWM_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_SDMAIACN_POS))
1811 #define MXC_F_RPU_OWM_CRYPTOACN_POS 7
1812 #define MXC_F_RPU_OWM_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_CRYPTOACN_POS))
1814 #define MXC_F_RPU_OWM_SDIOACN_POS 8
1815 #define MXC_F_RPU_OWM_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_OWM_SDIOACN_POS))
1825 #define MXC_F_RPU_SEMA_DMA0ACN_POS 0
1826 #define MXC_F_RPU_SEMA_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_DMA0ACN_POS))
1828 #define MXC_F_RPU_SEMA_DMA1ACN_POS 1
1829 #define MXC_F_RPU_SEMA_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_DMA1ACN_POS))
1831 #define MXC_F_RPU_SEMA_USBACN_POS 2
1832 #define MXC_F_RPU_SEMA_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_USBACN_POS))
1834 #define MXC_F_RPU_SEMA_SYS0ACN_POS 3
1835 #define MXC_F_RPU_SEMA_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SYS0ACN_POS))
1837 #define MXC_F_RPU_SEMA_SYS1ACN_POS 4
1838 #define MXC_F_RPU_SEMA_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SYS1ACN_POS))
1840 #define MXC_F_RPU_SEMA_SDMADACN_POS 5
1841 #define MXC_F_RPU_SEMA_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SDMADACN_POS))
1843 #define MXC_F_RPU_SEMA_SDMAIACN_POS 6
1844 #define MXC_F_RPU_SEMA_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SDMAIACN_POS))
1846 #define MXC_F_RPU_SEMA_CRYPTOACN_POS 7
1847 #define MXC_F_RPU_SEMA_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_CRYPTOACN_POS))
1849 #define MXC_F_RPU_SEMA_SDIOACN_POS 8
1850 #define MXC_F_RPU_SEMA_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SDIOACN_POS))
1860 #define MXC_F_RPU_UART0_DMA0ACN_POS 0
1861 #define MXC_F_RPU_UART0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_DMA0ACN_POS))
1863 #define MXC_F_RPU_UART0_DMA1ACN_POS 1
1864 #define MXC_F_RPU_UART0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_DMA1ACN_POS))
1866 #define MXC_F_RPU_UART0_USBACN_POS 2
1867 #define MXC_F_RPU_UART0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_USBACN_POS))
1869 #define MXC_F_RPU_UART0_SYS0ACN_POS 3
1870 #define MXC_F_RPU_UART0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SYS0ACN_POS))
1872 #define MXC_F_RPU_UART0_SYS1ACN_POS 4
1873 #define MXC_F_RPU_UART0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SYS1ACN_POS))
1875 #define MXC_F_RPU_UART0_SDMADACN_POS 5
1876 #define MXC_F_RPU_UART0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SDMADACN_POS))
1878 #define MXC_F_RPU_UART0_SDMAIACN_POS 6
1879 #define MXC_F_RPU_UART0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SDMAIACN_POS))
1881 #define MXC_F_RPU_UART0_CRYPTOACN_POS 7
1882 #define MXC_F_RPU_UART0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_CRYPTOACN_POS))
1884 #define MXC_F_RPU_UART0_SDIOACN_POS 8
1885 #define MXC_F_RPU_UART0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SDIOACN_POS))
1895 #define MXC_F_RPU_UART1_DMA0ACN_POS 0
1896 #define MXC_F_RPU_UART1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_DMA0ACN_POS))
1898 #define MXC_F_RPU_UART1_DMA1ACN_POS 1
1899 #define MXC_F_RPU_UART1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_DMA1ACN_POS))
1901 #define MXC_F_RPU_UART1_USBACN_POS 2
1902 #define MXC_F_RPU_UART1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_USBACN_POS))
1904 #define MXC_F_RPU_UART1_SYS0ACN_POS 3
1905 #define MXC_F_RPU_UART1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_SYS0ACN_POS))
1907 #define MXC_F_RPU_UART1_SYS1ACN_POS 4
1908 #define MXC_F_RPU_UART1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_SYS1ACN_POS))
1910 #define MXC_F_RPU_UART1_SDMADACN_POS 5
1911 #define MXC_F_RPU_UART1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_SDMADACN_POS))
1913 #define MXC_F_RPU_UART1_SDMAIACN_POS 6
1914 #define MXC_F_RPU_UART1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_SDMAIACN_POS))
1916 #define MXC_F_RPU_UART1_CRYPTOACN_POS 7
1917 #define MXC_F_RPU_UART1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_CRYPTOACN_POS))
1919 #define MXC_F_RPU_UART1_SDIOACN_POS 8
1920 #define MXC_F_RPU_UART1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_UART1_SDIOACN_POS))
1930 #define MXC_F_RPU_UART2_DMA0ACN_POS 0
1931 #define MXC_F_RPU_UART2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_DMA0ACN_POS))
1933 #define MXC_F_RPU_UART2_DMA1ACN_POS 1
1934 #define MXC_F_RPU_UART2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_DMA1ACN_POS))
1936 #define MXC_F_RPU_UART2_USBACN_POS 2
1937 #define MXC_F_RPU_UART2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_USBACN_POS))
1939 #define MXC_F_RPU_UART2_SYS0ACN_POS 3
1940 #define MXC_F_RPU_UART2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_SYS0ACN_POS))
1942 #define MXC_F_RPU_UART2_SYS1ACN_POS 4
1943 #define MXC_F_RPU_UART2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_SYS1ACN_POS))
1945 #define MXC_F_RPU_UART2_SDMADACN_POS 5
1946 #define MXC_F_RPU_UART2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_SDMADACN_POS))
1948 #define MXC_F_RPU_UART2_SDMAIACN_POS 6
1949 #define MXC_F_RPU_UART2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_SDMAIACN_POS))
1951 #define MXC_F_RPU_UART2_CRYPTOACN_POS 7
1952 #define MXC_F_RPU_UART2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_CRYPTOACN_POS))
1954 #define MXC_F_RPU_UART2_SDIOACN_POS 8
1955 #define MXC_F_RPU_UART2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_UART2_SDIOACN_POS))
1965 #define MXC_F_RPU_SPI1_DMA0ACN_POS 0
1966 #define MXC_F_RPU_SPI1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_DMA0ACN_POS))
1968 #define MXC_F_RPU_SPI1_DMA1ACN_POS 1
1969 #define MXC_F_RPU_SPI1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_DMA1ACN_POS))
1971 #define MXC_F_RPU_SPI1_USBACN_POS 2
1972 #define MXC_F_RPU_SPI1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_USBACN_POS))
1974 #define MXC_F_RPU_SPI1_SYS0ACN_POS 3
1975 #define MXC_F_RPU_SPI1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SYS0ACN_POS))
1977 #define MXC_F_RPU_SPI1_SYS1ACN_POS 4
1978 #define MXC_F_RPU_SPI1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SYS1ACN_POS))
1980 #define MXC_F_RPU_SPI1_SDMADACN_POS 5
1981 #define MXC_F_RPU_SPI1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SDMADACN_POS))
1983 #define MXC_F_RPU_SPI1_SDMAIACN_POS 6
1984 #define MXC_F_RPU_SPI1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SDMAIACN_POS))
1986 #define MXC_F_RPU_SPI1_CRYPTOACN_POS 7
1987 #define MXC_F_RPU_SPI1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_CRYPTOACN_POS))
1989 #define MXC_F_RPU_SPI1_SDIOACN_POS 8
1990 #define MXC_F_RPU_SPI1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SDIOACN_POS))
2000 #define MXC_F_RPU_SPI2_DMA0ACN_POS 0
2001 #define MXC_F_RPU_SPI2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_DMA0ACN_POS))
2003 #define MXC_F_RPU_SPI2_DMA1ACN_POS 1
2004 #define MXC_F_RPU_SPI2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_DMA1ACN_POS))
2006 #define MXC_F_RPU_SPI2_USBACN_POS 2
2007 #define MXC_F_RPU_SPI2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_USBACN_POS))
2009 #define MXC_F_RPU_SPI2_SYS0ACN_POS 3
2010 #define MXC_F_RPU_SPI2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SYS0ACN_POS))
2012 #define MXC_F_RPU_SPI2_SYS1ACN_POS 4
2013 #define MXC_F_RPU_SPI2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SYS1ACN_POS))
2015 #define MXC_F_RPU_SPI2_SDMADACN_POS 5
2016 #define MXC_F_RPU_SPI2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDMADACN_POS))
2018 #define MXC_F_RPU_SPI2_SDMAIACN_POS 6
2019 #define MXC_F_RPU_SPI2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDMAIACN_POS))
2021 #define MXC_F_RPU_SPI2_CRYPTOACN_POS 7
2022 #define MXC_F_RPU_SPI2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_CRYPTOACN_POS))
2024 #define MXC_F_RPU_SPI2_SDIOACN_POS 8
2025 #define MXC_F_RPU_SPI2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDIOACN_POS))
2035 #define MXC_F_RPU_AUDIO_DMA0ACN_POS 0
2036 #define MXC_F_RPU_AUDIO_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_DMA0ACN_POS))
2038 #define MXC_F_RPU_AUDIO_DMA1ACN_POS 1
2039 #define MXC_F_RPU_AUDIO_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_DMA1ACN_POS))
2041 #define MXC_F_RPU_AUDIO_USBACN_POS 2
2042 #define MXC_F_RPU_AUDIO_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_USBACN_POS))
2044 #define MXC_F_RPU_AUDIO_SYS0ACN_POS 3
2045 #define MXC_F_RPU_AUDIO_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_SYS0ACN_POS))
2047 #define MXC_F_RPU_AUDIO_SYS1ACN_POS 4
2048 #define MXC_F_RPU_AUDIO_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_SYS1ACN_POS))
2050 #define MXC_F_RPU_AUDIO_SDMADACN_POS 5
2051 #define MXC_F_RPU_AUDIO_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_SDMADACN_POS))
2053 #define MXC_F_RPU_AUDIO_SDMAIACN_POS 6
2054 #define MXC_F_RPU_AUDIO_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_SDMAIACN_POS))
2056 #define MXC_F_RPU_AUDIO_CRYPTOACN_POS 7
2057 #define MXC_F_RPU_AUDIO_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_CRYPTOACN_POS))
2059 #define MXC_F_RPU_AUDIO_SDIOACN_POS 8
2060 #define MXC_F_RPU_AUDIO_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_AUDIO_SDIOACN_POS))
2070 #define MXC_F_RPU_TRNG_DMA0ACN_POS 0
2071 #define MXC_F_RPU_TRNG_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_DMA0ACN_POS))
2073 #define MXC_F_RPU_TRNG_DMA1ACN_POS 1
2074 #define MXC_F_RPU_TRNG_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_DMA1ACN_POS))
2076 #define MXC_F_RPU_TRNG_USBACN_POS 2
2077 #define MXC_F_RPU_TRNG_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_USBACN_POS))
2079 #define MXC_F_RPU_TRNG_SYS0ACN_POS 3
2080 #define MXC_F_RPU_TRNG_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_SYS0ACN_POS))
2082 #define MXC_F_RPU_TRNG_SYS1ACN_POS 4
2083 #define MXC_F_RPU_TRNG_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_SYS1ACN_POS))
2085 #define MXC_F_RPU_TRNG_SDMADACN_POS 5
2086 #define MXC_F_RPU_TRNG_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_SDMADACN_POS))
2088 #define MXC_F_RPU_TRNG_SDMAIACN_POS 6
2089 #define MXC_F_RPU_TRNG_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_SDMAIACN_POS))
2091 #define MXC_F_RPU_TRNG_CRYPTOACN_POS 7
2092 #define MXC_F_RPU_TRNG_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_CRYPTOACN_POS))
2094 #define MXC_F_RPU_TRNG_SDIOACN_POS 8
2095 #define MXC_F_RPU_TRNG_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TRNG_SDIOACN_POS))
2105 #define MXC_F_RPU_BTLE_DMA0ACN_POS 0
2106 #define MXC_F_RPU_BTLE_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_DMA0ACN_POS))
2108 #define MXC_F_RPU_BTLE_DMA1ACN_POS 1
2109 #define MXC_F_RPU_BTLE_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_DMA1ACN_POS))
2111 #define MXC_F_RPU_BTLE_USBACN_POS 2
2112 #define MXC_F_RPU_BTLE_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_USBACN_POS))
2114 #define MXC_F_RPU_BTLE_SYS0ACN_POS 3
2115 #define MXC_F_RPU_BTLE_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_SYS0ACN_POS))
2117 #define MXC_F_RPU_BTLE_SYS1ACN_POS 4
2118 #define MXC_F_RPU_BTLE_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_SYS1ACN_POS))
2120 #define MXC_F_RPU_BTLE_SDMADACN_POS 5
2121 #define MXC_F_RPU_BTLE_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_SDMADACN_POS))
2123 #define MXC_F_RPU_BTLE_SDMAIACN_POS 6
2124 #define MXC_F_RPU_BTLE_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_SDMAIACN_POS))
2126 #define MXC_F_RPU_BTLE_CRYPTOACN_POS 7
2127 #define MXC_F_RPU_BTLE_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_CRYPTOACN_POS))
2129 #define MXC_F_RPU_BTLE_SDIOACN_POS 8
2130 #define MXC_F_RPU_BTLE_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_BTLE_SDIOACN_POS))
2140 #define MXC_F_RPU_USBHS_DMA0ACNR_POS 0
2141 #define MXC_F_RPU_USBHS_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_DMA0ACNR_POS))
2143 #define MXC_F_RPU_USBHS_DMA0ACNW_POS 1
2144 #define MXC_F_RPU_USBHS_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_DMA0ACNW_POS))
2146 #define MXC_F_RPU_USBHS_DMA1ACNR_POS 2
2147 #define MXC_F_RPU_USBHS_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_DMA1ACNR_POS))
2149 #define MXC_F_RPU_USBHS_DMA1ACNW_POS 3
2150 #define MXC_F_RPU_USBHS_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_DMA1ACNW_POS))
2152 #define MXC_F_RPU_USBHS_USBACNR_POS 4
2153 #define MXC_F_RPU_USBHS_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_USBACNR_POS))
2155 #define MXC_F_RPU_USBHS_USBACNW_POS 5
2156 #define MXC_F_RPU_USBHS_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_USBACNW_POS))
2158 #define MXC_F_RPU_USBHS_SYS0ACNR_POS 6
2159 #define MXC_F_RPU_USBHS_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SYS0ACNR_POS))
2161 #define MXC_F_RPU_USBHS_SYS0ACNW_POS 7
2162 #define MXC_F_RPU_USBHS_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SYS0ACNW_POS))
2164 #define MXC_F_RPU_USBHS_SYS1ACNR_POS 8
2165 #define MXC_F_RPU_USBHS_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SYS1ACNR_POS))
2167 #define MXC_F_RPU_USBHS_SYS1ACNW_POS 9
2168 #define MXC_F_RPU_USBHS_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SYS1ACNW_POS))
2170 #define MXC_F_RPU_USBHS_SDMADACNR_POS 10
2171 #define MXC_F_RPU_USBHS_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SDMADACNR_POS))
2173 #define MXC_F_RPU_USBHS_SDMADACNW_POS 11
2174 #define MXC_F_RPU_USBHS_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SDMADACNW_POS))
2176 #define MXC_F_RPU_USBHS_SDMAIACNR_POS 12
2177 #define MXC_F_RPU_USBHS_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SDMAIACNR_POS))
2179 #define MXC_F_RPU_USBHS_SDMAIACNW_POS 13
2180 #define MXC_F_RPU_USBHS_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SDMAIACNW_POS))
2182 #define MXC_F_RPU_USBHS_CRYPTOACNR_POS 14
2183 #define MXC_F_RPU_USBHS_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_CRYPTOACNR_POS))
2185 #define MXC_F_RPU_USBHS_CRYPTOACNW_POS 15
2186 #define MXC_F_RPU_USBHS_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_CRYPTOACNW_POS))
2188 #define MXC_F_RPU_USBHS_SDIOACNR_POS 16
2189 #define MXC_F_RPU_USBHS_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SDIOACNR_POS))
2191 #define MXC_F_RPU_USBHS_SDIOACNW_POS 17
2192 #define MXC_F_RPU_USBHS_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_USBHS_SDIOACNW_POS))
2202 #define MXC_F_RPU_SDIO_DMA0ACNR_POS 0
2203 #define MXC_F_RPU_SDIO_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_DMA0ACNR_POS))
2205 #define MXC_F_RPU_SDIO_DMA0ACNW_POS 1
2206 #define MXC_F_RPU_SDIO_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_DMA0ACNW_POS))
2208 #define MXC_F_RPU_SDIO_DMA1ACNR_POS 2
2209 #define MXC_F_RPU_SDIO_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_DMA1ACNR_POS))
2211 #define MXC_F_RPU_SDIO_DMA1ACNW_POS 3
2212 #define MXC_F_RPU_SDIO_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_DMA1ACNW_POS))
2214 #define MXC_F_RPU_SDIO_USBACNR_POS 4
2215 #define MXC_F_RPU_SDIO_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_USBACNR_POS))
2217 #define MXC_F_RPU_SDIO_USBACNW_POS 5
2218 #define MXC_F_RPU_SDIO_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_USBACNW_POS))
2220 #define MXC_F_RPU_SDIO_SYS0ACNR_POS 6
2221 #define MXC_F_RPU_SDIO_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SYS0ACNR_POS))
2223 #define MXC_F_RPU_SDIO_SYS0ACNW_POS 7
2224 #define MXC_F_RPU_SDIO_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SYS0ACNW_POS))
2226 #define MXC_F_RPU_SDIO_SYS1ACNR_POS 8
2227 #define MXC_F_RPU_SDIO_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SYS1ACNR_POS))
2229 #define MXC_F_RPU_SDIO_SYS1ACNW_POS 9
2230 #define MXC_F_RPU_SDIO_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SYS1ACNW_POS))
2232 #define MXC_F_RPU_SDIO_SDMADACNR_POS 10
2233 #define MXC_F_RPU_SDIO_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SDMADACNR_POS))
2235 #define MXC_F_RPU_SDIO_SDMADACNW_POS 11
2236 #define MXC_F_RPU_SDIO_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SDMADACNW_POS))
2238 #define MXC_F_RPU_SDIO_SDMAIACNR_POS 12
2239 #define MXC_F_RPU_SDIO_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SDMAIACNR_POS))
2241 #define MXC_F_RPU_SDIO_SDMAIACNW_POS 13
2242 #define MXC_F_RPU_SDIO_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SDMAIACNW_POS))
2244 #define MXC_F_RPU_SDIO_CRYPTOACNR_POS 14
2245 #define MXC_F_RPU_SDIO_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_CRYPTOACNR_POS))
2247 #define MXC_F_RPU_SDIO_CRYPTOACNW_POS 15
2248 #define MXC_F_RPU_SDIO_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_CRYPTOACNW_POS))
2250 #define MXC_F_RPU_SDIO_SDIOACNR_POS 16
2251 #define MXC_F_RPU_SDIO_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SDIOACNR_POS))
2253 #define MXC_F_RPU_SDIO_SDIOACNW_POS 17
2254 #define MXC_F_RPU_SDIO_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SDIO_SDIOACNW_POS))
2264 #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS 0
2265 #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS))
2267 #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS 1
2268 #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS))
2270 #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS 2
2271 #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS))
2273 #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS 3
2274 #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS))
2276 #define MXC_F_RPU_SPIXM_FIFO_USBACNR_POS 4
2277 #define MXC_F_RPU_SPIXM_FIFO_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_USBACNR_POS))
2279 #define MXC_F_RPU_SPIXM_FIFO_USBACNW_POS 5
2280 #define MXC_F_RPU_SPIXM_FIFO_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_USBACNW_POS))
2282 #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS 6
2283 #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS))
2285 #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS 7
2286 #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS))
2288 #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS 8
2289 #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS))
2291 #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS 9
2292 #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS))
2294 #define MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS 10
2295 #define MXC_F_RPU_SPIXM_FIFO_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS))
2297 #define MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS 11
2298 #define MXC_F_RPU_SPIXM_FIFO_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS))
2300 #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS 12
2301 #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS))
2303 #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS 13
2304 #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS))
2306 #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS 14
2307 #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS))
2309 #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS 15
2310 #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS))
2312 #define MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS 16
2313 #define MXC_F_RPU_SPIXM_FIFO_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS))
2315 #define MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS 17
2316 #define MXC_F_RPU_SPIXM_FIFO_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS))
2326 #define MXC_F_RPU_SPI0_DMA0ACNR_POS 0
2327 #define MXC_F_RPU_SPI0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNR_POS))
2329 #define MXC_F_RPU_SPI0_DMA0ACNW_POS 1
2330 #define MXC_F_RPU_SPI0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNW_POS))
2332 #define MXC_F_RPU_SPI0_DMA1ACNR_POS 2
2333 #define MXC_F_RPU_SPI0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNR_POS))
2335 #define MXC_F_RPU_SPI0_DMA1ACNW_POS 3
2336 #define MXC_F_RPU_SPI0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNW_POS))
2338 #define MXC_F_RPU_SPI0_USBACNR_POS 4
2339 #define MXC_F_RPU_SPI0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNR_POS))
2341 #define MXC_F_RPU_SPI0_USBACNW_POS 5
2342 #define MXC_F_RPU_SPI0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNW_POS))
2344 #define MXC_F_RPU_SPI0_SYS0ACNR_POS 6
2345 #define MXC_F_RPU_SPI0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNR_POS))
2347 #define MXC_F_RPU_SPI0_SYS0ACNW_POS 7
2348 #define MXC_F_RPU_SPI0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNW_POS))
2350 #define MXC_F_RPU_SPI0_SYS1ACNR_POS 8
2351 #define MXC_F_RPU_SPI0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNR_POS))
2353 #define MXC_F_RPU_SPI0_SYS1ACNW_POS 9
2354 #define MXC_F_RPU_SPI0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNW_POS))
2356 #define MXC_F_RPU_SPI0_SDMADACNR_POS 10
2357 #define MXC_F_RPU_SPI0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNR_POS))
2359 #define MXC_F_RPU_SPI0_SDMADACNW_POS 11
2360 #define MXC_F_RPU_SPI0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNW_POS))
2362 #define MXC_F_RPU_SPI0_SDMAIACNR_POS 12
2363 #define MXC_F_RPU_SPI0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNR_POS))
2365 #define MXC_F_RPU_SPI0_SDMAIACNW_POS 13
2366 #define MXC_F_RPU_SPI0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNW_POS))
2368 #define MXC_F_RPU_SPI0_CRYPTOACNR_POS 14
2369 #define MXC_F_RPU_SPI0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNR_POS))
2371 #define MXC_F_RPU_SPI0_CRYPTOACNW_POS 15
2372 #define MXC_F_RPU_SPI0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNW_POS))
2374 #define MXC_F_RPU_SPI0_SDIOACNR_POS 16
2375 #define MXC_F_RPU_SPI0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNR_POS))
2377 #define MXC_F_RPU_SPI0_SDIOACNW_POS 17
2378 #define MXC_F_RPU_SPI0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNW_POS))
2388 #define MXC_F_RPU_SYSRAM0_DMA0ACNR_POS 0
2389 #define MXC_F_RPU_SYSRAM0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA0ACNR_POS))
2391 #define MXC_F_RPU_SYSRAM0_DMA0ACNW_POS 1
2392 #define MXC_F_RPU_SYSRAM0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA0ACNW_POS))
2394 #define MXC_F_RPU_SYSRAM0_DMA1ACNR_POS 2
2395 #define MXC_F_RPU_SYSRAM0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA1ACNR_POS))
2397 #define MXC_F_RPU_SYSRAM0_DMA1ACNW_POS 3
2398 #define MXC_F_RPU_SYSRAM0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA1ACNW_POS))
2400 #define MXC_F_RPU_SYSRAM0_USBACNR_POS 4
2401 #define MXC_F_RPU_SYSRAM0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_USBACNR_POS))
2403 #define MXC_F_RPU_SYSRAM0_USBACNW_POS 5
2404 #define MXC_F_RPU_SYSRAM0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_USBACNW_POS))
2406 #define MXC_F_RPU_SYSRAM0_SYS0ACNR_POS 6
2407 #define MXC_F_RPU_SYSRAM0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS0ACNR_POS))
2409 #define MXC_F_RPU_SYSRAM0_SYS0ACNW_POS 7
2410 #define MXC_F_RPU_SYSRAM0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS0ACNW_POS))
2412 #define MXC_F_RPU_SYSRAM0_SYS1ACNR_POS 8
2413 #define MXC_F_RPU_SYSRAM0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS1ACNR_POS))
2415 #define MXC_F_RPU_SYSRAM0_SYS1ACNW_POS 9
2416 #define MXC_F_RPU_SYSRAM0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS1ACNW_POS))
2418 #define MXC_F_RPU_SYSRAM0_SDMADACNR_POS 10
2419 #define MXC_F_RPU_SYSRAM0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMADACNR_POS))
2421 #define MXC_F_RPU_SYSRAM0_SDMADACNW_POS 11
2422 #define MXC_F_RPU_SYSRAM0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMADACNW_POS))
2424 #define MXC_F_RPU_SYSRAM0_SDMAIACNR_POS 12
2425 #define MXC_F_RPU_SYSRAM0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMAIACNR_POS))
2427 #define MXC_F_RPU_SYSRAM0_SDMAIACNW_POS 13
2428 #define MXC_F_RPU_SYSRAM0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMAIACNW_POS))
2430 #define MXC_F_RPU_SYSRAM0_CRYPTOACNR_POS 14
2431 #define MXC_F_RPU_SYSRAM0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_CRYPTOACNR_POS))
2433 #define MXC_F_RPU_SYSRAM0_CRYPTOACNW_POS 15
2434 #define MXC_F_RPU_SYSRAM0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_CRYPTOACNW_POS))
2436 #define MXC_F_RPU_SYSRAM0_SDIOACNR_POS 16
2437 #define MXC_F_RPU_SYSRAM0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDIOACNR_POS))
2439 #define MXC_F_RPU_SYSRAM0_SDIOACNW_POS 17
2440 #define MXC_F_RPU_SYSRAM0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDIOACNW_POS))
2450 #define MXC_F_RPU_SYSRAM1_DMA0ACNR_POS 0
2451 #define MXC_F_RPU_SYSRAM1_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA0ACNR_POS))
2453 #define MXC_F_RPU_SYSRAM1_DMA0ACNW_POS 1
2454 #define MXC_F_RPU_SYSRAM1_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA0ACNW_POS))
2456 #define MXC_F_RPU_SYSRAM1_DMA1ACNR_POS 2
2457 #define MXC_F_RPU_SYSRAM1_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA1ACNR_POS))
2459 #define MXC_F_RPU_SYSRAM1_DMA1ACNW_POS 3
2460 #define MXC_F_RPU_SYSRAM1_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA1ACNW_POS))
2462 #define MXC_F_RPU_SYSRAM1_USBACNR_POS 4
2463 #define MXC_F_RPU_SYSRAM1_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_USBACNR_POS))
2465 #define MXC_F_RPU_SYSRAM1_USBACNW_POS 5
2466 #define MXC_F_RPU_SYSRAM1_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_USBACNW_POS))
2468 #define MXC_F_RPU_SYSRAM1_SYS0ACNR_POS 6
2469 #define MXC_F_RPU_SYSRAM1_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS0ACNR_POS))
2471 #define MXC_F_RPU_SYSRAM1_SYS0ACNW_POS 7
2472 #define MXC_F_RPU_SYSRAM1_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS0ACNW_POS))
2474 #define MXC_F_RPU_SYSRAM1_SYS1ACNR_POS 8
2475 #define MXC_F_RPU_SYSRAM1_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS1ACNR_POS))
2477 #define MXC_F_RPU_SYSRAM1_SYS1ACNW_POS 9
2478 #define MXC_F_RPU_SYSRAM1_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS1ACNW_POS))
2480 #define MXC_F_RPU_SYSRAM1_SDMADACNR_POS 10
2481 #define MXC_F_RPU_SYSRAM1_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMADACNR_POS))
2483 #define MXC_F_RPU_SYSRAM1_SDMADACNW_POS 11
2484 #define MXC_F_RPU_SYSRAM1_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMADACNW_POS))
2486 #define MXC_F_RPU_SYSRAM1_SDMAIACNR_POS 12
2487 #define MXC_F_RPU_SYSRAM1_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMAIACNR_POS))
2489 #define MXC_F_RPU_SYSRAM1_SDMAIACNW_POS 13
2490 #define MXC_F_RPU_SYSRAM1_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMAIACNW_POS))
2492 #define MXC_F_RPU_SYSRAM1_CRYPTOACNR_POS 14
2493 #define MXC_F_RPU_SYSRAM1_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_CRYPTOACNR_POS))
2495 #define MXC_F_RPU_SYSRAM1_CRYPTOACNW_POS 15
2496 #define MXC_F_RPU_SYSRAM1_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_CRYPTOACNW_POS))
2498 #define MXC_F_RPU_SYSRAM1_SDIOACNR_POS 16
2499 #define MXC_F_RPU_SYSRAM1_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDIOACNR_POS))
2501 #define MXC_F_RPU_SYSRAM1_SDIOACNW_POS 17
2502 #define MXC_F_RPU_SYSRAM1_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDIOACNW_POS))
2512 #define MXC_F_RPU_SYSRAM2_DMA0ACNR_POS 0
2513 #define MXC_F_RPU_SYSRAM2_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA0ACNR_POS))
2515 #define MXC_F_RPU_SYSRAM2_DMA0ACNW_POS 1
2516 #define MXC_F_RPU_SYSRAM2_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA0ACNW_POS))
2518 #define MXC_F_RPU_SYSRAM2_DMA1ACNR_POS 2
2519 #define MXC_F_RPU_SYSRAM2_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA1ACNR_POS))
2521 #define MXC_F_RPU_SYSRAM2_DMA1ACNW_POS 3
2522 #define MXC_F_RPU_SYSRAM2_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA1ACNW_POS))
2524 #define MXC_F_RPU_SYSRAM2_USBACNR_POS 4
2525 #define MXC_F_RPU_SYSRAM2_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_USBACNR_POS))
2527 #define MXC_F_RPU_SYSRAM2_USBACNW_POS 5
2528 #define MXC_F_RPU_SYSRAM2_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_USBACNW_POS))
2530 #define MXC_F_RPU_SYSRAM2_SYS0ACNR_POS 6
2531 #define MXC_F_RPU_SYSRAM2_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS0ACNR_POS))
2533 #define MXC_F_RPU_SYSRAM2_SYS0ACNW_POS 7
2534 #define MXC_F_RPU_SYSRAM2_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS0ACNW_POS))
2536 #define MXC_F_RPU_SYSRAM2_SYS1ACNR_POS 8
2537 #define MXC_F_RPU_SYSRAM2_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS1ACNR_POS))
2539 #define MXC_F_RPU_SYSRAM2_SYS1ACNW_POS 9
2540 #define MXC_F_RPU_SYSRAM2_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS1ACNW_POS))
2542 #define MXC_F_RPU_SYSRAM2_SDMADACNR_POS 10
2543 #define MXC_F_RPU_SYSRAM2_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMADACNR_POS))
2545 #define MXC_F_RPU_SYSRAM2_SDMADACNW_POS 11
2546 #define MXC_F_RPU_SYSRAM2_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMADACNW_POS))
2548 #define MXC_F_RPU_SYSRAM2_SDMAIACNR_POS 12
2549 #define MXC_F_RPU_SYSRAM2_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMAIACNR_POS))
2551 #define MXC_F_RPU_SYSRAM2_SDMAIACNW_POS 13
2552 #define MXC_F_RPU_SYSRAM2_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMAIACNW_POS))
2554 #define MXC_F_RPU_SYSRAM2_CRYPTOACNR_POS 14
2555 #define MXC_F_RPU_SYSRAM2_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_CRYPTOACNR_POS))
2557 #define MXC_F_RPU_SYSRAM2_CRYPTOACNW_POS 15
2558 #define MXC_F_RPU_SYSRAM2_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_CRYPTOACNW_POS))
2560 #define MXC_F_RPU_SYSRAM2_SDIOACNR_POS 16
2561 #define MXC_F_RPU_SYSRAM2_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDIOACNR_POS))
2563 #define MXC_F_RPU_SYSRAM2_SDIOACNW_POS 17
2564 #define MXC_F_RPU_SYSRAM2_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDIOACNW_POS))
2574 #define MXC_F_RPU_SYSRAM3_DMA0ACNR_POS 0
2575 #define MXC_F_RPU_SYSRAM3_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA0ACNR_POS))
2577 #define MXC_F_RPU_SYSRAM3_DMA0ACNW_POS 1
2578 #define MXC_F_RPU_SYSRAM3_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA0ACNW_POS))
2580 #define MXC_F_RPU_SYSRAM3_DMA1ACNR_POS 2
2581 #define MXC_F_RPU_SYSRAM3_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA1ACNR_POS))
2583 #define MXC_F_RPU_SYSRAM3_DMA1ACNW_POS 3
2584 #define MXC_F_RPU_SYSRAM3_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA1ACNW_POS))
2586 #define MXC_F_RPU_SYSRAM3_USBACNR_POS 4
2587 #define MXC_F_RPU_SYSRAM3_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_USBACNR_POS))
2589 #define MXC_F_RPU_SYSRAM3_USBACNW_POS 5
2590 #define MXC_F_RPU_SYSRAM3_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_USBACNW_POS))
2592 #define MXC_F_RPU_SYSRAM3_SYS0ACNR_POS 6
2593 #define MXC_F_RPU_SYSRAM3_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS0ACNR_POS))
2595 #define MXC_F_RPU_SYSRAM3_SYS0ACNW_POS 7
2596 #define MXC_F_RPU_SYSRAM3_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS0ACNW_POS))
2598 #define MXC_F_RPU_SYSRAM3_SYS1ACNR_POS 8
2599 #define MXC_F_RPU_SYSRAM3_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS1ACNR_POS))
2601 #define MXC_F_RPU_SYSRAM3_SYS1ACNW_POS 9
2602 #define MXC_F_RPU_SYSRAM3_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS1ACNW_POS))
2604 #define MXC_F_RPU_SYSRAM3_SDMADACNR_POS 10
2605 #define MXC_F_RPU_SYSRAM3_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMADACNR_POS))
2607 #define MXC_F_RPU_SYSRAM3_SDMADACNW_POS 11
2608 #define MXC_F_RPU_SYSRAM3_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMADACNW_POS))
2610 #define MXC_F_RPU_SYSRAM3_SDMAIACNR_POS 12
2611 #define MXC_F_RPU_SYSRAM3_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMAIACNR_POS))
2613 #define MXC_F_RPU_SYSRAM3_SDMAIACNW_POS 13
2614 #define MXC_F_RPU_SYSRAM3_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMAIACNW_POS))
2616 #define MXC_F_RPU_SYSRAM3_CRYPTOACNR_POS 14
2617 #define MXC_F_RPU_SYSRAM3_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_CRYPTOACNR_POS))
2619 #define MXC_F_RPU_SYSRAM3_CRYPTOACNW_POS 15
2620 #define MXC_F_RPU_SYSRAM3_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_CRYPTOACNW_POS))
2622 #define MXC_F_RPU_SYSRAM3_SDIOACNR_POS 16
2623 #define MXC_F_RPU_SYSRAM3_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDIOACNR_POS))
2625 #define MXC_F_RPU_SYSRAM3_SDIOACNW_POS 17
2626 #define MXC_F_RPU_SYSRAM3_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDIOACNW_POS))
2636 #define MXC_F_RPU_SYSRAM4_DMA0ACNR_POS 0
2637 #define MXC_F_RPU_SYSRAM4_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA0ACNR_POS))
2639 #define MXC_F_RPU_SYSRAM4_DMA0ACNW_POS 1
2640 #define MXC_F_RPU_SYSRAM4_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA0ACNW_POS))
2642 #define MXC_F_RPU_SYSRAM4_DMA1ACNR_POS 2
2643 #define MXC_F_RPU_SYSRAM4_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA1ACNR_POS))
2645 #define MXC_F_RPU_SYSRAM4_DMA1ACNW_POS 3
2646 #define MXC_F_RPU_SYSRAM4_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA1ACNW_POS))
2648 #define MXC_F_RPU_SYSRAM4_USBACNR_POS 4
2649 #define MXC_F_RPU_SYSRAM4_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_USBACNR_POS))
2651 #define MXC_F_RPU_SYSRAM4_USBACNW_POS 5
2652 #define MXC_F_RPU_SYSRAM4_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_USBACNW_POS))
2654 #define MXC_F_RPU_SYSRAM4_SYS0ACNR_POS 6
2655 #define MXC_F_RPU_SYSRAM4_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS0ACNR_POS))
2657 #define MXC_F_RPU_SYSRAM4_SYS0ACNW_POS 7
2658 #define MXC_F_RPU_SYSRAM4_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS0ACNW_POS))
2660 #define MXC_F_RPU_SYSRAM4_SYS1ACNR_POS 8
2661 #define MXC_F_RPU_SYSRAM4_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS1ACNR_POS))
2663 #define MXC_F_RPU_SYSRAM4_SYS1ACNW_POS 9
2664 #define MXC_F_RPU_SYSRAM4_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS1ACNW_POS))
2666 #define MXC_F_RPU_SYSRAM4_SDMADACNR_POS 10
2667 #define MXC_F_RPU_SYSRAM4_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMADACNR_POS))
2669 #define MXC_F_RPU_SYSRAM4_SDMADACNW_POS 11
2670 #define MXC_F_RPU_SYSRAM4_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMADACNW_POS))
2672 #define MXC_F_RPU_SYSRAM4_SDMAIACNR_POS 12
2673 #define MXC_F_RPU_SYSRAM4_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMAIACNR_POS))
2675 #define MXC_F_RPU_SYSRAM4_SDMAIACNW_POS 13
2676 #define MXC_F_RPU_SYSRAM4_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMAIACNW_POS))
2678 #define MXC_F_RPU_SYSRAM4_CRYPTOACNR_POS 14
2679 #define MXC_F_RPU_SYSRAM4_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_CRYPTOACNR_POS))
2681 #define MXC_F_RPU_SYSRAM4_CRYPTOACNW_POS 15
2682 #define MXC_F_RPU_SYSRAM4_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_CRYPTOACNW_POS))
2684 #define MXC_F_RPU_SYSRAM4_SDIOACNR_POS 16
2685 #define MXC_F_RPU_SYSRAM4_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDIOACNR_POS))
2687 #define MXC_F_RPU_SYSRAM4_SDIOACNW_POS 17
2688 #define MXC_F_RPU_SYSRAM4_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDIOACNW_POS))
2698 #define MXC_F_RPU_SYSRAM5_DMA0ACNR_POS 0
2699 #define MXC_F_RPU_SYSRAM5_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA0ACNR_POS))
2701 #define MXC_F_RPU_SYSRAM5_DMA0ACNW_POS 1
2702 #define MXC_F_RPU_SYSRAM5_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA0ACNW_POS))
2704 #define MXC_F_RPU_SYSRAM5_DMA1ACNR_POS 2
2705 #define MXC_F_RPU_SYSRAM5_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA1ACNR_POS))
2707 #define MXC_F_RPU_SYSRAM5_DMA1ACNW_POS 3
2708 #define MXC_F_RPU_SYSRAM5_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA1ACNW_POS))
2710 #define MXC_F_RPU_SYSRAM5_USBACNR_POS 4
2711 #define MXC_F_RPU_SYSRAM5_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_USBACNR_POS))
2713 #define MXC_F_RPU_SYSRAM5_USBACNW_POS 5
2714 #define MXC_F_RPU_SYSRAM5_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_USBACNW_POS))
2716 #define MXC_F_RPU_SYSRAM5_SYS0ACNR_POS 6
2717 #define MXC_F_RPU_SYSRAM5_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS0ACNR_POS))
2719 #define MXC_F_RPU_SYSRAM5_SYS0ACNW_POS 7
2720 #define MXC_F_RPU_SYSRAM5_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS0ACNW_POS))
2722 #define MXC_F_RPU_SYSRAM5_SYS1ACNR_POS 8
2723 #define MXC_F_RPU_SYSRAM5_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS1ACNR_POS))
2725 #define MXC_F_RPU_SYSRAM5_SYS1ACNW_POS 9
2726 #define MXC_F_RPU_SYSRAM5_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS1ACNW_POS))
2728 #define MXC_F_RPU_SYSRAM5_SDMADACNR_POS 10
2729 #define MXC_F_RPU_SYSRAM5_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMADACNR_POS))
2731 #define MXC_F_RPU_SYSRAM5_SDMADACNW_POS 11
2732 #define MXC_F_RPU_SYSRAM5_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMADACNW_POS))
2734 #define MXC_F_RPU_SYSRAM5_SDMAIACNR_POS 12
2735 #define MXC_F_RPU_SYSRAM5_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMAIACNR_POS))
2737 #define MXC_F_RPU_SYSRAM5_SDMAIACNW_POS 13
2738 #define MXC_F_RPU_SYSRAM5_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMAIACNW_POS))
2740 #define MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS 14
2741 #define MXC_F_RPU_SYSRAM5_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS))
2743 #define MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS 15
2744 #define MXC_F_RPU_SYSRAM5_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS))
2746 #define MXC_F_RPU_SYSRAM5_SDIOACNR_POS 16
2747 #define MXC_F_RPU_SYSRAM5_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDIOACNR_POS))
2749 #define MXC_F_RPU_SYSRAM5_SDIOACNW_POS 17
2750 #define MXC_F_RPU_SYSRAM5_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDIOACNW_POS))
2760 #define MXC_F_RPU_SYSRAM6_DMA0ACNR_POS 0
2761 #define MXC_F_RPU_SYSRAM6_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA0ACNR_POS))
2763 #define MXC_F_RPU_SYSRAM6_DMA0ACNW_POS 1
2764 #define MXC_F_RPU_SYSRAM6_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA0ACNW_POS))
2766 #define MXC_F_RPU_SYSRAM6_DMA1ACNR_POS 2
2767 #define MXC_F_RPU_SYSRAM6_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA1ACNR_POS))
2769 #define MXC_F_RPU_SYSRAM6_DMA1ACNW_POS 3
2770 #define MXC_F_RPU_SYSRAM6_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA1ACNW_POS))
2772 #define MXC_F_RPU_SYSRAM6_USBACNR_POS 4
2773 #define MXC_F_RPU_SYSRAM6_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_USBACNR_POS))
2775 #define MXC_F_RPU_SYSRAM6_USBACNW_POS 5
2776 #define MXC_F_RPU_SYSRAM6_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_USBACNW_POS))
2778 #define MXC_F_RPU_SYSRAM6_SYS0ACNR_POS 6
2779 #define MXC_F_RPU_SYSRAM6_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS0ACNR_POS))
2781 #define MXC_F_RPU_SYSRAM6_SYS0ACNW_POS 7
2782 #define MXC_F_RPU_SYSRAM6_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS0ACNW_POS))
2784 #define MXC_F_RPU_SYSRAM6_SYS1ACNR_POS 8
2785 #define MXC_F_RPU_SYSRAM6_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS1ACNR_POS))
2787 #define MXC_F_RPU_SYSRAM6_SYS1ACNW_POS 9
2788 #define MXC_F_RPU_SYSRAM6_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS1ACNW_POS))
2790 #define MXC_F_RPU_SYSRAM6_SDMADACNR_POS 10
2791 #define MXC_F_RPU_SYSRAM6_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMADACNR_POS))
2793 #define MXC_F_RPU_SYSRAM6_SDMADACNW_POS 11
2794 #define MXC_F_RPU_SYSRAM6_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMADACNW_POS))
2796 #define MXC_F_RPU_SYSRAM6_SDMAIACNR_POS 12
2797 #define MXC_F_RPU_SYSRAM6_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMAIACNR_POS))
2799 #define MXC_F_RPU_SYSRAM6_SDMAIACNW_POS 13
2800 #define MXC_F_RPU_SYSRAM6_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMAIACNW_POS))
2802 #define MXC_F_RPU_SYSRAM6_CRYPTOACNR_POS 14
2803 #define MXC_F_RPU_SYSRAM6_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_CRYPTOACNR_POS))
2805 #define MXC_F_RPU_SYSRAM6_CRYPTOACNW_POS 15
2806 #define MXC_F_RPU_SYSRAM6_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_CRYPTOACNW_POS))
2808 #define MXC_F_RPU_SYSRAM6_SDIOACNR_POS 16
2809 #define MXC_F_RPU_SYSRAM6_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDIOACNR_POS))
2811 #define MXC_F_RPU_SYSRAM6_SDIOACNW_POS 17
2812 #define MXC_F_RPU_SYSRAM6_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDIOACNW_POS))
__IO uint32_t wut
Definition: rpu_regs.h:105
__IO uint32_t sysram0
Definition: rpu_regs.h:191
__IO uint32_t sdhcctrl
Definition: rpu_regs.h:157
__IO uint32_t wdt2
Definition: rpu_regs.h:96
__IO uint32_t i2c1_bus0
Definition: rpu_regs.h:131
__IO uint32_t trng
Definition: rpu_regs.h:179
__IO uint32_t sdio
Definition: rpu_regs.h:185
__IO uint32_t spixfc
Definition: rpu_regs.h:137
__IO uint32_t icc1
Definition: rpu_regs.h:145
__IO uint32_t wdt0
Definition: rpu_regs.h:94
__IO uint32_t gcr
Definition: rpu_regs.h:89
__IO uint32_t flc0
Definition: rpu_regs.h:141
__IO uint32_t mcr
Definition: rpu_regs.h:107
__IO uint32_t audio
Definition: rpu_regs.h:177
__IO uint32_t usbhs
Definition: rpu_regs.h:183
__IO uint32_t dma1
Definition: rpu_regs.h:153
__IO uint32_t uart2
Definition: rpu_regs.h:171
__IO uint32_t sema
Definition: rpu_regs.h:165
__IO uint32_t i2c2_bus0
Definition: rpu_regs.h:133
__IO uint32_t sdma
Definition: rpu_regs.h:155
__IO uint32_t spi0
Definition: rpu_regs.h:189
__IO uint32_t tmr5
Definition: rpu_regs.h:123
__IO uint32_t pwrseq
Definition: rpu_regs.h:106
__IO uint32_t htimer0
Definition: rpu_regs.h:125
__IO uint32_t gpio1
Definition: rpu_regs.h:111
__IO uint32_t spixm_fifo
Definition: rpu_regs.h:187
__IO uint32_t tmr2
Definition: rpu_regs.h:117
__IO uint32_t sysram6
Definition: rpu_regs.h:203
__IO uint32_t rtc
Definition: rpu_regs.h:104
__IO uint32_t btle
Definition: rpu_regs.h:181
__IO uint32_t dma0
Definition: rpu_regs.h:139
__IO uint32_t sysram5
Definition: rpu_regs.h:201
__IO uint32_t htimer1
Definition: rpu_regs.h:127
__IO uint32_t gpio0
Definition: rpu_regs.h:109
__IO uint32_t sysram4
Definition: rpu_regs.h:199
__IO uint32_t sysram2
Definition: rpu_regs.h:195
__IO uint32_t spi1
Definition: rpu_regs.h:173
__IO uint32_t spixfm
Definition: rpu_regs.h:135
__IO uint32_t ptg_bus0
Definition: rpu_regs.h:161
__IO uint32_t adc
Definition: rpu_regs.h:151
__IO uint32_t wdt1
Definition: rpu_regs.h:95
__IO uint32_t tmr3
Definition: rpu_regs.h:119
__IO uint32_t spi2
Definition: rpu_regs.h:175
__IO uint32_t i2c0_bus0
Definition: rpu_regs.h:129
__IO uint32_t srcc
Definition: rpu_regs.h:149
__IO uint32_t tmr0
Definition: rpu_regs.h:113
__IO uint32_t dvs
Definition: rpu_regs.h:100
__IO uint32_t sysram1
Definition: rpu_regs.h:193
__IO uint32_t crypto
Definition: rpu_regs.h:92
__IO uint32_t icc0
Definition: rpu_regs.h:144
__IO uint32_t tmr4
Definition: rpu_regs.h:121
__IO uint32_t flc1
Definition: rpu_regs.h:142
__IO uint32_t sir
Definition: rpu_regs.h:90
__IO uint32_t sysram3
Definition: rpu_regs.h:197
__IO uint32_t tmr1
Definition: rpu_regs.h:115
__IO uint32_t bbsir
Definition: rpu_regs.h:102
__IO uint32_t uart1
Definition: rpu_regs.h:169
__IO uint32_t simo
Definition: rpu_regs.h:99
__IO uint32_t smon
Definition: rpu_regs.h:98
__IO uint32_t owm
Definition: rpu_regs.h:163
__IO uint32_t uart0
Definition: rpu_regs.h:167
Definition: rpu_regs.h:88
__IO uint32_t sfcc
Definition: rpu_regs.h:147
__IO uint32_t fcr
Definition: rpu_regs.h:91
__IO uint32_t spixr
Definition: rpu_regs.h:159