MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
mxc_sys.h
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32  * $Date: 2020-01-16 08:38:14 -0600 (Thu, 16 Jan 2020) $
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36 
42 #ifndef _MXC_SYS_H_
43 #define _MXC_SYS_H_
44 
45 #include "mxc_device.h"
46 #include "gcr_regs.h"
47 
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51 
53 typedef enum {
54  MXC_SYS_RESET_DMA0 = MXC_F_GCR_RST0_DMA0_POS,
55  MXC_SYS_RESET_WDT0 = MXC_F_GCR_RST0_WDT0_POS,
56  MXC_SYS_RESET_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS,
57  MXC_SYS_RESET_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS,
58  MXC_SYS_RESET_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS,
59  MXC_SYS_RESET_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS,
60  MXC_SYS_RESET_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS,
61  MXC_SYS_RESET_TIMER3 = MXC_F_GCR_RST0_TIMER3_POS,
62  MXC_SYS_RESET_TIMER4 = MXC_F_GCR_RST0_TIMER4_POS,
63  MXC_SYS_RESET_TIMER5 = MXC_F_GCR_RST0_TIMER5_POS,
64  MXC_SYS_RESET_UART0 = MXC_F_GCR_RST0_UART0_POS,
65  MXC_SYS_RESET_UART1 = MXC_F_GCR_RST0_UART1_POS,
66  MXC_SYS_RESET_SPI1 = MXC_F_GCR_RST0_SPI1_POS,
67  MXC_SYS_RESET_SPI2 = MXC_F_GCR_RST0_SPI2_POS,
68  MXC_SYS_RESET_I2C0 = MXC_F_GCR_RST0_I2C0_POS,
69  MXC_SYS_RESET_RTC = MXC_F_GCR_RST0_RTC_POS,
70  MXC_SYS_RESET_CRYPTO = MXC_F_GCR_RST0_CRYPTO_POS,
71  MXC_SYS_RESET_SMPHR = MXC_F_GCR_RST0_SMPHR_POS,
72  MXC_SYS_RESET_USB = MXC_F_GCR_RST0_USB_POS,
73  MXC_SYS_RESET_TRNG = MXC_F_GCR_RST0_TRNG_POS,
74  MXC_SYS_RESET_ADC = MXC_F_GCR_RST0_ADC_POS,
75  MXC_SYS_RESET_DMA1 = MXC_F_GCR_RST0_DMA1_POS,
76  MXC_SYS_RESET_UART2 = MXC_F_GCR_RST0_UART2_POS,
77  MXC_SYS_RESET_SRST = MXC_F_GCR_RST0_SOFT_RST_POS,
78  MXC_SYS_RESET_PRST = MXC_F_GCR_RST0_PERIPH_RST_POS,
79  MXC_SYS_RESET_SYSTEM = MXC_F_GCR_RST0_SYS_RST_POS ,
80  /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
81  MXC_SYS_RESET_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32),
82  MXC_SYS_RESET_PT = (MXC_F_GCR_RST1_PT_POS + 32),
83  MXC_SYS_RESET_SPIXIP = (MXC_F_GCR_RST1_SPIXIP_POS + 32),
84  MXC_SYS_RESET_XSPIM = (MXC_F_GCR_RST1_XSPIM_POS + 32),
85  MXC_SYS_RESET_SDHC = (MXC_F_GCR_RST1_SDHC_POS + 32),
86  MXC_SYS_RESET_OWIRE = (MXC_F_GCR_RST1_OWIRE_POS + 32),
87  MXC_SYS_RESET_WDT1 = (MXC_F_GCR_RST1_WDT1_POS+32),
88  MXC_SYS_RESET_SPI3 = (MXC_F_GCR_RST1_SPI3_POS+32),
89  MXC_SYS_RESET_XIPR = (MXC_F_GCR_RST1_XIPR_POS+32),
90  MXC_SYS_RESET_SEMA = (MXC_F_GCR_RST1_SEMA_POS+32),
91  MXC_SYS_RESET_WDT2 = (MXC_F_GCR_RST1_WDT2_POS + 32),
92  MXC_SYS_RESET_BTLE = (MXC_F_GCR_RST1_BTLE_POS + 32),
93  MXC_SYS_RESET_AUDIO = (MXC_F_GCR_RST1_AUDIO_POS + 32),
94  MXC_SYS_RESET_RPU = (MXC_F_GCR_RST1_RPU_POS + 32),
95  MXC_SYS_RESET_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32),
96  MXC_SYS_RESET_HTMR0 = (MXC_F_GCR_RST1_HTMR0_POS + 32),
97  MXC_SYS_RESET_HTMR1 = (MXC_F_GCR_RST1_HTMR1_POS + 32),
98  MXC_SYS_RESET_DVS = (MXC_F_GCR_RST1_DVS_POS + 32),
99  MXC_SYS_RESET_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32),
100 } mxc_sys_reset_t;
101 
103 typedef enum {
104  MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLK_DIS0_GPIO0_POS,
105  MXC_SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PCLK_DIS0_GPIO1_POS,
106  MXC_SYS_PERIPH_CLOCK_USB = MXC_F_GCR_PCLK_DIS0_USB_POS,
107  MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLK_DIS0_DMA0_POS,
108  MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLK_DIS0_SPI0_POS,
109  MXC_SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PCLK_DIS0_SPI1_POS,
110  MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLK_DIS0_UART0_POS,
111  MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLK_DIS0_UART1_POS,
112  MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLK_DIS0_I2C0_POS,
113  MXC_SYS_PERIPH_CLOCK_TPU = MXC_F_GCR_PCLK_DIS0_CRYPTO_POS,
114  MXC_SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PCLK_DIS0_TIMER0_POS,
115  MXC_SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PCLK_DIS0_TIMER1_POS,
116  MXC_SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PCLK_DIS0_TIMER2_POS,
117  MXC_SYS_PERIPH_CLOCK_T3 = MXC_F_GCR_PCLK_DIS0_TIMER3_POS,
118  MXC_SYS_PERIPH_CLOCK_T4 = MXC_F_GCR_PCLK_DIS0_TIMER4_POS,
119  MXC_SYS_PERIPH_CLOCK_T5 = MXC_F_GCR_PCLK_DIS0_TIMER5_POS,
120  MXC_SYS_PERIPH_CLOCK_ADC = MXC_F_GCR_PCLK_DIS0_ADC_POS,
121  MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLK_DIS0_I2C1_POS,
122  MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLK_DIS0_PTD_POS,
123  MXC_SYS_PERIPH_CLOCK_SPIXIP = MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS,
124  MXC_SYS_PERIPH_CLOCK_SPIXFC = MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS,
125  /* PERCKCN1 Below this line we add 32 to separate PERCKCN0 and PERCKCN1 */
126  MXC_SYS_PERIPH_CLOCK_BTLE =(MXC_F_GCR_PCLK_DIS1_BTLE_POS + 32),
127  MXC_SYS_PERIPH_CLOCK_UART2 =(MXC_F_GCR_PCLK_DIS1_UART2_POS + 32),
128  MXC_SYS_PERIPH_CLOCK_TRNG =(MXC_F_GCR_PCLK_DIS1_TRNG_POS + 32),
129  MXC_SYS_PERIPH_CLOCK_SCACHE =(MXC_F_GCR_PCLK_DIS1_SCACHE_POS + 32),
130  MXC_SYS_PERIPH_CLOCK_SDMA =(MXC_F_GCR_PCLK_DIS1_SDMA_POS + 32),
131  MXC_SYS_PERIPH_CLOCK_SMPHR =(MXC_F_GCR_PCLK_DIS1_SMPHR_POS + 32),
132  MXC_SYS_PERIPH_CLOCK_SDHC =(MXC_F_GCR_PCLK_DIS1_SDHC_POS + 32),
133  MXC_SYS_PERIPH_CLOCK_ICACHEXIP =(MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS + 32),
134  MXC_SYS_PERIPH_CLOCK_OWIRE =(MXC_F_GCR_PCLK_DIS1_OW_POS + 32),
135  MXC_SYS_PERIPH_CLOCK_SPI0 =(MXC_F_GCR_PCLK_DIS1_SPI3_POS + 32),
136  MXC_SYS_PERIPH_CLOCK_SPIXIPD =(MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS + 32),
137  MXC_SYS_PERIPH_CLOCK_DMA1 =(MXC_F_GCR_PCLK_DIS1_DMA1_POS + 32),
138  MXC_SYS_PERIPH_CLOCK_AUDIO =(MXC_F_GCR_PCLK_DIS1_AUDIO_POS + 32),
139  MXC_SYS_PERIPH_CLOCK_I2C2 =(MXC_F_GCR_PCLK_DIS1_I2C2_POS + 32),
140  MXC_SYS_PERIPH_CLOCK_HTMR0 =(MXC_F_GCR_PCLK_DIS1_HTMR0_POS + 32),
141  MXC_SYS_PERIPH_CLOCK_HTMR1 =(MXC_F_GCR_PCLK_DIS1_HTMR1_POS + 32),
142  MXC_SYS_PERIPH_CLOCK_WDT0 =(MXC_F_GCR_PCLK_DIS1_WDT0_POS + 32),
143  MXC_SYS_PERIPH_CLOCK_WDT1 =(MXC_F_GCR_PCLK_DIS1_WDT1_POS + 32),
144  MXC_SYS_PERIPH_CLOCK_WDT2 =(MXC_F_GCR_PCLK_DIS1_WDT2_POS + 32),
145  MXC_SYS_PERIPH_CLOCK_CPU1 =(MXC_F_GCR_PCLK_DIS1_CPU1_POS + 32),
146 } mxc_sys_periph_clock_t;
147 
148 typedef enum {
149  MXC_SYS_CLOCK_HIRC96 = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96,
150  MXC_SYS_CLOCK_HIRC8 = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8,
151  MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC,
152  MXC_SYS_CLOCK_XTAL32M = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M,
153  MXC_SYS_CLOCK_LIRC8K = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8,
154  MXC_SYS_CLOCK_XTAL32K = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K,
155 } mxc_sys_system_clock_t;
156 
157 #define MXC_SYS_SCACHE_CLK 1 // Enable SCACHE CLK
158 #define MXC_SYS_CTB_CLK 1 // Enable CTB CLK
159 
160 /***** Function Prototypes *****/
161 
167 int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock);
168 
173 void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock);
174 
179 void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock);
180 
185 void MXC_SYS_RTCClockEnable (void);
186 
191 int MXC_SYS_RTCClockDisable();
192 
198 int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock);
199 
205 int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
206 
213 int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock);
214 
220 int MXC_SYS_Clock_Timeout (uint32_t ready);
221 
226 void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
227 
232 uint8_t MXC_SYS_GetRev (void);
233 
240 int MXC_SYS_GetUSN (uint8_t* serialNumber, int len);
241 
242 #ifdef __cplusplus
243 }
244 #endif
245 
246 #endif /* _MXC_MXC_SYS_H_*/
MXC_F_GCR_RST0_SOFT_RST_POS
#define MXC_F_GCR_RST0_SOFT_RST_POS
Definition: gcr_regs.h:275
MXC_F_GCR_RST0_TIMER4_POS
#define MXC_F_GCR_RST0_TIMER4_POS
Definition: gcr_regs.h:230
MXC_F_GCR_RST0_UART2_POS
#define MXC_F_GCR_RST0_UART2_POS
Definition: gcr_regs.h:272
MXC_F_GCR_PCLK_DIS1_SMPHR_POS
#define MXC_F_GCR_PCLK_DIS1_SMPHR_POS
Definition: gcr_regs.h:742
MXC_F_GCR_RST0_I2C0_POS
#define MXC_F_GCR_RST0_I2C0_POS
Definition: gcr_regs.h:248
MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS
#define MXC_F_GCR_PCLK_DIS1_ICACHEXIP_POS
Definition: gcr_regs.h:748
MXC_F_GCR_RST1_OWIRE_POS
#define MXC_F_GCR_RST1_OWIRE_POS
Definition: gcr_regs.h:677
MXC_F_GCR_RST1_BTLE_POS
#define MXC_F_GCR_RST1_BTLE_POS
Definition: gcr_regs.h:695
MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32K
Definition: gcr_regs.h:323
MXC_F_GCR_RST0_TIMER3_POS
#define MXC_F_GCR_RST0_TIMER3_POS
Definition: gcr_regs.h:227
MXC_F_GCR_RST0_SYS_RST_POS
#define MXC_F_GCR_RST0_SYS_RST_POS
Definition: gcr_regs.h:281
MXC_F_GCR_RST0_PERIPH_RST_POS
#define MXC_F_GCR_RST0_PERIPH_RST_POS
Definition: gcr_regs.h:278
MXC_F_GCR_RST1_XSPIM_POS
#define MXC_F_GCR_RST1_XSPIM_POS
Definition: gcr_regs.h:671
MXC_F_GCR_PCLK_DIS1_HTMR0_POS
#define MXC_F_GCR_PCLK_DIS1_HTMR0_POS
Definition: gcr_regs.h:769
MXC_F_GCR_RST1_XIPR_POS
#define MXC_F_GCR_RST1_XIPR_POS
Definition: gcr_regs.h:686
MXC_F_GCR_RST0_GPIO0_POS
#define MXC_F_GCR_RST0_GPIO0_POS
Definition: gcr_regs.h:212
MXC_F_GCR_RST0_TIMER5_POS
#define MXC_F_GCR_RST0_TIMER5_POS
Definition: gcr_regs.h:233
MXC_F_GCR_PCLK_DIS1_WDT2_POS
#define MXC_F_GCR_PCLK_DIS1_WDT2_POS
Definition: gcr_regs.h:781
MXC_F_GCR_RST0_UART1_POS
#define MXC_F_GCR_RST0_UART1_POS
Definition: gcr_regs.h:239
MXC_F_GCR_RST0_RTC_POS
#define MXC_F_GCR_RST0_RTC_POS
Definition: gcr_regs.h:251
MXC_F_GCR_PCLK_DIS1_SDHC_POS
#define MXC_F_GCR_PCLK_DIS1_SDHC_POS
Definition: gcr_regs.h:745
MXC_F_GCR_PCLK_DIS0_CRYPTO_POS
#define MXC_F_GCR_PCLK_DIS0_CRYPTO_POS
Definition: gcr_regs.h:495
MXC_F_GCR_RST0_SPI2_POS
#define MXC_F_GCR_RST0_SPI2_POS
Definition: gcr_regs.h:245
MXC_F_GCR_RST0_DMA0_POS
#define MXC_F_GCR_RST0_DMA0_POS
Definition: gcr_regs.h:206
MXC_F_GCR_RST0_ADC_POS
#define MXC_F_GCR_RST0_ADC_POS
Definition: gcr_regs.h:266
MXC_F_GCR_PCLK_DIS0_I2C0_POS
#define MXC_F_GCR_PCLK_DIS0_I2C0_POS
Definition: gcr_regs.h:492
MXC_F_GCR_RST1_I2C2_POS
#define MXC_F_GCR_RST1_I2C2_POS
Definition: gcr_regs.h:701
MXC_F_GCR_RST0_DMA1_POS
#define MXC_F_GCR_RST0_DMA1_POS
Definition: gcr_regs.h:269
MXC_F_GCR_RST1_SPI3_POS
#define MXC_F_GCR_RST1_SPI3_POS
Definition: gcr_regs.h:683
MXC_F_GCR_PCLK_DIS1_SPI3_POS
#define MXC_F_GCR_PCLK_DIS1_SPI3_POS
Definition: gcr_regs.h:754
MXC_F_GCR_PCLK_DIS1_CPU1_POS
#define MXC_F_GCR_PCLK_DIS1_CPU1_POS
Definition: gcr_regs.h:784
MXC_F_GCR_PCLK_DIS1_I2C2_POS
#define MXC_F_GCR_PCLK_DIS1_I2C2_POS
Definition: gcr_regs.h:766
MXC_F_GCR_RST1_SIMO_POS
#define MXC_F_GCR_RST1_SIMO_POS
Definition: gcr_regs.h:716
MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_LIRC8
Definition: gcr_regs.h:317
MXC_F_GCR_PCLK_DIS0_ADC_POS
#define MXC_F_GCR_PCLK_DIS0_ADC_POS
Definition: gcr_regs.h:516
MXC_F_GCR_RST0_CRYPTO_POS
#define MXC_F_GCR_RST0_CRYPTO_POS
Definition: gcr_regs.h:254
MXC_F_GCR_PCLK_DIS0_USB_POS
#define MXC_F_GCR_PCLK_DIS0_USB_POS
Definition: gcr_regs.h:474
MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS
#define MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS
Definition: gcr_regs.h:757
MXC_F_GCR_RST1_SPIXIP_POS
#define MXC_F_GCR_RST1_SPIXIP_POS
Definition: gcr_regs.h:668
MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS
#define MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS
Definition: gcr_regs.h:528
MXC_F_GCR_RST1_SDHC_POS
#define MXC_F_GCR_RST1_SDHC_POS
Definition: gcr_regs.h:674
MXC_F_GCR_RST1_DVS_POS
#define MXC_F_GCR_RST1_DVS_POS
Definition: gcr_regs.h:713
MXC_F_GCR_RST0_TRNG_POS
#define MXC_F_GCR_RST0_TRNG_POS
Definition: gcr_regs.h:263
MXC_F_GCR_RST0_TIMER1_POS
#define MXC_F_GCR_RST0_TIMER1_POS
Definition: gcr_regs.h:221
MXC_F_GCR_PCLK_DIS0_PTD_POS
#define MXC_F_GCR_PCLK_DIS0_PTD_POS
Definition: gcr_regs.h:522
MXC_F_GCR_PCLK_DIS1_WDT1_POS
#define MXC_F_GCR_PCLK_DIS1_WDT1_POS
Definition: gcr_regs.h:778
MXC_F_GCR_PCLK_DIS1_SCACHE_POS
#define MXC_F_GCR_PCLK_DIS1_SCACHE_POS
Definition: gcr_regs.h:736
MXC_F_GCR_RST0_SPI1_POS
#define MXC_F_GCR_RST0_SPI1_POS
Definition: gcr_regs.h:242
MXC_F_GCR_PCLK_DIS0_UART0_POS
#define MXC_F_GCR_PCLK_DIS0_UART0_POS
Definition: gcr_regs.h:486
MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8
Definition: gcr_regs.h:321
MXC_F_GCR_RST1_HTMR1_POS
#define MXC_F_GCR_RST1_HTMR1_POS
Definition: gcr_regs.h:710
MXC_F_GCR_PCLK_DIS1_OW_POS
#define MXC_F_GCR_PCLK_DIS1_OW_POS
Definition: gcr_regs.h:751
MXC_F_GCR_PCLK_DIS0_I2C1_POS
#define MXC_F_GCR_PCLK_DIS0_I2C1_POS
Definition: gcr_regs.h:519
MXC_F_GCR_PCLK_DIS1_HTMR1_POS
#define MXC_F_GCR_PCLK_DIS1_HTMR1_POS
Definition: gcr_regs.h:772
MXC_F_GCR_RST1_WDT2_POS
#define MXC_F_GCR_RST1_WDT2_POS
Definition: gcr_regs.h:692
MXC_F_GCR_PCLK_DIS0_GPIO1_POS
#define MXC_F_GCR_PCLK_DIS0_GPIO1_POS
Definition: gcr_regs.h:471
MXC_F_GCR_PCLK_DIS0_DMA0_POS
#define MXC_F_GCR_PCLK_DIS0_DMA0_POS
Definition: gcr_regs.h:477
MXC_F_GCR_RST0_SMPHR_POS
#define MXC_F_GCR_RST0_SMPHR_POS
Definition: gcr_regs.h:257
MXC_F_GCR_PCLK_DIS0_UART1_POS
#define MXC_F_GCR_PCLK_DIS0_UART1_POS
Definition: gcr_regs.h:489
MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96
Definition: gcr_regs.h:319
MXC_F_GCR_PCLK_DIS1_WDT0_POS
#define MXC_F_GCR_PCLK_DIS1_WDT0_POS
Definition: gcr_regs.h:775
MXC_F_GCR_RST1_PT_POS
#define MXC_F_GCR_RST1_PT_POS
Definition: gcr_regs.h:665
MXC_F_GCR_RST1_AUDIO_POS
#define MXC_F_GCR_RST1_AUDIO_POS
Definition: gcr_regs.h:698
MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_XTAL32M
Definition: gcr_regs.h:315
MXC_F_GCR_RST1_WDT1_POS
#define MXC_F_GCR_RST1_WDT1_POS
Definition: gcr_regs.h:680
MXC_F_GCR_PCLK_DIS0_TIMER0_POS
#define MXC_F_GCR_PCLK_DIS0_TIMER0_POS
Definition: gcr_regs.h:498
MXC_F_GCR_RST1_RPU_POS
#define MXC_F_GCR_RST1_RPU_POS
Definition: gcr_regs.h:704
MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC
#define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC
Definition: gcr_regs.h:313
MXC_F_GCR_PCLK_DIS1_BTLE_POS
#define MXC_F_GCR_PCLK_DIS1_BTLE_POS
Definition: gcr_regs.h:727
MXC_F_GCR_PCLK_DIS0_TIMER4_POS
#define MXC_F_GCR_PCLK_DIS0_TIMER4_POS
Definition: gcr_regs.h:510
MXC_F_GCR_PCLK_DIS1_TRNG_POS
#define MXC_F_GCR_PCLK_DIS1_TRNG_POS
Definition: gcr_regs.h:733
MXC_F_GCR_PCLK_DIS1_UART2_POS
#define MXC_F_GCR_PCLK_DIS1_UART2_POS
Definition: gcr_regs.h:730
MXC_F_GCR_RST0_USB_POS
#define MXC_F_GCR_RST0_USB_POS
Definition: gcr_regs.h:260
MXC_F_GCR_PCLK_DIS0_TIMER5_POS
#define MXC_F_GCR_PCLK_DIS0_TIMER5_POS
Definition: gcr_regs.h:513
MXC_F_GCR_RST1_HTMR0_POS
#define MXC_F_GCR_RST1_HTMR0_POS
Definition: gcr_regs.h:707
MXC_F_GCR_PCLK_DIS1_AUDIO_POS
#define MXC_F_GCR_PCLK_DIS1_AUDIO_POS
Definition: gcr_regs.h:763
MXC_F_GCR_RST0_GPIO1_POS
#define MXC_F_GCR_RST0_GPIO1_POS
Definition: gcr_regs.h:215
MXC_F_GCR_PCLK_DIS1_DMA1_POS
#define MXC_F_GCR_PCLK_DIS1_DMA1_POS
Definition: gcr_regs.h:760
MXC_F_GCR_PCLK_DIS0_SPI1_POS
#define MXC_F_GCR_PCLK_DIS0_SPI1_POS
Definition: gcr_regs.h:483
MXC_F_GCR_RST0_TIMER2_POS
#define MXC_F_GCR_RST0_TIMER2_POS
Definition: gcr_regs.h:224
MXC_F_GCR_RST1_I2C1_POS
#define MXC_F_GCR_RST1_I2C1_POS
Definition: gcr_regs.h:662
MXC_F_GCR_PCLK_DIS0_GPIO0_POS
#define MXC_F_GCR_PCLK_DIS0_GPIO0_POS
Definition: gcr_regs.h:468
MXC_F_GCR_PCLK_DIS0_SPI0_POS
#define MXC_F_GCR_PCLK_DIS0_SPI0_POS
Definition: gcr_regs.h:480
MXC_F_GCR_RST0_TIMER0_POS
#define MXC_F_GCR_RST0_TIMER0_POS
Definition: gcr_regs.h:218
MXC_F_GCR_PCLK_DIS0_TIMER2_POS
#define MXC_F_GCR_PCLK_DIS0_TIMER2_POS
Definition: gcr_regs.h:504
MXC_F_GCR_PCLK_DIS0_TIMER1_POS
#define MXC_F_GCR_PCLK_DIS0_TIMER1_POS
Definition: gcr_regs.h:501
MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS
#define MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS
Definition: gcr_regs.h:525
MXC_F_GCR_PCLK_DIS1_SDMA_POS
#define MXC_F_GCR_PCLK_DIS1_SDMA_POS
Definition: gcr_regs.h:739
MXC_F_GCR_RST0_UART0_POS
#define MXC_F_GCR_RST0_UART0_POS
Definition: gcr_regs.h:236
MXC_F_GCR_PCLK_DIS0_TIMER3_POS
#define MXC_F_GCR_PCLK_DIS0_TIMER3_POS
Definition: gcr_regs.h:507
MXC_F_GCR_RST1_SEMA_POS
#define MXC_F_GCR_RST1_SEMA_POS
Definition: gcr_regs.h:689
MXC_F_GCR_RST0_WDT0_POS
#define MXC_F_GCR_RST0_WDT0_POS
Definition: gcr_regs.h:209