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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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ECC IRQ Enable Register.
#define MXC_F_GCR_ECC_IRQEN_EC0ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_EC0ECCEN_POS)) |
ECC_IRQEN_EC0ECCEN Mask
#define MXC_F_GCR_ECC_IRQEN_EC0ECCEN_POS 8 |
ECC_IRQEN_EC0ECCEN Position
#define MXC_F_GCR_ECC_IRQEN_EC1ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_EC1ECCEN_POS)) |
ECC_IRQEN_EC1ECCEN Mask
#define MXC_F_GCR_ECC_IRQEN_EC1ECCEN_POS 9 |
ECC_IRQEN_EC1ECCEN Position
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM0EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM0EN_POS)) |
ECC_IRQEN_ECCSYSRAM0EN Mask
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM0EN_POS 0 |
ECC_IRQEN_ECCSYSRAM0EN Position
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM1EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM1EN_POS)) |
ECC_IRQEN_ECCSYSRAM1EN Mask
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM1EN_POS 1 |
ECC_IRQEN_ECCSYSRAM1EN Position
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM2EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM2EN_POS)) |
ECC_IRQEN_ECCSYSRAM2EN Mask
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM2EN_POS 2 |
ECC_IRQEN_ECCSYSRAM2EN Position
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM3EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM3EN_POS)) |
ECC_IRQEN_ECCSYSRAM3EN Mask
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM3EN_POS 3 |
ECC_IRQEN_ECCSYSRAM3EN Position
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM4EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM4EN_POS)) |
ECC_IRQEN_ECCSYSRAM4EN Mask
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM4EN_POS 4 |
ECC_IRQEN_ECCSYSRAM4EN Position
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM5EN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ECCSYSRAM5EN_POS)) |
ECC_IRQEN_ECCSYSRAM5EN Mask
#define MXC_F_GCR_ECC_IRQEN_ECCSYSRAM5EN_POS 5 |
ECC_IRQEN_ECCSYSRAM5EN Position
#define MXC_F_GCR_ECC_IRQEN_FL0ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS)) |
ECC_IRQEN_FL0ECCEN Mask
#define MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS 11 |
ECC_IRQEN_FL0ECCEN Position
#define MXC_F_GCR_ECC_IRQEN_FL1ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS)) |
ECC_IRQEN_FL1ECCEN Mask
#define MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS 12 |
ECC_IRQEN_FL1ECCEN Position
#define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS)) |
ECC_IRQEN_ICXIPECCEN Mask
#define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS 10 |
ECC_IRQEN_ICXIPECCEN Position
#define MXC_F_GCR_ECC_IRQEN_SYSRAM6ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM6ECCEN_POS)) |
ECC_IRQEN_SYSRAM6ECCEN Mask
#define MXC_F_GCR_ECC_IRQEN_SYSRAM6ECCEN_POS 6 |
ECC_IRQEN_SYSRAM6ECCEN Position