MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
Register Offsets

Macros

#define MXC_R_GCR_SCON   ((uint32_t)0x00000000UL)
 
#define MXC_R_GCR_RST0   ((uint32_t)0x00000004UL)
 
#define MXC_R_GCR_CLK_CTRL   ((uint32_t)0x00000008UL)
 
#define MXC_R_GCR_PMR   ((uint32_t)0x0000000CUL)
 
#define MXC_R_GCR_PCLK_DIV   ((uint32_t)0x00000018UL)
 
#define MXC_R_GCR_PCLK_DIS0   ((uint32_t)0x00000024UL)
 
#define MXC_R_GCR_MEM_CLK   ((uint32_t)0x00000028UL)
 
#define MXC_R_GCR_MEM_ZERO   ((uint32_t)0x0000002CUL)
 
#define MXC_R_GCR_SCCK   ((uint32_t)0x00000034UL)
 
#define MXC_R_GCR_MPRI0   ((uint32_t)0x00000038UL)
 
#define MXC_R_GCR_MPRI1   ((uint32_t)0x0000003CUL)
 
#define MXC_R_GCR_SYS_STAT   ((uint32_t)0x00000040UL)
 
#define MXC_R_GCR_RST1   ((uint32_t)0x00000044UL)
 
#define MXC_R_GCR_PCLK_DIS1   ((uint32_t)0x00000048UL)
 
#define MXC_R_GCR_EVENT_EN   ((uint32_t)0x0000004CUL)
 
#define MXC_R_GCR_REVISION   ((uint32_t)0x00000050UL)
 
#define MXC_R_GCR_SYS_STAT_IE   ((uint32_t)0x00000054UL)
 
#define MXC_R_GCR_ECC_ER   ((uint32_t)0x00000064UL)
 
#define MXC_R_GCR_ECC_NDED   ((uint32_t)0x00000068UL)
 
#define MXC_R_GCR_ECC_IRQEN   ((uint32_t)0x0000006CUL)
 
#define MXC_R_GCR_ECC_ERRAD   ((uint32_t)0x00000070UL)
 
#define MXC_R_GCR_BTLE_LDOCR   ((uint32_t)0x00000074UL)
 
#define MXC_R_GCR_BTLE_LDODCR   ((uint32_t)0x00000078UL)
 
#define MXC_R_GCR_GPR0   ((uint32_t)0x00000080UL)
 
#define MXC_R_GCR_APB_ASYNC   ((uint32_t)0x00000084UL)
 

Detailed Description

GCR Peripheral Register Offsets from the GCR Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_GCR_APB_ASYNC

#define MXC_R_GCR_APB_ASYNC   ((uint32_t)0x00000084UL)

Offset from GCR Base Address: 0x0084

◆ MXC_R_GCR_BTLE_LDOCR

#define MXC_R_GCR_BTLE_LDOCR   ((uint32_t)0x00000074UL)

Offset from GCR Base Address: 0x0074

◆ MXC_R_GCR_BTLE_LDODCR

#define MXC_R_GCR_BTLE_LDODCR   ((uint32_t)0x00000078UL)

Offset from GCR Base Address: 0x0078

◆ MXC_R_GCR_CLK_CTRL

#define MXC_R_GCR_CLK_CTRL   ((uint32_t)0x00000008UL)

Offset from GCR Base Address: 0x0008

◆ MXC_R_GCR_ECC_ER

#define MXC_R_GCR_ECC_ER   ((uint32_t)0x00000064UL)

Offset from GCR Base Address: 0x0064

◆ MXC_R_GCR_ECC_ERRAD

#define MXC_R_GCR_ECC_ERRAD   ((uint32_t)0x00000070UL)

Offset from GCR Base Address: 0x0070

◆ MXC_R_GCR_ECC_IRQEN

#define MXC_R_GCR_ECC_IRQEN   ((uint32_t)0x0000006CUL)

Offset from GCR Base Address: 0x006C

◆ MXC_R_GCR_ECC_NDED

#define MXC_R_GCR_ECC_NDED   ((uint32_t)0x00000068UL)

Offset from GCR Base Address: 0x0068

◆ MXC_R_GCR_EVENT_EN

#define MXC_R_GCR_EVENT_EN   ((uint32_t)0x0000004CUL)

Offset from GCR Base Address: 0x004C

◆ MXC_R_GCR_GPR0

#define MXC_R_GCR_GPR0   ((uint32_t)0x00000080UL)

Offset from GCR Base Address: 0x0080

◆ MXC_R_GCR_MEM_CLK

#define MXC_R_GCR_MEM_CLK   ((uint32_t)0x00000028UL)

Offset from GCR Base Address: 0x0028

◆ MXC_R_GCR_MEM_ZERO

#define MXC_R_GCR_MEM_ZERO   ((uint32_t)0x0000002CUL)

Offset from GCR Base Address: 0x002C

◆ MXC_R_GCR_MPRI0

#define MXC_R_GCR_MPRI0   ((uint32_t)0x00000038UL)

Offset from GCR Base Address: 0x0038

◆ MXC_R_GCR_MPRI1

#define MXC_R_GCR_MPRI1   ((uint32_t)0x0000003CUL)

Offset from GCR Base Address: 0x003C

◆ MXC_R_GCR_PCLK_DIS0

#define MXC_R_GCR_PCLK_DIS0   ((uint32_t)0x00000024UL)

Offset from GCR Base Address: 0x0024

◆ MXC_R_GCR_PCLK_DIS1

#define MXC_R_GCR_PCLK_DIS1   ((uint32_t)0x00000048UL)

Offset from GCR Base Address: 0x0048

◆ MXC_R_GCR_PCLK_DIV

#define MXC_R_GCR_PCLK_DIV   ((uint32_t)0x00000018UL)

Offset from GCR Base Address: 0x0018

◆ MXC_R_GCR_PMR

#define MXC_R_GCR_PMR   ((uint32_t)0x0000000CUL)

Offset from GCR Base Address: 0x000C

◆ MXC_R_GCR_REVISION

#define MXC_R_GCR_REVISION   ((uint32_t)0x00000050UL)

Offset from GCR Base Address: 0x0050

◆ MXC_R_GCR_RST0

#define MXC_R_GCR_RST0   ((uint32_t)0x00000004UL)

Offset from GCR Base Address: 0x0004

◆ MXC_R_GCR_RST1

#define MXC_R_GCR_RST1   ((uint32_t)0x00000044UL)

Offset from GCR Base Address: 0x0044

◆ MXC_R_GCR_SCCK

#define MXC_R_GCR_SCCK   ((uint32_t)0x00000034UL)

Offset from GCR Base Address: 0x0034

◆ MXC_R_GCR_SCON

#define MXC_R_GCR_SCON   ((uint32_t)0x00000000UL)

Offset from GCR Base Address: 0x0000

◆ MXC_R_GCR_SYS_STAT

#define MXC_R_GCR_SYS_STAT   ((uint32_t)0x00000040UL)

Offset from GCR Base Address: 0x0040

◆ MXC_R_GCR_SYS_STAT_IE

#define MXC_R_GCR_SYS_STAT_IE   ((uint32_t)0x00000054UL)

Offset from GCR Base Address: 0x0054