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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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QSPI0 Protection Register.
#define MXC_F_RPU_SPI0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNR_POS)) |
SPI0_CRYPTOACNR Mask
#define MXC_F_RPU_SPI0_CRYPTOACNR_POS 14 |
SPI0_CRYPTOACNR Position
#define MXC_F_RPU_SPI0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNW_POS)) |
SPI0_CRYPTOACNW Mask
#define MXC_F_RPU_SPI0_CRYPTOACNW_POS 15 |
SPI0_CRYPTOACNW Position
#define MXC_F_RPU_SPI0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNR_POS)) |
SPI0_DMA0ACNR Mask
#define MXC_F_RPU_SPI0_DMA0ACNR_POS 0 |
SPI0_DMA0ACNR Position
#define MXC_F_RPU_SPI0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNW_POS)) |
SPI0_DMA0ACNW Mask
#define MXC_F_RPU_SPI0_DMA0ACNW_POS 1 |
SPI0_DMA0ACNW Position
#define MXC_F_RPU_SPI0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNR_POS)) |
SPI0_DMA1ACNR Mask
#define MXC_F_RPU_SPI0_DMA1ACNR_POS 2 |
SPI0_DMA1ACNR Position
#define MXC_F_RPU_SPI0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNW_POS)) |
SPI0_DMA1ACNW Mask
#define MXC_F_RPU_SPI0_DMA1ACNW_POS 3 |
SPI0_DMA1ACNW Position
#define MXC_F_RPU_SPI0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNR_POS)) |
SPI0_SDIOACNR Mask
#define MXC_F_RPU_SPI0_SDIOACNR_POS 16 |
SPI0_SDIOACNR Position
#define MXC_F_RPU_SPI0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNW_POS)) |
SPI0_SDIOACNW Mask
#define MXC_F_RPU_SPI0_SDIOACNW_POS 17 |
SPI0_SDIOACNW Position
#define MXC_F_RPU_SPI0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNR_POS)) |
SPI0_SDMADACNR Mask
#define MXC_F_RPU_SPI0_SDMADACNR_POS 10 |
SPI0_SDMADACNR Position
#define MXC_F_RPU_SPI0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNW_POS)) |
SPI0_SDMADACNW Mask
#define MXC_F_RPU_SPI0_SDMADACNW_POS 11 |
SPI0_SDMADACNW Position
#define MXC_F_RPU_SPI0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNR_POS)) |
SPI0_SDMAIACNR Mask
#define MXC_F_RPU_SPI0_SDMAIACNR_POS 12 |
SPI0_SDMAIACNR Position
#define MXC_F_RPU_SPI0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNW_POS)) |
SPI0_SDMAIACNW Mask
#define MXC_F_RPU_SPI0_SDMAIACNW_POS 13 |
SPI0_SDMAIACNW Position
#define MXC_F_RPU_SPI0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNR_POS)) |
SPI0_SYS0ACNR Mask
#define MXC_F_RPU_SPI0_SYS0ACNR_POS 6 |
SPI0_SYS0ACNR Position
#define MXC_F_RPU_SPI0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNW_POS)) |
SPI0_SYS0ACNW Mask
#define MXC_F_RPU_SPI0_SYS0ACNW_POS 7 |
SPI0_SYS0ACNW Position
#define MXC_F_RPU_SPI0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNR_POS)) |
SPI0_SYS1ACNR Mask
#define MXC_F_RPU_SPI0_SYS1ACNR_POS 8 |
SPI0_SYS1ACNR Position
#define MXC_F_RPU_SPI0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNW_POS)) |
SPI0_SYS1ACNW Mask
#define MXC_F_RPU_SPI0_SYS1ACNW_POS 9 |
SPI0_SYS1ACNW Position
#define MXC_F_RPU_SPI0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNR_POS)) |
SPI0_USBACNR Mask
#define MXC_F_RPU_SPI0_USBACNR_POS 4 |
SPI0_USBACNR Position
#define MXC_F_RPU_SPI0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNW_POS)) |
SPI0_USBACNW Mask
#define MXC_F_RPU_SPI0_USBACNW_POS 5 |
SPI0_USBACNW Position