MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665

Macros

#define MXC_F_SRCC_INVALIDATE_IA_POS   0
 
#define MXC_F_SRCC_INVALIDATE_IA   ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_INVALIDATE_IA_POS))
 

Detailed Description

Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.

Macro Definition Documentation

◆ MXC_F_SRCC_INVALIDATE_IA

#define MXC_F_SRCC_INVALIDATE_IA   ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_INVALIDATE_IA_POS))

INVALIDATE_IA Mask

◆ MXC_F_SRCC_INVALIDATE_IA_POS

#define MXC_F_SRCC_INVALIDATE_IA_POS   0

INVALIDATE_IA Position