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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Peripheral Clock Disable.
#define MXC_F_GCR_PCLK_DIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_ADC_POS)) |
PCLK_DIS0_ADC Mask
#define MXC_F_GCR_PCLK_DIS0_ADC_POS 23 |
PCLK_DIS0_ADC Position
#define MXC_F_GCR_PCLK_DIS0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_CRYPTO_POS)) |
PCLK_DIS0_CRYPTO Mask
#define MXC_F_GCR_PCLK_DIS0_CRYPTO_POS 14 |
PCLK_DIS0_CRYPTO Position
#define MXC_F_GCR_PCLK_DIS0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMA0_POS)) |
PCLK_DIS0_DMA0 Mask
#define MXC_F_GCR_PCLK_DIS0_DMA0_POS 5 |
PCLK_DIS0_DMA0 Position
#define MXC_F_GCR_PCLK_DIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0_POS)) |
PCLK_DIS0_GPIO0 Mask
#define MXC_F_GCR_PCLK_DIS0_GPIO0_POS 0 |
PCLK_DIS0_GPIO0 Position
#define MXC_F_GCR_PCLK_DIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO1_POS)) |
PCLK_DIS0_GPIO1 Mask
#define MXC_F_GCR_PCLK_DIS0_GPIO1_POS 1 |
PCLK_DIS0_GPIO1 Position
#define MXC_F_GCR_PCLK_DIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0_POS)) |
PCLK_DIS0_I2C0 Mask
#define MXC_F_GCR_PCLK_DIS0_I2C0_POS 13 |
PCLK_DIS0_I2C0 Position
#define MXC_F_GCR_PCLK_DIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1_POS)) |
PCLK_DIS0_I2C1 Mask
#define MXC_F_GCR_PCLK_DIS0_I2C1_POS 28 |
PCLK_DIS0_I2C1 Position
#define MXC_F_GCR_PCLK_DIS0_PTD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_PTD_POS)) |
PCLK_DIS0_PTD Mask
#define MXC_F_GCR_PCLK_DIS0_PTD_POS 29 |
PCLK_DIS0_PTD Position
#define MXC_F_GCR_PCLK_DIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0_POS)) |
PCLK_DIS0_SPI0 Mask
#define MXC_F_GCR_PCLK_DIS0_SPI0_POS 6 |
PCLK_DIS0_SPI0 Position
#define MXC_F_GCR_PCLK_DIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1_POS)) |
PCLK_DIS0_SPI1 Mask
#define MXC_F_GCR_PCLK_DIS0_SPI1_POS 7 |
PCLK_DIS0_SPI1 Position
#define MXC_F_GCR_PCLK_DIS0_SPIXIPF ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS)) |
PCLK_DIS0_SPIXIPF Mask
#define MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS 30 |
PCLK_DIS0_SPIXIPF Position
#define MXC_F_GCR_PCLK_DIS0_SPIXIPM ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS)) |
PCLK_DIS0_SPIXIPM Mask
#define MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS 31 |
PCLK_DIS0_SPIXIPM Position
#define MXC_F_GCR_PCLK_DIS0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0_POS)) |
PCLK_DIS0_TIMER0 Mask
#define MXC_F_GCR_PCLK_DIS0_TIMER0_POS 15 |
PCLK_DIS0_TIMER0 Position
#define MXC_F_GCR_PCLK_DIS0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1_POS)) |
PCLK_DIS0_TIMER1 Mask
#define MXC_F_GCR_PCLK_DIS0_TIMER1_POS 16 |
PCLK_DIS0_TIMER1 Position
#define MXC_F_GCR_PCLK_DIS0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2_POS)) |
PCLK_DIS0_TIMER2 Mask
#define MXC_F_GCR_PCLK_DIS0_TIMER2_POS 17 |
PCLK_DIS0_TIMER2 Position
#define MXC_F_GCR_PCLK_DIS0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER3_POS)) |
PCLK_DIS0_TIMER3 Mask
#define MXC_F_GCR_PCLK_DIS0_TIMER3_POS 18 |
PCLK_DIS0_TIMER3 Position
#define MXC_F_GCR_PCLK_DIS0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER4_POS)) |
PCLK_DIS0_TIMER4 Mask
#define MXC_F_GCR_PCLK_DIS0_TIMER4_POS 19 |
PCLK_DIS0_TIMER4 Position
#define MXC_F_GCR_PCLK_DIS0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER5_POS)) |
PCLK_DIS0_TIMER5 Mask
#define MXC_F_GCR_PCLK_DIS0_TIMER5_POS 20 |
PCLK_DIS0_TIMER5 Position
#define MXC_F_GCR_PCLK_DIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0_POS)) |
PCLK_DIS0_UART0 Mask
#define MXC_F_GCR_PCLK_DIS0_UART0_POS 9 |
PCLK_DIS0_UART0 Position
#define MXC_F_GCR_PCLK_DIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1_POS)) |
PCLK_DIS0_UART1 Mask
#define MXC_F_GCR_PCLK_DIS0_UART1_POS 10 |
PCLK_DIS0_UART1 Position
#define MXC_F_GCR_PCLK_DIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_USB_POS)) |
PCLK_DIS0_USB Mask
#define MXC_F_GCR_PCLK_DIS0_USB_POS 3 |
PCLK_DIS0_USB Position