MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665

Macros

#define MXC_F_RPU_SPI0_DMA0ACNR_POS   0
 
#define MXC_F_RPU_SPI0_DMA0ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNR_POS))
 
#define MXC_F_RPU_SPI0_DMA0ACNW_POS   1
 
#define MXC_F_RPU_SPI0_DMA0ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNW_POS))
 
#define MXC_F_RPU_SPI0_DMA1ACNR_POS   2
 
#define MXC_F_RPU_SPI0_DMA1ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNR_POS))
 
#define MXC_F_RPU_SPI0_DMA1ACNW_POS   3
 
#define MXC_F_RPU_SPI0_DMA1ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNW_POS))
 
#define MXC_F_RPU_SPI0_USBACNR_POS   4
 
#define MXC_F_RPU_SPI0_USBACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNR_POS))
 
#define MXC_F_RPU_SPI0_USBACNW_POS   5
 
#define MXC_F_RPU_SPI0_USBACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNW_POS))
 
#define MXC_F_RPU_SPI0_SYS0ACNR_POS   6
 
#define MXC_F_RPU_SPI0_SYS0ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNR_POS))
 
#define MXC_F_RPU_SPI0_SYS0ACNW_POS   7
 
#define MXC_F_RPU_SPI0_SYS0ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNW_POS))
 
#define MXC_F_RPU_SPI0_SYS1ACNR_POS   8
 
#define MXC_F_RPU_SPI0_SYS1ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNR_POS))
 
#define MXC_F_RPU_SPI0_SYS1ACNW_POS   9
 
#define MXC_F_RPU_SPI0_SYS1ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNW_POS))
 
#define MXC_F_RPU_SPI0_SDMADACNR_POS   10
 
#define MXC_F_RPU_SPI0_SDMADACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNR_POS))
 
#define MXC_F_RPU_SPI0_SDMADACNW_POS   11
 
#define MXC_F_RPU_SPI0_SDMADACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNW_POS))
 
#define MXC_F_RPU_SPI0_SDMAIACNR_POS   12
 
#define MXC_F_RPU_SPI0_SDMAIACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNR_POS))
 
#define MXC_F_RPU_SPI0_SDMAIACNW_POS   13
 
#define MXC_F_RPU_SPI0_SDMAIACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNW_POS))
 
#define MXC_F_RPU_SPI0_CRYPTOACNR_POS   14
 
#define MXC_F_RPU_SPI0_CRYPTOACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNR_POS))
 
#define MXC_F_RPU_SPI0_CRYPTOACNW_POS   15
 
#define MXC_F_RPU_SPI0_CRYPTOACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNW_POS))
 
#define MXC_F_RPU_SPI0_SDIOACNR_POS   16
 
#define MXC_F_RPU_SPI0_SDIOACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNR_POS))
 
#define MXC_F_RPU_SPI0_SDIOACNW_POS   17
 
#define MXC_F_RPU_SPI0_SDIOACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNW_POS))
 

Detailed Description

QSPI0 Protection Register.

Macro Definition Documentation

◆ MXC_F_RPU_SPI0_CRYPTOACNR

#define MXC_F_RPU_SPI0_CRYPTOACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNR_POS))

SPI0_CRYPTOACNR Mask

◆ MXC_F_RPU_SPI0_CRYPTOACNR_POS

#define MXC_F_RPU_SPI0_CRYPTOACNR_POS   14

SPI0_CRYPTOACNR Position

◆ MXC_F_RPU_SPI0_CRYPTOACNW

#define MXC_F_RPU_SPI0_CRYPTOACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNW_POS))

SPI0_CRYPTOACNW Mask

◆ MXC_F_RPU_SPI0_CRYPTOACNW_POS

#define MXC_F_RPU_SPI0_CRYPTOACNW_POS   15

SPI0_CRYPTOACNW Position

◆ MXC_F_RPU_SPI0_DMA0ACNR

#define MXC_F_RPU_SPI0_DMA0ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNR_POS))

SPI0_DMA0ACNR Mask

◆ MXC_F_RPU_SPI0_DMA0ACNR_POS

#define MXC_F_RPU_SPI0_DMA0ACNR_POS   0

SPI0_DMA0ACNR Position

◆ MXC_F_RPU_SPI0_DMA0ACNW

#define MXC_F_RPU_SPI0_DMA0ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNW_POS))

SPI0_DMA0ACNW Mask

◆ MXC_F_RPU_SPI0_DMA0ACNW_POS

#define MXC_F_RPU_SPI0_DMA0ACNW_POS   1

SPI0_DMA0ACNW Position

◆ MXC_F_RPU_SPI0_DMA1ACNR

#define MXC_F_RPU_SPI0_DMA1ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNR_POS))

SPI0_DMA1ACNR Mask

◆ MXC_F_RPU_SPI0_DMA1ACNR_POS

#define MXC_F_RPU_SPI0_DMA1ACNR_POS   2

SPI0_DMA1ACNR Position

◆ MXC_F_RPU_SPI0_DMA1ACNW

#define MXC_F_RPU_SPI0_DMA1ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNW_POS))

SPI0_DMA1ACNW Mask

◆ MXC_F_RPU_SPI0_DMA1ACNW_POS

#define MXC_F_RPU_SPI0_DMA1ACNW_POS   3

SPI0_DMA1ACNW Position

◆ MXC_F_RPU_SPI0_SDIOACNR

#define MXC_F_RPU_SPI0_SDIOACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNR_POS))

SPI0_SDIOACNR Mask

◆ MXC_F_RPU_SPI0_SDIOACNR_POS

#define MXC_F_RPU_SPI0_SDIOACNR_POS   16

SPI0_SDIOACNR Position

◆ MXC_F_RPU_SPI0_SDIOACNW

#define MXC_F_RPU_SPI0_SDIOACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNW_POS))

SPI0_SDIOACNW Mask

◆ MXC_F_RPU_SPI0_SDIOACNW_POS

#define MXC_F_RPU_SPI0_SDIOACNW_POS   17

SPI0_SDIOACNW Position

◆ MXC_F_RPU_SPI0_SDMADACNR

#define MXC_F_RPU_SPI0_SDMADACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNR_POS))

SPI0_SDMADACNR Mask

◆ MXC_F_RPU_SPI0_SDMADACNR_POS

#define MXC_F_RPU_SPI0_SDMADACNR_POS   10

SPI0_SDMADACNR Position

◆ MXC_F_RPU_SPI0_SDMADACNW

#define MXC_F_RPU_SPI0_SDMADACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNW_POS))

SPI0_SDMADACNW Mask

◆ MXC_F_RPU_SPI0_SDMADACNW_POS

#define MXC_F_RPU_SPI0_SDMADACNW_POS   11

SPI0_SDMADACNW Position

◆ MXC_F_RPU_SPI0_SDMAIACNR

#define MXC_F_RPU_SPI0_SDMAIACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNR_POS))

SPI0_SDMAIACNR Mask

◆ MXC_F_RPU_SPI0_SDMAIACNR_POS

#define MXC_F_RPU_SPI0_SDMAIACNR_POS   12

SPI0_SDMAIACNR Position

◆ MXC_F_RPU_SPI0_SDMAIACNW

#define MXC_F_RPU_SPI0_SDMAIACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNW_POS))

SPI0_SDMAIACNW Mask

◆ MXC_F_RPU_SPI0_SDMAIACNW_POS

#define MXC_F_RPU_SPI0_SDMAIACNW_POS   13

SPI0_SDMAIACNW Position

◆ MXC_F_RPU_SPI0_SYS0ACNR

#define MXC_F_RPU_SPI0_SYS0ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNR_POS))

SPI0_SYS0ACNR Mask

◆ MXC_F_RPU_SPI0_SYS0ACNR_POS

#define MXC_F_RPU_SPI0_SYS0ACNR_POS   6

SPI0_SYS0ACNR Position

◆ MXC_F_RPU_SPI0_SYS0ACNW

#define MXC_F_RPU_SPI0_SYS0ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNW_POS))

SPI0_SYS0ACNW Mask

◆ MXC_F_RPU_SPI0_SYS0ACNW_POS

#define MXC_F_RPU_SPI0_SYS0ACNW_POS   7

SPI0_SYS0ACNW Position

◆ MXC_F_RPU_SPI0_SYS1ACNR

#define MXC_F_RPU_SPI0_SYS1ACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNR_POS))

SPI0_SYS1ACNR Mask

◆ MXC_F_RPU_SPI0_SYS1ACNR_POS

#define MXC_F_RPU_SPI0_SYS1ACNR_POS   8

SPI0_SYS1ACNR Position

◆ MXC_F_RPU_SPI0_SYS1ACNW

#define MXC_F_RPU_SPI0_SYS1ACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNW_POS))

SPI0_SYS1ACNW Mask

◆ MXC_F_RPU_SPI0_SYS1ACNW_POS

#define MXC_F_RPU_SPI0_SYS1ACNW_POS   9

SPI0_SYS1ACNW Position

◆ MXC_F_RPU_SPI0_USBACNR

#define MXC_F_RPU_SPI0_USBACNR   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNR_POS))

SPI0_USBACNR Mask

◆ MXC_F_RPU_SPI0_USBACNR_POS

#define MXC_F_RPU_SPI0_USBACNR_POS   4

SPI0_USBACNR Position

◆ MXC_F_RPU_SPI0_USBACNW

#define MXC_F_RPU_SPI0_USBACNW   ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNW_POS))

SPI0_USBACNW Mask

◆ MXC_F_RPU_SPI0_USBACNW_POS

#define MXC_F_RPU_SPI0_USBACNW_POS   5

SPI0_USBACNW Position