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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Reset.
#define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) |
RST0_ADC Mask
#define MXC_F_GCR_RST0_ADC_POS 26 |
RST0_ADC Position
#define MXC_F_GCR_RST0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CRYPTO_POS)) |
RST0_CRYPTO Mask
#define MXC_F_GCR_RST0_CRYPTO_POS 18 |
RST0_CRYPTO Position
#define MXC_F_GCR_RST0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA0_POS)) |
RST0_DMA0 Mask
#define MXC_F_GCR_RST0_DMA0_POS 0 |
RST0_DMA0 Position
#define MXC_F_GCR_RST0_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA1_POS)) |
RST0_DMA1 Mask
#define MXC_F_GCR_RST0_DMA1_POS 27 |
RST0_DMA1 Position
#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) |
RST0_GPIO0 Mask
#define MXC_F_GCR_RST0_GPIO0_POS 2 |
RST0_GPIO0 Position
#define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) |
RST0_GPIO1 Mask
#define MXC_F_GCR_RST0_GPIO1_POS 3 |
RST0_GPIO1 Position
#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) |
RST0_I2C0 Mask
#define MXC_F_GCR_RST0_I2C0_POS 16 |
RST0_I2C0 Position
#define MXC_F_GCR_RST0_PERIPH_RST ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_RST_POS)) |
RST0_PERIPH_RST Mask
#define MXC_F_GCR_RST0_PERIPH_RST_POS 30 |
RST0_PERIPH_RST Position
#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) |
RST0_RTC Mask
#define MXC_F_GCR_RST0_RTC_POS 17 |
RST0_RTC Position
#define MXC_F_GCR_RST0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SMPHR_POS)) |
RST0_SMPHR Mask
#define MXC_F_GCR_RST0_SMPHR_POS 22 |
RST0_SMPHR Position
#define MXC_F_GCR_RST0_SOFT_RST ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_RST_POS)) |
RST0_SOFT_RST Mask
#define MXC_F_GCR_RST0_SOFT_RST_POS 29 |
RST0_SOFT_RST Position
#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) |
RST0_SPI1 Mask
#define MXC_F_GCR_RST0_SPI1_POS 13 |
RST0_SPI1 Position
#define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) |
RST0_SPI2 Mask
#define MXC_F_GCR_RST0_SPI2_POS 14 |
RST0_SPI2 Position
#define MXC_F_GCR_RST0_SYS_RST ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_RST_POS)) |
RST0_SYS_RST Mask
#define MXC_F_GCR_RST0_SYS_RST_POS 31 |
RST0_SYS_RST Position
#define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) |
RST0_TIMER0 Mask
#define MXC_F_GCR_RST0_TIMER0_POS 5 |
RST0_TIMER0 Position
#define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) |
RST0_TIMER1 Mask
#define MXC_F_GCR_RST0_TIMER1_POS 6 |
RST0_TIMER1 Position
#define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) |
RST0_TIMER2 Mask
#define MXC_F_GCR_RST0_TIMER2_POS 7 |
RST0_TIMER2 Position
#define MXC_F_GCR_RST0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER3_POS)) |
RST0_TIMER3 Mask
#define MXC_F_GCR_RST0_TIMER3_POS 8 |
RST0_TIMER3 Position
#define MXC_F_GCR_RST0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER4_POS)) |
RST0_TIMER4 Mask
#define MXC_F_GCR_RST0_TIMER4_POS 9 |
RST0_TIMER4 Position
#define MXC_F_GCR_RST0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER5_POS)) |
RST0_TIMER5 Mask
#define MXC_F_GCR_RST0_TIMER5_POS 10 |
RST0_TIMER5 Position
#define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) |
RST0_TRNG Mask
#define MXC_F_GCR_RST0_TRNG_POS 24 |
RST0_TRNG Position
#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) |
RST0_UART0 Mask
#define MXC_F_GCR_RST0_UART0_POS 11 |
RST0_UART0 Position
#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) |
RST0_UART1 Mask
#define MXC_F_GCR_RST0_UART1_POS 12 |
RST0_UART1 Position
#define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) |
RST0_UART2 Mask
#define MXC_F_GCR_RST0_UART2_POS 28 |
RST0_UART2 Position
#define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) |
RST0_USB Mask
#define MXC_F_GCR_RST0_USB_POS 23 |
RST0_USB Position
#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) |
RST0_WDT0 Mask
#define MXC_F_GCR_RST0_WDT0_POS 1 |
RST0_WDT0 Position