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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros | |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS 0 |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCI2C0 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS)) |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS 1 |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCI2C1 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS)) |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS 2 |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCI2C2 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS)) |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS 3 |
#define | MXC_F_GCR_APB_ASYNC_APBASYNCPT ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS)) |
APB Asynchronous Bridge Select Register.
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS)) |
APB_ASYNC_APBASYNCI2C0 Mask
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS 0 |
APB_ASYNC_APBASYNCI2C0 Position
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS)) |
APB_ASYNC_APBASYNCI2C1 Mask
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS 1 |
APB_ASYNC_APBASYNCI2C1 Position
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS)) |
APB_ASYNC_APBASYNCI2C2 Mask
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS 2 |
APB_ASYNC_APBASYNCI2C2 Position
#define MXC_F_GCR_APB_ASYNC_APBASYNCPT ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS)) |
APB_ASYNC_APBASYNCPT Mask
#define MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS 3 |
APB_ASYNC_APBASYNCPT Position