MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665

Macros

#define MXC_F_RPU_HTIMER1_DMA0ACN_POS   0
 
#define MXC_F_RPU_HTIMER1_DMA0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_DMA0ACN_POS))
 
#define MXC_F_RPU_HTIMER1_DMA1ACN_POS   1
 
#define MXC_F_RPU_HTIMER1_DMA1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_DMA1ACN_POS))
 
#define MXC_F_RPU_HTIMER1_USBACN_POS   2
 
#define MXC_F_RPU_HTIMER1_USBACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_USBACN_POS))
 
#define MXC_F_RPU_HTIMER1_SYS0ACN_POS   3
 
#define MXC_F_RPU_HTIMER1_SYS0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SYS0ACN_POS))
 
#define MXC_F_RPU_HTIMER1_SYS1ACN_POS   4
 
#define MXC_F_RPU_HTIMER1_SYS1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SYS1ACN_POS))
 
#define MXC_F_RPU_HTIMER1_SDMADACN_POS   5
 
#define MXC_F_RPU_HTIMER1_SDMADACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDMADACN_POS))
 
#define MXC_F_RPU_HTIMER1_SDMAIACN_POS   6
 
#define MXC_F_RPU_HTIMER1_SDMAIACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDMAIACN_POS))
 
#define MXC_F_RPU_HTIMER1_CRYPTOACN_POS   7
 
#define MXC_F_RPU_HTIMER1_CRYPTOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_CRYPTOACN_POS))
 
#define MXC_F_RPU_HTIMER1_SDIOACN_POS   8
 
#define MXC_F_RPU_HTIMER1_SDIOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDIOACN_POS))
 

Detailed Description

HTimer1 Protection Register.

Macro Definition Documentation

◆ MXC_F_RPU_HTIMER1_CRYPTOACN

#define MXC_F_RPU_HTIMER1_CRYPTOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_CRYPTOACN_POS))

HTIMER1_CRYPTOACN Mask

◆ MXC_F_RPU_HTIMER1_CRYPTOACN_POS

#define MXC_F_RPU_HTIMER1_CRYPTOACN_POS   7

HTIMER1_CRYPTOACN Position

◆ MXC_F_RPU_HTIMER1_DMA0ACN

#define MXC_F_RPU_HTIMER1_DMA0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_DMA0ACN_POS))

HTIMER1_DMA0ACN Mask

◆ MXC_F_RPU_HTIMER1_DMA0ACN_POS

#define MXC_F_RPU_HTIMER1_DMA0ACN_POS   0

HTIMER1_DMA0ACN Position

◆ MXC_F_RPU_HTIMER1_DMA1ACN

#define MXC_F_RPU_HTIMER1_DMA1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_DMA1ACN_POS))

HTIMER1_DMA1ACN Mask

◆ MXC_F_RPU_HTIMER1_DMA1ACN_POS

#define MXC_F_RPU_HTIMER1_DMA1ACN_POS   1

HTIMER1_DMA1ACN Position

◆ MXC_F_RPU_HTIMER1_SDIOACN

#define MXC_F_RPU_HTIMER1_SDIOACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDIOACN_POS))

HTIMER1_SDIOACN Mask

◆ MXC_F_RPU_HTIMER1_SDIOACN_POS

#define MXC_F_RPU_HTIMER1_SDIOACN_POS   8

HTIMER1_SDIOACN Position

◆ MXC_F_RPU_HTIMER1_SDMADACN

#define MXC_F_RPU_HTIMER1_SDMADACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDMADACN_POS))

HTIMER1_SDMADACN Mask

◆ MXC_F_RPU_HTIMER1_SDMADACN_POS

#define MXC_F_RPU_HTIMER1_SDMADACN_POS   5

HTIMER1_SDMADACN Position

◆ MXC_F_RPU_HTIMER1_SDMAIACN

#define MXC_F_RPU_HTIMER1_SDMAIACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SDMAIACN_POS))

HTIMER1_SDMAIACN Mask

◆ MXC_F_RPU_HTIMER1_SDMAIACN_POS

#define MXC_F_RPU_HTIMER1_SDMAIACN_POS   6

HTIMER1_SDMAIACN Position

◆ MXC_F_RPU_HTIMER1_SYS0ACN

#define MXC_F_RPU_HTIMER1_SYS0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SYS0ACN_POS))

HTIMER1_SYS0ACN Mask

◆ MXC_F_RPU_HTIMER1_SYS0ACN_POS

#define MXC_F_RPU_HTIMER1_SYS0ACN_POS   3

HTIMER1_SYS0ACN Position

◆ MXC_F_RPU_HTIMER1_SYS1ACN

#define MXC_F_RPU_HTIMER1_SYS1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_SYS1ACN_POS))

HTIMER1_SYS1ACN Mask

◆ MXC_F_RPU_HTIMER1_SYS1ACN_POS

#define MXC_F_RPU_HTIMER1_SYS1ACN_POS   4

HTIMER1_SYS1ACN Position

◆ MXC_F_RPU_HTIMER1_USBACN

#define MXC_F_RPU_HTIMER1_USBACN   ((uint32_t)(0x1UL << MXC_F_RPU_HTIMER1_USBACN_POS))

HTIMER1_USBACN Mask

◆ MXC_F_RPU_HTIMER1_USBACN_POS

#define MXC_F_RPU_HTIMER1_USBACN_POS   2

HTIMER1_USBACN Position