![]() |
MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
|
QSPI2 Protection Register.
#define MXC_F_RPU_SPI2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_CRYPTOACN_POS)) |
SPI2_CRYPTOACN Mask
#define MXC_F_RPU_SPI2_CRYPTOACN_POS 7 |
SPI2_CRYPTOACN Position
#define MXC_F_RPU_SPI2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_DMA0ACN_POS)) |
SPI2_DMA0ACN Mask
#define MXC_F_RPU_SPI2_DMA0ACN_POS 0 |
SPI2_DMA0ACN Position
#define MXC_F_RPU_SPI2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_DMA1ACN_POS)) |
SPI2_DMA1ACN Mask
#define MXC_F_RPU_SPI2_DMA1ACN_POS 1 |
SPI2_DMA1ACN Position
#define MXC_F_RPU_SPI2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDIOACN_POS)) |
SPI2_SDIOACN Mask
#define MXC_F_RPU_SPI2_SDIOACN_POS 8 |
SPI2_SDIOACN Position
#define MXC_F_RPU_SPI2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDMADACN_POS)) |
SPI2_SDMADACN Mask
#define MXC_F_RPU_SPI2_SDMADACN_POS 5 |
SPI2_SDMADACN Position
#define MXC_F_RPU_SPI2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDMAIACN_POS)) |
SPI2_SDMAIACN Mask
#define MXC_F_RPU_SPI2_SDMAIACN_POS 6 |
SPI2_SDMAIACN Position
#define MXC_F_RPU_SPI2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SYS0ACN_POS)) |
SPI2_SYS0ACN Mask
#define MXC_F_RPU_SPI2_SYS0ACN_POS 3 |
SPI2_SYS0ACN Position
#define MXC_F_RPU_SPI2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SYS1ACN_POS)) |
SPI2_SYS1ACN Mask
#define MXC_F_RPU_SPI2_SYS1ACN_POS 4 |
SPI2_SYS1ACN Position
#define MXC_F_RPU_SPI2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_USBACN_POS)) |
SPI2_USBACN Mask
#define MXC_F_RPU_SPI2_USBACN_POS 2 |
SPI2_USBACN Position