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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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TMR5 Protection Register.
#define MXC_F_RPU_TMR5_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_CRYPTOACN_POS)) |
TMR5_CRYPTOACN Mask
#define MXC_F_RPU_TMR5_CRYPTOACN_POS 7 |
TMR5_CRYPTOACN Position
#define MXC_F_RPU_TMR5_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_DMA0ACN_POS)) |
TMR5_DMA0ACN Mask
#define MXC_F_RPU_TMR5_DMA0ACN_POS 0 |
TMR5_DMA0ACN Position
#define MXC_F_RPU_TMR5_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_DMA1ACN_POS)) |
TMR5_DMA1ACN Mask
#define MXC_F_RPU_TMR5_DMA1ACN_POS 1 |
TMR5_DMA1ACN Position
#define MXC_F_RPU_TMR5_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SDIOACN_POS)) |
TMR5_SDIOACN Mask
#define MXC_F_RPU_TMR5_SDIOACN_POS 8 |
TMR5_SDIOACN Position
#define MXC_F_RPU_TMR5_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SDMADACN_POS)) |
TMR5_SDMADACN Mask
#define MXC_F_RPU_TMR5_SDMADACN_POS 5 |
TMR5_SDMADACN Position
#define MXC_F_RPU_TMR5_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SDMAIACN_POS)) |
TMR5_SDMAIACN Mask
#define MXC_F_RPU_TMR5_SDMAIACN_POS 6 |
TMR5_SDMAIACN Position
#define MXC_F_RPU_TMR5_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SYS0ACN_POS)) |
TMR5_SYS0ACN Mask
#define MXC_F_RPU_TMR5_SYS0ACN_POS 3 |
TMR5_SYS0ACN Position
#define MXC_F_RPU_TMR5_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_SYS1ACN_POS)) |
TMR5_SYS1ACN Mask
#define MXC_F_RPU_TMR5_SYS1ACN_POS 4 |
TMR5_SYS1ACN Position
#define MXC_F_RPU_TMR5_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR5_USBACN_POS)) |
TMR5_USBACN Mask
#define MXC_F_RPU_TMR5_USBACN_POS 2 |
TMR5_USBACN Position