MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
USBHS_OUTCSRL

Macros

#define MXC_F_USBHS_OUTCSRL_CLRDATATOG_POS   7
 
#define MXC_F_USBHS_OUTCSRL_CLRDATATOG   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_CLRDATATOG_POS))
 
#define MXC_F_USBHS_OUTCSRL_SENTSTALL_POS   6
 
#define MXC_F_USBHS_OUTCSRL_SENTSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_SENTSTALL_POS))
 
#define MXC_F_USBHS_OUTCSRL_SENDSTALL_POS   5
 
#define MXC_F_USBHS_OUTCSRL_SENDSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_SENDSTALL_POS))
 
#define MXC_F_USBHS_OUTCSRL_FLUSHFIFO_POS   4
 
#define MXC_F_USBHS_OUTCSRL_FLUSHFIFO   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_FLUSHFIFO_POS))
 
#define MXC_F_USBHS_OUTCSRL_DATAERROR_POS   3
 
#define MXC_F_USBHS_OUTCSRL_DATAERROR   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_DATAERROR_POS))
 
#define MXC_F_USBHS_OUTCSRL_OVERRUN_POS   2
 
#define MXC_F_USBHS_OUTCSRL_OVERRUN   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_OVERRUN_POS))
 
#define MXC_F_USBHS_OUTCSRL_FIFOFULL_POS   1
 
#define MXC_F_USBHS_OUTCSRL_FIFOFULL   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_FIFOFULL_POS))
 
#define MXC_F_USBHS_OUTCSRL_OUTPKTRDY_POS   0
 
#define MXC_F_USBHS_OUTCSRL_OUTPKTRDY   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_OUTPKTRDY_POS))
 

Detailed Description

Control status lower register for OUTx endpoint (x == INDEX).

Macro Definition Documentation

◆ MXC_F_USBHS_OUTCSRL_CLRDATATOG

#define MXC_F_USBHS_OUTCSRL_CLRDATATOG   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_CLRDATATOG_POS))

OUTCSRL_CLRDATATOG Mask

◆ MXC_F_USBHS_OUTCSRL_CLRDATATOG_POS

#define MXC_F_USBHS_OUTCSRL_CLRDATATOG_POS   7

OUTCSRL_CLRDATATOG Position

◆ MXC_F_USBHS_OUTCSRL_DATAERROR

#define MXC_F_USBHS_OUTCSRL_DATAERROR   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_DATAERROR_POS))

OUTCSRL_DATAERROR Mask

◆ MXC_F_USBHS_OUTCSRL_DATAERROR_POS

#define MXC_F_USBHS_OUTCSRL_DATAERROR_POS   3

OUTCSRL_DATAERROR Position

◆ MXC_F_USBHS_OUTCSRL_FIFOFULL

#define MXC_F_USBHS_OUTCSRL_FIFOFULL   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_FIFOFULL_POS))

OUTCSRL_FIFOFULL Mask

◆ MXC_F_USBHS_OUTCSRL_FIFOFULL_POS

#define MXC_F_USBHS_OUTCSRL_FIFOFULL_POS   1

OUTCSRL_FIFOFULL Position

◆ MXC_F_USBHS_OUTCSRL_FLUSHFIFO

#define MXC_F_USBHS_OUTCSRL_FLUSHFIFO   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_FLUSHFIFO_POS))

OUTCSRL_FLUSHFIFO Mask

◆ MXC_F_USBHS_OUTCSRL_FLUSHFIFO_POS

#define MXC_F_USBHS_OUTCSRL_FLUSHFIFO_POS   4

OUTCSRL_FLUSHFIFO Position

◆ MXC_F_USBHS_OUTCSRL_OUTPKTRDY

#define MXC_F_USBHS_OUTCSRL_OUTPKTRDY   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_OUTPKTRDY_POS))

OUTCSRL_OUTPKTRDY Mask

◆ MXC_F_USBHS_OUTCSRL_OUTPKTRDY_POS

#define MXC_F_USBHS_OUTCSRL_OUTPKTRDY_POS   0

OUTCSRL_OUTPKTRDY Position

◆ MXC_F_USBHS_OUTCSRL_OVERRUN

#define MXC_F_USBHS_OUTCSRL_OVERRUN   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_OVERRUN_POS))

OUTCSRL_OVERRUN Mask

◆ MXC_F_USBHS_OUTCSRL_OVERRUN_POS

#define MXC_F_USBHS_OUTCSRL_OVERRUN_POS   2

OUTCSRL_OVERRUN Position

◆ MXC_F_USBHS_OUTCSRL_SENDSTALL

#define MXC_F_USBHS_OUTCSRL_SENDSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_SENDSTALL_POS))

OUTCSRL_SENDSTALL Mask

◆ MXC_F_USBHS_OUTCSRL_SENDSTALL_POS

#define MXC_F_USBHS_OUTCSRL_SENDSTALL_POS   5

OUTCSRL_SENDSTALL Position

◆ MXC_F_USBHS_OUTCSRL_SENTSTALL

#define MXC_F_USBHS_OUTCSRL_SENTSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_SENTSTALL_POS))

OUTCSRL_SENTSTALL Mask

◆ MXC_F_USBHS_OUTCSRL_SENTSTALL_POS

#define MXC_F_USBHS_OUTCSRL_SENTSTALL_POS   6

OUTCSRL_SENTSTALL Position