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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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TMR1 Protection Register.
#define MXC_F_RPU_TMR1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_CRYPTOACN_POS)) |
TMR1_CRYPTOACN Mask
#define MXC_F_RPU_TMR1_CRYPTOACN_POS 7 |
TMR1_CRYPTOACN Position
#define MXC_F_RPU_TMR1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_DMA0ACN_POS)) |
TMR1_DMA0ACN Mask
#define MXC_F_RPU_TMR1_DMA0ACN_POS 0 |
TMR1_DMA0ACN Position
#define MXC_F_RPU_TMR1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_DMA1ACN_POS)) |
TMR1_DMA1ACN Mask
#define MXC_F_RPU_TMR1_DMA1ACN_POS 1 |
TMR1_DMA1ACN Position
#define MXC_F_RPU_TMR1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SDIOACN_POS)) |
TMR1_SDIOACN Mask
#define MXC_F_RPU_TMR1_SDIOACN_POS 8 |
TMR1_SDIOACN Position
#define MXC_F_RPU_TMR1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SDMADACN_POS)) |
TMR1_SDMADACN Mask
#define MXC_F_RPU_TMR1_SDMADACN_POS 5 |
TMR1_SDMADACN Position
#define MXC_F_RPU_TMR1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SDMAIACN_POS)) |
TMR1_SDMAIACN Mask
#define MXC_F_RPU_TMR1_SDMAIACN_POS 6 |
TMR1_SDMAIACN Position
#define MXC_F_RPU_TMR1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SYS0ACN_POS)) |
TMR1_SYS0ACN Mask
#define MXC_F_RPU_TMR1_SYS0ACN_POS 3 |
TMR1_SYS0ACN Position
#define MXC_F_RPU_TMR1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_SYS1ACN_POS)) |
TMR1_SYS1ACN Mask
#define MXC_F_RPU_TMR1_SYS1ACN_POS 4 |
TMR1_SYS1ACN Position
#define MXC_F_RPU_TMR1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_TMR1_USBACN_POS)) |
TMR1_USBACN Mask
#define MXC_F_RPU_TMR1_USBACN_POS 2 |
TMR1_USBACN Position