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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros | |
#define | MXC_F_SPI_CLK_CFG_LO_POS 0 |
#define | MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) |
#define | MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) |
#define | MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) |
#define | MXC_F_SPI_CLK_CFG_HI_POS 8 |
#define | MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) |
#define | MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) |
#define | MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) |
#define | MXC_F_SPI_CLK_CFG_SCALE_POS 16 |
#define | MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) |
Register for controlling SPI clock rate.
#define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) |
CLK_CFG_HI Mask
#define MXC_F_SPI_CLK_CFG_HI_POS 8 |
CLK_CFG_HI Position
#define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) |
CLK_CFG_LO Mask
#define MXC_F_SPI_CLK_CFG_LO_POS 0 |
CLK_CFG_LO Position
#define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) |
CLK_CFG_SCALE Mask
#define MXC_F_SPI_CLK_CFG_SCALE_POS 16 |
CLK_CFG_SCALE Position
#define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) |
CLK_CFG_HI_DIS Setting
#define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) |
CLK_CFG_LO_DIS Setting
#define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) |
CLK_CFG_HI_DIS Value
#define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) |
CLK_CFG_LO_DIS Value