MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
max32665.h
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/*******************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2020-01-16 11:18:21 -0600 (Thu, 16 Jan 2020) $
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* $Revision: 50703 $
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*
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******************************************************************************/
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#ifndef _MAX32665_REGS_H_
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#define _MAX32665_REGS_H_
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#ifndef TARGET_NUM
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#define TARGET_NUM 32665
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#endif
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#define MXC_NUMCORES 2
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#include <stdint.h>
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#ifndef FALSE
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#define FALSE (0)
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#endif
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#ifndef TRUE
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#define TRUE (1)
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#endif
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#if !defined ( __GNUC__ )
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#define CMSIS_VECTAB_VIRTUAL
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#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
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#endif
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/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
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#if defined ( __GNUC__ )
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#define __weak __attribute__((weak))
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#elif defined ( __CC_ARM)
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#define inline __inline
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#pragma anon_unions
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#endif
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typedef
enum
{
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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/* Device-specific interrupt sources (external to ARM core) */
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/* table entry number */
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/* |||| */
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/* |||| table offset address */
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/* vvvv vvvvvv */
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PF_IRQn = 0,
/* 0x10 0x0040 16: Power Fail */
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WDT0_IRQn,
/* 0x11 0x0044 17: Watchdog 0 */
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USB_IRQn,
/* 0x12 0x0048 18: USB */
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RTC_IRQn,
/* 0x13 0x004C 19: RTC */
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TRNG_IRQn,
/* 0x14 0x0050 20: True Random Number Generator */
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TMR0_IRQn,
/* 0x15 0x0054 21: Timer 0 */
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TMR1_IRQn,
/* 0x16 0x0058 22: Timer 1 */
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TMR2_IRQn,
/* 0x17 0x005C 23: Timer 2 */
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TMR3_IRQn,
/* 0x18 0x0060 24: Timer 3*/
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TMR4_IRQn,
/* 0x19 0x0064 25: Timer 4*/
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TMR5_IRQn,
/* 0x1A 0x0068 26: Timer 5 */
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RSV11_IRQn,
/* 0x1B 0x006C 27: Reserved */
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RSV12_IRQn,
/* 0x1C 0x0070 28: Reserved */
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I2C0_IRQn,
/* 0x1D 0x0074 29: I2C0 */
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UART0_IRQn,
/* 0x1E 0x0078 30: UART 0 */
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UART1_IRQn,
/* 0x1F 0x007C 31: UART 1 */
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SPI1_IRQn,
/* 0x20 0x0080 32: SPI1 */
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SPI2_IRQn,
/* 0x21 0x0084 33: SPI2 */
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RSV18_IRQn,
/* 0x22 0x0088 34: Reserved */
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RSV19_IRQn,
/* 0x23 0x008C 35: Reserved */
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ADC_IRQn,
/* 0x24 0x0090 36: ADC */
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RSV21_IRQn,
/* 0x25 0x0094 37: Reserved */
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RSV22_IRQn,
/* 0x26 0x0098 38: Reserved */
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FLC0_IRQn,
/* 0x27 0x009C 39: Flash Controller 0 */
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GPIO0_IRQn,
/* 0x28 0x00A0 40: GPIO0 */
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GPIO1_IRQn,
/* 0x29 0x00A4 41: GPIO1 */
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RSV26_IRQn,
/* 0x2A 0x00A8 42: Reserved */
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TPU_IRQn,
/* 0x2B 0x00AC 43: Crypto */
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DMA0_IRQn,
/* 0x2C 0x00B0 44: DMA0 */
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DMA1_IRQn,
/* 0x2D 0x00B4 45: DMA1 */
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DMA2_IRQn,
/* 0x2E 0x00B8 46: DMA2 */
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DMA3_IRQn,
/* 0x2F 0x00BC 47: DMA3 */
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RSV32_IRQn,
/* 0x30 0x00C0 48: Reserved */
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RSV33_IRQn,
/* 0x31 0x00C4 49: Reserved */
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UART2_IRQn,
/* 0x32 0x00C8 50: UART 2 */
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RSV35_IRQn,
/* 0x33 0x00CC 51: Reserved */
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I2C1_IRQn,
/* 0x34 0x00D0 52: I2C1 */
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RSV36_IRQn,
/* 0x35 0x00D4 53: Reserved */
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SPIXFC_IRQn,
/* 0x36 0x00D8 54: SPI execute in place */
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BTLE_TX_DONE_IRQn,
/* 0x37 0x00DC 55: BTLE TX Done */
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BTLE_RX_RCVD_IRQn,
/* 0x38 0x00E0 56: BTLE RX Received */
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BTLE_RX_ENG_DET_IRQn,
/* 0x39 0x00E4 57: BTLE RX Energy Detected */
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BTLE_SFD_DET_IRQn,
/* 0x3A 0x00E8 58: BTLE SFD Detected */
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BTLE_SFD_TO_IRQn,
/* 0x3B 0x00EC 59: BTLE SFD Timeout*/
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BTLE_GP_EVENT_IRQn,
/* 0x3C 0x00F0 60: BTLE Timestamp*/
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BTLE_CFO_IRQn,
/* 0x3D 0x00F4 61: BTLE CFO Done */
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BTLE_SIG_DET_IRQn,
/* 0x3E 0x00F8 62: BTLE Signal Detected */
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BTLE_AGC_EVENT_IRQn,
/* 0x3F 0x00FC 63: BTLE AGC Event */
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BTLE_RFFE_SPIM_IRQn,
/* 0x40 0x0100 64: BTLE RFFE SPIM Done */
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BTLE_TX_AES_IRQn,
/* 0x41 0x0104 65: BTLE TX AES Done */
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BTLE_RX_AES_IRQn,
/* 0x42 0x0108 66: BTLE RX AES Done */
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BTLE_INV_APB_ADDR_IRQn,
/* 0x43 0x010C 67: BTLE Invalid APB Address*/
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BTLE_IQ_DATA_VALID_IRQn,
/* 0x44 0x0110 68: BTLE IQ Data Valid */
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WUT_IRQn,
/* 0x45 0x0114 69: WUT Wakeup */
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GPIOWAKE_IRQn,
/* 0x46 0x0118 70: GPIO Wakeup */
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RSV55_IRQn,
/* 0x47 0x011C 71: Reserved */
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SPI0_IRQn,
/* 0x48 0x0120 72: SPI0 AHB*/
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WDT1_IRQn,
/* 0x49 0x0124 73: Watchdog 1 */
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RSV58_IRQn,
/* 0x4A 0x0128 74: Reserved */
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PT_IRQn,
/* 0x4B 0x012C 75: Pulse train */
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SDMA_IRQn,
/* 0x4C 0x0130 76: Smart DMA 0 */
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RSV61_IRQn,
/* 0x4D 0x0134 77: Reserved */
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I2C2_IRQn,
/* 0x4E 0x0138 78: I2C 2 */
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RSV63_IRQn,
/* 0x4F 0x013C 79: Reserved */
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RSV64_IRQn,
/* 0x50 0x0140 80: Reserved */
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RSV65_IRQn,
/* 0x51 0x0144 81: Reserved */
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SDHC_IRQn,
/* 0x52 0x0148 82: SDIO/SDHC */
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OWM_IRQn,
/* 0x53 0x014C 83: One Wire Master */
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DMA4_IRQn,
/* 0x54 0x0150 84: DMA4 */
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DMA5_IRQn,
/* 0x55 0x0154 85: DMA5 */
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DMA6_IRQn,
/* 0x56 0x0158 86: DMA6 */
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DMA7_IRQn,
/* 0x57 0x015C 87: DMA7 */
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DMA8_IRQn,
/* 0x58 0x0160 88: DMA8 */
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DMA9_IRQn,
/* 0x59 0x0164 89: DMA9 */
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DMA10_IRQn,
/* 0x5A 0x0168 90: DMA10 */
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DMA11_IRQn,
/* 0x5B 0x016C 91: DMA11 */
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DMA12_IRQn,
/* 0x5C 0x0170 92: DMA12 */
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DMA13_IRQn,
/* 0x5D 0x0174 93: DMA13 */
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DMA14_IRQn,
/* 0x5E 0x0178 94: DMA14 */
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DMA15_IRQn,
/* 0x5F 0x017C 95: DMA15 */
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USBDMA_IRQn,
/* 0x60 0x0180 96: USB DMA */
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WDT2_IRQn,
/* 0x61 0x0184 97: Watchdog Timer 2 */
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ECC_IRQn,
/* 0x62 0x0188 98: Error Correction */
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DVS_IRQn,
/* 0x63 0x018C 99: DVS Controller */
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SIMO_IRQn,
/* 0x64 0x0190 100: SIMO Controller */
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SCA_IRQn,
/* 0x65 0x0194 101: SCA */
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AUDIO_IRQn,
/* 0x66 0x0198 102: Audio subsystem */
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FLC1_IRQn,
/* 0x67 0x019C 103: Flash Control 1 */
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UART3_IRQn,
/* 0x68 0x01A0 104: UART 3 */
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UART4_IRQn,
/* 0x69 0x01A4 105: UART 4 */
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UART5_IRQn,
/* 0x6A 0x01A8 106: UART 5 */
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CameraIF_IRQn,
/* 0x6B 0x01AC 107: Camera IF */
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I3C_IRQn,
/* 0x6C 0x01B0 108: I3C */
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HTMR0_IRQn,
/* 0x6D 0x01B4 109: HTimer0 */
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HTMR1_IRQn,
/* 0x6E 0x01B8 110: HTimer1 */
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MXC_IRQ_EXT_COUNT
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} IRQn_Type;
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#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
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#define __CM4_REV 0x0100
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#define __MPU_PRESENT 1
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#define __NVIC_PRIO_BITS 3
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#define __Vendor_SysTickConfig 0
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#define __FPU_PRESENT 1
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#include <core_cm4.h>
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#include "system_max32665.h"
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/* ================================================================================ */
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/* ================== Device Specific Memory Section ================== */
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/* ================================================================================ */
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#define MXC_ROM_MEM_BASE 0x00000000UL
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#define MXC_ROM_MEM_SIZE 0x00020000UL
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#define MXC_XIP_MEM_BASE 0x08000000UL
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#define MXC_XIP_MEM_SIZE 0x08000000UL
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#define MXC_FLASH0_MEM_BASE 0x10000000UL
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#define MXC_FLASH1_MEM_BASE 0x10080000UL
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#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
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#define MXC_FLASH_PAGE_SIZE 0x00002000UL
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#define MXC_FLASH_MEM_SIZE 0x00080000UL
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#define MXC_INFO0_MEM_BASE 0x10800000UL
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#define MXC_INFO1_MEM_BASE 0x10804000UL
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#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
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#define MXC_INFO_MEM_SIZE 0x00004000UL
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#define MXC_SRAM_MEM_BASE 0x20000000UL
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#define MXC_SRAM_MEM_SIZE 0x0008C000UL
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#define MXC_XIP_DATA_MEM_BASE 0x80000000UL
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#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/*
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Base addresses and configuration settings for all MAX32665 peripheral modules.
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*/
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/******************************************************************************/
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/* Global control */
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#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
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#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
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/******************************************************************************/
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/* Non-battery backed SI Registers */
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#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
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#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
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/******************************************************************************/
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/* Non-battery backed Function Control */
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#define MXC_BASE_FCR ((uint32_t)0x40000800UL)
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#define MXC_FCR ((mxc_fcr_regs_t*)MXC_BASE_FCR)
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/******************************************************************************/
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/* Trust Protection Unit */
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#define MXC_BASE_TPU ((uint32_t)0x40001000UL)
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#define MXC_TPU ((mxc_tpu_regs_t*)MXC_BASE_TPU)
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/******************************************************************************/
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/* Watchdog */
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#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
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#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
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#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
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#define MXC_WDT1 ((mxc_wdt_regs_t*)MXC_BASE_WDT1)
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#define MXC_BASE_WDT2 ((uint32_t)0x40003800UL)
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#define MXC_WDT2 ((mxc_wdt_regs_t*)MXC_BASE_WDT2)
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/******************************************************************************/
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/* Security Monitor */
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#define MXC_BASE_SMON ((uint32_t)0x40004000UL)
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#define MXC_SMON ((mxc_smon_regs_t*)MXC_BASE_SMON)
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/******************************************************************************/
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/* SIMO */
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#define MXC_BASE_SIMO ((uint32_t)0x40004400UL)
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#define MXC_SIMO ((mxc_simo_regs_t*)MXC_BASE_SIMO)
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/******************************************************************************/
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/* DVS*/
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#define MXC_BASE_DVS ((uint32_t)0x40004800UL)
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#define MXC_DVS ((mxc_dvs_regs_t*)MXC_BASE_DVS)
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/******************************************************************************/
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/* Security Monitor */
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#define MXC_BASE_SMON ((uint32_t)0x40004000UL)
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#define MXC_SMON ((mxc_smon_regs_t*)MXC_BASE_SMON)
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/******************************************************************************/
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/* Real Time Clock */
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#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
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#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
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/******************************************************************************/
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/* Wakeup Timer */
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#define MXC_BASE_WUT ((uint32_t)0x40006400UL)
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#define MXC_WUT ((mxc_wut_regs_t*)MXC_BASE_WUT)
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/******************************************************************************/
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/* Power Sequencer */
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#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
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#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
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/******************************************************************************/
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/* Power Sequencer */
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#define MXC_BASE_MCR ((uint32_t)0x40006C00UL)
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#define MXC_MCR ((mxc_mcr_regs_t*)MXC_BASE_MCR)
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/******************************************************************************/
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/* GPIO */
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#define MXC_CFG_GPIO_INSTANCES (2)
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#define MXC_CFG_GPIO_PINS_PORT (32)
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#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
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#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
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#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
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#define MXC_GPIO1 ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)
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#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \
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(p) == MXC_GPIO1 ? 1 : -1)
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#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \
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(i) == 1 ? MXC_GPIO1 : 0)
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#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \
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(i) == 1 ? GPIO1_IRQn : (IRQn_Type) 0)
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/******************************************************************************/
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/* Timer */
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#define MXC_CFG_TMR_INSTANCES (6)
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#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
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#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
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#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
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#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
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#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
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#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
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#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
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#define MXC_TMR3 ((mxc_tmr_regs_t*)MXC_BASE_TMR3)
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#define MXC_BASE_TMR4 ((uint32_t)0x40014000UL)
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#define MXC_TMR4 ((mxc_tmr_regs_t*)MXC_BASE_TMR4)
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#define MXC_BASE_TMR5 ((uint32_t)0x40015000UL)
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#define MXC_TMR5 ((mxc_tmr_regs_t*)MXC_BASE_TMR5)
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#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
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(i) == 1 ? TMR1_IRQn : \
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(i) == 2 ? TMR2_IRQn : \
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(i) == 3 ? TMR3_IRQn : \
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(i) == 4 ? TMR4_IRQn : \
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(i) == 5 ? TMR5_IRQn : 0)
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#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
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(i) == 1 ? MXC_BASE_TMR1 : \
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(i) == 2 ? MXC_BASE_TMR2 : \
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(i) == 3 ? MXC_BASE_TMR3 : \
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(i) == 4 ? MXC_BASE_TMR4 : \
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(i) == 5 ? MXC_BASE_TMR5 : 0)
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#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
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(i) == 1 ? MXC_TMR1 : \
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(i) == 2 ? MXC_TMR2 : \
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(i) == 3 ? MXC_TMR3 : \
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(i) == 4 ? MXC_TMR4 : \
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(i) == 5 ? MXC_TMR5 : 0)
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#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
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(p) == MXC_TMR1 ? 1 : \
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(p) == MXC_TMR2 ? 2 : \
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(p) == MXC_TMR3 ? 3 : \
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(p) == MXC_TMR4 ? 4 : \
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(p) == MXC_TMR5 ? 5 : -1)
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/******************************************************************************/
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/* High Speed Timer */
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#define MXC_BASE_HTMR0 ((uint32_t)0x4001B000UL)
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#define MXC_HTMR0 ((mxc_htmr_regs_t*)MXC_BASE_HTMR0)
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#define MXC_BASE_HTMR1 ((uint32_t)0x4001C000UL)
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#define MXC_HTMR1 ((mxc_htmr_regs_t*)MXC_BASE_HTMR1)
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/******************************************************************************/
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/* I2C */
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#define MXC_I2C_INSTANCES (3)
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#define MXC_BASE_I2C0_BUS0 ((uint32_t)0x4001D000UL)
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#define MXC_I2C0_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS0)
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#define MXC_BASE_I2C1_BUS0 ((uint32_t)0x4001E000UL)
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#define MXC_I2C1_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS0)
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#define MXC_BASE_I2C2_BUS0 ((uint32_t)0x4001F000UL)
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#define MXC_I2C2_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS0)
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#define MXC_BASE_I2C0_BUS1 ((uint32_t)0x4011D000UL)
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#define MXC_I2C0_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS1)
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#define MXC_BASE_I2C1_BUS1 ((uint32_t)0x4011E000UL)
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#define MXC_I2C1_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS1)
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#define MXC_BASE_I2C2_BUS1 ((uint32_t)0x4011F000UL)
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#define MXC_I2C2_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS1)
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401
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#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0x0 ? I2C0_IRQn : \
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(i) == 0x1 ? I2C1_IRQn : \
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(i) == 0x2 ? I2C2_IRQn : \
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(i) == 0x8000 ? I2C0_IRQn : \
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(i) == 0x8001 ? I2C1_IRQn : \
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(i) == 0x8002 ? I2C2_IRQn : 0)
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#define MXC_I2C_GET_BASE(i) ((i) == 0x0 ? MXC_BASE_I2C0_BUS0 : \
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(i) == 0x1 ? MXC_BASE_I2C1_BUS0 : \
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(i) == 0x2 ? MXC_BASE_I2C2_BUS0 : \
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(i) == 0x8000 ? MXC_BASE_I2C0_BUS1 : \
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(i) == 0x8001 ? MXC_BASE_I2C1_BUS1 : \
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(i) == 0x8002 ? MXC_BASE_I2C2_BUS1 : 0)
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#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0_BUS0 ? 0x0 : \
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(p) == MXC_I2C1_BUS0 ? 0x1 : \
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(p) == MXC_I2C2_BUS0 ? 0x2 : \
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(p) == MXC_I2C0_BUS1 ? 0x8000 : \
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(p) == MXC_I2C1_BUS1 ? 0x8001 : \
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(p) == MXC_I2C2_BUS1 ? 0x8002 : -1)
422
423
#define MXC_I2C_GET_I2C(p) ((p) == 0x0 ? MXC_I2C0_BUS0 : \
424
(p) == 0x1 ? MXC_I2C1_BUS0 : \
425
(p) == 0x2 ? MXC_I2C2_BUS0 : \
426
(p) == 0x8000 ? MXC_I2C0_BUS1 : \
427
(p) == 0x8001 ? MXC_I2C1_BUS1 : \
428
(p) == 0x8002? MXC_I2C2_BUS1 : 0)
429
#define MXC_I2C_FIFO_DEPTH (8)
430
431
/******************************************************************************/
432
/* SPI Execute in Place */
433
#define MXC_BASE_SPIXFM ((uint32_t)0x40026000UL)
434
#define MXC_SPIXFM ((mxc_spixfm_regs_t*)MXC_BASE_SPIXFM)
435
436
#define MXC_BASE_SPIXFC_FIFO ((uint32_t)0x400BC000UL)
437
#define MXC_SPIXFC_FIFO ((mxc_spixfc_fifo_regs_t*)MXC_BASE_SPIXFC_FIFO)
438
/******************************************************************************/
439
/* SPI Execute in Place Master */
440
441
#define MXC_CFG_SPIXFC_FIFO_DEPTH (16)
442
443
#define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL)
444
#define MXC_SPIXFC ((mxc_spixfc_regs_t*)MXC_BASE_SPIXFC)
445
446
/******************************************************************************/
447
/* DMA */
448
#define MXC_DMA_CHANNELS (16)
449
#define MXC_DMA_INSTANCES (2)
450
451
#define MXC_BASE_DMA0 ((uint32_t)0x40028000UL)
452
#define MXC_DMA0 ((mxc_dma_regs_t*)MXC_BASE_DMA0)
453
#define MXC_BASE_DMA1 ((uint32_t)0x40035000UL)
454
#define MXC_DMA1 ((mxc_dma_regs_t*)MXC_BASE_DMA1)
455
456
// TODO: remove this when creating drivers to accept two instance of these.
457
#define MXC_DMA MXC_DMA0
458
459
#define MXC_DMA_GET_BASE(i) ((i) == 0 ? MXC_BASE_DMA0 : \
460
(i) == 1 ? MXC_BASE_DMA1 : 0)
461
462
#define MXC_DMA_GET_DMA(i) ((i) == 0 ? MXC_DMA0 : \
463
(i) == 1 ? MXC_DMA1 : 0)
464
465
#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : \
466
(p) == MXC_DMA1 ? 1 : -1)
467
/******************************************************************************/
468
/* FLC */
469
#define MXC_FLC_INSTANCES (2)
470
471
#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
472
#define MXC_FLC0 ((mxc_flc_regs_t*)MXC_BASE_FLC0)
473
#define MXC_BASE_FLC1 ((uint32_t)0x40029400UL)
474
#define MXC_FLC1 ((mxc_flc_regs_t*)MXC_BASE_FLC1)
475
476
// TODO: remove this when creating drivers to accept two instance of these.
477
// #define MXC_FLC MXC_FLC0
478
479
480
#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : \
481
(i) == 1 ? FLC1_IRQn :0)
482
483
#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : \
484
(i) == 1 ? MXC_BASE_FLC1 : 0)
485
486
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : \
487
(i) == 1 ? MXC_FLC1 : 0)
488
489
#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : \
490
(p) == MXC_FLC1 ? 1 : -1)
491
/******************************************************************************/
492
/* Instruction Cache */
493
#define MXC_ICC_INSTANCES (2)
494
495
#define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL)
496
#define MXC_ICC0 ((mxc_icc_regs_t*)MXC_BASE_ICC0)
497
#define MXC_BASE_ICC1 ((uint32_t)0x4002F000UL)
498
#define MXC_ICC1 ((mxc_icc_regs_t*)MXC_BASE_ICC1)
499
500
// TODO: remove this when creating drivers to accept two instance of these.
501
#define MXC_ICC MXC_ICC0
502
503
504
#define MXC_ICC_GET_BASE(i) ((i) == 0 ? MXC_BASE_ICC0 : \
505
(i) == 1 ? MXC_BASE_ICC1 : 0)
506
507
#define MXC_ICC_GET_ICC(i) ((i) == 0 ? MXC_ICC0 : \
508
(i) == 1 ? MXC_ICC1 : 0)
509
510
#define MXC_ICC_GET_IDX(p) ((p) == MXC_ICC0 ? 0 : \
511
(p) == MXC_ICC1 ? 1 : -1)
512
/******************************************************************************/
513
/* Instruction Cache XIP */
514
#define MXC_BASE_SFCC ((uint32_t)0x4002F000UL)
515
#define MXC_SFCC ((mxc_icc_regs_t*)MXC_BASE_SFCC)
516
517
/******************************************************************************/
518
/* Data Cache */
519
#define MXC_BASE_SRCC ((uint32_t)0x40033000UL)
520
#define MXC_SRCC ((mxc_srcc_regs_t*)MXC_BASE_SRCC)
521
522
/******************************************************************************/
523
/* ADC */
524
#define MXC_BASE_ADC ((uint32_t)0x40034000UL)
525
#define MXC_ADC ((mxc_adc_regs_t*)MXC_BASE_ADC)
526
#define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz
527
528
/******************************************************************************/
529
/* USB */
530
#define MXC_BASE_USBHS ((uint32_t)0x400B1000UL)
531
#define MXC_USBHS ((mxc_usbhs_regs_t*)MXC_BASE_USBHS)
532
#define MXC_USBHS_NUM_EP 12
/* HW must have at least EP 0 CONTROL + 11 IN/OUT */
533
#define MXC_USBHS_NUM_DMA 8
/* HW must have at least this many DMA channels */
534
#define MXC_USBHS_MAX_PACKET 512
535
536
/******************************************************************************/
537
/* Smart DMA */
538
#define MXC_BASE_SDMA ((uint32_t)0x40036000UL)
539
#define MXC_SDMA ((mxc_sdma_regs_t*)MXC_BASE_SDMA)
540
541
/******************************************************************************/
542
/* SPI XIP Data */
543
#define MXC_BASE_SPIXR ((uint32_t)0x4003A000UL)
544
#define MXC_SPIXR ((mxc_spixr_regs_t*)MXC_BASE_SPIXR)
545
546
/*******************************************************************************/
547
/* Pulse Train Generation */
548
549
#define MXC_CFG_PT_INSTANCES (16)
550
551
#define MXC_BASE_PTG_BUS0 ((uint32_t)0x4003C000UL)
552
#define MXC_PTG_BUS0 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS0)
553
#define MXC_BASE_PT0_BUS0 ((uint32_t)0x4003C020UL)
554
#define MXC_PT0_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS0)
555
#define MXC_BASE_PT1_BUS0 ((uint32_t)0x4003C040UL)
556
#define MXC_PT1_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS0)
557
#define MXC_BASE_PT2_BUS0 ((uint32_t)0x4003C060UL)
558
#define MXC_PT2_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS0)
559
#define MXC_BASE_PT3_BUS0 ((uint32_t)0x4003C080UL)
560
#define MXC_PT3_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS0)
561
#define MXC_BASE_PT4_BUS0 ((uint32_t)0x4003C0A0UL)
562
#define MXC_PT4_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS0)
563
#define MXC_BASE_PT5_BUS0 ((uint32_t)0x4003C0C0UL)
564
#define MXC_PT5_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS0)
565
#define MXC_BASE_PT6_BUS0 ((uint32_t)0x4003C0E0UL)
566
#define MXC_PT6_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS0)
567
#define MXC_BASE_PT7_BUS0 ((uint32_t)0x4003C100UL)
568
#define MXC_PT7_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS0)
569
#define MXC_BASE_PT8_BUS0 ((uint32_t)0x4003C120UL)
570
#define MXC_PT8_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS0)
571
#define MXC_BASE_PT9_BUS0 ((uint32_t)0x4003C140UL)
572
#define MXC_PT9_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS0)
573
#define MXC_BASE_PT10_BUS0 ((uint32_t)0x4003C160UL)
574
#define MXC_PT10_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS0)
575
#define MXC_BASE_PT11_BUS0 ((uint32_t)0x4003C180UL)
576
#define MXC_PT11_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS0)
577
#define MXC_BASE_PT12_BUS0 ((uint32_t)0x4003C1A0UL)
578
#define MXC_PT12_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS0)
579
#define MXC_BASE_PT13_BUS0 ((uint32_t)0x4003C1C0UL)
580
#define MXC_PT13_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS0)
581
#define MXC_BASE_PT14_BUS0 ((uint32_t)0x4003C1E0UL)
582
#define MXC_PT14_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS0)
583
#define MXC_BASE_PT15_BUS0 ((uint32_t)0x4003C200UL)
584
#define MXC_PT15_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS0)
585
586
587
#define MXC_BASE_PTG_BUS1 ((uint32_t)0x4013C000UL)
588
#define MXC_PTG_BUS1 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS1)
589
#define MXC_BASE_PT0_BUS1 ((uint32_t)0x4013C020UL)
590
#define MXC_PT0_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS1)
591
#define MXC_BASE_PT1_BUS1 ((uint32_t)0x4013C040UL)
592
#define MXC_PT1_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS1)
593
#define MXC_BASE_PT2_BUS1 ((uint32_t)0x4013C060UL)
594
#define MXC_PT2_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS1)
595
#define MXC_BASE_PT3_BUS1 ((uint32_t)0x4013C080UL)
596
#define MXC_PT3_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS1)
597
#define MXC_BASE_PT4_BUS1 ((uint32_t)0x4013C0A0UL)
598
#define MXC_PT4_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS1)
599
#define MXC_BASE_PT5_BUS1 ((uint32_t)0x4013C0C0UL)
600
#define MXC_PT5_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS1)
601
#define MXC_BASE_PT6_BUS1 ((uint32_t)0x4013C0E0UL)
602
#define MXC_PT6_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS1)
603
#define MXC_BASE_PT7_BUS1 ((uint32_t)0x4013C100UL)
604
#define MXC_PT7_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS1)
605
#define MXC_BASE_PT8_BUS1 ((uint32_t)0x4013C120UL)
606
#define MXC_PT8_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS1)
607
#define MXC_BASE_PT9_BUS1 ((uint32_t)0x4013C140UL)
608
#define MXC_PT9_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS1)
609
#define MXC_BASE_PT10_BUS1 ((uint32_t)0x4013C160UL)
610
#define MXC_PT10_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS1)
611
#define MXC_BASE_PT11_BUS1 ((uint32_t)0x4013C180UL)
612
#define MXC_PT11_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS1)
613
#define MXC_BASE_PT12_BUS1 ((uint32_t)0x4013C1A0UL)
614
#define MXC_PT12_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS1)
615
#define MXC_BASE_PT13_BUS1 ((uint32_t)0x4013C1C0UL)
616
#define MXC_PT13_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS1)
617
#define MXC_BASE_PT14_BUS1 ((uint32_t)0x4013C1E0UL)
618
#define MXC_PT14_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS1)
619
#define MXC_BASE_PT15_BUS1 ((uint32_t)0x4013C200UL)
620
#define MXC_PT15_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS1)
621
622
#define MXC_PT_GET_BASE(i) ((i) == 0x0 ? MXC_BASE_PT0_BUS0 : \
623
(i) == 0x1 ? MXC_BASE_PT1_BUS0 : \
624
(i) == 0x2 ? MXC_BASE_PT2_BUS0 : \
625
(i) == 0x3 ? MXC_BASE_PT3_BUS0 : \
626
(i) == 0x4 ? MXC_BASE_PT4_BUS0 : \
627
(i) == 0x5 ? MXC_BASE_PT5_BUS0 : \
628
(i) == 0x6 ? MXC_BASE_PT6_BUS0 : \
629
(i) == 0x7 ? MXC_BASE_PT7_BUS0 : \
630
(i) == 0x8 ? MXC_BASE_PT8_BUS0 : \
631
(i) == 0x9 ? MXC_BASE_PT9_BUS0 : \
632
(i) == 0xA ? MXC_BASE_PT10_BUS0 : \
633
(i) == 0xB ? MXC_BASE_PT11_BUS0 : \
634
(i) == 0xC ? MXC_BASE_PT12_BUS0 : \
635
(i) == 0xD ? MXC_BASE_PT13_BUS0 : \
636
(i) == 0xE ? MXC_BASE_PT14_BUS0 : \
637
(i) == 0xF ? MXC_BASE_PT15_BUS0 : \
638
(i) == 0x8000 ? MXC_BASE_PT0_BUS1 : \
639
(i) == 0x8001 ? MXC_BASE_PT1_BUS1 : \
640
(i) == 0x8002 ? MXC_BASE_PT2_BUS1 : \
641
(i) == 0x8003 ? MXC_BASE_PT3_BUS1 : \
642
(i) == 0x8004 ? MXC_BASE_PT4_BUS1 : \
643
(i) == 0x8005 ? MXC_BASE_PT5_BUS1 : \
644
(i) == 0x8006 ? MXC_BASE_PT6_BUS1 : \
645
(i) == 0x8007 ? MXC_BASE_PT7_BUS1 : \
646
(i) == 0x8008 ? MXC_BASE_PT8_BUS1 : \
647
(i) == 0x8009 ? MXC_BASE_PT9_BUS1 : \
648
(i) == 0x800A ? MXC_BASE_PT10_BUS1 : \
649
(i) == 0x800B ? MXC_BASE_PT11_BUS1 : \
650
(i) == 0x800C ? MXC_BASE_PT12_BUS1 : \
651
(i) == 0x800D ? MXC_BASE_PT13_BUS1 : \
652
(i) == 0x800E ? MXC_BASE_PT14_BUS1 : \
653
(i) == 0x800F ? MXC_BASE_PT15_BUS1 : 0)
654
655
#define MXC_PT_GET_PT(i) ((i) == 0x0 ? MXC_PT0_BUS0 : \
656
(i) == 0x1 ? MXC_PT1_BUS0 : \
657
(i) == 0x2 ? MXC_PT2_BUS0 : \
658
(i) == 0x3 ? MXC_PT3_BUS0 : \
659
(i) == 0x4 ? MXC_PT4_BUS0 : \
660
(i) == 0x5 ? MXC_PT5_BUS0 : \
661
(i) == 0x6 ? MXC_PT6_BUS0 : \
662
(i) == 0x7 ? MXC_PT7_BUS0 : \
663
(i) == 0x8 ? MXC_PT8_BUS0 : \
664
(i) == 0x9 ? MXC_PT9_BUS0 : \
665
(i) == 0xA ? MXC_PT10_BUS0 : \
666
(i) == 0xB ? MXC_PT11_BUS0 : \
667
(i) == 0xC ? MXC_PT12_BUS0 : \
668
(i) == 0xD ? MXC_PT13_BUS0 : \
669
(i) == 0xE ? MXC_PT14_BUS0 : \
670
(i) == 0xF ? MXC_PT15_BUS0 : \
671
(i) == 0x8000 ? MXC_PT0_BUS1 : \
672
(i) == 0x8001 ? MXC_PT1_BUS1 : \
673
(i) == 0x8002 ? MXC_PT2_BUS1 : \
674
(i) == 0x8003 ? MXC_PT3_BUS1 : \
675
(i) == 0x8004 ? MXC_PT4_BUS1 : \
676
(i) == 0x8005 ? MXC_PT5_BUS1 : \
677
(i) == 0x8006 ? MXC_PT6_BUS1 : \
678
(i) == 0x8007 ? MXC_PT7_BUS1 : \
679
(i) == 0x8008 ? MXC_PT8_BUS1 : \
680
(i) == 0x8009 ? MXC_PT9_BUS1 : \
681
(i) == 0x800A ? MXC_PT10_BUS1 : \
682
(i) == 0x800B ? MXC_PT11_BUS1 : \
683
(i) == 0x800C ? MXC_PT12_BUS1 : \
684
(i) == 0x800D ? MXC_PT13_BUS1 : \
685
(i) == 0x800E ? MXC_PT14_BUS1 : \
686
(i) == 0x800F ? MXC_PT15_BUS1 : 0)
687
688
#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0_BUS0 ? 0x0 : \
689
(p) == MXC_PT1_BUS0 ? 0x1 : \
690
(p) == MXC_PT2_BUS0 ? 0x2 : \
691
(p) == MXC_PT3_BUS0 ? 0x3 : \
692
(p) == MXC_PT4_BUS0 ? 0x4 : \
693
(p) == MXC_PT5_BUS0 ? 0x5 : \
694
(p) == MXC_PT6_BUS0 ? 0x6 : \
695
(p) == MXC_PT7_BUS0 ? 0x7 : \
696
(p) == MXC_PT8_BUS0 ? 0x8 : \
697
(p) == MXC_PT9_BUS0 ? 0x9 : \
698
(p) == MXC_PT10_BUS0 ? 0xA : \
699
(p) == MXC_PT11_BUS0 ? 0xB : \
700
(p) == MXC_PT12_BUS0 ? 0xC : \
701
(p) == MXC_PT13_BUS0 ? 0xD : \
702
(p) == MXC_PT14_BUS0 ? 0xE : \
703
(p) == MXC_PT15_BUS0 ? 0xF : \
704
(p) == MXC_PT0_BUS1 ? 0x8000 : \
705
(p) == MXC_PT1_BUS1 ? 0x8001 : \
706
(p) == MXC_PT2_BUS1 ? 0x8002 : \
707
(p) == MXC_PT3_BUS1 ? 0x8003 : \
708
(p) == MXC_PT4_BUS1 ? 0x8004 : \
709
(p) == MXC_PT5_BUS1 ? 0x8005 : \
710
(p) == MXC_PT6_BUS1 ? 0x8006 : \
711
(p) == MXC_PT7_BUS1 ? 0x8007 : \
712
(p) == MXC_PT8_BUS1 ? 0x8008 : \
713
(p) == MXC_PT9_BUS1 ? 0x8009 : \
714
(p) == MXC_PT10_BUS1 ? 0x800A : \
715
(p) == MXC_PT11_BUS1 ? 0x800B : \
716
(p) == MXC_PT12_BUS1 ? 0x800C : \
717
(p) == MXC_PT13_BUS1 ? 0x800D : \
718
(p) == MXC_PT14_BUS1 ? 0x800E : \
719
(p) == MXC_PT15_BUS1 ? 0x800F : -1)
720
721
#define MXC_PT_GET_BUS(i) (((i) & 0x00100000UL)>>20)
722
723
#define MXC_PTG_GET_PTG(i) (MXC_PT_GET_BUS((i)) == 0 ? MXC_PTG_BUS0 : \
724
MXC_PT_GET_BUS((i)) == 1 ? MXC_PTG_BUS1 : 0)
725
726
/******************************************************************************/
727
/* One Wire Master */
728
#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
729
#define MXC_OWM ((mxc_owm_regs_t*)MXC_BASE_OWM)
730
731
/******************************************************************************/
732
/* Semaphore */
733
#define MXC_CFG_SEMA_INSTANCES (8)
734
735
#define MXC_BASE_SEMA ((uint32_t)0x4003E000UL)
736
#define MXC_SEMA ((mxc_sema_regs_t*)MXC_BASE_SEMA)
737
738
/******************************************************************************/
739
/* UART / Serial Port Interface */
740
741
#define MXC_UART_INSTANCES (3)
742
#define MXC_UART_FIFO_DEPTH (32)
743
744
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
745
#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
746
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
747
#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
748
#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
749
#define MXC_UART2 ((mxc_uart_regs_t*)MXC_BASE_UART2)
750
751
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
752
(i) == 1 ? UART1_IRQn : \
753
(i) == 2 ? UART2_IRQn : 0)
754
755
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
756
(i) == 1 ? MXC_BASE_UART1 : \
757
(i) == 2 ? MXC_BASE_UART2 : 0)
758
759
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
760
(i) == 1 ? MXC_UART1 : \
761
(i) == 2 ? MXC_UART2 : 0)
762
763
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
764
(p) == MXC_UART1 ? 1 : \
765
(p) == MXC_UART2 ? 2 : -1)
766
767
/******************************************************************************/
768
/* SPI */
769
770
#define MXC_SPI_INSTANCES (3)
771
#define MXC_SPI_SS_INSTANCES (4)
772
#define MXC_SPI_FIFO_DEPTH (32)
773
774
#define MXC_BASE_SPI0 ((uint32_t)0x400BE000UL)
775
#define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI0)
776
#define MXC_BASE_SPI1 ((uint32_t)0x40046000UL)
777
#define MXC_SPI1 ((mxc_spi_regs_t*)MXC_BASE_SPI1)
778
#define MXC_BASE_SPI2 ((uint32_t)0x40047000UL)
779
#define MXC_SPI2 ((mxc_spi_regs_t*)MXC_BASE_SPI2)
780
781
782
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : \
783
(p) == MXC_SPI1 ? 1 : \
784
(p) == MXC_SPI2 ? 2 : -1)
785
786
#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
787
(i) == 1 ? MXC_BASE_SPI1 : \
788
(i) == 2 ? MXC_BASE_SPI2 : 0)
789
790
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
791
(i) == 1 ? MXC_SPI1 : \
792
(i) == 2 ? MXC_SPI2 : 0)
793
794
#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI0_IRQn : \
795
(i) == 1 ? SPI1_IRQn : \
796
(i) == 2 ? SPI2_IRQn : 0)
797
798
799
/******************************************************************************/
800
/* TRNG */
801
#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
802
#define MXC_TRNG ((mxc_trng_regs_t*)MXC_BASE_TRNG)
803
804
/******************************************************************************/
805
/* SDHC */
806
#define MXC_BASE_SDHC ((uint32_t)0x400B6000UL)
807
#define MXC_SDHC ((mxc_sdhc_regs_t*)MXC_BASE_SDHC)
808
809
/******************************************************************************/
810
/* RPU */
811
#define MXC_BASE_RPU ((uint32_t)0x40002000UL)
812
#define MXC_RPU ((mxc_rpu_regs_t*)MXC_BASE_RPU)
813
#define MXC_RPU_NUM_BUS_MASTERS 9
814
815
/******************************************************************************/
816
/* Audio Subsystem */
817
#define MXC_BASE_AUDIO ((uint32_t)0x4004C000UL)
818
#define MXC_AUDIO ((mxc_audio_regs_t*)MXC_BASE_AUDIO)
819
820
/******************************************************************************/
821
/* Bluetooth Low Energy */
822
#define MXC_BASE_BTLE (0x40050000UL)
823
#define MXC_BTLE ((mxc_btle_regs_t*)MXC_BASE_BTLE)
824
#define MXC_BASE_BTLE_DBB_CTRL (MXC_BASE_BTLE + 0x1000)
825
#define MXC_BASE_BTLE_DBB_TX (MXC_BASE_BTLE + 0x2000)
826
#define MXC_BASE_BTLE_DBB_RX (MXC_BASE_BTLE + 0x3000)
827
#define MXC_BASE_BTLE_DBB_EXT_RFFE (MXC_BASE_BTLE + 0x8000)
828
829
// Base address definitions needed for DBB register definitions in BTLE stack
830
#define DBB_CTRL_BASE MXC_BASE_BTLE_DBB_CTRL
831
#define DBB_TX_BASE MXC_BASE_BTLE_DBB_TX
832
#define DBB_RX_BASE MXC_BASE_BTLE_DBB_RX
833
#define DBB_EXT_RFFE_BASE MXC_BASE_BTLE_DBB_EXT_RFFE
834
835
836
/******************************************************************************/
837
/* Bit Shifting */
838
839
#define MXC_F_BIT_0 (1 << 0)
840
#define MXC_F_BIT_1 (1 << 1)
841
#define MXC_F_BIT_2 (1 << 2)
842
#define MXC_F_BIT_3 (1 << 3)
843
#define MXC_F_BIT_4 (1 << 4)
844
#define MXC_F_BIT_5 (1 << 5)
845
#define MXC_F_BIT_6 (1 << 6)
846
#define MXC_F_BIT_7 (1 << 7)
847
#define MXC_F_BIT_8 (1 << 8)
848
#define MXC_F_BIT_9 (1 << 9)
849
#define MXC_F_BIT_10 (1 << 10)
850
#define MXC_F_BIT_11 (1 << 11)
851
#define MXC_F_BIT_12 (1 << 12)
852
#define MXC_F_BIT_13 (1 << 13)
853
#define MXC_F_BIT_14 (1 << 14)
854
#define MXC_F_BIT_15 (1 << 15)
855
#define MXC_F_BIT_16 (1 << 16)
856
#define MXC_F_BIT_17 (1 << 17)
857
#define MXC_F_BIT_18 (1 << 18)
858
#define MXC_F_BIT_19 (1 << 19)
859
#define MXC_F_BIT_20 (1 << 20)
860
#define MXC_F_BIT_21 (1 << 21)
861
#define MXC_F_BIT_22 (1 << 22)
862
#define MXC_F_BIT_23 (1 << 23)
863
#define MXC_F_BIT_24 (1 << 24)
864
#define MXC_F_BIT_25 (1 << 25)
865
#define MXC_F_BIT_26 (1 << 26)
866
#define MXC_F_BIT_27 (1 << 27)
867
#define MXC_F_BIT_28 (1 << 28)
868
#define MXC_F_BIT_29 (1 << 29)
869
#define MXC_F_BIT_30 (1 << 30)
870
#define MXC_F_BIT_31 (1 << 31)
871
872
/******************************************************************************/
873
/* Bit Banding */
874
875
876
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
877
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
878
879
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
880
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
881
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
882
883
#define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask))
884
885
/******************************************************************************/
886
/* SCB CPACR */
887
888
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
889
#define SCB_CPACR_CP10_Pos 20
890
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
891
#define SCB_CPACR_CP11_Pos 22
892
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
894
#endif
/* _MAX32665_REGS_H_ */
CMSIS
Device
Maxim
MAX32665
Include
max32665.h
Generated on Fri Dec 4 2020 11:48:57 for MAX32665 Peripheral Driver API by
1.8.20