MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
ICC_CACHE_CTRL

Macros

#define MXC_F_ICC_CACHE_CTRL_ENABLE_POS   0
 
#define MXC_F_ICC_CACHE_CTRL_ENABLE   ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS))
 
#define MXC_F_ICC_CACHE_CTRL_READY_POS   16
 
#define MXC_F_ICC_CACHE_CTRL_READY   ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS))
 

Detailed Description

Cache Control and Status Register.

Macro Definition Documentation

◆ MXC_F_ICC_CACHE_CTRL_ENABLE

#define MXC_F_ICC_CACHE_CTRL_ENABLE   ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS))

CACHE_CTRL_ENABLE Mask

◆ MXC_F_ICC_CACHE_CTRL_ENABLE_POS

#define MXC_F_ICC_CACHE_CTRL_ENABLE_POS   0

CACHE_CTRL_ENABLE Position

◆ MXC_F_ICC_CACHE_CTRL_READY

#define MXC_F_ICC_CACHE_CTRL_READY   ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS))

CACHE_CTRL_READY Mask

◆ MXC_F_ICC_CACHE_CTRL_READY_POS

#define MXC_F_ICC_CACHE_CTRL_READY_POS   16

CACHE_CTRL_READY Position