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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Low Power Control Register.
#define MXC_F_PWRSEQ_LPCN_BCKGRND ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) |
LPCN_BCKGRND Mask
#define MXC_F_PWRSEQ_LPCN_BCKGRND_POS 9 |
LPCN_BCKGRND Position
#define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) |
LPCN_BGOFF Mask
#define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 |
LPCN_BGOFF Position
#define MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS)) |
LPCN_BLKDET Mask
#define MXC_F_PWRSEQ_LPCN_BLKDET_POS 6 |
LPCN_BLKDET Position
#define MXC_F_PWRSEQ_LPCN_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS)) |
LPCN_FWKM Mask
#define MXC_F_PWRSEQ_LPCN_FWKM_POS 10 |
LPCN_FWKM Position
#define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS)) |
LPCN_PDOWNDSLEN Mask
#define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS 30 |
LPCN_PDOWNDSLEN Position
#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) |
LPCN_PORVDDIOHMD Mask
#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS 26 |
LPCN_PORVDDIOHMD Position
#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) |
LPCN_PORVDDIOMD Mask
#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS 25 |
LPCN_PORVDDIOMD Position
#define MXC_F_PWRSEQ_LPCN_RAMRET ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_POS)) |
LPCN_RAMRET Mask
#define MXC_F_PWRSEQ_LPCN_RAMRET_POS 0 |
LPCN_RAMRET Position
#define MXC_F_PWRSEQ_LPCN_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS)) |
LPCN_VCOREMD Mask
#define MXC_F_PWRSEQ_LPCN_VCOREMD_POS 20 |
LPCN_VCOREMD Position
#define MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) |
LPCN_VDDAMD Mask
#define MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22 |
LPCN_VDDAMD Position
#define MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) |
LPCN_VDDBMD Mask
#define MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27 |
LPCN_VDDBMD Position
#define MXC_F_PWRSEQ_LPCN_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) |
LPCN_VDDIOHMD Mask
#define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS 24 |
LPCN_VDDIOHMD Position
#define MXC_F_PWRSEQ_LPCN_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) |
LPCN_VDDIOMD Mask
#define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS 23 |
LPCN_VDDIOMD Position
#define MXC_F_PWRSEQ_LPCN_VREGIMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VREGIMD_POS)) |
LPCN_VREGIMD Mask
#define MXC_F_PWRSEQ_LPCN_VREGIMD_POS 21 |
LPCN_VREGIMD Position
#define MXC_F_PWRSEQ_LPCN_VRXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS)) |
LPCN_VRXOUTMD Mask
#define MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS 28 |
LPCN_VRXOUTMD Position
#define MXC_F_PWRSEQ_LPCN_VTXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS)) |
LPCN_VTXOUTMD Mask
#define MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS 29 |
LPCN_VTXOUTMD Position
#define MXC_S_PWRSEQ_LPCN_RAMRET_DIS (MXC_V_PWRSEQ_LPCN_RAMRET_DIS << MXC_F_PWRSEQ_LPCN_RAMRET_POS) |
LPCN_RAMRET_DIS Setting
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN1 (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) |
LPCN_RAMRET_EN1 Setting
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN2 (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) |
LPCN_RAMRET_EN2 Setting
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN3 (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) |
LPCN_RAMRET_EN3 Setting
#define MXC_V_PWRSEQ_LPCN_RAMRET_DIS ((uint32_t)0x0UL) |
LPCN_RAMRET_DIS Value
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN1 ((uint32_t)0x1UL) |
LPCN_RAMRET_EN1 Value
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN2 ((uint32_t)0x2UL) |
LPCN_RAMRET_EN2 Value
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN3 ((uint32_t)0x3UL) |
LPCN_RAMRET_EN3 Value