MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
USBHS_INCSRL

Macros

#define MXC_F_USBHS_INCSRL_INCOMPTX_POS   7
 
#define MXC_F_USBHS_INCSRL_INCOMPTX   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_INCOMPTX_POS))
 
#define MXC_F_USBHS_INCSRL_CLRDATATOG_POS   6
 
#define MXC_F_USBHS_INCSRL_CLRDATATOG   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_CLRDATATOG_POS))
 
#define MXC_F_USBHS_INCSRL_SENTSTALL_POS   5
 
#define MXC_F_USBHS_INCSRL_SENTSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_SENTSTALL_POS))
 
#define MXC_F_USBHS_INCSRL_SENDSTALL_POS   4
 
#define MXC_F_USBHS_INCSRL_SENDSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_SENDSTALL_POS))
 
#define MXC_F_USBHS_INCSRL_FLUSHFIFO_POS   3
 
#define MXC_F_USBHS_INCSRL_FLUSHFIFO   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_FLUSHFIFO_POS))
 
#define MXC_F_USBHS_INCSRL_UNDERRUN_POS   2
 
#define MXC_F_USBHS_INCSRL_UNDERRUN   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_UNDERRUN_POS))
 
#define MXC_F_USBHS_INCSRL_FIFONOTEMPTY_POS   1
 
#define MXC_F_USBHS_INCSRL_FIFONOTEMPTY   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_FIFONOTEMPTY_POS))
 
#define MXC_F_USBHS_INCSRL_INPKTRDY_POS   0
 
#define MXC_F_USBHS_INCSRL_INPKTRDY   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_INPKTRDY_POS))
 

Detailed Description

Control status lower register for INx endpoint (x == INDEX).

Macro Definition Documentation

◆ MXC_F_USBHS_INCSRL_CLRDATATOG

#define MXC_F_USBHS_INCSRL_CLRDATATOG   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_CLRDATATOG_POS))

INCSRL_CLRDATATOG Mask

◆ MXC_F_USBHS_INCSRL_CLRDATATOG_POS

#define MXC_F_USBHS_INCSRL_CLRDATATOG_POS   6

INCSRL_CLRDATATOG Position

◆ MXC_F_USBHS_INCSRL_FIFONOTEMPTY

#define MXC_F_USBHS_INCSRL_FIFONOTEMPTY   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_FIFONOTEMPTY_POS))

INCSRL_FIFONOTEMPTY Mask

◆ MXC_F_USBHS_INCSRL_FIFONOTEMPTY_POS

#define MXC_F_USBHS_INCSRL_FIFONOTEMPTY_POS   1

INCSRL_FIFONOTEMPTY Position

◆ MXC_F_USBHS_INCSRL_FLUSHFIFO

#define MXC_F_USBHS_INCSRL_FLUSHFIFO   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_FLUSHFIFO_POS))

INCSRL_FLUSHFIFO Mask

◆ MXC_F_USBHS_INCSRL_FLUSHFIFO_POS

#define MXC_F_USBHS_INCSRL_FLUSHFIFO_POS   3

INCSRL_FLUSHFIFO Position

◆ MXC_F_USBHS_INCSRL_INCOMPTX

#define MXC_F_USBHS_INCSRL_INCOMPTX   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_INCOMPTX_POS))

INCSRL_INCOMPTX Mask

◆ MXC_F_USBHS_INCSRL_INCOMPTX_POS

#define MXC_F_USBHS_INCSRL_INCOMPTX_POS   7

INCSRL_INCOMPTX Position

◆ MXC_F_USBHS_INCSRL_INPKTRDY

#define MXC_F_USBHS_INCSRL_INPKTRDY   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_INPKTRDY_POS))

INCSRL_INPKTRDY Mask

◆ MXC_F_USBHS_INCSRL_INPKTRDY_POS

#define MXC_F_USBHS_INCSRL_INPKTRDY_POS   0

INCSRL_INPKTRDY Position

◆ MXC_F_USBHS_INCSRL_SENDSTALL

#define MXC_F_USBHS_INCSRL_SENDSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_SENDSTALL_POS))

INCSRL_SENDSTALL Mask

◆ MXC_F_USBHS_INCSRL_SENDSTALL_POS

#define MXC_F_USBHS_INCSRL_SENDSTALL_POS   4

INCSRL_SENDSTALL Position

◆ MXC_F_USBHS_INCSRL_SENTSTALL

#define MXC_F_USBHS_INCSRL_SENTSTALL   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_SENTSTALL_POS))

INCSRL_SENTSTALL Mask

◆ MXC_F_USBHS_INCSRL_SENTSTALL_POS

#define MXC_F_USBHS_INCSRL_SENTSTALL_POS   5

INCSRL_SENTSTALL Position

◆ MXC_F_USBHS_INCSRL_UNDERRUN

#define MXC_F_USBHS_INCSRL_UNDERRUN   ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_UNDERRUN_POS))

INCSRL_UNDERRUN Mask

◆ MXC_F_USBHS_INCSRL_UNDERRUN_POS

#define MXC_F_USBHS_INCSRL_UNDERRUN_POS   2

INCSRL_UNDERRUN Position