![]() |
MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
|
Memory Clock Control Register.
#define MXC_F_GCR_MEM_CLK_CRYPTOLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS)) |
MEM_CLK_CRYPTOLS Mask
#define MXC_F_GCR_MEM_CLK_CRYPTOLS_POS 27 |
MEM_CLK_CRYPTOLS Position
#define MXC_F_GCR_MEM_CLK_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CLK_FWS_POS)) |
MEM_CLK_FWS Mask
#define MXC_F_GCR_MEM_CLK_FWS_POS 0 |
MEM_CLK_FWS Position
#define MXC_F_GCR_MEM_CLK_ICACHE0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHE0LS_POS)) |
MEM_CLK_ICACHE0LS Mask
#define MXC_F_GCR_MEM_CLK_ICACHE0LS_POS 24 |
MEM_CLK_ICACHE0LS Position
#define MXC_F_GCR_MEM_CLK_ICACHE1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHE1LS_POS)) |
MEM_CLK_ICACHE1LS Mask
#define MXC_F_GCR_MEM_CLK_ICACHE1LS_POS 31 |
MEM_CLK_ICACHE1LS Position
#define MXC_F_GCR_MEM_CLK_ICACHEXIPLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS)) |
MEM_CLK_ICACHEXIPLS Mask
#define MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS 25 |
MEM_CLK_ICACHEXIPLS Position
#define MXC_F_GCR_MEM_CLK_ROM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ROM0LS_POS)) |
MEM_CLK_ROM0LS Mask
#define MXC_F_GCR_MEM_CLK_ROM0LS_POS 29 |
MEM_CLK_ROM0LS Position
#define MXC_F_GCR_MEM_CLK_ROM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ROM1LS_POS)) |
MEM_CLK_ROM1LS Mask
#define MXC_F_GCR_MEM_CLK_ROM1LS_POS 30 |
MEM_CLK_ROM1LS Position
#define MXC_F_GCR_MEM_CLK_SCACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SCACHELS_POS)) |
MEM_CLK_SCACHELS Mask
#define MXC_F_GCR_MEM_CLK_SCACHELS_POS 26 |
MEM_CLK_SCACHELS Position
#define MXC_F_GCR_MEM_CLK_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS)) |
MEM_CLK_SYSRAM0LS Mask
#define MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS 16 |
MEM_CLK_SYSRAM0LS Position
#define MXC_F_GCR_MEM_CLK_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS)) |
MEM_CLK_SYSRAM1LS Mask
#define MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS 17 |
MEM_CLK_SYSRAM1LS Position
#define MXC_F_GCR_MEM_CLK_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS)) |
MEM_CLK_SYSRAM2LS Mask
#define MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS 18 |
MEM_CLK_SYSRAM2LS Position
#define MXC_F_GCR_MEM_CLK_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS)) |
MEM_CLK_SYSRAM3LS Mask
#define MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS 19 |
MEM_CLK_SYSRAM3LS Position
#define MXC_F_GCR_MEM_CLK_SYSRAM4LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS)) |
MEM_CLK_SYSRAM4LS Mask
#define MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS 20 |
MEM_CLK_SYSRAM4LS Position
#define MXC_F_GCR_MEM_CLK_SYSRAM5LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS)) |
MEM_CLK_SYSRAM5LS Mask
#define MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS 21 |
MEM_CLK_SYSRAM5LS Position
#define MXC_F_GCR_MEM_CLK_SYSRAM6LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS)) |
MEM_CLK_SYSRAM6LS Mask
#define MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS 22 |
MEM_CLK_SYSRAM6LS Position
#define MXC_F_GCR_MEM_CLK_USBLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_USBLS_POS)) |
MEM_CLK_USBLS Mask
#define MXC_F_GCR_MEM_CLK_USBLS_POS 28 |
MEM_CLK_USBLS Position