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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Reset 1.
#define MXC_F_GCR_RST1_AUDIO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AUDIO_POS)) |
RST1_AUDIO Mask
#define MXC_F_GCR_RST1_AUDIO_POS 19 |
RST1_AUDIO Position
#define MXC_F_GCR_RST1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_BTLE_POS)) |
RST1_BTLE Mask
#define MXC_F_GCR_RST1_BTLE_POS 18 |
RST1_BTLE Position
#define MXC_F_GCR_RST1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS)) |
RST1_DVS Mask
#define MXC_F_GCR_RST1_DVS_POS 24 |
RST1_DVS Position
#define MXC_F_GCR_RST1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR0_POS)) |
RST1_HTMR0 Mask
#define MXC_F_GCR_RST1_HTMR0_POS 22 |
RST1_HTMR0 Position
#define MXC_F_GCR_RST1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR1_POS)) |
RST1_HTMR1 Mask
#define MXC_F_GCR_RST1_HTMR1_POS 23 |
RST1_HTMR1 Position
#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) |
RST1_I2C1 Mask
#define MXC_F_GCR_RST1_I2C1_POS 0 |
RST1_I2C1 Position
#define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) |
RST1_I2C2 Mask
#define MXC_F_GCR_RST1_I2C2_POS 20 |
RST1_I2C2 Position
#define MXC_F_GCR_RST1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS)) |
RST1_OWIRE Mask
#define MXC_F_GCR_RST1_OWIRE_POS 7 |
RST1_OWIRE Position
#define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) |
RST1_PT Mask
#define MXC_F_GCR_RST1_PT_POS 1 |
RST1_PT Position
#define MXC_F_GCR_RST1_RPU ((uint32_t)(0x1UL << MXC_F_GCR_RST1_RPU_POS)) |
RST1_RPU Mask
#define MXC_F_GCR_RST1_RPU_POS 21 |
RST1_RPU Position
#define MXC_F_GCR_RST1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS)) |
RST1_SDHC Mask
#define MXC_F_GCR_RST1_SDHC_POS 6 |
RST1_SDHC Position
#define MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS)) |
RST1_SEMA Mask
#define MXC_F_GCR_RST1_SEMA_POS 16 |
RST1_SEMA Position
#define MXC_F_GCR_RST1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS)) |
RST1_SIMO Mask
#define MXC_F_GCR_RST1_SIMO_POS 25 |
RST1_SIMO Position
#define MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS)) |
RST1_SPI3 Mask
#define MXC_F_GCR_RST1_SPI3_POS 9 |
RST1_SPI3 Position
#define MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS)) |
RST1_SPIXIP Mask
#define MXC_F_GCR_RST1_SPIXIP_POS 3 |
RST1_SPIXIP Position
#define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) |
RST1_WDT1 Mask
#define MXC_F_GCR_RST1_WDT1_POS 8 |
RST1_WDT1 Position
#define MXC_F_GCR_RST1_WDT2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT2_POS)) |
RST1_WDT2 Mask
#define MXC_F_GCR_RST1_WDT2_POS 17 |
RST1_WDT2 Position
#define MXC_F_GCR_RST1_XIPR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XIPR_POS)) |
RST1_XIPR Mask
#define MXC_F_GCR_RST1_XIPR_POS 15 |
RST1_XIPR Position
#define MXC_F_GCR_RST1_XSPIM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XSPIM_POS)) |
RST1_XSPIM Mask
#define MXC_F_GCR_RST1_XSPIM_POS 4 |
RST1_XSPIM Position