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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros | |
#define | MXC_R_USBHS_FADDR ((uint32_t)0x00000000UL) |
#define | MXC_R_USBHS_POWER ((uint32_t)0x00000001UL) |
#define | MXC_R_USBHS_INTRIN ((uint32_t)0x00000002UL) |
#define | MXC_R_USBHS_INTROUT ((uint32_t)0x00000004UL) |
#define | MXC_R_USBHS_INTRINEN ((uint32_t)0x00000006UL) |
#define | MXC_R_USBHS_INTROUTEN ((uint32_t)0x00000008UL) |
#define | MXC_R_USBHS_INTRUSB ((uint32_t)0x0000000AUL) |
#define | MXC_R_USBHS_INTRUSBEN ((uint32_t)0x0000000BUL) |
#define | MXC_R_USBHS_FRAME ((uint32_t)0x0000000CUL) |
#define | MXC_R_USBHS_INDEX ((uint32_t)0x0000000EUL) |
#define | MXC_R_USBHS_TESTMODE ((uint32_t)0x0000000FUL) |
#define | MXC_R_USBHS_INMAXP ((uint32_t)0x00000010UL) |
#define | MXC_R_USBHS_CSR0 ((uint32_t)0x00000012UL) |
#define | MXC_R_USBHS_INCSRL ((uint32_t)0x00000012UL) |
#define | MXC_R_USBHS_INCSRU ((uint32_t)0x00000013UL) |
#define | MXC_R_USBHS_OUTMAXP ((uint32_t)0x00000014UL) |
#define | MXC_R_USBHS_OUTCSRL ((uint32_t)0x00000016UL) |
#define | MXC_R_USBHS_OUTCSRU ((uint32_t)0x00000017UL) |
#define | MXC_R_USBHS_COUNT0 ((uint32_t)0x00000018UL) |
#define | MXC_R_USBHS_OUTCOUNT ((uint32_t)0x00000018UL) |
#define | MXC_R_USBHS_FIFO0 ((uint32_t)0x00000020UL) |
#define | MXC_R_USBHS_FIFO1 ((uint32_t)0x00000024UL) |
#define | MXC_R_USBHS_FIFO2 ((uint32_t)0x00000028UL) |
#define | MXC_R_USBHS_FIFO3 ((uint32_t)0x0000002CUL) |
#define | MXC_R_USBHS_FIFO4 ((uint32_t)0x00000030UL) |
#define | MXC_R_USBHS_FIFO5 ((uint32_t)0x00000034UL) |
#define | MXC_R_USBHS_FIFO6 ((uint32_t)0x00000038UL) |
#define | MXC_R_USBHS_FIFO7 ((uint32_t)0x0000003CUL) |
#define | MXC_R_USBHS_FIFO8 ((uint32_t)0x00000040UL) |
#define | MXC_R_USBHS_FIFO9 ((uint32_t)0x00000044UL) |
#define | MXC_R_USBHS_FIFO10 ((uint32_t)0x00000048UL) |
#define | MXC_R_USBHS_FIFO11 ((uint32_t)0x0000004CUL) |
#define | MXC_R_USBHS_FIFO12 ((uint32_t)0x00000050UL) |
#define | MXC_R_USBHS_FIFO13 ((uint32_t)0x00000054UL) |
#define | MXC_R_USBHS_FIFO14 ((uint32_t)0x00000058UL) |
#define | MXC_R_USBHS_FIFO15 ((uint32_t)0x0000005CUL) |
#define | MXC_R_USBHS_HWVERS ((uint32_t)0x0000006CUL) |
#define | MXC_R_USBHS_EPINFO ((uint32_t)0x00000078UL) |
#define | MXC_R_USBHS_RAMINFO ((uint32_t)0x00000079UL) |
#define | MXC_R_USBHS_SOFTRESET ((uint32_t)0x0000007AUL) |
#define | MXC_R_USBHS_EARLYDMA ((uint32_t)0x0000007BUL) |
#define | MXC_R_USBHS_CTUCH ((uint32_t)0x00000080UL) |
#define | MXC_R_USBHS_CTHSRTN ((uint32_t)0x00000082UL) |
#define | MXC_R_USBHS_M31_PHY_PONRST ((uint32_t)0x00000410UL) |
#define | MXC_R_USBHS_M31_PHY_NONCRY_RSTB ((uint32_t)0x00000414UL) |
#define | MXC_R_USBHS_M31_PHY_NONCRY_EN ((uint32_t)0x00000418UL) |
#define | MXC_R_USBHS_M31_PHY_PLL_EN ((uint32_t)0x00000430UL) |
#define | MXC_R_USBHS_M31_PHY_OSCOUTEN ((uint32_t)0x0000043CUL) |
#define | MXC_R_USBHS_M31_PHY_CORECLKIN ((uint32_t)0x00000448UL) |
#define | MXC_R_USBHS_M31_PHY_XTLSEL ((uint32_t)0x0000044CUL) |
#define | MXC_R_USBHS_M31_PHY_OUTCLKSEL ((uint32_t)0x0000045CUL) |
#define | MXC_R_USBHS_MXM_INT ((uint32_t)0x00000498UL) |
#define | MXC_R_USBHS_MXM_INT_EN ((uint32_t)0x0000049CUL) |
#define | MXC_R_USBHS_MXM_SUSPEND ((uint32_t)0x000004A0UL) |
#define | MXC_R_USBHS_MXM_REG_A4 ((uint32_t)0x000004A4UL) |
USBHS Peripheral Register Offsets from the USBHS Base Peripheral Address.
#define MXC_R_USBHS_COUNT0 ((uint32_t)0x00000018UL) |
Offset from USBHS Base Address: 0x0018
#define MXC_R_USBHS_CSR0 ((uint32_t)0x00000012UL) |
Offset from USBHS Base Address: 0x0012
#define MXC_R_USBHS_CTHSRTN ((uint32_t)0x00000082UL) |
Offset from USBHS Base Address: 0x0082
#define MXC_R_USBHS_CTUCH ((uint32_t)0x00000080UL) |
Offset from USBHS Base Address: 0x0080
#define MXC_R_USBHS_EARLYDMA ((uint32_t)0x0000007BUL) |
Offset from USBHS Base Address: 0x007B
#define MXC_R_USBHS_EPINFO ((uint32_t)0x00000078UL) |
Offset from USBHS Base Address: 0x0078
#define MXC_R_USBHS_FADDR ((uint32_t)0x00000000UL) |
Offset from USBHS Base Address: 0x0000
#define MXC_R_USBHS_FIFO0 ((uint32_t)0x00000020UL) |
Offset from USBHS Base Address: 0x0020
#define MXC_R_USBHS_FIFO1 ((uint32_t)0x00000024UL) |
Offset from USBHS Base Address: 0x0024
#define MXC_R_USBHS_FIFO10 ((uint32_t)0x00000048UL) |
Offset from USBHS Base Address: 0x0048
#define MXC_R_USBHS_FIFO11 ((uint32_t)0x0000004CUL) |
Offset from USBHS Base Address: 0x004C
#define MXC_R_USBHS_FIFO12 ((uint32_t)0x00000050UL) |
Offset from USBHS Base Address: 0x0050
#define MXC_R_USBHS_FIFO13 ((uint32_t)0x00000054UL) |
Offset from USBHS Base Address: 0x0054
#define MXC_R_USBHS_FIFO14 ((uint32_t)0x00000058UL) |
Offset from USBHS Base Address: 0x0058
#define MXC_R_USBHS_FIFO15 ((uint32_t)0x0000005CUL) |
Offset from USBHS Base Address: 0x005C
#define MXC_R_USBHS_FIFO2 ((uint32_t)0x00000028UL) |
Offset from USBHS Base Address: 0x0028
#define MXC_R_USBHS_FIFO3 ((uint32_t)0x0000002CUL) |
Offset from USBHS Base Address: 0x002C
#define MXC_R_USBHS_FIFO4 ((uint32_t)0x00000030UL) |
Offset from USBHS Base Address: 0x0030
#define MXC_R_USBHS_FIFO5 ((uint32_t)0x00000034UL) |
Offset from USBHS Base Address: 0x0034
#define MXC_R_USBHS_FIFO6 ((uint32_t)0x00000038UL) |
Offset from USBHS Base Address: 0x0038
#define MXC_R_USBHS_FIFO7 ((uint32_t)0x0000003CUL) |
Offset from USBHS Base Address: 0x003C
#define MXC_R_USBHS_FIFO8 ((uint32_t)0x00000040UL) |
Offset from USBHS Base Address: 0x0040
#define MXC_R_USBHS_FIFO9 ((uint32_t)0x00000044UL) |
Offset from USBHS Base Address: 0x0044
#define MXC_R_USBHS_FRAME ((uint32_t)0x0000000CUL) |
Offset from USBHS Base Address: 0x000C
#define MXC_R_USBHS_HWVERS ((uint32_t)0x0000006CUL) |
Offset from USBHS Base Address: 0x006C
#define MXC_R_USBHS_INCSRL ((uint32_t)0x00000012UL) |
Offset from USBHS Base Address: 0x0012
#define MXC_R_USBHS_INCSRU ((uint32_t)0x00000013UL) |
Offset from USBHS Base Address: 0x0013
#define MXC_R_USBHS_INDEX ((uint32_t)0x0000000EUL) |
Offset from USBHS Base Address: 0x000E
#define MXC_R_USBHS_INMAXP ((uint32_t)0x00000010UL) |
Offset from USBHS Base Address: 0x0010
#define MXC_R_USBHS_INTRIN ((uint32_t)0x00000002UL) |
Offset from USBHS Base Address: 0x0002
#define MXC_R_USBHS_INTRINEN ((uint32_t)0x00000006UL) |
Offset from USBHS Base Address: 0x0006
#define MXC_R_USBHS_INTROUT ((uint32_t)0x00000004UL) |
Offset from USBHS Base Address: 0x0004
#define MXC_R_USBHS_INTROUTEN ((uint32_t)0x00000008UL) |
Offset from USBHS Base Address: 0x0008
#define MXC_R_USBHS_INTRUSB ((uint32_t)0x0000000AUL) |
Offset from USBHS Base Address: 0x000A
#define MXC_R_USBHS_INTRUSBEN ((uint32_t)0x0000000BUL) |
Offset from USBHS Base Address: 0x000B
#define MXC_R_USBHS_M31_PHY_CORECLKIN ((uint32_t)0x00000448UL) |
Offset from USBHS Base Address: 0x0448
#define MXC_R_USBHS_M31_PHY_NONCRY_EN ((uint32_t)0x00000418UL) |
Offset from USBHS Base Address: 0x0418
#define MXC_R_USBHS_M31_PHY_NONCRY_RSTB ((uint32_t)0x00000414UL) |
Offset from USBHS Base Address: 0x0414
#define MXC_R_USBHS_M31_PHY_OSCOUTEN ((uint32_t)0x0000043CUL) |
Offset from USBHS Base Address: 0x043C
#define MXC_R_USBHS_M31_PHY_OUTCLKSEL ((uint32_t)0x0000045CUL) |
Offset from USBHS Base Address: 0x045C
#define MXC_R_USBHS_M31_PHY_PLL_EN ((uint32_t)0x00000430UL) |
Offset from USBHS Base Address: 0x0430
#define MXC_R_USBHS_M31_PHY_PONRST ((uint32_t)0x00000410UL) |
Offset from USBHS Base Address: 0x0410
#define MXC_R_USBHS_M31_PHY_XTLSEL ((uint32_t)0x0000044CUL) |
Offset from USBHS Base Address: 0x044C
#define MXC_R_USBHS_MXM_INT ((uint32_t)0x00000498UL) |
Offset from USBHS Base Address: 0x0498
#define MXC_R_USBHS_MXM_INT_EN ((uint32_t)0x0000049CUL) |
Offset from USBHS Base Address: 0x049C
#define MXC_R_USBHS_MXM_REG_A4 ((uint32_t)0x000004A4UL) |
Offset from USBHS Base Address: 0x04A4
#define MXC_R_USBHS_MXM_SUSPEND ((uint32_t)0x000004A0UL) |
Offset from USBHS Base Address: 0x04A0
#define MXC_R_USBHS_OUTCOUNT ((uint32_t)0x00000018UL) |
Offset from USBHS Base Address: 0x0018
#define MXC_R_USBHS_OUTCSRL ((uint32_t)0x00000016UL) |
Offset from USBHS Base Address: 0x0016
#define MXC_R_USBHS_OUTCSRU ((uint32_t)0x00000017UL) |
Offset from USBHS Base Address: 0x0017
#define MXC_R_USBHS_OUTMAXP ((uint32_t)0x00000014UL) |
Offset from USBHS Base Address: 0x0014
#define MXC_R_USBHS_POWER ((uint32_t)0x00000001UL) |
Offset from USBHS Base Address: 0x0001
#define MXC_R_USBHS_RAMINFO ((uint32_t)0x00000079UL) |
Offset from USBHS Base Address: 0x0079
#define MXC_R_USBHS_SOFTRESET ((uint32_t)0x0000007AUL) |
Offset from USBHS Base Address: 0x007A
#define MXC_R_USBHS_TESTMODE ((uint32_t)0x0000000FUL) |
Offset from USBHS Base Address: 0x000F