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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros | |
#define | MXC_R_GCR_SCON ((uint32_t)0x00000000UL) |
#define | MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) |
#define | MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) |
#define | MXC_R_GCR_PMR ((uint32_t)0x0000000CUL) |
#define | MXC_R_GCR_PCLK_DIV ((uint32_t)0x00000018UL) |
#define | MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) |
#define | MXC_R_GCR_MEM_CLK ((uint32_t)0x00000028UL) |
#define | MXC_R_GCR_MEM_ZERO ((uint32_t)0x0000002CUL) |
#define | MXC_R_GCR_SCCK ((uint32_t)0x00000034UL) |
#define | MXC_R_GCR_MPRI0 ((uint32_t)0x00000038UL) |
#define | MXC_R_GCR_MPRI1 ((uint32_t)0x0000003CUL) |
#define | MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) |
#define | MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) |
#define | MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) |
#define | MXC_R_GCR_EVENT_EN ((uint32_t)0x0000004CUL) |
#define | MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) |
#define | MXC_R_GCR_SYS_STAT_IE ((uint32_t)0x00000054UL) |
#define | MXC_R_GCR_ECC_ER ((uint32_t)0x00000064UL) |
#define | MXC_R_GCR_ECC_NDED ((uint32_t)0x00000068UL) |
#define | MXC_R_GCR_ECC_IRQEN ((uint32_t)0x0000006CUL) |
#define | MXC_R_GCR_ECC_ERRAD ((uint32_t)0x00000070UL) |
#define | MXC_R_GCR_BTLE_LDOCR ((uint32_t)0x00000074UL) |
#define | MXC_R_GCR_BTLE_LDODCR ((uint32_t)0x00000078UL) |
#define | MXC_R_GCR_GPR0 ((uint32_t)0x00000080UL) |
#define | MXC_R_GCR_APB_ASYNC ((uint32_t)0x00000084UL) |
GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
#define MXC_R_GCR_APB_ASYNC ((uint32_t)0x00000084UL) |
Offset from GCR Base Address: 0x0084
#define MXC_R_GCR_BTLE_LDOCR ((uint32_t)0x00000074UL) |
Offset from GCR Base Address: 0x0074
#define MXC_R_GCR_BTLE_LDODCR ((uint32_t)0x00000078UL) |
Offset from GCR Base Address: 0x0078
#define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) |
Offset from GCR Base Address: 0x0008
#define MXC_R_GCR_ECC_ER ((uint32_t)0x00000064UL) |
Offset from GCR Base Address: 0x0064
#define MXC_R_GCR_ECC_ERRAD ((uint32_t)0x00000070UL) |
Offset from GCR Base Address: 0x0070
#define MXC_R_GCR_ECC_IRQEN ((uint32_t)0x0000006CUL) |
Offset from GCR Base Address: 0x006C
#define MXC_R_GCR_ECC_NDED ((uint32_t)0x00000068UL) |
Offset from GCR Base Address: 0x0068
#define MXC_R_GCR_EVENT_EN ((uint32_t)0x0000004CUL) |
Offset from GCR Base Address: 0x004C
#define MXC_R_GCR_GPR0 ((uint32_t)0x00000080UL) |
Offset from GCR Base Address: 0x0080
#define MXC_R_GCR_MEM_CLK ((uint32_t)0x00000028UL) |
Offset from GCR Base Address: 0x0028
#define MXC_R_GCR_MEM_ZERO ((uint32_t)0x0000002CUL) |
Offset from GCR Base Address: 0x002C
#define MXC_R_GCR_MPRI0 ((uint32_t)0x00000038UL) |
Offset from GCR Base Address: 0x0038
#define MXC_R_GCR_MPRI1 ((uint32_t)0x0000003CUL) |
Offset from GCR Base Address: 0x003C
#define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) |
Offset from GCR Base Address: 0x0024
#define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) |
Offset from GCR Base Address: 0x0048
#define MXC_R_GCR_PCLK_DIV ((uint32_t)0x00000018UL) |
Offset from GCR Base Address: 0x0018
#define MXC_R_GCR_PMR ((uint32_t)0x0000000CUL) |
Offset from GCR Base Address: 0x000C
#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) |
Offset from GCR Base Address: 0x0050
#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) |
Offset from GCR Base Address: 0x0004
#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) |
Offset from GCR Base Address: 0x0044
#define MXC_R_GCR_SCCK ((uint32_t)0x00000034UL) |
Offset from GCR Base Address: 0x0034
#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) |
Offset from GCR Base Address: 0x0000
#define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) |
Offset from GCR Base Address: 0x0040
#define MXC_R_GCR_SYS_STAT_IE ((uint32_t)0x00000054UL) |
Offset from GCR Base Address: 0x0054