MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
SDMA_INT_MUX_CTRL1

Macros

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS   0
 
#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS))
 
#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS   8
 
#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS))
 
#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS   16
 
#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS))
 
#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS   24
 
#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS))
 

Detailed Description

Interrupt Mux Control 1.

Macro Definition Documentation

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS))

INT_MUX_CTRL1_INTSEL20 Mask

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS   0

INT_MUX_CTRL1_INTSEL20 Position

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS))

INT_MUX_CTRL1_INTSEL21 Mask

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS   8

INT_MUX_CTRL1_INTSEL21 Position

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS))

INT_MUX_CTRL1_INTSEL22 Mask

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS   16

INT_MUX_CTRL1_INTSEL22 Position

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23   ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS))

INT_MUX_CTRL1_INTSEL23 Mask

◆ MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS

#define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS   24

INT_MUX_CTRL1_INTSEL23 Position