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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Data Cache Controller Protection Register.
#define MXC_F_RPU_SRCC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_CRYPTOACN_POS)) |
SRCC_CRYPTOACN Mask
#define MXC_F_RPU_SRCC_CRYPTOACN_POS 7 |
SRCC_CRYPTOACN Position
#define MXC_F_RPU_SRCC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_DMA0ACN_POS)) |
SRCC_DMA0ACN Mask
#define MXC_F_RPU_SRCC_DMA0ACN_POS 0 |
SRCC_DMA0ACN Position
#define MXC_F_RPU_SRCC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_DMA1ACN_POS)) |
SRCC_DMA1ACN Mask
#define MXC_F_RPU_SRCC_DMA1ACN_POS 1 |
SRCC_DMA1ACN Position
#define MXC_F_RPU_SRCC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDIOACN_POS)) |
SRCC_SDIOACN Mask
#define MXC_F_RPU_SRCC_SDIOACN_POS 8 |
SRCC_SDIOACN Position
#define MXC_F_RPU_SRCC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDMADACN_POS)) |
SRCC_SDMADACN Mask
#define MXC_F_RPU_SRCC_SDMADACN_POS 5 |
SRCC_SDMADACN Position
#define MXC_F_RPU_SRCC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDMAIACN_POS)) |
SRCC_SDMAIACN Mask
#define MXC_F_RPU_SRCC_SDMAIACN_POS 6 |
SRCC_SDMAIACN Position
#define MXC_F_RPU_SRCC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SYS0ACN_POS)) |
SRCC_SYS0ACN Mask
#define MXC_F_RPU_SRCC_SYS0ACN_POS 3 |
SRCC_SYS0ACN Position
#define MXC_F_RPU_SRCC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SYS1ACN_POS)) |
SRCC_SYS1ACN Mask
#define MXC_F_RPU_SRCC_SYS1ACN_POS 4 |
SRCC_SYS1ACN Position
#define MXC_F_RPU_SRCC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_USBACN_POS)) |
SRCC_USBACN Mask
#define MXC_F_RPU_SRCC_USBACN_POS 2 |
SRCC_USBACN Position