MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
rpu.h
1 
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37  * $Date: 2019-12-24 11:42:21 -0600 (Tue, 24 Dec 2019) $
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41 
42 /* Define to prevent redundant inclusion */
43 #ifndef _RPU_H_
44 #define _RPU_H_
45 
46 /* **** Includes **** */
47 #include "rpu_regs.h"
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
59 /* **** Definitions **** */
60 
61 // Bus Masters whose access to peripherals is controlled by the RPU
62 typedef enum {
63  MXC_RPU_DMA0_ALLOW = 0x01,
64  MXC_RPU_DMA1_ALLOW = 0x02,
65  MXC_RPU_USB_ALLOW = 0x04,
66  MXC_RPU_SYS0_ALLOW = 0x08,
67  MXC_RPU_SYS1_ALLOW = 0x10,
68  MXC_RPU_SDMAD_ALLOW = 0x20,
69  MXC_RPU_SDMAI_ALLOW = 0x40,
70  MXC_RPU_CRYPTO_ALLOW = 0x80,
71  MXC_RPU_SDIO_ALLOW = 0x100
72 } mxc_rpu_allow_t;
73 
74 // Peripherals gated by the RPU
75 typedef enum {
76  MXC_RPU_GCR = MXC_R_RPU_GCR,
77  MXC_RPU_FLC0 = MXC_R_RPU_FLC0,
78  MXC_RPU_SDHCCTRL = MXC_R_RPU_SDHCCTRL,
79  MXC_RPU_SIR = MXC_R_RPU_SIR,
80  MXC_RPU_FCR = MXC_R_RPU_FCR,
81  MXC_RPU_CRYPTO = MXC_R_RPU_CRYPTO,
82  MXC_RPU_WDT0 = MXC_R_RPU_WDT0,
83  MXC_RPU_WDT1 = MXC_R_RPU_WDT1,
84  MXC_RPU_WDT2 = MXC_R_RPU_WDT2,
85  MXC_RPU_SMON = MXC_R_RPU_SMON,
86  MXC_RPU_SIMO = MXC_R_RPU_SIMO,
87  MXC_RPU_DVS = MXC_R_RPU_DVS,
88  MXC_RPU_BBSIR = MXC_R_RPU_BBSIR,
89  MXC_RPU_RTC = MXC_R_RPU_RTC,
90  MXC_RPU_WUT = MXC_R_RPU_WUT,
91  MXC_RPU_PWRSEQ = MXC_R_RPU_PWRSEQ,
92  MXC_RPU_MCR = MXC_R_RPU_MCR,
93  MXC_RPU_GPIO0 = MXC_R_RPU_GPIO0,
94  MXC_RPU_GPIO1 = MXC_R_RPU_GPIO1,
95  MXC_RPU_TMR0 = MXC_R_RPU_TMR0,
96  MXC_RPU_TMR1 = MXC_R_RPU_TMR1,
97  MXC_RPU_TMR2 = MXC_R_RPU_TMR2,
98  MXC_RPU_TMR3 = MXC_R_RPU_TMR3,
99  MXC_RPU_TMR4 = MXC_R_RPU_TMR4,
100  MXC_RPU_TMR5 = MXC_R_RPU_TMR5,
101  MXC_RPU_HTIMER0 = MXC_R_RPU_HTIMER0,
102  MXC_RPU_HTIMER1 = MXC_R_RPU_HTIMER1,
103  MXC_RPU_I2C0_BUS0 = MXC_R_RPU_I2C0_BUS0,
104  MXC_RPU_I2C1_BUS0 = MXC_R_RPU_I2C1_BUS0,
105  MXC_RPU_I2C2_BUS0 = MXC_R_RPU_I2C2_BUS0,
106  MXC_RPU_SPIXFM = MXC_R_RPU_SPIXFM,
107  MXC_RPU_SPIXFC = MXC_R_RPU_SPIXFC,
108  MXC_RPU_DMA0 = MXC_R_RPU_DMA0,
109  MXC_RPU_FLC1 = MXC_R_RPU_FLC1,
110  MXC_RPU_ICC0 = MXC_R_RPU_ICC0,
111  MXC_RPU_ICC1 = MXC_R_RPU_ICC1,
112  MXC_RPU_SFCC = MXC_R_RPU_SFCC,
113  MXC_RPU_SRCC = MXC_R_RPU_SRCC,
114  MXC_RPU_ADC = MXC_R_RPU_ADC,
115  MXC_RPU_DMA1 = MXC_R_RPU_DMA1,
116  MXC_RPU_SDMA = MXC_R_RPU_SDMA,
117  MXC_RPU_SPIXR = MXC_R_RPU_SPIXR,
118  MXC_RPU_PTG_BUS0 = MXC_R_RPU_PTG_BUS0,
119  MXC_RPU_OWM = MXC_R_RPU_OWM,
120  MXC_RPU_SEMA = MXC_R_RPU_SEMA,
121  MXC_RPU_UART0 = MXC_R_RPU_UART0,
122  MXC_RPU_UART1 = MXC_R_RPU_UART1,
123  MXC_RPU_UART2 = MXC_R_RPU_UART2,
124  MXC_RPU_SPI1 = MXC_R_RPU_SPI1,
125  MXC_RPU_SPI2 = MXC_R_RPU_SPI2,
126  MXC_RPU_AUDIO = MXC_R_RPU_AUDIO,
127  MXC_RPU_TRNG = MXC_R_RPU_TRNG,
128  MXC_RPU_BTLE = MXC_R_RPU_BTLE,
129  MXC_RPU_USBHS = MXC_R_RPU_USBHS,
130  MXC_RPU_SDIO = MXC_R_RPU_SDIO,
131  MXC_RPU_SPIXM_FIFO = MXC_R_RPU_SPIXM_FIFO,
132  MXC_RPU_SPI0 = MXC_R_RPU_SPI0
133 } mxc_rpu_device_t;
134 
135 /* **** Function Prototypes **** */
143 int MXC_RPU_Allow(mxc_rpu_device_t periph, uint32_t allow_mask);
144 
152 int MXC_RPU_Disallow(mxc_rpu_device_t periph, uint32_t disallow_mask);
153 
160 
161 
164 #ifdef __cplusplus
165 }
166 #endif
167 
168 #endif /* _RPU_H_ */
MXC_R_RPU_I2C0_BUS0
#define MXC_R_RPU_I2C0_BUS0
Definition: rpu_regs.h:238
MXC_R_RPU_TMR3
#define MXC_R_RPU_TMR3
Definition: rpu_regs.h:233
MXC_R_RPU_ICC1
#define MXC_R_RPU_ICC1
Definition: rpu_regs.h:247
MXC_R_RPU_I2C2_BUS0
#define MXC_R_RPU_I2C2_BUS0
Definition: rpu_regs.h:240
MXC_R_RPU_FLC0
#define MXC_R_RPU_FLC0
Definition: rpu_regs.h:244
MXC_R_RPU_TMR4
#define MXC_R_RPU_TMR4
Definition: rpu_regs.h:234
MXC_R_RPU_TMR2
#define MXC_R_RPU_TMR2
Definition: rpu_regs.h:232
MXC_R_RPU_ICC0
#define MXC_R_RPU_ICC0
Definition: rpu_regs.h:246
MXC_R_RPU_UART2
#define MXC_R_RPU_UART2
Definition: rpu_regs.h:260
MXC_R_RPU_GCR
#define MXC_R_RPU_GCR
Definition: rpu_regs.h:213
MXC_R_RPU_MCR
#define MXC_R_RPU_MCR
Definition: rpu_regs.h:227
MXC_R_RPU_SIMO
#define MXC_R_RPU_SIMO
Definition: rpu_regs.h:221
MXC_R_RPU_ADC
#define MXC_R_RPU_ADC
Definition: rpu_regs.h:250
MXC_R_RPU_AUDIO
#define MXC_R_RPU_AUDIO
Definition: rpu_regs.h:263
MXC_R_RPU_SFCC
#define MXC_R_RPU_SFCC
Definition: rpu_regs.h:248
MXC_R_RPU_SPI0
#define MXC_R_RPU_SPI0
Definition: rpu_regs.h:269
MXC_R_RPU_UART1
#define MXC_R_RPU_UART1
Definition: rpu_regs.h:259
MXC_R_RPU_PWRSEQ
#define MXC_R_RPU_PWRSEQ
Definition: rpu_regs.h:226
MXC_RPU_IsAllowed
int MXC_RPU_IsAllowed(void)
Check to see if this process is running in handler mode.
MXC_R_RPU_TMR1
#define MXC_R_RPU_TMR1
Definition: rpu_regs.h:231
MXC_R_RPU_BBSIR
#define MXC_R_RPU_BBSIR
Definition: rpu_regs.h:223
MXC_R_RPU_SPI2
#define MXC_R_RPU_SPI2
Definition: rpu_regs.h:262
MXC_R_RPU_UART0
#define MXC_R_RPU_UART0
Definition: rpu_regs.h:258
MXC_R_RPU_WDT2
#define MXC_R_RPU_WDT2
Definition: rpu_regs.h:219
MXC_R_RPU_SPIXFM
#define MXC_R_RPU_SPIXFM
Definition: rpu_regs.h:241
MXC_R_RPU_I2C1_BUS0
#define MXC_R_RPU_I2C1_BUS0
Definition: rpu_regs.h:239
MXC_R_RPU_WUT
#define MXC_R_RPU_WUT
Definition: rpu_regs.h:225
MXC_R_RPU_WDT0
#define MXC_R_RPU_WDT0
Definition: rpu_regs.h:217
MXC_R_RPU_DVS
#define MXC_R_RPU_DVS
Definition: rpu_regs.h:222
MXC_R_RPU_FCR
#define MXC_R_RPU_FCR
Definition: rpu_regs.h:215
MXC_R_RPU_BTLE
#define MXC_R_RPU_BTLE
Definition: rpu_regs.h:265
MXC_R_RPU_USBHS
#define MXC_R_RPU_USBHS
Definition: rpu_regs.h:266
MXC_R_RPU_SMON
#define MXC_R_RPU_SMON
Definition: rpu_regs.h:220
MXC_RPU_Disallow
int MXC_RPU_Disallow(mxc_rpu_device_t periph, uint32_t disallow_mask)
Disable access to peripherals restricted by the RPU This function must be called from handler (privil...
MXC_R_RPU_DMA1
#define MXC_R_RPU_DMA1
Definition: rpu_regs.h:251
MXC_R_RPU_HTIMER0
#define MXC_R_RPU_HTIMER0
Definition: rpu_regs.h:236
MXC_R_RPU_SIR
#define MXC_R_RPU_SIR
Definition: rpu_regs.h:214
MXC_R_RPU_RTC
#define MXC_R_RPU_RTC
Definition: rpu_regs.h:224
MXC_R_RPU_SDMA
#define MXC_R_RPU_SDMA
Definition: rpu_regs.h:252
MXC_R_RPU_FLC1
#define MXC_R_RPU_FLC1
Definition: rpu_regs.h:245
MXC_R_RPU_SPI1
#define MXC_R_RPU_SPI1
Definition: rpu_regs.h:261
MXC_R_RPU_PTG_BUS0
#define MXC_R_RPU_PTG_BUS0
Definition: rpu_regs.h:255
MXC_R_RPU_WDT1
#define MXC_R_RPU_WDT1
Definition: rpu_regs.h:218
MXC_RPU_Allow
int MXC_RPU_Allow(mxc_rpu_device_t periph, uint32_t allow_mask)
Enable access to peripherals restricted by the RPU This function must be called from handler (privile...
MXC_R_RPU_SDIO
#define MXC_R_RPU_SDIO
Definition: rpu_regs.h:267
MXC_R_RPU_SRCC
#define MXC_R_RPU_SRCC
Definition: rpu_regs.h:249
MXC_R_RPU_TMR0
#define MXC_R_RPU_TMR0
Definition: rpu_regs.h:230
MXC_R_RPU_DMA0
#define MXC_R_RPU_DMA0
Definition: rpu_regs.h:243
MXC_R_RPU_OWM
#define MXC_R_RPU_OWM
Definition: rpu_regs.h:256
MXC_R_RPU_SPIXFC
#define MXC_R_RPU_SPIXFC
Definition: rpu_regs.h:242
MXC_R_RPU_SPIXM_FIFO
#define MXC_R_RPU_SPIXM_FIFO
Definition: rpu_regs.h:268
MXC_R_RPU_CRYPTO
#define MXC_R_RPU_CRYPTO
Definition: rpu_regs.h:216
MXC_R_RPU_SEMA
#define MXC_R_RPU_SEMA
Definition: rpu_regs.h:257
MXC_R_RPU_TMR5
#define MXC_R_RPU_TMR5
Definition: rpu_regs.h:235
MXC_R_RPU_SPIXR
#define MXC_R_RPU_SPIXR
Definition: rpu_regs.h:254
MXC_R_RPU_GPIO1
#define MXC_R_RPU_GPIO1
Definition: rpu_regs.h:229
MXC_R_RPU_HTIMER1
#define MXC_R_RPU_HTIMER1
Definition: rpu_regs.h:237
MXC_R_RPU_TRNG
#define MXC_R_RPU_TRNG
Definition: rpu_regs.h:264
MXC_R_RPU_GPIO0
#define MXC_R_RPU_GPIO0
Definition: rpu_regs.h:228
MXC_R_RPU_SDHCCTRL
#define MXC_R_RPU_SDHCCTRL
Definition: rpu_regs.h:253