MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
smon_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the "Software"),
11  * to deal in the Software without restriction, including without limitation
12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13  * and/or sell copies of the Software, and to permit persons to whom the
14  * Software is furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included
17  * in all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
23  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25  * OTHER DEALINGS IN THE SOFTWARE.
26  *
27  * Except as contained in this notice, the name of Maxim Integrated
28  * Products, Inc. shall not be used except as stated in the Maxim Integrated
29  * Products, Inc. Branding Policy.
30  *
31  * The mere transfer of this software does not imply any licenses
32  * of trade secrets, proprietary technology, copyrights, patents,
33  * trademarks, maskwork rights, or any other form of intellectual
34  * property whatsoever. Maxim Integrated Products, Inc. retains all
35  * ownership rights.
36  *
37  *
38  *************************************************************************** */
39 
40 #ifndef _SMON_REGS_H_
41 #define _SMON_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t extscn;
90  __IO uint32_t intscn;
91  __IO uint32_t secalm;
92  __I uint32_t secdiag;
93  __I uint32_t dlrtc;
94  __R uint32_t rsv_0x14_0x33[8];
95  __I uint32_t secst;
97 
98 /* Register offsets for module SMON */
105  #define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL)
106  #define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL)
107  #define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL)
108  #define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL)
109  #define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL)
110  #define MXC_R_SMON_SECST ((uint32_t)0x00000034UL)
119  #define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0
120  #define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS))
122  #define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1
123  #define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS))
125  #define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2
126  #define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS))
128  #define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3
129  #define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS))
131  #define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4
132  #define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS))
134  #define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5
135  #define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS))
137  #define MXC_F_SMON_EXTSCN_EXTCNT_POS 16
138  #define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS))
140  #define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21
141  #define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS))
142  #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL)
143  #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS)
144  #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL)
145  #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS)
146  #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL)
147  #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS)
148  #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL)
149  #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS)
150  #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL)
151  #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS)
152  #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL)
153  #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS)
154  #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL)
155  #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS)
157  #define MXC_F_SMON_EXTSCN_DIVCLK_POS 24
158  #define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS))
159  #define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL)
160  #define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS)
161  #define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL)
162  #define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS)
163  #define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL)
164  #define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS)
165  #define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL)
166  #define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS)
167  #define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL)
168  #define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS)
169  #define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL)
170  #define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS)
171  #define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL)
172  #define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS)
174  #define MXC_F_SMON_EXTSCN_BUSY_POS 30
175  #define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS))
177  #define MXC_F_SMON_EXTSCN_LOCK_POS 31
178  #define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS))
188  #define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0
189  #define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS))
191  #define MXC_F_SMON_INTSCN_TEMP_EN_POS 1
192  #define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS))
194  #define MXC_F_SMON_INTSCN_VBAT_EN_POS 2
195  #define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS))
197  #define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16
198  #define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS))
200  #define MXC_F_SMON_INTSCN_VCORELOEN_POS 18
201  #define MXC_F_SMON_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS))
203  #define MXC_F_SMON_INTSCN_VCOREHIEN_POS 19
204  #define MXC_F_SMON_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS))
206  #define MXC_F_SMON_INTSCN_VDDLOEN_POS 20
207  #define MXC_F_SMON_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS))
209  #define MXC_F_SMON_INTSCN_VDDHIEN_POS 21
210  #define MXC_F_SMON_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS))
212  #define MXC_F_SMON_INTSCN_VGLEN_POS 22
213  #define MXC_F_SMON_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS))
215  #define MXC_F_SMON_INTSCN_LOCK_POS 31
216  #define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS))
226  #define MXC_F_SMON_SECALM_DRS_POS 0
227  #define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS))
229  #define MXC_F_SMON_SECALM_KEYWIPE_POS 1
230  #define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS))
232  #define MXC_F_SMON_SECALM_SHIELDF_POS 2
233  #define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS))
235  #define MXC_F_SMON_SECALM_LOTEMP_POS 3
236  #define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS))
238  #define MXC_F_SMON_SECALM_HITEMP_POS 4
239  #define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS))
241  #define MXC_F_SMON_SECALM_BATLO_POS 5
242  #define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS))
244  #define MXC_F_SMON_SECALM_BATHI_POS 6
245  #define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS))
247  #define MXC_F_SMON_SECALM_EXTF_POS 7
248  #define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS))
250  #define MXC_F_SMON_SECALM_VDDLO_POS 8
251  #define MXC_F_SMON_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS))
253  #define MXC_F_SMON_SECALM_VCORELO_POS 9
254  #define MXC_F_SMON_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS))
256  #define MXC_F_SMON_SECALM_VCOREHI_POS 10
257  #define MXC_F_SMON_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS))
259  #define MXC_F_SMON_SECALM_VDDHI_POS 11
260  #define MXC_F_SMON_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS))
262  #define MXC_F_SMON_SECALM_VGL_POS 12
263  #define MXC_F_SMON_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS))
265  #define MXC_F_SMON_SECALM_EXTSTAT0_POS 16
266  #define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS))
268  #define MXC_F_SMON_SECALM_EXTSTAT1_POS 17
269  #define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS))
271  #define MXC_F_SMON_SECALM_EXTSTAT2_POS 18
272  #define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS))
274  #define MXC_F_SMON_SECALM_EXTSTAT3_POS 19
275  #define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS))
277  #define MXC_F_SMON_SECALM_EXTSTAT4_POS 20
278  #define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS))
280  #define MXC_F_SMON_SECALM_EXTSTAT5_POS 21
281  #define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS))
283  #define MXC_F_SMON_SECALM_EXTSWARN0_POS 24
284  #define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS))
286  #define MXC_F_SMON_SECALM_EXTSWARN1_POS 25
287  #define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS))
289  #define MXC_F_SMON_SECALM_EXTSWARN2_POS 26
290  #define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS))
292  #define MXC_F_SMON_SECALM_EXTSWARN3_POS 27
293  #define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS))
295  #define MXC_F_SMON_SECALM_EXTSWARN4_POS 28
296  #define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS))
298  #define MXC_F_SMON_SECALM_EXTSWARN5_POS 29
299  #define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS))
309  #define MXC_F_SMON_SECDIAG_BORF_POS 0
310  #define MXC_F_SMON_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS))
312  #define MXC_F_SMON_SECDIAG_SHIELDF_POS 2
313  #define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS))
315  #define MXC_F_SMON_SECDIAG_LOTEMP_POS 3
316  #define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS))
318  #define MXC_F_SMON_SECDIAG_HITEMP_POS 4
319  #define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS))
321  #define MXC_F_SMON_SECDIAG_BATLO_POS 5
322  #define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS))
324  #define MXC_F_SMON_SECDIAG_BATHI_POS 6
325  #define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS))
327  #define MXC_F_SMON_SECDIAG_DYNF_POS 7
328  #define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS))
330  #define MXC_F_SMON_SECDIAG_AESKT_POS 8
331  #define MXC_F_SMON_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS))
333  #define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16
334  #define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS))
336  #define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17
337  #define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS))
339  #define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18
340  #define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS))
342  #define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19
343  #define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS))
345  #define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20
346  #define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS))
348  #define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21
349  #define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS))
360  #define MXC_F_SMON_DLRTC_DLRTC_POS 0
361  #define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS))
371  #define MXC_F_SMON_SECST_EXTSRS_POS 0
372  #define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS))
374  #define MXC_F_SMON_SECST_INTSRS_POS 1
375  #define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS))
377  #define MXC_F_SMON_SECST_SECALRS_POS 2
378  #define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS))
382 #ifdef __cplusplus
383 }
384 #endif
385 
386 #endif /* _SMON_REGS_H_ */
mxc_smon_regs_t::secdiag
__I uint32_t secdiag
Definition: smon_regs.h:92
mxc_smon_regs_t::intscn
__IO uint32_t intscn
Definition: smon_regs.h:90
mxc_smon_regs_t::secst
__I uint32_t secst
Definition: smon_regs.h:95
mxc_smon_regs_t::extscn
__IO uint32_t extscn
Definition: smon_regs.h:89
mxc_smon_regs_t
Definition: smon_regs.h:88
mxc_smon_regs_t::secalm
__IO uint32_t secalm
Definition: smon_regs.h:91
mxc_smon_regs_t::dlrtc
__I uint32_t dlrtc
Definition: smon_regs.h:93