MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
GCR_PCLK_DIV

Macros

#define MXC_F_GCR_PCLK_DIV_PCF_POS   0
 
#define MXC_F_GCR_PCLK_DIV_PCF   ((uint32_t)(0x7UL << MXC_F_GCR_PCLK_DIV_PCF_POS))
 
#define MXC_V_GCR_PCLK_DIV_PCF_96MHZ   ((uint32_t)0x2UL)
 
#define MXC_S_GCR_PCLK_DIV_PCF_96MHZ   (MXC_V_GCR_PCLK_DIV_PCF_96MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
 
#define MXC_V_GCR_PCLK_DIV_PCF_48MHZ   ((uint32_t)0x3UL)
 
#define MXC_S_GCR_PCLK_DIV_PCF_48MHZ   (MXC_V_GCR_PCLK_DIV_PCF_48MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
 
#define MXC_V_GCR_PCLK_DIV_PCF_24MHZ   ((uint32_t)0x4UL)
 
#define MXC_S_GCR_PCLK_DIV_PCF_24MHZ   (MXC_V_GCR_PCLK_DIV_PCF_24MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
 
#define MXC_V_GCR_PCLK_DIV_PCF_12MHZ   ((uint32_t)0x5UL)
 
#define MXC_S_GCR_PCLK_DIV_PCF_12MHZ   (MXC_V_GCR_PCLK_DIV_PCF_12MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
 
#define MXC_V_GCR_PCLK_DIV_PCF_6MHZ   ((uint32_t)0x6UL)
 
#define MXC_S_GCR_PCLK_DIV_PCF_6MHZ   (MXC_V_GCR_PCLK_DIV_PCF_6MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
 
#define MXC_V_GCR_PCLK_DIV_PCF_3MHZ   ((uint32_t)0x7UL)
 
#define MXC_S_GCR_PCLK_DIV_PCF_3MHZ   (MXC_V_GCR_PCLK_DIV_PCF_3MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)
 
#define MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS   7
 
#define MXC_F_GCR_PCLK_DIV_SDHCFRQ   ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS))
 
#define MXC_F_GCR_PCLK_DIV_ADCFRQ_POS   10
 
#define MXC_F_GCR_PCLK_DIV_ADCFRQ   ((uint32_t)(0xFUL << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS))
 
#define MXC_F_GCR_PCLK_DIV_AONDIV_POS   14
 
#define MXC_F_GCR_PCLK_DIV_AONDIV   ((uint32_t)(0x3UL << MXC_F_GCR_PCLK_DIV_AONDIV_POS))
 
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4   ((uint32_t)0x0UL)
 
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_4   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
 
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8   ((uint32_t)0x1UL)
 
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_8   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
 
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16   ((uint32_t)0x2UL)
 
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_16   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
 
#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32   ((uint32_t)0x3UL)
 
#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_32   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)
 

Detailed Description

Peripheral Clock Divider.

Macro Definition Documentation

◆ MXC_F_GCR_PCLK_DIV_ADCFRQ

#define MXC_F_GCR_PCLK_DIV_ADCFRQ   ((uint32_t)(0xFUL << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS))

PCLK_DIV_ADCFRQ Mask

◆ MXC_F_GCR_PCLK_DIV_ADCFRQ_POS

#define MXC_F_GCR_PCLK_DIV_ADCFRQ_POS   10

PCLK_DIV_ADCFRQ Position

◆ MXC_F_GCR_PCLK_DIV_AONDIV

#define MXC_F_GCR_PCLK_DIV_AONDIV   ((uint32_t)(0x3UL << MXC_F_GCR_PCLK_DIV_AONDIV_POS))

PCLK_DIV_AONDIV Mask

◆ MXC_F_GCR_PCLK_DIV_AONDIV_POS

#define MXC_F_GCR_PCLK_DIV_AONDIV_POS   14

PCLK_DIV_AONDIV Position

◆ MXC_F_GCR_PCLK_DIV_PCF

#define MXC_F_GCR_PCLK_DIV_PCF   ((uint32_t)(0x7UL << MXC_F_GCR_PCLK_DIV_PCF_POS))

PCLK_DIV_PCF Mask

◆ MXC_F_GCR_PCLK_DIV_PCF_POS

#define MXC_F_GCR_PCLK_DIV_PCF_POS   0

PCLK_DIV_PCF Position

◆ MXC_F_GCR_PCLK_DIV_SDHCFRQ

#define MXC_F_GCR_PCLK_DIV_SDHCFRQ   ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS))

PCLK_DIV_SDHCFRQ Mask

◆ MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS

#define MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS   7

PCLK_DIV_SDHCFRQ Position

◆ MXC_S_GCR_PCLK_DIV_AONDIV_DIV_16

#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_16   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)

PCLK_DIV_AONDIV_DIV_16 Setting

◆ MXC_S_GCR_PCLK_DIV_AONDIV_DIV_32

#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_32   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)

PCLK_DIV_AONDIV_DIV_32 Setting

◆ MXC_S_GCR_PCLK_DIV_AONDIV_DIV_4

#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_4   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)

PCLK_DIV_AONDIV_DIV_4 Setting

◆ MXC_S_GCR_PCLK_DIV_AONDIV_DIV_8

#define MXC_S_GCR_PCLK_DIV_AONDIV_DIV_8   (MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8 << MXC_F_GCR_PCLK_DIV_AONDIV_POS)

PCLK_DIV_AONDIV_DIV_8 Setting

◆ MXC_S_GCR_PCLK_DIV_PCF_12MHZ

#define MXC_S_GCR_PCLK_DIV_PCF_12MHZ   (MXC_V_GCR_PCLK_DIV_PCF_12MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)

PCLK_DIV_PCF_12MHZ Setting

◆ MXC_S_GCR_PCLK_DIV_PCF_24MHZ

#define MXC_S_GCR_PCLK_DIV_PCF_24MHZ   (MXC_V_GCR_PCLK_DIV_PCF_24MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)

PCLK_DIV_PCF_24MHZ Setting

◆ MXC_S_GCR_PCLK_DIV_PCF_3MHZ

#define MXC_S_GCR_PCLK_DIV_PCF_3MHZ   (MXC_V_GCR_PCLK_DIV_PCF_3MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)

PCLK_DIV_PCF_3MHZ Setting

◆ MXC_S_GCR_PCLK_DIV_PCF_48MHZ

#define MXC_S_GCR_PCLK_DIV_PCF_48MHZ   (MXC_V_GCR_PCLK_DIV_PCF_48MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)

PCLK_DIV_PCF_48MHZ Setting

◆ MXC_S_GCR_PCLK_DIV_PCF_6MHZ

#define MXC_S_GCR_PCLK_DIV_PCF_6MHZ   (MXC_V_GCR_PCLK_DIV_PCF_6MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)

PCLK_DIV_PCF_6MHZ Setting

◆ MXC_S_GCR_PCLK_DIV_PCF_96MHZ

#define MXC_S_GCR_PCLK_DIV_PCF_96MHZ   (MXC_V_GCR_PCLK_DIV_PCF_96MHZ << MXC_F_GCR_PCLK_DIV_PCF_POS)

PCLK_DIV_PCF_96MHZ Setting

◆ MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16

#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_16   ((uint32_t)0x2UL)

PCLK_DIV_AONDIV_DIV_16 Value

◆ MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32

#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_32   ((uint32_t)0x3UL)

PCLK_DIV_AONDIV_DIV_32 Value

◆ MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4

#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_4   ((uint32_t)0x0UL)

PCLK_DIV_AONDIV_DIV_4 Value

◆ MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8

#define MXC_V_GCR_PCLK_DIV_AONDIV_DIV_8   ((uint32_t)0x1UL)

PCLK_DIV_AONDIV_DIV_8 Value

◆ MXC_V_GCR_PCLK_DIV_PCF_12MHZ

#define MXC_V_GCR_PCLK_DIV_PCF_12MHZ   ((uint32_t)0x5UL)

PCLK_DIV_PCF_12MHZ Value

◆ MXC_V_GCR_PCLK_DIV_PCF_24MHZ

#define MXC_V_GCR_PCLK_DIV_PCF_24MHZ   ((uint32_t)0x4UL)

PCLK_DIV_PCF_24MHZ Value

◆ MXC_V_GCR_PCLK_DIV_PCF_3MHZ

#define MXC_V_GCR_PCLK_DIV_PCF_3MHZ   ((uint32_t)0x7UL)

PCLK_DIV_PCF_3MHZ Value

◆ MXC_V_GCR_PCLK_DIV_PCF_48MHZ

#define MXC_V_GCR_PCLK_DIV_PCF_48MHZ   ((uint32_t)0x3UL)

PCLK_DIV_PCF_48MHZ Value

◆ MXC_V_GCR_PCLK_DIV_PCF_6MHZ

#define MXC_V_GCR_PCLK_DIV_PCF_6MHZ   ((uint32_t)0x6UL)

PCLK_DIV_PCF_6MHZ Value

◆ MXC_V_GCR_PCLK_DIV_PCF_96MHZ

#define MXC_V_GCR_PCLK_DIV_PCF_96MHZ   ((uint32_t)0x2UL)

PCLK_DIV_PCF_96MHZ Value