Macros
#define	MXC_F_PWRSEQ_LPCN_RAMRET0_POS 0

#define	MXC_F_PWRSEQ_LPCN_RAMRET0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET0_POS))

#define	MXC_F_PWRSEQ_LPCN_RAMRET1_POS 1

#define	MXC_F_PWRSEQ_LPCN_RAMRET1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET1_POS))

#define	MXC_F_PWRSEQ_LPCN_RAMRET2_POS 2

#define	MXC_F_PWRSEQ_LPCN_RAMRET2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET2_POS))

#define	MXC_F_PWRSEQ_LPCN_RAMRET3_POS 3

#define	MXC_F_PWRSEQ_LPCN_RAMRET3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET3_POS))

#define	MXC_F_PWRSEQ_LPCN_OVR_POS 4

#define	MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS))

#define	MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL)

#define	MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS)

#define	MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL)

#define	MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS)

#define	MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL)

#define	MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS)

#define	MXC_F_PWRSEQ_LPCN_BLKDET_POS 6

#define	MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS))

#define	MXC_F_PWRSEQ_LPCN_FVDDEN_POS 7

#define	MXC_F_PWRSEQ_LPCN_FVDDEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FVDDEN_POS))

#define	MXC_F_PWRSEQ_LPCN_RREGEN_POS 8

#define	MXC_F_PWRSEQ_LPCN_RREGEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RREGEN_POS))

#define	MXC_F_PWRSEQ_LPCN_STORAGE_POS 9

#define	MXC_F_PWRSEQ_LPCN_STORAGE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_POS))

#define	MXC_F_PWRSEQ_LPCN_FWKM_POS 10

#define	MXC_F_PWRSEQ_LPCN_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS))

#define	MXC_F_PWRSEQ_LPCN_BGOFF_POS 11

#define	MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS))

#define	MXC_F_PWRSEQ_LPCN_PORVCOREMD_POS 12

#define	MXC_F_PWRSEQ_LPCN_PORVCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVCOREMD_POS))

#define	MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16

#define	MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS))

#define	MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17

#define	MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS))

#define	MXC_F_PWRSEQ_LPCN_VCOREMD_POS 20

#define	MXC_F_PWRSEQ_LPCN_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS))

#define	MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22

#define	MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS))

#define	MXC_F_PWRSEQ_LPCN_VDDIOMD_POS 23

#define	MXC_F_PWRSEQ_LPCN_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS))

#define	MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS 24

#define	MXC_F_PWRSEQ_LPCN_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS))

#define	MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS 25

#define	MXC_F_PWRSEQ_LPCN_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS))

#define	MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS 26

#define	MXC_F_PWRSEQ_LPCN_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS))

#define	MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27

#define	MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS))

#define	MXC_F_PWRSEQ_LPCN_INROEN_POS 28

#define	MXC_F_PWRSEQ_LPCN_INROEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INROEN_POS))

#define	MXC_F_PWRSEQ_LPCN_XRTCOEN_POS 29

#define	MXC_F_PWRSEQ_LPCN_XRTCOEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_XRTCOEN_POS))

#define	MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30

#define	MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS))

#define	MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31

#define	MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS))

Detailed Description

Low Power Control Register.

Macro Definition Documentation

◆ MXC_F_PWRSEQ_LPCN_BGOFF

#define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS))

LPCN_BGOFF Mask

◆ MXC_F_PWRSEQ_LPCN_BGOFF_POS

#define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11

LPCN_BGOFF Position

◆ MXC_F_PWRSEQ_LPCN_BLKDET

#define MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS))

LPCN_BLKDET Mask

◆ MXC_F_PWRSEQ_LPCN_BLKDET_POS

#define MXC_F_PWRSEQ_LPCN_BLKDET_POS 6

LPCN_BLKDET Position

◆ MXC_F_PWRSEQ_LPCN_FVDDEN

#define MXC_F_PWRSEQ_LPCN_FVDDEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FVDDEN_POS))

LPCN_FVDDEN Mask

◆ MXC_F_PWRSEQ_LPCN_FVDDEN_POS

#define MXC_F_PWRSEQ_LPCN_FVDDEN_POS 7

LPCN_FVDDEN Position

◆ MXC_F_PWRSEQ_LPCN_FWKM

#define MXC_F_PWRSEQ_LPCN_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS))

LPCN_FWKM Mask

◆ MXC_F_PWRSEQ_LPCN_FWKM_POS

#define MXC_F_PWRSEQ_LPCN_FWKM_POS 10

LPCN_FWKM Position

◆ MXC_F_PWRSEQ_LPCN_INROEN

#define MXC_F_PWRSEQ_LPCN_INROEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INROEN_POS))

LPCN_INROEN Mask

◆ MXC_F_PWRSEQ_LPCN_INROEN_POS

#define MXC_F_PWRSEQ_LPCN_INROEN_POS 28

LPCN_INROEN Position

◆ MXC_F_PWRSEQ_LPCN_LDO_DIS

#define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS))

LPCN_LDO_DIS Mask

◆ MXC_F_PWRSEQ_LPCN_LDO_DIS_POS

#define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16

LPCN_LDO_DIS Position

◆ MXC_F_PWRSEQ_LPCN_OVR

#define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS))

LPCN_OVR Mask

◆ MXC_F_PWRSEQ_LPCN_OVR_POS

#define MXC_F_PWRSEQ_LPCN_OVR_POS 4

LPCN_OVR Position

◆ MXC_F_PWRSEQ_LPCN_PORVCOREMD

#define MXC_F_PWRSEQ_LPCN_PORVCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVCOREMD_POS))

LPCN_PORVCOREMD Mask

◆ MXC_F_PWRSEQ_LPCN_PORVCOREMD_POS

#define MXC_F_PWRSEQ_LPCN_PORVCOREMD_POS 12

LPCN_PORVCOREMD Position

◆ MXC_F_PWRSEQ_LPCN_PORVDDIOHMD

#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS))

LPCN_PORVDDIOHMD Mask

◆ MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS

#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS 26

LPCN_PORVDDIOHMD Position

◆ MXC_F_PWRSEQ_LPCN_PORVDDIOMD

#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS))

LPCN_PORVDDIOMD Mask

◆ MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS

#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS 25

LPCN_PORVDDIOMD Position

◆ MXC_F_PWRSEQ_LPCN_RAMRET0

#define MXC_F_PWRSEQ_LPCN_RAMRET0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET0_POS))

LPCN_RAMRET0 Mask

◆ MXC_F_PWRSEQ_LPCN_RAMRET0_POS

#define MXC_F_PWRSEQ_LPCN_RAMRET0_POS 0

LPCN_RAMRET0 Position

◆ MXC_F_PWRSEQ_LPCN_RAMRET1

#define MXC_F_PWRSEQ_LPCN_RAMRET1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET1_POS))

LPCN_RAMRET1 Mask

◆ MXC_F_PWRSEQ_LPCN_RAMRET1_POS

#define MXC_F_PWRSEQ_LPCN_RAMRET1_POS 1

LPCN_RAMRET1 Position

◆ MXC_F_PWRSEQ_LPCN_RAMRET2

#define MXC_F_PWRSEQ_LPCN_RAMRET2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET2_POS))

LPCN_RAMRET2 Mask

◆ MXC_F_PWRSEQ_LPCN_RAMRET2_POS

#define MXC_F_PWRSEQ_LPCN_RAMRET2_POS 2

LPCN_RAMRET2 Position

◆ MXC_F_PWRSEQ_LPCN_RAMRET3

#define MXC_F_PWRSEQ_LPCN_RAMRET3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET3_POS))

LPCN_RAMRET3 Mask

◆ MXC_F_PWRSEQ_LPCN_RAMRET3_POS

#define MXC_F_PWRSEQ_LPCN_RAMRET3_POS 3

LPCN_RAMRET3 Position

◆ MXC_F_PWRSEQ_LPCN_RREGEN

#define MXC_F_PWRSEQ_LPCN_RREGEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RREGEN_POS))

LPCN_RREGEN Mask

◆ MXC_F_PWRSEQ_LPCN_RREGEN_POS

#define MXC_F_PWRSEQ_LPCN_RREGEN_POS 8

LPCN_RREGEN Position

◆ MXC_F_PWRSEQ_LPCN_STORAGE

#define MXC_F_PWRSEQ_LPCN_STORAGE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_POS))

LPCN_STORAGE Mask

◆ MXC_F_PWRSEQ_LPCN_STORAGE_POS

#define MXC_F_PWRSEQ_LPCN_STORAGE_POS 9

LPCN_STORAGE Position

◆ MXC_F_PWRSEQ_LPCN_TM_LPMODE

#define MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS))

LPCN_TM_LPMODE Mask

◆ MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS

#define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30

LPCN_TM_LPMODE Position

◆ MXC_F_PWRSEQ_LPCN_TM_PWRSEQ

#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS))

LPCN_TM_PWRSEQ Mask

◆ MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS

#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31

LPCN_TM_PWRSEQ Position

◆ MXC_F_PWRSEQ_LPCN_VCORE_EXT

#define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS))

LPCN_VCORE_EXT Mask

◆ MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS

#define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17

LPCN_VCORE_EXT Position

◆ MXC_F_PWRSEQ_LPCN_VCOREMD

#define MXC_F_PWRSEQ_LPCN_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS))

LPCN_VCOREMD Mask

◆ MXC_F_PWRSEQ_LPCN_VCOREMD_POS

#define MXC_F_PWRSEQ_LPCN_VCOREMD_POS 20

LPCN_VCOREMD Position

◆ MXC_F_PWRSEQ_LPCN_VDDAMD

#define MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS))

LPCN_VDDAMD Mask

◆ MXC_F_PWRSEQ_LPCN_VDDAMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22

LPCN_VDDAMD Position

◆ MXC_F_PWRSEQ_LPCN_VDDBMD

#define MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS))

LPCN_VDDBMD Mask

◆ MXC_F_PWRSEQ_LPCN_VDDBMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27

LPCN_VDDBMD Position

◆ MXC_F_PWRSEQ_LPCN_VDDIOHMD

#define MXC_F_PWRSEQ_LPCN_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS))

LPCN_VDDIOHMD Mask

◆ MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS 24

LPCN_VDDIOHMD Position

◆ MXC_F_PWRSEQ_LPCN_VDDIOMD

#define MXC_F_PWRSEQ_LPCN_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS))

LPCN_VDDIOMD Mask

◆ MXC_F_PWRSEQ_LPCN_VDDIOMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS 23

LPCN_VDDIOMD Position

◆ MXC_F_PWRSEQ_LPCN_XRTCOEN

#define MXC_F_PWRSEQ_LPCN_XRTCOEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_XRTCOEN_POS))

LPCN_XRTCOEN Mask

◆ MXC_F_PWRSEQ_LPCN_XRTCOEN_POS

#define MXC_F_PWRSEQ_LPCN_XRTCOEN_POS 29

LPCN_XRTCOEN Position

◆ MXC_S_PWRSEQ_LPCN_OVR_0_9V

#define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS)

LPCN_OVR_0_9V Setting

◆ MXC_S_PWRSEQ_LPCN_OVR_1_0V

#define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS)

LPCN_OVR_1_0V Setting

◆ MXC_S_PWRSEQ_LPCN_OVR_1_1V

#define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS)

LPCN_OVR_1_1V Setting

◆ MXC_V_PWRSEQ_LPCN_OVR_0_9V

#define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL)

LPCN_OVR_0_9V Value

◆ MXC_V_PWRSEQ_LPCN_OVR_1_0V

#define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL)

LPCN_OVR_1_0V Value

◆ MXC_V_PWRSEQ_LPCN_OVR_1_1V

#define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL)

LPCN_OVR_1_1V Value

Macros