Macros
#define	MXC_F_FCR_REG1_ACEN_POS 0

#define	MXC_F_FCR_REG1_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACEN_POS))

#define	MXC_F_FCR_REG1_ACRUN_POS 1

#define	MXC_F_FCR_REG1_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACRUN_POS))

#define	MXC_F_FCR_REG1_LDTRM_POS 2

#define	MXC_F_FCR_REG1_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_REG1_LDTRM_POS))

#define	MXC_F_FCR_REG1_GAININV_POS 3

#define	MXC_F_FCR_REG1_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_REG1_GAININV_POS))

#define	MXC_F_FCR_REG1_ATOMIC_POS 4

#define	MXC_F_FCR_REG1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ATOMIC_POS))

#define	MXC_F_FCR_REG1_MU_POS 8

#define	MXC_F_FCR_REG1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_REG1_MU_POS))

Detailed Description

Register 1.

Macro Definition Documentation

◆ MXC_F_FCR_REG1_ACEN

#define MXC_F_FCR_REG1_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACEN_POS))

REG1_ACEN Mask

◆ MXC_F_FCR_REG1_ACEN_POS

#define MXC_F_FCR_REG1_ACEN_POS 0

REG1_ACEN Position

◆ MXC_F_FCR_REG1_ACRUN

#define MXC_F_FCR_REG1_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACRUN_POS))

REG1_ACRUN Mask

◆ MXC_F_FCR_REG1_ACRUN_POS

#define MXC_F_FCR_REG1_ACRUN_POS 1

REG1_ACRUN Position

◆ MXC_F_FCR_REG1_ATOMIC

#define MXC_F_FCR_REG1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ATOMIC_POS))

REG1_ATOMIC Mask

◆ MXC_F_FCR_REG1_ATOMIC_POS

#define MXC_F_FCR_REG1_ATOMIC_POS 4

REG1_ATOMIC Position

◆ MXC_F_FCR_REG1_GAININV

#define MXC_F_FCR_REG1_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_REG1_GAININV_POS))

REG1_GAININV Mask

◆ MXC_F_FCR_REG1_GAININV_POS

#define MXC_F_FCR_REG1_GAININV_POS 3

REG1_GAININV Position

◆ MXC_F_FCR_REG1_LDTRM

#define MXC_F_FCR_REG1_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_REG1_LDTRM_POS))

REG1_LDTRM Mask

◆ MXC_F_FCR_REG1_LDTRM_POS

#define MXC_F_FCR_REG1_LDTRM_POS 2

REG1_LDTRM Position

◆ MXC_F_FCR_REG1_MU

#define MXC_F_FCR_REG1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_REG1_MU_POS))

REG1_MU Mask

◆ MXC_F_FCR_REG1_MU_POS

#define MXC_F_FCR_REG1_MU_POS 8

REG1_MU Position

Macros