40 #ifndef _PWRSEQ_REGS_H_ 41 #define _PWRSEQ_REGS_H_ 50 #if defined (__ICCARM__) 51 #pragma system_include 54 #if defined (__CC_ARM) 65 #define __I volatile const 71 #define __R volatile const 94 __R uint32_t rsv_0x14_0x2f[7];
97 __R uint32_t rsv_0x38_0x3f[2];
99 __R uint32_t rsv_0x44;
111 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) 112 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) 113 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) 114 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) 115 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) 116 #define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) 117 #define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL) 118 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) 119 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) 120 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) 129 #define MXC_F_PWRSEQ_LPCN_RAMRET0_POS 0 130 #define MXC_F_PWRSEQ_LPCN_RAMRET0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET0_POS)) 132 #define MXC_F_PWRSEQ_LPCN_RAMRET1_POS 1 133 #define MXC_F_PWRSEQ_LPCN_RAMRET1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET1_POS)) 135 #define MXC_F_PWRSEQ_LPCN_RAMRET2_POS 2 136 #define MXC_F_PWRSEQ_LPCN_RAMRET2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET2_POS)) 138 #define MXC_F_PWRSEQ_LPCN_RAMRET3_POS 3 139 #define MXC_F_PWRSEQ_LPCN_RAMRET3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET3_POS)) 141 #define MXC_F_PWRSEQ_LPCN_OVR_POS 4 142 #define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) 143 #define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) 144 #define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) 145 #define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) 146 #define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) 147 #define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) 148 #define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) 150 #define MXC_F_PWRSEQ_LPCN_BLKDET_POS 6 151 #define MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS)) 153 #define MXC_F_PWRSEQ_LPCN_FVDDEN_POS 7 154 #define MXC_F_PWRSEQ_LPCN_FVDDEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FVDDEN_POS)) 156 #define MXC_F_PWRSEQ_LPCN_RREGEN_POS 8 157 #define MXC_F_PWRSEQ_LPCN_RREGEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RREGEN_POS)) 159 #define MXC_F_PWRSEQ_LPCN_STORAGE_POS 9 160 #define MXC_F_PWRSEQ_LPCN_STORAGE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_POS)) 162 #define MXC_F_PWRSEQ_LPCN_FWKM_POS 10 163 #define MXC_F_PWRSEQ_LPCN_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS)) 165 #define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 166 #define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) 168 #define MXC_F_PWRSEQ_LPCN_PORVCOREMD_POS 12 169 #define MXC_F_PWRSEQ_LPCN_PORVCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVCOREMD_POS)) 171 #define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 172 #define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) 174 #define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 175 #define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) 177 #define MXC_F_PWRSEQ_LPCN_VCOREMD_POS 20 178 #define MXC_F_PWRSEQ_LPCN_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS)) 180 #define MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22 181 #define MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) 183 #define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS 23 184 #define MXC_F_PWRSEQ_LPCN_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) 186 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS 24 187 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) 189 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS 25 190 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) 192 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS 26 193 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) 195 #define MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27 196 #define MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) 198 #define MXC_F_PWRSEQ_LPCN_INROEN_POS 28 199 #define MXC_F_PWRSEQ_LPCN_INROEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INROEN_POS)) 201 #define MXC_F_PWRSEQ_LPCN_XRTCOEN_POS 29 202 #define MXC_F_PWRSEQ_LPCN_XRTCOEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_XRTCOEN_POS)) 204 #define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30 205 #define MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS)) 207 #define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31 208 #define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS)) 219 #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS 0 220 #define MXC_F_PWRSEQ_LPWKST0_WAKEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) 231 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 232 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) 242 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS 4 243 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS)) 245 #define MXC_F_PWRSEQ_LPPWST_BACKUP_POS 16 246 #define MXC_F_PWRSEQ_LPPWST_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BACKUP_POS)) 248 #define MXC_F_PWRSEQ_LPPWST_RESET_POS 17 249 #define MXC_F_PWRSEQ_LPPWST_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RESET_POS)) 259 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS 4 260 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS)) 262 #define MXC_F_PWRSEQ_LPPWEN_WDT0_POS 8 263 #define MXC_F_PWRSEQ_LPPWEN_WDT0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT0_POS)) 265 #define MXC_F_PWRSEQ_LPPWEN_WDT1_POS 9 266 #define MXC_F_PWRSEQ_LPPWEN_WDT1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT1_POS)) 268 #define MXC_F_PWRSEQ_LPPWEN_CPU1_POS 10 269 #define MXC_F_PWRSEQ_LPPWEN_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CPU1_POS)) 271 #define MXC_F_PWRSEQ_LPPWEN_TMR0_POS 11 272 #define MXC_F_PWRSEQ_LPPWEN_TMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR0_POS)) 274 #define MXC_F_PWRSEQ_LPPWEN_TMR1_POS 12 275 #define MXC_F_PWRSEQ_LPPWEN_TMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR1_POS)) 277 #define MXC_F_PWRSEQ_LPPWEN_TMR2_POS 13 278 #define MXC_F_PWRSEQ_LPPWEN_TMR2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR2_POS)) 280 #define MXC_F_PWRSEQ_LPPWEN_TMR3_POS 14 281 #define MXC_F_PWRSEQ_LPPWEN_TMR3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR3_POS)) 283 #define MXC_F_PWRSEQ_LPPWEN_TMR4_POS 15 284 #define MXC_F_PWRSEQ_LPPWEN_TMR4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR4_POS)) 286 #define MXC_F_PWRSEQ_LPPWEN_TMR5_POS 16 287 #define MXC_F_PWRSEQ_LPPWEN_TMR5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR5_POS)) 289 #define MXC_F_PWRSEQ_LPPWEN_UART0_POS 17 290 #define MXC_F_PWRSEQ_LPPWEN_UART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART0_POS)) 292 #define MXC_F_PWRSEQ_LPPWEN_UART1_POS 18 293 #define MXC_F_PWRSEQ_LPPWEN_UART1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART1_POS)) 295 #define MXC_F_PWRSEQ_LPPWEN_UART2_POS 19 296 #define MXC_F_PWRSEQ_LPPWEN_UART2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART2_POS)) 298 #define MXC_F_PWRSEQ_LPPWEN_UART3_POS 20 299 #define MXC_F_PWRSEQ_LPPWEN_UART3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART3_POS)) 301 #define MXC_F_PWRSEQ_LPPWEN_I2C0_POS 21 302 #define MXC_F_PWRSEQ_LPPWEN_I2C0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C0_POS)) 304 #define MXC_F_PWRSEQ_LPPWEN_I2C1_POS 22 305 #define MXC_F_PWRSEQ_LPPWEN_I2C1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C1_POS)) 307 #define MXC_F_PWRSEQ_LPPWEN_I2C2_POS 23 308 #define MXC_F_PWRSEQ_LPPWEN_I2C2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C2_POS)) 310 #define MXC_F_PWRSEQ_LPPWEN_I2S_POS 24 311 #define MXC_F_PWRSEQ_LPPWEN_I2S ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2S_POS)) 313 #define MXC_F_PWRSEQ_LPPWEN_SPI0_POS 25 314 #define MXC_F_PWRSEQ_LPPWEN_SPI0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI0_POS)) 316 #define MXC_F_PWRSEQ_LPPWEN_LPCMP_POS 26 317 #define MXC_F_PWRSEQ_LPPWEN_LPCMP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_LPCMP_POS)) 327 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS 0 328 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS)) 330 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS 1 331 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS)) 333 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS 2 334 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS)) 336 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS 3 337 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS)) __IO uint32_t lppwst
Definition: pwrseq_regs.h:95
__IO uint32_t gp1
Definition: pwrseq_regs.h:101
__IO uint32_t lpwken0
Definition: pwrseq_regs.h:91
__IO uint32_t gp0
Definition: pwrseq_regs.h:100
__IO uint32_t lppwen
Definition: pwrseq_regs.h:96
Definition: pwrseq_regs.h:88
__IO uint32_t lpwkst1
Definition: pwrseq_regs.h:92
__IO uint32_t lpcn
Definition: pwrseq_regs.h:89
__IO uint32_t lpwkst0
Definition: pwrseq_regs.h:90
__IO uint32_t lpmemsd
Definition: pwrseq_regs.h:98
__IO uint32_t lpwken1
Definition: pwrseq_regs.h:93