MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
mxc_sys.h
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36 
42 #ifndef _MXC_MXC_SYS_H_
43 #define _MXC_MXC_SYS_H_
44 
45 #include "mxc_device.h"
46 #include "gcr_regs.h"
47 #include "lpgcr_regs.h"
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
54 typedef enum {
55  MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS,
56  MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS,
57  MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS,
58  MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS,
59  MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS,
60  MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS,
61  MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS,
62  MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS,
63  MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS,
64  MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS,
65  MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS,
66  MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS,
67  MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS,
68  MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS,
69  MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS,
70  MXC_SYS_RESET0_CNN = MXC_F_GCR_RST0_CNN_POS,
71  MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS,
72  MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS,
73  MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS,
74  MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS,
75  MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS,
76  /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
77  MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32),
78  MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32),
79  MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32),
80  MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32),
81  MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32),
82  MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32),
83  MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32),
84  MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32),
85  MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32),
86  // MXC_SYS_RESET1_BTLE = (MXC_F_GCR_RST1_BTLE_POS + 32), /**< Reset BTLE*/
87  MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32),
88  MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32),
89  MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32),
90  MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32),
91  /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
92  MXC_SYS_RESET_GPIO2 = (MXC_F_LPGCR_RST_GPIO2_POS + 64),
93  MXC_SYS_RESET_WDT2 = (MXC_F_LPGCR_RST_WDT2_POS + 64),
94  MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64),
95  MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64),
96  MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64),
97  MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64),
98 } mxc_sys_reset_t;
99 
101 typedef enum {
102  MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS,
103  MXC_SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PCLKDIS0_GPIO1_POS,
104  MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLKDIS0_DMA_POS,
105  MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLKDIS0_SPI1_POS,
106  MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLKDIS0_UART0_POS,
107  MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLKDIS0_UART1_POS,
108  MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLKDIS0_I2C0_POS,
109  MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS,
110  MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS,
111  MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS,
112  MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS,
113  MXC_SYS_PERIPH_CLOCK_ADC = MXC_F_GCR_PCLKDIS0_ADC_POS,
114  MXC_SYS_PERIPH_CLOCK_CNN = MXC_F_GCR_PCLKDIS0_CNN_POS,
115  MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLKDIS0_I2C1_POS,
116  MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS,
117  /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
118  MXC_SYS_PERIPH_CLOCK_UART2 = (MXC_F_GCR_PCLKDIS1_UART2_POS + 32),
119  MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32),
120  MXC_SYS_PERIPH_CLOCK_SMPHR = (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32),
121  MXC_SYS_PERIPH_CLOCK_OWIRE = (MXC_F_GCR_PCLKDIS1_OWM_POS + 32),
122  MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32),
123  MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32),
124  MXC_SYS_PERIPH_CLOCK_I2S = (MXC_F_GCR_PCLKDIS1_I2S_POS + 32),
125  MXC_SYS_PERIPH_CLOCK_SPI0 = (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32),
126  MXC_SYS_PERIPH_CLOCK_I2C2 = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32),
127  MXC_SYS_PERIPH_CLOCK_WDT0 = (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32),
128  MXC_SYS_PERIPH_CLOCK_CPU1 = (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32),
129  /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
130  MXC_SYS_PERIPH_CLOCK_GPIO2 = (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64),
131  MXC_SYS_PERIPH_CLOCK_WDT2 = (MXC_F_LPGCR_PCLKDIS_WDT2_POS + 64),
132  MXC_SYS_PERIPH_CLOCK_TMR4 = (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64),
133  MXC_SYS_PERIPH_CLOCK_TMR5 = (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64),
134  MXC_SYS_PERIPH_CLOCK_UART3 = (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64),
135  MXC_SYS_PERIPH_CLOCK_LPCOMP = (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64),
136 } mxc_sys_periph_clock_t;
137 
139 typedef enum {
140  MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO,
141  MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO,
142  MXC_SYS_CLOCK_ERFO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO,
143  MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO,
144  MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO,
145  MXC_SYS_CLOCK_EXTCLK = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
146 } mxc_sys_system_clock_t;
147 
148 #define MXC_SYS_USN_CHECKSUM_LEN 16
149 
150 /***** Function Prototypes *****/
151 
158 int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
159 
165 int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock);
166 
171 void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock);
172 
177 void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock);
178 
183 void MXC_SYS_RTCClockEnable (void);
184 
189 int MXC_SYS_RTCClockDisable();
190 
196 int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock);
197 
203 int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
204 
211 int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock);
212 
218 int MXC_SYS_Clock_Timeout (uint32_t ready);
223 void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
224 
225 #ifdef __cplusplus
226 }
227 #endif
228 
229 #endif /* _MXC_MXC_SYS_H_*/
#define MXC_F_GCR_RST0_SMPHR_POS
Definition: gcr_regs.h:221
#define MXC_F_GCR_RST0_RTC_POS
Definition: gcr_regs.h:218
#define MXC_F_GCR_RST0_UART1_POS
Definition: gcr_regs.h:209
#define MXC_F_GCR_RST1_I2C1_POS
Definition: gcr_regs.h:511
#define MXC_F_GCR_PCLKDIS0_DMA_POS
Definition: gcr_regs.h:416
#define MXC_F_LPGCR_PCLKDIS_GPIO2_POS
Definition: lpgcr_regs.h:137
#define MXC_F_GCR_RST1_OWM_POS
Definition: gcr_regs.h:517
#define MXC_F_GCR_RST0_DMA_POS
Definition: gcr_regs.h:182
#define MXC_F_GCR_PCLKDIS0_CNN_POS
Definition: gcr_regs.h:446
#define MXC_F_GCR_PCLKDIS0_UART1_POS
Definition: gcr_regs.h:425
#define MXC_F_GCR_PCLKDIS1_TRNG_POS
Definition: gcr_regs.h:564
#define MXC_F_GCR_PCLKDIS0_ADC_POS
Definition: gcr_regs.h:443
#define MXC_F_LPGCR_RST_TMR4_POS
Definition: lpgcr_regs.h:117
#define MXC_F_GCR_PCLKDIS0_GPIO0_POS
Definition: gcr_regs.h:410
#define MXC_F_GCR_PCLKDIS0_I2C0_POS
Definition: gcr_regs.h:428
#define MXC_F_LPGCR_RST_WDT2_POS
Definition: lpgcr_regs.h:114
#define MXC_F_GCR_RST1_I2S_POS
Definition: gcr_regs.h:535
#define MXC_F_LPGCR_RST_UART3_POS
Definition: lpgcr_regs.h:123
#define MXC_F_GCR_RST0_TRNG_POS
Definition: gcr_regs.h:224
#define MXC_F_LPGCR_RST_TMR5_POS
Definition: lpgcr_regs.h:120
#define MXC_F_GCR_RST0_WDT0_POS
Definition: gcr_regs.h:185
#define MXC_F_LPGCR_RST_LPCOMP_POS
Definition: lpgcr_regs.h:126
#define MXC_F_GCR_RST1_I2C2_POS
Definition: gcr_regs.h:538
#define MXC_F_GCR_PCLKDIS0_TMR1_POS
Definition: gcr_regs.h:434
#define MXC_F_GCR_PCLKDIS1_SMPHR_POS
Definition: gcr_regs.h:567
#define MXC_F_GCR_RST0_ADC_POS
Definition: gcr_regs.h:230
#define MXC_F_GCR_PCLKDIS1_I2C2_POS
Definition: gcr_regs.h:588
#define MXC_F_GCR_RST1_PT_POS
Definition: gcr_regs.h:514
#define MXC_F_GCR_PCLKDIS0_SPI1_POS
Definition: gcr_regs.h:419
#define MXC_F_GCR_RST0_CNN_POS
Definition: gcr_regs.h:227
#define MXC_F_GCR_RST1_CRC_POS
Definition: gcr_regs.h:523
#define MXC_F_GCR_PCLKDIS0_TMR2_POS
Definition: gcr_regs.h:437
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO
Definition: gcr_regs.h:276
#define MXC_F_LPGCR_PCLKDIS_TMR4_POS
Definition: lpgcr_regs.h:143
#define MXC_F_GCR_PCLKDIS0_TMR3_POS
Definition: gcr_regs.h:440
#define MXC_F_GCR_PCLKDIS1_OWM_POS
Definition: gcr_regs.h:570
#define MXC_F_GCR_PCLKDIS0_GPIO1_POS
Definition: gcr_regs.h:413
#define MXC_F_GCR_PCLKDIS1_AES_POS
Definition: gcr_regs.h:576
#define MXC_F_GCR_RST1_SPI0_POS
Definition: gcr_regs.h:529
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO
Definition: gcr_regs.h:274
#define MXC_F_GCR_RST0_SYS_POS
Definition: gcr_regs.h:242
#define MXC_F_LPGCR_PCLKDIS_LPCOMP_POS
Definition: lpgcr_regs.h:152
#define MXC_F_GCR_PCLKDIS1_WDT0_POS
Definition: gcr_regs.h:591
#define MXC_F_GCR_PCLKDIS1_UART2_POS
Definition: gcr_regs.h:561
#define MXC_F_GCR_RST1_SIMO_POS
Definition: gcr_regs.h:544
#define MXC_F_GCR_RST0_UART0_POS
Definition: gcr_regs.h:206
#define MXC_F_GCR_RST1_AES_POS
Definition: gcr_regs.h:526
#define MXC_F_GCR_RST0_TMR0_POS
Definition: gcr_regs.h:194
#define MXC_F_GCR_RST0_SPI1_POS
Definition: gcr_regs.h:212
#define MXC_F_GCR_PCLKDIS1_I2S_POS
Definition: gcr_regs.h:585
#define MXC_F_GCR_RST1_DVS_POS
Definition: gcr_regs.h:541
#define MXC_F_LPGCR_RST_GPIO2_POS
Definition: lpgcr_regs.h:111
#define MXC_F_LPGCR_PCLKDIS_UART3_POS
Definition: lpgcr_regs.h:149
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO
Definition: gcr_regs.h:278
#define MXC_F_LPGCR_PCLKDIS_WDT2_POS
Definition: lpgcr_regs.h:140
#define MXC_F_GCR_RST0_SOFT_POS
Definition: gcr_regs.h:236
#define MXC_F_GCR_PCLKDIS0_PT_POS
Definition: gcr_regs.h:452
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO
Definition: gcr_regs.h:282
#define MXC_F_GCR_PCLKDIS1_CPU1_POS
Definition: gcr_regs.h:594
#define MXC_F_GCR_RST0_PERIPH_POS
Definition: gcr_regs.h:239
#define MXC_F_GCR_RST0_TMR2_POS
Definition: gcr_regs.h:200
#define MXC_F_GCR_RST1_SMPHR_POS
Definition: gcr_regs.h:532
#define MXC_F_GCR_RST0_GPIO1_POS
Definition: gcr_regs.h:191
#define MXC_F_GCR_PCLKDIS1_CRC_POS
Definition: gcr_regs.h:573
#define MXC_F_GCR_PCLKDIS1_SPI0_POS
Definition: gcr_regs.h:579
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO
Definition: gcr_regs.h:280
#define MXC_F_GCR_RST1_CPU1_POS
Definition: gcr_regs.h:547
#define MXC_F_GCR_RST0_I2C0_POS
Definition: gcr_regs.h:215
#define MXC_F_GCR_PCLKDIS0_I2C1_POS
Definition: gcr_regs.h:449
#define MXC_F_GCR_PCLKDIS0_TMR0_POS
Definition: gcr_regs.h:431
#define MXC_F_GCR_RST0_GPIO0_POS
Definition: gcr_regs.h:188
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
Definition: gcr_regs.h:284
#define MXC_F_LPGCR_PCLKDIS_TMR5_POS
Definition: lpgcr_regs.h:146
#define MXC_F_GCR_RST0_UART2_POS
Definition: gcr_regs.h:233
#define MXC_F_GCR_RST0_TMR1_POS
Definition: gcr_regs.h:197
#define MXC_F_GCR_RST0_TMR3_POS
Definition: gcr_regs.h:203
#define MXC_F_GCR_PCLKDIS0_UART0_POS
Definition: gcr_regs.h:422
#define MXC_F_GCR_RST1_WDT1_POS
Definition: gcr_regs.h:520