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MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
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Macros | |
#define | MXC_F_GCR_PCLKDIS1_BTLE_POS 0 |
#define | MXC_F_GCR_PCLKDIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_BTLE_POS)) |
#define | MXC_F_GCR_PCLKDIS1_UART2_POS 1 |
#define | MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) |
#define | MXC_F_GCR_PCLKDIS1_TRNG_POS 2 |
#define | MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) |
#define | MXC_F_GCR_PCLKDIS1_SMPHR_POS 9 |
#define | MXC_F_GCR_PCLKDIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SMPHR_POS)) |
#define | MXC_F_GCR_PCLKDIS1_OWM_POS 13 |
#define | MXC_F_GCR_PCLKDIS1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWM_POS)) |
#define | MXC_F_GCR_PCLKDIS1_CRC_POS 14 |
#define | MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) |
#define | MXC_F_GCR_PCLKDIS1_AES_POS 15 |
#define | MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) |
#define | MXC_F_GCR_PCLKDIS1_SPI0_POS 16 |
#define | MXC_F_GCR_PCLKDIS1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI0_POS)) |
#define | MXC_F_GCR_PCLKDIS1_PCIF_POS 18 |
#define | MXC_F_GCR_PCLKDIS1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PCIF_POS)) |
#define | MXC_F_GCR_PCLKDIS1_I2S_POS 23 |
#define | MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) |
#define | MXC_F_GCR_PCLKDIS1_I2C2_POS 24 |
#define | MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) |
#define | MXC_F_GCR_PCLKDIS1_WDT0_POS 27 |
#define | MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) |
#define | MXC_F_GCR_PCLKDIS1_CPU1_POS 31 |
#define | MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) |
Peripheral Clock Disable.
#define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) |
PCLKDIS1_AES Mask
#define MXC_F_GCR_PCLKDIS1_AES_POS 15 |
PCLKDIS1_AES Position
#define MXC_F_GCR_PCLKDIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_BTLE_POS)) |
PCLKDIS1_BTLE Mask
#define MXC_F_GCR_PCLKDIS1_BTLE_POS 0 |
PCLKDIS1_BTLE Position
#define MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) |
PCLKDIS1_CPU1 Mask
#define MXC_F_GCR_PCLKDIS1_CPU1_POS 31 |
PCLKDIS1_CPU1 Position
#define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) |
PCLKDIS1_CRC Mask
#define MXC_F_GCR_PCLKDIS1_CRC_POS 14 |
PCLKDIS1_CRC Position
#define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) |
PCLKDIS1_I2C2 Mask
#define MXC_F_GCR_PCLKDIS1_I2C2_POS 24 |
PCLKDIS1_I2C2 Position
#define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) |
PCLKDIS1_I2S Mask
#define MXC_F_GCR_PCLKDIS1_I2S_POS 23 |
PCLKDIS1_I2S Position
#define MXC_F_GCR_PCLKDIS1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWM_POS)) |
PCLKDIS1_OWM Mask
#define MXC_F_GCR_PCLKDIS1_OWM_POS 13 |
PCLKDIS1_OWM Position
#define MXC_F_GCR_PCLKDIS1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PCIF_POS)) |
PCLKDIS1_PCIF Mask
#define MXC_F_GCR_PCLKDIS1_PCIF_POS 18 |
PCLKDIS1_PCIF Position
#define MXC_F_GCR_PCLKDIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SMPHR_POS)) |
PCLKDIS1_SMPHR Mask
#define MXC_F_GCR_PCLKDIS1_SMPHR_POS 9 |
PCLKDIS1_SMPHR Position
#define MXC_F_GCR_PCLKDIS1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI0_POS)) |
PCLKDIS1_SPI0 Mask
#define MXC_F_GCR_PCLKDIS1_SPI0_POS 16 |
PCLKDIS1_SPI0 Position
#define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) |
PCLKDIS1_TRNG Mask
#define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 |
PCLKDIS1_TRNG Position
#define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) |
PCLKDIS1_UART2 Mask
#define MXC_F_GCR_PCLKDIS1_UART2_POS 1 |
PCLKDIS1_UART2 Position
#define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) |
PCLKDIS1_WDT0 Mask
#define MXC_F_GCR_PCLKDIS1_WDT0_POS 27 |
PCLKDIS1_WDT0 Position