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MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
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Macros | |
#define | MXC_F_FCR_REG1_ACEN_POS 0 |
#define | MXC_F_FCR_REG1_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACEN_POS)) |
#define | MXC_F_FCR_REG1_ACRUN_POS 1 |
#define | MXC_F_FCR_REG1_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACRUN_POS)) |
#define | MXC_F_FCR_REG1_LDTRM_POS 2 |
#define | MXC_F_FCR_REG1_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_REG1_LDTRM_POS)) |
#define | MXC_F_FCR_REG1_GAININV_POS 3 |
#define | MXC_F_FCR_REG1_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_REG1_GAININV_POS)) |
#define | MXC_F_FCR_REG1_ATOMIC_POS 4 |
#define | MXC_F_FCR_REG1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ATOMIC_POS)) |
#define | MXC_F_FCR_REG1_MU_POS 8 |
#define | MXC_F_FCR_REG1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_REG1_MU_POS)) |
Register 1.
#define MXC_F_FCR_REG1_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACEN_POS)) |
REG1_ACEN Mask
#define MXC_F_FCR_REG1_ACEN_POS 0 |
REG1_ACEN Position
#define MXC_F_FCR_REG1_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACRUN_POS)) |
REG1_ACRUN Mask
#define MXC_F_FCR_REG1_ACRUN_POS 1 |
REG1_ACRUN Position
#define MXC_F_FCR_REG1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ATOMIC_POS)) |
REG1_ATOMIC Mask
#define MXC_F_FCR_REG1_ATOMIC_POS 4 |
REG1_ATOMIC Position
#define MXC_F_FCR_REG1_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_REG1_GAININV_POS)) |
REG1_GAININV Mask
#define MXC_F_FCR_REG1_GAININV_POS 3 |
REG1_GAININV Position
#define MXC_F_FCR_REG1_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_REG1_LDTRM_POS)) |
REG1_LDTRM Mask
#define MXC_F_FCR_REG1_LDTRM_POS 2 |
REG1_LDTRM Position
#define MXC_F_FCR_REG1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_REG1_MU_POS)) |
REG1_MU Mask
#define MXC_F_FCR_REG1_MU_POS 8 |
REG1_MU Position