MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
simo_regs.h
1 
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38 
39 #ifndef _SIMO_REGS_H_
40 #define _SIMO_REGS_H_
41 
42 /* **** Includes **** */
43 #include <stdint.h>
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 #if defined (__ICCARM__)
50  #pragma system_include
51 #endif
52 
53 #if defined (__CC_ARM)
54  #pragma anon_unions
55 #endif
56 /*
58  If types are not defined elsewhere (CMSIS) define them here
59 */
60 #ifndef __IO
61 #define __IO volatile
62 #endif
63 #ifndef __I
64 #define __I volatile const
65 #endif
66 #ifndef __O
67 #define __O volatile
68 #endif
69 #ifndef __R
70 #define __R volatile const
71 #endif
72 
74 /* **** Definitions **** */
75 
87 typedef struct {
88  __R uint32_t rsv_0x0;
89  __IO uint32_t vrego_a;
90  __IO uint32_t vrego_b;
91  __IO uint32_t vrego_c;
92  __IO uint32_t vrego_d;
93  __IO uint32_t ipka;
94  __IO uint32_t ipkb;
95  __IO uint32_t maxton;
96  __I uint32_t iload_a;
97  __I uint32_t iload_b;
98  __I uint32_t iload_c;
99  __I uint32_t iload_d;
100  __IO uint32_t buck_alert_thr_a;
101  __IO uint32_t buck_alert_thr_b;
102  __IO uint32_t buck_alert_thr_c;
103  __IO uint32_t buck_alert_thr_d;
104  __I uint32_t buck_out_ready;
105  __I uint32_t zero_cross_cal_a;
106  __I uint32_t zero_cross_cal_b;
107  __I uint32_t zero_cross_cal_c;
108  __I uint32_t zero_cross_cal_d;
110 
111 /* Register offsets for module SIMO */
118  #define MXC_R_SIMO_VREGO_A ((uint32_t)0x00000004UL)
119  #define MXC_R_SIMO_VREGO_B ((uint32_t)0x00000008UL)
120  #define MXC_R_SIMO_VREGO_C ((uint32_t)0x0000000CUL)
121  #define MXC_R_SIMO_VREGO_D ((uint32_t)0x00000010UL)
122  #define MXC_R_SIMO_IPKA ((uint32_t)0x00000014UL)
123  #define MXC_R_SIMO_IPKB ((uint32_t)0x00000018UL)
124  #define MXC_R_SIMO_MAXTON ((uint32_t)0x0000001CUL)
125  #define MXC_R_SIMO_ILOAD_A ((uint32_t)0x00000020UL)
126  #define MXC_R_SIMO_ILOAD_B ((uint32_t)0x00000024UL)
127  #define MXC_R_SIMO_ILOAD_C ((uint32_t)0x00000028UL)
128  #define MXC_R_SIMO_ILOAD_D ((uint32_t)0x0000002CUL)
129  #define MXC_R_SIMO_BUCK_ALERT_THR_A ((uint32_t)0x00000030UL)
130  #define MXC_R_SIMO_BUCK_ALERT_THR_B ((uint32_t)0x00000034UL)
131  #define MXC_R_SIMO_BUCK_ALERT_THR_C ((uint32_t)0x00000038UL)
132  #define MXC_R_SIMO_BUCK_ALERT_THR_D ((uint32_t)0x0000003CUL)
133  #define MXC_R_SIMO_BUCK_OUT_READY ((uint32_t)0x00000040UL)
134  #define MXC_R_SIMO_ZERO_CROSS_CAL_A ((uint32_t)0x00000044UL)
135  #define MXC_R_SIMO_ZERO_CROSS_CAL_B ((uint32_t)0x00000048UL)
136  #define MXC_R_SIMO_ZERO_CROSS_CAL_C ((uint32_t)0x0000004CUL)
137  #define MXC_R_SIMO_ZERO_CROSS_CAL_D ((uint32_t)0x00000050UL)
146  #define MXC_F_SIMO_VREGO_A_VSETA_POS 0
147  #define MXC_F_SIMO_VREGO_A_VSETA ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_A_VSETA_POS))
149  #define MXC_F_SIMO_VREGO_A_RANGEA_POS 7
150  #define MXC_F_SIMO_VREGO_A_RANGEA ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_A_RANGEA_POS))
160  #define MXC_F_SIMO_VREGO_B_VSETB_POS 0
161  #define MXC_F_SIMO_VREGO_B_VSETB ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_B_VSETB_POS))
163  #define MXC_F_SIMO_VREGO_B_RANGEB_POS 7
164  #define MXC_F_SIMO_VREGO_B_RANGEB ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_B_RANGEB_POS))
174  #define MXC_F_SIMO_VREGO_C_VSETC_POS 0
175  #define MXC_F_SIMO_VREGO_C_VSETC ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_C_VSETC_POS))
177  #define MXC_F_SIMO_VREGO_C_RANGEC_POS 7
178  #define MXC_F_SIMO_VREGO_C_RANGEC ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_C_RANGEC_POS))
188  #define MXC_F_SIMO_VREGO_D_VSETD_POS 0
189  #define MXC_F_SIMO_VREGO_D_VSETD ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_D_VSETD_POS))
191  #define MXC_F_SIMO_VREGO_D_RANGED_POS 7
192  #define MXC_F_SIMO_VREGO_D_RANGED ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_D_RANGED_POS))
202  #define MXC_F_SIMO_IPKA_IPKSETA_POS 0
203  #define MXC_F_SIMO_IPKA_IPKSETA ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETA_POS))
205  #define MXC_F_SIMO_IPKA_IPKSETB_POS 4
206  #define MXC_F_SIMO_IPKA_IPKSETB ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETB_POS))
216  #define MXC_F_SIMO_IPKB_IPKSETC_POS 0
217  #define MXC_F_SIMO_IPKB_IPKSETC ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETC_POS))
219  #define MXC_F_SIMO_IPKB_IPKSETD_POS 4
220  #define MXC_F_SIMO_IPKB_IPKSETD ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETD_POS))
230  #define MXC_F_SIMO_MAXTON_TONSET_POS 0
231  #define MXC_F_SIMO_MAXTON_TONSET ((uint32_t)(0xFUL << MXC_F_SIMO_MAXTON_TONSET_POS))
241  #define MXC_F_SIMO_ILOAD_A_ILOADA_POS 0
242  #define MXC_F_SIMO_ILOAD_A_ILOADA ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_A_ILOADA_POS))
252  #define MXC_F_SIMO_ILOAD_B_ILOADB_POS 0
253  #define MXC_F_SIMO_ILOAD_B_ILOADB ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_B_ILOADB_POS))
263  #define MXC_F_SIMO_ILOAD_C_ILOADC_POS 0
264  #define MXC_F_SIMO_ILOAD_C_ILOADC ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_C_ILOADC_POS))
274  #define MXC_F_SIMO_ILOAD_D_ILOADD_POS 0
275  #define MXC_F_SIMO_ILOAD_D_ILOADD ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_D_ILOADD_POS))
285  #define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS 0
286  #define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS))
296  #define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS 0
297  #define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS))
307  #define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS 0
308  #define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS))
318  #define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS 0
319  #define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS))
329  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS 3
330  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS))
332  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS 2
333  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS))
335  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS 1
336  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS))
338  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS 0
339  #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS))
349  #define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCLA_POS 0
350  #define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCLA ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCLA_POS))
360  #define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCLB_POS 0
361  #define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCLB ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCLB_POS))
371  #define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCLC_POS 0
372  #define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCLC ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCLC_POS))
382  #define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCLD_POS 0
383  #define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCLD ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCLD_POS))
387 #ifdef __cplusplus
388 }
389 #endif
390 
391 #endif /* _SIMO_REGS_H_ */
392 
__IO uint32_t vrego_a
Definition: simo_regs.h:89
__IO uint32_t ipka
Definition: simo_regs.h:93
__IO uint32_t ipkb
Definition: simo_regs.h:94
__IO uint32_t buck_alert_thr_c
Definition: simo_regs.h:102
__IO uint32_t vrego_b
Definition: simo_regs.h:90
__IO uint32_t maxton
Definition: simo_regs.h:95
__IO uint32_t vrego_c
Definition: simo_regs.h:91
__I uint32_t iload_d
Definition: simo_regs.h:99
__I uint32_t iload_b
Definition: simo_regs.h:97
__IO uint32_t vrego_d
Definition: simo_regs.h:92
__I uint32_t buck_out_ready
Definition: simo_regs.h:104
__I uint32_t iload_c
Definition: simo_regs.h:98
__IO uint32_t buck_alert_thr_b
Definition: simo_regs.h:101
__I uint32_t zero_cross_cal_b
Definition: simo_regs.h:106
__I uint32_t zero_cross_cal_a
Definition: simo_regs.h:105
__I uint32_t zero_cross_cal_c
Definition: simo_regs.h:107
__IO uint32_t buck_alert_thr_a
Definition: simo_regs.h:100
__I uint32_t iload_a
Definition: simo_regs.h:96
Definition: simo_regs.h:87
__IO uint32_t buck_alert_thr_d
Definition: simo_regs.h:103
__I uint32_t zero_cross_cal_d
Definition: simo_regs.h:108