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MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
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Peripheral Clock Divider.
#define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) |
PCLKDIV_ADCFRQ Mask
#define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 |
PCLKDIV_ADCFRQ Position
#define MXC_F_GCR_PCLKDIV_CNNCLKDIV ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)) |
PCLKDIV_CNNCLKDIV Mask
#define MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS 14 |
PCLKDIV_CNNCLKDIV Position
#define MXC_F_GCR_PCLKDIV_CNNCLKSEL ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS)) |
PCLKDIV_CNNCLKSEL Mask
#define MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS 17 |
PCLKDIV_CNNCLKSEL Position
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV1 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) |
PCLKDIV_CNNCLKDIV_DIV1 Setting
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) |
PCLKDIV_CNNCLKDIV_DIV16 Setting
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV2 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) |
PCLKDIV_CNNCLKDIV_DIV2 Setting
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) |
PCLKDIV_CNNCLKDIV_DIV4 Setting
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) |
PCLKDIV_CNNCLKDIV_DIV8 Setting
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 ((uint32_t)0x4UL) |
PCLKDIV_CNNCLKDIV_DIV1 Value
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 ((uint32_t)0x3UL) |
PCLKDIV_CNNCLKDIV_DIV16 Value
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 ((uint32_t)0x0UL) |
PCLKDIV_CNNCLKDIV_DIV2 Value
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 ((uint32_t)0x1UL) |
PCLKDIV_CNNCLKDIV_DIV4 Value
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 ((uint32_t)0x2UL) |
PCLKDIV_CNNCLKDIV_DIV8 Value