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MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
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Macros | |
#define | MXC_F_FLC_CLKDIV_CLKDIV_POS 0 |
#define | MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) |
Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) |
CLKDIV_CLKDIV Mask
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 |
CLKDIV_CLKDIV Position