MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655

Macros

#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS   0
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS   1
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS   2
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS))
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS   3
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS))
 

Detailed Description

Low Power Memory Shutdown Control.

Macro Definition Documentation

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM0SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS))

LPMEMSD_SRAM0SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS   0

LPMEMSD_SRAM0SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM1SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS))

LPMEMSD_SRAM1SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS   1

LPMEMSD_SRAM1SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM2SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS))

LPMEMSD_SRAM2SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS   2

LPMEMSD_SRAM2SD Position

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM3SD

#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS))

LPMEMSD_SRAM3SD Mask

◆ MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS

#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS   3

LPMEMSD_SRAM3SD Position