MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
i2c_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
8  *
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14  * Software is furnished to do so, subject to the following conditions:
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31  * The mere transfer of this software does not imply any licenses
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39 
40 #ifndef _I2C_REGS_H_
41 #define _I2C_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t ctrl;
90  __IO uint32_t status;
91  __IO uint32_t intfl0;
92  __IO uint32_t inten0;
93  __IO uint32_t intfl1;
94  __IO uint32_t inten1;
95  __IO uint32_t fifolen;
96  __IO uint32_t rxctrl0;
97  __IO uint32_t rxctrl1;
98  __IO uint32_t txctrl0;
99  __IO uint32_t txctrl1;
100  __IO uint32_t fifo;
101  __IO uint32_t mstctrl;
102  __IO uint32_t clklo;
103  __IO uint32_t clkhi;
104  __IO uint32_t hsclk;
105  __IO uint32_t timeout;
106  __R uint32_t rsv_0x44;
107  __IO uint32_t dma;
108  __IO uint32_t slave;
110 
111 /* Register offsets for module I2C */
118  #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL)
119  #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL)
120  #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL)
121  #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL)
122  #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL)
123  #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL)
124  #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL)
125  #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL)
126  #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL)
127  #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL)
128  #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL)
129  #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL)
130  #define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL)
131  #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL)
132  #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL)
133  #define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL)
134  #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL)
135  #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL)
136  #define MXC_R_I2C_SLAVE ((uint32_t)0x0000004CUL)
145  #define MXC_F_I2C_CTRL_EN_POS 0
146  #define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS))
148  #define MXC_F_I2C_CTRL_MST_MODE_POS 1
149  #define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS))
151  #define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2
152  #define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS))
154  #define MXC_F_I2C_CTRL_IRXM_EN_POS 3
155  #define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS))
157  #define MXC_F_I2C_CTRL_IRXM_ACK_POS 4
158  #define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS))
160  #define MXC_F_I2C_CTRL_SCL_OUT_POS 6
161  #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS))
163  #define MXC_F_I2C_CTRL_SDA_OUT_POS 7
164  #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS))
166  #define MXC_F_I2C_CTRL_SCL_POS 8
167  #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS))
169  #define MXC_F_I2C_CTRL_SDA_POS 9
170  #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS))
172  #define MXC_F_I2C_CTRL_BB_MODE_POS 10
173  #define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS))
175  #define MXC_F_I2C_CTRL_READ_POS 11
176  #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS))
178  #define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12
179  #define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS))
181  #define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13
182  #define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS))
184  #define MXC_F_I2C_CTRL_HS_EN_POS 15
185  #define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS))
195  #define MXC_F_I2C_STATUS_BUSY_POS 0
196  #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS))
198  #define MXC_F_I2C_STATUS_RX_EM_POS 1
199  #define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS))
201  #define MXC_F_I2C_STATUS_RX_FULL_POS 2
202  #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS))
204  #define MXC_F_I2C_STATUS_TX_EM_POS 3
205  #define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS))
207  #define MXC_F_I2C_STATUS_TX_FULL_POS 4
208  #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS))
210  #define MXC_F_I2C_STATUS_MST_BUSY_POS 5
211  #define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS))
221  #define MXC_F_I2C_INTFL0_DONE_POS 0
222  #define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS))
224  #define MXC_F_I2C_INTFL0_IRXM_POS 1
225  #define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS))
227  #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2
228  #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS))
230  #define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3
231  #define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS))
233  #define MXC_F_I2C_INTFL0_RX_THD_POS 4
234  #define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS))
236  #define MXC_F_I2C_INTFL0_TX_THD_POS 5
237  #define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS))
239  #define MXC_F_I2C_INTFL0_STOP_POS 6
240  #define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS))
242  #define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7
243  #define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS))
245  #define MXC_F_I2C_INTFL0_ARB_ERR_POS 8
246  #define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS))
248  #define MXC_F_I2C_INTFL0_TO_ERR_POS 9
249  #define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS))
251  #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10
252  #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS))
254  #define MXC_F_I2C_INTFL0_DATA_ERR_POS 11
255  #define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS))
257  #define MXC_F_I2C_INTFL0_DNR_ERR_POS 12
258  #define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS))
260  #define MXC_F_I2C_INTFL0_START_ERR_POS 13
261  #define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS))
263  #define MXC_F_I2C_INTFL0_STOP_ERR_POS 14
264  #define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS))
266  #define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15
267  #define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS))
269  #define MXC_F_I2C_INTFL0_MAMI_POS 16
270  #define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS))
272  #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22
273  #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS))
275  #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23
276  #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS))
286  #define MXC_F_I2C_INTEN0_DONE_POS 0
287  #define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS))
289  #define MXC_F_I2C_INTEN0_IRXM_POS 1
290  #define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS))
292  #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2
293  #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS))
295  #define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3
296  #define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS))
298  #define MXC_F_I2C_INTEN0_RX_THD_POS 4
299  #define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS))
301  #define MXC_F_I2C_INTEN0_TX_THD_POS 5
302  #define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS))
304  #define MXC_F_I2C_INTEN0_STOP_POS 6
305  #define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS))
307  #define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7
308  #define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS))
310  #define MXC_F_I2C_INTEN0_ARB_ERR_POS 8
311  #define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS))
313  #define MXC_F_I2C_INTEN0_TO_ERR_POS 9
314  #define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS))
316  #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10
317  #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS))
319  #define MXC_F_I2C_INTEN0_DATA_ERR_POS 11
320  #define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS))
322  #define MXC_F_I2C_INTEN0_DNR_ERR_POS 12
323  #define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS))
325  #define MXC_F_I2C_INTEN0_START_ERR_POS 13
326  #define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS))
328  #define MXC_F_I2C_INTEN0_STOP_ERR_POS 14
329  #define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS))
331  #define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15
332  #define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS))
334  #define MXC_F_I2C_INTEN0_MAMI_POS 16
335  #define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS))
337  #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22
338  #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS))
340  #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23
341  #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS))
351  #define MXC_F_I2C_INTFL1_RX_OV_POS 0
352  #define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS))
354  #define MXC_F_I2C_INTFL1_TX_UN_POS 1
355  #define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS))
357  #define MXC_F_I2C_INTFL1_START_POS 2
358  #define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS))
368  #define MXC_F_I2C_INTEN1_RX_OV_POS 0
369  #define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS))
371  #define MXC_F_I2C_INTEN1_TX_UN_POS 1
372  #define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS))
374  #define MXC_F_I2C_INTEN1_START_POS 2
375  #define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS))
385  #define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0
386  #define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS))
388  #define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8
389  #define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS))
399  #define MXC_F_I2C_RXCTRL0_DNR_POS 0
400  #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS))
402  #define MXC_F_I2C_RXCTRL0_FLUSH_POS 7
403  #define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS))
405  #define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8
406  #define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS))
416  #define MXC_F_I2C_RXCTRL1_CNT_POS 0
417  #define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS))
419  #define MXC_F_I2C_RXCTRL1_LVL_POS 8
420  #define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS))
430  #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0
431  #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS))
433  #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1
434  #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS))
436  #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2
437  #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS))
439  #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3
440  #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS))
442  #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4
443  #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS))
445  #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5
446  #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS))
448  #define MXC_F_I2C_TXCTRL0_FLUSH_POS 7
449  #define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS))
451  #define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8
452  #define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS))
462  #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0
463  #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS))
465  #define MXC_F_I2C_TXCTRL1_LVL_POS 8
466  #define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS))
476  #define MXC_F_I2C_FIFO_DATA_POS 0
477  #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS))
487  #define MXC_F_I2C_MSTCTRL_START_POS 0
488  #define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS))
490  #define MXC_F_I2C_MSTCTRL_RESTART_POS 1
491  #define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS))
493  #define MXC_F_I2C_MSTCTRL_STOP_POS 2
494  #define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS))
496  #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7
497  #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS))
507  #define MXC_F_I2C_CLKLO_LO_POS 0
508  #define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS))
518  #define MXC_F_I2C_CLKHI_HI_POS 0
519  #define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS))
529  #define MXC_F_I2C_HSCLK_LO_POS 0
530  #define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS))
532  #define MXC_F_I2C_HSCLK_HI_POS 8
533  #define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS))
543  #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0
544  #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS))
554  #define MXC_F_I2C_DMA_TX_EN_POS 0
555  #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS))
557  #define MXC_F_I2C_DMA_RX_EN_POS 1
558  #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS))
568  #define MXC_F_I2C_SLAVE_ADDR_POS 0
569  #define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS))
571  #define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15
572  #define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS))
576 #ifdef __cplusplus
577 }
578 #endif
579 
580 #endif /* _I2C_REGS_H_ */
__IO uint32_t fifo
Definition: i2c_regs.h:100
__IO uint32_t dma
Definition: i2c_regs.h:107
__IO uint32_t inten1
Definition: i2c_regs.h:94
__IO uint32_t hsclk
Definition: i2c_regs.h:104
__IO uint32_t inten0
Definition: i2c_regs.h:92
__IO uint32_t ctrl
Definition: i2c_regs.h:89
__IO uint32_t slave
Definition: i2c_regs.h:108
__IO uint32_t fifolen
Definition: i2c_regs.h:95
__IO uint32_t intfl0
Definition: i2c_regs.h:91
__IO uint32_t clklo
Definition: i2c_regs.h:102
Definition: i2c_regs.h:88
__IO uint32_t txctrl1
Definition: i2c_regs.h:99
__IO uint32_t timeout
Definition: i2c_regs.h:105
__IO uint32_t mstctrl
Definition: i2c_regs.h:101
__IO uint32_t rxctrl1
Definition: i2c_regs.h:97
__IO uint32_t intfl1
Definition: i2c_regs.h:93
__IO uint32_t txctrl0
Definition: i2c_regs.h:98
__IO uint32_t status
Definition: i2c_regs.h:90
__IO uint32_t rxctrl0
Definition: i2c_regs.h:96
__IO uint32_t clkhi
Definition: i2c_regs.h:103