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MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
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Clock Control.
#define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) |
CLKCTRL_ERFO_EN Mask
#define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 |
CLKCTRL_ERFO_EN Position
#define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) |
CLKCTRL_ERFO_RDY Mask
#define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 |
CLKCTRL_ERFO_RDY Position
#define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) |
CLKCTRL_ERTCO_EN Mask
#define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 |
CLKCTRL_ERTCO_EN Position
#define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) |
CLKCTRL_ERTCO_RDY Mask
#define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 |
CLKCTRL_ERTCO_RDY Position
#define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) |
CLKCTRL_IBRO_EN Mask
#define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 |
CLKCTRL_IBRO_EN Position
#define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) |
CLKCTRL_IBRO_RDY Mask
#define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 |
CLKCTRL_IBRO_RDY Position
#define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) |
CLKCTRL_IBRO_VS Mask
#define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 |
CLKCTRL_IBRO_VS Position
#define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) |
CLKCTRL_INRO_RDY Mask
#define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 |
CLKCTRL_INRO_RDY Position
#define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) |
CLKCTRL_IPO_EN Mask
#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 |
CLKCTRL_IPO_EN Position
#define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) |
CLKCTRL_IPO_RDY Mask
#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 |
CLKCTRL_IPO_RDY Position
#define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) |
CLKCTRL_ISO_EN Mask
#define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 |
CLKCTRL_ISO_EN Position
#define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) |
CLKCTRL_ISO_RDY Mask
#define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 |
CLKCTRL_ISO_RDY Position
#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) |
CLKCTRL_SYSCLK_DIV Mask
#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 |
CLKCTRL_SYSCLK_DIV Position
#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) |
CLKCTRL_SYSCLK_RDY Mask
#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 |
CLKCTRL_SYSCLK_RDY Position
#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) |
CLKCTRL_SYSCLK_SEL Mask
#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 |
CLKCTRL_SYSCLK_SEL Position
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV1 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV128 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV16 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV2 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV32 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV4 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV64 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) |
CLKCTRL_SYSCLK_DIV_DIV8 Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) |
CLKCTRL_SYSCLK_SEL_ERFO Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) |
CLKCTRL_SYSCLK_SEL_ERTCO Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) |
CLKCTRL_SYSCLK_SEL_EXTCLK Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) |
CLKCTRL_SYSCLK_SEL_IBRO Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) |
CLKCTRL_SYSCLK_SEL_INRO Setting
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) |
CLKCTRL_SYSCLK_SEL_IPO Setting
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) |
CLKCTRL_SYSCLK_DIV_DIV1 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) |
CLKCTRL_SYSCLK_DIV_DIV128 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) |
CLKCTRL_SYSCLK_DIV_DIV16 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) |
CLKCTRL_SYSCLK_DIV_DIV2 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) |
CLKCTRL_SYSCLK_DIV_DIV32 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) |
CLKCTRL_SYSCLK_DIV_DIV4 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) |
CLKCTRL_SYSCLK_DIV_DIV64 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) |
CLKCTRL_SYSCLK_DIV_DIV8 Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) |
CLKCTRL_SYSCLK_SEL_ERFO Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) |
CLKCTRL_SYSCLK_SEL_ERTCO Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) |
CLKCTRL_SYSCLK_SEL_EXTCLK Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) |
CLKCTRL_SYSCLK_SEL_IBRO Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) |
CLKCTRL_SYSCLK_SEL_INRO Value
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) |
CLKCTRL_SYSCLK_SEL_IPO Value