52 typedef void (*mxc_tpu_complete_t) (
void* req,
int result);
55 MXC_TPU_FEATURE_DMA = 1 << 0,
56 MXC_TPU_FEATURE_ECC = 1 << 1,
57 MXC_TPU_FEATURE_CRC = 1 << 2,
58 MXC_TPU_FEATURE_MAA = 1 << 3,
59 MXC_TPU_FEATURE_HASH = 1 << 4,
60 MXC_TPU_FEATURE_CIPHER = 1 << 5,
61 MXC_TPU_FEATURE_TRNG = 1 << 6
69 struct _mxc_tpu_dma_req_t {
70 uint8_t* sourceBuffer;
73 mxc_tpu_complete_t callback;
74 }
typedef mxc_tpu_dma_req_t;
77 MXC_TPU_DMA_READ_FIFO_DMA = MXC_V_TPU_CTRL_RDSRC_DMAORAPB,
78 MXC_TPU_DMA_READ_FIFO_RNG = MXC_V_TPU_CTRL_RDSRC_RNG
79 } mxc_tpu_dma_read_source_t;
82 MXC_TPU_DMA_WRITE_FIFO_CIPHER = MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT,
83 MXC_TPU_DMA_WRITE_FIFO_READ_FIFO = MXC_V_TPU_CTRL_WRSRC_READFIFO,
84 MXC_TPU_DMA_WRITE_FIFO_NONE = MXC_V_TPU_CTRL_WRSRC_NONE
85 } mxc_tpu_dma_write_source_t;
91 struct _mxc_tpu_ecc_req_t {
95 mxc_tpu_complete_t callback;
96 }
typedef mxc_tpu_ecc_req_t;
98 struct _mxc_tpu_crc_req_t {
102 mxc_tpu_complete_t callback;
103 }
typedef mxc_tpu_crc_req_t;
110 MXC_TPU_MAA_EXP = MXC_V_TPU_MAA_CTRL_CLC_EXP,
111 MXC_TPU_MAA_SQ = MXC_V_TPU_MAA_CTRL_CLC_SQ,
112 MXC_TPU_MAA_MUL = MXC_V_TPU_MAA_CTRL_CLC_MUL,
113 MXC_TPU_MAA_SQMUL = MXC_V_TPU_MAA_CTRL_CLC_SQMUL,
114 MXC_TPU_MAA_ADD = MXC_V_TPU_MAA_CTRL_CLC_ADD,
115 MXC_TPU_MAA_SUB = MXC_V_TPU_MAA_CTRL_CLC_SUB,
117 } mxc_tpu_maa_operation_t;
119 struct _mxc_tpu_maa_req_t {
126 mxc_tpu_maa_operation_t op;
127 mxc_tpu_complete_t callback;
128 }
typedef mxc_tpu_maa_req_t;
131 MXC_TPU_MAA_REG_OPA = MXC_F_TPU_MAA_CTRL_AMS_POS,
132 MXC_TPU_MAA_REG_OPB = MXC_F_TPU_MAA_CTRL_BMS_POS,
133 MXC_TPU_MAA_REG_EXP = MXC_F_TPU_MAA_CTRL_EMS_POS,
134 MXC_TPU_MAA_REG_MOD = MXC_F_TPU_MAA_CTRL_MMS_POS
135 } mxc_tpu_maa_register_t;
141 struct _mxc_tpu_hash_req_t {
145 mxc_tpu_complete_t callback;
146 }
typedef mxc_tpu_hash_req_t;
149 MXC_TPU_HASH_DIS = MXC_V_TPU_HASH_CTRL_HASH_DIS,
150 MXC_TPU_HASH_SHA1 = MXC_V_TPU_HASH_CTRL_HASH_SHA1,
151 MXC_TPU_HASH_SHA224 = MXC_V_TPU_HASH_CTRL_HASH_SHA224,
152 MXC_TPU_HASH_SHA256 = MXC_V_TPU_HASH_CTRL_HASH_SHA256,
153 MXC_TPU_HASH_SHA384 = MXC_V_TPU_HASH_CTRL_HASH_SHA384,
154 MXC_TPU_HASH_SHA512 = MXC_V_TPU_HASH_CTRL_HASH_SHA512
155 } mxc_tpu_hash_func_t;
158 MXC_TPU_HASH_SOURCE_INFIFO = 0,
159 MXC_TPU_HASH_SOURCE_OUTFIFO = 1
160 } mxc_tpu_hash_source_t;
166 struct _mxc_tpu_cipher_req_t {
171 mxc_tpu_complete_t callback;
172 }
typedef mxc_tpu_cipher_req_t;
175 MXC_TPU_MODE_ECB = MXC_V_TPU_CIPHER_CTRL_MODE_ECB,
176 MXC_TPU_MODE_CBC = MXC_V_TPU_CIPHER_CTRL_MODE_CBC,
177 MXC_TPU_MODE_CFB = MXC_V_TPU_CIPHER_CTRL_MODE_CFB,
178 MXC_TPU_MODE_CTR = MXC_V_TPU_CIPHER_CTRL_MODE_CTR,
180 } mxc_tpu_cipher_mode_t;
183 MXC_TPU_CIPHER_DIS = MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS,
184 MXC_TPU_CIPHER_AES128 = MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128,
185 MXC_TPU_CIPHER_AES192 = MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192,
186 MXC_TPU_CIPHER_AES256 = MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256,
187 MXC_TPU_CIPHER_DES = MXC_V_TPU_CIPHER_CTRL_CIPHER_DES,
188 MXC_TPU_CIPHER_TDES = MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES
192 MXC_TPU_CIPHER_KEY_SOFTWARE = 0,
193 MXC_TPU_CIPHER_KEY_AES_KEY2 = 2,
194 MXC_TPU_CIPHER_KEY_AES_KEY3 = 3
195 } mxc_tpu_cipher_key_t;
212 int MXC_TPU_Init (uint32_t features);
219 uint32_t MXC_TPU_CheckFeatures (
void);
226 void MXC_TPU_IntEnable (
int enable);
233 int MXC_TPU_Ready (
void);
239 void MXC_TPU_DoneClear (uint32_t features);
246 uint32_t MXC_TPU_Done (
void);
252 void MXC_TPU_Reset (uint32_t features);
259 void MXC_TPU_CacheInvalidate (
void);
269 int MXC_TPU_Shutdown (uint32_t features);
276 uint32_t MXC_TPU_GetEnabledFeatures (
void);
282 void MXC_TPU_Handler (
void);
295 void MXC_TPU_DMA_SetReadSource (mxc_tpu_dma_read_source_t source);
303 mxc_tpu_dma_read_source_t MXC_TPU_DMA_GetReadSource (
void);
311 void MXC_TPU_DMA_SetWriteSource (mxc_tpu_dma_write_source_t source);
319 mxc_tpu_dma_write_source_t MXC_TPU_DMA_GetWriteSource (
void);
328 void MXC_TPU_DMA_SetSource (uint8_t* source);
335 void MXC_TPU_DMA_SetDestination (uint8_t* dest);
346 int MXC_TPU_DMA_SetupOperation (mxc_tpu_dma_req_t* req);
358 int MXC_TPU_DMA_DoOperation (mxc_tpu_dma_req_t* req);
366 void MXC_TPU_DMA_StartTransfer (uint32_t length);
377 int MXC_TPU_TRNG_RandomInt (
void);
387 int MXC_TPU_TRNG_Random (uint8_t* data, uint32_t len);
398 void MXC_TPU_TRNG_RandomAsync (uint8_t* data, uint32_t len, mxc_tpu_complete_t callback);
406 int MXC_TPU_TRNG_Generate_AES (
void);
414 int MXC_TPU_TRNG_HealthTest (
void);
422 void MXC_TPU_TRNG_HealthTestAsync (mxc_tpu_complete_t callback);
439 void MXC_TPU_ECC_Enable (
int enable);
446 uint32_t MXC_TPU_ECC_GetResult (
void);
461 int MXC_TPU_ECC_Compute (mxc_tpu_ecc_req_t* req);
472 int MXC_TPU_ECC_ErrorCheck (mxc_tpu_ecc_req_t* req);
482 void MXC_TPU_ECC_ComputeAsync (mxc_tpu_ecc_req_t* req);
491 void MXC_TPU_ECC_ErrorCheckAsync (mxc_tpu_ecc_req_t* req);
506 void MXC_TPU_CRC_SetDirection (
int msbFirst);
513 int MXC_TPU_CRC_GetDirection (
void);
520 void MXC_TPU_CRC_SetPoly (uint32_t poly);
527 uint32_t MXC_TPU_CRC_GetPoly (
void);
534 uint32_t MXC_TPU_CRC_GetResult (
void);
549 int MXC_TPU_CRC_Compute (mxc_tpu_crc_req_t* req);
559 void MXC_TPU_CRC_ComputeAsync (mxc_tpu_crc_req_t* req);
576 uint32_t* MXC_TPU_MAA_GetAddress (
int segment);
583 void MXC_TPU_MAA_SetRAMTemporary (
int segment);
590 int MXC_TPU_MAA_GetRAMTemporary (
void);
597 void MXC_TPU_MAA_SetRAMResult (
int segment);
604 int MXC_TPU_MAA_GetRAMResult (
void);
611 void MXC_TPU_MAA_SetRAMOperandA (
int segment);
618 int MXC_TPU_MAA_GetRAMOperandA (
void);
625 void MXC_TPU_MAA_SetRAMOperandB (
int segment);
632 int MXC_TPU_MAA_GetRAMOperandB (
void);
640 void MXC_TPU_MAA_SetMemoryBlinding (mxc_tpu_maa_register_t reg,
int blindIndex);
649 int MXC_TPU_MAA_GetMemoryBlinding (mxc_tpu_maa_register_t reg);
658 void MXC_TPU_MAA_SetSecureMode (
int secureMode);
666 int MXC_TPU_MAA_GetSecureMode (
void);
675 void MXC_TPU_MAA_SetCalculation (mxc_tpu_maa_operation_t operation);
683 void MXC_TPU_MAA_Start (
void);
690 void MXC_TPU_MAA_StartBlocking (
void);
697 void MXC_TPU_MAA_SetWordSize (
int size);
704 int MXC_TPU_MAA_GetWordSize (
void);
720 int MXC_TPU_MAA_Compute (mxc_tpu_maa_req_t* req);
729 void MXC_TPU_MAA_ComputeAsync (mxc_tpu_maa_req_t* req);
746 unsigned int MXC_TPU_Hash_GetBlockSize (mxc_tpu_hash_func_t
function);
755 unsigned int MXC_TPU_Hash_GetDigestSize (mxc_tpu_hash_func_t
function);
762 void MXC_TPU_Hash_SetFunction (mxc_tpu_hash_func_t
function);
769 mxc_tpu_hash_func_t MXC_TPU_Hash_GetFunction (
void);
777 void MXC_TPU_Hash_SetAutoPad (
int pad);
784 int MXC_TPU_Hash_GetAutoPad (
void);
792 void MXC_TPU_Hash_GetResult (uint8_t* digest,
int* len);
800 void MXC_TPU_Hash_SetMessageSize (uint32_t size);
807 void MXC_TPU_Hash_SetSource (mxc_tpu_hash_source_t source);
814 mxc_tpu_hash_source_t MXC_TPU_Hash_GetSource (
void);
822 void MXC_TPU_Hash_InitializeHash (
void);
836 int MXC_TPU_Hash_Compute (mxc_tpu_hash_req_t* req);
845 void MXC_TPU_Hash_ComputeAsync (mxc_tpu_hash_req_t* req);
862 unsigned int MXC_TPU_Cipher_GetKeySize (mxc_tpu_cipher_t cipher);
871 unsigned int MXC_TPU_Cipher_GetBlockSize (mxc_tpu_cipher_t cipher);
878 void MXC_TPU_Cipher_SetMode (mxc_tpu_cipher_mode_t mode);
885 mxc_tpu_cipher_mode_t MXC_TPU_Cipher_GetMode (
void);
892 void MXC_TPU_Cipher_SetCipher (mxc_tpu_cipher_t cipher);
899 mxc_tpu_cipher_t MXC_TPU_Cipher_GetCipher (
void);
906 void MXC_TPU_Cipher_SetKeySource (mxc_tpu_cipher_key_t source);
913 mxc_tpu_cipher_key_t MXC_TPU_Cipher_GetKeySource (
void);
919 void MXC_TPU_Cipher_LoadKey (
void);
926 void MXC_TPU_Cipher_SetOperation (
int encrypt);
935 void MXC_TPU_Cipher_SetKey (uint8_t* key,
int len);
943 void MXC_TPU_Cipher_SetIV (uint8_t* iv,
int len);
951 void MXC_TPU_Cipher_GetIV (uint8_t* ivOut,
int len);
965 int MXC_TPU_Cipher_Encrypt (mxc_tpu_cipher_req_t* req);
975 int MXC_TPU_Cipher_Decrypt (mxc_tpu_cipher_req_t* req);
984 void MXC_TPU_Cipher_EncryptAsync (mxc_tpu_cipher_req_t* req);
993 void MXC_TPU_Cipher_DecryptAsync (mxc_tpu_cipher_req_t* req);