MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
max32655.h
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33 
34 #ifndef _MAX32655_REGS_H_
35 #define _MAX32655_REGS_H_
36 
37 #ifndef TARGET_NUM
38 #define TARGET_NUM 78000
39 #endif
40 
41 #define MXC_NUMCORES 1
42 
43 #include <stdint.h>
44 
45 #ifndef FALSE
46 #define FALSE (0)
47 #endif
48 
49 #ifndef TRUE
50 #define TRUE (1)
51 #endif
52 
53 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
54 #if defined ( __GNUC__ )
55 #define __weak __attribute__((weak))
56 
57 #elif defined ( __CC_ARM)
58 
59 #define inline __inline
60 #pragma anon_unions
61 
62 #endif
63 
64 typedef enum {
65 #ifndef __riscv // not RISC-V
66  NonMaskableInt_IRQn = -14,
67  HardFault_IRQn = -13,
68  MemoryManagement_IRQn = -12,
69  BusFault_IRQn = -11,
70  UsageFault_IRQn = -10,
71  SVCall_IRQn = -5,
72  DebugMonitor_IRQn = -4,
73  PendSV_IRQn = -2,
74  SysTick_IRQn = -1,
75 
76  /* Device-specific interrupt sources (external to ARM core) */
77  /* table entry number */
78  /* |||| */
79  /* |||| table offset address */
80  /* vvvv vvvvvv */
81 
82  PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
83  WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
84  RSV02_IRQn, /* 0x12 0x0048 18: Reserved */
85  RTC_IRQn, /* 0x13 0x004C 19: RTC */
86  TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
87  TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
88  TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
89  TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
90  TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */
91  TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 (LP) */
92  TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 (LP) */
93  RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
94  RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
95  I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
96  UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
97  UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
98  SPI1_IRQn, /* 0x20 0x0080 32: SPI1 */
99  RSV17_IRQn, /* 0x21 0x0084 33: Reserved */
100  RSV18_IRQn, /* 0x22 0x0088 34: Reserved */
101  RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
102  ADC_IRQn, /* 0x24 0x0090 36: ADC */
103  RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
104  RSV22_IRQn, /* 0x26 0x0098 38: Reserved */
105  FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller */
106  GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
107  GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */
108  GPIO2_IRQn, /* 0x2A 0x00A8 42: GPIO2 (LP) */
109  RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */
110  DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
111  DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
112  DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
113  DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
114  RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
115  RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
116  UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
117  RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */
118  I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
119  RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */
120  RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */
121  BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */
122  BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */
123  BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */
124  BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */
125  BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/
126  BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/
127  BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */
128  BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */
129  BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */
130  BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */
131  BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */
132  BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */
133  BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/
134  BTLE_IQ_DATA_VALID_IRQn,/* 0x44 0x0110 68: BTLE IQ Data Valid */
135  WUT_IRQn, /* 0x45 0x0114 69: Wakeup Timer */
136  GPIOWake_IRQn, /* 0x46 0x0118 70: GPIO and AIN Wakeup */
137  RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
138  SPI0_IRQn, /* 0x48 0x0120 72: SPI0 */
139  WDT1_IRQn, /* 0x49 0x0124 73: LP Watchdog */
140  RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */
141  PT_IRQn, /* 0x4B 0x012C 75: Pulse Train */
142  RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */
143  RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
144  I2C2_IRQn, /* 0x4E 0x0138 78: I2C2 */
145  RISCV_IRQn, /* 0x4F 0x013C 79: RISC-V */
146  RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
147  RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
148  RSV66_IRQn, /* 0x52 0x0148 82: Reserved */
149  OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */
150  RSV68_IRQn, /* 0x54 0x0150 84: Reserved */
151  RSV69_IRQn, /* 0x55 0x0154 85: Reserved */
152  RSV70_IRQn, /* 0x56 0x0158 86: Reserved */
153  RSV71_IRQn, /* 0x57 0x015C 87: Reserved */
154  RSV72_IRQn, /* 0x58 0x0160 88: Reserved */
155  RSV73_IRQn, /* 0x59 0x0164 89: Reserved */
156  RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */
157  RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */
158  RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */
159  RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */
160  RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */
161  RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */
162  RSV80_IRQn, /* 0x60 0x0180 96: Reserved */
163  RSV81_IRQn, /* 0x61 0x0184 97: Reserved */
164  ECC_IRQn, /* 0x62 0x0188 98: ECC */
165  DVS_IRQn, /* 0x63 0x018C 99: DVS */
166  SIMO_IRQn, /* 0x64 0x0190 100: SIMO */
167  RSV85_IRQn, /* 0x65 0x0194 101: Reserved */
168  RSV86_IRQn, /* 0x66 0x0198 102: Reserved */
169  RSV87_IRQn, /* 0x67 0x019C 103: Reserved */
170  UART3_IRQn, /* 0x68 0x01A0 104: UART 3 (LP) */
171  RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */
172  RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */
173  PCIF_IRQn, /* 0x6B 0x01AC 107: PCIF (Camera) */
174  RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */
175  RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */
176  RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */
177  RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */
178  RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */
179  AES_IRQn, /* 0x71 0x01C4 113: AES */
180  RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */
181  I2S_IRQn, /* 0x73 0x01CC 115: I2S */
182  CNN_FIFO_IRQn, /* 0x74 0x01D0 116: CNN FIFO */
183  CNN_IRQn, /* 0x75 0x01D4 117: CNN */
184  RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */
185  LPCMP_IRQn, /* 0x77 0x01Dc 119: LP Comparator */
186 #else // __riscv
187  PF_IRQn = 4, /* 0x04,4 PFW | SYSFAULT | CM4 */
188  WDT0_IRQn, /* 0x05,5 Watchdog 0 */
189  GPIOWake_IRQn = 6, /* 0x06,6 GPIO Wakeup */
190  AINComp_IRQn = 6, /* 0x06,6 AINComp */
191  RTC_IRQn, /* 0x07,7 RTC */
192  TMR0_IRQn, /* 0x08,8 Timer 0 */
193  TMR1_IRQn, /* 0x09,9 Timer 1 */
194  TMR2_IRQn, /* 0x0A,10 Timer 2 */
195  TMR3_IRQn, /* 0x0B,11 Timer 3 */
196  TMR4_IRQn, /* 0x0C,12 Timer 4 (LP) */
197  TMR5_IRQn, /* 0x0D,13 Timer 5 (LP) */
198  I2C0_IRQn, /* 0x0E,14 I2C0 */
199  UART0_IRQn, /* 0x0F,15 UART 0 */
200  RSV16_IRQn, /* 0x10,16 Reserved */
201  I2C1_IRQn, /* 0x11,17 I2C1 */
202  UART1_IRQn, /* 0x12,18 UART 1 */
203  UART2_IRQn, /* 0x13,19 UART 2 */
204  I2C2_IRQn, /* 0x14,20 I2C2 */
205  UART3_IRQn, /* 0x15,21 LPUART */
206  SPI1_IRQn, /* 0x16,22 SPI1 */
207  WUT_IRQn, /* 0x17,23 WUT */
208  FLC0_IRQn, /* 0x18,24 Flash Controller */
209  GPIO0_IRQn, /* 0x19,25 GPIO0 */
210  GPIO1_IRQn, /* 0x1A,26 GPIO1 */
211  GPIO2_IRQn, /* 0x1B,27 GPIO2 (LP) */
212  DMA0_IRQn, /* 0x1C,28 DMA0 */
213  DMA1_IRQn, /* 0x1D,29 DMA1 */
214  DMA2_IRQn, /* 0x1E,30 DMA2 */
215  DMA3_IRQn, /* 0x1F,31 DMA3 */
216  RSV32_IRQn, /* 0x20,32 Reserved */
217  RSV33_IRQn, /* 0x21,33 Reserved */
218  RSV34_IRQn, /* 0x22,34 Reserved */
219  RSV35_IRQn, /* 0x23,35 Reserved */
220  RSV36_IRQn, /* 0x24,36 Reserved */
221  RSV37_IRQn, /* 0x25,37 Reserved */
222  RSV38_IRQn, /* 0x26,38 Reserved */
223  RSV39_IRQn, /* 0x27,39 Reserved */
224  RSV40_IRQn, /* 0x28,40 Reserved */
225  RSV41_IRQn, /* 0x29,41 Reserved */
226  RSV42_IRQn, /* 0x2A,42 Reserved */
227  RSV43_IRQn, /* 0x2B,43 Reserved */
228  RSV44_IRQn, /* 0x2C,44 Reserved */
229  RSV45_IRQn, /* 0x2D,45 Reserved */
230  AES_IRQn, /* 0x2E,46 AES */
231  TRNG_IRQn, /* 0x2F,47 True Random Number Generator */
232  WDT1_IRQn, /* 0x30,48 Watchdog 1 (LP) */
233  DVS_IRQn, /* 0x31,49 DVS Controller */
234  SIMO_IRQn, /* 0x32,50 SIMO Controller */
235  RSV51_IRQn, /* 0x33,51 CRC */
236  PT_IRQn, /* 0x34,52 Pulse train */
237  ADC_IRQn, /* 0x35,53 ADC */
238  OWM_IRQn, /* 0x36,54 One Wire Master */
239  I2S_IRQn, /* 0x37,55 I2S */
240  CNN_FIFO_IRQn, /* 0x38,56 CNN FIFO */
241  CNN_IRQn, /* 0x39,57 CNN */
242  RSV58_IRQn, /* 0x3A,58 Reserved */
243  PCIF_IRQn, /* 0x3B,59 Parallel Camera IF */
244 #endif // __riscv
245  MXC_IRQ_EXT_COUNT,
246 } IRQn_Type;
247 
248 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
249 
250 
251 /* ================================================================================ */
252 /* ================ Processor and Core Peripheral Section ================ */
253 /* ================================================================================ */
254 
255 #ifndef __riscv
256 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
257 #define __CM4_REV 0x0100
258 #define __MPU_PRESENT 1
259 #define __NVIC_PRIO_BITS 3
260 #define __Vendor_SysTickConfig 0
261 #define __FPU_PRESENT 1
263 #include <core_cm4.h>
265 #else // __riscv
266 
267 #include <core_rv32.h>
268 
269 #endif // __riscv
270 
271 #include "system_max32655.h"
274 /* ================================================================================ */
275 /* ================== Device Specific Memory Section ================== */
276 /* ================================================================================ */
277 
278 #define MXC_ROM_MEM_BASE 0x00000000UL
279 #define MXC_ROM_MEM_SIZE 0x00020000UL
280 #define MXC_FLASH0_MEM_BASE 0x10000000UL
281 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
282 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
283 #define MXC_FLASH_MEM_SIZE 0x00080000UL
284 #define MXC_INFO0_MEM_BASE 0x10800000UL
285 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
286 #define MXC_INFO_MEM_SIZE 0x00004000UL
287 #define MXC_SRAM_MEM_BASE 0x20000000UL
288 #define MXC_SRAM_MEM_SIZE 0x00020000UL
289 
290 
291 /* ================================================================================ */
292 /* ================ Device Specific Peripheral Section ================ */
293 /* ================================================================================ */
294 
295 /*
296  Base addresses and configuration settings for all MAX78000 peripheral modules.
297 */
298 
299 /******************************************************************************/
300 /* Global control */
301 #define MXC_BASE_GCR ((uint32_t)0x40000000UL)
302 #define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
303 
304 /******************************************************************************/
305 /* Non-battery backed SI Registers */
306 #define MXC_BASE_SIR ((uint32_t)0x40000400UL)
307 #define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
308 
309 /******************************************************************************/
310 /* Non-Battery Backed Function Control */
311 #define MXC_BASE_FCR ((uint32_t)0x40000800UL)
312 #define MXC_FCR ((mxc_fcr_regs_t*)MXC_BASE_FCR)
313 
314 /******************************************************************************/
315 /* Dynamic Voltage Scaling (DVS) Control */
316 #define MXC_BASE_DVS ((uint32_t)0x40003C00UL)
317 #define MXC_DVS ((mxc_dvs_regs_t*)MXC_BASE_DVS)
318 
319 /******************************************************************************/
320 /* SIMO Control */
321 #define MXC_BASE_SIMO ((uint32_t)0x40004400UL)
322 #define MXC_SIMO ((mxc_simo_regs_t*)MXC_BASE_SIMO)
323 
324 /******************************************************************************/
325 /* Trim System Initalization Register */
326 #define MXC_BASE_TRIMSIR ((uint32_t)0x40105400UL)
327 #define MXC_TRIMSIR ((mxc_trimsir_regs_t*)MXC_BASE_TRIMSIR)
328 
329 /******************************************************************************/
330 /* BBFC */
331 #define MXC_BASE_BBFC ((uint32_t)0x40005800UL)
332 #define MXC_BBFC ((mxc_bbfc_regs_t*)MXC_BASE_BBFC)
333 
334 /******************************************************************************/
335 /* Windowed Watchdog Timer */
336 #define MXC_CFG_WDT_INSTANCES (2)
337 
338 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
339 #define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
340 #define MXC_BASE_WDT1 ((uint32_t)0x40080800UL)
341 #define MXC_WDT1 ((mxc_wdt_regs_t*)MXC_BASE_WDT1)
342 
343 /******************************************************************************/
344 /* Real Time Clock */
345 #define MXC_BASE_RTC ((uint32_t)0x40006000UL)
346 #define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
347 
348 /******************************************************************************/
349 /* Wake-Up Timer (WUT) */
350 #define MXC_BASE_WUT ((uint32_t)0x40006400UL)
351 #define MXC_WUT ((mxc_wut_regs_t*)MXC_BASE_WUT)
352 
353 /******************************************************************************/
354 /* Power Sequencer */
355 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
356 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
357 
358 /******************************************************************************/
359 /* Misc Control */
360 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL)
361 #define MXC_MCR ((mxc_mcr_regs_t*)MXC_BASE_MCR)
362 
363 /******************************************************************************/
364 /* Low Power General control */
365 #define MXC_BASE_LPGCR ((uint32_t)0x40080000UL)
366 #define MXC_LPGCR ((mxc_lpgcr_regs_t*)MXC_BASE_LPGCR)
367 
368 /******************************************************************************/
369 /* GPIO */
370 #define MXC_CFG_GPIO_INSTANCES (4)
371 #define MXC_CFG_GPIO_PINS_PORT (32)
372 
373 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
374 #define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
375 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
376 #define MXC_GPIO1 ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)
377 #define MXC_BASE_GPIO2 ((uint32_t)0x40080400UL)
378 #define MXC_GPIO2 ((mxc_gpio_regs_t*)MXC_BASE_GPIO2)
379 #define MXC_BASE_GPIO3 ((uint32_t)0x40080600UL)
380 #define MXC_GPIO3 ((mxc_gpio_regs_t*)MXC_BASE_GPIO3)
381 
382 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \
383  (p) == MXC_GPIO1 ? 1 : \
384  (p) == MXC_GPIO2 ? 2 : \
385  (p) == MXC_GPIO3 ? 3 : -1)
386 
387 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \
388  (i) == 1 ? MXC_GPIO1 : \
389  (i) == 2 ? MXC_GPIO2 : \
390  (i) == 3 ? MXC_GPIO3 : 0)
391 
392 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \
393  (i) == 1 ? GPIO1_IRQn : \
394  (i) == 2 ? GPIO2_IRQn : 0)
395 // GPIO3 does not have an interrupt
396 
397 /******************************************************************************/
398 
399 #define SEC(s) (((unsigned long)s) * 1000000UL)
400 #define MSEC(ms) (ms * 1000UL)
401 #define USEC(us) (us)
402 
403 /* Timer */
404 #define MXC_CFG_TMR_INSTANCES (6)
405 
406 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
407 #define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
408 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
409 #define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
410 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
411 #define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
412 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
413 #define MXC_TMR3 ((mxc_tmr_regs_t*)MXC_BASE_TMR3)
414 #define MXC_BASE_TMR4 ((uint32_t)0x40080C00UL)
415 #define MXC_TMR4 ((mxc_tmr_regs_t*)MXC_BASE_TMR4)
416 #define MXC_BASE_TMR5 ((uint32_t)0x40081000UL)
417 #define MXC_TMR5 ((mxc_tmr_regs_t*)MXC_BASE_TMR5)
418 
419 #define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
420  (i) == 1 ? TMR1_IRQn : \
421  (i) == 2 ? TMR2_IRQn : \
422  (i) == 3 ? TMR3_IRQn : \
423  (i) == 4 ? TMR4_IRQn : \
424  (i) == 5 ? TMR5_IRQn : 0)
425 
426 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
427  (i) == 1 ? MXC_BASE_TMR1 : \
428  (i) == 2 ? MXC_BASE_TMR2 : \
429  (i) == 3 ? MXC_BASE_TMR3 : \
430  (i) == 4 ? MXC_BASE_TMR4 : \
431  (i) == 5 ? MXC_BASE_TMR5 : 0)
432 
433 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
434  (i) == 1 ? MXC_TMR1 : \
435  (i) == 2 ? MXC_TMR2 : \
436  (i) == 3 ? MXC_TMR3 : \
437  (i) == 4 ? MXC_TMR4 : \
438  (i) == 5 ? MXC_TMR5 : 0)
439 
440 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
441  (p) == MXC_TMR1 ? 1 : \
442  (p) == MXC_TMR2 ? 2 : \
443  (p) == MXC_TMR3 ? 3 : \
444  (p) == MXC_TMR4 ? 4 : \
445  (p) == MXC_TMR5 ? 5 : -1)
446 
447 /******************************************************************************/
448 /* I2C */
449 #define MXC_I2C_INSTANCES (3)
450 
451 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
452 #define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
453 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
454 #define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
455 #define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
456 #define MXC_I2C2 ((mxc_i2c_regs_t*)MXC_BASE_I2C2)
457 
458 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
459  (i) == 1 ? I2C1_IRQn : \
460  (i) == 2 ? I2C2_IRQn : 0)
461 
462 #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
463  (i) == 1 ? MXC_BASE_I2C1 : \
464  (i) == 2 ? MXC_BASE_I2C2 : 0)
465 
466 #define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
467  (i) == 1 ? MXC_I2C1 : \
468  (i) == 2 ? MXC_I2C2 : 0)
469 
470 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
471  (p) == MXC_I2C1 ? 1 : \
472  (p) == MXC_I2C2 ? 2 : -1)
473 #define MXC_I2C_FIFO_DEPTH (8)
474 
475 /******************************************************************************/
476 /* DMA */
477 #define MXC_DMA_CHANNELS (16)
478 
479 #define MXC_BASE_DMA ((uint32_t)0x40028000UL)
480 #define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA)
481 
482 /******************************************************************************/
483 /* FLC */
484 #define MXC_FLC_INSTANCES (1)
485 
486 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
487 #define MXC_FLC0 ((mxc_flc_regs_t*)MXC_BASE_FLC0)
488 #define MXC_FLC MXC_FLC0
489 
490 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
491 
492 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0)
493 
494 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0)
495 
496 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1)
497 
498 /******************************************************************************/
499 /* ADC */
500 #define MXC_BASE_ADC ((uint32_t)0x40034000UL)
501 #define MXC_ADC ((mxc_adc_regs_t*)MXC_BASE_ADC)
502 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz
503 
504 /******************************************************************************/
505 /* Instruction Cache */
506 #define MXC_ICC_INSTANCES (2)
507 
508 #define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL)
509 #define MXC_ICC0 ((mxc_icc_regs_t*)MXC_BASE_ICC0)
510 
511 #define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL)
512 #define MXC_ICC1 ((mxc_icc_regs_t*)MXC_BASE_ICC1)
513 
514 #define MXC_ICC MXC_ICC0
515 // ICC1 is the RISC-V cache
516 
517 #define MXC_ICC MXC_ICC0
518 
519 /******************************************************************************/
520 /* One Wire Master */
521 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
522 #define MXC_OWM ((mxc_owm_regs_t*)MXC_BASE_OWM)
523 
524 /******************************************************************************/
525 /* Semaphore */
526 #define MXC_CFG_SEMA_INSTANCES (8)
527 
528 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL)
529 #define MXC_SEMA ((mxc_sema_regs_t*)MXC_BASE_SEMA)
530 
531 /******************************************************************************/
532 /* UART / Serial Port Interface */
533 #define MXC_UART_INSTANCES (4)
534 #define MXC_UART_FIFO_DEPTH (8)
535 
536 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
537 #define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
538 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
539 #define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
540 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
541 #define MXC_UART2 ((mxc_uart_regs_t*)MXC_BASE_UART2)
542 #define MXC_BASE_UART3 ((uint32_t)0x40081400UL)
543 #define MXC_UART3 ((mxc_uart_regs_t*)MXC_BASE_UART3)
544 
545 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
546  (i) == 1 ? UART1_IRQn : \
547  (i) == 2 ? UART2_IRQn : \
548  (i) == 3 ? UART3_IRQn : 0)
549 
550 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
551  (i) == 1 ? MXC_BASE_UART1 : \
552  (i) == 2 ? MXC_BASE_UART2 : \
553  (i) == 3 ? MXC_BASE_UART3 : 0)
554 
555 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
556  (i) == 1 ? MXC_UART1 : \
557  (i) == 2 ? MXC_UART2 : \
558  (i) == 3 ? MXC_UART3 : 0)
559 
560 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
561  (p) == MXC_UART1 ? 1 : \
562  (p) == MXC_UART2 ? 2 : \
563  (p) == MXC_UART3 ? 3 : -1)
564 
565 /******************************************************************************/
566 /* SPI */
567 #ifndef __riscv
568 #define MXC_SPI_INSTANCES (2)
569 #else
570 #define MXC_SPI_INSTANCES (1)
571 #endif // __riscv
572 #define MXC_SPI_SS_INSTANCES (4)
573 #define MXC_SPI_FIFO_DEPTH (32)
574 
575 #define MXC_BASE_SPI1 ((uint32_t)0x40046000UL)
576 #define MXC_SPI1 ((mxc_spi_regs_t*)MXC_BASE_SPI1)
577 #ifndef __riscv
578 #define MXC_BASE_SPI0 ((uint32_t)0x400BE000UL)
579 #define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI0)
580 
581 // Note: These must be in order SPI1, SPI0 to support RISC-V
582 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI1 ? 0 : \
583  (p) == MXC_SPI0 ? 1 : -1)
584 
585 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI1 : \
586  (i) == 1 ? MXC_BASE_SPI0 : 0)
587 
588 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI1 : \
589  (i) == 1 ? MXC_SPI0 : 0)
590 
591 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI1_IRQn : \
592  (i) == 1 ? SPI0_IRQn : 0)
593 #else // __riscv
594 
595 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI1 ? 0 : -1)
596 
597 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI1 : 0)
598 
599 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI1 : 0)
600 
601 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI1_IRQn : 0)
602 
603 #endif // __riscv
604 
605 
606 /*******************************************************************************/
607 /* Pulse Train Generation */
608 #define MXC_CFG_PT_INSTANCES (4)
609 
610 #define MXC_BASE_PTG ((uint32_t)0x4003C000UL)
611 #define MXC_PTG ((mxc_ptg_regs_t*)MXC_BASE_PTG)
612 #define MXC_BASE_PT0 ((uint32_t)0x4003C020UL)
613 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
614 #define MXC_BASE_PT1 ((uint32_t)0x4003C040UL)
615 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
616 #define MXC_BASE_PT2 ((uint32_t)0x4003C060UL)
617 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
618 #define MXC_BASE_PT3 ((uint32_t)0x4003C080UL)
619 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
620 
621 #define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
622  (i) == 1 ? MXC_BASE_PT1 : \
623  (i) == 2 ? MXC_BASE_PT2 : \
624  (i) == 3 ? MXC_BASE_PT3 : 0)
625 
626 #define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
627  (i) == 1 ? MXC_PT1 : \
628  (i) == 2 ? MXC_PT2 : \
629  (i) == 3 ? MXC_PT3 : 0)
630 
631 #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
632  (p) == MXC_PT1 ? 1 : \
633  (p) == MXC_PT2 ? 2 : \
634  (p) == MXC_PT3 ? 3 : -1)
635 
636 /******************************************************************************/
637 /* TRNG */
638 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
639 #define MXC_TRNG ((mxc_trng_regs_t*)MXC_BASE_TRNG)
640 
641 /******************************************************************************/
642 /* AES */
643 #define MXC_BASE_AES ((uint32_t)0x40007400UL)
644 #define MXC_AES ((mxc_aes_regs_t*)MXC_BASE_AES)
645 
646 /******************************************************************************/
647 /* AES Keys */
648 #define MXC_BASE_AESKEY ((uint32_t)0x40007800UL)
649 #define MXC_AESKEY ((mxc_aes_key_regs_t*)MXC_BASE_AESKEY)
650 
651 /******************************************************************************/
652 /* Parallel Camera Interface */
653 #define MXC_BASE_PCIF ((uint32_t)0x4000E000UL)
654 #define MXC_PCIF ((mxc_cameraif_regs_t*)MXC_BASE_PCIF)
655 
656 /******************************************************************************/
657 /* CRC */
658 #define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
659 #define MXC_CRC ((mxc_crc_regs_t*)MXC_BASE_CRC)
660 
661 /******************************************************************************/
662 /* I2S */
663 #define MXC_BASE_I2S ((uint32_t)0x40060000UL)
664 #define MXC_I2S ((mxc_i2s_regs_t*)MXC_BASE_I2S)
665 
666 /******************************************************************************/
667 /* Low-Power Comparator */
668 #define MXC_CFG_LPCOMP_INSTANCES (4)
669 
670 #define MXC_BASE_LPCOMP0 ((uint32_t)0x40088000UL)
671 #define MXC_LPCOMP0 ((mxc_lpcomp_regs_t*)MXC_BASE_LPCOMP0)
672 #define MXC_BASE_LPCOMP1 ((uint32_t)0x40088400UL)
673 #define MXC_LPCOMP1 ((mxc_lpcomp_regs_t*)MXC_BASE_LPCOMP1)
674 #define MXC_BASE_LPCOMP2 ((uint32_t)0x40088800UL)
675 #define MXC_LPCOMP2 ((mxc_lpcomp_regs_t*)MXC_BASE_LPCOMP2)
676 #define MXC_BASE_LPCOMP3 ((uint32_t)0x40088C00UL)
677 #define MXC_LPCOMP3 ((mxc_lpcomp_regs_t*)MXC_BASE_LPCOMP3)
678 
679 
680 /******************************************************************************/
681 /* Bit Shifting */
682 
683 #define MXC_F_BIT_0 (1 << 0)
684 #define MXC_F_BIT_1 (1 << 1)
685 #define MXC_F_BIT_2 (1 << 2)
686 #define MXC_F_BIT_3 (1 << 3)
687 #define MXC_F_BIT_4 (1 << 4)
688 #define MXC_F_BIT_5 (1 << 5)
689 #define MXC_F_BIT_6 (1 << 6)
690 #define MXC_F_BIT_7 (1 << 7)
691 #define MXC_F_BIT_8 (1 << 8)
692 #define MXC_F_BIT_9 (1 << 9)
693 #define MXC_F_BIT_10 (1 << 10)
694 #define MXC_F_BIT_11 (1 << 11)
695 #define MXC_F_BIT_12 (1 << 12)
696 #define MXC_F_BIT_13 (1 << 13)
697 #define MXC_F_BIT_14 (1 << 14)
698 #define MXC_F_BIT_15 (1 << 15)
699 #define MXC_F_BIT_16 (1 << 16)
700 #define MXC_F_BIT_17 (1 << 17)
701 #define MXC_F_BIT_18 (1 << 18)
702 #define MXC_F_BIT_19 (1 << 19)
703 #define MXC_F_BIT_20 (1 << 20)
704 #define MXC_F_BIT_21 (1 << 21)
705 #define MXC_F_BIT_22 (1 << 22)
706 #define MXC_F_BIT_23 (1 << 23)
707 #define MXC_F_BIT_24 (1 << 24)
708 #define MXC_F_BIT_25 (1 << 25)
709 #define MXC_F_BIT_26 (1 << 26)
710 #define MXC_F_BIT_27 (1 << 27)
711 #define MXC_F_BIT_28 (1 << 28)
712 #define MXC_F_BIT_29 (1 << 29)
713 #define MXC_F_BIT_30 (1 << 30)
714 #define MXC_F_BIT_31 (1 << 31)
715 
716 /******************************************************************************/
717 /* Bit Banding */
718 
719 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
720  (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
721 
722 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
723 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
724 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
725 
726 #define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask))
727 
728 /******************************************************************************/
729 /* SCB CPACR */
730 
731 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
732 #define SCB_CPACR_CP10_Pos 20
733 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
734 #define SCB_CPACR_CP11_Pos 22
735 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
737 #endif /* _MAX32655_REGS_H_ */