MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
tmr_regs.h
1 
6 /* ****************************************************************************
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39 
40 #ifndef _TMR_REGS_H_
41 #define _TMR_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t cnt;
90  __IO uint32_t cmp;
91  __IO uint32_t pwm;
92  __IO uint32_t intfl;
93  __IO uint32_t ctrl0;
94  __IO uint32_t nolcmp;
95  __IO uint32_t ctrl1;
96  __IO uint32_t wkfl;
98 
99 /* Register offsets for module TMR */
106  #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL)
107  #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL)
108  #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL)
109  #define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL)
110  #define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL)
111  #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL)
112  #define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL)
113  #define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL)
122  #define MXC_F_TMR_CNT_COUNT_POS 0
123  #define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS))
133  #define MXC_F_TMR_CMP_COMPARE_POS 0
134  #define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS))
144  #define MXC_F_TMR_PWM_PWM_POS 0
145  #define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS))
155  #define MXC_F_TMR_INTFL_IRQ_A_POS 0
156  #define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS))
158  #define MXC_F_TMR_INTFL_WRDONE_A_POS 8
159  #define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS))
161  #define MXC_F_TMR_INTFL_WR_DIS_A_POS 9
162  #define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS))
164  #define MXC_F_TMR_INTFL_IRQ_B_POS 16
165  #define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS))
167  #define MXC_F_TMR_INTFL_WRDONE_B_POS 24
168  #define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS))
170  #define MXC_F_TMR_INTFL_WR_DIS_B_POS 25
171  #define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS))
181  #define MXC_F_TMR_CTRL0_MODE_A_POS 0
182  #define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS))
183  #define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL)
184  #define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS)
185  #define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL)
186  #define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS)
187  #define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL)
188  #define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS)
189  #define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL)
190  #define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS)
191  #define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL)
192  #define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS)
193  #define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL)
194  #define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS)
195  #define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL)
196  #define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS)
197  #define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL)
198  #define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS)
199  #define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL)
200  #define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS)
201  #define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xCUL)
202  #define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS)
204  #define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4
205  #define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS))
206  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL)
207  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
208  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL)
209  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
210  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL)
211  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
212  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL)
213  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
214  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL)
215  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
216  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL)
217  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
218  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL)
219  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
220  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL)
221  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
222  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL)
223  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
224  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL)
225  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
226  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL)
227  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
228  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL)
229  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
230  #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL)
231  #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)
233  #define MXC_F_TMR_CTRL0_POL_A_POS 8
234  #define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS))
236  #define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9
237  #define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS))
239  #define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10
240  #define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS))
242  #define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11
243  #define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS))
245  #define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12
246  #define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS))
248  #define MXC_F_TMR_CTRL0_RST_A_POS 13
249  #define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS))
251  #define MXC_F_TMR_CTRL0_CLKEN_A_POS 14
252  #define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS))
254  #define MXC_F_TMR_CTRL0_EN_A_POS 15
255  #define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS))
257  #define MXC_F_TMR_CTRL0_MODE_B_POS 16
258  #define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS))
259  #define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL)
260  #define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS)
261  #define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL)
262  #define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS)
263  #define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL)
264  #define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS)
265  #define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL)
266  #define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS)
267  #define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL)
268  #define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS)
269  #define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL)
270  #define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS)
271  #define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL)
272  #define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS)
273  #define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL)
274  #define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS)
275  #define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL)
276  #define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS)
277  #define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL)
278  #define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS)
280  #define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20
281  #define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS))
282  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL)
283  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
284  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL)
285  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
286  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL)
287  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
288  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL)
289  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
290  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL)
291  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
292  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL)
293  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
294  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL)
295  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
296  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL)
297  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
298  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL)
299  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
300  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL)
301  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
302  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL)
303  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
304  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL)
305  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
306  #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL)
307  #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)
309  #define MXC_F_TMR_CTRL0_POL_B_POS 24
310  #define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS))
312  #define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25
313  #define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS))
315  #define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26
316  #define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS))
318  #define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27
319  #define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS))
321  #define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28
322  #define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS))
324  #define MXC_F_TMR_CTRL0_RST_B_POS 29
325  #define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS))
327  #define MXC_F_TMR_CTRL0_CLKEN_B_POS 30
328  #define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS))
330  #define MXC_F_TMR_CTRL0_EN_B_POS 31
331  #define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS))
341  #define MXC_F_TMR_NOLCMP_LO_A_POS 0
342  #define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS))
344  #define MXC_F_TMR_NOLCMP_HI_A_POS 8
345  #define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS))
347  #define MXC_F_TMR_NOLCMP_LO_B_POS 16
348  #define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS))
350  #define MXC_F_TMR_NOLCMP_HI_B_POS 24
351  #define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS))
361  #define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0
362  #define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS))
364  #define MXC_F_TMR_CTRL1_CLKEN_A_POS 2
365  #define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS))
367  #define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3
368  #define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS))
370  #define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4
371  #define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS))
373  #define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7
374  #define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS))
376  #define MXC_F_TMR_CTRL1_IE_A_POS 8
377  #define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS))
379  #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9
380  #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS))
382  #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11
383  #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS))
385  #define MXC_F_TMR_CTRL1_WE_A_POS 12
386  #define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS))
388  #define MXC_F_TMR_CTRL1_OUTEN_A_POS 13
389  #define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS))
391  #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14
392  #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS))
394  #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16
395  #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS))
397  #define MXC_F_TMR_CTRL1_CLKEN_B_POS 18
398  #define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS))
400  #define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19
401  #define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS))
403  #define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20
404  #define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS))
406  #define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23
407  #define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS))
409  #define MXC_F_TMR_CTRL1_IE_B_POS 24
410  #define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS))
412  #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25
413  #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS))
415  #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27
416  #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS))
418  #define MXC_F_TMR_CTRL1_WE_B_POS 28
419  #define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS))
421  #define MXC_F_TMR_CTRL1_CASCADE_POS 31
422  #define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS))
432  #define MXC_F_TMR_WKFL_A_POS 0
433  #define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS))
435  #define MXC_F_TMR_WKFL_B_POS 16
436  #define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS))
440 #ifdef __cplusplus
441 }
442 #endif
443 
444 #endif /* _TMR_REGS_H_ */
__IO uint32_t pwm
Definition: tmr_regs.h:91
__IO uint32_t ctrl1
Definition: tmr_regs.h:95
__IO uint32_t ctrl0
Definition: tmr_regs.h:93
__IO uint32_t nolcmp
Definition: tmr_regs.h:94
__IO uint32_t cmp
Definition: tmr_regs.h:90
__IO uint32_t cnt
Definition: tmr_regs.h:89
__IO uint32_t wkfl
Definition: tmr_regs.h:96
__IO uint32_t intfl
Definition: tmr_regs.h:92
Definition: tmr_regs.h:88