MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
dma_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
8  *
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14  * Software is furnished to do so, subject to the following conditions:
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23  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25  * OTHER DEALINGS IN THE SOFTWARE.
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31  * The mere transfer of this software does not imply any licenses
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39 
40 #ifndef _DMA_REGS_H_
41 #define _DMA_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t ctrl;
90  __IO uint32_t status;
91  __IO uint32_t src;
92  __IO uint32_t dst;
93  __IO uint32_t cnt;
94  __IO uint32_t srcrld;
95  __IO uint32_t dstrld;
96  __IO uint32_t cntrld;
98 
99 typedef struct {
100  __IO uint32_t inten;
101  __I uint32_t intfl;
102  __R uint32_t rsv_0x8_0xff[62];
103  __IO mxc_dma_ch_regs_t ch[8];
104 } mxc_dma_regs_t;
105 
106 /* Register offsets for module DMA */
113  #define MXC_R_DMA_CTRL ((uint32_t)0x00000100UL)
114  #define MXC_R_DMA_STATUS ((uint32_t)0x00000104UL)
115  #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL)
116  #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL)
117  #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL)
118  #define MXC_R_DMA_SRCRLD ((uint32_t)0x00000114UL)
119  #define MXC_R_DMA_DSTRLD ((uint32_t)0x00000118UL)
120  #define MXC_R_DMA_CNTRLD ((uint32_t)0x0000011CUL)
121  #define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL)
122  #define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL)
123  #define MXC_R_DMA_CH ((uint32_t)0x00000100UL)
132  #define MXC_F_DMA_INTEN_CH0_POS 0
133  #define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS))
135  #define MXC_F_DMA_INTEN_CH1_POS 1
136  #define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS))
138  #define MXC_F_DMA_INTEN_CH2_POS 2
139  #define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS))
141  #define MXC_F_DMA_INTEN_CH3_POS 3
142  #define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS))
144  #define MXC_F_DMA_INTEN_CH4_POS 4
145  #define MXC_F_DMA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS))
147  #define MXC_F_DMA_INTEN_CH5_POS 5
148  #define MXC_F_DMA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS))
150  #define MXC_F_DMA_INTEN_CH6_POS 6
151  #define MXC_F_DMA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS))
153  #define MXC_F_DMA_INTEN_CH7_POS 7
154  #define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS))
164  #define MXC_F_DMA_INTFL_CH0_POS 0
165  #define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS))
167  #define MXC_F_DMA_INTFL_CH1_POS 1
168  #define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS))
170  #define MXC_F_DMA_INTFL_CH2_POS 2
171  #define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS))
173  #define MXC_F_DMA_INTFL_CH3_POS 3
174  #define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS))
176  #define MXC_F_DMA_INTFL_CH4_POS 4
177  #define MXC_F_DMA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS))
179  #define MXC_F_DMA_INTFL_CH5_POS 5
180  #define MXC_F_DMA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS))
182  #define MXC_F_DMA_INTFL_CH6_POS 6
183  #define MXC_F_DMA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS))
185  #define MXC_F_DMA_INTFL_CH7_POS 7
186  #define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS))
196  #define MXC_F_DMA_CTRL_EN_POS 0
197  #define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS))
199  #define MXC_F_DMA_CTRL_RLDEN_POS 1
200  #define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS))
202  #define MXC_F_DMA_CTRL_PRI_POS 2
203  #define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS))
204  #define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL)
205  #define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS)
206  #define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL)
207  #define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS)
208  #define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL)
209  #define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS)
210  #define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL)
211  #define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS)
213  #define MXC_F_DMA_CTRL_REQUEST_POS 4
214  #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS))
215  #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL)
216  #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS)
217  #define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x1UL)
218  #define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS)
219  #define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL)
220  #define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS)
221  #define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL)
222  #define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS)
223  #define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL)
224  #define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS)
225  #define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL)
226  #define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS)
227  #define MXC_V_DMA_CTRL_REQUEST_ADC ((uint32_t)0x9UL)
228  #define MXC_S_DMA_CTRL_REQUEST_ADC (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS)
229  #define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL)
230  #define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS)
231  #define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL)
232  #define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS)
233  #define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0xFUL)
234  #define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS)
235  #define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL)
236  #define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS)
237  #define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL)
238  #define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS)
239  #define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x21UL)
240  #define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS)
241  #define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL)
242  #define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS)
243  #define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL)
244  #define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS)
245  #define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL)
246  #define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS)
247  #define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL)
248  #define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS)
249  #define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL)
250  #define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS)
251  #define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL)
252  #define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS)
253  #define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL)
254  #define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS)
255  #define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x2FUL)
256  #define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS)
257  #define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL)
258  #define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS)
259  #define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL)
260  #define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS)
262  #define MXC_F_DMA_CTRL_TO_WAIT_POS 10
263  #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS))
265  #define MXC_F_DMA_CTRL_TO_PER_POS 11
266  #define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS))
267  #define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL)
268  #define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS)
269  #define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL)
270  #define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS)
271  #define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL)
272  #define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS)
273  #define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL)
274  #define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS)
275  #define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL)
276  #define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS)
277  #define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL)
278  #define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS)
279  #define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL)
280  #define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS)
281  #define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL)
282  #define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS)
284  #define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14
285  #define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS))
286  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL)
287  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
288  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL)
289  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
290  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL)
291  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
292  #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL)
293  #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS)
295  #define MXC_F_DMA_CTRL_SRCWD_POS 16
296  #define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS))
297  #define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL)
298  #define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS)
299  #define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL)
300  #define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS)
301  #define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL)
302  #define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS)
304  #define MXC_F_DMA_CTRL_SRCINC_POS 18
305  #define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS))
307  #define MXC_F_DMA_CTRL_DSTWD_POS 20
308  #define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS))
309  #define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL)
310  #define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS)
311  #define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL)
312  #define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS)
313  #define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL)
314  #define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS)
316  #define MXC_F_DMA_CTRL_DSTINC_POS 22
317  #define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS))
319  #define MXC_F_DMA_CTRL_BURST_SIZE_POS 24
320  #define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS))
322  #define MXC_F_DMA_CTRL_DIS_IE_POS 30
323  #define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS))
325  #define MXC_F_DMA_CTRL_CTZ_IE_POS 31
326  #define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS))
336  #define MXC_F_DMA_STATUS_STATUS_POS 0
337  #define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS))
339  #define MXC_F_DMA_STATUS_IPEND_POS 1
340  #define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS))
342  #define MXC_F_DMA_STATUS_CTZ_IF_POS 2
343  #define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS))
345  #define MXC_F_DMA_STATUS_RLD_IF_POS 3
346  #define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS))
348  #define MXC_F_DMA_STATUS_BUS_ERR_POS 4
349  #define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS))
351  #define MXC_F_DMA_STATUS_TO_IF_POS 6
352  #define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS))
366  #define MXC_F_DMA_SRC_ADDR_POS 0
367  #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS))
381  #define MXC_F_DMA_DST_ADDR_POS 0
382  #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS))
395  #define MXC_F_DMA_CNT_CNT_POS 0
396  #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS))
407  #define MXC_F_DMA_SRCRLD_ADDR_POS 0
408  #define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS))
419  #define MXC_F_DMA_DSTRLD_ADDR_POS 0
420  #define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS))
430  #define MXC_F_DMA_CNTRLD_CNT_POS 0
431  #define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS))
433  #define MXC_F_DMA_CNTRLD_EN_POS 31
434  #define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS))
438 #ifdef __cplusplus
439 }
440 #endif
441 
442 #endif /* _DMA_REGS_H_ */
__IO uint32_t ctrl
Definition: dma_regs.h:89
__IO uint32_t srcrld
Definition: dma_regs.h:94
Definition: dma_regs.h:88
__IO uint32_t status
Definition: dma_regs.h:90
__IO uint32_t cnt
Definition: dma_regs.h:93
__IO uint32_t dst
Definition: dma_regs.h:92
__IO uint32_t dstrld
Definition: dma_regs.h:95
__IO uint32_t src
Definition: dma_regs.h:91
__IO uint32_t cntrld
Definition: dma_regs.h:96