MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
gcr_regs.h
1 
6 /* ****************************************************************************
7  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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39 
40 #ifndef _GCR_REGS_H_
41 #define _GCR_REGS_H_
42 
43 /* **** Includes **** */
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #if defined (__ICCARM__)
51  #pragma system_include
52 #endif
53 
54 #if defined (__CC_ARM)
55  #pragma anon_unions
56 #endif
57 /*
59  If types are not defined elsewhere (CMSIS) define them here
60 */
61 #ifndef __IO
62 #define __IO volatile
63 #endif
64 #ifndef __I
65 #define __I volatile const
66 #endif
67 #ifndef __O
68 #define __O volatile
69 #endif
70 #ifndef __R
71 #define __R volatile const
72 #endif
73 
75 /* **** Definitions **** */
76 
88 typedef struct {
89  __IO uint32_t sysctrl;
90  __IO uint32_t rst0;
91  __IO uint32_t clkctrl;
92  __IO uint32_t pm;
93  __R uint32_t rsv_0x10_0x17[2];
94  __IO uint32_t pclkdiv;
95  __R uint32_t rsv_0x1c_0x23[2];
96  __IO uint32_t pclkdis0;
97  __IO uint32_t memctrl;
98  __IO uint32_t memz;
99  __R uint32_t rsv_0x30_0x3f[4];
100  __IO uint32_t sysst;
101  __IO uint32_t rst1;
102  __IO uint32_t pclkdis1;
103  __IO uint32_t eventen;
104  __I uint32_t revision;
105  __IO uint32_t sysie;
106  __R uint32_t rsv_0x58_0x63[3];
107  __IO uint32_t eccerr;
108  __IO uint32_t eccced;
109  __IO uint32_t eccie;
110  __IO uint32_t eccaddr;
111  __IO uint32_t btleldoctrl;
112  __IO uint32_t btleldodly;
114 
115 /* Register offsets for module GCR */
122  #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL)
123  #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL)
124  #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL)
125  #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL)
126  #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL)
127  #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL)
128  #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL)
129  #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL)
130  #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL)
131  #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL)
132  #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL)
133  #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL)
134  #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL)
135  #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL)
136  #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL)
137  #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL)
138  #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL)
139  #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL)
140  #define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL)
141  #define MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL)
150  #define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 1
151  #define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS))
153  #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS 4
154  #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS))
156  #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6
157  #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS))
159  #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12
160  #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS))
162  #define MXC_F_GCR_SYSCTRL_CCHK_POS 13
163  #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS))
165  #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14
166  #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS))
168  #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15
169  #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS))
171  #define MXC_F_GCR_SYSCTRL_OVR_POS 16
172  #define MXC_F_GCR_SYSCTRL_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS))
182  #define MXC_F_GCR_RST0_DMA_POS 0
183  #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS))
185  #define MXC_F_GCR_RST0_WDT0_POS 1
186  #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS))
188  #define MXC_F_GCR_RST0_GPIO0_POS 2
189  #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS))
191  #define MXC_F_GCR_RST0_GPIO1_POS 3
192  #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS))
194  #define MXC_F_GCR_RST0_TMR0_POS 5
195  #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS))
197  #define MXC_F_GCR_RST0_TMR1_POS 6
198  #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS))
200  #define MXC_F_GCR_RST0_TMR2_POS 7
201  #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS))
203  #define MXC_F_GCR_RST0_TMR3_POS 8
204  #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS))
206  #define MXC_F_GCR_RST0_UART0_POS 11
207  #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS))
209  #define MXC_F_GCR_RST0_UART1_POS 12
210  #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS))
212  #define MXC_F_GCR_RST0_SPI1_POS 13
213  #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS))
215  #define MXC_F_GCR_RST0_I2C0_POS 16
216  #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS))
218  #define MXC_F_GCR_RST0_RTC_POS 17
219  #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS))
221  #define MXC_F_GCR_RST0_SMPHR_POS 22
222  #define MXC_F_GCR_RST0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SMPHR_POS))
224  #define MXC_F_GCR_RST0_TRNG_POS 24
225  #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS))
227  #define MXC_F_GCR_RST0_CNN_POS 25
228  #define MXC_F_GCR_RST0_CNN ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CNN_POS))
230  #define MXC_F_GCR_RST0_ADC_POS 26
231  #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS))
233  #define MXC_F_GCR_RST0_UART2_POS 28
234  #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS))
236  #define MXC_F_GCR_RST0_SOFT_POS 29
237  #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS))
239  #define MXC_F_GCR_RST0_PERIPH_POS 30
240  #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS))
242  #define MXC_F_GCR_RST0_SYS_POS 31
243  #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS))
253  #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6
254  #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS))
255  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL)
256  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
257  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL)
258  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
259  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL)
260  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
261  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL)
262  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
263  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL)
264  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
265  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL)
266  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
267  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL)
268  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
269  #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL)
270  #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)
272  #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9
273  #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS))
274  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL)
275  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
276  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL)
277  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
278  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL)
279  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
280  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL)
281  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
282  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL)
283  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
284  #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL)
285  #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)
287  #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13
288  #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS))
290  #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16
291  #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS))
293  #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17
294  #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS))
296  #define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18
297  #define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS))
299  #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19
300  #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS))
302  #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20
303  #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS))
305  #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21
306  #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS))
308  #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24
309  #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS))
311  #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25
312  #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS))
314  #define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26
315  #define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS))
317  #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27
318  #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS))
320  #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28
321  #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS))
323  #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29
324  #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS))
334  #define MXC_F_GCR_PM_MODE_POS 0
335  #define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS))
336  #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL)
337  #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS)
338  #define MXC_V_GCR_PM_MODE_CM4 ((uint32_t)0x1UL)
339  #define MXC_S_GCR_PM_MODE_CM4 (MXC_V_GCR_PM_MODE_CM4 << MXC_F_GCR_PM_MODE_POS)
340  #define MXC_V_GCR_PM_MODE_STANDBY ((uint32_t)0x2UL)
341  #define MXC_S_GCR_PM_MODE_STANDBY (MXC_V_GCR_PM_MODE_STANDBY << MXC_F_GCR_PM_MODE_POS)
342  #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL)
343  #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS)
344  #define MXC_V_GCR_PM_MODE_LPM ((uint32_t)0x8UL)
345  #define MXC_S_GCR_PM_MODE_LPM (MXC_V_GCR_PM_MODE_LPM << MXC_F_GCR_PM_MODE_POS)
346  #define MXC_V_GCR_PM_MODE_UPM ((uint32_t)0x9UL)
347  #define MXC_S_GCR_PM_MODE_UPM (MXC_V_GCR_PM_MODE_UPM << MXC_F_GCR_PM_MODE_POS)
348  #define MXC_V_GCR_PM_MODE_POWERDOWN ((uint32_t)0xAUL)
349  #define MXC_S_GCR_PM_MODE_POWERDOWN (MXC_V_GCR_PM_MODE_POWERDOWN << MXC_F_GCR_PM_MODE_POS)
351  #define MXC_F_GCR_PM_GPIO_WE_POS 4
352  #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS))
354  #define MXC_F_GCR_PM_RTC_WE_POS 5
355  #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS))
357  #define MXC_F_GCR_PM_WUT_WE_POS 7
358  #define MXC_F_GCR_PM_WUT_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUT_WE_POS))
360  #define MXC_F_GCR_PM_AINCOMP_WE_POS 9
361  #define MXC_F_GCR_PM_AINCOMP_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_AINCOMP_WE_POS))
363  #define MXC_F_GCR_PM_ISO_PD_POS 15
364  #define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS))
366  #define MXC_F_GCR_PM_IPO_PD_POS 16
367  #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS))
369  #define MXC_F_GCR_PM_IBRO_PD_POS 17
370  #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS))
372  #define MXC_F_GCR_PM_ERFO_BP_POS 20
373  #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS))
383  #define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10
384  #define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS))
386  #define MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS 14
387  #define MXC_F_GCR_PCLKDIV_CNNCLKDIV ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS))
388  #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 ((uint32_t)0x0UL)
389  #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV2 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)
390  #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 ((uint32_t)0x1UL)
391  #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)
392  #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 ((uint32_t)0x2UL)
393  #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)
394  #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 ((uint32_t)0x3UL)
395  #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)
396  #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 ((uint32_t)0x4UL)
397  #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV1 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)
399  #define MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS 17
400  #define MXC_F_GCR_PCLKDIV_CNNCLKSEL ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS))
410  #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0
411  #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS))
413  #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1
414  #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS))
416  #define MXC_F_GCR_PCLKDIS0_DMA_POS 5
417  #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS))
419  #define MXC_F_GCR_PCLKDIS0_SPI1_POS 6
420  #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS))
422  #define MXC_F_GCR_PCLKDIS0_UART0_POS 9
423  #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS))
425  #define MXC_F_GCR_PCLKDIS0_UART1_POS 10
426  #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS))
428  #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13
429  #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS))
431  #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15
432  #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS))
434  #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16
435  #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS))
437  #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17
438  #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS))
440  #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18
441  #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS))
443  #define MXC_F_GCR_PCLKDIS0_ADC_POS 23
444  #define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS))
446  #define MXC_F_GCR_PCLKDIS0_CNN_POS 25
447  #define MXC_F_GCR_PCLKDIS0_CNN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CNN_POS))
449  #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28
450  #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS))
452  #define MXC_F_GCR_PCLKDIS0_PT_POS 29
453  #define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS))
463  #define MXC_F_GCR_MEMCTRL_FWS_POS 0
464  #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS))
466  #define MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS 16
467  #define MXC_F_GCR_MEMCTRL_SYSRAM0ECC ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS))
477  #define MXC_F_GCR_MEMZ_RAM0_POS 0
478  #define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS))
480  #define MXC_F_GCR_MEMZ_RAM1_POS 1
481  #define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS))
483  #define MXC_F_GCR_MEMZ_RAM2_POS 2
484  #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS))
486  #define MXC_F_GCR_MEMZ_RAM3_POS 3
487  #define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS))
489  #define MXC_F_GCR_MEMZ_ICC1_POS 14
490  #define MXC_F_GCR_MEMZ_ICC1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS))
500  #define MXC_F_GCR_SYSST_ICELOCK_POS 0
501  #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS))
511  #define MXC_F_GCR_RST1_I2C1_POS 0
512  #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))
514  #define MXC_F_GCR_RST1_PT_POS 1
515  #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))
517  #define MXC_F_GCR_RST1_OWM_POS 7
518  #define MXC_F_GCR_RST1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS))
520  #define MXC_F_GCR_RST1_WDT1_POS 8
521  #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS))
523  #define MXC_F_GCR_RST1_CRC_POS 9
524  #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS))
526  #define MXC_F_GCR_RST1_AES_POS 10
527  #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS))
529  #define MXC_F_GCR_RST1_SPI0_POS 11
530  #define MXC_F_GCR_RST1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI0_POS))
532  #define MXC_F_GCR_RST1_SMPHR_POS 16
533  #define MXC_F_GCR_RST1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS))
535  #define MXC_F_GCR_RST1_I2S_POS 19
536  #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))
538  #define MXC_F_GCR_RST1_I2C2_POS 20
539  #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))
541  #define MXC_F_GCR_RST1_DVS_POS 24
542  #define MXC_F_GCR_RST1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS))
544  #define MXC_F_GCR_RST1_SIMO_POS 25
545  #define MXC_F_GCR_RST1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS))
547  #define MXC_F_GCR_RST1_CPU1_POS 31
548  #define MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS))
558  #define MXC_F_GCR_PCLKDIS1_BTLE_POS 0
559  #define MXC_F_GCR_PCLKDIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_BTLE_POS))
561  #define MXC_F_GCR_PCLKDIS1_UART2_POS 1
562  #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS))
564  #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2
565  #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS))
567  #define MXC_F_GCR_PCLKDIS1_SMPHR_POS 9
568  #define MXC_F_GCR_PCLKDIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SMPHR_POS))
570  #define MXC_F_GCR_PCLKDIS1_OWM_POS 13
571  #define MXC_F_GCR_PCLKDIS1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWM_POS))
573  #define MXC_F_GCR_PCLKDIS1_CRC_POS 14
574  #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS))
576  #define MXC_F_GCR_PCLKDIS1_AES_POS 15
577  #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS))
579  #define MXC_F_GCR_PCLKDIS1_SPI0_POS 16
580  #define MXC_F_GCR_PCLKDIS1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI0_POS))
582  #define MXC_F_GCR_PCLKDIS1_PCIF_POS 18
583  #define MXC_F_GCR_PCLKDIS1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PCIF_POS))
585  #define MXC_F_GCR_PCLKDIS1_I2S_POS 23
586  #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS))
588  #define MXC_F_GCR_PCLKDIS1_I2C2_POS 24
589  #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS))
591  #define MXC_F_GCR_PCLKDIS1_WDT0_POS 27
592  #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS))
594  #define MXC_F_GCR_PCLKDIS1_CPU1_POS 31
595  #define MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS))
605  #define MXC_F_GCR_EVENTEN_DMA_POS 0
606  #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS))
608  #define MXC_F_GCR_EVENTEN_RX_POS 1
609  #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS))
611  #define MXC_F_GCR_EVENTEN_TX_POS 2
612  #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS))
622  #define MXC_F_GCR_REVISION_REVISION_POS 0
623  #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS))
633  #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0
634  #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS))
644  #define MXC_F_GCR_ECCERR_RAM_POS 0
645  #define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS))
655  #define MXC_F_GCR_ECCCED_RAM_POS 0
656  #define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS))
666  #define MXC_F_GCR_ECCIE_RAM_POS 0
667  #define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS))
677  #define MXC_F_GCR_ECCADDR_ECCERRAD_POS 0
678  #define MXC_F_GCR_ECCADDR_ECCERRAD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_ECCADDR_ECCERRAD_POS))
688  #define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0
689  #define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS))
691  #define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1
692  #define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS))
694  #define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS 2
695  #define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS))
697  #define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS 3
698  #define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS))
700  #define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4
701  #define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS))
703  #define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5
704  #define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS))
706  #define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS 6
707  #define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS))
709  #define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS 7
710  #define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS))
712  #define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8
713  #define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS))
715  #define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9
716  #define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS))
718  #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10
719  #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS))
721  #define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11
722  #define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS))
724  #define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12
725  #define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS))
727  #define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13
728  #define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS))
730  #define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14
731  #define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS))
733  #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15
734  #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS))
744  #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0
745  #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS))
747  #define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 8
748  #define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS))
750  #define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 20
751  #define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS))
755 #ifdef __cplusplus
756 }
757 #endif
758 
759 #endif /* _GCR_REGS_H_ */
__IO uint32_t memz
Definition: gcr_regs.h:98
__IO uint32_t eccerr
Definition: gcr_regs.h:107
__IO uint32_t btleldodly
Definition: gcr_regs.h:112
__IO uint32_t pclkdis0
Definition: gcr_regs.h:96
__IO uint32_t eccced
Definition: gcr_regs.h:108
__IO uint32_t btleldoctrl
Definition: gcr_regs.h:111
__IO uint32_t pclkdiv
Definition: gcr_regs.h:94
__IO uint32_t eventen
Definition: gcr_regs.h:103
__IO uint32_t pm
Definition: gcr_regs.h:92
__IO uint32_t eccie
Definition: gcr_regs.h:109
__IO uint32_t rst0
Definition: gcr_regs.h:90
__IO uint32_t memctrl
Definition: gcr_regs.h:97
__IO uint32_t clkctrl
Definition: gcr_regs.h:91
__IO uint32_t eccaddr
Definition: gcr_regs.h:110
Definition: gcr_regs.h:88
__IO uint32_t sysie
Definition: gcr_regs.h:105
__IO uint32_t rst1
Definition: gcr_regs.h:101
__IO uint32_t sysctrl
Definition: gcr_regs.h:89
__IO uint32_t pclkdis1
Definition: gcr_regs.h:102
__IO uint32_t sysst
Definition: gcr_regs.h:100
__I uint32_t revision
Definition: gcr_regs.h:104