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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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Go to the source code of this file.
Direct Memory Access low level access library.
Data Structures | |
union | tDMA_ctrl |
This union and its structure lists the bit assignments for the channel_cfg memory location. More... | |
struct | DMA_entry |
Macros | |
#define | DMA_CH0 (0u) |
DMA channel selection macro, DMA CH0. More... | |
#define | DMA_CH1 (1u) |
DMA channel selection macro, DMA CH1. More... | |
#define | DMA_CH2 (2u) |
DMA channel selection macro, DMA CH2. More... | |
#define | DMA_CH3 (3u) |
DMA channel selection macro, DMA CH3. More... | |
#define | DMA_CH4 (4u) |
DMA channel selection macro, DMA CH4. More... | |
#define | DMA_CH5 (5u) |
DMA channel selection macro, DMA CH5. More... | |
#define | DMA_CH6 (6u) |
DMA channel selection macro, DMA CH6. More... | |
#define | DMA_CH7 (7u) |
DMA channel selection macro, DMA CH7. More... | |
#define | DMA_MASK_CH0 ((uint16)1u << DMA_CH0) |
DMA channel Mask macro, DMA CH0 MASK. More... | |
#define | DMA_MASK_CH1 ((uint16)1u << DMA_CH1) |
DMA channel Mask macro, DMA CH1 MASK. More... | |
#define | DMA_MASK_CH2 ((uint16)1u << DMA_CH2) |
DMA channel Mask macro, DMA CH2 MASK. More... | |
#define | DMA_MASK_CH3 ((uint16)1u << DMA_CH3) |
DMA channel Mask macro, DMA CH3 MASK. More... | |
#define | DMA_MASK_CH4 ((uint16)1u << DMA_CH4) |
DMA channel Mask macro, DMA CH4 MASK. More... | |
#define | DMA_MASK_CH5 ((uint16)1u << DMA_CH5) |
DMA channel Mask macro, DMA CH5 MASK. More... | |
#define | DMA_MASK_CH6 ((uint16)1u << DMA_CH6) |
DMA channel Mask macro, DMA CH6 MASK. More... | |
#define | DMA_MASK_CH7 ((uint16)1u << DMA_CH7) |
DMA channel Mask macro, DMA CH7 MASK. More... | |
Typedefs | |
typedef enum DMA_transferSize | tDMA_transferSize |
typedef enum DMA_incrementSize | tDMA_incrementSize |
typedef enum DMA_incrementMode | tDMA_incrementMode |
typedef enum DMA_cycleType | tDMA_cycleType |
typedef struct DMA_entry | tDMA_entry |
Enumerations | |
enum | DMA_transferSize { DMA_transferSize_8bit = 0u , DMA_transferSize_16bit = 1u , DMA_transferSize_32bit = 2u } |
This enum lists the transfer size options for the DMA. More... | |
enum | DMA_incrementSize { DMA_incrementSize_8bit = 0u , DMA_incrementSize_16bit = 1u , DMA_incrementSize_32bit = 2u } |
This enum lists the increment size options for the DMA. More... | |
enum | DMA_incrementMode { DMA_incrementMode_srcInc = 0u , DMA_incrementMode_dstInc = 1u , DMA_incrementMode_srcDstInc = 2u , DMA_incrementMode_noInc = 3u } |
This enum lists the increment mode options for the DMA. More... | |
enum | DMA_cycleType { DMA_cycleType_Invalid = 0u , DMA_cycleType_Basic = 1u , DMA_cycleType_Auto = 2u , DMA_cycleType_PingPong = 3u , DMA_cycleType_MemSctGthPrim = 4u , DMA_cycleType_MemSctGthAlt = 5u , DMA_cycleType_PerSctGthPrim = 6u , DMA_cycleType_PerSctGthAlt = 7u } |
This enum lists the cycle type options for the DMA. More... | |
Functions | |
sint8 | DMA_init (void) |
Initialize the DMA structure in RAM and SFRs according to the ConfigWizard settings. More... | |
void | DMA_setBasicTransfer (uint8 u8_chIdx, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode) |
Set up a basic transfer for the desired DMA channel in the primary structure in RAM. More... | |
void | DMA_resetChannel (uint8 u8_chIdx, uint32 u32_transferCnt) |
Reset the primary structure in RAM for a given channel and rearm it. More... | |
void | DMA_setMemSctGth (uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt) |
Set up a channel to operate in Memory Scatter-Gather mode on a given task list. More... | |
void | DMA_setPerSctGth (uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt) |
Set up a channel to operate in Peripheral Scatter-Gather mode on a given task list. More... | |
tDMA_entry * | DMA_setPrimaryTaskSctGth (tDMA_entry *s_primEntry, uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt) |
Set up the primary task to configure the scatter-gather mode. More... | |
tDMA_entry * | DMA_setTaskSctGth (tDMA_entry *s_entry, tDMA_cycleType e_cycleType, uint8 u8_Rpower, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode) |
Set up a task to be used in the scatter-gather mode. More... | |
INLINE void | DMA_enMaster (void) |
Enable DMA Master. More... | |
INLINE void | DMA_enCh0EndlessMode (void) |
Enable DMA Channel 0 Endless Mode. More... | |
INLINE void | DMA_disCh0EndlessMode (void) |
Disable DMA Channel 0 Endless Mode. More... | |
INLINE void | DMA_enCh1EndlessMode (void) |
Enable DMA Channel 1 Endless Mode. More... | |
INLINE void | DMA_disCh1EndlessMode (void) |
Disable DMA Channel 1 Endless Mode. More... | |
INLINE void | DMA_enCh2EndlessMode (void) |
Enable DMA Channel 2 Endless Mode. More... | |
INLINE void | DMA_disCh2EndlessMode (void) |
Disable DMA Channel 2 Endless Mode. More... | |
INLINE void | DMA_enCh3EndlessMode (void) |
Enable DMA Channel 3 Endless Mode. More... | |
INLINE void | DMA_disCh3EndlessMode (void) |
Disable DMA Channel 3 Endless Mode. More... | |
INLINE void | DMA_enCh4EndlessMode (void) |
Enable DMA Channel 4 Endless Mode. More... | |
INLINE void | DMA_disCh4EndlessMode (void) |
Disable DMA Channel 4 Endless Mode. More... | |
INLINE void | DMA_enCh5EndlessMode (void) |
Enable DMA Channel 5 Endless Mode. More... | |
INLINE void | DMA_disCh5EndlessMode (void) |
Disable DMA Channel 5 Endless Mode. More... | |
INLINE void | DMA_enCh6EndlessMode (void) |
Enable DMA Channel 6 Endless Mode. More... | |
INLINE void | DMA_disCh6EndlessMode (void) |
Disable DMA Channel 6 Endless Mode. More... | |
INLINE void | DMA_enCh7EndlessMode (void) |
Enable DMA Channel 7 Endless Mode. More... | |
INLINE void | DMA_disCh7EndlessMode (void) |
Disable DMA Channel 7 Endless Mode. More... | |
INLINE void | DMA_enCh0Int (void) |
Enable DMA Channel 0 Interrupt. More... | |
INLINE void | DMA_disCh0Int (void) |
Disable DMA Channel 0 Interrupt. More... | |
INLINE void | DMA_enCh1Int (void) |
Enable DMA Channel 1 Interrupt. More... | |
INLINE void | DMA_disCh1Int (void) |
Disable DMA Channel 1 Interrupt. More... | |
INLINE void | DMA_enCh2Int (void) |
Enable DMA Channel 2 Interrupt. More... | |
INLINE void | DMA_disCh2Int (void) |
Disable DMA Channel 2 Interrupt. More... | |
INLINE void | DMA_enCh3Int (void) |
Enable DMA Channel 3 Interrupt. More... | |
INLINE void | DMA_disCh3Int (void) |
Disable DMA Channel 3 Interrupt. More... | |
INLINE void | DMA_enCh4Int (void) |
Enable DMA Channel 4 Interrupt. More... | |
INLINE void | DMA_disCh4Int (void) |
Disable DMA Channel 4 Interrupt. More... | |
INLINE void | DMA_enCh5Int (void) |
Enable DMA Channel 5 Interrupt. More... | |
INLINE void | DMA_disCh5Int (void) |
Disable DMA Channel 5 Interrupt. More... | |
INLINE void | DMA_enCh6Int (void) |
Enable DMA Channel 6 Interrupt. More... | |
INLINE void | DMA_disCh6Int (void) |
Disable DMA Channel 6 Interrupt. More... | |
INLINE void | DMA_enCh7Int (void) |
Enable DMA Channel 7 Interrupt. More... | |
INLINE void | DMA_disCh7Int (void) |
Disable DMA Channel 7 Interrupt. More... | |
INLINE void | DMA_enErrInt (void) |
Enable DMA Transfer Error Interrupt. More... | |
INLINE void | DMA_disErrInt (void) |
Disable DMA Transfer Error Interrupt. More... | |
INLINE uint8 | DMA_getCh0IntSts (void) |
Get DMA Channel 0 Interrupt Status. More... | |
INLINE uint8 | DMA_getCh1IntSts (void) |
Get DMA Channel 1 Interrupt Status. More... | |
INLINE uint8 | DMA_getCh2IntSts (void) |
Get DMA Channel 2 Interrupt Status. More... | |
INLINE uint8 | DMA_getCh3IntSts (void) |
Get DMA Channel 3 Interrupt Status. More... | |
INLINE uint8 | DMA_getCh4IntSts (void) |
Get DMA Channel 4 Interrupt Status. More... | |
INLINE uint8 | DMA_getCh5IntSts (void) |
Get DMA Channel 5 Interrupt Status. More... | |
INLINE uint8 | DMA_getCh6IntSts (void) |
Get DMA Channel 6 Interrupt Status. More... | |
INLINE uint8 | DMA_getCh7IntSts (void) |
Get DMA Channel 7 Interrupt Status. More... | |
INLINE void | DMA_clrCh0IntSts (void) |
Clear DMA Channel 0 Interrupt Status. More... | |
INLINE void | DMA_clrCh1IntSts (void) |
Clear DMA Channel 1 Interrupt Status. More... | |
INLINE void | DMA_clrCh2IntSts (void) |
Clear DMA Channel 2 Interrupt Status. More... | |
INLINE void | DMA_clrCh3IntSts (void) |
Clear DMA Channel 3 Interrupt Status. More... | |
INLINE void | DMA_clrCh4IntSts (void) |
Clear DMA Channel 4 Interrupt Status. More... | |
INLINE void | DMA_clrCh5IntSts (void) |
Clear DMA Channel 5 Interrupt Status. More... | |
INLINE void | DMA_clrCh6IntSts (void) |
Clear DMA Channel 6 Interrupt Status. More... | |
INLINE void | DMA_clrCh7IntSts (void) |
Clear DMA Channel 7 Interrupt Status. More... | |
INLINE void | DMA_setSWReq (uint8 u8_chIdx) |
Sets the SW request for the given channel. More... | |
void | DMA_setCh0IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 0 Interrupt Node Pointer. More... | |
void | DMA_setCh1IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 1 Interrupt Node Pointer. More... | |
void | DMA_setCh2IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 2 Interrupt Node Pointer. More... | |
void | DMA_setCh3IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 3 Interrupt Node Pointer. More... | |
void | DMA_setCh4IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 4 Interrupt Node Pointer. More... | |
void | DMA_setCh5IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 5 Interrupt Node Pointer. More... | |
void | DMA_setCh6IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 6 Interrupt Node Pointer. More... | |
void | DMA_setCh7IntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel 7 Interrupt Node Pointer. More... | |
void | DMA_setErrIntNodePtr (void) __attribute__((deprecated("Do not change this at runtime |
Set Channel Bus Error Interrupt Node Pointer. More... | |
Variables | |
void use the ConfigWizard to configure this | feature |
#define DMA_CH0 (0u) |
DMA channel selection macro, DMA CH0.
#define DMA_CH1 (1u) |
DMA channel selection macro, DMA CH1.
#define DMA_CH2 (2u) |
DMA channel selection macro, DMA CH2.
#define DMA_CH3 (3u) |
DMA channel selection macro, DMA CH3.
#define DMA_CH4 (4u) |
DMA channel selection macro, DMA CH4.
#define DMA_CH5 (5u) |
DMA channel selection macro, DMA CH5.
#define DMA_CH6 (6u) |
DMA channel selection macro, DMA CH6.
#define DMA_CH7 (7u) |
DMA channel selection macro, DMA CH7.
typedef enum DMA_cycleType tDMA_cycleType |
typedef struct DMA_entry tDMA_entry |
typedef enum DMA_incrementMode tDMA_incrementMode |
typedef enum DMA_incrementSize tDMA_incrementSize |
typedef enum DMA_transferSize tDMA_transferSize |
enum DMA_cycleType |
This enum lists the cycle type options for the DMA.
enum DMA_incrementMode |
This enum lists the increment mode options for the DMA.
enum DMA_incrementSize |
enum DMA_transferSize |
INLINE void DMA_clrCh0IntSts | ( | void | ) |
Clear DMA Channel 0 Interrupt Status.
INLINE void DMA_clrCh1IntSts | ( | void | ) |
Clear DMA Channel 1 Interrupt Status.
INLINE void DMA_clrCh2IntSts | ( | void | ) |
Clear DMA Channel 2 Interrupt Status.
INLINE void DMA_clrCh3IntSts | ( | void | ) |
Clear DMA Channel 3 Interrupt Status.
INLINE void DMA_clrCh4IntSts | ( | void | ) |
Clear DMA Channel 4 Interrupt Status.
INLINE void DMA_clrCh5IntSts | ( | void | ) |
Clear DMA Channel 5 Interrupt Status.
INLINE void DMA_clrCh6IntSts | ( | void | ) |
Clear DMA Channel 6 Interrupt Status.
INLINE void DMA_clrCh7IntSts | ( | void | ) |
Clear DMA Channel 7 Interrupt Status.
INLINE void DMA_disCh0EndlessMode | ( | void | ) |
Disable DMA Channel 0 Endless Mode.
INLINE void DMA_disCh0Int | ( | void | ) |
Disable DMA Channel 0 Interrupt.
INLINE void DMA_disCh1EndlessMode | ( | void | ) |
Disable DMA Channel 1 Endless Mode.
INLINE void DMA_disCh1Int | ( | void | ) |
Disable DMA Channel 1 Interrupt.
INLINE void DMA_disCh2EndlessMode | ( | void | ) |
Disable DMA Channel 2 Endless Mode.
INLINE void DMA_disCh2Int | ( | void | ) |
Disable DMA Channel 2 Interrupt.
INLINE void DMA_disCh3EndlessMode | ( | void | ) |
Disable DMA Channel 3 Endless Mode.
INLINE void DMA_disCh3Int | ( | void | ) |
Disable DMA Channel 3 Interrupt.
INLINE void DMA_disCh4EndlessMode | ( | void | ) |
Disable DMA Channel 4 Endless Mode.
INLINE void DMA_disCh4Int | ( | void | ) |
Disable DMA Channel 4 Interrupt.
INLINE void DMA_disCh5EndlessMode | ( | void | ) |
Disable DMA Channel 5 Endless Mode.
INLINE void DMA_disCh5Int | ( | void | ) |
Disable DMA Channel 5 Interrupt.
INLINE void DMA_disCh6EndlessMode | ( | void | ) |
Disable DMA Channel 6 Endless Mode.
INLINE void DMA_disCh6Int | ( | void | ) |
Disable DMA Channel 6 Interrupt.
INLINE void DMA_disCh7EndlessMode | ( | void | ) |
Disable DMA Channel 7 Endless Mode.
INLINE void DMA_disCh7Int | ( | void | ) |
Disable DMA Channel 7 Interrupt.
INLINE void DMA_disErrInt | ( | void | ) |
Disable DMA Transfer Error Interrupt.
INLINE void DMA_enCh0EndlessMode | ( | void | ) |
Enable DMA Channel 0 Endless Mode.
INLINE void DMA_enCh0Int | ( | void | ) |
Enable DMA Channel 0 Interrupt.
INLINE void DMA_enCh1EndlessMode | ( | void | ) |
Enable DMA Channel 1 Endless Mode.
INLINE void DMA_enCh1Int | ( | void | ) |
Enable DMA Channel 1 Interrupt.
INLINE void DMA_enCh2EndlessMode | ( | void | ) |
Enable DMA Channel 2 Endless Mode.
INLINE void DMA_enCh2Int | ( | void | ) |
Enable DMA Channel 2 Interrupt.
INLINE void DMA_enCh3EndlessMode | ( | void | ) |
Enable DMA Channel 3 Endless Mode.
INLINE void DMA_enCh3Int | ( | void | ) |
Enable DMA Channel 3 Interrupt.
INLINE void DMA_enCh4EndlessMode | ( | void | ) |
Enable DMA Channel 4 Endless Mode.
INLINE void DMA_enCh4Int | ( | void | ) |
Enable DMA Channel 4 Interrupt.
INLINE void DMA_enCh5EndlessMode | ( | void | ) |
Enable DMA Channel 5 Endless Mode.
INLINE void DMA_enCh5Int | ( | void | ) |
Enable DMA Channel 5 Interrupt.
INLINE void DMA_enCh6EndlessMode | ( | void | ) |
Enable DMA Channel 6 Endless Mode.
INLINE void DMA_enCh6Int | ( | void | ) |
Enable DMA Channel 6 Interrupt.
INLINE void DMA_enCh7EndlessMode | ( | void | ) |
Enable DMA Channel 7 Endless Mode.
INLINE void DMA_enCh7Int | ( | void | ) |
Enable DMA Channel 7 Interrupt.
INLINE void DMA_enErrInt | ( | void | ) |
Enable DMA Transfer Error Interrupt.
INLINE void DMA_enMaster | ( | void | ) |
Enable DMA Master.
Get DMA Channel 0 Interrupt Status.
Get DMA Channel 1 Interrupt Status.
Get DMA Channel 2 Interrupt Status.
Get DMA Channel 3 Interrupt Status.
Get DMA Channel 4 Interrupt Status.
Get DMA Channel 5 Interrupt Status.
Get DMA Channel 6 Interrupt Status.
Get DMA Channel 7 Interrupt Status.
sint8 DMA_init | ( | void | ) |
Initialize the DMA structure in RAM and SFRs according to the ConfigWizard settings.
Reset the primary structure in RAM for a given channel and rearm it.
u8_chIdx | DMA channel to be reset |
u32_transferCnt | Number of transfers |
void DMA_setBasicTransfer | ( | uint8 | u8_chIdx, |
uint32 | u32_srcAddr, | ||
uint32 | u32_dstAddr, | ||
uint32 | u32_transferCnt, | ||
tDMA_transferSize | e_transferSize, | ||
tDMA_incrementMode | e_incrementMode | ||
) |
Set up a basic transfer for the desired DMA channel in the primary structure in RAM.
u8_chIdx | DMA channel to be set up |
u32_srcAddr | Address pointing to the source location |
u32_dstAddr | Address pointing to the destination location |
u32_transferCnt | Number of transfers |
e_transferSize | Data width for each transfer, see tDMA_transferSize |
e_incrementMode | incrementing scheme used for the transfer, see tDMA_incrementMode |
void DMA_setCh0IntNodePtr | ( | void | ) |
Set Channel 0 Interrupt Node Pointer.
void DMA_setCh1IntNodePtr | ( | void | ) |
Set Channel 1 Interrupt Node Pointer.
void DMA_setCh2IntNodePtr | ( | void | ) |
Set Channel 2 Interrupt Node Pointer.
void DMA_setCh3IntNodePtr | ( | void | ) |
Set Channel 3 Interrupt Node Pointer.
void DMA_setCh4IntNodePtr | ( | void | ) |
Set Channel 4 Interrupt Node Pointer.
void DMA_setCh5IntNodePtr | ( | void | ) |
Set Channel 5 Interrupt Node Pointer.
void DMA_setCh6IntNodePtr | ( | void | ) |
Set Channel 6 Interrupt Node Pointer.
void DMA_setCh7IntNodePtr | ( | void | ) |
Set Channel 7 Interrupt Node Pointer.
void DMA_setErrIntNodePtr | ( | void | ) |
Set Channel Bus Error Interrupt Node Pointer.
void DMA_setMemSctGth | ( | uint8 | u8_chIdx, |
tDMA_entry * | s_taskList, | ||
uint32 | u32_taskCnt | ||
) |
Set up a channel to operate in Memory Scatter-Gather mode on a given task list.
u8_chIdx | DMA channel to be set up |
s_taskList | Points to the task structure defined in RAM, see DMA_setTaskSctGth |
u32_taskCnt | Number of tasks in the s_taskList |
void DMA_setPerSctGth | ( | uint8 | u8_chIdx, |
tDMA_entry * | s_taskList, | ||
uint32 | u32_taskCnt | ||
) |
Set up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
u8_chIdx | DMA channel to be set up |
s_taskList | Points to the task structure defined in RAM, see DMA_setTaskSctGth |
u32_taskCnt | Number of tasks in the s_taskList |
tDMA_entry* DMA_setPrimaryTaskSctGth | ( | tDMA_entry * | s_primEntry, |
uint8 | u8_chIdx, | ||
tDMA_entry * | s_taskList, | ||
uint32 | u32_taskCnt | ||
) |
Set up the primary task to configure the scatter-gather mode.
The DMA scather-gather mode can be used to perform multiple but different DMA transfers initiated with one trigger.
The last task can be used to self-arm this scatter-gather transfer again.
s_primEntry | Pointer to the task |
u8_chIdx | DMA channel for with the task is setup |
s_taskList | Pointer to the task list to be executed with this DMA transfer |
u32_taskCnt | Number of tasks defined in the task list |
Sets the SW request for the given channel.
u8_chIdx | DMA channel number, recommended to use the defines DMA_CHx |
tDMA_entry* DMA_setTaskSctGth | ( | tDMA_entry * | s_entry, |
tDMA_cycleType | e_cycleType, | ||
uint8 | u8_Rpower, | ||
uint32 | u32_srcAddr, | ||
uint32 | u32_dstAddr, | ||
uint32 | u32_transferCnt, | ||
tDMA_transferSize | e_transferSize, | ||
tDMA_incrementMode | e_incrementMode | ||
) |
Set up a task to be used in the scatter-gather mode.
s_entry | pointer to the task structure tDMA_entry |
e_cycleType | defines the type of DMA transfer to be performed, see tDMA_cycleType |
u8_Rpower | Arbitration rate, defines after how many DMA transfers (2^u8_Rpower) the controller rearbitrates |
u32_srcAddr | Address pointing to the source location |
u32_dstAddr | Address pointing to the destination location |
u32_transferCnt | Number of transfers |
e_transferSize | Data width for each transfer, see tDMA_transferSize |
e_incrementMode | Incrementing scheme used for the transfer, see tDMA_incrementMode |
void use the ConfigWizard to configure this feature |