Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
CANTRX_Type Struct Reference

Detailed Description

CANTRX (CANTRX)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   MODE: 2
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   EN_TXD_TO: 1
 
      __IOM uint32_t   TSIL_EN: 1
 
      uint32_t   __pad1__: 6
 
      __IOM uint32_t   TXD_IN_SEL: 2
 
      uint32_t   __pad2__: 14
 
   }   bit
 
CTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   BUS_TO_IS: 1
 
      __IM uint32_t   TXD_TO_IS: 1
 
      __IM uint32_t   OT_IS: 1
 
      __IM uint32_t   BUS_ACT_IS: 1
 
      uint32_t   __pad0__: 12
 
      __IM uint32_t   BUS_TO_STS: 1
 
      __IM uint32_t   TXD_TO_STS: 1
 
      __IM uint32_t   OT_STS: 1
 
      uint32_t   __pad1__: 1
 
      __IM uint32_t   UV_STS: 1
 
      uint32_t   __pad2__: 11
 
   }   bit
 
IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   BUS_TO_ISC: 1
 
      __OM uint32_t   TXD_TO_ISC: 1
 
      __OM uint32_t   OT_ISC: 1
 
      __OM uint32_t   BUS_ACT_ISC: 1
 
      uint32_t   __pad0__: 12
 
      __OM uint32_t   BUS_TO_SC: 1
 
      __OM uint32_t   TXD_TO_SC: 1
 
      __OM uint32_t   OT_SC: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   BUS_TO_ISS: 1
 
      __OM uint32_t   TXD_TO_ISS: 1
 
      __OM uint32_t   OT_ISS: 1
 
      __OM uint32_t   BUS_ACT_ISS: 1
 
      uint32_t   __pad0__: 12
 
      __OM uint32_t   BUS_TO_SS: 1
 
      __OM uint32_t   TXD_TO_SS: 1
 
      __OM uint32_t   OT_SS: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
IRQSET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BUS_TO_IEN: 1
 
      __IOM uint32_t   TXD_TO_IEN: 1
 
      __IOM uint32_t   OT_IEN: 1
 
      __IOM uint32_t   BUS_ACT_IEN: 1
 
      uint32_t   __pad0__: 28
 
   }   bit
 
IRQEN
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆  [1/5]

struct { ... } bit

◆  [2/5]

struct { ... } bit

◆  [3/5]

struct { ... } bit

◆  [4/5]

struct { ... } bit

◆  [5/5]

struct { ... } bit

◆ BUS_ACT_IEN

__IOM uint32_t BUS_ACT_IEN

[3..3] Bus active during CAN sleep interrupt enable

◆ BUS_ACT_IS

__IM uint32_t BUS_ACT_IS

[3..3] Bus active during CAN sleep interrupt status

◆ BUS_ACT_ISC

__OM uint32_t BUS_ACT_ISC

[3..3] Bus active during CAN sleep interrupt status clear

◆ BUS_ACT_ISS

__OM uint32_t BUS_ACT_ISS

[3..3] Bus active during CAN sleep interrupt status set

◆ BUS_TO_IEN

__IOM uint32_t BUS_TO_IEN

[0..0] Bus dominant timeout interrupt enable

◆ BUS_TO_IS

__IM uint32_t BUS_TO_IS

[0..0] Bus dominant timeout interrupt status

◆ BUS_TO_ISC

__OM uint32_t BUS_TO_ISC

[0..0] Bus dominant timeout interrupt status clear

◆ BUS_TO_ISS

__OM uint32_t BUS_TO_ISS

[0..0] Bus dominant timeout interrupt status set

◆ BUS_TO_SC

__OM uint32_t BUS_TO_SC

[16..16] Bus dominant timeout status clear

◆ BUS_TO_SS

__OM uint32_t BUS_TO_SS

[16..16] Bus dominant timeout status set

◆ BUS_TO_STS

__IM uint32_t BUS_TO_STS

[16..16] Bus dominant timeout status

◆ 

union { ... } CTRL

◆ EN

__IOM uint32_t EN

[0..0] CAN transceiver enable

◆ EN_TXD_TO

__IOM uint32_t EN_TXD_TO

[8..8] Enable transmitter deactivation due to TXD dominant timeout

◆ 

union { ... } IRQCLR

◆ 

union { ... } IRQEN

◆ 

union { ... } IRQS

◆ 

union { ... } IRQSET

◆ MODE

__IOM uint32_t MODE

[2..1] CAN mode control

◆ OT_IEN

__IOM uint32_t OT_IEN

[2..2] CAN overtemperature interrupt enable

◆ OT_IS

__IM uint32_t OT_IS

[2..2] CAN overtemperature interrupt status

◆ OT_ISC

__OM uint32_t OT_ISC

[2..2] CAN overtemperature interrupt status clear

◆ OT_ISS

__OM uint32_t OT_ISS

[2..2] CAN overtemperature interrupt status set

◆ OT_SC

__OM uint32_t OT_SC

[18..18] CAN overtemperature status clear

◆ OT_SS

__OM uint32_t OT_SS

[18..18] CAN overtemperature status set

◆ OT_STS

__IM uint32_t OT_STS

[18..18] CAN overtemperature status

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) CAN transceiver control

(@ 0x00000008) CAN transceiver interrupt status register clear

(@ 0x0000000C) CAN transceiver interrupt status register set

(@ 0x00000010) CAN transceiver interrupt enable

◆ reg [2/2]

__IM uint32_t reg

(@ 0x00000004) CAN transceiver interrupt status

◆ TSIL_EN

__IOM uint32_t TSIL_EN

[9..9] Enable tsilence counter

◆ TXD_IN_SEL

__IOM uint32_t TXD_IN_SEL

[17..16] TXD input selector

◆ TXD_TO_IEN

__IOM uint32_t TXD_TO_IEN

[1..1] TXD dominant timeout interrupt enable

◆ TXD_TO_IS

__IM uint32_t TXD_TO_IS

[1..1] TXD dominant timeout interrupt status

◆ TXD_TO_ISC

__OM uint32_t TXD_TO_ISC

[1..1] TXD dominant timeout interrupt status clear

◆ TXD_TO_ISS

__OM uint32_t TXD_TO_ISS

[1..1] TXD dominant timeout interrupt status set

◆ TXD_TO_SC

__OM uint32_t TXD_TO_SC

[17..17] TXD dominant timeout status clear

◆ TXD_TO_SS

__OM uint32_t TXD_TO_SS

[17..17] TXD dominant timeout status set

◆ TXD_TO_STS

__IM uint32_t TXD_TO_STS

[17..17] TXD dominant timeout status

◆ UV_STS

__IM uint32_t UV_STS

[20..20] CAN supply undervoltage status


The documentation for this struct was generated from the following file: