82 #include "isr_defines.h"
91 #define WARN_INP_NVIC_IRQ0 0
92 #define WARN_INP_NVIC_IRQ1 1
93 #define CCU7_INP_NVIC_IRQ2 0
94 #define CCU7_INP_NVIC_IRQ3 1
95 #define CCU7_INP_NVIC_IRQ4 2
96 #define CCU7_INP_NVIC_IRQ5 3
97 #define MEMCTRL_INP_NVIC_IRQ6 0
98 #define GPT12_INP_NVIC_IRQ7 0
99 #define GPT12_INP_NVIC_IRQ8 1
100 #define ADC2_INP_NVIC_IRQ10 0
101 #define ADC2_INP_NVIC_IRQ11 1
102 #define MON_INP_NVIC_IRQ12 0
103 #define MON_INP_NVIC_IRQ13 1
104 #define ADC1_INP_NVIC_IRQ14 0
105 #define ADC1_INP_NVIC_IRQ15 1
106 #define ADC1_INP_NVIC_IRQ16 2
107 #define ADC1_INP_NVIC_IRQ17 3
108 #define BEMF_SDADC_INP_NVIC_IRQ18 0
109 #define BEMF_SDADC_INP_NVIC_IRQ19 1
110 #define EXTINT_INP_NVIC_IRQ20 0
111 #define EXTINT_INP_NVIC_IRQ21 1
112 #define UART_INP_NVIC_IRQ22 0
113 #define UART_INP_NVIC_IRQ23 1
114 #define SSC_INP_NVIC_IRQ24 0
115 #define SSC_INP_NVIC_IRQ25 1
116 #define CAN_INP_NVIC_IRQ26 0
117 #define CAN_INP_NVIC_IRQ27 1
118 #define CAN_INP_NVIC_IRQ28 2
119 #define DMA_INP_NVIC_IRQ29 0
120 #define DMA_INP_NVIC_IRQ30 1
121 #define T20_INP_NVIC_IRQ9 0
122 #define T21_INP_NVIC_IRQ31 0
124 #ifndef SCU_NMICON_NMIXTALEN_NMI_EN
125 #define SCU_NMICON_NMIXTALEN_NMI_EN 0
127 #ifndef SCU_NMICON_NMIPLL0EN_NMI_EN
128 #define SCU_NMICON_NMIPLL0EN_NMI_EN 0
130 #ifndef SCU_NMICON_NMIPLL1EN_NMI_EN
131 #define SCU_NMICON_NMIPLL1EN_NMI_EN 0
133 #ifndef MEMCTRL_NMICON_NMIDSEN_NMI_EN
134 #define MEMCTRL_NMICON_NMIDSEN_NMI_EN 0
136 #ifndef MEMCTRL_NMICON_NMIPSEN_NMI_EN
137 #define MEMCTRL_NMICON_NMIPSEN_NMI_EN 0
139 #ifndef MEMCTRL_NMICON_NMICDEN_NMI_EN
140 #define MEMCTRL_NMICON_NMICDEN_NMI_EN 0
142 #ifndef MEMCTRL_NMICON_NMINVM0EN_NMI_EN
143 #define MEMCTRL_NMICON_NMINVM0EN_NMI_EN 0
145 #ifndef MEMCTRL_NMICON_NMINVM1EN_NMI_EN
146 #define MEMCTRL_NMICON_NMINVM1EN_NMI_EN 0
148 #ifndef MEMCTRL_NMICON_NMIMAP0EN_NMI_EN
149 #define MEMCTRL_NMICON_NMIMAP0EN_NMI_EN 0
151 #ifndef MEMCTRL_NMICON_NMIMAP1EN_NMI_EN
152 #define MEMCTRL_NMICON_NMIMAP1EN_NMI_EN 0
154 #ifndef MEMCTRL_NMICON_NMIWDTEN_NMI_EN
155 #define MEMCTRL_NMICON_NMIWDTEN_NMI_EN 0
157 #ifndef MEMCTRL_NMICON_NMISTOFEN_NMI_EN
158 #define MEMCTRL_NMICON_NMISTOFEN_NMI_EN 0
160 #ifndef ADC2_UPTH0_INT_EN
161 #define ADC2_UPTH0_INT_EN 0
163 #ifndef ADC2_LOTH0_INT_EN
164 #define ADC2_LOTH0_INT_EN 0
166 #ifndef ADC2_LOTH1_INT_EN
167 #define ADC2_LOTH1_INT_EN 0
169 #ifndef ADC2_UPTH2_INT_EN
170 #define ADC2_UPTH2_INT_EN 0
172 #ifndef ADC2_LOTH2_INT_EN
173 #define ADC2_LOTH2_INT_EN 0
175 #ifndef ADC2_LOTH3_INT_EN
176 #define ADC2_LOTH3_INT_EN 0
178 #ifndef ADC2_UPTH4_INT_EN
179 #define ADC2_UPTH4_INT_EN 0
181 #ifndef CANTRX_BUS_TO_INT_EN
182 #define CANTRX_BUS_TO_INT_EN 0
184 #ifndef CANTRX_TXD_TO_INT_EN
185 #define CANTRX_TXD_TO_INT_EN 0
187 #ifndef CANTRX_OT_INT_EN
188 #define CANTRX_OT_INT_EN 0
190 #ifndef CANTRX_BUS_ACT_INT_EN
191 #define CANTRX_BUS_ACT_INT_EN 0
193 #ifndef BDRV_LS1_OC_INT_EN
194 #define BDRV_LS1_OC_INT_EN 0
196 #ifndef BDRV_LS1_DS_INT_EN
197 #define BDRV_LS1_DS_INT_EN 0
199 #ifndef BDRV_HS1_OC_INT_EN
200 #define BDRV_HS1_OC_INT_EN 0
202 #ifndef BDRV_HS1_DS_INT_EN
203 #define BDRV_HS1_DS_INT_EN 0
205 #ifndef BDRV_LS2_OC_INT_EN
206 #define BDRV_LS2_OC_INT_EN 0
208 #ifndef BDRV_LS2_DS_INT_EN
209 #define BDRV_LS2_DS_INT_EN 0
211 #ifndef BDRV_HS2_OC_INT_EN
212 #define BDRV_HS2_OC_INT_EN 0
214 #ifndef BDRV_HS2_DS_INT_EN
215 #define BDRV_HS2_DS_INT_EN 0
217 #ifndef BDRV_LS3_OC_INT_EN
218 #define BDRV_LS3_OC_INT_EN 0
220 #ifndef BDRV_LS3_DS_INT_EN
221 #define BDRV_LS3_DS_INT_EN 0
223 #ifndef BDRV_HS3_OC_INT_EN
224 #define BDRV_HS3_OC_INT_EN 0
226 #ifndef BDRV_HS3_DS_INT_EN
227 #define BDRV_HS3_DS_INT_EN 0
229 #ifndef BDRV_HB1_ASEQ_INT_EN
230 #define BDRV_HB1_ASEQ_INT_EN 0
232 #ifndef BDRV_HB2_ASEQ_INT_EN
233 #define BDRV_HB2_ASEQ_INT_EN 0
235 #ifndef BDRV_HB3_ASEQ_INT_EN
236 #define BDRV_HB3_ASEQ_INT_EN 0
238 #ifndef BDRV_SEQ_ERR_INT_EN
239 #define BDRV_SEQ_ERR_INT_EN 0
241 #ifndef BDRV_HB1_ACTDRV_INT_EN
242 #define BDRV_HB1_ACTDRV_INT_EN 0
244 #ifndef BDRV_HB2_ACTDRV_INT_EN
245 #define BDRV_HB2_ACTDRV_INT_EN 0
247 #ifndef BDRV_HB3_ACTDRV_INT_EN
248 #define BDRV_HB3_ACTDRV_INT_EN 0
250 #ifndef BDRV_VCP_LOTH2_INT_EN
251 #define BDRV_VCP_LOTH2_INT_EN 0
253 #ifndef CSACSC_OC_INT_EN
254 #define CSACSC_OC_INT_EN 0
256 #ifndef CSACSC_PARAM_INT_EN
257 #define CSACSC_PARAM_INT_EN 0
259 #ifndef PMU_VDDP_UVWARN_INT_EN
260 #define PMU_VDDP_UVWARN_INT_EN 0
262 #ifndef PMU_VDDP_OV_INT_EN
263 #define PMU_VDDP_OV_INT_EN 0
265 #ifndef PMU_VDDC_UVWARN_INT_EN
266 #define PMU_VDDC_UVWARN_INT_EN 0
268 #ifndef PMU_VDDC_OV_INT_EN
269 #define PMU_VDDC_OV_INT_EN 0
271 #ifndef PMU_VDDEXT_UV_INT_EN
272 #define PMU_VDDEXT_UV_INT_EN 0
274 #ifndef PMU_VDDEXT_OT_INT_EN
275 #define PMU_VDDEXT_OT_INT_EN 0
277 #ifndef ARVG_VAREF_OC_INT_EN
278 #define ARVG_VAREF_OC_INT_EN 0
280 #ifndef CCU7_T12_OM_INT_EN
281 #define CCU7_T12_OM_INT_EN 0
283 #ifndef CCU7_T12_PM_INT_EN
284 #define CCU7_T12_PM_INT_EN 0
286 #ifndef CCU7_T13_CM_INT_EN
287 #define CCU7_T13_CM_INT_EN 0
289 #ifndef CCU7_T13_PM_INT_EN
290 #define CCU7_T13_PM_INT_EN 0
292 #ifndef CCU7_T14_CM_INT_EN
293 #define CCU7_T14_CM_INT_EN 0
295 #ifndef CCU7_T14_PM_INT_EN
296 #define CCU7_T14_PM_INT_EN 0
298 #ifndef CCU7_T15_CM_INT_EN
299 #define CCU7_T15_CM_INT_EN 0
301 #ifndef CCU7_T15_PM_INT_EN
302 #define CCU7_T15_PM_INT_EN 0
304 #ifndef CCU7_T16_CM_INT_EN
305 #define CCU7_T16_CM_INT_EN 0
307 #ifndef CCU7_T16_PM_INT_EN
308 #define CCU7_T16_PM_INT_EN 0
310 #ifndef CCU7_CC70A_CM_R_INT_EN
311 #define CCU7_CC70A_CM_R_INT_EN 0
313 #ifndef CCU7_CC70A_CM_F_INT_EN
314 #define CCU7_CC70A_CM_F_INT_EN 0
316 #ifndef CCU7_CC71A_CM_R_INT_EN
317 #define CCU7_CC71A_CM_R_INT_EN 0
319 #ifndef CCU7_CC71A_CM_F_INT_EN
320 #define CCU7_CC71A_CM_F_INT_EN 0
322 #ifndef CCU7_CC71A_CM_R_INT_EN
323 #define CCU7_CC71A_CM_R_INT_EN 0
325 #ifndef CCU7_CC71A_CM_F_INT_EN
326 #define CCU7_CC71A_CM_F_INT_EN 0
328 #ifndef CCU7_C70B_CM_R_INT_EN
329 #define CCU7_C70B_CM_R_INT_EN 0
331 #ifndef CCU7_C70B_CM_F_INT_EN
332 #define CCU7_C70B_CM_F_INT_EN 0
334 #ifndef CCU7_C71B_CM_R_INT_EN
335 #define CCU7_C71B_CM_R_INT_EN 0
337 #ifndef CCU7_C71B_CM_F_INT_EN
338 #define CCU7_C71B_CM_F_INT_EN 0
340 #ifndef CCU7_C72B_CM_R_INT_EN
341 #define CCU7_C72B_CM_R_INT_EN 0
343 #ifndef CCU7_C72B_CM_F_INT_EN
344 #define CCU7_C72B_CM_F_INT_EN 0
346 #ifndef CCU7_TRAP_INT_EN
347 #define CCU7_TRAP_INT_EN 0
349 #ifndef CCU7_CORRECT_HALL_INT_EN
350 #define CCU7_CORRECT_HALL_INT_EN 0
352 #ifndef CCU7_WRONG_HALL_INT_EN
353 #define CCU7_WRONG_HALL_INT_EN 0
355 #ifndef CCU7_MCM_STR_INT_EN
356 #define CCU7_MCM_STR_INT_EN 0
358 #ifndef CCU7_LI_INT_EN
359 #define CCU7_LI_INT_EN 0
361 #ifndef MEMCTRL_NVM0_OP_COMPLETE_INT_EN
362 #define MEMCTRL_NVM0_OP_COMPLETE_INT_EN 0
364 #ifndef MEMCTRL_NVM1_OP_COMPLETE_INT_EN
365 #define MEMCTRL_NVM1_OP_COMPLETE_INT_EN 0
367 #ifndef GPT12_GPT1T2_INT_EN
368 #define GPT12_GPT1T2_INT_EN 0
370 #ifndef GPT12_GPT1T3_INT_EN
371 #define GPT12_GPT1T3_INT_EN 0
373 #ifndef GPT12_GPT1T4_INT_EN
374 #define GPT12_GPT1T4_INT_EN 0
376 #ifndef GPT12_GPT2T5_INT_EN
377 #define GPT12_GPT2T5_INT_EN 0
379 #ifndef GPT12_GPT2T6_INT_EN
380 #define GPT12_GPT2T6_INT_EN 0
382 #ifndef GPT12_GPT2CAPREL_INT_EN
383 #define GPT12_GPT2CAPREL_INT_EN 0
385 #ifndef ADC2_CH0_INT_EN
386 #define ADC2_CH0_INT_EN 0
388 #ifndef ADC2_CH1_INT_EN
389 #define ADC2_CH1_INT_EN 0
391 #ifndef ADC2_CH2_INT_EN
392 #define ADC2_CH2_INT_EN 0
394 #ifndef ADC2_CH3_INT_EN
395 #define ADC2_CH3_INT_EN 0
397 #ifndef ADC2_CH4_INT_EN
398 #define ADC2_CH4_INT_EN 0
400 #ifndef ADC2_CH5_INT_EN
401 #define ADC2_CH5_INT_EN 0
403 #ifndef ADC2_CH6_INT_EN
404 #define ADC2_CH6_INT_EN 0
406 #ifndef ADC2_CH7_INT_EN
407 #define ADC2_CH7_INT_EN 0
409 #ifndef ADC2_CH8_INT_EN
410 #define ADC2_CH8_INT_EN 0
412 #ifndef ADC2_CH9_INT_EN
413 #define ADC2_CH9_INT_EN 0
415 #ifndef ADC2_CH10_INT_EN
416 #define ADC2_CH10_INT_EN 0
418 #ifndef ADC2_CH11_INT_EN
419 #define ADC2_CH11_INT_EN 0
421 #ifndef ADC2_CH12_INT_EN
422 #define ADC2_CH12_INT_EN 0
424 #ifndef ADC2_CH13_INT_EN
425 #define ADC2_CH13_INT_EN 0
427 #ifndef ADC2_CH14_INT_EN
428 #define ADC2_CH14_INT_EN 0
430 #ifndef ADC2_SQ0_INT_EN
431 #define ADC2_SQ0_INT_EN 0
433 #ifndef ADC2_SQ1_INT_EN
434 #define ADC2_SQ1_INT_EN 0
436 #ifndef ADC2_SQ2_INT_EN
437 #define ADC2_SQ2_INT_EN 0
439 #ifndef ADC2_SQ3_INT_EN
440 #define ADC2_SQ3_INT_EN 0
442 #ifndef ADC2_LOTH0_INT_EN
443 #define ADC2_LOTH0_INT_EN 0
445 #ifndef ADC2_LOTH1_INT_EN
446 #define ADC2_LOTH1_INT_EN 0
448 #ifndef ADC2_LOTH2_INT_EN
449 #define ADC2_LOTH2_INT_EN 0
451 #ifndef ADC2_LOTH3_INT_EN
452 #define ADC2_LOTH3_INT_EN 0
454 #ifndef ADC2_LOTH4_INT_EN
455 #define ADC2_LOTH4_INT_EN 0
457 #ifndef ADC2_LOTH5_INT_EN
458 #define ADC2_LOTH5_INT_EN 0
460 #ifndef ADC2_LOTH6_INT_EN
461 #define ADC2_LOTH6_INT_EN 0
463 #ifndef ADC2_LOTH7_INT_EN
464 #define ADC2_LOTH7_INT_EN 0
466 #ifndef ADC2_UPTH0_INT_EN
467 #define ADC2_UPTH0_INT_EN 0
469 #ifndef ADC2_UPTH1_INT_EN
470 #define ADC2_UPTH1_INT_EN 0
472 #ifndef ADC2_UPTH2_INT_EN
473 #define ADC2_UPTH2_INT_EN 0
475 #ifndef ADC2_UPTH3_INT_EN
476 #define ADC2_UPTH3_INT_EN 0
478 #ifndef ADC2_UPTH4_INT_EN
479 #define ADC2_UPTH4_INT_EN 0
481 #ifndef ADC2_UPTH5_INT_EN
482 #define ADC2_UPTH5_INT_EN 0
484 #ifndef ADC2_UPTH6_INT_EN
485 #define ADC2_UPTH6_INT_EN 0
487 #ifndef ADC2_UPTH7_INT_EN
488 #define ADC2_UPTH7_INT_EN 0
490 #ifndef MON_MON1_R_INT_EN
491 #define MON_MON1_R_INT_EN 0
493 #ifndef MON_MON1_F_INT_EN
494 #define MON_MON1_F_INT_EN 0
496 #ifndef MON_MON2_R_INT_EN
497 #define MON_MON2_R_INT_EN 0
499 #ifndef MON_MON2_F_INT_EN
500 #define MON_MON2_F_INT_EN 0
502 #ifndef MON_MON3_R_INT_EN
503 #define MON_MON3_R_INT_EN 0
505 #ifndef MON_MON3_F_INT_EN
506 #define MON_MON3_F_INT_EN 0
508 #ifndef ADC1_CH0_INT_EN
509 #define ADC1_CH0_INT_EN 0
511 #ifndef ADC1_CH1_INT_EN
512 #define ADC1_CH1_INT_EN 0
514 #ifndef ADC1_CH2_INT_EN
515 #define ADC1_CH2_INT_EN 0
517 #ifndef ADC1_CH3_INT_EN
518 #define ADC1_CH3_INT_EN 0
520 #ifndef ADC1_CH4_INT_EN
521 #define ADC1_CH4_INT_EN 0
523 #ifndef ADC1_CH5_INT_EN
524 #define ADC1_CH5_INT_EN 0
526 #ifndef ADC1_CH6_INT_EN
527 #define ADC1_CH6_INT_EN 0
529 #ifndef ADC1_CH7_INT_EN
530 #define ADC1_CH7_INT_EN 0
532 #ifndef ADC1_CH8_INT_EN
533 #define ADC1_CH8_INT_EN 0
535 #ifndef ADC1_CH9_INT_EN
536 #define ADC1_CH9_INT_EN 0
538 #ifndef ADC1_CH10_INT_EN
539 #define ADC1_CH10_INT_EN 0
541 #ifndef ADC1_CH11_INT_EN
542 #define ADC1_CH11_INT_EN 0
544 #ifndef ADC1_CH12_INT_EN
545 #define ADC1_CH12_INT_EN 0
547 #ifndef ADC1_CH13_INT_EN
548 #define ADC1_CH13_INT_EN 0
550 #ifndef ADC1_CH14_INT_EN
551 #define ADC1_CH14_INT_EN 0
553 #ifndef ADC1_CH15_INT_EN
554 #define ADC1_CH15_INT_EN 0
556 #ifndef ADC1_CH16_INT_EN
557 #define ADC1_CH16_INT_EN 0
559 #ifndef ADC1_CH17_INT_EN
560 #define ADC1_CH17_INT_EN 0
562 #ifndef ADC1_CH18_INT_EN
563 #define ADC1_CH18_INT_EN 0
565 #ifndef ADC1_CH19_INT_EN
566 #define ADC1_CH19_INT_EN 0
568 #ifndef ADC1_SQ0_INT_EN
569 #define ADC1_SQ0_INT_EN 0
571 #ifndef ADC1_SQ1_INT_EN
572 #define ADC1_SQ1_INT_EN 0
574 #ifndef ADC1_SQ2_INT_EN
575 #define ADC1_SQ2_INT_EN 0
577 #ifndef ADC1_SQ3_INT_EN
578 #define ADC1_SQ3_INT_EN 0
580 #ifndef ADC1_LOTH0_INT_EN
581 #define ADC1_LOTH0_INT_EN 0
583 #ifndef ADC1_LOTH1_INT_EN
584 #define ADC1_LOTH1_INT_EN 0
586 #ifndef ADC1_LOTH2_INT_EN
587 #define ADC1_LOTH2_INT_EN 0
589 #ifndef ADC1_LOTH3_INT_EN
590 #define ADC1_LOTH3_INT_EN 0
592 #ifndef ADC1_UPTH0_INT_EN
593 #define ADC1_UPTH0_INT_EN 0
595 #ifndef ADC1_UPTH1_INT_EN
596 #define ADC1_UPTH1_INT_EN 0
598 #ifndef ADC1_UPTH2_INT_EN
599 #define ADC1_UPTH2_INT_EN 0
601 #ifndef ADC1_UPTH3_INT_EN
602 #define ADC1_UPTH3_INT_EN 0
604 #ifndef ADC1_COLL0_INT_EN
605 #define ADC1_COLL0_INT_EN 0
607 #ifndef ADC1_COLL1_INT_EN
608 #define ADC1_COLL1_INT_EN 0
610 #ifndef ADC1_COLL2_INT_EN
611 #define ADC1_COLL2_INT_EN 0
613 #ifndef ADC1_COLL3_INT_EN
614 #define ADC1_COLL3_INT_EN 0
616 #ifndef ADC1_WFR0_INT_EN
617 #define ADC1_WFR0_INT_EN 0
619 #ifndef ADC1_WFR1_INT_EN
620 #define ADC1_WFR1_INT_EN 0
622 #ifndef ADC1_WFR2_INT_EN
623 #define ADC1_WFR2_INT_EN 0
625 #ifndef ADC1_WFR3_INT_EN
626 #define ADC1_WFR3_INT_EN 0
628 #ifndef BDRV_PH1_ZC_RISE_INT_EN
629 #define BDRV_PH1_ZC_RISE_INT_EN 0
631 #ifndef BDRV_PH1_ZC_FALL_INT_EN
632 #define BDRV_PH1_ZC_FALL_INT_EN 0
634 #ifndef BDRV_PH2_ZC_RISE_INT_EN
635 #define BDRV_PH2_ZC_RISE_INT_EN 0
637 #ifndef BDRV_PH2_ZC_FALL_INT_EN
638 #define BDRV_PH2_ZC_FALL_INT_EN 0
640 #ifndef BDRV_PH3_ZC_RISE_INT_EN
641 #define BDRV_PH3_ZC_RISE_INT_EN 0
643 #ifndef BDRV_PH3_ZC_FALL_INT_EN
644 #define BDRV_PH3_ZC_FALL_INT_EN 0
646 #ifndef SDADC_RES0_INT_EN
647 #define SDADC_RES0_INT_EN 0
649 #ifndef SDADC_CMP0_UP_INT_EN
650 #define SDADC_CMP0_UP_INT_EN 0
652 #ifndef SDADC_CMP0_LO_INT_EN
653 #define SDADC_CMP0_LO_INT_EN 0
655 #ifndef SDADC_RES1_INT_EN
656 #define SDADC_RES1_INT_EN 0
658 #ifndef SDADC_CMP1_UP_INT_EN
659 #define SDADC_CMP1_UP_INT_EN 0
661 #ifndef SDADC_CMP1_LO_INT_EN
662 #define SDADC_CMP1_LO_INT_EN 0
664 #ifndef SCU_EXTINT0_RISING_INT_EN
665 #define SCU_EXTINT0_RISING_INT_EN 0
667 #ifndef SCU_EXTINT0_FALLING_INT_EN
668 #define SCU_EXTINT0_FALLING_INT_EN 0
670 #ifndef SCU_EXTINT1_RISING_INT_EN
671 #define SCU_EXTINT1_RISING_INT_EN 0
673 #ifndef SCU_EXTINT1_FALLING_INT_EN
674 #define SCU_EXTINT1_FALLING_INT_EN 0
676 #ifndef SCU_EXTINT2_RISING_INT_EN
677 #define SCU_EXTINT2_RISING_INT_EN 0
679 #ifndef SCU_EXTINT2_FALLING_INT_EN
680 #define SCU_EXTINT2_FALLING_INT_EN 0
682 #ifndef SCU_EXTINT3_RISING_INT_EN
683 #define SCU_EXTINT3_RISING_INT_EN 0
685 #ifndef SCU_EXTINT3_FALLING_INT_EN
686 #define SCU_EXTINT3_FALLING_INT_EN 0
688 #ifndef UART0_TI_INT_EN
689 #define UART0_TI_INT_EN 0
691 #ifndef UART0_RI_INT_EN
692 #define UART0_RI_INT_EN 0
694 #ifndef UART0_EOS_INT_EN
695 #define UART0_EOS_INT_EN 0
697 #ifndef UART0_SYNCERR_INT_EN
698 #define UART0_SYNCERR_INT_EN 0
700 #ifndef UART1_TI_INT_EN
701 #define UART1_TI_INT_EN 0
703 #ifndef UART1_RI_INT_EN
704 #define UART1_RI_INT_EN 0
706 #ifndef UART1_EOS_INT_EN
707 #define UART1_EOS_INT_EN 0
709 #ifndef UART1_SYNCERR_INT_EN
710 #define UART1_SYNCERR_INT_EN 0
712 #ifndef SSC0_TI_INT_EN
713 #define SSC0_TI_INT_EN 0
715 #ifndef SSC0_RI_INT_EN
716 #define SSC0_RI_INT_EN 0
718 #ifndef SSC0_ERR_INT_EN
719 #define SSC0_ERR_INT_EN 0
721 #ifndef SSC0_ERR_INT_EN
722 #define SSC0_ERR_INT_EN 0
724 #ifndef SSC0_ERR_INT_EN
725 #define SSC0_ERR_INT_EN 0
727 #ifndef SSC0_ERR_INT_EN
728 #define SSC0_ERR_INT_EN 0
730 #ifndef SSC1_TI_INT_EN
731 #define SSC1_TI_INT_EN 0
733 #ifndef SSC1_RI_INT_EN
734 #define SSC1_RI_INT_EN 0
736 #ifndef SSC1_ERR_INT_EN
737 #define SSC1_ERR_INT_EN 0
739 #ifndef SSC1_ERR_INT_EN
740 #define SSC1_ERR_INT_EN 0
742 #ifndef SSC1_ERR_INT_EN
743 #define SSC1_ERR_INT_EN 0
745 #ifndef SSC1_ERR_INT_EN
746 #define SSC1_ERR_INT_EN 0
748 #ifndef DMA_CH0_INT_EN
749 #define DMA_CH0_INT_EN 0
751 #ifndef DMA_CH1_INT_EN
752 #define DMA_CH1_INT_EN 0
754 #ifndef DMA_CH2_INT_EN
755 #define DMA_CH2_INT_EN 0
757 #ifndef DMA_CH3_INT_EN
758 #define DMA_CH3_INT_EN 0
760 #ifndef DMA_CH4_INT_EN
761 #define DMA_CH4_INT_EN 0
763 #ifndef DMA_CH5_INT_EN
764 #define DMA_CH5_INT_EN 0
766 #ifndef DMA_CH6_INT_EN
767 #define DMA_CH6_INT_EN 0
769 #ifndef DMA_CH7_INT_EN
770 #define DMA_CH7_INT_EN 0
772 #ifndef DMA_ERROR_INT_EN
773 #define DMA_ERROR_INT_EN 0
775 #ifndef T20_EXF2_INT_EN
776 #define T20_EXF2_INT_EN 0
778 #ifndef T20_TF2_INT_EN
779 #define T20_TF2_INT_EN 0
781 #ifndef T21_EXF2_INT_EN
782 #define T21_EXF2_INT_EN 0
784 #ifndef T21_TF2_INT_EN
785 #define T21_TF2_INT_EN 0
797 #if (NVIC_IRQ0_HANDLER_INT_CHECK == 1)
798 extern uint8 u8_interrupt_cnt_irq0;
800 #if (NVIC_IRQ1_HANDLER_INT_CHECK == 1)
801 extern uint8 u8_interrupt_cnt_irq1;
803 #if (NVIC_IRQ2_HANDLER_INT_CHECK == 1)
804 extern uint8 u8_interrupt_cnt_irq2;
806 #if (NVIC_IRQ3_HANDLER_INT_CHECK == 1)
807 extern uint8 u8_interrupt_cnt_irq3;
809 #if (NVIC_IRQ4_HANDLER_INT_CHECK == 1)
810 extern uint8 u8_interrupt_cnt_irq4;
812 #if (NVIC_IRQ5_HANDLER_INT_CHECK == 1)
813 extern uint8 u8_interrupt_cnt_irq5;
815 #if (NVIC_IRQ6_HANDLER_INT_CHECK == 1)
816 extern uint8 u8_interrupt_cnt_irq6;
818 #if (NVIC_IRQ7_HANDLER_INT_CHECK == 1)
819 extern uint8 u8_interrupt_cnt_irq7;
821 #if (NVIC_IRQ8_HANDLER_INT_CHECK == 1)
822 extern uint8 u8_interrupt_cnt_irq8;
824 #if (NVIC_IRQ10_HANDLER_INT_CHECK == 1)
825 extern uint8 u8_interrupt_cnt_irq10;
827 #if (NVIC_IRQ11_HANDLER_INT_CHECK == 1)
828 extern uint8 u8_interrupt_cnt_irq11;
830 #if (NVIC_IRQ12_HANDLER_INT_CHECK == 1)
831 extern uint8 u8_interrupt_cnt_irq12;
833 #if (NVIC_IRQ13_HANDLER_INT_CHECK == 1)
834 extern uint8 u8_interrupt_cnt_irq13;
836 #if (NVIC_IRQ14_HANDLER_INT_CHECK == 1)
837 extern uint8 u8_interrupt_cnt_irq14;
839 #if (NVIC_IRQ15_HANDLER_INT_CHECK == 1)
840 extern uint8 u8_interrupt_cnt_irq15;
842 #if (NVIC_IRQ16_HANDLER_INT_CHECK == 1)
843 extern uint8 u8_interrupt_cnt_irq16;
845 #if (NVIC_IRQ17_HANDLER_INT_CHECK == 1)
846 extern uint8 u8_interrupt_cnt_irq17;
848 #if (NVIC_IRQ18_HANDLER_INT_CHECK == 1)
849 extern uint8 u8_interrupt_cnt_irq18;
851 #if (NVIC_IRQ19_HANDLER_INT_CHECK == 1)
852 extern uint8 u8_interrupt_cnt_irq19;
854 #if (NVIC_IRQ20_HANDLER_INT_CHECK == 1)
855 extern uint8 u8_interrupt_cnt_irq20;
857 #if (NVIC_IRQ21_HANDLER_INT_CHECK == 1)
858 extern uint8 u8_interrupt_cnt_irq21;
860 #if (NVIC_IRQ22_HANDLER_INT_CHECK == 1)
861 extern uint8 u8_interrupt_cnt_irq22;
863 #if (NVIC_IRQ23_HANDLER_INT_CHECK == 1)
864 extern uint8 u8_interrupt_cnt_irq23;
866 #if (NVIC_IRQ24_HANDLER_INT_CHECK == 1)
867 extern uint8 u8_interrupt_cnt_irq24;
869 #if (NVIC_IRQ25_HANDLER_INT_CHECK == 1)
870 extern uint8 u8_interrupt_cnt_irq25;
872 #if (NVIC_IRQ26_HANDLER_INT_CHECK == 1)
873 extern uint8 u8_interrupt_cnt_irq26;
875 #if (NVIC_IRQ27_HANDLER_INT_CHECK == 1)
876 extern uint8 u8_interrupt_cnt_irq27;
878 #if (NVIC_IRQ28_HANDLER_INT_CHECK == 1)
879 extern uint8 u8_interrupt_cnt_irq28;
881 #if (NVIC_IRQ29_HANDLER_INT_CHECK == 1)
882 extern uint8 u8_interrupt_cnt_irq29;
884 #if (NVIC_IRQ30_HANDLER_INT_CHECK == 1)
885 extern uint8 u8_interrupt_cnt_irq30;
887 #if (NVIC_IRQ9_HANDLER_INT_CHECK == 1)
888 extern uint8 u8_interrupt_cnt_irq9;
890 #if (NVIC_IRQ31_HANDLER_INT_CHECK == 1)
891 extern uint8 u8_interrupt_cnt_irq31;
Interrupt Service Routines low level access library.
void SCU_EXTINT1_RISING_CALLBACK(void)
void PMU_VDDEXT_OT_CALLBACK(void)
void MON_MON3_F_CALLBACK(void)
void CCU7_WRONG_HALL_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXPND_CALLBACK(void)
void ADC1_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG3_TXPND_CALLBACK(void)
void CPU_PENDSV_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXOVF_CALLBACK(void)
void NVIC_IRQ28_Handler(void)
Definition: startup_tle989x.c:274
void CPU_USAGEFAULT_CALLBACK(void)
void BDRV_LS2_OC_CALLBACK(void)
void DMA_CH4_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXPND_CALLBACK(void)
void BDRV_HB3_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXPND_CALLBACK(void)
void ADC1_UPTH2_CALLBACK(void)
void NVIC_IRQ3_Handler(void)
Definition: startup_tle989x.c:249
void CANNODE_NODE0_BOFF_CALLBACK(void)
void CCU7_T12_PM_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXOVF_CALLBACK(void)
void ADC1_WFR0_CALLBACK(void)
void NVIC_IRQ26_Handler(void)
Definition: startup_tle989x.c:272
void CANMSGOBJ0_MSG3_TXOVF_CALLBACK(void)
void MEMCTRL_NMICON_NMIDSEN_CALLBACK(void)
void DMA_CH6_CALLBACK(void)
void ADC1_WFR2_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXPND_CALLBACK(void)
void SSC1_BEI_CALLBACK(void)
void NVIC_IRQ21_Handler(void)
Definition: startup_tle989x.c:267
void CANMSGOBJ0_MSG4_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXOVF_CALLBACK(void)
void ADC1_CH0_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXPND_CALLBACK(void)
void ADC1_LOTH1_CALLBACK(void)
void ADC2_CH1_CALLBACK(void)
void T21_TF2_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP1EN_CALLBACK(void)
void CANNODE_NODE0_RXOK_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXPND_CALLBACK(void)
void SSC0_REI_CALLBACK(void)
void BDRV_LS2_DS_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXOVF_CALLBACK(void)
void SDADC_CMP0_UP_CALLBACK(void)
void CSACSC_OC_CALLBACK(void)
void SCU_EXTINT1_FALLING_CALLBACK(void)
void SCU_NMICON_NMIXTALEN_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXOVF_CALLBACK(void)
void NVIC_IRQ10_Handler(void)
Definition: startup_tle989x.c:256
void CANMSGOBJ0_MSG28_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXPND_CALLBACK(void)
void UsageFault_Handler(void)
UsageFault ISR.
Definition: startup_tle989x.c:234
void T21_EXF2_CALLBACK(void)
void ADC1_COLL0_CALLBACK(void)
void CCU7_C71B_CM_R_CALLBACK(void)
void PMU_VDDP_OV_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG7_RXPND_CALLBACK(void)
void NVIC_IRQ20_Handler(void)
Definition: startup_tle989x.c:266
void CANMSGOBJ0_MSG21_TXOVF_CALLBACK(void)
void UART0_RI_CALLBACK(void)
void BDRV_PH1_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXPND_CALLBACK(void)
void HardFault_Handler(void)
HardFault ISR.
Definition: startup_tle989x.c:231
void MON_MON2_F_CALLBACK(void)
void ADC1_COLL1_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXOVF_CALLBACK(void)
void SDADC_RES1_CALLBACK(void)
void SSC0_PEI_CALLBACK(void)
void CCU7_CC71A_CM_F_CALLBACK(void)
void CCU7_T12_OM_CALLBACK(void)
void BDRV_PH2_ZC_FALL_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXOVF_CALLBACK(void)
void UART0_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXPND_CALLBACK(void)
void MemManage_Handler(void)
MemManage ISR.
Definition: startup_tle989x.c:232
void SCU_EXTINT3_FALLING_CALLBACK(void)
void ADC1_UPTH1_CALLBACK(void)
void NVIC_IRQ17_Handler(void)
Definition: startup_tle989x.c:263
void NVIC_IRQ1_Handler(void)
Definition: startup_tle989x.c:247
void ADC2_SQ1_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXOVF_CALLBACK(void)
void ADC2_UPTH4_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXPND_CALLBACK(void)
void MEMCTRL_NMICON_NMIPSEN_CALLBACK(void)
void PMU_VDDC_UVWARN_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXPND_CALLBACK(void)
void MON_MON2_R_CALLBACK(void)
void NVIC_IRQ29_Handler(void)
Definition: startup_tle989x.c:275
void CANMSGOBJ0_MSG19_RXPND_CALLBACK(void)
void CCU7_CC70A_CM_F_CALLBACK(void)
void MON_MON3_R_CALLBACK(void)
void UART1_SYNCERR_CALLBACK(void)
void SCU_NMICON_NMIPLL1EN_CALLBACK(void)
void CANMSGOBJ0_MSG16_RXPND_CALLBACK(void)
void MEMCTRL_NVM1_OP_COMPLETE_CALLBACK(void)
void BDRV_HS2_DS_CALLBACK(void)
void CCU7_T15_CM_CALLBACK(void)
void MEMCTRL_NMICON_NMICDEN_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXOVF_CALLBACK(void)
void ADC1_CH7_CALLBACK(void)
void ADC1_CH17_CALLBACK(void)
void BDRV_HS2_OC_CALLBACK(void)
void SDADC_CMP1_UP_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXOVF_CALLBACK(void)
void CCU7_T14_PM_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXPND_CALLBACK(void)
void GPT12_GPT1T4_CALLBACK(void)
void ADC2_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXOVF_CALLBACK(void)
void BDRV_SEQ_ERR_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXOVF_CALLBACK(void)
void CSACSC_PARAM_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXPND_CALLBACK(void)
void CANTRX_BUS_TO_CALLBACK(void)
void CCU7_T16_CM_CALLBACK(void)
void ADC1_CH5_CALLBACK(void)
void NVIC_IRQ12_Handler(void)
Definition: startup_tle989x.c:258
void UART0_SYNCERR_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXOVF_CALLBACK(void)
void ADC1_CH16_CALLBACK(void)
void CANMSGOBJ0_MSG4_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXOVF_CALLBACK(void)
void BDRV_HS3_OC_CALLBACK(void)
void ADC1_CH19_CALLBACK(void)
void CCU7_MCM_STR_CALLBACK(void)
void UART1_TI_CALLBACK(void)
void NVIC_IRQ7_Handler(void)
Definition: startup_tle989x.c:253
void SDADC_CMP0_LO_CALLBACK(void)
void SCU_EXTINT0_FALLING_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXOVF_CALLBACK(void)
void ADC2_CH0_CALLBACK(void)
void SDADC_CMP1_LO_CALLBACK(void)
void ADC1_LOTH0_CALLBACK(void)
void ADC2_CH6_CALLBACK(void)
void UART1_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXOVF_CALLBACK(void)
void PMU_VDDC_OV_CALLBACK(void)
void PendSV_Handler(void)
PendSV ISR.
Definition: startup_tle989x.c:241
void NVIC_IRQ27_Handler(void)
Definition: startup_tle989x.c:273
void CCU7_C70B_CM_F_CALLBACK(void)
void SCU_NMICON_NMIPLL0EN_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXPND_CALLBACK(void)
void CCU7_T15_PM_CALLBACK(void)
void GPT12_GPT1T2_CALLBACK(void)
void BDRV_HS3_DS_CALLBACK(void)
void SCU_EXTINT2_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXOVF_CALLBACK(void)
void NVIC_IRQ31_Handler(void)
Definition: startup_tle989x.c:278
void NMI_Handler(void)
NMI ISR.
Definition: startup_tle989x.c:230
void DMA_CH2_CALLBACK(void)
void ADC1_CH10_CALLBACK(void)
void ADC1_CH1_CALLBACK(void)
void ADC2_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXPND_CALLBACK(void)
void BDRV_LS3_DS_CALLBACK(void)
void NVIC_IRQ9_Handler(void)
Definition: startup_tle989x.c:255
void CANMSGOBJ0_MSG19_TXPND_CALLBACK(void)
void MON_MON1_R_CALLBACK(void)
void NVIC_IRQ8_Handler(void)
Definition: startup_tle989x.c:254
void NVIC_IRQ6_Handler(void)
void CANMSGOBJ0_MSG27_RXOVF_CALLBACK(void)
void BDRV_LS1_DS_CALLBACK(void)
void BDRV_LS3_OC_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXOVF_CALLBACK(void)
void ADC2_CH5_CALLBACK(void)
void SSC0_RI_CALLBACK(void)
void CCU7_LI_CALLBACK(void)
void MEMCTRL_NMICON_NMISTOFEN_CALLBACK(void)
void DMA_CH0_CALLBACK(void)
void ADC2_LOTH7_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXPND_CALLBACK(void)
void CPU_MEMMANAGE_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXOVF_CALLBACK(void)
void GPT12_GPT2CAPREL_CALLBACK(void)
void BDRV_PH3_ZC_FALL_CALLBACK(void)
void CPU_HARDFAULT_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXPND_CALLBACK(void)
void SDADC_RES0_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM0EN_CALLBACK(void)
void ADC1_UPTH0_CALLBACK(void)
void CANMSGOBJ0_MSG21_TXPND_CALLBACK(void)
void ADC1_WFR1_CALLBACK(void)
void NVIC_IRQ13_Handler(void)
Definition: startup_tle989x.c:259
void CANMSGOBJ0_MSG16_RXOVF_CALLBACK(void)
void NVIC_IRQ16_Handler(void)
Definition: startup_tle989x.c:262
void ADC2_LOTH0_CALLBACK(void)
void SCU_EXTINT3_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXPND_CALLBACK(void)
void SSC1_PEI_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM1EN_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXOVF_CALLBACK(void)
void CCU7_T13_PM_CALLBACK(void)
void ADC1_CH13_CALLBACK(void)
void UART0_TI_CALLBACK(void)
void PMU_VDDEXT_UV_CALLBACK(void)
void BusFault_Handler(void)
BusFault ISR.
Definition: startup_tle989x.c:233
void CANMSGOBJ0_MSG28_RXPND_CALLBACK(void)
void ADC2_CH11_CALLBACK(void)
void ADC2_CH3_CALLBACK(void)
void ADC2_CH4_CALLBACK(void)
void ADC1_COLL2_CALLBACK(void)
void ADC1_UPTH3_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXPND_CALLBACK(void)
void NVIC_IRQ0_Handler(void)
Definition: startup_tle989x.c:246
void BDRV_HB1_ASEQ_CALLBACK(void)
void ADC2_UPTH6_CALLBACK(void)
void ADC2_UPTH5_CALLBACK(void)
void BDRV_PH1_ZC_FALL_CALLBACK(void)
void MEMCTRL_NVM0_OP_COMPLETE_CALLBACK(void)
void GPT12_GPT2T5_CALLBACK(void)
void ADC1_CH11_CALLBACK(void)
void ADC1_LOTH2_CALLBACK(void)
void ADC2_UPTH1_CALLBACK(void)
void MEMCTRL_NMICON_NMIWDTEN_CALLBACK(void)
void CCU7_T13_CM_CALLBACK(void)
void ADC1_CH4_CALLBACK(void)
void ADC1_LOTH3_CALLBACK(void)
void PMU_VDDP_UVWARN_CALLBACK(void)
void CCU7_T14_CM_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXOVF_CALLBACK(void)
void CCU7_T16_PM_CALLBACK(void)
void CANTRX_OT_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXPND_CALLBACK(void)
void CCU7_CC72A_CM_R_CALLBACK(void)
void BDRV_HB2_ACTDRV_CALLBACK(void)
void ADC2_CH10_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXPND_CALLBACK(void)
void NVIC_IRQ5_Handler(void)
Definition: startup_tle989x.c:251
void ADC1_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_RXPND_CALLBACK(void)
void ADC1_CH18_CALLBACK(void)
void SSC1_REI_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXOVF_CALLBACK(void)
void ADC1_CH12_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXOVF_CALLBACK(void)
void SCU_EXTINT0_RISING_CALLBACK(void)
void SSC1_TEI_CALLBACK(void)
void NVIC_IRQ24_Handler(void)
Definition: startup_tle989x.c:270
void SSC0_BEI_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXPND_CALLBACK(void)
void NVIC_IRQ18_Handler(void)
Definition: startup_tle989x.c:264
void CCU7_CC72A_CM_F_CALLBACK(void)
void T20_EXF2_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG19_TXOVF_CALLBACK(void)
void NVIC_IRQ25_Handler(void)
Definition: startup_tle989x.c:271
void NVIC_IRQ22_Handler(void)
Definition: startup_tle989x.c:268
void CANMSGOBJ0_MSG7_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXPND_CALLBACK(void)
void ADC2_UPTH2_CALLBACK(void)
void ADC2_LOTH6_CALLBACK(void)
void ADC2_UPTH3_CALLBACK(void)
void DMA_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXPND_CALLBACK(void)
void DMA_CH5_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXPND_CALLBACK(void)
void SSC1_RI_CALLBACK(void)
void SysTick_Handler(void)
SysTick ISR.
Definition: startup_tle989x.c:243
void ADC2_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXPND_CALLBACK(void)
void UART1_RI_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXPND_CALLBACK(void)
void ADC2_LOTH3_CALLBACK(void)
void DMA_CH1_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXPND_CALLBACK(void)
void CCU7_C70B_CM_R_CALLBACK(void)
void CANNODE_NODE0_LEC_CALLBACK(void)
void CANMSGOBJ0_MSG19_RXOVF_CALLBACK(void)
void CPU_SYSTICK_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXPND_CALLBACK(void)
void ADC2_CH13_CALLBACK(void)
void CANNODE_NODE0_EWRN_CALLBACK(void)
void CANNODE_NODE0_LOE_CALLBACK(void)
void NVIC_IRQ11_Handler(void)
Definition: startup_tle989x.c:257
void CANMSGOBJ0_MSG6_RXOVF_CALLBACK(void)
volatile uint32 u32_globTimestamp_ms
Definition: isr_exceptions.c:25
void ADC1_SQ2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXOVF_CALLBACK(void)
void ADC2_LOTH1_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXOVF_CALLBACK(void)
void NVIC_IRQ23_Handler(void)
Definition: startup_tle989x.c:269
void ADC1_CH15_CALLBACK(void)
void NVIC_IRQ19_Handler(void)
Definition: startup_tle989x.c:265
void ADC2_SQ3_CALLBACK(void)
void ADC1_CH8_CALLBACK(void)
void ADC2_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXPND_CALLBACK(void)
void SCU_EXTINT2_FALLING_CALLBACK(void)
void CCU7_CC70A_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXOVF_CALLBACK(void)
void NVIC_IRQ30_Handler(void)
Definition: startup_tle989x.c:276
void DMA_ERROR_CALLBACK(void)
void GPT12_GPT2T6_CALLBACK(void)
void ADC2_CH9_CALLBACK(void)
void MON_MON1_F_CALLBACK(void)
void CANMSGOBJ0_MSG6_RXPND_CALLBACK(void)
void CANNODE_NODE0_CFCOV_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXPND_CALLBACK(void)
void ADC2_CH2_CALLBACK(void)
void CCU7_C72B_CM_F_CALLBACK(void)
void SSC0_TEI_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXOVF_CALLBACK(void)
void CCU7_TRAP_CALLBACK(void)
void ADC2_SQ2_CALLBACK(void)
void SSC0_TI_CALLBACK(void)
void ADC2_CH12_CALLBACK(void)
void CCU7_CC71A_CM_R_CALLBACK(void)
void ADC1_CH3_CALLBACK(void)
void BDRV_PH3_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG8_RXPND_CALLBACK(void)
void CCU7_C71B_CM_F_CALLBACK(void)
void ARVG_VAREF_OC_CALLBACK(void)
void ADC1_COLL3_CALLBACK(void)
void ADC2_LOTH5_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXPND_CALLBACK(void)
void CANTRX_TXD_TO_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXPND_CALLBACK(void)
void NVIC_IRQ15_Handler(void)
Definition: startup_tle989x.c:261
void NVIC_IRQ2_Handler(void)
Definition: startup_tle989x.c:248
void BDRV_LS1_OC_CALLBACK(void)
void BDRV_HB1_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXOVF_CALLBACK(void)
void BDRV_HB2_ASEQ_CALLBACK(void)
void ADC1_SQ1_CALLBACK(void)
void CPU_BUSFAULT_CALLBACK(void)
void SSC1_TI_CALLBACK(void)
void DMA_CH3_CALLBACK(void)
void ADC2_CH8_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXPND_CALLBACK(void)
void T20_TF2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXPND_CALLBACK(void)
void BDRV_HS1_OC_CALLBACK(void)
void GPT12_GPT1T3_CALLBACK(void)
void BDRV_HB3_ASEQ_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXOVF_CALLBACK(void)
void CCU7_CORRECT_HALL_CALLBACK(void)
void BDRV_PH2_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXPND_CALLBACK(void)
void NVIC_IRQ14_Handler(void)
Definition: startup_tle989x.c:260
void CANMSGOBJ0_MSG4_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXPND_CALLBACK(void)
void NVIC_IRQ4_Handler(void)
Definition: startup_tle989x.c:250
void CANMSGOBJ0_MSG8_RXOVF_CALLBACK(void)
void CANNODE_NODE0_TXOK_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP0EN_CALLBACK(void)
void ADC2_LOTH4_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXOVF_CALLBACK(void)
void ADC1_WFR3_CALLBACK(void)
void ADC2_UPTH0_CALLBACK(void)
void ADC2_UPTH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXPND_CALLBACK(void)
void ADC1_CH6_CALLBACK(void)
void ADC1_CH9_CALLBACK(void)
void CANNODE_NODE0_LLE_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXOVF_CALLBACK(void)
void BDRV_VCP_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXPND_CALLBACK(void)
void BDRV_HS1_DS_CALLBACK(void)
void CCU7_C72B_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXPND_CALLBACK(void)
INLINE uint32 INT_getGlobTimestamp(void)
Get the global timestamp value.
Definition: isr.h:1308
void ADC1_CH2_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG4_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXOVF_CALLBACK(void)
void CANTRX_BUS_ACT_CALLBACK(void)
void ADC1_SQ3_CALLBACK(void)
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:151
uint8_t uint8
8 bit unsigned value
Definition: types.h:204
uint32_t uint32
32 bit unsigned value
Definition: types.h:206