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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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CAN Node (CANNODE)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DISR: 1 | |
__IM uint32_t DISS: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t EDIS: 1 | |
uint32_t __pad1__: 28 | |
} bit | |
} | CLC |
__IM uint32_t | RESERVED |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MOD_REV: 8 | |
__IM uint32_t MOD_TYPE: 8 | |
__IM uint32_t MOD_NUMBER: 16 | |
} bit | |
} | ID |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t STEP: 10 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t DM: 2 | |
uint32_t __pad1__: 16 | |
} bit | |
} | FDR |
__IM uint32_t | RESERVED1 [60] |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST2 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST3 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST4 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST5 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST6 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BEGIN: 8 | |
__IM uint32_t END: 8 | |
__IM uint32_t SIZE: 8 | |
__IM uint32_t EMPTY: 1 | |
uint32_t __pad0__: 7 | |
} bit | |
} | LIST7 |
__IM uint32_t | RESERVED2 [8] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PND: 32 | |
} bit | |
} | MSPND0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PND: 32 | |
} bit | |
} | MSPND1 |
__IM uint32_t | RESERVED3 [14] |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t INDEX: 6 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MSID0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t INDEX: 6 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MSID1 |
__IM uint32_t | RESERVED4 [14] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IM: 32 | |
} bit | |
} | MSIMASK |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PANCMD: 8 | |
__IM uint32_t BUSY: 1 | |
__IM uint32_t RBUSY: 1 | |
uint32_t __pad0__: 6 | |
__IOM uint32_t PANAR1: 8 | |
__IOM uint32_t PANAR2: 8 | |
} bit | |
} | PANCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CLKSEL: 4 | |
uint32_t __pad0__: 8 | |
__IOM uint32_t MPSEL: 4 | |
uint32_t __pad1__: 16 | |
} bit | |
} | MCR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t IT: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | MITR |
__IM uint32_t | RESERVED5 [12] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INIT: 1 | |
__IOM uint32_t TRIE: 1 | |
__IOM uint32_t LECIE: 1 | |
__IOM uint32_t ALIE: 1 | |
__IOM uint32_t CANDIS: 1 | |
__IOM uint32_t TXDIS: 1 | |
__IOM uint32_t CCE: 1 | |
__IOM uint32_t CALM: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t FDEN: 1 | |
__IOM uint32_t PED: 1 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t NISO: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | CAN_NCR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LEC: 3 | |
__IOM uint32_t TXOK: 1 | |
__IOM uint32_t RXOK: 1 | |
__IOM uint32_t ALERT: 1 | |
__IM uint32_t EWRN: 1 | |
__IM uint32_t BOFF: 1 | |
__IOM uint32_t LLE: 1 | |
__IOM uint32_t LOE: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t RESI: 1 | |
__IOM uint32_t FLEC: 3 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CAN_NSR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ALINP: 4 | |
__IOM uint32_t LECINP: 4 | |
__IOM uint32_t TRINP: 4 | |
__IOM uint32_t CFCINP: 4 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CAN_NIPR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXSEL: 3 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t LBM: 1 | |
uint32_t __pad1__: 23 | |
} bit | |
} | CAN_NPCR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BRP: 6 | |
__IOM uint32_t SJW: 2 | |
__IOM uint32_t TSEG1: 4 | |
__IOM uint32_t TSEG2: 3 | |
__IOM uint32_t DIV8: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CAN_NBTR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t REC: 8 | |
__IOM uint32_t TEC: 8 | |
__IOM uint32_t EWRNLVL: 8 | |
__IM uint32_t LETD: 1 | |
__IM uint32_t LEINC: 1 | |
uint32_t __pad0__: 6 | |
} bit | |
} | CAN_NECNT0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CFC: 16 | |
__IOM uint32_t CFSEL: 3 | |
__IOM uint32_t CFMOD: 2 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CFCIE: 1 | |
__IOM uint32_t CFCOV: 1 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CAN_NFCR0 |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
__IOM uint32_t ALERT |
[5..5] Alert Warning
__IOM uint32_t ALIE |
[3..3] Alert Interrupt Enable
__IOM uint32_t ALINP |
[3..0] Alert Interrupt Node Pointer
__IM uint32_t BEGIN |
[7..0] List Begin
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IM uint32_t BOFF |
[7..7] Bus-off Status
__IOM uint32_t BRP |
[5..0] Baud Rate Prescaler
__IM uint32_t BUSY |
[8..8] Panel Busy Flag
__IOM uint32_t CALM |
[7..7] CAN Analyzer Mode
union { ... } CAN_NBTR0 |
union { ... } CAN_NCR0 |
union { ... } CAN_NECNT0 |
union { ... } CAN_NFCR0 |
union { ... } CAN_NIPR0 |
union { ... } CAN_NPCR0 |
union { ... } CAN_NSR0 |
__IOM uint32_t CANDIS |
[4..4] CAN Disable
__IOM uint32_t CCE |
[6..6] Configuration Change Enable
__IOM uint32_t CFC |
[15..0] CAN Frame Counter - CFC
__IOM uint32_t CFCIE |
[22..22] CAN Frame Count Interrupt Enable - CFCIE
__IOM uint32_t CFCINP |
[15..12] Frame Counter Interrupt Node Pointer
__IOM uint32_t CFCOV |
[23..23] CAN Frame Counter Overflow Flag - CFCOV
__IOM uint32_t CFMOD |
[20..19] CAN Frame Counter Mode - CFMOD
__IOM uint32_t CFSEL |
[18..16] CAN Frame Count Selection - CFSEL
union { ... } CLC |
__IOM uint32_t CLKSEL |
[3..0] Baud Rate Logic Clock Select
__IOM uint32_t DISR |
[0..0] Module Disable Request Bit
__IM uint32_t DISS |
[1..1] Module Disable Status Bit
__IOM uint32_t DIV8 |
[15..15] Divide Prescaler Clock by 8
__IOM uint32_t DM |
[15..14] Divider Mode
__IOM uint32_t EDIS |
[3..3] Sleep Mode Enable Control
__IM uint32_t EMPTY |
[24..24] List Empty Indication
__IM uint32_t END |
[15..8] List End
__IM uint32_t EWRN |
[6..6] Error Warning Status
__IOM uint32_t EWRNLVL |
[23..16] Error Warning Level
__IOM uint32_t FDEN |
[9..9] CAN Flexible Data-Rate Enable
union { ... } FDR |
__IOM uint32_t FLEC |
[14..12] Fast Last Error Code
union { ... } ID |
__IOM uint32_t IM |
[31..0] Message Index Mask
__IM uint32_t INDEX |
[5..0] Message Pending Index
__IOM uint32_t INIT |
[0..0] Node Initialization
__OM uint32_t IT |
[7..0] Interrupt Trigger
__IOM uint32_t LBM |
[8..8] Loop-Back Mode
__IOM uint32_t LEC |
[2..0] Last Error Code
__IOM uint32_t LECIE |
[2..2] LEC Indicated Error Interrupt Enable
__IOM uint32_t LECINP |
[7..4] Last Error Code Interrupt Node Pointer
__IM uint32_t LEINC |
[25..25] Last Error Increment
__IM uint32_t LETD |
[24..24] Last Error Transfer Direction
union { ... } LIST0 |
union { ... } LIST1 |
union { ... } LIST2 |
union { ... } LIST3 |
union { ... } LIST4 |
union { ... } LIST5 |
union { ... } LIST6 |
union { ... } LIST7 |
__IOM uint32_t LLE |
[8..8] List Length Error
__IOM uint32_t LOE |
[9..9] List Object Error
union { ... } MCR |
union { ... } MITR |
__IM uint32_t MOD_NUMBER |
[31..16] Module Number Value
__IM uint32_t MOD_REV |
[7..0] Module Revision Number
__IM uint32_t MOD_TYPE |
[15..8] Module Type
__IOM uint32_t MPSEL |
[15..12] Message Pending Selector
union { ... } MSID0 |
union { ... } MSID1 |
union { ... } MSIMASK |
union { ... } MSPND0 |
union { ... } MSPND1 |
__IOM uint32_t NISO |
[15..15] Non ISO Operation
__IOM uint32_t PANAR1 |
[23..16] Panel Argument 1
__IOM uint32_t PANAR2 |
[31..24] Panel Argument 2
__IOM uint32_t PANCMD |
[7..0] Panel Command
union { ... } PANCTR |
__IOM uint32_t PED |
[10..10] Protocol Exeption Disable
__IOM uint32_t PND |
[31..0] Message Pending
__IM uint32_t RBUSY |
[9..9] Result Busy Flag
__IOM uint32_t REC |
[7..0] Receive Error Counter
__IOM uint32_t reg |
(@ 0x00000000) CAN Clock Control Register
(@ 0x0000000C) CAN Fractional Divider Register
(@ 0x00000140) Message Pending Register 0
(@ 0x00000144) Message Pending Register 1
(@ 0x000001C0) Message Index Mask Register
(@ 0x000001C4) Panel Control Register
(@ 0x000001C8) Module Control Register
(@ 0x000001CC) Module Interrupt Trigger Register
(@ 0x00000200) Node 0 Control Register
(@ 0x00000204) Node 0 Status Register
(@ 0x00000208) Node 0 Interrupt Pointer Register
(@ 0x0000020C) Node 0 Port Control Register
(@ 0x00000210) Node 0 Bit Timing Register
(@ 0x00000214) Node 0 Error Counter Register
(@ 0x00000218) Node 0 Frame Counter Register
__IM uint32_t reg |
(@ 0x00000008) Module Identification Register
(@ 0x00000100) List Register 0
(@ 0x00000104) List Register 1
(@ 0x00000108) List Register 2
(@ 0x0000010C) List Register 3
(@ 0x00000110) List Register 4
(@ 0x00000114) List Register 5
(@ 0x00000118) List Register 6
(@ 0x0000011C) List Register 7
(@ 0x00000180) Message Index Register 0
(@ 0x00000184) Message Index Register 1
__IM uint32_t RESERVED |
__IM uint32_t RESERVED1[60] |
__IM uint32_t RESERVED2[8] |
__IM uint32_t RESERVED3[14] |
__IM uint32_t RESERVED4[14] |
__IM uint32_t RESERVED5[12] |
__IOM uint32_t RESI |
[11..11] Received Error State Indicator Flag
__IOM uint32_t RXOK |
[4..4] Message Received Successfully
__IOM uint32_t RXSEL |
[2..0] Receive Select
__IM uint32_t SIZE |
[23..16] List Size
__IOM uint32_t SJW |
[7..6] (Re) Synchronization Jump Width
__IOM uint32_t STEP |
[9..0] Step Value
__IOM uint32_t TEC |
[15..8] Transmit Error Counter
__IOM uint32_t TRIE |
[1..1] Transfer Interrupt Enable
__IOM uint32_t TRINP |
[11..8] Transfer OK Interrupt Node Pointer
__IOM uint32_t TSEG1 |
[11..8] Time Segment Before Sample Point
__IOM uint32_t TSEG2 |
[14..12] Time Segment After Sample Point
__IOM uint32_t TXDIS |
[5..5] Transmit Disable
__IOM uint32_t TXOK |
[3..3] Message Transmitted Successfully