64 #include "dma_defines.h"
178 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
180 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
182 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
184 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
186 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
188 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
190 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
192 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
316 DMA->DMA_CFG.bit.MASTER_ENABLE = 1u;
323 SCU->DMACTRL.bit.DEMEN_CH0 = 1u;
330 SCU->DMACTRL.bit.DEMEN_CH0 = 0u;
337 SCU->DMACTRL.bit.DEMEN_CH1 = 1u;
344 SCU->DMACTRL.bit.DEMEN_CH1 = 0u;
351 SCU->DMACTRL.bit.DEMEN_CH2 = 1u;
358 SCU->DMACTRL.bit.DEMEN_CH2 = 0u;
365 SCU->DMACTRL.bit.DEMEN_CH3 = 1u;
372 SCU->DMACTRL.bit.DEMEN_CH3 = 0u;
379 SCU->DMACTRL.bit.DEMEN_CH4 = 1u;
386 SCU->DMACTRL.bit.DEMEN_CH4 = 0u;
393 SCU->DMACTRL.bit.DEMEN_CH5 = 1u;
400 SCU->DMACTRL.bit.DEMEN_CH5 = 0u;
407 SCU->DMACTRL.bit.DEMEN_CH6 = 1u;
414 SCU->DMACTRL.bit.DEMEN_CH6 = 0u;
421 SCU->DMACTRL.bit.DEMEN_CH7 = 1u;
428 SCU->DMACTRL.bit.DEMEN_CH7 = 0u;
435 SCU->DMAIEN.bit.DMACH0EN = 1u;
442 SCU->DMAIEN.bit.DMACH0EN = 0u;
449 SCU->DMAIEN.bit.DMACH1EN = 1u;
456 SCU->DMAIEN.bit.DMACH1EN = 0u;
463 SCU->DMAIEN.bit.DMACH2EN = 1u;
470 SCU->DMAIEN.bit.DMACH2EN = 0u;
477 SCU->DMAIEN.bit.DMACH3EN = 1u;
484 SCU->DMAIEN.bit.DMACH3EN = 0u;
491 SCU->DMAIEN.bit.DMACH4EN = 1u;
498 SCU->DMAIEN.bit.DMACH4EN = 0u;
505 SCU->DMAIEN.bit.DMACH5EN = 1u;
512 SCU->DMAIEN.bit.DMACH5EN = 0u;
519 SCU->DMAIEN.bit.DMACH6EN = 1u;
526 SCU->DMAIEN.bit.DMACH6EN = 0u;
533 SCU->DMAIEN.bit.DMACH7EN = 1u;
540 SCU->DMAIEN.bit.DMACH7EN = 0u;
547 SCU->DMAIEN.bit.DMATRERREN = 1u;
554 SCU->DMAIEN.bit.DMATRERREN = 0u;
563 return (
uint8)
SCU->DMAIS.bit.DMACH0;
572 return (
uint8)
SCU->DMAIS.bit.DMACH1;
581 return (
uint8)
SCU->DMAIS.bit.DMACH2;
590 return (
uint8)
SCU->DMAIS.bit.DMACH3;
599 return (
uint8)
SCU->DMAIS.bit.DMACH4;
608 return (
uint8)
SCU->DMAIS.bit.DMACH5;
617 return (
uint8)
SCU->DMAIS.bit.DMACH6;
626 return (
uint8)
SCU->DMAIS.bit.DMACH7;
633 SCU->DMAISC.bit.DMACH0CLR = 1u;
640 SCU->DMAISC.bit.DMACH1CLR = 1u;
647 SCU->DMAISC.bit.DMACH2CLR = 1u;
654 SCU->DMAISC.bit.DMACH3CLR = 1u;
661 SCU->DMAISC.bit.DMACH4CLR = 1u;
668 SCU->DMAISC.bit.DMACH5CLR = 1u;
675 SCU->DMAISC.bit.DMACH6CLR = 1u;
682 SCU->DMAISC.bit.DMACH7CLR = 1u;
INLINE void DMA_enCh3EndlessMode(void)
Enable DMA Channel 3 Endless Mode.
Definition: dma.h:363
INLINE uint8 DMA_getCh1IntSts(void)
Get DMA Channel 1 Interrupt Status.
Definition: dma.h:570
void DMA_setCh7IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 7 Interrupt Node Pointer.
void DMA_setCh2IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 2 Interrupt Node Pointer.
void DMA_setCh1IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 1 Interrupt Node Pointer.
INLINE uint8 DMA_getCh6IntSts(void)
Get DMA Channel 6 Interrupt Status.
Definition: dma.h:615
INLINE void DMA_enCh5Int(void)
Enable DMA Channel 5 Interrupt.
Definition: dma.h:503
INLINE void DMA_enCh2Int(void)
Enable DMA Channel 2 Interrupt.
Definition: dma.h:461
INLINE uint8 DMA_getCh2IntSts(void)
Get DMA Channel 2 Interrupt Status.
Definition: dma.h:579
enum DMA_incrementSize tDMA_incrementSize
INLINE void DMA_disErrInt(void)
Disable DMA Transfer Error Interrupt.
Definition: dma.h:552
INLINE void DMA_disCh3Int(void)
Disable DMA Channel 3 Interrupt.
Definition: dma.h:482
INLINE uint8 DMA_getCh3IntSts(void)
Get DMA Channel 3 Interrupt Status.
Definition: dma.h:588
INLINE void DMA_enCh4EndlessMode(void)
Enable DMA Channel 4 Endless Mode.
Definition: dma.h:377
enum DMA_transferSize tDMA_transferSize
INLINE void DMA_enCh4Int(void)
Enable DMA Channel 4 Interrupt.
Definition: dma.h:489
DMA_incrementSize
This enum lists the increment size options for the DMA.
Definition: dma.h:90
@ DMA_incrementSize_16bit
Definition: dma.h:92
@ DMA_incrementSize_32bit
Definition: dma.h:93
@ DMA_incrementSize_8bit
Definition: dma.h:91
enum DMA_incrementMode tDMA_incrementMode
INLINE void DMA_enCh6Int(void)
Enable DMA Channel 6 Interrupt.
Definition: dma.h:517
INLINE void DMA_clrCh1IntSts(void)
Clear DMA Channel 1 Interrupt Status.
Definition: dma.h:638
INLINE void DMA_disCh1EndlessMode(void)
Disable DMA Channel 1 Endless Mode.
Definition: dma.h:342
void DMA_setCh5IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 5 Interrupt Node Pointer.
INLINE void DMA_enCh1EndlessMode(void)
Enable DMA Channel 1 Endless Mode.
Definition: dma.h:335
void DMA_setMemSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Memory Scatter-Gather mode on a given task list.
Definition: dma.c:1191
void DMA_setErrIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel Bus Error Interrupt Node Pointer.
tDMA_entry * DMA_setTaskSctGth(tDMA_entry *s_entry, tDMA_cycleType e_cycleType, uint8 u8_Rpower, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a task to be used in the scatter-gather mode.
Definition: dma.c:1295
DMA_cycleType
This enum lists the cycle type options for the DMA.
Definition: dma.h:113
@ DMA_cycleType_PerSctGthPrim
Definition: dma.h:120
@ DMA_cycleType_Auto
Definition: dma.h:116
@ DMA_cycleType_Invalid
Definition: dma.h:114
@ DMA_cycleType_MemSctGthAlt
Definition: dma.h:119
@ DMA_cycleType_MemSctGthPrim
Definition: dma.h:118
@ DMA_cycleType_PingPong
Definition: dma.h:117
@ DMA_cycleType_PerSctGthAlt
Definition: dma.h:121
@ DMA_cycleType_Basic
Definition: dma.h:115
INLINE void DMA_disCh7EndlessMode(void)
Disable DMA Channel 7 Endless Mode.
Definition: dma.h:426
INLINE void DMA_disCh6EndlessMode(void)
Disable DMA Channel 6 Endless Mode.
Definition: dma.h:412
INLINE uint8 DMA_getCh0IntSts(void)
Get DMA Channel 0 Interrupt Status.
Definition: dma.h:561
INLINE void DMA_disCh5EndlessMode(void)
Disable DMA Channel 5 Endless Mode.
Definition: dma.h:398
void DMA_setCh3IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 3 Interrupt Node Pointer.
INLINE void DMA_disCh2Int(void)
Disable DMA Channel 2 Interrupt.
Definition: dma.h:468
INLINE void DMA_disCh2EndlessMode(void)
Disable DMA Channel 2 Endless Mode.
Definition: dma.h:356
DMA_incrementMode
This enum lists the increment mode options for the DMA.
Definition: dma.h:101
@ DMA_incrementMode_srcInc
Definition: dma.h:102
@ DMA_incrementMode_dstInc
Definition: dma.h:103
@ DMA_incrementMode_noInc
Definition: dma.h:105
@ DMA_incrementMode_srcDstInc
Definition: dma.h:104
INLINE void DMA_enCh2EndlessMode(void)
Enable DMA Channel 2 Endless Mode.
Definition: dma.h:349
INLINE void DMA_clrCh2IntSts(void)
Clear DMA Channel 2 Interrupt Status.
Definition: dma.h:645
void DMA_setPerSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
Definition: dma.c:1224
INLINE void DMA_enCh3Int(void)
Enable DMA Channel 3 Interrupt.
Definition: dma.h:475
INLINE void DMA_enCh0EndlessMode(void)
Enable DMA Channel 0 Endless Mode.
Definition: dma.h:321
void DMA_setCh6IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 6 Interrupt Node Pointer.
INLINE void DMA_enErrInt(void)
Enable DMA Transfer Error Interrupt.
Definition: dma.h:545
INLINE void DMA_enMaster(void)
Enable DMA Master.
Definition: dma.h:314
INLINE void DMA_disCh0EndlessMode(void)
Disable DMA Channel 0 Endless Mode.
Definition: dma.h:328
INLINE void DMA_clrCh0IntSts(void)
Clear DMA Channel 0 Interrupt Status.
Definition: dma.h:631
INLINE void DMA_enCh0Int(void)
Enable DMA Channel 0 Interrupt.
Definition: dma.h:433
INLINE void DMA_disCh4EndlessMode(void)
Disable DMA Channel 4 Endless Mode.
Definition: dma.h:384
INLINE void DMA_enCh7EndlessMode(void)
Enable DMA Channel 7 Endless Mode.
Definition: dma.h:419
INLINE void DMA_disCh5Int(void)
Disable DMA Channel 5 Interrupt.
Definition: dma.h:510
DMA_transferSize
This enum lists the transfer size options for the DMA.
Definition: dma.h:79
@ DMA_transferSize_8bit
Definition: dma.h:80
@ DMA_transferSize_32bit
Definition: dma.h:82
@ DMA_transferSize_16bit
Definition: dma.h:81
enum DMA_cycleType tDMA_cycleType
void DMA_setCh4IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 4 Interrupt Node Pointer.
INLINE void DMA_enCh5EndlessMode(void)
Enable DMA Channel 5 Endless Mode.
Definition: dma.h:391
INLINE uint8 DMA_getCh4IntSts(void)
Get DMA Channel 4 Interrupt Status.
Definition: dma.h:597
void DMA_resetChannel(uint8 u8_chIdx, uint32 u32_transferCnt)
Reset the primary structure in RAM for a given channel and rearm it.
Definition: dma.c:1174
INLINE uint8 DMA_getCh5IntSts(void)
Get DMA Channel 5 Interrupt Status.
Definition: dma.h:606
INLINE void DMA_enCh1Int(void)
Enable DMA Channel 1 Interrupt.
Definition: dma.h:447
INLINE void DMA_disCh6Int(void)
Disable DMA Channel 6 Interrupt.
Definition: dma.h:524
INLINE void DMA_clrCh6IntSts(void)
Clear DMA Channel 6 Interrupt Status.
Definition: dma.h:673
INLINE void DMA_enCh6EndlessMode(void)
Enable DMA Channel 6 Endless Mode.
Definition: dma.h:405
INLINE void DMA_disCh1Int(void)
Disable DMA Channel 1 Interrupt.
Definition: dma.h:454
tDMA_entry * DMA_setPrimaryTaskSctGth(tDMA_entry *s_primEntry, uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up the primary task to configure the scatter-gather mode.
Definition: dma.c:1262
struct DMA_entry tDMA_entry
INLINE uint8 DMA_getCh7IntSts(void)
Get DMA Channel 7 Interrupt Status.
Definition: dma.h:624
sint8 DMA_init(void)
Initialize the DMA structure in RAM and SFRs according to the ConfigWizard settings.
Definition: dma.c:684
INLINE void DMA_enCh7Int(void)
Enable DMA Channel 7 Interrupt.
Definition: dma.h:531
INLINE void DMA_disCh3EndlessMode(void)
Disable DMA Channel 3 Endless Mode.
Definition: dma.h:370
INLINE void DMA_clrCh5IntSts(void)
Clear DMA Channel 5 Interrupt Status.
Definition: dma.h:666
INLINE void DMA_disCh7Int(void)
Disable DMA Channel 7 Interrupt.
Definition: dma.h:538
void DMA_setCh0IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 0 Interrupt Node Pointer.
void DMA_setBasicTransfer(uint8 u8_chIdx, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a basic transfer for the desired DMA channel in the primary structure in RAM.
Definition: dma.c:1084
INLINE void DMA_setSWReq(uint8 u8_chIdx)
Sets the SW request for the given channel.
Definition: dma.h:688
INLINE void DMA_disCh4Int(void)
Disable DMA Channel 4 Interrupt.
Definition: dma.h:496
INLINE void DMA_clrCh7IntSts(void)
Clear DMA Channel 7 Interrupt Status.
Definition: dma.h:680
INLINE void DMA_disCh0Int(void)
Disable DMA Channel 0 Interrupt.
Definition: dma.h:440
INLINE void DMA_clrCh3IntSts(void)
Clear DMA Channel 3 Interrupt Status.
Definition: dma.h:652
INLINE void DMA_clrCh4IntSts(void)
Clear DMA Channel 4 Interrupt Status.
Definition: dma.h:659
#define DMA
Definition: tle989x.h:24069
#define SCU
Definition: tle989x.h:24075
__attribute__((noreturn))
Definition: startup_tle989x.c:193
uint32 u32_srcEndPtr
Definition: dma.h:150
tDMA_ctrl s_ctrl
Definition: dma.h:152
uint32 reserved
Definition: dma.h:153
uint32 u32_dstEndPtr
Definition: dma.h:151
This structure lists the DMA transfer memory locations.
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:151
uint8_t uint8
8 bit unsigned value
Definition: types.h:204
int8_t sint8
8 bit signed value
Definition: types.h:209
uint32_t uint32
32 bit unsigned value
Definition: types.h:206
This union and its structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:128
uint32 u32_cycleCtrl
Bit[2..0].
Definition: dma.h:132
uint32 u32_srcSize
Bit[25..24].
Definition: dma.h:138
uint32 u32_nextUseburst
Bit[3].
Definition: dma.h:133
uint32 u32_dstInc
Bit[31..30].
Definition: dma.h:141
uint32 u32_srcProtCtrl
Bit[20..18].
Definition: dma.h:136
uint32 u32_srcInc
Bit[27..26].
Definition: dma.h:139
uint32 u32_Rpower
Bit[17..14].
Definition: dma.h:135
uint32 u32_dstProtCtrl
Bit[23..21].
Definition: dma.h:137
uint32 u32_Nminus1
Bit[13..4].
Definition: dma.h:134
uint32 u32_dstSize
Bit[29..28].
Definition: dma.h:140
uint32 reg
Definition: dma.h:129