Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
pmu.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
26 /*******************************************************************************
27 ** Author(s) Identity **
28 ********************************************************************************
29 ** Initials Name **
30 ** ---------------------------------------------------------------------------**
31 ** JO Julia Ott **
32 ** BG Blandine Guillot **
33 ** DM Daniel Mysliwitz **
34 ** PS Patrik Schwarz **
35 *******************************************************************************/
36 
37 /*******************************************************************************
38 ** Revision Control History **
39 ********************************************************************************
40 ** V0.1.0: 2020-06-10, BG: Initial version **
41 ** V0.2.0: 2020-06-10, BG: Added declaration of global function **
42 ** V0.2.1: 2020-09-16, BG: Added interrupt enable/disable functions **
43 ** Added function for GPIO and MON as wake-up src **
44 ** V0.2.2: 2020-09-21, JO: EP-468: Corrected PMU_serviceFailSafeWatchdog() **
45 ** (toggle bit PMU->WD_TRIG.bit.TRIG to service the **
46 ** watchdog) **
47 ** V0.2.3: 2020-09-21, JO: EP-465: Added break commands to switch case **
48 ** statements in setGPIOWakeCfg and setMONWakeCfg **
49 ** V0.2.4: 2020-10-06, BG: EP-492: Removed MISRA 2012 errors **
50 ** V0.2.5: 2020-10-12, BG: EP-515: Added delay and cleared safe-state status**
51 ** for the fail-safe watchdog initialization **
52 ** EP-515: Updated PMU_serviceFailSafeWatchdog() **
53 ** with a safe trigger point calculated in Config **
54 ** Wizard **
55 ** EP-515: Updated functions name related to the **
56 ** fail-safe watchdog **
57 ** V0.2.6: 2020-10-16, JO: EP-523: Updated parameter names **
58 ** V0.2.7: 2020-10-20, BG: EP-534: Configured missing register START_CONFIG **
59 ** in the initialization function **
60 ** V0.2.8: 2020-10-20, JO: EP-515: Removed the enabling of the watchdog **
61 ** Added toggling of PMU->WD_TRIG.bit.TRIG for **
62 ** initial watchdog trigger **
63 ** V0.2.9: 2020-10-21, JO: EP-536: Applied PMU.WD_CTRL.EN setting in **
64 ** function PMU_initFailSafeWatchdog **
65 ** V0.3.0: 2020-11-12, JO: EP-590: Removed \param none and \return none to **
66 ** avoid doxygen warning **
67 ** V0.3.1: 2020-11-17, BG: EP-600: Corrected watchdog initialization **
68 ** V0.3.2: 2020-11-20, BG: EP-610: Corrected MISRA 2012 errors **
69 ** The following rules are globally deactivated: **
70 ** - Info 774: Boolean within 'if' always evaluates **
71 ** to False/True **
72 ** V0.3.3: 2020-12-02, BG: EP-626: Updated wake-up sources functions to **
73 ** consider several wake-up sources at once **
74 ** V0.4.0: 2020-12-04, JO: EP-626: Reworked PMU_enWakeupSrc and **
75 ** PMU_enWakeupSrc, added defines PMU_WAKEUPSRC_* **
76 ** as parameter for the functions (can be combined **
77 ** with bitwise OR) **
78 ** Added functions PMU_enStopModeVDDCReduct **
79 ** and PMU_disStopModeVDDCReduct **
80 ** V0.4.1: 2020-12-10, BG: EP-600: Added a function to clear the fail-safe **
81 ** watchdog fail status **
82 ** V0.4.2: 2020-12-18, BG: EP-652: Corrected name of error code variable **
83 ** V0.4.3: 2021-01-04, BG: EP-661: Renamed u32_maxDelay_ticks variable to **
84 ** u32_maxDelay_ms **
85 ** V0.4.4: 2021-01-20, BG: EP-679: Removed clearing of reset status register**
86 ** in the init function **
87 ** V0.4.5: 2021-02-10, JO: EP-696: Changed from anonymous to named typedefs **
88 ** to prevent MISRA warning **
89 ** V0.4.6: 2021-02-26, BG: EP-701: Updated function to trigger SOW **
90 ** Added SOW bitfield definition before the first **
91 ** watchdog trigger **
92 ** V0.4.7: 2021-03-08, BG: EP-733: Added FIFO pull-up enable in PMU_init **
93 ** after removing it from main function **
94 ** V0.4.8: 2021-03-17, BG: EP-737: Corrected misspelling for **
95 ** PMU_disWakeupSrc **
96 ** V0.4.9: 2021-06-02, BG: EP-813: Removed the clearing of status registers **
97 ** in the initialization function **
98 ** V0.5.0: 2021-06-18, JO: EP-842: Updated PMU_initFailSafeWatchdog for **
99 ** unit test (API call instead of bit access) **
100 ** V0.5.1: 2021-06-29, JO: EP-851: Made u32_failsafeWatchdogCnt volatile **
101 ** V0.5.2: 2021-07-21, BG: EP-870: Removed the range check for GPIO number **
102 ** PMU_setGPIOWakeCfg and for MON number for **
103 ** PMU_setMONWakeCfg so that the default case for **
104 ** switch is not empty **
105 ** V0.5.3: 2021-09-28, BG: EP-929: Updated PMU_init() so that checking for **
106 ** possible hardware failure does not block the **
107 ** initialization with Config Wizard defines **
108 ** V0.5.4: 2021-11-12, JO: EP-937: Updated copyright and branding **
109 ** V0.5.5: 2022-04-25, JO: EP-1139: Corrected definition of variable **
110 ** u32_failsafeWatchdogCnt **
111 ** Corrected doxygen errors/warnings **
112 ** V0.5.6: 2022-06-23, JO: EP-1150: Removed ARMCC V6.18 warnings **
113 ** V0.5.7: 2022-11-17, JO: EP-1342: Updated enum documentation to remove **
114 ** doxygen warning **
115 ** V0.5.8: 2023-03-01, BG: EP-1335: Removed the unnecessary while loop for **
116 ** the fail-safe watchdog initialization **
117 ** Moved the clearance of the WD fail status bit **
118 ** from PMU_serviceFailSafeWatchdog() to **
119 ** PMU_initFailSafeWatchdog() **
120 ** V0.5.9: 2023-04-04, PS: EP-1141: Correct MISRA warnings **
121 ** V0.6.0: 2023-04-26, BG: EP-1428: Removed the functions PMU_enStartCfg() **
122 ** and PMU_disStartCfg since the bitfield CONF in **
123 ** the register START_CONFIG is not available in the**
124 ** SVD file v1.0.0 **
125 ** V0.6.1: 2024-11-05, JO: EP-1494: Updated license **
126 *******************************************************************************/
127 
128 #ifndef _PMU_H
129 #define _PMU_H
130 
131 /*******************************************************************************
132 ** Includes **
133 *******************************************************************************/
134 #include "tle_variants.h"
135 #include "types.h"
136 #include "pmu_defines.h"
137 #include "tle989x.h"
138 #include "scu_defines.h"
139 
140 /*******************************************************************************
141 ** Global Macro Declarations **
142 *******************************************************************************/
144 #define PMU_WAKEUPSRC_CAN PMU_WAKE_CTRL_CAN_WAKE_EN_Msk
146 #define PMU_WAKEUPSRC_CYCLICSENSE (2u)
148 #define PMU_WAKEUPSRC_CYCLICWAKE PMU_WAKE_CTRL_CYC_WAKE_EN_Msk
150 #define PMU_WAKEUPSRC_GPIO0 PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk
152 #define PMU_WAKEUPSRC_GPIO1 PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk
154 #define PMU_WAKEUPSRC_GPIO2 PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk
156 #define PMU_WAKEUPSRC_GPIO3 PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk
158 #define PMU_WAKEUPSRC_GPIO4 PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk
160 #define PMU_WAKEUPSRC_GPIO5 PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk
162 #define PMU_WAKEUPSRC_MON1 PMU_WAKE_CTRL_MON0_WAKE_EN_Msk
164 #define PMU_WAKEUPSRC_MON2 PMU_WAKE_CTRL_MON1_WAKE_EN_Msk
166 #define PMU_WAKEUPSRC_MON3 PMU_WAKE_CTRL_MON2_WAKE_EN_Msk
168 #define PMU_WAKEUPSRC_VDDP_UV PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk
170 #define PMU_WAKEUPSRC_VDDP_OV PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk
172 #define PMU_WAKEUPSRC_VDDP_HCM PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk
174 #define PMU_WAKEUPSRC_VDDC_UV PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk
176 #define PMU_WAKEUPSRC_VDDC_OV PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk
178 #define PMU_WAKEUPSRC_VDDC_HCM PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk
180 #define PMU_WAKEUPSRC_VDDEXT_OT PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk
182 #define PMU_WAKEUPSRC_VDDEXT_UV PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk
184 #define PMU_WAKEUPSRC_VSD_OV PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk
186 #define PMU_WAKEUPSRC_ALL_SRC (0x11FF73F7UL)
188 #define PMU_WAKEUPSRC_ALLGPIOS (0x3F0UL)
189 
190 /*******************************************************************************
191 ** Global Type Declarations **
192 *******************************************************************************/
193 
198 typedef enum PMU_gpioInput
199 {
224  PMU_gpioInput_P2_9 = 24u
226 
227 /*******************************************************************************
228 ** Global Function Declarations **
229 *******************************************************************************/
230 
231 sint8 PMU_init(void);
232 void PMU_countFailSafeWatchdog(void);
234 void PMU_stopFailSafeWatchdog(void);
285 INLINE void PMU_clrHPClkFailSts(void);
287 INLINE void PMU_clrSeqWdFailSts(void);
304 INLINE void PMU_clrMstrClkWDRstSts(void);
306 INLINE void PMU_clrSleepExitRstSts(void);
307 INLINE void PMU_clrStopExitRstSts(void);
308 INLINE void PMU_clrPinRstSts(void);
310 INLINE void PMU_clrWDTimerRstSts(void);
311 INLINE void PMU_clrSoftRstSts(void);
312 INLINE void PMU_clrLockupRstSts(void);
316 INLINE sint8 PMU_enWakeupSrc(uint32 u32_wakeupSrc);
317 INLINE sint8 PMU_disWakeupSrc(uint32 u32_wakeupSrc);
321 INLINE sint8 PMU_setGPIOWakeCfg(uint8 u8_GPIO, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, tPMU_gpioInput e_gpioInput);
322 INLINE sint8 PMU_setMONWakeCfg(uint8 u8_MON, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, uint8 u8_enPullupCurrSrc, uint8 u8_enPulldownCurrSrc);
346 INLINE void PMU_clrCANWakeSts(void);
347 INLINE void PMU_clrCyclicWakeSts(void);
348 INLINE void PMU_clrGPIO0WakeSts(void);
349 INLINE void PMU_clrGPIO1WakeSts(void);
350 INLINE void PMU_clrGPIO2WakeSts(void);
351 INLINE void PMU_clrGPIO3WakeSts(void);
352 INLINE void PMU_clrGPIO4WakeSts(void);
353 INLINE void PMU_clrGPIO5WakeSts(void);
354 INLINE void PMU_clrMON1WakeSts(void);
355 INLINE void PMU_clrMON2WakeSts(void);
356 INLINE void PMU_clrMON3WakeSts(void);
366 INLINE void PMU_enFailInputPullUp(void);
367 INLINE void PMU_enResetPin(void);
368 INLINE void PMU_disFailInputPullUp(void);
369 INLINE void PMU_disResetPin(void);
389 INLINE void PMU_clrWDFailSts(void);
399 INLINE void PMU_clrCSCEnFailSts(void);
404 INLINE void PMU_clrSafeShutdownSts(void);
405 INLINE void PMU_clrFailOutputSts(void);
406 
407 /*******************************************************************************
408 ** Deprecated Function Declarations **
409 *******************************************************************************/
410 
414 void PMU_setVDDPUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
415 
419 void PMU_setVDDPOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
420 
424 void PMU_setVDDCUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
425 
429 void PMU_setVDDCOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
430 
434 void PMU_setVDDEXTUndervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
435 
439 void PMU_setVDDEXTOvertemperatureIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
440 
441 /*******************************************************************************
442 ** Global Inline Function Definitions **
443 *******************************************************************************/
444 
448 {
449  PMU->VDDP_IRQEN.bit.UVWARN_IEN = 1u;
450 }
451 
455 {
456  PMU->VDDP_IRQEN.bit.OV_IEN = 1u;
457 }
458 
462 {
463  PMU->VDDP_IRQEN.bit.UVWARN_IEN = 0u;
464 }
465 
469 {
470  PMU->VDDP_IRQEN.bit.OV_IEN = 0u;
471 }
472 
478 {
479  return (uint8)PMU->VDDP_STS.bit.UVWARN_IS;
480 }
481 
487 {
488  return (uint8)PMU->VDDP_STS.bit.OV_IS;
489 }
490 
496 {
497  return (uint8)PMU->VDDP_STS.bit.UVWARN_STS;
498 }
499 
505 {
506  return (uint8)PMU->VDDP_STS.bit.ILIM_STS;
507 }
508 
514 {
515  return (uint8)PMU->VDDP_STS.bit.HCM_STS;
516 }
517 
521 {
522  PMU->VDDP_STS_CLR.bit.UVWARN_IS_CLR = 1u;
523 }
524 
528 {
529  PMU->VDDP_STS_CLR.bit.OV_IS_CLR = 1u;
530 }
531 
535 {
536  PMU->VDDP_STS_CLR.bit.UVWARN_STS_CLR = 1u;
537 }
538 
542 {
543  PMU->VDDP_STS_CLR.bit.ILIM_STS_CLR = 1u;
544 }
545 
549 {
550  PMU->VDDP_STS_CLR.bit.HCM_STS_CLR = 1u;
551 }
552 
556 {
557  PMU->VDDC_IRQEN.bit.UVWARN_IEN = 1u;
558 }
559 
563 {
564  PMU->VDDC_IRQEN.bit.OV_IEN = 1u;
565 }
566 
570 {
571  PMU->VDDC_IRQEN.bit.UVWARN_IEN = 0u;
572 }
573 
577 {
578  PMU->VDDC_IRQEN.bit.OV_IEN = 0u;
579 }
580 
586 {
587  return (uint8)PMU->VDDC_STS.bit.UVWARN_IS;
588 }
589 
595 {
596  return (uint8)PMU->VDDC_STS.bit.OV_IS;
597 }
598 
604 {
605  return (uint8)PMU->VDDC_STS.bit.UVWARN_STS;
606 }
607 
613 {
614  return (uint8)PMU->VDDC_STS.bit.HCM_STS;
615 }
616 
620 {
621  PMU->VDDC_STS_CLR.bit.UVWARN_IS_CLR = 1u;
622 }
623 
627 {
628  PMU->VDDC_STS_CLR.bit.OV_IS_CLR = 1u;
629 }
630 
634 {
635  PMU->VDDC_STS_CLR.bit.UVWARN_STS_CLR = 1u;
636 }
637 
641 {
642  PMU->VDDC_STS_CLR.bit.HCM_STS_CLR = 1u;
643 }
644 
648 {
649  PMU->VDDEXT_IRQEN.bit.UV_IEN = 1u;
650 }
651 
655 {
656  PMU->VDDEXT_IRQEN.bit.OT_IEN = 1u;
657 }
658 
662 {
663  PMU->VDDEXT_IRQEN.bit.UV_IEN = 0u;
664 }
665 
669 {
670  PMU->VDDEXT_IRQEN.bit.OT_IEN = 0u;
671 }
672 
678 {
679  return (uint8)PMU->VDDEXT_STS.bit.UV_IS;
680 }
681 
687 {
688  return (uint8)PMU->VDDEXT_STS.bit.OT_IS;
689 }
690 
696 {
697  return (uint8)PMU->VDDEXT_STS.bit.UV_STS;
698 }
699 
705 {
706  return (uint8)PMU->VDDEXT_STS.bit.OT_STS;
707 }
708 
712 {
713  PMU->VDDEXT_STS_CLR.bit.UV_IS_CLR = 1u;
714 }
715 
719 {
720  PMU->VDDEXT_STS_CLR.bit.OT_IS_CLR = 1u;
721 }
722 
726 {
727  PMU->VDDEXT_STS_CLR.bit.UV_STS_CLR = 1u;
728 }
729 
733 {
734  PMU->VDDEXT_STS_CLR.bit.OT_STS_CLR = 1u;
735 }
736 
742 {
743  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDP_TMOUT;
744 }
745 
751 {
752  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDC_TMOUT;
753 }
754 
760 {
761  return (uint8)PMU->WAKE_FAIL_STS.bit.HPCLK_FAIL;
762 }
763 
769 {
770  return (uint8)PMU->WAKE_FAIL_STS.bit.SYS_OT;
771 }
772 
778 {
779  return (uint8)PMU->WAKE_FAIL_STS.bit.FSWD_SEQ_FAIL;
780 }
781 
787 {
788  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDP_OT;
789 }
790 
796 {
797  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDC_OC;
798 }
799 
803 {
804  PMU->WAKE_FAIL_CLR.bit.VDDP_TMOUT_CLR = 1u;
805 }
806 
810 {
811  PMU->WAKE_FAIL_CLR.bit.VDDC_TMOUT_CLR = 1u;
812 }
813 
817 {
818  PMU->WAKE_FAIL_CLR.bit.HPCLK_FAIL_CLR = 1u;
819 }
820 
824 {
825  PMU->WAKE_FAIL_CLR.bit.SYS_OT_CLR = 1u;
826 }
827 
831 {
832  PMU->WAKE_FAIL_CLR.bit.FSWD_SEQ_FAIL_CLR = 1u;
833 }
834 
838 {
839  PMU->WAKE_FAIL_CLR.bit.VDDP_OT_CLR = 1u;
840 }
841 
845 {
846  PMU->WAKE_FAIL_CLR.bit.VDDC_OC_CLR = 1u;
847 }
848 
854 {
855  return (uint8)PMU->RESET_STS.bit.VMSUP_UV_RST;
856 }
857 
863 {
864  return (uint8)PMU->RESET_STS.bit.MCLK_WD_RST;
865 }
866 
872 {
873  return (uint8)PMU->RESET_STS.bit.FS_SLEEPEX_RST;
874 }
875 
881 {
882  return (uint8)PMU->RESET_STS.bit.SLEEPEX_RST;
883 }
884 
890 {
891  return (uint8)PMU->RESET_STS.bit.STOPEX_RST;
892 }
893 
899 {
900  return (uint8)PMU->RESET_STS.bit.PIN_RST;
901 }
902 
908 {
909  return (uint8)PMU->RESET_STS.bit.FSWD_RST;
910 }
911 
917 {
918  return (uint8)PMU->RESET_STS.bit.WDT_MCU_RST;
919 }
920 
926 {
927  return (uint8)PMU->RESET_STS.bit.SOFT_RST;
928 }
929 
935 {
936  return (uint8)PMU->RESET_STS.bit.LOCKUP_RST;
937 }
938 
944 {
945  return (uint8)PMU->RESET_STS.bit.VDDP_UV_RST;
946 }
947 
953 {
954  return (uint8)PMU->RESET_STS.bit.VDDC_UV_RST;
955 }
956 
962 {
963  return (uint8)PMU->RESET_STS.bit.SEC_STACK_RST;
964 }
965 
969 {
970  PMU->RESET_STS_CLR.bit.VMSUP_UV_RST_CLR = 1u;
971 }
972 
976 {
977  PMU->RESET_STS_CLR.bit.MCLK_WD_RST_CLR = 1u;
978 }
979 
983 {
984  PMU->RESET_STS_CLR.bit.FS_SLEEPEX_RST_CLR = 1u;
985 }
986 
990 {
991  PMU->RESET_STS_CLR.bit.SLEEPEX_RST_CLR = 1u;
992 }
993 
997 {
998  PMU->RESET_STS_CLR.bit.STOPEX_RST_CLR = 1u;
999 }
1000 
1004 {
1005  PMU->RESET_STS_CLR.bit.PIN_RST_CLR = 1u;
1006 }
1007 
1011 {
1012  PMU->RESET_STS_CLR.bit.FSWD_RST_CLR = 1u;
1013 }
1014 
1018 {
1019  PMU->RESET_STS_CLR.bit.WDT_MCU_RST_CLR = 1u;
1020 }
1021 
1025 {
1026  PMU->RESET_STS_CLR.bit.SOFT_RST_CLR = 1u;
1027 }
1028 
1032 {
1033  PMU->RESET_STS_CLR.bit.LOCKUP_RST_CLR = 1u;
1034 }
1035 
1039 {
1040  PMU->RESET_STS_CLR.bit.VDDP_UV_RST_CLR = 1u;
1041 }
1042 
1046 {
1047  PMU->RESET_STS_CLR.bit.VDDC_UV_RST_CLR = 1u;
1048 }
1049 
1053 {
1054  PMU->RESET_STS_CLR.bit.SEC_STACK_RST_CLR = 1u;
1055 }
1056 
1063 {
1064  sint8 s8_returnCode;
1065  uint32 u32_wakeupSrcWithoutCycSense;
1066  s8_returnCode = ERR_LOG_SUCCESS;
1067  /* PMU_WAKEUPSRC_CYCLICSENSE is not part of register PMU->WAKE_CTRL */
1068  u32_wakeupSrcWithoutCycSense = u32_wakeupSrc & (~PMU_WAKEUPSRC_CYCLICSENSE);
1069 
1070  if ((u32_wakeupSrc & (~PMU_WAKEUPSRC_ALL_SRC)) == 0u)
1071  {
1072  PMU->WAKE_CTRL.reg |= u32_wakeupSrcWithoutCycSense;
1073 
1074  /* PMU_WAKEUPSRC_CYCLICSENSE is in register CYC_CTRL */
1075  if ((u32_wakeupSrc & PMU_WAKEUPSRC_CYCLICSENSE) == PMU_WAKEUPSRC_CYCLICSENSE)
1076  {
1077  PMU->CYC_CTRL.bit.CYC_SENSE_EN = 1u;
1078  }
1079  }
1080  else
1081  {
1082  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1083  }
1084 
1085  return s8_returnCode;
1086 }
1087 
1094 {
1095  sint8 s8_returnCode;
1096  uint32 u32_wakeupSrcWithoutCycSense;
1097  s8_returnCode = ERR_LOG_SUCCESS;
1098  /* PMU_WAKEUPSRC_CYCLICSENSE is not part of register PMU->WAKE_CTRL */
1099  u32_wakeupSrcWithoutCycSense = u32_wakeupSrc & ~PMU_WAKEUPSRC_CYCLICSENSE;
1100 
1101  if ((u32_wakeupSrc & (~PMU_WAKEUPSRC_ALL_SRC)) == 0u)
1102  {
1103  PMU->WAKE_CTRL.reg &= (~u32_wakeupSrcWithoutCycSense);
1104 
1105  /* PMU_WAKEUPSRC_CYCLICSENSE is in register CYC_CTRL */
1106  if ((u32_wakeupSrc & PMU_WAKEUPSRC_CYCLICSENSE) == PMU_WAKEUPSRC_CYCLICSENSE)
1107  {
1108  PMU->CYC_CTRL.bit.CYC_SENSE_EN = 0u;
1109  }
1110  }
1111  else
1112  {
1113  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1114  }
1115 
1116  return s8_returnCode;
1117 }
1118 
1124 {
1125  return PMU->WAKE_CTRL.reg;
1126 }
1127 
1131 {
1132  PMU->WAKE_CTRL.bit.VDDC_RED_EN = 1u;
1133 }
1134 
1138 {
1139  PMU->WAKE_CTRL.bit.VDDC_RED_EN = 0u;
1140 }
1141 
1151 INLINE sint8 PMU_setGPIOWakeCfg(uint8 u8_GPIO, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, tPMU_gpioInput e_gpioInput)
1152 {
1153  sint8 s8_returnCode;
1154  s8_returnCode = ERR_LOG_SUCCESS;
1155 
1156  if ((u8_enRisingEdge <= 1) && (u8_enFallingEdge <= 1) && (u8_enCycSen <= 1) && (e_gpioInput <= PMU_gpioInput_P2_9))
1157  {
1158  switch (u8_GPIO)
1159  {
1160  case 0:
1161  {
1162  PMU->WAKE_GPIO_CTRL0.bit.RI = u8_enRisingEdge;
1163  PMU->WAKE_GPIO_CTRL0.bit.FA = u8_enFallingEdge;
1164  PMU->WAKE_GPIO_CTRL0.bit.CYC = u8_enCycSen;
1165  PMU->WAKE_GPIO_CTRL0.bit.INP = (uint8)e_gpioInput;
1166  break;
1167  }
1168 
1169  case 1:
1170  {
1171  PMU->WAKE_GPIO_CTRL1.bit.RI = u8_enRisingEdge;
1172  PMU->WAKE_GPIO_CTRL1.bit.FA = u8_enFallingEdge;
1173  PMU->WAKE_GPIO_CTRL1.bit.CYC = u8_enCycSen;
1174  PMU->WAKE_GPIO_CTRL1.bit.INP = (uint8)e_gpioInput;
1175  break;
1176  }
1177 
1178  case 2:
1179  {
1180  PMU->WAKE_GPIO_CTRL2.bit.RI = u8_enRisingEdge;
1181  PMU->WAKE_GPIO_CTRL2.bit.FA = u8_enFallingEdge;
1182  PMU->WAKE_GPIO_CTRL2.bit.CYC = u8_enCycSen;
1183  PMU->WAKE_GPIO_CTRL2.bit.INP = (uint8)e_gpioInput;
1184  break;
1185  }
1186 
1187  case 3:
1188  {
1189  PMU->WAKE_GPIO_CTRL3.bit.RI = u8_enRisingEdge;
1190  PMU->WAKE_GPIO_CTRL3.bit.FA = u8_enFallingEdge;
1191  PMU->WAKE_GPIO_CTRL3.bit.CYC = u8_enCycSen;
1192  PMU->WAKE_GPIO_CTRL3.bit.INP = (uint8)e_gpioInput;
1193  break;
1194  }
1195 
1196  case 4:
1197  {
1198  PMU->WAKE_GPIO_CTRL4.bit.RI = u8_enRisingEdge;
1199  PMU->WAKE_GPIO_CTRL4.bit.FA = u8_enFallingEdge;
1200  PMU->WAKE_GPIO_CTRL4.bit.CYC = u8_enCycSen;
1201  PMU->WAKE_GPIO_CTRL4.bit.INP = (uint8)e_gpioInput;
1202  break;
1203  }
1204 
1205  case 5:
1206  {
1207  PMU->WAKE_GPIO_CTRL5.bit.RI = u8_enRisingEdge;
1208  PMU->WAKE_GPIO_CTRL5.bit.FA = u8_enFallingEdge;
1209  PMU->WAKE_GPIO_CTRL5.bit.CYC = u8_enCycSen;
1210  PMU->WAKE_GPIO_CTRL5.bit.INP = (uint8)e_gpioInput;
1211  break;
1212  }
1213 
1214  default:
1215  {
1216  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1217  break;
1218  }
1219  }
1220  }
1221  else
1222  {
1223  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1224  }
1225 
1226  return s8_returnCode;
1227 }
1228 
1239 INLINE sint8 PMU_setMONWakeCfg(uint8 u8_MON, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, uint8 u8_enPullupCurrSrc, uint8 u8_enPulldownCurrSrc)
1240 {
1241  sint8 s8_returnCode;
1242  s8_returnCode = ERR_LOG_SUCCESS;
1243 
1244  if ((u8_enRisingEdge <= 1) && (u8_enFallingEdge <= 1) && (u8_enCycSen <= 1) && (u8_enPullupCurrSrc <= 1) && (u8_enPulldownCurrSrc <= 1))
1245  {
1246  switch (u8_MON)
1247  {
1248  case 1:
1249  {
1250  PMU->MON_CTRL1.bit.WAKE_RISE = u8_enRisingEdge;
1251  PMU->MON_CTRL1.bit.WAKE_FALL = u8_enFallingEdge;
1252  PMU->MON_CTRL1.bit.CYC_SENSE_EN = u8_enCycSen;
1253  PMU->MON_CTRL1.bit.PU = u8_enPullupCurrSrc;
1254  PMU->MON_CTRL1.bit.PD = u8_enPulldownCurrSrc;
1255  break;
1256  }
1257 
1258  case 2:
1259  {
1260  PMU->MON_CTRL2.bit.WAKE_RISE = u8_enRisingEdge;
1261  PMU->MON_CTRL2.bit.WAKE_FALL = u8_enFallingEdge;
1262  PMU->MON_CTRL2.bit.CYC_SENSE_EN = u8_enCycSen;
1263  PMU->MON_CTRL2.bit.PU = u8_enPullupCurrSrc;
1264  PMU->MON_CTRL2.bit.PD = u8_enPulldownCurrSrc;
1265  break;
1266  }
1267 
1268  case 3:
1269  {
1270  PMU->MON_CTRL3.bit.WAKE_RISE = u8_enRisingEdge;
1271  PMU->MON_CTRL3.bit.WAKE_FALL = u8_enFallingEdge;
1272  PMU->MON_CTRL3.bit.CYC_SENSE_EN = u8_enCycSen;
1273  PMU->MON_CTRL3.bit.PU = u8_enPullupCurrSrc;
1274  PMU->MON_CTRL3.bit.PD = u8_enPulldownCurrSrc;
1275  break;
1276  }
1277 
1278  default:
1279  {
1280  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1281  break;
1282  }
1283  }
1284  }
1285  else
1286  {
1287  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1288  }
1289 
1290  return s8_returnCode;
1291 }
1292 
1298 {
1299  return (uint8)PMU->MON_STS.bit.MON1_STS;
1300 }
1301 
1307 {
1308  return (uint8)PMU->MON_STS.bit.MON2_STS;
1309 }
1310 
1316 {
1317  return (uint8)PMU->MON_STS.bit.MON3_STS;
1318 }
1319 
1325 {
1326  return (uint8)PMU->WAKE_STS.bit.CAN;
1327 }
1328 
1334 {
1335  return (uint8)PMU->WAKE_STS.bit.CYC_WAKE;
1336 }
1337 
1343 {
1344  return (uint8)PMU->WAKE_STS.bit.GPIO0;
1345 }
1346 
1352 {
1353  return (uint8)PMU->WAKE_STS.bit.GPIO1;
1354 }
1355 
1361 {
1362  return (uint8)PMU->WAKE_STS.bit.GPIO2;
1363 }
1364 
1370 {
1371  return (uint8)PMU->WAKE_STS.bit.GPIO3;
1372 }
1373 
1379 {
1380  return (uint8)PMU->WAKE_STS.bit.GPIO4;
1381 }
1382 
1388 {
1389  return (uint8)PMU->WAKE_STS.bit.GPIO5;
1390 }
1391 
1397 {
1398  return (uint8)PMU->WAKE_STS.bit.MON1;
1399 }
1400 
1406 {
1407  return (uint8)PMU->WAKE_STS.bit.MON2;
1408 }
1409 
1415 {
1416  return (uint8)PMU->WAKE_STS.bit.MON3;
1417 }
1418 
1424 {
1425  return (uint8)PMU->WAKE_STS.bit.VDDP_UVWARN;
1426 }
1427 
1433 {
1434  return (uint8)PMU->WAKE_STS.bit.VDDP_OV;
1435 }
1436 
1442 {
1443  return (uint8)PMU->WAKE_STS.bit.VDDP_HCM;
1444 }
1445 
1451 {
1452  return (uint8)PMU->WAKE_STS.bit.VDDC_UVWARN;
1453 }
1454 
1460 {
1461  return (uint8)PMU->WAKE_STS.bit.VDDC_OV;
1462 }
1463 
1469 {
1470  return (uint8)PMU->WAKE_STS.bit.VDDC_HCM;
1471 }
1472 
1478 {
1479  return (uint8)PMU->WAKE_STS.bit.VDDEXT_OT;
1480 }
1481 
1487 {
1488  return (uint8)PMU->WAKE_STS.bit.VDDEXT_UV;
1489 }
1490 
1496 {
1497  return (uint8)PMU->WAKE_STS.bit.VSD_OV;
1498 }
1499 
1503 {
1504  PMU->WAKE_STS_CLR.bit.CAN_CLR = 1u;
1505 }
1506 
1510 {
1511  PMU->WAKE_STS_CLR.bit.CYC_WAKE_CLR = 1u;
1512 }
1513 
1517 {
1518  PMU->WAKE_STS_CLR.bit.GPIO0_CLR = 1u;
1519 }
1520 
1524 {
1525  PMU->WAKE_STS_CLR.bit.GPIO1_CLR = 1u;
1526 }
1527 
1531 {
1532  PMU->WAKE_STS_CLR.bit.GPIO2_CLR = 1u;
1533 }
1534 
1538 {
1539  PMU->WAKE_STS_CLR.bit.GPIO3_CLR = 1u;
1540 }
1541 
1545 {
1546  PMU->WAKE_STS_CLR.bit.GPIO4_CLR = 1u;
1547 }
1548 
1552 {
1553  PMU->WAKE_STS_CLR.bit.GPIO5_CLR = 1u;
1554 }
1555 
1559 {
1560  PMU->WAKE_STS_CLR.bit.MON1_CLR = 1u;
1561 }
1562 
1566 {
1567  PMU->WAKE_STS_CLR.bit.MON2_CLR = 1u;
1568 }
1569 
1573 {
1574  PMU->WAKE_STS_CLR.bit.MON3_CLR = 1u;
1575 }
1576 
1580 {
1581  PMU->WAKE_STS_CLR.bit.VDDP_UVWARN_CLR = 1u;
1582 }
1583 
1587 {
1588  PMU->WAKE_STS_CLR.bit.VDDP_OV_CLR = 1u;
1589 }
1590 
1594 {
1595  PMU->WAKE_STS_CLR.bit.VDDP_HCM_CLR = 1u;
1596 }
1597 
1601 {
1602  PMU->WAKE_STS_CLR.bit.VDDC_UVWARN_CLR = 1u;
1603 }
1604 
1608 {
1609  PMU->WAKE_STS_CLR.bit.VDDC_OV_CLR = 1u;
1610 }
1611 
1615 {
1616  PMU->WAKE_STS_CLR.bit.VDDC_HCM_CLR = 1u;
1617 }
1618 
1622 {
1623  PMU->WAKE_STS_CLR.bit.VDDEXT_OT_CLR = 1u;
1624 }
1625 
1629 {
1630  PMU->WAKE_STS_CLR.bit.VDDEXT_UV_CLR = 1u;
1631 }
1632 
1636 {
1637  PMU->WAKE_STS_CLR.bit.VSD_OV_CLR = 1u;
1638 }
1639 
1643 {
1644  PMU->MISC_CTRL.bit.FI_PU_EN = 1u;
1645 }
1646 
1650 {
1651  PMU->START_CONFIG.bit.RST_PIN_EN = 1u;
1652 }
1653 
1657 {
1658  PMU->MISC_CTRL.bit.FI_PU_EN = 0u;
1659 }
1660 
1664 {
1665  PMU->START_CONFIG.bit.RST_PIN_EN = 0u;
1666 }
1667 
1673 {
1674  return (uint8)PMU->FS_STS.bit.MCLK_FAIL_STS;
1675 }
1676 
1682 {
1683  return (uint8)PMU->FS_STS.bit.VMSUP_UV_STS;
1684 }
1685 
1691 {
1692  return (uint8)PMU->FS_STS.bit.VMSUP_OV_STS;
1693 }
1694 
1700 {
1701  return (uint8)PMU->FS_STS.bit.WD_FAIL_STS;
1702 }
1703 
1709 {
1710  return (uint8)PMU->FS_STS.bit.WD_TEST_FAIL_STS;
1711 }
1712 
1718 {
1719  return (uint8)PMU->FS_STS.bit.VDDC_UV_STS;
1720 }
1721 
1727 {
1728  return (uint8)PMU->FS_STS.bit.VDDC_OV_STS;
1729 }
1730 
1736 {
1737  return (uint8)PMU->FS_STS.bit.VDDP_UV_STS;
1738 }
1739 
1745 {
1746  return (uint8)PMU->FS_STS.bit.VDDP_OV_STS;
1747 }
1748 
1754 {
1755  return (uint8)PMU->FS_STS.bit.VDDP_OT_STS;
1756 }
1757 
1763 {
1764  return (uint8)PMU->FS_STS.bit.VAREF_OV_STS;
1765 }
1766 
1772 {
1773  return (uint8)PMU->FS_STS.bit.CSC_OC_STS;
1774 }
1775 
1781 {
1782  return (uint8)PMU->FS_STS.bit.CSC_BIST_FAIL_STS;
1783 }
1784 
1790 {
1791  return (uint8)PMU->FS_STS.bit.CSC_EN_FAIL_STS;
1792 }
1793 
1799 {
1800  return (uint8)PMU->FS_STS.bit.PIN_MON_STS;
1801 }
1802 
1808 {
1809  return (uint8)PMU->FS_STS.bit.FO_OC_STS;
1810 }
1811 
1815 {
1816  PMU->FS_STS_CLR.bit.MCLK_FAIL_STS_CLR = 1u;
1817 }
1818 
1822 {
1823  PMU->FS_STS_CLR.bit.VMSUP_UV_STS_CLR = 1u;
1824 }
1825 
1829 {
1830  PMU->FS_STS_CLR.bit.VMSUP_OV_STS_CLR = 1u;
1831 }
1832 
1836 {
1837  PMU->FS_STS_CLR.bit.WD_FAIL_STS_CLR = 1u;
1838 }
1839 
1843 {
1844  PMU->FS_STS_CLR.bit.WD_TEST_FAIL_STS_CLR = 1u;
1845 }
1846 
1850 {
1851  PMU->FS_STS_CLR.bit.VDDC_UV_STS_CLR = 1u;
1852 }
1853 
1857 {
1858  PMU->FS_STS_CLR.bit.VDDC_OV_STS_CLR = 1u;
1859 }
1860 
1864 {
1865  PMU->FS_STS_CLR.bit.VDDP_UV_STS_CLR = 1u;
1866 }
1867 
1871 {
1872  PMU->FS_STS_CLR.bit.VDDP_OV_STS_CLR = 1u;
1873 }
1874 
1878 {
1879  PMU->FS_STS_CLR.bit.VDDP_OT_STS_CLR = 1u;
1880 }
1881 
1885 {
1886  PMU->FS_STS_CLR.bit.VAREF_OV_STS_CLR = 1u;
1887 }
1888 
1892 {
1893  PMU->FS_STS_CLR.bit.CSC_OC_STS_CLR = 1u;
1894 }
1895 
1899 {
1900  PMU->FS_STS_CLR.bit.CSC_BIST_FAIL_STS_CLR = 1u;
1901 }
1902 
1906 {
1907  PMU->FS_STS_CLR.bit.CSC_EN_FAIL_STS_CLR = 1u;
1908 }
1909 
1913 {
1914  PMU->FS_STS_CLR.bit.PIN_MON_STS_CLR = 1u;
1915 }
1916 
1920 {
1921  PMU->FS_STS_CLR.bit.FO_OC_STS_CLR = 1u;
1922 }
1923 
1929 {
1930  return (uint8)PMU->FS_SSD.bit.SSD_STS;
1931 }
1932 
1938 {
1939  return (uint8)PMU->FS_SSD.bit.FO_STS;
1940 }
1941 
1945 {
1946  PMU->FS_SSD_CLR.bit.SSD_STS_CLR = 1u;
1947 }
1948 
1952 {
1953  PMU->FS_SSD_CLR.bit.FO_STS_CLR = 1u;
1954 }
1955 
1958 #endif /* _PMU_H */
1959 
#define ERR_LOG_SUCCESS
Definition: error_codes.h:60
#define PMU
Definition: tle989x.h:24074
INLINE void PMU_disFailInputPullUp(void)
Disable the failure input pull up.
Definition: pmu.h:1656
INLINE void PMU_clrMON1WakeSts(void)
Clear MON1 wake-up status.
Definition: pmu.h:1558
INLINE uint8 PMU_getHPClkFailSts(void)
Get HP clock fail status.
Definition: pmu.h:759
INLINE sint8 PMU_enWakeupSrc(uint32 u32_wakeupSrc)
Enable a wake-up source.
Definition: pmu.h:1062
INLINE uint8 PMU_getSecureStackOverflowRstSts(void)
Get secure stack overflow reset status.
Definition: pmu.h:961
INLINE void PMU_clrVDDEXTUndervoltageIntSts(void)
Clear VDDEXT undervoltage interrupt status.
Definition: pmu.h:711
INLINE uint8 PMU_getCSCSelfTestFailSts(void)
Get CSC self-test fail status.
Definition: pmu.h:1780
void PMU_setVDDPOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDP Overvoltage Interrupt Node Pointer.
INLINE void PMU_clrWDTimerRstSts(void)
Clear MCU watchdog timer reset status.
Definition: pmu.h:1017
#define PMU_WAKEUPSRC_ALL_SRC
PMU Wake-up source all sources.
Definition: pmu.h:186
INLINE void PMU_enVDDCUndervoltageWarnInt(void)
Enable VDDC undervoltage warning interrupt.
Definition: pmu.h:555
INLINE uint8 PMU_getVDDPUndervoltageWarnSts(void)
Get VDDP undervoltage warning status.
Definition: pmu.h:495
INLINE void PMU_clrVDDPUndervoltageWarnWakeSts(void)
Clear VDDP undervoltage warning wake-up status.
Definition: pmu.h:1579
INLINE uint8 PMU_getMON2WakeSts(void)
Get MON2 wake-up status.
Definition: pmu.h:1405
INLINE void PMU_clrVDDCUndervoltageWarnWakeSts(void)
Clear VDDC undervoltage warning wake-up status.
Definition: pmu.h:1600
INLINE uint8 PMU_getGPIO2WakeSts(void)
Get GPIO2 wake-up status.
Definition: pmu.h:1360
INLINE void PMU_clrVDDCUndervoltageWarnSts(void)
Clear VDDC undervoltage warning status.
Definition: pmu.h:633
INLINE uint8 PMU_getGPIO5WakeSts(void)
Get GPIO5 wake-up status.
Definition: pmu.h:1387
INLINE uint8 PMU_getVDDPOvervoltageSts(void)
Get VDDP overvoltage status.
Definition: pmu.h:1744
INLINE uint8 PMU_getCANWakeSts(void)
Get CAN wake-up status.
Definition: pmu.h:1324
INLINE uint8 PMU_getMON3InputSts(void)
Get MON3 input status.
Definition: pmu.h:1315
#define PMU_WAKEUPSRC_CYCLICSENSE
PMU Wake-up source cyclic sense.
Definition: pmu.h:146
INLINE void PMU_clrSeqWdFailSts(void)
Clear sequential watchdog fail status.
Definition: pmu.h:830
INLINE uint8 PMU_getMstrSupplyUndervoltageSts(void)
Get master supply undervoltage status.
Definition: pmu.h:1681
INLINE uint8 PMU_getVDDPOvertemperatureSts(void)
Get VDDP overtemperature status.
Definition: pmu.h:1753
INLINE sint8 PMU_setMONWakeCfg(uint8 u8_MON, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, uint8 u8_enPullupCurrSrc, uint8 u8_enPulldownCurrSrc)
Set a MON wake configuration.
Definition: pmu.h:1239
INLINE void PMU_clrFailOutputSts(void)
Clear fail output status.
Definition: pmu.h:1951
INLINE void PMU_clrVSDOvervoltageWakeSts(void)
Clear VSD overvoltage wake-up status.
Definition: pmu.h:1635
INLINE void PMU_clrCSCOvercurrentSts(void)
Clear CSC overcurrent status.
Definition: pmu.h:1891
INLINE void PMU_clrGPIO5WakeSts(void)
Clear GPIO5 wake-up status.
Definition: pmu.h:1551
INLINE void PMU_enVDDEXTUndervoltageInt(void)
Enable VDDEXT undervoltage interrupt.
Definition: pmu.h:647
INLINE uint8 PMU_getWDSelfTestFailSts(void)
Get watchdog self-test fail status.
Definition: pmu.h:1708
INLINE uint8 PMU_getCyclicWakeSts(void)
Get cyclic wake-up status.
Definition: pmu.h:1333
INLINE void PMU_clrVDDPHighCurrentModeSts(void)
Clear VDDP high current mode status.
Definition: pmu.h:548
void PMU_stopFailSafeWatchdog(void)
Stop the fail-safe watchdog.
Definition: pmu.c:140
INLINE void PMU_clrVDDPCurrentLimitSts(void)
Clear VDDP current limitation status.
Definition: pmu.h:541
INLINE uint8 PMU_getVDDCUndervoltageRstSts(void)
Get VDDC undervoltage reset status.
Definition: pmu.h:952
INLINE void PMU_clrVDDCUndervoltageSts(void)
Clear VDDC undervoltage status.
Definition: pmu.h:1849
INLINE uint8 PMU_getSoftRstSts(void)
Get soft reset status.
Definition: pmu.h:925
INLINE void PMU_clrVDDCUndervoltageWarnIntSts(void)
Clear VDDC undervoltage warning interrupt status.
Definition: pmu.h:619
INLINE uint8 PMU_getMstrSupplyOvervoltageSts(void)
Get master supply overvoltage status.
Definition: pmu.h:1690
INLINE void PMU_clrVDDPUndervoltageWarnIntSts(void)
Clear VDDP undervoltage warning interrupt status.
Definition: pmu.h:520
INLINE void PMU_enVDDPOvervoltageInt(void)
Enable VDDP overvoltage interrupt.
Definition: pmu.h:454
INLINE void PMU_clrVDDPOvertemperatureSts(void)
Clear VDDP overtemperature status.
Definition: pmu.h:1877
INLINE void PMU_clrVDDCHighCurrentModeWakeSts(void)
Clear VDDC high current mode wake-up status.
Definition: pmu.h:1614
void PMU_clrFailSafeWatchdogFailSts(void)
Clear the fail-safe watchdog fail status.
Definition: pmu.c:188
INLINE void PMU_clrWDFailSts(void)
Clear watchdog fail status.
Definition: pmu.h:1835
INLINE uint8 PMU_getSleepExitRstSts(void)
Get sleep mode exit reset status.
Definition: pmu.h:880
INLINE uint8 PMU_getVDDPHighCurrentModeWakeSts(void)
Get VDDP high current mode wake-up status.
Definition: pmu.h:1441
INLINE void PMU_disVDDPOvervoltageInt(void)
Disable VDDP overvoltage interrupt.
Definition: pmu.h:468
INLINE uint8 PMU_getMON2InputSts(void)
Get MON2 input status.
Definition: pmu.h:1306
INLINE void PMU_clrVDDPHighCurrentModeWakeSts(void)
Clear VDDP high current mode wake-up status.
Definition: pmu.h:1593
INLINE void PMU_enVDDCOvervoltageInt(void)
Enable VDDC overvoltage interrupt.
Definition: pmu.h:562
INLINE void PMU_clrGPIO4WakeSts(void)
Clear GPIO4 wake-up status.
Definition: pmu.h:1544
INLINE uint8 PMU_getVDDCOvervoltageIntSts(void)
Get VDDC overvoltage interrupt status.
Definition: pmu.h:594
INLINE void PMU_clrFailSafeWDRstSts(void)
Clear fail safe watchdog reset status.
Definition: pmu.h:1010
INLINE uint8 PMU_getVDDCUndervoltageWarnWakeSts(void)
Get VDDC undervoltage warning wake-up status.
Definition: pmu.h:1450
INLINE uint8 PMU_getFOOvercurrentSts(void)
Get FO overcurrent status.
Definition: pmu.h:1807
INLINE uint8 PMU_getWDFailSts(void)
Get watchdog fail status.
Definition: pmu.h:1699
INLINE uint8 PMU_getVDDCOvervoltageWakeSts(void)
Get VDDC overvoltage wake-up status.
Definition: pmu.h:1459
INLINE uint8 PMU_getVDDCOvervoltageSts(void)
Get VDDC overvoltage status.
Definition: pmu.h:1726
INLINE void PMU_clrMON3WakeSts(void)
Clear MON3 wake-up status.
Definition: pmu.h:1572
INLINE uint8 PMU_getVDDEXTUndervoltageWakeSts(void)
Get VDDEXT undervoltage wake-up status.
Definition: pmu.h:1486
INLINE uint8 PMU_getGPIO0WakeSts(void)
Get GPIO0 wake-up status.
Definition: pmu.h:1342
INLINE uint8 PMU_getVDDEXTUndervoltageSts(void)
Get VDDEXT undervoltage status.
Definition: pmu.h:695
sint8 PMU_serviceFailSafeWatchdog(void)
Service the fail-safe watchdog.
Definition: pmu.c:150
INLINE void PMU_clrMstrSupplyUndervoltageSts(void)
Clear master supply undervoltage status.
Definition: pmu.h:1821
INLINE void PMU_clrSafeShutdownSts(void)
Clear safe shutdown status.
Definition: pmu.h:1944
INLINE uint8 PMU_getMstrClkWDFailSts(void)
Get master clock watchdog fail status.
Definition: pmu.h:1672
INLINE uint8 PMU_getVDDEXTOvertemperatureSts(void)
Get VDDEXT overtemperature status.
Definition: pmu.h:704
INLINE void PMU_clrVDDEXTOvertemperatureIntSts(void)
Clear VDDEXT overtemperature interrupt status.
Definition: pmu.h:718
INLINE uint8 PMU_getVDDCHighCurrentModeWakeSts(void)
Get VDDC high current mode wake-up status.
Definition: pmu.h:1468
INLINE uint8 PMU_getVDDPHighCurrentModeSts(void)
Get VDDP high current mode status.
Definition: pmu.h:513
INLINE uint8 PMU_getPinRstSts(void)
Get pin reset status.
Definition: pmu.h:898
INLINE sint8 PMU_setGPIOWakeCfg(uint8 u8_GPIO, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, tPMU_gpioInput e_gpioInput)
Set a GPIO wake configuration.
Definition: pmu.h:1151
INLINE void PMU_clrMstrSupplyUndervoltageRstSts(void)
Clear master supply undervoltage reset status.
Definition: pmu.h:968
INLINE void PMU_disVDDEXTUndervoltageInt(void)
Disable VDDEXT undervoltage interrupt.
Definition: pmu.h:661
INLINE void PMU_clrHPClkFailSts(void)
Clear HP clock fail status.
Definition: pmu.h:816
INLINE uint8 PMU_getFailSafeWDRstSts(void)
Get fail safe watchdog reset status.
Definition: pmu.h:907
INLINE void PMU_disResetPin(void)
Disable the Reset Pin.
Definition: pmu.h:1663
INLINE uint8 PMU_getWDTimerRstSts(void)
Get MCU watchdog timer reset status.
Definition: pmu.h:916
INLINE void PMU_clrStopExitRstSts(void)
Clear stop mode exit reset status.
Definition: pmu.h:996
INLINE void PMU_clrWDSelfTestFailSts(void)
Clear watchdog self-test fail status.
Definition: pmu.h:1842
INLINE uint8 PMU_getVDDEXTUndervoltageIntSts(void)
Get VDDEXT undervoltage interrupt status.
Definition: pmu.h:677
INLINE uint8 PMU_getVDDCOvercurrentSts(void)
Get VDDC overcurrent status.
Definition: pmu.h:795
INLINE void PMU_clrVAREFOvervoltageSts(void)
Clear VAREF overvoltage status.
Definition: pmu.h:1884
INLINE uint8 PMU_getSafeShutdownSts(void)
Get safe shutdown status.
Definition: pmu.h:1928
INLINE void PMU_clrCANWakeSts(void)
Clear CAN wake-up status.
Definition: pmu.h:1502
INLINE void PMU_clrFOOvercurrentSts(void)
Clear FO overcurrent status.
Definition: pmu.h:1919
INLINE uint8 PMU_getMON3WakeSts(void)
Get MON3 wake-up status.
Definition: pmu.h:1414
void PMU_setVDDCUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDC Undervoltage Warning Interrupt Node Pointer.
INLINE void PMU_disVDDCOvervoltageInt(void)
Disable VDDC overvoltage interrupt.
Definition: pmu.h:576
INLINE void PMU_clrVDDEXTUndervoltageWakeSts(void)
Clear VDDEXT undervoltage wake-up status.
Definition: pmu.h:1628
INLINE void PMU_clrVDDEXTUndervoltageSts(void)
Clear VDDEXT undervoltage status.
Definition: pmu.h:725
INLINE void PMU_disStopModeVDDCReduct(void)
Disable VDDC reduction in Stop Mode.
Definition: pmu.h:1137
INLINE void PMU_clrVDDPOvervoltageSts(void)
Clear VDDP overvoltage status.
Definition: pmu.h:1870
INLINE void PMU_clrSysOvertemperatureSts(void)
Clear system overtemperature status.
Definition: pmu.h:823
INLINE void PMU_clrPinRstSts(void)
Clear pin reset status.
Definition: pmu.h:1003
INLINE void PMU_clrVDDCUndervoltageRstSts(void)
Clear VDDC undervoltage reset status.
Definition: pmu.h:1045
INLINE uint8 PMU_getFailOutputSts(void)
Get fail output status.
Definition: pmu.h:1937
INLINE sint8 PMU_disWakeupSrc(uint32 u32_wakeupSrc)
Disable a wake-up source.
Definition: pmu.h:1093
INLINE void PMU_clrVDDCRegulatorTimeoutSts(void)
Clear VDDC regulator timeout status.
Definition: pmu.h:809
INLINE void PMU_clrGPIO3WakeSts(void)
Clear GPIO3 wake-up status.
Definition: pmu.h:1537
INLINE void PMU_clrCSCSelfTestFailSts(void)
Clear CSC self-test fail status.
Definition: pmu.h:1898
INLINE void PMU_clrLockupRstSts(void)
Clear ARM core lockup reset status.
Definition: pmu.h:1031
INLINE void PMU_clrVDDPRegulatorOvertemperatureSts(void)
Clear VDDP regulator overtemperature status.
Definition: pmu.h:837
sint8 PMU_initFailSafeWatchdog(void)
Initialize the fail-safe watchdog.
Definition: pmu.c:106
INLINE uint8 PMU_getVDDPUndervoltageWarnIntSts(void)
Get VDDP undervoltage warning interrupt status.
Definition: pmu.h:477
INLINE void PMU_disVDDEXTOvertemperatureInt(void)
Disable VDDEXT overtemperature interrupt.
Definition: pmu.h:668
INLINE void PMU_clrGPIO0WakeSts(void)
Clear GPIO0 wake-up status.
Definition: pmu.h:1516
INLINE uint8 PMU_getVDDPRegulatorOvertemperatureSts(void)
Get VDDP regulator overtemperature status.
Definition: pmu.h:786
INLINE void PMU_clrVDDCHighCurrentModeSts(void)
Clear VDDC high current mode status.
Definition: pmu.h:640
INLINE uint8 PMU_getVSDOvervoltageWakeSts(void)
Get VSD overvoltage wake-up status.
Definition: pmu.h:1495
INLINE void PMU_disVDDPUndervoltageWarnInt(void)
Disable VDDP undervoltage warning interrupt.
Definition: pmu.h:461
void PMU_setVDDPUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDP Undervoltage Warning Interrupt Node Pointer.
sint8 PMU_serviceFailSafeWatchdogSOW(void)
Service a Short Open Window for the watchdog.
Definition: pmu.c:203
INLINE uint8 PMU_getVDDCRegulatorTimeoutSts(void)
Get VDDC regulator timeout status.
Definition: pmu.h:750
INLINE void PMU_clrSleepExitRstSts(void)
Clear sleep mode exit reset status.
Definition: pmu.h:989
INLINE void PMU_clrVDDEXTOvertemperatureSts(void)
Clear VDDEXT overtemperature status.
Definition: pmu.h:732
sint8 PMU_init(void)
Initialize all CW registers of the PMU module.
Definition: pmu.c:50
PMU_gpioInput
This enum lists the gpio input pointer.
Definition: pmu.h:199
INLINE uint8 PMU_getMON1WakeSts(void)
Get MON1 wake-up status.
Definition: pmu.h:1396
INLINE void PMU_clrCSCEnFailSts(void)
Clear CSC enabling fail status.
Definition: pmu.h:1905
INLINE void PMU_enVDDPUndervoltageWarnInt(void)
Enable VDDP undervoltage warning interrupt.
Definition: pmu.h:447
INLINE uint8 PMU_getVDDPCurrentLimitSts(void)
Get VDDP current limitation status.
Definition: pmu.h:504
INLINE uint8 PMU_getVDDCUndervoltageWarnIntSts(void)
Get VDDC undervoltage warning interrupt status.
Definition: pmu.h:585
INLINE uint8 PMU_getVDDEXTOvertemperatureWakeSts(void)
Get VDDEXT overtemperature wake-up status.
Definition: pmu.h:1477
INLINE uint8 PMU_getPinMonitorFailSts(void)
Get pin monitor fail status.
Definition: pmu.h:1798
INLINE uint8 PMU_getVDDEXTOvertemperatureIntSts(void)
Get VDDEXT overtemperature interrupt status.
Definition: pmu.h:686
INLINE uint8 PMU_getVDDPUndervoltageRstSts(void)
Get VDDP undervoltage reset status.
Definition: pmu.h:943
INLINE void PMU_clrVDDCOvervoltageIntSts(void)
Clear VDDC overvoltage interrupt status.
Definition: pmu.h:626
INLINE void PMU_clrSoftRstSts(void)
Clear soft reset status.
Definition: pmu.h:1024
INLINE void PMU_clrVDDPOvervoltageIntSts(void)
Clear VDDP overvoltage interrupt status.
Definition: pmu.h:527
INLINE void PMU_clrMstrClkWDRstSts(void)
Clear master clock watchdog reset status.
Definition: pmu.h:975
INLINE uint8 PMU_getMON1InputSts(void)
Get MON1 input status.
Definition: pmu.h:1297
INLINE void PMU_clrVDDPUndervoltageWarnSts(void)
Clear VDDP undervoltage warning status.
Definition: pmu.h:534
INLINE uint8 PMU_getVDDCUndervoltageSts(void)
Get VDDC undervoltage status.
Definition: pmu.h:1717
INLINE uint8 PMU_getVDDPOvervoltageWakeSts(void)
Get VDDP overvoltage wake-up status.
Definition: pmu.h:1432
INLINE void PMU_clrVDDPRegulatorTimeoutSts(void)
Clear VDDP regulator timeout status.
Definition: pmu.h:802
INLINE void PMU_clrVDDPUndervoltageSts(void)
Clear VDDP undervoltage status.
Definition: pmu.h:1863
INLINE uint8 PMU_getLockupRstSts(void)
Get ARM core lockup reset status.
Definition: pmu.h:934
INLINE uint8 PMU_getCSCOvercurrentSts(void)
Get CSC overcurrent status.
Definition: pmu.h:1771
INLINE uint8 PMU_getGPIO4WakeSts(void)
Get GPIO4 wake-up status.
Definition: pmu.h:1378
INLINE uint8 PMU_getVDDCUndervoltageWarnSts(void)
Get VDDC undervoltage warning status.
Definition: pmu.h:603
INLINE void PMU_clrVDDCOvercurrentSts(void)
Clear VDDC overcurrent status.
Definition: pmu.h:844
INLINE void PMU_enFailInputPullUp(void)
Enable the failure input pull up.
Definition: pmu.h:1642
INLINE void PMU_clrSecureStackOverflowRstSts(void)
Clear secure stack overflow reset status.
Definition: pmu.h:1052
INLINE void PMU_clrVDDPOvervoltageWakeSts(void)
Clear VDDP overvoltage wake-up status.
Definition: pmu.h:1586
INLINE void PMU_clrMON2WakeSts(void)
Clear MON2 wake-up status.
Definition: pmu.h:1565
INLINE void PMU_clrGPIO1WakeSts(void)
Clear GPIO1 wake-up status.
Definition: pmu.h:1523
INLINE uint32 PMU_getWakeupSrc(void)
Get a wake-up source.
Definition: pmu.h:1123
INLINE void PMU_clrVDDEXTOvertemperatureWakeSts(void)
Clear VDDEXT overtemperature wake-up status.
Definition: pmu.h:1621
INLINE uint8 PMU_getMstrClkWDRstSts(void)
Get master clock watchdog reset status.
Definition: pmu.h:862
INLINE void PMU_clrMstrClkWDFailSts(void)
Clear master clock watchdog fail status.
Definition: pmu.h:1814
INLINE void PMU_clrPinMonitorFailSts(void)
Clear pin monitor fail status.
Definition: pmu.h:1912
INLINE uint8 PMU_getVDDCHighCurrentModeSts(void)
Get VDDC high current mode status.
Definition: pmu.h:612
INLINE void PMU_clrMstrSupplyOvervoltageSts(void)
Clear master supply overvoltage status.
Definition: pmu.h:1828
void PMU_countFailSafeWatchdog(void)
Count up since the last watchdog trigger.
Definition: pmu.c:97
void PMU_setVDDEXTOvertemperatureIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDEXT Overtemperature Interrupt Node Pointer.
enum PMU_gpioInput tPMU_gpioInput
INLINE void PMU_clrGPIO2WakeSts(void)
Clear GPIO2 wake-up status.
Definition: pmu.h:1530
INLINE uint8 PMU_getVAREFOvervoltageSts(void)
Get VAREF overvoltage status.
Definition: pmu.h:1762
INLINE void PMU_clrVDDCOvervoltageWakeSts(void)
Clear VDDC overvoltage wake-up status.
Definition: pmu.h:1607
INLINE uint8 PMU_getCSCEnFailSts(void)
Get CSC enabling fail status.
Definition: pmu.h:1789
INLINE uint8 PMU_getVDDPOvervoltageIntSts(void)
Get VDDP overvoltage interrupt status.
Definition: pmu.h:486
INLINE uint8 PMU_getVDDPUndervoltageWarnWakeSts(void)
Get VDDP undervoltage warning wake-up status.
Definition: pmu.h:1423
INLINE void PMU_clrCyclicWakeSts(void)
Clear cyclic wake-up status.
Definition: pmu.h:1509
INLINE void PMU_clrVDDCOvervoltageSts(void)
Clear VDDC overvoltage status.
Definition: pmu.h:1856
INLINE uint8 PMU_getMstrSupplyUndervoltageRstSts(void)
Get master supply undervoltage reset status.
Definition: pmu.h:853
void PMU_setVDDCOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDC Overvoltage Interrupt Node Pointer.
INLINE uint8 PMU_getSysOvertemperatureSts(void)
Get system overtemperature status.
Definition: pmu.h:768
INLINE void PMU_clrVDDPUndervoltageRstSts(void)
Clear VDDP undervoltage reset status.
Definition: pmu.h:1038
INLINE uint8 PMU_getGPIO1WakeSts(void)
Get GPIO1 wake-up status.
Definition: pmu.h:1351
INLINE uint8 PMU_getVDDPRegulatorTimeoutSts(void)
Get VDDP regulator timeout status.
Definition: pmu.h:741
INLINE void PMU_clrFailSleepExitRstSts(void)
Clear fail sleep mode exit reset status.
Definition: pmu.h:982
INLINE void PMU_disVDDCUndervoltageWarnInt(void)
Disable VDDC undervoltage warning interrupt.
Definition: pmu.h:569
INLINE void PMU_enResetPin(void)
Enable the Reset pin.
Definition: pmu.h:1649
INLINE uint8 PMU_getVDDPUndervoltageSts(void)
Get VDDP undervoltage status.
Definition: pmu.h:1735
INLINE void PMU_enVDDEXTOvertemperatureInt(void)
Enable VDDEXT overtemperature interrupt.
Definition: pmu.h:654
INLINE uint8 PMU_getStopExitRstSts(void)
Get stop mode exit reset status.
Definition: pmu.h:889
INLINE void PMU_enStopModeVDDCReduct(void)
Enable VDDC reduction in Stop Mode.
Definition: pmu.h:1130
INLINE uint8 PMU_getSeqWdFailSts(void)
Get sequential watchdog fail status.
Definition: pmu.h:777
INLINE uint8 PMU_getFailSleepExitRstSts(void)
Get fail sleep mode exit reset status.
Definition: pmu.h:871
INLINE uint8 PMU_getGPIO3WakeSts(void)
Get GPIO3 wake-up status.
Definition: pmu.h:1369
void PMU_setVDDEXTUndervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDEXT Undervoltage Interrupt Node Pointer.
@ PMU_gpioInput_P0_0
Definition: pmu.h:200
@ PMU_gpioInput_P2_0
Definition: pmu.h:215
@ PMU_gpioInput_P2_3
Definition: pmu.h:218
@ PMU_gpioInput_P0_1
Definition: pmu.h:201
@ PMU_gpioInput_P1_2
Definition: pmu.h:212
@ PMU_gpioInput_P1_1
Definition: pmu.h:211
@ PMU_gpioInput_P1_3
Definition: pmu.h:213
@ PMU_gpioInput_P0_8
Definition: pmu.h:208
@ PMU_gpioInput_P0_2
Definition: pmu.h:202
@ PMU_gpioInput_P2_9
Definition: pmu.h:224
@ PMU_gpioInput_P0_3
Definition: pmu.h:203
@ PMU_gpioInput_P2_2
Definition: pmu.h:217
@ PMU_gpioInput_P2_7
Definition: pmu.h:222
@ PMU_gpioInput_P0_4
Definition: pmu.h:204
@ PMU_gpioInput_P2_8
Definition: pmu.h:223
@ PMU_gpioInput_P0_5
Definition: pmu.h:205
@ PMU_gpioInput_P0_6
Definition: pmu.h:206
@ PMU_gpioInput_P2_4
Definition: pmu.h:219
@ PMU_gpioInput_P2_6
Definition: pmu.h:221
@ PMU_gpioInput_P1_0
Definition: pmu.h:210
@ PMU_gpioInput_P2_5
Definition: pmu.h:220
@ PMU_gpioInput_P2_1
Definition: pmu.h:216
@ PMU_gpioInput_P0_7
Definition: pmu.h:207
@ PMU_gpioInput_P1_4
Definition: pmu.h:214
@ PMU_gpioInput_P0_9
Definition: pmu.h:209
__attribute__((noreturn))
Definition: startup_tle989x.c:193
Device specific memory layout defines and features.
General type declarations.
#define ERR_LOG_CODE_PARAM_OUT_OF_RANGE
Parameter out of range.
Definition: types.h:197
#define INLINE
Definition: types.h:151
uint8_t uint8
8 bit unsigned value
Definition: types.h:204
int8_t sint8
8 bit signed value
Definition: types.h:209
uint32_t uint32
32 bit unsigned value
Definition: types.h:206