Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
MEMCTRL_Type Struct Reference

Detailed Description

MEMCTRL (MEMCTRL)

#include <tle989x.h>

Data Fields

union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFSTS: 1
 
      __IM uint32_t   SBFSTS: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DBFSTSCLR: 1
 
      __OM uint32_t   SBFSTSCLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTSC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DBFSTSSET: 1
 
      __OM uint32_t   SBFSTSSET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTSS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFA: 32
 
   }   bit
 
DBFA
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   SBFA: 32
 
   }   bit
 
SBFA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NMIDSEN: 1
 
      __IOM uint32_t   NMIPSEN: 1
 
      __IOM uint32_t   NMICDEN: 1
 
      __IOM uint32_t   NMINVM0EN: 1
 
      __IOM uint32_t   NMINVM1EN: 1
 
      __IOM uint32_t   NMIMAP0EN: 1
 
      __IOM uint32_t   NMIMAP1EN: 1
 
      __IOM uint32_t   NMIWDTEN: 1
 
      __IOM uint32_t   NMISTOFEN: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMICON
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NMIDS: 1
 
      __IM uint32_t   NMIPS: 1
 
      __IM uint32_t   NMICD: 1
 
      __IM uint32_t   NMINVM0: 1
 
      __IM uint32_t   NMINVM1: 1
 
      __IM uint32_t   NMIMAP0: 1
 
      __IM uint32_t   NMIMAP1: 1
 
      __IM uint32_t   NMIWDT: 1
 
      __IM uint32_t   NMISTOF: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIDSCLR: 1
 
      __OM uint32_t   NMIPSCLR: 1
 
      __OM uint32_t   NMICDCLR: 1
 
      __OM uint32_t   NMINVM0CLR: 1
 
      __OM uint32_t   NMINVM1CLR: 1
 
      __OM uint32_t   NMIMAP0CLR: 1
 
      __OM uint32_t   NMIMAP1CLR: 1
 
      __OM uint32_t   NMIWDTCLR: 1
 
      __OM uint32_t   NMISTOFCLR: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISRC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIDSSET: 1
 
      __OM uint32_t   NMIPSSET: 1
 
      __OM uint32_t   NMICDSET: 1
 
      __OM uint32_t   NMINVM0SET: 1
 
      __OM uint32_t   NMINVM1SET: 1
 
      __OM uint32_t   NMIMAP0SET: 1
 
      __OM uint32_t   NMIMAP1SET: 1
 
      __OM uint32_t   NMIWDTSET: 1
 
      __OM uint32_t   NMISTOFSET: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISRS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NVM0OPCIEN: 1
 
      __IOM uint32_t   NVM1OPCIEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NVM0OPC: 1
 
      __IM uint32_t   NVM1OPC: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0OPCLR: 1
 
      __OM uint32_t   NVM1OPCLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
ISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0OPSET: 1
 
      __OM uint32_t   NVM1OPSET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
ISS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NVM0_PROT_ERR: 1
 
      __IM uint32_t   NVM0_ADDR_ERR: 1
 
      __IM uint32_t   NVM0_SFR_PROT_ERR: 1
 
      __IM uint32_t   NVM0_SFR_ADDR_ERR: 1
 
      __IM uint32_t   NVM1_PROT_ERR: 1
 
      __IM uint32_t   NVM1_ADDR_ERR: 1
 
      __IM uint32_t   NVM1_SFR_PROT_ERR: 1
 
      __IM uint32_t   NVM1_SFR_ADDR_ERR: 1
 
      __IM uint32_t   ROM_PROT_ERR: 1
 
      __IM uint32_t   DSRAM_PROT_ERR: 1
 
      __IM uint32_t   PSRAM_PROT_ERR: 1
 
      uint32_t   __pad0__: 5
 
      __IM uint32_t   DSSBE: 1
 
      __IM uint32_t   PSSBE: 1
 
      __IM uint32_t   CDSBE: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM0_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM0_SFR_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM0_SFR_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM1_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM1_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM1_SFR_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM1_SFR_ADDR_ERRCLR: 1
 
      __OM uint32_t   ROM_PROT_ERRCLR: 1
 
      __OM uint32_t   DSRAM_PROT_ERRCLR: 1
 
      __OM uint32_t   PSRAM_PROT_ERRCLR: 1
 
      uint32_t   __pad0__: 5
 
      __OM uint32_t   DSSBECLR: 1
 
      __OM uint32_t   PSSBECLR: 1
 
      __OM uint32_t   CDSBECLR: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTSC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0_PROT_ERRSET: 1
 
      __OM uint32_t   NVM0_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM0_SFR_PROT_ERRSET: 1
 
      __OM uint32_t   NVM0_SFR_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM1_PROT_ERRSET: 1
 
      __OM uint32_t   NVM1_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM1_SFR_PROT_ERRSET: 1
 
      __OM uint32_t   NVM1_SFR_ADDR_ERRSET: 1
 
      __OM uint32_t   ROM_PROT_ERRSET: 1
 
      __OM uint32_t   DSRAM_PROT_ERRSET: 1
 
      __OM uint32_t   PSRAM_PROT_ERRSET: 1
 
      uint32_t   __pad0__: 5
 
      __OM uint32_t   DSSBESET: 1
 
      __OM uint32_t   PSSBESET: 1
 
      __OM uint32_t   CDSBESET: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTSS
 
__IM uint32_t RESERVED [23]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OP_STS: 32
 
   }   bit
 
NVM_OP_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OP_RESULT: 32
 
   }   bit
 
NVM_OP_RESULT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SECTORINFO: 6
 
      __IOM uint32_t   SASTATUS: 2
 
      uint32_t   __pad0__: 24
 
   }   bit
 
MEMSTAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STOF_EN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
STACK_OVF_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   STOF_ADDR_OFF_L: 13
 
      uint32_t   __pad1__: 3
 
      __IOM uint32_t   STOF_ADDR_OFF_H: 13
 
      uint32_t   __pad2__: 1
 
   }   bit
 
STACK_OVF_ADDR
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STCALIB: 26
 
      uint32_t   __pad0__: 6
 
   }   bit
 
STCALIB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTIN: 1
 
      __IOM uint32_t   WDTRS: 1
 
      __IOM uint32_t   WDTEN: 1
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   WDTPR: 1
 
      __IOM uint32_t   WDTBEN: 1
 
      uint32_t   __pad1__: 26
 
   }   bit
 
SYSWDTCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTREL: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
SYSWDTREL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   WDT: 16
 
      uint32_t   __pad0__: 16
 
   }   bit
 
SYSWDT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTWINB: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
SYSWDTWINB
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ 

union { ... } BFSTS

◆ 

union { ... } BFSTSC

◆ 

union { ... } BFSTSS

◆  [1/26]

struct { ... } bit

◆  [2/26]

struct { ... } bit

◆  [3/26]

struct { ... } bit

◆  [4/26]

struct { ... } bit

◆  [5/26]

struct { ... } bit

◆  [6/26]

struct { ... } bit

◆  [7/26]

struct { ... } bit

◆  [8/26]

struct { ... } bit

◆  [9/26]

struct { ... } bit

◆  [10/26]

struct { ... } bit

◆  [11/26]

struct { ... } bit

◆  [12/26]

struct { ... } bit

◆  [13/26]

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◆  [14/26]

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◆  [15/26]

struct { ... } bit

◆  [16/26]

struct { ... } bit

◆  [17/26]

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◆  [18/26]

struct { ... } bit

◆  [19/26]

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◆  [20/26]

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◆  [21/26]

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◆  [22/26]

struct { ... } bit

◆  [23/26]

struct { ... } bit

◆  [24/26]

struct { ... } bit

◆  [25/26]

struct { ... } bit

◆  [26/26]

struct { ... } bit

◆ CDSBE

__IM uint32_t CDSBE

[18..18] Cache Data RAM Single Bit Error Status

◆ CDSBECLR

__OM uint32_t CDSBECLR

[18..18] Cache Data RAM Single Bit Error Status Clear

◆ CDSBESET

__OM uint32_t CDSBESET

[18..18] Cache Data RAM Single Bit Error Status Set

◆ DBFA [1/2]

__IM uint32_t DBFA

[31..0] Data Bus Fault Address

◆  [2/2]

union { ... } DBFA

◆ DBFSTS

__IM uint32_t DBFSTS

[0..0] Data Bus Fault Status Valid Flag

◆ DBFSTSCLR

__OM uint32_t DBFSTSCLR

[0..0] Data Bus Fault Status Valid Flag Clear

◆ DBFSTSSET

__OM uint32_t DBFSTSSET

[0..0] Data Bus Fault Status Valid Flag Set

◆ DSRAM_PROT_ERR

__IM uint32_t DSRAM_PROT_ERR

[9..9] DSRAM Access Protection Error

◆ DSRAM_PROT_ERRCLR

__OM uint32_t DSRAM_PROT_ERRCLR

[9..9] DSRAM Access Protection Error Clear

◆ DSRAM_PROT_ERRSET

__OM uint32_t DSRAM_PROT_ERRSET

[9..9] DSRAM Access Protection Error Set

◆ DSSBE

__IM uint32_t DSSBE

[16..16] DSRAM Single Bit Error Status

◆ DSSBECLR

__OM uint32_t DSSBECLR

[16..16] DSRAM Single Bit Error Status Clear

◆ DSSBESET

__OM uint32_t DSSBESET

[16..16] DSRAM Single Bit Error Status Set

◆ 

union { ... } IEN

◆ 

union { ... } IS

◆ 

union { ... } ISC

◆ 

union { ... } ISS

◆ 

union { ... } MEMSTAT

◆ 

union { ... } MEMSTS

◆ 

union { ... } MEMSTSC

◆ 

union { ... } MEMSTSS

◆ NMICD

__IM uint32_t NMICD

[2..2] Cache Data RAM Double Bit ECC Error NMI Status

◆ NMICDCLR

__OM uint32_t NMICDCLR

[2..2] Cache Data RAM Double Bit ECC Error NMI Status Clear

◆ NMICDEN

__IOM uint32_t NMICDEN

[2..2] Cache Data RAM Double Bit ECC Error NMI Enable

◆ NMICDSET

__OM uint32_t NMICDSET

[2..2] Cache Data RAM Double Bit ECC Error NMI Status Set

◆ 

union { ... } NMICON

◆ NMIDS

__IM uint32_t NMIDS

[0..0] DSRAM Double Bit ECC Error NMI Status

◆ NMIDSCLR

__OM uint32_t NMIDSCLR

[0..0] DSRAM Double Bit ECC Error NMI Status Clear

◆ NMIDSEN

__IOM uint32_t NMIDSEN

[0..0] DSRAM Double Bit ECC Error NMI Enable

◆ NMIDSSET

__OM uint32_t NMIDSSET

[0..0] DSRAM Double Bit ECC Error NMI Status Set

◆ NMIMAP0

__IM uint32_t NMIMAP0

[5..5] NVM0 MAP Error NMI Status

◆ NMIMAP0CLR

__OM uint32_t NMIMAP0CLR

[5..5] NVM0 MAP Error NMI Status Clear

◆ NMIMAP0EN

__IOM uint32_t NMIMAP0EN

[5..5] NVM0 MAP Error NMI Enable

◆ NMIMAP0SET

__OM uint32_t NMIMAP0SET

[5..5] NVM0 MAP Error NMI Status Set

◆ NMIMAP1

__IM uint32_t NMIMAP1

[6..6] NVM1 MAP Error NMI Status

◆ NMIMAP1CLR

__OM uint32_t NMIMAP1CLR

[6..6] NVM1 MAP Error NMI Status Clear

◆ NMIMAP1EN

__IOM uint32_t NMIMAP1EN

[6..6] NVM1 MAP Error NMI Enable

◆ NMIMAP1SET

__OM uint32_t NMIMAP1SET

[6..6] NVM1 MAP Error NMI Status Set

◆ NMINVM0

__IM uint32_t NMINVM0

[3..3] NVM0 Double Bit ECC Error NMI Status

◆ NMINVM0CLR

__OM uint32_t NMINVM0CLR

[3..3] NVM 0 Double Bit ECC Error NMI Status Clear

◆ NMINVM0EN

__IOM uint32_t NMINVM0EN

[3..3] NVM0 Double Bit ECC Error NMI Enable

◆ NMINVM0SET

__OM uint32_t NMINVM0SET

[3..3] NVM 0 Double Bit ECC Error NMI Status Set

◆ NMINVM1

__IM uint32_t NMINVM1

[4..4] NVM1 Double Bit ECC Error NMI Status

◆ NMINVM1CLR

__OM uint32_t NMINVM1CLR

[4..4] NVM1 Double Bit ECC Error NMI Status Clear

◆ NMINVM1EN

__IOM uint32_t NMINVM1EN

[4..4] NVM1 Double Bit ECC Error NMI Enable

◆ NMINVM1SET

__OM uint32_t NMINVM1SET

[4..4] NVM1 Double Bit ECC Error NMI Status Set

◆ NMIPS

__IM uint32_t NMIPS

[1..1] PSRAM Double Bit ECC Error NMI Status

◆ NMIPSCLR

__OM uint32_t NMIPSCLR

[1..1] PSRAM Double Bit ECC Error NMI Status Clear

◆ NMIPSEN

__IOM uint32_t NMIPSEN

[1..1] PSRAM Double Bit ECC Error NMI Enable

◆ NMIPSSET

__OM uint32_t NMIPSSET

[1..1] PSRAM Double Bit ECC Error NMI Status Set

◆ 

union { ... } NMISR

◆ 

union { ... } NMISRC

◆ 

union { ... } NMISRS

◆ NMISTOF

__IM uint32_t NMISTOF

[8..8] Stack Overflow NMI Status

◆ NMISTOFCLR

__OM uint32_t NMISTOFCLR

[8..8] Stack Overflow NMI Status Clear

◆ NMISTOFEN

__IOM uint32_t NMISTOFEN

[8..8] Stack Overflow NMI Enable

◆ NMISTOFSET

__OM uint32_t NMISTOFSET

[8..8] Stack Overflow NMI Status Set

◆ NMIWDT

__IM uint32_t NMIWDT

[7..7] Watchdog Timer NMI Status

◆ NMIWDTCLR

__OM uint32_t NMIWDTCLR

[7..7] Watchdog Timer NMI Status Clear

◆ NMIWDTEN

__IOM uint32_t NMIWDTEN

[7..7] Watchdog Timer NMI Enable

◆ NMIWDTSET

__OM uint32_t NMIWDTSET

[7..7] Watchdog Timer NMI Status Set

◆ NVM0_ADDR_ERR

__IM uint32_t NVM0_ADDR_ERR

[1..1] NVM0 Address Protection Error

◆ NVM0_ADDR_ERRCLR

__OM uint32_t NVM0_ADDR_ERRCLR

[1..1] NVM0 Address Protection Error Clear

◆ NVM0_ADDR_ERRSET

__OM uint32_t NVM0_ADDR_ERRSET

[1..1] NVM0 Address Protection Error Set

◆ NVM0_PROT_ERR

__IM uint32_t NVM0_PROT_ERR

[0..0] NVM0 Access Protection Error

◆ NVM0_PROT_ERRCLR

__OM uint32_t NVM0_PROT_ERRCLR

[0..0] NVM0Access Protection Error Clear

◆ NVM0_PROT_ERRSET

__OM uint32_t NVM0_PROT_ERRSET

[0..0] NVM0 Access Protection Error Set

◆ NVM0_SFR_ADDR_ERR

__IM uint32_t NVM0_SFR_ADDR_ERR

[3..3] NVM0 SFR Address Protection Error

◆ NVM0_SFR_ADDR_ERRCLR

__OM uint32_t NVM0_SFR_ADDR_ERRCLR

[3..3] NVM0 SFR Address Protection Error Clear

◆ NVM0_SFR_ADDR_ERRSET

__OM uint32_t NVM0_SFR_ADDR_ERRSET

[3..3] NVM0 SFR Address Protection Error Set

◆ NVM0_SFR_PROT_ERR

__IM uint32_t NVM0_SFR_PROT_ERR

[2..2] NVM0 SFR Access Protection Error

◆ NVM0_SFR_PROT_ERRCLR

__OM uint32_t NVM0_SFR_PROT_ERRCLR

[2..2] NVM0 SFR Access Protection Error Clear

◆ NVM0_SFR_PROT_ERRSET

__OM uint32_t NVM0_SFR_PROT_ERRSET

[2..2] NVM0 SFR Access Protection Error Set

◆ NVM0OPC

__IM uint32_t NVM0OPC

[0..0] NVM0 Operation Complete Interrupt Status

◆ NVM0OPCIEN

__IOM uint32_t NVM0OPCIEN

[0..0] NVM0 Operation Complete Interrupt Enable

◆ NVM0OPCLR

__OM uint32_t NVM0OPCLR

[0..0] NVM0 Operation Complete Interrupt Status Clear

◆ NVM0OPSET

__OM uint32_t NVM0OPSET

[0..0] NVM0 Operation Complete Interrupt Status Set

◆ NVM1_ADDR_ERR

__IM uint32_t NVM1_ADDR_ERR

[5..5] NVM1 Address Protection Error

◆ NVM1_ADDR_ERRCLR

__OM uint32_t NVM1_ADDR_ERRCLR

[5..5] NVM1 Address Protection Error Clear

◆ NVM1_ADDR_ERRSET

__OM uint32_t NVM1_ADDR_ERRSET

[5..5] NVM1 Address Protection Error Set

◆ NVM1_PROT_ERR

__IM uint32_t NVM1_PROT_ERR

[4..4] NVM1 Access Protection Error

◆ NVM1_PROT_ERRCLR

__OM uint32_t NVM1_PROT_ERRCLR

[4..4] NVM1 Access Protection Error Clear

◆ NVM1_PROT_ERRSET

__OM uint32_t NVM1_PROT_ERRSET

[4..4] NVM1 Access Protection Error Set

◆ NVM1_SFR_ADDR_ERR

__IM uint32_t NVM1_SFR_ADDR_ERR

[7..7] NVM1 SFR Address Protection Error

◆ NVM1_SFR_ADDR_ERRCLR

__OM uint32_t NVM1_SFR_ADDR_ERRCLR

[7..7] NVM1 SFR Address Protection Error Clear

◆ NVM1_SFR_ADDR_ERRSET

__OM uint32_t NVM1_SFR_ADDR_ERRSET

[7..7] NVM1 SFR Address Protection Error Set

◆ NVM1_SFR_PROT_ERR

__IM uint32_t NVM1_SFR_PROT_ERR

[6..6] NVM1 SFR Access Protection Error

◆ NVM1_SFR_PROT_ERRCLR

__OM uint32_t NVM1_SFR_PROT_ERRCLR

[6..6] NVM1 SFR Access Protection Error Clear

◆ NVM1_SFR_PROT_ERRSET

__OM uint32_t NVM1_SFR_PROT_ERRSET

[6..6] NVM1 SFR Access Protection Error Set

◆ NVM1OPC

__IM uint32_t NVM1OPC

[1..1] NVM1 Operation Complete Interrupt Status

◆ NVM1OPCIEN

__IOM uint32_t NVM1OPCIEN

[1..1] NVM1 Operation Complete Interrupt Enable

◆ NVM1OPCLR

__OM uint32_t NVM1OPCLR

[1..1] NVM1 Operation Complete Interrupt Status Clear

◆ NVM1OPSET

__OM uint32_t NVM1OPSET

[1..1] NVM1 Operation Complete Interrupt Status Set

◆ 

union { ... } NVM_OP_RESULT

◆ 

union { ... } NVM_OP_STS

◆ OP_RESULT

__IOM uint32_t OP_RESULT

[31..0] NVM operation result in case of a write/erase operation in the background

◆ OP_STS

__IOM uint32_t OP_STS

[31..0] Operation Status

◆ PSRAM_PROT_ERR

__IM uint32_t PSRAM_PROT_ERR

[10..10] PSRAM Access Protection Error

◆ PSRAM_PROT_ERRCLR

__OM uint32_t PSRAM_PROT_ERRCLR

[10..10] PSRAM Access Protection Error Clear

◆ PSRAM_PROT_ERRSET

__OM uint32_t PSRAM_PROT_ERRSET

[10..10] PSRAM Access Protection Error Set

◆ PSSBE

__IM uint32_t PSSBE

[17..17] PSRAM Single Bit Error Status

◆ PSSBECLR

__OM uint32_t PSSBECLR

[17..17] PSRAM Single Bit Error Status Clear

◆ PSSBESET

__OM uint32_t PSSBESET

[17..17] PSRAM Single Bit Error Status Set

◆ reg [1/2]

__IM uint32_t reg

(@ 0x00000000) Bus Fault Status Register

(@ 0x0000000C) Data Bus Fault Address Register

(@ 0x00000010) System Bus Fault Address Register

(@ 0x00000018) NMI Status Register

(@ 0x00000028) MEMCTRL Interrupt Status Register

(@ 0x00000034) Memory Protection and Error Status Register

(@ 0x000000C0) System Watchdog Timer Value

◆ reg [2/2]

__IOM uint32_t reg

(@ 0x00000004) Bus Fault Status Clear Register

(@ 0x00000008) Bus Fault Status Set Register

(@ 0x00000014) NMI Control Register

(@ 0x0000001C) NMI Status Clear Register

(@ 0x00000020) NMI Status Set Register

(@ 0x00000024) MEMCTRL Interrupt Enable Register

(@ 0x0000002C) MEMCTRL Interrupt Status Clear Register

(@ 0x00000030) MEMCTRL Interrupt Status Set Register

(@ 0x00000038) Memory Protection and Error Status Register Clear

(@ 0x0000003C) Memory Protection and Error Status Register Set

(@ 0x0000009C) NVM Operation Status

(@ 0x000000A0) NVM operation result

(@ 0x000000A4) Memory Status Register

(@ 0x000000A8) Stack Overflow Control Register

(@ 0x000000AC) Stack Overflow Address Register

(@ 0x000000B4) System Tick Calibration Register

(@ 0x000000B8) System Watchdog Timer Control Register

(@ 0x000000BC) System Watchdog Timer Reload Register

(@ 0x000000C4) System Watchdog Window-Boundary Count

◆ RESERVED

__IM uint32_t RESERVED[23]

◆ RESERVED1

__IM uint32_t RESERVED1

◆ ROM_PROT_ERR

__IM uint32_t ROM_PROT_ERR

[8..8] ROM Access Protection Error

◆ ROM_PROT_ERRCLR

__OM uint32_t ROM_PROT_ERRCLR

[8..8] ROM Access Protection Error Clear

◆ ROM_PROT_ERRSET

__OM uint32_t ROM_PROT_ERRSET

[8..8] ROM Access Protection Error Set

◆ SASTATUS

__IOM uint32_t SASTATUS

[7..6] Service Algorithm Status

◆ SBFA [1/2]

__IM uint32_t SBFA

[31..0] System Bus Fault Address

◆  [2/2]

union { ... } SBFA

◆ SBFSTS

__IM uint32_t SBFSTS

[1..1] System Bus Fault Status Valid Flag

◆ SBFSTSCLR

__OM uint32_t SBFSTSCLR

[1..1] System Bus Fault Status Valid Flag Clear

◆ SBFSTSSET

__OM uint32_t SBFSTSSET

[1..1] System Bus Fault Status Valid Flag Set

◆ SECTORINFO

__IOM uint32_t SECTORINFO

[5..0] Sector number where the Service Algorithm is running

◆ 

union { ... } STACK_OVF_ADDR

◆ 

union { ... } STACK_OVF_CTRL

◆ STCALIB [1/2]

__IOM uint32_t STCALIB

[25..0] System Tick Calibration

◆  [2/2]

union { ... } STCALIB

◆ STOF_ADDR_OFF_H

__IOM uint32_t STOF_ADDR_OFF_H

[30..18] Higher DSRAM address offset boundary for stack overflow protection

◆ STOF_ADDR_OFF_L

__IOM uint32_t STOF_ADDR_OFF_L

[14..2] Lower DSRAM address offset boundary for stack overflow protection

◆ STOF_EN

__IOM uint32_t STOF_EN

[0..0] Stack Overflow Enable

◆ 

union { ... } SYSWDT

◆ 

union { ... } SYSWDTCON

◆ 

union { ... } SYSWDTREL

◆ 

union { ... } SYSWDTWINB

◆ WDT

__IM uint32_t WDT

[15..0] Watchdog Timer Current Value

◆ WDTBEN

__IOM uint32_t WDTBEN

[5..5] Watchdog Window-Boundary Enable

◆ WDTEN

__IOM uint32_t WDTEN

[2..2] WDT Enable

◆ WDTIN

__IOM uint32_t WDTIN

[0..0] Watchdog Timer Input Frequency Selection

◆ WDTPR

__IM uint32_t WDTPR

[4..4] Watchdog Prewarning Mode Flag

◆ WDTREL

__IOM uint32_t WDTREL

[7..0] Watchdog Timer Reload Value - Upper Watchdog Timer Byte

◆ WDTRS

__IOM uint32_t WDTRS

[1..1] WDT Refresh Start

◆ WDTWINB

__IOM uint32_t WDTWINB

[7..0] Watchdog Window-Boundary Count Value


The documentation for this struct was generated from the following file: