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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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Sigma Delta Analog/Digital Converter (SDADC)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EN0: 1 | |
__IOM uint32_t CICMODE0: 1 | |
__IOM uint32_t WFREN0: 1 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t EN1: 1 | |
__IOM uint32_t CICMODE1: 1 | |
__IOM uint32_t WFREN1: 1 | |
uint32_t __pad1__: 5 | |
__IOM uint32_t PRE: 3 | |
__IOM uint32_t DITHEREN: 1 | |
uint32_t __pad2__: 12 | |
} bit | |
} | CFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DECF0: 9 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t RESSHIFT0: 4 | |
__IOM uint32_t DECF1: 9 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t RESSHIFT1: 4 | |
} bit | |
} | CFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MCLK: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t DOUT0: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t DOUT1: 2 | |
uint32_t __pad2__: 22 | |
} bit | |
} | ALTSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IN0PSEL: 2 | |
__IOM uint32_t IN0NSEL: 2 | |
__IOM uint32_t DIN0SEL: 2 | |
__IOM uint32_t TRG0SEL: 1 | |
uint32_t __pad0__: 9 | |
__IOM uint32_t IN1PSEL: 2 | |
__IOM uint32_t IN1NSEL: 2 | |
__IOM uint32_t DIN1SEL: 2 | |
__IOM uint32_t TRG1SEL: 1 | |
uint32_t __pad1__: 9 | |
} bit | |
} | INSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RES0_EN: 1 | |
__IOM uint32_t CMP0_UP_EN: 1 | |
__IOM uint32_t CMP0_LO_EN: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t RES1_EN: 1 | |
__IOM uint32_t CMP1_UP_EN: 1 | |
__IOM uint32_t CMP1_LO_EN: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | IEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RES0_IS: 1 | |
__IOM uint32_t CMP0_UP_IS: 1 | |
__IOM uint32_t CMP0_LO_IS: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t RES1_IS: 1 | |
__IOM uint32_t CMP1_UP_IS: 1 | |
__IOM uint32_t CMP1_LO_IS: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | IS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t RES0_ISC: 1 | |
__OM uint32_t CMP0_UP_ISC: 1 | |
__OM uint32_t CMP0_LO_ISC: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t RES1_ISC: 1 | |
__OM uint32_t CMP1_UP_ISC: 1 | |
__OM uint32_t CMP1_LO_ISC: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | ISR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t RES0_ISS: 1 | |
__OM uint32_t CMP0_UP_ISS: 1 | |
__OM uint32_t CMP0_LO_ISS: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t RES1_ISS: 1 | |
__OM uint32_t CMP1_UP_ISS: 1 | |
__OM uint32_t CMP1_LO_ISS: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | ISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RES0_INP: 1 | |
__IOM uint32_t CMP0_UP_INP: 1 | |
__IOM uint32_t CMP0_LO_INP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t RES1_INP: 1 | |
__IOM uint32_t CMP1_UP_INP: 1 | |
__IOM uint32_t CMP1_LO_INP: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | INP |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EN: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | SUSCTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t STAT: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | SUSSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 9 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
__IOM uint32_t UPLO_OUTSEL: 2 | |
__IOM uint32_t UPPER: 9 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMP0_CTRL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 9 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
__IOM uint32_t UPLO_OUTSEL: 2 | |
__IOM uint32_t UPPER: 9 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMP1_CTRL |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 16 | |
__IM uint32_t TIMVAL: 9 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALCNT: 3 | |
__IM uint32_t RESVALID: 1 | |
} bit | |
} | RES0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 16 | |
__IM uint32_t TIMVAL: 9 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALCNT: 3 | |
__IM uint32_t RESVALID: 1 | |
} bit | |
} | RES1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t TIMVAL: 9 | |
uint32_t __pad0__: 23 | |
} bit | |
} | CTIM0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t TIMVAL: 9 | |
uint32_t __pad0__: 23 | |
} bit | |
} | CTIM1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DITH_VOLT_SEL: 4 | |
uint32_t __pad0__: 28 | |
} bit | |
} | DITHCFG |
__IM uint32_t | RESERVED |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__OM uint32_t CMP0_UP_SC: 1 | |
__OM uint32_t CMP0_LO_SC: 1 | |
__OM uint32_t WFR0_SC: 1 | |
uint32_t __pad1__: 1 | |
__OM uint32_t CMP1_UP_SC: 1 | |
__OM uint32_t CMP1_LO_SC: 1 | |
__OM uint32_t WFR1_SC: 1 | |
uint32_t __pad2__: 24 | |
} bit | |
} | STSR |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CMP0_UP_STS: 1 | |
__IOM uint32_t CMP0_LO_STS: 1 | |
__IOM uint32_t WFR0_STS: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t CMP1_UP_STS: 1 | |
__IOM uint32_t CMP1_LO_STS: 1 | |
__IOM uint32_t WFR1_STS: 1 | |
uint32_t __pad2__: 24 | |
} bit | |
} | STS |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__OM uint32_t CMP0_UP_SS: 1 | |
__OM uint32_t CMP0_LO_SS: 1 | |
__OM uint32_t WFR0_SS: 1 | |
uint32_t __pad1__: 1 | |
__OM uint32_t CMP1_UP_SS: 1 | |
__OM uint32_t CMP1_LO_SS: 1 | |
__OM uint32_t WFR1_SS: 1 | |
uint32_t __pad2__: 24 | |
} bit | |
} | STSS |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
union { ... } ALTSEL |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
union { ... } CFG0 |
union { ... } CFG1 |
__IOM uint32_t CICMODE0 |
[1..1] CIC Filter Mode channel 0
__IOM uint32_t CICMODE1 |
[9..9] CIC Filter Mode channel 1
union { ... } CMP0_CTRL |
__IOM uint32_t CMP0_LO_EN |
[2..2] Lower compare level Interrupt channel 0
__IOM uint32_t CMP0_LO_INP |
[2..2] Lower Compare Level Interupt Pointer channel 0
__IOM uint32_t CMP0_LO_IS |
[2..2] Lower compare level interupt channel 0
__OM uint32_t CMP0_LO_ISC |
[2..2] Lower Compare Level Interupt clear channel 0
__OM uint32_t CMP0_LO_ISS |
[2..2] Lower Compare Level Interrupt set channel 0
__OM uint32_t CMP0_LO_SC |
[2..2] Lower compare level Status clear channel 0
__OM uint32_t CMP0_LO_SS |
[2..2] Lower compare level Status set channel 0
__IOM uint32_t CMP0_LO_STS |
[2..2] Lower compare level Status channel 0
__IOM uint32_t CMP0_UP_EN |
[1..1] Upper Compare Level Interrupt channel 0
__IOM uint32_t CMP0_UP_INP |
[1..1] Upper Compare Level Interupt Pointer channel 0
__IOM uint32_t CMP0_UP_IS |
[1..1] Upper Compare level Interupt channel 0
__OM uint32_t CMP0_UP_ISC |
[1..1] Upper Compare Level Interupt clear channel 0
__OM uint32_t CMP0_UP_ISS |
[1..1] Upper Compare Level Interupt set channel 0
__OM uint32_t CMP0_UP_SC |
[1..1] Upper Compare level Status clear channel 0
__OM uint32_t CMP0_UP_SS |
[1..1] Upper Compare level Status set channel 0
__IOM uint32_t CMP0_UP_STS |
[1..1] Upper Compare level Status channel 0
union { ... } CMP1_CTRL |
__IOM uint32_t CMP1_LO_EN |
[6..6] Lower compare level Interrupt channel 1
__IOM uint32_t CMP1_LO_INP |
[6..6] Lower Compare Level Interupt Pointer channel 1
__IOM uint32_t CMP1_LO_IS |
[6..6] Lower compare level interupt channel 1
__OM uint32_t CMP1_LO_ISC |
[6..6] Lower Compare Level Interupt clear channel 1
__OM uint32_t CMP1_LO_ISS |
[6..6] Lower Compare Level Interupt set channel 1
__OM uint32_t CMP1_LO_SC |
[6..6] Lower compare level Status clear channel 1
__OM uint32_t CMP1_LO_SS |
[6..6] Lower compare level Status set channel 1
__IOM uint32_t CMP1_LO_STS |
[6..6] Lower compare level Status channel 1
__IOM uint32_t CMP1_UP_EN |
[5..5] Upper Compare Level Interrupt channel 1
__IOM uint32_t CMP1_UP_INP |
[5..5] Upper Compare Level Interupt Pointer channel 1
__IOM uint32_t CMP1_UP_IS |
[5..5] Upper Compare level Interupt channel 1
__OM uint32_t CMP1_UP_ISC |
[5..5] Upper Compare Level Interupt clear channel 1
__OM uint32_t CMP1_UP_ISS |
[5..5] Upper Compare Level Interupt set channel 1
__OM uint32_t CMP1_UP_SC |
[5..5] Upper Compare level Status clear channel 1
__OM uint32_t CMP1_UP_SS |
[5..5] Upper Compare level Status set channel 1
__IOM uint32_t CMP1_UP_STS |
[5..5] Upper Compare level Status channel 1
union { ... } CTIM0 |
union { ... } CTIM1 |
__IOM uint32_t DECF0 |
[8..0] Decimation Factor channel 0
__IOM uint32_t DECF1 |
[24..16] Decimation factor channel 1
__IOM uint32_t DIN0SEL |
[5..4] Selection of digital input of channel 0
__IOM uint32_t DIN1SEL |
[21..20] External Digital Input Selection 1
__IOM uint32_t DITH_VOLT_SEL |
[3..0] Dither voltage Selection
union { ... } DITHCFG |
__IOM uint32_t DITHEREN |
[19..19] Dithering of SD ADC Clock for channel 0/1
__IOM uint32_t DOUT0 |
[5..4] DOUT0 mapping
__IOM uint32_t DOUT1 |
[9..8] DOUT1 mapping
__IOM uint32_t EN |
[0..0] Suspend Mode Enable
__IOM uint32_t EN0 |
[0..0] Enable Channel 0
__IOM uint32_t EN1 |
[8..8] Enable Channel 1
__IOM uint32_t HYST_LO |
[13..12] Hysteresis setting for lower compare threshold channel 0
[13..12] Hysteresis setting for lower compare threshold channel 1
__IOM uint32_t HYST_UP |
[29..28] Hysteresis setting for upper compare threshold channel 0
[29..28] Hysteresis setting for upper compare threshold channel 1
union { ... } IEN |
__IOM uint32_t IN0NSEL |
[3..2] Selection for negative analog input of channel 0
__IOM uint32_t IN0PSEL |
[1..0] Selection for positive analog input of channel 0
__IOM uint32_t IN1NSEL |
[19..18] INN Input Select 1
__IOM uint32_t IN1PSEL |
[17..16] Selection for positive analog input of channel 0
union { ... } INP |
union { ... } INSEL |
union { ... } IS |
union { ... } ISR |
union { ... } ISS |
__IOM uint32_t LOWER |
[8..0] Lower Compare Level for channel 0
[8..0] Lower Compare Level for channel 1
__IOM uint32_t MCLK |
[1..0] MCLK output mapping
__IOM uint32_t MODE |
[31..30] Compare Mode channel 0
[31..30] Compare Mode channel 1
__IOM uint32_t PRE |
[18..16] Prescaler for Modulator and CIC clock
__IOM uint32_t reg |
(@ 0x00000000) Configuration Register 0
(@ 0x00000004) Configuration Register 1
(@ 0x00000008) Alternate function selection
(@ 0x0000000C) Input Port Selection
(@ 0x00000010) Interrupt Enable Register
(@ 0x00000014) Event Register
(@ 0x00000018) Event Clear Register
(@ 0x0000001C) Event Set Register
(@ 0x00000020) Interrupt Node Pointer
(@ 0x00000024) Suspend Control
(@ 0x0000002C) Compare Channel 0 Control Register
(@ 0x00000030) Compare Channel 1 Control Register
(@ 0x00000044) Dither Configuration Register
(@ 0x0000004C) Status Clear Register
(@ 0x00000050) Status Register
(@ 0x00000054) Status Set Register
__IM uint32_t reg |
(@ 0x00000028) Suspend Status
(@ 0x00000034) Result Register channel 0
(@ 0x00000038) Result Register channel 1
(@ 0x0000003C) Captured Timestamp channel 0
(@ 0x00000040) Captured Timestamp channel 1
union { ... } RES0 |
__IOM uint32_t RES0_EN |
[0..0] Result interrupt channel 0
__IOM uint32_t RES0_INP |
[0..0] Result Interupt Node Pointer channel 0
__IOM uint32_t RES0_IS |
[0..0] Result Interupt channel 0
__OM uint32_t RES0_ISC |
[0..0] Result Interupt clear channel 0
__OM uint32_t RES0_ISS |
[0..0] Result Interupt set channel 0
union { ... } RES1 |
__IOM uint32_t RES1_EN |
[4..4] Result interrupt channel 1
__IOM uint32_t RES1_INP |
[4..4] Result Interupt Node Pointer channel 1
__IOM uint32_t RES1_IS |
[4..4] Result interupt channel 1
__OM uint32_t RES1_ISC |
[4..4] Result Interupt clear channel 1
__OM uint32_t RES1_ISS |
[4..4] Result Interupt set channel 1
__IM uint32_t RESERVED |
__IOM uint32_t RESSHIFT0 |
[15..12] Result Left shift channel 0
__IOM uint32_t RESSHIFT1 |
[31..28] Result Left shift channel 1
__IM uint32_t RESULT |
[15..0] Result Register 2s complement
__IM uint32_t RESVALID |
[31..31] Result valid
__IM uint32_t STAT |
[0..0] Suspend Status
union { ... } STS |
union { ... } STSR |
union { ... } STSS |
union { ... } SUSCTR |
union { ... } SUSSTAT |
__IM uint32_t TIMVAL |
[24..16] Timestamp Value
[8..0] Captured Timestamp Value
__IOM uint32_t TRG0SEL |
[6..6] Trigger Event Selection
__IOM uint32_t TRG1SEL |
[22..22] Trigger Event Selection
__IOM uint32_t UPLO_OUTSEL |
[15..14] Signal output selection for UPLO output of channel 0
[15..14] Signal output selection for UPLO output of channel 1
__IOM uint32_t UPPER |
[24..16] Upper Compare Level for channel 0
[24..16] Upper Compare Level for channel 1
__IM uint32_t VALCNT |
[30..28] Valid Counter
__OM uint32_t WFR0_SC |
[3..3] Wait for Read Status clear channel 0
__OM uint32_t WFR0_SS |
[3..3] Wait for Read Status set channel 0
__IOM uint32_t WFR0_STS |
[3..3] Result discarded channel 0
__OM uint32_t WFR1_SC |
[7..7] Wait for Read Status clear channel 1
__OM uint32_t WFR1_SS |
[7..7] Wait for Read Status set channel 1
__IOM uint32_t WFR1_STS |
[7..7] Result discarded channel 1
__IOM uint32_t WFREN0 |
[2..2] Wait for Read of Result Register Channel 0
__IOM uint32_t WFREN1 |
[10..10] Wait for Read of Result Register Channel 1