Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
PLL_Type Struct Reference

Detailed Description

PLL (PLL)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NDIV: 8
 
      __IOM uint32_t   PDIV: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   K2DIV: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   INSEL: 2
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   FREERUN: 1
 
      __OM uint32_t   RESLD: 1
 
      uint32_t   __pad3__: 5
 
      __IOM uint32_t   PLLEN: 1
 
   }   bit
 
CON0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NDIV: 8
 
      __IOM uint32_t   PDIV: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   K2DIV: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   INSEL: 2
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   FREERUN: 1
 
      __OM uint32_t   RESLD: 1
 
      uint32_t   __pad3__: 5
 
      __IOM uint32_t   PLLEN: 1
 
   }   bit
 
CON1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SPEN0: 1
 
      uint32_t   __pad0__: 3
 
      __IOM uint32_t   SPRANGE0: 2
 
      __IOM uint32_t   SPUPVAL0: 10
 
      __IOM uint32_t   SPEN1: 1
 
      uint32_t   __pad1__: 3
 
      __IOM uint32_t   SPRANGE1: 2
 
      __IOM uint32_t   SPUPVAL1: 10
 
   }   bit
 
SPCTR
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   LCK0: 1
 
      __IM uint32_t   LCK1: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   PLL0_LOL_STS: 1
 
      __IM uint32_t   PLL1_LOL_STS: 1
 
      uint32_t   __pad1__: 10
 
      __IM uint32_t   OSCSEL_STAT0: 1
 
      __IM uint32_t   OSCSEL_STAT1: 1
 
      uint32_t   __pad2__: 14
 
   }   bit
 
STAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PLL0_LOL_STSCLR: 1
 
      __OM uint32_t   PLL1_LOL_STSCLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
STATC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PLL0_LOL_STSSET: 1
 
      __OM uint32_t   PLL1_LOL_STSSET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
STATS
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆  [1/6]

struct { ... } bit

◆  [2/6]

struct { ... } bit

◆  [3/6]

struct { ... } bit

◆  [4/6]

struct { ... } bit

◆  [5/6]

struct { ... } bit

◆  [6/6]

struct { ... } bit

◆ 

union { ... } CON0

◆ 

union { ... } CON1

◆ FREERUN

__IOM uint32_t FREERUN

[24..24] Free-running Mode Select

[24..24] Freerunning Mode Select

◆ INSEL

__IOM uint32_t INSEL

[21..20] PLL Reference Clock Select

◆ K2DIV

__IOM uint32_t K2DIV

[18..16] K2-Divider Setting

◆ LCK0

__IM uint32_t LCK0

[0..0] Lock Status PLL 0

◆ LCK1

__IM uint32_t LCK1

[1..1] Lock Status PLL1

◆ NDIV

__IOM uint32_t NDIV

[7..0] N-Divider Setting

◆ OSCSEL_STAT0

__IM uint32_t OSCSEL_STAT0

[16..16] Oscillator Select Status PLL0

◆ OSCSEL_STAT1

__IM uint32_t OSCSEL_STAT1

[17..17] Oscillator Select Status PLL1

◆ PDIV

__IOM uint32_t PDIV

[13..8] P-Divider Setting

◆ PLL0_LOL_STS

__IM uint32_t PLL0_LOL_STS

[4..4] PLL0 Loss Of Lock Status

◆ PLL0_LOL_STSCLR

__OM uint32_t PLL0_LOL_STSCLR

[0..0] PLL0 Loss Of Lock Status Clear

◆ PLL0_LOL_STSSET

__OM uint32_t PLL0_LOL_STSSET

[0..0] PLL0 Loss Of Lock Status Set

◆ PLL1_LOL_STS

__IM uint32_t PLL1_LOL_STS

[5..5] PLL1 Loss Of Lock Status

◆ PLL1_LOL_STSCLR

__OM uint32_t PLL1_LOL_STSCLR

[1..1] PLL1 Loss Of Lock Status Clear

◆ PLL1_LOL_STSSET

__OM uint32_t PLL1_LOL_STSSET

[1..1] PLL1 Loss Of Lock Status Set

◆ PLLEN

__IOM uint32_t PLLEN

[31..31] PLL Enable

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) PLL0 Control Register

(@ 0x00000004) PLL1 Control Register

(@ 0x00000008) PLL NDIV Spread Control Register

(@ 0x00000010) PLL Status Clear Register

(@ 0x00000014) PLL Status Set Register

◆ reg [2/2]

__IM uint32_t reg

(@ 0x0000000C) PLL Status Register

◆ RESLD

__OM uint32_t RESLD

[25..25] Lock Detection Reset

◆ 

union { ... } SPCTR

◆ SPEN0

__IOM uint32_t SPEN0

[0..0] NDIV PLL0 Spread Enable

◆ SPEN1

__IOM uint32_t SPEN1

[16..16] NDIV PLL1 Spread Enable

◆ SPRANGE0

__IOM uint32_t SPRANGE0

[5..4] PLL0 NDIV Spread Range Value

◆ SPRANGE1

__IOM uint32_t SPRANGE1

[21..20] PLL1 NDIV Spread Range Value

◆ SPUPVAL0

__IOM uint32_t SPUPVAL0

[15..6] PLL0 NDIV Spread Update Interval

◆ SPUPVAL1

__IOM uint32_t SPUPVAL1

[31..22] PLL1 NDIV Spread Update Interval

◆ 

union { ... } STAT

◆ 

union { ... } STATC

◆ 

union { ... } STATS

The documentation for this struct was generated from the following file: