Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
int.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
26 /* Generated by generate_functions_02_xlsx2func.py, version 0.9.0 on 20. Oct 2020
27  * from File 'cpu.xlsx', version 0.1.0
28  */
29 
30 /*******************************************************************************
31 ** Author(s) Identity **
32 ********************************************************************************
33 ** Initials Name **
34 ** ---------------------------------------------------------------------------**
35 ** JO Julia Ott **
36 ** BG Blandine Guillot **
37 ** DM Daniel Mysliwitz **
38 *******************************************************************************/
39 
40 /*******************************************************************************
41 ** Revision Control History **
42 ********************************************************************************
43 ** V0.1.0: 2019-10-28, DM: Initial version **
44 ** V0.2.0: 2020-04-28, BG: Updated revision history format **
45 ** V0.2.1: 2020-10-20, JO: EP-533: Added functions to set the priority of **
46 ** NVIC nodes **
47 ** Added functions to enable and disable NVIC nodes **
48 ** V0.2.2: 2020-11-12, JO: EP-590: Removed \param none and \return none to **
49 ** avoid doxygen warning **
50 ** V0.2.3: 2020-11-20, BG: EP-610: Corrected MISRA 2012 errors **
51 ** V0.2.4: 2020-11-27, BG: EP-627: Initialized registers for CANTRX **
52 ** EP-598: Initialized registers for ARVG **
53 ** V0.2.5: 2020-12-03, BG: EP-633: Added missing register for MON in the **
54 ** initialization **
55 ** V0.2.6: 2020-12-17, BG: EP-599: Added condition with UC_FEATURE_SDADC **
56 ** for init of SDADC int. **
57 ** V0.2.7: 2020-12-18, BG: EP-607: Removed precompiler condition for ADC2 **
58 ** V0.2.8: 2021-06-02, BG: EP-813: Corrected assigned values to PMU, CANTRX **
59 ** ARVG and CSACSC interrupt status clear registers **
60 ** V0.2.9: 2021-10-12, JO: EP-954: Added include of tle_variants.h to **
61 ** apply condition with UC_FEATURE_SDADC **
62 ** V0.3.0: 2021-10-22, BG: EP-964: Removed registers CONVSTATCLR for ADC1/2 **
63 ** in INT_init() **
64 ** V0.3.1: 2021-11-12, JO: EP-937: Updated copyright and branding **
65 ** V0.3.2: 2024-10-28, JO: EP-1531: Added initialization of SHPR1 adn SHPR3 **
66 ** V0.3.3: 2024-11-05, JO: EP-1494: Updated license **
67 *******************************************************************************/
68 
69 #ifndef _INT_H
70 #define _INT_H
71 
72 /*******************************************************************************
73 ** Includes **
74 *******************************************************************************/
75 
76 #include "types.h"
77 #include "tle_variants.h"
78 #include "tle989x.h"
79 #include "isr_defines.h"
80 #include "ccu7_defines.h"
81 
82 /*******************************************************************************
83 ** Global Macro Declarations **
84 *******************************************************************************/
85 
86 /*******************************************************************************
87 ** Global Type Declarations **
88 *******************************************************************************/
89 
90 /*******************************************************************************
91 ** Global Function Declarations **
92 *******************************************************************************/
93 INLINE void NVIC_disIRQ0(void);
94 INLINE void NVIC_disIRQ1(void);
95 INLINE void NVIC_disIRQ2(void);
96 INLINE void NVIC_disIRQ3(void);
97 INLINE void NVIC_disIRQ4(void);
98 INLINE void NVIC_disIRQ5(void);
99 INLINE void NVIC_disIRQ6(void);
100 INLINE void NVIC_disIRQ7(void);
101 INLINE void NVIC_disIRQ8(void);
102 INLINE void NVIC_disIRQ9(void);
103 INLINE void NVIC_disIRQ10(void);
104 INLINE void NVIC_disIRQ11(void);
105 INLINE void NVIC_disIRQ12(void);
106 INLINE void NVIC_disIRQ13(void);
107 INLINE void NVIC_disIRQ14(void);
108 INLINE void NVIC_disIRQ15(void);
109 INLINE void NVIC_disIRQ16(void);
110 INLINE void NVIC_disIRQ17(void);
111 INLINE void NVIC_disIRQ18(void);
112 INLINE void NVIC_disIRQ19(void);
113 INLINE void NVIC_disIRQ20(void);
114 INLINE void NVIC_disIRQ21(void);
115 INLINE void NVIC_disIRQ22(void);
116 INLINE void NVIC_disIRQ23(void);
117 INLINE void NVIC_disIRQ24(void);
118 INLINE void NVIC_disIRQ25(void);
119 INLINE void NVIC_disIRQ26(void);
120 INLINE void NVIC_disIRQ27(void);
121 INLINE void NVIC_disIRQ28(void);
122 INLINE void NVIC_disIRQ29(void);
123 INLINE void NVIC_disIRQ30(void);
124 INLINE void NVIC_disIRQ31(void);
125 INLINE void NVIC_setIRQ0Priority(uint8 u8_value);
126 INLINE void NVIC_setIRQ1Priority(uint8 u8_value);
127 INLINE void NVIC_setIRQ2Priority(uint8 u8_value);
128 INLINE void NVIC_setIRQ3Priority(uint8 u8_value);
129 INLINE void NVIC_setIRQ4Priority(uint8 u8_value);
130 INLINE void NVIC_setIRQ5Priority(uint8 u8_value);
131 INLINE void NVIC_setIRQ6Priority(uint8 u8_value);
132 INLINE void NVIC_setIRQ7Priority(uint8 u8_value);
133 INLINE void NVIC_setIRQ8Priority(uint8 u8_value);
134 INLINE void NVIC_setIRQ9Priority(uint8 u8_value);
135 INLINE void NVIC_setIRQ10Priority(uint8 u8_value);
136 INLINE void NVIC_setIRQ11Priority(uint8 u8_value);
137 INLINE void NVIC_setIRQ12Priority(uint8 u8_value);
138 INLINE void NVIC_setIRQ13Priority(uint8 u8_value);
139 INLINE void NVIC_setIRQ14Priority(uint8 u8_value);
140 INLINE void NVIC_setIRQ15Priority(uint8 u8_value);
141 INLINE void NVIC_setIRQ16Priority(uint8 u8_value);
142 INLINE void NVIC_setIRQ17Priority(uint8 u8_value);
143 INLINE void NVIC_setIRQ18Priority(uint8 u8_value);
144 INLINE void NVIC_setIRQ19Priority(uint8 u8_value);
145 INLINE void NVIC_setIRQ20Priority(uint8 u8_value);
146 INLINE void NVIC_setIRQ21Priority(uint8 u8_value);
147 INLINE void NVIC_setIRQ22Priority(uint8 u8_value);
148 INLINE void NVIC_setIRQ23Priority(uint8 u8_value);
149 INLINE void NVIC_setIRQ24Priority(uint8 u8_value);
150 INLINE void NVIC_setIRQ25Priority(uint8 u8_value);
151 INLINE void NVIC_setIRQ26Priority(uint8 u8_value);
152 INLINE void NVIC_setIRQ27Priority(uint8 u8_value);
153 INLINE void NVIC_setIRQ28Priority(uint8 u8_value);
154 INLINE void NVIC_setIRQ29Priority(uint8 u8_value);
155 INLINE void NVIC_setIRQ30Priority(uint8 u8_value);
156 INLINE void NVIC_setIRQ31Priority(uint8 u8_value);
157 INLINE void NVIC_enIRQ0(void);
158 INLINE void NVIC_enIRQ1(void);
159 INLINE void NVIC_enIRQ2(void);
160 INLINE void NVIC_enIRQ3(void);
161 INLINE void NVIC_enIRQ4(void);
162 INLINE void NVIC_enIRQ5(void);
163 INLINE void NVIC_enIRQ6(void);
164 INLINE void NVIC_enIRQ7(void);
165 INLINE void NVIC_enIRQ8(void);
166 INLINE void NVIC_enIRQ9(void);
167 INLINE void NVIC_enIRQ10(void);
168 INLINE void NVIC_enIRQ11(void);
169 INLINE void NVIC_enIRQ12(void);
170 INLINE void NVIC_enIRQ13(void);
171 INLINE void NVIC_enIRQ14(void);
172 INLINE void NVIC_enIRQ15(void);
173 INLINE void NVIC_enIRQ16(void);
174 INLINE void NVIC_enIRQ17(void);
175 INLINE void NVIC_enIRQ18(void);
176 INLINE void NVIC_enIRQ19(void);
177 INLINE void NVIC_enIRQ20(void);
178 INLINE void NVIC_enIRQ21(void);
179 INLINE void NVIC_enIRQ22(void);
180 INLINE void NVIC_enIRQ23(void);
181 INLINE void NVIC_enIRQ24(void);
182 INLINE void NVIC_enIRQ25(void);
183 INLINE void NVIC_enIRQ26(void);
184 INLINE void NVIC_enIRQ27(void);
185 INLINE void NVIC_enIRQ28(void);
186 INLINE void NVIC_enIRQ29(void);
187 INLINE void NVIC_enIRQ30(void);
188 INLINE void NVIC_enIRQ31(void);
189 void INT_init(void);
190 
191 /*******************************************************************************
192 ** Global Inline Function Definitions **
193 *******************************************************************************/
197 {
198  CPU->NVIC_ICER.bit.IRQCLREN0 = 0u;
199 }
200 
204 {
205  CPU->NVIC_ICER.bit.IRQCLREN1 = 0u;
206 }
207 
211 {
212  CPU->NVIC_ICER.bit.IRQCLREN2 = 0u;
213 }
214 
218 {
219  CPU->NVIC_ICER.bit.IRQCLREN3 = 0u;
220 }
221 
225 {
226  CPU->NVIC_ICER.bit.IRQCLREN4 = 0u;
227 }
228 
232 {
233  CPU->NVIC_ICER.bit.IRQCLREN5 = 0u;
234 }
235 
239 {
240  CPU->NVIC_ICER.bit.IRQCLREN6 = 0u;
241 }
242 
246 {
247  CPU->NVIC_ICER.bit.IRQCLREN7 = 0u;
248 }
249 
253 {
254  CPU->NVIC_ICER.bit.IRQCLREN8 = 0u;
255 }
256 
260 {
261  CPU->NVIC_ICER.bit.IRQCLREN9 = 0u;
262 }
263 
267 {
268  CPU->NVIC_ICER.bit.IRQCLREN10 = 0u;
269 }
270 
274 {
275  CPU->NVIC_ICER.bit.IRQCLREN11 = 0u;
276 }
277 
281 {
282  CPU->NVIC_ICER.bit.IRQCLREN12 = 0u;
283 }
284 
288 {
289  CPU->NVIC_ICER.bit.IRQCLREN13 = 0u;
290 }
291 
295 {
296  CPU->NVIC_ICER.bit.IRQCLREN14 = 0u;
297 }
298 
302 {
303  CPU->NVIC_ICER.bit.IRQCLREN15 = 0u;
304 }
305 
309 {
310  CPU->NVIC_ICER.bit.IRQCLREN16 = 0u;
311 }
312 
316 {
317  CPU->NVIC_ICER.bit.IRQCLREN17 = 0u;
318 }
319 
323 {
324  CPU->NVIC_ICER.bit.IRQCLREN18 = 0u;
325 }
326 
330 {
331  CPU->NVIC_ICER.bit.IRQCLREN19 = 0u;
332 }
333 
337 {
338  CPU->NVIC_ICER.bit.IRQCLREN20 = 0u;
339 }
340 
344 {
345  CPU->NVIC_ICER.bit.IRQCLREN21 = 0u;
346 }
347 
351 {
352  CPU->NVIC_ICER.bit.IRQCLREN22 = 0u;
353 }
354 
358 {
359  CPU->NVIC_ICER.bit.IRQCLREN23 = 0u;
360 }
361 
365 {
366  CPU->NVIC_ICER.bit.IRQCLREN24 = 0u;
367 }
368 
372 {
373  CPU->NVIC_ICER.bit.IRQCLREN25 = 0u;
374 }
375 
379 {
380  CPU->NVIC_ICER.bit.IRQCLREN26 = 0u;
381 }
382 
386 {
387  CPU->NVIC_ICER.bit.IRQCLREN27 = 0u;
388 }
389 
393 {
394  CPU->NVIC_ICER.bit.IRQCLREN28 = 0u;
395 }
396 
400 {
401  CPU->NVIC_ICER.bit.IRQCLREN29 = 0u;
402 }
403 
407 {
408  CPU->NVIC_ICER.bit.IRQCLREN30 = 0u;
409 }
410 
414 {
415  CPU->NVIC_ICER.bit.IRQCLREN31 = 0u;
416 }
417 
423 {
424  CPU->NVIC_IPR0.bit.PRI_N0 = u8_value;
425 }
426 
432 {
433  CPU->NVIC_IPR0.bit.PRI_N1 = u8_value;
434 }
435 
441 {
442  CPU->NVIC_IPR0.bit.PRI_N2 = u8_value;
443 }
444 
450 {
451  CPU->NVIC_IPR0.bit.PRI_N3 = u8_value;
452 }
453 
459 {
460  CPU->NVIC_IPR1.bit.PRI_N4 = u8_value;
461 }
462 
468 {
469  CPU->NVIC_IPR1.bit.PRI_N5 = u8_value;
470 }
471 
477 {
478  CPU->NVIC_IPR1.bit.PRI_N6 = u8_value;
479 }
480 
486 {
487  CPU->NVIC_IPR1.bit.PRI_N7 = u8_value;
488 }
489 
495 {
496  CPU->NVIC_IPR2.bit.PRI_N8 = u8_value;
497 }
498 
504 {
505  CPU->NVIC_IPR2.bit.PRI_N9 = u8_value;
506 }
507 
513 {
514  CPU->NVIC_IPR2.bit.PRI_N10 = u8_value;
515 }
516 
522 {
523  CPU->NVIC_IPR2.bit.PRI_N11 = u8_value;
524 }
525 
531 {
532  CPU->NVIC_IPR3.bit.PRI_N12 = u8_value;
533 }
534 
540 {
541  CPU->NVIC_IPR3.bit.PRI_N13 = u8_value;
542 }
543 
549 {
550  CPU->NVIC_IPR3.bit.PRI_N14 = u8_value;
551 }
552 
558 {
559  CPU->NVIC_IPR3.bit.PRI_N15 = u8_value;
560 }
561 
567 {
568  CPU->NVIC_IPR4.bit.PRI_N16 = u8_value;
569 }
570 
576 {
577  CPU->NVIC_IPR4.bit.PRI_N17 = u8_value;
578 }
579 
585 {
586  CPU->NVIC_IPR4.bit.PRI_N18 = u8_value;
587 }
588 
594 {
595  CPU->NVIC_IPR4.bit.PRI_N19 = u8_value;
596 }
597 
603 {
604  CPU->NVIC_IPR5.bit.PRI_N20 = u8_value;
605 }
606 
612 {
613  CPU->NVIC_IPR5.bit.PRI_N21 = u8_value;
614 }
615 
621 {
622  CPU->NVIC_IPR5.bit.PRI_N22 = u8_value;
623 }
624 
630 {
631  CPU->NVIC_IPR5.bit.PRI_N23 = u8_value;
632 }
633 
639 {
640  CPU->NVIC_IPR6.bit.PRI_N24 = u8_value;
641 }
642 
648 {
649  CPU->NVIC_IPR6.bit.PRI_N25 = u8_value;
650 }
651 
657 {
658  CPU->NVIC_IPR6.bit.PRI_N26 = u8_value;
659 }
660 
666 {
667  CPU->NVIC_IPR6.bit.PRI_N27 = u8_value;
668 }
669 
675 {
676  CPU->NVIC_IPR7.bit.PRI_N28 = u8_value;
677 }
678 
684 {
685  CPU->NVIC_IPR7.bit.PRI_N29 = u8_value;
686 }
687 
693 {
694  CPU->NVIC_IPR7.bit.PRI_N30 = u8_value;
695 }
696 
702 {
703  CPU->NVIC_IPR7.bit.PRI_N31 = u8_value;
704 }
705 
708 INLINE void NVIC_enIRQ0(void)
709 {
710  CPU->NVIC_ISER.bit.IRQEN0 = 1u;
711 }
712 
715 INLINE void NVIC_enIRQ1(void)
716 {
717  CPU->NVIC_ISER.bit.IRQEN1 = 1u;
718 }
719 
722 INLINE void NVIC_enIRQ2(void)
723 {
724  CPU->NVIC_ISER.bit.IRQEN2 = 1u;
725 }
726 
729 INLINE void NVIC_enIRQ3(void)
730 {
731  CPU->NVIC_ISER.bit.IRQEN3 = 1u;
732 }
733 
736 INLINE void NVIC_enIRQ4(void)
737 {
738  CPU->NVIC_ISER.bit.IRQEN4 = 1u;
739 }
740 
743 INLINE void NVIC_enIRQ5(void)
744 {
745  CPU->NVIC_ISER.bit.IRQEN5 = 1u;
746 }
747 
750 INLINE void NVIC_enIRQ6(void)
751 {
752  CPU->NVIC_ISER.bit.IRQEN6 = 1u;
753 }
754 
757 INLINE void NVIC_enIRQ7(void)
758 {
759  CPU->NVIC_ISER.bit.IRQEN7 = 1u;
760 }
761 
764 INLINE void NVIC_enIRQ8(void)
765 {
766  CPU->NVIC_ISER.bit.IRQEN8 = 1u;
767 }
768 
771 INLINE void NVIC_enIRQ9(void)
772 {
773  CPU->NVIC_ISER.bit.IRQEN9 = 1u;
774 }
775 
779 {
780  CPU->NVIC_ISER.bit.IRQEN10 = 1u;
781 }
782 
786 {
787  CPU->NVIC_ISER.bit.IRQEN11 = 1u;
788 }
789 
793 {
794  CPU->NVIC_ISER.bit.IRQEN12 = 1u;
795 }
796 
800 {
801  CPU->NVIC_ISER.bit.IRQEN13 = 1u;
802 }
803 
807 {
808  CPU->NVIC_ISER.bit.IRQEN14 = 1u;
809 }
810 
814 {
815  CPU->NVIC_ISER.bit.IRQEN15 = 1u;
816 }
817 
821 {
822  CPU->NVIC_ISER.bit.IRQEN16 = 1u;
823 }
824 
828 {
829  CPU->NVIC_ISER.bit.IRQEN17 = 1u;
830 }
831 
835 {
836  CPU->NVIC_ISER.bit.IRQEN18 = 1u;
837 }
838 
842 {
843  CPU->NVIC_ISER.bit.IRQEN19 = 1u;
844 }
845 
849 {
850  CPU->NVIC_ISER.bit.IRQEN20 = 1u;
851 }
852 
856 {
857  CPU->NVIC_ISER.bit.IRQEN21 = 1u;
858 }
859 
863 {
864  CPU->NVIC_ISER.bit.IRQEN22 = 1u;
865 }
866 
870 {
871  CPU->NVIC_ISER.bit.IRQEN23 = 1u;
872 }
873 
877 {
878  CPU->NVIC_ISER.bit.IRQEN24 = 1u;
879 }
880 
884 {
885  CPU->NVIC_ISER.bit.IRQEN25 = 1u;
886 }
887 
891 {
892  CPU->NVIC_ISER.bit.IRQEN26 = 1u;
893 }
894 
898 {
899  CPU->NVIC_ISER.bit.IRQEN27 = 1u;
900 }
901 
905 {
906  CPU->NVIC_ISER.bit.IRQEN28 = 1u;
907 }
908 
912 {
913  CPU->NVIC_ISER.bit.IRQEN29 = 1u;
914 }
915 
919 {
920  CPU->NVIC_ISER.bit.IRQEN30 = 1u;
921 }
922 
926 {
927  CPU->NVIC_ISER.bit.IRQEN31 = 1u;
928 }
929 
930 /*******************************************************************************
931 ** Global Function Declarations **
932 *******************************************************************************/
935 #endif /* _INT_H */
936 
#define CPU
Definition: tle989x.h:24067
INLINE void NVIC_disIRQ13(void)
Disable NVIC node 13.
Definition: int.h:287
INLINE void NVIC_enIRQ3(void)
Enable NVIC node 3.
Definition: int.h:729
INLINE void NVIC_enIRQ2(void)
Enable NVIC node 2.
Definition: int.h:722
INLINE void NVIC_enIRQ19(void)
Enable NVIC node 19.
Definition: int.h:841
INLINE void NVIC_disIRQ20(void)
Disable NVIC node 20.
Definition: int.h:336
INLINE void NVIC_disIRQ5(void)
Disable NVIC node 5.
Definition: int.h:231
INLINE void NVIC_disIRQ15(void)
Disable NVIC node 15.
Definition: int.h:301
INLINE void NVIC_enIRQ5(void)
Enable NVIC node 5.
Definition: int.h:743
INLINE void NVIC_setIRQ29Priority(uint8 u8_value)
Set NVIC node 29 interrupt priority.
Definition: int.h:683
INLINE void NVIC_disIRQ22(void)
Disable NVIC node 22.
Definition: int.h:350
INLINE void NVIC_disIRQ29(void)
Disable NVIC node 29.
Definition: int.h:399
INLINE void NVIC_disIRQ19(void)
Disable NVIC node 19.
Definition: int.h:329
INLINE void NVIC_enIRQ24(void)
Enable NVIC node 24.
Definition: int.h:876
INLINE void NVIC_enIRQ8(void)
Enable NVIC node 8.
Definition: int.h:764
INLINE void NVIC_enIRQ11(void)
Enable NVIC node 11.
Definition: int.h:785
INLINE void NVIC_setIRQ6Priority(uint8 u8_value)
Set NVIC node 6 interrupt priority.
Definition: int.h:476
INLINE void NVIC_enIRQ12(void)
Enable NVIC node 12.
Definition: int.h:792
INLINE void NVIC_enIRQ18(void)
Enable NVIC node 18.
Definition: int.h:834
INLINE void NVIC_disIRQ8(void)
Disable NVIC node 8.
Definition: int.h:252
INLINE void NVIC_enIRQ13(void)
Enable NVIC node 13.
Definition: int.h:799
INLINE void NVIC_enIRQ10(void)
Enable NVIC node 10.
Definition: int.h:778
INLINE void NVIC_setIRQ8Priority(uint8 u8_value)
Set NVIC node 8 interrupt priority.
Definition: int.h:494
INLINE void NVIC_disIRQ7(void)
Disable NVIC node 7.
Definition: int.h:245
INLINE void NVIC_setIRQ15Priority(uint8 u8_value)
Set NVIC node 15 interrupt priority.
Definition: int.h:557
INLINE void NVIC_setIRQ11Priority(uint8 u8_value)
Set NVIC node 11 interrupt priority.
Definition: int.h:521
INLINE void NVIC_enIRQ7(void)
Enable NVIC node 7.
Definition: int.h:757
INLINE void NVIC_enIRQ0(void)
Enable NVIC node 0.
Definition: int.h:708
INLINE void NVIC_enIRQ22(void)
Enable NVIC node 22.
Definition: int.h:862
INLINE void NVIC_disIRQ21(void)
Disable NVIC node 21.
Definition: int.h:343
INLINE void NVIC_disIRQ6(void)
Disable NVIC node 6.
Definition: int.h:238
INLINE void NVIC_enIRQ15(void)
Enable NVIC node 15.
Definition: int.h:813
INLINE void NVIC_setIRQ10Priority(uint8 u8_value)
Set NVIC node 10 interrupt priority.
Definition: int.h:512
INLINE void NVIC_disIRQ12(void)
Disable NVIC node 12.
Definition: int.h:280
INLINE void NVIC_disIRQ18(void)
Disable NVIC node 18.
Definition: int.h:322
INLINE void NVIC_setIRQ13Priority(uint8 u8_value)
Set NVIC node 13 interrupt priority.
Definition: int.h:539
INLINE void NVIC_enIRQ16(void)
Enable NVIC node 16.
Definition: int.h:820
INLINE void NVIC_disIRQ16(void)
Disable NVIC node 16.
Definition: int.h:308
INLINE void NVIC_setIRQ25Priority(uint8 u8_value)
Set NVIC node 25 interrupt priority.
Definition: int.h:647
INLINE void NVIC_setIRQ3Priority(uint8 u8_value)
Set NVIC node 3 interrupt priority.
Definition: int.h:449
INLINE void NVIC_enIRQ28(void)
Enable NVIC node 28.
Definition: int.h:904
INLINE void NVIC_enIRQ14(void)
Enable NVIC node 14.
Definition: int.h:806
INLINE void NVIC_disIRQ1(void)
Disable NVIC node 1.
Definition: int.h:203
INLINE void NVIC_setIRQ22Priority(uint8 u8_value)
Set NVIC node 22 interrupt priority.
Definition: int.h:620
INLINE void NVIC_disIRQ3(void)
Disable NVIC node 3.
Definition: int.h:217
INLINE void NVIC_enIRQ21(void)
Enable NVIC node 21.
Definition: int.h:855
INLINE void NVIC_setIRQ30Priority(uint8 u8_value)
Set NVIC node 30 interrupt priority.
Definition: int.h:692
INLINE void NVIC_setIRQ2Priority(uint8 u8_value)
Set NVIC node 2 interrupt priority.
Definition: int.h:440
INLINE void NVIC_setIRQ18Priority(uint8 u8_value)
Set NVIC node 18 interrupt priority.
Definition: int.h:584
INLINE void NVIC_setIRQ31Priority(uint8 u8_value)
Set NVIC node 31 interrupt priority.
Definition: int.h:701
INLINE void NVIC_disIRQ23(void)
Disable NVIC node 23.
Definition: int.h:357
INLINE void NVIC_disIRQ10(void)
Disable NVIC node 10.
Definition: int.h:266
INLINE void NVIC_disIRQ2(void)
Disable NVIC node 2.
Definition: int.h:210
INLINE void NVIC_disIRQ11(void)
Disable NVIC node 11.
Definition: int.h:273
INLINE void NVIC_setIRQ20Priority(uint8 u8_value)
Set NVIC node 20 interrupt priority.
Definition: int.h:602
INLINE void NVIC_setIRQ24Priority(uint8 u8_value)
Set NVIC node 24 interrupt priority.
Definition: int.h:638
INLINE void NVIC_enIRQ20(void)
Enable NVIC node 20.
Definition: int.h:848
INLINE void NVIC_enIRQ29(void)
Enable NVIC node 29.
Definition: int.h:911
INLINE void NVIC_setIRQ5Priority(uint8 u8_value)
Set NVIC node 5 interrupt priority.
Definition: int.h:467
void INT_init(void)
Initialize all interrupt-related registers.
Definition: int.c:41
INLINE void NVIC_disIRQ0(void)
Disable NVIC node 0.
Definition: int.h:196
INLINE void NVIC_enIRQ25(void)
Enable NVIC node 25.
Definition: int.h:883
INLINE void NVIC_disIRQ26(void)
Disable NVIC node 26.
Definition: int.h:378
INLINE void NVIC_setIRQ17Priority(uint8 u8_value)
Set NVIC node 17 interrupt priority.
Definition: int.h:575
INLINE void NVIC_enIRQ1(void)
Enable NVIC node 1.
Definition: int.h:715
INLINE void NVIC_enIRQ23(void)
Enable NVIC node 23.
Definition: int.h:869
INLINE void NVIC_disIRQ28(void)
Disable NVIC node 28.
Definition: int.h:392
INLINE void NVIC_setIRQ12Priority(uint8 u8_value)
Set NVIC node 12 interrupt priority.
Definition: int.h:530
INLINE void NVIC_setIRQ28Priority(uint8 u8_value)
Set NVIC node 28 interrupt priority.
Definition: int.h:674
INLINE void NVIC_setIRQ23Priority(uint8 u8_value)
Set NVIC node 23 interrupt priority.
Definition: int.h:629
INLINE void NVIC_setIRQ9Priority(uint8 u8_value)
Set NVIC node 9 interrupt priority.
Definition: int.h:503
INLINE void NVIC_setIRQ26Priority(uint8 u8_value)
Set NVIC node 26 interrupt priority.
Definition: int.h:656
INLINE void NVIC_enIRQ26(void)
Enable NVIC node 26.
Definition: int.h:890
INLINE void NVIC_setIRQ1Priority(uint8 u8_value)
Set NVIC node 1 interrupt priority.
Definition: int.h:431
INLINE void NVIC_disIRQ25(void)
Disable NVIC node 25.
Definition: int.h:371
INLINE void NVIC_setIRQ14Priority(uint8 u8_value)
Set NVIC node 14 interrupt priority.
Definition: int.h:548
INLINE void NVIC_disIRQ4(void)
Disable NVIC node 4.
Definition: int.h:224
INLINE void NVIC_enIRQ27(void)
Enable NVIC node 27.
Definition: int.h:897
INLINE void NVIC_enIRQ30(void)
Enable NVIC node 30.
Definition: int.h:918
INLINE void NVIC_disIRQ30(void)
Disable NVIC node 30.
Definition: int.h:406
INLINE void NVIC_setIRQ4Priority(uint8 u8_value)
Set NVIC node 4 interrupt priority.
Definition: int.h:458
INLINE void NVIC_setIRQ0Priority(uint8 u8_value)
Set NVIC node 0 interrupt priority.
Definition: int.h:422
INLINE void NVIC_enIRQ4(void)
Enable NVIC node 4.
Definition: int.h:736
INLINE void NVIC_setIRQ21Priority(uint8 u8_value)
Set NVIC node 21 interrupt priority.
Definition: int.h:611
INLINE void NVIC_enIRQ17(void)
Enable NVIC node 17.
Definition: int.h:827
INLINE void NVIC_disIRQ17(void)
Disable NVIC node 17.
Definition: int.h:315
INLINE void NVIC_disIRQ14(void)
Disable NVIC node 14.
Definition: int.h:294
INLINE void NVIC_disIRQ24(void)
Disable NVIC node 24.
Definition: int.h:364
INLINE void NVIC_enIRQ31(void)
Enable NVIC node 31.
Definition: int.h:925
INLINE void NVIC_setIRQ27Priority(uint8 u8_value)
Set NVIC node 27 interrupt priority.
Definition: int.h:665
INLINE void NVIC_disIRQ31(void)
Disable NVIC node 31.
Definition: int.h:413
INLINE void NVIC_setIRQ7Priority(uint8 u8_value)
Set NVIC node 7 interrupt priority.
Definition: int.h:485
INLINE void NVIC_setIRQ19Priority(uint8 u8_value)
Set NVIC node 19 interrupt priority.
Definition: int.h:593
INLINE void NVIC_enIRQ9(void)
Enable NVIC node 9.
Definition: int.h:771
INLINE void NVIC_setIRQ16Priority(uint8 u8_value)
Set NVIC node 16 interrupt priority.
Definition: int.h:566
INLINE void NVIC_disIRQ9(void)
Disable NVIC node 9.
Definition: int.h:259
INLINE void NVIC_disIRQ27(void)
Disable NVIC node 27.
Definition: int.h:385
INLINE void NVIC_enIRQ6(void)
Enable NVIC node 6.
Definition: int.h:750
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:151
uint8_t uint8
8 bit unsigned value
Definition: types.h:204