Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
isr.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
22 /*******************************************************************************
23 ** Author(s) Identity **
24 ********************************************************************************
25 ** Initials Name **
26 ** ---------------------------------------------------------------------------**
27 ** DM Daniel Mysliwitz **
28 ** BG Blandine Guillot **
29 ** JO Julia Ott **
30 ** PS Patrik Schwarz **
31 *******************************************************************************/
32 
33 /*******************************************************************************
34 ** Revision Control History **
35 ********************************************************************************
36 ** V0.1.0: 2020-08-24, JO: Initial version **
37 ** V0.2.0: 2020-09-29, JO: EP-483: Fixed condition for the 'Check if NVIC **
38 ** node x is enabled' in all **
39 ** isr_nvic_irqx_handler.c files **
40 ** V0.3.0: 2020-10-20, BG: EP-532: Added function prototypes from NVIC **
41 ** handlers and isr_exceptions.c **
42 ** V0.4.0: 2020-10-28, JO: EP-563: Added NMI_Handler to isr_exceptions.c, **
43 ** Formatted files isr related files **
44 ** V0.4.1: 2020-11-02, JO: EP-556: Removed ADC2 EOC Fail interrupts **
45 ** V0.4.2: 2020-11-12, JO: EP-590: Removed \param none and \return none to **
46 ** avoid doxygen warning **
47 ** V0.4.3: 2020-12-02, JO: EP-610: Fixed error related to EXTINT on falling **
48 ** edge **
49 ** Moved callback declarations from c files **
50 ** to header to prevent MISRA warning **
51 ** The following rules are globally deactivated: **
52 ** - Warning 572: Excessive shift value **
53 ** (precision 0 shifted right by ...) **
54 ** V0.4.4: 2020-12-03, BG: EP-631: Added interrupt handling for CAN **
55 ** V0.4.5: 2020-12-18, JO: EP-599: Defined each *_INT_EN macros to 0 in **
56 ** case it is not defined, done in isr.h **
57 ** V0.4.6: 2021-02-18, BG: EP-691: Removed *_INT_EN macros for CANNODE and **
58 ** CANMSGOBJ0 **
59 ** Removed interrupt handling for CANMSGOBJ1 and **
60 ** CANMSGOBJ1 due to restructuration in tle989x.h **
61 ** V0.4.7: 2021-05-07, JO: EP-812: Made u32_globTimestamp_ms volatile **
62 ** V0.4.8: 2021-08-18, JO: EP-806: Added function INT_getGlobTimestamp **
63 ** V0.4.9: 2021-11-12, JO: EP-937: Updated copyright and branding **
64 ** V0.5.0: 2022-04-25, JO: EP-1139: Added initialization to 0 of variables **
65 ** u8_interrupt_cnt_irq to avoid MISRA violation **
66 ** V0.5.1: 2023-05-05, PS: EP-1242: Removed content from CAN ISR NVIC **
67 ** Handler, to be implemented by the user **
68 ** V0.5.2: 2024-11-05, JO: EP-1494: Updated license **
69 *******************************************************************************/
70 
71 #ifndef _ISR_H
72 #define _ISR_H
73 
74 /*******************************************************************************
75 ** Includes **
76 *******************************************************************************/
77 
78 #include "isr.h"
79 #include "types.h"
80 #include "tle989x.h"
81 #include "tle_variants.h"
82 #include "isr_defines.h"
83 
84 
85 /*******************************************************************************
86 ** Global Macro Declarations **
87 *******************************************************************************/
88 
89 #define NMI_INP_NMI 3
90 
91 #define WARN_INP_NVIC_IRQ0 0
92 #define WARN_INP_NVIC_IRQ1 1
93 #define CCU7_INP_NVIC_IRQ2 0
94 #define CCU7_INP_NVIC_IRQ3 1
95 #define CCU7_INP_NVIC_IRQ4 2
96 #define CCU7_INP_NVIC_IRQ5 3
97 #define MEMCTRL_INP_NVIC_IRQ6 0
98 #define GPT12_INP_NVIC_IRQ7 0
99 #define GPT12_INP_NVIC_IRQ8 1
100 #define ADC2_INP_NVIC_IRQ10 0
101 #define ADC2_INP_NVIC_IRQ11 1
102 #define MON_INP_NVIC_IRQ12 0
103 #define MON_INP_NVIC_IRQ13 1
104 #define ADC1_INP_NVIC_IRQ14 0
105 #define ADC1_INP_NVIC_IRQ15 1
106 #define ADC1_INP_NVIC_IRQ16 2
107 #define ADC1_INP_NVIC_IRQ17 3
108 #define BEMF_SDADC_INP_NVIC_IRQ18 0
109 #define BEMF_SDADC_INP_NVIC_IRQ19 1
110 #define EXTINT_INP_NVIC_IRQ20 0
111 #define EXTINT_INP_NVIC_IRQ21 1
112 #define UART_INP_NVIC_IRQ22 0
113 #define UART_INP_NVIC_IRQ23 1
114 #define SSC_INP_NVIC_IRQ24 0
115 #define SSC_INP_NVIC_IRQ25 1
116 #define CAN_INP_NVIC_IRQ26 0
117 #define CAN_INP_NVIC_IRQ27 1
118 #define CAN_INP_NVIC_IRQ28 2
119 #define DMA_INP_NVIC_IRQ29 0
120 #define DMA_INP_NVIC_IRQ30 1
121 #define T20_INP_NVIC_IRQ9 0
122 #define T21_INP_NVIC_IRQ31 0
123 
124 #ifndef SCU_NMICON_NMIXTALEN_NMI_EN
125  #define SCU_NMICON_NMIXTALEN_NMI_EN 0
126 #endif
127 #ifndef SCU_NMICON_NMIPLL0EN_NMI_EN
128  #define SCU_NMICON_NMIPLL0EN_NMI_EN 0
129 #endif
130 #ifndef SCU_NMICON_NMIPLL1EN_NMI_EN
131  #define SCU_NMICON_NMIPLL1EN_NMI_EN 0
132 #endif
133 #ifndef MEMCTRL_NMICON_NMIDSEN_NMI_EN
134  #define MEMCTRL_NMICON_NMIDSEN_NMI_EN 0
135 #endif
136 #ifndef MEMCTRL_NMICON_NMIPSEN_NMI_EN
137  #define MEMCTRL_NMICON_NMIPSEN_NMI_EN 0
138 #endif
139 #ifndef MEMCTRL_NMICON_NMICDEN_NMI_EN
140  #define MEMCTRL_NMICON_NMICDEN_NMI_EN 0
141 #endif
142 #ifndef MEMCTRL_NMICON_NMINVM0EN_NMI_EN
143  #define MEMCTRL_NMICON_NMINVM0EN_NMI_EN 0
144 #endif
145 #ifndef MEMCTRL_NMICON_NMINVM1EN_NMI_EN
146  #define MEMCTRL_NMICON_NMINVM1EN_NMI_EN 0
147 #endif
148 #ifndef MEMCTRL_NMICON_NMIMAP0EN_NMI_EN
149  #define MEMCTRL_NMICON_NMIMAP0EN_NMI_EN 0
150 #endif
151 #ifndef MEMCTRL_NMICON_NMIMAP1EN_NMI_EN
152  #define MEMCTRL_NMICON_NMIMAP1EN_NMI_EN 0
153 #endif
154 #ifndef MEMCTRL_NMICON_NMIWDTEN_NMI_EN
155  #define MEMCTRL_NMICON_NMIWDTEN_NMI_EN 0
156 #endif
157 #ifndef MEMCTRL_NMICON_NMISTOFEN_NMI_EN
158  #define MEMCTRL_NMICON_NMISTOFEN_NMI_EN 0
159 #endif
160 #ifndef ADC2_UPTH0_INT_EN
161  #define ADC2_UPTH0_INT_EN 0
162 #endif
163 #ifndef ADC2_LOTH0_INT_EN
164  #define ADC2_LOTH0_INT_EN 0
165 #endif
166 #ifndef ADC2_LOTH1_INT_EN
167  #define ADC2_LOTH1_INT_EN 0
168 #endif
169 #ifndef ADC2_UPTH2_INT_EN
170  #define ADC2_UPTH2_INT_EN 0
171 #endif
172 #ifndef ADC2_LOTH2_INT_EN
173  #define ADC2_LOTH2_INT_EN 0
174 #endif
175 #ifndef ADC2_LOTH3_INT_EN
176  #define ADC2_LOTH3_INT_EN 0
177 #endif
178 #ifndef ADC2_UPTH4_INT_EN
179  #define ADC2_UPTH4_INT_EN 0
180 #endif
181 #ifndef CANTRX_BUS_TO_INT_EN
182  #define CANTRX_BUS_TO_INT_EN 0
183 #endif
184 #ifndef CANTRX_TXD_TO_INT_EN
185  #define CANTRX_TXD_TO_INT_EN 0
186 #endif
187 #ifndef CANTRX_OT_INT_EN
188  #define CANTRX_OT_INT_EN 0
189 #endif
190 #ifndef CANTRX_BUS_ACT_INT_EN
191  #define CANTRX_BUS_ACT_INT_EN 0
192 #endif
193 #ifndef BDRV_LS1_OC_INT_EN
194  #define BDRV_LS1_OC_INT_EN 0
195 #endif
196 #ifndef BDRV_LS1_DS_INT_EN
197  #define BDRV_LS1_DS_INT_EN 0
198 #endif
199 #ifndef BDRV_HS1_OC_INT_EN
200  #define BDRV_HS1_OC_INT_EN 0
201 #endif
202 #ifndef BDRV_HS1_DS_INT_EN
203  #define BDRV_HS1_DS_INT_EN 0
204 #endif
205 #ifndef BDRV_LS2_OC_INT_EN
206  #define BDRV_LS2_OC_INT_EN 0
207 #endif
208 #ifndef BDRV_LS2_DS_INT_EN
209  #define BDRV_LS2_DS_INT_EN 0
210 #endif
211 #ifndef BDRV_HS2_OC_INT_EN
212  #define BDRV_HS2_OC_INT_EN 0
213 #endif
214 #ifndef BDRV_HS2_DS_INT_EN
215  #define BDRV_HS2_DS_INT_EN 0
216 #endif
217 #ifndef BDRV_LS3_OC_INT_EN
218  #define BDRV_LS3_OC_INT_EN 0
219 #endif
220 #ifndef BDRV_LS3_DS_INT_EN
221  #define BDRV_LS3_DS_INT_EN 0
222 #endif
223 #ifndef BDRV_HS3_OC_INT_EN
224  #define BDRV_HS3_OC_INT_EN 0
225 #endif
226 #ifndef BDRV_HS3_DS_INT_EN
227  #define BDRV_HS3_DS_INT_EN 0
228 #endif
229 #ifndef BDRV_HB1_ASEQ_INT_EN
230  #define BDRV_HB1_ASEQ_INT_EN 0
231 #endif
232 #ifndef BDRV_HB2_ASEQ_INT_EN
233  #define BDRV_HB2_ASEQ_INT_EN 0
234 #endif
235 #ifndef BDRV_HB3_ASEQ_INT_EN
236  #define BDRV_HB3_ASEQ_INT_EN 0
237 #endif
238 #ifndef BDRV_SEQ_ERR_INT_EN
239  #define BDRV_SEQ_ERR_INT_EN 0
240 #endif
241 #ifndef BDRV_HB1_ACTDRV_INT_EN
242  #define BDRV_HB1_ACTDRV_INT_EN 0
243 #endif
244 #ifndef BDRV_HB2_ACTDRV_INT_EN
245  #define BDRV_HB2_ACTDRV_INT_EN 0
246 #endif
247 #ifndef BDRV_HB3_ACTDRV_INT_EN
248  #define BDRV_HB3_ACTDRV_INT_EN 0
249 #endif
250 #ifndef BDRV_VCP_LOTH2_INT_EN
251  #define BDRV_VCP_LOTH2_INT_EN 0
252 #endif
253 #ifndef CSACSC_OC_INT_EN
254  #define CSACSC_OC_INT_EN 0
255 #endif
256 #ifndef CSACSC_PARAM_INT_EN
257  #define CSACSC_PARAM_INT_EN 0
258 #endif
259 #ifndef PMU_VDDP_UVWARN_INT_EN
260  #define PMU_VDDP_UVWARN_INT_EN 0
261 #endif
262 #ifndef PMU_VDDP_OV_INT_EN
263  #define PMU_VDDP_OV_INT_EN 0
264 #endif
265 #ifndef PMU_VDDC_UVWARN_INT_EN
266  #define PMU_VDDC_UVWARN_INT_EN 0
267 #endif
268 #ifndef PMU_VDDC_OV_INT_EN
269  #define PMU_VDDC_OV_INT_EN 0
270 #endif
271 #ifndef PMU_VDDEXT_UV_INT_EN
272  #define PMU_VDDEXT_UV_INT_EN 0
273 #endif
274 #ifndef PMU_VDDEXT_OT_INT_EN
275  #define PMU_VDDEXT_OT_INT_EN 0
276 #endif
277 #ifndef ARVG_VAREF_OC_INT_EN
278  #define ARVG_VAREF_OC_INT_EN 0
279 #endif
280 #ifndef CCU7_T12_OM_INT_EN
281  #define CCU7_T12_OM_INT_EN 0
282 #endif
283 #ifndef CCU7_T12_PM_INT_EN
284  #define CCU7_T12_PM_INT_EN 0
285 #endif
286 #ifndef CCU7_T13_CM_INT_EN
287  #define CCU7_T13_CM_INT_EN 0
288 #endif
289 #ifndef CCU7_T13_PM_INT_EN
290  #define CCU7_T13_PM_INT_EN 0
291 #endif
292 #ifndef CCU7_T14_CM_INT_EN
293  #define CCU7_T14_CM_INT_EN 0
294 #endif
295 #ifndef CCU7_T14_PM_INT_EN
296  #define CCU7_T14_PM_INT_EN 0
297 #endif
298 #ifndef CCU7_T15_CM_INT_EN
299  #define CCU7_T15_CM_INT_EN 0
300 #endif
301 #ifndef CCU7_T15_PM_INT_EN
302  #define CCU7_T15_PM_INT_EN 0
303 #endif
304 #ifndef CCU7_T16_CM_INT_EN
305  #define CCU7_T16_CM_INT_EN 0
306 #endif
307 #ifndef CCU7_T16_PM_INT_EN
308  #define CCU7_T16_PM_INT_EN 0
309 #endif
310 #ifndef CCU7_CC70A_CM_R_INT_EN
311  #define CCU7_CC70A_CM_R_INT_EN 0
312 #endif
313 #ifndef CCU7_CC70A_CM_F_INT_EN
314  #define CCU7_CC70A_CM_F_INT_EN 0
315 #endif
316 #ifndef CCU7_CC71A_CM_R_INT_EN
317  #define CCU7_CC71A_CM_R_INT_EN 0
318 #endif
319 #ifndef CCU7_CC71A_CM_F_INT_EN
320  #define CCU7_CC71A_CM_F_INT_EN 0
321 #endif
322 #ifndef CCU7_CC71A_CM_R_INT_EN
323  #define CCU7_CC71A_CM_R_INT_EN 0
324 #endif
325 #ifndef CCU7_CC71A_CM_F_INT_EN
326  #define CCU7_CC71A_CM_F_INT_EN 0
327 #endif
328 #ifndef CCU7_C70B_CM_R_INT_EN
329  #define CCU7_C70B_CM_R_INT_EN 0
330 #endif
331 #ifndef CCU7_C70B_CM_F_INT_EN
332  #define CCU7_C70B_CM_F_INT_EN 0
333 #endif
334 #ifndef CCU7_C71B_CM_R_INT_EN
335  #define CCU7_C71B_CM_R_INT_EN 0
336 #endif
337 #ifndef CCU7_C71B_CM_F_INT_EN
338  #define CCU7_C71B_CM_F_INT_EN 0
339 #endif
340 #ifndef CCU7_C72B_CM_R_INT_EN
341  #define CCU7_C72B_CM_R_INT_EN 0
342 #endif
343 #ifndef CCU7_C72B_CM_F_INT_EN
344  #define CCU7_C72B_CM_F_INT_EN 0
345 #endif
346 #ifndef CCU7_TRAP_INT_EN
347  #define CCU7_TRAP_INT_EN 0
348 #endif
349 #ifndef CCU7_CORRECT_HALL_INT_EN
350  #define CCU7_CORRECT_HALL_INT_EN 0
351 #endif
352 #ifndef CCU7_WRONG_HALL_INT_EN
353  #define CCU7_WRONG_HALL_INT_EN 0
354 #endif
355 #ifndef CCU7_MCM_STR_INT_EN
356  #define CCU7_MCM_STR_INT_EN 0
357 #endif
358 #ifndef CCU7_LI_INT_EN
359  #define CCU7_LI_INT_EN 0
360 #endif
361 #ifndef MEMCTRL_NVM0_OP_COMPLETE_INT_EN
362  #define MEMCTRL_NVM0_OP_COMPLETE_INT_EN 0
363 #endif
364 #ifndef MEMCTRL_NVM1_OP_COMPLETE_INT_EN
365  #define MEMCTRL_NVM1_OP_COMPLETE_INT_EN 0
366 #endif
367 #ifndef GPT12_GPT1T2_INT_EN
368  #define GPT12_GPT1T2_INT_EN 0
369 #endif
370 #ifndef GPT12_GPT1T3_INT_EN
371  #define GPT12_GPT1T3_INT_EN 0
372 #endif
373 #ifndef GPT12_GPT1T4_INT_EN
374  #define GPT12_GPT1T4_INT_EN 0
375 #endif
376 #ifndef GPT12_GPT2T5_INT_EN
377  #define GPT12_GPT2T5_INT_EN 0
378 #endif
379 #ifndef GPT12_GPT2T6_INT_EN
380  #define GPT12_GPT2T6_INT_EN 0
381 #endif
382 #ifndef GPT12_GPT2CAPREL_INT_EN
383  #define GPT12_GPT2CAPREL_INT_EN 0
384 #endif
385 #ifndef ADC2_CH0_INT_EN
386  #define ADC2_CH0_INT_EN 0
387 #endif
388 #ifndef ADC2_CH1_INT_EN
389  #define ADC2_CH1_INT_EN 0
390 #endif
391 #ifndef ADC2_CH2_INT_EN
392  #define ADC2_CH2_INT_EN 0
393 #endif
394 #ifndef ADC2_CH3_INT_EN
395  #define ADC2_CH3_INT_EN 0
396 #endif
397 #ifndef ADC2_CH4_INT_EN
398  #define ADC2_CH4_INT_EN 0
399 #endif
400 #ifndef ADC2_CH5_INT_EN
401  #define ADC2_CH5_INT_EN 0
402 #endif
403 #ifndef ADC2_CH6_INT_EN
404  #define ADC2_CH6_INT_EN 0
405 #endif
406 #ifndef ADC2_CH7_INT_EN
407  #define ADC2_CH7_INT_EN 0
408 #endif
409 #ifndef ADC2_CH8_INT_EN
410  #define ADC2_CH8_INT_EN 0
411 #endif
412 #ifndef ADC2_CH9_INT_EN
413  #define ADC2_CH9_INT_EN 0
414 #endif
415 #ifndef ADC2_CH10_INT_EN
416  #define ADC2_CH10_INT_EN 0
417 #endif
418 #ifndef ADC2_CH11_INT_EN
419  #define ADC2_CH11_INT_EN 0
420 #endif
421 #ifndef ADC2_CH12_INT_EN
422  #define ADC2_CH12_INT_EN 0
423 #endif
424 #ifndef ADC2_CH13_INT_EN
425  #define ADC2_CH13_INT_EN 0
426 #endif
427 #ifndef ADC2_CH14_INT_EN
428  #define ADC2_CH14_INT_EN 0
429 #endif
430 #ifndef ADC2_SQ0_INT_EN
431  #define ADC2_SQ0_INT_EN 0
432 #endif
433 #ifndef ADC2_SQ1_INT_EN
434  #define ADC2_SQ1_INT_EN 0
435 #endif
436 #ifndef ADC2_SQ2_INT_EN
437  #define ADC2_SQ2_INT_EN 0
438 #endif
439 #ifndef ADC2_SQ3_INT_EN
440  #define ADC2_SQ3_INT_EN 0
441 #endif
442 #ifndef ADC2_LOTH0_INT_EN
443  #define ADC2_LOTH0_INT_EN 0
444 #endif
445 #ifndef ADC2_LOTH1_INT_EN
446  #define ADC2_LOTH1_INT_EN 0
447 #endif
448 #ifndef ADC2_LOTH2_INT_EN
449  #define ADC2_LOTH2_INT_EN 0
450 #endif
451 #ifndef ADC2_LOTH3_INT_EN
452  #define ADC2_LOTH3_INT_EN 0
453 #endif
454 #ifndef ADC2_LOTH4_INT_EN
455  #define ADC2_LOTH4_INT_EN 0
456 #endif
457 #ifndef ADC2_LOTH5_INT_EN
458  #define ADC2_LOTH5_INT_EN 0
459 #endif
460 #ifndef ADC2_LOTH6_INT_EN
461  #define ADC2_LOTH6_INT_EN 0
462 #endif
463 #ifndef ADC2_LOTH7_INT_EN
464  #define ADC2_LOTH7_INT_EN 0
465 #endif
466 #ifndef ADC2_UPTH0_INT_EN
467  #define ADC2_UPTH0_INT_EN 0
468 #endif
469 #ifndef ADC2_UPTH1_INT_EN
470  #define ADC2_UPTH1_INT_EN 0
471 #endif
472 #ifndef ADC2_UPTH2_INT_EN
473  #define ADC2_UPTH2_INT_EN 0
474 #endif
475 #ifndef ADC2_UPTH3_INT_EN
476  #define ADC2_UPTH3_INT_EN 0
477 #endif
478 #ifndef ADC2_UPTH4_INT_EN
479  #define ADC2_UPTH4_INT_EN 0
480 #endif
481 #ifndef ADC2_UPTH5_INT_EN
482  #define ADC2_UPTH5_INT_EN 0
483 #endif
484 #ifndef ADC2_UPTH6_INT_EN
485  #define ADC2_UPTH6_INT_EN 0
486 #endif
487 #ifndef ADC2_UPTH7_INT_EN
488  #define ADC2_UPTH7_INT_EN 0
489 #endif
490 #ifndef MON_MON1_R_INT_EN
491  #define MON_MON1_R_INT_EN 0
492 #endif
493 #ifndef MON_MON1_F_INT_EN
494  #define MON_MON1_F_INT_EN 0
495 #endif
496 #ifndef MON_MON2_R_INT_EN
497  #define MON_MON2_R_INT_EN 0
498 #endif
499 #ifndef MON_MON2_F_INT_EN
500  #define MON_MON2_F_INT_EN 0
501 #endif
502 #ifndef MON_MON3_R_INT_EN
503  #define MON_MON3_R_INT_EN 0
504 #endif
505 #ifndef MON_MON3_F_INT_EN
506  #define MON_MON3_F_INT_EN 0
507 #endif
508 #ifndef ADC1_CH0_INT_EN
509  #define ADC1_CH0_INT_EN 0
510 #endif
511 #ifndef ADC1_CH1_INT_EN
512  #define ADC1_CH1_INT_EN 0
513 #endif
514 #ifndef ADC1_CH2_INT_EN
515  #define ADC1_CH2_INT_EN 0
516 #endif
517 #ifndef ADC1_CH3_INT_EN
518  #define ADC1_CH3_INT_EN 0
519 #endif
520 #ifndef ADC1_CH4_INT_EN
521  #define ADC1_CH4_INT_EN 0
522 #endif
523 #ifndef ADC1_CH5_INT_EN
524  #define ADC1_CH5_INT_EN 0
525 #endif
526 #ifndef ADC1_CH6_INT_EN
527  #define ADC1_CH6_INT_EN 0
528 #endif
529 #ifndef ADC1_CH7_INT_EN
530  #define ADC1_CH7_INT_EN 0
531 #endif
532 #ifndef ADC1_CH8_INT_EN
533  #define ADC1_CH8_INT_EN 0
534 #endif
535 #ifndef ADC1_CH9_INT_EN
536  #define ADC1_CH9_INT_EN 0
537 #endif
538 #ifndef ADC1_CH10_INT_EN
539  #define ADC1_CH10_INT_EN 0
540 #endif
541 #ifndef ADC1_CH11_INT_EN
542  #define ADC1_CH11_INT_EN 0
543 #endif
544 #ifndef ADC1_CH12_INT_EN
545  #define ADC1_CH12_INT_EN 0
546 #endif
547 #ifndef ADC1_CH13_INT_EN
548  #define ADC1_CH13_INT_EN 0
549 #endif
550 #ifndef ADC1_CH14_INT_EN
551  #define ADC1_CH14_INT_EN 0
552 #endif
553 #ifndef ADC1_CH15_INT_EN
554  #define ADC1_CH15_INT_EN 0
555 #endif
556 #ifndef ADC1_CH16_INT_EN
557  #define ADC1_CH16_INT_EN 0
558 #endif
559 #ifndef ADC1_CH17_INT_EN
560  #define ADC1_CH17_INT_EN 0
561 #endif
562 #ifndef ADC1_CH18_INT_EN
563  #define ADC1_CH18_INT_EN 0
564 #endif
565 #ifndef ADC1_CH19_INT_EN
566  #define ADC1_CH19_INT_EN 0
567 #endif
568 #ifndef ADC1_SQ0_INT_EN
569  #define ADC1_SQ0_INT_EN 0
570 #endif
571 #ifndef ADC1_SQ1_INT_EN
572  #define ADC1_SQ1_INT_EN 0
573 #endif
574 #ifndef ADC1_SQ2_INT_EN
575  #define ADC1_SQ2_INT_EN 0
576 #endif
577 #ifndef ADC1_SQ3_INT_EN
578  #define ADC1_SQ3_INT_EN 0
579 #endif
580 #ifndef ADC1_LOTH0_INT_EN
581  #define ADC1_LOTH0_INT_EN 0
582 #endif
583 #ifndef ADC1_LOTH1_INT_EN
584  #define ADC1_LOTH1_INT_EN 0
585 #endif
586 #ifndef ADC1_LOTH2_INT_EN
587  #define ADC1_LOTH2_INT_EN 0
588 #endif
589 #ifndef ADC1_LOTH3_INT_EN
590  #define ADC1_LOTH3_INT_EN 0
591 #endif
592 #ifndef ADC1_UPTH0_INT_EN
593  #define ADC1_UPTH0_INT_EN 0
594 #endif
595 #ifndef ADC1_UPTH1_INT_EN
596  #define ADC1_UPTH1_INT_EN 0
597 #endif
598 #ifndef ADC1_UPTH2_INT_EN
599  #define ADC1_UPTH2_INT_EN 0
600 #endif
601 #ifndef ADC1_UPTH3_INT_EN
602  #define ADC1_UPTH3_INT_EN 0
603 #endif
604 #ifndef ADC1_COLL0_INT_EN
605  #define ADC1_COLL0_INT_EN 0
606 #endif
607 #ifndef ADC1_COLL1_INT_EN
608  #define ADC1_COLL1_INT_EN 0
609 #endif
610 #ifndef ADC1_COLL2_INT_EN
611  #define ADC1_COLL2_INT_EN 0
612 #endif
613 #ifndef ADC1_COLL3_INT_EN
614  #define ADC1_COLL3_INT_EN 0
615 #endif
616 #ifndef ADC1_WFR0_INT_EN
617  #define ADC1_WFR0_INT_EN 0
618 #endif
619 #ifndef ADC1_WFR1_INT_EN
620  #define ADC1_WFR1_INT_EN 0
621 #endif
622 #ifndef ADC1_WFR2_INT_EN
623  #define ADC1_WFR2_INT_EN 0
624 #endif
625 #ifndef ADC1_WFR3_INT_EN
626  #define ADC1_WFR3_INT_EN 0
627 #endif
628 #ifndef BDRV_PH1_ZC_RISE_INT_EN
629  #define BDRV_PH1_ZC_RISE_INT_EN 0
630 #endif
631 #ifndef BDRV_PH1_ZC_FALL_INT_EN
632  #define BDRV_PH1_ZC_FALL_INT_EN 0
633 #endif
634 #ifndef BDRV_PH2_ZC_RISE_INT_EN
635  #define BDRV_PH2_ZC_RISE_INT_EN 0
636 #endif
637 #ifndef BDRV_PH2_ZC_FALL_INT_EN
638  #define BDRV_PH2_ZC_FALL_INT_EN 0
639 #endif
640 #ifndef BDRV_PH3_ZC_RISE_INT_EN
641  #define BDRV_PH3_ZC_RISE_INT_EN 0
642 #endif
643 #ifndef BDRV_PH3_ZC_FALL_INT_EN
644  #define BDRV_PH3_ZC_FALL_INT_EN 0
645 #endif
646 #ifndef SDADC_RES0_INT_EN
647  #define SDADC_RES0_INT_EN 0
648 #endif
649 #ifndef SDADC_CMP0_UP_INT_EN
650  #define SDADC_CMP0_UP_INT_EN 0
651 #endif
652 #ifndef SDADC_CMP0_LO_INT_EN
653  #define SDADC_CMP0_LO_INT_EN 0
654 #endif
655 #ifndef SDADC_RES1_INT_EN
656  #define SDADC_RES1_INT_EN 0
657 #endif
658 #ifndef SDADC_CMP1_UP_INT_EN
659  #define SDADC_CMP1_UP_INT_EN 0
660 #endif
661 #ifndef SDADC_CMP1_LO_INT_EN
662  #define SDADC_CMP1_LO_INT_EN 0
663 #endif
664 #ifndef SCU_EXTINT0_RISING_INT_EN
665  #define SCU_EXTINT0_RISING_INT_EN 0
666 #endif
667 #ifndef SCU_EXTINT0_FALLING_INT_EN
668  #define SCU_EXTINT0_FALLING_INT_EN 0
669 #endif
670 #ifndef SCU_EXTINT1_RISING_INT_EN
671  #define SCU_EXTINT1_RISING_INT_EN 0
672 #endif
673 #ifndef SCU_EXTINT1_FALLING_INT_EN
674  #define SCU_EXTINT1_FALLING_INT_EN 0
675 #endif
676 #ifndef SCU_EXTINT2_RISING_INT_EN
677  #define SCU_EXTINT2_RISING_INT_EN 0
678 #endif
679 #ifndef SCU_EXTINT2_FALLING_INT_EN
680  #define SCU_EXTINT2_FALLING_INT_EN 0
681 #endif
682 #ifndef SCU_EXTINT3_RISING_INT_EN
683  #define SCU_EXTINT3_RISING_INT_EN 0
684 #endif
685 #ifndef SCU_EXTINT3_FALLING_INT_EN
686  #define SCU_EXTINT3_FALLING_INT_EN 0
687 #endif
688 #ifndef UART0_TI_INT_EN
689  #define UART0_TI_INT_EN 0
690 #endif
691 #ifndef UART0_RI_INT_EN
692  #define UART0_RI_INT_EN 0
693 #endif
694 #ifndef UART0_EOS_INT_EN
695  #define UART0_EOS_INT_EN 0
696 #endif
697 #ifndef UART0_SYNCERR_INT_EN
698  #define UART0_SYNCERR_INT_EN 0
699 #endif
700 #ifndef UART1_TI_INT_EN
701  #define UART1_TI_INT_EN 0
702 #endif
703 #ifndef UART1_RI_INT_EN
704  #define UART1_RI_INT_EN 0
705 #endif
706 #ifndef UART1_EOS_INT_EN
707  #define UART1_EOS_INT_EN 0
708 #endif
709 #ifndef UART1_SYNCERR_INT_EN
710  #define UART1_SYNCERR_INT_EN 0
711 #endif
712 #ifndef SSC0_TI_INT_EN
713  #define SSC0_TI_INT_EN 0
714 #endif
715 #ifndef SSC0_RI_INT_EN
716  #define SSC0_RI_INT_EN 0
717 #endif
718 #ifndef SSC0_ERR_INT_EN
719  #define SSC0_ERR_INT_EN 0
720 #endif
721 #ifndef SSC0_ERR_INT_EN
722  #define SSC0_ERR_INT_EN 0
723 #endif
724 #ifndef SSC0_ERR_INT_EN
725  #define SSC0_ERR_INT_EN 0
726 #endif
727 #ifndef SSC0_ERR_INT_EN
728  #define SSC0_ERR_INT_EN 0
729 #endif
730 #ifndef SSC1_TI_INT_EN
731  #define SSC1_TI_INT_EN 0
732 #endif
733 #ifndef SSC1_RI_INT_EN
734  #define SSC1_RI_INT_EN 0
735 #endif
736 #ifndef SSC1_ERR_INT_EN
737  #define SSC1_ERR_INT_EN 0
738 #endif
739 #ifndef SSC1_ERR_INT_EN
740  #define SSC1_ERR_INT_EN 0
741 #endif
742 #ifndef SSC1_ERR_INT_EN
743  #define SSC1_ERR_INT_EN 0
744 #endif
745 #ifndef SSC1_ERR_INT_EN
746  #define SSC1_ERR_INT_EN 0
747 #endif
748 #ifndef DMA_CH0_INT_EN
749  #define DMA_CH0_INT_EN 0
750 #endif
751 #ifndef DMA_CH1_INT_EN
752  #define DMA_CH1_INT_EN 0
753 #endif
754 #ifndef DMA_CH2_INT_EN
755  #define DMA_CH2_INT_EN 0
756 #endif
757 #ifndef DMA_CH3_INT_EN
758  #define DMA_CH3_INT_EN 0
759 #endif
760 #ifndef DMA_CH4_INT_EN
761  #define DMA_CH4_INT_EN 0
762 #endif
763 #ifndef DMA_CH5_INT_EN
764  #define DMA_CH5_INT_EN 0
765 #endif
766 #ifndef DMA_CH6_INT_EN
767  #define DMA_CH6_INT_EN 0
768 #endif
769 #ifndef DMA_CH7_INT_EN
770  #define DMA_CH7_INT_EN 0
771 #endif
772 #ifndef DMA_ERROR_INT_EN
773  #define DMA_ERROR_INT_EN 0
774 #endif
775 #ifndef T20_EXF2_INT_EN
776  #define T20_EXF2_INT_EN 0
777 #endif
778 #ifndef T20_TF2_INT_EN
779  #define T20_TF2_INT_EN 0
780 #endif
781 #ifndef T21_EXF2_INT_EN
782  #define T21_EXF2_INT_EN 0
783 #endif
784 #ifndef T21_TF2_INT_EN
785  #define T21_TF2_INT_EN 0
786 #endif
787 
788 
789 
790 /*******************************************************************************
791 ** Global Variable Declarations **
792 *******************************************************************************/
793 
794 /* global counter variable for ms, can count ~1.5 months, requirement EMPS-SHRQ-66 */
795 extern volatile uint32 u32_globTimestamp_ms;
796 
797 #if (NVIC_IRQ0_HANDLER_INT_CHECK == 1)
798  extern uint8 u8_interrupt_cnt_irq0;
799 #endif
800 #if (NVIC_IRQ1_HANDLER_INT_CHECK == 1)
801  extern uint8 u8_interrupt_cnt_irq1;
802 #endif
803 #if (NVIC_IRQ2_HANDLER_INT_CHECK == 1)
804  extern uint8 u8_interrupt_cnt_irq2;
805 #endif
806 #if (NVIC_IRQ3_HANDLER_INT_CHECK == 1)
807  extern uint8 u8_interrupt_cnt_irq3;
808 #endif
809 #if (NVIC_IRQ4_HANDLER_INT_CHECK == 1)
810  extern uint8 u8_interrupt_cnt_irq4;
811 #endif
812 #if (NVIC_IRQ5_HANDLER_INT_CHECK == 1)
813  extern uint8 u8_interrupt_cnt_irq5;
814 #endif
815 #if (NVIC_IRQ6_HANDLER_INT_CHECK == 1)
816  extern uint8 u8_interrupt_cnt_irq6;
817 #endif
818 #if (NVIC_IRQ7_HANDLER_INT_CHECK == 1)
819  extern uint8 u8_interrupt_cnt_irq7;
820 #endif
821 #if (NVIC_IRQ8_HANDLER_INT_CHECK == 1)
822  extern uint8 u8_interrupt_cnt_irq8;
823 #endif
824 #if (NVIC_IRQ10_HANDLER_INT_CHECK == 1)
825  extern uint8 u8_interrupt_cnt_irq10;
826 #endif
827 #if (NVIC_IRQ11_HANDLER_INT_CHECK == 1)
828  extern uint8 u8_interrupt_cnt_irq11;
829 #endif
830 #if (NVIC_IRQ12_HANDLER_INT_CHECK == 1)
831  extern uint8 u8_interrupt_cnt_irq12;
832 #endif
833 #if (NVIC_IRQ13_HANDLER_INT_CHECK == 1)
834  extern uint8 u8_interrupt_cnt_irq13;
835 #endif
836 #if (NVIC_IRQ14_HANDLER_INT_CHECK == 1)
837  extern uint8 u8_interrupt_cnt_irq14;
838 #endif
839 #if (NVIC_IRQ15_HANDLER_INT_CHECK == 1)
840  extern uint8 u8_interrupt_cnt_irq15;
841 #endif
842 #if (NVIC_IRQ16_HANDLER_INT_CHECK == 1)
843  extern uint8 u8_interrupt_cnt_irq16;
844 #endif
845 #if (NVIC_IRQ17_HANDLER_INT_CHECK == 1)
846  extern uint8 u8_interrupt_cnt_irq17;
847 #endif
848 #if (NVIC_IRQ18_HANDLER_INT_CHECK == 1)
849  extern uint8 u8_interrupt_cnt_irq18;
850 #endif
851 #if (NVIC_IRQ19_HANDLER_INT_CHECK == 1)
852  extern uint8 u8_interrupt_cnt_irq19;
853 #endif
854 #if (NVIC_IRQ20_HANDLER_INT_CHECK == 1)
855  extern uint8 u8_interrupt_cnt_irq20;
856 #endif
857 #if (NVIC_IRQ21_HANDLER_INT_CHECK == 1)
858  extern uint8 u8_interrupt_cnt_irq21;
859 #endif
860 #if (NVIC_IRQ22_HANDLER_INT_CHECK == 1)
861  extern uint8 u8_interrupt_cnt_irq22;
862 #endif
863 #if (NVIC_IRQ23_HANDLER_INT_CHECK == 1)
864  extern uint8 u8_interrupt_cnt_irq23;
865 #endif
866 #if (NVIC_IRQ24_HANDLER_INT_CHECK == 1)
867  extern uint8 u8_interrupt_cnt_irq24;
868 #endif
869 #if (NVIC_IRQ25_HANDLER_INT_CHECK == 1)
870  extern uint8 u8_interrupt_cnt_irq25;
871 #endif
872 #if (NVIC_IRQ26_HANDLER_INT_CHECK == 1)
873  extern uint8 u8_interrupt_cnt_irq26;
874 #endif
875 #if (NVIC_IRQ27_HANDLER_INT_CHECK == 1)
876  extern uint8 u8_interrupt_cnt_irq27;
877 #endif
878 #if (NVIC_IRQ28_HANDLER_INT_CHECK == 1)
879  extern uint8 u8_interrupt_cnt_irq28;
880 #endif
881 #if (NVIC_IRQ29_HANDLER_INT_CHECK == 1)
882  extern uint8 u8_interrupt_cnt_irq29;
883 #endif
884 #if (NVIC_IRQ30_HANDLER_INT_CHECK == 1)
885  extern uint8 u8_interrupt_cnt_irq30;
886 #endif
887 #if (NVIC_IRQ9_HANDLER_INT_CHECK == 1)
888  extern uint8 u8_interrupt_cnt_irq9;
889 #endif
890 #if (NVIC_IRQ31_HANDLER_INT_CHECK == 1)
891  extern uint8 u8_interrupt_cnt_irq31;
892 #endif
893 
894 /*******************************************************************************
895 ** Global Function Declarations **
896 *******************************************************************************/
898 void HardFault_Handler(void);
899 void MemManage_Handler(void);
900 void BusFault_Handler(void);
901 void UsageFault_Handler(void);
902 void NMI_Handler(void);
903 void SysTick_Handler(void);
904 void PendSV_Handler(void);
905 void NVIC_IRQ0_Handler(void);
906 void NVIC_IRQ1_Handler(void);
907 void NVIC_IRQ2_Handler(void);
908 void NVIC_IRQ3_Handler(void);
909 void NVIC_IRQ4_Handler(void);
910 void NVIC_IRQ5_Handler(void);
911 void NVIC_IRQ6_Handler(void);
912 void NVIC_IRQ7_Handler(void);
913 void NVIC_IRQ8_Handler(void);
914 void NVIC_IRQ9_Handler(void);
915 void NVIC_IRQ10_Handler(void);
916 void NVIC_IRQ11_Handler(void);
917 void NVIC_IRQ12_Handler(void);
918 void NVIC_IRQ13_Handler(void);
919 void NVIC_IRQ14_Handler(void);
920 void NVIC_IRQ15_Handler(void);
921 void NVIC_IRQ16_Handler(void);
922 void NVIC_IRQ17_Handler(void);
923 void NVIC_IRQ18_Handler(void);
924 void NVIC_IRQ19_Handler(void);
925 void NVIC_IRQ20_Handler(void);
926 void NVIC_IRQ21_Handler(void);
927 void NVIC_IRQ22_Handler(void);
928 void NVIC_IRQ23_Handler(void);
929 void NVIC_IRQ24_Handler(void);
930 void NVIC_IRQ25_Handler(void);
931 void NVIC_IRQ26_Handler(void);
932 void NVIC_IRQ27_Handler(void);
933 void NVIC_IRQ28_Handler(void);
934 void NVIC_IRQ29_Handler(void);
935 void NVIC_IRQ30_Handler(void);
936 void NVIC_IRQ31_Handler(void);
937 extern void CPU_HARDFAULT_CALLBACK(void);
938 extern void CPU_MEMMANAGE_CALLBACK(void);
939 extern void CPU_BUSFAULT_CALLBACK(void);
940 extern void CPU_USAGEFAULT_CALLBACK(void);
955 extern void ADC2_UPTH0_CALLBACK(void);
956 extern void ADC2_LOTH0_CALLBACK(void);
957 extern void ADC2_LOTH1_CALLBACK(void);
958 extern void ADC2_UPTH2_CALLBACK(void);
959 extern void ADC2_LOTH2_CALLBACK(void);
960 extern void ADC2_LOTH3_CALLBACK(void);
961 extern void ADC2_UPTH4_CALLBACK(void);
962 extern void CANTRX_BUS_TO_CALLBACK(void);
963 extern void CANTRX_TXD_TO_CALLBACK(void);
964 extern void CANTRX_OT_CALLBACK(void);
965 extern void CANTRX_BUS_ACT_CALLBACK(void);
966 extern void BDRV_LS1_OC_CALLBACK(void);
967 extern void BDRV_LS1_DS_CALLBACK(void);
968 extern void BDRV_HS1_OC_CALLBACK(void);
969 extern void BDRV_HS1_DS_CALLBACK(void);
970 extern void BDRV_LS2_OC_CALLBACK(void);
971 extern void BDRV_LS2_DS_CALLBACK(void);
972 extern void BDRV_HS2_OC_CALLBACK(void);
973 extern void BDRV_HS2_DS_CALLBACK(void);
974 extern void BDRV_LS3_OC_CALLBACK(void);
975 extern void BDRV_LS3_DS_CALLBACK(void);
976 extern void BDRV_HS3_OC_CALLBACK(void);
977 extern void BDRV_HS3_DS_CALLBACK(void);
978 extern void BDRV_HB1_ASEQ_CALLBACK(void);
979 extern void BDRV_HB2_ASEQ_CALLBACK(void);
980 extern void BDRV_HB3_ASEQ_CALLBACK(void);
981 extern void BDRV_SEQ_ERR_CALLBACK(void);
982 extern void BDRV_HB1_ACTDRV_CALLBACK(void);
983 extern void BDRV_HB2_ACTDRV_CALLBACK(void);
984 extern void BDRV_HB3_ACTDRV_CALLBACK(void);
985 extern void BDRV_VCP_LOTH2_CALLBACK(void);
986 extern void CSACSC_OC_CALLBACK(void);
987 extern void CSACSC_PARAM_CALLBACK(void);
988 extern void PMU_VDDP_UVWARN_CALLBACK(void);
989 extern void PMU_VDDP_OV_CALLBACK(void);
990 extern void PMU_VDDC_UVWARN_CALLBACK(void);
991 extern void PMU_VDDC_OV_CALLBACK(void);
992 extern void PMU_VDDEXT_UV_CALLBACK(void);
993 extern void PMU_VDDEXT_OT_CALLBACK(void);
994 extern void ARVG_VAREF_OC_CALLBACK(void);
995 extern void CCU7_T12_OM_CALLBACK(void);
996 extern void CCU7_T12_PM_CALLBACK(void);
997 extern void CCU7_T13_CM_CALLBACK(void);
998 extern void CCU7_T13_PM_CALLBACK(void);
999 extern void CCU7_T14_CM_CALLBACK(void);
1000 extern void CCU7_T14_PM_CALLBACK(void);
1001 extern void CCU7_T15_CM_CALLBACK(void);
1002 extern void CCU7_T15_PM_CALLBACK(void);
1003 extern void CCU7_T16_CM_CALLBACK(void);
1004 extern void CCU7_T16_PM_CALLBACK(void);
1005 extern void CCU7_CC70A_CM_R_CALLBACK(void);
1006 extern void CCU7_CC70A_CM_F_CALLBACK(void);
1007 extern void CCU7_CC71A_CM_R_CALLBACK(void);
1008 extern void CCU7_CC71A_CM_F_CALLBACK(void);
1009 extern void CCU7_CC72A_CM_R_CALLBACK(void);
1010 extern void CCU7_CC72A_CM_F_CALLBACK(void);
1011 extern void CCU7_C70B_CM_R_CALLBACK(void);
1012 extern void CCU7_C70B_CM_F_CALLBACK(void);
1013 extern void CCU7_C71B_CM_R_CALLBACK(void);
1014 extern void CCU7_C71B_CM_F_CALLBACK(void);
1015 extern void CCU7_C72B_CM_R_CALLBACK(void);
1016 extern void CCU7_C72B_CM_F_CALLBACK(void);
1017 extern void CCU7_TRAP_CALLBACK(void);
1018 extern void CCU7_CORRECT_HALL_CALLBACK(void);
1019 extern void CCU7_WRONG_HALL_CALLBACK(void);
1020 extern void CCU7_MCM_STR_CALLBACK(void);
1021 extern void CCU7_LI_CALLBACK(void);
1024 extern void GPT12_GPT1T2_CALLBACK(void);
1025 extern void GPT12_GPT1T3_CALLBACK(void);
1026 extern void GPT12_GPT1T4_CALLBACK(void);
1027 extern void GPT12_GPT2T5_CALLBACK(void);
1028 extern void GPT12_GPT2T6_CALLBACK(void);
1029 extern void GPT12_GPT2CAPREL_CALLBACK(void);
1030 extern void ADC2_CH0_CALLBACK(void);
1031 extern void ADC2_CH1_CALLBACK(void);
1032 extern void ADC2_CH2_CALLBACK(void);
1033 extern void ADC2_CH3_CALLBACK(void);
1034 extern void ADC2_CH4_CALLBACK(void);
1035 extern void ADC2_CH5_CALLBACK(void);
1036 extern void ADC2_CH6_CALLBACK(void);
1037 extern void ADC2_CH7_CALLBACK(void);
1038 extern void ADC2_CH8_CALLBACK(void);
1039 extern void ADC2_CH9_CALLBACK(void);
1040 extern void ADC2_CH10_CALLBACK(void);
1041 extern void ADC2_CH11_CALLBACK(void);
1042 extern void ADC2_CH12_CALLBACK(void);
1043 extern void ADC2_CH13_CALLBACK(void);
1044 extern void ADC2_CH14_CALLBACK(void);
1045 extern void ADC2_SQ0_CALLBACK(void);
1046 extern void ADC2_SQ1_CALLBACK(void);
1047 extern void ADC2_SQ2_CALLBACK(void);
1048 extern void ADC2_SQ3_CALLBACK(void);
1049 extern void ADC2_LOTH0_CALLBACK(void);
1050 extern void ADC2_LOTH1_CALLBACK(void);
1051 extern void ADC2_LOTH2_CALLBACK(void);
1052 extern void ADC2_LOTH3_CALLBACK(void);
1053 extern void ADC2_LOTH4_CALLBACK(void);
1054 extern void ADC2_LOTH5_CALLBACK(void);
1055 extern void ADC2_LOTH6_CALLBACK(void);
1056 extern void ADC2_LOTH7_CALLBACK(void);
1057 extern void ADC2_UPTH0_CALLBACK(void);
1058 extern void ADC2_UPTH1_CALLBACK(void);
1059 extern void ADC2_UPTH2_CALLBACK(void);
1060 extern void ADC2_UPTH3_CALLBACK(void);
1061 extern void ADC2_UPTH4_CALLBACK(void);
1062 extern void ADC2_UPTH5_CALLBACK(void);
1063 extern void ADC2_UPTH6_CALLBACK(void);
1064 extern void ADC2_UPTH7_CALLBACK(void);
1065 extern void MON_MON1_R_CALLBACK(void);
1066 extern void MON_MON1_F_CALLBACK(void);
1067 extern void MON_MON2_R_CALLBACK(void);
1068 extern void MON_MON2_F_CALLBACK(void);
1069 extern void MON_MON3_R_CALLBACK(void);
1070 extern void MON_MON3_F_CALLBACK(void);
1071 extern void ADC1_CH0_CALLBACK(void);
1072 extern void ADC1_CH1_CALLBACK(void);
1073 extern void ADC1_CH2_CALLBACK(void);
1074 extern void ADC1_CH3_CALLBACK(void);
1075 extern void ADC1_CH4_CALLBACK(void);
1076 extern void ADC1_CH5_CALLBACK(void);
1077 extern void ADC1_CH6_CALLBACK(void);
1078 extern void ADC1_CH7_CALLBACK(void);
1079 extern void ADC1_CH8_CALLBACK(void);
1080 extern void ADC1_CH9_CALLBACK(void);
1081 extern void ADC1_CH10_CALLBACK(void);
1082 extern void ADC1_CH11_CALLBACK(void);
1083 extern void ADC1_CH12_CALLBACK(void);
1084 extern void ADC1_CH13_CALLBACK(void);
1085 extern void ADC1_CH14_CALLBACK(void);
1086 extern void ADC1_CH15_CALLBACK(void);
1087 extern void ADC1_CH16_CALLBACK(void);
1088 extern void ADC1_CH17_CALLBACK(void);
1089 extern void ADC1_CH18_CALLBACK(void);
1090 extern void ADC1_CH19_CALLBACK(void);
1091 extern void ADC1_SQ0_CALLBACK(void);
1092 extern void ADC1_SQ1_CALLBACK(void);
1093 extern void ADC1_SQ2_CALLBACK(void);
1094 extern void ADC1_SQ3_CALLBACK(void);
1095 extern void ADC1_LOTH0_CALLBACK(void);
1096 extern void ADC1_LOTH1_CALLBACK(void);
1097 extern void ADC1_LOTH2_CALLBACK(void);
1098 extern void ADC1_LOTH3_CALLBACK(void);
1099 extern void ADC1_UPTH0_CALLBACK(void);
1100 extern void ADC1_UPTH1_CALLBACK(void);
1101 extern void ADC1_UPTH2_CALLBACK(void);
1102 extern void ADC1_UPTH3_CALLBACK(void);
1103 extern void ADC1_COLL0_CALLBACK(void);
1104 extern void ADC1_COLL1_CALLBACK(void);
1105 extern void ADC1_COLL2_CALLBACK(void);
1106 extern void ADC1_COLL3_CALLBACK(void);
1107 extern void ADC1_WFR0_CALLBACK(void);
1108 extern void ADC1_WFR1_CALLBACK(void);
1109 extern void ADC1_WFR2_CALLBACK(void);
1110 extern void ADC1_WFR3_CALLBACK(void);
1111 extern void BDRV_PH1_ZC_RISE_CALLBACK(void);
1112 extern void BDRV_PH1_ZC_FALL_CALLBACK(void);
1113 extern void BDRV_PH2_ZC_RISE_CALLBACK(void);
1114 extern void BDRV_PH2_ZC_FALL_CALLBACK(void);
1115 extern void BDRV_PH3_ZC_RISE_CALLBACK(void);
1116 extern void BDRV_PH3_ZC_FALL_CALLBACK(void);
1117 extern void SDADC_RES0_CALLBACK(void);
1118 extern void SDADC_CMP0_UP_CALLBACK(void);
1119 extern void SDADC_CMP0_LO_CALLBACK(void);
1120 extern void SDADC_RES1_CALLBACK(void);
1121 extern void SDADC_CMP1_UP_CALLBACK(void);
1122 extern void SDADC_CMP1_LO_CALLBACK(void);
1131 extern void UART0_TI_CALLBACK(void);
1132 extern void UART0_RI_CALLBACK(void);
1133 extern void UART0_EOS_CALLBACK(void);
1134 extern void UART0_SYNCERR_CALLBACK(void);
1135 extern void UART1_TI_CALLBACK(void);
1136 extern void UART1_RI_CALLBACK(void);
1137 extern void UART1_EOS_CALLBACK(void);
1138 extern void UART1_SYNCERR_CALLBACK(void);
1139 extern void SSC0_TI_CALLBACK(void);
1140 extern void SSC0_RI_CALLBACK(void);
1141 extern void SSC0_TEI_CALLBACK(void);
1142 extern void SSC0_REI_CALLBACK(void);
1143 extern void SSC0_PEI_CALLBACK(void);
1144 extern void SSC0_BEI_CALLBACK(void);
1145 extern void SSC1_TI_CALLBACK(void);
1146 extern void SSC1_RI_CALLBACK(void);
1147 extern void SSC1_TEI_CALLBACK(void);
1148 extern void SSC1_REI_CALLBACK(void);
1149 extern void SSC1_PEI_CALLBACK(void);
1150 extern void SSC1_BEI_CALLBACK(void);
1153 extern void CANNODE_NODE0_LEC_CALLBACK(void);
1156 extern void CANNODE_NODE0_LLE_CALLBACK(void);
1157 extern void CANNODE_NODE0_LOE_CALLBACK(void);
1287 extern void DMA_CH0_CALLBACK(void);
1288 extern void DMA_CH1_CALLBACK(void);
1289 extern void DMA_CH2_CALLBACK(void);
1290 extern void DMA_CH3_CALLBACK(void);
1291 extern void DMA_CH4_CALLBACK(void);
1292 extern void DMA_CH5_CALLBACK(void);
1293 extern void DMA_CH6_CALLBACK(void);
1294 extern void DMA_CH7_CALLBACK(void);
1295 extern void DMA_ERROR_CALLBACK(void);
1296 extern void T20_EXF2_CALLBACK(void);
1297 extern void T20_TF2_CALLBACK(void);
1298 extern void T21_EXF2_CALLBACK(void);
1299 extern void T21_TF2_CALLBACK(void);
1300 
1301 /*******************************************************************************
1302 ** Global Function Definitions **
1303 *******************************************************************************/
1309 {
1310  return u32_globTimestamp_ms;
1311 }
1312 
1313 #endif /* _ISR_H */
1314 
Interrupt Service Routines low level access library.
void SCU_EXTINT1_RISING_CALLBACK(void)
void PMU_VDDEXT_OT_CALLBACK(void)
void MON_MON3_F_CALLBACK(void)
void CCU7_WRONG_HALL_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXPND_CALLBACK(void)
void ADC1_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG3_TXPND_CALLBACK(void)
void CPU_PENDSV_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXOVF_CALLBACK(void)
void NVIC_IRQ28_Handler(void)
Definition: startup_tle989x.c:274
void CPU_USAGEFAULT_CALLBACK(void)
void BDRV_LS2_OC_CALLBACK(void)
void DMA_CH4_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXPND_CALLBACK(void)
void BDRV_HB3_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXPND_CALLBACK(void)
void ADC1_UPTH2_CALLBACK(void)
void NVIC_IRQ3_Handler(void)
Definition: startup_tle989x.c:249
void CANNODE_NODE0_BOFF_CALLBACK(void)
void CCU7_T12_PM_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXOVF_CALLBACK(void)
void ADC1_WFR0_CALLBACK(void)
void NVIC_IRQ26_Handler(void)
Definition: startup_tle989x.c:272
void CANMSGOBJ0_MSG3_TXOVF_CALLBACK(void)
void MEMCTRL_NMICON_NMIDSEN_CALLBACK(void)
void DMA_CH6_CALLBACK(void)
void ADC1_WFR2_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXPND_CALLBACK(void)
void SSC1_BEI_CALLBACK(void)
void NVIC_IRQ21_Handler(void)
Definition: startup_tle989x.c:267
void CANMSGOBJ0_MSG4_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXOVF_CALLBACK(void)
void ADC1_CH0_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXPND_CALLBACK(void)
void ADC1_LOTH1_CALLBACK(void)
void ADC2_CH1_CALLBACK(void)
void T21_TF2_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP1EN_CALLBACK(void)
void CANNODE_NODE0_RXOK_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXPND_CALLBACK(void)
void SSC0_REI_CALLBACK(void)
void BDRV_LS2_DS_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXOVF_CALLBACK(void)
void SDADC_CMP0_UP_CALLBACK(void)
void CSACSC_OC_CALLBACK(void)
void SCU_EXTINT1_FALLING_CALLBACK(void)
void SCU_NMICON_NMIXTALEN_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXOVF_CALLBACK(void)
void NVIC_IRQ10_Handler(void)
Definition: startup_tle989x.c:256
void CANMSGOBJ0_MSG28_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXPND_CALLBACK(void)
void UsageFault_Handler(void)
UsageFault ISR.
Definition: startup_tle989x.c:234
void T21_EXF2_CALLBACK(void)
void ADC1_COLL0_CALLBACK(void)
void CCU7_C71B_CM_R_CALLBACK(void)
void PMU_VDDP_OV_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG7_RXPND_CALLBACK(void)
void NVIC_IRQ20_Handler(void)
Definition: startup_tle989x.c:266
void CANMSGOBJ0_MSG21_TXOVF_CALLBACK(void)
void UART0_RI_CALLBACK(void)
void BDRV_PH1_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXPND_CALLBACK(void)
void HardFault_Handler(void)
HardFault ISR.
Definition: startup_tle989x.c:231
void MON_MON2_F_CALLBACK(void)
void ADC1_COLL1_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXOVF_CALLBACK(void)
void SDADC_RES1_CALLBACK(void)
void SSC0_PEI_CALLBACK(void)
void CCU7_CC71A_CM_F_CALLBACK(void)
void CCU7_T12_OM_CALLBACK(void)
void BDRV_PH2_ZC_FALL_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXOVF_CALLBACK(void)
void UART0_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXPND_CALLBACK(void)
void MemManage_Handler(void)
MemManage ISR.
Definition: startup_tle989x.c:232
void SCU_EXTINT3_FALLING_CALLBACK(void)
void ADC1_UPTH1_CALLBACK(void)
void NVIC_IRQ17_Handler(void)
Definition: startup_tle989x.c:263
void NVIC_IRQ1_Handler(void)
Definition: startup_tle989x.c:247
void ADC2_SQ1_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXOVF_CALLBACK(void)
void ADC2_UPTH4_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXPND_CALLBACK(void)
void MEMCTRL_NMICON_NMIPSEN_CALLBACK(void)
void PMU_VDDC_UVWARN_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXPND_CALLBACK(void)
void MON_MON2_R_CALLBACK(void)
void NVIC_IRQ29_Handler(void)
Definition: startup_tle989x.c:275
void CANMSGOBJ0_MSG19_RXPND_CALLBACK(void)
void CCU7_CC70A_CM_F_CALLBACK(void)
void MON_MON3_R_CALLBACK(void)
void UART1_SYNCERR_CALLBACK(void)
void SCU_NMICON_NMIPLL1EN_CALLBACK(void)
void CANMSGOBJ0_MSG16_RXPND_CALLBACK(void)
void MEMCTRL_NVM1_OP_COMPLETE_CALLBACK(void)
void BDRV_HS2_DS_CALLBACK(void)
void CCU7_T15_CM_CALLBACK(void)
void MEMCTRL_NMICON_NMICDEN_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXOVF_CALLBACK(void)
void ADC1_CH7_CALLBACK(void)
void ADC1_CH17_CALLBACK(void)
void BDRV_HS2_OC_CALLBACK(void)
void SDADC_CMP1_UP_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXOVF_CALLBACK(void)
void CCU7_T14_PM_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXPND_CALLBACK(void)
void GPT12_GPT1T4_CALLBACK(void)
void ADC2_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXOVF_CALLBACK(void)
void BDRV_SEQ_ERR_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXOVF_CALLBACK(void)
void CSACSC_PARAM_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXPND_CALLBACK(void)
void CANTRX_BUS_TO_CALLBACK(void)
void CCU7_T16_CM_CALLBACK(void)
void ADC1_CH5_CALLBACK(void)
void NVIC_IRQ12_Handler(void)
Definition: startup_tle989x.c:258
void UART0_SYNCERR_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXOVF_CALLBACK(void)
void ADC1_CH16_CALLBACK(void)
void CANMSGOBJ0_MSG4_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXOVF_CALLBACK(void)
void BDRV_HS3_OC_CALLBACK(void)
void ADC1_CH19_CALLBACK(void)
void CCU7_MCM_STR_CALLBACK(void)
void UART1_TI_CALLBACK(void)
void NVIC_IRQ7_Handler(void)
Definition: startup_tle989x.c:253
void SDADC_CMP0_LO_CALLBACK(void)
void SCU_EXTINT0_FALLING_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXOVF_CALLBACK(void)
void ADC2_CH0_CALLBACK(void)
void SDADC_CMP1_LO_CALLBACK(void)
void ADC1_LOTH0_CALLBACK(void)
void ADC2_CH6_CALLBACK(void)
void UART1_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXOVF_CALLBACK(void)
void PMU_VDDC_OV_CALLBACK(void)
void PendSV_Handler(void)
PendSV ISR.
Definition: startup_tle989x.c:241
void NVIC_IRQ27_Handler(void)
Definition: startup_tle989x.c:273
void CCU7_C70B_CM_F_CALLBACK(void)
void SCU_NMICON_NMIPLL0EN_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXPND_CALLBACK(void)
void CCU7_T15_PM_CALLBACK(void)
void GPT12_GPT1T2_CALLBACK(void)
void BDRV_HS3_DS_CALLBACK(void)
void SCU_EXTINT2_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXOVF_CALLBACK(void)
void NVIC_IRQ31_Handler(void)
Definition: startup_tle989x.c:278
void NMI_Handler(void)
NMI ISR.
Definition: startup_tle989x.c:230
void DMA_CH2_CALLBACK(void)
void ADC1_CH10_CALLBACK(void)
void ADC1_CH1_CALLBACK(void)
void ADC2_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXPND_CALLBACK(void)
void BDRV_LS3_DS_CALLBACK(void)
void NVIC_IRQ9_Handler(void)
Definition: startup_tle989x.c:255
void CANMSGOBJ0_MSG19_TXPND_CALLBACK(void)
void MON_MON1_R_CALLBACK(void)
void NVIC_IRQ8_Handler(void)
Definition: startup_tle989x.c:254
void NVIC_IRQ6_Handler(void)
void CANMSGOBJ0_MSG27_RXOVF_CALLBACK(void)
void BDRV_LS1_DS_CALLBACK(void)
void BDRV_LS3_OC_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXOVF_CALLBACK(void)
void ADC2_CH5_CALLBACK(void)
void SSC0_RI_CALLBACK(void)
void CCU7_LI_CALLBACK(void)
void MEMCTRL_NMICON_NMISTOFEN_CALLBACK(void)
void DMA_CH0_CALLBACK(void)
void ADC2_LOTH7_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXPND_CALLBACK(void)
void CPU_MEMMANAGE_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXOVF_CALLBACK(void)
void GPT12_GPT2CAPREL_CALLBACK(void)
void BDRV_PH3_ZC_FALL_CALLBACK(void)
void CPU_HARDFAULT_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXPND_CALLBACK(void)
void SDADC_RES0_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM0EN_CALLBACK(void)
void ADC1_UPTH0_CALLBACK(void)
void CANMSGOBJ0_MSG21_TXPND_CALLBACK(void)
void ADC1_WFR1_CALLBACK(void)
void NVIC_IRQ13_Handler(void)
Definition: startup_tle989x.c:259
void CANMSGOBJ0_MSG16_RXOVF_CALLBACK(void)
void NVIC_IRQ16_Handler(void)
Definition: startup_tle989x.c:262
void ADC2_LOTH0_CALLBACK(void)
void SCU_EXTINT3_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXPND_CALLBACK(void)
void SSC1_PEI_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM1EN_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXOVF_CALLBACK(void)
void CCU7_T13_PM_CALLBACK(void)
void ADC1_CH13_CALLBACK(void)
void UART0_TI_CALLBACK(void)
void PMU_VDDEXT_UV_CALLBACK(void)
void BusFault_Handler(void)
BusFault ISR.
Definition: startup_tle989x.c:233
void CANMSGOBJ0_MSG28_RXPND_CALLBACK(void)
void ADC2_CH11_CALLBACK(void)
void ADC2_CH3_CALLBACK(void)
void ADC2_CH4_CALLBACK(void)
void ADC1_COLL2_CALLBACK(void)
void ADC1_UPTH3_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXPND_CALLBACK(void)
void NVIC_IRQ0_Handler(void)
Definition: startup_tle989x.c:246
void BDRV_HB1_ASEQ_CALLBACK(void)
void ADC2_UPTH6_CALLBACK(void)
void ADC2_UPTH5_CALLBACK(void)
void BDRV_PH1_ZC_FALL_CALLBACK(void)
void MEMCTRL_NVM0_OP_COMPLETE_CALLBACK(void)
void GPT12_GPT2T5_CALLBACK(void)
void ADC1_CH11_CALLBACK(void)
void ADC1_LOTH2_CALLBACK(void)
void ADC2_UPTH1_CALLBACK(void)
void MEMCTRL_NMICON_NMIWDTEN_CALLBACK(void)
void CCU7_T13_CM_CALLBACK(void)
void ADC1_CH4_CALLBACK(void)
void ADC1_LOTH3_CALLBACK(void)
void PMU_VDDP_UVWARN_CALLBACK(void)
void CCU7_T14_CM_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXOVF_CALLBACK(void)
void CCU7_T16_PM_CALLBACK(void)
void CANTRX_OT_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXPND_CALLBACK(void)
void CCU7_CC72A_CM_R_CALLBACK(void)
void BDRV_HB2_ACTDRV_CALLBACK(void)
void ADC2_CH10_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXPND_CALLBACK(void)
void NVIC_IRQ5_Handler(void)
Definition: startup_tle989x.c:251
void ADC1_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_RXPND_CALLBACK(void)
void ADC1_CH18_CALLBACK(void)
void SSC1_REI_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXOVF_CALLBACK(void)
void ADC1_CH12_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXOVF_CALLBACK(void)
void SCU_EXTINT0_RISING_CALLBACK(void)
void SSC1_TEI_CALLBACK(void)
void NVIC_IRQ24_Handler(void)
Definition: startup_tle989x.c:270
void SSC0_BEI_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXPND_CALLBACK(void)
void NVIC_IRQ18_Handler(void)
Definition: startup_tle989x.c:264
void CCU7_CC72A_CM_F_CALLBACK(void)
void T20_EXF2_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG19_TXOVF_CALLBACK(void)
void NVIC_IRQ25_Handler(void)
Definition: startup_tle989x.c:271
void NVIC_IRQ22_Handler(void)
Definition: startup_tle989x.c:268
void CANMSGOBJ0_MSG7_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXPND_CALLBACK(void)
void ADC2_UPTH2_CALLBACK(void)
void ADC2_LOTH6_CALLBACK(void)
void ADC2_UPTH3_CALLBACK(void)
void DMA_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXPND_CALLBACK(void)
void DMA_CH5_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXPND_CALLBACK(void)
void SSC1_RI_CALLBACK(void)
void SysTick_Handler(void)
SysTick ISR.
Definition: startup_tle989x.c:243
void ADC2_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXPND_CALLBACK(void)
void UART1_RI_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXPND_CALLBACK(void)
void ADC2_LOTH3_CALLBACK(void)
void DMA_CH1_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXPND_CALLBACK(void)
void CCU7_C70B_CM_R_CALLBACK(void)
void CANNODE_NODE0_LEC_CALLBACK(void)
void CANMSGOBJ0_MSG19_RXOVF_CALLBACK(void)
void CPU_SYSTICK_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXPND_CALLBACK(void)
void ADC2_CH13_CALLBACK(void)
void CANNODE_NODE0_EWRN_CALLBACK(void)
void CANNODE_NODE0_LOE_CALLBACK(void)
void NVIC_IRQ11_Handler(void)
Definition: startup_tle989x.c:257
void CANMSGOBJ0_MSG6_RXOVF_CALLBACK(void)
volatile uint32 u32_globTimestamp_ms
Definition: isr_exceptions.c:25
void ADC1_SQ2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXOVF_CALLBACK(void)
void ADC2_LOTH1_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXOVF_CALLBACK(void)
void NVIC_IRQ23_Handler(void)
Definition: startup_tle989x.c:269
void ADC1_CH15_CALLBACK(void)
void NVIC_IRQ19_Handler(void)
Definition: startup_tle989x.c:265
void ADC2_SQ3_CALLBACK(void)
void ADC1_CH8_CALLBACK(void)
void ADC2_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXPND_CALLBACK(void)
void SCU_EXTINT2_FALLING_CALLBACK(void)
void CCU7_CC70A_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXOVF_CALLBACK(void)
void NVIC_IRQ30_Handler(void)
Definition: startup_tle989x.c:276
void DMA_ERROR_CALLBACK(void)
void GPT12_GPT2T6_CALLBACK(void)
void ADC2_CH9_CALLBACK(void)
void MON_MON1_F_CALLBACK(void)
void CANMSGOBJ0_MSG6_RXPND_CALLBACK(void)
void CANNODE_NODE0_CFCOV_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXPND_CALLBACK(void)
void ADC2_CH2_CALLBACK(void)
void CCU7_C72B_CM_F_CALLBACK(void)
void SSC0_TEI_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXOVF_CALLBACK(void)
void CCU7_TRAP_CALLBACK(void)
void ADC2_SQ2_CALLBACK(void)
void SSC0_TI_CALLBACK(void)
void ADC2_CH12_CALLBACK(void)
void CCU7_CC71A_CM_R_CALLBACK(void)
void ADC1_CH3_CALLBACK(void)
void BDRV_PH3_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG8_RXPND_CALLBACK(void)
void CCU7_C71B_CM_F_CALLBACK(void)
void ARVG_VAREF_OC_CALLBACK(void)
void ADC1_COLL3_CALLBACK(void)
void ADC2_LOTH5_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXPND_CALLBACK(void)
void CANTRX_TXD_TO_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXPND_CALLBACK(void)
void NVIC_IRQ15_Handler(void)
Definition: startup_tle989x.c:261
void NVIC_IRQ2_Handler(void)
Definition: startup_tle989x.c:248
void BDRV_LS1_OC_CALLBACK(void)
void BDRV_HB1_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXOVF_CALLBACK(void)
void BDRV_HB2_ASEQ_CALLBACK(void)
void ADC1_SQ1_CALLBACK(void)
void CPU_BUSFAULT_CALLBACK(void)
void SSC1_TI_CALLBACK(void)
void DMA_CH3_CALLBACK(void)
void ADC2_CH8_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXPND_CALLBACK(void)
void T20_TF2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXPND_CALLBACK(void)
void BDRV_HS1_OC_CALLBACK(void)
void GPT12_GPT1T3_CALLBACK(void)
void BDRV_HB3_ASEQ_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXOVF_CALLBACK(void)
void CCU7_CORRECT_HALL_CALLBACK(void)
void BDRV_PH2_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXPND_CALLBACK(void)
void NVIC_IRQ14_Handler(void)
Definition: startup_tle989x.c:260
void CANMSGOBJ0_MSG4_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXPND_CALLBACK(void)
void NVIC_IRQ4_Handler(void)
Definition: startup_tle989x.c:250
void CANMSGOBJ0_MSG8_RXOVF_CALLBACK(void)
void CANNODE_NODE0_TXOK_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP0EN_CALLBACK(void)
void ADC2_LOTH4_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXOVF_CALLBACK(void)
void ADC1_WFR3_CALLBACK(void)
void ADC2_UPTH0_CALLBACK(void)
void ADC2_UPTH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXPND_CALLBACK(void)
void ADC1_CH6_CALLBACK(void)
void ADC1_CH9_CALLBACK(void)
void CANNODE_NODE0_LLE_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXOVF_CALLBACK(void)
void BDRV_VCP_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXPND_CALLBACK(void)
void BDRV_HS1_DS_CALLBACK(void)
void CCU7_C72B_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXPND_CALLBACK(void)
INLINE uint32 INT_getGlobTimestamp(void)
Get the global timestamp value.
Definition: isr.h:1308
void ADC1_CH2_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG4_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXOVF_CALLBACK(void)
void CANTRX_BUS_ACT_CALLBACK(void)
void ADC1_SQ3_CALLBACK(void)
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:151
uint8_t uint8
8 bit unsigned value
Definition: types.h:204
uint32_t uint32
32 bit unsigned value
Definition: types.h:206