Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
dma.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
22 /*******************************************************************************
23 ** Author(s) Identity **
24 ********************************************************************************
25 ** Initials Name **
26 ** ---------------------------------------------------------------------------**
27 ** BG Blandine Guillot **
28 ** JO Julia Ott **
29 *******************************************************************************/
30 
31 /*******************************************************************************
32 ** Revision Control History **
33 ********************************************************************************
34 ** V0.1.0: 2021-03-03, BG: Initial version **
35 ** V0.2.0: 2021-06-08, BG: EP-685: Replaced UC_RAM_SIZE with UC_DSRAM_SIZE **
36 ** V0.2.1: 2021-06-14, BG: EP-685: Added functions for the endless mode **
37 ** V0.2.2: 2021-06-21, BG: EP-685: Updated init function with return code **
38 ** V0.2.3: 2021-07-30, BG: EP-877: Corrected MISRA 2012 errors **
39 ** V0.2.4: 2021-08-11, BG: EP-905: Added missing scu_defines.h **
40 ** V0.2.5: 2021-08-16, JO: EP-860: Added variable u32p_DMA_entriesForTest **
41 ** for unit testing **
42 ** V0.2.6: 2021-09-07, BG: EP-922: Added support for ARMCC V5 **
43 ** V0.2.7: 2021-11-12, JO: EP-937: Updated copyright and branding **
44 ** V0.2.8: 2022-04-27, JO: EP-1139: Corrected doxygen errors/warnings **
45 ** V0.2.9: 2022-06-22, JO: EP-1146: Added initialization of SCU->DMACTRL **
46 ** and DMA->DMA_CFG.bit.MASTER_ENABLE **
47 ** V0.3.0: 2022-06-23, JO: EP-1157: Added function DMA_setSWReq **
48 ** V0.3.1: 2022-06-23, JO: EP-1150: Removed ARMCC V6.18 warnings **
49 ** V0.3.2: 2022-11-17, JO: EP-1342: Updated enum documentation to remove **
50 ** doxygen warning **
51 ** V0.3.3: 2024-11-05, JO: EP-1494: Updated license **
52 *******************************************************************************/
53 
54 #ifndef _DMA_H
55 #define _DMA_H
56 
57 /*******************************************************************************
58 ** Includes **
59 *******************************************************************************/
60 
61 #include "types.h"
62 #include "tle989x.h"
63 #include "tle_variants.h"
64 #include "dma_defines.h"
65 
66 /*******************************************************************************
67 ** Global Constant Declarations **
68 *******************************************************************************/
69 
70 /*******************************************************************************
71 ** Global Type Declarations **
72 *******************************************************************************/
73 
78 typedef enum DMA_transferSize
79 {
84 
89 typedef enum DMA_incrementSize
90 {
95 
100 typedef enum DMA_incrementMode
101 {
107 
112 typedef enum DMA_cycleType
113 {
123 
127 typedef union
128 {
130  struct
131  {
142  } bit;
143 } tDMA_ctrl;
144 
148 typedef struct DMA_entry
149 {
155 
156 /*******************************************************************************
157 ** Global Macro Declarations **
158 *******************************************************************************/
159 
161 #define DMA_CH0 (0u)
163 #define DMA_CH1 (1u)
165 #define DMA_CH2 (2u)
167 #define DMA_CH3 (3u)
169 #define DMA_CH4 (4u)
171 #define DMA_CH5 (5u)
173 #define DMA_CH6 (6u)
175 #define DMA_CH7 (7u)
176 
178 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
180 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
182 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
184 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
186 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
188 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
190 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
192 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
193 
194 
195 /*******************************************************************************
196 ** Global Function Declarations **
197 *******************************************************************************/
198 
199 sint8 DMA_init(void);
200 void DMA_setBasicTransfer(uint8 u8_chIdx, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode);
201 void DMA_resetChannel(uint8 u8_chIdx, uint32 u32_transferCnt);
202 void DMA_setMemSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt);
203 void DMA_setPerSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt);
204 tDMA_entry *DMA_setPrimaryTaskSctGth(tDMA_entry *s_primEntry, uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt);
205 tDMA_entry *DMA_setTaskSctGth(tDMA_entry *s_entry, tDMA_cycleType e_cycleType, uint8 u8_Rpower, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode);
206 INLINE void DMA_enMaster(void);
207 INLINE void DMA_enCh0EndlessMode(void);
208 INLINE void DMA_disCh0EndlessMode(void);
209 INLINE void DMA_enCh1EndlessMode(void);
210 INLINE void DMA_disCh1EndlessMode(void);
211 INLINE void DMA_enCh2EndlessMode(void);
212 INLINE void DMA_disCh2EndlessMode(void);
213 INLINE void DMA_enCh3EndlessMode(void);
214 INLINE void DMA_disCh3EndlessMode(void);
215 INLINE void DMA_enCh4EndlessMode(void);
216 INLINE void DMA_disCh4EndlessMode(void);
217 INLINE void DMA_enCh5EndlessMode(void);
218 INLINE void DMA_disCh5EndlessMode(void);
219 INLINE void DMA_enCh6EndlessMode(void);
220 INLINE void DMA_disCh6EndlessMode(void);
221 INLINE void DMA_enCh7EndlessMode(void);
222 INLINE void DMA_disCh7EndlessMode(void);
223 INLINE void DMA_enCh0Int(void);
224 INLINE void DMA_disCh0Int(void);
225 INLINE void DMA_enCh1Int(void);
226 INLINE void DMA_disCh1Int(void);
227 INLINE void DMA_enCh2Int(void);
228 INLINE void DMA_disCh2Int(void);
229 INLINE void DMA_enCh3Int(void);
230 INLINE void DMA_disCh3Int(void);
231 INLINE void DMA_enCh4Int(void);
232 INLINE void DMA_disCh4Int(void);
233 INLINE void DMA_enCh5Int(void);
234 INLINE void DMA_disCh5Int(void);
235 INLINE void DMA_enCh6Int(void);
236 INLINE void DMA_disCh6Int(void);
237 INLINE void DMA_enCh7Int(void);
238 INLINE void DMA_disCh7Int(void);
239 INLINE void DMA_enErrInt(void);
240 INLINE void DMA_disErrInt(void);
249 INLINE void DMA_clrCh0IntSts(void);
250 INLINE void DMA_clrCh1IntSts(void);
251 INLINE void DMA_clrCh2IntSts(void);
252 INLINE void DMA_clrCh3IntSts(void);
253 INLINE void DMA_clrCh4IntSts(void);
254 INLINE void DMA_clrCh5IntSts(void);
255 INLINE void DMA_clrCh6IntSts(void);
256 INLINE void DMA_clrCh7IntSts(void);
257 INLINE void DMA_setSWReq(uint8 u8_chIdx);
258 
259 /*******************************************************************************
260 ** Deprecated Function Declarations **
261 *******************************************************************************/
262 
266 void DMA_setCh0IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
267 
271 void DMA_setCh1IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
272 
276 void DMA_setCh2IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
277 
281 void DMA_setCh3IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
282 
286 void DMA_setCh4IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
287 
291 void DMA_setCh5IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
292 
296 void DMA_setCh6IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
297 
301 void DMA_setCh7IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
302 
306 void DMA_setErrIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
307 
308 /*******************************************************************************
309 ** Global Inline Function Definitions **
310 *******************************************************************************/
311 
315 {
316  DMA->DMA_CFG.bit.MASTER_ENABLE = 1u;
317 }
318 
322 {
323  SCU->DMACTRL.bit.DEMEN_CH0 = 1u;
324 }
325 
329 {
330  SCU->DMACTRL.bit.DEMEN_CH0 = 0u;
331 }
332 
336 {
337  SCU->DMACTRL.bit.DEMEN_CH1 = 1u;
338 }
339 
343 {
344  SCU->DMACTRL.bit.DEMEN_CH1 = 0u;
345 }
346 
350 {
351  SCU->DMACTRL.bit.DEMEN_CH2 = 1u;
352 }
353 
357 {
358  SCU->DMACTRL.bit.DEMEN_CH2 = 0u;
359 }
360 
364 {
365  SCU->DMACTRL.bit.DEMEN_CH3 = 1u;
366 }
367 
371 {
372  SCU->DMACTRL.bit.DEMEN_CH3 = 0u;
373 }
374 
378 {
379  SCU->DMACTRL.bit.DEMEN_CH4 = 1u;
380 }
381 
385 {
386  SCU->DMACTRL.bit.DEMEN_CH4 = 0u;
387 }
388 
392 {
393  SCU->DMACTRL.bit.DEMEN_CH5 = 1u;
394 }
395 
399 {
400  SCU->DMACTRL.bit.DEMEN_CH5 = 0u;
401 }
402 
406 {
407  SCU->DMACTRL.bit.DEMEN_CH6 = 1u;
408 }
409 
413 {
414  SCU->DMACTRL.bit.DEMEN_CH6 = 0u;
415 }
416 
420 {
421  SCU->DMACTRL.bit.DEMEN_CH7 = 1u;
422 }
423 
427 {
428  SCU->DMACTRL.bit.DEMEN_CH7 = 0u;
429 }
430 
434 {
435  SCU->DMAIEN.bit.DMACH0EN = 1u;
436 }
437 
441 {
442  SCU->DMAIEN.bit.DMACH0EN = 0u;
443 }
444 
448 {
449  SCU->DMAIEN.bit.DMACH1EN = 1u;
450 }
451 
455 {
456  SCU->DMAIEN.bit.DMACH1EN = 0u;
457 }
458 
462 {
463  SCU->DMAIEN.bit.DMACH2EN = 1u;
464 }
465 
469 {
470  SCU->DMAIEN.bit.DMACH2EN = 0u;
471 }
472 
476 {
477  SCU->DMAIEN.bit.DMACH3EN = 1u;
478 }
479 
483 {
484  SCU->DMAIEN.bit.DMACH3EN = 0u;
485 }
486 
490 {
491  SCU->DMAIEN.bit.DMACH4EN = 1u;
492 }
493 
497 {
498  SCU->DMAIEN.bit.DMACH4EN = 0u;
499 }
500 
504 {
505  SCU->DMAIEN.bit.DMACH5EN = 1u;
506 }
507 
511 {
512  SCU->DMAIEN.bit.DMACH5EN = 0u;
513 }
514 
518 {
519  SCU->DMAIEN.bit.DMACH6EN = 1u;
520 }
521 
525 {
526  SCU->DMAIEN.bit.DMACH6EN = 0u;
527 }
528 
532 {
533  SCU->DMAIEN.bit.DMACH7EN = 1u;
534 }
535 
539 {
540  SCU->DMAIEN.bit.DMACH7EN = 0u;
541 }
542 
546 {
547  SCU->DMAIEN.bit.DMATRERREN = 1u;
548 }
549 
553 {
554  SCU->DMAIEN.bit.DMATRERREN = 0u;
555 }
556 
562 {
563  return (uint8)SCU->DMAIS.bit.DMACH0;
564 }
565 
571 {
572  return (uint8)SCU->DMAIS.bit.DMACH1;
573 }
574 
580 {
581  return (uint8)SCU->DMAIS.bit.DMACH2;
582 }
583 
589 {
590  return (uint8)SCU->DMAIS.bit.DMACH3;
591 }
592 
598 {
599  return (uint8)SCU->DMAIS.bit.DMACH4;
600 }
601 
607 {
608  return (uint8)SCU->DMAIS.bit.DMACH5;
609 }
610 
616 {
617  return (uint8)SCU->DMAIS.bit.DMACH6;
618 }
619 
625 {
626  return (uint8)SCU->DMAIS.bit.DMACH7;
627 }
628 
632 {
633  SCU->DMAISC.bit.DMACH0CLR = 1u;
634 }
635 
639 {
640  SCU->DMAISC.bit.DMACH1CLR = 1u;
641 }
642 
646 {
647  SCU->DMAISC.bit.DMACH2CLR = 1u;
648 }
649 
653 {
654  SCU->DMAISC.bit.DMACH3CLR = 1u;
655 }
656 
660 {
661  SCU->DMAISC.bit.DMACH4CLR = 1u;
662 }
663 
667 {
668  SCU->DMAISC.bit.DMACH5CLR = 1u;
669 }
670 
674 {
675  SCU->DMAISC.bit.DMACH6CLR = 1u;
676 }
677 
681 {
682  SCU->DMAISC.bit.DMACH7CLR = 1u;
683 }
688 INLINE void DMA_setSWReq(uint8 u8_chIdx)
689 {
690  DMA->CHNL_SW_REQUEST.reg = (uint32)((uint32)1u << u8_chIdx);
691 }
692 
693 #endif /* _DMA_H */
INLINE void DMA_enCh3EndlessMode(void)
Enable DMA Channel 3 Endless Mode.
Definition: dma.h:363
INLINE uint8 DMA_getCh1IntSts(void)
Get DMA Channel 1 Interrupt Status.
Definition: dma.h:570
void DMA_setCh7IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 7 Interrupt Node Pointer.
void DMA_setCh2IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 2 Interrupt Node Pointer.
void DMA_setCh1IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 1 Interrupt Node Pointer.
INLINE uint8 DMA_getCh6IntSts(void)
Get DMA Channel 6 Interrupt Status.
Definition: dma.h:615
INLINE void DMA_enCh5Int(void)
Enable DMA Channel 5 Interrupt.
Definition: dma.h:503
INLINE void DMA_enCh2Int(void)
Enable DMA Channel 2 Interrupt.
Definition: dma.h:461
INLINE uint8 DMA_getCh2IntSts(void)
Get DMA Channel 2 Interrupt Status.
Definition: dma.h:579
enum DMA_incrementSize tDMA_incrementSize
INLINE void DMA_disErrInt(void)
Disable DMA Transfer Error Interrupt.
Definition: dma.h:552
INLINE void DMA_disCh3Int(void)
Disable DMA Channel 3 Interrupt.
Definition: dma.h:482
INLINE uint8 DMA_getCh3IntSts(void)
Get DMA Channel 3 Interrupt Status.
Definition: dma.h:588
INLINE void DMA_enCh4EndlessMode(void)
Enable DMA Channel 4 Endless Mode.
Definition: dma.h:377
enum DMA_transferSize tDMA_transferSize
INLINE void DMA_enCh4Int(void)
Enable DMA Channel 4 Interrupt.
Definition: dma.h:489
DMA_incrementSize
This enum lists the increment size options for the DMA.
Definition: dma.h:90
@ DMA_incrementSize_16bit
Definition: dma.h:92
@ DMA_incrementSize_32bit
Definition: dma.h:93
@ DMA_incrementSize_8bit
Definition: dma.h:91
enum DMA_incrementMode tDMA_incrementMode
INLINE void DMA_enCh6Int(void)
Enable DMA Channel 6 Interrupt.
Definition: dma.h:517
INLINE void DMA_clrCh1IntSts(void)
Clear DMA Channel 1 Interrupt Status.
Definition: dma.h:638
INLINE void DMA_disCh1EndlessMode(void)
Disable DMA Channel 1 Endless Mode.
Definition: dma.h:342
void DMA_setCh5IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 5 Interrupt Node Pointer.
INLINE void DMA_enCh1EndlessMode(void)
Enable DMA Channel 1 Endless Mode.
Definition: dma.h:335
void DMA_setMemSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Memory Scatter-Gather mode on a given task list.
Definition: dma.c:1191
void DMA_setErrIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel Bus Error Interrupt Node Pointer.
tDMA_entry * DMA_setTaskSctGth(tDMA_entry *s_entry, tDMA_cycleType e_cycleType, uint8 u8_Rpower, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a task to be used in the scatter-gather mode.
Definition: dma.c:1295
DMA_cycleType
This enum lists the cycle type options for the DMA.
Definition: dma.h:113
@ DMA_cycleType_PerSctGthPrim
Definition: dma.h:120
@ DMA_cycleType_Auto
Definition: dma.h:116
@ DMA_cycleType_Invalid
Definition: dma.h:114
@ DMA_cycleType_MemSctGthAlt
Definition: dma.h:119
@ DMA_cycleType_MemSctGthPrim
Definition: dma.h:118
@ DMA_cycleType_PingPong
Definition: dma.h:117
@ DMA_cycleType_PerSctGthAlt
Definition: dma.h:121
@ DMA_cycleType_Basic
Definition: dma.h:115
INLINE void DMA_disCh7EndlessMode(void)
Disable DMA Channel 7 Endless Mode.
Definition: dma.h:426
INLINE void DMA_disCh6EndlessMode(void)
Disable DMA Channel 6 Endless Mode.
Definition: dma.h:412
INLINE uint8 DMA_getCh0IntSts(void)
Get DMA Channel 0 Interrupt Status.
Definition: dma.h:561
INLINE void DMA_disCh5EndlessMode(void)
Disable DMA Channel 5 Endless Mode.
Definition: dma.h:398
void DMA_setCh3IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 3 Interrupt Node Pointer.
INLINE void DMA_disCh2Int(void)
Disable DMA Channel 2 Interrupt.
Definition: dma.h:468
INLINE void DMA_disCh2EndlessMode(void)
Disable DMA Channel 2 Endless Mode.
Definition: dma.h:356
DMA_incrementMode
This enum lists the increment mode options for the DMA.
Definition: dma.h:101
@ DMA_incrementMode_srcInc
Definition: dma.h:102
@ DMA_incrementMode_dstInc
Definition: dma.h:103
@ DMA_incrementMode_noInc
Definition: dma.h:105
@ DMA_incrementMode_srcDstInc
Definition: dma.h:104
INLINE void DMA_enCh2EndlessMode(void)
Enable DMA Channel 2 Endless Mode.
Definition: dma.h:349
INLINE void DMA_clrCh2IntSts(void)
Clear DMA Channel 2 Interrupt Status.
Definition: dma.h:645
void DMA_setPerSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
Definition: dma.c:1224
INLINE void DMA_enCh3Int(void)
Enable DMA Channel 3 Interrupt.
Definition: dma.h:475
INLINE void DMA_enCh0EndlessMode(void)
Enable DMA Channel 0 Endless Mode.
Definition: dma.h:321
void DMA_setCh6IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 6 Interrupt Node Pointer.
INLINE void DMA_enErrInt(void)
Enable DMA Transfer Error Interrupt.
Definition: dma.h:545
INLINE void DMA_enMaster(void)
Enable DMA Master.
Definition: dma.h:314
INLINE void DMA_disCh0EndlessMode(void)
Disable DMA Channel 0 Endless Mode.
Definition: dma.h:328
INLINE void DMA_clrCh0IntSts(void)
Clear DMA Channel 0 Interrupt Status.
Definition: dma.h:631
INLINE void DMA_enCh0Int(void)
Enable DMA Channel 0 Interrupt.
Definition: dma.h:433
INLINE void DMA_disCh4EndlessMode(void)
Disable DMA Channel 4 Endless Mode.
Definition: dma.h:384
INLINE void DMA_enCh7EndlessMode(void)
Enable DMA Channel 7 Endless Mode.
Definition: dma.h:419
INLINE void DMA_disCh5Int(void)
Disable DMA Channel 5 Interrupt.
Definition: dma.h:510
DMA_transferSize
This enum lists the transfer size options for the DMA.
Definition: dma.h:79
@ DMA_transferSize_8bit
Definition: dma.h:80
@ DMA_transferSize_32bit
Definition: dma.h:82
@ DMA_transferSize_16bit
Definition: dma.h:81
enum DMA_cycleType tDMA_cycleType
void DMA_setCh4IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 4 Interrupt Node Pointer.
INLINE void DMA_enCh5EndlessMode(void)
Enable DMA Channel 5 Endless Mode.
Definition: dma.h:391
INLINE uint8 DMA_getCh4IntSts(void)
Get DMA Channel 4 Interrupt Status.
Definition: dma.h:597
void DMA_resetChannel(uint8 u8_chIdx, uint32 u32_transferCnt)
Reset the primary structure in RAM for a given channel and rearm it.
Definition: dma.c:1174
INLINE uint8 DMA_getCh5IntSts(void)
Get DMA Channel 5 Interrupt Status.
Definition: dma.h:606
INLINE void DMA_enCh1Int(void)
Enable DMA Channel 1 Interrupt.
Definition: dma.h:447
INLINE void DMA_disCh6Int(void)
Disable DMA Channel 6 Interrupt.
Definition: dma.h:524
INLINE void DMA_clrCh6IntSts(void)
Clear DMA Channel 6 Interrupt Status.
Definition: dma.h:673
INLINE void DMA_enCh6EndlessMode(void)
Enable DMA Channel 6 Endless Mode.
Definition: dma.h:405
INLINE void DMA_disCh1Int(void)
Disable DMA Channel 1 Interrupt.
Definition: dma.h:454
tDMA_entry * DMA_setPrimaryTaskSctGth(tDMA_entry *s_primEntry, uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up the primary task to configure the scatter-gather mode.
Definition: dma.c:1262
struct DMA_entry tDMA_entry
INLINE uint8 DMA_getCh7IntSts(void)
Get DMA Channel 7 Interrupt Status.
Definition: dma.h:624
sint8 DMA_init(void)
Initialize the DMA structure in RAM and SFRs according to the ConfigWizard settings.
Definition: dma.c:684
INLINE void DMA_enCh7Int(void)
Enable DMA Channel 7 Interrupt.
Definition: dma.h:531
INLINE void DMA_disCh3EndlessMode(void)
Disable DMA Channel 3 Endless Mode.
Definition: dma.h:370
INLINE void DMA_clrCh5IntSts(void)
Clear DMA Channel 5 Interrupt Status.
Definition: dma.h:666
INLINE void DMA_disCh7Int(void)
Disable DMA Channel 7 Interrupt.
Definition: dma.h:538
void DMA_setCh0IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 0 Interrupt Node Pointer.
void DMA_setBasicTransfer(uint8 u8_chIdx, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a basic transfer for the desired DMA channel in the primary structure in RAM.
Definition: dma.c:1084
INLINE void DMA_setSWReq(uint8 u8_chIdx)
Sets the SW request for the given channel.
Definition: dma.h:688
INLINE void DMA_disCh4Int(void)
Disable DMA Channel 4 Interrupt.
Definition: dma.h:496
INLINE void DMA_clrCh7IntSts(void)
Clear DMA Channel 7 Interrupt Status.
Definition: dma.h:680
INLINE void DMA_disCh0Int(void)
Disable DMA Channel 0 Interrupt.
Definition: dma.h:440
INLINE void DMA_clrCh3IntSts(void)
Clear DMA Channel 3 Interrupt Status.
Definition: dma.h:652
INLINE void DMA_clrCh4IntSts(void)
Clear DMA Channel 4 Interrupt Status.
Definition: dma.h:659
#define DMA
Definition: tle989x.h:24069
#define SCU
Definition: tle989x.h:24075
__attribute__((noreturn))
Definition: startup_tle989x.c:193
Definition: dma.h:149
uint32 u32_srcEndPtr
Definition: dma.h:150
tDMA_ctrl s_ctrl
Definition: dma.h:152
uint32 reserved
Definition: dma.h:153
uint32 u32_dstEndPtr
Definition: dma.h:151
This structure lists the DMA transfer memory locations.
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:151
uint8_t uint8
8 bit unsigned value
Definition: types.h:204
int8_t sint8
8 bit signed value
Definition: types.h:209
uint32_t uint32
32 bit unsigned value
Definition: types.h:206
This union and its structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:128
uint32 u32_cycleCtrl
Bit[2..0].
Definition: dma.h:132
uint32 u32_srcSize
Bit[25..24].
Definition: dma.h:138
uint32 u32_nextUseburst
Bit[3].
Definition: dma.h:133
uint32 u32_dstInc
Bit[31..30].
Definition: dma.h:141
uint32 u32_srcProtCtrl
Bit[20..18].
Definition: dma.h:136
uint32 u32_srcInc
Bit[27..26].
Definition: dma.h:139
uint32 u32_Rpower
Bit[17..14].
Definition: dma.h:135
uint32 u32_dstProtCtrl
Bit[23..21].
Definition: dma.h:137
uint32 u32_Nminus1
Bit[13..4].
Definition: dma.h:134
uint32 u32_dstSize
Bit[29..28].
Definition: dma.h:140
uint32 reg
Definition: dma.h:129