Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
int.h
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1 /*
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43 /* Generated by generate_functions_02_xlsx2func.py, version 0.9.0 on 20. Oct 2020
44  * from File 'cpu.xlsx', version 0.1.0
45  */
46 
47 /*******************************************************************************
48 ** Author(s) Identity **
49 ********************************************************************************
50 ** Initials Name **
51 ** ---------------------------------------------------------------------------**
52 ** JO Julia Ott **
53 ** BG Blandine Guillot **
54 ** DM Daniel Mysliwitz **
55 *******************************************************************************/
56 
57 /*******************************************************************************
58 ** Revision Control History **
59 ********************************************************************************
60 ** V0.1.0: 2019-10-28, DM: Initial version **
61 ** V0.2.0: 2020-04-28, BG: Updated revision history format **
62 ** V0.2.1: 2020-10-20, JO: EP-533: Added functions to set the priority of **
63 ** NVIC nodes **
64 ** Added functions to enable and disable NVIC nodes **
65 ** V0.2.2: 2020-11-12, JO: EP-590: Removed \param none and \return none to **
66 ** avoid doxygen warning **
67 ** V0.2.3: 2020-11-20, BG: EP-610: Corrected MISRA 2012 errors **
68 ** V0.2.4: 2020-11-27, BG: EP-627: Initialized registers for CANTRX **
69 ** EP-598: Initialized registers for ARVG **
70 ** V0.2.5: 2020-12-03, BG: EP-633: Added missing register for MON in the **
71 ** initialization **
72 ** V0.2.6: 2020-12-17, BG: EP-599: Added condition with UC_FEATURE_SDADC **
73 ** for init of SDADC int. **
74 ** V0.2.7: 2020-12-18, BG: EP-607: Removed precompiler condition for ADC2 **
75 ** V0.2.8: 2021-06-02, BG: EP-813: Corrected assigned values to PMU, CANTRX **
76 ** ARVG and CSACSC interrupt status clear registers **
77 ** V0.2.9: 2021-10-12, JO: EP-954: Added include of tle_variants.h to **
78 ** apply condition with UC_FEATURE_SDADC **
79 ** V0.3.0: 2021-10-22, BG: EP-964: Removed registers CONVSTATCLR for ADC1/2 **
80 ** in INT_init() **
81 ** V0.3.1: 2021-11-12, JO: EP-937: Updated copyright and branding **
82 *******************************************************************************/
83 
84 #ifndef _INT_H
85 #define _INT_H
86 
87 /*******************************************************************************
88 ** Includes **
89 *******************************************************************************/
90 
91 #include "types.h"
92 #include "tle_variants.h"
93 #include "tle989x.h"
94 #include "isr_defines.h"
95 #include "ccu7_defines.h"
96 
97 /*******************************************************************************
98 ** Global Macro Declarations **
99 *******************************************************************************/
100 
101 /*******************************************************************************
102 ** Global Type Declarations **
103 *******************************************************************************/
104 
105 /*******************************************************************************
106 ** Global Function Declarations **
107 *******************************************************************************/
108 INLINE void NVIC_disIRQ0(void);
109 INLINE void NVIC_disIRQ1(void);
110 INLINE void NVIC_disIRQ2(void);
111 INLINE void NVIC_disIRQ3(void);
112 INLINE void NVIC_disIRQ4(void);
113 INLINE void NVIC_disIRQ5(void);
114 INLINE void NVIC_disIRQ6(void);
115 INLINE void NVIC_disIRQ7(void);
116 INLINE void NVIC_disIRQ8(void);
117 INLINE void NVIC_disIRQ9(void);
118 INLINE void NVIC_disIRQ10(void);
119 INLINE void NVIC_disIRQ11(void);
120 INLINE void NVIC_disIRQ12(void);
121 INLINE void NVIC_disIRQ13(void);
122 INLINE void NVIC_disIRQ14(void);
123 INLINE void NVIC_disIRQ15(void);
124 INLINE void NVIC_disIRQ16(void);
125 INLINE void NVIC_disIRQ17(void);
126 INLINE void NVIC_disIRQ18(void);
127 INLINE void NVIC_disIRQ19(void);
128 INLINE void NVIC_disIRQ20(void);
129 INLINE void NVIC_disIRQ21(void);
130 INLINE void NVIC_disIRQ22(void);
131 INLINE void NVIC_disIRQ23(void);
132 INLINE void NVIC_disIRQ24(void);
133 INLINE void NVIC_disIRQ25(void);
134 INLINE void NVIC_disIRQ26(void);
135 INLINE void NVIC_disIRQ27(void);
136 INLINE void NVIC_disIRQ28(void);
137 INLINE void NVIC_disIRQ29(void);
138 INLINE void NVIC_disIRQ30(void);
139 INLINE void NVIC_disIRQ31(void);
140 INLINE void NVIC_setIRQ0Priority(uint8 u8_value);
141 INLINE void NVIC_setIRQ1Priority(uint8 u8_value);
142 INLINE void NVIC_setIRQ2Priority(uint8 u8_value);
143 INLINE void NVIC_setIRQ3Priority(uint8 u8_value);
144 INLINE void NVIC_setIRQ4Priority(uint8 u8_value);
145 INLINE void NVIC_setIRQ5Priority(uint8 u8_value);
146 INLINE void NVIC_setIRQ6Priority(uint8 u8_value);
147 INLINE void NVIC_setIRQ7Priority(uint8 u8_value);
148 INLINE void NVIC_setIRQ8Priority(uint8 u8_value);
149 INLINE void NVIC_setIRQ9Priority(uint8 u8_value);
150 INLINE void NVIC_setIRQ10Priority(uint8 u8_value);
151 INLINE void NVIC_setIRQ11Priority(uint8 u8_value);
152 INLINE void NVIC_setIRQ12Priority(uint8 u8_value);
153 INLINE void NVIC_setIRQ13Priority(uint8 u8_value);
154 INLINE void NVIC_setIRQ14Priority(uint8 u8_value);
155 INLINE void NVIC_setIRQ15Priority(uint8 u8_value);
156 INLINE void NVIC_setIRQ16Priority(uint8 u8_value);
157 INLINE void NVIC_setIRQ17Priority(uint8 u8_value);
158 INLINE void NVIC_setIRQ18Priority(uint8 u8_value);
159 INLINE void NVIC_setIRQ19Priority(uint8 u8_value);
160 INLINE void NVIC_setIRQ20Priority(uint8 u8_value);
161 INLINE void NVIC_setIRQ21Priority(uint8 u8_value);
162 INLINE void NVIC_setIRQ22Priority(uint8 u8_value);
163 INLINE void NVIC_setIRQ23Priority(uint8 u8_value);
164 INLINE void NVIC_setIRQ24Priority(uint8 u8_value);
165 INLINE void NVIC_setIRQ25Priority(uint8 u8_value);
166 INLINE void NVIC_setIRQ26Priority(uint8 u8_value);
167 INLINE void NVIC_setIRQ27Priority(uint8 u8_value);
168 INLINE void NVIC_setIRQ28Priority(uint8 u8_value);
169 INLINE void NVIC_setIRQ29Priority(uint8 u8_value);
170 INLINE void NVIC_setIRQ30Priority(uint8 u8_value);
171 INLINE void NVIC_setIRQ31Priority(uint8 u8_value);
172 INLINE void NVIC_enIRQ0(void);
173 INLINE void NVIC_enIRQ1(void);
174 INLINE void NVIC_enIRQ2(void);
175 INLINE void NVIC_enIRQ3(void);
176 INLINE void NVIC_enIRQ4(void);
177 INLINE void NVIC_enIRQ5(void);
178 INLINE void NVIC_enIRQ6(void);
179 INLINE void NVIC_enIRQ7(void);
180 INLINE void NVIC_enIRQ8(void);
181 INLINE void NVIC_enIRQ9(void);
182 INLINE void NVIC_enIRQ10(void);
183 INLINE void NVIC_enIRQ11(void);
184 INLINE void NVIC_enIRQ12(void);
185 INLINE void NVIC_enIRQ13(void);
186 INLINE void NVIC_enIRQ14(void);
187 INLINE void NVIC_enIRQ15(void);
188 INLINE void NVIC_enIRQ16(void);
189 INLINE void NVIC_enIRQ17(void);
190 INLINE void NVIC_enIRQ18(void);
191 INLINE void NVIC_enIRQ19(void);
192 INLINE void NVIC_enIRQ20(void);
193 INLINE void NVIC_enIRQ21(void);
194 INLINE void NVIC_enIRQ22(void);
195 INLINE void NVIC_enIRQ23(void);
196 INLINE void NVIC_enIRQ24(void);
197 INLINE void NVIC_enIRQ25(void);
198 INLINE void NVIC_enIRQ26(void);
199 INLINE void NVIC_enIRQ27(void);
200 INLINE void NVIC_enIRQ28(void);
201 INLINE void NVIC_enIRQ29(void);
202 INLINE void NVIC_enIRQ30(void);
203 INLINE void NVIC_enIRQ31(void);
204 void INT_init(void);
205 
206 /*******************************************************************************
207 ** Global Inline Function Definitions **
208 *******************************************************************************/
212 {
213  CPU->NVIC_ICER.bit.IRQCLREN0 = 0u;
214 }
215 
219 {
220  CPU->NVIC_ICER.bit.IRQCLREN1 = 0u;
221 }
222 
226 {
227  CPU->NVIC_ICER.bit.IRQCLREN2 = 0u;
228 }
229 
233 {
234  CPU->NVIC_ICER.bit.IRQCLREN3 = 0u;
235 }
236 
240 {
241  CPU->NVIC_ICER.bit.IRQCLREN4 = 0u;
242 }
243 
247 {
248  CPU->NVIC_ICER.bit.IRQCLREN5 = 0u;
249 }
250 
254 {
255  CPU->NVIC_ICER.bit.IRQCLREN6 = 0u;
256 }
257 
261 {
262  CPU->NVIC_ICER.bit.IRQCLREN7 = 0u;
263 }
264 
268 {
269  CPU->NVIC_ICER.bit.IRQCLREN8 = 0u;
270 }
271 
275 {
276  CPU->NVIC_ICER.bit.IRQCLREN9 = 0u;
277 }
278 
282 {
283  CPU->NVIC_ICER.bit.IRQCLREN10 = 0u;
284 }
285 
289 {
290  CPU->NVIC_ICER.bit.IRQCLREN11 = 0u;
291 }
292 
296 {
297  CPU->NVIC_ICER.bit.IRQCLREN12 = 0u;
298 }
299 
303 {
304  CPU->NVIC_ICER.bit.IRQCLREN13 = 0u;
305 }
306 
310 {
311  CPU->NVIC_ICER.bit.IRQCLREN14 = 0u;
312 }
313 
317 {
318  CPU->NVIC_ICER.bit.IRQCLREN15 = 0u;
319 }
320 
324 {
325  CPU->NVIC_ICER.bit.IRQCLREN16 = 0u;
326 }
327 
331 {
332  CPU->NVIC_ICER.bit.IRQCLREN17 = 0u;
333 }
334 
338 {
339  CPU->NVIC_ICER.bit.IRQCLREN18 = 0u;
340 }
341 
345 {
346  CPU->NVIC_ICER.bit.IRQCLREN19 = 0u;
347 }
348 
352 {
353  CPU->NVIC_ICER.bit.IRQCLREN20 = 0u;
354 }
355 
359 {
360  CPU->NVIC_ICER.bit.IRQCLREN21 = 0u;
361 }
362 
366 {
367  CPU->NVIC_ICER.bit.IRQCLREN22 = 0u;
368 }
369 
373 {
374  CPU->NVIC_ICER.bit.IRQCLREN23 = 0u;
375 }
376 
380 {
381  CPU->NVIC_ICER.bit.IRQCLREN24 = 0u;
382 }
383 
387 {
388  CPU->NVIC_ICER.bit.IRQCLREN25 = 0u;
389 }
390 
394 {
395  CPU->NVIC_ICER.bit.IRQCLREN26 = 0u;
396 }
397 
401 {
402  CPU->NVIC_ICER.bit.IRQCLREN27 = 0u;
403 }
404 
408 {
409  CPU->NVIC_ICER.bit.IRQCLREN28 = 0u;
410 }
411 
415 {
416  CPU->NVIC_ICER.bit.IRQCLREN29 = 0u;
417 }
418 
422 {
423  CPU->NVIC_ICER.bit.IRQCLREN30 = 0u;
424 }
425 
429 {
430  CPU->NVIC_ICER.bit.IRQCLREN31 = 0u;
431 }
432 
438 {
439  CPU->NVIC_IPR0.bit.PRI_N0 = u8_value;
440 }
441 
447 {
448  CPU->NVIC_IPR0.bit.PRI_N1 = u8_value;
449 }
450 
456 {
457  CPU->NVIC_IPR0.bit.PRI_N2 = u8_value;
458 }
459 
465 {
466  CPU->NVIC_IPR0.bit.PRI_N3 = u8_value;
467 }
468 
474 {
475  CPU->NVIC_IPR1.bit.PRI_N4 = u8_value;
476 }
477 
483 {
484  CPU->NVIC_IPR1.bit.PRI_N5 = u8_value;
485 }
486 
492 {
493  CPU->NVIC_IPR1.bit.PRI_N6 = u8_value;
494 }
495 
501 {
502  CPU->NVIC_IPR1.bit.PRI_N7 = u8_value;
503 }
504 
510 {
511  CPU->NVIC_IPR2.bit.PRI_N8 = u8_value;
512 }
513 
519 {
520  CPU->NVIC_IPR2.bit.PRI_N9 = u8_value;
521 }
522 
528 {
529  CPU->NVIC_IPR2.bit.PRI_N10 = u8_value;
530 }
531 
537 {
538  CPU->NVIC_IPR2.bit.PRI_N11 = u8_value;
539 }
540 
546 {
547  CPU->NVIC_IPR3.bit.PRI_N12 = u8_value;
548 }
549 
555 {
556  CPU->NVIC_IPR3.bit.PRI_N13 = u8_value;
557 }
558 
564 {
565  CPU->NVIC_IPR3.bit.PRI_N14 = u8_value;
566 }
567 
573 {
574  CPU->NVIC_IPR3.bit.PRI_N15 = u8_value;
575 }
576 
582 {
583  CPU->NVIC_IPR4.bit.PRI_N16 = u8_value;
584 }
585 
591 {
592  CPU->NVIC_IPR4.bit.PRI_N17 = u8_value;
593 }
594 
600 {
601  CPU->NVIC_IPR4.bit.PRI_N18 = u8_value;
602 }
603 
609 {
610  CPU->NVIC_IPR4.bit.PRI_N19 = u8_value;
611 }
612 
618 {
619  CPU->NVIC_IPR5.bit.PRI_N20 = u8_value;
620 }
621 
627 {
628  CPU->NVIC_IPR5.bit.PRI_N21 = u8_value;
629 }
630 
636 {
637  CPU->NVIC_IPR5.bit.PRI_N22 = u8_value;
638 }
639 
645 {
646  CPU->NVIC_IPR5.bit.PRI_N23 = u8_value;
647 }
648 
654 {
655  CPU->NVIC_IPR6.bit.PRI_N24 = u8_value;
656 }
657 
663 {
664  CPU->NVIC_IPR6.bit.PRI_N25 = u8_value;
665 }
666 
672 {
673  CPU->NVIC_IPR6.bit.PRI_N26 = u8_value;
674 }
675 
681 {
682  CPU->NVIC_IPR6.bit.PRI_N27 = u8_value;
683 }
684 
690 {
691  CPU->NVIC_IPR7.bit.PRI_N28 = u8_value;
692 }
693 
699 {
700  CPU->NVIC_IPR7.bit.PRI_N29 = u8_value;
701 }
702 
708 {
709  CPU->NVIC_IPR7.bit.PRI_N30 = u8_value;
710 }
711 
717 {
718  CPU->NVIC_IPR7.bit.PRI_N31 = u8_value;
719 }
720 
723 INLINE void NVIC_enIRQ0(void)
724 {
725  CPU->NVIC_ISER.bit.IRQEN0 = 1u;
726 }
727 
730 INLINE void NVIC_enIRQ1(void)
731 {
732  CPU->NVIC_ISER.bit.IRQEN1 = 1u;
733 }
734 
737 INLINE void NVIC_enIRQ2(void)
738 {
739  CPU->NVIC_ISER.bit.IRQEN2 = 1u;
740 }
741 
744 INLINE void NVIC_enIRQ3(void)
745 {
746  CPU->NVIC_ISER.bit.IRQEN3 = 1u;
747 }
748 
751 INLINE void NVIC_enIRQ4(void)
752 {
753  CPU->NVIC_ISER.bit.IRQEN4 = 1u;
754 }
755 
758 INLINE void NVIC_enIRQ5(void)
759 {
760  CPU->NVIC_ISER.bit.IRQEN5 = 1u;
761 }
762 
765 INLINE void NVIC_enIRQ6(void)
766 {
767  CPU->NVIC_ISER.bit.IRQEN6 = 1u;
768 }
769 
772 INLINE void NVIC_enIRQ7(void)
773 {
774  CPU->NVIC_ISER.bit.IRQEN7 = 1u;
775 }
776 
779 INLINE void NVIC_enIRQ8(void)
780 {
781  CPU->NVIC_ISER.bit.IRQEN8 = 1u;
782 }
783 
786 INLINE void NVIC_enIRQ9(void)
787 {
788  CPU->NVIC_ISER.bit.IRQEN9 = 1u;
789 }
790 
794 {
795  CPU->NVIC_ISER.bit.IRQEN10 = 1u;
796 }
797 
801 {
802  CPU->NVIC_ISER.bit.IRQEN11 = 1u;
803 }
804 
808 {
809  CPU->NVIC_ISER.bit.IRQEN12 = 1u;
810 }
811 
815 {
816  CPU->NVIC_ISER.bit.IRQEN13 = 1u;
817 }
818 
822 {
823  CPU->NVIC_ISER.bit.IRQEN14 = 1u;
824 }
825 
829 {
830  CPU->NVIC_ISER.bit.IRQEN15 = 1u;
831 }
832 
836 {
837  CPU->NVIC_ISER.bit.IRQEN16 = 1u;
838 }
839 
843 {
844  CPU->NVIC_ISER.bit.IRQEN17 = 1u;
845 }
846 
850 {
851  CPU->NVIC_ISER.bit.IRQEN18 = 1u;
852 }
853 
857 {
858  CPU->NVIC_ISER.bit.IRQEN19 = 1u;
859 }
860 
864 {
865  CPU->NVIC_ISER.bit.IRQEN20 = 1u;
866 }
867 
871 {
872  CPU->NVIC_ISER.bit.IRQEN21 = 1u;
873 }
874 
878 {
879  CPU->NVIC_ISER.bit.IRQEN22 = 1u;
880 }
881 
885 {
886  CPU->NVIC_ISER.bit.IRQEN23 = 1u;
887 }
888 
892 {
893  CPU->NVIC_ISER.bit.IRQEN24 = 1u;
894 }
895 
899 {
900  CPU->NVIC_ISER.bit.IRQEN25 = 1u;
901 }
902 
906 {
907  CPU->NVIC_ISER.bit.IRQEN26 = 1u;
908 }
909 
913 {
914  CPU->NVIC_ISER.bit.IRQEN27 = 1u;
915 }
916 
920 {
921  CPU->NVIC_ISER.bit.IRQEN28 = 1u;
922 }
923 
927 {
928  CPU->NVIC_ISER.bit.IRQEN29 = 1u;
929 }
930 
934 {
935  CPU->NVIC_ISER.bit.IRQEN30 = 1u;
936 }
937 
941 {
942  CPU->NVIC_ISER.bit.IRQEN31 = 1u;
943 }
944 
945 /*******************************************************************************
946 ** Global Function Declarations **
947 *******************************************************************************/
950 #endif /* _INT_H */
951 
#define CPU
Definition: tle989x.h:24067
INLINE void NVIC_disIRQ13(void)
Disable NVIC node 13.
Definition: int.h:302
INLINE void NVIC_enIRQ3(void)
Enable NVIC node 3.
Definition: int.h:744
INLINE void NVIC_enIRQ2(void)
Enable NVIC node 2.
Definition: int.h:737
INLINE void NVIC_enIRQ19(void)
Enable NVIC node 19.
Definition: int.h:856
INLINE void NVIC_disIRQ20(void)
Disable NVIC node 20.
Definition: int.h:351
INLINE void NVIC_disIRQ5(void)
Disable NVIC node 5.
Definition: int.h:246
INLINE void NVIC_disIRQ15(void)
Disable NVIC node 15.
Definition: int.h:316
INLINE void NVIC_enIRQ5(void)
Enable NVIC node 5.
Definition: int.h:758
INLINE void NVIC_setIRQ29Priority(uint8 u8_value)
Set NVIC node 29 interrupt priority.
Definition: int.h:698
INLINE void NVIC_disIRQ22(void)
Disable NVIC node 22.
Definition: int.h:365
INLINE void NVIC_disIRQ29(void)
Disable NVIC node 29.
Definition: int.h:414
INLINE void NVIC_disIRQ19(void)
Disable NVIC node 19.
Definition: int.h:344
INLINE void NVIC_enIRQ24(void)
Enable NVIC node 24.
Definition: int.h:891
INLINE void NVIC_enIRQ8(void)
Enable NVIC node 8.
Definition: int.h:779
INLINE void NVIC_enIRQ11(void)
Enable NVIC node 11.
Definition: int.h:800
INLINE void NVIC_setIRQ6Priority(uint8 u8_value)
Set NVIC node 6 interrupt priority.
Definition: int.h:491
INLINE void NVIC_enIRQ12(void)
Enable NVIC node 12.
Definition: int.h:807
INLINE void NVIC_enIRQ18(void)
Enable NVIC node 18.
Definition: int.h:849
INLINE void NVIC_disIRQ8(void)
Disable NVIC node 8.
Definition: int.h:267
INLINE void NVIC_enIRQ13(void)
Enable NVIC node 13.
Definition: int.h:814
INLINE void NVIC_enIRQ10(void)
Enable NVIC node 10.
Definition: int.h:793
INLINE void NVIC_setIRQ8Priority(uint8 u8_value)
Set NVIC node 8 interrupt priority.
Definition: int.h:509
INLINE void NVIC_disIRQ7(void)
Disable NVIC node 7.
Definition: int.h:260
INLINE void NVIC_setIRQ15Priority(uint8 u8_value)
Set NVIC node 15 interrupt priority.
Definition: int.h:572
INLINE void NVIC_setIRQ11Priority(uint8 u8_value)
Set NVIC node 11 interrupt priority.
Definition: int.h:536
INLINE void NVIC_enIRQ7(void)
Enable NVIC node 7.
Definition: int.h:772
INLINE void NVIC_enIRQ0(void)
Enable NVIC node 0.
Definition: int.h:723
INLINE void NVIC_enIRQ22(void)
Enable NVIC node 22.
Definition: int.h:877
INLINE void NVIC_disIRQ21(void)
Disable NVIC node 21.
Definition: int.h:358
INLINE void NVIC_disIRQ6(void)
Disable NVIC node 6.
Definition: int.h:253
INLINE void NVIC_enIRQ15(void)
Enable NVIC node 15.
Definition: int.h:828
INLINE void NVIC_setIRQ10Priority(uint8 u8_value)
Set NVIC node 10 interrupt priority.
Definition: int.h:527
INLINE void NVIC_disIRQ12(void)
Disable NVIC node 12.
Definition: int.h:295
INLINE void NVIC_disIRQ18(void)
Disable NVIC node 18.
Definition: int.h:337
INLINE void NVIC_setIRQ13Priority(uint8 u8_value)
Set NVIC node 13 interrupt priority.
Definition: int.h:554
INLINE void NVIC_enIRQ16(void)
Enable NVIC node 16.
Definition: int.h:835
INLINE void NVIC_disIRQ16(void)
Disable NVIC node 16.
Definition: int.h:323
INLINE void NVIC_setIRQ25Priority(uint8 u8_value)
Set NVIC node 25 interrupt priority.
Definition: int.h:662
INLINE void NVIC_setIRQ3Priority(uint8 u8_value)
Set NVIC node 3 interrupt priority.
Definition: int.h:464
INLINE void NVIC_enIRQ28(void)
Enable NVIC node 28.
Definition: int.h:919
INLINE void NVIC_enIRQ14(void)
Enable NVIC node 14.
Definition: int.h:821
INLINE void NVIC_disIRQ1(void)
Disable NVIC node 1.
Definition: int.h:218
INLINE void NVIC_setIRQ22Priority(uint8 u8_value)
Set NVIC node 22 interrupt priority.
Definition: int.h:635
INLINE void NVIC_disIRQ3(void)
Disable NVIC node 3.
Definition: int.h:232
INLINE void NVIC_enIRQ21(void)
Enable NVIC node 21.
Definition: int.h:870
INLINE void NVIC_setIRQ30Priority(uint8 u8_value)
Set NVIC node 30 interrupt priority.
Definition: int.h:707
INLINE void NVIC_setIRQ2Priority(uint8 u8_value)
Set NVIC node 2 interrupt priority.
Definition: int.h:455
INLINE void NVIC_setIRQ18Priority(uint8 u8_value)
Set NVIC node 18 interrupt priority.
Definition: int.h:599
INLINE void NVIC_setIRQ31Priority(uint8 u8_value)
Set NVIC node 31 interrupt priority.
Definition: int.h:716
INLINE void NVIC_disIRQ23(void)
Disable NVIC node 23.
Definition: int.h:372
INLINE void NVIC_disIRQ10(void)
Disable NVIC node 10.
Definition: int.h:281
INLINE void NVIC_disIRQ2(void)
Disable NVIC node 2.
Definition: int.h:225
INLINE void NVIC_disIRQ11(void)
Disable NVIC node 11.
Definition: int.h:288
INLINE void NVIC_setIRQ20Priority(uint8 u8_value)
Set NVIC node 20 interrupt priority.
Definition: int.h:617
INLINE void NVIC_setIRQ24Priority(uint8 u8_value)
Set NVIC node 24 interrupt priority.
Definition: int.h:653
INLINE void NVIC_enIRQ20(void)
Enable NVIC node 20.
Definition: int.h:863
INLINE void NVIC_enIRQ29(void)
Enable NVIC node 29.
Definition: int.h:926
INLINE void NVIC_setIRQ5Priority(uint8 u8_value)
Set NVIC node 5 interrupt priority.
Definition: int.h:482
void INT_init(void)
Initialize all interrupt-related registers.
Definition: int.c:58
INLINE void NVIC_disIRQ0(void)
Disable NVIC node 0.
Definition: int.h:211
INLINE void NVIC_enIRQ25(void)
Enable NVIC node 25.
Definition: int.h:898
INLINE void NVIC_disIRQ26(void)
Disable NVIC node 26.
Definition: int.h:393
INLINE void NVIC_setIRQ17Priority(uint8 u8_value)
Set NVIC node 17 interrupt priority.
Definition: int.h:590
INLINE void NVIC_enIRQ1(void)
Enable NVIC node 1.
Definition: int.h:730
INLINE void NVIC_enIRQ23(void)
Enable NVIC node 23.
Definition: int.h:884
INLINE void NVIC_disIRQ28(void)
Disable NVIC node 28.
Definition: int.h:407
INLINE void NVIC_setIRQ12Priority(uint8 u8_value)
Set NVIC node 12 interrupt priority.
Definition: int.h:545
INLINE void NVIC_setIRQ28Priority(uint8 u8_value)
Set NVIC node 28 interrupt priority.
Definition: int.h:689
INLINE void NVIC_setIRQ23Priority(uint8 u8_value)
Set NVIC node 23 interrupt priority.
Definition: int.h:644
INLINE void NVIC_setIRQ9Priority(uint8 u8_value)
Set NVIC node 9 interrupt priority.
Definition: int.h:518
INLINE void NVIC_setIRQ26Priority(uint8 u8_value)
Set NVIC node 26 interrupt priority.
Definition: int.h:671
INLINE void NVIC_enIRQ26(void)
Enable NVIC node 26.
Definition: int.h:905
INLINE void NVIC_setIRQ1Priority(uint8 u8_value)
Set NVIC node 1 interrupt priority.
Definition: int.h:446
INLINE void NVIC_disIRQ25(void)
Disable NVIC node 25.
Definition: int.h:386
INLINE void NVIC_setIRQ14Priority(uint8 u8_value)
Set NVIC node 14 interrupt priority.
Definition: int.h:563
INLINE void NVIC_disIRQ4(void)
Disable NVIC node 4.
Definition: int.h:239
INLINE void NVIC_enIRQ27(void)
Enable NVIC node 27.
Definition: int.h:912
INLINE void NVIC_enIRQ30(void)
Enable NVIC node 30.
Definition: int.h:933
INLINE void NVIC_disIRQ30(void)
Disable NVIC node 30.
Definition: int.h:421
INLINE void NVIC_setIRQ4Priority(uint8 u8_value)
Set NVIC node 4 interrupt priority.
Definition: int.h:473
INLINE void NVIC_setIRQ0Priority(uint8 u8_value)
Set NVIC node 0 interrupt priority.
Definition: int.h:437
INLINE void NVIC_enIRQ4(void)
Enable NVIC node 4.
Definition: int.h:751
INLINE void NVIC_setIRQ21Priority(uint8 u8_value)
Set NVIC node 21 interrupt priority.
Definition: int.h:626
INLINE void NVIC_enIRQ17(void)
Enable NVIC node 17.
Definition: int.h:842
INLINE void NVIC_disIRQ17(void)
Disable NVIC node 17.
Definition: int.h:330
INLINE void NVIC_disIRQ14(void)
Disable NVIC node 14.
Definition: int.h:309
INLINE void NVIC_disIRQ24(void)
Disable NVIC node 24.
Definition: int.h:379
INLINE void NVIC_enIRQ31(void)
Enable NVIC node 31.
Definition: int.h:940
INLINE void NVIC_setIRQ27Priority(uint8 u8_value)
Set NVIC node 27 interrupt priority.
Definition: int.h:680
INLINE void NVIC_disIRQ31(void)
Disable NVIC node 31.
Definition: int.h:428
INLINE void NVIC_setIRQ7Priority(uint8 u8_value)
Set NVIC node 7 interrupt priority.
Definition: int.h:500
INLINE void NVIC_setIRQ19Priority(uint8 u8_value)
Set NVIC node 19 interrupt priority.
Definition: int.h:608
INLINE void NVIC_enIRQ9(void)
Enable NVIC node 9.
Definition: int.h:786
INLINE void NVIC_setIRQ16Priority(uint8 u8_value)
Set NVIC node 16 interrupt priority.
Definition: int.h:581
INLINE void NVIC_disIRQ9(void)
Disable NVIC node 9.
Definition: int.h:274
INLINE void NVIC_disIRQ27(void)
Disable NVIC node 27.
Definition: int.h:400
INLINE void NVIC_enIRQ6(void)
Enable NVIC node 6.
Definition: int.h:765
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:167
uint8_t uint8
8 bit unsigned value
Definition: types.h:220