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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
|
CPU (CPU)
#include <tle989x.h>
Data Fields | |
__IM uint32_t | RESERVED |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t INTLINESNUM: 5 | |
uint32_t __pad0__: 27 | |
} bit | |
} | ICT |
__IM uint32_t | RESERVED1 [2] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ENABLE: 1 | |
__IOM uint32_t TICKINT: 1 | |
__IOM uint32_t CLKSOURCE: 1 | |
uint32_t __pad0__: 13 | |
__IM uint32_t COUNTFLAG: 1 | |
uint32_t __pad1__: 15 | |
} bit | |
} | SYSTICK_CS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RELOAD: 24 | |
uint32_t __pad0__: 8 | |
} bit | |
} | SYSTICK_RL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CURRENT: 24 | |
uint32_t __pad0__: 8 | |
} bit | |
} | SYSTICK_CUR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t TENMS: 24 | |
uint32_t __pad0__: 6 | |
__IM uint32_t SKEW: 1 | |
__IM uint32_t NOREF: 1 | |
} bit | |
} | SYSTICK_CAL |
__IM uint32_t | RESERVED2 [56] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IRQEN0: 1 | |
__IOM uint32_t IRQEN1: 1 | |
__IOM uint32_t IRQEN2: 1 | |
__IOM uint32_t IRQEN3: 1 | |
__IOM uint32_t IRQEN4: 1 | |
__IOM uint32_t IRQEN5: 1 | |
__IOM uint32_t IRQEN6: 1 | |
__IOM uint32_t IRQEN7: 1 | |
__IOM uint32_t IRQEN8: 1 | |
__IOM uint32_t IRQEN9: 1 | |
__IOM uint32_t IRQEN10: 1 | |
__IOM uint32_t IRQEN11: 1 | |
__IOM uint32_t IRQEN12: 1 | |
__IOM uint32_t IRQEN13: 1 | |
__IOM uint32_t IRQEN14: 1 | |
__IOM uint32_t IRQEN15: 1 | |
__IOM uint32_t IRQEN16: 1 | |
__IOM uint32_t IRQEN17: 1 | |
__IOM uint32_t IRQEN18: 1 | |
__IOM uint32_t IRQEN19: 1 | |
__IOM uint32_t IRQEN20: 1 | |
__IOM uint32_t IRQEN21: 1 | |
__IOM uint32_t IRQEN22: 1 | |
__IOM uint32_t IRQEN23: 1 | |
__IOM uint32_t IRQEN24: 1 | |
__IOM uint32_t IRQEN25: 1 | |
__IOM uint32_t IRQEN26: 1 | |
__IOM uint32_t IRQEN27: 1 | |
__IOM uint32_t IRQEN28: 1 | |
__IOM uint32_t IRQEN29: 1 | |
__IOM uint32_t IRQEN30: 1 | |
__IOM uint32_t IRQEN31: 1 | |
} bit | |
} | NVIC_ISER |
__IM uint32_t | RESERVED3 [31] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IRQCLREN0: 1 | |
__IOM uint32_t IRQCLREN1: 1 | |
__IOM uint32_t IRQCLREN2: 1 | |
__IOM uint32_t IRQCLREN3: 1 | |
__IOM uint32_t IRQCLREN4: 1 | |
__IOM uint32_t IRQCLREN5: 1 | |
__IOM uint32_t IRQCLREN6: 1 | |
__IOM uint32_t IRQCLREN7: 1 | |
__IOM uint32_t IRQCLREN8: 1 | |
__IOM uint32_t IRQCLREN9: 1 | |
__IOM uint32_t IRQCLREN10: 1 | |
__IOM uint32_t IRQCLREN11: 1 | |
__IOM uint32_t IRQCLREN12: 1 | |
__IOM uint32_t IRQCLREN13: 1 | |
__IOM uint32_t IRQCLREN14: 1 | |
__IOM uint32_t IRQCLREN15: 1 | |
__IOM uint32_t IRQCLREN16: 1 | |
__IOM uint32_t IRQCLREN17: 1 | |
__IOM uint32_t IRQCLREN18: 1 | |
__IOM uint32_t IRQCLREN19: 1 | |
__IOM uint32_t IRQCLREN20: 1 | |
__IOM uint32_t IRQCLREN21: 1 | |
__IOM uint32_t IRQCLREN22: 1 | |
__IOM uint32_t IRQCLREN23: 1 | |
__IOM uint32_t IRQCLREN24: 1 | |
__IOM uint32_t IRQCLREN25: 1 | |
__IOM uint32_t IRQCLREN26: 1 | |
__IOM uint32_t IRQCLREN27: 1 | |
__IOM uint32_t IRQCLREN28: 1 | |
__IOM uint32_t IRQCLREN29: 1 | |
__IOM uint32_t IRQCLREN30: 1 | |
__IOM uint32_t IRQCLREN31: 1 | |
} bit | |
} | NVIC_ICER |
__IM uint32_t | RESERVED4 [31] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IRQSETPEND0: 1 | |
__IOM uint32_t IRQSETPEND1: 1 | |
__IOM uint32_t IRQSETPEND2: 1 | |
__IOM uint32_t IRQSETPEND3: 1 | |
__IOM uint32_t IRQSETPEND4: 1 | |
__IOM uint32_t IRQSETPEND5: 1 | |
__IOM uint32_t IRQSETPEND6: 1 | |
__IOM uint32_t IRQSETPEND7: 1 | |
__IOM uint32_t IRQSETPEND8: 1 | |
__IOM uint32_t IRQSETPEND9: 1 | |
__IOM uint32_t IRQSETPEND10: 1 | |
__IOM uint32_t IRQSETPEND11: 1 | |
__IOM uint32_t IRQSETPEND12: 1 | |
__IOM uint32_t IRQSETPEND13: 1 | |
__IOM uint32_t IRQSETPEND14: 1 | |
__IOM uint32_t IRQSETPEND15: 1 | |
__IOM uint32_t IRQSETPEND16: 1 | |
__IOM uint32_t IRQSETPEND17: 1 | |
__IOM uint32_t IRQSETPEND18: 1 | |
__IOM uint32_t IRQSETPEND19: 1 | |
__IOM uint32_t IRQSETPEND20: 1 | |
__IOM uint32_t IRQSETPEND21: 1 | |
__IOM uint32_t IRQSETPEND22: 1 | |
__IOM uint32_t IRQSETPEND23: 1 | |
__IOM uint32_t IRQSETPEND24: 1 | |
__IOM uint32_t IRQSETPEND25: 1 | |
__IOM uint32_t IRQSETPEND26: 1 | |
__IOM uint32_t IRQSETPEND27: 1 | |
__IOM uint32_t IRQSETPEND28: 1 | |
__IOM uint32_t IRQSETPEND29: 1 | |
__IOM uint32_t IRQSETPEND30: 1 | |
__IOM uint32_t IRQSETPEND31: 1 | |
} bit | |
} | NVIC_ISPR |
__IM uint32_t | RESERVED5 [31] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IRQCLRPEND0: 1 | |
__IOM uint32_t IRQCLRPEND1: 1 | |
__IOM uint32_t IRQCLRPEND2: 1 | |
__IOM uint32_t IRQCLRPEND3: 1 | |
__IOM uint32_t IRQCLRPEND4: 1 | |
__IOM uint32_t IRQCLRPEND5: 1 | |
__IOM uint32_t IRQCLRPEND6: 1 | |
__IOM uint32_t IRQCLRPEND7: 1 | |
__IOM uint32_t IRQCLRPEND8: 1 | |
__IOM uint32_t IRQCLRPEND9: 1 | |
__IOM uint32_t IRQCLRPEND10: 1 | |
__IOM uint32_t IRQCLRPEND11: 1 | |
__IOM uint32_t IRQCLRPEND12: 1 | |
__IOM uint32_t IRQCLRPEND13: 1 | |
__IOM uint32_t IRQCLRPEND14: 1 | |
__IOM uint32_t IRQCLRPEND15: 1 | |
__IOM uint32_t IRQCLRPEND16: 1 | |
__IOM uint32_t IRQCLRPEND17: 1 | |
__IOM uint32_t IRQCLRPEND18: 1 | |
__IOM uint32_t IRQCLRPEND19: 1 | |
__IOM uint32_t IRQCLRPEND20: 1 | |
__IOM uint32_t IRQCLRPEND21: 1 | |
__IOM uint32_t IRQCLRPEND22: 1 | |
__IOM uint32_t IRQCLRPEND23: 1 | |
__IOM uint32_t IRQCLRPEND24: 1 | |
__IOM uint32_t IRQCLRPEND25: 1 | |
__IOM uint32_t IRQCLRPEND26: 1 | |
__IOM uint32_t IRQCLRPEND27: 1 | |
__IOM uint32_t IRQCLRPEND28: 1 | |
__IOM uint32_t IRQCLRPEND29: 1 | |
__IOM uint32_t IRQCLRPEND30: 1 | |
__IOM uint32_t IRQCLRPEND31: 1 | |
} bit | |
} | NVIC_ICPR |
__IM uint32_t | RESERVED6 [31] |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t IRQACTIVE0: 1 | |
__IM uint32_t IRQACTIVE1: 1 | |
__IM uint32_t IRQACTIVE2: 1 | |
__IM uint32_t IRQACTIVE3: 1 | |
__IM uint32_t IRQACTIVE4: 1 | |
__IM uint32_t IRQACTIVE5: 1 | |
__IM uint32_t IRQACTIVE6: 1 | |
__IM uint32_t IRQACTIVE7: 1 | |
__IM uint32_t IRQACTIVE8: 1 | |
__IM uint32_t IRQACTIVE9: 1 | |
__IM uint32_t IRQACTIVE10: 1 | |
__IM uint32_t IRQACTIVE11: 1 | |
__IM uint32_t IRQACTIVE12: 1 | |
__IM uint32_t IRQACTIVE13: 1 | |
__IM uint32_t IRQACTIVE14: 1 | |
__IM uint32_t IRQACTIVE15: 1 | |
__IM uint32_t IRQACTIVE16: 1 | |
__IM uint32_t IRQACTIVE17: 1 | |
__IM uint32_t IRQACTIVE18: 1 | |
__IM uint32_t IRQACTIVE19: 1 | |
__IM uint32_t IRQACTIVE20: 1 | |
__IM uint32_t IRQACTIVE21: 1 | |
__IM uint32_t IRQACTIVE22: 1 | |
__IM uint32_t IRQACTIVE23: 1 | |
__IM uint32_t IRQACTIVE24: 1 | |
__IM uint32_t IRQACTIVE25: 1 | |
__IM uint32_t IRQACTIVE26: 1 | |
__IM uint32_t IRQACTIVE27: 1 | |
__IM uint32_t IRQACTIVE28: 1 | |
__IM uint32_t IRQACTIVE29: 1 | |
__IM uint32_t IRQACTIVE30: 1 | |
__IM uint32_t IRQACTIVE31: 1 | |
} bit | |
} | NVIC_IABR |
__IM uint32_t | RESERVED7 [63] |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N0: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N1: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N2: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N3: 5 | |
} bit | |
} | NVIC_IPR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N4: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N5: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N6: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N7: 5 | |
} bit | |
} | NVIC_IPR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N8: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N9: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N10: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N11: 5 | |
} bit | |
} | NVIC_IPR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N12: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N13: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N14: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N15: 5 | |
} bit | |
} | NVIC_IPR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N16: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N17: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N18: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N19: 5 | |
} bit | |
} | NVIC_IPR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N20: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N21: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N22: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N23: 5 | |
} bit | |
} | NVIC_IPR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N24: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N25: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N26: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N27: 5 | |
} bit | |
} | NVIC_IPR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_N28: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_N29: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_N30: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_N31: 5 | |
} bit | |
} | NVIC_IPR7 |
__IM uint32_t | RESERVED8 [568] |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t REVISION: 4 | |
__IM uint32_t PARTNO: 12 | |
__IM uint32_t ARCHITECTURE: 4 | |
__IM uint32_t VARIANT: 4 | |
__IM uint32_t IMPLEMENTER: 8 | |
} bit | |
} | CPUID |
union { | |
__IOM uint32_t reg | |
struct { | |
__IM uint32_t VECTACTIVE: 9 | |
uint32_t __pad0__: 2 | |
__IM uint32_t RETTOBASE: 1 | |
__IM uint32_t VECTPending: 9 | |
uint32_t __pad1__: 1 | |
__IM uint32_t ISRPending: 1 | |
__IM uint32_t ISRPREEMPT: 1 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t PENDSTCLR: 1 | |
__IOM uint32_t PENDSTSET: 1 | |
__IOM uint32_t PENDSVCLR: 1 | |
__IOM uint32_t PENDSVSET: 1 | |
uint32_t __pad3__: 2 | |
__IOM uint32_t NMIPENDSET: 1 | |
} bit | |
} | ICSR |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 7 | |
__IOM uint32_t TBLOFF: 25 | |
} bit | |
} | VTOR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t VECTRESET: 1 | |
__IOM uint32_t VECTCLRACTIVE: 1 | |
__IOM uint32_t SYSRESETREQ: 1 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t PRIGROUP: 3 | |
uint32_t __pad1__: 4 | |
__IM uint32_t ENDIANNESS: 1 | |
__IOM uint32_t VECTKEY: 16 | |
} bit | |
} | AIRCR |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SLEEPONEXIT: 1 | |
__IOM uint32_t SLEEPDEEP: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t SEVONPEND: 1 | |
uint32_t __pad2__: 27 | |
} bit | |
} | SCR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t NONBASETHRDENA: 1 | |
__IOM uint32_t USERSETMPEND: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t UNALIGN_TRP: 1 | |
__IOM uint32_t DIV_0_TRP: 1 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t BFHFMIGN: 1 | |
__IOM uint32_t STKALIGN: 1 | |
uint32_t __pad2__: 22 | |
} bit | |
} | CCR |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_4: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_5: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_6: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_7: 5 | |
} bit | |
} | SHPR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_8: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_9: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_10: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_11: 5 | |
} bit | |
} | SHPR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t PRI_12: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t PRI_13: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t PRI_14: 5 | |
uint32_t __pad3__: 3 | |
__IOM uint32_t PRI_15: 5 | |
} bit | |
} | SHPR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MEMFAULTACT: 1 | |
__IOM uint32_t BUSFAULTACT: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t USGFAULTACT: 1 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t SVCALLACT: 1 | |
__IOM uint32_t MONITORACT: 1 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t PENDSVACT: 1 | |
__IOM uint32_t SYSTICKACT: 1 | |
__IOM uint32_t USGFAULTPENDED: 1 | |
__IOM uint32_t MEMFAULTPENDED: 1 | |
__IOM uint32_t BUSFAULTPENDED: 1 | |
__IOM uint32_t SVCALLPENDED: 1 | |
__IOM uint32_t MEMFAULTENA: 1 | |
__IOM uint32_t BUSFAULTENA: 1 | |
__IOM uint32_t USGFAULTENA: 1 | |
uint32_t __pad3__: 13 | |
} bit | |
} | SHCSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IACCVIOL: 1 | |
__IOM uint32_t DACCVIOL: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MUNSTKERR: 1 | |
__IOM uint32_t MSTERR: 1 | |
__IOM uint32_t MLSPERR: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t MMARVALID: 1 | |
__IOM uint32_t IBUSERR: 1 | |
__IOM uint32_t PRECISERR: 1 | |
__IOM uint32_t IMPRECISERR: 1 | |
__IOM uint32_t UNSTKERR: 1 | |
__IOM uint32_t STKERR: 1 | |
__IOM uint32_t LSPERR: 1 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t BFARVALID: 1 | |
__IOM uint32_t UNDEFINSTR: 1 | |
__IOM uint32_t INVSTATE: 1 | |
__IOM uint32_t INVPC: 1 | |
__IOM uint32_t NOCP: 1 | |
uint32_t __pad3__: 4 | |
__IOM uint32_t UNALIGNED: 1 | |
__IOM uint32_t DIVBYZERO: 1 | |
uint32_t __pad4__: 6 | |
} bit | |
} | CFSR |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__IOM uint32_t VECTTBL: 1 | |
uint32_t __pad1__: 28 | |
__IOM uint32_t FORCED: 1 | |
__IOM uint32_t DEBUGEVT: 1 | |
} bit | |
} | HFSR |
__IM uint32_t | RESERVED9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ADDRESS: 32 | |
} bit | |
} | MMFAR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ADDRESS: 32 | |
} bit | |
} | BFAR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t AUXFAULT: 32 | |
} bit | |
} | AFSR |
__IM uint32_t | RESERVED10 [44] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t C_DEBUGEN: 1 | |
__IOM uint32_t C_HALT: 1 | |
__IOM uint32_t C_STEP: 1 | |
__IOM uint32_t C_MASKINTS: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t C_SNAPSTALL: 1 | |
uint32_t __pad1__: 10 | |
__IM uint32_t S_REGRDY: 1 | |
__IM uint32_t S_HALT: 1 | |
__IM uint32_t S_SLEEP: 1 | |
__IM uint32_t S_LOCKUP: 1 | |
uint32_t __pad2__: 4 | |
__IM uint32_t S_RETIRE_ST: 1 | |
__IM uint32_t S_RESET_ST: 1 | |
uint32_t __pad3__: 6 | |
} bit | |
} | DHCSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t REGSEL: 7 | |
uint32_t __pad0__: 9 | |
__IOM uint32_t REGWnR: 1 | |
uint32_t __pad1__: 15 | |
} bit | |
} | DCRSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DBGTMP: 32 | |
} bit | |
} | DCRDR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t VC_CORERESET: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t VC_MMERR: 1 | |
__IOM uint32_t VC_NOCPERR: 1 | |
__IOM uint32_t VC_CHKERR: 1 | |
__IOM uint32_t VC_STATERR: 1 | |
__IOM uint32_t VC_BUSERR: 1 | |
__IOM uint32_t VC_INTERR: 1 | |
__IOM uint32_t VC_HARDERR: 1 | |
uint32_t __pad1__: 5 | |
__IOM uint32_t MON_EN: 1 | |
__IOM uint32_t MON_PEND: 1 | |
__IOM uint32_t MON_STEP: 1 | |
__IOM uint32_t MON_REQ: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t DWTENA: 1 | |
uint32_t __pad3__: 7 | |
} bit | |
} | DEMCR |
__IM uint32_t | RESERVED11 [64] |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t INTID: 9 | |
uint32_t __pad0__: 23 | |
} bit | |
} | STIR |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
uint32_t __pad4__ |
__IOM uint32_t ADDRESS |
[31..0] Address of the location that generated a MemManage fault
[31..0] Address of the location that generated a BusFault
union { ... } AFSR |
union { ... } AIRCR |
__IM uint32_t ARCHITECTURE |
[19..16] Architecture
__IM uint32_t AUXFAULT |
[31..0] Additional system fault information
union { ... } BFAR |
__IOM uint32_t BFARVALID |
[15..15] BusFault Address Register (BFAR) valid flag
__IOM uint32_t BFHFMIGN |
[8..8] Effect of precise data access faults on handlers running at a priority -1 or -2
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IOM uint32_t BUSFAULTACT |
[1..1] BusFault exception status
__IOM uint32_t BUSFAULTENA |
[17..17] BusFault enable
__IOM uint32_t BUSFAULTPENDED |
[14..14] BusFault exception pending status
__IOM uint32_t C_DEBUGEN |
[0..0] Debug enable
__IOM uint32_t C_HALT |
[1..1] Processor Halt
__IOM uint32_t C_MASKINTS |
[3..3] Mask external interrupts, SysTick and PendSV
__IOM uint32_t C_SNAPSTALL |
[5..5] Allow imprecise entry to Debug state
__IOM uint32_t C_STEP |
[2..2] Processor Step
union { ... } CCR |
union { ... } CFSR |
__IOM uint32_t CLKSOURCE |
[2..2] CLK SysTick timer clock source selection
__IM uint32_t COUNTFLAG |
[16..16] Count Flag
union { ... } CPUID |
__IOM uint32_t CURRENT |
[23..0] Current value of SysTick
__IOM uint32_t DACCVIOL |
[1..1] Data access violation flag
__IOM uint32_t DBGTMP |
[31..0] Data written to the register selected by DCRSR
union { ... } DCRDR |
union { ... } DCRSR |
__IOM uint32_t DEBUGEVT |
[31..31] Debug Event
union { ... } DEMCR |
union { ... } DHCSR |
__IOM uint32_t DIV_0_TRP |
[4..4] Trap divide by zero enable
__IOM uint32_t DIVBYZERO |
[25..25] Divide by zero UsageFault
__IOM uint32_t DWTENA |
[24..24] Global enable for the DW unit
__IOM uint32_t ENABLE |
[0..0] SysTick counter enable
__IM uint32_t ENDIANNESS |
[15..15] Data endianness
__IOM uint32_t FORCED |
[30..30] Forced HardFault flag
union { ... } HFSR |
__IOM uint32_t IACCVIOL |
[0..0] Instruction access violation flag
__IOM uint32_t IBUSERR |
[8..8] Instruction bus error
union { ... } ICSR |
union { ... } ICT |
__IM uint32_t IMPLEMENTER |
[31..24] Implementer Code
__IOM uint32_t IMPRECISERR |
[10..10] Imprecise data bus error
__OM uint32_t INTID |
[8..0] Interrupt ID to be triggered. The value written is (ExceptionNumber
__IM uint32_t INTLINESNUM |
[4..0] Total number of interrupt lines
__IOM uint32_t INVPC |
[18..18] Invalid PC load UsageFault
__IOM uint32_t INVSTATE |
[17..17] Invalid state UsageFault
__IM uint32_t IRQACTIVE0 |
[0..0] IRQx interrupt active flag
__IM uint32_t IRQACTIVE1 |
[1..1] IRQx interrupt active flag
__IM uint32_t IRQACTIVE10 |
[10..10] IRQx interrupt active flag
__IM uint32_t IRQACTIVE11 |
[11..11] IRQx interrupt active flag
__IM uint32_t IRQACTIVE12 |
[12..12] IRQx interrupt active flag
__IM uint32_t IRQACTIVE13 |
[13..13] IRQx interrupt active flag
__IM uint32_t IRQACTIVE14 |
[14..14] IRQx interrupt active flag
__IM uint32_t IRQACTIVE15 |
[15..15] IRQx interrupt active flag
__IM uint32_t IRQACTIVE16 |
[16..16] IRQx interrupt active flag
__IM uint32_t IRQACTIVE17 |
[17..17] IRQx interrupt active flag
__IM uint32_t IRQACTIVE18 |
[18..18] IRQx interrupt active flag
__IM uint32_t IRQACTIVE19 |
[19..19] IRQx interrupt active flag
__IM uint32_t IRQACTIVE2 |
[2..2] IRQx interrupt active flag
__IM uint32_t IRQACTIVE20 |
[20..20] IRQx interrupt active flag
__IM uint32_t IRQACTIVE21 |
[21..21] IRQx interrupt active flag
__IM uint32_t IRQACTIVE22 |
[22..22] IRQx interrupt active flag
__IM uint32_t IRQACTIVE23 |
[23..23] IRQx interrupt active flag
__IM uint32_t IRQACTIVE24 |
[24..24] IRQx interrupt active flag
__IM uint32_t IRQACTIVE25 |
[25..25] IRQx interrupt active flag
__IM uint32_t IRQACTIVE26 |
[26..26] IRQx interrupt active flag
__IM uint32_t IRQACTIVE27 |
[27..27] IRQx interrupt active flag
__IM uint32_t IRQACTIVE28 |
[28..28] IRQx interrupt active flag
__IM uint32_t IRQACTIVE29 |
[29..29] IRQx interrupt active flag
__IM uint32_t IRQACTIVE3 |
[3..3] IRQx interrupt active flag
__IM uint32_t IRQACTIVE30 |
[30..30] IRQx interrupt active flag
__IM uint32_t IRQACTIVE31 |
[31..31] IRQx interrupt active flag
__IM uint32_t IRQACTIVE4 |
[4..4] IRQx interrupt active flag
__IM uint32_t IRQACTIVE5 |
[5..5] IRQx interrupt active flag
__IM uint32_t IRQACTIVE6 |
[6..6] IRQx interrupt active flag
__IM uint32_t IRQACTIVE7 |
[7..7] IRQx interrupt active flag
__IM uint32_t IRQACTIVE8 |
[8..8] IRQx interrupt active flag
__IM uint32_t IRQACTIVE9 |
[9..9] IRQx interrupt active flag
__IOM uint32_t IRQCLREN0 |
[0..0] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN1 |
[1..1] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN10 |
[10..10] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN11 |
[11..11] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN12 |
[12..12] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN13 |
[13..13] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN14 |
[14..14] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN15 |
[15..15] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN16 |
[16..16] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN17 |
[17..17] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN18 |
[18..18] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN19 |
[19..19] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN2 |
[2..2] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN20 |
[20..20] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN21 |
[21..21] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN22 |
[22..22] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN23 |
[23..23] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN24 |
[24..24] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN25 |
[25..25] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN26 |
[26..26] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN27 |
[27..27] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN28 |
[28..28] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN29 |
[29..29] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN3 |
[3..3] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN30 |
[30..30] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN31 |
[31..31] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN4 |
[4..4] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN5 |
[5..5] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN6 |
[6..6] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN7 |
[7..7] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN8 |
[8..8] IRQx interrupt clear enable
__IOM uint32_t IRQCLREN9 |
[9..9] IRQx interrupt clear enable
__IOM uint32_t IRQCLRPEND0 |
[0..0] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND1 |
[1..1] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND10 |
[10..10] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND11 |
[11..11] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND12 |
[12..12] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND13 |
[13..13] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND14 |
[14..14] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND15 |
[15..15] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND16 |
[16..16] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND17 |
[17..17] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND18 |
[18..18] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND19 |
[19..19] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND2 |
[2..2] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND20 |
[20..20] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND21 |
[21..21] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND22 |
[22..22] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND23 |
[23..23] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND24 |
[24..24] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND25 |
[25..25] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND26 |
[26..26] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND27 |
[27..27] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND28 |
[28..28] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND29 |
[29..29] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND3 |
[3..3] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND30 |
[30..30] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND31 |
[31..31] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND4 |
[4..4] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND5 |
[5..5] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND6 |
[6..6] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND7 |
[7..7] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND8 |
[8..8] IRQx interrupt clear pending
__IOM uint32_t IRQCLRPEND9 |
[9..9] IRQx interrupt clear pending
__IOM uint32_t IRQEN0 |
[0..0] IRQx interrupt set enable
__IOM uint32_t IRQEN1 |
[1..1] IRQx interrupt set enable
__IOM uint32_t IRQEN10 |
[10..10] IRQx interrupt set enable
__IOM uint32_t IRQEN11 |
[11..11] IRQx interrupt set enable
__IOM uint32_t IRQEN12 |
[12..12] IRQx interrupt set enable
__IOM uint32_t IRQEN13 |
[13..13] IRQx interrupt set enable
__IOM uint32_t IRQEN14 |
[14..14] IRQx interrupt set enable
__IOM uint32_t IRQEN15 |
[15..15] IRQx interrupt set enable
__IOM uint32_t IRQEN16 |
[16..16] IRQx interrupt set enable
__IOM uint32_t IRQEN17 |
[17..17] IRQx interrupt set enable
__IOM uint32_t IRQEN18 |
[18..18] IRQx interrupt set enable
__IOM uint32_t IRQEN19 |
[19..19] IRQx interrupt set enable
__IOM uint32_t IRQEN2 |
[2..2] IRQx interrupt set enable
__IOM uint32_t IRQEN20 |
[20..20] IRQx interrupt set enable
__IOM uint32_t IRQEN21 |
[21..21] IRQx interrupt set enable
__IOM uint32_t IRQEN22 |
[22..22] IRQx interrupt set enable
__IOM uint32_t IRQEN23 |
[23..23] IRQx interrupt set enable
__IOM uint32_t IRQEN24 |
[24..24] IRQx interrupt set enable
__IOM uint32_t IRQEN25 |
[25..25] IRQx interrupt set enable
__IOM uint32_t IRQEN26 |
[26..26] IRQx interrupt set enable
__IOM uint32_t IRQEN27 |
[27..27] IRQx interrupt set enable
__IOM uint32_t IRQEN28 |
[28..28] IRQx interrupt set enable
__IOM uint32_t IRQEN29 |
[29..29] IRQx interrupt set enable
__IOM uint32_t IRQEN3 |
[3..3] IRQx interrupt set enable
__IOM uint32_t IRQEN30 |
[30..30] IRQx interrupt set enable
__IOM uint32_t IRQEN31 |
[31..31] IRQx interrupt set enable
__IOM uint32_t IRQEN4 |
[4..4] IRQx interrupt set enable
__IOM uint32_t IRQEN5 |
[5..5] IRQx interrupt set enable
__IOM uint32_t IRQEN6 |
[6..6] IRQx interrupt set enable
__IOM uint32_t IRQEN7 |
[7..7] IRQx interrupt set enable
__IOM uint32_t IRQEN8 |
[8..8] IRQx interrupt set enable
__IOM uint32_t IRQEN9 |
[9..9] IRQx interrupt set enable
__IOM uint32_t IRQSETPEND0 |
[0..0] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND1 |
[1..1] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND10 |
[10..10] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND11 |
[11..11] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND12 |
[12..12] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND13 |
[13..13] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND14 |
[14..14] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND15 |
[15..15] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND16 |
[16..16] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND17 |
[17..17] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND18 |
[18..18] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND19 |
[19..19] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND2 |
[2..2] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND20 |
[20..20] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND21 |
[21..21] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND22 |
[22..22] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND23 |
[23..23] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND24 |
[24..24] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND25 |
[25..25] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND26 |
[26..26] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND27 |
[27..27] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND28 |
[28..28] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND29 |
[29..29] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND3 |
[3..3] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND30 |
[30..30] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND31 |
[31..31] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND4 |
[4..4] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND5 |
[5..5] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND6 |
[6..6] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND7 |
[7..7] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND8 |
[8..8] IRQx interrupt set pending
__IOM uint32_t IRQSETPEND9 |
[9..9] IRQx interrupt set pending
__IM uint32_t ISRPending |
[22..22] External interrupt generated by the NVIC pending flag
__IM uint32_t ISRPREEMPT |
[23..23] Service of a pending exception on exit from debug halt state
__IOM uint32_t LSPERR |
[13..13] BusFault during FP lazy state preservation
__IOM uint32_t MEMFAULTACT |
[0..0] MemManage exception status
__IOM uint32_t MEMFAULTENA |
[16..16] MemManage enable
__IOM uint32_t MEMFAULTPENDED |
[13..13] MemManage exception pending status
__IOM uint32_t MLSPERR |
[5..5] MemManage fault during FP lazy state preservation
__IOM uint32_t MMARVALID |
[7..7] MemManage Fault Address Register (MMFAR) valid flag
union { ... } MMFAR |
__IOM uint32_t MON_EN |
[16..16] Debug Monitor Exception Enable
__IOM uint32_t MON_PEND |
[17..17] Debug Monitor Pending Exception Set/Clear
__IOM uint32_t MON_REQ |
[19..19] Debug Monitor Semaphore Bit
__IOM uint32_t MON_STEP |
[18..18] Step Request
__IOM uint32_t MONITORACT |
[8..8] Debug monitor status
__IOM uint32_t MSTERR |
[4..4] MemManage fault on stacking for exception entry
__IOM uint32_t MUNSTKERR |
[3..3] MemManage fault on unstacking for a return from exception
__IOM uint32_t NMIPENDSET |
[31..31] NMI set pending
__IOM uint32_t NOCP |
[19..19] No coprocessor UsageFault
__IOM uint32_t NONBASETHRDENA |
[0..0] Control of the processor entry point into the Thread mode
__IM uint32_t NOREF |
[31..31] Presence of a reference clock
union { ... } NVIC_IABR |
union { ... } NVIC_ICER |
union { ... } NVIC_ICPR |
union { ... } NVIC_IPR0 |
union { ... } NVIC_IPR1 |
union { ... } NVIC_IPR2 |
union { ... } NVIC_IPR3 |
union { ... } NVIC_IPR4 |
union { ... } NVIC_IPR5 |
union { ... } NVIC_IPR6 |
union { ... } NVIC_IPR7 |
union { ... } NVIC_ISER |
union { ... } NVIC_ISPR |
__IM uint32_t PARTNO |
[15..4] Part Number
__IOM uint32_t PENDSTCLR |
[25..25] SysTick exception clear pending
__IOM uint32_t PENDSTSET |
[26..26] SysTick exception set pending
__IOM uint32_t PENDSVACT |
[10..10] PendSV exception status
__IOM uint32_t PENDSVCLR |
[27..27] PendSV clear pending
__IOM uint32_t PENDSVSET |
[28..28] PendSV set pending
__IOM uint32_t PRECISERR |
[9..9] Precise data bus error
__IOM uint32_t PRI_10 |
[23..19] Reserved for Priority of System Handler 10
__IOM uint32_t PRI_11 |
[31..27] Priority of System Handler 11, SVCall
__IOM uint32_t PRI_12 |
[7..3] Priority of System Handler 12, DebugMonitor
__IOM uint32_t PRI_13 |
[15..11] Reserved for Priority of System Handler 13
__IOM uint32_t PRI_14 |
[23..19] Priority of System Handler 14, PendSV
__IOM uint32_t PRI_15 |
[31..27] Priority of System Handler 15, SysTick
__IOM uint32_t PRI_4 |
[7..3] Priority of System Handler 4, MemManage
__IOM uint32_t PRI_5 |
[15..11] Priority of System Handler 5, BusFault
__IOM uint32_t PRI_6 |
[23..19] Priority of System Handler 6, UsageFault
__IOM uint32_t PRI_7 |
[31..27] Reserved for Priority of System Handler 7
__IOM uint32_t PRI_8 |
[7..3] Reserved for Priority of System Handler 8
__IOM uint32_t PRI_9 |
[15..11] Reserved for Priority of System Handler 9
__IOM uint32_t PRI_N0 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N1 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRI_N10 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N11 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N12 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N13 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRI_N14 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N15 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N16 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N17 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRI_N18 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N19 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N2 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N20 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N21 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRI_N22 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N23 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N24 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N25 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRI_N26 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N27 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N28 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N29 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRI_N3 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N30 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N31 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N4 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N5 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRI_N6 |
[23..19] IRQx interrupt priority
__IOM uint32_t PRI_N7 |
[31..27] IRQx interrupt priority
__IOM uint32_t PRI_N8 |
[7..3] IRQx interrupt priority
__IOM uint32_t PRI_N9 |
[15..11] IRQx interrupt priority
__IOM uint32_t PRIGROUP |
[10..8] Priority Grouping
__IM uint32_t reg |
(@ 0x00000004) Interrupt Controller Type
(@ 0x0000001C) SysTick Calibration Value
(@ 0x00000300) Active Bit Register
(@ 0x00000D00) CPU ID Base Register
(@ 0x00000D3C) Auxiliary Fault Status Register
__IOM uint32_t reg |
(@ 0x00000010) SysTick Control and Status
(@ 0x00000014) SysTick Reload Value
(@ 0x00000018) SysTick Current Value
(@ 0x00000100) Interrupt Set-Enable
(@ 0x00000180) Interrupt Clear-Enable
(@ 0x00000200) Interrupt Set-Pending
(@ 0x00000280) Interrupt Clear-Pending
(@ 0x00000400) Interrupt Priority
(@ 0x00000404) Interrupt Priority
(@ 0x00000408) Interrupt Priority
(@ 0x0000040C) Interrupt Priority
(@ 0x00000410) Interrupt Priority
(@ 0x00000414) Interrupt Priority
(@ 0x00000418) Interrupt Priority
(@ 0x0000041C) Interrupt Priority
(@ 0x00000D04) Interrupt Control State Register
(@ 0x00000D08) Vector Table Offset Register
(@ 0x00000D0C) Application Interrupt/Reset Control Register
(@ 0x00000D10) System Control Register
(@ 0x00000D14) Configuration Control Register
(@ 0x00000D18) System Handler Priority Register 1
(@ 0x00000D1C) System Handler Priority Register 2
(@ 0x00000D20) System Handler Priority Register 3
(@ 0x00000D24) System Handler Control and State Register
(@ 0x00000D28) Configurable Fault Status Register
(@ 0x00000D2C) Hard Fault Status Register
(@ 0x00000D34) MemManage Fault Address Register
(@ 0x00000D38) Bus Fault Address Register
(@ 0x00000DF0) Debug Halting Control and Status Register
(@ 0x00000DF4) Debug Core Register Selector Register
(@ 0x00000DF8) Debug Core Register Data Register
(@ 0x00000DFC) Debug Exception and Monitor Control Register
(@ 0x00000F00) Software Triggered Interrupt
__IOM uint32_t REGSEL |
[6..0] Selection of the ARM core register or special-purpose register to transfer
__IOM uint32_t REGWnR |
[16..16] Access type for the transfer
__IOM uint32_t RELOAD |
[23..0] Reload value for SysTick
__IM uint32_t RESERVED |
__IM uint32_t RESERVED1[2] |
__IM uint32_t RESERVED10[44] |
__IM uint32_t RESERVED11[64] |
__IM uint32_t RESERVED2[56] |
__IM uint32_t RESERVED3[31] |
__IM uint32_t RESERVED4[31] |
__IM uint32_t RESERVED5[31] |
__IM uint32_t RESERVED6[31] |
__IM uint32_t RESERVED7[63] |
__IM uint32_t RESERVED8[568] |
__IM uint32_t RESERVED9 |
__IM uint32_t RETTOBASE |
[11..11] Presence of preempted active exceptions
__IM uint32_t REVISION |
[3..0] Revision Number
__IM uint32_t S_HALT |
[17..17] Processor halt in debug state
__IM uint32_t S_LOCKUP |
[19..19] Processor lockup state
__IM uint32_t S_REGRDY |
[16..16] Handshake flag for transfers through the DCRDR
__IM uint32_t S_RESET_ST |
[25..25] Processor reset flag since last read
__IM uint32_t S_RETIRE_ST |
[24..24] Complete instruction flag since last read
__IM uint32_t S_SLEEP |
[18..18] Processor sleep state
union { ... } SCR |
__IOM uint32_t SEVONPEND |
[4..4] Send event on pending
union { ... } SHCSR |
union { ... } SHPR1 |
union { ... } SHPR2 |
union { ... } SHPR3 |
__IM uint32_t SKEW |
[30..30] Skew
__IOM uint32_t SLEEPDEEP |
[2..2] Selection of sleep mode or deep sleep mode as low power mode
__IOM uint32_t SLEEPONEXIT |
[1..1] Sleep on exit when returning from Handler mode to Thread mode
union { ... } STIR |
__IOM uint32_t STKALIGN |
[9..9] Stack frame alignment on exception entry
__IOM uint32_t STKERR |
[12..12] BusFault on stacking for exception entry
__IOM uint32_t SVCALLACT |
[7..7] SVCall status
__IOM uint32_t SVCALLPENDED |
[15..15] SVCall exception pending status
__IOM uint32_t SYSRESETREQ |
[2..2] System Reset Request
union { ... } SYSTICK_CAL |
union { ... } SYSTICK_CS |
union { ... } SYSTICK_CUR |
union { ... } SYSTICK_RL |
__IOM uint32_t SYSTICKACT |
[11..11] SysTick exception status
__IOM uint32_t TBLOFF |
[31..7] Vector Table Offset
__IM uint32_t TENMS |
[23..0] Reload value used for 10 ms timing
__IOM uint32_t TICKINT |
[1..1] TICKINT
__IOM uint32_t UNALIGN_TRP |
[3..3] Unaligned access traps enable
__IOM uint32_t UNALIGNED |
[24..24] Unaligned access UsageFault
__IOM uint32_t UNDEFINSTR |
[16..16] Undefined instruction UsageFault
__IOM uint32_t UNSTKERR |
[11..11] BusFault on unstacking for a return from exception
__IOM uint32_t USERSETMPEND |
[1..1] Unprivileged software access to the STIR enable
__IOM uint32_t USGFAULTACT |
[3..3] UsageFault exception status
__IOM uint32_t USGFAULTENA |
[18..18] UsageFault enable
__IOM uint32_t USGFAULTPENDED |
[12..12] UsageFault exception pending status
__IM uint32_t VARIANT |
[23..20] Variant Number
__IOM uint32_t VC_BUSERR |
[8..8] Halting debug trap enable on a BusFault exception
__IOM uint32_t VC_CHKERR |
[6..6] Halting debug trap enable on a UsageFault caused by a checking error
__IOM uint32_t VC_CORERESET |
[0..0] Reset vector catch enable
__IOM uint32_t VC_HARDERR |
[10..10] Halting debug trap enable on a HardFault exception
__IOM uint32_t VC_INTERR |
[9..9] Halting debug trap enable on a fault during an exception entry or return
__IOM uint32_t VC_MMERR |
[4..4] Halting debug trap enable on a MemManage exception
__IOM uint32_t VC_NOCPERR |
[5..5] Halting debug trap enable on a UsageFault caused by an access to the coprocessor
__IOM uint32_t VC_STATERR |
[7..7] Halting debug trap enable on a UsageFault caused by a state information error
__IM uint32_t VECTACTIVE |
[8..0] Active exception number
__IOM uint32_t VECTCLRACTIVE |
[1..1] Active status information clear for fixed and configurable exception
__IOM uint32_t VECTKEY |
[31..16] Vector Key
__IM uint32_t VECTPending |
[20..12] Exception number with the highest priority pending enabled exception
__IOM uint32_t VECTRESET |
[0..0] Local system reset
__IOM uint32_t VECTTBL |
[1..1] BusFault flag on a vector table read during exception processing
union { ... } VTOR |