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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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PLL (PLL)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t NDIV: 8 | |
__IOM uint32_t PDIV: 6 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t K2DIV: 3 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t INSEL: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t FREERUN: 1 | |
__OM uint32_t RESLD: 1 | |
uint32_t __pad3__: 5 | |
__IOM uint32_t PLLEN: 1 | |
} bit | |
} | CON0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t NDIV: 8 | |
__IOM uint32_t PDIV: 6 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t K2DIV: 3 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t INSEL: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t FREERUN: 1 | |
__OM uint32_t RESLD: 1 | |
uint32_t __pad3__: 5 | |
__IOM uint32_t PLLEN: 1 | |
} bit | |
} | CON1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SPEN0: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t SPRANGE0: 2 | |
__IOM uint32_t SPUPVAL0: 10 | |
__IOM uint32_t SPEN1: 1 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t SPRANGE1: 2 | |
__IOM uint32_t SPUPVAL1: 10 | |
} bit | |
} | SPCTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t LCK0: 1 | |
__IM uint32_t LCK1: 1 | |
uint32_t __pad0__: 2 | |
__IM uint32_t PLL0_LOL_STS: 1 | |
__IM uint32_t PLL1_LOL_STS: 1 | |
uint32_t __pad1__: 10 | |
__IM uint32_t OSCSEL_STAT0: 1 | |
__IM uint32_t OSCSEL_STAT1: 1 | |
uint32_t __pad2__: 14 | |
} bit | |
} | STAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t PLL0_LOL_STSCLR: 1 | |
__OM uint32_t PLL1_LOL_STSCLR: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | STATC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t PLL0_LOL_STSSET: 1 | |
__OM uint32_t PLL1_LOL_STSSET: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | STATS |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
union { ... } CON0 |
union { ... } CON1 |
__IOM uint32_t FREERUN |
[24..24] Free-running Mode Select
[24..24] Freerunning Mode Select
__IOM uint32_t INSEL |
[21..20] PLL Reference Clock Select
__IOM uint32_t K2DIV |
[18..16] K2-Divider Setting
__IM uint32_t LCK0 |
[0..0] Lock Status PLL 0
__IM uint32_t LCK1 |
[1..1] Lock Status PLL1
__IOM uint32_t NDIV |
[7..0] N-Divider Setting
__IM uint32_t OSCSEL_STAT0 |
[16..16] Oscillator Select Status PLL0
__IM uint32_t OSCSEL_STAT1 |
[17..17] Oscillator Select Status PLL1
__IOM uint32_t PDIV |
[13..8] P-Divider Setting
__IM uint32_t PLL0_LOL_STS |
[4..4] PLL0 Loss Of Lock Status
__OM uint32_t PLL0_LOL_STSCLR |
[0..0] PLL0 Loss Of Lock Status Clear
__OM uint32_t PLL0_LOL_STSSET |
[0..0] PLL0 Loss Of Lock Status Set
__IM uint32_t PLL1_LOL_STS |
[5..5] PLL1 Loss Of Lock Status
__OM uint32_t PLL1_LOL_STSCLR |
[1..1] PLL1 Loss Of Lock Status Clear
__OM uint32_t PLL1_LOL_STSSET |
[1..1] PLL1 Loss Of Lock Status Set
__IOM uint32_t PLLEN |
[31..31] PLL Enable
__IOM uint32_t reg |
(@ 0x00000000) PLL0 Control Register
(@ 0x00000004) PLL1 Control Register
(@ 0x00000008) PLL NDIV Spread Control Register
(@ 0x00000010) PLL Status Clear Register
(@ 0x00000014) PLL Status Set Register
__IM uint32_t reg |
(@ 0x0000000C) PLL Status Register
__OM uint32_t RESLD |
[25..25] Lock Detection Reset
union { ... } SPCTR |
__IOM uint32_t SPEN0 |
[0..0] NDIV PLL0 Spread Enable
__IOM uint32_t SPEN1 |
[16..16] NDIV PLL1 Spread Enable
__IOM uint32_t SPRANGE0 |
[5..4] PLL0 NDIV Spread Range Value
__IOM uint32_t SPRANGE1 |
[21..20] PLL1 NDIV Spread Range Value
__IOM uint32_t SPUPVAL0 |
[15..6] PLL0 NDIV Spread Update Interval
__IOM uint32_t SPUPVAL1 |
[31..22] PLL1 NDIV Spread Update Interval
union { ... } STAT |
union { ... } STATC |
union { ... } STATS |