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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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UART0 (UART0)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXDSEL: 2 | |
__IOM uint32_t TXEVSEL: 2 | |
uint32_t __pad0__: 28 | |
} bit | |
} | INSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SM0: 1 | |
__IOM uint32_t SM1: 1 | |
__IOM uint32_t SM2: 1 | |
__IOM uint32_t REN: 1 | |
__IOM uint32_t RMOD: 1 | |
__IOM uint32_t TXINV: 1 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t TXENSEL: 2 | |
uint32_t __pad1__: 22 | |
} bit | |
} | SCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t TXSTART: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | TSTART |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TXDATA: 8 | |
__IOM uint32_t TB8: 1 | |
uint32_t __pad0__: 23 | |
} bit | |
} | TXBUF |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXDATA: 8 | |
__IM uint32_t RB8: 1 | |
uint32_t __pad0__: 23 | |
} bit | |
} | RXBUF |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TIEN: 1 | |
__IOM uint32_t RIEN: 1 | |
uint32_t __pad0__: 6 | |
__IOM uint32_t ERRSYNEN: 1 | |
__IOM uint32_t EOFSYNEN: 1 | |
uint32_t __pad1__: 22 | |
} bit | |
} | IEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t TI: 1 | |
__IM uint32_t RI: 1 | |
uint32_t __pad0__: 6 | |
__IM uint32_t ERRSYN: 1 | |
__IM uint32_t EOFSYN: 1 | |
uint32_t __pad1__: 22 | |
} bit | |
} | IS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t TISET: 1 | |
__OM uint32_t RISET: 1 | |
uint32_t __pad0__: 6 | |
__OM uint32_t ERRSYNSET: 1 | |
__OM uint32_t EOFSYNSET: 1 | |
uint32_t __pad1__: 22 | |
} bit | |
} | ISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t TICLR: 1 | |
__OM uint32_t RICLR: 1 | |
uint32_t __pad0__: 6 | |
__OM uint32_t ERRSYNCLR: 1 | |
__OM uint32_t EOFSYNCLR: 1 | |
uint32_t __pad1__: 22 | |
} bit | |
} | ISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BR_R: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t BR_PRE: 3 | |
uint32_t __pad1__: 9 | |
__IOM uint32_t BG_FD_SEL: 5 | |
__IOM uint32_t BG_BR_VALUE: 11 | |
} bit | |
} | BCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BREN: 1 | |
__IOM uint32_t BGSEL: 2 | |
uint32_t __pad0__: 29 | |
} bit | |
} | LINCON |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BRK: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | LINST |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t BRKCLR: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | LINSTC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t BRKSET: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | LINSTS |
uint32_t __pad0__ |
uint32_t __pad1__ |
union { ... } BCON |
__IOM uint32_t BG_BR_VALUE |
[31..21] Baud Rate Reload Value
__IOM uint32_t BG_FD_SEL |
[20..16] Fractional Divider Selection
__IOM uint32_t BGSEL |
[2..1] Baud Rate Select for Detection
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IOM uint32_t BR_PRE |
[6..4] Prescaler Bit
__IOM uint32_t BR_R |
[0..0] Baud Rate Generator Enable Bit
__IOM uint32_t BREN |
[0..0] Baud Rate Detection Enable
__IM uint32_t BRK |
[0..0] Break Field Detection Flag
__OM uint32_t BRKCLR |
[0..0] Break Field Flag Clear
__OM uint32_t BRKSET |
[0..0] Break Field Flag Set
__IM uint32_t EOFSYN |
[9..9] End of SYN Byte Interrupt Flag
__OM uint32_t EOFSYNCLR |
[9..9] End of SYN Byte Interrupt Clear
__IOM uint32_t EOFSYNEN |
[9..9] End of SYN Byte Interrupt Enable
__OM uint32_t EOFSYNSET |
[9..9] End of SYN Byte Interrupt Set
__IM uint32_t ERRSYN |
[8..8] SYN Error Interrupt Flag
__OM uint32_t ERRSYNCLR |
[8..8] SYN Error Interrupt Clear
__IOM uint32_t ERRSYNEN |
[8..8] SYN Error Interrupt Enable
__OM uint32_t ERRSYNSET |
[8..8] SYN Error Interrupt Set
union { ... } IEN |
union { ... } INSEL |
union { ... } IS |
union { ... } ISC |
union { ... } ISS |
union { ... } LINCON |
union { ... } LINST |
union { ... } LINSTC |
union { ... } LINSTS |
__IM uint32_t RB8 |
[8..8] Serial Port Receiver Bit 9
__IOM uint32_t reg |
(@ 0x00000000) Port Input Select Register
(@ 0x00000004) Serial Channel Control Register
(@ 0x00000008) Transmit Start Register
(@ 0x0000000C) Serial TX Data Buffer
(@ 0x00000014) Interrupt Enable Register
(@ 0x0000001C) Interrupt Status Set Register
(@ 0x00000020) Interrupt Status Clear Register
(@ 0x00000024) Baud Rate Control Register
(@ 0x00000028) LIN Control Register
(@ 0x00000030) LIN Status Clear Register
(@ 0x00000034) LIN Status Set Register
__IM uint32_t reg |
(@ 0x00000010) Serial RX Data Buffer
(@ 0x00000018) Interrupt Status Register
(@ 0x0000002C) LIN Status Register
__IOM uint32_t REN |
[3..3] Enable Receiver of Serial Port
__IM uint32_t RI |
[1..1] Receive Interrupt Flag
__OM uint32_t RICLR |
[1..1] Receive Interrupt Clear
__IOM uint32_t RIEN |
[1..1] Receive Interrupt Enable
__OM uint32_t RISET |
[1..1] Receive Interrupt Set
__IOM uint32_t RMOD |
[4..4] Receiver Mode
union { ... } RXBUF |
__IM uint32_t RXDATA |
[7..0] Serial Interface RxBuffer Register
__IOM uint32_t RXDSEL |
[1..0] RXD Input Select
union { ... } SCON |
__IOM uint32_t SM0 |
[0..0] Serial Port Operating Mode Selection
__IOM uint32_t SM1 |
[1..1] Serial Port Operating Mode Selection
__IOM uint32_t SM2 |
[2..2] Enable Serial Port Multiprocessor Communication in Mode 2 and 3
__IOM uint32_t TB8 |
[8..8] Serial Port Transmitter Bit 9
__IM uint32_t TI |
[0..0] Transmit Buffer Empty Interrupt Flag
__OM uint32_t TICLR |
[0..0] Transmit Interrupt Clear
__IOM uint32_t TIEN |
[0..0] Transmit Interrupt Enable
__OM uint32_t TISET |
[0..0] Transmit Interrupt Set
union { ... } TSTART |
union { ... } TXBUF |
__IOM uint32_t TXDATA |
[7..0] Serial Interface TxBuffer Register
__IOM uint32_t TXENSEL |
[9..8] Transmit Start Trigger Select
__IOM uint32_t TXEVSEL |
[3..2] TX Start Event Input Select
__IOM uint32_t TXINV |
[5..5] TX Data Inverter Enable
__OM uint32_t TXSTART |
[0..0] Transmit Start Bit