Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
PMU_Type Struct Reference

Detailed Description

Power Management Unit (PMU)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MCNFSTOP: 2
 
      __IOM uint32_t   ITH_SEL: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
VDDP_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   UVWARN_IEN: 1
 
      __IOM uint32_t   OV_IEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
VDDP_IRQEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   UVWARN_IS: 1
 
      __IM uint32_t   OV_IS: 1
 
      uint32_t   __pad0__: 14
 
      __IM uint32_t   UVWARN_STS: 1
 
      uint32_t   __pad1__: 3
 
      __IM uint32_t   ILIM_STS: 1
 
      __IM uint32_t   HCM_STS: 1
 
      uint32_t   __pad2__: 10
 
   }   bit
 
VDDP_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   UVWARN_IS_CLR: 1
 
      __OM uint32_t   OV_IS_CLR: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   UVWARN_STS_CLR: 1
 
      uint32_t   __pad1__: 3
 
      __OM uint32_t   ILIM_STS_CLR: 1
 
      __OM uint32_t   HCM_STS_CLR: 1
 
      uint32_t   __pad2__: 10
 
   }   bit
 
VDDP_STS_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   UVWARN_IS_SET: 1
 
      __OM uint32_t   OV_IS_SET: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   UVWARN_STS_SET: 1
 
      uint32_t   __pad1__: 3
 
      __OM uint32_t   ILIM_STS_SET: 1
 
      __OM uint32_t   HCM_STS_SET: 1
 
      uint32_t   __pad2__: 10
 
   }   bit
 
VDDP_STS_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MCNFSTOP: 2
 
      uint32_t   __pad0__: 30
 
   }   bit
 
VDDC_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   UVWARN_IEN: 1
 
      __IOM uint32_t   OV_IEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
VDDC_IRQEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   UVWARN_IS: 1
 
      __IM uint32_t   OV_IS: 1
 
      uint32_t   __pad0__: 14
 
      __IM uint32_t   UVWARN_STS: 1
 
      uint32_t   __pad1__: 4
 
      __IM uint32_t   HCM_STS: 1
 
      uint32_t   __pad2__: 10
 
   }   bit
 
VDDC_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   UVWARN_IS_CLR: 1
 
      __OM uint32_t   OV_IS_CLR: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   UVWARN_STS_CLR: 1
 
      uint32_t   __pad1__: 4
 
      __OM uint32_t   HCM_STS_CLR: 1
 
      uint32_t   __pad2__: 10
 
   }   bit
 
VDDC_STS_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   UVWARN_IS_SET: 1
 
      __OM uint32_t   OV_IS_SET: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   UVWARN_STS_SET: 1
 
      uint32_t   __pad1__: 4
 
      __OM uint32_t   HCM_STS_SET: 1
 
      uint32_t   __pad2__: 10
 
   }   bit
 
VDDC_STS_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   CYC_EN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
VDDEXT_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   UV_IEN: 1
 
      __IOM uint32_t   OT_IEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
VDDEXT_IRQEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   UV_IS: 1
 
      __IM uint32_t   OT_IS: 1
 
      uint32_t   __pad0__: 14
 
      __IM uint32_t   UV_STS: 1
 
      __IM uint32_t   OT_STS: 1
 
      uint32_t   __pad1__: 14
 
   }   bit
 
VDDEXT_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   UV_IS_CLR: 1
 
      __OM uint32_t   OT_IS_CLR: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   UV_STS_CLR: 1
 
      __OM uint32_t   OT_STS_CLR: 1
 
      uint32_t   __pad1__: 14
 
   }   bit
 
VDDEXT_STS_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   UV_IS_SET: 1
 
      __OM uint32_t   OT_IS_SET: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   UV_STS_SET: 1
 
      __OM uint32_t   OT_STS_SET: 1
 
      uint32_t   __pad1__: 14
 
   }   bit
 
VDDEXT_STS_SET
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   VDDP_TMOUT: 1
 
      __IM uint32_t   VDDC_TMOUT: 1
 
      __IM uint32_t   HPCLK_FAIL: 1
 
      __IM uint32_t   SYS_OT: 1
 
      __IM uint32_t   FSWD_SEQ_FAIL: 1
 
      __IM uint32_t   VDDP_OT: 1
 
      __IM uint32_t   VDDC_OC: 1
 
      uint32_t   __pad0__: 25
 
   }   bit
 
WAKE_FAIL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   VDDP_TMOUT_CLR: 1
 
      __OM uint32_t   VDDC_TMOUT_CLR: 1
 
      __OM uint32_t   HPCLK_FAIL_CLR: 1
 
      __OM uint32_t   SYS_OT_CLR: 1
 
      __OM uint32_t   FSWD_SEQ_FAIL_CLR: 1
 
      __OM uint32_t   VDDP_OT_CLR: 1
 
      __OM uint32_t   VDDC_OC_CLR: 1
 
      uint32_t   __pad0__: 25
 
   }   bit
 
WAKE_FAIL_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   VDDP_TMOUT_SET: 1
 
      __OM uint32_t   VDDC_TMOUT_SET: 1
 
      __OM uint32_t   HPCLK_FAIL_SET: 1
 
      __OM uint32_t   SYS_OT_SET: 1
 
      __OM uint32_t   FSWD_SEQ_FAIL_SET: 1
 
      __OM uint32_t   VDDP_OT_SET: 1
 
      __OM uint32_t   VDDC_OC_SET: 1
 
      uint32_t   __pad0__: 25
 
   }   bit
 
WAKE_FAIL_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TFB: 3
 
      uint32_t   __pad0__: 29
 
   }   bit
 
RST_CTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   VMSUP_UV_RST: 1
 
      __IM uint32_t   MCLK_WD_RST: 1
 
      __IM uint32_t   FS_SLEEPEX_RST: 1
 
      __IM uint32_t   SLEEPEX_RST: 1
 
      __IM uint32_t   STOPEX_RST: 1
 
      __IM uint32_t   PIN_RST: 1
 
      __IM uint32_t   FSWD_RST: 1
 
      __IM uint32_t   WDT_MCU_RST: 1
 
      __IM uint32_t   SOFT_RST: 1
 
      __IM uint32_t   LOCKUP_RST: 1
 
      __IM uint32_t   VDDP_UV_RST: 1
 
      __IM uint32_t   VDDC_UV_RST: 1
 
      __IM uint32_t   SEC_STACK_RST: 1
 
      __IM uint32_t   TMS_RST: 1
 
      uint32_t   __pad0__: 18
 
   }   bit
 
RESET_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   VMSUP_UV_RST_CLR: 1
 
      __OM uint32_t   MCLK_WD_RST_CLR: 1
 
      __OM uint32_t   FS_SLEEPEX_RST_CLR: 1
 
      __OM uint32_t   SLEEPEX_RST_CLR: 1
 
      __OM uint32_t   STOPEX_RST_CLR: 1
 
      __OM uint32_t   PIN_RST_CLR: 1
 
      __OM uint32_t   FSWD_RST_CLR: 1
 
      __OM uint32_t   WDT_MCU_RST_CLR: 1
 
      __OM uint32_t   SOFT_RST_CLR: 1
 
      __OM uint32_t   LOCKUP_RST_CLR: 1
 
      __OM uint32_t   VDDP_UV_RST_CLR: 1
 
      __OM uint32_t   VDDC_UV_RST_CLR: 1
 
      __OM uint32_t   SEC_STACK_RST_CLR: 1
 
      __OM uint32_t   TMS_RST_CLR: 1
 
      uint32_t   __pad0__: 18
 
   }   bit
 
RESET_STS_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   VMSUP_UV_RST_SET: 1
 
      __OM uint32_t   MCLK_WD_RST_SET: 1
 
      __OM uint32_t   FS_SLEEPEX_RST_SET: 1
 
      __OM uint32_t   SLEEPEX_RST_SET: 1
 
      __OM uint32_t   STOPEX_RST_SET: 1
 
      __OM uint32_t   PIN_RST_SET: 1
 
      __OM uint32_t   FSWD_RST_SET: 1
 
      __OM uint32_t   WDT_MCU_RST_SET: 1
 
      __OM uint32_t   SOFT_RST_SET: 1
 
      __OM uint32_t   LOCKUP_RST_SET: 1
 
      __OM uint32_t   VDDP_UV_RST_SET: 1
 
      __OM uint32_t   VDDC_UV_RST_SET: 1
 
      __OM uint32_t   SEC_STACK_RST_SET: 1
 
      __OM uint32_t   TMS_RST_SET: 1
 
      uint32_t   __pad0__: 18
 
   }   bit
 
RESET_STS_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   MON_FT: 1
 
      __IOM uint32_t   GPIO_FT: 2
 
      uint32_t   __pad1__: 28
 
   }   bit
 
WAKE_FILT_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CYC_SENSE_EN: 1
 
      uint32_t   __pad0__: 3
 
      __IOM uint32_t   CYC_ON_TIME: 3
 
      uint32_t   __pad1__: 9
 
      __IOM uint32_t   CYC_SENSE_M03: 4
 
      __IOM uint32_t   CYC_SENSE_E01: 2
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   CYC_WAKE_M03: 4
 
      __IOM uint32_t   CYC_WAKE_E01: 2
 
      uint32_t   __pad3__: 2
 
   }   bit
 
CYC_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI: 1
 
      __IOM uint32_t   FA: 1
 
      __IOM uint32_t   CYC: 1
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   INP: 5
 
      uint32_t   __pad1__: 19
 
   }   bit
 
WAKE_GPIO_CTRL0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI: 1
 
      __IOM uint32_t   FA: 1
 
      __IOM uint32_t   CYC: 1
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   INP: 5
 
      uint32_t   __pad1__: 19
 
   }   bit
 
WAKE_GPIO_CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI: 1
 
      __IOM uint32_t   FA: 1
 
      __IOM uint32_t   CYC: 1
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   INP: 5
 
      uint32_t   __pad1__: 19
 
   }   bit
 
WAKE_GPIO_CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI: 1
 
      __IOM uint32_t   FA: 1
 
      __IOM uint32_t   CYC: 1
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   INP: 5
 
      uint32_t   __pad1__: 19
 
   }   bit
 
WAKE_GPIO_CTRL3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI: 1
 
      __IOM uint32_t   FA: 1
 
      __IOM uint32_t   CYC: 1
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   INP: 5
 
      uint32_t   __pad1__: 19
 
   }   bit
 
WAKE_GPIO_CTRL4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI: 1
 
      __IOM uint32_t   FA: 1
 
      __IOM uint32_t   CYC: 1
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   INP: 5
 
      uint32_t   __pad1__: 19
 
   }   bit
 
WAKE_GPIO_CTRL5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   WAKE_RISE: 1
 
      __IOM uint32_t   WAKE_FALL: 1
 
      __IOM uint32_t   CYC_SENSE_EN: 1
 
      __IOM uint32_t   PU: 1
 
      __IOM uint32_t   PD: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MON_CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   WAKE_RISE: 1
 
      __IOM uint32_t   WAKE_FALL: 1
 
      __IOM uint32_t   CYC_SENSE_EN: 1
 
      __IOM uint32_t   PU: 1
 
      __IOM uint32_t   PD: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MON_CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   WAKE_RISE: 1
 
      __IOM uint32_t   WAKE_FALL: 1
 
      __IOM uint32_t   CYC_SENSE_EN: 1
 
      __IOM uint32_t   PU: 1
 
      __IOM uint32_t   PD: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MON_CTRL3
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   MON1_STS: 1
 
      __IM uint32_t   MON2_STS: 1
 
      __IM uint32_t   MON3_STS: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
MON_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CAN_WAKE_EN: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   CYC_WAKE_EN: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   GPIO0_WAKE_EN: 1
 
      __IOM uint32_t   GPIO1_WAKE_EN: 1
 
      __IOM uint32_t   GPIO2_WAKE_EN: 1
 
      __IOM uint32_t   GPIO3_WAKE_EN: 1
 
      __IOM uint32_t   GPIO4_WAKE_EN: 1
 
      __IOM uint32_t   GPIO5_WAKE_EN: 1
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   MON1_WAKE_EN: 1
 
      __IOM uint32_t   MON2_WAKE_EN: 1
 
      __IOM uint32_t   MON3_WAKE_EN: 1
 
      uint32_t   __pad3__: 1
 
      __IOM uint32_t   VDDP_UVWARN_WAKE_EN: 1
 
      __IOM uint32_t   VDDP_OV_WAKE_EN: 1
 
      __IOM uint32_t   VDDP_HCM_WAKE_EN: 1
 
      __IOM uint32_t   VDDC_UVWARN_WAKE_EN: 1
 
      __IOM uint32_t   VDDC_OV_WAKE_EN: 1
 
      __IOM uint32_t   VDDC_HCM_WAKE_EN: 1
 
      __IOM uint32_t   VDDEXT_OT_WAKE_EN: 1
 
      __IOM uint32_t   VDDEXT_UV_WAKE_EN: 1
 
      __IOM uint32_t   VSDOV_WAKE_EN: 1
 
      uint32_t   __pad4__: 4
 
      __IOM uint32_t   VDDC_RED_EN: 1
 
      uint32_t   __pad5__: 2
 
   }   bit
 
WAKE_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   CAN: 1
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   CYC_WAKE: 1
 
      uint32_t   __pad1__: 1
 
      __IM uint32_t   GPIO0: 1
 
      __IM uint32_t   GPIO1: 1
 
      __IM uint32_t   GPIO2: 1
 
      __IM uint32_t   GPIO3: 1
 
      __IM uint32_t   GPIO4: 1
 
      __IM uint32_t   GPIO5: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   MON1: 1
 
      __IM uint32_t   MON2: 1
 
      __IM uint32_t   MON3: 1
 
      uint32_t   __pad3__: 1
 
      __IM uint32_t   VDDP_UVWARN: 1
 
      __IM uint32_t   VDDP_OV: 1
 
      __IM uint32_t   VDDP_HCM: 1
 
      __IM uint32_t   VDDC_UVWARN: 1
 
      __IM uint32_t   VDDC_OV: 1
 
      __IM uint32_t   VDDC_HCM: 1
 
      __IM uint32_t   VDDEXT_OT: 1
 
      __IM uint32_t   VDDEXT_UV: 1
 
      __IOM uint32_t   VSD_OV: 1
 
      uint32_t   __pad4__: 7
 
   }   bit
 
WAKE_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CAN_CLR: 1
 
      uint32_t   __pad0__: 1
 
      __OM uint32_t   CYC_WAKE_CLR: 1
 
      uint32_t   __pad1__: 1
 
      __OM uint32_t   GPIO0_CLR: 1
 
      __OM uint32_t   GPIO1_CLR: 1
 
      __OM uint32_t   GPIO2_CLR: 1
 
      __OM uint32_t   GPIO3_CLR: 1
 
      __OM uint32_t   GPIO4_CLR: 1
 
      __OM uint32_t   GPIO5_CLR: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   MON1_CLR: 1
 
      __OM uint32_t   MON2_CLR: 1
 
      __OM uint32_t   MON3_CLR: 1
 
      uint32_t   __pad3__: 1
 
      __OM uint32_t   VDDP_UVWARN_CLR: 1
 
      __OM uint32_t   VDDP_OV_CLR: 1
 
      __OM uint32_t   VDDP_HCM_CLR: 1
 
      __OM uint32_t   VDDC_UVWARN_CLR: 1
 
      __OM uint32_t   VDDC_OV_CLR: 1
 
      __OM uint32_t   VDDC_HCM_CLR: 1
 
      __OM uint32_t   VDDEXT_OT_CLR: 1
 
      __OM uint32_t   VDDEXT_UV_CLR: 1
 
      __OM uint32_t   VSD_OV_CLR: 1
 
      uint32_t   __pad4__: 7
 
   }   bit
 
WAKE_STS_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CAN_SET: 1
 
      uint32_t   __pad0__: 1
 
      __OM uint32_t   CYC_WAKE_SET: 1
 
      uint32_t   __pad1__: 1
 
      __OM uint32_t   GPIO0_SET: 1
 
      __OM uint32_t   GPIO1_SET: 1
 
      __OM uint32_t   GPIO2_SET: 1
 
      __OM uint32_t   GPIO3_SET: 1
 
      __OM uint32_t   GPIO4_SET: 1
 
      __OM uint32_t   GPIO5_SET: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   MON1_SET: 1
 
      __OM uint32_t   MON2_SET: 1
 
      __OM uint32_t   MON3_SET: 1
 
      uint32_t   __pad3__: 1
 
      __OM uint32_t   VDDP_UVWARN_SET: 1
 
      __OM uint32_t   VDDP_OV_SET: 1
 
      __OM uint32_t   VDDP_HCM_SET: 1
 
      __OM uint32_t   VDDC_UVWARN_SET: 1
 
      __OM uint32_t   VDDC_OV_SET: 1
 
      __OM uint32_t   VDDC_HCM_SET: 1
 
      __OM uint32_t   VDDEXT_OT_SET: 1
 
      __OM uint32_t   VDDEXT_UV_SET: 1
 
      __OM uint32_t   VSD_OV_SET: 1
 
      uint32_t   __pad4__: 7
 
   }   bit
 
WAKE_STS_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DATA: 32
 
   }   bit
 
GPUDATA0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DATA: 32
 
   }   bit
 
GPUDATA1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DATA: 32
 
   }   bit
 
GPUDATA2
 
__IM uint32_t RESERVED [13]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FI_PU_EN: 1
 
      uint32_t   __pad0__: 15
 
      __IOM uint32_t   TRIG_RST: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
MISC_CTRL
 
__IM uint32_t RESERVED1 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   RST_PIN_EN: 1
 
      uint32_t   __pad1__: 30
 
   }   bit
 
START_CONFIG
 
__IM uint32_t RESERVED2 [390]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 2
 
      uint32_t   __pad0__: 14
 
      __IOM uint32_t   WDP: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   SOW: 2
 
      uint32_t   __pad2__: 6
 
   }   bit
 
WD_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TRIG: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
WD_TRIG
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TRIG: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
WD_TRIG_SOW
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   MCLK_FAIL_STS: 1
 
      __IM uint32_t   VMSUP_UV_STS: 1
 
      __IM uint32_t   VMSUP_OV_STS: 1
 
      __IM uint32_t   WD_FAIL_STS: 1
 
      __IM uint32_t   WD_TEST_FAIL_STS: 1
 
      __IM uint32_t   VDDC_UV_STS: 1
 
      __IM uint32_t   VDDC_OV_STS: 1
 
      __IM uint32_t   VDDP_UV_STS: 1
 
      __IM uint32_t   VDDP_OV_STS: 1
 
      __IM uint32_t   VDDP_OT_STS: 1
 
      __IM uint32_t   VAREF_OV_STS: 1
 
      __IM uint32_t   CSC_OC_STS: 1
 
      __IM uint32_t   CSC_BIST_FAIL_STS: 1
 
      __IM uint32_t   CSC_EN_FAIL_STS: 1
 
      __IM uint32_t   PIN_MON_STS: 1
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   FO_OC_STS: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
FS_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   MCLK_FAIL_STS_CLR: 1
 
      __OM uint32_t   VMSUP_UV_STS_CLR: 1
 
      __OM uint32_t   VMSUP_OV_STS_CLR: 1
 
      __OM uint32_t   WD_FAIL_STS_CLR: 1
 
      __OM uint32_t   WD_TEST_FAIL_STS_CLR: 1
 
      __OM uint32_t   VDDC_UV_STS_CLR: 1
 
      __OM uint32_t   VDDC_OV_STS_CLR: 1
 
      __OM uint32_t   VDDP_UV_STS_CLR: 1
 
      __OM uint32_t   VDDP_OV_STS_CLR: 1
 
      __OM uint32_t   VDDP_OT_STS_CLR: 1
 
      __OM uint32_t   VAREF_OV_STS_CLR: 1
 
      __OM uint32_t   CSC_OC_STS_CLR: 1
 
      __OM uint32_t   CSC_BIST_FAIL_STS_CLR: 1
 
      __OM uint32_t   CSC_EN_FAIL_STS_CLR: 1
 
      __OM uint32_t   PIN_MON_STS_CLR: 1
 
      uint32_t   __pad0__: 1
 
      __OM uint32_t   FO_OC_STS_CLR: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
FS_STS_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   MCLK_FAIL_STS_SET: 1
 
      __OM uint32_t   VMSUP_UV_STS_SET: 1
 
      __OM uint32_t   VMSUP_OV_STS_SET: 1
 
      __OM uint32_t   WD_FAIL_STS_SET: 1
 
      __OM uint32_t   WD_TEST_FAIL_STS_SET: 1
 
      __OM uint32_t   VDDC_UV_STS_SET: 1
 
      __OM uint32_t   VDDC_OV_STS_SET: 1
 
      __OM uint32_t   VDDP_UV_STS_SET: 1
 
      __OM uint32_t   VDDP_OV_STS_SET: 1
 
      __OM uint32_t   VDDP_OT_STS_SET: 1
 
      __OM uint32_t   VAREF_OV_STS_SET: 1
 
      __OM uint32_t   CSC_OC_STS_SET: 1
 
      __OM uint32_t   CSC_BIST_FAIL_STS_SET: 1
 
      __OM uint32_t   CSC_EN_FAIL_STS_SET: 1
 
      __OM uint32_t   PIN_MON_STS_SET: 1
 
      uint32_t   __pad0__: 1
 
      __OM uint32_t   FO_OC_STS_SET: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
FS_STS_SET
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   SSD_STS: 2
 
      __IM uint32_t   FO_STS: 2
 
      uint32_t   __pad0__: 28
 
   }   bit
 
FS_SSD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   SSD_STS_CLR: 1
 
      __OM uint32_t   FO_STS_CLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
FS_SSD_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   SSD_STS_SET: 1
 
      __OM uint32_t   FO_STS_SET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
FS_SSD_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CSC_DIS: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
CSC_CTRL
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆ __pad4__

uint32_t __pad4__

◆ __pad5__

uint32_t __pad5__

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struct { ... } bit

◆ CAN

__IM uint32_t CAN

[0..0] CAN wake status

◆ CAN_CLR

__OM uint32_t CAN_CLR

[0..0] CAN wake status clear

◆ CAN_SET

__OM uint32_t CAN_SET

[0..0] CAN wake status set

◆ CAN_WAKE_EN

__IOM uint32_t CAN_WAKE_EN

[0..0] CAN wake enable

◆ CSC_BIST_FAIL_STS

__IM uint32_t CSC_BIST_FAIL_STS

[12..12] Current sense comparator self-test fail status

◆ CSC_BIST_FAIL_STS_CLR

__OM uint32_t CSC_BIST_FAIL_STS_CLR

[12..12] Current sense comparator self-test fail status

◆ CSC_BIST_FAIL_STS_SET

__OM uint32_t CSC_BIST_FAIL_STS_SET

[12..12] Current sense comparator self test fail status

◆ 

union { ... } CSC_CTRL

◆ CSC_DIS

__IOM uint32_t CSC_DIS

[0..0] Current sense comparator disable

◆ CSC_EN_FAIL_STS

__IM uint32_t CSC_EN_FAIL_STS

[13..13] Current sense comparator enabling fail status

◆ CSC_EN_FAIL_STS_CLR

__OM uint32_t CSC_EN_FAIL_STS_CLR

[13..13] Current sense comparator enable fail status

◆ CSC_EN_FAIL_STS_SET

__OM uint32_t CSC_EN_FAIL_STS_SET

[13..13] Current sense comparator enable fail status

◆ CSC_OC_STS

__IM uint32_t CSC_OC_STS

[11..11] Current Sense comparator overcurrent status

◆ CSC_OC_STS_CLR

__OM uint32_t CSC_OC_STS_CLR

[11..11] Current sense comparator overcurrent status

◆ CSC_OC_STS_SET

__OM uint32_t CSC_OC_STS_SET

[11..11] Current sense comparator overcurrent status

◆ CYC

__IOM uint32_t CYC

[2..2] Cyclic sense enable

◆ 

union { ... } CYC_CTRL

◆ CYC_EN

__IOM uint32_t CYC_EN

[1..1] VDDEXT cyclic sense enable

◆ CYC_ON_TIME

__IOM uint32_t CYC_ON_TIME

[6..4] On time in cyclic sense mode

◆ CYC_SENSE_E01

__IOM uint32_t CYC_SENSE_E01

[21..20] Cyclic sense timer exponent

◆ CYC_SENSE_EN

__IOM uint32_t CYC_SENSE_EN

[0..0] Cyclic sense enable

[3..3] Cyclic sense enable

◆ CYC_SENSE_M03

__IOM uint32_t CYC_SENSE_M03

[19..16] Cyclic sense timer mantissa

◆ CYC_WAKE

__IM uint32_t CYC_WAKE

[2..2] Cyclic wake status

◆ CYC_WAKE_CLR

__OM uint32_t CYC_WAKE_CLR

[2..2] Cyclic wake status

◆ CYC_WAKE_E01

__IOM uint32_t CYC_WAKE_E01

[29..28] Cyclic wake timer exponent

◆ CYC_WAKE_EN

__IOM uint32_t CYC_WAKE_EN

[2..2] Cyclic wake enable

◆ CYC_WAKE_M03

__IOM uint32_t CYC_WAKE_M03

[27..24] Cyclic wake timer mantissa

◆ CYC_WAKE_SET

__OM uint32_t CYC_WAKE_SET

[2..2] Cyclic wake status set

◆ DATA

__IOM uint32_t DATA

[31..0] Data storage

◆ EN

__IOM uint32_t EN

[0..0] VDDEXT enable

[0..0] MON input enable

[1..0] Watchdog enable

◆ FA

__IOM uint32_t FA

[1..1] Falling edge wake enable

◆ FI_PU_EN

__IOM uint32_t FI_PU_EN

[0..0] Failure input pull up enable

◆ FO_OC_STS

__IM uint32_t FO_OC_STS

[16..16] FO overcurrent status (FO)

◆ FO_OC_STS_CLR

__OM uint32_t FO_OC_STS_CLR

[16..16] FO overcurrent status clear (FO)

◆ FO_OC_STS_SET

__OM uint32_t FO_OC_STS_SET

[16..16] FO overcurrent status set (FO)

◆ FO_STS

__IM uint32_t FO_STS

[3..2] Fail output status (FO)

◆ FO_STS_CLR

__OM uint32_t FO_STS_CLR

[1..1] Fail output status clear (FO)

◆ FO_STS_SET

__OM uint32_t FO_STS_SET

[1..1] Fail output status set (FO)

◆ FS_SLEEPEX_RST

__IM uint32_t FS_SLEEPEX_RST

[2..2] Fail Sleep mode exit reset status

◆ FS_SLEEPEX_RST_CLR

__OM uint32_t FS_SLEEPEX_RST_CLR

[2..2] Fail Sleep mode exit reset status clear

◆ FS_SLEEPEX_RST_SET

__OM uint32_t FS_SLEEPEX_RST_SET

[2..2] Fail Sleep mode exit reset status set

◆ 

union { ... } FS_SSD

◆ 

union { ... } FS_SSD_CLR

◆ 

union { ... } FS_SSD_SET

◆ 

union { ... } FS_STS

◆ 

union { ... } FS_STS_CLR

◆ 

union { ... } FS_STS_SET

◆ FSWD_RST

__IM uint32_t FSWD_RST

[6..6] Fail safe watchdog reset status

◆ FSWD_RST_CLR

__OM uint32_t FSWD_RST_CLR

[6..6] Fail safe watchdog reset status clear

◆ FSWD_RST_SET

__OM uint32_t FSWD_RST_SET

[6..6] Fail safe watchdog reset status set

◆ FSWD_SEQ_FAIL

__IM uint32_t FSWD_SEQ_FAIL

[4..4] Fail safe watchdog sequential fail status

◆ FSWD_SEQ_FAIL_CLR

__OM uint32_t FSWD_SEQ_FAIL_CLR

[4..4] Fail safe watchdog sequential fail status clear

◆ FSWD_SEQ_FAIL_SET

__OM uint32_t FSWD_SEQ_FAIL_SET

[4..4] Fails safe watchdog sequential fail status set

◆ GPIO0

__IM uint32_t GPIO0

[4..4] GPIO0 wake status

◆ GPIO0_CLR

__OM uint32_t GPIO0_CLR

[4..4] GPIO0 wake status clear

◆ GPIO0_SET

__OM uint32_t GPIO0_SET

[4..4] GPIO0 wake status set

◆ GPIO0_WAKE_EN

__IOM uint32_t GPIO0_WAKE_EN

[4..4] GPIO0 wake enable

◆ GPIO1

__IM uint32_t GPIO1

[5..5] GPIO1 wake status

◆ GPIO1_CLR

__OM uint32_t GPIO1_CLR

[5..5] GPIO1 wake status clear

◆ GPIO1_SET

__OM uint32_t GPIO1_SET

[5..5] GPIO1 wake status set

◆ GPIO1_WAKE_EN

__IOM uint32_t GPIO1_WAKE_EN

[5..5] GPIO1 wake enable

◆ GPIO2

__IM uint32_t GPIO2

[6..6] GPIO2 wake status

◆ GPIO2_CLR

__OM uint32_t GPIO2_CLR

[6..6] GPIO2 wake status clear

◆ GPIO2_SET

__OM uint32_t GPIO2_SET

[6..6] GPIO2 wake status set

◆ GPIO2_WAKE_EN

__IOM uint32_t GPIO2_WAKE_EN

[6..6] GPIO2 wake enable

◆ GPIO3

__IM uint32_t GPIO3

[7..7] GPIO3 wake status

◆ GPIO3_CLR

__OM uint32_t GPIO3_CLR

[7..7] GPIO3 wake status clear

◆ GPIO3_SET

__OM uint32_t GPIO3_SET

[7..7] GPIO3 wake status set

◆ GPIO3_WAKE_EN

__IOM uint32_t GPIO3_WAKE_EN

[7..7] GPIO3 wake enable

◆ GPIO4

__IM uint32_t GPIO4

[8..8] GPIO4 wake status

◆ GPIO4_CLR

__OM uint32_t GPIO4_CLR

[8..8] GPIO4 wake status clear

◆ GPIO4_SET

__OM uint32_t GPIO4_SET

[8..8] GPIO4 wake status set

◆ GPIO4_WAKE_EN

__IOM uint32_t GPIO4_WAKE_EN

[8..8] GPIO4 wake enable

◆ GPIO5

__IM uint32_t GPIO5

[9..9] GPIO5 wake status

◆ GPIO5_CLR

__OM uint32_t GPIO5_CLR

[9..9] GPIO5 wake status clear

◆ GPIO5_SET

__OM uint32_t GPIO5_SET

[9..9] GPIO5 wake status set

◆ GPIO5_WAKE_EN

__IOM uint32_t GPIO5_WAKE_EN

[9..9] GPIO5 wake enable

◆ GPIO_FT

__IOM uint32_t GPIO_FT

[3..2] GPIO wake up filter time selection

◆ 

union { ... } GPUDATA0

◆ 

union { ... } GPUDATA1

◆ 

union { ... } GPUDATA2

◆ HCM_STS

__IM uint32_t HCM_STS

[21..21] VDDP high current mode status

[21..21] VDDC high current mode status

◆ HCM_STS_CLR

__OM uint32_t HCM_STS_CLR

[21..21] VDDP high current mode status clear

[21..21] VDDC high current mode status clear

◆ HCM_STS_SET

__OM uint32_t HCM_STS_SET

[21..21] VDDP high current mode status set

[21..21] VDDC high current mode status set

◆ HPCLK_FAIL

__IM uint32_t HPCLK_FAIL

[2..2] HP clock fail status

◆ HPCLK_FAIL_CLR

__OM uint32_t HPCLK_FAIL_CLR

[2..2] HP clock fail status clear

◆ HPCLK_FAIL_SET

__OM uint32_t HPCLK_FAIL_SET

[2..2] HP clock fail status set

◆ ILIM_STS

__IM uint32_t ILIM_STS

[20..20] VDDP current limitation status

◆ ILIM_STS_CLR

__OM uint32_t ILIM_STS_CLR

[20..20] VDDP current limitation status clear

◆ ILIM_STS_SET

__OM uint32_t ILIM_STS_SET

[20..20] VDDP Ilimit status set

◆ INP

__IOM uint32_t INP

[12..8] GPIO input pointer

◆ ITH_SEL

__IOM uint32_t ITH_SEL

[2..2] Select current threshold for LCM/HCM mode

◆ LOCKUP_RST

__IM uint32_t LOCKUP_RST

[9..9] ARM core lockup reset status

◆ LOCKUP_RST_CLR

__OM uint32_t LOCKUP_RST_CLR

[9..9] ARM core lockup reset status

◆ LOCKUP_RST_SET

__OM uint32_t LOCKUP_RST_SET

[9..9] ARM core lockup reset status set

◆ MCLK_FAIL_STS

__IM uint32_t MCLK_FAIL_STS

[0..0] Master clock watchdog fail status

◆ MCLK_FAIL_STS_CLR

__OM uint32_t MCLK_FAIL_STS_CLR

[0..0] Master clock watchdog fail status

◆ MCLK_FAIL_STS_SET

__OM uint32_t MCLK_FAIL_STS_SET

[0..0] Master clock watchdog fail status

◆ MCLK_WD_RST

__IM uint32_t MCLK_WD_RST

[1..1] Master clock watchdog reset status

◆ MCLK_WD_RST_CLR

__OM uint32_t MCLK_WD_RST_CLR

[1..1] Master clock watchdog reset status clear

◆ MCLK_WD_RST_SET

__OM uint32_t MCLK_WD_RST_SET

[1..1] Master clock watchdog reset status set

◆ MCNFSTOP

__IOM uint32_t MCNFSTOP

[1..0] Stop mode configuration of VDDP regulator

[1..0] Stop mode configuration of VDDC regulator

◆ 

union { ... } MISC_CTRL

◆ MON1

__IM uint32_t MON1

[12..12] MON1 wake status

◆ MON1_CLR

__OM uint32_t MON1_CLR

[12..12] MON1 wake status clear

◆ MON1_SET

__OM uint32_t MON1_SET

[12..12] MON1 wake status set

◆ MON1_STS

__IM uint32_t MON1_STS

[0..0] MON1 input status

◆ MON1_WAKE_EN

__IOM uint32_t MON1_WAKE_EN

[12..12] MON1 wake enable

◆ MON2

__IM uint32_t MON2

[13..13] MON2 wake status

◆ MON2_CLR

__OM uint32_t MON2_CLR

[13..13] MON2 wake status clear

◆ MON2_SET

__OM uint32_t MON2_SET

[13..13] MON2 wake status set

◆ MON2_STS

__IM uint32_t MON2_STS

[1..1] MON2 input status

◆ MON2_WAKE_EN

__IOM uint32_t MON2_WAKE_EN

[13..13] MON2 wake enable

◆ MON3

__IM uint32_t MON3

[14..14] MON3 wake status

◆ MON3_CLR

__OM uint32_t MON3_CLR

[14..14] MON3 wake status clear

◆ MON3_SET

__OM uint32_t MON3_SET

[14..14] MON3 wake status set

◆ MON3_STS

__IM uint32_t MON3_STS

[2..2] MON3 input status

◆ MON3_WAKE_EN

__IOM uint32_t MON3_WAKE_EN

[14..14] MON3 wake enable

◆ 

union { ... } MON_CTRL1

◆ 

union { ... } MON_CTRL2

◆ 

union { ... } MON_CTRL3

◆ MON_FT

__IOM uint32_t MON_FT

[1..1] MON wake up filter time selection

◆ 

union { ... } MON_STS

◆ OT_IEN

__IOM uint32_t OT_IEN

[1..1] VDDEXT overtemperature interrupt enable

◆ OT_IS

__IM uint32_t OT_IS

[1..1] VDDEXT overtemperature interrupt status

◆ OT_IS_CLR

__OM uint32_t OT_IS_CLR

[1..1] VDDEXT overtemperature interrupt status clear

◆ OT_IS_SET

__OM uint32_t OT_IS_SET

[1..1] VDDEXT overtemperature interrupt status set

◆ OT_STS

__IM uint32_t OT_STS

[17..17] VDDEXT overtemperature status

◆ OT_STS_CLR

__OM uint32_t OT_STS_CLR

[17..17] VDDEXT overtemperature status clear

◆ OT_STS_SET

__OM uint32_t OT_STS_SET

[17..17] VDDEXT overtemperature status set

◆ OV_IEN

__IOM uint32_t OV_IEN

[1..1] VDDP overvoltage interrupt enable

[1..1] VDDC overvoltage interrupt enable

◆ OV_IS

__IM uint32_t OV_IS

[1..1] VDDP overvoltage interrupt status

[1..1] VDDC overvoltage interrupt status

◆ OV_IS_CLR

__OM uint32_t OV_IS_CLR

[1..1] VDDP overvoltage interrupt status clear

[1..1] Overvoltage interrupt status clear

◆ OV_IS_SET

__OM uint32_t OV_IS_SET

[1..1] VDDP overvoltage interrupt status set

[1..1] VDDC overvoltage interrupt status set

◆ PD

__IOM uint32_t PD

[5..5] Input pull down current source enable

◆ PIN_MON_STS

__IM uint32_t PIN_MON_STS

[14..14] Pin monitor fail status (FI)

◆ PIN_MON_STS_CLR

__OM uint32_t PIN_MON_STS_CLR

[14..14] Pin monitor fail status (FI)

◆ PIN_MON_STS_SET

__OM uint32_t PIN_MON_STS_SET

[14..14] Pin monitor fail status (FI)

◆ PIN_RST

__IM uint32_t PIN_RST

[5..5] Pin-Reset reset status

◆ PIN_RST_CLR

__OM uint32_t PIN_RST_CLR

[5..5] Pin reset Status Clear

◆ PIN_RST_SET

__OM uint32_t PIN_RST_SET

[5..5] Pin reset status set

◆ PU

__IOM uint32_t PU

[4..4] Input pull up current Source enable

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) VDDP voltage regulator control register

(@ 0x00000004) VDDP interrupt enable register

(@ 0x0000000C) VDDP regulator status clear register

(@ 0x00000010) VDDP regulator status set register

(@ 0x00000014) VDDC voltage regulator control register

(@ 0x00000018) VDDC interrupt enable register

(@ 0x00000020) VDDC regulator status clear register

(@ 0x00000024) VDDC regulator status set register

(@ 0x00000028) VDDEXT voltage regulator control register

(@ 0x0000002C) VDDEXT interrupt enable register

(@ 0x00000034) VDDEXT regulator status register clear

(@ 0x00000038) VDDEXT regulator status register set

(@ 0x00000040) Wake fail status clear register

(@ 0x00000044) Wake fail status set register

(@ 0x00000048) RESET pin control register

(@ 0x00000050) Reset status clear register

(@ 0x00000054) Reset status set register

(@ 0x00000058) Wake up filter control register

(@ 0x0000005C) Cyclic sense / Cyclic wake control register

(@ 0x00000060) GPIO wake control register

(@ 0x00000064) GPIO wake control register

(@ 0x00000068) GPIO wake control register

(@ 0x0000006C) GPIO wake control register

(@ 0x00000070) GPIO wake control register

(@ 0x00000074) GPIO wake control register

(@ 0x00000078) MON input control register

(@ 0x0000007C) MON input control register

(@ 0x00000080) MON input control register

(@ 0x00000088) Wake control register

(@ 0x0000008C) Wake status register

(@ 0x00000090) Wake status clear register

(@ 0x00000094) Wake status set register

(@ 0x00000098) General purpose user data register

(@ 0x0000009C) General purpose user data register

(@ 0x000000A0) General purpose user data register

(@ 0x000000D8) Miscellaneous control register

(@ 0x000000E4) Start configuration control register

(@ 0x00000700) Watchdog control register

(@ 0x00000704) Watchdog trigger register

(@ 0x00000708) Watchdog SOW trigger register

(@ 0x00000710) Functional safety status clear register

(@ 0x00000714) Functional safety status set register

(@ 0x0000071C) Safe state status clear register

(@ 0x00000720) Safe state status set register

(@ 0x00000724) Current sense comparator control register

◆ reg [2/2]

__IM uint32_t reg

(@ 0x00000008) VDDP regulator status register

(@ 0x0000001C) VDDC regulator status register

(@ 0x00000030) VDDEXT regulator status register

(@ 0x0000003C) Wake fail status register

(@ 0x0000004C) Reset status register

(@ 0x00000084) MON input status register

(@ 0x0000070C) Functional safety status register

(@ 0x00000718) Safe state status register

◆ RESERVED

__IM uint32_t RESERVED[13]

◆ RESERVED1

__IM uint32_t RESERVED1[2]

◆ RESERVED2

__IM uint32_t RESERVED2[390]

◆ 

union { ... } RESET_STS

◆ 

union { ... } RESET_STS_CLR

◆ 

union { ... } RESET_STS_SET

◆ RI

__IOM uint32_t RI

[0..0] Rising edge wake enable

◆ 

union { ... } RST_CTRL

◆ RST_PIN_EN

__IOM uint32_t RST_PIN_EN

[1..1] Reset PIN enable

◆ SEC_STACK_RST

__IM uint32_t SEC_STACK_RST

[12..12] Secure stack overflow reset status

◆ SEC_STACK_RST_CLR

__OM uint32_t SEC_STACK_RST_CLR

[12..12] Secure stack overflow reset status clear

◆ SEC_STACK_RST_SET

__OM uint32_t SEC_STACK_RST_SET

[12..12] Secure stack overflow reset status set

◆ SLEEPEX_RST

__IM uint32_t SLEEPEX_RST

[3..3] Sleep mode exit reset status

◆ SLEEPEX_RST_CLR

__OM uint32_t SLEEPEX_RST_CLR

[3..3] Sleep mode exit reset status clear

◆ SLEEPEX_RST_SET

__OM uint32_t SLEEPEX_RST_SET

[3..3] Sleep mode exit reset status set

◆ SOFT_RST

__IM uint32_t SOFT_RST

[8..8] Soft reset status

◆ SOFT_RST_CLR

__OM uint32_t SOFT_RST_CLR

[8..8] Soft reset status clear

◆ SOFT_RST_SET

__OM uint32_t SOFT_RST_SET

[8..8] Soft reset status set

◆ SOW

__IOM uint32_t SOW

[25..24] Short open window selection - Can only be configured in LOW

◆ SSD_STS

__IM uint32_t SSD_STS

[1..0] Safe shutdown status

◆ SSD_STS_CLR

__OM uint32_t SSD_STS_CLR

[0..0] Safe shutdown status clear

◆ SSD_STS_SET

__OM uint32_t SSD_STS_SET

[0..0] Safe shutdown status set

◆ 

union { ... } START_CONFIG

◆ STOPEX_RST

__IM uint32_t STOPEX_RST

[4..4] Stop mode exit reset status

◆ STOPEX_RST_CLR

__OM uint32_t STOPEX_RST_CLR

[4..4] Stop mode exit reset status clear

◆ STOPEX_RST_SET

__OM uint32_t STOPEX_RST_SET

[4..4] Stop mode exit reset status set

◆ SYS_OT

__IM uint32_t SYS_OT

[3..3] System overtemperature status

◆ SYS_OT_CLR

__OM uint32_t SYS_OT_CLR

[3..3] System overtemperature status clear

◆ SYS_OT_SET

__OM uint32_t SYS_OT_SET

[3..3] System overtemperature status set

◆ TFB

__IOM uint32_t TFB

[2..0] Reset blind time selection

◆ TMS_RST

__IM uint32_t TMS_RST

[13..13] TMS reset status

◆ TMS_RST_CLR

__OM uint32_t TMS_RST_CLR

[13..13] TMS reset Status Clear

◆ TMS_RST_SET

__OM uint32_t TMS_RST_SET

[13..13] TNS reset status set

◆ TRIG

__IOM uint32_t TRIG

[0..0] Trigger bit for long open- /window Mode

[0..0] Trigger bit for short open window mode

◆ TRIG_RST

__IOM uint32_t TRIG_RST

[16..16] Trigger Pin Reset

◆ UV_IEN

__IOM uint32_t UV_IEN

[0..0] VDDEXT undervoltage interrupt enable

◆ UV_IS

__IM uint32_t UV_IS

[0..0] VDDEXT undervoltage interrupt status

◆ UV_IS_CLR

__OM uint32_t UV_IS_CLR

[0..0] VDDEXT undervoltage interrupt status clear

◆ UV_IS_SET

__OM uint32_t UV_IS_SET

[0..0] VDDEXT undervoltage interrupt status set

◆ UV_STS

__IM uint32_t UV_STS

[16..16] VDDEXT undervoltage status

◆ UV_STS_CLR

__OM uint32_t UV_STS_CLR

[16..16] VDDEXT undervoltage status clear

◆ UV_STS_SET

__OM uint32_t UV_STS_SET

[16..16] VDDEXT undervoltage status set

◆ UVWARN_IEN

__IOM uint32_t UVWARN_IEN

[0..0] VDDP undervoltage warning interrupt enable

[0..0] VDDC undervoltage warning interrupt enable

◆ UVWARN_IS

__IM uint32_t UVWARN_IS

[0..0] VDDP undervoltage warning interrupt status

[0..0] VDDC undervoltage warning interrupt status

◆ UVWARN_IS_CLR

__OM uint32_t UVWARN_IS_CLR

[0..0] VDDP undervoltage warning interrupt status clear

[0..0] VDDC undervoltage warning interrupt status clear

◆ UVWARN_IS_SET

__OM uint32_t UVWARN_IS_SET

[0..0] VDDP undervoltage warning interrupt status set

[0..0] VDDC undervoltage warning interrupt status set

◆ UVWARN_STS

__IM uint32_t UVWARN_STS

[16..16] VDDP undervoltage warning status

[16..16] VDDC undervoltage warning status

◆ UVWARN_STS_CLR

__OM uint32_t UVWARN_STS_CLR

[16..16] VDDP undervoltage warning status clear

[16..16] VDDC undervoltage warning status clear

◆ UVWARN_STS_SET

__OM uint32_t UVWARN_STS_SET

[16..16] VDDP undervoltage warning status set

[16..16] VDDC undervoltage warning status set

◆ VAREF_OV_STS

__IM uint32_t VAREF_OV_STS

[10..10] VAREF overvoltage status

◆ VAREF_OV_STS_CLR

__OM uint32_t VAREF_OV_STS_CLR

[10..10] VAREF overvoltage status

◆ VAREF_OV_STS_SET

__OM uint32_t VAREF_OV_STS_SET

[10..10] VAREF overvoltage status

◆ 

union { ... } VDDC_CTRL

◆ VDDC_HCM

__IM uint32_t VDDC_HCM

[21..21] VDDC high current mode wake status

◆ VDDC_HCM_CLR

__OM uint32_t VDDC_HCM_CLR

[21..21] VDDC high current mode wake status clear

◆ VDDC_HCM_SET

__OM uint32_t VDDC_HCM_SET

[21..21] VDDC high current mode wake status set

◆ VDDC_HCM_WAKE_EN

__IOM uint32_t VDDC_HCM_WAKE_EN

[21..21] Stop mode VDDC high current mode wake enable

◆ 

union { ... } VDDC_IRQEN

◆ VDDC_OC

__IM uint32_t VDDC_OC

[6..6] VDDC overcurrent Status

◆ VDDC_OC_CLR

__OM uint32_t VDDC_OC_CLR

[6..6] VDDC overcurrent status clear

◆ VDDC_OC_SET

__OM uint32_t VDDC_OC_SET

[6..6] VDDC overcurrent status set

◆ VDDC_OV

__IM uint32_t VDDC_OV

[20..20] VDDC overvoltage wake status

◆ VDDC_OV_CLR

__OM uint32_t VDDC_OV_CLR

[20..20] VDDC overvoltage wake status clear

◆ VDDC_OV_SET

__OM uint32_t VDDC_OV_SET

[20..20] VDDC overvoltage wake status set

◆ VDDC_OV_STS

__IM uint32_t VDDC_OV_STS

[6..6] VDDC overvoltage status

◆ VDDC_OV_STS_CLR

__OM uint32_t VDDC_OV_STS_CLR

[6..6] VDDC overvoltage status

◆ VDDC_OV_STS_SET

__OM uint32_t VDDC_OV_STS_SET

[6..6] VDDC overvoltage status

◆ VDDC_OV_WAKE_EN

__IOM uint32_t VDDC_OV_WAKE_EN

[20..20] Stop mode VDDC overvoltage wake enable

◆ VDDC_RED_EN

__IOM uint32_t VDDC_RED_EN

[29..29] Stop mode - VDDC output voltage reduction enable

◆ 

union { ... } VDDC_STS

◆ 

union { ... } VDDC_STS_CLR

◆ 

union { ... } VDDC_STS_SET

◆ VDDC_TMOUT

__IM uint32_t VDDC_TMOUT

[1..1] VDDP regulator timeout

◆ VDDC_TMOUT_CLR

__OM uint32_t VDDC_TMOUT_CLR

[1..1] VDDP regulator timeout status clear

◆ VDDC_TMOUT_SET

__OM uint32_t VDDC_TMOUT_SET

[1..1] VDDP regulator timeout status set

◆ VDDC_UV_RST

__IM uint32_t VDDC_UV_RST

[11..11] VDDC undervoltage reset status

◆ VDDC_UV_RST_CLR

__OM uint32_t VDDC_UV_RST_CLR

[11..11] VDDC undervoltage reset status clear

◆ VDDC_UV_RST_SET

__OM uint32_t VDDC_UV_RST_SET

[11..11] VDDC undervoltage reset status set

◆ VDDC_UV_STS

__IM uint32_t VDDC_UV_STS

[5..5] VDDC undervoltage status

◆ VDDC_UV_STS_CLR

__OM uint32_t VDDC_UV_STS_CLR

[5..5] VDDC undervoltage status

◆ VDDC_UV_STS_SET

__OM uint32_t VDDC_UV_STS_SET

[5..5] VDDC undervoltage status

◆ VDDC_UVWARN

__IM uint32_t VDDC_UVWARN

[19..19] VDDC undervoltage warning wake status

◆ VDDC_UVWARN_CLR

__OM uint32_t VDDC_UVWARN_CLR

[19..19] VDDC undervoltage warning wake status clear

◆ VDDC_UVWARN_SET

__OM uint32_t VDDC_UVWARN_SET

[19..19] VDDC undervoltage warning wake status set

◆ VDDC_UVWARN_WAKE_EN

__IOM uint32_t VDDC_UVWARN_WAKE_EN

[19..19] Stop mode VDDC undervoltage warning wake enable

◆ 

union { ... } VDDEXT_CTRL

◆ 

union { ... } VDDEXT_IRQEN

◆ VDDEXT_OT

__IM uint32_t VDDEXT_OT

[22..22] VDDEXT overtemperature wake status

◆ VDDEXT_OT_CLR

__OM uint32_t VDDEXT_OT_CLR

[22..22] VDDEXT overtemperature wake status clear

◆ VDDEXT_OT_SET

__OM uint32_t VDDEXT_OT_SET

[22..22] VDDEXT overtemperature wake status set

◆ VDDEXT_OT_WAKE_EN

__IOM uint32_t VDDEXT_OT_WAKE_EN

[22..22] Stop mode VDDEXT overtemperature wake enable

◆ 

union { ... } VDDEXT_STS

◆ 

union { ... } VDDEXT_STS_CLR

◆ 

union { ... } VDDEXT_STS_SET

◆ VDDEXT_UV

__IM uint32_t VDDEXT_UV

[23..23] VDDEXT undervoltage wake status

◆ VDDEXT_UV_CLR

__OM uint32_t VDDEXT_UV_CLR

[23..23] VDDEXT undervoltage wake status clear

◆ VDDEXT_UV_SET

__OM uint32_t VDDEXT_UV_SET

[23..23] VDDEXT undervoltage wake status set

◆ VDDEXT_UV_WAKE_EN

__IOM uint32_t VDDEXT_UV_WAKE_EN

[23..23] Stop mode VDDEXT undervoltage wake enable

◆ 

union { ... } VDDP_CTRL

◆ VDDP_HCM

__IM uint32_t VDDP_HCM

[18..18] VDDP high current mode wake Status

◆ VDDP_HCM_CLR

__OM uint32_t VDDP_HCM_CLR

[18..18] VDDP high current mode wake status clear

◆ VDDP_HCM_SET

__OM uint32_t VDDP_HCM_SET

[18..18] VDDP high current mode wake status set

◆ VDDP_HCM_WAKE_EN

__IOM uint32_t VDDP_HCM_WAKE_EN

[18..18] Stop mode VDDP high current mode wake enable

◆ 

union { ... } VDDP_IRQEN

◆ VDDP_OT

__IM uint32_t VDDP_OT

[5..5] VDDP regulator overtemperature status

◆ VDDP_OT_CLR

__OM uint32_t VDDP_OT_CLR

[5..5] VDDP regulator overtemperature status clear

◆ VDDP_OT_SET

__OM uint32_t VDDP_OT_SET

[5..5] VDDP regulator overtemperature status set

◆ VDDP_OT_STS

__IM uint32_t VDDP_OT_STS

[9..9] VDDP overtemperature status

◆ VDDP_OT_STS_CLR

__OM uint32_t VDDP_OT_STS_CLR

[9..9] VDDP overtemperature status

◆ VDDP_OT_STS_SET

__OM uint32_t VDDP_OT_STS_SET

[9..9] VDDP overtemperature status

◆ VDDP_OV

__IM uint32_t VDDP_OV

[17..17] VDDP overvoltage wake status

◆ VDDP_OV_CLR

__OM uint32_t VDDP_OV_CLR

[17..17] VDDP overvoltage wake status clear

◆ VDDP_OV_SET

__OM uint32_t VDDP_OV_SET

[17..17] VDDP overvoltage wake status set

◆ VDDP_OV_STS

__IM uint32_t VDDP_OV_STS

[8..8] VDDP overvoltage status

◆ VDDP_OV_STS_CLR

__OM uint32_t VDDP_OV_STS_CLR

[8..8] VDDP overvoltage status

◆ VDDP_OV_STS_SET

__OM uint32_t VDDP_OV_STS_SET

[8..8] VDDP overvoltage status

◆ VDDP_OV_WAKE_EN

__IOM uint32_t VDDP_OV_WAKE_EN

[17..17] Stop mode VDDP overvoltage wake enable

◆ 

union { ... } VDDP_STS

◆ 

union { ... } VDDP_STS_CLR

◆ 

union { ... } VDDP_STS_SET

◆ VDDP_TMOUT

__IM uint32_t VDDP_TMOUT

[0..0] VDDP regulator timeout

◆ VDDP_TMOUT_CLR

__OM uint32_t VDDP_TMOUT_CLR

[0..0] VDDP Regulator timeout Status Clear

◆ VDDP_TMOUT_SET

__OM uint32_t VDDP_TMOUT_SET

[0..0] VDDP regulator timeout status set

◆ VDDP_UV_RST

__IM uint32_t VDDP_UV_RST

[10..10] VDDP undervoltage reset status

◆ VDDP_UV_RST_CLR

__OM uint32_t VDDP_UV_RST_CLR

[10..10] VDDP undervoltage reset status clear

◆ VDDP_UV_RST_SET

__OM uint32_t VDDP_UV_RST_SET

[10..10] VDDP undervoltage reset status set

◆ VDDP_UV_STS

__IM uint32_t VDDP_UV_STS

[7..7] VDDP undervoltage status

◆ VDDP_UV_STS_CLR

__OM uint32_t VDDP_UV_STS_CLR

[7..7] VDDP undervoltage status

◆ VDDP_UV_STS_SET

__OM uint32_t VDDP_UV_STS_SET

[7..7] VDDP undervoltage status

◆ VDDP_UVWARN

__IM uint32_t VDDP_UVWARN

[16..16] VDDP undervoltage warning wake status

◆ VDDP_UVWARN_CLR

__OM uint32_t VDDP_UVWARN_CLR

[16..16] VDDP undervoltage warning wake status clear

◆ VDDP_UVWARN_SET

__OM uint32_t VDDP_UVWARN_SET

[16..16] VDDP undervoltage warning wake status set

◆ VDDP_UVWARN_WAKE_EN

__IOM uint32_t VDDP_UVWARN_WAKE_EN

[16..16] Stop mode VDDP undervoltage warning wake enable

◆ VMSUP_OV_STS

__IM uint32_t VMSUP_OV_STS

[2..2] Master supply overvoltage status

◆ VMSUP_OV_STS_CLR

__OM uint32_t VMSUP_OV_STS_CLR

[2..2] Master supply overvoltage status

◆ VMSUP_OV_STS_SET

__OM uint32_t VMSUP_OV_STS_SET

[2..2] Master supply overvoltage status

◆ VMSUP_UV_RST

__IM uint32_t VMSUP_UV_RST

[0..0] Master supply undervoltage reset status

◆ VMSUP_UV_RST_CLR

__OM uint32_t VMSUP_UV_RST_CLR

[0..0] Master supply undervoltage reset status clear

◆ VMSUP_UV_RST_SET

__OM uint32_t VMSUP_UV_RST_SET

[0..0] Master supply undervoltage reset status set

◆ VMSUP_UV_STS

__IM uint32_t VMSUP_UV_STS

[1..1] Master supply undervoltage status

◆ VMSUP_UV_STS_CLR

__OM uint32_t VMSUP_UV_STS_CLR

[1..1] Master supply undervoltage status

◆ VMSUP_UV_STS_SET

__OM uint32_t VMSUP_UV_STS_SET

[1..1] Master supply undervoltage status

◆ VSD_OV

__IOM uint32_t VSD_OV

[24..24] VSD overvoltage wake status

◆ VSD_OV_CLR

__OM uint32_t VSD_OV_CLR

[24..24] VSD undervoltage wake status clear

◆ VSD_OV_SET

__OM uint32_t VSD_OV_SET

[24..24] VSD overvoltage wake status set

◆ VSDOV_WAKE_EN

__IOM uint32_t VSDOV_WAKE_EN

[24..24] VSD overvoltage wake enable

◆ 

union { ... } WAKE_CTRL

◆ 

union { ... } WAKE_FAIL_CLR

◆ 

union { ... } WAKE_FAIL_SET

◆ 

union { ... } WAKE_FAIL_STS

◆ WAKE_FALL

__IOM uint32_t WAKE_FALL

[2..2] Falling edge wake enable

◆ 

union { ... } WAKE_FILT_CTRL

◆ 

union { ... } WAKE_GPIO_CTRL0

◆ 

union { ... } WAKE_GPIO_CTRL1

◆ 

union { ... } WAKE_GPIO_CTRL2

◆ 

union { ... } WAKE_GPIO_CTRL3

◆ 

union { ... } WAKE_GPIO_CTRL4

◆ 

union { ... } WAKE_GPIO_CTRL5

◆ WAKE_RISE

__IOM uint32_t WAKE_RISE

[1..1] Rising edge wake enable

◆ 

union { ... } WAKE_STS

◆ 

union { ... } WAKE_STS_CLR

◆ 

union { ... } WAKE_STS_SET

◆ 

union { ... } WD_CTRL

◆ WD_FAIL_STS

__IM uint32_t WD_FAIL_STS

[3..3] Watchdog Fail status

◆ WD_FAIL_STS_CLR

__OM uint32_t WD_FAIL_STS_CLR

[3..3] Watchdog fail status

◆ WD_FAIL_STS_SET

__OM uint32_t WD_FAIL_STS_SET

[3..3] Watchdog fail status

◆ WD_TEST_FAIL_STS

__IM uint32_t WD_TEST_FAIL_STS

[4..4] Watchdog self-test fail status

◆ WD_TEST_FAIL_STS_CLR

__OM uint32_t WD_TEST_FAIL_STS_CLR

[4..4] Watchdog self test fail status

◆ WD_TEST_FAIL_STS_SET

__OM uint32_t WD_TEST_FAIL_STS_SET

[4..4] Watchdog self test fail status

◆ 

union { ... } WD_TRIG

◆ 

union { ... } WD_TRIG_SOW

◆ WDP

__IOM uint32_t WDP

[21..16] Watchdog period selection

◆ WDT_MCU_RST

__IM uint32_t WDT_MCU_RST

[7..7] MCU watchdog timer reset status

◆ WDT_MCU_RST_CLR

__OM uint32_t WDT_MCU_RST_CLR

[7..7] MCU watchdog timer reset status clear

◆ WDT_MCU_RST_SET

__OM uint32_t WDT_MCU_RST_SET

[7..7] MCU watchdog timer reset status set


The documentation for this struct was generated from the following file: