Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
isr.h
Go to the documentation of this file.
1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
28 
40 /*******************************************************************************
41 ** Author(s) Identity **
42 ********************************************************************************
43 ** Initials Name **
44 ** ---------------------------------------------------------------------------**
45 ** DM Daniel Mysliwitz **
46 ** BG Blandine Guillot **
47 ** JO Julia Ott **
48 ** PS Patrik Schwarz **
49 *******************************************************************************/
50 
51 /*******************************************************************************
52 ** Revision Control History **
53 ********************************************************************************
54 ** V0.1.0: 2020-08-24, JO: Initial version **
55 ** V0.2.0: 2020-09-29, JO: EP-483: Fixed condition for the 'Check if NVIC **
56 ** node x is enabled' in all **
57 ** isr_nvic_irqx_handler.c files **
58 ** V0.3.0: 2020-10-20, BG: EP-532: Added function prototypes from NVIC **
59 ** handlers and isr_exceptions.c **
60 ** V0.4.0: 2020-10-28, JO: EP-563: Added NMI_Handler to isr_exceptions.c, **
61 ** Formatted files isr related files **
62 ** V0.4.1: 2020-11-02, JO: EP-556: Removed ADC2 EOC Fail interrupts **
63 ** V0.4.2: 2020-11-12, JO: EP-590: Removed \param none and \return none to **
64 ** avoid doxygen warning **
65 ** V0.4.3: 2020-12-02, JO: EP-610: Fixed error related to EXTINT on falling **
66 ** edge **
67 ** Moved callback declarations from c files **
68 ** to header to prevent MISRA warning **
69 ** The following rules are globally deactivated: **
70 ** - Warning 572: Excessive shift value **
71 ** (precision 0 shifted right by ...) **
72 ** V0.4.4: 2020-12-03, BG: EP-631: Added interrupt handling for CAN **
73 ** V0.4.5: 2020-12-18, JO: EP-599: Defined each *_INT_EN macros to 0 in **
74 ** case it is not defined, done in isr.h **
75 ** V0.4.6: 2021-02-18, BG: EP-691: Removed *_INT_EN macros for CANNODE and **
76 ** CANMSGOBJ0 **
77 ** Removed interrupt handling for CANMSGOBJ1 and **
78 ** CANMSGOBJ1 due to restructuration in tle989x.h **
79 ** V0.4.7: 2021-05-07, JO: EP-812: Made u32_globTimestamp_ms volatile **
80 ** V0.4.8: 2021-08-18, JO: EP-806: Added function INT_getGlobTimestamp **
81 ** V0.4.9: 2021-11-12, JO: EP-937: Updated copyright and branding **
82 ** V0.5.0: 2022-04-25, JO: EP-1139: Added initialization to 0 of variables **
83 ** u8_interrupt_cnt_irq to avoid MISRA violation **
84 ** V0.5.1: 2023-05-05, PS: EP-1242: Removed content from CAN ISR NVIC **
85 ** Handler, to be implemented by the user **
86 *******************************************************************************/
87 
88 #ifndef _ISR_H
89 #define _ISR_H
90 
91 /*******************************************************************************
92 ** Includes **
93 *******************************************************************************/
94 
95 #include "isr.h"
96 #include "types.h"
97 #include "tle989x.h"
98 #include "tle_variants.h"
99 #include "isr_defines.h"
100 
101 
102 /*******************************************************************************
103 ** Global Macro Declarations **
104 *******************************************************************************/
105 
106 #define NMI_INP_NMI 3
107 
108 #define WARN_INP_NVIC_IRQ0 0
109 #define WARN_INP_NVIC_IRQ1 1
110 #define CCU7_INP_NVIC_IRQ2 0
111 #define CCU7_INP_NVIC_IRQ3 1
112 #define CCU7_INP_NVIC_IRQ4 2
113 #define CCU7_INP_NVIC_IRQ5 3
114 #define MEMCTRL_INP_NVIC_IRQ6 0
115 #define GPT12_INP_NVIC_IRQ7 0
116 #define GPT12_INP_NVIC_IRQ8 1
117 #define ADC2_INP_NVIC_IRQ10 0
118 #define ADC2_INP_NVIC_IRQ11 1
119 #define MON_INP_NVIC_IRQ12 0
120 #define MON_INP_NVIC_IRQ13 1
121 #define ADC1_INP_NVIC_IRQ14 0
122 #define ADC1_INP_NVIC_IRQ15 1
123 #define ADC1_INP_NVIC_IRQ16 2
124 #define ADC1_INP_NVIC_IRQ17 3
125 #define BEMF_SDADC_INP_NVIC_IRQ18 0
126 #define BEMF_SDADC_INP_NVIC_IRQ19 1
127 #define EXTINT_INP_NVIC_IRQ20 0
128 #define EXTINT_INP_NVIC_IRQ21 1
129 #define UART_INP_NVIC_IRQ22 0
130 #define UART_INP_NVIC_IRQ23 1
131 #define SSC_INP_NVIC_IRQ24 0
132 #define SSC_INP_NVIC_IRQ25 1
133 #define CAN_INP_NVIC_IRQ26 0
134 #define CAN_INP_NVIC_IRQ27 1
135 #define CAN_INP_NVIC_IRQ28 2
136 #define DMA_INP_NVIC_IRQ29 0
137 #define DMA_INP_NVIC_IRQ30 1
138 #define T20_INP_NVIC_IRQ9 0
139 #define T21_INP_NVIC_IRQ31 0
140 
141 #ifndef SCU_NMICON_NMIXTALEN_NMI_EN
142  #define SCU_NMICON_NMIXTALEN_NMI_EN 0
143 #endif
144 #ifndef SCU_NMICON_NMIPLL0EN_NMI_EN
145  #define SCU_NMICON_NMIPLL0EN_NMI_EN 0
146 #endif
147 #ifndef SCU_NMICON_NMIPLL1EN_NMI_EN
148  #define SCU_NMICON_NMIPLL1EN_NMI_EN 0
149 #endif
150 #ifndef MEMCTRL_NMICON_NMIDSEN_NMI_EN
151  #define MEMCTRL_NMICON_NMIDSEN_NMI_EN 0
152 #endif
153 #ifndef MEMCTRL_NMICON_NMIPSEN_NMI_EN
154  #define MEMCTRL_NMICON_NMIPSEN_NMI_EN 0
155 #endif
156 #ifndef MEMCTRL_NMICON_NMICDEN_NMI_EN
157  #define MEMCTRL_NMICON_NMICDEN_NMI_EN 0
158 #endif
159 #ifndef MEMCTRL_NMICON_NMINVM0EN_NMI_EN
160  #define MEMCTRL_NMICON_NMINVM0EN_NMI_EN 0
161 #endif
162 #ifndef MEMCTRL_NMICON_NMINVM1EN_NMI_EN
163  #define MEMCTRL_NMICON_NMINVM1EN_NMI_EN 0
164 #endif
165 #ifndef MEMCTRL_NMICON_NMIMAP0EN_NMI_EN
166  #define MEMCTRL_NMICON_NMIMAP0EN_NMI_EN 0
167 #endif
168 #ifndef MEMCTRL_NMICON_NMIMAP1EN_NMI_EN
169  #define MEMCTRL_NMICON_NMIMAP1EN_NMI_EN 0
170 #endif
171 #ifndef MEMCTRL_NMICON_NMIWDTEN_NMI_EN
172  #define MEMCTRL_NMICON_NMIWDTEN_NMI_EN 0
173 #endif
174 #ifndef MEMCTRL_NMICON_NMISTOFEN_NMI_EN
175  #define MEMCTRL_NMICON_NMISTOFEN_NMI_EN 0
176 #endif
177 #ifndef ADC2_UPTH0_INT_EN
178  #define ADC2_UPTH0_INT_EN 0
179 #endif
180 #ifndef ADC2_LOTH0_INT_EN
181  #define ADC2_LOTH0_INT_EN 0
182 #endif
183 #ifndef ADC2_LOTH1_INT_EN
184  #define ADC2_LOTH1_INT_EN 0
185 #endif
186 #ifndef ADC2_UPTH2_INT_EN
187  #define ADC2_UPTH2_INT_EN 0
188 #endif
189 #ifndef ADC2_LOTH2_INT_EN
190  #define ADC2_LOTH2_INT_EN 0
191 #endif
192 #ifndef ADC2_LOTH3_INT_EN
193  #define ADC2_LOTH3_INT_EN 0
194 #endif
195 #ifndef ADC2_UPTH4_INT_EN
196  #define ADC2_UPTH4_INT_EN 0
197 #endif
198 #ifndef CANTRX_BUS_TO_INT_EN
199  #define CANTRX_BUS_TO_INT_EN 0
200 #endif
201 #ifndef CANTRX_TXD_TO_INT_EN
202  #define CANTRX_TXD_TO_INT_EN 0
203 #endif
204 #ifndef CANTRX_OT_INT_EN
205  #define CANTRX_OT_INT_EN 0
206 #endif
207 #ifndef CANTRX_BUS_ACT_INT_EN
208  #define CANTRX_BUS_ACT_INT_EN 0
209 #endif
210 #ifndef BDRV_LS1_OC_INT_EN
211  #define BDRV_LS1_OC_INT_EN 0
212 #endif
213 #ifndef BDRV_LS1_DS_INT_EN
214  #define BDRV_LS1_DS_INT_EN 0
215 #endif
216 #ifndef BDRV_HS1_OC_INT_EN
217  #define BDRV_HS1_OC_INT_EN 0
218 #endif
219 #ifndef BDRV_HS1_DS_INT_EN
220  #define BDRV_HS1_DS_INT_EN 0
221 #endif
222 #ifndef BDRV_LS2_OC_INT_EN
223  #define BDRV_LS2_OC_INT_EN 0
224 #endif
225 #ifndef BDRV_LS2_DS_INT_EN
226  #define BDRV_LS2_DS_INT_EN 0
227 #endif
228 #ifndef BDRV_HS2_OC_INT_EN
229  #define BDRV_HS2_OC_INT_EN 0
230 #endif
231 #ifndef BDRV_HS2_DS_INT_EN
232  #define BDRV_HS2_DS_INT_EN 0
233 #endif
234 #ifndef BDRV_LS3_OC_INT_EN
235  #define BDRV_LS3_OC_INT_EN 0
236 #endif
237 #ifndef BDRV_LS3_DS_INT_EN
238  #define BDRV_LS3_DS_INT_EN 0
239 #endif
240 #ifndef BDRV_HS3_OC_INT_EN
241  #define BDRV_HS3_OC_INT_EN 0
242 #endif
243 #ifndef BDRV_HS3_DS_INT_EN
244  #define BDRV_HS3_DS_INT_EN 0
245 #endif
246 #ifndef BDRV_HB1_ASEQ_INT_EN
247  #define BDRV_HB1_ASEQ_INT_EN 0
248 #endif
249 #ifndef BDRV_HB2_ASEQ_INT_EN
250  #define BDRV_HB2_ASEQ_INT_EN 0
251 #endif
252 #ifndef BDRV_HB3_ASEQ_INT_EN
253  #define BDRV_HB3_ASEQ_INT_EN 0
254 #endif
255 #ifndef BDRV_SEQ_ERR_INT_EN
256  #define BDRV_SEQ_ERR_INT_EN 0
257 #endif
258 #ifndef BDRV_HB1_ACTDRV_INT_EN
259  #define BDRV_HB1_ACTDRV_INT_EN 0
260 #endif
261 #ifndef BDRV_HB2_ACTDRV_INT_EN
262  #define BDRV_HB2_ACTDRV_INT_EN 0
263 #endif
264 #ifndef BDRV_HB3_ACTDRV_INT_EN
265  #define BDRV_HB3_ACTDRV_INT_EN 0
266 #endif
267 #ifndef BDRV_VCP_LOTH2_INT_EN
268  #define BDRV_VCP_LOTH2_INT_EN 0
269 #endif
270 #ifndef CSACSC_OC_INT_EN
271  #define CSACSC_OC_INT_EN 0
272 #endif
273 #ifndef CSACSC_PARAM_INT_EN
274  #define CSACSC_PARAM_INT_EN 0
275 #endif
276 #ifndef PMU_VDDP_UVWARN_INT_EN
277  #define PMU_VDDP_UVWARN_INT_EN 0
278 #endif
279 #ifndef PMU_VDDP_OV_INT_EN
280  #define PMU_VDDP_OV_INT_EN 0
281 #endif
282 #ifndef PMU_VDDC_UVWARN_INT_EN
283  #define PMU_VDDC_UVWARN_INT_EN 0
284 #endif
285 #ifndef PMU_VDDC_OV_INT_EN
286  #define PMU_VDDC_OV_INT_EN 0
287 #endif
288 #ifndef PMU_VDDEXT_UV_INT_EN
289  #define PMU_VDDEXT_UV_INT_EN 0
290 #endif
291 #ifndef PMU_VDDEXT_OT_INT_EN
292  #define PMU_VDDEXT_OT_INT_EN 0
293 #endif
294 #ifndef ARVG_VAREF_OC_INT_EN
295  #define ARVG_VAREF_OC_INT_EN 0
296 #endif
297 #ifndef CCU7_T12_OM_INT_EN
298  #define CCU7_T12_OM_INT_EN 0
299 #endif
300 #ifndef CCU7_T12_PM_INT_EN
301  #define CCU7_T12_PM_INT_EN 0
302 #endif
303 #ifndef CCU7_T13_CM_INT_EN
304  #define CCU7_T13_CM_INT_EN 0
305 #endif
306 #ifndef CCU7_T13_PM_INT_EN
307  #define CCU7_T13_PM_INT_EN 0
308 #endif
309 #ifndef CCU7_T14_CM_INT_EN
310  #define CCU7_T14_CM_INT_EN 0
311 #endif
312 #ifndef CCU7_T14_PM_INT_EN
313  #define CCU7_T14_PM_INT_EN 0
314 #endif
315 #ifndef CCU7_T15_CM_INT_EN
316  #define CCU7_T15_CM_INT_EN 0
317 #endif
318 #ifndef CCU7_T15_PM_INT_EN
319  #define CCU7_T15_PM_INT_EN 0
320 #endif
321 #ifndef CCU7_T16_CM_INT_EN
322  #define CCU7_T16_CM_INT_EN 0
323 #endif
324 #ifndef CCU7_T16_PM_INT_EN
325  #define CCU7_T16_PM_INT_EN 0
326 #endif
327 #ifndef CCU7_CC70A_CM_R_INT_EN
328  #define CCU7_CC70A_CM_R_INT_EN 0
329 #endif
330 #ifndef CCU7_CC70A_CM_F_INT_EN
331  #define CCU7_CC70A_CM_F_INT_EN 0
332 #endif
333 #ifndef CCU7_CC71A_CM_R_INT_EN
334  #define CCU7_CC71A_CM_R_INT_EN 0
335 #endif
336 #ifndef CCU7_CC71A_CM_F_INT_EN
337  #define CCU7_CC71A_CM_F_INT_EN 0
338 #endif
339 #ifndef CCU7_CC71A_CM_R_INT_EN
340  #define CCU7_CC71A_CM_R_INT_EN 0
341 #endif
342 #ifndef CCU7_CC71A_CM_F_INT_EN
343  #define CCU7_CC71A_CM_F_INT_EN 0
344 #endif
345 #ifndef CCU7_C70B_CM_R_INT_EN
346  #define CCU7_C70B_CM_R_INT_EN 0
347 #endif
348 #ifndef CCU7_C70B_CM_F_INT_EN
349  #define CCU7_C70B_CM_F_INT_EN 0
350 #endif
351 #ifndef CCU7_C71B_CM_R_INT_EN
352  #define CCU7_C71B_CM_R_INT_EN 0
353 #endif
354 #ifndef CCU7_C71B_CM_F_INT_EN
355  #define CCU7_C71B_CM_F_INT_EN 0
356 #endif
357 #ifndef CCU7_C72B_CM_R_INT_EN
358  #define CCU7_C72B_CM_R_INT_EN 0
359 #endif
360 #ifndef CCU7_C72B_CM_F_INT_EN
361  #define CCU7_C72B_CM_F_INT_EN 0
362 #endif
363 #ifndef CCU7_TRAP_INT_EN
364  #define CCU7_TRAP_INT_EN 0
365 #endif
366 #ifndef CCU7_CORRECT_HALL_INT_EN
367  #define CCU7_CORRECT_HALL_INT_EN 0
368 #endif
369 #ifndef CCU7_WRONG_HALL_INT_EN
370  #define CCU7_WRONG_HALL_INT_EN 0
371 #endif
372 #ifndef CCU7_MCM_STR_INT_EN
373  #define CCU7_MCM_STR_INT_EN 0
374 #endif
375 #ifndef CCU7_LI_INT_EN
376  #define CCU7_LI_INT_EN 0
377 #endif
378 #ifndef MEMCTRL_NVM0_OP_COMPLETE_INT_EN
379  #define MEMCTRL_NVM0_OP_COMPLETE_INT_EN 0
380 #endif
381 #ifndef MEMCTRL_NVM1_OP_COMPLETE_INT_EN
382  #define MEMCTRL_NVM1_OP_COMPLETE_INT_EN 0
383 #endif
384 #ifndef GPT12_GPT1T2_INT_EN
385  #define GPT12_GPT1T2_INT_EN 0
386 #endif
387 #ifndef GPT12_GPT1T3_INT_EN
388  #define GPT12_GPT1T3_INT_EN 0
389 #endif
390 #ifndef GPT12_GPT1T4_INT_EN
391  #define GPT12_GPT1T4_INT_EN 0
392 #endif
393 #ifndef GPT12_GPT2T5_INT_EN
394  #define GPT12_GPT2T5_INT_EN 0
395 #endif
396 #ifndef GPT12_GPT2T6_INT_EN
397  #define GPT12_GPT2T6_INT_EN 0
398 #endif
399 #ifndef GPT12_GPT2CAPREL_INT_EN
400  #define GPT12_GPT2CAPREL_INT_EN 0
401 #endif
402 #ifndef ADC2_CH0_INT_EN
403  #define ADC2_CH0_INT_EN 0
404 #endif
405 #ifndef ADC2_CH1_INT_EN
406  #define ADC2_CH1_INT_EN 0
407 #endif
408 #ifndef ADC2_CH2_INT_EN
409  #define ADC2_CH2_INT_EN 0
410 #endif
411 #ifndef ADC2_CH3_INT_EN
412  #define ADC2_CH3_INT_EN 0
413 #endif
414 #ifndef ADC2_CH4_INT_EN
415  #define ADC2_CH4_INT_EN 0
416 #endif
417 #ifndef ADC2_CH5_INT_EN
418  #define ADC2_CH5_INT_EN 0
419 #endif
420 #ifndef ADC2_CH6_INT_EN
421  #define ADC2_CH6_INT_EN 0
422 #endif
423 #ifndef ADC2_CH7_INT_EN
424  #define ADC2_CH7_INT_EN 0
425 #endif
426 #ifndef ADC2_CH8_INT_EN
427  #define ADC2_CH8_INT_EN 0
428 #endif
429 #ifndef ADC2_CH9_INT_EN
430  #define ADC2_CH9_INT_EN 0
431 #endif
432 #ifndef ADC2_CH10_INT_EN
433  #define ADC2_CH10_INT_EN 0
434 #endif
435 #ifndef ADC2_CH11_INT_EN
436  #define ADC2_CH11_INT_EN 0
437 #endif
438 #ifndef ADC2_CH12_INT_EN
439  #define ADC2_CH12_INT_EN 0
440 #endif
441 #ifndef ADC2_CH13_INT_EN
442  #define ADC2_CH13_INT_EN 0
443 #endif
444 #ifndef ADC2_CH14_INT_EN
445  #define ADC2_CH14_INT_EN 0
446 #endif
447 #ifndef ADC2_SQ0_INT_EN
448  #define ADC2_SQ0_INT_EN 0
449 #endif
450 #ifndef ADC2_SQ1_INT_EN
451  #define ADC2_SQ1_INT_EN 0
452 #endif
453 #ifndef ADC2_SQ2_INT_EN
454  #define ADC2_SQ2_INT_EN 0
455 #endif
456 #ifndef ADC2_SQ3_INT_EN
457  #define ADC2_SQ3_INT_EN 0
458 #endif
459 #ifndef ADC2_LOTH0_INT_EN
460  #define ADC2_LOTH0_INT_EN 0
461 #endif
462 #ifndef ADC2_LOTH1_INT_EN
463  #define ADC2_LOTH1_INT_EN 0
464 #endif
465 #ifndef ADC2_LOTH2_INT_EN
466  #define ADC2_LOTH2_INT_EN 0
467 #endif
468 #ifndef ADC2_LOTH3_INT_EN
469  #define ADC2_LOTH3_INT_EN 0
470 #endif
471 #ifndef ADC2_LOTH4_INT_EN
472  #define ADC2_LOTH4_INT_EN 0
473 #endif
474 #ifndef ADC2_LOTH5_INT_EN
475  #define ADC2_LOTH5_INT_EN 0
476 #endif
477 #ifndef ADC2_LOTH6_INT_EN
478  #define ADC2_LOTH6_INT_EN 0
479 #endif
480 #ifndef ADC2_LOTH7_INT_EN
481  #define ADC2_LOTH7_INT_EN 0
482 #endif
483 #ifndef ADC2_UPTH0_INT_EN
484  #define ADC2_UPTH0_INT_EN 0
485 #endif
486 #ifndef ADC2_UPTH1_INT_EN
487  #define ADC2_UPTH1_INT_EN 0
488 #endif
489 #ifndef ADC2_UPTH2_INT_EN
490  #define ADC2_UPTH2_INT_EN 0
491 #endif
492 #ifndef ADC2_UPTH3_INT_EN
493  #define ADC2_UPTH3_INT_EN 0
494 #endif
495 #ifndef ADC2_UPTH4_INT_EN
496  #define ADC2_UPTH4_INT_EN 0
497 #endif
498 #ifndef ADC2_UPTH5_INT_EN
499  #define ADC2_UPTH5_INT_EN 0
500 #endif
501 #ifndef ADC2_UPTH6_INT_EN
502  #define ADC2_UPTH6_INT_EN 0
503 #endif
504 #ifndef ADC2_UPTH7_INT_EN
505  #define ADC2_UPTH7_INT_EN 0
506 #endif
507 #ifndef MON_MON1_R_INT_EN
508  #define MON_MON1_R_INT_EN 0
509 #endif
510 #ifndef MON_MON1_F_INT_EN
511  #define MON_MON1_F_INT_EN 0
512 #endif
513 #ifndef MON_MON2_R_INT_EN
514  #define MON_MON2_R_INT_EN 0
515 #endif
516 #ifndef MON_MON2_F_INT_EN
517  #define MON_MON2_F_INT_EN 0
518 #endif
519 #ifndef MON_MON3_R_INT_EN
520  #define MON_MON3_R_INT_EN 0
521 #endif
522 #ifndef MON_MON3_F_INT_EN
523  #define MON_MON3_F_INT_EN 0
524 #endif
525 #ifndef ADC1_CH0_INT_EN
526  #define ADC1_CH0_INT_EN 0
527 #endif
528 #ifndef ADC1_CH1_INT_EN
529  #define ADC1_CH1_INT_EN 0
530 #endif
531 #ifndef ADC1_CH2_INT_EN
532  #define ADC1_CH2_INT_EN 0
533 #endif
534 #ifndef ADC1_CH3_INT_EN
535  #define ADC1_CH3_INT_EN 0
536 #endif
537 #ifndef ADC1_CH4_INT_EN
538  #define ADC1_CH4_INT_EN 0
539 #endif
540 #ifndef ADC1_CH5_INT_EN
541  #define ADC1_CH5_INT_EN 0
542 #endif
543 #ifndef ADC1_CH6_INT_EN
544  #define ADC1_CH6_INT_EN 0
545 #endif
546 #ifndef ADC1_CH7_INT_EN
547  #define ADC1_CH7_INT_EN 0
548 #endif
549 #ifndef ADC1_CH8_INT_EN
550  #define ADC1_CH8_INT_EN 0
551 #endif
552 #ifndef ADC1_CH9_INT_EN
553  #define ADC1_CH9_INT_EN 0
554 #endif
555 #ifndef ADC1_CH10_INT_EN
556  #define ADC1_CH10_INT_EN 0
557 #endif
558 #ifndef ADC1_CH11_INT_EN
559  #define ADC1_CH11_INT_EN 0
560 #endif
561 #ifndef ADC1_CH12_INT_EN
562  #define ADC1_CH12_INT_EN 0
563 #endif
564 #ifndef ADC1_CH13_INT_EN
565  #define ADC1_CH13_INT_EN 0
566 #endif
567 #ifndef ADC1_CH14_INT_EN
568  #define ADC1_CH14_INT_EN 0
569 #endif
570 #ifndef ADC1_CH15_INT_EN
571  #define ADC1_CH15_INT_EN 0
572 #endif
573 #ifndef ADC1_CH16_INT_EN
574  #define ADC1_CH16_INT_EN 0
575 #endif
576 #ifndef ADC1_CH17_INT_EN
577  #define ADC1_CH17_INT_EN 0
578 #endif
579 #ifndef ADC1_CH18_INT_EN
580  #define ADC1_CH18_INT_EN 0
581 #endif
582 #ifndef ADC1_CH19_INT_EN
583  #define ADC1_CH19_INT_EN 0
584 #endif
585 #ifndef ADC1_SQ0_INT_EN
586  #define ADC1_SQ0_INT_EN 0
587 #endif
588 #ifndef ADC1_SQ1_INT_EN
589  #define ADC1_SQ1_INT_EN 0
590 #endif
591 #ifndef ADC1_SQ2_INT_EN
592  #define ADC1_SQ2_INT_EN 0
593 #endif
594 #ifndef ADC1_SQ3_INT_EN
595  #define ADC1_SQ3_INT_EN 0
596 #endif
597 #ifndef ADC1_LOTH0_INT_EN
598  #define ADC1_LOTH0_INT_EN 0
599 #endif
600 #ifndef ADC1_LOTH1_INT_EN
601  #define ADC1_LOTH1_INT_EN 0
602 #endif
603 #ifndef ADC1_LOTH2_INT_EN
604  #define ADC1_LOTH2_INT_EN 0
605 #endif
606 #ifndef ADC1_LOTH3_INT_EN
607  #define ADC1_LOTH3_INT_EN 0
608 #endif
609 #ifndef ADC1_UPTH0_INT_EN
610  #define ADC1_UPTH0_INT_EN 0
611 #endif
612 #ifndef ADC1_UPTH1_INT_EN
613  #define ADC1_UPTH1_INT_EN 0
614 #endif
615 #ifndef ADC1_UPTH2_INT_EN
616  #define ADC1_UPTH2_INT_EN 0
617 #endif
618 #ifndef ADC1_UPTH3_INT_EN
619  #define ADC1_UPTH3_INT_EN 0
620 #endif
621 #ifndef ADC1_COLL0_INT_EN
622  #define ADC1_COLL0_INT_EN 0
623 #endif
624 #ifndef ADC1_COLL1_INT_EN
625  #define ADC1_COLL1_INT_EN 0
626 #endif
627 #ifndef ADC1_COLL2_INT_EN
628  #define ADC1_COLL2_INT_EN 0
629 #endif
630 #ifndef ADC1_COLL3_INT_EN
631  #define ADC1_COLL3_INT_EN 0
632 #endif
633 #ifndef ADC1_WFR0_INT_EN
634  #define ADC1_WFR0_INT_EN 0
635 #endif
636 #ifndef ADC1_WFR1_INT_EN
637  #define ADC1_WFR1_INT_EN 0
638 #endif
639 #ifndef ADC1_WFR2_INT_EN
640  #define ADC1_WFR2_INT_EN 0
641 #endif
642 #ifndef ADC1_WFR3_INT_EN
643  #define ADC1_WFR3_INT_EN 0
644 #endif
645 #ifndef BDRV_PH1_ZC_RISE_INT_EN
646  #define BDRV_PH1_ZC_RISE_INT_EN 0
647 #endif
648 #ifndef BDRV_PH1_ZC_FALL_INT_EN
649  #define BDRV_PH1_ZC_FALL_INT_EN 0
650 #endif
651 #ifndef BDRV_PH2_ZC_RISE_INT_EN
652  #define BDRV_PH2_ZC_RISE_INT_EN 0
653 #endif
654 #ifndef BDRV_PH2_ZC_FALL_INT_EN
655  #define BDRV_PH2_ZC_FALL_INT_EN 0
656 #endif
657 #ifndef BDRV_PH3_ZC_RISE_INT_EN
658  #define BDRV_PH3_ZC_RISE_INT_EN 0
659 #endif
660 #ifndef BDRV_PH3_ZC_FALL_INT_EN
661  #define BDRV_PH3_ZC_FALL_INT_EN 0
662 #endif
663 #ifndef SDADC_RES0_INT_EN
664  #define SDADC_RES0_INT_EN 0
665 #endif
666 #ifndef SDADC_CMP0_UP_INT_EN
667  #define SDADC_CMP0_UP_INT_EN 0
668 #endif
669 #ifndef SDADC_CMP0_LO_INT_EN
670  #define SDADC_CMP0_LO_INT_EN 0
671 #endif
672 #ifndef SDADC_RES1_INT_EN
673  #define SDADC_RES1_INT_EN 0
674 #endif
675 #ifndef SDADC_CMP1_UP_INT_EN
676  #define SDADC_CMP1_UP_INT_EN 0
677 #endif
678 #ifndef SDADC_CMP1_LO_INT_EN
679  #define SDADC_CMP1_LO_INT_EN 0
680 #endif
681 #ifndef SCU_EXTINT0_RISING_INT_EN
682  #define SCU_EXTINT0_RISING_INT_EN 0
683 #endif
684 #ifndef SCU_EXTINT0_FALLING_INT_EN
685  #define SCU_EXTINT0_FALLING_INT_EN 0
686 #endif
687 #ifndef SCU_EXTINT1_RISING_INT_EN
688  #define SCU_EXTINT1_RISING_INT_EN 0
689 #endif
690 #ifndef SCU_EXTINT1_FALLING_INT_EN
691  #define SCU_EXTINT1_FALLING_INT_EN 0
692 #endif
693 #ifndef SCU_EXTINT2_RISING_INT_EN
694  #define SCU_EXTINT2_RISING_INT_EN 0
695 #endif
696 #ifndef SCU_EXTINT2_FALLING_INT_EN
697  #define SCU_EXTINT2_FALLING_INT_EN 0
698 #endif
699 #ifndef SCU_EXTINT3_RISING_INT_EN
700  #define SCU_EXTINT3_RISING_INT_EN 0
701 #endif
702 #ifndef SCU_EXTINT3_FALLING_INT_EN
703  #define SCU_EXTINT3_FALLING_INT_EN 0
704 #endif
705 #ifndef UART0_TI_INT_EN
706  #define UART0_TI_INT_EN 0
707 #endif
708 #ifndef UART0_RI_INT_EN
709  #define UART0_RI_INT_EN 0
710 #endif
711 #ifndef UART0_EOS_INT_EN
712  #define UART0_EOS_INT_EN 0
713 #endif
714 #ifndef UART0_SYNCERR_INT_EN
715  #define UART0_SYNCERR_INT_EN 0
716 #endif
717 #ifndef UART1_TI_INT_EN
718  #define UART1_TI_INT_EN 0
719 #endif
720 #ifndef UART1_RI_INT_EN
721  #define UART1_RI_INT_EN 0
722 #endif
723 #ifndef UART1_EOS_INT_EN
724  #define UART1_EOS_INT_EN 0
725 #endif
726 #ifndef UART1_SYNCERR_INT_EN
727  #define UART1_SYNCERR_INT_EN 0
728 #endif
729 #ifndef SSC0_TI_INT_EN
730  #define SSC0_TI_INT_EN 0
731 #endif
732 #ifndef SSC0_RI_INT_EN
733  #define SSC0_RI_INT_EN 0
734 #endif
735 #ifndef SSC0_ERR_INT_EN
736  #define SSC0_ERR_INT_EN 0
737 #endif
738 #ifndef SSC0_ERR_INT_EN
739  #define SSC0_ERR_INT_EN 0
740 #endif
741 #ifndef SSC0_ERR_INT_EN
742  #define SSC0_ERR_INT_EN 0
743 #endif
744 #ifndef SSC0_ERR_INT_EN
745  #define SSC0_ERR_INT_EN 0
746 #endif
747 #ifndef SSC1_TI_INT_EN
748  #define SSC1_TI_INT_EN 0
749 #endif
750 #ifndef SSC1_RI_INT_EN
751  #define SSC1_RI_INT_EN 0
752 #endif
753 #ifndef SSC1_ERR_INT_EN
754  #define SSC1_ERR_INT_EN 0
755 #endif
756 #ifndef SSC1_ERR_INT_EN
757  #define SSC1_ERR_INT_EN 0
758 #endif
759 #ifndef SSC1_ERR_INT_EN
760  #define SSC1_ERR_INT_EN 0
761 #endif
762 #ifndef SSC1_ERR_INT_EN
763  #define SSC1_ERR_INT_EN 0
764 #endif
765 #ifndef DMA_CH0_INT_EN
766  #define DMA_CH0_INT_EN 0
767 #endif
768 #ifndef DMA_CH1_INT_EN
769  #define DMA_CH1_INT_EN 0
770 #endif
771 #ifndef DMA_CH2_INT_EN
772  #define DMA_CH2_INT_EN 0
773 #endif
774 #ifndef DMA_CH3_INT_EN
775  #define DMA_CH3_INT_EN 0
776 #endif
777 #ifndef DMA_CH4_INT_EN
778  #define DMA_CH4_INT_EN 0
779 #endif
780 #ifndef DMA_CH5_INT_EN
781  #define DMA_CH5_INT_EN 0
782 #endif
783 #ifndef DMA_CH6_INT_EN
784  #define DMA_CH6_INT_EN 0
785 #endif
786 #ifndef DMA_CH7_INT_EN
787  #define DMA_CH7_INT_EN 0
788 #endif
789 #ifndef DMA_ERROR_INT_EN
790  #define DMA_ERROR_INT_EN 0
791 #endif
792 #ifndef T20_EXF2_INT_EN
793  #define T20_EXF2_INT_EN 0
794 #endif
795 #ifndef T20_TF2_INT_EN
796  #define T20_TF2_INT_EN 0
797 #endif
798 #ifndef T21_EXF2_INT_EN
799  #define T21_EXF2_INT_EN 0
800 #endif
801 #ifndef T21_TF2_INT_EN
802  #define T21_TF2_INT_EN 0
803 #endif
804 
805 
806 
807 /*******************************************************************************
808 ** Global Variable Declarations **
809 *******************************************************************************/
810 
811 /* global counter variable for ms, can count ~1.5 months, requirement EMPS-SHRQ-66 */
812 extern volatile uint32 u32_globTimestamp_ms;
813 
814 #if (NVIC_IRQ0_HANDLER_INT_CHECK == 1)
815  extern uint8 u8_interrupt_cnt_irq0;
816 #endif
817 #if (NVIC_IRQ1_HANDLER_INT_CHECK == 1)
818  extern uint8 u8_interrupt_cnt_irq1;
819 #endif
820 #if (NVIC_IRQ2_HANDLER_INT_CHECK == 1)
821  extern uint8 u8_interrupt_cnt_irq2;
822 #endif
823 #if (NVIC_IRQ3_HANDLER_INT_CHECK == 1)
824  extern uint8 u8_interrupt_cnt_irq3;
825 #endif
826 #if (NVIC_IRQ4_HANDLER_INT_CHECK == 1)
827  extern uint8 u8_interrupt_cnt_irq4;
828 #endif
829 #if (NVIC_IRQ5_HANDLER_INT_CHECK == 1)
830  extern uint8 u8_interrupt_cnt_irq5;
831 #endif
832 #if (NVIC_IRQ6_HANDLER_INT_CHECK == 1)
833  extern uint8 u8_interrupt_cnt_irq6;
834 #endif
835 #if (NVIC_IRQ7_HANDLER_INT_CHECK == 1)
836  extern uint8 u8_interrupt_cnt_irq7;
837 #endif
838 #if (NVIC_IRQ8_HANDLER_INT_CHECK == 1)
839  extern uint8 u8_interrupt_cnt_irq8;
840 #endif
841 #if (NVIC_IRQ10_HANDLER_INT_CHECK == 1)
842  extern uint8 u8_interrupt_cnt_irq10;
843 #endif
844 #if (NVIC_IRQ11_HANDLER_INT_CHECK == 1)
845  extern uint8 u8_interrupt_cnt_irq11;
846 #endif
847 #if (NVIC_IRQ12_HANDLER_INT_CHECK == 1)
848  extern uint8 u8_interrupt_cnt_irq12;
849 #endif
850 #if (NVIC_IRQ13_HANDLER_INT_CHECK == 1)
851  extern uint8 u8_interrupt_cnt_irq13;
852 #endif
853 #if (NVIC_IRQ14_HANDLER_INT_CHECK == 1)
854  extern uint8 u8_interrupt_cnt_irq14;
855 #endif
856 #if (NVIC_IRQ15_HANDLER_INT_CHECK == 1)
857  extern uint8 u8_interrupt_cnt_irq15;
858 #endif
859 #if (NVIC_IRQ16_HANDLER_INT_CHECK == 1)
860  extern uint8 u8_interrupt_cnt_irq16;
861 #endif
862 #if (NVIC_IRQ17_HANDLER_INT_CHECK == 1)
863  extern uint8 u8_interrupt_cnt_irq17;
864 #endif
865 #if (NVIC_IRQ18_HANDLER_INT_CHECK == 1)
866  extern uint8 u8_interrupt_cnt_irq18;
867 #endif
868 #if (NVIC_IRQ19_HANDLER_INT_CHECK == 1)
869  extern uint8 u8_interrupt_cnt_irq19;
870 #endif
871 #if (NVIC_IRQ20_HANDLER_INT_CHECK == 1)
872  extern uint8 u8_interrupt_cnt_irq20;
873 #endif
874 #if (NVIC_IRQ21_HANDLER_INT_CHECK == 1)
875  extern uint8 u8_interrupt_cnt_irq21;
876 #endif
877 #if (NVIC_IRQ22_HANDLER_INT_CHECK == 1)
878  extern uint8 u8_interrupt_cnt_irq22;
879 #endif
880 #if (NVIC_IRQ23_HANDLER_INT_CHECK == 1)
881  extern uint8 u8_interrupt_cnt_irq23;
882 #endif
883 #if (NVIC_IRQ24_HANDLER_INT_CHECK == 1)
884  extern uint8 u8_interrupt_cnt_irq24;
885 #endif
886 #if (NVIC_IRQ25_HANDLER_INT_CHECK == 1)
887  extern uint8 u8_interrupt_cnt_irq25;
888 #endif
889 #if (NVIC_IRQ26_HANDLER_INT_CHECK == 1)
890  extern uint8 u8_interrupt_cnt_irq26;
891 #endif
892 #if (NVIC_IRQ27_HANDLER_INT_CHECK == 1)
893  extern uint8 u8_interrupt_cnt_irq27;
894 #endif
895 #if (NVIC_IRQ28_HANDLER_INT_CHECK == 1)
896  extern uint8 u8_interrupt_cnt_irq28;
897 #endif
898 #if (NVIC_IRQ29_HANDLER_INT_CHECK == 1)
899  extern uint8 u8_interrupt_cnt_irq29;
900 #endif
901 #if (NVIC_IRQ30_HANDLER_INT_CHECK == 1)
902  extern uint8 u8_interrupt_cnt_irq30;
903 #endif
904 #if (NVIC_IRQ9_HANDLER_INT_CHECK == 1)
905  extern uint8 u8_interrupt_cnt_irq9;
906 #endif
907 #if (NVIC_IRQ31_HANDLER_INT_CHECK == 1)
908  extern uint8 u8_interrupt_cnt_irq31;
909 #endif
910 
911 /*******************************************************************************
912 ** Global Function Declarations **
913 *******************************************************************************/
915 void HardFault_Handler(void);
916 void MemManage_Handler(void);
917 void BusFault_Handler(void);
918 void UsageFault_Handler(void);
919 void NMI_Handler(void);
920 void SysTick_Handler(void);
921 void PendSV_Handler(void);
922 void NVIC_IRQ0_Handler(void);
923 void NVIC_IRQ1_Handler(void);
924 void NVIC_IRQ2_Handler(void);
925 void NVIC_IRQ3_Handler(void);
926 void NVIC_IRQ4_Handler(void);
927 void NVIC_IRQ5_Handler(void);
928 void NVIC_IRQ6_Handler(void);
929 void NVIC_IRQ7_Handler(void);
930 void NVIC_IRQ8_Handler(void);
931 void NVIC_IRQ9_Handler(void);
932 void NVIC_IRQ10_Handler(void);
933 void NVIC_IRQ11_Handler(void);
934 void NVIC_IRQ12_Handler(void);
935 void NVIC_IRQ13_Handler(void);
936 void NVIC_IRQ14_Handler(void);
937 void NVIC_IRQ15_Handler(void);
938 void NVIC_IRQ16_Handler(void);
939 void NVIC_IRQ17_Handler(void);
940 void NVIC_IRQ18_Handler(void);
941 void NVIC_IRQ19_Handler(void);
942 void NVIC_IRQ20_Handler(void);
943 void NVIC_IRQ21_Handler(void);
944 void NVIC_IRQ22_Handler(void);
945 void NVIC_IRQ23_Handler(void);
946 void NVIC_IRQ24_Handler(void);
947 void NVIC_IRQ25_Handler(void);
948 void NVIC_IRQ26_Handler(void);
949 void NVIC_IRQ27_Handler(void);
950 void NVIC_IRQ28_Handler(void);
951 void NVIC_IRQ29_Handler(void);
952 void NVIC_IRQ30_Handler(void);
953 void NVIC_IRQ31_Handler(void);
954 extern void CPU_HARDFAULT_CALLBACK(void);
955 extern void CPU_MEMMANAGE_CALLBACK(void);
956 extern void CPU_BUSFAULT_CALLBACK(void);
957 extern void CPU_USAGEFAULT_CALLBACK(void);
972 extern void ADC2_UPTH0_CALLBACK(void);
973 extern void ADC2_LOTH0_CALLBACK(void);
974 extern void ADC2_LOTH1_CALLBACK(void);
975 extern void ADC2_UPTH2_CALLBACK(void);
976 extern void ADC2_LOTH2_CALLBACK(void);
977 extern void ADC2_LOTH3_CALLBACK(void);
978 extern void ADC2_UPTH4_CALLBACK(void);
979 extern void CANTRX_BUS_TO_CALLBACK(void);
980 extern void CANTRX_TXD_TO_CALLBACK(void);
981 extern void CANTRX_OT_CALLBACK(void);
982 extern void CANTRX_BUS_ACT_CALLBACK(void);
983 extern void BDRV_LS1_OC_CALLBACK(void);
984 extern void BDRV_LS1_DS_CALLBACK(void);
985 extern void BDRV_HS1_OC_CALLBACK(void);
986 extern void BDRV_HS1_DS_CALLBACK(void);
987 extern void BDRV_LS2_OC_CALLBACK(void);
988 extern void BDRV_LS2_DS_CALLBACK(void);
989 extern void BDRV_HS2_OC_CALLBACK(void);
990 extern void BDRV_HS2_DS_CALLBACK(void);
991 extern void BDRV_LS3_OC_CALLBACK(void);
992 extern void BDRV_LS3_DS_CALLBACK(void);
993 extern void BDRV_HS3_OC_CALLBACK(void);
994 extern void BDRV_HS3_DS_CALLBACK(void);
995 extern void BDRV_HB1_ASEQ_CALLBACK(void);
996 extern void BDRV_HB2_ASEQ_CALLBACK(void);
997 extern void BDRV_HB3_ASEQ_CALLBACK(void);
998 extern void BDRV_SEQ_ERR_CALLBACK(void);
999 extern void BDRV_HB1_ACTDRV_CALLBACK(void);
1000 extern void BDRV_HB2_ACTDRV_CALLBACK(void);
1001 extern void BDRV_HB3_ACTDRV_CALLBACK(void);
1002 extern void BDRV_VCP_LOTH2_CALLBACK(void);
1003 extern void CSACSC_OC_CALLBACK(void);
1004 extern void CSACSC_PARAM_CALLBACK(void);
1005 extern void PMU_VDDP_UVWARN_CALLBACK(void);
1006 extern void PMU_VDDP_OV_CALLBACK(void);
1007 extern void PMU_VDDC_UVWARN_CALLBACK(void);
1008 extern void PMU_VDDC_OV_CALLBACK(void);
1009 extern void PMU_VDDEXT_UV_CALLBACK(void);
1010 extern void PMU_VDDEXT_OT_CALLBACK(void);
1011 extern void ARVG_VAREF_OC_CALLBACK(void);
1012 extern void CCU7_T12_OM_CALLBACK(void);
1013 extern void CCU7_T12_PM_CALLBACK(void);
1014 extern void CCU7_T13_CM_CALLBACK(void);
1015 extern void CCU7_T13_PM_CALLBACK(void);
1016 extern void CCU7_T14_CM_CALLBACK(void);
1017 extern void CCU7_T14_PM_CALLBACK(void);
1018 extern void CCU7_T15_CM_CALLBACK(void);
1019 extern void CCU7_T15_PM_CALLBACK(void);
1020 extern void CCU7_T16_CM_CALLBACK(void);
1021 extern void CCU7_T16_PM_CALLBACK(void);
1022 extern void CCU7_CC70A_CM_R_CALLBACK(void);
1023 extern void CCU7_CC70A_CM_F_CALLBACK(void);
1024 extern void CCU7_CC71A_CM_R_CALLBACK(void);
1025 extern void CCU7_CC71A_CM_F_CALLBACK(void);
1026 extern void CCU7_CC72A_CM_R_CALLBACK(void);
1027 extern void CCU7_CC72A_CM_F_CALLBACK(void);
1028 extern void CCU7_C70B_CM_R_CALLBACK(void);
1029 extern void CCU7_C70B_CM_F_CALLBACK(void);
1030 extern void CCU7_C71B_CM_R_CALLBACK(void);
1031 extern void CCU7_C71B_CM_F_CALLBACK(void);
1032 extern void CCU7_C72B_CM_R_CALLBACK(void);
1033 extern void CCU7_C72B_CM_F_CALLBACK(void);
1034 extern void CCU7_TRAP_CALLBACK(void);
1035 extern void CCU7_CORRECT_HALL_CALLBACK(void);
1036 extern void CCU7_WRONG_HALL_CALLBACK(void);
1037 extern void CCU7_MCM_STR_CALLBACK(void);
1038 extern void CCU7_LI_CALLBACK(void);
1041 extern void GPT12_GPT1T2_CALLBACK(void);
1042 extern void GPT12_GPT1T3_CALLBACK(void);
1043 extern void GPT12_GPT1T4_CALLBACK(void);
1044 extern void GPT12_GPT2T5_CALLBACK(void);
1045 extern void GPT12_GPT2T6_CALLBACK(void);
1046 extern void GPT12_GPT2CAPREL_CALLBACK(void);
1047 extern void ADC2_CH0_CALLBACK(void);
1048 extern void ADC2_CH1_CALLBACK(void);
1049 extern void ADC2_CH2_CALLBACK(void);
1050 extern void ADC2_CH3_CALLBACK(void);
1051 extern void ADC2_CH4_CALLBACK(void);
1052 extern void ADC2_CH5_CALLBACK(void);
1053 extern void ADC2_CH6_CALLBACK(void);
1054 extern void ADC2_CH7_CALLBACK(void);
1055 extern void ADC2_CH8_CALLBACK(void);
1056 extern void ADC2_CH9_CALLBACK(void);
1057 extern void ADC2_CH10_CALLBACK(void);
1058 extern void ADC2_CH11_CALLBACK(void);
1059 extern void ADC2_CH12_CALLBACK(void);
1060 extern void ADC2_CH13_CALLBACK(void);
1061 extern void ADC2_CH14_CALLBACK(void);
1062 extern void ADC2_SQ0_CALLBACK(void);
1063 extern void ADC2_SQ1_CALLBACK(void);
1064 extern void ADC2_SQ2_CALLBACK(void);
1065 extern void ADC2_SQ3_CALLBACK(void);
1066 extern void ADC2_LOTH0_CALLBACK(void);
1067 extern void ADC2_LOTH1_CALLBACK(void);
1068 extern void ADC2_LOTH2_CALLBACK(void);
1069 extern void ADC2_LOTH3_CALLBACK(void);
1070 extern void ADC2_LOTH4_CALLBACK(void);
1071 extern void ADC2_LOTH5_CALLBACK(void);
1072 extern void ADC2_LOTH6_CALLBACK(void);
1073 extern void ADC2_LOTH7_CALLBACK(void);
1074 extern void ADC2_UPTH0_CALLBACK(void);
1075 extern void ADC2_UPTH1_CALLBACK(void);
1076 extern void ADC2_UPTH2_CALLBACK(void);
1077 extern void ADC2_UPTH3_CALLBACK(void);
1078 extern void ADC2_UPTH4_CALLBACK(void);
1079 extern void ADC2_UPTH5_CALLBACK(void);
1080 extern void ADC2_UPTH6_CALLBACK(void);
1081 extern void ADC2_UPTH7_CALLBACK(void);
1082 extern void MON_MON1_R_CALLBACK(void);
1083 extern void MON_MON1_F_CALLBACK(void);
1084 extern void MON_MON2_R_CALLBACK(void);
1085 extern void MON_MON2_F_CALLBACK(void);
1086 extern void MON_MON3_R_CALLBACK(void);
1087 extern void MON_MON3_F_CALLBACK(void);
1088 extern void ADC1_CH0_CALLBACK(void);
1089 extern void ADC1_CH1_CALLBACK(void);
1090 extern void ADC1_CH2_CALLBACK(void);
1091 extern void ADC1_CH3_CALLBACK(void);
1092 extern void ADC1_CH4_CALLBACK(void);
1093 extern void ADC1_CH5_CALLBACK(void);
1094 extern void ADC1_CH6_CALLBACK(void);
1095 extern void ADC1_CH7_CALLBACK(void);
1096 extern void ADC1_CH8_CALLBACK(void);
1097 extern void ADC1_CH9_CALLBACK(void);
1098 extern void ADC1_CH10_CALLBACK(void);
1099 extern void ADC1_CH11_CALLBACK(void);
1100 extern void ADC1_CH12_CALLBACK(void);
1101 extern void ADC1_CH13_CALLBACK(void);
1102 extern void ADC1_CH14_CALLBACK(void);
1103 extern void ADC1_CH15_CALLBACK(void);
1104 extern void ADC1_CH16_CALLBACK(void);
1105 extern void ADC1_CH17_CALLBACK(void);
1106 extern void ADC1_CH18_CALLBACK(void);
1107 extern void ADC1_CH19_CALLBACK(void);
1108 extern void ADC1_SQ0_CALLBACK(void);
1109 extern void ADC1_SQ1_CALLBACK(void);
1110 extern void ADC1_SQ2_CALLBACK(void);
1111 extern void ADC1_SQ3_CALLBACK(void);
1112 extern void ADC1_LOTH0_CALLBACK(void);
1113 extern void ADC1_LOTH1_CALLBACK(void);
1114 extern void ADC1_LOTH2_CALLBACK(void);
1115 extern void ADC1_LOTH3_CALLBACK(void);
1116 extern void ADC1_UPTH0_CALLBACK(void);
1117 extern void ADC1_UPTH1_CALLBACK(void);
1118 extern void ADC1_UPTH2_CALLBACK(void);
1119 extern void ADC1_UPTH3_CALLBACK(void);
1120 extern void ADC1_COLL0_CALLBACK(void);
1121 extern void ADC1_COLL1_CALLBACK(void);
1122 extern void ADC1_COLL2_CALLBACK(void);
1123 extern void ADC1_COLL3_CALLBACK(void);
1124 extern void ADC1_WFR0_CALLBACK(void);
1125 extern void ADC1_WFR1_CALLBACK(void);
1126 extern void ADC1_WFR2_CALLBACK(void);
1127 extern void ADC1_WFR3_CALLBACK(void);
1128 extern void BDRV_PH1_ZC_RISE_CALLBACK(void);
1129 extern void BDRV_PH1_ZC_FALL_CALLBACK(void);
1130 extern void BDRV_PH2_ZC_RISE_CALLBACK(void);
1131 extern void BDRV_PH2_ZC_FALL_CALLBACK(void);
1132 extern void BDRV_PH3_ZC_RISE_CALLBACK(void);
1133 extern void BDRV_PH3_ZC_FALL_CALLBACK(void);
1134 extern void SDADC_RES0_CALLBACK(void);
1135 extern void SDADC_CMP0_UP_CALLBACK(void);
1136 extern void SDADC_CMP0_LO_CALLBACK(void);
1137 extern void SDADC_RES1_CALLBACK(void);
1138 extern void SDADC_CMP1_UP_CALLBACK(void);
1139 extern void SDADC_CMP1_LO_CALLBACK(void);
1148 extern void UART0_TI_CALLBACK(void);
1149 extern void UART0_RI_CALLBACK(void);
1150 extern void UART0_EOS_CALLBACK(void);
1151 extern void UART0_SYNCERR_CALLBACK(void);
1152 extern void UART1_TI_CALLBACK(void);
1153 extern void UART1_RI_CALLBACK(void);
1154 extern void UART1_EOS_CALLBACK(void);
1155 extern void UART1_SYNCERR_CALLBACK(void);
1156 extern void SSC0_TI_CALLBACK(void);
1157 extern void SSC0_RI_CALLBACK(void);
1158 extern void SSC0_TEI_CALLBACK(void);
1159 extern void SSC0_REI_CALLBACK(void);
1160 extern void SSC0_PEI_CALLBACK(void);
1161 extern void SSC0_BEI_CALLBACK(void);
1162 extern void SSC1_TI_CALLBACK(void);
1163 extern void SSC1_RI_CALLBACK(void);
1164 extern void SSC1_TEI_CALLBACK(void);
1165 extern void SSC1_REI_CALLBACK(void);
1166 extern void SSC1_PEI_CALLBACK(void);
1167 extern void SSC1_BEI_CALLBACK(void);
1170 extern void CANNODE_NODE0_LEC_CALLBACK(void);
1173 extern void CANNODE_NODE0_LLE_CALLBACK(void);
1174 extern void CANNODE_NODE0_LOE_CALLBACK(void);
1304 extern void DMA_CH0_CALLBACK(void);
1305 extern void DMA_CH1_CALLBACK(void);
1306 extern void DMA_CH2_CALLBACK(void);
1307 extern void DMA_CH3_CALLBACK(void);
1308 extern void DMA_CH4_CALLBACK(void);
1309 extern void DMA_CH5_CALLBACK(void);
1310 extern void DMA_CH6_CALLBACK(void);
1311 extern void DMA_CH7_CALLBACK(void);
1312 extern void DMA_ERROR_CALLBACK(void);
1313 extern void T20_EXF2_CALLBACK(void);
1314 extern void T20_TF2_CALLBACK(void);
1315 extern void T21_EXF2_CALLBACK(void);
1316 extern void T21_TF2_CALLBACK(void);
1317 
1318 /*******************************************************************************
1319 ** Global Function Definitions **
1320 *******************************************************************************/
1326 {
1327  return u32_globTimestamp_ms;
1328 }
1329 
1330 #endif /* _ISR_H */
1331 
Interrupt Service Routines low level access library.
void SCU_EXTINT1_RISING_CALLBACK(void)
void PMU_VDDEXT_OT_CALLBACK(void)
void MON_MON3_F_CALLBACK(void)
void CCU7_WRONG_HALL_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXPND_CALLBACK(void)
void ADC1_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG3_TXPND_CALLBACK(void)
void CPU_PENDSV_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXOVF_CALLBACK(void)
void NVIC_IRQ28_Handler(void)
Definition: startup_tle989x.c:289
void CPU_USAGEFAULT_CALLBACK(void)
void BDRV_LS2_OC_CALLBACK(void)
void DMA_CH4_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXPND_CALLBACK(void)
void BDRV_HB3_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXPND_CALLBACK(void)
void ADC1_UPTH2_CALLBACK(void)
void NVIC_IRQ3_Handler(void)
Definition: startup_tle989x.c:264
void CANNODE_NODE0_BOFF_CALLBACK(void)
void CCU7_T12_PM_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXOVF_CALLBACK(void)
void ADC1_WFR0_CALLBACK(void)
void NVIC_IRQ26_Handler(void)
Definition: startup_tle989x.c:287
void CANMSGOBJ0_MSG3_TXOVF_CALLBACK(void)
void MEMCTRL_NMICON_NMIDSEN_CALLBACK(void)
void DMA_CH6_CALLBACK(void)
void ADC1_WFR2_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXPND_CALLBACK(void)
void SSC1_BEI_CALLBACK(void)
void NVIC_IRQ21_Handler(void)
Definition: startup_tle989x.c:282
void CANMSGOBJ0_MSG4_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXOVF_CALLBACK(void)
void ADC1_CH0_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXPND_CALLBACK(void)
void ADC1_LOTH1_CALLBACK(void)
void ADC2_CH1_CALLBACK(void)
void T21_TF2_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP1EN_CALLBACK(void)
void CANNODE_NODE0_RXOK_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXPND_CALLBACK(void)
void SSC0_REI_CALLBACK(void)
void BDRV_LS2_DS_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXOVF_CALLBACK(void)
void SDADC_CMP0_UP_CALLBACK(void)
void CSACSC_OC_CALLBACK(void)
void SCU_EXTINT1_FALLING_CALLBACK(void)
void SCU_NMICON_NMIXTALEN_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXOVF_CALLBACK(void)
void NVIC_IRQ10_Handler(void)
Definition: startup_tle989x.c:271
void CANMSGOBJ0_MSG28_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXPND_CALLBACK(void)
void UsageFault_Handler(void)
UsageFault ISR.
Definition: startup_tle989x.c:249
void T21_EXF2_CALLBACK(void)
void ADC1_COLL0_CALLBACK(void)
void CCU7_C71B_CM_R_CALLBACK(void)
void PMU_VDDP_OV_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG7_RXPND_CALLBACK(void)
void NVIC_IRQ20_Handler(void)
Definition: startup_tle989x.c:281
void CANMSGOBJ0_MSG21_TXOVF_CALLBACK(void)
void UART0_RI_CALLBACK(void)
void BDRV_PH1_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXPND_CALLBACK(void)
void HardFault_Handler(void)
HardFault ISR.
Definition: startup_tle989x.c:246
void MON_MON2_F_CALLBACK(void)
void ADC1_COLL1_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXOVF_CALLBACK(void)
void SDADC_RES1_CALLBACK(void)
void SSC0_PEI_CALLBACK(void)
void CCU7_CC71A_CM_F_CALLBACK(void)
void CCU7_T12_OM_CALLBACK(void)
void BDRV_PH2_ZC_FALL_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXOVF_CALLBACK(void)
void UART0_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXPND_CALLBACK(void)
void MemManage_Handler(void)
MemManage ISR.
Definition: startup_tle989x.c:247
void SCU_EXTINT3_FALLING_CALLBACK(void)
void ADC1_UPTH1_CALLBACK(void)
void NVIC_IRQ17_Handler(void)
Definition: startup_tle989x.c:278
void NVIC_IRQ1_Handler(void)
Definition: startup_tle989x.c:262
void ADC2_SQ1_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXOVF_CALLBACK(void)
void ADC2_UPTH4_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXPND_CALLBACK(void)
void MEMCTRL_NMICON_NMIPSEN_CALLBACK(void)
void PMU_VDDC_UVWARN_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXPND_CALLBACK(void)
void MON_MON2_R_CALLBACK(void)
void NVIC_IRQ29_Handler(void)
Definition: startup_tle989x.c:290
void CANMSGOBJ0_MSG19_RXPND_CALLBACK(void)
void CCU7_CC70A_CM_F_CALLBACK(void)
void MON_MON3_R_CALLBACK(void)
void UART1_SYNCERR_CALLBACK(void)
void SCU_NMICON_NMIPLL1EN_CALLBACK(void)
void CANMSGOBJ0_MSG16_RXPND_CALLBACK(void)
void MEMCTRL_NVM1_OP_COMPLETE_CALLBACK(void)
void BDRV_HS2_DS_CALLBACK(void)
void CCU7_T15_CM_CALLBACK(void)
void MEMCTRL_NMICON_NMICDEN_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXOVF_CALLBACK(void)
void ADC1_CH7_CALLBACK(void)
void ADC1_CH17_CALLBACK(void)
void BDRV_HS2_OC_CALLBACK(void)
void SDADC_CMP1_UP_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXOVF_CALLBACK(void)
void CCU7_T14_PM_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXPND_CALLBACK(void)
void GPT12_GPT1T4_CALLBACK(void)
void ADC2_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXOVF_CALLBACK(void)
void BDRV_SEQ_ERR_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXOVF_CALLBACK(void)
void CSACSC_PARAM_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXPND_CALLBACK(void)
void CANTRX_BUS_TO_CALLBACK(void)
void CCU7_T16_CM_CALLBACK(void)
void ADC1_CH5_CALLBACK(void)
void NVIC_IRQ12_Handler(void)
Definition: startup_tle989x.c:273
void UART0_SYNCERR_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXOVF_CALLBACK(void)
void ADC1_CH16_CALLBACK(void)
void CANMSGOBJ0_MSG4_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXOVF_CALLBACK(void)
void BDRV_HS3_OC_CALLBACK(void)
void ADC1_CH19_CALLBACK(void)
void CCU7_MCM_STR_CALLBACK(void)
void UART1_TI_CALLBACK(void)
void NVIC_IRQ7_Handler(void)
Definition: startup_tle989x.c:268
void SDADC_CMP0_LO_CALLBACK(void)
void SCU_EXTINT0_FALLING_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXOVF_CALLBACK(void)
void ADC2_CH0_CALLBACK(void)
void SDADC_CMP1_LO_CALLBACK(void)
void ADC1_LOTH0_CALLBACK(void)
void ADC2_CH6_CALLBACK(void)
void UART1_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXOVF_CALLBACK(void)
void PMU_VDDC_OV_CALLBACK(void)
void PendSV_Handler(void)
PendSV ISR.
Definition: startup_tle989x.c:256
void NVIC_IRQ27_Handler(void)
Definition: startup_tle989x.c:288
void CCU7_C70B_CM_F_CALLBACK(void)
void SCU_NMICON_NMIPLL0EN_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXPND_CALLBACK(void)
void CCU7_T15_PM_CALLBACK(void)
void GPT12_GPT1T2_CALLBACK(void)
void BDRV_HS3_DS_CALLBACK(void)
void SCU_EXTINT2_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXOVF_CALLBACK(void)
void NVIC_IRQ31_Handler(void)
Definition: startup_tle989x.c:293
void NMI_Handler(void)
NMI ISR.
Definition: startup_tle989x.c:245
void DMA_CH2_CALLBACK(void)
void ADC1_CH10_CALLBACK(void)
void ADC1_CH1_CALLBACK(void)
void ADC2_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXPND_CALLBACK(void)
void BDRV_LS3_DS_CALLBACK(void)
void NVIC_IRQ9_Handler(void)
Definition: startup_tle989x.c:270
void CANMSGOBJ0_MSG19_TXPND_CALLBACK(void)
void MON_MON1_R_CALLBACK(void)
void NVIC_IRQ8_Handler(void)
Definition: startup_tle989x.c:269
void NVIC_IRQ6_Handler(void)
void CANMSGOBJ0_MSG27_RXOVF_CALLBACK(void)
void BDRV_LS1_DS_CALLBACK(void)
void BDRV_LS3_OC_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXOVF_CALLBACK(void)
void ADC2_CH5_CALLBACK(void)
void SSC0_RI_CALLBACK(void)
void CCU7_LI_CALLBACK(void)
void MEMCTRL_NMICON_NMISTOFEN_CALLBACK(void)
void DMA_CH0_CALLBACK(void)
void ADC2_LOTH7_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXPND_CALLBACK(void)
void CPU_MEMMANAGE_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXOVF_CALLBACK(void)
void GPT12_GPT2CAPREL_CALLBACK(void)
void BDRV_PH3_ZC_FALL_CALLBACK(void)
void CPU_HARDFAULT_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXPND_CALLBACK(void)
void SDADC_RES0_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM0EN_CALLBACK(void)
void ADC1_UPTH0_CALLBACK(void)
void CANMSGOBJ0_MSG21_TXPND_CALLBACK(void)
void ADC1_WFR1_CALLBACK(void)
void NVIC_IRQ13_Handler(void)
Definition: startup_tle989x.c:274
void CANMSGOBJ0_MSG16_RXOVF_CALLBACK(void)
void NVIC_IRQ16_Handler(void)
Definition: startup_tle989x.c:277
void ADC2_LOTH0_CALLBACK(void)
void SCU_EXTINT3_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXPND_CALLBACK(void)
void SSC1_PEI_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM1EN_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXOVF_CALLBACK(void)
void CCU7_T13_PM_CALLBACK(void)
void ADC1_CH13_CALLBACK(void)
void UART0_TI_CALLBACK(void)
void PMU_VDDEXT_UV_CALLBACK(void)
void BusFault_Handler(void)
BusFault ISR.
Definition: startup_tle989x.c:248
void CANMSGOBJ0_MSG28_RXPND_CALLBACK(void)
void ADC2_CH11_CALLBACK(void)
void ADC2_CH3_CALLBACK(void)
void ADC2_CH4_CALLBACK(void)
void ADC1_COLL2_CALLBACK(void)
void ADC1_UPTH3_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXPND_CALLBACK(void)
void NVIC_IRQ0_Handler(void)
Definition: startup_tle989x.c:261
void BDRV_HB1_ASEQ_CALLBACK(void)
void ADC2_UPTH6_CALLBACK(void)
void ADC2_UPTH5_CALLBACK(void)
void BDRV_PH1_ZC_FALL_CALLBACK(void)
void MEMCTRL_NVM0_OP_COMPLETE_CALLBACK(void)
void GPT12_GPT2T5_CALLBACK(void)
void ADC1_CH11_CALLBACK(void)
void ADC1_LOTH2_CALLBACK(void)
void ADC2_UPTH1_CALLBACK(void)
void MEMCTRL_NMICON_NMIWDTEN_CALLBACK(void)
void CCU7_T13_CM_CALLBACK(void)
void ADC1_CH4_CALLBACK(void)
void ADC1_LOTH3_CALLBACK(void)
void PMU_VDDP_UVWARN_CALLBACK(void)
void CCU7_T14_CM_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXOVF_CALLBACK(void)
void CCU7_T16_PM_CALLBACK(void)
void CANTRX_OT_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXPND_CALLBACK(void)
void CCU7_CC72A_CM_R_CALLBACK(void)
void BDRV_HB2_ACTDRV_CALLBACK(void)
void ADC2_CH10_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXPND_CALLBACK(void)
void NVIC_IRQ5_Handler(void)
Definition: startup_tle989x.c:266
void ADC1_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_RXPND_CALLBACK(void)
void ADC1_CH18_CALLBACK(void)
void SSC1_REI_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXOVF_CALLBACK(void)
void ADC1_CH12_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXOVF_CALLBACK(void)
void SCU_EXTINT0_RISING_CALLBACK(void)
void SSC1_TEI_CALLBACK(void)
void NVIC_IRQ24_Handler(void)
Definition: startup_tle989x.c:285
void SSC0_BEI_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXPND_CALLBACK(void)
void NVIC_IRQ18_Handler(void)
Definition: startup_tle989x.c:279
void CCU7_CC72A_CM_F_CALLBACK(void)
void T20_EXF2_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG19_TXOVF_CALLBACK(void)
void NVIC_IRQ25_Handler(void)
Definition: startup_tle989x.c:286
void NVIC_IRQ22_Handler(void)
Definition: startup_tle989x.c:283
void CANMSGOBJ0_MSG7_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXPND_CALLBACK(void)
void ADC2_UPTH2_CALLBACK(void)
void ADC2_LOTH6_CALLBACK(void)
void ADC2_UPTH3_CALLBACK(void)
void DMA_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXPND_CALLBACK(void)
void DMA_CH5_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXPND_CALLBACK(void)
void SSC1_RI_CALLBACK(void)
void SysTick_Handler(void)
SysTick ISR.
Definition: startup_tle989x.c:258
void ADC2_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXPND_CALLBACK(void)
void UART1_RI_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXPND_CALLBACK(void)
void ADC2_LOTH3_CALLBACK(void)
void DMA_CH1_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXPND_CALLBACK(void)
void CCU7_C70B_CM_R_CALLBACK(void)
void CANNODE_NODE0_LEC_CALLBACK(void)
void CANMSGOBJ0_MSG19_RXOVF_CALLBACK(void)
void CPU_SYSTICK_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXPND_CALLBACK(void)
void ADC2_CH13_CALLBACK(void)
void CANNODE_NODE0_EWRN_CALLBACK(void)
void CANNODE_NODE0_LOE_CALLBACK(void)
void NVIC_IRQ11_Handler(void)
Definition: startup_tle989x.c:272
void CANMSGOBJ0_MSG6_RXOVF_CALLBACK(void)
volatile uint32 u32_globTimestamp_ms
Definition: isr_exceptions.c:42
void ADC1_SQ2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXOVF_CALLBACK(void)
void ADC2_LOTH1_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXOVF_CALLBACK(void)
void NVIC_IRQ23_Handler(void)
Definition: startup_tle989x.c:284
void ADC1_CH15_CALLBACK(void)
void NVIC_IRQ19_Handler(void)
Definition: startup_tle989x.c:280
void ADC2_SQ3_CALLBACK(void)
void ADC1_CH8_CALLBACK(void)
void ADC2_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXPND_CALLBACK(void)
void SCU_EXTINT2_FALLING_CALLBACK(void)
void CCU7_CC70A_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXOVF_CALLBACK(void)
void NVIC_IRQ30_Handler(void)
Definition: startup_tle989x.c:291
void DMA_ERROR_CALLBACK(void)
void GPT12_GPT2T6_CALLBACK(void)
void ADC2_CH9_CALLBACK(void)
void MON_MON1_F_CALLBACK(void)
void CANMSGOBJ0_MSG6_RXPND_CALLBACK(void)
void CANNODE_NODE0_CFCOV_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXPND_CALLBACK(void)
void ADC2_CH2_CALLBACK(void)
void CCU7_C72B_CM_F_CALLBACK(void)
void SSC0_TEI_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXOVF_CALLBACK(void)
void CCU7_TRAP_CALLBACK(void)
void ADC2_SQ2_CALLBACK(void)
void SSC0_TI_CALLBACK(void)
void ADC2_CH12_CALLBACK(void)
void CCU7_CC71A_CM_R_CALLBACK(void)
void ADC1_CH3_CALLBACK(void)
void BDRV_PH3_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG8_RXPND_CALLBACK(void)
void CCU7_C71B_CM_F_CALLBACK(void)
void ARVG_VAREF_OC_CALLBACK(void)
void ADC1_COLL3_CALLBACK(void)
void ADC2_LOTH5_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXPND_CALLBACK(void)
void CANTRX_TXD_TO_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXPND_CALLBACK(void)
void NVIC_IRQ15_Handler(void)
Definition: startup_tle989x.c:276
void NVIC_IRQ2_Handler(void)
Definition: startup_tle989x.c:263
void BDRV_LS1_OC_CALLBACK(void)
void BDRV_HB1_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXOVF_CALLBACK(void)
void BDRV_HB2_ASEQ_CALLBACK(void)
void ADC1_SQ1_CALLBACK(void)
void CPU_BUSFAULT_CALLBACK(void)
void SSC1_TI_CALLBACK(void)
void DMA_CH3_CALLBACK(void)
void ADC2_CH8_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXPND_CALLBACK(void)
void T20_TF2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXPND_CALLBACK(void)
void BDRV_HS1_OC_CALLBACK(void)
void GPT12_GPT1T3_CALLBACK(void)
void BDRV_HB3_ASEQ_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXOVF_CALLBACK(void)
void CCU7_CORRECT_HALL_CALLBACK(void)
void BDRV_PH2_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXPND_CALLBACK(void)
void NVIC_IRQ14_Handler(void)
Definition: startup_tle989x.c:275
void CANMSGOBJ0_MSG4_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXPND_CALLBACK(void)
void NVIC_IRQ4_Handler(void)
Definition: startup_tle989x.c:265
void CANMSGOBJ0_MSG8_RXOVF_CALLBACK(void)
void CANNODE_NODE0_TXOK_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP0EN_CALLBACK(void)
void ADC2_LOTH4_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXOVF_CALLBACK(void)
void ADC1_WFR3_CALLBACK(void)
void ADC2_UPTH0_CALLBACK(void)
void ADC2_UPTH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXPND_CALLBACK(void)
void ADC1_CH6_CALLBACK(void)
void ADC1_CH9_CALLBACK(void)
void CANNODE_NODE0_LLE_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXOVF_CALLBACK(void)
void BDRV_VCP_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXPND_CALLBACK(void)
void BDRV_HS1_DS_CALLBACK(void)
void CCU7_C72B_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXPND_CALLBACK(void)
INLINE uint32 INT_getGlobTimestamp(void)
Get the global timestamp value.
Definition: isr.h:1325
void ADC1_CH2_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG4_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXOVF_CALLBACK(void)
void CANTRX_BUS_ACT_CALLBACK(void)
void ADC1_SQ3_CALLBACK(void)
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:167
uint8_t uint8
8 bit unsigned value
Definition: types.h:220
uint32_t uint32
32 bit unsigned value
Definition: types.h:222