Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
SCU_Type Struct Reference

Detailed Description

SCU (SCU)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SELSYS0: 2
 
      __IOM uint32_t   SELSYS1: 2
 
      uint32_t   __pad0__: 12
 
      __IOM uint32_t   SELCLKOUT: 3
 
      __IOM uint32_t   CLKOUTEN: 1
 
      uint32_t   __pad1__: 12
 
   }   bit
 
CLKSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRECPU: 3
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   PREFILT: 5
 
      __IOM uint32_t   PREMI: 3
 
      uint32_t   __pad1__: 4
 
      __IOM uint32_t   PRECAN: 3
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   PREUART: 3
 
      uint32_t   __pad3__: 1
 
      __IOM uint32_t   PRECLKOUT: 3
 
      __IOM uint32_t   DIV2CLKOUT: 1
 
      uint32_t   __pad4__: 4
 
   }   bit
 
CLKCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   UARTCLKEN: 1
 
      __IOM uint32_t   CANCLKEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
CLKEN
 
__IM uint32_t RESERVED [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   XPD: 1
 
      __IOM uint32_t   XTALHYSEN: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   XTALHYS: 2
 
      uint32_t   __pad1__: 18
 
      __IOM uint32_t   XWDGEN: 1
 
      uint32_t   __pad2__: 3
 
      __OM uint32_t   XWDGRES: 1
 
      uint32_t   __pad3__: 3
 
   }   bit
 
XTALCON
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   XTAL_FAIL_STS: 1
 
      uint32_t   __pad0__: 7
 
      __IM uint32_t   XTALFAIL: 1
 
      uint32_t   __pad1__: 23
 
   }   bit
 
XTALSTAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   XTAL_FAIL_STSCLR: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
XTALSTATC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   XTAL_FAIL_STSSET: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
XTALSTATS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_PMU: 1
 
      __IOM uint32_t   INP_BDRV_IRQ0: 1
 
      __IOM uint32_t   INP_BDRV_IRQ1: 1
 
      __IOM uint32_t   INP_CANTX: 1
 
      __IOM uint32_t   INP_ARVG: 1
 
      __IOM uint32_t   INP_CSC: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
INP0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_GPT1T2: 1
 
      __IOM uint32_t   INP_GPT1T3: 1
 
      __IOM uint32_t   INP_GPT1T4: 1
 
      __IOM uint32_t   INP_GPT2T5: 1
 
      __IOM uint32_t   INP_GPT2T6: 1
 
      __IOM uint32_t   INP_GPT2CR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
INP1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_MON1: 1
 
      __IOM uint32_t   INP_MON2: 1
 
      __IOM uint32_t   INP_MON3: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
INP2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_SDADC0: 1
 
      __IOM uint32_t   INP_SDADC1: 1
 
      __IOM uint32_t   INP_BEMF0: 1
 
      __IOM uint32_t   INP_BEMF1: 1
 
      __IOM uint32_t   INP_BEMF2: 1
 
      uint32_t   __pad0__: 27
 
   }   bit
 
INP3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_EXINT0: 1
 
      __IOM uint32_t   INP_EXINT1: 1
 
      __IOM uint32_t   INP_EXINT2: 1
 
      __IOM uint32_t   INP_EXINT3: 1
 
      uint32_t   __pad0__: 28
 
   }   bit
 
INP4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_LIN0_EOFSYN: 1
 
      __IOM uint32_t   INP_LIN0_ERRSYN: 1
 
      __IOM uint32_t   INP_LIN1_EOFSYN: 1
 
      __IOM uint32_t   INP_LIN1_ERRSYN: 1
 
      __IOM uint32_t   INP_UART0_RI: 1
 
      __IOM uint32_t   INP_UART0_TI: 1
 
      __IOM uint32_t   INP_UART1_RI: 1
 
      __IOM uint32_t   INP_UART1_TI: 1
 
      uint32_t   __pad0__: 24
 
   }   bit
 
INP5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_SSC0_RIR: 1
 
      __IOM uint32_t   INP_SSC0_TIR: 1
 
      __IOM uint32_t   INP_SSC0_EIR: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   INP_SSC1_RIR: 1
 
      __IOM uint32_t   INP_SSC1_TIR: 1
 
      __IOM uint32_t   INP_SSC1_EIR: 1
 
      uint32_t   __pad1__: 25
 
   }   bit
 
INP6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INP_DMACH0: 1
 
      __IOM uint32_t   INP_DMACH1: 1
 
      __IOM uint32_t   INP_DMACH2: 1
 
      __IOM uint32_t   INP_DMACH3: 1
 
      __IOM uint32_t   INP_DMACH4: 1
 
      __IOM uint32_t   INP_DMACH5: 1
 
      __IOM uint32_t   INP_DMACH6: 1
 
      __IOM uint32_t   INP_DMACH7: 1
 
      __IOM uint32_t   INP_DMATRERR: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
INP7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NMIXTALEN: 1
 
      __IOM uint32_t   NMIPLL0EN: 1
 
      __IOM uint32_t   NMIPLL1EN: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
NMICON
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NMIXTAL: 1
 
      __IM uint32_t   NMIPLL0: 1
 
      __IM uint32_t   NMIPLL1: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
NMISR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIXTALCLR: 1
 
      __OM uint32_t   NMIPLL0CLR: 1
 
      __OM uint32_t   NMIPLL1CLR: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
NMISRC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIXTALSET: 1
 
      __OM uint32_t   NMIPLL0SET: 1
 
      __OM uint32_t   NMIPLL1SET: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
NMISRS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MON1EN: 1
 
      __IOM uint32_t   MON2EN: 1
 
      __IOM uint32_t   MON3EN: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
MONIEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   MON1R: 1
 
      __IM uint32_t   MON1F: 1
 
      __IM uint32_t   MON2R: 1
 
      __IM uint32_t   MON2F: 1
 
      __IM uint32_t   MON3R: 1
 
      __IM uint32_t   MON3F: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MONIS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   MON1RCLR: 1
 
      __OM uint32_t   MON1FCLR: 1
 
      __OM uint32_t   MON2RCLR: 1
 
      __OM uint32_t   MON2FCLR: 1
 
      __OM uint32_t   MON3RCLR: 1
 
      __OM uint32_t   MON3FCLR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MONISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   MON1RSET: 1
 
      __OM uint32_t   MON1FSET: 1
 
      __OM uint32_t   MON2RSET: 1
 
      __OM uint32_t   MON2FSET: 1
 
      __OM uint32_t   MON3RSET: 1
 
      __OM uint32_t   MON3FSET: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MONISS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MON1IEV: 2
 
      __IOM uint32_t   MON2IEV: 2
 
      __IOM uint32_t   MON3IEV: 2
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MONCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EXTINT0EN: 1
 
      __IOM uint32_t   EXTINT1EN: 1
 
      __IOM uint32_t   EXTINT2EN: 1
 
      __IOM uint32_t   EXTINT3EN: 1
 
      uint32_t   __pad0__: 28
 
   }   bit
 
EXTIEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   EXTINT0R: 1
 
      __IM uint32_t   EXTINT0F: 1
 
      __IM uint32_t   EXTINT1R: 1
 
      __IM uint32_t   EXTINT1F: 1
 
      __IM uint32_t   EXTINT2R: 1
 
      __IM uint32_t   EXTINT2F: 1
 
      __IM uint32_t   EXTINT3R: 1
 
      __IM uint32_t   EXTINT3F: 1
 
      uint32_t   __pad0__: 24
 
   }   bit
 
EXTIS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   EXTINT0RCLR: 1
 
      __OM uint32_t   EXTINT0FCLR: 1
 
      __OM uint32_t   EXTINT1RCLR: 1
 
      __OM uint32_t   EXTINT1FCLR: 1
 
      __OM uint32_t   EXTINT2RCLR: 1
 
      __OM uint32_t   EXTINT2FCLR: 1
 
      __OM uint32_t   EXTINT3RCLR: 1
 
      __OM uint32_t   EXTINT3FCLR: 1
 
      uint32_t   __pad0__: 24
 
   }   bit
 
EXTISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   EXTINT0RSET: 1
 
      __OM uint32_t   EXTINT0FSET: 1
 
      __OM uint32_t   EXTINT1RSET: 1
 
      __OM uint32_t   EXTINT1FSET: 1
 
      __OM uint32_t   EXTINT2RSET: 1
 
      __OM uint32_t   EXTINT2FSET: 1
 
      __OM uint32_t   EXTINT3RSET: 1
 
      __OM uint32_t   EXTINT3FSET: 1
 
      uint32_t   __pad0__: 24
 
   }   bit
 
EXTISS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EXTINT0IEV: 2
 
      __IOM uint32_t   EXTINT1IEV: 2
 
      __IOM uint32_t   EXTINT2IEV: 2
 
      __IOM uint32_t   EXTINT3IEV: 2
 
      __IOM uint32_t   EXTINT0INSEL: 2
 
      __IOM uint32_t   EXTINT1INSEL: 2
 
      __IOM uint32_t   EXTINT2INSEL: 2
 
      __IOM uint32_t   EXTINT3INSEL: 2
 
      uint32_t   __pad0__: 16
 
   }   bit
 
EXTCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   GPT1T2EN: 1
 
      __IOM uint32_t   GPT1T3EN: 1
 
      __IOM uint32_t   GPT1T4EN: 1
 
      __IOM uint32_t   GPT2T5EN: 1
 
      __IOM uint32_t   GPT2T6EN: 1
 
      __IOM uint32_t   GPT2CREN: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
GPTIEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   GPT1T2: 1
 
      __IM uint32_t   GPT1T3: 1
 
      __IM uint32_t   GPT1T4: 1
 
      __IM uint32_t   GPT2T5: 1
 
      __IM uint32_t   GPT2T6: 1
 
      __IM uint32_t   GPT2CR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
GPTIS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   GPT1T2CLR: 1
 
      __OM uint32_t   GPT1T3CLR: 1
 
      __OM uint32_t   GPT1T4CLR: 1
 
      __OM uint32_t   GPT2T5CLR: 1
 
      __OM uint32_t   GPT2T6CLR: 1
 
      __OM uint32_t   GPT2CRCLR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
GPTISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   GPT1T2SET: 1
 
      __OM uint32_t   GPT1T3SET: 1
 
      __OM uint32_t   GPT1T4SET: 1
 
      __OM uint32_t   GPT2T5SET: 1
 
      __OM uint32_t   GPT2T6SET: 1
 
      __OM uint32_t   GPT2CRSET: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
GPTISS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DMACH0EN: 1
 
      __IOM uint32_t   DMACH1EN: 1
 
      __IOM uint32_t   DMACH2EN: 1
 
      __IOM uint32_t   DMACH3EN: 1
 
      __IOM uint32_t   DMACH4EN: 1
 
      __IOM uint32_t   DMACH5EN: 1
 
      __IOM uint32_t   DMACH6EN: 1
 
      __IOM uint32_t   DMACH7EN: 1
 
      __IOM uint32_t   DMATRERREN: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
DMAIEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DMACH0: 1
 
      __IM uint32_t   DMACH1: 1
 
      __IM uint32_t   DMACH2: 1
 
      __IM uint32_t   DMACH3: 1
 
      __IM uint32_t   DMACH4: 1
 
      __IM uint32_t   DMACH5: 1
 
      __IM uint32_t   DMACH6: 1
 
      __IM uint32_t   DMACH7: 1
 
      uint32_t   __pad0__: 24
 
   }   bit
 
DMAIS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DMACH0CLR: 1
 
      __OM uint32_t   DMACH1CLR: 1
 
      __OM uint32_t   DMACH2CLR: 1
 
      __OM uint32_t   DMACH3CLR: 1
 
      __OM uint32_t   DMACH4CLR: 1
 
      __OM uint32_t   DMACH5CLR: 1
 
      __OM uint32_t   DMACH6CLR: 1
 
      __OM uint32_t   DMACH7CLR: 1
 
      uint32_t   __pad0__: 24
 
   }   bit
 
DMAISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DMACH0SET: 1
 
      __OM uint32_t   DMACH1SET: 1
 
      __OM uint32_t   DMACH2SET: 1
 
      __OM uint32_t   DMACH3SET: 1
 
      __OM uint32_t   DMACH4SET: 1
 
      __OM uint32_t   DMACH5SET: 1
 
      __OM uint32_t   DMACH6SET: 1
 
      __OM uint32_t   DMACH7SET: 1
 
      uint32_t   __pad0__: 24
 
   }   bit
 
DMAISS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T12CM70: 2
 
      __IOM uint32_t   T12CM71: 2
 
      __IOM uint32_t   T12CM72: 2
 
      __IOM uint32_t   T12PM: 2
 
      __IOM uint32_t   T12ZM: 2
 
      __IOM uint32_t   T13CM: 2
 
      __IOM uint32_t   T13PM: 2
 
      __IOM uint32_t   T13ZM: 2
 
      __IOM uint32_t   T14CM: 2
 
      __IOM uint32_t   T14PM: 2
 
      __IOM uint32_t   T15CM: 2
 
      __IOM uint32_t   T15PM: 2
 
      __IOM uint32_t   T16CM: 2
 
      __IOM uint32_t   T16PM: 2
 
      __IOM uint32_t   CHE: 2
 
      uint32_t   __pad0__: 2
 
   }   bit
 
DMAP_CCU7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ADC1_RES0: 2
 
      __IOM uint32_t   ADC1_RES1: 2
 
      __IOM uint32_t   ADC1_RES2: 2
 
      __IOM uint32_t   ADC1_RES3: 2
 
      __IOM uint32_t   ADC1_RES4: 2
 
      __IOM uint32_t   ADC1_RES5: 2
 
      __IOM uint32_t   ADC1_RES6: 2
 
      __IOM uint32_t   ADC1_RES7: 2
 
      __IOM uint32_t   ADC1_SQ0: 2
 
      __IOM uint32_t   ADC1_SQ1: 2
 
      __IOM uint32_t   ADC1_CMPLO: 2
 
      __IOM uint32_t   ADC1_CMPHI: 2
 
      __IOM uint32_t   SDADC_RES0: 2
 
      __IOM uint32_t   SDADC_RES1: 2
 
      uint32_t   __pad0__: 4
 
   }   bit
 
DMAP_ADC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T2OV: 1
 
      __IOM uint32_t   T21OV: 1
 
      uint32_t   __pad0__: 6
 
      __IOM uint32_t   GPT12T2: 1
 
      __IOM uint32_t   GPT12T3: 1
 
      __IOM uint32_t   GPT12T4: 1
 
      __IOM uint32_t   GPT12T5: 1
 
      __IOM uint32_t   GPT12T6: 1
 
      __IOM uint32_t   GPT12CR: 1
 
      uint32_t   __pad1__: 18
 
   }   bit
 
DMAP_TIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SSC0_RIR: 2
 
      __IOM uint32_t   SSC0_TIR: 2
 
      __IOM uint32_t   SSC1_RIR: 2
 
      __IOM uint32_t   SSC1_TIR: 2
 
      __IOM uint32_t   UART0_RI: 2
 
      __IOM uint32_t   UART0_TI: 2
 
      __IOM uint32_t   UART1_RI: 2
 
      __IOM uint32_t   UART1_TI: 2
 
      __IOM uint32_t   CAN_IR0: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   CAN_IR1: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
DMAP_COM
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 1
 
      __OM uint32_t   SLEEP: 1
 
      __OM uint32_t   STOP: 1
 
      uint32_t   __pad1__: 29
 
   }   bit
 
PMCON0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SSC0_DIS: 1
 
      __IOM uint32_t   SSC1_DIS: 1
 
      __IOM uint32_t   T2_DIS: 1
 
      __IOM uint32_t   T21_DIS: 1
 
      __IOM uint32_t   GPT12_DIS: 1
 
      uint32_t   __pad0__: 27
 
   }   bit
 
PMCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SSC0SUS: 1
 
      __IOM uint32_t   SSC1SUS: 1
 
      __IOM uint32_t   T2SUS: 1
 
      __IOM uint32_t   T21SUS: 1
 
      __IOM uint32_t   GPT12SUS: 1
 
      __IOM uint32_t   WDTSUS: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
SUSCTR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OT_SLEEP_EN: 1
 
      uint32_t   __pad0__: 13
 
      __IOM uint32_t   OTWARN_SD_DIS: 1
 
      __IOM uint32_t   XTALWDG_SD_DIS: 1
 
      uint32_t   __pad1__: 8
 
      __IOM uint32_t   BDRV_SD_EN: 1
 
      uint32_t   __pad2__: 7
 
   }   bit
 
PCU_CTRL
 
__IM uint32_t RESERVED1 [9]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DEMEN_CH0: 1
 
      __IOM uint32_t   DEMEN_CH1: 1
 
      __IOM uint32_t   DEMEN_CH2: 1
 
      __IOM uint32_t   DEMEN_CH3: 1
 
      __IOM uint32_t   DEMEN_CH4: 1
 
      __IOM uint32_t   DEMEN_CH5: 1
 
      __IOM uint32_t   DEMEN_CH6: 1
 
      __IOM uint32_t   DEMEN_CH7: 1
 
      __IOM uint32_t   DMAREQINTEN_CH0: 1
 
      __IOM uint32_t   DMAREQINTEN_CH1: 1
 
      __IOM uint32_t   DMAREQINTEN_CH2: 1
 
      __IOM uint32_t   DMAREQINTEN_CH3: 1
 
      __IOM uint32_t   DMAREQINTEN_CH4: 1
 
      __IOM uint32_t   DMAREQINTEN_CH5: 1
 
      __IOM uint32_t   DMAREQINTEN_CH6: 1
 
      __IOM uint32_t   DMAREQINTEN_CH7: 1
 
      uint32_t   __pad0__: 16
 
   }   bit
 
DMACTRL
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LOCKUP_EN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
LOCKUPCFG
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆ __pad4__

uint32_t __pad4__

◆ ADC1_CMPHI

__IOM uint32_t ADC1_CMPHI

[23..22] DMA Channel Request Select

◆ ADC1_CMPLO

__IOM uint32_t ADC1_CMPLO

[21..20] DMA Channel Request Select

◆ ADC1_RES0

__IOM uint32_t ADC1_RES0

[1..0] DMA Channel Request Select

◆ ADC1_RES1

__IOM uint32_t ADC1_RES1

[3..2] DMA Channel Request Select

◆ ADC1_RES2

__IOM uint32_t ADC1_RES2

[5..4] DMA Channel Request Select

◆ ADC1_RES3

__IOM uint32_t ADC1_RES3

[7..6] DMA Channel Request Select

◆ ADC1_RES4

__IOM uint32_t ADC1_RES4

[9..8] DMA Channel Request Select

◆ ADC1_RES5

__IOM uint32_t ADC1_RES5

[11..10] DMA Channel Request Select

◆ ADC1_RES6

__IOM uint32_t ADC1_RES6

[13..12] DMA Channel Request Select

◆ ADC1_RES7

__IOM uint32_t ADC1_RES7

[15..14] DMA Channel Request Select

◆ ADC1_SQ0

__IOM uint32_t ADC1_SQ0

[17..16] DMA Channel Request Select

◆ ADC1_SQ1

__IOM uint32_t ADC1_SQ1

[19..18] DMA Channel Request Select

◆ BDRV_SD_EN

__IOM uint32_t BDRV_SD_EN

[24..24] BDRV Shutdown Enable

◆  [1/47]

struct { ... } bit

◆  [2/47]

struct { ... } bit

◆  [3/47]

struct { ... } bit

◆  [4/47]

struct { ... } bit

◆  [5/47]

struct { ... } bit

◆  [6/47]

struct { ... } bit

◆  [7/47]

struct { ... } bit

◆  [8/47]

struct { ... } bit

◆  [9/47]

struct { ... } bit

◆  [10/47]

struct { ... } bit

◆  [11/47]

struct { ... } bit

◆  [12/47]

struct { ... } bit

◆  [13/47]

struct { ... } bit

◆  [14/47]

struct { ... } bit

◆  [15/47]

struct { ... } bit

◆  [16/47]

struct { ... } bit

◆  [17/47]

struct { ... } bit

◆  [18/47]

struct { ... } bit

◆  [19/47]

struct { ... } bit

◆  [20/47]

struct { ... } bit

◆  [21/47]

struct { ... } bit

◆  [22/47]

struct { ... } bit

◆  [23/47]

struct { ... } bit

◆  [24/47]

struct { ... } bit

◆  [25/47]

struct { ... } bit

◆  [26/47]

struct { ... } bit

◆  [27/47]

struct { ... } bit

◆  [28/47]

struct { ... } bit

◆  [29/47]

struct { ... } bit

◆  [30/47]

struct { ... } bit

◆  [31/47]

struct { ... } bit

◆  [32/47]

struct { ... } bit

◆  [33/47]

struct { ... } bit

◆  [34/47]

struct { ... } bit

◆  [35/47]

struct { ... } bit

◆  [36/47]

struct { ... } bit

◆  [37/47]

struct { ... } bit

◆  [38/47]

struct { ... } bit

◆  [39/47]

struct { ... } bit

◆  [40/47]

struct { ... } bit

◆  [41/47]

struct { ... } bit

◆  [42/47]

struct { ... } bit

◆  [43/47]

struct { ... } bit

◆  [44/47]

struct { ... } bit

◆  [45/47]

struct { ... } bit

◆  [46/47]

struct { ... } bit

◆  [47/47]

struct { ... } bit

◆ CAN_IR0

__IOM uint32_t CAN_IR0

[16..16] DMA Channel Request Select

◆ CAN_IR1

__IOM uint32_t CAN_IR1

[18..18] DMA Channel Request Select

◆ CANCLKEN

__IOM uint32_t CANCLKEN

[1..1] CAN Clock Enable

◆ CHE

__IOM uint32_t CHE

[29..28] DMA Channel Request Select

◆ 

union { ... } CLKCON

◆ 

union { ... } CLKEN

◆ CLKOUTEN

__IOM uint32_t CLKOUTEN

[19..19] CLKOUT Enable

◆ 

union { ... } CLKSEL

◆ DEMEN_CH0

__IOM uint32_t DEMEN_CH0

[0..0] DMA Endless Mode Enable Channel 0

◆ DEMEN_CH1

__IOM uint32_t DEMEN_CH1

[1..1] DMA Endless Mode Enable Channel 1

◆ DEMEN_CH2

__IOM uint32_t DEMEN_CH2

[2..2] DMA Endless Mode Enable Channel 2

◆ DEMEN_CH3

__IOM uint32_t DEMEN_CH3

[3..3] DMA Endless Mode Enable Channel 3

◆ DEMEN_CH4

__IOM uint32_t DEMEN_CH4

[4..4] DMA Endless Mode Enable Channel 4

◆ DEMEN_CH5

__IOM uint32_t DEMEN_CH5

[5..5] DMA Endless Mode Enable Channel 5

◆ DEMEN_CH6

__IOM uint32_t DEMEN_CH6

[6..6] DMA Endless Mode Enable Channel 6

◆ DEMEN_CH7

__IOM uint32_t DEMEN_CH7

[7..7] DMA Endless Mode Enable Channel 7

◆ DIV2CLKOUT

__IOM uint32_t DIV2CLKOUT

[27..27] CLKOUT clock divider by2

◆ DMACH0

__IM uint32_t DMACH0

[0..0] DMA Channel 0 Interrupt Status

◆ DMACH0CLR

__OM uint32_t DMACH0CLR

[0..0] DMA Channel 0 Interrupt Status Clear

◆ DMACH0EN

__IOM uint32_t DMACH0EN

[0..0] DMA Channel 0 Interrupt Enable

◆ DMACH0SET

__OM uint32_t DMACH0SET

[0..0] DMA Channel 0 Interrupt Status Set

◆ DMACH1

__IM uint32_t DMACH1

[1..1] DMA Channel 1 Interrupt Status

◆ DMACH1CLR

__OM uint32_t DMACH1CLR

[1..1] DMA Channel 1 Interrupt Status Clear

◆ DMACH1EN

__IOM uint32_t DMACH1EN

[1..1] DMA Channel 1 Interrupt Enable

◆ DMACH1SET

__OM uint32_t DMACH1SET

[1..1] DMA Channel 1 Interrupt Status Set

◆ DMACH2

__IM uint32_t DMACH2

[2..2] DMA Channel 2 Interrupt Status

◆ DMACH2CLR

__OM uint32_t DMACH2CLR

[2..2] DMA Channel 2 Interrupt Status Clear

◆ DMACH2EN

__IOM uint32_t DMACH2EN

[2..2] DMA Channel 2 Interrupt Enable

◆ DMACH2SET

__OM uint32_t DMACH2SET

[2..2] DMA Channel 2 Interrupt Status Set

◆ DMACH3

__IM uint32_t DMACH3

[3..3] DMA Channel 3 Interrupt Status

◆ DMACH3CLR

__OM uint32_t DMACH3CLR

[3..3] DMA Channel 3 Interrupt Status Clear

◆ DMACH3EN

__IOM uint32_t DMACH3EN

[3..3] DMA Channel 3 Interrupt Enable

◆ DMACH3SET

__OM uint32_t DMACH3SET

[3..3] DMA Channel 3 Interrupt Status Set

◆ DMACH4

__IM uint32_t DMACH4

[4..4] DMA Channel 4 Interrupt Status

◆ DMACH4CLR

__OM uint32_t DMACH4CLR

[4..4] DMA Channel 4 Interrupt Status Clear

◆ DMACH4EN

__IOM uint32_t DMACH4EN

[4..4] DMA Channel 4 Interrupt Enable

◆ DMACH4SET

__OM uint32_t DMACH4SET

[4..4] DMA Channel 4 Interrupt Status Set

◆ DMACH5

__IM uint32_t DMACH5

[5..5] DMA Channel 5 Interrupt Status

◆ DMACH5CLR

__OM uint32_t DMACH5CLR

[5..5] DMA Channel 5 Interrupt Status Clear

◆ DMACH5EN

__IOM uint32_t DMACH5EN

[5..5] DMA Channel 5 Interrupt Enable

◆ DMACH5SET

__OM uint32_t DMACH5SET

[5..5] DMA Channel 5 Interrupt Status Set

◆ DMACH6

__IM uint32_t DMACH6

[6..6] DMA Channel 6 Interrupt Status

◆ DMACH6CLR

__OM uint32_t DMACH6CLR

[6..6] DMA Channel 6 Interrupt Status Clear

◆ DMACH6EN

__IOM uint32_t DMACH6EN

[6..6] DMA Channel 6 Interrupt Enable

◆ DMACH6SET

__OM uint32_t DMACH6SET

[6..6] DMA Channel 6 Interrupt Status Set

◆ DMACH7

__IM uint32_t DMACH7

[7..7] DMA Channel 7 Interrupt Status

◆ DMACH7CLR

__OM uint32_t DMACH7CLR

[7..7] DMA Channel 7 Interrupt Status Clear

◆ DMACH7EN

__IOM uint32_t DMACH7EN

[7..7] DMA Channel 7 Interrupt Enable

◆ DMACH7SET

__OM uint32_t DMACH7SET

[7..7] DMA Channel 7 Interrupt Status Set

◆ 

union { ... } DMACTRL

◆ 

union { ... } DMAIEN

◆ 

union { ... } DMAIS

◆ 

union { ... } DMAISC

◆ 

union { ... } DMAISS

◆ 

union { ... } DMAP_ADC

◆ 

union { ... } DMAP_CCU7

◆ 

union { ... } DMAP_COM

◆ 

union { ... } DMAP_TIM

◆ DMAREQINTEN_CH0

__IOM uint32_t DMAREQINTEN_CH0

[8..8] DMA Pending Request Interrupt Enable Channel 0

◆ DMAREQINTEN_CH1

__IOM uint32_t DMAREQINTEN_CH1

[9..9] DMA Pending Request Interrupt Enable Channel 1

◆ DMAREQINTEN_CH2

__IOM uint32_t DMAREQINTEN_CH2

[10..10] DMA Pending Request Interrupt Enable Channel 2

◆ DMAREQINTEN_CH3

__IOM uint32_t DMAREQINTEN_CH3

[11..11] DMA Pending Request Interrupt Enable Channel 3

◆ DMAREQINTEN_CH4

__IOM uint32_t DMAREQINTEN_CH4

[12..12] DMA Pending Request Interrupt Enable Channel 4

◆ DMAREQINTEN_CH5

__IOM uint32_t DMAREQINTEN_CH5

[13..13] DMA Pending Request Interrupt Enable Channel 5

◆ DMAREQINTEN_CH6

__IOM uint32_t DMAREQINTEN_CH6

[14..14] DMA Pending Request Interrupt Enable Channel 6

◆ DMAREQINTEN_CH7

__IOM uint32_t DMAREQINTEN_CH7

[15..15] DMA Pending Request Interrupt Enable Channel 7

◆ DMATRERREN

__IOM uint32_t DMATRERREN

[8..8] DMA Error Interrupt Enable

◆ 

union { ... } EXTCON

◆ 

union { ... } EXTIEN

◆ EXTINT0EN

__IOM uint32_t EXTINT0EN

[0..0] External EXTINT0 Interrupt Enable

◆ EXTINT0F

__IM uint32_t EXTINT0F

[1..1] External EXTINT0 Falling Edge Interrupt Status

◆ EXTINT0FCLR

__OM uint32_t EXTINT0FCLR

[1..1] External EXTINT0 Falling Edge Interrupt Status Clear

◆ EXTINT0FSET

__OM uint32_t EXTINT0FSET

[1..1] External EXTINT0 Falling Edge Interrupt Status Set

◆ EXTINT0IEV

__IOM uint32_t EXTINT0IEV

[1..0] External EXTINT0 Interrupt Event Select

◆ EXTINT0INSEL

__IOM uint32_t EXTINT0INSEL

[9..8] External EXTINT0 Input Select

◆ EXTINT0R

__IM uint32_t EXTINT0R

[0..0] External EXTINT0 Rising Edge Interrupt Status

◆ EXTINT0RCLR

__OM uint32_t EXTINT0RCLR

[0..0] External EXTINT0 Rising Edge Interrupt Status Clear

◆ EXTINT0RSET

__OM uint32_t EXTINT0RSET

[0..0] External EXTINT0 Rising Edge Interrupt Status Set

◆ EXTINT1EN

__IOM uint32_t EXTINT1EN

[1..1] External EXTINT1 Interrupt Enable

◆ EXTINT1F

__IM uint32_t EXTINT1F

[3..3] External EXTINT1 Falling Edge Interrupt Status

◆ EXTINT1FCLR

__OM uint32_t EXTINT1FCLR

[3..3] External EXTINT1 Falling Edge Interrupt Status Clear

◆ EXTINT1FSET

__OM uint32_t EXTINT1FSET

[3..3] External EXTINT1Falling Edge Interrupt Status Set

◆ EXTINT1IEV

__IOM uint32_t EXTINT1IEV

[3..2] External EXTINT1 Interrupt Event Select

◆ EXTINT1INSEL

__IOM uint32_t EXTINT1INSEL

[11..10] External EXTINT1 Input Select

◆ EXTINT1R

__IM uint32_t EXTINT1R

[2..2] External EXTINT1 Rising Edge Interrupt Status

◆ EXTINT1RCLR

__OM uint32_t EXTINT1RCLR

[2..2] External EXTINT1 Rising Edge Interrupt Status Clear

◆ EXTINT1RSET

__OM uint32_t EXTINT1RSET

[2..2] External EXTINT1Rising Edge Interrupt Status Set

◆ EXTINT2EN

__IOM uint32_t EXTINT2EN

[2..2] External EXTINT2 Interrupt Enable

◆ EXTINT2F

__IM uint32_t EXTINT2F

[5..5] External EXTINT2 Falling Edge Interrupt Status

◆ EXTINT2FCLR

__OM uint32_t EXTINT2FCLR

[5..5] External EXTINT2 Falling Edge Interrupt Status Clear

◆ EXTINT2FSET

__OM uint32_t EXTINT2FSET

[5..5] External EXTINT2 Falling Edge Interrupt Status Set

◆ EXTINT2IEV

__IOM uint32_t EXTINT2IEV

[5..4] External EXTINT2 Interrupt Event Select

◆ EXTINT2INSEL

__IOM uint32_t EXTINT2INSEL

[13..12] External EXTINT2 Input Select

◆ EXTINT2R

__IM uint32_t EXTINT2R

[4..4] External EXTINT2 Rising Edge Interrupt Status

◆ EXTINT2RCLR

__OM uint32_t EXTINT2RCLR

[4..4] External EXTINT2 Rising Edge Interrupt Status Clear

◆ EXTINT2RSET

__OM uint32_t EXTINT2RSET

[4..4] External EXTINT2 Rising Edge Interrupt Status Set

◆ EXTINT3EN

__IOM uint32_t EXTINT3EN

[3..3] External EXTINT3 Interrupt Enable

◆ EXTINT3F

__IM uint32_t EXTINT3F

[7..7] External EXTINT3 Falling Edge Interrupt Status

◆ EXTINT3FCLR

__OM uint32_t EXTINT3FCLR

[7..7] External EXTINT3 Falling Edge Interrupt Status Clear

◆ EXTINT3FSET

__OM uint32_t EXTINT3FSET

[7..7] External EXTINT3 Falling Edge Interrupt Status Set

◆ EXTINT3IEV

__IOM uint32_t EXTINT3IEV

[7..6] External EXTINT3Interrupt Event Select

◆ EXTINT3INSEL

__IOM uint32_t EXTINT3INSEL

[15..14] External EXTINT3 Input Select

◆ EXTINT3R

__IM uint32_t EXTINT3R

[6..6] External EXTINT3 Rising Edge Interrupt Status

◆ EXTINT3RCLR

__OM uint32_t EXTINT3RCLR

[6..6] External EXTINT3 Rising Edge Interrupt Status Clear

◆ EXTINT3RSET

__OM uint32_t EXTINT3RSET

[6..6] External EXTINT3 Rising Edge Interrupt Status Set

◆ 

union { ... } EXTIS

◆ 

union { ... } EXTISC

◆ 

union { ... } EXTISS

◆ GPT12_DIS

__IOM uint32_t GPT12_DIS

[4..4] General Purpose Timer 12 Module Disable

◆ GPT12CR

__IOM uint32_t GPT12CR

[13..13] DMA Channel Request Select

◆ GPT12SUS

__IOM uint32_t GPT12SUS

[4..4] Gerneral Purpose Timer 12 Suspend

◆ GPT12T2

__IOM uint32_t GPT12T2

[8..8] DMA Channel Request Select

◆ GPT12T3

__IOM uint32_t GPT12T3

[9..9] DMA Channel Request Select

◆ GPT12T4

__IOM uint32_t GPT12T4

[10..10] DMA Channel Request Select

◆ GPT12T5

__IOM uint32_t GPT12T5

[11..11] DMA Channel Request Select

◆ GPT12T6

__IOM uint32_t GPT12T6

[12..12] DMA Channel Request Select

◆ GPT1T2

__IM uint32_t GPT1T2

[0..0] General Purpose Timer 1 T2 Interrupt Status

◆ GPT1T2CLR

__OM uint32_t GPT1T2CLR

[0..0] General Purpose Timer 1 T2 Interrupt Status Clear

◆ GPT1T2EN

__IOM uint32_t GPT1T2EN

[0..0] General Purpose Timer 1 T2 Interrupt Enable

◆ GPT1T2SET

__OM uint32_t GPT1T2SET

[0..0] General Purpose Timer 1 T2 Interrupt Status Set

◆ GPT1T3

__IM uint32_t GPT1T3

[1..1] General Purpose Timer 1 T3 Interrupt Status

◆ GPT1T3CLR

__OM uint32_t GPT1T3CLR

[1..1] General Purpose Timer 1 T3 Interrupt Status Clear

◆ GPT1T3EN

__IOM uint32_t GPT1T3EN

[1..1] General Purpose Timer 1 T3 Interrupt Enable

◆ GPT1T3SET

__OM uint32_t GPT1T3SET

[1..1] General Purpose Timer 1 T3 Interrupt Status Set

◆ GPT1T4

__IM uint32_t GPT1T4

[2..2] General Purpose Timer 1 T4 Interrupt Status

◆ GPT1T4CLR

__OM uint32_t GPT1T4CLR

[2..2] General Purpose Timer 1 T4 Interrupt Status Clear

◆ GPT1T4EN

__IOM uint32_t GPT1T4EN

[2..2] General Purpose Timer 1 T4 Interrupt Enable

◆ GPT1T4SET

__OM uint32_t GPT1T4SET

[2..2] General Purpose Timer 1 T4 Interrupt Status Set

◆ GPT2CR

__IM uint32_t GPT2CR

[5..5] General Purpose Timer 2 CR Interrupt Status

◆ GPT2CRCLR

__OM uint32_t GPT2CRCLR

[5..5] General Purpose Timer 2 CR Interrupt Status Clear

◆ GPT2CREN

__IOM uint32_t GPT2CREN

[5..5] General Purpose Timer 2 CR Interrupt Enable

◆ GPT2CRSET

__OM uint32_t GPT2CRSET

[5..5] General Purpose Timer 2 CR Interrupt Status Set

◆ GPT2T5

__IM uint32_t GPT2T5

[3..3] General Purpose Timer 2 T5 Interrupt Status

◆ GPT2T5CLR

__OM uint32_t GPT2T5CLR

[3..3] General Purpose Timer 2 T5 Interrupt Status Clear

◆ GPT2T5EN

__IOM uint32_t GPT2T5EN

[3..3] General Purpose Timer 2 T5 Interrupt Enable

◆ GPT2T5SET

__OM uint32_t GPT2T5SET

[3..3] General Purpose Timer 2 T5 Interrupt Status Set

◆ GPT2T6

__IM uint32_t GPT2T6

[4..4] General Purpose Timer 2 T6 Interrupt Status

◆ GPT2T6CLR

__OM uint32_t GPT2T6CLR

[4..4] General Purpose Timer 2 T6 Interrupt Status Clear

◆ GPT2T6EN

__IOM uint32_t GPT2T6EN

[4..4] General Purpose Timer 2 T6 Interrupt Enable

◆ GPT2T6SET

__OM uint32_t GPT2T6SET

[4..4] General Purpose Timer 2 T6 Interrupt Status Set

◆ 

union { ... } GPTIEN

◆ 

union { ... } GPTIS

◆ 

union { ... } GPTISC

◆ 

union { ... } GPTISS

◆ 

union { ... } INP0

◆ 

union { ... } INP1

◆ 

union { ... } INP2

◆ 

union { ... } INP3

◆ 

union { ... } INP4

◆ 

union { ... } INP5

◆ 

union { ... } INP6

◆ 

union { ... } INP7

◆ INP_ARVG

__IOM uint32_t INP_ARVG

[4..4] ARVG Interrupt Mapping

◆ INP_BDRV_IRQ0

__IOM uint32_t INP_BDRV_IRQ0

[1..1] Bridge Driver Interrupt 0 Mapping

◆ INP_BDRV_IRQ1

__IOM uint32_t INP_BDRV_IRQ1

[2..2] Bridge Driver Interrupt 1 Mapping

◆ INP_BEMF0

__IOM uint32_t INP_BEMF0

[2..2] BEMF0 Interrupt Mapping

◆ INP_BEMF1

__IOM uint32_t INP_BEMF1

[3..3] BEMF1 Interrupt Mapping

◆ INP_BEMF2

__IOM uint32_t INP_BEMF2

[4..4] BEMF2 Interrupt Mapping

◆ INP_CANTX

__IOM uint32_t INP_CANTX

[3..3] CANTX Interrupt Mapping

◆ INP_CSC

__IOM uint32_t INP_CSC

[5..5] CSC Interrupt Mapping

◆ INP_DMACH0

__IOM uint32_t INP_DMACH0

[0..0] DMACH0 Interrupt Mapping

◆ INP_DMACH1

__IOM uint32_t INP_DMACH1

[1..1] DMACH1 Interrupt Mapping

◆ INP_DMACH2

__IOM uint32_t INP_DMACH2

[2..2] DMACH2 Interrupt Mapping

◆ INP_DMACH3

__IOM uint32_t INP_DMACH3

[3..3] DMACH3 Interrupt Mapping

◆ INP_DMACH4

__IOM uint32_t INP_DMACH4

[4..4] DMACH4 Interrupt Mapping

◆ INP_DMACH5

__IOM uint32_t INP_DMACH5

[5..5] DMACH5 Interrupt Mapping

◆ INP_DMACH6

__IOM uint32_t INP_DMACH6

[6..6] DMACH6 Interrupt Mapping

◆ INP_DMACH7

__IOM uint32_t INP_DMACH7

[7..7] DMACH7 Interrupt Mapping

◆ INP_DMATRERR

__IOM uint32_t INP_DMATRERR

[8..8] DMATRERR Interrupt Mapping

◆ INP_EXINT0

__IOM uint32_t INP_EXINT0

[0..0] EXINT0 Interrupt Mapping

◆ INP_EXINT1

__IOM uint32_t INP_EXINT1

[1..1] EXINT1 Interrupt Mapping

◆ INP_EXINT2

__IOM uint32_t INP_EXINT2

[2..2] EXINT2 Interrupt Mapping

◆ INP_EXINT3

__IOM uint32_t INP_EXINT3

[3..3] EXINT3 Interrupt Mapping

◆ INP_GPT1T2

__IOM uint32_t INP_GPT1T2

[0..0] GPT1T2 Interrupt Mapping

◆ INP_GPT1T3

__IOM uint32_t INP_GPT1T3

[1..1] GPT1T3 Interrupt Mapping

◆ INP_GPT1T4

__IOM uint32_t INP_GPT1T4

[2..2] GPT1T4 Interrupt Mapping

◆ INP_GPT2CR

__IOM uint32_t INP_GPT2CR

[5..5] GPT2CR Interrupt Mapping

◆ INP_GPT2T5

__IOM uint32_t INP_GPT2T5

[3..3] GPT2T5 Interrupt Mapping

◆ INP_GPT2T6

__IOM uint32_t INP_GPT2T6

[4..4] GPT2T6 Interrupt Mapping

◆ INP_LIN0_EOFSYN

__IOM uint32_t INP_LIN0_EOFSYN

[0..0] LIN0_EOFSYN Interrupt Mapping

◆ INP_LIN0_ERRSYN

__IOM uint32_t INP_LIN0_ERRSYN

[1..1] LIN0_ERRSYN Interrupt Mapping

◆ INP_LIN1_EOFSYN

__IOM uint32_t INP_LIN1_EOFSYN

[2..2] LIN1_EOFSYN Interrupt Mapping

◆ INP_LIN1_ERRSYN

__IOM uint32_t INP_LIN1_ERRSYN

[3..3] LIN1_ERRSYN Interrupt Mapping

◆ INP_MON1

__IOM uint32_t INP_MON1

[0..0] MON1 Interrupt Mapping

◆ INP_MON2

__IOM uint32_t INP_MON2

[1..1] MON2 Interrupt Mapping

◆ INP_MON3

__IOM uint32_t INP_MON3

[2..2] MON3 Interrupt Mapping

◆ INP_PMU

__IOM uint32_t INP_PMU

[0..0] PMU Interrupt Mapping

◆ INP_SDADC0

__IOM uint32_t INP_SDADC0

[0..0] SDADC0 Interrupt Mapping

◆ INP_SDADC1

__IOM uint32_t INP_SDADC1

[1..1] SDADC1 Interrupt Mapping

◆ INP_SSC0_EIR

__IOM uint32_t INP_SSC0_EIR

[2..2] SSC0_EIR Interrupt Mapping

◆ INP_SSC0_RIR

__IOM uint32_t INP_SSC0_RIR

[0..0] SSC0_RIR Interrupt Mapping

◆ INP_SSC0_TIR

__IOM uint32_t INP_SSC0_TIR

[1..1] SSC0_TIR Interrupt Mapping

◆ INP_SSC1_EIR

__IOM uint32_t INP_SSC1_EIR

[6..6] SSC1_EIR Interrupt Mapping

◆ INP_SSC1_RIR

__IOM uint32_t INP_SSC1_RIR

[4..4] SSC1_RIR Interrupt Mapping

◆ INP_SSC1_TIR

__IOM uint32_t INP_SSC1_TIR

[5..5] SSC1_TIR Interrupt Mapping

◆ INP_UART0_RI

__IOM uint32_t INP_UART0_RI

[4..4] UART0_RI Interrupt Mapping

◆ INP_UART0_TI

__IOM uint32_t INP_UART0_TI

[5..5] UART0_TI Interrupt Mapping

◆ INP_UART1_RI

__IOM uint32_t INP_UART1_RI

[6..6] UART1_RI Interrupt Mapping

◆ INP_UART1_TI

__IOM uint32_t INP_UART1_TI

[7..7] UART1_TI Interrupt Mapping

◆ LOCKUP_EN

__IOM uint32_t LOCKUP_EN

[0..0] CPU LOCKUP Reset Enable

◆ 

union { ... } LOCKUPCFG

◆ MON1EN

__IOM uint32_t MON1EN

[0..0] MON1 Interrupt Enable

◆ MON1F

__IM uint32_t MON1F

[1..1] MON1 Falling Edge Interrupt Status

◆ MON1FCLR

__OM uint32_t MON1FCLR

[1..1] MON1 Falling Edge Interrupt Status Clear

◆ MON1FSET

__OM uint32_t MON1FSET

[1..1] MON1 Falling Edge Interrupt Status Set

◆ MON1IEV

__IOM uint32_t MON1IEV

[1..0] MON1 Interrupt Event Select

◆ MON1R

__IM uint32_t MON1R

[0..0] MON1 Rising Edge Interrupt Status

◆ MON1RCLR

__OM uint32_t MON1RCLR

[0..0] MON1 Rising Edge Interrupt Status Clear

◆ MON1RSET

__OM uint32_t MON1RSET

[0..0] MON1 Rising Edge Interrupt Status Set

◆ MON2EN

__IOM uint32_t MON2EN

[1..1] MON2 Interrupt Enable

◆ MON2F

__IM uint32_t MON2F

[3..3] MON2 Falling Edge Interrupt Status

◆ MON2FCLR

__OM uint32_t MON2FCLR

[3..3] MON2 Falling Edge Interrupt Status Clear

◆ MON2FSET

__OM uint32_t MON2FSET

[3..3] MON2 Falling Edge Interrupt Status Set

◆ MON2IEV

__IOM uint32_t MON2IEV

[3..2] MON2 Interrupt Event Select

◆ MON2R

__IM uint32_t MON2R

[2..2] MON2 Rising Edge Interrupt Status

◆ MON2RCLR

__OM uint32_t MON2RCLR

[2..2] MON2 Rising Edge Interrupt Status Clear

◆ MON2RSET

__OM uint32_t MON2RSET

[2..2] MON2 Rising Edge Interrupt Status Set

◆ MON3EN

__IOM uint32_t MON3EN

[2..2] MON3 Interrupt Enable

◆ MON3F

__IM uint32_t MON3F

[5..5] MON3 Falling Edge Interrupt Status

◆ MON3FCLR

__OM uint32_t MON3FCLR

[5..5] MON3 Falling Edge Interrupt Status Clear

◆ MON3FSET

__OM uint32_t MON3FSET

[5..5] MON3 Falling Edge Interrupt Status Set

◆ MON3IEV

__IOM uint32_t MON3IEV

[5..4] MON3 Interrupt Event Select

◆ MON3R

__IM uint32_t MON3R

[4..4] MON3 Rising Edge Interrupt Status

◆ MON3RCLR

__OM uint32_t MON3RCLR

[4..4] MON3 Rising Edge Interrupt Status Clear

◆ MON3RSET

__OM uint32_t MON3RSET

[4..4] MON3 Rising Edge Interrupt Status Set

◆ 

union { ... } MONCON

◆ 

union { ... } MONIEN

◆ 

union { ... } MONIS

◆ 

union { ... } MONISC

◆ 

union { ... } MONISS

◆ 

union { ... } NMICON

◆ NMIPLL0

__IM uint32_t NMIPLL0

[1..1] PLL0 Loss of Lock NMI Status

◆ NMIPLL0CLR

__OM uint32_t NMIPLL0CLR

[1..1] PLL0 Loss of Lock NMI Status Clear

◆ NMIPLL0EN

__IOM uint32_t NMIPLL0EN

[1..1] PLL0 Loss of Lock NMI Enable

◆ NMIPLL0SET

__OM uint32_t NMIPLL0SET

[1..1] PLL0 Loss of Lock NMI Status Set

◆ NMIPLL1

__IM uint32_t NMIPLL1

[2..2] PLL1 Loss of Lock NMI Status

◆ NMIPLL1CLR

__OM uint32_t NMIPLL1CLR

[2..2] PLL1 Loss of Lock NMI Status Clear

◆ NMIPLL1EN

__IOM uint32_t NMIPLL1EN

[2..2] PLL1 Loss of Lock NMI Enable

◆ NMIPLL1SET

__OM uint32_t NMIPLL1SET

[2..2] PLL1 Loss of Lock NMI Status Set

◆ 

union { ... } NMISR

◆ 

union { ... } NMISRC

◆ 

union { ... } NMISRS

◆ NMIXTAL

__IM uint32_t NMIXTAL

[0..0] XTAL Watchdog Fail NMI Status

◆ NMIXTALCLR

__OM uint32_t NMIXTALCLR

[0..0] XTAL Watchdog Fail NMI Status Clear

◆ NMIXTALEN

__IOM uint32_t NMIXTALEN

[0..0] XTAL Watchdog Fail NMI Enable

◆ NMIXTALSET

__OM uint32_t NMIXTALSET

[0..0] XTAL Watchdog Fail NMI Status Set

◆ OT_SLEEP_EN

__IOM uint32_t OT_SLEEP_EN

[0..0] System Overtemperature Sleep Mode Enable

◆ OTWARN_SD_DIS

__IOM uint32_t OTWARN_SD_DIS

[14..14] Overtemperature Warning Peripherals Shutdown Disable

◆ 

union { ... } PCU_CTRL

◆ 

union { ... } PMCON

◆ 

union { ... } PMCON0

◆ PRECAN

__IOM uint32_t PRECAN

[18..16] CAN_CLK Prescaler Setting (based on sys1_clk)

◆ PRECLKOUT

__IOM uint32_t PRECLKOUT

[26..24] CLKOUT_CLK Prescaler Setting (based on selected clock by SELCLKOUT)

◆ PRECPU

__IOM uint32_t PRECPU

[2..0] CPU_CLK Prescaler Setting (based on sys0_clk)

◆ PREFILT

__IOM uint32_t PREFILT

[8..4] TFILT_CLK Prescaler Setting (based on sys0_clk)

◆ PREMI

__IOM uint32_t PREMI

[11..9] MI_CLK Prescaler Setting (based on sys0_clk)

◆ PREUART

__IOM uint32_t PREUART

[22..20] UART_CLK Prescaler Setting (based on sys1_clk)

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) System Clock Select Register

(@ 0x00000004) Peripheral Clock Prescaler Register

(@ 0x00000008) Peripheral Clock Enable Register

(@ 0x00000014) XTAL Control Register

(@ 0x0000001C) XTAL Status Clear Register

(@ 0x00000020) XTAL Status Set Register

(@ 0x00000024) Interrupt Node 0 Mapping Register

(@ 0x00000028) Interrupt Node 1 Mapping Register

(@ 0x0000002C) Interrupt Node 2 Mapping Register

(@ 0x00000030) Interrupt Node 3 Mapping Register

(@ 0x00000034) Interrupt Node 4 Mapping Register

(@ 0x00000038) Interrupt Node 5 Mapping Register

(@ 0x0000003C) Interrupt Node 6 Mapping Register

(@ 0x00000040) Interrupt Node 7 Mapping Register

(@ 0x00000044) NMI Control Register

(@ 0x0000004C) NMI Status Clear Register

(@ 0x00000050) NMI Status Set Register

(@ 0x00000054) MON Interrupt Enable Register

(@ 0x0000005C) MON Interrupt Status Clear Register

(@ 0x00000060) MON Interrupt Status Set Register

(@ 0x00000064) MON Interrupt Configuration Register

(@ 0x00000068) External Interrupt Enable Register

(@ 0x00000070) External Interrupt Status Clear Register

(@ 0x00000074) External Interrupt Status Set Register

(@ 0x00000078) EXT Interrupt Configuration Register

(@ 0x0000007C) General Purpose Timer 12 Interrupt Enable Register

(@ 0x00000084) General Purpose Timer 12 Interrupt Status Clear Register

(@ 0x00000088) General Purpose Timer 12 Interrupt Status Set Register

(@ 0x0000008C) DMA Interrupt Enable Register

(@ 0x00000094) DAM Interrupt Status Clear Register

(@ 0x00000098) DMA Interrupt Status Set Register

(@ 0x0000009C) DMA Channel Select Register CCU7

(@ 0x000000A0) DMA Channel Select Register ADCs

(@ 0x000000A4) DMA Channel Select Register Timer

(@ 0x000000A8) DMA Channel Select Register COM Modules

(@ 0x000000AC) Power Mode Control Register

(@ 0x000000B0) Peripheral Management Control Register

(@ 0x000000B4) Module Suspend Control Register

(@ 0x000000B8) PCU Control Register

(@ 0x000000E0) DMA Control Register

(@ 0x000000E8) CPU LOCKUP Config Register

◆ reg [2/2]

__IM uint32_t reg

(@ 0x00000018) XTAL Status Register

(@ 0x00000048) NMI Status Register

(@ 0x00000058) MON Interrupt Status Register

(@ 0x0000006C) External Interrupt Status Register

(@ 0x00000080) General Purpose Timer 12 Interrupt Status Register

(@ 0x00000090) DMA Interrupt Status Register

◆ RESERVED

__IM uint32_t RESERVED[2]

◆ RESERVED1

__IM uint32_t RESERVED1[9]

◆ RESERVED2

__IM uint32_t RESERVED2

◆ SDADC_RES0

__IOM uint32_t SDADC_RES0

[25..24] DMA Channel Request Select

◆ SDADC_RES1

__IOM uint32_t SDADC_RES1

[27..26] DMA Channel Request Select

◆ SELCLKOUT

__IOM uint32_t SELCLKOUT

[18..16] CLKOUT Selection

◆ SELSYS0

__IOM uint32_t SELSYS0

[1..0] System Clock fsys0 Select

◆ SELSYS1

__IOM uint32_t SELSYS1

[3..2] System Clock fsys1 Select

◆ SLEEP

__OM uint32_t SLEEP

[1..1] Sleep Mode Enable

◆ SSC0_DIS

__IOM uint32_t SSC0_DIS

[0..0] SSC0 Module Disable

◆ SSC0_RIR

__IOM uint32_t SSC0_RIR

[1..0] DMA Channel Request Select

◆ SSC0_TIR

__IOM uint32_t SSC0_TIR

[3..2] DMA Channel Request Select

◆ SSC0SUS

__IOM uint32_t SSC0SUS

[0..0] SSC0 Suspend

◆ SSC1_DIS

__IOM uint32_t SSC1_DIS

[1..1] SSC1 Module Disable

◆ SSC1_RIR

__IOM uint32_t SSC1_RIR

[5..4] DMA Channel Request Select

◆ SSC1_TIR

__IOM uint32_t SSC1_TIR

[7..6] DMA Channel Request Select

◆ SSC1SUS

__IOM uint32_t SSC1SUS

[1..1] SSC1 Suspend

◆ STOP

__OM uint32_t STOP

[2..2] STOP Mode Enable

◆ 

union { ... } SUSCTR

◆ T12CM70

__IOM uint32_t T12CM70

[1..0] DMA Channel Request Select

◆ T12CM71

__IOM uint32_t T12CM71

[3..2] DMA Channel Request Select

◆ T12CM72

__IOM uint32_t T12CM72

[5..4] DMA Channel Request Select

◆ T12PM

__IOM uint32_t T12PM

[7..6] DMA Channel Request Select

◆ T12ZM

__IOM uint32_t T12ZM

[9..8] DMA Channel Request Select

◆ T13CM

__IOM uint32_t T13CM

[11..10] DMA Channel Request Select

◆ T13PM

__IOM uint32_t T13PM

[13..12] DMA Channel Request Select

◆ T13ZM

__IOM uint32_t T13ZM

[15..14] DMA Channel Request Select

◆ T14CM

__IOM uint32_t T14CM

[17..16] DMA Channel Request Select

◆ T14PM

__IOM uint32_t T14PM

[19..18] DMA Channel Request Select

◆ T15CM

__IOM uint32_t T15CM

[21..20] DMA Channel Request Select

◆ T15PM

__IOM uint32_t T15PM

[23..22] DMA Channel Request Select

◆ T16CM

__IOM uint32_t T16CM

[25..24] DMA Channel Request Select

◆ T16PM

__IOM uint32_t T16PM

[27..26] DMA Channel Request Select

◆ T21_DIS

__IOM uint32_t T21_DIS

[3..3] Timer 21 Module Disable

◆ T21OV

__IOM uint32_t T21OV

[1..1] DMA Channel Request Select

◆ T21SUS

__IOM uint32_t T21SUS

[3..3] Timer 21 Suspend

◆ T2_DIS

__IOM uint32_t T2_DIS

[2..2] Timer 20 Module Disable

◆ T2OV

__IOM uint32_t T2OV

[0..0] DMA Channel Request Select

◆ T2SUS

__IOM uint32_t T2SUS

[2..2] Timer 20 Suspend

◆ UART0_RI

__IOM uint32_t UART0_RI

[9..8] DMA Channel Request Select

◆ UART0_TI

__IOM uint32_t UART0_TI

[11..10] DMA Channel Request Select

◆ UART1_RI

__IOM uint32_t UART1_RI

[13..12] DMA Channel Request Select

◆ UART1_TI

__IOM uint32_t UART1_TI

[15..14] DMA Channel Request Select

◆ UARTCLKEN

__IOM uint32_t UARTCLKEN

[0..0] UART Clock Enable

◆ WDTSUS

__IOM uint32_t WDTSUS

[5..5] SCU Watchdog Timer Suspend

◆ XPD

__IOM uint32_t XPD

[0..0] XTAL Power Down Control

◆ XTAL_FAIL_STS

__IM uint32_t XTAL_FAIL_STS

[0..0] XTAL Watchdog Fail Latched Status

◆ XTAL_FAIL_STSCLR

__OM uint32_t XTAL_FAIL_STSCLR

[0..0] XTAL Watchdog Fail Latched Status Clear

◆ XTAL_FAIL_STSSET

__OM uint32_t XTAL_FAIL_STSSET

[0..0] XTAL Watchdog Fail Latched Status Set

◆ 

union { ... } XTALCON

◆ XTALFAIL

__IM uint32_t XTALFAIL

[8..8] XTAL Watchdog Fail Current Status

◆ XTALHYS

__IOM uint32_t XTALHYS

[5..4] XTAL Hysteresis Control

◆ XTALHYSEN

__IOM uint32_t XTALHYSEN

[1..1] XTAL Hysteresis Enable

◆ 

union { ... } XTALSTAT

◆ 

union { ... } XTALSTATC

◆ 

union { ... } XTALSTATS

◆ XTALWDG_SD_DIS

__IOM uint32_t XTALWDG_SD_DIS

[15..15] XTAL Watchdog Peripherals Shutdown Disable

◆ XWDGEN

__IOM uint32_t XWDGEN

[24..24] XTALWDG Enable

◆ XWDGRES

__OM uint32_t XWDGRES

[28..28] XTALWDG Reset


The documentation for this struct was generated from the following file: