Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
GPIO_Type Struct Reference

Detailed Description

GPIO (GPIO)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PO0: 1
 
      __IOM uint32_t   PO1: 1
 
      __IOM uint32_t   PO2: 1
 
      __IOM uint32_t   PO3: 1
 
      __IOM uint32_t   PO4: 1
 
      __IOM uint32_t   PO5: 1
 
      __IOM uint32_t   PO6: 1
 
      __IOM uint32_t   PO7: 1
 
      __IOM uint32_t   PO8: 1
 
      __IOM uint32_t   PO9: 1
 
      __IOM uint32_t   PO10: 1
 
      uint32_t   __pad0__: 21
 
   }   bit
 
P0_OUT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PS0: 1
 
      __OM uint32_t   PS1: 1
 
      __OM uint32_t   PS2: 1
 
      __OM uint32_t   PS3: 1
 
      __OM uint32_t   PS4: 1
 
      __OM uint32_t   PS5: 1
 
      __OM uint32_t   PS6: 1
 
      __OM uint32_t   PS7: 1
 
      __OM uint32_t   PS8: 1
 
      __OM uint32_t   PS9: 1
 
      __OM uint32_t   PS10: 1
 
      uint32_t   __pad0__: 5
 
      __OM uint32_t   PR0: 1
 
      __OM uint32_t   PR1: 1
 
      __OM uint32_t   PR2: 1
 
      __OM uint32_t   PR3: 1
 
      __OM uint32_t   PR4: 1
 
      __OM uint32_t   PR5: 1
 
      __OM uint32_t   PR6: 1
 
      __OM uint32_t   PR7: 1
 
      __OM uint32_t   PR8: 1
 
      __OM uint32_t   PR9: 1
 
      __OM uint32_t   PR10: 1
 
      uint32_t   __pad1__: 5
 
   }   bit
 
P0_OMR
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   PI0: 1
 
      __IM uint32_t   PI1: 1
 
      __IM uint32_t   PI2: 1
 
      __IM uint32_t   PI3: 1
 
      __IM uint32_t   PI4: 1
 
      __IM uint32_t   PI5: 1
 
      __IM uint32_t   PI6: 1
 
      __IM uint32_t   PI7: 1
 
      __IM uint32_t   PI8: 1
 
      __IM uint32_t   PI9: 1
 
      __IM uint32_t   PI10: 1
 
      uint32_t   __pad0__: 21
 
   }   bit
 
P0_IN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DIR0: 1
 
      __IOM uint32_t   DIR1: 1
 
      __IOM uint32_t   DIR2: 1
 
      __IOM uint32_t   DIR3: 1
 
      __IOM uint32_t   DIR4: 1
 
      __IOM uint32_t   DIR5: 1
 
      __IOM uint32_t   DIR6: 1
 
      __IOM uint32_t   DIR7: 1
 
      __IOM uint32_t   DIR8: 1
 
      __IOM uint32_t   DIR9: 1
 
      __IOM uint32_t   DIR10: 1
 
      uint32_t   __pad0__: 21
 
   }   bit
 
P0_DIR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OD0: 1
 
      __IOM uint32_t   OD1: 1
 
      __IOM uint32_t   OD2: 1
 
      __IOM uint32_t   OD3: 1
 
      __IOM uint32_t   OD4: 1
 
      __IOM uint32_t   OD5: 1
 
      __IOM uint32_t   OD6: 1
 
      __IOM uint32_t   OD7: 1
 
      __IOM uint32_t   OD8: 1
 
      __IOM uint32_t   OD9: 1
 
      __IOM uint32_t   OD10: 1
 
      uint32_t   __pad0__: 21
 
   }   bit
 
P0_OD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PUDEN0: 1
 
      __IOM uint32_t   PUDEN1: 1
 
      __IOM uint32_t   PUDEN2: 1
 
      __IOM uint32_t   PUDEN3: 1
 
      __IOM uint32_t   PUDEN4: 1
 
      __IOM uint32_t   PUDEN5: 1
 
      __IOM uint32_t   PUDEN6: 1
 
      __IOM uint32_t   PUDEN7: 1
 
      __IOM uint32_t   PUDEN8: 1
 
      __IOM uint32_t   PUDEN9: 1
 
      __IOM uint32_t   PUDEN10: 1
 
      uint32_t   __pad0__: 5
 
      __IOM uint32_t   PUDSEL0: 1
 
      __IOM uint32_t   PUDSEL1: 1
 
      __IOM uint32_t   PUDSEL2: 1
 
      __IOM uint32_t   PUDSEL3: 1
 
      __IOM uint32_t   PUDSEL4: 1
 
      __IOM uint32_t   PUDSEL5: 1
 
      __IOM uint32_t   PUDSEL6: 1
 
      __IOM uint32_t   PUDSEL7: 1
 
      __IOM uint32_t   PUDSEL8: 1
 
      __IOM uint32_t   PUDSEL9: 1
 
      __IOM uint32_t   PUDSEL10: 1
 
      uint32_t   __pad1__: 5
 
   }   bit
 
P0_PUD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ALTSEL0: 3
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   ALTSEL1: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   ALTSEL2: 3
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   ALTSEL3: 3
 
      uint32_t   __pad3__: 1
 
      __IOM uint32_t   ALTSEL4: 3
 
      uint32_t   __pad4__: 1
 
      __IOM uint32_t   ALTSEL5: 3
 
      uint32_t   __pad5__: 1
 
      __IOM uint32_t   ALTSEL6: 3
 
      uint32_t   __pad6__: 1
 
      __IOM uint32_t   ALTSEL7: 3
 
      uint32_t   __pad7__: 1
 
   }   bit
 
P0_ALTSEL0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ALTSEL8: 3
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   ALTSEL9: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   ALTSEL10: 3
 
      uint32_t   __pad2__: 21
 
   }   bit
 
P0_ALTSEL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PDM0: 2
 
      __IOM uint32_t   PDM1: 2
 
      __IOM uint32_t   PDM2: 2
 
      __IOM uint32_t   PDM3: 2
 
      __IOM uint32_t   PDM4: 2
 
      __IOM uint32_t   PDM5: 2
 
      __IOM uint32_t   PDM6: 2
 
      __IOM uint32_t   PDM7: 2
 
      __IOM uint32_t   PDM8: 2
 
      __IOM uint32_t   PDM9: 2
 
      __IOM uint32_t   PDM10: 2
 
      uint32_t   __pad0__: 10
 
   }   bit
 
P0_POCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PO0: 1
 
      __IOM uint32_t   PO1: 1
 
      __IOM uint32_t   PO2: 1
 
      __IOM uint32_t   PO3: 1
 
      __IOM uint32_t   PO4: 1
 
      uint32_t   __pad0__: 27
 
   }   bit
 
P1_OUT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PS0: 1
 
      __OM uint32_t   PS1: 1
 
      __OM uint32_t   PS2: 1
 
      __OM uint32_t   PS3: 1
 
      __OM uint32_t   PS4: 1
 
      uint32_t   __pad0__: 11
 
      __OM uint32_t   PR0: 1
 
      __OM uint32_t   PR1: 1
 
      __OM uint32_t   PR2: 1
 
      __OM uint32_t   PR3: 1
 
      __OM uint32_t   PR4: 1
 
      uint32_t   __pad1__: 11
 
   }   bit
 
P1_OMR
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   PI0: 1
 
      __IM uint32_t   PI1: 1
 
      __IM uint32_t   PI2: 1
 
      __IM uint32_t   PI3: 1
 
      __IM uint32_t   PI4: 1
 
      uint32_t   __pad0__: 27
 
   }   bit
 
P1_IN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DIR0: 1
 
      __IOM uint32_t   DIR1: 1
 
      __IOM uint32_t   DIR2: 1
 
      __IOM uint32_t   DIR3: 1
 
      __IOM uint32_t   DIR4: 1
 
      uint32_t   __pad0__: 27
 
   }   bit
 
P1_DIR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OD0: 1
 
      __IOM uint32_t   OD1: 1
 
      __IOM uint32_t   OD2: 1
 
      __IOM uint32_t   OD3: 1
 
      __IOM uint32_t   OD4: 1
 
      uint32_t   __pad0__: 27
 
   }   bit
 
P1_OD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PUDEN0: 1
 
      __IOM uint32_t   PUDEN1: 1
 
      __IOM uint32_t   PUDEN2: 1
 
      __IOM uint32_t   PUDEN3: 1
 
      __IOM uint32_t   PUDEN4: 1
 
      uint32_t   __pad0__: 11
 
      __IOM uint32_t   PUDSEL0: 1
 
      __IOM uint32_t   PUDSEL1: 1
 
      __IOM uint32_t   PUDSEL2: 1
 
      __IOM uint32_t   PUDSEL3: 1
 
      __IOM uint32_t   PUDSEL4: 1
 
      uint32_t   __pad1__: 11
 
   }   bit
 
P1_PUD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ALTSEL0: 3
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   ALTSEL1: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   ALTSEL2: 3
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   ALTSEL3: 3
 
      uint32_t   __pad3__: 1
 
      __IOM uint32_t   ALTSEL4: 3
 
      uint32_t   __pad4__: 13
 
   }   bit
 
P1_ALTSEL0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PDM0: 2
 
      __IOM uint32_t   PDM1: 2
 
      __IOM uint32_t   PDM2: 2
 
      __IOM uint32_t   PDM3: 2
 
      __IOM uint32_t   PDM4: 2
 
      uint32_t   __pad0__: 22
 
   }   bit
 
P1_POCON
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   PI0: 1
 
      __IM uint32_t   PI1: 1
 
      __IM uint32_t   PI2: 1
 
      __IM uint32_t   PI3: 1
 
      __IM uint32_t   PI4: 1
 
      __IM uint32_t   PI5: 1
 
      __IM uint32_t   PI6: 1
 
      __IM uint32_t   PI7: 1
 
      __IM uint32_t   PI8: 1
 
      __IM uint32_t   PI9: 1
 
      uint32_t   __pad0__: 22
 
   }   bit
 
P2_IN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INDIS0: 1
 
      __IOM uint32_t   INDIS1: 1
 
      __IOM uint32_t   INDIS2: 1
 
      __IOM uint32_t   INDIS3: 1
 
      __IOM uint32_t   INDIS4: 1
 
      __IOM uint32_t   INDIS5: 1
 
      __IOM uint32_t   INDIS6: 1
 
      __IOM uint32_t   INDIS7: 1
 
      __IOM uint32_t   INDIS8: 1
 
      __IOM uint32_t   INDIS9: 1
 
      uint32_t   __pad0__: 22
 
   }   bit
 
P2_INDIS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PUDEN0: 1
 
      __IOM uint32_t   PUDEN1: 1
 
      __IOM uint32_t   PUDEN2: 1
 
      __IOM uint32_t   PUDEN3: 1
 
      __IOM uint32_t   PUDEN4: 1
 
      __IOM uint32_t   PUDEN5: 1
 
      __IOM uint32_t   PUDEN6: 1
 
      __IOM uint32_t   PUDEN7: 1
 
      __IOM uint32_t   PUDEN8: 1
 
      __IOM uint32_t   PUDEN9: 1
 
      uint32_t   __pad0__: 6
 
      __IOM uint32_t   PUDSEL0: 1
 
      __IOM uint32_t   PUDSEL1: 1
 
      __IOM uint32_t   PUDSEL2: 1
 
      __IOM uint32_t   PUDSEL3: 1
 
      __IOM uint32_t   PUDSEL4: 1
 
      __IOM uint32_t   PUDSEL5: 1
 
      __IOM uint32_t   PUDSEL6: 1
 
      __IOM uint32_t   PUDSEL7: 1
 
      __IOM uint32_t   PUDSEL8: 1
 
      __IOM uint32_t   PUDSEL9: 1
 
      uint32_t   __pad1__: 6
 
   }   bit
 
P2_PUD
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆ __pad4__

uint32_t __pad4__

◆ __pad5__

uint32_t __pad5__

◆ __pad6__

uint32_t __pad6__

◆ __pad7__

uint32_t __pad7__

◆ ALTSEL0

__IOM uint32_t ALTSEL0

[2..0] Alternate output select

◆ ALTSEL1

__IOM uint32_t ALTSEL1

[6..4] Alternate output select

◆ ALTSEL10

__IOM uint32_t ALTSEL10

[10..8] Alternate output select

◆ ALTSEL2

__IOM uint32_t ALTSEL2

[10..8] Alternate output select

◆ ALTSEL3

__IOM uint32_t ALTSEL3

[14..12] Alternate output select

◆ ALTSEL4

__IOM uint32_t ALTSEL4

[18..16] Alternate output select

◆ ALTSEL5

__IOM uint32_t ALTSEL5

[22..20] Alternate output select

◆ ALTSEL6

__IOM uint32_t ALTSEL6

[26..24] Alternate output select

◆ ALTSEL7

__IOM uint32_t ALTSEL7

[30..28] Alternate output select

◆ ALTSEL8

__IOM uint32_t ALTSEL8

[2..0] Alternate output select

◆ ALTSEL9

__IOM uint32_t ALTSEL9

[6..4] Alternate output select

◆  [1/20]

struct { ... } bit

◆  [2/20]

struct { ... } bit

◆  [3/20]

struct { ... } bit

◆  [4/20]

struct { ... } bit

◆  [5/20]

struct { ... } bit

◆  [6/20]

struct { ... } bit

◆  [7/20]

struct { ... } bit

◆  [8/20]

struct { ... } bit

◆  [9/20]

struct { ... } bit

◆  [10/20]

struct { ... } bit

◆  [11/20]

struct { ... } bit

◆  [12/20]

struct { ... } bit

◆  [13/20]

struct { ... } bit

◆  [14/20]

struct { ... } bit

◆  [15/20]

struct { ... } bit

◆  [16/20]

struct { ... } bit

◆  [17/20]

struct { ... } bit

◆  [18/20]

struct { ... } bit

◆  [19/20]

struct { ... } bit

◆  [20/20]

struct { ... } bit

◆ DIR0

__IOM uint32_t DIR0

[0..0] Direction control bit

◆ DIR1

__IOM uint32_t DIR1

[1..1] Direction control bit

◆ DIR10

__IOM uint32_t DIR10

[10..10] Direction control bit

◆ DIR2

__IOM uint32_t DIR2

[2..2] Direction control bit

◆ DIR3

__IOM uint32_t DIR3

[3..3] Direction control bit

◆ DIR4

__IOM uint32_t DIR4

[4..4] Direction control bit

◆ DIR5

__IOM uint32_t DIR5

[5..5] Direction control bit

◆ DIR6

__IOM uint32_t DIR6

[6..6] Direction control bit

◆ DIR7

__IOM uint32_t DIR7

[7..7] Direction control bit

◆ DIR8

__IOM uint32_t DIR8

[8..8] Direction control bit

◆ DIR9

__IOM uint32_t DIR9

[9..9] Direction control bit

◆ INDIS0

__IOM uint32_t INDIS0

[0..0] Input disable control bit

◆ INDIS1

__IOM uint32_t INDIS1

[1..1] Input disable control bit

◆ INDIS2

__IOM uint32_t INDIS2

[2..2] Input disable control bit

◆ INDIS3

__IOM uint32_t INDIS3

[3..3] Input disable control bit

◆ INDIS4

__IOM uint32_t INDIS4

[4..4] Input disable control bit

◆ INDIS5

__IOM uint32_t INDIS5

[5..5] Input disable control bit

◆ INDIS6

__IOM uint32_t INDIS6

[6..6] Input disable control bit

◆ INDIS7

__IOM uint32_t INDIS7

[7..7] Input disable control bit

◆ INDIS8

__IOM uint32_t INDIS8

[8..8] Input disable control bit

◆ INDIS9

__IOM uint32_t INDIS9

[9..9] Input disable control bit

◆ OD0

__IOM uint32_t OD0

[0..0] Open drain control bit

◆ OD1

__IOM uint32_t OD1

[1..1] Open drain control bit

◆ OD10

__IOM uint32_t OD10

[10..10] Open drain control bit

◆ OD2

__IOM uint32_t OD2

[2..2] Open drain control bit

◆ OD3

__IOM uint32_t OD3

[3..3] Open drain control bit

◆ OD4

__IOM uint32_t OD4

[4..4] Open drain control bit

◆ OD5

__IOM uint32_t OD5

[5..5] Open drain control bit

◆ OD6

__IOM uint32_t OD6

[6..6] Open drain control bit

◆ OD7

__IOM uint32_t OD7

[7..7] Open drain control bit

◆ OD8

__IOM uint32_t OD8

[8..8] Open drain control bit

◆ OD9

__IOM uint32_t OD9

[9..9] Open drain control bit

◆ 

union { ... } P0_ALTSEL0

◆ 

union { ... } P0_ALTSEL1

◆ 

union { ... } P0_DIR

◆ 

union { ... } P0_IN

◆ 

union { ... } P0_OD

◆ 

union { ... } P0_OMR

◆ 

union { ... } P0_OUT

◆ 

union { ... } P0_POCON

◆ 

union { ... } P0_PUD

◆ 

union { ... } P1_ALTSEL0

◆ 

union { ... } P1_DIR

◆ 

union { ... } P1_IN

◆ 

union { ... } P1_OD

◆ 

union { ... } P1_OMR

◆ 

union { ... } P1_OUT

◆ 

union { ... } P1_POCON

◆ 

union { ... } P1_PUD

◆ 

union { ... } P2_IN

◆ 

union { ... } P2_INDIS

◆ 

union { ... } P2_PUD

◆ PDM0

__IOM uint32_t PDM0

[1..0] Output driver mode control

◆ PDM1

__IOM uint32_t PDM1

[3..2] Output driver mode control

◆ PDM10

__IOM uint32_t PDM10

[21..20] Output driver mode control

◆ PDM2

__IOM uint32_t PDM2

[5..4] Output driver mode control

◆ PDM3

__IOM uint32_t PDM3

[7..6] Output driver mode control

◆ PDM4

__IOM uint32_t PDM4

[9..8] Output driver mode control

◆ PDM5

__IOM uint32_t PDM5

[11..10] Output driver mode control

◆ PDM6

__IOM uint32_t PDM6

[13..12] Output driver mode control

◆ PDM7

__IOM uint32_t PDM7

[15..14] Output driver mode control

◆ PDM8

__IOM uint32_t PDM8

[17..16] Output driver mode control

◆ PDM9

__IOM uint32_t PDM9

[19..18] Output driver mode control

◆ PI0

__IM uint32_t PI0

[0..0] Input bit

◆ PI1

__IM uint32_t PI1

[1..1] Input bit

◆ PI10

__IM uint32_t PI10

[10..10] Input bit

◆ PI2

__IM uint32_t PI2

[2..2] Input bit

◆ PI3

__IM uint32_t PI3

[3..3] Input bit

◆ PI4

__IM uint32_t PI4

[4..4] Input bit

◆ PI5

__IM uint32_t PI5

[5..5] Input bit

◆ PI6

__IM uint32_t PI6

[6..6] Input bit

◆ PI7

__IM uint32_t PI7

[7..7] Input bit

◆ PI8

__IM uint32_t PI8

[8..8] Input bit

◆ PI9

__IM uint32_t PI9

[9..9] Input bit

◆ PO0

__IOM uint32_t PO0

[0..0] Output bit

◆ PO1

__IOM uint32_t PO1

[1..1] Output bit

◆ PO10

__IOM uint32_t PO10

[10..10] Output bit

◆ PO2

__IOM uint32_t PO2

[2..2] Output bit

◆ PO3

__IOM uint32_t PO3

[3..3] Output bit

◆ PO4

__IOM uint32_t PO4

[4..4] Output bit

◆ PO5

__IOM uint32_t PO5

[5..5] Output bit

◆ PO6

__IOM uint32_t PO6

[6..6] Output bit

◆ PO7

__IOM uint32_t PO7

[7..7] Output bit

◆ PO8

__IOM uint32_t PO8

[8..8] Output bit

◆ PO9

__IOM uint32_t PO9

[9..9] Output bit

◆ PR0

__OM uint32_t PR0

[16..16] Output reset bit

◆ PR1

__OM uint32_t PR1

[17..17] Output reset bit

◆ PR10

__OM uint32_t PR10

[26..26] Output reset bit

◆ PR2

__OM uint32_t PR2

[18..18] Output reset bit

◆ PR3

__OM uint32_t PR3

[19..19] Output reset bit

◆ PR4

__OM uint32_t PR4

[20..20] Output reset bit

◆ PR5

__OM uint32_t PR5

[21..21] Output reset bit

◆ PR6

__OM uint32_t PR6

[22..22] Output reset bit

◆ PR7

__OM uint32_t PR7

[23..23] Output reset bit

◆ PR8

__OM uint32_t PR8

[24..24] Output reset bit

◆ PR9

__OM uint32_t PR9

[25..25] Output reset bit

◆ PS0

__OM uint32_t PS0

[0..0] Output set bit

◆ PS1

__OM uint32_t PS1

[1..1] Output set bit

◆ PS10

__OM uint32_t PS10

[10..10] Output set bit

◆ PS2

__OM uint32_t PS2

[2..2] Output set bit

◆ PS3

__OM uint32_t PS3

[3..3] Output set bit

◆ PS4

__OM uint32_t PS4

[4..4] Output set bit

◆ PS5

__OM uint32_t PS5

[5..5] Output set bit

◆ PS6

__OM uint32_t PS6

[6..6] Output set bit

◆ PS7

__OM uint32_t PS7

[7..7] Output set bit

◆ PS8

__OM uint32_t PS8

[8..8] Output set bit

◆ PS9

__OM uint32_t PS9

[9..9] Output set bit

◆ PUDEN0

__IOM uint32_t PUDEN0

[0..0] Pull-up/pull-down enable bit

◆ PUDEN1

__IOM uint32_t PUDEN1

[1..1] Pull-up/pull-down enable bit

◆ PUDEN10

__IOM uint32_t PUDEN10

[10..10] Pull-up/pull-down enable bit

◆ PUDEN2

__IOM uint32_t PUDEN2

[2..2] Pull-up/pull-down enable bit

◆ PUDEN3

__IOM uint32_t PUDEN3

[3..3] Pull-up/pull-down enable bit

◆ PUDEN4

__IOM uint32_t PUDEN4

[4..4] Pull-up/pull-down enable bit

◆ PUDEN5

__IOM uint32_t PUDEN5

[5..5] Pull-up/pull-down enable bit

◆ PUDEN6

__IOM uint32_t PUDEN6

[6..6] Pull-up/pull-down enable bit

◆ PUDEN7

__IOM uint32_t PUDEN7

[7..7] Pull-up/pull-down enable bit

◆ PUDEN8

__IOM uint32_t PUDEN8

[8..8] Pull-up/pull-down enable bit

◆ PUDEN9

__IOM uint32_t PUDEN9

[9..9] Pull-up/pull-down enable bit

◆ PUDSEL0

__IOM uint32_t PUDSEL0

[16..16] Pull-up/pull-down select bit

◆ PUDSEL1

__IOM uint32_t PUDSEL1

[17..17] Pull-up/pull-down select bit

◆ PUDSEL10

__IOM uint32_t PUDSEL10

[26..26] Pull-up/pull-down select bit

◆ PUDSEL2

__IOM uint32_t PUDSEL2

[18..18] Pull-up/pull-down select bit

◆ PUDSEL3

__IOM uint32_t PUDSEL3

[19..19] Pull-up/pull-down select bit

◆ PUDSEL4

__IOM uint32_t PUDSEL4

[20..20] Pull-up/pull-down select bit

◆ PUDSEL5

__IOM uint32_t PUDSEL5

[21..21] Pull-up/pull-down select bit

◆ PUDSEL6

__IOM uint32_t PUDSEL6

[22..22] Pull-up/pull-down select bit

◆ PUDSEL7

__IOM uint32_t PUDSEL7

[23..23] Pull-up/pull-down select bit

◆ PUDSEL8

__IOM uint32_t PUDSEL8

[24..24] Pull-up/pull-down select bit

◆ PUDSEL9

__IOM uint32_t PUDSEL9

[25..25] Pull-up/pull-down select bit

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) Port 0 output register

(@ 0x00000004) Port 0 output modification register

(@ 0x0000000C) Port 0 direction control

(@ 0x00000010) Port 0 open drain control

(@ 0x00000014) Port 0 pull-up/pull-down control

(@ 0x00000018) Port 0 alternate output select 0

(@ 0x0000001C) Port 0 alternate output select 1

(@ 0x00000020) Port 0 output driver control

(@ 0x00000024) Port 1 output register

(@ 0x00000028) Port 1 output modification register

(@ 0x00000030) Port 1 direction control

(@ 0x00000034) Port 1 open drain control

(@ 0x00000038) Port 1 pull-up/pull-down control

(@ 0x0000003C) Port 1 alternate output select 0

(@ 0x00000040) Port 1 output driver control

(@ 0x00000048) Port 2 input disable register

(@ 0x0000004C) Port 2 pull-up/pull-down control

◆ reg [2/2]

__IM uint32_t reg

(@ 0x00000008) Port 0 input register

(@ 0x0000002C) Port 1 input register

(@ 0x00000044) Port 2 input register


The documentation for this struct was generated from the following file: