80 #include "dma_defines.h"
194 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
196 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
198 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
200 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
202 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
204 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
206 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
208 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
332 DMA->DMA_CFG.bit.MASTER_ENABLE = 1u;
339 SCU->DMACTRL.bit.DEMEN_CH0 = 1u;
346 SCU->DMACTRL.bit.DEMEN_CH0 = 0u;
353 SCU->DMACTRL.bit.DEMEN_CH1 = 1u;
360 SCU->DMACTRL.bit.DEMEN_CH1 = 0u;
367 SCU->DMACTRL.bit.DEMEN_CH2 = 1u;
374 SCU->DMACTRL.bit.DEMEN_CH2 = 0u;
381 SCU->DMACTRL.bit.DEMEN_CH3 = 1u;
388 SCU->DMACTRL.bit.DEMEN_CH3 = 0u;
395 SCU->DMACTRL.bit.DEMEN_CH4 = 1u;
402 SCU->DMACTRL.bit.DEMEN_CH4 = 0u;
409 SCU->DMACTRL.bit.DEMEN_CH5 = 1u;
416 SCU->DMACTRL.bit.DEMEN_CH5 = 0u;
423 SCU->DMACTRL.bit.DEMEN_CH6 = 1u;
430 SCU->DMACTRL.bit.DEMEN_CH6 = 0u;
437 SCU->DMACTRL.bit.DEMEN_CH7 = 1u;
444 SCU->DMACTRL.bit.DEMEN_CH7 = 0u;
451 SCU->DMAIEN.bit.DMACH0EN = 1u;
458 SCU->DMAIEN.bit.DMACH0EN = 0u;
465 SCU->DMAIEN.bit.DMACH1EN = 1u;
472 SCU->DMAIEN.bit.DMACH1EN = 0u;
479 SCU->DMAIEN.bit.DMACH2EN = 1u;
486 SCU->DMAIEN.bit.DMACH2EN = 0u;
493 SCU->DMAIEN.bit.DMACH3EN = 1u;
500 SCU->DMAIEN.bit.DMACH3EN = 0u;
507 SCU->DMAIEN.bit.DMACH4EN = 1u;
514 SCU->DMAIEN.bit.DMACH4EN = 0u;
521 SCU->DMAIEN.bit.DMACH5EN = 1u;
528 SCU->DMAIEN.bit.DMACH5EN = 0u;
535 SCU->DMAIEN.bit.DMACH6EN = 1u;
542 SCU->DMAIEN.bit.DMACH6EN = 0u;
549 SCU->DMAIEN.bit.DMACH7EN = 1u;
556 SCU->DMAIEN.bit.DMACH7EN = 0u;
563 SCU->DMAIEN.bit.DMATRERREN = 1u;
570 SCU->DMAIEN.bit.DMATRERREN = 0u;
579 return (
uint8)
SCU->DMAIS.bit.DMACH0;
588 return (
uint8)
SCU->DMAIS.bit.DMACH1;
597 return (
uint8)
SCU->DMAIS.bit.DMACH2;
606 return (
uint8)
SCU->DMAIS.bit.DMACH3;
615 return (
uint8)
SCU->DMAIS.bit.DMACH4;
624 return (
uint8)
SCU->DMAIS.bit.DMACH5;
633 return (
uint8)
SCU->DMAIS.bit.DMACH6;
642 return (
uint8)
SCU->DMAIS.bit.DMACH7;
649 SCU->DMAISC.bit.DMACH0CLR = 1u;
656 SCU->DMAISC.bit.DMACH1CLR = 1u;
663 SCU->DMAISC.bit.DMACH2CLR = 1u;
670 SCU->DMAISC.bit.DMACH3CLR = 1u;
677 SCU->DMAISC.bit.DMACH4CLR = 1u;
684 SCU->DMAISC.bit.DMACH5CLR = 1u;
691 SCU->DMAISC.bit.DMACH6CLR = 1u;
698 SCU->DMAISC.bit.DMACH7CLR = 1u;
INLINE void DMA_enCh3EndlessMode(void)
Enable DMA Channel 3 Endless Mode.
Definition: dma.h:379
INLINE uint8 DMA_getCh1IntSts(void)
Get DMA Channel 1 Interrupt Status.
Definition: dma.h:586
void DMA_setCh7IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 7 Interrupt Node Pointer.
void DMA_setCh2IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 2 Interrupt Node Pointer.
void DMA_setCh1IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 1 Interrupt Node Pointer.
INLINE uint8 DMA_getCh6IntSts(void)
Get DMA Channel 6 Interrupt Status.
Definition: dma.h:631
INLINE void DMA_enCh5Int(void)
Enable DMA Channel 5 Interrupt.
Definition: dma.h:519
INLINE void DMA_enCh2Int(void)
Enable DMA Channel 2 Interrupt.
Definition: dma.h:477
INLINE uint8 DMA_getCh2IntSts(void)
Get DMA Channel 2 Interrupt Status.
Definition: dma.h:595
enum DMA_incrementSize tDMA_incrementSize
INLINE void DMA_disErrInt(void)
Disable DMA Transfer Error Interrupt.
Definition: dma.h:568
INLINE void DMA_disCh3Int(void)
Disable DMA Channel 3 Interrupt.
Definition: dma.h:498
INLINE uint8 DMA_getCh3IntSts(void)
Get DMA Channel 3 Interrupt Status.
Definition: dma.h:604
INLINE void DMA_enCh4EndlessMode(void)
Enable DMA Channel 4 Endless Mode.
Definition: dma.h:393
enum DMA_transferSize tDMA_transferSize
INLINE void DMA_enCh4Int(void)
Enable DMA Channel 4 Interrupt.
Definition: dma.h:505
DMA_incrementSize
This enum lists the increment size options for the DMA.
Definition: dma.h:106
@ DMA_incrementSize_16bit
Definition: dma.h:108
@ DMA_incrementSize_32bit
Definition: dma.h:109
@ DMA_incrementSize_8bit
Definition: dma.h:107
enum DMA_incrementMode tDMA_incrementMode
INLINE void DMA_enCh6Int(void)
Enable DMA Channel 6 Interrupt.
Definition: dma.h:533
INLINE void DMA_clrCh1IntSts(void)
Clear DMA Channel 1 Interrupt Status.
Definition: dma.h:654
INLINE void DMA_disCh1EndlessMode(void)
Disable DMA Channel 1 Endless Mode.
Definition: dma.h:358
void DMA_setCh5IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 5 Interrupt Node Pointer.
INLINE void DMA_enCh1EndlessMode(void)
Enable DMA Channel 1 Endless Mode.
Definition: dma.h:351
void DMA_setMemSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Memory Scatter-Gather mode on a given task list.
Definition: dma.c:1208
void DMA_setErrIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel Bus Error Interrupt Node Pointer.
tDMA_entry * DMA_setTaskSctGth(tDMA_entry *s_entry, tDMA_cycleType e_cycleType, uint8 u8_Rpower, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a task to be used in the scatter-gather mode.
Definition: dma.c:1312
DMA_cycleType
This enum lists the cycle type options for the DMA.
Definition: dma.h:129
@ DMA_cycleType_PerSctGthPrim
Definition: dma.h:136
@ DMA_cycleType_Auto
Definition: dma.h:132
@ DMA_cycleType_Invalid
Definition: dma.h:130
@ DMA_cycleType_MemSctGthAlt
Definition: dma.h:135
@ DMA_cycleType_MemSctGthPrim
Definition: dma.h:134
@ DMA_cycleType_PingPong
Definition: dma.h:133
@ DMA_cycleType_PerSctGthAlt
Definition: dma.h:137
@ DMA_cycleType_Basic
Definition: dma.h:131
INLINE void DMA_disCh7EndlessMode(void)
Disable DMA Channel 7 Endless Mode.
Definition: dma.h:442
INLINE void DMA_disCh6EndlessMode(void)
Disable DMA Channel 6 Endless Mode.
Definition: dma.h:428
INLINE uint8 DMA_getCh0IntSts(void)
Get DMA Channel 0 Interrupt Status.
Definition: dma.h:577
INLINE void DMA_disCh5EndlessMode(void)
Disable DMA Channel 5 Endless Mode.
Definition: dma.h:414
void DMA_setCh3IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 3 Interrupt Node Pointer.
INLINE void DMA_disCh2Int(void)
Disable DMA Channel 2 Interrupt.
Definition: dma.h:484
INLINE void DMA_disCh2EndlessMode(void)
Disable DMA Channel 2 Endless Mode.
Definition: dma.h:372
DMA_incrementMode
This enum lists the increment mode options for the DMA.
Definition: dma.h:117
@ DMA_incrementMode_srcInc
Definition: dma.h:118
@ DMA_incrementMode_dstInc
Definition: dma.h:119
@ DMA_incrementMode_noInc
Definition: dma.h:121
@ DMA_incrementMode_srcDstInc
Definition: dma.h:120
INLINE void DMA_enCh2EndlessMode(void)
Enable DMA Channel 2 Endless Mode.
Definition: dma.h:365
INLINE void DMA_clrCh2IntSts(void)
Clear DMA Channel 2 Interrupt Status.
Definition: dma.h:661
void DMA_setPerSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
Definition: dma.c:1241
INLINE void DMA_enCh3Int(void)
Enable DMA Channel 3 Interrupt.
Definition: dma.h:491
INLINE void DMA_enCh0EndlessMode(void)
Enable DMA Channel 0 Endless Mode.
Definition: dma.h:337
void DMA_setCh6IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 6 Interrupt Node Pointer.
INLINE void DMA_enErrInt(void)
Enable DMA Transfer Error Interrupt.
Definition: dma.h:561
INLINE void DMA_enMaster(void)
Enable DMA Master.
Definition: dma.h:330
INLINE void DMA_disCh0EndlessMode(void)
Disable DMA Channel 0 Endless Mode.
Definition: dma.h:344
INLINE void DMA_clrCh0IntSts(void)
Clear DMA Channel 0 Interrupt Status.
Definition: dma.h:647
INLINE void DMA_enCh0Int(void)
Enable DMA Channel 0 Interrupt.
Definition: dma.h:449
INLINE void DMA_disCh4EndlessMode(void)
Disable DMA Channel 4 Endless Mode.
Definition: dma.h:400
INLINE void DMA_enCh7EndlessMode(void)
Enable DMA Channel 7 Endless Mode.
Definition: dma.h:435
INLINE void DMA_disCh5Int(void)
Disable DMA Channel 5 Interrupt.
Definition: dma.h:526
DMA_transferSize
This enum lists the transfer size options for the DMA.
Definition: dma.h:95
@ DMA_transferSize_8bit
Definition: dma.h:96
@ DMA_transferSize_32bit
Definition: dma.h:98
@ DMA_transferSize_16bit
Definition: dma.h:97
enum DMA_cycleType tDMA_cycleType
void DMA_setCh4IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 4 Interrupt Node Pointer.
INLINE void DMA_enCh5EndlessMode(void)
Enable DMA Channel 5 Endless Mode.
Definition: dma.h:407
INLINE uint8 DMA_getCh4IntSts(void)
Get DMA Channel 4 Interrupt Status.
Definition: dma.h:613
void DMA_resetChannel(uint8 u8_chIdx, uint32 u32_transferCnt)
Reset the primary structure in RAM for a given channel and rearm it.
Definition: dma.c:1191
INLINE uint8 DMA_getCh5IntSts(void)
Get DMA Channel 5 Interrupt Status.
Definition: dma.h:622
INLINE void DMA_enCh1Int(void)
Enable DMA Channel 1 Interrupt.
Definition: dma.h:463
INLINE void DMA_disCh6Int(void)
Disable DMA Channel 6 Interrupt.
Definition: dma.h:540
INLINE void DMA_clrCh6IntSts(void)
Clear DMA Channel 6 Interrupt Status.
Definition: dma.h:689
INLINE void DMA_enCh6EndlessMode(void)
Enable DMA Channel 6 Endless Mode.
Definition: dma.h:421
INLINE void DMA_disCh1Int(void)
Disable DMA Channel 1 Interrupt.
Definition: dma.h:470
tDMA_entry * DMA_setPrimaryTaskSctGth(tDMA_entry *s_primEntry, uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up the primary task to configure the scatter-gather mode.
Definition: dma.c:1279
struct DMA_entry tDMA_entry
INLINE uint8 DMA_getCh7IntSts(void)
Get DMA Channel 7 Interrupt Status.
Definition: dma.h:640
sint8 DMA_init(void)
Initialize the DMA structure in RAM and SFRs according to the ConfigWizard settings.
Definition: dma.c:701
INLINE void DMA_enCh7Int(void)
Enable DMA Channel 7 Interrupt.
Definition: dma.h:547
INLINE void DMA_disCh3EndlessMode(void)
Disable DMA Channel 3 Endless Mode.
Definition: dma.h:386
INLINE void DMA_clrCh5IntSts(void)
Clear DMA Channel 5 Interrupt Status.
Definition: dma.h:682
INLINE void DMA_disCh7Int(void)
Disable DMA Channel 7 Interrupt.
Definition: dma.h:554
void DMA_setCh0IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 0 Interrupt Node Pointer.
void DMA_setBasicTransfer(uint8 u8_chIdx, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a basic transfer for the desired DMA channel in the primary structure in RAM.
Definition: dma.c:1101
INLINE void DMA_setSWReq(uint8 u8_chIdx)
Sets the SW request for the given channel.
Definition: dma.h:704
INLINE void DMA_disCh4Int(void)
Disable DMA Channel 4 Interrupt.
Definition: dma.h:512
INLINE void DMA_clrCh7IntSts(void)
Clear DMA Channel 7 Interrupt Status.
Definition: dma.h:696
INLINE void DMA_disCh0Int(void)
Disable DMA Channel 0 Interrupt.
Definition: dma.h:456
INLINE void DMA_clrCh3IntSts(void)
Clear DMA Channel 3 Interrupt Status.
Definition: dma.h:668
INLINE void DMA_clrCh4IntSts(void)
Clear DMA Channel 4 Interrupt Status.
Definition: dma.h:675
#define DMA
Definition: tle989x.h:24069
#define SCU
Definition: tle989x.h:24075
__attribute__((noreturn))
Definition: startup_tle989x.c:208
uint32 u32_srcEndPtr
Definition: dma.h:166
tDMA_ctrl s_ctrl
Definition: dma.h:168
uint32 reserved
Definition: dma.h:169
uint32 u32_dstEndPtr
Definition: dma.h:167
This structure lists the DMA transfer memory locations.
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:167
uint8_t uint8
8 bit unsigned value
Definition: types.h:220
int8_t sint8
8 bit signed value
Definition: types.h:225
uint32_t uint32
32 bit unsigned value
Definition: types.h:222
This union and its structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:144
uint32 u32_cycleCtrl
Bit[2..0].
Definition: dma.h:148
uint32 u32_srcSize
Bit[25..24].
Definition: dma.h:154
uint32 u32_nextUseburst
Bit[3].
Definition: dma.h:149
uint32 u32_dstInc
Bit[31..30].
Definition: dma.h:157
uint32 u32_srcProtCtrl
Bit[20..18].
Definition: dma.h:152
uint32 u32_srcInc
Bit[27..26].
Definition: dma.h:155
uint32 u32_Rpower
Bit[17..14].
Definition: dma.h:151
uint32 u32_dstProtCtrl
Bit[23..21].
Definition: dma.h:153
uint32 u32_Nminus1
Bit[13..4].
Definition: dma.h:150
uint32 u32_dstSize
Bit[29..28].
Definition: dma.h:156
uint32 reg
Definition: dma.h:145