Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
dma.h
Go to the documentation of this file.
1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** BG Blandine Guillot **
45 ** JO Julia Ott **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.1.0: 2021-03-03, BG: Initial version **
52 ** V0.2.0: 2021-06-08, BG: EP-685: Replaced UC_RAM_SIZE with UC_DSRAM_SIZE **
53 ** V0.2.1: 2021-06-14, BG: EP-685: Added functions for the endless mode **
54 ** V0.2.2: 2021-06-21, BG: EP-685: Updated init function with return code **
55 ** V0.2.3: 2021-07-30, BG: EP-877: Corrected MISRA 2012 errors **
56 ** V0.2.4: 2021-08-11, BG: EP-905: Added missing scu_defines.h **
57 ** V0.2.5: 2021-08-16, JO: EP-860: Added variable u32p_DMA_entriesForTest **
58 ** for unit testing **
59 ** V0.2.6: 2021-09-07, BG: EP-922: Added support for ARMCC V5 **
60 ** V0.2.7: 2021-11-12, JO: EP-937: Updated copyright and branding **
61 ** V0.2.8: 2022-04-27, JO: EP-1139: Corrected doxygen errors/warnings **
62 ** V0.2.9: 2022-06-22, JO: EP-1146: Added initialization of SCU->DMACTRL **
63 ** and DMA->DMA_CFG.bit.MASTER_ENABLE **
64 ** V0.3.0: 2022-06-23, JO: EP-1157: Added function DMA_setSWReq **
65 ** V0.3.1: 2022-06-23, JO: EP-1150: Removed ARMCC V6.18 warnings **
66 ** V0.3.2: 2022-11-17, JO: EP-1342: Updated enum documentation to remove **
67 ** doxygen warning **
68 *******************************************************************************/
69 
70 #ifndef _DMA_H
71 #define _DMA_H
72 
73 /*******************************************************************************
74 ** Includes **
75 *******************************************************************************/
76 
77 #include "types.h"
78 #include "tle989x.h"
79 #include "tle_variants.h"
80 #include "dma_defines.h"
81 
82 /*******************************************************************************
83 ** Global Constant Declarations **
84 *******************************************************************************/
85 
86 /*******************************************************************************
87 ** Global Type Declarations **
88 *******************************************************************************/
89 
94 typedef enum DMA_transferSize
95 {
100 
105 typedef enum DMA_incrementSize
106 {
111 
116 typedef enum DMA_incrementMode
117 {
123 
128 typedef enum DMA_cycleType
129 {
139 
143 typedef union
144 {
146  struct
147  {
158  } bit;
159 } tDMA_ctrl;
160 
164 typedef struct DMA_entry
165 {
171 
172 /*******************************************************************************
173 ** Global Macro Declarations **
174 *******************************************************************************/
175 
177 #define DMA_CH0 (0u)
179 #define DMA_CH1 (1u)
181 #define DMA_CH2 (2u)
183 #define DMA_CH3 (3u)
185 #define DMA_CH4 (4u)
187 #define DMA_CH5 (5u)
189 #define DMA_CH6 (6u)
191 #define DMA_CH7 (7u)
192 
194 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
196 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
198 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
200 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
202 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
204 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
206 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
208 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
209 
210 
211 /*******************************************************************************
212 ** Global Function Declarations **
213 *******************************************************************************/
214 
215 sint8 DMA_init(void);
216 void DMA_setBasicTransfer(uint8 u8_chIdx, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode);
217 void DMA_resetChannel(uint8 u8_chIdx, uint32 u32_transferCnt);
218 void DMA_setMemSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt);
219 void DMA_setPerSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt);
220 tDMA_entry *DMA_setPrimaryTaskSctGth(tDMA_entry *s_primEntry, uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt);
221 tDMA_entry *DMA_setTaskSctGth(tDMA_entry *s_entry, tDMA_cycleType e_cycleType, uint8 u8_Rpower, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode);
222 INLINE void DMA_enMaster(void);
223 INLINE void DMA_enCh0EndlessMode(void);
224 INLINE void DMA_disCh0EndlessMode(void);
225 INLINE void DMA_enCh1EndlessMode(void);
226 INLINE void DMA_disCh1EndlessMode(void);
227 INLINE void DMA_enCh2EndlessMode(void);
228 INLINE void DMA_disCh2EndlessMode(void);
229 INLINE void DMA_enCh3EndlessMode(void);
230 INLINE void DMA_disCh3EndlessMode(void);
231 INLINE void DMA_enCh4EndlessMode(void);
232 INLINE void DMA_disCh4EndlessMode(void);
233 INLINE void DMA_enCh5EndlessMode(void);
234 INLINE void DMA_disCh5EndlessMode(void);
235 INLINE void DMA_enCh6EndlessMode(void);
236 INLINE void DMA_disCh6EndlessMode(void);
237 INLINE void DMA_enCh7EndlessMode(void);
238 INLINE void DMA_disCh7EndlessMode(void);
239 INLINE void DMA_enCh0Int(void);
240 INLINE void DMA_disCh0Int(void);
241 INLINE void DMA_enCh1Int(void);
242 INLINE void DMA_disCh1Int(void);
243 INLINE void DMA_enCh2Int(void);
244 INLINE void DMA_disCh2Int(void);
245 INLINE void DMA_enCh3Int(void);
246 INLINE void DMA_disCh3Int(void);
247 INLINE void DMA_enCh4Int(void);
248 INLINE void DMA_disCh4Int(void);
249 INLINE void DMA_enCh5Int(void);
250 INLINE void DMA_disCh5Int(void);
251 INLINE void DMA_enCh6Int(void);
252 INLINE void DMA_disCh6Int(void);
253 INLINE void DMA_enCh7Int(void);
254 INLINE void DMA_disCh7Int(void);
255 INLINE void DMA_enErrInt(void);
256 INLINE void DMA_disErrInt(void);
265 INLINE void DMA_clrCh0IntSts(void);
266 INLINE void DMA_clrCh1IntSts(void);
267 INLINE void DMA_clrCh2IntSts(void);
268 INLINE void DMA_clrCh3IntSts(void);
269 INLINE void DMA_clrCh4IntSts(void);
270 INLINE void DMA_clrCh5IntSts(void);
271 INLINE void DMA_clrCh6IntSts(void);
272 INLINE void DMA_clrCh7IntSts(void);
273 INLINE void DMA_setSWReq(uint8 u8_chIdx);
274 
275 /*******************************************************************************
276 ** Deprecated Function Declarations **
277 *******************************************************************************/
278 
282 void DMA_setCh0IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
283 
287 void DMA_setCh1IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
288 
292 void DMA_setCh2IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
293 
297 void DMA_setCh3IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
298 
302 void DMA_setCh4IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
303 
307 void DMA_setCh5IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
308 
312 void DMA_setCh6IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
313 
317 void DMA_setCh7IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
318 
322 void DMA_setErrIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
323 
324 /*******************************************************************************
325 ** Global Inline Function Definitions **
326 *******************************************************************************/
327 
331 {
332  DMA->DMA_CFG.bit.MASTER_ENABLE = 1u;
333 }
334 
338 {
339  SCU->DMACTRL.bit.DEMEN_CH0 = 1u;
340 }
341 
345 {
346  SCU->DMACTRL.bit.DEMEN_CH0 = 0u;
347 }
348 
352 {
353  SCU->DMACTRL.bit.DEMEN_CH1 = 1u;
354 }
355 
359 {
360  SCU->DMACTRL.bit.DEMEN_CH1 = 0u;
361 }
362 
366 {
367  SCU->DMACTRL.bit.DEMEN_CH2 = 1u;
368 }
369 
373 {
374  SCU->DMACTRL.bit.DEMEN_CH2 = 0u;
375 }
376 
380 {
381  SCU->DMACTRL.bit.DEMEN_CH3 = 1u;
382 }
383 
387 {
388  SCU->DMACTRL.bit.DEMEN_CH3 = 0u;
389 }
390 
394 {
395  SCU->DMACTRL.bit.DEMEN_CH4 = 1u;
396 }
397 
401 {
402  SCU->DMACTRL.bit.DEMEN_CH4 = 0u;
403 }
404 
408 {
409  SCU->DMACTRL.bit.DEMEN_CH5 = 1u;
410 }
411 
415 {
416  SCU->DMACTRL.bit.DEMEN_CH5 = 0u;
417 }
418 
422 {
423  SCU->DMACTRL.bit.DEMEN_CH6 = 1u;
424 }
425 
429 {
430  SCU->DMACTRL.bit.DEMEN_CH6 = 0u;
431 }
432 
436 {
437  SCU->DMACTRL.bit.DEMEN_CH7 = 1u;
438 }
439 
443 {
444  SCU->DMACTRL.bit.DEMEN_CH7 = 0u;
445 }
446 
450 {
451  SCU->DMAIEN.bit.DMACH0EN = 1u;
452 }
453 
457 {
458  SCU->DMAIEN.bit.DMACH0EN = 0u;
459 }
460 
464 {
465  SCU->DMAIEN.bit.DMACH1EN = 1u;
466 }
467 
471 {
472  SCU->DMAIEN.bit.DMACH1EN = 0u;
473 }
474 
478 {
479  SCU->DMAIEN.bit.DMACH2EN = 1u;
480 }
481 
485 {
486  SCU->DMAIEN.bit.DMACH2EN = 0u;
487 }
488 
492 {
493  SCU->DMAIEN.bit.DMACH3EN = 1u;
494 }
495 
499 {
500  SCU->DMAIEN.bit.DMACH3EN = 0u;
501 }
502 
506 {
507  SCU->DMAIEN.bit.DMACH4EN = 1u;
508 }
509 
513 {
514  SCU->DMAIEN.bit.DMACH4EN = 0u;
515 }
516 
520 {
521  SCU->DMAIEN.bit.DMACH5EN = 1u;
522 }
523 
527 {
528  SCU->DMAIEN.bit.DMACH5EN = 0u;
529 }
530 
534 {
535  SCU->DMAIEN.bit.DMACH6EN = 1u;
536 }
537 
541 {
542  SCU->DMAIEN.bit.DMACH6EN = 0u;
543 }
544 
548 {
549  SCU->DMAIEN.bit.DMACH7EN = 1u;
550 }
551 
555 {
556  SCU->DMAIEN.bit.DMACH7EN = 0u;
557 }
558 
562 {
563  SCU->DMAIEN.bit.DMATRERREN = 1u;
564 }
565 
569 {
570  SCU->DMAIEN.bit.DMATRERREN = 0u;
571 }
572 
578 {
579  return (uint8)SCU->DMAIS.bit.DMACH0;
580 }
581 
587 {
588  return (uint8)SCU->DMAIS.bit.DMACH1;
589 }
590 
596 {
597  return (uint8)SCU->DMAIS.bit.DMACH2;
598 }
599 
605 {
606  return (uint8)SCU->DMAIS.bit.DMACH3;
607 }
608 
614 {
615  return (uint8)SCU->DMAIS.bit.DMACH4;
616 }
617 
623 {
624  return (uint8)SCU->DMAIS.bit.DMACH5;
625 }
626 
632 {
633  return (uint8)SCU->DMAIS.bit.DMACH6;
634 }
635 
641 {
642  return (uint8)SCU->DMAIS.bit.DMACH7;
643 }
644 
648 {
649  SCU->DMAISC.bit.DMACH0CLR = 1u;
650 }
651 
655 {
656  SCU->DMAISC.bit.DMACH1CLR = 1u;
657 }
658 
662 {
663  SCU->DMAISC.bit.DMACH2CLR = 1u;
664 }
665 
669 {
670  SCU->DMAISC.bit.DMACH3CLR = 1u;
671 }
672 
676 {
677  SCU->DMAISC.bit.DMACH4CLR = 1u;
678 }
679 
683 {
684  SCU->DMAISC.bit.DMACH5CLR = 1u;
685 }
686 
690 {
691  SCU->DMAISC.bit.DMACH6CLR = 1u;
692 }
693 
697 {
698  SCU->DMAISC.bit.DMACH7CLR = 1u;
699 }
704 INLINE void DMA_setSWReq(uint8 u8_chIdx)
705 {
706  DMA->CHNL_SW_REQUEST.reg = (uint32)((uint32)1u << u8_chIdx);
707 }
708 
709 #endif /* _DMA_H */
INLINE void DMA_enCh3EndlessMode(void)
Enable DMA Channel 3 Endless Mode.
Definition: dma.h:379
INLINE uint8 DMA_getCh1IntSts(void)
Get DMA Channel 1 Interrupt Status.
Definition: dma.h:586
void DMA_setCh7IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 7 Interrupt Node Pointer.
void DMA_setCh2IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 2 Interrupt Node Pointer.
void DMA_setCh1IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 1 Interrupt Node Pointer.
INLINE uint8 DMA_getCh6IntSts(void)
Get DMA Channel 6 Interrupt Status.
Definition: dma.h:631
INLINE void DMA_enCh5Int(void)
Enable DMA Channel 5 Interrupt.
Definition: dma.h:519
INLINE void DMA_enCh2Int(void)
Enable DMA Channel 2 Interrupt.
Definition: dma.h:477
INLINE uint8 DMA_getCh2IntSts(void)
Get DMA Channel 2 Interrupt Status.
Definition: dma.h:595
enum DMA_incrementSize tDMA_incrementSize
INLINE void DMA_disErrInt(void)
Disable DMA Transfer Error Interrupt.
Definition: dma.h:568
INLINE void DMA_disCh3Int(void)
Disable DMA Channel 3 Interrupt.
Definition: dma.h:498
INLINE uint8 DMA_getCh3IntSts(void)
Get DMA Channel 3 Interrupt Status.
Definition: dma.h:604
INLINE void DMA_enCh4EndlessMode(void)
Enable DMA Channel 4 Endless Mode.
Definition: dma.h:393
enum DMA_transferSize tDMA_transferSize
INLINE void DMA_enCh4Int(void)
Enable DMA Channel 4 Interrupt.
Definition: dma.h:505
DMA_incrementSize
This enum lists the increment size options for the DMA.
Definition: dma.h:106
@ DMA_incrementSize_16bit
Definition: dma.h:108
@ DMA_incrementSize_32bit
Definition: dma.h:109
@ DMA_incrementSize_8bit
Definition: dma.h:107
enum DMA_incrementMode tDMA_incrementMode
INLINE void DMA_enCh6Int(void)
Enable DMA Channel 6 Interrupt.
Definition: dma.h:533
INLINE void DMA_clrCh1IntSts(void)
Clear DMA Channel 1 Interrupt Status.
Definition: dma.h:654
INLINE void DMA_disCh1EndlessMode(void)
Disable DMA Channel 1 Endless Mode.
Definition: dma.h:358
void DMA_setCh5IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 5 Interrupt Node Pointer.
INLINE void DMA_enCh1EndlessMode(void)
Enable DMA Channel 1 Endless Mode.
Definition: dma.h:351
void DMA_setMemSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Memory Scatter-Gather mode on a given task list.
Definition: dma.c:1208
void DMA_setErrIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel Bus Error Interrupt Node Pointer.
tDMA_entry * DMA_setTaskSctGth(tDMA_entry *s_entry, tDMA_cycleType e_cycleType, uint8 u8_Rpower, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a task to be used in the scatter-gather mode.
Definition: dma.c:1312
DMA_cycleType
This enum lists the cycle type options for the DMA.
Definition: dma.h:129
@ DMA_cycleType_PerSctGthPrim
Definition: dma.h:136
@ DMA_cycleType_Auto
Definition: dma.h:132
@ DMA_cycleType_Invalid
Definition: dma.h:130
@ DMA_cycleType_MemSctGthAlt
Definition: dma.h:135
@ DMA_cycleType_MemSctGthPrim
Definition: dma.h:134
@ DMA_cycleType_PingPong
Definition: dma.h:133
@ DMA_cycleType_PerSctGthAlt
Definition: dma.h:137
@ DMA_cycleType_Basic
Definition: dma.h:131
INLINE void DMA_disCh7EndlessMode(void)
Disable DMA Channel 7 Endless Mode.
Definition: dma.h:442
INLINE void DMA_disCh6EndlessMode(void)
Disable DMA Channel 6 Endless Mode.
Definition: dma.h:428
INLINE uint8 DMA_getCh0IntSts(void)
Get DMA Channel 0 Interrupt Status.
Definition: dma.h:577
INLINE void DMA_disCh5EndlessMode(void)
Disable DMA Channel 5 Endless Mode.
Definition: dma.h:414
void DMA_setCh3IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 3 Interrupt Node Pointer.
INLINE void DMA_disCh2Int(void)
Disable DMA Channel 2 Interrupt.
Definition: dma.h:484
INLINE void DMA_disCh2EndlessMode(void)
Disable DMA Channel 2 Endless Mode.
Definition: dma.h:372
DMA_incrementMode
This enum lists the increment mode options for the DMA.
Definition: dma.h:117
@ DMA_incrementMode_srcInc
Definition: dma.h:118
@ DMA_incrementMode_dstInc
Definition: dma.h:119
@ DMA_incrementMode_noInc
Definition: dma.h:121
@ DMA_incrementMode_srcDstInc
Definition: dma.h:120
INLINE void DMA_enCh2EndlessMode(void)
Enable DMA Channel 2 Endless Mode.
Definition: dma.h:365
INLINE void DMA_clrCh2IntSts(void)
Clear DMA Channel 2 Interrupt Status.
Definition: dma.h:661
void DMA_setPerSctGth(uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
Definition: dma.c:1241
INLINE void DMA_enCh3Int(void)
Enable DMA Channel 3 Interrupt.
Definition: dma.h:491
INLINE void DMA_enCh0EndlessMode(void)
Enable DMA Channel 0 Endless Mode.
Definition: dma.h:337
void DMA_setCh6IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 6 Interrupt Node Pointer.
INLINE void DMA_enErrInt(void)
Enable DMA Transfer Error Interrupt.
Definition: dma.h:561
INLINE void DMA_enMaster(void)
Enable DMA Master.
Definition: dma.h:330
INLINE void DMA_disCh0EndlessMode(void)
Disable DMA Channel 0 Endless Mode.
Definition: dma.h:344
INLINE void DMA_clrCh0IntSts(void)
Clear DMA Channel 0 Interrupt Status.
Definition: dma.h:647
INLINE void DMA_enCh0Int(void)
Enable DMA Channel 0 Interrupt.
Definition: dma.h:449
INLINE void DMA_disCh4EndlessMode(void)
Disable DMA Channel 4 Endless Mode.
Definition: dma.h:400
INLINE void DMA_enCh7EndlessMode(void)
Enable DMA Channel 7 Endless Mode.
Definition: dma.h:435
INLINE void DMA_disCh5Int(void)
Disable DMA Channel 5 Interrupt.
Definition: dma.h:526
DMA_transferSize
This enum lists the transfer size options for the DMA.
Definition: dma.h:95
@ DMA_transferSize_8bit
Definition: dma.h:96
@ DMA_transferSize_32bit
Definition: dma.h:98
@ DMA_transferSize_16bit
Definition: dma.h:97
enum DMA_cycleType tDMA_cycleType
void DMA_setCh4IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 4 Interrupt Node Pointer.
INLINE void DMA_enCh5EndlessMode(void)
Enable DMA Channel 5 Endless Mode.
Definition: dma.h:407
INLINE uint8 DMA_getCh4IntSts(void)
Get DMA Channel 4 Interrupt Status.
Definition: dma.h:613
void DMA_resetChannel(uint8 u8_chIdx, uint32 u32_transferCnt)
Reset the primary structure in RAM for a given channel and rearm it.
Definition: dma.c:1191
INLINE uint8 DMA_getCh5IntSts(void)
Get DMA Channel 5 Interrupt Status.
Definition: dma.h:622
INLINE void DMA_enCh1Int(void)
Enable DMA Channel 1 Interrupt.
Definition: dma.h:463
INLINE void DMA_disCh6Int(void)
Disable DMA Channel 6 Interrupt.
Definition: dma.h:540
INLINE void DMA_clrCh6IntSts(void)
Clear DMA Channel 6 Interrupt Status.
Definition: dma.h:689
INLINE void DMA_enCh6EndlessMode(void)
Enable DMA Channel 6 Endless Mode.
Definition: dma.h:421
INLINE void DMA_disCh1Int(void)
Disable DMA Channel 1 Interrupt.
Definition: dma.h:470
tDMA_entry * DMA_setPrimaryTaskSctGth(tDMA_entry *s_primEntry, uint8 u8_chIdx, tDMA_entry *s_taskList, uint32 u32_taskCnt)
Set up the primary task to configure the scatter-gather mode.
Definition: dma.c:1279
struct DMA_entry tDMA_entry
INLINE uint8 DMA_getCh7IntSts(void)
Get DMA Channel 7 Interrupt Status.
Definition: dma.h:640
sint8 DMA_init(void)
Initialize the DMA structure in RAM and SFRs according to the ConfigWizard settings.
Definition: dma.c:701
INLINE void DMA_enCh7Int(void)
Enable DMA Channel 7 Interrupt.
Definition: dma.h:547
INLINE void DMA_disCh3EndlessMode(void)
Disable DMA Channel 3 Endless Mode.
Definition: dma.h:386
INLINE void DMA_clrCh5IntSts(void)
Clear DMA Channel 5 Interrupt Status.
Definition: dma.h:682
INLINE void DMA_disCh7Int(void)
Disable DMA Channel 7 Interrupt.
Definition: dma.h:554
void DMA_setCh0IntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set Channel 0 Interrupt Node Pointer.
void DMA_setBasicTransfer(uint8 u8_chIdx, uint32 u32_srcAddr, uint32 u32_dstAddr, uint32 u32_transferCnt, tDMA_transferSize e_transferSize, tDMA_incrementMode e_incrementMode)
Set up a basic transfer for the desired DMA channel in the primary structure in RAM.
Definition: dma.c:1101
INLINE void DMA_setSWReq(uint8 u8_chIdx)
Sets the SW request for the given channel.
Definition: dma.h:704
INLINE void DMA_disCh4Int(void)
Disable DMA Channel 4 Interrupt.
Definition: dma.h:512
INLINE void DMA_clrCh7IntSts(void)
Clear DMA Channel 7 Interrupt Status.
Definition: dma.h:696
INLINE void DMA_disCh0Int(void)
Disable DMA Channel 0 Interrupt.
Definition: dma.h:456
INLINE void DMA_clrCh3IntSts(void)
Clear DMA Channel 3 Interrupt Status.
Definition: dma.h:668
INLINE void DMA_clrCh4IntSts(void)
Clear DMA Channel 4 Interrupt Status.
Definition: dma.h:675
#define DMA
Definition: tle989x.h:24069
#define SCU
Definition: tle989x.h:24075
__attribute__((noreturn))
Definition: startup_tle989x.c:208
Definition: dma.h:165
uint32 u32_srcEndPtr
Definition: dma.h:166
tDMA_ctrl s_ctrl
Definition: dma.h:168
uint32 reserved
Definition: dma.h:169
uint32 u32_dstEndPtr
Definition: dma.h:167
This structure lists the DMA transfer memory locations.
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:167
uint8_t uint8
8 bit unsigned value
Definition: types.h:220
int8_t sint8
8 bit signed value
Definition: types.h:225
uint32_t uint32
32 bit unsigned value
Definition: types.h:222
This union and its structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:144
uint32 u32_cycleCtrl
Bit[2..0].
Definition: dma.h:148
uint32 u32_srcSize
Bit[25..24].
Definition: dma.h:154
uint32 u32_nextUseburst
Bit[3].
Definition: dma.h:149
uint32 u32_dstInc
Bit[31..30].
Definition: dma.h:157
uint32 u32_srcProtCtrl
Bit[20..18].
Definition: dma.h:152
uint32 u32_srcInc
Bit[27..26].
Definition: dma.h:155
uint32 u32_Rpower
Bit[17..14].
Definition: dma.h:151
uint32 u32_dstProtCtrl
Bit[23..21].
Definition: dma.h:153
uint32 u32_Nminus1
Bit[13..4].
Definition: dma.h:150
uint32 u32_dstSize
Bit[29..28].
Definition: dma.h:156
uint32 reg
Definition: dma.h:145