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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
|
ADC2 (ADC2)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EN: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t ISTE: 1 | |
uint32_t __pad1__: 29 | |
} bit | |
} | GLOBCONF |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CLKDIV: 4 | |
uint32_t __pad0__: 28 | |
} bit | |
} | CLKCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SUSEN: 1 | |
__IOM uint32_t SUSMOD: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | SUSCTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t STAT: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | SUSSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0: 1 | |
__IOM uint32_t SQ1: 1 | |
__IOM uint32_t SQ2: 1 | |
__IOM uint32_t SQ3: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t COLL0: 1 | |
__IOM uint32_t COLL1: 1 | |
__IOM uint32_t COLL2: 1 | |
__IOM uint32_t COLL3: 1 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t SQNUM: 3 | |
uint32_t __pad2__: 13 | |
} bit | |
} | SQSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0CLR: 1 | |
__IOM uint32_t SQ1CLR: 1 | |
__IOM uint32_t SQ2CLR: 1 | |
__IOM uint32_t SQ3CLR: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t COLL0CLR: 1 | |
__IOM uint32_t COLL1CLR: 1 | |
__IOM uint32_t COLL2CLR: 1 | |
__IOM uint32_t COLL3CLR: 1 | |
uint32_t __pad1__: 20 | |
} bit | |
} | SQSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0SET: 1 | |
__IOM uint32_t SQ1SET: 1 | |
__IOM uint32_t SQ2SET: 1 | |
__IOM uint32_t SQ3SET: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t COLL0SET: 1 | |
__IOM uint32_t COLL1SET: 1 | |
__IOM uint32_t COLL2SET: 1 | |
__IOM uint32_t COLL3SET: 1 | |
uint32_t __pad1__: 20 | |
} bit | |
} | SQSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CH0: 1 | |
__IOM uint32_t CH1: 1 | |
__IOM uint32_t CH2: 1 | |
__IOM uint32_t CH3: 1 | |
__IOM uint32_t CH4: 1 | |
__IOM uint32_t CH5: 1 | |
__IOM uint32_t CH6: 1 | |
__IOM uint32_t CH7: 1 | |
__IOM uint32_t CH8: 1 | |
__IOM uint32_t CH9: 1 | |
__IOM uint32_t CH10: 1 | |
__IOM uint32_t CH11: 1 | |
__IOM uint32_t CH12: 1 | |
__IOM uint32_t CH13: 1 | |
__IOM uint32_t CH14: 1 | |
uint32_t __pad0__: 9 | |
__IOM uint32_t CHNUM: 4 | |
uint32_t __pad1__: 4 | |
} bit | |
} | CHSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CH0CLR: 1 | |
__OM uint32_t CH1CLR: 1 | |
__OM uint32_t CH2CLR: 1 | |
__OM uint32_t CH3CLR: 1 | |
__OM uint32_t CH4CLR: 1 | |
__OM uint32_t CH5CLR: 1 | |
__OM uint32_t CH6CLR: 1 | |
__OM uint32_t CH7CLR: 1 | |
__OM uint32_t CH8CLR: 1 | |
__OM uint32_t CH9CLR: 1 | |
__OM uint32_t CH10CLR: 1 | |
__OM uint32_t CH11CLR: 1 | |
__OM uint32_t CH12CLR: 1 | |
__OM uint32_t CH13CLR: 1 | |
__OM uint32_t CH14CLR: 1 | |
uint32_t __pad0__: 17 | |
} bit | |
} | CHSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CH0SET: 1 | |
__OM uint32_t CH1SET: 1 | |
__OM uint32_t CH2SET: 1 | |
__OM uint32_t CH3SET: 1 | |
__OM uint32_t CH4SET: 1 | |
__OM uint32_t CH5SET: 1 | |
__OM uint32_t CH6SET: 1 | |
__OM uint32_t CH7SET: 1 | |
__OM uint32_t CH8SET: 1 | |
__OM uint32_t CH9SET: 1 | |
__OM uint32_t CH10SET: 1 | |
__OM uint32_t CH11SET: 1 | |
__OM uint32_t CH12SET: 1 | |
__OM uint32_t CH13SET: 1 | |
__OM uint32_t CH14SET: 1 | |
uint32_t __pad0__: 17 | |
} bit | |
} | CHSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALEN0: 1 | |
__IOM uint32_t CALEN1: 1 | |
__IOM uint32_t CALEN2: 1 | |
__IOM uint32_t CALEN3: 1 | |
__IOM uint32_t CALEN4: 1 | |
__IOM uint32_t CALEN5: 1 | |
__IOM uint32_t CALEN6: 1 | |
__IOM uint32_t CALEN7: 1 | |
__IOM uint32_t CALEN8: 1 | |
__IOM uint32_t CALEN9: 1 | |
__IOM uint32_t CALEN10: 1 | |
__IOM uint32_t CALEN11: 1 | |
__IOM uint32_t CALEN12: 1 | |
__IOM uint32_t CALEN13: 1 | |
__IOM uint32_t CALEN14: 1 | |
uint32_t __pad0__: 17 | |
} bit | |
} | CALEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALPEN0: 1 | |
__IOM uint32_t CALPEN1: 1 | |
__IOM uint32_t CALPEN2: 1 | |
__IOM uint32_t CALPEN3: 1 | |
__IOM uint32_t CALPEN4: 1 | |
__IOM uint32_t CALPEN5: 1 | |
__IOM uint32_t CALPEN6: 1 | |
__IOM uint32_t CALPEN7: 1 | |
__IOM uint32_t CALPEN8: 1 | |
__IOM uint32_t CALPEN9: 1 | |
__IOM uint32_t CALPEN10: 1 | |
__IOM uint32_t CALPEN11: 1 | |
__IOM uint32_t CALPEN12: 1 | |
__IOM uint32_t CALPEN13: 1 | |
__IOM uint32_t CALPEN14: 1 | |
uint32_t __pad0__: 17 | |
} bit | |
} | CALPEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL2 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL3 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL4 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL5 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL6 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | FIL7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t FIL0: 1 | |
__IOM uint32_t FIL1: 1 | |
__IOM uint32_t FIL2: 1 | |
__IOM uint32_t FIL3: 1 | |
__IOM uint32_t FIL4: 1 | |
__IOM uint32_t FIL5: 1 | |
__IOM uint32_t FIL6: 1 | |
__IOM uint32_t FIL7: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | FILSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t FIL0CLR: 1 | |
__OM uint32_t FIL1CLR: 1 | |
__OM uint32_t FIL2CLR: 1 | |
__OM uint32_t FIL3CLR: 1 | |
__OM uint32_t FIL4CLR: 1 | |
__OM uint32_t FIL5CLR: 1 | |
__OM uint32_t FIL6CLR: 1 | |
__OM uint32_t FIL7CLR: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | FILSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t FIL0SET: 1 | |
__OM uint32_t FIL1SET: 1 | |
__OM uint32_t FIL2SET: 1 | |
__OM uint32_t FIL3SET: 1 | |
__OM uint32_t FIL4SET: 1 | |
__OM uint32_t FIL5SET: 1 | |
__OM uint32_t FIL6SET: 1 | |
__OM uint32_t FIL7SET: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | FILSTATSET |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES2 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES3 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES4 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES5 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES6 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES7 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES8 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES9 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES10 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES11 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES12 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES13 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 12 | |
uint32_t __pad0__: 3 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CMP_LO0_STS: 1 | |
__IOM uint32_t CMP_LO1_STS: 1 | |
__IOM uint32_t CMP_LO2_STS: 1 | |
__IOM uint32_t CMP_LO3_STS: 1 | |
__IOM uint32_t CMP_LO4_STS: 1 | |
__IOM uint32_t CMP_LO5_STS: 1 | |
__IOM uint32_t CMP_LO6_STS: 1 | |
__IOM uint32_t CMP_LO7_STS: 1 | |
__IOM uint32_t CMP_LO0_IS: 1 | |
__IOM uint32_t CMP_LO1_IS: 1 | |
__IOM uint32_t CMP_LO2_IS: 1 | |
__IOM uint32_t CMP_LO3_IS: 1 | |
__IOM uint32_t CMP_LO4_IS: 1 | |
__IOM uint32_t CMP_LO5_IS: 1 | |
__IOM uint32_t CMP_LO6_IS: 1 | |
__IOM uint32_t CMP_LO7_IS: 1 | |
__IOM uint32_t CMP_UP0_STS: 1 | |
__IOM uint32_t CMP_UP1_STS: 1 | |
__IOM uint32_t CMP_UP2_STS: 1 | |
__IOM uint32_t CMP_UP3_STS: 1 | |
__IOM uint32_t CMP_UP4_STS: 1 | |
__IOM uint32_t CMP_UP5_STS: 1 | |
__IOM uint32_t CMP_UP6_STS: 1 | |
__IOM uint32_t CMP_UP7_STS: 1 | |
__IOM uint32_t CMP_UP0_IS: 1 | |
__IOM uint32_t CMP_UP1_IS: 1 | |
__IOM uint32_t CMP_UP2_IS: 1 | |
__IOM uint32_t CMP_UP3_IS: 1 | |
__IOM uint32_t CMP_UP4_IS: 1 | |
__IOM uint32_t CMP_UP5_IS: 1 | |
__IOM uint32_t CMP_UP6_IS: 1 | |
__IOM uint32_t CMP_UP7_IS: 1 | |
} bit | |
} | CMPSTAT |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t CMP_LO0_STSCLR: 1 | |
__OM uint32_t CMP_LO1_STSCLR: 1 | |
__OM uint32_t CMP_LO2_STSCLR: 1 | |
__OM uint32_t CMP_LO3_STSCLR: 1 | |
__OM uint32_t CMP_LO4_STSCLR: 1 | |
__OM uint32_t CMP_LO5_STSCLR: 1 | |
__OM uint32_t CMP_LO6_STSCLR: 1 | |
__OM uint32_t CMP_LO7_STSCLR: 1 | |
__OM uint32_t CMP_LO0_ISCLR: 1 | |
__OM uint32_t CMP_LO1_ISCLR: 1 | |
__OM uint32_t CMP_LO2_ISCLR: 1 | |
__OM uint32_t CMP_LO3_ISCLR: 1 | |
__OM uint32_t CMP_LO4_ISCLR: 1 | |
__OM uint32_t CMP_LO5_ISCLR: 1 | |
__OM uint32_t CMP_LO6_ISCLR: 1 | |
__OM uint32_t CMP_LO7_ISCLR: 1 | |
__OM uint32_t CMP_UP0_STSCLR: 1 | |
__OM uint32_t CMP_UP1_STSCLR: 1 | |
__OM uint32_t CMP_UP2_STSCLR: 1 | |
__OM uint32_t CMP_UP3_STSCLR: 1 | |
__OM uint32_t CMP_UP4_STSCLR: 1 | |
__OM uint32_t CMP_UP5_STSCLR: 1 | |
__OM uint32_t CMP_UP6_STSCLR: 1 | |
__OM uint32_t CMP_UP7_STSCLR: 1 | |
__OM uint32_t CMP_UP0_ISCLR: 1 | |
__OM uint32_t CMP_UP1_ISCLR: 1 | |
__OM uint32_t CMP_UP2_ISCLR: 1 | |
__OM uint32_t CMP_UP3_ISCLR: 1 | |
__OM uint32_t CMP_UP4_ISCLR: 1 | |
__OM uint32_t CMP_UP5_ISCLR: 1 | |
__OM uint32_t CMP_UP6_ISCLR: 1 | |
__OM uint32_t CMP_UP7_ISCLR: 1 | |
} bit | |
} | CMPSTATCLR |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t CMP_LO0_STSSET: 1 | |
__OM uint32_t CMP_LO1_STSSET: 1 | |
__OM uint32_t CMP_LO2_STSSET: 1 | |
__OM uint32_t CMP_LO3_STSSET: 1 | |
__OM uint32_t CMP_LO4_STSSET: 1 | |
__OM uint32_t CMP_LO5_STSSET: 1 | |
__OM uint32_t CMP_LO6_STSSET: 1 | |
__OM uint32_t CMP_LO7_STSSET: 1 | |
__OM uint32_t CMP_LO0_ISSET: 1 | |
__OM uint32_t CMP_LO1_ISSET: 1 | |
__OM uint32_t CMP_LO2_ISSET: 1 | |
__OM uint32_t CMP_LO3_ISSET: 1 | |
__OM uint32_t CMP_LO4_ISSET: 1 | |
__OM uint32_t CMP_LO5_ISSET: 1 | |
__OM uint32_t CMP_LO6_ISSET: 1 | |
__OM uint32_t CMP_LO7_ISSET: 1 | |
__OM uint32_t CMP_UP0_STSSET: 1 | |
__OM uint32_t CMP_UP1_STSSET: 1 | |
__OM uint32_t CMP_UP2_STSSET: 1 | |
__OM uint32_t CMP_UP3_STSSET: 1 | |
__OM uint32_t CMP_UP4_STSSET: 1 | |
__OM uint32_t CMP_UP5_STSSET: 1 | |
__OM uint32_t CMP_UP6_STSSET: 1 | |
__OM uint32_t CMP_UP7_STSSET: 1 | |
__OM uint32_t CMP_UP0_ISSET: 1 | |
__OM uint32_t CMP_UP1_ISSET: 1 | |
__OM uint32_t CMP_UP2_ISSET: 1 | |
__OM uint32_t CMP_UP3_ISSET: 1 | |
__OM uint32_t CMP_UP4_ISSET: 1 | |
__OM uint32_t CMP_UP5_ISSET: 1 | |
__OM uint32_t CMP_UP6_ISSET: 1 | |
__OM uint32_t CMP_UP7_ISSET: 1 | |
} bit | |
} | CMPSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IEN_CH0: 1 | |
__IOM uint32_t IEN_CH1: 1 | |
__IOM uint32_t IEN_CH2: 1 | |
__IOM uint32_t IEN_CH3: 1 | |
__IOM uint32_t IEN_CH4: 1 | |
__IOM uint32_t IEN_CH5: 1 | |
__IOM uint32_t IEN_CH6: 1 | |
__IOM uint32_t IEN_CH7: 1 | |
__IOM uint32_t IEN_CH8: 1 | |
__IOM uint32_t IEN_CH9: 1 | |
__IOM uint32_t IEN_CH10: 1 | |
__IOM uint32_t IEN_CH11: 1 | |
__IOM uint32_t IEN_CH12: 1 | |
__IOM uint32_t IEN_CH13: 1 | |
__IOM uint32_t IEN_CH14: 1 | |
uint32_t __pad0__: 17 | |
} bit | |
} | IEN0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IEN_SQ0: 1 | |
__IOM uint32_t IEN_SQ1: 1 | |
__IOM uint32_t IEN_SQ2: 1 | |
__IOM uint32_t IEN_SQ3: 1 | |
__IOM uint32_t IEN_COLL0: 1 | |
__IOM uint32_t IEN_COLL1: 1 | |
__IOM uint32_t IEN_COLL2: 1 | |
__IOM uint32_t IEN_COLL3: 1 | |
uint32_t __pad0__: 8 | |
__IOM uint32_t IEN_LO0: 1 | |
__IOM uint32_t IEN_LO1: 1 | |
__IOM uint32_t IEN_LO2: 1 | |
__IOM uint32_t IEN_LO3: 1 | |
__IOM uint32_t IEN_LO4: 1 | |
__IOM uint32_t IEN_LO5: 1 | |
__IOM uint32_t IEN_LO6: 1 | |
__IOM uint32_t IEN_LO7: 1 | |
__IOM uint32_t IEN_UP0: 1 | |
__IOM uint32_t IEN_UP1: 1 | |
__IOM uint32_t IEN_UP2: 1 | |
__IOM uint32_t IEN_UP3: 1 | |
__IOM uint32_t IEN_UP4: 1 | |
__IOM uint32_t IEN_UP5: 1 | |
__IOM uint32_t IEN_UP6: 1 | |
__IOM uint32_t IEN_UP7: 1 | |
} bit | |
} | IEN1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CH0: 2 | |
__IOM uint32_t INP_CH1: 2 | |
__IOM uint32_t INP_CH2: 2 | |
__IOM uint32_t INP_CH3: 2 | |
__IOM uint32_t INP_CH4: 2 | |
__IOM uint32_t INP_CH5: 2 | |
__IOM uint32_t INP_CH6: 2 | |
__IOM uint32_t INP_CH7: 2 | |
__IOM uint32_t INP_CH8: 2 | |
__IOM uint32_t INP_CH9: 2 | |
__IOM uint32_t INP_CH10: 2 | |
__IOM uint32_t INP_CH11: 2 | |
__IOM uint32_t INP_CH12: 2 | |
__IOM uint32_t INP_CH13: 2 | |
__IOM uint32_t INP_CH14: 2 | |
uint32_t __pad0__: 2 | |
} bit | |
} | INP0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CMP_LO0: 2 | |
__IOM uint32_t INP_CMP_LO1: 2 | |
__IOM uint32_t INP_CMP_LO2: 2 | |
__IOM uint32_t INP_CMP_LO3: 2 | |
__IOM uint32_t INP_CMP_LO4: 2 | |
__IOM uint32_t INP_CMP_LO5: 2 | |
__IOM uint32_t INP_CMP_LO6: 2 | |
__IOM uint32_t INP_CMP_LO7: 2 | |
__IOM uint32_t INP_CMP_UP0: 2 | |
__IOM uint32_t INP_CMP_UP1: 2 | |
__IOM uint32_t INP_CMP_UP2: 2 | |
__IOM uint32_t INP_CMP_UP3: 2 | |
__IOM uint32_t INP_CMP_UP4: 2 | |
__IOM uint32_t INP_CMP_UP5: 2 | |
__IOM uint32_t INP_CMP_UP6: 2 | |
__IOM uint32_t INP_CMP_UP7: 2 | |
} bit | |
} | INP2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_SQ0: 2 | |
__IOM uint32_t INP_SQ1: 2 | |
__IOM uint32_t INP_SQ2: 2 | |
__IOM uint32_t INP_SQ3: 2 | |
__IOM uint32_t INP_COLL0: 2 | |
__IOM uint32_t INP_COLL1: 2 | |
__IOM uint32_t INP_COLL2: 2 | |
__IOM uint32_t INP_COLL3: 2 | |
uint32_t __pad0__: 16 | |
} bit | |
} | INP3 |
__IM uint32_t | RESERVED [4] |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t LOW_VOLT_STS: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | INTSTAT |
__IM uint32_t | RESERVED1 [3] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t TRGSEL: 2 | |
uint32_t __pad2__: 4 | |
__OM uint32_t TRGSW: 1 | |
uint32_t __pad3__: 17 | |
} bit | |
} | SQCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t TRGSEL: 2 | |
uint32_t __pad2__: 4 | |
__OM uint32_t TRGSW: 1 | |
uint32_t __pad3__: 17 | |
} bit | |
} | SQCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t TRGSEL: 2 | |
uint32_t __pad2__: 4 | |
__OM uint32_t TRGSW: 1 | |
uint32_t __pad3__: 17 | |
} bit | |
} | SQCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t TRGSEL: 2 | |
uint32_t __pad2__: 4 | |
__OM uint32_t TRGSW: 1 | |
uint32_t __pad3__: 17 | |
} bit | |
} | SQCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG4 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG5 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG6 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG7 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG8 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG9 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG10 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG11 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG12 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG13 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 4 | |
__IOM uint32_t CMPSEL: 4 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 6 | |
} bit | |
} | CHCFG14 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CMP_LO: 8 | |
uint32_t __pad0__: 8 | |
__IM uint32_t CMP_UP: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CMPSTAT2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 5 | |
uint32_t __pad0__: 11 | |
__IOM uint32_t CALGAIN: 8 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CALAI14 |
__IM uint32_t | RESERVED2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CHSEL1: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t CHSEL2: 4 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t CHSEL3: 4 | |
uint32_t __pad3__: 4 | |
} bit | |
} | SQSLOT0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CHSEL1: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t CHSEL2: 4 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t CHSEL3: 4 | |
uint32_t __pad3__: 4 | |
} bit | |
} | SQSLOT1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CHSEL1: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t CHSEL2: 4 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t CHSEL3: 4 | |
uint32_t __pad3__: 4 | |
} bit | |
} | SQSLOT2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CHSEL1: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t CHSEL2: 4 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t CHSEL3: 4 | |
uint32_t __pad3__: 4 | |
} bit | |
} | SQSLOT3 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 4 | |
__IOM uint32_t STC: 4 | |
uint32_t __pad1__: 24 | |
} bit | |
} | CONVCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 4 | |
__IOM uint32_t STC: 4 | |
uint32_t __pad1__: 24 | |
} bit | |
} | CONVCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 4 | |
__IOM uint32_t STC: 4 | |
uint32_t __pad1__: 24 | |
} bit | |
} | CONVCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 4 | |
__IOM uint32_t STC: 4 | |
uint32_t __pad1__: 24 | |
} bit | |
} | CONVCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t COEF_A0: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t COEF_A1: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t COEF_A2: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t COEF_A3: 2 | |
uint32_t __pad3__: 2 | |
__IOM uint32_t COEF_A4: 2 | |
uint32_t __pad4__: 2 | |
__IOM uint32_t COEF_A5: 2 | |
uint32_t __pad5__: 2 | |
__IOM uint32_t COEF_A6: 2 | |
uint32_t __pad6__: 2 | |
__IOM uint32_t COEF_A7: 2 | |
uint32_t __pad7__: 2 | |
} bit | |
} | FILTCFG |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
uint32_t __pad4__ |
uint32_t __pad5__ |
uint32_t __pad6__ |
uint32_t __pad7__ |
struct { ... } bit |
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struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
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struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IOM uint32_t BLANK_TIME |
[26..24] Blank Time configuration
union { ... } CALAI0 |
union { ... } CALAI1 |
union { ... } CALAI10 |
union { ... } CALAI11 |
union { ... } CALAI12 |
union { ... } CALAI13 |
union { ... } CALAI14 |
union { ... } CALAI2 |
union { ... } CALAI3 |
union { ... } CALAI4 |
union { ... } CALAI5 |
union { ... } CALAI6 |
union { ... } CALAI7 |
union { ... } CALAI8 |
union { ... } CALAI9 |
union { ... } CALEN |
__IOM uint32_t CALEN0 |
[0..0] Channel 0 Calibration Enable
__IOM uint32_t CALEN1 |
[1..1] Channel 1 Calibration Enable
__IOM uint32_t CALEN10 |
[10..10] Channel 10 Calibration Enable
__IOM uint32_t CALEN11 |
[11..11] Channel 11 Calibration Enable
__IOM uint32_t CALEN12 |
[12..12] Channel 12 Calibration Enable
__IOM uint32_t CALEN13 |
[13..13] Channel 13 Calibration Enable
__IOM uint32_t CALEN14 |
[14..14] Channel 14 Calibration Enable
__IOM uint32_t CALEN2 |
[2..2] Channel 2 Calibration Enable
__IOM uint32_t CALEN3 |
[3..3] Channel 3 Calibration Enable
__IOM uint32_t CALEN4 |
[4..4] Channel 4 Calibration Enable
__IOM uint32_t CALEN5 |
[5..5] Channel 5 Calibration Enable
__IOM uint32_t CALEN6 |
[6..6] Channel 6 Calibration Enable
__IOM uint32_t CALEN7 |
[7..7] Channel 7 Calibration Enable
__IOM uint32_t CALEN8 |
[8..8] Channel 8 Calibration Enable
__IOM uint32_t CALEN9 |
[9..9] Channel 9 Calibration Enable
__IOM uint32_t CALGAIN |
[23..16] Calibration Gain
__IOM uint32_t CALOFFS |
[4..0] Calibration Offset
union { ... } CALPEN |
__IOM uint32_t CALPEN0 |
[0..0] Channel 0 Calibration Protection
__IOM uint32_t CALPEN1 |
[1..1] Channel 1 Calibration Protection
__IOM uint32_t CALPEN10 |
[10..10] Channel 10 Calibration Protection
__IOM uint32_t CALPEN11 |
[11..11] Channel 11 Calibration Protection
__IOM uint32_t CALPEN12 |
[12..12] Channel 12 Calibration Protection
__IOM uint32_t CALPEN13 |
[13..13] Channel 13 Calibration Protection
__IOM uint32_t CALPEN14 |
[14..14] Channel 14 Calibration Protection
__IOM uint32_t CALPEN2 |
[2..2] Channel 2 Calibration Protection
__IOM uint32_t CALPEN3 |
[3..3] Channel 3 Calibration Protection
__IOM uint32_t CALPEN4 |
[4..4] Channel 4 Calibration Protection
__IOM uint32_t CALPEN5 |
[5..5] Channel 5 Calibration Protection
__IOM uint32_t CALPEN6 |
[6..6] Channel 6 Calibration Protection
__IOM uint32_t CALPEN7 |
[7..7] Channel 7 Calibration Protection
__IOM uint32_t CALPEN8 |
[8..8] Channel 8 Calibration Protection
__IOM uint32_t CALPEN9 |
[9..9] Channel 9 Calibration Protection
__IOM uint32_t CH0 |
[0..0] Channel 0 Status
__OM uint32_t CH0CLR |
[0..0] Channel 0 Status clear flag
__OM uint32_t CH0SET |
[0..0] Channel 0 Status set flag
__IOM uint32_t CH1 |
[1..1] Channel 1 Status
__IOM uint32_t CH10 |
[10..10] Channel 10 Status
__OM uint32_t CH10CLR |
[10..10] Channel 10 Status clear flag
__OM uint32_t CH10SET |
[10..10] Channel 10 Status set flag
__IOM uint32_t CH11 |
[11..11] Channel 11 Status
__OM uint32_t CH11CLR |
[11..11] Channel 11 Status clear flag
__OM uint32_t CH11SET |
[11..11] Channel 11 Status set flag
__IOM uint32_t CH12 |
[12..12] Channel 12 Status
__OM uint32_t CH12CLR |
[12..12] Channel 12 Status clear flag
__OM uint32_t CH12SET |
[12..12] Channel 12 Status set flag
__IOM uint32_t CH13 |
[13..13] Channel 13 Status
__OM uint32_t CH13CLR |
[13..13] Channel 13 Status clear flag
__OM uint32_t CH13SET |
[13..13] Channel 13 Status set flag
__IOM uint32_t CH14 |
[14..14] Channel 14 Status
__OM uint32_t CH14CLR |
[14..14] Channel 14 Status clear flag
__OM uint32_t CH14SET |
[14..14] Channel 14 Status set flag
__OM uint32_t CH1CLR |
[1..1] Channel 1 Status clear flag
__OM uint32_t CH1SET |
[1..1] Channel 1 Status set flag
__IOM uint32_t CH2 |
[2..2] Channel 2 Status
__OM uint32_t CH2CLR |
[2..2] Channel 2 Status clear flag
__OM uint32_t CH2SET |
[2..2] Channel 2 Status set flag
__IOM uint32_t CH3 |
[3..3] Channel 3 Status
__OM uint32_t CH3CLR |
[3..3] Channel 3 Status clear flag
__OM uint32_t CH3SET |
[3..3] Channel 3 Status set flag
__IOM uint32_t CH4 |
[4..4] Channel 4 Status
__OM uint32_t CH4CLR |
[4..4] Channel 4 Status clear flag
__OM uint32_t CH4SET |
[4..4] Channel 4 Status set flag
__IOM uint32_t CH5 |
[5..5] Channel 5 Status
__OM uint32_t CH5CLR |
[5..5] Channel 5 Status clear flag
__OM uint32_t CH5SET |
[5..5] Channel 5 Status set flag
__IOM uint32_t CH6 |
[6..6] Channel 6 Status
__OM uint32_t CH6CLR |
[6..6] Channel 6 Status clear flag
__OM uint32_t CH6SET |
[6..6] Channel 6 Status set flag
__IOM uint32_t CH7 |
[7..7] Channel 7 Status
__OM uint32_t CH7CLR |
[7..7] Channel 7 Status clear flag
__OM uint32_t CH7SET |
[7..7] Channel 7 Status set flag
__IOM uint32_t CH8 |
[8..8] Channel 8 Status
__OM uint32_t CH8CLR |
[8..8] Channel 8 Status clear flag
__OM uint32_t CH8SET |
[8..8] Channel 8 Status set flag
__IOM uint32_t CH9 |
[9..9] Channel 9 Status
__OM uint32_t CH9CLR |
[9..9] Channel 9 Status clear flag
__OM uint32_t CH9SET |
[9..9] Channel 9 Status set flag
union { ... } CHCFG0 |
union { ... } CHCFG1 |
union { ... } CHCFG10 |
union { ... } CHCFG11 |
union { ... } CHCFG12 |
union { ... } CHCFG13 |
union { ... } CHCFG14 |
union { ... } CHCFG2 |
union { ... } CHCFG3 |
union { ... } CHCFG4 |
union { ... } CHCFG5 |
union { ... } CHCFG6 |
union { ... } CHCFG7 |
union { ... } CHCFG8 |
union { ... } CHCFG9 |
__IOM uint32_t CHNUM |
[27..24] Current Channel under conversion
__IOM uint32_t CHREP |
[11..8] Channel Repetition
__IOM uint32_t CHSEL0 |
[3..0] Channel Select
__IOM uint32_t CHSEL1 |
[11..8] Channel Select
__IOM uint32_t CHSEL2 |
[19..16] Channel Select
__IOM uint32_t CHSEL3 |
[27..24] Channel Select
union { ... } CHSTAT |
union { ... } CHSTATCLR |
union { ... } CHSTATSET |
__IOM uint32_t CLASSEL |
[25..24] Conversion Class Selection
union { ... } CLKCON |
__IOM uint32_t CLKDIV |
[3..0] Clock Divider Settings
__IM uint32_t CMP_LO |
[7..0] Compare low Status
__IOM uint32_t CMP_LO0_IS |
[8..8] Compare 0 low Interrupt Status
__OM uint32_t CMP_LO0_ISCLR |
[8..8] Compare 0 low Interrupt clear
__OM uint32_t CMP_LO0_ISSET |
[8..8] Compare 0 low Interupt set
__IOM uint32_t CMP_LO0_STS |
[0..0] Compare 0 low Status
__OM uint32_t CMP_LO0_STSCLR |
[0..0] Compare 0 low Status clear
__OM uint32_t CMP_LO0_STSSET |
[0..0] Compare 0 low Status set
__IOM uint32_t CMP_LO1_IS |
[9..9] Compare 1 low Interrupt Status
__OM uint32_t CMP_LO1_ISCLR |
[9..9] Compare 1 low Interrupt clear
__OM uint32_t CMP_LO1_ISSET |
[9..9] Compare 1 low Interupt set
__IOM uint32_t CMP_LO1_STS |
[1..1] Compare 1 low Status
__OM uint32_t CMP_LO1_STSCLR |
[1..1] Compare 1 low Status clear
__OM uint32_t CMP_LO1_STSSET |
[1..1] Compare 1 low Status set
__IOM uint32_t CMP_LO2_IS |
[10..10] Compare 2 low Interrupt Status
__OM uint32_t CMP_LO2_ISCLR |
[10..10] Compare 2 low Interrupt clear
__OM uint32_t CMP_LO2_ISSET |
[10..10] Compare 2 low Interupt set
__IOM uint32_t CMP_LO2_STS |
[2..2] Compare 2 low Status
__OM uint32_t CMP_LO2_STSCLR |
[2..2] Compare 2 low Status clear
__OM uint32_t CMP_LO2_STSSET |
[2..2] Compare 2 low Status set
__IOM uint32_t CMP_LO3_IS |
[11..11] Compare 3 low Interrupt Status
__OM uint32_t CMP_LO3_ISCLR |
[11..11] Compare 3 low Interrupt clear
__OM uint32_t CMP_LO3_ISSET |
[11..11] Compare 3 low Interupt set
__IOM uint32_t CMP_LO3_STS |
[3..3] Compare 3 low Status
__OM uint32_t CMP_LO3_STSCLR |
[3..3] Compare 3 low Status clear
__OM uint32_t CMP_LO3_STSSET |
[3..3] Compare 3 low Status set
__IOM uint32_t CMP_LO4_IS |
[12..12] Compare 4 low Interrupt Status
__OM uint32_t CMP_LO4_ISCLR |
[12..12] Compare 4 low Interrupt clear
__OM uint32_t CMP_LO4_ISSET |
[12..12] Compare 4 low Interupt set
__IOM uint32_t CMP_LO4_STS |
[4..4] Compare 4 low Status
__OM uint32_t CMP_LO4_STSCLR |
[4..4] Compare 4 low Status clear
__OM uint32_t CMP_LO4_STSSET |
[4..4] Compare 4 low Status set
__IOM uint32_t CMP_LO5_IS |
[13..13] Compare 5 low Interrupt Status
__OM uint32_t CMP_LO5_ISCLR |
[13..13] Compare 5 low Interrupt clear
__OM uint32_t CMP_LO5_ISSET |
[13..13] Compare 5 low Interupt set
__IOM uint32_t CMP_LO5_STS |
[5..5] Compare 5 low Status
__OM uint32_t CMP_LO5_STSCLR |
[5..5] Compare 5 low Status clear
__OM uint32_t CMP_LO5_STSSET |
[5..5] Compare 5 low Status set
__IOM uint32_t CMP_LO6_IS |
[14..14] Compare 6 low Interrupt Status
__OM uint32_t CMP_LO6_ISCLR |
[14..14] Compare 6 low Interrupt clear
__OM uint32_t CMP_LO6_ISSET |
[14..14] Compare 6 low Interupt set
__IOM uint32_t CMP_LO6_STS |
[6..6] Compare 6 low Status
__OM uint32_t CMP_LO6_STSCLR |
[6..6] Compare 6 low Status clear
__OM uint32_t CMP_LO6_STSSET |
[6..6] Compare 6 low Status set
__IOM uint32_t CMP_LO7_IS |
[15..15] Compare 7 low Interrupt Status
__OM uint32_t CMP_LO7_ISCLR |
[15..15] Compare 7 low Interrupt clear
__OM uint32_t CMP_LO7_ISSET |
[15..15] Compare 7 low Interupt set
__IOM uint32_t CMP_LO7_STS |
[7..7] Compare 7 low Status
__OM uint32_t CMP_LO7_STSCLR |
[7..7] Compare 7 low Status clear
__OM uint32_t CMP_LO7_STSSET |
[7..7] Compare 7 low Status set
__IM uint32_t CMP_UP |
[23..16] Compare up Status
__IOM uint32_t CMP_UP0_IS |
[24..24] Compare 0 up Interrupt Status
__OM uint32_t CMP_UP0_ISCLR |
[24..24] Compare 0 up Interrupt clear
__OM uint32_t CMP_UP0_ISSET |
[24..24] Compare 0 up Interrupt set
__IOM uint32_t CMP_UP0_STS |
[16..16] Compare 0 up Status
__OM uint32_t CMP_UP0_STSCLR |
[16..16] Compare 0 up Status clear
__OM uint32_t CMP_UP0_STSSET |
[16..16] Compare 0 up Status set
__IOM uint32_t CMP_UP1_IS |
[25..25] Compare 1 up Interrupt Status
__OM uint32_t CMP_UP1_ISCLR |
[25..25] Compare 1 up Interrupt clear
__OM uint32_t CMP_UP1_ISSET |
[25..25] Compare 1 up Interrupt set
__IOM uint32_t CMP_UP1_STS |
[17..17] Compare 1 up Status
__OM uint32_t CMP_UP1_STSCLR |
[17..17] Compare 1 up Status clear
__OM uint32_t CMP_UP1_STSSET |
[17..17] Compare 1 up Status set
__IOM uint32_t CMP_UP2_IS |
[26..26] Compare 2 up Interrupt Status
__OM uint32_t CMP_UP2_ISCLR |
[26..26] Compare 2 up Interrupt clear
__OM uint32_t CMP_UP2_ISSET |
[26..26] Compare 2 up Interrupt set
__IOM uint32_t CMP_UP2_STS |
[18..18] Compare 2 up Status
__OM uint32_t CMP_UP2_STSCLR |
[18..18] Compare 2 up Status clear
__OM uint32_t CMP_UP2_STSSET |
[18..18] Compare 2 up Status set
__IOM uint32_t CMP_UP3_IS |
[27..27] Compare 3 up Interrupt Status
__OM uint32_t CMP_UP3_ISCLR |
[27..27] Compare 3 up Interrupt clear
__OM uint32_t CMP_UP3_ISSET |
[27..27] Compare 3 up Interrupt set
__IOM uint32_t CMP_UP3_STS |
[19..19] Compare 3 up Status
__OM uint32_t CMP_UP3_STSCLR |
[19..19] Compare 3 up Status clear
__OM uint32_t CMP_UP3_STSSET |
[19..19] Compare 3 up Status set
__IOM uint32_t CMP_UP4_IS |
[28..28] Compare 4 up Interrupt Status
__OM uint32_t CMP_UP4_ISCLR |
[28..28] Compare 4 up Interrupt clear
__OM uint32_t CMP_UP4_ISSET |
[28..28] Compare 4 up Interrupt set
__IOM uint32_t CMP_UP4_STS |
[20..20] Compare 4 up Status
__OM uint32_t CMP_UP4_STSCLR |
[20..20] Compare 4 up Status clear
__OM uint32_t CMP_UP4_STSSET |
[20..20] Compare 4 up Status set
__IOM uint32_t CMP_UP5_IS |
[29..29] Compare 5 up Interrupt Status
__OM uint32_t CMP_UP5_ISCLR |
[29..29] Compare 5 up Interrupt clear
__OM uint32_t CMP_UP5_ISSET |
[29..29] Compare 5 up Interrupt set
__IOM uint32_t CMP_UP5_STS |
[21..21] Compare 5 up Status
__OM uint32_t CMP_UP5_STSCLR |
[21..21] Compare 5 up Status clear
__OM uint32_t CMP_UP5_STSSET |
[21..21] Compare 5 up Status set
__IOM uint32_t CMP_UP6_IS |
[30..30] Compare 6 up Interrupt Status
__OM uint32_t CMP_UP6_ISCLR |
[30..30] Compare 6 up Interrupt clear
__OM uint32_t CMP_UP6_ISSET |
[30..30] Compare 6 up Interrupt set
__IOM uint32_t CMP_UP6_STS |
[22..22] Compare 6 up Status
__OM uint32_t CMP_UP6_STSCLR |
[22..22] Compare 6 up Status clear
__OM uint32_t CMP_UP6_STSSET |
[22..22] Compare 6 up Status set
__IOM uint32_t CMP_UP7_IS |
[31..31] Compare 7 up Interrupt Status
__OM uint32_t CMP_UP7_ISCLR |
[31..31] Compare 7 up Interrupt clear
__OM uint32_t CMP_UP7_ISSET |
[31..31] Compare 7 up Interrupt set
__IOM uint32_t CMP_UP7_STS |
[23..23] Compare 7 up Status
__OM uint32_t CMP_UP7_STSCLR |
[23..23] Compare 7 up Status clear
__OM uint32_t CMP_UP7_STSSET |
[23..23] Compare 7 up Status set
union { ... } CMPCFG0 |
union { ... } CMPCFG1 |
union { ... } CMPCFG2 |
union { ... } CMPCFG3 |
union { ... } CMPCFG4 |
union { ... } CMPCFG5 |
union { ... } CMPCFG6 |
union { ... } CMPCFG7 |
__IOM uint32_t CMPSEL |
[23..20] Compare Selection
union { ... } CMPSTAT |
union { ... } CMPSTAT2 |
union { ... } CMPSTATCLR |
union { ... } CMPSTATSET |
__IOM uint32_t COEF_A0 |
[1..0] Filter Coefficient 0
__IOM uint32_t COEF_A1 |
[5..4] Filter Coefficient 0
__IOM uint32_t COEF_A2 |
[9..8] Filter Coefficient 0
__IOM uint32_t COEF_A3 |
[13..12] Filter Coefficient 0
__IOM uint32_t COEF_A4 |
[17..16] Filter Coefficient 0
__IOM uint32_t COEF_A5 |
[21..20] Filter Coefficient 0
__IOM uint32_t COEF_A6 |
[25..24] Filter Coefficient 0
__IOM uint32_t COEF_A7 |
[29..28] Filter Coefficient 0
__IOM uint32_t COLL0 |
[8..8] Collision 0 Status
__IOM uint32_t COLL0CLR |
[8..8] Collision 0 Status Clear
__IOM uint32_t COLL0SET |
[8..8] Collision 0 Status Set
__IOM uint32_t COLL1 |
[9..9] Collision 1 Status
__IOM uint32_t COLL1CLR |
[9..9] Collision 1 Status Clear
__IOM uint32_t COLL1SET |
[9..9] Collision 1 Status Set
__IOM uint32_t COLL2 |
[10..10] Collision 2 Status
__IOM uint32_t COLL2CLR |
[10..10] Collision 2 Status Clear
__IOM uint32_t COLL2SET |
[10..10] Collision 2 Status Set
__IOM uint32_t COLL3 |
[11..11] Collision 3 Status
__IOM uint32_t COLL3CLR |
[11..11] Collision 3 Status Clear
__IOM uint32_t COLL3SET |
[11..11] Collision 3 Status Set
union { ... } CONVCFG0 |
union { ... } CONVCFG1 |
union { ... } CONVCFG2 |
union { ... } CONVCFG3 |
__IOM uint32_t EN |
[0..0] Module Enable
union { ... } FIL0 |
__IOM uint32_t FIL0 |
[0..0] Filter 0 Event flag
__OM uint32_t FIL0CLR |
[0..0] Filter 0 Event flag clear
__OM uint32_t FIL0SET |
[0..0] Filter 0 Event flag set
union { ... } FIL1 |
__IOM uint32_t FIL1 |
[1..1] Filter 1 Event flag
__OM uint32_t FIL1CLR |
[1..1] Filter 1 Event flag clear
__OM uint32_t FIL1SET |
[1..1] Filter 1 Event flag set
union { ... } FIL2 |
__IOM uint32_t FIL2 |
[2..2] Filter 2 Event flag
__OM uint32_t FIL2CLR |
[2..2] Filter 2 Event flag clear
__OM uint32_t FIL2SET |
[2..2] Filter 2 Event flag set
union { ... } FIL3 |
__IOM uint32_t FIL3 |
[3..3] Filter 3 Event flag
__OM uint32_t FIL3CLR |
[3..3] Filter 3 Event flag clear
__OM uint32_t FIL3SET |
[3..3] Filter 3 Event flag set
union { ... } FIL4 |
__IOM uint32_t FIL4 |
[4..4] Filter 4 Event flag
__OM uint32_t FIL4CLR |
[4..4] Filter 4 Event flag clear
__OM uint32_t FIL4SET |
[4..4] Filter 4 Event flag set
union { ... } FIL5 |
__IOM uint32_t FIL5 |
[5..5] Filter 5 Event flag
__OM uint32_t FIL5CLR |
[5..5] Filter 5 Event flag clear
__OM uint32_t FIL5SET |
[5..5] Filter 5 Event flag set
union { ... } FIL6 |
__IOM uint32_t FIL6 |
[6..6] Filter 6 Event flag
__OM uint32_t FIL6CLR |
[6..6] Filter 6 Event flag clear
__OM uint32_t FIL6SET |
[6..6] Filter 6 Event flag set
union { ... } FIL7 |
__IOM uint32_t FIL7 |
[7..7] Filter 7 Event flag
__OM uint32_t FIL7CLR |
[7..7] Filter 7 Event flag clear
__OM uint32_t FIL7SET |
[7..7] Filter 7 Event flag set
__IM uint32_t FILRESULT |
[13..0] Filter Result Value
__IOM uint32_t FILSEL |
[19..16] Filter Selection
union { ... } FILSTAT |
union { ... } FILSTATCLR |
union { ... } FILSTATSET |
union { ... } FILTCFG |
union { ... } GLOBCONF |
__IOM uint32_t HYST_LO |
[13..12] Hysteresis setting for lower compare threshold
__IOM uint32_t HYST_UP |
[29..28] Hysteresis setting for upper compare threshold
union { ... } IEN0 |
union { ... } IEN1 |
__IOM uint32_t IEN_CH0 |
[0..0] Channel 0 Interrupt Enable
__IOM uint32_t IEN_CH1 |
[1..1] Channel 1 Interrupt Enable
__IOM uint32_t IEN_CH10 |
[10..10] Channel 10 Interrupt Enable
__IOM uint32_t IEN_CH11 |
[11..11] Channel 11 Interrupt Enable
__IOM uint32_t IEN_CH12 |
[12..12] Channel 12 Interrupt Enable
__IOM uint32_t IEN_CH13 |
[13..13] Channel 13 Interrupt Enable
__IOM uint32_t IEN_CH14 |
[14..14] Channel 14 Interrupt Enable
__IOM uint32_t IEN_CH2 |
[2..2] Channel 2 Interrupt Enable
__IOM uint32_t IEN_CH3 |
[3..3] Channel 3 Interrupt Enable
__IOM uint32_t IEN_CH4 |
[4..4] Channel 4 Interrupt Enable
__IOM uint32_t IEN_CH5 |
[5..5] Channel 5 Interrupt Enable
__IOM uint32_t IEN_CH6 |
[6..6] Channel 6 Interrupt Enable
__IOM uint32_t IEN_CH7 |
[7..7] Channel 7 Interrupt Enable
__IOM uint32_t IEN_CH8 |
[8..8] Channel 8 Interrupt Enable
__IOM uint32_t IEN_CH9 |
[9..9] Channel 9 Interrupt Enable
__IOM uint32_t IEN_COLL0 |
[4..4] Collision 0 Interrupt Enable
__IOM uint32_t IEN_COLL1 |
[5..5] Collision 1 Interrupt Enable
__IOM uint32_t IEN_COLL2 |
[6..6] Collision 2 Interrupt Enable
__IOM uint32_t IEN_COLL3 |
[7..7] Collision 3 Interrupt Enable
__IOM uint32_t IEN_LO0 |
[16..16] Compare 0 LO Interrupt Enable
__IOM uint32_t IEN_LO1 |
[17..17] Compare 1 LO Interrupt Enable
__IOM uint32_t IEN_LO2 |
[18..18] Compare 2 LO Interrupt Enable
__IOM uint32_t IEN_LO3 |
[19..19] Compare 3 LO Interrupt Enable
__IOM uint32_t IEN_LO4 |
[20..20] Compare 4 LO Interrupt Enable
__IOM uint32_t IEN_LO5 |
[21..21] Compare 5 LO Interrupt Enable
__IOM uint32_t IEN_LO6 |
[22..22] Compare 6 LO Interrupt Enable
__IOM uint32_t IEN_LO7 |
[23..23] Compare 7 LO Interrupt Enable
__IOM uint32_t IEN_SQ0 |
[0..0] Sequence 0 Interrupt Enable
__IOM uint32_t IEN_SQ1 |
[1..1] Sequence 1 Interrupt Enable
__IOM uint32_t IEN_SQ2 |
[2..2] Sequence 2 Interrupt Enable
__IOM uint32_t IEN_SQ3 |
[3..3] Sequence 3 Interrupt Enable
__IOM uint32_t IEN_UP0 |
[24..24] Compare 0 UP Interrupt Enable
__IOM uint32_t IEN_UP1 |
[25..25] Compare 1 UP Interrupt Enable
__IOM uint32_t IEN_UP2 |
[26..26] Compare 2 UP Interrupt Enable
__IOM uint32_t IEN_UP3 |
[27..27] Compare 3 UP Interrupt Enable
__IOM uint32_t IEN_UP4 |
[28..28] Compare 4 UP Interrupt Enable
__IOM uint32_t IEN_UP5 |
[29..29] Compare 5 UP Interrupt Enable
__IOM uint32_t IEN_UP6 |
[30..30] Compare 6 UP Interrupt Enable
__IOM uint32_t IEN_UP7 |
[31..31] Compare 7 UP Interrupt Enable
union { ... } INP0 |
union { ... } INP2 |
union { ... } INP3 |
__IOM uint32_t INP_CH0 |
[1..0] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH1 |
[3..2] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH10 |
[21..20] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH11 |
[23..22] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH12 |
[25..24] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH13 |
[27..26] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH14 |
[29..28] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH2 |
[5..4] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH3 |
[7..6] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH4 |
[9..8] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH5 |
[11..10] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH6 |
[13..12] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH7 |
[15..14] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH8 |
[17..16] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH9 |
[19..18] Channel Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO0 |
[1..0] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO1 |
[3..2] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO2 |
[5..4] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO3 |
[7..6] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO4 |
[9..8] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO5 |
[11..10] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO6 |
[13..12] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO7 |
[15..14] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP0 |
[17..16] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP1 |
[19..18] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP2 |
[21..20] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP3 |
[23..22] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP4 |
[25..24] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP5 |
[27..26] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP6 |
[29..28] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP7 |
[31..30] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_COLL0 |
[9..8] Collision Interrupt Node Pointer
__IOM uint32_t INP_COLL1 |
[11..10] Collision Interrupt Node Pointer
__IOM uint32_t INP_COLL2 |
[13..12] Collision Interrupt Node Pointer
__IOM uint32_t INP_COLL3 |
[15..14] Collision Interrupt Node Pointer
__IOM uint32_t INP_SEL |
[8..8] Input selection for the comparator unit
__IOM uint32_t INP_SQ0 |
[1..0] Sequence Interrupt Node Pointer
__IOM uint32_t INP_SQ1 |
[3..2] Sequence Interrupt Node Pointer
__IOM uint32_t INP_SQ2 |
[5..4] Sequence Interrupt Node Pointer
__IOM uint32_t INP_SQ3 |
[7..6] Sequence Interrupt Node Pointer
union { ... } INTSTAT |
__IOM uint32_t ISTE |
[2..2] Idle shadow transfer enable
__IM uint32_t LOW_VOLT_STS |
[0..0] ADC2 low voltage Status
__IOM uint32_t LOWER |
[7..0] Lower Compare Value
__IOM uint32_t MODE |
[31..30] Compare Mode
__IOM uint32_t reg |
(@ 0x00000000) Global Configuration Register
(@ 0x00000004) Clock Control Register
(@ 0x00000008) Suspend Control Register
(@ 0x00000010) Sequence Status Register
(@ 0x00000014) Sequence Status Clear Register
(@ 0x00000018) Sequence Status Clear Register
(@ 0x0000001C) Channel Status Register
(@ 0x00000020) Channel Status Register
(@ 0x00000024) Channel Status Register
(@ 0x00000028) Calibration Enable
(@ 0x0000002C) Calibration Protection Enable
(@ 0x00000050) Filter Status Register
(@ 0x00000054) Filter Status Clear Register
(@ 0x00000058) Filter Status Clear Register
(@ 0x00000098) Compare Status Register
(@ 0x000000A4) Interrupt Enable Register 0
(@ 0x000000A8) Interrupt Enable Register 1
(@ 0x000000AC) Interrupt Node Pointer Register 0
(@ 0x000000B0) Interrupt Node Pointer Register 2
(@ 0x000000B4) Interrupt Node Pointer Register 3
(@ 0x000000D8) Sequence Configuration Register 0
(@ 0x000000DC) Sequence Configuration Register 1
(@ 0x000000E0) Sequence Configuration Register 2
(@ 0x000000E4) Sequence Configuration Register 3
(@ 0x000000E8) Channel Configuration Register 0
(@ 0x000000EC) Channel Configuration Register 1
(@ 0x000000F0) Channel Configuration Register 2
(@ 0x000000F4) Channel Configuration Register 3
(@ 0x000000F8) Channel Configuration Register 4
(@ 0x000000FC) Channel Configuration Register 5
(@ 0x00000100) Channel Configuration Register 6
(@ 0x00000104) Channel Configuration Register 7
(@ 0x00000108) Channel Configuration Register 8
(@ 0x0000010C) Channel Configuration Register 9
(@ 0x00000110) Channel Configuration Register 10
(@ 0x00000114) Channel Configuration Register 11
(@ 0x00000118) Channel Configuration Register 12
(@ 0x0000011C) Channel Configuration Register 13
(@ 0x00000120) Channel Configuration Register 14
(@ 0x00000128) Calibration Setting for Analog Inputs
(@ 0x0000012C) Calibration Setting for Analog Inputs
(@ 0x00000130) Calibration Setting for Analog Inputs
(@ 0x00000134) Calibration Setting for Analog Inputs
(@ 0x00000138) Calibration Setting for Analog Inputs
(@ 0x0000013C) Calibration Setting for Analog Inputs
(@ 0x00000140) Calibration Setting for Analog Inputs
(@ 0x00000144) Calibration Setting for Analog Inputs
(@ 0x00000148) Calibration Setting for Analog Inputs
(@ 0x0000014C) Calibration Setting for Analog Inputs
(@ 0x00000150) Calibration Setting for Analog Inputs
(@ 0x00000154) Calibration Setting for Analog Inputs
(@ 0x00000158) Calibration Setting for Analog Inputs
(@ 0x0000015C) Calibration Setting for Analog Inputs
(@ 0x00000160) Calibration Setting for Analog Inputs
(@ 0x00000168) SQ Channel Slot Register 0
(@ 0x0000016C) SQ Channel Slot Register 1
(@ 0x00000170) SQ Channel Slot Register 2
(@ 0x00000174) SQ Channel Slot Register 3
(@ 0x00000178) Conversion Configuration Register 0
(@ 0x0000017C) Conversion Configuration Register 1
(@ 0x00000180) Conversion Configuration Register 2
(@ 0x00000184) Conversion Configuration Register 3
(@ 0x00000188) Compare Channel 0 Control Register
(@ 0x0000018C) Compare Channel 1 Control Register
(@ 0x00000190) Compare Channel 2 Control Register
(@ 0x00000194) Compare Channel 3 Control Register
(@ 0x00000198) Compare Channel 4 Control Register
(@ 0x0000019C) Compare Channel 5 Control Register
(@ 0x000001A0) Compare Channel 6 Control Register
(@ 0x000001A4) Compare Channel 7 Control Register
(@ 0x000001A8) Filter Configuration
__IM uint32_t reg |
(@ 0x0000000C) Suspend Status Register
(@ 0x00000030) Filter Result Register
(@ 0x00000034) Filter Result Register
(@ 0x00000038) Filter Result Register
(@ 0x0000003C) Filter Result Register
(@ 0x00000040) Filter Result Register
(@ 0x00000044) Filter Result Register
(@ 0x00000048) Filter Result Register
(@ 0x0000004C) Filter Result Register
(@ 0x0000005C) Result Register
(@ 0x00000060) Result Register
(@ 0x00000064) Result Register
(@ 0x00000068) Result Register
(@ 0x0000006C) Result Register
(@ 0x00000070) Result Register
(@ 0x00000074) Result Register
(@ 0x00000078) Result Register
(@ 0x0000007C) Result Register
(@ 0x00000080) Result Register
(@ 0x00000084) Result Register
(@ 0x00000088) Result Register
(@ 0x0000008C) Result Register
(@ 0x00000090) Result Register
(@ 0x00000094) Result Register
(@ 0x000000C8) Internal Configuration Register
(@ 0x00000124) Compare Status Register
__OM uint32_t reg |
(@ 0x0000009C) Compare Status Clear Register
(@ 0x000000A0) Compare Status Clear Register
union { ... } RES0 |
union { ... } RES1 |
union { ... } RES10 |
union { ... } RES11 |
union { ... } RES12 |
union { ... } RES13 |
union { ... } RES14 |
union { ... } RES2 |
union { ... } RES3 |
union { ... } RES4 |
union { ... } RES5 |
union { ... } RES6 |
union { ... } RES7 |
union { ... } RES8 |
union { ... } RES9 |
__IM uint32_t RESERVED[4] |
__IM uint32_t RESERVED1[3] |
__IM uint32_t RESERVED2 |
__IM uint32_t RESULT |
[11..0] Result Value
__IOM uint32_t RST_BLANK_TIME |
[27..27] Restart Blank time
__IOM uint32_t SLOTS |
[2..0] Number of used Slots in Sequence
__IOM uint32_t SQ0 |
[0..0] SQ 0 Interrupt Status
__IOM uint32_t SQ0CLR |
[0..0] SQ 0 Interrupt Status Clear
__IOM uint32_t SQ0SET |
[0..0] SQ 0 Interrupt Status Set
__IOM uint32_t SQ1 |
[1..1] SQ 1 Interrupt Status
__IOM uint32_t SQ1CLR |
[1..1] SQ 1 Interrupt Status Clear
__IOM uint32_t SQ1SET |
[1..1] SQ 1 Interrupt Status Set
__IOM uint32_t SQ2 |
[2..2] SQ 2 Interrupt Status
__IOM uint32_t SQ2CLR |
[2..2] SQ 2 Interrupt Status Clear
__IOM uint32_t SQ2SET |
[2..2] SQ 2 Interrupt Status Set
__IOM uint32_t SQ3 |
[3..3] SQ 3 Interrupt Status
__IOM uint32_t SQ3CLR |
[3..3] SQ 3 Interrupt Status Clear
__IOM uint32_t SQ3SET |
[3..3] SQ 3 Interrupt Status Set
union { ... } SQCFG0 |
union { ... } SQCFG1 |
union { ... } SQCFG2 |
union { ... } SQCFG3 |
__IOM uint32_t SQNUM |
[18..16] Actual Sequence processed
__IOM uint32_t SQREP |
[5..4] Sequence repetition
union { ... } SQSLOT0 |
union { ... } SQSLOT1 |
union { ... } SQSLOT2 |
union { ... } SQSLOT3 |
union { ... } SQSTAT |
union { ... } SQSTATCLR |
union { ... } SQSTATSET |
__IM uint32_t STAT |
[0..0] Suspend Mode Status
__IOM uint32_t STC |
[7..4] Sample Time config
union { ... } SUSCTR |
__IOM uint32_t SUSEN |
[0..0] ADC2 Suspend Enable
__IOM uint32_t SUSMOD |
[1..1] Suspend Mode
union { ... } SUSSTAT |
__IOM uint32_t TRGSEL |
[9..8] Trigger Select
__OM uint32_t TRGSW |
[14..14] Software Trigger Bit
__IOM uint32_t UPPER |
[23..16] Upper Compare Value
__IM uint32_t VALID |
[15..15] Valid flag