#include <tle989x.h>
◆ __pad0__
◆ __pad1__
◆ __pad2__
◆ [1/5]
◆ [2/5]
◆ [3/5]
◆ [4/5]
◆ [5/5]
◆ BUS_ACT_IEN
__IOM uint32_t BUS_ACT_IEN |
[3..3] Bus active during CAN sleep interrupt enable
◆ BUS_ACT_IS
[3..3] Bus active during CAN sleep interrupt status
◆ BUS_ACT_ISC
__OM uint32_t BUS_ACT_ISC |
[3..3] Bus active during CAN sleep interrupt status clear
◆ BUS_ACT_ISS
__OM uint32_t BUS_ACT_ISS |
[3..3] Bus active during CAN sleep interrupt status set
◆ BUS_TO_IEN
__IOM uint32_t BUS_TO_IEN |
[0..0] Bus dominant timeout interrupt enable
◆ BUS_TO_IS
[0..0] Bus dominant timeout interrupt status
◆ BUS_TO_ISC
[0..0] Bus dominant timeout interrupt status clear
◆ BUS_TO_ISS
[0..0] Bus dominant timeout interrupt status set
◆ BUS_TO_SC
[16..16] Bus dominant timeout status clear
◆ BUS_TO_SS
[16..16] Bus dominant timeout status set
◆ BUS_TO_STS
[16..16] Bus dominant timeout status
◆ EN
[0..0] CAN transceiver enable
◆ EN_TXD_TO
[8..8] Enable transmitter deactivation due to TXD dominant timeout
◆ MODE
◆ OT_IEN
[2..2] CAN overtemperature interrupt enable
◆ OT_IS
[2..2] CAN overtemperature interrupt status
◆ OT_ISC
[2..2] CAN overtemperature interrupt status clear
◆ OT_ISS
[2..2] CAN overtemperature interrupt status set
◆ OT_SC
[18..18] CAN overtemperature status clear
◆ OT_SS
[18..18] CAN overtemperature status set
◆ OT_STS
[18..18] CAN overtemperature status
◆ reg [1/2]
(@ 0x00000000) CAN transceiver control
(@ 0x00000008) CAN transceiver interrupt status register clear
(@ 0x0000000C) CAN transceiver interrupt status register set
(@ 0x00000010) CAN transceiver interrupt enable
◆ reg [2/2]
(@ 0x00000004) CAN transceiver interrupt status
◆ TSIL_EN
[9..9] Enable tsilence counter
◆ TXD_IN_SEL
__IOM uint32_t TXD_IN_SEL |
[17..16] TXD input selector
◆ TXD_TO_IEN
__IOM uint32_t TXD_TO_IEN |
[1..1] TXD dominant timeout interrupt enable
◆ TXD_TO_IS
[1..1] TXD dominant timeout interrupt status
◆ TXD_TO_ISC
[1..1] TXD dominant timeout interrupt status clear
◆ TXD_TO_ISS
[1..1] TXD dominant timeout interrupt status set
◆ TXD_TO_SC
[17..17] TXD dominant timeout status clear
◆ TXD_TO_SS
[17..17] TXD dominant timeout status set
◆ TXD_TO_STS
[17..17] TXD dominant timeout status
◆ UV_STS
[20..20] CAN supply undervoltage status
The documentation for this struct was generated from the following file: