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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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CADC1_CHCFGx | |
CADC1_CMPCFGx | |
CADC1_CONVCFGx | |
CADC1_FILx | |
CADC1_RESx | |
CADC1_SQCFGx | |
CADC1_SQSLOTx | |
CADC1_Type | ADC1 (ADC1) |
CADC2_CHCFGx | |
CADC2_CMPCFGx | |
CADC2_CONVCFGx | |
CADC2_FILx | |
CADC2_RESx | |
CADC2_SQCFGx | |
CADC2_SQSLOTx | |
CADC2_Type | ADC2 (ADC2) |
CARVG_Type | ARVG (ARVG) |
CBDRV_offState | |
CBDRV_Type | BDRV (BDRV) |
CCACHE_Type | CACHE (CACHE) |
CCANMSGOBJ0_Type | CAN Message Object 0 (CANMSGOBJ0) |
CCANMSGOBJ1_Type | CAN Message Object 1 (CANMSGOBJ1) |
CCANMSGOBJ2_Type | CAN Message Object 2 (CANMSGOBJ2) |
CCANNODE_Type | CAN Node (CANNODE) |
CCANNODEFD_Type | CAN Node FD (CANNODEFD) |
CCANTRX_Type | CANTRX (CANTRX) |
CCCU7_Type | CCU7 (CCU7) |
CCPU_Type | CPU (CPU) |
CCSACSC_Type | CSA and CSC (CSACSC) |
CDMA_entry | |
CDMA_Type | DMA (DMA) |
CGPIO_Type | GPIO (GPIO) |
CGPT12_Type | GPT12 (GPT12) |
CMEMCTRL_Type | MEMCTRL (MEMCTRL) |
CPLL_Type | PLL (PLL) |
CPMU_Type | Power Management Unit (PMU) |
CSCU_Type | SCU (SCU) |
CSDADC_Type | Sigma Delta Analog/Digital Converter (SDADC) |
CSSC0_Type | SSC0 (SSC0) |
CSSC1_Type | SSC1 (SSC1) |
CstComFrameDescriptor | |
CstComSignalDescriptor | |
CStdRealComplex | Complex type definition based on TStdReal |
CT20_Type | T20 (T20) |
CT21_Type | T21 (T21) |
CtADC1_CHCFGx | Structure for the ADC1 Channel Configuration Register |
CtADC1_CMPCFGx | Structure for the ADC1 Compare Channel 0 Control Register |
CtADC1_CONVCFGx | Structure for the ADC1 Channel Configuration Register |
CtADC1_SQCFGx | Structure for the ADC1 Sequence Configuration Register |
CtADC1_SQSLOTx | Structure for the ADC1 SQ Channel Slot Register |
CtBDRV_aseqCfg | This struct lists the configuration for adaptive sequencer for one half-bridge |
CtBDRV_constCfg | This struct lists the configuration in constant mode for one half-bridge |
CtBDRV_offState | This struct lists the off-state diagnosis status for every phase |
CtBDRV_seqCfg | This struct lists the configuration in sequencer mode for one half-bridge |
CTComplex | Complex type definition |
CtDMA_ctrl | This union and its structure lists the bit assignments for the channel_cfg memory location |
CtDMA_entry | This structure lists the DMA transfer memory locations |
CTPhaseCurr | 2 phase currents type definition |
CUART0_Type | UART0 (UART0) |
CUART1_Type | UART1 (UART1) |
CUARTx_BCON | |
Cuser_100tp_read_t | |
Cuser_100tp_write_t | |
Cuser_crypto_cbc_t | |
Cuser_crypto_cmac_t | |
Cuser_crypto_inp_buf_t | |
Cuser_crypto_io_buf_t | |
Cuser_crypto_out_buf_t | |
Cuser_key_erase_params_t | |
Cuser_key_erase_t | |
Cuser_key_t | Key data structure aligned with CFS page (ignored reserved bytes) |
Cuser_key_write_params_t | |
Cuser_key_write_t | |
Cuser_nvm_page_write_t |