Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
BDRV_Type Struct Reference

Detailed Description

BDRV (BDRV)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_EN: 1
 
      __IOM uint32_t   LS1_PWM: 1
 
      __IOM uint32_t   LS1_ON: 1
 
      __IOM uint32_t   LS1_OC_SEL: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   HS1_PWM: 1
 
      __IOM uint32_t   HS1_ON: 1
 
      __IOM uint32_t   HS1_OC_SEL: 1
 
      __IOM uint32_t   HB2_EN: 1
 
      __IOM uint32_t   LS2_PWM: 1
 
      __IOM uint32_t   LS2_ON: 1
 
      __IOM uint32_t   LS2_OC_SEL: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   HS2_PWM: 1
 
      __IOM uint32_t   HS2_ON: 1
 
      __IOM uint32_t   HS2_OC_SEL: 1
 
      __IOM uint32_t   HB3_EN: 1
 
      __IOM uint32_t   LS3_PWM: 1
 
      __IOM uint32_t   LS3_ON: 1
 
      __IOM uint32_t   LS3_OC_SEL: 1
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   HS3_PWM: 1
 
      __IOM uint32_t   HS3_ON: 1
 
      __IOM uint32_t   HS3_OC_SEL: 1
 
      __IOM uint32_t   HS1_DCS_EN: 1
 
      __IOM uint32_t   HS2_DCS_EN: 1
 
      __IOM uint32_t   HS3_DCS_EN: 1
 
      uint32_t   __pad3__: 1
 
      __IM uint32_t   SUPERR_STS: 1
 
      uint32_t   __pad4__: 3
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1ONSEQCNF: 1
 
      __IOM uint32_t   HB1OFFSEQCNF: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB2ONSEQCNF: 1
 
      __IOM uint32_t   HB2OFFSEQCNF: 1
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HB3ONSEQCNF: 1
 
      __IOM uint32_t   HB3OFFSEQCNF: 1
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   ACTDRV_DET_EN: 1
 
      uint32_t   __pad3__: 3
 
      __IOM uint32_t   DSMONVTH: 3
 
      uint32_t   __pad4__: 1
 
      __IOM uint32_t   LSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   HSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   LS_HS_BT_TFILT_SEL: 2
 
      uint32_t   __pad5__: 2
 
      __IOM uint32_t   DRV_CCP_TIMSEL: 3
 
      __IOM uint32_t   DRV_CCP_DIS: 1
 
   }   bit
 
CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_SRC_SEL: 3
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   HS1_SRC_SEL: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   LS2_SRC_SEL: 3
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   HS2_SRC_SEL: 3
 
      uint32_t   __pad3__: 1
 
      __IOM uint32_t   LS3_SRC_SEL: 3
 
      uint32_t   __pad4__: 1
 
      __IOM uint32_t   HS3_SRC_SEL: 3
 
      uint32_t   __pad5__: 9
 
   }   bit
 
PWMSRCSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_SEQMAP: 1
 
      __IM uint32_t   HB1_ACTDRV: 1
 
      uint32_t   __pad0__: 6
 
      __IOM uint32_t   HB2_SEQMAP: 1
 
      __IM uint32_t   HB2_ACTDRV: 1
 
      uint32_t   __pad1__: 6
 
      __IOM uint32_t   HB3_SEQMAP: 1
 
      __IM uint32_t   HB3_ACTDRV: 1
 
      uint32_t   __pad2__: 14
 
   }   bit
 
SEQMAP
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   DLY_DIAG_TIM: 10
 
      uint32_t   __pad0__: 6
 
      __IOM uint32_t   DLY_DIAG_CHSEL: 3
 
      __IOM uint32_t   DLY_DIAG_DIRSEL: 1
 
      uint32_t   __pad1__: 4
 
      __IM uint32_t   DLY_DIAG_STS: 1
 
      __OM uint32_t   DLY_DIAG_SCLR: 1
 
      __OM uint32_t   DLY_DIAG_SSET: 1
 
      uint32_t   __pad2__: 5
 
   }   bit
 
DLY_DIAG
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CP_EN: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   CP_RDY_EN: 1
 
      uint32_t   __pad1__: 5
 
      __IOM uint32_t   VCP_LOWTH2: 1
 
      __IOM uint32_t   VCP_LOWSRC_SEL: 1
 
      __IOM uint32_t   CPLOW_TFILT_SEL: 2
 
      uint32_t   __pad2__: 4
 
      __IOM uint32_t   CP_1STAGE: 1
 
      __IOM uint32_t   CP_STG_AUTO: 1
 
      uint32_t   __pad3__: 14
 
   }   bit
 
CP_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DITH_LOWER: 5
 
      uint32_t   __pad0__: 3
 
      __IOM uint32_t   DITH_UPPER: 5
 
      __IOM uint32_t   F_CP: 2
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   CPCLK_EN: 1
 
      __IOM uint32_t   CPCLKDIS_SET: 1
 
      uint32_t   __pad2__: 14
 
   }   bit
 
CP_CLK_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   LS1DRV_OCSDN_DIS: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   HS1DRV_OCSDN_DIS: 1
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   LS2DRV_OCSDN_DIS: 1
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS2DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   HS2DRV_OCSDN_DIS: 1
 
      uint32_t   __pad3__: 2
 
      __IOM uint32_t   LS3DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   LS3DRV_OCSDN_DIS: 1
 
      uint32_t   __pad4__: 2
 
      __IOM uint32_t   HS3DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   HS3DRV_OCSDN_DIS: 1
 
      uint32_t   __pad5__: 2
 
      __IOM uint32_t   DRVx_VCPLO_SDEN: 1
 
      __IOM uint32_t   DRVx_VCPLO_DIS: 1
 
      __IOM uint32_t   DRVx_VCPUP_DIS: 1
 
      __IOM uint32_t   DRVx_VSDLO_DIS: 1
 
      __IOM uint32_t   DRVx_VSDUP_DIS: 1
 
      uint32_t   __pad6__: 3
 
   }   bit
 
PROT_CTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   LS1_OC_STS: 1
 
      __IM uint32_t   LS1_DS_STS: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HS1_OC_STS: 1
 
      __IM uint32_t   HS1_DS_STS: 1
 
      __IM uint32_t   SH1_LOW_STS: 1
 
      __IM uint32_t   SH1_HIGH_STS: 1
 
      __IM uint32_t   LS2_OC_STS: 1
 
      __IM uint32_t   LS2_DS_STS: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   HS2_OC_STS: 1
 
      __IM uint32_t   HS2_DS_STS: 1
 
      __IM uint32_t   SH2_LOW_STS: 1
 
      __IM uint32_t   SH2_HIGH_STS: 1
 
      __IM uint32_t   LS3_OC_STS: 1
 
      __IM uint32_t   LS3_DS_STS: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HS3_OC_STS: 1
 
      __IM uint32_t   HS3_DS_STS: 1
 
      __IM uint32_t   SH3_LOW_STS: 1
 
      __IM uint32_t   SH3_HIGH_STS: 1
 
      __IM uint32_t   CP_OTSD_STS: 1
 
      __IM uint32_t   VCP_LOTH1_STS: 1
 
      __IM uint32_t   VCP_UPTH_STS: 1
 
      __IM uint32_t   VSD_LOTH_STS: 1
 
      __IM uint32_t   VSD_UPTH_STS: 1
 
      __IM uint32_t   VSD_CP1ST_STS: 1
 
      __IM uint32_t   VSD_OV_STS: 1
 
      __IM uint32_t   VCP_LOTH2_STS: 1
 
   }   bit
 
STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_SC: 1
 
      __OM uint32_t   LS1_DS_SC: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_SC: 1
 
      __OM uint32_t   HS1_DS_SC: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_SC: 1
 
      __OM uint32_t   LS2_DS_SC: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_SC: 1
 
      __OM uint32_t   HS2_DS_SC: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_SC: 1
 
      __OM uint32_t   LS3_DS_SC: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_SC: 1
 
      __OM uint32_t   HS3_DS_SC: 1
 
      uint32_t   __pad5__: 9
 
      __OM uint32_t   VCP_LOTH2_SC: 1
 
   }   bit
 
STSCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_SS: 1
 
      __OM uint32_t   LS1_DS_SS: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_SS: 1
 
      __OM uint32_t   HS1_DS_SS: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_SS: 1
 
      __OM uint32_t   LS2_DS_SS: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_SS: 1
 
      __OM uint32_t   HS2_DS_SS: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_SS: 1
 
      __OM uint32_t   LS3_DS_SS: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_SS: 1
 
      __OM uint32_t   HS3_DS_SS: 1
 
      uint32_t   __pad5__: 9
 
      __OM uint32_t   VCP_LOTH2_SS: 1
 
   }   bit
 
STSSET
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   LS1_OC_IS: 1
 
      __IM uint32_t   LS1_DS_IS: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HS1_OC_IS: 1
 
      __IM uint32_t   HS1_DS_IS: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   LS2_OC_IS: 1
 
      __IM uint32_t   LS2_DS_IS: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HS2_OC_IS: 1
 
      __IM uint32_t   HS2_DS_IS: 1
 
      uint32_t   __pad3__: 2
 
      __IM uint32_t   LS3_OC_IS: 1
 
      __IM uint32_t   LS3_DS_IS: 1
 
      uint32_t   __pad4__: 2
 
      __IM uint32_t   HS3_OC_IS: 1
 
      __IM uint32_t   HS3_DS_IS: 1
 
      uint32_t   __pad5__: 2
 
      __IM uint32_t   HB1_ASEQ_IS: 1
 
      __IM uint32_t   HB2_ASEQ_IS: 1
 
      __IM uint32_t   HB3_ASEQ_IS: 1
 
      __IM uint32_t   SEQ_ERR_IS: 1
 
      __IM uint32_t   HB1_ACTDRV_IS: 1
 
      __IM uint32_t   HB2_ACTDRV_IS: 1
 
      __IM uint32_t   HB3_ACTDRV_IS: 1
 
      __IM uint32_t   VCP_LOTH2_IS: 1
 
   }   bit
 
IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_ISC: 1
 
      __OM uint32_t   LS1_DS_ISC: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_ISC: 1
 
      __OM uint32_t   HS1_DS_ISC: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_ISC: 1
 
      __OM uint32_t   LS2_DS_ISC: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_ISC: 1
 
      __OM uint32_t   HS2_DS_ISC: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_ISC: 1
 
      __OM uint32_t   LS3_DS_ISC: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_ISC: 1
 
      __OM uint32_t   HS3_DS_ISC: 1
 
      uint32_t   __pad5__: 2
 
      __OM uint32_t   HB1_ASEQ_ISC: 1
 
      __OM uint32_t   HB2_ASEQ_ISC: 1
 
      __OM uint32_t   HB3_ASEQ_ISC: 1
 
      __OM uint32_t   SEQ_ERR_ISC: 1
 
      __OM uint32_t   HB1_ACTDRV_ISC: 1
 
      __OM uint32_t   HB2_ACTDRV_ISC: 1
 
      __OM uint32_t   HB3_ACTDRV_ISC: 1
 
      __OM uint32_t   VCP_LOTH2_ISC: 1
 
   }   bit
 
IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_ISS: 1
 
      __OM uint32_t   LS1_DS_ISS: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_ISS: 1
 
      __OM uint32_t   HS1_DS_ISS: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_ISS: 1
 
      __OM uint32_t   LS2_DS_ISS: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_ISS: 1
 
      __OM uint32_t   HS2_DS_ISS: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_ISS: 1
 
      __OM uint32_t   LS3_DS_ISS: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_ISS: 1
 
      __OM uint32_t   HS3_DS_ISS: 1
 
      uint32_t   __pad5__: 2
 
      __OM uint32_t   HB1_ASEQ_ISS: 1
 
      __OM uint32_t   HB2_ASEQ_ISS: 1
 
      __OM uint32_t   HB3_ASEQ_ISS: 1
 
      __OM uint32_t   SEQ_ERR_ISS: 1
 
      __OM uint32_t   HB1_ACTDRV_ISS: 1
 
      __OM uint32_t   HB2_ACTDRV_ISS: 1
 
      __OM uint32_t   HB3_ACTDRV_ISS: 1
 
      __OM uint32_t   VCP_LOTH2_ISS: 1
 
   }   bit
 
IRQSET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_OC_IEN: 1
 
      __IOM uint32_t   LS1_DS_IEN: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_OC_IEN: 1
 
      __IOM uint32_t   HS1_DS_IEN: 1
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_OC_IEN: 1
 
      __IOM uint32_t   LS2_DS_IEN: 1
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS2_OC_IEN: 1
 
      __IOM uint32_t   HS2_DS_IEN: 1
 
      uint32_t   __pad3__: 2
 
      __IOM uint32_t   LS3_OC_IEN: 1
 
      __IOM uint32_t   LS3_DS_IEN: 1
 
      uint32_t   __pad4__: 2
 
      __IOM uint32_t   HS3_OC_IEN: 1
 
      __IOM uint32_t   HS3_DS_IEN: 1
 
      uint32_t   __pad5__: 2
 
      __IOM uint32_t   HB1_ASEQ_IEN: 1
 
      __IOM uint32_t   HB2_ASEQ_IEN: 1
 
      __IOM uint32_t   HB3_ASEQ_IEN: 1
 
      __IOM uint32_t   SEQ_ERR_IEN: 1
 
      __IOM uint32_t   HB1_ACTDRV_IEN: 1
 
      __IOM uint32_t   HB2_ACTDRV_IEN: 1
 
      __IOM uint32_t   HB3_ACTDRV_IEN: 1
 
      __IOM uint32_t   VCP_LOTH2_IEN: 1
 
   }   bit
 
IRQEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_ICLMPON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB1_ICLMPOFF: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HB1IGATECLMPC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2_ICLMPON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB2_ICLMPOFF: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HB2IGATECLMPC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB3_ICLMPON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB3_ICLMPOFF: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HB3IGATECLMPC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_TAFOFF: 8
 
      __IOM uint32_t   LS1_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
LS1AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
LS1AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_TAFOFF: 8
 
      __IOM uint32_t   HS1_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
HS1AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HS1AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_T1OFF: 8
 
      __IOM uint32_t   LS1_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
LS1SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS1_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
LS1SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_T1ON: 8
 
      __IOM uint32_t   LS1_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS1_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
LS1SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS1_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   LS1_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
LS1SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_T1OFF: 8
 
      __IOM uint32_t   HS1_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
HS1SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS1_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
HS1SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_T1ON: 8
 
      __IOM uint32_t   HS1_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS1_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
HS1SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS1_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS1_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
HS1SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_TAFOFF: 8
 
      __IOM uint32_t   LS2_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
LS2AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
LS2AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_TAFOFF: 8
 
      __IOM uint32_t   HS2_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
HS2AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HS2AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_T1OFF: 8
 
      __IOM uint32_t   LS2_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
LS2SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
LS2SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_T1ON: 8
 
      __IOM uint32_t   LS2_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
LS2SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   LS2_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
LS2SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_T1OFF: 8
 
      __IOM uint32_t   HS2_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
HS2SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS2_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
HS2SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_T1ON: 8
 
      __IOM uint32_t   HS2_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS2_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
HS2SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS2_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS2_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
HS2SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_TAFOFF: 8
 
      __IOM uint32_t   LS3_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
LS3AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
LS3AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_TAFOFF: 8
 
      __IOM uint32_t   HS3_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
HS3AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HS3AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_T1OFF: 8
 
      __IOM uint32_t   LS3_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
LS3SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS3_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
LS3SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_T1ON: 8
 
      __IOM uint32_t   LS3_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS3_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
LS3SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS3_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   LS3_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
LS3SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_T1OFF: 8
 
      __IOM uint32_t   HS3_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
HS3SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS3_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
HS3SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_T1ON: 8
 
      __IOM uint32_t   HS3_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS3_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
HS3SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS3_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS3_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
HS3SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T4OFF: 6
 
      uint32_t   __pad0__: 10
 
      __IOM uint32_t   I4OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
SEQOFFT4I4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IHCDIS: 6
 
      uint32_t   __pad0__: 10
 
      __IOM uint32_t   HCDIS_SSO: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
HCDIS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1_TONDLY: 8
 
      __IM uint32_t   HB1_I1ONVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1_TONDUR: 6
 
      __IM uint32_t   HB1_TONDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB1_ACTDRV_ON: 1
 
      __IOM uint32_t   HB1_ONVALVF: 1
 
      __OM uint32_t   HB1_ONVALVF_CLR: 1
 
      __OM uint32_t   HB1_ONVALVF_SET: 1
 
   }   bit
 
HB1ONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1_TOFFDLY: 8
 
      __IM uint32_t   HB1_I1OFFVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1_TOFFDUR: 6
 
      __IM uint32_t   HB1_TOFFDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB1_ACTDRV_OFF: 1
 
      __IOM uint32_t   HB1_OFFVALVF: 1
 
      __OM uint32_t   HB1_OFFVALVF_CLR: 1
 
      __OM uint32_t   HB1_OFFVALVF_SET: 1
 
   }   bit
 
HB1OFFVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB2_TONDLY: 8
 
      __IM uint32_t   HB2_I1ONVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB2_TONDUR: 6
 
      __IM uint32_t   HB2_TONDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB2_ACTDRV_ON: 1
 
      __IOM uint32_t   HB2_ONVALVF: 1
 
      __OM uint32_t   HB2_ONVALVF_CLR: 1
 
      __OM uint32_t   HB2_ONVALVF_SET: 1
 
   }   bit
 
HB2ONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB2_TOFFDLY: 8
 
      __IM uint32_t   HB2_I1OFFVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB2_TOFFDUR: 6
 
      __IM uint32_t   HB2_TOFFDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB2_ACTDRV_OFF: 1
 
      __IOM uint32_t   HB2_OFFVALVF: 1
 
      __OM uint32_t   HB2_OFFVALVF_CLR: 1
 
      __OM uint32_t   HB2_OFFVALVF_SET: 1
 
   }   bit
 
HB2OFFVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB3_TONDLY: 8
 
      __IM uint32_t   HB3_I1ONVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB3_TONDUR: 6
 
      __IM uint32_t   HB3_TONDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB3_ACTDRV_ON: 1
 
      __IOM uint32_t   HB3_ONVALVF: 1
 
      __OM uint32_t   HB3_ONVALVF_CLR: 1
 
      __OM uint32_t   HB3_ONVALVF_SET: 1
 
   }   bit
 
HB3ONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB3_TOFFDLY: 8
 
      __IM uint32_t   HB3_I1OFFVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB3_TOFFDUR: 6
 
      __IM uint32_t   HB3_TOFFDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB3_ACTDRV_OFF: 1
 
      __IOM uint32_t   HB3_OFFVALVF: 1
 
      __OM uint32_t   HB3_OFFVALVF_CLR: 1
 
      __OM uint32_t   HB3_OFFVALVF_SET: 1
 
   }   bit
 
HB3OFFVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1ASMONEN: 1
 
      __IOM uint32_t   HB1ASMOFFEN: 1
 
      uint32_t   __pad0__: 4
 
      __IOM uint32_t   HB1ONHYSTEN: 1
 
      __IOM uint32_t   HB1OFFHYSTEN: 1
 
      __IOM uint32_t   HB2ASMONEN: 1
 
      __IOM uint32_t   HB2ASMOFFEN: 1
 
      uint32_t   __pad1__: 4
 
      __IOM uint32_t   HB2ONHYSTEN: 1
 
      __IOM uint32_t   HB2OFFHYSTEN: 1
 
      __IOM uint32_t   HB3ASMONEN: 1
 
      __IOM uint32_t   HB3ASMOFFEN: 1
 
      uint32_t   __pad2__: 4
 
      __IOM uint32_t   HB3ONHYSTEN: 1
 
      __IOM uint32_t   HB3OFFHYSTEN: 1
 
      uint32_t   __pad3__: 8
 
   }   bit
 
ASEQC
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1T12ONMAX: 1
 
      __IM uint32_t   HB1I1ONMAX: 1
 
      __IM uint32_t   HB1T12ONMIN: 1
 
      __IM uint32_t   HB1I1ONMIN: 1
 
      __IM uint32_t   HB1ONMF: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1ONFAILDRV: 1
 
      __IM uint32_t   HB2T12ONMAX: 1
 
      __IM uint32_t   HB2I1ONMAX: 1
 
      __IM uint32_t   HB2T12ONMIN: 1
 
      __IM uint32_t   HB2I1ONMIN: 1
 
      __IM uint32_t   HB2ONMF: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   HB2ONFAILDRV: 1
 
      __IM uint32_t   HB3T12ONMAX: 1
 
      __IM uint32_t   HB3I1ONMAX: 1
 
      __IM uint32_t   HB3T12ONMIN: 1
 
      __IM uint32_t   HB3I1ONMIN: 1
 
      __IM uint32_t   HB3ONMF: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HB3ONFAILDRV: 1
 
      uint32_t   __pad3__: 8
 
   }   bit
 
ASEQONSTS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1T1OFFMAX: 1
 
      __IM uint32_t   HB1I1OFFMAX: 1
 
      __IM uint32_t   HB1T1OFFMIN: 1
 
      __IM uint32_t   HB1I1OFFMIN: 1
 
      __IM uint32_t   HB1OFFMF: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1OFFFAILDRV: 1
 
      __IM uint32_t   HB2T1OFFMAX: 1
 
      __IM uint32_t   HB2I1OFFMAX: 1
 
      __IM uint32_t   HB2T1OFFMIN: 1
 
      __IM uint32_t   HB2I1OFFMIN: 1
 
      __IM uint32_t   HB2OFFMF: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   HB2OFFFAILDRV: 1
 
      __IM uint32_t   HB3T1OFFMAX: 1
 
      __IM uint32_t   HB3I1OFFMAX: 1
 
      __IM uint32_t   HB3T1OFFMIN: 1
 
      __IM uint32_t   HB3I1OFFMIN: 1
 
      __IM uint32_t   HB3OFFMF: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HB3OFFFAILDRV: 1
 
      uint32_t   __pad3__: 8
 
   }   bit
 
ASEQOFFSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1T1OFFERRCNT: 2
 
      __IOM uint32_t   HB1T12ONERRCNT: 2
 
      __IOM uint32_t   HB1MFERRCNT: 2
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB2T1OFFERRCNT: 2
 
      __IOM uint32_t   HB2T12ONERRCNT: 2
 
      __IOM uint32_t   HB2MFERRCNT: 2
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HB3T1OFFERRCNT: 2
 
      __IOM uint32_t   HB3T12ONERRCNT: 2
 
      __IOM uint32_t   HB3MFERRCNT: 2
 
      uint32_t   __pad2__: 10
 
   }   bit
 
ASEQERRCNT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T12ONMIN: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQONTMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T1OFFMIN: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQOFFTMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1ONMIN: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQONIMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1OFFMIN: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQOFFIMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T12ONMAX: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQONTMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T1OFFMAX: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQOFFTMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1ONMAX: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQONIMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1OFFMAX: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQOFFIMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1T1OFFADDDLY: 4
 
      __IOM uint32_t   HS1T1OFFADDDLY: 4
 
      __IOM uint32_t   LS2T1OFFADDDLY: 4
 
      __IOM uint32_t   HS2T1OFFADDDLY: 4
 
      __IOM uint32_t   LS3T1OFFADDDLY: 4
 
      __IOM uint32_t   HS3T1OFFADDDLY: 4
 
      uint32_t   __pad0__: 8
 
   }   bit
 
ASEQOFFADDDLY
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PH1_COMP_EN: 1
 
      __IOM uint32_t   PH2_COMP_EN: 1
 
      __IOM uint32_t   PH3_COMP_EN: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   PH1_COMP_DIS_SET: 1
 
      __IOM uint32_t   PH2_COMP_DIS_SET: 1
 
      __IOM uint32_t   PH3_COMP_DIS_SET: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   CMP_TFILT_SEL: 2
 
      __IOM uint32_t   TBLNK_SEL: 3
 
      __IOM uint32_t   DEMAG_FILT_BYP: 1
 
      __IOM uint32_t   BLNK_FILT_BYP: 1
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   TRIG_SEL: 2
 
      __IOM uint32_t   IN_SEL: 1
 
      __IOM uint32_t   TRIGA_SEL: 1
 
      __IOM uint32_t   TRIGB_SEL: 1
 
      uint32_t   __pad3__: 3
 
      __IOM uint32_t   SW_TRIG: 1
 
      __IM uint32_t   PH1_ZC_STS: 1
 
      __IM uint32_t   PH2_ZC_STS: 1
 
      __IM uint32_t   PH3_ZC_STS: 1
 
      uint32_t   __pad4__: 4
 
   }   bit
 
BEMFC_CTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   PH1_ZCFALL_IS: 1
 
      __IM uint32_t   PH1_ZCRISE_IS: 1
 
      __IM uint32_t   PH2_ZCFALL_IS: 1
 
      __IM uint32_t   PH2_ZCRISE_IS: 1
 
      __IM uint32_t   PH3_ZCFALL_IS: 1
 
      __IM uint32_t   PH3_ZCRISE_IS: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PH1_ZCFALL_ISC: 1
 
      __OM uint32_t   PH1_ZCRISE_ISC: 1
 
      __OM uint32_t   PH2_ZCFALL_ISC: 1
 
      __OM uint32_t   PH2_ZCRISE_ISC: 1
 
      __OM uint32_t   PH3_ZCFALL_ISC: 1
 
      __OM uint32_t   PH3_ZCRISE_ISC: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PH1_ZCFALL_ISS: 1
 
      __OM uint32_t   PH1_ZCRISE_ISS: 1
 
      __OM uint32_t   PH2_ZCFALL_ISS: 1
 
      __OM uint32_t   PH2_ZCRISE_ISS: 1
 
      __OM uint32_t   PH3_ZCFALL_ISS: 1
 
      __OM uint32_t   PH3_ZCRISE_ISS: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQSET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PH1_ZCFALL_IEN: 1
 
      __IOM uint32_t   PH1_ZCRISE_IEN: 1
 
      __IOM uint32_t   PH2_ZCFALL_IEN: 1
 
      __IOM uint32_t   PH2_ZCRISE_IEN: 1
 
      __IOM uint32_t   PH3_ZCFALL_IEN: 1
 
      __IOM uint32_t   PH3_ZCRISE_IEN: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DTB0_OUT: 2
 
      __IOM uint32_t   DTB1_OUT: 2
 
      __IOM uint32_t   DTB2_OUT: 2
 
      __IOM uint32_t   DTB3_OUT: 2
 
      __IOM uint32_t   DTB4_OUT: 2
 
      __IOM uint32_t   DTB5_OUT: 2
 
      __IOM uint32_t   ON_DTB: 1
 
      __IOM uint32_t   IDAC_DTB: 1
 
      __IOM uint32_t   IGATE_TRIM_DTB: 1
 
      __IOM uint32_t   CBIST_DTB: 1
 
      __IOM uint32_t   CP_EN_DTB: 2
 
      __IOM uint32_t   VCP_LOWTH2_DTB: 2
 
      __IOM uint32_t   VCP_TRIM_DTB: 2
 
      __IOM uint32_t   CP_1STAGE_DTB: 2
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   ATB3_SEL: 4
 
      __IOM uint32_t   MI_EN: 1
 
      __IOM uint32_t   TST_CTRL: 1
 
   }   bit
 
TCR1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PASSIVE_OFF: 1
 
      __IOM uint32_t   BLOCK_DS_MON: 1
 
      __IOM uint32_t   STRESS_GDRV: 1
 
      __IOM uint32_t   STRESS_CP: 1
 
      __IOM uint32_t   CP_STAGE_SEL: 2
 
      __IOM uint32_t   CP_REG_DIS: 1
 
      __IOM uint32_t   CPOTSD_DIS: 1
 
      __IOM uint32_t   ICHG_IDCHG: 6
 
      __IOM uint32_t   SPARE_15_14: 2
 
      __IM uint32_t   SAFE_EN_STS: 1
 
      __IM uint32_t   SAFE_SD_STS: 1
 
      uint32_t   __pad0__: 14
 
   }   bit
 
TCR2
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   THR_CNT_HS1: 8
 
      __IM uint32_t   THR_CNT_HS2: 8
 
      __IM uint32_t   THR_CNT_HS3: 8
 
      uint32_t   __pad0__: 8
 
   }   bit
 
THR_CNT_HS_BEMF
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   THR_CNT_LS1: 8
 
      __IM uint32_t   THR_CNT_LS2: 8
 
      __IM uint32_t   THR_CNT_LS3: 8
 
      uint32_t   __pad0__: 8
 
   }   bit
 
THR_CNT_LS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IRCHG_MAX_TRIM: 5
 
      __IOM uint32_t   ICHGMAX_TCTRIM: 3
 
      __IOM uint32_t   IRDISCHG_MAX_TRIM: 5
 
      __IOM uint32_t   IDISCHGMAX_TCTRIM: 3
 
      __IOM uint32_t   IRCHG_MIN_TRIM: 5
 
      __IOM uint32_t   ICHGMIN_TCTRIM: 3
 
      __IOM uint32_t   IRDISCHG_MIN_TRIM: 5
 
      __IOM uint32_t   IDISCHGMIN_TCTRIM: 3
 
   }   bit
 
TRIM_CURR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VCP_TRIM: 2
 
      uint32_t   __pad0__: 30
 
   }   bit
 
TRIM_VCP
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IDAC_SH_EN: 1
 
      __IOM uint32_t   IDAC_SH_TS: 1
 
      __IOM uint32_t   IDAC_SH_TP: 1
 
      __IOM uint32_t   SPARETRIM_7_3: 5
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   SPARETRIM_15_10: 6
 
      __IOM uint32_t   COMPENS_HS: 3
 
      __IOM uint32_t   COMPENS_LS: 3
 
      uint32_t   __pad1__: 10
 
   }   bit
 
TRIM_FUNC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_EN: 1
 
      __IOM uint32_t   LS1_PWM: 1
 
      __IOM uint32_t   LS1_ON: 1
 
      __IOM uint32_t   LS1_OC_SEL: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   HS1_PWM: 1
 
      __IOM uint32_t   HS1_ON: 1
 
      __IOM uint32_t   HS1_OC_SEL: 1
 
      __IOM uint32_t   HB2_EN: 1
 
      __IOM uint32_t   LS2_PWM: 1
 
      __IOM uint32_t   LS2_ON: 1
 
      __IOM uint32_t   LS2_OC_SEL: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   HS2_PWM: 1
 
      __IOM uint32_t   HS2_ON: 1
 
      __IOM uint32_t   HS2_OC_SEL: 1
 
      __IOM uint32_t   HB3_EN: 1
 
      __IOM uint32_t   LS3_PWM: 1
 
      __IOM uint32_t   LS3_ON: 1
 
      __IOM uint32_t   LS3_OC_SEL: 1
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   HS3_PWM: 1
 
      __IOM uint32_t   HS3_ON: 1
 
      __IOM uint32_t   HS3_OC_SEL: 1
 
      __IOM uint32_t   HS1_DCS_EN: 1
 
      __IOM uint32_t   HS2_DCS_EN: 1
 
      __IOM uint32_t   HS3_DCS_EN: 1
 
      uint32_t   __pad3__: 1
 
      __IM uint32_t   SUPERR_STS: 1
 
      uint32_t   __pad4__: 3
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1ONSEQCNF: 1
 
      __IOM uint32_t   HB1OFFSEQCNF: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB2ONSEQCNF: 1
 
      __IOM uint32_t   HB2OFFSEQCNF: 1
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HB3ONSEQCNF: 1
 
      __IOM uint32_t   HB3OFFSEQCNF: 1
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   ACTDRV_DET_EN: 1
 
      uint32_t   __pad3__: 3
 
      __IOM uint32_t   DSMONVTH: 3
 
      uint32_t   __pad4__: 1
 
      __IOM uint32_t   LSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   HSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   LS_HS_BT_TFILT_SEL: 2
 
      uint32_t   __pad5__: 2
 
      __IOM uint32_t   DRV_CCP_TIMSEL: 3
 
      __IOM uint32_t   DRV_CCP_DIS: 1
 
   }   bit
 
CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_SRC_SEL: 3
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   HS1_SRC_SEL: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   LS2_SRC_SEL: 3
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   HS2_SRC_SEL: 3
 
      uint32_t   __pad3__: 1
 
      __IOM uint32_t   LS3_SRC_SEL: 3
 
      uint32_t   __pad4__: 1
 
      __IOM uint32_t   HS3_SRC_SEL: 3
 
      uint32_t   __pad5__: 9
 
   }   bit
 
PWMSRCSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_SEQMAP: 1
 
      __IM uint32_t   HB1_ACTDRV: 1
 
      uint32_t   __pad0__: 6
 
      __IOM uint32_t   HB2_SEQMAP: 1
 
      __IM uint32_t   HB2_ACTDRV: 1
 
      uint32_t   __pad1__: 6
 
      __IOM uint32_t   HB3_SEQMAP: 1
 
      __IM uint32_t   HB3_ACTDRV: 1
 
      uint32_t   __pad2__: 14
 
   }   bit
 
SEQMAP
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   DLY_DIAG_TIM: 10
 
      uint32_t   __pad0__: 6
 
      __IOM uint32_t   DLY_DIAG_CHSEL: 3
 
      __IOM uint32_t   DLY_DIAG_DIRSEL: 1
 
      uint32_t   __pad1__: 4
 
      __IM uint32_t   DLY_DIAG_STS: 1
 
      __OM uint32_t   DLY_DIAG_SCLR: 1
 
      __OM uint32_t   DLY_DIAG_SSET: 1
 
      uint32_t   __pad2__: 5
 
   }   bit
 
DLY_DIAG
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CP_EN: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   CP_RDY_EN: 1
 
      uint32_t   __pad1__: 5
 
      __IOM uint32_t   VCP_LOWTH2: 1
 
      __IOM uint32_t   VCP_LOWSRC_SEL: 1
 
      __IOM uint32_t   CPLOW_TFILT_SEL: 2
 
      uint32_t   __pad2__: 4
 
      __IOM uint32_t   CP_1STAGE: 1
 
      __IOM uint32_t   CP_STG_AUTO: 1
 
      uint32_t   __pad3__: 14
 
   }   bit
 
CP_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DITH_LOWER: 5
 
      uint32_t   __pad0__: 3
 
      __IOM uint32_t   DITH_UPPER: 5
 
      __IOM uint32_t   F_CP: 2
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   CPCLK_EN: 1
 
      __IOM uint32_t   CPCLKDIS_SET: 1
 
      uint32_t   __pad2__: 14
 
   }   bit
 
CP_CLK_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   LS1DRV_OCSDN_DIS: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   HS1DRV_OCSDN_DIS: 1
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   LS2DRV_OCSDN_DIS: 1
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS2DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   HS2DRV_OCSDN_DIS: 1
 
      uint32_t   __pad3__: 2
 
      __IOM uint32_t   LS3DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   LS3DRV_OCSDN_DIS: 1
 
      uint32_t   __pad4__: 2
 
      __IOM uint32_t   HS3DRV_HCDISCHG_DIS: 1
 
      __IOM uint32_t   HS3DRV_OCSDN_DIS: 1
 
      uint32_t   __pad5__: 2
 
      __IOM uint32_t   DRVx_VCPLO_SDEN: 1
 
      __IOM uint32_t   DRVx_VCPLO_DIS: 1
 
      __IOM uint32_t   DRVx_VCPUP_DIS: 1
 
      __IOM uint32_t   DRVx_VSDLO_DIS: 1
 
      __IOM uint32_t   DRVx_VSDUP_DIS: 1
 
      uint32_t   __pad6__: 3
 
   }   bit
 
PROT_CTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   LS1_OC_STS: 1
 
      __IM uint32_t   LS1_DS_STS: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HS1_OC_STS: 1
 
      __IM uint32_t   HS1_DS_STS: 1
 
      __IM uint32_t   SH1_LOW_STS: 1
 
      __IM uint32_t   SH1_HIGH_STS: 1
 
      __IM uint32_t   LS2_OC_STS: 1
 
      __IM uint32_t   LS2_DS_STS: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   HS2_OC_STS: 1
 
      __IM uint32_t   HS2_DS_STS: 1
 
      __IM uint32_t   SH2_LOW_STS: 1
 
      __IM uint32_t   SH2_HIGH_STS: 1
 
      __IM uint32_t   LS3_OC_STS: 1
 
      __IM uint32_t   LS3_DS_STS: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HS3_OC_STS: 1
 
      __IM uint32_t   HS3_DS_STS: 1
 
      __IM uint32_t   SH3_LOW_STS: 1
 
      __IM uint32_t   SH3_HIGH_STS: 1
 
      __IM uint32_t   CP_OTSD_STS: 1
 
      __IM uint32_t   VCP_LOTH1_STS: 1
 
      __IM uint32_t   VCP_UPTH_STS: 1
 
      __IM uint32_t   VSD_LOTH_STS: 1
 
      __IM uint32_t   VSD_UPTH_STS: 1
 
      __IM uint32_t   VSD_CP1ST_STS: 1
 
      __IM uint32_t   VSD_OV_STS: 1
 
      __IM uint32_t   VCP_LOTH2_STS: 1
 
   }   bit
 
STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_SC: 1
 
      __OM uint32_t   LS1_DS_SC: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_SC: 1
 
      __OM uint32_t   HS1_DS_SC: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_SC: 1
 
      __OM uint32_t   LS2_DS_SC: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_SC: 1
 
      __OM uint32_t   HS2_DS_SC: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_SC: 1
 
      __OM uint32_t   LS3_DS_SC: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_SC: 1
 
      __OM uint32_t   HS3_DS_SC: 1
 
      uint32_t   __pad5__: 9
 
      __OM uint32_t   VCP_LOTH2_SC: 1
 
   }   bit
 
STSCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_SS: 1
 
      __OM uint32_t   LS1_DS_SS: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_SS: 1
 
      __OM uint32_t   HS1_DS_SS: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_SS: 1
 
      __OM uint32_t   LS2_DS_SS: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_SS: 1
 
      __OM uint32_t   HS2_DS_SS: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_SS: 1
 
      __OM uint32_t   LS3_DS_SS: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_SS: 1
 
      __OM uint32_t   HS3_DS_SS: 1
 
      uint32_t   __pad5__: 9
 
      __OM uint32_t   VCP_LOTH2_SS: 1
 
   }   bit
 
STSSET
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   LS1_OC_IS: 1
 
      __IM uint32_t   LS1_DS_IS: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HS1_OC_IS: 1
 
      __IM uint32_t   HS1_DS_IS: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   LS2_OC_IS: 1
 
      __IM uint32_t   LS2_DS_IS: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HS2_OC_IS: 1
 
      __IM uint32_t   HS2_DS_IS: 1
 
      uint32_t   __pad3__: 2
 
      __IM uint32_t   LS3_OC_IS: 1
 
      __IM uint32_t   LS3_DS_IS: 1
 
      uint32_t   __pad4__: 2
 
      __IM uint32_t   HS3_OC_IS: 1
 
      __IM uint32_t   HS3_DS_IS: 1
 
      uint32_t   __pad5__: 2
 
      __IM uint32_t   HB1_ASEQ_IS: 1
 
      __IM uint32_t   HB2_ASEQ_IS: 1
 
      __IM uint32_t   HB3_ASEQ_IS: 1
 
      __IM uint32_t   SEQ_ERR_IS: 1
 
      __IM uint32_t   HB1_ACTDRV_IS: 1
 
      __IM uint32_t   HB2_ACTDRV_IS: 1
 
      __IM uint32_t   HB3_ACTDRV_IS: 1
 
      __IM uint32_t   VCP_LOTH2_IS: 1
 
   }   bit
 
IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_ISC: 1
 
      __OM uint32_t   LS1_DS_ISC: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_ISC: 1
 
      __OM uint32_t   HS1_DS_ISC: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_ISC: 1
 
      __OM uint32_t   LS2_DS_ISC: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_ISC: 1
 
      __OM uint32_t   HS2_DS_ISC: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_ISC: 1
 
      __OM uint32_t   LS3_DS_ISC: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_ISC: 1
 
      __OM uint32_t   HS3_DS_ISC: 1
 
      uint32_t   __pad5__: 2
 
      __OM uint32_t   HB1_ASEQ_ISC: 1
 
      __OM uint32_t   HB2_ASEQ_ISC: 1
 
      __OM uint32_t   HB3_ASEQ_ISC: 1
 
      __OM uint32_t   SEQ_ERR_ISC: 1
 
      __OM uint32_t   HB1_ACTDRV_ISC: 1
 
      __OM uint32_t   HB2_ACTDRV_ISC: 1
 
      __OM uint32_t   HB3_ACTDRV_ISC: 1
 
      __OM uint32_t   VCP_LOTH2_ISC: 1
 
   }   bit
 
IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_OC_ISS: 1
 
      __OM uint32_t   LS1_DS_ISS: 1
 
      uint32_t   __pad0__: 2
 
      __OM uint32_t   HS1_OC_ISS: 1
 
      __OM uint32_t   HS1_DS_ISS: 1
 
      uint32_t   __pad1__: 2
 
      __OM uint32_t   LS2_OC_ISS: 1
 
      __OM uint32_t   LS2_DS_ISS: 1
 
      uint32_t   __pad2__: 2
 
      __OM uint32_t   HS2_OC_ISS: 1
 
      __OM uint32_t   HS2_DS_ISS: 1
 
      uint32_t   __pad3__: 2
 
      __OM uint32_t   LS3_OC_ISS: 1
 
      __OM uint32_t   LS3_DS_ISS: 1
 
      uint32_t   __pad4__: 2
 
      __OM uint32_t   HS3_OC_ISS: 1
 
      __OM uint32_t   HS3_DS_ISS: 1
 
      uint32_t   __pad5__: 2
 
      __OM uint32_t   HB1_ASEQ_ISS: 1
 
      __OM uint32_t   HB2_ASEQ_ISS: 1
 
      __OM uint32_t   HB3_ASEQ_ISS: 1
 
      __OM uint32_t   SEQ_ERR_ISS: 1
 
      __OM uint32_t   HB1_ACTDRV_ISS: 1
 
      __OM uint32_t   HB2_ACTDRV_ISS: 1
 
      __OM uint32_t   HB3_ACTDRV_ISS: 1
 
      __OM uint32_t   VCP_LOTH2_ISS: 1
 
   }   bit
 
IRQSET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_OC_IEN: 1
 
      __IOM uint32_t   LS1_DS_IEN: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_OC_IEN: 1
 
      __IOM uint32_t   HS1_DS_IEN: 1
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_OC_IEN: 1
 
      __IOM uint32_t   LS2_DS_IEN: 1
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS2_OC_IEN: 1
 
      __IOM uint32_t   HS2_DS_IEN: 1
 
      uint32_t   __pad3__: 2
 
      __IOM uint32_t   LS3_OC_IEN: 1
 
      __IOM uint32_t   LS3_DS_IEN: 1
 
      uint32_t   __pad4__: 2
 
      __IOM uint32_t   HS3_OC_IEN: 1
 
      __IOM uint32_t   HS3_DS_IEN: 1
 
      uint32_t   __pad5__: 2
 
      __IOM uint32_t   HB1_ASEQ_IEN: 1
 
      __IOM uint32_t   HB2_ASEQ_IEN: 1
 
      __IOM uint32_t   HB3_ASEQ_IEN: 1
 
      __IOM uint32_t   SEQ_ERR_IEN: 1
 
      __IOM uint32_t   HB1_ACTDRV_IEN: 1
 
      __IOM uint32_t   HB2_ACTDRV_IEN: 1
 
      __IOM uint32_t   HB3_ACTDRV_IEN: 1
 
      __IOM uint32_t   VCP_LOTH2_IEN: 1
 
   }   bit
 
IRQEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_ICLMPON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB1_ICLMPOFF: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HB1IGATECLMPC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2_ICLMPON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB2_ICLMPOFF: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HB2IGATECLMPC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB3_ICLMPON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB3_ICLMPOFF: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HB3IGATECLMPC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_TAFOFF: 8
 
      __IOM uint32_t   LS1_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
LS1AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
LS1AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_TAFOFF: 8
 
      __IOM uint32_t   HS1_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
HS1AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HS1AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_T1OFF: 8
 
      __IOM uint32_t   LS1_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
LS1SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS1_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
LS1SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_T1ON: 8
 
      __IOM uint32_t   LS1_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS1_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
LS1SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS1_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS1_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   LS1_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
LS1SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_T1OFF: 8
 
      __IOM uint32_t   HS1_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
HS1SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS1_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
HS1SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_T1ON: 8
 
      __IOM uint32_t   HS1_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS1_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
HS1SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS1_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS1_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS1_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS1_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
HS1SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_TAFOFF: 8
 
      __IOM uint32_t   LS2_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
LS2AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
LS2AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_TAFOFF: 8
 
      __IOM uint32_t   HS2_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
HS2AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HS2AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_T1OFF: 8
 
      __IOM uint32_t   LS2_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
LS2SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
LS2SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_T1ON: 8
 
      __IOM uint32_t   LS2_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
LS2SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS2_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS2_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS2_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   LS2_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
LS2SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_T1OFF: 8
 
      __IOM uint32_t   HS2_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
HS2SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS2_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
HS2SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_T1ON: 8
 
      __IOM uint32_t   HS2_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS2_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
HS2SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS2_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS2_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS2_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS2_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
HS2SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_TAFOFF: 8
 
      __IOM uint32_t   LS3_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
LS3AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
LS3AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_TAFOFF: 8
 
      __IOM uint32_t   HS3_TAFON: 8
 
      uint32_t   __pad0__: 16
 
   }   bit
 
HS3AFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_IAFOFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_IAFON: 6
 
      uint32_t   __pad1__: 18
 
   }   bit
 
HS3AFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_T1OFF: 8
 
      __IOM uint32_t   LS3_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
LS3SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS3_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
LS3SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_T1ON: 8
 
      __IOM uint32_t   LS3_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS3_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
LS3SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   LS3_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   LS3_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   LS3_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
LS3SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_T1OFF: 8
 
      __IOM uint32_t   HS3_T2OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_T3OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
HS3SEQOFFTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_I1OFF: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_I2OFF: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS3_I3OFF: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
HS3SEQOFFIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_T1ON: 8
 
      __IOM uint32_t   HS3_T2ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_T3ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS3_T4ON: 6
 
      uint32_t   __pad2__: 2
 
   }   bit
 
HS3SEQONTC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HS3_I1ON: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HS3_I2ON: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HS3_I3ON: 6
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   HS3_I4ON: 6
 
      uint32_t   __pad3__: 2
 
   }   bit
 
HS3SEQONIC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T4OFF: 6
 
      uint32_t   __pad0__: 10
 
      __IOM uint32_t   I4OFF: 6
 
      uint32_t   __pad1__: 10
 
   }   bit
 
SEQOFFT4I4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IHCDIS: 6
 
      uint32_t   __pad0__: 10
 
      __IOM uint32_t   HCDIS_SSO: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
HCDIS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1_TONDLY: 8
 
      __IM uint32_t   HB1_I1ONVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1_TONDUR: 6
 
      __IM uint32_t   HB1_TONDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB1_ACTDRV_ON: 1
 
      __IOM uint32_t   HB1_ONVALVF: 1
 
      __OM uint32_t   HB1_ONVALVF_CLR: 1
 
      __OM uint32_t   HB1_ONVALVF_SET: 1
 
   }   bit
 
HB1ONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1_TOFFDLY: 8
 
      __IM uint32_t   HB1_I1OFFVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1_TOFFDUR: 6
 
      __IM uint32_t   HB1_TOFFDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB1_ACTDRV_OFF: 1
 
      __IOM uint32_t   HB1_OFFVALVF: 1
 
      __OM uint32_t   HB1_OFFVALVF_CLR: 1
 
      __OM uint32_t   HB1_OFFVALVF_SET: 1
 
   }   bit
 
HB1OFFVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB2_TONDLY: 8
 
      __IM uint32_t   HB2_I1ONVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB2_TONDUR: 6
 
      __IM uint32_t   HB2_TONDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB2_ACTDRV_ON: 1
 
      __IOM uint32_t   HB2_ONVALVF: 1
 
      __OM uint32_t   HB2_ONVALVF_CLR: 1
 
      __OM uint32_t   HB2_ONVALVF_SET: 1
 
   }   bit
 
HB2ONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB2_TOFFDLY: 8
 
      __IM uint32_t   HB2_I1OFFVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB2_TOFFDUR: 6
 
      __IM uint32_t   HB2_TOFFDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB2_ACTDRV_OFF: 1
 
      __IOM uint32_t   HB2_OFFVALVF: 1
 
      __OM uint32_t   HB2_OFFVALVF_CLR: 1
 
      __OM uint32_t   HB2_OFFVALVF_SET: 1
 
   }   bit
 
HB2OFFVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB3_TONDLY: 8
 
      __IM uint32_t   HB3_I1ONVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB3_TONDUR: 6
 
      __IM uint32_t   HB3_TONDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB3_ACTDRV_ON: 1
 
      __IOM uint32_t   HB3_ONVALVF: 1
 
      __OM uint32_t   HB3_ONVALVF_CLR: 1
 
      __OM uint32_t   HB3_ONVALVF_SET: 1
 
   }   bit
 
HB3ONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB3_TOFFDLY: 8
 
      __IM uint32_t   HB3_I1OFFVAL: 6
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB3_TOFFDUR: 6
 
      __IM uint32_t   HB3_TOFFDURMERR: 1
 
      uint32_t   __pad1__: 5
 
      __IM uint32_t   HB3_ACTDRV_OFF: 1
 
      __IOM uint32_t   HB3_OFFVALVF: 1
 
      __OM uint32_t   HB3_OFFVALVF_CLR: 1
 
      __OM uint32_t   HB3_OFFVALVF_SET: 1
 
   }   bit
 
HB3OFFVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1ASMONEN: 1
 
      __IOM uint32_t   HB1ASMOFFEN: 1
 
      uint32_t   __pad0__: 4
 
      __IOM uint32_t   HB1ONHYSTEN: 1
 
      __IOM uint32_t   HB1OFFHYSTEN: 1
 
      __IOM uint32_t   HB2ASMONEN: 1
 
      __IOM uint32_t   HB2ASMOFFEN: 1
 
      uint32_t   __pad1__: 4
 
      __IOM uint32_t   HB2ONHYSTEN: 1
 
      __IOM uint32_t   HB2OFFHYSTEN: 1
 
      __IOM uint32_t   HB3ASMONEN: 1
 
      __IOM uint32_t   HB3ASMOFFEN: 1
 
      uint32_t   __pad2__: 4
 
      __IOM uint32_t   HB3ONHYSTEN: 1
 
      __IOM uint32_t   HB3OFFHYSTEN: 1
 
      uint32_t   __pad3__: 8
 
   }   bit
 
ASEQC
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1T12ONMAX: 1
 
      __IM uint32_t   HB1I1ONMAX: 1
 
      __IM uint32_t   HB1T12ONMIN: 1
 
      __IM uint32_t   HB1I1ONMIN: 1
 
      __IM uint32_t   HB1ONMF: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1ONFAILDRV: 1
 
      __IM uint32_t   HB2T12ONMAX: 1
 
      __IM uint32_t   HB2I1ONMAX: 1
 
      __IM uint32_t   HB2T12ONMIN: 1
 
      __IM uint32_t   HB2I1ONMIN: 1
 
      __IM uint32_t   HB2ONMF: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   HB2ONFAILDRV: 1
 
      __IM uint32_t   HB3T12ONMAX: 1
 
      __IM uint32_t   HB3I1ONMAX: 1
 
      __IM uint32_t   HB3T12ONMIN: 1
 
      __IM uint32_t   HB3I1ONMIN: 1
 
      __IM uint32_t   HB3ONMF: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HB3ONFAILDRV: 1
 
      uint32_t   __pad3__: 8
 
   }   bit
 
ASEQONSTS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1T1OFFMAX: 1
 
      __IM uint32_t   HB1I1OFFMAX: 1
 
      __IM uint32_t   HB1T1OFFMIN: 1
 
      __IM uint32_t   HB1I1OFFMIN: 1
 
      __IM uint32_t   HB1OFFMF: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   HB1OFFFAILDRV: 1
 
      __IM uint32_t   HB2T1OFFMAX: 1
 
      __IM uint32_t   HB2I1OFFMAX: 1
 
      __IM uint32_t   HB2T1OFFMIN: 1
 
      __IM uint32_t   HB2I1OFFMIN: 1
 
      __IM uint32_t   HB2OFFMF: 1
 
      uint32_t   __pad1__: 2
 
      __IM uint32_t   HB2OFFFAILDRV: 1
 
      __IM uint32_t   HB3T1OFFMAX: 1
 
      __IM uint32_t   HB3I1OFFMAX: 1
 
      __IM uint32_t   HB3T1OFFMIN: 1
 
      __IM uint32_t   HB3I1OFFMIN: 1
 
      __IM uint32_t   HB3OFFMF: 1
 
      uint32_t   __pad2__: 2
 
      __IM uint32_t   HB3OFFFAILDRV: 1
 
      uint32_t   __pad3__: 8
 
   }   bit
 
ASEQOFFSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1T1OFFERRCNT: 2
 
      __IOM uint32_t   HB1T12ONERRCNT: 2
 
      __IOM uint32_t   HB1MFERRCNT: 2
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   HB2T1OFFERRCNT: 2
 
      __IOM uint32_t   HB2T12ONERRCNT: 2
 
      __IOM uint32_t   HB2MFERRCNT: 2
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HB3T1OFFERRCNT: 2
 
      __IOM uint32_t   HB3T12ONERRCNT: 2
 
      __IOM uint32_t   HB3MFERRCNT: 2
 
      uint32_t   __pad2__: 10
 
   }   bit
 
ASEQERRCNT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T12ONMIN: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQONTMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T1OFFMIN: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQOFFTMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1ONMIN: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQONIMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1OFFMIN: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQOFFIMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T12ONMAX: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQONTMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T1OFFMAX: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
ASEQOFFTMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1ONMAX: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQONIMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1OFFMAX: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ASEQOFFIMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1T1OFFADDDLY: 4
 
      __IOM uint32_t   HS1T1OFFADDDLY: 4
 
      __IOM uint32_t   LS2T1OFFADDDLY: 4
 
      __IOM uint32_t   HS2T1OFFADDDLY: 4
 
      __IOM uint32_t   LS3T1OFFADDDLY: 4
 
      __IOM uint32_t   HS3T1OFFADDDLY: 4
 
      uint32_t   __pad0__: 8
 
   }   bit
 
ASEQOFFADDDLY
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PH1_COMP_EN: 1
 
      __IOM uint32_t   PH2_COMP_EN: 1
 
      __IOM uint32_t   PH3_COMP_EN: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   PH1_COMP_DIS_SET: 1
 
      __IOM uint32_t   PH2_COMP_DIS_SET: 1
 
      __IOM uint32_t   PH3_COMP_DIS_SET: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   CMP_TFILT_SEL: 2
 
      __IOM uint32_t   TBLNK_SEL: 3
 
      __IOM uint32_t   DEMAG_FILT_BYP: 1
 
      __IOM uint32_t   BLNK_FILT_BYP: 1
 
      uint32_t   __pad2__: 1
 
      __IOM uint32_t   TRIG_SEL: 2
 
      __IOM uint32_t   IN_SEL: 1
 
      __IOM uint32_t   TRIGA_SEL: 1
 
      __IOM uint32_t   TRIGB_SEL: 1
 
      uint32_t   __pad3__: 3
 
      __IOM uint32_t   SW_TRIG: 1
 
      __IM uint32_t   PH1_ZC_STS: 1
 
      __IM uint32_t   PH2_ZC_STS: 1
 
      __IM uint32_t   PH3_ZC_STS: 1
 
      uint32_t   __pad4__: 4
 
   }   bit
 
BEMFC_CTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   PH1_ZCFALL_IS: 1
 
      __IM uint32_t   PH1_ZCRISE_IS: 1
 
      __IM uint32_t   PH2_ZCFALL_IS: 1
 
      __IM uint32_t   PH2_ZCRISE_IS: 1
 
      __IM uint32_t   PH3_ZCFALL_IS: 1
 
      __IM uint32_t   PH3_ZCRISE_IS: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PH1_ZCFALL_ISC: 1
 
      __OM uint32_t   PH1_ZCRISE_ISC: 1
 
      __OM uint32_t   PH2_ZCFALL_ISC: 1
 
      __OM uint32_t   PH2_ZCRISE_ISC: 1
 
      __OM uint32_t   PH3_ZCFALL_ISC: 1
 
      __OM uint32_t   PH3_ZCRISE_ISC: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PH1_ZCFALL_ISS: 1
 
      __OM uint32_t   PH1_ZCRISE_ISS: 1
 
      __OM uint32_t   PH2_ZCFALL_ISS: 1
 
      __OM uint32_t   PH2_ZCRISE_ISS: 1
 
      __OM uint32_t   PH3_ZCFALL_ISS: 1
 
      __OM uint32_t   PH3_ZCRISE_ISS: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQSET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PH1_ZCFALL_IEN: 1
 
      __IOM uint32_t   PH1_ZCRISE_IEN: 1
 
      __IOM uint32_t   PH2_ZCFALL_IEN: 1
 
      __IOM uint32_t   PH2_ZCRISE_IEN: 1
 
      __IOM uint32_t   PH3_ZCFALL_IEN: 1
 
      __IOM uint32_t   PH3_ZCRISE_IEN: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
BEMFC_IRQEN
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆ __pad4__

uint32_t __pad4__

◆ __pad5__

uint32_t __pad5__

◆ __pad6__

uint32_t __pad6__

◆ ACTDRV_DET_EN

__IOM uint32_t ACTDRV_DET_EN

[12..12] Detection of active / free-wheeling MOSFET

◆  [1/2]

union { ... } ASEQC

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union { ... } ASEQC

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union { ... } ASEQERRCNT

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union { ... } ASEQERRCNT

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union { ... } ASEQOFFADDDLY

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union { ... } ASEQOFFADDDLY

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union { ... } ASEQOFFIMAX

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union { ... } ASEQOFFIMAX

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union { ... } ASEQOFFIMIN

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union { ... } ASEQOFFIMIN

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union { ... } ASEQOFFSTS

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union { ... } ASEQOFFSTS

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union { ... } ASEQOFFTMAX

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union { ... } ASEQOFFTMAX

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union { ... } ASEQOFFTMIN

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union { ... } ASEQOFFTMIN

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union { ... } ASEQONIMAX

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union { ... } ASEQONIMAX

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union { ... } ASEQONIMIN

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union { ... } ASEQONIMIN

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union { ... } ASEQONSTS

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union { ... } ASEQONSTS

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union { ... } ASEQONTMAX

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union { ... } ASEQONTMAX

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union { ... } ASEQONTMIN

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union { ... } ASEQONTMIN

◆ ATB3_SEL

__IOM uint32_t ATB3_SEL

[29..26] ATB3 bus assignment

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union { ... } BEMFC_CTRL

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union { ... } BEMFC_CTRL

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union { ... } BEMFC_IRQCLR

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union { ... } BEMFC_IRQCLR

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union { ... } BEMFC_IRQEN

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union { ... } BEMFC_IRQEN

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union { ... } BEMFC_IRQS

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union { ... } BEMFC_IRQS

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union { ... } BEMFC_IRQSET

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union { ... } BEMFC_IRQSET

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◆ BLNK_FILT_BYP

__IOM uint32_t BLNK_FILT_BYP

[14..14] Blanking time and demagnetisation filter bypass

◆ BLOCK_DS_MON

__IOM uint32_t BLOCK_DS_MON

[1..1] Drain-source monitoring signal blocking

◆ CBIST_DTB

__IOM uint32_t CBIST_DTB

[15..15] Comparator counter BIST DTB input assignment

◆ CMP_TFILT_SEL

__IOM uint32_t CMP_TFILT_SEL

[9..8] Symmetrical spike filter time for BEMF comparators

◆ COMPENS_HS

__IOM uint32_t COMPENS_HS

[18..16] Gain settings for high-side charge current compensation

◆ COMPENS_LS

__IOM uint32_t COMPENS_LS

[21..19] Gain settings for low-side charge current compensation

◆ CP_1STAGE

__IOM uint32_t CP_1STAGE

[16..16] Charge pump 1-stage mode select

◆ CP_1STAGE_DTB

__IOM uint32_t CP_1STAGE_DTB

[23..22] CP stage setting DTB input assignment

◆  [1/2]

union { ... } CP_CLK_CTRL

◆  [2/2]

union { ... } CP_CLK_CTRL

◆  [1/2]

union { ... } CP_CTRL

◆  [2/2]

union { ... } CP_CTRL

◆ CP_EN

__IOM uint32_t CP_EN

[0..0] Charge pump enable

◆ CP_EN_DTB

__IOM uint32_t CP_EN_DTB

[17..16] CP enable DTB input assignment

◆ CP_OTSD_STS

__IM uint32_t CP_OTSD_STS

[24..24] Charge pump temperature measurement status

◆ CP_RDY_EN

__IOM uint32_t CP_RDY_EN

[2..2] Bridge driver on charge pump ready enable

◆ CP_REG_DIS

__IOM uint32_t CP_REG_DIS

[6..6] Charge pump regulation disable

◆ CP_STAGE_SEL

__IOM uint32_t CP_STAGE_SEL

[5..4] Charge pump stage select

◆ CP_STG_AUTO

__IOM uint32_t CP_STG_AUTO

[17..17] Automatic switch to 1-stage mode and back to 2-stage mode depending on VSD

◆ CPCLK_EN

__IOM uint32_t CPCLK_EN

[16..16] Charge pump clock enable

◆ CPCLKDIS_SET

__IOM uint32_t CPCLKDIS_SET

[17..17] Charge pump clock value if disabled

◆ CPLOW_TFILT_SEL

__IOM uint32_t CPLOW_TFILT_SEL

[11..10] Filter time for charge pump voltage low diagnosis

◆ CPOTSD_DIS

__IOM uint32_t CPOTSD_DIS

[7..7] Charge pump overtemperature shutdown disable

◆  [1/2]

union { ... } CTRL1

◆  [2/2]

union { ... } CTRL1

◆  [1/2]

union { ... } CTRL2

◆  [2/2]

union { ... } CTRL2

◆ DEMAG_FILT_BYP

__IOM uint32_t DEMAG_FILT_BYP

[13..13] Demagnetisation filter bypass

◆ DITH_LOWER

__IOM uint32_t DITH_LOWER

[4..0] CP clock divider boundary for lower frequency during dithering

◆ DITH_UPPER

__IOM uint32_t DITH_UPPER

[12..8] CP clock divider boundary for upper frequency during dithering

◆  [1/2]

union { ... } DLY_DIAG

◆  [2/2]

union { ... } DLY_DIAG

◆ DLY_DIAG_CHSEL

__IOM uint32_t DLY_DIAG_CHSEL

[18..16] External power MOSFET switch-on/-off timer channel select

◆ DLY_DIAG_DIRSEL

__IOM uint32_t DLY_DIAG_DIRSEL

[19..19] External power MOSFET timer on/off select

◆ DLY_DIAG_SCLR

__OM uint32_t DLY_DIAG_SCLR

[25..25] External power MOSFET switch-on/-off timer valid flag clear

◆ DLY_DIAG_SSET

__OM uint32_t DLY_DIAG_SSET

[26..26] External power MOSFET switch-on/-off timer valid flag set

◆ DLY_DIAG_STS

__IM uint32_t DLY_DIAG_STS

[24..24] External power MOSFET switch-on/-off timer valid flag

◆ DLY_DIAG_TIM

__IM uint32_t DLY_DIAG_TIM

[9..0] External power MOSFET switch-on/-off timer result register

◆ DRV_CCP_DIS

__IOM uint32_t DRV_CCP_DIS

[31..31] Dynamic cross-conduction protection disable

◆ DRV_CCP_TIMSEL

__IOM uint32_t DRV_CCP_TIMSEL

[30..28] Minimum cross-conduction protection time setting

◆ DRVx_VCPLO_DIS

__IOM uint32_t DRVx_VCPLO_DIS

[25..25] Disable driver discharge on charge pump low voltage

◆ DRVx_VCPLO_SDEN

__IOM uint32_t DRVx_VCPLO_SDEN

[24..24] Driver shutdown on charge pump low voltage

◆ DRVx_VCPUP_DIS

__IOM uint32_t DRVx_VCPUP_DIS

[26..26] Disable driver discharge on charge pump high voltage

◆ DRVx_VSDLO_DIS

__IOM uint32_t DRVx_VSDLO_DIS

[27..27] Disable driver discharge on VSD low voltage

◆ DRVx_VSDUP_DIS

__IOM uint32_t DRVx_VSDUP_DIS

[28..28] Disable driver discharge on VSD high voltage

◆ DSMONVTH

__IOM uint32_t DSMONVTH

[18..16] Voltage threshold for drain-source monitoring of external MOSFETs

◆ DTB0_OUT

__IOM uint32_t DTB0_OUT

[1..0] DTB0 output assignment

◆ DTB1_OUT

__IOM uint32_t DTB1_OUT

[3..2] DTB1 output assignment

◆ DTB2_OUT

__IOM uint32_t DTB2_OUT

[5..4] DTB2 output assignment

◆ DTB3_OUT

__IOM uint32_t DTB3_OUT

[7..6] DTB3 output assignment

◆ DTB4_OUT

__IOM uint32_t DTB4_OUT

[9..8] DTB4 output assignment

◆ DTB5_OUT

__IOM uint32_t DTB5_OUT

[11..10] DTB5 output assignment

◆ F_CP

__IOM uint32_t F_CP

[14..13] MSB of CP clock divider

◆ HB1_ACTDRV

__IM uint32_t HB1_ACTDRV

[1..1] Half bridge 1 active driver detected at switch-on

◆ HB1_ACTDRV_IEN

__IOM uint32_t HB1_ACTDRV_IEN

[28..28] Half bridge 1 active driver detection interrupt enable

◆ HB1_ACTDRV_IS

__IM uint32_t HB1_ACTDRV_IS

[28..28] Half bridge 1 active driver detection interrupt status

◆ HB1_ACTDRV_ISC

__OM uint32_t HB1_ACTDRV_ISC

[28..28] Half bridge 1 active driver detection interrupt status clear

◆ HB1_ACTDRV_ISS

__OM uint32_t HB1_ACTDRV_ISS

[28..28] Half bridge 1 active driver detection interrupt status set

◆ HB1_ACTDRV_OFF

__IM uint32_t HB1_ACTDRV_OFF

[28..28] Half bridge 1 switch-off active driver

◆ HB1_ACTDRV_ON

__IM uint32_t HB1_ACTDRV_ON

[28..28] Half bridge 1 switch-on active driver

◆ HB1_ASEQ_IEN

__IOM uint32_t HB1_ASEQ_IEN

[24..24] Half bridge 1 adaptive sequencer interrupt enable

◆ HB1_ASEQ_IS

__IM uint32_t HB1_ASEQ_IS

[24..24] Half bridge 1 adaptive sequencer interrupt status

◆ HB1_ASEQ_ISC

__OM uint32_t HB1_ASEQ_ISC

[24..24] Half bridge 1 adaptive sequencer interrupt status clear

◆ HB1_ASEQ_ISS

__OM uint32_t HB1_ASEQ_ISS

[24..24] Half bridge 1 adaptive sequencer interrupt status set

◆ HB1_EN

__IOM uint32_t HB1_EN

[0..0] Half bridge 1 enable

◆ HB1_I1OFFVAL

__IM uint32_t HB1_I1OFFVAL

[13..8] Half bridge 1 switch-off phase 1 current setting from adaptive sequencer

◆ HB1_I1ONVAL

__IM uint32_t HB1_I1ONVAL

[13..8] Half bridge 1 switch-on phase 1 current setting from adaptive sequencer

◆ HB1_ICLMPOFF

__IOM uint32_t HB1_ICLMPOFF

[13..8] Half bridge 1 current clamping value for off state

◆ HB1_ICLMPON

__IOM uint32_t HB1_ICLMPON

[5..0] Half bridge 1 current clamping value for on state

◆ HB1_OFFVALVF

__IOM uint32_t HB1_OFFVALVF

[29..29] Half bridge 1 switch-off measurement values valid flag

◆ HB1_OFFVALVF_CLR

__OM uint32_t HB1_OFFVALVF_CLR

[30..30] Half bridge 1 switch-off measurement values valid flag clear

◆ HB1_OFFVALVF_SET

__OM uint32_t HB1_OFFVALVF_SET

[31..31] Half bridge 1 switch-off measurement values valid flag set

◆ HB1_ONVALVF

__IOM uint32_t HB1_ONVALVF

[29..29] Half bridge 1 switch-on measurement values valid flag

◆ HB1_ONVALVF_CLR

__OM uint32_t HB1_ONVALVF_CLR

[30..30] Half bridge 1 switch-on measurement values valid flag clear

◆ HB1_ONVALVF_SET

__OM uint32_t HB1_ONVALVF_SET

[31..31] Half bridge 1 switch-on measurement values valid flag set

◆ HB1_SEQMAP

__IOM uint32_t HB1_SEQMAP

[0..0] Half bridge 1 sequencer mapping

◆ HB1_TOFFDLY

__IM uint32_t HB1_TOFFDLY

[7..0] Half bridge 1 switch-off delay time value measured until VSH voltage starts to change

◆ HB1_TOFFDUR

__IM uint32_t HB1_TOFFDUR

[21..16] Half bridge 1 switch-off voltage slope duration time value

◆ HB1_TOFFDURMERR

__IM uint32_t HB1_TOFFDURMERR

[22..22] Half bridge 1 switch-off voltage slope time measurement error

◆ HB1_TONDLY

__IM uint32_t HB1_TONDLY

[7..0] Half bridge 1 switch-on delay time value measured until VSH voltage starts to change

◆ HB1_TONDUR

__IM uint32_t HB1_TONDUR

[21..16] Half bridge 1 switch-on voltage slope duration time value

◆ HB1_TONDURMERR

__IM uint32_t HB1_TONDURMERR

[22..22] Half bridge 1 switch-on voltage slope time measurement error

◆ HB1ASMOFFEN

__IOM uint32_t HB1ASMOFFEN

[1..1] Half bridge 1 adaptive sequencer for switch-off

◆ HB1ASMONEN

__IOM uint32_t HB1ASMONEN

[0..0] Half bridge 1 adaptive sequencer for switch-on

◆ HB1I1OFFMAX

__IM uint32_t HB1I1OFFMAX

[1..1] Half bridge 1 max I1OFF value reached

◆ HB1I1OFFMIN

__IM uint32_t HB1I1OFFMIN

[3..3] Half bridge 1 min I1OFF value reached

◆ HB1I1ONMAX

__IM uint32_t HB1I1ONMAX

[1..1] Half bridge 1 max I1ON value reached

◆ HB1I1ONMIN

__IM uint32_t HB1I1ONMIN

[3..3] Half bridge 1 min I1ON value reached

◆  [1/2]

union { ... } HB1IGATECLMPC

◆  [2/2]

union { ... } HB1IGATECLMPC

◆ HB1MFERRCNT

__IOM uint32_t HB1MFERRCNT

[5..4] Half bridge 1 measurement failure error counter setting

◆ HB1OFFFAILDRV

__IM uint32_t HB1OFFFAILDRV

[7..7] Half bridge 1 switch-off failed gate driver

◆ HB1OFFHYSTEN

__IOM uint32_t HB1OFFHYSTEN

[7..7] Half bridge 1 optimizer hysteresis for switch-off

◆ HB1OFFMF

__IM uint32_t HB1OFFMF

[4..4] Half bridge 1 adaptive sequencer switch-off measurement failure

◆ HB1OFFSEQCNF

__IOM uint32_t HB1OFFSEQCNF

[1..1] Half bridge 1 sequencer switch-off configuration

◆  [1/2]

union { ... } HB1OFFVAL

◆  [2/2]

union { ... } HB1OFFVAL

◆ HB1ONFAILDRV

__IM uint32_t HB1ONFAILDRV

[7..7] Half bridge 1 switch-on failed gate driver

◆ HB1ONHYSTEN

__IOM uint32_t HB1ONHYSTEN

[6..6] Half bridge 1 optimizer hysteresis for switch-on

◆ HB1ONMF

__IM uint32_t HB1ONMF

[4..4] Half bridge 1 adaptive sequencer switch-on measurement failure

◆ HB1ONSEQCNF

__IOM uint32_t HB1ONSEQCNF

[0..0] Half bridge 1 sequencer switch-on configuration

◆  [1/2]

union { ... } HB1ONVAL

◆  [2/2]

union { ... } HB1ONVAL

◆ HB1T12ONERRCNT

__IOM uint32_t HB1T12ONERRCNT

[3..2] Half bridge 1 T12ON error counter setting

◆ HB1T12ONMAX

__IM uint32_t HB1T12ONMAX

[0..0] Half bridge 1 max T12ON value reached

◆ HB1T12ONMIN

__IM uint32_t HB1T12ONMIN

[2..2] Half bridge 1 min T12ON value reached

◆ HB1T1OFFERRCNT

__IOM uint32_t HB1T1OFFERRCNT

[1..0] Half bridge 1 T1OFF error counter setting

◆ HB1T1OFFMAX

__IM uint32_t HB1T1OFFMAX

[0..0] Half bridge 1 max T1OFF value reached

◆ HB1T1OFFMIN

__IM uint32_t HB1T1OFFMIN

[2..2] Half bridge 1 min T1OFF value reached

◆ HB2_ACTDRV

__IM uint32_t HB2_ACTDRV

[9..9] Half bridge 2 active driver detected at switch-on

◆ HB2_ACTDRV_IEN

__IOM uint32_t HB2_ACTDRV_IEN

[29..29] Half bridge 2 active driver detection interrupt enable

◆ HB2_ACTDRV_IS

__IM uint32_t HB2_ACTDRV_IS

[29..29] Half bridge 2 active driver detection interrupt status

◆ HB2_ACTDRV_ISC

__OM uint32_t HB2_ACTDRV_ISC

[29..29] Half bridge 2 active driver detection interrupt status clear

◆ HB2_ACTDRV_ISS

__OM uint32_t HB2_ACTDRV_ISS

[29..29] Half bridge 2 active driver detection interrupt status set

◆ HB2_ACTDRV_OFF

__IM uint32_t HB2_ACTDRV_OFF

[28..28] Half bridge 2 switch-off active driver

◆ HB2_ACTDRV_ON

__IM uint32_t HB2_ACTDRV_ON

[28..28] Half bridge 2 switch-on active driver

◆ HB2_ASEQ_IEN

__IOM uint32_t HB2_ASEQ_IEN

[25..25] Half bridge 2 adaptive sequencer interrupt enable

◆ HB2_ASEQ_IS

__IM uint32_t HB2_ASEQ_IS

[25..25] Half bridge 2 adaptive sequencer interrupt status

◆ HB2_ASEQ_ISC

__OM uint32_t HB2_ASEQ_ISC

[25..25] Half bridge 2 adaptive sequencer interrupt status clear

◆ HB2_ASEQ_ISS

__OM uint32_t HB2_ASEQ_ISS

[25..25] Half bridge 2 adaptive sequencer interrupt status set

◆ HB2_EN

__IOM uint32_t HB2_EN

[8..8] Half bridge 2 enable

◆ HB2_I1OFFVAL

__IM uint32_t HB2_I1OFFVAL

[13..8] Half bridge 2 switch-off phase 1 current setting from adaptive sequencer

◆ HB2_I1ONVAL

__IM uint32_t HB2_I1ONVAL

[13..8] Half bridge 2 switch-on phase 1 current setting from adaptive sequencer

◆ HB2_ICLMPOFF

__IOM uint32_t HB2_ICLMPOFF

[13..8] Half bridge 2 current clamping value for off state

◆ HB2_ICLMPON

__IOM uint32_t HB2_ICLMPON

[5..0] Half bridge 2 current clamping value for on state

◆ HB2_OFFVALVF

__IOM uint32_t HB2_OFFVALVF

[29..29] Half bridge 2 switch-off measurement values valid flag

◆ HB2_OFFVALVF_CLR

__OM uint32_t HB2_OFFVALVF_CLR

[30..30] Half bridge 2 switch-off measurement values valid flag clear

◆ HB2_OFFVALVF_SET

__OM uint32_t HB2_OFFVALVF_SET

[31..31] Half bridge 2 switch-off measurement values valid flag set

◆ HB2_ONVALVF

__IOM uint32_t HB2_ONVALVF

[29..29] Half bridge 2 switch-on measurement values valid flag

◆ HB2_ONVALVF_CLR

__OM uint32_t HB2_ONVALVF_CLR

[30..30] Half bridge 2 switch-on measurement values valid flag clear

◆ HB2_ONVALVF_SET

__OM uint32_t HB2_ONVALVF_SET

[31..31] Half bridge 2 switch-on measurement values valid flag set

◆ HB2_SEQMAP

__IOM uint32_t HB2_SEQMAP

[8..8] Half bridge 2 sequencer mapping

◆ HB2_TOFFDLY

__IM uint32_t HB2_TOFFDLY

[7..0] Half bridge 2 switch-off delay time value measured until VSH voltage starts to change

◆ HB2_TOFFDUR

__IM uint32_t HB2_TOFFDUR

[21..16] Half bridge 2 switch-off voltage slope duration time value

◆ HB2_TOFFDURMERR

__IM uint32_t HB2_TOFFDURMERR

[22..22] Half bridge 2 switch-off voltage slope time measurement error

◆ HB2_TONDLY

__IM uint32_t HB2_TONDLY

[7..0] Half bridge 2 switch-on delay time value measured until VSH voltage starts to change

◆ HB2_TONDUR

__IM uint32_t HB2_TONDUR

[21..16] Half bridge 2 switch-on voltage slope duration time value

◆ HB2_TONDURMERR

__IM uint32_t HB2_TONDURMERR

[22..22] Half bridge 2 switch-on voltage slope time measurement error

◆ HB2ASMOFFEN

__IOM uint32_t HB2ASMOFFEN

[9..9] Half bridge 2 adaptive sequencer for switch-off

◆ HB2ASMONEN

__IOM uint32_t HB2ASMONEN

[8..8] Half bridge 2 adaptive sequencer for switch-on

◆ HB2I1OFFMAX

__IM uint32_t HB2I1OFFMAX

[9..9] Half bridge 2 max I1OFF value reached

◆ HB2I1OFFMIN

__IM uint32_t HB2I1OFFMIN

[11..11] Half bridge 2 min I1OFF value reached

◆ HB2I1ONMAX

__IM uint32_t HB2I1ONMAX

[9..9] Half bridge 2 max I1ON value reached

◆ HB2I1ONMIN

__IM uint32_t HB2I1ONMIN

[11..11] Half bridge 2 min I1ON value reached

◆  [1/2]

union { ... } HB2IGATECLMPC

◆  [2/2]

union { ... } HB2IGATECLMPC

◆ HB2MFERRCNT

__IOM uint32_t HB2MFERRCNT

[13..12] Half bridge 2 measurement failure error counter setting

◆ HB2OFFFAILDRV

__IM uint32_t HB2OFFFAILDRV

[15..15] Half bridge 2 switch-off failed gate driver

◆ HB2OFFHYSTEN

__IOM uint32_t HB2OFFHYSTEN

[15..15] Half bridge 2 optimizer hysteresis for switch-off

◆ HB2OFFMF

__IM uint32_t HB2OFFMF

[12..12] Half bridge 2 adaptive sequencer switch-off measurement failure

◆ HB2OFFSEQCNF

__IOM uint32_t HB2OFFSEQCNF

[5..5] Half bridge 2 sequencer switch-off configuration

◆  [1/2]

union { ... } HB2OFFVAL

◆  [2/2]

union { ... } HB2OFFVAL

◆ HB2ONFAILDRV

__IM uint32_t HB2ONFAILDRV

[15..15] Half bridge 2 switch-on failed gate driver

◆ HB2ONHYSTEN

__IOM uint32_t HB2ONHYSTEN

[14..14] Half bridge 2 optimizer hysteresis for switch-on

◆ HB2ONMF

__IM uint32_t HB2ONMF

[12..12] Half bridge 2 adaptive sequencer switch-on measurement failure

◆ HB2ONSEQCNF

__IOM uint32_t HB2ONSEQCNF

[4..4] Half bridge 2 sequencer switch-on configuration

◆  [1/2]

union { ... } HB2ONVAL

◆  [2/2]

union { ... } HB2ONVAL

◆ HB2T12ONERRCNT

__IOM uint32_t HB2T12ONERRCNT

[11..10] Half bridge 2 T12ON error counter setting

◆ HB2T12ONMAX

__IM uint32_t HB2T12ONMAX

[8..8] Half bridge 2 max T12ON value reached

◆ HB2T12ONMIN

__IM uint32_t HB2T12ONMIN

[10..10] Half bridge 2 min T12ON value reached

◆ HB2T1OFFERRCNT

__IOM uint32_t HB2T1OFFERRCNT

[9..8] Half bridge 2 T1OFF error counter setting

◆ HB2T1OFFMAX

__IM uint32_t HB2T1OFFMAX

[8..8] Half bridge 2 max T1OFF value reached

◆ HB2T1OFFMIN

__IM uint32_t HB2T1OFFMIN

[10..10] Half bridge 2 min T1OFF value reached

◆ HB3_ACTDRV

__IM uint32_t HB3_ACTDRV

[17..17] Half bridge 3 active driver detected at switch-on

◆ HB3_ACTDRV_IEN

__IOM uint32_t HB3_ACTDRV_IEN

[30..30] Half bridge 3 active driver detection interrupt enable

◆ HB3_ACTDRV_IS

__IM uint32_t HB3_ACTDRV_IS

[30..30] Half bridge 3 active driver detection interrupt status

◆ HB3_ACTDRV_ISC

__OM uint32_t HB3_ACTDRV_ISC

[30..30] Half bridge 3 active driver detection interrupt status clear

◆ HB3_ACTDRV_ISS

__OM uint32_t HB3_ACTDRV_ISS

[30..30] Half bridge 3 active driver detection interrupt status set

◆ HB3_ACTDRV_OFF

__IM uint32_t HB3_ACTDRV_OFF

[28..28] Half bridge 3 switch-off active driver

◆ HB3_ACTDRV_ON

__IM uint32_t HB3_ACTDRV_ON

[28..28] Half bridge 3 switch-on active driver

◆ HB3_ASEQ_IEN

__IOM uint32_t HB3_ASEQ_IEN

[26..26] Half bridge 3 adaptive sequencer interrupt enable

◆ HB3_ASEQ_IS

__IM uint32_t HB3_ASEQ_IS

[26..26] Half bridge 3 adaptive sequencer interrupt status

◆ HB3_ASEQ_ISC

__OM uint32_t HB3_ASEQ_ISC

[26..26] Half bridge 3 adaptive sequencer interrupt status clear

◆ HB3_ASEQ_ISS

__OM uint32_t HB3_ASEQ_ISS

[26..26] Half bridge 3 adaptive sequencer interrupt status set

◆ HB3_EN

__IOM uint32_t HB3_EN

[16..16] Half bridge 3 enable

◆ HB3_I1OFFVAL

__IM uint32_t HB3_I1OFFVAL

[13..8] Half bridge 3 switch-off phase 1 current setting from adaptive sequencer

◆ HB3_I1ONVAL

__IM uint32_t HB3_I1ONVAL

[13..8] Half bridge 3 switch-on phase 1 current setting from adaptive sequencer

◆ HB3_ICLMPOFF

__IOM uint32_t HB3_ICLMPOFF

[13..8] Half bridge 3 current clamping value for off state

◆ HB3_ICLMPON

__IOM uint32_t HB3_ICLMPON

[5..0] Half bridge 3 current clamping value for on state

◆ HB3_OFFVALVF

__IOM uint32_t HB3_OFFVALVF

[29..29] Half bridge 3 switch-off measurement values valid flag

◆ HB3_OFFVALVF_CLR

__OM uint32_t HB3_OFFVALVF_CLR

[30..30] Half bridge 3 switch-off measurement values valid flag clear

◆ HB3_OFFVALVF_SET

__OM uint32_t HB3_OFFVALVF_SET

[31..31] Half bridge 3 switch-off measurement values valid flag set

◆ HB3_ONVALVF

__IOM uint32_t HB3_ONVALVF

[29..29] Half bridge 3 switch-on measurement values valid flag

◆ HB3_ONVALVF_CLR

__OM uint32_t HB3_ONVALVF_CLR

[30..30] Half bridge 3 switch-on measurement values valid flag clear

◆ HB3_ONVALVF_SET

__OM uint32_t HB3_ONVALVF_SET

[31..31] Half bridge 3 switch-on measurement values valid flag set

◆ HB3_SEQMAP

__IOM uint32_t HB3_SEQMAP

[16..16] Half bridge 3 sequencer mapping

◆ HB3_TOFFDLY

__IM uint32_t HB3_TOFFDLY

[7..0] Half bridge 3 switch-off delay time value measured until VSH voltage starts to change

◆ HB3_TOFFDUR

__IM uint32_t HB3_TOFFDUR

[21..16] Half bridge 3 switch-off voltage slope duration time value

◆ HB3_TOFFDURMERR

__IM uint32_t HB3_TOFFDURMERR

[22..22] Half bridge 3 switch-off voltage slope time measurement error

◆ HB3_TONDLY

__IM uint32_t HB3_TONDLY

[7..0] Half bridge 3 switch-on delay time value measured until VSH voltage starts to change

◆ HB3_TONDUR

__IM uint32_t HB3_TONDUR

[21..16] Half bridge 3 switch-on voltage slope duration time value

◆ HB3_TONDURMERR

__IM uint32_t HB3_TONDURMERR

[22..22] Half bridge 3 switch-on voltage slope time measurement error

◆ HB3ASMOFFEN

__IOM uint32_t HB3ASMOFFEN

[17..17] Half bridge 3 adaptive sequencer for switch-off

◆ HB3ASMONEN

__IOM uint32_t HB3ASMONEN

[16..16] Half bridge 3 adaptive sequencer for switch-on

◆ HB3I1OFFMAX

__IM uint32_t HB3I1OFFMAX

[17..17] Half bridge 3 max I1OFF value reached

◆ HB3I1OFFMIN

__IM uint32_t HB3I1OFFMIN

[19..19] Half bridge 3 min I1OFF value reached

◆ HB3I1ONMAX

__IM uint32_t HB3I1ONMAX

[17..17] Half bridge 3 max I1ON value reached

◆ HB3I1ONMIN

__IM uint32_t HB3I1ONMIN

[19..19] Half bridge 3 min I1ON value reached

◆  [1/2]

union { ... } HB3IGATECLMPC

◆  [2/2]

union { ... } HB3IGATECLMPC

◆ HB3MFERRCNT

__IOM uint32_t HB3MFERRCNT

[21..20] Half bridge 3 measurement failure error counter setting

◆ HB3OFFFAILDRV

__IM uint32_t HB3OFFFAILDRV

[23..23] Half bridge 3 switch-off failed gate driver

◆ HB3OFFHYSTEN

__IOM uint32_t HB3OFFHYSTEN

[23..23] Half bridge 3 optimizer hysteresis for switch-off

◆ HB3OFFMF

__IM uint32_t HB3OFFMF

[20..20] Half bridge 3 adaptive sequencer switch-off measurement failure

◆ HB3OFFSEQCNF

__IOM uint32_t HB3OFFSEQCNF

[9..9] Half bridge 3 sequencer switch-off configuration

◆  [1/2]

union { ... } HB3OFFVAL

◆  [2/2]

union { ... } HB3OFFVAL

◆ HB3ONFAILDRV

__IM uint32_t HB3ONFAILDRV

[23..23] Half bridge 3 switch-on failed gate driver

◆ HB3ONHYSTEN

__IOM uint32_t HB3ONHYSTEN

[22..22] Half bridge 3 optimizer hysteresis for switch-on

◆ HB3ONMF

__IM uint32_t HB3ONMF

[20..20] Half bridge 3 adaptive sequencer switch-on measurement failure

◆ HB3ONSEQCNF

__IOM uint32_t HB3ONSEQCNF

[8..8] Half bridge 3 sequencer switch-on configuration

◆  [1/2]

union { ... } HB3ONVAL

◆  [2/2]

union { ... } HB3ONVAL

◆ HB3T12ONERRCNT

__IOM uint32_t HB3T12ONERRCNT

[19..18] Half bridge 3 T12ON error counter setting

◆ HB3T12ONMAX

__IM uint32_t HB3T12ONMAX

[16..16] Half bridge 3 max T12ON value reached

◆ HB3T12ONMIN

__IM uint32_t HB3T12ONMIN

[18..18] Half bridge 3 min T12ON value reached

◆ HB3T1OFFERRCNT

__IOM uint32_t HB3T1OFFERRCNT

[17..16] Half bridge 3 T1OFF error counter setting

◆ HB3T1OFFMAX

__IM uint32_t HB3T1OFFMAX

[16..16] Half bridge 3 max T1OFF value reached

◆ HB3T1OFFMIN

__IM uint32_t HB3T1OFFMIN

[18..18] Half bridge 3 min T1OFF value reached

◆  [1/2]

union { ... } HCDIS

◆  [2/2]

union { ... } HCDIS

◆ HCDIS_SSO

__IOM uint32_t HCDIS_SSO

[16..16] High-current discharge mode with safe switch-off

◆ HS1_DCS_EN

__IOM uint32_t HS1_DCS_EN

[24..24] High-side driver 1 diagnosis current source enable

◆ HS1_DS_IEN

__IOM uint32_t HS1_DS_IEN

[5..5] High-side driver 1 off-state drain source monitoring interrupt enable

◆ HS1_DS_IS

__IM uint32_t HS1_DS_IS

[5..5] High-side driver 1 off-state drain source monitoring interrupt status

◆ HS1_DS_ISC

__OM uint32_t HS1_DS_ISC

[5..5] High-side driver 1 off-state drain source monitoring interrupt status clear

◆ HS1_DS_ISS

__OM uint32_t HS1_DS_ISS

[5..5] High-side driver 1 off-state drain source monitoring interrupt status set

◆ HS1_DS_SC

__OM uint32_t HS1_DS_SC

[5..5] High-side driver 1 off-state drain source monitoring status clear

◆ HS1_DS_SS

__OM uint32_t HS1_DS_SS

[5..5] High-side driver 1 off-state drain source monitoring status set

◆ HS1_DS_STS

__IM uint32_t HS1_DS_STS

[5..5] High-side driver 1 off-state drain source monitoring status

◆ HS1_I1OFF

__IOM uint32_t HS1_I1OFF

[5..0] High-side driver 1 sequencer switch-off phase 1 and constant switch-off current setting

◆ HS1_I1ON

__IOM uint32_t HS1_I1ON

[5..0] High-side driver 1 sequencer switch-on phase 1 and constant switch-on current setting

◆ HS1_I2OFF

__IOM uint32_t HS1_I2OFF

[13..8] High-side driver 1 sequencer switch-off phase 2 current setting

◆ HS1_I2ON

__IOM uint32_t HS1_I2ON

[13..8] High-side driver 1 sequencer switch-on phase 2 current setting

◆ HS1_I3OFF

__IOM uint32_t HS1_I3OFF

[21..16] High-side driver 1 sequencer switch-off phase 3 current setting

◆ HS1_I3ON

__IOM uint32_t HS1_I3ON

[21..16] High-side driver 1 sequencer switch-on phase 3 current setting

◆ HS1_I4ON

__IOM uint32_t HS1_I4ON

[29..24] High-side driver 1 sequencer switch-on phase 4 current setting

◆ HS1_IAFOFF

__IOM uint32_t HS1_IAFOFF

[5..0] High-side driver 1 active free-wheeling switch-off current setting

◆ HS1_IAFON

__IOM uint32_t HS1_IAFON

[13..8] High-side driver 1 active free-wheeling switch-on current setting

◆ HS1_OC_IEN

__IOM uint32_t HS1_OC_IEN

[4..4] External high-side 1 MOSFET overcurrent interrupt enable

◆ HS1_OC_IS

__IM uint32_t HS1_OC_IS

[4..4] External high-side 1 MOSFET overcurrent interrupt status

◆ HS1_OC_ISC

__OM uint32_t HS1_OC_ISC

[4..4] External high-side 1 MOSFET overcurrent interrupt status clear

◆ HS1_OC_ISS

__OM uint32_t HS1_OC_ISS

[4..4] External high-side 1 MOSFET overcurrent interrupt status set

◆ HS1_OC_SC

__OM uint32_t HS1_OC_SC

[4..4] External high-side 1 MOSFET overcurrent status clear

◆ HS1_OC_SEL

__IOM uint32_t HS1_OC_SEL

[7..7] High-side driver 1 overcurrent shutdown select

◆ HS1_OC_SS

__OM uint32_t HS1_OC_SS

[4..4] External high-side 1 MOSFET overcurrent status set

◆ HS1_OC_STS

__IM uint32_t HS1_OC_STS

[4..4] External high-side 1 MOSFET overcurrent status

◆ HS1_ON

__IOM uint32_t HS1_ON

[6..6] High-side driver 1 on

◆ HS1_PWM

__IOM uint32_t HS1_PWM

[5..5] High-side driver 1 PWM enable

◆ HS1_SRC_SEL

__IOM uint32_t HS1_SRC_SEL

[6..4] High-side driver 1 PWM source selection

◆ HS1_T1OFF

__IOM uint32_t HS1_T1OFF

[7..0] High-side driver 1 sequencer switch-off phase 1 and constant switch-off time setting

◆ HS1_T1ON

__IOM uint32_t HS1_T1ON

[7..0] High-side driver 1 sequencer switch-on phase 1 and constant switch-on time setting

◆ HS1_T2OFF

__IOM uint32_t HS1_T2OFF

[13..8] High-side driver 1 sequencer switch-off phase 2 time setting

◆ HS1_T2ON

__IOM uint32_t HS1_T2ON

[13..8] High-side driver 1 sequencer switch-on phase 2 time setting

◆ HS1_T3OFF

__IOM uint32_t HS1_T3OFF

[21..16] High-side driver 1 sequencer switch-off phase 3 time setting

◆ HS1_T3ON

__IOM uint32_t HS1_T3ON

[21..16] High-side driver 1 sequencer switch-on phase 3 time setting

◆ HS1_T4ON

__IOM uint32_t HS1_T4ON

[29..24] High-side driver 1 sequencer switch-on phase 4 time setting

◆ HS1_TAFOFF

__IOM uint32_t HS1_TAFOFF

[7..0] High-side driver 1 active free-wheeling switch-off time setting

◆ HS1_TAFON

__IOM uint32_t HS1_TAFON

[15..8] High-side driver 1 active free-wheeling switch-on time setting

◆  [1/2]

union { ... } HS1AFIC

◆  [2/2]

union { ... } HS1AFIC

◆  [1/2]

union { ... } HS1AFTC

◆  [2/2]

union { ... } HS1AFTC

◆ HS1DRV_HCDISCHG_DIS

__IOM uint32_t HS1DRV_HCDISCHG_DIS

[4..4] High-side driver 1 high-current discharge disable

◆ HS1DRV_OCSDN_DIS

__IOM uint32_t HS1DRV_OCSDN_DIS

[5..5] High-side driver 1 overcurrent shutdown disable

◆  [1/2]

union { ... } HS1SEQOFFIC

◆  [2/2]

union { ... } HS1SEQOFFIC

◆  [1/2]

union { ... } HS1SEQOFFTC

◆  [2/2]

union { ... } HS1SEQOFFTC

◆  [1/2]

union { ... } HS1SEQONIC

◆  [2/2]

union { ... } HS1SEQONIC

◆  [1/2]

union { ... } HS1SEQONTC

◆  [2/2]

union { ... } HS1SEQONTC

◆ HS1T1OFFADDDLY

__IOM uint32_t HS1T1OFFADDDLY

[7..4] High-side driver 1 adaptive sequencer T1OFF additional delay setting

◆ HS2_DCS_EN

__IOM uint32_t HS2_DCS_EN

[25..25] High-side driver 2 diagnosis current source enable

◆ HS2_DS_IEN

__IOM uint32_t HS2_DS_IEN

[13..13] High-side driver 2 off-state drain source monitoring interrupt enable

◆ HS2_DS_IS

__IM uint32_t HS2_DS_IS

[13..13] High-side driver 2 off-state drain source monitoring interrupt status

◆ HS2_DS_ISC

__OM uint32_t HS2_DS_ISC

[13..13] High-side driver 2 off-state drain source monitoring interrupt status clear

◆ HS2_DS_ISS

__OM uint32_t HS2_DS_ISS

[13..13] High-side driver 2 off-state drain source monitoring interrupt status set

◆ HS2_DS_SC

__OM uint32_t HS2_DS_SC

[13..13] High-side driver 2 off-state drain source monitoring status clear

◆ HS2_DS_SS

__OM uint32_t HS2_DS_SS

[13..13] High-side driver 2 off-state drain source monitoring status set

◆ HS2_DS_STS

__IM uint32_t HS2_DS_STS

[13..13] High-side driver 2 off-state drain source monitoring status

◆ HS2_I1OFF

__IOM uint32_t HS2_I1OFF

[5..0] High-side driver 2 sequencer switch-off phase 1 and constant switch-off current setting

◆ HS2_I1ON

__IOM uint32_t HS2_I1ON

[5..0] High-side driver 2 sequencer switch-on phase 1 and constant switch-on current setting

◆ HS2_I2OFF

__IOM uint32_t HS2_I2OFF

[13..8] High-side driver 2 sequencer switch-off phase 2 current setting

◆ HS2_I2ON

__IOM uint32_t HS2_I2ON

[13..8] High-side driver 2 sequencer switch-on phase 2 current setting

◆ HS2_I3OFF

__IOM uint32_t HS2_I3OFF

[21..16] High-side driver 2 sequencer switch-off phase 3 current setting

◆ HS2_I3ON

__IOM uint32_t HS2_I3ON

[21..16] High-side driver 2 sequencer switch-on phase 3 current setting

◆ HS2_I4ON

__IOM uint32_t HS2_I4ON

[29..24] High-side driver 2 sequencer switch-on phase 4 current setting

◆ HS2_IAFOFF

__IOM uint32_t HS2_IAFOFF

[5..0] High-side driver 2 active free-wheeling switch-off current setting

◆ HS2_IAFON

__IOM uint32_t HS2_IAFON

[13..8] High-side driver 2 active free-wheeling switch-on current setting

◆ HS2_OC_IEN

__IOM uint32_t HS2_OC_IEN

[12..12] External high-side 2 MOSFET overcurrent interrupt enable

◆ HS2_OC_IS

__IM uint32_t HS2_OC_IS

[12..12] External high-side 2 MOSFET overcurrent interrupt status

◆ HS2_OC_ISC

__OM uint32_t HS2_OC_ISC

[12..12] External high-side 2 MOSFET overcurrent interrupt status clear

◆ HS2_OC_ISS

__OM uint32_t HS2_OC_ISS

[12..12] External high-side 2 MOSFET overcurrent interrupt status set

◆ HS2_OC_SC

__OM uint32_t HS2_OC_SC

[12..12] External high-side 2 MOSFET overcurrent status clear

◆ HS2_OC_SEL

__IOM uint32_t HS2_OC_SEL

[15..15] High-side driver 2 overcurrent shutdown select

◆ HS2_OC_SS

__OM uint32_t HS2_OC_SS

[12..12] External high-side 2 MOSFET overcurrent status set

◆ HS2_OC_STS

__IM uint32_t HS2_OC_STS

[12..12] External high-side 2 MOSFET overcurrent status

◆ HS2_ON

__IOM uint32_t HS2_ON

[14..14] High-side driver 2 on

◆ HS2_PWM

__IOM uint32_t HS2_PWM

[13..13] High-side driver 2 PWM enable

◆ HS2_SRC_SEL

__IOM uint32_t HS2_SRC_SEL

[14..12] High-side driver 2 PWM source selection

◆ HS2_T1OFF

__IOM uint32_t HS2_T1OFF

[7..0] High-side driver 2 sequencer switch-off phase 1 and constant switch-off time setting

◆ HS2_T1ON

__IOM uint32_t HS2_T1ON

[7..0] High-side driver 2 sequencer switch-on phase 1 and constant switch-on time setting

◆ HS2_T2OFF

__IOM uint32_t HS2_T2OFF

[13..8] High-side driver 2 sequencer switch-off phase 2 time setting

◆ HS2_T2ON

__IOM uint32_t HS2_T2ON

[13..8] High-side driver 2 sequencer switch-on phase 2 time setting

◆ HS2_T3OFF

__IOM uint32_t HS2_T3OFF

[21..16] High-side driver 2 sequencer switch-off phase 3 time setting

◆ HS2_T3ON

__IOM uint32_t HS2_T3ON

[21..16] High-side driver 2 sequencer switch-on phase 3 time setting

◆ HS2_T4ON

__IOM uint32_t HS2_T4ON

[29..24] High-side driver 2 sequencer switch-on phase 4 time setting

◆ HS2_TAFOFF

__IOM uint32_t HS2_TAFOFF

[7..0] High-side driver 2 active free-wheeling switch-off time setting

◆ HS2_TAFON

__IOM uint32_t HS2_TAFON

[15..8] High-side driver 2 active free-wheeling switch-on time setting

◆  [1/2]

union { ... } HS2AFIC

◆  [2/2]

union { ... } HS2AFIC

◆  [1/2]

union { ... } HS2AFTC

◆  [2/2]

union { ... } HS2AFTC

◆ HS2DRV_HCDISCHG_DIS

__IOM uint32_t HS2DRV_HCDISCHG_DIS

[12..12] High-side driver 2 high-current discharge disable

◆ HS2DRV_OCSDN_DIS

__IOM uint32_t HS2DRV_OCSDN_DIS

[13..13] High-side driver 2 overcurrent shutdown disable

◆  [1/2]

union { ... } HS2SEQOFFIC

◆  [2/2]

union { ... } HS2SEQOFFIC

◆  [1/2]

union { ... } HS2SEQOFFTC

◆  [2/2]

union { ... } HS2SEQOFFTC

◆  [1/2]

union { ... } HS2SEQONIC

◆  [2/2]

union { ... } HS2SEQONIC

◆  [1/2]

union { ... } HS2SEQONTC

◆  [2/2]

union { ... } HS2SEQONTC

◆ HS2T1OFFADDDLY

__IOM uint32_t HS2T1OFFADDDLY

[15..12] High-side driver 2 adaptive sequencer T1OFF additional delay setting

◆ HS3_DCS_EN

__IOM uint32_t HS3_DCS_EN

[26..26] High-side driver 3 diagnosis current source enable

◆ HS3_DS_IEN

__IOM uint32_t HS3_DS_IEN

[21..21] High-side driver 3 off-state drain source monitoring interrupt enable

◆ HS3_DS_IS

__IM uint32_t HS3_DS_IS

[21..21] High-side driver 3 off-state drain source monitoring interrupt status

◆ HS3_DS_ISC

__OM uint32_t HS3_DS_ISC

[21..21] High-side driver 3 off-state drain source monitoring interrupt status clear

◆ HS3_DS_ISS

__OM uint32_t HS3_DS_ISS

[21..21] High-side driver 3 off-state drain source monitoring interrupt status set

◆ HS3_DS_SC

__OM uint32_t HS3_DS_SC

[21..21] High-side driver 3 off-state drain source monitoring status clear

◆ HS3_DS_SS

__OM uint32_t HS3_DS_SS

[21..21] High-side driver 3 off-state drain source monitoring status set

◆ HS3_DS_STS

__IM uint32_t HS3_DS_STS

[21..21] High-side driver 3 off-state drain source monitoring status

◆ HS3_I1OFF

__IOM uint32_t HS3_I1OFF

[5..0] High-side driver 3 sequencer switch-off phase 1 and constant switch-off current setting

◆ HS3_I1ON

__IOM uint32_t HS3_I1ON

[5..0] High-side driver 3 sequencer switch-on phase 1 and constant switch-on current setting

◆ HS3_I2OFF

__IOM uint32_t HS3_I2OFF

[13..8] High-side driver 3 sequencer switch-off phase 2 current setting

◆ HS3_I2ON

__IOM uint32_t HS3_I2ON

[13..8] High-side driver 3 sequencer switch-on phase 2 current setting

◆ HS3_I3OFF

__IOM uint32_t HS3_I3OFF

[21..16] High-side driver 3 sequencer switch-off phase 3 current setting

◆ HS3_I3ON

__IOM uint32_t HS3_I3ON

[21..16] High-side driver 3 sequencer switch-on phase 3 current setting

◆ HS3_I4ON

__IOM uint32_t HS3_I4ON

[29..24] High-side driver 3 sequencer switch-on phase 4 current setting

◆ HS3_IAFOFF

__IOM uint32_t HS3_IAFOFF

[5..0] High-side driver 3 active free-wheeling switch-off current setting

◆ HS3_IAFON

__IOM uint32_t HS3_IAFON

[13..8] High-side driver 3 active free-wheeling switch-on current setting

◆ HS3_OC_IEN

__IOM uint32_t HS3_OC_IEN

[20..20] External high-side 3 MOSFET overcurrent interrupt enable

◆ HS3_OC_IS

__IM uint32_t HS3_OC_IS

[20..20] External high-side 3 MOSFET overcurrent interrupt status

◆ HS3_OC_ISC

__OM uint32_t HS3_OC_ISC

[20..20] External high-side 3 MOSFET overcurrent interrupt status clear

◆ HS3_OC_ISS

__OM uint32_t HS3_OC_ISS

[20..20] External high-side 3 MOSFET overcurrent interrupt status set

◆ HS3_OC_SC

__OM uint32_t HS3_OC_SC

[20..20] External high-side 3 MOSFET overcurrent status clear

◆ HS3_OC_SEL

__IOM uint32_t HS3_OC_SEL

[23..23] High-side driver 3 overcurrent shutdown select

◆ HS3_OC_SS

__OM uint32_t HS3_OC_SS

[20..20] External high-side 3 MOSFET overcurrent status set

◆ HS3_OC_STS

__IM uint32_t HS3_OC_STS

[20..20] External high-side 3 MOSFET overcurrent status

◆ HS3_ON

__IOM uint32_t HS3_ON

[22..22] High-side driver 3 on

◆ HS3_PWM

__IOM uint32_t HS3_PWM

[21..21] High-side driver 3 PWM enable

◆ HS3_SRC_SEL

__IOM uint32_t HS3_SRC_SEL

[22..20] High-side driver 3 PWM source selection

◆ HS3_T1OFF

__IOM uint32_t HS3_T1OFF

[7..0] High-side driver 3 sequencer switch-off phase 1 and constant switch-off time setting

◆ HS3_T1ON

__IOM uint32_t HS3_T1ON

[7..0] High-side driver 3 sequencer switch-on phase 1 and constant switch-on time setting

◆ HS3_T2OFF

__IOM uint32_t HS3_T2OFF

[13..8] High-side driver 3 sequencer switch-off phase 2 time setting

◆ HS3_T2ON

__IOM uint32_t HS3_T2ON

[13..8] High-side driver 3 sequencer switch-on phase 2 time setting

◆ HS3_T3OFF

__IOM uint32_t HS3_T3OFF

[21..16] High-side driver 3 sequencer switch-off phase 3 time setting

◆ HS3_T3ON

__IOM uint32_t HS3_T3ON

[21..16] High-side driver 3 sequencer switch-on phase 3 time setting

◆ HS3_T4ON

__IOM uint32_t HS3_T4ON

[29..24] High-side driver 3 sequencer switch-on phase 4 time setting

◆ HS3_TAFOFF

__IOM uint32_t HS3_TAFOFF

[7..0] High-side driver 3 active free-wheeling switch-off time setting

◆ HS3_TAFON

__IOM uint32_t HS3_TAFON

[15..8] High-side driver 3 active free-wheeling switch-on time setting

◆  [1/2]

union { ... } HS3AFIC

◆  [2/2]

union { ... } HS3AFIC

◆  [1/2]

union { ... } HS3AFTC

◆  [2/2]

union { ... } HS3AFTC

◆ HS3DRV_HCDISCHG_DIS

__IOM uint32_t HS3DRV_HCDISCHG_DIS

[20..20] High-side driver 3 high-current discharge disable

◆ HS3DRV_OCSDN_DIS

__IOM uint32_t HS3DRV_OCSDN_DIS

[21..21] High-side driver 3 overcurrent shutdown disable

◆  [1/2]

union { ... } HS3SEQOFFIC

◆  [2/2]

union { ... } HS3SEQOFFIC

◆  [1/2]

union { ... } HS3SEQOFFTC

◆  [2/2]

union { ... } HS3SEQOFFTC

◆  [1/2]

union { ... } HS3SEQONIC

◆  [2/2]

union { ... } HS3SEQONIC

◆  [1/2]

union { ... } HS3SEQONTC

◆  [2/2]

union { ... } HS3SEQONTC

◆ HS3T1OFFADDDLY

__IOM uint32_t HS3T1OFFADDDLY

[23..20] High-side driver 3 adaptive sequencer T1OFF additional delay setting

◆ HSDRV_DS_TFILT_SEL

__IOM uint32_t HSDRV_DS_TFILT_SEL

[23..22] Filter time for drain-source monitoring of high-side drivers

◆ I1OFFMAX

__IOM uint32_t I1OFFMAX

[5..0] Switch-off phase 1 maximum current setting

◆ I1OFFMIN

__IOM uint32_t I1OFFMIN

[5..0] Switch-off phase 1 minimum current setting

◆ I1ONMAX

__IOM uint32_t I1ONMAX

[5..0] Switch-on phase 1 maximum current setting

◆ I1ONMIN

__IOM uint32_t I1ONMIN

[5..0] Switch-on phase 1 minimum current setting

◆ I4OFF

__IOM uint32_t I4OFF

[21..16] Sequencer switch-off phase 4 current setting for all drivers

◆ ICHG_IDCHG

__IOM uint32_t ICHG_IDCHG

[13..8] Charge/discharge current setting common for all drivers

◆ ICHGMAX_TCTRIM

__IOM uint32_t ICHGMAX_TCTRIM

[7..5] Tk trimming of the maximum charge current

◆ ICHGMIN_TCTRIM

__IOM uint32_t ICHGMIN_TCTRIM

[23..21] Tk trimming of the minimum charge current

◆ IDAC_DTB

__IOM uint32_t IDAC_DTB

[13..13] Charge/discharge current DTB input assignment

◆ IDAC_SH_EN

__IOM uint32_t IDAC_SH_EN

[0..0] iDAC sample-and-hold enable

◆ IDAC_SH_TP

__IOM uint32_t IDAC_SH_TP

[2..2] iDAC sample-and-hold period time

◆ IDAC_SH_TS

__IOM uint32_t IDAC_SH_TS

[1..1] iDAC sample-and-hold sample time

◆ IDISCHGMAX_TCTRIM

__IOM uint32_t IDISCHGMAX_TCTRIM

[15..13] Tk trimming of the maximum discharge current

◆ IDISCHGMIN_TCTRIM

__IOM uint32_t IDISCHGMIN_TCTRIM

[31..29] Tk trimming of the minimum discharge current

◆ IGATE_TRIM_DTB

__IOM uint32_t IGATE_TRIM_DTB

[14..14] Driver current trimming DTB input assignment

◆ IHCDIS

__IOM uint32_t IHCDIS

[5..0] High-current discharge mode current setting for all drivers

◆ IN_SEL

__IOM uint32_t IN_SEL

[18..18] Deactivate INA/B/C as sample pulse sources

◆ IRCHG_MAX_TRIM

__IOM uint32_t IRCHG_MAX_TRIM

[4..0] Maximum charge current trimming

◆ IRCHG_MIN_TRIM

__IOM uint32_t IRCHG_MIN_TRIM

[20..16] Minimum charge current trimming

◆ IRDISCHG_MAX_TRIM

__IOM uint32_t IRDISCHG_MAX_TRIM

[12..8] Maximum discharge current trimming

◆ IRDISCHG_MIN_TRIM

__IOM uint32_t IRDISCHG_MIN_TRIM

[28..24] Minimum discharge current trimming

◆  [1/2]

union { ... } IRQCLR

◆  [2/2]

union { ... } IRQCLR

◆  [1/2]

union { ... } IRQEN

◆  [2/2]

union { ... } IRQEN

◆  [1/2]

union { ... } IRQS

◆  [2/2]

union { ... } IRQS

◆  [1/2]

union { ... } IRQSET

◆  [2/2]

union { ... } IRQSET

◆ LS1_DS_IEN

__IOM uint32_t LS1_DS_IEN

[1..1] Low-side driver 1 off-state drain source monitoring interrupt enable

◆ LS1_DS_IS

__IM uint32_t LS1_DS_IS

[1..1] Low-side driver 1 off-state drain source monitoring interrupt status

◆ LS1_DS_ISC

__OM uint32_t LS1_DS_ISC

[1..1] Low-side driver 1 off-state drain source monitoring interrupt status clear

◆ LS1_DS_ISS

__OM uint32_t LS1_DS_ISS

[1..1] Low-side driver 1 off-state drain source monitoring interrupt status set

◆ LS1_DS_SC

__OM uint32_t LS1_DS_SC

[1..1] Low-side driver 1 off-state drain source monitoring status clear

◆ LS1_DS_SS

__OM uint32_t LS1_DS_SS

[1..1] Low-side driver 1 off-state drain source monitoring status set

◆ LS1_DS_STS

__IM uint32_t LS1_DS_STS

[1..1] Low-side driver 1 off-state drain source monitoring status

◆ LS1_I1OFF

__IOM uint32_t LS1_I1OFF

[5..0] Low-side driver 1 sequencer switch-off phase 1 and constant switch-off current setting

◆ LS1_I1ON

__IOM uint32_t LS1_I1ON

[5..0] Low-side driver 1 sequencer switch-on phase 1 and constant switch-on current setting

◆ LS1_I2OFF

__IOM uint32_t LS1_I2OFF

[13..8] Low-side driver 1 sequencer switch-off phase 2 current setting

◆ LS1_I2ON

__IOM uint32_t LS1_I2ON

[13..8] Low-side driver 1 sequencer switch-on phase 2 current setting

◆ LS1_I3OFF

__IOM uint32_t LS1_I3OFF

[21..16] Low-side driver 1 sequencer switch-off phase 3 current setting

◆ LS1_I3ON

__IOM uint32_t LS1_I3ON

[21..16] Low-side driver 1 sequencer switch-on phase 3 current setting

◆ LS1_I4ON

__IOM uint32_t LS1_I4ON

[29..24] Low-side driver 1 sequencer switch-on phase 4 current setting

◆ LS1_IAFOFF

__IOM uint32_t LS1_IAFOFF

[5..0] Low-side driver 1 active free-wheeling switch-off current setting

◆ LS1_IAFON

__IOM uint32_t LS1_IAFON

[13..8] Low-side driver 1 active free-wheeling switch-on current setting

◆ LS1_OC_IEN

__IOM uint32_t LS1_OC_IEN

[0..0] External low-side 1 MOSFET overcurrent interrupt enable

◆ LS1_OC_IS

__IM uint32_t LS1_OC_IS

[0..0] External low-side 1 MOSFET overcurrent interrupt status

◆ LS1_OC_ISC

__OM uint32_t LS1_OC_ISC

[0..0] External low-side 1 MOSFET overcurrent interrupt status clear

◆ LS1_OC_ISS

__OM uint32_t LS1_OC_ISS

[0..0] External low-side 1 MOSFET overcurrent interrupt status set

◆ LS1_OC_SC

__OM uint32_t LS1_OC_SC

[0..0] External low-side 1 MOSFET overcurrent status clear

◆ LS1_OC_SEL

__IOM uint32_t LS1_OC_SEL

[3..3] Low-side driver 1 overcurrent shutdown select

◆ LS1_OC_SS

__OM uint32_t LS1_OC_SS

[0..0] External low-side 1 MOSFET overcurrent status set

◆ LS1_OC_STS

__IM uint32_t LS1_OC_STS

[0..0] External low-side 1 MOSFET overcurrent status

◆ LS1_ON

__IOM uint32_t LS1_ON

[2..2] Low-side driver 1 on

◆ LS1_PWM

__IOM uint32_t LS1_PWM

[1..1] Low-side driver 1 PWM enable

◆ LS1_SRC_SEL

__IOM uint32_t LS1_SRC_SEL

[2..0] Low-side driver 1 PWM source selection

◆ LS1_T1OFF

__IOM uint32_t LS1_T1OFF

[7..0] Low-side driver 1 sequencer switch-off phase 1 and constant switch-off time setting

◆ LS1_T1ON

__IOM uint32_t LS1_T1ON

[7..0] Low-side driver 1 sequencer switch-on phase 1 and constant switch-on time setting

◆ LS1_T2OFF

__IOM uint32_t LS1_T2OFF

[13..8] Low-side driver 1 sequencer switch-off phase 2 time setting

◆ LS1_T2ON

__IOM uint32_t LS1_T2ON

[13..8] Low-side driver 1 sequencer switch-on phase 2 time setting

◆ LS1_T3OFF

__IOM uint32_t LS1_T3OFF

[21..16] Low-side driver 1 sequencer switch-off phase 3 time setting

◆ LS1_T3ON

__IOM uint32_t LS1_T3ON

[21..16] Low-side driver 1 sequencer switch-on phase 3 time setting

◆ LS1_T4ON

__IOM uint32_t LS1_T4ON

[29..24] Low-side driver 1 sequencer switch-on phase 4 time setting

◆ LS1_TAFOFF

__IOM uint32_t LS1_TAFOFF

[7..0] Low-side driver 1 active free-wheeling switch-off time setting

◆ LS1_TAFON

__IOM uint32_t LS1_TAFON

[15..8] Low-side driver 1 active free-wheeling switch-on time setting

◆  [1/2]

union { ... } LS1AFIC

◆  [2/2]

union { ... } LS1AFIC

◆  [1/2]

union { ... } LS1AFTC

◆  [2/2]

union { ... } LS1AFTC

◆ LS1DRV_HCDISCHG_DIS

__IOM uint32_t LS1DRV_HCDISCHG_DIS

[0..0] Low-side driver 1 high-current discharge disable

◆ LS1DRV_OCSDN_DIS

__IOM uint32_t LS1DRV_OCSDN_DIS

[1..1] Low-side driver 1 overcurrent shutdown disable

◆  [1/2]

union { ... } LS1SEQOFFIC

◆  [2/2]

union { ... } LS1SEQOFFIC

◆  [1/2]

union { ... } LS1SEQOFFTC

◆  [2/2]

union { ... } LS1SEQOFFTC

◆  [1/2]

union { ... } LS1SEQONIC

◆  [2/2]

union { ... } LS1SEQONIC

◆  [1/2]

union { ... } LS1SEQONTC

◆  [2/2]

union { ... } LS1SEQONTC

◆ LS1T1OFFADDDLY

__IOM uint32_t LS1T1OFFADDDLY

[3..0] Low-side driver 1 adaptive sequencer T1OFF additional delay setting

◆ LS2_DS_IEN

__IOM uint32_t LS2_DS_IEN

[9..9] Low-side driver 2 off-state drain source monitoring interrupt enable

◆ LS2_DS_IS

__IM uint32_t LS2_DS_IS

[9..9] Low-side driver 2 off-state drain source monitoring interrupt status

◆ LS2_DS_ISC

__OM uint32_t LS2_DS_ISC

[9..9] Low-side driver 2 off-state drain source monitoring interrupt status clear

◆ LS2_DS_ISS

__OM uint32_t LS2_DS_ISS

[9..9] Low-side driver 2 off-state drain source monitoring interrupt status set

◆ LS2_DS_SC

__OM uint32_t LS2_DS_SC

[9..9] Low-side driver 2 off-state drain source monitoring status clear

◆ LS2_DS_SS

__OM uint32_t LS2_DS_SS

[9..9] Low-side driver 2 off-state drain source monitoring status set

◆ LS2_DS_STS

__IM uint32_t LS2_DS_STS

[9..9] Low-side driver 2 off-state drain source monitoring status

◆ LS2_I1OFF

__IOM uint32_t LS2_I1OFF

[5..0] Low-side driver 2 sequencer switch-off phase 1 and constant switch-off current setting

◆ LS2_I1ON

__IOM uint32_t LS2_I1ON

[5..0] Low-side driver 2 sequencer switch-on phase 1 and constant switch-on current setting

◆ LS2_I2OFF

__IOM uint32_t LS2_I2OFF

[13..8] Low-side driver 2 sequencer switch-off phase 2 current setting

◆ LS2_I2ON

__IOM uint32_t LS2_I2ON

[13..8] Low-side driver 2 sequencer switch-on phase 2 current setting

◆ LS2_I3OFF

__IOM uint32_t LS2_I3OFF

[21..16] Low-side driver 2 sequencer switch-off phase 3 current setting

◆ LS2_I3ON

__IOM uint32_t LS2_I3ON

[21..16] Low-side driver 2 sequencer switch-on phase 3 current setting

◆ LS2_I4ON

__IOM uint32_t LS2_I4ON

[29..24] Low-side driver 2 sequencer switch-on phase 4 current setting

◆ LS2_IAFOFF

__IOM uint32_t LS2_IAFOFF

[5..0] Low-side driver 2 active free-wheeling switch-off current setting

◆ LS2_IAFON

__IOM uint32_t LS2_IAFON

[13..8] Low-side driver 2 active free-wheeling switch-on current setting

◆ LS2_OC_IEN

__IOM uint32_t LS2_OC_IEN

[8..8] External low-side 2 MOSFET overcurrent interrupt enable

◆ LS2_OC_IS

__IM uint32_t LS2_OC_IS

[8..8] External low-side 2 MOSFET overcurrent interrupt status

◆ LS2_OC_ISC

__OM uint32_t LS2_OC_ISC

[8..8] External low-side 2 MOSFET overcurrent interrupt status clear

◆ LS2_OC_ISS

__OM uint32_t LS2_OC_ISS

[8..8] External low-side 2 MOSFET overcurrent interrupt status set

◆ LS2_OC_SC

__OM uint32_t LS2_OC_SC

[8..8] External low-side 2 MOSFET overcurrent status clear

◆ LS2_OC_SEL

__IOM uint32_t LS2_OC_SEL

[11..11] Low-side driver 2 overcurrent shutdown select

◆ LS2_OC_SS

__OM uint32_t LS2_OC_SS

[8..8] External low-side 2 MOSFET overcurrent status set

◆ LS2_OC_STS

__IM uint32_t LS2_OC_STS

[8..8] External low-side 2 MOSFET overcurrent status

◆ LS2_ON

__IOM uint32_t LS2_ON

[10..10] Low-side driver 2 on

◆ LS2_PWM

__IOM uint32_t LS2_PWM

[9..9] Low-side driver 2 PWM enable

◆ LS2_SRC_SEL

__IOM uint32_t LS2_SRC_SEL

[10..8] Low-side driver 2 PWM source selection

◆ LS2_T1OFF

__IOM uint32_t LS2_T1OFF

[7..0] Low-side driver 2 sequencer switch-off phase 1 and constant switch-off time setting

◆ LS2_T1ON

__IOM uint32_t LS2_T1ON

[7..0] Low-side driver 2 sequencer switch-on phase 1 and constant switch-on time setting

◆ LS2_T2OFF

__IOM uint32_t LS2_T2OFF

[13..8] Low-side driver 2 sequencer switch-off phase 2 time setting

◆ LS2_T2ON

__IOM uint32_t LS2_T2ON

[13..8] Low-side driver 2 sequencer switch-on phase 2 time setting

◆ LS2_T3OFF

__IOM uint32_t LS2_T3OFF

[21..16] Low-side driver 2 sequencer switch-off phase 3 time setting

◆ LS2_T3ON

__IOM uint32_t LS2_T3ON

[21..16] Low-side driver 2 sequencer switch-on phase 3 time setting

◆ LS2_T4ON

__IOM uint32_t LS2_T4ON

[29..24] Low-side driver 2 sequencer switch-on phase 4 time setting

◆ LS2_TAFOFF

__IOM uint32_t LS2_TAFOFF

[7..0] Low-side driver 2 active free-wheeling switch-off time setting

◆ LS2_TAFON

__IOM uint32_t LS2_TAFON

[15..8] Low-side driver 2 active free-wheeling switch-on time setting

◆  [1/2]

union { ... } LS2AFIC

◆  [2/2]

union { ... } LS2AFIC

◆  [1/2]

union { ... } LS2AFTC

◆  [2/2]

union { ... } LS2AFTC

◆ LS2DRV_HCDISCHG_DIS

__IOM uint32_t LS2DRV_HCDISCHG_DIS

[8..8] Low-side driver 2 high-current discharge disable

◆ LS2DRV_OCSDN_DIS

__IOM uint32_t LS2DRV_OCSDN_DIS

[9..9] Low-side driver 2 overcurrent shutdown disable

◆  [1/2]

union { ... } LS2SEQOFFIC

◆  [2/2]

union { ... } LS2SEQOFFIC

◆  [1/2]

union { ... } LS2SEQOFFTC

◆  [2/2]

union { ... } LS2SEQOFFTC

◆  [1/2]

union { ... } LS2SEQONIC

◆  [2/2]

union { ... } LS2SEQONIC

◆  [1/2]

union { ... } LS2SEQONTC

◆  [2/2]

union { ... } LS2SEQONTC

◆ LS2T1OFFADDDLY

__IOM uint32_t LS2T1OFFADDDLY

[11..8] Low-side driver 2 adaptive sequencer T1OFF additional delay setting

◆ LS3_DS_IEN

__IOM uint32_t LS3_DS_IEN

[17..17] Low-side driver 3 off-state drain source monitoring interrupt enable

◆ LS3_DS_IS

__IM uint32_t LS3_DS_IS

[17..17] Low-side driver 3 off-state drain source monitoring interrupt status

◆ LS3_DS_ISC

__OM uint32_t LS3_DS_ISC

[17..17] Low-side driver 3 off-state drain source monitoring interrupt status clear

◆ LS3_DS_ISS

__OM uint32_t LS3_DS_ISS

[17..17] Low-side driver 3 off-state drain source monitoring interrupt status set

◆ LS3_DS_SC

__OM uint32_t LS3_DS_SC

[17..17] Low-side driver 3 off-state drain source monitoring status clear

◆ LS3_DS_SS

__OM uint32_t LS3_DS_SS

[17..17] Low-side driver 3 off-state drain source monitoring status set

◆ LS3_DS_STS

__IM uint32_t LS3_DS_STS

[17..17] Low-side driver 3 off-state drain source monitoring status

◆ LS3_I1OFF

__IOM uint32_t LS3_I1OFF

[5..0] Low-side driver 3 sequencer switch-off phase 1 and constant switch-off current setting

◆ LS3_I1ON

__IOM uint32_t LS3_I1ON

[5..0] Low-side driver 3 sequencer switch-on phase 1 and constant switch-on current setting

◆ LS3_I2OFF

__IOM uint32_t LS3_I2OFF

[13..8] Low-side driver 3 sequencer switch-off phase 2 current setting

◆ LS3_I2ON

__IOM uint32_t LS3_I2ON

[13..8] Low-side driver 3 sequencer switch-on phase 2 current setting

◆ LS3_I3OFF

__IOM uint32_t LS3_I3OFF

[21..16] Low-side driver 3 sequencer switch-off phase 3 current setting

◆ LS3_I3ON

__IOM uint32_t LS3_I3ON

[21..16] Low-side driver 3 sequencer switch-on phase 3 current setting

◆ LS3_I4ON

__IOM uint32_t LS3_I4ON

[29..24] Low-side driver 3 sequencer switch-on phase 4 current setting

◆ LS3_IAFOFF

__IOM uint32_t LS3_IAFOFF

[5..0] Low-side driver 3 active free-wheeling switch-off current setting

◆ LS3_IAFON

__IOM uint32_t LS3_IAFON

[13..8] Low-side driver 3 active free-wheeling switch-on current setting

◆ LS3_OC_IEN

__IOM uint32_t LS3_OC_IEN

[16..16] External low-side 3 MOSFET overcurrent interrupt enable

◆ LS3_OC_IS

__IM uint32_t LS3_OC_IS

[16..16] External low-side 3 MOSFET overcurrent interrupt status

◆ LS3_OC_ISC

__OM uint32_t LS3_OC_ISC

[16..16] External low-side 3 MOSFET overcurrent interrupt status clear

◆ LS3_OC_ISS

__OM uint32_t LS3_OC_ISS

[16..16] External low-side 3 MOSFET overcurrent interrupt status set

◆ LS3_OC_SC

__OM uint32_t LS3_OC_SC

[16..16] External low-side 3 MOSFET overcurrent status clear

◆ LS3_OC_SEL

__IOM uint32_t LS3_OC_SEL

[19..19] Low-side driver 3 overcurrent shutdown select

◆ LS3_OC_SS

__OM uint32_t LS3_OC_SS

[16..16] External low-side 3 MOSFET overcurrent status set

◆ LS3_OC_STS

__IM uint32_t LS3_OC_STS

[16..16] External low-side 3 MOSFET overcurrent status

◆ LS3_ON

__IOM uint32_t LS3_ON

[18..18] Low-side driver 3 on

◆ LS3_PWM

__IOM uint32_t LS3_PWM

[17..17] Low-side driver 3 PWM enable

◆ LS3_SRC_SEL

__IOM uint32_t LS3_SRC_SEL

[18..16] Low-side driver 3 PWM source selection

◆ LS3_T1OFF

__IOM uint32_t LS3_T1OFF

[7..0] Low-side driver 3 sequencer switch-off phase 1 and constant switch-off time setting

◆ LS3_T1ON

__IOM uint32_t LS3_T1ON

[7..0] Low-side driver 3 sequencer switch-on phase 1 and constant switch-on time setting

◆ LS3_T2OFF

__IOM uint32_t LS3_T2OFF

[13..8] Low-side driver 3 sequencer switch-off phase 2 time setting

◆ LS3_T2ON

__IOM uint32_t LS3_T2ON

[13..8] Low-side driver 3 sequencer switch-on phase 2 time setting

◆ LS3_T3OFF

__IOM uint32_t LS3_T3OFF

[21..16] Low-side driver 3 sequencer switch-off phase 3 time setting

◆ LS3_T3ON

__IOM uint32_t LS3_T3ON

[21..16] Low-side driver 3 sequencer switch-on phase 3 time setting

◆ LS3_T4ON

__IOM uint32_t LS3_T4ON

[29..24] Low-side driver 3 sequencer switch-on phase 4 time setting

◆ LS3_TAFOFF

__IOM uint32_t LS3_TAFOFF

[7..0] Low-side driver 3 active free-wheeling switch-off time setting

◆ LS3_TAFON

__IOM uint32_t LS3_TAFON

[15..8] Low-side driver 3 active free-wheeling switch-on time setting

◆  [1/2]

union { ... } LS3AFIC

◆  [2/2]

union { ... } LS3AFIC

◆  [1/2]

union { ... } LS3AFTC

◆  [2/2]

union { ... } LS3AFTC

◆ LS3DRV_HCDISCHG_DIS

__IOM uint32_t LS3DRV_HCDISCHG_DIS

[16..16] Low-side driver 3 high-current discharge disable

◆ LS3DRV_OCSDN_DIS

__IOM uint32_t LS3DRV_OCSDN_DIS

[17..17] Low-side driver 3 overcurrent shutdown disable

◆  [1/2]

union { ... } LS3SEQOFFIC

◆  [2/2]

union { ... } LS3SEQOFFIC

◆  [1/2]

union { ... } LS3SEQOFFTC

◆  [2/2]

union { ... } LS3SEQOFFTC

◆  [1/2]

union { ... } LS3SEQONIC

◆  [2/2]

union { ... } LS3SEQONIC

◆  [1/2]

union { ... } LS3SEQONTC

◆  [2/2]

union { ... } LS3SEQONTC

◆ LS3T1OFFADDDLY

__IOM uint32_t LS3T1OFFADDDLY

[19..16] Low-side driver 3 adaptive sequencer T1OFF additional delay setting

◆ LS_HS_BT_TFILT_SEL

__IOM uint32_t LS_HS_BT_TFILT_SEL

[25..24] Blanking time for drain-source monitoring of low-side/high-side drivers

◆ LSDRV_DS_TFILT_SEL

__IOM uint32_t LSDRV_DS_TFILT_SEL

[21..20] Filter time for drain-source monitoring of low-side drivers

◆ MI_EN

__IOM uint32_t MI_EN

[30..30] Module isolation mode

◆ ON_DTB

__IOM uint32_t ON_DTB

[12..12] Driver control DTB input assignment

◆ PASSIVE_OFF

__IOM uint32_t PASSIVE_OFF

[0..0] Passive OFF for all drivers

◆ PH1_COMP_DIS_SET

__IOM uint32_t PH1_COMP_DIS_SET

[4..4] Phase 1 comparator output status value if disabled

◆ PH1_COMP_EN

__IOM uint32_t PH1_COMP_EN

[0..0] Phase 1 comparator enable

◆ PH1_ZC_STS

__IM uint32_t PH1_ZC_STS

[25..25] Phase 1 zero crossing comparator status

◆ PH1_ZCFALL_IEN

__IOM uint32_t PH1_ZCFALL_IEN

[0..0] Phase 1 zero crossing falling interrupt enable

◆ PH1_ZCFALL_IS

__IM uint32_t PH1_ZCFALL_IS

[0..0] Phase 1 zero crossing falling interrupt status

◆ PH1_ZCFALL_ISC

__OM uint32_t PH1_ZCFALL_ISC

[0..0] Phase 1 zero crossing falling interrupt status clear

◆ PH1_ZCFALL_ISS

__OM uint32_t PH1_ZCFALL_ISS

[0..0] Phase 1 zero crossing falling interrupt status set

◆ PH1_ZCRISE_IEN

__IOM uint32_t PH1_ZCRISE_IEN

[1..1] Phase 1 zero crossing rising interrupt enable

◆ PH1_ZCRISE_IS

__IM uint32_t PH1_ZCRISE_IS

[1..1] Phase 1 zero crossing rising interrupt status

◆ PH1_ZCRISE_ISC

__OM uint32_t PH1_ZCRISE_ISC

[1..1] Phase 1 zero crossing rising interrupt status clear

◆ PH1_ZCRISE_ISS

__OM uint32_t PH1_ZCRISE_ISS

[1..1] Phase 1 zero crossing rising interrupt status set

◆ PH2_COMP_DIS_SET

__IOM uint32_t PH2_COMP_DIS_SET

[5..5] Phase 2 comparator output status value if disabled

◆ PH2_COMP_EN

__IOM uint32_t PH2_COMP_EN

[1..1] Phase 2 comparator enable

◆ PH2_ZC_STS

__IM uint32_t PH2_ZC_STS

[26..26] Phase 2 zero crossing comparator status

◆ PH2_ZCFALL_IEN

__IOM uint32_t PH2_ZCFALL_IEN

[2..2] Phase 2 zero crossing falling interrupt enable

◆ PH2_ZCFALL_IS

__IM uint32_t PH2_ZCFALL_IS

[2..2] Phase 2 zero crossing falling interrupt status

◆ PH2_ZCFALL_ISC

__OM uint32_t PH2_ZCFALL_ISC

[2..2] Phase 2 zero crossing falling interrupt status clear

◆ PH2_ZCFALL_ISS

__OM uint32_t PH2_ZCFALL_ISS

[2..2] Phase 2 zero crossing falling interrupt status set

◆ PH2_ZCRISE_IEN

__IOM uint32_t PH2_ZCRISE_IEN

[3..3] Phase 2 zero crossing rising interrupt enable

◆ PH2_ZCRISE_IS

__IM uint32_t PH2_ZCRISE_IS

[3..3] Phase 2 zero crossing rising interrupt status

◆ PH2_ZCRISE_ISC

__OM uint32_t PH2_ZCRISE_ISC

[3..3] Phase 2 zero crossing rising interrupt status clear

◆ PH2_ZCRISE_ISS

__OM uint32_t PH2_ZCRISE_ISS

[3..3] Phase 2 zero crossing rising interrupt status set

◆ PH3_COMP_DIS_SET

__IOM uint32_t PH3_COMP_DIS_SET

[6..6] Phase 3 comparator output status value if disabled

◆ PH3_COMP_EN

__IOM uint32_t PH3_COMP_EN

[2..2] Phase 3 comparator enable

◆ PH3_ZC_STS

__IM uint32_t PH3_ZC_STS

[27..27] Phase 3 zero crossing comparator status

◆ PH3_ZCFALL_IEN

__IOM uint32_t PH3_ZCFALL_IEN

[4..4] Phase 3 zero crossing falling interrupt enable

◆ PH3_ZCFALL_IS

__IM uint32_t PH3_ZCFALL_IS

[4..4] Phase 3 zero crossing falling interrupt status

◆ PH3_ZCFALL_ISC

__OM uint32_t PH3_ZCFALL_ISC

[4..4] Phase 3 zero crossing falling interrupt status clear

◆ PH3_ZCFALL_ISS

__OM uint32_t PH3_ZCFALL_ISS

[4..4] Phase 3 zero crossing falling interrupt status set

◆ PH3_ZCRISE_IEN

__IOM uint32_t PH3_ZCRISE_IEN

[5..5] Phase 3 zero crossing rising interrupt enable

◆ PH3_ZCRISE_IS

__IM uint32_t PH3_ZCRISE_IS

[5..5] Phase 3 zero crossing rising interrupt status

◆ PH3_ZCRISE_ISC

__OM uint32_t PH3_ZCRISE_ISC

[5..5] Phase 3 zero crossing rising interrupt status clear

◆ PH3_ZCRISE_ISS

__OM uint32_t PH3_ZCRISE_ISS

[5..5] Phase 3 zero crossing rising interrupt status set

◆  [1/2]

union { ... } PROT_CTRL

◆  [2/2]

union { ... } PROT_CTRL

◆  [1/2]

union { ... } PWMSRCSEL

◆  [2/2]

union { ... } PWMSRCSEL

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) Bridge driver control 1

(@ 0x00000004) Bridge driver control 2

(@ 0x00000008) PWM source selection

(@ 0x0000000C) Sequencer mapping

(@ 0x00000010) Delay diagnosis timer

(@ 0x00000014) Charge pump control

(@ 0x00000018) Charge pump clock control

(@ 0x0000001C) Protection function control

(@ 0x00000024) Bridge driver status clear

(@ 0x00000028) Bridge driver status set

(@ 0x00000030) Bridge driver interrupt status clear

(@ 0x00000034) Bridge driver interrupt status set

(@ 0x00000038) Bridge driver interrupt enable

(@ 0x0000003C) Half bridge 1 gate current clamping value

(@ 0x00000040) Half bridge 2 gate current clamping value

(@ 0x00000044) Half bridge 3 gate current clamping value

(@ 0x00000048) Low-side driver 1 active free-wheeling time control

(@ 0x0000004C) Low-side driver 1 active free-wheeling current control

(@ 0x00000050) High-side driver 1 active free-wheeling time control

(@ 0x00000054) High-side driver 1 active free-wheeling current control

(@ 0x00000058) Low-side driver 1 switch-off time control

(@ 0x0000005C) Low-side driver 1 switch-off current control

(@ 0x00000060) Low-side driver 1 switch-on time control

(@ 0x00000064) Low-side driver 1 switch-on current control

(@ 0x00000068) High-side driver 1 switch-off time control

(@ 0x0000006C) High-side driver 1 switch-off current control

(@ 0x00000070) High-side driver 1 switch-on time control

(@ 0x00000074) High-side driver 1 switch-on current control

(@ 0x00000078) Low-side driver 2 active free-wheeling time control

(@ 0x0000007C) Low-side driver 2 active free-wheeling current control

(@ 0x00000080) High-side driver 2 active free-wheeling time control

(@ 0x00000084) High-side driver 2 active free-wheeling current control

(@ 0x00000088) Low-side driver 2 switch-off time control

(@ 0x0000008C) Low-side driver 2 switch-off current control

(@ 0x00000090) Low-side driver 2 switch-on time control

(@ 0x00000094) Low-side driver 2 switch-on current control

(@ 0x00000098) High-side driver 2 switch-off time control

(@ 0x0000009C) High-side driver 2 switch-off current control

(@ 0x000000A0) High-side driver 2 switch-on time control

(@ 0x000000A4) High-side driver 2 switch-on current control

(@ 0x000000A8) Low-side driver 3 active free-wheeling time control

(@ 0x000000AC) Low-side driver 3 active free-wheeling current control

(@ 0x000000B0) High-side driver 3 active free-wheeling time control

(@ 0x000000B4) High-side driver 3 active free-wheeling current control

(@ 0x000000B8) Low-side driver 3 switch-off time control

(@ 0x000000BC) Low-side driver 3 switch-off current control

(@ 0x000000C0) Low-side driver 3 switch-on time control

(@ 0x000000C4) Low-side driver 3 switch-on current control

(@ 0x000000C8) High-side driver 3 switch-off time control

(@ 0x000000CC) High-side driver 3 switch-off current control

(@ 0x000000D0) High-side driver 3 switch-on time control

(@ 0x000000D4) High-side driver 3 switch-on current control

(@ 0x000000D8) Sequencer switch-off phase 4 time and current control

(@ 0x000000DC) High-current discharge mode control

(@ 0x000000E0) Half bridge 1 switch-on measurement values

(@ 0x000000E4) Half bridge 1 switch-off measurement values

(@ 0x000000E8) Half bridge 2 switch-on measurement values

(@ 0x000000EC) Half bridge 2 switch-off measurement values

(@ 0x000000F0) Half bridge 3 switch-on measurement values

(@ 0x000000F4) Half bridge 3 switch-off measurement values

(@ 0x000000F8) Adaptive sequencer control

(@ 0x00000104) Adaptive sequencer error counter control

(@ 0x00000108) Adaptive sequencer minimum switch-on time setting

(@ 0x0000010C) Adaptive sequencer minimum switch-off time setting

(@ 0x00000110) Adaptive sequencer minimum switch-on current setting

(@ 0x00000114) Adaptive sequencer minimum switch-off current setting

(@ 0x00000118) Adaptive sequencer maximum switch-on time setting

(@ 0x0000011C) Adaptive sequencer maximum switch-off time setting

(@ 0x00000120) Adaptive sequencer maximum switch-on current setting

(@ 0x00000124) Adaptive sequencer maximum switch-off current setting

(@ 0x00000128) Adaptive sequencer additional switch-off delay setting

(@ 0x0000012C) BEMF comparator control and status

(@ 0x00000134) BEMF comparator interrupt status clear

(@ 0x00000138) BEMF comparator interrupt status set

(@ 0x0000013C) BEMF comparator interrupt enable

(@ 0x00000140) Bridge driver test control register 1

(@ 0x00000144) Bridge driver test control register 2

(@ 0x00000150) Trimming of driver currents

(@ 0x00000154) Trimming of charge pump voltage

(@ 0x00000158) Trimming of other functions

◆ reg [2/2]

__IM uint32_t reg

(@ 0x00000020) Bridge driver status

(@ 0x0000002C) Bridge driver interrupt status

(@ 0x000000FC) Adaptive sequencer switch-on status

(@ 0x00000100) Adaptive sequencer switch-off status

(@ 0x00000130) BEMF comparator interrupt status

(@ 0x00000148) Threshold BIST counter high-side / back-EMF

(@ 0x0000014C) Threshold BIST counter low-side

◆ SAFE_EN_STS

__IM uint32_t SAFE_EN_STS

[16..16] Safe enable status

◆ SAFE_SD_STS

__IM uint32_t SAFE_SD_STS

[17..17] Safe shutdown status

◆ SEQ_ERR_IEN

__IOM uint32_t SEQ_ERR_IEN

[27..27] Driver sequence error interrupt enable

◆ SEQ_ERR_IS

__IM uint32_t SEQ_ERR_IS

[27..27] Driver sequence error interrupt status

◆ SEQ_ERR_ISC

__OM uint32_t SEQ_ERR_ISC

[27..27] Driver sequence error interrupt status clear

◆ SEQ_ERR_ISS

__OM uint32_t SEQ_ERR_ISS

[27..27] Driver sequence error interrupt status set

◆  [1/2]

union { ... } SEQMAP

◆  [2/2]

union { ... } SEQMAP

◆  [1/2]

union { ... } SEQOFFT4I4

◆  [2/2]

union { ... } SEQOFFT4I4

◆ SH1_HIGH_STS

__IM uint32_t SH1_HIGH_STS

[7..7] SH1 voltage high comparator status

◆ SH1_LOW_STS

__IM uint32_t SH1_LOW_STS

[6..6] SH1 voltage low comparator status

◆ SH2_HIGH_STS

__IM uint32_t SH2_HIGH_STS

[15..15] SH2 voltage high comparator status

◆ SH2_LOW_STS

__IM uint32_t SH2_LOW_STS

[14..14] SH2 voltage low comparator status

◆ SH3_HIGH_STS

__IM uint32_t SH3_HIGH_STS

[23..23] SH3 voltage high comparator status

◆ SH3_LOW_STS

__IM uint32_t SH3_LOW_STS

[22..22] SH3 voltage low comparator status

◆ SPARE_15_14

__IOM uint32_t SPARE_15_14

[15..14] Spare bit

◆ SPARETRIM_15_10

__IOM uint32_t SPARETRIM_15_10

[15..10] Spare bits

◆ SPARETRIM_7_3

__IOM uint32_t SPARETRIM_7_3

[7..3] Spare bits

◆ STRESS_CP

__IOM uint32_t STRESS_CP

[3..3] Vgs stress charge pump enable

◆ STRESS_GDRV

__IOM uint32_t STRESS_GDRV

[2..2] Vgs stress gate driver enable

◆  [1/2]

union { ... } STS

◆  [2/2]

union { ... } STS

◆  [1/2]

union { ... } STSCLR

◆  [2/2]

union { ... } STSCLR

◆  [1/2]

union { ... } STSSET

◆  [2/2]

union { ... } STSSET

◆ SUPERR_STS

__IM uint32_t SUPERR_STS

[28..28] Supply error status

◆ SW_TRIG

__IOM uint32_t SW_TRIG

[24..24] Software trigger for output to timer

◆ T12ONMAX

__IOM uint32_t T12ONMAX

[7..0] Switch-on phases 1 and 2 maximum time setting

◆ T12ONMIN

__IOM uint32_t T12ONMIN

[7..0] Switch-on phases 1 and 2 minimum time setting

◆ T1OFFMAX

__IOM uint32_t T1OFFMAX

[7..0] Switch-off phase 1 maximum time setting

◆ T1OFFMIN

__IOM uint32_t T1OFFMIN

[7..0] Switch-off phase 1 minimum time setting

◆ T4OFF

__IOM uint32_t T4OFF

[5..0] Sequencer switch-off phase 4 time setting for all drivers

◆ TBLNK_SEL

__IOM uint32_t TBLNK_SEL

[12..10] Blanking time for BEMF comparators

◆ 

union { ... } TCR1

◆ 

union { ... } TCR2

◆ THR_CNT_HS1

__IM uint32_t THR_CNT_HS1

[7..0] Threshold BIST counter HS1 DS monitoring, SH1 high comparator and BEMFC1

◆ THR_CNT_HS2

__IM uint32_t THR_CNT_HS2

[15..8] Threshold BIST counter HS2 DS monitoring, SH2 high comparator and BEMFC2

◆ THR_CNT_HS3

__IM uint32_t THR_CNT_HS3

[23..16] Threshold BIST counter HS3 DS monitoring, SH3 high comparator and BEMFC3

◆ 

union { ... } THR_CNT_HS_BEMF

◆ 

union { ... } THR_CNT_LS

◆ THR_CNT_LS1

__IM uint32_t THR_CNT_LS1

[7..0] Threshold BIST counter LS1 DS monitoring and SH1 low comparator

◆ THR_CNT_LS2

__IM uint32_t THR_CNT_LS2

[15..8] Threshold BIST counter LS2 DS monitoring and SH2 low comparator

◆ THR_CNT_LS3

__IM uint32_t THR_CNT_LS3

[23..16] Threshold BIST counter LS3 DS monitoring and SH3 low comparator

◆ TRIG_SEL

__IOM uint32_t TRIG_SEL

[17..16] Trigger output selector

◆ TRIGA_SEL

__IOM uint32_t TRIGA_SEL

[19..19] Deactivate TRIGA as sample pulse source

◆ TRIGB_SEL

__IOM uint32_t TRIGB_SEL

[20..20] Deactivate TRIGB as sample pulse source

◆ 

union { ... } TRIM_CURR

◆ 

union { ... } TRIM_FUNC

◆ 

union { ... } TRIM_VCP

◆ TST_CTRL

__IOM uint32_t TST_CTRL

[31..31] Module test enable signal

◆ VCP_LOTH1_STS

__IM uint32_t VCP_LOTH1_STS

[25..25] VCP measurement low voltage status

◆ VCP_LOTH2_IEN

__IOM uint32_t VCP_LOTH2_IEN

[31..31] Charge pump comparator low voltage interrupt enable

◆ VCP_LOTH2_IS

__IM uint32_t VCP_LOTH2_IS

[31..31] Charge pump comparator low voltage interrupt status

◆ VCP_LOTH2_ISC

__OM uint32_t VCP_LOTH2_ISC

[31..31] Charge pump comparator low voltage interrupt status clear

◆ VCP_LOTH2_ISS

__OM uint32_t VCP_LOTH2_ISS

[31..31] Charge pump comparator low voltage interrupt status set

◆ VCP_LOTH2_SC

__OM uint32_t VCP_LOTH2_SC

[31..31] Charge pump comparator low voltage status clear

◆ VCP_LOTH2_SS

__OM uint32_t VCP_LOTH2_SS

[31..31] Charge pump comparator low voltage status set

◆ VCP_LOTH2_STS

__IM uint32_t VCP_LOTH2_STS

[31..31] Charge pump analog comparator low voltage status

◆ VCP_LOWSRC_SEL

__IOM uint32_t VCP_LOWSRC_SEL

[9..9] Charge pump low voltage detection source select

◆ VCP_LOWTH2

__IOM uint32_t VCP_LOWTH2

[8..8] Charge pump output voltage comparator falling threshold

◆ VCP_LOWTH2_DTB

__IOM uint32_t VCP_LOWTH2_DTB

[19..18] VCP UV threshold DTB input assignment

◆ VCP_TRIM

__IOM uint32_t VCP_TRIM

[1..0] Charge pump output voltage trimming

◆ VCP_TRIM_DTB

__IOM uint32_t VCP_TRIM_DTB

[21..20] VCP trimming DTB input assignment

◆ VCP_UPTH_STS

__IM uint32_t VCP_UPTH_STS

[26..26] VCP measurement high voltage status

◆ VSD_CP1ST_STS

__IM uint32_t VSD_CP1ST_STS

[29..29] VSD measurement status for automatic CP stage selection

◆ VSD_LOTH_STS

__IM uint32_t VSD_LOTH_STS

[27..27] VSD measurement low voltage status

◆ VSD_OV_STS

__IM uint32_t VSD_OV_STS

[30..30] VSD overvoltage comparator status

◆ VSD_UPTH_STS

__IM uint32_t VSD_UPTH_STS

[28..28] VSD measurement high voltage status


The documentation for this struct was generated from the following file: