Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
CSACSC_Type Struct Reference

Detailed Description

CSA and CSC (CSACSC)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CSAC_EN: 1
 
      uint32_t   __pad0__: 7
 
      __IOM uint32_t   GAIN_MIN: 4
 
      __IOM uint32_t   OFFS_MIN: 4
 
      __IOM uint32_t   THR_MAX: 10
 
      uint32_t   __pad1__: 6
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ADD_INP_OFFS: 1
 
      __IOM uint32_t   GAIN_SEL: 2
 
      __IOM uint32_t   OFFS_SEL: 2
 
      uint32_t   __pad0__: 3
 
      __IOM uint32_t   VOUT_SEL: 1
 
      uint32_t   __pad1__: 7
 
      __IOM uint32_t   THR_SEL: 5
 
      uint32_t   __pad2__: 3
 
      __IOM uint32_t   TFILT_SEL: 2
 
      uint32_t   __pad3__: 6
 
   }   bit
 
CTRL2
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   CSC_OC_IS: 1
 
      __IM uint32_t   SEL_ERR_IS: 1
 
      uint32_t   __pad0__: 14
 
      __IM uint32_t   CSC_OC_STS: 1
 
      uint32_t   __pad1__: 7
 
      __IM uint32_t   CSC_OC_OUT: 1
 
      __IM uint32_t   CSC_BIST_STS: 1
 
      uint32_t   __pad2__: 6
 
   }   bit
 
IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CSC_OC_ISC: 1
 
      __OM uint32_t   SEL_ERR_ISC: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   CSC_OC_SC: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CSC_OC_ISS: 1
 
      __OM uint32_t   SEL_ERR_ISS: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   CSC_OC_SS: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
IRQSET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CSC_OC_IEN: 1
 
      __IOM uint32_t   SEL_ERR_IEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IRQEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 12
 
      __IOM uint32_t   CNT_RES_DTB: 2
 
      __IOM uint32_t   CNT_INCR_DTB: 2
 
      __IOM uint32_t   THR_CNT_EN: 1
 
      uint32_t   __pad1__: 7
 
      __IOM uint32_t   ATB0_SEL: 2
 
      uint32_t   __pad2__: 2
 
      __IOM uint32_t   ATB3_SEL: 2
 
      uint32_t   __pad3__: 1
 
      __IOM uint32_t   TST_CTRL: 1
 
   }   bit
 
TCR1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VINP_OFFS_TRIM: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
TRIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CSAC_EN: 1
 
      uint32_t   __pad0__: 7
 
      __IOM uint32_t   GAIN_MIN: 4
 
      __IOM uint32_t   OFFS_MIN: 4
 
      __IOM uint32_t   THR_MAX: 10
 
      uint32_t   __pad1__: 6
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ADD_INP_OFFS: 1
 
      __IOM uint32_t   GAIN_SEL: 2
 
      __IOM uint32_t   OFFS_SEL: 2
 
      uint32_t   __pad0__: 3
 
      __IOM uint32_t   VOUT_SEL: 1
 
      uint32_t   __pad1__: 7
 
      __IOM uint32_t   THR_SEL: 5
 
      uint32_t   __pad2__: 3
 
      __IOM uint32_t   TFILT_SEL: 2
 
      uint32_t   __pad3__: 6
 
   }   bit
 
CTRL2
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   CSC_OC_IS: 1
 
      __IM uint32_t   SEL_ERR_IS: 1
 
      uint32_t   __pad0__: 14
 
      __IM uint32_t   CSC_OC_STS: 1
 
      uint32_t   __pad1__: 7
 
      __IM uint32_t   CSC_OC_OUT: 1
 
      __IM uint32_t   CSC_BIST_STS: 1
 
      uint32_t   __pad2__: 6
 
   }   bit
 
IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CSC_OC_ISC: 1
 
      __OM uint32_t   SEL_ERR_ISC: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   CSC_OC_SC: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CSC_OC_ISS: 1
 
      __OM uint32_t   SEL_ERR_ISS: 1
 
      uint32_t   __pad0__: 14
 
      __OM uint32_t   CSC_OC_SS: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
IRQSET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CSC_OC_IEN: 1
 
      __IOM uint32_t   SEL_ERR_IEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IRQEN
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆ ADD_INP_OFFS

__IOM uint32_t ADD_INP_OFFS

[0..0] Additional input offset setting

◆ ATB0_SEL

__IOM uint32_t ATB0_SEL

[25..24] ATB0 bus assignment

◆ ATB3_SEL

__IOM uint32_t ATB3_SEL

[29..28] ATB3 bus assignment

◆  [1/14]

struct { ... } bit

◆  [2/14]

struct { ... } bit

◆  [3/14]

struct { ... } bit

◆  [4/14]

struct { ... } bit

◆  [5/14]

struct { ... } bit

◆  [6/14]

struct { ... } bit

◆  [7/14]

struct { ... } bit

◆  [8/14]

struct { ... } bit

◆  [9/14]

struct { ... } bit

◆  [10/14]

struct { ... } bit

◆  [11/14]

struct { ... } bit

◆  [12/14]

struct { ... } bit

◆  [13/14]

struct { ... } bit

◆  [14/14]

struct { ... } bit

◆ CNT_INCR_DTB

__IOM uint32_t CNT_INCR_DTB

[15..14] Reference counter increment DTB input connection

◆ CNT_RES_DTB

__IOM uint32_t CNT_RES_DTB

[13..12] Reference counter reset DTB input connection

◆ CSAC_EN

__IOM uint32_t CSAC_EN

[0..0] Current sense amplifier and comparator enable

◆ CSC_BIST_STS

__IM uint32_t CSC_BIST_STS

[25..25] CSC built-in self test status

◆ CSC_OC_IEN

__IOM uint32_t CSC_OC_IEN

[0..0] Overcurrent event interrupt enable

◆ CSC_OC_IS

__IM uint32_t CSC_OC_IS

[0..0] Overcurrent event interrupt status

◆ CSC_OC_ISC

__OM uint32_t CSC_OC_ISC

[0..0] Overcurrent event interrupt status clear

◆ CSC_OC_ISS

__OM uint32_t CSC_OC_ISS

[0..0] Overcurrent event interrupt status set

◆ CSC_OC_OUT

__IM uint32_t CSC_OC_OUT

[24..24] Overcurrent comparator output

◆ CSC_OC_SC

__OM uint32_t CSC_OC_SC

[16..16] Overcurrent event status clear

◆ CSC_OC_SS

__OM uint32_t CSC_OC_SS

[16..16] Overcurrent event status set

◆ CSC_OC_STS

__IM uint32_t CSC_OC_STS

[16..16] Overcurrent event status

◆  [1/2]

union { ... } CTRL1

◆  [2/2]

union { ... } CTRL1

◆  [1/2]

union { ... } CTRL2

◆  [2/2]

union { ... } CTRL2

◆ GAIN_MIN

__IOM uint32_t GAIN_MIN

[11..8] Current sense amplifier minimum gain setting

◆ GAIN_SEL

__IOM uint32_t GAIN_SEL

[2..1] Current sense amplifier gain setting

◆  [1/2]

union { ... } IRQCLR

◆  [2/2]

union { ... } IRQCLR

◆  [1/2]

union { ... } IRQEN

◆  [2/2]

union { ... } IRQEN

◆  [1/2]

union { ... } IRQS

◆  [2/2]

union { ... } IRQS

◆  [1/2]

union { ... } IRQSET

◆  [2/2]

union { ... } IRQSET

◆ OFFS_MIN

__IOM uint32_t OFFS_MIN

[15..12] Current sense amplifier minimum output offset setting

◆ OFFS_SEL

__IOM uint32_t OFFS_SEL

[4..3] Current sense amplifier output offset setting

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) Current sense amplifier and comparator control

(@ 0x00000004) Current sense amplifier and comparator control

(@ 0x0000000C) Current sense amplifier/comparator interrupt status clear

(@ 0x00000010) Current sense amplifier/comparator interrupt status set

(@ 0x00000014) Current sense amplifier/comparator interrupt enable

(@ 0x00000018) Current sense amplifier and comparator test control register

(@ 0x0000001C) Current sense amplifier trimming register

◆ reg [2/2]

__IM uint32_t reg

(@ 0x00000008) Current sense amplifier/comparator interrupt status

◆ SEL_ERR_IEN

__IOM uint32_t SEL_ERR_IEN

[1..1] CSA minimum gain or offset selection error interrupt enable

◆ SEL_ERR_IS

__IM uint32_t SEL_ERR_IS

[1..1] CSA minimum gain or offset selection error interrupt status

◆ SEL_ERR_ISC

__OM uint32_t SEL_ERR_ISC

[1..1] CSA minimum gain or offset selection error interrupt status clear

◆ SEL_ERR_ISS

__OM uint32_t SEL_ERR_ISS

[1..1] CSA minimum gain or offset selection error interrupt status set

◆ 

union { ... } TCR1

◆ TFILT_SEL

__IOM uint32_t TFILT_SEL

[25..24] Filter time for current sense comparator

◆ THR_CNT_EN

__IOM uint32_t THR_CNT_EN

[16..16] Enable 5-bit CSC threshold counter

◆ THR_MAX

__IOM uint32_t THR_MAX

[25..16] Current sense comparator maximum threshold setting

◆ THR_SEL

__IOM uint32_t THR_SEL

[20..16] Current sense comparator threshold setting

◆ 

union { ... } TRIM

◆ TST_CTRL

__IOM uint32_t TST_CTRL

[31..31] Module test enable signal

◆ VINP_OFFS_TRIM

__IOM uint32_t VINP_OFFS_TRIM

[5..0] Current sense amplifier input offset trimming

◆ VOUT_SEL

__IOM uint32_t VOUT_SEL

[8..8] Current sense output selection


The documentation for this struct was generated from the following file: