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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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CANTRX (CANTRX)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EN: 1 | |
__IOM uint32_t MODE: 2 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t EN_TXD_TO: 1 | |
__IOM uint32_t TSIL_EN: 1 | |
uint32_t __pad1__: 6 | |
__IOM uint32_t TXD_IN_SEL: 2 | |
uint32_t __pad2__: 14 | |
} bit | |
} | CTRL |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BUS_TO_IS: 1 | |
__IM uint32_t TXD_TO_IS: 1 | |
__IM uint32_t OT_IS: 1 | |
__IM uint32_t BUS_ACT_IS: 1 | |
uint32_t __pad0__: 12 | |
__IM uint32_t BUS_TO_STS: 1 | |
__IM uint32_t TXD_TO_STS: 1 | |
__IM uint32_t OT_STS: 1 | |
uint32_t __pad1__: 1 | |
__IM uint32_t UV_STS: 1 | |
uint32_t __pad2__: 11 | |
} bit | |
} | IRQS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t BUS_TO_ISC: 1 | |
__OM uint32_t TXD_TO_ISC: 1 | |
__OM uint32_t OT_ISC: 1 | |
__OM uint32_t BUS_ACT_ISC: 1 | |
uint32_t __pad0__: 12 | |
__OM uint32_t BUS_TO_SC: 1 | |
__OM uint32_t TXD_TO_SC: 1 | |
__OM uint32_t OT_SC: 1 | |
uint32_t __pad1__: 13 | |
} bit | |
} | IRQCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t BUS_TO_ISS: 1 | |
__OM uint32_t TXD_TO_ISS: 1 | |
__OM uint32_t OT_ISS: 1 | |
__OM uint32_t BUS_ACT_ISS: 1 | |
uint32_t __pad0__: 12 | |
__OM uint32_t BUS_TO_SS: 1 | |
__OM uint32_t TXD_TO_SS: 1 | |
__OM uint32_t OT_SS: 1 | |
uint32_t __pad1__: 13 | |
} bit | |
} | IRQSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BUS_TO_IEN: 1 | |
__IOM uint32_t TXD_TO_IEN: 1 | |
__IOM uint32_t OT_IEN: 1 | |
__IOM uint32_t BUS_ACT_IEN: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | IRQEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTB0_OUT: 2 | |
__IOM uint32_t DTB1_OUT: 2 | |
__IOM uint32_t DTB2_OUT: 2 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t DTB5_OUT: 2 | |
__IOM uint32_t TXD_DTB: 1 | |
__IOM uint32_t WAKE_EN_DTB: 1 | |
__IOM uint32_t RX_EN_DTB: 2 | |
__IOM uint32_t TX_EN_DTB: 2 | |
__IOM uint32_t TSD_EN_DTB: 1 | |
__IOM uint32_t VCAN_UV_DTB: 1 | |
uint32_t __pad1__: 6 | |
__IOM uint32_t ATB2_SEL: 1 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t MI_EN: 1 | |
__IOM uint32_t TST_CTRL: 1 | |
} bit | |
} | TCR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BUS_BIAS_ZERO: 1 | |
__IOM uint32_t BUS_BIAS_EN: 1 | |
__IOM uint32_t BUS_BIAS_5VPD: 1 | |
__IOM uint32_t FORCE_VDD_TM: 1 | |
__IOM uint32_t SHORT_TSIL: 1 | |
__IOM uint32_t RX_SINGLE: 1 | |
__IOM uint32_t RX_EN: 1 | |
__IOM uint32_t RX_FILTBYP_TM: 1 | |
__IOM uint32_t TSD_EN: 1 | |
__IOM uint32_t TSD_TM_EN: 1 | |
__IOM uint32_t TX_ADD_JITTER: 1 | |
__IOM uint32_t TX_EN: 1 | |
__IOM uint32_t EN_UV_CAN: 1 | |
__IOM uint32_t RX_CLK_EN: 1 | |
uint32_t __pad0__: 1 | |
__IM uint32_t RX_OK: 1 | |
__IM uint32_t CNT_LOOP: 6 | |
uint32_t __pad1__: 10 | |
} bit | |
} | TCR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RX_VTH: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t RX_FCLK: 7 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t RX_TFALL: 3 | |
__IOM uint32_t RX_TRISE: 3 | |
uint32_t __pad2__: 10 | |
} bit | |
} | TRIM_PARAM |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TSD_TH: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t TX_ASYM: 3 | |
__IOM uint32_t TX_SR: 3 | |
__IOM uint32_t TX_LOW_CIN: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t RX_CLK_F: 1 | |
uint32_t __pad2__: 7 | |
__IOM uint32_t WK_TH: 4 | |
__IOM uint32_t WK_TH_HIGH: 1 | |
uint32_t __pad3__: 3 | |
} bit | |
} | TRIM_FUNC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EN: 1 | |
__IOM uint32_t MODE: 2 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t EN_TXD_TO: 1 | |
__IOM uint32_t TSIL_EN: 1 | |
uint32_t __pad1__: 6 | |
__IOM uint32_t TXD_IN_SEL: 2 | |
uint32_t __pad2__: 14 | |
} bit | |
} | CTRL |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BUS_TO_IS: 1 | |
__IM uint32_t TXD_TO_IS: 1 | |
__IM uint32_t OT_IS: 1 | |
__IM uint32_t BUS_ACT_IS: 1 | |
uint32_t __pad0__: 12 | |
__IM uint32_t BUS_TO_STS: 1 | |
__IM uint32_t TXD_TO_STS: 1 | |
__IM uint32_t OT_STS: 1 | |
uint32_t __pad1__: 1 | |
__IM uint32_t UV_STS: 1 | |
uint32_t __pad2__: 11 | |
} bit | |
} | IRQS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t BUS_TO_ISC: 1 | |
__OM uint32_t TXD_TO_ISC: 1 | |
__OM uint32_t OT_ISC: 1 | |
__OM uint32_t BUS_ACT_ISC: 1 | |
uint32_t __pad0__: 12 | |
__OM uint32_t BUS_TO_SC: 1 | |
__OM uint32_t TXD_TO_SC: 1 | |
__OM uint32_t OT_SC: 1 | |
uint32_t __pad1__: 13 | |
} bit | |
} | IRQCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t BUS_TO_ISS: 1 | |
__OM uint32_t TXD_TO_ISS: 1 | |
__OM uint32_t OT_ISS: 1 | |
__OM uint32_t BUS_ACT_ISS: 1 | |
uint32_t __pad0__: 12 | |
__OM uint32_t BUS_TO_SS: 1 | |
__OM uint32_t TXD_TO_SS: 1 | |
__OM uint32_t OT_SS: 1 | |
uint32_t __pad1__: 13 | |
} bit | |
} | IRQSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BUS_TO_IEN: 1 | |
__IOM uint32_t TXD_TO_IEN: 1 | |
__IOM uint32_t OT_IEN: 1 | |
__IOM uint32_t BUS_ACT_IEN: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | IRQEN |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
__IOM uint32_t ATB2_SEL |
[26..26] ATB2 bus assignment
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IOM uint32_t BUS_ACT_IEN |
[3..3] Bus active during CAN sleep interrupt enable
__IM uint32_t BUS_ACT_IS |
[3..3] Bus active during CAN sleep interrupt status
__OM uint32_t BUS_ACT_ISC |
[3..3] Bus active during CAN sleep interrupt status clear
__OM uint32_t BUS_ACT_ISS |
[3..3] Bus active during CAN sleep interrupt status set
__IOM uint32_t BUS_BIAS_5VPD |
[2..2] Bus bias VDD5V_PD enable
__IOM uint32_t BUS_BIAS_EN |
[1..1] Bus bias enable
__IOM uint32_t BUS_BIAS_ZERO |
[0..0] Bus bias to ground enable
__IOM uint32_t BUS_TO_IEN |
[0..0] Bus dominant timeout interrupt enable
__IM uint32_t BUS_TO_IS |
[0..0] Bus dominant timeout interrupt status
__OM uint32_t BUS_TO_ISC |
[0..0] Bus dominant timeout interrupt status clear
__OM uint32_t BUS_TO_ISS |
[0..0] Bus dominant timeout interrupt status set
__OM uint32_t BUS_TO_SC |
[16..16] Bus dominant timeout status clear
__OM uint32_t BUS_TO_SS |
[16..16] Bus dominant timeout status set
__IM uint32_t BUS_TO_STS |
[16..16] Bus dominant timeout status
__IM uint32_t CNT_LOOP |
[21..16] TRX loop delay measurement counter
union { ... } CTRL |
union { ... } CTRL |
__IOM uint32_t DTB0_OUT |
[1..0] DTB0 output assignment
__IOM uint32_t DTB1_OUT |
[3..2] DTB1 output assignment
__IOM uint32_t DTB2_OUT |
[5..4] DTB2 output assignment
__IOM uint32_t DTB5_OUT |
[11..10] DTB5 output assignment
__IOM uint32_t EN |
[0..0] CAN transceiver enable
__IOM uint32_t EN_TXD_TO |
[8..8] Enable transmitter deactivation due to TXD dominant timeout
__IOM uint32_t EN_UV_CAN |
[12..12] CAN supply undervoltage shutdown enable
__IOM uint32_t FORCE_VDD_TM |
[3..3] Force VDD enable
union { ... } IRQCLR |
union { ... } IRQCLR |
union { ... } IRQEN |
union { ... } IRQEN |
union { ... } IRQS |
union { ... } IRQS |
union { ... } IRQSET |
union { ... } IRQSET |
__IOM uint32_t MI_EN |
[30..30] Module isolation mode
__IOM uint32_t MODE |
[2..1] CAN mode control
__IOM uint32_t OT_IEN |
[2..2] CAN overtemperature interrupt enable
__IM uint32_t OT_IS |
[2..2] CAN overtemperature interrupt status
__OM uint32_t OT_ISC |
[2..2] CAN overtemperature interrupt status clear
__OM uint32_t OT_ISS |
[2..2] CAN overtemperature interrupt status set
__OM uint32_t OT_SC |
[18..18] CAN overtemperature status clear
__OM uint32_t OT_SS |
[18..18] CAN overtemperature status set
__IM uint32_t OT_STS |
[18..18] CAN overtemperature status
__IOM uint32_t reg |
(@ 0x00000000) CAN transceiver control
(@ 0x00000008) CAN transceiver interrupt status register clear
(@ 0x0000000C) CAN transceiver interrupt status register set
(@ 0x00000010) CAN transceiver interrupt enable
(@ 0x00000014) CAN transceiver test control register 1
(@ 0x00000018) CAN transceiver test control register 2
(@ 0x0000001C) CAN transceiver trimming register
(@ 0x00000020) CAN transceiver trimming register
__IM uint32_t reg |
(@ 0x00000004) CAN transceiver interrupt status
__IOM uint32_t RX_CLK_EN |
[13..13] RX oscillator enable
__IOM uint32_t RX_CLK_F |
[16..16] Receiver clock frequency range
__IOM uint32_t RX_EN |
[6..6] Receiver enable
__IOM uint32_t RX_EN_DTB |
[15..14] Receiver enable DTB input assignment
__IOM uint32_t RX_FCLK |
[14..8] Receiver clock frequency
__IOM uint32_t RX_FILTBYP_TM |
[7..7] Receiver filter bypass for hysteresis
__IM uint32_t RX_OK |
[15..15] Receiver output BIST
__IOM uint32_t RX_SINGLE |
[5..5] Use only one receiver
__IOM uint32_t RX_TFALL |
[18..16] Receiver output filter trimming (increase recessive bit width)
__IOM uint32_t RX_TRISE |
[21..19] Receiver output filter trimming (reduce recessive bit width)
__IOM uint32_t RX_VTH |
[3..0] Receiver threshold recessive-to-dominant
__IOM uint32_t SHORT_TSIL |
[4..4] Short tsilence
union { ... } TCR1 |
union { ... } TCR2 |
union { ... } TRIM_FUNC |
union { ... } TRIM_PARAM |
__IOM uint32_t TSD_EN |
[8..8] Temperature sensor / thermal shutdown enable
__IOM uint32_t TSD_EN_DTB |
[18..18] Thermal sensor enable DTB input assignment
__IOM uint32_t TSD_TH |
[3..0] Thermal shutdown threshold
__IOM uint32_t TSD_TM_EN |
[9..9] Temperature sensor testmode enable
__IOM uint32_t TSIL_EN |
[9..9] Enable tsilence counter
__IOM uint32_t TST_CTRL |
[31..31] Module test enable signal
__IOM uint32_t TX_ADD_JITTER |
[10..10] TX jitter enable
__IOM uint32_t TX_ASYM |
[10..8] Transmitter-to-bus delay asymmetry
__IOM uint32_t TX_EN |
[11..11] Transmitter enable
__IOM uint32_t TX_EN_DTB |
[17..16] Transmitter enable DTB input assignment
__IOM uint32_t TX_LOW_CIN |
[14..14] Bus input capacitance setting
__IOM uint32_t TX_SR |
[13..11] Transmitter slew rate setting
__IOM uint32_t TXD_DTB |
[12..12] TXD DTB input assignment
__IOM uint32_t TXD_IN_SEL |
[17..16] TXD input selector
__IOM uint32_t TXD_TO_IEN |
[1..1] TXD dominant timeout interrupt enable
__IM uint32_t TXD_TO_IS |
[1..1] TXD dominant timeout interrupt status
__OM uint32_t TXD_TO_ISC |
[1..1] TXD dominant timeout interrupt status clear
__OM uint32_t TXD_TO_ISS |
[1..1] TXD dominant timeout interrupt status set
__OM uint32_t TXD_TO_SC |
[17..17] TXD dominant timeout status clear
__OM uint32_t TXD_TO_SS |
[17..17] TXD dominant timeout status set
__IM uint32_t TXD_TO_STS |
[17..17] TXD dominant timeout status
__IM uint32_t UV_STS |
[20..20] CAN supply undervoltage status
__IOM uint32_t VCAN_UV_DTB |
[19..19] VCAN UV error DTB input assignment
__IOM uint32_t WAKE_EN_DTB |
[13..13] Wake receiver enable DTB input assignment
__IOM uint32_t WK_TH |
[27..24] Wake receiver threshold recessive-to-dominant
__IOM uint32_t WK_TH_HIGH |
[28..28] Wake receiver threshold range