Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
BP_Type Struct Reference

Detailed Description

BP (BP)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CYCCNTENA: 1
 
      __IOM uint32_t   POSTPRESET: 4
 
      __IOM uint32_t   POSTINIT: 4
 
      __IOM uint32_t   CYCTAP: 1
 
      __IOM uint32_t   SYNCTAP: 2
 
      __IOM uint32_t   PCSAMPLENA: 1
 
      __IOM uint32_t   SPARE: 3
 
      __IOM uint32_t   EXCTRCENA: 1
 
      __IOM uint32_t   CPIEVTENA: 1
 
      __IOM uint32_t   EXCEVTENA: 1
 
      __IOM uint32_t   SLEEPEVTENA: 1
 
      __IOM uint32_t   LSUEVTENA: 1
 
      __IOM uint32_t   FOLDEVTENA: 1
 
      __IOM uint32_t   CYCEVTENA: 1
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   NOPRFCNT: 1
 
      __IM uint32_t   NOCYCCNT: 1
 
      __IM uint32_t   NOEXITTRIG: 1
 
      __IM uint32_t   NOTRCPKT: 1
 
      __IM uint32_t   NUMCOMP: 4
 
   }   bit
 
DWT_CTRL
 
__IM uint32_t RESERVED [6]
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   EIASAMPLE: 32
 
   }   bit
 
DWT_PCSR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   COMP: 32
 
   }   bit
 
DWT_COMP0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MASK: 4
 
      uint32_t   __pad0__: 28
 
   }   bit
 
DWT_MASK0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FUNCTION: 4
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   EMITRANGE: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   CYCMATCH: 1
 
      uint32_t   __pad2__: 16
 
      __IM uint32_t   MATCHED: 1
 
      uint32_t   __pad3__: 7
 
   }   bit
 
DWT_FUNCTION0
 
__IM uint32_t RESERVED1 [1013]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ENABLE: 1
 
      __OM uint32_t   KEY: 1
 
      uint32_t   __pad0__: 2
 
      __IM uint32_t   NUM_CODE: 4
 
      __IM uint32_t   NUM_LIT: 4
 
      __IM uint32_t   NUM_CODE6_4: 3
 
      uint32_t   __pad1__: 13
 
      __IM uint32_t   REV: 4
 
   }   bit
 
BP_CTRL
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ENABLE: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   COMP: 27
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   REPLACE: 2
 
   }   bit
 
BP_COMP0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ENABLE: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   COMP: 27
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   REPLACE: 2
 
   }   bit
 
BP_COMP1
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆  [1/8]

struct { ... } bit

◆  [2/8]

struct { ... } bit

◆  [3/8]

struct { ... } bit

◆  [4/8]

struct { ... } bit

◆  [5/8]

struct { ... } bit

◆  [6/8]

struct { ... } bit

◆  [7/8]

struct { ... } bit

◆  [8/8]

struct { ... } bit

◆ 

union { ... } BP_COMP0

◆ 

union { ... } BP_COMP1

◆ 

union { ... } BP_CTRL

◆ COMP

__IOM uint32_t COMP

[31..0] Reference value for comparison

[28..2] Comparison address

◆ CPIEVTENA

__IOM uint32_t CPIEVTENA

[17..17] Cycle Per Instruction counter overflow event enable

◆ CYCCNTENA

__IOM uint32_t CYCCNTENA

[0..0] Cycle Counter enable

◆ CYCEVTENA

__IOM uint32_t CYCEVTENA

[22..22] POSTCNT underflow event enable

◆ CYCMATCH

__IOM uint32_t CYCMATCH

[7..7] Comparator Cycle Match Comparison Enable

◆ CYCTAP

__IOM uint32_t CYCTAP

[9..9] Selects the position of the POSTCNT tap on the CYCCNT counter:

◆ 

union { ... } DWT_COMP0

◆ 

union { ... } DWT_CTRL

◆ 

union { ... } DWT_FUNCTION0

◆ 

union { ... } DWT_MASK0

◆ 

union { ... } DWT_PCSR

◆ EIASAMPLE

__IM uint32_t EIASAMPLE

[31..0] Program Counter Value

◆ EMITRANGE

__IOM uint32_t EMITRANGE

[5..5] enables generation of Data trace address packets

◆ ENABLE

__IOM uint32_t ENABLE

[0..0] Enables Break Point Unit

[0..0] Breakpoint comparator enable

◆ EXCEVTENA

__IOM uint32_t EXCEVTENA

[18..18] Exception overhead counter overflow event enable

◆ EXCTRCENA

__IOM uint32_t EXCTRCENA

[16..16] Exception trace enable

◆ FOLDEVTENA

__IOM uint32_t FOLDEVTENA

[21..21] Fold instruction counter overflow event enable

◆ FUNCTION

__IOM uint32_t FUNCTION

[3..0] Comparator Match Action Select

◆ KEY

__OM uint32_t KEY

[1..1] Write operation onto register BP_CTRL enable

◆ LSUEVTENA

__IOM uint32_t LSUEVTENA

[20..20] Load and Store Unit cycle counter overflow event enable

◆ MASK

__IOM uint32_t MASK

[3..0] Size of ignore mask

◆ MATCHED

__IM uint32_t MATCHED

[24..24] Comparator Match Status

◆ NOCYCCNT

__IM uint32_t NOCYCCNT

[25..25] Support Cycle Counters

◆ NOEXITTRIG

__IM uint32_t NOEXITTRIG

[26..26] Support External Match

◆ NOPRFCNT

__IM uint32_t NOPRFCNT

[24..24] Support Profiling Counters

◆ NOTRCPKT

__IM uint32_t NOTRCPKT

[27..27] Support Trace Sampling

◆ NUM_CODE

__IM uint32_t NUM_CODE

[7..4] Number of Breakpoint Comparators Bits 4 to 0

◆ NUM_CODE6_4

__IM uint32_t NUM_CODE6_4

[14..12] Number of breakpoint comparators, bits 6 to 4

◆ NUM_LIT

__IM uint32_t NUM_LIT

[11..8] Number of literal address comparators

◆ NUMCOMP

__IM uint32_t NUMCOMP

[31..28] Number of Breakpoint Comparators

◆ PCSAMPLENA

__IOM uint32_t PCSAMPLENA

[12..12] Periodic PC (Program Counter) sample enable

◆ POSTINIT

__IOM uint32_t POSTINIT

[8..5] Initial value for the POSTCNT Timer counter

◆ POSTPRESET

__IOM uint32_t POSTPRESET

[4..1] Reload value for the POSTCNT Timer counter

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) Control Register

(@ 0x00000020) Comparator Register 0

(@ 0x00000024) Comparator Mask Register 0

(@ 0x00000028) Function Register 0

(@ 0x00001000) Breakpoint Control Register

(@ 0x00001008) Breakpoint Comparator Register 0

(@ 0x0000100C) Breakpoint Comparator Register 1

◆ reg [2/2]

__IM uint32_t reg

(@ 0x0000001C) Program Counter Sample Register

◆ REPLACE

__IOM uint32_t REPLACE

[31..30] Behavior by a comparison match

◆ RESERVED

__IM uint32_t RESERVED[6]

◆ RESERVED1

__IM uint32_t RESERVED1[1013]

◆ RESERVED2

__IM uint32_t RESERVED2

◆ REV

__IM uint32_t REV

[31..28] Flash Patch breakpoint architecture revision

◆ SLEEPEVTENA

__IOM uint32_t SLEEPEVTENA

[19..19] Sleep counter overflow event enable

◆ SPARE

__IOM uint32_t SPARE

[15..13] SPARE

◆ SYNCTAP

__IOM uint32_t SYNCTAP

[11..10] Selection of the position of the synchronization packet counter tap on the CYCNT counter


The documentation for this struct was generated from the following file: