Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
startup_tle989x.h
Go to the documentation of this file.
1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** JO Julia Ott **
45 ** PS Patrik Schwarz **
46 ** VO Vanessa Ongaro **
47 *******************************************************************************/
48 
49 /*******************************************************************************
50 ** Revision Control History **
51 ********************************************************************************
52 ** V0.1.0: 2022-08-18, JO: EP-1235: Initial version of startup file in C **
53 ** V0.1.1: 2023-05-15, PS: EP-1441: Update c startup file and linker file **
54 ** for IAR to use sections **
55 ** V0.1.2: 2023-08-10, VO: EP-1464: Put debug_entry also in deprecated VTOR **
56 ** Fixed location of ER_NVM0_DEBUG_CONNECT **
57 ** in sct files **
58 ** V0.1.3: 2023-11-29, VO: EP-1465: Added chache enable to reset handler **
59 *******************************************************************************/
60 
61 /* Work instructions:
62  When using this startup file, the project needs a linker script.
63  The linker script is has already been copied to the
64  RTE/Device/--devicename-- folder of this project and
65  needs to be added to the project manually.
66  Keil:
67  'Options for target'
68  --> 'Linker' tab
69  --> uncheck 'Use Memory Layout from Rarget Dialog'
70  --> Scatter file: '...'
71  --> add the linker file mentioned above (tle9881_91.sct or tle9883_93.sct)
72 */
73 
74 #include "tle989x.h"
75 #include "bootrom.h"
76 #include "tle_variants.h"
77 #include "bsl_defines.h"
78 #include "scu_defines.h"
79 
80 /*---------------------------------------------------------------------------
81  External References
82  *---------------------------------------------------------------------------*/
83 extern uint32_t __INITIAL_SP;
84 extern uint32_t __STACK_LIMIT;
85 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
86  extern uint32_t __STACK_SEAL;
87 #endif
88 
92 typedef void(*VECTOR_TABLE_Type)(void);
93 
94 extern __NO_RETURN void __PROGRAM_START(void);
95 
96 #if defined(__ARMCC_VERSION)
97  /* Arm Compiler V5 and V6 */
98  __attribute__((noreturn)) static void debug_entry(void) __attribute__((section("sec_NVM0_DEBUG_CONNECT"), used));
99 #elif defined(__IAR_SYSTEMS_ICC__)
100  /* IAR compiler */
101  __attribute__((noreturn)) static void debug_entry(void) @ "sec_NVM0_DEBUG_CONNECT";
102 #elif defined(UNIT_TESTING_OCN)
103  __attribute__((noreturn)) static void debug_entry(void);
104 #endif
105 
106 
107 
108 /*---------------------------------------------------------------------------
109  Internal References
110  *---------------------------------------------------------------------------*/
111 __NO_RETURN void Reset_Handler (void);
112 __NO_RETURN void Default_Handler(void);
113 __NO_RETURN static void debug_entry(void);
114 
115 /* ToDo: Add Cortex exception handler according the used Cortex-Core */
116 /*---------------------------------------------------------------------------
117  Exception / Interrupt Handler
118  *---------------------------------------------------------------------------*/
119 /* Exceptions */
120 void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
121 void HardFault_Handler (void) __attribute__ ((weak));
122 void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
123 void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
124 void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
125 //void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
126 void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
127 void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
128 void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
129 void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
130 
131 /* ToDo: Add your device specific interrupt handler */
132 //void <DeviceInterrupt first>_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
133 //...
134 //void <DeviceInterrupt last>_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
135 void NVIC_IRQ0_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 0: PMU, BDRV, CSC, ARVG
136 void NVIC_IRQ1_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 1: PMU, BDRV, CSC, ARVG
137 void NVIC_IRQ2_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 2: CCU7
138 void NVIC_IRQ3_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 3: CCU7
139 void NVIC_IRQ4_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 4: CCU7
140 void NVIC_IRQ5_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 5: CCU7
141 //0x000000c1 // 6: MEMCTRL
142 void NVIC_IRQ7_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 7: GPT12E
143 void NVIC_IRQ8_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 8: GPT12E
144 void NVIC_IRQ9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); // 9: Timer2
145 void NVIC_IRQ10_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 10: ADC2
146 void NVIC_IRQ11_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 11: ADC2
147 void NVIC_IRQ12_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 12: MON
148 void NVIC_IRQ13_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 13: MON
149 void NVIC_IRQ14_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 14: ADC1
150 void NVIC_IRQ15_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 15: ADC1
151 void NVIC_IRQ16_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 16: ADC1
152 void NVIC_IRQ17_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 17: ADC1
153 void NVIC_IRQ18_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 18: BEMF, SDADC
154 void NVIC_IRQ19_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 19: BEMF, SDADC
155 void NVIC_IRQ20_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 20: EXTINT
156 void NVIC_IRQ21_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 21: EXTINT
157 void NVIC_IRQ22_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 22: UART0/1, LIN
158 void NVIC_IRQ23_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 23: UART0/1, LIN
159 void NVIC_IRQ24_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 24: SSC0/1
160 void NVIC_IRQ25_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 25: SSC0/1
161 void NVIC_IRQ26_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 26: MultiCAN
162 void NVIC_IRQ27_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 27: MultiCAN
163 void NVIC_IRQ28_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 28: MultiCAN
164 void NVIC_IRQ29_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 29: DMA
165 void NVIC_IRQ30_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 30: DMA
166 void NVIC_IRQ31_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); // 31: Timer21
167 
168 
169 
170 
171 /*----------------------------------------------------------------------------
172  Exception / Interrupt Vector table
173  *----------------------------------------------------------------------------*/
174 
175 #if defined ( __GNUC__ )
176  #pragma GCC diagnostic push
177  #pragma GCC diagnostic ignored "-Wpedantic"
178 #endif
179 
180 #if defined(__ARMCC_VERSION)
181  /* Arm Compiler V5 and V6 */
182  static const uint32 u32_flash0_page0[11] __attribute__((section("sec_NVM0_BOOTCFG"), used)) =
183 #elif defined(__IAR_SYSTEMS_ICC__)
184  /* IAR compiler */
185  __root const uint32 u32_flash0_page0[11] @ "sec_NVM0_BOOTCFG" =
186 #elif defined(UNIT_TESTING_OCN)
187  const uint32 u32_flash0_page0[11] =
188 #endif
189 {
190  (uint32)BSL_NAD_NAC, /* 0x00: NAC,NAD */
191  0xFFFFFFFF, /* 0x04: reserved */
192  0xFFFFFFFF, /* 0x08: Secure Boot Hash */
193  0xFFFFFFFF, /* 0x0C: Secure Boot Hash */
194  0xFFFFFFFF, /* 0x10: Secure Boot Hash */
195  0xFFFFFFFF, /* 0x14: Secure Boot Hash */
196  0xFFFFFFFF, /* 0x18: reserved */
197  0xFFFFFFFF, /* 0x1C: reserved */
198  0xFFFFFFFF, /* 0x20: reserved */
199  0xFFFFFFFF, /* 0x24: User BSL Code Size */
200  0xFFFFFFFF, /* 0x28: Secure Key ID */
201 };
202 
203 
204 #if defined(__ARMCC_VERSION)
205  /* Arm Compiler V5 and V6 */
206  static const VECTOR_TABLE_Type vt_vectab_deprecated[2] __attribute__((section("sec_NVM0_VECTAB_DEPRECATED"), used)) =
207 #elif defined(__IAR_SYSTEMS_ICC__)
208  /* IAR compiler: __root needed so that the variable is not optimized away */
209  __root const VECTOR_TABLE_Type vt_vectab_deprecated[2] @ "sec_NVM0_VECTAB_DEPRECATED" =
210 #elif defined(UNIT_TESTING_OCN)
211  static const VECTOR_TABLE_Type vt_vectab_deprecated[2] =
212 #endif
213 {
214  (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
215  debug_entry, /* Reset Handler */
216 };
217 
218 
219 
220 
221 __attribute__((noreturn)) static void debug_entry(void)
222 {
223 #define SCU_BOOT_CFG_LATCH_ADDR 0x480040BC
224 #define SCU_BOOT_CFG_LATCH_TMS_MASK 0x00000001
225 #define SCU_BOOT_CFG_LATCH_P00_MASK 0x00000002
226 #define CPU_DHCSR_ADDR 0xE000EDF0
227 #define CPU_DHCSR_C_DEBUGEN_MASK 0x00000001
228  uint32 u32_boot_cfg_latch;
229  uint32 u32_dhcsr_c_debugen;
230  u32_boot_cfg_latch = *(uint32 *)SCU_BOOT_CFG_LATCH_ADDR;
231 
233  {
234  do
235  {
236  u32_dhcsr_c_debugen = (*(uint32 *)CPU_DHCSR_ADDR) & CPU_DHCSR_C_DEBUGEN_MASK;
237  }
238  while (u32_dhcsr_c_debugen == 0);
239  }
240 
241  Reset_Handler();
242 }
243 
244 
245 /* ToDo: Add Cortex exception vectors according the used Cortex-Core */
247 
248 #if defined(__ARMCC_VERSION)
249 /* Arm Compiler V5 and V6 */
250 const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE =
251 {
252 #elif defined(__IAR_SYSTEMS_ICC__)
253 /* IAR compiler */
254 const VECTOR_TABLE_Type __VECTOR_TABLE[48] @ "sec_NVM0_VECTAB" = {
255 #elif defined(UNIT_TESTING_OCN)
256 const VECTOR_TABLE_Type __VECTOR_TABLE[48] = {
257 #endif
258  (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
259  debug_entry, /* Reset Handler */
260  NMI_Handler, /* -14 NMI Handler */
261  HardFault_Handler, /* -13 Hard Fault Handler */
262  MemManage_Handler, /* -12 MPU Fault Handler */
263  BusFault_Handler, /* -11 Bus Fault Handler */
264  UsageFault_Handler, /* -10 Usage Fault Handler */
265  0, /* -9 Secure Fault Handler */
266  0, /* Reserved */
267  0, /* Reserved */
268  0, /* Reserved */
269  SVC_Handler, /* -5 SVCall Handler */
270  DebugMon_Handler, /* -4 Debug Monitor Handler */
271  0, /* Reserved */
272  PendSV_Handler, /* -2 PendSV Handler */
273  SysTick_Handler, /* -1 SysTick Handler */
274 
275  /* ToDo: Add your device specific interrupt vectors */
276  /* Interrupts */
277  // <DeviceInterrupt first>_Handler, /* first Device Interrupt */
278  // ...
279  // <DeviceInterrupt last>_Handler /* last Device Interrupt */
280  NVIC_IRQ0_Handler, // 0: PMU, BDRV, CSC, ARVG
281  NVIC_IRQ1_Handler, // 1: PMU, BDRV, CSC, ARVG
282  NVIC_IRQ2_Handler, // 2: CCU7
283  NVIC_IRQ3_Handler, // 3: CCU7
284  NVIC_IRQ4_Handler, // 4: CCU7
285  NVIC_IRQ5_Handler, // 5: CCU7
286  (VECTOR_TABLE_Type)0x000000c1, // 6: MEMCTRL
287  NVIC_IRQ7_Handler, // 7: GPT12E
288  NVIC_IRQ8_Handler, // 8: GPT12E
289  NVIC_IRQ9_Handler, // 9: Timer2
290  NVIC_IRQ10_Handler, // 10: ADC2
291  NVIC_IRQ11_Handler, // 11: ADC2
292  NVIC_IRQ12_Handler, // 12: MON
293  NVIC_IRQ13_Handler, // 13: MON
294  NVIC_IRQ14_Handler, // 14: ADC1
295  NVIC_IRQ15_Handler, // 15: ADC1
296  NVIC_IRQ16_Handler, // 16: ADC1
297  NVIC_IRQ17_Handler, // 17: ADC1
298  NVIC_IRQ18_Handler, // 18: BEMF, SDADC
299  NVIC_IRQ19_Handler, // 19: BEMF, SDADC
300  NVIC_IRQ20_Handler, // 20: EXTINT
301  NVIC_IRQ21_Handler, // 21: EXTINT
302  NVIC_IRQ22_Handler, // 22: UART0/1, LIN
303  NVIC_IRQ23_Handler, // 23: UART0/1, LIN
304  NVIC_IRQ24_Handler, // 24: SSC0/1
305  NVIC_IRQ25_Handler, // 25: SSC0/1
306  NVIC_IRQ26_Handler, // 26: MultiCAN
307  NVIC_IRQ27_Handler, // 27: MultiCAN
308  NVIC_IRQ28_Handler, // 28: MultiCAN
309  NVIC_IRQ29_Handler, // 29: DMA
310  NVIC_IRQ30_Handler, // 30: DMA
311  NVIC_IRQ31_Handler // 31: Timer21
312 };
313 
314 #if defined ( __GNUC__ )
315 #pragma GCC diagnostic pop
316 #endif
317 
318 /*---------------------------------------------------------------------------
319  Reset Handler called on controller reset
320  *---------------------------------------------------------------------------*/
321 __NO_RETURN void Reset_Handler(void)
322 {
323  __set_PSP((uint32_t)(&__INITIAL_SP));
324  /* ToDo: Initialize stack limit register for Armv8-M Main Extension based processors*/
325  // __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
326  // __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
327  /* ToDo: Add stack sealing for Armv8-M based processors */
328 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
329  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
330 #endif
331 
332  /* Enable Flash1 caching according to CW setting */
333  if(FLASH1_CACHE_EN == 1)
334  {
336  }
337 
338  SystemInit(); /* CMSIS System Initialization */
339  __PROGRAM_START(); /* Enter PreMain (C library entry point) */
340 }
341 
342 
343 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
344 #pragma clang diagnostic push
345 #pragma clang diagnostic ignored "-Wmissing-noreturn"
346 #endif
347 
348 /*---------------------------------------------------------------------------
349  Hard Fault Handler
350  *---------------------------------------------------------------------------*/
351 void HardFault_Handler(void)
352 {
353  while (1);
354 }
355 
356 /*---------------------------------------------------------------------------
357  Default Handler for Exceptions / Interrupts
358  *---------------------------------------------------------------------------*/
359 void Default_Handler(void)
360 {
361  while (1);
362 }
363 
364 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
365 #pragma clang diagnostic pop
366 #endif
BootROM low level access library.
#define user_cache_operation
This user API function provides an alternative to writing to cache registers in addition to direct re...
Definition: bootrom.h:791
@ CACHE_OP_EN
Cache enable operation.
Definition: bootrom.h:272
void(* VECTOR_TABLE_Type)(void)
Exception / Interrupt Handler Function Prototype.
Definition: startup_tle989x.h:92
() VECTOR_TABLE_Type NVIC_IRQ17_Handler
Definition: startup_tle989x.h:297
() VECTOR_TABLE_Type NVIC_IRQ30_Handler
Definition: startup_tle989x.h:310
() VECTOR_TABLE_Type NVIC_IRQ27_Handler
Definition: startup_tle989x.h:307
() VECTOR_TABLE_Type SysTick_Handler
Definition: startup_tle989x.h:273
__NO_RETURN void Reset_Handler(void)
Definition: startup_tle989x.h:321
() VECTOR_TABLE_Type NVIC_IRQ4_Handler
Definition: startup_tle989x.h:284
() VECTOR_TABLE_Type NVIC_IRQ5_Handler
Definition: startup_tle989x.h:285
() VECTOR_TABLE_Type UsageFault_Handler
Definition: startup_tle989x.h:264
() VECTOR_TABLE_Type NVIC_IRQ12_Handler
Definition: startup_tle989x.h:292
__attribute__((noreturn)) static void debug_entry(void)
Definition: startup_tle989x.h:221
() VECTOR_TABLE_Type NMI_Handler
Definition: startup_tle989x.h:260
() VECTOR_TABLE_Type NVIC_IRQ0_Handler
Definition: startup_tle989x.h:280
#define CPU_DHCSR_ADDR
() VECTOR_TABLE_Type BusFault_Handler
Definition: startup_tle989x.h:263
() VECTOR_TABLE_Type NVIC_IRQ9_Handler
Definition: startup_tle989x.h:289
() VECTOR_TABLE_Type debug_entry
Definition: startup_tle989x.h:259
() VECTOR_TABLE_Type NVIC_IRQ10_Handler
Definition: startup_tle989x.h:290
() VECTOR_TABLE_Type NVIC_IRQ31_Handler
Definition: startup_tle989x.h:312
() VECTOR_TABLE_Type NVIC_IRQ14_Handler
Definition: startup_tle989x.h:294
() VECTOR_TABLE_Type NVIC_IRQ15_Handler
Definition: startup_tle989x.h:295
() VECTOR_TABLE_Type MemManage_Handler
Definition: startup_tle989x.h:262
() VECTOR_TABLE_Type HardFault_Handler
Definition: startup_tle989x.h:261
() VECTOR_TABLE_Type NVIC_IRQ7_Handler
Definition: startup_tle989x.h:287
const VECTOR_TABLE_Type __VECTOR_TABLE[48]
() VECTOR_TABLE_Type NVIC_IRQ11_Handler
Definition: startup_tle989x.h:291
() VECTOR_TABLE_Type NVIC_IRQ21_Handler
Definition: startup_tle989x.h:301
() VECTOR_TABLE_Type NVIC_IRQ8_Handler
Definition: startup_tle989x.h:288
__NO_RETURN void Default_Handler(void)
Definition: startup_tle989x.h:359
() VECTOR_TABLE_Type PendSV_Handler
Definition: startup_tle989x.h:271
() VECTOR_TABLE_Type NVIC_IRQ20_Handler
Definition: startup_tle989x.h:300
#define SCU_BOOT_CFG_LATCH_TMS_MASK
() VECTOR_TABLE_Type DebugMon_Handler
Definition: startup_tle989x.h:270
() VECTOR_TABLE_Type NVIC_IRQ16_Handler
Definition: startup_tle989x.h:296
() VECTOR_TABLE_Type NVIC_IRQ18_Handler
Definition: startup_tle989x.h:298
() VECTOR_TABLE_Type NVIC_IRQ28_Handler
Definition: startup_tle989x.h:308
() VECTOR_TABLE_Type NVIC_IRQ1_Handler
Definition: startup_tle989x.h:281
#define SCU_BOOT_CFG_LATCH_P00_MASK
#define CPU_DHCSR_C_DEBUGEN_MASK
() VECTOR_TABLE_Type SVC_Handler
Definition: startup_tle989x.h:265
() VECTOR_TABLE_Type NVIC_IRQ19_Handler
Definition: startup_tle989x.h:299
() VECTOR_TABLE_Type NVIC_IRQ2_Handler
Definition: startup_tle989x.h:282
() VECTOR_TABLE_Type NVIC_IRQ24_Handler
Definition: startup_tle989x.h:304
() VECTOR_TABLE_Type NVIC_IRQ3_Handler
Definition: startup_tle989x.h:283
#define SCU_BOOT_CFG_LATCH_ADDR
void alias("Default_Handler")))
uint32_t __STACK_LIMIT
__NO_RETURN void __PROGRAM_START(void)
() VECTOR_TABLE_Type NVIC_IRQ22_Handler
Definition: startup_tle989x.h:302
uint32_t __INITIAL_SP
Definition: startup_tle989x.h:258
() VECTOR_TABLE_Type NVIC_IRQ23_Handler
Definition: startup_tle989x.h:303
() VECTOR_TABLE_Type NVIC_IRQ26_Handler
Definition: startup_tle989x.h:306
() VECTOR_TABLE_Type NVIC_IRQ29_Handler
Definition: startup_tle989x.h:309
() VECTOR_TABLE_Type NVIC_IRQ25_Handler
Definition: startup_tle989x.h:305
() VECTOR_TABLE_Type NVIC_IRQ13_Handler
Definition: startup_tle989x.h:293
void SystemInit(void)
Initialize the system.
Definition: system_tle988x.c:46
Device specific memory layout defines and features.
#define UC_FLASH1_START
Definition: tle_variants.h:338
uint32_t uint32
32 bit unsigned value
Definition: types.h:222