Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
pmu.h
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43 /*******************************************************************************
44 ** Author(s) Identity **
45 ********************************************************************************
46 ** Initials Name **
47 ** ---------------------------------------------------------------------------**
48 ** JO Julia Ott **
49 ** BG Blandine Guillot **
50 ** DM Daniel Mysliwitz **
51 ** PS Patrik Schwarz **
52 *******************************************************************************/
53 
54 /*******************************************************************************
55 ** Revision Control History **
56 ********************************************************************************
57 ** V0.1.0: 2020-06-10, BG: Initial version **
58 ** V0.2.0: 2020-06-10, BG: Added declaration of global function **
59 ** V0.2.1: 2020-09-16, BG: Added interrupt enable/disable functions **
60 ** Added function for GPIO and MON as wake-up src **
61 ** V0.2.2: 2020-09-21, JO: EP-468: Corrected PMU_serviceFailSafeWatchdog() **
62 ** (toggle bit PMU->WD_TRIG.bit.TRIG to service the **
63 ** watchdog) **
64 ** V0.2.3: 2020-09-21, JO: EP-465: Added break commands to switch case **
65 ** statements in setGPIOWakeCfg and setMONWakeCfg **
66 ** V0.2.4: 2020-10-06, BG: EP-492: Removed MISRA 2012 errors **
67 ** V0.2.5: 2020-10-12, BG: EP-515: Added delay and cleared safe-state status**
68 ** for the fail-safe watchdog initialization **
69 ** EP-515: Updated PMU_serviceFailSafeWatchdog() **
70 ** with a safe trigger point calculated in Config **
71 ** Wizard **
72 ** EP-515: Updated functions name related to the **
73 ** fail-safe watchdog **
74 ** V0.2.6: 2020-10-16, JO: EP-523: Updated parameter names **
75 ** V0.2.7: 2020-10-20, BG: EP-534: Configured missing register START_CONFIG **
76 ** in the initialization function **
77 ** V0.2.8: 2020-10-20, JO: EP-515: Removed the enabling of the watchdog **
78 ** Added toggling of PMU->WD_TRIG.bit.TRIG for **
79 ** initial watchdog trigger **
80 ** V0.2.9: 2020-10-21, JO: EP-536: Applied PMU.WD_CTRL.EN setting in **
81 ** function PMU_initFailSafeWatchdog **
82 ** V0.3.0: 2020-11-12, JO: EP-590: Removed \param none and \return none to **
83 ** avoid doxygen warning **
84 ** V0.3.1: 2020-11-17, BG: EP-600: Corrected watchdog initialization **
85 ** V0.3.2: 2020-11-20, BG: EP-610: Corrected MISRA 2012 errors **
86 ** The following rules are globally deactivated: **
87 ** - Info 774: Boolean within 'if' always evaluates **
88 ** to False/True **
89 ** V0.3.3: 2020-12-02, BG: EP-626: Updated wake-up sources functions to **
90 ** consider several wake-up sources at once **
91 ** V0.4.0: 2020-12-04, JO: EP-626: Reworked PMU_enWakeupSrc and **
92 ** PMU_enWakeupSrc, added defines PMU_WAKEUPSRC_* **
93 ** as parameter for the functions (can be combined **
94 ** with bitwise OR) **
95 ** Added functions PMU_enStopModeVDDCReduct **
96 ** and PMU_disStopModeVDDCReduct **
97 ** V0.4.1: 2020-12-10, BG: EP-600: Added a function to clear the fail-safe **
98 ** watchdog fail status **
99 ** V0.4.2: 2020-12-18, BG: EP-652: Corrected name of error code variable **
100 ** V0.4.3: 2021-01-04, BG: EP-661: Renamed u32_maxDelay_ticks variable to **
101 ** u32_maxDelay_ms **
102 ** V0.4.4: 2021-01-20, BG: EP-679: Removed clearing of reset status register**
103 ** in the init function **
104 ** V0.4.5: 2021-02-10, JO: EP-696: Changed from anonymous to named typedefs **
105 ** to prevent MISRA warning **
106 ** V0.4.6: 2021-02-26, BG: EP-701: Updated function to trigger SOW **
107 ** Added SOW bitfield definition before the first **
108 ** watchdog trigger **
109 ** V0.4.7: 2021-03-08, BG: EP-733: Added FIFO pull-up enable in PMU_init **
110 ** after removing it from main function **
111 ** V0.4.8: 2021-03-17, BG: EP-737: Corrected misspelling for **
112 ** PMU_disWakeupSrc **
113 ** V0.4.9: 2021-06-02, BG: EP-813: Removed the clearing of status registers **
114 ** in the initialization function **
115 ** V0.5.0: 2021-06-18, JO: EP-842: Updated PMU_initFailSafeWatchdog for **
116 ** unit test (API call instead of bit access) **
117 ** V0.5.1: 2021-06-29, JO: EP-851: Made u32_failsafeWatchdogCnt volatile **
118 ** V0.5.2: 2021-07-21, BG: EP-870: Removed the range check for GPIO number **
119 ** PMU_setGPIOWakeCfg and for MON number for **
120 ** PMU_setMONWakeCfg so that the default case for **
121 ** switch is not empty **
122 ** V0.5.3: 2021-09-28, BG: EP-929: Updated PMU_init() so that checking for **
123 ** possible hardware failure does not block the **
124 ** initialization with Config Wizard defines **
125 ** V0.5.4: 2021-11-12, JO: EP-937: Updated copyright and branding **
126 ** V0.5.5: 2022-04-25, JO: EP-1139: Corrected definition of variable **
127 ** u32_failsafeWatchdogCnt **
128 ** Corrected doxygen errors/warnings **
129 ** V0.5.6: 2022-06-23, JO: EP-1150: Removed ARMCC V6.18 warnings **
130 ** V0.5.7: 2022-11-17, JO: EP-1342: Updated enum documentation to remove **
131 ** doxygen warning **
132 ** V0.5.8: 2023-03-01, BG: EP-1335: Removed the unnecessary while loop for **
133 ** the fail-safe watchdog initialization **
134 ** Moved the clearance of the WD fail status bit **
135 ** from PMU_serviceFailSafeWatchdog() to **
136 ** PMU_initFailSafeWatchdog() **
137 ** V0.5.9: 2023-04-04, PS: EP-1141: Correct MISRA warnings **
138 ** V0.6.0: 2023-04-26, BG: EP-1428: Removed the functions PMU_enStartCfg() **
139 ** and PMU_disStartCfg since the bitfield CONF in **
140 ** the register START_CONFIG is not available in the**
141 ** SVD file v1.0.0 **
142 *******************************************************************************/
143 
144 #ifndef _PMU_H
145 #define _PMU_H
146 
147 /*******************************************************************************
148 ** Includes **
149 *******************************************************************************/
150 #include "tle_variants.h"
151 #include "types.h"
152 #include "pmu_defines.h"
153 #include "tle989x.h"
154 #include "scu_defines.h"
155 
156 /*******************************************************************************
157 ** Global Macro Declarations **
158 *******************************************************************************/
160 #define PMU_WAKEUPSRC_CAN PMU_WAKE_CTRL_CAN_WAKE_EN_Msk
162 #define PMU_WAKEUPSRC_CYCLICSENSE (2u)
164 #define PMU_WAKEUPSRC_CYCLICWAKE PMU_WAKE_CTRL_CYC_WAKE_EN_Msk
166 #define PMU_WAKEUPSRC_GPIO0 PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk
168 #define PMU_WAKEUPSRC_GPIO1 PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk
170 #define PMU_WAKEUPSRC_GPIO2 PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk
172 #define PMU_WAKEUPSRC_GPIO3 PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk
174 #define PMU_WAKEUPSRC_GPIO4 PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk
176 #define PMU_WAKEUPSRC_GPIO5 PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk
178 #define PMU_WAKEUPSRC_MON1 PMU_WAKE_CTRL_MON0_WAKE_EN_Msk
180 #define PMU_WAKEUPSRC_MON2 PMU_WAKE_CTRL_MON1_WAKE_EN_Msk
182 #define PMU_WAKEUPSRC_MON3 PMU_WAKE_CTRL_MON2_WAKE_EN_Msk
184 #define PMU_WAKEUPSRC_VDDP_UV PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk
186 #define PMU_WAKEUPSRC_VDDP_OV PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk
188 #define PMU_WAKEUPSRC_VDDP_HCM PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk
190 #define PMU_WAKEUPSRC_VDDC_UV PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk
192 #define PMU_WAKEUPSRC_VDDC_OV PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk
194 #define PMU_WAKEUPSRC_VDDC_HCM PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk
196 #define PMU_WAKEUPSRC_VDDEXT_OT PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk
198 #define PMU_WAKEUPSRC_VDDEXT_UV PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk
200 #define PMU_WAKEUPSRC_VSD_OV PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk
202 #define PMU_WAKEUPSRC_ALL_SRC (0x11FF73F7UL)
204 #define PMU_WAKEUPSRC_ALLGPIOS (0x3F0UL)
205 
206 /*******************************************************************************
207 ** Global Type Declarations **
208 *******************************************************************************/
209 
214 typedef enum PMU_gpioInput
215 {
240  PMU_gpioInput_P2_9 = 24u
242 
243 /*******************************************************************************
244 ** Global Function Declarations **
245 *******************************************************************************/
246 
247 sint8 PMU_init(void);
248 void PMU_countFailSafeWatchdog(void);
250 void PMU_stopFailSafeWatchdog(void);
301 INLINE void PMU_clrHPClkFailSts(void);
303 INLINE void PMU_clrSeqWdFailSts(void);
320 INLINE void PMU_clrMstrClkWDRstSts(void);
322 INLINE void PMU_clrSleepExitRstSts(void);
323 INLINE void PMU_clrStopExitRstSts(void);
324 INLINE void PMU_clrPinRstSts(void);
326 INLINE void PMU_clrWDTimerRstSts(void);
327 INLINE void PMU_clrSoftRstSts(void);
328 INLINE void PMU_clrLockupRstSts(void);
332 INLINE sint8 PMU_enWakeupSrc(uint32 u32_wakeupSrc);
333 INLINE sint8 PMU_disWakeupSrc(uint32 u32_wakeupSrc);
337 INLINE sint8 PMU_setGPIOWakeCfg(uint8 u8_GPIO, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, tPMU_gpioInput e_gpioInput);
338 INLINE sint8 PMU_setMONWakeCfg(uint8 u8_MON, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, uint8 u8_enPullupCurrSrc, uint8 u8_enPulldownCurrSrc);
362 INLINE void PMU_clrCANWakeSts(void);
363 INLINE void PMU_clrCyclicWakeSts(void);
364 INLINE void PMU_clrGPIO0WakeSts(void);
365 INLINE void PMU_clrGPIO1WakeSts(void);
366 INLINE void PMU_clrGPIO2WakeSts(void);
367 INLINE void PMU_clrGPIO3WakeSts(void);
368 INLINE void PMU_clrGPIO4WakeSts(void);
369 INLINE void PMU_clrGPIO5WakeSts(void);
370 INLINE void PMU_clrMON1WakeSts(void);
371 INLINE void PMU_clrMON2WakeSts(void);
372 INLINE void PMU_clrMON3WakeSts(void);
382 INLINE void PMU_enFailInputPullUp(void);
383 INLINE void PMU_enResetPin(void);
384 INLINE void PMU_disFailInputPullUp(void);
385 INLINE void PMU_disResetPin(void);
405 INLINE void PMU_clrWDFailSts(void);
415 INLINE void PMU_clrCSCEnFailSts(void);
420 INLINE void PMU_clrSafeShutdownSts(void);
421 INLINE void PMU_clrFailOutputSts(void);
422 
423 /*******************************************************************************
424 ** Deprecated Function Declarations **
425 *******************************************************************************/
426 
430 void PMU_setVDDPUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
431 
435 void PMU_setVDDPOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
436 
440 void PMU_setVDDCUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
441 
445 void PMU_setVDDCOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
446 
450 void PMU_setVDDEXTUndervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
451 
455 void PMU_setVDDEXTOvertemperatureIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime, use the ConfigWizard to configure this feature!")));
456 
457 /*******************************************************************************
458 ** Global Inline Function Definitions **
459 *******************************************************************************/
460 
464 {
465  PMU->VDDP_IRQEN.bit.UVWARN_IEN = 1u;
466 }
467 
471 {
472  PMU->VDDP_IRQEN.bit.OV_IEN = 1u;
473 }
474 
478 {
479  PMU->VDDP_IRQEN.bit.UVWARN_IEN = 0u;
480 }
481 
485 {
486  PMU->VDDP_IRQEN.bit.OV_IEN = 0u;
487 }
488 
494 {
495  return (uint8)PMU->VDDP_STS.bit.UVWARN_IS;
496 }
497 
503 {
504  return (uint8)PMU->VDDP_STS.bit.OV_IS;
505 }
506 
512 {
513  return (uint8)PMU->VDDP_STS.bit.UVWARN_STS;
514 }
515 
521 {
522  return (uint8)PMU->VDDP_STS.bit.ILIM_STS;
523 }
524 
530 {
531  return (uint8)PMU->VDDP_STS.bit.HCM_STS;
532 }
533 
537 {
538  PMU->VDDP_STS_CLR.bit.UVWARN_IS_CLR = 1u;
539 }
540 
544 {
545  PMU->VDDP_STS_CLR.bit.OV_IS_CLR = 1u;
546 }
547 
551 {
552  PMU->VDDP_STS_CLR.bit.UVWARN_STS_CLR = 1u;
553 }
554 
558 {
559  PMU->VDDP_STS_CLR.bit.ILIM_STS_CLR = 1u;
560 }
561 
565 {
566  PMU->VDDP_STS_CLR.bit.HCM_STS_CLR = 1u;
567 }
568 
572 {
573  PMU->VDDC_IRQEN.bit.UVWARN_IEN = 1u;
574 }
575 
579 {
580  PMU->VDDC_IRQEN.bit.OV_IEN = 1u;
581 }
582 
586 {
587  PMU->VDDC_IRQEN.bit.UVWARN_IEN = 0u;
588 }
589 
593 {
594  PMU->VDDC_IRQEN.bit.OV_IEN = 0u;
595 }
596 
602 {
603  return (uint8)PMU->VDDC_STS.bit.UVWARN_IS;
604 }
605 
611 {
612  return (uint8)PMU->VDDC_STS.bit.OV_IS;
613 }
614 
620 {
621  return (uint8)PMU->VDDC_STS.bit.UVWARN_STS;
622 }
623 
629 {
630  return (uint8)PMU->VDDC_STS.bit.HCM_STS;
631 }
632 
636 {
637  PMU->VDDC_STS_CLR.bit.UVWARN_IS_CLR = 1u;
638 }
639 
643 {
644  PMU->VDDC_STS_CLR.bit.OV_IS_CLR = 1u;
645 }
646 
650 {
651  PMU->VDDC_STS_CLR.bit.UVWARN_STS_CLR = 1u;
652 }
653 
657 {
658  PMU->VDDC_STS_CLR.bit.HCM_STS_CLR = 1u;
659 }
660 
664 {
665  PMU->VDDEXT_IRQEN.bit.UV_IEN = 1u;
666 }
667 
671 {
672  PMU->VDDEXT_IRQEN.bit.OT_IEN = 1u;
673 }
674 
678 {
679  PMU->VDDEXT_IRQEN.bit.UV_IEN = 0u;
680 }
681 
685 {
686  PMU->VDDEXT_IRQEN.bit.OT_IEN = 0u;
687 }
688 
694 {
695  return (uint8)PMU->VDDEXT_STS.bit.UV_IS;
696 }
697 
703 {
704  return (uint8)PMU->VDDEXT_STS.bit.OT_IS;
705 }
706 
712 {
713  return (uint8)PMU->VDDEXT_STS.bit.UV_STS;
714 }
715 
721 {
722  return (uint8)PMU->VDDEXT_STS.bit.OT_STS;
723 }
724 
728 {
729  PMU->VDDEXT_STS_CLR.bit.UV_IS_CLR = 1u;
730 }
731 
735 {
736  PMU->VDDEXT_STS_CLR.bit.OT_IS_CLR = 1u;
737 }
738 
742 {
743  PMU->VDDEXT_STS_CLR.bit.UV_STS_CLR = 1u;
744 }
745 
749 {
750  PMU->VDDEXT_STS_CLR.bit.OT_STS_CLR = 1u;
751 }
752 
758 {
759  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDP_TMOUT;
760 }
761 
767 {
768  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDC_TMOUT;
769 }
770 
776 {
777  return (uint8)PMU->WAKE_FAIL_STS.bit.HPCLK_FAIL;
778 }
779 
785 {
786  return (uint8)PMU->WAKE_FAIL_STS.bit.SYS_OT;
787 }
788 
794 {
795  return (uint8)PMU->WAKE_FAIL_STS.bit.FSWD_SEQ_FAIL;
796 }
797 
803 {
804  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDP_OT;
805 }
806 
812 {
813  return (uint8)PMU->WAKE_FAIL_STS.bit.VDDC_OC;
814 }
815 
819 {
820  PMU->WAKE_FAIL_CLR.bit.VDDP_TMOUT_CLR = 1u;
821 }
822 
826 {
827  PMU->WAKE_FAIL_CLR.bit.VDDC_TMOUT_CLR = 1u;
828 }
829 
833 {
834  PMU->WAKE_FAIL_CLR.bit.HPCLK_FAIL_CLR = 1u;
835 }
836 
840 {
841  PMU->WAKE_FAIL_CLR.bit.SYS_OT_CLR = 1u;
842 }
843 
847 {
848  PMU->WAKE_FAIL_CLR.bit.FSWD_SEQ_FAIL_CLR = 1u;
849 }
850 
854 {
855  PMU->WAKE_FAIL_CLR.bit.VDDP_OT_CLR = 1u;
856 }
857 
861 {
862  PMU->WAKE_FAIL_CLR.bit.VDDC_OC_CLR = 1u;
863 }
864 
870 {
871  return (uint8)PMU->RESET_STS.bit.VMSUP_UV_RST;
872 }
873 
879 {
880  return (uint8)PMU->RESET_STS.bit.MCLK_WD_RST;
881 }
882 
888 {
889  return (uint8)PMU->RESET_STS.bit.FS_SLEEPEX_RST;
890 }
891 
897 {
898  return (uint8)PMU->RESET_STS.bit.SLEEPEX_RST;
899 }
900 
906 {
907  return (uint8)PMU->RESET_STS.bit.STOPEX_RST;
908 }
909 
915 {
916  return (uint8)PMU->RESET_STS.bit.PIN_RST;
917 }
918 
924 {
925  return (uint8)PMU->RESET_STS.bit.FSWD_RST;
926 }
927 
933 {
934  return (uint8)PMU->RESET_STS.bit.WDT_MCU_RST;
935 }
936 
942 {
943  return (uint8)PMU->RESET_STS.bit.SOFT_RST;
944 }
945 
951 {
952  return (uint8)PMU->RESET_STS.bit.LOCKUP_RST;
953 }
954 
960 {
961  return (uint8)PMU->RESET_STS.bit.VDDP_UV_RST;
962 }
963 
969 {
970  return (uint8)PMU->RESET_STS.bit.VDDC_UV_RST;
971 }
972 
978 {
979  return (uint8)PMU->RESET_STS.bit.SEC_STACK_RST;
980 }
981 
985 {
986  PMU->RESET_STS_CLR.bit.VMSUP_UV_RST_CLR = 1u;
987 }
988 
992 {
993  PMU->RESET_STS_CLR.bit.MCLK_WD_RST_CLR = 1u;
994 }
995 
999 {
1000  PMU->RESET_STS_CLR.bit.FS_SLEEPEX_RST_CLR = 1u;
1001 }
1002 
1006 {
1007  PMU->RESET_STS_CLR.bit.SLEEPEX_RST_CLR = 1u;
1008 }
1009 
1013 {
1014  PMU->RESET_STS_CLR.bit.STOPEX_RST_CLR = 1u;
1015 }
1016 
1020 {
1021  PMU->RESET_STS_CLR.bit.PIN_RST_CLR = 1u;
1022 }
1023 
1027 {
1028  PMU->RESET_STS_CLR.bit.FSWD_RST_CLR = 1u;
1029 }
1030 
1034 {
1035  PMU->RESET_STS_CLR.bit.WDT_MCU_RST_CLR = 1u;
1036 }
1037 
1041 {
1042  PMU->RESET_STS_CLR.bit.SOFT_RST_CLR = 1u;
1043 }
1044 
1048 {
1049  PMU->RESET_STS_CLR.bit.LOCKUP_RST_CLR = 1u;
1050 }
1051 
1055 {
1056  PMU->RESET_STS_CLR.bit.VDDP_UV_RST_CLR = 1u;
1057 }
1058 
1062 {
1063  PMU->RESET_STS_CLR.bit.VDDC_UV_RST_CLR = 1u;
1064 }
1065 
1069 {
1070  PMU->RESET_STS_CLR.bit.SEC_STACK_RST_CLR = 1u;
1071 }
1072 
1079 {
1080  sint8 s8_returnCode;
1081  uint32 u32_wakeupSrcWithoutCycSense;
1082  s8_returnCode = ERR_LOG_SUCCESS;
1083  /* PMU_WAKEUPSRC_CYCLICSENSE is not part of register PMU->WAKE_CTRL */
1084  u32_wakeupSrcWithoutCycSense = u32_wakeupSrc & (~PMU_WAKEUPSRC_CYCLICSENSE);
1085 
1086  if ((u32_wakeupSrc & (~PMU_WAKEUPSRC_ALL_SRC)) == 0u)
1087  {
1088  PMU->WAKE_CTRL.reg |= u32_wakeupSrcWithoutCycSense;
1089 
1090  /* PMU_WAKEUPSRC_CYCLICSENSE is in register CYC_CTRL */
1091  if ((u32_wakeupSrc & PMU_WAKEUPSRC_CYCLICSENSE) == PMU_WAKEUPSRC_CYCLICSENSE)
1092  {
1093  PMU->CYC_CTRL.bit.CYC_SENSE_EN = 1u;
1094  }
1095  }
1096  else
1097  {
1098  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1099  }
1100 
1101  return s8_returnCode;
1102 }
1103 
1110 {
1111  sint8 s8_returnCode;
1112  uint32 u32_wakeupSrcWithoutCycSense;
1113  s8_returnCode = ERR_LOG_SUCCESS;
1114  /* PMU_WAKEUPSRC_CYCLICSENSE is not part of register PMU->WAKE_CTRL */
1115  u32_wakeupSrcWithoutCycSense = u32_wakeupSrc & ~PMU_WAKEUPSRC_CYCLICSENSE;
1116 
1117  if ((u32_wakeupSrc & (~PMU_WAKEUPSRC_ALL_SRC)) == 0u)
1118  {
1119  PMU->WAKE_CTRL.reg &= (~u32_wakeupSrcWithoutCycSense);
1120 
1121  /* PMU_WAKEUPSRC_CYCLICSENSE is in register CYC_CTRL */
1122  if ((u32_wakeupSrc & PMU_WAKEUPSRC_CYCLICSENSE) == PMU_WAKEUPSRC_CYCLICSENSE)
1123  {
1124  PMU->CYC_CTRL.bit.CYC_SENSE_EN = 0u;
1125  }
1126  }
1127  else
1128  {
1129  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1130  }
1131 
1132  return s8_returnCode;
1133 }
1134 
1140 {
1141  return PMU->WAKE_CTRL.reg;
1142 }
1143 
1147 {
1148  PMU->WAKE_CTRL.bit.VDDC_RED_EN = 1u;
1149 }
1150 
1154 {
1155  PMU->WAKE_CTRL.bit.VDDC_RED_EN = 0u;
1156 }
1157 
1167 INLINE sint8 PMU_setGPIOWakeCfg(uint8 u8_GPIO, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, tPMU_gpioInput e_gpioInput)
1168 {
1169  sint8 s8_returnCode;
1170  s8_returnCode = ERR_LOG_SUCCESS;
1171 
1172  if ((u8_enRisingEdge <= 1) && (u8_enFallingEdge <= 1) && (u8_enCycSen <= 1) && (e_gpioInput <= PMU_gpioInput_P2_9))
1173  {
1174  switch (u8_GPIO)
1175  {
1176  case 0:
1177  {
1178  PMU->WAKE_GPIO_CTRL0.bit.RI = u8_enRisingEdge;
1179  PMU->WAKE_GPIO_CTRL0.bit.FA = u8_enFallingEdge;
1180  PMU->WAKE_GPIO_CTRL0.bit.CYC = u8_enCycSen;
1181  PMU->WAKE_GPIO_CTRL0.bit.INP = (uint8)e_gpioInput;
1182  break;
1183  }
1184 
1185  case 1:
1186  {
1187  PMU->WAKE_GPIO_CTRL1.bit.RI = u8_enRisingEdge;
1188  PMU->WAKE_GPIO_CTRL1.bit.FA = u8_enFallingEdge;
1189  PMU->WAKE_GPIO_CTRL1.bit.CYC = u8_enCycSen;
1190  PMU->WAKE_GPIO_CTRL1.bit.INP = (uint8)e_gpioInput;
1191  break;
1192  }
1193 
1194  case 2:
1195  {
1196  PMU->WAKE_GPIO_CTRL2.bit.RI = u8_enRisingEdge;
1197  PMU->WAKE_GPIO_CTRL2.bit.FA = u8_enFallingEdge;
1198  PMU->WAKE_GPIO_CTRL2.bit.CYC = u8_enCycSen;
1199  PMU->WAKE_GPIO_CTRL2.bit.INP = (uint8)e_gpioInput;
1200  break;
1201  }
1202 
1203  case 3:
1204  {
1205  PMU->WAKE_GPIO_CTRL3.bit.RI = u8_enRisingEdge;
1206  PMU->WAKE_GPIO_CTRL3.bit.FA = u8_enFallingEdge;
1207  PMU->WAKE_GPIO_CTRL3.bit.CYC = u8_enCycSen;
1208  PMU->WAKE_GPIO_CTRL3.bit.INP = (uint8)e_gpioInput;
1209  break;
1210  }
1211 
1212  case 4:
1213  {
1214  PMU->WAKE_GPIO_CTRL4.bit.RI = u8_enRisingEdge;
1215  PMU->WAKE_GPIO_CTRL4.bit.FA = u8_enFallingEdge;
1216  PMU->WAKE_GPIO_CTRL4.bit.CYC = u8_enCycSen;
1217  PMU->WAKE_GPIO_CTRL4.bit.INP = (uint8)e_gpioInput;
1218  break;
1219  }
1220 
1221  case 5:
1222  {
1223  PMU->WAKE_GPIO_CTRL5.bit.RI = u8_enRisingEdge;
1224  PMU->WAKE_GPIO_CTRL5.bit.FA = u8_enFallingEdge;
1225  PMU->WAKE_GPIO_CTRL5.bit.CYC = u8_enCycSen;
1226  PMU->WAKE_GPIO_CTRL5.bit.INP = (uint8)e_gpioInput;
1227  break;
1228  }
1229 
1230  default:
1231  {
1232  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1233  break;
1234  }
1235  }
1236  }
1237  else
1238  {
1239  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1240  }
1241 
1242  return s8_returnCode;
1243 }
1244 
1255 INLINE sint8 PMU_setMONWakeCfg(uint8 u8_MON, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, uint8 u8_enPullupCurrSrc, uint8 u8_enPulldownCurrSrc)
1256 {
1257  sint8 s8_returnCode;
1258  s8_returnCode = ERR_LOG_SUCCESS;
1259 
1260  if ((u8_enRisingEdge <= 1) && (u8_enFallingEdge <= 1) && (u8_enCycSen <= 1) && (u8_enPullupCurrSrc <= 1) && (u8_enPulldownCurrSrc <= 1))
1261  {
1262  switch (u8_MON)
1263  {
1264  case 1:
1265  {
1266  PMU->MON_CTRL1.bit.WAKE_RISE = u8_enRisingEdge;
1267  PMU->MON_CTRL1.bit.WAKE_FALL = u8_enFallingEdge;
1268  PMU->MON_CTRL1.bit.CYC_SENSE_EN = u8_enCycSen;
1269  PMU->MON_CTRL1.bit.PU = u8_enPullupCurrSrc;
1270  PMU->MON_CTRL1.bit.PD = u8_enPulldownCurrSrc;
1271  break;
1272  }
1273 
1274  case 2:
1275  {
1276  PMU->MON_CTRL2.bit.WAKE_RISE = u8_enRisingEdge;
1277  PMU->MON_CTRL2.bit.WAKE_FALL = u8_enFallingEdge;
1278  PMU->MON_CTRL2.bit.CYC_SENSE_EN = u8_enCycSen;
1279  PMU->MON_CTRL2.bit.PU = u8_enPullupCurrSrc;
1280  PMU->MON_CTRL2.bit.PD = u8_enPulldownCurrSrc;
1281  break;
1282  }
1283 
1284  case 3:
1285  {
1286  PMU->MON_CTRL3.bit.WAKE_RISE = u8_enRisingEdge;
1287  PMU->MON_CTRL3.bit.WAKE_FALL = u8_enFallingEdge;
1288  PMU->MON_CTRL3.bit.CYC_SENSE_EN = u8_enCycSen;
1289  PMU->MON_CTRL3.bit.PU = u8_enPullupCurrSrc;
1290  PMU->MON_CTRL3.bit.PD = u8_enPulldownCurrSrc;
1291  break;
1292  }
1293 
1294  default:
1295  {
1296  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1297  break;
1298  }
1299  }
1300  }
1301  else
1302  {
1303  s8_returnCode = ERR_LOG_CODE_PARAM_OUT_OF_RANGE;
1304  }
1305 
1306  return s8_returnCode;
1307 }
1308 
1314 {
1315  return (uint8)PMU->MON_STS.bit.MON1_STS;
1316 }
1317 
1323 {
1324  return (uint8)PMU->MON_STS.bit.MON2_STS;
1325 }
1326 
1332 {
1333  return (uint8)PMU->MON_STS.bit.MON3_STS;
1334 }
1335 
1341 {
1342  return (uint8)PMU->WAKE_STS.bit.CAN;
1343 }
1344 
1350 {
1351  return (uint8)PMU->WAKE_STS.bit.CYC_WAKE;
1352 }
1353 
1359 {
1360  return (uint8)PMU->WAKE_STS.bit.GPIO0;
1361 }
1362 
1368 {
1369  return (uint8)PMU->WAKE_STS.bit.GPIO1;
1370 }
1371 
1377 {
1378  return (uint8)PMU->WAKE_STS.bit.GPIO2;
1379 }
1380 
1386 {
1387  return (uint8)PMU->WAKE_STS.bit.GPIO3;
1388 }
1389 
1395 {
1396  return (uint8)PMU->WAKE_STS.bit.GPIO4;
1397 }
1398 
1404 {
1405  return (uint8)PMU->WAKE_STS.bit.GPIO5;
1406 }
1407 
1413 {
1414  return (uint8)PMU->WAKE_STS.bit.MON1;
1415 }
1416 
1422 {
1423  return (uint8)PMU->WAKE_STS.bit.MON2;
1424 }
1425 
1431 {
1432  return (uint8)PMU->WAKE_STS.bit.MON3;
1433 }
1434 
1440 {
1441  return (uint8)PMU->WAKE_STS.bit.VDDP_UVWARN;
1442 }
1443 
1449 {
1450  return (uint8)PMU->WAKE_STS.bit.VDDP_OV;
1451 }
1452 
1458 {
1459  return (uint8)PMU->WAKE_STS.bit.VDDP_HCM;
1460 }
1461 
1467 {
1468  return (uint8)PMU->WAKE_STS.bit.VDDC_UVWARN;
1469 }
1470 
1476 {
1477  return (uint8)PMU->WAKE_STS.bit.VDDC_OV;
1478 }
1479 
1485 {
1486  return (uint8)PMU->WAKE_STS.bit.VDDC_HCM;
1487 }
1488 
1494 {
1495  return (uint8)PMU->WAKE_STS.bit.VDDEXT_OT;
1496 }
1497 
1503 {
1504  return (uint8)PMU->WAKE_STS.bit.VDDEXT_UV;
1505 }
1506 
1512 {
1513  return (uint8)PMU->WAKE_STS.bit.VSD_OV;
1514 }
1515 
1519 {
1520  PMU->WAKE_STS_CLR.bit.CAN_CLR = 1u;
1521 }
1522 
1526 {
1527  PMU->WAKE_STS_CLR.bit.CYC_WAKE_CLR = 1u;
1528 }
1529 
1533 {
1534  PMU->WAKE_STS_CLR.bit.GPIO0_CLR = 1u;
1535 }
1536 
1540 {
1541  PMU->WAKE_STS_CLR.bit.GPIO1_CLR = 1u;
1542 }
1543 
1547 {
1548  PMU->WAKE_STS_CLR.bit.GPIO2_CLR = 1u;
1549 }
1550 
1554 {
1555  PMU->WAKE_STS_CLR.bit.GPIO3_CLR = 1u;
1556 }
1557 
1561 {
1562  PMU->WAKE_STS_CLR.bit.GPIO4_CLR = 1u;
1563 }
1564 
1568 {
1569  PMU->WAKE_STS_CLR.bit.GPIO5_CLR = 1u;
1570 }
1571 
1575 {
1576  PMU->WAKE_STS_CLR.bit.MON1_CLR = 1u;
1577 }
1578 
1582 {
1583  PMU->WAKE_STS_CLR.bit.MON2_CLR = 1u;
1584 }
1585 
1589 {
1590  PMU->WAKE_STS_CLR.bit.MON3_CLR = 1u;
1591 }
1592 
1596 {
1597  PMU->WAKE_STS_CLR.bit.VDDP_UVWARN_CLR = 1u;
1598 }
1599 
1603 {
1604  PMU->WAKE_STS_CLR.bit.VDDP_OV_CLR = 1u;
1605 }
1606 
1610 {
1611  PMU->WAKE_STS_CLR.bit.VDDP_HCM_CLR = 1u;
1612 }
1613 
1617 {
1618  PMU->WAKE_STS_CLR.bit.VDDC_UVWARN_CLR = 1u;
1619 }
1620 
1624 {
1625  PMU->WAKE_STS_CLR.bit.VDDC_OV_CLR = 1u;
1626 }
1627 
1631 {
1632  PMU->WAKE_STS_CLR.bit.VDDC_HCM_CLR = 1u;
1633 }
1634 
1638 {
1639  PMU->WAKE_STS_CLR.bit.VDDEXT_OT_CLR = 1u;
1640 }
1641 
1645 {
1646  PMU->WAKE_STS_CLR.bit.VDDEXT_UV_CLR = 1u;
1647 }
1648 
1652 {
1653  PMU->WAKE_STS_CLR.bit.VSD_OV_CLR = 1u;
1654 }
1655 
1659 {
1660  PMU->MISC_CTRL.bit.FI_PU_EN = 1u;
1661 }
1662 
1666 {
1667  PMU->START_CONFIG.bit.RST_PIN_EN = 1u;
1668 }
1669 
1673 {
1674  PMU->MISC_CTRL.bit.FI_PU_EN = 0u;
1675 }
1676 
1680 {
1681  PMU->START_CONFIG.bit.RST_PIN_EN = 0u;
1682 }
1683 
1689 {
1690  return (uint8)PMU->FS_STS.bit.MCLK_FAIL_STS;
1691 }
1692 
1698 {
1699  return (uint8)PMU->FS_STS.bit.VMSUP_UV_STS;
1700 }
1701 
1707 {
1708  return (uint8)PMU->FS_STS.bit.VMSUP_OV_STS;
1709 }
1710 
1716 {
1717  return (uint8)PMU->FS_STS.bit.WD_FAIL_STS;
1718 }
1719 
1725 {
1726  return (uint8)PMU->FS_STS.bit.WD_TEST_FAIL_STS;
1727 }
1728 
1734 {
1735  return (uint8)PMU->FS_STS.bit.VDDC_UV_STS;
1736 }
1737 
1743 {
1744  return (uint8)PMU->FS_STS.bit.VDDC_OV_STS;
1745 }
1746 
1752 {
1753  return (uint8)PMU->FS_STS.bit.VDDP_UV_STS;
1754 }
1755 
1761 {
1762  return (uint8)PMU->FS_STS.bit.VDDP_OV_STS;
1763 }
1764 
1770 {
1771  return (uint8)PMU->FS_STS.bit.VDDP_OT_STS;
1772 }
1773 
1779 {
1780  return (uint8)PMU->FS_STS.bit.VAREF_OV_STS;
1781 }
1782 
1788 {
1789  return (uint8)PMU->FS_STS.bit.CSC_OC_STS;
1790 }
1791 
1797 {
1798  return (uint8)PMU->FS_STS.bit.CSC_BIST_FAIL_STS;
1799 }
1800 
1806 {
1807  return (uint8)PMU->FS_STS.bit.CSC_EN_FAIL_STS;
1808 }
1809 
1815 {
1816  return (uint8)PMU->FS_STS.bit.PIN_MON_STS;
1817 }
1818 
1824 {
1825  return (uint8)PMU->FS_STS.bit.FO_OC_STS;
1826 }
1827 
1831 {
1832  PMU->FS_STS_CLR.bit.MCLK_FAIL_STS_CLR = 1u;
1833 }
1834 
1838 {
1839  PMU->FS_STS_CLR.bit.VMSUP_UV_STS_CLR = 1u;
1840 }
1841 
1845 {
1846  PMU->FS_STS_CLR.bit.VMSUP_OV_STS_CLR = 1u;
1847 }
1848 
1852 {
1853  PMU->FS_STS_CLR.bit.WD_FAIL_STS_CLR = 1u;
1854 }
1855 
1859 {
1860  PMU->FS_STS_CLR.bit.WD_TEST_FAIL_STS_CLR = 1u;
1861 }
1862 
1866 {
1867  PMU->FS_STS_CLR.bit.VDDC_UV_STS_CLR = 1u;
1868 }
1869 
1873 {
1874  PMU->FS_STS_CLR.bit.VDDC_OV_STS_CLR = 1u;
1875 }
1876 
1880 {
1881  PMU->FS_STS_CLR.bit.VDDP_UV_STS_CLR = 1u;
1882 }
1883 
1887 {
1888  PMU->FS_STS_CLR.bit.VDDP_OV_STS_CLR = 1u;
1889 }
1890 
1894 {
1895  PMU->FS_STS_CLR.bit.VDDP_OT_STS_CLR = 1u;
1896 }
1897 
1901 {
1902  PMU->FS_STS_CLR.bit.VAREF_OV_STS_CLR = 1u;
1903 }
1904 
1908 {
1909  PMU->FS_STS_CLR.bit.CSC_OC_STS_CLR = 1u;
1910 }
1911 
1915 {
1916  PMU->FS_STS_CLR.bit.CSC_BIST_FAIL_STS_CLR = 1u;
1917 }
1918 
1922 {
1923  PMU->FS_STS_CLR.bit.CSC_EN_FAIL_STS_CLR = 1u;
1924 }
1925 
1929 {
1930  PMU->FS_STS_CLR.bit.PIN_MON_STS_CLR = 1u;
1931 }
1932 
1936 {
1937  PMU->FS_STS_CLR.bit.FO_OC_STS_CLR = 1u;
1938 }
1939 
1945 {
1946  return (uint8)PMU->FS_SSD.bit.SSD_STS;
1947 }
1948 
1954 {
1955  return (uint8)PMU->FS_SSD.bit.FO_STS;
1956 }
1957 
1961 {
1962  PMU->FS_SSD_CLR.bit.SSD_STS_CLR = 1u;
1963 }
1964 
1968 {
1969  PMU->FS_SSD_CLR.bit.FO_STS_CLR = 1u;
1970 }
1971 
1974 #endif /* _PMU_H */
1975 
#define ERR_LOG_SUCCESS
Definition: error_codes.h:69
#define PMU
Definition: internal/tle989x.h:25612
INLINE void PMU_disFailInputPullUp(void)
Disable the failure input pull up.
Definition: pmu.h:1672
INLINE void PMU_clrMON1WakeSts(void)
Clear MON1 wake-up status.
Definition: pmu.h:1574
INLINE uint8 PMU_getHPClkFailSts(void)
Get HP clock fail status.
Definition: pmu.h:775
INLINE sint8 PMU_enWakeupSrc(uint32 u32_wakeupSrc)
Enable a wake-up source.
Definition: pmu.h:1078
INLINE uint8 PMU_getSecureStackOverflowRstSts(void)
Get secure stack overflow reset status.
Definition: pmu.h:977
INLINE void PMU_clrVDDEXTUndervoltageIntSts(void)
Clear VDDEXT undervoltage interrupt status.
Definition: pmu.h:727
INLINE uint8 PMU_getCSCSelfTestFailSts(void)
Get CSC self-test fail status.
Definition: pmu.h:1796
void PMU_setVDDPOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDP Overvoltage Interrupt Node Pointer.
INLINE void PMU_clrWDTimerRstSts(void)
Clear MCU watchdog timer reset status.
Definition: pmu.h:1033
#define PMU_WAKEUPSRC_ALL_SRC
PMU Wake-up source all sources.
Definition: pmu.h:202
INLINE void PMU_enVDDCUndervoltageWarnInt(void)
Enable VDDC undervoltage warning interrupt.
Definition: pmu.h:571
INLINE uint8 PMU_getVDDPUndervoltageWarnSts(void)
Get VDDP undervoltage warning status.
Definition: pmu.h:511
INLINE void PMU_clrVDDPUndervoltageWarnWakeSts(void)
Clear VDDP undervoltage warning wake-up status.
Definition: pmu.h:1595
INLINE uint8 PMU_getMON2WakeSts(void)
Get MON2 wake-up status.
Definition: pmu.h:1421
INLINE void PMU_clrVDDCUndervoltageWarnWakeSts(void)
Clear VDDC undervoltage warning wake-up status.
Definition: pmu.h:1616
INLINE uint8 PMU_getGPIO2WakeSts(void)
Get GPIO2 wake-up status.
Definition: pmu.h:1376
INLINE void PMU_clrVDDCUndervoltageWarnSts(void)
Clear VDDC undervoltage warning status.
Definition: pmu.h:649
INLINE uint8 PMU_getGPIO5WakeSts(void)
Get GPIO5 wake-up status.
Definition: pmu.h:1403
INLINE uint8 PMU_getVDDPOvervoltageSts(void)
Get VDDP overvoltage status.
Definition: pmu.h:1760
INLINE uint8 PMU_getCANWakeSts(void)
Get CAN wake-up status.
Definition: pmu.h:1340
INLINE uint8 PMU_getMON3InputSts(void)
Get MON3 input status.
Definition: pmu.h:1331
#define PMU_WAKEUPSRC_CYCLICSENSE
PMU Wake-up source cyclic sense.
Definition: pmu.h:162
INLINE void PMU_clrSeqWdFailSts(void)
Clear sequential watchdog fail status.
Definition: pmu.h:846
INLINE uint8 PMU_getMstrSupplyUndervoltageSts(void)
Get master supply undervoltage status.
Definition: pmu.h:1697
INLINE uint8 PMU_getVDDPOvertemperatureSts(void)
Get VDDP overtemperature status.
Definition: pmu.h:1769
INLINE sint8 PMU_setMONWakeCfg(uint8 u8_MON, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, uint8 u8_enPullupCurrSrc, uint8 u8_enPulldownCurrSrc)
Set a MON wake configuration.
Definition: pmu.h:1255
INLINE void PMU_clrFailOutputSts(void)
Clear fail output status.
Definition: pmu.h:1967
INLINE void PMU_clrVSDOvervoltageWakeSts(void)
Clear VSD overvoltage wake-up status.
Definition: pmu.h:1651
INLINE void PMU_clrCSCOvercurrentSts(void)
Clear CSC overcurrent status.
Definition: pmu.h:1907
INLINE void PMU_clrGPIO5WakeSts(void)
Clear GPIO5 wake-up status.
Definition: pmu.h:1567
INLINE void PMU_enVDDEXTUndervoltageInt(void)
Enable VDDEXT undervoltage interrupt.
Definition: pmu.h:663
INLINE uint8 PMU_getWDSelfTestFailSts(void)
Get watchdog self-test fail status.
Definition: pmu.h:1724
INLINE uint8 PMU_getCyclicWakeSts(void)
Get cyclic wake-up status.
Definition: pmu.h:1349
INLINE void PMU_clrVDDPHighCurrentModeSts(void)
Clear VDDP high current mode status.
Definition: pmu.h:564
void PMU_stopFailSafeWatchdog(void)
Stop the fail-safe watchdog.
Definition: pmu.c:157
INLINE void PMU_clrVDDPCurrentLimitSts(void)
Clear VDDP current limitation status.
Definition: pmu.h:557
INLINE uint8 PMU_getVDDCUndervoltageRstSts(void)
Get VDDC undervoltage reset status.
Definition: pmu.h:968
INLINE void PMU_clrVDDCUndervoltageSts(void)
Clear VDDC undervoltage status.
Definition: pmu.h:1865
INLINE uint8 PMU_getSoftRstSts(void)
Get soft reset status.
Definition: pmu.h:941
INLINE void PMU_clrVDDCUndervoltageWarnIntSts(void)
Clear VDDC undervoltage warning interrupt status.
Definition: pmu.h:635
INLINE uint8 PMU_getMstrSupplyOvervoltageSts(void)
Get master supply overvoltage status.
Definition: pmu.h:1706
INLINE void PMU_clrVDDPUndervoltageWarnIntSts(void)
Clear VDDP undervoltage warning interrupt status.
Definition: pmu.h:536
INLINE void PMU_enVDDPOvervoltageInt(void)
Enable VDDP overvoltage interrupt.
Definition: pmu.h:470
INLINE void PMU_clrVDDPOvertemperatureSts(void)
Clear VDDP overtemperature status.
Definition: pmu.h:1893
INLINE void PMU_clrVDDCHighCurrentModeWakeSts(void)
Clear VDDC high current mode wake-up status.
Definition: pmu.h:1630
void PMU_clrFailSafeWatchdogFailSts(void)
Clear the fail-safe watchdog fail status.
Definition: pmu.c:205
INLINE void PMU_clrWDFailSts(void)
Clear watchdog fail status.
Definition: pmu.h:1851
INLINE uint8 PMU_getSleepExitRstSts(void)
Get sleep mode exit reset status.
Definition: pmu.h:896
INLINE uint8 PMU_getVDDPHighCurrentModeWakeSts(void)
Get VDDP high current mode wake-up status.
Definition: pmu.h:1457
INLINE void PMU_disVDDPOvervoltageInt(void)
Disable VDDP overvoltage interrupt.
Definition: pmu.h:484
INLINE uint8 PMU_getMON2InputSts(void)
Get MON2 input status.
Definition: pmu.h:1322
INLINE void PMU_clrVDDPHighCurrentModeWakeSts(void)
Clear VDDP high current mode wake-up status.
Definition: pmu.h:1609
INLINE void PMU_enVDDCOvervoltageInt(void)
Enable VDDC overvoltage interrupt.
Definition: pmu.h:578
INLINE void PMU_clrGPIO4WakeSts(void)
Clear GPIO4 wake-up status.
Definition: pmu.h:1560
INLINE uint8 PMU_getVDDCOvervoltageIntSts(void)
Get VDDC overvoltage interrupt status.
Definition: pmu.h:610
INLINE void PMU_clrFailSafeWDRstSts(void)
Clear fail safe watchdog reset status.
Definition: pmu.h:1026
INLINE uint8 PMU_getVDDCUndervoltageWarnWakeSts(void)
Get VDDC undervoltage warning wake-up status.
Definition: pmu.h:1466
INLINE uint8 PMU_getFOOvercurrentSts(void)
Get FO overcurrent status.
Definition: pmu.h:1823
INLINE uint8 PMU_getWDFailSts(void)
Get watchdog fail status.
Definition: pmu.h:1715
INLINE uint8 PMU_getVDDCOvervoltageWakeSts(void)
Get VDDC overvoltage wake-up status.
Definition: pmu.h:1475
INLINE uint8 PMU_getVDDCOvervoltageSts(void)
Get VDDC overvoltage status.
Definition: pmu.h:1742
INLINE void PMU_clrMON3WakeSts(void)
Clear MON3 wake-up status.
Definition: pmu.h:1588
INLINE uint8 PMU_getVDDEXTUndervoltageWakeSts(void)
Get VDDEXT undervoltage wake-up status.
Definition: pmu.h:1502
INLINE uint8 PMU_getGPIO0WakeSts(void)
Get GPIO0 wake-up status.
Definition: pmu.h:1358
INLINE uint8 PMU_getVDDEXTUndervoltageSts(void)
Get VDDEXT undervoltage status.
Definition: pmu.h:711
sint8 PMU_serviceFailSafeWatchdog(void)
Service the fail-safe watchdog.
Definition: pmu.c:167
INLINE void PMU_clrMstrSupplyUndervoltageSts(void)
Clear master supply undervoltage status.
Definition: pmu.h:1837
INLINE void PMU_clrSafeShutdownSts(void)
Clear safe shutdown status.
Definition: pmu.h:1960
INLINE uint8 PMU_getMstrClkWDFailSts(void)
Get master clock watchdog fail status.
Definition: pmu.h:1688
INLINE uint8 PMU_getVDDEXTOvertemperatureSts(void)
Get VDDEXT overtemperature status.
Definition: pmu.h:720
INLINE void PMU_clrVDDEXTOvertemperatureIntSts(void)
Clear VDDEXT overtemperature interrupt status.
Definition: pmu.h:734
INLINE uint8 PMU_getVDDCHighCurrentModeWakeSts(void)
Get VDDC high current mode wake-up status.
Definition: pmu.h:1484
INLINE uint8 PMU_getVDDPHighCurrentModeSts(void)
Get VDDP high current mode status.
Definition: pmu.h:529
INLINE uint8 PMU_getPinRstSts(void)
Get pin reset status.
Definition: pmu.h:914
INLINE sint8 PMU_setGPIOWakeCfg(uint8 u8_GPIO, uint8 u8_enRisingEdge, uint8 u8_enFallingEdge, uint8 u8_enCycSen, tPMU_gpioInput e_gpioInput)
Set a GPIO wake configuration.
Definition: pmu.h:1167
INLINE void PMU_clrMstrSupplyUndervoltageRstSts(void)
Clear master supply undervoltage reset status.
Definition: pmu.h:984
INLINE void PMU_disVDDEXTUndervoltageInt(void)
Disable VDDEXT undervoltage interrupt.
Definition: pmu.h:677
INLINE void PMU_clrHPClkFailSts(void)
Clear HP clock fail status.
Definition: pmu.h:832
INLINE uint8 PMU_getFailSafeWDRstSts(void)
Get fail safe watchdog reset status.
Definition: pmu.h:923
INLINE void PMU_disResetPin(void)
Disable the Reset Pin.
Definition: pmu.h:1679
INLINE uint8 PMU_getWDTimerRstSts(void)
Get MCU watchdog timer reset status.
Definition: pmu.h:932
INLINE void PMU_clrStopExitRstSts(void)
Clear stop mode exit reset status.
Definition: pmu.h:1012
INLINE void PMU_clrWDSelfTestFailSts(void)
Clear watchdog self-test fail status.
Definition: pmu.h:1858
INLINE uint8 PMU_getVDDEXTUndervoltageIntSts(void)
Get VDDEXT undervoltage interrupt status.
Definition: pmu.h:693
INLINE uint8 PMU_getVDDCOvercurrentSts(void)
Get VDDC overcurrent status.
Definition: pmu.h:811
INLINE void PMU_clrVAREFOvervoltageSts(void)
Clear VAREF overvoltage status.
Definition: pmu.h:1900
INLINE uint8 PMU_getSafeShutdownSts(void)
Get safe shutdown status.
Definition: pmu.h:1944
INLINE void PMU_clrCANWakeSts(void)
Clear CAN wake-up status.
Definition: pmu.h:1518
INLINE void PMU_clrFOOvercurrentSts(void)
Clear FO overcurrent status.
Definition: pmu.h:1935
INLINE uint8 PMU_getMON3WakeSts(void)
Get MON3 wake-up status.
Definition: pmu.h:1430
void PMU_setVDDCUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDC Undervoltage Warning Interrupt Node Pointer.
INLINE void PMU_disVDDCOvervoltageInt(void)
Disable VDDC overvoltage interrupt.
Definition: pmu.h:592
INLINE void PMU_clrVDDEXTUndervoltageWakeSts(void)
Clear VDDEXT undervoltage wake-up status.
Definition: pmu.h:1644
INLINE void PMU_clrVDDEXTUndervoltageSts(void)
Clear VDDEXT undervoltage status.
Definition: pmu.h:741
INLINE void PMU_disStopModeVDDCReduct(void)
Disable VDDC reduction in Stop Mode.
Definition: pmu.h:1153
INLINE void PMU_clrVDDPOvervoltageSts(void)
Clear VDDP overvoltage status.
Definition: pmu.h:1886
INLINE void PMU_clrSysOvertemperatureSts(void)
Clear system overtemperature status.
Definition: pmu.h:839
INLINE void PMU_clrPinRstSts(void)
Clear pin reset status.
Definition: pmu.h:1019
INLINE void PMU_clrVDDCUndervoltageRstSts(void)
Clear VDDC undervoltage reset status.
Definition: pmu.h:1061
INLINE uint8 PMU_getFailOutputSts(void)
Get fail output status.
Definition: pmu.h:1953
INLINE sint8 PMU_disWakeupSrc(uint32 u32_wakeupSrc)
Disable a wake-up source.
Definition: pmu.h:1109
INLINE void PMU_clrVDDCRegulatorTimeoutSts(void)
Clear VDDC regulator timeout status.
Definition: pmu.h:825
INLINE void PMU_clrGPIO3WakeSts(void)
Clear GPIO3 wake-up status.
Definition: pmu.h:1553
INLINE void PMU_clrCSCSelfTestFailSts(void)
Clear CSC self-test fail status.
Definition: pmu.h:1914
INLINE void PMU_clrLockupRstSts(void)
Clear ARM core lockup reset status.
Definition: pmu.h:1047
INLINE void PMU_clrVDDPRegulatorOvertemperatureSts(void)
Clear VDDP regulator overtemperature status.
Definition: pmu.h:853
sint8 PMU_initFailSafeWatchdog(void)
Initialize the fail-safe watchdog.
Definition: pmu.c:123
INLINE uint8 PMU_getVDDPUndervoltageWarnIntSts(void)
Get VDDP undervoltage warning interrupt status.
Definition: pmu.h:493
INLINE void PMU_disVDDEXTOvertemperatureInt(void)
Disable VDDEXT overtemperature interrupt.
Definition: pmu.h:684
INLINE void PMU_clrGPIO0WakeSts(void)
Clear GPIO0 wake-up status.
Definition: pmu.h:1532
INLINE uint8 PMU_getVDDPRegulatorOvertemperatureSts(void)
Get VDDP regulator overtemperature status.
Definition: pmu.h:802
INLINE void PMU_clrVDDCHighCurrentModeSts(void)
Clear VDDC high current mode status.
Definition: pmu.h:656
INLINE uint8 PMU_getVSDOvervoltageWakeSts(void)
Get VSD overvoltage wake-up status.
Definition: pmu.h:1511
INLINE void PMU_disVDDPUndervoltageWarnInt(void)
Disable VDDP undervoltage warning interrupt.
Definition: pmu.h:477
void PMU_setVDDPUndervoltageWarnIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDP Undervoltage Warning Interrupt Node Pointer.
sint8 PMU_serviceFailSafeWatchdogSOW(void)
Service a Short Open Window for the watchdog.
Definition: pmu.c:220
INLINE uint8 PMU_getVDDCRegulatorTimeoutSts(void)
Get VDDC regulator timeout status.
Definition: pmu.h:766
INLINE void PMU_clrSleepExitRstSts(void)
Clear sleep mode exit reset status.
Definition: pmu.h:1005
INLINE void PMU_clrVDDEXTOvertemperatureSts(void)
Clear VDDEXT overtemperature status.
Definition: pmu.h:748
sint8 PMU_init(void)
Initialize all CW registers of the PMU module.
Definition: pmu.c:67
PMU_gpioInput
This enum lists the gpio input pointer.
Definition: pmu.h:215
INLINE uint8 PMU_getMON1WakeSts(void)
Get MON1 wake-up status.
Definition: pmu.h:1412
INLINE void PMU_clrCSCEnFailSts(void)
Clear CSC enabling fail status.
Definition: pmu.h:1921
INLINE void PMU_enVDDPUndervoltageWarnInt(void)
Enable VDDP undervoltage warning interrupt.
Definition: pmu.h:463
INLINE uint8 PMU_getVDDPCurrentLimitSts(void)
Get VDDP current limitation status.
Definition: pmu.h:520
INLINE uint8 PMU_getVDDCUndervoltageWarnIntSts(void)
Get VDDC undervoltage warning interrupt status.
Definition: pmu.h:601
INLINE uint8 PMU_getVDDEXTOvertemperatureWakeSts(void)
Get VDDEXT overtemperature wake-up status.
Definition: pmu.h:1493
INLINE uint8 PMU_getPinMonitorFailSts(void)
Get pin monitor fail status.
Definition: pmu.h:1814
INLINE uint8 PMU_getVDDEXTOvertemperatureIntSts(void)
Get VDDEXT overtemperature interrupt status.
Definition: pmu.h:702
INLINE uint8 PMU_getVDDPUndervoltageRstSts(void)
Get VDDP undervoltage reset status.
Definition: pmu.h:959
INLINE void PMU_clrVDDCOvervoltageIntSts(void)
Clear VDDC overvoltage interrupt status.
Definition: pmu.h:642
INLINE void PMU_clrSoftRstSts(void)
Clear soft reset status.
Definition: pmu.h:1040
INLINE void PMU_clrVDDPOvervoltageIntSts(void)
Clear VDDP overvoltage interrupt status.
Definition: pmu.h:543
INLINE void PMU_clrMstrClkWDRstSts(void)
Clear master clock watchdog reset status.
Definition: pmu.h:991
INLINE uint8 PMU_getMON1InputSts(void)
Get MON1 input status.
Definition: pmu.h:1313
INLINE void PMU_clrVDDPUndervoltageWarnSts(void)
Clear VDDP undervoltage warning status.
Definition: pmu.h:550
INLINE uint8 PMU_getVDDCUndervoltageSts(void)
Get VDDC undervoltage status.
Definition: pmu.h:1733
INLINE uint8 PMU_getVDDPOvervoltageWakeSts(void)
Get VDDP overvoltage wake-up status.
Definition: pmu.h:1448
INLINE void PMU_clrVDDPRegulatorTimeoutSts(void)
Clear VDDP regulator timeout status.
Definition: pmu.h:818
INLINE void PMU_clrVDDPUndervoltageSts(void)
Clear VDDP undervoltage status.
Definition: pmu.h:1879
INLINE uint8 PMU_getLockupRstSts(void)
Get ARM core lockup reset status.
Definition: pmu.h:950
INLINE uint8 PMU_getCSCOvercurrentSts(void)
Get CSC overcurrent status.
Definition: pmu.h:1787
INLINE uint8 PMU_getGPIO4WakeSts(void)
Get GPIO4 wake-up status.
Definition: pmu.h:1394
INLINE uint8 PMU_getVDDCUndervoltageWarnSts(void)
Get VDDC undervoltage warning status.
Definition: pmu.h:619
INLINE void PMU_clrVDDCOvercurrentSts(void)
Clear VDDC overcurrent status.
Definition: pmu.h:860
INLINE void PMU_enFailInputPullUp(void)
Enable the failure input pull up.
Definition: pmu.h:1658
INLINE void PMU_clrSecureStackOverflowRstSts(void)
Clear secure stack overflow reset status.
Definition: pmu.h:1068
INLINE void PMU_clrVDDPOvervoltageWakeSts(void)
Clear VDDP overvoltage wake-up status.
Definition: pmu.h:1602
INLINE void PMU_clrMON2WakeSts(void)
Clear MON2 wake-up status.
Definition: pmu.h:1581
INLINE void PMU_clrGPIO1WakeSts(void)
Clear GPIO1 wake-up status.
Definition: pmu.h:1539
INLINE uint32 PMU_getWakeupSrc(void)
Get a wake-up source.
Definition: pmu.h:1139
INLINE void PMU_clrVDDEXTOvertemperatureWakeSts(void)
Clear VDDEXT overtemperature wake-up status.
Definition: pmu.h:1637
INLINE uint8 PMU_getMstrClkWDRstSts(void)
Get master clock watchdog reset status.
Definition: pmu.h:878
INLINE void PMU_clrMstrClkWDFailSts(void)
Clear master clock watchdog fail status.
Definition: pmu.h:1830
INLINE void PMU_clrPinMonitorFailSts(void)
Clear pin monitor fail status.
Definition: pmu.h:1928
INLINE uint8 PMU_getVDDCHighCurrentModeSts(void)
Get VDDC high current mode status.
Definition: pmu.h:628
INLINE void PMU_clrMstrSupplyOvervoltageSts(void)
Clear master supply overvoltage status.
Definition: pmu.h:1844
void PMU_countFailSafeWatchdog(void)
Count up since the last watchdog trigger.
Definition: pmu.c:114
void PMU_setVDDEXTOvertemperatureIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDEXT Overtemperature Interrupt Node Pointer.
enum PMU_gpioInput tPMU_gpioInput
INLINE void PMU_clrGPIO2WakeSts(void)
Clear GPIO2 wake-up status.
Definition: pmu.h:1546
INLINE uint8 PMU_getVAREFOvervoltageSts(void)
Get VAREF overvoltage status.
Definition: pmu.h:1778
INLINE void PMU_clrVDDCOvervoltageWakeSts(void)
Clear VDDC overvoltage wake-up status.
Definition: pmu.h:1623
INLINE uint8 PMU_getCSCEnFailSts(void)
Get CSC enabling fail status.
Definition: pmu.h:1805
INLINE uint8 PMU_getVDDPOvervoltageIntSts(void)
Get VDDP overvoltage interrupt status.
Definition: pmu.h:502
INLINE uint8 PMU_getVDDPUndervoltageWarnWakeSts(void)
Get VDDP undervoltage warning wake-up status.
Definition: pmu.h:1439
INLINE void PMU_clrCyclicWakeSts(void)
Clear cyclic wake-up status.
Definition: pmu.h:1525
INLINE void PMU_clrVDDCOvervoltageSts(void)
Clear VDDC overvoltage status.
Definition: pmu.h:1872
INLINE uint8 PMU_getMstrSupplyUndervoltageRstSts(void)
Get master supply undervoltage reset status.
Definition: pmu.h:869
void PMU_setVDDCOvervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDC Overvoltage Interrupt Node Pointer.
INLINE uint8 PMU_getSysOvertemperatureSts(void)
Get system overtemperature status.
Definition: pmu.h:784
INLINE void PMU_clrVDDPUndervoltageRstSts(void)
Clear VDDP undervoltage reset status.
Definition: pmu.h:1054
INLINE uint8 PMU_getGPIO1WakeSts(void)
Get GPIO1 wake-up status.
Definition: pmu.h:1367
INLINE uint8 PMU_getVDDPRegulatorTimeoutSts(void)
Get VDDP regulator timeout status.
Definition: pmu.h:757
INLINE void PMU_clrFailSleepExitRstSts(void)
Clear fail sleep mode exit reset status.
Definition: pmu.h:998
INLINE void PMU_disVDDCUndervoltageWarnInt(void)
Disable VDDC undervoltage warning interrupt.
Definition: pmu.h:585
INLINE void PMU_enResetPin(void)
Enable the Reset pin.
Definition: pmu.h:1665
INLINE uint8 PMU_getVDDPUndervoltageSts(void)
Get VDDP undervoltage status.
Definition: pmu.h:1751
INLINE void PMU_enVDDEXTOvertemperatureInt(void)
Enable VDDEXT overtemperature interrupt.
Definition: pmu.h:670
INLINE uint8 PMU_getStopExitRstSts(void)
Get stop mode exit reset status.
Definition: pmu.h:905
INLINE void PMU_enStopModeVDDCReduct(void)
Enable VDDC reduction in Stop Mode.
Definition: pmu.h:1146
INLINE uint8 PMU_getSeqWdFailSts(void)
Get sequential watchdog fail status.
Definition: pmu.h:793
INLINE uint8 PMU_getFailSleepExitRstSts(void)
Get fail sleep mode exit reset status.
Definition: pmu.h:887
INLINE uint8 PMU_getGPIO3WakeSts(void)
Get GPIO3 wake-up status.
Definition: pmu.h:1385
void PMU_setVDDEXTUndervoltageIntNodePtr(void) __attribute__((deprecated("Do not change this at runtime
Set VDDEXT Undervoltage Interrupt Node Pointer.
@ PMU_gpioInput_P0_0
Definition: pmu.h:216
@ PMU_gpioInput_P2_0
Definition: pmu.h:231
@ PMU_gpioInput_P2_3
Definition: pmu.h:234
@ PMU_gpioInput_P0_1
Definition: pmu.h:217
@ PMU_gpioInput_P1_2
Definition: pmu.h:228
@ PMU_gpioInput_P1_1
Definition: pmu.h:227
@ PMU_gpioInput_P1_3
Definition: pmu.h:229
@ PMU_gpioInput_P0_8
Definition: pmu.h:224
@ PMU_gpioInput_P0_2
Definition: pmu.h:218
@ PMU_gpioInput_P2_9
Definition: pmu.h:240
@ PMU_gpioInput_P0_3
Definition: pmu.h:219
@ PMU_gpioInput_P2_2
Definition: pmu.h:233
@ PMU_gpioInput_P2_7
Definition: pmu.h:238
@ PMU_gpioInput_P0_4
Definition: pmu.h:220
@ PMU_gpioInput_P2_8
Definition: pmu.h:239
@ PMU_gpioInput_P0_5
Definition: pmu.h:221
@ PMU_gpioInput_P0_6
Definition: pmu.h:222
@ PMU_gpioInput_P2_4
Definition: pmu.h:235
@ PMU_gpioInput_P2_6
Definition: pmu.h:237
@ PMU_gpioInput_P1_0
Definition: pmu.h:226
@ PMU_gpioInput_P2_5
Definition: pmu.h:236
@ PMU_gpioInput_P2_1
Definition: pmu.h:232
@ PMU_gpioInput_P0_7
Definition: pmu.h:223
@ PMU_gpioInput_P1_4
Definition: pmu.h:230
@ PMU_gpioInput_P0_9
Definition: pmu.h:225
__attribute__((noreturn))
Definition: startup_tle989x.c:221
Device specific memory layout defines and features.
General type declarations.
#define ERR_LOG_CODE_PARAM_OUT_OF_RANGE
Parameter out of range.
Definition: types.h:213
#define INLINE
Definition: types.h:167
uint8_t uint8
8 bit unsigned value
Definition: types.h:220
int8_t sint8
8 bit signed value
Definition: types.h:225
uint32_t uint32
32 bit unsigned value
Definition: types.h:222