![]() |
Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
|
SCU (SCU)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SELSYS0: 2 | |
__IOM uint32_t SELSYS1: 2 | |
uint32_t __pad0__: 12 | |
__IOM uint32_t SELCLKOUT: 3 | |
__IOM uint32_t CLKOUTEN: 1 | |
uint32_t __pad1__: 12 | |
} bit | |
} | CLKSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PRECPU: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t PREFILT: 5 | |
__IOM uint32_t PREMI: 3 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t PRECAN: 3 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t PREUART: 3 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t PRECLKOUT: 3 | |
__IOM uint32_t DIV2CLKOUT: 1 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CLKCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t UARTCLKEN: 1 | |
__IOM uint32_t CANCLKEN: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | CLKEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t FINE: 5 | |
__IOM uint32_t COARSE: 5 | |
__IOM uint32_t RREF: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t DYEN: 1 | |
__IOM uint32_t OFFSET0: 4 | |
__IOM uint32_t OFFSET1: 4 | |
__IOM uint32_t OFFSET2: 4 | |
__IOM uint32_t OFFSET3: 4 | |
} bit | |
} | HPCLKTRIM |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t HPWDGEN: 1 | |
__IOM uint32_t HPWDGRST: 1 | |
uint32_t __pad1__: 22 | |
} bit | |
} | SYSCLKTEST |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t XPD: 1 | |
__IOM uint32_t XTALHYSEN: 1 | |
__IOM uint32_t XTALSHBYEN: 1 | |
__IOM uint32_t XTALSHDIS: 1 | |
__IOM uint32_t XTALHYS: 2 | |
uint32_t __pad0__: 18 | |
__IOM uint32_t XWDGEN: 1 | |
uint32_t __pad1__: 3 | |
__OM uint32_t XWDGRES: 1 | |
uint32_t __pad2__: 3 | |
} bit | |
} | XTALCON |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t XTAL_FAIL_STS: 1 | |
uint32_t __pad0__: 7 | |
__IM uint32_t XTALFAIL: 1 | |
uint32_t __pad1__: 23 | |
} bit | |
} | XTALSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t XTAL_FAIL_STSCLR: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | XTALSTATC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t XTAL_FAIL_STSSET: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | XTALSTATS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_PMU: 1 | |
__IOM uint32_t INP_BDRV_IRQ0: 1 | |
__IOM uint32_t INP_BDRV_IRQ1: 1 | |
__IOM uint32_t INP_CANTX: 1 | |
__IOM uint32_t INP_ARVG: 1 | |
__IOM uint32_t INP_CSC: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | INP0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_GPT1T2: 1 | |
__IOM uint32_t INP_GPT1T3: 1 | |
__IOM uint32_t INP_GPT1T4: 1 | |
__IOM uint32_t INP_GPT2T5: 1 | |
__IOM uint32_t INP_GPT2T6: 1 | |
__IOM uint32_t INP_GPT2CR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | INP1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_MON1: 1 | |
__IOM uint32_t INP_MON2: 1 | |
__IOM uint32_t INP_MON3: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | INP2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_SDADC0: 1 | |
__IOM uint32_t INP_SDADC1: 1 | |
__IOM uint32_t INP_BEMF0: 1 | |
__IOM uint32_t INP_BEMF1: 1 | |
__IOM uint32_t INP_BEMF2: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | INP3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_EXINT0: 1 | |
__IOM uint32_t INP_EXINT1: 1 | |
__IOM uint32_t INP_EXINT2: 1 | |
__IOM uint32_t INP_EXINT3: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | INP4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_LIN0_EOFSYN: 1 | |
__IOM uint32_t INP_LIN0_ERRSYN: 1 | |
__IOM uint32_t INP_LIN1_EOFSYN: 1 | |
__IOM uint32_t INP_LIN1_ERRSYN: 1 | |
__IOM uint32_t INP_UART0_RI: 1 | |
__IOM uint32_t INP_UART0_TI: 1 | |
__IOM uint32_t INP_UART1_RI: 1 | |
__IOM uint32_t INP_UART1_TI: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | INP5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_SSC0_RIR: 1 | |
__IOM uint32_t INP_SSC0_TIR: 1 | |
__IOM uint32_t INP_SSC0_EIR: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t INP_SSC1_RIR: 1 | |
__IOM uint32_t INP_SSC1_TIR: 1 | |
__IOM uint32_t INP_SSC1_EIR: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | INP6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_DMACH0: 1 | |
__IOM uint32_t INP_DMACH1: 1 | |
__IOM uint32_t INP_DMACH2: 1 | |
__IOM uint32_t INP_DMACH3: 1 | |
__IOM uint32_t INP_DMACH4: 1 | |
__IOM uint32_t INP_DMACH5: 1 | |
__IOM uint32_t INP_DMACH6: 1 | |
__IOM uint32_t INP_DMACH7: 1 | |
__IOM uint32_t INP_DMATRERR: 1 | |
uint32_t __pad0__: 23 | |
} bit | |
} | INP7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t NMIXTALEN: 1 | |
__IOM uint32_t NMIPLL0EN: 1 | |
__IOM uint32_t NMIPLL1EN: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMICON |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t NMIXTAL: 1 | |
__IM uint32_t NMIPLL0: 1 | |
__IM uint32_t NMIPLL1: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMISR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t NMIXTALCLR: 1 | |
__OM uint32_t NMIPLL0CLR: 1 | |
__OM uint32_t NMIPLL1CLR: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMISRC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t NMIXTALSET: 1 | |
__OM uint32_t NMIPLL0SET: 1 | |
__OM uint32_t NMIPLL1SET: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMISRS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MON1EN: 1 | |
__IOM uint32_t MON2EN: 1 | |
__IOM uint32_t MON3EN: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | MONIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MON1R: 1 | |
__IM uint32_t MON1F: 1 | |
__IM uint32_t MON2R: 1 | |
__IM uint32_t MON2F: 1 | |
__IM uint32_t MON3R: 1 | |
__IM uint32_t MON3F: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MON1RCLR: 1 | |
__OM uint32_t MON1FCLR: 1 | |
__OM uint32_t MON2RCLR: 1 | |
__OM uint32_t MON2FCLR: 1 | |
__OM uint32_t MON3RCLR: 1 | |
__OM uint32_t MON3FCLR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MON1RSET: 1 | |
__OM uint32_t MON1FSET: 1 | |
__OM uint32_t MON2RSET: 1 | |
__OM uint32_t MON2FSET: 1 | |
__OM uint32_t MON3RSET: 1 | |
__OM uint32_t MON3FSET: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MON1IEV: 2 | |
__IOM uint32_t MON2IEV: 2 | |
__IOM uint32_t MON3IEV: 2 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EXTINT0EN: 1 | |
__IOM uint32_t EXTINT1EN: 1 | |
__IOM uint32_t EXTINT2EN: 1 | |
__IOM uint32_t EXTINT3EN: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | EXTIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t EXTINT0R: 1 | |
__IM uint32_t EXTINT0F: 1 | |
__IM uint32_t EXTINT1R: 1 | |
__IM uint32_t EXTINT1F: 1 | |
__IM uint32_t EXTINT2R: 1 | |
__IM uint32_t EXTINT2F: 1 | |
__IM uint32_t EXTINT3R: 1 | |
__IM uint32_t EXTINT3F: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | EXTIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t EXTINT0RCLR: 1 | |
__OM uint32_t EXTINT0FCLR: 1 | |
__OM uint32_t EXTINT1RCLR: 1 | |
__OM uint32_t EXTINT1FCLR: 1 | |
__OM uint32_t EXTINT2RCLR: 1 | |
__OM uint32_t EXTINT2FCLR: 1 | |
__OM uint32_t EXTINT3RCLR: 1 | |
__OM uint32_t EXTINT3FCLR: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | EXTISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t EXTINT0RSET: 1 | |
__OM uint32_t EXTINT0FSET: 1 | |
__OM uint32_t EXTINT1RSET: 1 | |
__OM uint32_t EXTINT1FSET: 1 | |
__OM uint32_t EXTINT2RSET: 1 | |
__OM uint32_t EXTINT2FSET: 1 | |
__OM uint32_t EXTINT3RSET: 1 | |
__OM uint32_t EXTINT3FSET: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | EXTISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EXTINT0IEV: 2 | |
__IOM uint32_t EXTINT1IEV: 2 | |
__IOM uint32_t EXTINT2IEV: 2 | |
__IOM uint32_t EXTINT3IEV: 2 | |
__IOM uint32_t EXTINT0INSEL: 2 | |
__IOM uint32_t EXTINT1INSEL: 2 | |
__IOM uint32_t EXTINT2INSEL: 2 | |
__IOM uint32_t EXTINT3INSEL: 2 | |
uint32_t __pad0__: 16 | |
} bit | |
} | EXTCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t GPT1T2EN: 1 | |
__IOM uint32_t GPT1T3EN: 1 | |
__IOM uint32_t GPT1T4EN: 1 | |
__IOM uint32_t GPT2T5EN: 1 | |
__IOM uint32_t GPT2T6EN: 1 | |
__IOM uint32_t GPT2CREN: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t GPT1T2: 1 | |
__IM uint32_t GPT1T3: 1 | |
__IM uint32_t GPT1T4: 1 | |
__IM uint32_t GPT2T5: 1 | |
__IM uint32_t GPT2T6: 1 | |
__IM uint32_t GPT2CR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t GPT1T2CLR: 1 | |
__OM uint32_t GPT1T3CLR: 1 | |
__OM uint32_t GPT1T4CLR: 1 | |
__OM uint32_t GPT2T5CLR: 1 | |
__OM uint32_t GPT2T6CLR: 1 | |
__OM uint32_t GPT2CRCLR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t GPT1T2SET: 1 | |
__OM uint32_t GPT1T3SET: 1 | |
__OM uint32_t GPT1T4SET: 1 | |
__OM uint32_t GPT2T5SET: 1 | |
__OM uint32_t GPT2T6SET: 1 | |
__OM uint32_t GPT2CRSET: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DMACH0EN: 1 | |
__IOM uint32_t DMACH1EN: 1 | |
__IOM uint32_t DMACH2EN: 1 | |
__IOM uint32_t DMACH3EN: 1 | |
__IOM uint32_t DMACH4EN: 1 | |
__IOM uint32_t DMACH5EN: 1 | |
__IOM uint32_t DMACH6EN: 1 | |
__IOM uint32_t DMACH7EN: 1 | |
__IOM uint32_t DMATRERREN: 1 | |
uint32_t __pad0__: 23 | |
} bit | |
} | DMAIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t DMACH0: 1 | |
__IM uint32_t DMACH1: 1 | |
__IM uint32_t DMACH2: 1 | |
__IM uint32_t DMACH3: 1 | |
__IM uint32_t DMACH4: 1 | |
__IM uint32_t DMACH5: 1 | |
__IM uint32_t DMACH6: 1 | |
__IM uint32_t DMACH7: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMAIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t DMACH0CLR: 1 | |
__OM uint32_t DMACH1CLR: 1 | |
__OM uint32_t DMACH2CLR: 1 | |
__OM uint32_t DMACH3CLR: 1 | |
__OM uint32_t DMACH4CLR: 1 | |
__OM uint32_t DMACH5CLR: 1 | |
__OM uint32_t DMACH6CLR: 1 | |
__OM uint32_t DMACH7CLR: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMAISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t DMACH0SET: 1 | |
__OM uint32_t DMACH1SET: 1 | |
__OM uint32_t DMACH2SET: 1 | |
__OM uint32_t DMACH3SET: 1 | |
__OM uint32_t DMACH4SET: 1 | |
__OM uint32_t DMACH5SET: 1 | |
__OM uint32_t DMACH6SET: 1 | |
__OM uint32_t DMACH7SET: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMAISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12CM70: 2 | |
__IOM uint32_t T12CM71: 2 | |
__IOM uint32_t T12CM72: 2 | |
__IOM uint32_t T12PM: 2 | |
__IOM uint32_t T12ZM: 2 | |
__IOM uint32_t T13CM: 2 | |
__IOM uint32_t T13PM: 2 | |
__IOM uint32_t T13ZM: 2 | |
__IOM uint32_t T14CM: 2 | |
__IOM uint32_t T14PM: 2 | |
__IOM uint32_t T15CM: 2 | |
__IOM uint32_t T15PM: 2 | |
__IOM uint32_t T16CM: 2 | |
__IOM uint32_t T16PM: 2 | |
__IOM uint32_t CHE: 2 | |
uint32_t __pad0__: 2 | |
} bit | |
} | DMAP_CCU7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ADC1_RES0: 2 | |
__IOM uint32_t ADC1_RES1: 2 | |
__IOM uint32_t ADC1_RES2: 2 | |
__IOM uint32_t ADC1_RES3: 2 | |
__IOM uint32_t ADC1_RES4: 2 | |
__IOM uint32_t ADC1_RES5: 2 | |
__IOM uint32_t ADC1_RES6: 2 | |
__IOM uint32_t ADC1_RES7: 2 | |
__IOM uint32_t ADC1_SQ0: 2 | |
__IOM uint32_t ADC1_SQ1: 2 | |
__IOM uint32_t ADC1_CMPLO: 2 | |
__IOM uint32_t ADC1_CMPHI: 2 | |
__IOM uint32_t SDADC_RES0: 2 | |
__IOM uint32_t SDADC_RES1: 2 | |
uint32_t __pad0__: 4 | |
} bit | |
} | DMAP_ADC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T2OV: 1 | |
__IOM uint32_t T21OV: 1 | |
uint32_t __pad0__: 6 | |
__IOM uint32_t GPT12T2: 1 | |
__IOM uint32_t GPT12T3: 1 | |
__IOM uint32_t GPT12T4: 1 | |
__IOM uint32_t GPT12T5: 1 | |
__IOM uint32_t GPT12T6: 1 | |
__IOM uint32_t GPT12CR: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | DMAP_TIM |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SSC0_RIR: 2 | |
__IOM uint32_t SSC0_TIR: 2 | |
__IOM uint32_t SSC1_RIR: 2 | |
__IOM uint32_t SSC1_TIR: 2 | |
__IOM uint32_t UART0_RI: 2 | |
__IOM uint32_t UART0_TI: 2 | |
__IOM uint32_t UART1_RI: 2 | |
__IOM uint32_t UART1_TI: 2 | |
__IOM uint32_t CAN_IR0: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CAN_IR1: 1 | |
uint32_t __pad1__: 13 | |
} bit | |
} | DMAP_COM |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t XTAL_ON: 1 | |
__OM uint32_t SLEEP: 1 | |
__OM uint32_t STOP: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | PMCON0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SSC0_DIS: 1 | |
__IOM uint32_t SSC1_DIS: 1 | |
__IOM uint32_t T2_DIS: 1 | |
__IOM uint32_t T21_DIS: 1 | |
__IOM uint32_t GPT12_DIS: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PMCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SSC0SUS: 1 | |
__IOM uint32_t SSC1SUS: 1 | |
__IOM uint32_t T2SUS: 1 | |
__IOM uint32_t T21SUS: 1 | |
__IOM uint32_t GPT12SUS: 1 | |
__IOM uint32_t WDTSUS: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | SUSCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t OT_SLEEP_EN: 1 | |
uint32_t __pad0__: 7 | |
__IOM uint32_t VDDP_OV_SD_DIS: 1 | |
__IOM uint32_t VDDP_UV_SD_DIS: 1 | |
__IOM uint32_t VDDC_OV_SD_DIS: 1 | |
__IOM uint32_t VDDC_UV_SD_DIS: 1 | |
__IOM uint32_t VS_OV_SD_DIS: 1 | |
__IOM uint32_t VS_UV_SD_DIS: 1 | |
__IOM uint32_t OTWARN_SD_DIS: 1 | |
__IOM uint32_t XTALWDG_SD_DIS: 1 | |
uint32_t __pad1__: 8 | |
__IOM uint32_t BDRV_SD_EN: 1 | |
__IOM uint32_t CANTX_SD_EN: 1 | |
uint32_t __pad2__: 6 | |
} bit | |
} | PCU_CTRL |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t TMS: 1 | |
__IM uint32_t P00: 1 | |
__IM uint32_t P01: 1 | |
__IM uint32_t P02: 1 | |
__IM uint32_t P22: 1 | |
__IM uint32_t P23: 1 | |
__IM uint32_t JSTAT: 1 | |
uint32_t __pad0__: 25 | |
} bit | |
} | BOOT_CFG_LATCH |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTB0_out: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t DTB1_out: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t DTB2_out: 2 | |
__IOM uint32_t DTB3_out: 1 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t DTB4_out: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t SDADC_MOD_VDIG_I_dtb: 2 | |
__IOM uint32_t DOOR_FREQ_BIST_dtb: 2 | |
__IOM uint32_t TESTCK_SEL: 2 | |
__IOM uint32_t TESTCK_EN: 1 | |
__IOM uint32_t SWD_EN: 2 | |
__IOM uint32_t JTAG_EN: 1 | |
uint32_t __pad4__: 3 | |
__IM uint32_t FTM_EN: 1 | |
__IM uint32_t FTM: 4 | |
uint32_t __pad5__: 3 | |
__IOM uint32_t TST_CTRL: 1 | |
} bit | |
} | TCR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TM_PASSWD: 12 | |
uint32_t __pad0__: 20 | |
} bit | |
} | TMPWD |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t FREQ_BIST: 1 | |
__IOM uint32_t BIST_WINDOW_SEL: 4 | |
__IOM uint32_t BIST_EXT_CLK: 1 | |
__IM uint32_t BIST_WINDOW_DONE: 1 | |
uint32_t __pad0__: 9 | |
__IM uint32_t FREQ: 16 | |
} bit | |
} | FREQ_BIST1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t GP_TRC_IN_REG: 32 | |
} bit | |
} | GP_TRC_IN_REG |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t GP_TRC_OUT_REG: 32 | |
} bit | |
} | GP_TRC_OUT_REG |
union { | |
__IM uint32_t reg | |
struct { | |
uint32_t __pad0__: 21 | |
__IM uint32_t HARR: 1 | |
__IM uint32_t GLOB_TM: 1 | |
uint32_t __pad1__: 9 | |
} bit | |
} | TEST_STS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TMODE_R: 1 | |
__IOM uint32_t UMODE_R: 1 | |
__IOM uint32_t XPROT_R: 1 | |
__IOM uint32_t SFR_PROT1ST: 1 | |
__IOM uint32_t SFR_PROT2ND: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | SSTCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CAN_FD_EN: 1 | |
__IOM uint32_t B4: 1 | |
__IOM uint32_t SDADC_EN: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SEC_MODE: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t RAM_ID: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t VARIANT_ID: 4 | |
uint32_t __pad3__: 16 | |
} bit | |
} | PKGCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DEMEN_CH0: 1 | |
__IOM uint32_t DEMEN_CH1: 1 | |
__IOM uint32_t DEMEN_CH2: 1 | |
__IOM uint32_t DEMEN_CH3: 1 | |
__IOM uint32_t DEMEN_CH4: 1 | |
__IOM uint32_t DEMEN_CH5: 1 | |
__IOM uint32_t DEMEN_CH6: 1 | |
__IOM uint32_t DEMEN_CH7: 1 | |
__IOM uint32_t DMAREQINTEN_CH0: 1 | |
__IOM uint32_t DMAREQINTEN_CH1: 1 | |
__IOM uint32_t DMAREQINTEN_CH2: 1 | |
__IOM uint32_t DMAREQINTEN_CH3: 1 | |
__IOM uint32_t DMAREQINTEN_CH4: 1 | |
__IOM uint32_t DMAREQINTEN_CH5: 1 | |
__IOM uint32_t DMAREQINTEN_CH6: 1 | |
__IOM uint32_t DMAREQINTEN_CH7: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | DMACTRL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t NMIDISMOD: 1 | |
__IOM uint32_t NMICNTEN: 1 | |
__IOM uint32_t NMIDIS: 1 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t NMICNTVAL: 6 | |
uint32_t __pad1__: 18 | |
} bit | |
} | NMIDISCFG |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOCKUP_EN: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | LOCKUPCFG |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SELSYS0: 2 | |
__IOM uint32_t SELSYS1: 2 | |
uint32_t __pad0__: 12 | |
__IOM uint32_t SELCLKOUT: 3 | |
__IOM uint32_t CLKOUTEN: 1 | |
uint32_t __pad1__: 12 | |
} bit | |
} | CLKSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PRECPU: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t PREFILT: 5 | |
__IOM uint32_t PREMI: 3 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t PRECAN: 3 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t PREUART: 3 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t PRECLKOUT: 3 | |
__IOM uint32_t DIV2CLKOUT: 1 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CLKCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t UARTCLKEN: 1 | |
__IOM uint32_t CANCLKEN: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | CLKEN |
__IM uint32_t | RESERVED [2] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t XPD: 1 | |
__IOM uint32_t XTALHYSEN: 1 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t XTALHYS: 2 | |
uint32_t __pad1__: 18 | |
__IOM uint32_t XWDGEN: 1 | |
uint32_t __pad2__: 3 | |
__OM uint32_t XWDGRES: 1 | |
uint32_t __pad3__: 3 | |
} bit | |
} | XTALCON |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t XTAL_FAIL_STS: 1 | |
uint32_t __pad0__: 7 | |
__IM uint32_t XTALFAIL: 1 | |
uint32_t __pad1__: 23 | |
} bit | |
} | XTALSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t XTAL_FAIL_STSCLR: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | XTALSTATC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t XTAL_FAIL_STSSET: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | XTALSTATS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_PMU: 1 | |
__IOM uint32_t INP_BDRV_IRQ0: 1 | |
__IOM uint32_t INP_BDRV_IRQ1: 1 | |
__IOM uint32_t INP_CANTX: 1 | |
__IOM uint32_t INP_ARVG: 1 | |
__IOM uint32_t INP_CSC: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | INP0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_GPT1T2: 1 | |
__IOM uint32_t INP_GPT1T3: 1 | |
__IOM uint32_t INP_GPT1T4: 1 | |
__IOM uint32_t INP_GPT2T5: 1 | |
__IOM uint32_t INP_GPT2T6: 1 | |
__IOM uint32_t INP_GPT2CR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | INP1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_MON1: 1 | |
__IOM uint32_t INP_MON2: 1 | |
__IOM uint32_t INP_MON3: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | INP2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_SDADC0: 1 | |
__IOM uint32_t INP_SDADC1: 1 | |
__IOM uint32_t INP_BEMF0: 1 | |
__IOM uint32_t INP_BEMF1: 1 | |
__IOM uint32_t INP_BEMF2: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | INP3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_EXINT0: 1 | |
__IOM uint32_t INP_EXINT1: 1 | |
__IOM uint32_t INP_EXINT2: 1 | |
__IOM uint32_t INP_EXINT3: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | INP4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_LIN0_EOFSYN: 1 | |
__IOM uint32_t INP_LIN0_ERRSYN: 1 | |
__IOM uint32_t INP_LIN1_EOFSYN: 1 | |
__IOM uint32_t INP_LIN1_ERRSYN: 1 | |
__IOM uint32_t INP_UART0_RI: 1 | |
__IOM uint32_t INP_UART0_TI: 1 | |
__IOM uint32_t INP_UART1_RI: 1 | |
__IOM uint32_t INP_UART1_TI: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | INP5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_SSC0_RIR: 1 | |
__IOM uint32_t INP_SSC0_TIR: 1 | |
__IOM uint32_t INP_SSC0_EIR: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t INP_SSC1_RIR: 1 | |
__IOM uint32_t INP_SSC1_TIR: 1 | |
__IOM uint32_t INP_SSC1_EIR: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | INP6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_DMACH0: 1 | |
__IOM uint32_t INP_DMACH1: 1 | |
__IOM uint32_t INP_DMACH2: 1 | |
__IOM uint32_t INP_DMACH3: 1 | |
__IOM uint32_t INP_DMACH4: 1 | |
__IOM uint32_t INP_DMACH5: 1 | |
__IOM uint32_t INP_DMACH6: 1 | |
__IOM uint32_t INP_DMACH7: 1 | |
__IOM uint32_t INP_DMATRERR: 1 | |
uint32_t __pad0__: 23 | |
} bit | |
} | INP7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t NMIXTALEN: 1 | |
__IOM uint32_t NMIPLL0EN: 1 | |
__IOM uint32_t NMIPLL1EN: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMICON |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t NMIXTAL: 1 | |
__IM uint32_t NMIPLL0: 1 | |
__IM uint32_t NMIPLL1: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMISR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t NMIXTALCLR: 1 | |
__OM uint32_t NMIPLL0CLR: 1 | |
__OM uint32_t NMIPLL1CLR: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMISRC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t NMIXTALSET: 1 | |
__OM uint32_t NMIPLL0SET: 1 | |
__OM uint32_t NMIPLL1SET: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | NMISRS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MON1EN: 1 | |
__IOM uint32_t MON2EN: 1 | |
__IOM uint32_t MON3EN: 1 | |
uint32_t __pad0__: 29 | |
} bit | |
} | MONIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MON1R: 1 | |
__IM uint32_t MON1F: 1 | |
__IM uint32_t MON2R: 1 | |
__IM uint32_t MON2F: 1 | |
__IM uint32_t MON3R: 1 | |
__IM uint32_t MON3F: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MON1RCLR: 1 | |
__OM uint32_t MON1FCLR: 1 | |
__OM uint32_t MON2RCLR: 1 | |
__OM uint32_t MON2FCLR: 1 | |
__OM uint32_t MON3RCLR: 1 | |
__OM uint32_t MON3FCLR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MON1RSET: 1 | |
__OM uint32_t MON1FSET: 1 | |
__OM uint32_t MON2RSET: 1 | |
__OM uint32_t MON2FSET: 1 | |
__OM uint32_t MON3RSET: 1 | |
__OM uint32_t MON3FSET: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MON1IEV: 2 | |
__IOM uint32_t MON2IEV: 2 | |
__IOM uint32_t MON3IEV: 2 | |
uint32_t __pad0__: 26 | |
} bit | |
} | MONCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EXTINT0EN: 1 | |
__IOM uint32_t EXTINT1EN: 1 | |
__IOM uint32_t EXTINT2EN: 1 | |
__IOM uint32_t EXTINT3EN: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | EXTIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t EXTINT0R: 1 | |
__IM uint32_t EXTINT0F: 1 | |
__IM uint32_t EXTINT1R: 1 | |
__IM uint32_t EXTINT1F: 1 | |
__IM uint32_t EXTINT2R: 1 | |
__IM uint32_t EXTINT2F: 1 | |
__IM uint32_t EXTINT3R: 1 | |
__IM uint32_t EXTINT3F: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | EXTIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t EXTINT0RCLR: 1 | |
__OM uint32_t EXTINT0FCLR: 1 | |
__OM uint32_t EXTINT1RCLR: 1 | |
__OM uint32_t EXTINT1FCLR: 1 | |
__OM uint32_t EXTINT2RCLR: 1 | |
__OM uint32_t EXTINT2FCLR: 1 | |
__OM uint32_t EXTINT3RCLR: 1 | |
__OM uint32_t EXTINT3FCLR: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | EXTISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t EXTINT0RSET: 1 | |
__OM uint32_t EXTINT0FSET: 1 | |
__OM uint32_t EXTINT1RSET: 1 | |
__OM uint32_t EXTINT1FSET: 1 | |
__OM uint32_t EXTINT2RSET: 1 | |
__OM uint32_t EXTINT2FSET: 1 | |
__OM uint32_t EXTINT3RSET: 1 | |
__OM uint32_t EXTINT3FSET: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | EXTISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EXTINT0IEV: 2 | |
__IOM uint32_t EXTINT1IEV: 2 | |
__IOM uint32_t EXTINT2IEV: 2 | |
__IOM uint32_t EXTINT3IEV: 2 | |
__IOM uint32_t EXTINT0INSEL: 2 | |
__IOM uint32_t EXTINT1INSEL: 2 | |
__IOM uint32_t EXTINT2INSEL: 2 | |
__IOM uint32_t EXTINT3INSEL: 2 | |
uint32_t __pad0__: 16 | |
} bit | |
} | EXTCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t GPT1T2EN: 1 | |
__IOM uint32_t GPT1T3EN: 1 | |
__IOM uint32_t GPT1T4EN: 1 | |
__IOM uint32_t GPT2T5EN: 1 | |
__IOM uint32_t GPT2T6EN: 1 | |
__IOM uint32_t GPT2CREN: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t GPT1T2: 1 | |
__IM uint32_t GPT1T3: 1 | |
__IM uint32_t GPT1T4: 1 | |
__IM uint32_t GPT2T5: 1 | |
__IM uint32_t GPT2T6: 1 | |
__IM uint32_t GPT2CR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t GPT1T2CLR: 1 | |
__OM uint32_t GPT1T3CLR: 1 | |
__OM uint32_t GPT1T4CLR: 1 | |
__OM uint32_t GPT2T5CLR: 1 | |
__OM uint32_t GPT2T6CLR: 1 | |
__OM uint32_t GPT2CRCLR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t GPT1T2SET: 1 | |
__OM uint32_t GPT1T3SET: 1 | |
__OM uint32_t GPT1T4SET: 1 | |
__OM uint32_t GPT2T5SET: 1 | |
__OM uint32_t GPT2T6SET: 1 | |
__OM uint32_t GPT2CRSET: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GPTISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DMACH0EN: 1 | |
__IOM uint32_t DMACH1EN: 1 | |
__IOM uint32_t DMACH2EN: 1 | |
__IOM uint32_t DMACH3EN: 1 | |
__IOM uint32_t DMACH4EN: 1 | |
__IOM uint32_t DMACH5EN: 1 | |
__IOM uint32_t DMACH6EN: 1 | |
__IOM uint32_t DMACH7EN: 1 | |
__IOM uint32_t DMATRERREN: 1 | |
uint32_t __pad0__: 23 | |
} bit | |
} | DMAIEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t DMACH0: 1 | |
__IM uint32_t DMACH1: 1 | |
__IM uint32_t DMACH2: 1 | |
__IM uint32_t DMACH3: 1 | |
__IM uint32_t DMACH4: 1 | |
__IM uint32_t DMACH5: 1 | |
__IM uint32_t DMACH6: 1 | |
__IM uint32_t DMACH7: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMAIS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t DMACH0CLR: 1 | |
__OM uint32_t DMACH1CLR: 1 | |
__OM uint32_t DMACH2CLR: 1 | |
__OM uint32_t DMACH3CLR: 1 | |
__OM uint32_t DMACH4CLR: 1 | |
__OM uint32_t DMACH5CLR: 1 | |
__OM uint32_t DMACH6CLR: 1 | |
__OM uint32_t DMACH7CLR: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMAISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t DMACH0SET: 1 | |
__OM uint32_t DMACH1SET: 1 | |
__OM uint32_t DMACH2SET: 1 | |
__OM uint32_t DMACH3SET: 1 | |
__OM uint32_t DMACH4SET: 1 | |
__OM uint32_t DMACH5SET: 1 | |
__OM uint32_t DMACH6SET: 1 | |
__OM uint32_t DMACH7SET: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMAISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12CM70: 2 | |
__IOM uint32_t T12CM71: 2 | |
__IOM uint32_t T12CM72: 2 | |
__IOM uint32_t T12PM: 2 | |
__IOM uint32_t T12ZM: 2 | |
__IOM uint32_t T13CM: 2 | |
__IOM uint32_t T13PM: 2 | |
__IOM uint32_t T13ZM: 2 | |
__IOM uint32_t T14CM: 2 | |
__IOM uint32_t T14PM: 2 | |
__IOM uint32_t T15CM: 2 | |
__IOM uint32_t T15PM: 2 | |
__IOM uint32_t T16CM: 2 | |
__IOM uint32_t T16PM: 2 | |
__IOM uint32_t CHE: 2 | |
uint32_t __pad0__: 2 | |
} bit | |
} | DMAP_CCU7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ADC1_RES0: 2 | |
__IOM uint32_t ADC1_RES1: 2 | |
__IOM uint32_t ADC1_RES2: 2 | |
__IOM uint32_t ADC1_RES3: 2 | |
__IOM uint32_t ADC1_RES4: 2 | |
__IOM uint32_t ADC1_RES5: 2 | |
__IOM uint32_t ADC1_RES6: 2 | |
__IOM uint32_t ADC1_RES7: 2 | |
__IOM uint32_t ADC1_SQ0: 2 | |
__IOM uint32_t ADC1_SQ1: 2 | |
__IOM uint32_t ADC1_CMPLO: 2 | |
__IOM uint32_t ADC1_CMPHI: 2 | |
__IOM uint32_t SDADC_RES0: 2 | |
__IOM uint32_t SDADC_RES1: 2 | |
uint32_t __pad0__: 4 | |
} bit | |
} | DMAP_ADC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T2OV: 1 | |
__IOM uint32_t T21OV: 1 | |
uint32_t __pad0__: 6 | |
__IOM uint32_t GPT12T2: 1 | |
__IOM uint32_t GPT12T3: 1 | |
__IOM uint32_t GPT12T4: 1 | |
__IOM uint32_t GPT12T5: 1 | |
__IOM uint32_t GPT12T6: 1 | |
__IOM uint32_t GPT12CR: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | DMAP_TIM |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SSC0_RIR: 2 | |
__IOM uint32_t SSC0_TIR: 2 | |
__IOM uint32_t SSC1_RIR: 2 | |
__IOM uint32_t SSC1_TIR: 2 | |
__IOM uint32_t UART0_RI: 2 | |
__IOM uint32_t UART0_TI: 2 | |
__IOM uint32_t UART1_RI: 2 | |
__IOM uint32_t UART1_TI: 2 | |
__IOM uint32_t CAN_IR0: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CAN_IR1: 1 | |
uint32_t __pad1__: 13 | |
} bit | |
} | DMAP_COM |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__OM uint32_t SLEEP: 1 | |
__OM uint32_t STOP: 1 | |
uint32_t __pad1__: 29 | |
} bit | |
} | PMCON0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SSC0_DIS: 1 | |
__IOM uint32_t SSC1_DIS: 1 | |
__IOM uint32_t T2_DIS: 1 | |
__IOM uint32_t T21_DIS: 1 | |
__IOM uint32_t GPT12_DIS: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PMCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SSC0SUS: 1 | |
__IOM uint32_t SSC1SUS: 1 | |
__IOM uint32_t T2SUS: 1 | |
__IOM uint32_t T21SUS: 1 | |
__IOM uint32_t GPT12SUS: 1 | |
__IOM uint32_t WDTSUS: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | SUSCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t OT_SLEEP_EN: 1 | |
uint32_t __pad0__: 13 | |
__IOM uint32_t OTWARN_SD_DIS: 1 | |
__IOM uint32_t XTALWDG_SD_DIS: 1 | |
uint32_t __pad1__: 8 | |
__IOM uint32_t BDRV_SD_EN: 1 | |
uint32_t __pad2__: 7 | |
} bit | |
} | PCU_CTRL |
__IM uint32_t | RESERVED1 [9] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DEMEN_CH0: 1 | |
__IOM uint32_t DEMEN_CH1: 1 | |
__IOM uint32_t DEMEN_CH2: 1 | |
__IOM uint32_t DEMEN_CH3: 1 | |
__IOM uint32_t DEMEN_CH4: 1 | |
__IOM uint32_t DEMEN_CH5: 1 | |
__IOM uint32_t DEMEN_CH6: 1 | |
__IOM uint32_t DEMEN_CH7: 1 | |
__IOM uint32_t DMAREQINTEN_CH0: 1 | |
__IOM uint32_t DMAREQINTEN_CH1: 1 | |
__IOM uint32_t DMAREQINTEN_CH2: 1 | |
__IOM uint32_t DMAREQINTEN_CH3: 1 | |
__IOM uint32_t DMAREQINTEN_CH4: 1 | |
__IOM uint32_t DMAREQINTEN_CH5: 1 | |
__IOM uint32_t DMAREQINTEN_CH6: 1 | |
__IOM uint32_t DMAREQINTEN_CH7: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | DMACTRL |
__IM uint32_t | RESERVED2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOCKUP_EN: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | LOCKUPCFG |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
uint32_t __pad4__ |
uint32_t __pad5__ |
__IOM uint32_t ADC1_CMPHI |
[23..22] DMA Channel Request Select
__IOM uint32_t ADC1_CMPLO |
[21..20] DMA Channel Request Select
__IOM uint32_t ADC1_RES0 |
[1..0] DMA Channel Request Select
__IOM uint32_t ADC1_RES1 |
[3..2] DMA Channel Request Select
__IOM uint32_t ADC1_RES2 |
[5..4] DMA Channel Request Select
__IOM uint32_t ADC1_RES3 |
[7..6] DMA Channel Request Select
__IOM uint32_t ADC1_RES4 |
[9..8] DMA Channel Request Select
__IOM uint32_t ADC1_RES5 |
[11..10] DMA Channel Request Select
__IOM uint32_t ADC1_RES6 |
[13..12] DMA Channel Request Select
__IOM uint32_t ADC1_RES7 |
[15..14] DMA Channel Request Select
__IOM uint32_t ADC1_SQ0 |
[17..16] DMA Channel Request Select
__IOM uint32_t ADC1_SQ1 |
[19..18] DMA Channel Request Select
__IOM uint32_t B4 |
[1..1] Bridge Driver B6/B4 Configuration Bit
__IOM uint32_t BDRV_SD_EN |
[24..24] BDRV Shutdown Enable
__IOM uint32_t BIST_EXT_CLK |
[5..5] BIST window reference clock selection
__IM uint32_t BIST_WINDOW_DONE |
[6..6] Frequency BIST WINDOW Finished
__IOM uint32_t BIST_WINDOW_SEL |
[4..1] Frequency Bist window selection
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
union { ... } BOOT_CFG_LATCH |
__IOM uint32_t CAN_FD_EN |
[0..0] CAN Flexible Data Rate Enable Bit
__IOM uint32_t CAN_IR0 |
[16..16] DMA Channel Request Select
__IOM uint32_t CAN_IR1 |
[18..18] DMA Channel Request Select
__IOM uint32_t CANCLKEN |
[1..1] CAN Clock Enable
__IOM uint32_t CANTX_SD_EN |
[25..25] CANTX Shutdown Enable
__IOM uint32_t CHE |
[29..28] DMA Channel Request Select
union { ... } CLKCON |
union { ... } CLKCON |
union { ... } CLKEN |
union { ... } CLKEN |
__IOM uint32_t CLKOUTEN |
[19..19] CLKOUT Enable
union { ... } CLKSEL |
union { ... } CLKSEL |
__IOM uint32_t COARSE |
[9..5] HP_CLK Coarse Trim
__IOM uint32_t DEMEN_CH0 |
[0..0] DMA Endless Mode Enable Channel 0
__IOM uint32_t DEMEN_CH1 |
[1..1] DMA Endless Mode Enable Channel 1
__IOM uint32_t DEMEN_CH2 |
[2..2] DMA Endless Mode Enable Channel 2
__IOM uint32_t DEMEN_CH3 |
[3..3] DMA Endless Mode Enable Channel 3
__IOM uint32_t DEMEN_CH4 |
[4..4] DMA Endless Mode Enable Channel 4
__IOM uint32_t DEMEN_CH5 |
[5..5] DMA Endless Mode Enable Channel 5
__IOM uint32_t DEMEN_CH6 |
[6..6] DMA Endless Mode Enable Channel 6
__IOM uint32_t DEMEN_CH7 |
[7..7] DMA Endless Mode Enable Channel 7
__IOM uint32_t DIV2CLKOUT |
[27..27] CLKOUT clock divider by2
__IM uint32_t DMACH0 |
[0..0] DMA Channel 0 Interrupt Status
__OM uint32_t DMACH0CLR |
[0..0] DMA Channel 0 Interrupt Status Clear
__IOM uint32_t DMACH0EN |
[0..0] DMA Channel 0 Interrupt Enable
__OM uint32_t DMACH0SET |
[0..0] DMA Channel 0 Interrupt Status Set
__IM uint32_t DMACH1 |
[1..1] DMA Channel 1 Interrupt Status
__OM uint32_t DMACH1CLR |
[1..1] DMA Channel 1 Interrupt Status Clear
__IOM uint32_t DMACH1EN |
[1..1] DMA Channel 1 Interrupt Enable
__OM uint32_t DMACH1SET |
[1..1] DMA Channel 1 Interrupt Status Set
__IM uint32_t DMACH2 |
[2..2] DMA Channel 2 Interrupt Status
__OM uint32_t DMACH2CLR |
[2..2] DMA Channel 2 Interrupt Status Clear
__IOM uint32_t DMACH2EN |
[2..2] DMA Channel 2 Interrupt Enable
__OM uint32_t DMACH2SET |
[2..2] DMA Channel 2 Interrupt Status Set
__IM uint32_t DMACH3 |
[3..3] DMA Channel 3 Interrupt Status
__OM uint32_t DMACH3CLR |
[3..3] DMA Channel 3 Interrupt Status Clear
__IOM uint32_t DMACH3EN |
[3..3] DMA Channel 3 Interrupt Enable
__OM uint32_t DMACH3SET |
[3..3] DMA Channel 3 Interrupt Status Set
__IM uint32_t DMACH4 |
[4..4] DMA Channel 4 Interrupt Status
__OM uint32_t DMACH4CLR |
[4..4] DMA Channel 4 Interrupt Status Clear
__IOM uint32_t DMACH4EN |
[4..4] DMA Channel 4 Interrupt Enable
__OM uint32_t DMACH4SET |
[4..4] DMA Channel 4 Interrupt Status Set
__IM uint32_t DMACH5 |
[5..5] DMA Channel 5 Interrupt Status
__OM uint32_t DMACH5CLR |
[5..5] DMA Channel 5 Interrupt Status Clear
__IOM uint32_t DMACH5EN |
[5..5] DMA Channel 5 Interrupt Enable
__OM uint32_t DMACH5SET |
[5..5] DMA Channel 5 Interrupt Status Set
__IM uint32_t DMACH6 |
[6..6] DMA Channel 6 Interrupt Status
__OM uint32_t DMACH6CLR |
[6..6] DMA Channel 6 Interrupt Status Clear
__IOM uint32_t DMACH6EN |
[6..6] DMA Channel 6 Interrupt Enable
__OM uint32_t DMACH6SET |
[6..6] DMA Channel 6 Interrupt Status Set
__IM uint32_t DMACH7 |
[7..7] DMA Channel 7 Interrupt Status
__OM uint32_t DMACH7CLR |
[7..7] DMA Channel 7 Interrupt Status Clear
__IOM uint32_t DMACH7EN |
[7..7] DMA Channel 7 Interrupt Enable
__OM uint32_t DMACH7SET |
[7..7] DMA Channel 7 Interrupt Status Set
union { ... } DMACTRL |
union { ... } DMACTRL |
union { ... } DMAIEN |
union { ... } DMAIEN |
union { ... } DMAIS |
union { ... } DMAIS |
union { ... } DMAISC |
union { ... } DMAISC |
union { ... } DMAISS |
union { ... } DMAISS |
union { ... } DMAP_ADC |
union { ... } DMAP_ADC |
union { ... } DMAP_CCU7 |
union { ... } DMAP_CCU7 |
union { ... } DMAP_COM |
union { ... } DMAP_COM |
union { ... } DMAP_TIM |
union { ... } DMAP_TIM |
__IOM uint32_t DMAREQINTEN_CH0 |
[8..8] DMA Pending Request Interrupt Enable Channel 0
__IOM uint32_t DMAREQINTEN_CH1 |
[9..9] DMA Pending Request Interrupt Enable Channel 1
__IOM uint32_t DMAREQINTEN_CH2 |
[10..10] DMA Pending Request Interrupt Enable Channel 2
__IOM uint32_t DMAREQINTEN_CH3 |
[11..11] DMA Pending Request Interrupt Enable Channel 3
__IOM uint32_t DMAREQINTEN_CH4 |
[12..12] DMA Pending Request Interrupt Enable Channel 4
__IOM uint32_t DMAREQINTEN_CH5 |
[13..13] DMA Pending Request Interrupt Enable Channel 5
__IOM uint32_t DMAREQINTEN_CH6 |
[14..14] DMA Pending Request Interrupt Enable Channel 6
__IOM uint32_t DMAREQINTEN_CH7 |
[15..15] DMA Pending Request Interrupt Enable Channel 7
__IOM uint32_t DMATRERREN |
[8..8] DMA Error Interrupt Enable
__IOM uint32_t DOOR_FREQ_BIST_dtb |
[13..12] Frequency Bist Door Input Select
__IOM uint32_t DTB0_out |
[0..0] DTB0 output assignment
__IOM uint32_t DTB1_out |
[2..2] DTB1 output assignment
__IOM uint32_t DTB2_out |
[5..4] DTB2 output assignment
__IOM uint32_t DTB3_out |
[6..6] DTB3 output assignment
__IOM uint32_t DTB4_out |
[8..8] DTB4 output assignment
__IOM uint32_t DYEN |
[15..15] Dynamic Trimming Enable
union { ... } EXTCON |
union { ... } EXTCON |
union { ... } EXTIEN |
union { ... } EXTIEN |
__IOM uint32_t EXTINT0EN |
[0..0] External EXTINT0 Interrupt Enable
__IM uint32_t EXTINT0F |
[1..1] External EXTINT0 Falling Edge Interrupt Status
__OM uint32_t EXTINT0FCLR |
[1..1] External EXTINT0 Falling Edge Interrupt Status Clear
__OM uint32_t EXTINT0FSET |
[1..1] External EXTINT0 Falling Edge Interrupt Status Set
__IOM uint32_t EXTINT0IEV |
[1..0] External EXTINT0 Interrupt Event Select
__IOM uint32_t EXTINT0INSEL |
[9..8] External EXTINT0 Input Select
__IM uint32_t EXTINT0R |
[0..0] External EXTINT0 Rising Edge Interrupt Status
__OM uint32_t EXTINT0RCLR |
[0..0] External EXTINT0 Rising Edge Interrupt Status Clear
__OM uint32_t EXTINT0RSET |
[0..0] External EXTINT0 Rising Edge Interrupt Status Set
__IOM uint32_t EXTINT1EN |
[1..1] External EXTINT1 Interrupt Enable
__IM uint32_t EXTINT1F |
[3..3] External EXTINT1 Falling Edge Interrupt Status
__OM uint32_t EXTINT1FCLR |
[3..3] External EXTINT1 Falling Edge Interrupt Status Clear
__OM uint32_t EXTINT1FSET |
[3..3] External EXTINT1Falling Edge Interrupt Status Set
__IOM uint32_t EXTINT1IEV |
[3..2] External EXTINT1 Interrupt Event Select
__IOM uint32_t EXTINT1INSEL |
[11..10] External EXTINT1 Input Select
__IM uint32_t EXTINT1R |
[2..2] External EXTINT1 Rising Edge Interrupt Status
__OM uint32_t EXTINT1RCLR |
[2..2] External EXTINT1 Rising Edge Interrupt Status Clear
__OM uint32_t EXTINT1RSET |
[2..2] External EXTINT1Rising Edge Interrupt Status Set
__IOM uint32_t EXTINT2EN |
[2..2] External EXTINT2 Interrupt Enable
__IM uint32_t EXTINT2F |
[5..5] External EXTINT2 Falling Edge Interrupt Status
__OM uint32_t EXTINT2FCLR |
[5..5] External EXTINT2 Falling Edge Interrupt Status Clear
__OM uint32_t EXTINT2FSET |
[5..5] External EXTINT2 Falling Edge Interrupt Status Set
__IOM uint32_t EXTINT2IEV |
[5..4] External EXTINT2 Interrupt Event Select
__IOM uint32_t EXTINT2INSEL |
[13..12] External EXTINT2 Input Select
__IM uint32_t EXTINT2R |
[4..4] External EXTINT2 Rising Edge Interrupt Status
__OM uint32_t EXTINT2RCLR |
[4..4] External EXTINT2 Rising Edge Interrupt Status Clear
__OM uint32_t EXTINT2RSET |
[4..4] External EXTINT2 Rising Edge Interrupt Status Set
__IOM uint32_t EXTINT3EN |
[3..3] External EXTINT3 Interrupt Enable
__IM uint32_t EXTINT3F |
[7..7] External EXTINT3 Falling Edge Interrupt Status
__OM uint32_t EXTINT3FCLR |
[7..7] External EXTINT3 Falling Edge Interrupt Status Clear
__OM uint32_t EXTINT3FSET |
[7..7] External EXTINT3 Falling Edge Interrupt Status Set
__IOM uint32_t EXTINT3IEV |
[7..6] External EXTINT3Interrupt Event Select
__IOM uint32_t EXTINT3INSEL |
[15..14] External EXTINT3 Input Select
__IM uint32_t EXTINT3R |
[6..6] External EXTINT3 Rising Edge Interrupt Status
__OM uint32_t EXTINT3RCLR |
[6..6] External EXTINT3 Rising Edge Interrupt Status Clear
__OM uint32_t EXTINT3RSET |
[6..6] External EXTINT3 Rising Edge Interrupt Status Set
union { ... } EXTIS |
union { ... } EXTIS |
union { ... } EXTISC |
union { ... } EXTISC |
union { ... } EXTISS |
union { ... } EXTISS |
__IOM uint32_t FINE |
[4..0] HP_CLK Fine Trim
__IM uint32_t FREQ |
[31..16] Frequency Counter Value
__IOM uint32_t FREQ_BIST |
[0..0] Activates Frequency BIST
union { ... } FREQ_BIST1 |
__IM uint32_t FTM |
[27..24] Firmware Test Setting
__IM uint32_t FTM_EN |
[23..23] Firmware Test Mode Active
__IM uint32_t GLOB_TM |
[22..22] Global Testmode active
__IOM uint32_t GP_TRC_IN_REG |
[31..0] GP JTAG data out
union { ... } GP_TRC_IN_REG |
__IM uint32_t GP_TRC_OUT_REG |
[31..0] GP JTAG data in
union { ... } GP_TRC_OUT_REG |
__IOM uint32_t GPT12_DIS |
[4..4] General Purpose Timer 12 Module Disable
__IOM uint32_t GPT12CR |
[13..13] DMA Channel Request Select
__IOM uint32_t GPT12SUS |
[4..4] Gerneral Purpose Timer 12 Suspend
__IOM uint32_t GPT12T2 |
[8..8] DMA Channel Request Select
__IOM uint32_t GPT12T3 |
[9..9] DMA Channel Request Select
__IOM uint32_t GPT12T4 |
[10..10] DMA Channel Request Select
__IOM uint32_t GPT12T5 |
[11..11] DMA Channel Request Select
__IOM uint32_t GPT12T6 |
[12..12] DMA Channel Request Select
__IM uint32_t GPT1T2 |
[0..0] General Purpose Timer 1 T2 Interrupt Status
__OM uint32_t GPT1T2CLR |
[0..0] General Purpose Timer 1 T2 Interrupt Status Clear
__IOM uint32_t GPT1T2EN |
[0..0] General Purpose Timer 1 T2 Interrupt Enable
__OM uint32_t GPT1T2SET |
[0..0] General Purpose Timer 1 T2 Interrupt Status Set
__IM uint32_t GPT1T3 |
[1..1] General Purpose Timer 1 T3 Interrupt Status
__OM uint32_t GPT1T3CLR |
[1..1] General Purpose Timer 1 T3 Interrupt Status Clear
__IOM uint32_t GPT1T3EN |
[1..1] General Purpose Timer 1 T3 Interrupt Enable
__OM uint32_t GPT1T3SET |
[1..1] General Purpose Timer 1 T3 Interrupt Status Set
__IM uint32_t GPT1T4 |
[2..2] General Purpose Timer 1 T4 Interrupt Status
__OM uint32_t GPT1T4CLR |
[2..2] General Purpose Timer 1 T4 Interrupt Status Clear
__IOM uint32_t GPT1T4EN |
[2..2] General Purpose Timer 1 T4 Interrupt Enable
__OM uint32_t GPT1T4SET |
[2..2] General Purpose Timer 1 T4 Interrupt Status Set
__IM uint32_t GPT2CR |
[5..5] General Purpose Timer 2 CR Interrupt Status
__OM uint32_t GPT2CRCLR |
[5..5] General Purpose Timer 2 CR Interrupt Status Clear
__IOM uint32_t GPT2CREN |
[5..5] General Purpose Timer 2 CR Interrupt Enable
__OM uint32_t GPT2CRSET |
[5..5] General Purpose Timer 2 CR Interrupt Status Set
__IM uint32_t GPT2T5 |
[3..3] General Purpose Timer 2 T5 Interrupt Status
__OM uint32_t GPT2T5CLR |
[3..3] General Purpose Timer 2 T5 Interrupt Status Clear
__IOM uint32_t GPT2T5EN |
[3..3] General Purpose Timer 2 T5 Interrupt Enable
__OM uint32_t GPT2T5SET |
[3..3] General Purpose Timer 2 T5 Interrupt Status Set
__IM uint32_t GPT2T6 |
[4..4] General Purpose Timer 2 T6 Interrupt Status
__OM uint32_t GPT2T6CLR |
[4..4] General Purpose Timer 2 T6 Interrupt Status Clear
__IOM uint32_t GPT2T6EN |
[4..4] General Purpose Timer 2 T6 Interrupt Enable
__OM uint32_t GPT2T6SET |
[4..4] General Purpose Timer 2 T6 Interrupt Status Set
union { ... } GPTIEN |
union { ... } GPTIEN |
union { ... } GPTIS |
union { ... } GPTIS |
union { ... } GPTISC |
union { ... } GPTISC |
union { ... } GPTISS |
union { ... } GPTISS |
__IM uint32_t HARR |
[21..21] HARR Request
union { ... } HPCLKTRIM |
__IOM uint32_t HPWDGEN |
[8..8] HPWDG Enable in Test Mode
__IOM uint32_t HPWDGRST |
[9..9] HPWDG Reset in Test Mode
union { ... } INP0 |
union { ... } INP0 |
union { ... } INP1 |
union { ... } INP1 |
union { ... } INP2 |
union { ... } INP2 |
union { ... } INP3 |
union { ... } INP3 |
union { ... } INP4 |
union { ... } INP4 |
union { ... } INP5 |
union { ... } INP5 |
union { ... } INP6 |
union { ... } INP6 |
union { ... } INP7 |
union { ... } INP7 |
__IOM uint32_t INP_ARVG |
[4..4] ARVG Interrupt Mapping
__IOM uint32_t INP_BDRV_IRQ0 |
[1..1] Bridge Driver Interrupt 0 Mapping
__IOM uint32_t INP_BDRV_IRQ1 |
[2..2] Bridge Driver Interrupt 1 Mapping
__IOM uint32_t INP_BEMF0 |
[2..2] BEMF0 Interrupt Mapping
__IOM uint32_t INP_BEMF1 |
[3..3] BEMF1 Interrupt Mapping
__IOM uint32_t INP_BEMF2 |
[4..4] BEMF2 Interrupt Mapping
__IOM uint32_t INP_CANTX |
[3..3] CANTX Interrupt Mapping
__IOM uint32_t INP_CSC |
[5..5] CSC Interrupt Mapping
__IOM uint32_t INP_DMACH0 |
[0..0] DMACH0 Interrupt Mapping
__IOM uint32_t INP_DMACH1 |
[1..1] DMACH1 Interrupt Mapping
__IOM uint32_t INP_DMACH2 |
[2..2] DMACH2 Interrupt Mapping
__IOM uint32_t INP_DMACH3 |
[3..3] DMACH3 Interrupt Mapping
__IOM uint32_t INP_DMACH4 |
[4..4] DMACH4 Interrupt Mapping
__IOM uint32_t INP_DMACH5 |
[5..5] DMACH5 Interrupt Mapping
__IOM uint32_t INP_DMACH6 |
[6..6] DMACH6 Interrupt Mapping
__IOM uint32_t INP_DMACH7 |
[7..7] DMACH7 Interrupt Mapping
__IOM uint32_t INP_DMATRERR |
[8..8] DMATRERR Interrupt Mapping
__IOM uint32_t INP_EXINT0 |
[0..0] EXINT0 Interrupt Mapping
__IOM uint32_t INP_EXINT1 |
[1..1] EXINT1 Interrupt Mapping
__IOM uint32_t INP_EXINT2 |
[2..2] EXINT2 Interrupt Mapping
__IOM uint32_t INP_EXINT3 |
[3..3] EXINT3 Interrupt Mapping
__IOM uint32_t INP_GPT1T2 |
[0..0] GPT1T2 Interrupt Mapping
__IOM uint32_t INP_GPT1T3 |
[1..1] GPT1T3 Interrupt Mapping
__IOM uint32_t INP_GPT1T4 |
[2..2] GPT1T4 Interrupt Mapping
__IOM uint32_t INP_GPT2CR |
[5..5] GPT2CR Interrupt Mapping
__IOM uint32_t INP_GPT2T5 |
[3..3] GPT2T5 Interrupt Mapping
__IOM uint32_t INP_GPT2T6 |
[4..4] GPT2T6 Interrupt Mapping
__IOM uint32_t INP_LIN0_EOFSYN |
[0..0] LIN0_EOFSYN Interrupt Mapping
__IOM uint32_t INP_LIN0_ERRSYN |
[1..1] LIN0_ERRSYN Interrupt Mapping
__IOM uint32_t INP_LIN1_EOFSYN |
[2..2] LIN1_EOFSYN Interrupt Mapping
__IOM uint32_t INP_LIN1_ERRSYN |
[3..3] LIN1_ERRSYN Interrupt Mapping
__IOM uint32_t INP_MON1 |
[0..0] MON1 Interrupt Mapping
__IOM uint32_t INP_MON2 |
[1..1] MON2 Interrupt Mapping
__IOM uint32_t INP_MON3 |
[2..2] MON3 Interrupt Mapping
__IOM uint32_t INP_PMU |
[0..0] PMU Interrupt Mapping
__IOM uint32_t INP_SDADC0 |
[0..0] SDADC0 Interrupt Mapping
__IOM uint32_t INP_SDADC1 |
[1..1] SDADC1 Interrupt Mapping
__IOM uint32_t INP_SSC0_EIR |
[2..2] SSC0_EIR Interrupt Mapping
__IOM uint32_t INP_SSC0_RIR |
[0..0] SSC0_RIR Interrupt Mapping
__IOM uint32_t INP_SSC0_TIR |
[1..1] SSC0_TIR Interrupt Mapping
__IOM uint32_t INP_SSC1_EIR |
[6..6] SSC1_EIR Interrupt Mapping
__IOM uint32_t INP_SSC1_RIR |
[4..4] SSC1_RIR Interrupt Mapping
__IOM uint32_t INP_SSC1_TIR |
[5..5] SSC1_TIR Interrupt Mapping
__IOM uint32_t INP_UART0_RI |
[4..4] UART0_RI Interrupt Mapping
__IOM uint32_t INP_UART0_TI |
[5..5] UART0_TI Interrupt Mapping
__IOM uint32_t INP_UART1_RI |
[6..6] UART1_RI Interrupt Mapping
__IOM uint32_t INP_UART1_TI |
[7..7] UART1_TI Interrupt Mapping
__IM uint32_t JSTAT |
[6..6] JTAG/SWD Activity Status Bit
__IOM uint32_t JTAG_EN |
[19..19] JTAG Activity Status Bit
__IOM uint32_t LOCKUP_EN |
[0..0] CPU LOCKUP Reset Enable
union { ... } LOCKUPCFG |
union { ... } LOCKUPCFG |
__IOM uint32_t MON1EN |
[0..0] MON1 Interrupt Enable
__IM uint32_t MON1F |
[1..1] MON1 Falling Edge Interrupt Status
__OM uint32_t MON1FCLR |
[1..1] MON1 Falling Edge Interrupt Status Clear
__OM uint32_t MON1FSET |
[1..1] MON1 Falling Edge Interrupt Status Set
__IOM uint32_t MON1IEV |
[1..0] MON1 Interrupt Event Select
__IM uint32_t MON1R |
[0..0] MON1 Rising Edge Interrupt Status
__OM uint32_t MON1RCLR |
[0..0] MON1 Rising Edge Interrupt Status Clear
__OM uint32_t MON1RSET |
[0..0] MON1 Rising Edge Interrupt Status Set
__IOM uint32_t MON2EN |
[1..1] MON2 Interrupt Enable
__IM uint32_t MON2F |
[3..3] MON2 Falling Edge Interrupt Status
__OM uint32_t MON2FCLR |
[3..3] MON2 Falling Edge Interrupt Status Clear
__OM uint32_t MON2FSET |
[3..3] MON2 Falling Edge Interrupt Status Set
__IOM uint32_t MON2IEV |
[3..2] MON2 Interrupt Event Select
__IM uint32_t MON2R |
[2..2] MON2 Rising Edge Interrupt Status
__OM uint32_t MON2RCLR |
[2..2] MON2 Rising Edge Interrupt Status Clear
__OM uint32_t MON2RSET |
[2..2] MON2 Rising Edge Interrupt Status Set
__IOM uint32_t MON3EN |
[2..2] MON3 Interrupt Enable
__IM uint32_t MON3F |
[5..5] MON3 Falling Edge Interrupt Status
__OM uint32_t MON3FCLR |
[5..5] MON3 Falling Edge Interrupt Status Clear
__OM uint32_t MON3FSET |
[5..5] MON3 Falling Edge Interrupt Status Set
__IOM uint32_t MON3IEV |
[5..4] MON3 Interrupt Event Select
__IM uint32_t MON3R |
[4..4] MON3 Rising Edge Interrupt Status
__OM uint32_t MON3RCLR |
[4..4] MON3 Rising Edge Interrupt Status Clear
__OM uint32_t MON3RSET |
[4..4] MON3 Rising Edge Interrupt Status Set
union { ... } MONCON |
union { ... } MONCON |
union { ... } MONIEN |
union { ... } MONIEN |
union { ... } MONIS |
union { ... } MONIS |
union { ... } MONISC |
union { ... } MONISC |
union { ... } MONISS |
union { ... } MONISS |
__IOM uint32_t NMICNTEN |
[1..1] NMI Disable Counter Enable
__IOM uint32_t NMICNTVAL |
[13..8] NMI Disable Counter Setting
union { ... } NMICON |
union { ... } NMICON |
__IOM uint32_t NMIDIS |
[2..2] NMI Disable
union { ... } NMIDISCFG |
__IOM uint32_t NMIDISMOD |
[0..0] NMI Disable Mode - SFR or EXEC_ADDR
__IM uint32_t NMIPLL0 |
[1..1] PLL0 Loss of Lock NMI Status
__OM uint32_t NMIPLL0CLR |
[1..1] PLL0 Loss of Lock NMI Status Clear
__IOM uint32_t NMIPLL0EN |
[1..1] PLL0 Loss of Lock NMI Enable
__OM uint32_t NMIPLL0SET |
[1..1] PLL0 Loss of Lock NMI Status Set
__IM uint32_t NMIPLL1 |
[2..2] PLL1 Loss of Lock NMI Status
__OM uint32_t NMIPLL1CLR |
[2..2] PLL1 Loss of Lock NMI Status Clear
__IOM uint32_t NMIPLL1EN |
[2..2] PLL1 Loss of Lock NMI Enable
__OM uint32_t NMIPLL1SET |
[2..2] PLL1 Loss of Lock NMI Status Set
union { ... } NMISR |
union { ... } NMISR |
union { ... } NMISRC |
union { ... } NMISRC |
union { ... } NMISRS |
union { ... } NMISRS |
__IM uint32_t NMIXTAL |
[0..0] XTAL Watchdog Fail NMI Status
__OM uint32_t NMIXTALCLR |
[0..0] XTAL Watchdog Fail NMI Status Clear
__IOM uint32_t NMIXTALEN |
[0..0] XTAL Watchdog Fail NMI Enable
__OM uint32_t NMIXTALSET |
[0..0] XTAL Watchdog Fail NMI Status Set
__IOM uint32_t OFFSET0 |
[19..16] Dynamic Fine Trim Offset 0
__IOM uint32_t OFFSET1 |
[23..20] Dynamic Fine Trim Offset 1
__IOM uint32_t OFFSET2 |
[27..24] Dynamic Fine Trim Offset 2
__IOM uint32_t OFFSET3 |
[31..28] Dynamic Fine Trim Offset 3
__IOM uint32_t OT_SLEEP_EN |
[0..0] System Overtemperature Sleep Mode Enable
__IOM uint32_t OTWARN_SD_DIS |
[14..14] Overtemperature Warning Peripherals Shutdown Disable
__IM uint32_t P00 |
[1..1] Pin P0.0 Latch Value
__IM uint32_t P01 |
[2..2] Pin P0.1 Latch Value
__IM uint32_t P02 |
[3..3] Pin P0.2 Latch Value
__IM uint32_t P22 |
[4..4] Pin P2.2 Latch Value
__IM uint32_t P23 |
[5..5] Pin P2.3 Latch Value
union { ... } PCU_CTRL |
union { ... } PCU_CTRL |
union { ... } PKGCFG0 |
union { ... } PMCON |
union { ... } PMCON |
union { ... } PMCON0 |
union { ... } PMCON0 |
__IOM uint32_t PRECAN |
[18..16] CAN_CLK Prescaler Setting (based on sys1_clk)
__IOM uint32_t PRECLKOUT |
[26..24] CLKOUT_CLK Prescaler Setting (based on selected clock by SELCLKOUT)
__IOM uint32_t PRECPU |
[2..0] CPU_CLK Prescaler Setting (based on sys0_clk)
__IOM uint32_t PREFILT |
[8..4] TFILT_CLK Prescaler Setting (based on sys0_clk)
__IOM uint32_t PREMI |
[11..9] MI_CLK Prescaler Setting (based on sys0_clk)
__IOM uint32_t PREUART |
[22..20] UART_CLK Prescaler Setting (based on sys1_clk)
__IOM uint32_t RAM_ID |
[9..8] RAM ID
__IOM uint32_t reg |
(@ 0x00000000) System Clock Select Register
(@ 0x00000004) Peripheral Clock Prescaler Register
(@ 0x00000008) Peripheral Clock Enable Register
(@ 0x0000000C) HP_CLK Trimming Settings
(@ 0x00000010) System Test Clock Register
(@ 0x00000014) XTAL Control Register
(@ 0x0000001C) XTAL Status Clear Register
(@ 0x00000020) XTAL Status Set Register
(@ 0x00000024) Interrupt Node 0 Mapping Register
(@ 0x00000028) Interrupt Node 1 Mapping Register
(@ 0x0000002C) Interrupt Node 2 Mapping Register
(@ 0x00000030) Interrupt Node 3 Mapping Register
(@ 0x00000034) Interrupt Node 4 Mapping Register
(@ 0x00000038) Interrupt Node 5 Mapping Register
(@ 0x0000003C) Interrupt Node 6 Mapping Register
(@ 0x00000040) Interrupt Node 7 Mapping Register
(@ 0x00000044) NMI Control Register
(@ 0x0000004C) NMI Status Clear Register
(@ 0x00000050) NMI Status Set Register
(@ 0x00000054) MON Interrupt Enable Register
(@ 0x0000005C) MON Interrupt Status Clear Register
(@ 0x00000060) MON Interrupt Status Set Register
(@ 0x00000064) MON Interrupt Configuration Register
(@ 0x00000068) External Interrupt Enable Register
(@ 0x00000070) External Interrupt Status Clear Register
(@ 0x00000074) External Interrupt Status Set Register
(@ 0x00000078) EXT Interrupt Configuration Register
(@ 0x0000007C) General Purpose Timer 12 Interrupt Enable Register
(@ 0x00000084) General Purpose Timer 12 Interrupt Status Clear Register
(@ 0x00000088) General Purpose Timer 12 Interrupt Status Set Register
(@ 0x0000008C) DMA Interrupt Enable Register
(@ 0x00000094) DAM Interrupt Status Clear Register
(@ 0x00000098) DMA Interrupt Status Set Register
(@ 0x0000009C) DMA Channel Select Register CCU7
(@ 0x000000A0) DMA Channel Select Register ADCs
(@ 0x000000A4) DMA Channel Select Register Timer
(@ 0x000000A8) DMA Channel Select Register COM Modules
(@ 0x000000AC) Power Mode Control Register
(@ 0x000000B0) Peripheral Management Control Register
(@ 0x000000B4) Module Suspend Control Register
(@ 0x000000B8) PCU Control Register
(@ 0x000000C0) Test Control Register 1
(@ 0x000000C4) Testmode Password
(@ 0x000000C8) Frequency Bist Control Register 1
(@ 0x000000CC) General Purpose TRC Input Register
(@ 0x000000D8) Protection Control Register
(@ 0x000000DC) Package Configuration Register 0
(@ 0x000000E0) DMA Control Register
(@ 0x000000E4) NMI Disable Control Register
(@ 0x000000E8) CPU LOCKUP Config Register
__IM uint32_t reg |
(@ 0x00000018) XTAL Status Register
(@ 0x00000048) NMI Status Register
(@ 0x00000058) MON Interrupt Status Register
(@ 0x0000006C) External Interrupt Status Register
(@ 0x00000080) General Purpose Timer 12 Interrupt Status Register
(@ 0x00000090) DMA Interrupt Status Register
(@ 0x000000BC) Boot Configuration Latch Register
(@ 0x000000D0) General Purpose TRC Output Register
(@ 0x000000D4) Test Status Register 1
__IM uint32_t RESERVED[2] |
__IM uint32_t RESERVED1[9] |
__IM uint32_t RESERVED2 |
__IOM uint32_t RREF |
[13..10] HP_CLK RREF Trim
__IOM uint32_t SDADC_EN |
[2..2] Sigma Delta ADC Enable Bit
__IOM uint32_t SDADC_MOD_VDIG_I_dtb |
[11..10] MOD_VDIG_I input DTB assignment (SD-ADC)
__IOM uint32_t SDADC_RES0 |
[25..24] DMA Channel Request Select
__IOM uint32_t SDADC_RES1 |
[27..26] DMA Channel Request Select
__IOM uint32_t SEC_MODE |
[5..4] Security Mode
__IOM uint32_t SELCLKOUT |
[18..16] CLKOUT Selection
__IOM uint32_t SELSYS0 |
[1..0] System Clock fsys0 Select
__IOM uint32_t SELSYS1 |
[3..2] System Clock fsys1 Select
__IOM uint32_t SFR_PROT1ST |
[3..3] Internal SFRs first level protection
__IOM uint32_t SFR_PROT2ND |
[4..4] Internal SFRs second level protection
__OM uint32_t SLEEP |
[1..1] Sleep Mode Enable
__IOM uint32_t SSC0_DIS |
[0..0] SSC0 Module Disable
__IOM uint32_t SSC0_RIR |
[1..0] DMA Channel Request Select
__IOM uint32_t SSC0_TIR |
[3..2] DMA Channel Request Select
__IOM uint32_t SSC0SUS |
[0..0] SSC0 Suspend
__IOM uint32_t SSC1_DIS |
[1..1] SSC1 Module Disable
__IOM uint32_t SSC1_RIR |
[5..4] DMA Channel Request Select
__IOM uint32_t SSC1_TIR |
[7..6] DMA Channel Request Select
__IOM uint32_t SSC1SUS |
[1..1] SSC1 Suspend
union { ... } SSTCON |
__OM uint32_t STOP |
[2..2] STOP Mode Enable
union { ... } SUSCTR |
union { ... } SUSCTR |
__IOM uint32_t SWD_EN |
[18..17] SWD Activity Status Bit
union { ... } SYSCLKTEST |
__IOM uint32_t T12CM70 |
[1..0] DMA Channel Request Select
__IOM uint32_t T12CM71 |
[3..2] DMA Channel Request Select
__IOM uint32_t T12CM72 |
[5..4] DMA Channel Request Select
__IOM uint32_t T12PM |
[7..6] DMA Channel Request Select
__IOM uint32_t T12ZM |
[9..8] DMA Channel Request Select
__IOM uint32_t T13CM |
[11..10] DMA Channel Request Select
__IOM uint32_t T13PM |
[13..12] DMA Channel Request Select
__IOM uint32_t T13ZM |
[15..14] DMA Channel Request Select
__IOM uint32_t T14CM |
[17..16] DMA Channel Request Select
__IOM uint32_t T14PM |
[19..18] DMA Channel Request Select
__IOM uint32_t T15CM |
[21..20] DMA Channel Request Select
__IOM uint32_t T15PM |
[23..22] DMA Channel Request Select
__IOM uint32_t T16CM |
[25..24] DMA Channel Request Select
__IOM uint32_t T16PM |
[27..26] DMA Channel Request Select
__IOM uint32_t T21_DIS |
[3..3] Timer 21 Module Disable
__IOM uint32_t T21OV |
[1..1] DMA Channel Request Select
__IOM uint32_t T21SUS |
[3..3] Timer 21 Suspend
__IOM uint32_t T2_DIS |
[2..2] Timer 20 Module Disable
__IOM uint32_t T2OV |
[0..0] DMA Channel Request Select
__IOM uint32_t T2SUS |
[2..2] Timer 20 Suspend
union { ... } TCR1 |
union { ... } TEST_STS |
__IOM uint32_t TESTCK_EN |
[16..16] TESTCK Enable Bit
__IOM uint32_t TESTCK_SEL |
[15..14] TESTCK Selection Bits
__IOM uint32_t TM_PASSWD |
[11..0] Testmode Password
__IOM uint32_t TMODE_R |
[0..0] TEST Mode Status Bit
union { ... } TMPWD |
__IM uint32_t TMS |
[0..0] Pin TMS Latch Value
__IOM uint32_t TST_CTRL |
[31..31] module test enable Signal
__IOM uint32_t UART0_RI |
[9..8] DMA Channel Request Select
__IOM uint32_t UART0_TI |
[11..10] DMA Channel Request Select
__IOM uint32_t UART1_RI |
[13..12] DMA Channel Request Select
__IOM uint32_t UART1_TI |
[15..14] DMA Channel Request Select
__IOM uint32_t UARTCLKEN |
[0..0] UART Clock Enable
__IOM uint32_t UMODE_R |
[1..1] User Mode Status Bit
__IOM uint32_t VARIANT_ID |
[15..12] Variant ID
__IOM uint32_t VDDC_OV_SD_DIS |
[10..10] VDDC Overvoltage Peripherals Shutdown Disable
__IOM uint32_t VDDC_UV_SD_DIS |
[11..11] VDDC Undervoltage Peripherals Shutdown Disable
__IOM uint32_t VDDP_OV_SD_DIS |
[8..8] VDDP Overvoltage Peripherals Shutdown Disable
__IOM uint32_t VDDP_UV_SD_DIS |
[9..9] VDDP Undervoltage Peripherals Shutdown Disable
__IOM uint32_t VS_OV_SD_DIS |
[12..12] VS Overvoltage Peripherals Shutdown Disable
__IOM uint32_t VS_UV_SD_DIS |
[13..13] VS Undervoltage Peripherals Shutdown Disable
__IOM uint32_t WDTSUS |
[5..5] SCU Watchdog Timer Suspend
__IOM uint32_t XPD |
[0..0] XTAL Power Down Control
__IOM uint32_t XPROT_R |
[2..2] XSFR Bit Protection Enable Bit
__IM uint32_t XTAL_FAIL_STS |
[0..0] XTAL Watchdog Fail Latched Status
__OM uint32_t XTAL_FAIL_STSCLR |
[0..0] XTAL Watchdog Fail Latched Status Clear
__OM uint32_t XTAL_FAIL_STSSET |
[0..0] XTAL Watchdog Fail Latched Status Set
__IOM uint32_t XTAL_ON |
[0..0] XTAL Operation in Power Down Mode
union { ... } XTALCON |
union { ... } XTALCON |
__IM uint32_t XTALFAIL |
[8..8] XTAL Watchdog Fail Current Status
__IOM uint32_t XTALHYS |
[5..4] XTAL Hysteresis Control
__IOM uint32_t XTALHYSEN |
[1..1] XTAL Hysteresis Enable
__IOM uint32_t XTALSHBYEN |
[2..2] XTAL Shaper Bypass
__IOM uint32_t XTALSHDIS |
[3..3] XTAL Shaper Disable
union { ... } XTALSTAT |
union { ... } XTALSTAT |
union { ... } XTALSTATC |
union { ... } XTALSTATC |
union { ... } XTALSTATS |
union { ... } XTALSTATS |
__IOM uint32_t XTALWDG_SD_DIS |
[15..15] XTAL Watchdog Peripherals Shutdown Disable
__IOM uint32_t XWDGEN |
[24..24] XTALWDG Enable
__OM uint32_t XWDGRES |
[28..28] XTALWDG Reset