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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
|
ADC1 (ADC1)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EN: 1 | |
__IOM uint32_t LOWSUP: 1 | |
__IOM uint32_t DSCAL: 1 | |
__IOM uint32_t CPCLK_HV_FAST: 1 | |
__IOM uint32_t EN_CONV_TIMOUT: 1 | |
__IOM uint32_t ISTE: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | GLOBCONF |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CLKDIV: 4 | |
uint32_t __pad0__: 28 | |
} bit | |
} | CLKCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SUSEN: 1 | |
__IOM uint32_t SUSMOD: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | SUSCTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t STAT: 1 | |
__IM uint32_t READY: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | SUSSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0: 1 | |
__IOM uint32_t SQ1: 1 | |
__IOM uint32_t SQ2: 1 | |
__IOM uint32_t SQ3: 1 | |
__IOM uint32_t WFR0: 1 | |
__IOM uint32_t WFR1: 1 | |
__IOM uint32_t WFR2: 1 | |
__IOM uint32_t WFR3: 1 | |
__IOM uint32_t COLL0: 1 | |
__IOM uint32_t COLL1: 1 | |
__IOM uint32_t COLL2: 1 | |
__IOM uint32_t COLL3: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t SQNUM: 3 | |
uint32_t __pad1__: 13 | |
} bit | |
} | SQSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0CLR: 1 | |
__IOM uint32_t SQ1CLR: 1 | |
__IOM uint32_t SQ2CLR: 1 | |
__IOM uint32_t SQ3CLR: 1 | |
__IOM uint32_t WFR0CLR: 1 | |
__IOM uint32_t WFR1CLR: 1 | |
__IOM uint32_t WFR2CLR: 1 | |
__IOM uint32_t WFR3CLR: 1 | |
__IOM uint32_t COLL0CLR: 1 | |
__IOM uint32_t COLL1CLR: 1 | |
__IOM uint32_t COLL2CLR: 1 | |
__IOM uint32_t COLL3CLR: 1 | |
uint32_t __pad0__: 20 | |
} bit | |
} | SQSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0SET: 1 | |
__IOM uint32_t SQ1SET: 1 | |
__IOM uint32_t SQ2SET: 1 | |
__IOM uint32_t SQ3SET: 1 | |
__IOM uint32_t WFR0SET: 1 | |
__IOM uint32_t WFR1SET: 1 | |
__IOM uint32_t WFR2SET: 1 | |
__IOM uint32_t WFR3SET: 1 | |
__IOM uint32_t COLL0SET: 1 | |
__IOM uint32_t COLL1SET: 1 | |
__IOM uint32_t COLL2SET: 1 | |
__IOM uint32_t COLL3SET: 1 | |
uint32_t __pad0__: 20 | |
} bit | |
} | SQSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CH0: 1 | |
__IOM uint32_t CH1: 1 | |
__IOM uint32_t CH2: 1 | |
__IOM uint32_t CH3: 1 | |
__IOM uint32_t CH4: 1 | |
__IOM uint32_t CH5: 1 | |
__IOM uint32_t CH6: 1 | |
__IOM uint32_t CH7: 1 | |
__IOM uint32_t CH8: 1 | |
__IOM uint32_t CH9: 1 | |
__IOM uint32_t CH10: 1 | |
__IOM uint32_t CH11: 1 | |
__IOM uint32_t CH12: 1 | |
__IOM uint32_t CH13: 1 | |
__IOM uint32_t CH14: 1 | |
__IOM uint32_t CH15: 1 | |
__IOM uint32_t CH16: 1 | |
__IOM uint32_t CH17: 1 | |
__IOM uint32_t CH18: 1 | |
__IOM uint32_t CH19: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CHNUM: 5 | |
uint32_t __pad1__: 3 | |
} bit | |
} | CHSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CH0CLR: 1 | |
__OM uint32_t CH1CLR: 1 | |
__OM uint32_t CH2CLR: 1 | |
__OM uint32_t CH3CLR: 1 | |
__OM uint32_t CH4CLR: 1 | |
__OM uint32_t CH5CLR: 1 | |
__OM uint32_t CH6CLR: 1 | |
__OM uint32_t CH7CLR: 1 | |
__OM uint32_t CH8CLR: 1 | |
__OM uint32_t CH9CLR: 1 | |
__OM uint32_t CH10CLR: 1 | |
__OM uint32_t CH11CLR: 1 | |
__OM uint32_t CH12CLR: 1 | |
__OM uint32_t CH13CLR: 1 | |
__OM uint32_t CH14CLR: 1 | |
__OM uint32_t CH15CLR: 1 | |
__OM uint32_t CH16CLR: 1 | |
__OM uint32_t CH17CLR: 1 | |
__OM uint32_t CH18CLR: 1 | |
__OM uint32_t CH19CLR: 1 | |
uint32_t __pad0__: 12 | |
} bit | |
} | CHSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CH0SET: 1 | |
__OM uint32_t CH1SET: 1 | |
__OM uint32_t CH2SET: 1 | |
__OM uint32_t CH3SET: 1 | |
__OM uint32_t CH4SET: 1 | |
__OM uint32_t CH5SET: 1 | |
__OM uint32_t CH6SET: 1 | |
__OM uint32_t CH7SET: 1 | |
__OM uint32_t CH8SET: 1 | |
__OM uint32_t CH9SET: 1 | |
__OM uint32_t CH10SET: 1 | |
__OM uint32_t CH11SET: 1 | |
__OM uint32_t CH12SET: 1 | |
__OM uint32_t CH13SET: 1 | |
__OM uint32_t CH14SET: 1 | |
__OM uint32_t CH15SET: 1 | |
__OM uint32_t CH16SET: 1 | |
__OM uint32_t CH17SET: 1 | |
__OM uint32_t CH18SET: 1 | |
__OM uint32_t CH19SET: 1 | |
uint32_t __pad0__: 12 | |
} bit | |
} | CHSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALEN0: 1 | |
__IOM uint32_t CALEN1: 1 | |
__IOM uint32_t CALEN2: 1 | |
__IOM uint32_t CALEN3: 1 | |
__IOM uint32_t CALEN4: 1 | |
__IOM uint32_t CALEN5: 1 | |
__IOM uint32_t CALEN6: 1 | |
__IOM uint32_t CALEN7: 1 | |
__IOM uint32_t CALEN8: 1 | |
__IOM uint32_t CALEN9: 1 | |
__IOM uint32_t CALEN10: 1 | |
__IOM uint32_t CALEN11: 1 | |
__IOM uint32_t CALEN12: 1 | |
__IOM uint32_t CALEN13: 1 | |
__IOM uint32_t CALEN14: 1 | |
__IOM uint32_t CALEN15: 1 | |
__IOM uint32_t CALEN16: 1 | |
__IOM uint32_t CALEN17: 1 | |
__IOM uint32_t CALEN18: 1 | |
__IOM uint32_t CALEN19: 1 | |
__IOM uint32_t CALEN20: 1 | |
__IOM uint32_t CALEN21: 1 | |
__IOM uint32_t CALEN22: 1 | |
__IOM uint32_t CALEN23: 1 | |
__IOM uint32_t CALEN24: 1 | |
__IOM uint32_t CALEN25: 1 | |
__IOM uint32_t CALEN26: 1 | |
uint32_t __pad0__: 5 | |
} bit | |
} | CALEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALPEN0: 1 | |
__IOM uint32_t CALPEN1: 1 | |
__IOM uint32_t CALPEN2: 1 | |
__IOM uint32_t CALPEN3: 1 | |
__IOM uint32_t CALPEN4: 1 | |
__IOM uint32_t CALPEN5: 1 | |
__IOM uint32_t CALPEN6: 1 | |
__IOM uint32_t CALPEN7: 1 | |
__IOM uint32_t CALPEN8: 1 | |
__IOM uint32_t CALPEN9: 1 | |
__IOM uint32_t CALPEN10: 1 | |
__IOM uint32_t CALPEN11: 1 | |
__IOM uint32_t CALPEN12: 1 | |
__IOM uint32_t CALPEN13: 1 | |
__IOM uint32_t CALPEN14: 1 | |
__IOM uint32_t CALPEN15: 1 | |
__IOM uint32_t CALPEN16: 1 | |
__IOM uint32_t CALPEN17: 1 | |
__IOM uint32_t CALPEN18: 1 | |
__IOM uint32_t CALPEN19: 1 | |
__IOM uint32_t CALPEN20: 1 | |
__IOM uint32_t CALPEN21: 1 | |
__IOM uint32_t CALPEN22: 1 | |
__IOM uint32_t CALPEN23: 1 | |
__IOM uint32_t CALPEN24: 1 | |
__IOM uint32_t CALPEN25: 1 | |
__IOM uint32_t CALPEN26: 1 | |
uint32_t __pad0__: 5 | |
} bit | |
} | CALPEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t COEF_A0: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t COEF_A1: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t COEF_A2: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t COEF_A3: 2 | |
uint32_t __pad3__: 18 | |
} bit | |
} | FILTCFG |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL2 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t FIL0: 1 | |
__IOM uint32_t FIL1: 1 | |
__IOM uint32_t FIL2: 1 | |
__IOM uint32_t FIL3: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | FILSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t FIL0CLR: 1 | |
__OM uint32_t FIL1CLR: 1 | |
__OM uint32_t FIL2CLR: 1 | |
__OM uint32_t FIL3CLR: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | FILSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t FIL0SET: 1 | |
__OM uint32_t FIL1SET: 1 | |
__OM uint32_t FIL2SET: 1 | |
__OM uint32_t FIL3SET: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | FILSTATSET |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES2 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES3 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES4 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES5 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES6 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES7 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES8 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES9 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES10 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES11 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES12 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES13 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES14 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES15 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES16 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES17 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES18 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CMP_LO0_STS: 1 | |
__IOM uint32_t CMP_LO1_STS: 1 | |
__IOM uint32_t CMP_LO2_STS: 1 | |
__IOM uint32_t CMP_LO3_STS: 1 | |
__IOM uint32_t CMP_LO0_IS: 1 | |
__IOM uint32_t CMP_LO1_IS: 1 | |
__IOM uint32_t CMP_LO2_IS: 1 | |
__IOM uint32_t CMP_LO3_IS: 1 | |
__IM uint32_t CMP_LO: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CMP_UP0_STS: 1 | |
__IOM uint32_t CMP_UP1_STS: 1 | |
__IOM uint32_t CMP_UP2_STS: 1 | |
__IOM uint32_t CMP_UP3_STS: 1 | |
__IOM uint32_t CMP_UP0_IS: 1 | |
__IOM uint32_t CMP_UP1_IS: 1 | |
__IOM uint32_t CMP_UP2_IS: 1 | |
__IOM uint32_t CMP_UP3_IS: 1 | |
__IM uint32_t CMP_UP: 4 | |
uint32_t __pad1__: 4 | |
} bit | |
} | CMPSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CMP_LO0_STSCLR: 1 | |
__OM uint32_t CMP_LO1_STSCLR: 1 | |
__OM uint32_t CMP_LO2_STSCLR: 1 | |
__OM uint32_t CMP_LO3_STSCLR: 1 | |
__OM uint32_t CMP_LO0_ISCLR: 1 | |
__OM uint32_t CMP_LO1_ISCLR: 1 | |
__OM uint32_t CMP_LO2_ISCLR: 1 | |
__OM uint32_t CMP_LO3_ISCLR: 1 | |
uint32_t __pad0__: 8 | |
__OM uint32_t CMP_UP0_STSCLR: 1 | |
__OM uint32_t CMP_UP1_STSCLR: 1 | |
__OM uint32_t CMP_UP2_STSCLR: 1 | |
__OM uint32_t CMP_UP3_STSCLR: 1 | |
__OM uint32_t CMP_UP0_ISCLR: 1 | |
__OM uint32_t CMP_UP1_ISCLR: 1 | |
__OM uint32_t CMP_UP2_ISCLR: 1 | |
__OM uint32_t CMP_UP3_ISCLR: 1 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CMPSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CMP_LO0_STSSET: 1 | |
__OM uint32_t CMP_LO1_STSSET: 1 | |
__OM uint32_t CMP_LO2_STSSET: 1 | |
__OM uint32_t CMP_LO3_STSSET: 1 | |
__OM uint32_t CMP_LO0_ISSET: 1 | |
__OM uint32_t CMP_LO1_ISSET: 1 | |
__OM uint32_t CMP_LO2_ISSET: 1 | |
__OM uint32_t CMP_LO3_ISSET: 1 | |
uint32_t __pad0__: 8 | |
__OM uint32_t CMP_UP0_STSSET: 1 | |
__OM uint32_t CMP_UP1_STSSET: 1 | |
__OM uint32_t CMP_UP2_STSSET: 1 | |
__OM uint32_t CMP_UP3_STSSET: 1 | |
__OM uint32_t CMP_UP0_ISSET: 1 | |
__OM uint32_t CMP_UP1_ISSET: 1 | |
__OM uint32_t CMP_UP2_ISSET: 1 | |
__OM uint32_t CMP_UP3_ISSET: 1 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CMPSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IEN_CH0: 1 | |
__IOM uint32_t IEN_CH1: 1 | |
__IOM uint32_t IEN_CH2: 1 | |
__IOM uint32_t IEN_CH3: 1 | |
__IOM uint32_t IEN_CH4: 1 | |
__IOM uint32_t IEN_CH5: 1 | |
__IOM uint32_t IEN_CH6: 1 | |
__IOM uint32_t IEN_CH7: 1 | |
__IOM uint32_t IEN_CH8: 1 | |
__IOM uint32_t IEN_CH9: 1 | |
__IOM uint32_t IEN_CH10: 1 | |
__IOM uint32_t IEN_CH11: 1 | |
__IOM uint32_t IEN_CH12: 1 | |
__IOM uint32_t IEN_CH13: 1 | |
__IOM uint32_t IEN_CH14: 1 | |
__IOM uint32_t IEN_CH15: 1 | |
__IOM uint32_t IEN_CH16: 1 | |
__IOM uint32_t IEN_CH17: 1 | |
__IOM uint32_t IEN_CH18: 1 | |
__IOM uint32_t IEN_CH19: 1 | |
__IOM uint32_t IEN_SQ0: 1 | |
__IOM uint32_t IEN_SQ1: 1 | |
__IOM uint32_t IEN_SQ2: 1 | |
__IOM uint32_t IEN_SQ3: 1 | |
__IOM uint32_t IEN_LO0: 1 | |
__IOM uint32_t IEN_LO1: 1 | |
__IOM uint32_t IEN_LO2: 1 | |
__IOM uint32_t IEN_LO3: 1 | |
__IOM uint32_t IEN_UP0: 1 | |
__IOM uint32_t IEN_UP1: 1 | |
__IOM uint32_t IEN_UP2: 1 | |
__IOM uint32_t IEN_UP3: 1 | |
} bit | |
} | IEN0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IEN_COLL0: 1 | |
__IOM uint32_t IEN_COLL1: 1 | |
__IOM uint32_t IEN_COLL2: 1 | |
__IOM uint32_t IEN_COLL3: 1 | |
__IOM uint32_t IEN_WFR0: 1 | |
__IOM uint32_t IEN_WFR1: 1 | |
__IOM uint32_t IEN_WFR2: 1 | |
__IOM uint32_t IEN_WFR3: 1 | |
__IOM uint32_t IEN_EOC_FAIL: 1 | |
uint32_t __pad0__: 23 | |
} bit | |
} | IEN1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CH0: 2 | |
__IOM uint32_t INP_CH1: 2 | |
__IOM uint32_t INP_CH2: 2 | |
__IOM uint32_t INP_CH3: 2 | |
__IOM uint32_t INP_CH4: 2 | |
__IOM uint32_t INP_CH5: 2 | |
__IOM uint32_t INP_CH6: 2 | |
__IOM uint32_t INP_CH7: 2 | |
__IOM uint32_t INP_CH8: 2 | |
__IOM uint32_t INP_CH9: 2 | |
__IOM uint32_t INP_CH10: 2 | |
__IOM uint32_t INP_CH11: 2 | |
__IOM uint32_t INP_CH12: 2 | |
__IOM uint32_t INP_CH13: 2 | |
__IOM uint32_t INP_CH14: 2 | |
__IOM uint32_t INP_CH15: 2 | |
} bit | |
} | INP0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CH16: 2 | |
__IOM uint32_t INP_CH17: 2 | |
__IOM uint32_t INP_CH18: 2 | |
__IOM uint32_t INP_CH19: 2 | |
__IOM uint32_t INP_EOC_FAIL: 2 | |
uint32_t __pad0__: 22 | |
} bit | |
} | INP1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CMP_LO0: 2 | |
__IOM uint32_t INP_CMP_LO1: 2 | |
__IOM uint32_t INP_CMP_LO2: 2 | |
__IOM uint32_t INP_CMP_LO3: 2 | |
__IOM uint32_t INP_CMP_UP0: 2 | |
__IOM uint32_t INP_CMP_UP1: 2 | |
__IOM uint32_t INP_CMP_UP2: 2 | |
__IOM uint32_t INP_CMP_UP3: 2 | |
uint32_t __pad0__: 16 | |
} bit | |
} | INP2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_SQ0: 2 | |
__IOM uint32_t INP_SQ1: 2 | |
__IOM uint32_t INP_SQ2: 2 | |
__IOM uint32_t INP_SQ3: 2 | |
__IOM uint32_t INP_COLL0: 2 | |
__IOM uint32_t INP_COLL1: 2 | |
__IOM uint32_t INP_COLL2: 2 | |
__IOM uint32_t INP_COLL3: 2 | |
__IOM uint32_t INP_WFR0: 2 | |
__IOM uint32_t INP_WFR1: 2 | |
__IOM uint32_t INP_WFR2: 2 | |
__IOM uint32_t INP_WFR3: 2 | |
uint32_t __pad0__: 8 | |
} bit | |
} | INP3 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t DIGOUT: 20 | |
uint32_t __pad0__: 12 | |
} bit | |
} | TST0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SEL: 2 | |
__IOM uint32_t MSB_SEL: 1 | |
__IOM uint32_t MSB_EN4CONV: 1 | |
__IOM uint32_t MSB_EN4BIST: 1 | |
__IOM uint32_t MSB_EN4PCAL: 1 | |
__IOM uint32_t MSB_SCAL_CFG: 2 | |
__IOM uint32_t SESP_ANA_DEL_OFF: 1 | |
__IOM uint32_t SESP_DIG_SPREAD_SHORT: 1 | |
__IOM uint32_t CAL_VAL: 6 | |
__IOM uint32_t CAL_WRITE: 1 | |
__IOM uint32_t CAL_OFF_FILTER_DIS: 1 | |
__IOM uint32_t HV_SWITCH_TIME: 3 | |
__IOM uint32_t DISCHARGE_CXXXX: 1 | |
__IOM uint32_t DISCHARGE_FILTER: 2 | |
__IOM uint32_t HV_FRAME: 1 | |
__IOM uint32_t HV_PRE_TIME: 2 | |
__IOM uint32_t BIST_SAMP_VAL_WRITE: 1 | |
__IOM uint32_t BWD_CURR_TEST_EN: 1 | |
uint32_t __pad0__: 3 | |
} bit | |
} | TST1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BIST_TRACK_SEL: 5 | |
__IOM uint32_t BIST_CAL_SEL: 6 | |
__IOM uint32_t TST_STRESS: 1 | |
__IOM uint32_t BWD_CFG: 2 | |
__IOM uint32_t BWD_HIGH_CUR: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BWD_TST_CH_SEL: 5 | |
__IOM uint32_t BWD_SER: 1 | |
uint32_t __pad1__: 10 | |
} bit | |
} | TST2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t COMP_VAL: 14 | |
uint32_t __pad0__: 18 | |
} bit | |
} | TST3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ST_SQSEL: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t ST_TRGSEL: 3 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t ST_GTGSEL: 3 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t STE_SQSEL: 1 | |
__IOM uint32_t STE_TRGSEL: 1 | |
__IOM uint32_t STE_GTGSEL: 1 | |
uint32_t __pad3__: 1 | |
__OM uint32_t ST_SQSW: 1 | |
__OM uint32_t ST_TRGSW: 1 | |
__OM uint32_t ST_GTGSW: 1 | |
uint32_t __pad4__: 1 | |
__IOM uint32_t STE_SQ: 1 | |
__IOM uint32_t STE_TRG: 1 | |
__IOM uint32_t STE_GTG: 1 | |
uint32_t __pad5__: 9 | |
} bit | |
} | SHDCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTB_OUT0: 2 | |
__IOM uint32_t DTB_OUT1: 2 | |
__IOM uint32_t DTB_OUT2: 2 | |
uint32_t __pad0__: 6 | |
__IOM uint32_t START_ADC_DTB: 2 | |
uint32_t __pad1__: 17 | |
__IOM uint32_t TEST_CTRL: 1 | |
} bit | |
} | TCR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t EOC_FAIL_IS: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | CONVSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t EOC_FAIL_CLR: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | CONVSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t EOC_FAIL_SET: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | CONVSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t EN: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t ISTE: 1 | |
uint32_t __pad1__: 26 | |
} bit | |
} | GLOBCONF |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CLKDIV: 4 | |
uint32_t __pad0__: 28 | |
} bit | |
} | CLKCON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SUSEN: 1 | |
__IOM uint32_t SUSMOD: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | SUSCTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t STAT: 1 | |
__IM uint32_t READY: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | SUSSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SLOTS: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SQREP: 2 | |
__IOM uint32_t COLLCFG: 1 | |
__IOM uint32_t WFRCFG: 1 | |
__IOM uint32_t TRGSEL: 4 | |
__IOM uint32_t GTSEL: 2 | |
__OM uint32_t TRGSW: 1 | |
__IOM uint32_t GTSW: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | SQCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHSEL0: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHSEL1: 5 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t CHSEL2: 5 | |
uint32_t __pad2__: 3 | |
__IOM uint32_t CHSEL3: 5 | |
uint32_t __pad3__: 3 | |
} bit | |
} | SQSLOT3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0: 1 | |
__IOM uint32_t SQ1: 1 | |
__IOM uint32_t SQ2: 1 | |
__IOM uint32_t SQ3: 1 | |
__IOM uint32_t WFR0: 1 | |
__IOM uint32_t WFR1: 1 | |
__IOM uint32_t WFR2: 1 | |
__IOM uint32_t WFR3: 1 | |
__IOM uint32_t COLL0: 1 | |
__IOM uint32_t COLL1: 1 | |
__IOM uint32_t COLL2: 1 | |
__IOM uint32_t COLL3: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t SQNUM: 3 | |
uint32_t __pad1__: 13 | |
} bit | |
} | SQSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0CLR: 1 | |
__IOM uint32_t SQ1CLR: 1 | |
__IOM uint32_t SQ2CLR: 1 | |
__IOM uint32_t SQ3CLR: 1 | |
__IOM uint32_t WFR0CLR: 1 | |
__IOM uint32_t WFR1CLR: 1 | |
__IOM uint32_t WFR2CLR: 1 | |
__IOM uint32_t WFR3CLR: 1 | |
__IOM uint32_t COLL0CLR: 1 | |
__IOM uint32_t COLL1CLR: 1 | |
__IOM uint32_t COLL2CLR: 1 | |
__IOM uint32_t COLL3CLR: 1 | |
uint32_t __pad0__: 20 | |
} bit | |
} | SQSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SQ0SET: 1 | |
__IOM uint32_t SQ1SET: 1 | |
__IOM uint32_t SQ2SET: 1 | |
__IOM uint32_t SQ3SET: 1 | |
__IOM uint32_t WFR0SET: 1 | |
__IOM uint32_t WFR1SET: 1 | |
__IOM uint32_t WFR2SET: 1 | |
__IOM uint32_t WFR3SET: 1 | |
__IOM uint32_t COLL0SET: 1 | |
__IOM uint32_t COLL1SET: 1 | |
__IOM uint32_t COLL2SET: 1 | |
__IOM uint32_t COLL3SET: 1 | |
uint32_t __pad0__: 20 | |
} bit | |
} | SQSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INSEL: 5 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t CHREP: 4 | |
uint32_t __pad1__: 4 | |
__IOM uint32_t FILSEL: 3 | |
__IOM uint32_t CMPSEL: 3 | |
__IOM uint32_t CLASSEL: 2 | |
uint32_t __pad2__: 8 | |
} bit | |
} | CHCFG19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CH0: 1 | |
__IOM uint32_t CH1: 1 | |
__IOM uint32_t CH2: 1 | |
__IOM uint32_t CH3: 1 | |
__IOM uint32_t CH4: 1 | |
__IOM uint32_t CH5: 1 | |
__IOM uint32_t CH6: 1 | |
__IOM uint32_t CH7: 1 | |
__IOM uint32_t CH8: 1 | |
__IOM uint32_t CH9: 1 | |
__IOM uint32_t CH10: 1 | |
__IOM uint32_t CH11: 1 | |
__IOM uint32_t CH12: 1 | |
__IOM uint32_t CH13: 1 | |
__IOM uint32_t CH14: 1 | |
__IOM uint32_t CH15: 1 | |
__IOM uint32_t CH16: 1 | |
__IOM uint32_t CH17: 1 | |
__IOM uint32_t CH18: 1 | |
__IOM uint32_t CH19: 1 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CHNUM: 5 | |
uint32_t __pad1__: 3 | |
} bit | |
} | CHSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CH0CLR: 1 | |
__OM uint32_t CH1CLR: 1 | |
__OM uint32_t CH2CLR: 1 | |
__OM uint32_t CH3CLR: 1 | |
__OM uint32_t CH4CLR: 1 | |
__OM uint32_t CH5CLR: 1 | |
__OM uint32_t CH6CLR: 1 | |
__OM uint32_t CH7CLR: 1 | |
__OM uint32_t CH8CLR: 1 | |
__OM uint32_t CH9CLR: 1 | |
__OM uint32_t CH10CLR: 1 | |
__OM uint32_t CH11CLR: 1 | |
__OM uint32_t CH12CLR: 1 | |
__OM uint32_t CH13CLR: 1 | |
__OM uint32_t CH14CLR: 1 | |
__OM uint32_t CH15CLR: 1 | |
__OM uint32_t CH16CLR: 1 | |
__OM uint32_t CH17CLR: 1 | |
__OM uint32_t CH18CLR: 1 | |
__OM uint32_t CH19CLR: 1 | |
uint32_t __pad0__: 12 | |
} bit | |
} | CHSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CH0SET: 1 | |
__OM uint32_t CH1SET: 1 | |
__OM uint32_t CH2SET: 1 | |
__OM uint32_t CH3SET: 1 | |
__OM uint32_t CH4SET: 1 | |
__OM uint32_t CH5SET: 1 | |
__OM uint32_t CH6SET: 1 | |
__OM uint32_t CH7SET: 1 | |
__OM uint32_t CH8SET: 1 | |
__OM uint32_t CH9SET: 1 | |
__OM uint32_t CH10SET: 1 | |
__OM uint32_t CH11SET: 1 | |
__OM uint32_t CH12SET: 1 | |
__OM uint32_t CH13SET: 1 | |
__OM uint32_t CH14SET: 1 | |
__OM uint32_t CH15SET: 1 | |
__OM uint32_t CH16SET: 1 | |
__OM uint32_t CH17SET: 1 | |
__OM uint32_t CH18SET: 1 | |
__OM uint32_t CH19SET: 1 | |
uint32_t __pad0__: 12 | |
} bit | |
} | CHSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TCONF: 2 | |
__IOM uint32_t OVERS: 2 | |
__IOM uint32_t STC: 4 | |
__IOM uint32_t SESP: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MSBD: 1 | |
__IOM uint32_t PCAL: 1 | |
__IOM uint32_t BWD: 2 | |
__IOM uint32_t BWD_HI_CUR: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CONVCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALEN0: 1 | |
__IOM uint32_t CALEN1: 1 | |
__IOM uint32_t CALEN2: 1 | |
__IOM uint32_t CALEN3: 1 | |
__IOM uint32_t CALEN4: 1 | |
__IOM uint32_t CALEN5: 1 | |
__IOM uint32_t CALEN6: 1 | |
__IOM uint32_t CALEN7: 1 | |
__IOM uint32_t CALEN8: 1 | |
__IOM uint32_t CALEN9: 1 | |
__IOM uint32_t CALEN10: 1 | |
__IOM uint32_t CALEN11: 1 | |
__IOM uint32_t CALEN12: 1 | |
__IOM uint32_t CALEN13: 1 | |
__IOM uint32_t CALEN14: 1 | |
__IOM uint32_t CALEN15: 1 | |
__IOM uint32_t CALEN16: 1 | |
__IOM uint32_t CALEN17: 1 | |
__IOM uint32_t CALEN18: 1 | |
__IOM uint32_t CALEN19: 1 | |
__IOM uint32_t CALEN20: 1 | |
__IOM uint32_t CALEN21: 1 | |
__IOM uint32_t CALEN22: 1 | |
__IOM uint32_t CALEN23: 1 | |
__IOM uint32_t CALEN24: 1 | |
__IOM uint32_t CALEN25: 1 | |
__IOM uint32_t CALEN26: 1 | |
uint32_t __pad0__: 5 | |
} bit | |
} | CALEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALPEN0: 1 | |
__IOM uint32_t CALPEN1: 1 | |
__IOM uint32_t CALPEN2: 1 | |
__IOM uint32_t CALPEN3: 1 | |
__IOM uint32_t CALPEN4: 1 | |
__IOM uint32_t CALPEN5: 1 | |
__IOM uint32_t CALPEN6: 1 | |
__IOM uint32_t CALPEN7: 1 | |
__IOM uint32_t CALPEN8: 1 | |
__IOM uint32_t CALPEN9: 1 | |
__IOM uint32_t CALPEN10: 1 | |
__IOM uint32_t CALPEN11: 1 | |
__IOM uint32_t CALPEN12: 1 | |
__IOM uint32_t CALPEN13: 1 | |
__IOM uint32_t CALPEN14: 1 | |
__IOM uint32_t CALPEN15: 1 | |
__IOM uint32_t CALPEN16: 1 | |
__IOM uint32_t CALPEN17: 1 | |
__IOM uint32_t CALPEN18: 1 | |
__IOM uint32_t CALPEN19: 1 | |
__IOM uint32_t CALPEN20: 1 | |
__IOM uint32_t CALPEN21: 1 | |
__IOM uint32_t CALPEN22: 1 | |
__IOM uint32_t CALPEN23: 1 | |
__IOM uint32_t CALPEN24: 1 | |
__IOM uint32_t CALPEN25: 1 | |
__IOM uint32_t CALPEN26: 1 | |
uint32_t __pad0__: 5 | |
} bit | |
} | CALPEN |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t COEF_A0: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t COEF_A1: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t COEF_A2: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t COEF_A3: 2 | |
uint32_t __pad3__: 18 | |
} bit | |
} | FILTCFG |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL2 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t FILRESULT: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | FIL3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t FIL0: 1 | |
__IOM uint32_t FIL1: 1 | |
__IOM uint32_t FIL2: 1 | |
__IOM uint32_t FIL3: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | FILSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t FIL0CLR: 1 | |
__OM uint32_t FIL1CLR: 1 | |
__OM uint32_t FIL2CLR: 1 | |
__OM uint32_t FIL3CLR: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | FILSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t FIL0SET: 1 | |
__OM uint32_t FIL1SET: 1 | |
__OM uint32_t FIL2SET: 1 | |
__OM uint32_t FIL3SET: 1 | |
uint32_t __pad0__: 28 | |
} bit | |
} | FILSTATSET |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES2 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES3 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES4 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES5 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES6 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES7 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES8 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES9 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES10 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES11 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES12 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES13 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES14 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES15 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES16 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES17 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES18 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RESULT: 14 | |
uint32_t __pad0__: 1 | |
__IM uint32_t VALID: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | RES19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LOWER: 8 | |
__IOM uint32_t INP_SEL: 1 | |
uint32_t __pad0__: 3 | |
__IOM uint32_t HYST_LO: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t UPPER: 8 | |
__IOM uint32_t BLANK_TIME: 3 | |
__IOM uint32_t RST_BLANK_TIME: 1 | |
__IOM uint32_t HYST_UP: 2 | |
__IOM uint32_t MODE: 2 | |
} bit | |
} | CMPCFG3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CMP_LO0_STS: 1 | |
__IOM uint32_t CMP_LO1_STS: 1 | |
__IOM uint32_t CMP_LO2_STS: 1 | |
__IOM uint32_t CMP_LO3_STS: 1 | |
__IOM uint32_t CMP_LO0_IS: 1 | |
__IOM uint32_t CMP_LO1_IS: 1 | |
__IOM uint32_t CMP_LO2_IS: 1 | |
__IOM uint32_t CMP_LO3_IS: 1 | |
__IM uint32_t CMP_LO: 4 | |
uint32_t __pad0__: 4 | |
__IOM uint32_t CMP_UP0_STS: 1 | |
__IOM uint32_t CMP_UP1_STS: 1 | |
__IOM uint32_t CMP_UP2_STS: 1 | |
__IOM uint32_t CMP_UP3_STS: 1 | |
__IOM uint32_t CMP_UP0_IS: 1 | |
__IOM uint32_t CMP_UP1_IS: 1 | |
__IOM uint32_t CMP_UP2_IS: 1 | |
__IOM uint32_t CMP_UP3_IS: 1 | |
__IM uint32_t CMP_UP: 4 | |
uint32_t __pad1__: 4 | |
} bit | |
} | CMPSTAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CMP_LO0_STSCLR: 1 | |
__OM uint32_t CMP_LO1_STSCLR: 1 | |
__OM uint32_t CMP_LO2_STSCLR: 1 | |
__OM uint32_t CMP_LO3_STSCLR: 1 | |
__OM uint32_t CMP_LO0_ISCLR: 1 | |
__OM uint32_t CMP_LO1_ISCLR: 1 | |
__OM uint32_t CMP_LO2_ISCLR: 1 | |
__OM uint32_t CMP_LO3_ISCLR: 1 | |
uint32_t __pad0__: 8 | |
__OM uint32_t CMP_UP0_STSCLR: 1 | |
__OM uint32_t CMP_UP1_STSCLR: 1 | |
__OM uint32_t CMP_UP2_STSCLR: 1 | |
__OM uint32_t CMP_UP3_STSCLR: 1 | |
__OM uint32_t CMP_UP0_ISCLR: 1 | |
__OM uint32_t CMP_UP1_ISCLR: 1 | |
__OM uint32_t CMP_UP2_ISCLR: 1 | |
__OM uint32_t CMP_UP3_ISCLR: 1 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CMPSTATCLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CMP_LO0_STSSET: 1 | |
__OM uint32_t CMP_LO1_STSSET: 1 | |
__OM uint32_t CMP_LO2_STSSET: 1 | |
__OM uint32_t CMP_LO3_STSSET: 1 | |
__OM uint32_t CMP_LO0_ISSET: 1 | |
__OM uint32_t CMP_LO1_ISSET: 1 | |
__OM uint32_t CMP_LO2_ISSET: 1 | |
__OM uint32_t CMP_LO3_ISSET: 1 | |
uint32_t __pad0__: 8 | |
__OM uint32_t CMP_UP0_STSSET: 1 | |
__OM uint32_t CMP_UP1_STSSET: 1 | |
__OM uint32_t CMP_UP2_STSSET: 1 | |
__OM uint32_t CMP_UP3_STSSET: 1 | |
__OM uint32_t CMP_UP0_ISSET: 1 | |
__OM uint32_t CMP_UP1_ISSET: 1 | |
__OM uint32_t CMP_UP2_ISSET: 1 | |
__OM uint32_t CMP_UP3_ISSET: 1 | |
uint32_t __pad1__: 8 | |
} bit | |
} | CMPSTATSET |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IEN_CH0: 1 | |
__IOM uint32_t IEN_CH1: 1 | |
__IOM uint32_t IEN_CH2: 1 | |
__IOM uint32_t IEN_CH3: 1 | |
__IOM uint32_t IEN_CH4: 1 | |
__IOM uint32_t IEN_CH5: 1 | |
__IOM uint32_t IEN_CH6: 1 | |
__IOM uint32_t IEN_CH7: 1 | |
__IOM uint32_t IEN_CH8: 1 | |
__IOM uint32_t IEN_CH9: 1 | |
__IOM uint32_t IEN_CH10: 1 | |
__IOM uint32_t IEN_CH11: 1 | |
__IOM uint32_t IEN_CH12: 1 | |
__IOM uint32_t IEN_CH13: 1 | |
__IOM uint32_t IEN_CH14: 1 | |
__IOM uint32_t IEN_CH15: 1 | |
__IOM uint32_t IEN_CH16: 1 | |
__IOM uint32_t IEN_CH17: 1 | |
__IOM uint32_t IEN_CH18: 1 | |
__IOM uint32_t IEN_CH19: 1 | |
__IOM uint32_t IEN_SQ0: 1 | |
__IOM uint32_t IEN_SQ1: 1 | |
__IOM uint32_t IEN_SQ2: 1 | |
__IOM uint32_t IEN_SQ3: 1 | |
__IOM uint32_t IEN_LO0: 1 | |
__IOM uint32_t IEN_LO1: 1 | |
__IOM uint32_t IEN_LO2: 1 | |
__IOM uint32_t IEN_LO3: 1 | |
__IOM uint32_t IEN_UP0: 1 | |
__IOM uint32_t IEN_UP1: 1 | |
__IOM uint32_t IEN_UP2: 1 | |
__IOM uint32_t IEN_UP3: 1 | |
} bit | |
} | IEN0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IEN_COLL0: 1 | |
__IOM uint32_t IEN_COLL1: 1 | |
__IOM uint32_t IEN_COLL2: 1 | |
__IOM uint32_t IEN_COLL3: 1 | |
__IOM uint32_t IEN_WFR0: 1 | |
__IOM uint32_t IEN_WFR1: 1 | |
__IOM uint32_t IEN_WFR2: 1 | |
__IOM uint32_t IEN_WFR3: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | IEN1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CH0: 2 | |
__IOM uint32_t INP_CH1: 2 | |
__IOM uint32_t INP_CH2: 2 | |
__IOM uint32_t INP_CH3: 2 | |
__IOM uint32_t INP_CH4: 2 | |
__IOM uint32_t INP_CH5: 2 | |
__IOM uint32_t INP_CH6: 2 | |
__IOM uint32_t INP_CH7: 2 | |
__IOM uint32_t INP_CH8: 2 | |
__IOM uint32_t INP_CH9: 2 | |
__IOM uint32_t INP_CH10: 2 | |
__IOM uint32_t INP_CH11: 2 | |
__IOM uint32_t INP_CH12: 2 | |
__IOM uint32_t INP_CH13: 2 | |
__IOM uint32_t INP_CH14: 2 | |
__IOM uint32_t INP_CH15: 2 | |
} bit | |
} | INP0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CH16: 2 | |
__IOM uint32_t INP_CH17: 2 | |
__IOM uint32_t INP_CH18: 2 | |
__IOM uint32_t INP_CH19: 2 | |
uint32_t __pad0__: 24 | |
} bit | |
} | INP1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_CMP_LO0: 2 | |
__IOM uint32_t INP_CMP_LO1: 2 | |
__IOM uint32_t INP_CMP_LO2: 2 | |
__IOM uint32_t INP_CMP_LO3: 2 | |
__IOM uint32_t INP_CMP_UP0: 2 | |
__IOM uint32_t INP_CMP_UP1: 2 | |
__IOM uint32_t INP_CMP_UP2: 2 | |
__IOM uint32_t INP_CMP_UP3: 2 | |
uint32_t __pad0__: 16 | |
} bit | |
} | INP2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INP_SQ0: 2 | |
__IOM uint32_t INP_SQ1: 2 | |
__IOM uint32_t INP_SQ2: 2 | |
__IOM uint32_t INP_SQ3: 2 | |
__IOM uint32_t INP_COLL0: 2 | |
__IOM uint32_t INP_COLL1: 2 | |
__IOM uint32_t INP_COLL2: 2 | |
__IOM uint32_t INP_COLL3: 2 | |
__IOM uint32_t INP_WFR0: 2 | |
__IOM uint32_t INP_WFR1: 2 | |
__IOM uint32_t INP_WFR2: 2 | |
__IOM uint32_t INP_WFR3: 2 | |
uint32_t __pad0__: 8 | |
} bit | |
} | INP3 |
__IM uint32_t | RESERVED [4] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ST_SQSEL: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t ST_TRGSEL: 3 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t ST_GTGSEL: 3 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t STE_SQSEL: 1 | |
__IOM uint32_t STE_TRGSEL: 1 | |
__IOM uint32_t STE_GTGSEL: 1 | |
uint32_t __pad3__: 1 | |
__OM uint32_t ST_SQSW: 1 | |
__OM uint32_t ST_TRGSW: 1 | |
__OM uint32_t ST_GTGSW: 1 | |
uint32_t __pad4__: 1 | |
__IOM uint32_t STE_SQ: 1 | |
__IOM uint32_t STE_TRG: 1 | |
__IOM uint32_t STE_GTG: 1 | |
uint32_t __pad5__: 9 | |
} bit | |
} | SHDCTR |
__IM uint32_t | RESERVED1 [4] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CALOFFS: 6 | |
uint32_t __pad0__: 10 | |
__IOM uint32_t CALGAIN: 10 | |
uint32_t __pad1__: 6 | |
} bit | |
} | CALAI26 |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
uint32_t __pad4__ |
uint32_t __pad5__ |
__IOM uint32_t BIST_CAL_SEL |
[10..5] BIST calibration array capacitor selection - connected to ADC12.tst_dig_i[39:34]
__IOM uint32_t BIST_SAMP_VAL_WRITE |
[27..27] Bist sample value write - connected to ADC12.tst_dig_i[27]
__IOM uint32_t BIST_TRACK_SEL |
[4..0] BIST tracking capacitor selection - connected to ADC12.tst_dig_i[33:29]
struct { ... } bit |
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__IOM uint32_t BLANK_TIME |
[26..24] Blank Time configuration
__IOM uint32_t BWD |
[13..12] BWD timing config
__IOM uint32_t BWD_CFG |
[13..12] Broken Wire Detection configuration
__IOM uint32_t BWD_CURR_TEST_EN |
[28..28] Broken Wire Detection current test enable - connected to ADC12.tst_dig_i[28]
__IOM uint32_t BWD_HI_CUR |
[14..14] BWD current configuration
__IOM uint32_t BWD_HIGH_CUR |
[14..14] Broken Wire Detection high current selection
__IOM uint32_t BWD_SER |
[21..21] Enable serial channel measurments for broken wire detection
__IOM uint32_t BWD_TST_CH_SEL |
[20..16] Broken Wire Detection channel select - connected to ADC12.tst_dig_i[69:40]
__IOM uint32_t CAL_OFF_FILTER_DIS |
[17..17] Offset Calibration Filter disable - connected to ADC12.tst_dig_i[17]
__IOM uint32_t CAL_VAL |
[15..10] Calibration Value - connected to ADC12.tst_dig_i[15:10]
__IOM uint32_t CAL_WRITE |
[16..16] Calibration write strobe - connected to ADC12.tst_dig_i[16]
union { ... } CALAI1 |
union { ... } CALAI1 |
union { ... } CALAI11 |
union { ... } CALAI11 |
union { ... } CALAI13 |
union { ... } CALAI13 |
union { ... } CALAI15 |
union { ... } CALAI15 |
union { ... } CALAI16 |
union { ... } CALAI16 |
union { ... } CALAI17 |
union { ... } CALAI17 |
union { ... } CALAI18 |
union { ... } CALAI18 |
union { ... } CALAI19 |
union { ... } CALAI19 |
union { ... } CALAI20 |
union { ... } CALAI20 |
union { ... } CALAI21 |
union { ... } CALAI21 |
union { ... } CALAI22 |
union { ... } CALAI22 |
union { ... } CALAI23 |
union { ... } CALAI23 |
union { ... } CALAI24 |
union { ... } CALAI24 |
union { ... } CALAI25 |
union { ... } CALAI25 |
union { ... } CALAI26 |
union { ... } CALAI26 |
union { ... } CALAI3 |
union { ... } CALAI3 |
union { ... } CALAI5 |
union { ... } CALAI5 |
union { ... } CALAI7 |
union { ... } CALAI7 |
union { ... } CALAI9 |
union { ... } CALAI9 |
union { ... } CALEN |
union { ... } CALEN |
__IOM uint32_t CALEN0 |
[0..0] Channel 0 Calibration Enable
__IOM uint32_t CALEN1 |
[1..1] Channel 1 Calibration Enable
__IOM uint32_t CALEN10 |
[10..10] Channel 10 Calibration Enable
__IOM uint32_t CALEN11 |
[11..11] Channel 11 Calibration Enable
__IOM uint32_t CALEN12 |
[12..12] Channel 12 Calibration Enable
__IOM uint32_t CALEN13 |
[13..13] Channel 13 Calibration Enable
__IOM uint32_t CALEN14 |
[14..14] Channel 14 Calibration Enable
__IOM uint32_t CALEN15 |
[15..15] Channel 15 Calibration Enable
__IOM uint32_t CALEN16 |
[16..16] Channel 16 Calibration Enable
__IOM uint32_t CALEN17 |
[17..17] Channel 17 Calibration Enable
__IOM uint32_t CALEN18 |
[18..18] Channel 18 Calibration Enable
__IOM uint32_t CALEN19 |
[19..19] Channel 19 Calibration Enable
__IOM uint32_t CALEN2 |
[2..2] Channel 2 Calibration Enable
__IOM uint32_t CALEN20 |
[20..20] Channel 20 Calibration Enable
__IOM uint32_t CALEN21 |
[21..21] Channel 21 Calibration Enable
__IOM uint32_t CALEN22 |
[22..22] Channel 22 Calibration Enable
__IOM uint32_t CALEN23 |
[23..23] Channel 23 Calibration Enable
__IOM uint32_t CALEN24 |
[24..24] Channel 24 Calibration Enable
__IOM uint32_t CALEN25 |
[25..25] Channel 25 Calibration Enable
__IOM uint32_t CALEN26 |
[26..26] Channel 26 Calibration Enable
__IOM uint32_t CALEN3 |
[3..3] Channel 3 Calibration Enable
__IOM uint32_t CALEN4 |
[4..4] Channel 4 Calibration Enable
__IOM uint32_t CALEN5 |
[5..5] Channel 5 Calibration Enable
__IOM uint32_t CALEN6 |
[6..6] Channel 6 Calibration Enable
__IOM uint32_t CALEN7 |
[7..7] Channel 7 Calibration Enable
__IOM uint32_t CALEN8 |
[8..8] Channel 8 Calibration Enable
__IOM uint32_t CALEN9 |
[9..9] Channel 9 Calibration Enable
__IOM uint32_t CALGAIN |
[25..16] Calibration Gain
__IOM uint32_t CALOFFS |
[5..0] Calibration Offset
union { ... } CALPEN |
union { ... } CALPEN |
__IOM uint32_t CALPEN0 |
[0..0] Channel 0 Calibration Protection
__IOM uint32_t CALPEN1 |
[1..1] Channel 1 Calibration Protection
__IOM uint32_t CALPEN10 |
[10..10] Channel 10 Calibration Protection
__IOM uint32_t CALPEN11 |
[11..11] Channel 11 Calibration Protection
__IOM uint32_t CALPEN12 |
[12..12] Channel 12 Calibration Protection
__IOM uint32_t CALPEN13 |
[13..13] Channel 13 Calibration Protection
__IOM uint32_t CALPEN14 |
[14..14] Channel 14 Calibration Protection
__IOM uint32_t CALPEN15 |
[15..15] Channel 15 Calibration Protection
__IOM uint32_t CALPEN16 |
[16..16] Channel 16 Calibration Protection
__IOM uint32_t CALPEN17 |
[17..17] Channel 17 Calibration Protection
__IOM uint32_t CALPEN18 |
[18..18] Channel 18 Calibration Protection
__IOM uint32_t CALPEN19 |
[19..19] Channel 19 Calibration Protection
__IOM uint32_t CALPEN2 |
[2..2] Channel 2 Calibration Protection
__IOM uint32_t CALPEN20 |
[20..20] Channel 20 Calibration Protection
__IOM uint32_t CALPEN21 |
[21..21] Channel 21 Calibration Protection
__IOM uint32_t CALPEN22 |
[22..22] Channel 22 Calibration Protection
__IOM uint32_t CALPEN23 |
[23..23] Channel 23 Calibration Protection
__IOM uint32_t CALPEN24 |
[24..24] Channel 24 Calibration Protection
__IOM uint32_t CALPEN25 |
[25..25] Channel 25 Calibration Protection
__IOM uint32_t CALPEN26 |
[26..26] Channel 26 Calibration Protection
__IOM uint32_t CALPEN3 |
[3..3] Channel 3 Calibration Protection
__IOM uint32_t CALPEN4 |
[4..4] Channel 4 Calibration Protection
__IOM uint32_t CALPEN5 |
[5..5] Channel 5 Calibration Protection
__IOM uint32_t CALPEN6 |
[6..6] Channel 6 Calibration Protection
__IOM uint32_t CALPEN7 |
[7..7] Channel 7 Calibration Protection
__IOM uint32_t CALPEN8 |
[8..8] Channel 8 Calibration Protection
__IOM uint32_t CALPEN9 |
[9..9] Channel 9 Calibration Protection
__IOM uint32_t CH0 |
[0..0] Channel 0 Status
__OM uint32_t CH0CLR |
[0..0] Channel 0 Status clear flag
__OM uint32_t CH0SET |
[0..0] Channel 0 Status set flag
__IOM uint32_t CH1 |
[1..1] Channel 1 Status
__IOM uint32_t CH10 |
[10..10] Channel 10 Status
__OM uint32_t CH10CLR |
[10..10] Channel 10 Status clear flag
__OM uint32_t CH10SET |
[10..10] Channel 10 Status set flag
__IOM uint32_t CH11 |
[11..11] Channel 11 Status
__OM uint32_t CH11CLR |
[11..11] Channel 11 Status clear flag
__OM uint32_t CH11SET |
[11..11] Channel 11 Status set flag
__IOM uint32_t CH12 |
[12..12] Channel 12 Status
__OM uint32_t CH12CLR |
[12..12] Channel 12 Status clear flag
__OM uint32_t CH12SET |
[12..12] Channel 12 Status set flag
__IOM uint32_t CH13 |
[13..13] Channel 13 Status
__OM uint32_t CH13CLR |
[13..13] Channel 13 Status clear flag
__OM uint32_t CH13SET |
[13..13] Channel 13 Status set flag
__IOM uint32_t CH14 |
[14..14] Channel 14 Status
__OM uint32_t CH14CLR |
[14..14] Channel 14 Status clear flag
__OM uint32_t CH14SET |
[14..14] Channel 14 Status set flag
__IOM uint32_t CH15 |
[15..15] Channel 15 Status
__OM uint32_t CH15CLR |
[15..15] Channel 15 Status clear flag
__OM uint32_t CH15SET |
[15..15] Channel 15 Status set flag
__IOM uint32_t CH16 |
[16..16] Channel 16 Status
__OM uint32_t CH16CLR |
[16..16] Channel 16 Status clear flag
__OM uint32_t CH16SET |
[16..16] Channel 16 Status set flag
__IOM uint32_t CH17 |
[17..17] Channel 17 Status
__OM uint32_t CH17CLR |
[17..17] Channel 17 Status clear flag
__OM uint32_t CH17SET |
[17..17] Channel 17 Status set flag
__IOM uint32_t CH18 |
[18..18] Channel 18 Status
__OM uint32_t CH18CLR |
[18..18] Channel 18 Status clear flag
__OM uint32_t CH18SET |
[18..18] Channel 18 Status set flag
__IOM uint32_t CH19 |
[19..19] Channel 19 Status
__OM uint32_t CH19CLR |
[19..19] Channel 19 Status clear flag
__OM uint32_t CH19SET |
[19..19] Channel 19 Status set flag
__OM uint32_t CH1CLR |
[1..1] Channel 1 Status clear flag
__OM uint32_t CH1SET |
[1..1] Channel 1 Status set flag
__IOM uint32_t CH2 |
[2..2] Channel 2 Status
__OM uint32_t CH2CLR |
[2..2] Channel 2 Status clear flag
__OM uint32_t CH2SET |
[2..2] Channel 2 Status set flag
__IOM uint32_t CH3 |
[3..3] Channel 3 Status
__OM uint32_t CH3CLR |
[3..3] Channel 3 Status clear flag
__OM uint32_t CH3SET |
[3..3] Channel 3 Status set flag
__IOM uint32_t CH4 |
[4..4] Channel 4 Status
__OM uint32_t CH4CLR |
[4..4] Channel 4 Status clear flag
__OM uint32_t CH4SET |
[4..4] Channel 4 Status set flag
__IOM uint32_t CH5 |
[5..5] Channel 5 Status
__OM uint32_t CH5CLR |
[5..5] Channel 5 Status clear flag
__OM uint32_t CH5SET |
[5..5] Channel 5 Status set flag
__IOM uint32_t CH6 |
[6..6] Channel 6 Status
__OM uint32_t CH6CLR |
[6..6] Channel 6 Status clear flag
__OM uint32_t CH6SET |
[6..6] Channel 6 Status set flag
__IOM uint32_t CH7 |
[7..7] Channel 7 Status
__OM uint32_t CH7CLR |
[7..7] Channel 7 Status clear flag
__OM uint32_t CH7SET |
[7..7] Channel 7 Status set flag
__IOM uint32_t CH8 |
[8..8] Channel 8 Status
__OM uint32_t CH8CLR |
[8..8] Channel 8 Status clear flag
__OM uint32_t CH8SET |
[8..8] Channel 8 Status set flag
__IOM uint32_t CH9 |
[9..9] Channel 9 Status
__OM uint32_t CH9CLR |
[9..9] Channel 9 Status clear flag
__OM uint32_t CH9SET |
[9..9] Channel 9 Status set flag
union { ... } CHCFG0 |
union { ... } CHCFG0 |
union { ... } CHCFG1 |
union { ... } CHCFG1 |
union { ... } CHCFG10 |
union { ... } CHCFG10 |
union { ... } CHCFG11 |
union { ... } CHCFG11 |
union { ... } CHCFG12 |
union { ... } CHCFG12 |
union { ... } CHCFG13 |
union { ... } CHCFG13 |
union { ... } CHCFG14 |
union { ... } CHCFG14 |
union { ... } CHCFG15 |
union { ... } CHCFG15 |
union { ... } CHCFG16 |
union { ... } CHCFG16 |
union { ... } CHCFG17 |
union { ... } CHCFG17 |
union { ... } CHCFG18 |
union { ... } CHCFG18 |
union { ... } CHCFG19 |
union { ... } CHCFG19 |
union { ... } CHCFG2 |
union { ... } CHCFG2 |
union { ... } CHCFG3 |
union { ... } CHCFG3 |
union { ... } CHCFG4 |
union { ... } CHCFG4 |
union { ... } CHCFG5 |
union { ... } CHCFG5 |
union { ... } CHCFG6 |
union { ... } CHCFG6 |
union { ... } CHCFG7 |
union { ... } CHCFG7 |
union { ... } CHCFG8 |
union { ... } CHCFG8 |
union { ... } CHCFG9 |
union { ... } CHCFG9 |
__IOM uint32_t CHNUM |
[28..24] Current Channel under conversion
__IOM uint32_t CHREP |
[11..8] Channel Repetition
__IOM uint32_t CHSEL0 |
[4..0] Channel Select
__IOM uint32_t CHSEL1 |
[12..8] Channel Select
__IOM uint32_t CHSEL2 |
[20..16] Channel Select
__IOM uint32_t CHSEL3 |
[28..24] Channel Select
union { ... } CHSTAT |
union { ... } CHSTAT |
union { ... } CHSTATCLR |
union { ... } CHSTATCLR |
union { ... } CHSTATSET |
union { ... } CHSTATSET |
__IOM uint32_t CLASSEL |
[23..22] Conversion Class Selection
union { ... } CLKCON |
union { ... } CLKCON |
__IOM uint32_t CLKDIV |
[3..0] Clock Divider Settings
__IM uint32_t CMP_LO |
[11..8] Compare low Status
__IOM uint32_t CMP_LO0_IS |
[4..4] Compare 0 low Interrupt Status
__OM uint32_t CMP_LO0_ISCLR |
[4..4] Compare 0 low Interrupt clear
__OM uint32_t CMP_LO0_ISSET |
[4..4] Compare 0 low Interupt set
__IOM uint32_t CMP_LO0_STS |
[0..0] Compare 0 low Status
__OM uint32_t CMP_LO0_STSCLR |
[0..0] Compare 0 low Status clear
__OM uint32_t CMP_LO0_STSSET |
[0..0] Compare 0 low Status set
__IOM uint32_t CMP_LO1_IS |
[5..5] Compare 1 low Interrupt Status
__OM uint32_t CMP_LO1_ISCLR |
[5..5] Compare 1 low Interrupt clear
__OM uint32_t CMP_LO1_ISSET |
[5..5] Compare 1 low Interupt set
__IOM uint32_t CMP_LO1_STS |
[1..1] Compare 1 low Status
__OM uint32_t CMP_LO1_STSCLR |
[1..1] Compare 1 low Status clear
__OM uint32_t CMP_LO1_STSSET |
[1..1] Compare 1 low Status set
__IOM uint32_t CMP_LO2_IS |
[6..6] Compare 2 low Interrupt Status
__OM uint32_t CMP_LO2_ISCLR |
[6..6] Compare 2 low Interrupt clear
__OM uint32_t CMP_LO2_ISSET |
[6..6] Compare 2 low Interupt set
__IOM uint32_t CMP_LO2_STS |
[2..2] Compare 2 low Status
__OM uint32_t CMP_LO2_STSCLR |
[2..2] Compare 2 low Status clear
__OM uint32_t CMP_LO2_STSSET |
[2..2] Compare 2 low Status set
__IOM uint32_t CMP_LO3_IS |
[7..7] Compare 3 low Interrupt Status
__OM uint32_t CMP_LO3_ISCLR |
[7..7] Compare 3 low Interrupt clear
__OM uint32_t CMP_LO3_ISSET |
[7..7] Compare 3 low Interupt set
__IOM uint32_t CMP_LO3_STS |
[3..3] Compare 3 low Status
__OM uint32_t CMP_LO3_STSCLR |
[3..3] Compare 3 low Status clear
__OM uint32_t CMP_LO3_STSSET |
[3..3] Compare 3 low Status set
__IM uint32_t CMP_UP |
[27..24] Compare up Status
__IOM uint32_t CMP_UP0_IS |
[20..20] Compare 0 up Interrupt Status
__OM uint32_t CMP_UP0_ISCLR |
[20..20] Compare 0 up Interrupt clear
__OM uint32_t CMP_UP0_ISSET |
[20..20] Compare 0 up Interrupt set
__IOM uint32_t CMP_UP0_STS |
[16..16] Compare 0 up Status
__OM uint32_t CMP_UP0_STSCLR |
[16..16] Compare 0 up Status clear
__OM uint32_t CMP_UP0_STSSET |
[16..16] Compare 0 up Status set
__IOM uint32_t CMP_UP1_IS |
[21..21] Compare 1 up Interrupt Status
__OM uint32_t CMP_UP1_ISCLR |
[21..21] Compare 1 up Interrupt clear
__OM uint32_t CMP_UP1_ISSET |
[21..21] Compare 1 up Interrupt set
__IOM uint32_t CMP_UP1_STS |
[17..17] Compare 1 up Status
__OM uint32_t CMP_UP1_STSCLR |
[17..17] Compare 1 up Status clear
__OM uint32_t CMP_UP1_STSSET |
[17..17] Compare 1 up Status set
__IOM uint32_t CMP_UP2_IS |
[22..22] Compare 2 up Interrupt Status
__OM uint32_t CMP_UP2_ISCLR |
[22..22] Compare 2 up Interrupt clear
__OM uint32_t CMP_UP2_ISSET |
[22..22] Compare 2 up Interrupt set
__IOM uint32_t CMP_UP2_STS |
[18..18] Compare 2 up Status
__OM uint32_t CMP_UP2_STSCLR |
[18..18] Compare 2 up Status clear
__OM uint32_t CMP_UP2_STSSET |
[18..18] Compare 2 up Status set
__IOM uint32_t CMP_UP3_IS |
[23..23] Compare 3 up Interrupt Status
__OM uint32_t CMP_UP3_ISCLR |
[23..23] Compare 3 up Interrupt clear
__OM uint32_t CMP_UP3_ISSET |
[23..23] Compare 3 up Interrupt set
__IOM uint32_t CMP_UP3_STS |
[19..19] Compare 3 up Status
__OM uint32_t CMP_UP3_STSCLR |
[19..19] Compare 3 up Status clear
__OM uint32_t CMP_UP3_STSSET |
[19..19] Compare 3 up Status set
union { ... } CMPCFG0 |
union { ... } CMPCFG0 |
union { ... } CMPCFG1 |
union { ... } CMPCFG1 |
union { ... } CMPCFG2 |
union { ... } CMPCFG2 |
union { ... } CMPCFG3 |
union { ... } CMPCFG3 |
__IOM uint32_t CMPSEL |
[21..19] Compare Selection
union { ... } CMPSTAT |
union { ... } CMPSTAT |
union { ... } CMPSTATCLR |
union { ... } CMPSTATCLR |
union { ... } CMPSTATSET |
union { ... } CMPSTATSET |
__IOM uint32_t COEF_A0 |
[1..0] Filter Coefficient
__IOM uint32_t COEF_A1 |
[5..4] Filter Coefficient
__IOM uint32_t COEF_A2 |
[9..8] Filter Coefficient
__IOM uint32_t COEF_A3 |
[13..12] Filter Coefficient
__IOM uint32_t COLL0 |
[8..8] Collision 0 Status
__IOM uint32_t COLL0CLR |
[8..8] Collision 0 Status Clear
__IOM uint32_t COLL0SET |
[8..8] Collision 0 Status Set
__IOM uint32_t COLL1 |
[9..9] Collision 1 Status
__IOM uint32_t COLL1CLR |
[9..9] Collision 1 Status Clear
__IOM uint32_t COLL1SET |
[9..9] Collision 1 Status Set
__IOM uint32_t COLL2 |
[10..10] Collision 2 Status
__IOM uint32_t COLL2CLR |
[10..10] Collision 2 Status Clear
__IOM uint32_t COLL2SET |
[10..10] Collision 2 Status Set
__IOM uint32_t COLL3 |
[11..11] Collision 3 Status
__IOM uint32_t COLL3CLR |
[11..11] Collision 3 Status Clear
__IOM uint32_t COLL3SET |
[11..11] Collision 3 Status Set
__IOM uint32_t COLLCFG |
[6..6] Collision Config
__IOM uint32_t COMP_VAL |
[13..0] Compare value
union { ... } CONVCFG0 |
union { ... } CONVCFG0 |
union { ... } CONVCFG1 |
union { ... } CONVCFG1 |
union { ... } CONVCFG2 |
union { ... } CONVCFG2 |
union { ... } CONVCFG3 |
union { ... } CONVCFG3 |
union { ... } CONVSTAT |
union { ... } CONVSTATCLR |
union { ... } CONVSTATSET |
__IOM uint32_t CPCLK_HV_FAST |
[3..3] Charge Pump fast clock enable
__IM uint32_t DIGOUT |
[19..0] Test Register Digout Register
__IOM uint32_t DISCHARGE_CXXXX |
[21..21] BIST discharge off Cxxxx node - connected to ADC12.tst_dig_i[21]
__IOM uint32_t DISCHARGE_FILTER |
[23..22] Bist discharge filter execute several discharge phases
__IOM uint32_t DSCAL |
[2..2] Disable Start up Calibration
__IOM uint32_t DTB_OUT0 |
[1..0] DTB1 output assignment
__IOM uint32_t DTB_OUT1 |
[3..2] DTB0 output assignment
__IOM uint32_t DTB_OUT2 |
[5..4] DTB2 output assignment
__IOM uint32_t EN |
[0..0] Module Enable
__IOM uint32_t EN_CONV_TIMOUT |
[4..4] Conversion Timeout Enable
__OM uint32_t EOC_FAIL_CLR |
[0..0] EOC Fail Status clear flag
__IM uint32_t EOC_FAIL_IS |
[0..0] End of conversion fail Status
__OM uint32_t EOC_FAIL_SET |
[0..0] EOC Fail Status set flag
union { ... } FIL0 |
__IOM uint32_t FIL0 |
[0..0] Filter 0 Event flag
union { ... } FIL0 |
__OM uint32_t FIL0CLR |
[0..0] Filter 0 Event flag clear
__OM uint32_t FIL0SET |
[0..0] Filter 0 Event flag set
union { ... } FIL1 |
__IOM uint32_t FIL1 |
[1..1] Filter 1 Event flag
union { ... } FIL1 |
__OM uint32_t FIL1CLR |
[1..1] Filter 1 Event flag clear
__OM uint32_t FIL1SET |
[1..1] Filter 1 Event flag set
union { ... } FIL2 |
__IOM uint32_t FIL2 |
[2..2] Filter 2 Event flag
union { ... } FIL2 |
__OM uint32_t FIL2CLR |
[2..2] Filter 2 Event flag clear
__OM uint32_t FIL2SET |
[2..2] Filter 2 Event flag set
union { ... } FIL3 |
__IOM uint32_t FIL3 |
[3..3] Filter 3 Event flag
union { ... } FIL3 |
__OM uint32_t FIL3CLR |
[3..3] Filter 3 Event flag clear
__OM uint32_t FIL3SET |
[3..3] Filter 3 Event flag set
__IM uint32_t FILRESULT |
[15..0] Filter Result Value
__IOM uint32_t FILSEL |
[18..16] Filter Selection
union { ... } FILSTAT |
union { ... } FILSTAT |
union { ... } FILSTATCLR |
union { ... } FILSTATCLR |
union { ... } FILSTATSET |
union { ... } FILSTATSET |
union { ... } FILTCFG |
union { ... } FILTCFG |
union { ... } GLOBCONF |
union { ... } GLOBCONF |
__IOM uint32_t GTSEL |
[13..12] Gating Select
__IOM uint32_t GTSW |
[15..15] Trigger Software Gating
__IOM uint32_t HV_FRAME |
[24..24] HV input FRAME - connected to ADC12.tst_dig_i[24]
__IOM uint32_t HV_PRE_TIME |
[26..25] HV sample switch clock disable pre sampling time - connected to ADC12.tst_dig_i[26:25]
__IOM uint32_t HV_SWITCH_TIME |
[20..18] HV sample switch clock enable - connected to ADC12.tst_dig_i[20:18]
__IOM uint32_t HYST_LO |
[13..12] Hysteresis set for lower compare threshold
__IOM uint32_t HYST_UP |
[29..28] Hysteresis setting for upper compare threshold
union { ... } IEN0 |
union { ... } IEN0 |
union { ... } IEN1 |
union { ... } IEN1 |
__IOM uint32_t IEN_CH0 |
[0..0] Channel 0 Interrupt Enable
__IOM uint32_t IEN_CH1 |
[1..1] Channel 1 Interrupt Enable
__IOM uint32_t IEN_CH10 |
[10..10] Channel 10 Interrupt Enable
__IOM uint32_t IEN_CH11 |
[11..11] Channel 11 Interrupt Enable
__IOM uint32_t IEN_CH12 |
[12..12] Channel 12 Interrupt Enable
__IOM uint32_t IEN_CH13 |
[13..13] Channel 13 Interrupt Enable
__IOM uint32_t IEN_CH14 |
[14..14] Channel 14 Interrupt Enable
__IOM uint32_t IEN_CH15 |
[15..15] Channel 15 Interrupt Enable
__IOM uint32_t IEN_CH16 |
[16..16] Channel 16 Interrupt Enable
__IOM uint32_t IEN_CH17 |
[17..17] Channel 17 Interrupt Enable
__IOM uint32_t IEN_CH18 |
[18..18] Channel 18 Interrupt Enable
__IOM uint32_t IEN_CH19 |
[19..19] Channel 19 Interrupt Enable
__IOM uint32_t IEN_CH2 |
[2..2] Channel 2 Interrupt Enable
__IOM uint32_t IEN_CH3 |
[3..3] Channel 3 Interrupt Enable
__IOM uint32_t IEN_CH4 |
[4..4] Channel 4 Interrupt Enable
__IOM uint32_t IEN_CH5 |
[5..5] Channel 5 Interrupt Enable
__IOM uint32_t IEN_CH6 |
[6..6] Channel 6 Interrupt Enable
__IOM uint32_t IEN_CH7 |
[7..7] Channel 7 Interrupt Enable
__IOM uint32_t IEN_CH8 |
[8..8] Channel 8 Interrupt Enable
__IOM uint32_t IEN_CH9 |
[9..9] Channel 9 Interrupt Enable
__IOM uint32_t IEN_COLL0 |
[0..0] Collision 0 Interrupt Enable
__IOM uint32_t IEN_COLL1 |
[1..1] Collision 1 Interrupt Enable
__IOM uint32_t IEN_COLL2 |
[2..2] Collision 2 Interrupt Enable
__IOM uint32_t IEN_COLL3 |
[3..3] Collision 3 Interrupt Enable
__IOM uint32_t IEN_EOC_FAIL |
[8..8] EOC FAIL Interrupt Enable
__IOM uint32_t IEN_LO0 |
[24..24] Compare 0 LO Interrupt Enable
__IOM uint32_t IEN_LO1 |
[25..25] Compare 1 LO Interrupt Enable
__IOM uint32_t IEN_LO2 |
[26..26] Compare 2 LO Interrupt Enable
__IOM uint32_t IEN_LO3 |
[27..27] Compare 3 LO Interrupt Enable
__IOM uint32_t IEN_SQ0 |
[20..20] Sequence 0 Interrupt Enable
__IOM uint32_t IEN_SQ1 |
[21..21] Sequence 1 Interrupt Enable
__IOM uint32_t IEN_SQ2 |
[22..22] Sequence 2 Interrupt Enable
__IOM uint32_t IEN_SQ3 |
[23..23] Sequence 3 Interrupt Enable
__IOM uint32_t IEN_UP0 |
[28..28] Compare 0 UP Interrupt Enable
__IOM uint32_t IEN_UP1 |
[29..29] Compare 1 UP Interrupt Enable
__IOM uint32_t IEN_UP2 |
[30..30] Compare 2 UP Interrupt Enable
__IOM uint32_t IEN_UP3 |
[31..31] Compare 3 UP Interrupt Enable
__IOM uint32_t IEN_WFR0 |
[4..4] WFR 0 Interrupt Enable
__IOM uint32_t IEN_WFR1 |
[5..5] WFR 1 Interrupt Enable
__IOM uint32_t IEN_WFR2 |
[6..6] WFR 2 Interrupt Enable
__IOM uint32_t IEN_WFR3 |
[7..7] WFR 3 Interrupt Enable
union { ... } INP0 |
union { ... } INP0 |
union { ... } INP1 |
union { ... } INP1 |
union { ... } INP2 |
union { ... } INP2 |
union { ... } INP3 |
union { ... } INP3 |
__IOM uint32_t INP_CH0 |
[1..0] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH1 |
[3..2] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH10 |
[21..20] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH11 |
[23..22] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH12 |
[25..24] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH13 |
[27..26] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH14 |
[29..28] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH15 |
[31..30] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH16 |
[1..0] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH17 |
[3..2] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH18 |
[5..4] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH19 |
[7..6] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH2 |
[5..4] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH3 |
[7..6] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH4 |
[9..8] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH5 |
[11..10] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH6 |
[13..12] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH7 |
[15..14] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH8 |
[17..16] Channel Interrupt Node Pointer
__IOM uint32_t INP_CH9 |
[19..18] Channel Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO0 |
[1..0] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO1 |
[3..2] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO2 |
[5..4] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_LO3 |
[7..6] Compare Lo Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP0 |
[9..8] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP1 |
[11..10] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP2 |
[13..12] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_CMP_UP3 |
[15..14] Compare Up Interrupt Node Pointer
__IOM uint32_t INP_COLL0 |
[9..8] Collision Interrupt Node Pointer
__IOM uint32_t INP_COLL1 |
[11..10] Collision Interrupt Node Pointer
__IOM uint32_t INP_COLL2 |
[13..12] Collision Interrupt Node Pointer
__IOM uint32_t INP_COLL3 |
[15..14] Collision Interrupt Node Pointer
__IOM uint32_t INP_EOC_FAIL |
[9..8] EOC FAIL Interrupt Node Pointer
__IOM uint32_t INP_SEL |
[8..8] Input selection for the comparator unit
__IOM uint32_t INP_SQ0 |
[1..0] Sequence Interrupt Node Pointer
__IOM uint32_t INP_SQ1 |
[3..2] Sequence Interrupt Node Pointer
__IOM uint32_t INP_SQ2 |
[5..4] Sequence Interrupt Node Pointer
__IOM uint32_t INP_SQ3 |
[7..6] Sequence Interrupt Node Pointer
__IOM uint32_t INP_WFR0 |
[17..16] Wait for read Interrupt Node Pointer
__IOM uint32_t INP_WFR1 |
[19..18] Wait for read Interrupt Node Pointer
__IOM uint32_t INP_WFR2 |
[21..20] Wait for read Interrupt Node Pointer
__IOM uint32_t INP_WFR3 |
[23..22] Wait for read Interrupt Node Pointer
__IOM uint32_t INSEL |
[4..0] ADC Input Selection
__IOM uint32_t ISTE |
[5..5] Idle shadow transfer enable
__IOM uint32_t LOWER |
[7..0] Lower Compare Value
__IOM uint32_t LOWSUP |
[1..1] ADC12 Low Supply operating range
__IOM uint32_t MODE |
[31..30] Compare Mode
__IOM uint32_t MSB_EN4BIST |
[4..4] MSB distribution time doubling BIST enable - connected to ADC12.tst_dig_i[4]
__IOM uint32_t MSB_EN4CONV |
[3..3] MSB distribution time doubling Conversion enable - connected to ADC12.tst_dig_i[3]
__IOM uint32_t MSB_EN4PCAL |
[5..5] MSB distribution time doubling Post cal enable - connected to ADC12.tst_dig_i[5]
__IOM uint32_t MSB_SCAL_CFG |
[7..6] MSB distribution time doubling Start up calibration enable
__IOM uint32_t MSB_SEL |
[2..2] MSB distribution Time double - connected to ADC12.tst_dig_i[2]
__IOM uint32_t MSBD |
[10..10] MSB doubling enable
__IOM uint32_t OVERS |
[3..2] Oversampling config
__IOM uint32_t PCAL |
[11..11] Post Calibration enable
__IM uint32_t READY |
[1..1] Module Ready
__IOM uint32_t reg |
(@ 0x00000000) Global Configuration Register
(@ 0x00000004) Clock Control Register
(@ 0x00000008) Suspend Control Register
(@ 0x00000010) Sequence Configuration Register
(@ 0x00000014) SQ Channel Slot Register
(@ 0x00000018) Sequence Configuration Register
(@ 0x0000001C) SQ Channel Slot Register
(@ 0x00000020) Sequence Configuration Register
(@ 0x00000024) SQ Channel Slot Register
(@ 0x00000028) Sequence Configuration Register
(@ 0x0000002C) SQ Channel Slot Register
(@ 0x00000030) Sequence Status Register
(@ 0x00000034) Sequence Status Clear Register
(@ 0x00000038) Sequence Status Clear Register
(@ 0x0000003C) Channel Configuration Register
(@ 0x00000040) Channel Configuration Register
(@ 0x00000044) Channel Configuration Register
(@ 0x00000048) Channel Configuration Register
(@ 0x0000004C) Channel Configuration Register
(@ 0x00000050) Channel Configuration Register
(@ 0x00000054) Channel Configuration Register
(@ 0x00000058) Channel Configuration Register
(@ 0x0000005C) Channel Configuration Register
(@ 0x00000060) Channel Configuration Register
(@ 0x00000064) Channel Configuration Register
(@ 0x00000068) Channel Configuration Register
(@ 0x0000006C) Channel Configuration Register
(@ 0x00000070) Channel Configuration Register
(@ 0x00000074) Channel Configuration Register
(@ 0x00000078) Channel Configuration Register
(@ 0x0000007C) Channel Configuration Register
(@ 0x00000080) Channel Configuration Register
(@ 0x00000084) Channel Configuration Register
(@ 0x00000088) Channel Configuration Register
(@ 0x0000008C) Channel Status Register
(@ 0x00000090) Channel Status Register
(@ 0x00000094) Channel Status Set Register
(@ 0x00000098) Conversion Configuration Register
(@ 0x0000009C) Conversion Configuration Register
(@ 0x000000A0) Conversion Configuration Register
(@ 0x000000A4) Conversion Configuration Register
(@ 0x000000A8) Calibration Enable
(@ 0x000000AC) Calibration Protection Enable
(@ 0x000000B0) Filter Configuration
(@ 0x000000C4) Filter Status Register
(@ 0x000000C8) Filter Status Clear Register
(@ 0x000000CC) Filter Status Set Register
(@ 0x00000120) Compare Channel 0 Control Register
(@ 0x00000124) Compare Channel 1 Control Register
(@ 0x00000128) Compare Channel 2 Control Register
(@ 0x0000012C) Compare Channel 3 Control Register
(@ 0x00000130) Compare Status Register
(@ 0x00000134) Compare Status Clear Register
(@ 0x00000138) Compare Status Set Register
(@ 0x0000013C) Interrupt Enable Register 0
(@ 0x00000140) Interrupt Enable Register 1
(@ 0x00000144) Interrupt Node Pointer Register 0
(@ 0x00000148) Interrupt Node Pointer Register 1
(@ 0x0000014C) Interrupt Node Pointer Register 2
(@ 0x00000150) Interrupt Node Pointer Register 3
(@ 0x00000158) Test Register 1
(@ 0x0000015C) Test Register 2
(@ 0x00000160) Test Register 2
(@ 0x00000164) Shadow Transfer Control Register
(@ 0x00000168) Test Control Register
(@ 0x00000170) Conversion Status Clear Register
(@ 0x00000174) Conversion Status Set Register
(@ 0x00000178) Calibration Setting for Analog Input 1
(@ 0x0000017C) Calibration Setting for Analog Input 3
(@ 0x00000180) Calibration Setting for Analog Input 5
(@ 0x00000184) Calibration Setting for Analog Input 7
(@ 0x00000188) Calibration Setting for Analog Input 9
(@ 0x0000018C) Calibration Setting for Analog Input 11
(@ 0x00000190) Calibration Setting for Analog Input 13
(@ 0x00000194) Calibration Setting for Analog Input 15
(@ 0x00000198) Calibration Setting for Analog Input 16
(@ 0x0000019C) Calibration Setting for Analog Input 17
(@ 0x000001A0) Calibration Setting for Analog Input 18
(@ 0x000001A4) Calibration Setting for Analog Input 19
(@ 0x000001A8) Calibration Setting for Analog Input 20
(@ 0x000001AC) Calibration Setting for Analog Input 21
(@ 0x000001B0) Calibration Setting for Analog Input 22
(@ 0x000001B4) Calibration Setting for Analog Input 23
(@ 0x000001B8) Calibration Setting for Analog Input 24
(@ 0x000001BC) Calibration Setting for Analog Input 25
(@ 0x000001C0) Calibration Setting for Analog Input 26
__IM uint32_t reg |
(@ 0x0000000C) Suspend Status Register
(@ 0x000000B4) Filter Result Register
(@ 0x000000B8) Filter Result Register
(@ 0x000000BC) Filter Result Register
(@ 0x000000C0) Filter Result Register
(@ 0x000000D0) Result Register
(@ 0x000000D4) Result Register
(@ 0x000000D8) Result Register
(@ 0x000000DC) Result Register
(@ 0x000000E0) Result Register
(@ 0x000000E4) Result Register
(@ 0x000000E8) Result Register
(@ 0x000000EC) Result Register
(@ 0x000000F0) Result Register
(@ 0x000000F4) Result Register
(@ 0x000000F8) Result Register
(@ 0x000000FC) Result Register
(@ 0x00000100) Result Register
(@ 0x00000104) Result Register
(@ 0x00000108) Result Register
(@ 0x0000010C) Result Register
(@ 0x00000110) Result Register
(@ 0x00000114) Result Register
(@ 0x00000118) Result Register
(@ 0x0000011C) Result Register
(@ 0x00000154) Test Register 0
(@ 0x0000016C) Conversion Status Register
union { ... } RES0 |
union { ... } RES0 |
union { ... } RES1 |
union { ... } RES1 |
union { ... } RES10 |
union { ... } RES10 |
union { ... } RES11 |
union { ... } RES11 |
union { ... } RES12 |
union { ... } RES12 |
union { ... } RES13 |
union { ... } RES13 |
union { ... } RES14 |
union { ... } RES14 |
union { ... } RES15 |
union { ... } RES15 |
union { ... } RES16 |
union { ... } RES16 |
union { ... } RES17 |
union { ... } RES17 |
union { ... } RES18 |
union { ... } RES18 |
union { ... } RES19 |
union { ... } RES19 |
union { ... } RES2 |
union { ... } RES2 |
union { ... } RES3 |
union { ... } RES3 |
union { ... } RES4 |
union { ... } RES4 |
union { ... } RES5 |
union { ... } RES5 |
union { ... } RES6 |
union { ... } RES6 |
union { ... } RES7 |
union { ... } RES7 |
union { ... } RES8 |
union { ... } RES8 |
union { ... } RES9 |
union { ... } RES9 |
__IM uint32_t RESERVED[4] |
__IM uint32_t RESERVED1[4] |
__IM uint32_t RESULT |
[13..0] Result Value
__IOM uint32_t RST_BLANK_TIME |
[27..27] Restart Blank time
__IOM uint32_t SEL |
[1..0] Select register for tst_dig_o - connected to ADC12.tst_dig_i[1:0]
__IOM uint32_t SESP |
[8..8] Spread early sample point config
__IOM uint32_t SESP_ANA_DEL_OFF |
[8..8] SESP Analog Delay switch off - connected to ADC12.tst_dig_i[8]
__IOM uint32_t SESP_DIG_SPREAD_SHORT |
[9..9] SESP Digital Short - connected to ADC12.tst_dig_i[9]
union { ... } SHDCTR |
union { ... } SHDCTR |
__IOM uint32_t SLOTS |
[2..0] Number of used Slots in Sequence
__IOM uint32_t SQ0 |
[0..0] SQ 0 Interrupt Status
__IOM uint32_t SQ0CLR |
[0..0] SQ 0 Interrupt Status Clear
__IOM uint32_t SQ0SET |
[0..0] SQ 0 Interrupt Status Set
__IOM uint32_t SQ1 |
[1..1] SQ 1 Interrupt Status
__IOM uint32_t SQ1CLR |
[1..1] SQ 1 Interrupt Status Clear
__IOM uint32_t SQ1SET |
[1..1] SQ 1 Interrupt Status Set
__IOM uint32_t SQ2 |
[2..2] SQ 2 Interrupt Status
__IOM uint32_t SQ2CLR |
[2..2] SQ 2 Interrupt Status Clear
__IOM uint32_t SQ2SET |
[2..2] SQ 2 Interrupt Status Set
__IOM uint32_t SQ3 |
[3..3] SQ 3 Interrupt Status
__IOM uint32_t SQ3CLR |
[3..3] SQ 3 Interrupt Status Clear
__IOM uint32_t SQ3SET |
[3..3] SQ 3 Interrupt Status Set
union { ... } SQCFG0 |
union { ... } SQCFG0 |
union { ... } SQCFG1 |
union { ... } SQCFG1 |
union { ... } SQCFG2 |
union { ... } SQCFG2 |
union { ... } SQCFG3 |
union { ... } SQCFG3 |
__IOM uint32_t SQNUM |
[18..16] Actual Sequence processed
__IOM uint32_t SQREP |
[5..4] Sequence repetition
union { ... } SQSLOT0 |
union { ... } SQSLOT0 |
union { ... } SQSLOT1 |
union { ... } SQSLOT1 |
union { ... } SQSLOT2 |
union { ... } SQSLOT2 |
union { ... } SQSLOT3 |
union { ... } SQSLOT3 |
union { ... } SQSTAT |
union { ... } SQSTAT |
union { ... } SQSTATCLR |
union { ... } SQSTATCLR |
union { ... } SQSTATSET |
union { ... } SQSTATSET |
__IOM uint32_t ST_GTGSEL |
[10..8] Gating Shadow Transfer Selection
__OM uint32_t ST_GTGSW |
[18..18] Gating Software Shadow Transfer
__IOM uint32_t ST_SQSEL |
[2..0] Sequence Shadow Transfer Selection
__OM uint32_t ST_SQSW |
[16..16] Sequence Software Shadow Transfer
__IOM uint32_t ST_TRGSEL |
[6..4] Trigger Shadow Transfer Selection
__OM uint32_t ST_TRGSW |
[17..17] Trigger Software Shadow Transfer
__IOM uint32_t START_ADC_DTB |
[13..12] Start ADC DTB input assignment
__IM uint32_t STAT |
[0..0] Suspend Mode Status
__IOM uint32_t STC |
[7..4] Sample Time config
__IOM uint32_t STE_GTG |
[22..22] Gating Shadow Transfer Enable
__IOM uint32_t STE_GTGSEL |
[14..14] Gating Shadow Transfer Enable Selection
__IOM uint32_t STE_SQ |
[20..20] Sequence Shadow Transfer Enable
__IOM uint32_t STE_SQSEL |
[12..12] Sequence Shadow Transfer Enable Selection
__IOM uint32_t STE_TRG |
[21..21] Trigger Shadow Transfer Enable
__IOM uint32_t STE_TRGSEL |
[13..13] Trigger Shadow Transfer Enable Selection
union { ... } SUSCTR |
union { ... } SUSCTR |
__IOM uint32_t SUSEN |
[0..0] ADC1 Suspend Enable
__IOM uint32_t SUSMOD |
[1..1] Suspend Mode
union { ... } SUSSTAT |
union { ... } SUSSTAT |
__IOM uint32_t TCONF |
[1..0] Tracking Conversion config
union { ... } TCR |
__IOM uint32_t TEST_CTRL |
[31..31] Module Test Enable
__IOM uint32_t TRGSEL |
[11..8] Trigger Select
__OM uint32_t TRGSW |
[14..14] Software Trigger Bit
union { ... } TST0 |
union { ... } TST1 |
union { ... } TST2 |
union { ... } TST3 |
__IOM uint32_t TST_STRESS |
[11..11] Stress Test Mode
__IOM uint32_t UPPER |
[23..16] Upper Compare Value
__IM uint32_t VALID |
[15..15] Valid flag
__IOM uint32_t WFR0 |
[4..4] Wait for Read 0 Status
__IOM uint32_t WFR0CLR |
[4..4] Wait for Read 0 Status Clear
__IOM uint32_t WFR0SET |
[4..4] Wait for Read 0 Status Set
__IOM uint32_t WFR1 |
[5..5] Wait for Read 1 Status
__IOM uint32_t WFR1CLR |
[5..5] Wait for Read 1 Status Clear
__IOM uint32_t WFR1SET |
[5..5] Wait for Read 1 Status Set
__IOM uint32_t WFR2 |
[6..6] Wait for Read 2 Status
__IOM uint32_t WFR2CLR |
[6..6] Wait for Read 2 Status Clear
__IOM uint32_t WFR2SET |
[6..6] Wait for Read 2 Status Set
__IOM uint32_t WFR3 |
[7..7] Wait for Read 3 Status
__IOM uint32_t WFR3CLR |
[7..7] Wait for Read 3 Status Clear
__IOM uint32_t WFR3SET |
[7..7] Wait for Read 3 Status Set
__IOM uint32_t WFRCFG |
[7..7] Wait for Read Enable