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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
|
CAN Message Object 0 (CANMSGOBJ0)
#include <tle989x.h>
Data Fields | |
__IM uint32_t | RESERVED [960] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR0 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR0 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT0 | |
} | OBJ0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR1 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR1 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT1 | |
} | OBJ1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR2 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR2 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT2 | |
} | OBJ2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR3 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR3 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT3 | |
} | OBJ3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR4 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR4 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT4 | |
} | OBJ4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR5 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR5 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT5 | |
} | OBJ5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR6 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR6 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT6 | |
} | OBJ6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR7 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR7 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT7 | |
} | OBJ7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR8 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR8 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT8 | |
} | OBJ8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR9 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR9 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT9 | |
} | OBJ9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR10 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR10 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT10 | |
} | OBJ10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR11 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR11 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT11 | |
} | OBJ11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR12 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR12 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT12 | |
} | OBJ12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR13 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR13 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT13 | |
} | OBJ13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR14 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR14 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT14 | |
} | OBJ14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR15 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR15 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT15 | |
} | OBJ15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR16 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR16 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT16 | |
} | OBJ16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR17 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR17 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT17 | |
} | OBJ17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR18 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR18 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT18 | |
} | OBJ18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR19 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR19 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT19 | |
} | OBJ19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR20 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR20 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT20 | |
} | OBJ20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR21 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR21 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT21 | |
} | OBJ21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR22 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR22 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT22 | |
} | OBJ22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR23 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR23 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT23 | |
} | OBJ23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR24 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR24 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT24 | |
} | OBJ24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR25 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR25 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT25 | |
} | OBJ25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR26 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR26 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT26 | |
} | OBJ26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR27 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR27 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT27 | |
} | OBJ27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR28 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR28 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT28 | |
} | OBJ28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR29 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR29 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT29 | |
} | OBJ29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR30 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR30 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT30 | |
} | OBJ30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR31 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR31 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT31 | |
} | OBJ31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR0 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR0 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT0 | |
} | OBJ0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR1 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR1 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT1 | |
} | OBJ1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR2 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR2 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT2 | |
} | OBJ2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR3 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR3 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT3 | |
} | OBJ3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR4 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR4 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT4 | |
} | OBJ4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR5 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR5 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT5 | |
} | OBJ5 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR6 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR6 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT6 | |
} | OBJ6 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR7 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR7 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT7 | |
} | OBJ7 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR8 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR8 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT8 | |
} | OBJ8 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR9 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR9 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT9 | |
} | OBJ9 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR10 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR10 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT10 | |
} | OBJ10 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR11 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR11 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT11 | |
} | OBJ11 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR12 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR12 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT12 | |
} | OBJ12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR13 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR13 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT13 | |
} | OBJ13 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR14 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR14 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT14 | |
} | OBJ14 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR15 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR15 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT15 | |
} | OBJ15 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR16 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR16 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT16 | |
} | OBJ16 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR17 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR17 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT17 | |
} | OBJ17 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR18 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR18 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT18 | |
} | OBJ18 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR19 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR19 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT19 | |
} | OBJ19 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR20 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR20 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT20 | |
} | OBJ20 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR21 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR21 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT21 | |
} | OBJ21 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR22 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR22 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT22 | |
} | OBJ22 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR23 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR23 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT23 | |
} | OBJ23 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR24 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR24 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT24 | |
} | OBJ24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR25 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR25 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT25 | |
} | OBJ25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR26 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR26 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT26 | |
} | OBJ26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR27 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR27 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT27 | |
} | OBJ27 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR28 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR28 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT28 | |
} | OBJ28 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR29 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR29 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT29 | |
} | OBJ29 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR30 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR30 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT30 | |
} | OBJ30 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MMC: 4 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t BRS: 1 | |
__IOM uint32_t FDF: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t GDFS: 1 | |
__IOM uint32_t IDC: 1 | |
__IOM uint32_t DLCC: 1 | |
__IOM uint32_t DATC: 1 | |
uint32_t __pad2__: 4 | |
__IOM uint32_t RXIE: 1 | |
__IOM uint32_t TXIE: 1 | |
__IOM uint32_t OVIE: 1 | |
uint32_t __pad3__: 1 | |
__IOM uint32_t FRREN: 1 | |
__IOM uint32_t RMM: 1 | |
__IOM uint32_t SDT: 1 | |
__IOM uint32_t STT: 1 | |
__IOM uint32_t DLC: 4 | |
uint32_t __pad4__: 4 | |
} bit | |
} | CAN_MOFCR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BOT: 8 | |
__IOM uint32_t TOP: 8 | |
__IOM uint32_t CUR: 8 | |
__IOM uint32_t SEL: 8 | |
} bit | |
} | CAN_MOFGPR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t RXINP: 4 | |
__IOM uint32_t TXINP: 4 | |
__IOM uint32_t MPN: 8 | |
__IOM uint32_t CFCVAL: 16 | |
} bit | |
} | CAN_MOIPR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t AM: 29 | |
__IOM uint32_t MIDE: 1 | |
uint32_t __pad0__: 2 | |
} bit | |
} | CAN_MOAMR31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB0: 8 | |
__IOM uint32_t DB1: 8 | |
__IOM uint32_t DB2: 8 | |
__IOM uint32_t DB3: 8 | |
} bit | |
} | CAN_MODATAL31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DB4: 8 | |
__IOM uint32_t DB5: 8 | |
__IOM uint32_t DB6: 8 | |
__IOM uint32_t DB7: 8 | |
} bit | |
} | CAN_MODATAH31 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ID: 29 | |
__IOM uint32_t IDE: 1 | |
__IOM uint32_t PRI: 2 | |
} bit | |
} | CAN_MOAR31 |
union { | |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t RESRXPND: 1 | |
__OM uint32_t RESTXPND: 1 | |
__OM uint32_t RESRXUPD: 1 | |
__OM uint32_t RESNEWDAT: 1 | |
__OM uint32_t RESMSGLST: 1 | |
__OM uint32_t RESMSGVAL: 1 | |
__OM uint32_t RESRTSEL: 1 | |
__OM uint32_t RESRXEN: 1 | |
__OM uint32_t RESTXRQ: 1 | |
__OM uint32_t RESTXEN0: 1 | |
__OM uint32_t RESTXEN1: 1 | |
__OM uint32_t RESDIR_SETDIR: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t SETRXPND: 1 | |
__OM uint32_t SETTXPND: 1 | |
__OM uint32_t SETRXUPD: 1 | |
__OM uint32_t SETNEWDAT: 1 | |
__OM uint32_t SETMSGLST: 1 | |
__OM uint32_t SETMSGVAL: 1 | |
__OM uint32_t SETRTSEL: 1 | |
__OM uint32_t SETRXEN: 1 | |
__OM uint32_t SETTXRQ: 1 | |
__OM uint32_t SETTXEN0: 1 | |
__OM uint32_t SETTXEN1: 1 | |
__OM uint32_t SETDIR: 1 | |
uint32_t __pad1__: 4 | |
} bit | |
} CAN_MOCTR31 | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RXPND: 1 | |
__IM uint32_t TXPND: 1 | |
__IM uint32_t RXUPD: 1 | |
__IM uint32_t NEWDAT: 1 | |
__IM uint32_t MSGLST: 1 | |
__IM uint32_t MSGVAL: 1 | |
__IM uint32_t RTSEL: 1 | |
__IM uint32_t RXEN: 1 | |
__IM uint32_t TXRQ: 1 | |
__IM uint32_t TXEN0: 1 | |
__IM uint32_t TXEN1: 1 | |
__IM uint32_t DIR: 1 | |
__IM uint32_t LIST: 4 | |
__IM uint32_t PPREV: 8 | |
__IM uint32_t PNEXT: 8 | |
} bit | |
} CAN_MOSTAT31 | |
} | OBJ31 |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
uint32_t __pad4__ |
__IOM uint32_t AM |
[28..0] Acceptance Mask for Message Identifier
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struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IOM uint32_t BOT |
[7..0] Bottom Pointer
__IOM uint32_t BRS |
[5..5] Bit Rate Switch
union { ... } CAN_MOAMR0 |
union { ... } CAN_MOAMR0 |
union { ... } CAN_MOAMR1 |
union { ... } CAN_MOAMR1 |
union { ... } CAN_MOAMR10 |
union { ... } CAN_MOAMR10 |
union { ... } CAN_MOAMR11 |
union { ... } CAN_MOAMR11 |
union { ... } CAN_MOAMR12 |
union { ... } CAN_MOAMR12 |
union { ... } CAN_MOAMR13 |
union { ... } CAN_MOAMR13 |
union { ... } CAN_MOAMR14 |
union { ... } CAN_MOAMR14 |
union { ... } CAN_MOAMR15 |
union { ... } CAN_MOAMR15 |
union { ... } CAN_MOAMR16 |
union { ... } CAN_MOAMR16 |
union { ... } CAN_MOAMR17 |
union { ... } CAN_MOAMR17 |
union { ... } CAN_MOAMR18 |
union { ... } CAN_MOAMR18 |
union { ... } CAN_MOAMR19 |
union { ... } CAN_MOAMR19 |
union { ... } CAN_MOAMR2 |
union { ... } CAN_MOAMR2 |
union { ... } CAN_MOAMR20 |
union { ... } CAN_MOAMR20 |
union { ... } CAN_MOAMR21 |
union { ... } CAN_MOAMR21 |
union { ... } CAN_MOAMR22 |
union { ... } CAN_MOAMR22 |
union { ... } CAN_MOAMR23 |
union { ... } CAN_MOAMR23 |
union { ... } CAN_MOAMR24 |
union { ... } CAN_MOAMR24 |
union { ... } CAN_MOAMR25 |
union { ... } CAN_MOAMR25 |
union { ... } CAN_MOAMR26 |
union { ... } CAN_MOAMR26 |
union { ... } CAN_MOAMR27 |
union { ... } CAN_MOAMR27 |
union { ... } CAN_MOAMR28 |
union { ... } CAN_MOAMR28 |
union { ... } CAN_MOAMR29 |
union { ... } CAN_MOAMR29 |
union { ... } CAN_MOAMR3 |
union { ... } CAN_MOAMR3 |
union { ... } CAN_MOAMR30 |
union { ... } CAN_MOAMR30 |
union { ... } CAN_MOAMR31 |
union { ... } CAN_MOAMR31 |
union { ... } CAN_MOAMR4 |
union { ... } CAN_MOAMR4 |
union { ... } CAN_MOAMR5 |
union { ... } CAN_MOAMR5 |
union { ... } CAN_MOAMR6 |
union { ... } CAN_MOAMR6 |
union { ... } CAN_MOAMR7 |
union { ... } CAN_MOAMR7 |
union { ... } CAN_MOAMR8 |
union { ... } CAN_MOAMR8 |
union { ... } CAN_MOAMR9 |
union { ... } CAN_MOAMR9 |
union { ... } CAN_MOAR0 |
union { ... } CAN_MOAR0 |
union { ... } CAN_MOAR1 |
union { ... } CAN_MOAR1 |
union { ... } CAN_MOAR10 |
union { ... } CAN_MOAR10 |
union { ... } CAN_MOAR11 |
union { ... } CAN_MOAR11 |
union { ... } CAN_MOAR12 |
union { ... } CAN_MOAR12 |
union { ... } CAN_MOAR13 |
union { ... } CAN_MOAR13 |
union { ... } CAN_MOAR14 |
union { ... } CAN_MOAR14 |
union { ... } CAN_MOAR15 |
union { ... } CAN_MOAR15 |
union { ... } CAN_MOAR16 |
union { ... } CAN_MOAR16 |
union { ... } CAN_MOAR17 |
union { ... } CAN_MOAR17 |
union { ... } CAN_MOAR18 |
union { ... } CAN_MOAR18 |
union { ... } CAN_MOAR19 |
union { ... } CAN_MOAR19 |
union { ... } CAN_MOAR2 |
union { ... } CAN_MOAR2 |
union { ... } CAN_MOAR20 |
union { ... } CAN_MOAR20 |
union { ... } CAN_MOAR21 |
union { ... } CAN_MOAR21 |
union { ... } CAN_MOAR22 |
union { ... } CAN_MOAR22 |
union { ... } CAN_MOAR23 |
union { ... } CAN_MOAR23 |
union { ... } CAN_MOAR24 |
union { ... } CAN_MOAR24 |
union { ... } CAN_MOAR25 |
union { ... } CAN_MOAR25 |
union { ... } CAN_MOAR26 |
union { ... } CAN_MOAR26 |
union { ... } CAN_MOAR27 |
union { ... } CAN_MOAR27 |
union { ... } CAN_MOAR28 |
union { ... } CAN_MOAR28 |
union { ... } CAN_MOAR29 |
union { ... } CAN_MOAR29 |
union { ... } CAN_MOAR3 |
union { ... } CAN_MOAR3 |
union { ... } CAN_MOAR30 |
union { ... } CAN_MOAR30 |
union { ... } CAN_MOAR31 |
union { ... } CAN_MOAR31 |
union { ... } CAN_MOAR4 |
union { ... } CAN_MOAR4 |
union { ... } CAN_MOAR5 |
union { ... } CAN_MOAR5 |
union { ... } CAN_MOAR6 |
union { ... } CAN_MOAR6 |
union { ... } CAN_MOAR7 |
union { ... } CAN_MOAR7 |
union { ... } CAN_MOAR8 |
union { ... } CAN_MOAR8 |
union { ... } CAN_MOAR9 |
union { ... } CAN_MOAR9 |
union { ... } CAN_MOCTR0 |
union { ... } CAN_MOCTR0 |
union { ... } CAN_MOCTR1 |
union { ... } CAN_MOCTR1 |
union { ... } CAN_MOCTR10 |
union { ... } CAN_MOCTR10 |
union { ... } CAN_MOCTR11 |
union { ... } CAN_MOCTR11 |
union { ... } CAN_MOCTR12 |
union { ... } CAN_MOCTR12 |
union { ... } CAN_MOCTR13 |
union { ... } CAN_MOCTR13 |
union { ... } CAN_MOCTR14 |
union { ... } CAN_MOCTR14 |
union { ... } CAN_MOCTR15 |
union { ... } CAN_MOCTR15 |
union { ... } CAN_MOCTR16 |
union { ... } CAN_MOCTR16 |
union { ... } CAN_MOCTR17 |
union { ... } CAN_MOCTR17 |
union { ... } CAN_MOCTR18 |
union { ... } CAN_MOCTR18 |
union { ... } CAN_MOCTR19 |
union { ... } CAN_MOCTR19 |
union { ... } CAN_MOCTR2 |
union { ... } CAN_MOCTR2 |
union { ... } CAN_MOCTR20 |
union { ... } CAN_MOCTR20 |
union { ... } CAN_MOCTR21 |
union { ... } CAN_MOCTR21 |
union { ... } CAN_MOCTR22 |
union { ... } CAN_MOCTR22 |
union { ... } CAN_MOCTR23 |
union { ... } CAN_MOCTR23 |
union { ... } CAN_MOCTR24 |
union { ... } CAN_MOCTR24 |
union { ... } CAN_MOCTR25 |
union { ... } CAN_MOCTR25 |
union { ... } CAN_MOCTR26 |
union { ... } CAN_MOCTR26 |
union { ... } CAN_MOCTR27 |
union { ... } CAN_MOCTR27 |
union { ... } CAN_MOCTR28 |
union { ... } CAN_MOCTR28 |
union { ... } CAN_MOCTR29 |
union { ... } CAN_MOCTR29 |
union { ... } CAN_MOCTR3 |
union { ... } CAN_MOCTR3 |
union { ... } CAN_MOCTR30 |
union { ... } CAN_MOCTR30 |
union { ... } CAN_MOCTR31 |
union { ... } CAN_MOCTR31 |
union { ... } CAN_MOCTR4 |
union { ... } CAN_MOCTR4 |
union { ... } CAN_MOCTR5 |
union { ... } CAN_MOCTR5 |
union { ... } CAN_MOCTR6 |
union { ... } CAN_MOCTR6 |
union { ... } CAN_MOCTR7 |
union { ... } CAN_MOCTR7 |
union { ... } CAN_MOCTR8 |
union { ... } CAN_MOCTR8 |
union { ... } CAN_MOCTR9 |
union { ... } CAN_MOCTR9 |
union { ... } CAN_MODATAH0 |
union { ... } CAN_MODATAH0 |
union { ... } CAN_MODATAH1 |
union { ... } CAN_MODATAH1 |
union { ... } CAN_MODATAH10 |
union { ... } CAN_MODATAH10 |
union { ... } CAN_MODATAH11 |
union { ... } CAN_MODATAH11 |
union { ... } CAN_MODATAH12 |
union { ... } CAN_MODATAH12 |
union { ... } CAN_MODATAH13 |
union { ... } CAN_MODATAH13 |
union { ... } CAN_MODATAH14 |
union { ... } CAN_MODATAH14 |
union { ... } CAN_MODATAH15 |
union { ... } CAN_MODATAH15 |
union { ... } CAN_MODATAH16 |
union { ... } CAN_MODATAH16 |
union { ... } CAN_MODATAH17 |
union { ... } CAN_MODATAH17 |
union { ... } CAN_MODATAH18 |
union { ... } CAN_MODATAH18 |
union { ... } CAN_MODATAH19 |
union { ... } CAN_MODATAH19 |
union { ... } CAN_MODATAH2 |
union { ... } CAN_MODATAH2 |
union { ... } CAN_MODATAH20 |
union { ... } CAN_MODATAH20 |
union { ... } CAN_MODATAH21 |
union { ... } CAN_MODATAH21 |
union { ... } CAN_MODATAH22 |
union { ... } CAN_MODATAH22 |
union { ... } CAN_MODATAH23 |
union { ... } CAN_MODATAH23 |
union { ... } CAN_MODATAH24 |
union { ... } CAN_MODATAH24 |
union { ... } CAN_MODATAH25 |
union { ... } CAN_MODATAH25 |
union { ... } CAN_MODATAH26 |
union { ... } CAN_MODATAH26 |
union { ... } CAN_MODATAH27 |
union { ... } CAN_MODATAH27 |
union { ... } CAN_MODATAH28 |
union { ... } CAN_MODATAH28 |
union { ... } CAN_MODATAH29 |
union { ... } CAN_MODATAH29 |
union { ... } CAN_MODATAH3 |
union { ... } CAN_MODATAH3 |
union { ... } CAN_MODATAH30 |
union { ... } CAN_MODATAH30 |
union { ... } CAN_MODATAH31 |
union { ... } CAN_MODATAH31 |
union { ... } CAN_MODATAH4 |
union { ... } CAN_MODATAH4 |
union { ... } CAN_MODATAH5 |
union { ... } CAN_MODATAH5 |
union { ... } CAN_MODATAH6 |
union { ... } CAN_MODATAH6 |
union { ... } CAN_MODATAH7 |
union { ... } CAN_MODATAH7 |
union { ... } CAN_MODATAH8 |
union { ... } CAN_MODATAH8 |
union { ... } CAN_MODATAH9 |
union { ... } CAN_MODATAH9 |
union { ... } CAN_MODATAL0 |
union { ... } CAN_MODATAL0 |
union { ... } CAN_MODATAL1 |
union { ... } CAN_MODATAL1 |
union { ... } CAN_MODATAL10 |
union { ... } CAN_MODATAL10 |
union { ... } CAN_MODATAL11 |
union { ... } CAN_MODATAL11 |
union { ... } CAN_MODATAL12 |
union { ... } CAN_MODATAL12 |
union { ... } CAN_MODATAL13 |
union { ... } CAN_MODATAL13 |
union { ... } CAN_MODATAL14 |
union { ... } CAN_MODATAL14 |
union { ... } CAN_MODATAL15 |
union { ... } CAN_MODATAL15 |
union { ... } CAN_MODATAL16 |
union { ... } CAN_MODATAL16 |
union { ... } CAN_MODATAL17 |
union { ... } CAN_MODATAL17 |
union { ... } CAN_MODATAL18 |
union { ... } CAN_MODATAL18 |
union { ... } CAN_MODATAL19 |
union { ... } CAN_MODATAL19 |
union { ... } CAN_MODATAL2 |
union { ... } CAN_MODATAL2 |
union { ... } CAN_MODATAL20 |
union { ... } CAN_MODATAL20 |
union { ... } CAN_MODATAL21 |
union { ... } CAN_MODATAL21 |
union { ... } CAN_MODATAL22 |
union { ... } CAN_MODATAL22 |
union { ... } CAN_MODATAL23 |
union { ... } CAN_MODATAL23 |
union { ... } CAN_MODATAL24 |
union { ... } CAN_MODATAL24 |
union { ... } CAN_MODATAL25 |
union { ... } CAN_MODATAL25 |
union { ... } CAN_MODATAL26 |
union { ... } CAN_MODATAL26 |
union { ... } CAN_MODATAL27 |
union { ... } CAN_MODATAL27 |
union { ... } CAN_MODATAL28 |
union { ... } CAN_MODATAL28 |
union { ... } CAN_MODATAL29 |
union { ... } CAN_MODATAL29 |
union { ... } CAN_MODATAL3 |
union { ... } CAN_MODATAL3 |
union { ... } CAN_MODATAL30 |
union { ... } CAN_MODATAL30 |
union { ... } CAN_MODATAL31 |
union { ... } CAN_MODATAL31 |
union { ... } CAN_MODATAL4 |
union { ... } CAN_MODATAL4 |
union { ... } CAN_MODATAL5 |
union { ... } CAN_MODATAL5 |
union { ... } CAN_MODATAL6 |
union { ... } CAN_MODATAL6 |
union { ... } CAN_MODATAL7 |
union { ... } CAN_MODATAL7 |
union { ... } CAN_MODATAL8 |
union { ... } CAN_MODATAL8 |
union { ... } CAN_MODATAL9 |
union { ... } CAN_MODATAL9 |
union { ... } CAN_MOFCR0 |
union { ... } CAN_MOFCR0 |
union { ... } CAN_MOFCR1 |
union { ... } CAN_MOFCR1 |
union { ... } CAN_MOFCR10 |
union { ... } CAN_MOFCR10 |
union { ... } CAN_MOFCR11 |
union { ... } CAN_MOFCR11 |
union { ... } CAN_MOFCR12 |
union { ... } CAN_MOFCR12 |
union { ... } CAN_MOFCR13 |
union { ... } CAN_MOFCR13 |
union { ... } CAN_MOFCR14 |
union { ... } CAN_MOFCR14 |
union { ... } CAN_MOFCR15 |
union { ... } CAN_MOFCR15 |
union { ... } CAN_MOFCR16 |
union { ... } CAN_MOFCR16 |
union { ... } CAN_MOFCR17 |
union { ... } CAN_MOFCR17 |
union { ... } CAN_MOFCR18 |
union { ... } CAN_MOFCR18 |
union { ... } CAN_MOFCR19 |
union { ... } CAN_MOFCR19 |
union { ... } CAN_MOFCR2 |
union { ... } CAN_MOFCR2 |
union { ... } CAN_MOFCR20 |
union { ... } CAN_MOFCR20 |
union { ... } CAN_MOFCR21 |
union { ... } CAN_MOFCR21 |
union { ... } CAN_MOFCR22 |
union { ... } CAN_MOFCR22 |
union { ... } CAN_MOFCR23 |
union { ... } CAN_MOFCR23 |
union { ... } CAN_MOFCR24 |
union { ... } CAN_MOFCR24 |
union { ... } CAN_MOFCR25 |
union { ... } CAN_MOFCR25 |
union { ... } CAN_MOFCR26 |
union { ... } CAN_MOFCR26 |
union { ... } CAN_MOFCR27 |
union { ... } CAN_MOFCR27 |
union { ... } CAN_MOFCR28 |
union { ... } CAN_MOFCR28 |
union { ... } CAN_MOFCR29 |
union { ... } CAN_MOFCR29 |
union { ... } CAN_MOFCR3 |
union { ... } CAN_MOFCR3 |
union { ... } CAN_MOFCR30 |
union { ... } CAN_MOFCR30 |
union { ... } CAN_MOFCR31 |
union { ... } CAN_MOFCR31 |
union { ... } CAN_MOFCR4 |
union { ... } CAN_MOFCR4 |
union { ... } CAN_MOFCR5 |
union { ... } CAN_MOFCR5 |
union { ... } CAN_MOFCR6 |
union { ... } CAN_MOFCR6 |
union { ... } CAN_MOFCR7 |
union { ... } CAN_MOFCR7 |
union { ... } CAN_MOFCR8 |
union { ... } CAN_MOFCR8 |
union { ... } CAN_MOFCR9 |
union { ... } CAN_MOFCR9 |
union { ... } CAN_MOFGPR0 |
union { ... } CAN_MOFGPR0 |
union { ... } CAN_MOFGPR1 |
union { ... } CAN_MOFGPR1 |
union { ... } CAN_MOFGPR10 |
union { ... } CAN_MOFGPR10 |
union { ... } CAN_MOFGPR11 |
union { ... } CAN_MOFGPR11 |
union { ... } CAN_MOFGPR12 |
union { ... } CAN_MOFGPR12 |
union { ... } CAN_MOFGPR13 |
union { ... } CAN_MOFGPR13 |
union { ... } CAN_MOFGPR14 |
union { ... } CAN_MOFGPR14 |
union { ... } CAN_MOFGPR15 |
union { ... } CAN_MOFGPR15 |
union { ... } CAN_MOFGPR16 |
union { ... } CAN_MOFGPR16 |
union { ... } CAN_MOFGPR17 |
union { ... } CAN_MOFGPR17 |
union { ... } CAN_MOFGPR18 |
union { ... } CAN_MOFGPR18 |
union { ... } CAN_MOFGPR19 |
union { ... } CAN_MOFGPR19 |
union { ... } CAN_MOFGPR2 |
union { ... } CAN_MOFGPR2 |
union { ... } CAN_MOFGPR20 |
union { ... } CAN_MOFGPR20 |
union { ... } CAN_MOFGPR21 |
union { ... } CAN_MOFGPR21 |
union { ... } CAN_MOFGPR22 |
union { ... } CAN_MOFGPR22 |
union { ... } CAN_MOFGPR23 |
union { ... } CAN_MOFGPR23 |
union { ... } CAN_MOFGPR24 |
union { ... } CAN_MOFGPR24 |
union { ... } CAN_MOFGPR25 |
union { ... } CAN_MOFGPR25 |
union { ... } CAN_MOFGPR26 |
union { ... } CAN_MOFGPR26 |
union { ... } CAN_MOFGPR27 |
union { ... } CAN_MOFGPR27 |
union { ... } CAN_MOFGPR28 |
union { ... } CAN_MOFGPR28 |
union { ... } CAN_MOFGPR29 |
union { ... } CAN_MOFGPR29 |
union { ... } CAN_MOFGPR3 |
union { ... } CAN_MOFGPR3 |
union { ... } CAN_MOFGPR30 |
union { ... } CAN_MOFGPR30 |
union { ... } CAN_MOFGPR31 |
union { ... } CAN_MOFGPR31 |
union { ... } CAN_MOFGPR4 |
union { ... } CAN_MOFGPR4 |
union { ... } CAN_MOFGPR5 |
union { ... } CAN_MOFGPR5 |
union { ... } CAN_MOFGPR6 |
union { ... } CAN_MOFGPR6 |
union { ... } CAN_MOFGPR7 |
union { ... } CAN_MOFGPR7 |
union { ... } CAN_MOFGPR8 |
union { ... } CAN_MOFGPR8 |
union { ... } CAN_MOFGPR9 |
union { ... } CAN_MOFGPR9 |
union { ... } CAN_MOIPR0 |
union { ... } CAN_MOIPR0 |
union { ... } CAN_MOIPR1 |
union { ... } CAN_MOIPR1 |
union { ... } CAN_MOIPR10 |
union { ... } CAN_MOIPR10 |
union { ... } CAN_MOIPR11 |
union { ... } CAN_MOIPR11 |
union { ... } CAN_MOIPR12 |
union { ... } CAN_MOIPR12 |
union { ... } CAN_MOIPR13 |
union { ... } CAN_MOIPR13 |
union { ... } CAN_MOIPR14 |
union { ... } CAN_MOIPR14 |
union { ... } CAN_MOIPR15 |
union { ... } CAN_MOIPR15 |
union { ... } CAN_MOIPR16 |
union { ... } CAN_MOIPR16 |
union { ... } CAN_MOIPR17 |
union { ... } CAN_MOIPR17 |
union { ... } CAN_MOIPR18 |
union { ... } CAN_MOIPR18 |
union { ... } CAN_MOIPR19 |
union { ... } CAN_MOIPR19 |
union { ... } CAN_MOIPR2 |
union { ... } CAN_MOIPR2 |
union { ... } CAN_MOIPR20 |
union { ... } CAN_MOIPR20 |
union { ... } CAN_MOIPR21 |
union { ... } CAN_MOIPR21 |
union { ... } CAN_MOIPR22 |
union { ... } CAN_MOIPR22 |
union { ... } CAN_MOIPR23 |
union { ... } CAN_MOIPR23 |
union { ... } CAN_MOIPR24 |
union { ... } CAN_MOIPR24 |
union { ... } CAN_MOIPR25 |
union { ... } CAN_MOIPR25 |
union { ... } CAN_MOIPR26 |
union { ... } CAN_MOIPR26 |
union { ... } CAN_MOIPR27 |
union { ... } CAN_MOIPR27 |
union { ... } CAN_MOIPR28 |
union { ... } CAN_MOIPR28 |
union { ... } CAN_MOIPR29 |
union { ... } CAN_MOIPR29 |
union { ... } CAN_MOIPR3 |
union { ... } CAN_MOIPR3 |
union { ... } CAN_MOIPR30 |
union { ... } CAN_MOIPR30 |
union { ... } CAN_MOIPR31 |
union { ... } CAN_MOIPR31 |
union { ... } CAN_MOIPR4 |
union { ... } CAN_MOIPR4 |
union { ... } CAN_MOIPR5 |
union { ... } CAN_MOIPR5 |
union { ... } CAN_MOIPR6 |
union { ... } CAN_MOIPR6 |
union { ... } CAN_MOIPR7 |
union { ... } CAN_MOIPR7 |
union { ... } CAN_MOIPR8 |
union { ... } CAN_MOIPR8 |
union { ... } CAN_MOIPR9 |
union { ... } CAN_MOIPR9 |
union { ... } CAN_MOSTAT0 |
union { ... } CAN_MOSTAT0 |
union { ... } CAN_MOSTAT1 |
union { ... } CAN_MOSTAT1 |
union { ... } CAN_MOSTAT10 |
union { ... } CAN_MOSTAT10 |
union { ... } CAN_MOSTAT11 |
union { ... } CAN_MOSTAT11 |
union { ... } CAN_MOSTAT12 |
union { ... } CAN_MOSTAT12 |
union { ... } CAN_MOSTAT13 |
union { ... } CAN_MOSTAT13 |
union { ... } CAN_MOSTAT14 |
union { ... } CAN_MOSTAT14 |
union { ... } CAN_MOSTAT15 |
union { ... } CAN_MOSTAT15 |
union { ... } CAN_MOSTAT16 |
union { ... } CAN_MOSTAT16 |
union { ... } CAN_MOSTAT17 |
union { ... } CAN_MOSTAT17 |
union { ... } CAN_MOSTAT18 |
union { ... } CAN_MOSTAT18 |
union { ... } CAN_MOSTAT19 |
union { ... } CAN_MOSTAT19 |
union { ... } CAN_MOSTAT2 |
union { ... } CAN_MOSTAT2 |
union { ... } CAN_MOSTAT20 |
union { ... } CAN_MOSTAT20 |
union { ... } CAN_MOSTAT21 |
union { ... } CAN_MOSTAT21 |
union { ... } CAN_MOSTAT22 |
union { ... } CAN_MOSTAT22 |
union { ... } CAN_MOSTAT23 |
union { ... } CAN_MOSTAT23 |
union { ... } CAN_MOSTAT24 |
union { ... } CAN_MOSTAT24 |
union { ... } CAN_MOSTAT25 |
union { ... } CAN_MOSTAT25 |
union { ... } CAN_MOSTAT26 |
union { ... } CAN_MOSTAT26 |
union { ... } CAN_MOSTAT27 |
union { ... } CAN_MOSTAT27 |
union { ... } CAN_MOSTAT28 |
union { ... } CAN_MOSTAT28 |
union { ... } CAN_MOSTAT29 |
union { ... } CAN_MOSTAT29 |
union { ... } CAN_MOSTAT3 |
union { ... } CAN_MOSTAT3 |
union { ... } CAN_MOSTAT30 |
union { ... } CAN_MOSTAT30 |
union { ... } CAN_MOSTAT31 |
union { ... } CAN_MOSTAT31 |
union { ... } CAN_MOSTAT4 |
union { ... } CAN_MOSTAT4 |
union { ... } CAN_MOSTAT5 |
union { ... } CAN_MOSTAT5 |
union { ... } CAN_MOSTAT6 |
union { ... } CAN_MOSTAT6 |
union { ... } CAN_MOSTAT7 |
union { ... } CAN_MOSTAT7 |
union { ... } CAN_MOSTAT8 |
union { ... } CAN_MOSTAT8 |
union { ... } CAN_MOSTAT9 |
union { ... } CAN_MOSTAT9 |
__IOM uint32_t CFCVAL |
[31..16] CAN Frame Counter Value
__IOM uint32_t CUR |
[23..16] Current Object Pointer
__IOM uint32_t DATC |
[11..11] Data Copy
__IOM uint32_t DB0 |
[7..0] Data Byte 0 of Message Object n
__IOM uint32_t DB1 |
[15..8] Data Byte 1 of Message Object n
__IOM uint32_t DB2 |
[23..16] Data Byte 2 of Message Object n
__IOM uint32_t DB3 |
[31..24] Data Byte 3 of Message Object n
__IOM uint32_t DB4 |
[7..0] Data Byte 4 of Message Object n
__IOM uint32_t DB5 |
[15..8] Data Byte 5 of Message Object n
__IOM uint32_t DB6 |
[23..16] Data Byte 6 of Message Object n
__IOM uint32_t DB7 |
[31..24] Data Byte 7 of Message Object n
__IM uint32_t DIR |
[11..11] Message Direction
__IOM uint32_t DLC |
[27..24] Data Length Code
__IOM uint32_t DLCC |
[10..10] Data Length Code Copy
__IOM uint32_t FDF |
[6..6] CAN FD Frame Format
__IOM uint32_t FRREN |
[20..20] Foreign Remote Request Enable
__IOM uint32_t GDFS |
[8..8] Gateway Data Frame Send
__IOM uint32_t ID |
[28..0] CAN Identifier of Message Object n
__IOM uint32_t IDC |
[9..9] Identifier Copy
__IOM uint32_t IDE |
[29..29] Identifier Extension Bit of Message Object n
__IM uint32_t LIST |
[15..12] List Allocation
__IOM uint32_t MIDE |
[29..29] Acceptance Mask Bit for Message IDE Bit
__IOM uint32_t MMC |
[3..0] Message Mode Control
__IOM uint32_t MPN |
[15..8] Message Pending Number
__IM uint32_t MSGLST |
[4..4] Message Lost
__IM uint32_t MSGVAL |
[5..5] Message Valid
__IM uint32_t NEWDAT |
[3..3] New Data
union { ... } OBJ0 |
union { ... } OBJ0 |
union { ... } OBJ1 |
union { ... } OBJ1 |
union { ... } OBJ10 |
union { ... } OBJ10 |
union { ... } OBJ11 |
union { ... } OBJ11 |
union { ... } OBJ12 |
union { ... } OBJ12 |
union { ... } OBJ13 |
union { ... } OBJ13 |
union { ... } OBJ14 |
union { ... } OBJ14 |
union { ... } OBJ15 |
union { ... } OBJ15 |
union { ... } OBJ16 |
union { ... } OBJ16 |
union { ... } OBJ17 |
union { ... } OBJ17 |
union { ... } OBJ18 |
union { ... } OBJ18 |
union { ... } OBJ19 |
union { ... } OBJ19 |
union { ... } OBJ2 |
union { ... } OBJ2 |
union { ... } OBJ20 |
union { ... } OBJ20 |
union { ... } OBJ21 |
union { ... } OBJ21 |
union { ... } OBJ22 |
union { ... } OBJ22 |
union { ... } OBJ23 |
union { ... } OBJ23 |
union { ... } OBJ24 |
union { ... } OBJ24 |
union { ... } OBJ25 |
union { ... } OBJ25 |
union { ... } OBJ26 |
union { ... } OBJ26 |
union { ... } OBJ27 |
union { ... } OBJ27 |
union { ... } OBJ28 |
union { ... } OBJ28 |
union { ... } OBJ29 |
union { ... } OBJ29 |
union { ... } OBJ3 |
union { ... } OBJ3 |
union { ... } OBJ30 |
union { ... } OBJ30 |
union { ... } OBJ31 |
union { ... } OBJ31 |
union { ... } OBJ4 |
union { ... } OBJ4 |
union { ... } OBJ5 |
union { ... } OBJ5 |
union { ... } OBJ6 |
union { ... } OBJ6 |
union { ... } OBJ7 |
union { ... } OBJ7 |
union { ... } OBJ8 |
union { ... } OBJ8 |
union { ... } OBJ9 |
union { ... } OBJ9 |
__IOM uint32_t OVIE |
[18..18] Overflow Interrupt Enable
__IM uint32_t PNEXT |
[31..24] Pointer to Next Message Object
__IM uint32_t PPREV |
[23..16] Pointer to Previous Message Object
__IOM uint32_t PRI |
[31..30] Priority Class
__IOM uint32_t reg |
(@ 0x00000F00) Message Object 0 Function Control Register
(@ 0x00000F04) Message Object 0 FIFO/Gateway Pointer Register
(@ 0x00000F08) Message Object 0 Interrupt Pointer Register
(@ 0x00000F0C) Message Object 0 Acceptance Mask Register
(@ 0x00000F10) Message Object 0 Data Register Low
(@ 0x00000F14) Message Object 0 Data Register High
(@ 0x00000F18) Message Object 0 Arbitration Register
(@ 0x00000F20) Message Object 1 Function Control Register
(@ 0x00000F24) Message Object 1 FIFO/Gateway Pointer Register
(@ 0x00000F28) Message Object 1 Interrupt Pointer Register
(@ 0x00000F2C) Message Object 1 Acceptance Mask Register
(@ 0x00000F30) Message Object 1 Data Register Low
(@ 0x00000F34) Message Object 1 Data Register High
(@ 0x00000F38) Message Object 1 Arbitration Register
(@ 0x00000F40) Message Object 2 Function Control Register
(@ 0x00000F44) Message Object 2 FIFO/Gateway Pointer Register
(@ 0x00000F48) Message Object 2 Interrupt Pointer Register
(@ 0x00000F4C) Message Object 2 Acceptance Mask Register
(@ 0x00000F50) Message Object 2 Data Register Low
(@ 0x00000F54) Message Object 2 Data Register High
(@ 0x00000F58) Message Object 2 Arbitration Register
(@ 0x00000F60) Message Object 3 Function Control Register
(@ 0x00000F64) Message Object 3 FIFO/Gateway Pointer Register
(@ 0x00000F68) Message Object 3 Interrupt Pointer Register
(@ 0x00000F6C) Message Object 3 Acceptance Mask Register
(@ 0x00000F70) Message Object 3 Data Register Low
(@ 0x00000F74) Message Object 3 Data Register High
(@ 0x00000F78) Message Object 3 Arbitration Register
(@ 0x00000F80) Message Object 4 Function Control Register
(@ 0x00000F84) Message Object 4 FIFO/Gateway Pointer Register
(@ 0x00000F88) Message Object 4 Interrupt Pointer Register
(@ 0x00000F8C) Message Object 4 Acceptance Mask Register
(@ 0x00000F90) Message Object 4 Data Register Low
(@ 0x00000F94) Message Object 4 Data Register High
(@ 0x00000F98) Message Object 4 Arbitration Register
(@ 0x00000FA0) Message Object 5 Function Control Register
(@ 0x00000FA4) Message Object 5 FIFO/Gateway Pointer Register
(@ 0x00000FA8) Message Object 5 Interrupt Pointer Register
(@ 0x00000FAC) Message Object 5 Acceptance Mask Register
(@ 0x00000FB0) Message Object 5 Data Register Low
(@ 0x00000FB4) Message Object 5 Data Register High
(@ 0x00000FB8) Message Object 5 Arbitration Register
(@ 0x00000FC0) Message Object 6 Function Control Register
(@ 0x00000FC4) Message Object 6 FIFO/Gateway Pointer Register
(@ 0x00000FC8) Message Object 6 Interrupt Pointer Register
(@ 0x00000FCC) Message Object 6 Acceptance Mask Register
(@ 0x00000FD0) Message Object 6 Data Register Low
(@ 0x00000FD4) Message Object 6 Data Register High
(@ 0x00000FD8) Message Object 6 Arbitration Register
(@ 0x00000FE0) Message Object 7 Function Control Register
(@ 0x00000FE4) Message Object 7 FIFO/Gateway Pointer Register
(@ 0x00000FE8) Message Object 7 Interrupt Pointer Register
(@ 0x00000FEC) Message Object 7 Acceptance Mask Register
(@ 0x00000FF0) Message Object 7 Data Register Low
(@ 0x00000FF4) Message Object 7 Data Register High
(@ 0x00000FF8) Message Object 7 Arbitration Register
(@ 0x00001000) Message Object 8 Function Control Register
(@ 0x00001004) Message Object 8 FIFO/Gateway Pointer Register
(@ 0x00001008) Message Object 8 Interrupt Pointer Register
(@ 0x0000100C) Message Object 8 Acceptance Mask Register
(@ 0x00001010) Message Object 8 Data Register Low
(@ 0x00001014) Message Object 8 Data Register High
(@ 0x00001018) Message Object 8 Arbitration Register
(@ 0x00001020) Message Object 9 Function Control Register
(@ 0x00001024) Message Object 9 FIFO/Gateway Pointer Register
(@ 0x00001028) Message Object 9 Interrupt Pointer Register
(@ 0x0000102C) Message Object 9 Acceptance Mask Register
(@ 0x00001030) Message Object 9 Data Register Low
(@ 0x00001034) Message Object 9 Data Register High
(@ 0x00001038) Message Object 9 Arbitration Register
(@ 0x00001040) Message Object 10 Function Control Register
(@ 0x00001044) Message Object 10 FIFO/Gateway Pointer Register
(@ 0x00001048) Message Object 10 Interrupt Pointer Register
(@ 0x0000104C) Message Object 10 Acceptance Mask Register
(@ 0x00001050) Message Object 10 Data Register Low
(@ 0x00001054) Message Object 10 Data Register High
(@ 0x00001058) Message Object 10 Arbitration Register
(@ 0x00001060) Message Object 11 Function Control Register
(@ 0x00001064) Message Object 11 FIFO/Gateway Pointer Register
(@ 0x00001068) Message Object 11 Interrupt Pointer Register
(@ 0x0000106C) Message Object 11 Acceptance Mask Register
(@ 0x00001070) Message Object 11 Data Register Low
(@ 0x00001074) Message Object 11 Data Register High
(@ 0x00001078) Message Object 11 Arbitration Register
(@ 0x00001080) Message Object 12 Function Control Register
(@ 0x00001084) Message Object 12 FIFO/Gateway Pointer Register
(@ 0x00001088) Message Object 12 Interrupt Pointer Register
(@ 0x0000108C) Message Object 12 Acceptance Mask Register
(@ 0x00001090) Message Object 12 Data Register Low
(@ 0x00001094) Message Object 12 Data Register High
(@ 0x00001098) Message Object 12 Arbitration Register
(@ 0x000010A0) Message Object 13 Function Control Register
(@ 0x000010A4) Message Object 13 FIFO/Gateway Pointer Register
(@ 0x000010A8) Message Object 13 Interrupt Pointer Register
(@ 0x000010AC) Message Object 13 Acceptance Mask Register
(@ 0x000010B0) Message Object 13 Data Register Low
(@ 0x000010B4) Message Object 13 Data Register High
(@ 0x000010B8) Message Object 13 Arbitration Register
(@ 0x000010C0) Message Object 14 Function Control Register
(@ 0x000010C4) Message Object 14 FIFO/Gateway Pointer Register
(@ 0x000010C8) Message Object 14 Interrupt Pointer Register
(@ 0x000010CC) Message Object 14 Acceptance Mask Register
(@ 0x000010D0) Message Object 14 Data Register Low
(@ 0x000010D4) Message Object 14 Data Register High
(@ 0x000010D8) Message Object 14 Arbitration Register
(@ 0x000010E0) Message Object 15 Function Control Register
(@ 0x000010E4) Message Object 15 FIFO/Gateway Pointer Register
(@ 0x000010E8) Message Object 15 Interrupt Pointer Register
(@ 0x000010EC) Message Object 15 Acceptance Mask Register
(@ 0x000010F0) Message Object 15 Data Register Low
(@ 0x000010F4) Message Object 15 Data Register High
(@ 0x000010F8) Message Object 15 Arbitration Register
(@ 0x00001100) Message Object 16 Function Control Register
(@ 0x00001104) Message Object 16 FIFO/Gateway Pointer Register
(@ 0x00001108) Message Object 16 Interrupt Pointer Register
(@ 0x0000110C) Message Object 16 Acceptance Mask Register
(@ 0x00001110) Message Object 16 Data Register Low
(@ 0x00001114) Message Object 16 Data Register High
(@ 0x00001118) Message Object 16 Arbitration Register
(@ 0x00001120) Message Object 17 Function Control Register
(@ 0x00001124) Message Object 17 FIFO/Gateway Pointer Register
(@ 0x00001128) Message Object 17 Interrupt Pointer Register
(@ 0x0000112C) Message Object 17 Acceptance Mask Register
(@ 0x00001130) Message Object 17 Data Register Low
(@ 0x00001134) Message Object 17 Data Register High
(@ 0x00001138) Message Object 17 Arbitration Register
(@ 0x00001140) Message Object 18 Function Control Register
(@ 0x00001144) Message Object 18 FIFO/Gateway Pointer Register
(@ 0x00001148) Message Object 18 Interrupt Pointer Register
(@ 0x0000114C) Message Object 18 Acceptance Mask Register
(@ 0x00001150) Message Object 18 Data Register Low
(@ 0x00001154) Message Object 18 Data Register High
(@ 0x00001158) Message Object 18 Arbitration Register
(@ 0x00001160) Message Object 19 Function Control Register
(@ 0x00001164) Message Object 19 FIFO/Gateway Pointer Register
(@ 0x00001168) Message Object 19 Interrupt Pointer Register
(@ 0x0000116C) Message Object 19 Acceptance Mask Register
(@ 0x00001170) Message Object 19 Data Register Low
(@ 0x00001174) Message Object 19 Data Register High
(@ 0x00001178) Message Object 19 Arbitration Register
(@ 0x00001180) Message Object 20 Function Control Register
(@ 0x00001184) Message Object 20 FIFO/Gateway Pointer Register
(@ 0x00001188) Message Object 20 Interrupt Pointer Register
(@ 0x0000118C) Message Object 20 Acceptance Mask Register
(@ 0x00001190) Message Object 20 Data Register Low
(@ 0x00001194) Message Object 20 Data Register High
(@ 0x00001198) Message Object 20 Arbitration Register
(@ 0x000011A0) Message Object 21 Function Control Register
(@ 0x000011A4) Message Object 21 FIFO/Gateway Pointer Register
(@ 0x000011A8) Message Object 21 Interrupt Pointer Register
(@ 0x000011AC) Message Object 21 Acceptance Mask Register
(@ 0x000011B0) Message Object 21 Data Register Low
(@ 0x000011B4) Message Object 21 Data Register High
(@ 0x000011B8) Message Object 21 Arbitration Register
(@ 0x000011C0) Message Object 22 Function Control Register
(@ 0x000011C4) Message Object 22 FIFO/Gateway Pointer Register
(@ 0x000011C8) Message Object 22 Interrupt Pointer Register
(@ 0x000011CC) Message Object 22 Acceptance Mask Register
(@ 0x000011D0) Message Object 22 Data Register Low
(@ 0x000011D4) Message Object 22 Data Register High
(@ 0x000011D8) Message Object 22 Arbitration Register
(@ 0x000011E0) Message Object 23 Function Control Register
(@ 0x000011E4) Message Object 23 FIFO/Gateway Pointer Register
(@ 0x000011E8) Message Object 23 Interrupt Pointer Register
(@ 0x000011EC) Message Object 23 Acceptance Mask Register
(@ 0x000011F0) Message Object 23 Data Register Low
(@ 0x000011F4) Message Object 23 Data Register High
(@ 0x000011F8) Message Object 23 Arbitration Register
(@ 0x00001200) Message Object 24 Function Control Register
(@ 0x00001204) Message Object 24 FIFO/Gateway Pointer Register
(@ 0x00001208) Message Object 24 Interrupt Pointer Register
(@ 0x0000120C) Message Object 24 Acceptance Mask Register
(@ 0x00001210) Message Object 24 Data Register Low
(@ 0x00001214) Message Object 24 Data Register High
(@ 0x00001218) Message Object 24 Arbitration Register
(@ 0x00001220) Message Object 25 Function Control Register
(@ 0x00001224) Message Object 25 FIFO/Gateway Pointer Register
(@ 0x00001228) Message Object 25 Interrupt Pointer Register
(@ 0x0000122C) Message Object 25 Acceptance Mask Register
(@ 0x00001230) Message Object 25 Data Register Low
(@ 0x00001234) Message Object 25 Data Register High
(@ 0x00001238) Message Object 25 Arbitration Register
(@ 0x00001240) Message Object 26 Function Control Register
(@ 0x00001244) Message Object 26 FIFO/Gateway Pointer Register
(@ 0x00001248) Message Object 26 Interrupt Pointer Register
(@ 0x0000124C) Message Object 26 Acceptance Mask Register
(@ 0x00001250) Message Object 26 Data Register Low
(@ 0x00001254) Message Object 26 Data Register High
(@ 0x00001258) Message Object 26 Arbitration Register
(@ 0x00001260) Message Object 27 Function Control Register
(@ 0x00001264) Message Object 27 FIFO/Gateway Pointer Register
(@ 0x00001268) Message Object 27 Interrupt Pointer Register
(@ 0x0000126C) Message Object 27 Acceptance Mask Register
(@ 0x00001270) Message Object 27 Data Register Low
(@ 0x00001274) Message Object 27 Data Register High
(@ 0x00001278) Message Object 27 Arbitration Register
(@ 0x00001280) Message Object 28 Function Control Register
(@ 0x00001284) Message Object 28 FIFO/Gateway Pointer Register
(@ 0x00001288) Message Object 28 Interrupt Pointer Register
(@ 0x0000128C) Message Object 28 Acceptance Mask Register
(@ 0x00001290) Message Object 28 Data Register Low
(@ 0x00001294) Message Object 28 Data Register High
(@ 0x00001298) Message Object 28 Arbitration Register
(@ 0x000012A0) Message Object 29 Function Control Register
(@ 0x000012A4) Message Object 29 FIFO/Gateway Pointer Register
(@ 0x000012A8) Message Object 29 Interrupt Pointer Register
(@ 0x000012AC) Message Object 29 Acceptance Mask Register
(@ 0x000012B0) Message Object 29 Data Register Low
(@ 0x000012B4) Message Object 29 Data Register High
(@ 0x000012B8) Message Object 29 Arbitration Register
(@ 0x000012C0) Message Object 30 Function Control Register
(@ 0x000012C4) Message Object 30 FIFO/Gateway Pointer Register
(@ 0x000012C8) Message Object 30 Interrupt Pointer Register
(@ 0x000012CC) Message Object 30 Acceptance Mask Register
(@ 0x000012D0) Message Object 30 Data Register Low
(@ 0x000012D4) Message Object 30 Data Register High
(@ 0x000012D8) Message Object 30 Arbitration Register
(@ 0x000012E0) Message Object 31 Function Control Register
(@ 0x000012E4) Message Object 31 FIFO/Gateway Pointer Register
(@ 0x000012E8) Message Object 31 Interrupt Pointer Register
(@ 0x000012EC) Message Object 31 Acceptance Mask Register
(@ 0x000012F0) Message Object 31 Data Register Low
(@ 0x000012F4) Message Object 31 Data Register High
(@ 0x000012F8) Message Object 31 Arbitration Register
__OM uint32_t reg |
(@ 0x00000F1C) Message Object 0 Control Register
(@ 0x00000F3C) Message Object 1 Control Register
(@ 0x00000F5C) Message Object 2 Control Register
(@ 0x00000F7C) Message Object 3 Control Register
(@ 0x00000F9C) Message Object 4 Control Register
(@ 0x00000FBC) Message Object 5 Control Register
(@ 0x00000FDC) Message Object 6 Control Register
(@ 0x00000FFC) Message Object 7 Control Register
(@ 0x0000101C) Message Object 8 Control Register
(@ 0x0000103C) Message Object 9 Control Register
(@ 0x0000105C) Message Object 10 Control Register
(@ 0x0000107C) Message Object 11 Control Register
(@ 0x0000109C) Message Object 12 Control Register
(@ 0x000010BC) Message Object 13 Control Register
(@ 0x000010DC) Message Object 14 Control Register
(@ 0x000010FC) Message Object 15 Control Register
(@ 0x0000111C) Message Object 16 Control Register
(@ 0x0000113C) Message Object 17 Control Register
(@ 0x0000115C) Message Object 18 Control Register
(@ 0x0000117C) Message Object 19 Control Register
(@ 0x0000119C) Message Object 20 Control Register
(@ 0x000011BC) Message Object 21 Control Register
(@ 0x000011DC) Message Object 22 Control Register
(@ 0x000011FC) Message Object 23 Control Register
(@ 0x0000121C) Message Object 24 Control Register
(@ 0x0000123C) Message Object 25 Control Register
(@ 0x0000125C) Message Object 26 Control Register
(@ 0x0000127C) Message Object 27 Control Register
(@ 0x0000129C) Message Object 28 Control Register
(@ 0x000012BC) Message Object 29 Control Register
(@ 0x000012DC) Message Object 30 Control Register
(@ 0x000012FC) Message Object 31 Control Register
__IM uint32_t reg |
(@ 0x00000F1C) Message Object 0 Status Register
(@ 0x00000F3C) Message Object 1 Status Register
(@ 0x00000F5C) Message Object 2 Status Register
(@ 0x00000F7C) Message Object 3 Status Register
(@ 0x00000F9C) Message Object 4 Status Register
(@ 0x00000FBC) Message Object 5 Status Register
(@ 0x00000FDC) Message Object 6 Status Register
(@ 0x00000FFC) Message Object 7 Status Register
(@ 0x0000101C) Message Object 8 Status Register
(@ 0x0000103C) Message Object 9 Status Register
(@ 0x0000105C) Message Object 10 Status Register
(@ 0x0000107C) Message Object 11 Status Register
(@ 0x0000109C) Message Object 12 Status Register
(@ 0x000010BC) Message Object 13 Status Register
(@ 0x000010DC) Message Object 14 Status Register
(@ 0x000010FC) Message Object 15 Status Register
(@ 0x0000111C) Message Object 16 Status Register
(@ 0x0000113C) Message Object 17 Status Register
(@ 0x0000115C) Message Object 18 Status Register
(@ 0x0000117C) Message Object 19 Status Register
(@ 0x0000119C) Message Object 20 Status Register
(@ 0x000011BC) Message Object 21 Status Register
(@ 0x000011DC) Message Object 22 Status Register
(@ 0x000011FC) Message Object 23 Status Register
(@ 0x0000121C) Message Object 24 Status Register
(@ 0x0000123C) Message Object 25 Status Register
(@ 0x0000125C) Message Object 26 Status Register
(@ 0x0000127C) Message Object 27 Status Register
(@ 0x0000129C) Message Object 28 Status Register
(@ 0x000012BC) Message Object 29 Status Register
(@ 0x000012DC) Message Object 30 Status Register
(@ 0x000012FC) Message Object 31 Status Register
__OM uint32_t RESDIR_SETDIR |
[11..11] Reset Message Direction
__IM uint32_t RESERVED |
__OM uint32_t RESMSGLST |
[4..4] Reset Message Lost
__OM uint32_t RESMSGVAL |
[5..5] Reset Message Valid
__OM uint32_t RESNEWDAT |
[3..3] Reset New Data
__OM uint32_t RESRTSEL |
[6..6] Reset Receive/Transmit Selected
__OM uint32_t RESRXEN |
[7..7] Reset Receive Enable
__OM uint32_t RESRXPND |
[0..0] Reset Receive Pending
__OM uint32_t RESRXUPD |
[2..2] Reset Receive Updating
__OM uint32_t RESTXEN0 |
[9..9] Reset Transmit Enable 0
__OM uint32_t RESTXEN1 |
[10..10] Reset Transmit Enable 1
__OM uint32_t RESTXPND |
[1..1] Reset Transmit Pending
__OM uint32_t RESTXRQ |
[8..8] Reset Transmit Request
__IOM uint32_t RMM |
[21..21] Transmit Object Remote Monitoring
__IM uint32_t RTSEL |
[6..6] Receive/Transmit Selected
__IM uint32_t RXEN |
[7..7] Receive Enable
__IOM uint32_t RXIE |
[16..16] Receive Interrupt Enable
__IOM uint32_t RXINP |
[3..0] Receive Interrupt Node Pointer
__IM uint32_t RXPND |
[0..0] Receive Pending
__IM uint32_t RXUPD |
[2..2] Receive Updating
__IOM uint32_t SDT |
[22..22] Single Data Transfer
__IOM uint32_t SEL |
[31..24] Object Select Pointer
__OM uint32_t SETDIR |
[27..27] Set Message Direction
__OM uint32_t SETMSGLST |
[20..20] Set Message Lost
__OM uint32_t SETMSGVAL |
[21..21] Set Message Valid
__OM uint32_t SETNEWDAT |
[19..19] Set New Data
__OM uint32_t SETRTSEL |
[22..22] Set Receive/Transmit Selected
__OM uint32_t SETRXEN |
[23..23] Set Receive Enable
__OM uint32_t SETRXPND |
[16..16] Set Receive Pending
__OM uint32_t SETRXUPD |
[18..18] Set Receive Updating
__OM uint32_t SETTXEN0 |
[25..25] Set Transmit Enable 0
__OM uint32_t SETTXEN1 |
[26..26] Set Transmit Enable 1
__OM uint32_t SETTXPND |
[17..17] Set Transmit Pending
__OM uint32_t SETTXRQ |
[24..24] Set Transmit Request
__IOM uint32_t STT |
[23..23] Single Transmit Trial
__IOM uint32_t TOP |
[15..8] Top Pointer
__IM uint32_t TXEN0 |
[9..9] Transmit Enable 0
__IM uint32_t TXEN1 |
[10..10] Transmit Enable 1
__IOM uint32_t TXIE |
[17..17] Transmit Interrupt Enable
__IOM uint32_t TXINP |
[7..4] Transmit Interrupt Node Pointer
__IM uint32_t TXPND |
[1..1] Transmit Pending
__IM uint32_t TXRQ |
[8..8] Transmit Request