Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
MEMCTRL_Type Struct Reference

Detailed Description

MEMCTRL (MEMCTRL)

#include <tle989x.h>

Data Fields

union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFSTS: 1
 
      __IM uint32_t   SBFSTS: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DBFSTSCLR: 1
 
      __OM uint32_t   SBFSTSCLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTSC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DBFSTSSET: 1
 
      __OM uint32_t   SBFSTSSET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTSS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFA: 32
 
   }   bit
 
DBFA
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   SBFA: 32
 
   }   bit
 
SBFA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NMIDSEN: 1
 
      __IOM uint32_t   NMIPSEN: 1
 
      __IOM uint32_t   NMICDEN: 1
 
      __IOM uint32_t   NMINVM0EN: 1
 
      __IOM uint32_t   NMINVM1EN: 1
 
      __IOM uint32_t   NMIMAP0EN: 1
 
      __IOM uint32_t   NMIMAP1EN: 1
 
      __IOM uint32_t   NMIWDTEN: 1
 
      __IOM uint32_t   NMISTOFEN: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMICON
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NMIDS: 1
 
      __IM uint32_t   NMIPS: 1
 
      __IM uint32_t   NMICD: 1
 
      __IM uint32_t   NMINVM0: 1
 
      __IM uint32_t   NMINVM1: 1
 
      __IM uint32_t   NMIMAP0: 1
 
      __IM uint32_t   NMIMAP1: 1
 
      __IM uint32_t   NMIWDT: 1
 
      __IM uint32_t   NMISTOF: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIDSCLR: 1
 
      __OM uint32_t   NMIPSCLR: 1
 
      __OM uint32_t   NMICDCLR: 1
 
      __OM uint32_t   NMINVM0CLR: 1
 
      __OM uint32_t   NMINVM1CLR: 1
 
      __OM uint32_t   NMIMAP0CLR: 1
 
      __OM uint32_t   NMIMAP1CLR: 1
 
      __OM uint32_t   NMIWDTCLR: 1
 
      __OM uint32_t   NMISTOFCLR: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISRC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIDSSET: 1
 
      __OM uint32_t   NMIPSSET: 1
 
      __OM uint32_t   NMICDSET: 1
 
      __OM uint32_t   NMINVM0SET: 1
 
      __OM uint32_t   NMINVM1SET: 1
 
      __OM uint32_t   NMIMAP0SET: 1
 
      __OM uint32_t   NMIMAP1SET: 1
 
      __OM uint32_t   NMIWDTSET: 1
 
      __OM uint32_t   NMISTOFSET: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISRS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NVM0OPCIEN: 1
 
      __IOM uint32_t   NVM1OPCIEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NVM0OPC: 1
 
      __IM uint32_t   NVM1OPC: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0OPCLR: 1
 
      __OM uint32_t   NVM1OPCLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
ISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0OPSET: 1
 
      __OM uint32_t   NVM1OPSET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
ISS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NVM0_PROT_ERR: 1
 
      __IM uint32_t   NVM0_ADDR_ERR: 1
 
      __IM uint32_t   NVM0_SFR_PROT_ERR: 1
 
      __IM uint32_t   NVM0_SFR_ADDR_ERR: 1
 
      __IM uint32_t   NVM1_PROT_ERR: 1
 
      __IM uint32_t   NVM1_ADDR_ERR: 1
 
      __IM uint32_t   NVM1_SFR_PROT_ERR: 1
 
      __IM uint32_t   NVM1_SFR_ADDR_ERR: 1
 
      __IM uint32_t   ROM_PROT_ERR: 1
 
      __IM uint32_t   DSRAM_PROT_ERR: 1
 
      __IM uint32_t   PSRAM_PROT_ERR: 1
 
      uint32_t   __pad0__: 5
 
      __IM uint32_t   DSSBE: 1
 
      __IM uint32_t   PSSBE: 1
 
      __IM uint32_t   CDSBE: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM0_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM0_SFR_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM0_SFR_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM1_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM1_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM1_SFR_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM1_SFR_ADDR_ERRCLR: 1
 
      __OM uint32_t   ROM_PROT_ERRCLR: 1
 
      __OM uint32_t   DSRAM_PROT_ERRCLR: 1
 
      __OM uint32_t   PSRAM_PROT_ERRCLR: 1
 
      uint32_t   __pad0__: 5
 
      __OM uint32_t   DSSBECLR: 1
 
      __OM uint32_t   PSSBECLR: 1
 
      __OM uint32_t   CDSBECLR: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTSC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0_PROT_ERRSET: 1
 
      __OM uint32_t   NVM0_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM0_SFR_PROT_ERRSET: 1
 
      __OM uint32_t   NVM0_SFR_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM1_PROT_ERRSET: 1
 
      __OM uint32_t   NVM1_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM1_SFR_PROT_ERRSET: 1
 
      __OM uint32_t   NVM1_SFR_ADDR_ERRSET: 1
 
      __OM uint32_t   ROM_PROT_ERRSET: 1
 
      __OM uint32_t   DSRAM_PROT_ERRSET: 1
 
      __OM uint32_t   PSRAM_PROT_ERRSET: 1
 
      uint32_t   __pad0__: 5
 
      __OM uint32_t   DSSBESET: 1
 
      __OM uint32_t   PSSBESET: 1
 
      __OM uint32_t   CDSBESET: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTSS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ROMAWSEN: 1
 
      __IOM uint32_t   MEM_DBG_ERR: 1
 
      __IOM uint32_t   CACHEEN: 1
 
      uint32_t   __pad0__: 29
 
   }   bit
 
MEMCONTROL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DSECCWR: 7
 
      __IOM uint32_t   DSECCCDIS: 1
 
      __IOM uint32_t   PSECCWR: 7
 
      __IOM uint32_t   PSECCCDIS: 1
 
      __IOM uint32_t   CDECCWR: 7
 
      __IOM uint32_t   CDECCCDIS: 1
 
      uint32_t   __pad0__: 8
 
   }   bit
 
ECCCTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DSECCRD: 7
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   PSECCRD: 7
 
      uint32_t   __pad1__: 17
 
   }   bit
 
ECCRDAT0
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   CDECCRD0: 7
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   CDECCRD1: 7
 
      uint32_t   __pad1__: 1
 
      __IM uint32_t   CDECCRD2: 7
 
      uint32_t   __pad2__: 1
 
      __IM uint32_t   CDECCRD3: 7
 
      uint32_t   __pad3__: 1
 
   }   bit
 
ECCRDAT1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_PROT_0: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
FW_PROT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_PROT_ADDR_LOW: 32
 
   }   bit
 
FW_PROT_ADDR_LOW
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_PROT_ADDR_HIGH: 32
 
   }   bit
 
FW_PROT_ADDR_HIGH
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_PROT_ADDR_HIGH1: 32
 
   }   bit
 
FW_PROT_ADDR_HIGH1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   UBSLAPIST: 15
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   TESTAPIST: 15
 
      uint32_t   __pad1__: 1
 
   }   bit
 
ROM_SEGM_ADDR0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SECEXITST: 15
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   SECST: 15
 
      uint32_t   __pad1__: 1
 
   }   bit
 
ROM_SEGM_ADDR1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MSIZE: 6
 
      uint32_t   __pad0__: 26
 
   }   bit
 
MCTRL_SIZE
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_SCRATCH_1: 32
 
   }   bit
 
FW_SCRATCH_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_SCRATCH_2: 32
 
   }   bit
 
FW_SCRATCH_2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_SCRATCH_3: 32
 
   }   bit
 
FW_SCRATCH_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_SCRATCH_4: 32
 
   }   bit
 
FW_SCRATCH_4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FW_SCRATCH_5: 32
 
   }   bit
 
FW_SCRATCH_5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   USER_VTOR: 32
 
   }   bit
 
FW_USER_VTOR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   USER_STACK: 32
 
   }   bit
 
FW_USER_STACK
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   USER_DEMCR: 32
 
   }   bit
 
FW_USER_DEMCR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SECURE_STACK: 32
 
   }   bit
 
FW_SECURE_STACK
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MRAMINITSTS: 1
 
      __IOM uint32_t   PG100TP_CHKS_ERR: 1
 
      __IOM uint32_t   SPARE_PROT: 2
 
      uint32_t   __pad0__: 12
 
      __IOM uint32_t   MAPRAM1_MBISTEXEC: 1
 
      __IOM uint32_t   MAPRAM0_MBISTEXEC: 1
 
      __IOM uint32_t   CDRAM_MBISTEXEC: 1
 
      __IOM uint32_t   CTRAM_MBISTEXEC: 1
 
      __IOM uint32_t   CMRAM_MBISTEXEC: 1
 
      __IOM uint32_t   PSRAM_MBISTEXEC: 1
 
      __IOM uint32_t   DSRAM_MBISTEXEC: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   MAPRAM1_MBISTFAIL: 1
 
      __IOM uint32_t   MAPRAM0_MBISTFAIL: 1
 
      __IOM uint32_t   CDRAM_MBISTFAIL: 1
 
      __IOM uint32_t   CTRAM_MBISTFAIL: 1
 
      __IOM uint32_t   CMRAM_MBISTFAIL: 1
 
      __IOM uint32_t   PSRAM_MBISTFAIL: 1
 
      __IOM uint32_t   DSRAM_MBISTFAIL: 1
 
      uint32_t   __pad2__: 1
 
   }   bit
 
SYS_STRTUP_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RDEN_UBSL: 1
 
      __IOM uint32_t   WREN_UBSL: 1
 
      __IOM uint32_t   RDEN_UCODE: 1
 
      __IOM uint32_t   WREN_UCODE: 1
 
      __IOM uint32_t   RDEN_UDATA: 1
 
      __IOM uint32_t   WREN_UDATA: 1
 
      __IOM uint32_t   WREN_CS0: 1
 
      __IOM uint32_t   WREN_CS1: 1
 
      __IOM uint32_t   RDEN_CS0: 1
 
      __IOM uint32_t   RDEN_CS1: 1
 
      __IOM uint32_t   WREN_CRYPTO: 1
 
      __IOM uint32_t   WREN_MCTRL: 1
 
      __IOM uint32_t   SFR_PROT_DIS: 1
 
      __IOM uint32_t   RDEN_CRYPTO: 1
 
      __IOM uint32_t   RDEN_MCTRL: 1
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   ROM_PROT_DIS: 1
 
      __IOM uint32_t   DSRAM_PROT_DIS: 1
 
      __IOM uint32_t   PSRAM_PROT_DIS: 1
 
      __IOM uint32_t   NVM0_PROT_DIS: 1
 
      __IOM uint32_t   NVM1_PROT_DIS: 1
 
      __IOM uint32_t   NVMSFR_PROT_DIS: 1
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   UBSL_SIZE: 3
 
      __IOM uint32_t   UBSL_PRIV: 1
 
      uint32_t   __pad2__: 4
 
   }   bit
 
NVM_PROT_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FSM_STATE_ID: 12
 
      uint32_t   __pad0__: 4
 
      __IOM uint32_t   PRG_FLAG: 8
 
      uint32_t   __pad1__: 8
 
   }   bit
 
NVM_OP_FSM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OP_STS: 32
 
   }   bit
 
NVM_OP_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OP_RESULT: 32
 
   }   bit
 
NVM_OP_RESULT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SECTORINFO: 6
 
      __IOM uint32_t   SASTATUS: 2
 
      uint32_t   __pad0__: 24
 
   }   bit
 
MEMSTAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STOF_EN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
STACK_OVF_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   STOF_ADDR_OFF_L: 13
 
      uint32_t   __pad1__: 3
 
      __IOM uint32_t   STOF_ADDR_OFF_H: 13
 
      uint32_t   __pad2__: 1
 
   }   bit
 
STACK_OVF_ADDR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   INTERCEPT_HANDLER: 32
 
   }   bit
 
INTERCEPT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STCALIB: 26
 
      uint32_t   __pad0__: 6
 
   }   bit
 
STCALIB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTIN: 1
 
      __IOM uint32_t   WDTRS: 1
 
      __IOM uint32_t   WDTEN: 1
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   WDTPR: 1
 
      __IOM uint32_t   WDTBEN: 1
 
      uint32_t   __pad1__: 26
 
   }   bit
 
SYSWDTCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTREL: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
SYSWDTREL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   WDT: 16
 
      uint32_t   __pad0__: 16
 
   }   bit
 
SYSWDT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTWINB: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
SYSWDTWINB
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 23
 
      __IOM uint32_t   MBP_EN: 7
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   TST_CTRL: 1
 
   }   bit
 
TCR1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NMIDISLOW: 15
 
      uint32_t   __pad0__: 1
 
      __IOM uint32_t   NMIDISHIGH: 15
 
      uint32_t   __pad1__: 1
 
   }   bit
 
ROM_SEGM_NMI
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SECSTOF_EN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
SECSTACK_OVF_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   SECSTOF_ADDR_OFF_L: 13
 
      uint32_t   __pad1__: 3
 
      __IOM uint32_t   SECSTOF_ADDR_OFF_H: 13
 
      uint32_t   __pad2__: 1
 
   }   bit
 
SECSTACK_OVF_ADDR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NVM0_ACCDIS: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
AEP_CTRL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFSTS: 1
 
      __IM uint32_t   SBFSTS: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DBFSTSCLR: 1
 
      __OM uint32_t   SBFSTSCLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTSC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DBFSTSSET: 1
 
      __OM uint32_t   SBFSTSSET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
BFSTSS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFA: 32
 
   }   bit
 
DBFA
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   SBFA: 32
 
   }   bit
 
SBFA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NMIDSEN: 1
 
      __IOM uint32_t   NMIPSEN: 1
 
      __IOM uint32_t   NMICDEN: 1
 
      __IOM uint32_t   NMINVM0EN: 1
 
      __IOM uint32_t   NMINVM1EN: 1
 
      __IOM uint32_t   NMIMAP0EN: 1
 
      __IOM uint32_t   NMIMAP1EN: 1
 
      __IOM uint32_t   NMIWDTEN: 1
 
      __IOM uint32_t   NMISTOFEN: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMICON
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NMIDS: 1
 
      __IM uint32_t   NMIPS: 1
 
      __IM uint32_t   NMICD: 1
 
      __IM uint32_t   NMINVM0: 1
 
      __IM uint32_t   NMINVM1: 1
 
      __IM uint32_t   NMIMAP0: 1
 
      __IM uint32_t   NMIMAP1: 1
 
      __IM uint32_t   NMIWDT: 1
 
      __IM uint32_t   NMISTOF: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIDSCLR: 1
 
      __OM uint32_t   NMIPSCLR: 1
 
      __OM uint32_t   NMICDCLR: 1
 
      __OM uint32_t   NMINVM0CLR: 1
 
      __OM uint32_t   NMINVM1CLR: 1
 
      __OM uint32_t   NMIMAP0CLR: 1
 
      __OM uint32_t   NMIMAP1CLR: 1
 
      __OM uint32_t   NMIWDTCLR: 1
 
      __OM uint32_t   NMISTOFCLR: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISRC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NMIDSSET: 1
 
      __OM uint32_t   NMIPSSET: 1
 
      __OM uint32_t   NMICDSET: 1
 
      __OM uint32_t   NMINVM0SET: 1
 
      __OM uint32_t   NMINVM1SET: 1
 
      __OM uint32_t   NMIMAP0SET: 1
 
      __OM uint32_t   NMIMAP1SET: 1
 
      __OM uint32_t   NMIWDTSET: 1
 
      __OM uint32_t   NMISTOFSET: 1
 
      uint32_t   __pad0__: 23
 
   }   bit
 
NMISRS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NVM0OPCIEN: 1
 
      __IOM uint32_t   NVM1OPCIEN: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NVM0OPC: 1
 
      __IM uint32_t   NVM1OPC: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0OPCLR: 1
 
      __OM uint32_t   NVM1OPCLR: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
ISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0OPSET: 1
 
      __OM uint32_t   NVM1OPSET: 1
 
      uint32_t   __pad0__: 30
 
   }   bit
 
ISS
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   NVM0_PROT_ERR: 1
 
      __IM uint32_t   NVM0_ADDR_ERR: 1
 
      __IM uint32_t   NVM0_SFR_PROT_ERR: 1
 
      __IM uint32_t   NVM0_SFR_ADDR_ERR: 1
 
      __IM uint32_t   NVM1_PROT_ERR: 1
 
      __IM uint32_t   NVM1_ADDR_ERR: 1
 
      __IM uint32_t   NVM1_SFR_PROT_ERR: 1
 
      __IM uint32_t   NVM1_SFR_ADDR_ERR: 1
 
      __IM uint32_t   ROM_PROT_ERR: 1
 
      __IM uint32_t   DSRAM_PROT_ERR: 1
 
      __IM uint32_t   PSRAM_PROT_ERR: 1
 
      uint32_t   __pad0__: 5
 
      __IM uint32_t   DSSBE: 1
 
      __IM uint32_t   PSSBE: 1
 
      __IM uint32_t   CDSBE: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM0_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM0_SFR_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM0_SFR_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM1_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM1_ADDR_ERRCLR: 1
 
      __OM uint32_t   NVM1_SFR_PROT_ERRCLR: 1
 
      __OM uint32_t   NVM1_SFR_ADDR_ERRCLR: 1
 
      __OM uint32_t   ROM_PROT_ERRCLR: 1
 
      __OM uint32_t   DSRAM_PROT_ERRCLR: 1
 
      __OM uint32_t   PSRAM_PROT_ERRCLR: 1
 
      uint32_t   __pad0__: 5
 
      __OM uint32_t   DSSBECLR: 1
 
      __OM uint32_t   PSSBECLR: 1
 
      __OM uint32_t   CDSBECLR: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTSC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   NVM0_PROT_ERRSET: 1
 
      __OM uint32_t   NVM0_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM0_SFR_PROT_ERRSET: 1
 
      __OM uint32_t   NVM0_SFR_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM1_PROT_ERRSET: 1
 
      __OM uint32_t   NVM1_ADDR_ERRSET: 1
 
      __OM uint32_t   NVM1_SFR_PROT_ERRSET: 1
 
      __OM uint32_t   NVM1_SFR_ADDR_ERRSET: 1
 
      __OM uint32_t   ROM_PROT_ERRSET: 1
 
      __OM uint32_t   DSRAM_PROT_ERRSET: 1
 
      __OM uint32_t   PSRAM_PROT_ERRSET: 1
 
      uint32_t   __pad0__: 5
 
      __OM uint32_t   DSSBESET: 1
 
      __OM uint32_t   PSSBESET: 1
 
      __OM uint32_t   CDSBESET: 1
 
      uint32_t   __pad1__: 13
 
   }   bit
 
MEMSTSS
 
__IM uint32_t RESERVED [23]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OP_STS: 32
 
   }   bit
 
NVM_OP_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OP_RESULT: 32
 
   }   bit
 
NVM_OP_RESULT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SECTORINFO: 6
 
      __IOM uint32_t   SASTATUS: 2
 
      uint32_t   __pad0__: 24
 
   }   bit
 
MEMSTAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STOF_EN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
STACK_OVF_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   STOF_ADDR_OFF_L: 13
 
      uint32_t   __pad1__: 3
 
      __IOM uint32_t   STOF_ADDR_OFF_H: 13
 
      uint32_t   __pad2__: 1
 
   }   bit
 
STACK_OVF_ADDR
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STCALIB: 26
 
      uint32_t   __pad0__: 6
 
   }   bit
 
STCALIB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTIN: 1
 
      __IOM uint32_t   WDTRS: 1
 
      __IOM uint32_t   WDTEN: 1
 
      uint32_t   __pad0__: 1
 
      __IM uint32_t   WDTPR: 1
 
      __IOM uint32_t   WDTBEN: 1
 
      uint32_t   __pad1__: 26
 
   }   bit
 
SYSWDTCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTREL: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
SYSWDTREL
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   WDT: 16
 
      uint32_t   __pad0__: 16
 
   }   bit
 
SYSWDT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTWINB: 8
 
      uint32_t   __pad0__: 24
 
   }   bit
 
SYSWDTWINB
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ __pad3__

uint32_t __pad3__

◆ 

union { ... } AEP_CTRL

◆  [1/2]

union { ... } BFSTS

◆  [2/2]

union { ... } BFSTS

◆  [1/2]

union { ... } BFSTSC

◆  [2/2]

union { ... } BFSTSC

◆  [1/2]

union { ... } BFSTSS

◆  [2/2]

union { ... } BFSTSS

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struct { ... } bit

◆ CACHEEN

__IOM uint32_t CACHEEN

[2..2] NVM1 Cache Enable

◆ CDECCCDIS

__IOM uint32_t CDECCCDIS

[23..23] Cache Data RAM ECC Enable Bit

◆ CDECCRD0

__IM uint32_t CDECCRD0

[6..0] Cache Data RAM0 ECC Read Data

◆ CDECCRD1

__IM uint32_t CDECCRD1

[14..8] Cache Data RAM1 ECC Read Data

◆ CDECCRD2

__IM uint32_t CDECCRD2

[22..16] Cache Data RAM2 ECC Read Data

◆ CDECCRD3

__IM uint32_t CDECCRD3

[30..24] Cache Data RAM3 ECC Read Data

◆ CDECCWR

__IOM uint32_t CDECCWR

[22..16] Cache Data RAM ECC Write Data

◆ CDRAM_MBISTEXEC

__IOM uint32_t CDRAM_MBISTEXEC

[18..18] Cache Data RAM MBIST Execution Status Flag

◆ CDRAM_MBISTFAIL

__IOM uint32_t CDRAM_MBISTFAIL

[26..26] Cache Data RAM MBIST Execution Fail Flag

◆ CDSBE

__IM uint32_t CDSBE

[18..18] Cache Data RAM Single Bit Error Status

◆ CDSBECLR

__OM uint32_t CDSBECLR

[18..18] Cache Data RAM Single Bit Error Status Clear

◆ CDSBESET

__OM uint32_t CDSBESET

[18..18] Cache Data RAM Single Bit Error Status Set

◆ CMRAM_MBISTEXEC

__IOM uint32_t CMRAM_MBISTEXEC

[20..20] CAN Msg RAM MBIST Execution Status Flag

◆ CMRAM_MBISTFAIL

__IOM uint32_t CMRAM_MBISTFAIL

[28..28] CAN Msg RAM MBIST Execution Fail Flag

◆ CTRAM_MBISTEXEC

__IOM uint32_t CTRAM_MBISTEXEC

[19..19] Cache Tag RAM MBIST Execution Status Flag

◆ CTRAM_MBISTFAIL

__IOM uint32_t CTRAM_MBISTFAIL

[27..27] Cache Tag RAM MBIST Execution Fail Flag

◆ DBFA [1/3]

__IM uint32_t DBFA

[31..0] Data Bus Fault Address

◆  [2/3]

union { ... } DBFA

◆  [3/3]

union { ... } DBFA

◆ DBFSTS

__IM uint32_t DBFSTS

[0..0] Data Bus Fault Status Valid Flag

◆ DBFSTSCLR

__OM uint32_t DBFSTSCLR

[0..0] Data Bus Fault Status Valid Flag Clear

◆ DBFSTSSET

__OM uint32_t DBFSTSSET

[0..0] Data Bus Fault Status Valid Flag Set

◆ DSECCCDIS

__IOM uint32_t DSECCCDIS

[7..7] DSRAM ECC Enable Bit

◆ DSECCRD

__IM uint32_t DSECCRD

[6..0] DSRAM ECC Read Data

◆ DSECCWR

__IOM uint32_t DSECCWR

[6..0] DSRAM ECC Write Data

◆ DSRAM_MBISTEXEC

__IOM uint32_t DSRAM_MBISTEXEC

[22..22] DSRAM MBIST Execution Status Flag

◆ DSRAM_MBISTFAIL

__IOM uint32_t DSRAM_MBISTFAIL

[30..30] DSRAM MBIST Execution Fail Flag

◆ DSRAM_PROT_DIS

__IOM uint32_t DSRAM_PROT_DIS

[17..17] Disable DSRAM Protection

◆ DSRAM_PROT_ERR

__IM uint32_t DSRAM_PROT_ERR

[9..9] DSRAM Access Protection Error

◆ DSRAM_PROT_ERRCLR

__OM uint32_t DSRAM_PROT_ERRCLR

[9..9] DSRAM Access Protection Error Clear

◆ DSRAM_PROT_ERRSET

__OM uint32_t DSRAM_PROT_ERRSET

[9..9] DSRAM Access Protection Error Set

◆ DSSBE

__IM uint32_t DSSBE

[16..16] DSRAM Single Bit Error Status

◆ DSSBECLR

__OM uint32_t DSSBECLR

[16..16] DSRAM Single Bit Error Status Clear

◆ DSSBESET

__OM uint32_t DSSBESET

[16..16] DSRAM Single Bit Error Status Set

◆ 

union { ... } ECCCTRL

◆ 

union { ... } ECCRDAT0

◆ 

union { ... } ECCRDAT1

◆ FSM_STATE_ID

__IOM uint32_t FSM_STATE_ID

[11..0] State ID

◆ 

union { ... } FW_PROT

◆ FW_PROT_0

__IOM uint32_t FW_PROT_0

[0..0] Firmware Protection

◆ FW_PROT_ADDR_HIGH [1/2]

__IOM uint32_t FW_PROT_ADDR_HIGH

[31..0] Firmware Protection Address High Limit for upper protection code region

◆  [2/2]

union { ... } FW_PROT_ADDR_HIGH

◆ FW_PROT_ADDR_HIGH1 [1/2]

__IOM uint32_t FW_PROT_ADDR_HIGH1

[31..0] Firmware Protection Address High Limit 1 for lower protected code region

◆  [2/2]

union { ... } FW_PROT_ADDR_HIGH1

◆ FW_PROT_ADDR_LOW [1/2]

__IOM uint32_t FW_PROT_ADDR_LOW

[31..0] Firmware Protection Address Low Limit for upper protected code region

◆  [2/2]

union { ... } FW_PROT_ADDR_LOW

◆ FW_SCRATCH_1 [1/2]

__IOM uint32_t FW_SCRATCH_1

[31..0] FW Scratch 1

◆  [2/2]

union { ... } FW_SCRATCH_1

◆ FW_SCRATCH_2 [1/2]

__IOM uint32_t FW_SCRATCH_2

[31..0] FW Scratch 2

◆  [2/2]

union { ... } FW_SCRATCH_2

◆ FW_SCRATCH_3 [1/2]

__IOM uint32_t FW_SCRATCH_3

[31..0] FW Scratch 3

◆  [2/2]

union { ... } FW_SCRATCH_3

◆ FW_SCRATCH_4 [1/2]

__IOM uint32_t FW_SCRATCH_4

[31..0] FW Scratch 4

◆  [2/2]

union { ... } FW_SCRATCH_4

◆ FW_SCRATCH_5 [1/2]

__IOM uint32_t FW_SCRATCH_5

[31..0] FW Scratch 5

◆  [2/2]

union { ... } FW_SCRATCH_5

◆ 

union { ... } FW_SECURE_STACK

◆ 

union { ... } FW_USER_DEMCR

◆ 

union { ... } FW_USER_STACK

◆ 

union { ... } FW_USER_VTOR

◆  [1/2]

union { ... } IEN

◆  [2/2]

union { ... } IEN

◆ 

union { ... } INTERCEPT

◆ INTERCEPT_HANDLER

__IOM uint32_t INTERCEPT_HANDLER

[31..0] Intercept Handler Address

◆  [1/2]

union { ... } IS

◆  [2/2]

union { ... } IS

◆  [1/2]

union { ... } ISC

◆  [2/2]

union { ... } ISC

◆  [1/2]

union { ... } ISS

◆  [2/2]

union { ... } ISS

◆ MAPRAM0_MBISTEXEC

__IOM uint32_t MAPRAM0_MBISTEXEC

[17..17] Map RAM 0 MBIST Execution Status Flag

◆ MAPRAM0_MBISTFAIL

__IOM uint32_t MAPRAM0_MBISTFAIL

[25..25] Map RAM 0 MBIST Execution Fail Flag

◆ MAPRAM1_MBISTEXEC

__IOM uint32_t MAPRAM1_MBISTEXEC

[16..16] Map RAM 1 MBIST Execution Status Flag

◆ MAPRAM1_MBISTFAIL

__IOM uint32_t MAPRAM1_MBISTFAIL

[24..24] Map RAM 1 MBIST Execution Fail Flag

◆ MBP_EN

__IOM uint32_t MBP_EN

[29..23] MBISTPLUS test enable

◆ 

union { ... } MCTRL_SIZE

◆ MEM_DBG_ERR

__IOM uint32_t MEM_DBG_ERR

[1..1] Mem Debug Error

◆ 

union { ... } MEMCONTROL

◆  [1/2]

union { ... } MEMSTAT

◆  [2/2]

union { ... } MEMSTAT

◆  [1/2]

union { ... } MEMSTS

◆  [2/2]

union { ... } MEMSTS

◆  [1/2]

union { ... } MEMSTSC

◆  [2/2]

union { ... } MEMSTSC

◆  [1/2]

union { ... } MEMSTSS

◆  [2/2]

union { ... } MEMSTSS

◆ MRAMINITSTS

__IOM uint32_t MRAMINITSTS

[0..0] Map RAM Initialization Status

◆ MSIZE

__IOM uint32_t MSIZE

[5..0] Motor Control Library Size (MSIZE x 4kBytes)

◆ NMICD

__IM uint32_t NMICD

[2..2] Cache Data RAM Double Bit ECC Error NMI Status

◆ NMICDCLR

__OM uint32_t NMICDCLR

[2..2] Cache Data RAM Double Bit ECC Error NMI Status Clear

◆ NMICDEN

__IOM uint32_t NMICDEN

[2..2] Cache Data RAM Double Bit ECC Error NMI Enable

◆ NMICDSET

__OM uint32_t NMICDSET

[2..2] Cache Data RAM Double Bit ECC Error NMI Status Set

◆  [1/2]

union { ... } NMICON

◆  [2/2]

union { ... } NMICON

◆ NMIDISHIGH

__IOM uint32_t NMIDISHIGH

[30..16] NMI disable upper address limit

◆ NMIDISLOW

__IOM uint32_t NMIDISLOW

[14..0] NMI disable lower address limit

◆ NMIDS

__IM uint32_t NMIDS

[0..0] DSRAM Double Bit ECC Error NMI Status

◆ NMIDSCLR

__OM uint32_t NMIDSCLR

[0..0] DSRAM Double Bit ECC Error NMI Status Clear

◆ NMIDSEN

__IOM uint32_t NMIDSEN

[0..0] DSRAM Double Bit ECC Error NMI Enable

◆ NMIDSSET

__OM uint32_t NMIDSSET

[0..0] DSRAM Double Bit ECC Error NMI Status Set

◆ NMIMAP0

__IM uint32_t NMIMAP0

[5..5] NVM0 MAP Error NMI Status

◆ NMIMAP0CLR

__OM uint32_t NMIMAP0CLR

[5..5] NVM0 MAP Error NMI Status Clear

◆ NMIMAP0EN

__IOM uint32_t NMIMAP0EN

[5..5] NVM0 MAP Error NMI Enable

◆ NMIMAP0SET

__OM uint32_t NMIMAP0SET

[5..5] NVM0 MAP Error NMI Status Set

◆ NMIMAP1

__IM uint32_t NMIMAP1

[6..6] NVM1 MAP Error NMI Status

◆ NMIMAP1CLR

__OM uint32_t NMIMAP1CLR

[6..6] NVM1 MAP Error NMI Status Clear

◆ NMIMAP1EN

__IOM uint32_t NMIMAP1EN

[6..6] NVM1 MAP Error NMI Enable

◆ NMIMAP1SET

__OM uint32_t NMIMAP1SET

[6..6] NVM1 MAP Error NMI Status Set

◆ NMINVM0

__IM uint32_t NMINVM0

[3..3] NVM0 Double Bit ECC Error NMI Status

◆ NMINVM0CLR

__OM uint32_t NMINVM0CLR

[3..3] NVM 0 Double Bit ECC Error NMI Status Clear

◆ NMINVM0EN

__IOM uint32_t NMINVM0EN

[3..3] NVM0 Double Bit ECC Error NMI Enable

◆ NMINVM0SET

__OM uint32_t NMINVM0SET

[3..3] NVM 0 Double Bit ECC Error NMI Status Set

◆ NMINVM1

__IM uint32_t NMINVM1

[4..4] NVM1 Double Bit ECC Error NMI Status

◆ NMINVM1CLR

__OM uint32_t NMINVM1CLR

[4..4] NVM1 Double Bit ECC Error NMI Status Clear

◆ NMINVM1EN

__IOM uint32_t NMINVM1EN

[4..4] NVM1 Double Bit ECC Error NMI Enable

◆ NMINVM1SET

__OM uint32_t NMINVM1SET

[4..4] NVM1 Double Bit ECC Error NMI Status Set

◆ NMIPS

__IM uint32_t NMIPS

[1..1] PSRAM Double Bit ECC Error NMI Status

◆ NMIPSCLR

__OM uint32_t NMIPSCLR

[1..1] PSRAM Double Bit ECC Error NMI Status Clear

◆ NMIPSEN

__IOM uint32_t NMIPSEN

[1..1] PSRAM Double Bit ECC Error NMI Enable

◆ NMIPSSET

__OM uint32_t NMIPSSET

[1..1] PSRAM Double Bit ECC Error NMI Status Set

◆  [1/2]

union { ... } NMISR

◆  [2/2]

union { ... } NMISR

◆  [1/2]

union { ... } NMISRC

◆  [2/2]

union { ... } NMISRC

◆  [1/2]

union { ... } NMISRS

◆  [2/2]

union { ... } NMISRS

◆ NMISTOF

__IM uint32_t NMISTOF

[8..8] Stack Overflow NMI Status

◆ NMISTOFCLR

__OM uint32_t NMISTOFCLR

[8..8] Stack Overflow NMI Status Clear

◆ NMISTOFEN

__IOM uint32_t NMISTOFEN

[8..8] Stack Overflow NMI Enable

◆ NMISTOFSET

__OM uint32_t NMISTOFSET

[8..8] Stack Overflow NMI Status Set

◆ NMIWDT

__IM uint32_t NMIWDT

[7..7] Watchdog Timer NMI Status

◆ NMIWDTCLR

__OM uint32_t NMIWDTCLR

[7..7] Watchdog Timer NMI Status Clear

◆ NMIWDTEN

__IOM uint32_t NMIWDTEN

[7..7] Watchdog Timer NMI Enable

◆ NMIWDTSET

__OM uint32_t NMIWDTSET

[7..7] Watchdog Timer NMI Status Set

◆ NVM0_ACCDIS

__IOM uint32_t NVM0_ACCDIS

[0..0] NVM0 Access Disable for AEP

◆ NVM0_ADDR_ERR

__IM uint32_t NVM0_ADDR_ERR

[1..1] NVM0 Address Protection Error

◆ NVM0_ADDR_ERRCLR

__OM uint32_t NVM0_ADDR_ERRCLR

[1..1] NVM0 Address Protection Error Clear

◆ NVM0_ADDR_ERRSET

__OM uint32_t NVM0_ADDR_ERRSET

[1..1] NVM0 Address Protection Error Set

◆ NVM0_PROT_DIS

__IOM uint32_t NVM0_PROT_DIS

[19..19] Disable NVM0 Protection

◆ NVM0_PROT_ERR

__IM uint32_t NVM0_PROT_ERR

[0..0] NVM0 Access Protection Error

◆ NVM0_PROT_ERRCLR

__OM uint32_t NVM0_PROT_ERRCLR

[0..0] NVM0Access Protection Error Clear

◆ NVM0_PROT_ERRSET

__OM uint32_t NVM0_PROT_ERRSET

[0..0] NVM0 Access Protection Error Set

◆ NVM0_SFR_ADDR_ERR

__IM uint32_t NVM0_SFR_ADDR_ERR

[3..3] NVM0 SFR Address Protection Error

◆ NVM0_SFR_ADDR_ERRCLR

__OM uint32_t NVM0_SFR_ADDR_ERRCLR

[3..3] NVM0 SFR Address Protection Error Clear

◆ NVM0_SFR_ADDR_ERRSET

__OM uint32_t NVM0_SFR_ADDR_ERRSET

[3..3] NVM0 SFR Address Protection Error Set

◆ NVM0_SFR_PROT_ERR

__IM uint32_t NVM0_SFR_PROT_ERR

[2..2] NVM0 SFR Access Protection Error

◆ NVM0_SFR_PROT_ERRCLR

__OM uint32_t NVM0_SFR_PROT_ERRCLR

[2..2] NVM0 SFR Access Protection Error Clear

◆ NVM0_SFR_PROT_ERRSET

__OM uint32_t NVM0_SFR_PROT_ERRSET

[2..2] NVM0 SFR Access Protection Error Set

◆ NVM0OPC

__IM uint32_t NVM0OPC

[0..0] NVM0 Operation Complete Interrupt Status

◆ NVM0OPCIEN

__IOM uint32_t NVM0OPCIEN

[0..0] NVM0 Operation Complete Interrupt Enable

◆ NVM0OPCLR

__OM uint32_t NVM0OPCLR

[0..0] NVM0 Operation Complete Interrupt Status Clear

◆ NVM0OPSET

__OM uint32_t NVM0OPSET

[0..0] NVM0 Operation Complete Interrupt Status Set

◆ NVM1_ADDR_ERR

__IM uint32_t NVM1_ADDR_ERR

[5..5] NVM1 Address Protection Error

◆ NVM1_ADDR_ERRCLR

__OM uint32_t NVM1_ADDR_ERRCLR

[5..5] NVM1 Address Protection Error Clear

◆ NVM1_ADDR_ERRSET

__OM uint32_t NVM1_ADDR_ERRSET

[5..5] NVM1 Address Protection Error Set

◆ NVM1_PROT_DIS

__IOM uint32_t NVM1_PROT_DIS

[20..20] Disable NVM1 Protection

◆ NVM1_PROT_ERR

__IM uint32_t NVM1_PROT_ERR

[4..4] NVM1 Access Protection Error

◆ NVM1_PROT_ERRCLR

__OM uint32_t NVM1_PROT_ERRCLR

[4..4] NVM1 Access Protection Error Clear

◆ NVM1_PROT_ERRSET

__OM uint32_t NVM1_PROT_ERRSET

[4..4] NVM1 Access Protection Error Set

◆ NVM1_SFR_ADDR_ERR

__IM uint32_t NVM1_SFR_ADDR_ERR

[7..7] NVM1 SFR Address Protection Error

◆ NVM1_SFR_ADDR_ERRCLR

__OM uint32_t NVM1_SFR_ADDR_ERRCLR

[7..7] NVM1 SFR Address Protection Error Clear

◆ NVM1_SFR_ADDR_ERRSET

__OM uint32_t NVM1_SFR_ADDR_ERRSET

[7..7] NVM1 SFR Address Protection Error Set

◆ NVM1_SFR_PROT_ERR

__IM uint32_t NVM1_SFR_PROT_ERR

[6..6] NVM1 SFR Access Protection Error

◆ NVM1_SFR_PROT_ERRCLR

__OM uint32_t NVM1_SFR_PROT_ERRCLR

[6..6] NVM1 SFR Access Protection Error Clear

◆ NVM1_SFR_PROT_ERRSET

__OM uint32_t NVM1_SFR_PROT_ERRSET

[6..6] NVM1 SFR Access Protection Error Set

◆ NVM1OPC

__IM uint32_t NVM1OPC

[1..1] NVM1 Operation Complete Interrupt Status

◆ NVM1OPCIEN

__IOM uint32_t NVM1OPCIEN

[1..1] NVM1 Operation Complete Interrupt Enable

◆ NVM1OPCLR

__OM uint32_t NVM1OPCLR

[1..1] NVM1 Operation Complete Interrupt Status Clear

◆ NVM1OPSET

__OM uint32_t NVM1OPSET

[1..1] NVM1 Operation Complete Interrupt Status Set

◆ 

union { ... } NVM_OP_FSM

◆  [1/2]

union { ... } NVM_OP_RESULT

◆  [2/2]

union { ... } NVM_OP_RESULT

◆  [1/2]

union { ... } NVM_OP_STS

◆  [2/2]

union { ... } NVM_OP_STS

◆ 

union { ... } NVM_PROT_STS

◆ NVMSFR_PROT_DIS

__IOM uint32_t NVMSFR_PROT_DIS

[21..21] Disable NVMSFR Protection

◆ OP_RESULT

__IOM uint32_t OP_RESULT

[31..0] NVM operation result in case of a write/erase operation in the background

◆ OP_STS

__IOM uint32_t OP_STS

[31..0] Operation Status

◆ PG100TP_CHKS_ERR

__IOM uint32_t PG100TP_CHKS_ERR

[1..1] 100TP Page Checksum Error

◆ PRG_FLAG

__IOM uint32_t PRG_FLAG

[23..16] Programm Flag

◆ PSECCCDIS

__IOM uint32_t PSECCCDIS

[15..15] PSRAM ECC Enable Bit

◆ PSECCRD

__IM uint32_t PSECCRD

[14..8] PSRAM ECC Read Data

◆ PSECCWR

__IOM uint32_t PSECCWR

[14..8] PSRAM ECC Write Data

◆ PSRAM_MBISTEXEC

__IOM uint32_t PSRAM_MBISTEXEC

[21..21] PSRAM MBIST Execution Status Flag

◆ PSRAM_MBISTFAIL

__IOM uint32_t PSRAM_MBISTFAIL

[29..29] PSRAM MBIST Execution Fail Flag

◆ PSRAM_PROT_DIS

__IOM uint32_t PSRAM_PROT_DIS

[18..18] Disable PSRAM Protection

◆ PSRAM_PROT_ERR

__IM uint32_t PSRAM_PROT_ERR

[10..10] PSRAM Access Protection Error

◆ PSRAM_PROT_ERRCLR

__OM uint32_t PSRAM_PROT_ERRCLR

[10..10] PSRAM Access Protection Error Clear

◆ PSRAM_PROT_ERRSET

__OM uint32_t PSRAM_PROT_ERRSET

[10..10] PSRAM Access Protection Error Set

◆ PSSBE

__IM uint32_t PSSBE

[17..17] PSRAM Single Bit Error Status

◆ PSSBECLR

__OM uint32_t PSSBECLR

[17..17] PSRAM Single Bit Error Status Clear

◆ PSSBESET

__OM uint32_t PSSBESET

[17..17] PSRAM Single Bit Error Status Set

◆ RDEN_CRYPTO

__IOM uint32_t RDEN_CRYPTO

[13..13] NVM1 Read Protection of Crypto Lib

◆ RDEN_CS0

__IOM uint32_t RDEN_CS0

[8..8] NVM0 Read Protection of Config Sector 0

◆ RDEN_CS1

__IOM uint32_t RDEN_CS1

[9..9] NVM0 Read Protection of Config Sector 1

◆ RDEN_MCTRL

__IOM uint32_t RDEN_MCTRL

[14..14] NVM1 Read Protection of Secure Lib

◆ RDEN_UBSL

__IOM uint32_t RDEN_UBSL

[0..0] NVM0 Read Protection of Data in User BSL Region

◆ RDEN_UCODE

__IOM uint32_t RDEN_UCODE

[2..2] NVM1 Read Protection of Data in User Code Sectors

◆ RDEN_UDATA

__IOM uint32_t RDEN_UDATA

[4..4] NVM0 Read Protection of Data in User Data Sectors

◆ reg [1/2]

__IM uint32_t reg

(@ 0x00000000) Bus Fault Status Register

(@ 0x0000000C) Data Bus Fault Address Register

(@ 0x00000010) System Bus Fault Address Register

(@ 0x00000018) NMI Status Register

(@ 0x00000028) MEMCTRL Interrupt Status Register

(@ 0x00000034) Memory Protection and Error Status Register

(@ 0x00000048) ECC Read Data 0 Register

(@ 0x0000004C) ECC Read Data 1 Register

(@ 0x000000C0) System Watchdog Timer Value

◆ reg [2/2]

__IOM uint32_t reg

(@ 0x00000004) Bus Fault Status Clear Register

(@ 0x00000008) Bus Fault Status Set Register

(@ 0x00000014) NMI Control Register

(@ 0x0000001C) NMI Status Clear Register

(@ 0x00000020) NMI Status Set Register

(@ 0x00000024) MEMCTRL Interrupt Enable Register

(@ 0x0000002C) MEMCTRL Interrupt Status Clear Register

(@ 0x00000030) MEMCTRL Interrupt Status Set Register

(@ 0x00000038) Memory Protection and Error Status Register Clear

(@ 0x0000003C) Memory Protection and Error Status Register Set

(@ 0x00000040) Memory Control Register

(@ 0x00000044) ECC Control Register

(@ 0x00000050) Firmware Protection Register

(@ 0x00000054) Firmware Protection Address Low Register

(@ 0x00000058) Firmware Protection Address High Register

(@ 0x0000005C) Firmware Protection Address High Register 1

(@ 0x00000060) ROM Segments Address Register 0

(@ 0x00000064) ROM Segments Address Register 1

(@ 0x00000068) Motor Control Library Size

(@ 0x0000006C) Firmware Scratch 1 Register

(@ 0x00000070) Firmware Scratch 2 Register

(@ 0x00000074) Firmware Scratch 3 Register

(@ 0x00000078) Firmware Scratch 4 Register

(@ 0x0000007C) Firmware Scratch 5 Register

(@ 0x00000080) User VTOR Storage

(@ 0x00000084) User Stack Storage

(@ 0x00000088) User DEMCR Storage

(@ 0x0000008C) Secure Stack Pointer

(@ 0x00000090) System Startup Status Register

(@ 0x00000094) NVM Protection Status Register

(@ 0x00000098) NVM Operation FSM Register

(@ 0x0000009C) NVM Operation Status

(@ 0x000000A0) NVM operation result

(@ 0x000000A4) Memory Status Register

(@ 0x000000A8) Stack Overflow Control Register

(@ 0x000000AC) Stack Overflow Address Register

(@ 0x000000B0) Intercept Handler Address Register

(@ 0x000000B4) System Tick Calibration Register

(@ 0x000000B8) System Watchdog Timer Control Register

(@ 0x000000BC) System Watchdog Timer Reload Register

(@ 0x000000C4) System Watchdog Window-Boundary Count

(@ 0x000000C8) Test Control Register 1

(@ 0x000000CC) ROM Segments NMI Disable Address Register

(@ 0x000000D0) Secure Stack Overflow Control Register

(@ 0x000000D4) Secure Stack Overflow Address Register

(@ 0x000000D8) NVM0 AEP Control Register

◆ RESERVED

__IM uint32_t RESERVED[23]

◆ RESERVED1

__IM uint32_t RESERVED1

◆ ROM_PROT_DIS

__IOM uint32_t ROM_PROT_DIS

[16..16] Disable ROM Protection

◆ ROM_PROT_ERR

__IM uint32_t ROM_PROT_ERR

[8..8] ROM Access Protection Error

◆ ROM_PROT_ERRCLR

__OM uint32_t ROM_PROT_ERRCLR

[8..8] ROM Access Protection Error Clear

◆ ROM_PROT_ERRSET

__OM uint32_t ROM_PROT_ERRSET

[8..8] ROM Access Protection Error Set

◆ 

union { ... } ROM_SEGM_ADDR0

◆ 

union { ... } ROM_SEGM_ADDR1

◆ 

union { ... } ROM_SEGM_NMI

◆ ROMAWSEN

__IOM uint32_t ROMAWSEN

[0..0] ROM AHB Wait State Enable

◆ SASTATUS

__IOM uint32_t SASTATUS

[7..6] Service Algorithm Status

◆ SBFA [1/3]

__IM uint32_t SBFA

[31..0] System Bus Fault Address

◆  [2/3]

union { ... } SBFA

◆  [3/3]

union { ... } SBFA

◆ SBFSTS

__IM uint32_t SBFSTS

[1..1] System Bus Fault Status Valid Flag

◆ SBFSTSCLR

__OM uint32_t SBFSTSCLR

[1..1] System Bus Fault Status Valid Flag Clear

◆ SBFSTSSET

__OM uint32_t SBFSTSSET

[1..1] System Bus Fault Status Valid Flag Set

◆ SECEXITST

__IOM uint32_t SECEXITST

[14..0] Secure Exit Segment Start Address Offset

◆ SECST

__IOM uint32_t SECST

[30..16] Secure Segment Start Address Offset

◆ 

union { ... } SECSTACK_OVF_ADDR

◆ 

union { ... } SECSTACK_OVF_CTRL

◆ SECSTOF_ADDR_OFF_H

__IOM uint32_t SECSTOF_ADDR_OFF_H

[30..18] Higher secure DSRAM address offset boundary for stack overflow protection

◆ SECSTOF_ADDR_OFF_L

__IOM uint32_t SECSTOF_ADDR_OFF_L

[14..2] Lower secure DSRAM address offset boundary for stack overflow protection

◆ SECSTOF_EN

__IOM uint32_t SECSTOF_EN

[0..0] Secure Stack Overflow Enable

◆ SECTORINFO

__IOM uint32_t SECTORINFO

[5..0] Sector number where the Service Algorithm is running

◆ SECURE_STACK

__IOM uint32_t SECURE_STACK

[31..0] Secure Stack Pointer

◆ SFR_PROT_DIS

__IOM uint32_t SFR_PROT_DIS

[12..12] NVM1 SFR Access Protection

◆ SPARE_PROT

__IOM uint32_t SPARE_PROT

[3..2] Spare Protection Bits

◆  [1/2]

union { ... } STACK_OVF_ADDR

◆  [2/2]

union { ... } STACK_OVF_ADDR

◆  [1/2]

union { ... } STACK_OVF_CTRL

◆  [2/2]

union { ... } STACK_OVF_CTRL

◆ STCALIB [1/3]

__IOM uint32_t STCALIB

[25..0] System Tick Calibration

◆  [2/3]

union { ... } STCALIB

◆  [3/3]

union { ... } STCALIB

◆ STOF_ADDR_OFF_H

__IOM uint32_t STOF_ADDR_OFF_H

[30..18] Higher DSRAM address offset boundary for stack overflow protection

◆ STOF_ADDR_OFF_L

__IOM uint32_t STOF_ADDR_OFF_L

[14..2] Lower DSRAM address offset boundary for stack overflow protection

◆ STOF_EN

__IOM uint32_t STOF_EN

[0..0] Stack Overflow Enable

◆ 

union { ... } SYS_STRTUP_STS

◆  [1/2]

union { ... } SYSWDT

◆  [2/2]

union { ... } SYSWDT

◆  [1/2]

union { ... } SYSWDTCON

◆  [2/2]

union { ... } SYSWDTCON

◆  [1/2]

union { ... } SYSWDTREL

◆  [2/2]

union { ... } SYSWDTREL

◆  [1/2]

union { ... } SYSWDTWINB

◆  [2/2]

union { ... } SYSWDTWINB

◆ 

union { ... } TCR1

◆ TESTAPIST

__IOM uint32_t TESTAPIST

[30..16] TEST API Segment Start Address Offset

◆ TST_CTRL

__IOM uint32_t TST_CTRL

[31..31] module test enable Signal

◆ UBSL_PRIV

__IOM uint32_t UBSL_PRIV

[27..27] User BSL Privilege Setting

◆ UBSL_SIZE

__IOM uint32_t UBSL_SIZE

[26..24] User BSL Region Size Definition

◆ UBSLAPIST

__IOM uint32_t UBSLAPIST

[14..0] UBSL API Segment Start Address Offset

◆ USER_DEMCR

__IOM uint32_t USER_DEMCR

[31..0] User DEMCR

◆ USER_STACK

__IOM uint32_t USER_STACK

[31..0] User Stack

◆ USER_VTOR

__IOM uint32_t USER_VTOR

[31..0] User VTOR

◆ WDT

__IM uint32_t WDT

[15..0] Watchdog Timer Current Value

◆ WDTBEN

__IOM uint32_t WDTBEN

[5..5] Watchdog Window-Boundary Enable

◆ WDTEN

__IOM uint32_t WDTEN

[2..2] WDT Enable

◆ WDTIN

__IOM uint32_t WDTIN

[0..0] Watchdog Timer Input Frequency Selection

◆ WDTPR

__IM uint32_t WDTPR

[4..4] Watchdog Prewarning Mode Flag

◆ WDTREL

__IOM uint32_t WDTREL

[7..0] Watchdog Timer Reload Value - Upper Watchdog Timer Byte

◆ WDTRS

__IOM uint32_t WDTRS

[1..1] WDT Refresh Start

◆ WDTWINB

__IOM uint32_t WDTWINB

[7..0] Watchdog Window-Boundary Count Value

◆ WREN_CRYPTO

__IOM uint32_t WREN_CRYPTO

[10..10] NVM1 Write Protection of Data in Crypto Lib Sectors

◆ WREN_CS0

__IOM uint32_t WREN_CS0

[6..6] NVM0 Config Sector Write Protection

◆ WREN_CS1

__IOM uint32_t WREN_CS1

[7..7] NVM1 Config Sector Write Protection

◆ WREN_MCTRL

__IOM uint32_t WREN_MCTRL

[11..11] NVM1 Write Protection of Data in Motor Control Lib Sectors

◆ WREN_UBSL

__IOM uint32_t WREN_UBSL

[1..1] NVM0 Write Protection of Data in User BSL Region

◆ WREN_UCODE

__IOM uint32_t WREN_UCODE

[3..3] NVM1 Write Protection of Data in User Code Sectors

◆ WREN_UDATA

__IOM uint32_t WREN_UDATA

[5..5] NVM0 Write Protection of Data in User Data Sectors


The documentation for this struct was generated from the following file: