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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
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SSC0 (SSC0)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BM: 6 | |
__IOM uint32_t HB: 1 | |
__IOM uint32_t PH: 1 | |
__IOM uint32_t PO: 1 | |
__IOM uint32_t LB: 1 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t AREN: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t MS: 1 | |
__IOM uint32_t EN: 1 | |
__IOM uint32_t SLCSEN: 1 | |
__IOM uint32_t MSCSEN: 1 | |
__IOM uint32_t MSCSSEL: 4 | |
__OM uint32_t MSTXSTART: 1 | |
__IOM uint32_t MSTXENSEL: 2 | |
uint32_t __pad2__: 7 | |
} bit | |
} | CON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MRSTSEL: 2 | |
__IOM uint32_t SLCLKSEL: 2 | |
__IOM uint32_t MTSRSEL: 2 | |
__IOM uint32_t SLCSSEL: 2 | |
__IOM uint32_t TXEVSEL: 2 | |
uint32_t __pad0__: 22 | |
} bit | |
} | INSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ST: 6 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t END: 6 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t HIGH: 6 | |
uint32_t __pad2__: 10 | |
} bit | |
} | CSTIM |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TIREN: 1 | |
__IOM uint32_t RIREN: 1 | |
__IOM uint32_t TEIREN: 1 | |
__IOM uint32_t REIREN: 1 | |
__IOM uint32_t PEIREN: 1 | |
__IOM uint32_t BEIREN: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | IEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t TIR: 1 | |
__IM uint32_t RIR: 1 | |
__IM uint32_t TEIR: 1 | |
__IM uint32_t REIR: 1 | |
__IM uint32_t PEIR: 1 | |
__IM uint32_t BEIR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | IS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t TIRSET: 1 | |
__OM uint32_t RIRSET: 1 | |
__OM uint32_t TEIRSET: 1 | |
__OM uint32_t REIRSET: 1 | |
__OM uint32_t PEIRSET: 1 | |
__OM uint32_t BEIRSET: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | ISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t TIRCLR: 1 | |
__OM uint32_t RIRCLR: 1 | |
__OM uint32_t TEIRCLR: 1 | |
__OM uint32_t REIRCLR: 1 | |
__OM uint32_t PEIRCLR: 1 | |
__OM uint32_t BEIRCLR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | ISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BR_VALUE: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | BR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TB_VALUE_LOWER: 32 | |
} bit | |
} | TB0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TB_VALUE_UPPER: 32 | |
} bit | |
} | TB1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RB_VALUE_LOWER: 32 | |
} bit | |
} | RB0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RB_VALUE_UPPER: 32 | |
} bit | |
} | RB1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BC: 6 | |
__IM uint32_t BSY: 1 | |
uint32_t __pad0__: 25 | |
} bit | |
} | STAT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BM: 6 | |
__IOM uint32_t HB: 1 | |
__IOM uint32_t PH: 1 | |
__IOM uint32_t PO: 1 | |
__IOM uint32_t LB: 1 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t AREN: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t MS: 1 | |
__IOM uint32_t EN: 1 | |
__IOM uint32_t SLCSEN: 1 | |
__IOM uint32_t MSCSEN: 1 | |
__IOM uint32_t MSCSSEL: 4 | |
__OM uint32_t MSTXSTART: 1 | |
__IOM uint32_t MSTXENSEL: 2 | |
uint32_t __pad2__: 7 | |
} bit | |
} | CON |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MRSTSEL: 2 | |
__IOM uint32_t SLCLKSEL: 2 | |
__IOM uint32_t MTSRSEL: 2 | |
__IOM uint32_t SLCSSEL: 2 | |
__IOM uint32_t TXEVSEL: 2 | |
uint32_t __pad0__: 22 | |
} bit | |
} | INSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ST: 6 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t END: 6 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t HIGH: 6 | |
uint32_t __pad2__: 10 | |
} bit | |
} | CSTIM |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TIREN: 1 | |
__IOM uint32_t RIREN: 1 | |
__IOM uint32_t TEIREN: 1 | |
__IOM uint32_t REIREN: 1 | |
__IOM uint32_t PEIREN: 1 | |
__IOM uint32_t BEIREN: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | IEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t TIR: 1 | |
__IM uint32_t RIR: 1 | |
__IM uint32_t TEIR: 1 | |
__IM uint32_t REIR: 1 | |
__IM uint32_t PEIR: 1 | |
__IM uint32_t BEIR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | IS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t TIRSET: 1 | |
__OM uint32_t RIRSET: 1 | |
__OM uint32_t TEIRSET: 1 | |
__OM uint32_t REIRSET: 1 | |
__OM uint32_t PEIRSET: 1 | |
__OM uint32_t BEIRSET: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | ISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t TIRCLR: 1 | |
__OM uint32_t RIRCLR: 1 | |
__OM uint32_t TEIRCLR: 1 | |
__OM uint32_t REIRCLR: 1 | |
__OM uint32_t PEIRCLR: 1 | |
__OM uint32_t BEIRCLR: 1 | |
uint32_t __pad0__: 26 | |
} bit | |
} | ISC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t BR_VALUE: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | BR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TB_VALUE_LOWER: 32 | |
} bit | |
} | TB0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TB_VALUE_UPPER: 32 | |
} bit | |
} | TB1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RB_VALUE_LOWER: 32 | |
} bit | |
} | RB0 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t RB_VALUE_UPPER: 32 | |
} bit | |
} | RB1 |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t BC: 6 | |
__IM uint32_t BSY: 1 | |
uint32_t __pad0__: 25 | |
} bit | |
} | STAT |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
__IOM uint32_t AREN |
[12..12] Automatic Reset Enable
__IM uint32_t BC |
[5..0] Bit Count Field
__IM uint32_t BEIR |
[5..5] Baud Rate Error Interrupt Flag
__OM uint32_t BEIRCLR |
[5..5] Baud Rate Error Interrupt Clear
__IOM uint32_t BEIREN |
[5..5] Baud Rate Error Interrupt Enable
__OM uint32_t BEIRSET |
[5..5] Baud Rate Error Interrupt Set
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IOM uint32_t BM |
[5..0] Data Width Selection - Number of bits per transfer
union { ... } BR |
union { ... } BR |
__IOM uint32_t BR_VALUE |
[15..0] Baud Rate Timer Value
__IM uint32_t BSY |
[6..6] Busy Flag
union { ... } CON |
union { ... } CON |
union { ... } CSTIM |
union { ... } CSTIM |
__IOM uint32_t EN |
[15..15] Enable Bit
__IOM uint32_t END |
[13..8] CS Hold Time
__IOM uint32_t HB |
[6..6] Heading Control
__IOM uint32_t HIGH |
[21..16] CS High Time
union { ... } IEN |
union { ... } IEN |
union { ... } INSEL |
union { ... } INSEL |
union { ... } IS |
union { ... } IS |
union { ... } ISC |
union { ... } ISC |
union { ... } ISS |
union { ... } ISS |
__IOM uint32_t LB |
[9..9] Loop Back Control
__IOM uint32_t MRSTSEL |
[1..0] Master Mode Data Input Select
__IOM uint32_t MS |
[14..14] Master Select
__IOM uint32_t MSCSEN |
[17..17] Master Chip Select Enable
__IOM uint32_t MSCSSEL |
[21..18] Master Chip Select Output Selection
__IOM uint32_t MSTXENSEL |
[24..23] Master Mode Transmit Start Trigger Select
__OM uint32_t MSTXSTART |
[22..22] Master Mode Transmit Start Bit
__IOM uint32_t MTSRSEL |
[5..4] Slave Mode Data Input Select
__IM uint32_t PEIR |
[4..4] Phase Error Interrupt Flag
__OM uint32_t PEIRCLR |
[4..4] Phase Error Interrupt Clear
__IOM uint32_t PEIREN |
[4..4] Phase Error Interrupt Enable
__OM uint32_t PEIRSET |
[4..4] Phase Error Interrupt Set
__IOM uint32_t PH |
[7..7] Clock Phase Control
__IOM uint32_t PO |
[8..8] Clock Polarity Control
union { ... } RB0 |
union { ... } RB0 |
union { ... } RB1 |
union { ... } RB1 |
__IM uint32_t RB_VALUE_LOWER |
[31..0] Receive Data [31:0]
__IM uint32_t RB_VALUE_UPPER |
[31..0] Receive Data [63:32]
__IOM uint32_t reg |
(@ 0x00000000) Control Register
(@ 0x00000004) Port Input Select Register
(@ 0x00000008) Master Mode Chip Select Timings Register
(@ 0x0000000C) Interrupt Enable Register
(@ 0x00000014) Interrupt Status Set Register
(@ 0x00000018) Interrupt Status Clear Register
(@ 0x0000001C) Baud Rate Timer Register
(@ 0x00000020) Transmitter Buffer Register Bits [31:0]
(@ 0x00000024) Transmitter Buffer Register Bits [63:32]
__IM uint32_t reg |
(@ 0x00000010) Interrupt Status Register
(@ 0x00000028) Receiver Buffer Register Bits [31:0]
(@ 0x0000002C) Receiver Buffer Register Bits [63:32]
(@ 0x00000030) Status Register
__IM uint32_t REIR |
[3..3] Receive Error Interrupt Flag
__OM uint32_t REIRCLR |
[3..3] Receive Error Interrupt Clear
__IOM uint32_t REIREN |
[3..3] Receive Error Interrupt Enable
__OM uint32_t REIRSET |
[3..3] Receive Error Interrupt Set
__IM uint32_t RIR |
[1..1] Receive Buffer Full Interrupt Flag
__OM uint32_t RIRCLR |
[1..1] Receive Buffer Full Interrupt Clear
__IOM uint32_t RIREN |
[1..1] Receive Buffer Full Interrupt Enable
__OM uint32_t RIRSET |
[1..1] Receive Buffer Full Interrupt Set
__IOM uint32_t SLCLKSEL |
[3..2] Slave Mode Clock Input Select
__IOM uint32_t SLCSEN |
[16..16] Slave Chip Select Enable
__IOM uint32_t SLCSSEL |
[7..6] Slave Mode Chip Select Input Select
__IOM uint32_t ST |
[5..0] CS Setup Time
union { ... } STAT |
union { ... } STAT |
union { ... } TB0 |
union { ... } TB0 |
union { ... } TB1 |
union { ... } TB1 |
__IOM uint32_t TB_VALUE_LOWER |
[31..0] Transmit Data [31:0]
__IOM uint32_t TB_VALUE_UPPER |
[31..0] Transmit Data [63:32]
__IM uint32_t TEIR |
[2..2] Transmit Error Interrupt Flag
__OM uint32_t TEIRCLR |
[2..2] Transmit Error Interrupt Clear
__IOM uint32_t TEIREN |
[2..2] Transmit Error Interrupt Enable
__OM uint32_t TEIRSET |
[2..2] Transmit Error Interrupt Set
__IM uint32_t TIR |
[0..0] Transmit Buffer Empty Interrupt Flag
__OM uint32_t TIRCLR |
[0..0] Transmit Buffer Empty Interrupt Clear
__IOM uint32_t TIREN |
[0..0] Transmit Buffer Empty Interrupt Enable
__OM uint32_t TIRSET |
[0..0] Transmit Buffer Empty Interrupt Set
__IOM uint32_t TXEVSEL |
[9..8] Master Mode TX Start Event Input Select