#include <tle989x.h>
◆ __pad0__
◆ __pad1__
◆ __pad2__
◆ __pad3__
◆ [1/8]
◆ [2/8]
◆ [3/8]
◆ [4/8]
◆ [5/8]
◆ [6/8]
◆ [7/8]
◆ [8/8]
◆ COMP
[31..0] Reference value for comparison
[28..2] Comparison address
◆ CPIEVTENA
[17..17] Cycle Per Instruction counter overflow event enable
◆ CYCCNTENA
[0..0] Cycle Counter enable
◆ CYCEVTENA
[22..22] POSTCNT underflow event enable
◆ CYCMATCH
[7..7] Comparator Cycle Match Comparison Enable
◆ CYCTAP
[9..9] Selects the position of the POSTCNT tap on the CYCCNT counter:
union { ... } DWT_FUNCTION0 |
◆ EIASAMPLE
[31..0] Program Counter Value
◆ EMITRANGE
[5..5] enables generation of Data trace address packets
◆ ENABLE
[0..0] Enables Break Point Unit
[0..0] Breakpoint comparator enable
◆ EXCEVTENA
[18..18] Exception overhead counter overflow event enable
◆ EXCTRCENA
[16..16] Exception trace enable
◆ FOLDEVTENA
__IOM uint32_t FOLDEVTENA |
[21..21] Fold instruction counter overflow event enable
◆ FUNCTION
[3..0] Comparator Match Action Select
◆ KEY
[1..1] Write operation onto register BP_CTRL enable
◆ LSUEVTENA
[20..20] Load and Store Unit cycle counter overflow event enable
◆ MASK
[3..0] Size of ignore mask
◆ MATCHED
[24..24] Comparator Match Status
◆ NOCYCCNT
[25..25] Support Cycle Counters
◆ NOEXITTRIG
[26..26] Support External Match
◆ NOPRFCNT
[24..24] Support Profiling Counters
◆ NOTRCPKT
[27..27] Support Trace Sampling
◆ NUM_CODE
[7..4] Number of Breakpoint Comparators Bits 4 to 0
◆ NUM_CODE6_4
__IM uint32_t NUM_CODE6_4 |
[14..12] Number of breakpoint comparators, bits 6 to 4
◆ NUM_LIT
[11..8] Number of literal address comparators
◆ NUMCOMP
[31..28] Number of Breakpoint Comparators
◆ PCSAMPLENA
__IOM uint32_t PCSAMPLENA |
[12..12] Periodic PC (Program Counter) sample enable
◆ POSTINIT
[8..5] Initial value for the POSTCNT Timer counter
◆ POSTPRESET
__IOM uint32_t POSTPRESET |
[4..1] Reload value for the POSTCNT Timer counter
◆ reg [1/2]
(@ 0x00000000) Control Register
(@ 0x00000020) Comparator Register 0
(@ 0x00000024) Comparator Mask Register 0
(@ 0x00000028) Function Register 0
(@ 0x00001000) Breakpoint Control Register
(@ 0x00001008) Breakpoint Comparator Register 0
(@ 0x0000100C) Breakpoint Comparator Register 1
◆ reg [2/2]
(@ 0x0000001C) Program Counter Sample Register
◆ REPLACE
[31..30] Behavior by a comparison match
◆ RESERVED
__IM uint32_t RESERVED[6] |
◆ RESERVED1
__IM uint32_t RESERVED1[1013] |
◆ RESERVED2
◆ REV
[31..28] Flash Patch breakpoint architecture revision
◆ SLEEPEVTENA
__IOM uint32_t SLEEPEVTENA |
[19..19] Sleep counter overflow event enable
◆ SPARE
◆ SYNCTAP
[11..10] Selection of the position of the synchronization packet counter tap on the CYCNT counter
The documentation for this struct was generated from the following file: