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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
|
CCU7 (CCU7)
#include <tle989x.h>
Data Fields | |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DISR: 1 | |
__IM uint32_t DISS: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | CLC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12: 1 | |
__IOM uint32_t T13: 1 | |
__IOM uint32_t MCM: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t T14: 1 | |
__IOM uint32_t T15: 1 | |
__IOM uint32_t T16: 1 | |
uint32_t __pad1__: 8 | |
__IOM uint32_t WREN: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | MCFG |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MODREV: 8 | |
__IM uint32_t MODNUM: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | ID |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ISCC70: 2 | |
__IOM uint32_t ISCC71: 2 | |
__IOM uint32_t ISCC72: 2 | |
__IOM uint32_t ISTRP: 2 | |
__IOM uint32_t ISPOS0: 2 | |
__IOM uint32_t ISPOS1: 2 | |
__IOM uint32_t ISPOS2: 2 | |
__IOM uint32_t IST12HR: 2 | |
uint32_t __pad0__: 16 | |
} bit | |
} | PISEL0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST13HR: 2 | |
__IOM uint32_t ISCNT12: 2 | |
__IOM uint32_t ISCNT13: 2 | |
__IOM uint32_t T12EXT: 1 | |
__IOM uint32_t T13EXT: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | PISEL2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST1xHR: 2 | |
__IOM uint32_t ISCNT1x: 2 | |
__IOM uint32_t T1xEXT: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PISEL24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST1xHR: 2 | |
__IOM uint32_t ISCNT1x: 2 | |
__IOM uint32_t T1xEXT: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PISEL25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST1xHR: 2 | |
__IOM uint32_t ISCNT1x: 2 | |
__IOM uint32_t T1xEXT: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PISEL26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SB0: 1 | |
__IOM uint32_t SB1: 1 | |
__IOM uint32_t SB2: 1 | |
__IOM uint32_t SB3: 1 | |
__IOM uint32_t SB4: 1 | |
__IOM uint32_t SB5: 1 | |
__IOM uint32_t SB6: 1 | |
uint32_t __pad0__: 25 | |
} bit | |
} | KSCSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12PV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTE0: 1 | |
__IOM uint32_t DTE1: 1 | |
__IOM uint32_t DTE2: 1 | |
uint32_t __pad0__: 5 | |
__IM uint32_t DTR0: 1 | |
__IM uint32_t DTR1: 1 | |
__IM uint32_t DTR2: 1 | |
uint32_t __pad1__: 21 | |
} bit | |
} | T12DTC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTM_RISE: 8 | |
__IOM uint32_t DTM_FALL: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12DT0_VAL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTM_RISE: 8 | |
__IOM uint32_t DTM_FALL: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12DT1_VAL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTM_RISE: 8 | |
__IOM uint32_t DTM_FALL: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12DT2_VAL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTINSEL0: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t DTINSEL1: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t DTINSEL2: 2 | |
uint32_t __pad2__: 22 | |
} bit | |
} | T12DTINSEL |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72SR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70BR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71BR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72BR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70BSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71BSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72BSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T13R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T14R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T15R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T16R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T13PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T14PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T15PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T16PR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C73R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C74R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C75R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C76R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C73SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C74SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C75SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C76SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IM uint32_t CC70ST: 1 | |
__IM uint32_t CC71ST: 1 | |
__IM uint32_t CC72ST: 1 | |
__IM uint32_t CCPOS0: 1 | |
__IM uint32_t CCPOS1: 1 | |
__IM uint32_t CCPOS2: 1 | |
__IM uint32_t CC73ST: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CC70PS: 1 | |
__IOM uint32_t COUT70PS: 1 | |
__IOM uint32_t CC71PS: 1 | |
__IOM uint32_t COUT71PS: 1 | |
__IOM uint32_t CC72PS: 1 | |
__IOM uint32_t COUT72PS: 1 | |
__IOM uint32_t COUT73PS: 1 | |
__IOM uint32_t T13IM: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | CMPSTAT |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t C70BST: 1 | |
__IM uint32_t C71BST: 1 | |
__IM uint32_t C72BST: 1 | |
uint32_t __pad0__: 1 | |
__IM uint32_t C74ST: 1 | |
__IM uint32_t C75ST: 1 | |
__IM uint32_t C76ST: 1 | |
uint32_t __pad1__: 1 | |
__IM uint32_t CC70ST: 1 | |
__IM uint32_t CC71ST: 1 | |
__IM uint32_t CC72ST: 1 | |
uint32_t __pad2__: 21 | |
} bit | |
} | CMPSTAT_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MCC70S: 1 | |
__OM uint32_t MCC71S: 1 | |
__OM uint32_t MCC72S: 1 | |
__OM uint32_t MCC70BS: 1 | |
__OM uint32_t MCC71BS: 1 | |
__OM uint32_t MCC72BS: 1 | |
__OM uint32_t MCC73S: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t MCC70R: 1 | |
__OM uint32_t MCC71R: 1 | |
__OM uint32_t MCC72R: 1 | |
__OM uint32_t MCC70BR: 1 | |
__OM uint32_t MCC71BR: 1 | |
__OM uint32_t MCC72BR: 1 | |
__OM uint32_t MCC73R: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CMPMODIF |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MC74S: 1 | |
__OM uint32_t MC75S: 1 | |
__OM uint32_t MC76S: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CC70INV: 1 | |
__IOM uint32_t CC71INV: 1 | |
__IOM uint32_t CC72INV: 1 | |
uint32_t __pad1__: 1 | |
__OM uint32_t MC74R: 1 | |
__OM uint32_t MC75R: 1 | |
__OM uint32_t MC76R: 1 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t C70BINV: 1 | |
__IOM uint32_t C71BINV: 1 | |
__IOM uint32_t C72BINV: 1 | |
uint32_t __pad3__: 17 | |
} bit | |
} | CMPMODIF_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MSEL70: 4 | |
__IOM uint32_t MSEL71: 4 | |
__IOM uint32_t MSEL72: 4 | |
__IOM uint32_t HSYNC: 3 | |
__IOM uint32_t DBYP: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12MSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t T12PRE: 1 | |
__IM uint32_t T12R: 1 | |
__IM uint32_t STE12: 1 | |
__IM uint32_t CDIR: 1 | |
__IOM uint32_t CTM: 1 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t T13PRE: 1 | |
__IM uint32_t T13R: 1 | |
__IM uint32_t STE13: 1 | |
uint32_t __pad2__: 18 | |
} bit | |
} | TCTR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t T1xPRE: 1 | |
__IM uint32_t T14R: 1 | |
__IM uint32_t STE14: 1 | |
uint32_t __pad1__: 2 | |
__IM uint32_t T15R: 1 | |
__IM uint32_t STE15: 1 | |
uint32_t __pad2__: 2 | |
__IM uint32_t T16R: 1 | |
__IM uint32_t STE16: 1 | |
__IM uint32_t STE12: 1 | |
__IM uint32_t STE13: 1 | |
uint32_t __pad3__: 16 | |
} bit | |
} | TCTR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12SSC: 1 | |
__IOM uint32_t T13SSC: 1 | |
__IOM uint32_t T13TEC: 3 | |
__IOM uint32_t T13TED: 2 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t T12RSEL: 2 | |
__IOM uint32_t T13RSEL: 2 | |
uint32_t __pad1__: 20 | |
} bit | |
} | TCTR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xSSC: 1 | |
__IOM uint32_t T1xTEC: 3 | |
__IOM uint32_t T1xTED: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t T1xRSEL: 2 | |
uint32_t __pad1__: 22 | |
} bit | |
} | TCTR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xSSC: 1 | |
__IOM uint32_t T1xTEC: 3 | |
__IOM uint32_t T1xTED: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t T1xRSEL: 2 | |
uint32_t __pad1__: 22 | |
} bit | |
} | TCTR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xSSC: 1 | |
__IOM uint32_t T1xTEC: 3 | |
__IOM uint32_t T1xTED: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t T1xRSEL: 2 | |
uint32_t __pad1__: 22 | |
} bit | |
} | TCTR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T12RR: 1 | |
__OM uint32_t T12RS: 1 | |
__OM uint32_t T12RES: 1 | |
__OM uint32_t DTRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T12CNT: 1 | |
__OM uint32_t T12STR: 1 | |
__OM uint32_t T12STD: 1 | |
__OM uint32_t T13RR: 1 | |
__OM uint32_t T13RS: 1 | |
__OM uint32_t T13RES: 1 | |
uint32_t __pad1__: 2 | |
__OM uint32_t T13CNT: 1 | |
__OM uint32_t T13STR: 1 | |
__OM uint32_t T13STD: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | TCTR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T1xRR: 1 | |
__OM uint32_t T1xRS: 1 | |
__OM uint32_t T1xRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T1xCNT: 1 | |
__OM uint32_t T1xSTR: 1 | |
__OM uint32_t T1xSTD: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | TCTR44 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T1xRR: 1 | |
__OM uint32_t T1xRS: 1 | |
__OM uint32_t T1xRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T1xCNT: 1 | |
__OM uint32_t T1xSTR: 1 | |
__OM uint32_t T1xSTD: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | TCTR45 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T1xRR: 1 | |
__OM uint32_t T1xRS: 1 | |
__OM uint32_t T1xRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T1xCNT: 1 | |
__OM uint32_t T1xSTR: 1 | |
__OM uint32_t T1xSTD: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | TCTR46 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12MODEN_CC70: 1 | |
__IOM uint32_t T12MODEN_COUT70: 1 | |
__IOM uint32_t T12MODEN_CC71: 1 | |
__IOM uint32_t T12MODEN_COUT71: 1 | |
__IOM uint32_t T12MODEN_CC72: 1 | |
__IOM uint32_t T12MODEN_COUT72: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MCMEN: 1 | |
__IOM uint32_t T13MODEN_CC70: 1 | |
__IOM uint32_t T13MODEN_COUT70: 1 | |
__IOM uint32_t T13MODEN_CC71: 1 | |
__IOM uint32_t T13MODEN_COUT71: 1 | |
__IOM uint32_t T13MODEN_CC72: 1 | |
__IOM uint32_t T13MODEN_COUT72: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t ECT13O: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | MODCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TRPM0: 1 | |
__IOM uint32_t TRPM1: 1 | |
__IOM uint32_t TRPM2: 1 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t TRPEN: 6 | |
__IOM uint32_t TRPEN13: 1 | |
__IOM uint32_t TRPPEN: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | TRPCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PSL_CC70: 1 | |
__IOM uint32_t PSL_COUT70: 1 | |
__IOM uint32_t PSL_CC71: 1 | |
__IOM uint32_t PSL_COUT71: 1 | |
__IOM uint32_t PSL_CC72: 1 | |
__IOM uint32_t PSL_COUT72: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t PSL73: 1 | |
uint32_t __pad1__: 24 | |
} bit | |
} | PSLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MCMPS: 6 | |
uint32_t __pad0__: 1 | |
__OM uint32_t STRMCM: 1 | |
__IOM uint32_t EXPHS: 3 | |
__IOM uint32_t CURHS: 3 | |
uint32_t __pad1__: 1 | |
__OM uint32_t STRHP: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | MCMOUTS |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MCMP: 6 | |
__IM uint32_t R: 1 | |
uint32_t __pad0__: 1 | |
__IM uint32_t EXPH: 3 | |
__IM uint32_t CURH: 3 | |
uint32_t __pad1__: 18 | |
} bit | |
} | MCMOUT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SWSEL: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SWSYN: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t STE12U: 1 | |
__IOM uint32_t STE12D: 1 | |
__IOM uint32_t STE13U: 1 | |
uint32_t __pad2__: 21 | |
} bit | |
} | MCMCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LBE: 1 | |
__IOM uint32_t CCPOS0I: 1 | |
__IOM uint32_t CCPOS1I: 1 | |
__IOM uint32_t CCPOS2I: 1 | |
__IOM uint32_t CC70INI: 1 | |
__IOM uint32_t CC71INI: 1 | |
__IOM uint32_t CC72INI: 1 | |
__IOM uint32_t CTRAPI: 1 | |
__IOM uint32_t T12HRI: 1 | |
__IOM uint32_t T13HRI: 1 | |
uint32_t __pad0__: 22 | |
} bit | |
} | IMON |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CCPOS0EN: 1 | |
__IOM uint32_t CCPOS1EN: 1 | |
__IOM uint32_t CCPOS2EN: 1 | |
__IOM uint32_t CC70INEN: 1 | |
__IOM uint32_t CC71INEN: 1 | |
__IOM uint32_t CC72INEN: 1 | |
__IOM uint32_t CTRAPEN: 1 | |
__IOM uint32_t T12HREN: 1 | |
__IOM uint32_t T13HREN: 1 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t LBEEN: 1 | |
__IOM uint32_t INPLBE: 2 | |
uint32_t __pad2__: 16 | |
} bit | |
} | LI |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t ICC70R: 1 | |
__IM uint32_t ICC70F: 1 | |
__IM uint32_t ICC71R: 1 | |
__IM uint32_t ICC71F: 1 | |
__IM uint32_t ICC72R: 1 | |
__IM uint32_t ICC72F: 1 | |
__IM uint32_t T12OM: 1 | |
__IM uint32_t T12PM: 1 | |
__IM uint32_t T13CM: 1 | |
__IM uint32_t T13PM: 1 | |
__IM uint32_t TRPF: 1 | |
__IM uint32_t TRPS: 1 | |
__IM uint32_t CHE: 1 | |
__IM uint32_t WHE: 1 | |
__IM uint32_t IDLE: 1 | |
__IM uint32_t STR: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | IS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t SCC70R: 1 | |
__OM uint32_t SCC70F: 1 | |
__OM uint32_t SCC71R: 1 | |
__OM uint32_t SCC71F: 1 | |
__OM uint32_t SCC72R: 1 | |
__OM uint32_t SCC72F: 1 | |
__OM uint32_t ST12OM: 1 | |
__OM uint32_t ST12PM: 1 | |
__OM uint32_t ST13CM: 1 | |
__OM uint32_t ST13PM: 1 | |
__OM uint32_t STRPF: 1 | |
__OM uint32_t SWHC: 1 | |
__OM uint32_t SCHE: 1 | |
__OM uint32_t SWHE: 1 | |
__OM uint32_t SIDLE: 1 | |
__OM uint32_t SSTR: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | ISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t RCC70R: 1 | |
__OM uint32_t RCC70F: 1 | |
__OM uint32_t RCC71R: 1 | |
__OM uint32_t RCC71F: 1 | |
__OM uint32_t RCC72R: 1 | |
__OM uint32_t RCC72F: 1 | |
__OM uint32_t RT12OM: 1 | |
__OM uint32_t RT12PM: 1 | |
__OM uint32_t RT13CM: 1 | |
__OM uint32_t RT13PM: 1 | |
__OM uint32_t RTRPF: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t RCHE: 1 | |
__OM uint32_t RWHE: 1 | |
__OM uint32_t RIDLE: 1 | |
__OM uint32_t RSTR: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | ISR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INPCC70: 2 | |
__IOM uint32_t INPCC71: 2 | |
__IOM uint32_t INPCC72: 2 | |
__IOM uint32_t INPCHE: 2 | |
__IOM uint32_t INPERR: 2 | |
__IOM uint32_t INPT12: 2 | |
__IOM uint32_t INPT13: 2 | |
uint32_t __pad0__: 18 | |
} bit | |
} | INP |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ENCC70R: 1 | |
__IOM uint32_t ENCC70F: 1 | |
__IOM uint32_t ENCC71R: 1 | |
__IOM uint32_t ENCC71F: 1 | |
__IOM uint32_t ENCC72R: 1 | |
__IOM uint32_t ENCC72F: 1 | |
__IOM uint32_t ENT12OM: 1 | |
__IOM uint32_t ENT12PM: 1 | |
__IOM uint32_t ENT13CM: 1 | |
__IOM uint32_t ENT13PM: 1 | |
__IOM uint32_t ENTRPF: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t ENCHE: 1 | |
__IOM uint32_t ENWHE: 1 | |
__IOM uint32_t ENIDLE: 1 | |
__IOM uint32_t ENSTR: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | IEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t ICC70BR: 1 | |
__IM uint32_t ICC70BF: 1 | |
__IM uint32_t ICC71BR: 1 | |
__IM uint32_t ICC71BF: 1 | |
__IM uint32_t ICC72BR: 1 | |
__IM uint32_t ICC72BF: 1 | |
uint32_t __pad0__: 2 | |
__IM uint32_t T14CM: 1 | |
__IM uint32_t T14PM: 1 | |
__IM uint32_t T15CM: 1 | |
__IM uint32_t T15PM: 1 | |
__IM uint32_t T16CM: 1 | |
__IM uint32_t T16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | IS_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t SCC70BR: 1 | |
__OM uint32_t SCC70BF: 1 | |
__OM uint32_t SCC71BR: 1 | |
__OM uint32_t SCC71BF: 1 | |
__OM uint32_t SCC72BR: 1 | |
__OM uint32_t SCC72BF: 1 | |
uint32_t __pad0__: 2 | |
__OM uint32_t ST14CM: 1 | |
__OM uint32_t ST14PM: 1 | |
__OM uint32_t ST15CM: 1 | |
__OM uint32_t ST15PM: 1 | |
__OM uint32_t ST16CM: 1 | |
__OM uint32_t ST16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | ISS_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t RCC70BR: 1 | |
__OM uint32_t RCC70BF: 1 | |
__OM uint32_t RCC71BR: 1 | |
__OM uint32_t RCC71BF: 1 | |
__OM uint32_t RCC72BR: 1 | |
__OM uint32_t RCC72BF: 1 | |
uint32_t __pad0__: 2 | |
__OM uint32_t RT14CM: 1 | |
__OM uint32_t RT14PM: 1 | |
__OM uint32_t RT15CM: 1 | |
__OM uint32_t RT15PM: 1 | |
__OM uint32_t RT16CM: 1 | |
__OM uint32_t RT16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | ISR_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INPCC70B: 2 | |
__IOM uint32_t INPCC71B: 2 | |
__IOM uint32_t INPCC72B: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t INPT14: 2 | |
__IOM uint32_t INPT15: 2 | |
__IOM uint32_t INPT16: 2 | |
uint32_t __pad1__: 18 | |
} bit | |
} | INP_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ENCC70BR: 1 | |
__IOM uint32_t ENCC70BF: 1 | |
__IOM uint32_t ENCC71BR: 1 | |
__IOM uint32_t ENCC71BF: 1 | |
__IOM uint32_t ENCC72BR: 1 | |
__IOM uint32_t ENCC72BF: 1 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t ENT14CM: 1 | |
__IOM uint32_t ENT14PM: 1 | |
__IOM uint32_t ENT15CM: 1 | |
__IOM uint32_t ENT15PM: 1 | |
__IOM uint32_t ENT16CM: 1 | |
__IOM uint32_t ENT16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | IEN_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 24 | |
__IOM uint32_t SUS: 4 | |
__OM uint32_t SUS_P: 1 | |
__IM uint32_t SUSSTA: 1 | |
uint32_t __pad1__: 2 | |
} bit | |
} | OCS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PQ: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T_FDIV0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PQ: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T_FDIV1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12_CLK_SEL: 2 | |
__IOM uint32_t T13_CLK_SEL: 2 | |
__IOM uint32_t T14_CLK_SEL: 2 | |
__IOM uint32_t T15_CLK_SEL: 2 | |
__IOM uint32_t T16_CLK_SEL: 2 | |
__IOM uint32_t DT_CLK_SEL: 2 | |
__IOM uint32_t FDIV0_SEL: 1 | |
__IOM uint32_t FDIV1_SEL: 1 | |
uint32_t __pad0__: 18 | |
} bit | |
} | T_CLK_CTRL |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T12STR: 1 | |
__OM uint32_t T13STR: 1 | |
__OM uint32_t T14STR: 1 | |
__OM uint32_t T15STR: 1 | |
__OM uint32_t T16STR: 1 | |
uint32_t __pad0__: 3 | |
__OM uint32_t T12STD: 1 | |
__OM uint32_t T13STD: 1 | |
__OM uint32_t T14STD: 1 | |
__OM uint32_t T15STD: 1 | |
__OM uint32_t T16STD: 1 | |
uint32_t __pad1__: 19 | |
} bit | |
} | TCTR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t GT0: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t GT1: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t GT2: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t GT3: 2 | |
uint32_t __pad3__: 18 | |
} bit | |
} | IGT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DISR: 1 | |
__IM uint32_t DISS: 1 | |
uint32_t __pad0__: 30 | |
} bit | |
} | CLC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12: 1 | |
__IOM uint32_t T13: 1 | |
__IOM uint32_t MCM: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t T14: 1 | |
__IOM uint32_t T15: 1 | |
__IOM uint32_t T16: 1 | |
uint32_t __pad1__: 8 | |
__IOM uint32_t WREN: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | MCFG |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MODREV: 8 | |
__IM uint32_t MODNUM: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | ID |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ISCC70: 2 | |
__IOM uint32_t ISCC71: 2 | |
__IOM uint32_t ISCC72: 2 | |
__IOM uint32_t ISTRP: 2 | |
__IOM uint32_t ISPOS0: 2 | |
__IOM uint32_t ISPOS1: 2 | |
__IOM uint32_t ISPOS2: 2 | |
__IOM uint32_t IST12HR: 2 | |
uint32_t __pad0__: 16 | |
} bit | |
} | PISEL0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST13HR: 2 | |
__IOM uint32_t ISCNT12: 2 | |
__IOM uint32_t ISCNT13: 2 | |
__IOM uint32_t T12EXT: 1 | |
__IOM uint32_t T13EXT: 1 | |
uint32_t __pad0__: 24 | |
} bit | |
} | PISEL2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST1xHR: 2 | |
__IOM uint32_t ISCNT1x: 2 | |
__IOM uint32_t T1xEXT: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PISEL24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST1xHR: 2 | |
__IOM uint32_t ISCNT1x: 2 | |
__IOM uint32_t T1xEXT: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PISEL25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t IST1xHR: 2 | |
__IOM uint32_t ISCNT1x: 2 | |
__IOM uint32_t T1xEXT: 1 | |
uint32_t __pad0__: 27 | |
} bit | |
} | PISEL26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SB0: 1 | |
__IOM uint32_t SB1: 1 | |
__IOM uint32_t SB2: 1 | |
__IOM uint32_t SB3: 1 | |
__IOM uint32_t SB4: 1 | |
__IOM uint32_t SB5: 1 | |
__IOM uint32_t SB6: 1 | |
uint32_t __pad0__: 25 | |
} bit | |
} | KSCSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12PV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTE0: 1 | |
__IOM uint32_t DTE1: 1 | |
__IOM uint32_t DTE2: 1 | |
uint32_t __pad0__: 5 | |
__IM uint32_t DTR0: 1 | |
__IM uint32_t DTR1: 1 | |
__IM uint32_t DTR2: 1 | |
uint32_t __pad1__: 21 | |
} bit | |
} | T12DTC |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTM_RISE: 8 | |
__IOM uint32_t DTM_FALL: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12DT0_VAL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTM_RISE: 8 | |
__IOM uint32_t DTM_FALL: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12DT1_VAL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTM_RISE: 8 | |
__IOM uint32_t DTM_FALL: 8 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12DT2_VAL |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t DTINSEL0: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t DTINSEL1: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t DTINSEL2: 2 | |
uint32_t __pad2__: 22 | |
} bit | |
} | T12DTINSEL |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72SR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70BR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71BR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72BR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC70BSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC71BSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | CC72BSR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T13R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T14R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T15R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T16R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T13PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T14PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T15PR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xPV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T16PR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C73R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C74R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C75R |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t CCV: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C76R |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C73SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C74SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C75SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CCS: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | C76SR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IM uint32_t CC70ST: 1 | |
__IM uint32_t CC71ST: 1 | |
__IM uint32_t CC72ST: 1 | |
__IM uint32_t CCPOS0: 1 | |
__IM uint32_t CCPOS1: 1 | |
__IM uint32_t CCPOS2: 1 | |
__IM uint32_t CC73ST: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CC70PS: 1 | |
__IOM uint32_t COUT70PS: 1 | |
__IOM uint32_t CC71PS: 1 | |
__IOM uint32_t COUT71PS: 1 | |
__IOM uint32_t CC72PS: 1 | |
__IOM uint32_t COUT72PS: 1 | |
__IOM uint32_t COUT73PS: 1 | |
__IOM uint32_t T13IM: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | CMPSTAT |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t C70BST: 1 | |
__IM uint32_t C71BST: 1 | |
__IM uint32_t C72BST: 1 | |
uint32_t __pad0__: 1 | |
__IM uint32_t C74ST: 1 | |
__IM uint32_t C75ST: 1 | |
__IM uint32_t C76ST: 1 | |
uint32_t __pad1__: 1 | |
__IM uint32_t CC70ST: 1 | |
__IM uint32_t CC71ST: 1 | |
__IM uint32_t CC72ST: 1 | |
uint32_t __pad2__: 21 | |
} bit | |
} | CMPSTAT_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MCC70S: 1 | |
__OM uint32_t MCC71S: 1 | |
__OM uint32_t MCC72S: 1 | |
__OM uint32_t MCC70BS: 1 | |
__OM uint32_t MCC71BS: 1 | |
__OM uint32_t MCC72BS: 1 | |
__OM uint32_t MCC73S: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t MCC70R: 1 | |
__OM uint32_t MCC71R: 1 | |
__OM uint32_t MCC72R: 1 | |
__OM uint32_t MCC70BR: 1 | |
__OM uint32_t MCC71BR: 1 | |
__OM uint32_t MCC72BR: 1 | |
__OM uint32_t MCC73R: 1 | |
uint32_t __pad1__: 17 | |
} bit | |
} | CMPMODIF |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t MC74S: 1 | |
__OM uint32_t MC75S: 1 | |
__OM uint32_t MC76S: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CC70INV: 1 | |
__IOM uint32_t CC71INV: 1 | |
__IOM uint32_t CC72INV: 1 | |
uint32_t __pad1__: 1 | |
__OM uint32_t MC74R: 1 | |
__OM uint32_t MC75R: 1 | |
__OM uint32_t MC76R: 1 | |
uint32_t __pad2__: 1 | |
__IOM uint32_t C70BINV: 1 | |
__IOM uint32_t C71BINV: 1 | |
__IOM uint32_t C72BINV: 1 | |
uint32_t __pad3__: 17 | |
} bit | |
} | CMPMODIF_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MSEL70: 4 | |
__IOM uint32_t MSEL71: 4 | |
__IOM uint32_t MSEL72: 4 | |
__IOM uint32_t HSYNC: 3 | |
__IOM uint32_t DBYP: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T12MSEL |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t T12PRE: 1 | |
__IM uint32_t T12R: 1 | |
__IM uint32_t STE12: 1 | |
__IM uint32_t CDIR: 1 | |
__IOM uint32_t CTM: 1 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t T13PRE: 1 | |
__IM uint32_t T13R: 1 | |
__IM uint32_t STE13: 1 | |
uint32_t __pad2__: 18 | |
} bit | |
} | TCTR0 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 3 | |
__IOM uint32_t T1xPRE: 1 | |
__IM uint32_t T14R: 1 | |
__IM uint32_t STE14: 1 | |
uint32_t __pad1__: 2 | |
__IM uint32_t T15R: 1 | |
__IM uint32_t STE15: 1 | |
uint32_t __pad2__: 2 | |
__IM uint32_t T16R: 1 | |
__IM uint32_t STE16: 1 | |
__IM uint32_t STE12: 1 | |
__IM uint32_t STE13: 1 | |
uint32_t __pad3__: 16 | |
} bit | |
} | TCTR1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12SSC: 1 | |
__IOM uint32_t T13SSC: 1 | |
__IOM uint32_t T13TEC: 3 | |
__IOM uint32_t T13TED: 2 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t T12RSEL: 2 | |
__IOM uint32_t T13RSEL: 2 | |
uint32_t __pad1__: 20 | |
} bit | |
} | TCTR2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xSSC: 1 | |
__IOM uint32_t T1xTEC: 3 | |
__IOM uint32_t T1xTED: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t T1xRSEL: 2 | |
uint32_t __pad1__: 22 | |
} bit | |
} | TCTR24 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xSSC: 1 | |
__IOM uint32_t T1xTEC: 3 | |
__IOM uint32_t T1xTED: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t T1xRSEL: 2 | |
uint32_t __pad1__: 22 | |
} bit | |
} | TCTR25 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T1xSSC: 1 | |
__IOM uint32_t T1xTEC: 3 | |
__IOM uint32_t T1xTED: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t T1xRSEL: 2 | |
uint32_t __pad1__: 22 | |
} bit | |
} | TCTR26 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T12RR: 1 | |
__OM uint32_t T12RS: 1 | |
__OM uint32_t T12RES: 1 | |
__OM uint32_t DTRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T12CNT: 1 | |
__OM uint32_t T12STR: 1 | |
__OM uint32_t T12STD: 1 | |
__OM uint32_t T13RR: 1 | |
__OM uint32_t T13RS: 1 | |
__OM uint32_t T13RES: 1 | |
uint32_t __pad1__: 2 | |
__OM uint32_t T13CNT: 1 | |
__OM uint32_t T13STR: 1 | |
__OM uint32_t T13STD: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | TCTR4 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T1xRR: 1 | |
__OM uint32_t T1xRS: 1 | |
__OM uint32_t T1xRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T1xCNT: 1 | |
__OM uint32_t T1xSTR: 1 | |
__OM uint32_t T1xSTD: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | TCTR44 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T1xRR: 1 | |
__OM uint32_t T1xRS: 1 | |
__OM uint32_t T1xRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T1xCNT: 1 | |
__OM uint32_t T1xSTR: 1 | |
__OM uint32_t T1xSTD: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | TCTR45 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T1xRR: 1 | |
__OM uint32_t T1xRS: 1 | |
__OM uint32_t T1xRES: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t T1xCNT: 1 | |
__OM uint32_t T1xSTR: 1 | |
__OM uint32_t T1xSTD: 1 | |
uint32_t __pad1__: 25 | |
} bit | |
} | TCTR46 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12MODEN_CC70: 1 | |
__IOM uint32_t T12MODEN_COUT70: 1 | |
__IOM uint32_t T12MODEN_CC71: 1 | |
__IOM uint32_t T12MODEN_COUT71: 1 | |
__IOM uint32_t T12MODEN_CC72: 1 | |
__IOM uint32_t T12MODEN_COUT72: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t MCMEN: 1 | |
__IOM uint32_t T13MODEN_CC70: 1 | |
__IOM uint32_t T13MODEN_COUT70: 1 | |
__IOM uint32_t T13MODEN_CC71: 1 | |
__IOM uint32_t T13MODEN_COUT71: 1 | |
__IOM uint32_t T13MODEN_CC72: 1 | |
__IOM uint32_t T13MODEN_COUT72: 1 | |
uint32_t __pad1__: 1 | |
__IOM uint32_t ECT13O: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | MODCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t TRPM0: 1 | |
__IOM uint32_t TRPM1: 1 | |
__IOM uint32_t TRPM2: 1 | |
uint32_t __pad0__: 5 | |
__IOM uint32_t TRPEN: 6 | |
__IOM uint32_t TRPEN13: 1 | |
__IOM uint32_t TRPPEN: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | TRPCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PSL_CC70: 1 | |
__IOM uint32_t PSL_COUT70: 1 | |
__IOM uint32_t PSL_CC71: 1 | |
__IOM uint32_t PSL_COUT71: 1 | |
__IOM uint32_t PSL_CC72: 1 | |
__IOM uint32_t PSL_COUT72: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t PSL73: 1 | |
uint32_t __pad1__: 24 | |
} bit | |
} | PSLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t MCMPS: 6 | |
uint32_t __pad0__: 1 | |
__OM uint32_t STRMCM: 1 | |
__IOM uint32_t EXPHS: 3 | |
__IOM uint32_t CURHS: 3 | |
uint32_t __pad1__: 1 | |
__OM uint32_t STRHP: 1 | |
uint32_t __pad2__: 16 | |
} bit | |
} | MCMOUTS |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MCMP: 6 | |
__IM uint32_t R: 1 | |
uint32_t __pad0__: 1 | |
__IM uint32_t EXPH: 3 | |
__IM uint32_t CURH: 3 | |
uint32_t __pad1__: 18 | |
} bit | |
} | MCMOUT |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t SWSEL: 3 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t SWSYN: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t STE12U: 1 | |
__IOM uint32_t STE12D: 1 | |
__IOM uint32_t STE13U: 1 | |
uint32_t __pad2__: 21 | |
} bit | |
} | MCMCTR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t LBE: 1 | |
__IOM uint32_t CCPOS0I: 1 | |
__IOM uint32_t CCPOS1I: 1 | |
__IOM uint32_t CCPOS2I: 1 | |
__IOM uint32_t CC70INI: 1 | |
__IOM uint32_t CC71INI: 1 | |
__IOM uint32_t CC72INI: 1 | |
__IOM uint32_t CTRAPI: 1 | |
__IOM uint32_t T12HRI: 1 | |
__IOM uint32_t T13HRI: 1 | |
uint32_t __pad0__: 22 | |
} bit | |
} | IMON |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 1 | |
__IOM uint32_t CCPOS0EN: 1 | |
__IOM uint32_t CCPOS1EN: 1 | |
__IOM uint32_t CCPOS2EN: 1 | |
__IOM uint32_t CC70INEN: 1 | |
__IOM uint32_t CC71INEN: 1 | |
__IOM uint32_t CC72INEN: 1 | |
__IOM uint32_t CTRAPEN: 1 | |
__IOM uint32_t T12HREN: 1 | |
__IOM uint32_t T13HREN: 1 | |
uint32_t __pad1__: 3 | |
__IOM uint32_t LBEEN: 1 | |
__IOM uint32_t INPLBE: 2 | |
uint32_t __pad2__: 16 | |
} bit | |
} | LI |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t ICC70R: 1 | |
__IM uint32_t ICC70F: 1 | |
__IM uint32_t ICC71R: 1 | |
__IM uint32_t ICC71F: 1 | |
__IM uint32_t ICC72R: 1 | |
__IM uint32_t ICC72F: 1 | |
__IM uint32_t T12OM: 1 | |
__IM uint32_t T12PM: 1 | |
__IM uint32_t T13CM: 1 | |
__IM uint32_t T13PM: 1 | |
__IM uint32_t TRPF: 1 | |
__IM uint32_t TRPS: 1 | |
__IM uint32_t CHE: 1 | |
__IM uint32_t WHE: 1 | |
__IM uint32_t IDLE: 1 | |
__IM uint32_t STR: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | IS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t SCC70R: 1 | |
__OM uint32_t SCC70F: 1 | |
__OM uint32_t SCC71R: 1 | |
__OM uint32_t SCC71F: 1 | |
__OM uint32_t SCC72R: 1 | |
__OM uint32_t SCC72F: 1 | |
__OM uint32_t ST12OM: 1 | |
__OM uint32_t ST12PM: 1 | |
__OM uint32_t ST13CM: 1 | |
__OM uint32_t ST13PM: 1 | |
__OM uint32_t STRPF: 1 | |
__OM uint32_t SWHC: 1 | |
__OM uint32_t SCHE: 1 | |
__OM uint32_t SWHE: 1 | |
__OM uint32_t SIDLE: 1 | |
__OM uint32_t SSTR: 1 | |
uint32_t __pad0__: 16 | |
} bit | |
} | ISS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t RCC70R: 1 | |
__OM uint32_t RCC70F: 1 | |
__OM uint32_t RCC71R: 1 | |
__OM uint32_t RCC71F: 1 | |
__OM uint32_t RCC72R: 1 | |
__OM uint32_t RCC72F: 1 | |
__OM uint32_t RT12OM: 1 | |
__OM uint32_t RT12PM: 1 | |
__OM uint32_t RT13CM: 1 | |
__OM uint32_t RT13PM: 1 | |
__OM uint32_t RTRPF: 1 | |
uint32_t __pad0__: 1 | |
__OM uint32_t RCHE: 1 | |
__OM uint32_t RWHE: 1 | |
__OM uint32_t RIDLE: 1 | |
__OM uint32_t RSTR: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | ISR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INPCC70: 2 | |
__IOM uint32_t INPCC71: 2 | |
__IOM uint32_t INPCC72: 2 | |
__IOM uint32_t INPCHE: 2 | |
__IOM uint32_t INPERR: 2 | |
__IOM uint32_t INPT12: 2 | |
__IOM uint32_t INPT13: 2 | |
uint32_t __pad0__: 18 | |
} bit | |
} | INP |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ENCC70R: 1 | |
__IOM uint32_t ENCC70F: 1 | |
__IOM uint32_t ENCC71R: 1 | |
__IOM uint32_t ENCC71F: 1 | |
__IOM uint32_t ENCC72R: 1 | |
__IOM uint32_t ENCC72F: 1 | |
__IOM uint32_t ENT12OM: 1 | |
__IOM uint32_t ENT12PM: 1 | |
__IOM uint32_t ENT13CM: 1 | |
__IOM uint32_t ENT13PM: 1 | |
__IOM uint32_t ENTRPF: 1 | |
uint32_t __pad0__: 1 | |
__IOM uint32_t ENCHE: 1 | |
__IOM uint32_t ENWHE: 1 | |
__IOM uint32_t ENIDLE: 1 | |
__IOM uint32_t ENSTR: 1 | |
uint32_t __pad1__: 16 | |
} bit | |
} | IEN |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t ICC70BR: 1 | |
__IM uint32_t ICC70BF: 1 | |
__IM uint32_t ICC71BR: 1 | |
__IM uint32_t ICC71BF: 1 | |
__IM uint32_t ICC72BR: 1 | |
__IM uint32_t ICC72BF: 1 | |
uint32_t __pad0__: 2 | |
__IM uint32_t T14CM: 1 | |
__IM uint32_t T14PM: 1 | |
__IM uint32_t T15CM: 1 | |
__IM uint32_t T15PM: 1 | |
__IM uint32_t T16CM: 1 | |
__IM uint32_t T16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | IS_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t SCC70BR: 1 | |
__OM uint32_t SCC70BF: 1 | |
__OM uint32_t SCC71BR: 1 | |
__OM uint32_t SCC71BF: 1 | |
__OM uint32_t SCC72BR: 1 | |
__OM uint32_t SCC72BF: 1 | |
uint32_t __pad0__: 2 | |
__OM uint32_t ST14CM: 1 | |
__OM uint32_t ST14PM: 1 | |
__OM uint32_t ST15CM: 1 | |
__OM uint32_t ST15PM: 1 | |
__OM uint32_t ST16CM: 1 | |
__OM uint32_t ST16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | ISS_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t RCC70BR: 1 | |
__OM uint32_t RCC70BF: 1 | |
__OM uint32_t RCC71BR: 1 | |
__OM uint32_t RCC71BF: 1 | |
__OM uint32_t RCC72BR: 1 | |
__OM uint32_t RCC72BF: 1 | |
uint32_t __pad0__: 2 | |
__OM uint32_t RT14CM: 1 | |
__OM uint32_t RT14PM: 1 | |
__OM uint32_t RT15CM: 1 | |
__OM uint32_t RT15PM: 1 | |
__OM uint32_t RT16CM: 1 | |
__OM uint32_t RT16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | ISR_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t INPCC70B: 2 | |
__IOM uint32_t INPCC71B: 2 | |
__IOM uint32_t INPCC72B: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t INPT14: 2 | |
__IOM uint32_t INPT15: 2 | |
__IOM uint32_t INPT16: 2 | |
uint32_t __pad1__: 18 | |
} bit | |
} | INP_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ENCC70BR: 1 | |
__IOM uint32_t ENCC70BF: 1 | |
__IOM uint32_t ENCC71BR: 1 | |
__IOM uint32_t ENCC71BF: 1 | |
__IOM uint32_t ENCC72BR: 1 | |
__IOM uint32_t ENCC72BF: 1 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t ENT14CM: 1 | |
__IOM uint32_t ENT14PM: 1 | |
__IOM uint32_t ENT15CM: 1 | |
__IOM uint32_t ENT15PM: 1 | |
__IOM uint32_t ENT16CM: 1 | |
__IOM uint32_t ENT16PM: 1 | |
uint32_t __pad1__: 18 | |
} bit | |
} | IEN_2 |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 24 | |
__IOM uint32_t SUS: 4 | |
__OM uint32_t SUS_P: 1 | |
__IM uint32_t SUSSTA: 1 | |
uint32_t __pad1__: 2 | |
} bit | |
} | OCS |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PQ: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T_FDIV0 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t PQ: 16 | |
uint32_t __pad0__: 16 | |
} bit | |
} | T_FDIV1 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t T12_CLK_SEL: 2 | |
__IOM uint32_t T13_CLK_SEL: 2 | |
__IOM uint32_t T14_CLK_SEL: 2 | |
__IOM uint32_t T15_CLK_SEL: 2 | |
__IOM uint32_t T16_CLK_SEL: 2 | |
__IOM uint32_t DT_CLK_SEL: 2 | |
__IOM uint32_t FDIV0_SEL: 1 | |
__IOM uint32_t FDIV1_SEL: 1 | |
uint32_t __pad0__: 18 | |
} bit | |
} | T_CLK_CTRL |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t T12STR: 1 | |
__OM uint32_t T13STR: 1 | |
__OM uint32_t T14STR: 1 | |
__OM uint32_t T15STR: 1 | |
__OM uint32_t T16STR: 1 | |
uint32_t __pad0__: 3 | |
__OM uint32_t T12STD: 1 | |
__OM uint32_t T13STD: 1 | |
__OM uint32_t T14STD: 1 | |
__OM uint32_t T15STD: 1 | |
__OM uint32_t T16STD: 1 | |
uint32_t __pad1__: 19 | |
} bit | |
} | TCTR3 |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t GT0: 2 | |
uint32_t __pad0__: 2 | |
__IOM uint32_t GT1: 2 | |
uint32_t __pad1__: 2 | |
__IOM uint32_t GT2: 2 | |
uint32_t __pad2__: 2 | |
__IOM uint32_t GT3: 2 | |
uint32_t __pad3__: 18 | |
} bit | |
} | IGT |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
uint32_t __pad3__ |
struct { ... } bit |
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struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__IOM uint32_t C70BINV |
[12..12] Output channel C70BST Inversion Enable
__IM uint32_t C70BST |
[0..0] Compare State Bits B
__IOM uint32_t C71BINV |
[13..13] Output channel C71BST Inversion Enable
__IM uint32_t C71BST |
[1..1] Compare State Bits B
__IOM uint32_t C72BINV |
[14..14] Output channel C72BST Inversion Enable
__IM uint32_t C72BST |
[2..2] Compare State Bits B
union { ... } C73R |
union { ... } C73R |
union { ... } C73SR |
union { ... } C73SR |
union { ... } C74R |
union { ... } C74R |
union { ... } C74SR |
union { ... } C74SR |
__IM uint32_t C74ST |
[4..4] Compare State Bits
union { ... } C75R |
union { ... } C75R |
union { ... } C75SR |
union { ... } C75SR |
__IM uint32_t C75ST |
[5..5] Compare State Bits
union { ... } C76R |
union { ... } C76R |
union { ... } C76SR |
union { ... } C76SR |
__IM uint32_t C76ST |
[6..6] Compare State Bits
union { ... } CC70BR |
union { ... } CC70BR |
union { ... } CC70BSR |
union { ... } CC70BSR |
__IOM uint32_t CC70INEN |
[4..4] Lost Indicator Enable for input signal CC70IN - CC70INEN
__IOM uint32_t CC70INI |
[4..4] Event indication for input signal CC70IN - CC70INI
__IOM uint32_t CC70INV |
[4..4] Output channel CC70ST Inversion Enable
__IOM uint32_t CC70PS |
[8..8] Passive State Select for Compare Outputs
union { ... } CC70R |
union { ... } CC70R |
union { ... } CC70SR |
union { ... } CC70SR |
__IM uint32_t CC70ST |
[0..0] Capture/Compare State Bits
[8..8] Capture/Compare State Bits
union { ... } CC71BR |
union { ... } CC71BR |
union { ... } CC71BSR |
union { ... } CC71BSR |
__IOM uint32_t CC71INEN |
[5..5] Lost Indicator Enable for input signal CC71IN - CC71INEN
__IOM uint32_t CC71INI |
[5..5] Event indication for input signal CC71IN - CC71INI
__IOM uint32_t CC71INV |
[5..5] Output channel CC71ST Inversion Enable
__IOM uint32_t CC71PS |
[10..10] Passive State Select for Compare Outputs
union { ... } CC71R |
union { ... } CC71R |
union { ... } CC71SR |
union { ... } CC71SR |
__IM uint32_t CC71ST |
[1..1] Capture/Compare State Bits
[9..9] Capture/Compare State Bits
union { ... } CC72BR |
union { ... } CC72BR |
union { ... } CC72BSR |
union { ... } CC72BSR |
__IOM uint32_t CC72INEN |
[6..6] Lost Indicator Enable for input signal CC72IN - CC72INEN
__IOM uint32_t CC72INI |
[6..6] Event indication for input signal CC72IN - CC72INI
__IOM uint32_t CC72INV |
[6..6] Output channel CC72ST Inversion Enable
__IOM uint32_t CC72PS |
[12..12] Passive State Select for Compare Outputs
union { ... } CC72R |
union { ... } CC72R |
union { ... } CC72SR |
union { ... } CC72SR |
__IM uint32_t CC72ST |
[2..2] Capture/Compare State Bits
[10..10] Capture/Compare State Bits
__IM uint32_t CC73ST |
[6..6] Compare State Bits
__IM uint32_t CCPOS0 |
[3..3] Sampled Hall Pattern Bit 0
__IOM uint32_t CCPOS0EN |
[1..1] Lost Indicator Enable for input signal CCPOS0 - CCPOS0EN
__IOM uint32_t CCPOS0I |
[1..1] Event indication for input signal CCPOS0 - CCPOS0I
__IM uint32_t CCPOS1 |
[4..4] Sampled Hall Pattern Bit 1
__IOM uint32_t CCPOS1EN |
[2..2] Lost Indicator Enable for input signal CCPOS1 - CCPOS1EN
__IOM uint32_t CCPOS1I |
[2..2] Event indication for input signal CCPOS1 - CCPOS1I
__IM uint32_t CCPOS2 |
[5..5] Sampled Hall Pattern Bit 2
__IOM uint32_t CCPOS2EN |
[3..3] Lost Indicator Enable for input signal CCPOS2 - CCPOS2EN
__IOM uint32_t CCPOS2I |
[3..3] Event indication for input signal CCPOS2 - CCPOS2I
__IOM uint32_t CCS |
[15..0] Shadow Register for Channel x Capture/Compare Value
[15..0] Shadow Register for Channel CC73 Compare Value
[15..0] Shadow Register for Channel CC74 Compare Value
[15..0] Shadow Register for Channel CC75 Compare Value
[15..0] Shadow Register for Channel CC76 Compare Value
__IM uint32_t CCV |
[15..0] Capture/Compare Value - CCV
[15..0] Channel C7x Compare Value - CCV
__IM uint32_t CDIR |
[6..6] Count Direction of Timer T12
__IM uint32_t CHE |
[12..12] Correct Hall Event
union { ... } CLC |
union { ... } CLC |
union { ... } CMPMODIF |
union { ... } CMPMODIF |
union { ... } CMPMODIF_2 |
union { ... } CMPMODIF_2 |
union { ... } CMPSTAT |
union { ... } CMPSTAT |
union { ... } CMPSTAT_2 |
union { ... } CMPSTAT_2 |
__IOM uint32_t COUT70PS |
[9..9] Passive State Select for Compare Outputs
__IOM uint32_t COUT71PS |
[11..11] Passive State Select for Compare Outputs
__IOM uint32_t COUT72PS |
[13..13] Passive State Select for Compare Outputs
__IOM uint32_t COUT73PS |
[14..14] Passive State Select for Compare Outputs
__IOM uint32_t CS |
[15..0] Shadow Register for Channel x Compare Value - CS
__IOM uint32_t CTM |
[7..7] T12 Operating Mode
__IOM uint32_t CTRAPEN |
[7..7] Lost Indicator Enable for input signal CTRAP - CTRAPEN
__IOM uint32_t CTRAPI |
[7..7] Event indication for input signal CTRAP - CTRAPI
__IM uint32_t CURH |
[13..11] Current Hall Pattern - CURH
__IOM uint32_t CURHS |
[13..11] Current Hall Pattern Shadow
__IM uint32_t CV |
[15..0] Compare Value - CV
__IOM uint32_t DBYP |
[15..15] Delay Bypass
__IOM uint32_t DISR |
[0..0] Module Disable Request Bit - DISR
__IM uint32_t DISS |
[1..1] Module Disable Status Bit - DISS
__IOM uint32_t DT_CLK_SEL |
[11..10] Clock Selector for dead time control
__IOM uint32_t DTE0 |
[0..0] Dead-Time Enable Bit 0
__IOM uint32_t DTE1 |
[1..1] Dead-Time Enable Bit 1
__IOM uint32_t DTE2 |
[2..2] Dead-Time Enable Bit 2
__IOM uint32_t DTINSEL0 |
[1..0] Deadtime Input selection 0
__IOM uint32_t DTINSEL1 |
[5..4] Deadtime Input selection 1
__IOM uint32_t DTINSEL2 |
[9..8] Deadtime Input selection 2
__IOM uint32_t DTM_FALL |
[15..8] Dead-Time fall
__IOM uint32_t DTM_RISE |
[7..0] Dead-Time rise
__IM uint32_t DTR0 |
[8..8] Dead-Time Run Indication Bit 0
__IM uint32_t DTR1 |
[9..9] Dead-Time Run Indication Bit 1
__IM uint32_t DTR2 |
[10..10] Dead-Time Run Indication Bit 2
__OM uint32_t DTRES |
[3..3] Dead-Time Counter Reset
__IOM uint32_t ECT13O |
[15..15] Enable Compare Timer T13 Output
__IOM uint32_t ENCC70BF |
[1..1] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0
__IOM uint32_t ENCC70BR |
[0..0] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0
__IOM uint32_t ENCC70F |
[1..1] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0
__IOM uint32_t ENCC70R |
[0..0] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0
__IOM uint32_t ENCC71BF |
[3..3] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1
__IOM uint32_t ENCC71BR |
[2..2] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 1
__IOM uint32_t ENCC71F |
[3..3] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1
__IOM uint32_t ENCC71R |
[2..2] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 1
__IOM uint32_t ENCC72BF |
[5..5] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 2
__IOM uint32_t ENCC72BR |
[4..4] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 2
__IOM uint32_t ENCC72F |
[5..5] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 2
__IOM uint32_t ENCC72R |
[4..4] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 2
__IOM uint32_t ENCHE |
[12..12] Enable Interrupt for Correct Hall Event
__IOM uint32_t ENIDLE |
[14..14] Enable Idle
__IOM uint32_t ENSTR |
[15..15] Enable Multi-Channel Mode Shadow Transfer Interrupt
__IOM uint32_t ENT12OM |
[6..6] Enable Interrupt for T12 One-Match
__IOM uint32_t ENT12PM |
[7..7] Enable Interrupt for T12 Period-Match
__IOM uint32_t ENT13CM |
[8..8] Enable Interrupt for T13 Compare-Match
__IOM uint32_t ENT13PM |
[9..9] Enable Interrupt for T13 Period-Match
__IOM uint32_t ENT14CM |
[8..8] Enable Interrupt for T14 Compare-Match
__IOM uint32_t ENT14PM |
[9..9] Enable Interrupt for T14 Period-Match
__IOM uint32_t ENT15CM |
[10..10] Enable Interrupt for T15 Compare-Match
__IOM uint32_t ENT15PM |
[11..11] Enable Interrupt for T15 Period-Match
__IOM uint32_t ENT16CM |
[12..12] Enable Interrupt for T16 Compare-Match
__IOM uint32_t ENT16PM |
[13..13] Enable Interrupt for T16 Period-Match
__IOM uint32_t ENTRPF |
[10..10] Enable Interrupt for Trap Flag
__IOM uint32_t ENWHE |
[13..13] Enable Interrupt for Wrong Hall Event
__IM uint32_t EXPH |
[10..8] Expected Hall Pattern - EXPH
__IOM uint32_t EXPHS |
[10..8] Expected Hall Pattern Shadow
__IOM uint32_t FDIV0_SEL |
[12..12] FDIV0 Mode Selection
__IOM uint32_t FDIV1_SEL |
[13..13] FDIV1 Mode Selection
__IOM uint32_t GT0 |
[1..0] Gating SR0
__IOM uint32_t GT1 |
[5..4] Gating SR1
__IOM uint32_t GT2 |
[9..8] Gating SR2
__IOM uint32_t GT3 |
[13..12] Gating SR3
__IOM uint32_t HSYNC |
[14..12] Hall Synchronization
__IM uint32_t ICC70BF |
[1..1] Capture, Compare-Match Falling Edge Flag
__IM uint32_t ICC70BR |
[0..0] Capture, Compare-Match Rising Edge Flag
__IM uint32_t ICC70F |
[1..1] Capture, Compare-Match Falling Edge Flag
__IM uint32_t ICC70R |
[0..0] Capture, Compare-Match Rising Edge Flag
__IM uint32_t ICC71BF |
[3..3] Capture, Compare-Match Falling Edge Flag
__IM uint32_t ICC71BR |
[2..2] Capture, Compare-Match Rising Edge Flag
__IM uint32_t ICC71F |
[3..3] Capture, Compare-Match Falling Edge Flag
__IM uint32_t ICC71R |
[2..2] Capture, Compare-Match Rising Edge Flag
__IM uint32_t ICC72BF |
[5..5] Capture, Compare-Match Falling Edge Flag
__IM uint32_t ICC72BR |
[4..4] Capture, Compare-Match Rising Edge Flag
__IM uint32_t ICC72F |
[5..5] Capture, Compare-Match Falling Edge Flag
__IM uint32_t ICC72R |
[4..4] Capture, Compare-Match Rising Edge Flag
union { ... } ID |
union { ... } ID |
__IM uint32_t IDLE |
[14..14] IDLE State
union { ... } IEN |
union { ... } IEN |
union { ... } IEN_2 |
union { ... } IEN_2 |
union { ... } IGT |
union { ... } IGT |
union { ... } IMON |
union { ... } IMON |
union { ... } INP |
union { ... } INP |
union { ... } INP_2 |
union { ... } INP_2 |
__IOM uint32_t INPCC70 |
[1..0] Interrupt Node Pointer for Channel 0 Interrupts
__IOM uint32_t INPCC70B |
[1..0] Interrupt Node Pointer for Channel 0 Interrupts
__IOM uint32_t INPCC71 |
[3..2] Interrupt Node Pointer for Channel 1 Interrupts
__IOM uint32_t INPCC71B |
[3..2] Interrupt Node Pointer for Channel 1 Interrupts
__IOM uint32_t INPCC72 |
[5..4] Interrupt Node Pointer for Channel 2 Interrupts
__IOM uint32_t INPCC72B |
[5..4] Interrupt Node Pointer for Channel 2 Interrupts
__IOM uint32_t INPCHE |
[7..6] Interrupt Node Pointer for the CHE Interrupt
__IOM uint32_t INPERR |
[9..8] Interrupt Node Pointer for Error Interrupts
__IOM uint32_t INPLBE |
[15..14] Interrupt Node Pointer for lost bit event - INPLBE
__IOM uint32_t INPT12 |
[11..10] Interrupt Node Pointer for Timer T12 Interrupts
__IOM uint32_t INPT13 |
[13..12] Interrupt Node Pointer for Timer T13 Interrupts
__IOM uint32_t INPT14 |
[9..8] Interrupt Node Pointer for Timer T14 Interrupts
__IOM uint32_t INPT15 |
[11..10] Interrupt Node Pointer for Timer T15 Interrupts
__IOM uint32_t INPT16 |
[13..12] Interrupt Node Pointer for Timer T16 Interrupts
union { ... } IS |
union { ... } IS |
union { ... } IS_2 |
union { ... } IS_2 |
__IOM uint32_t ISCC70 |
[1..0] Input Select for CC70
__IOM uint32_t ISCC71 |
[3..2] Input Select for CC71
__IOM uint32_t ISCC72 |
[5..4] Input Select for CC72
__IOM uint32_t ISCNT12 |
[3..2] Input Select for T12 Counting Input
__IOM uint32_t ISCNT13 |
[5..4] Input Select for T13 Counting Input
__IOM uint32_t ISCNT1x |
[3..2] Input Select for T1x Counting Input
__IOM uint32_t ISPOS0 |
[9..8] Input Select for CCPOS0
__IOM uint32_t ISPOS1 |
[11..10] Input Select for CCPOS1
__IOM uint32_t ISPOS2 |
[13..12] Input Select for CCPOS2
union { ... } ISR |
union { ... } ISR |
union { ... } ISR_2 |
union { ... } ISR_2 |
union { ... } ISS |
union { ... } ISS |
union { ... } ISS_2 |
union { ... } ISS_2 |
__IOM uint32_t IST12HR |
[15..14] Input Select for T12HR
__IOM uint32_t IST13HR |
[1..0] Input Select for T13HR
__IOM uint32_t IST1xHR |
[1..0] Input Select for T1xHR
__IOM uint32_t ISTRP |
[7..6] Input Select for CTRAP
union { ... } KSCSR |
union { ... } KSCSR |
__IOM uint32_t LBE |
[0..0] Lost Bit Event - LBE
__IOM uint32_t LBEEN |
[13..13] Interrupt Enable for Lost Bit Event - LBEEN
union { ... } LI |
union { ... } LI |
__OM uint32_t MC74R |
[8..8] Compare Status Modification Bit 4(Reset)
__OM uint32_t MC74S |
[0..0] Compare Status Modification Bit 4 (Set)
__OM uint32_t MC75R |
[9..9] Compare Status Modification Bit 5(Reset)
__OM uint32_t MC75S |
[1..1] Compare Status Modification Bit 5 (Set)
__OM uint32_t MC76R |
[10..10] Compare Status Modification Bit 6(Reset)
__OM uint32_t MC76S |
[2..2] Compare Status Modification Bit 6 (Set)
__OM uint32_t MCC70BR |
[11..11] Compare B Status Modification Bit 0(Reset)
__OM uint32_t MCC70BS |
[3..3] Compare B Status Modification Bit 0 (Set)
__OM uint32_t MCC70R |
[8..8] Capture/Compare Status Modification Bit 0(Reset)
__OM uint32_t MCC70S |
[0..0] Capture/Compare Status Modification Bit 0 (Set)
__OM uint32_t MCC71BR |
[12..12] Compare B Status Modification Bit 1(Reset)
__OM uint32_t MCC71BS |
[4..4] Compare B Status Modification Bit 1 (Set)
__OM uint32_t MCC71R |
[9..9] Capture/Compare Status Modification Bit 1(Reset)
__OM uint32_t MCC71S |
[1..1] Capture/Compare Status Modification Bit 1 (Set)
__OM uint32_t MCC72BR |
[13..13] Compare B Status Modification Bit 2(Reset)
__OM uint32_t MCC72BS |
[5..5] Compare B Status Modification Bit 2 (Set)
__OM uint32_t MCC72R |
[10..10] Capture/Compare Status Modification Bit 2(Reset)
__OM uint32_t MCC72S |
[2..2] Capture/Compare Status Modification Bit 2 (Set)
__OM uint32_t MCC73R |
[14..14] Capture/Compare Status Modification Bits (Reset)
__OM uint32_t MCC73S |
[6..6] Capture/Compare Status Modification Bits (Set)
union { ... } MCFG |
union { ... } MCFG |
__IOM uint32_t MCM |
[2..2] Multi-Channel Mode Available - MCM
union { ... } MCMCTR |
union { ... } MCMCTR |
__IOM uint32_t MCMEN |
[7..7] Multi-Channel Mode Enable
union { ... } MCMOUT |
union { ... } MCMOUT |
union { ... } MCMOUTS |
union { ... } MCMOUTS |
__IM uint32_t MCMP |
[5..0] Multi-Channel PWM Pattern
__IOM uint32_t MCMPS |
[5..0] Multi-Channel PWM Pattern Shadow
union { ... } MODCTR |
union { ... } MODCTR |
__IM uint32_t MODNUM |
[15..8] Module Number Value - MODNUM
__IM uint32_t MODREV |
[7..0] Module Revision Number - MODREV
__IOM uint32_t MSEL70 |
[3..0] Capture/Compare Mode Selection MSEL7x (x=0,1,2)
__IOM uint32_t MSEL71 |
[7..4] Capture/Compare Mode Selection MSEL7x (x=0,1,2)
__IOM uint32_t MSEL72 |
[11..8] Capture/Compare Mode Selection MSEL7x (x=0,1,2)
union { ... } OCS |
union { ... } OCS |
union { ... } PISEL0 |
union { ... } PISEL0 |
union { ... } PISEL2 |
union { ... } PISEL2 |
union { ... } PISEL24 |
union { ... } PISEL24 |
union { ... } PISEL25 |
union { ... } PISEL25 |
union { ... } PISEL26 |
union { ... } PISEL26 |
__IOM uint32_t PQ |
[15..0] PQ
__IOM uint32_t PSL73 |
[7..7] Passive State Level of Output COUT73
__IOM uint32_t PSL_CC70 |
[0..0] Compare Outputs Passive State Level
__IOM uint32_t PSL_CC71 |
[2..2] Compare Outputs Passive State Level
__IOM uint32_t PSL_CC72 |
[4..4] Compare Outputs Passive State Level
__IOM uint32_t PSL_COUT70 |
[1..1] Compare Outputs Passive State Level
__IOM uint32_t PSL_COUT71 |
[3..3] Compare Outputs Passive State Level
__IOM uint32_t PSL_COUT72 |
[5..5] Compare Outputs Passive State Level
union { ... } PSLR |
union { ... } PSLR |
__IM uint32_t R |
[6..6] Reminder Flag
__OM uint32_t RCC70BF |
[1..1] Reset Capture, Compare-Match Falling Edge Flag
__OM uint32_t RCC70BR |
[0..0] Reset Capture, Compare-Match Rising Edge Flag
__OM uint32_t RCC70F |
[1..1] Reset Capture, Compare-Match Falling Edge Flag
__OM uint32_t RCC70R |
[0..0] Reset Capture, Compare-Match Rising Edge Flag
__OM uint32_t RCC71BF |
[3..3] Reset Capture, Compare-Match Falling Edge Flag
__OM uint32_t RCC71BR |
[2..2] Reset Capture, Compare-Match Rising Edge Flag
__OM uint32_t RCC71F |
[3..3] Reset Capture, Compare-Match Falling Edge Flag
__OM uint32_t RCC71R |
[2..2] Reset Capture, Compare-Match Rising Edge Flag
__OM uint32_t RCC72BF |
[5..5] Reset Capture, Compare-Match Falling Edge Flag
__OM uint32_t RCC72BR |
[4..4] Reset Capture, Compare-Match Rising Edge Flag
__OM uint32_t RCC72F |
[5..5] Reset Capture, Compare-Match Falling Edge Flag
__OM uint32_t RCC72R |
[4..4] Reset Capture, Compare-Match Rising Edge Flag
__OM uint32_t RCHE |
[12..12] Reset Correct Hall Event Flag
__IOM uint32_t reg |
(@ 0x00000000) Clock Control Register
(@ 0x00000004) Module Configuration Register
(@ 0x0000000C) Port Input Select Register 0
(@ 0x00000010) Port Input Select Register 2
(@ 0x00000014) Port Input Select Register 24
(@ 0x00000018) Port Input Select Register 25
(@ 0x0000001C) Port Input Select Register 26
(@ 0x00000020) Kernel State Control Sensitivity Register
(@ 0x00000024) Timer T12 Counter Register
(@ 0x00000028) Timer T12 Period Register
(@ 0x0000002C) Dead-Time Control Register for Timer T12 Low
(@ 0x00000030) Dead-Time value Register CC70
(@ 0x00000034) Dead-Time value Register CC71
(@ 0x00000038) Dead-Time value Register CC72
(@ 0x0000003C) Dead-Time Input Selection Register (Demo in Windows)
(@ 0x0000004C) Capture/Compare Shadow Reg. for Channel CC70
(@ 0x00000050) Capture/Compare Shadow Reg. for Channel CC71
(@ 0x00000054) Capture/Compare Shadow Reg. for Channel CC72
(@ 0x00000064) Compare Shadow Reg. for Channel C70BSR
(@ 0x00000068) Compare Shadow Reg. for Channel C71BSR
(@ 0x0000006C) Compare Shadow Reg. for Channel C72BSR
(@ 0x00000070) Timer T13 Counter Register
(@ 0x00000074) Timer T14 Counter Register
(@ 0x00000078) Timer T15 Counter Register
(@ 0x0000007C) Timer T16 Counter Register
(@ 0x00000080) Timer T13 Period Register
(@ 0x00000084) Timer T14 Period Register
(@ 0x00000088) Timer T15 Period Register
(@ 0x0000008C) Timer T16 Period Register
(@ 0x000000A0) Compare Shadow Reg. for Channel CC73
(@ 0x000000A4) Compare Shadow Reg. for Channel CC74
(@ 0x000000A8) Compare Shadow Reg. for Channel CC75
(@ 0x000000AC) Compare Shadow Reg. for Channel CC76
(@ 0x000000B0) Compare State Register
(@ 0x000000B8) Compare State Modification Register
(@ 0x000000BC) Compare State Modification Register 2
(@ 0x000000C0) T12 Capture/Compare Mode Select Register
(@ 0x000000C4) Timer Control Register 0
(@ 0x000000C8) Timer Control Register 1
(@ 0x000000CC) Timer Control Register 2
(@ 0x000000D0) Timer Control Register 24
(@ 0x000000D4) Timer Control Register 25
(@ 0x000000D8) Timer Control Register 26
(@ 0x000000DC) Timer Control Register 4
(@ 0x000000E0) Timer Control Register 44
(@ 0x000000E4) Timer Control Register 45
(@ 0x000000E8) Timer Control Register 46
(@ 0x000000EC) Modulation Control Register
(@ 0x000000F0) Trap Control Register
(@ 0x000000F4) Passive State Level Register
(@ 0x000000F8) Multi-Channel Mode Output Shadow Register
(@ 0x00000100) Multi-Channel Mode Control Register
(@ 0x00000104) Input Monitoring Register
(@ 0x00000108) Lost Indicator Register
(@ 0x00000110) Capture/Compare Interrupt Status Set Register 1
(@ 0x00000114) Capture/Compare Interrupt Status Reset Register 1
(@ 0x00000118) Capture/Compare Interrupt Node Pointer Register 1
(@ 0x0000011C) Capture/Compare Interrupt Enable Register 1
(@ 0x00000124) Capture/Compare Interrupt Status Set Register 2
(@ 0x00000128) Capture/Compare Interrupt Status Reset Register 2
(@ 0x0000012C) Capture/Compare Interrupt Node Pointer Register 2
(@ 0x00000130) Capture/Compare Interrupt Enable Register 2
(@ 0x00000134) OCDS Control and Status Register
(@ 0x00000138) Fractional Divider0
(@ 0x0000013C) Fractional Divider1
(@ 0x00000140) Timer Clock Selection
(@ 0x00000144) Timer Control Register 3
(@ 0x00000148) Interupt gating Register
__IM uint32_t reg |
(@ 0x00000008) Module Identification Register
(@ 0x00000040) Capture/Compare Register for Channel CC70
(@ 0x00000044) Capture/Compare Register for Channel CC71
(@ 0x00000048) Capture/Compare Register for Channel CC72
(@ 0x00000058) Compare Register for Channel C70B
(@ 0x0000005C) Compare Register for Channel C71B
(@ 0x00000060) Compare Register for Channel C72B
(@ 0x00000090) Compare Register for Channel C73
(@ 0x00000094) Compare Register for Channel C74
(@ 0x00000098) Compare Register for Channel C75
(@ 0x0000009C) Compare Register for Channel C76
(@ 0x000000B4) Compare State Register 2
(@ 0x000000FC) Multi-Channel Mode Output Register
(@ 0x0000010C) Capture/Compare Interrupt Status Register 1
(@ 0x00000120) Capture/Compare Interrupt Status Register 2
__OM uint32_t RIDLE |
[14..14] Reset IDLE Flag
__OM uint32_t RSTR |
[15..15] Reset STR Flag
__OM uint32_t RT12OM |
[6..6] Reset Timer T12 One-Match Flag
__OM uint32_t RT12PM |
[7..7] Reset Timer T12 Period-Match Flag
__OM uint32_t RT13CM |
[8..8] Reset Timer T13 Compare-Match Flag
__OM uint32_t RT13PM |
[9..9] Reset Timer T13 Period-Match Flag
__OM uint32_t RT14CM |
[8..8] Reset Timer T14 Compare-Match Flag
__OM uint32_t RT14PM |
[9..9] Reset Timer T14 Period-Match Flag
__OM uint32_t RT15CM |
[10..10] Reset Timer T15 Compare-Match Flag
__OM uint32_t RT15PM |
[11..11] Reset Timer T15 Period-Match Flag
__OM uint32_t RT16CM |
[12..12] Reset Timer T16 Compare-Match Flag
__OM uint32_t RT16PM |
[13..13] Reset Timer T16 Period-Match Flag
__OM uint32_t RTRPF |
[10..10] Reset Trap Flag
__OM uint32_t RWHE |
[13..13] Reset Wrong Hall Event Flag
__IOM uint32_t SB0 |
[0..0] Sensitivity Block x SBx (x=0,1,2,...)
__IOM uint32_t SB1 |
[1..1] Sensitivity Block x SBx (x=0,1,2,...)
__IOM uint32_t SB2 |
[2..2] Sensitivity Block x SBx (x=0,1,2,...)
__IOM uint32_t SB3 |
[3..3] Sensitivity Block x SBx (x=0,1,2,...)
__IOM uint32_t SB4 |
[4..4] Sensitivity Block x SBx (x=0,1,2,...)
__IOM uint32_t SB5 |
[5..5] Sensitivity Block x SBx (x=0,1,2,...)
__IOM uint32_t SB6 |
[6..6] Sensitivity Block x SBx (x=0,1,2,...)
__OM uint32_t SCC70BF |
[1..1] Set Capture, Compare-Match Falling Edge Flag
__OM uint32_t SCC70BR |
[0..0] Set Capture, Compare-Match Rising Edge Flag
__OM uint32_t SCC70F |
[1..1] Set Capture, Compare-Match Falling Edge Flag
__OM uint32_t SCC70R |
[0..0] Set Capture, Compare-Match Rising Edge Flag
__OM uint32_t SCC71BF |
[3..3] Set Capture, Compare-Match Falling Edge Flag
__OM uint32_t SCC71BR |
[2..2] Set Capture, Compare-Match Rising Edge Flag
__OM uint32_t SCC71F |
[3..3] Set Capture, Compare-Match Falling Edge Flag
__OM uint32_t SCC71R |
[2..2] Set Capture, Compare-Match Rising Edge Flag
__OM uint32_t SCC72BF |
[5..5] Set Capture, Compare-Match Falling Edge Flag
__OM uint32_t SCC72BR |
[4..4] Set Capture, Compare-Match Rising Edge Flag
__OM uint32_t SCC72F |
[5..5] Set Capture, Compare-Match Falling Edge Flag
__OM uint32_t SCC72R |
[4..4] Set Capture, Compare-Match Rising Edge Flag
__OM uint32_t SCHE |
[12..12] Set Correct Hall Event Flag
__OM uint32_t SIDLE |
[14..14] Set IDLE Flag
__OM uint32_t SSTR |
[15..15] Set STR Flag
__OM uint32_t ST12OM |
[6..6] Set Timer T12 One-Match Flag
__OM uint32_t ST12PM |
[7..7] Set Timer T12 Period-Match Flag
__OM uint32_t ST13CM |
[8..8] Set Timer T13 Compare-Match Flag
__OM uint32_t ST13PM |
[9..9] Set Timer T13 Period-Match Flag
__OM uint32_t ST14CM |
[8..8] Set Timer T14 Compare-Match Flag
__OM uint32_t ST14PM |
[9..9] Set Timer T14 Period-Match Flag
__OM uint32_t ST15CM |
[10..10] Set Timer T15 Compare-Match Flag
__OM uint32_t ST15PM |
[11..11] Set Timer T15 Period-Match Flag
__OM uint32_t ST16CM |
[12..12] Set Timer T16 Compare-Match Flag
__OM uint32_t ST16PM |
[13..13] Set Timer T16 Period-Match Flag
__IM uint32_t STE12 |
[5..5] Timer T12 Shadow Transfer Enable
[14..14] Timer T12 Shadow Transfer Enable
__IOM uint32_t STE12D |
[9..9] Shadow Transfer Enable for T12 Downcounting
__IOM uint32_t STE12U |
[8..8] Shadow Transfer Enable for T12 Upcounting
__IM uint32_t STE13 |
[13..13] Timer T13 Shadow Transfer Enable
[15..15] Timer T13 Shadow Transfer Enable
__IOM uint32_t STE13U |
[10..10] Shadow Transfer Enable for T13 Upcounting
__IM uint32_t STE14 |
[5..5] Timer T14 Shadow Transfer Enable
__IM uint32_t STE15 |
[9..9] Timer T15 Shadow Transfer Enable
__IM uint32_t STE16 |
[13..13] Timer T16 Shadow Transfer Enable
__IM uint32_t STR |
[15..15] Multi-Channel Mode Shadow Transfer Request
__OM uint32_t STRHP |
[15..15] Shadow Transfer Request for the Hall Pattern - STRHP
__OM uint32_t STRMCM |
[7..7] Shadow Transfer Request for MCMPS - STRMCM
__OM uint32_t STRPF |
[10..10] Set Trap Flag
__IOM uint32_t SUS |
[27..24] OCDS Suspend Control - SUS
__OM uint32_t SUS_P |
[28..28] SUS Write Protection - SUS_P
__IM uint32_t SUSSTA |
[29..29] Suspend State - SUSSTA
__OM uint32_t SWHC |
[11..11] Software Hall Compare
__OM uint32_t SWHE |
[13..13] Set Wrong Hall Event Flag
__IOM uint32_t SWSEL |
[2..0] Switching Selection
__IOM uint32_t SWSYN |
[5..4] Switching Synchronization
__IOM uint32_t T12 |
[0..0] T12 Available - T12
union { ... } T12 |
union { ... } T12 |
__IOM uint32_t T12_CLK_SEL |
[1..0] Clock selector for Timer 12
__OM uint32_t T12CNT |
[5..5] Timer T12 Count Event
__IOM uint32_t T12CV |
[15..0] Timer T12 Counter Value
union { ... } T12DT0_VAL |
union { ... } T12DT0_VAL |
union { ... } T12DT1_VAL |
union { ... } T12DT1_VAL |
union { ... } T12DT2_VAL |
union { ... } T12DT2_VAL |
union { ... } T12DTC |
union { ... } T12DTC |
union { ... } T12DTINSEL |
union { ... } T12DTINSEL |
__IOM uint32_t T12EXT |
[6..6] Extension for T12HR Inputs
__IOM uint32_t T12HREN |
[8..8] Lost Indicator Enable for input signal T12HR - T12HREN
__IOM uint32_t T12HRI |
[8..8] Event indication for input signal T12HR - T12HRI
__IOM uint32_t T12MODEN_CC70 |
[0..0] T12 Modulation Enable
__IOM uint32_t T12MODEN_CC71 |
[2..2] T12 Modulation Enable
__IOM uint32_t T12MODEN_CC72 |
[4..4] T12 Modulation Enable
__IOM uint32_t T12MODEN_COUT70 |
[1..1] T12 Modulation Enable
__IOM uint32_t T12MODEN_COUT71 |
[3..3] T12 Modulation Enable
__IOM uint32_t T12MODEN_COUT72 |
[5..5] T12 Modulation Enable
union { ... } T12MSEL |
union { ... } T12MSEL |
__IM uint32_t T12OM |
[6..6] Timer T12 One-Match Flag
__IM uint32_t T12PM |
[7..7] Timer T12 Period-Match Flag
union { ... } T12PR |
union { ... } T12PR |
__IOM uint32_t T12PRE |
[3..3] Timer T12 Prescaler Bit
__IOM uint32_t T12PV |
[15..0] T12 Period Value
__IM uint32_t T12R |
[4..4] Timer T12 Run Bit
__OM uint32_t T12RES |
[2..2] Timer T12 Reset
__OM uint32_t T12RR |
[0..0] Timer T12 Run Reset
__OM uint32_t T12RS |
[1..1] Timer T12 Run Set
__IOM uint32_t T12RSEL |
[9..8] Timer T12 External Run Selection
__IOM uint32_t T12SSC |
[0..0] Timer T12 Single Shot Control
__OM uint32_t T12STD |
[7..7] Timer T12 Shadow Transfer Disable
[8..8] Timer T12 Shadow Transfer Disable
__OM uint32_t T12STR |
[6..6] Timer T12 Shadow Transfer Request
[0..0] Timer T12 Shadow Transfer Request
__IOM uint32_t T13 |
[1..1] T13 Available - T13
__IOM uint32_t T13_CLK_SEL |
[3..2] Clock selector for Timer 13
__IM uint32_t T13CM |
[8..8] Timer T13 Compare-Match Flag
__OM uint32_t T13CNT |
[13..13] Timer T13 Count Event
__IOM uint32_t T13EXT |
[7..7] Extension for T13HR Inputs
__IOM uint32_t T13HREN |
[9..9] Lost Indicator Enable for input signal T13HR - T13HREN
__IOM uint32_t T13HRI |
[9..9] Event indication for input signal T13HR - T13HRI
__IOM uint32_t T13IM |
[15..15] T13 Inverted Modulation
__IOM uint32_t T13MODEN_CC70 |
[8..8] T13 Modulation Enable
__IOM uint32_t T13MODEN_CC71 |
[10..10] T13 Modulation Enable
__IOM uint32_t T13MODEN_CC72 |
[12..12] T13 Modulation Enable
__IOM uint32_t T13MODEN_COUT70 |
[9..9] T13 Modulation Enable
__IOM uint32_t T13MODEN_COUT71 |
[11..11] T13 Modulation Enable
__IOM uint32_t T13MODEN_COUT72 |
[13..13] T13 Modulation Enable
__IM uint32_t T13PM |
[9..9] Timer T13 Period-Match Flag
union { ... } T13PR |
union { ... } T13PR |
__IOM uint32_t T13PRE |
[11..11] Timer T13 Prescaler Bit
union { ... } T13R |
__IM uint32_t T13R |
[12..12] Timer T13 Run Bit
union { ... } T13R |
__OM uint32_t T13RES |
[10..10] Timer T13 Reset
__OM uint32_t T13RR |
[8..8] Timer T13 Run Reset
__OM uint32_t T13RS |
[9..9] Timer T13 Run Set
__IOM uint32_t T13RSEL |
[11..10] Timer T13 External Run Selection
__IOM uint32_t T13SSC |
[1..1] Timer T13 Single Shot Control
__OM uint32_t T13STD |
[15..15] Timer T13 Shadow Transfer Disable
[9..9] Timer T13 Shadow Transfer Disable
__OM uint32_t T13STR |
[14..14] Timer T13 Shadow Transfer Request
[1..1] Timer T13 Shadow Transfer Request
__IOM uint32_t T13TEC |
[4..2] T13 Trigger Event Control
__IOM uint32_t T13TED |
[6..5] Timer T13 Trigger Event Direction
__IOM uint32_t T14 |
[4..4] T14 Available -T14
__IOM uint32_t T14_CLK_SEL |
[5..4] Clock selector for Timer 14
__IM uint32_t T14CM |
[8..8] Timer T14 Compare-Match Flag
__IM uint32_t T14PM |
[9..9] Timer T14 Period-Match Flag
union { ... } T14PR |
union { ... } T14PR |
union { ... } T14R |
__IM uint32_t T14R |
[4..4] Timer T14 Run Bit
union { ... } T14R |
__OM uint32_t T14STD |
[10..10] Timer T14 Shadow Transfer Disable
__OM uint32_t T14STR |
[2..2] Timer T14 Shadow Transfer Request
__IOM uint32_t T15 |
[5..5] T15 Available - T15
__IOM uint32_t T15_CLK_SEL |
[7..6] Clock selector for Timer 15
__IM uint32_t T15CM |
[10..10] Timer T15 Compare-Match Flag
__IM uint32_t T15PM |
[11..11] Timer T15 Period-Match Flag
union { ... } T15PR |
union { ... } T15PR |
union { ... } T15R |
__IM uint32_t T15R |
[8..8] Timer T15 Run Bit
union { ... } T15R |
__OM uint32_t T15STD |
[11..11] Timer T15 Shadow Transfer Disable
__OM uint32_t T15STR |
[3..3] Timer T15 Shadow Transfer Request
__IOM uint32_t T16 |
[6..6] T16 Available - T16
__IOM uint32_t T16_CLK_SEL |
[9..8] Clock selector for Timer 16
__IM uint32_t T16CM |
[12..12] Timer T16 Compare-Match Flag
__IM uint32_t T16PM |
[13..13] Timer T16 Period-Match Flag
union { ... } T16PR |
union { ... } T16PR |
union { ... } T16R |
__IM uint32_t T16R |
[12..12] Timer T16 Run Bit
union { ... } T16R |
__OM uint32_t T16STD |
[12..12] Timer T16 Shadow Transfer Disable
__OM uint32_t T16STR |
[4..4] Timer T16 Shadow Transfer Request
__OM uint32_t T1xCNT |
[4..4] Timer T1x Count Event
__IOM uint32_t T1xCV |
[15..0] Timer T1x Counter Value
__IOM uint32_t T1xEXT |
[4..4] Extension for T1xHR Inputs
__IOM uint32_t T1xPRE |
[3..3] Timer T14 / 15 /16 Prescaler Bit
__IOM uint32_t T1xPV |
[15..0] T1x Period Value
__OM uint32_t T1xRES |
[2..2] Timer T1x Reset
__OM uint32_t T1xRR |
[0..0] Timer T1x Run Reset
__OM uint32_t T1xRS |
[1..1] Timer T1x Run Set
__IOM uint32_t T1xRSEL |
[9..8] Timer T1x External Run Selection
__IOM uint32_t T1xSSC |
[0..0] Timer T1x Single Shot Control
__OM uint32_t T1xSTD |
[6..6] Timer T1x Shadow Transfer Disable
__OM uint32_t T1xSTR |
[5..5] Timer T1x Shadow Transfer Request
__IOM uint32_t T1xTEC |
[3..1] T1x Trigger Event Control
__IOM uint32_t T1xTED |
[5..4] Timer T1x Trigger Event Direction
union { ... } T_CLK_CTRL |
union { ... } T_CLK_CTRL |
union { ... } T_FDIV0 |
union { ... } T_FDIV0 |
union { ... } T_FDIV1 |
union { ... } T_FDIV1 |
union { ... } TCTR0 |
union { ... } TCTR0 |
union { ... } TCTR1 |
union { ... } TCTR1 |
union { ... } TCTR2 |
union { ... } TCTR2 |
union { ... } TCTR24 |
union { ... } TCTR24 |
union { ... } TCTR25 |
union { ... } TCTR25 |
union { ... } TCTR26 |
union { ... } TCTR26 |
union { ... } TCTR3 |
union { ... } TCTR3 |
union { ... } TCTR4 |
union { ... } TCTR4 |
union { ... } TCTR44 |
union { ... } TCTR44 |
union { ... } TCTR45 |
union { ... } TCTR45 |
union { ... } TCTR46 |
union { ... } TCTR46 |
union { ... } TRPCTR |
union { ... } TRPCTR |
__IOM uint32_t TRPEN |
[13..8] Trap Enable Control
__IOM uint32_t TRPEN13 |
[14..14] Trap Enable Control for Timer T13
__IM uint32_t TRPF |
[10..10] Trap Flag
__IOM uint32_t TRPM0 |
[0..0] Trap Mode Control Bit 0 - TRPM0
__IOM uint32_t TRPM1 |
[1..1] Trap Mode Control Bit 1 - TRPM1
__IOM uint32_t TRPM2 |
[2..2] Trap Mode Control Bit 2 - TRPM2
__IOM uint32_t TRPPEN |
[15..15] Trap Pin Enable - TRPPEN
__IM uint32_t TRPS |
[11..11] Trap State
__IM uint32_t WHE |
[13..13] Wrong Hall Event
__IOM uint32_t WREN |
[15..15] Write Enable - WREN