Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
SSC0_Type Struct Reference

Detailed Description

SSC0 (SSC0)

#include <tle989x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BM: 6
 
      __IOM uint32_t   HB: 1
 
      __IOM uint32_t   PH: 1
 
      __IOM uint32_t   PO: 1
 
      __IOM uint32_t   LB: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   AREN: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   MS: 1
 
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   SLCSEN: 1
 
      __IOM uint32_t   MSCSEN: 1
 
      __IOM uint32_t   MSCSSEL: 4
 
      __OM uint32_t   MSTXSTART: 1
 
      __IOM uint32_t   MSTXENSEL: 2
 
      uint32_t   __pad2__: 7
 
   }   bit
 
CON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MRSTSEL: 2
 
      __IOM uint32_t   SLCLKSEL: 2
 
      __IOM uint32_t   MTSRSEL: 2
 
      __IOM uint32_t   SLCSSEL: 2
 
      __IOM uint32_t   TXEVSEL: 2
 
      uint32_t   __pad0__: 22
 
   }   bit
 
INSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ST: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   END: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HIGH: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
CSTIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TIREN: 1
 
      __IOM uint32_t   RIREN: 1
 
      __IOM uint32_t   TEIREN: 1
 
      __IOM uint32_t   REIREN: 1
 
      __IOM uint32_t   PEIREN: 1
 
      __IOM uint32_t   BEIREN: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
IEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   TIR: 1
 
      __IM uint32_t   RIR: 1
 
      __IM uint32_t   TEIR: 1
 
      __IM uint32_t   REIR: 1
 
      __IM uint32_t   PEIR: 1
 
      __IM uint32_t   BEIR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   TIRSET: 1
 
      __OM uint32_t   RIRSET: 1
 
      __OM uint32_t   TEIRSET: 1
 
      __OM uint32_t   REIRSET: 1
 
      __OM uint32_t   PEIRSET: 1
 
      __OM uint32_t   BEIRSET: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ISS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   TIRCLR: 1
 
      __OM uint32_t   RIRCLR: 1
 
      __OM uint32_t   TEIRCLR: 1
 
      __OM uint32_t   REIRCLR: 1
 
      __OM uint32_t   PEIRCLR: 1
 
      __OM uint32_t   BEIRCLR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BR_VALUE: 16
 
      uint32_t   __pad0__: 16
 
   }   bit
 
BR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TB_VALUE_LOWER: 32
 
   }   bit
 
TB0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TB_VALUE_UPPER: 32
 
   }   bit
 
TB1
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   RB_VALUE_LOWER: 32
 
   }   bit
 
RB0
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   RB_VALUE_UPPER: 32
 
   }   bit
 
RB1
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   BC: 6
 
      __IM uint32_t   BSY: 1
 
      uint32_t   __pad0__: 25
 
   }   bit
 
STAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BM: 6
 
      __IOM uint32_t   HB: 1
 
      __IOM uint32_t   PH: 1
 
      __IOM uint32_t   PO: 1
 
      __IOM uint32_t   LB: 1
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   AREN: 1
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   MS: 1
 
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   SLCSEN: 1
 
      __IOM uint32_t   MSCSEN: 1
 
      __IOM uint32_t   MSCSSEL: 4
 
      __OM uint32_t   MSTXSTART: 1
 
      __IOM uint32_t   MSTXENSEL: 2
 
      uint32_t   __pad2__: 7
 
   }   bit
 
CON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MRSTSEL: 2
 
      __IOM uint32_t   SLCLKSEL: 2
 
      __IOM uint32_t   MTSRSEL: 2
 
      __IOM uint32_t   SLCSSEL: 2
 
      __IOM uint32_t   TXEVSEL: 2
 
      uint32_t   __pad0__: 22
 
   }   bit
 
INSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ST: 6
 
      uint32_t   __pad0__: 2
 
      __IOM uint32_t   END: 6
 
      uint32_t   __pad1__: 2
 
      __IOM uint32_t   HIGH: 6
 
      uint32_t   __pad2__: 10
 
   }   bit
 
CSTIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TIREN: 1
 
      __IOM uint32_t   RIREN: 1
 
      __IOM uint32_t   TEIREN: 1
 
      __IOM uint32_t   REIREN: 1
 
      __IOM uint32_t   PEIREN: 1
 
      __IOM uint32_t   BEIREN: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
IEN
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   TIR: 1
 
      __IM uint32_t   RIR: 1
 
      __IM uint32_t   TEIR: 1
 
      __IM uint32_t   REIR: 1
 
      __IM uint32_t   PEIR: 1
 
      __IM uint32_t   BEIR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   TIRSET: 1
 
      __OM uint32_t   RIRSET: 1
 
      __OM uint32_t   TEIRSET: 1
 
      __OM uint32_t   REIRSET: 1
 
      __OM uint32_t   PEIRSET: 1
 
      __OM uint32_t   BEIRSET: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ISS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   TIRCLR: 1
 
      __OM uint32_t   RIRCLR: 1
 
      __OM uint32_t   TEIRCLR: 1
 
      __OM uint32_t   REIRCLR: 1
 
      __OM uint32_t   PEIRCLR: 1
 
      __OM uint32_t   BEIRCLR: 1
 
      uint32_t   __pad0__: 26
 
   }   bit
 
ISC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BR_VALUE: 16
 
      uint32_t   __pad0__: 16
 
   }   bit
 
BR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TB_VALUE_LOWER: 32
 
   }   bit
 
TB0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TB_VALUE_UPPER: 32
 
   }   bit
 
TB1
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   RB_VALUE_LOWER: 32
 
   }   bit
 
RB0
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   RB_VALUE_UPPER: 32
 
   }   bit
 
RB1
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   BC: 6
 
      __IM uint32_t   BSY: 1
 
      uint32_t   __pad0__: 25
 
   }   bit
 
STAT
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ AREN

__IOM uint32_t AREN

[12..12] Automatic Reset Enable

◆ BC

__IM uint32_t BC

[5..0] Bit Count Field

◆ BEIR

__IM uint32_t BEIR

[5..5] Baud Rate Error Interrupt Flag

◆ BEIRCLR

__OM uint32_t BEIRCLR

[5..5] Baud Rate Error Interrupt Clear

◆ BEIREN

__IOM uint32_t BEIREN

[5..5] Baud Rate Error Interrupt Enable

◆ BEIRSET

__OM uint32_t BEIRSET

[5..5] Baud Rate Error Interrupt Set

◆  [1/26]

struct { ... } bit

◆  [2/26]

struct { ... } bit

◆  [3/26]

struct { ... } bit

◆  [4/26]

struct { ... } bit

◆  [5/26]

struct { ... } bit

◆  [6/26]

struct { ... } bit

◆  [7/26]

struct { ... } bit

◆  [8/26]

struct { ... } bit

◆  [9/26]

struct { ... } bit

◆  [10/26]

struct { ... } bit

◆  [11/26]

struct { ... } bit

◆  [12/26]

struct { ... } bit

◆  [13/26]

struct { ... } bit

◆  [14/26]

struct { ... } bit

◆  [15/26]

struct { ... } bit

◆  [16/26]

struct { ... } bit

◆  [17/26]

struct { ... } bit

◆  [18/26]

struct { ... } bit

◆  [19/26]

struct { ... } bit

◆  [20/26]

struct { ... } bit

◆  [21/26]

struct { ... } bit

◆  [22/26]

struct { ... } bit

◆  [23/26]

struct { ... } bit

◆  [24/26]

struct { ... } bit

◆  [25/26]

struct { ... } bit

◆  [26/26]

struct { ... } bit

◆ BM

__IOM uint32_t BM

[5..0] Data Width Selection - Number of bits per transfer

◆  [1/2]

union { ... } BR

◆  [2/2]

union { ... } BR

◆ BR_VALUE

__IOM uint32_t BR_VALUE

[15..0] Baud Rate Timer Value

◆ BSY

__IM uint32_t BSY

[6..6] Busy Flag

◆  [1/2]

union { ... } CON

◆  [2/2]

union { ... } CON

◆  [1/2]

union { ... } CSTIM

◆  [2/2]

union { ... } CSTIM

◆ EN

__IOM uint32_t EN

[15..15] Enable Bit

◆ END

__IOM uint32_t END

[13..8] CS Hold Time

◆ HB

__IOM uint32_t HB

[6..6] Heading Control

◆ HIGH

__IOM uint32_t HIGH

[21..16] CS High Time

◆  [1/2]

union { ... } IEN

◆  [2/2]

union { ... } IEN

◆  [1/2]

union { ... } INSEL

◆  [2/2]

union { ... } INSEL

◆  [1/2]

union { ... } IS

◆  [2/2]

union { ... } IS

◆  [1/2]

union { ... } ISC

◆  [2/2]

union { ... } ISC

◆  [1/2]

union { ... } ISS

◆  [2/2]

union { ... } ISS

◆ LB

__IOM uint32_t LB

[9..9] Loop Back Control

◆ MRSTSEL

__IOM uint32_t MRSTSEL

[1..0] Master Mode Data Input Select

◆ MS

__IOM uint32_t MS

[14..14] Master Select

◆ MSCSEN

__IOM uint32_t MSCSEN

[17..17] Master Chip Select Enable

◆ MSCSSEL

__IOM uint32_t MSCSSEL

[21..18] Master Chip Select Output Selection

◆ MSTXENSEL

__IOM uint32_t MSTXENSEL

[24..23] Master Mode Transmit Start Trigger Select

◆ MSTXSTART

__OM uint32_t MSTXSTART

[22..22] Master Mode Transmit Start Bit

◆ MTSRSEL

__IOM uint32_t MTSRSEL

[5..4] Slave Mode Data Input Select

◆ PEIR

__IM uint32_t PEIR

[4..4] Phase Error Interrupt Flag

◆ PEIRCLR

__OM uint32_t PEIRCLR

[4..4] Phase Error Interrupt Clear

◆ PEIREN

__IOM uint32_t PEIREN

[4..4] Phase Error Interrupt Enable

◆ PEIRSET

__OM uint32_t PEIRSET

[4..4] Phase Error Interrupt Set

◆ PH

__IOM uint32_t PH

[7..7] Clock Phase Control

◆ PO

__IOM uint32_t PO

[8..8] Clock Polarity Control

◆  [1/2]

union { ... } RB0

◆  [2/2]

union { ... } RB0

◆  [1/2]

union { ... } RB1

◆  [2/2]

union { ... } RB1

◆ RB_VALUE_LOWER

__IM uint32_t RB_VALUE_LOWER

[31..0] Receive Data [31:0]

◆ RB_VALUE_UPPER

__IM uint32_t RB_VALUE_UPPER

[31..0] Receive Data [63:32]

◆ reg [1/2]

__IOM uint32_t reg

(@ 0x00000000) Control Register

(@ 0x00000004) Port Input Select Register

(@ 0x00000008) Master Mode Chip Select Timings Register

(@ 0x0000000C) Interrupt Enable Register

(@ 0x00000014) Interrupt Status Set Register

(@ 0x00000018) Interrupt Status Clear Register

(@ 0x0000001C) Baud Rate Timer Register

(@ 0x00000020) Transmitter Buffer Register Bits [31:0]

(@ 0x00000024) Transmitter Buffer Register Bits [63:32]

◆ reg [2/2]

__IM uint32_t reg

(@ 0x00000010) Interrupt Status Register

(@ 0x00000028) Receiver Buffer Register Bits [31:0]

(@ 0x0000002C) Receiver Buffer Register Bits [63:32]

(@ 0x00000030) Status Register

◆ REIR

__IM uint32_t REIR

[3..3] Receive Error Interrupt Flag

◆ REIRCLR

__OM uint32_t REIRCLR

[3..3] Receive Error Interrupt Clear

◆ REIREN

__IOM uint32_t REIREN

[3..3] Receive Error Interrupt Enable

◆ REIRSET

__OM uint32_t REIRSET

[3..3] Receive Error Interrupt Set

◆ RIR

__IM uint32_t RIR

[1..1] Receive Buffer Full Interrupt Flag

◆ RIRCLR

__OM uint32_t RIRCLR

[1..1] Receive Buffer Full Interrupt Clear

◆ RIREN

__IOM uint32_t RIREN

[1..1] Receive Buffer Full Interrupt Enable

◆ RIRSET

__OM uint32_t RIRSET

[1..1] Receive Buffer Full Interrupt Set

◆ SLCLKSEL

__IOM uint32_t SLCLKSEL

[3..2] Slave Mode Clock Input Select

◆ SLCSEN

__IOM uint32_t SLCSEN

[16..16] Slave Chip Select Enable

◆ SLCSSEL

__IOM uint32_t SLCSSEL

[7..6] Slave Mode Chip Select Input Select

◆ ST

__IOM uint32_t ST

[5..0] CS Setup Time

◆  [1/2]

union { ... } STAT

◆  [2/2]

union { ... } STAT

◆  [1/2]

union { ... } TB0

◆  [2/2]

union { ... } TB0

◆  [1/2]

union { ... } TB1

◆  [2/2]

union { ... } TB1

◆ TB_VALUE_LOWER

__IOM uint32_t TB_VALUE_LOWER

[31..0] Transmit Data [31:0]

◆ TB_VALUE_UPPER

__IOM uint32_t TB_VALUE_UPPER

[31..0] Transmit Data [63:32]

◆ TEIR

__IM uint32_t TEIR

[2..2] Transmit Error Interrupt Flag

◆ TEIRCLR

__OM uint32_t TEIRCLR

[2..2] Transmit Error Interrupt Clear

◆ TEIREN

__IOM uint32_t TEIREN

[2..2] Transmit Error Interrupt Enable

◆ TEIRSET

__OM uint32_t TEIRSET

[2..2] Transmit Error Interrupt Set

◆ TIR

__IM uint32_t TIR

[0..0] Transmit Buffer Empty Interrupt Flag

◆ TIRCLR

__OM uint32_t TIRCLR

[0..0] Transmit Buffer Empty Interrupt Clear

◆ TIREN

__IOM uint32_t TIREN

[0..0] Transmit Buffer Empty Interrupt Enable

◆ TIRSET

__OM uint32_t TIRSET

[0..0] Transmit Buffer Empty Interrupt Set

◆ TXEVSEL

__IOM uint32_t TXEVSEL

[9..8] Master Mode TX Start Event Input Select


The documentation for this struct was generated from the following file: