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Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
|
DMA (DMA)
#include <tle989x.h>
Data Fields | |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MASTER_ENABLE: 1 | |
uint32_t __pad0__: 3 | |
__IM uint32_t STATE: 4 | |
uint32_t __pad1__: 8 | |
__IM uint32_t CHNLS_MINUS1: 5 | |
uint32_t __pad2__: 11 | |
} bit | |
} | DMA_STATUS |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t MASTER_ENABLE: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t CHN1_PROT_CTRL: 3 | |
uint32_t __pad1__: 24 | |
} bit | |
} | DMA_CFG |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CTRL_BASE_PTR: 24 | |
} bit | |
} | CTRL_BASE_PTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t ALT_CTRL_BASE_PTR: 32 | |
} bit | |
} | ALT_CTRL_BASE_PTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t DMA_WAITONREQ_STATUS: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMA_WAITONREQ_STATUS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_SW_REQUEST: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_SW_REQUEST |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_USEBURST_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_USEBURST_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_USEBURST_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_USEBURST_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_REQ_MASK_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_REQ_MASK_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_REQ_MASK_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_REQ_MASK_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_ENABLE_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_ENABLE_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_ENABLE_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_ENABLE_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_PRI_ALT_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRI_ALT_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_PRI_ALT_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRI_ALT_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_PRIORITY_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRIORITY_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_PRIORITY_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRIORITY_CLR |
__IM uint32_t | RESERVED [3] |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ERR_CLR: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | ERR_CLR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t MASTER_ENABLE: 1 | |
uint32_t __pad0__: 3 | |
__IM uint32_t STATE: 4 | |
uint32_t __pad1__: 8 | |
__IM uint32_t CHNLS_MINUS1: 5 | |
uint32_t __pad2__: 11 | |
} bit | |
} | DMA_STATUS |
union { | |
__OM uint32_t reg | |
struct { | |
__OM uint32_t MASTER_ENABLE: 1 | |
uint32_t __pad0__: 4 | |
__OM uint32_t CHN1_PROT_CTRL: 3 | |
uint32_t __pad1__: 24 | |
} bit | |
} | DMA_CFG |
union { | |
__IOM uint32_t reg | |
struct { | |
uint32_t __pad0__: 8 | |
__IOM uint32_t CTRL_BASE_PTR: 24 | |
} bit | |
} | CTRL_BASE_PTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t ALT_CTRL_BASE_PTR: 32 | |
} bit | |
} | ALT_CTRL_BASE_PTR |
union { | |
__IM uint32_t reg | |
struct { | |
__IM uint32_t DMA_WAITONREQ_STATUS: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | DMA_WAITONREQ_STATUS |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_SW_REQUEST: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_SW_REQUEST |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_USEBURST_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_USEBURST_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_USEBURST_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_USEBURST_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_REQ_MASK_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_REQ_MASK_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_REQ_MASK_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_REQ_MASK_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_ENABLE_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_ENABLE_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_ENABLE_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_ENABLE_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_PRI_ALT_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRI_ALT_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_PRI_ALT_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRI_ALT_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t CHNL_PRIORITY_SET: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRIORITY_SET |
union { | |
__IOM uint32_t reg | |
struct { | |
__OM uint32_t CHNL_PRIORITY_CLR: 8 | |
uint32_t __pad0__: 24 | |
} bit | |
} | CHNL_PRIORITY_CLR |
union { | |
__IOM uint32_t reg | |
struct { | |
__IOM uint32_t ERR_CLR: 1 | |
uint32_t __pad0__: 31 | |
} bit | |
} | ERR_CLR |
uint32_t __pad0__ |
uint32_t __pad1__ |
uint32_t __pad2__ |
__IM uint32_t ALT_CTRL_BASE_PTR |
[31..0] Base Address of the Alternate Data Structure
union { ... } ALT_CTRL_BASE_PTR |
union { ... } ALT_CTRL_BASE_PTR |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
__OM uint32_t CHN1_PROT_CTRL |
[7..5] AHB Protection
__OM uint32_t CHNL_ENABLE_CLR |
[7..0] Channel Enable Clear
union { ... } CHNL_ENABLE_CLR |
union { ... } CHNL_ENABLE_CLR |
__IOM uint32_t CHNL_ENABLE_SET |
[7..0] Channel Enable Set
union { ... } CHNL_ENABLE_SET |
union { ... } CHNL_ENABLE_SET |
__OM uint32_t CHNL_PRI_ALT_CLR |
[7..0] Channel Primary Alternate Clear
union { ... } CHNL_PRI_ALT_CLR |
union { ... } CHNL_PRI_ALT_CLR |
__IOM uint32_t CHNL_PRI_ALT_SET |
[7..0] Channel Primary Alternate Set
union { ... } CHNL_PRI_ALT_SET |
union { ... } CHNL_PRI_ALT_SET |
__OM uint32_t CHNL_PRIORITY_CLR |
[7..0] Channel Priority Clear
union { ... } CHNL_PRIORITY_CLR |
union { ... } CHNL_PRIORITY_CLR |
__IOM uint32_t CHNL_PRIORITY_SET |
[7..0] Channel Priority Set
union { ... } CHNL_PRIORITY_SET |
union { ... } CHNL_PRIORITY_SET |
__OM uint32_t CHNL_REQ_MASK_CLR |
[7..0] Channel Request Mask Clear
union { ... } CHNL_REQ_MASK_CLR |
union { ... } CHNL_REQ_MASK_CLR |
__IOM uint32_t CHNL_REQ_MASK_SET |
[7..0] Channel Request Mask Set
union { ... } CHNL_REQ_MASK_SET |
union { ... } CHNL_REQ_MASK_SET |
__OM uint32_t CHNL_SW_REQUEST |
[7..0] Software DMA Request
union { ... } CHNL_SW_REQUEST |
union { ... } CHNL_SW_REQUEST |
__OM uint32_t CHNL_USEBURST_CLR |
[7..0] Channel Useburst Clear
union { ... } CHNL_USEBURST_CLR |
union { ... } CHNL_USEBURST_CLR |
__IOM uint32_t CHNL_USEBURST_SET |
[7..0] Channel Useburst Set
union { ... } CHNL_USEBURST_SET |
union { ... } CHNL_USEBURST_SET |
__IM uint32_t CHNLS_MINUS1 |
[20..16] Number of DMA Channels
__IOM uint32_t CTRL_BASE_PTR |
[31..8] Pointer to the base address of the primary data structure
union { ... } CTRL_BASE_PTR |
union { ... } CTRL_BASE_PTR |
union { ... } DMA_CFG |
union { ... } DMA_CFG |
union { ... } DMA_STATUS |
union { ... } DMA_STATUS |
__IM uint32_t DMA_WAITONREQ_STATUS |
[7..0] Channel Wait on Request Status
union { ... } DMA_WAITONREQ_STATUS |
union { ... } DMA_WAITONREQ_STATUS |
__IOM uint32_t ERR_CLR |
[0..0] Error Clear
union { ... } ERR_CLR |
union { ... } ERR_CLR |
__IM uint32_t MASTER_ENABLE |
[0..0] Controller Status Enable
__OM uint32_t MASTER_ENABLE |
[0..0] DMA Controller Enable
__IM uint32_t reg |
(@ 0x00000000) DMA Status Register
(@ 0x0000000C) Channel Alternate Control Data Base Pointer Register
(@ 0x00000010) Channel Wait on Request Status Register
__OM uint32_t reg |
(@ 0x00000004) DMA Configuration Register
__IOM uint32_t reg |
(@ 0x00000008) Channel Control Data Base Pointer Register
(@ 0x00000014) Channel Software Request Register
(@ 0x00000018) Channel Useburst Set Register
(@ 0x0000001C) Channel Useburst Clear Register
(@ 0x00000020) Channel Request Mask Set Register
(@ 0x00000024) Channel Request Mask Clear Register
(@ 0x00000028) Channel Enable Set Register
(@ 0x0000002C) Channel Enable Clear Register
(@ 0x00000030) Channel Primary-Alternate Set Register
(@ 0x00000034) Channel Primary-Alternate Clear Register
(@ 0x00000038) Channel Priority Set Register
(@ 0x0000003C) Channel Priority Clear Register
(@ 0x0000004C) Bus Error Status and Clear Register
__IM uint32_t RESERVED |
__IM uint32_t STATE |
[7..4] Current State of the Control State Machine