#include <tle989x.h>
◆ __pad0__
◆ __pad1__
◆ __pad2__
◆ ATB0_SEL
[25..24] ATB0 bus assignment
◆ ATB2_SEL
[27..26] ATB2 bus assignment
◆ ATB3_SEL
[29..28] ATB0 bus assignment
◆ [1/15]
◆ [2/15]
◆ [3/15]
◆ [4/15]
◆ [5/15]
◆ [6/15]
◆ [7/15]
◆ [8/15]
◆ [9/15]
◆ [10/15]
◆ [11/15]
◆ [12/15]
◆ [13/15]
◆ [14/15]
◆ [15/15]
◆ [1/2]
◆ [2/2]
◆ DTB4_OUT
[9..8] DTB4 output assignment
◆ DTB5_OUT
[11..10] DTB5 output assignment
◆ EN
◆ IBIAS
[4..0] Bias current trimming settings. Target value is 40uA, trimming step is 1uA.
◆ IBIAS_PD_N
__IOM uint32_t IBIAS_PD_N |
[20..20] IBIAS enable bit (ibias_pd_n_i). Note: This bit is only valid if MI_EN is set.
◆ MI_EN
[30..30] Module Isolation mode enable. Note: This bit is only valid if TST_CTRL is set.
◆ OC_IEN
[0..0] VAREF Overcurrent (undervoltage) Interrupt Enable
◆ OC_IS
[0..0] VAREF overcurrent (undervoltage) interrupt.
◆ OC_IS_CLR
[0..0] VAREF overcurrent (undervoltage) interrupt clear
◆ OC_IS_SET
[0..0] VAREF overcurrent (undervoltage) interrupt set
◆ OC_STS
[16..16] VAREF overcurrent (undervoltage) status flag. The detection circuit monitors VAREF voltage.
◆ OC_STS_CLR
[16..16] VAREF overcurrent (undervoltage) status flag clear
◆ OC_STS_SET
[16..16] VAREF overcurrent (undervoltage) status flag set. Setting this bit will trigger a VAREF switch off.
◆ REFNVM
[13..12] NVM Reference trimming. Target value is 1.2V, trimming step is 5mV.
◆ REFNVM_BI_EN
__IOM uint32_t REFNVM_BI_EN |
[14..14] NVM reference burn in enable
◆ REFNVM_BI_SET
__IOM uint32_t REFNVM_BI_SET |
[13..12] NVM reference burn in settings. Increases NVM buffer output for BI stress test without changing VREF1V2 or VREF_BUF
◆ REFNVM_BUF_PD_N
__IOM uint32_t REFNVM_BUF_PD_N |
[17..17] NVM buffer enable bit (refnvm_buf_pd_n_i). Note: This bit is only valid if MI_EN is set.
◆ reg [1/2]
(@ 0x00000000) CFU status register
◆ reg [2/2]
(@ 0x00000004) VAREF Interrupt Status Register
(@ 0x00000008) VAREF Interrupt Set Register
(@ 0x0000000C) VAREF Interrupt Clear Register
(@ 0x00000010) VAREF Interrupt Enable Register
(@ 0x00000018) VAREF control register
(@ 0x0000001C) AVRG Test Control Register 1
(@ 0x00000100) VAREF Trimming Register
(@ 0x00000104) CFU trimming settings
◆ RESERVED
◆ RESERVED1
__IM uint32_t RESERVED1[56] |
◆ TRIM_OUT
[3..0] VAREF voltage trimming settings. Target value is 5V, trimming step is 20mV.
◆ TST_CTRL
[31..31] Module test enable Signal
◆ [1/2]
◆ [2/2]
◆ VAREF_DIS_SHTDWN
__IM uint32_t VAREF_DIS_SHTDWN |
[16..16] Disables VAREF automatic shutdown in case of overcurrent (undervoltage). Note: This bit is only valid if TST_CTRL is set.
◆ [1/2]
◆ [2/2]
◆ [1/2]
◆ [2/2]
◆ [1/2]
union { ... } VAREF_IRQ_CLR |
◆ [2/2]
union { ... } VAREF_IRQ_CLR |
◆ [1/2]
union { ... } VAREF_IRQ_SET |
◆ [2/2]
union { ... } VAREF_IRQ_SET |
◆ VREF1V2_PD_N
__IOM uint32_t VREF1V2_PD_N |
[19..19] VREF1V2 enable bit (vref1v2_pd_n_i). Note: This bit is only valid if MI_EN is set.
◆ VREF1V2_TC
__IOM uint32_t VREF1V2_TC |
[10..8] BandGap temperature coefficient trimming. Target value is 1.2V, trimming step is 5mV.
◆ VREF1V2_UP
[0..0] Reference voltage status
◆ VREF_BUF_PD_N
__IOM uint32_t VREF_BUF_PD_N |
[18..18] VREF buffer enable bit (vref_buf_pd_n_i). Note: This bit is only valid if MI_EN is set.
The documentation for this struct was generated from the following file: