99 #include "isr_defines.h"
106 #define NMI_INP_NMI 3
108 #define WARN_INP_NVIC_IRQ0 0
109 #define WARN_INP_NVIC_IRQ1 1
110 #define CCU7_INP_NVIC_IRQ2 0
111 #define CCU7_INP_NVIC_IRQ3 1
112 #define CCU7_INP_NVIC_IRQ4 2
113 #define CCU7_INP_NVIC_IRQ5 3
114 #define MEMCTRL_INP_NVIC_IRQ6 0
115 #define GPT12_INP_NVIC_IRQ7 0
116 #define GPT12_INP_NVIC_IRQ8 1
117 #define ADC2_INP_NVIC_IRQ10 0
118 #define ADC2_INP_NVIC_IRQ11 1
119 #define MON_INP_NVIC_IRQ12 0
120 #define MON_INP_NVIC_IRQ13 1
121 #define ADC1_INP_NVIC_IRQ14 0
122 #define ADC1_INP_NVIC_IRQ15 1
123 #define ADC1_INP_NVIC_IRQ16 2
124 #define ADC1_INP_NVIC_IRQ17 3
125 #define BEMF_SDADC_INP_NVIC_IRQ18 0
126 #define BEMF_SDADC_INP_NVIC_IRQ19 1
127 #define EXTINT_INP_NVIC_IRQ20 0
128 #define EXTINT_INP_NVIC_IRQ21 1
129 #define UART_INP_NVIC_IRQ22 0
130 #define UART_INP_NVIC_IRQ23 1
131 #define SSC_INP_NVIC_IRQ24 0
132 #define SSC_INP_NVIC_IRQ25 1
133 #define CAN_INP_NVIC_IRQ26 0
134 #define CAN_INP_NVIC_IRQ27 1
135 #define CAN_INP_NVIC_IRQ28 2
136 #define DMA_INP_NVIC_IRQ29 0
137 #define DMA_INP_NVIC_IRQ30 1
138 #define T20_INP_NVIC_IRQ9 0
139 #define T21_INP_NVIC_IRQ31 0
141 #ifndef SCU_NMICON_NMIXTALEN_NMI_EN
142 #define SCU_NMICON_NMIXTALEN_NMI_EN 0
144 #ifndef SCU_NMICON_NMIPLL0EN_NMI_EN
145 #define SCU_NMICON_NMIPLL0EN_NMI_EN 0
147 #ifndef SCU_NMICON_NMIPLL1EN_NMI_EN
148 #define SCU_NMICON_NMIPLL1EN_NMI_EN 0
150 #ifndef MEMCTRL_NMICON_NMIDSEN_NMI_EN
151 #define MEMCTRL_NMICON_NMIDSEN_NMI_EN 0
153 #ifndef MEMCTRL_NMICON_NMIPSEN_NMI_EN
154 #define MEMCTRL_NMICON_NMIPSEN_NMI_EN 0
156 #ifndef MEMCTRL_NMICON_NMICDEN_NMI_EN
157 #define MEMCTRL_NMICON_NMICDEN_NMI_EN 0
159 #ifndef MEMCTRL_NMICON_NMINVM0EN_NMI_EN
160 #define MEMCTRL_NMICON_NMINVM0EN_NMI_EN 0
162 #ifndef MEMCTRL_NMICON_NMINVM1EN_NMI_EN
163 #define MEMCTRL_NMICON_NMINVM1EN_NMI_EN 0
165 #ifndef MEMCTRL_NMICON_NMIMAP0EN_NMI_EN
166 #define MEMCTRL_NMICON_NMIMAP0EN_NMI_EN 0
168 #ifndef MEMCTRL_NMICON_NMIMAP1EN_NMI_EN
169 #define MEMCTRL_NMICON_NMIMAP1EN_NMI_EN 0
171 #ifndef MEMCTRL_NMICON_NMIWDTEN_NMI_EN
172 #define MEMCTRL_NMICON_NMIWDTEN_NMI_EN 0
174 #ifndef MEMCTRL_NMICON_NMISTOFEN_NMI_EN
175 #define MEMCTRL_NMICON_NMISTOFEN_NMI_EN 0
177 #ifndef ADC2_UPTH0_INT_EN
178 #define ADC2_UPTH0_INT_EN 0
180 #ifndef ADC2_LOTH0_INT_EN
181 #define ADC2_LOTH0_INT_EN 0
183 #ifndef ADC2_LOTH1_INT_EN
184 #define ADC2_LOTH1_INT_EN 0
186 #ifndef ADC2_UPTH2_INT_EN
187 #define ADC2_UPTH2_INT_EN 0
189 #ifndef ADC2_LOTH2_INT_EN
190 #define ADC2_LOTH2_INT_EN 0
192 #ifndef ADC2_LOTH3_INT_EN
193 #define ADC2_LOTH3_INT_EN 0
195 #ifndef ADC2_UPTH4_INT_EN
196 #define ADC2_UPTH4_INT_EN 0
198 #ifndef CANTRX_BUS_TO_INT_EN
199 #define CANTRX_BUS_TO_INT_EN 0
201 #ifndef CANTRX_TXD_TO_INT_EN
202 #define CANTRX_TXD_TO_INT_EN 0
204 #ifndef CANTRX_OT_INT_EN
205 #define CANTRX_OT_INT_EN 0
207 #ifndef CANTRX_BUS_ACT_INT_EN
208 #define CANTRX_BUS_ACT_INT_EN 0
210 #ifndef BDRV_LS1_OC_INT_EN
211 #define BDRV_LS1_OC_INT_EN 0
213 #ifndef BDRV_LS1_DS_INT_EN
214 #define BDRV_LS1_DS_INT_EN 0
216 #ifndef BDRV_HS1_OC_INT_EN
217 #define BDRV_HS1_OC_INT_EN 0
219 #ifndef BDRV_HS1_DS_INT_EN
220 #define BDRV_HS1_DS_INT_EN 0
222 #ifndef BDRV_LS2_OC_INT_EN
223 #define BDRV_LS2_OC_INT_EN 0
225 #ifndef BDRV_LS2_DS_INT_EN
226 #define BDRV_LS2_DS_INT_EN 0
228 #ifndef BDRV_HS2_OC_INT_EN
229 #define BDRV_HS2_OC_INT_EN 0
231 #ifndef BDRV_HS2_DS_INT_EN
232 #define BDRV_HS2_DS_INT_EN 0
234 #ifndef BDRV_LS3_OC_INT_EN
235 #define BDRV_LS3_OC_INT_EN 0
237 #ifndef BDRV_LS3_DS_INT_EN
238 #define BDRV_LS3_DS_INT_EN 0
240 #ifndef BDRV_HS3_OC_INT_EN
241 #define BDRV_HS3_OC_INT_EN 0
243 #ifndef BDRV_HS3_DS_INT_EN
244 #define BDRV_HS3_DS_INT_EN 0
246 #ifndef BDRV_HB1_ASEQ_INT_EN
247 #define BDRV_HB1_ASEQ_INT_EN 0
249 #ifndef BDRV_HB2_ASEQ_INT_EN
250 #define BDRV_HB2_ASEQ_INT_EN 0
252 #ifndef BDRV_HB3_ASEQ_INT_EN
253 #define BDRV_HB3_ASEQ_INT_EN 0
255 #ifndef BDRV_SEQ_ERR_INT_EN
256 #define BDRV_SEQ_ERR_INT_EN 0
258 #ifndef BDRV_HB1_ACTDRV_INT_EN
259 #define BDRV_HB1_ACTDRV_INT_EN 0
261 #ifndef BDRV_HB2_ACTDRV_INT_EN
262 #define BDRV_HB2_ACTDRV_INT_EN 0
264 #ifndef BDRV_HB3_ACTDRV_INT_EN
265 #define BDRV_HB3_ACTDRV_INT_EN 0
267 #ifndef BDRV_VCP_LOTH2_INT_EN
268 #define BDRV_VCP_LOTH2_INT_EN 0
270 #ifndef CSACSC_OC_INT_EN
271 #define CSACSC_OC_INT_EN 0
273 #ifndef CSACSC_PARAM_INT_EN
274 #define CSACSC_PARAM_INT_EN 0
276 #ifndef PMU_VDDP_UVWARN_INT_EN
277 #define PMU_VDDP_UVWARN_INT_EN 0
279 #ifndef PMU_VDDP_OV_INT_EN
280 #define PMU_VDDP_OV_INT_EN 0
282 #ifndef PMU_VDDC_UVWARN_INT_EN
283 #define PMU_VDDC_UVWARN_INT_EN 0
285 #ifndef PMU_VDDC_OV_INT_EN
286 #define PMU_VDDC_OV_INT_EN 0
288 #ifndef PMU_VDDEXT_UV_INT_EN
289 #define PMU_VDDEXT_UV_INT_EN 0
291 #ifndef PMU_VDDEXT_OT_INT_EN
292 #define PMU_VDDEXT_OT_INT_EN 0
294 #ifndef ARVG_VAREF_OC_INT_EN
295 #define ARVG_VAREF_OC_INT_EN 0
297 #ifndef CCU7_T12_OM_INT_EN
298 #define CCU7_T12_OM_INT_EN 0
300 #ifndef CCU7_T12_PM_INT_EN
301 #define CCU7_T12_PM_INT_EN 0
303 #ifndef CCU7_T13_CM_INT_EN
304 #define CCU7_T13_CM_INT_EN 0
306 #ifndef CCU7_T13_PM_INT_EN
307 #define CCU7_T13_PM_INT_EN 0
309 #ifndef CCU7_T14_CM_INT_EN
310 #define CCU7_T14_CM_INT_EN 0
312 #ifndef CCU7_T14_PM_INT_EN
313 #define CCU7_T14_PM_INT_EN 0
315 #ifndef CCU7_T15_CM_INT_EN
316 #define CCU7_T15_CM_INT_EN 0
318 #ifndef CCU7_T15_PM_INT_EN
319 #define CCU7_T15_PM_INT_EN 0
321 #ifndef CCU7_T16_CM_INT_EN
322 #define CCU7_T16_CM_INT_EN 0
324 #ifndef CCU7_T16_PM_INT_EN
325 #define CCU7_T16_PM_INT_EN 0
327 #ifndef CCU7_CC70A_CM_R_INT_EN
328 #define CCU7_CC70A_CM_R_INT_EN 0
330 #ifndef CCU7_CC70A_CM_F_INT_EN
331 #define CCU7_CC70A_CM_F_INT_EN 0
333 #ifndef CCU7_CC71A_CM_R_INT_EN
334 #define CCU7_CC71A_CM_R_INT_EN 0
336 #ifndef CCU7_CC71A_CM_F_INT_EN
337 #define CCU7_CC71A_CM_F_INT_EN 0
339 #ifndef CCU7_CC71A_CM_R_INT_EN
340 #define CCU7_CC71A_CM_R_INT_EN 0
342 #ifndef CCU7_CC71A_CM_F_INT_EN
343 #define CCU7_CC71A_CM_F_INT_EN 0
345 #ifndef CCU7_C70B_CM_R_INT_EN
346 #define CCU7_C70B_CM_R_INT_EN 0
348 #ifndef CCU7_C70B_CM_F_INT_EN
349 #define CCU7_C70B_CM_F_INT_EN 0
351 #ifndef CCU7_C71B_CM_R_INT_EN
352 #define CCU7_C71B_CM_R_INT_EN 0
354 #ifndef CCU7_C71B_CM_F_INT_EN
355 #define CCU7_C71B_CM_F_INT_EN 0
357 #ifndef CCU7_C72B_CM_R_INT_EN
358 #define CCU7_C72B_CM_R_INT_EN 0
360 #ifndef CCU7_C72B_CM_F_INT_EN
361 #define CCU7_C72B_CM_F_INT_EN 0
363 #ifndef CCU7_TRAP_INT_EN
364 #define CCU7_TRAP_INT_EN 0
366 #ifndef CCU7_CORRECT_HALL_INT_EN
367 #define CCU7_CORRECT_HALL_INT_EN 0
369 #ifndef CCU7_WRONG_HALL_INT_EN
370 #define CCU7_WRONG_HALL_INT_EN 0
372 #ifndef CCU7_MCM_STR_INT_EN
373 #define CCU7_MCM_STR_INT_EN 0
375 #ifndef CCU7_LI_INT_EN
376 #define CCU7_LI_INT_EN 0
378 #ifndef MEMCTRL_NVM0_OP_COMPLETE_INT_EN
379 #define MEMCTRL_NVM0_OP_COMPLETE_INT_EN 0
381 #ifndef MEMCTRL_NVM1_OP_COMPLETE_INT_EN
382 #define MEMCTRL_NVM1_OP_COMPLETE_INT_EN 0
384 #ifndef GPT12_GPT1T2_INT_EN
385 #define GPT12_GPT1T2_INT_EN 0
387 #ifndef GPT12_GPT1T3_INT_EN
388 #define GPT12_GPT1T3_INT_EN 0
390 #ifndef GPT12_GPT1T4_INT_EN
391 #define GPT12_GPT1T4_INT_EN 0
393 #ifndef GPT12_GPT2T5_INT_EN
394 #define GPT12_GPT2T5_INT_EN 0
396 #ifndef GPT12_GPT2T6_INT_EN
397 #define GPT12_GPT2T6_INT_EN 0
399 #ifndef GPT12_GPT2CAPREL_INT_EN
400 #define GPT12_GPT2CAPREL_INT_EN 0
402 #ifndef ADC2_CH0_INT_EN
403 #define ADC2_CH0_INT_EN 0
405 #ifndef ADC2_CH1_INT_EN
406 #define ADC2_CH1_INT_EN 0
408 #ifndef ADC2_CH2_INT_EN
409 #define ADC2_CH2_INT_EN 0
411 #ifndef ADC2_CH3_INT_EN
412 #define ADC2_CH3_INT_EN 0
414 #ifndef ADC2_CH4_INT_EN
415 #define ADC2_CH4_INT_EN 0
417 #ifndef ADC2_CH5_INT_EN
418 #define ADC2_CH5_INT_EN 0
420 #ifndef ADC2_CH6_INT_EN
421 #define ADC2_CH6_INT_EN 0
423 #ifndef ADC2_CH7_INT_EN
424 #define ADC2_CH7_INT_EN 0
426 #ifndef ADC2_CH8_INT_EN
427 #define ADC2_CH8_INT_EN 0
429 #ifndef ADC2_CH9_INT_EN
430 #define ADC2_CH9_INT_EN 0
432 #ifndef ADC2_CH10_INT_EN
433 #define ADC2_CH10_INT_EN 0
435 #ifndef ADC2_CH11_INT_EN
436 #define ADC2_CH11_INT_EN 0
438 #ifndef ADC2_CH12_INT_EN
439 #define ADC2_CH12_INT_EN 0
441 #ifndef ADC2_CH13_INT_EN
442 #define ADC2_CH13_INT_EN 0
444 #ifndef ADC2_CH14_INT_EN
445 #define ADC2_CH14_INT_EN 0
447 #ifndef ADC2_SQ0_INT_EN
448 #define ADC2_SQ0_INT_EN 0
450 #ifndef ADC2_SQ1_INT_EN
451 #define ADC2_SQ1_INT_EN 0
453 #ifndef ADC2_SQ2_INT_EN
454 #define ADC2_SQ2_INT_EN 0
456 #ifndef ADC2_SQ3_INT_EN
457 #define ADC2_SQ3_INT_EN 0
459 #ifndef ADC2_LOTH0_INT_EN
460 #define ADC2_LOTH0_INT_EN 0
462 #ifndef ADC2_LOTH1_INT_EN
463 #define ADC2_LOTH1_INT_EN 0
465 #ifndef ADC2_LOTH2_INT_EN
466 #define ADC2_LOTH2_INT_EN 0
468 #ifndef ADC2_LOTH3_INT_EN
469 #define ADC2_LOTH3_INT_EN 0
471 #ifndef ADC2_LOTH4_INT_EN
472 #define ADC2_LOTH4_INT_EN 0
474 #ifndef ADC2_LOTH5_INT_EN
475 #define ADC2_LOTH5_INT_EN 0
477 #ifndef ADC2_LOTH6_INT_EN
478 #define ADC2_LOTH6_INT_EN 0
480 #ifndef ADC2_LOTH7_INT_EN
481 #define ADC2_LOTH7_INT_EN 0
483 #ifndef ADC2_UPTH0_INT_EN
484 #define ADC2_UPTH0_INT_EN 0
486 #ifndef ADC2_UPTH1_INT_EN
487 #define ADC2_UPTH1_INT_EN 0
489 #ifndef ADC2_UPTH2_INT_EN
490 #define ADC2_UPTH2_INT_EN 0
492 #ifndef ADC2_UPTH3_INT_EN
493 #define ADC2_UPTH3_INT_EN 0
495 #ifndef ADC2_UPTH4_INT_EN
496 #define ADC2_UPTH4_INT_EN 0
498 #ifndef ADC2_UPTH5_INT_EN
499 #define ADC2_UPTH5_INT_EN 0
501 #ifndef ADC2_UPTH6_INT_EN
502 #define ADC2_UPTH6_INT_EN 0
504 #ifndef ADC2_UPTH7_INT_EN
505 #define ADC2_UPTH7_INT_EN 0
507 #ifndef MON_MON1_R_INT_EN
508 #define MON_MON1_R_INT_EN 0
510 #ifndef MON_MON1_F_INT_EN
511 #define MON_MON1_F_INT_EN 0
513 #ifndef MON_MON2_R_INT_EN
514 #define MON_MON2_R_INT_EN 0
516 #ifndef MON_MON2_F_INT_EN
517 #define MON_MON2_F_INT_EN 0
519 #ifndef MON_MON3_R_INT_EN
520 #define MON_MON3_R_INT_EN 0
522 #ifndef MON_MON3_F_INT_EN
523 #define MON_MON3_F_INT_EN 0
525 #ifndef ADC1_CH0_INT_EN
526 #define ADC1_CH0_INT_EN 0
528 #ifndef ADC1_CH1_INT_EN
529 #define ADC1_CH1_INT_EN 0
531 #ifndef ADC1_CH2_INT_EN
532 #define ADC1_CH2_INT_EN 0
534 #ifndef ADC1_CH3_INT_EN
535 #define ADC1_CH3_INT_EN 0
537 #ifndef ADC1_CH4_INT_EN
538 #define ADC1_CH4_INT_EN 0
540 #ifndef ADC1_CH5_INT_EN
541 #define ADC1_CH5_INT_EN 0
543 #ifndef ADC1_CH6_INT_EN
544 #define ADC1_CH6_INT_EN 0
546 #ifndef ADC1_CH7_INT_EN
547 #define ADC1_CH7_INT_EN 0
549 #ifndef ADC1_CH8_INT_EN
550 #define ADC1_CH8_INT_EN 0
552 #ifndef ADC1_CH9_INT_EN
553 #define ADC1_CH9_INT_EN 0
555 #ifndef ADC1_CH10_INT_EN
556 #define ADC1_CH10_INT_EN 0
558 #ifndef ADC1_CH11_INT_EN
559 #define ADC1_CH11_INT_EN 0
561 #ifndef ADC1_CH12_INT_EN
562 #define ADC1_CH12_INT_EN 0
564 #ifndef ADC1_CH13_INT_EN
565 #define ADC1_CH13_INT_EN 0
567 #ifndef ADC1_CH14_INT_EN
568 #define ADC1_CH14_INT_EN 0
570 #ifndef ADC1_CH15_INT_EN
571 #define ADC1_CH15_INT_EN 0
573 #ifndef ADC1_CH16_INT_EN
574 #define ADC1_CH16_INT_EN 0
576 #ifndef ADC1_CH17_INT_EN
577 #define ADC1_CH17_INT_EN 0
579 #ifndef ADC1_CH18_INT_EN
580 #define ADC1_CH18_INT_EN 0
582 #ifndef ADC1_CH19_INT_EN
583 #define ADC1_CH19_INT_EN 0
585 #ifndef ADC1_SQ0_INT_EN
586 #define ADC1_SQ0_INT_EN 0
588 #ifndef ADC1_SQ1_INT_EN
589 #define ADC1_SQ1_INT_EN 0
591 #ifndef ADC1_SQ2_INT_EN
592 #define ADC1_SQ2_INT_EN 0
594 #ifndef ADC1_SQ3_INT_EN
595 #define ADC1_SQ3_INT_EN 0
597 #ifndef ADC1_LOTH0_INT_EN
598 #define ADC1_LOTH0_INT_EN 0
600 #ifndef ADC1_LOTH1_INT_EN
601 #define ADC1_LOTH1_INT_EN 0
603 #ifndef ADC1_LOTH2_INT_EN
604 #define ADC1_LOTH2_INT_EN 0
606 #ifndef ADC1_LOTH3_INT_EN
607 #define ADC1_LOTH3_INT_EN 0
609 #ifndef ADC1_UPTH0_INT_EN
610 #define ADC1_UPTH0_INT_EN 0
612 #ifndef ADC1_UPTH1_INT_EN
613 #define ADC1_UPTH1_INT_EN 0
615 #ifndef ADC1_UPTH2_INT_EN
616 #define ADC1_UPTH2_INT_EN 0
618 #ifndef ADC1_UPTH3_INT_EN
619 #define ADC1_UPTH3_INT_EN 0
621 #ifndef ADC1_COLL0_INT_EN
622 #define ADC1_COLL0_INT_EN 0
624 #ifndef ADC1_COLL1_INT_EN
625 #define ADC1_COLL1_INT_EN 0
627 #ifndef ADC1_COLL2_INT_EN
628 #define ADC1_COLL2_INT_EN 0
630 #ifndef ADC1_COLL3_INT_EN
631 #define ADC1_COLL3_INT_EN 0
633 #ifndef ADC1_WFR0_INT_EN
634 #define ADC1_WFR0_INT_EN 0
636 #ifndef ADC1_WFR1_INT_EN
637 #define ADC1_WFR1_INT_EN 0
639 #ifndef ADC1_WFR2_INT_EN
640 #define ADC1_WFR2_INT_EN 0
642 #ifndef ADC1_WFR3_INT_EN
643 #define ADC1_WFR3_INT_EN 0
645 #ifndef BDRV_PH1_ZC_RISE_INT_EN
646 #define BDRV_PH1_ZC_RISE_INT_EN 0
648 #ifndef BDRV_PH1_ZC_FALL_INT_EN
649 #define BDRV_PH1_ZC_FALL_INT_EN 0
651 #ifndef BDRV_PH2_ZC_RISE_INT_EN
652 #define BDRV_PH2_ZC_RISE_INT_EN 0
654 #ifndef BDRV_PH2_ZC_FALL_INT_EN
655 #define BDRV_PH2_ZC_FALL_INT_EN 0
657 #ifndef BDRV_PH3_ZC_RISE_INT_EN
658 #define BDRV_PH3_ZC_RISE_INT_EN 0
660 #ifndef BDRV_PH3_ZC_FALL_INT_EN
661 #define BDRV_PH3_ZC_FALL_INT_EN 0
663 #ifndef SDADC_RES0_INT_EN
664 #define SDADC_RES0_INT_EN 0
666 #ifndef SDADC_CMP0_UP_INT_EN
667 #define SDADC_CMP0_UP_INT_EN 0
669 #ifndef SDADC_CMP0_LO_INT_EN
670 #define SDADC_CMP0_LO_INT_EN 0
672 #ifndef SDADC_RES1_INT_EN
673 #define SDADC_RES1_INT_EN 0
675 #ifndef SDADC_CMP1_UP_INT_EN
676 #define SDADC_CMP1_UP_INT_EN 0
678 #ifndef SDADC_CMP1_LO_INT_EN
679 #define SDADC_CMP1_LO_INT_EN 0
681 #ifndef SCU_EXTINT0_RISING_INT_EN
682 #define SCU_EXTINT0_RISING_INT_EN 0
684 #ifndef SCU_EXTINT0_FALLING_INT_EN
685 #define SCU_EXTINT0_FALLING_INT_EN 0
687 #ifndef SCU_EXTINT1_RISING_INT_EN
688 #define SCU_EXTINT1_RISING_INT_EN 0
690 #ifndef SCU_EXTINT1_FALLING_INT_EN
691 #define SCU_EXTINT1_FALLING_INT_EN 0
693 #ifndef SCU_EXTINT2_RISING_INT_EN
694 #define SCU_EXTINT2_RISING_INT_EN 0
696 #ifndef SCU_EXTINT2_FALLING_INT_EN
697 #define SCU_EXTINT2_FALLING_INT_EN 0
699 #ifndef SCU_EXTINT3_RISING_INT_EN
700 #define SCU_EXTINT3_RISING_INT_EN 0
702 #ifndef SCU_EXTINT3_FALLING_INT_EN
703 #define SCU_EXTINT3_FALLING_INT_EN 0
705 #ifndef UART0_TI_INT_EN
706 #define UART0_TI_INT_EN 0
708 #ifndef UART0_RI_INT_EN
709 #define UART0_RI_INT_EN 0
711 #ifndef UART0_EOS_INT_EN
712 #define UART0_EOS_INT_EN 0
714 #ifndef UART0_SYNCERR_INT_EN
715 #define UART0_SYNCERR_INT_EN 0
717 #ifndef UART1_TI_INT_EN
718 #define UART1_TI_INT_EN 0
720 #ifndef UART1_RI_INT_EN
721 #define UART1_RI_INT_EN 0
723 #ifndef UART1_EOS_INT_EN
724 #define UART1_EOS_INT_EN 0
726 #ifndef UART1_SYNCERR_INT_EN
727 #define UART1_SYNCERR_INT_EN 0
729 #ifndef SSC0_TI_INT_EN
730 #define SSC0_TI_INT_EN 0
732 #ifndef SSC0_RI_INT_EN
733 #define SSC0_RI_INT_EN 0
735 #ifndef SSC0_ERR_INT_EN
736 #define SSC0_ERR_INT_EN 0
738 #ifndef SSC0_ERR_INT_EN
739 #define SSC0_ERR_INT_EN 0
741 #ifndef SSC0_ERR_INT_EN
742 #define SSC0_ERR_INT_EN 0
744 #ifndef SSC0_ERR_INT_EN
745 #define SSC0_ERR_INT_EN 0
747 #ifndef SSC1_TI_INT_EN
748 #define SSC1_TI_INT_EN 0
750 #ifndef SSC1_RI_INT_EN
751 #define SSC1_RI_INT_EN 0
753 #ifndef SSC1_ERR_INT_EN
754 #define SSC1_ERR_INT_EN 0
756 #ifndef SSC1_ERR_INT_EN
757 #define SSC1_ERR_INT_EN 0
759 #ifndef SSC1_ERR_INT_EN
760 #define SSC1_ERR_INT_EN 0
762 #ifndef SSC1_ERR_INT_EN
763 #define SSC1_ERR_INT_EN 0
765 #ifndef DMA_CH0_INT_EN
766 #define DMA_CH0_INT_EN 0
768 #ifndef DMA_CH1_INT_EN
769 #define DMA_CH1_INT_EN 0
771 #ifndef DMA_CH2_INT_EN
772 #define DMA_CH2_INT_EN 0
774 #ifndef DMA_CH3_INT_EN
775 #define DMA_CH3_INT_EN 0
777 #ifndef DMA_CH4_INT_EN
778 #define DMA_CH4_INT_EN 0
780 #ifndef DMA_CH5_INT_EN
781 #define DMA_CH5_INT_EN 0
783 #ifndef DMA_CH6_INT_EN
784 #define DMA_CH6_INT_EN 0
786 #ifndef DMA_CH7_INT_EN
787 #define DMA_CH7_INT_EN 0
789 #ifndef DMA_ERROR_INT_EN
790 #define DMA_ERROR_INT_EN 0
792 #ifndef T20_EXF2_INT_EN
793 #define T20_EXF2_INT_EN 0
795 #ifndef T20_TF2_INT_EN
796 #define T20_TF2_INT_EN 0
798 #ifndef T21_EXF2_INT_EN
799 #define T21_EXF2_INT_EN 0
801 #ifndef T21_TF2_INT_EN
802 #define T21_TF2_INT_EN 0
814 #if (NVIC_IRQ0_HANDLER_INT_CHECK == 1)
815 extern uint8 u8_interrupt_cnt_irq0;
817 #if (NVIC_IRQ1_HANDLER_INT_CHECK == 1)
818 extern uint8 u8_interrupt_cnt_irq1;
820 #if (NVIC_IRQ2_HANDLER_INT_CHECK == 1)
821 extern uint8 u8_interrupt_cnt_irq2;
823 #if (NVIC_IRQ3_HANDLER_INT_CHECK == 1)
824 extern uint8 u8_interrupt_cnt_irq3;
826 #if (NVIC_IRQ4_HANDLER_INT_CHECK == 1)
827 extern uint8 u8_interrupt_cnt_irq4;
829 #if (NVIC_IRQ5_HANDLER_INT_CHECK == 1)
830 extern uint8 u8_interrupt_cnt_irq5;
832 #if (NVIC_IRQ6_HANDLER_INT_CHECK == 1)
833 extern uint8 u8_interrupt_cnt_irq6;
835 #if (NVIC_IRQ7_HANDLER_INT_CHECK == 1)
836 extern uint8 u8_interrupt_cnt_irq7;
838 #if (NVIC_IRQ8_HANDLER_INT_CHECK == 1)
839 extern uint8 u8_interrupt_cnt_irq8;
841 #if (NVIC_IRQ10_HANDLER_INT_CHECK == 1)
842 extern uint8 u8_interrupt_cnt_irq10;
844 #if (NVIC_IRQ11_HANDLER_INT_CHECK == 1)
845 extern uint8 u8_interrupt_cnt_irq11;
847 #if (NVIC_IRQ12_HANDLER_INT_CHECK == 1)
848 extern uint8 u8_interrupt_cnt_irq12;
850 #if (NVIC_IRQ13_HANDLER_INT_CHECK == 1)
851 extern uint8 u8_interrupt_cnt_irq13;
853 #if (NVIC_IRQ14_HANDLER_INT_CHECK == 1)
854 extern uint8 u8_interrupt_cnt_irq14;
856 #if (NVIC_IRQ15_HANDLER_INT_CHECK == 1)
857 extern uint8 u8_interrupt_cnt_irq15;
859 #if (NVIC_IRQ16_HANDLER_INT_CHECK == 1)
860 extern uint8 u8_interrupt_cnt_irq16;
862 #if (NVIC_IRQ17_HANDLER_INT_CHECK == 1)
863 extern uint8 u8_interrupt_cnt_irq17;
865 #if (NVIC_IRQ18_HANDLER_INT_CHECK == 1)
866 extern uint8 u8_interrupt_cnt_irq18;
868 #if (NVIC_IRQ19_HANDLER_INT_CHECK == 1)
869 extern uint8 u8_interrupt_cnt_irq19;
871 #if (NVIC_IRQ20_HANDLER_INT_CHECK == 1)
872 extern uint8 u8_interrupt_cnt_irq20;
874 #if (NVIC_IRQ21_HANDLER_INT_CHECK == 1)
875 extern uint8 u8_interrupt_cnt_irq21;
877 #if (NVIC_IRQ22_HANDLER_INT_CHECK == 1)
878 extern uint8 u8_interrupt_cnt_irq22;
880 #if (NVIC_IRQ23_HANDLER_INT_CHECK == 1)
881 extern uint8 u8_interrupt_cnt_irq23;
883 #if (NVIC_IRQ24_HANDLER_INT_CHECK == 1)
884 extern uint8 u8_interrupt_cnt_irq24;
886 #if (NVIC_IRQ25_HANDLER_INT_CHECK == 1)
887 extern uint8 u8_interrupt_cnt_irq25;
889 #if (NVIC_IRQ26_HANDLER_INT_CHECK == 1)
890 extern uint8 u8_interrupt_cnt_irq26;
892 #if (NVIC_IRQ27_HANDLER_INT_CHECK == 1)
893 extern uint8 u8_interrupt_cnt_irq27;
895 #if (NVIC_IRQ28_HANDLER_INT_CHECK == 1)
896 extern uint8 u8_interrupt_cnt_irq28;
898 #if (NVIC_IRQ29_HANDLER_INT_CHECK == 1)
899 extern uint8 u8_interrupt_cnt_irq29;
901 #if (NVIC_IRQ30_HANDLER_INT_CHECK == 1)
902 extern uint8 u8_interrupt_cnt_irq30;
904 #if (NVIC_IRQ9_HANDLER_INT_CHECK == 1)
905 extern uint8 u8_interrupt_cnt_irq9;
907 #if (NVIC_IRQ31_HANDLER_INT_CHECK == 1)
908 extern uint8 u8_interrupt_cnt_irq31;
Interrupt Service Routines low level access library.
void SCU_EXTINT1_RISING_CALLBACK(void)
void PMU_VDDEXT_OT_CALLBACK(void)
void MON_MON3_F_CALLBACK(void)
void CCU7_WRONG_HALL_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXPND_CALLBACK(void)
void ADC1_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG3_TXPND_CALLBACK(void)
void CPU_PENDSV_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXOVF_CALLBACK(void)
void NVIC_IRQ28_Handler(void)
Definition: startup_tle989x.c:308
void CPU_USAGEFAULT_CALLBACK(void)
void BDRV_LS2_OC_CALLBACK(void)
void DMA_CH4_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXPND_CALLBACK(void)
void BDRV_HB3_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXPND_CALLBACK(void)
void ADC1_UPTH2_CALLBACK(void)
void NVIC_IRQ3_Handler(void)
Definition: startup_tle989x.c:283
void CANNODE_NODE0_BOFF_CALLBACK(void)
void CCU7_T12_PM_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXOVF_CALLBACK(void)
void ADC1_WFR0_CALLBACK(void)
void NVIC_IRQ26_Handler(void)
Definition: startup_tle989x.c:306
void CANMSGOBJ0_MSG3_TXOVF_CALLBACK(void)
void MEMCTRL_NMICON_NMIDSEN_CALLBACK(void)
void DMA_CH6_CALLBACK(void)
void ADC1_WFR2_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXPND_CALLBACK(void)
void SSC1_BEI_CALLBACK(void)
void NVIC_IRQ21_Handler(void)
Definition: startup_tle989x.c:301
void CANMSGOBJ0_MSG4_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXOVF_CALLBACK(void)
void ADC1_CH0_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXPND_CALLBACK(void)
void ADC1_LOTH1_CALLBACK(void)
void ADC2_CH1_CALLBACK(void)
void T21_TF2_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP1EN_CALLBACK(void)
void CANNODE_NODE0_RXOK_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXPND_CALLBACK(void)
void SSC0_REI_CALLBACK(void)
void BDRV_LS2_DS_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXOVF_CALLBACK(void)
void SDADC_CMP0_UP_CALLBACK(void)
void CSACSC_OC_CALLBACK(void)
void SCU_EXTINT1_FALLING_CALLBACK(void)
void SCU_NMICON_NMIXTALEN_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXOVF_CALLBACK(void)
void NVIC_IRQ10_Handler(void)
Definition: startup_tle989x.c:290
void CANMSGOBJ0_MSG28_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG30_RXPND_CALLBACK(void)
void UsageFault_Handler(void)
UsageFault ISR.
Definition: startup_tle989x.c:264
void T21_EXF2_CALLBACK(void)
void ADC1_COLL0_CALLBACK(void)
void CCU7_C71B_CM_R_CALLBACK(void)
void PMU_VDDP_OV_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG7_RXPND_CALLBACK(void)
void NVIC_IRQ20_Handler(void)
Definition: startup_tle989x.c:300
void CANMSGOBJ0_MSG21_TXOVF_CALLBACK(void)
void UART0_RI_CALLBACK(void)
void BDRV_PH1_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXPND_CALLBACK(void)
void HardFault_Handler(void)
HardFault ISR.
Definition: startup_tle989x.c:261
void MON_MON2_F_CALLBACK(void)
void ADC1_COLL1_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG24_RXOVF_CALLBACK(void)
void SDADC_RES1_CALLBACK(void)
void SSC0_PEI_CALLBACK(void)
void CCU7_CC71A_CM_F_CALLBACK(void)
void CCU7_T12_OM_CALLBACK(void)
void BDRV_PH2_ZC_FALL_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXOVF_CALLBACK(void)
void UART0_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_RXPND_CALLBACK(void)
void MemManage_Handler(void)
MemManage ISR.
Definition: startup_tle989x.c:262
void SCU_EXTINT3_FALLING_CALLBACK(void)
void ADC1_UPTH1_CALLBACK(void)
void NVIC_IRQ17_Handler(void)
Definition: startup_tle989x.c:297
void NVIC_IRQ1_Handler(void)
Definition: startup_tle989x.c:281
void ADC2_SQ1_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXOVF_CALLBACK(void)
void ADC2_UPTH4_CALLBACK(void)
void CANMSGOBJ0_MSG29_RXPND_CALLBACK(void)
void MEMCTRL_NMICON_NMIPSEN_CALLBACK(void)
void PMU_VDDC_UVWARN_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXPND_CALLBACK(void)
void MON_MON2_R_CALLBACK(void)
void NVIC_IRQ29_Handler(void)
Definition: startup_tle989x.c:309
void CANMSGOBJ0_MSG19_RXPND_CALLBACK(void)
void CCU7_CC70A_CM_F_CALLBACK(void)
void MON_MON3_R_CALLBACK(void)
void UART1_SYNCERR_CALLBACK(void)
void SCU_NMICON_NMIPLL1EN_CALLBACK(void)
void CANMSGOBJ0_MSG16_RXPND_CALLBACK(void)
void MEMCTRL_NVM1_OP_COMPLETE_CALLBACK(void)
void BDRV_HS2_DS_CALLBACK(void)
void CCU7_T15_CM_CALLBACK(void)
void MEMCTRL_NMICON_NMICDEN_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXOVF_CALLBACK(void)
void ADC1_CH7_CALLBACK(void)
void ADC1_CH17_CALLBACK(void)
void BDRV_HS2_OC_CALLBACK(void)
void SDADC_CMP1_UP_CALLBACK(void)
void CANMSGOBJ0_MSG23_RXOVF_CALLBACK(void)
void CCU7_T14_PM_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXPND_CALLBACK(void)
void GPT12_GPT1T4_CALLBACK(void)
void ADC2_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXOVF_CALLBACK(void)
void BDRV_SEQ_ERR_CALLBACK(void)
void CANMSGOBJ0_MSG5_RXOVF_CALLBACK(void)
void CSACSC_PARAM_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXPND_CALLBACK(void)
void CANTRX_BUS_TO_CALLBACK(void)
void CCU7_T16_CM_CALLBACK(void)
void ADC1_CH5_CALLBACK(void)
void NVIC_IRQ12_Handler(void)
Definition: startup_tle989x.c:292
void UART0_SYNCERR_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXOVF_CALLBACK(void)
void ADC1_CH16_CALLBACK(void)
void CANMSGOBJ0_MSG4_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXPND_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXOVF_CALLBACK(void)
void BDRV_HS3_OC_CALLBACK(void)
void ADC1_CH19_CALLBACK(void)
void CCU7_MCM_STR_CALLBACK(void)
void UART1_TI_CALLBACK(void)
void NVIC_IRQ7_Handler(void)
Definition: startup_tle989x.c:287
void SDADC_CMP0_LO_CALLBACK(void)
void SCU_EXTINT0_FALLING_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG18_TXOVF_CALLBACK(void)
void ADC2_CH0_CALLBACK(void)
void SDADC_CMP1_LO_CALLBACK(void)
void ADC1_LOTH0_CALLBACK(void)
void ADC2_CH6_CALLBACK(void)
void UART1_EOS_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXOVF_CALLBACK(void)
void PMU_VDDC_OV_CALLBACK(void)
void PendSV_Handler(void)
PendSV ISR.
Definition: startup_tle989x.c:271
void NVIC_IRQ27_Handler(void)
Definition: startup_tle989x.c:307
void CCU7_C70B_CM_F_CALLBACK(void)
void SCU_NMICON_NMIPLL0EN_CALLBACK(void)
void CANMSGOBJ0_MSG20_RXPND_CALLBACK(void)
void CCU7_T15_PM_CALLBACK(void)
void GPT12_GPT1T2_CALLBACK(void)
void BDRV_HS3_DS_CALLBACK(void)
void SCU_EXTINT2_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXOVF_CALLBACK(void)
void NVIC_IRQ31_Handler(void)
Definition: startup_tle989x.c:312
void NMI_Handler(void)
NMI ISR.
Definition: startup_tle989x.c:260
void DMA_CH2_CALLBACK(void)
void ADC1_CH10_CALLBACK(void)
void ADC1_CH1_CALLBACK(void)
void ADC2_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_TXPND_CALLBACK(void)
void BDRV_LS3_DS_CALLBACK(void)
void NVIC_IRQ9_Handler(void)
Definition: startup_tle989x.c:289
void CANMSGOBJ0_MSG19_TXPND_CALLBACK(void)
void MON_MON1_R_CALLBACK(void)
void NVIC_IRQ8_Handler(void)
Definition: startup_tle989x.c:288
void NVIC_IRQ6_Handler(void)
void CANMSGOBJ0_MSG27_RXOVF_CALLBACK(void)
void BDRV_LS1_DS_CALLBACK(void)
void BDRV_LS3_OC_CALLBACK(void)
void CANMSGOBJ0_MSG17_TXOVF_CALLBACK(void)
void ADC2_CH5_CALLBACK(void)
void SSC0_RI_CALLBACK(void)
void CCU7_LI_CALLBACK(void)
void MEMCTRL_NMICON_NMISTOFEN_CALLBACK(void)
void DMA_CH0_CALLBACK(void)
void ADC2_LOTH7_CALLBACK(void)
void CANMSGOBJ0_MSG20_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXPND_CALLBACK(void)
void CPU_MEMMANAGE_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXOVF_CALLBACK(void)
void GPT12_GPT2CAPREL_CALLBACK(void)
void BDRV_PH3_ZC_FALL_CALLBACK(void)
void CPU_HARDFAULT_CALLBACK(void)
void CANMSGOBJ0_MSG9_TXPND_CALLBACK(void)
void SDADC_RES0_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM0EN_CALLBACK(void)
void ADC1_UPTH0_CALLBACK(void)
void CANMSGOBJ0_MSG21_TXPND_CALLBACK(void)
void ADC1_WFR1_CALLBACK(void)
void NVIC_IRQ13_Handler(void)
Definition: startup_tle989x.c:293
void CANMSGOBJ0_MSG16_RXOVF_CALLBACK(void)
void NVIC_IRQ16_Handler(void)
Definition: startup_tle989x.c:296
void ADC2_LOTH0_CALLBACK(void)
void SCU_EXTINT3_RISING_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXPND_CALLBACK(void)
void SSC1_PEI_CALLBACK(void)
void MEMCTRL_NMICON_NMINVM1EN_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG15_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG11_RXOVF_CALLBACK(void)
void CCU7_T13_PM_CALLBACK(void)
void ADC1_CH13_CALLBACK(void)
void UART0_TI_CALLBACK(void)
void PMU_VDDEXT_UV_CALLBACK(void)
void BusFault_Handler(void)
BusFault ISR.
Definition: startup_tle989x.c:263
void CANMSGOBJ0_MSG28_RXPND_CALLBACK(void)
void ADC2_CH11_CALLBACK(void)
void ADC2_CH3_CALLBACK(void)
void ADC2_CH4_CALLBACK(void)
void ADC1_COLL2_CALLBACK(void)
void ADC1_UPTH3_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXPND_CALLBACK(void)
void NVIC_IRQ0_Handler(void)
Definition: startup_tle989x.c:280
void BDRV_HB1_ASEQ_CALLBACK(void)
void ADC2_UPTH6_CALLBACK(void)
void ADC2_UPTH5_CALLBACK(void)
void BDRV_PH1_ZC_FALL_CALLBACK(void)
void MEMCTRL_NVM0_OP_COMPLETE_CALLBACK(void)
void GPT12_GPT2T5_CALLBACK(void)
void ADC1_CH11_CALLBACK(void)
void ADC1_LOTH2_CALLBACK(void)
void ADC2_UPTH1_CALLBACK(void)
void MEMCTRL_NMICON_NMIWDTEN_CALLBACK(void)
void CCU7_T13_CM_CALLBACK(void)
void ADC1_CH4_CALLBACK(void)
void ADC1_LOTH3_CALLBACK(void)
void PMU_VDDP_UVWARN_CALLBACK(void)
void CCU7_T14_CM_CALLBACK(void)
void CANMSGOBJ0_MSG0_TXOVF_CALLBACK(void)
void CCU7_T16_PM_CALLBACK(void)
void CANTRX_OT_CALLBACK(void)
void CANMSGOBJ0_MSG0_RXPND_CALLBACK(void)
void CCU7_CC72A_CM_R_CALLBACK(void)
void BDRV_HB2_ACTDRV_CALLBACK(void)
void ADC2_CH10_CALLBACK(void)
void CANMSGOBJ0_MSG30_TXPND_CALLBACK(void)
void NVIC_IRQ5_Handler(void)
Definition: startup_tle989x.c:285
void ADC1_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_RXPND_CALLBACK(void)
void ADC1_CH18_CALLBACK(void)
void SSC1_REI_CALLBACK(void)
void CANMSGOBJ0_MSG24_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG12_TXOVF_CALLBACK(void)
void ADC1_CH12_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXOVF_CALLBACK(void)
void SCU_EXTINT0_RISING_CALLBACK(void)
void SSC1_TEI_CALLBACK(void)
void NVIC_IRQ24_Handler(void)
Definition: startup_tle989x.c:304
void SSC0_BEI_CALLBACK(void)
void CANMSGOBJ0_MSG2_TXPND_CALLBACK(void)
void NVIC_IRQ18_Handler(void)
Definition: startup_tle989x.c:298
void CCU7_CC72A_CM_F_CALLBACK(void)
void T20_EXF2_CALLBACK(void)
void CANMSGOBJ0_MSG18_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG19_TXOVF_CALLBACK(void)
void NVIC_IRQ25_Handler(void)
Definition: startup_tle989x.c:305
void NVIC_IRQ22_Handler(void)
Definition: startup_tle989x.c:302
void CANMSGOBJ0_MSG7_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG21_RXPND_CALLBACK(void)
void ADC2_UPTH2_CALLBACK(void)
void ADC2_LOTH6_CALLBACK(void)
void ADC2_UPTH3_CALLBACK(void)
void DMA_CH7_CALLBACK(void)
void CANMSGOBJ0_MSG8_TXPND_CALLBACK(void)
void DMA_CH5_CALLBACK(void)
void CANMSGOBJ0_MSG1_RXPND_CALLBACK(void)
void SSC1_RI_CALLBACK(void)
void SysTick_Handler(void)
SysTick ISR.
Definition: startup_tle989x.c:273
void ADC2_SQ0_CALLBACK(void)
void CANMSGOBJ0_MSG27_TXPND_CALLBACK(void)
void UART1_RI_CALLBACK(void)
void CANMSGOBJ0_MSG22_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_RXPND_CALLBACK(void)
void ADC2_LOTH3_CALLBACK(void)
void DMA_CH1_CALLBACK(void)
void CANMSGOBJ0_MSG10_RXPND_CALLBACK(void)
void CCU7_C70B_CM_R_CALLBACK(void)
void CANNODE_NODE0_LEC_CALLBACK(void)
void CANMSGOBJ0_MSG19_RXOVF_CALLBACK(void)
void CPU_SYSTICK_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXPND_CALLBACK(void)
void ADC2_CH13_CALLBACK(void)
void CANNODE_NODE0_EWRN_CALLBACK(void)
void CANNODE_NODE0_LOE_CALLBACK(void)
void NVIC_IRQ11_Handler(void)
Definition: startup_tle989x.c:291
void CANMSGOBJ0_MSG6_RXOVF_CALLBACK(void)
volatile uint32 u32_globTimestamp_ms
Definition: isr_exceptions.c:42
void ADC1_SQ2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXOVF_CALLBACK(void)
void ADC2_LOTH1_CALLBACK(void)
void CANMSGOBJ0_MSG14_RXOVF_CALLBACK(void)
void NVIC_IRQ23_Handler(void)
Definition: startup_tle989x.c:303
void ADC1_CH15_CALLBACK(void)
void NVIC_IRQ19_Handler(void)
Definition: startup_tle989x.c:299
void ADC2_SQ3_CALLBACK(void)
void ADC1_CH8_CALLBACK(void)
void ADC2_CH14_CALLBACK(void)
void CANMSGOBJ0_MSG22_RXPND_CALLBACK(void)
void SCU_EXTINT2_FALLING_CALLBACK(void)
void CCU7_CC70A_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG16_TXOVF_CALLBACK(void)
void NVIC_IRQ30_Handler(void)
Definition: startup_tle989x.c:310
void DMA_ERROR_CALLBACK(void)
void GPT12_GPT2T6_CALLBACK(void)
void ADC2_CH9_CALLBACK(void)
void MON_MON1_F_CALLBACK(void)
void CANMSGOBJ0_MSG6_RXPND_CALLBACK(void)
void CANNODE_NODE0_CFCOV_CALLBACK(void)
void CANMSGOBJ0_MSG17_RXPND_CALLBACK(void)
void ADC2_CH2_CALLBACK(void)
void CCU7_C72B_CM_F_CALLBACK(void)
void SSC0_TEI_CALLBACK(void)
void CANMSGOBJ0_MSG11_TXOVF_CALLBACK(void)
void CCU7_TRAP_CALLBACK(void)
void ADC2_SQ2_CALLBACK(void)
void SSC0_TI_CALLBACK(void)
void ADC2_CH12_CALLBACK(void)
void CCU7_CC71A_CM_R_CALLBACK(void)
void ADC1_CH3_CALLBACK(void)
void BDRV_PH3_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG8_RXPND_CALLBACK(void)
void CCU7_C71B_CM_F_CALLBACK(void)
void ARVG_VAREF_OC_CALLBACK(void)
void ADC1_COLL3_CALLBACK(void)
void ADC2_LOTH5_CALLBACK(void)
void CANMSGOBJ0_MSG3_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXPND_CALLBACK(void)
void CANTRX_TXD_TO_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG1_TXPND_CALLBACK(void)
void NVIC_IRQ15_Handler(void)
Definition: startup_tle989x.c:295
void NVIC_IRQ2_Handler(void)
Definition: startup_tle989x.c:282
void BDRV_LS1_OC_CALLBACK(void)
void BDRV_HB1_ACTDRV_CALLBACK(void)
void CANMSGOBJ0_MSG2_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG23_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG13_TXOVF_CALLBACK(void)
void BDRV_HB2_ASEQ_CALLBACK(void)
void ADC1_SQ1_CALLBACK(void)
void CPU_BUSFAULT_CALLBACK(void)
void SSC1_TI_CALLBACK(void)
void DMA_CH3_CALLBACK(void)
void ADC2_CH8_CALLBACK(void)
void CANMSGOBJ0_MSG10_TXPND_CALLBACK(void)
void T20_TF2_CALLBACK(void)
void CANMSGOBJ0_MSG7_TXPND_CALLBACK(void)
void BDRV_HS1_OC_CALLBACK(void)
void GPT12_GPT1T3_CALLBACK(void)
void BDRV_HB3_ASEQ_CALLBACK(void)
void CANMSGOBJ0_MSG31_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG26_TXOVF_CALLBACK(void)
void CCU7_CORRECT_HALL_CALLBACK(void)
void BDRV_PH2_ZC_RISE_CALLBACK(void)
void CANMSGOBJ0_MSG29_TXPND_CALLBACK(void)
void NVIC_IRQ14_Handler(void)
Definition: startup_tle989x.c:294
void CANMSGOBJ0_MSG4_RXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG13_RXPND_CALLBACK(void)
void NVIC_IRQ4_Handler(void)
Definition: startup_tle989x.c:284
void CANMSGOBJ0_MSG8_RXOVF_CALLBACK(void)
void CANNODE_NODE0_TXOK_CALLBACK(void)
void MEMCTRL_NMICON_NMIMAP0EN_CALLBACK(void)
void ADC2_LOTH4_CALLBACK(void)
void CANMSGOBJ0_MSG5_TXOVF_CALLBACK(void)
void ADC1_WFR3_CALLBACK(void)
void ADC2_UPTH0_CALLBACK(void)
void ADC2_UPTH7_CALLBACK(void)
void CANMSGOBJ0_MSG25_RXPND_CALLBACK(void)
void ADC1_CH6_CALLBACK(void)
void ADC1_CH9_CALLBACK(void)
void CANNODE_NODE0_LLE_CALLBACK(void)
void CANMSGOBJ0_MSG9_RXOVF_CALLBACK(void)
void BDRV_VCP_LOTH2_CALLBACK(void)
void CANMSGOBJ0_MSG12_RXPND_CALLBACK(void)
void BDRV_HS1_DS_CALLBACK(void)
void CCU7_C72B_CM_R_CALLBACK(void)
void CANMSGOBJ0_MSG6_TXPND_CALLBACK(void)
void CANMSGOBJ0_MSG31_TXPND_CALLBACK(void)
INLINE uint32 INT_getGlobTimestamp(void)
Get the global timestamp value.
Definition: isr.h:1325
void ADC1_CH2_CALLBACK(void)
void CANMSGOBJ0_MSG28_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG4_TXOVF_CALLBACK(void)
void CANMSGOBJ0_MSG14_TXOVF_CALLBACK(void)
void CANTRX_BUS_ACT_CALLBACK(void)
void ADC1_SQ3_CALLBACK(void)
Device specific memory layout defines and features.
General type declarations.
#define INLINE
Definition: types.h:167
uint8_t uint8
8 bit unsigned value
Definition: types.h:220
uint32_t uint32
32 bit unsigned value
Definition: types.h:222