Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Data Fields
ARVG_Type Struct Reference

Detailed Description

ARVG (ARVG)

#include <tle989x.h>

Data Fields

union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   VREF1V2_UP: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
CFU_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OC_IS: 1
 
      uint32_t   __pad0__: 15
 
      __IOM uint32_t   OC_STS: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
VAREF_IRQ
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   OC_IS_SET: 1
 
      uint32_t   __pad0__: 15
 
      __OM uint32_t   OC_STS_SET: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
VAREF_IRQ_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   OC_IS_CLR: 1
 
      uint32_t   __pad0__: 15
 
      __OM uint32_t   OC_STS_CLR: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
VAREF_IRQ_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OC_IEN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
VAREF_IEN
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
VAREF_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      uint32_t   __pad0__: 8
 
      __IOM uint32_t   DTB4_OUT: 2
 
      __IOM uint32_t   DTB5_OUT: 2
 
      __IOM uint32_t   REFNVM_BI_SET: 2
 
      __IOM uint32_t   REFNVM_BI_EN: 1
 
      uint32_t   __pad1__: 1
 
      __IM uint32_t   VAREF_DIS_SHTDWN: 1
 
      __IOM uint32_t   REFNVM_BUF_PD_N: 1
 
      __IOM uint32_t   VREF_BUF_PD_N: 1
 
      __IOM uint32_t   VREF1V2_PD_N: 1
 
      __IOM uint32_t   IBIAS_PD_N: 1
 
      uint32_t   __pad2__: 3
 
      __IOM uint32_t   ATB0_SEL: 2
 
      __IOM uint32_t   ATB2_SEL: 2
 
      __IOM uint32_t   ATB3_SEL: 2
 
      __IOM uint32_t   MI_EN: 1
 
      __IOM uint32_t   TST_CTRL: 1
 
   }   bit
 
ARVG_TCR1
 
__IM uint32_t RESERVED1 [56]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TRIM_OUT: 4
 
      uint32_t   __pad0__: 28
 
   }   bit
 
VAREF_TRIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IBIAS: 5
 
      uint32_t   __pad0__: 3
 
      __IOM uint32_t   VREF1V2_TC: 3
 
      uint32_t   __pad1__: 1
 
      __IOM uint32_t   REFNVM: 2
 
      uint32_t   __pad2__: 18
 
   }   bit
 
CFU_TRIM
 
union {
   __IM uint32_t   reg
 
   struct {
      __IM uint32_t   VREF1V2_UP: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
CFU_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OC_IS: 1
 
      uint32_t   __pad0__: 15
 
      __IOM uint32_t   OC_STS: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
VAREF_IRQ
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   OC_IS_SET: 1
 
      uint32_t   __pad0__: 15
 
      __OM uint32_t   OC_STS_SET: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
VAREF_IRQ_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   OC_IS_CLR: 1
 
      uint32_t   __pad0__: 15
 
      __OM uint32_t   OC_STS_CLR: 1
 
      uint32_t   __pad1__: 15
 
   }   bit
 
VAREF_IRQ_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OC_IEN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
VAREF_IEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EN: 1
 
      uint32_t   __pad0__: 31
 
   }   bit
 
VAREF_CTRL
 

Field Documentation

◆ __pad0__

uint32_t __pad0__

◆ __pad1__

uint32_t __pad1__

◆ __pad2__

uint32_t __pad2__

◆ 

union { ... } ARVG_TCR1

◆ ATB0_SEL

__IOM uint32_t ATB0_SEL

[25..24] ATB0 bus assignment

◆ ATB2_SEL

__IOM uint32_t ATB2_SEL

[27..26] ATB2 bus assignment

◆ ATB3_SEL

__IOM uint32_t ATB3_SEL

[29..28] ATB0 bus assignment

◆  [1/15]

struct { ... } bit

◆  [2/15]

struct { ... } bit

◆  [3/15]

struct { ... } bit

◆  [4/15]

struct { ... } bit

◆  [5/15]

struct { ... } bit

◆  [6/15]

struct { ... } bit

◆  [7/15]

struct { ... } bit

◆  [8/15]

struct { ... } bit

◆  [9/15]

struct { ... } bit

◆  [10/15]

struct { ... } bit

◆  [11/15]

struct { ... } bit

◆  [12/15]

struct { ... } bit

◆  [13/15]

struct { ... } bit

◆  [14/15]

struct { ... } bit

◆  [15/15]

struct { ... } bit

◆  [1/2]

union { ... } CFU_STS

◆  [2/2]

union { ... } CFU_STS

◆ 

union { ... } CFU_TRIM

◆ DTB4_OUT

__IOM uint32_t DTB4_OUT

[9..8] DTB4 output assignment

◆ DTB5_OUT

__IOM uint32_t DTB5_OUT

[11..10] DTB5 output assignment

◆ EN

__IOM uint32_t EN

[0..0] VAREF enable bit

◆ IBIAS

__IOM uint32_t IBIAS

[4..0] Bias current trimming settings. Target value is 40uA, trimming step is 1uA.

◆ IBIAS_PD_N

__IOM uint32_t IBIAS_PD_N

[20..20] IBIAS enable bit (ibias_pd_n_i). Note: This bit is only valid if MI_EN is set.

◆ MI_EN

__IOM uint32_t MI_EN

[30..30] Module Isolation mode enable. Note: This bit is only valid if TST_CTRL is set.

◆ OC_IEN

__IOM uint32_t OC_IEN

[0..0] VAREF Overcurrent (undervoltage) Interrupt Enable

◆ OC_IS

__IOM uint32_t OC_IS

[0..0] VAREF overcurrent (undervoltage) interrupt.

◆ OC_IS_CLR

__OM uint32_t OC_IS_CLR

[0..0] VAREF overcurrent (undervoltage) interrupt clear

◆ OC_IS_SET

__OM uint32_t OC_IS_SET

[0..0] VAREF overcurrent (undervoltage) interrupt set

◆ OC_STS

__IOM uint32_t OC_STS

[16..16] VAREF overcurrent (undervoltage) status flag. The detection circuit monitors VAREF voltage.

◆ OC_STS_CLR

__OM uint32_t OC_STS_CLR

[16..16] VAREF overcurrent (undervoltage) status flag clear

◆ OC_STS_SET

__OM uint32_t OC_STS_SET

[16..16] VAREF overcurrent (undervoltage) status flag set. Setting this bit will trigger a VAREF switch off.

◆ REFNVM

__IOM uint32_t REFNVM

[13..12] NVM Reference trimming. Target value is 1.2V, trimming step is 5mV.

◆ REFNVM_BI_EN

__IOM uint32_t REFNVM_BI_EN

[14..14] NVM reference burn in enable

◆ REFNVM_BI_SET

__IOM uint32_t REFNVM_BI_SET

[13..12] NVM reference burn in settings. Increases NVM buffer output for BI stress test without changing VREF1V2 or VREF_BUF

◆ REFNVM_BUF_PD_N

__IOM uint32_t REFNVM_BUF_PD_N

[17..17] NVM buffer enable bit (refnvm_buf_pd_n_i). Note: This bit is only valid if MI_EN is set.

◆ reg [1/2]

__IM uint32_t reg

(@ 0x00000000) CFU status register

◆ reg [2/2]

__IOM uint32_t reg

(@ 0x00000004) VAREF Interrupt Status Register

(@ 0x00000008) VAREF Interrupt Set Register

(@ 0x0000000C) VAREF Interrupt Clear Register

(@ 0x00000010) VAREF Interrupt Enable Register

(@ 0x00000018) VAREF control register

(@ 0x0000001C) AVRG Test Control Register 1

(@ 0x00000100) VAREF Trimming Register

(@ 0x00000104) CFU trimming settings

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1[56]

◆ TRIM_OUT

__IOM uint32_t TRIM_OUT

[3..0] VAREF voltage trimming settings. Target value is 5V, trimming step is 20mV.

◆ TST_CTRL

__IOM uint32_t TST_CTRL

[31..31] Module test enable Signal

◆  [1/2]

union { ... } VAREF_CTRL

◆  [2/2]

union { ... } VAREF_CTRL

◆ VAREF_DIS_SHTDWN

__IM uint32_t VAREF_DIS_SHTDWN

[16..16] Disables VAREF automatic shutdown in case of overcurrent (undervoltage). Note: This bit is only valid if TST_CTRL is set.

◆  [1/2]

union { ... } VAREF_IEN

◆  [2/2]

union { ... } VAREF_IEN

◆  [1/2]

union { ... } VAREF_IRQ

◆  [2/2]

union { ... } VAREF_IRQ

◆  [1/2]

union { ... } VAREF_IRQ_CLR

◆  [2/2]

union { ... } VAREF_IRQ_CLR

◆  [1/2]

union { ... } VAREF_IRQ_SET

◆  [2/2]

union { ... } VAREF_IRQ_SET

◆ 

union { ... } VAREF_TRIM

◆ VREF1V2_PD_N

__IOM uint32_t VREF1V2_PD_N

[19..19] VREF1V2 enable bit (vref1v2_pd_n_i). Note: This bit is only valid if MI_EN is set.

◆ VREF1V2_TC

__IOM uint32_t VREF1V2_TC

[10..8] BandGap temperature coefficient trimming. Target value is 1.2V, trimming step is 5mV.

◆ VREF1V2_UP

__IM uint32_t VREF1V2_UP

[0..0] Reference voltage status

◆ VREF_BUF_PD_N

__IOM uint32_t VREF_BUF_PD_N

[18..18] VREF buffer enable bit (vref_buf_pd_n_i). Note: This bit is only valid if MI_EN is set.


The documentation for this struct was generated from the following file: