Infineon MOTIX™ MCU TLE988x/9x Device Family SDK
Macros
PosMask_peripherals

Detailed Description

Collaboration diagram for PosMask_peripherals:

Macros

#define ADC1_GLOBCONF_EN_Pos   (0UL)
 
#define ADC1_GLOBCONF_EN_Msk   (0x1UL)
 
#define ADC1_INP0_INP_CH0_Pos   (0UL)
 
#define ADC1_INP0_INP_CH0_Msk   (0x3UL)
 
#define ADC1_INP0_INP_CH1_Pos   (2UL)
 
#define ADC1_INP0_INP_CH1_Msk   (0xcUL)
 
#define ADC1_INP0_INP_CH2_Pos   (4UL)
 
#define ADC1_INP0_INP_CH2_Msk   (0x30UL)
 
#define ADC1_INP0_INP_CH3_Pos   (6UL)
 
#define ADC1_INP0_INP_CH3_Msk   (0xc0UL)
 
#define ADC1_INP0_INP_CH4_Pos   (8UL)
 
#define ADC1_INP0_INP_CH4_Msk   (0x300UL)
 
#define ADC1_INP0_INP_CH5_Pos   (10UL)
 
#define ADC1_INP0_INP_CH5_Msk   (0xc00UL)
 
#define ADC1_INP0_INP_CH6_Pos   (12UL)
 
#define ADC1_INP0_INP_CH6_Msk   (0x3000UL)
 
#define ADC1_INP0_INP_CH7_Pos   (14UL)
 
#define ADC1_INP0_INP_CH7_Msk   (0xc000UL)
 
#define ADC1_INP0_INP_CH8_Pos   (16UL)
 
#define ADC1_INP0_INP_CH8_Msk   (0x30000UL)
 
#define ADC1_INP0_INP_CH9_Pos   (18UL)
 
#define ADC1_INP0_INP_CH9_Msk   (0xc0000UL)
 
#define ADC1_INP0_INP_CH10_Pos   (20UL)
 
#define ADC1_INP0_INP_CH10_Msk   (0x300000UL)
 
#define ADC1_INP0_INP_CH11_Pos   (22UL)
 
#define ADC1_INP0_INP_CH11_Msk   (0xc00000UL)
 
#define ADC1_INP0_INP_CH12_Pos   (24UL)
 
#define ADC1_INP0_INP_CH12_Msk   (0x3000000UL)
 
#define ADC1_INP0_INP_CH13_Pos   (26UL)
 
#define ADC1_INP0_INP_CH13_Msk   (0xc000000UL)
 
#define ADC1_INP0_INP_CH14_Pos   (28UL)
 
#define ADC1_INP0_INP_CH14_Msk   (0x30000000UL)
 
#define ADC1_INP0_INP_CH15_Pos   (30UL)
 
#define ADC1_INP0_INP_CH15_Msk   (0xc0000000UL)
 
#define ADC1_INP1_INP_CH16_Pos   (0UL)
 
#define ADC1_INP1_INP_CH16_Msk   (0x3UL)
 
#define ADC1_INP1_INP_CH17_Pos   (2UL)
 
#define ADC1_INP1_INP_CH17_Msk   (0xcUL)
 
#define ADC1_INP1_INP_CH18_Pos   (4UL)
 
#define ADC1_INP1_INP_CH18_Msk   (0x30UL)
 
#define ADC1_INP1_INP_CH19_Pos   (6UL)
 
#define ADC1_INP1_INP_CH19_Msk   (0xc0UL)
 
#define ADC1_INP1_INP_EOC_FAIL_Pos   (8UL)
 
#define ADC1_INP1_INP_EOC_FAIL_Msk   (0x300UL)
 
#define ADC1_INP2_INP_CMP_LO0_Pos   (0UL)
 
#define ADC1_INP2_INP_CMP_LO0_Msk   (0x3UL)
 
#define ADC1_INP2_INP_CMP_LO1_Pos   (2UL)
 
#define ADC1_INP2_INP_CMP_LO1_Msk   (0xcUL)
 
#define ADC1_INP2_INP_CMP_LO2_Pos   (4UL)
 
#define ADC1_INP2_INP_CMP_LO2_Msk   (0x30UL)
 
#define ADC1_INP2_INP_CMP_LO3_Pos   (6UL)
 
#define ADC1_INP2_INP_CMP_LO3_Msk   (0xc0UL)
 
#define ADC1_INP2_INP_CMP_UP0_Pos   (8UL)
 
#define ADC1_INP2_INP_CMP_UP0_Msk   (0x300UL)
 
#define ADC1_INP2_INP_CMP_UP1_Pos   (10UL)
 
#define ADC1_INP2_INP_CMP_UP1_Msk   (0xc00UL)
 
#define ADC1_INP2_INP_CMP_UP2_Pos   (12UL)
 
#define ADC1_INP2_INP_CMP_UP2_Msk   (0x3000UL)
 
#define ADC1_INP2_INP_CMP_UP3_Pos   (14UL)
 
#define ADC1_INP2_INP_CMP_UP3_Msk   (0xc000UL)
 
#define ADC1_INP3_INP_SQ0_Pos   (0UL)
 
#define ADC1_INP3_INP_SQ0_Msk   (0x3UL)
 
#define ADC1_INP3_INP_SQ1_Pos   (2UL)
 
#define ADC1_INP3_INP_SQ1_Msk   (0xcUL)
 
#define ADC1_INP3_INP_SQ2_Pos   (4UL)
 
#define ADC1_INP3_INP_SQ2_Msk   (0x30UL)
 
#define ADC1_INP3_INP_SQ3_Pos   (6UL)
 
#define ADC1_INP3_INP_SQ3_Msk   (0xc0UL)
 
#define ADC1_INP3_INP_COLL0_Pos   (8UL)
 
#define ADC1_INP3_INP_COLL0_Msk   (0x300UL)
 
#define ADC1_INP3_INP_COLL1_Pos   (10UL)
 
#define ADC1_INP3_INP_COLL1_Msk   (0xc00UL)
 
#define ADC1_INP3_INP_COLL2_Pos   (12UL)
 
#define ADC1_INP3_INP_COLL2_Msk   (0x3000UL)
 
#define ADC1_INP3_INP_COLL3_Pos   (14UL)
 
#define ADC1_INP3_INP_COLL3_Msk   (0xc000UL)
 
#define ADC1_INP3_INP_WFR0_Pos   (16UL)
 
#define ADC1_INP3_INP_WFR0_Msk   (0x30000UL)
 
#define ADC1_INP3_INP_WFR1_Pos   (18UL)
 
#define ADC1_INP3_INP_WFR1_Msk   (0xc0000UL)
 
#define ADC1_INP3_INP_WFR2_Pos   (20UL)
 
#define ADC1_INP3_INP_WFR2_Msk   (0x300000UL)
 
#define ADC1_INP3_INP_WFR3_Pos   (22UL)
 
#define ADC1_INP3_INP_WFR3_Msk   (0xc00000UL)
 
#define ADC2_GLOBCONF_EN_Pos   (0UL)
 
#define ADC2_GLOBCONF_EN_Msk   (0x1UL)
 
#define ADC2_INP0_INP_CH0_Pos   (0UL)
 
#define ADC2_INP0_INP_CH0_Msk   (0x3UL)
 
#define ADC2_INP0_INP_CH1_Pos   (2UL)
 
#define ADC2_INP0_INP_CH1_Msk   (0xcUL)
 
#define ADC2_INP0_INP_CH2_Pos   (4UL)
 
#define ADC2_INP0_INP_CH2_Msk   (0x30UL)
 
#define ADC2_INP0_INP_CH3_Pos   (6UL)
 
#define ADC2_INP0_INP_CH3_Msk   (0xc0UL)
 
#define ADC2_INP0_INP_CH4_Pos   (8UL)
 
#define ADC2_INP0_INP_CH4_Msk   (0x300UL)
 
#define ADC2_INP0_INP_CH5_Pos   (10UL)
 
#define ADC2_INP0_INP_CH5_Msk   (0xc00UL)
 
#define ADC2_INP0_INP_CH6_Pos   (12UL)
 
#define ADC2_INP0_INP_CH6_Msk   (0x3000UL)
 
#define ADC2_INP0_INP_CH7_Pos   (14UL)
 
#define ADC2_INP0_INP_CH7_Msk   (0xc000UL)
 
#define ADC2_INP0_INP_CH8_Pos   (16UL)
 
#define ADC2_INP0_INP_CH8_Msk   (0x30000UL)
 
#define ADC2_INP0_INP_CH9_Pos   (18UL)
 
#define ADC2_INP0_INP_CH9_Msk   (0xc0000UL)
 
#define ADC2_INP0_INP_CH10_Pos   (20UL)
 
#define ADC2_INP0_INP_CH10_Msk   (0x300000UL)
 
#define ADC2_INP0_INP_CH11_Pos   (22UL)
 
#define ADC2_INP0_INP_CH11_Msk   (0xc00000UL)
 
#define ADC2_INP0_INP_CH12_Pos   (24UL)
 
#define ADC2_INP0_INP_CH12_Msk   (0x3000000UL)
 
#define ADC2_INP0_INP_CH13_Pos   (26UL)
 
#define ADC2_INP0_INP_CH13_Msk   (0xc000000UL)
 
#define ADC2_INP0_INP_CH14_Pos   (28UL)
 
#define ADC2_INP0_INP_CH14_Msk   (0x30000000UL)
 
#define ADC2_INP0_INP_EOC_FAIL_Pos   (30UL)
 
#define ADC2_INP0_INP_EOC_FAIL_Msk   (0xc0000000UL)
 
#define ADC2_INP2_INP_CMP_LO0_Pos   (0UL)
 
#define ADC2_INP2_INP_CMP_LO0_Msk   (0x3UL)
 
#define ADC2_INP2_INP_CMP_LO1_Pos   (2UL)
 
#define ADC2_INP2_INP_CMP_LO1_Msk   (0xcUL)
 
#define ADC2_INP2_INP_CMP_LO2_Pos   (4UL)
 
#define ADC2_INP2_INP_CMP_LO2_Msk   (0x30UL)
 
#define ADC2_INP2_INP_CMP_LO3_Pos   (6UL)
 
#define ADC2_INP2_INP_CMP_LO3_Msk   (0xc0UL)
 
#define ADC2_INP2_INP_CMP_LO4_Pos   (8UL)
 
#define ADC2_INP2_INP_CMP_LO4_Msk   (0x300UL)
 
#define ADC2_INP2_INP_CMP_LO5_Pos   (10UL)
 
#define ADC2_INP2_INP_CMP_LO5_Msk   (0xc00UL)
 
#define ADC2_INP2_INP_CMP_LO6_Pos   (12UL)
 
#define ADC2_INP2_INP_CMP_LO6_Msk   (0x3000UL)
 
#define ADC2_INP2_INP_CMP_LO7_Pos   (14UL)
 
#define ADC2_INP2_INP_CMP_LO7_Msk   (0xc000UL)
 
#define ADC2_INP2_INP_CMP_UP0_Pos   (16UL)
 
#define ADC2_INP2_INP_CMP_UP0_Msk   (0x30000UL)
 
#define ADC2_INP2_INP_CMP_UP1_Pos   (18UL)
 
#define ADC2_INP2_INP_CMP_UP1_Msk   (0xc0000UL)
 
#define ADC2_INP2_INP_CMP_UP2_Pos   (20UL)
 
#define ADC2_INP2_INP_CMP_UP2_Msk   (0x300000UL)
 
#define ADC2_INP2_INP_CMP_UP3_Pos   (22UL)
 
#define ADC2_INP2_INP_CMP_UP3_Msk   (0xc00000UL)
 
#define ADC2_INP2_INP_CMP_UP4_Pos   (24UL)
 
#define ADC2_INP2_INP_CMP_UP4_Msk   (0x3000000UL)
 
#define ADC2_INP2_INP_CMP_UP5_Pos   (26UL)
 
#define ADC2_INP2_INP_CMP_UP5_Msk   (0xc000000UL)
 
#define ADC2_INP2_INP_CMP_UP6_Pos   (28UL)
 
#define ADC2_INP2_INP_CMP_UP6_Msk   (0x30000000UL)
 
#define ADC2_INP2_INP_CMP_UP7_Pos   (30UL)
 
#define ADC2_INP2_INP_CMP_UP7_Msk   (0xc0000000UL)
 
#define ADC2_INP3_INP_SQ0_Pos   (0UL)
 
#define ADC2_INP3_INP_SQ0_Msk   (0x3UL)
 
#define ADC2_INP3_INP_SQ1_Pos   (2UL)
 
#define ADC2_INP3_INP_SQ1_Msk   (0xcUL)
 
#define ADC2_INP3_INP_SQ2_Pos   (4UL)
 
#define ADC2_INP3_INP_SQ2_Msk   (0x30UL)
 
#define ADC2_INP3_INP_SQ3_Pos   (6UL)
 
#define ADC2_INP3_INP_SQ3_Msk   (0xc0UL)
 
#define ADC2_INP3_INP_COLL0_Pos   (8UL)
 
#define ADC2_INP3_INP_COLL0_Msk   (0x300UL)
 
#define ADC2_INP3_INP_COLL1_Pos   (10UL)
 
#define ADC2_INP3_INP_COLL1_Msk   (0xc00UL)
 
#define ADC2_INP3_INP_COLL2_Pos   (12UL)
 
#define ADC2_INP3_INP_COLL2_Msk   (0x3000UL)
 
#define ADC2_INP3_INP_COLL3_Pos   (14UL)
 
#define ADC2_INP3_INP_COLL3_Msk   (0xc000UL)
 
#define BDRV_CP_CTRL_CP_RDY_EN_Pos   (2UL)
 
#define BDRV_CP_CTRL_CP_RDY_EN_Msk   (0x4UL)
 
#define BDRV_CP_CTRL_CP_1STAGE_Pos   (16UL)
 
#define BDRV_CP_CTRL_CP_1STAGE_Msk   (0x10000UL)
 
#define CANNODE_CAN_NIPR0_ALINP_Pos   (0UL)
 
#define CANNODE_CAN_NIPR0_ALINP_Msk   (0xfUL)
 
#define CANNODE_CAN_NIPR0_LECINP_Pos   (4UL)
 
#define CANNODE_CAN_NIPR0_LECINP_Msk   (0xf0UL)
 
#define CANNODE_CAN_NIPR0_TRINP_Pos   (8UL)
 
#define CANNODE_CAN_NIPR0_TRINP_Msk   (0xf00UL)
 
#define CANNODE_CAN_NIPR0_CFCINP_Pos   (12UL)
 
#define CANNODE_CAN_NIPR0_CFCINP_Msk   (0xf000UL)
 
#define CANTRX_CTRL_EN_Pos   (0UL)
 
#define CANTRX_CTRL_EN_Msk   (0x1UL)
 
#define CCU7_CMPSTAT_CCPOS0_Pos   (3UL)
 
#define CCU7_CMPSTAT_CCPOS0_Msk   (0x8UL)
 
#define CCU7_CMPSTAT_CCPOS1_Pos   (4UL)
 
#define CCU7_CMPSTAT_CCPOS1_Msk   (0x10UL)
 
#define CCU7_CMPSTAT_CCPOS2_Pos   (5UL)
 
#define CCU7_CMPSTAT_CCPOS2_Msk   (0x20UL)
 
#define CCU7_INP_INPCC70_Pos   (0UL)
 
#define CCU7_INP_INPCC70_Msk   (0x3UL)
 
#define CCU7_INP_INPCC71_Pos   (2UL)
 
#define CCU7_INP_INPCC71_Msk   (0xcUL)
 
#define CCU7_INP_INPCC72_Pos   (4UL)
 
#define CCU7_INP_INPCC72_Msk   (0x30UL)
 
#define CCU7_INP_INPCHE_Pos   (6UL)
 
#define CCU7_INP_INPCHE_Msk   (0xc0UL)
 
#define CCU7_INP_INPERR_Pos   (8UL)
 
#define CCU7_INP_INPERR_Msk   (0x300UL)
 
#define CCU7_INP_INPT12_Pos   (10UL)
 
#define CCU7_INP_INPT12_Msk   (0xc00UL)
 
#define CCU7_INP_INPT13_Pos   (12UL)
 
#define CCU7_INP_INPT13_Msk   (0x3000UL)
 
#define CCU7_INP_2_INPCC70B_Pos   (0UL)
 
#define CCU7_INP_2_INPCC70B_Msk   (0x3UL)
 
#define CCU7_INP_2_INPCC71B_Pos   (2UL)
 
#define CCU7_INP_2_INPCC71B_Msk   (0xcUL)
 
#define CCU7_INP_2_INPCC72B_Pos   (4UL)
 
#define CCU7_INP_2_INPCC72B_Msk   (0x30UL)
 
#define CCU7_INP_2_INPT14_Pos   (8UL)
 
#define CCU7_INP_2_INPT14_Msk   (0x300UL)
 
#define CCU7_INP_2_INPT15_Pos   (10UL)
 
#define CCU7_INP_2_INPT15_Msk   (0xc00UL)
 
#define CCU7_INP_2_INPT16_Pos   (12UL)
 
#define CCU7_INP_2_INPT16_Msk   (0x3000UL)
 
#define CCU7_LI_INPLBE_Pos   (14UL)
 
#define CCU7_LI_INPLBE_Msk   (0xc000UL)
 
#define CPU_NVIC_ISER_IRQEN0_Pos   (0UL)
 
#define CPU_NVIC_ISER_IRQEN0_Msk   (0x1UL)
 
#define CPU_NVIC_ISER_IRQEN1_Pos   (1UL)
 
#define CPU_NVIC_ISER_IRQEN1_Msk   (0x2UL)
 
#define CPU_NVIC_ISER_IRQEN2_Pos   (2UL)
 
#define CPU_NVIC_ISER_IRQEN2_Msk   (0x4UL)
 
#define CPU_NVIC_ISER_IRQEN3_Pos   (3UL)
 
#define CPU_NVIC_ISER_IRQEN3_Msk   (0x8UL)
 
#define CPU_NVIC_ISER_IRQEN4_Pos   (4UL)
 
#define CPU_NVIC_ISER_IRQEN4_Msk   (0x10UL)
 
#define CPU_NVIC_ISER_IRQEN5_Pos   (5UL)
 
#define CPU_NVIC_ISER_IRQEN5_Msk   (0x20UL)
 
#define CPU_NVIC_ISER_IRQEN6_Pos   (6UL)
 
#define CPU_NVIC_ISER_IRQEN6_Msk   (0x40UL)
 
#define CPU_NVIC_ISER_IRQEN7_Pos   (7UL)
 
#define CPU_NVIC_ISER_IRQEN7_Msk   (0x80UL)
 
#define CPU_NVIC_ISER_IRQEN8_Pos   (8UL)
 
#define CPU_NVIC_ISER_IRQEN8_Msk   (0x100UL)
 
#define CPU_NVIC_ISER_IRQEN9_Pos   (9UL)
 
#define CPU_NVIC_ISER_IRQEN9_Msk   (0x200UL)
 
#define CPU_NVIC_ISER_IRQEN10_Pos   (10UL)
 
#define CPU_NVIC_ISER_IRQEN10_Msk   (0x400UL)
 
#define CPU_NVIC_ISER_IRQEN11_Pos   (11UL)
 
#define CPU_NVIC_ISER_IRQEN11_Msk   (0x800UL)
 
#define CPU_NVIC_ISER_IRQEN12_Pos   (12UL)
 
#define CPU_NVIC_ISER_IRQEN12_Msk   (0x1000UL)
 
#define CPU_NVIC_ISER_IRQEN13_Pos   (13UL)
 
#define CPU_NVIC_ISER_IRQEN13_Msk   (0x2000UL)
 
#define CPU_NVIC_ISER_IRQEN14_Pos   (14UL)
 
#define CPU_NVIC_ISER_IRQEN14_Msk   (0x4000UL)
 
#define CPU_NVIC_ISER_IRQEN15_Pos   (15UL)
 
#define CPU_NVIC_ISER_IRQEN15_Msk   (0x8000UL)
 
#define CPU_NVIC_ISER_IRQEN16_Pos   (16UL)
 
#define CPU_NVIC_ISER_IRQEN16_Msk   (0x10000UL)
 
#define CPU_NVIC_ISER_IRQEN17_Pos   (17UL)
 
#define CPU_NVIC_ISER_IRQEN17_Msk   (0x20000UL)
 
#define CPU_NVIC_ISER_IRQEN18_Pos   (18UL)
 
#define CPU_NVIC_ISER_IRQEN18_Msk   (0x40000UL)
 
#define CPU_NVIC_ISER_IRQEN19_Pos   (19UL)
 
#define CPU_NVIC_ISER_IRQEN19_Msk   (0x80000UL)
 
#define CPU_NVIC_ISER_IRQEN20_Pos   (20UL)
 
#define CPU_NVIC_ISER_IRQEN20_Msk   (0x100000UL)
 
#define CPU_NVIC_ISER_IRQEN21_Pos   (21UL)
 
#define CPU_NVIC_ISER_IRQEN21_Msk   (0x200000UL)
 
#define CPU_NVIC_ISER_IRQEN22_Pos   (22UL)
 
#define CPU_NVIC_ISER_IRQEN22_Msk   (0x400000UL)
 
#define CPU_NVIC_ISER_IRQEN23_Pos   (23UL)
 
#define CPU_NVIC_ISER_IRQEN23_Msk   (0x800000UL)
 
#define CPU_NVIC_ISER_IRQEN24_Pos   (24UL)
 
#define CPU_NVIC_ISER_IRQEN24_Msk   (0x1000000UL)
 
#define CPU_NVIC_ISER_IRQEN25_Pos   (25UL)
 
#define CPU_NVIC_ISER_IRQEN25_Msk   (0x2000000UL)
 
#define CPU_NVIC_ISER_IRQEN26_Pos   (26UL)
 
#define CPU_NVIC_ISER_IRQEN26_Msk   (0x4000000UL)
 
#define CPU_NVIC_ISER_IRQEN27_Pos   (27UL)
 
#define CPU_NVIC_ISER_IRQEN27_Msk   (0x8000000UL)
 
#define CPU_NVIC_ISER_IRQEN28_Pos   (28UL)
 
#define CPU_NVIC_ISER_IRQEN28_Msk   (0x10000000UL)
 
#define CPU_NVIC_ISER_IRQEN29_Pos   (29UL)
 
#define CPU_NVIC_ISER_IRQEN29_Msk   (0x20000000UL)
 
#define CPU_NVIC_ISER_IRQEN30_Pos   (30UL)
 
#define CPU_NVIC_ISER_IRQEN30_Msk   (0x40000000UL)
 
#define CPU_NVIC_ISER_IRQEN31_Pos   (31UL)
 
#define CPU_NVIC_ISER_IRQEN31_Msk   (0x80000000UL)
 
#define CSACSC_CTRL1_CSAC_EN_Pos   (0UL)
 
#define CSACSC_CTRL1_CSAC_EN_Msk   (0x1UL)
 
#define GPIO_P0_OMR_PS0_Pos   (0UL)
 
#define GPIO_P0_OMR_PS0_Msk   (0x1UL)
 
#define GPIO_P0_OMR_PS1_Pos   (1UL)
 
#define GPIO_P0_OMR_PS1_Msk   (0x2UL)
 
#define GPIO_P0_OMR_PS2_Pos   (2UL)
 
#define GPIO_P0_OMR_PS2_Msk   (0x4UL)
 
#define GPIO_P0_OMR_PS3_Pos   (3UL)
 
#define GPIO_P0_OMR_PS3_Msk   (0x8UL)
 
#define GPIO_P0_OMR_PS4_Pos   (4UL)
 
#define GPIO_P0_OMR_PS4_Msk   (0x10UL)
 
#define GPIO_P0_OMR_PS5_Pos   (5UL)
 
#define GPIO_P0_OMR_PS5_Msk   (0x20UL)
 
#define GPIO_P0_OMR_PS6_Pos   (6UL)
 
#define GPIO_P0_OMR_PS6_Msk   (0x40UL)
 
#define GPIO_P0_OMR_PS7_Pos   (7UL)
 
#define GPIO_P0_OMR_PS7_Msk   (0x80UL)
 
#define GPIO_P0_OMR_PS8_Pos   (8UL)
 
#define GPIO_P0_OMR_PS8_Msk   (0x100UL)
 
#define GPIO_P0_OMR_PS9_Pos   (9UL)
 
#define GPIO_P0_OMR_PS9_Msk   (0x200UL)
 
#define GPIO_P0_OMR_PS10_Pos   (10UL)
 
#define GPIO_P0_OMR_PS10_Msk   (0x400UL)
 
#define GPIO_P1_OMR_PS0_Pos   (0UL)
 
#define GPIO_P1_OMR_PS0_Msk   (0x1UL)
 
#define GPIO_P1_OMR_PS1_Pos   (1UL)
 
#define GPIO_P1_OMR_PS1_Msk   (0x2UL)
 
#define GPIO_P1_OMR_PS2_Pos   (2UL)
 
#define GPIO_P1_OMR_PS2_Msk   (0x4UL)
 
#define GPIO_P1_OMR_PS3_Pos   (3UL)
 
#define GPIO_P1_OMR_PS3_Msk   (0x8UL)
 
#define GPIO_P1_OMR_PS4_Pos   (4UL)
 
#define GPIO_P1_OMR_PS4_Msk   (0x10UL)
 
#define PLL_CON0_PLLEN_Pos   (31UL)
 
#define PLL_CON0_PLLEN_Msk   (0x80000000UL)
 
#define PLL_CON1_PLLEN_Pos   (31UL)
 
#define PLL_CON1_PLLEN_Msk   (0x80000000UL)
 
#define PLL_SPCTR_SPEN0_Pos   (0UL)
 
#define PLL_SPCTR_SPEN0_Msk   (0x1UL)
 
#define PLL_SPCTR_SPEN1_Pos   (16UL)
 
#define PLL_SPCTR_SPEN1_Msk   (0x10000UL)
 
#define PLL_STATC_PLL0_LOL_STSCLR_Pos   (0UL)
 
#define PLL_STATC_PLL0_LOL_STSCLR_Msk   (0x1UL)
 
#define PLL_STATC_PLL1_LOL_STSCLR_Pos   (1UL)
 
#define PLL_STATC_PLL1_LOL_STSCLR_Msk   (0x2UL)
 
#define PMU_FS_SSD_CLR_SSD_STS_CLR_Pos   (0UL)
 
#define PMU_FS_SSD_CLR_SSD_STS_CLR_Msk   (0x1UL)
 
#define PMU_FS_SSD_CLR_FO_STS_CLR_Pos   (1UL)
 
#define PMU_FS_SSD_CLR_FO_STS_CLR_Msk   (0x2UL)
 
#define PMU_WD_CTRL_WDP_Pos   (16UL)
 
#define PMU_WD_CTRL_WDP_Msk   (0x3f0000UL)
 
#define PMU_WD_CTRL_SOW_Pos   (24UL)
 
#define PMU_WD_CTRL_SOW_Msk   (0x3000000UL)
 
#define PMU_WAKE_CTRL_CAN_WAKE_EN_Pos   (0UL)
 
#define PMU_WAKE_CTRL_CAN_WAKE_EN_Msk   (0x1UL)
 
#define PMU_WAKE_CTRL_MON1_WAKE_EN_Pos   (12UL)
 
#define PMU_WAKE_CTRL_MON1_WAKE_EN_Msk   (0x1000UL)
 
#define PMU_WAKE_CTRL_MON2_WAKE_EN_Pos   (13UL)
 
#define PMU_WAKE_CTRL_MON2_WAKE_EN_Msk   (0x2000UL)
 
#define PMU_WAKE_CTRL_MON3_WAKE_EN_Pos   (14UL)
 
#define PMU_WAKE_CTRL_MON3_WAKE_EN_Msk   (0x4000UL)
 
#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Pos   (4UL)
 
#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk   (0x10UL)
 
#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Pos   (5UL)
 
#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk   (0x20UL)
 
#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Pos   (6UL)
 
#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk   (0x40UL)
 
#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Pos   (7UL)
 
#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk   (0x80UL)
 
#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Pos   (8UL)
 
#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk   (0x100UL)
 
#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Pos   (9UL)
 
#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk   (0x200UL)
 
#define PMU_WAKE_CTRL_LIN_WAKE_EN_Pos   (1UL)
 
#define PMU_WAKE_CTRL_LIN_WAKE_EN_Msk   (0x2UL)
 
#define PMU_WAKE_CTRL_CYC_WAKE_EN_Pos   (2UL)
 
#define PMU_WAKE_CTRL_CYC_WAKE_EN_Msk   (0x4UL)
 
#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Pos   (16UL)
 
#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk   (0x10000UL)
 
#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Pos   (17UL)
 
#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk   (0x20000UL)
 
#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Pos   (18UL)
 
#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk   (0x40000UL)
 
#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Pos   (19UL)
 
#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk   (0x80000UL)
 
#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Pos   (20UL)
 
#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk   (0x100000UL)
 
#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Pos   (21UL)
 
#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk   (0x200000UL)
 
#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Pos   (22UL)
 
#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk   (0x400000UL)
 
#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Pos   (23UL)
 
#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk   (0x800000UL)
 
#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Pos   (24UL)
 
#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk   (0x1000000UL)
 
#define PMU_WAKE_CTRL_WAKE_W_RST_Pos   (28UL)
 
#define PMU_WAKE_CTRL_WAKE_W_RST_Msk   (0x10000000UL)
 
#define PMU_WAKE_CTRL_VDDC_RED_EN_Pos   (29UL)
 
#define PMU_WAKE_CTRL_VDDC_RED_EN_Msk   (0x20000000UL)
 
#define SCU_CLKSEL_CLKOUTEN_Pos   (19UL)
 
#define SCU_CLKSEL_CLKOUTEN_Msk   (0x80000UL)
 
#define SCU_INP0_INP_PMU_Pos   (0UL)
 
#define SCU_INP0_INP_PMU_Msk   (0x1UL)
 
#define SCU_INP0_INP_BDRV_IRQ0_Pos   (1UL)
 
#define SCU_INP0_INP_BDRV_IRQ0_Msk   (0x2UL)
 
#define SCU_INP0_INP_BDRV_IRQ1_Pos   (2UL)
 
#define SCU_INP0_INP_BDRV_IRQ1_Msk   (0x4UL)
 
#define SCU_INP0_INP_CANTX_Pos   (3UL)
 
#define SCU_INP0_INP_CANTX_Msk   (0x8UL)
 
#define SCU_INP0_INP_ARVG_Pos   (4UL)
 
#define SCU_INP0_INP_ARVG_Msk   (0x10UL)
 
#define SCU_INP0_INP_CSC_Pos   (5UL)
 
#define SCU_INP0_INP_CSC_Msk   (0x20UL)
 
#define SCU_INP1_INP_GPT1T2_Pos   (0UL)
 
#define SCU_INP1_INP_GPT1T2_Msk   (0x1UL)
 
#define SCU_INP1_INP_GPT1T3_Pos   (1UL)
 
#define SCU_INP1_INP_GPT1T3_Msk   (0x2UL)
 
#define SCU_INP1_INP_GPT1T4_Pos   (2UL)
 
#define SCU_INP1_INP_GPT1T4_Msk   (0x4UL)
 
#define SCU_INP1_INP_GPT2T5_Pos   (3UL)
 
#define SCU_INP1_INP_GPT2T5_Msk   (0x8UL)
 
#define SCU_INP1_INP_GPT2T6_Pos   (4UL)
 
#define SCU_INP1_INP_GPT2T6_Msk   (0x10UL)
 
#define SCU_INP1_INP_GPT2CR_Pos   (5UL)
 
#define SCU_INP1_INP_GPT2CR_Msk   (0x20UL)
 
#define SCU_INP2_INP_MON1_Pos   (0UL)
 
#define SCU_INP2_INP_MON1_Msk   (0x1UL)
 
#define SCU_INP2_INP_MON2_Pos   (1UL)
 
#define SCU_INP2_INP_MON2_Msk   (0x2UL)
 
#define SCU_INP2_INP_MON3_Pos   (2UL)
 
#define SCU_INP2_INP_MON3_Msk   (0x4UL)
 
#define SCU_INP3_INP_SDADC0_Pos   (0UL)
 
#define SCU_INP3_INP_SDADC0_Msk   (0x1UL)
 
#define SCU_INP3_INP_SDADC1_Pos   (1UL)
 
#define SCU_INP3_INP_SDADC1_Msk   (0x2UL)
 
#define SCU_INP3_INP_BEMF0_Pos   (2UL)
 
#define SCU_INP3_INP_BEMF0_Msk   (0x4UL)
 
#define SCU_INP3_INP_BEMF1_Pos   (3UL)
 
#define SCU_INP3_INP_BEMF1_Msk   (0x8UL)
 
#define SCU_INP3_INP_BEMF2_Pos   (4UL)
 
#define SCU_INP3_INP_BEMF2_Msk   (0x10UL)
 
#define SCU_INP4_INP_EXINT0_Pos   (0UL)
 
#define SCU_INP4_INP_EXINT0_Msk   (0x1UL)
 
#define SCU_INP4_INP_EXINT1_Pos   (1UL)
 
#define SCU_INP4_INP_EXINT1_Msk   (0x2UL)
 
#define SCU_INP4_INP_EXINT2_Pos   (2UL)
 
#define SCU_INP4_INP_EXINT2_Msk   (0x4UL)
 
#define SCU_INP4_INP_EXINT3_Pos   (3UL)
 
#define SCU_INP4_INP_EXINT3_Msk   (0x8UL)
 
#define SCU_INP5_INP_LIN0_EOFSYN_Pos   (0UL)
 
#define SCU_INP5_INP_LIN0_EOFSYN_Msk   (0x1UL)
 
#define SCU_INP5_INP_LIN0_ERRSYN_Pos   (1UL)
 
#define SCU_INP5_INP_LIN0_ERRSYN_Msk   (0x2UL)
 
#define SCU_INP5_INP_LIN1_EOFSYN_Pos   (2UL)
 
#define SCU_INP5_INP_LIN1_EOFSYN_Msk   (0x4UL)
 
#define SCU_INP5_INP_LIN1_ERRSYN_Pos   (3UL)
 
#define SCU_INP5_INP_LIN1_ERRSYN_Msk   (0x8UL)
 
#define SCU_INP5_INP_UART0_RI_Pos   (4UL)
 
#define SCU_INP5_INP_UART0_RI_Msk   (0x10UL)
 
#define SCU_INP5_INP_UART0_TI_Pos   (5UL)
 
#define SCU_INP5_INP_UART0_TI_Msk   (0x20UL)
 
#define SCU_INP5_INP_UART1_RI_Pos   (6UL)
 
#define SCU_INP5_INP_UART1_RI_Msk   (0x40UL)
 
#define SCU_INP5_INP_UART1_TI_Pos   (7UL)
 
#define SCU_INP5_INP_UART1_TI_Msk   (0x80UL)
 
#define SCU_INP6_INP_SSC0_RIR_Pos   (0UL)
 
#define SCU_INP6_INP_SSC0_RIR_Msk   (0x1UL)
 
#define SCU_INP6_INP_SSC0_TIR_Pos   (1UL)
 
#define SCU_INP6_INP_SSC0_TIR_Msk   (0x2UL)
 
#define SCU_INP6_INP_SSC0_EIR_Pos   (2UL)
 
#define SCU_INP6_INP_SSC0_EIR_Msk   (0x4UL)
 
#define SCU_INP6_INP_SSC1_RIR_Pos   (4UL)
 
#define SCU_INP6_INP_SSC1_RIR_Msk   (0x10UL)
 
#define SCU_INP6_INP_SSC1_TIR_Pos   (5UL)
 
#define SCU_INP6_INP_SSC1_TIR_Msk   (0x20UL)
 
#define SCU_INP6_INP_SSC1_EIR_Pos   (6UL)
 
#define SCU_INP6_INP_SSC1_EIR_Msk   (0x40UL)
 
#define SCU_INP7_INP_DMACH0_Pos   (0UL)
 
#define SCU_INP7_INP_DMACH0_Msk   (0x1UL)
 
#define SCU_INP7_INP_DMACH1_Pos   (1UL)
 
#define SCU_INP7_INP_DMACH1_Msk   (0x2UL)
 
#define SCU_INP7_INP_DMACH2_Pos   (2UL)
 
#define SCU_INP7_INP_DMACH2_Msk   (0x4UL)
 
#define SCU_INP7_INP_DMACH3_Pos   (3UL)
 
#define SCU_INP7_INP_DMACH3_Msk   (0x8UL)
 
#define SCU_INP7_INP_DMACH4_Pos   (4UL)
 
#define SCU_INP7_INP_DMACH4_Msk   (0x10UL)
 
#define SCU_INP7_INP_DMACH5_Pos   (5UL)
 
#define SCU_INP7_INP_DMACH5_Msk   (0x20UL)
 
#define SCU_INP7_INP_DMACH6_Pos   (6UL)
 
#define SCU_INP7_INP_DMACH6_Msk   (0x40UL)
 
#define SCU_INP7_INP_DMACH7_Pos   (7UL)
 
#define SCU_INP7_INP_DMACH7_Msk   (0x80UL)
 
#define SCU_INP7_INP_DMATRERR_Pos   (8UL)
 
#define SCU_INP7_INP_DMATRERR_Msk   (0x100UL)
 
#define SCU_NMISRC_NMIXTALCLR_Pos   (0UL)
 
#define SCU_NMISRC_NMIXTALCLR_Msk   (0x1UL)
 
#define SCU_NMISRC_NMIPLL0CLR_Pos   (1UL)
 
#define SCU_NMISRC_NMIPLL0CLR_Msk   (0x2UL)
 
#define SCU_NMISRC_NMIPLL1CLR_Pos   (2UL)
 
#define SCU_NMISRC_NMIPLL1CLR_Msk   (0x4UL)
 
#define SCU_PMCON_SSC0_DIS_Pos   (0UL)
 
#define SCU_PMCON_SSC0_DIS_Msk   (0x1UL)
 
#define SCU_PMCON_SSC1_DIS_Pos   (1UL)
 
#define SCU_PMCON_SSC1_DIS_Msk   (0x2UL)
 
#define SCU_PMCON_T2_DIS_Pos   (2UL)
 
#define SCU_PMCON_T2_DIS_Msk   (0x4UL)
 
#define SCU_PMCON_T21_DIS_Pos   (3UL)
 
#define SCU_PMCON_T21_DIS_Msk   (0x8UL)
 
#define SCU_PMCON_GPT12_DIS_Pos   (4UL)
 
#define SCU_PMCON_GPT12_DIS_Msk   (0x10UL)
 
#define SCU_XTALCON_XPD_Pos   (0UL)
 
#define SCU_XTALCON_XPD_Msk   (0x1UL)
 
#define SCU_XTALCON_XTALSHBYEN_Pos   (2UL)
 
#define SCU_XTALCON_XTALSHBYEN_Msk   (0x4UL)
 
#define SCU_XTALCON_XTALSHDIS_Pos   (3UL)
 
#define SCU_XTALCON_XTALSHDIS_Msk   (0x8UL)
 
#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Pos   (0UL)
 
#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Msk   (0x1UL)
 
#define UART0_BCON_BR_R_Pos   (0UL)
 
#define UART0_BCON_BR_R_Msk   (0x1UL)
 
#define UART0_SCON_SM1_Pos   (1UL)
 
#define UART0_SCON_SM1_Msk   (0x2UL)
 
#define UART1_BCON_BR_R_Pos   (0UL)
 
#define UART1_BCON_BR_R_Msk   (0x1UL)
 
#define UART1_SCON_SM1_Pos   (1UL)
 
#define UART1_SCON_SM1_Msk   (0x2UL)
 
#define ADC1_GLOBCONF_EN_Pos   (0UL)
 
#define ADC1_GLOBCONF_EN_Msk   (0x1UL)
 
#define ADC1_INP0_INP_CH0_Pos   (0UL)
 
#define ADC1_INP0_INP_CH0_Msk   (0x3UL)
 
#define ADC1_INP0_INP_CH1_Pos   (2UL)
 
#define ADC1_INP0_INP_CH1_Msk   (0xcUL)
 
#define ADC1_INP0_INP_CH2_Pos   (4UL)
 
#define ADC1_INP0_INP_CH2_Msk   (0x30UL)
 
#define ADC1_INP0_INP_CH3_Pos   (6UL)
 
#define ADC1_INP0_INP_CH3_Msk   (0xc0UL)
 
#define ADC1_INP0_INP_CH4_Pos   (8UL)
 
#define ADC1_INP0_INP_CH4_Msk   (0x300UL)
 
#define ADC1_INP0_INP_CH5_Pos   (10UL)
 
#define ADC1_INP0_INP_CH5_Msk   (0xc00UL)
 
#define ADC1_INP0_INP_CH6_Pos   (12UL)
 
#define ADC1_INP0_INP_CH6_Msk   (0x3000UL)
 
#define ADC1_INP0_INP_CH7_Pos   (14UL)
 
#define ADC1_INP0_INP_CH7_Msk   (0xc000UL)
 
#define ADC1_INP0_INP_CH8_Pos   (16UL)
 
#define ADC1_INP0_INP_CH8_Msk   (0x30000UL)
 
#define ADC1_INP0_INP_CH9_Pos   (18UL)
 
#define ADC1_INP0_INP_CH9_Msk   (0xc0000UL)
 
#define ADC1_INP0_INP_CH10_Pos   (20UL)
 
#define ADC1_INP0_INP_CH10_Msk   (0x300000UL)
 
#define ADC1_INP0_INP_CH11_Pos   (22UL)
 
#define ADC1_INP0_INP_CH11_Msk   (0xc00000UL)
 
#define ADC1_INP0_INP_CH12_Pos   (24UL)
 
#define ADC1_INP0_INP_CH12_Msk   (0x3000000UL)
 
#define ADC1_INP0_INP_CH13_Pos   (26UL)
 
#define ADC1_INP0_INP_CH13_Msk   (0xc000000UL)
 
#define ADC1_INP0_INP_CH14_Pos   (28UL)
 
#define ADC1_INP0_INP_CH14_Msk   (0x30000000UL)
 
#define ADC1_INP0_INP_CH15_Pos   (30UL)
 
#define ADC1_INP0_INP_CH15_Msk   (0xc0000000UL)
 
#define ADC1_INP1_INP_CH16_Pos   (0UL)
 
#define ADC1_INP1_INP_CH16_Msk   (0x3UL)
 
#define ADC1_INP1_INP_CH17_Pos   (2UL)
 
#define ADC1_INP1_INP_CH17_Msk   (0xcUL)
 
#define ADC1_INP1_INP_CH18_Pos   (4UL)
 
#define ADC1_INP1_INP_CH18_Msk   (0x30UL)
 
#define ADC1_INP1_INP_CH19_Pos   (6UL)
 
#define ADC1_INP1_INP_CH19_Msk   (0xc0UL)
 
#define ADC1_INP2_INP_CMP_LO0_Pos   (0UL)
 
#define ADC1_INP2_INP_CMP_LO0_Msk   (0x3UL)
 
#define ADC1_INP2_INP_CMP_LO1_Pos   (2UL)
 
#define ADC1_INP2_INP_CMP_LO1_Msk   (0xcUL)
 
#define ADC1_INP2_INP_CMP_LO2_Pos   (4UL)
 
#define ADC1_INP2_INP_CMP_LO2_Msk   (0x30UL)
 
#define ADC1_INP2_INP_CMP_LO3_Pos   (6UL)
 
#define ADC1_INP2_INP_CMP_LO3_Msk   (0xc0UL)
 
#define ADC1_INP2_INP_CMP_UP0_Pos   (8UL)
 
#define ADC1_INP2_INP_CMP_UP0_Msk   (0x300UL)
 
#define ADC1_INP2_INP_CMP_UP1_Pos   (10UL)
 
#define ADC1_INP2_INP_CMP_UP1_Msk   (0xc00UL)
 
#define ADC1_INP2_INP_CMP_UP2_Pos   (12UL)
 
#define ADC1_INP2_INP_CMP_UP2_Msk   (0x3000UL)
 
#define ADC1_INP2_INP_CMP_UP3_Pos   (14UL)
 
#define ADC1_INP2_INP_CMP_UP3_Msk   (0xc000UL)
 
#define ADC1_INP3_INP_SQ0_Pos   (0UL)
 
#define ADC1_INP3_INP_SQ0_Msk   (0x3UL)
 
#define ADC1_INP3_INP_SQ1_Pos   (2UL)
 
#define ADC1_INP3_INP_SQ1_Msk   (0xcUL)
 
#define ADC1_INP3_INP_SQ2_Pos   (4UL)
 
#define ADC1_INP3_INP_SQ2_Msk   (0x30UL)
 
#define ADC1_INP3_INP_SQ3_Pos   (6UL)
 
#define ADC1_INP3_INP_SQ3_Msk   (0xc0UL)
 
#define ADC1_INP3_INP_COLL0_Pos   (8UL)
 
#define ADC1_INP3_INP_COLL0_Msk   (0x300UL)
 
#define ADC1_INP3_INP_COLL1_Pos   (10UL)
 
#define ADC1_INP3_INP_COLL1_Msk   (0xc00UL)
 
#define ADC1_INP3_INP_COLL2_Pos   (12UL)
 
#define ADC1_INP3_INP_COLL2_Msk   (0x3000UL)
 
#define ADC1_INP3_INP_COLL3_Pos   (14UL)
 
#define ADC1_INP3_INP_COLL3_Msk   (0xc000UL)
 
#define ADC1_INP3_INP_WFR0_Pos   (16UL)
 
#define ADC1_INP3_INP_WFR0_Msk   (0x30000UL)
 
#define ADC1_INP3_INP_WFR1_Pos   (18UL)
 
#define ADC1_INP3_INP_WFR1_Msk   (0xc0000UL)
 
#define ADC1_INP3_INP_WFR2_Pos   (20UL)
 
#define ADC1_INP3_INP_WFR2_Msk   (0x300000UL)
 
#define ADC1_INP3_INP_WFR3_Pos   (22UL)
 
#define ADC1_INP3_INP_WFR3_Msk   (0xc00000UL)
 
#define ADC2_FILTCFG_COEF_A6_Pos   (24UL)
 
#define ADC2_FILTCFG_COEF_A6_Msk   (0x3000000UL)
 
#define ADC2_FILTCFG_COEF_A7_Pos   (28UL)
 
#define ADC2_FILTCFG_COEF_A7_Msk   (0x30000000UL)
 
#define ADC2_GLOBCONF_EN_Pos   (0UL)
 
#define ADC2_GLOBCONF_EN_Msk   (0x1UL)
 
#define ADC2_INP0_INP_CH0_Pos   (0UL)
 
#define ADC2_INP0_INP_CH0_Msk   (0x3UL)
 
#define ADC2_INP0_INP_CH1_Pos   (2UL)
 
#define ADC2_INP0_INP_CH1_Msk   (0xcUL)
 
#define ADC2_INP0_INP_CH2_Pos   (4UL)
 
#define ADC2_INP0_INP_CH2_Msk   (0x30UL)
 
#define ADC2_INP0_INP_CH3_Pos   (6UL)
 
#define ADC2_INP0_INP_CH3_Msk   (0xc0UL)
 
#define ADC2_INP0_INP_CH4_Pos   (8UL)
 
#define ADC2_INP0_INP_CH4_Msk   (0x300UL)
 
#define ADC2_INP0_INP_CH5_Pos   (10UL)
 
#define ADC2_INP0_INP_CH5_Msk   (0xc00UL)
 
#define ADC2_INP0_INP_CH6_Pos   (12UL)
 
#define ADC2_INP0_INP_CH6_Msk   (0x3000UL)
 
#define ADC2_INP0_INP_CH7_Pos   (14UL)
 
#define ADC2_INP0_INP_CH7_Msk   (0xc000UL)
 
#define ADC2_INP0_INP_CH8_Pos   (16UL)
 
#define ADC2_INP0_INP_CH8_Msk   (0x30000UL)
 
#define ADC2_INP0_INP_CH9_Pos   (18UL)
 
#define ADC2_INP0_INP_CH9_Msk   (0xc0000UL)
 
#define ADC2_INP0_INP_CH10_Pos   (20UL)
 
#define ADC2_INP0_INP_CH10_Msk   (0x300000UL)
 
#define ADC2_INP0_INP_CH11_Pos   (22UL)
 
#define ADC2_INP0_INP_CH11_Msk   (0xc00000UL)
 
#define ADC2_INP0_INP_CH12_Pos   (24UL)
 
#define ADC2_INP0_INP_CH12_Msk   (0x3000000UL)
 
#define ADC2_INP0_INP_CH13_Pos   (26UL)
 
#define ADC2_INP0_INP_CH13_Msk   (0xc000000UL)
 
#define ADC2_INP0_INP_CH14_Pos   (28UL)
 
#define ADC2_INP0_INP_CH14_Msk   (0x30000000UL)
 
#define ADC2_INP2_INP_CMP_LO0_Pos   (0UL)
 
#define ADC2_INP2_INP_CMP_LO0_Msk   (0x3UL)
 
#define ADC2_INP2_INP_CMP_LO1_Pos   (2UL)
 
#define ADC2_INP2_INP_CMP_LO1_Msk   (0xcUL)
 
#define ADC2_INP2_INP_CMP_LO2_Pos   (4UL)
 
#define ADC2_INP2_INP_CMP_LO2_Msk   (0x30UL)
 
#define ADC2_INP2_INP_CMP_LO3_Pos   (6UL)
 
#define ADC2_INP2_INP_CMP_LO3_Msk   (0xc0UL)
 
#define ADC2_INP2_INP_CMP_LO4_Pos   (8UL)
 
#define ADC2_INP2_INP_CMP_LO4_Msk   (0x300UL)
 
#define ADC2_INP2_INP_CMP_LO5_Pos   (10UL)
 
#define ADC2_INP2_INP_CMP_LO5_Msk   (0xc00UL)
 
#define ADC2_INP2_INP_CMP_LO6_Pos   (12UL)
 
#define ADC2_INP2_INP_CMP_LO6_Msk   (0x3000UL)
 
#define ADC2_INP2_INP_CMP_LO7_Pos   (14UL)
 
#define ADC2_INP2_INP_CMP_LO7_Msk   (0xc000UL)
 
#define ADC2_INP2_INP_CMP_UP0_Pos   (16UL)
 
#define ADC2_INP2_INP_CMP_UP0_Msk   (0x30000UL)
 
#define ADC2_INP2_INP_CMP_UP1_Pos   (18UL)
 
#define ADC2_INP2_INP_CMP_UP1_Msk   (0xc0000UL)
 
#define ADC2_INP2_INP_CMP_UP2_Pos   (20UL)
 
#define ADC2_INP2_INP_CMP_UP2_Msk   (0x300000UL)
 
#define ADC2_INP2_INP_CMP_UP3_Pos   (22UL)
 
#define ADC2_INP2_INP_CMP_UP3_Msk   (0xc00000UL)
 
#define ADC2_INP2_INP_CMP_UP4_Pos   (24UL)
 
#define ADC2_INP2_INP_CMP_UP4_Msk   (0x3000000UL)
 
#define ADC2_INP2_INP_CMP_UP5_Pos   (26UL)
 
#define ADC2_INP2_INP_CMP_UP5_Msk   (0xc000000UL)
 
#define ADC2_INP2_INP_CMP_UP6_Pos   (28UL)
 
#define ADC2_INP2_INP_CMP_UP6_Msk   (0x30000000UL)
 
#define ADC2_INP2_INP_CMP_UP7_Pos   (30UL)
 
#define ADC2_INP2_INP_CMP_UP7_Msk   (0xc0000000UL)
 
#define ADC2_INP3_INP_SQ0_Pos   (0UL)
 
#define ADC2_INP3_INP_SQ0_Msk   (0x3UL)
 
#define ADC2_INP3_INP_SQ1_Pos   (2UL)
 
#define ADC2_INP3_INP_SQ1_Msk   (0xcUL)
 
#define ADC2_INP3_INP_SQ2_Pos   (4UL)
 
#define ADC2_INP3_INP_SQ2_Msk   (0x30UL)
 
#define ADC2_INP3_INP_SQ3_Pos   (6UL)
 
#define ADC2_INP3_INP_SQ3_Msk   (0xc0UL)
 
#define ADC2_INP3_INP_COLL0_Pos   (8UL)
 
#define ADC2_INP3_INP_COLL0_Msk   (0x300UL)
 
#define ADC2_INP3_INP_COLL1_Pos   (10UL)
 
#define ADC2_INP3_INP_COLL1_Msk   (0xc00UL)
 
#define ADC2_INP3_INP_COLL2_Pos   (12UL)
 
#define ADC2_INP3_INP_COLL2_Msk   (0x3000UL)
 
#define ADC2_INP3_INP_COLL3_Pos   (14UL)
 
#define ADC2_INP3_INP_COLL3_Msk   (0xc000UL)
 
#define BDRV_CP_CTRL_CP_RDY_EN_Pos   (2UL)
 
#define BDRV_CP_CTRL_CP_RDY_EN_Msk   (0x4UL)
 
#define BDRV_CP_CTRL_CP_1STAGE_Pos   (16UL)
 
#define BDRV_CP_CTRL_CP_1STAGE_Msk   (0x10000UL)
 
#define CANNODE_CAN_NIPR0_ALINP_Pos   (0UL)
 
#define CANNODE_CAN_NIPR0_ALINP_Msk   (0xfUL)
 
#define CANNODE_CAN_NIPR0_LECINP_Pos   (4UL)
 
#define CANNODE_CAN_NIPR0_LECINP_Msk   (0xf0UL)
 
#define CANNODE_CAN_NIPR0_TRINP_Pos   (8UL)
 
#define CANNODE_CAN_NIPR0_TRINP_Msk   (0xf00UL)
 
#define CANNODE_CAN_NIPR0_CFCINP_Pos   (12UL)
 
#define CANNODE_CAN_NIPR0_CFCINP_Msk   (0xf000UL)
 
#define CANTRX_CTRL_EN_Pos   (0UL)
 
#define CANTRX_CTRL_EN_Msk   (0x1UL)
 
#define CCU7_CMPSTAT_CCPOS0_Pos   (3UL)
 
#define CCU7_CMPSTAT_CCPOS0_Msk   (0x8UL)
 
#define CCU7_CMPSTAT_CCPOS1_Pos   (4UL)
 
#define CCU7_CMPSTAT_CCPOS1_Msk   (0x10UL)
 
#define CCU7_CMPSTAT_CCPOS2_Pos   (5UL)
 
#define CCU7_CMPSTAT_CCPOS2_Msk   (0x20UL)
 
#define CCU7_INP_INPCC70_Pos   (0UL)
 
#define CCU7_INP_INPCC70_Msk   (0x3UL)
 
#define CCU7_INP_INPCC71_Pos   (2UL)
 
#define CCU7_INP_INPCC71_Msk   (0xcUL)
 
#define CCU7_INP_INPCC72_Pos   (4UL)
 
#define CCU7_INP_INPCC72_Msk   (0x30UL)
 
#define CCU7_INP_INPCHE_Pos   (6UL)
 
#define CCU7_INP_INPCHE_Msk   (0xc0UL)
 
#define CCU7_INP_INPERR_Pos   (8UL)
 
#define CCU7_INP_INPERR_Msk   (0x300UL)
 
#define CCU7_INP_INPT12_Pos   (10UL)
 
#define CCU7_INP_INPT12_Msk   (0xc00UL)
 
#define CCU7_INP_INPT13_Pos   (12UL)
 
#define CCU7_INP_INPT13_Msk   (0x3000UL)
 
#define CCU7_INP_2_INPCC70B_Pos   (0UL)
 
#define CCU7_INP_2_INPCC70B_Msk   (0x3UL)
 
#define CCU7_INP_2_INPCC71B_Pos   (2UL)
 
#define CCU7_INP_2_INPCC71B_Msk   (0xcUL)
 
#define CCU7_INP_2_INPCC72B_Pos   (4UL)
 
#define CCU7_INP_2_INPCC72B_Msk   (0x30UL)
 
#define CCU7_INP_2_INPT14_Pos   (8UL)
 
#define CCU7_INP_2_INPT14_Msk   (0x300UL)
 
#define CCU7_INP_2_INPT15_Pos   (10UL)
 
#define CCU7_INP_2_INPT15_Msk   (0xc00UL)
 
#define CCU7_INP_2_INPT16_Pos   (12UL)
 
#define CCU7_INP_2_INPT16_Msk   (0x3000UL)
 
#define CCU7_LI_INPLBE_Pos   (14UL)
 
#define CCU7_LI_INPLBE_Msk   (0xc000UL)
 
#define CPU_NVIC_ISER_IRQEN0_Pos   (0UL)
 
#define CPU_NVIC_ISER_IRQEN0_Msk   (0x1UL)
 
#define CPU_NVIC_ISER_IRQEN1_Pos   (1UL)
 
#define CPU_NVIC_ISER_IRQEN1_Msk   (0x2UL)
 
#define CPU_NVIC_ISER_IRQEN2_Pos   (2UL)
 
#define CPU_NVIC_ISER_IRQEN2_Msk   (0x4UL)
 
#define CPU_NVIC_ISER_IRQEN3_Pos   (3UL)
 
#define CPU_NVIC_ISER_IRQEN3_Msk   (0x8UL)
 
#define CPU_NVIC_ISER_IRQEN4_Pos   (4UL)
 
#define CPU_NVIC_ISER_IRQEN4_Msk   (0x10UL)
 
#define CPU_NVIC_ISER_IRQEN5_Pos   (5UL)
 
#define CPU_NVIC_ISER_IRQEN5_Msk   (0x20UL)
 
#define CPU_NVIC_ISER_IRQEN6_Pos   (6UL)
 
#define CPU_NVIC_ISER_IRQEN6_Msk   (0x40UL)
 
#define CPU_NVIC_ISER_IRQEN7_Pos   (7UL)
 
#define CPU_NVIC_ISER_IRQEN7_Msk   (0x80UL)
 
#define CPU_NVIC_ISER_IRQEN8_Pos   (8UL)
 
#define CPU_NVIC_ISER_IRQEN8_Msk   (0x100UL)
 
#define CPU_NVIC_ISER_IRQEN9_Pos   (9UL)
 
#define CPU_NVIC_ISER_IRQEN9_Msk   (0x200UL)
 
#define CPU_NVIC_ISER_IRQEN10_Pos   (10UL)
 
#define CPU_NVIC_ISER_IRQEN10_Msk   (0x400UL)
 
#define CPU_NVIC_ISER_IRQEN11_Pos   (11UL)
 
#define CPU_NVIC_ISER_IRQEN11_Msk   (0x800UL)
 
#define CPU_NVIC_ISER_IRQEN12_Pos   (12UL)
 
#define CPU_NVIC_ISER_IRQEN12_Msk   (0x1000UL)
 
#define CPU_NVIC_ISER_IRQEN13_Pos   (13UL)
 
#define CPU_NVIC_ISER_IRQEN13_Msk   (0x2000UL)
 
#define CPU_NVIC_ISER_IRQEN14_Pos   (14UL)
 
#define CPU_NVIC_ISER_IRQEN14_Msk   (0x4000UL)
 
#define CPU_NVIC_ISER_IRQEN15_Pos   (15UL)
 
#define CPU_NVIC_ISER_IRQEN15_Msk   (0x8000UL)
 
#define CPU_NVIC_ISER_IRQEN16_Pos   (16UL)
 
#define CPU_NVIC_ISER_IRQEN16_Msk   (0x10000UL)
 
#define CPU_NVIC_ISER_IRQEN17_Pos   (17UL)
 
#define CPU_NVIC_ISER_IRQEN17_Msk   (0x20000UL)
 
#define CPU_NVIC_ISER_IRQEN18_Pos   (18UL)
 
#define CPU_NVIC_ISER_IRQEN18_Msk   (0x40000UL)
 
#define CPU_NVIC_ISER_IRQEN19_Pos   (19UL)
 
#define CPU_NVIC_ISER_IRQEN19_Msk   (0x80000UL)
 
#define CPU_NVIC_ISER_IRQEN20_Pos   (20UL)
 
#define CPU_NVIC_ISER_IRQEN20_Msk   (0x100000UL)
 
#define CPU_NVIC_ISER_IRQEN21_Pos   (21UL)
 
#define CPU_NVIC_ISER_IRQEN21_Msk   (0x200000UL)
 
#define CPU_NVIC_ISER_IRQEN22_Pos   (22UL)
 
#define CPU_NVIC_ISER_IRQEN22_Msk   (0x400000UL)
 
#define CPU_NVIC_ISER_IRQEN23_Pos   (23UL)
 
#define CPU_NVIC_ISER_IRQEN23_Msk   (0x800000UL)
 
#define CPU_NVIC_ISER_IRQEN24_Pos   (24UL)
 
#define CPU_NVIC_ISER_IRQEN24_Msk   (0x1000000UL)
 
#define CPU_NVIC_ISER_IRQEN25_Pos   (25UL)
 
#define CPU_NVIC_ISER_IRQEN25_Msk   (0x2000000UL)
 
#define CPU_NVIC_ISER_IRQEN26_Pos   (26UL)
 
#define CPU_NVIC_ISER_IRQEN26_Msk   (0x4000000UL)
 
#define CPU_NVIC_ISER_IRQEN27_Pos   (27UL)
 
#define CPU_NVIC_ISER_IRQEN27_Msk   (0x8000000UL)
 
#define CPU_NVIC_ISER_IRQEN28_Pos   (28UL)
 
#define CPU_NVIC_ISER_IRQEN28_Msk   (0x10000000UL)
 
#define CPU_NVIC_ISER_IRQEN29_Pos   (29UL)
 
#define CPU_NVIC_ISER_IRQEN29_Msk   (0x20000000UL)
 
#define CPU_NVIC_ISER_IRQEN30_Pos   (30UL)
 
#define CPU_NVIC_ISER_IRQEN30_Msk   (0x40000000UL)
 
#define CPU_NVIC_ISER_IRQEN31_Pos   (31UL)
 
#define CPU_NVIC_ISER_IRQEN31_Msk   (0x80000000UL)
 
#define CSACSC_CTRL1_CSAC_EN_Pos   (0UL)
 
#define CSACSC_CTRL1_CSAC_EN_Msk   (0x1UL)
 
#define GPIO_P0_OMR_PS0_Pos   (0UL)
 
#define GPIO_P0_OMR_PS0_Msk   (0x1UL)
 
#define GPIO_P0_OMR_PS1_Pos   (1UL)
 
#define GPIO_P0_OMR_PS1_Msk   (0x2UL)
 
#define GPIO_P0_OMR_PS2_Pos   (2UL)
 
#define GPIO_P0_OMR_PS2_Msk   (0x4UL)
 
#define GPIO_P0_OMR_PS3_Pos   (3UL)
 
#define GPIO_P0_OMR_PS3_Msk   (0x8UL)
 
#define GPIO_P0_OMR_PS4_Pos   (4UL)
 
#define GPIO_P0_OMR_PS4_Msk   (0x10UL)
 
#define GPIO_P0_OMR_PS5_Pos   (5UL)
 
#define GPIO_P0_OMR_PS5_Msk   (0x20UL)
 
#define GPIO_P0_OMR_PS6_Pos   (6UL)
 
#define GPIO_P0_OMR_PS6_Msk   (0x40UL)
 
#define GPIO_P0_OMR_PS7_Pos   (7UL)
 
#define GPIO_P0_OMR_PS7_Msk   (0x80UL)
 
#define GPIO_P0_OMR_PS8_Pos   (8UL)
 
#define GPIO_P0_OMR_PS8_Msk   (0x100UL)
 
#define GPIO_P0_OMR_PS9_Pos   (9UL)
 
#define GPIO_P0_OMR_PS9_Msk   (0x200UL)
 
#define GPIO_P0_OMR_PS10_Pos   (10UL)
 
#define GPIO_P0_OMR_PS10_Msk   (0x400UL)
 
#define GPIO_P1_OMR_PS0_Pos   (0UL)
 
#define GPIO_P1_OMR_PS0_Msk   (0x1UL)
 
#define GPIO_P1_OMR_PS1_Pos   (1UL)
 
#define GPIO_P1_OMR_PS1_Msk   (0x2UL)
 
#define GPIO_P1_OMR_PS2_Pos   (2UL)
 
#define GPIO_P1_OMR_PS2_Msk   (0x4UL)
 
#define GPIO_P1_OMR_PS3_Pos   (3UL)
 
#define GPIO_P1_OMR_PS3_Msk   (0x8UL)
 
#define GPIO_P1_OMR_PS4_Pos   (4UL)
 
#define GPIO_P1_OMR_PS4_Msk   (0x10UL)
 
#define PLL_CON0_PLLEN_Pos   (31UL)
 
#define PLL_CON0_PLLEN_Msk   (0x80000000UL)
 
#define PLL_CON1_PLLEN_Pos   (31UL)
 
#define PLL_CON1_PLLEN_Msk   (0x80000000UL)
 
#define PLL_SPCTR_SPEN0_Pos   (0UL)
 
#define PLL_SPCTR_SPEN0_Msk   (0x1UL)
 
#define PLL_SPCTR_SPEN1_Pos   (16UL)
 
#define PLL_SPCTR_SPEN1_Msk   (0x10000UL)
 
#define PLL_STATC_PLL0_LOL_STSCLR_Pos   (0UL)
 
#define PLL_STATC_PLL0_LOL_STSCLR_Msk   (0x1UL)
 
#define PLL_STATC_PLL1_LOL_STSCLR_Pos   (1UL)
 
#define PLL_STATC_PLL1_LOL_STSCLR_Msk   (0x2UL)
 
#define PMU_FS_SSD_CLR_SSD_STS_CLR_Pos   (0UL)
 
#define PMU_FS_SSD_CLR_SSD_STS_CLR_Msk   (0x1UL)
 
#define PMU_FS_SSD_CLR_FO_STS_CLR_Pos   (1UL)
 
#define PMU_FS_SSD_CLR_FO_STS_CLR_Msk   (0x2UL)
 
#define PMU_WAKE_CTRL_CAN_WAKE_EN_Pos   (0UL)
 
#define PMU_WAKE_CTRL_CAN_WAKE_EN_Msk   (0x1UL)
 
#define PMU_WAKE_CTRL_MON1_WAKE_EN_Pos   (12UL)
 
#define PMU_WAKE_CTRL_MON1_WAKE_EN_Msk   (0x1000UL)
 
#define PMU_WAKE_CTRL_MON2_WAKE_EN_Pos   (13UL)
 
#define PMU_WAKE_CTRL_MON2_WAKE_EN_Msk   (0x2000UL)
 
#define PMU_WAKE_CTRL_MON3_WAKE_EN_Pos   (14UL)
 
#define PMU_WAKE_CTRL_MON3_WAKE_EN_Msk   (0x4000UL)
 
#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Pos   (4UL)
 
#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk   (0x10UL)
 
#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Pos   (5UL)
 
#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk   (0x20UL)
 
#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Pos   (6UL)
 
#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk   (0x40UL)
 
#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Pos   (7UL)
 
#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk   (0x80UL)
 
#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Pos   (8UL)
 
#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk   (0x100UL)
 
#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Pos   (9UL)
 
#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk   (0x200UL)
 
#define PMU_WAKE_CTRL_CYC_WAKE_EN_Pos   (2UL)
 
#define PMU_WAKE_CTRL_CYC_WAKE_EN_Msk   (0x4UL)
 
#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Pos   (16UL)
 
#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk   (0x10000UL)
 
#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Pos   (17UL)
 
#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk   (0x20000UL)
 
#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Pos   (18UL)
 
#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk   (0x40000UL)
 
#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Pos   (19UL)
 
#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk   (0x80000UL)
 
#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Pos   (20UL)
 
#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk   (0x100000UL)
 
#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Pos   (21UL)
 
#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk   (0x200000UL)
 
#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Pos   (22UL)
 
#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk   (0x400000UL)
 
#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Pos   (23UL)
 
#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk   (0x800000UL)
 
#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Pos   (24UL)
 
#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk   (0x1000000UL)
 
#define PMU_WAKE_CTRL_VDDC_RED_EN_Pos   (29UL)
 
#define PMU_WAKE_CTRL_VDDC_RED_EN_Msk   (0x20000000UL)
 
#define PMU_WD_CTRL_WDP_Pos   (16UL)
 
#define PMU_WD_CTRL_WDP_Msk   (0x3f0000UL)
 
#define PMU_WD_CTRL_SOW_Pos   (24UL)
 
#define PMU_WD_CTRL_SOW_Msk   (0x3000000UL)
 
#define SCU_CLKSEL_CLKOUTEN_Pos   (19UL)
 
#define SCU_CLKSEL_CLKOUTEN_Msk   (0x80000UL)
 
#define SCU_INP0_INP_PMU_Pos   (0UL)
 
#define SCU_INP0_INP_PMU_Msk   (0x1UL)
 
#define SCU_INP0_INP_BDRV_IRQ0_Pos   (1UL)
 
#define SCU_INP0_INP_BDRV_IRQ0_Msk   (0x2UL)
 
#define SCU_INP0_INP_BDRV_IRQ1_Pos   (2UL)
 
#define SCU_INP0_INP_BDRV_IRQ1_Msk   (0x4UL)
 
#define SCU_INP0_INP_CANTX_Pos   (3UL)
 
#define SCU_INP0_INP_CANTX_Msk   (0x8UL)
 
#define SCU_INP0_INP_ARVG_Pos   (4UL)
 
#define SCU_INP0_INP_ARVG_Msk   (0x10UL)
 
#define SCU_INP0_INP_CSC_Pos   (5UL)
 
#define SCU_INP0_INP_CSC_Msk   (0x20UL)
 
#define SCU_INP1_INP_GPT1T2_Pos   (0UL)
 
#define SCU_INP1_INP_GPT1T2_Msk   (0x1UL)
 
#define SCU_INP1_INP_GPT1T3_Pos   (1UL)
 
#define SCU_INP1_INP_GPT1T3_Msk   (0x2UL)
 
#define SCU_INP1_INP_GPT1T4_Pos   (2UL)
 
#define SCU_INP1_INP_GPT1T4_Msk   (0x4UL)
 
#define SCU_INP1_INP_GPT2T5_Pos   (3UL)
 
#define SCU_INP1_INP_GPT2T5_Msk   (0x8UL)
 
#define SCU_INP1_INP_GPT2T6_Pos   (4UL)
 
#define SCU_INP1_INP_GPT2T6_Msk   (0x10UL)
 
#define SCU_INP1_INP_GPT2CR_Pos   (5UL)
 
#define SCU_INP1_INP_GPT2CR_Msk   (0x20UL)
 
#define SCU_INP2_INP_MON1_Pos   (0UL)
 
#define SCU_INP2_INP_MON1_Msk   (0x1UL)
 
#define SCU_INP2_INP_MON2_Pos   (1UL)
 
#define SCU_INP2_INP_MON2_Msk   (0x2UL)
 
#define SCU_INP2_INP_MON3_Pos   (2UL)
 
#define SCU_INP2_INP_MON3_Msk   (0x4UL)
 
#define SCU_INP3_INP_SDADC0_Pos   (0UL)
 
#define SCU_INP3_INP_SDADC0_Msk   (0x1UL)
 
#define SCU_INP3_INP_SDADC1_Pos   (1UL)
 
#define SCU_INP3_INP_SDADC1_Msk   (0x2UL)
 
#define SCU_INP3_INP_BEMF0_Pos   (2UL)
 
#define SCU_INP3_INP_BEMF0_Msk   (0x4UL)
 
#define SCU_INP3_INP_BEMF1_Pos   (3UL)
 
#define SCU_INP3_INP_BEMF1_Msk   (0x8UL)
 
#define SCU_INP3_INP_BEMF2_Pos   (4UL)
 
#define SCU_INP3_INP_BEMF2_Msk   (0x10UL)
 
#define SCU_INP4_INP_EXINT0_Pos   (0UL)
 
#define SCU_INP4_INP_EXINT0_Msk   (0x1UL)
 
#define SCU_INP4_INP_EXINT1_Pos   (1UL)
 
#define SCU_INP4_INP_EXINT1_Msk   (0x2UL)
 
#define SCU_INP4_INP_EXINT2_Pos   (2UL)
 
#define SCU_INP4_INP_EXINT2_Msk   (0x4UL)
 
#define SCU_INP4_INP_EXINT3_Pos   (3UL)
 
#define SCU_INP4_INP_EXINT3_Msk   (0x8UL)
 
#define SCU_INP5_INP_LIN0_EOFSYN_Pos   (0UL)
 
#define SCU_INP5_INP_LIN0_EOFSYN_Msk   (0x1UL)
 
#define SCU_INP5_INP_LIN0_ERRSYN_Pos   (1UL)
 
#define SCU_INP5_INP_LIN0_ERRSYN_Msk   (0x2UL)
 
#define SCU_INP5_INP_LIN1_EOFSYN_Pos   (2UL)
 
#define SCU_INP5_INP_LIN1_EOFSYN_Msk   (0x4UL)
 
#define SCU_INP5_INP_LIN1_ERRSYN_Pos   (3UL)
 
#define SCU_INP5_INP_LIN1_ERRSYN_Msk   (0x8UL)
 
#define SCU_INP5_INP_UART0_RI_Pos   (4UL)
 
#define SCU_INP5_INP_UART0_RI_Msk   (0x10UL)
 
#define SCU_INP5_INP_UART0_TI_Pos   (5UL)
 
#define SCU_INP5_INP_UART0_TI_Msk   (0x20UL)
 
#define SCU_INP5_INP_UART1_RI_Pos   (6UL)
 
#define SCU_INP5_INP_UART1_RI_Msk   (0x40UL)
 
#define SCU_INP5_INP_UART1_TI_Pos   (7UL)
 
#define SCU_INP5_INP_UART1_TI_Msk   (0x80UL)
 
#define SCU_INP6_INP_SSC0_RIR_Pos   (0UL)
 
#define SCU_INP6_INP_SSC0_RIR_Msk   (0x1UL)
 
#define SCU_INP6_INP_SSC0_TIR_Pos   (1UL)
 
#define SCU_INP6_INP_SSC0_TIR_Msk   (0x2UL)
 
#define SCU_INP6_INP_SSC0_EIR_Pos   (2UL)
 
#define SCU_INP6_INP_SSC0_EIR_Msk   (0x4UL)
 
#define SCU_INP6_INP_SSC1_RIR_Pos   (4UL)
 
#define SCU_INP6_INP_SSC1_RIR_Msk   (0x10UL)
 
#define SCU_INP6_INP_SSC1_TIR_Pos   (5UL)
 
#define SCU_INP6_INP_SSC1_TIR_Msk   (0x20UL)
 
#define SCU_INP6_INP_SSC1_EIR_Pos   (6UL)
 
#define SCU_INP6_INP_SSC1_EIR_Msk   (0x40UL)
 
#define SCU_INP7_INP_DMACH0_Pos   (0UL)
 
#define SCU_INP7_INP_DMACH0_Msk   (0x1UL)
 
#define SCU_INP7_INP_DMACH1_Pos   (1UL)
 
#define SCU_INP7_INP_DMACH1_Msk   (0x2UL)
 
#define SCU_INP7_INP_DMACH2_Pos   (2UL)
 
#define SCU_INP7_INP_DMACH2_Msk   (0x4UL)
 
#define SCU_INP7_INP_DMACH3_Pos   (3UL)
 
#define SCU_INP7_INP_DMACH3_Msk   (0x8UL)
 
#define SCU_INP7_INP_DMACH4_Pos   (4UL)
 
#define SCU_INP7_INP_DMACH4_Msk   (0x10UL)
 
#define SCU_INP7_INP_DMACH5_Pos   (5UL)
 
#define SCU_INP7_INP_DMACH5_Msk   (0x20UL)
 
#define SCU_INP7_INP_DMACH6_Pos   (6UL)
 
#define SCU_INP7_INP_DMACH6_Msk   (0x40UL)
 
#define SCU_INP7_INP_DMACH7_Pos   (7UL)
 
#define SCU_INP7_INP_DMACH7_Msk   (0x80UL)
 
#define SCU_INP7_INP_DMATRERR_Pos   (8UL)
 
#define SCU_INP7_INP_DMATRERR_Msk   (0x100UL)
 
#define SCU_NMISRC_NMIXTALCLR_Pos   (0UL)
 
#define SCU_NMISRC_NMIXTALCLR_Msk   (0x1UL)
 
#define SCU_NMISRC_NMIPLL0CLR_Pos   (1UL)
 
#define SCU_NMISRC_NMIPLL0CLR_Msk   (0x2UL)
 
#define SCU_NMISRC_NMIPLL1CLR_Pos   (2UL)
 
#define SCU_NMISRC_NMIPLL1CLR_Msk   (0x4UL)
 
#define SCU_PMCON_SSC0_DIS_Pos   (0UL)
 
#define SCU_PMCON_SSC0_DIS_Msk   (0x1UL)
 
#define SCU_PMCON_SSC1_DIS_Pos   (1UL)
 
#define SCU_PMCON_SSC1_DIS_Msk   (0x2UL)
 
#define SCU_PMCON_T2_DIS_Pos   (2UL)
 
#define SCU_PMCON_T2_DIS_Msk   (0x4UL)
 
#define SCU_PMCON_T21_DIS_Pos   (3UL)
 
#define SCU_PMCON_T21_DIS_Msk   (0x8UL)
 
#define SCU_PMCON_GPT12_DIS_Pos   (4UL)
 
#define SCU_PMCON_GPT12_DIS_Msk   (0x10UL)
 
#define SCU_XTALCON_XPD_Pos   (0UL)
 
#define SCU_XTALCON_XPD_Msk   (0x1UL)
 
#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Pos   (0UL)
 
#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Msk   (0x1UL)
 
#define UART0_BCON_BR_R_Pos   (0UL)
 
#define UART0_BCON_BR_R_Msk   (0x1UL)
 
#define UART0_SCON_SM1_Pos   (1UL)
 
#define UART0_SCON_SM1_Msk   (0x2UL)
 
#define UART1_BCON_BR_R_Pos   (0UL)
 
#define UART1_BCON_BR_R_Msk   (0x1UL)
 
#define UART1_SCON_SM1_Pos   (1UL)
 
#define UART1_SCON_SM1_Msk   (0x2UL)
 

Macro Definition Documentation

◆ ADC1_GLOBCONF_EN_Msk [1/2]

#define ADC1_GLOBCONF_EN_Msk   (0x1UL)

EN (Bitfield-Mask: 0x01)

◆ ADC1_GLOBCONF_EN_Msk [2/2]

#define ADC1_GLOBCONF_EN_Msk   (0x1UL)

EN (Bitfield-Mask: 0x01)

◆ ADC1_GLOBCONF_EN_Pos [1/2]

#define ADC1_GLOBCONF_EN_Pos   (0UL)

EN (Bit 0)

◆ ADC1_GLOBCONF_EN_Pos [2/2]

#define ADC1_GLOBCONF_EN_Pos   (0UL)

EN (Bit 0)

◆ ADC1_INP0_INP_CH0_Msk [1/2]

#define ADC1_INP0_INP_CH0_Msk   (0x3UL)

INP_CH0 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH0_Msk [2/2]

#define ADC1_INP0_INP_CH0_Msk   (0x3UL)

INP_CH0 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH0_Pos [1/2]

#define ADC1_INP0_INP_CH0_Pos   (0UL)

INP_CH0 (Bit 0)

◆ ADC1_INP0_INP_CH0_Pos [2/2]

#define ADC1_INP0_INP_CH0_Pos   (0UL)

INP_CH0 (Bit 0)

◆ ADC1_INP0_INP_CH10_Msk [1/2]

#define ADC1_INP0_INP_CH10_Msk   (0x300000UL)

INP_CH10 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH10_Msk [2/2]

#define ADC1_INP0_INP_CH10_Msk   (0x300000UL)

INP_CH10 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH10_Pos [1/2]

#define ADC1_INP0_INP_CH10_Pos   (20UL)

INP_CH10 (Bit 20)

◆ ADC1_INP0_INP_CH10_Pos [2/2]

#define ADC1_INP0_INP_CH10_Pos   (20UL)

INP_CH10 (Bit 20)

◆ ADC1_INP0_INP_CH11_Msk [1/2]

#define ADC1_INP0_INP_CH11_Msk   (0xc00000UL)

INP_CH11 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH11_Msk [2/2]

#define ADC1_INP0_INP_CH11_Msk   (0xc00000UL)

INP_CH11 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH11_Pos [1/2]

#define ADC1_INP0_INP_CH11_Pos   (22UL)

INP_CH11 (Bit 22)

◆ ADC1_INP0_INP_CH11_Pos [2/2]

#define ADC1_INP0_INP_CH11_Pos   (22UL)

INP_CH11 (Bit 22)

◆ ADC1_INP0_INP_CH12_Msk [1/2]

#define ADC1_INP0_INP_CH12_Msk   (0x3000000UL)

INP_CH12 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH12_Msk [2/2]

#define ADC1_INP0_INP_CH12_Msk   (0x3000000UL)

INP_CH12 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH12_Pos [1/2]

#define ADC1_INP0_INP_CH12_Pos   (24UL)

INP_CH12 (Bit 24)

◆ ADC1_INP0_INP_CH12_Pos [2/2]

#define ADC1_INP0_INP_CH12_Pos   (24UL)

INP_CH12 (Bit 24)

◆ ADC1_INP0_INP_CH13_Msk [1/2]

#define ADC1_INP0_INP_CH13_Msk   (0xc000000UL)

INP_CH13 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH13_Msk [2/2]

#define ADC1_INP0_INP_CH13_Msk   (0xc000000UL)

INP_CH13 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH13_Pos [1/2]

#define ADC1_INP0_INP_CH13_Pos   (26UL)

INP_CH13 (Bit 26)

◆ ADC1_INP0_INP_CH13_Pos [2/2]

#define ADC1_INP0_INP_CH13_Pos   (26UL)

INP_CH13 (Bit 26)

◆ ADC1_INP0_INP_CH14_Msk [1/2]

#define ADC1_INP0_INP_CH14_Msk   (0x30000000UL)

INP_CH14 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH14_Msk [2/2]

#define ADC1_INP0_INP_CH14_Msk   (0x30000000UL)

INP_CH14 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH14_Pos [1/2]

#define ADC1_INP0_INP_CH14_Pos   (28UL)

INP_CH14 (Bit 28)

◆ ADC1_INP0_INP_CH14_Pos [2/2]

#define ADC1_INP0_INP_CH14_Pos   (28UL)

INP_CH14 (Bit 28)

◆ ADC1_INP0_INP_CH15_Msk [1/2]

#define ADC1_INP0_INP_CH15_Msk   (0xc0000000UL)

INP_CH15 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH15_Msk [2/2]

#define ADC1_INP0_INP_CH15_Msk   (0xc0000000UL)

INP_CH15 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH15_Pos [1/2]

#define ADC1_INP0_INP_CH15_Pos   (30UL)

INP_CH15 (Bit 30)

◆ ADC1_INP0_INP_CH15_Pos [2/2]

#define ADC1_INP0_INP_CH15_Pos   (30UL)

INP_CH15 (Bit 30)

◆ ADC1_INP0_INP_CH1_Msk [1/2]

#define ADC1_INP0_INP_CH1_Msk   (0xcUL)

INP_CH1 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH1_Msk [2/2]

#define ADC1_INP0_INP_CH1_Msk   (0xcUL)

INP_CH1 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH1_Pos [1/2]

#define ADC1_INP0_INP_CH1_Pos   (2UL)

INP_CH1 (Bit 2)

◆ ADC1_INP0_INP_CH1_Pos [2/2]

#define ADC1_INP0_INP_CH1_Pos   (2UL)

INP_CH1 (Bit 2)

◆ ADC1_INP0_INP_CH2_Msk [1/2]

#define ADC1_INP0_INP_CH2_Msk   (0x30UL)

INP_CH2 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH2_Msk [2/2]

#define ADC1_INP0_INP_CH2_Msk   (0x30UL)

INP_CH2 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH2_Pos [1/2]

#define ADC1_INP0_INP_CH2_Pos   (4UL)

INP_CH2 (Bit 4)

◆ ADC1_INP0_INP_CH2_Pos [2/2]

#define ADC1_INP0_INP_CH2_Pos   (4UL)

INP_CH2 (Bit 4)

◆ ADC1_INP0_INP_CH3_Msk [1/2]

#define ADC1_INP0_INP_CH3_Msk   (0xc0UL)

INP_CH3 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH3_Msk [2/2]

#define ADC1_INP0_INP_CH3_Msk   (0xc0UL)

INP_CH3 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH3_Pos [1/2]

#define ADC1_INP0_INP_CH3_Pos   (6UL)

INP_CH3 (Bit 6)

◆ ADC1_INP0_INP_CH3_Pos [2/2]

#define ADC1_INP0_INP_CH3_Pos   (6UL)

INP_CH3 (Bit 6)

◆ ADC1_INP0_INP_CH4_Msk [1/2]

#define ADC1_INP0_INP_CH4_Msk   (0x300UL)

INP_CH4 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH4_Msk [2/2]

#define ADC1_INP0_INP_CH4_Msk   (0x300UL)

INP_CH4 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH4_Pos [1/2]

#define ADC1_INP0_INP_CH4_Pos   (8UL)

INP_CH4 (Bit 8)

◆ ADC1_INP0_INP_CH4_Pos [2/2]

#define ADC1_INP0_INP_CH4_Pos   (8UL)

INP_CH4 (Bit 8)

◆ ADC1_INP0_INP_CH5_Msk [1/2]

#define ADC1_INP0_INP_CH5_Msk   (0xc00UL)

INP_CH5 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH5_Msk [2/2]

#define ADC1_INP0_INP_CH5_Msk   (0xc00UL)

INP_CH5 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH5_Pos [1/2]

#define ADC1_INP0_INP_CH5_Pos   (10UL)

INP_CH5 (Bit 10)

◆ ADC1_INP0_INP_CH5_Pos [2/2]

#define ADC1_INP0_INP_CH5_Pos   (10UL)

INP_CH5 (Bit 10)

◆ ADC1_INP0_INP_CH6_Msk [1/2]

#define ADC1_INP0_INP_CH6_Msk   (0x3000UL)

INP_CH6 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH6_Msk [2/2]

#define ADC1_INP0_INP_CH6_Msk   (0x3000UL)

INP_CH6 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH6_Pos [1/2]

#define ADC1_INP0_INP_CH6_Pos   (12UL)

INP_CH6 (Bit 12)

◆ ADC1_INP0_INP_CH6_Pos [2/2]

#define ADC1_INP0_INP_CH6_Pos   (12UL)

INP_CH6 (Bit 12)

◆ ADC1_INP0_INP_CH7_Msk [1/2]

#define ADC1_INP0_INP_CH7_Msk   (0xc000UL)

INP_CH7 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH7_Msk [2/2]

#define ADC1_INP0_INP_CH7_Msk   (0xc000UL)

INP_CH7 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH7_Pos [1/2]

#define ADC1_INP0_INP_CH7_Pos   (14UL)

INP_CH7 (Bit 14)

◆ ADC1_INP0_INP_CH7_Pos [2/2]

#define ADC1_INP0_INP_CH7_Pos   (14UL)

INP_CH7 (Bit 14)

◆ ADC1_INP0_INP_CH8_Msk [1/2]

#define ADC1_INP0_INP_CH8_Msk   (0x30000UL)

INP_CH8 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH8_Msk [2/2]

#define ADC1_INP0_INP_CH8_Msk   (0x30000UL)

INP_CH8 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH8_Pos [1/2]

#define ADC1_INP0_INP_CH8_Pos   (16UL)

INP_CH8 (Bit 16)

◆ ADC1_INP0_INP_CH8_Pos [2/2]

#define ADC1_INP0_INP_CH8_Pos   (16UL)

INP_CH8 (Bit 16)

◆ ADC1_INP0_INP_CH9_Msk [1/2]

#define ADC1_INP0_INP_CH9_Msk   (0xc0000UL)

INP_CH9 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH9_Msk [2/2]

#define ADC1_INP0_INP_CH9_Msk   (0xc0000UL)

INP_CH9 (Bitfield-Mask: 0x03)

◆ ADC1_INP0_INP_CH9_Pos [1/2]

#define ADC1_INP0_INP_CH9_Pos   (18UL)

INP_CH9 (Bit 18)

◆ ADC1_INP0_INP_CH9_Pos [2/2]

#define ADC1_INP0_INP_CH9_Pos   (18UL)

INP_CH9 (Bit 18)

◆ ADC1_INP1_INP_CH16_Msk [1/2]

#define ADC1_INP1_INP_CH16_Msk   (0x3UL)

INP_CH16 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH16_Msk [2/2]

#define ADC1_INP1_INP_CH16_Msk   (0x3UL)

INP_CH16 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH16_Pos [1/2]

#define ADC1_INP1_INP_CH16_Pos   (0UL)

INP_CH16 (Bit 0)

◆ ADC1_INP1_INP_CH16_Pos [2/2]

#define ADC1_INP1_INP_CH16_Pos   (0UL)

INP_CH16 (Bit 0)

◆ ADC1_INP1_INP_CH17_Msk [1/2]

#define ADC1_INP1_INP_CH17_Msk   (0xcUL)

INP_CH17 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH17_Msk [2/2]

#define ADC1_INP1_INP_CH17_Msk   (0xcUL)

INP_CH17 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH17_Pos [1/2]

#define ADC1_INP1_INP_CH17_Pos   (2UL)

INP_CH17 (Bit 2)

◆ ADC1_INP1_INP_CH17_Pos [2/2]

#define ADC1_INP1_INP_CH17_Pos   (2UL)

INP_CH17 (Bit 2)

◆ ADC1_INP1_INP_CH18_Msk [1/2]

#define ADC1_INP1_INP_CH18_Msk   (0x30UL)

INP_CH18 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH18_Msk [2/2]

#define ADC1_INP1_INP_CH18_Msk   (0x30UL)

INP_CH18 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH18_Pos [1/2]

#define ADC1_INP1_INP_CH18_Pos   (4UL)

INP_CH18 (Bit 4)

◆ ADC1_INP1_INP_CH18_Pos [2/2]

#define ADC1_INP1_INP_CH18_Pos   (4UL)

INP_CH18 (Bit 4)

◆ ADC1_INP1_INP_CH19_Msk [1/2]

#define ADC1_INP1_INP_CH19_Msk   (0xc0UL)

INP_CH19 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH19_Msk [2/2]

#define ADC1_INP1_INP_CH19_Msk   (0xc0UL)

INP_CH19 (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_CH19_Pos [1/2]

#define ADC1_INP1_INP_CH19_Pos   (6UL)

INP_CH19 (Bit 6)

◆ ADC1_INP1_INP_CH19_Pos [2/2]

#define ADC1_INP1_INP_CH19_Pos   (6UL)

INP_CH19 (Bit 6)

◆ ADC1_INP1_INP_EOC_FAIL_Msk

#define ADC1_INP1_INP_EOC_FAIL_Msk   (0x300UL)

INP_EOC_FAIL (Bitfield-Mask: 0x03)

◆ ADC1_INP1_INP_EOC_FAIL_Pos

#define ADC1_INP1_INP_EOC_FAIL_Pos   (8UL)

INP_EOC_FAIL (Bit 8)

◆ ADC1_INP2_INP_CMP_LO0_Msk [1/2]

#define ADC1_INP2_INP_CMP_LO0_Msk   (0x3UL)

INP_CMP_LO0 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO0_Msk [2/2]

#define ADC1_INP2_INP_CMP_LO0_Msk   (0x3UL)

INP_CMP_LO0 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO0_Pos [1/2]

#define ADC1_INP2_INP_CMP_LO0_Pos   (0UL)

INP_CMP_LO0 (Bit 0)

◆ ADC1_INP2_INP_CMP_LO0_Pos [2/2]

#define ADC1_INP2_INP_CMP_LO0_Pos   (0UL)

INP_CMP_LO0 (Bit 0)

◆ ADC1_INP2_INP_CMP_LO1_Msk [1/2]

#define ADC1_INP2_INP_CMP_LO1_Msk   (0xcUL)

INP_CMP_LO1 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO1_Msk [2/2]

#define ADC1_INP2_INP_CMP_LO1_Msk   (0xcUL)

INP_CMP_LO1 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO1_Pos [1/2]

#define ADC1_INP2_INP_CMP_LO1_Pos   (2UL)

INP_CMP_LO1 (Bit 2)

◆ ADC1_INP2_INP_CMP_LO1_Pos [2/2]

#define ADC1_INP2_INP_CMP_LO1_Pos   (2UL)

INP_CMP_LO1 (Bit 2)

◆ ADC1_INP2_INP_CMP_LO2_Msk [1/2]

#define ADC1_INP2_INP_CMP_LO2_Msk   (0x30UL)

INP_CMP_LO2 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO2_Msk [2/2]

#define ADC1_INP2_INP_CMP_LO2_Msk   (0x30UL)

INP_CMP_LO2 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO2_Pos [1/2]

#define ADC1_INP2_INP_CMP_LO2_Pos   (4UL)

INP_CMP_LO2 (Bit 4)

◆ ADC1_INP2_INP_CMP_LO2_Pos [2/2]

#define ADC1_INP2_INP_CMP_LO2_Pos   (4UL)

INP_CMP_LO2 (Bit 4)

◆ ADC1_INP2_INP_CMP_LO3_Msk [1/2]

#define ADC1_INP2_INP_CMP_LO3_Msk   (0xc0UL)

INP_CMP_LO3 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO3_Msk [2/2]

#define ADC1_INP2_INP_CMP_LO3_Msk   (0xc0UL)

INP_CMP_LO3 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_LO3_Pos [1/2]

#define ADC1_INP2_INP_CMP_LO3_Pos   (6UL)

INP_CMP_LO3 (Bit 6)

◆ ADC1_INP2_INP_CMP_LO3_Pos [2/2]

#define ADC1_INP2_INP_CMP_LO3_Pos   (6UL)

INP_CMP_LO3 (Bit 6)

◆ ADC1_INP2_INP_CMP_UP0_Msk [1/2]

#define ADC1_INP2_INP_CMP_UP0_Msk   (0x300UL)

INP_CMP_UP0 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP0_Msk [2/2]

#define ADC1_INP2_INP_CMP_UP0_Msk   (0x300UL)

INP_CMP_UP0 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP0_Pos [1/2]

#define ADC1_INP2_INP_CMP_UP0_Pos   (8UL)

INP_CMP_UP0 (Bit 8)

◆ ADC1_INP2_INP_CMP_UP0_Pos [2/2]

#define ADC1_INP2_INP_CMP_UP0_Pos   (8UL)

INP_CMP_UP0 (Bit 8)

◆ ADC1_INP2_INP_CMP_UP1_Msk [1/2]

#define ADC1_INP2_INP_CMP_UP1_Msk   (0xc00UL)

INP_CMP_UP1 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP1_Msk [2/2]

#define ADC1_INP2_INP_CMP_UP1_Msk   (0xc00UL)

INP_CMP_UP1 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP1_Pos [1/2]

#define ADC1_INP2_INP_CMP_UP1_Pos   (10UL)

INP_CMP_UP1 (Bit 10)

◆ ADC1_INP2_INP_CMP_UP1_Pos [2/2]

#define ADC1_INP2_INP_CMP_UP1_Pos   (10UL)

INP_CMP_UP1 (Bit 10)

◆ ADC1_INP2_INP_CMP_UP2_Msk [1/2]

#define ADC1_INP2_INP_CMP_UP2_Msk   (0x3000UL)

INP_CMP_UP2 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP2_Msk [2/2]

#define ADC1_INP2_INP_CMP_UP2_Msk   (0x3000UL)

INP_CMP_UP2 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP2_Pos [1/2]

#define ADC1_INP2_INP_CMP_UP2_Pos   (12UL)

INP_CMP_UP2 (Bit 12)

◆ ADC1_INP2_INP_CMP_UP2_Pos [2/2]

#define ADC1_INP2_INP_CMP_UP2_Pos   (12UL)

INP_CMP_UP2 (Bit 12)

◆ ADC1_INP2_INP_CMP_UP3_Msk [1/2]

#define ADC1_INP2_INP_CMP_UP3_Msk   (0xc000UL)

INP_CMP_UP3 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP3_Msk [2/2]

#define ADC1_INP2_INP_CMP_UP3_Msk   (0xc000UL)

INP_CMP_UP3 (Bitfield-Mask: 0x03)

◆ ADC1_INP2_INP_CMP_UP3_Pos [1/2]

#define ADC1_INP2_INP_CMP_UP3_Pos   (14UL)

INP_CMP_UP3 (Bit 14)

◆ ADC1_INP2_INP_CMP_UP3_Pos [2/2]

#define ADC1_INP2_INP_CMP_UP3_Pos   (14UL)

INP_CMP_UP3 (Bit 14)

◆ ADC1_INP3_INP_COLL0_Msk [1/2]

#define ADC1_INP3_INP_COLL0_Msk   (0x300UL)

INP_COLL0 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL0_Msk [2/2]

#define ADC1_INP3_INP_COLL0_Msk   (0x300UL)

INP_COLL0 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL0_Pos [1/2]

#define ADC1_INP3_INP_COLL0_Pos   (8UL)

INP_COLL0 (Bit 8)

◆ ADC1_INP3_INP_COLL0_Pos [2/2]

#define ADC1_INP3_INP_COLL0_Pos   (8UL)

INP_COLL0 (Bit 8)

◆ ADC1_INP3_INP_COLL1_Msk [1/2]

#define ADC1_INP3_INP_COLL1_Msk   (0xc00UL)

INP_COLL1 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL1_Msk [2/2]

#define ADC1_INP3_INP_COLL1_Msk   (0xc00UL)

INP_COLL1 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL1_Pos [1/2]

#define ADC1_INP3_INP_COLL1_Pos   (10UL)

INP_COLL1 (Bit 10)

◆ ADC1_INP3_INP_COLL1_Pos [2/2]

#define ADC1_INP3_INP_COLL1_Pos   (10UL)

INP_COLL1 (Bit 10)

◆ ADC1_INP3_INP_COLL2_Msk [1/2]

#define ADC1_INP3_INP_COLL2_Msk   (0x3000UL)

INP_COLL2 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL2_Msk [2/2]

#define ADC1_INP3_INP_COLL2_Msk   (0x3000UL)

INP_COLL2 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL2_Pos [1/2]

#define ADC1_INP3_INP_COLL2_Pos   (12UL)

INP_COLL2 (Bit 12)

◆ ADC1_INP3_INP_COLL2_Pos [2/2]

#define ADC1_INP3_INP_COLL2_Pos   (12UL)

INP_COLL2 (Bit 12)

◆ ADC1_INP3_INP_COLL3_Msk [1/2]

#define ADC1_INP3_INP_COLL3_Msk   (0xc000UL)

INP_COLL3 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL3_Msk [2/2]

#define ADC1_INP3_INP_COLL3_Msk   (0xc000UL)

INP_COLL3 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_COLL3_Pos [1/2]

#define ADC1_INP3_INP_COLL3_Pos   (14UL)

INP_COLL3 (Bit 14)

◆ ADC1_INP3_INP_COLL3_Pos [2/2]

#define ADC1_INP3_INP_COLL3_Pos   (14UL)

INP_COLL3 (Bit 14)

◆ ADC1_INP3_INP_SQ0_Msk [1/2]

#define ADC1_INP3_INP_SQ0_Msk   (0x3UL)

INP_SQ0 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ0_Msk [2/2]

#define ADC1_INP3_INP_SQ0_Msk   (0x3UL)

INP_SQ0 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ0_Pos [1/2]

#define ADC1_INP3_INP_SQ0_Pos   (0UL)

INP_SQ0 (Bit 0)

◆ ADC1_INP3_INP_SQ0_Pos [2/2]

#define ADC1_INP3_INP_SQ0_Pos   (0UL)

INP_SQ0 (Bit 0)

◆ ADC1_INP3_INP_SQ1_Msk [1/2]

#define ADC1_INP3_INP_SQ1_Msk   (0xcUL)

INP_SQ1 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ1_Msk [2/2]

#define ADC1_INP3_INP_SQ1_Msk   (0xcUL)

INP_SQ1 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ1_Pos [1/2]

#define ADC1_INP3_INP_SQ1_Pos   (2UL)

INP_SQ1 (Bit 2)

◆ ADC1_INP3_INP_SQ1_Pos [2/2]

#define ADC1_INP3_INP_SQ1_Pos   (2UL)

INP_SQ1 (Bit 2)

◆ ADC1_INP3_INP_SQ2_Msk [1/2]

#define ADC1_INP3_INP_SQ2_Msk   (0x30UL)

INP_SQ2 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ2_Msk [2/2]

#define ADC1_INP3_INP_SQ2_Msk   (0x30UL)

INP_SQ2 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ2_Pos [1/2]

#define ADC1_INP3_INP_SQ2_Pos   (4UL)

INP_SQ2 (Bit 4)

◆ ADC1_INP3_INP_SQ2_Pos [2/2]

#define ADC1_INP3_INP_SQ2_Pos   (4UL)

INP_SQ2 (Bit 4)

◆ ADC1_INP3_INP_SQ3_Msk [1/2]

#define ADC1_INP3_INP_SQ3_Msk   (0xc0UL)

INP_SQ3 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ3_Msk [2/2]

#define ADC1_INP3_INP_SQ3_Msk   (0xc0UL)

INP_SQ3 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_SQ3_Pos [1/2]

#define ADC1_INP3_INP_SQ3_Pos   (6UL)

INP_SQ3 (Bit 6)

◆ ADC1_INP3_INP_SQ3_Pos [2/2]

#define ADC1_INP3_INP_SQ3_Pos   (6UL)

INP_SQ3 (Bit 6)

◆ ADC1_INP3_INP_WFR0_Msk [1/2]

#define ADC1_INP3_INP_WFR0_Msk   (0x30000UL)

INP_WFR0 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR0_Msk [2/2]

#define ADC1_INP3_INP_WFR0_Msk   (0x30000UL)

INP_WFR0 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR0_Pos [1/2]

#define ADC1_INP3_INP_WFR0_Pos   (16UL)

INP_WFR0 (Bit 16)

◆ ADC1_INP3_INP_WFR0_Pos [2/2]

#define ADC1_INP3_INP_WFR0_Pos   (16UL)

INP_WFR0 (Bit 16)

◆ ADC1_INP3_INP_WFR1_Msk [1/2]

#define ADC1_INP3_INP_WFR1_Msk   (0xc0000UL)

INP_WFR1 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR1_Msk [2/2]

#define ADC1_INP3_INP_WFR1_Msk   (0xc0000UL)

INP_WFR1 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR1_Pos [1/2]

#define ADC1_INP3_INP_WFR1_Pos   (18UL)

INP_WFR1 (Bit 18)

◆ ADC1_INP3_INP_WFR1_Pos [2/2]

#define ADC1_INP3_INP_WFR1_Pos   (18UL)

INP_WFR1 (Bit 18)

◆ ADC1_INP3_INP_WFR2_Msk [1/2]

#define ADC1_INP3_INP_WFR2_Msk   (0x300000UL)

INP_WFR2 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR2_Msk [2/2]

#define ADC1_INP3_INP_WFR2_Msk   (0x300000UL)

INP_WFR2 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR2_Pos [1/2]

#define ADC1_INP3_INP_WFR2_Pos   (20UL)

INP_WFR2 (Bit 20)

◆ ADC1_INP3_INP_WFR2_Pos [2/2]

#define ADC1_INP3_INP_WFR2_Pos   (20UL)

INP_WFR2 (Bit 20)

◆ ADC1_INP3_INP_WFR3_Msk [1/2]

#define ADC1_INP3_INP_WFR3_Msk   (0xc00000UL)

INP_WFR3 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR3_Msk [2/2]

#define ADC1_INP3_INP_WFR3_Msk   (0xc00000UL)

INP_WFR3 (Bitfield-Mask: 0x03)

◆ ADC1_INP3_INP_WFR3_Pos [1/2]

#define ADC1_INP3_INP_WFR3_Pos   (22UL)

INP_WFR3 (Bit 22)

◆ ADC1_INP3_INP_WFR3_Pos [2/2]

#define ADC1_INP3_INP_WFR3_Pos   (22UL)

INP_WFR3 (Bit 22)

◆ ADC2_FILTCFG_COEF_A6_Msk

#define ADC2_FILTCFG_COEF_A6_Msk   (0x3000000UL)

COEF_A6 (Bitfield-Mask: 0x03)

◆ ADC2_FILTCFG_COEF_A6_Pos

#define ADC2_FILTCFG_COEF_A6_Pos   (24UL)

COEF_A6 (Bit 24)

◆ ADC2_FILTCFG_COEF_A7_Msk

#define ADC2_FILTCFG_COEF_A7_Msk   (0x30000000UL)

COEF_A7 (Bitfield-Mask: 0x03)

◆ ADC2_FILTCFG_COEF_A7_Pos

#define ADC2_FILTCFG_COEF_A7_Pos   (28UL)

COEF_A7 (Bit 28)

◆ ADC2_GLOBCONF_EN_Msk [1/2]

#define ADC2_GLOBCONF_EN_Msk   (0x1UL)

EN (Bitfield-Mask: 0x01)

◆ ADC2_GLOBCONF_EN_Msk [2/2]

#define ADC2_GLOBCONF_EN_Msk   (0x1UL)

EN (Bitfield-Mask: 0x01)

◆ ADC2_GLOBCONF_EN_Pos [1/2]

#define ADC2_GLOBCONF_EN_Pos   (0UL)

EN (Bit 0)

◆ ADC2_GLOBCONF_EN_Pos [2/2]

#define ADC2_GLOBCONF_EN_Pos   (0UL)

EN (Bit 0)

◆ ADC2_INP0_INP_CH0_Msk [1/2]

#define ADC2_INP0_INP_CH0_Msk   (0x3UL)

INP_CH0 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH0_Msk [2/2]

#define ADC2_INP0_INP_CH0_Msk   (0x3UL)

INP_CH0 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH0_Pos [1/2]

#define ADC2_INP0_INP_CH0_Pos   (0UL)

INP_CH0 (Bit 0)

◆ ADC2_INP0_INP_CH0_Pos [2/2]

#define ADC2_INP0_INP_CH0_Pos   (0UL)

INP_CH0 (Bit 0)

◆ ADC2_INP0_INP_CH10_Msk [1/2]

#define ADC2_INP0_INP_CH10_Msk   (0x300000UL)

INP_CH10 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH10_Msk [2/2]

#define ADC2_INP0_INP_CH10_Msk   (0x300000UL)

INP_CH10 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH10_Pos [1/2]

#define ADC2_INP0_INP_CH10_Pos   (20UL)

INP_CH10 (Bit 20)

◆ ADC2_INP0_INP_CH10_Pos [2/2]

#define ADC2_INP0_INP_CH10_Pos   (20UL)

INP_CH10 (Bit 20)

◆ ADC2_INP0_INP_CH11_Msk [1/2]

#define ADC2_INP0_INP_CH11_Msk   (0xc00000UL)

INP_CH11 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH11_Msk [2/2]

#define ADC2_INP0_INP_CH11_Msk   (0xc00000UL)

INP_CH11 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH11_Pos [1/2]

#define ADC2_INP0_INP_CH11_Pos   (22UL)

INP_CH11 (Bit 22)

◆ ADC2_INP0_INP_CH11_Pos [2/2]

#define ADC2_INP0_INP_CH11_Pos   (22UL)

INP_CH11 (Bit 22)

◆ ADC2_INP0_INP_CH12_Msk [1/2]

#define ADC2_INP0_INP_CH12_Msk   (0x3000000UL)

INP_CH12 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH12_Msk [2/2]

#define ADC2_INP0_INP_CH12_Msk   (0x3000000UL)

INP_CH12 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH12_Pos [1/2]

#define ADC2_INP0_INP_CH12_Pos   (24UL)

INP_CH12 (Bit 24)

◆ ADC2_INP0_INP_CH12_Pos [2/2]

#define ADC2_INP0_INP_CH12_Pos   (24UL)

INP_CH12 (Bit 24)

◆ ADC2_INP0_INP_CH13_Msk [1/2]

#define ADC2_INP0_INP_CH13_Msk   (0xc000000UL)

INP_CH13 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH13_Msk [2/2]

#define ADC2_INP0_INP_CH13_Msk   (0xc000000UL)

INP_CH13 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH13_Pos [1/2]

#define ADC2_INP0_INP_CH13_Pos   (26UL)

INP_CH13 (Bit 26)

◆ ADC2_INP0_INP_CH13_Pos [2/2]

#define ADC2_INP0_INP_CH13_Pos   (26UL)

INP_CH13 (Bit 26)

◆ ADC2_INP0_INP_CH14_Msk [1/2]

#define ADC2_INP0_INP_CH14_Msk   (0x30000000UL)

INP_CH14 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH14_Msk [2/2]

#define ADC2_INP0_INP_CH14_Msk   (0x30000000UL)

INP_CH14 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH14_Pos [1/2]

#define ADC2_INP0_INP_CH14_Pos   (28UL)

INP_CH14 (Bit 28)

◆ ADC2_INP0_INP_CH14_Pos [2/2]

#define ADC2_INP0_INP_CH14_Pos   (28UL)

INP_CH14 (Bit 28)

◆ ADC2_INP0_INP_CH1_Msk [1/2]

#define ADC2_INP0_INP_CH1_Msk   (0xcUL)

INP_CH1 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH1_Msk [2/2]

#define ADC2_INP0_INP_CH1_Msk   (0xcUL)

INP_CH1 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH1_Pos [1/2]

#define ADC2_INP0_INP_CH1_Pos   (2UL)

INP_CH1 (Bit 2)

◆ ADC2_INP0_INP_CH1_Pos [2/2]

#define ADC2_INP0_INP_CH1_Pos   (2UL)

INP_CH1 (Bit 2)

◆ ADC2_INP0_INP_CH2_Msk [1/2]

#define ADC2_INP0_INP_CH2_Msk   (0x30UL)

INP_CH2 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH2_Msk [2/2]

#define ADC2_INP0_INP_CH2_Msk   (0x30UL)

INP_CH2 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH2_Pos [1/2]

#define ADC2_INP0_INP_CH2_Pos   (4UL)

INP_CH2 (Bit 4)

◆ ADC2_INP0_INP_CH2_Pos [2/2]

#define ADC2_INP0_INP_CH2_Pos   (4UL)

INP_CH2 (Bit 4)

◆ ADC2_INP0_INP_CH3_Msk [1/2]

#define ADC2_INP0_INP_CH3_Msk   (0xc0UL)

INP_CH3 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH3_Msk [2/2]

#define ADC2_INP0_INP_CH3_Msk   (0xc0UL)

INP_CH3 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH3_Pos [1/2]

#define ADC2_INP0_INP_CH3_Pos   (6UL)

INP_CH3 (Bit 6)

◆ ADC2_INP0_INP_CH3_Pos [2/2]

#define ADC2_INP0_INP_CH3_Pos   (6UL)

INP_CH3 (Bit 6)

◆ ADC2_INP0_INP_CH4_Msk [1/2]

#define ADC2_INP0_INP_CH4_Msk   (0x300UL)

INP_CH4 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH4_Msk [2/2]

#define ADC2_INP0_INP_CH4_Msk   (0x300UL)

INP_CH4 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH4_Pos [1/2]

#define ADC2_INP0_INP_CH4_Pos   (8UL)

INP_CH4 (Bit 8)

◆ ADC2_INP0_INP_CH4_Pos [2/2]

#define ADC2_INP0_INP_CH4_Pos   (8UL)

INP_CH4 (Bit 8)

◆ ADC2_INP0_INP_CH5_Msk [1/2]

#define ADC2_INP0_INP_CH5_Msk   (0xc00UL)

INP_CH5 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH5_Msk [2/2]

#define ADC2_INP0_INP_CH5_Msk   (0xc00UL)

INP_CH5 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH5_Pos [1/2]

#define ADC2_INP0_INP_CH5_Pos   (10UL)

INP_CH5 (Bit 10)

◆ ADC2_INP0_INP_CH5_Pos [2/2]

#define ADC2_INP0_INP_CH5_Pos   (10UL)

INP_CH5 (Bit 10)

◆ ADC2_INP0_INP_CH6_Msk [1/2]

#define ADC2_INP0_INP_CH6_Msk   (0x3000UL)

INP_CH6 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH6_Msk [2/2]

#define ADC2_INP0_INP_CH6_Msk   (0x3000UL)

INP_CH6 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH6_Pos [1/2]

#define ADC2_INP0_INP_CH6_Pos   (12UL)

INP_CH6 (Bit 12)

◆ ADC2_INP0_INP_CH6_Pos [2/2]

#define ADC2_INP0_INP_CH6_Pos   (12UL)

INP_CH6 (Bit 12)

◆ ADC2_INP0_INP_CH7_Msk [1/2]

#define ADC2_INP0_INP_CH7_Msk   (0xc000UL)

INP_CH7 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH7_Msk [2/2]

#define ADC2_INP0_INP_CH7_Msk   (0xc000UL)

INP_CH7 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH7_Pos [1/2]

#define ADC2_INP0_INP_CH7_Pos   (14UL)

INP_CH7 (Bit 14)

◆ ADC2_INP0_INP_CH7_Pos [2/2]

#define ADC2_INP0_INP_CH7_Pos   (14UL)

INP_CH7 (Bit 14)

◆ ADC2_INP0_INP_CH8_Msk [1/2]

#define ADC2_INP0_INP_CH8_Msk   (0x30000UL)

INP_CH8 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH8_Msk [2/2]

#define ADC2_INP0_INP_CH8_Msk   (0x30000UL)

INP_CH8 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH8_Pos [1/2]

#define ADC2_INP0_INP_CH8_Pos   (16UL)

INP_CH8 (Bit 16)

◆ ADC2_INP0_INP_CH8_Pos [2/2]

#define ADC2_INP0_INP_CH8_Pos   (16UL)

INP_CH8 (Bit 16)

◆ ADC2_INP0_INP_CH9_Msk [1/2]

#define ADC2_INP0_INP_CH9_Msk   (0xc0000UL)

INP_CH9 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH9_Msk [2/2]

#define ADC2_INP0_INP_CH9_Msk   (0xc0000UL)

INP_CH9 (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_CH9_Pos [1/2]

#define ADC2_INP0_INP_CH9_Pos   (18UL)

INP_CH9 (Bit 18)

◆ ADC2_INP0_INP_CH9_Pos [2/2]

#define ADC2_INP0_INP_CH9_Pos   (18UL)

INP_CH9 (Bit 18)

◆ ADC2_INP0_INP_EOC_FAIL_Msk

#define ADC2_INP0_INP_EOC_FAIL_Msk   (0xc0000000UL)

INP_EOC_FAIL (Bitfield-Mask: 0x03)

◆ ADC2_INP0_INP_EOC_FAIL_Pos

#define ADC2_INP0_INP_EOC_FAIL_Pos   (30UL)

INP_EOC_FAIL (Bit 30)

◆ ADC2_INP2_INP_CMP_LO0_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO0_Msk   (0x3UL)

INP_CMP_LO0 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO0_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO0_Msk   (0x3UL)

INP_CMP_LO0 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO0_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO0_Pos   (0UL)

INP_CMP_LO0 (Bit 0)

◆ ADC2_INP2_INP_CMP_LO0_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO0_Pos   (0UL)

INP_CMP_LO0 (Bit 0)

◆ ADC2_INP2_INP_CMP_LO1_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO1_Msk   (0xcUL)

INP_CMP_LO1 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO1_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO1_Msk   (0xcUL)

INP_CMP_LO1 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO1_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO1_Pos   (2UL)

INP_CMP_LO1 (Bit 2)

◆ ADC2_INP2_INP_CMP_LO1_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO1_Pos   (2UL)

INP_CMP_LO1 (Bit 2)

◆ ADC2_INP2_INP_CMP_LO2_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO2_Msk   (0x30UL)

INP_CMP_LO2 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO2_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO2_Msk   (0x30UL)

INP_CMP_LO2 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO2_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO2_Pos   (4UL)

INP_CMP_LO2 (Bit 4)

◆ ADC2_INP2_INP_CMP_LO2_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO2_Pos   (4UL)

INP_CMP_LO2 (Bit 4)

◆ ADC2_INP2_INP_CMP_LO3_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO3_Msk   (0xc0UL)

INP_CMP_LO3 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO3_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO3_Msk   (0xc0UL)

INP_CMP_LO3 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO3_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO3_Pos   (6UL)

INP_CMP_LO3 (Bit 6)

◆ ADC2_INP2_INP_CMP_LO3_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO3_Pos   (6UL)

INP_CMP_LO3 (Bit 6)

◆ ADC2_INP2_INP_CMP_LO4_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO4_Msk   (0x300UL)

INP_CMP_LO4 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO4_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO4_Msk   (0x300UL)

INP_CMP_LO4 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO4_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO4_Pos   (8UL)

INP_CMP_LO4 (Bit 8)

◆ ADC2_INP2_INP_CMP_LO4_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO4_Pos   (8UL)

INP_CMP_LO4 (Bit 8)

◆ ADC2_INP2_INP_CMP_LO5_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO5_Msk   (0xc00UL)

INP_CMP_LO5 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO5_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO5_Msk   (0xc00UL)

INP_CMP_LO5 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO5_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO5_Pos   (10UL)

INP_CMP_LO5 (Bit 10)

◆ ADC2_INP2_INP_CMP_LO5_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO5_Pos   (10UL)

INP_CMP_LO5 (Bit 10)

◆ ADC2_INP2_INP_CMP_LO6_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO6_Msk   (0x3000UL)

INP_CMP_LO6 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO6_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO6_Msk   (0x3000UL)

INP_CMP_LO6 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO6_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO6_Pos   (12UL)

INP_CMP_LO6 (Bit 12)

◆ ADC2_INP2_INP_CMP_LO6_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO6_Pos   (12UL)

INP_CMP_LO6 (Bit 12)

◆ ADC2_INP2_INP_CMP_LO7_Msk [1/2]

#define ADC2_INP2_INP_CMP_LO7_Msk   (0xc000UL)

INP_CMP_LO7 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO7_Msk [2/2]

#define ADC2_INP2_INP_CMP_LO7_Msk   (0xc000UL)

INP_CMP_LO7 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_LO7_Pos [1/2]

#define ADC2_INP2_INP_CMP_LO7_Pos   (14UL)

INP_CMP_LO7 (Bit 14)

◆ ADC2_INP2_INP_CMP_LO7_Pos [2/2]

#define ADC2_INP2_INP_CMP_LO7_Pos   (14UL)

INP_CMP_LO7 (Bit 14)

◆ ADC2_INP2_INP_CMP_UP0_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP0_Msk   (0x30000UL)

INP_CMP_UP0 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP0_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP0_Msk   (0x30000UL)

INP_CMP_UP0 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP0_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP0_Pos   (16UL)

INP_CMP_UP0 (Bit 16)

◆ ADC2_INP2_INP_CMP_UP0_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP0_Pos   (16UL)

INP_CMP_UP0 (Bit 16)

◆ ADC2_INP2_INP_CMP_UP1_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP1_Msk   (0xc0000UL)

INP_CMP_UP1 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP1_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP1_Msk   (0xc0000UL)

INP_CMP_UP1 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP1_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP1_Pos   (18UL)

INP_CMP_UP1 (Bit 18)

◆ ADC2_INP2_INP_CMP_UP1_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP1_Pos   (18UL)

INP_CMP_UP1 (Bit 18)

◆ ADC2_INP2_INP_CMP_UP2_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP2_Msk   (0x300000UL)

INP_CMP_UP2 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP2_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP2_Msk   (0x300000UL)

INP_CMP_UP2 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP2_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP2_Pos   (20UL)

INP_CMP_UP2 (Bit 20)

◆ ADC2_INP2_INP_CMP_UP2_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP2_Pos   (20UL)

INP_CMP_UP2 (Bit 20)

◆ ADC2_INP2_INP_CMP_UP3_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP3_Msk   (0xc00000UL)

INP_CMP_UP3 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP3_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP3_Msk   (0xc00000UL)

INP_CMP_UP3 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP3_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP3_Pos   (22UL)

INP_CMP_UP3 (Bit 22)

◆ ADC2_INP2_INP_CMP_UP3_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP3_Pos   (22UL)

INP_CMP_UP3 (Bit 22)

◆ ADC2_INP2_INP_CMP_UP4_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP4_Msk   (0x3000000UL)

INP_CMP_UP4 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP4_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP4_Msk   (0x3000000UL)

INP_CMP_UP4 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP4_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP4_Pos   (24UL)

INP_CMP_UP4 (Bit 24)

◆ ADC2_INP2_INP_CMP_UP4_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP4_Pos   (24UL)

INP_CMP_UP4 (Bit 24)

◆ ADC2_INP2_INP_CMP_UP5_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP5_Msk   (0xc000000UL)

INP_CMP_UP5 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP5_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP5_Msk   (0xc000000UL)

INP_CMP_UP5 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP5_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP5_Pos   (26UL)

INP_CMP_UP5 (Bit 26)

◆ ADC2_INP2_INP_CMP_UP5_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP5_Pos   (26UL)

INP_CMP_UP5 (Bit 26)

◆ ADC2_INP2_INP_CMP_UP6_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP6_Msk   (0x30000000UL)

INP_CMP_UP6 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP6_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP6_Msk   (0x30000000UL)

INP_CMP_UP6 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP6_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP6_Pos   (28UL)

INP_CMP_UP6 (Bit 28)

◆ ADC2_INP2_INP_CMP_UP6_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP6_Pos   (28UL)

INP_CMP_UP6 (Bit 28)

◆ ADC2_INP2_INP_CMP_UP7_Msk [1/2]

#define ADC2_INP2_INP_CMP_UP7_Msk   (0xc0000000UL)

INP_CMP_UP7 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP7_Msk [2/2]

#define ADC2_INP2_INP_CMP_UP7_Msk   (0xc0000000UL)

INP_CMP_UP7 (Bitfield-Mask: 0x03)

◆ ADC2_INP2_INP_CMP_UP7_Pos [1/2]

#define ADC2_INP2_INP_CMP_UP7_Pos   (30UL)

INP_CMP_UP7 (Bit 30)

◆ ADC2_INP2_INP_CMP_UP7_Pos [2/2]

#define ADC2_INP2_INP_CMP_UP7_Pos   (30UL)

INP_CMP_UP7 (Bit 30)

◆ ADC2_INP3_INP_COLL0_Msk [1/2]

#define ADC2_INP3_INP_COLL0_Msk   (0x300UL)

INP_COLL0 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL0_Msk [2/2]

#define ADC2_INP3_INP_COLL0_Msk   (0x300UL)

INP_COLL0 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL0_Pos [1/2]

#define ADC2_INP3_INP_COLL0_Pos   (8UL)

INP_COLL0 (Bit 8)

◆ ADC2_INP3_INP_COLL0_Pos [2/2]

#define ADC2_INP3_INP_COLL0_Pos   (8UL)

INP_COLL0 (Bit 8)

◆ ADC2_INP3_INP_COLL1_Msk [1/2]

#define ADC2_INP3_INP_COLL1_Msk   (0xc00UL)

INP_COLL1 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL1_Msk [2/2]

#define ADC2_INP3_INP_COLL1_Msk   (0xc00UL)

INP_COLL1 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL1_Pos [1/2]

#define ADC2_INP3_INP_COLL1_Pos   (10UL)

INP_COLL1 (Bit 10)

◆ ADC2_INP3_INP_COLL1_Pos [2/2]

#define ADC2_INP3_INP_COLL1_Pos   (10UL)

INP_COLL1 (Bit 10)

◆ ADC2_INP3_INP_COLL2_Msk [1/2]

#define ADC2_INP3_INP_COLL2_Msk   (0x3000UL)

INP_COLL2 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL2_Msk [2/2]

#define ADC2_INP3_INP_COLL2_Msk   (0x3000UL)

INP_COLL2 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL2_Pos [1/2]

#define ADC2_INP3_INP_COLL2_Pos   (12UL)

INP_COLL2 (Bit 12)

◆ ADC2_INP3_INP_COLL2_Pos [2/2]

#define ADC2_INP3_INP_COLL2_Pos   (12UL)

INP_COLL2 (Bit 12)

◆ ADC2_INP3_INP_COLL3_Msk [1/2]

#define ADC2_INP3_INP_COLL3_Msk   (0xc000UL)

INP_COLL3 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL3_Msk [2/2]

#define ADC2_INP3_INP_COLL3_Msk   (0xc000UL)

INP_COLL3 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_COLL3_Pos [1/2]

#define ADC2_INP3_INP_COLL3_Pos   (14UL)

INP_COLL3 (Bit 14)

◆ ADC2_INP3_INP_COLL3_Pos [2/2]

#define ADC2_INP3_INP_COLL3_Pos   (14UL)

INP_COLL3 (Bit 14)

◆ ADC2_INP3_INP_SQ0_Msk [1/2]

#define ADC2_INP3_INP_SQ0_Msk   (0x3UL)

INP_SQ0 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ0_Msk [2/2]

#define ADC2_INP3_INP_SQ0_Msk   (0x3UL)

INP_SQ0 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ0_Pos [1/2]

#define ADC2_INP3_INP_SQ0_Pos   (0UL)

INP_SQ0 (Bit 0)

◆ ADC2_INP3_INP_SQ0_Pos [2/2]

#define ADC2_INP3_INP_SQ0_Pos   (0UL)

INP_SQ0 (Bit 0)

◆ ADC2_INP3_INP_SQ1_Msk [1/2]

#define ADC2_INP3_INP_SQ1_Msk   (0xcUL)

INP_SQ1 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ1_Msk [2/2]

#define ADC2_INP3_INP_SQ1_Msk   (0xcUL)

INP_SQ1 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ1_Pos [1/2]

#define ADC2_INP3_INP_SQ1_Pos   (2UL)

INP_SQ1 (Bit 2)

◆ ADC2_INP3_INP_SQ1_Pos [2/2]

#define ADC2_INP3_INP_SQ1_Pos   (2UL)

INP_SQ1 (Bit 2)

◆ ADC2_INP3_INP_SQ2_Msk [1/2]

#define ADC2_INP3_INP_SQ2_Msk   (0x30UL)

INP_SQ2 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ2_Msk [2/2]

#define ADC2_INP3_INP_SQ2_Msk   (0x30UL)

INP_SQ2 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ2_Pos [1/2]

#define ADC2_INP3_INP_SQ2_Pos   (4UL)

INP_SQ2 (Bit 4)

◆ ADC2_INP3_INP_SQ2_Pos [2/2]

#define ADC2_INP3_INP_SQ2_Pos   (4UL)

INP_SQ2 (Bit 4)

◆ ADC2_INP3_INP_SQ3_Msk [1/2]

#define ADC2_INP3_INP_SQ3_Msk   (0xc0UL)

INP_SQ3 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ3_Msk [2/2]

#define ADC2_INP3_INP_SQ3_Msk   (0xc0UL)

INP_SQ3 (Bitfield-Mask: 0x03)

◆ ADC2_INP3_INP_SQ3_Pos [1/2]

#define ADC2_INP3_INP_SQ3_Pos   (6UL)

INP_SQ3 (Bit 6)

◆ ADC2_INP3_INP_SQ3_Pos [2/2]

#define ADC2_INP3_INP_SQ3_Pos   (6UL)

INP_SQ3 (Bit 6)

◆ BDRV_CP_CTRL_CP_1STAGE_Msk [1/2]

#define BDRV_CP_CTRL_CP_1STAGE_Msk   (0x10000UL)

CP_1STAGE (Bitfield-Mask: 0x01)

◆ BDRV_CP_CTRL_CP_1STAGE_Msk [2/2]

#define BDRV_CP_CTRL_CP_1STAGE_Msk   (0x10000UL)

CP_1STAGE (Bitfield-Mask: 0x01)

◆ BDRV_CP_CTRL_CP_1STAGE_Pos [1/2]

#define BDRV_CP_CTRL_CP_1STAGE_Pos   (16UL)

CP_1STAGE (Bit 16)

◆ BDRV_CP_CTRL_CP_1STAGE_Pos [2/2]

#define BDRV_CP_CTRL_CP_1STAGE_Pos   (16UL)

CP_1STAGE (Bit 16)

◆ BDRV_CP_CTRL_CP_RDY_EN_Msk [1/2]

#define BDRV_CP_CTRL_CP_RDY_EN_Msk   (0x4UL)

CP_RDY_EN (Bitfield-Mask: 0x01)

◆ BDRV_CP_CTRL_CP_RDY_EN_Msk [2/2]

#define BDRV_CP_CTRL_CP_RDY_EN_Msk   (0x4UL)

CP_RDY_EN (Bitfield-Mask: 0x01)

◆ BDRV_CP_CTRL_CP_RDY_EN_Pos [1/2]

#define BDRV_CP_CTRL_CP_RDY_EN_Pos   (2UL)

CP_RDY_EN (Bit 2)

◆ BDRV_CP_CTRL_CP_RDY_EN_Pos [2/2]

#define BDRV_CP_CTRL_CP_RDY_EN_Pos   (2UL)

CP_RDY_EN (Bit 2)

◆ CANNODE_CAN_NIPR0_ALINP_Msk [1/2]

#define CANNODE_CAN_NIPR0_ALINP_Msk   (0xfUL)

ALINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_ALINP_Msk [2/2]

#define CANNODE_CAN_NIPR0_ALINP_Msk   (0xfUL)

ALINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_ALINP_Pos [1/2]

#define CANNODE_CAN_NIPR0_ALINP_Pos   (0UL)

ALINP (Bit 0)

◆ CANNODE_CAN_NIPR0_ALINP_Pos [2/2]

#define CANNODE_CAN_NIPR0_ALINP_Pos   (0UL)

ALINP (Bit 0)

◆ CANNODE_CAN_NIPR0_CFCINP_Msk [1/2]

#define CANNODE_CAN_NIPR0_CFCINP_Msk   (0xf000UL)

CFCINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_CFCINP_Msk [2/2]

#define CANNODE_CAN_NIPR0_CFCINP_Msk   (0xf000UL)

CFCINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_CFCINP_Pos [1/2]

#define CANNODE_CAN_NIPR0_CFCINP_Pos   (12UL)

CFCINP (Bit 12)

◆ CANNODE_CAN_NIPR0_CFCINP_Pos [2/2]

#define CANNODE_CAN_NIPR0_CFCINP_Pos   (12UL)

CFCINP (Bit 12)

◆ CANNODE_CAN_NIPR0_LECINP_Msk [1/2]

#define CANNODE_CAN_NIPR0_LECINP_Msk   (0xf0UL)

LECINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_LECINP_Msk [2/2]

#define CANNODE_CAN_NIPR0_LECINP_Msk   (0xf0UL)

LECINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_LECINP_Pos [1/2]

#define CANNODE_CAN_NIPR0_LECINP_Pos   (4UL)

LECINP (Bit 4)

◆ CANNODE_CAN_NIPR0_LECINP_Pos [2/2]

#define CANNODE_CAN_NIPR0_LECINP_Pos   (4UL)

LECINP (Bit 4)

◆ CANNODE_CAN_NIPR0_TRINP_Msk [1/2]

#define CANNODE_CAN_NIPR0_TRINP_Msk   (0xf00UL)

TRINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_TRINP_Msk [2/2]

#define CANNODE_CAN_NIPR0_TRINP_Msk   (0xf00UL)

TRINP (Bitfield-Mask: 0x0f)

◆ CANNODE_CAN_NIPR0_TRINP_Pos [1/2]

#define CANNODE_CAN_NIPR0_TRINP_Pos   (8UL)

TRINP (Bit 8)

◆ CANNODE_CAN_NIPR0_TRINP_Pos [2/2]

#define CANNODE_CAN_NIPR0_TRINP_Pos   (8UL)

TRINP (Bit 8)

◆ CANTRX_CTRL_EN_Msk [1/2]

#define CANTRX_CTRL_EN_Msk   (0x1UL)

EN (Bitfield-Mask: 0x01)

◆ CANTRX_CTRL_EN_Msk [2/2]

#define CANTRX_CTRL_EN_Msk   (0x1UL)

EN (Bitfield-Mask: 0x01)

◆ CANTRX_CTRL_EN_Pos [1/2]

#define CANTRX_CTRL_EN_Pos   (0UL)

EN (Bit 0)

◆ CANTRX_CTRL_EN_Pos [2/2]

#define CANTRX_CTRL_EN_Pos   (0UL)

EN (Bit 0)

◆ CCU7_CMPSTAT_CCPOS0_Msk [1/2]

#define CCU7_CMPSTAT_CCPOS0_Msk   (0x8UL)

CCPOS0 (Bitfield-Mask: 0x01)

◆ CCU7_CMPSTAT_CCPOS0_Msk [2/2]

#define CCU7_CMPSTAT_CCPOS0_Msk   (0x8UL)

CCPOS0 (Bitfield-Mask: 0x01)

◆ CCU7_CMPSTAT_CCPOS0_Pos [1/2]

#define CCU7_CMPSTAT_CCPOS0_Pos   (3UL)

CCPOS0 (Bit 3)

◆ CCU7_CMPSTAT_CCPOS0_Pos [2/2]

#define CCU7_CMPSTAT_CCPOS0_Pos   (3UL)

CCPOS0 (Bit 3)

◆ CCU7_CMPSTAT_CCPOS1_Msk [1/2]

#define CCU7_CMPSTAT_CCPOS1_Msk   (0x10UL)

CCPOS1 (Bitfield-Mask: 0x01)

◆ CCU7_CMPSTAT_CCPOS1_Msk [2/2]

#define CCU7_CMPSTAT_CCPOS1_Msk   (0x10UL)

CCPOS1 (Bitfield-Mask: 0x01)

◆ CCU7_CMPSTAT_CCPOS1_Pos [1/2]

#define CCU7_CMPSTAT_CCPOS1_Pos   (4UL)

CCPOS1 (Bit 4)

◆ CCU7_CMPSTAT_CCPOS1_Pos [2/2]

#define CCU7_CMPSTAT_CCPOS1_Pos   (4UL)

CCPOS1 (Bit 4)

◆ CCU7_CMPSTAT_CCPOS2_Msk [1/2]

#define CCU7_CMPSTAT_CCPOS2_Msk   (0x20UL)

CCPOS2 (Bitfield-Mask: 0x01)

◆ CCU7_CMPSTAT_CCPOS2_Msk [2/2]

#define CCU7_CMPSTAT_CCPOS2_Msk   (0x20UL)

CCPOS2 (Bitfield-Mask: 0x01)

◆ CCU7_CMPSTAT_CCPOS2_Pos [1/2]

#define CCU7_CMPSTAT_CCPOS2_Pos   (5UL)

CCPOS2 (Bit 5)

◆ CCU7_CMPSTAT_CCPOS2_Pos [2/2]

#define CCU7_CMPSTAT_CCPOS2_Pos   (5UL)

CCPOS2 (Bit 5)

◆ CCU7_INP_2_INPCC70B_Msk [1/2]

#define CCU7_INP_2_INPCC70B_Msk   (0x3UL)

INPCC70B (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPCC70B_Msk [2/2]

#define CCU7_INP_2_INPCC70B_Msk   (0x3UL)

INPCC70B (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPCC70B_Pos [1/2]

#define CCU7_INP_2_INPCC70B_Pos   (0UL)

INPCC70B (Bit 0)

◆ CCU7_INP_2_INPCC70B_Pos [2/2]

#define CCU7_INP_2_INPCC70B_Pos   (0UL)

INPCC70B (Bit 0)

◆ CCU7_INP_2_INPCC71B_Msk [1/2]

#define CCU7_INP_2_INPCC71B_Msk   (0xcUL)

INPCC71B (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPCC71B_Msk [2/2]

#define CCU7_INP_2_INPCC71B_Msk   (0xcUL)

INPCC71B (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPCC71B_Pos [1/2]

#define CCU7_INP_2_INPCC71B_Pos   (2UL)

INPCC71B (Bit 2)

◆ CCU7_INP_2_INPCC71B_Pos [2/2]

#define CCU7_INP_2_INPCC71B_Pos   (2UL)

INPCC71B (Bit 2)

◆ CCU7_INP_2_INPCC72B_Msk [1/2]

#define CCU7_INP_2_INPCC72B_Msk   (0x30UL)

INPCC72B (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPCC72B_Msk [2/2]

#define CCU7_INP_2_INPCC72B_Msk   (0x30UL)

INPCC72B (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPCC72B_Pos [1/2]

#define CCU7_INP_2_INPCC72B_Pos   (4UL)

INPCC72B (Bit 4)

◆ CCU7_INP_2_INPCC72B_Pos [2/2]

#define CCU7_INP_2_INPCC72B_Pos   (4UL)

INPCC72B (Bit 4)

◆ CCU7_INP_2_INPT14_Msk [1/2]

#define CCU7_INP_2_INPT14_Msk   (0x300UL)

INPT14 (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPT14_Msk [2/2]

#define CCU7_INP_2_INPT14_Msk   (0x300UL)

INPT14 (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPT14_Pos [1/2]

#define CCU7_INP_2_INPT14_Pos   (8UL)

INPT14 (Bit 8)

◆ CCU7_INP_2_INPT14_Pos [2/2]

#define CCU7_INP_2_INPT14_Pos   (8UL)

INPT14 (Bit 8)

◆ CCU7_INP_2_INPT15_Msk [1/2]

#define CCU7_INP_2_INPT15_Msk   (0xc00UL)

INPT15 (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPT15_Msk [2/2]

#define CCU7_INP_2_INPT15_Msk   (0xc00UL)

INPT15 (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPT15_Pos [1/2]

#define CCU7_INP_2_INPT15_Pos   (10UL)

INPT15 (Bit 10)

◆ CCU7_INP_2_INPT15_Pos [2/2]

#define CCU7_INP_2_INPT15_Pos   (10UL)

INPT15 (Bit 10)

◆ CCU7_INP_2_INPT16_Msk [1/2]

#define CCU7_INP_2_INPT16_Msk   (0x3000UL)

INPT16 (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPT16_Msk [2/2]

#define CCU7_INP_2_INPT16_Msk   (0x3000UL)

INPT16 (Bitfield-Mask: 0x03)

◆ CCU7_INP_2_INPT16_Pos [1/2]

#define CCU7_INP_2_INPT16_Pos   (12UL)

INPT16 (Bit 12)

◆ CCU7_INP_2_INPT16_Pos [2/2]

#define CCU7_INP_2_INPT16_Pos   (12UL)

INPT16 (Bit 12)

◆ CCU7_INP_INPCC70_Msk [1/2]

#define CCU7_INP_INPCC70_Msk   (0x3UL)

INPCC70 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCC70_Msk [2/2]

#define CCU7_INP_INPCC70_Msk   (0x3UL)

INPCC70 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCC70_Pos [1/2]

#define CCU7_INP_INPCC70_Pos   (0UL)

INPCC70 (Bit 0)

◆ CCU7_INP_INPCC70_Pos [2/2]

#define CCU7_INP_INPCC70_Pos   (0UL)

INPCC70 (Bit 0)

◆ CCU7_INP_INPCC71_Msk [1/2]

#define CCU7_INP_INPCC71_Msk   (0xcUL)

INPCC71 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCC71_Msk [2/2]

#define CCU7_INP_INPCC71_Msk   (0xcUL)

INPCC71 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCC71_Pos [1/2]

#define CCU7_INP_INPCC71_Pos   (2UL)

INPCC71 (Bit 2)

◆ CCU7_INP_INPCC71_Pos [2/2]

#define CCU7_INP_INPCC71_Pos   (2UL)

INPCC71 (Bit 2)

◆ CCU7_INP_INPCC72_Msk [1/2]

#define CCU7_INP_INPCC72_Msk   (0x30UL)

INPCC72 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCC72_Msk [2/2]

#define CCU7_INP_INPCC72_Msk   (0x30UL)

INPCC72 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCC72_Pos [1/2]

#define CCU7_INP_INPCC72_Pos   (4UL)

INPCC72 (Bit 4)

◆ CCU7_INP_INPCC72_Pos [2/2]

#define CCU7_INP_INPCC72_Pos   (4UL)

INPCC72 (Bit 4)

◆ CCU7_INP_INPCHE_Msk [1/2]

#define CCU7_INP_INPCHE_Msk   (0xc0UL)

INPCHE (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCHE_Msk [2/2]

#define CCU7_INP_INPCHE_Msk   (0xc0UL)

INPCHE (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPCHE_Pos [1/2]

#define CCU7_INP_INPCHE_Pos   (6UL)

INPCHE (Bit 6)

◆ CCU7_INP_INPCHE_Pos [2/2]

#define CCU7_INP_INPCHE_Pos   (6UL)

INPCHE (Bit 6)

◆ CCU7_INP_INPERR_Msk [1/2]

#define CCU7_INP_INPERR_Msk   (0x300UL)

INPERR (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPERR_Msk [2/2]

#define CCU7_INP_INPERR_Msk   (0x300UL)

INPERR (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPERR_Pos [1/2]

#define CCU7_INP_INPERR_Pos   (8UL)

INPERR (Bit 8)

◆ CCU7_INP_INPERR_Pos [2/2]

#define CCU7_INP_INPERR_Pos   (8UL)

INPERR (Bit 8)

◆ CCU7_INP_INPT12_Msk [1/2]

#define CCU7_INP_INPT12_Msk   (0xc00UL)

INPT12 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPT12_Msk [2/2]

#define CCU7_INP_INPT12_Msk   (0xc00UL)

INPT12 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPT12_Pos [1/2]

#define CCU7_INP_INPT12_Pos   (10UL)

INPT12 (Bit 10)

◆ CCU7_INP_INPT12_Pos [2/2]

#define CCU7_INP_INPT12_Pos   (10UL)

INPT12 (Bit 10)

◆ CCU7_INP_INPT13_Msk [1/2]

#define CCU7_INP_INPT13_Msk   (0x3000UL)

INPT13 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPT13_Msk [2/2]

#define CCU7_INP_INPT13_Msk   (0x3000UL)

INPT13 (Bitfield-Mask: 0x03)

◆ CCU7_INP_INPT13_Pos [1/2]

#define CCU7_INP_INPT13_Pos   (12UL)

INPT13 (Bit 12)

◆ CCU7_INP_INPT13_Pos [2/2]

#define CCU7_INP_INPT13_Pos   (12UL)

INPT13 (Bit 12)

◆ CCU7_LI_INPLBE_Msk [1/2]

#define CCU7_LI_INPLBE_Msk   (0xc000UL)

INPLBE (Bitfield-Mask: 0x03)

◆ CCU7_LI_INPLBE_Msk [2/2]

#define CCU7_LI_INPLBE_Msk   (0xc000UL)

INPLBE (Bitfield-Mask: 0x03)

◆ CCU7_LI_INPLBE_Pos [1/2]

#define CCU7_LI_INPLBE_Pos   (14UL)

INPLBE (Bit 14)

◆ CCU7_LI_INPLBE_Pos [2/2]

#define CCU7_LI_INPLBE_Pos   (14UL)

INPLBE (Bit 14)

◆ CPU_NVIC_ISER_IRQEN0_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN0_Msk   (0x1UL)

IRQEN0 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN0_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN0_Msk   (0x1UL)

IRQEN0 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN0_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN0_Pos   (0UL)

IRQEN0 (Bit 0)

◆ CPU_NVIC_ISER_IRQEN0_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN0_Pos   (0UL)

IRQEN0 (Bit 0)

◆ CPU_NVIC_ISER_IRQEN10_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN10_Msk   (0x400UL)

IRQEN10 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN10_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN10_Msk   (0x400UL)

IRQEN10 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN10_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN10_Pos   (10UL)

IRQEN10 (Bit 10)

◆ CPU_NVIC_ISER_IRQEN10_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN10_Pos   (10UL)

IRQEN10 (Bit 10)

◆ CPU_NVIC_ISER_IRQEN11_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN11_Msk   (0x800UL)

IRQEN11 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN11_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN11_Msk   (0x800UL)

IRQEN11 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN11_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN11_Pos   (11UL)

IRQEN11 (Bit 11)

◆ CPU_NVIC_ISER_IRQEN11_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN11_Pos   (11UL)

IRQEN11 (Bit 11)

◆ CPU_NVIC_ISER_IRQEN12_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN12_Msk   (0x1000UL)

IRQEN12 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN12_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN12_Msk   (0x1000UL)

IRQEN12 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN12_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN12_Pos   (12UL)

IRQEN12 (Bit 12)

◆ CPU_NVIC_ISER_IRQEN12_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN12_Pos   (12UL)

IRQEN12 (Bit 12)

◆ CPU_NVIC_ISER_IRQEN13_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN13_Msk   (0x2000UL)

IRQEN13 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN13_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN13_Msk   (0x2000UL)

IRQEN13 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN13_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN13_Pos   (13UL)

IRQEN13 (Bit 13)

◆ CPU_NVIC_ISER_IRQEN13_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN13_Pos   (13UL)

IRQEN13 (Bit 13)

◆ CPU_NVIC_ISER_IRQEN14_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN14_Msk   (0x4000UL)

IRQEN14 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN14_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN14_Msk   (0x4000UL)

IRQEN14 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN14_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN14_Pos   (14UL)

IRQEN14 (Bit 14)

◆ CPU_NVIC_ISER_IRQEN14_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN14_Pos   (14UL)

IRQEN14 (Bit 14)

◆ CPU_NVIC_ISER_IRQEN15_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN15_Msk   (0x8000UL)

IRQEN15 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN15_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN15_Msk   (0x8000UL)

IRQEN15 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN15_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN15_Pos   (15UL)

IRQEN15 (Bit 15)

◆ CPU_NVIC_ISER_IRQEN15_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN15_Pos   (15UL)

IRQEN15 (Bit 15)

◆ CPU_NVIC_ISER_IRQEN16_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN16_Msk   (0x10000UL)

IRQEN16 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN16_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN16_Msk   (0x10000UL)

IRQEN16 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN16_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN16_Pos   (16UL)

IRQEN16 (Bit 16)

◆ CPU_NVIC_ISER_IRQEN16_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN16_Pos   (16UL)

IRQEN16 (Bit 16)

◆ CPU_NVIC_ISER_IRQEN17_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN17_Msk   (0x20000UL)

IRQEN17 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN17_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN17_Msk   (0x20000UL)

IRQEN17 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN17_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN17_Pos   (17UL)

IRQEN17 (Bit 17)

◆ CPU_NVIC_ISER_IRQEN17_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN17_Pos   (17UL)

IRQEN17 (Bit 17)

◆ CPU_NVIC_ISER_IRQEN18_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN18_Msk   (0x40000UL)

IRQEN18 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN18_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN18_Msk   (0x40000UL)

IRQEN18 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN18_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN18_Pos   (18UL)

IRQEN18 (Bit 18)

◆ CPU_NVIC_ISER_IRQEN18_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN18_Pos   (18UL)

IRQEN18 (Bit 18)

◆ CPU_NVIC_ISER_IRQEN19_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN19_Msk   (0x80000UL)

IRQEN19 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN19_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN19_Msk   (0x80000UL)

IRQEN19 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN19_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN19_Pos   (19UL)

IRQEN19 (Bit 19)

◆ CPU_NVIC_ISER_IRQEN19_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN19_Pos   (19UL)

IRQEN19 (Bit 19)

◆ CPU_NVIC_ISER_IRQEN1_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN1_Msk   (0x2UL)

IRQEN1 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN1_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN1_Msk   (0x2UL)

IRQEN1 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN1_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN1_Pos   (1UL)

IRQEN1 (Bit 1)

◆ CPU_NVIC_ISER_IRQEN1_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN1_Pos   (1UL)

IRQEN1 (Bit 1)

◆ CPU_NVIC_ISER_IRQEN20_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN20_Msk   (0x100000UL)

IRQEN20 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN20_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN20_Msk   (0x100000UL)

IRQEN20 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN20_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN20_Pos   (20UL)

IRQEN20 (Bit 20)

◆ CPU_NVIC_ISER_IRQEN20_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN20_Pos   (20UL)

IRQEN20 (Bit 20)

◆ CPU_NVIC_ISER_IRQEN21_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN21_Msk   (0x200000UL)

IRQEN21 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN21_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN21_Msk   (0x200000UL)

IRQEN21 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN21_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN21_Pos   (21UL)

IRQEN21 (Bit 21)

◆ CPU_NVIC_ISER_IRQEN21_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN21_Pos   (21UL)

IRQEN21 (Bit 21)

◆ CPU_NVIC_ISER_IRQEN22_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN22_Msk   (0x400000UL)

IRQEN22 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN22_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN22_Msk   (0x400000UL)

IRQEN22 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN22_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN22_Pos   (22UL)

IRQEN22 (Bit 22)

◆ CPU_NVIC_ISER_IRQEN22_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN22_Pos   (22UL)

IRQEN22 (Bit 22)

◆ CPU_NVIC_ISER_IRQEN23_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN23_Msk   (0x800000UL)

IRQEN23 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN23_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN23_Msk   (0x800000UL)

IRQEN23 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN23_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN23_Pos   (23UL)

IRQEN23 (Bit 23)

◆ CPU_NVIC_ISER_IRQEN23_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN23_Pos   (23UL)

IRQEN23 (Bit 23)

◆ CPU_NVIC_ISER_IRQEN24_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN24_Msk   (0x1000000UL)

IRQEN24 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN24_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN24_Msk   (0x1000000UL)

IRQEN24 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN24_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN24_Pos   (24UL)

IRQEN24 (Bit 24)

◆ CPU_NVIC_ISER_IRQEN24_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN24_Pos   (24UL)

IRQEN24 (Bit 24)

◆ CPU_NVIC_ISER_IRQEN25_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN25_Msk   (0x2000000UL)

IRQEN25 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN25_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN25_Msk   (0x2000000UL)

IRQEN25 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN25_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN25_Pos   (25UL)

IRQEN25 (Bit 25)

◆ CPU_NVIC_ISER_IRQEN25_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN25_Pos   (25UL)

IRQEN25 (Bit 25)

◆ CPU_NVIC_ISER_IRQEN26_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN26_Msk   (0x4000000UL)

IRQEN26 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN26_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN26_Msk   (0x4000000UL)

IRQEN26 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN26_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN26_Pos   (26UL)

IRQEN26 (Bit 26)

◆ CPU_NVIC_ISER_IRQEN26_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN26_Pos   (26UL)

IRQEN26 (Bit 26)

◆ CPU_NVIC_ISER_IRQEN27_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN27_Msk   (0x8000000UL)

IRQEN27 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN27_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN27_Msk   (0x8000000UL)

IRQEN27 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN27_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN27_Pos   (27UL)

IRQEN27 (Bit 27)

◆ CPU_NVIC_ISER_IRQEN27_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN27_Pos   (27UL)

IRQEN27 (Bit 27)

◆ CPU_NVIC_ISER_IRQEN28_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN28_Msk   (0x10000000UL)

IRQEN28 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN28_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN28_Msk   (0x10000000UL)

IRQEN28 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN28_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN28_Pos   (28UL)

IRQEN28 (Bit 28)

◆ CPU_NVIC_ISER_IRQEN28_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN28_Pos   (28UL)

IRQEN28 (Bit 28)

◆ CPU_NVIC_ISER_IRQEN29_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN29_Msk   (0x20000000UL)

IRQEN29 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN29_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN29_Msk   (0x20000000UL)

IRQEN29 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN29_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN29_Pos   (29UL)

IRQEN29 (Bit 29)

◆ CPU_NVIC_ISER_IRQEN29_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN29_Pos   (29UL)

IRQEN29 (Bit 29)

◆ CPU_NVIC_ISER_IRQEN2_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN2_Msk   (0x4UL)

IRQEN2 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN2_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN2_Msk   (0x4UL)

IRQEN2 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN2_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN2_Pos   (2UL)

IRQEN2 (Bit 2)

◆ CPU_NVIC_ISER_IRQEN2_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN2_Pos   (2UL)

IRQEN2 (Bit 2)

◆ CPU_NVIC_ISER_IRQEN30_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN30_Msk   (0x40000000UL)

IRQEN30 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN30_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN30_Msk   (0x40000000UL)

IRQEN30 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN30_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN30_Pos   (30UL)

IRQEN30 (Bit 30)

◆ CPU_NVIC_ISER_IRQEN30_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN30_Pos   (30UL)

IRQEN30 (Bit 30)

◆ CPU_NVIC_ISER_IRQEN31_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN31_Msk   (0x80000000UL)

IRQEN31 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN31_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN31_Msk   (0x80000000UL)

IRQEN31 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN31_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN31_Pos   (31UL)

IRQEN31 (Bit 31)

◆ CPU_NVIC_ISER_IRQEN31_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN31_Pos   (31UL)

IRQEN31 (Bit 31)

◆ CPU_NVIC_ISER_IRQEN3_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN3_Msk   (0x8UL)

IRQEN3 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN3_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN3_Msk   (0x8UL)

IRQEN3 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN3_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN3_Pos   (3UL)

IRQEN3 (Bit 3)

◆ CPU_NVIC_ISER_IRQEN3_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN3_Pos   (3UL)

IRQEN3 (Bit 3)

◆ CPU_NVIC_ISER_IRQEN4_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN4_Msk   (0x10UL)

IRQEN4 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN4_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN4_Msk   (0x10UL)

IRQEN4 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN4_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN4_Pos   (4UL)

IRQEN4 (Bit 4)

◆ CPU_NVIC_ISER_IRQEN4_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN4_Pos   (4UL)

IRQEN4 (Bit 4)

◆ CPU_NVIC_ISER_IRQEN5_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN5_Msk   (0x20UL)

IRQEN5 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN5_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN5_Msk   (0x20UL)

IRQEN5 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN5_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN5_Pos   (5UL)

IRQEN5 (Bit 5)

◆ CPU_NVIC_ISER_IRQEN5_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN5_Pos   (5UL)

IRQEN5 (Bit 5)

◆ CPU_NVIC_ISER_IRQEN6_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN6_Msk   (0x40UL)

IRQEN6 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN6_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN6_Msk   (0x40UL)

IRQEN6 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN6_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN6_Pos   (6UL)

IRQEN6 (Bit 6)

◆ CPU_NVIC_ISER_IRQEN6_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN6_Pos   (6UL)

IRQEN6 (Bit 6)

◆ CPU_NVIC_ISER_IRQEN7_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN7_Msk   (0x80UL)

IRQEN7 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN7_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN7_Msk   (0x80UL)

IRQEN7 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN7_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN7_Pos   (7UL)

IRQEN7 (Bit 7)

◆ CPU_NVIC_ISER_IRQEN7_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN7_Pos   (7UL)

IRQEN7 (Bit 7)

◆ CPU_NVIC_ISER_IRQEN8_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN8_Msk   (0x100UL)

IRQEN8 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN8_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN8_Msk   (0x100UL)

IRQEN8 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN8_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN8_Pos   (8UL)

IRQEN8 (Bit 8)

◆ CPU_NVIC_ISER_IRQEN8_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN8_Pos   (8UL)

IRQEN8 (Bit 8)

◆ CPU_NVIC_ISER_IRQEN9_Msk [1/2]

#define CPU_NVIC_ISER_IRQEN9_Msk   (0x200UL)

IRQEN9 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN9_Msk [2/2]

#define CPU_NVIC_ISER_IRQEN9_Msk   (0x200UL)

IRQEN9 (Bitfield-Mask: 0x01)

◆ CPU_NVIC_ISER_IRQEN9_Pos [1/2]

#define CPU_NVIC_ISER_IRQEN9_Pos   (9UL)

IRQEN9 (Bit 9)

◆ CPU_NVIC_ISER_IRQEN9_Pos [2/2]

#define CPU_NVIC_ISER_IRQEN9_Pos   (9UL)

IRQEN9 (Bit 9)

◆ CSACSC_CTRL1_CSAC_EN_Msk [1/2]

#define CSACSC_CTRL1_CSAC_EN_Msk   (0x1UL)

CSAC_EN (Bitfield-Mask: 0x01)

◆ CSACSC_CTRL1_CSAC_EN_Msk [2/2]

#define CSACSC_CTRL1_CSAC_EN_Msk   (0x1UL)

CSAC_EN (Bitfield-Mask: 0x01)

◆ CSACSC_CTRL1_CSAC_EN_Pos [1/2]

#define CSACSC_CTRL1_CSAC_EN_Pos   (0UL)

CSAC_EN (Bit 0)

◆ CSACSC_CTRL1_CSAC_EN_Pos [2/2]

#define CSACSC_CTRL1_CSAC_EN_Pos   (0UL)

CSAC_EN (Bit 0)

◆ GPIO_P0_OMR_PS0_Msk [1/2]

#define GPIO_P0_OMR_PS0_Msk   (0x1UL)

PS0 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS0_Msk [2/2]

#define GPIO_P0_OMR_PS0_Msk   (0x1UL)

PS0 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS0_Pos [1/2]

#define GPIO_P0_OMR_PS0_Pos   (0UL)

PS0 (Bit 0)

◆ GPIO_P0_OMR_PS0_Pos [2/2]

#define GPIO_P0_OMR_PS0_Pos   (0UL)

PS0 (Bit 0)

◆ GPIO_P0_OMR_PS10_Msk [1/2]

#define GPIO_P0_OMR_PS10_Msk   (0x400UL)

PS10 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS10_Msk [2/2]

#define GPIO_P0_OMR_PS10_Msk   (0x400UL)

PS10 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS10_Pos [1/2]

#define GPIO_P0_OMR_PS10_Pos   (10UL)

PS10 (Bit 10)

◆ GPIO_P0_OMR_PS10_Pos [2/2]

#define GPIO_P0_OMR_PS10_Pos   (10UL)

PS10 (Bit 10)

◆ GPIO_P0_OMR_PS1_Msk [1/2]

#define GPIO_P0_OMR_PS1_Msk   (0x2UL)

PS1 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS1_Msk [2/2]

#define GPIO_P0_OMR_PS1_Msk   (0x2UL)

PS1 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS1_Pos [1/2]

#define GPIO_P0_OMR_PS1_Pos   (1UL)

PS1 (Bit 1)

◆ GPIO_P0_OMR_PS1_Pos [2/2]

#define GPIO_P0_OMR_PS1_Pos   (1UL)

PS1 (Bit 1)

◆ GPIO_P0_OMR_PS2_Msk [1/2]

#define GPIO_P0_OMR_PS2_Msk   (0x4UL)

PS2 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS2_Msk [2/2]

#define GPIO_P0_OMR_PS2_Msk   (0x4UL)

PS2 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS2_Pos [1/2]

#define GPIO_P0_OMR_PS2_Pos   (2UL)

PS2 (Bit 2)

◆ GPIO_P0_OMR_PS2_Pos [2/2]

#define GPIO_P0_OMR_PS2_Pos   (2UL)

PS2 (Bit 2)

◆ GPIO_P0_OMR_PS3_Msk [1/2]

#define GPIO_P0_OMR_PS3_Msk   (0x8UL)

PS3 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS3_Msk [2/2]

#define GPIO_P0_OMR_PS3_Msk   (0x8UL)

PS3 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS3_Pos [1/2]

#define GPIO_P0_OMR_PS3_Pos   (3UL)

PS3 (Bit 3)

◆ GPIO_P0_OMR_PS3_Pos [2/2]

#define GPIO_P0_OMR_PS3_Pos   (3UL)

PS3 (Bit 3)

◆ GPIO_P0_OMR_PS4_Msk [1/2]

#define GPIO_P0_OMR_PS4_Msk   (0x10UL)

PS4 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS4_Msk [2/2]

#define GPIO_P0_OMR_PS4_Msk   (0x10UL)

PS4 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS4_Pos [1/2]

#define GPIO_P0_OMR_PS4_Pos   (4UL)

PS4 (Bit 4)

◆ GPIO_P0_OMR_PS4_Pos [2/2]

#define GPIO_P0_OMR_PS4_Pos   (4UL)

PS4 (Bit 4)

◆ GPIO_P0_OMR_PS5_Msk [1/2]

#define GPIO_P0_OMR_PS5_Msk   (0x20UL)

PS5 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS5_Msk [2/2]

#define GPIO_P0_OMR_PS5_Msk   (0x20UL)

PS5 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS5_Pos [1/2]

#define GPIO_P0_OMR_PS5_Pos   (5UL)

PS5 (Bit 5)

◆ GPIO_P0_OMR_PS5_Pos [2/2]

#define GPIO_P0_OMR_PS5_Pos   (5UL)

PS5 (Bit 5)

◆ GPIO_P0_OMR_PS6_Msk [1/2]

#define GPIO_P0_OMR_PS6_Msk   (0x40UL)

PS6 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS6_Msk [2/2]

#define GPIO_P0_OMR_PS6_Msk   (0x40UL)

PS6 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS6_Pos [1/2]

#define GPIO_P0_OMR_PS6_Pos   (6UL)

PS6 (Bit 6)

◆ GPIO_P0_OMR_PS6_Pos [2/2]

#define GPIO_P0_OMR_PS6_Pos   (6UL)

PS6 (Bit 6)

◆ GPIO_P0_OMR_PS7_Msk [1/2]

#define GPIO_P0_OMR_PS7_Msk   (0x80UL)

PS7 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS7_Msk [2/2]

#define GPIO_P0_OMR_PS7_Msk   (0x80UL)

PS7 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS7_Pos [1/2]

#define GPIO_P0_OMR_PS7_Pos   (7UL)

PS7 (Bit 7)

◆ GPIO_P0_OMR_PS7_Pos [2/2]

#define GPIO_P0_OMR_PS7_Pos   (7UL)

PS7 (Bit 7)

◆ GPIO_P0_OMR_PS8_Msk [1/2]

#define GPIO_P0_OMR_PS8_Msk   (0x100UL)

PS8 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS8_Msk [2/2]

#define GPIO_P0_OMR_PS8_Msk   (0x100UL)

PS8 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS8_Pos [1/2]

#define GPIO_P0_OMR_PS8_Pos   (8UL)

PS8 (Bit 8)

◆ GPIO_P0_OMR_PS8_Pos [2/2]

#define GPIO_P0_OMR_PS8_Pos   (8UL)

PS8 (Bit 8)

◆ GPIO_P0_OMR_PS9_Msk [1/2]

#define GPIO_P0_OMR_PS9_Msk   (0x200UL)

PS9 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS9_Msk [2/2]

#define GPIO_P0_OMR_PS9_Msk   (0x200UL)

PS9 (Bitfield-Mask: 0x01)

◆ GPIO_P0_OMR_PS9_Pos [1/2]

#define GPIO_P0_OMR_PS9_Pos   (9UL)

PS9 (Bit 9)

◆ GPIO_P0_OMR_PS9_Pos [2/2]

#define GPIO_P0_OMR_PS9_Pos   (9UL)

PS9 (Bit 9)

◆ GPIO_P1_OMR_PS0_Msk [1/2]

#define GPIO_P1_OMR_PS0_Msk   (0x1UL)

PS0 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS0_Msk [2/2]

#define GPIO_P1_OMR_PS0_Msk   (0x1UL)

PS0 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS0_Pos [1/2]

#define GPIO_P1_OMR_PS0_Pos   (0UL)

PS0 (Bit 0)

◆ GPIO_P1_OMR_PS0_Pos [2/2]

#define GPIO_P1_OMR_PS0_Pos   (0UL)

PS0 (Bit 0)

◆ GPIO_P1_OMR_PS1_Msk [1/2]

#define GPIO_P1_OMR_PS1_Msk   (0x2UL)

PS1 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS1_Msk [2/2]

#define GPIO_P1_OMR_PS1_Msk   (0x2UL)

PS1 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS1_Pos [1/2]

#define GPIO_P1_OMR_PS1_Pos   (1UL)

PS1 (Bit 1)

◆ GPIO_P1_OMR_PS1_Pos [2/2]

#define GPIO_P1_OMR_PS1_Pos   (1UL)

PS1 (Bit 1)

◆ GPIO_P1_OMR_PS2_Msk [1/2]

#define GPIO_P1_OMR_PS2_Msk   (0x4UL)

PS2 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS2_Msk [2/2]

#define GPIO_P1_OMR_PS2_Msk   (0x4UL)

PS2 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS2_Pos [1/2]

#define GPIO_P1_OMR_PS2_Pos   (2UL)

PS2 (Bit 2)

◆ GPIO_P1_OMR_PS2_Pos [2/2]

#define GPIO_P1_OMR_PS2_Pos   (2UL)

PS2 (Bit 2)

◆ GPIO_P1_OMR_PS3_Msk [1/2]

#define GPIO_P1_OMR_PS3_Msk   (0x8UL)

PS3 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS3_Msk [2/2]

#define GPIO_P1_OMR_PS3_Msk   (0x8UL)

PS3 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS3_Pos [1/2]

#define GPIO_P1_OMR_PS3_Pos   (3UL)

PS3 (Bit 3)

◆ GPIO_P1_OMR_PS3_Pos [2/2]

#define GPIO_P1_OMR_PS3_Pos   (3UL)

PS3 (Bit 3)

◆ GPIO_P1_OMR_PS4_Msk [1/2]

#define GPIO_P1_OMR_PS4_Msk   (0x10UL)

PS4 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS4_Msk [2/2]

#define GPIO_P1_OMR_PS4_Msk   (0x10UL)

PS4 (Bitfield-Mask: 0x01)

◆ GPIO_P1_OMR_PS4_Pos [1/2]

#define GPIO_P1_OMR_PS4_Pos   (4UL)

PS4 (Bit 4)

◆ GPIO_P1_OMR_PS4_Pos [2/2]

#define GPIO_P1_OMR_PS4_Pos   (4UL)

PS4 (Bit 4)

◆ PLL_CON0_PLLEN_Msk [1/2]

#define PLL_CON0_PLLEN_Msk   (0x80000000UL)

PLLEN (Bitfield-Mask: 0x01)

◆ PLL_CON0_PLLEN_Msk [2/2]

#define PLL_CON0_PLLEN_Msk   (0x80000000UL)

PLLEN (Bitfield-Mask: 0x01)

◆ PLL_CON0_PLLEN_Pos [1/2]

#define PLL_CON0_PLLEN_Pos   (31UL)

PLLEN (Bit 31)

◆ PLL_CON0_PLLEN_Pos [2/2]

#define PLL_CON0_PLLEN_Pos   (31UL)

PLLEN (Bit 31)

◆ PLL_CON1_PLLEN_Msk [1/2]

#define PLL_CON1_PLLEN_Msk   (0x80000000UL)

PLLEN (Bitfield-Mask: 0x01)

◆ PLL_CON1_PLLEN_Msk [2/2]

#define PLL_CON1_PLLEN_Msk   (0x80000000UL)

PLLEN (Bitfield-Mask: 0x01)

◆ PLL_CON1_PLLEN_Pos [1/2]

#define PLL_CON1_PLLEN_Pos   (31UL)

PLLEN (Bit 31)

◆ PLL_CON1_PLLEN_Pos [2/2]

#define PLL_CON1_PLLEN_Pos   (31UL)

PLLEN (Bit 31)

◆ PLL_SPCTR_SPEN0_Msk [1/2]

#define PLL_SPCTR_SPEN0_Msk   (0x1UL)

SPEN0 (Bitfield-Mask: 0x01)

◆ PLL_SPCTR_SPEN0_Msk [2/2]

#define PLL_SPCTR_SPEN0_Msk   (0x1UL)

SPEN0 (Bitfield-Mask: 0x01)

◆ PLL_SPCTR_SPEN0_Pos [1/2]

#define PLL_SPCTR_SPEN0_Pos   (0UL)

SPEN0 (Bit 0)

◆ PLL_SPCTR_SPEN0_Pos [2/2]

#define PLL_SPCTR_SPEN0_Pos   (0UL)

SPEN0 (Bit 0)

◆ PLL_SPCTR_SPEN1_Msk [1/2]

#define PLL_SPCTR_SPEN1_Msk   (0x10000UL)

SPEN1 (Bitfield-Mask: 0x01)

◆ PLL_SPCTR_SPEN1_Msk [2/2]

#define PLL_SPCTR_SPEN1_Msk   (0x10000UL)

SPEN1 (Bitfield-Mask: 0x01)

◆ PLL_SPCTR_SPEN1_Pos [1/2]

#define PLL_SPCTR_SPEN1_Pos   (16UL)

SPEN1 (Bit 16)

◆ PLL_SPCTR_SPEN1_Pos [2/2]

#define PLL_SPCTR_SPEN1_Pos   (16UL)

SPEN1 (Bit 16)

◆ PLL_STATC_PLL0_LOL_STSCLR_Msk [1/2]

#define PLL_STATC_PLL0_LOL_STSCLR_Msk   (0x1UL)

PLL0_LOL_STSCLR (Bitfield-Mask: 0x01)

◆ PLL_STATC_PLL0_LOL_STSCLR_Msk [2/2]

#define PLL_STATC_PLL0_LOL_STSCLR_Msk   (0x1UL)

PLL0_LOL_STSCLR (Bitfield-Mask: 0x01)

◆ PLL_STATC_PLL0_LOL_STSCLR_Pos [1/2]

#define PLL_STATC_PLL0_LOL_STSCLR_Pos   (0UL)

PLL0_LOL_STSCLR (Bit 0)

◆ PLL_STATC_PLL0_LOL_STSCLR_Pos [2/2]

#define PLL_STATC_PLL0_LOL_STSCLR_Pos   (0UL)

PLL0_LOL_STSCLR (Bit 0)

◆ PLL_STATC_PLL1_LOL_STSCLR_Msk [1/2]

#define PLL_STATC_PLL1_LOL_STSCLR_Msk   (0x2UL)

PLL1_LOL_STSCLR (Bitfield-Mask: 0x01)

◆ PLL_STATC_PLL1_LOL_STSCLR_Msk [2/2]

#define PLL_STATC_PLL1_LOL_STSCLR_Msk   (0x2UL)

PLL1_LOL_STSCLR (Bitfield-Mask: 0x01)

◆ PLL_STATC_PLL1_LOL_STSCLR_Pos [1/2]

#define PLL_STATC_PLL1_LOL_STSCLR_Pos   (1UL)

PLL1_LOL_STSCLR (Bit 1)

◆ PLL_STATC_PLL1_LOL_STSCLR_Pos [2/2]

#define PLL_STATC_PLL1_LOL_STSCLR_Pos   (1UL)

PLL1_LOL_STSCLR (Bit 1)

◆ PMU_FS_SSD_CLR_FO_STS_CLR_Msk [1/2]

#define PMU_FS_SSD_CLR_FO_STS_CLR_Msk   (0x2UL)

FO_STS_CLR (Bitfield-Mask: 0x01)

◆ PMU_FS_SSD_CLR_FO_STS_CLR_Msk [2/2]

#define PMU_FS_SSD_CLR_FO_STS_CLR_Msk   (0x2UL)

FO_STS_CLR (Bitfield-Mask: 0x01)

◆ PMU_FS_SSD_CLR_FO_STS_CLR_Pos [1/2]

#define PMU_FS_SSD_CLR_FO_STS_CLR_Pos   (1UL)

FO_STS_CLR (Bit 1)

◆ PMU_FS_SSD_CLR_FO_STS_CLR_Pos [2/2]

#define PMU_FS_SSD_CLR_FO_STS_CLR_Pos   (1UL)

FO_STS_CLR (Bit 1)

◆ PMU_FS_SSD_CLR_SSD_STS_CLR_Msk [1/2]

#define PMU_FS_SSD_CLR_SSD_STS_CLR_Msk   (0x1UL)

SSD_STS_CLR (Bitfield-Mask: 0x01)

◆ PMU_FS_SSD_CLR_SSD_STS_CLR_Msk [2/2]

#define PMU_FS_SSD_CLR_SSD_STS_CLR_Msk   (0x1UL)

SSD_STS_CLR (Bitfield-Mask: 0x01)

◆ PMU_FS_SSD_CLR_SSD_STS_CLR_Pos [1/2]

#define PMU_FS_SSD_CLR_SSD_STS_CLR_Pos   (0UL)

SSD_STS_CLR (Bit 0)

◆ PMU_FS_SSD_CLR_SSD_STS_CLR_Pos [2/2]

#define PMU_FS_SSD_CLR_SSD_STS_CLR_Pos   (0UL)

SSD_STS_CLR (Bit 0)

◆ PMU_WAKE_CTRL_CAN_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_CAN_WAKE_EN_Msk   (0x1UL)

CAN_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_CAN_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_CAN_WAKE_EN_Msk   (0x1UL)

CAN_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_CAN_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_CAN_WAKE_EN_Pos   (0UL)

CAN_WAKE_EN (Bit 0)

◆ PMU_WAKE_CTRL_CAN_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_CAN_WAKE_EN_Pos   (0UL)

CAN_WAKE_EN (Bit 0)

◆ PMU_WAKE_CTRL_CYC_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_CYC_WAKE_EN_Msk   (0x4UL)

CYC_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_CYC_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_CYC_WAKE_EN_Msk   (0x4UL)

CYC_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_CYC_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_CYC_WAKE_EN_Pos   (2UL)

CYC_WAKE_EN (Bit 2)

◆ PMU_WAKE_CTRL_CYC_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_CYC_WAKE_EN_Pos   (2UL)

CYC_WAKE_EN (Bit 2)

◆ PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk   (0x10UL)

GPIO0_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Msk   (0x10UL)

GPIO0_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO0_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Pos   (4UL)

GPIO0_WAKE_EN (Bit 4)

◆ PMU_WAKE_CTRL_GPIO0_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_GPIO0_WAKE_EN_Pos   (4UL)

GPIO0_WAKE_EN (Bit 4)

◆ PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk   (0x20UL)

GPIO1_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Msk   (0x20UL)

GPIO1_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO1_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Pos   (5UL)

GPIO1_WAKE_EN (Bit 5)

◆ PMU_WAKE_CTRL_GPIO1_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_GPIO1_WAKE_EN_Pos   (5UL)

GPIO1_WAKE_EN (Bit 5)

◆ PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk   (0x40UL)

GPIO2_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Msk   (0x40UL)

GPIO2_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO2_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Pos   (6UL)

GPIO2_WAKE_EN (Bit 6)

◆ PMU_WAKE_CTRL_GPIO2_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_GPIO2_WAKE_EN_Pos   (6UL)

GPIO2_WAKE_EN (Bit 6)

◆ PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk   (0x80UL)

GPIO3_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Msk   (0x80UL)

GPIO3_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO3_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Pos   (7UL)

GPIO3_WAKE_EN (Bit 7)

◆ PMU_WAKE_CTRL_GPIO3_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_GPIO3_WAKE_EN_Pos   (7UL)

GPIO3_WAKE_EN (Bit 7)

◆ PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk   (0x100UL)

GPIO4_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Msk   (0x100UL)

GPIO4_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO4_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Pos   (8UL)

GPIO4_WAKE_EN (Bit 8)

◆ PMU_WAKE_CTRL_GPIO4_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_GPIO4_WAKE_EN_Pos   (8UL)

GPIO4_WAKE_EN (Bit 8)

◆ PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk   (0x200UL)

GPIO5_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Msk   (0x200UL)

GPIO5_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_GPIO5_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Pos   (9UL)

GPIO5_WAKE_EN (Bit 9)

◆ PMU_WAKE_CTRL_GPIO5_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_GPIO5_WAKE_EN_Pos   (9UL)

GPIO5_WAKE_EN (Bit 9)

◆ PMU_WAKE_CTRL_LIN_WAKE_EN_Msk

#define PMU_WAKE_CTRL_LIN_WAKE_EN_Msk   (0x2UL)

LIN_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_LIN_WAKE_EN_Pos

#define PMU_WAKE_CTRL_LIN_WAKE_EN_Pos   (1UL)

LIN_WAKE_EN (Bit 1)

◆ PMU_WAKE_CTRL_MON1_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_MON1_WAKE_EN_Msk   (0x1000UL)

MON1_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_MON1_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_MON1_WAKE_EN_Msk   (0x1000UL)

MON1_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_MON1_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_MON1_WAKE_EN_Pos   (12UL)

MON1_WAKE_EN (Bit 12)

◆ PMU_WAKE_CTRL_MON1_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_MON1_WAKE_EN_Pos   (12UL)

MON1_WAKE_EN (Bit 12)

◆ PMU_WAKE_CTRL_MON2_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_MON2_WAKE_EN_Msk   (0x2000UL)

MON2_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_MON2_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_MON2_WAKE_EN_Msk   (0x2000UL)

MON2_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_MON2_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_MON2_WAKE_EN_Pos   (13UL)

MON2_WAKE_EN (Bit 13)

◆ PMU_WAKE_CTRL_MON2_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_MON2_WAKE_EN_Pos   (13UL)

MON2_WAKE_EN (Bit 13)

◆ PMU_WAKE_CTRL_MON3_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_MON3_WAKE_EN_Msk   (0x4000UL)

MON3_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_MON3_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_MON3_WAKE_EN_Msk   (0x4000UL)

MON3_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_MON3_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_MON3_WAKE_EN_Pos   (14UL)

MON3_WAKE_EN (Bit 14)

◆ PMU_WAKE_CTRL_MON3_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_MON3_WAKE_EN_Pos   (14UL)

MON3_WAKE_EN (Bit 14)

◆ PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk   (0x200000UL)

VDDC_HCM_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Msk   (0x200000UL)

VDDC_HCM_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Pos   (21UL)

VDDC_HCM_WAKE_EN (Bit 21)

◆ PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDC_HCM_WAKE_EN_Pos   (21UL)

VDDC_HCM_WAKE_EN (Bit 21)

◆ PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk   (0x100000UL)

VDDC_OV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Msk   (0x100000UL)

VDDC_OV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Pos   (20UL)

VDDC_OV_WAKE_EN (Bit 20)

◆ PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDC_OV_WAKE_EN_Pos   (20UL)

VDDC_OV_WAKE_EN (Bit 20)

◆ PMU_WAKE_CTRL_VDDC_RED_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDC_RED_EN_Msk   (0x20000000UL)

VDDC_RED_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_RED_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDC_RED_EN_Msk   (0x20000000UL)

VDDC_RED_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_RED_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDC_RED_EN_Pos   (29UL)

VDDC_RED_EN (Bit 29)

◆ PMU_WAKE_CTRL_VDDC_RED_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDC_RED_EN_Pos   (29UL)

VDDC_RED_EN (Bit 29)

◆ PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk   (0x80000UL)

VDDC_UVWARN_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Msk   (0x80000UL)

VDDC_UVWARN_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Pos   (19UL)

VDDC_UVWARN_WAKE_EN (Bit 19)

◆ PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDC_UVWARN_WAKE_EN_Pos   (19UL)

VDDC_UVWARN_WAKE_EN (Bit 19)

◆ PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk   (0x400000UL)

VDDEXT_OT_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Msk   (0x400000UL)

VDDEXT_OT_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Pos   (22UL)

VDDEXT_OT_WAKE_EN (Bit 22)

◆ PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDEXT_OT_WAKE_EN_Pos   (22UL)

VDDEXT_OT_WAKE_EN (Bit 22)

◆ PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk   (0x800000UL)

VDDEXT_UV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Msk   (0x800000UL)

VDDEXT_UV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Pos   (23UL)

VDDEXT_UV_WAKE_EN (Bit 23)

◆ PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDEXT_UV_WAKE_EN_Pos   (23UL)

VDDEXT_UV_WAKE_EN (Bit 23)

◆ PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk   (0x40000UL)

VDDP_HCM_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Msk   (0x40000UL)

VDDP_HCM_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Pos   (18UL)

VDDP_HCM_WAKE_EN (Bit 18)

◆ PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDP_HCM_WAKE_EN_Pos   (18UL)

VDDP_HCM_WAKE_EN (Bit 18)

◆ PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk   (0x20000UL)

VDDP_OV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Msk   (0x20000UL)

VDDP_OV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Pos   (17UL)

VDDP_OV_WAKE_EN (Bit 17)

◆ PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDP_OV_WAKE_EN_Pos   (17UL)

VDDP_OV_WAKE_EN (Bit 17)

◆ PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk   (0x10000UL)

VDDP_UVWARN_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Msk   (0x10000UL)

VDDP_UVWARN_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Pos   (16UL)

VDDP_UVWARN_WAKE_EN (Bit 16)

◆ PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VDDP_UVWARN_WAKE_EN_Pos   (16UL)

VDDP_UVWARN_WAKE_EN (Bit 16)

◆ PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk [1/2]

#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk   (0x1000000UL)

VSDOV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk [2/2]

#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Msk   (0x1000000UL)

VSDOV_WAKE_EN (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_VSDOV_WAKE_EN_Pos [1/2]

#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Pos   (24UL)

VSDOV_WAKE_EN (Bit 24)

◆ PMU_WAKE_CTRL_VSDOV_WAKE_EN_Pos [2/2]

#define PMU_WAKE_CTRL_VSDOV_WAKE_EN_Pos   (24UL)

VSDOV_WAKE_EN (Bit 24)

◆ PMU_WAKE_CTRL_WAKE_W_RST_Msk

#define PMU_WAKE_CTRL_WAKE_W_RST_Msk   (0x10000000UL)

WAKE_W_RST (Bitfield-Mask: 0x01)

◆ PMU_WAKE_CTRL_WAKE_W_RST_Pos

#define PMU_WAKE_CTRL_WAKE_W_RST_Pos   (28UL)

WAKE_W_RST (Bit 28)

◆ PMU_WD_CTRL_SOW_Msk [1/2]

#define PMU_WD_CTRL_SOW_Msk   (0x3000000UL)

SOW (Bitfield-Mask: 0x03)

◆ PMU_WD_CTRL_SOW_Msk [2/2]

#define PMU_WD_CTRL_SOW_Msk   (0x3000000UL)

SOW (Bitfield-Mask: 0x03)

◆ PMU_WD_CTRL_SOW_Pos [1/2]

#define PMU_WD_CTRL_SOW_Pos   (24UL)

SOW (Bit 24)

◆ PMU_WD_CTRL_SOW_Pos [2/2]

#define PMU_WD_CTRL_SOW_Pos   (24UL)

SOW (Bit 24)

◆ PMU_WD_CTRL_WDP_Msk [1/2]

#define PMU_WD_CTRL_WDP_Msk   (0x3f0000UL)

WDP (Bitfield-Mask: 0x3f)

◆ PMU_WD_CTRL_WDP_Msk [2/2]

#define PMU_WD_CTRL_WDP_Msk   (0x3f0000UL)

WDP (Bitfield-Mask: 0x3f)

◆ PMU_WD_CTRL_WDP_Pos [1/2]

#define PMU_WD_CTRL_WDP_Pos   (16UL)

WDP (Bit 16)

◆ PMU_WD_CTRL_WDP_Pos [2/2]

#define PMU_WD_CTRL_WDP_Pos   (16UL)

WDP (Bit 16)

◆ SCU_CLKSEL_CLKOUTEN_Msk [1/2]

#define SCU_CLKSEL_CLKOUTEN_Msk   (0x80000UL)

CLKOUTEN (Bitfield-Mask: 0x01)

◆ SCU_CLKSEL_CLKOUTEN_Msk [2/2]

#define SCU_CLKSEL_CLKOUTEN_Msk   (0x80000UL)

CLKOUTEN (Bitfield-Mask: 0x01)

◆ SCU_CLKSEL_CLKOUTEN_Pos [1/2]

#define SCU_CLKSEL_CLKOUTEN_Pos   (19UL)

CLKOUTEN (Bit 19)

◆ SCU_CLKSEL_CLKOUTEN_Pos [2/2]

#define SCU_CLKSEL_CLKOUTEN_Pos   (19UL)

CLKOUTEN (Bit 19)

◆ SCU_INP0_INP_ARVG_Msk [1/2]

#define SCU_INP0_INP_ARVG_Msk   (0x10UL)

INP_ARVG (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_ARVG_Msk [2/2]

#define SCU_INP0_INP_ARVG_Msk   (0x10UL)

INP_ARVG (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_ARVG_Pos [1/2]

#define SCU_INP0_INP_ARVG_Pos   (4UL)

INP_ARVG (Bit 4)

◆ SCU_INP0_INP_ARVG_Pos [2/2]

#define SCU_INP0_INP_ARVG_Pos   (4UL)

INP_ARVG (Bit 4)

◆ SCU_INP0_INP_BDRV_IRQ0_Msk [1/2]

#define SCU_INP0_INP_BDRV_IRQ0_Msk   (0x2UL)

INP_BDRV_IRQ0 (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_BDRV_IRQ0_Msk [2/2]

#define SCU_INP0_INP_BDRV_IRQ0_Msk   (0x2UL)

INP_BDRV_IRQ0 (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_BDRV_IRQ0_Pos [1/2]

#define SCU_INP0_INP_BDRV_IRQ0_Pos   (1UL)

INP_BDRV_IRQ0 (Bit 1)

◆ SCU_INP0_INP_BDRV_IRQ0_Pos [2/2]

#define SCU_INP0_INP_BDRV_IRQ0_Pos   (1UL)

INP_BDRV_IRQ0 (Bit 1)

◆ SCU_INP0_INP_BDRV_IRQ1_Msk [1/2]

#define SCU_INP0_INP_BDRV_IRQ1_Msk   (0x4UL)

INP_BDRV_IRQ1 (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_BDRV_IRQ1_Msk [2/2]

#define SCU_INP0_INP_BDRV_IRQ1_Msk   (0x4UL)

INP_BDRV_IRQ1 (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_BDRV_IRQ1_Pos [1/2]

#define SCU_INP0_INP_BDRV_IRQ1_Pos   (2UL)

INP_BDRV_IRQ1 (Bit 2)

◆ SCU_INP0_INP_BDRV_IRQ1_Pos [2/2]

#define SCU_INP0_INP_BDRV_IRQ1_Pos   (2UL)

INP_BDRV_IRQ1 (Bit 2)

◆ SCU_INP0_INP_CANTX_Msk [1/2]

#define SCU_INP0_INP_CANTX_Msk   (0x8UL)

INP_CANTX (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_CANTX_Msk [2/2]

#define SCU_INP0_INP_CANTX_Msk   (0x8UL)

INP_CANTX (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_CANTX_Pos [1/2]

#define SCU_INP0_INP_CANTX_Pos   (3UL)

INP_CANTX (Bit 3)

◆ SCU_INP0_INP_CANTX_Pos [2/2]

#define SCU_INP0_INP_CANTX_Pos   (3UL)

INP_CANTX (Bit 3)

◆ SCU_INP0_INP_CSC_Msk [1/2]

#define SCU_INP0_INP_CSC_Msk   (0x20UL)

INP_CSC (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_CSC_Msk [2/2]

#define SCU_INP0_INP_CSC_Msk   (0x20UL)

INP_CSC (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_CSC_Pos [1/2]

#define SCU_INP0_INP_CSC_Pos   (5UL)

INP_CSC (Bit 5)

◆ SCU_INP0_INP_CSC_Pos [2/2]

#define SCU_INP0_INP_CSC_Pos   (5UL)

INP_CSC (Bit 5)

◆ SCU_INP0_INP_PMU_Msk [1/2]

#define SCU_INP0_INP_PMU_Msk   (0x1UL)

INP_PMU (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_PMU_Msk [2/2]

#define SCU_INP0_INP_PMU_Msk   (0x1UL)

INP_PMU (Bitfield-Mask: 0x01)

◆ SCU_INP0_INP_PMU_Pos [1/2]

#define SCU_INP0_INP_PMU_Pos   (0UL)

INP_PMU (Bit 0)

◆ SCU_INP0_INP_PMU_Pos [2/2]

#define SCU_INP0_INP_PMU_Pos   (0UL)

INP_PMU (Bit 0)

◆ SCU_INP1_INP_GPT1T2_Msk [1/2]

#define SCU_INP1_INP_GPT1T2_Msk   (0x1UL)

INP_GPT1T2 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT1T2_Msk [2/2]

#define SCU_INP1_INP_GPT1T2_Msk   (0x1UL)

INP_GPT1T2 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT1T2_Pos [1/2]

#define SCU_INP1_INP_GPT1T2_Pos   (0UL)

INP_GPT1T2 (Bit 0)

◆ SCU_INP1_INP_GPT1T2_Pos [2/2]

#define SCU_INP1_INP_GPT1T2_Pos   (0UL)

INP_GPT1T2 (Bit 0)

◆ SCU_INP1_INP_GPT1T3_Msk [1/2]

#define SCU_INP1_INP_GPT1T3_Msk   (0x2UL)

INP_GPT1T3 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT1T3_Msk [2/2]

#define SCU_INP1_INP_GPT1T3_Msk   (0x2UL)

INP_GPT1T3 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT1T3_Pos [1/2]

#define SCU_INP1_INP_GPT1T3_Pos   (1UL)

INP_GPT1T3 (Bit 1)

◆ SCU_INP1_INP_GPT1T3_Pos [2/2]

#define SCU_INP1_INP_GPT1T3_Pos   (1UL)

INP_GPT1T3 (Bit 1)

◆ SCU_INP1_INP_GPT1T4_Msk [1/2]

#define SCU_INP1_INP_GPT1T4_Msk   (0x4UL)

INP_GPT1T4 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT1T4_Msk [2/2]

#define SCU_INP1_INP_GPT1T4_Msk   (0x4UL)

INP_GPT1T4 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT1T4_Pos [1/2]

#define SCU_INP1_INP_GPT1T4_Pos   (2UL)

INP_GPT1T4 (Bit 2)

◆ SCU_INP1_INP_GPT1T4_Pos [2/2]

#define SCU_INP1_INP_GPT1T4_Pos   (2UL)

INP_GPT1T4 (Bit 2)

◆ SCU_INP1_INP_GPT2CR_Msk [1/2]

#define SCU_INP1_INP_GPT2CR_Msk   (0x20UL)

INP_GPT2CR (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT2CR_Msk [2/2]

#define SCU_INP1_INP_GPT2CR_Msk   (0x20UL)

INP_GPT2CR (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT2CR_Pos [1/2]

#define SCU_INP1_INP_GPT2CR_Pos   (5UL)

INP_GPT2CR (Bit 5)

◆ SCU_INP1_INP_GPT2CR_Pos [2/2]

#define SCU_INP1_INP_GPT2CR_Pos   (5UL)

INP_GPT2CR (Bit 5)

◆ SCU_INP1_INP_GPT2T5_Msk [1/2]

#define SCU_INP1_INP_GPT2T5_Msk   (0x8UL)

INP_GPT2T5 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT2T5_Msk [2/2]

#define SCU_INP1_INP_GPT2T5_Msk   (0x8UL)

INP_GPT2T5 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT2T5_Pos [1/2]

#define SCU_INP1_INP_GPT2T5_Pos   (3UL)

INP_GPT2T5 (Bit 3)

◆ SCU_INP1_INP_GPT2T5_Pos [2/2]

#define SCU_INP1_INP_GPT2T5_Pos   (3UL)

INP_GPT2T5 (Bit 3)

◆ SCU_INP1_INP_GPT2T6_Msk [1/2]

#define SCU_INP1_INP_GPT2T6_Msk   (0x10UL)

INP_GPT2T6 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT2T6_Msk [2/2]

#define SCU_INP1_INP_GPT2T6_Msk   (0x10UL)

INP_GPT2T6 (Bitfield-Mask: 0x01)

◆ SCU_INP1_INP_GPT2T6_Pos [1/2]

#define SCU_INP1_INP_GPT2T6_Pos   (4UL)

INP_GPT2T6 (Bit 4)

◆ SCU_INP1_INP_GPT2T6_Pos [2/2]

#define SCU_INP1_INP_GPT2T6_Pos   (4UL)

INP_GPT2T6 (Bit 4)

◆ SCU_INP2_INP_MON1_Msk [1/2]

#define SCU_INP2_INP_MON1_Msk   (0x1UL)

INP_MON1 (Bitfield-Mask: 0x01)

◆ SCU_INP2_INP_MON1_Msk [2/2]

#define SCU_INP2_INP_MON1_Msk   (0x1UL)

INP_MON1 (Bitfield-Mask: 0x01)

◆ SCU_INP2_INP_MON1_Pos [1/2]

#define SCU_INP2_INP_MON1_Pos   (0UL)

INP_MON1 (Bit 0)

◆ SCU_INP2_INP_MON1_Pos [2/2]

#define SCU_INP2_INP_MON1_Pos   (0UL)

INP_MON1 (Bit 0)

◆ SCU_INP2_INP_MON2_Msk [1/2]

#define SCU_INP2_INP_MON2_Msk   (0x2UL)

INP_MON2 (Bitfield-Mask: 0x01)

◆ SCU_INP2_INP_MON2_Msk [2/2]

#define SCU_INP2_INP_MON2_Msk   (0x2UL)

INP_MON2 (Bitfield-Mask: 0x01)

◆ SCU_INP2_INP_MON2_Pos [1/2]

#define SCU_INP2_INP_MON2_Pos   (1UL)

INP_MON2 (Bit 1)

◆ SCU_INP2_INP_MON2_Pos [2/2]

#define SCU_INP2_INP_MON2_Pos   (1UL)

INP_MON2 (Bit 1)

◆ SCU_INP2_INP_MON3_Msk [1/2]

#define SCU_INP2_INP_MON3_Msk   (0x4UL)

INP_MON3 (Bitfield-Mask: 0x01)

◆ SCU_INP2_INP_MON3_Msk [2/2]

#define SCU_INP2_INP_MON3_Msk   (0x4UL)

INP_MON3 (Bitfield-Mask: 0x01)

◆ SCU_INP2_INP_MON3_Pos [1/2]

#define SCU_INP2_INP_MON3_Pos   (2UL)

INP_MON3 (Bit 2)

◆ SCU_INP2_INP_MON3_Pos [2/2]

#define SCU_INP2_INP_MON3_Pos   (2UL)

INP_MON3 (Bit 2)

◆ SCU_INP3_INP_BEMF0_Msk [1/2]

#define SCU_INP3_INP_BEMF0_Msk   (0x4UL)

INP_BEMF0 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_BEMF0_Msk [2/2]

#define SCU_INP3_INP_BEMF0_Msk   (0x4UL)

INP_BEMF0 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_BEMF0_Pos [1/2]

#define SCU_INP3_INP_BEMF0_Pos   (2UL)

INP_BEMF0 (Bit 2)

◆ SCU_INP3_INP_BEMF0_Pos [2/2]

#define SCU_INP3_INP_BEMF0_Pos   (2UL)

INP_BEMF0 (Bit 2)

◆ SCU_INP3_INP_BEMF1_Msk [1/2]

#define SCU_INP3_INP_BEMF1_Msk   (0x8UL)

INP_BEMF1 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_BEMF1_Msk [2/2]

#define SCU_INP3_INP_BEMF1_Msk   (0x8UL)

INP_BEMF1 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_BEMF1_Pos [1/2]

#define SCU_INP3_INP_BEMF1_Pos   (3UL)

INP_BEMF1 (Bit 3)

◆ SCU_INP3_INP_BEMF1_Pos [2/2]

#define SCU_INP3_INP_BEMF1_Pos   (3UL)

INP_BEMF1 (Bit 3)

◆ SCU_INP3_INP_BEMF2_Msk [1/2]

#define SCU_INP3_INP_BEMF2_Msk   (0x10UL)

INP_BEMF2 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_BEMF2_Msk [2/2]

#define SCU_INP3_INP_BEMF2_Msk   (0x10UL)

INP_BEMF2 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_BEMF2_Pos [1/2]

#define SCU_INP3_INP_BEMF2_Pos   (4UL)

INP_BEMF2 (Bit 4)

◆ SCU_INP3_INP_BEMF2_Pos [2/2]

#define SCU_INP3_INP_BEMF2_Pos   (4UL)

INP_BEMF2 (Bit 4)

◆ SCU_INP3_INP_SDADC0_Msk [1/2]

#define SCU_INP3_INP_SDADC0_Msk   (0x1UL)

INP_SDADC0 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_SDADC0_Msk [2/2]

#define SCU_INP3_INP_SDADC0_Msk   (0x1UL)

INP_SDADC0 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_SDADC0_Pos [1/2]

#define SCU_INP3_INP_SDADC0_Pos   (0UL)

INP_SDADC0 (Bit 0)

◆ SCU_INP3_INP_SDADC0_Pos [2/2]

#define SCU_INP3_INP_SDADC0_Pos   (0UL)

INP_SDADC0 (Bit 0)

◆ SCU_INP3_INP_SDADC1_Msk [1/2]

#define SCU_INP3_INP_SDADC1_Msk   (0x2UL)

INP_SDADC1 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_SDADC1_Msk [2/2]

#define SCU_INP3_INP_SDADC1_Msk   (0x2UL)

INP_SDADC1 (Bitfield-Mask: 0x01)

◆ SCU_INP3_INP_SDADC1_Pos [1/2]

#define SCU_INP3_INP_SDADC1_Pos   (1UL)

INP_SDADC1 (Bit 1)

◆ SCU_INP3_INP_SDADC1_Pos [2/2]

#define SCU_INP3_INP_SDADC1_Pos   (1UL)

INP_SDADC1 (Bit 1)

◆ SCU_INP4_INP_EXINT0_Msk [1/2]

#define SCU_INP4_INP_EXINT0_Msk   (0x1UL)

INP_EXINT0 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT0_Msk [2/2]

#define SCU_INP4_INP_EXINT0_Msk   (0x1UL)

INP_EXINT0 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT0_Pos [1/2]

#define SCU_INP4_INP_EXINT0_Pos   (0UL)

INP_EXINT0 (Bit 0)

◆ SCU_INP4_INP_EXINT0_Pos [2/2]

#define SCU_INP4_INP_EXINT0_Pos   (0UL)

INP_EXINT0 (Bit 0)

◆ SCU_INP4_INP_EXINT1_Msk [1/2]

#define SCU_INP4_INP_EXINT1_Msk   (0x2UL)

INP_EXINT1 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT1_Msk [2/2]

#define SCU_INP4_INP_EXINT1_Msk   (0x2UL)

INP_EXINT1 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT1_Pos [1/2]

#define SCU_INP4_INP_EXINT1_Pos   (1UL)

INP_EXINT1 (Bit 1)

◆ SCU_INP4_INP_EXINT1_Pos [2/2]

#define SCU_INP4_INP_EXINT1_Pos   (1UL)

INP_EXINT1 (Bit 1)

◆ SCU_INP4_INP_EXINT2_Msk [1/2]

#define SCU_INP4_INP_EXINT2_Msk   (0x4UL)

INP_EXINT2 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT2_Msk [2/2]

#define SCU_INP4_INP_EXINT2_Msk   (0x4UL)

INP_EXINT2 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT2_Pos [1/2]

#define SCU_INP4_INP_EXINT2_Pos   (2UL)

INP_EXINT2 (Bit 2)

◆ SCU_INP4_INP_EXINT2_Pos [2/2]

#define SCU_INP4_INP_EXINT2_Pos   (2UL)

INP_EXINT2 (Bit 2)

◆ SCU_INP4_INP_EXINT3_Msk [1/2]

#define SCU_INP4_INP_EXINT3_Msk   (0x8UL)

INP_EXINT3 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT3_Msk [2/2]

#define SCU_INP4_INP_EXINT3_Msk   (0x8UL)

INP_EXINT3 (Bitfield-Mask: 0x01)

◆ SCU_INP4_INP_EXINT3_Pos [1/2]

#define SCU_INP4_INP_EXINT3_Pos   (3UL)

INP_EXINT3 (Bit 3)

◆ SCU_INP4_INP_EXINT3_Pos [2/2]

#define SCU_INP4_INP_EXINT3_Pos   (3UL)

INP_EXINT3 (Bit 3)

◆ SCU_INP5_INP_LIN0_EOFSYN_Msk [1/2]

#define SCU_INP5_INP_LIN0_EOFSYN_Msk   (0x1UL)

INP_LIN0_EOFSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN0_EOFSYN_Msk [2/2]

#define SCU_INP5_INP_LIN0_EOFSYN_Msk   (0x1UL)

INP_LIN0_EOFSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN0_EOFSYN_Pos [1/2]

#define SCU_INP5_INP_LIN0_EOFSYN_Pos   (0UL)

INP_LIN0_EOFSYN (Bit 0)

◆ SCU_INP5_INP_LIN0_EOFSYN_Pos [2/2]

#define SCU_INP5_INP_LIN0_EOFSYN_Pos   (0UL)

INP_LIN0_EOFSYN (Bit 0)

◆ SCU_INP5_INP_LIN0_ERRSYN_Msk [1/2]

#define SCU_INP5_INP_LIN0_ERRSYN_Msk   (0x2UL)

INP_LIN0_ERRSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN0_ERRSYN_Msk [2/2]

#define SCU_INP5_INP_LIN0_ERRSYN_Msk   (0x2UL)

INP_LIN0_ERRSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN0_ERRSYN_Pos [1/2]

#define SCU_INP5_INP_LIN0_ERRSYN_Pos   (1UL)

INP_LIN0_ERRSYN (Bit 1)

◆ SCU_INP5_INP_LIN0_ERRSYN_Pos [2/2]

#define SCU_INP5_INP_LIN0_ERRSYN_Pos   (1UL)

INP_LIN0_ERRSYN (Bit 1)

◆ SCU_INP5_INP_LIN1_EOFSYN_Msk [1/2]

#define SCU_INP5_INP_LIN1_EOFSYN_Msk   (0x4UL)

INP_LIN1_EOFSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN1_EOFSYN_Msk [2/2]

#define SCU_INP5_INP_LIN1_EOFSYN_Msk   (0x4UL)

INP_LIN1_EOFSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN1_EOFSYN_Pos [1/2]

#define SCU_INP5_INP_LIN1_EOFSYN_Pos   (2UL)

INP_LIN1_EOFSYN (Bit 2)

◆ SCU_INP5_INP_LIN1_EOFSYN_Pos [2/2]

#define SCU_INP5_INP_LIN1_EOFSYN_Pos   (2UL)

INP_LIN1_EOFSYN (Bit 2)

◆ SCU_INP5_INP_LIN1_ERRSYN_Msk [1/2]

#define SCU_INP5_INP_LIN1_ERRSYN_Msk   (0x8UL)

INP_LIN1_ERRSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN1_ERRSYN_Msk [2/2]

#define SCU_INP5_INP_LIN1_ERRSYN_Msk   (0x8UL)

INP_LIN1_ERRSYN (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_LIN1_ERRSYN_Pos [1/2]

#define SCU_INP5_INP_LIN1_ERRSYN_Pos   (3UL)

INP_LIN1_ERRSYN (Bit 3)

◆ SCU_INP5_INP_LIN1_ERRSYN_Pos [2/2]

#define SCU_INP5_INP_LIN1_ERRSYN_Pos   (3UL)

INP_LIN1_ERRSYN (Bit 3)

◆ SCU_INP5_INP_UART0_RI_Msk [1/2]

#define SCU_INP5_INP_UART0_RI_Msk   (0x10UL)

INP_UART0_RI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART0_RI_Msk [2/2]

#define SCU_INP5_INP_UART0_RI_Msk   (0x10UL)

INP_UART0_RI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART0_RI_Pos [1/2]

#define SCU_INP5_INP_UART0_RI_Pos   (4UL)

INP_UART0_RI (Bit 4)

◆ SCU_INP5_INP_UART0_RI_Pos [2/2]

#define SCU_INP5_INP_UART0_RI_Pos   (4UL)

INP_UART0_RI (Bit 4)

◆ SCU_INP5_INP_UART0_TI_Msk [1/2]

#define SCU_INP5_INP_UART0_TI_Msk   (0x20UL)

INP_UART0_TI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART0_TI_Msk [2/2]

#define SCU_INP5_INP_UART0_TI_Msk   (0x20UL)

INP_UART0_TI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART0_TI_Pos [1/2]

#define SCU_INP5_INP_UART0_TI_Pos   (5UL)

INP_UART0_TI (Bit 5)

◆ SCU_INP5_INP_UART0_TI_Pos [2/2]

#define SCU_INP5_INP_UART0_TI_Pos   (5UL)

INP_UART0_TI (Bit 5)

◆ SCU_INP5_INP_UART1_RI_Msk [1/2]

#define SCU_INP5_INP_UART1_RI_Msk   (0x40UL)

INP_UART1_RI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART1_RI_Msk [2/2]

#define SCU_INP5_INP_UART1_RI_Msk   (0x40UL)

INP_UART1_RI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART1_RI_Pos [1/2]

#define SCU_INP5_INP_UART1_RI_Pos   (6UL)

INP_UART1_RI (Bit 6)

◆ SCU_INP5_INP_UART1_RI_Pos [2/2]

#define SCU_INP5_INP_UART1_RI_Pos   (6UL)

INP_UART1_RI (Bit 6)

◆ SCU_INP5_INP_UART1_TI_Msk [1/2]

#define SCU_INP5_INP_UART1_TI_Msk   (0x80UL)

INP_UART1_TI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART1_TI_Msk [2/2]

#define SCU_INP5_INP_UART1_TI_Msk   (0x80UL)

INP_UART1_TI (Bitfield-Mask: 0x01)

◆ SCU_INP5_INP_UART1_TI_Pos [1/2]

#define SCU_INP5_INP_UART1_TI_Pos   (7UL)

INP_UART1_TI (Bit 7)

◆ SCU_INP5_INP_UART1_TI_Pos [2/2]

#define SCU_INP5_INP_UART1_TI_Pos   (7UL)

INP_UART1_TI (Bit 7)

◆ SCU_INP6_INP_SSC0_EIR_Msk [1/2]

#define SCU_INP6_INP_SSC0_EIR_Msk   (0x4UL)

INP_SSC0_EIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC0_EIR_Msk [2/2]

#define SCU_INP6_INP_SSC0_EIR_Msk   (0x4UL)

INP_SSC0_EIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC0_EIR_Pos [1/2]

#define SCU_INP6_INP_SSC0_EIR_Pos   (2UL)

INP_SSC0_EIR (Bit 2)

◆ SCU_INP6_INP_SSC0_EIR_Pos [2/2]

#define SCU_INP6_INP_SSC0_EIR_Pos   (2UL)

INP_SSC0_EIR (Bit 2)

◆ SCU_INP6_INP_SSC0_RIR_Msk [1/2]

#define SCU_INP6_INP_SSC0_RIR_Msk   (0x1UL)

INP_SSC0_RIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC0_RIR_Msk [2/2]

#define SCU_INP6_INP_SSC0_RIR_Msk   (0x1UL)

INP_SSC0_RIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC0_RIR_Pos [1/2]

#define SCU_INP6_INP_SSC0_RIR_Pos   (0UL)

INP_SSC0_RIR (Bit 0)

◆ SCU_INP6_INP_SSC0_RIR_Pos [2/2]

#define SCU_INP6_INP_SSC0_RIR_Pos   (0UL)

INP_SSC0_RIR (Bit 0)

◆ SCU_INP6_INP_SSC0_TIR_Msk [1/2]

#define SCU_INP6_INP_SSC0_TIR_Msk   (0x2UL)

INP_SSC0_TIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC0_TIR_Msk [2/2]

#define SCU_INP6_INP_SSC0_TIR_Msk   (0x2UL)

INP_SSC0_TIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC0_TIR_Pos [1/2]

#define SCU_INP6_INP_SSC0_TIR_Pos   (1UL)

INP_SSC0_TIR (Bit 1)

◆ SCU_INP6_INP_SSC0_TIR_Pos [2/2]

#define SCU_INP6_INP_SSC0_TIR_Pos   (1UL)

INP_SSC0_TIR (Bit 1)

◆ SCU_INP6_INP_SSC1_EIR_Msk [1/2]

#define SCU_INP6_INP_SSC1_EIR_Msk   (0x40UL)

INP_SSC1_EIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC1_EIR_Msk [2/2]

#define SCU_INP6_INP_SSC1_EIR_Msk   (0x40UL)

INP_SSC1_EIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC1_EIR_Pos [1/2]

#define SCU_INP6_INP_SSC1_EIR_Pos   (6UL)

INP_SSC1_EIR (Bit 6)

◆ SCU_INP6_INP_SSC1_EIR_Pos [2/2]

#define SCU_INP6_INP_SSC1_EIR_Pos   (6UL)

INP_SSC1_EIR (Bit 6)

◆ SCU_INP6_INP_SSC1_RIR_Msk [1/2]

#define SCU_INP6_INP_SSC1_RIR_Msk   (0x10UL)

INP_SSC1_RIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC1_RIR_Msk [2/2]

#define SCU_INP6_INP_SSC1_RIR_Msk   (0x10UL)

INP_SSC1_RIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC1_RIR_Pos [1/2]

#define SCU_INP6_INP_SSC1_RIR_Pos   (4UL)

INP_SSC1_RIR (Bit 4)

◆ SCU_INP6_INP_SSC1_RIR_Pos [2/2]

#define SCU_INP6_INP_SSC1_RIR_Pos   (4UL)

INP_SSC1_RIR (Bit 4)

◆ SCU_INP6_INP_SSC1_TIR_Msk [1/2]

#define SCU_INP6_INP_SSC1_TIR_Msk   (0x20UL)

INP_SSC1_TIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC1_TIR_Msk [2/2]

#define SCU_INP6_INP_SSC1_TIR_Msk   (0x20UL)

INP_SSC1_TIR (Bitfield-Mask: 0x01)

◆ SCU_INP6_INP_SSC1_TIR_Pos [1/2]

#define SCU_INP6_INP_SSC1_TIR_Pos   (5UL)

INP_SSC1_TIR (Bit 5)

◆ SCU_INP6_INP_SSC1_TIR_Pos [2/2]

#define SCU_INP6_INP_SSC1_TIR_Pos   (5UL)

INP_SSC1_TIR (Bit 5)

◆ SCU_INP7_INP_DMACH0_Msk [1/2]

#define SCU_INP7_INP_DMACH0_Msk   (0x1UL)

INP_DMACH0 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH0_Msk [2/2]

#define SCU_INP7_INP_DMACH0_Msk   (0x1UL)

INP_DMACH0 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH0_Pos [1/2]

#define SCU_INP7_INP_DMACH0_Pos   (0UL)

INP_DMACH0 (Bit 0)

◆ SCU_INP7_INP_DMACH0_Pos [2/2]

#define SCU_INP7_INP_DMACH0_Pos   (0UL)

INP_DMACH0 (Bit 0)

◆ SCU_INP7_INP_DMACH1_Msk [1/2]

#define SCU_INP7_INP_DMACH1_Msk   (0x2UL)

INP_DMACH1 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH1_Msk [2/2]

#define SCU_INP7_INP_DMACH1_Msk   (0x2UL)

INP_DMACH1 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH1_Pos [1/2]

#define SCU_INP7_INP_DMACH1_Pos   (1UL)

INP_DMACH1 (Bit 1)

◆ SCU_INP7_INP_DMACH1_Pos [2/2]

#define SCU_INP7_INP_DMACH1_Pos   (1UL)

INP_DMACH1 (Bit 1)

◆ SCU_INP7_INP_DMACH2_Msk [1/2]

#define SCU_INP7_INP_DMACH2_Msk   (0x4UL)

INP_DMACH2 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH2_Msk [2/2]

#define SCU_INP7_INP_DMACH2_Msk   (0x4UL)

INP_DMACH2 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH2_Pos [1/2]

#define SCU_INP7_INP_DMACH2_Pos   (2UL)

INP_DMACH2 (Bit 2)

◆ SCU_INP7_INP_DMACH2_Pos [2/2]

#define SCU_INP7_INP_DMACH2_Pos   (2UL)

INP_DMACH2 (Bit 2)

◆ SCU_INP7_INP_DMACH3_Msk [1/2]

#define SCU_INP7_INP_DMACH3_Msk   (0x8UL)

INP_DMACH3 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH3_Msk [2/2]

#define SCU_INP7_INP_DMACH3_Msk   (0x8UL)

INP_DMACH3 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH3_Pos [1/2]

#define SCU_INP7_INP_DMACH3_Pos   (3UL)

INP_DMACH3 (Bit 3)

◆ SCU_INP7_INP_DMACH3_Pos [2/2]

#define SCU_INP7_INP_DMACH3_Pos   (3UL)

INP_DMACH3 (Bit 3)

◆ SCU_INP7_INP_DMACH4_Msk [1/2]

#define SCU_INP7_INP_DMACH4_Msk   (0x10UL)

INP_DMACH4 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH4_Msk [2/2]

#define SCU_INP7_INP_DMACH4_Msk   (0x10UL)

INP_DMACH4 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH4_Pos [1/2]

#define SCU_INP7_INP_DMACH4_Pos   (4UL)

INP_DMACH4 (Bit 4)

◆ SCU_INP7_INP_DMACH4_Pos [2/2]

#define SCU_INP7_INP_DMACH4_Pos   (4UL)

INP_DMACH4 (Bit 4)

◆ SCU_INP7_INP_DMACH5_Msk [1/2]

#define SCU_INP7_INP_DMACH5_Msk   (0x20UL)

INP_DMACH5 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH5_Msk [2/2]

#define SCU_INP7_INP_DMACH5_Msk   (0x20UL)

INP_DMACH5 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH5_Pos [1/2]

#define SCU_INP7_INP_DMACH5_Pos   (5UL)

INP_DMACH5 (Bit 5)

◆ SCU_INP7_INP_DMACH5_Pos [2/2]

#define SCU_INP7_INP_DMACH5_Pos   (5UL)

INP_DMACH5 (Bit 5)

◆ SCU_INP7_INP_DMACH6_Msk [1/2]

#define SCU_INP7_INP_DMACH6_Msk   (0x40UL)

INP_DMACH6 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH6_Msk [2/2]

#define SCU_INP7_INP_DMACH6_Msk   (0x40UL)

INP_DMACH6 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH6_Pos [1/2]

#define SCU_INP7_INP_DMACH6_Pos   (6UL)

INP_DMACH6 (Bit 6)

◆ SCU_INP7_INP_DMACH6_Pos [2/2]

#define SCU_INP7_INP_DMACH6_Pos   (6UL)

INP_DMACH6 (Bit 6)

◆ SCU_INP7_INP_DMACH7_Msk [1/2]

#define SCU_INP7_INP_DMACH7_Msk   (0x80UL)

INP_DMACH7 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH7_Msk [2/2]

#define SCU_INP7_INP_DMACH7_Msk   (0x80UL)

INP_DMACH7 (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMACH7_Pos [1/2]

#define SCU_INP7_INP_DMACH7_Pos   (7UL)

INP_DMACH7 (Bit 7)

◆ SCU_INP7_INP_DMACH7_Pos [2/2]

#define SCU_INP7_INP_DMACH7_Pos   (7UL)

INP_DMACH7 (Bit 7)

◆ SCU_INP7_INP_DMATRERR_Msk [1/2]

#define SCU_INP7_INP_DMATRERR_Msk   (0x100UL)

INP_DMATRERR (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMATRERR_Msk [2/2]

#define SCU_INP7_INP_DMATRERR_Msk   (0x100UL)

INP_DMATRERR (Bitfield-Mask: 0x01)

◆ SCU_INP7_INP_DMATRERR_Pos [1/2]

#define SCU_INP7_INP_DMATRERR_Pos   (8UL)

INP_DMATRERR (Bit 8)

◆ SCU_INP7_INP_DMATRERR_Pos [2/2]

#define SCU_INP7_INP_DMATRERR_Pos   (8UL)

INP_DMATRERR (Bit 8)

◆ SCU_NMISRC_NMIPLL0CLR_Msk [1/2]

#define SCU_NMISRC_NMIPLL0CLR_Msk   (0x2UL)

NMIPLL0CLR (Bitfield-Mask: 0x01)

◆ SCU_NMISRC_NMIPLL0CLR_Msk [2/2]

#define SCU_NMISRC_NMIPLL0CLR_Msk   (0x2UL)

NMIPLL0CLR (Bitfield-Mask: 0x01)

◆ SCU_NMISRC_NMIPLL0CLR_Pos [1/2]

#define SCU_NMISRC_NMIPLL0CLR_Pos   (1UL)

NMIPLL0CLR (Bit 1)

◆ SCU_NMISRC_NMIPLL0CLR_Pos [2/2]

#define SCU_NMISRC_NMIPLL0CLR_Pos   (1UL)

NMIPLL0CLR (Bit 1)

◆ SCU_NMISRC_NMIPLL1CLR_Msk [1/2]

#define SCU_NMISRC_NMIPLL1CLR_Msk   (0x4UL)

NMIPLL1CLR (Bitfield-Mask: 0x01)

◆ SCU_NMISRC_NMIPLL1CLR_Msk [2/2]

#define SCU_NMISRC_NMIPLL1CLR_Msk   (0x4UL)

NMIPLL1CLR (Bitfield-Mask: 0x01)

◆ SCU_NMISRC_NMIPLL1CLR_Pos [1/2]

#define SCU_NMISRC_NMIPLL1CLR_Pos   (2UL)

NMIPLL1CLR (Bit 2)

◆ SCU_NMISRC_NMIPLL1CLR_Pos [2/2]

#define SCU_NMISRC_NMIPLL1CLR_Pos   (2UL)

NMIPLL1CLR (Bit 2)

◆ SCU_NMISRC_NMIXTALCLR_Msk [1/2]

#define SCU_NMISRC_NMIXTALCLR_Msk   (0x1UL)

NMIXTALCLR (Bitfield-Mask: 0x01)

◆ SCU_NMISRC_NMIXTALCLR_Msk [2/2]

#define SCU_NMISRC_NMIXTALCLR_Msk   (0x1UL)

NMIXTALCLR (Bitfield-Mask: 0x01)

◆ SCU_NMISRC_NMIXTALCLR_Pos [1/2]

#define SCU_NMISRC_NMIXTALCLR_Pos   (0UL)

NMIXTALCLR (Bit 0)

◆ SCU_NMISRC_NMIXTALCLR_Pos [2/2]

#define SCU_NMISRC_NMIXTALCLR_Pos   (0UL)

NMIXTALCLR (Bit 0)

◆ SCU_PMCON_GPT12_DIS_Msk [1/2]

#define SCU_PMCON_GPT12_DIS_Msk   (0x10UL)

GPT12_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_GPT12_DIS_Msk [2/2]

#define SCU_PMCON_GPT12_DIS_Msk   (0x10UL)

GPT12_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_GPT12_DIS_Pos [1/2]

#define SCU_PMCON_GPT12_DIS_Pos   (4UL)

GPT12_DIS (Bit 4)

◆ SCU_PMCON_GPT12_DIS_Pos [2/2]

#define SCU_PMCON_GPT12_DIS_Pos   (4UL)

GPT12_DIS (Bit 4)

◆ SCU_PMCON_SSC0_DIS_Msk [1/2]

#define SCU_PMCON_SSC0_DIS_Msk   (0x1UL)

SSC0_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_SSC0_DIS_Msk [2/2]

#define SCU_PMCON_SSC0_DIS_Msk   (0x1UL)

SSC0_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_SSC0_DIS_Pos [1/2]

#define SCU_PMCON_SSC0_DIS_Pos   (0UL)

SSC0_DIS (Bit 0)

◆ SCU_PMCON_SSC0_DIS_Pos [2/2]

#define SCU_PMCON_SSC0_DIS_Pos   (0UL)

SSC0_DIS (Bit 0)

◆ SCU_PMCON_SSC1_DIS_Msk [1/2]

#define SCU_PMCON_SSC1_DIS_Msk   (0x2UL)

SSC1_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_SSC1_DIS_Msk [2/2]

#define SCU_PMCON_SSC1_DIS_Msk   (0x2UL)

SSC1_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_SSC1_DIS_Pos [1/2]

#define SCU_PMCON_SSC1_DIS_Pos   (1UL)

SSC1_DIS (Bit 1)

◆ SCU_PMCON_SSC1_DIS_Pos [2/2]

#define SCU_PMCON_SSC1_DIS_Pos   (1UL)

SSC1_DIS (Bit 1)

◆ SCU_PMCON_T21_DIS_Msk [1/2]

#define SCU_PMCON_T21_DIS_Msk   (0x8UL)

T21_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_T21_DIS_Msk [2/2]

#define SCU_PMCON_T21_DIS_Msk   (0x8UL)

T21_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_T21_DIS_Pos [1/2]

#define SCU_PMCON_T21_DIS_Pos   (3UL)

T21_DIS (Bit 3)

◆ SCU_PMCON_T21_DIS_Pos [2/2]

#define SCU_PMCON_T21_DIS_Pos   (3UL)

T21_DIS (Bit 3)

◆ SCU_PMCON_T2_DIS_Msk [1/2]

#define SCU_PMCON_T2_DIS_Msk   (0x4UL)

T2_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_T2_DIS_Msk [2/2]

#define SCU_PMCON_T2_DIS_Msk   (0x4UL)

T2_DIS (Bitfield-Mask: 0x01)

◆ SCU_PMCON_T2_DIS_Pos [1/2]

#define SCU_PMCON_T2_DIS_Pos   (2UL)

T2_DIS (Bit 2)

◆ SCU_PMCON_T2_DIS_Pos [2/2]

#define SCU_PMCON_T2_DIS_Pos   (2UL)

T2_DIS (Bit 2)

◆ SCU_XTALCON_XPD_Msk [1/2]

#define SCU_XTALCON_XPD_Msk   (0x1UL)

XPD (Bitfield-Mask: 0x01)

◆ SCU_XTALCON_XPD_Msk [2/2]

#define SCU_XTALCON_XPD_Msk   (0x1UL)

XPD (Bitfield-Mask: 0x01)

◆ SCU_XTALCON_XPD_Pos [1/2]

#define SCU_XTALCON_XPD_Pos   (0UL)

XPD (Bit 0)

◆ SCU_XTALCON_XPD_Pos [2/2]

#define SCU_XTALCON_XPD_Pos   (0UL)

XPD (Bit 0)

◆ SCU_XTALCON_XTALSHBYEN_Msk

#define SCU_XTALCON_XTALSHBYEN_Msk   (0x4UL)

XTALSHBYEN (Bitfield-Mask: 0x01)

◆ SCU_XTALCON_XTALSHBYEN_Pos

#define SCU_XTALCON_XTALSHBYEN_Pos   (2UL)

XTALSHBYEN (Bit 2)

◆ SCU_XTALCON_XTALSHDIS_Msk

#define SCU_XTALCON_XTALSHDIS_Msk   (0x8UL)

XTALSHDIS (Bitfield-Mask: 0x01)

◆ SCU_XTALCON_XTALSHDIS_Pos

#define SCU_XTALCON_XTALSHDIS_Pos   (3UL)

XTALSHDIS (Bit 3)

◆ SCU_XTALSTATC_XTAL_FAIL_STSCLR_Msk [1/2]

#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Msk   (0x1UL)

XTAL_FAIL_STSCLR (Bitfield-Mask: 0x01)

◆ SCU_XTALSTATC_XTAL_FAIL_STSCLR_Msk [2/2]

#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Msk   (0x1UL)

XTAL_FAIL_STSCLR (Bitfield-Mask: 0x01)

◆ SCU_XTALSTATC_XTAL_FAIL_STSCLR_Pos [1/2]

#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Pos   (0UL)

XTAL_FAIL_STSCLR (Bit 0)

◆ SCU_XTALSTATC_XTAL_FAIL_STSCLR_Pos [2/2]

#define SCU_XTALSTATC_XTAL_FAIL_STSCLR_Pos   (0UL)

XTAL_FAIL_STSCLR (Bit 0)

◆ UART0_BCON_BR_R_Msk [1/2]

#define UART0_BCON_BR_R_Msk   (0x1UL)

BR_R (Bitfield-Mask: 0x01)

◆ UART0_BCON_BR_R_Msk [2/2]

#define UART0_BCON_BR_R_Msk   (0x1UL)

BR_R (Bitfield-Mask: 0x01)

◆ UART0_BCON_BR_R_Pos [1/2]

#define UART0_BCON_BR_R_Pos   (0UL)

BR_R (Bit 0)

◆ UART0_BCON_BR_R_Pos [2/2]

#define UART0_BCON_BR_R_Pos   (0UL)

BR_R (Bit 0)

◆ UART0_SCON_SM1_Msk [1/2]

#define UART0_SCON_SM1_Msk   (0x2UL)

SM1 (Bitfield-Mask: 0x01)

◆ UART0_SCON_SM1_Msk [2/2]

#define UART0_SCON_SM1_Msk   (0x2UL)

SM1 (Bitfield-Mask: 0x01)

◆ UART0_SCON_SM1_Pos [1/2]

#define UART0_SCON_SM1_Pos   (1UL)

SM1 (Bit 1)

◆ UART0_SCON_SM1_Pos [2/2]

#define UART0_SCON_SM1_Pos   (1UL)

SM1 (Bit 1)

◆ UART1_BCON_BR_R_Msk [1/2]

#define UART1_BCON_BR_R_Msk   (0x1UL)

BR_R (Bitfield-Mask: 0x01)

◆ UART1_BCON_BR_R_Msk [2/2]

#define UART1_BCON_BR_R_Msk   (0x1UL)

BR_R (Bitfield-Mask: 0x01)

◆ UART1_BCON_BR_R_Pos [1/2]

#define UART1_BCON_BR_R_Pos   (0UL)

BR_R (Bit 0)

◆ UART1_BCON_BR_R_Pos [2/2]

#define UART1_BCON_BR_R_Pos   (0UL)

BR_R (Bit 0)

◆ UART1_SCON_SM1_Msk [1/2]

#define UART1_SCON_SM1_Msk   (0x2UL)

SM1 (Bitfield-Mask: 0x01)

◆ UART1_SCON_SM1_Msk [2/2]

#define UART1_SCON_SM1_Msk   (0x2UL)

SM1 (Bitfield-Mask: 0x01)

◆ UART1_SCON_SM1_Pos [1/2]

#define UART1_SCON_SM1_Pos   (1UL)

SM1 (Bit 1)

◆ UART1_SCON_SM1_Pos [2/2]

#define UART1_SCON_SM1_Pos   (1UL)

SM1 (Bit 1)