Infineon MOTIX™ MCU TLE987x Device Family SDK
dma.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
22 /*******************************************************************************
23 ** Author(s) Identity **
24 ********************************************************************************
25 ** Initials Name **
26 ** ---------------------------------------------------------------------------**
27 ** DM Daniel Mysliwitz **
28 ** BG Blandine Guillot **
29 ** JO Julia Ott **
30 ** VO Vanessa Ongaro **
31 *******************************************************************************/
32 
33 /*******************************************************************************
34 ** Revision Control History **
35 ********************************************************************************
36 ** V0.1.0: 2015-11-25, DM: Initial version **
37 ** V0.1.1: 2017-07-09, DM: Interrupt macros added **
38 ** Scatter-gather support added **
39 ** V0.1.2: 2017-07-12, DM: Setup task for scatter-gather added **
40 ** V0.1.3: 2017-07-20, DM: API macros added **
41 ** V0.1.4: 2017-09-22, DM: MISRA 2012 compliance, the following PC-Lint **
42 ** rules are globally deactivated: **
43 ** - Info 793: ANSI/ISO limit of 6 'significant **
44 ** characters in an external identifier **
45 ** - Note 950: Non-ANSI reserved word or construct: **
46 ** '_to_brackets' [MISRA Rule 1] **
47 ** - Note 923: cast from unsigned int to pointer **
48 ** [MISRA Rule 45] **
49 ** - Note 923: cast from pointer to unsigned int **
50 ** [MISRA Rule 45] **
51 ** - Info 765: Info 765: external '...' could be **
52 ** made static [MISRA Rule 23] **
53 ** - Error 18: Symbol '..' redeclared (void/nonvoid)**
54 ** ... [MISRA Rule 26],[Encompasses MISRA Rule 72]**
55 ** V0.1.5: 2018-03-12, DM: DMA Ch13 (SDADC) added **
56 ** DMA_MASK_CHx macros changed due to MISRA 2012 **
57 ** Replaced macros by INLINE functions **
58 ** Replaced register accesses within functions by **
59 ** function calls **
60 ** Replaced __STATIC_INLINE by INLINE **
61 ** Renamed DMA entries according to channel number **
62 ** V0.1.6: 2018-11-27, JO: Doxygen update **
63 ** Moved revision history from dma.c to dma.h **
64 ** V0.1.7: 2019-02-21, DM: DMA structures modified to be ARMCC v6 compliant **
65 ** DMA base structure set to upper most address **
66 ** 3KB RAM: 0x18000A00..0x18000BFF **
67 ** 6KB RAM: 0x18001600..0x180017FF **
68 ** 8KB RAM: 0x18001E00..0x18001FFF **
69 ** V0.1.8: 2020-04-15, BG: Updated revision history format **
70 ** V0.1.9: 2020-07-14, JO: EP-431: remove ARMCC v6 Compiler warnings **
71 ** - Initialized alternate table entry **
72 ** - Disabled ARMCC v6 warnings -Wmissing-variable- **
73 ** declarations, -Wunreachable-code, and **
74 ** -Wpedantic locally in file dma.c **
75 ** V0.2.0: 2020-07-21, BG: EP-439: Formatted .h/.c files **
76 ** V0.2.1: 2020-10-28, DM: EP-565: Set DMA struct to volatile to remove **
77 ** ARMCC v6 O3 LTO problem **
78 ** V0.2.2: 2021-02-01, BG: EP-175: Updated code for compatibility with **
79 ** IAR compiler **
80 ** V0.2.3: 2022-02-28, JO: EP-936: Updated copyright and branding **
81 ** V0.2.4: 2022-10-18, VO: EP-1252: Removed ARMCC V6.18 warnings **
82 ** V0.2.5: 2023-03-09, BG: EP-1012: Included GCC compatibility in the DMA **
83 ** channel structure definitions **
84 ** V0.2.6: 2024-11-20, JO: EP-1547: Corrected function DMA_Setup_Channel **
85 ** V0.2.7: 2025-01-02, JO: EP-1493: Updated license **
86 *******************************************************************************/
87 
88 #ifndef _DMA_H
89 #define _DMA_H
90 
91 /*******************************************************************************
92 ** Includes **
93 *******************************************************************************/
94 #include "tle987x.h"
95 #include "types.h"
96 #include "dma_defines.h"
97 #include "sfr_access.h"
98 
99 /*******************************************************************************
100 ** Global Macro Definitions **
101 *******************************************************************************/
103 #define DMA_CH0 (0u)
105 #define DMA_CH1 (1u)
107 #define DMA_CH2 (2u)
109 #define DMA_CH3 (3u)
111 #define DMA_CH4 (4u)
113 #define DMA_CH5 (5u)
115 #define DMA_CH6 (6u)
117 #define DMA_CH7 (7u)
119 #define DMA_CH8 (8u)
121 #define DMA_CH9 (9u)
123 #define DMA_CH10 (10u)
125 #define DMA_CH11 (11u)
127 #define DMA_CH12 (12u)
128 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
130  #define DMA_CH13 (13u)
131 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
132 
134 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
136 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
138 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
140 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
142 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
144 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
146 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
148 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
150 #define DMA_MASK_CH8 ((uint16)1u << DMA_CH8)
152 #define DMA_MASK_CH9 ((uint16)1u << DMA_CH9)
154 #define DMA_MASK_CH10 ((uint16)1u << DMA_CH10)
156 #define DMA_MASK_CH11 ((uint16)1u << DMA_CH11)
158 #define DMA_MASK_CH12 ((uint16)1u << DMA_CH12)
159 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
161  #define DMA_MASK_CH13 ((uint16)1u << DMA_CH13)
162 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
163 
165 #define DMA_SRC_INCREMENT 1u
167 #define DMA_DEST_INCREMENT 2u
168 
172 typedef enum DMA_Transfer_Size
173 {
176  DMA_32Bit_Transfer = 2u
178 
182 typedef enum DMA_Increment_Size
183 {
186  DMA_Inc_32bit = 2u
188 
192 typedef enum DMA_Increment_Mode
193 {
194  DMA_No_Inc = 0u,
199 
203 typedef enum DMA_Cycle_Types
204 {
214 
215 /*******************************************************************************
216 ** Global Type Definitions **
217 *******************************************************************************/
221 typedef union
222 {
224  struct
225  {
236  } bit;
237 } TControl;
238 
242 typedef struct
243 {
248 } TDMA_Entry;
249 
250 
251 /*******************************************************************************
252 ** Global Inline Function Definitions **
253 *******************************************************************************/
272 {
274 }
275 
294 {
296 }
297 
316 {
318 }
319 
338 {
340 }
341 
360 {
362 }
363 
382 {
384 }
385 
404 {
406 }
407 
426 {
428 }
429 
448 {
450 }
451 
470 {
472 }
473 
492 {
494 }
495 
514 {
516 }
517 
536 {
538 }
539 
540 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
559 {
561 }
562 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
563 
582 {
584 }
585 
605 {
607 }
608 
627 {
629 }
630 
650 {
652 }
653 
672 {
674 }
675 
695 {
697 }
698 
717 {
719 }
720 
740 {
742 }
743 
762 {
764 }
765 
785 {
787 }
788 
807 {
809 }
810 
830 {
832 }
833 
852 {
854 }
855 
875 {
877 }
878 
897 {
899 }
900 
920 {
922 }
923 
942 {
944 }
945 
965 {
967 }
968 
987 {
989 }
990 
1010 {
1012 }
1013 
1032 {
1034 }
1035 
1055 {
1057 }
1058 
1077 {
1079 }
1080 
1100 {
1102 }
1103 
1122 {
1124 }
1125 
1145 {
1147 }
1148 
1149 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
1168 {
1170 }
1171 
1191 {
1193 }
1194 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
1195 
1212 {
1214 }
1215 
1232 {
1234 }
1235 
1252 {
1254 }
1255 
1272 {
1274 }
1275 
1292 {
1294 }
1295 
1304 {
1305  return ( (uint32)(DMA->ALT_CTRL_BASE_PTR.reg + (DMA_Ch * sizeof(TDMA_Entry))) );
1306 }
1307 
1316 {
1317  return ( (uint32)(DMA->CTRL_BASE_PTR.reg + (DMA_Ch * sizeof(TDMA_Entry))) );
1318 }
1319 
1320 /*******************************************************************************
1321 ** Global Function Declarations **
1322 *******************************************************************************/
1323 #if (DMA_XML_VERSION >= 10200)
1324 
1329 void DMA_Init(void);
1330 
1363 void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst,
1364  uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment);
1365 
1366 
1401 void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt);
1402 
1448 TDMA_Entry *DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask);
1449 
1490 void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks);
1491 
1492 
1531 void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks);
1532 
1575 TDMA_Entry *DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst,
1576  uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment);
1577 
1602 INLINE void DMA_Master_En(void);
1603 
1604 /*******************************************************************************
1605 ** Global Inline Function Definitions **
1606 *******************************************************************************/
1608 {
1609  /* arm the DMA */
1610  DMA->CFG.bit.MASTER_ENABLE = 1u;
1611 }
1612 #else
1613 #error "use IFXConfigWizard XML Version V1.2.0 or greater"
1614 #endif
1615 
1616 #endif
INLINE void DMA_CH0_Int_Clr(void)
clears DMA Channel 0 Interrupt flag.
Definition: dma.h:271
INLINE void DMA_Master_En(void)
Enabled the DMA master.
Definition: dma.h:1607
INLINE void DMA_CH10_Int_Dis(void)
disables DMA Channel 10 Interrupt.
Definition: dma.h:1054
INLINE void DMA_CH10_Int_Clr(void)
clears DMA Channel 10 Interrupt flag.
Definition: dma.h:491
INLINE uint32 DMA_CHx_Entry_Alt(uint8 DMA_Ch)
This function returns the address inside the alternate structure in RAM for a given DMA channel.
Definition: dma.h:1303
INLINE void DMA_CH5_Int_Dis(void)
disables DMA Channel 5 Interrupt.
Definition: dma.h:829
enum DMA_Increment_Size TDMA_Increment_Size
INLINE void DMA_CH11_Int_En(void)
enables DMA Channel 11 Interrupt.
Definition: dma.h:1076
INLINE void DMA_CH3_Int_Clr(void)
clears DMA Channel 3 Interrupt flag.
Definition: dma.h:337
DMA_Transfer_Size
Definition: dma.h:173
@ DMA_32Bit_Transfer
Definition: dma.h:176
@ DMA_8Bit_Transfer
Definition: dma.h:174
@ DMA_16Bit_Transfer
Definition: dma.h:175
INLINE void DMA_CH5_Int_En(void)
enables DMA Channel 5 Interrupt.
Definition: dma.h:806
INLINE void DMA_CH6_Int_Dis(void)
disables DMA Channel 6 Interrupt.
Definition: dma.h:874
INLINE void DMA_CH9_Int_Dis(void)
disables DMA Channel 9 Interrupt.
Definition: dma.h:1009
enum DMA_Cycle_Types TDMA_Cycle_Types
INLINE void DMA_CH0_Int_En(void)
enables DMA Channel 0 Interrupt.
Definition: dma.h:581
INLINE void DMA_CH13_Int_Clr(void)
clears DMA Channel 13 Interrupt flag.
Definition: dma.h:558
INLINE void DMA_CH7_Int_Clr(void)
clears DMA Channel 7 Interrupt flag.
Definition: dma.h:425
INLINE void DMA_CH1_Int_Dis(void)
disables DMA Channel 1 Interrupt.
Definition: dma.h:649
INLINE void DMA_CH4_Int_Dis(void)
disables DMA Channel 4 Interrupt.
Definition: dma.h:784
enum DMA_Increment_Mode TDMA_Increment_Mode
INLINE void DMA_CH11_Int_Dis(void)
disables DMA Channel 11 Interrupt.
Definition: dma.h:1099
INLINE void DMA_Primary_Struct_Usage_Set(uint32 mask_ch)
selects the primary data structure for the corresponding DMA channel.
Definition: dma.h:1271
DMA_Increment_Mode
Definition: dma.h:193
@ DMA_No_Inc
Definition: dma.h:194
@ DMA_Src_Inc
Definition: dma.h:195
@ DMA_Dst_Inc
Definition: dma.h:196
@ DMA_Src_Dst_Inc
Definition: dma.h:197
INLINE void DMA_CH0_Int_Dis(void)
disables DMA Channel 0 Interrupt.
Definition: dma.h:604
void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt)
Resets the primary structure in RAM for a given channel and rearms it.
INLINE void DMA_CH13_Int_Dis(void)
disables DMA Channel 13 Interrupt.
Definition: dma.h:1190
INLINE void DMA_CH9_Int_En(void)
enables DMA Channel 9 Interrupt.
Definition: dma.h:986
INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
enables DMA Channels.
Definition: dma.h:1231
#define DMA_SRC_INCREMENT
DMA source increment.
Definition: dma.h:165
INLINE void DMA_CH4_Int_Clr(void)
clears DMA Channel 4 Interrupt flag.
Definition: dma.h:359
INLINE void DMA_CH11_Int_Clr(void)
clears DMA Channel 11 Interrupt flag.
Definition: dma.h:513
INLINE void DMA_CH2_Int_Dis(void)
disables DMA Channel 2 Interrupt.
Definition: dma.h:694
TDMA_Entry * DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up a task to be used in the Scatter-Gather modes.
INLINE void DMA_CH3_Int_En(void)
enables DMA Channel 3 Interrupt.
Definition: dma.h:716
INLINE void DMA_CH8_Int_En(void)
enables DMA Channel 8 Interrupt.
Definition: dma.h:941
INLINE void DMA_CH6_Int_En(void)
enables DMA Channel 6 Interrupt.
Definition: dma.h:851
INLINE void DMA_CH1_Int_Clr(void)
clears DMA Channel 1 Interrupt flag.
Definition: dma.h:293
DMA_Cycle_Types
Definition: dma.h:204
@ DMA_Cycle_Type_PerSctGthPrim
Definition: dma.h:211
@ DMA_Cycle_Type_Basic
Definition: dma.h:206
@ DMA_Cycle_Type_MemSctGthPrim
Definition: dma.h:209
@ DMA_Cycle_Type_Auto
Definition: dma.h:207
@ DMA_Cycle_Type_PingPong
Definition: dma.h:208
@ DMA_Cycle_Type_MemSctGthAlt
Definition: dma.h:210
@ DMA_Cycle_Type_PerSctGthAlt
Definition: dma.h:212
@ DMA_Cycle_Type_Invalid
Definition: dma.h:205
INLINE void DMA_CH7_Int_Dis(void)
disables DMA Channel 7 Interrupt.
Definition: dma.h:919
INLINE void DMA_CH5_Int_Clr(void)
clears DMA Channel 5 Interrupt flag.
Definition: dma.h:381
INLINE void DMA_CH12_Int_Dis(void)
disables DMA Channel 12 Interrupt.
Definition: dma.h:1144
void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up the desired DMA channel in the primary structure in RAM.
INLINE void DMA_CH2_Int_Clr(void)
clears DMA Channel 2 Interrupt flag.
Definition: dma.h:315
INLINE void DMA_CH1_Int_En(void)
enables DMA Channel 1 Interrupt.
Definition: dma.h:626
INLINE void DMA_Alternate_Struct_Usage_Set(uint32 mask_ch)
selects the alternate data structure for the corresponding DMA channel.
Definition: dma.h:1291
void DMA_Init(void)
Initializes the DMA structure in RAM and SFRs based on the Config Wizard for MOTIX MCU configuration.
INLINE void DMA_Software_Request_Set(uint32 mask_ch)
Set software request for DMA Channels.
Definition: dma.h:1251
INLINE void DMA_CH7_Int_En(void)
enables DMA Channel 7 Interrupt.
Definition: dma.h:896
enum DMA_Transfer_Size TDMA_Transfer_Size
INLINE void DMA_CH3_Int_Dis(void)
disables DMA Channel 3 Interrupt.
Definition: dma.h:739
INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
points to the base address of the primary data structure.
Definition: dma.h:1211
INLINE void DMA_CH13_Int_En(void)
enables DMA Channel 13 Interrupt.
Definition: dma.h:1167
INLINE void DMA_CH9_Int_Clr(void)
clears DMA Channel 9 Interrupt flag.
Definition: dma.h:469
INLINE void DMA_CH6_Int_Clr(void)
clears DMA Channel 6 Interrupt flag.
Definition: dma.h:403
void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.
void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
INLINE void DMA_CH2_Int_En(void)
enables DMA Channel 2 Interrupt.
Definition: dma.h:671
INLINE void DMA_CH4_Int_En(void)
enables DMA Channel 4 Interrupt.
Definition: dma.h:761
DMA_Increment_Size
Definition: dma.h:183
@ DMA_Inc_8bit
Definition: dma.h:184
@ DMA_Inc_32bit
Definition: dma.h:186
@ DMA_Inc_16bit
Definition: dma.h:185
INLINE uint32 DMA_CHx_Entry_Pri(uint8 DMA_Ch)
This function returns the address inside the primary structure in RAM for a given DMA channel.
Definition: dma.h:1315
#define DMA_DEST_INCREMENT
DMA destination increment.
Definition: dma.h:167
INLINE void DMA_CH10_Int_En(void)
enables DMA Channel 10 Interrupt.
Definition: dma.h:1031
INLINE void DMA_CH8_Int_Dis(void)
disables DMA Channel 8 Interrupt.
Definition: dma.h:964
INLINE void DMA_CH12_Int_Clr(void)
clears DMA Channel 12 Interrupt flag.
Definition: dma.h:535
INLINE void DMA_CH8_Int_Clr(void)
clears DMA Channel 8 Interrupt flag.
Definition: dma.h:447
INLINE void DMA_CH12_Int_En(void)
enables DMA Channel 12 Interrupt.
Definition: dma.h:1121
TDMA_Entry * DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
Sets up a task to be used with memory scatter-gather mode.
#define DMA
Definition: tle987x.h:6064
#define SCU
Definition: tle987x.h:6071
#define SCU_DMAIRC1CLR_CH8C_Pos
Definition: tle987x.h:8833
#define SCU_DMAIEN1_CH1IE_Msk
Definition: tle987x.h:8799
#define SCU_DMAIEN1_CH7IE_Pos
Definition: tle987x.h:8786
#define SCU_DMAIRC2CLR_SDADCC_Pos
Definition: tle987x.h:8865
#define SCU_DMAIRC1CLR_CH7C_Pos
Definition: tle987x.h:8835
#define SCU_DMAIRC2CLR_SSC1C_Pos
Definition: tle987x.h:8871
#define SCU_DMAIRC1CLR_CH4C_Pos
Definition: tle987x.h:8841
#define SCU_DMAIRC2CLR_SSC1C_Msk
Definition: tle987x.h:8872
#define SCU_DMAIEN2_SSCTXIE_Pos
Definition: tle987x.h:8807
#define SCU_DMAIEN1_CH3IE_Pos
Definition: tle987x.h:8794
#define SCU_DMAIRC1CLR_CH5C_Pos
Definition: tle987x.h:8839
#define SCU_DMAIRC1CLR_CH1C_Msk
Definition: tle987x.h:8848
#define SCU_DMAIEN2_TRSEQ2RDYIE_Pos
Definition: tle987x.h:8809
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk
Definition: tle987x.h:7896
#define SCU_DMAIEN2_SDADCIE_Msk
Definition: tle987x.h:8802
#define SCU_DMAIRC1CLR_CH1C_Pos
Definition: tle987x.h:8847
#define SCU_DMAIEN1_CH8IE_Msk
Definition: tle987x.h:8785
#define SCU_DMAIRC1CLR_CH2C_Pos
Definition: tle987x.h:8845
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos
Definition: tle987x.h:7892
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos
Definition: tle987x.h:8875
#define SCU_DMAIEN2_GPT12IE_Pos
Definition: tle987x.h:8803
#define SCU_DMAIEN1_CH5IE_Pos
Definition: tle987x.h:8790
#define SCU_DMAIEN1_CH2IE_Pos
Definition: tle987x.h:8796
#define SCU_DMAIEN1_CH6IE_Msk
Definition: tle987x.h:8789
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos
Definition: tle987x.h:7895
#define SCU_DMAIRC1CLR_CH7C_Msk
Definition: tle987x.h:8836
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk
Definition: tle987x.h:7923
#define SCU_DMAIRC1CLR_CH3C_Msk
Definition: tle987x.h:8844
#define SCU_DMAIRC1CLR_CH2C_Msk
Definition: tle987x.h:8846
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos
Definition: tle987x.h:8873
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk
Definition: tle987x.h:7914
#define SCU_DMAIEN1_CH3IE_Msk
Definition: tle987x.h:8795
#define SCU_DMAIRC1CLR_CH5C_Msk
Definition: tle987x.h:8840
#define SCU_DMAIEN1_CH4IE_Pos
Definition: tle987x.h:8792
#define SCU_DMAIEN1_CH7IE_Msk
Definition: tle987x.h:8787
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk
Definition: tle987x.h:7899
#define SCU_DMAIRC1CLR_CH8C_Msk
Definition: tle987x.h:8834
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk
Definition: tle987x.h:8874
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos
Definition: tle987x.h:7898
#define SCU_DMAIEN2_SDADCIE_Pos
Definition: tle987x.h:8801
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos
Definition: tle987x.h:7913
#define SCU_DMAIRC2CLR_GPT12C_Msk
Definition: tle987x.h:8868
#define SCU_DMAIEN2_TRSEQ1RDYIE_Msk
Definition: tle987x.h:8812
#define SCU_DMAIEN1_CH4IE_Msk
Definition: tle987x.h:8793
#define SCU_DMAIEN2_SSCRXIE_Msk
Definition: tle987x.h:8806
#define SCU_DMAIRC1CLR_CH6C_Pos
Definition: tle987x.h:8837
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos
Definition: tle987x.h:7922
#define SCU_DMAIEN2_GPT12IE_Msk
Definition: tle987x.h:8804
#define SCU_DMAIEN1_CH5IE_Msk
Definition: tle987x.h:8791
#define SCU_DMAIRC2CLR_SSC2C_Msk
Definition: tle987x.h:8870
#define SCU_DMAIEN2_SSCRXIE_Pos
Definition: tle987x.h:8805
#define SCU_DMAIRC1CLR_CH6C_Msk
Definition: tle987x.h:8838
#define SCU_DMAIRC2CLR_GPT12C_Pos
Definition: tle987x.h:8867
#define SCU_DMAIEN1_CH6IE_Pos
Definition: tle987x.h:8788
#define SCU_DMAIEN1_CH8IE_Pos
Definition: tle987x.h:8784
#define SCU_DMAIEN1_CH2IE_Msk
Definition: tle987x.h:8797
#define SCU_DMAIEN2_TRSEQ2RDYIE_Msk
Definition: tle987x.h:8810
#define SCU_DMAIEN2_TRSEQ1RDYIE_Pos
Definition: tle987x.h:8811
#define SCU_DMAIEN1_CH1IE_Pos
Definition: tle987x.h:8798
#define SCU_DMAIRC1CLR_CH4C_Msk
Definition: tle987x.h:8842
#define SCU_DMAIRC2CLR_SSC2C_Pos
Definition: tle987x.h:8869
#define SCU_DMAIRC2CLR_SDADCC_Msk
Definition: tle987x.h:8866
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk
Definition: tle987x.h:8876
#define SCU_DMAIEN2_SSCTXIE_Msk
Definition: tle987x.h:8808
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk
Definition: tle987x.h:7893
#define SCU_DMAIRC1CLR_CH3C_Pos
Definition: tle987x.h:8843
SFR low level access library.
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:322
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:347
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
This structure lists the DMA transfer memory locations.
Definition: dma.h:243
uint32 Dst_End_Ptr
Definition: dma.h:245
uint32 Src_End_Ptr
Definition: dma.h:244
uint32 reserved
Definition: dma.h:247
TControl Control
Definition: dma.h:246
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:132
uint8_t uint8
8 bit unsigned value
Definition: types.h:137
uint32_t uint32
32 bit unsigned value
Definition: types.h:139
This structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:222
uint32 Dst_Inc
Bit[31..30].
Definition: dma.h:235
uint32 Cycle_Ctrl
Bit[2..0].
Definition: dma.h:226
uint32 R_Power
Bit[17..14].
Definition: dma.h:229
uint32 Src_Prot_Ctrl
Bit[20..18].
Definition: dma.h:230
uint32 Dst_Size
Bit[29..28].
Definition: dma.h:234
uint32 Next_UseBurst
Bit[3].
Definition: dma.h:227
uint32 Src_Inc
Bit[27..26].
Definition: dma.h:233
uint32 Dst_Prot_Ctrl
Bit[23..21].
Definition: dma.h:231
uint32 N_Minus_1
Bit[13..4].
Definition: dma.h:228
uint32 reg
Definition: dma.h:223
uint32 Src_Size
Bit[25..24].
Definition: dma.h:232