Infineon MOTIX™ MCU TLE987x Device Family SDK
tle987x.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
22 /*******************************************************************************
23 ** Author(s) Identity **
24 ********************************************************************************
25 ** **
26 ** Initials Name **
27 ** ---------------------------------------------------------------------------**
28 ** BG Blandine Guillot **
29 ** JO Julia Ott **
30 *******************************************************************************/
31 
32 /*******************************************************************************
33 ** Revision Control History **
34 ********************************************************************************
35 ** V3.0.4: 2020-04-15, BG: Initial version of revision history **
36 ** V3.0.5: 2020-07-16, JO: EP-392: Added field ADC2->CTRL2.bit.SEL_TS_COUNT **
37 ** V3.0.6: 2020-07-14, JO: EP-431: Added '#pragma clang diagnostic ignored' **
38 ** to disable compiler warnings (-Wpadded, **
39 ** -Wcovered-switch-default, -Wself-assign) for **
40 ** ARMCC v6 **
41 ** V3.0.7: 2020-07-21, BG: EP-439: Formatted .h/.c files **
42 ** V3.0.8: 2021-08-25, JO: EP-919: Corrected ADC2 Ch assignment comments **
43 ** V3.0.9: 2022-02-28, JO: EP-936: Updated copyright and branding **
44 ** V3.1.0: 2024-11-06, JO: EP-1550: Removed '#pragma clang diagnostic', **
45 ** not needed with ARMCC V6.22 **
46 ** V3.1.1: 2025-01-02, JO: EP-1493: Updated license **
47 *******************************************************************************/
48 
49 
60 #ifndef TLE987X_H
61 #define TLE987X_H
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 
74 /* =========================================================================================================================== */
75 /* ================ Interrupt Number Definition ================ */
76 /* =========================================================================================================================== */
77 
78 typedef enum
79 {
80  /* ======================================= ARM Cortex-M3 Specific Interrupt Numbers ======================================== */
81  Reset_IRQn = -15,
84  MemoryManagement_IRQn = -12,
86  BusFault_IRQn = -11,
89  SVCall_IRQn = -5,
91  PendSV_IRQn = -2,
92  SysTick_IRQn = -1,
93  /* ========================================== TLE987x Specific Interrupt Numbers =========================================== */
94  GPT1_Int = 0,
95  GPT2_Int = 1,
102  SSC1_Int = 8,
103  SSC2_Int = 9,
107  EXINT1_Int = 13,
108  BDRV_CP_Int = 14,
109  DMA_Int = 15
111 
112 
113 
114 /* =========================================================================================================================== */
115 /* ================ Processor and Core Peripheral Section ================ */
116 /* =========================================================================================================================== */
117 
118 /* =========================== Configuration of the ARM Cortex-M3 Processor and Core Peripherals =========================== */
119 #define __CM3_REV 0x0000U
120 #define __NVIC_PRIO_BITS 4
121 #define __Vendor_SysTickConfig 0
122 #define __MPU_PRESENT 0
123 #define __FPU_PRESENT 0 /* End of group Configuration_of_CMSIS */
127 
128 #include "core_cm3.h"
129 #include "system_tle987x.h"
131 #ifndef __IM
132 #define __IM __I
133 #endif
134 #ifndef __OM
135 #define __OM __O
136 #endif
137 #ifndef __IOM
138 #define __IOM __IO
139 #endif
140 
141 #ifdef UNIT_TESTING_LV2
142 #undef __IM
143 #define __IM volatile
144 #endif
145 
146 /* =========================================================================================================================== */
147 /* ================ Device Specific Peripheral Section ================ */
148 /* =========================================================================================================================== */
149 
150 
157 /* =========================================================================================================================== */
158 /* ================ ADC1 ================ */
159 /* =========================================================================================================================== */
160 
161 
166 typedef struct
167 {
168 
169  union
170  {
171  __IOM uint32_t reg;
173  struct
174  {
175  __IOM uint32_t PD_N : 1;
177  __IOM uint32_t SOC : 1;
178  __IM uint32_t EOC : 1;
179  __IOM uint32_t IN_MUX_SEL : 3;
180  } bit;
181  } CTRL_STS;
182 
183  union
184  {
185  __IOM uint32_t reg;
187  struct
188  {
189  __IOM uint32_t DIVA : 6;
192  __IM uint32_t : 2;
193  __IOM uint32_t ANON : 2;
194  } bit;
195  } GLOBCTR;
196 
197  union
198  {
199  __IOM uint32_t reg;
202  struct
203  {
204  __IOM uint32_t CHx : 3;
205  __IM uint32_t : 1;
206  __IOM uint32_t REP : 3;
207  __IM uint32_t : 9;
208  __IOM uint32_t TRIG_SEL : 3;
210  } bit;
211  } CHx_EIM;
212 
213  union
214  {
215  __IOM uint32_t reg;
218  struct
219  {
220  __IOM uint32_t ESM_0 : 8;
222  __IM uint32_t : 8;
223  __IOM uint32_t TRIG_SEL : 3;
225  } bit;
226  } CHx_ESM;
227  __IM uint32_t RESERVED[2];
228 
229  union
230  {
231  __IOM uint32_t reg;
234  struct
235  {
236  __IOM uint32_t SQ1 : 8;
237  __IOM uint32_t SQ2 : 8;
238  __IOM uint32_t SQ3 : 8;
239  __IOM uint32_t SQ4 : 8;
240  } bit;
241  } SQ1_4;
242 
243  union
244  {
245  __IOM uint32_t reg;
248  struct
249  {
250  __IOM uint32_t SQ5 : 8;
251  __IOM uint32_t SQ6 : 8;
252  __IOM uint32_t SQ7 : 8;
253  __IOM uint32_t SQ8 : 8;
254  } bit;
255  } SQ5_8;
256  __IM uint32_t RESERVED1;
257 
258  union
259  {
260  __IOM uint32_t reg;
262  struct
263  {
264  __IOM uint32_t ch0 : 1;
265  __IOM uint32_t ch1 : 1;
266  __IOM uint32_t ch2 : 1;
267  __IOM uint32_t ch3 : 1;
268  __IOM uint32_t ch4 : 1;
269  __IOM uint32_t ch5 : 1;
270  __IOM uint32_t ch6 : 1;
271  __IOM uint32_t ch7 : 1;
272  } bit;
273  } DWSEL;
274 
275  union
276  {
277  __IOM uint32_t reg;
279  struct
280  {
281  __IOM uint32_t ch0 : 8;
282  __IOM uint32_t ch1 : 8;
283  __IOM uint32_t ch2 : 8;
284  __IOM uint32_t ch3 : 8;
285  } bit;
286  } STC_0_3;
287 
288  union
289  {
290  __IOM uint32_t reg;
292  struct
293  {
294  __IOM uint32_t ch4 : 8;
295  __IOM uint32_t ch5 : 8;
296  __IOM uint32_t ch6 : 8;
297  __IOM uint32_t ch7 : 8;
298  } bit;
299  } STC_4_7;
300  __IM uint32_t RESERVED2[4];
301 
302  union
303  {
304  __IOM uint32_t reg;
306  struct
307  {
308  __IM uint32_t OUT_CH_EIM : 12;
309  __IM uint32_t : 4;
310  __IOM uint32_t WFR8 : 1;
311  __IM uint32_t VF8 : 1;
312  __IM uint32_t OF8 : 1;
313  } bit;
314  } RES_OUT_EIM;
315  __IM uint32_t RESERVED3[3];
316 
317  union
318  {
319  __IOM uint32_t reg;
321  struct
322  {
323  __IM uint32_t : 8;
324  __IOM uint32_t SQ_RUN : 1;
325  __IM uint32_t EIM_ACTIVE : 1;
326  __IM uint32_t ESM_ACTIVE : 1;
327  __IM uint32_t SQx : 3;
328  __IM uint32_t : 2;
329  __IM uint32_t CHx : 3;
330  } bit;
331  } SQ_FB;
332 
333  union
334  {
335  __IOM uint32_t reg;
337  struct
338  {
339  __IM uint32_t OUT_CH7 : 12;
340  __IM uint32_t : 4;
341  __IOM uint32_t WFR7 : 1;
342  __IM uint32_t VF7 : 1;
343  __IM uint32_t OF7 : 1;
344  } bit;
345  } RES_OUT7;
346 
347  union
348  {
349  __IOM uint32_t reg;
351  struct
352  {
353  __IM uint32_t OUT_CH6 : 12;
354  __IM uint32_t : 4;
355  __IOM uint32_t WFR6 : 1;
356  __IM uint32_t VF6 : 1;
357  __IM uint32_t OF6 : 1;
358  } bit;
359  } RES_OUT6;
360 
361  union
362  {
363  __IOM uint32_t reg;
365  struct
366  {
367  __IM uint32_t OUT_CH5 : 12;
368  __IM uint32_t : 4;
369  __IOM uint32_t WFR5 : 1;
370  __IM uint32_t VF5 : 1;
371  __IM uint32_t OF5 : 1;
372  } bit;
373  } RES_OUT5;
374 
375  union
376  {
377  __IOM uint32_t reg;
379  struct
380  {
381  __IM uint32_t OUT_CH4 : 12;
382  __IM uint32_t : 4;
383  __IOM uint32_t WFR4 : 1;
384  __IM uint32_t VF4 : 1;
385  __IM uint32_t OF4 : 1;
386  } bit;
387  } RES_OUT4;
388 
389  union
390  {
391  __IOM uint32_t reg;
393  struct
394  {
395  __IM uint32_t OUT_CH3 : 12;
396  __IM uint32_t : 4;
397  __IOM uint32_t WFR3 : 1;
398  __IM uint32_t VF3 : 1;
399  __IM uint32_t OF3 : 1;
400  } bit;
401  } RES_OUT3;
402 
403  union
404  {
405  __IOM uint32_t reg;
407  struct
408  {
409  __IM uint32_t OUT_CH2 : 12;
410  __IM uint32_t : 4;
411  __IOM uint32_t WFR2 : 1;
412  __IM uint32_t VF2 : 1;
413  __IM uint32_t OF2 : 1;
414  } bit;
415  } RES_OUT2;
416 
417  union
418  {
419  __IOM uint32_t reg;
421  struct
422  {
423  __IM uint32_t OUT_CH1 : 12;
424  __IM uint32_t : 4;
425  __IOM uint32_t WFR1 : 1;
426  __IM uint32_t VF1 : 1;
427  __IM uint32_t OF1 : 1;
428  } bit;
429  } RES_OUT1;
430 
431  union
432  {
433  __IOM uint32_t reg;
435  struct
436  {
437  __IM uint32_t OUT_CH0 : 12;
438  __IM uint32_t : 4;
439  __IOM uint32_t WFR0 : 1;
440  __IM uint32_t VF0 : 1;
441  __IM uint32_t OF0 : 1;
442  } bit;
443  } RES_OUT0;
444 
445  union
446  {
447  __IOM uint32_t reg;
449  struct
450  {
451  __IM uint32_t BUSY : 1;
452  __IM uint32_t SAMPLE : 1;
453  __IM uint32_t : 1;
454  __IM uint32_t CHNR : 3;
455  __IM uint32_t : 2;
456  __IM uint32_t ANON_ST : 2;
457  } bit;
458  } GLOBSTR;
459 
460  union
461  {
462  __IOM uint32_t reg;
464  struct
465  {
466  __IM uint32_t CH0_STS : 1;
467  __IM uint32_t CH1_STS : 1;
468  __IM uint32_t CH2_STS : 1;
469  __IM uint32_t CH3_STS : 1;
470  __IM uint32_t CH4_STS : 1;
471  __IM uint32_t CH5_STS : 1;
472  __IM uint32_t CH6_STS : 1;
473  __IM uint32_t CH7_STS : 1;
474  __IM uint32_t EIM_STS : 1;
475  __IM uint32_t ESM_STS : 1;
476  } bit;
477  } IS;
478 
479  union
480  {
481  __IOM uint32_t reg;
483  struct
484  {
485  __IOM uint32_t CH0_IE : 1;
486  __IOM uint32_t CH1_IE : 1;
487  __IOM uint32_t CH2_IE : 1;
488  __IOM uint32_t CH3_IE : 1;
489  __IOM uint32_t CH4_IE : 1;
490  __IOM uint32_t CH5_IE : 1;
491  __IOM uint32_t CH6_IE : 1;
492  __IOM uint32_t CH7_IE : 1;
493  __IOM uint32_t EIM_IE : 1;
494  __IOM uint32_t ESM_IE : 1;
495  } bit;
496  } IE;
497 
498  union
499  {
500  __IOM uint32_t reg;
502  struct
503  {
504  __OM uint32_t CH0_ICLR : 1;
505  __OM uint32_t CH1_ICLR : 1;
506  __OM uint32_t CH2_ICLR : 1;
507  __OM uint32_t CH3_ICLR : 1;
508  __OM uint32_t CH4_ICLR : 1;
509  __OM uint32_t CH5_ICLR : 1;
510  __OM uint32_t CH6_ICLR : 1;
511  __OM uint32_t CH7_ICLR : 1;
512  __OM uint32_t EIM_ICLR : 1;
513  __OM uint32_t ESM_ICLR : 1;
514  } bit;
515  } ICLR;
516 } ADC1_Type;
520 /* =========================================================================================================================== */
521 /* ================ ADC2 ================ */
522 /* =========================================================================================================================== */
523 
524 
529 typedef struct
530 {
531 
532  union
533  {
534  __IOM uint32_t reg;
536  struct
537  {
539  __IOM uint32_t VS_RANGE : 1;
540  } bit;
541  } CTRL_STS;
542 
543  union
544  {
545  __IOM uint32_t reg;
547  struct
548  {
549  __IM uint32_t SQ_FB : 4;
550  __IM uint32_t : 4;
551  __IM uint32_t SQ_STOP : 1;
552  __IM uint32_t EIM_ACTIVE : 1;
553  __IM uint32_t ESM_ACTIVE : 1;
554  __IM uint32_t SQx : 4;
555  __IM uint32_t : 1;
556  __IM uint32_t CHx : 5;
557  } bit;
558  } SQ_FB;
559 
560  union
561  {
562  __IOM uint32_t reg;
565  struct
566  {
567  __IOM uint32_t CHx : 5;
568  __IM uint32_t : 3;
569  __IOM uint32_t REP : 3;
570  __IOM uint32_t EN : 1;
572  __IOM uint32_t SEL : 1;
574  } bit;
575  } CHx_EIM;
576 
577  union
578  {
579  __IOM uint32_t reg;
582  struct
583  {
584  __IOM uint32_t ESM_0 : 6;
586  __IOM uint32_t ESM_1 : 4;
588  __IOM uint32_t SEL : 1;
589  __IM uint32_t : 5;
590  __IOM uint32_t EN : 1;
592  __IM uint32_t STS : 1;
593  } bit;
594  } CHx_ESM;
595  __IM uint32_t RESERVED;
596 
597  union
598  {
599  __IOM uint32_t reg;
601  struct
602  {
603  __IOM uint32_t CALIB_EN : 6;
604  } bit;
605  } CTRL1;
606 
607  union
608  {
609  __IOM uint32_t reg;
611  struct
612  {
613  __IOM uint32_t MCM_PD_N : 1;
614  __IOM uint32_t TS_SD_SEL_CONF : 1;
615  __IOM uint32_t TSENSE_SD_SEL : 1;
616  __IM uint32_t : 4;
617  __IM uint32_t MCM_RDY : 1;
618  __IOM uint32_t SAMPLE_TIME_int : 4;
619  __IM uint32_t : 4;
620  __IOM uint32_t SEL_TS_COUNT : 4;
621  } bit;
622  } CTRL2;
623 
624  union
625  {
626  __IOM uint32_t reg;
628  struct
629  {
630  __IOM uint32_t FILT_OUT_SEL_5_0 : 6;
631  __IM uint32_t : 2;
632  __IOM uint32_t FILT_OUT_SEL_9_6 : 4;
633  } bit;
634  } CTRL4;
635 
636  union
637  {
638  __IOM uint32_t reg;
640  struct
641  {
642  __IOM uint32_t SQ1 : 6;
643  __IM uint32_t : 2;
644  __IOM uint32_t SQ2 : 6;
645  __IM uint32_t : 2;
646  __IOM uint32_t SQ3 : 6;
647  __IM uint32_t : 2;
648  __IOM uint32_t SQ4 : 6;
649  } bit;
650  } SQ1_4;
651 
652  union
653  {
654  __IOM uint32_t reg;
657  struct
658  {
659  __IOM uint32_t SQ5 : 6;
660  __IM uint32_t : 2;
661  __IOM uint32_t SQ6 : 6;
662  __IM uint32_t : 2;
663  __IOM uint32_t SQ7 : 6;
664  __IM uint32_t : 2;
665  __IOM uint32_t SQ8 : 6;
666  } bit;
667  } SQ5_8;
668 
669  union
670  {
671  __IOM uint32_t reg;
674  struct
675  {
676  __IOM uint32_t SQ9 : 6;
677  __IM uint32_t : 2;
678  __IOM uint32_t SQ10 : 6;
679  } bit;
680  } SQ9_10;
681 
682  union
683  {
684  __IOM uint32_t reg;
687  struct
688  {
689  __IM uint32_t SQ1_int : 4;
690  __IM uint32_t SQ2_int : 4;
691  __IM uint32_t SQ3_int : 4;
692  __IM uint32_t SQ4_int : 4;
693  __IM uint32_t SQ5_int : 4;
694  __IM uint32_t SQ6_int : 4;
695  __IM uint32_t SQ7_int : 4;
696  __IM uint32_t SQ8_int : 4;
697  } bit;
698  } SQ1_8_int;
699 
700  union
701  {
702  __IOM uint32_t reg;
705  struct
706  {
707  __IM uint32_t SQ9_int : 4;
708  __IM uint32_t SQ10_int : 4;
709  } bit;
710  } SQ9_10_int;
711 
712  union
713  {
714  __IOM uint32_t reg;
716  struct
717  {
718  __IOM uint32_t OFFS_CH0 : 8;
719  __IOM uint32_t GAIN_CH0 : 8;
720  __IOM uint32_t OFFS_CH1 : 8;
721  __IOM uint32_t GAIN_CH1 : 8;
722  } bit;
723  } CAL_CH0_1;
724 
725  union
726  {
727  __IOM uint32_t reg;
729  struct
730  {
731  __IOM uint32_t OFFS_CH2 : 8;
732  __IOM uint32_t GAIN_CH2 : 8;
733  __IOM uint32_t OFFS_CH3 : 8;
734  __IOM uint32_t GAIN_CH3 : 8;
735  } bit;
736  } CAL_CH2_3;
737 
738  union
739  {
740  __IOM uint32_t reg;
742  struct
743  {
744  __IOM uint32_t OFFS_CH4 : 8;
745  __IOM uint32_t GAIN_CH4 : 8;
746  __IOM uint32_t OFFS_CH5 : 8;
747  __IOM uint32_t GAIN_CH5 : 8;
748  } bit;
749  } CAL_CH4_5;
750 
751  union
752  {
753  __IOM uint32_t reg;
755  struct
756  {
757  __IM uint32_t OFFS_CH6 : 8;
758  __IM uint32_t GAIN_CH6 : 8;
759  __IM uint32_t OFFS_CH7 : 8;
760  __IM uint32_t GAIN_CH7 : 8;
761  } bit;
762  } CAL_CH6_7;
763 
764  union
765  {
766  __IOM uint32_t reg;
768  struct
769  {
770  __IM uint32_t OFFS_CH8 : 8;
771  __IM uint32_t GAIN_CH8 : 8;
772  __IM uint32_t OFFS_CH9 : 8;
773  __IM uint32_t GAIN_CH9 : 8;
774  } bit;
775  } CAL_CH8_9;
776 
777  union
778  {
779  __IOM uint32_t reg;
781  struct
782  {
783  __IOM uint32_t CH0 : 2;
784  __IOM uint32_t CH1 : 2;
785  __IOM uint32_t CH2 : 2;
786  __IOM uint32_t CH3 : 2;
787  __IOM uint32_t CH4 : 2;
788  __IOM uint32_t CH5 : 2;
789  } bit;
790  } FILTCOEFF0_5;
791 
792  union
793  {
794  __IOM uint32_t reg;
796  struct
797  {
798  __IM uint32_t CH6 : 2;
799  __IM uint32_t CH7 : 2;
800  __IM uint32_t CH8 : 2;
801  __IM uint32_t CH9 : 2;
802  } bit;
803  } FILTCOEFF6_9;
804 
805  union
806  {
807  __IOM uint32_t reg;
809  struct
810  {
811  __IM uint32_t OUT_CH0 : 10;
812  } bit;
813  } FILT_OUT0;
814 
815  union
816  {
817  __IOM uint32_t reg;
819  struct
820  {
821  __IM uint32_t OUT_CH1 : 10;
822  } bit;
823  } FILT_OUT1;
824 
825  union
826  {
827  __IOM uint32_t reg;
829  struct
830  {
831  __IM uint32_t OUT_CH2 : 10;
832  } bit;
833  } FILT_OUT2;
834 
835  union
836  {
837  __IOM uint32_t reg;
839  struct
840  {
841  __IM uint32_t OUT_CH3 : 10;
842  } bit;
843  } FILT_OUT3;
844 
845  union
846  {
847  __IOM uint32_t reg;
849  struct
850  {
851  __IM uint32_t OUT_CH4 : 10;
852  } bit;
853  } FILT_OUT4;
854 
855  union
856  {
857  __IOM uint32_t reg;
859  struct
860  {
861  __IM uint32_t OUT_CH5 : 10;
862  } bit;
863  } FILT_OUT5;
864 
865  union
866  {
867  __IOM uint32_t reg;
869  struct
870  {
871  __IM uint32_t OUT_CH6 : 10;
872  } bit;
873  } FILT_OUT6;
874 
875  union
876  {
877  __IOM uint32_t reg;
879  struct
880  {
881  __IM uint32_t OUT_CH7 : 10;
882  } bit;
883  } FILT_OUT7;
884 
885  union
886  {
887  __IOM uint32_t reg;
889  struct
890  {
891  __IM uint32_t OUT_CH8 : 10;
892  } bit;
893  } FILT_OUT8;
894 
895  union
896  {
897  __IOM uint32_t reg;
899  struct
900  {
901  __IM uint32_t OUT_CH9 : 10;
902  } bit;
903  } FILT_OUT9;
904 
905  union
906  {
907  __IOM uint32_t reg;
909  struct
910  {
911  __IOM uint32_t Ch0_EN : 1;
912  __IOM uint32_t Ch1_EN : 1;
913  __IOM uint32_t Ch2_EN : 1;
914  __IOM uint32_t Ch3_EN : 1;
915  __IOM uint32_t Ch4_EN : 1;
916  __IOM uint32_t Ch5_EN : 1;
917  } bit;
918  } FILT_UP_CTRL;
919 
920  union
921  {
922  __IOM uint32_t reg;
924  struct
925  {
926  __IOM uint32_t Ch0_EN : 1;
927  __IOM uint32_t Ch1_EN : 1;
928  __IOM uint32_t Ch2_EN : 1;
929  __IOM uint32_t Ch3_EN : 1;
930  __IOM uint32_t Ch4_EN : 1;
931  __IOM uint32_t Ch5_EN : 1;
932  } bit;
933  } FILT_LO_CTRL;
934 
935  union
936  {
937  __IOM uint32_t reg;
939  struct
940  {
941  __IOM uint32_t CH0 : 8;
942  __IOM uint32_t CH1 : 8;
943  __IOM uint32_t CH2 : 8;
944  __IOM uint32_t CH3 : 8;
945  } bit;
946  } TH0_3_LOWER;
947 
948  union
949  {
950  __IOM uint32_t reg;
953  struct
954  {
955  __IOM uint32_t CH4 : 8;
956  __IOM uint32_t CH5 : 8;
957  } bit;
958  } TH4_5_LOWER;
959 
960  union
961  {
962  __IOM uint32_t reg;
964  struct
965  {
966  __IOM uint32_t CH6 : 8;
967  __IM uint32_t CH7 : 8;
968  __IOM uint32_t CH8 : 8;
969  __IOM uint32_t CH9 : 8;
970  } bit;
971  } TH6_9_LOWER;
972 
973  union
974  {
975  __IOM uint32_t reg;
977  struct
978  {
979  __IOM uint32_t CH0 : 8;
980  __IOM uint32_t CH1 : 8;
981  __IOM uint32_t CH2 : 8;
982  __IOM uint32_t CH3 : 8;
983  } bit;
984  } TH0_3_UPPER;
985 
986  union
987  {
988  __IOM uint32_t reg;
990  struct
991  {
992  __IOM uint32_t CH4 : 8;
993  __IOM uint32_t CH5 : 8;
994  } bit;
995  } TH4_5_UPPER;
996 
997  union
998  {
999  __IOM uint32_t reg;
1001  struct
1002  {
1003  __IM uint32_t CH6 : 8;
1004  __IM uint32_t CH7 : 8;
1005  __IM uint32_t CH8 : 8;
1006  __IM uint32_t CH9 : 8;
1007  } bit;
1008  } TH6_9_UPPER;
1009 
1010  union
1011  {
1012  __IOM uint32_t reg;
1014  struct
1015  {
1016  __IOM uint32_t CNT_LO_CH0 : 3;
1017  __IOM uint32_t HYST_LO_CH0 : 2;
1018  __IM uint32_t : 3;
1019  __IOM uint32_t CNT_LO_CH1 : 3;
1020  __IOM uint32_t HYST_LO_CH1 : 2;
1021  __IM uint32_t : 3;
1022  __IOM uint32_t CNT_LO_CH2 : 3;
1023  __IOM uint32_t HYST_LO_CH2 : 2;
1024  __IM uint32_t : 3;
1025  __IOM uint32_t CNT_LO_CH3 : 3;
1026  __IOM uint32_t HYST_LO_CH3 : 2;
1027  } bit;
1028  } CNT0_3_LOWER;
1029 
1030  union
1031  {
1032  __IOM uint32_t reg;
1034  struct
1035  {
1036  __IOM uint32_t CNT_LO_CH4 : 3;
1037  __IOM uint32_t HYST_LO_CH4 : 2;
1038  __IM uint32_t : 3;
1039  __IOM uint32_t CNT_LO_CH5 : 3;
1040  __IOM uint32_t HYST_LO_CH5 : 2;
1041  } bit;
1042  } CNT4_5_LOWER;
1043 
1044  union
1045  {
1046  __IOM uint32_t reg;
1048  struct
1049  {
1050  __IM uint32_t CNT_LO_CH6 : 3;
1051  __IM uint32_t HYST_LO_CH6 : 2;
1052  __IM uint32_t : 3;
1053  __IM uint32_t CNT_LO_CH7 : 3;
1054  __IM uint32_t HYST_LO_CH7 : 2;
1055  __IM uint32_t : 3;
1056  __IM uint32_t CNT_LO_CH8 : 3;
1057  __IM uint32_t HYST_LO_CH8 : 2;
1058  __IM uint32_t : 3;
1059  __IM uint32_t CNT_LO_CH9 : 3;
1060  __IM uint32_t HYST_LO_CH9 : 2;
1061  } bit;
1062  } CNT6_9_LOWER;
1063 
1064  union
1065  {
1066  __IOM uint32_t reg;
1068  struct
1069  {
1070  __IOM uint32_t CNT_UP_CH0 : 3;
1071  __IOM uint32_t HYST_UP_CH0 : 2;
1072  __IM uint32_t : 3;
1073  __IOM uint32_t CNT_UP_CH1 : 3;
1074  __IOM uint32_t HYST_UP_CH1 : 2;
1075  __IM uint32_t : 3;
1076  __IOM uint32_t CNT_UP_CH2 : 3;
1077  __IOM uint32_t HYST_UP_CH2 : 2;
1078  __IM uint32_t : 3;
1079  __IOM uint32_t CNT_UP_CH3 : 3;
1080  __IOM uint32_t HYST_UP_CH3 : 2;
1081  } bit;
1082  } CNT0_3_UPPER;
1083 
1084  union
1085  {
1086  __IOM uint32_t reg;
1088  struct
1089  {
1090  __IOM uint32_t CNT_UP_CH4 : 3;
1091  __IOM uint32_t HYST_UP_CH4 : 2;
1092  __IM uint32_t : 3;
1093  __IOM uint32_t CNT_UP_CH5 : 3;
1094  __IOM uint32_t HYST_UP_CH5 : 2;
1095  } bit;
1096  } CNT4_5_UPPER;
1097 
1098  union
1099  {
1100  __IOM uint32_t reg;
1102  struct
1103  {
1104  __IM uint32_t CNT_UP_CH6 : 3;
1105  __IM uint32_t HYST_UP_CH6 : 2;
1106  __IM uint32_t : 3;
1107  __IM uint32_t CNT_UP_CH7 : 3;
1108  __IM uint32_t HYST_UP_CH7 : 2;
1109  __IM uint32_t : 3;
1110  __IM uint32_t CNT_UP_CH8 : 3;
1111  __IM uint32_t HYST_UP_CH8 : 2;
1112  __IM uint32_t : 3;
1113  __IM uint32_t CNT_UP_CH9 : 3;
1114  __IM uint32_t HYST_UP_CH9 : 2;
1115  } bit;
1116  } CNT6_9_UPPER;
1117 
1118  union
1119  {
1120  __IOM uint32_t reg;
1122  struct
1123  {
1124  __IOM uint32_t Ch0 : 2;
1125  __IOM uint32_t Ch1 : 2;
1126  __IOM uint32_t Ch2 : 2;
1127  __IOM uint32_t Ch3 : 2;
1128  __IOM uint32_t Ch4 : 2;
1129  __IOM uint32_t Ch5 : 2;
1130  } bit;
1131  } MMODE0_5;
1132  __IM uint32_t RESERVED1[2];
1133 
1134  union
1135  {
1136  __IOM uint32_t reg;
1138  struct
1139  {
1140  __IM uint32_t : 1;
1141  __IM uint32_t READY : 1;
1142  } bit;
1143  } HV_STS;
1144 } ADC2_Type;
1148 /* =========================================================================================================================== */
1149 /* ================ ADC34 ================ */
1150 /* =========================================================================================================================== */
1151 
1152 
1157 typedef struct
1158 {
1159 
1160  union
1161  {
1162  __IOM uint32_t reg;
1164  struct
1165  {
1166  __IOM uint32_t ADC3_EN : 1;
1167  __IOM uint32_t ADC3_OFS_MEAS_EN : 1;
1168  __IOM uint32_t ADC3_SOC : 1;
1171  __IM uint32_t ADC3_EoC_STS : 1;
1172  __IM uint32_t ADC34_DREQ_SEL : 2;
1173  __IM uint32_t : 4;
1174  __IOM uint32_t ADC34_REF_SEL : 1;
1175  __IOM uint32_t ADC3_OSR : 4;
1176  __IOM uint32_t ADC4_EN : 1;
1177  __IOM uint32_t ADC4_OFS_MEAS_EN : 1;
1178  __IOM uint32_t ADC4_SOC : 1;
1180  __IM uint32_t : 1;
1181  __IM uint32_t ADC4_EoC_STS : 1;
1182  __IOM uint32_t ADC34_EoC_CNT : 2;
1183  __IOM uint32_t ADC34_DITHEN : 1;
1184  __IOM uint32_t ADC34_DITHVAL : 4;
1185  __IOM uint32_t ADC4_OSR : 4;
1186  } bit;
1187  } CTRL_STS;
1188 
1189  union
1190  {
1191  __IOM uint32_t reg;
1193  struct
1194  {
1195  __IM uint32_t ADC3_RESU : 16;
1196  __IM uint32_t ADC4_RESU : 16;
1197  } bit;
1198  } RESU;
1199 } ADC34_Type;
1203 /* =========================================================================================================================== */
1204 /* ================ BDRV ================ */
1205 /* =========================================================================================================================== */
1206 
1207 
1212 typedef struct
1213 {
1214 
1215  union
1216  {
1217  __IOM uint32_t reg;
1219  struct
1220  {
1221  __IOM uint32_t LS1_EN : 1;
1222  __IOM uint32_t LS1_PWM : 1;
1223  __IOM uint32_t LS1_ON : 1;
1224  __IOM uint32_t LS1_DCS_EN : 1;
1225  __IM uint32_t LS1_DS_STS : 1;
1226  __IM uint32_t LS1_SUPERR_STS : 1;
1227  __IM uint32_t LS1_OC_STS : 1;
1228  __IOM uint32_t LS1_OC_DIS : 1;
1229  __IOM uint32_t LS2_EN : 1;
1230  __IOM uint32_t LS2_PWM : 1;
1231  __IOM uint32_t LS2_ON : 1;
1232  __IOM uint32_t LS2_DCS_EN : 1;
1233  __IM uint32_t LS2_DS_STS : 1;
1235  __IM uint32_t LS2_SUPERR_STS : 1;
1236  __IM uint32_t LS2_OC_STS : 1;
1237  __IOM uint32_t LS2_OC_DIS : 1;
1238  __IOM uint32_t HS1_EN : 1;
1239  __IOM uint32_t HS1_PWM : 1;
1240  __IOM uint32_t HS1_ON : 1;
1241  __IOM uint32_t HS1_DCS_EN : 1;
1242  __IM uint32_t HS1_DS_STS : 1;
1244  __IM uint32_t HS1_SUPERR_STS : 1;
1245  __IM uint32_t HS1_OC_STS : 1;
1246  __IOM uint32_t HS1_OC_DIS : 1;
1247  __IOM uint32_t HS2_EN : 1;
1248  __IOM uint32_t HS2_PWM : 1;
1249  __IOM uint32_t HS2_ON : 1;
1250  __IOM uint32_t HS2_DCS_EN : 1;
1251  __IM uint32_t HS2_DS_STS : 1;
1253  __IM uint32_t HS2_SUPERR_STS : 1;
1254  __IM uint32_t HS2_OC_STS : 1;
1255  __IOM uint32_t HS2_OC_DIS : 1;
1256  } bit;
1257  } CTRL1;
1258 
1259  union
1260  {
1261  __IOM uint32_t reg;
1263  struct
1264  {
1265  __IOM uint32_t LS3_EN : 1;
1266  __IOM uint32_t LS3_PWM : 1;
1267  __IOM uint32_t LS3_ON : 1;
1268  __IOM uint32_t LS3_DCS_EN : 1;
1269  __IM uint32_t LS3_DS_STS : 1;
1270  __IM uint32_t LS3_SUPERR_STS : 1;
1271  __IM uint32_t LS3_OC_STS : 1;
1272  __IOM uint32_t LS3_OC_DIS : 1;
1273  __IOM uint32_t HS3_EN : 1;
1274  __IOM uint32_t HS3_PWM : 1;
1275  __IOM uint32_t HS3_ON : 1;
1276  __IOM uint32_t HS3_DCS_EN : 1;
1277  __IM uint32_t HS3_DS_STS : 1;
1278  __IM uint32_t HS3_SUPERR_STS : 1;
1279  __IM uint32_t HS3_OC_STS : 1;
1280  __IOM uint32_t HS3_OC_DIS : 1;
1281  __IM uint32_t DLY_DIAG_TIM : 10;
1282  __OM uint32_t DLY_DIAG_SCLR : 1;
1283  __IM uint32_t DLY_DIAG_STS : 1;
1284  __IOM uint32_t DLY_DIAG_CHSEL : 3;
1285  __IOM uint32_t DLY_DIAG_DIRSEL : 1;
1286  } bit;
1287  } CTRL2;
1288 
1289  union
1290  {
1291  __IOM uint32_t reg;
1293  struct
1294  {
1295  __IOM uint32_t ICHARGE_TRIM : 5;
1297  __IOM uint32_t ICHARGEDIV2_N : 1;
1298  __IOM uint32_t ON_SEQ_EN : 1;
1299  __IOM uint32_t IDISCHARGE_TRIM : 5;
1300  __IM uint32_t : 1;
1301  __IOM uint32_t IDISCHARGEDIV2_N : 1;
1302  __IOM uint32_t OFF_SEQ_EN : 1;
1303  __IOM uint32_t DSMONVTH : 3;
1305  __IM uint32_t : 5;
1306  __IOM uint32_t DRV_CCP_TIMSEL : 2;
1307  __IOM uint32_t DRV_CCP_DIS : 1;
1308  } bit;
1309  } CTRL3;
1310  __IM uint32_t RESERVED;
1311 
1312  union
1313  {
1314  __IOM uint32_t reg;
1316  struct
1317  {
1318  __IOM uint32_t DRV_OFF_t_4 : 3;
1319  __IOM uint32_t DRV_OFF_I_4 : 5;
1320  __IOM uint32_t DRV_OFF_t_3 : 3;
1321  __IOM uint32_t DRV_OFF_I_3 : 5;
1322  __IOM uint32_t DRV_OFF_t_2 : 3;
1323  __IOM uint32_t DRV_OFF_I_2 : 5;
1324  __IOM uint32_t DRV_OFF_t_1 : 3;
1325  __IOM uint32_t DRV_OFF_I_1 : 5;
1326  } bit;
1327  } OFF_SEQ_CTRL;
1328 
1329  union
1330  {
1331  __IOM uint32_t reg;
1333  struct
1334  {
1335  __IOM uint32_t DRV_ON_t_4 : 3;
1336  __IOM uint32_t DRV_ON_I_4 : 5;
1337  __IOM uint32_t DRV_ON_t_3 : 3;
1338  __IOM uint32_t DRV_ON_I_3 : 5;
1339  __IOM uint32_t DRV_ON_t_2 : 3;
1340  __IOM uint32_t DRV_ON_I_2 : 5;
1341  __IOM uint32_t DRV_ON_t_1 : 3;
1342  __IOM uint32_t DRV_ON_I_1 : 5;
1343  } bit;
1344  } ON_SEQ_CTRL;
1345 
1346  union
1347  {
1348  __IOM uint32_t reg;
1350  struct
1351  {
1352  __IOM uint32_t LS_HS_BT_TFILT_SEL : 2;
1354  __IM uint32_t : 3;
1355  __IOM uint32_t DRV_CCPTIMMUL : 2;
1357  __IM uint32_t : 1;
1358  __IOM uint32_t LSDRV_DS_TFILT_SEL : 2;
1359  __IOM uint32_t LS1DRV_FDISCHG_DIS : 1;
1360  __IOM uint32_t LS2DRV_FDISCHG_DIS : 1;
1361  __IOM uint32_t LS3DRV_FDISCHG_DIS : 1;
1362  __IOM uint32_t LS1DRV_OCSDN_DIS : 1;
1363  __IOM uint32_t LS2DRV_OCSDN_DIS : 1;
1364  __IOM uint32_t LS3DRV_OCSDN_DIS : 1;
1365  __IOM uint32_t HSDRV_DS_TFILT_SEL : 2;
1367  __IOM uint32_t HS1DRV_FDISCHG_DIS : 1;
1368  __IOM uint32_t HS2DRV_FDISCHG_DIS : 1;
1369  __IOM uint32_t HS3DRV_FDISCHG_DIS : 1;
1370  __IOM uint32_t HS1DRV_OCSDN_DIS : 1;
1371  __IOM uint32_t HS2DRV_OCSDN_DIS : 1;
1372  __IOM uint32_t HS3DRV_OCSDN_DIS : 1;
1373  __IOM uint32_t CPLOW_TFILT_SEL : 2;
1374  } bit;
1375  } TRIM_DRVx;
1376  __IM uint32_t RESERVED1;
1377 
1378  union
1379  {
1380  __IOM uint32_t reg;
1382  struct
1383  {
1384  __IOM uint32_t CP_EN : 1;
1385  __IM uint32_t : 1;
1386  __IOM uint32_t CP_RDY_EN : 1;
1387  __IM uint32_t : 2;
1388  __IM uint32_t VCP_LOTH2_STS : 1;
1389  __IM uint32_t : 2;
1390  __IOM uint32_t VCP_LOWTH2 : 3;
1392  __IM uint32_t : 5;
1393  __IOM uint32_t DRVx_VCPLO_DIS : 1;
1394  __IM uint32_t VCP_LOTH1_STS : 1;
1395  __IOM uint32_t DRVx_VCPUP_DIS : 1;
1396  __IM uint32_t VCP_UPTH_STS : 1;
1397  __IOM uint32_t DRVx_VSDLO_DIS : 1;
1398  __IM uint32_t VSD_LOTH_STS : 1;
1399  __IOM uint32_t DRVx_VSDUP_DIS : 1;
1400  __IM uint32_t VSD_UPTH_STS : 1;
1401  __IOM uint32_t CPLOPWRM_EN : 1;
1402  __IOM uint32_t VCP9V_SET : 1;
1403  __IOM uint32_t VTHVCP9V_TRIM : 2;
1404  } bit;
1405  } CP_CTRL_STS;
1406 
1407  union
1408  {
1409  __IOM uint32_t reg;
1411  struct
1412  {
1413  __IOM uint32_t DITH_LOWER : 5;
1414  __IM uint32_t : 3;
1415  __IOM uint32_t DITH_UPPER : 5;
1416  __IOM uint32_t F_CP : 2;
1417  __IOM uint32_t CPCLK_EN : 1;
1418  } bit;
1419  } CP_CLK_CTRL;
1420 } BDRV_Type;
1424 /* =========================================================================================================================== */
1425 /* ================ CCU6 ================ */
1426 /* =========================================================================================================================== */
1427 
1428 
1433 typedef struct
1434 {
1435 
1436  union
1437  {
1438  __IOM uint16_t reg;
1440  struct
1441  {
1442  __IM uint16_t CCV : 16;
1443  } bit;
1444  } CC63R;
1445  __IM uint16_t RESERVED;
1446 
1447  union
1448  {
1449  __IOM uint16_t reg;
1451  struct
1452  {
1453  __OM uint16_t T12RR : 1;
1454  __OM uint16_t T12RS : 1;
1455  __OM uint16_t T12RES : 1;
1456  __OM uint16_t DTRES : 1;
1458  __OM uint16_t T12CNT : 1;
1459  __OM uint16_t T12STR : 1;
1460  __OM uint16_t T12STD : 1;
1461  __OM uint16_t T13RR : 1;
1462  __OM uint16_t T13RS : 1;
1463  __OM uint16_t T13RES : 1;
1464  __IM uint16_t : 2;
1465  __OM uint16_t T13CNT : 1;
1466  __OM uint16_t T13STR : 1;
1467  __OM uint16_t T13STD : 1;
1468  } bit;
1469  } TCTR4;
1470  __IM uint16_t RESERVED1;
1471 
1472  union
1473  {
1474  __IOM uint16_t reg;
1476  struct
1477  {
1478  __IOM uint16_t MCMPS : 6;
1479  __IM uint16_t : 1;
1480  __IOM uint16_t STRMCM : 1;
1481  __IOM uint16_t EXPHS : 3;
1482  __IOM uint16_t CURHS : 3;
1483  __IM uint16_t : 1;
1484  __IOM uint16_t STRHP : 1;
1485  } bit;
1486  } MCMOUTS;
1487  __IM uint16_t RESERVED2;
1488 
1489  union
1490  {
1491  __IOM uint16_t reg;
1493  struct
1494  {
1495  __OM uint16_t RCC60R : 1;
1496  __OM uint16_t RCC60F : 1;
1497  __OM uint16_t RCC61R : 1;
1498  __OM uint16_t RCC61F : 1;
1499  __OM uint16_t RCC62R : 1;
1500  __OM uint16_t RCC62F : 1;
1501  __OM uint16_t RT12OM : 1;
1502  __OM uint16_t RT12PM : 1;
1503  __OM uint16_t RT13CM : 1;
1504  __OM uint16_t RT13PM : 1;
1505  __OM uint16_t RTRPF : 1;
1506  __IM uint16_t : 1;
1507  __OM uint16_t RCHE : 1;
1508  __OM uint16_t RWHE : 1;
1509  __OM uint16_t RIDLE : 1;
1510  __OM uint16_t RSTR : 1;
1511  } bit;
1512  } ISR;
1513  __IM uint16_t RESERVED3;
1514 
1515  union
1516  {
1517  __IOM uint16_t reg;
1519  struct
1520  {
1521  __OM uint16_t MCC60S : 1;
1523  __OM uint16_t MCC61S : 1;
1525  __OM uint16_t MCC62S : 1;
1527  __IM uint16_t : 3;
1528  __OM uint16_t MCC63S : 1;
1530  __IM uint16_t : 1;
1531  __OM uint16_t MCC60R : 1;
1533  __OM uint16_t MCC61R : 1;
1535  __OM uint16_t MCC62R : 1;
1537  __IM uint16_t : 3;
1538  __OM uint16_t MCC63R : 1;
1540  } bit;
1541  } CMPMODIF;
1542  __IM uint16_t RESERVED4;
1543 
1544  union
1545  {
1546  __IOM uint16_t reg;
1548  struct
1549  {
1550  __IOM uint16_t CCS : 16;
1551  } bit;
1552  } CC60SR;
1553  __IM uint16_t RESERVED5;
1554 
1555  union
1556  {
1557  __IOM uint16_t reg;
1559  struct
1560  {
1561  __IOM uint16_t CCS : 16;
1562  } bit;
1563  } CC61SR;
1564  __IM uint16_t RESERVED6;
1565 
1566  union
1567  {
1568  __IOM uint16_t reg;
1570  struct
1571  {
1572  __IOM uint16_t CCS : 16;
1573  } bit;
1574  } CC62SR;
1575  __IM uint16_t RESERVED7;
1576 
1577  union
1578  {
1579  __IOM uint16_t reg;
1581  struct
1582  {
1583  __IOM uint16_t CCS : 16;
1584  } bit;
1585  } CC63SR;
1586  __IM uint16_t RESERVED8;
1587 
1588  union
1589  {
1590  __IOM uint16_t reg;
1592  struct
1593  {
1594  __IOM uint16_t T12PV : 16;
1595  } bit;
1596  } T12PR;
1597  __IM uint16_t RESERVED9;
1598 
1599  union
1600  {
1601  __IOM uint16_t reg;
1603  struct
1604  {
1605  __IOM uint16_t T13PV : 16;
1606  } bit;
1607  } T13PR;
1608  __IM uint16_t RESERVED10;
1609 
1610  union
1611  {
1612  __IOM uint16_t reg;
1614  struct
1615  {
1616  __IOM uint16_t DTM : 8;
1617  __IOM uint16_t DTE0 : 1;
1618  __IOM uint16_t DTE1 : 1;
1619  __IOM uint16_t DTE2 : 1;
1620  __IM uint16_t : 1;
1621  __IM uint16_t DTR0 : 1;
1622  __IM uint16_t DTR1 : 1;
1623  __IM uint16_t DTR2 : 1;
1624  } bit;
1625  } T12DTC;
1626  __IM uint16_t RESERVED11;
1627 
1628  union
1629  {
1630  __IOM uint16_t reg;
1632  struct
1633  {
1634  __IOM uint16_t T12CLK : 3;
1635  __IOM uint16_t T12PRE : 1;
1636  __IM uint16_t T12R : 1;
1637  __IM uint16_t STE12 : 1;
1638  __IM uint16_t CDIR : 1;
1639  __IOM uint16_t CTM : 1;
1640  __IOM uint16_t T13CLK : 3;
1641  __IOM uint16_t T13PRE : 1;
1642  __IM uint16_t T13R : 1;
1643  __IM uint16_t STE13 : 1;
1644  } bit;
1645  } TCTR0;
1646  __IM uint16_t RESERVED12;
1647 
1648  union
1649  {
1650  __IOM uint16_t reg;
1652  struct
1653  {
1654  __IM uint16_t CCV : 16;
1655  } bit;
1656  } CC60R;
1657  __IM uint16_t RESERVED13;
1658 
1659  union
1660  {
1661  __IOM uint16_t reg;
1663  struct
1664  {
1665  __IM uint16_t CCV : 16;
1666  } bit;
1667  } CC61R;
1668  __IM uint16_t RESERVED14;
1669 
1670  union
1671  {
1672  __IOM uint16_t reg;
1674  struct
1675  {
1676  __IM uint16_t CCV : 16;
1677  } bit;
1678  } CC62R;
1679  __IM uint16_t RESERVED15;
1680 
1681  union
1682  {
1683  __IOM uint16_t reg;
1685  struct
1686  {
1687  __IOM uint16_t MSEL60 : 4;
1688  __IOM uint16_t MSEL61 : 4;
1689  __IOM uint16_t MSEL62 : 4;
1690  __IOM uint16_t HSYNC : 3;
1691  __IOM uint16_t DBYP : 1;
1692  } bit;
1693  } T12MSEL;
1694  __IM uint16_t RESERVED16;
1695 
1696  union
1697  {
1698  __IOM uint16_t reg;
1700  struct
1701  {
1702  __IOM uint16_t ENCC60R : 1;
1704  __IOM uint16_t ENCC60F : 1;
1706  __IOM uint16_t ENCC61R : 1;
1708  __IOM uint16_t ENCC61F : 1;
1710  __IOM uint16_t ENCC62R : 1;
1712  __IOM uint16_t ENCC62F : 1;
1714  __IOM uint16_t ENT12OM : 1;
1715  __IOM uint16_t ENT12PM : 1;
1716  __IOM uint16_t ENT13CM : 1;
1717  __IOM uint16_t ENT13PM : 1;
1718  __IOM uint16_t ENTRPF : 1;
1719  __IM uint16_t : 1;
1720  __IOM uint16_t ENCHE : 1;
1721  __IOM uint16_t ENWHE : 1;
1722  __IOM uint16_t ENIDLE : 1;
1723  __IOM uint16_t ENSTR : 1;
1724  } bit;
1725  } IEN;
1726  __IM uint16_t RESERVED17;
1727 
1728  union
1729  {
1730  __IOM uint16_t reg;
1732  struct
1733  {
1734  __IOM uint16_t INPCC60 : 2;
1735  __IOM uint16_t INPCC61 : 2;
1736  __IOM uint16_t INPCC62 : 2;
1737  __IOM uint16_t INPCHE : 2;
1738  __IOM uint16_t INPERR : 2;
1739  __IOM uint16_t INPT12 : 2;
1740  __IOM uint16_t INPT13 : 2;
1741  } bit;
1742  } INP;
1743  __IM uint16_t RESERVED18;
1744 
1745  union
1746  {
1747  __IOM uint16_t reg;
1749  struct
1750  {
1751  __OM uint16_t SCC60R : 1;
1752  __OM uint16_t SCC60F : 1;
1753  __OM uint16_t SCC61R : 1;
1754  __OM uint16_t SCC61F : 1;
1755  __OM uint16_t SCC62R : 1;
1756  __OM uint16_t SCC62F : 1;
1757  __OM uint16_t ST12OM : 1;
1758  __OM uint16_t ST12PM : 1;
1759  __OM uint16_t ST13CM : 1;
1760  __OM uint16_t ST13PM : 1;
1761  __OM uint16_t STRPF : 1;
1762  __OM uint16_t SWHC : 1;
1763  __OM uint16_t SCHE : 1;
1764  __OM uint16_t SWHE : 1;
1765  __OM uint16_t SIDLE : 1;
1766  __OM uint16_t SSTR : 1;
1767  } bit;
1768  } ISS;
1769  __IM uint16_t RESERVED19;
1770 
1771  union
1772  {
1773  __IOM uint16_t reg;
1775  struct
1776  {
1777  __IOM uint16_t PSL : 6;
1778  __IM uint16_t : 1;
1779  __IOM uint16_t PSL63 : 1;
1780  } bit;
1781  } PSLR;
1782  __IM uint16_t RESERVED20;
1783 
1784  union
1785  {
1786  __IOM uint16_t reg;
1788  struct
1789  {
1790  __IOM uint16_t SWSEL : 3;
1791  __IM uint16_t : 1;
1792  __IOM uint16_t SWSYN : 2;
1793  __IM uint16_t : 2;
1794  __IOM uint16_t STE12U : 1;
1795  __IOM uint16_t STE12D : 1;
1796  __IOM uint16_t STE13U : 1;
1797  } bit;
1798  } MCMCTR;
1799  __IM uint16_t RESERVED21;
1800 
1801  union
1802  {
1803  __IOM uint16_t reg;
1805  struct
1806  {
1807  __IOM uint16_t T12SSC : 1;
1808  __IOM uint16_t T13SSC : 1;
1809  __IOM uint16_t T13TEC : 3;
1810  __IOM uint16_t T13TED : 2;
1811  __IM uint16_t : 1;
1812  __IOM uint16_t T12RSEL : 2;
1813  __IOM uint16_t T13RSEL : 2;
1814  } bit;
1815  } TCTR2;
1816  __IM uint16_t RESERVED22;
1817 
1818  union
1819  {
1820  __IOM uint16_t reg;
1822  struct
1823  {
1824  __IOM uint16_t T12MODEN : 6;
1825  __IM uint16_t : 1;
1826  __IOM uint16_t MCMEN : 1;
1827  __IOM uint16_t T13MODEN : 6;
1828  __IM uint16_t : 1;
1829  __IOM uint16_t ECT13O : 1;
1830  } bit;
1831  } MODCTR;
1832  __IM uint16_t RESERVED23;
1833 
1834  union
1835  {
1836  __IOM uint16_t reg;
1838  struct
1839  {
1840  __IOM uint16_t TRPM0 : 1;
1841  __IOM uint16_t TRPM1 : 1;
1842  __IOM uint16_t TRPM2 : 1;
1843  __IM uint16_t : 5;
1844  __IOM uint16_t TRPEN : 6;
1845  __IOM uint16_t TRPEN13 : 1;
1846  __IOM uint16_t TRPPEN : 1;
1847  } bit;
1848  } TRPCTR;
1849  __IM uint16_t RESERVED24;
1850 
1851  union
1852  {
1853  __IOM uint16_t reg;
1855  struct
1856  {
1857  __IM uint16_t MCMP : 6;
1858  __IM uint16_t R : 1;
1859  __IM uint16_t : 1;
1860  __IM uint16_t EXPH : 3;
1861  __IM uint16_t CURH : 3;
1862  } bit;
1863  } MCMOUT;
1864  __IM uint16_t RESERVED25;
1865 
1866  union
1867  {
1868  __IOM uint16_t reg;
1870  struct
1871  {
1872  __IM uint16_t ICC60R : 1;
1873  __IM uint16_t ICC60F : 1;
1874  __IM uint16_t ICC61R : 1;
1875  __IM uint16_t ICC61F : 1;
1876  __IM uint16_t ICC62R : 1;
1877  __IM uint16_t ICC62F : 1;
1878  __IM uint16_t T12OM : 1;
1879  __IM uint16_t T12PM : 1;
1880  __IM uint16_t T13CM : 1;
1881  __IM uint16_t T13PM : 1;
1882  __IM uint16_t TRPF : 1;
1883  __IM uint16_t TRPS : 1;
1884  __IM uint16_t CHE : 1;
1885  __IM uint16_t WHE : 1;
1886  __IM uint16_t IDLE : 1;
1887  __IM uint16_t STR : 1;
1888  } bit;
1889  } IS;
1890  __IM uint16_t RESERVED26;
1891 
1892  union
1893  {
1894  __IOM uint16_t reg;
1896  struct
1897  {
1898  __IOM uint16_t ISCC60 : 2;
1899  __IOM uint16_t ISCC61 : 2;
1900  __IOM uint16_t ISCC62 : 2;
1901  __IOM uint16_t ISTRP : 2;
1902  __IOM uint16_t ISPOS0 : 2;
1903  __IOM uint16_t ISPOS1 : 2;
1904  __IOM uint16_t ISPOS2 : 2;
1905  __IOM uint16_t IST12HR : 2;
1906  } bit;
1907  } PISEL0;
1908  __IM uint16_t RESERVED27[3];
1909 
1910  union
1911  {
1912  __IOM uint16_t reg;
1914  struct
1915  {
1916  __IOM uint16_t IST13HR : 2;
1917  __IOM uint16_t ISCNT12 : 2;
1918  __IOM uint16_t ISCNT13 : 2;
1919  __IOM uint16_t T12EXT : 1;
1920  __IOM uint16_t T13EXT : 1;
1921  } bit;
1922  } PISEL2;
1923  __IM uint16_t RESERVED28;
1924 
1925  union
1926  {
1927  __IOM uint16_t reg;
1929  struct
1930  {
1931  __IOM uint16_t T12CV : 16;
1932  } bit;
1933  } T12;
1934  __IM uint16_t RESERVED29;
1935 
1936  union
1937  {
1938  __IOM uint16_t reg;
1940  struct
1941  {
1942  __IOM uint16_t T13CV : 16;
1943  } bit;
1944  } T13;
1945  __IM uint16_t RESERVED30;
1946 
1947  union
1948  {
1949  __IOM uint16_t reg;
1951  struct
1952  {
1953  __IM uint16_t CC60ST : 1;
1954  __IM uint16_t CC61ST : 1;
1955  __IM uint16_t CC62ST : 1;
1956  __IM uint16_t CCPOS0 : 1;
1957  __IM uint16_t CCPOS1 : 1;
1958  __IM uint16_t CCPOS2 : 1;
1959  __IM uint16_t CC63ST : 1;
1960  __IM uint16_t : 1;
1961  __IOM uint16_t CC60PS : 1;
1962  __IOM uint16_t COUT60PS : 1;
1963  __IOM uint16_t CC61PS : 1;
1964  __IOM uint16_t COUT61PS : 1;
1965  __IOM uint16_t CC62PS : 1;
1966  __IOM uint16_t COUT62PS : 1;
1967  __IOM uint16_t COUT63PS : 1;
1968  __IOM uint16_t T13IM : 1;
1969  } bit;
1970  } CMPSTAT;
1971 } CCU6_Type;
1975 /* =========================================================================================================================== */
1976 /* ================ CPU ================ */
1977 /* =========================================================================================================================== */
1978 
1979 
1984 typedef struct
1985 {
1986  __IM uint32_t RESERVED;
1987 
1988  union
1989  {
1990  __IOM uint32_t reg;
1992  struct
1993  {
1994  __IM uint32_t INTLINESNUM : 5;
1995  } bit;
1996  } ICT;
1997  __IM uint32_t RESERVED1[2];
1998 
1999  union
2000  {
2001  __IOM uint32_t reg;
2003  struct
2004  {
2005  __IOM uint32_t ENABLE : 1;
2006  __IOM uint32_t TICKINT : 1;
2007  __IOM uint32_t CLKSOURCE : 1;
2009  __IOM uint32_t COUNTFLAG : 1;
2010  } bit;
2011  } SYSTICK_CS;
2012 
2013  union
2014  {
2015  __IOM uint32_t reg;
2017  struct
2018  {
2019  __IOM uint32_t RELOAD : 24;
2020  } bit;
2021  } SYSTICK_RL;
2022 
2023  union
2024  {
2025  __IOM uint32_t reg;
2027  struct
2028  {
2029  __IOM uint32_t CURRENT : 24;
2030  } bit;
2031  } SYSTICK_CUR;
2032 
2033  union
2034  {
2035  __IOM uint32_t reg;
2037  struct
2038  {
2039  __IM uint32_t TENMS : 24;
2040  __IM uint32_t : 6;
2041  __IM uint32_t SKEW : 1;
2042  __IM uint32_t NOREF : 1;
2043  } bit;
2044  } SYSTICK_CAL;
2045  __IM uint32_t RESERVED2[56];
2046 
2047  union
2048  {
2049  __IOM uint32_t reg;
2051  struct
2052  {
2053  __IOM uint32_t Int_GPT1 : 1;
2054  __IOM uint32_t Int_GPT2 : 1;
2055  __IOM uint32_t Int_ADC2 : 1;
2056  __IOM uint32_t Int_ADC1 : 1;
2057  __IOM uint32_t Int_CCU6SR0 : 1;
2058  __IOM uint32_t Int_CCU6SR1 : 1;
2059  __IOM uint32_t Int_CCU6SR2 : 1;
2060  __IOM uint32_t Int_CCU6SR3 : 1;
2061  __IOM uint32_t Int_SSC1 : 1;
2062  __IOM uint32_t Int_SSC2 : 1;
2063  __IOM uint32_t Int_UART1 : 1;
2064  __IOM uint32_t Int_UART2 : 1;
2065  __IOM uint32_t Int_EXINT0 : 1;
2066  __IOM uint32_t Int_EXINT1 : 1;
2067  __IOM uint32_t Int_BDRV : 1;
2068  __IOM uint32_t Int_DMA : 1;
2069  } bit;
2070  } NVIC_ISER0;
2071  __IM uint32_t RESERVED3[31];
2072 
2073  union
2074  {
2075  __IOM uint32_t reg;
2077  struct
2078  {
2079  __IOM uint32_t Int_GPT1 : 1;
2080  __IOM uint32_t Int_GPT2 : 1;
2081  __IOM uint32_t Int_ADC2 : 1;
2082  __IOM uint32_t Int_ADC1 : 1;
2083  __IOM uint32_t Int_CCU6SR0 : 1;
2084  __IOM uint32_t Int_CCU6SR1 : 1;
2085  __IOM uint32_t Int_CCU6SR2 : 1;
2086  __IOM uint32_t Int_CCU6SR3 : 1;
2087  __IOM uint32_t Int_SSC1 : 1;
2088  __IOM uint32_t Int_SSC2 : 1;
2089  __IOM uint32_t Int_UART1 : 1;
2090  __IOM uint32_t Int_UART2 : 1;
2091  __IOM uint32_t Int_EXINT0 : 1;
2092  __IOM uint32_t Int_EXINT1 : 1;
2093  __IOM uint32_t Int_BDRV : 1;
2094  __IOM uint32_t Int_DMA : 1;
2095  } bit;
2096  } NVIC_ICER0;
2097  __IM uint32_t RESERVED4[31];
2098 
2099  union
2100  {
2101  __IOM uint32_t reg;
2103  struct
2104  {
2105  __IOM uint32_t Int_GPT1 : 1;
2106  __IOM uint32_t Int_GPT2 : 1;
2107  __IOM uint32_t Int_ADC2 : 1;
2108  __IOM uint32_t Int_ADC1 : 1;
2109  __IOM uint32_t Int_CCU6SR0 : 1;
2110  __IOM uint32_t Int_CCU6SR1 : 1;
2111  __IOM uint32_t Int_CCU6SR2 : 1;
2112  __IOM uint32_t Int_CCU6SR3 : 1;
2113  __IOM uint32_t Int_SSC1 : 1;
2114  __IOM uint32_t Int_SSC2 : 1;
2115  __IOM uint32_t Int_UART1 : 1;
2116  __IOM uint32_t Int_UART2 : 1;
2117  __IOM uint32_t Int_EXINT0 : 1;
2118  __IOM uint32_t Int_EXINT1 : 1;
2119  __IOM uint32_t Int_BDRV : 1;
2120  __IOM uint32_t Int_DMA : 1;
2121  } bit;
2122  } NVIC_ISPR0;
2123  __IM uint32_t RESERVED5[31];
2124 
2125  union
2126  {
2127  __IOM uint32_t reg;
2129  struct
2130  {
2131  __IOM uint32_t Int_GPT1 : 1;
2132  __IOM uint32_t Int_GPT2 : 1;
2133  __IOM uint32_t Int_ADC2 : 1;
2134  __IOM uint32_t Int_ADC1 : 1;
2135  __IOM uint32_t Int_CCU6SR0 : 1;
2136  __IOM uint32_t Int_CCU6SR1 : 1;
2137  __IOM uint32_t Int_CCU6SR2 : 1;
2138  __IOM uint32_t Int_CCU6SR3 : 1;
2139  __IOM uint32_t Int_SSC1 : 1;
2140  __IOM uint32_t Int_SSC2 : 1;
2141  __IOM uint32_t Int_UART1 : 1;
2142  __IOM uint32_t Int_UART2 : 1;
2143  __IOM uint32_t Int_EXINT0 : 1;
2144  __IOM uint32_t Int_EXINT1 : 1;
2145  __IOM uint32_t Int_BDRV : 1;
2146  __IOM uint32_t Int_DMA : 1;
2147  } bit;
2148  } NVIC_ICPR0;
2149  __IM uint32_t RESERVED6[31];
2150 
2151  union
2152  {
2153  __IOM uint32_t reg;
2155  struct
2156  {
2157  __IM uint32_t Int_GPT1 : 1;
2158  __IM uint32_t Int_GPT2 : 1;
2159  __IM uint32_t Int_ADC2 : 1;
2160  __IM uint32_t Int_ADC1 : 1;
2161  __IM uint32_t Int_CCU6SR0 : 1;
2162  __IM uint32_t Int_CCU6SR1 : 1;
2163  __IM uint32_t Int_CCU6SR2 : 1;
2164  __IM uint32_t Int_CCU6SR3 : 1;
2165  __IM uint32_t Int_SSC1 : 1;
2166  __IM uint32_t Int_SSC2 : 1;
2167  __IM uint32_t Int_UART1 : 1;
2168  __IM uint32_t Int_UART2 : 1;
2169  __IM uint32_t Int_EXINT0 : 1;
2170  __IM uint32_t Int_EXINT1 : 1;
2171  __IM uint32_t Int_BDRV : 1;
2172  __IM uint32_t Int_DMA : 1;
2173  } bit;
2174  } NVIC_IABR0;
2175  __IM uint32_t RESERVED7[63];
2176 
2177  union
2178  {
2179  __IOM uint32_t reg;
2181  struct
2182  {
2183  __IOM uint32_t PRI_GPT1 : 8;
2184  __IOM uint32_t PRI_GPT2 : 8;
2185  __IOM uint32_t PRI_ADC2 : 8;
2186  __IOM uint32_t PRI_ADC1 : 8;
2187  } bit;
2188  } NVIC_IPR0;
2189 
2190  union
2191  {
2192  __IOM uint32_t reg;
2194  struct
2195  {
2196  __IOM uint32_t PRI_CCU6SR0 : 8;
2197  __IOM uint32_t PRI_CCU6SR1 : 8;
2198  __IOM uint32_t PRI_CCU6SR2 : 8;
2199  __IOM uint32_t PRI_CCU6SR3 : 8;
2200  } bit;
2201  } NVIC_IPR1;
2202 
2203  union
2204  {
2205  __IOM uint32_t reg;
2207  struct
2208  {
2209  __IOM uint32_t PRI_SSC1 : 8;
2210  __IOM uint32_t PRI_SSC2 : 8;
2211  __IOM uint32_t PRI_UART1 : 8;
2212  __IOM uint32_t PRI_UART2 : 8;
2213  } bit;
2214  } NVIC_IPR2;
2215 
2216  union
2217  {
2218  __IOM uint32_t reg;
2220  struct
2221  {
2222  __IOM uint32_t PRI_EXINT0 : 8;
2223  __IOM uint32_t PRI_EXINT1 : 8;
2224  __IOM uint32_t PRI_BDRV : 8;
2225  __IOM uint32_t PRI_DMA : 8;
2226  } bit;
2227  } NVIC_IPR3;
2228  __IM uint32_t RESERVED8[572];
2229 
2230  union
2231  {
2232  __IOM uint32_t reg;
2234  struct
2235  {
2236  __IM uint32_t REVISION : 4;
2237  __IM uint32_t PARTNO : 12;
2238  __IM uint32_t ARCHITECTURE : 4;
2239  __IM uint32_t VARIANT : 4;
2240  __IM uint32_t IMPLEMENTER : 8;
2241  } bit;
2242  } CPUID;
2243 
2244  union
2245  {
2246  __IOM uint32_t reg;
2248  struct
2249  {
2250  __IM uint32_t VECTACTIVE : 9;
2251  __IM uint32_t : 2;
2252  __IM uint32_t RETTOBASE : 1;
2253  __IM uint32_t VECTPENDING : 9;
2254  __IM uint32_t : 1;
2255  __IM uint32_t ISRPENDING : 1;
2256  __IM uint32_t ISRPREEMPT : 1;
2257  __IM uint32_t : 1;
2258  __OM uint32_t PENDSTCLR : 1;
2259  __IOM uint32_t PENDSTSET : 1;
2260  __OM uint32_t PENDSVCLR : 1;
2261  __IOM uint32_t PENDSVSET : 1;
2262  __IM uint32_t : 2;
2263  __IOM uint32_t NMIPENDSET : 1;
2264  } bit;
2265  } ICSR;
2266 
2267  union
2268  {
2269  __IOM uint32_t reg;
2271  struct
2272  {
2273  __IM uint32_t : 7;
2274  __IOM uint32_t TBLOFF : 25;
2275  } bit;
2276  } VTOR;
2277 
2278  union
2279  {
2280  __IOM uint32_t reg;
2282  struct
2283  {
2284  __IOM uint32_t VECTRESET : 1;
2285  __IOM uint32_t VECTCLRACTIVE : 1;
2286  __IOM uint32_t SYSRESETREQ : 1;
2287  __IM uint32_t : 5;
2288  __IOM uint32_t PRIGROUP : 3;
2289  __IM uint32_t : 4;
2290  __IM uint32_t ENDIANNESS : 1;
2291  __IOM uint32_t VECTKEY : 16;
2292  } bit;
2293  } AIRCR;
2294 
2295  union
2296  {
2297  __IOM uint32_t reg;
2299  struct
2300  {
2301  __IM uint32_t : 1;
2302  __IOM uint32_t SLEEPONEXIT : 1;
2303  __IOM uint32_t SLEEPDEEP : 1;
2304  __IM uint32_t : 1;
2305  __IOM uint32_t SEVONPEND : 1;
2306  } bit;
2307  } SCR;
2308 
2309  union
2310  {
2311  __IOM uint32_t reg;
2313  struct
2314  {
2315  __IOM uint32_t NONBASETHRDENA : 1;
2316  __IOM uint32_t USERSETMPEND : 1;
2317  __IM uint32_t : 1;
2318  __IOM uint32_t UNALIGN_TRP : 1;
2319  __IOM uint32_t DIV_0_TRP : 1;
2321  __IM uint32_t : 3;
2322  __IOM uint32_t BFHFMIGN : 1;
2324  __IOM uint32_t STKALIGN : 1;
2325  } bit;
2326  } CCR;
2327 
2328  union
2329  {
2330  __IOM uint32_t reg;
2332  struct
2333  {
2334  __IOM uint32_t PRI_4 : 8;
2335  __IOM uint32_t PRI_5 : 8;
2336  __IOM uint32_t PRI_6 : 8;
2337  __IOM uint32_t PRI_7 : 8;
2338  } bit;
2339  } SHPR1;
2340 
2341  union
2342  {
2343  __IOM uint32_t reg;
2345  struct
2346  {
2347  __IOM uint32_t PRI_8 : 8;
2348  __IOM uint32_t PRI_9 : 8;
2349  __IOM uint32_t PRI_10 : 8;
2350  __IOM uint32_t PRI_11 : 8;
2351  } bit;
2352  } SHPR2;
2353 
2354  union
2355  {
2356  __IOM uint32_t reg;
2358  struct
2359  {
2360  __IOM uint32_t PRI_12 : 8;
2361  __IOM uint32_t PRI_13 : 8;
2362  __IOM uint32_t PRI_14 : 8;
2363  __IOM uint32_t PRI_15 : 8;
2364  } bit;
2365  } SHPR3;
2366 
2367  union
2368  {
2369  __IOM uint32_t reg;
2371  struct
2372  {
2373  __IOM uint32_t MEMFAULTACT : 1;
2374  __IOM uint32_t BUSFAULTACT : 1;
2375  __IM uint32_t : 1;
2376  __IOM uint32_t USGFAULTACT : 1;
2377  __IM uint32_t : 3;
2378  __IOM uint32_t SVCALLACT : 1;
2379  __IOM uint32_t MONITORACT : 1;
2380  __IM uint32_t : 1;
2381  __IOM uint32_t PENDSVACT : 1;
2382  __IOM uint32_t SYSTICKACT : 1;
2383  __IOM uint32_t USGFAULTPENDED : 1;
2384  __IOM uint32_t MEMFAULTPENDED : 1;
2385  __IOM uint32_t BUSFAULTPENDED : 1;
2386  __IOM uint32_t SVCALLPENDED : 1;
2387  __IOM uint32_t MEMFAULTENA : 1;
2388  __IOM uint32_t BUSFAULTENA : 1;
2389  __IOM uint32_t USGFAULTENA : 1;
2390  } bit;
2391  } SHCSR;
2392 
2393  union
2394  {
2395  __IOM uint32_t reg;
2397  struct
2398  {
2399  __IOM uint32_t IACCVIOL : 1;
2400  __IOM uint32_t DACCVIOL : 1;
2401  __IM uint32_t : 1;
2402  __IOM uint32_t MUNSTKERR : 1;
2403  __IOM uint32_t MSTERR : 1;
2404  __IM uint32_t : 2;
2405  __IOM uint32_t MMARVALID : 1;
2406  __IOM uint32_t IBUSERR : 1;
2407  __IOM uint32_t PRECISERR : 1;
2408  __IOM uint32_t IMPRECISERR : 1;
2409  __IOM uint32_t UNSTKERR : 1;
2410  __IOM uint32_t STKERR : 1;
2411  __IM uint32_t : 2;
2412  __IOM uint32_t BFARVALID : 1;
2413  __IOM uint32_t UNDEFINSTR : 1;
2414  __IOM uint32_t INVSTATE : 1;
2415  __IOM uint32_t INVPC : 1;
2416  __IOM uint32_t NOCP : 1;
2417  __IM uint32_t : 4;
2418  __IOM uint32_t UNALIGNED : 1;
2419  __IOM uint32_t DIVBYZERO : 1;
2420  } bit;
2421  } CFSR;
2422 
2423  union
2424  {
2425  __IOM uint32_t reg;
2427  struct
2428  {
2429  __IM uint32_t : 1;
2430  __IOM uint32_t VECTTBL : 1;
2431  __IM uint32_t : 28;
2432  __IOM uint32_t FORCED : 1;
2433  __IOM uint32_t DEBUGEVT : 1;
2434  } bit;
2435  } HFSR;
2436 
2437  union
2438  {
2439  __IOM uint32_t reg;
2441  struct
2442  {
2443  __IOM uint32_t HALTED : 1;
2444  __IOM uint32_t BKPT : 1;
2445  __IOM uint32_t DWTTRAP : 1;
2446  __IOM uint32_t VCATCH : 1;
2447  __IOM uint32_t EXTERNAL : 1;
2448  } bit;
2449  } DFSR;
2450 
2451  union
2452  {
2453  __IOM uint32_t reg;
2455  struct
2456  {
2457  __IOM uint32_t ADDRESS : 32;
2458  } bit;
2459  } MMFAR;
2460 
2461  union
2462  {
2463  __IOM uint32_t reg;
2465  struct
2466  {
2467  __IOM uint32_t ADDRESS : 32;
2468  } bit;
2469  } BFAR;
2470 
2471  union
2472  {
2473  __IOM uint32_t reg;
2475  struct
2476  {
2477  __IOM uint32_t CP0 : 2;
2478  __IOM uint32_t CP1 : 2;
2479  __IOM uint32_t CP2 : 2;
2480  __IOM uint32_t CP3 : 2;
2481  __IOM uint32_t CP4 : 2;
2482  __IOM uint32_t CP5 : 2;
2483  __IOM uint32_t CP6 : 2;
2484  __IOM uint32_t CP7 : 2;
2485  __IM uint32_t : 4;
2486  __IOM uint32_t CP10 : 2;
2487  __IOM uint32_t CP11 : 2;
2488  } bit;
2489  } AFSR;
2490 } CPU_Type;
2494 /* ================================================================================ */
2495 /* ================ CSA ================ */
2496 /* ================================================================================ */
2497 
2498 
2503 typedef struct
2504 {
2505  __I uint32_t RESERVED0[3];
2506 
2507  union
2508  {
2509  __IO uint32_t reg;
2511  struct
2512  {
2513  __IO uint32_t EN : 1;
2514  __IO uint32_t GAIN : 2;
2515  uint32_t : 5;
2516  __IO uint32_t VZERO : 1;
2517  } bit;
2518  } CTRL;
2519 } CSA_Type;
2520 
2521 
2522 /* =========================================================================================================================== */
2523 /* ================ DMA ================ */
2524 /* =========================================================================================================================== */
2525 
2526 
2531 typedef struct
2532 {
2533 
2534  union
2535  {
2536  __IOM uint32_t reg;
2538  struct
2539  {
2540  __IM uint32_t MASTER_ENABLE : 1;
2542  __IM uint32_t STATE : 4;
2543  __IM uint32_t : 8;
2544  __IM uint32_t CHNLS_MINUS1 : 5;
2545  } bit;
2546  } STATUS;
2547 
2548  union
2549  {
2550  __IOM uint32_t reg;
2552  struct
2553  {
2554  __OM uint32_t MASTER_ENABLE : 1;
2555  __IM uint32_t : 4;
2556  __OM uint32_t CHN1_PROT_CTRL : 3;
2557  } bit;
2558  } CFG;
2559 
2560  union
2561  {
2562  __IOM uint32_t reg;
2564  struct
2565  {
2566  __IM uint32_t : 9;
2567  __IOM uint32_t CTRL_BASE_PTR : 23;
2568  } bit;
2569  } CTRL_BASE_PTR;
2570 
2571  union
2572  {
2573  __IOM uint32_t reg;
2575  struct
2576  {
2577  __IM uint32_t ALT_CTRL_BASE_PTR : 32;
2578  } bit;
2579  } ALT_CTRL_BASE_PTR;
2580 
2581  union
2582  {
2583  __IOM uint32_t reg;
2585  struct
2586  {
2587  __IM uint32_t WAITONREQ_STATUS : 14;
2588  } bit;
2589  } WAITONREQ_STATUS;
2590 
2591  union
2592  {
2593  __IOM uint32_t reg;
2595  struct
2596  {
2597  __OM uint32_t CHNL_SW_REQUEST : 14;
2598  } bit;
2599  } CHNL_SW_REQUEST;
2600 
2601  union
2602  {
2603  __IOM uint32_t reg;
2605  struct
2606  {
2607  __IOM uint32_t CHNL_USEBURST_SET : 14;
2616  } bit;
2617  } CHNL_USEBURST_SET;
2618 
2619  union
2620  {
2621  __IOM uint32_t reg;
2623  struct
2624  {
2625  __OM uint32_t CHNL_USEBURST_CLR : 14;
2626  } bit;
2627  } CHNL_USEBURST_CLR;
2628 
2629  union
2630  {
2631  __IOM uint32_t reg;
2633  struct
2634  {
2635  __IOM uint32_t CHNL_REQ_MASK_SET : 14;
2641  } bit;
2642  } CHNL_REQ_MASK_SET;
2643 
2644  union
2645  {
2646  __IOM uint32_t reg;
2648  struct
2649  {
2650  __OM uint32_t CHNL_REQ_MASK_CLR : 14;
2651  } bit;
2652  } CHNL_REQ_MASK_CLR;
2653 
2654  union
2655  {
2656  __IOM uint32_t reg;
2658  struct
2659  {
2660  __IOM uint32_t CHNL_ENABLE_SET : 14;
2664  } bit;
2665  } CHNL_ENABLE_SET;
2666 
2667  union
2668  {
2669  __IOM uint32_t reg;
2671  struct
2672  {
2673  __OM uint32_t CHNL_ENABLE_CLR : 14;
2674  } bit;
2675  } CHNL_ENABLE_CLR;
2676 
2677  union
2678  {
2679  __IOM uint32_t reg;
2681  struct
2682  {
2683  __IOM uint32_t CHNL_PRI_ALT_SET : 14;
2689  } bit;
2690  } CHNL_PRI_ALT_SET;
2691 
2692  union
2693  {
2694  __IOM uint32_t reg;
2696  struct
2697  {
2698  __OM uint32_t CHNL_PRI_ALT_CLR : 14;
2699  } bit;
2700  } CHNL_PRI_ALT_CLR;
2701 
2702  union
2703  {
2704  __IOM uint32_t reg;
2706  struct
2707  {
2708  __IOM uint32_t CHNL_PRIORITY_SET : 14;
2714  } bit;
2715  } CHNL_PRIORITY_SET;
2716 
2717  union
2718  {
2719  __IOM uint32_t reg;
2721  struct
2722  {
2723  __OM uint32_t CHNL_PRIORITY_CLR : 14;
2724  } bit;
2725  } CHNL_PRIORITY_CLR;
2726  __IM uint32_t RESERVED[3];
2727 
2728  union
2729  {
2730  __IOM uint32_t reg;
2732  struct
2733  {
2734  __IOM uint32_t ERR_CLR : 1;
2737  } bit;
2738  } ERR_CLR;
2739 } DMA_Type;
2743 /* =========================================================================================================================== */
2744 /* ================ GPT12E ================ */
2745 /* =========================================================================================================================== */
2746 
2747 
2752 typedef struct
2753 {
2754 
2755  union
2756  {
2757  __IOM uint16_t reg;
2759  struct
2760  {
2761  __IM uint16_t MOD_REV : 8;
2762  __IM uint16_t MOD_TYPE : 8;
2763  } bit;
2764  } ID;
2765  __IM uint16_t RESERVED;
2766 
2767  union
2768  {
2769  __IOM uint16_t reg;
2771  struct
2772  {
2773  __IOM uint16_t IST2IN : 1;
2774  __IOM uint16_t IST2EUD : 1;
2775  __IOM uint16_t IST3IN : 2;
2776  __IOM uint16_t IST3EUD : 2;
2777  __IOM uint16_t IST4IN : 2;
2778  __IOM uint16_t IST4EUD : 2;
2779  __IOM uint16_t IST5IN : 1;
2780  __IOM uint16_t IST5EUD : 1;
2781  __IOM uint16_t IST6IN : 1;
2782  __IOM uint16_t IST6EUD : 1;
2783  __IOM uint16_t ISCAPIN : 2;
2784  } bit;
2785  } PISEL;
2786  __IM uint16_t RESERVED1;
2787 
2788  union
2789  {
2790  __IOM uint16_t reg;
2792  struct
2793  {
2794  __IOM uint16_t T2I : 3;
2795  __IOM uint16_t T2M : 3;
2796  __IOM uint16_t T2R : 1;
2797  __IOM uint16_t T2UD : 1;
2798  __IOM uint16_t T2UDE : 1;
2799  __IOM uint16_t T2RC : 1;
2801  __IOM uint16_t T2IRDIS : 1;
2802  __IOM uint16_t T2EDGE : 1;
2803  __IOM uint16_t T2CHDIR : 1;
2804  __IM uint16_t T2RDIR : 1;
2805  } bit;
2806  } T2CON;
2807  __IM uint16_t RESERVED2;
2808 
2809  union
2810  {
2811  __IOM uint16_t reg;
2813  struct
2814  {
2815  __IOM uint16_t T3I : 3;
2816  __IOM uint16_t T3M : 3;
2817  __IOM uint16_t T3R : 1;
2818  __IOM uint16_t T3UD : 1;
2819  __IOM uint16_t T3UDE : 1;
2820  __IOM uint16_t T3OE : 1;
2821  __IOM uint16_t T3OTL : 1;
2822  __IOM uint16_t BPS1 : 2;
2823  __IOM uint16_t T3EDGE : 1;
2824  __IOM uint16_t T3CHDIR : 1;
2825  __IM uint16_t T3RDIR : 1;
2826  } bit;
2827  } T3CON;
2828  __IM uint16_t RESERVED3;
2829 
2830  union
2831  {
2832  __IOM uint16_t reg;
2834  struct
2835  {
2836  __IOM uint16_t T4I : 3;
2837  __IOM uint16_t T4M : 3;
2838  __IOM uint16_t T4R : 1;
2839  __IOM uint16_t T4UD : 1;
2840  __IOM uint16_t T4UDE : 1;
2841  __IOM uint16_t T4RC : 1;
2842  __IOM uint16_t CLRT2EN : 1;
2843  __IOM uint16_t CLRT3EN : 1;
2844  __IOM uint16_t T4IRDIS : 1;
2845  __IOM uint16_t T4EDGE : 1;
2846  __IOM uint16_t T4CHDIR : 1;
2847  __IM uint16_t T4RDIR : 1;
2848  } bit;
2849  } T4CON;
2850  __IM uint16_t RESERVED4;
2851 
2852  union
2853  {
2854  __IOM uint16_t reg;
2856  struct
2857  {
2858  __IOM uint16_t T5I : 3;
2859  __IOM uint16_t T5M : 2;
2860  __IM uint16_t : 1;
2861  __IOM uint16_t T5R : 1;
2862  __IOM uint16_t T5UD : 1;
2863  __IOM uint16_t T5UDE : 1;
2864  __IOM uint16_t T5RC : 1;
2865  __IOM uint16_t CT3 : 1;
2866  __IM uint16_t : 1;
2867  __IOM uint16_t CI : 2;
2868  __IOM uint16_t T5CLR : 1;
2869  __IOM uint16_t T5SC : 1;
2870  } bit;
2871  } T5CON;
2872  __IM uint16_t RESERVED5;
2873 
2874  union
2875  {
2876  __IOM uint16_t reg;
2878  struct
2879  {
2880  __IOM uint16_t T6I : 3;
2881  __IOM uint16_t T6M : 3;
2882  __IOM uint16_t T6R : 1;
2883  __IOM uint16_t T6UD : 1;
2884  __IOM uint16_t T6UDE : 1;
2885  __IOM uint16_t T6OE : 1;
2886  __IOM uint16_t T6OTL : 1;
2887  __IOM uint16_t BPS2 : 2;
2888  __IM uint16_t : 1;
2889  __IOM uint16_t T6CLR : 1;
2890  __IOM uint16_t T6SR : 1;
2891  } bit;
2892  } T6CON;
2893  __IM uint16_t RESERVED6;
2894 
2895  union
2896  {
2897  __IOM uint16_t reg;
2899  struct
2900  {
2901  __IOM uint16_t CAPREL : 16;
2902  } bit;
2903  } CAPREL;
2904  __IM uint16_t RESERVED7;
2905 
2906  union
2907  {
2908  __IOM uint16_t reg;
2910  struct
2911  {
2912  __IOM uint16_t T2 : 16;
2913  } bit;
2914  } T2;
2915  __IM uint16_t RESERVED8;
2916 
2917  union
2918  {
2919  __IOM uint16_t reg;
2921  struct
2922  {
2923  __IOM uint16_t T3 : 16;
2924  } bit;
2925  } T3;
2926  __IM uint16_t RESERVED9;
2927 
2928  union
2929  {
2930  __IOM uint16_t reg;
2932  struct
2933  {
2934  __IOM uint16_t T4 : 16;
2935  } bit;
2936  } T4;
2937  __IM uint16_t RESERVED10;
2938 
2939  union
2940  {
2941  __IOM uint16_t reg;
2943  struct
2944  {
2945  __IOM uint16_t T5 : 16;
2946  } bit;
2947  } T5;
2948  __IM uint16_t RESERVED11;
2949 
2950  union
2951  {
2952  __IOM uint16_t reg;
2954  struct
2955  {
2956  __IOM uint16_t T6 : 16;
2957  } bit;
2958  } T6;
2959 } GPT12E_Type;
2963 /* =========================================================================================================================== */
2964 /* ================ LIN ================ */
2965 /* =========================================================================================================================== */
2966 
2967 
2972 typedef struct
2973 {
2974 
2975  union
2976  {
2977  __IOM uint32_t reg;
2979  struct
2980  {
2982  __IOM uint32_t MODE : 2;
2983  __IM uint32_t M_SM_ERR : 1;
2984  __IM uint32_t OT_STS : 1;
2985  __IM uint32_t OC_STS : 1;
2986  __IM uint32_t TXD_TMOUT_STS : 1;
2987  __IM uint32_t : 2;
2988  __IOM uint32_t TXD : 1;
2990  __IM uint32_t RXD : 1;
2991  __IOM uint32_t SM : 2;
2992  __IM uint32_t FB_SM1 : 1;
2993  __IM uint32_t FB_SM2 : 1;
2994  __IM uint32_t FB_SM3 : 1;
2995  __IM uint32_t MODE_FB : 3;
2996  __IM uint32_t : 2;
2997  __IOM uint32_t HV_MODE : 1;
2998  __IM uint32_t : 2;
2999  __IOM uint32_t M_SM_ERR_CLR : 1;
3000  } bit;
3001  } CTRL_STS;
3002 } LIN_Type;
3006 /* =========================================================================================================================== */
3007 /* ================ MF ================ */
3008 /* =========================================================================================================================== */
3009 
3010 
3015 typedef struct
3016 {
3017 
3018  union
3019  {
3020  __IOM uint32_t reg;
3022  struct
3023  {
3024  __IOM uint32_t P2_0_ADC_SEL : 1;
3025  __IOM uint32_t P2_2_ADC_SEL : 1;
3026  __IOM uint32_t P2_3_ADC_SEL : 1;
3027  __IOM uint32_t P2_4_ADC_SEL : 1;
3028  __IOM uint32_t P2_5_ADC_SEL : 1;
3030  __IOM uint32_t ADC3_INP_SEL : 1;
3031  __IOM uint32_t ADC3_INN_SEL : 1;
3032  __IOM uint32_t ADC1_CH1_SEL : 1;
3033  } bit;
3034  } P2_ADCSEL_CTRL;
3035 
3036  union
3037  {
3038  __IOM uint32_t reg;
3040  struct
3041  {
3042  __IOM uint32_t VMON_SEN_PD_N : 1;
3043  __IM uint32_t : 3;
3044  __IOM uint32_t VMON_SEN_HRESO_5V : 1;
3046  } bit;
3047  } VMON_SEN_CTRL;
3048 
3049  union
3050  {
3051  __IOM uint32_t reg;
3053  struct
3054  {
3055  __IOM uint32_t PHUCOMP_EN : 1;
3056  __IOM uint32_t PHVCOMP_EN : 1;
3057  __IOM uint32_t PHWCOMP_EN : 1;
3058  __IOM uint32_t DEMGFILTDIS : 1;
3059  __IOM uint32_t FILTBYPS : 1;
3060  __IOM uint32_t GPT12CAPINSW : 1;
3061  __IM uint32_t : 2;
3062  __IOM uint32_t PHUCOMP_ON : 1;
3063  __IOM uint32_t PHVCOMP_ON : 1;
3064  __IOM uint32_t PHWCOMP_ON : 1;
3065  __IM uint32_t : 1;
3066  __IOM uint32_t CCPOS_INSEL : 1;
3067  __IM uint32_t : 3;
3068  __IM uint32_t PHU_ZC_STS : 1;
3069  __IM uint32_t PHV_ZC_STS : 1;
3070  __IM uint32_t PHW_ZC_STS : 1;
3071  } bit;
3072  } BEMFC_CTRL_STS;
3073  __IM uint32_t RESERVED0;
3074 
3075  union
3076  {
3077  __IOM uint32_t reg;
3079  struct
3080  {
3081  __IM uint32_t : 4;
3082  __IM uint32_t PMU_OTWARN_STS : 1;
3083  __IM uint32_t PMU_OT_STS : 1;
3084  __IM uint32_t SYS_OTWARN_STS : 1;
3085  __IM uint32_t SYS_OT_STS : 1;
3086  } bit;
3087  } TEMPSENSE_CTRL;
3088 
3089  union
3090  {
3091  __IOM uint32_t reg;
3093  struct
3094  {
3095  __IM uint32_t : 4;
3096  __IM uint32_t REFBG_LOTHWARN_STS : 1;
3098  __IM uint32_t REFBG_UPTHWARN_STS : 1;
3100  } bit;
3101  } REF1_STS;
3102 
3103  union
3104  {
3105  __IOM uint32_t reg;
3107  struct
3108  {
3109  __IOM uint32_t VREF5V_PD_N : 1;
3110  __IM uint32_t VREF5V_OVL_STS : 1;
3111  __IM uint32_t VREF5V_UV_STS : 1;
3112  __IM uint32_t VREF5V_OV_STS : 1;
3113  } bit;
3114  } REF2_CTRL;
3115  __IM uint32_t RESERVED1;
3116 
3117  union
3118  {
3119  __IOM uint32_t reg;
3121  struct
3122  {
3123  __IOM uint32_t BEMF_BT_TFILT_SEL : 3;
3124  __IM uint32_t : 1;
3125  __IOM uint32_t BEMF_GPT_CAPIN_SEL : 2;
3126  __IM uint32_t : 2;
3127  __IOM uint32_t BEMF_TFILT_SEL : 2;
3128  } bit;
3129  } TRIM_BEMFx;
3130 } MF_Type;
3133 /* =========================================================================================================================== */
3134 /* ================ MON ================ */
3135 /* =========================================================================================================================== */
3136 
3137 
3142 typedef struct
3143 {
3144  __I uint32_t RESERVED0[13];
3145 
3146  union
3147  {
3148  __IO uint8_t reg;
3150  struct
3151  {
3152  __IO uint8_t EN : 1;
3153  __IO uint8_t FALL : 1;
3154  __IO uint8_t RISE : 1;
3155  __IO uint8_t CYC : 1;
3156  __IO uint8_t PD : 1;
3157  __IO uint8_t PU : 1;
3158  uint8_t : 1;
3159  __I uint8_t STS : 1;
3160  } bit;
3161  } CNF;
3162 } MON_Type;
3163 
3164 
3165 /* =========================================================================================================================== */
3166 /* ================ PMU ================ */
3167 /* =========================================================================================================================== */
3168 
3169 
3174 typedef struct
3175 {
3176 
3177  union
3178  {
3179  __IOM uint8_t reg;
3181  struct
3182  {
3183  __IM uint8_t LIN_WAKE : 1;
3184  __IM uint8_t MON_WAKE : 1;
3185  __IM uint8_t GPIO0 : 1;
3187  __IM uint8_t GPIO1 : 1;
3189  __IM uint8_t CYC_WAKE : 1;
3190  __IM uint8_t FAIL : 1;
3191  } bit;
3192  } WAKE_STATUS;
3193  __IM uint8_t RESERVED[3];
3194 
3195  union
3196  {
3197  __IOM uint8_t reg;
3199  struct
3200  {
3201  __IM uint8_t PMU_1V5_OVERVOLT : 1;
3202  __IM uint8_t PMU_1V5_OVERLOAD : 1;
3203  __IOM uint8_t PMU_1V5_FAIL_EN : 1;
3205  __IM uint8_t PMU_5V_OVERVOLT : 1;
3206  __IM uint8_t PMU_5V_OVERLOAD : 1;
3207  __IOM uint8_t PMU_5V_FAIL_EN : 1;
3208  } bit;
3209  } PMU_SUPPLY_STS;
3210  __IM uint8_t RESERVED1[3];
3211 
3212  union
3213  {
3214  __IOM uint8_t reg;
3216  struct
3217  {
3218  __IOM uint8_t ENABLE : 1;
3219  __IOM uint8_t CYC_EN : 1;
3220  __IOM uint8_t FAIL_EN : 1;
3222  __IOM uint8_t SHORT : 1;
3223  __IOM uint8_t OVERVOLT : 1;
3224  __IOM uint8_t OVERLOAD : 1;
3225  __IM uint8_t OK : 1;
3226  __IM uint8_t STABLE : 1;
3227  } bit;
3228  } VDDEXT_CTRL;
3229  __IM uint8_t RESERVED2[7];
3230 
3231  union
3232  {
3233  __IOM uint8_t reg;
3235  struct
3236  {
3237  __IOM uint8_t SYS_FAIL : 1;
3239  __IOM uint8_t PMU_WAKE : 1;
3240  __IOM uint8_t PMU_SleepEX : 1;
3241  __IOM uint8_t PMU_LPR : 1;
3242  __IOM uint8_t PMU_ClkWDT : 1;
3243  __IOM uint8_t PMU_ExtWDT : 1;
3244  __IOM uint8_t PMU_PIN : 1;
3245  __IOM uint8_t PMU_1V5DidPOR : 1;
3246  } bit;
3247  } PMU_RESET_STS1;
3248  __IM uint8_t RESERVED3[3];
3249 
3250  union
3251  {
3252  __IOM uint8_t reg;
3254  struct
3255  {
3256  __IOM uint8_t PMU_IntWDT : 1;
3257  __IOM uint8_t PMU_SOFT : 1;
3258  __IOM uint8_t LOCKUP : 1;
3259  } bit;
3260  } PMU_RESET_STS2;
3261  __IM uint8_t RESERVED4[11];
3262 
3263  union
3264  {
3265  __IOM uint8_t reg;
3267  struct
3268  {
3269  __IOM uint8_t WAKE_W_RST : 1;
3270  __IOM uint8_t EN_0V9_N : 1;
3272  __IOM uint8_t CYC_WAKE_EN : 1;
3273  __IOM uint8_t CYC_SENSE_EN : 1;
3274  __IM uint8_t : 3;
3276  } bit;
3277  } CNF_PMU_SETTINGS;
3278  __IM uint8_t RESERVED5[7];
3279 
3280  union
3281  {
3282  __IOM uint8_t reg;
3284  struct
3285  {
3286  __IOM uint8_t M03 : 4;
3287  __IOM uint8_t E01 : 2;
3288  __IM uint8_t : 1;
3289  __IOM uint8_t OSC_100kHz_EN : 1;
3290  } bit;
3291  } CNF_CYC_SENSE;
3292  __IM uint8_t RESERVED6[3];
3293 
3294  union
3295  {
3296  __IOM uint8_t reg;
3298  struct
3299  {
3300  __IOM uint8_t M03 : 4;
3301  __IOM uint8_t E01 : 2;
3302  } bit;
3303  } CNF_CYC_WAKE;
3304  __IM uint8_t RESERVED7[3];
3305 
3306  union
3307  {
3308  __IOM uint8_t reg;
3310  struct
3311  {
3312  __IOM uint8_t M03 : 4;
3313  } bit;
3314  } CNF_CYC_SAMPLE_DEL;
3315  __IM uint8_t RESERVED9[31];
3316 
3317  union
3318  {
3319  __IOM uint8_t reg;
3321  struct
3322  {
3323  __IM uint8_t : 7;
3324  __IOM uint8_t LIN_EN : 1;
3325  } bit;
3326  } LIN_WAKE_EN;
3327  __IM uint8_t RESERVED10[27];
3328 
3329  union
3330  {
3331  __IOM uint8_t reg;
3333  struct
3334  {
3335  __IOM uint8_t RST_TFB : 2;
3336  } bit;
3337  } CNF_RST_TFB;
3338  __IM uint8_t RESERVED11[3];
3339 
3340  union
3341  {
3342  __IOM uint8_t reg;
3344  struct
3345  {
3346  __IOM uint8_t SUPP_SHORT : 1;
3347  __IOM uint8_t SUPP_TMOUT : 1;
3348  __IOM uint8_t PMU_1V5_OVL : 1;
3349  __IOM uint8_t PMU_5V_OVL : 1;
3350  __IM uint8_t : 1;
3351  __IOM uint8_t SYS_OT : 1;
3352  __IOM uint8_t WDT1_SEQ_FAIL : 1;
3353  } bit;
3354  } SYS_FAIL_STS;
3355  __IM uint8_t RESERVED12[15];
3356 
3357  union
3358  {
3359  __IOM uint8_t reg;
3361  struct
3362  {
3363  __IOM uint8_t SUPPFAIL : 1;
3364  __IM uint8_t : 1;
3365  __IOM uint8_t VDDEXTSHORT : 1;
3366  } bit;
3367  } WAKE_STS_FAIL;
3368  __IM uint8_t RESERVED13[3];
3369 
3370  union
3371  {
3372  __IOM uint8_t reg;
3374  struct
3375  {
3376  __IM uint8_t WAKE_STS : 1;
3377  } bit;
3378  } WAKE_STS_MON;
3379  __IM uint8_t RESERVED14[3];
3380 
3381  union
3382  {
3383  __IOM uint8_t reg;
3385  struct
3386  {
3387  __IM uint8_t GPIO0_STS_0 : 1;
3388  __IM uint8_t GPIO0_STS_1 : 1;
3389  __IM uint8_t GPIO0_STS_2 : 1;
3390  __IM uint8_t GPIO0_STS_3 : 1;
3391  __IM uint8_t GPIO0_STS_4 : 1;
3392  } bit;
3393  } WAKE_STS_GPIO0;
3394  __IM uint8_t RESERVED15[3];
3395 
3396  union
3397  {
3398  __IOM uint8_t reg;
3400  struct
3401  {
3402  __IM uint8_t GPIO1_STS_0 : 1;
3403  __IM uint8_t GPIO1_STS_1 : 1;
3404  __IM uint8_t GPIO1_STS_2 : 1;
3405  __IM uint8_t GPIO1_STS_3 : 1;
3406  __IM uint8_t GPIO1_STS_4 : 1;
3407  } bit;
3408  } WAKE_STS_GPIO1;
3409  __IM uint8_t RESERVED16[31];
3410 
3411  union
3412  {
3413  __IOM uint8_t reg;
3415  struct
3416  {
3417  __IOM uint8_t CNF_LIN_FT : 1;
3418  __IOM uint8_t CNF_MON_FT : 1;
3419  __IOM uint8_t CNF_GPIO_FT : 2;
3420  } bit;
3421  } CNF_WAKE_FILTER;
3422  __IM uint8_t RESERVED17[19];
3423 
3424  union
3425  {
3426  __IOM uint8_t reg;
3428  struct
3429  {
3430  __IOM uint8_t DATA0 : 8;
3431  } bit;
3432  } GPUDATA00;
3433  __IM uint8_t RESERVED18[3];
3434 
3435  union
3436  {
3437  __IOM uint8_t reg;
3439  struct
3440  {
3441  __IOM uint8_t DATA1 : 8;
3442  } bit;
3443  } GPUDATA01;
3444  __IM uint8_t RESERVED19[3];
3445 
3446  union
3447  {
3448  __IOM uint8_t reg;
3450  struct
3451  {
3452  __IOM uint8_t DATA2 : 8;
3453  } bit;
3454  } GPUDATA02;
3455  __IM uint8_t RESERVED20[3];
3456 
3457  union
3458  {
3459  __IOM uint8_t reg;
3461  struct
3462  {
3463  __IOM uint8_t DATA3 : 8;
3464  } bit;
3465  } GPUDATA03;
3466  __IM uint8_t RESERVED21[3];
3467 
3468  union
3469  {
3470  __IOM uint8_t reg;
3472  struct
3473  {
3474  __IOM uint8_t DATA4 : 8;
3475  } bit;
3476  } GPUDATA04;
3477  __IM uint8_t RESERVED22[3];
3478 
3479  union
3480  {
3481  __IOM uint8_t reg;
3483  struct
3484  {
3485  __IOM uint8_t DATA5 : 8;
3486  } bit;
3487  } GPUDATA05;
3488  __IM uint8_t RESERVED23[3];
3489 
3490  union
3491  {
3492  __IOM uint8_t reg;
3494  struct
3495  {
3496  __IOM uint8_t GPIO0_RI_0 : 1;
3497  __IOM uint8_t GPIO0_RI_1 : 1;
3498  __IOM uint8_t GPIO0_RI_2 : 1;
3499  __IOM uint8_t GPIO0_RI_3 : 1;
3500  __IOM uint8_t GPIO0_RI_4 : 1;
3501  } bit;
3502  } WAKE_CONF_GPIO0_RISE;
3503  __IM uint8_t RESERVED24[3];
3504 
3505  union
3506  {
3507  __IOM uint8_t reg;
3509  struct
3510  {
3511  __IOM uint8_t GPIO0_FA_0 : 1;
3512  __IOM uint8_t GPIO0_FA_1 : 1;
3513  __IOM uint8_t GPIO0_FA_2 : 1;
3514  __IOM uint8_t GPIO0_FA_3 : 1;
3515  __IOM uint8_t GPIO0_FA_4 : 1;
3516  } bit;
3517  } WAKE_CONF_GPIO0_FALL;
3518  __IM uint8_t RESERVED25[3];
3519 
3520  union
3521  {
3522  __IOM uint8_t reg;
3524  struct
3525  {
3526  __IOM uint8_t GPIO0_CYC_0 : 1;
3527  __IOM uint8_t GPIO0_CYC_1 : 1;
3528  __IOM uint8_t GPIO0_CYC_2 : 1;
3529  __IOM uint8_t GPIO0_CYC_3 : 1;
3530  __IOM uint8_t GPIO0_CYC_4 : 1;
3531  } bit;
3532  } WAKE_CONF_GPIO0_CYC;
3533  __IM uint8_t RESERVED26[3];
3534 
3535  union
3536  {
3537  __IOM uint8_t reg;
3539  struct
3540  {
3541  __IOM uint8_t GPIO1_RI_0 : 1;
3542  __IOM uint8_t GPIO1_RI_1 : 1;
3543  __IOM uint8_t GPIO1_RI_2 : 1;
3544  __IOM uint8_t GPIO1_RI_3 : 1;
3545  __IOM uint8_t GPIO1_RI_4 : 1;
3546  } bit;
3547  } WAKE_CONF_GPIO1_RISE;
3548  __IM uint8_t RESERVED27[3];
3549 
3550  union
3551  {
3552  __IOM uint8_t reg;
3554  struct
3555  {
3556  __IOM uint8_t GPIO1_FA_0 : 1;
3557  __IOM uint8_t GPIO1_FA_1 : 1;
3558  __IOM uint8_t GPIO1_FA_2 : 1;
3559  __IOM uint8_t GPIO1_FA_3 : 1;
3560  __IOM uint8_t GPIO1_FA_4 : 1;
3561  } bit;
3562  } WAKE_CONF_GPIO1_FALL;
3563  __IM uint8_t RESERVED28[3];
3564 
3565  union
3566  {
3567  __IOM uint8_t reg;
3569  struct
3570  {
3571  __IOM uint8_t GPIO1_CYC_0 : 1;
3572  __IOM uint8_t GPIO1_CYC_1 : 1;
3573  __IOM uint8_t GPIO1_CYC_2 : 1;
3574  __IOM uint8_t GPIO1_CYC_3 : 1;
3575  __IOM uint8_t GPIO1_CYC_4 : 1;
3576  } bit;
3577  } WAKE_CONF_GPIO1_CYC;
3578  __IM uint8_t RESERVED29[487];
3579 
3580  union
3581  {
3582  __IOM uint8_t reg;
3584  struct
3585  {
3586  __IOM uint8_t MBIST_EN : 1;
3588  } bit;
3589  } SystemStartConfig;
3590 } PMU_Type;
3594 /* =========================================================================================================================== */
3595 /* ================ PORT ================ */
3596 /* =========================================================================================================================== */
3597 
3598 
3603 typedef struct
3604 {
3605 
3606  union
3607  {
3608  __IOM uint8_t reg;
3610  struct
3611  {
3612  __IOM uint8_t P0 : 1;
3613  __IOM uint8_t P1 : 1;
3614  __IOM uint8_t P2 : 1;
3615  __IOM uint8_t P3 : 1;
3616  __IOM uint8_t P4 : 1;
3617  } bit;
3618  } P0_DATA;
3619  __IM uint8_t RESERVED[3];
3620 
3621  union
3622  {
3623  __IOM uint8_t reg;
3625  struct
3626  {
3627  __IOM uint8_t P0 : 1;
3628  __IOM uint8_t P1 : 1;
3629  __IOM uint8_t P2 : 1;
3630  __IOM uint8_t P3 : 1;
3631  __IOM uint8_t P4 : 1;
3632  } bit;
3633  } P0_DIR;
3634  __IM uint8_t RESERVED1[3];
3635 
3636  union
3637  {
3638  __IOM uint8_t reg;
3640  struct
3641  {
3642  __IOM uint8_t P0 : 1;
3643  __IOM uint8_t P1 : 1;
3644  __IOM uint8_t P2 : 1;
3645  __IOM uint8_t P3 : 1;
3646  __IOM uint8_t P4 : 1;
3647  } bit;
3648  } P1_DATA;
3649  __IM uint8_t RESERVED2[3];
3650 
3651  union
3652  {
3653  __IOM uint8_t reg;
3655  struct
3656  {
3657  __IOM uint8_t P0 : 1;
3658  __IOM uint8_t P1 : 1;
3659  __IOM uint8_t P2 : 1;
3660  __IOM uint8_t P3 : 1;
3661  __IOM uint8_t P4 : 1;
3662  } bit;
3663  } P1_DIR;
3664  __IM uint8_t RESERVED3[3];
3665 
3666  union
3667  {
3668  __IOM uint8_t reg;
3670  struct
3671  {
3672  __IM uint8_t P0 : 1;
3674  __IM uint8_t P2 : 1;
3675  __IM uint8_t P3 : 1;
3676  __IM uint8_t P4 : 1;
3677  __IM uint8_t P5 : 1;
3678  } bit;
3679  } P2_DATA;
3680  __IM uint8_t RESERVED4[3];
3681 
3682  union
3683  {
3684  __IOM uint8_t reg;
3686  struct
3687  {
3688  __IOM uint8_t P0 : 1;
3689  __IM uint8_t : 1;
3690  __IOM uint8_t P2 : 1;
3691  __IOM uint8_t P3 : 1;
3692  __IOM uint8_t P4 : 1;
3693  __IOM uint8_t P5 : 1;
3694  } bit;
3695  } P2_DIR;
3696  __IM uint8_t RESERVED5[3];
3697 
3698  union
3699  {
3700  __IOM uint8_t reg;
3702  struct
3703  {
3704  __IOM uint8_t P0 : 1;
3705  __IOM uint8_t P1 : 1;
3706  __IOM uint8_t P2 : 1;
3707  __IOM uint8_t P3 : 1;
3708  __IOM uint8_t P4 : 1;
3709  } bit;
3710  } P0_PUDSEL;
3711  __IM uint8_t RESERVED6[3];
3712 
3713  union
3714  {
3715  __IOM uint8_t reg;
3717  struct
3718  {
3719  __IOM uint8_t P0 : 1;
3720  __IOM uint8_t P1 : 1;
3721  __IOM uint8_t P2 : 1;
3722  __IOM uint8_t P3 : 1;
3723  __IOM uint8_t P4 : 1;
3724  } bit;
3725  } P0_PUDEN;
3726  __IM uint8_t RESERVED7[3];
3727 
3728  union
3729  {
3730  __IOM uint8_t reg;
3732  struct
3733  {
3734  __IOM uint8_t P0 : 1;
3735  __IOM uint8_t P1 : 1;
3736  __IOM uint8_t P2 : 1;
3737  __IOM uint8_t P3 : 1;
3738  __IOM uint8_t P4 : 1;
3739  } bit;
3740  } P1_PUDSEL;
3741  __IM uint8_t RESERVED8[3];
3742 
3743  union
3744  {
3745  __IOM uint8_t reg;
3747  struct
3748  {
3749  __IOM uint8_t P0 : 1;
3750  __IOM uint8_t P1 : 1;
3751  __IOM uint8_t P2 : 1;
3752  __IOM uint8_t P3 : 1;
3753  __IOM uint8_t P4 : 1;
3754  } bit;
3755  } P1_PUDEN;
3756  __IM uint8_t RESERVED9[3];
3757 
3758  union
3759  {
3760  __IOM uint8_t reg;
3762  struct
3763  {
3764  __IOM uint8_t P0 : 1;
3765  __IM uint8_t : 1;
3766  __IOM uint8_t P2 : 1;
3767  __IOM uint8_t P3 : 1;
3768  __IOM uint8_t P4 : 1;
3769  __IOM uint8_t P5 : 1;
3770  } bit;
3771  } P2_PUDSEL;
3772  __IM uint8_t RESERVED10[3];
3773 
3774  union
3775  {
3776  __IOM uint8_t reg;
3778  struct
3779  {
3780  __IOM uint8_t P0 : 1;
3781  __IM uint8_t : 1;
3782  __IOM uint8_t P2 : 1;
3783  __IOM uint8_t P3 : 1;
3784  __IOM uint8_t P4 : 1;
3785  __IOM uint8_t P5 : 1;
3786  } bit;
3787  } P2_PUDEN;
3788  __IM uint8_t RESERVED11[3];
3789 
3790  union
3791  {
3792  __IOM uint8_t reg;
3794  struct
3795  {
3796  __IOM uint8_t P0 : 1;
3797  __IOM uint8_t P1 : 1;
3798  __IOM uint8_t P2 : 1;
3799  __IOM uint8_t P3 : 1;
3800  __IOM uint8_t P4 : 1;
3801  } bit;
3802  } P0_ALTSEL0;
3803  __IM uint8_t RESERVED12[3];
3804 
3805  union
3806  {
3807  __IOM uint8_t reg;
3809  struct
3810  {
3811  __IOM uint8_t P0 : 1;
3812  __IOM uint8_t P1 : 1;
3813  __IOM uint8_t P2 : 1;
3814  __IOM uint8_t P3 : 1;
3815  __IOM uint8_t P4 : 1;
3816  } bit;
3817  } P0_ALTSEL1;
3818  __IM uint8_t RESERVED13[3];
3819 
3820  union
3821  {
3822  __IOM uint8_t reg;
3824  struct
3825  {
3826  __IOM uint8_t P0 : 1;
3827  __IOM uint8_t P1 : 1;
3828  __IOM uint8_t P2 : 1;
3829  __IOM uint8_t P3 : 1;
3830  __IOM uint8_t P4 : 1;
3831  } bit;
3832  } P1_ALTSEL0;
3833  __IM uint8_t RESERVED14[3];
3834 
3835  union
3836  {
3837  __IOM uint8_t reg;
3839  struct
3840  {
3841  __IOM uint8_t P0 : 1;
3842  __IOM uint8_t P1 : 1;
3843  __IOM uint8_t P2 : 1;
3844  __IOM uint8_t P3 : 1;
3845  __IOM uint8_t P4 : 1;
3846  } bit;
3847  } P1_ALTSEL1;
3848  __IM uint8_t RESERVED15[3];
3849 
3850  union
3851  {
3852  __IOM uint8_t reg;
3854  struct
3855  {
3856  __IOM uint8_t P0 : 1;
3857  __IOM uint8_t P1 : 1;
3858  __IOM uint8_t P2 : 1;
3859  __IOM uint8_t P3 : 1;
3860  __IOM uint8_t P4 : 1;
3861  } bit;
3862  } P0_OD;
3863  __IM uint8_t RESERVED16[3];
3864 
3865  union
3866  {
3867  __IOM uint8_t reg;
3869  struct
3870  {
3871  __IM uint8_t : 1;
3872  __IOM uint8_t P0 : 1;
3873  __IOM uint8_t P1 : 1;
3874  __IOM uint8_t P3_P2 : 1;
3875  __IOM uint8_t P4 : 1;
3876  } bit;
3877  } P1_OD;
3878 } PORT_Type;
3882 /* =========================================================================================================================== */
3883 /* ================ SCU ================ */
3884 /* =========================================================================================================================== */
3885 
3886 
3891 typedef struct
3892 {
3893 
3894  union
3895  {
3896  __IOM uint8_t reg;
3898  struct
3899  {
3900  __OM uint8_t NMIWDTC : 1;
3901  __OM uint8_t NMIPLLC : 1;
3902  __OM uint8_t NMINVMC : 1;
3903  __OM uint8_t NMIOTC : 1;
3904  __OM uint8_t NMIOWDC : 1;
3905  __OM uint8_t NMIMAPC : 1;
3906  __OM uint8_t NMIECCC : 1;
3907  __OM uint8_t NMISUPC : 1;
3908  } bit;
3909  } NMICLR;
3910  __IM uint8_t RESERVED[3];
3911 
3912  union
3913  {
3914  __IOM uint8_t reg;
3916  struct
3917  {
3918  __IM uint8_t EXINT0R : 1;
3919  __IM uint8_t EXINT0F : 1;
3920  __IM uint8_t EXINT1R : 1;
3921  __IM uint8_t EXINT1F : 1;
3922  __IM uint8_t EXINT2R : 1;
3923  __IM uint8_t EXINT2F : 1;
3924  __IM uint8_t MONR : 1;
3925  __IM uint8_t MONF : 1;
3927  } bit;
3928  } IRCON0;
3929  __IM uint8_t RESERVED1[3];
3930 
3931  union
3932  {
3933  __IOM uint8_t reg;
3935  struct
3936  {
3937  __IM uint8_t EIR : 1;
3938  __IM uint8_t TIR : 1;
3939  __IM uint8_t RIR : 1;
3940  } bit;
3941  } IRCON1;
3942  __IM uint8_t RESERVED2[3];
3943 
3944  union
3945  {
3946  __IOM uint8_t reg;
3948  struct
3949  {
3950  __IM uint8_t EIR : 1;
3951  __IM uint8_t TIR : 1;
3952  __IM uint8_t RIR : 1;
3953  } bit;
3954  } IRCON2;
3955  __IM uint8_t RESERVED3[3];
3956 
3957  union
3958  {
3959  __IOM uint8_t reg;
3961  struct
3962  {
3963  __IM uint8_t CCU6SR0 : 1;
3965  __IM uint8_t CCU6SR1 : 1;
3966  } bit;
3967  } IRCON3;
3968  __IM uint8_t RESERVED4[3];
3969 
3970  union
3971  {
3972  __IOM uint8_t reg;
3974  struct
3975  {
3976  __IM uint8_t CCU6SR2 : 1;
3977  __IM uint8_t : 3;
3978  __IM uint8_t CCU6SR3 : 1;
3979  } bit;
3980  } IRCON4;
3981  __IM uint8_t RESERVED5[3];
3982 
3983  union
3984  {
3985  __IOM uint8_t reg;
3987  struct
3988  {
3989  __IM uint8_t FNMIWDT : 1;
3990  __IM uint8_t FNMIPLL : 1;
3991  __IM uint8_t FNMINVM : 1;
3992  __IM uint8_t FNMIOT : 1;
3993  __IM uint8_t FNMIOWD : 1;
3994  __IM uint8_t FNMIMAP : 1;
3995  __IM uint8_t FNMIECC : 1;
3996  __IM uint8_t FNMISUP : 1;
3997  } bit;
3998  } NMISR;
3999  __IM uint8_t RESERVED6[3];
4000 
4001  union
4002  {
4003  __IOM uint8_t reg;
4005  struct
4006  {
4007  __IM uint8_t : 7;
4008  __IOM uint8_t EA : 1;
4009  } bit;
4010  } IEN0;
4011  __IM uint8_t RESERVED7[7];
4012 
4013  union
4014  {
4015  __IOM uint8_t reg;
4017  struct
4018  {
4019  __IOM uint8_t NMIWDT : 1;
4020  __IOM uint8_t NMIPLL : 1;
4021  __IOM uint8_t NMINVM : 1;
4022  __IOM uint8_t NMIOT : 1;
4023  __IOM uint8_t NMIOWD : 1;
4024  __IOM uint8_t NMIMAP : 1;
4025  __IOM uint8_t NMIECC : 1;
4026  __IOM uint8_t NMISUP : 1;
4027  } bit;
4028  } NMICON;
4029  __IM uint8_t RESERVED8[3];
4030 
4031  union
4032  {
4033  __IOM uint8_t reg;
4035  struct
4036  {
4037  __IOM uint8_t EXINT0 : 2;
4038  __IOM uint8_t EXINT1 : 2;
4039  __IOM uint8_t EXINT2 : 2;
4040  __IOM uint8_t MON_Trig_Sel : 2;
4041  } bit;
4042  } EXICON0;
4043  __IM uint8_t RESERVED9[3];
4044 
4045  union
4046  {
4047  __IOM uint8_t reg;
4049  struct
4050  {
4051  __OM uint8_t EXINT0RC : 1;
4053  __OM uint8_t EXINT0FC : 1;
4055  __OM uint8_t EXINT1RC : 1;
4057  __OM uint8_t EXINT1FC : 1;
4059  __OM uint8_t EXINT2RC : 1;
4061  __OM uint8_t EXINT2FC : 1;
4063  __OM uint8_t MONRC : 1;
4065  __OM uint8_t MONFC : 1;
4067  } bit;
4068  } IRCON0CLR;
4069  __IM uint8_t RESERVED10[3];
4070 
4071  union
4072  {
4073  __IOM uint8_t reg;
4075  struct
4076  {
4077  __IOM uint8_t EIREN1 : 1;
4078  __IOM uint8_t TIREN1 : 1;
4079  __IOM uint8_t RIREN1 : 1;
4080  __IM uint8_t : 3;
4081  __IOM uint8_t RIEN1 : 1;
4082  __IOM uint8_t TIEN1 : 1;
4083  } bit;
4084  } MODIEN1;
4085  __IM uint8_t RESERVED11[3];
4086 
4087  union
4088  {
4089  __IOM uint8_t reg;
4091  struct
4092  {
4093  __IOM uint8_t EIREN2 : 1;
4094  __IOM uint8_t TIREN2 : 1;
4095  __IOM uint8_t RIREN2 : 1;
4096  __IM uint8_t : 2;
4097  __IOM uint8_t EXINT2_EN : 1;
4098  __IOM uint8_t RIEN2 : 1;
4099  __IOM uint8_t TIEN2 : 1;
4100  } bit;
4101  } MODIEN2;
4102  __IM uint8_t RESERVED12[3];
4103 
4104  union
4105  {
4106  __IOM uint8_t reg;
4108  struct
4109  {
4110  __IOM uint8_t IE0 : 1;
4111  __IM uint8_t : 3;
4112  __IOM uint8_t MONIE : 1;
4113  __IM uint8_t MONSTS : 1;
4114  } bit;
4115  } MODIEN3;
4116  __IM uint8_t RESERVED13[3];
4117 
4118  union
4119  {
4120  __IOM uint8_t reg;
4122  struct
4123  {
4124  __IOM uint8_t IE1 : 1;
4125  } bit;
4126  } MODIEN4;
4127  __IM uint8_t RESERVED14[3];
4128 
4129  union
4130  {
4131  __IOM uint8_t reg;
4133  struct
4134  {
4135  __IOM uint8_t XTAL_ON : 1;
4136  __IOM uint8_t SL : 1;
4137  __IOM uint8_t PD : 1;
4138  __IOM uint8_t SD : 1;
4139  } bit;
4140  } PMCON0;
4141  __IM uint8_t RESERVED15[3];
4142 
4143  union
4144  {
4145  __IOM uint8_t reg;
4147  struct
4148  {
4149  __IM uint8_t LOCK : 1;
4150  __IOM uint8_t RESLD : 1;
4151  __IOM uint8_t OSCDISC : 1;
4152  __IOM uint8_t VCOBYP : 1;
4153  __IOM uint8_t NDIV : 4;
4154  } bit;
4155  } PLL_CON;
4156  __IM uint8_t RESERVED16[3];
4157 
4158  union
4159  {
4160  __IOM uint8_t reg;
4162  struct
4163  {
4164  __IOM uint8_t CLKREL : 4;
4165  __IOM uint8_t K2DIV : 2;
4166  __IOM uint8_t K1DIV : 1;
4167  __IOM uint8_t VCOSEL : 1;
4168  } bit;
4169  } CMCON1;
4170  __IM uint8_t RESERVED17[3];
4171 
4172  union
4173  {
4174  __IOM uint8_t reg;
4176  struct
4177  {
4178  __IOM uint8_t PBA0CLKREL : 1;
4179  } bit;
4180  } CMCON2;
4181  __IM uint8_t RESERVED18[3];
4182 
4183  union
4184  {
4185  __IOM uint8_t reg;
4187  struct
4188  {
4189  __IOM uint8_t WDTIN : 1;
4190  __IOM uint8_t WDTRS : 1;
4191  __IOM uint8_t WDTEN : 1;
4192  __IM uint8_t : 1;
4193  __IM uint8_t WDTPR : 1;
4194  __IOM uint8_t WINBEN : 1;
4195  } bit;
4196  } WDTCON;
4197  __IM uint8_t RESERVED19[3];
4198 
4199  union
4200  {
4201  __IOM uint8_t reg;
4203  struct
4204  {
4205  __IM uint8_t PLL_LOCK : 1;
4206  __IOM uint8_t APCLK_SET : 1;
4207  __IOM uint8_t T3CLK_SEL : 1;
4208  __IOM uint8_t CLKWDT_IE : 1;
4209  __IOM uint8_t BGCLK_SEL : 1;
4210  __IOM uint8_t BGCLK_DIV : 1;
4211  __IOM uint8_t CPCLK_SEL : 1;
4212  __IOM uint8_t CPCLK_DIV : 1;
4213  } bit;
4214  } APCLK_CTRL1;
4215  __IM uint8_t RESERVED20[3];
4216 
4217  union
4218  {
4219  __IOM uint8_t reg;
4221  struct
4222  {
4223  __IOM uint8_t APCLK1FAC : 2;
4224  __IOM uint8_t APCLK1SCLR : 1;
4225  __IM uint8_t : 1;
4226  __IM uint8_t APCLK1STS : 2;
4227  __IM uint8_t APCLK3STS : 1;
4228  __IOM uint8_t APCLK3SCLR : 1;
4229  } bit;
4230  } APCLK1;
4231  __IM uint8_t RESERVED21[3];
4232 
4233  union
4234  {
4235  __IOM uint8_t reg;
4237  struct
4238  {
4239  __IOM uint8_t APCLK2FAC : 5;
4240  __IM uint8_t APCLK2STS : 2;
4241  __IOM uint8_t APCLK2SCLR : 1;
4242  } bit;
4243  } APCLK2;
4244  __IM uint8_t RESERVED22[3];
4245 
4246  union
4247  {
4248  __IOM uint8_t reg;
4250  struct
4251  {
4252  __IOM uint8_t ADC1_DIS : 1;
4253  __IOM uint8_t SSC1_DIS : 1;
4254  __IOM uint8_t CCU6_DIS : 1;
4255  __IOM uint8_t T2_DIS : 1;
4256  __IOM uint8_t GPT12_DIS : 1;
4257  } bit;
4258  } PMCON1;
4259  __IM uint8_t RESERVED23[3];
4260 
4261  union
4262  {
4263  __IOM uint8_t reg;
4265  struct
4266  {
4267  __IM uint8_t : 1;
4268  __IOM uint8_t SSC2_DIS : 1;
4269  __IM uint8_t : 1;
4270  __IOM uint8_t T21_DIS : 1;
4271  __IM uint8_t : 1;
4272  __IOM uint8_t T3_DIS : 1;
4273  } bit;
4274  } PMCON2;
4275  __IM uint8_t RESERVED24[3];
4276 
4277  union
4278  {
4279  __IOM uint8_t reg;
4281  struct
4282  {
4283  __IOM uint8_t LOCKUP : 1;
4284  __IM uint8_t : 6;
4285  __IOM uint8_t LOCKUP_EN : 1;
4286  } bit;
4287  } RSTCON;
4288  __IM uint8_t RESERVED25[3];
4289 
4290  union
4291  {
4292  __IOM uint8_t reg;
4294  struct
4295  {
4296  __IOM uint8_t SDADCCLK_DIV : 2;
4297  __IOM uint8_t T3CLK_DIV : 2;
4298  } bit;
4299  } APCLK_CTRL2;
4300  __IM uint8_t RESERVED26[3];
4301 
4302  union
4303  {
4304  __IOM uint8_t reg;
4306  struct
4307  {
4308  __IM uint8_t : 4;
4309  __IOM uint8_t NVMCLKFAC : 2;
4310  __IOM uint8_t SYSCLKSEL : 2;
4311  } bit;
4312  } SYSCON0;
4313  __IM uint8_t RESERVED27[3];
4314 
4315  union
4316  {
4317  __IOM uint8_t reg;
4319  struct
4320  {
4321  __IOM uint8_t INIT_FAIL : 1;
4322  __IOM uint8_t MRAMINITSTS : 1;
4323  __IOM uint8_t PG100TP_CHKS_ERR : 1;
4324  } bit;
4325  } SYS_STRTUP_STS;
4326  __IM uint8_t RESERVED28[3];
4327 
4328  union
4329  {
4330  __IOM uint8_t reg;
4332  struct
4333  {
4334  __IOM uint8_t WDTREL : 8;
4335  } bit;
4336  } WDTREL;
4337  __IM uint8_t RESERVED29[3];
4338 
4339  union
4340  {
4341  __IOM uint8_t reg;
4343  struct
4344  {
4345  __IOM uint8_t WDTWINB : 8;
4346  } bit;
4347  } WDTWINB;
4348  __IM uint8_t RESERVED30[3];
4349 
4350  union
4351  {
4352  __IOM uint8_t reg;
4354  struct
4355  {
4356  __IM uint8_t WDT : 8;
4357  } bit;
4358  } WDTL;
4359  __IM uint8_t RESERVED31[3];
4360 
4361  union
4362  {
4363  __IOM uint8_t reg;
4365  struct
4366  {
4367  __IM uint8_t WDT : 8;
4368  } bit;
4369  } WDTH;
4370  __IM uint8_t RESERVED32[3];
4371 
4372  union
4373  {
4374  __IOM uint8_t reg;
4376  struct
4377  {
4378  __IOM uint8_t R : 1;
4379  __IOM uint8_t BRPRE : 3;
4380  } bit;
4381  } BCON1;
4382  __IM uint8_t RESERVED33[3];
4383 
4384  union
4385  {
4386  __IOM uint8_t reg;
4389  struct
4390  {
4391  __IOM uint8_t FD_SEL : 5;
4392  __IOM uint8_t BR_VALUE : 3;
4393  } bit;
4394  } BGL1;
4395  __IM uint8_t RESERVED34[3];
4396 
4397  union
4398  {
4399  __IOM uint8_t reg;
4401  struct
4402  {
4403  __IOM uint8_t BR_VALUE : 8;
4404  } bit;
4405  } BGH1;
4406  __IM uint8_t RESERVED35[3];
4407 
4408  union
4409  {
4410  __IOM uint8_t reg;
4412  struct
4413  {
4414  __IOM uint8_t BRDIS : 1;
4415  __IOM uint8_t BGSEL : 2;
4416  __IM uint8_t BRK : 1;
4417  __IM uint8_t EOFSYN : 1;
4418  __IM uint8_t ERRSYN : 1;
4419  __IOM uint8_t SYNEN : 1;
4420  } bit;
4421  } LINST;
4422  __IM uint8_t RESERVED36[3];
4423 
4424  union
4425  {
4426  __IOM uint8_t reg;
4428  struct
4429  {
4430  __IOM uint8_t R : 1;
4431  __IOM uint8_t BRPRE : 3;
4432  } bit;
4433  } BCON2;
4434  __IM uint8_t RESERVED37[3];
4435 
4436  union
4437  {
4438  __IOM uint8_t reg;
4441  struct
4442  {
4443  __IOM uint8_t FD_SEL : 5;
4444  __IOM uint8_t BR_VALUE : 3;
4445  } bit;
4446  } BGL2;
4447  __IM uint8_t RESERVED38[3];
4448 
4449  union
4450  {
4451  __IOM uint8_t reg;
4453  struct
4454  {
4455  __IOM uint8_t BR_VALUE : 8;
4456  } bit;
4457  } BGH2;
4458  __IM uint8_t RESERVED39[3];
4459 
4460  union
4461  {
4462  __IOM uint8_t reg;
4464  struct
4465  {
4466  __IM uint8_t : 3;
4467  __OM uint8_t BRKC : 1;
4468  __OM uint8_t EOFSYNC : 1;
4469  __OM uint8_t ERRSYNC : 1;
4470  } bit;
4471  } LINSCLR;
4472  __IM uint8_t RESERVED40[3];
4473 
4474  union
4475  {
4476  __IOM uint8_t reg;
4478  struct
4479  {
4480  __IM uint8_t VERID : 3;
4481  __IM uint8_t PRODID : 5;
4482  } bit;
4483  } ID;
4484  __IM uint8_t RESERVED41[3];
4485 
4486  union
4487  {
4488  __IOM uint8_t reg;
4490  struct
4491  {
4492  __IOM uint8_t MODE : 2;
4493  __IM uint8_t PROTECT_S : 1;
4494  __IOM uint8_t PASS : 5;
4495  } bit;
4496  } PASSWD;
4497  __IM uint8_t RESERVED42[3];
4498 
4499  union
4500  {
4501  __IOM uint8_t reg;
4503  struct
4504  {
4505  __IOM uint8_t OSCSS : 2;
4506  __IOM uint8_t OSCWDTRST : 1;
4507  __IM uint8_t OSC2L : 1;
4508  __IOM uint8_t XPD : 1;
4509  __IM uint8_t : 2;
4510  __IOM uint8_t OSCTRIM_8 : 1;
4511  } bit;
4512  } OSC_CON;
4513  __IM uint8_t RESERVED43[3];
4514 
4515  union
4516  {
4517  __IOM uint8_t reg;
4519  struct
4520  {
4521  __IOM uint8_t COREL : 4;
4522  __IOM uint8_t COUTS0 : 1;
4523  __IOM uint8_t TLEN : 1;
4524  __IOM uint8_t COUTS1 : 1;
4525  __IOM uint8_t EN : 1;
4526  } bit;
4527  } COCON;
4528  __IM uint8_t RESERVED44[3];
4529 
4530  union
4531  {
4532  __IOM uint8_t reg;
4534  struct
4535  {
4536  __IOM uint8_t EXINT0IS : 2;
4537  __IOM uint8_t EXINT1IS : 2;
4538  __IOM uint8_t EXINT2IS : 2;
4539  __IOM uint8_t URIOS1 : 1;
4540  __IOM uint8_t U_TX_CONDIS : 1;
4541  } bit;
4542  } MODPISEL;
4543  __IM uint8_t RESERVED45[3];
4544 
4545  union
4546  {
4547  __IOM uint8_t reg;
4549  struct
4550  {
4551  __IOM uint8_t GPT12CAPINB : 1;
4552  __IM uint8_t : 5;
4553  __IOM uint8_t T2EXCON : 1;
4554  __IOM uint8_t T21EXCON : 1;
4555  } bit;
4556  } MODPISEL1;
4557  __IM uint8_t RESERVED46[3];
4558 
4559  union
4560  {
4561  __IOM uint8_t reg;
4563  struct
4564  {
4565  __IOM uint8_t T2IS : 2;
4566  __IOM uint8_t T21IS : 2;
4567  __IOM uint8_t T2EXIS : 2;
4568  __IOM uint8_t T21EXIS : 2;
4569  } bit;
4570  } MODPISEL2;
4571  __IM uint8_t RESERVED47[3];
4572 
4573  union
4574  {
4575  __IOM uint8_t reg;
4577  struct
4578  {
4579  __IM uint8_t : 6;
4580  __IOM uint8_t URIOS2 : 1;
4581  } bit;
4582  } MODPISEL3;
4583  __IM uint8_t RESERVED48[3];
4584 
4585  union
4586  {
4587  __IOM uint8_t reg;
4589  struct
4590  {
4591  __IOM uint8_t WDTSUSP : 1;
4592  __IOM uint8_t T12SUSP : 1;
4593  __IOM uint8_t T13SUSP : 1;
4594  __IOM uint8_t T2_SUSP : 1;
4595  __IOM uint8_t GPT12_SUSP : 1;
4596  __IM uint8_t : 1;
4597  __IOM uint8_t T21_SUSP : 1;
4598  } bit;
4599  } MODSUSP1;
4600  __IM uint8_t RESERVED49[3];
4601 
4602  union
4603  {
4604  __IOM uint8_t reg;
4606  struct
4607  {
4608  __IOM uint8_t T3_SUSP : 1;
4609  __IOM uint8_t MU_SUSP : 1;
4610  __IOM uint8_t ADC1_SUSP : 1;
4611  } bit;
4612  } MODSUSP2;
4613  __IM uint8_t RESERVED50[3];
4614 
4615  union
4616  {
4617  __IOM uint8_t reg;
4619  struct
4620  {
4621  __IOM uint8_t GPT12 : 4;
4622  __IOM uint8_t TRIG_CONF : 1;
4623  __IOM uint8_t T3_GPT12_SEL : 1;
4624  } bit;
4625  } GPT12PISEL;
4626  __IM uint8_t RESERVED51[3];
4627 
4628  union
4629  {
4630  __IOM uint8_t reg;
4633  struct
4634  {
4635  __IOM uint8_t RIE : 1;
4636  __IM uint8_t : 1;
4637  __IOM uint8_t NVMIE : 1;
4638  } bit;
4639  } EDCCON;
4640  __IM uint8_t RESERVED52[3];
4641 
4642  union
4643  {
4644  __IOM uint8_t reg;
4647  struct
4648  {
4649  __IM uint8_t RDBE : 1;
4650  __IM uint8_t : 1;
4651  __IM uint8_t NVMDBE : 1;
4652  __IM uint8_t : 1;
4653  __IM uint8_t RSBE : 1;
4654  } bit;
4655  } EDCSTAT;
4656  __IM uint8_t RESERVED53[3];
4657 
4658  union
4659  {
4660  __IOM uint8_t reg;
4662  struct
4663  {
4664  __IOM uint8_t SECTORINFO : 6;
4665  __IOM uint8_t SASTATUS : 2;
4666  } bit;
4667  } MEMSTAT;
4668  __IM uint8_t RESERVED54[3];
4669 
4670  union
4671  {
4672  __IOM uint8_t reg;
4674  struct
4675  {
4676  __IOM uint8_t NVMPROTSTSL_0 : 1;
4677  __IOM uint8_t NVMPROTSTSL_1 : 1;
4678  __IOM uint8_t NVMPROTSTSL_2 : 1;
4679  __IOM uint8_t NVMPROTSTSL_3 : 1;
4680  } bit;
4681  } NVM_PROT_STS;
4682  __IM uint8_t RESERVED55[3];
4683 
4684  union
4685  {
4686  __IOM uint8_t reg;
4688  struct
4689  {
4690  __IM uint8_t NVM_PROT_ERR : 1;
4691  __IM uint8_t NVM_ADDR_ERR : 1;
4692  __IM uint8_t NVM_SFR_PROT_ERR : 1;
4693  __IM uint8_t NVM_SFR_ADDR_ERR : 1;
4694  __IM uint8_t ROM_PROT_ERR : 1;
4695  __IM uint8_t ROM_ADDR_ERR : 1;
4696  __IM uint8_t RAM_PROT_ERR : 1;
4697  } bit;
4698  } MEM_ACC_STS;
4699  __IM uint8_t RESERVED56[3];
4700 
4701  union
4702  {
4703  __IOM uint8_t reg;
4705  struct
4706  {
4707  __IOM uint8_t PDM0 : 3;
4708  __IM uint8_t : 1;
4709  __IOM uint8_t PDM1 : 3;
4710  } bit;
4711  } P0_POCON0;
4712  __IM uint8_t RESERVED57[3];
4713 
4714  union
4715  {
4716  __IOM uint8_t reg;
4718  struct
4719  {
4720  __IOM uint8_t PDM2 : 3;
4721  __IM uint8_t : 1;
4722  __IOM uint8_t PDM3 : 3;
4723  } bit;
4724  } P0_POCON1;
4725  __IM uint8_t RESERVED58[3];
4726 
4727  union
4728  {
4729  __IOM uint8_t reg;
4731  struct
4732  {
4733  __IOM uint8_t PDM4 : 3;
4734  } bit;
4735  } P0_POCON2;
4736  __IM uint8_t RESERVED59[3];
4737 
4738  union
4739  {
4740  __IOM uint8_t reg;
4742  struct
4743  {
4744  __IOM uint8_t TCC : 2;
4745  } bit;
4746  } TCCR;
4747  __IM uint8_t RESERVED60[3];
4748 
4749  union
4750  {
4751  __IOM uint8_t reg;
4753  struct
4754  {
4755  __IOM uint8_t PDM0 : 3;
4756  __IM uint8_t : 1;
4757  __IOM uint8_t PDM1 : 3;
4758  } bit;
4759  } P1_POCON0;
4760  __IM uint8_t RESERVED61[3];
4761 
4762  union
4763  {
4764  __IOM uint8_t reg;
4766  struct
4767  {
4768  __IOM uint8_t PDM2 : 3;
4769  __IM uint8_t : 1;
4770  __IOM uint8_t PDM3 : 3;
4771  } bit;
4772  } P1_POCON1;
4773  __IM uint8_t RESERVED62[3];
4774 
4775  union
4776  {
4777  __IOM uint8_t reg;
4779  struct
4780  {
4781  __IOM uint8_t PDM4 : 3;
4782  } bit;
4783  } P1_POCON2;
4784  __IM uint8_t RESERVED63[11];
4785 
4786  union
4787  {
4788  __IOM uint8_t reg;
4791  struct
4792  {
4793  __OM uint8_t RDBEC : 1;
4794  __IM uint8_t : 1;
4795  __OM uint8_t NVMDBEC : 1;
4796  __IM uint8_t : 1;
4797  __OM uint8_t RSBEC : 1;
4798  } bit;
4799  } EDCSCLR;
4800  __IM uint8_t RESERVED64[55];
4801 
4802  union
4803  {
4804  __IOM uint8_t reg;
4806  struct
4807  {
4808  __IOM uint8_t CH1IE : 1;
4809  __IOM uint8_t CH2IE : 1;
4810  __IOM uint8_t CH3IE : 1;
4811  __IOM uint8_t CH4IE : 1;
4812  __IOM uint8_t CH5IE : 1;
4813  __IOM uint8_t CH6IE : 1;
4814  __IOM uint8_t CH7IE : 1;
4815  __IOM uint8_t CH8IE : 1;
4816  } bit;
4817  } DMAIEN1;
4818  __IM uint8_t RESERVED65[3];
4819 
4820  union
4821  {
4822  __IOM uint8_t reg;
4824  struct
4825  {
4826  __IOM uint8_t TRERRIE : 1;
4827  __IOM uint8_t TRSEQ1RDYIE : 1;
4828  __IOM uint8_t TRSEQ2RDYIE : 1;
4829  __IOM uint8_t SSCTXIE : 1;
4830  __IOM uint8_t SSCRXIE : 1;
4831  __IOM uint8_t GPT12IE : 1;
4832  __IOM uint8_t SDADCIE : 1;
4833  } bit;
4834  } DMAIEN2;
4835  __IM uint8_t RESERVED66[3];
4836 
4837  union
4838  {
4839  __IOM uint8_t reg;
4841  struct
4842  {
4843  __IOM uint8_t SSCTXSRCSEL : 1;
4844  __IOM uint8_t SSCRXSRCSEL : 1;
4845  __IOM uint8_t T12ZM_DMAEN : 1;
4846  __IOM uint8_t T12PM_DMAEN : 1;
4847  __IM uint8_t : 1;
4848  __IM uint8_t SSCTX : 1;
4849  __IM uint8_t SSCRX : 1;
4850  __IM uint8_t GPT12_T3 : 1;
4851  } bit;
4852  } DMASRCSEL;
4853  __IM uint8_t RESERVED67[7];
4854 
4855  union
4856  {
4857  __IOM uint8_t reg;
4859  struct
4860  {
4861  __IM uint8_t CH1 : 1;
4862  __IM uint8_t CH2 : 1;
4863  __IM uint8_t CH3 : 1;
4864  __IM uint8_t CH4 : 1;
4865  __IM uint8_t CH5 : 1;
4866  __IM uint8_t CH6 : 1;
4867  __IM uint8_t CH7 : 1;
4868  __IM uint8_t CH8 : 1;
4869  } bit;
4870  } DMAIRC1;
4871  __IM uint8_t RESERVED68[3];
4872 
4873  union
4874  {
4875  __IOM uint8_t reg;
4877  struct
4878  {
4879  __IM uint8_t STRDY : 1;
4880  __IM uint8_t TRSEQ1DY : 1;
4881  __IM uint8_t TRSEQ2DY : 1;
4882  __IM uint8_t SSC1RDY : 1;
4883  __IM uint8_t SSC2RDY : 1;
4884  __IM uint8_t GPT12 : 1;
4885  __IM uint8_t SDADC : 1;
4886  } bit;
4887  } DMAIRC2;
4888  __IM uint8_t RESERVED69[3];
4889 
4890  union
4891  {
4892  __IOM uint8_t reg;
4895  struct
4896  {
4897  __IOM uint8_t T2IE : 1;
4898  __IOM uint8_t T3IE : 1;
4899  __IOM uint8_t T4IE : 1;
4900  __IOM uint8_t T5IE : 1;
4901  __IOM uint8_t T6IE : 1;
4902  __IOM uint8_t CRIE : 1;
4904  } bit;
4905  } GPT12IEN;
4906  __IM uint8_t RESERVED70[3];
4907 
4908  union
4909  {
4910  __IOM uint8_t reg;
4912  struct
4913  {
4914  __IM uint8_t T2 : 1;
4915  __IM uint8_t T3 : 1;
4916  __IM uint8_t T4 : 1;
4917  __IM uint8_t T5 : 1;
4918  __IM uint8_t T6 : 1;
4919  __IM uint8_t CR : 1;
4920  } bit;
4921  } GPT12IRC;
4922  __IM uint8_t RESERVED71[3];
4923 
4924  union
4925  {
4926  __IOM uint8_t reg;
4929  struct
4930  {
4931  __OM uint8_t T2C : 1;
4932  __OM uint8_t T3C : 1;
4933  __OM uint8_t T4C : 1;
4934  __OM uint8_t T5C : 1;
4935  __OM uint8_t T6C : 1;
4936  __OM uint8_t CRC : 1;
4937  } bit;
4938  } GPT12ICLR;
4939  __IM uint8_t RESERVED72[19];
4940 
4941  union
4942  {
4943  __IOM uint8_t reg;
4945  struct
4946  {
4947  __OM uint8_t EIRC : 1;
4948  __OM uint8_t TIRC : 1;
4949  __OM uint8_t RIRC : 1;
4950  } bit;
4951  } IRCON1CLR;
4952  __IM uint8_t RESERVED73[3];
4953 
4954  union
4955  {
4956  __IOM uint8_t reg;
4958  struct
4959  {
4960  __OM uint8_t EIRC : 1;
4961  __OM uint8_t TIRC : 1;
4962  __OM uint8_t RIRC : 1;
4963  } bit;
4964  } IRCON2CLR;
4965  __IM uint8_t RESERVED74[3];
4966 
4967  union
4968  {
4969  __IOM uint8_t reg;
4971  struct
4972  {
4973  __IOM uint8_t GPT12_DMAEN : 2;
4974  } bit;
4975  } DMASRCSEL2;
4976  __IM uint8_t RESERVED75[3];
4977 
4978  union
4979  {
4980  __IOM uint8_t reg;
4982  struct
4983  {
4984  __OM uint8_t CH1C : 1;
4985  __OM uint8_t CH2C : 1;
4986  __OM uint8_t CH3C : 1;
4987  __OM uint8_t CH4C : 1;
4988  __OM uint8_t CH5C : 1;
4989  __OM uint8_t CH6C : 1;
4990  __OM uint8_t CH7C : 1;
4991  __OM uint8_t CH8C : 1;
4992  } bit;
4993  } DMAIRC1CLR;
4994  __IM uint8_t RESERVED76[3];
4995 
4996  union
4997  {
4998  __IOM uint8_t reg;
5000  struct
5001  {
5002  __IM uint8_t : 1;
5003  __OM uint8_t TRSEQ1DYC : 1;
5004  __OM uint8_t TRSEQ2DYC : 1;
5005  __OM uint8_t SSC1C : 1;
5006  __OM uint8_t SSC2C : 1;
5007  __OM uint8_t GPT12C : 1;
5008  __OM uint8_t SDADCC : 1;
5009  } bit;
5010  } DMAIRC2CLR;
5011  __IM uint8_t RESERVED77[7];
5012 
5013  union
5014  {
5015  __IOM uint8_t reg;
5017  struct
5018  {
5019  __OM uint8_t CCU6SR0C : 1;
5020  __IM uint8_t : 3;
5021  __OM uint8_t CCU6SR1C : 1;
5022  } bit;
5023  } IRCON3CLR;
5024  __IM uint8_t RESERVED78[3];
5025 
5026  union
5027  {
5028  __IOM uint8_t reg;
5030  struct
5031  {
5032  __OM uint8_t CCU6SR2C : 1;
5033  __IM uint8_t : 3;
5034  __OM uint8_t CCU6SR3C : 1;
5035  } bit;
5036  } IRCON4CLR;
5037  __IM uint8_t RESERVED79[3];
5038 
5039  union
5040  {
5041  __IOM uint8_t reg;
5043  struct
5044  {
5045  __IM uint8_t : 5;
5046  __OM uint8_t SSCTXC : 1;
5047  __OM uint8_t SSCRXC : 1;
5048  __OM uint8_t GPT12_T3C : 1;
5049  } bit;
5050  } DMASRCCLR;
5051 } SCU_Type;
5055 /* =========================================================================================================================== */
5056 /* ================ SCUPM ================ */
5057 /* =========================================================================================================================== */
5058 
5059 
5064 typedef struct
5065 {
5066 
5067  union
5068  {
5069  __IOM uint32_t reg;
5071  struct
5072  {
5073  __IM uint32_t AMCLK1_FREQ : 6;
5076  __IM uint32_t AMCLK2_FREQ : 6;
5077  } bit;
5078  } AMCLK_FREQ_STS;
5079 
5080  union
5081  {
5082  __IOM uint32_t reg;
5084  struct
5085  {
5086  __IOM uint32_t CLKWDT_PD_N : 1;
5087  } bit;
5088  } AMCLK_CTRL;
5089  __IM uint32_t RESERVED;
5090 
5091  union
5092  {
5093  __IOM uint32_t reg;
5095  struct
5096  {
5097  __IOM uint32_t AMCLK1_UP_TH : 6;
5098  __IOM uint32_t AMCLK1_UP_HYS : 2;
5099  __IOM uint32_t AMCLK1_LOW_TH : 6;
5100  __IOM uint32_t AMCLK1_LOW_HYS : 2;
5101  __IOM uint32_t AMCLK2_UP_TH : 6;
5102  __IOM uint32_t AMCLK2_UP_HYS : 2;
5103  __IOM uint32_t AMCLK2_LOW_TH : 6;
5104  __IOM uint32_t AMCLK2_LOW_HYS : 2;
5105  } bit;
5106  } AMCLK_TH_HYS;
5107  __IM uint32_t RESERVED1;
5108 
5109  union
5110  {
5111  __IOM uint32_t reg;
5113  struct
5114  {
5115  __OM uint32_t LIN_OC_ICLR : 1;
5116  __OM uint32_t LIN_OT_ICLR : 1;
5117  __OM uint32_t LIN_TMOUT_ICLR : 1;
5118  __IM uint32_t : 3;
5119  __OM uint32_t PMU_OTWARN_ICLR : 1;
5121  __OM uint32_t PMU_OT_ICLR : 1;
5123  __OM uint32_t SYS_OTWARN_ICLR : 1;
5125  __OM uint32_t SYS_OT_ICLR : 1;
5127  __OM uint32_t REFBG_LOTHWARN_ICLR : 1;
5129  __OM uint32_t REFBG_UPTHWARN_ICLR : 1;
5131  __OM uint32_t VREF5V_LOWTH_ICLR : 1;
5133  __OM uint32_t VREF5V_UPTH_ICLR : 1;
5135  __OM uint32_t VREF5V_OVL_ICLR : 1;
5136  __OM uint32_t ADC2_ESM_ICLR : 1;
5137  __OM uint32_t PHU_ZCLOW_ICLR : 1;
5138  __OM uint32_t PHU_ZCHI_ICLR : 1;
5139  __OM uint32_t PHV_ZCLOW_ICLR : 1;
5140  __OM uint32_t PHV_ZCHI_ICLR : 1;
5141  __OM uint32_t PHW_ZCLOW_ICLR : 1;
5142  __OM uint32_t PHW_ZCHI_ICLR : 1;
5143  __OM uint32_t ADC3_EOC_ICLR : 1;
5144  __OM uint32_t ADC4_EOC_ICLR : 1;
5145  __OM uint32_t PHU_ZCLOW_SCLR : 1;
5146  __OM uint32_t PHU_ZCHI_SCLR : 1;
5147  __OM uint32_t PHV_ZCLOW_SCLR : 1;
5148  __OM uint32_t PHV_ZCHI_SCLR : 1;
5149  __OM uint32_t PHW_ZCLOW_SCLR : 1;
5150  __OM uint32_t PHW_ZCHI_SCLR : 1;
5151  } bit;
5152  } SYS_ISCLR;
5153 
5154  union
5155  {
5156  __IOM uint32_t reg;
5158  struct
5159  {
5160  __IM uint32_t LIN_OC_IS : 1;
5161  __IM uint32_t LIN_OT_IS : 1;
5162  __IM uint32_t LIN_TMOUT_IS : 1;
5163  __IM uint32_t : 3;
5164  __IM uint32_t PMU_OTWARN_IS : 1;
5166  __IM uint32_t PMU_OT_IS : 1;
5168  __IM uint32_t SYS_OTWARN_IS : 1;
5170  __IM uint32_t SYS_OT_IS : 1;
5172  __IM uint32_t REFBG_LOTHWARN_IS : 1;
5174  __IM uint32_t REFBG_UPTHWARN_IS : 1;
5176  __IM uint32_t VREF5V_LOWTH_IS : 1;
5178  __IM uint32_t VREF5V_UPTH_IS : 1;
5180  __IM uint32_t VREF5V_OVL_IS : 1;
5181  __IM uint32_t ADC2_ESM_IS : 1;
5182  __IM uint32_t PHU_ZCLOW_IS : 1;
5183  __IM uint32_t PHU_ZCHI_IS : 1;
5184  __IM uint32_t PHV_ZCLOW_IS : 1;
5185  __IM uint32_t PHV_ZCHI_IS : 1;
5186  __IM uint32_t PHW_ZCLOW_IS : 1;
5187  __IM uint32_t PHW_ZCHI_IS : 1;
5188  __IM uint32_t ADC3_EOC_IS : 1;
5189  __IM uint32_t ADC4_EOC_IS : 1;
5190  __IM uint32_t PHU_ZCLOW_STS : 1;
5191  __IM uint32_t PHU_ZCHI_STS : 1;
5192  __IM uint32_t PHV_ZCLOW_STS : 1;
5193  __IM uint32_t PHV_ZCHI_STS : 1;
5194  __IM uint32_t PHW_ZCLOW_STS : 1;
5195  __IM uint32_t PHW_ZCHI_STS : 1;
5196  } bit;
5197  } SYS_IS;
5198 
5199  union
5200  {
5201  __IOM uint32_t reg;
5203  struct
5204  {
5205  __IM uint32_t MON_UV_IS : 1;
5206  __IM uint32_t VS_UV_IS : 1;
5207  __IM uint32_t VDD5V_UV_IS : 1;
5208  __IM uint32_t VDD1V5_UV_IS : 1;
5209  __IM uint32_t MON_OV_IS : 1;
5210  __IM uint32_t VS_OV_IS : 1;
5211  __IM uint32_t VDD5V_OV_IS : 1;
5212  __IM uint32_t VDD1V5_OV_IS : 1;
5213  __IM uint32_t : 8;
5214  __IM uint32_t MON_UV_STS : 1;
5215  __IM uint32_t VS_UV_STS : 1;
5216  __IM uint32_t VDD5V_UV_STS : 1;
5217  __IM uint32_t VDD1V5_UV_STS : 1;
5218  __IM uint32_t MON_OV_STS : 1;
5219  __IM uint32_t VS_OV_STS : 1;
5220  __IM uint32_t VDD5V_OV_STS : 1;
5221  __IM uint32_t VDD1V5_OV_STS : 1;
5222  } bit;
5223  } SYS_SUPPLY_IRQ_STS;
5224 
5225  union
5226  {
5227  __IOM uint32_t reg;
5229  struct
5230  {
5231  __IOM uint32_t MON_UV_IE : 1;
5232  __IOM uint32_t VS_UV_IE : 1;
5233  __IOM uint32_t VDD5V_UV_IE : 1;
5234  __IOM uint32_t VDD1V5_UV_IE : 1;
5235  __IOM uint32_t MON_OV_IE : 1;
5236  __IOM uint32_t VS_OV_IE : 1;
5237  __IOM uint32_t VDD5V_OV_IE : 1;
5238  __IOM uint32_t VDD1V5_OV_IE : 1;
5239  } bit;
5240  } SYS_SUPPLY_IRQ_CTRL;
5241 
5242  union
5243  {
5244  __IOM uint32_t reg;
5246  struct
5247  {
5248  __OM uint32_t MON_UV_ICLR : 1;
5249  __OM uint32_t VS_UV_ICLR : 1;
5250  __OM uint32_t VDD5V_UV_ICLR : 1;
5251  __OM uint32_t VDD1V5_UV_ICLR : 1;
5252  __OM uint32_t MON_OV_ICLR : 1;
5253  __OM uint32_t VS_OV_ICLR : 1;
5254  __OM uint32_t VDD5V_OV_ICLR : 1;
5255  __OM uint32_t VDD1V5_OV_ICLR : 1;
5256  __IM uint32_t : 8;
5257  __OM uint32_t MON_UV_SCLR : 1;
5258  __OM uint32_t VS_UV_SCLR : 1;
5259  __OM uint32_t VDD5V_UV_SCLR : 1;
5260  __OM uint32_t VDD1V5_UV_SCLR : 1;
5261  __OM uint32_t MON_OV_SCLR : 1;
5262  __OM uint32_t VS_OV_SCLR : 1;
5263  __OM uint32_t VDD5V_OV_SCLR : 1;
5264  __OM uint32_t VDD1V5_OV_SCLR : 1;
5265  } bit;
5266  } SYS_SUPPLY_IRQ_CLR;
5267 
5268  union
5269  {
5270  __IOM uint32_t reg;
5272  struct
5273  {
5274  __IOM uint32_t LIN_OC_IE : 1;
5275  __IOM uint32_t LIN_OT_IE : 1;
5276  __IOM uint32_t LIN_TMOUT_IE : 1;
5277  __IM uint32_t : 3;
5278  __IOM uint32_t PMU_OTWARN_IE : 1;
5279  __IOM uint32_t PMU_OT_IE : 1;
5281  __IOM uint32_t SYS_OTWARN_IE : 1;
5282  __IOM uint32_t SYS_OT_IE : 1;
5284  __IOM uint32_t REFBG_LOTHWARN_IE : 1;
5285  __IOM uint32_t REFBG_UPTHWARN_IE : 1;
5286  __IOM uint32_t VREF5V_LOWTH_IE : 1;
5288  __IOM uint32_t VREF5V_UPTH_IE : 1;
5290  __IOM uint32_t VREF5V_OVL_IE : 1;
5291  __IOM uint32_t ADC2_ESM_IE : 1;
5292  __IOM uint32_t PHU_ZCLOW_IE : 1;
5293  __IOM uint32_t PHU_ZCHI_IE : 1;
5294  __IOM uint32_t PHV_ZCLOW_IE : 1;
5295  __IOM uint32_t PHV_ZCHI_IE : 1;
5296  __IOM uint32_t PHW_ZCLOW_IE : 1;
5297  __IOM uint32_t PHW_ZCHI_IE : 1;
5298  __IOM uint32_t ADC3_EOC_IE : 1;
5299  __IOM uint32_t ADC4_EOC_IE : 1;
5300  } bit;
5301  } SYS_IRQ_CTRL;
5302  __IM uint32_t RESERVED2;
5303 
5304  union
5305  {
5306  __IOM uint32_t reg;
5308  struct
5309  {
5310  __IM uint32_t : 1;
5311  __IOM uint32_t CLKWDT_SD_DIS : 1;
5312  __IM uint32_t : 5;
5313  __IOM uint32_t FAIL_PS_DIS : 1;
5314  __IOM uint32_t LIN_VS_UV_SD_DIS : 1;
5315  __IM uint32_t : 5;
5316  __IOM uint32_t SYS_VSD_OV_SLM_DIS : 1;
5317  __IM uint32_t : 9;
5318  __IOM uint32_t SYS_OT_PS_DIS : 1;
5319  __IOM uint32_t CLKLOSS_SD_DIS : 1;
5320  __IOM uint32_t CLKWDT_RES_SD_DIS : 1;
5321  } bit;
5322  } PCU_CTRL_STS;
5323 
5324  union
5325  {
5326  __IOM uint32_t reg;
5328  struct
5329  {
5330  __IOM uint32_t WDP_SEL : 6;
5331  __IOM uint32_t SOWCONF : 2;
5332  } bit;
5333  } WDT1_TRIG;
5334  __IM uint32_t RESERVED3[7];
5335 
5336  union
5337  {
5338  __IOM uint32_t reg;
5340  struct
5341  {
5342  __OM uint32_t LS1_DS_ICLR : 1;
5343  __OM uint32_t LS2_DS_ICLR : 1;
5344  __OM uint32_t HS1_DS_ICLR : 1;
5346  __OM uint32_t HS2_DS_ICLR : 1;
5348  __OM uint32_t LS3_DS_ICLR : 1;
5349  __OM uint32_t HS3_DS_ICLR : 1;
5351  __IM uint32_t : 4;
5352  __OM uint32_t LS1_OC_ICLR : 1;
5353  __OM uint32_t LS2_OC_ICLR : 1;
5354  __OM uint32_t HS1_OC_ICLR : 1;
5355  __OM uint32_t HS2_OC_ICLR : 1;
5356  __OM uint32_t LS3_OC_ICLR : 1;
5357  __OM uint32_t HS3_OC_ICLR : 1;
5358  __OM uint32_t VCP_LOWTH2_ICLR : 1;
5360  __OM uint32_t VCP_LOWTH1_ICLR : 1;
5362  __OM uint32_t VCP_UPTH_ICLR : 1;
5364  __OM uint32_t VSD_LOWTH_ICLR : 1;
5366  __OM uint32_t VSD_UPTH_ICLR : 1;
5368  __IM uint32_t : 3;
5369  __OM uint32_t VCP_LOWTH2_SCLR : 1;
5371  __OM uint32_t VCP_LOWTH1_SCLR : 1;
5373  __OM uint32_t VCP_UPTH_SCLR : 1;
5375  __OM uint32_t VSD_LOWTH_SCLR : 1;
5377  __OM uint32_t VSD_UPTH_SCLR : 1;
5380  } bit;
5381  } BDRV_ISCLR;
5382 
5383  union
5384  {
5385  __IOM uint32_t reg;
5387  struct
5388  {
5389  __IM uint32_t LS1_DS_IS : 1;
5390  __IM uint32_t LS2_DS_IS : 1;
5391  __IM uint32_t HS1_DS_IS : 1;
5393  __IM uint32_t HS2_DS_IS : 1;
5395  __IM uint32_t LS3_DS_IS : 1;
5396  __IM uint32_t HS3_DS_IS : 1;
5398  __IM uint32_t : 4;
5399  __IM uint32_t LS1_OC_IS : 1;
5400  __IM uint32_t LS2_OC_IS : 1;
5401  __IM uint32_t HS1_OC_IS : 1;
5402  __IM uint32_t HS2_OC_IS : 1;
5403  __IM uint32_t LS3_OC_IS : 1;
5404  __IM uint32_t HS3_OC_IS : 1;
5405  __IM uint32_t VCP_LOWTH2_IS : 1;
5407  __IM uint32_t VCP_LOWTH1_IS : 1;
5409  __IM uint32_t VCP_UPTH_IS : 1;
5411  __IM uint32_t VSD_LOWTH_IS : 1;
5413  __IM uint32_t VSD_UPTH_IS : 1;
5415  __IM uint32_t : 3;
5416  __IM uint32_t VCP_LOWTH2_STS : 1;
5418  __IM uint32_t VCP_LOWTH1_STS : 1;
5420  __IM uint32_t VCP_UPTH_STS : 1;
5422  __IM uint32_t VSD_LOWTH_STS : 1;
5424  __IM uint32_t VSD_UPTH_STS : 1;
5427  } bit;
5428  } BDRV_IS;
5429 
5430  union
5431  {
5432  __IOM uint32_t reg;
5434  struct
5435  {
5436  __IOM uint32_t LS1_DS_IE : 1;
5437  __IOM uint32_t LS2_DS_IE : 1;
5438  __IOM uint32_t HS1_DS_IE : 1;
5440  __IOM uint32_t HS2_DS_IE : 1;
5442  __IOM uint32_t LS3_DS_IE : 1;
5443  __IOM uint32_t HS3_DS_IE : 1;
5445  __IM uint32_t : 4;
5446  __IOM uint32_t LS1_OC_IE : 1;
5447  __IOM uint32_t LS2_OC_IE : 1;
5448  __IOM uint32_t HS1_OC_IE : 1;
5449  __IOM uint32_t HS2_OC_IE : 1;
5450  __IOM uint32_t LS3_OC_IE : 1;
5451  __IOM uint32_t HS3_OC_IE : 1;
5452  __IOM uint32_t VCP_LOWTH2_IE : 1;
5453  __IOM uint32_t VCP_LOWTH1_IE : 1;
5454  __IOM uint32_t VCP_UPTH_IE : 1;
5455  __IOM uint32_t VSD_LOWTH_IE : 1;
5456  __IOM uint32_t VSD_UPTH_IE : 1;
5457  } bit;
5458  } BDRV_IRQ_CTRL;
5459  __IM uint32_t RESERVED4[3];
5460 
5461  union
5462  {
5463  __IOM uint32_t reg;
5465  struct
5466  {
5467  __IOM uint32_t STCALIB : 26;
5468  } bit;
5469  } STCALIB;
5470  __IM uint32_t RESERVED5[4];
5471 
5472  union
5473  {
5474  __IOM uint32_t reg;
5476  struct
5477  {
5478  __IM uint32_t DBFSTS : 1;
5479  __IM uint32_t SBFSTS : 1;
5480  } bit;
5481  } BFSTS;
5482 
5483  union
5484  {
5485  __IOM uint32_t reg;
5487  struct
5488  {
5489  __IM uint32_t DBFA : 32;
5490  } bit;
5491  } DBFA;
5492 
5493  union
5494  {
5495  __IOM uint32_t reg;
5497  struct
5498  {
5499  __IM uint32_t SBFA : 32;
5500  } bit;
5501  } SBFA;
5502 
5503  union
5504  {
5505  __IOM uint32_t reg;
5507  struct
5508  {
5509  __OM uint32_t DBFSTSCLR : 1;
5510  __OM uint32_t SBFSTSCLR : 1;
5511  } bit;
5512  } BFSTS_CLR;
5513 } SCUPM_Type;
5517 /* =========================================================================================================================== */
5518 /* ================ SSC1 ================ */
5519 /* =========================================================================================================================== */
5520 
5521 
5526 typedef struct
5527 {
5528 
5529  union
5530  {
5531  __IOM uint16_t reg;
5533  struct
5534  {
5535  __IOM uint16_t MIS_0 : 1;
5539  __IOM uint16_t SIS : 1;
5544  __IOM uint16_t CIS : 1;
5549  __IOM uint16_t MIS_1 : 1;
5551  } bit;
5552  } PISEL;
5553  __IM uint16_t RESERVED;
5554 
5555  union
5556  {
5557  __IOM uint16_t reg;
5559  struct
5560  {
5561  __IM uint16_t BC : 4;
5563  __IM uint16_t TE : 1;
5564  __IM uint16_t RE : 1;
5565  __IM uint16_t PE : 1;
5566  __IM uint16_t BE : 1;
5567  __IM uint16_t BSY : 1;
5568  __IM uint16_t : 1;
5569  __IOM uint16_t MS : 1;
5570  __IOM uint16_t EN : 1;
5571  } bit;
5572  } CON;
5573  __IM uint16_t RESERVED1;
5574 
5575  union
5576  {
5577  __IOM uint16_t reg;
5579  struct
5580  {
5581  __IOM uint16_t TB_VALUE : 16;
5582  } bit;
5583  } TB;
5584  __IM uint16_t RESERVED2;
5585 
5586  union
5587  {
5588  __IOM uint16_t reg;
5590  struct
5591  {
5592  __IM uint16_t RB_VALUE : 16;
5593  } bit;
5594  } RB;
5595  __IM uint16_t RESERVED3;
5596 
5597  union
5598  {
5599  __IOM uint16_t reg;
5601  struct
5602  {
5603  __IOM uint16_t BR_VALUE : 16;
5604  } bit;
5605  } BR;
5606  __IM uint16_t RESERVED4;
5607 
5608  union
5609  {
5610  __IOM uint16_t reg;
5612  struct
5613  {
5614  __IM uint16_t : 8;
5615  __OM uint16_t TECLR : 1;
5616  __OM uint16_t RECLR : 1;
5617  __OM uint16_t PECLR : 1;
5618  __OM uint16_t BECLR : 1;
5619  } bit;
5620  } ISRCLR;
5621 } SSC1_Type;
5625 /* =========================================================================================================================== */
5626 /* ================ SSC2 ================ */
5627 /* =========================================================================================================================== */
5628 
5629 
5634 typedef struct
5635 {
5636 
5637  union
5638  {
5639  __IOM uint16_t reg;
5641  struct
5642  {
5643  __IOM uint16_t MIS_0 : 1;
5647  __IOM uint16_t SIS : 1;
5652  __IOM uint16_t CIS : 1;
5657  __IOM uint16_t MIS_1 : 1;
5659  } bit;
5660  } PISEL;
5661  __IM uint16_t RESERVED;
5662 
5663  union
5664  {
5665  __IOM uint16_t reg;
5667  struct
5668  {
5669  __IM uint16_t BC : 4;
5671  __IM uint16_t TE : 1;
5672  __IM uint16_t RE : 1;
5673  __IM uint16_t PE : 1;
5674  __IM uint16_t BE : 1;
5675  __IM uint16_t BSY : 1;
5676  __IM uint16_t : 1;
5677  __IOM uint16_t MS : 1;
5678  __IOM uint16_t EN : 1;
5679  } bit;
5680  } CON;
5681  __IM uint16_t RESERVED1;
5682 
5683  union
5684  {
5685  __IOM uint16_t reg;
5687  struct
5688  {
5689  __IOM uint16_t TB_VALUE : 16;
5690  } bit;
5691  } TB;
5692  __IM uint16_t RESERVED2;
5693 
5694  union
5695  {
5696  __IOM uint16_t reg;
5698  struct
5699  {
5700  __IM uint16_t RB_VALUE : 16;
5701  } bit;
5702  } RB;
5703  __IM uint16_t RESERVED3;
5704 
5705  union
5706  {
5707  __IOM uint16_t reg;
5709  struct
5710  {
5711  __IOM uint16_t BR_VALUE : 16;
5712  } bit;
5713  } BR;
5714  __IM uint16_t RESERVED4;
5715 
5716  union
5717  {
5718  __IOM uint16_t reg;
5720  struct
5721  {
5722  __IM uint16_t : 8;
5723  __OM uint16_t TECLR : 1;
5724  __OM uint16_t RECLR : 1;
5725  __OM uint16_t PECLR : 1;
5726  __OM uint16_t BECLR : 1;
5727  } bit;
5728  } ISRCLR;
5729 } SSC2_Type;
5733 /* =========================================================================================================================== */
5734 /* ================ TIMER2x ================ */
5735 /* =========================================================================================================================== */
5736 
5737 
5742 typedef struct
5743 {
5744 
5745  union
5746  {
5747  __IOM uint8_t reg;
5749  struct
5750  {
5751  __IOM uint8_t CP_RL2 : 1;
5752  __IOM uint8_t C_T2 : 1;
5753  __IOM uint8_t TR2 : 1;
5754  __IOM uint8_t EXEN2 : 1;
5756  __IM uint8_t EXF2 : 1;
5757  __IM uint8_t TF2 : 1;
5758  } bit;
5759  } T2CON;
5760  __IM uint8_t RESERVED[3];
5761 
5762  union
5763  {
5764  __IOM uint8_t reg;
5766  struct
5767  {
5768  __IOM uint8_t DCEN : 1;
5769  __IOM uint8_t T2PRE : 3;
5770  __IOM uint8_t PREN : 1;
5771  __IOM uint8_t EDGESEL : 1;
5772  __IOM uint8_t T2RHEN : 1;
5773  __IOM uint8_t T2REGS : 1;
5774  } bit;
5775  } T2MOD;
5776  __IM uint8_t RESERVED1[3];
5777 
5778  union
5779  {
5780  __IOM uint8_t reg;
5782  struct
5783  {
5784  __IOM uint8_t RC2 : 8;
5785  } bit;
5786  } RC2L;
5787  __IM uint8_t RESERVED2[3];
5788 
5789  union
5790  {
5791  __IOM uint8_t reg;
5793  struct
5794  {
5795  __IOM uint8_t RC2 : 8;
5796  } bit;
5797  } RC2H;
5798  __IM uint8_t RESERVED3[3];
5799 
5800  union
5801  {
5802  __IOM uint8_t reg;
5804  struct
5805  {
5806  __IOM uint8_t T2L : 8;
5807  } bit;
5808  } T2L;
5809  __IM uint8_t RESERVED4[3];
5810 
5811  union
5812  {
5813  __IOM uint8_t reg;
5815  struct
5816  {
5817  __IOM uint8_t T2H : 8;
5818  } bit;
5819  } T2H;
5820  __IM uint8_t RESERVED5[3];
5821 
5822  union
5823  {
5824  __IOM uint8_t reg;
5826  struct
5827  {
5828  __IOM uint8_t EXF2EN : 1;
5829  __IOM uint8_t TF2EN : 1;
5830  } bit;
5831  } T2CON1;
5832  __IM uint8_t RESERVED6[3];
5833 
5834  union
5835  {
5836  __IOM uint8_t reg;
5838  struct
5839  {
5840  __IM uint8_t : 6;
5841  __OM uint8_t EXF2CLR : 1;
5842  __OM uint8_t TF2CLR : 1;
5843  } bit;
5844  } T2ICLR;
5845 } TIMER2x_Type;
5849 /* =========================================================================================================================== */
5850 /* ================ TIMER3 ================ */
5851 /* =========================================================================================================================== */
5852 
5853 
5858 typedef struct
5859 {
5860 
5861  union
5862  {
5863  __IOM uint32_t reg;
5865  struct
5866  {
5867  __IOM uint32_t T3_TRIGG_INP_SEL : 3;
5869  __IOM uint32_t T3_RES_CONF : 2;
5870  __IOM uint32_t RETRIG : 1;
5872  } bit;
5873  } T3_TRIGG_CTRL;
5874 
5875  union
5876  {
5877  __IOM uint32_t reg;
5879  struct
5880  {
5881  __IOM uint32_t LO : 8;
5882  __IOM uint32_t HI : 8;
5883  } bit;
5884  } CMP;
5885 
5886  union
5887  {
5888  __IOM uint32_t reg;
5890  struct
5891  {
5892  __IOM uint32_t LO : 8;
5893  __IOM uint32_t HI : 8;
5894  } bit;
5895  } CNT;
5896 
5897  union
5898  {
5899  __IOM uint32_t reg;
5901  struct
5902  {
5903  __IOM uint32_t T3_PD_N : 1;
5904  __IOM uint32_t T3_RD_REQ : 1;
5905  __IOM uint32_t T3_RD_REQ_CONF : 1;
5906  __IOM uint32_t CNT_RDY : 1;
5907  __IOM uint32_t TR3H : 1;
5908  __IM uint32_t T3H_OVF_STS : 1;
5909  __IOM uint32_t TR3L : 1;
5910  __IM uint32_t T3L_OVF_STS : 1;
5911  __IOM uint32_t T3L_OVF_IE : 1;
5912  __IOM uint32_t T3H_OVF_IE : 1;
5913  } bit;
5914  } CTRL;
5915 
5916  union
5917  {
5918  __IOM uint32_t reg;
5920  struct
5921  {
5922  __IOM uint32_t T3M : 2;
5923  __IM uint32_t : 4;
5924  __IOM uint32_t T3_SUBM : 2;
5925  } bit;
5926  } MODE_CONF;
5927 
5928  union
5929  {
5930  __IOM uint32_t reg;
5932  struct
5933  {
5934  __IM uint32_t : 5;
5935  __OM uint32_t T3H_OVF_ICLR : 1;
5936  __IM uint32_t : 1;
5937  __OM uint32_t T3L_OVF_ICLR : 1;
5938  } bit;
5939  } ISRCLR;
5940 } TIMER3_Type;
5944 /* =========================================================================================================================== */
5945 /* ================ UARTx ================ */
5946 /* =========================================================================================================================== */
5947 
5948 
5953 typedef struct
5954 {
5955 
5956  union
5957  {
5958  __IOM uint8_t reg;
5960  struct
5961  {
5962  __IOM uint8_t RI : 1;
5963  __IOM uint8_t TI : 1;
5964  __IOM uint8_t RB8 : 1;
5965  __IOM uint8_t TB8 : 1;
5966  __IOM uint8_t REN : 1;
5967  __IOM uint8_t SM2 : 1;
5969  __IOM uint8_t SM1 : 1;
5970  __IOM uint8_t SM0 : 1;
5971  } bit;
5972  } SCON;
5973  __IM uint8_t RESERVED[3];
5974 
5975  union
5976  {
5977  __IOM uint8_t reg;
5979  struct
5980  {
5981  __IOM uint8_t VAL : 8;
5982  } bit;
5983  } SBUF;
5984  __IM uint8_t RESERVED1[3];
5985 
5986  union
5987  {
5988  __IOM uint8_t reg;
5990  struct
5991  {
5992  __OM uint8_t RICLR : 1;
5993  __OM uint8_t TICLR : 1;
5994  } bit;
5995  } SCONCLR;
5996 } UART_Type; /* End of group Device_Peripheral_peripherals */
6002 
6003 
6004 /* =========================================================================================================================== */
6005 /* ================ Device Specific Peripheral Address Map ================ */
6006 /* =========================================================================================================================== */
6007 
6008 
6013 #define ADC1_BASE 0x40004000UL
6014 #define ADC2_BASE 0x4801C000UL
6015 #define ADC34_BASE 0x40008000UL
6016 #define BDRV_BASE 0x40034000UL
6017 #define CCU6_BASE 0x4000C000UL
6018 #define CPU_BASE 0xE000E000UL
6019 #define CSA_BASE 0x48018000UL
6020 #define DMA_BASE 0x50014000UL
6021 #define GPT12E_BASE 0x40010000UL
6022 #define LIN_BASE 0x4801E000UL
6023 #define MF_BASE 0x48018000UL
6024 #define MON_BASE 0x50004000UL
6025 #define PMU_BASE 0x50004000UL
6026 #define PORT_BASE 0x48028000UL
6027 #define SCU_BASE 0x50005000UL
6028 #define SCUPM_BASE 0x50006000UL
6029 #define SSC1_BASE 0x48024000UL
6030 #define SSC2_BASE 0x48026000UL
6031 #define TIMER2_BASE 0x48004000UL
6032 #define TIMER21_BASE 0x48005000UL
6033 #define TIMER3_BASE 0x48006000UL
6034 #define UART1_BASE 0x48020000UL
6035 #define UART2_BASE 0x48022000UL
6036  /* End of group Device_Peripheral_peripheralAddr */
6038 
6039 
6040 /* =========================================================================================================================== */
6041 /* ================ Peripheral declaration ================ */
6042 /* =========================================================================================================================== */
6043 
6044 
6048 /* Note 923: cast from unsigned long to pointer [MISRA Rule 45] */
6049 /* disable lint warning 923, to accept the conversion of the */
6050 /* base address into a pointer of the peripheral type. */
6051 /* This is a preferable exception as it generates the fastest */
6052 /* code, compared to other solutions which do not require a */
6053 /* suppressing of this MISRA rule */
6054 
6055 
6056 #ifndef UNIT_TESTING_LV2
6057 #define ADC1 ((ADC1_Type*) ADC1_BASE)
6058 #define ADC2 ((ADC2_Type*) ADC2_BASE)
6059 #define ADC34 ((ADC34_Type*) ADC34_BASE)
6060 #define BDRV ((BDRV_Type*) BDRV_BASE)
6061 #define CCU6 ((CCU6_Type*) CCU6_BASE)
6062 #define CSA ((CSA_Type*) CSA_BASE)
6063 #define CPU ((CPU_Type*) CPU_BASE)
6064 #define DMA ((DMA_Type*) DMA_BASE)
6065 #define GPT12E ((GPT12E_Type*) GPT12E_BASE)
6066 #define LIN ((LIN_Type*) LIN_BASE)
6067 #define MF ((MF_Type*) MF_BASE)
6068 #define MON ((MON_Type*) MON_BASE)
6069 #define PMU ((PMU_Type*) PMU_BASE)
6070 #define PORT ((PORT_Type*) PORT_BASE)
6071 #define SCU ((SCU_Type*) SCU_BASE)
6072 #define SCUPM ((SCUPM_Type*) SCUPM_BASE)
6073 #define SSC1 ((SSC1_Type*) SSC1_BASE)
6074 #define SSC2 ((SSC2_Type*) SSC2_BASE)
6075 #define TIMER2 ((TIMER2x_Type*) TIMER2_BASE)
6076 #define TIMER21 ((TIMER2x_Type*) TIMER21_BASE)
6077 #define TIMER3 ((TIMER3_Type*) TIMER3_BASE)
6078 #define UART1 ((UART_Type*) UART1_BASE)
6079 #define UART2 ((UART_Type*) UART2_BASE)
6080 #else
6081 extern ADC1_Type *ADC1;
6082 extern ADC2_Type *ADC2;
6083 extern ADC34_Type *ADC34;
6084 extern BDRV_Type *BDRV;
6085 extern CCU6_Type *CCU6;
6086 extern CSA_Type *CSA;
6087 extern CPU_Type *CPU;
6088 extern DMA_Type *DMA;
6089 extern GPT12E_Type *GPT12E;
6090 extern LIN_Type *LIN;
6091 extern MF_Type *MF;
6092 extern MON_Type *MON;
6093 extern PMU_Type *PMU;
6094 extern PORT_Type *PORT;
6095 extern SCU_Type *SCU;
6096 extern SCUPM_Type *SCUPM;
6097 extern SSC1_Type *SSC1;
6098 extern SSC2_Type *SSC2;
6099 extern TIMER2x_Type *TIMER2;
6100 extern TIMER2x_Type *TIMER21;
6101 extern TIMER3_Type *TIMER3;
6102 extern UART_Type *UART1;
6103 extern UART_Type *UART2;
6104 #endif /* UNIT_TESTING_LV2 */
6105 
6106 
6107  /* End of group Device_Peripheral_declaration */
6109 
6110 
6111 /* =========================================================================================================================== */
6112 /* ================ Pos/Mask Peripheral Section ================ */
6113 /* =========================================================================================================================== */
6114 
6115 
6121 /* violation: Identifier clash */
6122 /* =========================================================================================================================== */
6123 /* ================ ADC1 ================ */
6124 /* =========================================================================================================================== */
6125 
6126 /* ======================================================== CHx_EIM ======================================================== */
6127 #define ADC1_CHx_EIM_TRIG_SEL_Pos (16UL)
6128 #define ADC1_CHx_EIM_TRIG_SEL_Msk (0x70000UL)
6129 #define ADC1_CHx_EIM_REP_Pos (4UL)
6130 #define ADC1_CHx_EIM_REP_Msk (0x70UL)
6131 #define ADC1_CHx_EIM_CHx_Pos (0UL)
6132 #define ADC1_CHx_EIM_CHx_Msk (0x7UL)
6133 /* ======================================================== CHx_ESM ======================================================== */
6134 #define ADC1_CHx_ESM_TRIG_SEL_Pos (16UL)
6135 #define ADC1_CHx_ESM_TRIG_SEL_Msk (0x70000UL)
6136 #define ADC1_CHx_ESM_ESM_0_Pos (0UL)
6137 #define ADC1_CHx_ESM_ESM_0_Msk (0xffUL)
6138 /* ======================================================= CTRL_STS ======================================================== */
6139 #define ADC1_CTRL_STS_IN_MUX_SEL_Pos (4UL)
6140 #define ADC1_CTRL_STS_IN_MUX_SEL_Msk (0x70UL)
6141 #define ADC1_CTRL_STS_EOC_Pos (3UL)
6142 #define ADC1_CTRL_STS_EOC_Msk (0x8UL)
6143 #define ADC1_CTRL_STS_SOC_Pos (2UL)
6144 #define ADC1_CTRL_STS_SOC_Msk (0x4UL)
6145 #define ADC1_CTRL_STS_PD_N_Pos (0UL)
6146 #define ADC1_CTRL_STS_PD_N_Msk (0x1UL)
6147 /* ========================================================= DWSEL ========================================================= */
6148 #define ADC1_DWSEL_ch7_Pos (7UL)
6149 #define ADC1_DWSEL_ch7_Msk (0x80UL)
6150 #define ADC1_DWSEL_ch6_Pos (6UL)
6151 #define ADC1_DWSEL_ch6_Msk (0x40UL)
6152 #define ADC1_DWSEL_ch5_Pos (5UL)
6153 #define ADC1_DWSEL_ch5_Msk (0x20UL)
6154 #define ADC1_DWSEL_ch4_Pos (4UL)
6155 #define ADC1_DWSEL_ch4_Msk (0x10UL)
6156 #define ADC1_DWSEL_ch3_Pos (3UL)
6157 #define ADC1_DWSEL_ch3_Msk (0x8UL)
6158 #define ADC1_DWSEL_ch2_Pos (2UL)
6159 #define ADC1_DWSEL_ch2_Msk (0x4UL)
6160 #define ADC1_DWSEL_ch1_Pos (1UL)
6161 #define ADC1_DWSEL_ch1_Msk (0x2UL)
6162 #define ADC1_DWSEL_ch0_Pos (0UL)
6163 #define ADC1_DWSEL_ch0_Msk (0x1UL)
6164 /* ======================================================== GLOBCTR ======================================================== */
6165 #define ADC1_GLOBCTR_ANON_Pos (8UL)
6166 #define ADC1_GLOBCTR_ANON_Msk (0x300UL)
6167 #define ADC1_GLOBCTR_DIVA_Pos (0UL)
6168 #define ADC1_GLOBCTR_DIVA_Msk (0x3fUL)
6169 /* ======================================================== GLOBSTR ======================================================== */
6170 #define ADC1_GLOBSTR_ANON_ST_Pos (8UL)
6171 #define ADC1_GLOBSTR_ANON_ST_Msk (0x300UL)
6172 #define ADC1_GLOBSTR_CHNR_Pos (3UL)
6173 #define ADC1_GLOBSTR_CHNR_Msk (0x38UL)
6174 #define ADC1_GLOBSTR_SAMPLE_Pos (1UL)
6175 #define ADC1_GLOBSTR_SAMPLE_Msk (0x2UL)
6176 #define ADC1_GLOBSTR_BUSY_Pos (0UL)
6177 #define ADC1_GLOBSTR_BUSY_Msk (0x1UL)
6178 /* ========================================================= ICLR ========================================================== */
6179 #define ADC1_ICLR_ESM_ICLR_Pos (9UL)
6180 #define ADC1_ICLR_ESM_ICLR_Msk (0x200UL)
6181 #define ADC1_ICLR_EIM_ICLR_Pos (8UL)
6182 #define ADC1_ICLR_EIM_ICLR_Msk (0x100UL)
6183 #define ADC1_ICLR_CH7_ICLR_Pos (7UL)
6184 #define ADC1_ICLR_CH7_ICLR_Msk (0x80UL)
6185 #define ADC1_ICLR_CH6_ICLR_Pos (6UL)
6186 #define ADC1_ICLR_CH6_ICLR_Msk (0x40UL)
6187 #define ADC1_ICLR_CH5_ICLR_Pos (5UL)
6188 #define ADC1_ICLR_CH5_ICLR_Msk (0x20UL)
6189 #define ADC1_ICLR_CH4_ICLR_Pos (4UL)
6190 #define ADC1_ICLR_CH4_ICLR_Msk (0x10UL)
6191 #define ADC1_ICLR_CH3_ICLR_Pos (3UL)
6192 #define ADC1_ICLR_CH3_ICLR_Msk (0x8UL)
6193 #define ADC1_ICLR_CH2_ICLR_Pos (2UL)
6194 #define ADC1_ICLR_CH2_ICLR_Msk (0x4UL)
6195 #define ADC1_ICLR_CH1_ICLR_Pos (1UL)
6196 #define ADC1_ICLR_CH1_ICLR_Msk (0x2UL)
6197 #define ADC1_ICLR_CH0_ICLR_Pos (0UL)
6198 #define ADC1_ICLR_CH0_ICLR_Msk (0x1UL)
6199 /* ========================================================== IE =========================================================== */
6200 #define ADC1_IE_ESM_IE_Pos (9UL)
6201 #define ADC1_IE_ESM_IE_Msk (0x200UL)
6202 #define ADC1_IE_EIM_IE_Pos (8UL)
6203 #define ADC1_IE_EIM_IE_Msk (0x100UL)
6204 #define ADC1_IE_CH7_IE_Pos (7UL)
6205 #define ADC1_IE_CH7_IE_Msk (0x80UL)
6206 #define ADC1_IE_CH6_IE_Pos (6UL)
6207 #define ADC1_IE_CH6_IE_Msk (0x40UL)
6208 #define ADC1_IE_CH5_IE_Pos (5UL)
6209 #define ADC1_IE_CH5_IE_Msk (0x20UL)
6210 #define ADC1_IE_CH4_IE_Pos (4UL)
6211 #define ADC1_IE_CH4_IE_Msk (0x10UL)
6212 #define ADC1_IE_CH3_IE_Pos (3UL)
6213 #define ADC1_IE_CH3_IE_Msk (0x8UL)
6214 #define ADC1_IE_CH2_IE_Pos (2UL)
6215 #define ADC1_IE_CH2_IE_Msk (0x4UL)
6216 #define ADC1_IE_CH1_IE_Pos (1UL)
6217 #define ADC1_IE_CH1_IE_Msk (0x2UL)
6218 #define ADC1_IE_CH0_IE_Pos (0UL)
6219 #define ADC1_IE_CH0_IE_Msk (0x1UL)
6220 /* ========================================================== IS =========================================================== */
6221 #define ADC1_IS_ESM_STS_Pos (9UL)
6222 #define ADC1_IS_ESM_STS_Msk (0x200UL)
6223 #define ADC1_IS_EIM_STS_Pos (8UL)
6224 #define ADC1_IS_EIM_STS_Msk (0x100UL)
6225 #define ADC1_IS_CH7_STS_Pos (7UL)
6226 #define ADC1_IS_CH7_STS_Msk (0x80UL)
6227 #define ADC1_IS_CH6_STS_Pos (6UL)
6228 #define ADC1_IS_CH6_STS_Msk (0x40UL)
6229 #define ADC1_IS_CH5_STS_Pos (5UL)
6230 #define ADC1_IS_CH5_STS_Msk (0x20UL)
6231 #define ADC1_IS_CH4_STS_Pos (4UL)
6232 #define ADC1_IS_CH4_STS_Msk (0x10UL)
6233 #define ADC1_IS_CH3_STS_Pos (3UL)
6234 #define ADC1_IS_CH3_STS_Msk (0x8UL)
6235 #define ADC1_IS_CH2_STS_Pos (2UL)
6236 #define ADC1_IS_CH2_STS_Msk (0x4UL)
6237 #define ADC1_IS_CH1_STS_Pos (1UL)
6238 #define ADC1_IS_CH1_STS_Msk (0x2UL)
6239 #define ADC1_IS_CH0_STS_Pos (0UL)
6240 #define ADC1_IS_CH0_STS_Msk (0x1UL)
6241 /* ======================================================= RES_OUT0 ======================================================== */
6242 #define ADC1_RES_OUT0_OF0_Pos (18UL)
6243 #define ADC1_RES_OUT0_OF0_Msk (0x40000UL)
6244 #define ADC1_RES_OUT0_VF0_Pos (17UL)
6245 #define ADC1_RES_OUT0_VF0_Msk (0x20000UL)
6246 #define ADC1_RES_OUT0_WFR0_Pos (16UL)
6247 #define ADC1_RES_OUT0_WFR0_Msk (0x10000UL)
6248 #define ADC1_RES_OUT0_OUT_CH0_Pos (0UL)
6249 #define ADC1_RES_OUT0_OUT_CH0_Msk (0xfffUL)
6250 /* ======================================================= RES_OUT1 ======================================================== */
6251 #define ADC1_RES_OUT1_OF1_Pos (18UL)
6252 #define ADC1_RES_OUT1_OF1_Msk (0x40000UL)
6253 #define ADC1_RES_OUT1_VF1_Pos (17UL)
6254 #define ADC1_RES_OUT1_VF1_Msk (0x20000UL)
6255 #define ADC1_RES_OUT1_WFR1_Pos (16UL)
6256 #define ADC1_RES_OUT1_WFR1_Msk (0x10000UL)
6257 #define ADC1_RES_OUT1_OUT_CH1_Pos (0UL)
6258 #define ADC1_RES_OUT1_OUT_CH1_Msk (0xfffUL)
6259 /* ======================================================= RES_OUT2 ======================================================== */
6260 #define ADC1_RES_OUT2_OF2_Pos (18UL)
6261 #define ADC1_RES_OUT2_OF2_Msk (0x40000UL)
6262 #define ADC1_RES_OUT2_VF2_Pos (17UL)
6263 #define ADC1_RES_OUT2_VF2_Msk (0x20000UL)
6264 #define ADC1_RES_OUT2_WFR2_Pos (16UL)
6265 #define ADC1_RES_OUT2_WFR2_Msk (0x10000UL)
6266 #define ADC1_RES_OUT2_OUT_CH2_Pos (0UL)
6267 #define ADC1_RES_OUT2_OUT_CH2_Msk (0xfffUL)
6268 /* ======================================================= RES_OUT3 ======================================================== */
6269 #define ADC1_RES_OUT3_OF3_Pos (18UL)
6270 #define ADC1_RES_OUT3_OF3_Msk (0x40000UL)
6271 #define ADC1_RES_OUT3_VF3_Pos (17UL)
6272 #define ADC1_RES_OUT3_VF3_Msk (0x20000UL)
6273 #define ADC1_RES_OUT3_WFR3_Pos (16UL)
6274 #define ADC1_RES_OUT3_WFR3_Msk (0x10000UL)
6275 #define ADC1_RES_OUT3_OUT_CH3_Pos (0UL)
6276 #define ADC1_RES_OUT3_OUT_CH3_Msk (0xfffUL)
6277 /* ======================================================= RES_OUT4 ======================================================== */
6278 #define ADC1_RES_OUT4_OF4_Pos (18UL)
6279 #define ADC1_RES_OUT4_OF4_Msk (0x40000UL)
6280 #define ADC1_RES_OUT4_VF4_Pos (17UL)
6281 #define ADC1_RES_OUT4_VF4_Msk (0x20000UL)
6282 #define ADC1_RES_OUT4_WFR4_Pos (16UL)
6283 #define ADC1_RES_OUT4_WFR4_Msk (0x10000UL)
6284 #define ADC1_RES_OUT4_OUT_CH4_Pos (0UL)
6285 #define ADC1_RES_OUT4_OUT_CH4_Msk (0xfffUL)
6286 /* ======================================================= RES_OUT5 ======================================================== */
6287 #define ADC1_RES_OUT5_OF5_Pos (18UL)
6288 #define ADC1_RES_OUT5_OF5_Msk (0x40000UL)
6289 #define ADC1_RES_OUT5_VF5_Pos (17UL)
6290 #define ADC1_RES_OUT5_VF5_Msk (0x20000UL)
6291 #define ADC1_RES_OUT5_WFR5_Pos (16UL)
6292 #define ADC1_RES_OUT5_WFR5_Msk (0x10000UL)
6293 #define ADC1_RES_OUT5_OUT_CH5_Pos (0UL)
6294 #define ADC1_RES_OUT5_OUT_CH5_Msk (0xfffUL)
6295 /* ======================================================= RES_OUT6 ======================================================== */
6296 #define ADC1_RES_OUT6_OF6_Pos (18UL)
6297 #define ADC1_RES_OUT6_OF6_Msk (0x40000UL)
6298 #define ADC1_RES_OUT6_VF6_Pos (17UL)
6299 #define ADC1_RES_OUT6_VF6_Msk (0x20000UL)
6300 #define ADC1_RES_OUT6_WFR6_Pos (16UL)
6301 #define ADC1_RES_OUT6_WFR6_Msk (0x10000UL)
6302 #define ADC1_RES_OUT6_OUT_CH6_Pos (0UL)
6303 #define ADC1_RES_OUT6_OUT_CH6_Msk (0xfffUL)
6304 /* ======================================================= RES_OUT7 ======================================================== */
6305 #define ADC1_RES_OUT7_OF7_Pos (18UL)
6306 #define ADC1_RES_OUT7_OF7_Msk (0x40000UL)
6307 #define ADC1_RES_OUT7_VF7_Pos (17UL)
6308 #define ADC1_RES_OUT7_VF7_Msk (0x20000UL)
6309 #define ADC1_RES_OUT7_WFR7_Pos (16UL)
6310 #define ADC1_RES_OUT7_WFR7_Msk (0x10000UL)
6311 #define ADC1_RES_OUT7_OUT_CH7_Pos (0UL)
6312 #define ADC1_RES_OUT7_OUT_CH7_Msk (0xfffUL)
6313 /* ====================================================== RES_OUT_EIM ====================================================== */
6314 #define ADC1_RES_OUT_EIM_OF8_Pos (18UL)
6315 #define ADC1_RES_OUT_EIM_OF8_Msk (0x40000UL)
6316 #define ADC1_RES_OUT_EIM_VF8_Pos (17UL)
6317 #define ADC1_RES_OUT_EIM_VF8_Msk (0x20000UL)
6318 #define ADC1_RES_OUT_EIM_WFR8_Pos (16UL)
6319 #define ADC1_RES_OUT_EIM_WFR8_Msk (0x10000UL)
6320 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos (0UL)
6321 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk (0xfffUL)
6322 /* ========================================================= SQ1_4 ========================================================= */
6323 #define ADC1_SQ1_4_SQ4_Pos (24UL)
6324 #define ADC1_SQ1_4_SQ4_Msk (0xff000000UL)
6325 #define ADC1_SQ1_4_SQ3_Pos (16UL)
6326 #define ADC1_SQ1_4_SQ3_Msk (0xff0000UL)
6327 #define ADC1_SQ1_4_SQ2_Pos (8UL)
6328 #define ADC1_SQ1_4_SQ2_Msk (0xff00UL)
6329 #define ADC1_SQ1_4_SQ1_Pos (0UL)
6330 #define ADC1_SQ1_4_SQ1_Msk (0xffUL)
6331 /* ========================================================= SQ5_8 ========================================================= */
6332 #define ADC1_SQ5_8_SQ8_Pos (24UL)
6333 #define ADC1_SQ5_8_SQ8_Msk (0xff000000UL)
6334 #define ADC1_SQ5_8_SQ7_Pos (16UL)
6335 #define ADC1_SQ5_8_SQ7_Msk (0xff0000UL)
6336 #define ADC1_SQ5_8_SQ6_Pos (8UL)
6337 #define ADC1_SQ5_8_SQ6_Msk (0xff00UL)
6338 #define ADC1_SQ5_8_SQ5_Pos (0UL)
6339 #define ADC1_SQ5_8_SQ5_Msk (0xffUL)
6340 /* ========================================================= SQ_FB ========================================================= */
6341 #define ADC1_SQ_FB_CHx_Pos (16UL)
6342 #define ADC1_SQ_FB_CHx_Msk (0x70000UL)
6343 #define ADC1_SQ_FB_SQx_Pos (11UL)
6344 #define ADC1_SQ_FB_SQx_Msk (0x3800UL)
6345 #define ADC1_SQ_FB_ESM_ACTIVE_Pos (10UL)
6346 #define ADC1_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6347 #define ADC1_SQ_FB_EIM_ACTIVE_Pos (9UL)
6348 #define ADC1_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6349 #define ADC1_SQ_FB_SQ_RUN_Pos (8UL)
6350 #define ADC1_SQ_FB_SQ_RUN_Msk (0x100UL)
6351 /* ======================================================== STC_0_3 ======================================================== */
6352 #define ADC1_STC_0_3_ch3_Pos (24UL)
6353 #define ADC1_STC_0_3_ch3_Msk (0xff000000UL)
6354 #define ADC1_STC_0_3_ch2_Pos (16UL)
6355 #define ADC1_STC_0_3_ch2_Msk (0xff0000UL)
6356 #define ADC1_STC_0_3_ch1_Pos (8UL)
6357 #define ADC1_STC_0_3_ch1_Msk (0xff00UL)
6358 #define ADC1_STC_0_3_ch0_Pos (0UL)
6359 #define ADC1_STC_0_3_ch0_Msk (0xffUL)
6360 /* ======================================================== STC_4_7 ======================================================== */
6361 #define ADC1_STC_4_7_ch7_Pos (24UL)
6362 #define ADC1_STC_4_7_ch7_Msk (0xff000000UL)
6363 #define ADC1_STC_4_7_ch6_Pos (16UL)
6364 #define ADC1_STC_4_7_ch6_Msk (0xff0000UL)
6365 #define ADC1_STC_4_7_ch5_Pos (8UL)
6366 #define ADC1_STC_4_7_ch5_Msk (0xff00UL)
6367 #define ADC1_STC_4_7_ch4_Pos (0UL)
6368 #define ADC1_STC_4_7_ch4_Msk (0xffUL)
6371 /* =========================================================================================================================== */
6372 /* ================ ADC2 ================ */
6373 /* =========================================================================================================================== */
6374 
6375 /* ======================================================= CAL_CH0_1 ======================================================= */
6376 #define ADC2_CAL_CH0_1_GAIN_CH1_Pos (24UL)
6377 #define ADC2_CAL_CH0_1_GAIN_CH1_Msk (0xff000000UL)
6378 #define ADC2_CAL_CH0_1_OFFS_CH1_Pos (16UL)
6379 #define ADC2_CAL_CH0_1_OFFS_CH1_Msk (0xff0000UL)
6380 #define ADC2_CAL_CH0_1_GAIN_CH0_Pos (8UL)
6381 #define ADC2_CAL_CH0_1_GAIN_CH0_Msk (0xff00UL)
6382 #define ADC2_CAL_CH0_1_OFFS_CH0_Pos (0UL)
6383 #define ADC2_CAL_CH0_1_OFFS_CH0_Msk (0xffUL)
6384 /* ======================================================= CAL_CH2_3 ======================================================= */
6385 #define ADC2_CAL_CH2_3_GAIN_CH3_Pos (24UL)
6386 #define ADC2_CAL_CH2_3_GAIN_CH3_Msk (0xff000000UL)
6387 #define ADC2_CAL_CH2_3_OFFS_CH3_Pos (16UL)
6388 #define ADC2_CAL_CH2_3_OFFS_CH3_Msk (0xff0000UL)
6389 #define ADC2_CAL_CH2_3_GAIN_CH2_Pos (8UL)
6390 #define ADC2_CAL_CH2_3_GAIN_CH2_Msk (0xff00UL)
6391 #define ADC2_CAL_CH2_3_OFFS_CH2_Pos (0UL)
6392 #define ADC2_CAL_CH2_3_OFFS_CH2_Msk (0xffUL)
6393 /* ======================================================= CAL_CH4_5 ======================================================= */
6394 #define ADC2_CAL_CH4_5_GAIN_CH5_Pos (24UL)
6395 #define ADC2_CAL_CH4_5_GAIN_CH5_Msk (0xff000000UL)
6396 #define ADC2_CAL_CH4_5_OFFS_CH5_Pos (16UL)
6397 #define ADC2_CAL_CH4_5_OFFS_CH5_Msk (0xff0000UL)
6398 #define ADC2_CAL_CH4_5_GAIN_CH4_Pos (8UL)
6399 #define ADC2_CAL_CH4_5_GAIN_CH4_Msk (0xff00UL)
6400 #define ADC2_CAL_CH4_5_OFFS_CH4_Pos (0UL)
6401 #define ADC2_CAL_CH4_5_OFFS_CH4_Msk (0xffUL)
6402 /* ======================================================= CAL_CH6_7 ======================================================= */
6403 #define ADC2_CAL_CH6_7_GAIN_CH7_Pos (24UL)
6404 #define ADC2_CAL_CH6_7_GAIN_CH7_Msk (0xff000000UL)
6405 #define ADC2_CAL_CH6_7_OFFS_CH7_Pos (16UL)
6406 #define ADC2_CAL_CH6_7_OFFS_CH7_Msk (0xff0000UL)
6407 #define ADC2_CAL_CH6_7_GAIN_CH6_Pos (8UL)
6408 #define ADC2_CAL_CH6_7_GAIN_CH6_Msk (0xff00UL)
6409 #define ADC2_CAL_CH6_7_OFFS_CH6_Pos (0UL)
6410 #define ADC2_CAL_CH6_7_OFFS_CH6_Msk (0xffUL)
6411 /* ======================================================= CAL_CH8_9 ======================================================= */
6412 #define ADC2_CAL_CH8_9_GAIN_CH9_Pos (24UL)
6413 #define ADC2_CAL_CH8_9_GAIN_CH9_Msk (0xff000000UL)
6414 #define ADC2_CAL_CH8_9_OFFS_CH9_Pos (16UL)
6415 #define ADC2_CAL_CH8_9_OFFS_CH9_Msk (0xff0000UL)
6416 #define ADC2_CAL_CH8_9_GAIN_CH8_Pos (8UL)
6417 #define ADC2_CAL_CH8_9_GAIN_CH8_Msk (0xff00UL)
6418 #define ADC2_CAL_CH8_9_OFFS_CH8_Pos (0UL)
6419 #define ADC2_CAL_CH8_9_OFFS_CH8_Msk (0xffUL)
6420 /* ======================================================== CHx_EIM ======================================================== */
6421 #define ADC2_CHx_EIM_SEL_Pos (12UL)
6422 #define ADC2_CHx_EIM_SEL_Msk (0x1000UL)
6423 #define ADC2_CHx_EIM_EN_Pos (11UL)
6424 #define ADC2_CHx_EIM_EN_Msk (0x800UL)
6425 #define ADC2_CHx_EIM_REP_Pos (8UL)
6426 #define ADC2_CHx_EIM_REP_Msk (0x700UL)
6427 #define ADC2_CHx_EIM_CHx_Pos (0UL)
6428 #define ADC2_CHx_EIM_CHx_Msk (0x1fUL)
6429 /* ======================================================== CHx_ESM ======================================================== */
6430 #define ADC2_CHx_ESM_STS_Pos (17UL)
6431 #define ADC2_CHx_ESM_STS_Msk (0x20000UL)
6432 #define ADC2_CHx_ESM_EN_Pos (16UL)
6433 #define ADC2_CHx_ESM_EN_Msk (0x10000UL)
6434 #define ADC2_CHx_ESM_SEL_Pos (10UL)
6435 #define ADC2_CHx_ESM_SEL_Msk (0x400UL)
6436 #define ADC2_CHx_ESM_ESM_1_Pos (6UL)
6437 #define ADC2_CHx_ESM_ESM_1_Msk (0x3c0UL)
6438 #define ADC2_CHx_ESM_ESM_0_Pos (0UL)
6439 #define ADC2_CHx_ESM_ESM_0_Msk (0x3fUL)
6440 /* ===================================================== CNT0_3_LOWER ====================================================== */
6441 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Pos (27UL)
6442 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Msk (0x18000000UL)
6443 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Pos (24UL)
6444 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Msk (0x7000000UL)
6445 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Pos (19UL)
6446 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Msk (0x180000UL)
6447 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Pos (16UL)
6448 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Msk (0x70000UL)
6449 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Pos (11UL)
6450 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Msk (0x1800UL)
6451 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Pos (8UL)
6452 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Msk (0x700UL)
6453 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Pos (3UL)
6454 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Msk (0x18UL)
6455 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Pos (0UL)
6456 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Msk (0x7UL)
6457 /* ===================================================== CNT0_3_UPPER ====================================================== */
6458 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Pos (27UL)
6459 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Msk (0x18000000UL)
6460 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Pos (24UL)
6461 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Msk (0x7000000UL)
6462 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Pos (19UL)
6463 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Msk (0x180000UL)
6464 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Pos (16UL)
6465 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Msk (0x70000UL)
6466 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Pos (11UL)
6467 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Msk (0x1800UL)
6468 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Pos (8UL)
6469 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Msk (0x700UL)
6470 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Pos (3UL)
6471 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Msk (0x18UL)
6472 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Pos (0UL)
6473 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Msk (0x7UL)
6474 /* ===================================================== CNT4_5_LOWER ====================================================== */
6475 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Pos (11UL)
6476 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Msk (0x1800UL)
6477 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Pos (8UL)
6478 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Msk (0x700UL)
6479 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Pos (3UL)
6480 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Msk (0x18UL)
6481 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Pos (0UL)
6482 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Msk (0x7UL)
6483 /* ===================================================== CNT4_5_UPPER ====================================================== */
6484 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Pos (11UL)
6485 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Msk (0x1800UL)
6486 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Pos (8UL)
6487 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Msk (0x700UL)
6488 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Pos (3UL)
6489 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Msk (0x18UL)
6490 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Pos (0UL)
6491 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Msk (0x7UL)
6492 /* ===================================================== CNT6_9_LOWER ====================================================== */
6493 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Pos (27UL)
6494 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Msk (0x18000000UL)
6495 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Pos (24UL)
6496 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Msk (0x7000000UL)
6497 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Pos (19UL)
6498 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Msk (0x180000UL)
6499 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Pos (16UL)
6500 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Msk (0x70000UL)
6501 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Pos (11UL)
6502 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Msk (0x1800UL)
6503 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Pos (8UL)
6504 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Msk (0x700UL)
6505 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Pos (3UL)
6506 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Msk (0x18UL)
6507 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Pos (0UL)
6508 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Msk (0x7UL)
6509 /* ===================================================== CNT6_9_UPPER ====================================================== */
6510 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Pos (27UL)
6511 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Msk (0x18000000UL)
6512 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Pos (24UL)
6513 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Msk (0x7000000UL)
6514 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Pos (19UL)
6515 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Msk (0x180000UL)
6516 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Pos (16UL)
6517 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Msk (0x70000UL)
6518 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Pos (11UL)
6519 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Msk (0x1800UL)
6520 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Pos (8UL)
6521 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Msk (0x700UL)
6522 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Pos (3UL)
6523 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Msk (0x18UL)
6524 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Pos (0UL)
6525 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Msk (0x7UL)
6526 /* ========================================================= CTRL1 ========================================================= */
6527 #define ADC2_CTRL1_CALIB_EN_Pos (0UL)
6528 #define ADC2_CTRL1_CALIB_EN_Msk (0x3fUL)
6529 /* ========================================================= CTRL2 ========================================================= */
6530 #define ADC2_CTRL2_SEL_TS_COUNT_Pos (16UL)
6531 #define ADC2_CTRL2_SEL_TS_COUNT_Msk (0xf0000UL)
6532 #define ADC2_CTRL2_SAMPLE_TIME_int_Pos (8UL)
6533 #define ADC2_CTRL2_SAMPLE_TIME_int_Msk (0xf00UL)
6534 #define ADC2_CTRL2_MCM_RDY_Pos (7UL)
6535 #define ADC2_CTRL2_MCM_RDY_Msk (0x80UL)
6536 #define ADC2_CTRL2_TSENSE_SD_SEL_Pos (2UL)
6537 #define ADC2_CTRL2_TSENSE_SD_SEL_Msk (0x4UL)
6538 #define ADC2_CTRL2_TS_SD_SEL_CONF_Pos (1UL)
6539 #define ADC2_CTRL2_TS_SD_SEL_CONF_Msk (0x2UL)
6540 #define ADC2_CTRL2_MCM_PD_N_Pos (0UL)
6541 #define ADC2_CTRL2_MCM_PD_N_Msk (0x1UL)
6542 /* ========================================================= CTRL4 ========================================================= */
6543 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Pos (8UL)
6544 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Msk (0xf00UL)
6545 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Pos (0UL)
6546 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Msk (0x3fUL)
6547 /* ======================================================= CTRL_STS ======================================================== */
6548 #define ADC2_CTRL_STS_VS_RANGE_Pos (17UL)
6549 #define ADC2_CTRL_STS_VS_RANGE_Msk (0x20000UL)
6550 /* ===================================================== FILT_LO_CTRL ====================================================== */
6551 #define ADC2_FILT_LO_CTRL_Ch5_EN_Pos (5UL)
6552 #define ADC2_FILT_LO_CTRL_Ch5_EN_Msk (0x20UL)
6553 #define ADC2_FILT_LO_CTRL_Ch4_EN_Pos (4UL)
6554 #define ADC2_FILT_LO_CTRL_Ch4_EN_Msk (0x10UL)
6555 #define ADC2_FILT_LO_CTRL_Ch3_EN_Pos (3UL)
6556 #define ADC2_FILT_LO_CTRL_Ch3_EN_Msk (0x8UL)
6557 #define ADC2_FILT_LO_CTRL_Ch2_EN_Pos (2UL)
6558 #define ADC2_FILT_LO_CTRL_Ch2_EN_Msk (0x4UL)
6559 #define ADC2_FILT_LO_CTRL_Ch1_EN_Pos (1UL)
6560 #define ADC2_FILT_LO_CTRL_Ch1_EN_Msk (0x2UL)
6561 #define ADC2_FILT_LO_CTRL_Ch0_EN_Pos (0UL)
6562 #define ADC2_FILT_LO_CTRL_Ch0_EN_Msk (0x1UL)
6563 /* ======================================================= FILT_OUT0 ======================================================= */
6564 #define ADC2_FILT_OUT0_OUT_CH0_Pos (0UL)
6565 #define ADC2_FILT_OUT0_OUT_CH0_Msk (0x3ffUL)
6566 /* ======================================================= FILT_OUT1 ======================================================= */
6567 #define ADC2_FILT_OUT1_OUT_CH1_Pos (0UL)
6568 #define ADC2_FILT_OUT1_OUT_CH1_Msk (0x3ffUL)
6569 /* ======================================================= FILT_OUT2 ======================================================= */
6570 #define ADC2_FILT_OUT2_OUT_CH2_Pos (0UL)
6571 #define ADC2_FILT_OUT2_OUT_CH2_Msk (0x3ffUL)
6572 /* ======================================================= FILT_OUT3 ======================================================= */
6573 #define ADC2_FILT_OUT3_OUT_CH3_Pos (0UL)
6574 #define ADC2_FILT_OUT3_OUT_CH3_Msk (0x3ffUL)
6575 /* ======================================================= FILT_OUT4 ======================================================= */
6576 #define ADC2_FILT_OUT4_OUT_CH4_Pos (0UL)
6577 #define ADC2_FILT_OUT4_OUT_CH4_Msk (0x3ffUL)
6578 /* ======================================================= FILT_OUT5 ======================================================= */
6579 #define ADC2_FILT_OUT5_OUT_CH5_Pos (0UL)
6580 #define ADC2_FILT_OUT5_OUT_CH5_Msk (0x3ffUL)
6581 /* ======================================================= FILT_OUT6 ======================================================= */
6582 #define ADC2_FILT_OUT6_OUT_CH6_Pos (0UL)
6583 #define ADC2_FILT_OUT6_OUT_CH6_Msk (0x3ffUL)
6584 /* ======================================================= FILT_OUT7 ======================================================= */
6585 #define ADC2_FILT_OUT7_OUT_CH7_Pos (0UL)
6586 #define ADC2_FILT_OUT7_OUT_CH7_Msk (0x3ffUL)
6587 /* ======================================================= FILT_OUT8 ======================================================= */
6588 #define ADC2_FILT_OUT8_OUT_CH8_Pos (0UL)
6589 #define ADC2_FILT_OUT8_OUT_CH8_Msk (0x3ffUL)
6590 /* ======================================================= FILT_OUT9 ======================================================= */
6591 #define ADC2_FILT_OUT9_OUT_CH9_Pos (0UL)
6592 #define ADC2_FILT_OUT9_OUT_CH9_Msk (0x3ffUL)
6593 /* ===================================================== FILT_UP_CTRL ====================================================== */
6594 #define ADC2_FILT_UP_CTRL_Ch5_EN_Pos (5UL)
6595 #define ADC2_FILT_UP_CTRL_Ch5_EN_Msk (0x20UL)
6596 #define ADC2_FILT_UP_CTRL_Ch4_EN_Pos (4UL)
6597 #define ADC2_FILT_UP_CTRL_Ch4_EN_Msk (0x10UL)
6598 #define ADC2_FILT_UP_CTRL_Ch3_EN_Pos (3UL)
6599 #define ADC2_FILT_UP_CTRL_Ch3_EN_Msk (0x8UL)
6600 #define ADC2_FILT_UP_CTRL_Ch2_EN_Pos (2UL)
6601 #define ADC2_FILT_UP_CTRL_Ch2_EN_Msk (0x4UL)
6602 #define ADC2_FILT_UP_CTRL_Ch1_EN_Pos (1UL)
6603 #define ADC2_FILT_UP_CTRL_Ch1_EN_Msk (0x2UL)
6604 #define ADC2_FILT_UP_CTRL_Ch0_EN_Pos (0UL)
6605 #define ADC2_FILT_UP_CTRL_Ch0_EN_Msk (0x1UL)
6606 /* ===================================================== FILTCOEFF0_5 ====================================================== */
6607 #define ADC2_FILTCOEFF0_5_CH5_Pos (10UL)
6608 #define ADC2_FILTCOEFF0_5_CH5_Msk (0xc00UL)
6609 #define ADC2_FILTCOEFF0_5_CH4_Pos (8UL)
6610 #define ADC2_FILTCOEFF0_5_CH4_Msk (0x300UL)
6611 #define ADC2_FILTCOEFF0_5_CH3_Pos (6UL)
6612 #define ADC2_FILTCOEFF0_5_CH3_Msk (0xc0UL)
6613 #define ADC2_FILTCOEFF0_5_CH2_Pos (4UL)
6614 #define ADC2_FILTCOEFF0_5_CH2_Msk (0x30UL)
6615 #define ADC2_FILTCOEFF0_5_CH1_Pos (2UL)
6616 #define ADC2_FILTCOEFF0_5_CH1_Msk (0xcUL)
6617 #define ADC2_FILTCOEFF0_5_CH0_Pos (0UL)
6618 #define ADC2_FILTCOEFF0_5_CH0_Msk (0x3UL)
6619 /* ===================================================== FILTCOEFF6_9 ====================================================== */
6620 #define ADC2_FILTCOEFF6_9_CH9_Pos (6UL)
6621 #define ADC2_FILTCOEFF6_9_CH9_Msk (0xc0UL)
6622 #define ADC2_FILTCOEFF6_9_CH8_Pos (4UL)
6623 #define ADC2_FILTCOEFF6_9_CH8_Msk (0x30UL)
6624 #define ADC2_FILTCOEFF6_9_CH7_Pos (2UL)
6625 #define ADC2_FILTCOEFF6_9_CH7_Msk (0xcUL)
6626 #define ADC2_FILTCOEFF6_9_CH6_Pos (0UL)
6627 #define ADC2_FILTCOEFF6_9_CH6_Msk (0x3UL)
6628 /* ======================================================== HV_STS ========================================================= */
6629 #define ADC2_HV_STS_READY_Pos (1UL)
6630 #define ADC2_HV_STS_READY_Msk (0x2UL)
6631 /* ======================================================= MMODE0_5 ======================================================== */
6632 #define ADC2_MMODE0_5_Ch5_Pos (10UL)
6633 #define ADC2_MMODE0_5_Ch5_Msk (0xc00UL)
6634 #define ADC2_MMODE0_5_Ch4_Pos (8UL)
6635 #define ADC2_MMODE0_5_Ch4_Msk (0x300UL)
6636 #define ADC2_MMODE0_5_Ch3_Pos (6UL)
6637 #define ADC2_MMODE0_5_Ch3_Msk (0xc0UL)
6638 #define ADC2_MMODE0_5_Ch2_Pos (4UL)
6639 #define ADC2_MMODE0_5_Ch2_Msk (0x30UL)
6640 #define ADC2_MMODE0_5_Ch1_Pos (2UL)
6641 #define ADC2_MMODE0_5_Ch1_Msk (0xcUL)
6642 #define ADC2_MMODE0_5_Ch0_Pos (0UL)
6643 #define ADC2_MMODE0_5_Ch0_Msk (0x3UL)
6644 /* ========================================================= SQ1_4 ========================================================= */
6645 #define ADC2_SQ1_4_SQ4_Pos (24UL)
6646 #define ADC2_SQ1_4_SQ4_Msk (0x3f000000UL)
6647 #define ADC2_SQ1_4_SQ3_Pos (16UL)
6648 #define ADC2_SQ1_4_SQ3_Msk (0x3f0000UL)
6649 #define ADC2_SQ1_4_SQ2_Pos (8UL)
6650 #define ADC2_SQ1_4_SQ2_Msk (0x3f00UL)
6651 #define ADC2_SQ1_4_SQ1_Pos (0UL)
6652 #define ADC2_SQ1_4_SQ1_Msk (0x3fUL)
6653 /* ======================================================= SQ1_8_int ======================================================= */
6654 #define ADC2_SQ1_8_int_SQ8_int_Pos (28UL)
6655 #define ADC2_SQ1_8_int_SQ8_int_Msk (0xf0000000UL)
6656 #define ADC2_SQ1_8_int_SQ7_int_Pos (24UL)
6657 #define ADC2_SQ1_8_int_SQ7_int_Msk (0xf000000UL)
6658 #define ADC2_SQ1_8_int_SQ6_int_Pos (20UL)
6659 #define ADC2_SQ1_8_int_SQ6_int_Msk (0xf00000UL)
6660 #define ADC2_SQ1_8_int_SQ5_int_Pos (16UL)
6661 #define ADC2_SQ1_8_int_SQ5_int_Msk (0xf0000UL)
6662 #define ADC2_SQ1_8_int_SQ4_int_Pos (12UL)
6663 #define ADC2_SQ1_8_int_SQ4_int_Msk (0xf000UL)
6664 #define ADC2_SQ1_8_int_SQ3_int_Pos (8UL)
6665 #define ADC2_SQ1_8_int_SQ3_int_Msk (0xf00UL)
6666 #define ADC2_SQ1_8_int_SQ2_int_Pos (4UL)
6667 #define ADC2_SQ1_8_int_SQ2_int_Msk (0xf0UL)
6668 #define ADC2_SQ1_8_int_SQ1_int_Pos (0UL)
6669 #define ADC2_SQ1_8_int_SQ1_int_Msk (0xfUL)
6670 /* ========================================================= SQ5_8 ========================================================= */
6671 #define ADC2_SQ5_8_SQ8_Pos (24UL)
6672 #define ADC2_SQ5_8_SQ8_Msk (0x3f000000UL)
6673 #define ADC2_SQ5_8_SQ7_Pos (16UL)
6674 #define ADC2_SQ5_8_SQ7_Msk (0x3f0000UL)
6675 #define ADC2_SQ5_8_SQ6_Pos (8UL)
6676 #define ADC2_SQ5_8_SQ6_Msk (0x3f00UL)
6677 #define ADC2_SQ5_8_SQ5_Pos (0UL)
6678 #define ADC2_SQ5_8_SQ5_Msk (0x3fUL)
6679 /* ======================================================== SQ9_10 ========================================================= */
6680 #define ADC2_SQ9_10_SQ10_Pos (8UL)
6681 #define ADC2_SQ9_10_SQ10_Msk (0x3f00UL)
6682 #define ADC2_SQ9_10_SQ9_Pos (0UL)
6683 #define ADC2_SQ9_10_SQ9_Msk (0x3fUL)
6684 /* ====================================================== SQ9_10_int ======================================================= */
6685 #define ADC2_SQ9_10_int_SQ10_int_Pos (4UL)
6686 #define ADC2_SQ9_10_int_SQ10_int_Msk (0xf0UL)
6687 #define ADC2_SQ9_10_int_SQ9_int_Pos (0UL)
6688 #define ADC2_SQ9_10_int_SQ9_int_Msk (0xfUL)
6689 /* ========================================================= SQ_FB ========================================================= */
6690 #define ADC2_SQ_FB_CHx_Pos (16UL)
6691 #define ADC2_SQ_FB_CHx_Msk (0x1f0000UL)
6692 #define ADC2_SQ_FB_SQx_Pos (11UL)
6693 #define ADC2_SQ_FB_SQx_Msk (0x7800UL)
6694 #define ADC2_SQ_FB_ESM_ACTIVE_Pos (10UL)
6695 #define ADC2_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6696 #define ADC2_SQ_FB_EIM_ACTIVE_Pos (9UL)
6697 #define ADC2_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6698 #define ADC2_SQ_FB_SQ_STOP_Pos (8UL)
6699 #define ADC2_SQ_FB_SQ_STOP_Msk (0x100UL)
6700 #define ADC2_SQ_FB_SQ_FB_Pos (0UL)
6701 #define ADC2_SQ_FB_SQ_FB_Msk (0xfUL)
6702 /* ====================================================== TH0_3_LOWER ====================================================== */
6703 #define ADC2_TH0_3_LOWER_CH3_Pos (24UL)
6704 #define ADC2_TH0_3_LOWER_CH3_Msk (0xff000000UL)
6705 #define ADC2_TH0_3_LOWER_CH2_Pos (16UL)
6706 #define ADC2_TH0_3_LOWER_CH2_Msk (0xff0000UL)
6707 #define ADC2_TH0_3_LOWER_CH1_Pos (8UL)
6708 #define ADC2_TH0_3_LOWER_CH1_Msk (0xff00UL)
6709 #define ADC2_TH0_3_LOWER_CH0_Pos (0UL)
6710 #define ADC2_TH0_3_LOWER_CH0_Msk (0xffUL)
6711 /* ====================================================== TH0_3_UPPER ====================================================== */
6712 #define ADC2_TH0_3_UPPER_CH3_Pos (24UL)
6713 #define ADC2_TH0_3_UPPER_CH3_Msk (0xff000000UL)
6714 #define ADC2_TH0_3_UPPER_CH2_Pos (16UL)
6715 #define ADC2_TH0_3_UPPER_CH2_Msk (0xff0000UL)
6716 #define ADC2_TH0_3_UPPER_CH1_Pos (8UL)
6717 #define ADC2_TH0_3_UPPER_CH1_Msk (0xff00UL)
6718 #define ADC2_TH0_3_UPPER_CH0_Pos (0UL)
6719 #define ADC2_TH0_3_UPPER_CH0_Msk (0xffUL)
6720 /* ====================================================== TH4_5_LOWER ====================================================== */
6721 #define ADC2_TH4_5_LOWER_CH5_Pos (8UL)
6722 #define ADC2_TH4_5_LOWER_CH5_Msk (0xff00UL)
6723 #define ADC2_TH4_5_LOWER_CH4_Pos (0UL)
6724 #define ADC2_TH4_5_LOWER_CH4_Msk (0xffUL)
6725 /* ====================================================== TH4_5_UPPER ====================================================== */
6726 #define ADC2_TH4_5_UPPER_CH5_Pos (8UL)
6727 #define ADC2_TH4_5_UPPER_CH5_Msk (0xff00UL)
6728 #define ADC2_TH4_5_UPPER_CH4_Pos (0UL)
6729 #define ADC2_TH4_5_UPPER_CH4_Msk (0xffUL)
6730 /* ====================================================== TH6_9_LOWER ====================================================== */
6731 #define ADC2_TH6_9_LOWER_CH9_Pos (24UL)
6732 #define ADC2_TH6_9_LOWER_CH9_Msk (0xff000000UL)
6733 #define ADC2_TH6_9_LOWER_CH8_Pos (16UL)
6734 #define ADC2_TH6_9_LOWER_CH8_Msk (0xff0000UL)
6735 #define ADC2_TH6_9_LOWER_CH7_Pos (8UL)
6736 #define ADC2_TH6_9_LOWER_CH7_Msk (0xff00UL)
6737 #define ADC2_TH6_9_LOWER_CH6_Pos (0UL)
6738 #define ADC2_TH6_9_LOWER_CH6_Msk (0xffUL)
6739 /* ====================================================== TH6_9_UPPER ====================================================== */
6740 #define ADC2_TH6_9_UPPER_CH9_Pos (24UL)
6741 #define ADC2_TH6_9_UPPER_CH9_Msk (0xff000000UL)
6742 #define ADC2_TH6_9_UPPER_CH8_Pos (16UL)
6743 #define ADC2_TH6_9_UPPER_CH8_Msk (0xff0000UL)
6744 #define ADC2_TH6_9_UPPER_CH7_Pos (8UL)
6745 #define ADC2_TH6_9_UPPER_CH7_Msk (0xff00UL)
6746 #define ADC2_TH6_9_UPPER_CH6_Pos (0UL)
6747 #define ADC2_TH6_9_UPPER_CH6_Msk (0xffUL)
6750 /* =========================================================================================================================== */
6751 /* ================ ADC34 ================ */
6752 /* =========================================================================================================================== */
6753 
6754 /* ======================================================= CTRL_STS ======================================================== */
6755 #define ADC34_CTRL_STS_ADC4_OSR_Pos (28UL)
6756 #define ADC34_CTRL_STS_ADC4_OSR_Msk (0xf0000000UL)
6757 #define ADC34_CTRL_STS_ADC34_DITHVAL_Pos (24UL)
6758 #define ADC34_CTRL_STS_ADC34_DITHVAL_Msk (0xf000000UL)
6759 #define ADC34_CTRL_STS_ADC34_DITHEN_Pos (23UL)
6760 #define ADC34_CTRL_STS_ADC34_DITHEN_Msk (0x800000UL)
6761 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Pos (21UL)
6762 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Msk (0x600000UL)
6763 #define ADC34_CTRL_STS_ADC4_EoC_STS_Pos (20UL)
6764 #define ADC34_CTRL_STS_ADC4_EoC_STS_Msk (0x100000UL)
6765 #define ADC34_CTRL_STS_ADC4_SOC_Pos (18UL)
6766 #define ADC34_CTRL_STS_ADC4_SOC_Msk (0x40000UL)
6767 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Pos (17UL)
6768 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Msk (0x20000UL)
6769 #define ADC34_CTRL_STS_ADC4_EN_Pos (16UL)
6770 #define ADC34_CTRL_STS_ADC4_EN_Msk (0x10000UL)
6771 #define ADC34_CTRL_STS_ADC3_OSR_Pos (12UL)
6772 #define ADC34_CTRL_STS_ADC3_OSR_Msk (0xf000UL)
6773 #define ADC34_CTRL_STS_ADC34_REF_SEL_Pos (11UL)
6774 #define ADC34_CTRL_STS_ADC34_REF_SEL_Msk (0x800UL)
6775 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Pos (5UL)
6776 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Msk (0x60UL)
6777 #define ADC34_CTRL_STS_ADC3_EoC_STS_Pos (4UL)
6778 #define ADC34_CTRL_STS_ADC3_EoC_STS_Msk (0x10UL)
6779 #define ADC34_CTRL_STS_ADC3_SOC_Pos (2UL)
6780 #define ADC34_CTRL_STS_ADC3_SOC_Msk (0x4UL)
6781 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Pos (1UL)
6782 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Msk (0x2UL)
6783 #define ADC34_CTRL_STS_ADC3_EN_Pos (0UL)
6784 #define ADC34_CTRL_STS_ADC3_EN_Msk (0x1UL)
6785 /* ========================================================= RESU ========================================================== */
6786 #define ADC34_RESU_ADC4_RESU_Pos (16UL)
6787 #define ADC34_RESU_ADC4_RESU_Msk (0xffff0000UL)
6788 #define ADC34_RESU_ADC3_RESU_Pos (0UL)
6789 #define ADC34_RESU_ADC3_RESU_Msk (0xffffUL)
6792 /* =========================================================================================================================== */
6793 /* ================ BDRV ================ */
6794 /* =========================================================================================================================== */
6795 
6796 /* ====================================================== CP_CLK_CTRL ====================================================== */
6797 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Pos (15UL)
6798 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Msk (0x8000UL)
6799 #define BDRV_CP_CLK_CTRL_F_CP_Pos (13UL)
6800 #define BDRV_CP_CLK_CTRL_F_CP_Msk (0x6000UL)
6801 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Pos (8UL)
6802 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Msk (0x1f00UL)
6803 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Pos (0UL)
6804 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Msk (0x1fUL)
6805 /* ====================================================== CP_CTRL_STS ====================================================== */
6806 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Pos (26UL)
6807 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Msk (0xc000000UL)
6808 #define BDRV_CP_CTRL_STS_VCP9V_SET_Pos (25UL)
6809 #define BDRV_CP_CTRL_STS_VCP9V_SET_Msk (0x2000000UL)
6810 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Pos (24UL)
6811 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Msk (0x1000000UL)
6812 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Pos (23UL)
6813 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Msk (0x800000UL)
6814 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Pos (22UL)
6815 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Msk (0x400000UL)
6816 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Pos (21UL)
6817 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Msk (0x200000UL)
6818 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Pos (20UL)
6819 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Msk (0x100000UL)
6820 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Pos (19UL)
6821 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Msk (0x80000UL)
6822 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Pos (18UL)
6823 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Msk (0x40000UL)
6824 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Pos (17UL)
6825 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Msk (0x20000UL)
6826 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Pos (16UL)
6827 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Msk (0x10000UL)
6828 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Pos (8UL)
6829 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Msk (0x700UL)
6830 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Pos (5UL)
6831 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Msk (0x20UL)
6832 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Pos (2UL)
6833 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Msk (0x4UL)
6834 #define BDRV_CP_CTRL_STS_CP_EN_Pos (0UL)
6835 #define BDRV_CP_CTRL_STS_CP_EN_Msk (0x1UL)
6836 /* ========================================================= CTRL1 ========================================================= */
6837 #define BDRV_CTRL1_HS2_OC_DIS_Pos (31UL)
6838 #define BDRV_CTRL1_HS2_OC_DIS_Msk (0x80000000UL)
6839 #define BDRV_CTRL1_HS2_OC_STS_Pos (30UL)
6840 #define BDRV_CTRL1_HS2_OC_STS_Msk (0x40000000UL)
6841 #define BDRV_CTRL1_HS2_SUPERR_STS_Pos (29UL)
6842 #define BDRV_CTRL1_HS2_SUPERR_STS_Msk (0x20000000UL)
6843 #define BDRV_CTRL1_HS2_DS_STS_Pos (28UL)
6844 #define BDRV_CTRL1_HS2_DS_STS_Msk (0x10000000UL)
6845 #define BDRV_CTRL1_HS2_DCS_EN_Pos (27UL)
6846 #define BDRV_CTRL1_HS2_DCS_EN_Msk (0x8000000UL)
6847 #define BDRV_CTRL1_HS2_ON_Pos (26UL)
6848 #define BDRV_CTRL1_HS2_ON_Msk (0x4000000UL)
6849 #define BDRV_CTRL1_HS2_PWM_Pos (25UL)
6850 #define BDRV_CTRL1_HS2_PWM_Msk (0x2000000UL)
6851 #define BDRV_CTRL1_HS2_EN_Pos (24UL)
6852 #define BDRV_CTRL1_HS2_EN_Msk (0x1000000UL)
6853 #define BDRV_CTRL1_HS1_OC_DIS_Pos (23UL)
6854 #define BDRV_CTRL1_HS1_OC_DIS_Msk (0x800000UL)
6855 #define BDRV_CTRL1_HS1_OC_STS_Pos (22UL)
6856 #define BDRV_CTRL1_HS1_OC_STS_Msk (0x400000UL)
6857 #define BDRV_CTRL1_HS1_SUPERR_STS_Pos (21UL)
6858 #define BDRV_CTRL1_HS1_SUPERR_STS_Msk (0x200000UL)
6859 #define BDRV_CTRL1_HS1_DS_STS_Pos (20UL)
6860 #define BDRV_CTRL1_HS1_DS_STS_Msk (0x100000UL)
6861 #define BDRV_CTRL1_HS1_DCS_EN_Pos (19UL)
6862 #define BDRV_CTRL1_HS1_DCS_EN_Msk (0x80000UL)
6863 #define BDRV_CTRL1_HS1_ON_Pos (18UL)
6864 #define BDRV_CTRL1_HS1_ON_Msk (0x40000UL)
6865 #define BDRV_CTRL1_HS1_PWM_Pos (17UL)
6866 #define BDRV_CTRL1_HS1_PWM_Msk (0x20000UL)
6867 #define BDRV_CTRL1_HS1_EN_Pos (16UL)
6868 #define BDRV_CTRL1_HS1_EN_Msk (0x10000UL)
6869 #define BDRV_CTRL1_LS2_OC_DIS_Pos (15UL)
6870 #define BDRV_CTRL1_LS2_OC_DIS_Msk (0x8000UL)
6871 #define BDRV_CTRL1_LS2_OC_STS_Pos (14UL)
6872 #define BDRV_CTRL1_LS2_OC_STS_Msk (0x4000UL)
6873 #define BDRV_CTRL1_LS2_SUPERR_STS_Pos (13UL)
6874 #define BDRV_CTRL1_LS2_SUPERR_STS_Msk (0x2000UL)
6875 #define BDRV_CTRL1_LS2_DS_STS_Pos (12UL)
6876 #define BDRV_CTRL1_LS2_DS_STS_Msk (0x1000UL)
6877 #define BDRV_CTRL1_LS2_DCS_EN_Pos (11UL)
6878 #define BDRV_CTRL1_LS2_DCS_EN_Msk (0x800UL)
6879 #define BDRV_CTRL1_LS2_ON_Pos (10UL)
6880 #define BDRV_CTRL1_LS2_ON_Msk (0x400UL)
6881 #define BDRV_CTRL1_LS2_PWM_Pos (9UL)
6882 #define BDRV_CTRL1_LS2_PWM_Msk (0x200UL)
6883 #define BDRV_CTRL1_LS2_EN_Pos (8UL)
6884 #define BDRV_CTRL1_LS2_EN_Msk (0x100UL)
6885 #define BDRV_CTRL1_LS1_OC_DIS_Pos (7UL)
6886 #define BDRV_CTRL1_LS1_OC_DIS_Msk (0x80UL)
6887 #define BDRV_CTRL1_LS1_OC_STS_Pos (6UL)
6888 #define BDRV_CTRL1_LS1_OC_STS_Msk (0x40UL)
6889 #define BDRV_CTRL1_LS1_SUPERR_STS_Pos (5UL)
6890 #define BDRV_CTRL1_LS1_SUPERR_STS_Msk (0x20UL)
6891 #define BDRV_CTRL1_LS1_DS_STS_Pos (4UL)
6892 #define BDRV_CTRL1_LS1_DS_STS_Msk (0x10UL)
6893 #define BDRV_CTRL1_LS1_DCS_EN_Pos (3UL)
6894 #define BDRV_CTRL1_LS1_DCS_EN_Msk (0x8UL)
6895 #define BDRV_CTRL1_LS1_ON_Pos (2UL)
6896 #define BDRV_CTRL1_LS1_ON_Msk (0x4UL)
6897 #define BDRV_CTRL1_LS1_PWM_Pos (1UL)
6898 #define BDRV_CTRL1_LS1_PWM_Msk (0x2UL)
6899 #define BDRV_CTRL1_LS1_EN_Pos (0UL)
6900 #define BDRV_CTRL1_LS1_EN_Msk (0x1UL)
6901 /* ========================================================= CTRL2 ========================================================= */
6902 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Pos (31UL)
6903 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Msk (0x80000000UL)
6904 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Pos (28UL)
6905 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Msk (0x70000000UL)
6906 #define BDRV_CTRL2_DLY_DIAG_STS_Pos (27UL)
6907 #define BDRV_CTRL2_DLY_DIAG_STS_Msk (0x8000000UL)
6908 #define BDRV_CTRL2_DLY_DIAG_SCLR_Pos (26UL)
6909 #define BDRV_CTRL2_DLY_DIAG_SCLR_Msk (0x4000000UL)
6910 #define BDRV_CTRL2_DLY_DIAG_TIM_Pos (16UL)
6911 #define BDRV_CTRL2_DLY_DIAG_TIM_Msk (0x3ff0000UL)
6912 #define BDRV_CTRL2_HS3_OC_DIS_Pos (15UL)
6913 #define BDRV_CTRL2_HS3_OC_DIS_Msk (0x8000UL)
6914 #define BDRV_CTRL2_HS3_OC_STS_Pos (14UL)
6915 #define BDRV_CTRL2_HS3_OC_STS_Msk (0x4000UL)
6916 #define BDRV_CTRL2_HS3_SUPERR_STS_Pos (13UL)
6917 #define BDRV_CTRL2_HS3_SUPERR_STS_Msk (0x2000UL)
6918 #define BDRV_CTRL2_HS3_DS_STS_Pos (12UL)
6919 #define BDRV_CTRL2_HS3_DS_STS_Msk (0x1000UL)
6920 #define BDRV_CTRL2_HS3_DCS_EN_Pos (11UL)
6921 #define BDRV_CTRL2_HS3_DCS_EN_Msk (0x800UL)
6922 #define BDRV_CTRL2_HS3_ON_Pos (10UL)
6923 #define BDRV_CTRL2_HS3_ON_Msk (0x400UL)
6924 #define BDRV_CTRL2_HS3_PWM_Pos (9UL)
6925 #define BDRV_CTRL2_HS3_PWM_Msk (0x200UL)
6926 #define BDRV_CTRL2_HS3_EN_Pos (8UL)
6927 #define BDRV_CTRL2_HS3_EN_Msk (0x100UL)
6928 #define BDRV_CTRL2_LS3_OC_DIS_Pos (7UL)
6929 #define BDRV_CTRL2_LS3_OC_DIS_Msk (0x80UL)
6930 #define BDRV_CTRL2_LS3_OC_STS_Pos (6UL)
6931 #define BDRV_CTRL2_LS3_OC_STS_Msk (0x40UL)
6932 #define BDRV_CTRL2_LS3_SUPERR_STS_Pos (5UL)
6933 #define BDRV_CTRL2_LS3_SUPERR_STS_Msk (0x20UL)
6934 #define BDRV_CTRL2_LS3_DS_STS_Pos (4UL)
6935 #define BDRV_CTRL2_LS3_DS_STS_Msk (0x10UL)
6936 #define BDRV_CTRL2_LS3_DCS_EN_Pos (3UL)
6937 #define BDRV_CTRL2_LS3_DCS_EN_Msk (0x8UL)
6938 #define BDRV_CTRL2_LS3_ON_Pos (2UL)
6939 #define BDRV_CTRL2_LS3_ON_Msk (0x4UL)
6940 #define BDRV_CTRL2_LS3_PWM_Pos (1UL)
6941 #define BDRV_CTRL2_LS3_PWM_Msk (0x2UL)
6942 #define BDRV_CTRL2_LS3_EN_Pos (0UL)
6943 #define BDRV_CTRL2_LS3_EN_Msk (0x1UL)
6944 /* ========================================================= CTRL3 ========================================================= */
6945 #define BDRV_CTRL3_DRV_CCP_DIS_Pos (26UL)
6946 #define BDRV_CTRL3_DRV_CCP_DIS_Msk (0x4000000UL)
6947 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Pos (24UL)
6948 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Msk (0x3000000UL)
6949 #define BDRV_CTRL3_DSMONVTH_Pos (16UL)
6950 #define BDRV_CTRL3_DSMONVTH_Msk (0x70000UL)
6951 #define BDRV_CTRL3_OFF_SEQ_EN_Pos (15UL)
6952 #define BDRV_CTRL3_OFF_SEQ_EN_Msk (0x8000UL)
6953 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Pos (14UL)
6954 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Msk (0x4000UL)
6955 #define BDRV_CTRL3_IDISCHARGE_TRIM_Pos (8UL)
6956 #define BDRV_CTRL3_IDISCHARGE_TRIM_Msk (0x1f00UL)
6957 #define BDRV_CTRL3_ON_SEQ_EN_Pos (7UL)
6958 #define BDRV_CTRL3_ON_SEQ_EN_Msk (0x80UL)
6959 #define BDRV_CTRL3_ICHARGEDIV2_N_Pos (6UL)
6960 #define BDRV_CTRL3_ICHARGEDIV2_N_Msk (0x40UL)
6961 #define BDRV_CTRL3_ICHARGE_TRIM_Pos (0UL)
6962 #define BDRV_CTRL3_ICHARGE_TRIM_Msk (0x1fUL)
6963 /* ===================================================== OFF_SEQ_CTRL ====================================================== */
6964 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Pos (27UL)
6965 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Msk (0xf8000000UL)
6966 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Pos (24UL)
6967 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Msk (0x7000000UL)
6968 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Pos (19UL)
6969 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Msk (0xf80000UL)
6970 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Pos (16UL)
6971 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Msk (0x70000UL)
6972 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Pos (11UL)
6973 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Msk (0xf800UL)
6974 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Pos (8UL)
6975 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Msk (0x700UL)
6976 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Pos (3UL)
6977 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Msk (0xf8UL)
6978 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Pos (0UL)
6979 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Msk (0x7UL)
6980 /* ====================================================== ON_SEQ_CTRL ====================================================== */
6981 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Pos (27UL)
6982 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Msk (0xf8000000UL)
6983 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Pos (24UL)
6984 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Msk (0x7000000UL)
6985 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Pos (19UL)
6986 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Msk (0xf80000UL)
6987 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Pos (16UL)
6988 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Msk (0x70000UL)
6989 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Pos (11UL)
6990 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Msk (0xf800UL)
6991 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Pos (8UL)
6992 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Msk (0x700UL)
6993 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Pos (3UL)
6994 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Msk (0xf8UL)
6995 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Pos (0UL)
6996 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Msk (0x7UL)
6997 /* ======================================================= TRIM_DRVx ======================================================= */
6998 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Pos (24UL)
6999 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Msk (0x3000000UL)
7000 #define BDRV_TRIM_DRVx_HS3DRV_OCSDN_DIS_Pos (23UL)
7001 #define BDRV_TRIM_DRVx_HS3DRV_OCSDN_DIS_Msk (0x800000UL)
7002 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Pos (22UL)
7003 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Msk (0x400000UL)
7004 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Pos (21UL)
7005 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Msk (0x200000UL)
7006 #define BDRV_TRIM_DRVx_HS3DRV_FDISCHG_DIS_Pos (20UL)
7007 #define BDRV_TRIM_DRVx_HS3DRV_FDISCHG_DIS_Msk (0x100000UL)
7008 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Pos (19UL)
7009 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Msk (0x80000UL)
7010 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Pos (18UL)
7011 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Msk (0x40000UL)
7012 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Pos (16UL)
7013 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Msk (0x30000UL)
7014 #define BDRV_TRIM_DRVx_LS3DRV_OCSDN_DIS_Pos (15UL)
7015 #define BDRV_TRIM_DRVx_LS3DRV_OCSDN_DIS_Msk (0x8000UL)
7016 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Pos (14UL)
7017 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Msk (0x4000UL)
7018 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Pos (13UL)
7019 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Msk (0x2000UL)
7020 #define BDRV_TRIM_DRVx_LS3DRV_FDISCHG_DIS_Pos (12UL)
7021 #define BDRV_TRIM_DRVx_LS3DRV_FDISCHG_DIS_Msk (0x1000UL)
7022 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Pos (11UL)
7023 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Msk (0x800UL)
7024 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Pos (10UL)
7025 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Msk (0x400UL)
7026 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Pos (8UL)
7027 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Msk (0x300UL)
7028 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Pos (5UL)
7029 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Msk (0x60UL)
7030 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Pos (0UL)
7031 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Msk (0x3UL)
7034 /* =========================================================================================================================== */
7035 /* ================ CCU6 ================ */
7036 /* =========================================================================================================================== */
7037 
7038 /* ========================================================= CC60R ========================================================= */
7039 #define CCU6_CC60R_CCV_Pos (0UL)
7040 #define CCU6_CC60R_CCV_Msk (0xffffUL)
7041 /* ======================================================== CC60SR ========================================================= */
7042 #define CCU6_CC60SR_CCS_Pos (0UL)
7043 #define CCU6_CC60SR_CCS_Msk (0xffffUL)
7044 /* ========================================================= CC61R ========================================================= */
7045 #define CCU6_CC61R_CCV_Pos (0UL)
7046 #define CCU6_CC61R_CCV_Msk (0xffffUL)
7047 /* ======================================================== CC61SR ========================================================= */
7048 #define CCU6_CC61SR_CCS_Pos (0UL)
7049 #define CCU6_CC61SR_CCS_Msk (0xffffUL)
7050 /* ========================================================= CC62R ========================================================= */
7051 #define CCU6_CC62R_CCV_Pos (0UL)
7052 #define CCU6_CC62R_CCV_Msk (0xffffUL)
7053 /* ======================================================== CC62SR ========================================================= */
7054 #define CCU6_CC62SR_CCS_Pos (0UL)
7055 #define CCU6_CC62SR_CCS_Msk (0xffffUL)
7056 /* ========================================================= CC63R ========================================================= */
7057 #define CCU6_CC63R_CCV_Pos (0UL)
7058 #define CCU6_CC63R_CCV_Msk (0xffffUL)
7059 /* ======================================================== CC63SR ========================================================= */
7060 #define CCU6_CC63SR_CCS_Pos (0UL)
7061 #define CCU6_CC63SR_CCS_Msk (0xffffUL)
7062 /* ======================================================= CMPMODIF ======================================================== */
7063 #define CCU6_CMPMODIF_MCC60S_Pos (0UL)
7064 #define CCU6_CMPMODIF_MCC60S_Msk (0x1UL)
7065 #define CCU6_CMPMODIF_MCC61S_Pos (1UL)
7066 #define CCU6_CMPMODIF_MCC61S_Msk (0x2UL)
7067 #define CCU6_CMPMODIF_MCC62S_Pos (2UL)
7068 #define CCU6_CMPMODIF_MCC62S_Msk (0x4UL)
7069 #define CCU6_CMPMODIF_MCC63S_Pos (6UL)
7070 #define CCU6_CMPMODIF_MCC63S_Msk (0x40UL)
7071 #define CCU6_CMPMODIF_MCC60R_Pos (8UL)
7072 #define CCU6_CMPMODIF_MCC60R_Msk (0x100UL)
7073 #define CCU6_CMPMODIF_MCC61R_Pos (9UL)
7074 #define CCU6_CMPMODIF_MCC61R_Msk (0x200UL)
7075 #define CCU6_CMPMODIF_MCC62R_Pos (10UL)
7076 #define CCU6_CMPMODIF_MCC62R_Msk (0x400UL)
7077 #define CCU6_CMPMODIF_MCC63R_Pos (14UL)
7078 #define CCU6_CMPMODIF_MCC63R_Msk (0x4000UL)
7079 /* ======================================================== CMPSTAT ======================================================== */
7080 #define CCU6_CMPSTAT_CC60ST_Pos (0UL)
7081 #define CCU6_CMPSTAT_CC60ST_Msk (0x1UL)
7082 #define CCU6_CMPSTAT_CC61ST_Pos (1UL)
7083 #define CCU6_CMPSTAT_CC61ST_Msk (0x2UL)
7084 #define CCU6_CMPSTAT_CC62ST_Pos (2UL)
7085 #define CCU6_CMPSTAT_CC62ST_Msk (0x4UL)
7086 #define CCU6_CMPSTAT_CC63ST_Pos (6UL)
7087 #define CCU6_CMPSTAT_CC63ST_Msk (0x40UL)
7088 #define CCU6_CMPSTAT_CCPOS0_Pos (3UL)
7089 #define CCU6_CMPSTAT_CCPOS0_Msk (0x8UL)
7090 #define CCU6_CMPSTAT_CCPOS1_Pos (4UL)
7091 #define CCU6_CMPSTAT_CCPOS1_Msk (0x10UL)
7092 #define CCU6_CMPSTAT_CCPOS2_Pos (5UL)
7093 #define CCU6_CMPSTAT_CCPOS2_Msk (0x20UL)
7094 #define CCU6_CMPSTAT_CC60PS_Pos (8UL)
7095 #define CCU6_CMPSTAT_CC60PS_Msk (0x100UL)
7096 #define CCU6_CMPSTAT_CC61PS_Pos (10UL)
7097 #define CCU6_CMPSTAT_CC61PS_Msk (0x400UL)
7098 #define CCU6_CMPSTAT_CC62PS_Pos (12UL)
7099 #define CCU6_CMPSTAT_CC62PS_Msk (0x1000UL)
7100 #define CCU6_CMPSTAT_COUT60PS_Pos (9UL)
7101 #define CCU6_CMPSTAT_COUT60PS_Msk (0x200UL)
7102 #define CCU6_CMPSTAT_COUT61PS_Pos (11UL)
7103 #define CCU6_CMPSTAT_COUT61PS_Msk (0x800UL)
7104 #define CCU6_CMPSTAT_COUT62PS_Pos (13UL)
7105 #define CCU6_CMPSTAT_COUT62PS_Msk (0x2000UL)
7106 #define CCU6_CMPSTAT_COUT63PS_Pos (14UL)
7107 #define CCU6_CMPSTAT_COUT63PS_Msk (0x4000UL)
7108 #define CCU6_CMPSTAT_T13IM_Pos (15UL)
7109 #define CCU6_CMPSTAT_T13IM_Msk (0x8000UL)
7110 /* ========================================================== IEN ========================================================== */
7111 #define CCU6_IEN_ENCC60R_Pos (0UL)
7112 #define CCU6_IEN_ENCC60R_Msk (0x1UL)
7113 #define CCU6_IEN_ENCC60F_Pos (1UL)
7114 #define CCU6_IEN_ENCC60F_Msk (0x2UL)
7115 #define CCU6_IEN_ENCC61R_Pos (2UL)
7116 #define CCU6_IEN_ENCC61R_Msk (0x4UL)
7117 #define CCU6_IEN_ENCC61F_Pos (3UL)
7118 #define CCU6_IEN_ENCC61F_Msk (0x8UL)
7119 #define CCU6_IEN_ENCC62R_Pos (4UL)
7120 #define CCU6_IEN_ENCC62R_Msk (0x10UL)
7121 #define CCU6_IEN_ENCC62F_Pos (5UL)
7122 #define CCU6_IEN_ENCC62F_Msk (0x20UL)
7123 #define CCU6_IEN_ENT12OM_Pos (6UL)
7124 #define CCU6_IEN_ENT12OM_Msk (0x40UL)
7125 #define CCU6_IEN_ENT12PM_Pos (7UL)
7126 #define CCU6_IEN_ENT12PM_Msk (0x80UL)
7127 #define CCU6_IEN_ENT13CM_Pos (8UL)
7128 #define CCU6_IEN_ENT13CM_Msk (0x100UL)
7129 #define CCU6_IEN_ENT13PM_Pos (9UL)
7130 #define CCU6_IEN_ENT13PM_Msk (0x200UL)
7131 #define CCU6_IEN_ENTRPF_Pos (10UL)
7132 #define CCU6_IEN_ENTRPF_Msk (0x400UL)
7133 #define CCU6_IEN_ENCHE_Pos (12UL)
7134 #define CCU6_IEN_ENCHE_Msk (0x1000UL)
7135 #define CCU6_IEN_ENWHE_Pos (13UL)
7136 #define CCU6_IEN_ENWHE_Msk (0x2000UL)
7137 #define CCU6_IEN_ENIDLE_Pos (14UL)
7138 #define CCU6_IEN_ENIDLE_Msk (0x4000UL)
7139 #define CCU6_IEN_ENSTR_Pos (15UL)
7140 #define CCU6_IEN_ENSTR_Msk (0x8000UL)
7141 /* ========================================================== INP ========================================================== */
7142 #define CCU6_INP_INPCC60_Pos (0UL)
7143 #define CCU6_INP_INPCC60_Msk (0x3UL)
7144 #define CCU6_INP_INPCC61_Pos (2UL)
7145 #define CCU6_INP_INPCC61_Msk (0xcUL)
7146 #define CCU6_INP_INPCC62_Pos (4UL)
7147 #define CCU6_INP_INPCC62_Msk (0x30UL)
7148 #define CCU6_INP_INPCHE_Pos (6UL)
7149 #define CCU6_INP_INPCHE_Msk (0xc0UL)
7150 #define CCU6_INP_INPERR_Pos (8UL)
7151 #define CCU6_INP_INPERR_Msk (0x300UL)
7152 #define CCU6_INP_INPT12_Pos (10UL)
7153 #define CCU6_INP_INPT12_Msk (0xc00UL)
7154 #define CCU6_INP_INPT13_Pos (12UL)
7155 #define CCU6_INP_INPT13_Msk (0x3000UL)
7156 /* ========================================================== IS =========================================================== */
7157 #define CCU6_IS_ICC60R_Pos (0UL)
7158 #define CCU6_IS_ICC60R_Msk (0x1UL)
7159 #define CCU6_IS_ICC61R_Pos (2UL)
7160 #define CCU6_IS_ICC61R_Msk (0x4UL)
7161 #define CCU6_IS_ICC62R_Pos (4UL)
7162 #define CCU6_IS_ICC62R_Msk (0x10UL)
7163 #define CCU6_IS_ICC60F_Pos (1UL)
7164 #define CCU6_IS_ICC60F_Msk (0x2UL)
7165 #define CCU6_IS_ICC61F_Pos (3UL)
7166 #define CCU6_IS_ICC61F_Msk (0x8UL)
7167 #define CCU6_IS_ICC62F_Pos (5UL)
7168 #define CCU6_IS_ICC62F_Msk (0x20UL)
7169 #define CCU6_IS_T12OM_Pos (6UL)
7170 #define CCU6_IS_T12OM_Msk (0x40UL)
7171 #define CCU6_IS_T12PM_Pos (7UL)
7172 #define CCU6_IS_T12PM_Msk (0x80UL)
7173 #define CCU6_IS_T13CM_Pos (8UL)
7174 #define CCU6_IS_T13CM_Msk (0x100UL)
7175 #define CCU6_IS_T13PM_Pos (9UL)
7176 #define CCU6_IS_T13PM_Msk (0x200UL)
7177 #define CCU6_IS_TRPF_Pos (10UL)
7178 #define CCU6_IS_TRPF_Msk (0x400UL)
7179 #define CCU6_IS_TRPS_Pos (11UL)
7180 #define CCU6_IS_TRPS_Msk (0x800UL)
7181 #define CCU6_IS_CHE_Pos (12UL)
7182 #define CCU6_IS_CHE_Msk (0x1000UL)
7183 #define CCU6_IS_WHE_Pos (13UL)
7184 #define CCU6_IS_WHE_Msk (0x2000UL)
7185 #define CCU6_IS_IDLE_Pos (14UL)
7186 #define CCU6_IS_IDLE_Msk (0x4000UL)
7187 #define CCU6_IS_STR_Pos (15UL)
7188 #define CCU6_IS_STR_Msk (0x8000UL)
7189 /* ========================================================== ISR ========================================================== */
7190 #define CCU6_ISR_RCC60R_Pos (0UL)
7191 #define CCU6_ISR_RCC60R_Msk (0x1UL)
7192 #define CCU6_ISR_RCC60F_Pos (1UL)
7193 #define CCU6_ISR_RCC60F_Msk (0x2UL)
7194 #define CCU6_ISR_RCC61R_Pos (2UL)
7195 #define CCU6_ISR_RCC61R_Msk (0x4UL)
7196 #define CCU6_ISR_RCC61F_Pos (3UL)
7197 #define CCU6_ISR_RCC61F_Msk (0x8UL)
7198 #define CCU6_ISR_RCC62R_Pos (4UL)
7199 #define CCU6_ISR_RCC62R_Msk (0x10UL)
7200 #define CCU6_ISR_RCC62F_Pos (5UL)
7201 #define CCU6_ISR_RCC62F_Msk (0x20UL)
7202 #define CCU6_ISR_RT12OM_Pos (6UL)
7203 #define CCU6_ISR_RT12OM_Msk (0x40UL)
7204 #define CCU6_ISR_RT12PM_Pos (7UL)
7205 #define CCU6_ISR_RT12PM_Msk (0x80UL)
7206 #define CCU6_ISR_RT13CM_Pos (8UL)
7207 #define CCU6_ISR_RT13CM_Msk (0x100UL)
7208 #define CCU6_ISR_RT13PM_Pos (9UL)
7209 #define CCU6_ISR_RT13PM_Msk (0x200UL)
7210 #define CCU6_ISR_RTRPF_Pos (10UL)
7211 #define CCU6_ISR_RTRPF_Msk (0x400UL)
7212 #define CCU6_ISR_RCHE_Pos (12UL)
7213 #define CCU6_ISR_RCHE_Msk (0x1000UL)
7214 #define CCU6_ISR_RWHE_Pos (13UL)
7215 #define CCU6_ISR_RWHE_Msk (0x2000UL)
7216 #define CCU6_ISR_RIDLE_Pos (14UL)
7217 #define CCU6_ISR_RIDLE_Msk (0x4000UL)
7218 #define CCU6_ISR_RSTR_Pos (15UL)
7219 #define CCU6_ISR_RSTR_Msk (0x8000UL)
7220 /* ========================================================== ISS ========================================================== */
7221 #define CCU6_ISS_SCC60R_Pos (0UL)
7222 #define CCU6_ISS_SCC60R_Msk (0x1UL)
7223 #define CCU6_ISS_SCC60F_Pos (1UL)
7224 #define CCU6_ISS_SCC60F_Msk (0x2UL)
7225 #define CCU6_ISS_SCC61R_Pos (2UL)
7226 #define CCU6_ISS_SCC61R_Msk (0x4UL)
7227 #define CCU6_ISS_SCC61F_Pos (3UL)
7228 #define CCU6_ISS_SCC61F_Msk (0x8UL)
7229 #define CCU6_ISS_SCC62R_Pos (4UL)
7230 #define CCU6_ISS_SCC62R_Msk (0x10UL)
7231 #define CCU6_ISS_SCC62F_Pos (5UL)
7232 #define CCU6_ISS_SCC62F_Msk (0x20UL)
7233 #define CCU6_ISS_ST12OM_Pos (6UL)
7234 #define CCU6_ISS_ST12OM_Msk (0x40UL)
7235 #define CCU6_ISS_ST12PM_Pos (7UL)
7236 #define CCU6_ISS_ST12PM_Msk (0x80UL)
7237 #define CCU6_ISS_ST13CM_Pos (8UL)
7238 #define CCU6_ISS_ST13CM_Msk (0x100UL)
7239 #define CCU6_ISS_ST13PM_Pos (9UL)
7240 #define CCU6_ISS_ST13PM_Msk (0x200UL)
7241 #define CCU6_ISS_STRPF_Pos (10UL)
7242 #define CCU6_ISS_STRPF_Msk (0x400UL)
7243 #define CCU6_ISS_SWHC_Pos (11UL)
7244 #define CCU6_ISS_SWHC_Msk (0x800UL)
7245 #define CCU6_ISS_SCHE_Pos (12UL)
7246 #define CCU6_ISS_SCHE_Msk (0x1000UL)
7247 #define CCU6_ISS_SWHE_Pos (13UL)
7248 #define CCU6_ISS_SWHE_Msk (0x2000UL)
7249 #define CCU6_ISS_SIDLE_Pos (14UL)
7250 #define CCU6_ISS_SIDLE_Msk (0x4000UL)
7251 #define CCU6_ISS_SSTR_Pos (15UL)
7252 #define CCU6_ISS_SSTR_Msk (0x8000UL)
7253 /* ======================================================== MCMCTR ========================================================= */
7254 #define CCU6_MCMCTR_SWSEL_Pos (0UL)
7255 #define CCU6_MCMCTR_SWSEL_Msk (0x7UL)
7256 #define CCU6_MCMCTR_SWSYN_Pos (4UL)
7257 #define CCU6_MCMCTR_SWSYN_Msk (0x30UL)
7258 #define CCU6_MCMCTR_STE12U_Pos (8UL)
7259 #define CCU6_MCMCTR_STE12U_Msk (0x100UL)
7260 #define CCU6_MCMCTR_STE12D_Pos (9UL)
7261 #define CCU6_MCMCTR_STE12D_Msk (0x200UL)
7262 #define CCU6_MCMCTR_STE13U_Pos (10UL)
7263 #define CCU6_MCMCTR_STE13U_Msk (0x400UL)
7264 /* ======================================================== MCMOUT ========================================================= */
7265 #define CCU6_MCMOUT_MCMP_Pos (0UL)
7266 #define CCU6_MCMOUT_MCMP_Msk (0x3fUL)
7267 #define CCU6_MCMOUT_R_Pos (6UL)
7268 #define CCU6_MCMOUT_R_Msk (0x40UL)
7269 #define CCU6_MCMOUT_EXPH_Pos (8UL)
7270 #define CCU6_MCMOUT_EXPH_Msk (0x700UL)
7271 #define CCU6_MCMOUT_CURH_Pos (11UL)
7272 #define CCU6_MCMOUT_CURH_Msk (0x3800UL)
7273 /* ======================================================== MCMOUTS ======================================================== */
7274 #define CCU6_MCMOUTS_MCMPS_Pos (0UL)
7275 #define CCU6_MCMOUTS_MCMPS_Msk (0x3fUL)
7276 #define CCU6_MCMOUTS_STRMCM_Pos (7UL)
7277 #define CCU6_MCMOUTS_STRMCM_Msk (0x80UL)
7278 #define CCU6_MCMOUTS_EXPHS_Pos (8UL)
7279 #define CCU6_MCMOUTS_EXPHS_Msk (0x700UL)
7280 #define CCU6_MCMOUTS_CURHS_Pos (11UL)
7281 #define CCU6_MCMOUTS_CURHS_Msk (0x3800UL)
7282 #define CCU6_MCMOUTS_STRHP_Pos (15UL)
7283 #define CCU6_MCMOUTS_STRHP_Msk (0x8000UL)
7284 /* ======================================================== MODCTR ========================================================= */
7285 #define CCU6_MODCTR_T12MODEN_Pos (0UL)
7286 #define CCU6_MODCTR_T12MODEN_Msk (0x3fUL)
7287 #define CCU6_MODCTR_MCMEN_Pos (7UL)
7288 #define CCU6_MODCTR_MCMEN_Msk (0x80UL)
7289 #define CCU6_MODCTR_T13MODEN_Pos (8UL)
7290 #define CCU6_MODCTR_T13MODEN_Msk (0x3f00UL)
7291 #define CCU6_MODCTR_ECT13O_Pos (15UL)
7292 #define CCU6_MODCTR_ECT13O_Msk (0x8000UL)
7293 /* ======================================================== PISEL0 ========================================================= */
7294 #define CCU6_PISEL0_ISCC60_Pos (0UL)
7295 #define CCU6_PISEL0_ISCC60_Msk (0x3UL)
7296 #define CCU6_PISEL0_ISCC61_Pos (2UL)
7297 #define CCU6_PISEL0_ISCC61_Msk (0xcUL)
7298 #define CCU6_PISEL0_ISCC62_Pos (4UL)
7299 #define CCU6_PISEL0_ISCC62_Msk (0x30UL)
7300 #define CCU6_PISEL0_ISTRP_Pos (6UL)
7301 #define CCU6_PISEL0_ISTRP_Msk (0xc0UL)
7302 #define CCU6_PISEL0_ISPOS0_Pos (8UL)
7303 #define CCU6_PISEL0_ISPOS0_Msk (0x300UL)
7304 #define CCU6_PISEL0_ISPOS1_Pos (10UL)
7305 #define CCU6_PISEL0_ISPOS1_Msk (0xc00UL)
7306 #define CCU6_PISEL0_ISPOS2_Pos (12UL)
7307 #define CCU6_PISEL0_ISPOS2_Msk (0x3000UL)
7308 #define CCU6_PISEL0_IST12HR_Pos (14UL)
7309 #define CCU6_PISEL0_IST12HR_Msk (0xc000UL)
7310 /* ======================================================== PISEL2 ========================================================= */
7311 #define CCU6_PISEL2_IST13HR_Pos (0UL)
7312 #define CCU6_PISEL2_IST13HR_Msk (0x3UL)
7313 #define CCU6_PISEL2_ISCNT12_Pos (2UL)
7314 #define CCU6_PISEL2_ISCNT12_Msk (0xcUL)
7315 #define CCU6_PISEL2_ISCNT13_Pos (4UL)
7316 #define CCU6_PISEL2_ISCNT13_Msk (0x30UL)
7317 #define CCU6_PISEL2_T12EXT_Pos (6UL)
7318 #define CCU6_PISEL2_T12EXT_Msk (0x40UL)
7319 #define CCU6_PISEL2_T13EXT_Pos (7UL)
7320 #define CCU6_PISEL2_T13EXT_Msk (0x80UL)
7321 /* ========================================================= PSLR ========================================================== */
7322 #define CCU6_PSLR_PSL_Pos (0UL)
7323 #define CCU6_PSLR_PSL_Msk (0x3fUL)
7324 #define CCU6_PSLR_PSL63_Pos (7UL)
7325 #define CCU6_PSLR_PSL63_Msk (0x80UL)
7326 /* ========================================================== T12 ========================================================== */
7327 #define CCU6_T12_T12CV_Pos (0UL)
7328 #define CCU6_T12_T12CV_Msk (0xffffUL)
7329 /* ======================================================== T12DTC ========================================================= */
7330 #define CCU6_T12DTC_DTM_Pos (0UL)
7331 #define CCU6_T12DTC_DTM_Msk (0xffUL)
7332 #define CCU6_T12DTC_DTE0_Pos (8UL)
7333 #define CCU6_T12DTC_DTE0_Msk (0x100UL)
7334 #define CCU6_T12DTC_DTE1_Pos (9UL)
7335 #define CCU6_T12DTC_DTE1_Msk (0x200UL)
7336 #define CCU6_T12DTC_DTE2_Pos (10UL)
7337 #define CCU6_T12DTC_DTE2_Msk (0x400UL)
7338 #define CCU6_T12DTC_DTR0_Pos (12UL)
7339 #define CCU6_T12DTC_DTR0_Msk (0x1000UL)
7340 #define CCU6_T12DTC_DTR1_Pos (13UL)
7341 #define CCU6_T12DTC_DTR1_Msk (0x2000UL)
7342 #define CCU6_T12DTC_DTR2_Pos (14UL)
7343 #define CCU6_T12DTC_DTR2_Msk (0x4000UL)
7344 /* ======================================================== T12MSEL ======================================================== */
7345 #define CCU6_T12MSEL_MSEL60_Pos (0UL)
7346 #define CCU6_T12MSEL_MSEL60_Msk (0xfUL)
7347 #define CCU6_T12MSEL_MSEL61_Pos (4UL)
7348 #define CCU6_T12MSEL_MSEL61_Msk (0xf0UL)
7349 #define CCU6_T12MSEL_MSEL62_Pos (8UL)
7350 #define CCU6_T12MSEL_MSEL62_Msk (0xf00UL)
7351 #define CCU6_T12MSEL_HSYNC_Pos (12UL)
7352 #define CCU6_T12MSEL_HSYNC_Msk (0x7000UL)
7353 #define CCU6_T12MSEL_DBYP_Pos (15UL)
7354 #define CCU6_T12MSEL_DBYP_Msk (0x8000UL)
7355 /* ========================================================= T12PR ========================================================= */
7356 #define CCU6_T12PR_T12PV_Pos (0UL)
7357 #define CCU6_T12PR_T12PV_Msk (0xffffUL)
7358 /* ========================================================== T13 ========================================================== */
7359 #define CCU6_T13_T13CV_Pos (0UL)
7360 #define CCU6_T13_T13CV_Msk (0xffffUL)
7361 /* ========================================================= T13PR ========================================================= */
7362 #define CCU6_T13PR_T13PV_Pos (0UL)
7363 #define CCU6_T13PR_T13PV_Msk (0xffffUL)
7364 /* ========================================================= TCTR0 ========================================================= */
7365 #define CCU6_TCTR0_T12CLK_Pos (0UL)
7366 #define CCU6_TCTR0_T12CLK_Msk (0x7UL)
7367 #define CCU6_TCTR0_T12PRE_Pos (3UL)
7368 #define CCU6_TCTR0_T12PRE_Msk (0x8UL)
7369 #define CCU6_TCTR0_T12R_Pos (4UL)
7370 #define CCU6_TCTR0_T12R_Msk (0x10UL)
7371 #define CCU6_TCTR0_STE12_Pos (5UL)
7372 #define CCU6_TCTR0_STE12_Msk (0x20UL)
7373 #define CCU6_TCTR0_CDIR_Pos (6UL)
7374 #define CCU6_TCTR0_CDIR_Msk (0x40UL)
7375 #define CCU6_TCTR0_CTM_Pos (7UL)
7376 #define CCU6_TCTR0_CTM_Msk (0x80UL)
7377 #define CCU6_TCTR0_T13CLK_Pos (8UL)
7378 #define CCU6_TCTR0_T13CLK_Msk (0x700UL)
7379 #define CCU6_TCTR0_T13PRE_Pos (11UL)
7380 #define CCU6_TCTR0_T13PRE_Msk (0x800UL)
7381 #define CCU6_TCTR0_T13R_Pos (12UL)
7382 #define CCU6_TCTR0_T13R_Msk (0x1000UL)
7383 #define CCU6_TCTR0_STE13_Pos (13UL)
7384 #define CCU6_TCTR0_STE13_Msk (0x2000UL)
7385 /* ========================================================= TCTR2 ========================================================= */
7386 #define CCU6_TCTR2_T12SSC_Pos (0UL)
7387 #define CCU6_TCTR2_T12SSC_Msk (0x1UL)
7388 #define CCU6_TCTR2_T13SSC_Pos (1UL)
7389 #define CCU6_TCTR2_T13SSC_Msk (0x2UL)
7390 #define CCU6_TCTR2_T13TEC_Pos (2UL)
7391 #define CCU6_TCTR2_T13TEC_Msk (0x1cUL)
7392 #define CCU6_TCTR2_T13TED_Pos (5UL)
7393 #define CCU6_TCTR2_T13TED_Msk (0x60UL)
7394 #define CCU6_TCTR2_T12RSEL_Pos (8UL)
7395 #define CCU6_TCTR2_T12RSEL_Msk (0x300UL)
7396 #define CCU6_TCTR2_T13RSEL_Pos (10UL)
7397 #define CCU6_TCTR2_T13RSEL_Msk (0xc00UL)
7398 /* ========================================================= TCTR4 ========================================================= */
7399 #define CCU6_TCTR4_T12RR_Pos (0UL)
7400 #define CCU6_TCTR4_T12RR_Msk (0x1UL)
7401 #define CCU6_TCTR4_T12RS_Pos (1UL)
7402 #define CCU6_TCTR4_T12RS_Msk (0x2UL)
7403 #define CCU6_TCTR4_T12RES_Pos (2UL)
7404 #define CCU6_TCTR4_T12RES_Msk (0x4UL)
7405 #define CCU6_TCTR4_DTRES_Pos (3UL)
7406 #define CCU6_TCTR4_DTRES_Msk (0x8UL)
7407 #define CCU6_TCTR4_T12CNT_Pos (5UL)
7408 #define CCU6_TCTR4_T12CNT_Msk (0x20UL)
7409 #define CCU6_TCTR4_T12STR_Pos (6UL)
7410 #define CCU6_TCTR4_T12STR_Msk (0x40UL)
7411 #define CCU6_TCTR4_T12STD_Pos (7UL)
7412 #define CCU6_TCTR4_T12STD_Msk (0x80UL)
7413 #define CCU6_TCTR4_T13RR_Pos (8UL)
7414 #define CCU6_TCTR4_T13RR_Msk (0x100UL)
7415 #define CCU6_TCTR4_T13RS_Pos (9UL)
7416 #define CCU6_TCTR4_T13RS_Msk (0x200UL)
7417 #define CCU6_TCTR4_T13RES_Pos (10UL)
7418 #define CCU6_TCTR4_T13RES_Msk (0x400UL)
7419 #define CCU6_TCTR4_T13CNT_Pos (13UL)
7420 #define CCU6_TCTR4_T13CNT_Msk (0x2000UL)
7421 #define CCU6_TCTR4_T13STR_Pos (14UL)
7422 #define CCU6_TCTR4_T13STR_Msk (0x4000UL)
7423 #define CCU6_TCTR4_T13STD_Pos (15UL)
7424 #define CCU6_TCTR4_T13STD_Msk (0x8000UL)
7425 /* ======================================================== TRPCTR ========================================================= */
7426 #define CCU6_TRPCTR_TRPM0_Pos (0UL)
7427 #define CCU6_TRPCTR_TRPM0_Msk (0x1UL)
7428 #define CCU6_TRPCTR_TRPM1_Pos (1UL)
7429 #define CCU6_TRPCTR_TRPM1_Msk (0x2UL)
7430 #define CCU6_TRPCTR_TRPM2_Pos (2UL)
7431 #define CCU6_TRPCTR_TRPM2_Msk (0x4UL)
7432 #define CCU6_TRPCTR_TRPEN_Pos (8UL)
7433 #define CCU6_TRPCTR_TRPEN_Msk (0x3f00UL)
7434 #define CCU6_TRPCTR_TRPEN13_Pos (14UL)
7435 #define CCU6_TRPCTR_TRPEN13_Msk (0x4000UL)
7436 #define CCU6_TRPCTR_TRPPEN_Pos (15UL)
7437 #define CCU6_TRPCTR_TRPPEN_Msk (0x8000UL)
7440 /* =========================================================================================================================== */
7441 /* ================ CPU ================ */
7442 /* =========================================================================================================================== */
7443 
7444 /* ========================================================= AFSR ========================================================== */
7445 #define CPU_AFSR_CP0_Pos (0UL)
7446 #define CPU_AFSR_CP0_Msk (0x3UL)
7447 #define CPU_AFSR_CP1_Pos (2UL)
7448 #define CPU_AFSR_CP1_Msk (0xcUL)
7449 #define CPU_AFSR_CP2_Pos (4UL)
7450 #define CPU_AFSR_CP2_Msk (0x30UL)
7451 #define CPU_AFSR_CP3_Pos (6UL)
7452 #define CPU_AFSR_CP3_Msk (0xc0UL)
7453 #define CPU_AFSR_CP4_Pos (8UL)
7454 #define CPU_AFSR_CP4_Msk (0x300UL)
7455 #define CPU_AFSR_CP5_Pos (10UL)
7456 #define CPU_AFSR_CP5_Msk (0xc00UL)
7457 #define CPU_AFSR_CP6_Pos (12UL)
7458 #define CPU_AFSR_CP6_Msk (0x3000UL)
7459 #define CPU_AFSR_CP7_Pos (14UL)
7460 #define CPU_AFSR_CP7_Msk (0xc000UL)
7461 #define CPU_AFSR_CP10_Pos (20UL)
7462 #define CPU_AFSR_CP10_Msk (0x300000UL)
7463 #define CPU_AFSR_CP11_Pos (22UL)
7464 #define CPU_AFSR_CP11_Msk (0xc00000UL)
7465 /* ========================================================= AIRCR ========================================================= */
7466 #define CPU_AIRCR_VECTKEY_Pos (16UL)
7467 #define CPU_AIRCR_VECTKEY_Msk (0xffff0000UL)
7468 #define CPU_AIRCR_ENDIANNESS_Pos (15UL)
7469 #define CPU_AIRCR_ENDIANNESS_Msk (0x8000UL)
7470 #define CPU_AIRCR_PRIGROUP_Pos (8UL)
7471 #define CPU_AIRCR_PRIGROUP_Msk (0x700UL)
7472 #define CPU_AIRCR_SYSRESETREQ_Pos (2UL)
7473 #define CPU_AIRCR_SYSRESETREQ_Msk (0x4UL)
7474 #define CPU_AIRCR_VECTCLRACTIVE_Pos (1UL)
7475 #define CPU_AIRCR_VECTCLRACTIVE_Msk (0x2UL)
7476 #define CPU_AIRCR_VECTRESET_Pos (0UL)
7477 #define CPU_AIRCR_VECTRESET_Msk (0x1UL)
7478 /* ========================================================= BFAR ========================================================== */
7479 #define CPU_BFAR_ADDRESS_Pos (0UL)
7480 #define CPU_BFAR_ADDRESS_Msk (0xffffffffUL)
7481 /* ========================================================== CCR ========================================================== */
7482 #define CPU_CCR_STKALIGN_Pos (9UL)
7483 #define CPU_CCR_STKALIGN_Msk (0x200UL)
7484 #define CPU_CCR_BFHFMIGN_Pos (8UL)
7485 #define CPU_CCR_BFHFMIGN_Msk (0x100UL)
7486 #define CPU_CCR_DIV_0_TRP_Pos (4UL)
7487 #define CPU_CCR_DIV_0_TRP_Msk (0x10UL)
7488 #define CPU_CCR_UNALIGN_TRP_Pos (3UL)
7489 #define CPU_CCR_UNALIGN_TRP_Msk (0x8UL)
7490 #define CPU_CCR_USERSETMPEND_Pos (1UL)
7491 #define CPU_CCR_USERSETMPEND_Msk (0x2UL)
7492 #define CPU_CCR_NONBASETHRDENA_Pos (0UL)
7493 #define CPU_CCR_NONBASETHRDENA_Msk (0x1UL)
7494 /* ========================================================= CFSR ========================================================== */
7495 #define CPU_CFSR_DIVBYZERO_Pos (25UL)
7496 #define CPU_CFSR_DIVBYZERO_Msk (0x2000000UL)
7497 #define CPU_CFSR_UNALIGNED_Pos (24UL)
7498 #define CPU_CFSR_UNALIGNED_Msk (0x1000000UL)
7499 #define CPU_CFSR_NOCP_Pos (19UL)
7500 #define CPU_CFSR_NOCP_Msk (0x80000UL)
7501 #define CPU_CFSR_INVPC_Pos (18UL)
7502 #define CPU_CFSR_INVPC_Msk (0x40000UL)
7503 #define CPU_CFSR_INVSTATE_Pos (17UL)
7504 #define CPU_CFSR_INVSTATE_Msk (0x20000UL)
7505 #define CPU_CFSR_UNDEFINSTR_Pos (16UL)
7506 #define CPU_CFSR_UNDEFINSTR_Msk (0x10000UL)
7507 #define CPU_CFSR_BFARVALID_Pos (15UL)
7508 #define CPU_CFSR_BFARVALID_Msk (0x8000UL)
7509 #define CPU_CFSR_STKERR_Pos (12UL)
7510 #define CPU_CFSR_STKERR_Msk (0x1000UL)
7511 #define CPU_CFSR_UNSTKERR_Pos (11UL)
7512 #define CPU_CFSR_UNSTKERR_Msk (0x800UL)
7513 #define CPU_CFSR_IMPRECISERR_Pos (10UL)
7514 #define CPU_CFSR_IMPRECISERR_Msk (0x400UL)
7515 #define CPU_CFSR_PRECISERR_Pos (9UL)
7516 #define CPU_CFSR_PRECISERR_Msk (0x200UL)
7517 #define CPU_CFSR_IBUSERR_Pos (8UL)
7518 #define CPU_CFSR_IBUSERR_Msk (0x100UL)
7519 #define CPU_CFSR_MMARVALID_Pos (7UL)
7520 #define CPU_CFSR_MMARVALID_Msk (0x80UL)
7521 #define CPU_CFSR_MSTERR_Pos (4UL)
7522 #define CPU_CFSR_MSTERR_Msk (0x10UL)
7523 #define CPU_CFSR_MUNSTKERR_Pos (3UL)
7524 #define CPU_CFSR_MUNSTKERR_Msk (0x8UL)
7525 #define CPU_CFSR_DACCVIOL_Pos (1UL)
7526 #define CPU_CFSR_DACCVIOL_Msk (0x2UL)
7527 #define CPU_CFSR_IACCVIOL_Pos (0UL)
7528 #define CPU_CFSR_IACCVIOL_Msk (0x1UL)
7529 /* ========================================================= CPUID ========================================================= */
7530 #define CPU_CPUID_IMPLEMENTER_Pos (24UL)
7531 #define CPU_CPUID_IMPLEMENTER_Msk (0xff000000UL)
7532 #define CPU_CPUID_VARIANT_Pos (20UL)
7533 #define CPU_CPUID_VARIANT_Msk (0xf00000UL)
7534 #define CPU_CPUID_ARCHITECTURE_Pos (16UL)
7535 #define CPU_CPUID_ARCHITECTURE_Msk (0xf0000UL)
7536 #define CPU_CPUID_PARTNO_Pos (4UL)
7537 #define CPU_CPUID_PARTNO_Msk (0xfff0UL)
7538 #define CPU_CPUID_REVISION_Pos (0UL)
7539 #define CPU_CPUID_REVISION_Msk (0xfUL)
7540 /* ========================================================= DFSR ========================================================== */
7541 #define CPU_DFSR_EXTERNAL_Pos (4UL)
7542 #define CPU_DFSR_EXTERNAL_Msk (0x10UL)
7543 #define CPU_DFSR_VCATCH_Pos (3UL)
7544 #define CPU_DFSR_VCATCH_Msk (0x8UL)
7545 #define CPU_DFSR_DWTTRAP_Pos (2UL)
7546 #define CPU_DFSR_DWTTRAP_Msk (0x4UL)
7547 #define CPU_DFSR_BKPT_Pos (1UL)
7548 #define CPU_DFSR_BKPT_Msk (0x2UL)
7549 #define CPU_DFSR_HALTED_Pos (0UL)
7550 #define CPU_DFSR_HALTED_Msk (0x1UL)
7551 /* ========================================================= HFSR ========================================================== */
7552 #define CPU_HFSR_DEBUGEVT_Pos (31UL)
7553 #define CPU_HFSR_DEBUGEVT_Msk (0x80000000UL)
7554 #define CPU_HFSR_FORCED_Pos (30UL)
7555 #define CPU_HFSR_FORCED_Msk (0x40000000UL)
7556 #define CPU_HFSR_VECTTBL_Pos (1UL)
7557 #define CPU_HFSR_VECTTBL_Msk (0x2UL)
7558 /* ========================================================= ICSR ========================================================== */
7559 #define CPU_ICSR_NMIPENDSET_Pos (31UL)
7560 #define CPU_ICSR_NMIPENDSET_Msk (0x80000000UL)
7561 #define CPU_ICSR_PENDSVSET_Pos (28UL)
7562 #define CPU_ICSR_PENDSVSET_Msk (0x10000000UL)
7563 #define CPU_ICSR_PENDSVCLR_Pos (27UL)
7564 #define CPU_ICSR_PENDSVCLR_Msk (0x8000000UL)
7565 #define CPU_ICSR_PENDSTSET_Pos (26UL)
7566 #define CPU_ICSR_PENDSTSET_Msk (0x4000000UL)
7567 #define CPU_ICSR_PENDSTCLR_Pos (25UL)
7568 #define CPU_ICSR_PENDSTCLR_Msk (0x2000000UL)
7569 #define CPU_ICSR_ISRPREEMPT_Pos (23UL)
7570 #define CPU_ICSR_ISRPREEMPT_Msk (0x800000UL)
7571 #define CPU_ICSR_ISRPENDING_Pos (22UL)
7572 #define CPU_ICSR_ISRPENDING_Msk (0x400000UL)
7573 #define CPU_ICSR_VECTPENDING_Pos (12UL)
7574 #define CPU_ICSR_VECTPENDING_Msk (0x1ff000UL)
7575 #define CPU_ICSR_RETTOBASE_Pos (11UL)
7576 #define CPU_ICSR_RETTOBASE_Msk (0x800UL)
7577 #define CPU_ICSR_VECTACTIVE_Pos (0UL)
7578 #define CPU_ICSR_VECTACTIVE_Msk (0x1ffUL)
7579 /* ========================================================== ICT ========================================================== */
7580 #define CPU_ICT_INTLINESNUM_Pos (0UL)
7581 #define CPU_ICT_INTLINESNUM_Msk (0x1fUL)
7582 /* ========================================================= MMFAR ========================================================= */
7583 #define CPU_MMFAR_ADDRESS_Pos (0UL)
7584 #define CPU_MMFAR_ADDRESS_Msk (0xffffffffUL)
7585 /* ====================================================== NVIC_IABR0 ======================================================= */
7586 #define CPU_NVIC_IABR0_Int_DMA_Pos (15UL)
7587 #define CPU_NVIC_IABR0_Int_DMA_Msk (0x8000UL)
7588 #define CPU_NVIC_IABR0_Int_BDRV_Pos (14UL)
7589 #define CPU_NVIC_IABR0_Int_BDRV_Msk (0x4000UL)
7590 #define CPU_NVIC_IABR0_Int_EXINT1_Pos (13UL)
7591 #define CPU_NVIC_IABR0_Int_EXINT1_Msk (0x2000UL)
7592 #define CPU_NVIC_IABR0_Int_EXINT0_Pos (12UL)
7593 #define CPU_NVIC_IABR0_Int_EXINT0_Msk (0x1000UL)
7594 #define CPU_NVIC_IABR0_Int_UART2_Pos (11UL)
7595 #define CPU_NVIC_IABR0_Int_UART2_Msk (0x800UL)
7596 #define CPU_NVIC_IABR0_Int_UART1_Pos (10UL)
7597 #define CPU_NVIC_IABR0_Int_UART1_Msk (0x400UL)
7598 #define CPU_NVIC_IABR0_Int_SSC2_Pos (9UL)
7599 #define CPU_NVIC_IABR0_Int_SSC2_Msk (0x200UL)
7600 #define CPU_NVIC_IABR0_Int_SSC1_Pos (8UL)
7601 #define CPU_NVIC_IABR0_Int_SSC1_Msk (0x100UL)
7602 #define CPU_NVIC_IABR0_Int_CCU6SR3_Pos (7UL)
7603 #define CPU_NVIC_IABR0_Int_CCU6SR3_Msk (0x80UL)
7604 #define CPU_NVIC_IABR0_Int_CCU6SR2_Pos (6UL)
7605 #define CPU_NVIC_IABR0_Int_CCU6SR2_Msk (0x40UL)
7606 #define CPU_NVIC_IABR0_Int_CCU6SR1_Pos (5UL)
7607 #define CPU_NVIC_IABR0_Int_CCU6SR1_Msk (0x20UL)
7608 #define CPU_NVIC_IABR0_Int_CCU6SR0_Pos (4UL)
7609 #define CPU_NVIC_IABR0_Int_CCU6SR0_Msk (0x10UL)
7610 #define CPU_NVIC_IABR0_Int_ADC1_Pos (3UL)
7611 #define CPU_NVIC_IABR0_Int_ADC1_Msk (0x8UL)
7612 #define CPU_NVIC_IABR0_Int_ADC2_Pos (2UL)
7613 #define CPU_NVIC_IABR0_Int_ADC2_Msk (0x4UL)
7614 #define CPU_NVIC_IABR0_Int_GPT2_Pos (1UL)
7615 #define CPU_NVIC_IABR0_Int_GPT2_Msk (0x2UL)
7616 #define CPU_NVIC_IABR0_Int_GPT1_Pos (0UL)
7617 #define CPU_NVIC_IABR0_Int_GPT1_Msk (0x1UL)
7618 /* ====================================================== NVIC_ICER0 ======================================================= */
7619 #define CPU_NVIC_ICER0_Int_DMA_Pos (15UL)
7620 #define CPU_NVIC_ICER0_Int_DMA_Msk (0x8000UL)
7621 #define CPU_NVIC_ICER0_Int_BDRV_Pos (14UL)
7622 #define CPU_NVIC_ICER0_Int_BDRV_Msk (0x4000UL)
7623 #define CPU_NVIC_ICER0_Int_EXINT1_Pos (13UL)
7624 #define CPU_NVIC_ICER0_Int_EXINT1_Msk (0x2000UL)
7625 #define CPU_NVIC_ICER0_Int_EXINT0_Pos (12UL)
7626 #define CPU_NVIC_ICER0_Int_EXINT0_Msk (0x1000UL)
7627 #define CPU_NVIC_ICER0_Int_UART2_Pos (11UL)
7628 #define CPU_NVIC_ICER0_Int_UART2_Msk (0x800UL)
7629 #define CPU_NVIC_ICER0_Int_UART1_Pos (10UL)
7630 #define CPU_NVIC_ICER0_Int_UART1_Msk (0x400UL)
7631 #define CPU_NVIC_ICER0_Int_SSC2_Pos (9UL)
7632 #define CPU_NVIC_ICER0_Int_SSC2_Msk (0x200UL)
7633 #define CPU_NVIC_ICER0_Int_SSC1_Pos (8UL)
7634 #define CPU_NVIC_ICER0_Int_SSC1_Msk (0x100UL)
7635 #define CPU_NVIC_ICER0_Int_CCU6SR3_Pos (7UL)
7636 #define CPU_NVIC_ICER0_Int_CCU6SR3_Msk (0x80UL)
7637 #define CPU_NVIC_ICER0_Int_CCU6SR2_Pos (6UL)
7638 #define CPU_NVIC_ICER0_Int_CCU6SR2_Msk (0x40UL)
7639 #define CPU_NVIC_ICER0_Int_CCU6SR1_Pos (5UL)
7640 #define CPU_NVIC_ICER0_Int_CCU6SR1_Msk (0x20UL)
7641 #define CPU_NVIC_ICER0_Int_CCU6SR0_Pos (4UL)
7642 #define CPU_NVIC_ICER0_Int_CCU6SR0_Msk (0x10UL)
7643 #define CPU_NVIC_ICER0_Int_ADC1_Pos (3UL)
7644 #define CPU_NVIC_ICER0_Int_ADC1_Msk (0x8UL)
7645 #define CPU_NVIC_ICER0_Int_ADC2_Pos (2UL)
7646 #define CPU_NVIC_ICER0_Int_ADC2_Msk (0x4UL)
7647 #define CPU_NVIC_ICER0_Int_GPT2_Pos (1UL)
7648 #define CPU_NVIC_ICER0_Int_GPT2_Msk (0x2UL)
7649 #define CPU_NVIC_ICER0_Int_GPT1_Pos (0UL)
7650 #define CPU_NVIC_ICER0_Int_GPT1_Msk (0x1UL)
7651 /* ====================================================== NVIC_ICPR0 ======================================================= */
7652 #define CPU_NVIC_ICPR0_Int_DMA_Pos (15UL)
7653 #define CPU_NVIC_ICPR0_Int_DMA_Msk (0x8000UL)
7654 #define CPU_NVIC_ICPR0_Int_BDRV_Pos (14UL)
7655 #define CPU_NVIC_ICPR0_Int_BDRV_Msk (0x4000UL)
7656 #define CPU_NVIC_ICPR0_Int_EXINT1_Pos (13UL)
7657 #define CPU_NVIC_ICPR0_Int_EXINT1_Msk (0x2000UL)
7658 #define CPU_NVIC_ICPR0_Int_EXINT0_Pos (12UL)
7659 #define CPU_NVIC_ICPR0_Int_EXINT0_Msk (0x1000UL)
7660 #define CPU_NVIC_ICPR0_Int_UART2_Pos (11UL)
7661 #define CPU_NVIC_ICPR0_Int_UART2_Msk (0x800UL)
7662 #define CPU_NVIC_ICPR0_Int_UART1_Pos (10UL)
7663 #define CPU_NVIC_ICPR0_Int_UART1_Msk (0x400UL)
7664 #define CPU_NVIC_ICPR0_Int_SSC2_Pos (9UL)
7665 #define CPU_NVIC_ICPR0_Int_SSC2_Msk (0x200UL)
7666 #define CPU_NVIC_ICPR0_Int_SSC1_Pos (8UL)
7667 #define CPU_NVIC_ICPR0_Int_SSC1_Msk (0x100UL)
7668 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Pos (7UL)
7669 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Msk (0x80UL)
7670 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Pos (6UL)
7671 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Msk (0x40UL)
7672 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Pos (5UL)
7673 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Msk (0x20UL)
7674 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Pos (4UL)
7675 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Msk (0x10UL)
7676 #define CPU_NVIC_ICPR0_Int_ADC1_Pos (3UL)
7677 #define CPU_NVIC_ICPR0_Int_ADC1_Msk (0x8UL)
7678 #define CPU_NVIC_ICPR0_Int_ADC2_Pos (2UL)
7679 #define CPU_NVIC_ICPR0_Int_ADC2_Msk (0x4UL)
7680 #define CPU_NVIC_ICPR0_Int_GPT2_Pos (1UL)
7681 #define CPU_NVIC_ICPR0_Int_GPT2_Msk (0x2UL)
7682 #define CPU_NVIC_ICPR0_Int_GPT1_Pos (0UL)
7683 #define CPU_NVIC_ICPR0_Int_GPT1_Msk (0x1UL)
7684 /* ======================================================= NVIC_IPR0 ======================================================= */
7685 #define CPU_NVIC_IPR0_PRI_ADC1_Pos (24UL)
7686 #define CPU_NVIC_IPR0_PRI_ADC1_Msk (0xff000000UL)
7687 #define CPU_NVIC_IPR0_PRI_ADC2_Pos (16UL)
7688 #define CPU_NVIC_IPR0_PRI_ADC2_Msk (0xff0000UL)
7689 #define CPU_NVIC_IPR0_PRI_GPT2_Pos (8UL)
7690 #define CPU_NVIC_IPR0_PRI_GPT2_Msk (0xff00UL)
7691 #define CPU_NVIC_IPR0_PRI_GPT1_Pos (0UL)
7692 #define CPU_NVIC_IPR0_PRI_GPT1_Msk (0xffUL)
7693 /* ======================================================= NVIC_IPR1 ======================================================= */
7694 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Pos (24UL)
7695 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Msk (0xff000000UL)
7696 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Pos (16UL)
7697 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Msk (0xff0000UL)
7698 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Pos (8UL)
7699 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Msk (0xff00UL)
7700 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Pos (0UL)
7701 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Msk (0xffUL)
7702 /* ======================================================= NVIC_IPR2 ======================================================= */
7703 #define CPU_NVIC_IPR2_PRI_UART2_Pos (24UL)
7704 #define CPU_NVIC_IPR2_PRI_UART2_Msk (0xff000000UL)
7705 #define CPU_NVIC_IPR2_PRI_UART1_Pos (16UL)
7706 #define CPU_NVIC_IPR2_PRI_UART1_Msk (0xff0000UL)
7707 #define CPU_NVIC_IPR2_PRI_SSC2_Pos (8UL)
7708 #define CPU_NVIC_IPR2_PRI_SSC2_Msk (0xff00UL)
7709 #define CPU_NVIC_IPR2_PRI_SSC1_Pos (0UL)
7710 #define CPU_NVIC_IPR2_PRI_SSC1_Msk (0xffUL)
7711 /* ======================================================= NVIC_IPR3 ======================================================= */
7712 #define CPU_NVIC_IPR3_PRI_DMA_Pos (24UL)
7713 #define CPU_NVIC_IPR3_PRI_DMA_Msk (0xff000000UL)
7714 #define CPU_NVIC_IPR3_PRI_BDRV_Pos (16UL)
7715 #define CPU_NVIC_IPR3_PRI_BDRV_Msk (0xff0000UL)
7716 #define CPU_NVIC_IPR3_PRI_EXINT1_Pos (8UL)
7717 #define CPU_NVIC_IPR3_PRI_EXINT1_Msk (0xff00UL)
7718 #define CPU_NVIC_IPR3_PRI_EXINT0_Pos (0UL)
7719 #define CPU_NVIC_IPR3_PRI_EXINT0_Msk (0xffUL)
7720 /* ====================================================== NVIC_ISER0 ======================================================= */
7721 #define CPU_NVIC_ISER0_Int_DMA_Pos (15UL)
7722 #define CPU_NVIC_ISER0_Int_DMA_Msk (0x8000UL)
7723 #define CPU_NVIC_ISER0_Int_BDRV_Pos (14UL)
7724 #define CPU_NVIC_ISER0_Int_BDRV_Msk (0x4000UL)
7725 #define CPU_NVIC_ISER0_Int_EXINT1_Pos (13UL)
7726 #define CPU_NVIC_ISER0_Int_EXINT1_Msk (0x2000UL)
7727 #define CPU_NVIC_ISER0_Int_EXINT0_Pos (12UL)
7728 #define CPU_NVIC_ISER0_Int_EXINT0_Msk (0x1000UL)
7729 #define CPU_NVIC_ISER0_Int_UART2_Pos (11UL)
7730 #define CPU_NVIC_ISER0_Int_UART2_Msk (0x800UL)
7731 #define CPU_NVIC_ISER0_Int_UART1_Pos (10UL)
7732 #define CPU_NVIC_ISER0_Int_UART1_Msk (0x400UL)
7733 #define CPU_NVIC_ISER0_Int_SSC2_Pos (9UL)
7734 #define CPU_NVIC_ISER0_Int_SSC2_Msk (0x200UL)
7735 #define CPU_NVIC_ISER0_Int_SSC1_Pos (8UL)
7736 #define CPU_NVIC_ISER0_Int_SSC1_Msk (0x100UL)
7737 #define CPU_NVIC_ISER0_Int_CCU6SR3_Pos (7UL)
7738 #define CPU_NVIC_ISER0_Int_CCU6SR3_Msk (0x80UL)
7739 #define CPU_NVIC_ISER0_Int_CCU6SR2_Pos (6UL)
7740 #define CPU_NVIC_ISER0_Int_CCU6SR2_Msk (0x40UL)
7741 #define CPU_NVIC_ISER0_Int_CCU6SR1_Pos (5UL)
7742 #define CPU_NVIC_ISER0_Int_CCU6SR1_Msk (0x20UL)
7743 #define CPU_NVIC_ISER0_Int_CCU6SR0_Pos (4UL)
7744 #define CPU_NVIC_ISER0_Int_CCU6SR0_Msk (0x10UL)
7745 #define CPU_NVIC_ISER0_Int_ADC1_Pos (3UL)
7746 #define CPU_NVIC_ISER0_Int_ADC1_Msk (0x8UL)
7747 #define CPU_NVIC_ISER0_Int_ADC2_Pos (2UL)
7748 #define CPU_NVIC_ISER0_Int_ADC2_Msk (0x4UL)
7749 #define CPU_NVIC_ISER0_Int_GPT2_Pos (1UL)
7750 #define CPU_NVIC_ISER0_Int_GPT2_Msk (0x2UL)
7751 #define CPU_NVIC_ISER0_Int_GPT1_Pos (0UL)
7752 #define CPU_NVIC_ISER0_Int_GPT1_Msk (0x1UL)
7753 /* ====================================================== NVIC_ISPR0 ======================================================= */
7754 #define CPU_NVIC_ISPR0_Int_DMA_Pos (15UL)
7755 #define CPU_NVIC_ISPR0_Int_DMA_Msk (0x8000UL)
7756 #define CPU_NVIC_ISPR0_Int_BDRV_Pos (14UL)
7757 #define CPU_NVIC_ISPR0_Int_BDRV_Msk (0x4000UL)
7758 #define CPU_NVIC_ISPR0_Int_EXINT1_Pos (13UL)
7759 #define CPU_NVIC_ISPR0_Int_EXINT1_Msk (0x2000UL)
7760 #define CPU_NVIC_ISPR0_Int_EXINT0_Pos (12UL)
7761 #define CPU_NVIC_ISPR0_Int_EXINT0_Msk (0x1000UL)
7762 #define CPU_NVIC_ISPR0_Int_UART2_Pos (11UL)
7763 #define CPU_NVIC_ISPR0_Int_UART2_Msk (0x800UL)
7764 #define CPU_NVIC_ISPR0_Int_UART1_Pos (10UL)
7765 #define CPU_NVIC_ISPR0_Int_UART1_Msk (0x400UL)
7766 #define CPU_NVIC_ISPR0_Int_SSC2_Pos (9UL)
7767 #define CPU_NVIC_ISPR0_Int_SSC2_Msk (0x200UL)
7768 #define CPU_NVIC_ISPR0_Int_SSC1_Pos (8UL)
7769 #define CPU_NVIC_ISPR0_Int_SSC1_Msk (0x100UL)
7770 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Pos (7UL)
7771 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Msk (0x80UL)
7772 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Pos (6UL)
7773 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Msk (0x40UL)
7774 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Pos (5UL)
7775 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Msk (0x20UL)
7776 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Pos (4UL)
7777 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Msk (0x10UL)
7778 #define CPU_NVIC_ISPR0_Int_ADC1_Pos (3UL)
7779 #define CPU_NVIC_ISPR0_Int_ADC1_Msk (0x8UL)
7780 #define CPU_NVIC_ISPR0_Int_ADC2_Pos (2UL)
7781 #define CPU_NVIC_ISPR0_Int_ADC2_Msk (0x4UL)
7782 #define CPU_NVIC_ISPR0_Int_GPT2_Pos (1UL)
7783 #define CPU_NVIC_ISPR0_Int_GPT2_Msk (0x2UL)
7784 #define CPU_NVIC_ISPR0_Int_GPT1_Pos (0UL)
7785 #define CPU_NVIC_ISPR0_Int_GPT1_Msk (0x1UL)
7786 /* ========================================================== SCR ========================================================== */
7787 #define CPU_SCR_SEVONPEND_Pos (4UL)
7788 #define CPU_SCR_SEVONPEND_Msk (0x10UL)
7789 #define CPU_SCR_SLEEPDEEP_Pos (2UL)
7790 #define CPU_SCR_SLEEPDEEP_Msk (0x4UL)
7791 #define CPU_SCR_SLEEPONEXIT_Pos (1UL)
7792 #define CPU_SCR_SLEEPONEXIT_Msk (0x2UL)
7793 /* ========================================================= SHCSR ========================================================= */
7794 #define CPU_SHCSR_USGFAULTENA_Pos (18UL)
7795 #define CPU_SHCSR_USGFAULTENA_Msk (0x40000UL)
7796 #define CPU_SHCSR_BUSFAULTENA_Pos (17UL)
7797 #define CPU_SHCSR_BUSFAULTENA_Msk (0x20000UL)
7798 #define CPU_SHCSR_MEMFAULTENA_Pos (16UL)
7799 #define CPU_SHCSR_MEMFAULTENA_Msk (0x10000UL)
7800 #define CPU_SHCSR_SVCALLPENDED_Pos (15UL)
7801 #define CPU_SHCSR_SVCALLPENDED_Msk (0x8000UL)
7802 #define CPU_SHCSR_BUSFAULTPENDED_Pos (14UL)
7803 #define CPU_SHCSR_BUSFAULTPENDED_Msk (0x4000UL)
7804 #define CPU_SHCSR_MEMFAULTPENDED_Pos (13UL)
7805 #define CPU_SHCSR_MEMFAULTPENDED_Msk (0x2000UL)
7806 #define CPU_SHCSR_USGFAULTPENDED_Pos (12UL)
7807 #define CPU_SHCSR_USGFAULTPENDED_Msk (0x1000UL)
7808 #define CPU_SHCSR_SYSTICKACT_Pos (11UL)
7809 #define CPU_SHCSR_SYSTICKACT_Msk (0x800UL)
7810 #define CPU_SHCSR_PENDSVACT_Pos (10UL)
7811 #define CPU_SHCSR_PENDSVACT_Msk (0x400UL)
7812 #define CPU_SHCSR_MONITORACT_Pos (8UL)
7813 #define CPU_SHCSR_MONITORACT_Msk (0x100UL)
7814 #define CPU_SHCSR_SVCALLACT_Pos (7UL)
7815 #define CPU_SHCSR_SVCALLACT_Msk (0x80UL)
7816 #define CPU_SHCSR_USGFAULTACT_Pos (3UL)
7817 #define CPU_SHCSR_USGFAULTACT_Msk (0x8UL)
7818 #define CPU_SHCSR_BUSFAULTACT_Pos (1UL)
7819 #define CPU_SHCSR_BUSFAULTACT_Msk (0x2UL)
7820 #define CPU_SHCSR_MEMFAULTACT_Pos (0UL)
7821 #define CPU_SHCSR_MEMFAULTACT_Msk (0x1UL)
7822 /* ========================================================= SHPR1 ========================================================= */
7823 #define CPU_SHPR1_PRI_7_Pos (24UL)
7824 #define CPU_SHPR1_PRI_7_Msk (0xff000000UL)
7825 #define CPU_SHPR1_PRI_6_Pos (16UL)
7826 #define CPU_SHPR1_PRI_6_Msk (0xff0000UL)
7827 #define CPU_SHPR1_PRI_5_Pos (8UL)
7828 #define CPU_SHPR1_PRI_5_Msk (0xff00UL)
7829 #define CPU_SHPR1_PRI_4_Pos (0UL)
7830 #define CPU_SHPR1_PRI_4_Msk (0xffUL)
7831 /* ========================================================= SHPR2 ========================================================= */
7832 #define CPU_SHPR2_PRI_11_Pos (24UL)
7833 #define CPU_SHPR2_PRI_11_Msk (0xff000000UL)
7834 #define CPU_SHPR2_PRI_10_Pos (16UL)
7835 #define CPU_SHPR2_PRI_10_Msk (0xff0000UL)
7836 #define CPU_SHPR2_PRI_9_Pos (8UL)
7837 #define CPU_SHPR2_PRI_9_Msk (0xff00UL)
7838 #define CPU_SHPR2_PRI_8_Pos (0UL)
7839 #define CPU_SHPR2_PRI_8_Msk (0xffUL)
7840 /* ========================================================= SHPR3 ========================================================= */
7841 #define CPU_SHPR3_PRI_15_Pos (24UL)
7842 #define CPU_SHPR3_PRI_15_Msk (0xff000000UL)
7843 #define CPU_SHPR3_PRI_14_Pos (16UL)
7844 #define CPU_SHPR3_PRI_14_Msk (0xff0000UL)
7845 #define CPU_SHPR3_PRI_13_Pos (8UL)
7846 #define CPU_SHPR3_PRI_13_Msk (0xff00UL)
7847 #define CPU_SHPR3_PRI_12_Pos (0UL)
7848 #define CPU_SHPR3_PRI_12_Msk (0xffUL)
7849 /* ====================================================== SYSTICK_CAL ====================================================== */
7850 #define CPU_SYSTICK_CAL_NOREF_Pos (31UL)
7851 #define CPU_SYSTICK_CAL_NOREF_Msk (0x80000000UL)
7852 #define CPU_SYSTICK_CAL_SKEW_Pos (30UL)
7853 #define CPU_SYSTICK_CAL_SKEW_Msk (0x40000000UL)
7854 #define CPU_SYSTICK_CAL_TENMS_Pos (0UL)
7855 #define CPU_SYSTICK_CAL_TENMS_Msk (0xffffffUL)
7856 /* ====================================================== SYSTICK_CS ======================================================= */
7857 #define CPU_SYSTICK_CS_COUNTFLAG_Pos (16UL)
7858 #define CPU_SYSTICK_CS_COUNTFLAG_Msk (0x10000UL)
7859 #define CPU_SYSTICK_CS_CLKSOURCE_Pos (2UL)
7860 #define CPU_SYSTICK_CS_CLKSOURCE_Msk (0x4UL)
7861 #define CPU_SYSTICK_CS_TICKINT_Pos (1UL)
7862 #define CPU_SYSTICK_CS_TICKINT_Msk (0x2UL)
7863 #define CPU_SYSTICK_CS_ENABLE_Pos (0UL)
7864 #define CPU_SYSTICK_CS_ENABLE_Msk (0x1UL)
7865 /* ====================================================== SYSTICK_CUR ====================================================== */
7866 #define CPU_SYSTICK_CUR_CURRENT_Pos (0UL)
7867 #define CPU_SYSTICK_CUR_CURRENT_Msk (0xffffffUL)
7868 /* ====================================================== SYSTICK_RL ======================================================= */
7869 #define CPU_SYSTICK_RL_RELOAD_Pos (0UL)
7870 #define CPU_SYSTICK_RL_RELOAD_Msk (0xffffffUL)
7871 /* ========================================================= VTOR ========================================================== */
7872 #define CPU_VTOR_TBLOFF_Pos (7UL)
7873 #define CPU_VTOR_TBLOFF_Msk (0xffffff80UL)
7876 /* =========================================================================================================================== */
7877 /* ================ DMA ================ */
7878 /* =========================================================================================================================== */
7879 
7880 /* =================================================== ALT_CTRL_BASE_PTR =================================================== */
7881 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Pos (0UL)
7882 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Msk (0xffffffffUL)
7883 /* ========================================================== CFG ========================================================== */
7884 #define DMA_CFG_CHN1_PROT_CTRL_Pos (5UL)
7885 #define DMA_CFG_CHN1_PROT_CTRL_Msk (0xe0UL)
7886 #define DMA_CFG_MASTER_ENABLE_Pos (0UL)
7887 #define DMA_CFG_MASTER_ENABLE_Msk (0x1UL)
7888 /* ==================================================== CHNL_ENABLE_CLR ==================================================== */
7889 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Pos (0UL)
7890 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Msk (0x3fffUL)
7891 /* ==================================================== CHNL_ENABLE_SET ==================================================== */
7892 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos (0UL)
7893 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk (0x3fffUL)
7894 /* =================================================== CHNL_PRI_ALT_CLR ==================================================== */
7895 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos (0UL)
7896 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk (0x3fffUL)
7897 /* =================================================== CHNL_PRI_ALT_SET ==================================================== */
7898 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos (0UL)
7899 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk (0x3fffUL)
7900 /* =================================================== CHNL_PRIORITY_CLR =================================================== */
7901 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Pos (0UL)
7902 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Msk (0x3fffUL)
7903 /* =================================================== CHNL_PRIORITY_SET =================================================== */
7904 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Pos (0UL)
7905 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Msk (0x3fffUL)
7906 /* =================================================== CHNL_REQ_MASK_CLR =================================================== */
7907 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Pos (0UL)
7908 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Msk (0x3fffUL)
7909 /* =================================================== CHNL_REQ_MASK_SET =================================================== */
7910 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Pos (0UL)
7911 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Msk (0x3fffUL)
7912 /* ==================================================== CHNL_SW_REQUEST ==================================================== */
7913 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos (0UL)
7914 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk (0x3fffUL)
7915 /* =================================================== CHNL_USEBURST_CLR =================================================== */
7916 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Pos (0UL)
7917 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Msk (0x3fffUL)
7918 /* =================================================== CHNL_USEBURST_SET =================================================== */
7919 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Pos (0UL)
7920 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Msk (0x3fffUL)
7921 /* ===================================================== CTRL_BASE_PTR ===================================================== */
7922 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos (9UL)
7923 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk (0xfffffe00UL)
7924 /* ======================================================== ERR_CLR ======================================================== */
7925 #define DMA_ERR_CLR_ERR_CLR_Pos (0UL)
7926 #define DMA_ERR_CLR_ERR_CLR_Msk (0x1UL)
7927 /* ======================================================== STATUS ========================================================= */
7928 #define DMA_STATUS_CHNLS_MINUS1_Pos (16UL)
7929 #define DMA_STATUS_CHNLS_MINUS1_Msk (0x1f0000UL)
7930 #define DMA_STATUS_STATE_Pos (4UL)
7931 #define DMA_STATUS_STATE_Msk (0xf0UL)
7932 #define DMA_STATUS_MASTER_ENABLE_Pos (0UL)
7933 #define DMA_STATUS_MASTER_ENABLE_Msk (0x1UL)
7934 /* =================================================== WAITONREQ_STATUS ==================================================== */
7935 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Pos (0UL)
7936 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Msk (0x3fffUL)
7939 /* =========================================================================================================================== */
7940 /* ================ GPT12E ================ */
7941 /* =========================================================================================================================== */
7942 
7943 /* ======================================================== CAPREL ========================================================= */
7944 #define GPT12E_CAPREL_CAPREL_Pos (0UL)
7945 #define GPT12E_CAPREL_CAPREL_Msk (0xffffUL)
7946 /* ========================================================== ID =========================================================== */
7947 #define GPT12E_ID_MOD_REV_Pos (0UL)
7948 #define GPT12E_ID_MOD_REV_Msk (0xffUL)
7949 #define GPT12E_ID_MOD_TYPE_Pos (8UL)
7950 #define GPT12E_ID_MOD_TYPE_Msk (0xff00UL)
7951 /* ========================================================= PISEL ========================================================= */
7952 #define GPT12E_PISEL_IST2IN_Pos (0UL)
7953 #define GPT12E_PISEL_IST2IN_Msk (0x1UL)
7954 #define GPT12E_PISEL_IST2EUD_Pos (1UL)
7955 #define GPT12E_PISEL_IST2EUD_Msk (0x2UL)
7956 #define GPT12E_PISEL_IST3IN_Pos (2UL)
7957 #define GPT12E_PISEL_IST3IN_Msk (0xcUL)
7958 #define GPT12E_PISEL_IST3EUD_Pos (4UL)
7959 #define GPT12E_PISEL_IST3EUD_Msk (0x30UL)
7960 #define GPT12E_PISEL_IST4IN_Pos (6UL)
7961 #define GPT12E_PISEL_IST4IN_Msk (0xc0UL)
7962 #define GPT12E_PISEL_IST4EUD_Pos (8UL)
7963 #define GPT12E_PISEL_IST4EUD_Msk (0x300UL)
7964 #define GPT12E_PISEL_IST5IN_Pos (10UL)
7965 #define GPT12E_PISEL_IST5IN_Msk (0x400UL)
7966 #define GPT12E_PISEL_IST5EUD_Pos (11UL)
7967 #define GPT12E_PISEL_IST5EUD_Msk (0x800UL)
7968 #define GPT12E_PISEL_IST6IN_Pos (12UL)
7969 #define GPT12E_PISEL_IST6IN_Msk (0x1000UL)
7970 #define GPT12E_PISEL_IST6EUD_Pos (13UL)
7971 #define GPT12E_PISEL_IST6EUD_Msk (0x2000UL)
7972 #define GPT12E_PISEL_ISCAPIN_Pos (14UL)
7973 #define GPT12E_PISEL_ISCAPIN_Msk (0xc000UL)
7974 /* ========================================================== T2 =========================================================== */
7975 #define GPT12E_T2_T2_Pos (0UL)
7976 #define GPT12E_T2_T2_Msk (0xffffUL)
7977 /* ========================================================= T2CON ========================================================= */
7978 #define GPT12E_T2CON_T2I_Pos (0UL)
7979 #define GPT12E_T2CON_T2I_Msk (0x7UL)
7980 #define GPT12E_T2CON_T2M_Pos (3UL)
7981 #define GPT12E_T2CON_T2M_Msk (0x38UL)
7982 #define GPT12E_T2CON_T2R_Pos (6UL)
7983 #define GPT12E_T2CON_T2R_Msk (0x40UL)
7984 #define GPT12E_T2CON_T2UD_Pos (7UL)
7985 #define GPT12E_T2CON_T2UD_Msk (0x80UL)
7986 #define GPT12E_T2CON_T2UDE_Pos (8UL)
7987 #define GPT12E_T2CON_T2UDE_Msk (0x100UL)
7988 #define GPT12E_T2CON_T2RC_Pos (9UL)
7989 #define GPT12E_T2CON_T2RC_Msk (0x200UL)
7990 #define GPT12E_T2CON_T2IRDIS_Pos (12UL)
7991 #define GPT12E_T2CON_T2IRDIS_Msk (0x1000UL)
7992 #define GPT12E_T2CON_T2EDGE_Pos (13UL)
7993 #define GPT12E_T2CON_T2EDGE_Msk (0x2000UL)
7994 #define GPT12E_T2CON_T2CHDIR_Pos (14UL)
7995 #define GPT12E_T2CON_T2CHDIR_Msk (0x4000UL)
7996 #define GPT12E_T2CON_T2RDIR_Pos (15UL)
7997 #define GPT12E_T2CON_T2RDIR_Msk (0x8000UL)
7998 /* ========================================================== T3 =========================================================== */
7999 #define GPT12E_T3_T3_Pos (0UL)
8000 #define GPT12E_T3_T3_Msk (0xffffUL)
8001 /* ========================================================= T3CON ========================================================= */
8002 #define GPT12E_T3CON_T3I_Pos (0UL)
8003 #define GPT12E_T3CON_T3I_Msk (0x7UL)
8004 #define GPT12E_T3CON_T3M_Pos (3UL)
8005 #define GPT12E_T3CON_T3M_Msk (0x38UL)
8006 #define GPT12E_T3CON_T3R_Pos (6UL)
8007 #define GPT12E_T3CON_T3R_Msk (0x40UL)
8008 #define GPT12E_T3CON_T3UD_Pos (7UL)
8009 #define GPT12E_T3CON_T3UD_Msk (0x80UL)
8010 #define GPT12E_T3CON_T3UDE_Pos (8UL)
8011 #define GPT12E_T3CON_T3UDE_Msk (0x100UL)
8012 #define GPT12E_T3CON_T3OE_Pos (9UL)
8013 #define GPT12E_T3CON_T3OE_Msk (0x200UL)
8014 #define GPT12E_T3CON_T3OTL_Pos (10UL)
8015 #define GPT12E_T3CON_T3OTL_Msk (0x400UL)
8016 #define GPT12E_T3CON_BPS1_Pos (11UL)
8017 #define GPT12E_T3CON_BPS1_Msk (0x1800UL)
8018 #define GPT12E_T3CON_T3EDGE_Pos (13UL)
8019 #define GPT12E_T3CON_T3EDGE_Msk (0x2000UL)
8020 #define GPT12E_T3CON_T3CHDIR_Pos (14UL)
8021 #define GPT12E_T3CON_T3CHDIR_Msk (0x4000UL)
8022 #define GPT12E_T3CON_T3RDIR_Pos (15UL)
8023 #define GPT12E_T3CON_T3RDIR_Msk (0x8000UL)
8024 /* ========================================================== T4 =========================================================== */
8025 #define GPT12E_T4_T4_Pos (0UL)
8026 #define GPT12E_T4_T4_Msk (0xffffUL)
8027 /* ========================================================= T4CON ========================================================= */
8028 #define GPT12E_T4CON_T4I_Pos (0UL)
8029 #define GPT12E_T4CON_T4I_Msk (0x7UL)
8030 #define GPT12E_T4CON_T4M_Pos (3UL)
8031 #define GPT12E_T4CON_T4M_Msk (0x38UL)
8032 #define GPT12E_T4CON_T4R_Pos (6UL)
8033 #define GPT12E_T4CON_T4R_Msk (0x40UL)
8034 #define GPT12E_T4CON_T4UD_Pos (7UL)
8035 #define GPT12E_T4CON_T4UD_Msk (0x80UL)
8036 #define GPT12E_T4CON_T4UDE_Pos (8UL)
8037 #define GPT12E_T4CON_T4UDE_Msk (0x100UL)
8038 #define GPT12E_T4CON_T4RC_Pos (9UL)
8039 #define GPT12E_T4CON_T4RC_Msk (0x200UL)
8040 #define GPT12E_T4CON_CLRT2EN_Pos (10UL)
8041 #define GPT12E_T4CON_CLRT2EN_Msk (0x400UL)
8042 #define GPT12E_T4CON_CLRT3EN_Pos (11UL)
8043 #define GPT12E_T4CON_CLRT3EN_Msk (0x800UL)
8044 #define GPT12E_T4CON_T4IRDIS_Pos (12UL)
8045 #define GPT12E_T4CON_T4IRDIS_Msk (0x1000UL)
8046 #define GPT12E_T4CON_T4EDGE_Pos (13UL)
8047 #define GPT12E_T4CON_T4EDGE_Msk (0x2000UL)
8048 #define GPT12E_T4CON_T4CHDIR_Pos (14UL)
8049 #define GPT12E_T4CON_T4CHDIR_Msk (0x4000UL)
8050 #define GPT12E_T4CON_T4RDIR_Pos (15UL)
8051 #define GPT12E_T4CON_T4RDIR_Msk (0x8000UL)
8052 /* ========================================================== T5 =========================================================== */
8053 #define GPT12E_T5_T5_Pos (0UL)
8054 #define GPT12E_T5_T5_Msk (0xffffUL)
8055 /* ========================================================= T5CON ========================================================= */
8056 #define GPT12E_T5CON_T5I_Pos (0UL)
8057 #define GPT12E_T5CON_T5I_Msk (0x7UL)
8058 #define GPT12E_T5CON_T5M_Pos (3UL)
8059 #define GPT12E_T5CON_T5M_Msk (0x18UL)
8060 #define GPT12E_T5CON_T5R_Pos (6UL)
8061 #define GPT12E_T5CON_T5R_Msk (0x40UL)
8062 #define GPT12E_T5CON_T5UD_Pos (7UL)
8063 #define GPT12E_T5CON_T5UD_Msk (0x80UL)
8064 #define GPT12E_T5CON_T5UDE_Pos (8UL)
8065 #define GPT12E_T5CON_T5UDE_Msk (0x100UL)
8066 #define GPT12E_T5CON_T5RC_Pos (9UL)
8067 #define GPT12E_T5CON_T5RC_Msk (0x200UL)
8068 #define GPT12E_T5CON_CT3_Pos (10UL)
8069 #define GPT12E_T5CON_CT3_Msk (0x400UL)
8070 #define GPT12E_T5CON_CI_Pos (12UL)
8071 #define GPT12E_T5CON_CI_Msk (0x3000UL)
8072 #define GPT12E_T5CON_T5CLR_Pos (14UL)
8073 #define GPT12E_T5CON_T5CLR_Msk (0x4000UL)
8074 #define GPT12E_T5CON_T5SC_Pos (15UL)
8075 #define GPT12E_T5CON_T5SC_Msk (0x8000UL)
8076 /* ========================================================== T6 =========================================================== */
8077 #define GPT12E_T6_T6_Pos (0UL)
8078 #define GPT12E_T6_T6_Msk (0xffffUL)
8079 /* ========================================================= T6CON ========================================================= */
8080 #define GPT12E_T6CON_T6I_Pos (0UL)
8081 #define GPT12E_T6CON_T6I_Msk (0x7UL)
8082 #define GPT12E_T6CON_T6M_Pos (3UL)
8083 #define GPT12E_T6CON_T6M_Msk (0x38UL)
8084 #define GPT12E_T6CON_T6R_Pos (6UL)
8085 #define GPT12E_T6CON_T6R_Msk (0x40UL)
8086 #define GPT12E_T6CON_T6UD_Pos (7UL)
8087 #define GPT12E_T6CON_T6UD_Msk (0x80UL)
8088 #define GPT12E_T6CON_T6UDE_Pos (8UL)
8089 #define GPT12E_T6CON_T6UDE_Msk (0x100UL)
8090 #define GPT12E_T6CON_T6OE_Pos (9UL)
8091 #define GPT12E_T6CON_T6OE_Msk (0x200UL)
8092 #define GPT12E_T6CON_T6OTL_Pos (10UL)
8093 #define GPT12E_T6CON_T6OTL_Msk (0x400UL)
8094 #define GPT12E_T6CON_BPS2_Pos (11UL)
8095 #define GPT12E_T6CON_BPS2_Msk (0x1800UL)
8096 #define GPT12E_T6CON_T6CLR_Pos (14UL)
8097 #define GPT12E_T6CON_T6CLR_Msk (0x4000UL)
8098 #define GPT12E_T6CON_T6SR_Pos (15UL)
8099 #define GPT12E_T6CON_T6SR_Msk (0x8000UL)
8102 /* =========================================================================================================================== */
8103 /* ================ LIN ================ */
8104 /* =========================================================================================================================== */
8105 
8106 /* ======================================================= CTRL_STS ======================================================== */
8107 #define LIN_CTRL_STS_M_SM_ERR_CLR_Pos (24UL)
8108 #define LIN_CTRL_STS_M_SM_ERR_CLR_Msk (0x1000000UL)
8109 #define LIN_CTRL_STS_HV_MODE_Pos (21UL)
8110 #define LIN_CTRL_STS_HV_MODE_Msk (0x200000UL)
8111 #define LIN_CTRL_STS_MODE_FB_Pos (16UL)
8112 #define LIN_CTRL_STS_MODE_FB_Msk (0x70000UL)
8113 #define LIN_CTRL_STS_FB_SM3_Pos (15UL)
8114 #define LIN_CTRL_STS_FB_SM3_Msk (0x8000UL)
8115 #define LIN_CTRL_STS_FB_SM2_Pos (14UL)
8116 #define LIN_CTRL_STS_FB_SM2_Msk (0x4000UL)
8117 #define LIN_CTRL_STS_FB_SM1_Pos (13UL)
8118 #define LIN_CTRL_STS_FB_SM1_Msk (0x2000UL)
8119 #define LIN_CTRL_STS_SM_Pos (11UL)
8120 #define LIN_CTRL_STS_SM_Msk (0x1800UL)
8121 #define LIN_CTRL_STS_RXD_Pos (10UL)
8122 #define LIN_CTRL_STS_RXD_Msk (0x400UL)
8123 #define LIN_CTRL_STS_TXD_Pos (9UL)
8124 #define LIN_CTRL_STS_TXD_Msk (0x200UL)
8125 #define LIN_CTRL_STS_TXD_TMOUT_STS_Pos (6UL)
8126 #define LIN_CTRL_STS_TXD_TMOUT_STS_Msk (0x40UL)
8127 #define LIN_CTRL_STS_OC_STS_Pos (5UL)
8128 #define LIN_CTRL_STS_OC_STS_Msk (0x20UL)
8129 #define LIN_CTRL_STS_OT_STS_Pos (4UL)
8130 #define LIN_CTRL_STS_OT_STS_Msk (0x10UL)
8131 #define LIN_CTRL_STS_M_SM_ERR_Pos (3UL)
8132 #define LIN_CTRL_STS_M_SM_ERR_Msk (0x8UL)
8133 #define LIN_CTRL_STS_MODE_Pos (1UL)
8134 #define LIN_CTRL_STS_MODE_Msk (0x6UL)
8137 /* =========================================================================================================================== */
8138 /* ================ MF ================ */
8139 /* =========================================================================================================================== */
8140 
8141 /* ==================================================== BEMFC_CTRL_STS ===================================================== */
8142 #define MF_BEMFC_CTRL_STS_PHW_ZC_STS_Pos (18UL)
8143 #define MF_BEMFC_CTRL_STS_PHW_ZC_STS_Msk (0x40000UL)
8144 #define MF_BEMFC_CTRL_STS_PHV_ZC_STS_Pos (17UL)
8145 #define MF_BEMFC_CTRL_STS_PHV_ZC_STS_Msk (0x20000UL)
8146 #define MF_BEMFC_CTRL_STS_PHU_ZC_STS_Pos (16UL)
8147 #define MF_BEMFC_CTRL_STS_PHU_ZC_STS_Msk (0x10000UL)
8148 #define MF_BEMFC_CTRL_STS_CCPOS_INSEL_Pos (12UL)
8149 #define MF_BEMFC_CTRL_STS_CCPOS_INSEL_Msk (0x1000UL)
8150 #define MF_BEMFC_CTRL_STS_PHWCOMP_ON_Pos (10UL)
8151 #define MF_BEMFC_CTRL_STS_PHWCOMP_ON_Msk (0x400UL)
8152 #define MF_BEMFC_CTRL_STS_PHVCOMP_ON_Pos (9UL)
8153 #define MF_BEMFC_CTRL_STS_PHVCOMP_ON_Msk (0x200UL)
8154 #define MF_BEMFC_CTRL_STS_PHUCOMP_ON_Pos (8UL)
8155 #define MF_BEMFC_CTRL_STS_PHUCOMP_ON_Msk (0x100UL)
8156 #define MF_BEMFC_CTRL_STS_GPT12CAPINSW_Pos (5UL)
8157 #define MF_BEMFC_CTRL_STS_GPT12CAPINSW_Msk (0x20UL)
8158 #define MF_BEMFC_CTRL_STS_FILTBYPS_Pos (4UL)
8159 #define MF_BEMFC_CTRL_STS_FILTBYPS_Msk (0x10UL)
8160 #define MF_BEMFC_CTRL_STS_DEMGFILTDIS_Pos (3UL)
8161 #define MF_BEMFC_CTRL_STS_DEMGFILTDIS_Msk (0x8UL)
8162 #define MF_BEMFC_CTRL_STS_PHWCOMP_EN_Pos (2UL)
8163 #define MF_BEMFC_CTRL_STS_PHWCOMP_EN_Msk (0x4UL)
8164 #define MF_BEMFC_CTRL_STS_PHVCOMP_EN_Pos (1UL)
8165 #define MF_BEMFC_CTRL_STS_PHVCOMP_EN_Msk (0x2UL)
8166 #define MF_BEMFC_CTRL_STS_PHUCOMP_EN_Pos (0UL)
8167 #define MF_BEMFC_CTRL_STS_PHUCOMP_EN_Msk (0x1UL)
8168 /* ======================================================= CSA_CTRL ======================================================== */
8169 #define MF_CSA_CTRL_VZERO_Pos (8UL)
8170 #define MF_CSA_CTRL_VZERO_Msk (0x100UL)
8171 #define MF_CSA_CTRL_GAIN_Pos (1UL)
8172 #define MF_CSA_CTRL_GAIN_Msk (0x6UL)
8173 #define MF_CSA_CTRL_EN_Pos (0UL)
8174 #define MF_CSA_CTRL_EN_Msk (0x1UL)
8175 /* ==================================================== P2_ADCSEL_CTRL ===================================================== */
8176 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Pos (10UL)
8177 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Msk (0x400UL)
8178 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Pos (9UL)
8179 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Msk (0x200UL)
8180 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Pos (8UL)
8181 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Msk (0x100UL)
8182 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Pos (0UL)
8183 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Msk (0x1UL)
8184 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Pos (1UL)
8185 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Msk (0x2UL)
8186 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Pos (2UL)
8187 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Msk (0x4UL)
8188 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Pos (3UL)
8189 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Msk (0x8UL)
8190 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Pos (4UL)
8191 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Msk (0x10UL)
8192 /* ======================================================= REF1_STS ======================================================== */
8193 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Pos (5UL)
8194 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Msk (0x20UL)
8195 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Pos (4UL)
8196 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Msk (0x10UL)
8197 /* ======================================================= REF2_CTRL ======================================================= */
8198 #define MF_REF2_CTRL_VREF5V_OV_STS_Pos (3UL)
8199 #define MF_REF2_CTRL_VREF5V_OV_STS_Msk (0x8UL)
8200 #define MF_REF2_CTRL_VREF5V_UV_STS_Pos (2UL)
8201 #define MF_REF2_CTRL_VREF5V_UV_STS_Msk (0x4UL)
8202 #define MF_REF2_CTRL_VREF5V_OVL_STS_Pos (1UL)
8203 #define MF_REF2_CTRL_VREF5V_OVL_STS_Msk (0x2UL)
8204 #define MF_REF2_CTRL_VREF5V_PD_N_Pos (0UL)
8205 #define MF_REF2_CTRL_VREF5V_PD_N_Msk (0x1UL)
8206 /* ==================================================== TEMPSENSE_CTRL ===================================================== */
8207 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Pos (7UL)
8208 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Msk (0x80UL)
8209 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Pos (6UL)
8210 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Msk (0x40UL)
8211 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Pos (5UL)
8212 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Msk (0x20UL)
8213 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Pos (4UL)
8214 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Msk (0x10UL)
8215 /* ====================================================== TRIM_BEMFx ======================================================= */
8216 #define MF_TRIM_BEMFx_BEMF_TFILT_SEL_Pos (8UL)
8217 #define MF_TRIM_BEMFx_BEMF_TFILT_SEL_Msk (0x300UL)
8218 #define MF_TRIM_BEMFx_BEMF_GPT_CAPIN_SEL_Pos (4UL)
8219 #define MF_TRIM_BEMFx_BEMF_GPT_CAPIN_SEL_Msk (0x30UL)
8220 #define MF_TRIM_BEMFx_BEMF_BT_TFILT_SEL_Pos (0UL)
8221 #define MF_TRIM_BEMFx_BEMF_BT_TFILT_SEL_Msk (0x7UL)
8222 /* ===================================================== VMON_SEN_CTRL ===================================================== */
8223 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos (5UL)
8224 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk (0x20UL)
8225 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos (4UL)
8226 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk (0x10UL)
8227 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos (0UL)
8228 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk (0x1UL)
8231 /* =========================================================================================================================== */
8232 /* ================ PMU ================ */
8233 /* =========================================================================================================================== */
8234 
8235 /* ================================================== CNF_CYC_SAMPLE_DEL =================================================== */
8236 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Pos (0UL)
8237 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Msk (0xfUL)
8238 /* ===================================================== CNF_CYC_SENSE ===================================================== */
8239 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Pos (7UL)
8240 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Msk (0x80UL)
8241 #define PMU_CNF_CYC_SENSE_E01_Pos (4UL)
8242 #define PMU_CNF_CYC_SENSE_E01_Msk (0x30UL)
8243 #define PMU_CNF_CYC_SENSE_M03_Pos (0UL)
8244 #define PMU_CNF_CYC_SENSE_M03_Msk (0xfUL)
8245 /* ===================================================== CNF_CYC_WAKE ====================================================== */
8246 #define PMU_CNF_CYC_WAKE_E01_Pos (4UL)
8247 #define PMU_CNF_CYC_WAKE_E01_Msk (0x30UL)
8248 #define PMU_CNF_CYC_WAKE_M03_Pos (0UL)
8249 #define PMU_CNF_CYC_WAKE_M03_Msk (0xfUL)
8250 /* =================================================== CNF_PMU_SETTINGS ==================================================== */
8251 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Pos (7UL)
8252 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Msk (0x80UL)
8253 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Pos (3UL)
8254 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Msk (0x8UL)
8255 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Pos (2UL)
8256 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Msk (0x4UL)
8257 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Pos (1UL)
8258 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Msk (0x2UL)
8259 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Pos (0UL)
8260 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Msk (0x1UL)
8261 /* ====================================================== CNF_RST_TFB ====================================================== */
8262 #define PMU_CNF_RST_TFB_RST_TFB_Pos (0UL)
8263 #define PMU_CNF_RST_TFB_RST_TFB_Msk (0x3UL)
8264 /* ==================================================== CNF_WAKE_FILTER ==================================================== */
8265 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Pos (2UL)
8266 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Msk (0xcUL)
8267 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Pos (1UL)
8268 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Msk (0x2UL)
8269 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Pos (0UL)
8270 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Msk (0x1UL)
8271 /* ======================================================= GPUDATA00 ======================================================= */
8272 #define PMU_GPUDATA00_DATA0_Pos (0UL)
8273 #define PMU_GPUDATA00_DATA0_Msk (0xffUL)
8274 /* ======================================================= GPUDATA01 ======================================================= */
8275 #define PMU_GPUDATA01_DATA1_Pos (0UL)
8276 #define PMU_GPUDATA01_DATA1_Msk (0xffUL)
8277 /* ======================================================= GPUDATA02 ======================================================= */
8278 #define PMU_GPUDATA02_DATA2_Pos (0UL)
8279 #define PMU_GPUDATA02_DATA2_Msk (0xffUL)
8280 /* ======================================================= GPUDATA03 ======================================================= */
8281 #define PMU_GPUDATA03_DATA3_Pos (0UL)
8282 #define PMU_GPUDATA03_DATA3_Msk (0xffUL)
8283 /* ======================================================= GPUDATA04 ======================================================= */
8284 #define PMU_GPUDATA04_DATA4_Pos (0UL)
8285 #define PMU_GPUDATA04_DATA4_Msk (0xffUL)
8286 /* ======================================================= GPUDATA05 ======================================================= */
8287 #define PMU_GPUDATA05_DATA5_Pos (0UL)
8288 #define PMU_GPUDATA05_DATA5_Msk (0xffUL)
8289 /* ====================================================== LIN_WAKE_EN ====================================================== */
8290 #define PMU_LIN_WAKE_EN_LIN_EN_Pos (7UL)
8291 #define PMU_LIN_WAKE_EN_LIN_EN_Msk (0x80UL)
8292 /* ======================================================== MON_CNF ======================================================== */
8293 #define PMU_MON_CNF_STS_Pos (7UL)
8294 #define PMU_MON_CNF_STS_Msk (0x80UL)
8295 #define PMU_MON_CNF_PU_Pos (5UL)
8296 #define PMU_MON_CNF_PU_Msk (0x20UL)
8297 #define PMU_MON_CNF_PD_Pos (4UL)
8298 #define PMU_MON_CNF_PD_Msk (0x10UL)
8299 #define PMU_MON_CNF_CYC_Pos (3UL)
8300 #define PMU_MON_CNF_CYC_Msk (0x8UL)
8301 #define PMU_MON_CNF_RISE_Pos (2UL)
8302 #define PMU_MON_CNF_RISE_Msk (0x4UL)
8303 #define PMU_MON_CNF_FALL_Pos (1UL)
8304 #define PMU_MON_CNF_FALL_Msk (0x2UL)
8305 #define PMU_MON_CNF_EN_Pos (0UL)
8306 #define PMU_MON_CNF_EN_Msk (0x1UL)
8307 /* ==================================================== PMU_RESET_STS1 ===================================================== */
8308 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Pos (7UL)
8309 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Msk (0x80UL)
8310 #define PMU_PMU_RESET_STS1_PMU_PIN_Pos (6UL)
8311 #define PMU_PMU_RESET_STS1_PMU_PIN_Msk (0x40UL)
8312 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Pos (5UL)
8313 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Msk (0x20UL)
8314 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Pos (4UL)
8315 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Msk (0x10UL)
8316 #define PMU_PMU_RESET_STS1_PMU_LPR_Pos (3UL)
8317 #define PMU_PMU_RESET_STS1_PMU_LPR_Msk (0x8UL)
8318 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Pos (2UL)
8319 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Msk (0x4UL)
8320 #define PMU_PMU_RESET_STS1_PMU_WAKE_Pos (1UL)
8321 #define PMU_PMU_RESET_STS1_PMU_WAKE_Msk (0x2UL)
8322 #define PMU_PMU_RESET_STS1_SYS_FAIL_Pos (0UL)
8323 #define PMU_PMU_RESET_STS1_SYS_FAIL_Msk (0x1UL)
8324 /* ==================================================== PMU_RESET_STS2 ===================================================== */
8325 #define PMU_PMU_RESET_STS2_LOCKUP_Pos (2UL)
8326 #define PMU_PMU_RESET_STS2_LOCKUP_Msk (0x4UL)
8327 #define PMU_PMU_RESET_STS2_PMU_SOFT_Pos (1UL)
8328 #define PMU_PMU_RESET_STS2_PMU_SOFT_Msk (0x2UL)
8329 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Pos (0UL)
8330 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Msk (0x1UL)
8331 /* ==================================================== PMU_SUPPLY_STS ===================================================== */
8332 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos (6UL)
8333 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk (0x40UL)
8334 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Pos (5UL)
8335 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Msk (0x20UL)
8336 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Pos (4UL)
8337 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Msk (0x10UL)
8338 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos (2UL)
8339 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk (0x4UL)
8340 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Pos (1UL)
8341 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Msk (0x2UL)
8342 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Pos (0UL)
8343 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Msk (0x1UL)
8344 /* ===================================================== SYS_FAIL_STS ====================================================== */
8345 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Pos (6UL)
8346 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Msk (0x40UL)
8347 #define PMU_SYS_FAIL_STS_SYS_OT_Pos (5UL)
8348 #define PMU_SYS_FAIL_STS_SYS_OT_Msk (0x20UL)
8349 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Pos (3UL)
8350 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Msk (0x8UL)
8351 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Pos (2UL)
8352 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Msk (0x4UL)
8353 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Pos (1UL)
8354 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Msk (0x2UL)
8355 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Pos (0UL)
8356 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Msk (0x1UL)
8357 /* =================================================== SystemStartConfig =================================================== */
8358 #define PMU_SystemStartConfig_MBIST_EN_Pos (0UL)
8359 #define PMU_SystemStartConfig_MBIST_EN_Msk (0x1UL)
8360 /* ====================================================== VDDEXT_CTRL ====================================================== */
8361 #define PMU_VDDEXT_CTRL_STABLE_Pos (7UL)
8362 #define PMU_VDDEXT_CTRL_STABLE_Msk (0x80UL)
8363 #define PMU_VDDEXT_CTRL_OK_Pos (6UL)
8364 #define PMU_VDDEXT_CTRL_OK_Msk (0x40UL)
8365 #define PMU_VDDEXT_CTRL_OVERLOAD_Pos (5UL)
8366 #define PMU_VDDEXT_CTRL_OVERLOAD_Msk (0x20UL)
8367 #define PMU_VDDEXT_CTRL_OVERVOLT_Pos (4UL)
8368 #define PMU_VDDEXT_CTRL_OVERVOLT_Msk (0x10UL)
8369 #define PMU_VDDEXT_CTRL_SHORT_Pos (3UL)
8370 #define PMU_VDDEXT_CTRL_SHORT_Msk (0x8UL)
8371 #define PMU_VDDEXT_CTRL_FAIL_EN_Pos (2UL)
8372 #define PMU_VDDEXT_CTRL_FAIL_EN_Msk (0x4UL)
8373 #define PMU_VDDEXT_CTRL_CYC_EN_Pos (1UL)
8374 #define PMU_VDDEXT_CTRL_CYC_EN_Msk (0x2UL)
8375 #define PMU_VDDEXT_CTRL_ENABLE_Pos (0UL)
8376 #define PMU_VDDEXT_CTRL_ENABLE_Msk (0x1UL)
8377 /* ================================================== WAKE_CONF_GPIO0_CYC ================================================== */
8378 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Pos (4UL)
8379 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Msk (0x10UL)
8380 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Pos (3UL)
8381 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Msk (0x8UL)
8382 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Pos (2UL)
8383 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Msk (0x4UL)
8384 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Pos (1UL)
8385 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Msk (0x2UL)
8386 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Pos (0UL)
8387 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Msk (0x1UL)
8388 /* ================================================= WAKE_CONF_GPIO0_FALL ================================================== */
8389 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Pos (4UL)
8390 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Msk (0x10UL)
8391 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Pos (3UL)
8392 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Msk (0x8UL)
8393 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Pos (2UL)
8394 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Msk (0x4UL)
8395 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Pos (1UL)
8396 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Msk (0x2UL)
8397 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Pos (0UL)
8398 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Msk (0x1UL)
8399 /* ================================================= WAKE_CONF_GPIO0_RISE ================================================== */
8400 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Pos (4UL)
8401 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Msk (0x10UL)
8402 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Pos (3UL)
8403 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Msk (0x8UL)
8404 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Pos (2UL)
8405 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Msk (0x4UL)
8406 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Pos (1UL)
8407 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Msk (0x2UL)
8408 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Pos (0UL)
8409 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Msk (0x1UL)
8410 /* ================================================== WAKE_CONF_GPIO1_CYC ================================================== */
8411 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Pos (4UL)
8412 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Msk (0x10UL)
8413 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Pos (3UL)
8414 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Msk (0x8UL)
8415 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Pos (2UL)
8416 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Msk (0x4UL)
8417 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Pos (1UL)
8418 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Msk (0x2UL)
8419 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Pos (0UL)
8420 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Msk (0x1UL)
8421 /* ================================================= WAKE_CONF_GPIO1_FALL ================================================== */
8422 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Pos (4UL)
8423 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Msk (0x10UL)
8424 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Pos (3UL)
8425 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Msk (0x8UL)
8426 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Pos (2UL)
8427 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Msk (0x4UL)
8428 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Pos (1UL)
8429 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Msk (0x2UL)
8430 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Pos (0UL)
8431 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Msk (0x1UL)
8432 /* ================================================= WAKE_CONF_GPIO1_RISE ================================================== */
8433 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Pos (4UL)
8434 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Msk (0x10UL)
8435 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Pos (3UL)
8436 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Msk (0x8UL)
8437 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Pos (2UL)
8438 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Msk (0x4UL)
8439 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Pos (1UL)
8440 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Msk (0x2UL)
8441 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Pos (0UL)
8442 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Msk (0x1UL)
8443 /* ====================================================== WAKE_STATUS ====================================================== */
8444 #define PMU_WAKE_STATUS_FAIL_Pos (5UL)
8445 #define PMU_WAKE_STATUS_FAIL_Msk (0x20UL)
8446 #define PMU_WAKE_STATUS_CYC_WAKE_Pos (4UL)
8447 #define PMU_WAKE_STATUS_CYC_WAKE_Msk (0x10UL)
8448 #define PMU_WAKE_STATUS_GPIO1_Pos (3UL)
8449 #define PMU_WAKE_STATUS_GPIO1_Msk (0x8UL)
8450 #define PMU_WAKE_STATUS_GPIO0_Pos (2UL)
8451 #define PMU_WAKE_STATUS_GPIO0_Msk (0x4UL)
8452 #define PMU_WAKE_STATUS_MON_WAKE_Pos (1UL)
8453 #define PMU_WAKE_STATUS_MON_WAKE_Msk (0x2UL)
8454 #define PMU_WAKE_STATUS_LIN_WAKE_Pos (0UL)
8455 #define PMU_WAKE_STATUS_LIN_WAKE_Msk (0x1UL)
8456 /* ===================================================== WAKE_STS_FAIL ===================================================== */
8457 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Pos (2UL)
8458 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Msk (0x4UL)
8459 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Pos (0UL)
8460 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Msk (0x1UL)
8461 /* ==================================================== WAKE_STS_GPIO0 ===================================================== */
8462 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Pos (4UL)
8463 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Msk (0x10UL)
8464 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Pos (3UL)
8465 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Msk (0x8UL)
8466 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Pos (2UL)
8467 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Msk (0x4UL)
8468 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Pos (1UL)
8469 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Msk (0x2UL)
8470 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Pos (0UL)
8471 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Msk (0x1UL)
8472 /* ==================================================== WAKE_STS_GPIO1 ===================================================== */
8473 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Pos (4UL)
8474 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Msk (0x10UL)
8475 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Pos (3UL)
8476 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Msk (0x8UL)
8477 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Pos (2UL)
8478 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Msk (0x4UL)
8479 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Pos (1UL)
8480 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Msk (0x2UL)
8481 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Pos (0UL)
8482 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Msk (0x1UL)
8483 /* ===================================================== WAKE_STS_MON ====================================================== */
8484 #define PMU_WAKE_STS_MON_WAKE_STS_Pos (0UL)
8485 #define PMU_WAKE_STS_MON_WAKE_STS_Msk (0x1UL)
8488 /* =========================================================================================================================== */
8489 /* ================ PORT ================ */
8490 /* =========================================================================================================================== */
8491 
8492 /* ====================================================== P0_ALTSEL0 ======================================================= */
8493 #define PORT_P0_ALTSEL0_P0_Pos (0UL)
8494 #define PORT_P0_ALTSEL0_P0_Msk (0x1UL)
8495 #define PORT_P0_ALTSEL0_P1_Pos (1UL)
8496 #define PORT_P0_ALTSEL0_P1_Msk (0x2UL)
8497 #define PORT_P0_ALTSEL0_P2_Pos (2UL)
8498 #define PORT_P0_ALTSEL0_P2_Msk (0x4UL)
8499 #define PORT_P0_ALTSEL0_P3_Pos (3UL)
8500 #define PORT_P0_ALTSEL0_P3_Msk (0x8UL)
8501 #define PORT_P0_ALTSEL0_P4_Pos (4UL)
8502 #define PORT_P0_ALTSEL0_P4_Msk (0x10UL)
8503 /* ====================================================== P0_ALTSEL1 ======================================================= */
8504 #define PORT_P0_ALTSEL1_P0_Pos (0UL)
8505 #define PORT_P0_ALTSEL1_P0_Msk (0x1UL)
8506 #define PORT_P0_ALTSEL1_P1_Pos (1UL)
8507 #define PORT_P0_ALTSEL1_P1_Msk (0x2UL)
8508 #define PORT_P0_ALTSEL1_P2_Pos (2UL)
8509 #define PORT_P0_ALTSEL1_P2_Msk (0x4UL)
8510 #define PORT_P0_ALTSEL1_P3_Pos (3UL)
8511 #define PORT_P0_ALTSEL1_P3_Msk (0x8UL)
8512 #define PORT_P0_ALTSEL1_P4_Pos (4UL)
8513 #define PORT_P0_ALTSEL1_P4_Msk (0x10UL)
8514 /* ======================================================== P0_DATA ======================================================== */
8515 #define PORT_P0_DATA_P0_Pos (0UL)
8516 #define PORT_P0_DATA_P0_Msk (0x1UL)
8517 #define PORT_P0_DATA_P1_Pos (1UL)
8518 #define PORT_P0_DATA_P1_Msk (0x2UL)
8519 #define PORT_P0_DATA_P2_Pos (2UL)
8520 #define PORT_P0_DATA_P2_Msk (0x4UL)
8521 #define PORT_P0_DATA_P3_Pos (3UL)
8522 #define PORT_P0_DATA_P3_Msk (0x8UL)
8523 #define PORT_P0_DATA_P4_Pos (4UL)
8524 #define PORT_P0_DATA_P4_Msk (0x10UL)
8525 /* ======================================================== P0_DIR ========================================================= */
8526 #define PORT_P0_DIR_P0_Pos (0UL)
8527 #define PORT_P0_DIR_P0_Msk (0x1UL)
8528 #define PORT_P0_DIR_P1_Pos (1UL)
8529 #define PORT_P0_DIR_P1_Msk (0x2UL)
8530 #define PORT_P0_DIR_P2_Pos (2UL)
8531 #define PORT_P0_DIR_P2_Msk (0x4UL)
8532 #define PORT_P0_DIR_P3_Pos (3UL)
8533 #define PORT_P0_DIR_P3_Msk (0x8UL)
8534 #define PORT_P0_DIR_P4_Pos (4UL)
8535 #define PORT_P0_DIR_P4_Msk (0x10UL)
8536 /* ========================================================= P0_OD ========================================================= */
8537 #define PORT_P0_OD_P0_Pos (0UL)
8538 #define PORT_P0_OD_P0_Msk (0x1UL)
8539 #define PORT_P0_OD_P1_Pos (1UL)
8540 #define PORT_P0_OD_P1_Msk (0x2UL)
8541 #define PORT_P0_OD_P2_Pos (2UL)
8542 #define PORT_P0_OD_P2_Msk (0x4UL)
8543 #define PORT_P0_OD_P3_Pos (3UL)
8544 #define PORT_P0_OD_P3_Msk (0x8UL)
8545 #define PORT_P0_OD_P4_Pos (4UL)
8546 #define PORT_P0_OD_P4_Msk (0x10UL)
8547 /* ======================================================= P0_PUDEN ======================================================== */
8548 #define PORT_P0_PUDEN_P0_Pos (0UL)
8549 #define PORT_P0_PUDEN_P0_Msk (0x1UL)
8550 #define PORT_P0_PUDEN_P1_Pos (1UL)
8551 #define PORT_P0_PUDEN_P1_Msk (0x2UL)
8552 #define PORT_P0_PUDEN_P2_Pos (2UL)
8553 #define PORT_P0_PUDEN_P2_Msk (0x4UL)
8554 #define PORT_P0_PUDEN_P3_Pos (3UL)
8555 #define PORT_P0_PUDEN_P3_Msk (0x8UL)
8556 #define PORT_P0_PUDEN_P4_Pos (4UL)
8557 #define PORT_P0_PUDEN_P4_Msk (0x10UL)
8558 /* ======================================================= P0_PUDSEL ======================================================= */
8559 #define PORT_P0_PUDSEL_P0_Pos (0UL)
8560 #define PORT_P0_PUDSEL_P0_Msk (0x1UL)
8561 #define PORT_P0_PUDSEL_P1_Pos (1UL)
8562 #define PORT_P0_PUDSEL_P1_Msk (0x2UL)
8563 #define PORT_P0_PUDSEL_P2_Pos (2UL)
8564 #define PORT_P0_PUDSEL_P2_Msk (0x4UL)
8565 #define PORT_P0_PUDSEL_P3_Pos (3UL)
8566 #define PORT_P0_PUDSEL_P3_Msk (0x8UL)
8567 #define PORT_P0_PUDSEL_P4_Pos (4UL)
8568 #define PORT_P0_PUDSEL_P4_Msk (0x10UL)
8569 /* ====================================================== P1_ALTSEL0 ======================================================= */
8570 #define PORT_P1_ALTSEL0_P0_Pos (0UL)
8571 #define PORT_P1_ALTSEL0_P0_Msk (0x1UL)
8572 #define PORT_P1_ALTSEL0_P1_Pos (1UL)
8573 #define PORT_P1_ALTSEL0_P1_Msk (0x2UL)
8574 #define PORT_P1_ALTSEL0_P2_Pos (2UL)
8575 #define PORT_P1_ALTSEL0_P2_Msk (0x4UL)
8576 #define PORT_P1_ALTSEL0_P3_Pos (3UL)
8577 #define PORT_P1_ALTSEL0_P3_Msk (0x8UL)
8578 #define PORT_P1_ALTSEL0_P4_Pos (4UL)
8579 #define PORT_P1_ALTSEL0_P4_Msk (0x10UL)
8580 /* ====================================================== P1_ALTSEL1 ======================================================= */
8581 #define PORT_P1_ALTSEL1_P0_Pos (0UL)
8582 #define PORT_P1_ALTSEL1_P0_Msk (0x1UL)
8583 #define PORT_P1_ALTSEL1_P1_Pos (1UL)
8584 #define PORT_P1_ALTSEL1_P1_Msk (0x2UL)
8585 #define PORT_P1_ALTSEL1_P2_Pos (2UL)
8586 #define PORT_P1_ALTSEL1_P2_Msk (0x4UL)
8587 #define PORT_P1_ALTSEL1_P3_Pos (3UL)
8588 #define PORT_P1_ALTSEL1_P3_Msk (0x8UL)
8589 #define PORT_P1_ALTSEL1_P4_Pos (4UL)
8590 #define PORT_P1_ALTSEL1_P4_Msk (0x10UL)
8591 /* ======================================================== P1_DATA ======================================================== */
8592 #define PORT_P1_DATA_P0_Pos (0UL)
8593 #define PORT_P1_DATA_P0_Msk (0x1UL)
8594 #define PORT_P1_DATA_P1_Pos (1UL)
8595 #define PORT_P1_DATA_P1_Msk (0x2UL)
8596 #define PORT_P1_DATA_P2_Pos (2UL)
8597 #define PORT_P1_DATA_P2_Msk (0x4UL)
8598 #define PORT_P1_DATA_P3_Pos (3UL)
8599 #define PORT_P1_DATA_P3_Msk (0x8UL)
8600 #define PORT_P1_DATA_P4_Pos (4UL)
8601 #define PORT_P1_DATA_P4_Msk (0x10UL)
8602 /* ======================================================== P1_DIR ========================================================= */
8603 #define PORT_P1_DIR_P0_Pos (0UL)
8604 #define PORT_P1_DIR_P0_Msk (0x1UL)
8605 #define PORT_P1_DIR_P1_Pos (1UL)
8606 #define PORT_P1_DIR_P1_Msk (0x2UL)
8607 #define PORT_P1_DIR_P2_Pos (2UL)
8608 #define PORT_P1_DIR_P2_Msk (0x4UL)
8609 #define PORT_P1_DIR_P3_Pos (3UL)
8610 #define PORT_P1_DIR_P3_Msk (0x8UL)
8611 #define PORT_P1_DIR_P4_Pos (4UL)
8612 #define PORT_P1_DIR_P4_Msk (0x10UL)
8613 /* ========================================================= P1_OD ========================================================= */
8614 #define PORT_P1_OD_P0_Pos (1UL)
8615 #define PORT_P1_OD_P0_Msk (0x2UL)
8616 #define PORT_P1_OD_P1_Pos (2UL)
8617 #define PORT_P1_OD_P1_Msk (0x4UL)
8618 #define PORT_P1_OD_P3_P2_Pos (3UL)
8619 #define PORT_P1_OD_P3_P2_Msk (0x8UL)
8620 #define PORT_P1_OD_P4_Pos (4UL)
8621 #define PORT_P1_OD_P4_Msk (0x10UL)
8622 /* ======================================================= P1_PUDEN ======================================================== */
8623 #define PORT_P1_PUDEN_P0_Pos (0UL)
8624 #define PORT_P1_PUDEN_P0_Msk (0x1UL)
8625 #define PORT_P1_PUDEN_P1_Pos (1UL)
8626 #define PORT_P1_PUDEN_P1_Msk (0x2UL)
8627 #define PORT_P1_PUDEN_P2_Pos (2UL)
8628 #define PORT_P1_PUDEN_P2_Msk (0x4UL)
8629 #define PORT_P1_PUDEN_P3_Pos (3UL)
8630 #define PORT_P1_PUDEN_P3_Msk (0x8UL)
8631 #define PORT_P1_PUDEN_P4_Pos (4UL)
8632 #define PORT_P1_PUDEN_P4_Msk (0x10UL)
8633 /* ======================================================= P1_PUDSEL ======================================================= */
8634 #define PORT_P1_PUDSEL_P0_Pos (0UL)
8635 #define PORT_P1_PUDSEL_P0_Msk (0x1UL)
8636 #define PORT_P1_PUDSEL_P1_Pos (1UL)
8637 #define PORT_P1_PUDSEL_P1_Msk (0x2UL)
8638 #define PORT_P1_PUDSEL_P2_Pos (2UL)
8639 #define PORT_P1_PUDSEL_P2_Msk (0x4UL)
8640 #define PORT_P1_PUDSEL_P3_Pos (3UL)
8641 #define PORT_P1_PUDSEL_P3_Msk (0x8UL)
8642 #define PORT_P1_PUDSEL_P4_Pos (4UL)
8643 #define PORT_P1_PUDSEL_P4_Msk (0x10UL)
8644 /* ======================================================== P2_DATA ======================================================== */
8645 #define PORT_P2_DATA_P0_Pos (0UL)
8646 #define PORT_P2_DATA_P0_Msk (0x1UL)
8647 #define PORT_P2_DATA_P2_Pos (2UL)
8648 #define PORT_P2_DATA_P2_Msk (0x4UL)
8649 #define PORT_P2_DATA_P3_Pos (3UL)
8650 #define PORT_P2_DATA_P3_Msk (0x8UL)
8651 #define PORT_P2_DATA_P4_Pos (4UL)
8652 #define PORT_P2_DATA_P4_Msk (0x10UL)
8653 #define PORT_P2_DATA_P5_Pos (5UL)
8654 #define PORT_P2_DATA_P5_Msk (0x20UL)
8655 /* ======================================================== P2_DIR ========================================================= */
8656 #define PORT_P2_DIR_P0_Pos (0UL)
8657 #define PORT_P2_DIR_P0_Msk (0x1UL)
8658 #define PORT_P2_DIR_P2_Pos (2UL)
8659 #define PORT_P2_DIR_P2_Msk (0x4UL)
8660 #define PORT_P2_DIR_P3_Pos (3UL)
8661 #define PORT_P2_DIR_P3_Msk (0x8UL)
8662 #define PORT_P2_DIR_P4_Pos (4UL)
8663 #define PORT_P2_DIR_P4_Msk (0x10UL)
8664 #define PORT_P2_DIR_P5_Pos (5UL)
8665 #define PORT_P2_DIR_P5_Msk (0x20UL)
8666 /* ======================================================= P2_PUDEN ======================================================== */
8667 #define PORT_P2_PUDEN_P0_Pos (0UL)
8668 #define PORT_P2_PUDEN_P0_Msk (0x1UL)
8669 #define PORT_P2_PUDEN_P2_Pos (2UL)
8670 #define PORT_P2_PUDEN_P2_Msk (0x4UL)
8671 #define PORT_P2_PUDEN_P3_Pos (3UL)
8672 #define PORT_P2_PUDEN_P3_Msk (0x8UL)
8673 #define PORT_P2_PUDEN_P4_Pos (4UL)
8674 #define PORT_P2_PUDEN_P4_Msk (0x10UL)
8675 #define PORT_P2_PUDEN_P5_Pos (5UL)
8676 #define PORT_P2_PUDEN_P5_Msk (0x20UL)
8677 /* ======================================================= P2_PUDSEL ======================================================= */
8678 #define PORT_P2_PUDSEL_P0_Pos (0UL)
8679 #define PORT_P2_PUDSEL_P0_Msk (0x1UL)
8680 #define PORT_P2_PUDSEL_P2_Pos (2UL)
8681 #define PORT_P2_PUDSEL_P2_Msk (0x4UL)
8682 #define PORT_P2_PUDSEL_P3_Pos (3UL)
8683 #define PORT_P2_PUDSEL_P3_Msk (0x8UL)
8684 #define PORT_P2_PUDSEL_P4_Pos (4UL)
8685 #define PORT_P2_PUDSEL_P4_Msk (0x10UL)
8686 #define PORT_P2_PUDSEL_P5_Pos (5UL)
8687 #define PORT_P2_PUDSEL_P5_Msk (0x20UL)
8690 /* =========================================================================================================================== */
8691 /* ================ SCU ================ */
8692 /* =========================================================================================================================== */
8693 
8694 /* ======================================================== APCLK1 ========================================================= */
8695 #define SCU_APCLK1_APCLK3SCLR_Pos (7UL)
8696 #define SCU_APCLK1_APCLK3SCLR_Msk (0x80UL)
8697 #define SCU_APCLK1_APCLK3STS_Pos (6UL)
8698 #define SCU_APCLK1_APCLK3STS_Msk (0x40UL)
8699 #define SCU_APCLK1_APCLK1STS_Pos (4UL)
8700 #define SCU_APCLK1_APCLK1STS_Msk (0x30UL)
8701 #define SCU_APCLK1_APCLK1SCLR_Pos (2UL)
8702 #define SCU_APCLK1_APCLK1SCLR_Msk (0x4UL)
8703 #define SCU_APCLK1_APCLK1FAC_Pos (0UL)
8704 #define SCU_APCLK1_APCLK1FAC_Msk (0x3UL)
8705 /* ======================================================== APCLK2 ========================================================= */
8706 #define SCU_APCLK2_APCLK2SCLR_Pos (7UL)
8707 #define SCU_APCLK2_APCLK2SCLR_Msk (0x80UL)
8708 #define SCU_APCLK2_APCLK2STS_Pos (5UL)
8709 #define SCU_APCLK2_APCLK2STS_Msk (0x60UL)
8710 #define SCU_APCLK2_APCLK2FAC_Pos (0UL)
8711 #define SCU_APCLK2_APCLK2FAC_Msk (0x1fUL)
8712 /* ====================================================== APCLK_CTRL1 ====================================================== */
8713 #define SCU_APCLK_CTRL1_CPCLK_DIV_Pos (7UL)
8714 #define SCU_APCLK_CTRL1_CPCLK_DIV_Msk (0x80UL)
8715 #define SCU_APCLK_CTRL1_CPCLK_SEL_Pos (6UL)
8716 #define SCU_APCLK_CTRL1_CPCLK_SEL_Msk (0x40UL)
8717 #define SCU_APCLK_CTRL1_BGCLK_DIV_Pos (5UL)
8718 #define SCU_APCLK_CTRL1_BGCLK_DIV_Msk (0x20UL)
8719 #define SCU_APCLK_CTRL1_BGCLK_SEL_Pos (4UL)
8720 #define SCU_APCLK_CTRL1_BGCLK_SEL_Msk (0x10UL)
8721 #define SCU_APCLK_CTRL1_CLKWDT_IE_Pos (3UL)
8722 #define SCU_APCLK_CTRL1_CLKWDT_IE_Msk (0x8UL)
8723 #define SCU_APCLK_CTRL1_T3CLK_SEL_Pos (2UL)
8724 #define SCU_APCLK_CTRL1_T3CLK_SEL_Msk (0x4UL)
8725 #define SCU_APCLK_CTRL1_APCLK_SET_Pos (1UL)
8726 #define SCU_APCLK_CTRL1_APCLK_SET_Msk (0x2UL)
8727 #define SCU_APCLK_CTRL1_PLL_LOCK_Pos (0UL)
8728 #define SCU_APCLK_CTRL1_PLL_LOCK_Msk (0x1UL)
8729 /* ====================================================== APCLK_CTRL2 ====================================================== */
8730 #define SCU_APCLK_CTRL2_T3CLK_DIV_Pos (2UL)
8731 #define SCU_APCLK_CTRL2_T3CLK_DIV_Msk (0xcUL)
8732 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Pos (0UL)
8733 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Msk (0x3UL)
8734 /* ========================================================= BCON1 ========================================================= */
8735 #define SCU_BCON1_R_Pos (0UL)
8736 #define SCU_BCON1_R_Msk (0x1UL)
8737 #define SCU_BCON1_BRPRE_Pos (1UL)
8738 #define SCU_BCON1_BRPRE_Msk (0xeUL)
8739 /* ========================================================= BCON2 ========================================================= */
8740 #define SCU_BCON2_R_Pos (0UL)
8741 #define SCU_BCON2_R_Msk (0x1UL)
8742 #define SCU_BCON2_BRPRE_Pos (1UL)
8743 #define SCU_BCON2_BRPRE_Msk (0xeUL)
8744 /* ========================================================= BGH1 ========================================================== */
8745 #define SCU_BGH1_BR_VALUE_Pos (0UL)
8746 #define SCU_BGH1_BR_VALUE_Msk (0xffUL)
8747 /* ========================================================= BGH2 ========================================================== */
8748 #define SCU_BGH2_BR_VALUE_Pos (0UL)
8749 #define SCU_BGH2_BR_VALUE_Msk (0xffUL)
8750 /* ========================================================= BGL1 ========================================================== */
8751 #define SCU_BGL1_FD_SEL_Pos (0UL)
8752 #define SCU_BGL1_FD_SEL_Msk (0x1fUL)
8753 #define SCU_BGL1_BR_VALUE_Pos (5UL)
8754 #define SCU_BGL1_BR_VALUE_Msk (0xe0UL)
8755 /* ========================================================= BGL2 ========================================================== */
8756 #define SCU_BGL2_FD_SEL_Pos (0UL)
8757 #define SCU_BGL2_FD_SEL_Msk (0x1fUL)
8758 #define SCU_BGL2_BR_VALUE_Pos (5UL)
8759 #define SCU_BGL2_BR_VALUE_Msk (0xe0UL)
8760 /* ======================================================== CMCON1 ========================================================= */
8761 #define SCU_CMCON1_VCOSEL_Pos (7UL)
8762 #define SCU_CMCON1_VCOSEL_Msk (0x80UL)
8763 #define SCU_CMCON1_K1DIV_Pos (6UL)
8764 #define SCU_CMCON1_K1DIV_Msk (0x40UL)
8765 #define SCU_CMCON1_K2DIV_Pos (4UL)
8766 #define SCU_CMCON1_K2DIV_Msk (0x30UL)
8767 #define SCU_CMCON1_CLKREL_Pos (0UL)
8768 #define SCU_CMCON1_CLKREL_Msk (0xfUL)
8769 /* ======================================================== CMCON2 ========================================================= */
8770 #define SCU_CMCON2_PBA0CLKREL_Pos (0UL)
8771 #define SCU_CMCON2_PBA0CLKREL_Msk (0x1UL)
8772 /* ========================================================= COCON ========================================================= */
8773 #define SCU_COCON_EN_Pos (7UL)
8774 #define SCU_COCON_EN_Msk (0x80UL)
8775 #define SCU_COCON_COUTS1_Pos (6UL)
8776 #define SCU_COCON_COUTS1_Msk (0x40UL)
8777 #define SCU_COCON_TLEN_Pos (5UL)
8778 #define SCU_COCON_TLEN_Msk (0x20UL)
8779 #define SCU_COCON_COUTS0_Pos (4UL)
8780 #define SCU_COCON_COUTS0_Msk (0x10UL)
8781 #define SCU_COCON_COREL_Pos (0UL)
8782 #define SCU_COCON_COREL_Msk (0xfUL)
8783 /* ======================================================== DMAIEN1 ======================================================== */
8784 #define SCU_DMAIEN1_CH8IE_Pos (7UL)
8785 #define SCU_DMAIEN1_CH8IE_Msk (0x80UL)
8786 #define SCU_DMAIEN1_CH7IE_Pos (6UL)
8787 #define SCU_DMAIEN1_CH7IE_Msk (0x40UL)
8788 #define SCU_DMAIEN1_CH6IE_Pos (5UL)
8789 #define SCU_DMAIEN1_CH6IE_Msk (0x20UL)
8790 #define SCU_DMAIEN1_CH5IE_Pos (4UL)
8791 #define SCU_DMAIEN1_CH5IE_Msk (0x10UL)
8792 #define SCU_DMAIEN1_CH4IE_Pos (3UL)
8793 #define SCU_DMAIEN1_CH4IE_Msk (0x8UL)
8794 #define SCU_DMAIEN1_CH3IE_Pos (2UL)
8795 #define SCU_DMAIEN1_CH3IE_Msk (0x4UL)
8796 #define SCU_DMAIEN1_CH2IE_Pos (1UL)
8797 #define SCU_DMAIEN1_CH2IE_Msk (0x2UL)
8798 #define SCU_DMAIEN1_CH1IE_Pos (0UL)
8799 #define SCU_DMAIEN1_CH1IE_Msk (0x1UL)
8800 /* ======================================================== DMAIEN2 ======================================================== */
8801 #define SCU_DMAIEN2_SDADCIE_Pos (6UL)
8802 #define SCU_DMAIEN2_SDADCIE_Msk (0x40UL)
8803 #define SCU_DMAIEN2_GPT12IE_Pos (5UL)
8804 #define SCU_DMAIEN2_GPT12IE_Msk (0x20UL)
8805 #define SCU_DMAIEN2_SSCRXIE_Pos (4UL)
8806 #define SCU_DMAIEN2_SSCRXIE_Msk (0x10UL)
8807 #define SCU_DMAIEN2_SSCTXIE_Pos (3UL)
8808 #define SCU_DMAIEN2_SSCTXIE_Msk (0x8UL)
8809 #define SCU_DMAIEN2_TRSEQ2RDYIE_Pos (2UL)
8810 #define SCU_DMAIEN2_TRSEQ2RDYIE_Msk (0x4UL)
8811 #define SCU_DMAIEN2_TRSEQ1RDYIE_Pos (1UL)
8812 #define SCU_DMAIEN2_TRSEQ1RDYIE_Msk (0x2UL)
8813 #define SCU_DMAIEN2_TRERRIE_Pos (0UL)
8814 #define SCU_DMAIEN2_TRERRIE_Msk (0x1UL)
8815 /* ======================================================== DMAIRC1 ======================================================== */
8816 #define SCU_DMAIRC1_CH8_Pos (7UL)
8817 #define SCU_DMAIRC1_CH8_Msk (0x80UL)
8818 #define SCU_DMAIRC1_CH7_Pos (6UL)
8819 #define SCU_DMAIRC1_CH7_Msk (0x40UL)
8820 #define SCU_DMAIRC1_CH6_Pos (5UL)
8821 #define SCU_DMAIRC1_CH6_Msk (0x20UL)
8822 #define SCU_DMAIRC1_CH5_Pos (4UL)
8823 #define SCU_DMAIRC1_CH5_Msk (0x10UL)
8824 #define SCU_DMAIRC1_CH4_Pos (3UL)
8825 #define SCU_DMAIRC1_CH4_Msk (0x8UL)
8826 #define SCU_DMAIRC1_CH3_Pos (2UL)
8827 #define SCU_DMAIRC1_CH3_Msk (0x4UL)
8828 #define SCU_DMAIRC1_CH2_Pos (1UL)
8829 #define SCU_DMAIRC1_CH2_Msk (0x2UL)
8830 #define SCU_DMAIRC1_CH1_Pos (0UL)
8831 #define SCU_DMAIRC1_CH1_Msk (0x1UL)
8832 /* ====================================================== DMAIRC1CLR ======================================================= */
8833 #define SCU_DMAIRC1CLR_CH8C_Pos (7UL)
8834 #define SCU_DMAIRC1CLR_CH8C_Msk (0x80UL)
8835 #define SCU_DMAIRC1CLR_CH7C_Pos (6UL)
8836 #define SCU_DMAIRC1CLR_CH7C_Msk (0x40UL)
8837 #define SCU_DMAIRC1CLR_CH6C_Pos (5UL)
8838 #define SCU_DMAIRC1CLR_CH6C_Msk (0x20UL)
8839 #define SCU_DMAIRC1CLR_CH5C_Pos (4UL)
8840 #define SCU_DMAIRC1CLR_CH5C_Msk (0x10UL)
8841 #define SCU_DMAIRC1CLR_CH4C_Pos (3UL)
8842 #define SCU_DMAIRC1CLR_CH4C_Msk (0x8UL)
8843 #define SCU_DMAIRC1CLR_CH3C_Pos (2UL)
8844 #define SCU_DMAIRC1CLR_CH3C_Msk (0x4UL)
8845 #define SCU_DMAIRC1CLR_CH2C_Pos (1UL)
8846 #define SCU_DMAIRC1CLR_CH2C_Msk (0x2UL)
8847 #define SCU_DMAIRC1CLR_CH1C_Pos (0UL)
8848 #define SCU_DMAIRC1CLR_CH1C_Msk (0x1UL)
8849 /* ======================================================== DMAIRC2 ======================================================== */
8850 #define SCU_DMAIRC2_SDADC_Pos (6UL)
8851 #define SCU_DMAIRC2_SDADC_Msk (0x40UL)
8852 #define SCU_DMAIRC2_GPT12_Pos (5UL)
8853 #define SCU_DMAIRC2_GPT12_Msk (0x20UL)
8854 #define SCU_DMAIRC2_SSC2RDY_Pos (4UL)
8855 #define SCU_DMAIRC2_SSC2RDY_Msk (0x10UL)
8856 #define SCU_DMAIRC2_SSC1RDY_Pos (3UL)
8857 #define SCU_DMAIRC2_SSC1RDY_Msk (0x8UL)
8858 #define SCU_DMAIRC2_TRSEQ2DY_Pos (2UL)
8859 #define SCU_DMAIRC2_TRSEQ2DY_Msk (0x4UL)
8860 #define SCU_DMAIRC2_TRSEQ1DY_Pos (1UL)
8861 #define SCU_DMAIRC2_TRSEQ1DY_Msk (0x2UL)
8862 #define SCU_DMAIRC2_STRDY_Pos (0UL)
8863 #define SCU_DMAIRC2_STRDY_Msk (0x1UL)
8864 /* ====================================================== DMAIRC2CLR ======================================================= */
8865 #define SCU_DMAIRC2CLR_SDADCC_Pos (6UL)
8866 #define SCU_DMAIRC2CLR_SDADCC_Msk (0x40UL)
8867 #define SCU_DMAIRC2CLR_GPT12C_Pos (5UL)
8868 #define SCU_DMAIRC2CLR_GPT12C_Msk (0x20UL)
8869 #define SCU_DMAIRC2CLR_SSC2C_Pos (4UL)
8870 #define SCU_DMAIRC2CLR_SSC2C_Msk (0x10UL)
8871 #define SCU_DMAIRC2CLR_SSC1C_Pos (3UL)
8872 #define SCU_DMAIRC2CLR_SSC1C_Msk (0x8UL)
8873 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos (2UL)
8874 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk (0x4UL)
8875 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos (1UL)
8876 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk (0x2UL)
8877 /* ======================================================= DMASRCCLR ======================================================= */
8878 #define SCU_DMASRCCLR_GPT12_T3C_Pos (7UL)
8879 #define SCU_DMASRCCLR_GPT12_T3C_Msk (0x80UL)
8880 #define SCU_DMASRCCLR_SSCRXC_Pos (6UL)
8881 #define SCU_DMASRCCLR_SSCRXC_Msk (0x40UL)
8882 #define SCU_DMASRCCLR_SSCTXC_Pos (5UL)
8883 #define SCU_DMASRCCLR_SSCTXC_Msk (0x20UL)
8884 /* ======================================================= DMASRCSEL ======================================================= */
8885 #define SCU_DMASRCSEL_GPT12_T3_Pos (7UL)
8886 #define SCU_DMASRCSEL_GPT12_T3_Msk (0x80UL)
8887 #define SCU_DMASRCSEL_SSCRX_Pos (6UL)
8888 #define SCU_DMASRCSEL_SSCRX_Msk (0x40UL)
8889 #define SCU_DMASRCSEL_SSCTX_Pos (5UL)
8890 #define SCU_DMASRCSEL_SSCTX_Msk (0x20UL)
8891 #define SCU_DMASRCSEL_T12PM_DMAEN_Pos (3UL)
8892 #define SCU_DMASRCSEL_T12PM_DMAEN_Msk (0x8UL)
8893 #define SCU_DMASRCSEL_T12ZM_DMAEN_Pos (2UL)
8894 #define SCU_DMASRCSEL_T12ZM_DMAEN_Msk (0x4UL)
8895 #define SCU_DMASRCSEL_SSCRXSRCSEL_Pos (1UL)
8896 #define SCU_DMASRCSEL_SSCRXSRCSEL_Msk (0x2UL)
8897 #define SCU_DMASRCSEL_SSCTXSRCSEL_Pos (0UL)
8898 #define SCU_DMASRCSEL_SSCTXSRCSEL_Msk (0x1UL)
8899 /* ====================================================== DMASRCSEL2 ======================================================= */
8900 #define SCU_DMASRCSEL2_GPT12_DMAEN_Pos (0UL)
8901 #define SCU_DMASRCSEL2_GPT12_DMAEN_Msk (0x3UL)
8902 /* ======================================================== EDCCON ========================================================= */
8903 #define SCU_EDCCON_NVMIE_Pos (2UL)
8904 #define SCU_EDCCON_NVMIE_Msk (0x4UL)
8905 #define SCU_EDCCON_RIE_Pos (0UL)
8906 #define SCU_EDCCON_RIE_Msk (0x1UL)
8907 /* ======================================================== EDCSCLR ======================================================== */
8908 #define SCU_EDCSCLR_RSBEC_Pos (4UL)
8909 #define SCU_EDCSCLR_RSBEC_Msk (0x10UL)
8910 #define SCU_EDCSCLR_NVMDBEC_Pos (2UL)
8911 #define SCU_EDCSCLR_NVMDBEC_Msk (0x4UL)
8912 #define SCU_EDCSCLR_RDBEC_Pos (0UL)
8913 #define SCU_EDCSCLR_RDBEC_Msk (0x1UL)
8914 /* ======================================================== EDCSTAT ======================================================== */
8915 #define SCU_EDCSTAT_RSBE_Pos (4UL)
8916 #define SCU_EDCSTAT_RSBE_Msk (0x10UL)
8917 #define SCU_EDCSTAT_NVMDBE_Pos (2UL)
8918 #define SCU_EDCSTAT_NVMDBE_Msk (0x4UL)
8919 #define SCU_EDCSTAT_RDBE_Pos (0UL)
8920 #define SCU_EDCSTAT_RDBE_Msk (0x1UL)
8921 /* ======================================================== EXICON0 ======================================================== */
8922 #define SCU_EXICON0_MON_Trig_Sel_Pos (6UL)
8923 #define SCU_EXICON0_MON_Trig_Sel_Msk (0xc0UL)
8924 #define SCU_EXICON0_EXINT2_Pos (4UL)
8925 #define SCU_EXICON0_EXINT2_Msk (0x30UL)
8926 #define SCU_EXICON0_EXINT1_Pos (2UL)
8927 #define SCU_EXICON0_EXINT1_Msk (0xcUL)
8928 #define SCU_EXICON0_EXINT0_Pos (0UL)
8929 #define SCU_EXICON0_EXINT0_Msk (0x3UL)
8930 /* ======================================================= GPT12ICLR ======================================================= */
8931 #define SCU_GPT12ICLR_CRC_Pos (5UL)
8932 #define SCU_GPT12ICLR_CRC_Msk (0x20UL)
8933 #define SCU_GPT12ICLR_T6C_Pos (4UL)
8934 #define SCU_GPT12ICLR_T6C_Msk (0x10UL)
8935 #define SCU_GPT12ICLR_T5C_Pos (3UL)
8936 #define SCU_GPT12ICLR_T5C_Msk (0x8UL)
8937 #define SCU_GPT12ICLR_T4C_Pos (2UL)
8938 #define SCU_GPT12ICLR_T4C_Msk (0x4UL)
8939 #define SCU_GPT12ICLR_T3C_Pos (1UL)
8940 #define SCU_GPT12ICLR_T3C_Msk (0x2UL)
8941 #define SCU_GPT12ICLR_T2C_Pos (0UL)
8942 #define SCU_GPT12ICLR_T2C_Msk (0x1UL)
8943 /* ======================================================= GPT12IEN ======================================================== */
8944 #define SCU_GPT12IEN_CRIE_Pos (5UL)
8945 #define SCU_GPT12IEN_CRIE_Msk (0x20UL)
8946 #define SCU_GPT12IEN_T6IE_Pos (4UL)
8947 #define SCU_GPT12IEN_T6IE_Msk (0x10UL)
8948 #define SCU_GPT12IEN_T5IE_Pos (3UL)
8949 #define SCU_GPT12IEN_T5IE_Msk (0x8UL)
8950 #define SCU_GPT12IEN_T4IE_Pos (2UL)
8951 #define SCU_GPT12IEN_T4IE_Msk (0x4UL)
8952 #define SCU_GPT12IEN_T3IE_Pos (1UL)
8953 #define SCU_GPT12IEN_T3IE_Msk (0x2UL)
8954 #define SCU_GPT12IEN_T2IE_Pos (0UL)
8955 #define SCU_GPT12IEN_T2IE_Msk (0x1UL)
8956 /* ======================================================= GPT12IRC ======================================================== */
8957 #define SCU_GPT12IRC_CR_Pos (5UL)
8958 #define SCU_GPT12IRC_CR_Msk (0x20UL)
8959 #define SCU_GPT12IRC_T6_Pos (4UL)
8960 #define SCU_GPT12IRC_T6_Msk (0x10UL)
8961 #define SCU_GPT12IRC_T5_Pos (3UL)
8962 #define SCU_GPT12IRC_T5_Msk (0x8UL)
8963 #define SCU_GPT12IRC_T4_Pos (2UL)
8964 #define SCU_GPT12IRC_T4_Msk (0x4UL)
8965 #define SCU_GPT12IRC_T3_Pos (1UL)
8966 #define SCU_GPT12IRC_T3_Msk (0x2UL)
8967 #define SCU_GPT12IRC_T2_Pos (0UL)
8968 #define SCU_GPT12IRC_T2_Msk (0x1UL)
8969 /* ====================================================== GPT12PISEL ======================================================= */
8970 #define SCU_GPT12PISEL_T3_GPT12_SEL_Pos (5UL)
8971 #define SCU_GPT12PISEL_T3_GPT12_SEL_Msk (0x20UL)
8972 #define SCU_GPT12PISEL_TRIG_CONF_Pos (4UL)
8973 #define SCU_GPT12PISEL_TRIG_CONF_Msk (0x10UL)
8974 #define SCU_GPT12PISEL_GPT12_Pos (0UL)
8975 #define SCU_GPT12PISEL_GPT12_Msk (0xfUL)
8976 /* ========================================================== ID =========================================================== */
8977 #define SCU_ID_PRODID_Pos (3UL)
8978 #define SCU_ID_PRODID_Msk (0xf8UL)
8979 #define SCU_ID_VERID_Pos (0UL)
8980 #define SCU_ID_VERID_Msk (0x7UL)
8981 /* ========================================================= IEN0 ========================================================== */
8982 #define SCU_IEN0_EA_Pos (7UL)
8983 #define SCU_IEN0_EA_Msk (0x80UL)
8984 /* ======================================================== IRCON0 ========================================================= */
8985 #define SCU_IRCON0_MONF_Pos (7UL)
8986 #define SCU_IRCON0_MONF_Msk (0x80UL)
8987 #define SCU_IRCON0_MONR_Pos (6UL)
8988 #define SCU_IRCON0_MONR_Msk (0x40UL)
8989 #define SCU_IRCON0_EXINT2F_Pos (5UL)
8990 #define SCU_IRCON0_EXINT2F_Msk (0x20UL)
8991 #define SCU_IRCON0_EXINT2R_Pos (4UL)
8992 #define SCU_IRCON0_EXINT2R_Msk (0x10UL)
8993 #define SCU_IRCON0_EXINT1F_Pos (3UL)
8994 #define SCU_IRCON0_EXINT1F_Msk (0x8UL)
8995 #define SCU_IRCON0_EXINT1R_Pos (2UL)
8996 #define SCU_IRCON0_EXINT1R_Msk (0x4UL)
8997 #define SCU_IRCON0_EXINT0F_Pos (1UL)
8998 #define SCU_IRCON0_EXINT0F_Msk (0x2UL)
8999 #define SCU_IRCON0_EXINT0R_Pos (0UL)
9000 #define SCU_IRCON0_EXINT0R_Msk (0x1UL)
9001 /* ======================================================= IRCON0CLR ======================================================= */
9002 #define SCU_IRCON0CLR_MONFC_Pos (7UL)
9003 #define SCU_IRCON0CLR_MONFC_Msk (0x80UL)
9004 #define SCU_IRCON0CLR_MONRC_Pos (6UL)
9005 #define SCU_IRCON0CLR_MONRC_Msk (0x40UL)
9006 #define SCU_IRCON0CLR_EXINT2FC_Pos (5UL)
9007 #define SCU_IRCON0CLR_EXINT2FC_Msk (0x20UL)
9008 #define SCU_IRCON0CLR_EXINT2RC_Pos (4UL)
9009 #define SCU_IRCON0CLR_EXINT2RC_Msk (0x10UL)
9010 #define SCU_IRCON0CLR_EXINT1FC_Pos (3UL)
9011 #define SCU_IRCON0CLR_EXINT1FC_Msk (0x8UL)
9012 #define SCU_IRCON0CLR_EXINT1RC_Pos (2UL)
9013 #define SCU_IRCON0CLR_EXINT1RC_Msk (0x4UL)
9014 #define SCU_IRCON0CLR_EXINT0FC_Pos (1UL)
9015 #define SCU_IRCON0CLR_EXINT0FC_Msk (0x2UL)
9016 #define SCU_IRCON0CLR_EXINT0RC_Pos (0UL)
9017 #define SCU_IRCON0CLR_EXINT0RC_Msk (0x1UL)
9018 /* ======================================================== IRCON1 ========================================================= */
9019 #define SCU_IRCON1_RIR_Pos (2UL)
9020 #define SCU_IRCON1_RIR_Msk (0x4UL)
9021 #define SCU_IRCON1_TIR_Pos (1UL)
9022 #define SCU_IRCON1_TIR_Msk (0x2UL)
9023 #define SCU_IRCON1_EIR_Pos (0UL)
9024 #define SCU_IRCON1_EIR_Msk (0x1UL)
9025 /* ======================================================= IRCON1CLR ======================================================= */
9026 #define SCU_IRCON1CLR_RIRC_Pos (2UL)
9027 #define SCU_IRCON1CLR_RIRC_Msk (0x4UL)
9028 #define SCU_IRCON1CLR_TIRC_Pos (1UL)
9029 #define SCU_IRCON1CLR_TIRC_Msk (0x2UL)
9030 #define SCU_IRCON1CLR_EIRC_Pos (0UL)
9031 #define SCU_IRCON1CLR_EIRC_Msk (0x1UL)
9032 /* ======================================================== IRCON2 ========================================================= */
9033 #define SCU_IRCON2_RIR_Pos (2UL)
9034 #define SCU_IRCON2_RIR_Msk (0x4UL)
9035 #define SCU_IRCON2_TIR_Pos (1UL)
9036 #define SCU_IRCON2_TIR_Msk (0x2UL)
9037 #define SCU_IRCON2_EIR_Pos (0UL)
9038 #define SCU_IRCON2_EIR_Msk (0x1UL)
9039 /* ======================================================= IRCON2CLR ======================================================= */
9040 #define SCU_IRCON2CLR_RIRC_Pos (2UL)
9041 #define SCU_IRCON2CLR_RIRC_Msk (0x4UL)
9042 #define SCU_IRCON2CLR_TIRC_Pos (1UL)
9043 #define SCU_IRCON2CLR_TIRC_Msk (0x2UL)
9044 #define SCU_IRCON2CLR_EIRC_Pos (0UL)
9045 #define SCU_IRCON2CLR_EIRC_Msk (0x1UL)
9046 /* ======================================================== IRCON3 ========================================================= */
9047 #define SCU_IRCON3_CCU6SR1_Pos (4UL)
9048 #define SCU_IRCON3_CCU6SR1_Msk (0x10UL)
9049 #define SCU_IRCON3_CCU6SR0_Pos (0UL)
9050 #define SCU_IRCON3_CCU6SR0_Msk (0x1UL)
9051 /* ======================================================= IRCON3CLR ======================================================= */
9052 #define SCU_IRCON3CLR_CCU6SR1C_Pos (4UL)
9053 #define SCU_IRCON3CLR_CCU6SR1C_Msk (0x10UL)
9054 #define SCU_IRCON3CLR_CCU6SR0C_Pos (0UL)
9055 #define SCU_IRCON3CLR_CCU6SR0C_Msk (0x1UL)
9056 /* ======================================================== IRCON4 ========================================================= */
9057 #define SCU_IRCON4_CCU6SR3_Pos (4UL)
9058 #define SCU_IRCON4_CCU6SR3_Msk (0x10UL)
9059 #define SCU_IRCON4_CCU6SR2_Pos (0UL)
9060 #define SCU_IRCON4_CCU6SR2_Msk (0x1UL)
9061 /* ======================================================= IRCON4CLR ======================================================= */
9062 #define SCU_IRCON4CLR_CCU6SR3C_Pos (4UL)
9063 #define SCU_IRCON4CLR_CCU6SR3C_Msk (0x10UL)
9064 #define SCU_IRCON4CLR_CCU6SR2C_Pos (0UL)
9065 #define SCU_IRCON4CLR_CCU6SR2C_Msk (0x1UL)
9066 /* ======================================================== LINSCLR ======================================================== */
9067 #define SCU_LINSCLR_BRKC_Pos (3UL)
9068 #define SCU_LINSCLR_BRKC_Msk (0x8UL)
9069 #define SCU_LINSCLR_EOFSYNC_Pos (4UL)
9070 #define SCU_LINSCLR_EOFSYNC_Msk (0x10UL)
9071 #define SCU_LINSCLR_ERRSYNC_Pos (5UL)
9072 #define SCU_LINSCLR_ERRSYNC_Msk (0x20UL)
9073 /* ========================================================= LINST ========================================================= */
9074 #define SCU_LINST_BRDIS_Pos (0UL)
9075 #define SCU_LINST_BRDIS_Msk (0x1UL)
9076 #define SCU_LINST_BGSEL_Pos (1UL)
9077 #define SCU_LINST_BGSEL_Msk (0x6UL)
9078 #define SCU_LINST_BRK_Pos (3UL)
9079 #define SCU_LINST_BRK_Msk (0x8UL)
9080 #define SCU_LINST_EOFSYN_Pos (4UL)
9081 #define SCU_LINST_EOFSYN_Msk (0x10UL)
9082 #define SCU_LINST_ERRSYN_Pos (5UL)
9083 #define SCU_LINST_ERRSYN_Msk (0x20UL)
9084 #define SCU_LINST_SYNEN_Pos (6UL)
9085 #define SCU_LINST_SYNEN_Msk (0x40UL)
9086 /* ====================================================== MEM_ACC_STS ====================================================== */
9087 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Pos (6UL)
9088 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Msk (0x40UL)
9089 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Pos (5UL)
9090 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Msk (0x20UL)
9091 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Pos (4UL)
9092 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Msk (0x10UL)
9093 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Pos (3UL)
9094 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Msk (0x8UL)
9095 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Pos (2UL)
9096 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Msk (0x4UL)
9097 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Pos (1UL)
9098 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Msk (0x2UL)
9099 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Pos (0UL)
9100 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Msk (0x1UL)
9101 /* ======================================================== MEMSTAT ======================================================== */
9102 #define SCU_MEMSTAT_SASTATUS_Pos (6UL)
9103 #define SCU_MEMSTAT_SASTATUS_Msk (0xc0UL)
9104 #define SCU_MEMSTAT_SECTORINFO_Pos (0UL)
9105 #define SCU_MEMSTAT_SECTORINFO_Msk (0x3fUL)
9106 /* ======================================================== MODIEN1 ======================================================== */
9107 #define SCU_MODIEN1_TIEN1_Pos (7UL)
9108 #define SCU_MODIEN1_TIEN1_Msk (0x80UL)
9109 #define SCU_MODIEN1_RIEN1_Pos (6UL)
9110 #define SCU_MODIEN1_RIEN1_Msk (0x40UL)
9111 #define SCU_MODIEN1_RIREN1_Pos (2UL)
9112 #define SCU_MODIEN1_RIREN1_Msk (0x4UL)
9113 #define SCU_MODIEN1_TIREN1_Pos (1UL)
9114 #define SCU_MODIEN1_TIREN1_Msk (0x2UL)
9115 #define SCU_MODIEN1_EIREN1_Pos (0UL)
9116 #define SCU_MODIEN1_EIREN1_Msk (0x1UL)
9117 /* ======================================================== MODIEN2 ======================================================== */
9118 #define SCU_MODIEN2_TIEN2_Pos (7UL)
9119 #define SCU_MODIEN2_TIEN2_Msk (0x80UL)
9120 #define SCU_MODIEN2_RIEN2_Pos (6UL)
9121 #define SCU_MODIEN2_RIEN2_Msk (0x40UL)
9122 #define SCU_MODIEN2_EXINT2_EN_Pos (5UL)
9123 #define SCU_MODIEN2_EXINT2_EN_Msk (0x20UL)
9124 #define SCU_MODIEN2_RIREN2_Pos (2UL)
9125 #define SCU_MODIEN2_RIREN2_Msk (0x4UL)
9126 #define SCU_MODIEN2_TIREN2_Pos (1UL)
9127 #define SCU_MODIEN2_TIREN2_Msk (0x2UL)
9128 #define SCU_MODIEN2_EIREN2_Pos (0UL)
9129 #define SCU_MODIEN2_EIREN2_Msk (0x1UL)
9130 /* ======================================================== MODIEN3 ======================================================== */
9131 #define SCU_MODIEN3_MONSTS_Pos (5UL)
9132 #define SCU_MODIEN3_MONSTS_Msk (0x20UL)
9133 #define SCU_MODIEN3_MONIE_Pos (4UL)
9134 #define SCU_MODIEN3_MONIE_Msk (0x10UL)
9135 #define SCU_MODIEN3_IE0_Pos (0UL)
9136 #define SCU_MODIEN3_IE0_Msk (0x1UL)
9137 /* ======================================================== MODIEN4 ======================================================== */
9138 #define SCU_MODIEN4_IE1_Pos (0UL)
9139 #define SCU_MODIEN4_IE1_Msk (0x1UL)
9140 /* ======================================================= MODPISEL ======================================================== */
9141 #define SCU_MODPISEL_U_TX_CONDIS_Pos (7UL)
9142 #define SCU_MODPISEL_U_TX_CONDIS_Msk (0x80UL)
9143 #define SCU_MODPISEL_URIOS1_Pos (6UL)
9144 #define SCU_MODPISEL_URIOS1_Msk (0x40UL)
9145 #define SCU_MODPISEL_EXINT2IS_Pos (4UL)
9146 #define SCU_MODPISEL_EXINT2IS_Msk (0x30UL)
9147 #define SCU_MODPISEL_EXINT1IS_Pos (2UL)
9148 #define SCU_MODPISEL_EXINT1IS_Msk (0xcUL)
9149 #define SCU_MODPISEL_EXINT0IS_Pos (0UL)
9150 #define SCU_MODPISEL_EXINT0IS_Msk (0x3UL)
9151 /* ======================================================= MODPISEL1 ======================================================= */
9152 #define SCU_MODPISEL1_T21EXCON_Pos (7UL)
9153 #define SCU_MODPISEL1_T21EXCON_Msk (0x80UL)
9154 #define SCU_MODPISEL1_T2EXCON_Pos (6UL)
9155 #define SCU_MODPISEL1_T2EXCON_Msk (0x40UL)
9156 #define SCU_MODPISEL1_GPT12CAPINB_Pos (0UL)
9157 #define SCU_MODPISEL1_GPT12CAPINB_Msk (0x1UL)
9158 /* ======================================================= MODPISEL2 ======================================================= */
9159 #define SCU_MODPISEL2_T21EXIS_Pos (6UL)
9160 #define SCU_MODPISEL2_T21EXIS_Msk (0xc0UL)
9161 #define SCU_MODPISEL2_T2EXIS_Pos (4UL)
9162 #define SCU_MODPISEL2_T2EXIS_Msk (0x30UL)
9163 #define SCU_MODPISEL2_T21IS_Pos (2UL)
9164 #define SCU_MODPISEL2_T21IS_Msk (0xcUL)
9165 #define SCU_MODPISEL2_T2IS_Pos (0UL)
9166 #define SCU_MODPISEL2_T2IS_Msk (0x3UL)
9167 /* ======================================================= MODPISEL3 ======================================================= */
9168 #define SCU_MODPISEL3_URIOS2_Pos (6UL)
9169 #define SCU_MODPISEL3_URIOS2_Msk (0x40UL)
9170 /* ======================================================= MODSUSP1 ======================================================== */
9171 #define SCU_MODSUSP1_T21_SUSP_Pos (6UL)
9172 #define SCU_MODSUSP1_T21_SUSP_Msk (0x40UL)
9173 #define SCU_MODSUSP1_GPT12_SUSP_Pos (4UL)
9174 #define SCU_MODSUSP1_GPT12_SUSP_Msk (0x10UL)
9175 #define SCU_MODSUSP1_T2_SUSP_Pos (3UL)
9176 #define SCU_MODSUSP1_T2_SUSP_Msk (0x8UL)
9177 #define SCU_MODSUSP1_T13SUSP_Pos (2UL)
9178 #define SCU_MODSUSP1_T13SUSP_Msk (0x4UL)
9179 #define SCU_MODSUSP1_T12SUSP_Pos (1UL)
9180 #define SCU_MODSUSP1_T12SUSP_Msk (0x2UL)
9181 #define SCU_MODSUSP1_WDTSUSP_Pos (0UL)
9182 #define SCU_MODSUSP1_WDTSUSP_Msk (0x1UL)
9183 /* ======================================================= MODSUSP2 ======================================================== */
9184 #define SCU_MODSUSP2_ADC1_SUSP_Pos (2UL)
9185 #define SCU_MODSUSP2_ADC1_SUSP_Msk (0x4UL)
9186 #define SCU_MODSUSP2_MU_SUSP_Pos (1UL)
9187 #define SCU_MODSUSP2_MU_SUSP_Msk (0x2UL)
9188 #define SCU_MODSUSP2_T3_SUSP_Pos (0UL)
9189 #define SCU_MODSUSP2_T3_SUSP_Msk (0x1UL)
9190 /* ======================================================== NMICLR ========================================================= */
9191 #define SCU_NMICLR_NMISUPC_Pos (7UL)
9192 #define SCU_NMICLR_NMISUPC_Msk (0x80UL)
9193 #define SCU_NMICLR_NMIECCC_Pos (6UL)
9194 #define SCU_NMICLR_NMIECCC_Msk (0x40UL)
9195 #define SCU_NMICLR_NMIMAPC_Pos (5UL)
9196 #define SCU_NMICLR_NMIMAPC_Msk (0x20UL)
9197 #define SCU_NMICLR_NMIOWDC_Pos (4UL)
9198 #define SCU_NMICLR_NMIOWDC_Msk (0x10UL)
9199 #define SCU_NMICLR_NMIOTC_Pos (3UL)
9200 #define SCU_NMICLR_NMIOTC_Msk (0x8UL)
9201 #define SCU_NMICLR_NMINVMC_Pos (2UL)
9202 #define SCU_NMICLR_NMINVMC_Msk (0x4UL)
9203 #define SCU_NMICLR_NMIPLLC_Pos (1UL)
9204 #define SCU_NMICLR_NMIPLLC_Msk (0x2UL)
9205 #define SCU_NMICLR_NMIWDTC_Pos (0UL)
9206 #define SCU_NMICLR_NMIWDTC_Msk (0x1UL)
9207 /* ======================================================== NMICON ========================================================= */
9208 #define SCU_NMICON_NMISUP_Pos (7UL)
9209 #define SCU_NMICON_NMISUP_Msk (0x80UL)
9210 #define SCU_NMICON_NMIECC_Pos (6UL)
9211 #define SCU_NMICON_NMIECC_Msk (0x40UL)
9212 #define SCU_NMICON_NMIMAP_Pos (5UL)
9213 #define SCU_NMICON_NMIMAP_Msk (0x20UL)
9214 #define SCU_NMICON_NMIOWD_Pos (4UL)
9215 #define SCU_NMICON_NMIOWD_Msk (0x10UL)
9216 #define SCU_NMICON_NMIOT_Pos (3UL)
9217 #define SCU_NMICON_NMIOT_Msk (0x8UL)
9218 #define SCU_NMICON_NMINVM_Pos (2UL)
9219 #define SCU_NMICON_NMINVM_Msk (0x4UL)
9220 #define SCU_NMICON_NMIPLL_Pos (1UL)
9221 #define SCU_NMICON_NMIPLL_Msk (0x2UL)
9222 #define SCU_NMICON_NMIWDT_Pos (0UL)
9223 #define SCU_NMICON_NMIWDT_Msk (0x1UL)
9224 /* ========================================================= NMISR ========================================================= */
9225 #define SCU_NMISR_FNMISUP_Pos (7UL)
9226 #define SCU_NMISR_FNMISUP_Msk (0x80UL)
9227 #define SCU_NMISR_FNMIECC_Pos (6UL)
9228 #define SCU_NMISR_FNMIECC_Msk (0x40UL)
9229 #define SCU_NMISR_FNMIMAP_Pos (5UL)
9230 #define SCU_NMISR_FNMIMAP_Msk (0x20UL)
9231 #define SCU_NMISR_FNMIOWD_Pos (4UL)
9232 #define SCU_NMISR_FNMIOWD_Msk (0x10UL)
9233 #define SCU_NMISR_FNMIOT_Pos (3UL)
9234 #define SCU_NMISR_FNMIOT_Msk (0x8UL)
9235 #define SCU_NMISR_FNMINVM_Pos (2UL)
9236 #define SCU_NMISR_FNMINVM_Msk (0x4UL)
9237 #define SCU_NMISR_FNMIPLL_Pos (1UL)
9238 #define SCU_NMISR_FNMIPLL_Msk (0x2UL)
9239 #define SCU_NMISR_FNMIWDT_Pos (0UL)
9240 #define SCU_NMISR_FNMIWDT_Msk (0x1UL)
9241 /* ===================================================== NVM_PROT_STS ====================================================== */
9242 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Pos (3UL)
9243 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Msk (0x8UL)
9244 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Pos (2UL)
9245 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Msk (0x4UL)
9246 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Pos (1UL)
9247 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Msk (0x2UL)
9248 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Pos (0UL)
9249 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Msk (0x1UL)
9250 /* ======================================================== OSC_CON ======================================================== */
9251 #define SCU_OSC_CON_OSCTRIM_8_Pos (7UL)
9252 #define SCU_OSC_CON_OSCTRIM_8_Msk (0x80UL)
9253 #define SCU_OSC_CON_XPD_Pos (4UL)
9254 #define SCU_OSC_CON_XPD_Msk (0x10UL)
9255 #define SCU_OSC_CON_OSC2L_Pos (3UL)
9256 #define SCU_OSC_CON_OSC2L_Msk (0x8UL)
9257 #define SCU_OSC_CON_OSCWDTRST_Pos (2UL)
9258 #define SCU_OSC_CON_OSCWDTRST_Msk (0x4UL)
9259 #define SCU_OSC_CON_OSCSS_Pos (0UL)
9260 #define SCU_OSC_CON_OSCSS_Msk (0x3UL)
9261 /* ======================================================= P0_POCON0 ======================================================= */
9262 #define SCU_P0_POCON0_PDM1_Pos (4UL)
9263 #define SCU_P0_POCON0_PDM1_Msk (0x70UL)
9264 #define SCU_P0_POCON0_PDM0_Pos (0UL)
9265 #define SCU_P0_POCON0_PDM0_Msk (0x7UL)
9266 /* ======================================================= P0_POCON1 ======================================================= */
9267 #define SCU_P0_POCON1_PDM3_Pos (4UL)
9268 #define SCU_P0_POCON1_PDM3_Msk (0x70UL)
9269 #define SCU_P0_POCON1_PDM2_Pos (0UL)
9270 #define SCU_P0_POCON1_PDM2_Msk (0x7UL)
9271 /* ======================================================= P0_POCON2 ======================================================= */
9272 #define SCU_P0_POCON2_PDM4_Pos (0UL)
9273 #define SCU_P0_POCON2_PDM4_Msk (0x7UL)
9274 /* ======================================================= P1_POCON0 ======================================================= */
9275 #define SCU_P1_POCON0_PDM1_Pos (4UL)
9276 #define SCU_P1_POCON0_PDM1_Msk (0x70UL)
9277 #define SCU_P1_POCON0_PDM0_Pos (0UL)
9278 #define SCU_P1_POCON0_PDM0_Msk (0x7UL)
9279 /* ======================================================= P1_POCON1 ======================================================= */
9280 #define SCU_P1_POCON1_PDM3_Pos (4UL)
9281 #define SCU_P1_POCON1_PDM3_Msk (0x70UL)
9282 #define SCU_P1_POCON1_PDM2_Pos (0UL)
9283 #define SCU_P1_POCON1_PDM2_Msk (0x7UL)
9284 /* ======================================================= P1_POCON2 ======================================================= */
9285 #define SCU_P1_POCON2_PDM4_Pos (0UL)
9286 #define SCU_P1_POCON2_PDM4_Msk (0x7UL)
9287 /* ======================================================== PASSWD ========================================================= */
9288 #define SCU_PASSWD_PASS_Pos (3UL)
9289 #define SCU_PASSWD_PASS_Msk (0xf8UL)
9290 #define SCU_PASSWD_PROTECT_S_Pos (2UL)
9291 #define SCU_PASSWD_PROTECT_S_Msk (0x4UL)
9292 #define SCU_PASSWD_MODE_Pos (0UL)
9293 #define SCU_PASSWD_MODE_Msk (0x3UL)
9294 /* ======================================================== PLL_CON ======================================================== */
9295 #define SCU_PLL_CON_NDIV_Pos (4UL)
9296 #define SCU_PLL_CON_NDIV_Msk (0xf0UL)
9297 #define SCU_PLL_CON_VCOBYP_Pos (3UL)
9298 #define SCU_PLL_CON_VCOBYP_Msk (0x8UL)
9299 #define SCU_PLL_CON_OSCDISC_Pos (2UL)
9300 #define SCU_PLL_CON_OSCDISC_Msk (0x4UL)
9301 #define SCU_PLL_CON_RESLD_Pos (1UL)
9302 #define SCU_PLL_CON_RESLD_Msk (0x2UL)
9303 #define SCU_PLL_CON_LOCK_Pos (0UL)
9304 #define SCU_PLL_CON_LOCK_Msk (0x1UL)
9305 /* ======================================================== PMCON0 ========================================================= */
9306 #define SCU_PMCON0_SD_Pos (3UL)
9307 #define SCU_PMCON0_SD_Msk (0x8UL)
9308 #define SCU_PMCON0_PD_Pos (2UL)
9309 #define SCU_PMCON0_PD_Msk (0x4UL)
9310 #define SCU_PMCON0_SL_Pos (1UL)
9311 #define SCU_PMCON0_SL_Msk (0x2UL)
9312 #define SCU_PMCON0_XTAL_ON_Pos (0UL)
9313 #define SCU_PMCON0_XTAL_ON_Msk (0x1UL)
9314 /* ======================================================== PMCON1 ========================================================= */
9315 #define SCU_PMCON1_GPT12_DIS_Pos (4UL)
9316 #define SCU_PMCON1_GPT12_DIS_Msk (0x10UL)
9317 #define SCU_PMCON1_T2_DIS_Pos (3UL)
9318 #define SCU_PMCON1_T2_DIS_Msk (0x8UL)
9319 #define SCU_PMCON1_CCU6_DIS_Pos (2UL)
9320 #define SCU_PMCON1_CCU6_DIS_Msk (0x4UL)
9321 #define SCU_PMCON1_SSC1_DIS_Pos (1UL)
9322 #define SCU_PMCON1_SSC1_DIS_Msk (0x2UL)
9323 #define SCU_PMCON1_ADC1_DIS_Pos (0UL)
9324 #define SCU_PMCON1_ADC1_DIS_Msk (0x1UL)
9325 /* ======================================================== PMCON2 ========================================================= */
9326 #define SCU_PMCON2_T3_DIS_Pos (5UL)
9327 #define SCU_PMCON2_T3_DIS_Msk (0x20UL)
9328 #define SCU_PMCON2_T21_DIS_Pos (3UL)
9329 #define SCU_PMCON2_T21_DIS_Msk (0x8UL)
9330 #define SCU_PMCON2_SSC2_DIS_Pos (1UL)
9331 #define SCU_PMCON2_SSC2_DIS_Msk (0x2UL)
9332 /* ======================================================== RSTCON ========================================================= */
9333 #define SCU_RSTCON_LOCKUP_EN_Pos (7UL)
9334 #define SCU_RSTCON_LOCKUP_EN_Msk (0x80UL)
9335 #define SCU_RSTCON_LOCKUP_Pos (0UL)
9336 #define SCU_RSTCON_LOCKUP_Msk (0x1UL)
9337 /* ==================================================== SYS_STRTUP_STS ===================================================== */
9338 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Pos (2UL)
9339 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Msk (0x4UL)
9340 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Pos (1UL)
9341 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Msk (0x2UL)
9342 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Pos (0UL)
9343 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Msk (0x1UL)
9344 /* ======================================================== SYSCON0 ======================================================== */
9345 #define SCU_SYSCON0_SYSCLKSEL_Pos (6UL)
9346 #define SCU_SYSCON0_SYSCLKSEL_Msk (0xc0UL)
9347 #define SCU_SYSCON0_NVMCLKFAC_Pos (4UL)
9348 #define SCU_SYSCON0_NVMCLKFAC_Msk (0x30UL)
9349 /* ========================================================= TCCR ========================================================== */
9350 #define SCU_TCCR_TCC_Pos (0UL)
9351 #define SCU_TCCR_TCC_Msk (0x3UL)
9352 /* ======================================================== WDTCON ========================================================= */
9353 #define SCU_WDTCON_WINBEN_Pos (5UL)
9354 #define SCU_WDTCON_WINBEN_Msk (0x20UL)
9355 #define SCU_WDTCON_WDTPR_Pos (4UL)
9356 #define SCU_WDTCON_WDTPR_Msk (0x10UL)
9357 #define SCU_WDTCON_WDTEN_Pos (2UL)
9358 #define SCU_WDTCON_WDTEN_Msk (0x4UL)
9359 #define SCU_WDTCON_WDTRS_Pos (1UL)
9360 #define SCU_WDTCON_WDTRS_Msk (0x2UL)
9361 #define SCU_WDTCON_WDTIN_Pos (0UL)
9362 #define SCU_WDTCON_WDTIN_Msk (0x1UL)
9363 /* ========================================================= WDTH ========================================================== */
9364 #define SCU_WDTH_WDT_Pos (0UL)
9365 #define SCU_WDTH_WDT_Msk (0xffUL)
9366 /* ========================================================= WDTL ========================================================== */
9367 #define SCU_WDTL_WDT_Pos (0UL)
9368 #define SCU_WDTL_WDT_Msk (0xffUL)
9369 /* ======================================================== WDTREL ========================================================= */
9370 #define SCU_WDTREL_WDTREL_Pos (0UL)
9371 #define SCU_WDTREL_WDTREL_Msk (0xffUL)
9372 /* ======================================================== WDTWINB ======================================================== */
9373 #define SCU_WDTWINB_WDTWINB_Pos (0UL)
9374 #define SCU_WDTWINB_WDTWINB_Msk (0xffUL)
9377 /* =========================================================================================================================== */
9378 /* ================ SCUPM ================ */
9379 /* =========================================================================================================================== */
9380 
9381 /* ====================================================== AMCLK_CTRL ======================================================= */
9382 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos (0UL)
9383 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk (0x1UL)
9384 /* ==================================================== AMCLK_FREQ_STS ===================================================== */
9385 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Pos (8UL)
9386 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Msk (0x3f00UL)
9387 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Pos (0UL)
9388 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Msk (0x3fUL)
9389 /* ===================================================== AMCLK_TH_HYS ====================================================== */
9390 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos (30UL)
9391 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk (0xc0000000UL)
9392 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos (24UL)
9393 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk (0x3f000000UL)
9394 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos (22UL)
9395 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk (0xc00000UL)
9396 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos (16UL)
9397 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk (0x3f0000UL)
9398 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos (14UL)
9399 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk (0xc000UL)
9400 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos (8UL)
9401 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk (0x3f00UL)
9402 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos (6UL)
9403 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk (0xc0UL)
9404 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos (0UL)
9405 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk (0x3fUL)
9406 /* ===================================================== BDRV_IRQ_CTRL ===================================================== */
9407 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Pos (20UL)
9408 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Msk (0x100000UL)
9409 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Pos (19UL)
9410 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Msk (0x80000UL)
9411 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Pos (18UL)
9412 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Msk (0x40000UL)
9413 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Pos (17UL)
9414 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Msk (0x20000UL)
9415 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos (16UL)
9416 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk (0x10000UL)
9417 #define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos (15UL)
9418 #define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk (0x8000UL)
9419 #define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos (14UL)
9420 #define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk (0x4000UL)
9421 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos (13UL)
9422 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk (0x2000UL)
9423 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos (12UL)
9424 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk (0x1000UL)
9425 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos (11UL)
9426 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk (0x800UL)
9427 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos (10UL)
9428 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk (0x400UL)
9429 #define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos (5UL)
9430 #define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk (0x20UL)
9431 #define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos (4UL)
9432 #define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk (0x10UL)
9433 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos (3UL)
9434 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk (0x8UL)
9435 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos (2UL)
9436 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk (0x4UL)
9437 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos (1UL)
9438 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk (0x2UL)
9439 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos (0UL)
9440 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk (0x1UL)
9441 /* ======================================================== BDRV_IS ======================================================== */
9442 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Pos (28UL)
9443 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Msk (0x10000000UL)
9444 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Pos (27UL)
9445 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Msk (0x8000000UL)
9446 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Pos (26UL)
9447 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Msk (0x4000000UL)
9448 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Pos (25UL)
9449 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Msk (0x2000000UL)
9450 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Pos (24UL)
9451 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Msk (0x1000000UL)
9452 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Pos (20UL)
9453 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Msk (0x100000UL)
9454 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Pos (19UL)
9455 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Msk (0x80000UL)
9456 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Pos (18UL)
9457 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Msk (0x40000UL)
9458 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Pos (17UL)
9459 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Msk (0x20000UL)
9460 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos (16UL)
9461 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk (0x10000UL)
9462 #define SCUPM_BDRV_IS_HS3_OC_IS_Pos (15UL)
9463 #define SCUPM_BDRV_IS_HS3_OC_IS_Msk (0x8000UL)
9464 #define SCUPM_BDRV_IS_LS3_OC_IS_Pos (14UL)
9465 #define SCUPM_BDRV_IS_LS3_OC_IS_Msk (0x4000UL)
9466 #define SCUPM_BDRV_IS_HS2_OC_IS_Pos (13UL)
9467 #define SCUPM_BDRV_IS_HS2_OC_IS_Msk (0x2000UL)
9468 #define SCUPM_BDRV_IS_HS1_OC_IS_Pos (12UL)
9469 #define SCUPM_BDRV_IS_HS1_OC_IS_Msk (0x1000UL)
9470 #define SCUPM_BDRV_IS_LS2_OC_IS_Pos (11UL)
9471 #define SCUPM_BDRV_IS_LS2_OC_IS_Msk (0x800UL)
9472 #define SCUPM_BDRV_IS_LS1_OC_IS_Pos (10UL)
9473 #define SCUPM_BDRV_IS_LS1_OC_IS_Msk (0x400UL)
9474 #define SCUPM_BDRV_IS_HS3_DS_IS_Pos (5UL)
9475 #define SCUPM_BDRV_IS_HS3_DS_IS_Msk (0x20UL)
9476 #define SCUPM_BDRV_IS_LS3_DS_IS_Pos (4UL)
9477 #define SCUPM_BDRV_IS_LS3_DS_IS_Msk (0x10UL)
9478 #define SCUPM_BDRV_IS_HS2_DS_IS_Pos (3UL)
9479 #define SCUPM_BDRV_IS_HS2_DS_IS_Msk (0x8UL)
9480 #define SCUPM_BDRV_IS_HS1_DS_IS_Pos (2UL)
9481 #define SCUPM_BDRV_IS_HS1_DS_IS_Msk (0x4UL)
9482 #define SCUPM_BDRV_IS_LS2_DS_IS_Pos (1UL)
9483 #define SCUPM_BDRV_IS_LS2_DS_IS_Msk (0x2UL)
9484 #define SCUPM_BDRV_IS_LS1_DS_IS_Pos (0UL)
9485 #define SCUPM_BDRV_IS_LS1_DS_IS_Msk (0x1UL)
9486 /* ====================================================== BDRV_ISCLR ======================================================= */
9487 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Pos (28UL)
9488 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Msk (0x10000000UL)
9489 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Pos (27UL)
9490 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Msk (0x8000000UL)
9491 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Pos (26UL)
9492 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Msk (0x4000000UL)
9493 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Pos (25UL)
9494 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Msk (0x2000000UL)
9495 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Pos (24UL)
9496 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Msk (0x1000000UL)
9497 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Pos (20UL)
9498 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Msk (0x100000UL)
9499 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Pos (19UL)
9500 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Msk (0x80000UL)
9501 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Pos (18UL)
9502 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Msk (0x40000UL)
9503 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Pos (17UL)
9504 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Msk (0x20000UL)
9505 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos (16UL)
9506 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk (0x10000UL)
9507 #define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Pos (15UL)
9508 #define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk (0x8000UL)
9509 #define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Pos (14UL)
9510 #define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk (0x4000UL)
9511 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos (13UL)
9512 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk (0x2000UL)
9513 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos (12UL)
9514 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk (0x1000UL)
9515 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos (11UL)
9516 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk (0x800UL)
9517 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos (10UL)
9518 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk (0x400UL)
9519 #define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Pos (5UL)
9520 #define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk (0x20UL)
9521 #define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Pos (4UL)
9522 #define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk (0x10UL)
9523 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos (3UL)
9524 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk (0x8UL)
9525 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos (2UL)
9526 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk (0x4UL)
9527 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos (1UL)
9528 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk (0x2UL)
9529 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos (0UL)
9530 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk (0x1UL)
9531 /* ========================================================= BFSTS ========================================================= */
9532 #define SCUPM_BFSTS_SBFSTS_Pos (1UL)
9533 #define SCUPM_BFSTS_SBFSTS_Msk (0x2UL)
9534 #define SCUPM_BFSTS_DBFSTS_Pos (0UL)
9535 #define SCUPM_BFSTS_DBFSTS_Msk (0x1UL)
9536 /* ======================================================= BFSTS_CLR ======================================================= */
9537 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Pos (1UL)
9538 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Msk (0x2UL)
9539 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Pos (0UL)
9540 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Msk (0x1UL)
9541 /* ========================================================= DBFA ========================================================== */
9542 #define SCUPM_DBFA_DBFA_Pos (0UL)
9543 #define SCUPM_DBFA_DBFA_Msk (0xffffffffUL)
9544 /* ===================================================== PCU_CTRL_STS ====================================================== */
9545 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos (26UL)
9546 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk (0x4000000UL)
9547 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos (25UL)
9548 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk (0x2000000UL)
9549 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Pos (24UL)
9550 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Msk (0x1000000UL)
9551 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Pos (14UL)
9552 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Msk (0x4000UL)
9553 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos (8UL)
9554 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk (0x100UL)
9555 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos (7UL)
9556 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk (0x80UL)
9557 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos (1UL)
9558 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk (0x2UL)
9559 /* ========================================================= SBFA ========================================================== */
9560 #define SCUPM_SBFA_SBFA_Pos (0UL)
9561 #define SCUPM_SBFA_SBFA_Msk (0xffffffffUL)
9562 /* ======================================================== STCALIB ======================================================== */
9563 #define SCUPM_STCALIB_STCALIB_Pos (0UL)
9564 #define SCUPM_STCALIB_STCALIB_Msk (0x3ffffffUL)
9565 /* ===================================================== SYS_IRQ_CTRL ====================================================== */
9566 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Pos (23UL)
9567 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Msk (0x800000UL)
9568 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Pos (22UL)
9569 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Msk (0x400000UL)
9570 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Pos (21UL)
9571 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Msk (0x200000UL)
9572 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Pos (20UL)
9573 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Msk (0x100000UL)
9574 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Pos (19UL)
9575 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Msk (0x80000UL)
9576 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Pos (18UL)
9577 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Msk (0x40000UL)
9578 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Pos (17UL)
9579 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Msk (0x20000UL)
9580 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Pos (16UL)
9581 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Msk (0x10000UL)
9582 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Pos (15UL)
9583 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Msk (0x8000UL)
9584 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Pos (14UL)
9585 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Msk (0x4000UL)
9586 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Pos (13UL)
9587 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Msk (0x2000UL)
9588 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Pos (12UL)
9589 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Msk (0x1000UL)
9590 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Pos (11UL)
9591 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Msk (0x800UL)
9592 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Pos (10UL)
9593 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Msk (0x400UL)
9594 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Pos (9UL)
9595 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Msk (0x200UL)
9596 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Pos (8UL)
9597 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Msk (0x100UL)
9598 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Pos (7UL)
9599 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Msk (0x80UL)
9600 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Pos (6UL)
9601 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Msk (0x40UL)
9602 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Pos (2UL)
9603 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Msk (0x4UL)
9604 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Pos (1UL)
9605 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Msk (0x2UL)
9606 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Pos (0UL)
9607 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Msk (0x1UL)
9608 /* ======================================================== SYS_IS ========================================================= */
9609 #define SCUPM_SYS_IS_PHW_ZCHI_STS_Pos (29UL)
9610 #define SCUPM_SYS_IS_PHW_ZCHI_STS_Msk (0x20000000UL)
9611 #define SCUPM_SYS_IS_PHW_ZCLOW_STS_Pos (28UL)
9612 #define SCUPM_SYS_IS_PHW_ZCLOW_STS_Msk (0x10000000UL)
9613 #define SCUPM_SYS_IS_PHV_ZCHI_STS_Pos (27UL)
9614 #define SCUPM_SYS_IS_PHV_ZCHI_STS_Msk (0x8000000UL)
9615 #define SCUPM_SYS_IS_PHV_ZCLOW_STS_Pos (26UL)
9616 #define SCUPM_SYS_IS_PHV_ZCLOW_STS_Msk (0x4000000UL)
9617 #define SCUPM_SYS_IS_PHU_ZCHI_STS_Pos (25UL)
9618 #define SCUPM_SYS_IS_PHU_ZCHI_STS_Msk (0x2000000UL)
9619 #define SCUPM_SYS_IS_PHU_ZCLOW_STS_Pos (24UL)
9620 #define SCUPM_SYS_IS_PHU_ZCLOW_STS_Msk (0x1000000UL)
9621 #define SCUPM_SYS_IS_ADC4_EOC_IS_Pos (23UL)
9622 #define SCUPM_SYS_IS_ADC4_EOC_IS_Msk (0x800000UL)
9623 #define SCUPM_SYS_IS_ADC3_EOC_IS_Pos (22UL)
9624 #define SCUPM_SYS_IS_ADC3_EOC_IS_Msk (0x400000UL)
9625 #define SCUPM_SYS_IS_PHW_ZCHI_IS_Pos (21UL)
9626 #define SCUPM_SYS_IS_PHW_ZCHI_IS_Msk (0x200000UL)
9627 #define SCUPM_SYS_IS_PHW_ZCLOW_IS_Pos (20UL)
9628 #define SCUPM_SYS_IS_PHW_ZCLOW_IS_Msk (0x100000UL)
9629 #define SCUPM_SYS_IS_PHV_ZCHI_IS_Pos (19UL)
9630 #define SCUPM_SYS_IS_PHV_ZCHI_IS_Msk (0x80000UL)
9631 #define SCUPM_SYS_IS_PHV_ZCLOW_IS_Pos (18UL)
9632 #define SCUPM_SYS_IS_PHV_ZCLOW_IS_Msk (0x40000UL)
9633 #define SCUPM_SYS_IS_PHU_ZCHI_IS_Pos (17UL)
9634 #define SCUPM_SYS_IS_PHU_ZCHI_IS_Msk (0x20000UL)
9635 #define SCUPM_SYS_IS_PHU_ZCLOW_IS_Pos (16UL)
9636 #define SCUPM_SYS_IS_PHU_ZCLOW_IS_Msk (0x10000UL)
9637 #define SCUPM_SYS_IS_ADC2_ESM_IS_Pos (15UL)
9638 #define SCUPM_SYS_IS_ADC2_ESM_IS_Msk (0x8000UL)
9639 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Pos (14UL)
9640 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Msk (0x4000UL)
9641 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Pos (13UL)
9642 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Msk (0x2000UL)
9643 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Pos (12UL)
9644 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Msk (0x1000UL)
9645 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Pos (11UL)
9646 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Msk (0x800UL)
9647 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Pos (10UL)
9648 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Msk (0x400UL)
9649 #define SCUPM_SYS_IS_SYS_OT_IS_Pos (9UL)
9650 #define SCUPM_SYS_IS_SYS_OT_IS_Msk (0x200UL)
9651 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Pos (8UL)
9652 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Msk (0x100UL)
9653 #define SCUPM_SYS_IS_PMU_OT_IS_Pos (7UL)
9654 #define SCUPM_SYS_IS_PMU_OT_IS_Msk (0x80UL)
9655 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Pos (6UL)
9656 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Msk (0x40UL)
9657 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Pos (2UL)
9658 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Msk (0x4UL)
9659 #define SCUPM_SYS_IS_LIN_OT_IS_Pos (1UL)
9660 #define SCUPM_SYS_IS_LIN_OT_IS_Msk (0x2UL)
9661 #define SCUPM_SYS_IS_LIN_OC_IS_Pos (0UL)
9662 #define SCUPM_SYS_IS_LIN_OC_IS_Msk (0x1UL)
9663 /* ======================================================= SYS_ISCLR ======================================================= */
9664 #define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Pos (29UL)
9665 #define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Msk (0x20000000UL)
9666 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Pos (28UL)
9667 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Msk (0x10000000UL)
9668 #define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Pos (27UL)
9669 #define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Msk (0x8000000UL)
9670 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Pos (26UL)
9671 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Msk (0x4000000UL)
9672 #define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Pos (25UL)
9673 #define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Msk (0x2000000UL)
9674 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Pos (24UL)
9675 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Msk (0x1000000UL)
9676 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Pos (23UL)
9677 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Msk (0x800000UL)
9678 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Pos (22UL)
9679 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Msk (0x400000UL)
9680 #define SCUPM_SYS_ISCLR_PHW_ZCHI_ICLR_Pos (21UL)
9681 #define SCUPM_SYS_ISCLR_PHW_ZCHI_ICLR_Msk (0x200000UL)
9682 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_ICLR_Pos (20UL)
9683 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_ICLR_Msk (0x100000UL)
9684 #define SCUPM_SYS_ISCLR_PHV_ZCHI_ICLR_Pos (19UL)
9685 #define SCUPM_SYS_ISCLR_PHV_ZCHI_ICLR_Msk (0x80000UL)
9686 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_ICLR_Pos (18UL)
9687 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_ICLR_Msk (0x40000UL)
9688 #define SCUPM_SYS_ISCLR_PHU_ZCHI_ICLR_Pos (17UL)
9689 #define SCUPM_SYS_ISCLR_PHU_ZCHI_ICLR_Msk (0x20000UL)
9690 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_ICLR_Pos (16UL)
9691 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_ICLR_Msk (0x10000UL)
9692 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Pos (15UL)
9693 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Msk (0x8000UL)
9694 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Pos (14UL)
9695 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Msk (0x4000UL)
9696 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Pos (13UL)
9697 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Msk (0x2000UL)
9698 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Pos (12UL)
9699 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Msk (0x1000UL)
9700 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Pos (11UL)
9701 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Msk (0x800UL)
9702 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Pos (10UL)
9703 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Msk (0x400UL)
9704 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Pos (9UL)
9705 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Msk (0x200UL)
9706 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Pos (8UL)
9707 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Msk (0x100UL)
9708 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Pos (7UL)
9709 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Msk (0x80UL)
9710 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Pos (6UL)
9711 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Msk (0x40UL)
9712 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Pos (2UL)
9713 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Msk (0x4UL)
9714 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Pos (1UL)
9715 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Msk (0x2UL)
9716 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Pos (0UL)
9717 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Msk (0x1UL)
9718 /* ================================================== SYS_SUPPLY_IRQ_CLR =================================================== */
9719 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Pos (23UL)
9720 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Msk (0x800000UL)
9721 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Pos (22UL)
9722 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Msk (0x400000UL)
9723 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Pos (21UL)
9724 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Msk (0x200000UL)
9725 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_SCLR_Pos (20UL)
9726 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_SCLR_Msk (0x100000UL)
9727 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Pos (19UL)
9728 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Msk (0x80000UL)
9729 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Pos (18UL)
9730 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Msk (0x40000UL)
9731 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Pos (17UL)
9732 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Msk (0x20000UL)
9733 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_SCLR_Pos (16UL)
9734 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_SCLR_Msk (0x10000UL)
9735 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Pos (7UL)
9736 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Msk (0x80UL)
9737 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Pos (6UL)
9738 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Msk (0x40UL)
9739 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Pos (5UL)
9740 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Msk (0x20UL)
9741 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_ICLR_Pos (4UL)
9742 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_ICLR_Msk (0x10UL)
9743 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Pos (3UL)
9744 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Msk (0x8UL)
9745 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Pos (2UL)
9746 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Msk (0x4UL)
9747 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Pos (1UL)
9748 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Msk (0x2UL)
9749 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_ICLR_Pos (0UL)
9750 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_ICLR_Msk (0x1UL)
9751 /* ================================================== SYS_SUPPLY_IRQ_CTRL ================================================== */
9752 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Pos (7UL)
9753 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Msk (0x80UL)
9754 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Pos (6UL)
9755 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Msk (0x40UL)
9756 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Pos (5UL)
9757 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Msk (0x20UL)
9758 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_OV_IE_Pos (4UL)
9759 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_OV_IE_Msk (0x10UL)
9760 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Pos (3UL)
9761 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Msk (0x8UL)
9762 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Pos (2UL)
9763 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Msk (0x4UL)
9764 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Pos (1UL)
9765 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Msk (0x2UL)
9766 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_UV_IE_Pos (0UL)
9767 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_UV_IE_Msk (0x1UL)
9768 /* ================================================== SYS_SUPPLY_IRQ_STS =================================================== */
9769 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Pos (23UL)
9770 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Msk (0x800000UL)
9771 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Pos (22UL)
9772 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Msk (0x400000UL)
9773 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Pos (21UL)
9774 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Msk (0x200000UL)
9775 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_STS_Pos (20UL)
9776 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_STS_Msk (0x100000UL)
9777 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Pos (19UL)
9778 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Msk (0x80000UL)
9779 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Pos (18UL)
9780 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Msk (0x40000UL)
9781 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Pos (17UL)
9782 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Msk (0x20000UL)
9783 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_STS_Pos (16UL)
9784 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_STS_Msk (0x10000UL)
9785 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Pos (7UL)
9786 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Msk (0x80UL)
9787 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Pos (6UL)
9788 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Msk (0x40UL)
9789 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Pos (5UL)
9790 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Msk (0x20UL)
9791 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_IS_Pos (4UL)
9792 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_IS_Msk (0x10UL)
9793 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Pos (3UL)
9794 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Msk (0x8UL)
9795 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Pos (2UL)
9796 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Msk (0x4UL)
9797 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Pos (1UL)
9798 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Msk (0x2UL)
9799 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_IS_Pos (0UL)
9800 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_IS_Msk (0x1UL)
9801 /* ======================================================= WDT1_TRIG ======================================================= */
9802 #define SCUPM_WDT1_TRIG_SOWCONF_Pos (6UL)
9803 #define SCUPM_WDT1_TRIG_SOWCONF_Msk (0xc0UL)
9804 #define SCUPM_WDT1_TRIG_WDP_SEL_Pos (0UL)
9805 #define SCUPM_WDT1_TRIG_WDP_SEL_Msk (0x3fUL)
9808 /* =========================================================================================================================== */
9809 /* ================ SSC1 ================ */
9810 /* =========================================================================================================================== */
9811 
9812 /* ========================================================== BR =========================================================== */
9813 #define SSC1_BR_BR_VALUE_Pos (0UL)
9814 #define SSC1_BR_BR_VALUE_Msk (0xffffUL)
9815 /* ========================================================== CON ========================================================== */
9816 #define SSC1_CON_BC_Pos (0UL)
9817 #define SSC1_CON_BC_Msk (0xfUL)
9818 #define SSC1_CON_TE_Pos (8UL)
9819 #define SSC1_CON_TE_Msk (0x100UL)
9820 #define SSC1_CON_RE_Pos (9UL)
9821 #define SSC1_CON_RE_Msk (0x200UL)
9822 #define SSC1_CON_PE_Pos (10UL)
9823 #define SSC1_CON_PE_Msk (0x400UL)
9824 #define SSC1_CON_BE_Pos (11UL)
9825 #define SSC1_CON_BE_Msk (0x800UL)
9826 #define SSC1_CON_BSY_Pos (12UL)
9827 #define SSC1_CON_BSY_Msk (0x1000UL)
9828 #define SSC1_CON_MS_Pos (14UL)
9829 #define SSC1_CON_MS_Msk (0x4000UL)
9830 #define SSC1_CON_EN_Pos (15UL)
9831 #define SSC1_CON_EN_Msk (0x8000UL)
9832 /* ======================================================== ISRCLR ========================================================= */
9833 #define SSC1_ISRCLR_TECLR_Pos (8UL)
9834 #define SSC1_ISRCLR_TECLR_Msk (0x100UL)
9835 #define SSC1_ISRCLR_RECLR_Pos (9UL)
9836 #define SSC1_ISRCLR_RECLR_Msk (0x200UL)
9837 #define SSC1_ISRCLR_PECLR_Pos (10UL)
9838 #define SSC1_ISRCLR_PECLR_Msk (0x400UL)
9839 #define SSC1_ISRCLR_BECLR_Pos (11UL)
9840 #define SSC1_ISRCLR_BECLR_Msk (0x800UL)
9841 /* ========================================================= PISEL ========================================================= */
9842 #define SSC1_PISEL_MIS_0_Pos (0UL)
9843 #define SSC1_PISEL_MIS_0_Msk (0x1UL)
9844 #define SSC1_PISEL_SIS_Pos (1UL)
9845 #define SSC1_PISEL_SIS_Msk (0x2UL)
9846 #define SSC1_PISEL_CIS_Pos (2UL)
9847 #define SSC1_PISEL_CIS_Msk (0x4UL)
9848 #define SSC1_PISEL_MIS_1_Pos (3UL)
9849 #define SSC1_PISEL_MIS_1_Msk (0x8UL)
9850 /* ========================================================== RB =========================================================== */
9851 #define SSC1_RB_RB_VALUE_Pos (0UL)
9852 #define SSC1_RB_RB_VALUE_Msk (0xffffUL)
9853 /* ========================================================== TB =========================================================== */
9854 #define SSC1_TB_TB_VALUE_Pos (0UL)
9855 #define SSC1_TB_TB_VALUE_Msk (0xffffUL)
9858 /* =========================================================================================================================== */
9859 /* ================ SSC2 ================ */
9860 /* =========================================================================================================================== */
9861 
9862 /* ========================================================== BR =========================================================== */
9863 #define SSC2_BR_BR_VALUE_Pos (0UL)
9864 #define SSC2_BR_BR_VALUE_Msk (0xffffUL)
9865 /* ========================================================== CON ========================================================== */
9866 #define SSC2_CON_BC_Pos (0UL)
9867 #define SSC2_CON_BC_Msk (0xfUL)
9868 #define SSC2_CON_TE_Pos (8UL)
9869 #define SSC2_CON_TE_Msk (0x100UL)
9870 #define SSC2_CON_RE_Pos (9UL)
9871 #define SSC2_CON_RE_Msk (0x200UL)
9872 #define SSC2_CON_PE_Pos (10UL)
9873 #define SSC2_CON_PE_Msk (0x400UL)
9874 #define SSC2_CON_BE_Pos (11UL)
9875 #define SSC2_CON_BE_Msk (0x800UL)
9876 #define SSC2_CON_BSY_Pos (12UL)
9877 #define SSC2_CON_BSY_Msk (0x1000UL)
9878 #define SSC2_CON_MS_Pos (14UL)
9879 #define SSC2_CON_MS_Msk (0x4000UL)
9880 #define SSC2_CON_EN_Pos (15UL)
9881 #define SSC2_CON_EN_Msk (0x8000UL)
9882 /* ======================================================== ISRCLR ========================================================= */
9883 #define SSC2_ISRCLR_TECLR_Pos (8UL)
9884 #define SSC2_ISRCLR_TECLR_Msk (0x100UL)
9885 #define SSC2_ISRCLR_RECLR_Pos (9UL)
9886 #define SSC2_ISRCLR_RECLR_Msk (0x200UL)
9887 #define SSC2_ISRCLR_PECLR_Pos (10UL)
9888 #define SSC2_ISRCLR_PECLR_Msk (0x400UL)
9889 #define SSC2_ISRCLR_BECLR_Pos (11UL)
9890 #define SSC2_ISRCLR_BECLR_Msk (0x800UL)
9891 /* ========================================================= PISEL ========================================================= */
9892 #define SSC2_PISEL_MIS_0_Pos (0UL)
9893 #define SSC2_PISEL_MIS_0_Msk (0x1UL)
9894 #define SSC2_PISEL_SIS_Pos (1UL)
9895 #define SSC2_PISEL_SIS_Msk (0x2UL)
9896 #define SSC2_PISEL_CIS_Pos (2UL)
9897 #define SSC2_PISEL_CIS_Msk (0x4UL)
9898 #define SSC2_PISEL_MIS_1_Pos (3UL)
9899 #define SSC2_PISEL_MIS_1_Msk (0x8UL)
9900 /* ========================================================== RB =========================================================== */
9901 #define SSC2_RB_RB_VALUE_Pos (0UL)
9902 #define SSC2_RB_RB_VALUE_Msk (0xffffUL)
9903 /* ========================================================== TB =========================================================== */
9904 #define SSC2_TB_TB_VALUE_Pos (0UL)
9905 #define SSC2_TB_TB_VALUE_Msk (0xffffUL)
9908 /* =========================================================================================================================== */
9909 /* ================ TIMER2 ================ */
9910 /* =========================================================================================================================== */
9911 
9912 /* ========================================================= RC2H ========================================================== */
9913 #define TIMER2_RC2H_RC2_Pos (0UL)
9914 #define TIMER2_RC2H_RC2_Msk (0xffUL)
9915 /* ========================================================= RC2L ========================================================== */
9916 #define TIMER2_RC2L_RC2_Pos (0UL)
9917 #define TIMER2_RC2L_RC2_Msk (0xffUL)
9918 /* ========================================================= T2CON ========================================================= */
9919 #define TIMER2_T2CON_CP_RL2_Pos (0UL)
9920 #define TIMER2_T2CON_CP_RL2_Msk (0x1UL)
9921 #define TIMER2_T2CON_C_T2_Pos (1UL)
9922 #define TIMER2_T2CON_C_T2_Msk (0x2UL)
9923 #define TIMER2_T2CON_TR2_Pos (2UL)
9924 #define TIMER2_T2CON_TR2_Msk (0x4UL)
9925 #define TIMER2_T2CON_EXEN2_Pos (3UL)
9926 #define TIMER2_T2CON_EXEN2_Msk (0x8UL)
9927 #define TIMER2_T2CON_EXF2_Pos (6UL)
9928 #define TIMER2_T2CON_EXF2_Msk (0x40UL)
9929 #define TIMER2_T2CON_TF2_Pos (7UL)
9930 #define TIMER2_T2CON_TF2_Msk (0x80UL)
9931 /* ======================================================== T2CON1 ========================================================= */
9932 #define TIMER2_T2CON1_EXF2EN_Pos (0UL)
9933 #define TIMER2_T2CON1_EXF2EN_Msk (0x1UL)
9934 #define TIMER2_T2CON1_TF2EN_Pos (1UL)
9935 #define TIMER2_T2CON1_TF2EN_Msk (0x2UL)
9936 /* ========================================================== T2H ========================================================== */
9937 #define TIMER2_T2H_T2H_Pos (0UL)
9938 #define TIMER2_T2H_T2H_Msk (0xffUL)
9939 /* ======================================================== T2ICLR ========================================================= */
9940 #define TIMER2_T2ICLR_EXF2CLR_Pos (6UL)
9941 #define TIMER2_T2ICLR_EXF2CLR_Msk (0x40UL)
9942 #define TIMER2_T2ICLR_TF2CLR_Pos (7UL)
9943 #define TIMER2_T2ICLR_TF2CLR_Msk (0x80UL)
9944 /* ========================================================== T2L ========================================================== */
9945 #define TIMER2_T2L_T2L_Pos (0UL)
9946 #define TIMER2_T2L_T2L_Msk (0xffUL)
9947 /* ========================================================= T2MOD ========================================================= */
9948 #define TIMER2_T2MOD_DCEN_Pos (0UL)
9949 #define TIMER2_T2MOD_DCEN_Msk (0x1UL)
9950 #define TIMER2_T2MOD_T2PRE_Pos (1UL)
9951 #define TIMER2_T2MOD_T2PRE_Msk (0xeUL)
9952 #define TIMER2_T2MOD_PREN_Pos (4UL)
9953 #define TIMER2_T2MOD_PREN_Msk (0x10UL)
9954 #define TIMER2_T2MOD_EDGESEL_Pos (5UL)
9955 #define TIMER2_T2MOD_EDGESEL_Msk (0x20UL)
9956 #define TIMER2_T2MOD_T2RHEN_Pos (6UL)
9957 #define TIMER2_T2MOD_T2RHEN_Msk (0x40UL)
9958 #define TIMER2_T2MOD_T2REGS_Pos (7UL)
9959 #define TIMER2_T2MOD_T2REGS_Msk (0x80UL)
9962 /* =========================================================================================================================== */
9963 /* ================ TIMER21 ================ */
9964 /* =========================================================================================================================== */
9965 
9966 /* ========================================================= RC2H ========================================================== */
9967 #define TIMER21_RC2H_RC2_Pos (0UL)
9968 #define TIMER21_RC2H_RC2_Msk (0xffUL)
9969 /* ========================================================= RC2L ========================================================== */
9970 #define TIMER21_RC2L_RC2_Pos (0UL)
9971 #define TIMER21_RC2L_RC2_Msk (0xffUL)
9972 /* ========================================================= T2CON ========================================================= */
9973 #define TIMER21_T2CON_CP_RL2_Pos (0UL)
9974 #define TIMER21_T2CON_CP_RL2_Msk (0x1UL)
9975 #define TIMER21_T2CON_C_T2_Pos (1UL)
9976 #define TIMER21_T2CON_C_T2_Msk (0x2UL)
9977 #define TIMER21_T2CON_TR2_Pos (2UL)
9978 #define TIMER21_T2CON_TR2_Msk (0x4UL)
9979 #define TIMER21_T2CON_EXEN2_Pos (3UL)
9980 #define TIMER21_T2CON_EXEN2_Msk (0x8UL)
9981 #define TIMER21_T2CON_EXF2_Pos (6UL)
9982 #define TIMER21_T2CON_EXF2_Msk (0x40UL)
9983 #define TIMER21_T2CON_TF2_Pos (7UL)
9984 #define TIMER21_T2CON_TF2_Msk (0x80UL)
9985 /* ======================================================== T2CON1 ========================================================= */
9986 #define TIMER21_T2CON1_EXF2EN_Pos (0UL)
9987 #define TIMER21_T2CON1_EXF2EN_Msk (0x1UL)
9988 #define TIMER21_T2CON1_TF2EN_Pos (1UL)
9989 #define TIMER21_T2CON1_TF2EN_Msk (0x2UL)
9990 /* ========================================================== T2H ========================================================== */
9991 #define TIMER21_T2H_T2H_Pos (0UL)
9992 #define TIMER21_T2H_T2H_Msk (0xffUL)
9993 /* ======================================================== T2ICLR ========================================================= */
9994 #define TIMER21_T2ICLR_EXF2CLR_Pos (6UL)
9995 #define TIMER21_T2ICLR_EXF2CLR_Msk (0x40UL)
9996 #define TIMER21_T2ICLR_TF2CLR_Pos (7UL)
9997 #define TIMER21_T2ICLR_TF2CLR_Msk (0x80UL)
9998 /* ========================================================== T2L ========================================================== */
9999 #define TIMER21_T2L_T2L_Pos (0UL)
10000 #define TIMER21_T2L_T2L_Msk (0xffUL)
10001 /* ========================================================= T2MOD ========================================================= */
10002 #define TIMER21_T2MOD_DCEN_Pos (0UL)
10003 #define TIMER21_T2MOD_DCEN_Msk (0x1UL)
10004 #define TIMER21_T2MOD_T2PRE_Pos (1UL)
10005 #define TIMER21_T2MOD_T2PRE_Msk (0xeUL)
10006 #define TIMER21_T2MOD_PREN_Pos (4UL)
10007 #define TIMER21_T2MOD_PREN_Msk (0x10UL)
10008 #define TIMER21_T2MOD_EDGESEL_Pos (5UL)
10009 #define TIMER21_T2MOD_EDGESEL_Msk (0x20UL)
10010 #define TIMER21_T2MOD_T2RHEN_Pos (6UL)
10011 #define TIMER21_T2MOD_T2RHEN_Msk (0x40UL)
10012 #define TIMER21_T2MOD_T2REGS_Pos (7UL)
10013 #define TIMER21_T2MOD_T2REGS_Msk (0x80UL)
10016 /* =========================================================================================================================== */
10017 /* ================ TIMER3 ================ */
10018 /* =========================================================================================================================== */
10019 
10020 /* ========================================================== CMP ========================================================== */
10021 #define TIMER3_CMP_HI_Pos (8UL)
10022 #define TIMER3_CMP_HI_Msk (0xff00UL)
10023 #define TIMER3_CMP_LO_Pos (0UL)
10024 #define TIMER3_CMP_LO_Msk (0xffUL)
10025 /* ========================================================== CNT ========================================================== */
10026 #define TIMER3_CNT_HI_Pos (8UL)
10027 #define TIMER3_CNT_HI_Msk (0xff00UL)
10028 #define TIMER3_CNT_LO_Pos (0UL)
10029 #define TIMER3_CNT_LO_Msk (0xffUL)
10030 /* ========================================================= CTRL ========================================================== */
10031 #define TIMER3_CTRL_T3H_OVF_IE_Pos (9UL)
10032 #define TIMER3_CTRL_T3H_OVF_IE_Msk (0x200UL)
10033 #define TIMER3_CTRL_T3L_OVF_IE_Pos (8UL)
10034 #define TIMER3_CTRL_T3L_OVF_IE_Msk (0x100UL)
10035 #define TIMER3_CTRL_T3L_OVF_STS_Pos (7UL)
10036 #define TIMER3_CTRL_T3L_OVF_STS_Msk (0x80UL)
10037 #define TIMER3_CTRL_TR3L_Pos (6UL)
10038 #define TIMER3_CTRL_TR3L_Msk (0x40UL)
10039 #define TIMER3_CTRL_T3H_OVF_STS_Pos (5UL)
10040 #define TIMER3_CTRL_T3H_OVF_STS_Msk (0x20UL)
10041 #define TIMER3_CTRL_TR3H_Pos (4UL)
10042 #define TIMER3_CTRL_TR3H_Msk (0x10UL)
10043 #define TIMER3_CTRL_CNT_RDY_Pos (3UL)
10044 #define TIMER3_CTRL_CNT_RDY_Msk (0x8UL)
10045 #define TIMER3_CTRL_T3_RD_REQ_CONF_Pos (2UL)
10046 #define TIMER3_CTRL_T3_RD_REQ_CONF_Msk (0x4UL)
10047 #define TIMER3_CTRL_T3_RD_REQ_Pos (1UL)
10048 #define TIMER3_CTRL_T3_RD_REQ_Msk (0x2UL)
10049 #define TIMER3_CTRL_T3_PD_N_Pos (0UL)
10050 #define TIMER3_CTRL_T3_PD_N_Msk (0x1UL)
10051 /* ======================================================== ISRCLR ========================================================= */
10052 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Pos (7UL)
10053 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Msk (0x80UL)
10054 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Pos (5UL)
10055 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Msk (0x20UL)
10056 /* ======================================================= MODE_CONF ======================================================= */
10057 #define TIMER3_MODE_CONF_T3_SUBM_Pos (6UL)
10058 #define TIMER3_MODE_CONF_T3_SUBM_Msk (0xc0UL)
10059 #define TIMER3_MODE_CONF_T3M_Pos (0UL)
10060 #define TIMER3_MODE_CONF_T3M_Msk (0x3UL)
10061 /* ===================================================== T3_TRIGG_CTRL ===================================================== */
10062 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Pos (6UL)
10063 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Msk (0x40UL)
10064 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Pos (4UL)
10065 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Msk (0x30UL)
10066 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Pos (0UL)
10067 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Msk (0x7UL)
10070 /* =========================================================================================================================== */
10071 /* ================ UART1 ================ */
10072 /* =========================================================================================================================== */
10073 
10074 /* ========================================================= SBUF ========================================================== */
10075 #define UART1_SBUF_VAL_Pos (0UL)
10076 #define UART1_SBUF_VAL_Msk (0xffUL)
10077 /* ========================================================= SCON ========================================================== */
10078 #define UART1_SCON_RI_Pos (0UL)
10079 #define UART1_SCON_RI_Msk (0x1UL)
10080 #define UART1_SCON_TI_Pos (1UL)
10081 #define UART1_SCON_TI_Msk (0x2UL)
10082 #define UART1_SCON_RB8_Pos (2UL)
10083 #define UART1_SCON_RB8_Msk (0x4UL)
10084 #define UART1_SCON_TB8_Pos (3UL)
10085 #define UART1_SCON_TB8_Msk (0x8UL)
10086 #define UART1_SCON_REN_Pos (4UL)
10087 #define UART1_SCON_REN_Msk (0x10UL)
10088 #define UART1_SCON_SM2_Pos (5UL)
10089 #define UART1_SCON_SM2_Msk (0x20UL)
10090 #define UART1_SCON_SM1_Pos (6UL)
10091 #define UART1_SCON_SM1_Msk (0x40UL)
10092 #define UART1_SCON_SM0_Pos (7UL)
10093 #define UART1_SCON_SM0_Msk (0x80UL)
10094 /* ======================================================== SCONCLR ======================================================== */
10095 #define UART1_SCONCLR_RICLR_Pos (0UL)
10096 #define UART1_SCONCLR_RICLR_Msk (0x1UL)
10097 #define UART1_SCONCLR_TICLR_Pos (1UL)
10098 #define UART1_SCONCLR_TICLR_Msk (0x2UL)
10101 /* =========================================================================================================================== */
10102 /* ================ UART2 ================ */
10103 /* =========================================================================================================================== */
10104 
10105 /* ========================================================= SBUF ========================================================== */
10106 #define UART2_SBUF_VAL_Pos (0UL)
10107 #define UART2_SBUF_VAL_Msk (0xffUL)
10108 /* ========================================================= SCON ========================================================== */
10109 #define UART2_SCON_RI_Pos (0UL)
10110 #define UART2_SCON_RI_Msk (0x1UL)
10111 #define UART2_SCON_TI_Pos (1UL)
10112 #define UART2_SCON_TI_Msk (0x2UL)
10113 #define UART2_SCON_RB8_Pos (2UL)
10114 #define UART2_SCON_RB8_Msk (0x4UL)
10115 #define UART2_SCON_TB8_Pos (3UL)
10116 #define UART2_SCON_TB8_Msk (0x8UL)
10117 #define UART2_SCON_REN_Pos (4UL)
10118 #define UART2_SCON_REN_Msk (0x10UL)
10119 #define UART2_SCON_SM2_Pos (5UL)
10120 #define UART2_SCON_SM2_Msk (0x20UL)
10121 #define UART2_SCON_SM1_Pos (6UL)
10122 #define UART2_SCON_SM1_Msk (0x40UL)
10123 #define UART2_SCON_SM0_Pos (7UL)
10124 #define UART2_SCON_SM0_Msk (0x80UL)
10125 /* ======================================================== SCONCLR ======================================================== */
10126 #define UART2_SCONCLR_RICLR_Pos (0UL)
10127 #define UART2_SCONCLR_RICLR_Msk (0x1UL)
10128 #define UART2_SCONCLR_TICLR_Pos (1UL)
10129 #define UART2_SCONCLR_TICLR_Msk (0x2UL) /* End of group PosMask_peripherals */
10132 
10133 #ifdef __cplusplus
10134 }
10135 #endif
10136 
10137 #endif /* TLE987X_H */
10138 
10139  /* End of group TLE987x */
10141  /* End of group Infineon */
IRQn_Type
Definition: tle987x.h:79
@ PendSV_IRQn
Definition: tle987x.h:91
@ EXINT0_MON_Int
Definition: tle987x.h:106
@ SSC2_Int
Definition: tle987x.h:103
@ BDRV_CP_Int
Definition: tle987x.h:108
@ CCU6_SR2_Int
Definition: tle987x.h:100
@ GPT2_Int
Definition: tle987x.h:95
@ MemoryManagement_IRQn
Definition: tle987x.h:84
@ DMA_Int
Definition: tle987x.h:109
@ SVCall_IRQn
Definition: tle987x.h:89
@ Reset_IRQn
Definition: tle987x.h:81
@ SSC1_Int
Definition: tle987x.h:102
@ CCU6_SR0_Int
Definition: tle987x.h:98
@ UsageFault_IRQn
Definition: tle987x.h:88
@ SysTick_IRQn
Definition: tle987x.h:92
@ UART2_Tmr21_EINT2_Int
Definition: tle987x.h:105
@ BusFault_IRQn
Definition: tle987x.h:86
@ DebugMonitor_IRQn
Definition: tle987x.h:90
@ UART1_LIN_Tmr2_Int
Definition: tle987x.h:104
@ HardFault_IRQn
Definition: tle987x.h:83
@ CCU6_SR1_Int
Definition: tle987x.h:99
@ EXINT1_Int
Definition: tle987x.h:107
@ NonMaskableInt_IRQn
Definition: tle987x.h:82
@ ADC2_Tmr3_Int
Definition: tle987x.h:96
@ CCU6_SR3_Int
Definition: tle987x.h:101
@ GPT1_Int
Definition: tle987x.h:94
@ ADC1_VREF5_Int
Definition: tle987x.h:97
#define DMA
Definition: tle987x.h:6064
#define SCUPM
Definition: tle987x.h:6072
#define ADC34
Definition: tle987x.h:6059
#define TIMER21
Definition: tle987x.h:6076
#define MF
Definition: tle987x.h:6067
#define PORT
Definition: tle987x.h:6070
#define TIMER3
Definition: tle987x.h:6077
#define GPT12E
Definition: tle987x.h:6065
#define SSC2
Definition: tle987x.h:6074
#define UART2
Definition: tle987x.h:6079
#define UART1
Definition: tle987x.h:6078
#define BDRV
Definition: tle987x.h:6060
#define ADC1
Definition: tle987x.h:6057
#define MON
Definition: tle987x.h:6068
#define CCU6
Definition: tle987x.h:6061
#define CSA
Definition: tle987x.h:6062
#define ADC2
Definition: tle987x.h:6058
#define SSC1
Definition: tle987x.h:6073
#define TIMER2
Definition: tle987x.h:6075
#define PMU
Definition: tle987x.h:6069
#define CPU
Definition: tle987x.h:6063
#define SCU
Definition: tle987x.h:6071
#define LIN
Definition: tle987x.h:6066
#define __OM
Definition: tle987x.h:135
#define __IM
Definition: tle987x.h:132
#define __IOM
Definition: tle987x.h:138
ADC1 Module (ADC1)
Definition: tle987x.h:167
__IOM uint32_t CH0_IE
Definition: tle987x.h:485
__IM uint32_t OF7
Definition: tle987x.h:343
__OM uint32_t CH7_ICLR
Definition: tle987x.h:511
__IOM uint32_t IN_MUX_SEL
Definition: tle987x.h:179
__IM uint32_t VF8
Definition: tle987x.h:311
__IM uint32_t OUT_CH_EIM
Definition: tle987x.h:308
__OM uint32_t CH6_ICLR
Definition: tle987x.h:510
__IM uint32_t CH1_STS
Definition: tle987x.h:467
__IOM uint32_t SOC
Definition: tle987x.h:177
__IOM uint32_t SQ5
Definition: tle987x.h:250
__IM uint32_t CHNR
Definition: tle987x.h:454
__IM uint32_t VF6
Definition: tle987x.h:356
__IM uint32_t OUT_CH2
Definition: tle987x.h:409
__IOM uint32_t WFR0
Definition: tle987x.h:439
__IOM uint32_t WFR6
Definition: tle987x.h:355
__IOM uint32_t ch2
Definition: tle987x.h:266
__IOM uint32_t CH3_IE
Definition: tle987x.h:488
__IOM uint32_t ch0
Definition: tle987x.h:264
__IOM uint32_t ANON
Definition: tle987x.h:193
__IOM uint32_t ch3
Definition: tle987x.h:267
__IM uint32_t VF4
Definition: tle987x.h:384
__IOM uint32_t WFR5
Definition: tle987x.h:369
__IOM uint32_t SQ6
Definition: tle987x.h:251
__IOM uint32_t SQ2
Definition: tle987x.h:237
__IM uint32_t OF0
Definition: tle987x.h:441
__IM uint32_t OF6
Definition: tle987x.h:357
__IM uint32_t OF8
Definition: tle987x.h:312
__IOM uint32_t DIVA
Definition: tle987x.h:189
__OM uint32_t EIM_ICLR
Definition: tle987x.h:512
__OM uint32_t ESM_ICLR
Definition: tle987x.h:513
__IOM uint32_t ch7
Definition: tle987x.h:271
__IOM uint32_t WFR2
Definition: tle987x.h:411
__IOM uint32_t SQ1
Definition: tle987x.h:236
__IM uint32_t VF2
Definition: tle987x.h:412
__IM uint32_t BUSY
Definition: tle987x.h:451
__IM uint32_t
Definition: tle987x.h:176
__IOM uint32_t EIM_IE
Definition: tle987x.h:493
__IOM uint32_t ch4
Definition: tle987x.h:268
__IM uint32_t CHx
Definition: tle987x.h:329
__OM uint32_t CH1_ICLR
Definition: tle987x.h:505
__IM uint32_t CH7_STS
Definition: tle987x.h:473
__IM uint32_t VF0
Definition: tle987x.h:440
__IOM uint32_t REP
Definition: tle987x.h:206
__IM uint32_t OUT_CH4
Definition: tle987x.h:381
__OM uint32_t CH3_ICLR
Definition: tle987x.h:507
__OM uint32_t CH4_ICLR
Definition: tle987x.h:508
__IM uint32_t OF5
Definition: tle987x.h:371
__IM uint32_t OUT_CH6
Definition: tle987x.h:353
__IM uint32_t EIM_STS
Definition: tle987x.h:474
__IM uint32_t EOC
Definition: tle987x.h:178
__IOM uint32_t ESM_0
Definition: tle987x.h:220
__IM uint32_t SQx
Definition: tle987x.h:327
__IM uint32_t ESM_ACTIVE
Definition: tle987x.h:326
__IM uint32_t CH0_STS
Definition: tle987x.h:466
__IM uint32_t CH2_STS
Definition: tle987x.h:468
__IM uint32_t OF3
Definition: tle987x.h:399
__IOM uint32_t ch6
Definition: tle987x.h:270
__IM uint32_t OUT_CH5
Definition: tle987x.h:367
__IM uint32_t ANON_ST
Definition: tle987x.h:456
__IOM uint32_t SQ7
Definition: tle987x.h:252
__IM uint32_t VF1
Definition: tle987x.h:426
__IM uint32_t ESM_STS
Definition: tle987x.h:475
__IM uint32_t VF5
Definition: tle987x.h:370
__IOM uint32_t WFR8
Definition: tle987x.h:310
__IM uint32_t CH5_STS
Definition: tle987x.h:471
__IM uint32_t CH4_STS
Definition: tle987x.h:470
__IOM uint32_t ESM_IE
Definition: tle987x.h:494
__IOM uint32_t ch5
Definition: tle987x.h:269
__IOM uint32_t CH4_IE
Definition: tle987x.h:489
__IM uint32_t OF4
Definition: tle987x.h:385
__IOM uint32_t reg
Definition: tle987x.h:171
__IM uint32_t OUT_CH7
Definition: tle987x.h:339
__IM uint32_t VF7
Definition: tle987x.h:342
__IOM uint32_t PD_N
Definition: tle987x.h:175
__IM uint32_t OUT_CH1
Definition: tle987x.h:423
__OM uint32_t CH2_ICLR
Definition: tle987x.h:506
__IM uint32_t SAMPLE
Definition: tle987x.h:452
__IOM uint32_t WFR4
Definition: tle987x.h:383
__IM uint32_t OUT_CH3
Definition: tle987x.h:395
__IOM uint32_t CH6_IE
Definition: tle987x.h:491
__IOM uint32_t SQ_RUN
Definition: tle987x.h:324
__IOM uint32_t SQ8
Definition: tle987x.h:253
__IOM uint32_t CHx
Definition: tle987x.h:204
__IOM uint32_t WFR3
Definition: tle987x.h:397
__IOM uint32_t TRIG_SEL
Definition: tle987x.h:208
__IOM uint32_t SQ3
Definition: tle987x.h:238
__IOM uint32_t ch1
Definition: tle987x.h:265
__IM uint32_t RESERVED1
Definition: tle987x.h:256
__IM uint32_t OF2
Definition: tle987x.h:413
__IM uint32_t CH6_STS
Definition: tle987x.h:472
__IOM uint32_t WFR1
Definition: tle987x.h:425
__IOM uint32_t CH1_IE
Definition: tle987x.h:486
__IOM uint32_t CH2_IE
Definition: tle987x.h:487
__IOM uint32_t SQ4
Definition: tle987x.h:239
__IM uint32_t OUT_CH0
Definition: tle987x.h:437
__OM uint32_t CH5_ICLR
Definition: tle987x.h:509
__IOM uint32_t CH7_IE
Definition: tle987x.h:492
__OM uint32_t CH0_ICLR
Definition: tle987x.h:504
__IM uint32_t EIM_ACTIVE
Definition: tle987x.h:325
__IM uint32_t CH3_STS
Definition: tle987x.h:469
__IOM uint32_t CH5_IE
Definition: tle987x.h:490
__IOM uint32_t WFR7
Definition: tle987x.h:341
__IM uint32_t VF3
Definition: tle987x.h:398
__IM uint32_t OF1
Definition: tle987x.h:427
ADC2 Module (ADC2)
Definition: tle987x.h:530
__IOM uint32_t HYST_UP_CH2
Definition: tle987x.h:1077
__IOM uint32_t HYST_UP_CH3
Definition: tle987x.h:1080
__IOM uint32_t OFFS_CH3
Definition: tle987x.h:733
__IM uint32_t CNT_LO_CH6
Definition: tle987x.h:1050
__IM uint32_t SQ_FB
Definition: tle987x.h:549
__IOM uint32_t OFFS_CH5
Definition: tle987x.h:746
__IOM uint32_t GAIN_CH2
Definition: tle987x.h:732
__IOM uint32_t FILT_OUT_SEL_9_6
Definition: tle987x.h:632
__IOM uint32_t Ch0
Definition: tle987x.h:1124
__IOM uint32_t HYST_UP_CH1
Definition: tle987x.h:1074
__IOM uint32_t CNT_UP_CH5
Definition: tle987x.h:1093
__IM uint32_t GAIN_CH8
Definition: tle987x.h:771
__IOM uint32_t CH6
Definition: tle987x.h:966
__IM uint32_t GAIN_CH9
Definition: tle987x.h:773
__IOM uint32_t CH1
Definition: tle987x.h:784
__IM uint32_t CNT_LO_CH9
Definition: tle987x.h:1059
__IM uint32_t HYST_LO_CH6
Definition: tle987x.h:1051
__IM uint32_t OFFS_CH9
Definition: tle987x.h:772
__IOM uint32_t SQ5
Definition: tle987x.h:659
__IOM uint32_t CH3
Definition: tle987x.h:786
__IM uint32_t CNT_LO_CH7
Definition: tle987x.h:1053
__IM uint32_t SQ_STOP
Definition: tle987x.h:551
__IM uint32_t OUT_CH2
Definition: tle987x.h:831
__IM uint32_t GAIN_CH7
Definition: tle987x.h:760
__IOM uint32_t CNT_LO_CH1
Definition: tle987x.h:1019
__IM uint32_t CNT_UP_CH7
Definition: tle987x.h:1107
__IOM uint32_t SEL
Definition: tle987x.h:572
__IM uint32_t CH8
Definition: tle987x.h:800
__IM uint32_t HYST_LO_CH9
Definition: tle987x.h:1060
__IOM uint32_t CH9
Definition: tle987x.h:969
__IOM uint32_t SQ6
Definition: tle987x.h:661
__IM uint32_t HYST_UP_CH7
Definition: tle987x.h:1108
__IOM uint32_t GAIN_CH1
Definition: tle987x.h:721
__IM uint32_t STS
Definition: tle987x.h:592
__IOM uint32_t SQ2
Definition: tle987x.h:644
__IOM uint32_t CNT_UP_CH4
Definition: tle987x.h:1090
__IOM uint32_t FILT_OUT_SEL_5_0
Definition: tle987x.h:630
__IM uint32_t CH7
Definition: tle987x.h:799
__IOM uint32_t Ch1_EN
Definition: tle987x.h:912
__IM uint32_t CNT_LO_CH8
Definition: tle987x.h:1056
__IOM uint32_t CNT_UP_CH1
Definition: tle987x.h:1073
__IOM uint32_t HYST_LO_CH2
Definition: tle987x.h:1023
__IM uint32_t HYST_UP_CH6
Definition: tle987x.h:1105
__IOM uint32_t SQ1
Definition: tle987x.h:642
__IM uint32_t
Definition: tle987x.h:538
__IOM uint32_t GAIN_CH5
Definition: tle987x.h:747
__IM uint32_t OUT_CH9
Definition: tle987x.h:901
__IOM uint32_t Ch4_EN
Definition: tle987x.h:915
__IOM uint32_t CNT_UP_CH3
Definition: tle987x.h:1079
__IOM uint32_t OFFS_CH2
Definition: tle987x.h:731
__IOM uint32_t GAIN_CH4
Definition: tle987x.h:745
__IM uint32_t HYST_UP_CH9
Definition: tle987x.h:1114
__IOM uint32_t SEL_TS_COUNT
Definition: tle987x.h:620
__IM uint32_t CHx
Definition: tle987x.h:556
__IM uint32_t SQ5_int
Definition: tle987x.h:693
__IOM uint32_t REP
Definition: tle987x.h:569
__IM uint32_t OUT_CH4
Definition: tle987x.h:851
__IOM uint32_t CH8
Definition: tle987x.h:968
__IOM uint32_t CH5
Definition: tle987x.h:788
__IM uint32_t OFFS_CH6
Definition: tle987x.h:757
__IOM uint32_t HYST_LO_CH5
Definition: tle987x.h:1040
__IOM uint32_t OFFS_CH1
Definition: tle987x.h:720
__IM uint32_t CH6
Definition: tle987x.h:798
__IM uint32_t READY
Definition: tle987x.h:1141
__IM uint32_t OUT_CH6
Definition: tle987x.h:871
__IOM uint32_t HYST_LO_CH1
Definition: tle987x.h:1020
__IM uint32_t SQ1_int
Definition: tle987x.h:689
__IOM uint32_t Ch4
Definition: tle987x.h:1128
__IOM uint32_t CNT_LO_CH2
Definition: tle987x.h:1022
__IOM uint32_t ESM_0
Definition: tle987x.h:584
__IM uint32_t SQx
Definition: tle987x.h:554
__IOM uint32_t CNT_UP_CH0
Definition: tle987x.h:1070
__IM uint32_t SQ6_int
Definition: tle987x.h:694
__IOM uint32_t Ch3
Definition: tle987x.h:1127
__IOM uint32_t Ch1
Definition: tle987x.h:1125
__IOM uint32_t Ch2_EN
Definition: tle987x.h:913
__IM uint32_t SQ3_int
Definition: tle987x.h:691
__IOM uint32_t SQ9
Definition: tle987x.h:676
__IOM uint32_t GAIN_CH0
Definition: tle987x.h:719
__IM uint32_t ESM_ACTIVE
Definition: tle987x.h:553
__IOM uint32_t TSENSE_SD_SEL
Definition: tle987x.h:615
__IOM uint32_t Ch2
Definition: tle987x.h:1126
__IOM uint32_t SAMPLE_TIME_int
Definition: tle987x.h:618
__IOM uint32_t CNT_LO_CH4
Definition: tle987x.h:1036
__IOM uint32_t ESM_1
Definition: tle987x.h:586
__IM uint32_t CNT_UP_CH9
Definition: tle987x.h:1113
__IM uint32_t CH9
Definition: tle987x.h:801
__IOM uint32_t Ch5
Definition: tle987x.h:1129
__IM uint32_t OUT_CH5
Definition: tle987x.h:861
__IOM uint32_t Ch0_EN
Definition: tle987x.h:911
__IOM uint32_t SQ7
Definition: tle987x.h:663
__IOM uint32_t CALIB_EN
Definition: tle987x.h:603
__IOM uint32_t HYST_LO_CH4
Definition: tle987x.h:1037
__IOM uint32_t SQ10
Definition: tle987x.h:678
__IM uint32_t MCM_RDY
Definition: tle987x.h:617
__IM uint32_t RESERVED
Definition: tle987x.h:595
__IM uint32_t SQ4_int
Definition: tle987x.h:692
__IOM uint32_t Ch5_EN
Definition: tle987x.h:916
__IOM uint32_t CH2
Definition: tle987x.h:785
__IM uint32_t SQ9_int
Definition: tle987x.h:707
__IM uint32_t GAIN_CH6
Definition: tle987x.h:758
__IM uint32_t SQ10_int
Definition: tle987x.h:708
__IOM uint32_t CH4
Definition: tle987x.h:787
__IM uint32_t OUT_CH8
Definition: tle987x.h:891
__IOM uint32_t reg
Definition: tle987x.h:534
__IOM uint32_t CNT_UP_CH2
Definition: tle987x.h:1076
__IM uint32_t OUT_CH7
Definition: tle987x.h:881
__IOM uint32_t EN
Definition: tle987x.h:570
__IM uint32_t OFFS_CH7
Definition: tle987x.h:759
__IOM uint32_t CNT_LO_CH5
Definition: tle987x.h:1039
__IOM uint32_t TS_SD_SEL_CONF
Definition: tle987x.h:614
__IOM uint32_t CNT_LO_CH0
Definition: tle987x.h:1016
__IM uint32_t CNT_UP_CH8
Definition: tle987x.h:1110
__IM uint32_t SQ8_int
Definition: tle987x.h:696
__IOM uint32_t CH0
Definition: tle987x.h:783
__IOM uint32_t HYST_LO_CH0
Definition: tle987x.h:1017
__IOM uint32_t GAIN_CH3
Definition: tle987x.h:734
__IM uint32_t SQ7_int
Definition: tle987x.h:695
__IM uint32_t OUT_CH1
Definition: tle987x.h:821
__IM uint32_t OFFS_CH8
Definition: tle987x.h:770
__IM uint32_t OUT_CH3
Definition: tle987x.h:841
__IM uint32_t HYST_LO_CH8
Definition: tle987x.h:1057
__IM uint32_t HYST_UP_CH8
Definition: tle987x.h:1111
__IOM uint32_t HYST_UP_CH4
Definition: tle987x.h:1091
__IOM uint32_t SQ8
Definition: tle987x.h:665
__IOM uint32_t CHx
Definition: tle987x.h:567
__IM uint32_t HYST_LO_CH7
Definition: tle987x.h:1054
__IOM uint32_t SQ3
Definition: tle987x.h:646
__IOM uint32_t MCM_PD_N
Definition: tle987x.h:613
__IOM uint32_t HYST_LO_CH3
Definition: tle987x.h:1026
__IOM uint32_t CNT_LO_CH3
Definition: tle987x.h:1025
__IM uint32_t CNT_UP_CH6
Definition: tle987x.h:1104
__IOM uint32_t OFFS_CH0
Definition: tle987x.h:718
__IOM uint32_t SQ4
Definition: tle987x.h:648
__IOM uint32_t VS_RANGE
Definition: tle987x.h:539
__IOM uint32_t OFFS_CH4
Definition: tle987x.h:744
__IM uint32_t SQ2_int
Definition: tle987x.h:690
__IM uint32_t OUT_CH0
Definition: tle987x.h:811
__IOM uint32_t HYST_UP_CH5
Definition: tle987x.h:1094
__IM uint32_t EIM_ACTIVE
Definition: tle987x.h:552
__IOM uint32_t Ch3_EN
Definition: tle987x.h:914
__IOM uint32_t HYST_UP_CH0
Definition: tle987x.h:1071
ADC34 (ADC34)
Definition: tle987x.h:1158
__IOM uint32_t ADC4_SOC
Definition: tle987x.h:1178
__IOM uint32_t ADC4_OSR
Definition: tle987x.h:1185
__IM uint32_t ADC4_EoC_STS
Definition: tle987x.h:1181
__IM uint32_t ADC4_RESU
Definition: tle987x.h:1196
__IOM uint32_t ADC34_DITHVAL
Definition: tle987x.h:1184
__IOM uint32_t ADC3_SOC
Definition: tle987x.h:1168
__IM uint32_t ADC34_DREQ_SEL
Definition: tle987x.h:1172
__IM uint32_t
Definition: tle987x.h:1170
__IOM uint32_t ADC34_DITHEN
Definition: tle987x.h:1183
__IOM uint32_t ADC3_EN
Definition: tle987x.h:1166
__IM uint32_t ADC3_EoC_STS
Definition: tle987x.h:1171
__IOM uint32_t ADC34_REF_SEL
Definition: tle987x.h:1174
__IOM uint32_t ADC3_OSR
Definition: tle987x.h:1175
__IOM uint32_t ADC4_EN
Definition: tle987x.h:1176
__IOM uint32_t reg
Definition: tle987x.h:1162
__IOM uint32_t ADC4_OFS_MEAS_EN
Definition: tle987x.h:1177
__IOM uint32_t ADC3_OFS_MEAS_EN
Definition: tle987x.h:1167
__IOM uint32_t ADC34_EoC_CNT
Definition: tle987x.h:1182
__IM uint32_t ADC3_RESU
Definition: tle987x.h:1195
Bridge Driver (BDRV)
Definition: tle987x.h:1213
__IM uint32_t HS3_DS_STS
Definition: tle987x.h:1277
__IOM uint32_t LS1_PWM
Definition: tle987x.h:1222
__IOM uint32_t DRV_ON_I_3
Definition: tle987x.h:1338
__IOM uint32_t HS3_PWM
Definition: tle987x.h:1274
__IOM uint32_t DITH_LOWER
Definition: tle987x.h:1413
__IM uint32_t HS1_DS_STS
Definition: tle987x.h:1242
__IOM uint32_t HS2_DCS_EN
Definition: tle987x.h:1250
__IOM uint32_t LS2_PWM
Definition: tle987x.h:1230
__IOM uint32_t HS3DRV_FDISCHG_DIS
Definition: tle987x.h:1369
__IOM uint32_t ICHARGEDIV2_N
Definition: tle987x.h:1297
__IOM uint32_t LS2_OC_DIS
Definition: tle987x.h:1237
__IM uint32_t HS3_OC_STS
Definition: tle987x.h:1279
__IOM uint32_t LS3DRV_FDISCHG_DIS
Definition: tle987x.h:1361
__IOM uint32_t HS1_DCS_EN
Definition: tle987x.h:1241
__IOM uint32_t LS3_ON
Definition: tle987x.h:1267
__IM uint32_t LS1_OC_STS
Definition: tle987x.h:1227
__IOM uint32_t DITH_UPPER
Definition: tle987x.h:1415
__IM uint32_t VSD_LOTH_STS
Definition: tle987x.h:1398
__IOM uint32_t LS1_EN
Definition: tle987x.h:1221
__IOM uint32_t CPLOPWRM_EN
Definition: tle987x.h:1401
__IM uint32_t LS2_DS_STS
Definition: tle987x.h:1233
__IM uint32_t HS2_SUPERR_STS
Definition: tle987x.h:1253
__IOM uint32_t LS3DRV_OCSDN_DIS
Definition: tle987x.h:1364
__IOM uint32_t DRV_OFF_I_2
Definition: tle987x.h:1323
__IOM uint32_t HS3_OC_DIS
Definition: tle987x.h:1280
__IM uint32_t LS2_SUPERR_STS
Definition: tle987x.h:1235
__IOM uint32_t ICHARGE_TRIM
Definition: tle987x.h:1295
__IOM uint32_t HS3_ON
Definition: tle987x.h:1275
__IOM uint32_t HSDRV_DS_TFILT_SEL
Definition: tle987x.h:1365
__IOM uint32_t DRV_ON_t_3
Definition: tle987x.h:1337
__IOM uint32_t LS1DRV_OCSDN_DIS
Definition: tle987x.h:1362
__IM uint32_t HS3_SUPERR_STS
Definition: tle987x.h:1278
__IOM uint32_t LS2DRV_OCSDN_DIS
Definition: tle987x.h:1363
__IM uint32_t HS1_SUPERR_STS
Definition: tle987x.h:1244
__IM uint32_t LS1_DS_STS
Definition: tle987x.h:1225
__IOM uint32_t LS2_DCS_EN
Definition: tle987x.h:1232
__IOM uint32_t DRV_OFF_t_4
Definition: tle987x.h:1318
__IOM uint32_t VCP9V_SET
Definition: tle987x.h:1402
__IOM uint32_t HS3_EN
Definition: tle987x.h:1273
__IOM uint32_t DRV_ON_I_1
Definition: tle987x.h:1342
__IM uint32_t DLY_DIAG_TIM
Definition: tle987x.h:1281
__IOM uint32_t DRVx_VSDUP_DIS
Definition: tle987x.h:1399
__IOM uint32_t HS2DRV_FDISCHG_DIS
Definition: tle987x.h:1368
__IOM uint32_t HS1_PWM
Definition: tle987x.h:1239
__IOM uint32_t DRV_ON_I_4
Definition: tle987x.h:1336
__IOM uint32_t LS2DRV_FDISCHG_DIS
Definition: tle987x.h:1360
__IOM uint32_t LS3_PWM
Definition: tle987x.h:1266
__IOM uint32_t LS2_ON
Definition: tle987x.h:1231
__IOM uint32_t HS1_EN
Definition: tle987x.h:1238
__IOM uint32_t HS3DRV_OCSDN_DIS
Definition: tle987x.h:1372
__IOM uint32_t F_CP
Definition: tle987x.h:1416
__IOM uint32_t DRV_CCP_TIMSEL
Definition: tle987x.h:1306
__IM uint32_t HS1_OC_STS
Definition: tle987x.h:1245
__IM uint32_t
Definition: tle987x.h:1296
__IOM uint32_t DRV_OFF_t_2
Definition: tle987x.h:1322
__OM uint32_t DLY_DIAG_SCLR
Definition: tle987x.h:1282
__IOM uint32_t HS1_ON
Definition: tle987x.h:1240
__IOM uint32_t OFF_SEQ_EN
Definition: tle987x.h:1302
__IOM uint32_t LS_HS_BT_TFILT_SEL
Definition: tle987x.h:1352
__IOM uint32_t LS3_OC_DIS
Definition: tle987x.h:1272
__IOM uint32_t HS3_DCS_EN
Definition: tle987x.h:1276
__IOM uint32_t DRV_OFF_I_1
Definition: tle987x.h:1325
__IOM uint32_t DRV_ON_t_1
Definition: tle987x.h:1341
__IOM uint32_t DLY_DIAG_DIRSEL
Definition: tle987x.h:1285
__IOM uint32_t DRV_CCP_DIS
Definition: tle987x.h:1307
__IOM uint32_t HS2_PWM
Definition: tle987x.h:1248
__IOM uint32_t HS2_EN
Definition: tle987x.h:1247
__IOM uint32_t HS2_ON
Definition: tle987x.h:1249
__IOM uint32_t CPLOW_TFILT_SEL
Definition: tle987x.h:1373
__IM uint32_t VCP_LOTH1_STS
Definition: tle987x.h:1394
__IM uint32_t LS3_SUPERR_STS
Definition: tle987x.h:1270
__IOM uint32_t IDISCHARGE_TRIM
Definition: tle987x.h:1299
__IM uint32_t VCP_UPTH_STS
Definition: tle987x.h:1396
__IOM uint32_t LS3_EN
Definition: tle987x.h:1265
__IOM uint32_t HS1_OC_DIS
Definition: tle987x.h:1246
__IOM uint32_t CP_RDY_EN
Definition: tle987x.h:1386
__IOM uint32_t LS1_DCS_EN
Definition: tle987x.h:1224
__IOM uint32_t CPCLK_EN
Definition: tle987x.h:1417
__IOM uint32_t DRV_ON_t_2
Definition: tle987x.h:1339
__IM uint32_t DLY_DIAG_STS
Definition: tle987x.h:1283
__IOM uint32_t DRV_OFF_t_3
Definition: tle987x.h:1320
__IOM uint32_t DRV_CCPTIMMUL
Definition: tle987x.h:1355
__IOM uint32_t DRV_OFF_t_1
Definition: tle987x.h:1324
__IM uint32_t RESERVED
Definition: tle987x.h:1310
__IOM uint32_t LS1_OC_DIS
Definition: tle987x.h:1228
__IOM uint32_t LS1_ON
Definition: tle987x.h:1223
__IOM uint32_t DLY_DIAG_CHSEL
Definition: tle987x.h:1284
__IM uint32_t LS1_SUPERR_STS
Definition: tle987x.h:1226
__IOM uint32_t DRV_ON_t_4
Definition: tle987x.h:1335
__IM uint32_t HS2_DS_STS
Definition: tle987x.h:1251
__IOM uint32_t reg
Definition: tle987x.h:1217
__IOM uint32_t DRV_OFF_I_3
Definition: tle987x.h:1321
__IM uint32_t VSD_UPTH_STS
Definition: tle987x.h:1400
__IOM uint32_t HS1DRV_FDISCHG_DIS
Definition: tle987x.h:1367
__IM uint32_t VCP_LOTH2_STS
Definition: tle987x.h:1388
__IOM uint32_t VTHVCP9V_TRIM
Definition: tle987x.h:1403
__IOM uint32_t CP_EN
Definition: tle987x.h:1384
__IOM uint32_t DRVx_VSDLO_DIS
Definition: tle987x.h:1397
__IM uint32_t LS3_DS_STS
Definition: tle987x.h:1269
__IOM uint32_t DRVx_VCPUP_DIS
Definition: tle987x.h:1395
__IOM uint32_t LS3_DCS_EN
Definition: tle987x.h:1268
__IOM uint32_t LS2_EN
Definition: tle987x.h:1229
__IOM uint32_t LS1DRV_FDISCHG_DIS
Definition: tle987x.h:1359
__IOM uint32_t HS2DRV_OCSDN_DIS
Definition: tle987x.h:1371
__IOM uint32_t HS2_OC_DIS
Definition: tle987x.h:1255
__IM uint32_t RESERVED1
Definition: tle987x.h:1376
__IOM uint32_t IDISCHARGEDIV2_N
Definition: tle987x.h:1301
__IOM uint32_t DSMONVTH
Definition: tle987x.h:1303
__IOM uint32_t VCP_LOWTH2
Definition: tle987x.h:1390
__IOM uint32_t DRV_OFF_I_4
Definition: tle987x.h:1319
__IOM uint32_t HS1DRV_OCSDN_DIS
Definition: tle987x.h:1370
__IM uint32_t HS2_OC_STS
Definition: tle987x.h:1254
__IOM uint32_t ON_SEQ_EN
Definition: tle987x.h:1298
__IOM uint32_t DRVx_VCPLO_DIS
Definition: tle987x.h:1393
__IOM uint32_t DRV_ON_I_2
Definition: tle987x.h:1340
__IM uint32_t LS3_OC_STS
Definition: tle987x.h:1271
__IOM uint32_t LSDRV_DS_TFILT_SEL
Definition: tle987x.h:1358
__IM uint32_t LS2_OC_STS
Definition: tle987x.h:1236
Capture Compare Unit 6 (CCU6)
Definition: tle987x.h:1434
__IOM uint16_t T13MODEN
Definition: tle987x.h:1827
__IOM uint16_t INPCC62
Definition: tle987x.h:1736
__IOM uint16_t INPCHE
Definition: tle987x.h:1737
__IM uint16_t CC63ST
Definition: tle987x.h:1959
__IOM uint16_t ECT13O
Definition: tle987x.h:1829
__IOM uint16_t DTE2
Definition: tle987x.h:1619
__OM uint16_t MCC63R
Definition: tle987x.h:1538
__IOM uint16_t STRMCM
Definition: tle987x.h:1480
__OM uint16_t RT12PM
Definition: tle987x.h:1502
__IM uint16_t CHE
Definition: tle987x.h:1884
__OM uint16_t RCHE
Definition: tle987x.h:1507
__OM uint16_t MCC62S
Definition: tle987x.h:1525
__IOM uint16_t DBYP
Definition: tle987x.h:1691
__IOM uint16_t ENCC62R
Definition: tle987x.h:1710
__IM uint16_t T13R
Definition: tle987x.h:1642
__IOM uint16_t INPCC60
Definition: tle987x.h:1734
__IOM uint16_t ENT13PM
Definition: tle987x.h:1717
__IOM uint16_t ISCC61
Definition: tle987x.h:1899
__OM uint16_t RTRPF
Definition: tle987x.h:1505
__OM uint16_t T12RS
Definition: tle987x.h:1454
__IM uint16_t T12OM
Definition: tle987x.h:1878
__IM uint16_t IDLE
Definition: tle987x.h:1886
__IM uint16_t RESERVED26
Definition: tle987x.h:1890
__IM uint16_t DTR2
Definition: tle987x.h:1623
__IOM uint16_t T12PV
Definition: tle987x.h:1594
__OM uint16_t T13STD
Definition: tle987x.h:1467
__IM uint16_t RESERVED19
Definition: tle987x.h:1769
__IOM uint16_t ISPOS2
Definition: tle987x.h:1904
__IOM uint16_t T13TEC
Definition: tle987x.h:1809
__IM uint16_t RESERVED12
Definition: tle987x.h:1646
__IOM uint16_t T13RSEL
Definition: tle987x.h:1813
__OM uint16_t MCC60S
Definition: tle987x.h:1521
__IOM uint16_t T12MODEN
Definition: tle987x.h:1824
__IOM uint16_t INPT13
Definition: tle987x.h:1740
__OM uint16_t RCC62R
Definition: tle987x.h:1499
__IM uint16_t RESERVED13
Definition: tle987x.h:1657
__IM uint16_t CCV
Definition: tle987x.h:1442
__OM uint16_t SCHE
Definition: tle987x.h:1763
__IOM uint16_t ENIDLE
Definition: tle987x.h:1722
__IOM uint16_t ISPOS1
Definition: tle987x.h:1903
__IOM uint16_t PSL
Definition: tle987x.h:1777
__IOM uint16_t T12EXT
Definition: tle987x.h:1919
__IOM uint16_t T13CLK
Definition: tle987x.h:1640
__OM uint16_t ST12PM
Definition: tle987x.h:1758
__IOM uint16_t CC61PS
Definition: tle987x.h:1963
__OM uint16_t ST12OM
Definition: tle987x.h:1757
__OM uint16_t T12RES
Definition: tle987x.h:1455
__IM uint16_t RESERVED22
Definition: tle987x.h:1816
__OM uint16_t T12RR
Definition: tle987x.h:1453
__IOM uint16_t T12PRE
Definition: tle987x.h:1635
__IM uint16_t ICC60R
Definition: tle987x.h:1872
__IOM uint16_t HSYNC
Definition: tle987x.h:1690
__IOM uint16_t T13IM
Definition: tle987x.h:1968
__OM uint16_t SSTR
Definition: tle987x.h:1766
__OM uint16_t SCC61F
Definition: tle987x.h:1754
__IM uint16_t RESERVED8
Definition: tle987x.h:1586
__IM uint16_t STE13
Definition: tle987x.h:1643
__IOM uint16_t CTM
Definition: tle987x.h:1639
__IM uint16_t T12PM
Definition: tle987x.h:1879
__OM uint16_t MCC60R
Definition: tle987x.h:1531
__OM uint16_t SWHE
Definition: tle987x.h:1764
__IOM uint16_t DTE1
Definition: tle987x.h:1618
__OM uint16_t T13STR
Definition: tle987x.h:1466
__OM uint16_t MCC62R
Definition: tle987x.h:1535
__IOM uint16_t INPERR
Definition: tle987x.h:1738
__IM uint16_t RESERVED4
Definition: tle987x.h:1542
__OM uint16_t SCC62R
Definition: tle987x.h:1755
__OM uint16_t RCC60F
Definition: tle987x.h:1496
__IM uint16_t ICC60F
Definition: tle987x.h:1873
__IOM uint16_t DTM
Definition: tle987x.h:1616
__IM uint16_t STE12
Definition: tle987x.h:1637
__IOM uint16_t COUT60PS
Definition: tle987x.h:1962
__IOM uint16_t STE12D
Definition: tle987x.h:1795
__IOM uint16_t EXPHS
Definition: tle987x.h:1481
__IM uint16_t
Definition: tle987x.h:1457
__OM uint16_t RT12OM
Definition: tle987x.h:1501
__IOM uint16_t ISTRP
Definition: tle987x.h:1901
__OM uint16_t T13CNT
Definition: tle987x.h:1465
__IOM uint16_t ENCC60F
Definition: tle987x.h:1704
__IM uint16_t CCPOS2
Definition: tle987x.h:1958
__OM uint16_t RCC62F
Definition: tle987x.h:1500
__IOM uint16_t COUT63PS
Definition: tle987x.h:1967
__IOM uint16_t T12SSC
Definition: tle987x.h:1807
__OM uint16_t RCC60R
Definition: tle987x.h:1495
__IOM uint16_t SWSEL
Definition: tle987x.h:1790
__IM uint16_t TRPF
Definition: tle987x.h:1882
__IM uint16_t RESERVED10
Definition: tle987x.h:1608
__OM uint16_t SIDLE
Definition: tle987x.h:1765
__OM uint16_t STRPF
Definition: tle987x.h:1761
__OM uint16_t RWHE
Definition: tle987x.h:1508
__IOM uint16_t ENT12PM
Definition: tle987x.h:1715
__OM uint16_t MCC63S
Definition: tle987x.h:1528
__IOM uint16_t ENCC61F
Definition: tle987x.h:1708
__IM uint16_t RESERVED20
Definition: tle987x.h:1782
__IM uint16_t ICC62F
Definition: tle987x.h:1877
__IM uint16_t R
Definition: tle987x.h:1858
__OM uint16_t MCC61S
Definition: tle987x.h:1523
__IM uint16_t T12R
Definition: tle987x.h:1636
__IM uint16_t CCPOS0
Definition: tle987x.h:1956
__OM uint16_t ST13PM
Definition: tle987x.h:1760
__IOM uint16_t TRPM1
Definition: tle987x.h:1841
__OM uint16_t SWHC
Definition: tle987x.h:1762
__IM uint16_t RESERVED28
Definition: tle987x.h:1923
__IM uint16_t RESERVED14
Definition: tle987x.h:1668
__IOM uint16_t reg
Definition: tle987x.h:1438
__IOM uint16_t MSEL60
Definition: tle987x.h:1687
__IOM uint16_t COUT62PS
Definition: tle987x.h:1966
__IM uint16_t RESERVED25
Definition: tle987x.h:1864
__IOM uint16_t ISCNT13
Definition: tle987x.h:1918
__IOM uint16_t ENWHE
Definition: tle987x.h:1721
__IM uint16_t CCPOS1
Definition: tle987x.h:1957
__IM uint16_t RESERVED30
Definition: tle987x.h:1945
__OM uint16_t T13RS
Definition: tle987x.h:1462
__OM uint16_t RSTR
Definition: tle987x.h:1510
__IM uint16_t CDIR
Definition: tle987x.h:1638
__IOM uint16_t IST13HR
Definition: tle987x.h:1916
__OM uint16_t SCC61R
Definition: tle987x.h:1753
__IM uint16_t CC62ST
Definition: tle987x.h:1955
__OM uint16_t T12STR
Definition: tle987x.h:1459
__IM uint16_t RESERVED6
Definition: tle987x.h:1564
__IM uint16_t DTR1
Definition: tle987x.h:1622
__OM uint16_t T12CNT
Definition: tle987x.h:1458
__OM uint16_t SCC60F
Definition: tle987x.h:1752
__IOM uint16_t MCMPS
Definition: tle987x.h:1478
__IOM uint16_t T12CV
Definition: tle987x.h:1931
__IOM uint16_t STE13U
Definition: tle987x.h:1796
__IOM uint16_t ENCC60R
Definition: tle987x.h:1702
__OM uint16_t RCC61F
Definition: tle987x.h:1498
__IOM uint16_t ENCC61R
Definition: tle987x.h:1706
__IOM uint16_t CC60PS
Definition: tle987x.h:1961
__IM uint16_t DTR0
Definition: tle987x.h:1621
__IOM uint16_t T13EXT
Definition: tle987x.h:1920
__IOM uint16_t IST12HR
Definition: tle987x.h:1905
__IOM uint16_t T13SSC
Definition: tle987x.h:1808
__IOM uint16_t INPCC61
Definition: tle987x.h:1735
__OM uint16_t RCC61R
Definition: tle987x.h:1497
__IM uint16_t CC60ST
Definition: tle987x.h:1953
__IOM uint16_t MCMEN
Definition: tle987x.h:1826
__IOM uint16_t ENTRPF
Definition: tle987x.h:1718
__IM uint16_t RESERVED11
Definition: tle987x.h:1626
__IOM uint16_t TRPPEN
Definition: tle987x.h:1846
__IOM uint16_t CCS
Definition: tle987x.h:1550
__IOM uint16_t ENT13CM
Definition: tle987x.h:1716
__IM uint16_t MCMP
Definition: tle987x.h:1857
__IOM uint16_t T12CLK
Definition: tle987x.h:1634
__IM uint16_t RESERVED29
Definition: tle987x.h:1934
__IOM uint16_t TRPEN13
Definition: tle987x.h:1845
__IOM uint16_t CURHS
Definition: tle987x.h:1482
__OM uint16_t ST13CM
Definition: tle987x.h:1759
__IM uint16_t CC61ST
Definition: tle987x.h:1954
__IOM uint16_t T13TED
Definition: tle987x.h:1810
__IOM uint16_t CC62PS
Definition: tle987x.h:1965
__IOM uint16_t TRPEN
Definition: tle987x.h:1844
__OM uint16_t SCC62F
Definition: tle987x.h:1756
__IOM uint16_t T13PRE
Definition: tle987x.h:1641
__IOM uint16_t ISCNT12
Definition: tle987x.h:1917
__IOM uint16_t COUT61PS
Definition: tle987x.h:1964
__IM uint16_t STR
Definition: tle987x.h:1887
__IM uint16_t RESERVED23
Definition: tle987x.h:1832
__IM uint16_t RESERVED18
Definition: tle987x.h:1743
__IM uint16_t T13CM
Definition: tle987x.h:1880
__IOM uint16_t TRPM0
Definition: tle987x.h:1840
__IM uint16_t T13PM
Definition: tle987x.h:1881
__IM uint16_t CURH
Definition: tle987x.h:1861
__IM uint16_t RESERVED5
Definition: tle987x.h:1553
__IOM uint16_t DTE0
Definition: tle987x.h:1617
__IM uint16_t WHE
Definition: tle987x.h:1885
__IM uint16_t RESERVED17
Definition: tle987x.h:1726
__IOM uint16_t INPT12
Definition: tle987x.h:1739
__IOM uint16_t T13PV
Definition: tle987x.h:1605
__OM uint16_t T12STD
Definition: tle987x.h:1460
__OM uint16_t DTRES
Definition: tle987x.h:1456
__OM uint16_t MCC61R
Definition: tle987x.h:1533
__OM uint16_t T13RES
Definition: tle987x.h:1463
__OM uint16_t RIDLE
Definition: tle987x.h:1509
__IM uint16_t RESERVED9
Definition: tle987x.h:1597
__IOM uint16_t T13CV
Definition: tle987x.h:1942
__IOM uint16_t ENCC62F
Definition: tle987x.h:1712
__IOM uint16_t ENCHE
Definition: tle987x.h:1720
__IM uint16_t RESERVED1
Definition: tle987x.h:1470
__IOM uint16_t ISCC60
Definition: tle987x.h:1898
__IOM uint16_t TRPM2
Definition: tle987x.h:1842
__IOM uint16_t T12RSEL
Definition: tle987x.h:1812
__OM uint16_t SCC60R
Definition: tle987x.h:1751
__OM uint16_t RT13CM
Definition: tle987x.h:1503
__IOM uint16_t ENT12OM
Definition: tle987x.h:1714
__IOM uint16_t PSL63
Definition: tle987x.h:1779
__IM uint16_t RESERVED7
Definition: tle987x.h:1575
__IM uint16_t RESERVED15
Definition: tle987x.h:1679
__IM uint16_t RESERVED3
Definition: tle987x.h:1513
__IM uint16_t RESERVED21
Definition: tle987x.h:1799
__IOM uint16_t STE12U
Definition: tle987x.h:1794
__IM uint16_t EXPH
Definition: tle987x.h:1860
__IM uint16_t RESERVED
Definition: tle987x.h:1445
__IOM uint16_t STRHP
Definition: tle987x.h:1484
__IM uint16_t ICC62R
Definition: tle987x.h:1876
__IOM uint16_t ISPOS0
Definition: tle987x.h:1902
__IOM uint16_t ISCC62
Definition: tle987x.h:1900
__IM uint16_t ICC61R
Definition: tle987x.h:1874
__IM uint16_t RESERVED2
Definition: tle987x.h:1487
__IOM uint16_t SWSYN
Definition: tle987x.h:1792
__OM uint16_t RT13PM
Definition: tle987x.h:1504
__IM uint16_t RESERVED24
Definition: tle987x.h:1849
__IM uint16_t TRPS
Definition: tle987x.h:1883
__IM uint16_t RESERVED16
Definition: tle987x.h:1694
__OM uint16_t T13RR
Definition: tle987x.h:1461
__IM uint16_t ICC61F
Definition: tle987x.h:1875
__IOM uint16_t MSEL61
Definition: tle987x.h:1688
__IOM uint16_t ENSTR
Definition: tle987x.h:1723
__IOM uint16_t MSEL62
Definition: tle987x.h:1689
CPU Core (CPU)
Definition: tle987x.h:1985
__IM uint32_t Int_DMA
Definition: tle987x.h:2172
__IOM uint32_t CP10
Definition: tle987x.h:2486
__IM uint32_t Int_GPT2
Definition: tle987x.h:2158
__IOM uint32_t PRI_CCU6SR1
Definition: tle987x.h:2197
__IOM uint32_t SVCALLPENDED
Definition: tle987x.h:2386
__IOM uint32_t PRI_6
Definition: tle987x.h:2336
__IOM uint32_t Int_CCU6SR2
Definition: tle987x.h:2059
__IOM uint32_t RELOAD
Definition: tle987x.h:2019
__IOM uint32_t CLKSOURCE
Definition: tle987x.h:2007
__IM uint32_t Int_GPT1
Definition: tle987x.h:2157
__IOM uint32_t DWTTRAP
Definition: tle987x.h:2445
__IOM uint32_t PRI_GPT1
Definition: tle987x.h:2183
__IOM uint32_t CP0
Definition: tle987x.h:2477
__IOM uint32_t PRI_BDRV
Definition: tle987x.h:2224
__IOM uint32_t DIVBYZERO
Definition: tle987x.h:2419
__IOM uint32_t USGFAULTACT
Definition: tle987x.h:2376
__IOM uint32_t DEBUGEVT
Definition: tle987x.h:2433
__IOM uint32_t PRI_ADC2
Definition: tle987x.h:2185
__IOM uint32_t PRI_8
Definition: tle987x.h:2347
__IOM uint32_t DIV_0_TRP
Definition: tle987x.h:2319
__IOM uint32_t CP3
Definition: tle987x.h:2480
__IM uint32_t Int_CCU6SR0
Definition: tle987x.h:2161
__IOM uint32_t Int_SSC1
Definition: tle987x.h:2061
__IOM uint32_t PRI_UART2
Definition: tle987x.h:2212
__IM uint32_t Int_ADC2
Definition: tle987x.h:2159
__IOM uint32_t TBLOFF
Definition: tle987x.h:2274
__IOM uint32_t EXTERNAL
Definition: tle987x.h:2447
__IOM uint32_t PRI_13
Definition: tle987x.h:2361
__IOM uint32_t SLEEPONEXIT
Definition: tle987x.h:2302
__IOM uint32_t PENDSVACT
Definition: tle987x.h:2381
__IOM uint32_t SYSRESETREQ
Definition: tle987x.h:2286
__IM uint32_t ARCHITECTURE
Definition: tle987x.h:2238
__IOM uint32_t PRI_14
Definition: tle987x.h:2362
__IM uint32_t Int_ADC1
Definition: tle987x.h:2160
__IOM uint32_t Int_GPT2
Definition: tle987x.h:2054
__IOM uint32_t PRIGROUP
Definition: tle987x.h:2288
__IOM uint32_t Int_UART2
Definition: tle987x.h:2064
__IOM uint32_t Int_BDRV
Definition: tle987x.h:2067
__IOM uint32_t VECTTBL
Definition: tle987x.h:2430
__IM uint32_t VECTACTIVE
Definition: tle987x.h:2250
__OM uint32_t PENDSTCLR
Definition: tle987x.h:2258
__IOM uint32_t PRI_EXINT0
Definition: tle987x.h:2222
__IOM uint32_t Int_SSC2
Definition: tle987x.h:2062
__IOM uint32_t HALTED
Definition: tle987x.h:2443
__IOM uint32_t PRI_11
Definition: tle987x.h:2350
__IOM uint32_t USGFAULTPENDED
Definition: tle987x.h:2383
__IOM uint32_t PRI_GPT2
Definition: tle987x.h:2184
__IM uint32_t IMPLEMENTER
Definition: tle987x.h:2240
__IOM uint32_t PRI_15
Definition: tle987x.h:2363
__IOM uint32_t NONBASETHRDENA
Definition: tle987x.h:2315
__IOM uint32_t CP11
Definition: tle987x.h:2487
__IM uint32_t Int_EXINT1
Definition: tle987x.h:2170
__IOM uint32_t SEVONPEND
Definition: tle987x.h:2305
__IM uint32_t Int_UART1
Definition: tle987x.h:2167
__IOM uint32_t MEMFAULTENA
Definition: tle987x.h:2387
__IM uint32_t INTLINESNUM
Definition: tle987x.h:1994
__IOM uint32_t UNALIGN_TRP
Definition: tle987x.h:2318
__IOM uint32_t SVCALLACT
Definition: tle987x.h:2378
__IOM uint32_t Int_ADC1
Definition: tle987x.h:2056
__IOM uint32_t PRI_DMA
Definition: tle987x.h:2225
__IOM uint32_t MEMFAULTACT
Definition: tle987x.h:2373
__IOM uint32_t Int_GPT1
Definition: tle987x.h:2053
__IOM uint32_t CP5
Definition: tle987x.h:2482
__IOM uint32_t Int_EXINT1
Definition: tle987x.h:2066
__IM uint32_t
Definition: tle987x.h:2008
__IOM uint32_t PRECISERR
Definition: tle987x.h:2407
__IOM uint32_t BUSFAULTENA
Definition: tle987x.h:2388
__IOM uint32_t USGFAULTENA
Definition: tle987x.h:2389
__IOM uint32_t FORCED
Definition: tle987x.h:2432
__IOM uint32_t COUNTFLAG
Definition: tle987x.h:2009
__IOM uint32_t PRI_10
Definition: tle987x.h:2349
__IOM uint32_t ENABLE
Definition: tle987x.h:2005
__IM uint32_t Int_BDRV
Definition: tle987x.h:2171
__IOM uint32_t BFHFMIGN
Definition: tle987x.h:2322
__IOM uint32_t NOCP
Definition: tle987x.h:2416
__IOM uint32_t CURRENT
Definition: tle987x.h:2029
__IOM uint32_t Int_CCU6SR0
Definition: tle987x.h:2057
__IM uint32_t ISRPENDING
Definition: tle987x.h:2255
__IOM uint32_t IACCVIOL
Definition: tle987x.h:2399
__IOM uint32_t MUNSTKERR
Definition: tle987x.h:2402
__IM uint32_t Int_SSC1
Definition: tle987x.h:2165
__IM uint32_t Int_SSC2
Definition: tle987x.h:2166
__IOM uint32_t PRI_12
Definition: tle987x.h:2360
__IOM uint32_t MEMFAULTPENDED
Definition: tle987x.h:2384
__IOM uint32_t IMPRECISERR
Definition: tle987x.h:2408
__IOM uint32_t STKALIGN
Definition: tle987x.h:2324
__IOM uint32_t Int_UART1
Definition: tle987x.h:2063
__IM uint32_t TENMS
Definition: tle987x.h:2039
__IM uint32_t PARTNO
Definition: tle987x.h:2237
__IOM uint32_t PRI_CCU6SR3
Definition: tle987x.h:2199
__IOM uint32_t ADDRESS
Definition: tle987x.h:2457
__IOM uint32_t PRI_ADC1
Definition: tle987x.h:2186
__IOM uint32_t BUSFAULTPENDED
Definition: tle987x.h:2385
__IOM uint32_t PRI_CCU6SR2
Definition: tle987x.h:2198
__IOM uint32_t MSTERR
Definition: tle987x.h:2403
__IOM uint32_t VCATCH
Definition: tle987x.h:2446
__IOM uint32_t UNDEFINSTR
Definition: tle987x.h:2413
__IOM uint32_t SLEEPDEEP
Definition: tle987x.h:2303
__IOM uint32_t PRI_UART1
Definition: tle987x.h:2211
__IM uint32_t SKEW
Definition: tle987x.h:2041
__IM uint32_t RESERVED
Definition: tle987x.h:1986
__IOM uint32_t PRI_9
Definition: tle987x.h:2348
__IM uint32_t REVISION
Definition: tle987x.h:2236
__IOM uint32_t CP7
Definition: tle987x.h:2484
__IOM uint32_t CP4
Definition: tle987x.h:2481
__IOM uint32_t PRI_CCU6SR0
Definition: tle987x.h:2196
__IOM uint32_t PRI_SSC1
Definition: tle987x.h:2209
__IOM uint32_t PRI_5
Definition: tle987x.h:2335
__IM uint32_t Int_CCU6SR3
Definition: tle987x.h:2164
__IOM uint32_t VECTCLRACTIVE
Definition: tle987x.h:2285
__IOM uint32_t PRI_7
Definition: tle987x.h:2337
__IOM uint32_t TICKINT
Definition: tle987x.h:2006
__IM uint32_t Int_CCU6SR1
Definition: tle987x.h:2162
__IOM uint32_t INVSTATE
Definition: tle987x.h:2414
__IOM uint32_t reg
Definition: tle987x.h:1990
__IOM uint32_t VECTKEY
Definition: tle987x.h:2291
__IOM uint32_t PENDSVSET
Definition: tle987x.h:2261
__IOM uint32_t SYSTICKACT
Definition: tle987x.h:2382
__IOM uint32_t PRI_SSC2
Definition: tle987x.h:2210
__IM uint32_t Int_CCU6SR2
Definition: tle987x.h:2163
__IOM uint32_t INVPC
Definition: tle987x.h:2415
__IM uint32_t ENDIANNESS
Definition: tle987x.h:2290
__IM uint32_t Int_EXINT0
Definition: tle987x.h:2169
__IOM uint32_t CP1
Definition: tle987x.h:2478
__IM uint32_t RETTOBASE
Definition: tle987x.h:2252
__IOM uint32_t NMIPENDSET
Definition: tle987x.h:2263
__IOM uint32_t Int_CCU6SR3
Definition: tle987x.h:2060
__IOM uint32_t UNALIGNED
Definition: tle987x.h:2418
__IOM uint32_t Int_DMA
Definition: tle987x.h:2068
__IM uint32_t NOREF
Definition: tle987x.h:2042
__IOM uint32_t VECTRESET
Definition: tle987x.h:2284
__IOM uint32_t CP6
Definition: tle987x.h:2483
__IOM uint32_t MONITORACT
Definition: tle987x.h:2379
__IOM uint32_t CP2
Definition: tle987x.h:2479
__IM uint32_t VARIANT
Definition: tle987x.h:2239
__IOM uint32_t Int_EXINT0
Definition: tle987x.h:2065
__IOM uint32_t STKERR
Definition: tle987x.h:2410
__IOM uint32_t BKPT
Definition: tle987x.h:2444
__IOM uint32_t IBUSERR
Definition: tle987x.h:2406
__IOM uint32_t PENDSTSET
Definition: tle987x.h:2259
__IOM uint32_t Int_ADC2
Definition: tle987x.h:2055
__IOM uint32_t MMARVALID
Definition: tle987x.h:2405
__IOM uint32_t Int_CCU6SR1
Definition: tle987x.h:2058
__IM uint32_t ISRPREEMPT
Definition: tle987x.h:2256
__IOM uint32_t BFARVALID
Definition: tle987x.h:2412
__IOM uint32_t PRI_4
Definition: tle987x.h:2334
__IM uint32_t Int_UART2
Definition: tle987x.h:2168
__IOM uint32_t DACCVIOL
Definition: tle987x.h:2400
__IOM uint32_t USERSETMPEND
Definition: tle987x.h:2316
__IOM uint32_t UNSTKERR
Definition: tle987x.h:2409
__IOM uint32_t BUSFAULTACT
Definition: tle987x.h:2374
__IM uint32_t VECTPENDING
Definition: tle987x.h:2253
__OM uint32_t PENDSVCLR
Definition: tle987x.h:2260
__IOM uint32_t PRI_EXINT1
Definition: tle987x.h:2223
Current Sense Amplifier (CSA)
Definition: tle987x.h:2504
__IO uint32_t reg
Definition: tle987x.h:2509
__IO uint32_t EN
Definition: tle987x.h:2513
__IO uint32_t GAIN
Definition: tle987x.h:2514
__IO uint32_t VZERO
Definition: tle987x.h:2516
Direct Memeory Access (DMA)
Definition: tle987x.h:2532
__IM uint32_t MASTER_ENABLE
Definition: tle987x.h:2540
__IOM uint32_t CHNL_PRIORITY_SET
Definition: tle987x.h:2708
__IM uint32_t WAITONREQ_STATUS
Definition: tle987x.h:2587
__OM uint32_t MASTER_ENABLE
Definition: tle987x.h:2554
__IM uint32_t
Definition: tle987x.h:2541
__IM uint32_t STATE
Definition: tle987x.h:2542
__IOM uint32_t ERR_CLR
Definition: tle987x.h:2734
__OM uint32_t CHNL_SW_REQUEST
Definition: tle987x.h:2597
__OM uint32_t CHNL_USEBURST_CLR
Definition: tle987x.h:2625
__OM uint32_t CHNL_REQ_MASK_CLR
Definition: tle987x.h:2650
__IOM uint32_t reg
Definition: tle987x.h:2536
__OM uint32_t CHNL_PRIORITY_CLR
Definition: tle987x.h:2723
__OM uint32_t CHNL_ENABLE_CLR
Definition: tle987x.h:2673
__IM uint32_t CHNLS_MINUS1
Definition: tle987x.h:2544
__IM uint32_t ALT_CTRL_BASE_PTR
Definition: tle987x.h:2577
__IOM uint32_t CHNL_USEBURST_SET
Definition: tle987x.h:2607
__IOM uint32_t CHNL_REQ_MASK_SET
Definition: tle987x.h:2635
__IOM uint32_t CTRL_BASE_PTR
Definition: tle987x.h:2567
__IOM uint32_t CHNL_ENABLE_SET
Definition: tle987x.h:2660
__IOM uint32_t CHNL_PRI_ALT_SET
Definition: tle987x.h:2683
__OM uint32_t CHN1_PROT_CTRL
Definition: tle987x.h:2556
__OM uint32_t CHNL_PRI_ALT_CLR
Definition: tle987x.h:2698
General Purpose Timer 12E (GPT12E)
Definition: tle987x.h:2753
__IOM uint16_t T2I
Definition: tle987x.h:2794
__IOM uint16_t T4UD
Definition: tle987x.h:2839
__IOM uint16_t T3EDGE
Definition: tle987x.h:2823
__IOM uint16_t T3UDE
Definition: tle987x.h:2819
__IOM uint16_t T5R
Definition: tle987x.h:2861
__IOM uint16_t T4CHDIR
Definition: tle987x.h:2846
__IOM uint16_t IST6IN
Definition: tle987x.h:2781
__IOM uint16_t T4IRDIS
Definition: tle987x.h:2844
__IOM uint16_t IST4IN
Definition: tle987x.h:2777
__IOM uint16_t T4
Definition: tle987x.h:2934
__IOM uint16_t T2R
Definition: tle987x.h:2796
__IOM uint16_t T5UDE
Definition: tle987x.h:2863
__IM uint16_t T4RDIR
Definition: tle987x.h:2847
__IOM uint16_t T4RC
Definition: tle987x.h:2841
__IM uint16_t T3RDIR
Definition: tle987x.h:2825
__IOM uint16_t T6M
Definition: tle987x.h:2881
__IOM uint16_t CLRT2EN
Definition: tle987x.h:2842
__IOM uint16_t IST5EUD
Definition: tle987x.h:2780
__IOM uint16_t T6OTL
Definition: tle987x.h:2886
__IOM uint16_t T6OE
Definition: tle987x.h:2885
__IM uint16_t RESERVED8
Definition: tle987x.h:2915
__IOM uint16_t T6SR
Definition: tle987x.h:2890
__IOM uint16_t T5I
Definition: tle987x.h:2858
__IM uint16_t RESERVED4
Definition: tle987x.h:2850
__IOM uint16_t T5RC
Definition: tle987x.h:2864
__IOM uint16_t T3M
Definition: tle987x.h:2816
__IM uint16_t MOD_TYPE
Definition: tle987x.h:2762
__IM uint16_t
Definition: tle987x.h:2800
__IOM uint16_t T2IRDIS
Definition: tle987x.h:2801
__IOM uint16_t T3UD
Definition: tle987x.h:2818
__IOM uint16_t T6UD
Definition: tle987x.h:2883
__IOM uint16_t T6I
Definition: tle987x.h:2880
__IM uint16_t RESERVED10
Definition: tle987x.h:2937
__IOM uint16_t T4R
Definition: tle987x.h:2838
__IOM uint16_t T3R
Definition: tle987x.h:2817
__IOM uint16_t CT3
Definition: tle987x.h:2865
__IOM uint16_t T4EDGE
Definition: tle987x.h:2845
__IOM uint16_t CI
Definition: tle987x.h:2867
__IOM uint16_t T2EDGE
Definition: tle987x.h:2802
__IOM uint16_t reg
Definition: tle987x.h:2757
__IOM uint16_t BPS1
Definition: tle987x.h:2822
__IM uint16_t RESERVED6
Definition: tle987x.h:2893
__IOM uint16_t IST4EUD
Definition: tle987x.h:2778
__IOM uint16_t T2UDE
Definition: tle987x.h:2798
__IOM uint16_t ISCAPIN
Definition: tle987x.h:2783
__IOM uint16_t IST3IN
Definition: tle987x.h:2775
__IOM uint16_t T3CHDIR
Definition: tle987x.h:2824
__IOM uint16_t T6R
Definition: tle987x.h:2882
__IOM uint16_t T6
Definition: tle987x.h:2956
__IOM uint16_t T5
Definition: tle987x.h:2945
__IOM uint16_t IST2IN
Definition: tle987x.h:2773
__IOM uint16_t T4M
Definition: tle987x.h:2837
__IOM uint16_t T3OTL
Definition: tle987x.h:2821
__IOM uint16_t IST2EUD
Definition: tle987x.h:2774
__IOM uint16_t T5SC
Definition: tle987x.h:2869
__IOM uint16_t T2CHDIR
Definition: tle987x.h:2803
__IOM uint16_t T2M
Definition: tle987x.h:2795
__IM uint16_t RESERVED11
Definition: tle987x.h:2948
__IM uint16_t T2RDIR
Definition: tle987x.h:2804
__IM uint16_t MOD_REV
Definition: tle987x.h:2761
__IOM uint16_t T3OE
Definition: tle987x.h:2820
__IOM uint16_t IST3EUD
Definition: tle987x.h:2776
__IOM uint16_t IST5IN
Definition: tle987x.h:2779
__IOM uint16_t T4I
Definition: tle987x.h:2836
__IOM uint16_t T3
Definition: tle987x.h:2923
__IM uint16_t RESERVED5
Definition: tle987x.h:2872
__IOM uint16_t T5UD
Definition: tle987x.h:2862
__IM uint16_t RESERVED9
Definition: tle987x.h:2926
__IOM uint16_t T4UDE
Definition: tle987x.h:2840
__IOM uint16_t T6UDE
Definition: tle987x.h:2884
__IOM uint16_t CLRT3EN
Definition: tle987x.h:2843
__IOM uint16_t T5CLR
Definition: tle987x.h:2868
__IOM uint16_t T6CLR
Definition: tle987x.h:2889
__IOM uint16_t CAPREL
Definition: tle987x.h:2901
__IM uint16_t RESERVED1
Definition: tle987x.h:2786
__IOM uint16_t T3I
Definition: tle987x.h:2815
__IM uint16_t RESERVED7
Definition: tle987x.h:2904
__IM uint16_t RESERVED3
Definition: tle987x.h:2828
__IOM uint16_t BPS2
Definition: tle987x.h:2887
__IM uint16_t RESERVED
Definition: tle987x.h:2765
__IOM uint16_t T2
Definition: tle987x.h:2912
__IOM uint16_t T5M
Definition: tle987x.h:2859
__IM uint16_t RESERVED2
Definition: tle987x.h:2807
__IOM uint16_t IST6EUD
Definition: tle987x.h:2782
__IOM uint16_t T2RC
Definition: tle987x.h:2799
__IOM uint16_t T2UD
Definition: tle987x.h:2797
Local Interconnect Network (LIN)
Definition: tle987x.h:2973
__IM uint32_t FB_SM2
Definition: tle987x.h:2993
__IOM uint32_t SM
Definition: tle987x.h:2991
__IM uint32_t FB_SM1
Definition: tle987x.h:2992
__IOM uint32_t HV_MODE
Definition: tle987x.h:2997
__IM uint32_t MODE_FB
Definition: tle987x.h:2995
__IM uint32_t OT_STS
Definition: tle987x.h:2984
__IM uint32_t
Definition: tle987x.h:2981
__IM uint32_t TXD_TMOUT_STS
Definition: tle987x.h:2986
__IM uint32_t FB_SM3
Definition: tle987x.h:2994
__IM uint32_t RXD
Definition: tle987x.h:2990
__IOM uint32_t TXD
Definition: tle987x.h:2988
__IOM uint32_t M_SM_ERR_CLR
Definition: tle987x.h:2999
__IOM uint32_t reg
Definition: tle987x.h:2977
__IM uint32_t OC_STS
Definition: tle987x.h:2985
__IM uint32_t M_SM_ERR
Definition: tle987x.h:2983
__IOM uint32_t MODE
Definition: tle987x.h:2982
Measurement Function (MF)
Definition: tle987x.h:3016
__IM uint32_t REFBG_LOTHWARN_STS
Definition: tle987x.h:3096
__IM uint32_t PMU_OT_STS
Definition: tle987x.h:3083
__IOM uint32_t PHUCOMP_ON
Definition: tle987x.h:3062
__IOM uint32_t BEMF_TFILT_SEL
Definition: tle987x.h:3127
__IM uint32_t PHU_ZC_STS
Definition: tle987x.h:3068
__IM uint32_t PHW_ZC_STS
Definition: tle987x.h:3070
__IOM uint32_t PHWCOMP_ON
Definition: tle987x.h:3064
__IOM uint32_t ADC3_INN_SEL
Definition: tle987x.h:3031
__IOM uint32_t P2_3_ADC_SEL
Definition: tle987x.h:3026
__IOM uint32_t BEMF_BT_TFILT_SEL
Definition: tle987x.h:3123
__IM uint32_t PHV_ZC_STS
Definition: tle987x.h:3069
__IOM uint32_t VMON_SEN_HRESO_5V
Definition: tle987x.h:3044
__IM uint32_t VREF5V_OV_STS
Definition: tle987x.h:3112
__IM uint32_t REFBG_UPTHWARN_STS
Definition: tle987x.h:3098
__IM uint32_t
Definition: tle987x.h:3029
__IOM uint32_t P2_5_ADC_SEL
Definition: tle987x.h:3028
__IM uint32_t SYS_OT_STS
Definition: tle987x.h:3085
__IM uint32_t VREF5V_UV_STS
Definition: tle987x.h:3111
__IOM uint32_t VMON_SEN_PD_N
Definition: tle987x.h:3042
__IM uint32_t SYS_OTWARN_STS
Definition: tle987x.h:3084
__IOM uint32_t PHWCOMP_EN
Definition: tle987x.h:3057
__IOM uint32_t DEMGFILTDIS
Definition: tle987x.h:3058
__IOM uint32_t PHVCOMP_ON
Definition: tle987x.h:3063
__IOM uint32_t P2_4_ADC_SEL
Definition: tle987x.h:3027
__IOM uint32_t PHUCOMP_EN
Definition: tle987x.h:3055
__IM uint32_t PMU_OTWARN_STS
Definition: tle987x.h:3082
__IOM uint32_t P2_2_ADC_SEL
Definition: tle987x.h:3025
__IOM uint32_t VREF5V_PD_N
Definition: tle987x.h:3109
__IOM uint32_t reg
Definition: tle987x.h:3020
__IM uint32_t VREF5V_OVL_STS
Definition: tle987x.h:3110
__IOM uint32_t PHVCOMP_EN
Definition: tle987x.h:3056
__IOM uint32_t ADC1_CH1_SEL
Definition: tle987x.h:3032
__IOM uint32_t ADC3_INP_SEL
Definition: tle987x.h:3030
__IOM uint32_t GPT12CAPINSW
Definition: tle987x.h:3060
__IM uint32_t RESERVED1
Definition: tle987x.h:3115
__IOM uint32_t P2_0_ADC_SEL
Definition: tle987x.h:3024
__IOM uint32_t FILTBYPS
Definition: tle987x.h:3059
__IOM uint32_t VMON_SEN_SEL_INRANGE
Definition: tle987x.h:3045
__IOM uint32_t CCPOS_INSEL
Definition: tle987x.h:3066
__IOM uint32_t BEMF_GPT_CAPIN_SEL
Definition: tle987x.h:3125
__IM uint32_t RESERVED0
Definition: tle987x.h:3073
MON (MON)
Definition: tle987x.h:3143
__IO uint8_t CYC
Definition: tle987x.h:3155
__IO uint8_t PD
Definition: tle987x.h:3156
__IO uint8_t PU
Definition: tle987x.h:3157
__IO uint8_t EN
Definition: tle987x.h:3152
__IO uint8_t FALL
Definition: tle987x.h:3153
__IO uint8_t RISE
Definition: tle987x.h:3154
__I uint8_t STS
Definition: tle987x.h:3159
__IO uint8_t reg
Definition: tle987x.h:3148
Power Management Unit (PMU)
Definition: tle987x.h:3175
__IOM uint8_t LOCKUP
Definition: tle987x.h:3258
__IOM uint8_t GPIO0_FA_3
Definition: tle987x.h:3514
__IOM uint8_t GPIO0_RI_2
Definition: tle987x.h:3498
__IOM uint8_t GPIO0_RI_0
Definition: tle987x.h:3496
__IOM uint8_t CNF_MON_FT
Definition: tle987x.h:3418
__IOM uint8_t DATA1
Definition: tle987x.h:3441
__IM uint8_t GPIO0_STS_4
Definition: tle987x.h:3391
__IOM uint8_t PMU_1V5DidPOR
Definition: tle987x.h:3245
__IOM uint8_t CNF_LIN_FT
Definition: tle987x.h:3417
__IOM uint8_t GPIO1_RI_0
Definition: tle987x.h:3541
__IOM uint8_t GPIO1_RI_3
Definition: tle987x.h:3544
__IOM uint8_t CYC_WAKE_EN
Definition: tle987x.h:3272
__IOM uint8_t SUPPFAIL
Definition: tle987x.h:3363
__IM uint8_t PMU_5V_OVERLOAD
Definition: tle987x.h:3206
__IM uint8_t PMU_5V_OVERVOLT
Definition: tle987x.h:3205
__IOM uint8_t GPIO1_FA_0
Definition: tle987x.h:3556
__IOM uint8_t GPIO0_FA_4
Definition: tle987x.h:3515
__IOM uint8_t OVERLOAD
Definition: tle987x.h:3224
__IOM uint8_t PMU_1V5_OVL
Definition: tle987x.h:3348
__IOM uint8_t M03
Definition: tle987x.h:3286
__IM uint8_t GPIO1_STS_1
Definition: tle987x.h:3403
__IM uint8_t GPIO1_STS_4
Definition: tle987x.h:3406
__IOM uint8_t PMU_ClkWDT
Definition: tle987x.h:3242
__IM uint8_t GPIO1
Definition: tle987x.h:3187
__IOM uint8_t GPIO0_CYC_0
Definition: tle987x.h:3526
__IOM uint8_t PMU_5V_FAIL_EN
Definition: tle987x.h:3207
__IM uint8_t LIN_WAKE
Definition: tle987x.h:3183
__IOM uint8_t DATA2
Definition: tle987x.h:3452
__IOM uint8_t DATA5
Definition: tle987x.h:3485
__IOM uint8_t DATA0
Definition: tle987x.h:3430
__IOM uint8_t GPIO0_RI_4
Definition: tle987x.h:3500
__IM uint8_t
Definition: tle987x.h:3204
__IOM uint8_t GPIO1_RI_1
Definition: tle987x.h:3542
__IOM uint8_t OSC_100kHz_EN
Definition: tle987x.h:3289
__IOM uint8_t LIN_EN
Definition: tle987x.h:3324
__IM uint8_t GPIO0_STS_1
Definition: tle987x.h:3388
__IOM uint8_t GPIO0_CYC_2
Definition: tle987x.h:3528
__IM uint8_t GPIO1_STS_0
Definition: tle987x.h:3402
__IOM uint8_t GPIO1_RI_2
Definition: tle987x.h:3543
__IOM uint8_t E01
Definition: tle987x.h:3287
__IOM uint8_t WAKE_W_RST
Definition: tle987x.h:3269
__IOM uint8_t GPIO1_CYC_3
Definition: tle987x.h:3574
__IOM uint8_t GPIO0_RI_3
Definition: tle987x.h:3499
__IOM uint8_t GPIO0_CYC_1
Definition: tle987x.h:3527
__IOM uint8_t PMU_ExtWDT
Definition: tle987x.h:3243
__IOM uint8_t DATA4
Definition: tle987x.h:3474
__IOM uint8_t SUPP_SHORT
Definition: tle987x.h:3346
__IOM uint8_t GPIO1_FA_2
Definition: tle987x.h:3558
__IOM uint8_t MBIST_EN
Definition: tle987x.h:3586
__IM uint8_t WAKE_STS
Definition: tle987x.h:3376
__IOM uint8_t GPIO0_RI_1
Definition: tle987x.h:3497
__IM uint8_t GPIO0
Definition: tle987x.h:3185
__IOM uint8_t OVERVOLT
Definition: tle987x.h:3223
__IM uint8_t GPIO0_STS_3
Definition: tle987x.h:3390
__IOM uint8_t SHORT
Definition: tle987x.h:3222
__IOM uint8_t GPIO1_FA_3
Definition: tle987x.h:3559
__IOM uint8_t GPIO1_RI_4
Definition: tle987x.h:3545
__IOM uint8_t GPIO1_FA_4
Definition: tle987x.h:3560
__IOM uint8_t WDT1_SEQ_FAIL
Definition: tle987x.h:3352
__IM uint8_t MON_WAKE
Definition: tle987x.h:3184
__IOM uint8_t GPIO0_FA_0
Definition: tle987x.h:3511
__IM uint8_t FAIL
Definition: tle987x.h:3190
__IOM uint8_t CYC_EN
Definition: tle987x.h:3219
__IOM uint8_t GPIO0_CYC_3
Definition: tle987x.h:3529
__IM uint8_t STABLE
Definition: tle987x.h:3226
__IOM uint8_t RST_TFB
Definition: tle987x.h:3335
__IOM uint8_t SUPP_TMOUT
Definition: tle987x.h:3347
__IOM uint8_t VDDEXTSHORT
Definition: tle987x.h:3365
__IOM uint8_t GPIO0_CYC_4
Definition: tle987x.h:3530
__IOM uint8_t CNF_GPIO_FT
Definition: tle987x.h:3419
__IM uint8_t OK
Definition: tle987x.h:3225
__IOM uint8_t FAIL_EN
Definition: tle987x.h:3220
__IOM uint8_t PMU_WAKE
Definition: tle987x.h:3239
__IOM uint8_t GPIO1_CYC_4
Definition: tle987x.h:3575
__IM uint8_t GPIO1_STS_3
Definition: tle987x.h:3405
__IOM uint8_t PMU_5V_OVL
Definition: tle987x.h:3349
__IOM uint8_t PMU_IntWDT
Definition: tle987x.h:3256
__IM uint8_t CYC_WAKE
Definition: tle987x.h:3189
__IOM uint8_t GPIO0_FA_1
Definition: tle987x.h:3512
__IM uint8_t PMU_1V5_OVERVOLT
Definition: tle987x.h:3201
__IM uint8_t GPIO0_STS_2
Definition: tle987x.h:3389
__IM uint8_t GPIO0_STS_0
Definition: tle987x.h:3387
__IOM uint8_t GPIO0_FA_2
Definition: tle987x.h:3513
__IOM uint8_t SYS_FAIL
Definition: tle987x.h:3237
__IOM uint8_t PMU_PIN
Definition: tle987x.h:3244
__IOM uint8_t PMU_SOFT
Definition: tle987x.h:3257
__IOM uint8_t PMU_SleepEX
Definition: tle987x.h:3240
__IOM uint8_t DATA3
Definition: tle987x.h:3463
__IOM uint8_t GPIO1_FA_1
Definition: tle987x.h:3557
__IM uint8_t GPIO1_STS_2
Definition: tle987x.h:3404
__IOM uint8_t PMU_LPR
Definition: tle987x.h:3241
__IM uint8_t PMU_1V5_OVERLOAD
Definition: tle987x.h:3202
__IOM uint8_t GPIO1_CYC_0
Definition: tle987x.h:3571
__IOM uint8_t GPIO1_CYC_2
Definition: tle987x.h:3573
__IOM uint8_t reg
Definition: tle987x.h:3179
__IOM uint8_t GPIO1_CYC_1
Definition: tle987x.h:3572
__IOM uint8_t SYS_OT
Definition: tle987x.h:3351
__IOM uint8_t EN_VDDEXT_OC_OFF_N
Definition: tle987x.h:3275
__IOM uint8_t EN_0V9_N
Definition: tle987x.h:3270
__IOM uint8_t ENABLE
Definition: tle987x.h:3218
__IOM uint8_t PMU_1V5_FAIL_EN
Definition: tle987x.h:3203
__IOM uint8_t CYC_SENSE_EN
Definition: tle987x.h:3273
GPIO PORTs (PORT)
Definition: tle987x.h:3604
__IM uint8_t P4
Definition: tle987x.h:3676
__IOM uint8_t P1
Definition: tle987x.h:3613
__IM uint8_t P2
Definition: tle987x.h:3674
__IOM uint8_t P4
Definition: tle987x.h:3616
__IM uint8_t
Definition: tle987x.h:3673
__IOM uint8_t P0
Definition: tle987x.h:3612
__IM uint8_t P5
Definition: tle987x.h:3677
__IM uint8_t P0
Definition: tle987x.h:3672
__IOM uint8_t P2
Definition: tle987x.h:3614
__IOM uint8_t P3_P2
Definition: tle987x.h:3874
__IOM uint8_t P3
Definition: tle987x.h:3615
__IM uint8_t P3
Definition: tle987x.h:3675
__IOM uint8_t reg
Definition: tle987x.h:3608
__IOM uint8_t P5
Definition: tle987x.h:3693
System Control Unit (SCU)
Definition: tle987x.h:3892
__IOM uint8_t CH8IE
Definition: tle987x.h:4815
__OM uint8_t T2C
Definition: tle987x.h:4931
__OM uint8_t EXINT0RC
Definition: tle987x.h:4051
__IOM uint8_t NMIECC
Definition: tle987x.h:4025
__IM uint8_t FNMIECC
Definition: tle987x.h:3995
__IOM uint8_t LOCKUP
Definition: tle987x.h:4283
__IOM uint8_t K1DIV
Definition: tle987x.h:4166
__IOM uint8_t T2_DIS
Definition: tle987x.h:4255
__IOM uint8_t SECTORINFO
Definition: tle987x.h:4664
__IOM uint8_t TIREN1
Definition: tle987x.h:4078
__OM uint8_t CCU6SR2C
Definition: tle987x.h:5032
__IM uint8_t TRSEQ1DY
Definition: tle987x.h:4880
__IOM uint8_t T3IE
Definition: tle987x.h:4898
__IOM uint8_t T4IE
Definition: tle987x.h:4899
__OM uint8_t CH6C
Definition: tle987x.h:4989
__OM uint8_t NMINVMC
Definition: tle987x.h:3902
__IM uint8_t T2
Definition: tle987x.h:4914
__IOM uint8_t BR_VALUE
Definition: tle987x.h:4392
__IOM uint8_t PDM3
Definition: tle987x.h:4722
__IOM uint8_t EXINT1IS
Definition: tle987x.h:4537
__IM uint8_t NVM_ADDR_ERR
Definition: tle987x.h:4691
__OM uint8_t NMIWDTC
Definition: tle987x.h:3900
__IOM uint8_t SL
Definition: tle987x.h:4136
__IOM uint8_t T2_SUSP
Definition: tle987x.h:4594
__IOM uint8_t EXINT2IS
Definition: tle987x.h:4538
__OM uint8_t T3C
Definition: tle987x.h:4932
__IM uint8_t CCU6SR1
Definition: tle987x.h:3965
__IM uint8_t EXINT1R
Definition: tle987x.h:3920
__IM uint8_t CH7
Definition: tle987x.h:4867
__OM uint8_t NMIECCC
Definition: tle987x.h:3906
__IM uint8_t EXINT1F
Definition: tle987x.h:3921
__OM uint8_t RIRC
Definition: tle987x.h:4949
__IOM uint8_t OSCSS
Definition: tle987x.h:4505
__OM uint8_t RDBEC
Definition: tle987x.h:4793
__IOM uint8_t SSC2_DIS
Definition: tle987x.h:4268
__IOM uint8_t K2DIV
Definition: tle987x.h:4165
__IOM uint8_t COUTS0
Definition: tle987x.h:4522
__IOM uint8_t CRIE
Definition: tle987x.h:4902
__IOM uint8_t T12PM_DMAEN
Definition: tle987x.h:4846
__IOM uint8_t MU_SUSP
Definition: tle987x.h:4609
__IOM uint8_t VCOBYP
Definition: tle987x.h:4152
__IOM uint8_t EXINT0IS
Definition: tle987x.h:4536
__IOM uint8_t IE1
Definition: tle987x.h:4124
__IOM uint8_t CPCLK_DIV
Definition: tle987x.h:4212
__IOM uint8_t RIEN2
Definition: tle987x.h:4098
__IOM uint8_t WDTWINB
Definition: tle987x.h:4345
__IOM uint8_t CPCLK_SEL
Definition: tle987x.h:4211
__OM uint8_t CCU6SR1C
Definition: tle987x.h:5021
__IM uint8_t EXINT2R
Definition: tle987x.h:3922
__IOM uint8_t RIREN2
Definition: tle987x.h:4095
__OM uint8_t TIRC
Definition: tle987x.h:4948
__IM uint8_t T5
Definition: tle987x.h:4917
__IOM uint8_t NVMIE
Definition: tle987x.h:4637
__OM uint8_t EXINT1RC
Definition: tle987x.h:4055
__IOM uint8_t XTAL_ON
Definition: tle987x.h:4135
__IOM uint8_t NMIMAP
Definition: tle987x.h:4024
__IOM uint8_t CH6IE
Definition: tle987x.h:4813
__IOM uint8_t GPT12CAPINB
Definition: tle987x.h:4551
__OM uint8_t GPT12C
Definition: tle987x.h:5007
__OM uint8_t NMIOWDC
Definition: tle987x.h:3904
__OM uint8_t CCU6SR3C
Definition: tle987x.h:5034
__IOM uint8_t BRDIS
Definition: tle987x.h:4414
__OM uint8_t TRSEQ1DYC
Definition: tle987x.h:5003
__OM uint8_t BRKC
Definition: tle987x.h:4467
__IOM uint8_t COUTS1
Definition: tle987x.h:4524
__IOM uint8_t NMISUP
Definition: tle987x.h:4026
__OM uint8_t CH3C
Definition: tle987x.h:4986
__IOM uint8_t COREL
Definition: tle987x.h:4521
__IOM uint8_t T21_DIS
Definition: tle987x.h:4270
__IM uint8_t T6
Definition: tle987x.h:4918
__IOM uint8_t PDM0
Definition: tle987x.h:4707
__IOM uint8_t T5IE
Definition: tle987x.h:4900
__IOM uint8_t EN
Definition: tle987x.h:4525
__IOM uint8_t NVMPROTSTSL_2
Definition: tle987x.h:4678
__IOM uint8_t WINBEN
Definition: tle987x.h:4194
__IOM uint8_t RESLD
Definition: tle987x.h:4150
__IM uint8_t MONF
Definition: tle987x.h:3925
__IM uint8_t EIR
Definition: tle987x.h:3937
__IOM uint8_t CCU6_DIS
Definition: tle987x.h:4254
__IM uint8_t MONSTS
Definition: tle987x.h:4113
__OM uint8_t MONFC
Definition: tle987x.h:4065
__OM uint8_t SSC1C
Definition: tle987x.h:5005
__IOM uint8_t TRSEQ1RDYIE
Definition: tle987x.h:4827
__OM uint8_t CH5C
Definition: tle987x.h:4988
__IM uint8_t APCLK1STS
Definition: tle987x.h:4226
__IM uint8_t FNMINVM
Definition: tle987x.h:3991
__IOM uint8_t TLEN
Definition: tle987x.h:4523
__IOM uint8_t VCOSEL
Definition: tle987x.h:4167
__IOM uint8_t T21IS
Definition: tle987x.h:4566
__IM uint8_t FNMIOT
Definition: tle987x.h:3992
__IM uint8_t SSCTX
Definition: tle987x.h:4848
__IM uint8_t CR
Definition: tle987x.h:4919
__IOM uint8_t EXINT1
Definition: tle987x.h:4038
__IOM uint8_t BRPRE
Definition: tle987x.h:4379
__IOM uint8_t ADC1_SUSP
Definition: tle987x.h:4610
__IOM uint8_t APCLK1FAC
Definition: tle987x.h:4223
__IOM uint8_t IE0
Definition: tle987x.h:4110
__IOM uint8_t CH1IE
Definition: tle987x.h:4808
__IM uint8_t
Definition: tle987x.h:3964
__IOM uint8_t OSCDISC
Definition: tle987x.h:4151
__IOM uint8_t LOCKUP_EN
Definition: tle987x.h:4285
__IM uint8_t CCU6SR2
Definition: tle987x.h:3976
__IOM uint8_t TCC
Definition: tle987x.h:4744
__OM uint8_t GPT12_T3C
Definition: tle987x.h:5048
__IOM uint8_t SSCRXIE
Definition: tle987x.h:4830
__IOM uint8_t APCLK1SCLR
Definition: tle987x.h:4224
__OM uint8_t TRSEQ2DYC
Definition: tle987x.h:5004
__IOM uint8_t R
Definition: tle987x.h:4378
__IOM uint8_t T2IS
Definition: tle987x.h:4565
__OM uint8_t NMIMAPC
Definition: tle987x.h:3905
__IOM uint8_t T21EXCON
Definition: tle987x.h:4554
__IOM uint8_t SSCTXSRCSEL
Definition: tle987x.h:4843
__IM uint8_t BRK
Definition: tle987x.h:4416
__IOM uint8_t PDM1
Definition: tle987x.h:4709
__IOM uint8_t CH5IE
Definition: tle987x.h:4812
__IOM uint8_t WDTSUSP
Definition: tle987x.h:4591
__IM uint8_t CH2
Definition: tle987x.h:4862
__IOM uint8_t EA
Definition: tle987x.h:4008
__IM uint8_t FNMISUP
Definition: tle987x.h:3996
__OM uint8_t EIRC
Definition: tle987x.h:4947
__OM uint8_t EXINT1FC
Definition: tle987x.h:4057
__IOM uint8_t CLKWDT_IE
Definition: tle987x.h:4208
__OM uint8_t SDADCC
Definition: tle987x.h:5008
__IM uint8_t CH6
Definition: tle987x.h:4866
__IOM uint8_t TIEN1
Definition: tle987x.h:4082
__IOM uint8_t SDADCCLK_DIV
Definition: tle987x.h:4296
__OM uint8_t NMIPLLC
Definition: tle987x.h:3901
__IOM uint8_t APCLK3SCLR
Definition: tle987x.h:4228
__OM uint8_t EOFSYNC
Definition: tle987x.h:4468
__IOM uint8_t T12SUSP
Definition: tle987x.h:4592
__IM uint8_t EXINT0R
Definition: tle987x.h:3918
__IOM uint8_t TRSEQ2RDYIE
Definition: tle987x.h:4828
__IOM uint8_t T21_SUSP
Definition: tle987x.h:4597
__IOM uint8_t EIREN1
Definition: tle987x.h:4077
__IM uint8_t RDBE
Definition: tle987x.h:4649
__IOM uint8_t T12ZM_DMAEN
Definition: tle987x.h:4845
__IOM uint8_t T2EXCON
Definition: tle987x.h:4553
__IM uint8_t OSC2L
Definition: tle987x.h:4507
__IOM uint8_t TRIG_CONF
Definition: tle987x.h:4622
__IOM uint8_t URIOS1
Definition: tle987x.h:4539
__IOM uint8_t MRAMINITSTS
Definition: tle987x.h:4322
__IOM uint8_t INIT_FAIL
Definition: tle987x.h:4321
__IOM uint8_t SASTATUS
Definition: tle987x.h:4665
__IOM uint8_t T3_DIS
Definition: tle987x.h:4272
__IM uint8_t RSBE
Definition: tle987x.h:4653
__IM uint8_t FNMIWDT
Definition: tle987x.h:3989
__OM uint8_t EXINT0FC
Definition: tle987x.h:4053
__IOM uint8_t PD
Definition: tle987x.h:4137
__IOM uint8_t OSCWDTRST
Definition: tle987x.h:4506
__OM uint8_t T6C
Definition: tle987x.h:4935
__IM uint8_t VERID
Definition: tle987x.h:4480
__OM uint8_t MONRC
Definition: tle987x.h:4063
__IOM uint8_t BGSEL
Definition: tle987x.h:4415
__IM uint8_t EOFSYN
Definition: tle987x.h:4417
__IM uint8_t APCLK2STS
Definition: tle987x.h:4240
__IM uint8_t ROM_PROT_ERR
Definition: tle987x.h:4694
__IOM uint8_t APCLK2SCLR
Definition: tle987x.h:4241
__IOM uint8_t SD
Definition: tle987x.h:4138
__IOM uint8_t PBA0CLKREL
Definition: tle987x.h:4178
__IOM uint8_t NMIWDT
Definition: tle987x.h:4019
__IM uint8_t PLL_LOCK
Definition: tle987x.h:4205
__IOM uint8_t SYSCLKSEL
Definition: tle987x.h:4310
__IOM uint8_t NDIV
Definition: tle987x.h:4153
__IOM uint8_t WDTRS
Definition: tle987x.h:4190
__IM uint8_t FNMIOWD
Definition: tle987x.h:3993
__IM uint8_t GPT12_T3
Definition: tle987x.h:4850
__IM uint8_t CH8
Definition: tle987x.h:4868
__IOM uint8_t CLKREL
Definition: tle987x.h:4164
__IOM uint8_t APCLK_SET
Definition: tle987x.h:4206
__IOM uint8_t MODE
Definition: tle987x.h:4492
__IM uint8_t SSC1RDY
Definition: tle987x.h:4882
__IOM uint8_t RIE
Definition: tle987x.h:4635
__IM uint8_t EXINT0F
Definition: tle987x.h:3919
__IM uint8_t SSC2RDY
Definition: tle987x.h:4883
__OM uint8_t EXINT2FC
Definition: tle987x.h:4061
__OM uint8_t CH8C
Definition: tle987x.h:4991
__IM uint8_t APCLK3STS
Definition: tle987x.h:4227
__IOM uint8_t T2EXIS
Definition: tle987x.h:4567
__OM uint8_t CH1C
Definition: tle987x.h:4984
__IM uint8_t LOCK
Definition: tle987x.h:4149
__IOM uint8_t NVMPROTSTSL_1
Definition: tle987x.h:4677
__IM uint8_t CH1
Definition: tle987x.h:4861
__IM uint8_t CCU6SR3
Definition: tle987x.h:3978
__OM uint8_t T5C
Definition: tle987x.h:4934
__OM uint8_t CH4C
Definition: tle987x.h:4987
__IM uint8_t ERRSYN
Definition: tle987x.h:4418
__IOM uint8_t NMIOWD
Definition: tle987x.h:4023
__IOM uint8_t T13SUSP
Definition: tle987x.h:4593
__IOM uint8_t GPT12IE
Definition: tle987x.h:4831
__OM uint8_t RSBEC
Definition: tle987x.h:4797
__OM uint8_t NVMDBEC
Definition: tle987x.h:4795
__OM uint8_t CCU6SR0C
Definition: tle987x.h:5019
__IOM uint8_t RIEN1
Definition: tle987x.h:4081
__OM uint8_t SSC2C
Definition: tle987x.h:5006
__IM uint8_t PRODID
Definition: tle987x.h:4481
__OM uint8_t NMIOTC
Definition: tle987x.h:3903
__IOM uint8_t MONIE
Definition: tle987x.h:4112
__IOM uint8_t NVMPROTSTSL_3
Definition: tle987x.h:4679
__OM uint8_t CH2C
Definition: tle987x.h:4985
__IM uint8_t RAM_PROT_ERR
Definition: tle987x.h:4696
__IM uint8_t CCU6SR0
Definition: tle987x.h:3963
__IOM uint8_t NMIPLL
Definition: tle987x.h:4020
__IM uint8_t PROTECT_S
Definition: tle987x.h:4493
__IM uint8_t CH5
Definition: tle987x.h:4865
__IM uint8_t MONR
Definition: tle987x.h:3924
__IOM uint8_t CH7IE
Definition: tle987x.h:4814
__IOM uint8_t WDTREL
Definition: tle987x.h:4334
__IOM uint8_t ADC1_DIS
Definition: tle987x.h:4252
__IOM uint8_t PDM4
Definition: tle987x.h:4733
__IM uint8_t CH3
Definition: tle987x.h:4863
__IOM uint8_t RIREN1
Definition: tle987x.h:4079
__IOM uint8_t BGCLK_SEL
Definition: tle987x.h:4209
__IOM uint8_t T21EXIS
Definition: tle987x.h:4568
__IOM uint8_t NVMCLKFAC
Definition: tle987x.h:4309
__IOM uint8_t T3CLK_SEL
Definition: tle987x.h:4207
__IOM uint8_t NMINVM
Definition: tle987x.h:4021
__IOM uint8_t FD_SEL
Definition: tle987x.h:4391
__IM uint8_t EXINT2F
Definition: tle987x.h:3923
__IOM uint8_t SSCTXIE
Definition: tle987x.h:4829
__IOM uint8_t APCLK2FAC
Definition: tle987x.h:4239
__IOM uint8_t T6IE
Definition: tle987x.h:4901
__OM uint8_t SSCTXC
Definition: tle987x.h:5046
__IOM uint8_t T3CLK_DIV
Definition: tle987x.h:4297
__IOM uint8_t WDTEN
Definition: tle987x.h:4191
__OM uint8_t SSCRXC
Definition: tle987x.h:5047
__IOM uint8_t CH2IE
Definition: tle987x.h:4809
__IM uint8_t WDT
Definition: tle987x.h:4356
__IM uint8_t T4
Definition: tle987x.h:4916
__IOM uint8_t OSCTRIM_8
Definition: tle987x.h:4510
__IOM uint8_t GPT12_DIS
Definition: tle987x.h:4256
__IOM uint8_t XPD
Definition: tle987x.h:4508
__IOM uint8_t NMIOT
Definition: tle987x.h:4022
__IM uint8_t NVM_SFR_PROT_ERR
Definition: tle987x.h:4692
__IOM uint8_t BGCLK_DIV
Definition: tle987x.h:4210
__IOM uint8_t MON_Trig_Sel
Definition: tle987x.h:4040
__IOM uint8_t SYNEN
Definition: tle987x.h:4419
__IOM uint8_t GPT12_DMAEN
Definition: tle987x.h:4973
__IM uint8_t T3
Definition: tle987x.h:4915
__IM uint8_t NVM_PROT_ERR
Definition: tle987x.h:4690
__IOM uint8_t EXINT0
Definition: tle987x.h:4037
__IOM uint8_t SSCRXSRCSEL
Definition: tle987x.h:4844
__OM uint8_t CRC
Definition: tle987x.h:4936
__OM uint8_t EXINT2RC
Definition: tle987x.h:4059
__IOM uint8_t PG100TP_CHKS_ERR
Definition: tle987x.h:4323
__IOM uint8_t CH3IE
Definition: tle987x.h:4810
__IOM uint8_t TIREN2
Definition: tle987x.h:4094
__IOM uint8_t SDADCIE
Definition: tle987x.h:4832
__IM uint8_t SDADC
Definition: tle987x.h:4885
__IOM uint8_t GPT12
Definition: tle987x.h:4621
__IOM uint8_t NVMPROTSTSL_0
Definition: tle987x.h:4676
__IOM uint8_t CH4IE
Definition: tle987x.h:4811
__IM uint8_t STRDY
Definition: tle987x.h:4879
__IM uint8_t GPT12
Definition: tle987x.h:4884
__IM uint8_t ROM_ADDR_ERR
Definition: tle987x.h:4695
__IM uint8_t TRSEQ2DY
Definition: tle987x.h:4881
__IOM uint8_t T3_SUSP
Definition: tle987x.h:4608
__IOM uint8_t PDM2
Definition: tle987x.h:4720
__IOM uint8_t EXINT2_EN
Definition: tle987x.h:4097
__IM uint8_t SSCRX
Definition: tle987x.h:4849
__IM uint8_t CH4
Definition: tle987x.h:4864
__OM uint8_t ERRSYNC
Definition: tle987x.h:4469
__IM uint8_t FNMIPLL
Definition: tle987x.h:3990
__IM uint8_t TIR
Definition: tle987x.h:3938
__IOM uint8_t EXINT2
Definition: tle987x.h:4039
__IOM uint8_t reg
Definition: tle987x.h:3896
__IOM uint8_t GPT12_SUSP
Definition: tle987x.h:4595
__OM uint8_t NMISUPC
Definition: tle987x.h:3907
__IOM uint8_t EIREN2
Definition: tle987x.h:4093
__IM uint8_t FNMIMAP
Definition: tle987x.h:3994
__IOM uint8_t U_TX_CONDIS
Definition: tle987x.h:4540
__OM uint8_t CH7C
Definition: tle987x.h:4990
__IOM uint8_t SSC1_DIS
Definition: tle987x.h:4253
__IM uint8_t NVMDBE
Definition: tle987x.h:4651
__IOM uint8_t WDTIN
Definition: tle987x.h:4189
__IM uint8_t NVM_SFR_ADDR_ERR
Definition: tle987x.h:4693
__OM uint8_t T4C
Definition: tle987x.h:4933
__IOM uint8_t TRERRIE
Definition: tle987x.h:4826
__IOM uint8_t T2IE
Definition: tle987x.h:4897
__IM uint8_t RIR
Definition: tle987x.h:3939
__IOM uint8_t PASS
Definition: tle987x.h:4494
__IOM uint8_t T3_GPT12_SEL
Definition: tle987x.h:4623
__IOM uint8_t TIEN2
Definition: tle987x.h:4099
__IOM uint8_t URIOS2
Definition: tle987x.h:4580
__IM uint8_t WDTPR
Definition: tle987x.h:4193
System Control Unit for Power Modules (SCUPM)
Definition: tle987x.h:5065
__IM uint32_t PHU_ZCHI_STS
Definition: tle987x.h:5191
__IOM uint32_t SOWCONF
Definition: tle987x.h:5331
__IOM uint32_t PHV_ZCLOW_IE
Definition: tle987x.h:5294
__OM uint32_t HS3_OC_ICLR
Definition: tle987x.h:5357
__IOM uint32_t LS2_OC_IE
Definition: tle987x.h:5447
__IM uint32_t LIN_OT_IS
Definition: tle987x.h:5161
__IM uint32_t VDD5V_OV_STS
Definition: tle987x.h:5220
__IOM uint32_t PHU_ZCLOW_IE
Definition: tle987x.h:5292
__IM uint32_t PHU_ZCLOW_STS
Definition: tle987x.h:5190
__IM uint32_t VREF5V_UPTH_IS
Definition: tle987x.h:5178
__IM uint32_t PHW_ZCLOW_IS
Definition: tle987x.h:5186
__IM uint32_t ADC2_ESM_IS
Definition: tle987x.h:5181
__IOM uint32_t AMCLK2_UP_TH
Definition: tle987x.h:5101
__OM uint32_t VSD_UPTH_SCLR
Definition: tle987x.h:5377
__IM uint32_t LS3_DS_IS
Definition: tle987x.h:5395
__IM uint32_t VCP_LOWTH2_STS
Definition: tle987x.h:5416
__IM uint32_t VSD_LOWTH_IS
Definition: tle987x.h:5411
__IM uint32_t SYS_OTWARN_IS
Definition: tle987x.h:5168
__IOM uint32_t VREF5V_OVL_IE
Definition: tle987x.h:5290
__IM uint32_t PHW_ZCHI_STS
Definition: tle987x.h:5195
__IOM uint32_t HS3_DS_IE
Definition: tle987x.h:5443
__IOM uint32_t AMCLK2_LOW_TH
Definition: tle987x.h:5103
__IM uint32_t HS3_OC_IS
Definition: tle987x.h:5404
__IOM uint32_t HS2_OC_IE
Definition: tle987x.h:5449
__IM uint32_t PHV_ZCHI_STS
Definition: tle987x.h:5193
__OM uint32_t VCP_UPTH_ICLR
Definition: tle987x.h:5362
__OM uint32_t LIN_TMOUT_ICLR
Definition: tle987x.h:5117
__OM uint32_t VDD1V5_OV_ICLR
Definition: tle987x.h:5255
__OM uint32_t VSD_LOWTH_SCLR
Definition: tle987x.h:5375
__IOM uint32_t AMCLK1_UP_TH
Definition: tle987x.h:5097
__OM uint32_t HS3_DS_ICLR
Definition: tle987x.h:5349
__IOM uint32_t VS_UV_IE
Definition: tle987x.h:5232
__IM uint32_t PHV_ZCLOW_IS
Definition: tle987x.h:5184
__OM uint32_t MON_OV_ICLR
Definition: tle987x.h:5252
__IM uint32_t LS2_DS_IS
Definition: tle987x.h:5390
__IOM uint32_t VDD1V5_OV_IE
Definition: tle987x.h:5238
__IM uint32_t DBFSTS
Definition: tle987x.h:5478
__IOM uint32_t REFBG_LOTHWARN_IE
Definition: tle987x.h:5284
__IM uint32_t PHU_ZCHI_IS
Definition: tle987x.h:5183
__IM uint32_t VREF5V_OVL_IS
Definition: tle987x.h:5180
__IM uint32_t PHV_ZCHI_IS
Definition: tle987x.h:5185
__IOM uint32_t MON_UV_IE
Definition: tle987x.h:5231
__IM uint32_t LS1_OC_IS
Definition: tle987x.h:5399
__IOM uint32_t VCP_LOWTH1_IE
Definition: tle987x.h:5453
__IM uint32_t VS_UV_STS
Definition: tle987x.h:5215
__IM uint32_t MON_OV_IS
Definition: tle987x.h:5209
__IM uint32_t VDD1V5_UV_STS
Definition: tle987x.h:5217
__IM uint32_t HS1_OC_IS
Definition: tle987x.h:5401
__OM uint32_t REFBG_UPTHWARN_ICLR
Definition: tle987x.h:5129
__IOM uint32_t ADC3_EOC_IE
Definition: tle987x.h:5298
__OM uint32_t VCP_LOWTH1_SCLR
Definition: tle987x.h:5371
__IM uint32_t VDD1V5_OV_IS
Definition: tle987x.h:5212
__OM uint32_t VREF5V_LOWTH_ICLR
Definition: tle987x.h:5131
__IOM uint32_t LIN_OT_IE
Definition: tle987x.h:5275
__IOM uint32_t HS1_DS_IE
Definition: tle987x.h:5438
__OM uint32_t VS_OV_ICLR
Definition: tle987x.h:5253
__IM uint32_t HS3_DS_IS
Definition: tle987x.h:5396
__IOM uint32_t SYS_VSD_OV_SLM_DIS
Definition: tle987x.h:5316
__IOM uint32_t FAIL_PS_DIS
Definition: tle987x.h:5313
__OM uint32_t PHU_ZCLOW_SCLR
Definition: tle987x.h:5145
__IM uint32_t PHV_ZCLOW_STS
Definition: tle987x.h:5192
__OM uint32_t VCP_UPTH_SCLR
Definition: tle987x.h:5373
__OM uint32_t VDD5V_UV_ICLR
Definition: tle987x.h:5250
__IOM uint32_t LS3_OC_IE
Definition: tle987x.h:5450
__IM uint32_t HS2_DS_IS
Definition: tle987x.h:5393
__IOM uint32_t PMU_OTWARN_IE
Definition: tle987x.h:5278
__IOM uint32_t SYS_OT_IE
Definition: tle987x.h:5282
__IOM uint32_t VDD1V5_UV_IE
Definition: tle987x.h:5234
__IM uint32_t PHW_ZCHI_IS
Definition: tle987x.h:5187
__IOM uint32_t LIN_VS_UV_SD_DIS
Definition: tle987x.h:5314
__IM uint32_t AMCLK2_FREQ
Definition: tle987x.h:5076
__IM uint32_t PHU_ZCLOW_IS
Definition: tle987x.h:5182
__OM uint32_t LS3_DS_ICLR
Definition: tle987x.h:5348
__IM uint32_t AMCLK1_FREQ
Definition: tle987x.h:5073
__IOM uint32_t SYS_OT_PS_DIS
Definition: tle987x.h:5318
__OM uint32_t ADC3_EOC_ICLR
Definition: tle987x.h:5143
__IOM uint32_t AMCLK1_UP_HYS
Definition: tle987x.h:5098
__IM uint32_t
Definition: tle987x.h:5075
__OM uint32_t PHW_ZCLOW_SCLR
Definition: tle987x.h:5149
__IOM uint32_t AMCLK2_UP_HYS
Definition: tle987x.h:5102
__OM uint32_t VCP_LOWTH1_ICLR
Definition: tle987x.h:5360
__IOM uint32_t CLKLOSS_SD_DIS
Definition: tle987x.h:5319
__OM uint32_t ADC4_EOC_ICLR
Definition: tle987x.h:5144
__OM uint32_t VCP_LOWTH2_ICLR
Definition: tle987x.h:5358
__IOM uint32_t WDP_SEL
Definition: tle987x.h:5330
__IM uint32_t HS2_OC_IS
Definition: tle987x.h:5402
__IM uint32_t VS_UV_IS
Definition: tle987x.h:5206
__OM uint32_t PHV_ZCLOW_SCLR
Definition: tle987x.h:5147
__IOM uint32_t AMCLK1_LOW_TH
Definition: tle987x.h:5099
__IM uint32_t SBFSTS
Definition: tle987x.h:5479
__OM uint32_t VDD1V5_OV_SCLR
Definition: tle987x.h:5264
__IM uint32_t REFBG_UPTHWARN_IS
Definition: tle987x.h:5174
__IOM uint32_t CLKWDT_RES_SD_DIS
Definition: tle987x.h:5320
__IOM uint32_t LIN_OC_IE
Definition: tle987x.h:5274
__OM uint32_t MON_OV_SCLR
Definition: tle987x.h:5261
__IM uint32_t SYS_OT_IS
Definition: tle987x.h:5170
__IOM uint32_t VCP_UPTH_IE
Definition: tle987x.h:5454
__OM uint32_t VSD_LOWTH_ICLR
Definition: tle987x.h:5364
__IOM uint32_t LIN_TMOUT_IE
Definition: tle987x.h:5276
__IOM uint32_t LS1_DS_IE
Definition: tle987x.h:5436
__IOM uint32_t VSD_LOWTH_IE
Definition: tle987x.h:5455
__OM uint32_t PHV_ZCHI_ICLR
Definition: tle987x.h:5140
__OM uint32_t DBFSTSCLR
Definition: tle987x.h:5509
__IOM uint32_t MON_OV_IE
Definition: tle987x.h:5235
__IM uint32_t ADC4_EOC_IS
Definition: tle987x.h:5189
__IOM uint32_t AMCLK2_LOW_HYS
Definition: tle987x.h:5104
__IM uint32_t VREF5V_LOWTH_IS
Definition: tle987x.h:5176
__OM uint32_t PHW_ZCHI_ICLR
Definition: tle987x.h:5142
__OM uint32_t ADC2_ESM_ICLR
Definition: tle987x.h:5136
__OM uint32_t VDD5V_OV_ICLR
Definition: tle987x.h:5254
__IM uint32_t VCP_UPTH_STS
Definition: tle987x.h:5420
__IM uint32_t MON_UV_STS
Definition: tle987x.h:5214
__IM uint32_t DBFA
Definition: tle987x.h:5489
__IOM uint32_t STCALIB
Definition: tle987x.h:5467
__IOM uint32_t HS2_DS_IE
Definition: tle987x.h:5440
__OM uint32_t VS_UV_SCLR
Definition: tle987x.h:5258
__OM uint32_t PMU_OT_ICLR
Definition: tle987x.h:5121
__IOM uint32_t LS3_DS_IE
Definition: tle987x.h:5442
__OM uint32_t VREF5V_UPTH_ICLR
Definition: tle987x.h:5133
__IM uint32_t VS_OV_STS
Definition: tle987x.h:5219
__OM uint32_t PHU_ZCHI_SCLR
Definition: tle987x.h:5146
__IM uint32_t MON_OV_STS
Definition: tle987x.h:5218
__IM uint32_t LS3_OC_IS
Definition: tle987x.h:5403
__IM uint32_t VS_OV_IS
Definition: tle987x.h:5210
__IM uint32_t VCP_LOWTH1_IS
Definition: tle987x.h:5407
__IOM uint32_t VREF5V_UPTH_IE
Definition: tle987x.h:5288
__IM uint32_t PMU_OTWARN_IS
Definition: tle987x.h:5164
__OM uint32_t PHV_ZCHI_SCLR
Definition: tle987x.h:5148
__IOM uint32_t CLKWDT_SD_DIS
Definition: tle987x.h:5311
__IM uint32_t ADC3_EOC_IS
Definition: tle987x.h:5188
__IOM uint32_t PHU_ZCHI_IE
Definition: tle987x.h:5293
__OM uint32_t VS_OV_SCLR
Definition: tle987x.h:5262
__IOM uint32_t HS1_OC_IE
Definition: tle987x.h:5448
__OM uint32_t SYS_OTWARN_ICLR
Definition: tle987x.h:5123
__OM uint32_t PMU_OTWARN_ICLR
Definition: tle987x.h:5119
__OM uint32_t HS2_DS_ICLR
Definition: tle987x.h:5346
__OM uint32_t VDD5V_UV_SCLR
Definition: tle987x.h:5259
__OM uint32_t LS1_OC_ICLR
Definition: tle987x.h:5352
__IOM uint32_t VSD_UPTH_IE
Definition: tle987x.h:5456
__IM uint32_t RESERVED
Definition: tle987x.h:5089
__OM uint32_t HS1_DS_ICLR
Definition: tle987x.h:5344
__OM uint32_t HS1_OC_ICLR
Definition: tle987x.h:5354
__IM uint32_t SBFA
Definition: tle987x.h:5499
__OM uint32_t LIN_OC_ICLR
Definition: tle987x.h:5115
__OM uint32_t REFBG_LOTHWARN_ICLR
Definition: tle987x.h:5127
__OM uint32_t VSD_UPTH_ICLR
Definition: tle987x.h:5366
__IOM uint32_t VDD5V_OV_IE
Definition: tle987x.h:5237
__IOM uint32_t ADC2_ESM_IE
Definition: tle987x.h:5291
__IOM uint32_t reg
Definition: tle987x.h:5069
__IOM uint32_t VDD5V_UV_IE
Definition: tle987x.h:5233
__IM uint32_t HS1_DS_IS
Definition: tle987x.h:5391
__OM uint32_t PHW_ZCLOW_ICLR
Definition: tle987x.h:5141
__OM uint32_t PHV_ZCLOW_ICLR
Definition: tle987x.h:5139
__IOM uint32_t LS1_OC_IE
Definition: tle987x.h:5446
__OM uint32_t PHU_ZCLOW_ICLR
Definition: tle987x.h:5137
__OM uint32_t VREF5V_OVL_ICLR
Definition: tle987x.h:5135
__OM uint32_t VDD1V5_UV_ICLR
Definition: tle987x.h:5251
__IM uint32_t VSD_UPTH_STS
Definition: tle987x.h:5424
__IM uint32_t VSD_LOWTH_STS
Definition: tle987x.h:5422
__IM uint32_t LIN_TMOUT_IS
Definition: tle987x.h:5162
__IOM uint32_t PHW_ZCHI_IE
Definition: tle987x.h:5297
__IM uint32_t LIN_OC_IS
Definition: tle987x.h:5160
__OM uint32_t LS2_DS_ICLR
Definition: tle987x.h:5343
__IOM uint32_t HS3_OC_IE
Definition: tle987x.h:5451
__OM uint32_t LS3_OC_ICLR
Definition: tle987x.h:5356
__OM uint32_t VS_UV_ICLR
Definition: tle987x.h:5249
__IM uint32_t REFBG_LOTHWARN_IS
Definition: tle987x.h:5172
__IOM uint32_t PHV_ZCHI_IE
Definition: tle987x.h:5295
__IM uint32_t VDD5V_OV_IS
Definition: tle987x.h:5211
__IM uint32_t RESERVED2
Definition: tle987x.h:5302
__IM uint32_t LS1_DS_IS
Definition: tle987x.h:5389
__OM uint32_t SYS_OT_ICLR
Definition: tle987x.h:5125
__OM uint32_t LS2_OC_ICLR
Definition: tle987x.h:5353
__IOM uint32_t ADC4_EOC_IE
Definition: tle987x.h:5299
__IM uint32_t LS2_OC_IS
Definition: tle987x.h:5400
__OM uint32_t LS1_DS_ICLR
Definition: tle987x.h:5342
__IM uint32_t PMU_OT_IS
Definition: tle987x.h:5166
__IOM uint32_t VS_OV_IE
Definition: tle987x.h:5236
__OM uint32_t MON_UV_SCLR
Definition: tle987x.h:5257
__IM uint32_t VCP_LOWTH2_IS
Definition: tle987x.h:5405
__OM uint32_t PHU_ZCHI_ICLR
Definition: tle987x.h:5138
__IOM uint32_t LS2_DS_IE
Definition: tle987x.h:5437
__OM uint32_t VDD5V_OV_SCLR
Definition: tle987x.h:5263
__IOM uint32_t VREF5V_LOWTH_IE
Definition: tle987x.h:5286
__IM uint32_t PHW_ZCLOW_STS
Definition: tle987x.h:5194
__IM uint32_t RESERVED1
Definition: tle987x.h:5107
__OM uint32_t PHW_ZCHI_SCLR
Definition: tle987x.h:5150
__IOM uint32_t REFBG_UPTHWARN_IE
Definition: tle987x.h:5285
__OM uint32_t SBFSTSCLR
Definition: tle987x.h:5510
__IM uint32_t VCP_UPTH_IS
Definition: tle987x.h:5409
__OM uint32_t VCP_LOWTH2_SCLR
Definition: tle987x.h:5369
__IOM uint32_t AMCLK1_LOW_HYS
Definition: tle987x.h:5100
__OM uint32_t LIN_OT_ICLR
Definition: tle987x.h:5116
__OM uint32_t HS2_OC_ICLR
Definition: tle987x.h:5355
__OM uint32_t VDD1V5_UV_SCLR
Definition: tle987x.h:5260
__IM uint32_t VDD5V_UV_STS
Definition: tle987x.h:5216
__IM uint32_t MON_UV_IS
Definition: tle987x.h:5205
__OM uint32_t MON_UV_ICLR
Definition: tle987x.h:5248
__IM uint32_t VDD1V5_OV_STS
Definition: tle987x.h:5221
__IM uint32_t VDD5V_UV_IS
Definition: tle987x.h:5207
__IM uint32_t VSD_UPTH_IS
Definition: tle987x.h:5413
__IOM uint32_t SYS_OTWARN_IE
Definition: tle987x.h:5281
__IOM uint32_t PHW_ZCLOW_IE
Definition: tle987x.h:5296
__IOM uint32_t VCP_LOWTH2_IE
Definition: tle987x.h:5452
__IM uint32_t VDD1V5_UV_IS
Definition: tle987x.h:5208
__IM uint32_t VCP_LOWTH1_STS
Definition: tle987x.h:5418
__IOM uint32_t CLKWDT_PD_N
Definition: tle987x.h:5086
__IOM uint32_t PMU_OT_IE
Definition: tle987x.h:5279
SSC1 Module (SSC1)
Definition: tle987x.h:5527
__IM uint16_t TE
Definition: tle987x.h:5563
__IOM uint16_t BR_VALUE
Definition: tle987x.h:5603
__OM uint16_t PECLR
Definition: tle987x.h:5617
__IM uint16_t BSY
Definition: tle987x.h:5567
__OM uint16_t RECLR
Definition: tle987x.h:5616
__OM uint16_t BECLR
Definition: tle987x.h:5618
__IOM uint16_t MIS_0
Definition: tle987x.h:5535
__IM uint16_t RB_VALUE
Definition: tle987x.h:5592
__IM uint16_t RESERVED4
Definition: tle987x.h:5606
__IM uint16_t
Definition: tle987x.h:5562
__IOM uint16_t SIS
Definition: tle987x.h:5539
__IOM uint16_t reg
Definition: tle987x.h:5531
__IOM uint16_t MIS_1
Definition: tle987x.h:5549
__OM uint16_t TECLR
Definition: tle987x.h:5615
__IOM uint16_t TB_VALUE
Definition: tle987x.h:5581
__IM uint16_t PE
Definition: tle987x.h:5565
__IOM uint16_t CIS
Definition: tle987x.h:5544
__IM uint16_t BC
Definition: tle987x.h:5561
__IM uint16_t RE
Definition: tle987x.h:5564
__IOM uint16_t EN
Definition: tle987x.h:5570
__IM uint16_t RESERVED1
Definition: tle987x.h:5573
__IM uint16_t BE
Definition: tle987x.h:5566
__IM uint16_t RESERVED3
Definition: tle987x.h:5595
__IM uint16_t RESERVED
Definition: tle987x.h:5553
__IM uint16_t RESERVED2
Definition: tle987x.h:5584
__IOM uint16_t MS
Definition: tle987x.h:5569
SSC2 Module (SSC2)
Definition: tle987x.h:5635
__IM uint16_t TE
Definition: tle987x.h:5671
__IOM uint16_t BR_VALUE
Definition: tle987x.h:5711
__OM uint16_t PECLR
Definition: tle987x.h:5725
__IM uint16_t BSY
Definition: tle987x.h:5675
__OM uint16_t RECLR
Definition: tle987x.h:5724
__OM uint16_t BECLR
Definition: tle987x.h:5726
__IOM uint16_t MIS_0
Definition: tle987x.h:5643
__IM uint16_t RB_VALUE
Definition: tle987x.h:5700
__IM uint16_t RESERVED4
Definition: tle987x.h:5714
__IM uint16_t
Definition: tle987x.h:5670
__IOM uint16_t SIS
Definition: tle987x.h:5647
__IOM uint16_t reg
Definition: tle987x.h:5639
__IOM uint16_t MIS_1
Definition: tle987x.h:5657
__OM uint16_t TECLR
Definition: tle987x.h:5723
__IOM uint16_t TB_VALUE
Definition: tle987x.h:5689
__IM uint16_t PE
Definition: tle987x.h:5673
__IOM uint16_t CIS
Definition: tle987x.h:5652
__IM uint16_t BC
Definition: tle987x.h:5669
__IM uint16_t RE
Definition: tle987x.h:5672
__IOM uint16_t EN
Definition: tle987x.h:5678
__IM uint16_t RESERVED1
Definition: tle987x.h:5681
__IM uint16_t BE
Definition: tle987x.h:5674
__IM uint16_t RESERVED3
Definition: tle987x.h:5703
__IM uint16_t RESERVED
Definition: tle987x.h:5661
__IM uint16_t RESERVED2
Definition: tle987x.h:5692
__IOM uint16_t MS
Definition: tle987x.h:5677
TIMER2x Module (TIMER2x)
Definition: tle987x.h:5743
__IOM uint8_t EXF2EN
Definition: tle987x.h:5828
__IOM uint8_t PREN
Definition: tle987x.h:5770
__IOM uint8_t CP_RL2
Definition: tle987x.h:5751
__IOM uint8_t TR2
Definition: tle987x.h:5753
__IM uint8_t
Definition: tle987x.h:5755
__IOM uint8_t EXEN2
Definition: tle987x.h:5754
__IOM uint8_t T2REGS
Definition: tle987x.h:5773
__IOM uint8_t RC2
Definition: tle987x.h:5784
__IOM uint8_t DCEN
Definition: tle987x.h:5768
__IM uint8_t TF2
Definition: tle987x.h:5757
__IOM uint8_t T2L
Definition: tle987x.h:5806
__IM uint8_t EXF2
Definition: tle987x.h:5756
__IOM uint8_t TF2EN
Definition: tle987x.h:5829
__IOM uint8_t EDGESEL
Definition: tle987x.h:5771
__OM uint8_t EXF2CLR
Definition: tle987x.h:5841
__IOM uint8_t T2H
Definition: tle987x.h:5817
__IOM uint8_t T2PRE
Definition: tle987x.h:5769
__OM uint8_t TF2CLR
Definition: tle987x.h:5842
__IOM uint8_t T2RHEN
Definition: tle987x.h:5772
__IOM uint8_t reg
Definition: tle987x.h:5747
__IOM uint8_t C_T2
Definition: tle987x.h:5752
TIMER3 Module (TIMER3)
Definition: tle987x.h:5859
__IOM uint32_t T3_RD_REQ
Definition: tle987x.h:5904
__IOM uint32_t TR3H
Definition: tle987x.h:5907
__IOM uint32_t T3_RD_REQ_CONF
Definition: tle987x.h:5905
__IOM uint32_t T3_PD_N
Definition: tle987x.h:5903
__IM uint32_t T3H_OVF_STS
Definition: tle987x.h:5908
__IOM uint32_t T3_RES_CONF
Definition: tle987x.h:5869
__IOM uint32_t T3H_OVF_IE
Definition: tle987x.h:5912
__IOM uint32_t RETRIG
Definition: tle987x.h:5870
__IM uint32_t
Definition: tle987x.h:5868
__IOM uint32_t CNT_RDY
Definition: tle987x.h:5906
__IOM uint32_t T3_SUBM
Definition: tle987x.h:5924
__IOM uint32_t LO
Definition: tle987x.h:5881
__IM uint32_t T3L_OVF_STS
Definition: tle987x.h:5910
__IOM uint32_t TR3L
Definition: tle987x.h:5909
__IOM uint32_t reg
Definition: tle987x.h:5863
__IOM uint32_t T3L_OVF_IE
Definition: tle987x.h:5911
__IOM uint32_t HI
Definition: tle987x.h:5882
__IOM uint32_t T3_TRIGG_INP_SEL
Definition: tle987x.h:5867
__OM uint32_t T3L_OVF_ICLR
Definition: tle987x.h:5937
__OM uint32_t T3H_OVF_ICLR
Definition: tle987x.h:5935
__IOM uint32_t T3M
Definition: tle987x.h:5922
UARTx Module (UARTx)
Definition: tle987x.h:5954
__OM uint8_t TICLR
Definition: tle987x.h:5993
__IOM uint8_t TI
Definition: tle987x.h:5963
__IOM uint8_t REN
Definition: tle987x.h:5966
__IOM uint8_t SM0
Definition: tle987x.h:5970
__IOM uint8_t SM2
Definition: tle987x.h:5967
__IOM uint8_t SM1
Definition: tle987x.h:5969
__IOM uint8_t RI
Definition: tle987x.h:5962
__IOM uint8_t TB8
Definition: tle987x.h:5965
__IOM uint8_t RB8
Definition: tle987x.h:5964
__OM uint8_t RICLR
Definition: tle987x.h:5992
__IOM uint8_t VAL
Definition: tle987x.h:5981
__IOM uint8_t reg
Definition: tle987x.h:5958
System file for TLE987x.