96 #include "dma_defines.h"
123 #define DMA_CH10 (10u)
125 #define DMA_CH11 (11u)
127 #define DMA_CH12 (12u)
128 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
130 #define DMA_CH13 (13u)
134 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
136 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
138 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
140 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
142 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
144 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
146 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
148 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
150 #define DMA_MASK_CH8 ((uint16)1u << DMA_CH8)
152 #define DMA_MASK_CH9 ((uint16)1u << DMA_CH9)
154 #define DMA_MASK_CH10 ((uint16)1u << DMA_CH10)
156 #define DMA_MASK_CH11 ((uint16)1u << DMA_CH11)
158 #define DMA_MASK_CH12 ((uint16)1u << DMA_CH12)
159 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
161 #define DMA_MASK_CH13 ((uint16)1u << DMA_CH13)
165 #define DMA_SRC_INCREMENT 1u
167 #define DMA_DEST_INCREMENT 2u
540 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
1149 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
1323 #if (DMA_XML_VERSION >= 10200)
1610 DMA->CFG.bit.MASTER_ENABLE = 1u;
1613 #error "use IFXConfigWizard XML Version V1.2.0 or greater"
INLINE void DMA_CH0_Int_Clr(void)
clears DMA Channel 0 Interrupt flag.
Definition: dma.h:271
INLINE void DMA_Master_En(void)
Enabled the DMA master.
Definition: dma.h:1607
INLINE void DMA_CH10_Int_Dis(void)
disables DMA Channel 10 Interrupt.
Definition: dma.h:1054
INLINE void DMA_CH10_Int_Clr(void)
clears DMA Channel 10 Interrupt flag.
Definition: dma.h:491
INLINE uint32 DMA_CHx_Entry_Alt(uint8 DMA_Ch)
This function returns the address inside the alternate structure in RAM for a given DMA channel.
Definition: dma.h:1303
INLINE void DMA_CH5_Int_Dis(void)
disables DMA Channel 5 Interrupt.
Definition: dma.h:829
enum DMA_Increment_Size TDMA_Increment_Size
INLINE void DMA_CH11_Int_En(void)
enables DMA Channel 11 Interrupt.
Definition: dma.h:1076
INLINE void DMA_CH3_Int_Clr(void)
clears DMA Channel 3 Interrupt flag.
Definition: dma.h:337
DMA_Transfer_Size
Definition: dma.h:173
@ DMA_32Bit_Transfer
Definition: dma.h:176
@ DMA_8Bit_Transfer
Definition: dma.h:174
@ DMA_16Bit_Transfer
Definition: dma.h:175
INLINE void DMA_CH5_Int_En(void)
enables DMA Channel 5 Interrupt.
Definition: dma.h:806
INLINE void DMA_CH6_Int_Dis(void)
disables DMA Channel 6 Interrupt.
Definition: dma.h:874
INLINE void DMA_CH9_Int_Dis(void)
disables DMA Channel 9 Interrupt.
Definition: dma.h:1009
enum DMA_Cycle_Types TDMA_Cycle_Types
INLINE void DMA_CH0_Int_En(void)
enables DMA Channel 0 Interrupt.
Definition: dma.h:581
INLINE void DMA_CH13_Int_Clr(void)
clears DMA Channel 13 Interrupt flag.
Definition: dma.h:558
INLINE void DMA_CH7_Int_Clr(void)
clears DMA Channel 7 Interrupt flag.
Definition: dma.h:425
INLINE void DMA_CH1_Int_Dis(void)
disables DMA Channel 1 Interrupt.
Definition: dma.h:649
INLINE void DMA_CH4_Int_Dis(void)
disables DMA Channel 4 Interrupt.
Definition: dma.h:784
enum DMA_Increment_Mode TDMA_Increment_Mode
INLINE void DMA_CH11_Int_Dis(void)
disables DMA Channel 11 Interrupt.
Definition: dma.h:1099
INLINE void DMA_Primary_Struct_Usage_Set(uint32 mask_ch)
selects the primary data structure for the corresponding DMA channel.
Definition: dma.h:1271
DMA_Increment_Mode
Definition: dma.h:193
@ DMA_No_Inc
Definition: dma.h:194
@ DMA_Src_Inc
Definition: dma.h:195
@ DMA_Dst_Inc
Definition: dma.h:196
@ DMA_Src_Dst_Inc
Definition: dma.h:197
INLINE void DMA_CH0_Int_Dis(void)
disables DMA Channel 0 Interrupt.
Definition: dma.h:604
void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt)
Resets the primary structure in RAM for a given channel and rearms it.
INLINE void DMA_CH13_Int_Dis(void)
disables DMA Channel 13 Interrupt.
Definition: dma.h:1190
INLINE void DMA_CH9_Int_En(void)
enables DMA Channel 9 Interrupt.
Definition: dma.h:986
INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
enables DMA Channels.
Definition: dma.h:1231
#define DMA_SRC_INCREMENT
DMA source increment.
Definition: dma.h:165
INLINE void DMA_CH4_Int_Clr(void)
clears DMA Channel 4 Interrupt flag.
Definition: dma.h:359
INLINE void DMA_CH11_Int_Clr(void)
clears DMA Channel 11 Interrupt flag.
Definition: dma.h:513
INLINE void DMA_CH2_Int_Dis(void)
disables DMA Channel 2 Interrupt.
Definition: dma.h:694
TDMA_Entry * DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up a task to be used in the Scatter-Gather modes.
INLINE void DMA_CH3_Int_En(void)
enables DMA Channel 3 Interrupt.
Definition: dma.h:716
INLINE void DMA_CH8_Int_En(void)
enables DMA Channel 8 Interrupt.
Definition: dma.h:941
INLINE void DMA_CH6_Int_En(void)
enables DMA Channel 6 Interrupt.
Definition: dma.h:851
INLINE void DMA_CH1_Int_Clr(void)
clears DMA Channel 1 Interrupt flag.
Definition: dma.h:293
DMA_Cycle_Types
Definition: dma.h:204
@ DMA_Cycle_Type_PerSctGthPrim
Definition: dma.h:211
@ DMA_Cycle_Type_Basic
Definition: dma.h:206
@ DMA_Cycle_Type_MemSctGthPrim
Definition: dma.h:209
@ DMA_Cycle_Type_Auto
Definition: dma.h:207
@ DMA_Cycle_Type_PingPong
Definition: dma.h:208
@ DMA_Cycle_Type_MemSctGthAlt
Definition: dma.h:210
@ DMA_Cycle_Type_PerSctGthAlt
Definition: dma.h:212
@ DMA_Cycle_Type_Invalid
Definition: dma.h:205
INLINE void DMA_CH7_Int_Dis(void)
disables DMA Channel 7 Interrupt.
Definition: dma.h:919
INLINE void DMA_CH5_Int_Clr(void)
clears DMA Channel 5 Interrupt flag.
Definition: dma.h:381
INLINE void DMA_CH12_Int_Dis(void)
disables DMA Channel 12 Interrupt.
Definition: dma.h:1144
void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up the desired DMA channel in the primary structure in RAM.
INLINE void DMA_CH2_Int_Clr(void)
clears DMA Channel 2 Interrupt flag.
Definition: dma.h:315
INLINE void DMA_CH1_Int_En(void)
enables DMA Channel 1 Interrupt.
Definition: dma.h:626
INLINE void DMA_Alternate_Struct_Usage_Set(uint32 mask_ch)
selects the alternate data structure for the corresponding DMA channel.
Definition: dma.h:1291
void DMA_Init(void)
Initializes the DMA structure in RAM and SFRs based on the Config Wizard for MOTIX MCU configuration.
INLINE void DMA_Software_Request_Set(uint32 mask_ch)
Set software request for DMA Channels.
Definition: dma.h:1251
INLINE void DMA_CH7_Int_En(void)
enables DMA Channel 7 Interrupt.
Definition: dma.h:896
enum DMA_Transfer_Size TDMA_Transfer_Size
INLINE void DMA_CH3_Int_Dis(void)
disables DMA Channel 3 Interrupt.
Definition: dma.h:739
INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
points to the base address of the primary data structure.
Definition: dma.h:1211
INLINE void DMA_CH13_Int_En(void)
enables DMA Channel 13 Interrupt.
Definition: dma.h:1167
INLINE void DMA_CH9_Int_Clr(void)
clears DMA Channel 9 Interrupt flag.
Definition: dma.h:469
INLINE void DMA_CH6_Int_Clr(void)
clears DMA Channel 6 Interrupt flag.
Definition: dma.h:403
void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.
void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
INLINE void DMA_CH2_Int_En(void)
enables DMA Channel 2 Interrupt.
Definition: dma.h:671
INLINE void DMA_CH4_Int_En(void)
enables DMA Channel 4 Interrupt.
Definition: dma.h:761
DMA_Increment_Size
Definition: dma.h:183
@ DMA_Inc_8bit
Definition: dma.h:184
@ DMA_Inc_32bit
Definition: dma.h:186
@ DMA_Inc_16bit
Definition: dma.h:185
INLINE uint32 DMA_CHx_Entry_Pri(uint8 DMA_Ch)
This function returns the address inside the primary structure in RAM for a given DMA channel.
Definition: dma.h:1315
#define DMA_DEST_INCREMENT
DMA destination increment.
Definition: dma.h:167
INLINE void DMA_CH10_Int_En(void)
enables DMA Channel 10 Interrupt.
Definition: dma.h:1031
INLINE void DMA_CH8_Int_Dis(void)
disables DMA Channel 8 Interrupt.
Definition: dma.h:964
INLINE void DMA_CH12_Int_Clr(void)
clears DMA Channel 12 Interrupt flag.
Definition: dma.h:535
INLINE void DMA_CH8_Int_Clr(void)
clears DMA Channel 8 Interrupt flag.
Definition: dma.h:447
INLINE void DMA_CH12_Int_En(void)
enables DMA Channel 12 Interrupt.
Definition: dma.h:1121
TDMA_Entry * DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
Sets up a task to be used with memory scatter-gather mode.
#define DMA
Definition: tle987x.h:6064
#define SCU
Definition: tle987x.h:6071
#define SCU_DMAIRC1CLR_CH8C_Pos
Definition: tle987x.h:8833
#define SCU_DMAIEN1_CH1IE_Msk
Definition: tle987x.h:8799
#define SCU_DMAIEN1_CH7IE_Pos
Definition: tle987x.h:8786
#define SCU_DMAIRC2CLR_SDADCC_Pos
Definition: tle987x.h:8865
#define SCU_DMAIRC1CLR_CH7C_Pos
Definition: tle987x.h:8835
#define SCU_DMAIRC2CLR_SSC1C_Pos
Definition: tle987x.h:8871
#define SCU_DMAIRC1CLR_CH4C_Pos
Definition: tle987x.h:8841
#define SCU_DMAIRC2CLR_SSC1C_Msk
Definition: tle987x.h:8872
#define SCU_DMAIEN2_SSCTXIE_Pos
Definition: tle987x.h:8807
#define SCU_DMAIEN1_CH3IE_Pos
Definition: tle987x.h:8794
#define SCU_DMAIRC1CLR_CH5C_Pos
Definition: tle987x.h:8839
#define SCU_DMAIRC1CLR_CH1C_Msk
Definition: tle987x.h:8848
#define SCU_DMAIEN2_TRSEQ2RDYIE_Pos
Definition: tle987x.h:8809
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk
Definition: tle987x.h:7896
#define SCU_DMAIEN2_SDADCIE_Msk
Definition: tle987x.h:8802
#define SCU_DMAIRC1CLR_CH1C_Pos
Definition: tle987x.h:8847
#define SCU_DMAIEN1_CH8IE_Msk
Definition: tle987x.h:8785
#define SCU_DMAIRC1CLR_CH2C_Pos
Definition: tle987x.h:8845
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos
Definition: tle987x.h:7892
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos
Definition: tle987x.h:8875
#define SCU_DMAIEN2_GPT12IE_Pos
Definition: tle987x.h:8803
#define SCU_DMAIEN1_CH5IE_Pos
Definition: tle987x.h:8790
#define SCU_DMAIEN1_CH2IE_Pos
Definition: tle987x.h:8796
#define SCU_DMAIEN1_CH6IE_Msk
Definition: tle987x.h:8789
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos
Definition: tle987x.h:7895
#define SCU_DMAIRC1CLR_CH7C_Msk
Definition: tle987x.h:8836
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk
Definition: tle987x.h:7923
#define SCU_DMAIRC1CLR_CH3C_Msk
Definition: tle987x.h:8844
#define SCU_DMAIRC1CLR_CH2C_Msk
Definition: tle987x.h:8846
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos
Definition: tle987x.h:8873
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk
Definition: tle987x.h:7914
#define SCU_DMAIEN1_CH3IE_Msk
Definition: tle987x.h:8795
#define SCU_DMAIRC1CLR_CH5C_Msk
Definition: tle987x.h:8840
#define SCU_DMAIEN1_CH4IE_Pos
Definition: tle987x.h:8792
#define SCU_DMAIEN1_CH7IE_Msk
Definition: tle987x.h:8787
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk
Definition: tle987x.h:7899
#define SCU_DMAIRC1CLR_CH8C_Msk
Definition: tle987x.h:8834
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk
Definition: tle987x.h:8874
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos
Definition: tle987x.h:7898
#define SCU_DMAIEN2_SDADCIE_Pos
Definition: tle987x.h:8801
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos
Definition: tle987x.h:7913
#define SCU_DMAIRC2CLR_GPT12C_Msk
Definition: tle987x.h:8868
#define SCU_DMAIEN2_TRSEQ1RDYIE_Msk
Definition: tle987x.h:8812
#define SCU_DMAIEN1_CH4IE_Msk
Definition: tle987x.h:8793
#define SCU_DMAIEN2_SSCRXIE_Msk
Definition: tle987x.h:8806
#define SCU_DMAIRC1CLR_CH6C_Pos
Definition: tle987x.h:8837
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos
Definition: tle987x.h:7922
#define SCU_DMAIEN2_GPT12IE_Msk
Definition: tle987x.h:8804
#define SCU_DMAIEN1_CH5IE_Msk
Definition: tle987x.h:8791
#define SCU_DMAIRC2CLR_SSC2C_Msk
Definition: tle987x.h:8870
#define SCU_DMAIEN2_SSCRXIE_Pos
Definition: tle987x.h:8805
#define SCU_DMAIRC1CLR_CH6C_Msk
Definition: tle987x.h:8838
#define SCU_DMAIRC2CLR_GPT12C_Pos
Definition: tle987x.h:8867
#define SCU_DMAIEN1_CH6IE_Pos
Definition: tle987x.h:8788
#define SCU_DMAIEN1_CH8IE_Pos
Definition: tle987x.h:8784
#define SCU_DMAIEN1_CH2IE_Msk
Definition: tle987x.h:8797
#define SCU_DMAIEN2_TRSEQ2RDYIE_Msk
Definition: tle987x.h:8810
#define SCU_DMAIEN2_TRSEQ1RDYIE_Pos
Definition: tle987x.h:8811
#define SCU_DMAIEN1_CH1IE_Pos
Definition: tle987x.h:8798
#define SCU_DMAIRC1CLR_CH4C_Msk
Definition: tle987x.h:8842
#define SCU_DMAIRC2CLR_SSC2C_Pos
Definition: tle987x.h:8869
#define SCU_DMAIRC2CLR_SDADCC_Msk
Definition: tle987x.h:8866
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk
Definition: tle987x.h:8876
#define SCU_DMAIEN2_SSCTXIE_Msk
Definition: tle987x.h:8808
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk
Definition: tle987x.h:7893
#define SCU_DMAIRC1CLR_CH3C_Pos
Definition: tle987x.h:8843
SFR low level access library.
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:322
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:347
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
This structure lists the DMA transfer memory locations.
Definition: dma.h:243
uint32 Dst_End_Ptr
Definition: dma.h:245
uint32 Src_End_Ptr
Definition: dma.h:244
uint32 reserved
Definition: dma.h:247
TControl Control
Definition: dma.h:246
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:132
uint8_t uint8
8 bit unsigned value
Definition: types.h:137
uint32_t uint32
32 bit unsigned value
Definition: types.h:139
This structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:222
uint32 Dst_Inc
Bit[31..30].
Definition: dma.h:235
uint32 Cycle_Ctrl
Bit[2..0].
Definition: dma.h:226
uint32 R_Power
Bit[17..14].
Definition: dma.h:229
uint32 Src_Prot_Ctrl
Bit[20..18].
Definition: dma.h:230
uint32 Dst_Size
Bit[29..28].
Definition: dma.h:234
uint32 Next_UseBurst
Bit[3].
Definition: dma.h:227
uint32 Src_Inc
Bit[27..26].
Definition: dma.h:233
uint32 Dst_Prot_Ctrl
Bit[23..21].
Definition: dma.h:231
uint32 N_Minus_1
Bit[13..4].
Definition: dma.h:228
uint32 reg
Definition: dma.h:223
uint32 Src_Size
Bit[25..24].
Definition: dma.h:232