119 #define __CM3_REV 0x0000U
120 #define __NVIC_PRIO_BITS 4
121 #define __Vendor_SysTickConfig 0
122 #define __MPU_PRESENT 0
123 #define __FPU_PRESENT 0
128 #include "core_cm3.h"
141 #ifdef UNIT_TESTING_LV2
143 #define __IM volatile
223 __IOM uint32_t TRIG_SEL : 3;
281 __IOM uint32_t ch0 : 8;
282 __IOM uint32_t ch1 : 8;
283 __IOM uint32_t ch2 : 8;
284 __IOM uint32_t ch3 : 8;
294 __IOM uint32_t ch4 : 8;
295 __IOM uint32_t ch5 : 8;
296 __IOM uint32_t ch6 : 8;
297 __IOM uint32_t ch7 : 8;
588 __IOM uint32_t SEL : 1;
590 __IOM uint32_t EN : 1;
926 __IOM uint32_t Ch0_EN : 1;
927 __IOM uint32_t Ch1_EN : 1;
928 __IOM uint32_t Ch2_EN : 1;
929 __IOM uint32_t Ch3_EN : 1;
930 __IOM uint32_t Ch4_EN : 1;
931 __IOM uint32_t Ch5_EN : 1;
941 __IOM uint32_t CH0 : 8;
942 __IOM uint32_t CH1 : 8;
943 __IOM uint32_t CH2 : 8;
944 __IOM uint32_t CH3 : 8;
955 __IOM uint32_t CH4 : 8;
956 __IOM uint32_t CH5 : 8;
967 __IM uint32_t CH7 : 8;
979 __IOM uint32_t CH0 : 8;
980 __IOM uint32_t CH1 : 8;
981 __IOM uint32_t CH2 : 8;
982 __IOM uint32_t CH3 : 8;
992 __IOM uint32_t CH4 : 8;
993 __IOM uint32_t CH5 : 8;
1003 __IM uint32_t CH6 : 8;
1004 __IM uint32_t CH7 : 8;
1005 __IM uint32_t CH8 : 8;
1006 __IM uint32_t CH9 : 8;
1561 __IOM uint16_t CCS : 16;
1572 __IOM uint16_t CCS : 16;
1583 __IOM uint16_t CCS : 16;
1654 __IM uint16_t CCV : 16;
1665 __IM uint16_t CCV : 16;
1676 __IM uint16_t CCV : 16;
2079 __IOM uint32_t Int_GPT1 : 1;
2080 __IOM uint32_t Int_GPT2 : 1;
2081 __IOM uint32_t Int_ADC2 : 1;
2082 __IOM uint32_t Int_ADC1 : 1;
2083 __IOM uint32_t Int_CCU6SR0 : 1;
2084 __IOM uint32_t Int_CCU6SR1 : 1;
2085 __IOM uint32_t Int_CCU6SR2 : 1;
2086 __IOM uint32_t Int_CCU6SR3 : 1;
2087 __IOM uint32_t Int_SSC1 : 1;
2088 __IOM uint32_t Int_SSC2 : 1;
2089 __IOM uint32_t Int_UART1 : 1;
2090 __IOM uint32_t Int_UART2 : 1;
2091 __IOM uint32_t Int_EXINT0 : 1;
2092 __IOM uint32_t Int_EXINT1 : 1;
2093 __IOM uint32_t Int_BDRV : 1;
2094 __IOM uint32_t Int_DMA : 1;
2105 __IOM uint32_t Int_GPT1 : 1;
2106 __IOM uint32_t Int_GPT2 : 1;
2107 __IOM uint32_t Int_ADC2 : 1;
2108 __IOM uint32_t Int_ADC1 : 1;
2109 __IOM uint32_t Int_CCU6SR0 : 1;
2110 __IOM uint32_t Int_CCU6SR1 : 1;
2111 __IOM uint32_t Int_CCU6SR2 : 1;
2112 __IOM uint32_t Int_CCU6SR3 : 1;
2113 __IOM uint32_t Int_SSC1 : 1;
2114 __IOM uint32_t Int_SSC2 : 1;
2115 __IOM uint32_t Int_UART1 : 1;
2116 __IOM uint32_t Int_UART2 : 1;
2117 __IOM uint32_t Int_EXINT0 : 1;
2118 __IOM uint32_t Int_EXINT1 : 1;
2119 __IOM uint32_t Int_BDRV : 1;
2120 __IOM uint32_t Int_DMA : 1;
2131 __IOM uint32_t Int_GPT1 : 1;
2132 __IOM uint32_t Int_GPT2 : 1;
2133 __IOM uint32_t Int_ADC2 : 1;
2134 __IOM uint32_t Int_ADC1 : 1;
2135 __IOM uint32_t Int_CCU6SR0 : 1;
2136 __IOM uint32_t Int_CCU6SR1 : 1;
2137 __IOM uint32_t Int_CCU6SR2 : 1;
2138 __IOM uint32_t Int_CCU6SR3 : 1;
2139 __IOM uint32_t Int_SSC1 : 1;
2140 __IOM uint32_t Int_SSC2 : 1;
2141 __IOM uint32_t Int_UART1 : 1;
2142 __IOM uint32_t Int_UART2 : 1;
2143 __IOM uint32_t Int_EXINT0 : 1;
2144 __IOM uint32_t Int_EXINT1 : 1;
2145 __IOM uint32_t Int_BDRV : 1;
2146 __IOM uint32_t Int_DMA : 1;
2467 __IOM uint32_t ADDRESS : 32;
2505 __I uint32_t RESERVED0[3];
2579 } ALT_CTRL_BASE_PTR;
2617 } CHNL_USEBURST_SET;
2627 } CHNL_USEBURST_CLR;
2642 } CHNL_REQ_MASK_SET;
2652 } CHNL_REQ_MASK_CLR;
2715 } CHNL_PRIORITY_SET;
2725 } CHNL_PRIORITY_CLR;
3144 __I uint32_t RESERVED0[13];
3300 __IOM uint8_t M03 : 4;
3301 __IOM uint8_t E01 : 2;
3312 __IOM uint8_t M03 : 4;
3314 } CNF_CYC_SAMPLE_DEL;
3502 } WAKE_CONF_GPIO0_RISE;
3517 } WAKE_CONF_GPIO0_FALL;
3532 } WAKE_CONF_GPIO0_CYC;
3547 } WAKE_CONF_GPIO1_RISE;
3562 } WAKE_CONF_GPIO1_FALL;
3577 } WAKE_CONF_GPIO1_CYC;
3589 } SystemStartConfig;
3627 __IOM uint8_t P0 : 1;
3628 __IOM uint8_t P1 : 1;
3629 __IOM uint8_t P2 : 1;
3630 __IOM uint8_t P3 : 1;
3631 __IOM uint8_t P4 : 1;
3642 __IOM uint8_t P0 : 1;
3643 __IOM uint8_t P1 : 1;
3644 __IOM uint8_t P2 : 1;
3645 __IOM uint8_t P3 : 1;
3646 __IOM uint8_t P4 : 1;
3657 __IOM uint8_t P0 : 1;
3658 __IOM uint8_t P1 : 1;
3659 __IOM uint8_t P2 : 1;
3660 __IOM uint8_t P3 : 1;
3661 __IOM uint8_t P4 : 1;
3688 __IOM uint8_t P0 : 1;
3690 __IOM uint8_t P2 : 1;
3691 __IOM uint8_t P3 : 1;
3692 __IOM uint8_t P4 : 1;
3704 __IOM uint8_t P0 : 1;
3705 __IOM uint8_t P1 : 1;
3706 __IOM uint8_t P2 : 1;
3707 __IOM uint8_t P3 : 1;
3708 __IOM uint8_t P4 : 1;
3719 __IOM uint8_t P0 : 1;
3720 __IOM uint8_t P1 : 1;
3721 __IOM uint8_t P2 : 1;
3722 __IOM uint8_t P3 : 1;
3723 __IOM uint8_t P4 : 1;
3734 __IOM uint8_t P0 : 1;
3735 __IOM uint8_t P1 : 1;
3736 __IOM uint8_t P2 : 1;
3737 __IOM uint8_t P3 : 1;
3738 __IOM uint8_t P4 : 1;
3749 __IOM uint8_t P0 : 1;
3750 __IOM uint8_t P1 : 1;
3751 __IOM uint8_t P2 : 1;
3752 __IOM uint8_t P3 : 1;
3753 __IOM uint8_t P4 : 1;
3764 __IOM uint8_t P0 : 1;
3766 __IOM uint8_t P2 : 1;
3767 __IOM uint8_t P3 : 1;
3768 __IOM uint8_t P4 : 1;
3769 __IOM uint8_t P5 : 1;
3780 __IOM uint8_t P0 : 1;
3782 __IOM uint8_t P2 : 1;
3783 __IOM uint8_t P3 : 1;
3784 __IOM uint8_t P4 : 1;
3785 __IOM uint8_t P5 : 1;
3796 __IOM uint8_t P0 : 1;
3797 __IOM uint8_t P1 : 1;
3798 __IOM uint8_t P2 : 1;
3799 __IOM uint8_t P3 : 1;
3800 __IOM uint8_t P4 : 1;
3811 __IOM uint8_t P0 : 1;
3812 __IOM uint8_t P1 : 1;
3813 __IOM uint8_t P2 : 1;
3814 __IOM uint8_t P3 : 1;
3815 __IOM uint8_t P4 : 1;
3826 __IOM uint8_t P0 : 1;
3827 __IOM uint8_t P1 : 1;
3828 __IOM uint8_t P2 : 1;
3829 __IOM uint8_t P3 : 1;
3830 __IOM uint8_t P4 : 1;
3841 __IOM uint8_t P0 : 1;
3842 __IOM uint8_t P1 : 1;
3843 __IOM uint8_t P2 : 1;
3844 __IOM uint8_t P3 : 1;
3845 __IOM uint8_t P4 : 1;
3856 __IOM uint8_t P0 : 1;
3857 __IOM uint8_t P1 : 1;
3858 __IOM uint8_t P2 : 1;
3859 __IOM uint8_t P3 : 1;
3860 __IOM uint8_t P4 : 1;
3872 __IOM uint8_t P0 : 1;
3873 __IOM uint8_t P1 : 1;
3875 __IOM uint8_t P4 : 1;
3950 __IM uint8_t EIR : 1;
3951 __IM uint8_t TIR : 1;
3952 __IM uint8_t RIR : 1;
4367 __IM uint8_t WDT : 8;
4403 __IOM uint8_t BR_VALUE : 8;
4430 __IOM uint8_t R : 1;
4431 __IOM uint8_t BRPRE : 3;
4443 __IOM uint8_t FD_SEL : 5;
4444 __IOM uint8_t BR_VALUE : 3;
4455 __IOM uint8_t BR_VALUE : 8;
4755 __IOM uint8_t PDM0 : 3;
4757 __IOM uint8_t PDM1 : 3;
4768 __IOM uint8_t PDM2 : 3;
4770 __IOM uint8_t PDM3 : 3;
4781 __IOM uint8_t PDM4 : 3;
4960 __OM uint8_t EIRC : 1;
4961 __OM uint8_t TIRC : 1;
4962 __OM uint8_t RIRC : 1;
5223 } SYS_SUPPLY_IRQ_STS;
5240 } SYS_SUPPLY_IRQ_CTRL;
5266 } SYS_SUPPLY_IRQ_CLR;
5795 __IOM uint8_t RC2 : 8;
5892 __IOM uint32_t LO : 8;
5893 __IOM uint32_t HI : 8;
6013 #define ADC1_BASE 0x40004000UL
6014 #define ADC2_BASE 0x4801C000UL
6015 #define ADC34_BASE 0x40008000UL
6016 #define BDRV_BASE 0x40034000UL
6017 #define CCU6_BASE 0x4000C000UL
6018 #define CPU_BASE 0xE000E000UL
6019 #define CSA_BASE 0x48018000UL
6020 #define DMA_BASE 0x50014000UL
6021 #define GPT12E_BASE 0x40010000UL
6022 #define LIN_BASE 0x4801E000UL
6023 #define MF_BASE 0x48018000UL
6024 #define MON_BASE 0x50004000UL
6025 #define PMU_BASE 0x50004000UL
6026 #define PORT_BASE 0x48028000UL
6027 #define SCU_BASE 0x50005000UL
6028 #define SCUPM_BASE 0x50006000UL
6029 #define SSC1_BASE 0x48024000UL
6030 #define SSC2_BASE 0x48026000UL
6031 #define TIMER2_BASE 0x48004000UL
6032 #define TIMER21_BASE 0x48005000UL
6033 #define TIMER3_BASE 0x48006000UL
6034 #define UART1_BASE 0x48020000UL
6035 #define UART2_BASE 0x48022000UL
6056 #ifndef UNIT_TESTING_LV2
6057 #define ADC1 ((ADC1_Type*) ADC1_BASE)
6058 #define ADC2 ((ADC2_Type*) ADC2_BASE)
6059 #define ADC34 ((ADC34_Type*) ADC34_BASE)
6060 #define BDRV ((BDRV_Type*) BDRV_BASE)
6061 #define CCU6 ((CCU6_Type*) CCU6_BASE)
6062 #define CSA ((CSA_Type*) CSA_BASE)
6063 #define CPU ((CPU_Type*) CPU_BASE)
6064 #define DMA ((DMA_Type*) DMA_BASE)
6065 #define GPT12E ((GPT12E_Type*) GPT12E_BASE)
6066 #define LIN ((LIN_Type*) LIN_BASE)
6067 #define MF ((MF_Type*) MF_BASE)
6068 #define MON ((MON_Type*) MON_BASE)
6069 #define PMU ((PMU_Type*) PMU_BASE)
6070 #define PORT ((PORT_Type*) PORT_BASE)
6071 #define SCU ((SCU_Type*) SCU_BASE)
6072 #define SCUPM ((SCUPM_Type*) SCUPM_BASE)
6073 #define SSC1 ((SSC1_Type*) SSC1_BASE)
6074 #define SSC2 ((SSC2_Type*) SSC2_BASE)
6075 #define TIMER2 ((TIMER2x_Type*) TIMER2_BASE)
6076 #define TIMER21 ((TIMER2x_Type*) TIMER21_BASE)
6077 #define TIMER3 ((TIMER3_Type*) TIMER3_BASE)
6078 #define UART1 ((UART_Type*) UART1_BASE)
6079 #define UART2 ((UART_Type*) UART2_BASE)
6127 #define ADC1_CHx_EIM_TRIG_SEL_Pos (16UL)
6128 #define ADC1_CHx_EIM_TRIG_SEL_Msk (0x70000UL)
6129 #define ADC1_CHx_EIM_REP_Pos (4UL)
6130 #define ADC1_CHx_EIM_REP_Msk (0x70UL)
6131 #define ADC1_CHx_EIM_CHx_Pos (0UL)
6132 #define ADC1_CHx_EIM_CHx_Msk (0x7UL)
6134 #define ADC1_CHx_ESM_TRIG_SEL_Pos (16UL)
6135 #define ADC1_CHx_ESM_TRIG_SEL_Msk (0x70000UL)
6136 #define ADC1_CHx_ESM_ESM_0_Pos (0UL)
6137 #define ADC1_CHx_ESM_ESM_0_Msk (0xffUL)
6139 #define ADC1_CTRL_STS_IN_MUX_SEL_Pos (4UL)
6140 #define ADC1_CTRL_STS_IN_MUX_SEL_Msk (0x70UL)
6141 #define ADC1_CTRL_STS_EOC_Pos (3UL)
6142 #define ADC1_CTRL_STS_EOC_Msk (0x8UL)
6143 #define ADC1_CTRL_STS_SOC_Pos (2UL)
6144 #define ADC1_CTRL_STS_SOC_Msk (0x4UL)
6145 #define ADC1_CTRL_STS_PD_N_Pos (0UL)
6146 #define ADC1_CTRL_STS_PD_N_Msk (0x1UL)
6148 #define ADC1_DWSEL_ch7_Pos (7UL)
6149 #define ADC1_DWSEL_ch7_Msk (0x80UL)
6150 #define ADC1_DWSEL_ch6_Pos (6UL)
6151 #define ADC1_DWSEL_ch6_Msk (0x40UL)
6152 #define ADC1_DWSEL_ch5_Pos (5UL)
6153 #define ADC1_DWSEL_ch5_Msk (0x20UL)
6154 #define ADC1_DWSEL_ch4_Pos (4UL)
6155 #define ADC1_DWSEL_ch4_Msk (0x10UL)
6156 #define ADC1_DWSEL_ch3_Pos (3UL)
6157 #define ADC1_DWSEL_ch3_Msk (0x8UL)
6158 #define ADC1_DWSEL_ch2_Pos (2UL)
6159 #define ADC1_DWSEL_ch2_Msk (0x4UL)
6160 #define ADC1_DWSEL_ch1_Pos (1UL)
6161 #define ADC1_DWSEL_ch1_Msk (0x2UL)
6162 #define ADC1_DWSEL_ch0_Pos (0UL)
6163 #define ADC1_DWSEL_ch0_Msk (0x1UL)
6165 #define ADC1_GLOBCTR_ANON_Pos (8UL)
6166 #define ADC1_GLOBCTR_ANON_Msk (0x300UL)
6167 #define ADC1_GLOBCTR_DIVA_Pos (0UL)
6168 #define ADC1_GLOBCTR_DIVA_Msk (0x3fUL)
6170 #define ADC1_GLOBSTR_ANON_ST_Pos (8UL)
6171 #define ADC1_GLOBSTR_ANON_ST_Msk (0x300UL)
6172 #define ADC1_GLOBSTR_CHNR_Pos (3UL)
6173 #define ADC1_GLOBSTR_CHNR_Msk (0x38UL)
6174 #define ADC1_GLOBSTR_SAMPLE_Pos (1UL)
6175 #define ADC1_GLOBSTR_SAMPLE_Msk (0x2UL)
6176 #define ADC1_GLOBSTR_BUSY_Pos (0UL)
6177 #define ADC1_GLOBSTR_BUSY_Msk (0x1UL)
6179 #define ADC1_ICLR_ESM_ICLR_Pos (9UL)
6180 #define ADC1_ICLR_ESM_ICLR_Msk (0x200UL)
6181 #define ADC1_ICLR_EIM_ICLR_Pos (8UL)
6182 #define ADC1_ICLR_EIM_ICLR_Msk (0x100UL)
6183 #define ADC1_ICLR_CH7_ICLR_Pos (7UL)
6184 #define ADC1_ICLR_CH7_ICLR_Msk (0x80UL)
6185 #define ADC1_ICLR_CH6_ICLR_Pos (6UL)
6186 #define ADC1_ICLR_CH6_ICLR_Msk (0x40UL)
6187 #define ADC1_ICLR_CH5_ICLR_Pos (5UL)
6188 #define ADC1_ICLR_CH5_ICLR_Msk (0x20UL)
6189 #define ADC1_ICLR_CH4_ICLR_Pos (4UL)
6190 #define ADC1_ICLR_CH4_ICLR_Msk (0x10UL)
6191 #define ADC1_ICLR_CH3_ICLR_Pos (3UL)
6192 #define ADC1_ICLR_CH3_ICLR_Msk (0x8UL)
6193 #define ADC1_ICLR_CH2_ICLR_Pos (2UL)
6194 #define ADC1_ICLR_CH2_ICLR_Msk (0x4UL)
6195 #define ADC1_ICLR_CH1_ICLR_Pos (1UL)
6196 #define ADC1_ICLR_CH1_ICLR_Msk (0x2UL)
6197 #define ADC1_ICLR_CH0_ICLR_Pos (0UL)
6198 #define ADC1_ICLR_CH0_ICLR_Msk (0x1UL)
6200 #define ADC1_IE_ESM_IE_Pos (9UL)
6201 #define ADC1_IE_ESM_IE_Msk (0x200UL)
6202 #define ADC1_IE_EIM_IE_Pos (8UL)
6203 #define ADC1_IE_EIM_IE_Msk (0x100UL)
6204 #define ADC1_IE_CH7_IE_Pos (7UL)
6205 #define ADC1_IE_CH7_IE_Msk (0x80UL)
6206 #define ADC1_IE_CH6_IE_Pos (6UL)
6207 #define ADC1_IE_CH6_IE_Msk (0x40UL)
6208 #define ADC1_IE_CH5_IE_Pos (5UL)
6209 #define ADC1_IE_CH5_IE_Msk (0x20UL)
6210 #define ADC1_IE_CH4_IE_Pos (4UL)
6211 #define ADC1_IE_CH4_IE_Msk (0x10UL)
6212 #define ADC1_IE_CH3_IE_Pos (3UL)
6213 #define ADC1_IE_CH3_IE_Msk (0x8UL)
6214 #define ADC1_IE_CH2_IE_Pos (2UL)
6215 #define ADC1_IE_CH2_IE_Msk (0x4UL)
6216 #define ADC1_IE_CH1_IE_Pos (1UL)
6217 #define ADC1_IE_CH1_IE_Msk (0x2UL)
6218 #define ADC1_IE_CH0_IE_Pos (0UL)
6219 #define ADC1_IE_CH0_IE_Msk (0x1UL)
6221 #define ADC1_IS_ESM_STS_Pos (9UL)
6222 #define ADC1_IS_ESM_STS_Msk (0x200UL)
6223 #define ADC1_IS_EIM_STS_Pos (8UL)
6224 #define ADC1_IS_EIM_STS_Msk (0x100UL)
6225 #define ADC1_IS_CH7_STS_Pos (7UL)
6226 #define ADC1_IS_CH7_STS_Msk (0x80UL)
6227 #define ADC1_IS_CH6_STS_Pos (6UL)
6228 #define ADC1_IS_CH6_STS_Msk (0x40UL)
6229 #define ADC1_IS_CH5_STS_Pos (5UL)
6230 #define ADC1_IS_CH5_STS_Msk (0x20UL)
6231 #define ADC1_IS_CH4_STS_Pos (4UL)
6232 #define ADC1_IS_CH4_STS_Msk (0x10UL)
6233 #define ADC1_IS_CH3_STS_Pos (3UL)
6234 #define ADC1_IS_CH3_STS_Msk (0x8UL)
6235 #define ADC1_IS_CH2_STS_Pos (2UL)
6236 #define ADC1_IS_CH2_STS_Msk (0x4UL)
6237 #define ADC1_IS_CH1_STS_Pos (1UL)
6238 #define ADC1_IS_CH1_STS_Msk (0x2UL)
6239 #define ADC1_IS_CH0_STS_Pos (0UL)
6240 #define ADC1_IS_CH0_STS_Msk (0x1UL)
6242 #define ADC1_RES_OUT0_OF0_Pos (18UL)
6243 #define ADC1_RES_OUT0_OF0_Msk (0x40000UL)
6244 #define ADC1_RES_OUT0_VF0_Pos (17UL)
6245 #define ADC1_RES_OUT0_VF0_Msk (0x20000UL)
6246 #define ADC1_RES_OUT0_WFR0_Pos (16UL)
6247 #define ADC1_RES_OUT0_WFR0_Msk (0x10000UL)
6248 #define ADC1_RES_OUT0_OUT_CH0_Pos (0UL)
6249 #define ADC1_RES_OUT0_OUT_CH0_Msk (0xfffUL)
6251 #define ADC1_RES_OUT1_OF1_Pos (18UL)
6252 #define ADC1_RES_OUT1_OF1_Msk (0x40000UL)
6253 #define ADC1_RES_OUT1_VF1_Pos (17UL)
6254 #define ADC1_RES_OUT1_VF1_Msk (0x20000UL)
6255 #define ADC1_RES_OUT1_WFR1_Pos (16UL)
6256 #define ADC1_RES_OUT1_WFR1_Msk (0x10000UL)
6257 #define ADC1_RES_OUT1_OUT_CH1_Pos (0UL)
6258 #define ADC1_RES_OUT1_OUT_CH1_Msk (0xfffUL)
6260 #define ADC1_RES_OUT2_OF2_Pos (18UL)
6261 #define ADC1_RES_OUT2_OF2_Msk (0x40000UL)
6262 #define ADC1_RES_OUT2_VF2_Pos (17UL)
6263 #define ADC1_RES_OUT2_VF2_Msk (0x20000UL)
6264 #define ADC1_RES_OUT2_WFR2_Pos (16UL)
6265 #define ADC1_RES_OUT2_WFR2_Msk (0x10000UL)
6266 #define ADC1_RES_OUT2_OUT_CH2_Pos (0UL)
6267 #define ADC1_RES_OUT2_OUT_CH2_Msk (0xfffUL)
6269 #define ADC1_RES_OUT3_OF3_Pos (18UL)
6270 #define ADC1_RES_OUT3_OF3_Msk (0x40000UL)
6271 #define ADC1_RES_OUT3_VF3_Pos (17UL)
6272 #define ADC1_RES_OUT3_VF3_Msk (0x20000UL)
6273 #define ADC1_RES_OUT3_WFR3_Pos (16UL)
6274 #define ADC1_RES_OUT3_WFR3_Msk (0x10000UL)
6275 #define ADC1_RES_OUT3_OUT_CH3_Pos (0UL)
6276 #define ADC1_RES_OUT3_OUT_CH3_Msk (0xfffUL)
6278 #define ADC1_RES_OUT4_OF4_Pos (18UL)
6279 #define ADC1_RES_OUT4_OF4_Msk (0x40000UL)
6280 #define ADC1_RES_OUT4_VF4_Pos (17UL)
6281 #define ADC1_RES_OUT4_VF4_Msk (0x20000UL)
6282 #define ADC1_RES_OUT4_WFR4_Pos (16UL)
6283 #define ADC1_RES_OUT4_WFR4_Msk (0x10000UL)
6284 #define ADC1_RES_OUT4_OUT_CH4_Pos (0UL)
6285 #define ADC1_RES_OUT4_OUT_CH4_Msk (0xfffUL)
6287 #define ADC1_RES_OUT5_OF5_Pos (18UL)
6288 #define ADC1_RES_OUT5_OF5_Msk (0x40000UL)
6289 #define ADC1_RES_OUT5_VF5_Pos (17UL)
6290 #define ADC1_RES_OUT5_VF5_Msk (0x20000UL)
6291 #define ADC1_RES_OUT5_WFR5_Pos (16UL)
6292 #define ADC1_RES_OUT5_WFR5_Msk (0x10000UL)
6293 #define ADC1_RES_OUT5_OUT_CH5_Pos (0UL)
6294 #define ADC1_RES_OUT5_OUT_CH5_Msk (0xfffUL)
6296 #define ADC1_RES_OUT6_OF6_Pos (18UL)
6297 #define ADC1_RES_OUT6_OF6_Msk (0x40000UL)
6298 #define ADC1_RES_OUT6_VF6_Pos (17UL)
6299 #define ADC1_RES_OUT6_VF6_Msk (0x20000UL)
6300 #define ADC1_RES_OUT6_WFR6_Pos (16UL)
6301 #define ADC1_RES_OUT6_WFR6_Msk (0x10000UL)
6302 #define ADC1_RES_OUT6_OUT_CH6_Pos (0UL)
6303 #define ADC1_RES_OUT6_OUT_CH6_Msk (0xfffUL)
6305 #define ADC1_RES_OUT7_OF7_Pos (18UL)
6306 #define ADC1_RES_OUT7_OF7_Msk (0x40000UL)
6307 #define ADC1_RES_OUT7_VF7_Pos (17UL)
6308 #define ADC1_RES_OUT7_VF7_Msk (0x20000UL)
6309 #define ADC1_RES_OUT7_WFR7_Pos (16UL)
6310 #define ADC1_RES_OUT7_WFR7_Msk (0x10000UL)
6311 #define ADC1_RES_OUT7_OUT_CH7_Pos (0UL)
6312 #define ADC1_RES_OUT7_OUT_CH7_Msk (0xfffUL)
6314 #define ADC1_RES_OUT_EIM_OF8_Pos (18UL)
6315 #define ADC1_RES_OUT_EIM_OF8_Msk (0x40000UL)
6316 #define ADC1_RES_OUT_EIM_VF8_Pos (17UL)
6317 #define ADC1_RES_OUT_EIM_VF8_Msk (0x20000UL)
6318 #define ADC1_RES_OUT_EIM_WFR8_Pos (16UL)
6319 #define ADC1_RES_OUT_EIM_WFR8_Msk (0x10000UL)
6320 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos (0UL)
6321 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk (0xfffUL)
6323 #define ADC1_SQ1_4_SQ4_Pos (24UL)
6324 #define ADC1_SQ1_4_SQ4_Msk (0xff000000UL)
6325 #define ADC1_SQ1_4_SQ3_Pos (16UL)
6326 #define ADC1_SQ1_4_SQ3_Msk (0xff0000UL)
6327 #define ADC1_SQ1_4_SQ2_Pos (8UL)
6328 #define ADC1_SQ1_4_SQ2_Msk (0xff00UL)
6329 #define ADC1_SQ1_4_SQ1_Pos (0UL)
6330 #define ADC1_SQ1_4_SQ1_Msk (0xffUL)
6332 #define ADC1_SQ5_8_SQ8_Pos (24UL)
6333 #define ADC1_SQ5_8_SQ8_Msk (0xff000000UL)
6334 #define ADC1_SQ5_8_SQ7_Pos (16UL)
6335 #define ADC1_SQ5_8_SQ7_Msk (0xff0000UL)
6336 #define ADC1_SQ5_8_SQ6_Pos (8UL)
6337 #define ADC1_SQ5_8_SQ6_Msk (0xff00UL)
6338 #define ADC1_SQ5_8_SQ5_Pos (0UL)
6339 #define ADC1_SQ5_8_SQ5_Msk (0xffUL)
6341 #define ADC1_SQ_FB_CHx_Pos (16UL)
6342 #define ADC1_SQ_FB_CHx_Msk (0x70000UL)
6343 #define ADC1_SQ_FB_SQx_Pos (11UL)
6344 #define ADC1_SQ_FB_SQx_Msk (0x3800UL)
6345 #define ADC1_SQ_FB_ESM_ACTIVE_Pos (10UL)
6346 #define ADC1_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6347 #define ADC1_SQ_FB_EIM_ACTIVE_Pos (9UL)
6348 #define ADC1_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6349 #define ADC1_SQ_FB_SQ_RUN_Pos (8UL)
6350 #define ADC1_SQ_FB_SQ_RUN_Msk (0x100UL)
6352 #define ADC1_STC_0_3_ch3_Pos (24UL)
6353 #define ADC1_STC_0_3_ch3_Msk (0xff000000UL)
6354 #define ADC1_STC_0_3_ch2_Pos (16UL)
6355 #define ADC1_STC_0_3_ch2_Msk (0xff0000UL)
6356 #define ADC1_STC_0_3_ch1_Pos (8UL)
6357 #define ADC1_STC_0_3_ch1_Msk (0xff00UL)
6358 #define ADC1_STC_0_3_ch0_Pos (0UL)
6359 #define ADC1_STC_0_3_ch0_Msk (0xffUL)
6361 #define ADC1_STC_4_7_ch7_Pos (24UL)
6362 #define ADC1_STC_4_7_ch7_Msk (0xff000000UL)
6363 #define ADC1_STC_4_7_ch6_Pos (16UL)
6364 #define ADC1_STC_4_7_ch6_Msk (0xff0000UL)
6365 #define ADC1_STC_4_7_ch5_Pos (8UL)
6366 #define ADC1_STC_4_7_ch5_Msk (0xff00UL)
6367 #define ADC1_STC_4_7_ch4_Pos (0UL)
6368 #define ADC1_STC_4_7_ch4_Msk (0xffUL)
6376 #define ADC2_CAL_CH0_1_GAIN_CH1_Pos (24UL)
6377 #define ADC2_CAL_CH0_1_GAIN_CH1_Msk (0xff000000UL)
6378 #define ADC2_CAL_CH0_1_OFFS_CH1_Pos (16UL)
6379 #define ADC2_CAL_CH0_1_OFFS_CH1_Msk (0xff0000UL)
6380 #define ADC2_CAL_CH0_1_GAIN_CH0_Pos (8UL)
6381 #define ADC2_CAL_CH0_1_GAIN_CH0_Msk (0xff00UL)
6382 #define ADC2_CAL_CH0_1_OFFS_CH0_Pos (0UL)
6383 #define ADC2_CAL_CH0_1_OFFS_CH0_Msk (0xffUL)
6385 #define ADC2_CAL_CH2_3_GAIN_CH3_Pos (24UL)
6386 #define ADC2_CAL_CH2_3_GAIN_CH3_Msk (0xff000000UL)
6387 #define ADC2_CAL_CH2_3_OFFS_CH3_Pos (16UL)
6388 #define ADC2_CAL_CH2_3_OFFS_CH3_Msk (0xff0000UL)
6389 #define ADC2_CAL_CH2_3_GAIN_CH2_Pos (8UL)
6390 #define ADC2_CAL_CH2_3_GAIN_CH2_Msk (0xff00UL)
6391 #define ADC2_CAL_CH2_3_OFFS_CH2_Pos (0UL)
6392 #define ADC2_CAL_CH2_3_OFFS_CH2_Msk (0xffUL)
6394 #define ADC2_CAL_CH4_5_GAIN_CH5_Pos (24UL)
6395 #define ADC2_CAL_CH4_5_GAIN_CH5_Msk (0xff000000UL)
6396 #define ADC2_CAL_CH4_5_OFFS_CH5_Pos (16UL)
6397 #define ADC2_CAL_CH4_5_OFFS_CH5_Msk (0xff0000UL)
6398 #define ADC2_CAL_CH4_5_GAIN_CH4_Pos (8UL)
6399 #define ADC2_CAL_CH4_5_GAIN_CH4_Msk (0xff00UL)
6400 #define ADC2_CAL_CH4_5_OFFS_CH4_Pos (0UL)
6401 #define ADC2_CAL_CH4_5_OFFS_CH4_Msk (0xffUL)
6403 #define ADC2_CAL_CH6_7_GAIN_CH7_Pos (24UL)
6404 #define ADC2_CAL_CH6_7_GAIN_CH7_Msk (0xff000000UL)
6405 #define ADC2_CAL_CH6_7_OFFS_CH7_Pos (16UL)
6406 #define ADC2_CAL_CH6_7_OFFS_CH7_Msk (0xff0000UL)
6407 #define ADC2_CAL_CH6_7_GAIN_CH6_Pos (8UL)
6408 #define ADC2_CAL_CH6_7_GAIN_CH6_Msk (0xff00UL)
6409 #define ADC2_CAL_CH6_7_OFFS_CH6_Pos (0UL)
6410 #define ADC2_CAL_CH6_7_OFFS_CH6_Msk (0xffUL)
6412 #define ADC2_CAL_CH8_9_GAIN_CH9_Pos (24UL)
6413 #define ADC2_CAL_CH8_9_GAIN_CH9_Msk (0xff000000UL)
6414 #define ADC2_CAL_CH8_9_OFFS_CH9_Pos (16UL)
6415 #define ADC2_CAL_CH8_9_OFFS_CH9_Msk (0xff0000UL)
6416 #define ADC2_CAL_CH8_9_GAIN_CH8_Pos (8UL)
6417 #define ADC2_CAL_CH8_9_GAIN_CH8_Msk (0xff00UL)
6418 #define ADC2_CAL_CH8_9_OFFS_CH8_Pos (0UL)
6419 #define ADC2_CAL_CH8_9_OFFS_CH8_Msk (0xffUL)
6421 #define ADC2_CHx_EIM_SEL_Pos (12UL)
6422 #define ADC2_CHx_EIM_SEL_Msk (0x1000UL)
6423 #define ADC2_CHx_EIM_EN_Pos (11UL)
6424 #define ADC2_CHx_EIM_EN_Msk (0x800UL)
6425 #define ADC2_CHx_EIM_REP_Pos (8UL)
6426 #define ADC2_CHx_EIM_REP_Msk (0x700UL)
6427 #define ADC2_CHx_EIM_CHx_Pos (0UL)
6428 #define ADC2_CHx_EIM_CHx_Msk (0x1fUL)
6430 #define ADC2_CHx_ESM_STS_Pos (17UL)
6431 #define ADC2_CHx_ESM_STS_Msk (0x20000UL)
6432 #define ADC2_CHx_ESM_EN_Pos (16UL)
6433 #define ADC2_CHx_ESM_EN_Msk (0x10000UL)
6434 #define ADC2_CHx_ESM_SEL_Pos (10UL)
6435 #define ADC2_CHx_ESM_SEL_Msk (0x400UL)
6436 #define ADC2_CHx_ESM_ESM_1_Pos (6UL)
6437 #define ADC2_CHx_ESM_ESM_1_Msk (0x3c0UL)
6438 #define ADC2_CHx_ESM_ESM_0_Pos (0UL)
6439 #define ADC2_CHx_ESM_ESM_0_Msk (0x3fUL)
6441 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Pos (27UL)
6442 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Msk (0x18000000UL)
6443 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Pos (24UL)
6444 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Msk (0x7000000UL)
6445 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Pos (19UL)
6446 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Msk (0x180000UL)
6447 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Pos (16UL)
6448 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Msk (0x70000UL)
6449 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Pos (11UL)
6450 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Msk (0x1800UL)
6451 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Pos (8UL)
6452 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Msk (0x700UL)
6453 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Pos (3UL)
6454 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Msk (0x18UL)
6455 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Pos (0UL)
6456 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Msk (0x7UL)
6458 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Pos (27UL)
6459 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Msk (0x18000000UL)
6460 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Pos (24UL)
6461 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Msk (0x7000000UL)
6462 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Pos (19UL)
6463 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Msk (0x180000UL)
6464 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Pos (16UL)
6465 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Msk (0x70000UL)
6466 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Pos (11UL)
6467 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Msk (0x1800UL)
6468 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Pos (8UL)
6469 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Msk (0x700UL)
6470 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Pos (3UL)
6471 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Msk (0x18UL)
6472 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Pos (0UL)
6473 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Msk (0x7UL)
6475 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Pos (11UL)
6476 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Msk (0x1800UL)
6477 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Pos (8UL)
6478 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Msk (0x700UL)
6479 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Pos (3UL)
6480 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Msk (0x18UL)
6481 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Pos (0UL)
6482 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Msk (0x7UL)
6484 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Pos (11UL)
6485 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Msk (0x1800UL)
6486 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Pos (8UL)
6487 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Msk (0x700UL)
6488 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Pos (3UL)
6489 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Msk (0x18UL)
6490 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Pos (0UL)
6491 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Msk (0x7UL)
6493 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Pos (27UL)
6494 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Msk (0x18000000UL)
6495 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Pos (24UL)
6496 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Msk (0x7000000UL)
6497 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Pos (19UL)
6498 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Msk (0x180000UL)
6499 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Pos (16UL)
6500 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Msk (0x70000UL)
6501 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Pos (11UL)
6502 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Msk (0x1800UL)
6503 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Pos (8UL)
6504 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Msk (0x700UL)
6505 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Pos (3UL)
6506 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Msk (0x18UL)
6507 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Pos (0UL)
6508 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Msk (0x7UL)
6510 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Pos (27UL)
6511 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Msk (0x18000000UL)
6512 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Pos (24UL)
6513 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Msk (0x7000000UL)
6514 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Pos (19UL)
6515 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Msk (0x180000UL)
6516 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Pos (16UL)
6517 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Msk (0x70000UL)
6518 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Pos (11UL)
6519 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Msk (0x1800UL)
6520 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Pos (8UL)
6521 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Msk (0x700UL)
6522 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Pos (3UL)
6523 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Msk (0x18UL)
6524 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Pos (0UL)
6525 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Msk (0x7UL)
6527 #define ADC2_CTRL1_CALIB_EN_Pos (0UL)
6528 #define ADC2_CTRL1_CALIB_EN_Msk (0x3fUL)
6530 #define ADC2_CTRL2_SEL_TS_COUNT_Pos (16UL)
6531 #define ADC2_CTRL2_SEL_TS_COUNT_Msk (0xf0000UL)
6532 #define ADC2_CTRL2_SAMPLE_TIME_int_Pos (8UL)
6533 #define ADC2_CTRL2_SAMPLE_TIME_int_Msk (0xf00UL)
6534 #define ADC2_CTRL2_MCM_RDY_Pos (7UL)
6535 #define ADC2_CTRL2_MCM_RDY_Msk (0x80UL)
6536 #define ADC2_CTRL2_TSENSE_SD_SEL_Pos (2UL)
6537 #define ADC2_CTRL2_TSENSE_SD_SEL_Msk (0x4UL)
6538 #define ADC2_CTRL2_TS_SD_SEL_CONF_Pos (1UL)
6539 #define ADC2_CTRL2_TS_SD_SEL_CONF_Msk (0x2UL)
6540 #define ADC2_CTRL2_MCM_PD_N_Pos (0UL)
6541 #define ADC2_CTRL2_MCM_PD_N_Msk (0x1UL)
6543 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Pos (8UL)
6544 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Msk (0xf00UL)
6545 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Pos (0UL)
6546 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Msk (0x3fUL)
6548 #define ADC2_CTRL_STS_VS_RANGE_Pos (17UL)
6549 #define ADC2_CTRL_STS_VS_RANGE_Msk (0x20000UL)
6551 #define ADC2_FILT_LO_CTRL_Ch5_EN_Pos (5UL)
6552 #define ADC2_FILT_LO_CTRL_Ch5_EN_Msk (0x20UL)
6553 #define ADC2_FILT_LO_CTRL_Ch4_EN_Pos (4UL)
6554 #define ADC2_FILT_LO_CTRL_Ch4_EN_Msk (0x10UL)
6555 #define ADC2_FILT_LO_CTRL_Ch3_EN_Pos (3UL)
6556 #define ADC2_FILT_LO_CTRL_Ch3_EN_Msk (0x8UL)
6557 #define ADC2_FILT_LO_CTRL_Ch2_EN_Pos (2UL)
6558 #define ADC2_FILT_LO_CTRL_Ch2_EN_Msk (0x4UL)
6559 #define ADC2_FILT_LO_CTRL_Ch1_EN_Pos (1UL)
6560 #define ADC2_FILT_LO_CTRL_Ch1_EN_Msk (0x2UL)
6561 #define ADC2_FILT_LO_CTRL_Ch0_EN_Pos (0UL)
6562 #define ADC2_FILT_LO_CTRL_Ch0_EN_Msk (0x1UL)
6564 #define ADC2_FILT_OUT0_OUT_CH0_Pos (0UL)
6565 #define ADC2_FILT_OUT0_OUT_CH0_Msk (0x3ffUL)
6567 #define ADC2_FILT_OUT1_OUT_CH1_Pos (0UL)
6568 #define ADC2_FILT_OUT1_OUT_CH1_Msk (0x3ffUL)
6570 #define ADC2_FILT_OUT2_OUT_CH2_Pos (0UL)
6571 #define ADC2_FILT_OUT2_OUT_CH2_Msk (0x3ffUL)
6573 #define ADC2_FILT_OUT3_OUT_CH3_Pos (0UL)
6574 #define ADC2_FILT_OUT3_OUT_CH3_Msk (0x3ffUL)
6576 #define ADC2_FILT_OUT4_OUT_CH4_Pos (0UL)
6577 #define ADC2_FILT_OUT4_OUT_CH4_Msk (0x3ffUL)
6579 #define ADC2_FILT_OUT5_OUT_CH5_Pos (0UL)
6580 #define ADC2_FILT_OUT5_OUT_CH5_Msk (0x3ffUL)
6582 #define ADC2_FILT_OUT6_OUT_CH6_Pos (0UL)
6583 #define ADC2_FILT_OUT6_OUT_CH6_Msk (0x3ffUL)
6585 #define ADC2_FILT_OUT7_OUT_CH7_Pos (0UL)
6586 #define ADC2_FILT_OUT7_OUT_CH7_Msk (0x3ffUL)
6588 #define ADC2_FILT_OUT8_OUT_CH8_Pos (0UL)
6589 #define ADC2_FILT_OUT8_OUT_CH8_Msk (0x3ffUL)
6591 #define ADC2_FILT_OUT9_OUT_CH9_Pos (0UL)
6592 #define ADC2_FILT_OUT9_OUT_CH9_Msk (0x3ffUL)
6594 #define ADC2_FILT_UP_CTRL_Ch5_EN_Pos (5UL)
6595 #define ADC2_FILT_UP_CTRL_Ch5_EN_Msk (0x20UL)
6596 #define ADC2_FILT_UP_CTRL_Ch4_EN_Pos (4UL)
6597 #define ADC2_FILT_UP_CTRL_Ch4_EN_Msk (0x10UL)
6598 #define ADC2_FILT_UP_CTRL_Ch3_EN_Pos (3UL)
6599 #define ADC2_FILT_UP_CTRL_Ch3_EN_Msk (0x8UL)
6600 #define ADC2_FILT_UP_CTRL_Ch2_EN_Pos (2UL)
6601 #define ADC2_FILT_UP_CTRL_Ch2_EN_Msk (0x4UL)
6602 #define ADC2_FILT_UP_CTRL_Ch1_EN_Pos (1UL)
6603 #define ADC2_FILT_UP_CTRL_Ch1_EN_Msk (0x2UL)
6604 #define ADC2_FILT_UP_CTRL_Ch0_EN_Pos (0UL)
6605 #define ADC2_FILT_UP_CTRL_Ch0_EN_Msk (0x1UL)
6607 #define ADC2_FILTCOEFF0_5_CH5_Pos (10UL)
6608 #define ADC2_FILTCOEFF0_5_CH5_Msk (0xc00UL)
6609 #define ADC2_FILTCOEFF0_5_CH4_Pos (8UL)
6610 #define ADC2_FILTCOEFF0_5_CH4_Msk (0x300UL)
6611 #define ADC2_FILTCOEFF0_5_CH3_Pos (6UL)
6612 #define ADC2_FILTCOEFF0_5_CH3_Msk (0xc0UL)
6613 #define ADC2_FILTCOEFF0_5_CH2_Pos (4UL)
6614 #define ADC2_FILTCOEFF0_5_CH2_Msk (0x30UL)
6615 #define ADC2_FILTCOEFF0_5_CH1_Pos (2UL)
6616 #define ADC2_FILTCOEFF0_5_CH1_Msk (0xcUL)
6617 #define ADC2_FILTCOEFF0_5_CH0_Pos (0UL)
6618 #define ADC2_FILTCOEFF0_5_CH0_Msk (0x3UL)
6620 #define ADC2_FILTCOEFF6_9_CH9_Pos (6UL)
6621 #define ADC2_FILTCOEFF6_9_CH9_Msk (0xc0UL)
6622 #define ADC2_FILTCOEFF6_9_CH8_Pos (4UL)
6623 #define ADC2_FILTCOEFF6_9_CH8_Msk (0x30UL)
6624 #define ADC2_FILTCOEFF6_9_CH7_Pos (2UL)
6625 #define ADC2_FILTCOEFF6_9_CH7_Msk (0xcUL)
6626 #define ADC2_FILTCOEFF6_9_CH6_Pos (0UL)
6627 #define ADC2_FILTCOEFF6_9_CH6_Msk (0x3UL)
6629 #define ADC2_HV_STS_READY_Pos (1UL)
6630 #define ADC2_HV_STS_READY_Msk (0x2UL)
6632 #define ADC2_MMODE0_5_Ch5_Pos (10UL)
6633 #define ADC2_MMODE0_5_Ch5_Msk (0xc00UL)
6634 #define ADC2_MMODE0_5_Ch4_Pos (8UL)
6635 #define ADC2_MMODE0_5_Ch4_Msk (0x300UL)
6636 #define ADC2_MMODE0_5_Ch3_Pos (6UL)
6637 #define ADC2_MMODE0_5_Ch3_Msk (0xc0UL)
6638 #define ADC2_MMODE0_5_Ch2_Pos (4UL)
6639 #define ADC2_MMODE0_5_Ch2_Msk (0x30UL)
6640 #define ADC2_MMODE0_5_Ch1_Pos (2UL)
6641 #define ADC2_MMODE0_5_Ch1_Msk (0xcUL)
6642 #define ADC2_MMODE0_5_Ch0_Pos (0UL)
6643 #define ADC2_MMODE0_5_Ch0_Msk (0x3UL)
6645 #define ADC2_SQ1_4_SQ4_Pos (24UL)
6646 #define ADC2_SQ1_4_SQ4_Msk (0x3f000000UL)
6647 #define ADC2_SQ1_4_SQ3_Pos (16UL)
6648 #define ADC2_SQ1_4_SQ3_Msk (0x3f0000UL)
6649 #define ADC2_SQ1_4_SQ2_Pos (8UL)
6650 #define ADC2_SQ1_4_SQ2_Msk (0x3f00UL)
6651 #define ADC2_SQ1_4_SQ1_Pos (0UL)
6652 #define ADC2_SQ1_4_SQ1_Msk (0x3fUL)
6654 #define ADC2_SQ1_8_int_SQ8_int_Pos (28UL)
6655 #define ADC2_SQ1_8_int_SQ8_int_Msk (0xf0000000UL)
6656 #define ADC2_SQ1_8_int_SQ7_int_Pos (24UL)
6657 #define ADC2_SQ1_8_int_SQ7_int_Msk (0xf000000UL)
6658 #define ADC2_SQ1_8_int_SQ6_int_Pos (20UL)
6659 #define ADC2_SQ1_8_int_SQ6_int_Msk (0xf00000UL)
6660 #define ADC2_SQ1_8_int_SQ5_int_Pos (16UL)
6661 #define ADC2_SQ1_8_int_SQ5_int_Msk (0xf0000UL)
6662 #define ADC2_SQ1_8_int_SQ4_int_Pos (12UL)
6663 #define ADC2_SQ1_8_int_SQ4_int_Msk (0xf000UL)
6664 #define ADC2_SQ1_8_int_SQ3_int_Pos (8UL)
6665 #define ADC2_SQ1_8_int_SQ3_int_Msk (0xf00UL)
6666 #define ADC2_SQ1_8_int_SQ2_int_Pos (4UL)
6667 #define ADC2_SQ1_8_int_SQ2_int_Msk (0xf0UL)
6668 #define ADC2_SQ1_8_int_SQ1_int_Pos (0UL)
6669 #define ADC2_SQ1_8_int_SQ1_int_Msk (0xfUL)
6671 #define ADC2_SQ5_8_SQ8_Pos (24UL)
6672 #define ADC2_SQ5_8_SQ8_Msk (0x3f000000UL)
6673 #define ADC2_SQ5_8_SQ7_Pos (16UL)
6674 #define ADC2_SQ5_8_SQ7_Msk (0x3f0000UL)
6675 #define ADC2_SQ5_8_SQ6_Pos (8UL)
6676 #define ADC2_SQ5_8_SQ6_Msk (0x3f00UL)
6677 #define ADC2_SQ5_8_SQ5_Pos (0UL)
6678 #define ADC2_SQ5_8_SQ5_Msk (0x3fUL)
6680 #define ADC2_SQ9_10_SQ10_Pos (8UL)
6681 #define ADC2_SQ9_10_SQ10_Msk (0x3f00UL)
6682 #define ADC2_SQ9_10_SQ9_Pos (0UL)
6683 #define ADC2_SQ9_10_SQ9_Msk (0x3fUL)
6685 #define ADC2_SQ9_10_int_SQ10_int_Pos (4UL)
6686 #define ADC2_SQ9_10_int_SQ10_int_Msk (0xf0UL)
6687 #define ADC2_SQ9_10_int_SQ9_int_Pos (0UL)
6688 #define ADC2_SQ9_10_int_SQ9_int_Msk (0xfUL)
6690 #define ADC2_SQ_FB_CHx_Pos (16UL)
6691 #define ADC2_SQ_FB_CHx_Msk (0x1f0000UL)
6692 #define ADC2_SQ_FB_SQx_Pos (11UL)
6693 #define ADC2_SQ_FB_SQx_Msk (0x7800UL)
6694 #define ADC2_SQ_FB_ESM_ACTIVE_Pos (10UL)
6695 #define ADC2_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6696 #define ADC2_SQ_FB_EIM_ACTIVE_Pos (9UL)
6697 #define ADC2_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6698 #define ADC2_SQ_FB_SQ_STOP_Pos (8UL)
6699 #define ADC2_SQ_FB_SQ_STOP_Msk (0x100UL)
6700 #define ADC2_SQ_FB_SQ_FB_Pos (0UL)
6701 #define ADC2_SQ_FB_SQ_FB_Msk (0xfUL)
6703 #define ADC2_TH0_3_LOWER_CH3_Pos (24UL)
6704 #define ADC2_TH0_3_LOWER_CH3_Msk (0xff000000UL)
6705 #define ADC2_TH0_3_LOWER_CH2_Pos (16UL)
6706 #define ADC2_TH0_3_LOWER_CH2_Msk (0xff0000UL)
6707 #define ADC2_TH0_3_LOWER_CH1_Pos (8UL)
6708 #define ADC2_TH0_3_LOWER_CH1_Msk (0xff00UL)
6709 #define ADC2_TH0_3_LOWER_CH0_Pos (0UL)
6710 #define ADC2_TH0_3_LOWER_CH0_Msk (0xffUL)
6712 #define ADC2_TH0_3_UPPER_CH3_Pos (24UL)
6713 #define ADC2_TH0_3_UPPER_CH3_Msk (0xff000000UL)
6714 #define ADC2_TH0_3_UPPER_CH2_Pos (16UL)
6715 #define ADC2_TH0_3_UPPER_CH2_Msk (0xff0000UL)
6716 #define ADC2_TH0_3_UPPER_CH1_Pos (8UL)
6717 #define ADC2_TH0_3_UPPER_CH1_Msk (0xff00UL)
6718 #define ADC2_TH0_3_UPPER_CH0_Pos (0UL)
6719 #define ADC2_TH0_3_UPPER_CH0_Msk (0xffUL)
6721 #define ADC2_TH4_5_LOWER_CH5_Pos (8UL)
6722 #define ADC2_TH4_5_LOWER_CH5_Msk (0xff00UL)
6723 #define ADC2_TH4_5_LOWER_CH4_Pos (0UL)
6724 #define ADC2_TH4_5_LOWER_CH4_Msk (0xffUL)
6726 #define ADC2_TH4_5_UPPER_CH5_Pos (8UL)
6727 #define ADC2_TH4_5_UPPER_CH5_Msk (0xff00UL)
6728 #define ADC2_TH4_5_UPPER_CH4_Pos (0UL)
6729 #define ADC2_TH4_5_UPPER_CH4_Msk (0xffUL)
6731 #define ADC2_TH6_9_LOWER_CH9_Pos (24UL)
6732 #define ADC2_TH6_9_LOWER_CH9_Msk (0xff000000UL)
6733 #define ADC2_TH6_9_LOWER_CH8_Pos (16UL)
6734 #define ADC2_TH6_9_LOWER_CH8_Msk (0xff0000UL)
6735 #define ADC2_TH6_9_LOWER_CH7_Pos (8UL)
6736 #define ADC2_TH6_9_LOWER_CH7_Msk (0xff00UL)
6737 #define ADC2_TH6_9_LOWER_CH6_Pos (0UL)
6738 #define ADC2_TH6_9_LOWER_CH6_Msk (0xffUL)
6740 #define ADC2_TH6_9_UPPER_CH9_Pos (24UL)
6741 #define ADC2_TH6_9_UPPER_CH9_Msk (0xff000000UL)
6742 #define ADC2_TH6_9_UPPER_CH8_Pos (16UL)
6743 #define ADC2_TH6_9_UPPER_CH8_Msk (0xff0000UL)
6744 #define ADC2_TH6_9_UPPER_CH7_Pos (8UL)
6745 #define ADC2_TH6_9_UPPER_CH7_Msk (0xff00UL)
6746 #define ADC2_TH6_9_UPPER_CH6_Pos (0UL)
6747 #define ADC2_TH6_9_UPPER_CH6_Msk (0xffUL)
6755 #define ADC34_CTRL_STS_ADC4_OSR_Pos (28UL)
6756 #define ADC34_CTRL_STS_ADC4_OSR_Msk (0xf0000000UL)
6757 #define ADC34_CTRL_STS_ADC34_DITHVAL_Pos (24UL)
6758 #define ADC34_CTRL_STS_ADC34_DITHVAL_Msk (0xf000000UL)
6759 #define ADC34_CTRL_STS_ADC34_DITHEN_Pos (23UL)
6760 #define ADC34_CTRL_STS_ADC34_DITHEN_Msk (0x800000UL)
6761 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Pos (21UL)
6762 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Msk (0x600000UL)
6763 #define ADC34_CTRL_STS_ADC4_EoC_STS_Pos (20UL)
6764 #define ADC34_CTRL_STS_ADC4_EoC_STS_Msk (0x100000UL)
6765 #define ADC34_CTRL_STS_ADC4_SOC_Pos (18UL)
6766 #define ADC34_CTRL_STS_ADC4_SOC_Msk (0x40000UL)
6767 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Pos (17UL)
6768 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Msk (0x20000UL)
6769 #define ADC34_CTRL_STS_ADC4_EN_Pos (16UL)
6770 #define ADC34_CTRL_STS_ADC4_EN_Msk (0x10000UL)
6771 #define ADC34_CTRL_STS_ADC3_OSR_Pos (12UL)
6772 #define ADC34_CTRL_STS_ADC3_OSR_Msk (0xf000UL)
6773 #define ADC34_CTRL_STS_ADC34_REF_SEL_Pos (11UL)
6774 #define ADC34_CTRL_STS_ADC34_REF_SEL_Msk (0x800UL)
6775 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Pos (5UL)
6776 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Msk (0x60UL)
6777 #define ADC34_CTRL_STS_ADC3_EoC_STS_Pos (4UL)
6778 #define ADC34_CTRL_STS_ADC3_EoC_STS_Msk (0x10UL)
6779 #define ADC34_CTRL_STS_ADC3_SOC_Pos (2UL)
6780 #define ADC34_CTRL_STS_ADC3_SOC_Msk (0x4UL)
6781 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Pos (1UL)
6782 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Msk (0x2UL)
6783 #define ADC34_CTRL_STS_ADC3_EN_Pos (0UL)
6784 #define ADC34_CTRL_STS_ADC3_EN_Msk (0x1UL)
6786 #define ADC34_RESU_ADC4_RESU_Pos (16UL)
6787 #define ADC34_RESU_ADC4_RESU_Msk (0xffff0000UL)
6788 #define ADC34_RESU_ADC3_RESU_Pos (0UL)
6789 #define ADC34_RESU_ADC3_RESU_Msk (0xffffUL)
6797 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Pos (15UL)
6798 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Msk (0x8000UL)
6799 #define BDRV_CP_CLK_CTRL_F_CP_Pos (13UL)
6800 #define BDRV_CP_CLK_CTRL_F_CP_Msk (0x6000UL)
6801 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Pos (8UL)
6802 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Msk (0x1f00UL)
6803 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Pos (0UL)
6804 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Msk (0x1fUL)
6806 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Pos (26UL)
6807 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Msk (0xc000000UL)
6808 #define BDRV_CP_CTRL_STS_VCP9V_SET_Pos (25UL)
6809 #define BDRV_CP_CTRL_STS_VCP9V_SET_Msk (0x2000000UL)
6810 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Pos (24UL)
6811 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Msk (0x1000000UL)
6812 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Pos (23UL)
6813 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Msk (0x800000UL)
6814 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Pos (22UL)
6815 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Msk (0x400000UL)
6816 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Pos (21UL)
6817 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Msk (0x200000UL)
6818 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Pos (20UL)
6819 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Msk (0x100000UL)
6820 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Pos (19UL)
6821 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Msk (0x80000UL)
6822 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Pos (18UL)
6823 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Msk (0x40000UL)
6824 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Pos (17UL)
6825 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Msk (0x20000UL)
6826 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Pos (16UL)
6827 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Msk (0x10000UL)
6828 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Pos (8UL)
6829 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Msk (0x700UL)
6830 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Pos (5UL)
6831 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Msk (0x20UL)
6832 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Pos (2UL)
6833 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Msk (0x4UL)
6834 #define BDRV_CP_CTRL_STS_CP_EN_Pos (0UL)
6835 #define BDRV_CP_CTRL_STS_CP_EN_Msk (0x1UL)
6837 #define BDRV_CTRL1_HS2_OC_DIS_Pos (31UL)
6838 #define BDRV_CTRL1_HS2_OC_DIS_Msk (0x80000000UL)
6839 #define BDRV_CTRL1_HS2_OC_STS_Pos (30UL)
6840 #define BDRV_CTRL1_HS2_OC_STS_Msk (0x40000000UL)
6841 #define BDRV_CTRL1_HS2_SUPERR_STS_Pos (29UL)
6842 #define BDRV_CTRL1_HS2_SUPERR_STS_Msk (0x20000000UL)
6843 #define BDRV_CTRL1_HS2_DS_STS_Pos (28UL)
6844 #define BDRV_CTRL1_HS2_DS_STS_Msk (0x10000000UL)
6845 #define BDRV_CTRL1_HS2_DCS_EN_Pos (27UL)
6846 #define BDRV_CTRL1_HS2_DCS_EN_Msk (0x8000000UL)
6847 #define BDRV_CTRL1_HS2_ON_Pos (26UL)
6848 #define BDRV_CTRL1_HS2_ON_Msk (0x4000000UL)
6849 #define BDRV_CTRL1_HS2_PWM_Pos (25UL)
6850 #define BDRV_CTRL1_HS2_PWM_Msk (0x2000000UL)
6851 #define BDRV_CTRL1_HS2_EN_Pos (24UL)
6852 #define BDRV_CTRL1_HS2_EN_Msk (0x1000000UL)
6853 #define BDRV_CTRL1_HS1_OC_DIS_Pos (23UL)
6854 #define BDRV_CTRL1_HS1_OC_DIS_Msk (0x800000UL)
6855 #define BDRV_CTRL1_HS1_OC_STS_Pos (22UL)
6856 #define BDRV_CTRL1_HS1_OC_STS_Msk (0x400000UL)
6857 #define BDRV_CTRL1_HS1_SUPERR_STS_Pos (21UL)
6858 #define BDRV_CTRL1_HS1_SUPERR_STS_Msk (0x200000UL)
6859 #define BDRV_CTRL1_HS1_DS_STS_Pos (20UL)
6860 #define BDRV_CTRL1_HS1_DS_STS_Msk (0x100000UL)
6861 #define BDRV_CTRL1_HS1_DCS_EN_Pos (19UL)
6862 #define BDRV_CTRL1_HS1_DCS_EN_Msk (0x80000UL)
6863 #define BDRV_CTRL1_HS1_ON_Pos (18UL)
6864 #define BDRV_CTRL1_HS1_ON_Msk (0x40000UL)
6865 #define BDRV_CTRL1_HS1_PWM_Pos (17UL)
6866 #define BDRV_CTRL1_HS1_PWM_Msk (0x20000UL)
6867 #define BDRV_CTRL1_HS1_EN_Pos (16UL)
6868 #define BDRV_CTRL1_HS1_EN_Msk (0x10000UL)
6869 #define BDRV_CTRL1_LS2_OC_DIS_Pos (15UL)
6870 #define BDRV_CTRL1_LS2_OC_DIS_Msk (0x8000UL)
6871 #define BDRV_CTRL1_LS2_OC_STS_Pos (14UL)
6872 #define BDRV_CTRL1_LS2_OC_STS_Msk (0x4000UL)
6873 #define BDRV_CTRL1_LS2_SUPERR_STS_Pos (13UL)
6874 #define BDRV_CTRL1_LS2_SUPERR_STS_Msk (0x2000UL)
6875 #define BDRV_CTRL1_LS2_DS_STS_Pos (12UL)
6876 #define BDRV_CTRL1_LS2_DS_STS_Msk (0x1000UL)
6877 #define BDRV_CTRL1_LS2_DCS_EN_Pos (11UL)
6878 #define BDRV_CTRL1_LS2_DCS_EN_Msk (0x800UL)
6879 #define BDRV_CTRL1_LS2_ON_Pos (10UL)
6880 #define BDRV_CTRL1_LS2_ON_Msk (0x400UL)
6881 #define BDRV_CTRL1_LS2_PWM_Pos (9UL)
6882 #define BDRV_CTRL1_LS2_PWM_Msk (0x200UL)
6883 #define BDRV_CTRL1_LS2_EN_Pos (8UL)
6884 #define BDRV_CTRL1_LS2_EN_Msk (0x100UL)
6885 #define BDRV_CTRL1_LS1_OC_DIS_Pos (7UL)
6886 #define BDRV_CTRL1_LS1_OC_DIS_Msk (0x80UL)
6887 #define BDRV_CTRL1_LS1_OC_STS_Pos (6UL)
6888 #define BDRV_CTRL1_LS1_OC_STS_Msk (0x40UL)
6889 #define BDRV_CTRL1_LS1_SUPERR_STS_Pos (5UL)
6890 #define BDRV_CTRL1_LS1_SUPERR_STS_Msk (0x20UL)
6891 #define BDRV_CTRL1_LS1_DS_STS_Pos (4UL)
6892 #define BDRV_CTRL1_LS1_DS_STS_Msk (0x10UL)
6893 #define BDRV_CTRL1_LS1_DCS_EN_Pos (3UL)
6894 #define BDRV_CTRL1_LS1_DCS_EN_Msk (0x8UL)
6895 #define BDRV_CTRL1_LS1_ON_Pos (2UL)
6896 #define BDRV_CTRL1_LS1_ON_Msk (0x4UL)
6897 #define BDRV_CTRL1_LS1_PWM_Pos (1UL)
6898 #define BDRV_CTRL1_LS1_PWM_Msk (0x2UL)
6899 #define BDRV_CTRL1_LS1_EN_Pos (0UL)
6900 #define BDRV_CTRL1_LS1_EN_Msk (0x1UL)
6902 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Pos (31UL)
6903 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Msk (0x80000000UL)
6904 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Pos (28UL)
6905 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Msk (0x70000000UL)
6906 #define BDRV_CTRL2_DLY_DIAG_STS_Pos (27UL)
6907 #define BDRV_CTRL2_DLY_DIAG_STS_Msk (0x8000000UL)
6908 #define BDRV_CTRL2_DLY_DIAG_SCLR_Pos (26UL)
6909 #define BDRV_CTRL2_DLY_DIAG_SCLR_Msk (0x4000000UL)
6910 #define BDRV_CTRL2_DLY_DIAG_TIM_Pos (16UL)
6911 #define BDRV_CTRL2_DLY_DIAG_TIM_Msk (0x3ff0000UL)
6912 #define BDRV_CTRL2_HS3_OC_DIS_Pos (15UL)
6913 #define BDRV_CTRL2_HS3_OC_DIS_Msk (0x8000UL)
6914 #define BDRV_CTRL2_HS3_OC_STS_Pos (14UL)
6915 #define BDRV_CTRL2_HS3_OC_STS_Msk (0x4000UL)
6916 #define BDRV_CTRL2_HS3_SUPERR_STS_Pos (13UL)
6917 #define BDRV_CTRL2_HS3_SUPERR_STS_Msk (0x2000UL)
6918 #define BDRV_CTRL2_HS3_DS_STS_Pos (12UL)
6919 #define BDRV_CTRL2_HS3_DS_STS_Msk (0x1000UL)
6920 #define BDRV_CTRL2_HS3_DCS_EN_Pos (11UL)
6921 #define BDRV_CTRL2_HS3_DCS_EN_Msk (0x800UL)
6922 #define BDRV_CTRL2_HS3_ON_Pos (10UL)
6923 #define BDRV_CTRL2_HS3_ON_Msk (0x400UL)
6924 #define BDRV_CTRL2_HS3_PWM_Pos (9UL)
6925 #define BDRV_CTRL2_HS3_PWM_Msk (0x200UL)
6926 #define BDRV_CTRL2_HS3_EN_Pos (8UL)
6927 #define BDRV_CTRL2_HS3_EN_Msk (0x100UL)
6928 #define BDRV_CTRL2_LS3_OC_DIS_Pos (7UL)
6929 #define BDRV_CTRL2_LS3_OC_DIS_Msk (0x80UL)
6930 #define BDRV_CTRL2_LS3_OC_STS_Pos (6UL)
6931 #define BDRV_CTRL2_LS3_OC_STS_Msk (0x40UL)
6932 #define BDRV_CTRL2_LS3_SUPERR_STS_Pos (5UL)
6933 #define BDRV_CTRL2_LS3_SUPERR_STS_Msk (0x20UL)
6934 #define BDRV_CTRL2_LS3_DS_STS_Pos (4UL)
6935 #define BDRV_CTRL2_LS3_DS_STS_Msk (0x10UL)
6936 #define BDRV_CTRL2_LS3_DCS_EN_Pos (3UL)
6937 #define BDRV_CTRL2_LS3_DCS_EN_Msk (0x8UL)
6938 #define BDRV_CTRL2_LS3_ON_Pos (2UL)
6939 #define BDRV_CTRL2_LS3_ON_Msk (0x4UL)
6940 #define BDRV_CTRL2_LS3_PWM_Pos (1UL)
6941 #define BDRV_CTRL2_LS3_PWM_Msk (0x2UL)
6942 #define BDRV_CTRL2_LS3_EN_Pos (0UL)
6943 #define BDRV_CTRL2_LS3_EN_Msk (0x1UL)
6945 #define BDRV_CTRL3_DRV_CCP_DIS_Pos (26UL)
6946 #define BDRV_CTRL3_DRV_CCP_DIS_Msk (0x4000000UL)
6947 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Pos (24UL)
6948 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Msk (0x3000000UL)
6949 #define BDRV_CTRL3_DSMONVTH_Pos (16UL)
6950 #define BDRV_CTRL3_DSMONVTH_Msk (0x70000UL)
6951 #define BDRV_CTRL3_OFF_SEQ_EN_Pos (15UL)
6952 #define BDRV_CTRL3_OFF_SEQ_EN_Msk (0x8000UL)
6953 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Pos (14UL)
6954 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Msk (0x4000UL)
6955 #define BDRV_CTRL3_IDISCHARGE_TRIM_Pos (8UL)
6956 #define BDRV_CTRL3_IDISCHARGE_TRIM_Msk (0x1f00UL)
6957 #define BDRV_CTRL3_ON_SEQ_EN_Pos (7UL)
6958 #define BDRV_CTRL3_ON_SEQ_EN_Msk (0x80UL)
6959 #define BDRV_CTRL3_ICHARGEDIV2_N_Pos (6UL)
6960 #define BDRV_CTRL3_ICHARGEDIV2_N_Msk (0x40UL)
6961 #define BDRV_CTRL3_ICHARGE_TRIM_Pos (0UL)
6962 #define BDRV_CTRL3_ICHARGE_TRIM_Msk (0x1fUL)
6964 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Pos (27UL)
6965 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Msk (0xf8000000UL)
6966 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Pos (24UL)
6967 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Msk (0x7000000UL)
6968 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Pos (19UL)
6969 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Msk (0xf80000UL)
6970 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Pos (16UL)
6971 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Msk (0x70000UL)
6972 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Pos (11UL)
6973 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Msk (0xf800UL)
6974 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Pos (8UL)
6975 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Msk (0x700UL)
6976 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Pos (3UL)
6977 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Msk (0xf8UL)
6978 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Pos (0UL)
6979 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Msk (0x7UL)
6981 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Pos (27UL)
6982 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Msk (0xf8000000UL)
6983 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Pos (24UL)
6984 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Msk (0x7000000UL)
6985 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Pos (19UL)
6986 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Msk (0xf80000UL)
6987 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Pos (16UL)
6988 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Msk (0x70000UL)
6989 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Pos (11UL)
6990 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Msk (0xf800UL)
6991 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Pos (8UL)
6992 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Msk (0x700UL)
6993 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Pos (3UL)
6994 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Msk (0xf8UL)
6995 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Pos (0UL)
6996 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Msk (0x7UL)
6998 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Pos (24UL)
6999 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Msk (0x3000000UL)
7000 #define BDRV_TRIM_DRVx_HS3DRV_OCSDN_DIS_Pos (23UL)
7001 #define BDRV_TRIM_DRVx_HS3DRV_OCSDN_DIS_Msk (0x800000UL)
7002 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Pos (22UL)
7003 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Msk (0x400000UL)
7004 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Pos (21UL)
7005 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Msk (0x200000UL)
7006 #define BDRV_TRIM_DRVx_HS3DRV_FDISCHG_DIS_Pos (20UL)
7007 #define BDRV_TRIM_DRVx_HS3DRV_FDISCHG_DIS_Msk (0x100000UL)
7008 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Pos (19UL)
7009 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Msk (0x80000UL)
7010 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Pos (18UL)
7011 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Msk (0x40000UL)
7012 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Pos (16UL)
7013 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Msk (0x30000UL)
7014 #define BDRV_TRIM_DRVx_LS3DRV_OCSDN_DIS_Pos (15UL)
7015 #define BDRV_TRIM_DRVx_LS3DRV_OCSDN_DIS_Msk (0x8000UL)
7016 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Pos (14UL)
7017 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Msk (0x4000UL)
7018 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Pos (13UL)
7019 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Msk (0x2000UL)
7020 #define BDRV_TRIM_DRVx_LS3DRV_FDISCHG_DIS_Pos (12UL)
7021 #define BDRV_TRIM_DRVx_LS3DRV_FDISCHG_DIS_Msk (0x1000UL)
7022 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Pos (11UL)
7023 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Msk (0x800UL)
7024 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Pos (10UL)
7025 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Msk (0x400UL)
7026 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Pos (8UL)
7027 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Msk (0x300UL)
7028 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Pos (5UL)
7029 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Msk (0x60UL)
7030 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Pos (0UL)
7031 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Msk (0x3UL)
7039 #define CCU6_CC60R_CCV_Pos (0UL)
7040 #define CCU6_CC60R_CCV_Msk (0xffffUL)
7042 #define CCU6_CC60SR_CCS_Pos (0UL)
7043 #define CCU6_CC60SR_CCS_Msk (0xffffUL)
7045 #define CCU6_CC61R_CCV_Pos (0UL)
7046 #define CCU6_CC61R_CCV_Msk (0xffffUL)
7048 #define CCU6_CC61SR_CCS_Pos (0UL)
7049 #define CCU6_CC61SR_CCS_Msk (0xffffUL)
7051 #define CCU6_CC62R_CCV_Pos (0UL)
7052 #define CCU6_CC62R_CCV_Msk (0xffffUL)
7054 #define CCU6_CC62SR_CCS_Pos (0UL)
7055 #define CCU6_CC62SR_CCS_Msk (0xffffUL)
7057 #define CCU6_CC63R_CCV_Pos (0UL)
7058 #define CCU6_CC63R_CCV_Msk (0xffffUL)
7060 #define CCU6_CC63SR_CCS_Pos (0UL)
7061 #define CCU6_CC63SR_CCS_Msk (0xffffUL)
7063 #define CCU6_CMPMODIF_MCC60S_Pos (0UL)
7064 #define CCU6_CMPMODIF_MCC60S_Msk (0x1UL)
7065 #define CCU6_CMPMODIF_MCC61S_Pos (1UL)
7066 #define CCU6_CMPMODIF_MCC61S_Msk (0x2UL)
7067 #define CCU6_CMPMODIF_MCC62S_Pos (2UL)
7068 #define CCU6_CMPMODIF_MCC62S_Msk (0x4UL)
7069 #define CCU6_CMPMODIF_MCC63S_Pos (6UL)
7070 #define CCU6_CMPMODIF_MCC63S_Msk (0x40UL)
7071 #define CCU6_CMPMODIF_MCC60R_Pos (8UL)
7072 #define CCU6_CMPMODIF_MCC60R_Msk (0x100UL)
7073 #define CCU6_CMPMODIF_MCC61R_Pos (9UL)
7074 #define CCU6_CMPMODIF_MCC61R_Msk (0x200UL)
7075 #define CCU6_CMPMODIF_MCC62R_Pos (10UL)
7076 #define CCU6_CMPMODIF_MCC62R_Msk (0x400UL)
7077 #define CCU6_CMPMODIF_MCC63R_Pos (14UL)
7078 #define CCU6_CMPMODIF_MCC63R_Msk (0x4000UL)
7080 #define CCU6_CMPSTAT_CC60ST_Pos (0UL)
7081 #define CCU6_CMPSTAT_CC60ST_Msk (0x1UL)
7082 #define CCU6_CMPSTAT_CC61ST_Pos (1UL)
7083 #define CCU6_CMPSTAT_CC61ST_Msk (0x2UL)
7084 #define CCU6_CMPSTAT_CC62ST_Pos (2UL)
7085 #define CCU6_CMPSTAT_CC62ST_Msk (0x4UL)
7086 #define CCU6_CMPSTAT_CC63ST_Pos (6UL)
7087 #define CCU6_CMPSTAT_CC63ST_Msk (0x40UL)
7088 #define CCU6_CMPSTAT_CCPOS0_Pos (3UL)
7089 #define CCU6_CMPSTAT_CCPOS0_Msk (0x8UL)
7090 #define CCU6_CMPSTAT_CCPOS1_Pos (4UL)
7091 #define CCU6_CMPSTAT_CCPOS1_Msk (0x10UL)
7092 #define CCU6_CMPSTAT_CCPOS2_Pos (5UL)
7093 #define CCU6_CMPSTAT_CCPOS2_Msk (0x20UL)
7094 #define CCU6_CMPSTAT_CC60PS_Pos (8UL)
7095 #define CCU6_CMPSTAT_CC60PS_Msk (0x100UL)
7096 #define CCU6_CMPSTAT_CC61PS_Pos (10UL)
7097 #define CCU6_CMPSTAT_CC61PS_Msk (0x400UL)
7098 #define CCU6_CMPSTAT_CC62PS_Pos (12UL)
7099 #define CCU6_CMPSTAT_CC62PS_Msk (0x1000UL)
7100 #define CCU6_CMPSTAT_COUT60PS_Pos (9UL)
7101 #define CCU6_CMPSTAT_COUT60PS_Msk (0x200UL)
7102 #define CCU6_CMPSTAT_COUT61PS_Pos (11UL)
7103 #define CCU6_CMPSTAT_COUT61PS_Msk (0x800UL)
7104 #define CCU6_CMPSTAT_COUT62PS_Pos (13UL)
7105 #define CCU6_CMPSTAT_COUT62PS_Msk (0x2000UL)
7106 #define CCU6_CMPSTAT_COUT63PS_Pos (14UL)
7107 #define CCU6_CMPSTAT_COUT63PS_Msk (0x4000UL)
7108 #define CCU6_CMPSTAT_T13IM_Pos (15UL)
7109 #define CCU6_CMPSTAT_T13IM_Msk (0x8000UL)
7111 #define CCU6_IEN_ENCC60R_Pos (0UL)
7112 #define CCU6_IEN_ENCC60R_Msk (0x1UL)
7113 #define CCU6_IEN_ENCC60F_Pos (1UL)
7114 #define CCU6_IEN_ENCC60F_Msk (0x2UL)
7115 #define CCU6_IEN_ENCC61R_Pos (2UL)
7116 #define CCU6_IEN_ENCC61R_Msk (0x4UL)
7117 #define CCU6_IEN_ENCC61F_Pos (3UL)
7118 #define CCU6_IEN_ENCC61F_Msk (0x8UL)
7119 #define CCU6_IEN_ENCC62R_Pos (4UL)
7120 #define CCU6_IEN_ENCC62R_Msk (0x10UL)
7121 #define CCU6_IEN_ENCC62F_Pos (5UL)
7122 #define CCU6_IEN_ENCC62F_Msk (0x20UL)
7123 #define CCU6_IEN_ENT12OM_Pos (6UL)
7124 #define CCU6_IEN_ENT12OM_Msk (0x40UL)
7125 #define CCU6_IEN_ENT12PM_Pos (7UL)
7126 #define CCU6_IEN_ENT12PM_Msk (0x80UL)
7127 #define CCU6_IEN_ENT13CM_Pos (8UL)
7128 #define CCU6_IEN_ENT13CM_Msk (0x100UL)
7129 #define CCU6_IEN_ENT13PM_Pos (9UL)
7130 #define CCU6_IEN_ENT13PM_Msk (0x200UL)
7131 #define CCU6_IEN_ENTRPF_Pos (10UL)
7132 #define CCU6_IEN_ENTRPF_Msk (0x400UL)
7133 #define CCU6_IEN_ENCHE_Pos (12UL)
7134 #define CCU6_IEN_ENCHE_Msk (0x1000UL)
7135 #define CCU6_IEN_ENWHE_Pos (13UL)
7136 #define CCU6_IEN_ENWHE_Msk (0x2000UL)
7137 #define CCU6_IEN_ENIDLE_Pos (14UL)
7138 #define CCU6_IEN_ENIDLE_Msk (0x4000UL)
7139 #define CCU6_IEN_ENSTR_Pos (15UL)
7140 #define CCU6_IEN_ENSTR_Msk (0x8000UL)
7142 #define CCU6_INP_INPCC60_Pos (0UL)
7143 #define CCU6_INP_INPCC60_Msk (0x3UL)
7144 #define CCU6_INP_INPCC61_Pos (2UL)
7145 #define CCU6_INP_INPCC61_Msk (0xcUL)
7146 #define CCU6_INP_INPCC62_Pos (4UL)
7147 #define CCU6_INP_INPCC62_Msk (0x30UL)
7148 #define CCU6_INP_INPCHE_Pos (6UL)
7149 #define CCU6_INP_INPCHE_Msk (0xc0UL)
7150 #define CCU6_INP_INPERR_Pos (8UL)
7151 #define CCU6_INP_INPERR_Msk (0x300UL)
7152 #define CCU6_INP_INPT12_Pos (10UL)
7153 #define CCU6_INP_INPT12_Msk (0xc00UL)
7154 #define CCU6_INP_INPT13_Pos (12UL)
7155 #define CCU6_INP_INPT13_Msk (0x3000UL)
7157 #define CCU6_IS_ICC60R_Pos (0UL)
7158 #define CCU6_IS_ICC60R_Msk (0x1UL)
7159 #define CCU6_IS_ICC61R_Pos (2UL)
7160 #define CCU6_IS_ICC61R_Msk (0x4UL)
7161 #define CCU6_IS_ICC62R_Pos (4UL)
7162 #define CCU6_IS_ICC62R_Msk (0x10UL)
7163 #define CCU6_IS_ICC60F_Pos (1UL)
7164 #define CCU6_IS_ICC60F_Msk (0x2UL)
7165 #define CCU6_IS_ICC61F_Pos (3UL)
7166 #define CCU6_IS_ICC61F_Msk (0x8UL)
7167 #define CCU6_IS_ICC62F_Pos (5UL)
7168 #define CCU6_IS_ICC62F_Msk (0x20UL)
7169 #define CCU6_IS_T12OM_Pos (6UL)
7170 #define CCU6_IS_T12OM_Msk (0x40UL)
7171 #define CCU6_IS_T12PM_Pos (7UL)
7172 #define CCU6_IS_T12PM_Msk (0x80UL)
7173 #define CCU6_IS_T13CM_Pos (8UL)
7174 #define CCU6_IS_T13CM_Msk (0x100UL)
7175 #define CCU6_IS_T13PM_Pos (9UL)
7176 #define CCU6_IS_T13PM_Msk (0x200UL)
7177 #define CCU6_IS_TRPF_Pos (10UL)
7178 #define CCU6_IS_TRPF_Msk (0x400UL)
7179 #define CCU6_IS_TRPS_Pos (11UL)
7180 #define CCU6_IS_TRPS_Msk (0x800UL)
7181 #define CCU6_IS_CHE_Pos (12UL)
7182 #define CCU6_IS_CHE_Msk (0x1000UL)
7183 #define CCU6_IS_WHE_Pos (13UL)
7184 #define CCU6_IS_WHE_Msk (0x2000UL)
7185 #define CCU6_IS_IDLE_Pos (14UL)
7186 #define CCU6_IS_IDLE_Msk (0x4000UL)
7187 #define CCU6_IS_STR_Pos (15UL)
7188 #define CCU6_IS_STR_Msk (0x8000UL)
7190 #define CCU6_ISR_RCC60R_Pos (0UL)
7191 #define CCU6_ISR_RCC60R_Msk (0x1UL)
7192 #define CCU6_ISR_RCC60F_Pos (1UL)
7193 #define CCU6_ISR_RCC60F_Msk (0x2UL)
7194 #define CCU6_ISR_RCC61R_Pos (2UL)
7195 #define CCU6_ISR_RCC61R_Msk (0x4UL)
7196 #define CCU6_ISR_RCC61F_Pos (3UL)
7197 #define CCU6_ISR_RCC61F_Msk (0x8UL)
7198 #define CCU6_ISR_RCC62R_Pos (4UL)
7199 #define CCU6_ISR_RCC62R_Msk (0x10UL)
7200 #define CCU6_ISR_RCC62F_Pos (5UL)
7201 #define CCU6_ISR_RCC62F_Msk (0x20UL)
7202 #define CCU6_ISR_RT12OM_Pos (6UL)
7203 #define CCU6_ISR_RT12OM_Msk (0x40UL)
7204 #define CCU6_ISR_RT12PM_Pos (7UL)
7205 #define CCU6_ISR_RT12PM_Msk (0x80UL)
7206 #define CCU6_ISR_RT13CM_Pos (8UL)
7207 #define CCU6_ISR_RT13CM_Msk (0x100UL)
7208 #define CCU6_ISR_RT13PM_Pos (9UL)
7209 #define CCU6_ISR_RT13PM_Msk (0x200UL)
7210 #define CCU6_ISR_RTRPF_Pos (10UL)
7211 #define CCU6_ISR_RTRPF_Msk (0x400UL)
7212 #define CCU6_ISR_RCHE_Pos (12UL)
7213 #define CCU6_ISR_RCHE_Msk (0x1000UL)
7214 #define CCU6_ISR_RWHE_Pos (13UL)
7215 #define CCU6_ISR_RWHE_Msk (0x2000UL)
7216 #define CCU6_ISR_RIDLE_Pos (14UL)
7217 #define CCU6_ISR_RIDLE_Msk (0x4000UL)
7218 #define CCU6_ISR_RSTR_Pos (15UL)
7219 #define CCU6_ISR_RSTR_Msk (0x8000UL)
7221 #define CCU6_ISS_SCC60R_Pos (0UL)
7222 #define CCU6_ISS_SCC60R_Msk (0x1UL)
7223 #define CCU6_ISS_SCC60F_Pos (1UL)
7224 #define CCU6_ISS_SCC60F_Msk (0x2UL)
7225 #define CCU6_ISS_SCC61R_Pos (2UL)
7226 #define CCU6_ISS_SCC61R_Msk (0x4UL)
7227 #define CCU6_ISS_SCC61F_Pos (3UL)
7228 #define CCU6_ISS_SCC61F_Msk (0x8UL)
7229 #define CCU6_ISS_SCC62R_Pos (4UL)
7230 #define CCU6_ISS_SCC62R_Msk (0x10UL)
7231 #define CCU6_ISS_SCC62F_Pos (5UL)
7232 #define CCU6_ISS_SCC62F_Msk (0x20UL)
7233 #define CCU6_ISS_ST12OM_Pos (6UL)
7234 #define CCU6_ISS_ST12OM_Msk (0x40UL)
7235 #define CCU6_ISS_ST12PM_Pos (7UL)
7236 #define CCU6_ISS_ST12PM_Msk (0x80UL)
7237 #define CCU6_ISS_ST13CM_Pos (8UL)
7238 #define CCU6_ISS_ST13CM_Msk (0x100UL)
7239 #define CCU6_ISS_ST13PM_Pos (9UL)
7240 #define CCU6_ISS_ST13PM_Msk (0x200UL)
7241 #define CCU6_ISS_STRPF_Pos (10UL)
7242 #define CCU6_ISS_STRPF_Msk (0x400UL)
7243 #define CCU6_ISS_SWHC_Pos (11UL)
7244 #define CCU6_ISS_SWHC_Msk (0x800UL)
7245 #define CCU6_ISS_SCHE_Pos (12UL)
7246 #define CCU6_ISS_SCHE_Msk (0x1000UL)
7247 #define CCU6_ISS_SWHE_Pos (13UL)
7248 #define CCU6_ISS_SWHE_Msk (0x2000UL)
7249 #define CCU6_ISS_SIDLE_Pos (14UL)
7250 #define CCU6_ISS_SIDLE_Msk (0x4000UL)
7251 #define CCU6_ISS_SSTR_Pos (15UL)
7252 #define CCU6_ISS_SSTR_Msk (0x8000UL)
7254 #define CCU6_MCMCTR_SWSEL_Pos (0UL)
7255 #define CCU6_MCMCTR_SWSEL_Msk (0x7UL)
7256 #define CCU6_MCMCTR_SWSYN_Pos (4UL)
7257 #define CCU6_MCMCTR_SWSYN_Msk (0x30UL)
7258 #define CCU6_MCMCTR_STE12U_Pos (8UL)
7259 #define CCU6_MCMCTR_STE12U_Msk (0x100UL)
7260 #define CCU6_MCMCTR_STE12D_Pos (9UL)
7261 #define CCU6_MCMCTR_STE12D_Msk (0x200UL)
7262 #define CCU6_MCMCTR_STE13U_Pos (10UL)
7263 #define CCU6_MCMCTR_STE13U_Msk (0x400UL)
7265 #define CCU6_MCMOUT_MCMP_Pos (0UL)
7266 #define CCU6_MCMOUT_MCMP_Msk (0x3fUL)
7267 #define CCU6_MCMOUT_R_Pos (6UL)
7268 #define CCU6_MCMOUT_R_Msk (0x40UL)
7269 #define CCU6_MCMOUT_EXPH_Pos (8UL)
7270 #define CCU6_MCMOUT_EXPH_Msk (0x700UL)
7271 #define CCU6_MCMOUT_CURH_Pos (11UL)
7272 #define CCU6_MCMOUT_CURH_Msk (0x3800UL)
7274 #define CCU6_MCMOUTS_MCMPS_Pos (0UL)
7275 #define CCU6_MCMOUTS_MCMPS_Msk (0x3fUL)
7276 #define CCU6_MCMOUTS_STRMCM_Pos (7UL)
7277 #define CCU6_MCMOUTS_STRMCM_Msk (0x80UL)
7278 #define CCU6_MCMOUTS_EXPHS_Pos (8UL)
7279 #define CCU6_MCMOUTS_EXPHS_Msk (0x700UL)
7280 #define CCU6_MCMOUTS_CURHS_Pos (11UL)
7281 #define CCU6_MCMOUTS_CURHS_Msk (0x3800UL)
7282 #define CCU6_MCMOUTS_STRHP_Pos (15UL)
7283 #define CCU6_MCMOUTS_STRHP_Msk (0x8000UL)
7285 #define CCU6_MODCTR_T12MODEN_Pos (0UL)
7286 #define CCU6_MODCTR_T12MODEN_Msk (0x3fUL)
7287 #define CCU6_MODCTR_MCMEN_Pos (7UL)
7288 #define CCU6_MODCTR_MCMEN_Msk (0x80UL)
7289 #define CCU6_MODCTR_T13MODEN_Pos (8UL)
7290 #define CCU6_MODCTR_T13MODEN_Msk (0x3f00UL)
7291 #define CCU6_MODCTR_ECT13O_Pos (15UL)
7292 #define CCU6_MODCTR_ECT13O_Msk (0x8000UL)
7294 #define CCU6_PISEL0_ISCC60_Pos (0UL)
7295 #define CCU6_PISEL0_ISCC60_Msk (0x3UL)
7296 #define CCU6_PISEL0_ISCC61_Pos (2UL)
7297 #define CCU6_PISEL0_ISCC61_Msk (0xcUL)
7298 #define CCU6_PISEL0_ISCC62_Pos (4UL)
7299 #define CCU6_PISEL0_ISCC62_Msk (0x30UL)
7300 #define CCU6_PISEL0_ISTRP_Pos (6UL)
7301 #define CCU6_PISEL0_ISTRP_Msk (0xc0UL)
7302 #define CCU6_PISEL0_ISPOS0_Pos (8UL)
7303 #define CCU6_PISEL0_ISPOS0_Msk (0x300UL)
7304 #define CCU6_PISEL0_ISPOS1_Pos (10UL)
7305 #define CCU6_PISEL0_ISPOS1_Msk (0xc00UL)
7306 #define CCU6_PISEL0_ISPOS2_Pos (12UL)
7307 #define CCU6_PISEL0_ISPOS2_Msk (0x3000UL)
7308 #define CCU6_PISEL0_IST12HR_Pos (14UL)
7309 #define CCU6_PISEL0_IST12HR_Msk (0xc000UL)
7311 #define CCU6_PISEL2_IST13HR_Pos (0UL)
7312 #define CCU6_PISEL2_IST13HR_Msk (0x3UL)
7313 #define CCU6_PISEL2_ISCNT12_Pos (2UL)
7314 #define CCU6_PISEL2_ISCNT12_Msk (0xcUL)
7315 #define CCU6_PISEL2_ISCNT13_Pos (4UL)
7316 #define CCU6_PISEL2_ISCNT13_Msk (0x30UL)
7317 #define CCU6_PISEL2_T12EXT_Pos (6UL)
7318 #define CCU6_PISEL2_T12EXT_Msk (0x40UL)
7319 #define CCU6_PISEL2_T13EXT_Pos (7UL)
7320 #define CCU6_PISEL2_T13EXT_Msk (0x80UL)
7322 #define CCU6_PSLR_PSL_Pos (0UL)
7323 #define CCU6_PSLR_PSL_Msk (0x3fUL)
7324 #define CCU6_PSLR_PSL63_Pos (7UL)
7325 #define CCU6_PSLR_PSL63_Msk (0x80UL)
7327 #define CCU6_T12_T12CV_Pos (0UL)
7328 #define CCU6_T12_T12CV_Msk (0xffffUL)
7330 #define CCU6_T12DTC_DTM_Pos (0UL)
7331 #define CCU6_T12DTC_DTM_Msk (0xffUL)
7332 #define CCU6_T12DTC_DTE0_Pos (8UL)
7333 #define CCU6_T12DTC_DTE0_Msk (0x100UL)
7334 #define CCU6_T12DTC_DTE1_Pos (9UL)
7335 #define CCU6_T12DTC_DTE1_Msk (0x200UL)
7336 #define CCU6_T12DTC_DTE2_Pos (10UL)
7337 #define CCU6_T12DTC_DTE2_Msk (0x400UL)
7338 #define CCU6_T12DTC_DTR0_Pos (12UL)
7339 #define CCU6_T12DTC_DTR0_Msk (0x1000UL)
7340 #define CCU6_T12DTC_DTR1_Pos (13UL)
7341 #define CCU6_T12DTC_DTR1_Msk (0x2000UL)
7342 #define CCU6_T12DTC_DTR2_Pos (14UL)
7343 #define CCU6_T12DTC_DTR2_Msk (0x4000UL)
7345 #define CCU6_T12MSEL_MSEL60_Pos (0UL)
7346 #define CCU6_T12MSEL_MSEL60_Msk (0xfUL)
7347 #define CCU6_T12MSEL_MSEL61_Pos (4UL)
7348 #define CCU6_T12MSEL_MSEL61_Msk (0xf0UL)
7349 #define CCU6_T12MSEL_MSEL62_Pos (8UL)
7350 #define CCU6_T12MSEL_MSEL62_Msk (0xf00UL)
7351 #define CCU6_T12MSEL_HSYNC_Pos (12UL)
7352 #define CCU6_T12MSEL_HSYNC_Msk (0x7000UL)
7353 #define CCU6_T12MSEL_DBYP_Pos (15UL)
7354 #define CCU6_T12MSEL_DBYP_Msk (0x8000UL)
7356 #define CCU6_T12PR_T12PV_Pos (0UL)
7357 #define CCU6_T12PR_T12PV_Msk (0xffffUL)
7359 #define CCU6_T13_T13CV_Pos (0UL)
7360 #define CCU6_T13_T13CV_Msk (0xffffUL)
7362 #define CCU6_T13PR_T13PV_Pos (0UL)
7363 #define CCU6_T13PR_T13PV_Msk (0xffffUL)
7365 #define CCU6_TCTR0_T12CLK_Pos (0UL)
7366 #define CCU6_TCTR0_T12CLK_Msk (0x7UL)
7367 #define CCU6_TCTR0_T12PRE_Pos (3UL)
7368 #define CCU6_TCTR0_T12PRE_Msk (0x8UL)
7369 #define CCU6_TCTR0_T12R_Pos (4UL)
7370 #define CCU6_TCTR0_T12R_Msk (0x10UL)
7371 #define CCU6_TCTR0_STE12_Pos (5UL)
7372 #define CCU6_TCTR0_STE12_Msk (0x20UL)
7373 #define CCU6_TCTR0_CDIR_Pos (6UL)
7374 #define CCU6_TCTR0_CDIR_Msk (0x40UL)
7375 #define CCU6_TCTR0_CTM_Pos (7UL)
7376 #define CCU6_TCTR0_CTM_Msk (0x80UL)
7377 #define CCU6_TCTR0_T13CLK_Pos (8UL)
7378 #define CCU6_TCTR0_T13CLK_Msk (0x700UL)
7379 #define CCU6_TCTR0_T13PRE_Pos (11UL)
7380 #define CCU6_TCTR0_T13PRE_Msk (0x800UL)
7381 #define CCU6_TCTR0_T13R_Pos (12UL)
7382 #define CCU6_TCTR0_T13R_Msk (0x1000UL)
7383 #define CCU6_TCTR0_STE13_Pos (13UL)
7384 #define CCU6_TCTR0_STE13_Msk (0x2000UL)
7386 #define CCU6_TCTR2_T12SSC_Pos (0UL)
7387 #define CCU6_TCTR2_T12SSC_Msk (0x1UL)
7388 #define CCU6_TCTR2_T13SSC_Pos (1UL)
7389 #define CCU6_TCTR2_T13SSC_Msk (0x2UL)
7390 #define CCU6_TCTR2_T13TEC_Pos (2UL)
7391 #define CCU6_TCTR2_T13TEC_Msk (0x1cUL)
7392 #define CCU6_TCTR2_T13TED_Pos (5UL)
7393 #define CCU6_TCTR2_T13TED_Msk (0x60UL)
7394 #define CCU6_TCTR2_T12RSEL_Pos (8UL)
7395 #define CCU6_TCTR2_T12RSEL_Msk (0x300UL)
7396 #define CCU6_TCTR2_T13RSEL_Pos (10UL)
7397 #define CCU6_TCTR2_T13RSEL_Msk (0xc00UL)
7399 #define CCU6_TCTR4_T12RR_Pos (0UL)
7400 #define CCU6_TCTR4_T12RR_Msk (0x1UL)
7401 #define CCU6_TCTR4_T12RS_Pos (1UL)
7402 #define CCU6_TCTR4_T12RS_Msk (0x2UL)
7403 #define CCU6_TCTR4_T12RES_Pos (2UL)
7404 #define CCU6_TCTR4_T12RES_Msk (0x4UL)
7405 #define CCU6_TCTR4_DTRES_Pos (3UL)
7406 #define CCU6_TCTR4_DTRES_Msk (0x8UL)
7407 #define CCU6_TCTR4_T12CNT_Pos (5UL)
7408 #define CCU6_TCTR4_T12CNT_Msk (0x20UL)
7409 #define CCU6_TCTR4_T12STR_Pos (6UL)
7410 #define CCU6_TCTR4_T12STR_Msk (0x40UL)
7411 #define CCU6_TCTR4_T12STD_Pos (7UL)
7412 #define CCU6_TCTR4_T12STD_Msk (0x80UL)
7413 #define CCU6_TCTR4_T13RR_Pos (8UL)
7414 #define CCU6_TCTR4_T13RR_Msk (0x100UL)
7415 #define CCU6_TCTR4_T13RS_Pos (9UL)
7416 #define CCU6_TCTR4_T13RS_Msk (0x200UL)
7417 #define CCU6_TCTR4_T13RES_Pos (10UL)
7418 #define CCU6_TCTR4_T13RES_Msk (0x400UL)
7419 #define CCU6_TCTR4_T13CNT_Pos (13UL)
7420 #define CCU6_TCTR4_T13CNT_Msk (0x2000UL)
7421 #define CCU6_TCTR4_T13STR_Pos (14UL)
7422 #define CCU6_TCTR4_T13STR_Msk (0x4000UL)
7423 #define CCU6_TCTR4_T13STD_Pos (15UL)
7424 #define CCU6_TCTR4_T13STD_Msk (0x8000UL)
7426 #define CCU6_TRPCTR_TRPM0_Pos (0UL)
7427 #define CCU6_TRPCTR_TRPM0_Msk (0x1UL)
7428 #define CCU6_TRPCTR_TRPM1_Pos (1UL)
7429 #define CCU6_TRPCTR_TRPM1_Msk (0x2UL)
7430 #define CCU6_TRPCTR_TRPM2_Pos (2UL)
7431 #define CCU6_TRPCTR_TRPM2_Msk (0x4UL)
7432 #define CCU6_TRPCTR_TRPEN_Pos (8UL)
7433 #define CCU6_TRPCTR_TRPEN_Msk (0x3f00UL)
7434 #define CCU6_TRPCTR_TRPEN13_Pos (14UL)
7435 #define CCU6_TRPCTR_TRPEN13_Msk (0x4000UL)
7436 #define CCU6_TRPCTR_TRPPEN_Pos (15UL)
7437 #define CCU6_TRPCTR_TRPPEN_Msk (0x8000UL)
7445 #define CPU_AFSR_CP0_Pos (0UL)
7446 #define CPU_AFSR_CP0_Msk (0x3UL)
7447 #define CPU_AFSR_CP1_Pos (2UL)
7448 #define CPU_AFSR_CP1_Msk (0xcUL)
7449 #define CPU_AFSR_CP2_Pos (4UL)
7450 #define CPU_AFSR_CP2_Msk (0x30UL)
7451 #define CPU_AFSR_CP3_Pos (6UL)
7452 #define CPU_AFSR_CP3_Msk (0xc0UL)
7453 #define CPU_AFSR_CP4_Pos (8UL)
7454 #define CPU_AFSR_CP4_Msk (0x300UL)
7455 #define CPU_AFSR_CP5_Pos (10UL)
7456 #define CPU_AFSR_CP5_Msk (0xc00UL)
7457 #define CPU_AFSR_CP6_Pos (12UL)
7458 #define CPU_AFSR_CP6_Msk (0x3000UL)
7459 #define CPU_AFSR_CP7_Pos (14UL)
7460 #define CPU_AFSR_CP7_Msk (0xc000UL)
7461 #define CPU_AFSR_CP10_Pos (20UL)
7462 #define CPU_AFSR_CP10_Msk (0x300000UL)
7463 #define CPU_AFSR_CP11_Pos (22UL)
7464 #define CPU_AFSR_CP11_Msk (0xc00000UL)
7466 #define CPU_AIRCR_VECTKEY_Pos (16UL)
7467 #define CPU_AIRCR_VECTKEY_Msk (0xffff0000UL)
7468 #define CPU_AIRCR_ENDIANNESS_Pos (15UL)
7469 #define CPU_AIRCR_ENDIANNESS_Msk (0x8000UL)
7470 #define CPU_AIRCR_PRIGROUP_Pos (8UL)
7471 #define CPU_AIRCR_PRIGROUP_Msk (0x700UL)
7472 #define CPU_AIRCR_SYSRESETREQ_Pos (2UL)
7473 #define CPU_AIRCR_SYSRESETREQ_Msk (0x4UL)
7474 #define CPU_AIRCR_VECTCLRACTIVE_Pos (1UL)
7475 #define CPU_AIRCR_VECTCLRACTIVE_Msk (0x2UL)
7476 #define CPU_AIRCR_VECTRESET_Pos (0UL)
7477 #define CPU_AIRCR_VECTRESET_Msk (0x1UL)
7479 #define CPU_BFAR_ADDRESS_Pos (0UL)
7480 #define CPU_BFAR_ADDRESS_Msk (0xffffffffUL)
7482 #define CPU_CCR_STKALIGN_Pos (9UL)
7483 #define CPU_CCR_STKALIGN_Msk (0x200UL)
7484 #define CPU_CCR_BFHFMIGN_Pos (8UL)
7485 #define CPU_CCR_BFHFMIGN_Msk (0x100UL)
7486 #define CPU_CCR_DIV_0_TRP_Pos (4UL)
7487 #define CPU_CCR_DIV_0_TRP_Msk (0x10UL)
7488 #define CPU_CCR_UNALIGN_TRP_Pos (3UL)
7489 #define CPU_CCR_UNALIGN_TRP_Msk (0x8UL)
7490 #define CPU_CCR_USERSETMPEND_Pos (1UL)
7491 #define CPU_CCR_USERSETMPEND_Msk (0x2UL)
7492 #define CPU_CCR_NONBASETHRDENA_Pos (0UL)
7493 #define CPU_CCR_NONBASETHRDENA_Msk (0x1UL)
7495 #define CPU_CFSR_DIVBYZERO_Pos (25UL)
7496 #define CPU_CFSR_DIVBYZERO_Msk (0x2000000UL)
7497 #define CPU_CFSR_UNALIGNED_Pos (24UL)
7498 #define CPU_CFSR_UNALIGNED_Msk (0x1000000UL)
7499 #define CPU_CFSR_NOCP_Pos (19UL)
7500 #define CPU_CFSR_NOCP_Msk (0x80000UL)
7501 #define CPU_CFSR_INVPC_Pos (18UL)
7502 #define CPU_CFSR_INVPC_Msk (0x40000UL)
7503 #define CPU_CFSR_INVSTATE_Pos (17UL)
7504 #define CPU_CFSR_INVSTATE_Msk (0x20000UL)
7505 #define CPU_CFSR_UNDEFINSTR_Pos (16UL)
7506 #define CPU_CFSR_UNDEFINSTR_Msk (0x10000UL)
7507 #define CPU_CFSR_BFARVALID_Pos (15UL)
7508 #define CPU_CFSR_BFARVALID_Msk (0x8000UL)
7509 #define CPU_CFSR_STKERR_Pos (12UL)
7510 #define CPU_CFSR_STKERR_Msk (0x1000UL)
7511 #define CPU_CFSR_UNSTKERR_Pos (11UL)
7512 #define CPU_CFSR_UNSTKERR_Msk (0x800UL)
7513 #define CPU_CFSR_IMPRECISERR_Pos (10UL)
7514 #define CPU_CFSR_IMPRECISERR_Msk (0x400UL)
7515 #define CPU_CFSR_PRECISERR_Pos (9UL)
7516 #define CPU_CFSR_PRECISERR_Msk (0x200UL)
7517 #define CPU_CFSR_IBUSERR_Pos (8UL)
7518 #define CPU_CFSR_IBUSERR_Msk (0x100UL)
7519 #define CPU_CFSR_MMARVALID_Pos (7UL)
7520 #define CPU_CFSR_MMARVALID_Msk (0x80UL)
7521 #define CPU_CFSR_MSTERR_Pos (4UL)
7522 #define CPU_CFSR_MSTERR_Msk (0x10UL)
7523 #define CPU_CFSR_MUNSTKERR_Pos (3UL)
7524 #define CPU_CFSR_MUNSTKERR_Msk (0x8UL)
7525 #define CPU_CFSR_DACCVIOL_Pos (1UL)
7526 #define CPU_CFSR_DACCVIOL_Msk (0x2UL)
7527 #define CPU_CFSR_IACCVIOL_Pos (0UL)
7528 #define CPU_CFSR_IACCVIOL_Msk (0x1UL)
7530 #define CPU_CPUID_IMPLEMENTER_Pos (24UL)
7531 #define CPU_CPUID_IMPLEMENTER_Msk (0xff000000UL)
7532 #define CPU_CPUID_VARIANT_Pos (20UL)
7533 #define CPU_CPUID_VARIANT_Msk (0xf00000UL)
7534 #define CPU_CPUID_ARCHITECTURE_Pos (16UL)
7535 #define CPU_CPUID_ARCHITECTURE_Msk (0xf0000UL)
7536 #define CPU_CPUID_PARTNO_Pos (4UL)
7537 #define CPU_CPUID_PARTNO_Msk (0xfff0UL)
7538 #define CPU_CPUID_REVISION_Pos (0UL)
7539 #define CPU_CPUID_REVISION_Msk (0xfUL)
7541 #define CPU_DFSR_EXTERNAL_Pos (4UL)
7542 #define CPU_DFSR_EXTERNAL_Msk (0x10UL)
7543 #define CPU_DFSR_VCATCH_Pos (3UL)
7544 #define CPU_DFSR_VCATCH_Msk (0x8UL)
7545 #define CPU_DFSR_DWTTRAP_Pos (2UL)
7546 #define CPU_DFSR_DWTTRAP_Msk (0x4UL)
7547 #define CPU_DFSR_BKPT_Pos (1UL)
7548 #define CPU_DFSR_BKPT_Msk (0x2UL)
7549 #define CPU_DFSR_HALTED_Pos (0UL)
7550 #define CPU_DFSR_HALTED_Msk (0x1UL)
7552 #define CPU_HFSR_DEBUGEVT_Pos (31UL)
7553 #define CPU_HFSR_DEBUGEVT_Msk (0x80000000UL)
7554 #define CPU_HFSR_FORCED_Pos (30UL)
7555 #define CPU_HFSR_FORCED_Msk (0x40000000UL)
7556 #define CPU_HFSR_VECTTBL_Pos (1UL)
7557 #define CPU_HFSR_VECTTBL_Msk (0x2UL)
7559 #define CPU_ICSR_NMIPENDSET_Pos (31UL)
7560 #define CPU_ICSR_NMIPENDSET_Msk (0x80000000UL)
7561 #define CPU_ICSR_PENDSVSET_Pos (28UL)
7562 #define CPU_ICSR_PENDSVSET_Msk (0x10000000UL)
7563 #define CPU_ICSR_PENDSVCLR_Pos (27UL)
7564 #define CPU_ICSR_PENDSVCLR_Msk (0x8000000UL)
7565 #define CPU_ICSR_PENDSTSET_Pos (26UL)
7566 #define CPU_ICSR_PENDSTSET_Msk (0x4000000UL)
7567 #define CPU_ICSR_PENDSTCLR_Pos (25UL)
7568 #define CPU_ICSR_PENDSTCLR_Msk (0x2000000UL)
7569 #define CPU_ICSR_ISRPREEMPT_Pos (23UL)
7570 #define CPU_ICSR_ISRPREEMPT_Msk (0x800000UL)
7571 #define CPU_ICSR_ISRPENDING_Pos (22UL)
7572 #define CPU_ICSR_ISRPENDING_Msk (0x400000UL)
7573 #define CPU_ICSR_VECTPENDING_Pos (12UL)
7574 #define CPU_ICSR_VECTPENDING_Msk (0x1ff000UL)
7575 #define CPU_ICSR_RETTOBASE_Pos (11UL)
7576 #define CPU_ICSR_RETTOBASE_Msk (0x800UL)
7577 #define CPU_ICSR_VECTACTIVE_Pos (0UL)
7578 #define CPU_ICSR_VECTACTIVE_Msk (0x1ffUL)
7580 #define CPU_ICT_INTLINESNUM_Pos (0UL)
7581 #define CPU_ICT_INTLINESNUM_Msk (0x1fUL)
7583 #define CPU_MMFAR_ADDRESS_Pos (0UL)
7584 #define CPU_MMFAR_ADDRESS_Msk (0xffffffffUL)
7586 #define CPU_NVIC_IABR0_Int_DMA_Pos (15UL)
7587 #define CPU_NVIC_IABR0_Int_DMA_Msk (0x8000UL)
7588 #define CPU_NVIC_IABR0_Int_BDRV_Pos (14UL)
7589 #define CPU_NVIC_IABR0_Int_BDRV_Msk (0x4000UL)
7590 #define CPU_NVIC_IABR0_Int_EXINT1_Pos (13UL)
7591 #define CPU_NVIC_IABR0_Int_EXINT1_Msk (0x2000UL)
7592 #define CPU_NVIC_IABR0_Int_EXINT0_Pos (12UL)
7593 #define CPU_NVIC_IABR0_Int_EXINT0_Msk (0x1000UL)
7594 #define CPU_NVIC_IABR0_Int_UART2_Pos (11UL)
7595 #define CPU_NVIC_IABR0_Int_UART2_Msk (0x800UL)
7596 #define CPU_NVIC_IABR0_Int_UART1_Pos (10UL)
7597 #define CPU_NVIC_IABR0_Int_UART1_Msk (0x400UL)
7598 #define CPU_NVIC_IABR0_Int_SSC2_Pos (9UL)
7599 #define CPU_NVIC_IABR0_Int_SSC2_Msk (0x200UL)
7600 #define CPU_NVIC_IABR0_Int_SSC1_Pos (8UL)
7601 #define CPU_NVIC_IABR0_Int_SSC1_Msk (0x100UL)
7602 #define CPU_NVIC_IABR0_Int_CCU6SR3_Pos (7UL)
7603 #define CPU_NVIC_IABR0_Int_CCU6SR3_Msk (0x80UL)
7604 #define CPU_NVIC_IABR0_Int_CCU6SR2_Pos (6UL)
7605 #define CPU_NVIC_IABR0_Int_CCU6SR2_Msk (0x40UL)
7606 #define CPU_NVIC_IABR0_Int_CCU6SR1_Pos (5UL)
7607 #define CPU_NVIC_IABR0_Int_CCU6SR1_Msk (0x20UL)
7608 #define CPU_NVIC_IABR0_Int_CCU6SR0_Pos (4UL)
7609 #define CPU_NVIC_IABR0_Int_CCU6SR0_Msk (0x10UL)
7610 #define CPU_NVIC_IABR0_Int_ADC1_Pos (3UL)
7611 #define CPU_NVIC_IABR0_Int_ADC1_Msk (0x8UL)
7612 #define CPU_NVIC_IABR0_Int_ADC2_Pos (2UL)
7613 #define CPU_NVIC_IABR0_Int_ADC2_Msk (0x4UL)
7614 #define CPU_NVIC_IABR0_Int_GPT2_Pos (1UL)
7615 #define CPU_NVIC_IABR0_Int_GPT2_Msk (0x2UL)
7616 #define CPU_NVIC_IABR0_Int_GPT1_Pos (0UL)
7617 #define CPU_NVIC_IABR0_Int_GPT1_Msk (0x1UL)
7619 #define CPU_NVIC_ICER0_Int_DMA_Pos (15UL)
7620 #define CPU_NVIC_ICER0_Int_DMA_Msk (0x8000UL)
7621 #define CPU_NVIC_ICER0_Int_BDRV_Pos (14UL)
7622 #define CPU_NVIC_ICER0_Int_BDRV_Msk (0x4000UL)
7623 #define CPU_NVIC_ICER0_Int_EXINT1_Pos (13UL)
7624 #define CPU_NVIC_ICER0_Int_EXINT1_Msk (0x2000UL)
7625 #define CPU_NVIC_ICER0_Int_EXINT0_Pos (12UL)
7626 #define CPU_NVIC_ICER0_Int_EXINT0_Msk (0x1000UL)
7627 #define CPU_NVIC_ICER0_Int_UART2_Pos (11UL)
7628 #define CPU_NVIC_ICER0_Int_UART2_Msk (0x800UL)
7629 #define CPU_NVIC_ICER0_Int_UART1_Pos (10UL)
7630 #define CPU_NVIC_ICER0_Int_UART1_Msk (0x400UL)
7631 #define CPU_NVIC_ICER0_Int_SSC2_Pos (9UL)
7632 #define CPU_NVIC_ICER0_Int_SSC2_Msk (0x200UL)
7633 #define CPU_NVIC_ICER0_Int_SSC1_Pos (8UL)
7634 #define CPU_NVIC_ICER0_Int_SSC1_Msk (0x100UL)
7635 #define CPU_NVIC_ICER0_Int_CCU6SR3_Pos (7UL)
7636 #define CPU_NVIC_ICER0_Int_CCU6SR3_Msk (0x80UL)
7637 #define CPU_NVIC_ICER0_Int_CCU6SR2_Pos (6UL)
7638 #define CPU_NVIC_ICER0_Int_CCU6SR2_Msk (0x40UL)
7639 #define CPU_NVIC_ICER0_Int_CCU6SR1_Pos (5UL)
7640 #define CPU_NVIC_ICER0_Int_CCU6SR1_Msk (0x20UL)
7641 #define CPU_NVIC_ICER0_Int_CCU6SR0_Pos (4UL)
7642 #define CPU_NVIC_ICER0_Int_CCU6SR0_Msk (0x10UL)
7643 #define CPU_NVIC_ICER0_Int_ADC1_Pos (3UL)
7644 #define CPU_NVIC_ICER0_Int_ADC1_Msk (0x8UL)
7645 #define CPU_NVIC_ICER0_Int_ADC2_Pos (2UL)
7646 #define CPU_NVIC_ICER0_Int_ADC2_Msk (0x4UL)
7647 #define CPU_NVIC_ICER0_Int_GPT2_Pos (1UL)
7648 #define CPU_NVIC_ICER0_Int_GPT2_Msk (0x2UL)
7649 #define CPU_NVIC_ICER0_Int_GPT1_Pos (0UL)
7650 #define CPU_NVIC_ICER0_Int_GPT1_Msk (0x1UL)
7652 #define CPU_NVIC_ICPR0_Int_DMA_Pos (15UL)
7653 #define CPU_NVIC_ICPR0_Int_DMA_Msk (0x8000UL)
7654 #define CPU_NVIC_ICPR0_Int_BDRV_Pos (14UL)
7655 #define CPU_NVIC_ICPR0_Int_BDRV_Msk (0x4000UL)
7656 #define CPU_NVIC_ICPR0_Int_EXINT1_Pos (13UL)
7657 #define CPU_NVIC_ICPR0_Int_EXINT1_Msk (0x2000UL)
7658 #define CPU_NVIC_ICPR0_Int_EXINT0_Pos (12UL)
7659 #define CPU_NVIC_ICPR0_Int_EXINT0_Msk (0x1000UL)
7660 #define CPU_NVIC_ICPR0_Int_UART2_Pos (11UL)
7661 #define CPU_NVIC_ICPR0_Int_UART2_Msk (0x800UL)
7662 #define CPU_NVIC_ICPR0_Int_UART1_Pos (10UL)
7663 #define CPU_NVIC_ICPR0_Int_UART1_Msk (0x400UL)
7664 #define CPU_NVIC_ICPR0_Int_SSC2_Pos (9UL)
7665 #define CPU_NVIC_ICPR0_Int_SSC2_Msk (0x200UL)
7666 #define CPU_NVIC_ICPR0_Int_SSC1_Pos (8UL)
7667 #define CPU_NVIC_ICPR0_Int_SSC1_Msk (0x100UL)
7668 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Pos (7UL)
7669 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Msk (0x80UL)
7670 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Pos (6UL)
7671 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Msk (0x40UL)
7672 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Pos (5UL)
7673 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Msk (0x20UL)
7674 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Pos (4UL)
7675 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Msk (0x10UL)
7676 #define CPU_NVIC_ICPR0_Int_ADC1_Pos (3UL)
7677 #define CPU_NVIC_ICPR0_Int_ADC1_Msk (0x8UL)
7678 #define CPU_NVIC_ICPR0_Int_ADC2_Pos (2UL)
7679 #define CPU_NVIC_ICPR0_Int_ADC2_Msk (0x4UL)
7680 #define CPU_NVIC_ICPR0_Int_GPT2_Pos (1UL)
7681 #define CPU_NVIC_ICPR0_Int_GPT2_Msk (0x2UL)
7682 #define CPU_NVIC_ICPR0_Int_GPT1_Pos (0UL)
7683 #define CPU_NVIC_ICPR0_Int_GPT1_Msk (0x1UL)
7685 #define CPU_NVIC_IPR0_PRI_ADC1_Pos (24UL)
7686 #define CPU_NVIC_IPR0_PRI_ADC1_Msk (0xff000000UL)
7687 #define CPU_NVIC_IPR0_PRI_ADC2_Pos (16UL)
7688 #define CPU_NVIC_IPR0_PRI_ADC2_Msk (0xff0000UL)
7689 #define CPU_NVIC_IPR0_PRI_GPT2_Pos (8UL)
7690 #define CPU_NVIC_IPR0_PRI_GPT2_Msk (0xff00UL)
7691 #define CPU_NVIC_IPR0_PRI_GPT1_Pos (0UL)
7692 #define CPU_NVIC_IPR0_PRI_GPT1_Msk (0xffUL)
7694 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Pos (24UL)
7695 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Msk (0xff000000UL)
7696 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Pos (16UL)
7697 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Msk (0xff0000UL)
7698 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Pos (8UL)
7699 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Msk (0xff00UL)
7700 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Pos (0UL)
7701 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Msk (0xffUL)
7703 #define CPU_NVIC_IPR2_PRI_UART2_Pos (24UL)
7704 #define CPU_NVIC_IPR2_PRI_UART2_Msk (0xff000000UL)
7705 #define CPU_NVIC_IPR2_PRI_UART1_Pos (16UL)
7706 #define CPU_NVIC_IPR2_PRI_UART1_Msk (0xff0000UL)
7707 #define CPU_NVIC_IPR2_PRI_SSC2_Pos (8UL)
7708 #define CPU_NVIC_IPR2_PRI_SSC2_Msk (0xff00UL)
7709 #define CPU_NVIC_IPR2_PRI_SSC1_Pos (0UL)
7710 #define CPU_NVIC_IPR2_PRI_SSC1_Msk (0xffUL)
7712 #define CPU_NVIC_IPR3_PRI_DMA_Pos (24UL)
7713 #define CPU_NVIC_IPR3_PRI_DMA_Msk (0xff000000UL)
7714 #define CPU_NVIC_IPR3_PRI_BDRV_Pos (16UL)
7715 #define CPU_NVIC_IPR3_PRI_BDRV_Msk (0xff0000UL)
7716 #define CPU_NVIC_IPR3_PRI_EXINT1_Pos (8UL)
7717 #define CPU_NVIC_IPR3_PRI_EXINT1_Msk (0xff00UL)
7718 #define CPU_NVIC_IPR3_PRI_EXINT0_Pos (0UL)
7719 #define CPU_NVIC_IPR3_PRI_EXINT0_Msk (0xffUL)
7721 #define CPU_NVIC_ISER0_Int_DMA_Pos (15UL)
7722 #define CPU_NVIC_ISER0_Int_DMA_Msk (0x8000UL)
7723 #define CPU_NVIC_ISER0_Int_BDRV_Pos (14UL)
7724 #define CPU_NVIC_ISER0_Int_BDRV_Msk (0x4000UL)
7725 #define CPU_NVIC_ISER0_Int_EXINT1_Pos (13UL)
7726 #define CPU_NVIC_ISER0_Int_EXINT1_Msk (0x2000UL)
7727 #define CPU_NVIC_ISER0_Int_EXINT0_Pos (12UL)
7728 #define CPU_NVIC_ISER0_Int_EXINT0_Msk (0x1000UL)
7729 #define CPU_NVIC_ISER0_Int_UART2_Pos (11UL)
7730 #define CPU_NVIC_ISER0_Int_UART2_Msk (0x800UL)
7731 #define CPU_NVIC_ISER0_Int_UART1_Pos (10UL)
7732 #define CPU_NVIC_ISER0_Int_UART1_Msk (0x400UL)
7733 #define CPU_NVIC_ISER0_Int_SSC2_Pos (9UL)
7734 #define CPU_NVIC_ISER0_Int_SSC2_Msk (0x200UL)
7735 #define CPU_NVIC_ISER0_Int_SSC1_Pos (8UL)
7736 #define CPU_NVIC_ISER0_Int_SSC1_Msk (0x100UL)
7737 #define CPU_NVIC_ISER0_Int_CCU6SR3_Pos (7UL)
7738 #define CPU_NVIC_ISER0_Int_CCU6SR3_Msk (0x80UL)
7739 #define CPU_NVIC_ISER0_Int_CCU6SR2_Pos (6UL)
7740 #define CPU_NVIC_ISER0_Int_CCU6SR2_Msk (0x40UL)
7741 #define CPU_NVIC_ISER0_Int_CCU6SR1_Pos (5UL)
7742 #define CPU_NVIC_ISER0_Int_CCU6SR1_Msk (0x20UL)
7743 #define CPU_NVIC_ISER0_Int_CCU6SR0_Pos (4UL)
7744 #define CPU_NVIC_ISER0_Int_CCU6SR0_Msk (0x10UL)
7745 #define CPU_NVIC_ISER0_Int_ADC1_Pos (3UL)
7746 #define CPU_NVIC_ISER0_Int_ADC1_Msk (0x8UL)
7747 #define CPU_NVIC_ISER0_Int_ADC2_Pos (2UL)
7748 #define CPU_NVIC_ISER0_Int_ADC2_Msk (0x4UL)
7749 #define CPU_NVIC_ISER0_Int_GPT2_Pos (1UL)
7750 #define CPU_NVIC_ISER0_Int_GPT2_Msk (0x2UL)
7751 #define CPU_NVIC_ISER0_Int_GPT1_Pos (0UL)
7752 #define CPU_NVIC_ISER0_Int_GPT1_Msk (0x1UL)
7754 #define CPU_NVIC_ISPR0_Int_DMA_Pos (15UL)
7755 #define CPU_NVIC_ISPR0_Int_DMA_Msk (0x8000UL)
7756 #define CPU_NVIC_ISPR0_Int_BDRV_Pos (14UL)
7757 #define CPU_NVIC_ISPR0_Int_BDRV_Msk (0x4000UL)
7758 #define CPU_NVIC_ISPR0_Int_EXINT1_Pos (13UL)
7759 #define CPU_NVIC_ISPR0_Int_EXINT1_Msk (0x2000UL)
7760 #define CPU_NVIC_ISPR0_Int_EXINT0_Pos (12UL)
7761 #define CPU_NVIC_ISPR0_Int_EXINT0_Msk (0x1000UL)
7762 #define CPU_NVIC_ISPR0_Int_UART2_Pos (11UL)
7763 #define CPU_NVIC_ISPR0_Int_UART2_Msk (0x800UL)
7764 #define CPU_NVIC_ISPR0_Int_UART1_Pos (10UL)
7765 #define CPU_NVIC_ISPR0_Int_UART1_Msk (0x400UL)
7766 #define CPU_NVIC_ISPR0_Int_SSC2_Pos (9UL)
7767 #define CPU_NVIC_ISPR0_Int_SSC2_Msk (0x200UL)
7768 #define CPU_NVIC_ISPR0_Int_SSC1_Pos (8UL)
7769 #define CPU_NVIC_ISPR0_Int_SSC1_Msk (0x100UL)
7770 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Pos (7UL)
7771 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Msk (0x80UL)
7772 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Pos (6UL)
7773 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Msk (0x40UL)
7774 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Pos (5UL)
7775 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Msk (0x20UL)
7776 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Pos (4UL)
7777 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Msk (0x10UL)
7778 #define CPU_NVIC_ISPR0_Int_ADC1_Pos (3UL)
7779 #define CPU_NVIC_ISPR0_Int_ADC1_Msk (0x8UL)
7780 #define CPU_NVIC_ISPR0_Int_ADC2_Pos (2UL)
7781 #define CPU_NVIC_ISPR0_Int_ADC2_Msk (0x4UL)
7782 #define CPU_NVIC_ISPR0_Int_GPT2_Pos (1UL)
7783 #define CPU_NVIC_ISPR0_Int_GPT2_Msk (0x2UL)
7784 #define CPU_NVIC_ISPR0_Int_GPT1_Pos (0UL)
7785 #define CPU_NVIC_ISPR0_Int_GPT1_Msk (0x1UL)
7787 #define CPU_SCR_SEVONPEND_Pos (4UL)
7788 #define CPU_SCR_SEVONPEND_Msk (0x10UL)
7789 #define CPU_SCR_SLEEPDEEP_Pos (2UL)
7790 #define CPU_SCR_SLEEPDEEP_Msk (0x4UL)
7791 #define CPU_SCR_SLEEPONEXIT_Pos (1UL)
7792 #define CPU_SCR_SLEEPONEXIT_Msk (0x2UL)
7794 #define CPU_SHCSR_USGFAULTENA_Pos (18UL)
7795 #define CPU_SHCSR_USGFAULTENA_Msk (0x40000UL)
7796 #define CPU_SHCSR_BUSFAULTENA_Pos (17UL)
7797 #define CPU_SHCSR_BUSFAULTENA_Msk (0x20000UL)
7798 #define CPU_SHCSR_MEMFAULTENA_Pos (16UL)
7799 #define CPU_SHCSR_MEMFAULTENA_Msk (0x10000UL)
7800 #define CPU_SHCSR_SVCALLPENDED_Pos (15UL)
7801 #define CPU_SHCSR_SVCALLPENDED_Msk (0x8000UL)
7802 #define CPU_SHCSR_BUSFAULTPENDED_Pos (14UL)
7803 #define CPU_SHCSR_BUSFAULTPENDED_Msk (0x4000UL)
7804 #define CPU_SHCSR_MEMFAULTPENDED_Pos (13UL)
7805 #define CPU_SHCSR_MEMFAULTPENDED_Msk (0x2000UL)
7806 #define CPU_SHCSR_USGFAULTPENDED_Pos (12UL)
7807 #define CPU_SHCSR_USGFAULTPENDED_Msk (0x1000UL)
7808 #define CPU_SHCSR_SYSTICKACT_Pos (11UL)
7809 #define CPU_SHCSR_SYSTICKACT_Msk (0x800UL)
7810 #define CPU_SHCSR_PENDSVACT_Pos (10UL)
7811 #define CPU_SHCSR_PENDSVACT_Msk (0x400UL)
7812 #define CPU_SHCSR_MONITORACT_Pos (8UL)
7813 #define CPU_SHCSR_MONITORACT_Msk (0x100UL)
7814 #define CPU_SHCSR_SVCALLACT_Pos (7UL)
7815 #define CPU_SHCSR_SVCALLACT_Msk (0x80UL)
7816 #define CPU_SHCSR_USGFAULTACT_Pos (3UL)
7817 #define CPU_SHCSR_USGFAULTACT_Msk (0x8UL)
7818 #define CPU_SHCSR_BUSFAULTACT_Pos (1UL)
7819 #define CPU_SHCSR_BUSFAULTACT_Msk (0x2UL)
7820 #define CPU_SHCSR_MEMFAULTACT_Pos (0UL)
7821 #define CPU_SHCSR_MEMFAULTACT_Msk (0x1UL)
7823 #define CPU_SHPR1_PRI_7_Pos (24UL)
7824 #define CPU_SHPR1_PRI_7_Msk (0xff000000UL)
7825 #define CPU_SHPR1_PRI_6_Pos (16UL)
7826 #define CPU_SHPR1_PRI_6_Msk (0xff0000UL)
7827 #define CPU_SHPR1_PRI_5_Pos (8UL)
7828 #define CPU_SHPR1_PRI_5_Msk (0xff00UL)
7829 #define CPU_SHPR1_PRI_4_Pos (0UL)
7830 #define CPU_SHPR1_PRI_4_Msk (0xffUL)
7832 #define CPU_SHPR2_PRI_11_Pos (24UL)
7833 #define CPU_SHPR2_PRI_11_Msk (0xff000000UL)
7834 #define CPU_SHPR2_PRI_10_Pos (16UL)
7835 #define CPU_SHPR2_PRI_10_Msk (0xff0000UL)
7836 #define CPU_SHPR2_PRI_9_Pos (8UL)
7837 #define CPU_SHPR2_PRI_9_Msk (0xff00UL)
7838 #define CPU_SHPR2_PRI_8_Pos (0UL)
7839 #define CPU_SHPR2_PRI_8_Msk (0xffUL)
7841 #define CPU_SHPR3_PRI_15_Pos (24UL)
7842 #define CPU_SHPR3_PRI_15_Msk (0xff000000UL)
7843 #define CPU_SHPR3_PRI_14_Pos (16UL)
7844 #define CPU_SHPR3_PRI_14_Msk (0xff0000UL)
7845 #define CPU_SHPR3_PRI_13_Pos (8UL)
7846 #define CPU_SHPR3_PRI_13_Msk (0xff00UL)
7847 #define CPU_SHPR3_PRI_12_Pos (0UL)
7848 #define CPU_SHPR3_PRI_12_Msk (0xffUL)
7850 #define CPU_SYSTICK_CAL_NOREF_Pos (31UL)
7851 #define CPU_SYSTICK_CAL_NOREF_Msk (0x80000000UL)
7852 #define CPU_SYSTICK_CAL_SKEW_Pos (30UL)
7853 #define CPU_SYSTICK_CAL_SKEW_Msk (0x40000000UL)
7854 #define CPU_SYSTICK_CAL_TENMS_Pos (0UL)
7855 #define CPU_SYSTICK_CAL_TENMS_Msk (0xffffffUL)
7857 #define CPU_SYSTICK_CS_COUNTFLAG_Pos (16UL)
7858 #define CPU_SYSTICK_CS_COUNTFLAG_Msk (0x10000UL)
7859 #define CPU_SYSTICK_CS_CLKSOURCE_Pos (2UL)
7860 #define CPU_SYSTICK_CS_CLKSOURCE_Msk (0x4UL)
7861 #define CPU_SYSTICK_CS_TICKINT_Pos (1UL)
7862 #define CPU_SYSTICK_CS_TICKINT_Msk (0x2UL)
7863 #define CPU_SYSTICK_CS_ENABLE_Pos (0UL)
7864 #define CPU_SYSTICK_CS_ENABLE_Msk (0x1UL)
7866 #define CPU_SYSTICK_CUR_CURRENT_Pos (0UL)
7867 #define CPU_SYSTICK_CUR_CURRENT_Msk (0xffffffUL)
7869 #define CPU_SYSTICK_RL_RELOAD_Pos (0UL)
7870 #define CPU_SYSTICK_RL_RELOAD_Msk (0xffffffUL)
7872 #define CPU_VTOR_TBLOFF_Pos (7UL)
7873 #define CPU_VTOR_TBLOFF_Msk (0xffffff80UL)
7881 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Pos (0UL)
7882 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Msk (0xffffffffUL)
7884 #define DMA_CFG_CHN1_PROT_CTRL_Pos (5UL)
7885 #define DMA_CFG_CHN1_PROT_CTRL_Msk (0xe0UL)
7886 #define DMA_CFG_MASTER_ENABLE_Pos (0UL)
7887 #define DMA_CFG_MASTER_ENABLE_Msk (0x1UL)
7889 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Pos (0UL)
7890 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Msk (0x3fffUL)
7892 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos (0UL)
7893 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk (0x3fffUL)
7895 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos (0UL)
7896 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk (0x3fffUL)
7898 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos (0UL)
7899 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk (0x3fffUL)
7901 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Pos (0UL)
7902 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Msk (0x3fffUL)
7904 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Pos (0UL)
7905 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Msk (0x3fffUL)
7907 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Pos (0UL)
7908 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Msk (0x3fffUL)
7910 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Pos (0UL)
7911 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Msk (0x3fffUL)
7913 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos (0UL)
7914 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk (0x3fffUL)
7916 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Pos (0UL)
7917 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Msk (0x3fffUL)
7919 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Pos (0UL)
7920 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Msk (0x3fffUL)
7922 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos (9UL)
7923 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk (0xfffffe00UL)
7925 #define DMA_ERR_CLR_ERR_CLR_Pos (0UL)
7926 #define DMA_ERR_CLR_ERR_CLR_Msk (0x1UL)
7928 #define DMA_STATUS_CHNLS_MINUS1_Pos (16UL)
7929 #define DMA_STATUS_CHNLS_MINUS1_Msk (0x1f0000UL)
7930 #define DMA_STATUS_STATE_Pos (4UL)
7931 #define DMA_STATUS_STATE_Msk (0xf0UL)
7932 #define DMA_STATUS_MASTER_ENABLE_Pos (0UL)
7933 #define DMA_STATUS_MASTER_ENABLE_Msk (0x1UL)
7935 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Pos (0UL)
7936 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Msk (0x3fffUL)
7944 #define GPT12E_CAPREL_CAPREL_Pos (0UL)
7945 #define GPT12E_CAPREL_CAPREL_Msk (0xffffUL)
7947 #define GPT12E_ID_MOD_REV_Pos (0UL)
7948 #define GPT12E_ID_MOD_REV_Msk (0xffUL)
7949 #define GPT12E_ID_MOD_TYPE_Pos (8UL)
7950 #define GPT12E_ID_MOD_TYPE_Msk (0xff00UL)
7952 #define GPT12E_PISEL_IST2IN_Pos (0UL)
7953 #define GPT12E_PISEL_IST2IN_Msk (0x1UL)
7954 #define GPT12E_PISEL_IST2EUD_Pos (1UL)
7955 #define GPT12E_PISEL_IST2EUD_Msk (0x2UL)
7956 #define GPT12E_PISEL_IST3IN_Pos (2UL)
7957 #define GPT12E_PISEL_IST3IN_Msk (0xcUL)
7958 #define GPT12E_PISEL_IST3EUD_Pos (4UL)
7959 #define GPT12E_PISEL_IST3EUD_Msk (0x30UL)
7960 #define GPT12E_PISEL_IST4IN_Pos (6UL)
7961 #define GPT12E_PISEL_IST4IN_Msk (0xc0UL)
7962 #define GPT12E_PISEL_IST4EUD_Pos (8UL)
7963 #define GPT12E_PISEL_IST4EUD_Msk (0x300UL)
7964 #define GPT12E_PISEL_IST5IN_Pos (10UL)
7965 #define GPT12E_PISEL_IST5IN_Msk (0x400UL)
7966 #define GPT12E_PISEL_IST5EUD_Pos (11UL)
7967 #define GPT12E_PISEL_IST5EUD_Msk (0x800UL)
7968 #define GPT12E_PISEL_IST6IN_Pos (12UL)
7969 #define GPT12E_PISEL_IST6IN_Msk (0x1000UL)
7970 #define GPT12E_PISEL_IST6EUD_Pos (13UL)
7971 #define GPT12E_PISEL_IST6EUD_Msk (0x2000UL)
7972 #define GPT12E_PISEL_ISCAPIN_Pos (14UL)
7973 #define GPT12E_PISEL_ISCAPIN_Msk (0xc000UL)
7975 #define GPT12E_T2_T2_Pos (0UL)
7976 #define GPT12E_T2_T2_Msk (0xffffUL)
7978 #define GPT12E_T2CON_T2I_Pos (0UL)
7979 #define GPT12E_T2CON_T2I_Msk (0x7UL)
7980 #define GPT12E_T2CON_T2M_Pos (3UL)
7981 #define GPT12E_T2CON_T2M_Msk (0x38UL)
7982 #define GPT12E_T2CON_T2R_Pos (6UL)
7983 #define GPT12E_T2CON_T2R_Msk (0x40UL)
7984 #define GPT12E_T2CON_T2UD_Pos (7UL)
7985 #define GPT12E_T2CON_T2UD_Msk (0x80UL)
7986 #define GPT12E_T2CON_T2UDE_Pos (8UL)
7987 #define GPT12E_T2CON_T2UDE_Msk (0x100UL)
7988 #define GPT12E_T2CON_T2RC_Pos (9UL)
7989 #define GPT12E_T2CON_T2RC_Msk (0x200UL)
7990 #define GPT12E_T2CON_T2IRDIS_Pos (12UL)
7991 #define GPT12E_T2CON_T2IRDIS_Msk (0x1000UL)
7992 #define GPT12E_T2CON_T2EDGE_Pos (13UL)
7993 #define GPT12E_T2CON_T2EDGE_Msk (0x2000UL)
7994 #define GPT12E_T2CON_T2CHDIR_Pos (14UL)
7995 #define GPT12E_T2CON_T2CHDIR_Msk (0x4000UL)
7996 #define GPT12E_T2CON_T2RDIR_Pos (15UL)
7997 #define GPT12E_T2CON_T2RDIR_Msk (0x8000UL)
7999 #define GPT12E_T3_T3_Pos (0UL)
8000 #define GPT12E_T3_T3_Msk (0xffffUL)
8002 #define GPT12E_T3CON_T3I_Pos (0UL)
8003 #define GPT12E_T3CON_T3I_Msk (0x7UL)
8004 #define GPT12E_T3CON_T3M_Pos (3UL)
8005 #define GPT12E_T3CON_T3M_Msk (0x38UL)
8006 #define GPT12E_T3CON_T3R_Pos (6UL)
8007 #define GPT12E_T3CON_T3R_Msk (0x40UL)
8008 #define GPT12E_T3CON_T3UD_Pos (7UL)
8009 #define GPT12E_T3CON_T3UD_Msk (0x80UL)
8010 #define GPT12E_T3CON_T3UDE_Pos (8UL)
8011 #define GPT12E_T3CON_T3UDE_Msk (0x100UL)
8012 #define GPT12E_T3CON_T3OE_Pos (9UL)
8013 #define GPT12E_T3CON_T3OE_Msk (0x200UL)
8014 #define GPT12E_T3CON_T3OTL_Pos (10UL)
8015 #define GPT12E_T3CON_T3OTL_Msk (0x400UL)
8016 #define GPT12E_T3CON_BPS1_Pos (11UL)
8017 #define GPT12E_T3CON_BPS1_Msk (0x1800UL)
8018 #define GPT12E_T3CON_T3EDGE_Pos (13UL)
8019 #define GPT12E_T3CON_T3EDGE_Msk (0x2000UL)
8020 #define GPT12E_T3CON_T3CHDIR_Pos (14UL)
8021 #define GPT12E_T3CON_T3CHDIR_Msk (0x4000UL)
8022 #define GPT12E_T3CON_T3RDIR_Pos (15UL)
8023 #define GPT12E_T3CON_T3RDIR_Msk (0x8000UL)
8025 #define GPT12E_T4_T4_Pos (0UL)
8026 #define GPT12E_T4_T4_Msk (0xffffUL)
8028 #define GPT12E_T4CON_T4I_Pos (0UL)
8029 #define GPT12E_T4CON_T4I_Msk (0x7UL)
8030 #define GPT12E_T4CON_T4M_Pos (3UL)
8031 #define GPT12E_T4CON_T4M_Msk (0x38UL)
8032 #define GPT12E_T4CON_T4R_Pos (6UL)
8033 #define GPT12E_T4CON_T4R_Msk (0x40UL)
8034 #define GPT12E_T4CON_T4UD_Pos (7UL)
8035 #define GPT12E_T4CON_T4UD_Msk (0x80UL)
8036 #define GPT12E_T4CON_T4UDE_Pos (8UL)
8037 #define GPT12E_T4CON_T4UDE_Msk (0x100UL)
8038 #define GPT12E_T4CON_T4RC_Pos (9UL)
8039 #define GPT12E_T4CON_T4RC_Msk (0x200UL)
8040 #define GPT12E_T4CON_CLRT2EN_Pos (10UL)
8041 #define GPT12E_T4CON_CLRT2EN_Msk (0x400UL)
8042 #define GPT12E_T4CON_CLRT3EN_Pos (11UL)
8043 #define GPT12E_T4CON_CLRT3EN_Msk (0x800UL)
8044 #define GPT12E_T4CON_T4IRDIS_Pos (12UL)
8045 #define GPT12E_T4CON_T4IRDIS_Msk (0x1000UL)
8046 #define GPT12E_T4CON_T4EDGE_Pos (13UL)
8047 #define GPT12E_T4CON_T4EDGE_Msk (0x2000UL)
8048 #define GPT12E_T4CON_T4CHDIR_Pos (14UL)
8049 #define GPT12E_T4CON_T4CHDIR_Msk (0x4000UL)
8050 #define GPT12E_T4CON_T4RDIR_Pos (15UL)
8051 #define GPT12E_T4CON_T4RDIR_Msk (0x8000UL)
8053 #define GPT12E_T5_T5_Pos (0UL)
8054 #define GPT12E_T5_T5_Msk (0xffffUL)
8056 #define GPT12E_T5CON_T5I_Pos (0UL)
8057 #define GPT12E_T5CON_T5I_Msk (0x7UL)
8058 #define GPT12E_T5CON_T5M_Pos (3UL)
8059 #define GPT12E_T5CON_T5M_Msk (0x18UL)
8060 #define GPT12E_T5CON_T5R_Pos (6UL)
8061 #define GPT12E_T5CON_T5R_Msk (0x40UL)
8062 #define GPT12E_T5CON_T5UD_Pos (7UL)
8063 #define GPT12E_T5CON_T5UD_Msk (0x80UL)
8064 #define GPT12E_T5CON_T5UDE_Pos (8UL)
8065 #define GPT12E_T5CON_T5UDE_Msk (0x100UL)
8066 #define GPT12E_T5CON_T5RC_Pos (9UL)
8067 #define GPT12E_T5CON_T5RC_Msk (0x200UL)
8068 #define GPT12E_T5CON_CT3_Pos (10UL)
8069 #define GPT12E_T5CON_CT3_Msk (0x400UL)
8070 #define GPT12E_T5CON_CI_Pos (12UL)
8071 #define GPT12E_T5CON_CI_Msk (0x3000UL)
8072 #define GPT12E_T5CON_T5CLR_Pos (14UL)
8073 #define GPT12E_T5CON_T5CLR_Msk (0x4000UL)
8074 #define GPT12E_T5CON_T5SC_Pos (15UL)
8075 #define GPT12E_T5CON_T5SC_Msk (0x8000UL)
8077 #define GPT12E_T6_T6_Pos (0UL)
8078 #define GPT12E_T6_T6_Msk (0xffffUL)
8080 #define GPT12E_T6CON_T6I_Pos (0UL)
8081 #define GPT12E_T6CON_T6I_Msk (0x7UL)
8082 #define GPT12E_T6CON_T6M_Pos (3UL)
8083 #define GPT12E_T6CON_T6M_Msk (0x38UL)
8084 #define GPT12E_T6CON_T6R_Pos (6UL)
8085 #define GPT12E_T6CON_T6R_Msk (0x40UL)
8086 #define GPT12E_T6CON_T6UD_Pos (7UL)
8087 #define GPT12E_T6CON_T6UD_Msk (0x80UL)
8088 #define GPT12E_T6CON_T6UDE_Pos (8UL)
8089 #define GPT12E_T6CON_T6UDE_Msk (0x100UL)
8090 #define GPT12E_T6CON_T6OE_Pos (9UL)
8091 #define GPT12E_T6CON_T6OE_Msk (0x200UL)
8092 #define GPT12E_T6CON_T6OTL_Pos (10UL)
8093 #define GPT12E_T6CON_T6OTL_Msk (0x400UL)
8094 #define GPT12E_T6CON_BPS2_Pos (11UL)
8095 #define GPT12E_T6CON_BPS2_Msk (0x1800UL)
8096 #define GPT12E_T6CON_T6CLR_Pos (14UL)
8097 #define GPT12E_T6CON_T6CLR_Msk (0x4000UL)
8098 #define GPT12E_T6CON_T6SR_Pos (15UL)
8099 #define GPT12E_T6CON_T6SR_Msk (0x8000UL)
8107 #define LIN_CTRL_STS_M_SM_ERR_CLR_Pos (24UL)
8108 #define LIN_CTRL_STS_M_SM_ERR_CLR_Msk (0x1000000UL)
8109 #define LIN_CTRL_STS_HV_MODE_Pos (21UL)
8110 #define LIN_CTRL_STS_HV_MODE_Msk (0x200000UL)
8111 #define LIN_CTRL_STS_MODE_FB_Pos (16UL)
8112 #define LIN_CTRL_STS_MODE_FB_Msk (0x70000UL)
8113 #define LIN_CTRL_STS_FB_SM3_Pos (15UL)
8114 #define LIN_CTRL_STS_FB_SM3_Msk (0x8000UL)
8115 #define LIN_CTRL_STS_FB_SM2_Pos (14UL)
8116 #define LIN_CTRL_STS_FB_SM2_Msk (0x4000UL)
8117 #define LIN_CTRL_STS_FB_SM1_Pos (13UL)
8118 #define LIN_CTRL_STS_FB_SM1_Msk (0x2000UL)
8119 #define LIN_CTRL_STS_SM_Pos (11UL)
8120 #define LIN_CTRL_STS_SM_Msk (0x1800UL)
8121 #define LIN_CTRL_STS_RXD_Pos (10UL)
8122 #define LIN_CTRL_STS_RXD_Msk (0x400UL)
8123 #define LIN_CTRL_STS_TXD_Pos (9UL)
8124 #define LIN_CTRL_STS_TXD_Msk (0x200UL)
8125 #define LIN_CTRL_STS_TXD_TMOUT_STS_Pos (6UL)
8126 #define LIN_CTRL_STS_TXD_TMOUT_STS_Msk (0x40UL)
8127 #define LIN_CTRL_STS_OC_STS_Pos (5UL)
8128 #define LIN_CTRL_STS_OC_STS_Msk (0x20UL)
8129 #define LIN_CTRL_STS_OT_STS_Pos (4UL)
8130 #define LIN_CTRL_STS_OT_STS_Msk (0x10UL)
8131 #define LIN_CTRL_STS_M_SM_ERR_Pos (3UL)
8132 #define LIN_CTRL_STS_M_SM_ERR_Msk (0x8UL)
8133 #define LIN_CTRL_STS_MODE_Pos (1UL)
8134 #define LIN_CTRL_STS_MODE_Msk (0x6UL)
8142 #define MF_BEMFC_CTRL_STS_PHW_ZC_STS_Pos (18UL)
8143 #define MF_BEMFC_CTRL_STS_PHW_ZC_STS_Msk (0x40000UL)
8144 #define MF_BEMFC_CTRL_STS_PHV_ZC_STS_Pos (17UL)
8145 #define MF_BEMFC_CTRL_STS_PHV_ZC_STS_Msk (0x20000UL)
8146 #define MF_BEMFC_CTRL_STS_PHU_ZC_STS_Pos (16UL)
8147 #define MF_BEMFC_CTRL_STS_PHU_ZC_STS_Msk (0x10000UL)
8148 #define MF_BEMFC_CTRL_STS_CCPOS_INSEL_Pos (12UL)
8149 #define MF_BEMFC_CTRL_STS_CCPOS_INSEL_Msk (0x1000UL)
8150 #define MF_BEMFC_CTRL_STS_PHWCOMP_ON_Pos (10UL)
8151 #define MF_BEMFC_CTRL_STS_PHWCOMP_ON_Msk (0x400UL)
8152 #define MF_BEMFC_CTRL_STS_PHVCOMP_ON_Pos (9UL)
8153 #define MF_BEMFC_CTRL_STS_PHVCOMP_ON_Msk (0x200UL)
8154 #define MF_BEMFC_CTRL_STS_PHUCOMP_ON_Pos (8UL)
8155 #define MF_BEMFC_CTRL_STS_PHUCOMP_ON_Msk (0x100UL)
8156 #define MF_BEMFC_CTRL_STS_GPT12CAPINSW_Pos (5UL)
8157 #define MF_BEMFC_CTRL_STS_GPT12CAPINSW_Msk (0x20UL)
8158 #define MF_BEMFC_CTRL_STS_FILTBYPS_Pos (4UL)
8159 #define MF_BEMFC_CTRL_STS_FILTBYPS_Msk (0x10UL)
8160 #define MF_BEMFC_CTRL_STS_DEMGFILTDIS_Pos (3UL)
8161 #define MF_BEMFC_CTRL_STS_DEMGFILTDIS_Msk (0x8UL)
8162 #define MF_BEMFC_CTRL_STS_PHWCOMP_EN_Pos (2UL)
8163 #define MF_BEMFC_CTRL_STS_PHWCOMP_EN_Msk (0x4UL)
8164 #define MF_BEMFC_CTRL_STS_PHVCOMP_EN_Pos (1UL)
8165 #define MF_BEMFC_CTRL_STS_PHVCOMP_EN_Msk (0x2UL)
8166 #define MF_BEMFC_CTRL_STS_PHUCOMP_EN_Pos (0UL)
8167 #define MF_BEMFC_CTRL_STS_PHUCOMP_EN_Msk (0x1UL)
8169 #define MF_CSA_CTRL_VZERO_Pos (8UL)
8170 #define MF_CSA_CTRL_VZERO_Msk (0x100UL)
8171 #define MF_CSA_CTRL_GAIN_Pos (1UL)
8172 #define MF_CSA_CTRL_GAIN_Msk (0x6UL)
8173 #define MF_CSA_CTRL_EN_Pos (0UL)
8174 #define MF_CSA_CTRL_EN_Msk (0x1UL)
8176 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Pos (10UL)
8177 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Msk (0x400UL)
8178 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Pos (9UL)
8179 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Msk (0x200UL)
8180 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Pos (8UL)
8181 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Msk (0x100UL)
8182 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Pos (0UL)
8183 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Msk (0x1UL)
8184 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Pos (1UL)
8185 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Msk (0x2UL)
8186 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Pos (2UL)
8187 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Msk (0x4UL)
8188 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Pos (3UL)
8189 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Msk (0x8UL)
8190 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Pos (4UL)
8191 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Msk (0x10UL)
8193 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Pos (5UL)
8194 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Msk (0x20UL)
8195 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Pos (4UL)
8196 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Msk (0x10UL)
8198 #define MF_REF2_CTRL_VREF5V_OV_STS_Pos (3UL)
8199 #define MF_REF2_CTRL_VREF5V_OV_STS_Msk (0x8UL)
8200 #define MF_REF2_CTRL_VREF5V_UV_STS_Pos (2UL)
8201 #define MF_REF2_CTRL_VREF5V_UV_STS_Msk (0x4UL)
8202 #define MF_REF2_CTRL_VREF5V_OVL_STS_Pos (1UL)
8203 #define MF_REF2_CTRL_VREF5V_OVL_STS_Msk (0x2UL)
8204 #define MF_REF2_CTRL_VREF5V_PD_N_Pos (0UL)
8205 #define MF_REF2_CTRL_VREF5V_PD_N_Msk (0x1UL)
8207 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Pos (7UL)
8208 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Msk (0x80UL)
8209 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Pos (6UL)
8210 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Msk (0x40UL)
8211 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Pos (5UL)
8212 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Msk (0x20UL)
8213 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Pos (4UL)
8214 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Msk (0x10UL)
8216 #define MF_TRIM_BEMFx_BEMF_TFILT_SEL_Pos (8UL)
8217 #define MF_TRIM_BEMFx_BEMF_TFILT_SEL_Msk (0x300UL)
8218 #define MF_TRIM_BEMFx_BEMF_GPT_CAPIN_SEL_Pos (4UL)
8219 #define MF_TRIM_BEMFx_BEMF_GPT_CAPIN_SEL_Msk (0x30UL)
8220 #define MF_TRIM_BEMFx_BEMF_BT_TFILT_SEL_Pos (0UL)
8221 #define MF_TRIM_BEMFx_BEMF_BT_TFILT_SEL_Msk (0x7UL)
8223 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos (5UL)
8224 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk (0x20UL)
8225 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos (4UL)
8226 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk (0x10UL)
8227 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos (0UL)
8228 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk (0x1UL)
8236 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Pos (0UL)
8237 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Msk (0xfUL)
8239 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Pos (7UL)
8240 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Msk (0x80UL)
8241 #define PMU_CNF_CYC_SENSE_E01_Pos (4UL)
8242 #define PMU_CNF_CYC_SENSE_E01_Msk (0x30UL)
8243 #define PMU_CNF_CYC_SENSE_M03_Pos (0UL)
8244 #define PMU_CNF_CYC_SENSE_M03_Msk (0xfUL)
8246 #define PMU_CNF_CYC_WAKE_E01_Pos (4UL)
8247 #define PMU_CNF_CYC_WAKE_E01_Msk (0x30UL)
8248 #define PMU_CNF_CYC_WAKE_M03_Pos (0UL)
8249 #define PMU_CNF_CYC_WAKE_M03_Msk (0xfUL)
8251 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Pos (7UL)
8252 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Msk (0x80UL)
8253 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Pos (3UL)
8254 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Msk (0x8UL)
8255 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Pos (2UL)
8256 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Msk (0x4UL)
8257 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Pos (1UL)
8258 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Msk (0x2UL)
8259 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Pos (0UL)
8260 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Msk (0x1UL)
8262 #define PMU_CNF_RST_TFB_RST_TFB_Pos (0UL)
8263 #define PMU_CNF_RST_TFB_RST_TFB_Msk (0x3UL)
8265 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Pos (2UL)
8266 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Msk (0xcUL)
8267 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Pos (1UL)
8268 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Msk (0x2UL)
8269 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Pos (0UL)
8270 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Msk (0x1UL)
8272 #define PMU_GPUDATA00_DATA0_Pos (0UL)
8273 #define PMU_GPUDATA00_DATA0_Msk (0xffUL)
8275 #define PMU_GPUDATA01_DATA1_Pos (0UL)
8276 #define PMU_GPUDATA01_DATA1_Msk (0xffUL)
8278 #define PMU_GPUDATA02_DATA2_Pos (0UL)
8279 #define PMU_GPUDATA02_DATA2_Msk (0xffUL)
8281 #define PMU_GPUDATA03_DATA3_Pos (0UL)
8282 #define PMU_GPUDATA03_DATA3_Msk (0xffUL)
8284 #define PMU_GPUDATA04_DATA4_Pos (0UL)
8285 #define PMU_GPUDATA04_DATA4_Msk (0xffUL)
8287 #define PMU_GPUDATA05_DATA5_Pos (0UL)
8288 #define PMU_GPUDATA05_DATA5_Msk (0xffUL)
8290 #define PMU_LIN_WAKE_EN_LIN_EN_Pos (7UL)
8291 #define PMU_LIN_WAKE_EN_LIN_EN_Msk (0x80UL)
8293 #define PMU_MON_CNF_STS_Pos (7UL)
8294 #define PMU_MON_CNF_STS_Msk (0x80UL)
8295 #define PMU_MON_CNF_PU_Pos (5UL)
8296 #define PMU_MON_CNF_PU_Msk (0x20UL)
8297 #define PMU_MON_CNF_PD_Pos (4UL)
8298 #define PMU_MON_CNF_PD_Msk (0x10UL)
8299 #define PMU_MON_CNF_CYC_Pos (3UL)
8300 #define PMU_MON_CNF_CYC_Msk (0x8UL)
8301 #define PMU_MON_CNF_RISE_Pos (2UL)
8302 #define PMU_MON_CNF_RISE_Msk (0x4UL)
8303 #define PMU_MON_CNF_FALL_Pos (1UL)
8304 #define PMU_MON_CNF_FALL_Msk (0x2UL)
8305 #define PMU_MON_CNF_EN_Pos (0UL)
8306 #define PMU_MON_CNF_EN_Msk (0x1UL)
8308 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Pos (7UL)
8309 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Msk (0x80UL)
8310 #define PMU_PMU_RESET_STS1_PMU_PIN_Pos (6UL)
8311 #define PMU_PMU_RESET_STS1_PMU_PIN_Msk (0x40UL)
8312 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Pos (5UL)
8313 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Msk (0x20UL)
8314 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Pos (4UL)
8315 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Msk (0x10UL)
8316 #define PMU_PMU_RESET_STS1_PMU_LPR_Pos (3UL)
8317 #define PMU_PMU_RESET_STS1_PMU_LPR_Msk (0x8UL)
8318 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Pos (2UL)
8319 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Msk (0x4UL)
8320 #define PMU_PMU_RESET_STS1_PMU_WAKE_Pos (1UL)
8321 #define PMU_PMU_RESET_STS1_PMU_WAKE_Msk (0x2UL)
8322 #define PMU_PMU_RESET_STS1_SYS_FAIL_Pos (0UL)
8323 #define PMU_PMU_RESET_STS1_SYS_FAIL_Msk (0x1UL)
8325 #define PMU_PMU_RESET_STS2_LOCKUP_Pos (2UL)
8326 #define PMU_PMU_RESET_STS2_LOCKUP_Msk (0x4UL)
8327 #define PMU_PMU_RESET_STS2_PMU_SOFT_Pos (1UL)
8328 #define PMU_PMU_RESET_STS2_PMU_SOFT_Msk (0x2UL)
8329 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Pos (0UL)
8330 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Msk (0x1UL)
8332 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos (6UL)
8333 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk (0x40UL)
8334 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Pos (5UL)
8335 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Msk (0x20UL)
8336 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Pos (4UL)
8337 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Msk (0x10UL)
8338 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos (2UL)
8339 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk (0x4UL)
8340 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Pos (1UL)
8341 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Msk (0x2UL)
8342 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Pos (0UL)
8343 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Msk (0x1UL)
8345 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Pos (6UL)
8346 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Msk (0x40UL)
8347 #define PMU_SYS_FAIL_STS_SYS_OT_Pos (5UL)
8348 #define PMU_SYS_FAIL_STS_SYS_OT_Msk (0x20UL)
8349 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Pos (3UL)
8350 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Msk (0x8UL)
8351 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Pos (2UL)
8352 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Msk (0x4UL)
8353 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Pos (1UL)
8354 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Msk (0x2UL)
8355 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Pos (0UL)
8356 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Msk (0x1UL)
8358 #define PMU_SystemStartConfig_MBIST_EN_Pos (0UL)
8359 #define PMU_SystemStartConfig_MBIST_EN_Msk (0x1UL)
8361 #define PMU_VDDEXT_CTRL_STABLE_Pos (7UL)
8362 #define PMU_VDDEXT_CTRL_STABLE_Msk (0x80UL)
8363 #define PMU_VDDEXT_CTRL_OK_Pos (6UL)
8364 #define PMU_VDDEXT_CTRL_OK_Msk (0x40UL)
8365 #define PMU_VDDEXT_CTRL_OVERLOAD_Pos (5UL)
8366 #define PMU_VDDEXT_CTRL_OVERLOAD_Msk (0x20UL)
8367 #define PMU_VDDEXT_CTRL_OVERVOLT_Pos (4UL)
8368 #define PMU_VDDEXT_CTRL_OVERVOLT_Msk (0x10UL)
8369 #define PMU_VDDEXT_CTRL_SHORT_Pos (3UL)
8370 #define PMU_VDDEXT_CTRL_SHORT_Msk (0x8UL)
8371 #define PMU_VDDEXT_CTRL_FAIL_EN_Pos (2UL)
8372 #define PMU_VDDEXT_CTRL_FAIL_EN_Msk (0x4UL)
8373 #define PMU_VDDEXT_CTRL_CYC_EN_Pos (1UL)
8374 #define PMU_VDDEXT_CTRL_CYC_EN_Msk (0x2UL)
8375 #define PMU_VDDEXT_CTRL_ENABLE_Pos (0UL)
8376 #define PMU_VDDEXT_CTRL_ENABLE_Msk (0x1UL)
8378 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Pos (4UL)
8379 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Msk (0x10UL)
8380 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Pos (3UL)
8381 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Msk (0x8UL)
8382 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Pos (2UL)
8383 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Msk (0x4UL)
8384 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Pos (1UL)
8385 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Msk (0x2UL)
8386 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Pos (0UL)
8387 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Msk (0x1UL)
8389 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Pos (4UL)
8390 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Msk (0x10UL)
8391 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Pos (3UL)
8392 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Msk (0x8UL)
8393 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Pos (2UL)
8394 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Msk (0x4UL)
8395 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Pos (1UL)
8396 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Msk (0x2UL)
8397 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Pos (0UL)
8398 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Msk (0x1UL)
8400 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Pos (4UL)
8401 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Msk (0x10UL)
8402 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Pos (3UL)
8403 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Msk (0x8UL)
8404 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Pos (2UL)
8405 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Msk (0x4UL)
8406 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Pos (1UL)
8407 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Msk (0x2UL)
8408 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Pos (0UL)
8409 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Msk (0x1UL)
8411 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Pos (4UL)
8412 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Msk (0x10UL)
8413 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Pos (3UL)
8414 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Msk (0x8UL)
8415 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Pos (2UL)
8416 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Msk (0x4UL)
8417 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Pos (1UL)
8418 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Msk (0x2UL)
8419 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Pos (0UL)
8420 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Msk (0x1UL)
8422 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Pos (4UL)
8423 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Msk (0x10UL)
8424 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Pos (3UL)
8425 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Msk (0x8UL)
8426 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Pos (2UL)
8427 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Msk (0x4UL)
8428 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Pos (1UL)
8429 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Msk (0x2UL)
8430 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Pos (0UL)
8431 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Msk (0x1UL)
8433 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Pos (4UL)
8434 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Msk (0x10UL)
8435 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Pos (3UL)
8436 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Msk (0x8UL)
8437 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Pos (2UL)
8438 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Msk (0x4UL)
8439 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Pos (1UL)
8440 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Msk (0x2UL)
8441 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Pos (0UL)
8442 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Msk (0x1UL)
8444 #define PMU_WAKE_STATUS_FAIL_Pos (5UL)
8445 #define PMU_WAKE_STATUS_FAIL_Msk (0x20UL)
8446 #define PMU_WAKE_STATUS_CYC_WAKE_Pos (4UL)
8447 #define PMU_WAKE_STATUS_CYC_WAKE_Msk (0x10UL)
8448 #define PMU_WAKE_STATUS_GPIO1_Pos (3UL)
8449 #define PMU_WAKE_STATUS_GPIO1_Msk (0x8UL)
8450 #define PMU_WAKE_STATUS_GPIO0_Pos (2UL)
8451 #define PMU_WAKE_STATUS_GPIO0_Msk (0x4UL)
8452 #define PMU_WAKE_STATUS_MON_WAKE_Pos (1UL)
8453 #define PMU_WAKE_STATUS_MON_WAKE_Msk (0x2UL)
8454 #define PMU_WAKE_STATUS_LIN_WAKE_Pos (0UL)
8455 #define PMU_WAKE_STATUS_LIN_WAKE_Msk (0x1UL)
8457 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Pos (2UL)
8458 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Msk (0x4UL)
8459 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Pos (0UL)
8460 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Msk (0x1UL)
8462 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Pos (4UL)
8463 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Msk (0x10UL)
8464 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Pos (3UL)
8465 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Msk (0x8UL)
8466 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Pos (2UL)
8467 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Msk (0x4UL)
8468 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Pos (1UL)
8469 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Msk (0x2UL)
8470 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Pos (0UL)
8471 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Msk (0x1UL)
8473 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Pos (4UL)
8474 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Msk (0x10UL)
8475 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Pos (3UL)
8476 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Msk (0x8UL)
8477 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Pos (2UL)
8478 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Msk (0x4UL)
8479 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Pos (1UL)
8480 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Msk (0x2UL)
8481 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Pos (0UL)
8482 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Msk (0x1UL)
8484 #define PMU_WAKE_STS_MON_WAKE_STS_Pos (0UL)
8485 #define PMU_WAKE_STS_MON_WAKE_STS_Msk (0x1UL)
8493 #define PORT_P0_ALTSEL0_P0_Pos (0UL)
8494 #define PORT_P0_ALTSEL0_P0_Msk (0x1UL)
8495 #define PORT_P0_ALTSEL0_P1_Pos (1UL)
8496 #define PORT_P0_ALTSEL0_P1_Msk (0x2UL)
8497 #define PORT_P0_ALTSEL0_P2_Pos (2UL)
8498 #define PORT_P0_ALTSEL0_P2_Msk (0x4UL)
8499 #define PORT_P0_ALTSEL0_P3_Pos (3UL)
8500 #define PORT_P0_ALTSEL0_P3_Msk (0x8UL)
8501 #define PORT_P0_ALTSEL0_P4_Pos (4UL)
8502 #define PORT_P0_ALTSEL0_P4_Msk (0x10UL)
8504 #define PORT_P0_ALTSEL1_P0_Pos (0UL)
8505 #define PORT_P0_ALTSEL1_P0_Msk (0x1UL)
8506 #define PORT_P0_ALTSEL1_P1_Pos (1UL)
8507 #define PORT_P0_ALTSEL1_P1_Msk (0x2UL)
8508 #define PORT_P0_ALTSEL1_P2_Pos (2UL)
8509 #define PORT_P0_ALTSEL1_P2_Msk (0x4UL)
8510 #define PORT_P0_ALTSEL1_P3_Pos (3UL)
8511 #define PORT_P0_ALTSEL1_P3_Msk (0x8UL)
8512 #define PORT_P0_ALTSEL1_P4_Pos (4UL)
8513 #define PORT_P0_ALTSEL1_P4_Msk (0x10UL)
8515 #define PORT_P0_DATA_P0_Pos (0UL)
8516 #define PORT_P0_DATA_P0_Msk (0x1UL)
8517 #define PORT_P0_DATA_P1_Pos (1UL)
8518 #define PORT_P0_DATA_P1_Msk (0x2UL)
8519 #define PORT_P0_DATA_P2_Pos (2UL)
8520 #define PORT_P0_DATA_P2_Msk (0x4UL)
8521 #define PORT_P0_DATA_P3_Pos (3UL)
8522 #define PORT_P0_DATA_P3_Msk (0x8UL)
8523 #define PORT_P0_DATA_P4_Pos (4UL)
8524 #define PORT_P0_DATA_P4_Msk (0x10UL)
8526 #define PORT_P0_DIR_P0_Pos (0UL)
8527 #define PORT_P0_DIR_P0_Msk (0x1UL)
8528 #define PORT_P0_DIR_P1_Pos (1UL)
8529 #define PORT_P0_DIR_P1_Msk (0x2UL)
8530 #define PORT_P0_DIR_P2_Pos (2UL)
8531 #define PORT_P0_DIR_P2_Msk (0x4UL)
8532 #define PORT_P0_DIR_P3_Pos (3UL)
8533 #define PORT_P0_DIR_P3_Msk (0x8UL)
8534 #define PORT_P0_DIR_P4_Pos (4UL)
8535 #define PORT_P0_DIR_P4_Msk (0x10UL)
8537 #define PORT_P0_OD_P0_Pos (0UL)
8538 #define PORT_P0_OD_P0_Msk (0x1UL)
8539 #define PORT_P0_OD_P1_Pos (1UL)
8540 #define PORT_P0_OD_P1_Msk (0x2UL)
8541 #define PORT_P0_OD_P2_Pos (2UL)
8542 #define PORT_P0_OD_P2_Msk (0x4UL)
8543 #define PORT_P0_OD_P3_Pos (3UL)
8544 #define PORT_P0_OD_P3_Msk (0x8UL)
8545 #define PORT_P0_OD_P4_Pos (4UL)
8546 #define PORT_P0_OD_P4_Msk (0x10UL)
8548 #define PORT_P0_PUDEN_P0_Pos (0UL)
8549 #define PORT_P0_PUDEN_P0_Msk (0x1UL)
8550 #define PORT_P0_PUDEN_P1_Pos (1UL)
8551 #define PORT_P0_PUDEN_P1_Msk (0x2UL)
8552 #define PORT_P0_PUDEN_P2_Pos (2UL)
8553 #define PORT_P0_PUDEN_P2_Msk (0x4UL)
8554 #define PORT_P0_PUDEN_P3_Pos (3UL)
8555 #define PORT_P0_PUDEN_P3_Msk (0x8UL)
8556 #define PORT_P0_PUDEN_P4_Pos (4UL)
8557 #define PORT_P0_PUDEN_P4_Msk (0x10UL)
8559 #define PORT_P0_PUDSEL_P0_Pos (0UL)
8560 #define PORT_P0_PUDSEL_P0_Msk (0x1UL)
8561 #define PORT_P0_PUDSEL_P1_Pos (1UL)
8562 #define PORT_P0_PUDSEL_P1_Msk (0x2UL)
8563 #define PORT_P0_PUDSEL_P2_Pos (2UL)
8564 #define PORT_P0_PUDSEL_P2_Msk (0x4UL)
8565 #define PORT_P0_PUDSEL_P3_Pos (3UL)
8566 #define PORT_P0_PUDSEL_P3_Msk (0x8UL)
8567 #define PORT_P0_PUDSEL_P4_Pos (4UL)
8568 #define PORT_P0_PUDSEL_P4_Msk (0x10UL)
8570 #define PORT_P1_ALTSEL0_P0_Pos (0UL)
8571 #define PORT_P1_ALTSEL0_P0_Msk (0x1UL)
8572 #define PORT_P1_ALTSEL0_P1_Pos (1UL)
8573 #define PORT_P1_ALTSEL0_P1_Msk (0x2UL)
8574 #define PORT_P1_ALTSEL0_P2_Pos (2UL)
8575 #define PORT_P1_ALTSEL0_P2_Msk (0x4UL)
8576 #define PORT_P1_ALTSEL0_P3_Pos (3UL)
8577 #define PORT_P1_ALTSEL0_P3_Msk (0x8UL)
8578 #define PORT_P1_ALTSEL0_P4_Pos (4UL)
8579 #define PORT_P1_ALTSEL0_P4_Msk (0x10UL)
8581 #define PORT_P1_ALTSEL1_P0_Pos (0UL)
8582 #define PORT_P1_ALTSEL1_P0_Msk (0x1UL)
8583 #define PORT_P1_ALTSEL1_P1_Pos (1UL)
8584 #define PORT_P1_ALTSEL1_P1_Msk (0x2UL)
8585 #define PORT_P1_ALTSEL1_P2_Pos (2UL)
8586 #define PORT_P1_ALTSEL1_P2_Msk (0x4UL)
8587 #define PORT_P1_ALTSEL1_P3_Pos (3UL)
8588 #define PORT_P1_ALTSEL1_P3_Msk (0x8UL)
8589 #define PORT_P1_ALTSEL1_P4_Pos (4UL)
8590 #define PORT_P1_ALTSEL1_P4_Msk (0x10UL)
8592 #define PORT_P1_DATA_P0_Pos (0UL)
8593 #define PORT_P1_DATA_P0_Msk (0x1UL)
8594 #define PORT_P1_DATA_P1_Pos (1UL)
8595 #define PORT_P1_DATA_P1_Msk (0x2UL)
8596 #define PORT_P1_DATA_P2_Pos (2UL)
8597 #define PORT_P1_DATA_P2_Msk (0x4UL)
8598 #define PORT_P1_DATA_P3_Pos (3UL)
8599 #define PORT_P1_DATA_P3_Msk (0x8UL)
8600 #define PORT_P1_DATA_P4_Pos (4UL)
8601 #define PORT_P1_DATA_P4_Msk (0x10UL)
8603 #define PORT_P1_DIR_P0_Pos (0UL)
8604 #define PORT_P1_DIR_P0_Msk (0x1UL)
8605 #define PORT_P1_DIR_P1_Pos (1UL)
8606 #define PORT_P1_DIR_P1_Msk (0x2UL)
8607 #define PORT_P1_DIR_P2_Pos (2UL)
8608 #define PORT_P1_DIR_P2_Msk (0x4UL)
8609 #define PORT_P1_DIR_P3_Pos (3UL)
8610 #define PORT_P1_DIR_P3_Msk (0x8UL)
8611 #define PORT_P1_DIR_P4_Pos (4UL)
8612 #define PORT_P1_DIR_P4_Msk (0x10UL)
8614 #define PORT_P1_OD_P0_Pos (1UL)
8615 #define PORT_P1_OD_P0_Msk (0x2UL)
8616 #define PORT_P1_OD_P1_Pos (2UL)
8617 #define PORT_P1_OD_P1_Msk (0x4UL)
8618 #define PORT_P1_OD_P3_P2_Pos (3UL)
8619 #define PORT_P1_OD_P3_P2_Msk (0x8UL)
8620 #define PORT_P1_OD_P4_Pos (4UL)
8621 #define PORT_P1_OD_P4_Msk (0x10UL)
8623 #define PORT_P1_PUDEN_P0_Pos (0UL)
8624 #define PORT_P1_PUDEN_P0_Msk (0x1UL)
8625 #define PORT_P1_PUDEN_P1_Pos (1UL)
8626 #define PORT_P1_PUDEN_P1_Msk (0x2UL)
8627 #define PORT_P1_PUDEN_P2_Pos (2UL)
8628 #define PORT_P1_PUDEN_P2_Msk (0x4UL)
8629 #define PORT_P1_PUDEN_P3_Pos (3UL)
8630 #define PORT_P1_PUDEN_P3_Msk (0x8UL)
8631 #define PORT_P1_PUDEN_P4_Pos (4UL)
8632 #define PORT_P1_PUDEN_P4_Msk (0x10UL)
8634 #define PORT_P1_PUDSEL_P0_Pos (0UL)
8635 #define PORT_P1_PUDSEL_P0_Msk (0x1UL)
8636 #define PORT_P1_PUDSEL_P1_Pos (1UL)
8637 #define PORT_P1_PUDSEL_P1_Msk (0x2UL)
8638 #define PORT_P1_PUDSEL_P2_Pos (2UL)
8639 #define PORT_P1_PUDSEL_P2_Msk (0x4UL)
8640 #define PORT_P1_PUDSEL_P3_Pos (3UL)
8641 #define PORT_P1_PUDSEL_P3_Msk (0x8UL)
8642 #define PORT_P1_PUDSEL_P4_Pos (4UL)
8643 #define PORT_P1_PUDSEL_P4_Msk (0x10UL)
8645 #define PORT_P2_DATA_P0_Pos (0UL)
8646 #define PORT_P2_DATA_P0_Msk (0x1UL)
8647 #define PORT_P2_DATA_P2_Pos (2UL)
8648 #define PORT_P2_DATA_P2_Msk (0x4UL)
8649 #define PORT_P2_DATA_P3_Pos (3UL)
8650 #define PORT_P2_DATA_P3_Msk (0x8UL)
8651 #define PORT_P2_DATA_P4_Pos (4UL)
8652 #define PORT_P2_DATA_P4_Msk (0x10UL)
8653 #define PORT_P2_DATA_P5_Pos (5UL)
8654 #define PORT_P2_DATA_P5_Msk (0x20UL)
8656 #define PORT_P2_DIR_P0_Pos (0UL)
8657 #define PORT_P2_DIR_P0_Msk (0x1UL)
8658 #define PORT_P2_DIR_P2_Pos (2UL)
8659 #define PORT_P2_DIR_P2_Msk (0x4UL)
8660 #define PORT_P2_DIR_P3_Pos (3UL)
8661 #define PORT_P2_DIR_P3_Msk (0x8UL)
8662 #define PORT_P2_DIR_P4_Pos (4UL)
8663 #define PORT_P2_DIR_P4_Msk (0x10UL)
8664 #define PORT_P2_DIR_P5_Pos (5UL)
8665 #define PORT_P2_DIR_P5_Msk (0x20UL)
8667 #define PORT_P2_PUDEN_P0_Pos (0UL)
8668 #define PORT_P2_PUDEN_P0_Msk (0x1UL)
8669 #define PORT_P2_PUDEN_P2_Pos (2UL)
8670 #define PORT_P2_PUDEN_P2_Msk (0x4UL)
8671 #define PORT_P2_PUDEN_P3_Pos (3UL)
8672 #define PORT_P2_PUDEN_P3_Msk (0x8UL)
8673 #define PORT_P2_PUDEN_P4_Pos (4UL)
8674 #define PORT_P2_PUDEN_P4_Msk (0x10UL)
8675 #define PORT_P2_PUDEN_P5_Pos (5UL)
8676 #define PORT_P2_PUDEN_P5_Msk (0x20UL)
8678 #define PORT_P2_PUDSEL_P0_Pos (0UL)
8679 #define PORT_P2_PUDSEL_P0_Msk (0x1UL)
8680 #define PORT_P2_PUDSEL_P2_Pos (2UL)
8681 #define PORT_P2_PUDSEL_P2_Msk (0x4UL)
8682 #define PORT_P2_PUDSEL_P3_Pos (3UL)
8683 #define PORT_P2_PUDSEL_P3_Msk (0x8UL)
8684 #define PORT_P2_PUDSEL_P4_Pos (4UL)
8685 #define PORT_P2_PUDSEL_P4_Msk (0x10UL)
8686 #define PORT_P2_PUDSEL_P5_Pos (5UL)
8687 #define PORT_P2_PUDSEL_P5_Msk (0x20UL)
8695 #define SCU_APCLK1_APCLK3SCLR_Pos (7UL)
8696 #define SCU_APCLK1_APCLK3SCLR_Msk (0x80UL)
8697 #define SCU_APCLK1_APCLK3STS_Pos (6UL)
8698 #define SCU_APCLK1_APCLK3STS_Msk (0x40UL)
8699 #define SCU_APCLK1_APCLK1STS_Pos (4UL)
8700 #define SCU_APCLK1_APCLK1STS_Msk (0x30UL)
8701 #define SCU_APCLK1_APCLK1SCLR_Pos (2UL)
8702 #define SCU_APCLK1_APCLK1SCLR_Msk (0x4UL)
8703 #define SCU_APCLK1_APCLK1FAC_Pos (0UL)
8704 #define SCU_APCLK1_APCLK1FAC_Msk (0x3UL)
8706 #define SCU_APCLK2_APCLK2SCLR_Pos (7UL)
8707 #define SCU_APCLK2_APCLK2SCLR_Msk (0x80UL)
8708 #define SCU_APCLK2_APCLK2STS_Pos (5UL)
8709 #define SCU_APCLK2_APCLK2STS_Msk (0x60UL)
8710 #define SCU_APCLK2_APCLK2FAC_Pos (0UL)
8711 #define SCU_APCLK2_APCLK2FAC_Msk (0x1fUL)
8713 #define SCU_APCLK_CTRL1_CPCLK_DIV_Pos (7UL)
8714 #define SCU_APCLK_CTRL1_CPCLK_DIV_Msk (0x80UL)
8715 #define SCU_APCLK_CTRL1_CPCLK_SEL_Pos (6UL)
8716 #define SCU_APCLK_CTRL1_CPCLK_SEL_Msk (0x40UL)
8717 #define SCU_APCLK_CTRL1_BGCLK_DIV_Pos (5UL)
8718 #define SCU_APCLK_CTRL1_BGCLK_DIV_Msk (0x20UL)
8719 #define SCU_APCLK_CTRL1_BGCLK_SEL_Pos (4UL)
8720 #define SCU_APCLK_CTRL1_BGCLK_SEL_Msk (0x10UL)
8721 #define SCU_APCLK_CTRL1_CLKWDT_IE_Pos (3UL)
8722 #define SCU_APCLK_CTRL1_CLKWDT_IE_Msk (0x8UL)
8723 #define SCU_APCLK_CTRL1_T3CLK_SEL_Pos (2UL)
8724 #define SCU_APCLK_CTRL1_T3CLK_SEL_Msk (0x4UL)
8725 #define SCU_APCLK_CTRL1_APCLK_SET_Pos (1UL)
8726 #define SCU_APCLK_CTRL1_APCLK_SET_Msk (0x2UL)
8727 #define SCU_APCLK_CTRL1_PLL_LOCK_Pos (0UL)
8728 #define SCU_APCLK_CTRL1_PLL_LOCK_Msk (0x1UL)
8730 #define SCU_APCLK_CTRL2_T3CLK_DIV_Pos (2UL)
8731 #define SCU_APCLK_CTRL2_T3CLK_DIV_Msk (0xcUL)
8732 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Pos (0UL)
8733 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Msk (0x3UL)
8735 #define SCU_BCON1_R_Pos (0UL)
8736 #define SCU_BCON1_R_Msk (0x1UL)
8737 #define SCU_BCON1_BRPRE_Pos (1UL)
8738 #define SCU_BCON1_BRPRE_Msk (0xeUL)
8740 #define SCU_BCON2_R_Pos (0UL)
8741 #define SCU_BCON2_R_Msk (0x1UL)
8742 #define SCU_BCON2_BRPRE_Pos (1UL)
8743 #define SCU_BCON2_BRPRE_Msk (0xeUL)
8745 #define SCU_BGH1_BR_VALUE_Pos (0UL)
8746 #define SCU_BGH1_BR_VALUE_Msk (0xffUL)
8748 #define SCU_BGH2_BR_VALUE_Pos (0UL)
8749 #define SCU_BGH2_BR_VALUE_Msk (0xffUL)
8751 #define SCU_BGL1_FD_SEL_Pos (0UL)
8752 #define SCU_BGL1_FD_SEL_Msk (0x1fUL)
8753 #define SCU_BGL1_BR_VALUE_Pos (5UL)
8754 #define SCU_BGL1_BR_VALUE_Msk (0xe0UL)
8756 #define SCU_BGL2_FD_SEL_Pos (0UL)
8757 #define SCU_BGL2_FD_SEL_Msk (0x1fUL)
8758 #define SCU_BGL2_BR_VALUE_Pos (5UL)
8759 #define SCU_BGL2_BR_VALUE_Msk (0xe0UL)
8761 #define SCU_CMCON1_VCOSEL_Pos (7UL)
8762 #define SCU_CMCON1_VCOSEL_Msk (0x80UL)
8763 #define SCU_CMCON1_K1DIV_Pos (6UL)
8764 #define SCU_CMCON1_K1DIV_Msk (0x40UL)
8765 #define SCU_CMCON1_K2DIV_Pos (4UL)
8766 #define SCU_CMCON1_K2DIV_Msk (0x30UL)
8767 #define SCU_CMCON1_CLKREL_Pos (0UL)
8768 #define SCU_CMCON1_CLKREL_Msk (0xfUL)
8770 #define SCU_CMCON2_PBA0CLKREL_Pos (0UL)
8771 #define SCU_CMCON2_PBA0CLKREL_Msk (0x1UL)
8773 #define SCU_COCON_EN_Pos (7UL)
8774 #define SCU_COCON_EN_Msk (0x80UL)
8775 #define SCU_COCON_COUTS1_Pos (6UL)
8776 #define SCU_COCON_COUTS1_Msk (0x40UL)
8777 #define SCU_COCON_TLEN_Pos (5UL)
8778 #define SCU_COCON_TLEN_Msk (0x20UL)
8779 #define SCU_COCON_COUTS0_Pos (4UL)
8780 #define SCU_COCON_COUTS0_Msk (0x10UL)
8781 #define SCU_COCON_COREL_Pos (0UL)
8782 #define SCU_COCON_COREL_Msk (0xfUL)
8784 #define SCU_DMAIEN1_CH8IE_Pos (7UL)
8785 #define SCU_DMAIEN1_CH8IE_Msk (0x80UL)
8786 #define SCU_DMAIEN1_CH7IE_Pos (6UL)
8787 #define SCU_DMAIEN1_CH7IE_Msk (0x40UL)
8788 #define SCU_DMAIEN1_CH6IE_Pos (5UL)
8789 #define SCU_DMAIEN1_CH6IE_Msk (0x20UL)
8790 #define SCU_DMAIEN1_CH5IE_Pos (4UL)
8791 #define SCU_DMAIEN1_CH5IE_Msk (0x10UL)
8792 #define SCU_DMAIEN1_CH4IE_Pos (3UL)
8793 #define SCU_DMAIEN1_CH4IE_Msk (0x8UL)
8794 #define SCU_DMAIEN1_CH3IE_Pos (2UL)
8795 #define SCU_DMAIEN1_CH3IE_Msk (0x4UL)
8796 #define SCU_DMAIEN1_CH2IE_Pos (1UL)
8797 #define SCU_DMAIEN1_CH2IE_Msk (0x2UL)
8798 #define SCU_DMAIEN1_CH1IE_Pos (0UL)
8799 #define SCU_DMAIEN1_CH1IE_Msk (0x1UL)
8801 #define SCU_DMAIEN2_SDADCIE_Pos (6UL)
8802 #define SCU_DMAIEN2_SDADCIE_Msk (0x40UL)
8803 #define SCU_DMAIEN2_GPT12IE_Pos (5UL)
8804 #define SCU_DMAIEN2_GPT12IE_Msk (0x20UL)
8805 #define SCU_DMAIEN2_SSCRXIE_Pos (4UL)
8806 #define SCU_DMAIEN2_SSCRXIE_Msk (0x10UL)
8807 #define SCU_DMAIEN2_SSCTXIE_Pos (3UL)
8808 #define SCU_DMAIEN2_SSCTXIE_Msk (0x8UL)
8809 #define SCU_DMAIEN2_TRSEQ2RDYIE_Pos (2UL)
8810 #define SCU_DMAIEN2_TRSEQ2RDYIE_Msk (0x4UL)
8811 #define SCU_DMAIEN2_TRSEQ1RDYIE_Pos (1UL)
8812 #define SCU_DMAIEN2_TRSEQ1RDYIE_Msk (0x2UL)
8813 #define SCU_DMAIEN2_TRERRIE_Pos (0UL)
8814 #define SCU_DMAIEN2_TRERRIE_Msk (0x1UL)
8816 #define SCU_DMAIRC1_CH8_Pos (7UL)
8817 #define SCU_DMAIRC1_CH8_Msk (0x80UL)
8818 #define SCU_DMAIRC1_CH7_Pos (6UL)
8819 #define SCU_DMAIRC1_CH7_Msk (0x40UL)
8820 #define SCU_DMAIRC1_CH6_Pos (5UL)
8821 #define SCU_DMAIRC1_CH6_Msk (0x20UL)
8822 #define SCU_DMAIRC1_CH5_Pos (4UL)
8823 #define SCU_DMAIRC1_CH5_Msk (0x10UL)
8824 #define SCU_DMAIRC1_CH4_Pos (3UL)
8825 #define SCU_DMAIRC1_CH4_Msk (0x8UL)
8826 #define SCU_DMAIRC1_CH3_Pos (2UL)
8827 #define SCU_DMAIRC1_CH3_Msk (0x4UL)
8828 #define SCU_DMAIRC1_CH2_Pos (1UL)
8829 #define SCU_DMAIRC1_CH2_Msk (0x2UL)
8830 #define SCU_DMAIRC1_CH1_Pos (0UL)
8831 #define SCU_DMAIRC1_CH1_Msk (0x1UL)
8833 #define SCU_DMAIRC1CLR_CH8C_Pos (7UL)
8834 #define SCU_DMAIRC1CLR_CH8C_Msk (0x80UL)
8835 #define SCU_DMAIRC1CLR_CH7C_Pos (6UL)
8836 #define SCU_DMAIRC1CLR_CH7C_Msk (0x40UL)
8837 #define SCU_DMAIRC1CLR_CH6C_Pos (5UL)
8838 #define SCU_DMAIRC1CLR_CH6C_Msk (0x20UL)
8839 #define SCU_DMAIRC1CLR_CH5C_Pos (4UL)
8840 #define SCU_DMAIRC1CLR_CH5C_Msk (0x10UL)
8841 #define SCU_DMAIRC1CLR_CH4C_Pos (3UL)
8842 #define SCU_DMAIRC1CLR_CH4C_Msk (0x8UL)
8843 #define SCU_DMAIRC1CLR_CH3C_Pos (2UL)
8844 #define SCU_DMAIRC1CLR_CH3C_Msk (0x4UL)
8845 #define SCU_DMAIRC1CLR_CH2C_Pos (1UL)
8846 #define SCU_DMAIRC1CLR_CH2C_Msk (0x2UL)
8847 #define SCU_DMAIRC1CLR_CH1C_Pos (0UL)
8848 #define SCU_DMAIRC1CLR_CH1C_Msk (0x1UL)
8850 #define SCU_DMAIRC2_SDADC_Pos (6UL)
8851 #define SCU_DMAIRC2_SDADC_Msk (0x40UL)
8852 #define SCU_DMAIRC2_GPT12_Pos (5UL)
8853 #define SCU_DMAIRC2_GPT12_Msk (0x20UL)
8854 #define SCU_DMAIRC2_SSC2RDY_Pos (4UL)
8855 #define SCU_DMAIRC2_SSC2RDY_Msk (0x10UL)
8856 #define SCU_DMAIRC2_SSC1RDY_Pos (3UL)
8857 #define SCU_DMAIRC2_SSC1RDY_Msk (0x8UL)
8858 #define SCU_DMAIRC2_TRSEQ2DY_Pos (2UL)
8859 #define SCU_DMAIRC2_TRSEQ2DY_Msk (0x4UL)
8860 #define SCU_DMAIRC2_TRSEQ1DY_Pos (1UL)
8861 #define SCU_DMAIRC2_TRSEQ1DY_Msk (0x2UL)
8862 #define SCU_DMAIRC2_STRDY_Pos (0UL)
8863 #define SCU_DMAIRC2_STRDY_Msk (0x1UL)
8865 #define SCU_DMAIRC2CLR_SDADCC_Pos (6UL)
8866 #define SCU_DMAIRC2CLR_SDADCC_Msk (0x40UL)
8867 #define SCU_DMAIRC2CLR_GPT12C_Pos (5UL)
8868 #define SCU_DMAIRC2CLR_GPT12C_Msk (0x20UL)
8869 #define SCU_DMAIRC2CLR_SSC2C_Pos (4UL)
8870 #define SCU_DMAIRC2CLR_SSC2C_Msk (0x10UL)
8871 #define SCU_DMAIRC2CLR_SSC1C_Pos (3UL)
8872 #define SCU_DMAIRC2CLR_SSC1C_Msk (0x8UL)
8873 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos (2UL)
8874 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk (0x4UL)
8875 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos (1UL)
8876 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk (0x2UL)
8878 #define SCU_DMASRCCLR_GPT12_T3C_Pos (7UL)
8879 #define SCU_DMASRCCLR_GPT12_T3C_Msk (0x80UL)
8880 #define SCU_DMASRCCLR_SSCRXC_Pos (6UL)
8881 #define SCU_DMASRCCLR_SSCRXC_Msk (0x40UL)
8882 #define SCU_DMASRCCLR_SSCTXC_Pos (5UL)
8883 #define SCU_DMASRCCLR_SSCTXC_Msk (0x20UL)
8885 #define SCU_DMASRCSEL_GPT12_T3_Pos (7UL)
8886 #define SCU_DMASRCSEL_GPT12_T3_Msk (0x80UL)
8887 #define SCU_DMASRCSEL_SSCRX_Pos (6UL)
8888 #define SCU_DMASRCSEL_SSCRX_Msk (0x40UL)
8889 #define SCU_DMASRCSEL_SSCTX_Pos (5UL)
8890 #define SCU_DMASRCSEL_SSCTX_Msk (0x20UL)
8891 #define SCU_DMASRCSEL_T12PM_DMAEN_Pos (3UL)
8892 #define SCU_DMASRCSEL_T12PM_DMAEN_Msk (0x8UL)
8893 #define SCU_DMASRCSEL_T12ZM_DMAEN_Pos (2UL)
8894 #define SCU_DMASRCSEL_T12ZM_DMAEN_Msk (0x4UL)
8895 #define SCU_DMASRCSEL_SSCRXSRCSEL_Pos (1UL)
8896 #define SCU_DMASRCSEL_SSCRXSRCSEL_Msk (0x2UL)
8897 #define SCU_DMASRCSEL_SSCTXSRCSEL_Pos (0UL)
8898 #define SCU_DMASRCSEL_SSCTXSRCSEL_Msk (0x1UL)
8900 #define SCU_DMASRCSEL2_GPT12_DMAEN_Pos (0UL)
8901 #define SCU_DMASRCSEL2_GPT12_DMAEN_Msk (0x3UL)
8903 #define SCU_EDCCON_NVMIE_Pos (2UL)
8904 #define SCU_EDCCON_NVMIE_Msk (0x4UL)
8905 #define SCU_EDCCON_RIE_Pos (0UL)
8906 #define SCU_EDCCON_RIE_Msk (0x1UL)
8908 #define SCU_EDCSCLR_RSBEC_Pos (4UL)
8909 #define SCU_EDCSCLR_RSBEC_Msk (0x10UL)
8910 #define SCU_EDCSCLR_NVMDBEC_Pos (2UL)
8911 #define SCU_EDCSCLR_NVMDBEC_Msk (0x4UL)
8912 #define SCU_EDCSCLR_RDBEC_Pos (0UL)
8913 #define SCU_EDCSCLR_RDBEC_Msk (0x1UL)
8915 #define SCU_EDCSTAT_RSBE_Pos (4UL)
8916 #define SCU_EDCSTAT_RSBE_Msk (0x10UL)
8917 #define SCU_EDCSTAT_NVMDBE_Pos (2UL)
8918 #define SCU_EDCSTAT_NVMDBE_Msk (0x4UL)
8919 #define SCU_EDCSTAT_RDBE_Pos (0UL)
8920 #define SCU_EDCSTAT_RDBE_Msk (0x1UL)
8922 #define SCU_EXICON0_MON_Trig_Sel_Pos (6UL)
8923 #define SCU_EXICON0_MON_Trig_Sel_Msk (0xc0UL)
8924 #define SCU_EXICON0_EXINT2_Pos (4UL)
8925 #define SCU_EXICON0_EXINT2_Msk (0x30UL)
8926 #define SCU_EXICON0_EXINT1_Pos (2UL)
8927 #define SCU_EXICON0_EXINT1_Msk (0xcUL)
8928 #define SCU_EXICON0_EXINT0_Pos (0UL)
8929 #define SCU_EXICON0_EXINT0_Msk (0x3UL)
8931 #define SCU_GPT12ICLR_CRC_Pos (5UL)
8932 #define SCU_GPT12ICLR_CRC_Msk (0x20UL)
8933 #define SCU_GPT12ICLR_T6C_Pos (4UL)
8934 #define SCU_GPT12ICLR_T6C_Msk (0x10UL)
8935 #define SCU_GPT12ICLR_T5C_Pos (3UL)
8936 #define SCU_GPT12ICLR_T5C_Msk (0x8UL)
8937 #define SCU_GPT12ICLR_T4C_Pos (2UL)
8938 #define SCU_GPT12ICLR_T4C_Msk (0x4UL)
8939 #define SCU_GPT12ICLR_T3C_Pos (1UL)
8940 #define SCU_GPT12ICLR_T3C_Msk (0x2UL)
8941 #define SCU_GPT12ICLR_T2C_Pos (0UL)
8942 #define SCU_GPT12ICLR_T2C_Msk (0x1UL)
8944 #define SCU_GPT12IEN_CRIE_Pos (5UL)
8945 #define SCU_GPT12IEN_CRIE_Msk (0x20UL)
8946 #define SCU_GPT12IEN_T6IE_Pos (4UL)
8947 #define SCU_GPT12IEN_T6IE_Msk (0x10UL)
8948 #define SCU_GPT12IEN_T5IE_Pos (3UL)
8949 #define SCU_GPT12IEN_T5IE_Msk (0x8UL)
8950 #define SCU_GPT12IEN_T4IE_Pos (2UL)
8951 #define SCU_GPT12IEN_T4IE_Msk (0x4UL)
8952 #define SCU_GPT12IEN_T3IE_Pos (1UL)
8953 #define SCU_GPT12IEN_T3IE_Msk (0x2UL)
8954 #define SCU_GPT12IEN_T2IE_Pos (0UL)
8955 #define SCU_GPT12IEN_T2IE_Msk (0x1UL)
8957 #define SCU_GPT12IRC_CR_Pos (5UL)
8958 #define SCU_GPT12IRC_CR_Msk (0x20UL)
8959 #define SCU_GPT12IRC_T6_Pos (4UL)
8960 #define SCU_GPT12IRC_T6_Msk (0x10UL)
8961 #define SCU_GPT12IRC_T5_Pos (3UL)
8962 #define SCU_GPT12IRC_T5_Msk (0x8UL)
8963 #define SCU_GPT12IRC_T4_Pos (2UL)
8964 #define SCU_GPT12IRC_T4_Msk (0x4UL)
8965 #define SCU_GPT12IRC_T3_Pos (1UL)
8966 #define SCU_GPT12IRC_T3_Msk (0x2UL)
8967 #define SCU_GPT12IRC_T2_Pos (0UL)
8968 #define SCU_GPT12IRC_T2_Msk (0x1UL)
8970 #define SCU_GPT12PISEL_T3_GPT12_SEL_Pos (5UL)
8971 #define SCU_GPT12PISEL_T3_GPT12_SEL_Msk (0x20UL)
8972 #define SCU_GPT12PISEL_TRIG_CONF_Pos (4UL)
8973 #define SCU_GPT12PISEL_TRIG_CONF_Msk (0x10UL)
8974 #define SCU_GPT12PISEL_GPT12_Pos (0UL)
8975 #define SCU_GPT12PISEL_GPT12_Msk (0xfUL)
8977 #define SCU_ID_PRODID_Pos (3UL)
8978 #define SCU_ID_PRODID_Msk (0xf8UL)
8979 #define SCU_ID_VERID_Pos (0UL)
8980 #define SCU_ID_VERID_Msk (0x7UL)
8982 #define SCU_IEN0_EA_Pos (7UL)
8983 #define SCU_IEN0_EA_Msk (0x80UL)
8985 #define SCU_IRCON0_MONF_Pos (7UL)
8986 #define SCU_IRCON0_MONF_Msk (0x80UL)
8987 #define SCU_IRCON0_MONR_Pos (6UL)
8988 #define SCU_IRCON0_MONR_Msk (0x40UL)
8989 #define SCU_IRCON0_EXINT2F_Pos (5UL)
8990 #define SCU_IRCON0_EXINT2F_Msk (0x20UL)
8991 #define SCU_IRCON0_EXINT2R_Pos (4UL)
8992 #define SCU_IRCON0_EXINT2R_Msk (0x10UL)
8993 #define SCU_IRCON0_EXINT1F_Pos (3UL)
8994 #define SCU_IRCON0_EXINT1F_Msk (0x8UL)
8995 #define SCU_IRCON0_EXINT1R_Pos (2UL)
8996 #define SCU_IRCON0_EXINT1R_Msk (0x4UL)
8997 #define SCU_IRCON0_EXINT0F_Pos (1UL)
8998 #define SCU_IRCON0_EXINT0F_Msk (0x2UL)
8999 #define SCU_IRCON0_EXINT0R_Pos (0UL)
9000 #define SCU_IRCON0_EXINT0R_Msk (0x1UL)
9002 #define SCU_IRCON0CLR_MONFC_Pos (7UL)
9003 #define SCU_IRCON0CLR_MONFC_Msk (0x80UL)
9004 #define SCU_IRCON0CLR_MONRC_Pos (6UL)
9005 #define SCU_IRCON0CLR_MONRC_Msk (0x40UL)
9006 #define SCU_IRCON0CLR_EXINT2FC_Pos (5UL)
9007 #define SCU_IRCON0CLR_EXINT2FC_Msk (0x20UL)
9008 #define SCU_IRCON0CLR_EXINT2RC_Pos (4UL)
9009 #define SCU_IRCON0CLR_EXINT2RC_Msk (0x10UL)
9010 #define SCU_IRCON0CLR_EXINT1FC_Pos (3UL)
9011 #define SCU_IRCON0CLR_EXINT1FC_Msk (0x8UL)
9012 #define SCU_IRCON0CLR_EXINT1RC_Pos (2UL)
9013 #define SCU_IRCON0CLR_EXINT1RC_Msk (0x4UL)
9014 #define SCU_IRCON0CLR_EXINT0FC_Pos (1UL)
9015 #define SCU_IRCON0CLR_EXINT0FC_Msk (0x2UL)
9016 #define SCU_IRCON0CLR_EXINT0RC_Pos (0UL)
9017 #define SCU_IRCON0CLR_EXINT0RC_Msk (0x1UL)
9019 #define SCU_IRCON1_RIR_Pos (2UL)
9020 #define SCU_IRCON1_RIR_Msk (0x4UL)
9021 #define SCU_IRCON1_TIR_Pos (1UL)
9022 #define SCU_IRCON1_TIR_Msk (0x2UL)
9023 #define SCU_IRCON1_EIR_Pos (0UL)
9024 #define SCU_IRCON1_EIR_Msk (0x1UL)
9026 #define SCU_IRCON1CLR_RIRC_Pos (2UL)
9027 #define SCU_IRCON1CLR_RIRC_Msk (0x4UL)
9028 #define SCU_IRCON1CLR_TIRC_Pos (1UL)
9029 #define SCU_IRCON1CLR_TIRC_Msk (0x2UL)
9030 #define SCU_IRCON1CLR_EIRC_Pos (0UL)
9031 #define SCU_IRCON1CLR_EIRC_Msk (0x1UL)
9033 #define SCU_IRCON2_RIR_Pos (2UL)
9034 #define SCU_IRCON2_RIR_Msk (0x4UL)
9035 #define SCU_IRCON2_TIR_Pos (1UL)
9036 #define SCU_IRCON2_TIR_Msk (0x2UL)
9037 #define SCU_IRCON2_EIR_Pos (0UL)
9038 #define SCU_IRCON2_EIR_Msk (0x1UL)
9040 #define SCU_IRCON2CLR_RIRC_Pos (2UL)
9041 #define SCU_IRCON2CLR_RIRC_Msk (0x4UL)
9042 #define SCU_IRCON2CLR_TIRC_Pos (1UL)
9043 #define SCU_IRCON2CLR_TIRC_Msk (0x2UL)
9044 #define SCU_IRCON2CLR_EIRC_Pos (0UL)
9045 #define SCU_IRCON2CLR_EIRC_Msk (0x1UL)
9047 #define SCU_IRCON3_CCU6SR1_Pos (4UL)
9048 #define SCU_IRCON3_CCU6SR1_Msk (0x10UL)
9049 #define SCU_IRCON3_CCU6SR0_Pos (0UL)
9050 #define SCU_IRCON3_CCU6SR0_Msk (0x1UL)
9052 #define SCU_IRCON3CLR_CCU6SR1C_Pos (4UL)
9053 #define SCU_IRCON3CLR_CCU6SR1C_Msk (0x10UL)
9054 #define SCU_IRCON3CLR_CCU6SR0C_Pos (0UL)
9055 #define SCU_IRCON3CLR_CCU6SR0C_Msk (0x1UL)
9057 #define SCU_IRCON4_CCU6SR3_Pos (4UL)
9058 #define SCU_IRCON4_CCU6SR3_Msk (0x10UL)
9059 #define SCU_IRCON4_CCU6SR2_Pos (0UL)
9060 #define SCU_IRCON4_CCU6SR2_Msk (0x1UL)
9062 #define SCU_IRCON4CLR_CCU6SR3C_Pos (4UL)
9063 #define SCU_IRCON4CLR_CCU6SR3C_Msk (0x10UL)
9064 #define SCU_IRCON4CLR_CCU6SR2C_Pos (0UL)
9065 #define SCU_IRCON4CLR_CCU6SR2C_Msk (0x1UL)
9067 #define SCU_LINSCLR_BRKC_Pos (3UL)
9068 #define SCU_LINSCLR_BRKC_Msk (0x8UL)
9069 #define SCU_LINSCLR_EOFSYNC_Pos (4UL)
9070 #define SCU_LINSCLR_EOFSYNC_Msk (0x10UL)
9071 #define SCU_LINSCLR_ERRSYNC_Pos (5UL)
9072 #define SCU_LINSCLR_ERRSYNC_Msk (0x20UL)
9074 #define SCU_LINST_BRDIS_Pos (0UL)
9075 #define SCU_LINST_BRDIS_Msk (0x1UL)
9076 #define SCU_LINST_BGSEL_Pos (1UL)
9077 #define SCU_LINST_BGSEL_Msk (0x6UL)
9078 #define SCU_LINST_BRK_Pos (3UL)
9079 #define SCU_LINST_BRK_Msk (0x8UL)
9080 #define SCU_LINST_EOFSYN_Pos (4UL)
9081 #define SCU_LINST_EOFSYN_Msk (0x10UL)
9082 #define SCU_LINST_ERRSYN_Pos (5UL)
9083 #define SCU_LINST_ERRSYN_Msk (0x20UL)
9084 #define SCU_LINST_SYNEN_Pos (6UL)
9085 #define SCU_LINST_SYNEN_Msk (0x40UL)
9087 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Pos (6UL)
9088 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Msk (0x40UL)
9089 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Pos (5UL)
9090 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Msk (0x20UL)
9091 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Pos (4UL)
9092 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Msk (0x10UL)
9093 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Pos (3UL)
9094 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Msk (0x8UL)
9095 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Pos (2UL)
9096 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Msk (0x4UL)
9097 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Pos (1UL)
9098 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Msk (0x2UL)
9099 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Pos (0UL)
9100 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Msk (0x1UL)
9102 #define SCU_MEMSTAT_SASTATUS_Pos (6UL)
9103 #define SCU_MEMSTAT_SASTATUS_Msk (0xc0UL)
9104 #define SCU_MEMSTAT_SECTORINFO_Pos (0UL)
9105 #define SCU_MEMSTAT_SECTORINFO_Msk (0x3fUL)
9107 #define SCU_MODIEN1_TIEN1_Pos (7UL)
9108 #define SCU_MODIEN1_TIEN1_Msk (0x80UL)
9109 #define SCU_MODIEN1_RIEN1_Pos (6UL)
9110 #define SCU_MODIEN1_RIEN1_Msk (0x40UL)
9111 #define SCU_MODIEN1_RIREN1_Pos (2UL)
9112 #define SCU_MODIEN1_RIREN1_Msk (0x4UL)
9113 #define SCU_MODIEN1_TIREN1_Pos (1UL)
9114 #define SCU_MODIEN1_TIREN1_Msk (0x2UL)
9115 #define SCU_MODIEN1_EIREN1_Pos (0UL)
9116 #define SCU_MODIEN1_EIREN1_Msk (0x1UL)
9118 #define SCU_MODIEN2_TIEN2_Pos (7UL)
9119 #define SCU_MODIEN2_TIEN2_Msk (0x80UL)
9120 #define SCU_MODIEN2_RIEN2_Pos (6UL)
9121 #define SCU_MODIEN2_RIEN2_Msk (0x40UL)
9122 #define SCU_MODIEN2_EXINT2_EN_Pos (5UL)
9123 #define SCU_MODIEN2_EXINT2_EN_Msk (0x20UL)
9124 #define SCU_MODIEN2_RIREN2_Pos (2UL)
9125 #define SCU_MODIEN2_RIREN2_Msk (0x4UL)
9126 #define SCU_MODIEN2_TIREN2_Pos (1UL)
9127 #define SCU_MODIEN2_TIREN2_Msk (0x2UL)
9128 #define SCU_MODIEN2_EIREN2_Pos (0UL)
9129 #define SCU_MODIEN2_EIREN2_Msk (0x1UL)
9131 #define SCU_MODIEN3_MONSTS_Pos (5UL)
9132 #define SCU_MODIEN3_MONSTS_Msk (0x20UL)
9133 #define SCU_MODIEN3_MONIE_Pos (4UL)
9134 #define SCU_MODIEN3_MONIE_Msk (0x10UL)
9135 #define SCU_MODIEN3_IE0_Pos (0UL)
9136 #define SCU_MODIEN3_IE0_Msk (0x1UL)
9138 #define SCU_MODIEN4_IE1_Pos (0UL)
9139 #define SCU_MODIEN4_IE1_Msk (0x1UL)
9141 #define SCU_MODPISEL_U_TX_CONDIS_Pos (7UL)
9142 #define SCU_MODPISEL_U_TX_CONDIS_Msk (0x80UL)
9143 #define SCU_MODPISEL_URIOS1_Pos (6UL)
9144 #define SCU_MODPISEL_URIOS1_Msk (0x40UL)
9145 #define SCU_MODPISEL_EXINT2IS_Pos (4UL)
9146 #define SCU_MODPISEL_EXINT2IS_Msk (0x30UL)
9147 #define SCU_MODPISEL_EXINT1IS_Pos (2UL)
9148 #define SCU_MODPISEL_EXINT1IS_Msk (0xcUL)
9149 #define SCU_MODPISEL_EXINT0IS_Pos (0UL)
9150 #define SCU_MODPISEL_EXINT0IS_Msk (0x3UL)
9152 #define SCU_MODPISEL1_T21EXCON_Pos (7UL)
9153 #define SCU_MODPISEL1_T21EXCON_Msk (0x80UL)
9154 #define SCU_MODPISEL1_T2EXCON_Pos (6UL)
9155 #define SCU_MODPISEL1_T2EXCON_Msk (0x40UL)
9156 #define SCU_MODPISEL1_GPT12CAPINB_Pos (0UL)
9157 #define SCU_MODPISEL1_GPT12CAPINB_Msk (0x1UL)
9159 #define SCU_MODPISEL2_T21EXIS_Pos (6UL)
9160 #define SCU_MODPISEL2_T21EXIS_Msk (0xc0UL)
9161 #define SCU_MODPISEL2_T2EXIS_Pos (4UL)
9162 #define SCU_MODPISEL2_T2EXIS_Msk (0x30UL)
9163 #define SCU_MODPISEL2_T21IS_Pos (2UL)
9164 #define SCU_MODPISEL2_T21IS_Msk (0xcUL)
9165 #define SCU_MODPISEL2_T2IS_Pos (0UL)
9166 #define SCU_MODPISEL2_T2IS_Msk (0x3UL)
9168 #define SCU_MODPISEL3_URIOS2_Pos (6UL)
9169 #define SCU_MODPISEL3_URIOS2_Msk (0x40UL)
9171 #define SCU_MODSUSP1_T21_SUSP_Pos (6UL)
9172 #define SCU_MODSUSP1_T21_SUSP_Msk (0x40UL)
9173 #define SCU_MODSUSP1_GPT12_SUSP_Pos (4UL)
9174 #define SCU_MODSUSP1_GPT12_SUSP_Msk (0x10UL)
9175 #define SCU_MODSUSP1_T2_SUSP_Pos (3UL)
9176 #define SCU_MODSUSP1_T2_SUSP_Msk (0x8UL)
9177 #define SCU_MODSUSP1_T13SUSP_Pos (2UL)
9178 #define SCU_MODSUSP1_T13SUSP_Msk (0x4UL)
9179 #define SCU_MODSUSP1_T12SUSP_Pos (1UL)
9180 #define SCU_MODSUSP1_T12SUSP_Msk (0x2UL)
9181 #define SCU_MODSUSP1_WDTSUSP_Pos (0UL)
9182 #define SCU_MODSUSP1_WDTSUSP_Msk (0x1UL)
9184 #define SCU_MODSUSP2_ADC1_SUSP_Pos (2UL)
9185 #define SCU_MODSUSP2_ADC1_SUSP_Msk (0x4UL)
9186 #define SCU_MODSUSP2_MU_SUSP_Pos (1UL)
9187 #define SCU_MODSUSP2_MU_SUSP_Msk (0x2UL)
9188 #define SCU_MODSUSP2_T3_SUSP_Pos (0UL)
9189 #define SCU_MODSUSP2_T3_SUSP_Msk (0x1UL)
9191 #define SCU_NMICLR_NMISUPC_Pos (7UL)
9192 #define SCU_NMICLR_NMISUPC_Msk (0x80UL)
9193 #define SCU_NMICLR_NMIECCC_Pos (6UL)
9194 #define SCU_NMICLR_NMIECCC_Msk (0x40UL)
9195 #define SCU_NMICLR_NMIMAPC_Pos (5UL)
9196 #define SCU_NMICLR_NMIMAPC_Msk (0x20UL)
9197 #define SCU_NMICLR_NMIOWDC_Pos (4UL)
9198 #define SCU_NMICLR_NMIOWDC_Msk (0x10UL)
9199 #define SCU_NMICLR_NMIOTC_Pos (3UL)
9200 #define SCU_NMICLR_NMIOTC_Msk (0x8UL)
9201 #define SCU_NMICLR_NMINVMC_Pos (2UL)
9202 #define SCU_NMICLR_NMINVMC_Msk (0x4UL)
9203 #define SCU_NMICLR_NMIPLLC_Pos (1UL)
9204 #define SCU_NMICLR_NMIPLLC_Msk (0x2UL)
9205 #define SCU_NMICLR_NMIWDTC_Pos (0UL)
9206 #define SCU_NMICLR_NMIWDTC_Msk (0x1UL)
9208 #define SCU_NMICON_NMISUP_Pos (7UL)
9209 #define SCU_NMICON_NMISUP_Msk (0x80UL)
9210 #define SCU_NMICON_NMIECC_Pos (6UL)
9211 #define SCU_NMICON_NMIECC_Msk (0x40UL)
9212 #define SCU_NMICON_NMIMAP_Pos (5UL)
9213 #define SCU_NMICON_NMIMAP_Msk (0x20UL)
9214 #define SCU_NMICON_NMIOWD_Pos (4UL)
9215 #define SCU_NMICON_NMIOWD_Msk (0x10UL)
9216 #define SCU_NMICON_NMIOT_Pos (3UL)
9217 #define SCU_NMICON_NMIOT_Msk (0x8UL)
9218 #define SCU_NMICON_NMINVM_Pos (2UL)
9219 #define SCU_NMICON_NMINVM_Msk (0x4UL)
9220 #define SCU_NMICON_NMIPLL_Pos (1UL)
9221 #define SCU_NMICON_NMIPLL_Msk (0x2UL)
9222 #define SCU_NMICON_NMIWDT_Pos (0UL)
9223 #define SCU_NMICON_NMIWDT_Msk (0x1UL)
9225 #define SCU_NMISR_FNMISUP_Pos (7UL)
9226 #define SCU_NMISR_FNMISUP_Msk (0x80UL)
9227 #define SCU_NMISR_FNMIECC_Pos (6UL)
9228 #define SCU_NMISR_FNMIECC_Msk (0x40UL)
9229 #define SCU_NMISR_FNMIMAP_Pos (5UL)
9230 #define SCU_NMISR_FNMIMAP_Msk (0x20UL)
9231 #define SCU_NMISR_FNMIOWD_Pos (4UL)
9232 #define SCU_NMISR_FNMIOWD_Msk (0x10UL)
9233 #define SCU_NMISR_FNMIOT_Pos (3UL)
9234 #define SCU_NMISR_FNMIOT_Msk (0x8UL)
9235 #define SCU_NMISR_FNMINVM_Pos (2UL)
9236 #define SCU_NMISR_FNMINVM_Msk (0x4UL)
9237 #define SCU_NMISR_FNMIPLL_Pos (1UL)
9238 #define SCU_NMISR_FNMIPLL_Msk (0x2UL)
9239 #define SCU_NMISR_FNMIWDT_Pos (0UL)
9240 #define SCU_NMISR_FNMIWDT_Msk (0x1UL)
9242 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Pos (3UL)
9243 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Msk (0x8UL)
9244 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Pos (2UL)
9245 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Msk (0x4UL)
9246 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Pos (1UL)
9247 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Msk (0x2UL)
9248 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Pos (0UL)
9249 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Msk (0x1UL)
9251 #define SCU_OSC_CON_OSCTRIM_8_Pos (7UL)
9252 #define SCU_OSC_CON_OSCTRIM_8_Msk (0x80UL)
9253 #define SCU_OSC_CON_XPD_Pos (4UL)
9254 #define SCU_OSC_CON_XPD_Msk (0x10UL)
9255 #define SCU_OSC_CON_OSC2L_Pos (3UL)
9256 #define SCU_OSC_CON_OSC2L_Msk (0x8UL)
9257 #define SCU_OSC_CON_OSCWDTRST_Pos (2UL)
9258 #define SCU_OSC_CON_OSCWDTRST_Msk (0x4UL)
9259 #define SCU_OSC_CON_OSCSS_Pos (0UL)
9260 #define SCU_OSC_CON_OSCSS_Msk (0x3UL)
9262 #define SCU_P0_POCON0_PDM1_Pos (4UL)
9263 #define SCU_P0_POCON0_PDM1_Msk (0x70UL)
9264 #define SCU_P0_POCON0_PDM0_Pos (0UL)
9265 #define SCU_P0_POCON0_PDM0_Msk (0x7UL)
9267 #define SCU_P0_POCON1_PDM3_Pos (4UL)
9268 #define SCU_P0_POCON1_PDM3_Msk (0x70UL)
9269 #define SCU_P0_POCON1_PDM2_Pos (0UL)
9270 #define SCU_P0_POCON1_PDM2_Msk (0x7UL)
9272 #define SCU_P0_POCON2_PDM4_Pos (0UL)
9273 #define SCU_P0_POCON2_PDM4_Msk (0x7UL)
9275 #define SCU_P1_POCON0_PDM1_Pos (4UL)
9276 #define SCU_P1_POCON0_PDM1_Msk (0x70UL)
9277 #define SCU_P1_POCON0_PDM0_Pos (0UL)
9278 #define SCU_P1_POCON0_PDM0_Msk (0x7UL)
9280 #define SCU_P1_POCON1_PDM3_Pos (4UL)
9281 #define SCU_P1_POCON1_PDM3_Msk (0x70UL)
9282 #define SCU_P1_POCON1_PDM2_Pos (0UL)
9283 #define SCU_P1_POCON1_PDM2_Msk (0x7UL)
9285 #define SCU_P1_POCON2_PDM4_Pos (0UL)
9286 #define SCU_P1_POCON2_PDM4_Msk (0x7UL)
9288 #define SCU_PASSWD_PASS_Pos (3UL)
9289 #define SCU_PASSWD_PASS_Msk (0xf8UL)
9290 #define SCU_PASSWD_PROTECT_S_Pos (2UL)
9291 #define SCU_PASSWD_PROTECT_S_Msk (0x4UL)
9292 #define SCU_PASSWD_MODE_Pos (0UL)
9293 #define SCU_PASSWD_MODE_Msk (0x3UL)
9295 #define SCU_PLL_CON_NDIV_Pos (4UL)
9296 #define SCU_PLL_CON_NDIV_Msk (0xf0UL)
9297 #define SCU_PLL_CON_VCOBYP_Pos (3UL)
9298 #define SCU_PLL_CON_VCOBYP_Msk (0x8UL)
9299 #define SCU_PLL_CON_OSCDISC_Pos (2UL)
9300 #define SCU_PLL_CON_OSCDISC_Msk (0x4UL)
9301 #define SCU_PLL_CON_RESLD_Pos (1UL)
9302 #define SCU_PLL_CON_RESLD_Msk (0x2UL)
9303 #define SCU_PLL_CON_LOCK_Pos (0UL)
9304 #define SCU_PLL_CON_LOCK_Msk (0x1UL)
9306 #define SCU_PMCON0_SD_Pos (3UL)
9307 #define SCU_PMCON0_SD_Msk (0x8UL)
9308 #define SCU_PMCON0_PD_Pos (2UL)
9309 #define SCU_PMCON0_PD_Msk (0x4UL)
9310 #define SCU_PMCON0_SL_Pos (1UL)
9311 #define SCU_PMCON0_SL_Msk (0x2UL)
9312 #define SCU_PMCON0_XTAL_ON_Pos (0UL)
9313 #define SCU_PMCON0_XTAL_ON_Msk (0x1UL)
9315 #define SCU_PMCON1_GPT12_DIS_Pos (4UL)
9316 #define SCU_PMCON1_GPT12_DIS_Msk (0x10UL)
9317 #define SCU_PMCON1_T2_DIS_Pos (3UL)
9318 #define SCU_PMCON1_T2_DIS_Msk (0x8UL)
9319 #define SCU_PMCON1_CCU6_DIS_Pos (2UL)
9320 #define SCU_PMCON1_CCU6_DIS_Msk (0x4UL)
9321 #define SCU_PMCON1_SSC1_DIS_Pos (1UL)
9322 #define SCU_PMCON1_SSC1_DIS_Msk (0x2UL)
9323 #define SCU_PMCON1_ADC1_DIS_Pos (0UL)
9324 #define SCU_PMCON1_ADC1_DIS_Msk (0x1UL)
9326 #define SCU_PMCON2_T3_DIS_Pos (5UL)
9327 #define SCU_PMCON2_T3_DIS_Msk (0x20UL)
9328 #define SCU_PMCON2_T21_DIS_Pos (3UL)
9329 #define SCU_PMCON2_T21_DIS_Msk (0x8UL)
9330 #define SCU_PMCON2_SSC2_DIS_Pos (1UL)
9331 #define SCU_PMCON2_SSC2_DIS_Msk (0x2UL)
9333 #define SCU_RSTCON_LOCKUP_EN_Pos (7UL)
9334 #define SCU_RSTCON_LOCKUP_EN_Msk (0x80UL)
9335 #define SCU_RSTCON_LOCKUP_Pos (0UL)
9336 #define SCU_RSTCON_LOCKUP_Msk (0x1UL)
9338 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Pos (2UL)
9339 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Msk (0x4UL)
9340 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Pos (1UL)
9341 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Msk (0x2UL)
9342 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Pos (0UL)
9343 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Msk (0x1UL)
9345 #define SCU_SYSCON0_SYSCLKSEL_Pos (6UL)
9346 #define SCU_SYSCON0_SYSCLKSEL_Msk (0xc0UL)
9347 #define SCU_SYSCON0_NVMCLKFAC_Pos (4UL)
9348 #define SCU_SYSCON0_NVMCLKFAC_Msk (0x30UL)
9350 #define SCU_TCCR_TCC_Pos (0UL)
9351 #define SCU_TCCR_TCC_Msk (0x3UL)
9353 #define SCU_WDTCON_WINBEN_Pos (5UL)
9354 #define SCU_WDTCON_WINBEN_Msk (0x20UL)
9355 #define SCU_WDTCON_WDTPR_Pos (4UL)
9356 #define SCU_WDTCON_WDTPR_Msk (0x10UL)
9357 #define SCU_WDTCON_WDTEN_Pos (2UL)
9358 #define SCU_WDTCON_WDTEN_Msk (0x4UL)
9359 #define SCU_WDTCON_WDTRS_Pos (1UL)
9360 #define SCU_WDTCON_WDTRS_Msk (0x2UL)
9361 #define SCU_WDTCON_WDTIN_Pos (0UL)
9362 #define SCU_WDTCON_WDTIN_Msk (0x1UL)
9364 #define SCU_WDTH_WDT_Pos (0UL)
9365 #define SCU_WDTH_WDT_Msk (0xffUL)
9367 #define SCU_WDTL_WDT_Pos (0UL)
9368 #define SCU_WDTL_WDT_Msk (0xffUL)
9370 #define SCU_WDTREL_WDTREL_Pos (0UL)
9371 #define SCU_WDTREL_WDTREL_Msk (0xffUL)
9373 #define SCU_WDTWINB_WDTWINB_Pos (0UL)
9374 #define SCU_WDTWINB_WDTWINB_Msk (0xffUL)
9382 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos (0UL)
9383 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk (0x1UL)
9385 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Pos (8UL)
9386 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Msk (0x3f00UL)
9387 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Pos (0UL)
9388 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Msk (0x3fUL)
9390 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos (30UL)
9391 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk (0xc0000000UL)
9392 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos (24UL)
9393 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk (0x3f000000UL)
9394 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos (22UL)
9395 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk (0xc00000UL)
9396 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos (16UL)
9397 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk (0x3f0000UL)
9398 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos (14UL)
9399 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk (0xc000UL)
9400 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos (8UL)
9401 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk (0x3f00UL)
9402 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos (6UL)
9403 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk (0xc0UL)
9404 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos (0UL)
9405 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk (0x3fUL)
9407 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Pos (20UL)
9408 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Msk (0x100000UL)
9409 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Pos (19UL)
9410 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Msk (0x80000UL)
9411 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Pos (18UL)
9412 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Msk (0x40000UL)
9413 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Pos (17UL)
9414 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Msk (0x20000UL)
9415 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos (16UL)
9416 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk (0x10000UL)
9417 #define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos (15UL)
9418 #define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk (0x8000UL)
9419 #define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos (14UL)
9420 #define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk (0x4000UL)
9421 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos (13UL)
9422 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk (0x2000UL)
9423 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos (12UL)
9424 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk (0x1000UL)
9425 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos (11UL)
9426 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk (0x800UL)
9427 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos (10UL)
9428 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk (0x400UL)
9429 #define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos (5UL)
9430 #define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk (0x20UL)
9431 #define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos (4UL)
9432 #define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk (0x10UL)
9433 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos (3UL)
9434 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk (0x8UL)
9435 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos (2UL)
9436 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk (0x4UL)
9437 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos (1UL)
9438 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk (0x2UL)
9439 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos (0UL)
9440 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk (0x1UL)
9442 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Pos (28UL)
9443 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Msk (0x10000000UL)
9444 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Pos (27UL)
9445 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Msk (0x8000000UL)
9446 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Pos (26UL)
9447 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Msk (0x4000000UL)
9448 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Pos (25UL)
9449 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Msk (0x2000000UL)
9450 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Pos (24UL)
9451 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Msk (0x1000000UL)
9452 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Pos (20UL)
9453 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Msk (0x100000UL)
9454 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Pos (19UL)
9455 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Msk (0x80000UL)
9456 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Pos (18UL)
9457 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Msk (0x40000UL)
9458 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Pos (17UL)
9459 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Msk (0x20000UL)
9460 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos (16UL)
9461 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk (0x10000UL)
9462 #define SCUPM_BDRV_IS_HS3_OC_IS_Pos (15UL)
9463 #define SCUPM_BDRV_IS_HS3_OC_IS_Msk (0x8000UL)
9464 #define SCUPM_BDRV_IS_LS3_OC_IS_Pos (14UL)
9465 #define SCUPM_BDRV_IS_LS3_OC_IS_Msk (0x4000UL)
9466 #define SCUPM_BDRV_IS_HS2_OC_IS_Pos (13UL)
9467 #define SCUPM_BDRV_IS_HS2_OC_IS_Msk (0x2000UL)
9468 #define SCUPM_BDRV_IS_HS1_OC_IS_Pos (12UL)
9469 #define SCUPM_BDRV_IS_HS1_OC_IS_Msk (0x1000UL)
9470 #define SCUPM_BDRV_IS_LS2_OC_IS_Pos (11UL)
9471 #define SCUPM_BDRV_IS_LS2_OC_IS_Msk (0x800UL)
9472 #define SCUPM_BDRV_IS_LS1_OC_IS_Pos (10UL)
9473 #define SCUPM_BDRV_IS_LS1_OC_IS_Msk (0x400UL)
9474 #define SCUPM_BDRV_IS_HS3_DS_IS_Pos (5UL)
9475 #define SCUPM_BDRV_IS_HS3_DS_IS_Msk (0x20UL)
9476 #define SCUPM_BDRV_IS_LS3_DS_IS_Pos (4UL)
9477 #define SCUPM_BDRV_IS_LS3_DS_IS_Msk (0x10UL)
9478 #define SCUPM_BDRV_IS_HS2_DS_IS_Pos (3UL)
9479 #define SCUPM_BDRV_IS_HS2_DS_IS_Msk (0x8UL)
9480 #define SCUPM_BDRV_IS_HS1_DS_IS_Pos (2UL)
9481 #define SCUPM_BDRV_IS_HS1_DS_IS_Msk (0x4UL)
9482 #define SCUPM_BDRV_IS_LS2_DS_IS_Pos (1UL)
9483 #define SCUPM_BDRV_IS_LS2_DS_IS_Msk (0x2UL)
9484 #define SCUPM_BDRV_IS_LS1_DS_IS_Pos (0UL)
9485 #define SCUPM_BDRV_IS_LS1_DS_IS_Msk (0x1UL)
9487 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Pos (28UL)
9488 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Msk (0x10000000UL)
9489 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Pos (27UL)
9490 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Msk (0x8000000UL)
9491 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Pos (26UL)
9492 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Msk (0x4000000UL)
9493 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Pos (25UL)
9494 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Msk (0x2000000UL)
9495 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Pos (24UL)
9496 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Msk (0x1000000UL)
9497 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Pos (20UL)
9498 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Msk (0x100000UL)
9499 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Pos (19UL)
9500 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Msk (0x80000UL)
9501 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Pos (18UL)
9502 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Msk (0x40000UL)
9503 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Pos (17UL)
9504 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Msk (0x20000UL)
9505 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos (16UL)
9506 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk (0x10000UL)
9507 #define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Pos (15UL)
9508 #define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk (0x8000UL)
9509 #define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Pos (14UL)
9510 #define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk (0x4000UL)
9511 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos (13UL)
9512 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk (0x2000UL)
9513 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos (12UL)
9514 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk (0x1000UL)
9515 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos (11UL)
9516 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk (0x800UL)
9517 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos (10UL)
9518 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk (0x400UL)
9519 #define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Pos (5UL)
9520 #define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk (0x20UL)
9521 #define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Pos (4UL)
9522 #define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk (0x10UL)
9523 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos (3UL)
9524 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk (0x8UL)
9525 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos (2UL)
9526 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk (0x4UL)
9527 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos (1UL)
9528 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk (0x2UL)
9529 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos (0UL)
9530 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk (0x1UL)
9532 #define SCUPM_BFSTS_SBFSTS_Pos (1UL)
9533 #define SCUPM_BFSTS_SBFSTS_Msk (0x2UL)
9534 #define SCUPM_BFSTS_DBFSTS_Pos (0UL)
9535 #define SCUPM_BFSTS_DBFSTS_Msk (0x1UL)
9537 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Pos (1UL)
9538 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Msk (0x2UL)
9539 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Pos (0UL)
9540 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Msk (0x1UL)
9542 #define SCUPM_DBFA_DBFA_Pos (0UL)
9543 #define SCUPM_DBFA_DBFA_Msk (0xffffffffUL)
9545 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos (26UL)
9546 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk (0x4000000UL)
9547 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos (25UL)
9548 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk (0x2000000UL)
9549 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Pos (24UL)
9550 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Msk (0x1000000UL)
9551 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Pos (14UL)
9552 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Msk (0x4000UL)
9553 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos (8UL)
9554 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk (0x100UL)
9555 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos (7UL)
9556 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk (0x80UL)
9557 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos (1UL)
9558 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk (0x2UL)
9560 #define SCUPM_SBFA_SBFA_Pos (0UL)
9561 #define SCUPM_SBFA_SBFA_Msk (0xffffffffUL)
9563 #define SCUPM_STCALIB_STCALIB_Pos (0UL)
9564 #define SCUPM_STCALIB_STCALIB_Msk (0x3ffffffUL)
9566 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Pos (23UL)
9567 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Msk (0x800000UL)
9568 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Pos (22UL)
9569 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Msk (0x400000UL)
9570 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Pos (21UL)
9571 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Msk (0x200000UL)
9572 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Pos (20UL)
9573 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Msk (0x100000UL)
9574 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Pos (19UL)
9575 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Msk (0x80000UL)
9576 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Pos (18UL)
9577 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Msk (0x40000UL)
9578 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Pos (17UL)
9579 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Msk (0x20000UL)
9580 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Pos (16UL)
9581 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Msk (0x10000UL)
9582 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Pos (15UL)
9583 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Msk (0x8000UL)
9584 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Pos (14UL)
9585 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Msk (0x4000UL)
9586 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Pos (13UL)
9587 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Msk (0x2000UL)
9588 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Pos (12UL)
9589 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Msk (0x1000UL)
9590 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Pos (11UL)
9591 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Msk (0x800UL)
9592 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Pos (10UL)
9593 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Msk (0x400UL)
9594 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Pos (9UL)
9595 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Msk (0x200UL)
9596 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Pos (8UL)
9597 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Msk (0x100UL)
9598 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Pos (7UL)
9599 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Msk (0x80UL)
9600 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Pos (6UL)
9601 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Msk (0x40UL)
9602 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Pos (2UL)
9603 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Msk (0x4UL)
9604 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Pos (1UL)
9605 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Msk (0x2UL)
9606 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Pos (0UL)
9607 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Msk (0x1UL)
9609 #define SCUPM_SYS_IS_PHW_ZCHI_STS_Pos (29UL)
9610 #define SCUPM_SYS_IS_PHW_ZCHI_STS_Msk (0x20000000UL)
9611 #define SCUPM_SYS_IS_PHW_ZCLOW_STS_Pos (28UL)
9612 #define SCUPM_SYS_IS_PHW_ZCLOW_STS_Msk (0x10000000UL)
9613 #define SCUPM_SYS_IS_PHV_ZCHI_STS_Pos (27UL)
9614 #define SCUPM_SYS_IS_PHV_ZCHI_STS_Msk (0x8000000UL)
9615 #define SCUPM_SYS_IS_PHV_ZCLOW_STS_Pos (26UL)
9616 #define SCUPM_SYS_IS_PHV_ZCLOW_STS_Msk (0x4000000UL)
9617 #define SCUPM_SYS_IS_PHU_ZCHI_STS_Pos (25UL)
9618 #define SCUPM_SYS_IS_PHU_ZCHI_STS_Msk (0x2000000UL)
9619 #define SCUPM_SYS_IS_PHU_ZCLOW_STS_Pos (24UL)
9620 #define SCUPM_SYS_IS_PHU_ZCLOW_STS_Msk (0x1000000UL)
9621 #define SCUPM_SYS_IS_ADC4_EOC_IS_Pos (23UL)
9622 #define SCUPM_SYS_IS_ADC4_EOC_IS_Msk (0x800000UL)
9623 #define SCUPM_SYS_IS_ADC3_EOC_IS_Pos (22UL)
9624 #define SCUPM_SYS_IS_ADC3_EOC_IS_Msk (0x400000UL)
9625 #define SCUPM_SYS_IS_PHW_ZCHI_IS_Pos (21UL)
9626 #define SCUPM_SYS_IS_PHW_ZCHI_IS_Msk (0x200000UL)
9627 #define SCUPM_SYS_IS_PHW_ZCLOW_IS_Pos (20UL)
9628 #define SCUPM_SYS_IS_PHW_ZCLOW_IS_Msk (0x100000UL)
9629 #define SCUPM_SYS_IS_PHV_ZCHI_IS_Pos (19UL)
9630 #define SCUPM_SYS_IS_PHV_ZCHI_IS_Msk (0x80000UL)
9631 #define SCUPM_SYS_IS_PHV_ZCLOW_IS_Pos (18UL)
9632 #define SCUPM_SYS_IS_PHV_ZCLOW_IS_Msk (0x40000UL)
9633 #define SCUPM_SYS_IS_PHU_ZCHI_IS_Pos (17UL)
9634 #define SCUPM_SYS_IS_PHU_ZCHI_IS_Msk (0x20000UL)
9635 #define SCUPM_SYS_IS_PHU_ZCLOW_IS_Pos (16UL)
9636 #define SCUPM_SYS_IS_PHU_ZCLOW_IS_Msk (0x10000UL)
9637 #define SCUPM_SYS_IS_ADC2_ESM_IS_Pos (15UL)
9638 #define SCUPM_SYS_IS_ADC2_ESM_IS_Msk (0x8000UL)
9639 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Pos (14UL)
9640 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Msk (0x4000UL)
9641 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Pos (13UL)
9642 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Msk (0x2000UL)
9643 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Pos (12UL)
9644 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Msk (0x1000UL)
9645 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Pos (11UL)
9646 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Msk (0x800UL)
9647 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Pos (10UL)
9648 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Msk (0x400UL)
9649 #define SCUPM_SYS_IS_SYS_OT_IS_Pos (9UL)
9650 #define SCUPM_SYS_IS_SYS_OT_IS_Msk (0x200UL)
9651 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Pos (8UL)
9652 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Msk (0x100UL)
9653 #define SCUPM_SYS_IS_PMU_OT_IS_Pos (7UL)
9654 #define SCUPM_SYS_IS_PMU_OT_IS_Msk (0x80UL)
9655 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Pos (6UL)
9656 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Msk (0x40UL)
9657 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Pos (2UL)
9658 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Msk (0x4UL)
9659 #define SCUPM_SYS_IS_LIN_OT_IS_Pos (1UL)
9660 #define SCUPM_SYS_IS_LIN_OT_IS_Msk (0x2UL)
9661 #define SCUPM_SYS_IS_LIN_OC_IS_Pos (0UL)
9662 #define SCUPM_SYS_IS_LIN_OC_IS_Msk (0x1UL)
9664 #define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Pos (29UL)
9665 #define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Msk (0x20000000UL)
9666 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Pos (28UL)
9667 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Msk (0x10000000UL)
9668 #define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Pos (27UL)
9669 #define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Msk (0x8000000UL)
9670 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Pos (26UL)
9671 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Msk (0x4000000UL)
9672 #define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Pos (25UL)
9673 #define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Msk (0x2000000UL)
9674 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Pos (24UL)
9675 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Msk (0x1000000UL)
9676 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Pos (23UL)
9677 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Msk (0x800000UL)
9678 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Pos (22UL)
9679 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Msk (0x400000UL)
9680 #define SCUPM_SYS_ISCLR_PHW_ZCHI_ICLR_Pos (21UL)
9681 #define SCUPM_SYS_ISCLR_PHW_ZCHI_ICLR_Msk (0x200000UL)
9682 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_ICLR_Pos (20UL)
9683 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_ICLR_Msk (0x100000UL)
9684 #define SCUPM_SYS_ISCLR_PHV_ZCHI_ICLR_Pos (19UL)
9685 #define SCUPM_SYS_ISCLR_PHV_ZCHI_ICLR_Msk (0x80000UL)
9686 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_ICLR_Pos (18UL)
9687 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_ICLR_Msk (0x40000UL)
9688 #define SCUPM_SYS_ISCLR_PHU_ZCHI_ICLR_Pos (17UL)
9689 #define SCUPM_SYS_ISCLR_PHU_ZCHI_ICLR_Msk (0x20000UL)
9690 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_ICLR_Pos (16UL)
9691 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_ICLR_Msk (0x10000UL)
9692 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Pos (15UL)
9693 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Msk (0x8000UL)
9694 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Pos (14UL)
9695 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Msk (0x4000UL)
9696 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Pos (13UL)
9697 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Msk (0x2000UL)
9698 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Pos (12UL)
9699 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Msk (0x1000UL)
9700 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Pos (11UL)
9701 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Msk (0x800UL)
9702 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Pos (10UL)
9703 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Msk (0x400UL)
9704 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Pos (9UL)
9705 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Msk (0x200UL)
9706 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Pos (8UL)
9707 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Msk (0x100UL)
9708 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Pos (7UL)
9709 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Msk (0x80UL)
9710 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Pos (6UL)
9711 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Msk (0x40UL)
9712 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Pos (2UL)
9713 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Msk (0x4UL)
9714 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Pos (1UL)
9715 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Msk (0x2UL)
9716 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Pos (0UL)
9717 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Msk (0x1UL)
9719 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Pos (23UL)
9720 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Msk (0x800000UL)
9721 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Pos (22UL)
9722 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Msk (0x400000UL)
9723 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Pos (21UL)
9724 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Msk (0x200000UL)
9725 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_SCLR_Pos (20UL)
9726 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_SCLR_Msk (0x100000UL)
9727 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Pos (19UL)
9728 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Msk (0x80000UL)
9729 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Pos (18UL)
9730 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Msk (0x40000UL)
9731 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Pos (17UL)
9732 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Msk (0x20000UL)
9733 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_SCLR_Pos (16UL)
9734 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_SCLR_Msk (0x10000UL)
9735 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Pos (7UL)
9736 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Msk (0x80UL)
9737 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Pos (6UL)
9738 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Msk (0x40UL)
9739 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Pos (5UL)
9740 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Msk (0x20UL)
9741 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_ICLR_Pos (4UL)
9742 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_ICLR_Msk (0x10UL)
9743 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Pos (3UL)
9744 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Msk (0x8UL)
9745 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Pos (2UL)
9746 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Msk (0x4UL)
9747 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Pos (1UL)
9748 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Msk (0x2UL)
9749 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_ICLR_Pos (0UL)
9750 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_ICLR_Msk (0x1UL)
9752 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Pos (7UL)
9753 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Msk (0x80UL)
9754 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Pos (6UL)
9755 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Msk (0x40UL)
9756 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Pos (5UL)
9757 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Msk (0x20UL)
9758 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_OV_IE_Pos (4UL)
9759 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_OV_IE_Msk (0x10UL)
9760 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Pos (3UL)
9761 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Msk (0x8UL)
9762 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Pos (2UL)
9763 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Msk (0x4UL)
9764 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Pos (1UL)
9765 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Msk (0x2UL)
9766 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_UV_IE_Pos (0UL)
9767 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_UV_IE_Msk (0x1UL)
9769 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Pos (23UL)
9770 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Msk (0x800000UL)
9771 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Pos (22UL)
9772 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Msk (0x400000UL)
9773 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Pos (21UL)
9774 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Msk (0x200000UL)
9775 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_STS_Pos (20UL)
9776 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_STS_Msk (0x100000UL)
9777 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Pos (19UL)
9778 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Msk (0x80000UL)
9779 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Pos (18UL)
9780 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Msk (0x40000UL)
9781 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Pos (17UL)
9782 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Msk (0x20000UL)
9783 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_STS_Pos (16UL)
9784 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_STS_Msk (0x10000UL)
9785 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Pos (7UL)
9786 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Msk (0x80UL)
9787 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Pos (6UL)
9788 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Msk (0x40UL)
9789 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Pos (5UL)
9790 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Msk (0x20UL)
9791 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_IS_Pos (4UL)
9792 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_IS_Msk (0x10UL)
9793 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Pos (3UL)
9794 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Msk (0x8UL)
9795 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Pos (2UL)
9796 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Msk (0x4UL)
9797 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Pos (1UL)
9798 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Msk (0x2UL)
9799 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_IS_Pos (0UL)
9800 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_IS_Msk (0x1UL)
9802 #define SCUPM_WDT1_TRIG_SOWCONF_Pos (6UL)
9803 #define SCUPM_WDT1_TRIG_SOWCONF_Msk (0xc0UL)
9804 #define SCUPM_WDT1_TRIG_WDP_SEL_Pos (0UL)
9805 #define SCUPM_WDT1_TRIG_WDP_SEL_Msk (0x3fUL)
9813 #define SSC1_BR_BR_VALUE_Pos (0UL)
9814 #define SSC1_BR_BR_VALUE_Msk (0xffffUL)
9816 #define SSC1_CON_BC_Pos (0UL)
9817 #define SSC1_CON_BC_Msk (0xfUL)
9818 #define SSC1_CON_TE_Pos (8UL)
9819 #define SSC1_CON_TE_Msk (0x100UL)
9820 #define SSC1_CON_RE_Pos (9UL)
9821 #define SSC1_CON_RE_Msk (0x200UL)
9822 #define SSC1_CON_PE_Pos (10UL)
9823 #define SSC1_CON_PE_Msk (0x400UL)
9824 #define SSC1_CON_BE_Pos (11UL)
9825 #define SSC1_CON_BE_Msk (0x800UL)
9826 #define SSC1_CON_BSY_Pos (12UL)
9827 #define SSC1_CON_BSY_Msk (0x1000UL)
9828 #define SSC1_CON_MS_Pos (14UL)
9829 #define SSC1_CON_MS_Msk (0x4000UL)
9830 #define SSC1_CON_EN_Pos (15UL)
9831 #define SSC1_CON_EN_Msk (0x8000UL)
9833 #define SSC1_ISRCLR_TECLR_Pos (8UL)
9834 #define SSC1_ISRCLR_TECLR_Msk (0x100UL)
9835 #define SSC1_ISRCLR_RECLR_Pos (9UL)
9836 #define SSC1_ISRCLR_RECLR_Msk (0x200UL)
9837 #define SSC1_ISRCLR_PECLR_Pos (10UL)
9838 #define SSC1_ISRCLR_PECLR_Msk (0x400UL)
9839 #define SSC1_ISRCLR_BECLR_Pos (11UL)
9840 #define SSC1_ISRCLR_BECLR_Msk (0x800UL)
9842 #define SSC1_PISEL_MIS_0_Pos (0UL)
9843 #define SSC1_PISEL_MIS_0_Msk (0x1UL)
9844 #define SSC1_PISEL_SIS_Pos (1UL)
9845 #define SSC1_PISEL_SIS_Msk (0x2UL)
9846 #define SSC1_PISEL_CIS_Pos (2UL)
9847 #define SSC1_PISEL_CIS_Msk (0x4UL)
9848 #define SSC1_PISEL_MIS_1_Pos (3UL)
9849 #define SSC1_PISEL_MIS_1_Msk (0x8UL)
9851 #define SSC1_RB_RB_VALUE_Pos (0UL)
9852 #define SSC1_RB_RB_VALUE_Msk (0xffffUL)
9854 #define SSC1_TB_TB_VALUE_Pos (0UL)
9855 #define SSC1_TB_TB_VALUE_Msk (0xffffUL)
9863 #define SSC2_BR_BR_VALUE_Pos (0UL)
9864 #define SSC2_BR_BR_VALUE_Msk (0xffffUL)
9866 #define SSC2_CON_BC_Pos (0UL)
9867 #define SSC2_CON_BC_Msk (0xfUL)
9868 #define SSC2_CON_TE_Pos (8UL)
9869 #define SSC2_CON_TE_Msk (0x100UL)
9870 #define SSC2_CON_RE_Pos (9UL)
9871 #define SSC2_CON_RE_Msk (0x200UL)
9872 #define SSC2_CON_PE_Pos (10UL)
9873 #define SSC2_CON_PE_Msk (0x400UL)
9874 #define SSC2_CON_BE_Pos (11UL)
9875 #define SSC2_CON_BE_Msk (0x800UL)
9876 #define SSC2_CON_BSY_Pos (12UL)
9877 #define SSC2_CON_BSY_Msk (0x1000UL)
9878 #define SSC2_CON_MS_Pos (14UL)
9879 #define SSC2_CON_MS_Msk (0x4000UL)
9880 #define SSC2_CON_EN_Pos (15UL)
9881 #define SSC2_CON_EN_Msk (0x8000UL)
9883 #define SSC2_ISRCLR_TECLR_Pos (8UL)
9884 #define SSC2_ISRCLR_TECLR_Msk (0x100UL)
9885 #define SSC2_ISRCLR_RECLR_Pos (9UL)
9886 #define SSC2_ISRCLR_RECLR_Msk (0x200UL)
9887 #define SSC2_ISRCLR_PECLR_Pos (10UL)
9888 #define SSC2_ISRCLR_PECLR_Msk (0x400UL)
9889 #define SSC2_ISRCLR_BECLR_Pos (11UL)
9890 #define SSC2_ISRCLR_BECLR_Msk (0x800UL)
9892 #define SSC2_PISEL_MIS_0_Pos (0UL)
9893 #define SSC2_PISEL_MIS_0_Msk (0x1UL)
9894 #define SSC2_PISEL_SIS_Pos (1UL)
9895 #define SSC2_PISEL_SIS_Msk (0x2UL)
9896 #define SSC2_PISEL_CIS_Pos (2UL)
9897 #define SSC2_PISEL_CIS_Msk (0x4UL)
9898 #define SSC2_PISEL_MIS_1_Pos (3UL)
9899 #define SSC2_PISEL_MIS_1_Msk (0x8UL)
9901 #define SSC2_RB_RB_VALUE_Pos (0UL)
9902 #define SSC2_RB_RB_VALUE_Msk (0xffffUL)
9904 #define SSC2_TB_TB_VALUE_Pos (0UL)
9905 #define SSC2_TB_TB_VALUE_Msk (0xffffUL)
9913 #define TIMER2_RC2H_RC2_Pos (0UL)
9914 #define TIMER2_RC2H_RC2_Msk (0xffUL)
9916 #define TIMER2_RC2L_RC2_Pos (0UL)
9917 #define TIMER2_RC2L_RC2_Msk (0xffUL)
9919 #define TIMER2_T2CON_CP_RL2_Pos (0UL)
9920 #define TIMER2_T2CON_CP_RL2_Msk (0x1UL)
9921 #define TIMER2_T2CON_C_T2_Pos (1UL)
9922 #define TIMER2_T2CON_C_T2_Msk (0x2UL)
9923 #define TIMER2_T2CON_TR2_Pos (2UL)
9924 #define TIMER2_T2CON_TR2_Msk (0x4UL)
9925 #define TIMER2_T2CON_EXEN2_Pos (3UL)
9926 #define TIMER2_T2CON_EXEN2_Msk (0x8UL)
9927 #define TIMER2_T2CON_EXF2_Pos (6UL)
9928 #define TIMER2_T2CON_EXF2_Msk (0x40UL)
9929 #define TIMER2_T2CON_TF2_Pos (7UL)
9930 #define TIMER2_T2CON_TF2_Msk (0x80UL)
9932 #define TIMER2_T2CON1_EXF2EN_Pos (0UL)
9933 #define TIMER2_T2CON1_EXF2EN_Msk (0x1UL)
9934 #define TIMER2_T2CON1_TF2EN_Pos (1UL)
9935 #define TIMER2_T2CON1_TF2EN_Msk (0x2UL)
9937 #define TIMER2_T2H_T2H_Pos (0UL)
9938 #define TIMER2_T2H_T2H_Msk (0xffUL)
9940 #define TIMER2_T2ICLR_EXF2CLR_Pos (6UL)
9941 #define TIMER2_T2ICLR_EXF2CLR_Msk (0x40UL)
9942 #define TIMER2_T2ICLR_TF2CLR_Pos (7UL)
9943 #define TIMER2_T2ICLR_TF2CLR_Msk (0x80UL)
9945 #define TIMER2_T2L_T2L_Pos (0UL)
9946 #define TIMER2_T2L_T2L_Msk (0xffUL)
9948 #define TIMER2_T2MOD_DCEN_Pos (0UL)
9949 #define TIMER2_T2MOD_DCEN_Msk (0x1UL)
9950 #define TIMER2_T2MOD_T2PRE_Pos (1UL)
9951 #define TIMER2_T2MOD_T2PRE_Msk (0xeUL)
9952 #define TIMER2_T2MOD_PREN_Pos (4UL)
9953 #define TIMER2_T2MOD_PREN_Msk (0x10UL)
9954 #define TIMER2_T2MOD_EDGESEL_Pos (5UL)
9955 #define TIMER2_T2MOD_EDGESEL_Msk (0x20UL)
9956 #define TIMER2_T2MOD_T2RHEN_Pos (6UL)
9957 #define TIMER2_T2MOD_T2RHEN_Msk (0x40UL)
9958 #define TIMER2_T2MOD_T2REGS_Pos (7UL)
9959 #define TIMER2_T2MOD_T2REGS_Msk (0x80UL)
9967 #define TIMER21_RC2H_RC2_Pos (0UL)
9968 #define TIMER21_RC2H_RC2_Msk (0xffUL)
9970 #define TIMER21_RC2L_RC2_Pos (0UL)
9971 #define TIMER21_RC2L_RC2_Msk (0xffUL)
9973 #define TIMER21_T2CON_CP_RL2_Pos (0UL)
9974 #define TIMER21_T2CON_CP_RL2_Msk (0x1UL)
9975 #define TIMER21_T2CON_C_T2_Pos (1UL)
9976 #define TIMER21_T2CON_C_T2_Msk (0x2UL)
9977 #define TIMER21_T2CON_TR2_Pos (2UL)
9978 #define TIMER21_T2CON_TR2_Msk (0x4UL)
9979 #define TIMER21_T2CON_EXEN2_Pos (3UL)
9980 #define TIMER21_T2CON_EXEN2_Msk (0x8UL)
9981 #define TIMER21_T2CON_EXF2_Pos (6UL)
9982 #define TIMER21_T2CON_EXF2_Msk (0x40UL)
9983 #define TIMER21_T2CON_TF2_Pos (7UL)
9984 #define TIMER21_T2CON_TF2_Msk (0x80UL)
9986 #define TIMER21_T2CON1_EXF2EN_Pos (0UL)
9987 #define TIMER21_T2CON1_EXF2EN_Msk (0x1UL)
9988 #define TIMER21_T2CON1_TF2EN_Pos (1UL)
9989 #define TIMER21_T2CON1_TF2EN_Msk (0x2UL)
9991 #define TIMER21_T2H_T2H_Pos (0UL)
9992 #define TIMER21_T2H_T2H_Msk (0xffUL)
9994 #define TIMER21_T2ICLR_EXF2CLR_Pos (6UL)
9995 #define TIMER21_T2ICLR_EXF2CLR_Msk (0x40UL)
9996 #define TIMER21_T2ICLR_TF2CLR_Pos (7UL)
9997 #define TIMER21_T2ICLR_TF2CLR_Msk (0x80UL)
9999 #define TIMER21_T2L_T2L_Pos (0UL)
10000 #define TIMER21_T2L_T2L_Msk (0xffUL)
10002 #define TIMER21_T2MOD_DCEN_Pos (0UL)
10003 #define TIMER21_T2MOD_DCEN_Msk (0x1UL)
10004 #define TIMER21_T2MOD_T2PRE_Pos (1UL)
10005 #define TIMER21_T2MOD_T2PRE_Msk (0xeUL)
10006 #define TIMER21_T2MOD_PREN_Pos (4UL)
10007 #define TIMER21_T2MOD_PREN_Msk (0x10UL)
10008 #define TIMER21_T2MOD_EDGESEL_Pos (5UL)
10009 #define TIMER21_T2MOD_EDGESEL_Msk (0x20UL)
10010 #define TIMER21_T2MOD_T2RHEN_Pos (6UL)
10011 #define TIMER21_T2MOD_T2RHEN_Msk (0x40UL)
10012 #define TIMER21_T2MOD_T2REGS_Pos (7UL)
10013 #define TIMER21_T2MOD_T2REGS_Msk (0x80UL)
10021 #define TIMER3_CMP_HI_Pos (8UL)
10022 #define TIMER3_CMP_HI_Msk (0xff00UL)
10023 #define TIMER3_CMP_LO_Pos (0UL)
10024 #define TIMER3_CMP_LO_Msk (0xffUL)
10026 #define TIMER3_CNT_HI_Pos (8UL)
10027 #define TIMER3_CNT_HI_Msk (0xff00UL)
10028 #define TIMER3_CNT_LO_Pos (0UL)
10029 #define TIMER3_CNT_LO_Msk (0xffUL)
10031 #define TIMER3_CTRL_T3H_OVF_IE_Pos (9UL)
10032 #define TIMER3_CTRL_T3H_OVF_IE_Msk (0x200UL)
10033 #define TIMER3_CTRL_T3L_OVF_IE_Pos (8UL)
10034 #define TIMER3_CTRL_T3L_OVF_IE_Msk (0x100UL)
10035 #define TIMER3_CTRL_T3L_OVF_STS_Pos (7UL)
10036 #define TIMER3_CTRL_T3L_OVF_STS_Msk (0x80UL)
10037 #define TIMER3_CTRL_TR3L_Pos (6UL)
10038 #define TIMER3_CTRL_TR3L_Msk (0x40UL)
10039 #define TIMER3_CTRL_T3H_OVF_STS_Pos (5UL)
10040 #define TIMER3_CTRL_T3H_OVF_STS_Msk (0x20UL)
10041 #define TIMER3_CTRL_TR3H_Pos (4UL)
10042 #define TIMER3_CTRL_TR3H_Msk (0x10UL)
10043 #define TIMER3_CTRL_CNT_RDY_Pos (3UL)
10044 #define TIMER3_CTRL_CNT_RDY_Msk (0x8UL)
10045 #define TIMER3_CTRL_T3_RD_REQ_CONF_Pos (2UL)
10046 #define TIMER3_CTRL_T3_RD_REQ_CONF_Msk (0x4UL)
10047 #define TIMER3_CTRL_T3_RD_REQ_Pos (1UL)
10048 #define TIMER3_CTRL_T3_RD_REQ_Msk (0x2UL)
10049 #define TIMER3_CTRL_T3_PD_N_Pos (0UL)
10050 #define TIMER3_CTRL_T3_PD_N_Msk (0x1UL)
10052 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Pos (7UL)
10053 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Msk (0x80UL)
10054 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Pos (5UL)
10055 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Msk (0x20UL)
10057 #define TIMER3_MODE_CONF_T3_SUBM_Pos (6UL)
10058 #define TIMER3_MODE_CONF_T3_SUBM_Msk (0xc0UL)
10059 #define TIMER3_MODE_CONF_T3M_Pos (0UL)
10060 #define TIMER3_MODE_CONF_T3M_Msk (0x3UL)
10062 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Pos (6UL)
10063 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Msk (0x40UL)
10064 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Pos (4UL)
10065 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Msk (0x30UL)
10066 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Pos (0UL)
10067 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Msk (0x7UL)
10075 #define UART1_SBUF_VAL_Pos (0UL)
10076 #define UART1_SBUF_VAL_Msk (0xffUL)
10078 #define UART1_SCON_RI_Pos (0UL)
10079 #define UART1_SCON_RI_Msk (0x1UL)
10080 #define UART1_SCON_TI_Pos (1UL)
10081 #define UART1_SCON_TI_Msk (0x2UL)
10082 #define UART1_SCON_RB8_Pos (2UL)
10083 #define UART1_SCON_RB8_Msk (0x4UL)
10084 #define UART1_SCON_TB8_Pos (3UL)
10085 #define UART1_SCON_TB8_Msk (0x8UL)
10086 #define UART1_SCON_REN_Pos (4UL)
10087 #define UART1_SCON_REN_Msk (0x10UL)
10088 #define UART1_SCON_SM2_Pos (5UL)
10089 #define UART1_SCON_SM2_Msk (0x20UL)
10090 #define UART1_SCON_SM1_Pos (6UL)
10091 #define UART1_SCON_SM1_Msk (0x40UL)
10092 #define UART1_SCON_SM0_Pos (7UL)
10093 #define UART1_SCON_SM0_Msk (0x80UL)
10095 #define UART1_SCONCLR_RICLR_Pos (0UL)
10096 #define UART1_SCONCLR_RICLR_Msk (0x1UL)
10097 #define UART1_SCONCLR_TICLR_Pos (1UL)
10098 #define UART1_SCONCLR_TICLR_Msk (0x2UL)
10106 #define UART2_SBUF_VAL_Pos (0UL)
10107 #define UART2_SBUF_VAL_Msk (0xffUL)
10109 #define UART2_SCON_RI_Pos (0UL)
10110 #define UART2_SCON_RI_Msk (0x1UL)
10111 #define UART2_SCON_TI_Pos (1UL)
10112 #define UART2_SCON_TI_Msk (0x2UL)
10113 #define UART2_SCON_RB8_Pos (2UL)
10114 #define UART2_SCON_RB8_Msk (0x4UL)
10115 #define UART2_SCON_TB8_Pos (3UL)
10116 #define UART2_SCON_TB8_Msk (0x8UL)
10117 #define UART2_SCON_REN_Pos (4UL)
10118 #define UART2_SCON_REN_Msk (0x10UL)
10119 #define UART2_SCON_SM2_Pos (5UL)
10120 #define UART2_SCON_SM2_Msk (0x20UL)
10121 #define UART2_SCON_SM1_Pos (6UL)
10122 #define UART2_SCON_SM1_Msk (0x40UL)
10123 #define UART2_SCON_SM0_Pos (7UL)
10124 #define UART2_SCON_SM0_Msk (0x80UL)
10126 #define UART2_SCONCLR_RICLR_Pos (0UL)
10127 #define UART2_SCONCLR_RICLR_Msk (0x1UL)
10128 #define UART2_SCONCLR_TICLR_Pos (1UL)
10129 #define UART2_SCONCLR_TICLR_Msk (0x2UL)
IRQn_Type
Definition: tle987x.h:79
@ PendSV_IRQn
Definition: tle987x.h:91
@ EXINT0_MON_Int
Definition: tle987x.h:106
@ SSC2_Int
Definition: tle987x.h:103
@ BDRV_CP_Int
Definition: tle987x.h:108
@ CCU6_SR2_Int
Definition: tle987x.h:100
@ GPT2_Int
Definition: tle987x.h:95
@ MemoryManagement_IRQn
Definition: tle987x.h:84
@ DMA_Int
Definition: tle987x.h:109
@ SVCall_IRQn
Definition: tle987x.h:89
@ Reset_IRQn
Definition: tle987x.h:81
@ SSC1_Int
Definition: tle987x.h:102
@ CCU6_SR0_Int
Definition: tle987x.h:98
@ UsageFault_IRQn
Definition: tle987x.h:88
@ SysTick_IRQn
Definition: tle987x.h:92
@ UART2_Tmr21_EINT2_Int
Definition: tle987x.h:105
@ BusFault_IRQn
Definition: tle987x.h:86
@ DebugMonitor_IRQn
Definition: tle987x.h:90
@ UART1_LIN_Tmr2_Int
Definition: tle987x.h:104
@ HardFault_IRQn
Definition: tle987x.h:83
@ CCU6_SR1_Int
Definition: tle987x.h:99
@ EXINT1_Int
Definition: tle987x.h:107
@ NonMaskableInt_IRQn
Definition: tle987x.h:82
@ ADC2_Tmr3_Int
Definition: tle987x.h:96
@ CCU6_SR3_Int
Definition: tle987x.h:101
@ GPT1_Int
Definition: tle987x.h:94
@ ADC1_VREF5_Int
Definition: tle987x.h:97
#define DMA
Definition: tle987x.h:6064
#define SCUPM
Definition: tle987x.h:6072
#define ADC34
Definition: tle987x.h:6059
#define TIMER21
Definition: tle987x.h:6076
#define MF
Definition: tle987x.h:6067
#define PORT
Definition: tle987x.h:6070
#define TIMER3
Definition: tle987x.h:6077
#define GPT12E
Definition: tle987x.h:6065
#define SSC2
Definition: tle987x.h:6074
#define UART2
Definition: tle987x.h:6079
#define UART1
Definition: tle987x.h:6078
#define BDRV
Definition: tle987x.h:6060
#define ADC1
Definition: tle987x.h:6057
#define MON
Definition: tle987x.h:6068
#define CCU6
Definition: tle987x.h:6061
#define CSA
Definition: tle987x.h:6062
#define ADC2
Definition: tle987x.h:6058
#define SSC1
Definition: tle987x.h:6073
#define TIMER2
Definition: tle987x.h:6075
#define PMU
Definition: tle987x.h:6069
#define CPU
Definition: tle987x.h:6063
#define SCU
Definition: tle987x.h:6071
#define LIN
Definition: tle987x.h:6066
#define __OM
Definition: tle987x.h:135
#define __IM
Definition: tle987x.h:132
#define __IOM
Definition: tle987x.h:138
ADC1 Module (ADC1)
Definition: tle987x.h:167
__IOM uint32_t CH0_IE
Definition: tle987x.h:485
__IM uint32_t OF7
Definition: tle987x.h:343
__OM uint32_t CH7_ICLR
Definition: tle987x.h:511
__IOM uint32_t IN_MUX_SEL
Definition: tle987x.h:179
__IM uint32_t VF8
Definition: tle987x.h:311
__IM uint32_t OUT_CH_EIM
Definition: tle987x.h:308
__OM uint32_t CH6_ICLR
Definition: tle987x.h:510
__IM uint32_t CH1_STS
Definition: tle987x.h:467
__IOM uint32_t SOC
Definition: tle987x.h:177
__IOM uint32_t SQ5
Definition: tle987x.h:250
__IM uint32_t CHNR
Definition: tle987x.h:454
__IM uint32_t VF6
Definition: tle987x.h:356
__IM uint32_t OUT_CH2
Definition: tle987x.h:409
__IOM uint32_t WFR0
Definition: tle987x.h:439
__IOM uint32_t WFR6
Definition: tle987x.h:355
__IOM uint32_t ch2
Definition: tle987x.h:266
__IOM uint32_t CH3_IE
Definition: tle987x.h:488
__IOM uint32_t ch0
Definition: tle987x.h:264
__IOM uint32_t ANON
Definition: tle987x.h:193
__IOM uint32_t ch3
Definition: tle987x.h:267
__IM uint32_t VF4
Definition: tle987x.h:384
__IOM uint32_t WFR5
Definition: tle987x.h:369
__IOM uint32_t SQ6
Definition: tle987x.h:251
__IOM uint32_t SQ2
Definition: tle987x.h:237
__IM uint32_t OF0
Definition: tle987x.h:441
__IM uint32_t OF6
Definition: tle987x.h:357
__IM uint32_t OF8
Definition: tle987x.h:312
__IOM uint32_t DIVA
Definition: tle987x.h:189
__OM uint32_t EIM_ICLR
Definition: tle987x.h:512
__OM uint32_t ESM_ICLR
Definition: tle987x.h:513
__IOM uint32_t ch7
Definition: tle987x.h:271
__IOM uint32_t WFR2
Definition: tle987x.h:411
__IOM uint32_t SQ1
Definition: tle987x.h:236
__IM uint32_t VF2
Definition: tle987x.h:412
__IM uint32_t BUSY
Definition: tle987x.h:451
__IM uint32_t
Definition: tle987x.h:176
__IOM uint32_t EIM_IE
Definition: tle987x.h:493
__IOM uint32_t ch4
Definition: tle987x.h:268
__IM uint32_t CHx
Definition: tle987x.h:329
__OM uint32_t CH1_ICLR
Definition: tle987x.h:505
__IM uint32_t CH7_STS
Definition: tle987x.h:473
__IM uint32_t VF0
Definition: tle987x.h:440
__IOM uint32_t REP
Definition: tle987x.h:206
__IM uint32_t OUT_CH4
Definition: tle987x.h:381
__OM uint32_t CH3_ICLR
Definition: tle987x.h:507
__OM uint32_t CH4_ICLR
Definition: tle987x.h:508
__IM uint32_t OF5
Definition: tle987x.h:371
__IM uint32_t OUT_CH6
Definition: tle987x.h:353
__IM uint32_t EIM_STS
Definition: tle987x.h:474
__IM uint32_t EOC
Definition: tle987x.h:178
__IOM uint32_t ESM_0
Definition: tle987x.h:220
__IM uint32_t SQx
Definition: tle987x.h:327
__IM uint32_t ESM_ACTIVE
Definition: tle987x.h:326
__IM uint32_t CH0_STS
Definition: tle987x.h:466
__IM uint32_t CH2_STS
Definition: tle987x.h:468
__IM uint32_t OF3
Definition: tle987x.h:399
__IOM uint32_t ch6
Definition: tle987x.h:270
__IM uint32_t OUT_CH5
Definition: tle987x.h:367
__IM uint32_t ANON_ST
Definition: tle987x.h:456
__IOM uint32_t SQ7
Definition: tle987x.h:252
__IM uint32_t VF1
Definition: tle987x.h:426
__IM uint32_t ESM_STS
Definition: tle987x.h:475
__IM uint32_t VF5
Definition: tle987x.h:370
__IOM uint32_t WFR8
Definition: tle987x.h:310
__IM uint32_t CH5_STS
Definition: tle987x.h:471
__IM uint32_t CH4_STS
Definition: tle987x.h:470
__IOM uint32_t ESM_IE
Definition: tle987x.h:494
__IOM uint32_t ch5
Definition: tle987x.h:269
__IOM uint32_t CH4_IE
Definition: tle987x.h:489
__IM uint32_t OF4
Definition: tle987x.h:385
__IOM uint32_t reg
Definition: tle987x.h:171
__IM uint32_t OUT_CH7
Definition: tle987x.h:339
__IM uint32_t VF7
Definition: tle987x.h:342
__IOM uint32_t PD_N
Definition: tle987x.h:175
__IM uint32_t OUT_CH1
Definition: tle987x.h:423
__OM uint32_t CH2_ICLR
Definition: tle987x.h:506
__IM uint32_t SAMPLE
Definition: tle987x.h:452
__IOM uint32_t WFR4
Definition: tle987x.h:383
__IM uint32_t OUT_CH3
Definition: tle987x.h:395
__IOM uint32_t CH6_IE
Definition: tle987x.h:491
__IOM uint32_t SQ_RUN
Definition: tle987x.h:324
__IOM uint32_t SQ8
Definition: tle987x.h:253
__IOM uint32_t CHx
Definition: tle987x.h:204
__IOM uint32_t WFR3
Definition: tle987x.h:397
__IOM uint32_t TRIG_SEL
Definition: tle987x.h:208
__IOM uint32_t SQ3
Definition: tle987x.h:238
__IOM uint32_t ch1
Definition: tle987x.h:265
__IM uint32_t RESERVED1
Definition: tle987x.h:256
__IM uint32_t OF2
Definition: tle987x.h:413
__IM uint32_t CH6_STS
Definition: tle987x.h:472
__IOM uint32_t WFR1
Definition: tle987x.h:425
__IOM uint32_t CH1_IE
Definition: tle987x.h:486
__IOM uint32_t CH2_IE
Definition: tle987x.h:487
__IOM uint32_t SQ4
Definition: tle987x.h:239
__IM uint32_t OUT_CH0
Definition: tle987x.h:437
__OM uint32_t CH5_ICLR
Definition: tle987x.h:509
__IOM uint32_t CH7_IE
Definition: tle987x.h:492
__OM uint32_t CH0_ICLR
Definition: tle987x.h:504
__IM uint32_t EIM_ACTIVE
Definition: tle987x.h:325
__IM uint32_t CH3_STS
Definition: tle987x.h:469
__IOM uint32_t CH5_IE
Definition: tle987x.h:490
__IOM uint32_t WFR7
Definition: tle987x.h:341
__IM uint32_t VF3
Definition: tle987x.h:398
__IM uint32_t OF1
Definition: tle987x.h:427
ADC2 Module (ADC2)
Definition: tle987x.h:530
__IOM uint32_t HYST_UP_CH2
Definition: tle987x.h:1077
__IOM uint32_t HYST_UP_CH3
Definition: tle987x.h:1080
__IOM uint32_t OFFS_CH3
Definition: tle987x.h:733
__IM uint32_t CNT_LO_CH6
Definition: tle987x.h:1050
__IM uint32_t SQ_FB
Definition: tle987x.h:549
__IOM uint32_t OFFS_CH5
Definition: tle987x.h:746
__IOM uint32_t GAIN_CH2
Definition: tle987x.h:732
__IOM uint32_t FILT_OUT_SEL_9_6
Definition: tle987x.h:632
__IOM uint32_t Ch0
Definition: tle987x.h:1124
__IOM uint32_t HYST_UP_CH1
Definition: tle987x.h:1074
__IOM uint32_t CNT_UP_CH5
Definition: tle987x.h:1093
__IM uint32_t GAIN_CH8
Definition: tle987x.h:771
__IOM uint32_t CH6
Definition: tle987x.h:966
__IM uint32_t GAIN_CH9
Definition: tle987x.h:773
__IOM uint32_t CH1
Definition: tle987x.h:784
__IM uint32_t CNT_LO_CH9
Definition: tle987x.h:1059
__IM uint32_t HYST_LO_CH6
Definition: tle987x.h:1051
__IM uint32_t OFFS_CH9
Definition: tle987x.h:772
__IOM uint32_t SQ5
Definition: tle987x.h:659
__IOM uint32_t CH3
Definition: tle987x.h:786
__IM uint32_t CNT_LO_CH7
Definition: tle987x.h:1053
__IM uint32_t SQ_STOP
Definition: tle987x.h:551
__IM uint32_t OUT_CH2
Definition: tle987x.h:831
__IM uint32_t GAIN_CH7
Definition: tle987x.h:760
__IOM uint32_t CNT_LO_CH1
Definition: tle987x.h:1019
__IM uint32_t CNT_UP_CH7
Definition: tle987x.h:1107
__IOM uint32_t SEL
Definition: tle987x.h:572
__IM uint32_t CH8
Definition: tle987x.h:800
__IM uint32_t HYST_LO_CH9
Definition: tle987x.h:1060
__IOM uint32_t CH9
Definition: tle987x.h:969
__IOM uint32_t SQ6
Definition: tle987x.h:661
__IM uint32_t HYST_UP_CH7
Definition: tle987x.h:1108
__IOM uint32_t GAIN_CH1
Definition: tle987x.h:721
__IM uint32_t STS
Definition: tle987x.h:592
__IOM uint32_t SQ2
Definition: tle987x.h:644
__IOM uint32_t CNT_UP_CH4
Definition: tle987x.h:1090
__IOM uint32_t FILT_OUT_SEL_5_0
Definition: tle987x.h:630
__IM uint32_t CH7
Definition: tle987x.h:799
__IOM uint32_t Ch1_EN
Definition: tle987x.h:912
__IM uint32_t CNT_LO_CH8
Definition: tle987x.h:1056
__IOM uint32_t CNT_UP_CH1
Definition: tle987x.h:1073
__IOM uint32_t HYST_LO_CH2
Definition: tle987x.h:1023
__IM uint32_t HYST_UP_CH6
Definition: tle987x.h:1105
__IOM uint32_t SQ1
Definition: tle987x.h:642
__IM uint32_t
Definition: tle987x.h:538
__IOM uint32_t GAIN_CH5
Definition: tle987x.h:747
__IM uint32_t OUT_CH9
Definition: tle987x.h:901
__IOM uint32_t Ch4_EN
Definition: tle987x.h:915
__IOM uint32_t CNT_UP_CH3
Definition: tle987x.h:1079
__IOM uint32_t OFFS_CH2
Definition: tle987x.h:731
__IOM uint32_t GAIN_CH4
Definition: tle987x.h:745
__IM uint32_t HYST_UP_CH9
Definition: tle987x.h:1114
__IOM uint32_t SEL_TS_COUNT
Definition: tle987x.h:620
__IM uint32_t CHx
Definition: tle987x.h:556
__IM uint32_t SQ5_int
Definition: tle987x.h:693
__IOM uint32_t REP
Definition: tle987x.h:569
__IM uint32_t OUT_CH4
Definition: tle987x.h:851
__IOM uint32_t CH8
Definition: tle987x.h:968
__IOM uint32_t CH5
Definition: tle987x.h:788
__IM uint32_t OFFS_CH6
Definition: tle987x.h:757
__IOM uint32_t HYST_LO_CH5
Definition: tle987x.h:1040
__IOM uint32_t OFFS_CH1
Definition: tle987x.h:720
__IM uint32_t CH6
Definition: tle987x.h:798
__IM uint32_t READY
Definition: tle987x.h:1141
__IM uint32_t OUT_CH6
Definition: tle987x.h:871
__IOM uint32_t HYST_LO_CH1
Definition: tle987x.h:1020
__IM uint32_t SQ1_int
Definition: tle987x.h:689
__IOM uint32_t Ch4
Definition: tle987x.h:1128
__IOM uint32_t CNT_LO_CH2
Definition: tle987x.h:1022
__IOM uint32_t ESM_0
Definition: tle987x.h:584
__IM uint32_t SQx
Definition: tle987x.h:554
__IOM uint32_t CNT_UP_CH0
Definition: tle987x.h:1070
__IM uint32_t SQ6_int
Definition: tle987x.h:694
__IOM uint32_t Ch3
Definition: tle987x.h:1127
__IOM uint32_t Ch1
Definition: tle987x.h:1125
__IOM uint32_t Ch2_EN
Definition: tle987x.h:913
__IM uint32_t SQ3_int
Definition: tle987x.h:691
__IOM uint32_t SQ9
Definition: tle987x.h:676
__IOM uint32_t GAIN_CH0
Definition: tle987x.h:719
__IM uint32_t ESM_ACTIVE
Definition: tle987x.h:553
__IOM uint32_t TSENSE_SD_SEL
Definition: tle987x.h:615
__IOM uint32_t Ch2
Definition: tle987x.h:1126
__IOM uint32_t SAMPLE_TIME_int
Definition: tle987x.h:618
__IOM uint32_t CNT_LO_CH4
Definition: tle987x.h:1036
__IOM uint32_t ESM_1
Definition: tle987x.h:586
__IM uint32_t CNT_UP_CH9
Definition: tle987x.h:1113
__IM uint32_t CH9
Definition: tle987x.h:801
__IOM uint32_t Ch5
Definition: tle987x.h:1129
__IM uint32_t OUT_CH5
Definition: tle987x.h:861
__IOM uint32_t Ch0_EN
Definition: tle987x.h:911
__IOM uint32_t SQ7
Definition: tle987x.h:663
__IOM uint32_t CALIB_EN
Definition: tle987x.h:603
__IOM uint32_t HYST_LO_CH4
Definition: tle987x.h:1037
__IOM uint32_t SQ10
Definition: tle987x.h:678
__IM uint32_t MCM_RDY
Definition: tle987x.h:617
__IM uint32_t RESERVED
Definition: tle987x.h:595
__IM uint32_t SQ4_int
Definition: tle987x.h:692
__IOM uint32_t Ch5_EN
Definition: tle987x.h:916
__IOM uint32_t CH2
Definition: tle987x.h:785
__IM uint32_t SQ9_int
Definition: tle987x.h:707
__IM uint32_t GAIN_CH6
Definition: tle987x.h:758
__IM uint32_t SQ10_int
Definition: tle987x.h:708
__IOM uint32_t CH4
Definition: tle987x.h:787
__IM uint32_t OUT_CH8
Definition: tle987x.h:891
__IOM uint32_t reg
Definition: tle987x.h:534
__IOM uint32_t CNT_UP_CH2
Definition: tle987x.h:1076
__IM uint32_t OUT_CH7
Definition: tle987x.h:881
__IOM uint32_t EN
Definition: tle987x.h:570
__IM uint32_t OFFS_CH7
Definition: tle987x.h:759
__IOM uint32_t CNT_LO_CH5
Definition: tle987x.h:1039
__IOM uint32_t TS_SD_SEL_CONF
Definition: tle987x.h:614
__IOM uint32_t CNT_LO_CH0
Definition: tle987x.h:1016
__IM uint32_t CNT_UP_CH8
Definition: tle987x.h:1110
__IM uint32_t SQ8_int
Definition: tle987x.h:696
__IOM uint32_t CH0
Definition: tle987x.h:783
__IOM uint32_t HYST_LO_CH0
Definition: tle987x.h:1017
__IOM uint32_t GAIN_CH3
Definition: tle987x.h:734
__IM uint32_t SQ7_int
Definition: tle987x.h:695
__IM uint32_t OUT_CH1
Definition: tle987x.h:821
__IM uint32_t OFFS_CH8
Definition: tle987x.h:770
__IM uint32_t OUT_CH3
Definition: tle987x.h:841
__IM uint32_t HYST_LO_CH8
Definition: tle987x.h:1057
__IM uint32_t HYST_UP_CH8
Definition: tle987x.h:1111
__IOM uint32_t HYST_UP_CH4
Definition: tle987x.h:1091
__IOM uint32_t SQ8
Definition: tle987x.h:665
__IOM uint32_t CHx
Definition: tle987x.h:567
__IM uint32_t HYST_LO_CH7
Definition: tle987x.h:1054
__IOM uint32_t SQ3
Definition: tle987x.h:646
__IOM uint32_t MCM_PD_N
Definition: tle987x.h:613
__IOM uint32_t HYST_LO_CH3
Definition: tle987x.h:1026
__IOM uint32_t CNT_LO_CH3
Definition: tle987x.h:1025
__IM uint32_t CNT_UP_CH6
Definition: tle987x.h:1104
__IOM uint32_t OFFS_CH0
Definition: tle987x.h:718
__IOM uint32_t SQ4
Definition: tle987x.h:648
__IOM uint32_t VS_RANGE
Definition: tle987x.h:539
__IOM uint32_t OFFS_CH4
Definition: tle987x.h:744
__IM uint32_t SQ2_int
Definition: tle987x.h:690
__IM uint32_t OUT_CH0
Definition: tle987x.h:811
__IOM uint32_t HYST_UP_CH5
Definition: tle987x.h:1094
__IM uint32_t EIM_ACTIVE
Definition: tle987x.h:552
__IOM uint32_t Ch3_EN
Definition: tle987x.h:914
__IOM uint32_t HYST_UP_CH0
Definition: tle987x.h:1071
ADC34 (ADC34)
Definition: tle987x.h:1158
__IOM uint32_t ADC4_SOC
Definition: tle987x.h:1178
__IOM uint32_t ADC4_OSR
Definition: tle987x.h:1185
__IM uint32_t ADC4_EoC_STS
Definition: tle987x.h:1181
__IM uint32_t ADC4_RESU
Definition: tle987x.h:1196
__IOM uint32_t ADC34_DITHVAL
Definition: tle987x.h:1184
__IOM uint32_t ADC3_SOC
Definition: tle987x.h:1168
__IM uint32_t ADC34_DREQ_SEL
Definition: tle987x.h:1172
__IM uint32_t
Definition: tle987x.h:1170
__IOM uint32_t ADC34_DITHEN
Definition: tle987x.h:1183
__IOM uint32_t ADC3_EN
Definition: tle987x.h:1166
__IM uint32_t ADC3_EoC_STS
Definition: tle987x.h:1171
__IOM uint32_t ADC34_REF_SEL
Definition: tle987x.h:1174
__IOM uint32_t ADC3_OSR
Definition: tle987x.h:1175
__IOM uint32_t ADC4_EN
Definition: tle987x.h:1176
__IOM uint32_t reg
Definition: tle987x.h:1162
__IOM uint32_t ADC4_OFS_MEAS_EN
Definition: tle987x.h:1177
__IOM uint32_t ADC3_OFS_MEAS_EN
Definition: tle987x.h:1167
__IOM uint32_t ADC34_EoC_CNT
Definition: tle987x.h:1182
__IM uint32_t ADC3_RESU
Definition: tle987x.h:1195
Bridge Driver (BDRV)
Definition: tle987x.h:1213
__IM uint32_t HS3_DS_STS
Definition: tle987x.h:1277
__IOM uint32_t LS1_PWM
Definition: tle987x.h:1222
__IOM uint32_t DRV_ON_I_3
Definition: tle987x.h:1338
__IOM uint32_t HS3_PWM
Definition: tle987x.h:1274
__IOM uint32_t DITH_LOWER
Definition: tle987x.h:1413
__IM uint32_t HS1_DS_STS
Definition: tle987x.h:1242
__IOM uint32_t HS2_DCS_EN
Definition: tle987x.h:1250
__IOM uint32_t LS2_PWM
Definition: tle987x.h:1230
__IOM uint32_t HS3DRV_FDISCHG_DIS
Definition: tle987x.h:1369
__IOM uint32_t ICHARGEDIV2_N
Definition: tle987x.h:1297
__IOM uint32_t LS2_OC_DIS
Definition: tle987x.h:1237
__IM uint32_t HS3_OC_STS
Definition: tle987x.h:1279
__IOM uint32_t LS3DRV_FDISCHG_DIS
Definition: tle987x.h:1361
__IOM uint32_t HS1_DCS_EN
Definition: tle987x.h:1241
__IOM uint32_t LS3_ON
Definition: tle987x.h:1267
__IM uint32_t LS1_OC_STS
Definition: tle987x.h:1227
__IOM uint32_t DITH_UPPER
Definition: tle987x.h:1415
__IM uint32_t VSD_LOTH_STS
Definition: tle987x.h:1398
__IOM uint32_t LS1_EN
Definition: tle987x.h:1221
__IOM uint32_t CPLOPWRM_EN
Definition: tle987x.h:1401
__IM uint32_t LS2_DS_STS
Definition: tle987x.h:1233
__IM uint32_t HS2_SUPERR_STS
Definition: tle987x.h:1253
__IOM uint32_t LS3DRV_OCSDN_DIS
Definition: tle987x.h:1364
__IOM uint32_t DRV_OFF_I_2
Definition: tle987x.h:1323
__IOM uint32_t HS3_OC_DIS
Definition: tle987x.h:1280
__IM uint32_t LS2_SUPERR_STS
Definition: tle987x.h:1235
__IOM uint32_t ICHARGE_TRIM
Definition: tle987x.h:1295
__IOM uint32_t HS3_ON
Definition: tle987x.h:1275
__IOM uint32_t HSDRV_DS_TFILT_SEL
Definition: tle987x.h:1365
__IOM uint32_t DRV_ON_t_3
Definition: tle987x.h:1337
__IOM uint32_t LS1DRV_OCSDN_DIS
Definition: tle987x.h:1362
__IM uint32_t HS3_SUPERR_STS
Definition: tle987x.h:1278
__IOM uint32_t LS2DRV_OCSDN_DIS
Definition: tle987x.h:1363
__IM uint32_t HS1_SUPERR_STS
Definition: tle987x.h:1244
__IM uint32_t LS1_DS_STS
Definition: tle987x.h:1225
__IOM uint32_t LS2_DCS_EN
Definition: tle987x.h:1232
__IOM uint32_t DRV_OFF_t_4
Definition: tle987x.h:1318
__IOM uint32_t VCP9V_SET
Definition: tle987x.h:1402
__IOM uint32_t HS3_EN
Definition: tle987x.h:1273
__IOM uint32_t DRV_ON_I_1
Definition: tle987x.h:1342
__IM uint32_t DLY_DIAG_TIM
Definition: tle987x.h:1281
__IOM uint32_t DRVx_VSDUP_DIS
Definition: tle987x.h:1399
__IOM uint32_t HS2DRV_FDISCHG_DIS
Definition: tle987x.h:1368
__IOM uint32_t HS1_PWM
Definition: tle987x.h:1239
__IOM uint32_t DRV_ON_I_4
Definition: tle987x.h:1336
__IOM uint32_t LS2DRV_FDISCHG_DIS
Definition: tle987x.h:1360
__IOM uint32_t LS3_PWM
Definition: tle987x.h:1266
__IOM uint32_t LS2_ON
Definition: tle987x.h:1231
__IOM uint32_t HS1_EN
Definition: tle987x.h:1238
__IOM uint32_t HS3DRV_OCSDN_DIS
Definition: tle987x.h:1372
__IOM uint32_t F_CP
Definition: tle987x.h:1416
__IOM uint32_t DRV_CCP_TIMSEL
Definition: tle987x.h:1306
__IM uint32_t HS1_OC_STS
Definition: tle987x.h:1245
__IM uint32_t
Definition: tle987x.h:1296
__IOM uint32_t DRV_OFF_t_2
Definition: tle987x.h:1322
__OM uint32_t DLY_DIAG_SCLR
Definition: tle987x.h:1282
__IOM uint32_t HS1_ON
Definition: tle987x.h:1240
__IOM uint32_t OFF_SEQ_EN
Definition: tle987x.h:1302
__IOM uint32_t LS_HS_BT_TFILT_SEL
Definition: tle987x.h:1352
__IOM uint32_t LS3_OC_DIS
Definition: tle987x.h:1272
__IOM uint32_t HS3_DCS_EN
Definition: tle987x.h:1276
__IOM uint32_t DRV_OFF_I_1
Definition: tle987x.h:1325
__IOM uint32_t DRV_ON_t_1
Definition: tle987x.h:1341
__IOM uint32_t DLY_DIAG_DIRSEL
Definition: tle987x.h:1285
__IOM uint32_t DRV_CCP_DIS
Definition: tle987x.h:1307
__IOM uint32_t HS2_PWM
Definition: tle987x.h:1248
__IOM uint32_t HS2_EN
Definition: tle987x.h:1247
__IOM uint32_t HS2_ON
Definition: tle987x.h:1249
__IOM uint32_t CPLOW_TFILT_SEL
Definition: tle987x.h:1373
__IM uint32_t VCP_LOTH1_STS
Definition: tle987x.h:1394
__IM uint32_t LS3_SUPERR_STS
Definition: tle987x.h:1270
__IOM uint32_t IDISCHARGE_TRIM
Definition: tle987x.h:1299
__IM uint32_t VCP_UPTH_STS
Definition: tle987x.h:1396
__IOM uint32_t LS3_EN
Definition: tle987x.h:1265
__IOM uint32_t HS1_OC_DIS
Definition: tle987x.h:1246
__IOM uint32_t CP_RDY_EN
Definition: tle987x.h:1386
__IOM uint32_t LS1_DCS_EN
Definition: tle987x.h:1224
__IOM uint32_t CPCLK_EN
Definition: tle987x.h:1417
__IOM uint32_t DRV_ON_t_2
Definition: tle987x.h:1339
__IM uint32_t DLY_DIAG_STS
Definition: tle987x.h:1283
__IOM uint32_t DRV_OFF_t_3
Definition: tle987x.h:1320
__IOM uint32_t DRV_CCPTIMMUL
Definition: tle987x.h:1355
__IOM uint32_t DRV_OFF_t_1
Definition: tle987x.h:1324
__IM uint32_t RESERVED
Definition: tle987x.h:1310
__IOM uint32_t LS1_OC_DIS
Definition: tle987x.h:1228
__IOM uint32_t LS1_ON
Definition: tle987x.h:1223
__IOM uint32_t DLY_DIAG_CHSEL
Definition: tle987x.h:1284
__IM uint32_t LS1_SUPERR_STS
Definition: tle987x.h:1226
__IOM uint32_t DRV_ON_t_4
Definition: tle987x.h:1335
__IM uint32_t HS2_DS_STS
Definition: tle987x.h:1251
__IOM uint32_t reg
Definition: tle987x.h:1217
__IOM uint32_t DRV_OFF_I_3
Definition: tle987x.h:1321
__IM uint32_t VSD_UPTH_STS
Definition: tle987x.h:1400
__IOM uint32_t HS1DRV_FDISCHG_DIS
Definition: tle987x.h:1367
__IM uint32_t VCP_LOTH2_STS
Definition: tle987x.h:1388
__IOM uint32_t VTHVCP9V_TRIM
Definition: tle987x.h:1403
__IOM uint32_t CP_EN
Definition: tle987x.h:1384
__IOM uint32_t DRVx_VSDLO_DIS
Definition: tle987x.h:1397
__IM uint32_t LS3_DS_STS
Definition: tle987x.h:1269
__IOM uint32_t DRVx_VCPUP_DIS
Definition: tle987x.h:1395
__IOM uint32_t LS3_DCS_EN
Definition: tle987x.h:1268
__IOM uint32_t LS2_EN
Definition: tle987x.h:1229
__IOM uint32_t LS1DRV_FDISCHG_DIS
Definition: tle987x.h:1359
__IOM uint32_t HS2DRV_OCSDN_DIS
Definition: tle987x.h:1371
__IOM uint32_t HS2_OC_DIS
Definition: tle987x.h:1255
__IM uint32_t RESERVED1
Definition: tle987x.h:1376
__IOM uint32_t IDISCHARGEDIV2_N
Definition: tle987x.h:1301
__IOM uint32_t DSMONVTH
Definition: tle987x.h:1303
__IOM uint32_t VCP_LOWTH2
Definition: tle987x.h:1390
__IOM uint32_t DRV_OFF_I_4
Definition: tle987x.h:1319
__IOM uint32_t HS1DRV_OCSDN_DIS
Definition: tle987x.h:1370
__IM uint32_t HS2_OC_STS
Definition: tle987x.h:1254
__IOM uint32_t ON_SEQ_EN
Definition: tle987x.h:1298
__IOM uint32_t DRVx_VCPLO_DIS
Definition: tle987x.h:1393
__IOM uint32_t DRV_ON_I_2
Definition: tle987x.h:1340
__IM uint32_t LS3_OC_STS
Definition: tle987x.h:1271
__IOM uint32_t LSDRV_DS_TFILT_SEL
Definition: tle987x.h:1358
__IM uint32_t LS2_OC_STS
Definition: tle987x.h:1236
Capture Compare Unit 6 (CCU6)
Definition: tle987x.h:1434
__IOM uint16_t T13MODEN
Definition: tle987x.h:1827
__IOM uint16_t INPCC62
Definition: tle987x.h:1736
__IOM uint16_t INPCHE
Definition: tle987x.h:1737
__IM uint16_t CC63ST
Definition: tle987x.h:1959
__IOM uint16_t ECT13O
Definition: tle987x.h:1829
__IOM uint16_t DTE2
Definition: tle987x.h:1619
__OM uint16_t MCC63R
Definition: tle987x.h:1538
__IOM uint16_t STRMCM
Definition: tle987x.h:1480
__OM uint16_t RT12PM
Definition: tle987x.h:1502
__IM uint16_t CHE
Definition: tle987x.h:1884
__OM uint16_t RCHE
Definition: tle987x.h:1507
__OM uint16_t MCC62S
Definition: tle987x.h:1525
__IOM uint16_t DBYP
Definition: tle987x.h:1691
__IOM uint16_t ENCC62R
Definition: tle987x.h:1710
__IM uint16_t T13R
Definition: tle987x.h:1642
__IOM uint16_t INPCC60
Definition: tle987x.h:1734
__IOM uint16_t ENT13PM
Definition: tle987x.h:1717
__IOM uint16_t ISCC61
Definition: tle987x.h:1899
__OM uint16_t RTRPF
Definition: tle987x.h:1505
__OM uint16_t T12RS
Definition: tle987x.h:1454
__IM uint16_t T12OM
Definition: tle987x.h:1878
__IM uint16_t IDLE
Definition: tle987x.h:1886
__IM uint16_t RESERVED26
Definition: tle987x.h:1890
__IM uint16_t DTR2
Definition: tle987x.h:1623
__IOM uint16_t T12PV
Definition: tle987x.h:1594
__OM uint16_t T13STD
Definition: tle987x.h:1467
__IM uint16_t RESERVED19
Definition: tle987x.h:1769
__IOM uint16_t ISPOS2
Definition: tle987x.h:1904
__IOM uint16_t T13TEC
Definition: tle987x.h:1809
__IM uint16_t RESERVED12
Definition: tle987x.h:1646
__IOM uint16_t T13RSEL
Definition: tle987x.h:1813
__OM uint16_t MCC60S
Definition: tle987x.h:1521
__IOM uint16_t T12MODEN
Definition: tle987x.h:1824
__IOM uint16_t INPT13
Definition: tle987x.h:1740
__OM uint16_t RCC62R
Definition: tle987x.h:1499
__IM uint16_t RESERVED13
Definition: tle987x.h:1657
__IM uint16_t CCV
Definition: tle987x.h:1442
__OM uint16_t SCHE
Definition: tle987x.h:1763
__IOM uint16_t ENIDLE
Definition: tle987x.h:1722
__IOM uint16_t ISPOS1
Definition: tle987x.h:1903
__IOM uint16_t PSL
Definition: tle987x.h:1777
__IOM uint16_t T12EXT
Definition: tle987x.h:1919
__IOM uint16_t T13CLK
Definition: tle987x.h:1640
__OM uint16_t ST12PM
Definition: tle987x.h:1758
__IOM uint16_t CC61PS
Definition: tle987x.h:1963
__OM uint16_t ST12OM
Definition: tle987x.h:1757
__OM uint16_t T12RES
Definition: tle987x.h:1455
__IM uint16_t RESERVED22
Definition: tle987x.h:1816
__OM uint16_t T12RR
Definition: tle987x.h:1453
__IOM uint16_t T12PRE
Definition: tle987x.h:1635
__IM uint16_t ICC60R
Definition: tle987x.h:1872
__IOM uint16_t HSYNC
Definition: tle987x.h:1690
__IOM uint16_t T13IM
Definition: tle987x.h:1968
__OM uint16_t SSTR
Definition: tle987x.h:1766
__OM uint16_t SCC61F
Definition: tle987x.h:1754
__IM uint16_t RESERVED8
Definition: tle987x.h:1586
__IM uint16_t STE13
Definition: tle987x.h:1643
__IOM uint16_t CTM
Definition: tle987x.h:1639
__IM uint16_t T12PM
Definition: tle987x.h:1879
__OM uint16_t MCC60R
Definition: tle987x.h:1531
__OM uint16_t SWHE
Definition: tle987x.h:1764
__IOM uint16_t DTE1
Definition: tle987x.h:1618
__OM uint16_t T13STR
Definition: tle987x.h:1466
__OM uint16_t MCC62R
Definition: tle987x.h:1535
__IOM uint16_t INPERR
Definition: tle987x.h:1738
__IM uint16_t RESERVED4
Definition: tle987x.h:1542
__OM uint16_t SCC62R
Definition: tle987x.h:1755
__OM uint16_t RCC60F
Definition: tle987x.h:1496
__IM uint16_t ICC60F
Definition: tle987x.h:1873
__IOM uint16_t DTM
Definition: tle987x.h:1616
__IM uint16_t STE12
Definition: tle987x.h:1637
__IOM uint16_t COUT60PS
Definition: tle987x.h:1962
__IOM uint16_t STE12D
Definition: tle987x.h:1795
__IOM uint16_t EXPHS
Definition: tle987x.h:1481
__IM uint16_t
Definition: tle987x.h:1457
__OM uint16_t RT12OM
Definition: tle987x.h:1501
__IOM uint16_t ISTRP
Definition: tle987x.h:1901
__OM uint16_t T13CNT
Definition: tle987x.h:1465
__IOM uint16_t ENCC60F
Definition: tle987x.h:1704
__IM uint16_t CCPOS2
Definition: tle987x.h:1958
__OM uint16_t RCC62F
Definition: tle987x.h:1500
__IOM uint16_t COUT63PS
Definition: tle987x.h:1967
__IOM uint16_t T12SSC
Definition: tle987x.h:1807
__OM uint16_t RCC60R
Definition: tle987x.h:1495
__IOM uint16_t SWSEL
Definition: tle987x.h:1790
__IM uint16_t TRPF
Definition: tle987x.h:1882
__IM uint16_t RESERVED10
Definition: tle987x.h:1608
__OM uint16_t SIDLE
Definition: tle987x.h:1765
__OM uint16_t STRPF
Definition: tle987x.h:1761
__OM uint16_t RWHE
Definition: tle987x.h:1508
__IOM uint16_t ENT12PM
Definition: tle987x.h:1715
__OM uint16_t MCC63S
Definition: tle987x.h:1528
__IOM uint16_t ENCC61F
Definition: tle987x.h:1708
__IM uint16_t RESERVED20
Definition: tle987x.h:1782
__IM uint16_t ICC62F
Definition: tle987x.h:1877
__IM uint16_t R
Definition: tle987x.h:1858
__OM uint16_t MCC61S
Definition: tle987x.h:1523
__IM uint16_t T12R
Definition: tle987x.h:1636
__IM uint16_t CCPOS0
Definition: tle987x.h:1956
__OM uint16_t ST13PM
Definition: tle987x.h:1760
__IOM uint16_t TRPM1
Definition: tle987x.h:1841
__OM uint16_t SWHC
Definition: tle987x.h:1762
__IM uint16_t RESERVED28
Definition: tle987x.h:1923
__IM uint16_t RESERVED14
Definition: tle987x.h:1668
__IOM uint16_t reg
Definition: tle987x.h:1438
__IOM uint16_t MSEL60
Definition: tle987x.h:1687
__IOM uint16_t COUT62PS
Definition: tle987x.h:1966
__IM uint16_t RESERVED25
Definition: tle987x.h:1864
__IOM uint16_t ISCNT13
Definition: tle987x.h:1918
__IOM uint16_t ENWHE
Definition: tle987x.h:1721
__IM uint16_t CCPOS1
Definition: tle987x.h:1957
__IM uint16_t RESERVED30
Definition: tle987x.h:1945
__OM uint16_t T13RS
Definition: tle987x.h:1462
__OM uint16_t RSTR
Definition: tle987x.h:1510
__IM uint16_t CDIR
Definition: tle987x.h:1638
__IOM uint16_t IST13HR
Definition: tle987x.h:1916
__OM uint16_t SCC61R
Definition: tle987x.h:1753
__IM uint16_t CC62ST
Definition: tle987x.h:1955
__OM uint16_t T12STR
Definition: tle987x.h:1459
__IM uint16_t RESERVED6
Definition: tle987x.h:1564
__IM uint16_t DTR1
Definition: tle987x.h:1622
__OM uint16_t T12CNT
Definition: tle987x.h:1458
__OM uint16_t SCC60F
Definition: tle987x.h:1752
__IOM uint16_t MCMPS
Definition: tle987x.h:1478
__IOM uint16_t T12CV
Definition: tle987x.h:1931
__IOM uint16_t STE13U
Definition: tle987x.h:1796
__IOM uint16_t ENCC60R
Definition: tle987x.h:1702
__OM uint16_t RCC61F
Definition: tle987x.h:1498
__IOM uint16_t ENCC61R
Definition: tle987x.h:1706
__IOM uint16_t CC60PS
Definition: tle987x.h:1961
__IM uint16_t DTR0
Definition: tle987x.h:1621
__IOM uint16_t T13EXT
Definition: tle987x.h:1920
__IOM uint16_t IST12HR
Definition: tle987x.h:1905
__IOM uint16_t T13SSC
Definition: tle987x.h:1808
__IOM uint16_t INPCC61
Definition: tle987x.h:1735
__OM uint16_t RCC61R
Definition: tle987x.h:1497
__IM uint16_t CC60ST
Definition: tle987x.h:1953
__IOM uint16_t MCMEN
Definition: tle987x.h:1826
__IOM uint16_t ENTRPF
Definition: tle987x.h:1718
__IM uint16_t RESERVED11
Definition: tle987x.h:1626
__IOM uint16_t TRPPEN
Definition: tle987x.h:1846
__IOM uint16_t CCS
Definition: tle987x.h:1550
__IOM uint16_t ENT13CM
Definition: tle987x.h:1716
__IM uint16_t MCMP
Definition: tle987x.h:1857
__IOM uint16_t T12CLK
Definition: tle987x.h:1634
__IM uint16_t RESERVED29
Definition: tle987x.h:1934
__IOM uint16_t TRPEN13
Definition: tle987x.h:1845
__IOM uint16_t CURHS
Definition: tle987x.h:1482
__OM uint16_t ST13CM
Definition: tle987x.h:1759
__IM uint16_t CC61ST
Definition: tle987x.h:1954
__IOM uint16_t T13TED
Definition: tle987x.h:1810
__IOM uint16_t CC62PS
Definition: tle987x.h:1965
__IOM uint16_t TRPEN
Definition: tle987x.h:1844
__OM uint16_t SCC62F
Definition: tle987x.h:1756
__IOM uint16_t T13PRE
Definition: tle987x.h:1641
__IOM uint16_t ISCNT12
Definition: tle987x.h:1917
__IOM uint16_t COUT61PS
Definition: tle987x.h:1964
__IM uint16_t STR
Definition: tle987x.h:1887
__IM uint16_t RESERVED23
Definition: tle987x.h:1832
__IM uint16_t RESERVED18
Definition: tle987x.h:1743
__IM uint16_t T13CM
Definition: tle987x.h:1880
__IOM uint16_t TRPM0
Definition: tle987x.h:1840
__IM uint16_t T13PM
Definition: tle987x.h:1881
__IM uint16_t CURH
Definition: tle987x.h:1861
__IM uint16_t RESERVED5
Definition: tle987x.h:1553
__IOM uint16_t DTE0
Definition: tle987x.h:1617
__IM uint16_t WHE
Definition: tle987x.h:1885
__IM uint16_t RESERVED17
Definition: tle987x.h:1726
__IOM uint16_t INPT12
Definition: tle987x.h:1739
__IOM uint16_t T13PV
Definition: tle987x.h:1605
__OM uint16_t T12STD
Definition: tle987x.h:1460
__OM uint16_t DTRES
Definition: tle987x.h:1456
__OM uint16_t MCC61R
Definition: tle987x.h:1533
__OM uint16_t T13RES
Definition: tle987x.h:1463
__OM uint16_t RIDLE
Definition: tle987x.h:1509
__IM uint16_t RESERVED9
Definition: tle987x.h:1597
__IOM uint16_t T13CV
Definition: tle987x.h:1942
__IOM uint16_t ENCC62F
Definition: tle987x.h:1712
__IOM uint16_t ENCHE
Definition: tle987x.h:1720
__IM uint16_t RESERVED1
Definition: tle987x.h:1470
__IOM uint16_t ISCC60
Definition: tle987x.h:1898
__IOM uint16_t TRPM2
Definition: tle987x.h:1842
__IOM uint16_t T12RSEL
Definition: tle987x.h:1812
__OM uint16_t SCC60R
Definition: tle987x.h:1751
__OM uint16_t RT13CM
Definition: tle987x.h:1503
__IOM uint16_t ENT12OM
Definition: tle987x.h:1714
__IOM uint16_t PSL63
Definition: tle987x.h:1779
__IM uint16_t RESERVED7
Definition: tle987x.h:1575
__IM uint16_t RESERVED15
Definition: tle987x.h:1679
__IM uint16_t RESERVED3
Definition: tle987x.h:1513
__IM uint16_t RESERVED21
Definition: tle987x.h:1799
__IOM uint16_t STE12U
Definition: tle987x.h:1794
__IM uint16_t EXPH
Definition: tle987x.h:1860
__IM uint16_t RESERVED
Definition: tle987x.h:1445
__IOM uint16_t STRHP
Definition: tle987x.h:1484
__IM uint16_t ICC62R
Definition: tle987x.h:1876
__IOM uint16_t ISPOS0
Definition: tle987x.h:1902
__IOM uint16_t ISCC62
Definition: tle987x.h:1900
__IM uint16_t ICC61R
Definition: tle987x.h:1874
__IM uint16_t RESERVED2
Definition: tle987x.h:1487
__IOM uint16_t SWSYN
Definition: tle987x.h:1792
__OM uint16_t RT13PM
Definition: tle987x.h:1504
__IM uint16_t RESERVED24
Definition: tle987x.h:1849
__IM uint16_t TRPS
Definition: tle987x.h:1883
__IM uint16_t RESERVED16
Definition: tle987x.h:1694
__OM uint16_t T13RR
Definition: tle987x.h:1461
__IM uint16_t ICC61F
Definition: tle987x.h:1875
__IOM uint16_t MSEL61
Definition: tle987x.h:1688
__IOM uint16_t ENSTR
Definition: tle987x.h:1723
__IOM uint16_t MSEL62
Definition: tle987x.h:1689
CPU Core (CPU)
Definition: tle987x.h:1985
__IM uint32_t Int_DMA
Definition: tle987x.h:2172
__IOM uint32_t CP10
Definition: tle987x.h:2486
__IM uint32_t Int_GPT2
Definition: tle987x.h:2158
__IOM uint32_t PRI_CCU6SR1
Definition: tle987x.h:2197
__IOM uint32_t SVCALLPENDED
Definition: tle987x.h:2386
__IOM uint32_t PRI_6
Definition: tle987x.h:2336
__IOM uint32_t Int_CCU6SR2
Definition: tle987x.h:2059
__IOM uint32_t RELOAD
Definition: tle987x.h:2019
__IOM uint32_t CLKSOURCE
Definition: tle987x.h:2007
__IM uint32_t Int_GPT1
Definition: tle987x.h:2157
__IOM uint32_t DWTTRAP
Definition: tle987x.h:2445
__IOM uint32_t PRI_GPT1
Definition: tle987x.h:2183
__IOM uint32_t CP0
Definition: tle987x.h:2477
__IOM uint32_t PRI_BDRV
Definition: tle987x.h:2224
__IOM uint32_t DIVBYZERO
Definition: tle987x.h:2419
__IOM uint32_t USGFAULTACT
Definition: tle987x.h:2376
__IOM uint32_t DEBUGEVT
Definition: tle987x.h:2433
__IOM uint32_t PRI_ADC2
Definition: tle987x.h:2185
__IOM uint32_t PRI_8
Definition: tle987x.h:2347
__IOM uint32_t DIV_0_TRP
Definition: tle987x.h:2319
__IOM uint32_t CP3
Definition: tle987x.h:2480
__IM uint32_t Int_CCU6SR0
Definition: tle987x.h:2161
__IOM uint32_t Int_SSC1
Definition: tle987x.h:2061
__IOM uint32_t PRI_UART2
Definition: tle987x.h:2212
__IM uint32_t Int_ADC2
Definition: tle987x.h:2159
__IOM uint32_t TBLOFF
Definition: tle987x.h:2274
__IOM uint32_t EXTERNAL
Definition: tle987x.h:2447
__IOM uint32_t PRI_13
Definition: tle987x.h:2361
__IOM uint32_t SLEEPONEXIT
Definition: tle987x.h:2302
__IOM uint32_t PENDSVACT
Definition: tle987x.h:2381
__IOM uint32_t SYSRESETREQ
Definition: tle987x.h:2286
__IM uint32_t ARCHITECTURE
Definition: tle987x.h:2238
__IOM uint32_t PRI_14
Definition: tle987x.h:2362
__IM uint32_t Int_ADC1
Definition: tle987x.h:2160
__IOM uint32_t Int_GPT2
Definition: tle987x.h:2054
__IOM uint32_t PRIGROUP
Definition: tle987x.h:2288
__IOM uint32_t Int_UART2
Definition: tle987x.h:2064
__IOM uint32_t Int_BDRV
Definition: tle987x.h:2067
__IOM uint32_t VECTTBL
Definition: tle987x.h:2430
__IM uint32_t VECTACTIVE
Definition: tle987x.h:2250
__OM uint32_t PENDSTCLR
Definition: tle987x.h:2258
__IOM uint32_t PRI_EXINT0
Definition: tle987x.h:2222
__IOM uint32_t Int_SSC2
Definition: tle987x.h:2062
__IOM uint32_t HALTED
Definition: tle987x.h:2443
__IOM uint32_t PRI_11
Definition: tle987x.h:2350
__IOM uint32_t USGFAULTPENDED
Definition: tle987x.h:2383
__IOM uint32_t PRI_GPT2
Definition: tle987x.h:2184
__IM uint32_t IMPLEMENTER
Definition: tle987x.h:2240
__IOM uint32_t PRI_15
Definition: tle987x.h:2363
__IOM uint32_t NONBASETHRDENA
Definition: tle987x.h:2315
__IOM uint32_t CP11
Definition: tle987x.h:2487
__IM uint32_t Int_EXINT1
Definition: tle987x.h:2170
__IOM uint32_t SEVONPEND
Definition: tle987x.h:2305
__IM uint32_t Int_UART1
Definition: tle987x.h:2167
__IOM uint32_t MEMFAULTENA
Definition: tle987x.h:2387
__IM uint32_t INTLINESNUM
Definition: tle987x.h:1994
__IOM uint32_t UNALIGN_TRP
Definition: tle987x.h:2318
__IOM uint32_t SVCALLACT
Definition: tle987x.h:2378
__IOM uint32_t Int_ADC1
Definition: tle987x.h:2056
__IOM uint32_t PRI_DMA
Definition: tle987x.h:2225
__IOM uint32_t MEMFAULTACT
Definition: tle987x.h:2373
__IOM uint32_t Int_GPT1
Definition: tle987x.h:2053
__IOM uint32_t CP5
Definition: tle987x.h:2482
__IOM uint32_t Int_EXINT1
Definition: tle987x.h:2066
__IM uint32_t
Definition: tle987x.h:2008
__IOM uint32_t PRECISERR
Definition: tle987x.h:2407
__IOM uint32_t BUSFAULTENA
Definition: tle987x.h:2388
__IOM uint32_t USGFAULTENA
Definition: tle987x.h:2389
__IOM uint32_t FORCED
Definition: tle987x.h:2432
__IOM uint32_t COUNTFLAG
Definition: tle987x.h:2009
__IOM uint32_t PRI_10
Definition: tle987x.h:2349
__IOM uint32_t ENABLE
Definition: tle987x.h:2005
__IM uint32_t Int_BDRV
Definition: tle987x.h:2171
__IOM uint32_t BFHFMIGN
Definition: tle987x.h:2322
__IOM uint32_t NOCP
Definition: tle987x.h:2416
__IOM uint32_t CURRENT
Definition: tle987x.h:2029
__IOM uint32_t Int_CCU6SR0
Definition: tle987x.h:2057
__IM uint32_t ISRPENDING
Definition: tle987x.h:2255
__IOM uint32_t IACCVIOL
Definition: tle987x.h:2399
__IOM uint32_t MUNSTKERR
Definition: tle987x.h:2402
__IM uint32_t Int_SSC1
Definition: tle987x.h:2165
__IM uint32_t Int_SSC2
Definition: tle987x.h:2166
__IOM uint32_t PRI_12
Definition: tle987x.h:2360
__IOM uint32_t MEMFAULTPENDED
Definition: tle987x.h:2384
__IOM uint32_t IMPRECISERR
Definition: tle987x.h:2408
__IOM uint32_t STKALIGN
Definition: tle987x.h:2324
__IOM uint32_t Int_UART1
Definition: tle987x.h:2063
__IM uint32_t TENMS
Definition: tle987x.h:2039
__IM uint32_t PARTNO
Definition: tle987x.h:2237
__IOM uint32_t PRI_CCU6SR3
Definition: tle987x.h:2199
__IOM uint32_t ADDRESS
Definition: tle987x.h:2457
__IOM uint32_t PRI_ADC1
Definition: tle987x.h:2186
__IOM uint32_t BUSFAULTPENDED
Definition: tle987x.h:2385
__IOM uint32_t PRI_CCU6SR2
Definition: tle987x.h:2198
__IOM uint32_t MSTERR
Definition: tle987x.h:2403
__IOM uint32_t VCATCH
Definition: tle987x.h:2446
__IOM uint32_t UNDEFINSTR
Definition: tle987x.h:2413
__IOM uint32_t SLEEPDEEP
Definition: tle987x.h:2303
__IOM uint32_t PRI_UART1
Definition: tle987x.h:2211
__IM uint32_t SKEW
Definition: tle987x.h:2041
__IM uint32_t RESERVED
Definition: tle987x.h:1986
__IOM uint32_t PRI_9
Definition: tle987x.h:2348
__IM uint32_t REVISION
Definition: tle987x.h:2236
__IOM uint32_t CP7
Definition: tle987x.h:2484
__IOM uint32_t CP4
Definition: tle987x.h:2481
__IOM uint32_t PRI_CCU6SR0
Definition: tle987x.h:2196
__IOM uint32_t PRI_SSC1
Definition: tle987x.h:2209
__IOM uint32_t PRI_5
Definition: tle987x.h:2335
__IM uint32_t Int_CCU6SR3
Definition: tle987x.h:2164
__IOM uint32_t VECTCLRACTIVE
Definition: tle987x.h:2285
__IOM uint32_t PRI_7
Definition: tle987x.h:2337
__IOM uint32_t TICKINT
Definition: tle987x.h:2006
__IM uint32_t Int_CCU6SR1
Definition: tle987x.h:2162
__IOM uint32_t INVSTATE
Definition: tle987x.h:2414
__IOM uint32_t reg
Definition: tle987x.h:1990
__IOM uint32_t VECTKEY
Definition: tle987x.h:2291
__IOM uint32_t PENDSVSET
Definition: tle987x.h:2261
__IOM uint32_t SYSTICKACT
Definition: tle987x.h:2382
__IOM uint32_t PRI_SSC2
Definition: tle987x.h:2210
__IM uint32_t Int_CCU6SR2
Definition: tle987x.h:2163
__IOM uint32_t INVPC
Definition: tle987x.h:2415
__IM uint32_t ENDIANNESS
Definition: tle987x.h:2290
__IM uint32_t Int_EXINT0
Definition: tle987x.h:2169
__IOM uint32_t CP1
Definition: tle987x.h:2478
__IM uint32_t RETTOBASE
Definition: tle987x.h:2252
__IOM uint32_t NMIPENDSET
Definition: tle987x.h:2263
__IOM uint32_t Int_CCU6SR3
Definition: tle987x.h:2060
__IOM uint32_t UNALIGNED
Definition: tle987x.h:2418
__IOM uint32_t Int_DMA
Definition: tle987x.h:2068
__IM uint32_t NOREF
Definition: tle987x.h:2042
__IOM uint32_t VECTRESET
Definition: tle987x.h:2284
__IOM uint32_t CP6
Definition: tle987x.h:2483
__IOM uint32_t MONITORACT
Definition: tle987x.h:2379
__IOM uint32_t CP2
Definition: tle987x.h:2479
__IM uint32_t VARIANT
Definition: tle987x.h:2239
__IOM uint32_t Int_EXINT0
Definition: tle987x.h:2065
__IOM uint32_t STKERR
Definition: tle987x.h:2410
__IOM uint32_t BKPT
Definition: tle987x.h:2444
__IOM uint32_t IBUSERR
Definition: tle987x.h:2406
__IOM uint32_t PENDSTSET
Definition: tle987x.h:2259
__IOM uint32_t Int_ADC2
Definition: tle987x.h:2055
__IOM uint32_t MMARVALID
Definition: tle987x.h:2405
__IOM uint32_t Int_CCU6SR1
Definition: tle987x.h:2058
__IM uint32_t ISRPREEMPT
Definition: tle987x.h:2256
__IOM uint32_t BFARVALID
Definition: tle987x.h:2412
__IOM uint32_t PRI_4
Definition: tle987x.h:2334
__IM uint32_t Int_UART2
Definition: tle987x.h:2168
__IOM uint32_t DACCVIOL
Definition: tle987x.h:2400
__IOM uint32_t USERSETMPEND
Definition: tle987x.h:2316
__IOM uint32_t UNSTKERR
Definition: tle987x.h:2409
__IOM uint32_t BUSFAULTACT
Definition: tle987x.h:2374
__IM uint32_t VECTPENDING
Definition: tle987x.h:2253
__OM uint32_t PENDSVCLR
Definition: tle987x.h:2260
__IOM uint32_t PRI_EXINT1
Definition: tle987x.h:2223
Current Sense Amplifier (CSA)
Definition: tle987x.h:2504
__IO uint32_t reg
Definition: tle987x.h:2509
__IO uint32_t EN
Definition: tle987x.h:2513
__IO uint32_t GAIN
Definition: tle987x.h:2514
__IO uint32_t VZERO
Definition: tle987x.h:2516
Direct Memeory Access (DMA)
Definition: tle987x.h:2532
__IM uint32_t MASTER_ENABLE
Definition: tle987x.h:2540
__IOM uint32_t CHNL_PRIORITY_SET
Definition: tle987x.h:2708
__IM uint32_t WAITONREQ_STATUS
Definition: tle987x.h:2587
__OM uint32_t MASTER_ENABLE
Definition: tle987x.h:2554
__IM uint32_t
Definition: tle987x.h:2541
__IM uint32_t STATE
Definition: tle987x.h:2542
__IOM uint32_t ERR_CLR
Definition: tle987x.h:2734
__OM uint32_t CHNL_SW_REQUEST
Definition: tle987x.h:2597
__OM uint32_t CHNL_USEBURST_CLR
Definition: tle987x.h:2625
__OM uint32_t CHNL_REQ_MASK_CLR
Definition: tle987x.h:2650
__IOM uint32_t reg
Definition: tle987x.h:2536
__OM uint32_t CHNL_PRIORITY_CLR
Definition: tle987x.h:2723
__OM uint32_t CHNL_ENABLE_CLR
Definition: tle987x.h:2673
__IM uint32_t CHNLS_MINUS1
Definition: tle987x.h:2544
__IM uint32_t ALT_CTRL_BASE_PTR
Definition: tle987x.h:2577
__IOM uint32_t CHNL_USEBURST_SET
Definition: tle987x.h:2607
__IOM uint32_t CHNL_REQ_MASK_SET
Definition: tle987x.h:2635
__IOM uint32_t CTRL_BASE_PTR
Definition: tle987x.h:2567
__IOM uint32_t CHNL_ENABLE_SET
Definition: tle987x.h:2660
__IOM uint32_t CHNL_PRI_ALT_SET
Definition: tle987x.h:2683
__OM uint32_t CHN1_PROT_CTRL
Definition: tle987x.h:2556
__OM uint32_t CHNL_PRI_ALT_CLR
Definition: tle987x.h:2698
General Purpose Timer 12E (GPT12E)
Definition: tle987x.h:2753
__IOM uint16_t T2I
Definition: tle987x.h:2794
__IOM uint16_t T4UD
Definition: tle987x.h:2839
__IOM uint16_t T3EDGE
Definition: tle987x.h:2823
__IOM uint16_t T3UDE
Definition: tle987x.h:2819
__IOM uint16_t T5R
Definition: tle987x.h:2861
__IOM uint16_t T4CHDIR
Definition: tle987x.h:2846
__IOM uint16_t IST6IN
Definition: tle987x.h:2781
__IOM uint16_t T4IRDIS
Definition: tle987x.h:2844
__IOM uint16_t IST4IN
Definition: tle987x.h:2777
__IOM uint16_t T4
Definition: tle987x.h:2934
__IOM uint16_t T2R
Definition: tle987x.h:2796
__IOM uint16_t T5UDE
Definition: tle987x.h:2863
__IM uint16_t T4RDIR
Definition: tle987x.h:2847
__IOM uint16_t T4RC
Definition: tle987x.h:2841
__IM uint16_t T3RDIR
Definition: tle987x.h:2825
__IOM uint16_t T6M
Definition: tle987x.h:2881
__IOM uint16_t CLRT2EN
Definition: tle987x.h:2842
__IOM uint16_t IST5EUD
Definition: tle987x.h:2780
__IOM uint16_t T6OTL
Definition: tle987x.h:2886
__IOM uint16_t T6OE
Definition: tle987x.h:2885
__IM uint16_t RESERVED8
Definition: tle987x.h:2915
__IOM uint16_t T6SR
Definition: tle987x.h:2890
__IOM uint16_t T5I
Definition: tle987x.h:2858
__IM uint16_t RESERVED4
Definition: tle987x.h:2850
__IOM uint16_t T5RC
Definition: tle987x.h:2864
__IOM uint16_t T3M
Definition: tle987x.h:2816
__IM uint16_t MOD_TYPE
Definition: tle987x.h:2762
__IM uint16_t
Definition: tle987x.h:2800
__IOM uint16_t T2IRDIS
Definition: tle987x.h:2801
__IOM uint16_t T3UD
Definition: tle987x.h:2818
__IOM uint16_t T6UD
Definition: tle987x.h:2883
__IOM uint16_t T6I
Definition: tle987x.h:2880
__IM uint16_t RESERVED10
Definition: tle987x.h:2937
__IOM uint16_t T4R
Definition: tle987x.h:2838
__IOM uint16_t T3R
Definition: tle987x.h:2817
__IOM uint16_t CT3
Definition: tle987x.h:2865
__IOM uint16_t T4EDGE
Definition: tle987x.h:2845
__IOM uint16_t CI
Definition: tle987x.h:2867
__IOM uint16_t T2EDGE
Definition: tle987x.h:2802
__IOM uint16_t reg
Definition: tle987x.h:2757
__IOM uint16_t BPS1
Definition: tle987x.h:2822
__IM uint16_t RESERVED6
Definition: tle987x.h:2893
__IOM uint16_t IST4EUD
Definition: tle987x.h:2778
__IOM uint16_t T2UDE
Definition: tle987x.h:2798
__IOM uint16_t ISCAPIN
Definition: tle987x.h:2783
__IOM uint16_t IST3IN
Definition: tle987x.h:2775
__IOM uint16_t T3CHDIR
Definition: tle987x.h:2824
__IOM uint16_t T6R
Definition: tle987x.h:2882
__IOM uint16_t T6
Definition: tle987x.h:2956
__IOM uint16_t T5
Definition: tle987x.h:2945
__IOM uint16_t IST2IN
Definition: tle987x.h:2773
__IOM uint16_t T4M
Definition: tle987x.h:2837
__IOM uint16_t T3OTL
Definition: tle987x.h:2821
__IOM uint16_t IST2EUD
Definition: tle987x.h:2774
__IOM uint16_t T5SC
Definition: tle987x.h:2869
__IOM uint16_t T2CHDIR
Definition: tle987x.h:2803
__IOM uint16_t T2M
Definition: tle987x.h:2795
__IM uint16_t RESERVED11
Definition: tle987x.h:2948
__IM uint16_t T2RDIR
Definition: tle987x.h:2804
__IM uint16_t MOD_REV
Definition: tle987x.h:2761
__IOM uint16_t T3OE
Definition: tle987x.h:2820
__IOM uint16_t IST3EUD
Definition: tle987x.h:2776
__IOM uint16_t IST5IN
Definition: tle987x.h:2779
__IOM uint16_t T4I
Definition: tle987x.h:2836
__IOM uint16_t T3
Definition: tle987x.h:2923
__IM uint16_t RESERVED5
Definition: tle987x.h:2872
__IOM uint16_t T5UD
Definition: tle987x.h:2862
__IM uint16_t RESERVED9
Definition: tle987x.h:2926
__IOM uint16_t T4UDE
Definition: tle987x.h:2840
__IOM uint16_t T6UDE
Definition: tle987x.h:2884
__IOM uint16_t CLRT3EN
Definition: tle987x.h:2843
__IOM uint16_t T5CLR
Definition: tle987x.h:2868
__IOM uint16_t T6CLR
Definition: tle987x.h:2889
__IOM uint16_t CAPREL
Definition: tle987x.h:2901
__IM uint16_t RESERVED1
Definition: tle987x.h:2786
__IOM uint16_t T3I
Definition: tle987x.h:2815
__IM uint16_t RESERVED7
Definition: tle987x.h:2904
__IM uint16_t RESERVED3
Definition: tle987x.h:2828
__IOM uint16_t BPS2
Definition: tle987x.h:2887
__IM uint16_t RESERVED
Definition: tle987x.h:2765
__IOM uint16_t T2
Definition: tle987x.h:2912
__IOM uint16_t T5M
Definition: tle987x.h:2859
__IM uint16_t RESERVED2
Definition: tle987x.h:2807
__IOM uint16_t IST6EUD
Definition: tle987x.h:2782
__IOM uint16_t T2RC
Definition: tle987x.h:2799
__IOM uint16_t T2UD
Definition: tle987x.h:2797
Local Interconnect Network (LIN)
Definition: tle987x.h:2973
__IM uint32_t FB_SM2
Definition: tle987x.h:2993
__IOM uint32_t SM
Definition: tle987x.h:2991
__IM uint32_t FB_SM1
Definition: tle987x.h:2992
__IOM uint32_t HV_MODE
Definition: tle987x.h:2997
__IM uint32_t MODE_FB
Definition: tle987x.h:2995
__IM uint32_t OT_STS
Definition: tle987x.h:2984
__IM uint32_t
Definition: tle987x.h:2981
__IM uint32_t TXD_TMOUT_STS
Definition: tle987x.h:2986
__IM uint32_t FB_SM3
Definition: tle987x.h:2994
__IM uint32_t RXD
Definition: tle987x.h:2990
__IOM uint32_t TXD
Definition: tle987x.h:2988
__IOM uint32_t M_SM_ERR_CLR
Definition: tle987x.h:2999
__IOM uint32_t reg
Definition: tle987x.h:2977
__IM uint32_t OC_STS
Definition: tle987x.h:2985
__IM uint32_t M_SM_ERR
Definition: tle987x.h:2983
__IOM uint32_t MODE
Definition: tle987x.h:2982
Measurement Function (MF)
Definition: tle987x.h:3016
__IM uint32_t REFBG_LOTHWARN_STS
Definition: tle987x.h:3096
__IM uint32_t PMU_OT_STS
Definition: tle987x.h:3083
__IOM uint32_t PHUCOMP_ON
Definition: tle987x.h:3062
__IOM uint32_t BEMF_TFILT_SEL
Definition: tle987x.h:3127
__IM uint32_t PHU_ZC_STS
Definition: tle987x.h:3068
__IM uint32_t PHW_ZC_STS
Definition: tle987x.h:3070
__IOM uint32_t PHWCOMP_ON
Definition: tle987x.h:3064
__IOM uint32_t ADC3_INN_SEL
Definition: tle987x.h:3031
__IOM uint32_t P2_3_ADC_SEL
Definition: tle987x.h:3026
__IOM uint32_t BEMF_BT_TFILT_SEL
Definition: tle987x.h:3123
__IM uint32_t PHV_ZC_STS
Definition: tle987x.h:3069
__IOM uint32_t VMON_SEN_HRESO_5V
Definition: tle987x.h:3044
__IM uint32_t VREF5V_OV_STS
Definition: tle987x.h:3112
__IM uint32_t REFBG_UPTHWARN_STS
Definition: tle987x.h:3098
__IM uint32_t
Definition: tle987x.h:3029
__IOM uint32_t P2_5_ADC_SEL
Definition: tle987x.h:3028
__IM uint32_t SYS_OT_STS
Definition: tle987x.h:3085
__IM uint32_t VREF5V_UV_STS
Definition: tle987x.h:3111
__IOM uint32_t VMON_SEN_PD_N
Definition: tle987x.h:3042
__IM uint32_t SYS_OTWARN_STS
Definition: tle987x.h:3084
__IOM uint32_t PHWCOMP_EN
Definition: tle987x.h:3057
__IOM uint32_t DEMGFILTDIS
Definition: tle987x.h:3058
__IOM uint32_t PHVCOMP_ON
Definition: tle987x.h:3063
__IOM uint32_t P2_4_ADC_SEL
Definition: tle987x.h:3027
__IOM uint32_t PHUCOMP_EN
Definition: tle987x.h:3055
__IM uint32_t PMU_OTWARN_STS
Definition: tle987x.h:3082
__IOM uint32_t P2_2_ADC_SEL
Definition: tle987x.h:3025
__IOM uint32_t VREF5V_PD_N
Definition: tle987x.h:3109
__IOM uint32_t reg
Definition: tle987x.h:3020
__IM uint32_t VREF5V_OVL_STS
Definition: tle987x.h:3110
__IOM uint32_t PHVCOMP_EN
Definition: tle987x.h:3056
__IOM uint32_t ADC1_CH1_SEL
Definition: tle987x.h:3032
__IOM uint32_t ADC3_INP_SEL
Definition: tle987x.h:3030
__IOM uint32_t GPT12CAPINSW
Definition: tle987x.h:3060
__IM uint32_t RESERVED1
Definition: tle987x.h:3115
__IOM uint32_t P2_0_ADC_SEL
Definition: tle987x.h:3024
__IOM uint32_t FILTBYPS
Definition: tle987x.h:3059
__IOM uint32_t VMON_SEN_SEL_INRANGE
Definition: tle987x.h:3045
__IOM uint32_t CCPOS_INSEL
Definition: tle987x.h:3066
__IOM uint32_t BEMF_GPT_CAPIN_SEL
Definition: tle987x.h:3125
__IM uint32_t RESERVED0
Definition: tle987x.h:3073
MON (MON)
Definition: tle987x.h:3143
__IO uint8_t CYC
Definition: tle987x.h:3155
__IO uint8_t PD
Definition: tle987x.h:3156
__IO uint8_t PU
Definition: tle987x.h:3157
__IO uint8_t EN
Definition: tle987x.h:3152
__IO uint8_t FALL
Definition: tle987x.h:3153
__IO uint8_t RISE
Definition: tle987x.h:3154
__I uint8_t STS
Definition: tle987x.h:3159
__IO uint8_t reg
Definition: tle987x.h:3148
Power Management Unit (PMU)
Definition: tle987x.h:3175
__IOM uint8_t LOCKUP
Definition: tle987x.h:3258
__IOM uint8_t GPIO0_FA_3
Definition: tle987x.h:3514
__IOM uint8_t GPIO0_RI_2
Definition: tle987x.h:3498
__IOM uint8_t GPIO0_RI_0
Definition: tle987x.h:3496
__IOM uint8_t CNF_MON_FT
Definition: tle987x.h:3418
__IOM uint8_t DATA1
Definition: tle987x.h:3441
__IM uint8_t GPIO0_STS_4
Definition: tle987x.h:3391
__IOM uint8_t PMU_1V5DidPOR
Definition: tle987x.h:3245
__IOM uint8_t CNF_LIN_FT
Definition: tle987x.h:3417
__IOM uint8_t GPIO1_RI_0
Definition: tle987x.h:3541
__IOM uint8_t GPIO1_RI_3
Definition: tle987x.h:3544
__IOM uint8_t CYC_WAKE_EN
Definition: tle987x.h:3272
__IOM uint8_t SUPPFAIL
Definition: tle987x.h:3363
__IM uint8_t PMU_5V_OVERLOAD
Definition: tle987x.h:3206
__IM uint8_t PMU_5V_OVERVOLT
Definition: tle987x.h:3205
__IOM uint8_t GPIO1_FA_0
Definition: tle987x.h:3556
__IOM uint8_t GPIO0_FA_4
Definition: tle987x.h:3515
__IOM uint8_t OVERLOAD
Definition: tle987x.h:3224
__IOM uint8_t PMU_1V5_OVL
Definition: tle987x.h:3348
__IOM uint8_t M03
Definition: tle987x.h:3286
__IM uint8_t GPIO1_STS_1
Definition: tle987x.h:3403
__IM uint8_t GPIO1_STS_4
Definition: tle987x.h:3406
__IOM uint8_t PMU_ClkWDT
Definition: tle987x.h:3242
__IM uint8_t GPIO1
Definition: tle987x.h:3187
__IOM uint8_t GPIO0_CYC_0
Definition: tle987x.h:3526
__IOM uint8_t PMU_5V_FAIL_EN
Definition: tle987x.h:3207
__IM uint8_t LIN_WAKE
Definition: tle987x.h:3183
__IOM uint8_t DATA2
Definition: tle987x.h:3452
__IOM uint8_t DATA5
Definition: tle987x.h:3485
__IOM uint8_t DATA0
Definition: tle987x.h:3430
__IOM uint8_t GPIO0_RI_4
Definition: tle987x.h:3500
__IM uint8_t
Definition: tle987x.h:3204
__IOM uint8_t GPIO1_RI_1
Definition: tle987x.h:3542
__IOM uint8_t OSC_100kHz_EN
Definition: tle987x.h:3289
__IOM uint8_t LIN_EN
Definition: tle987x.h:3324
__IM uint8_t GPIO0_STS_1
Definition: tle987x.h:3388
__IOM uint8_t GPIO0_CYC_2
Definition: tle987x.h:3528
__IM uint8_t GPIO1_STS_0
Definition: tle987x.h:3402
__IOM uint8_t GPIO1_RI_2
Definition: tle987x.h:3543
__IOM uint8_t E01
Definition: tle987x.h:3287
__IOM uint8_t WAKE_W_RST
Definition: tle987x.h:3269
__IOM uint8_t GPIO1_CYC_3
Definition: tle987x.h:3574
__IOM uint8_t GPIO0_RI_3
Definition: tle987x.h:3499
__IOM uint8_t GPIO0_CYC_1
Definition: tle987x.h:3527
__IOM uint8_t PMU_ExtWDT
Definition: tle987x.h:3243
__IOM uint8_t DATA4
Definition: tle987x.h:3474
__IOM uint8_t SUPP_SHORT
Definition: tle987x.h:3346
__IOM uint8_t GPIO1_FA_2
Definition: tle987x.h:3558
__IOM uint8_t MBIST_EN
Definition: tle987x.h:3586
__IM uint8_t WAKE_STS
Definition: tle987x.h:3376
__IOM uint8_t GPIO0_RI_1
Definition: tle987x.h:3497
__IM uint8_t GPIO0
Definition: tle987x.h:3185
__IOM uint8_t OVERVOLT
Definition: tle987x.h:3223
__IM uint8_t GPIO0_STS_3
Definition: tle987x.h:3390
__IOM uint8_t SHORT
Definition: tle987x.h:3222
__IOM uint8_t GPIO1_FA_3
Definition: tle987x.h:3559
__IOM uint8_t GPIO1_RI_4
Definition: tle987x.h:3545
__IOM uint8_t GPIO1_FA_4
Definition: tle987x.h:3560
__IOM uint8_t WDT1_SEQ_FAIL
Definition: tle987x.h:3352
__IM uint8_t MON_WAKE
Definition: tle987x.h:3184
__IOM uint8_t GPIO0_FA_0
Definition: tle987x.h:3511
__IM uint8_t FAIL
Definition: tle987x.h:3190
__IOM uint8_t CYC_EN
Definition: tle987x.h:3219
__IOM uint8_t GPIO0_CYC_3
Definition: tle987x.h:3529
__IM uint8_t STABLE
Definition: tle987x.h:3226
__IOM uint8_t RST_TFB
Definition: tle987x.h:3335
__IOM uint8_t SUPP_TMOUT
Definition: tle987x.h:3347
__IOM uint8_t VDDEXTSHORT
Definition: tle987x.h:3365
__IOM uint8_t GPIO0_CYC_4
Definition: tle987x.h:3530
__IOM uint8_t CNF_GPIO_FT
Definition: tle987x.h:3419
__IM uint8_t OK
Definition: tle987x.h:3225
__IOM uint8_t FAIL_EN
Definition: tle987x.h:3220
__IOM uint8_t PMU_WAKE
Definition: tle987x.h:3239
__IOM uint8_t GPIO1_CYC_4
Definition: tle987x.h:3575
__IM uint8_t GPIO1_STS_3
Definition: tle987x.h:3405
__IOM uint8_t PMU_5V_OVL
Definition: tle987x.h:3349
__IOM uint8_t PMU_IntWDT
Definition: tle987x.h:3256
__IM uint8_t CYC_WAKE
Definition: tle987x.h:3189
__IOM uint8_t GPIO0_FA_1
Definition: tle987x.h:3512
__IM uint8_t PMU_1V5_OVERVOLT
Definition: tle987x.h:3201
__IM uint8_t GPIO0_STS_2
Definition: tle987x.h:3389
__IM uint8_t GPIO0_STS_0
Definition: tle987x.h:3387
__IOM uint8_t GPIO0_FA_2
Definition: tle987x.h:3513
__IOM uint8_t SYS_FAIL
Definition: tle987x.h:3237
__IOM uint8_t PMU_PIN
Definition: tle987x.h:3244
__IOM uint8_t PMU_SOFT
Definition: tle987x.h:3257
__IOM uint8_t PMU_SleepEX
Definition: tle987x.h:3240
__IOM uint8_t DATA3
Definition: tle987x.h:3463
__IOM uint8_t GPIO1_FA_1
Definition: tle987x.h:3557
__IM uint8_t GPIO1_STS_2
Definition: tle987x.h:3404
__IOM uint8_t PMU_LPR
Definition: tle987x.h:3241
__IM uint8_t PMU_1V5_OVERLOAD
Definition: tle987x.h:3202
__IOM uint8_t GPIO1_CYC_0
Definition: tle987x.h:3571
__IOM uint8_t GPIO1_CYC_2
Definition: tle987x.h:3573
__IOM uint8_t reg
Definition: tle987x.h:3179
__IOM uint8_t GPIO1_CYC_1
Definition: tle987x.h:3572
__IOM uint8_t SYS_OT
Definition: tle987x.h:3351
__IOM uint8_t EN_VDDEXT_OC_OFF_N
Definition: tle987x.h:3275
__IOM uint8_t EN_0V9_N
Definition: tle987x.h:3270
__IOM uint8_t ENABLE
Definition: tle987x.h:3218
__IOM uint8_t PMU_1V5_FAIL_EN
Definition: tle987x.h:3203
__IOM uint8_t CYC_SENSE_EN
Definition: tle987x.h:3273
GPIO PORTs (PORT)
Definition: tle987x.h:3604
__IM uint8_t P4
Definition: tle987x.h:3676
__IOM uint8_t P1
Definition: tle987x.h:3613
__IM uint8_t P2
Definition: tle987x.h:3674
__IOM uint8_t P4
Definition: tle987x.h:3616
__IM uint8_t
Definition: tle987x.h:3673
__IOM uint8_t P0
Definition: tle987x.h:3612
__IM uint8_t P5
Definition: tle987x.h:3677
__IM uint8_t P0
Definition: tle987x.h:3672
__IOM uint8_t P2
Definition: tle987x.h:3614
__IOM uint8_t P3_P2
Definition: tle987x.h:3874
__IOM uint8_t P3
Definition: tle987x.h:3615
__IM uint8_t P3
Definition: tle987x.h:3675
__IOM uint8_t reg
Definition: tle987x.h:3608
__IOM uint8_t P5
Definition: tle987x.h:3693
System Control Unit (SCU)
Definition: tle987x.h:3892
__IOM uint8_t CH8IE
Definition: tle987x.h:4815
__OM uint8_t T2C
Definition: tle987x.h:4931
__OM uint8_t EXINT0RC
Definition: tle987x.h:4051
__IOM uint8_t NMIECC
Definition: tle987x.h:4025
__IM uint8_t FNMIECC
Definition: tle987x.h:3995
__IOM uint8_t LOCKUP
Definition: tle987x.h:4283
__IOM uint8_t K1DIV
Definition: tle987x.h:4166
__IOM uint8_t T2_DIS
Definition: tle987x.h:4255
__IOM uint8_t SECTORINFO
Definition: tle987x.h:4664
__IOM uint8_t TIREN1
Definition: tle987x.h:4078
__OM uint8_t CCU6SR2C
Definition: tle987x.h:5032
__IM uint8_t TRSEQ1DY
Definition: tle987x.h:4880
__IOM uint8_t T3IE
Definition: tle987x.h:4898
__IOM uint8_t T4IE
Definition: tle987x.h:4899
__OM uint8_t CH6C
Definition: tle987x.h:4989
__OM uint8_t NMINVMC
Definition: tle987x.h:3902
__IM uint8_t T2
Definition: tle987x.h:4914
__IOM uint8_t BR_VALUE
Definition: tle987x.h:4392
__IOM uint8_t PDM3
Definition: tle987x.h:4722
__IOM uint8_t EXINT1IS
Definition: tle987x.h:4537
__IM uint8_t NVM_ADDR_ERR
Definition: tle987x.h:4691
__OM uint8_t NMIWDTC
Definition: tle987x.h:3900
__IOM uint8_t SL
Definition: tle987x.h:4136
__IOM uint8_t T2_SUSP
Definition: tle987x.h:4594
__IOM uint8_t EXINT2IS
Definition: tle987x.h:4538
__OM uint8_t T3C
Definition: tle987x.h:4932
__IM uint8_t CCU6SR1
Definition: tle987x.h:3965
__IM uint8_t EXINT1R
Definition: tle987x.h:3920
__IM uint8_t CH7
Definition: tle987x.h:4867
__OM uint8_t NMIECCC
Definition: tle987x.h:3906
__IM uint8_t EXINT1F
Definition: tle987x.h:3921
__OM uint8_t RIRC
Definition: tle987x.h:4949
__IOM uint8_t OSCSS
Definition: tle987x.h:4505
__OM uint8_t RDBEC
Definition: tle987x.h:4793
__IOM uint8_t SSC2_DIS
Definition: tle987x.h:4268
__IOM uint8_t K2DIV
Definition: tle987x.h:4165
__IOM uint8_t COUTS0
Definition: tle987x.h:4522
__IOM uint8_t CRIE
Definition: tle987x.h:4902
__IOM uint8_t T12PM_DMAEN
Definition: tle987x.h:4846
__IOM uint8_t MU_SUSP
Definition: tle987x.h:4609
__IOM uint8_t VCOBYP
Definition: tle987x.h:4152
__IOM uint8_t EXINT0IS
Definition: tle987x.h:4536
__IOM uint8_t IE1
Definition: tle987x.h:4124
__IOM uint8_t CPCLK_DIV
Definition: tle987x.h:4212
__IOM uint8_t RIEN2
Definition: tle987x.h:4098
__IOM uint8_t WDTWINB
Definition: tle987x.h:4345
__IOM uint8_t CPCLK_SEL
Definition: tle987x.h:4211
__OM uint8_t CCU6SR1C
Definition: tle987x.h:5021
__IM uint8_t EXINT2R
Definition: tle987x.h:3922
__IOM uint8_t RIREN2
Definition: tle987x.h:4095
__OM uint8_t TIRC
Definition: tle987x.h:4948
__IM uint8_t T5
Definition: tle987x.h:4917
__IOM uint8_t NVMIE
Definition: tle987x.h:4637
__OM uint8_t EXINT1RC
Definition: tle987x.h:4055
__IOM uint8_t XTAL_ON
Definition: tle987x.h:4135
__IOM uint8_t NMIMAP
Definition: tle987x.h:4024
__IOM uint8_t CH6IE
Definition: tle987x.h:4813
__IOM uint8_t GPT12CAPINB
Definition: tle987x.h:4551
__OM uint8_t GPT12C
Definition: tle987x.h:5007
__OM uint8_t NMIOWDC
Definition: tle987x.h:3904
__OM uint8_t CCU6SR3C
Definition: tle987x.h:5034
__IOM uint8_t BRDIS
Definition: tle987x.h:4414
__OM uint8_t TRSEQ1DYC
Definition: tle987x.h:5003
__OM uint8_t BRKC
Definition: tle987x.h:4467
__IOM uint8_t COUTS1
Definition: tle987x.h:4524
__IOM uint8_t NMISUP
Definition: tle987x.h:4026
__OM uint8_t CH3C
Definition: tle987x.h:4986
__IOM uint8_t COREL
Definition: tle987x.h:4521
__IOM uint8_t T21_DIS
Definition: tle987x.h:4270
__IM uint8_t T6
Definition: tle987x.h:4918
__IOM uint8_t PDM0
Definition: tle987x.h:4707
__IOM uint8_t T5IE
Definition: tle987x.h:4900
__IOM uint8_t EN
Definition: tle987x.h:4525
__IOM uint8_t NVMPROTSTSL_2
Definition: tle987x.h:4678
__IOM uint8_t WINBEN
Definition: tle987x.h:4194
__IOM uint8_t RESLD
Definition: tle987x.h:4150
__IM uint8_t MONF
Definition: tle987x.h:3925
__IM uint8_t EIR
Definition: tle987x.h:3937
__IOM uint8_t CCU6_DIS
Definition: tle987x.h:4254
__IM uint8_t MONSTS
Definition: tle987x.h:4113
__OM uint8_t MONFC
Definition: tle987x.h:4065
__OM uint8_t SSC1C
Definition: tle987x.h:5005
__IOM uint8_t TRSEQ1RDYIE
Definition: tle987x.h:4827
__OM uint8_t CH5C
Definition: tle987x.h:4988
__IM uint8_t APCLK1STS
Definition: tle987x.h:4226
__IM uint8_t FNMINVM
Definition: tle987x.h:3991
__IOM uint8_t TLEN
Definition: tle987x.h:4523
__IOM uint8_t VCOSEL
Definition: tle987x.h:4167
__IOM uint8_t T21IS
Definition: tle987x.h:4566
__IM uint8_t FNMIOT
Definition: tle987x.h:3992
__IM uint8_t SSCTX
Definition: tle987x.h:4848
__IM uint8_t CR
Definition: tle987x.h:4919
__IOM uint8_t EXINT1
Definition: tle987x.h:4038
__IOM uint8_t BRPRE
Definition: tle987x.h:4379
__IOM uint8_t ADC1_SUSP
Definition: tle987x.h:4610
__IOM uint8_t APCLK1FAC
Definition: tle987x.h:4223
__IOM uint8_t IE0
Definition: tle987x.h:4110
__IOM uint8_t CH1IE
Definition: tle987x.h:4808
__IM uint8_t
Definition: tle987x.h:3964
__IOM uint8_t OSCDISC
Definition: tle987x.h:4151
__IOM uint8_t LOCKUP_EN
Definition: tle987x.h:4285
__IM uint8_t CCU6SR2
Definition: tle987x.h:3976
__IOM uint8_t TCC
Definition: tle987x.h:4744
__OM uint8_t GPT12_T3C
Definition: tle987x.h:5048
__IOM uint8_t SSCRXIE
Definition: tle987x.h:4830
__IOM uint8_t APCLK1SCLR
Definition: tle987x.h:4224
__OM uint8_t TRSEQ2DYC
Definition: tle987x.h:5004
__IOM uint8_t R
Definition: tle987x.h:4378
__IOM uint8_t T2IS
Definition: tle987x.h:4565
__OM uint8_t NMIMAPC
Definition: tle987x.h:3905
__IOM uint8_t T21EXCON
Definition: tle987x.h:4554
__IOM uint8_t SSCTXSRCSEL
Definition: tle987x.h:4843
__IM uint8_t BRK
Definition: tle987x.h:4416
__IOM uint8_t PDM1
Definition: tle987x.h:4709
__IOM uint8_t CH5IE
Definition: tle987x.h:4812
__IOM uint8_t WDTSUSP
Definition: tle987x.h:4591
__IM uint8_t CH2
Definition: tle987x.h:4862
__IOM uint8_t EA
Definition: tle987x.h:4008
__IM uint8_t FNMISUP
Definition: tle987x.h:3996
__OM uint8_t EIRC
Definition: tle987x.h:4947
__OM uint8_t EXINT1FC
Definition: tle987x.h:4057
__IOM uint8_t CLKWDT_IE
Definition: tle987x.h:4208
__OM uint8_t SDADCC
Definition: tle987x.h:5008
__IM uint8_t CH6
Definition: tle987x.h:4866
__IOM uint8_t TIEN1
Definition: tle987x.h:4082
__IOM uint8_t SDADCCLK_DIV
Definition: tle987x.h:4296
__OM uint8_t NMIPLLC
Definition: tle987x.h:3901
__IOM uint8_t APCLK3SCLR
Definition: tle987x.h:4228
__OM uint8_t EOFSYNC
Definition: tle987x.h:4468
__IOM uint8_t T12SUSP
Definition: tle987x.h:4592
__IM uint8_t EXINT0R
Definition: tle987x.h:3918
__IOM uint8_t TRSEQ2RDYIE
Definition: tle987x.h:4828
__IOM uint8_t T21_SUSP
Definition: tle987x.h:4597
__IOM uint8_t EIREN1
Definition: tle987x.h:4077
__IM uint8_t RDBE
Definition: tle987x.h:4649
__IOM uint8_t T12ZM_DMAEN
Definition: tle987x.h:4845
__IOM uint8_t T2EXCON
Definition: tle987x.h:4553
__IM uint8_t OSC2L
Definition: tle987x.h:4507
__IOM uint8_t TRIG_CONF
Definition: tle987x.h:4622
__IOM uint8_t URIOS1
Definition: tle987x.h:4539
__IOM uint8_t MRAMINITSTS
Definition: tle987x.h:4322
__IOM uint8_t INIT_FAIL
Definition: tle987x.h:4321
__IOM uint8_t SASTATUS
Definition: tle987x.h:4665
__IOM uint8_t T3_DIS
Definition: tle987x.h:4272
__IM uint8_t RSBE
Definition: tle987x.h:4653
__IM uint8_t FNMIWDT
Definition: tle987x.h:3989
__OM uint8_t EXINT0FC
Definition: tle987x.h:4053
__IOM uint8_t PD
Definition: tle987x.h:4137
__IOM uint8_t OSCWDTRST
Definition: tle987x.h:4506
__OM uint8_t T6C
Definition: tle987x.h:4935
__IM uint8_t VERID
Definition: tle987x.h:4480
__OM uint8_t MONRC
Definition: tle987x.h:4063
__IOM uint8_t BGSEL
Definition: tle987x.h:4415
__IM uint8_t EOFSYN
Definition: tle987x.h:4417
__IM uint8_t APCLK2STS
Definition: tle987x.h:4240
__IM uint8_t ROM_PROT_ERR
Definition: tle987x.h:4694
__IOM uint8_t APCLK2SCLR
Definition: tle987x.h:4241
__IOM uint8_t SD
Definition: tle987x.h:4138
__IOM uint8_t PBA0CLKREL
Definition: tle987x.h:4178
__IOM uint8_t NMIWDT
Definition: tle987x.h:4019
__IM uint8_t PLL_LOCK
Definition: tle987x.h:4205
__IOM uint8_t SYSCLKSEL
Definition: tle987x.h:4310
__IOM uint8_t NDIV
Definition: tle987x.h:4153
__IOM uint8_t WDTRS
Definition: tle987x.h:4190
__IM uint8_t FNMIOWD
Definition: tle987x.h:3993
__IM uint8_t GPT12_T3
Definition: tle987x.h:4850
__IM uint8_t CH8
Definition: tle987x.h:4868
__IOM uint8_t CLKREL
Definition: tle987x.h:4164
__IOM uint8_t APCLK_SET
Definition: tle987x.h:4206
__IOM uint8_t MODE
Definition: tle987x.h:4492
__IM uint8_t SSC1RDY
Definition: tle987x.h:4882
__IOM uint8_t RIE
Definition: tle987x.h:4635
__IM uint8_t EXINT0F
Definition: tle987x.h:3919
__IM uint8_t SSC2RDY
Definition: tle987x.h:4883
__OM uint8_t EXINT2FC
Definition: tle987x.h:4061
__OM uint8_t CH8C
Definition: tle987x.h:4991
__IM uint8_t APCLK3STS
Definition: tle987x.h:4227
__IOM uint8_t T2EXIS
Definition: tle987x.h:4567
__OM uint8_t CH1C
Definition: tle987x.h:4984
__IM uint8_t LOCK
Definition: tle987x.h:4149
__IOM uint8_t NVMPROTSTSL_1
Definition: tle987x.h:4677
__IM uint8_t CH1
Definition: tle987x.h:4861
__IM uint8_t CCU6SR3
Definition: tle987x.h:3978
__OM uint8_t T5C
Definition: tle987x.h:4934
__OM uint8_t CH4C
Definition: tle987x.h:4987
__IM uint8_t ERRSYN
Definition: tle987x.h:4418
__IOM uint8_t NMIOWD
Definition: tle987x.h:4023
__IOM uint8_t T13SUSP
Definition: tle987x.h:4593
__IOM uint8_t GPT12IE
Definition: tle987x.h:4831
__OM uint8_t RSBEC
Definition: tle987x.h:4797
__OM uint8_t NVMDBEC
Definition: tle987x.h:4795
__OM uint8_t CCU6SR0C
Definition: tle987x.h:5019
__IOM uint8_t RIEN1
Definition: tle987x.h:4081
__OM uint8_t SSC2C
Definition: tle987x.h:5006
__IM uint8_t PRODID
Definition: tle987x.h:4481
__OM uint8_t NMIOTC
Definition: tle987x.h:3903
__IOM uint8_t MONIE
Definition: tle987x.h:4112
__IOM uint8_t NVMPROTSTSL_3
Definition: tle987x.h:4679
__OM uint8_t CH2C
Definition: tle987x.h:4985
__IM uint8_t RAM_PROT_ERR
Definition: tle987x.h:4696
__IM uint8_t CCU6SR0
Definition: tle987x.h:3963
__IOM uint8_t NMIPLL
Definition: tle987x.h:4020
__IM uint8_t PROTECT_S
Definition: tle987x.h:4493
__IM uint8_t CH5
Definition: tle987x.h:4865
__IM uint8_t MONR
Definition: tle987x.h:3924
__IOM uint8_t CH7IE
Definition: tle987x.h:4814
__IOM uint8_t WDTREL
Definition: tle987x.h:4334
__IOM uint8_t ADC1_DIS
Definition: tle987x.h:4252
__IOM uint8_t PDM4
Definition: tle987x.h:4733
__IM uint8_t CH3
Definition: tle987x.h:4863
__IOM uint8_t RIREN1
Definition: tle987x.h:4079
__IOM uint8_t BGCLK_SEL
Definition: tle987x.h:4209
__IOM uint8_t T21EXIS
Definition: tle987x.h:4568
__IOM uint8_t NVMCLKFAC
Definition: tle987x.h:4309
__IOM uint8_t T3CLK_SEL
Definition: tle987x.h:4207
__IOM uint8_t NMINVM
Definition: tle987x.h:4021
__IOM uint8_t FD_SEL
Definition: tle987x.h:4391
__IM uint8_t EXINT2F
Definition: tle987x.h:3923
__IOM uint8_t SSCTXIE
Definition: tle987x.h:4829
__IOM uint8_t APCLK2FAC
Definition: tle987x.h:4239
__IOM uint8_t T6IE
Definition: tle987x.h:4901
__OM uint8_t SSCTXC
Definition: tle987x.h:5046
__IOM uint8_t T3CLK_DIV
Definition: tle987x.h:4297
__IOM uint8_t WDTEN
Definition: tle987x.h:4191
__OM uint8_t SSCRXC
Definition: tle987x.h:5047
__IOM uint8_t CH2IE
Definition: tle987x.h:4809
__IM uint8_t WDT
Definition: tle987x.h:4356
__IM uint8_t T4
Definition: tle987x.h:4916
__IOM uint8_t OSCTRIM_8
Definition: tle987x.h:4510
__IOM uint8_t GPT12_DIS
Definition: tle987x.h:4256
__IOM uint8_t XPD
Definition: tle987x.h:4508
__IOM uint8_t NMIOT
Definition: tle987x.h:4022
__IM uint8_t NVM_SFR_PROT_ERR
Definition: tle987x.h:4692
__IOM uint8_t BGCLK_DIV
Definition: tle987x.h:4210
__IOM uint8_t MON_Trig_Sel
Definition: tle987x.h:4040
__IOM uint8_t SYNEN
Definition: tle987x.h:4419
__IOM uint8_t GPT12_DMAEN
Definition: tle987x.h:4973
__IM uint8_t T3
Definition: tle987x.h:4915
__IM uint8_t NVM_PROT_ERR
Definition: tle987x.h:4690
__IOM uint8_t EXINT0
Definition: tle987x.h:4037
__IOM uint8_t SSCRXSRCSEL
Definition: tle987x.h:4844
__OM uint8_t CRC
Definition: tle987x.h:4936
__OM uint8_t EXINT2RC
Definition: tle987x.h:4059
__IOM uint8_t PG100TP_CHKS_ERR
Definition: tle987x.h:4323
__IOM uint8_t CH3IE
Definition: tle987x.h:4810
__IOM uint8_t TIREN2
Definition: tle987x.h:4094
__IOM uint8_t SDADCIE
Definition: tle987x.h:4832
__IM uint8_t SDADC
Definition: tle987x.h:4885
__IOM uint8_t GPT12
Definition: tle987x.h:4621
__IOM uint8_t NVMPROTSTSL_0
Definition: tle987x.h:4676
__IOM uint8_t CH4IE
Definition: tle987x.h:4811
__IM uint8_t STRDY
Definition: tle987x.h:4879
__IM uint8_t GPT12
Definition: tle987x.h:4884
__IM uint8_t ROM_ADDR_ERR
Definition: tle987x.h:4695
__IM uint8_t TRSEQ2DY
Definition: tle987x.h:4881
__IOM uint8_t T3_SUSP
Definition: tle987x.h:4608
__IOM uint8_t PDM2
Definition: tle987x.h:4720
__IOM uint8_t EXINT2_EN
Definition: tle987x.h:4097
__IM uint8_t SSCRX
Definition: tle987x.h:4849
__IM uint8_t CH4
Definition: tle987x.h:4864
__OM uint8_t ERRSYNC
Definition: tle987x.h:4469
__IM uint8_t FNMIPLL
Definition: tle987x.h:3990
__IM uint8_t TIR
Definition: tle987x.h:3938
__IOM uint8_t EXINT2
Definition: tle987x.h:4039
__IOM uint8_t reg
Definition: tle987x.h:3896
__IOM uint8_t GPT12_SUSP
Definition: tle987x.h:4595
__OM uint8_t NMISUPC
Definition: tle987x.h:3907
__IOM uint8_t EIREN2
Definition: tle987x.h:4093
__IM uint8_t FNMIMAP
Definition: tle987x.h:3994
__IOM uint8_t U_TX_CONDIS
Definition: tle987x.h:4540
__OM uint8_t CH7C
Definition: tle987x.h:4990
__IOM uint8_t SSC1_DIS
Definition: tle987x.h:4253
__IM uint8_t NVMDBE
Definition: tle987x.h:4651
__IOM uint8_t WDTIN
Definition: tle987x.h:4189
__IM uint8_t NVM_SFR_ADDR_ERR
Definition: tle987x.h:4693
__OM uint8_t T4C
Definition: tle987x.h:4933
__IOM uint8_t TRERRIE
Definition: tle987x.h:4826
__IOM uint8_t T2IE
Definition: tle987x.h:4897
__IM uint8_t RIR
Definition: tle987x.h:3939
__IOM uint8_t PASS
Definition: tle987x.h:4494
__IOM uint8_t T3_GPT12_SEL
Definition: tle987x.h:4623
__IOM uint8_t TIEN2
Definition: tle987x.h:4099
__IOM uint8_t URIOS2
Definition: tle987x.h:4580
__IM uint8_t WDTPR
Definition: tle987x.h:4193
System Control Unit for Power Modules (SCUPM)
Definition: tle987x.h:5065
__IM uint32_t PHU_ZCHI_STS
Definition: tle987x.h:5191
__IOM uint32_t SOWCONF
Definition: tle987x.h:5331
__IOM uint32_t PHV_ZCLOW_IE
Definition: tle987x.h:5294
__OM uint32_t HS3_OC_ICLR
Definition: tle987x.h:5357
__IOM uint32_t LS2_OC_IE
Definition: tle987x.h:5447
__IM uint32_t LIN_OT_IS
Definition: tle987x.h:5161
__IM uint32_t VDD5V_OV_STS
Definition: tle987x.h:5220
__IOM uint32_t PHU_ZCLOW_IE
Definition: tle987x.h:5292
__IM uint32_t PHU_ZCLOW_STS
Definition: tle987x.h:5190
__IM uint32_t VREF5V_UPTH_IS
Definition: tle987x.h:5178
__IM uint32_t PHW_ZCLOW_IS
Definition: tle987x.h:5186
__IM uint32_t ADC2_ESM_IS
Definition: tle987x.h:5181
__IOM uint32_t AMCLK2_UP_TH
Definition: tle987x.h:5101
__OM uint32_t VSD_UPTH_SCLR
Definition: tle987x.h:5377
__IM uint32_t LS3_DS_IS
Definition: tle987x.h:5395
__IM uint32_t VCP_LOWTH2_STS
Definition: tle987x.h:5416
__IM uint32_t VSD_LOWTH_IS
Definition: tle987x.h:5411
__IM uint32_t SYS_OTWARN_IS
Definition: tle987x.h:5168
__IOM uint32_t VREF5V_OVL_IE
Definition: tle987x.h:5290
__IM uint32_t PHW_ZCHI_STS
Definition: tle987x.h:5195
__IOM uint32_t HS3_DS_IE
Definition: tle987x.h:5443
__IOM uint32_t AMCLK2_LOW_TH
Definition: tle987x.h:5103
__IM uint32_t HS3_OC_IS
Definition: tle987x.h:5404
__IOM uint32_t HS2_OC_IE
Definition: tle987x.h:5449
__IM uint32_t PHV_ZCHI_STS
Definition: tle987x.h:5193
__OM uint32_t VCP_UPTH_ICLR
Definition: tle987x.h:5362
__OM uint32_t LIN_TMOUT_ICLR
Definition: tle987x.h:5117
__OM uint32_t VDD1V5_OV_ICLR
Definition: tle987x.h:5255
__OM uint32_t VSD_LOWTH_SCLR
Definition: tle987x.h:5375
__IOM uint32_t AMCLK1_UP_TH
Definition: tle987x.h:5097
__OM uint32_t HS3_DS_ICLR
Definition: tle987x.h:5349
__IOM uint32_t VS_UV_IE
Definition: tle987x.h:5232
__IM uint32_t PHV_ZCLOW_IS
Definition: tle987x.h:5184
__OM uint32_t MON_OV_ICLR
Definition: tle987x.h:5252
__IM uint32_t LS2_DS_IS
Definition: tle987x.h:5390
__IOM uint32_t VDD1V5_OV_IE
Definition: tle987x.h:5238
__IM uint32_t DBFSTS
Definition: tle987x.h:5478
__IOM uint32_t REFBG_LOTHWARN_IE
Definition: tle987x.h:5284
__IM uint32_t PHU_ZCHI_IS
Definition: tle987x.h:5183
__IM uint32_t VREF5V_OVL_IS
Definition: tle987x.h:5180
__IM uint32_t PHV_ZCHI_IS
Definition: tle987x.h:5185
__IOM uint32_t MON_UV_IE
Definition: tle987x.h:5231
__IM uint32_t LS1_OC_IS
Definition: tle987x.h:5399
__IOM uint32_t VCP_LOWTH1_IE
Definition: tle987x.h:5453
__IM uint32_t VS_UV_STS
Definition: tle987x.h:5215
__IM uint32_t MON_OV_IS
Definition: tle987x.h:5209
__IM uint32_t VDD1V5_UV_STS
Definition: tle987x.h:5217
__IM uint32_t HS1_OC_IS
Definition: tle987x.h:5401
__OM uint32_t REFBG_UPTHWARN_ICLR
Definition: tle987x.h:5129
__IOM uint32_t ADC3_EOC_IE
Definition: tle987x.h:5298
__OM uint32_t VCP_LOWTH1_SCLR
Definition: tle987x.h:5371
__IM uint32_t VDD1V5_OV_IS
Definition: tle987x.h:5212
__OM uint32_t VREF5V_LOWTH_ICLR
Definition: tle987x.h:5131
__IOM uint32_t LIN_OT_IE
Definition: tle987x.h:5275
__IOM uint32_t HS1_DS_IE
Definition: tle987x.h:5438
__OM uint32_t VS_OV_ICLR
Definition: tle987x.h:5253
__IM uint32_t HS3_DS_IS
Definition: tle987x.h:5396
__IOM uint32_t SYS_VSD_OV_SLM_DIS
Definition: tle987x.h:5316
__IOM uint32_t FAIL_PS_DIS
Definition: tle987x.h:5313
__OM uint32_t PHU_ZCLOW_SCLR
Definition: tle987x.h:5145
__IM uint32_t PHV_ZCLOW_STS
Definition: tle987x.h:5192
__OM uint32_t VCP_UPTH_SCLR
Definition: tle987x.h:5373
__OM uint32_t VDD5V_UV_ICLR
Definition: tle987x.h:5250
__IOM uint32_t LS3_OC_IE
Definition: tle987x.h:5450
__IM uint32_t HS2_DS_IS
Definition: tle987x.h:5393
__IOM uint32_t PMU_OTWARN_IE
Definition: tle987x.h:5278
__IOM uint32_t SYS_OT_IE
Definition: tle987x.h:5282
__IOM uint32_t VDD1V5_UV_IE
Definition: tle987x.h:5234
__IM uint32_t PHW_ZCHI_IS
Definition: tle987x.h:5187
__IOM uint32_t LIN_VS_UV_SD_DIS
Definition: tle987x.h:5314
__IM uint32_t AMCLK2_FREQ
Definition: tle987x.h:5076
__IM uint32_t PHU_ZCLOW_IS
Definition: tle987x.h:5182
__OM uint32_t LS3_DS_ICLR
Definition: tle987x.h:5348
__IM uint32_t AMCLK1_FREQ
Definition: tle987x.h:5073
__IOM uint32_t SYS_OT_PS_DIS
Definition: tle987x.h:5318
__OM uint32_t ADC3_EOC_ICLR
Definition: tle987x.h:5143
__IOM uint32_t AMCLK1_UP_HYS
Definition: tle987x.h:5098
__IM uint32_t
Definition: tle987x.h:5075
__OM uint32_t PHW_ZCLOW_SCLR
Definition: tle987x.h:5149
__IOM uint32_t AMCLK2_UP_HYS
Definition: tle987x.h:5102
__OM uint32_t VCP_LOWTH1_ICLR
Definition: tle987x.h:5360
__IOM uint32_t CLKLOSS_SD_DIS
Definition: tle987x.h:5319
__OM uint32_t ADC4_EOC_ICLR
Definition: tle987x.h:5144
__OM uint32_t VCP_LOWTH2_ICLR
Definition: tle987x.h:5358
__IOM uint32_t WDP_SEL
Definition: tle987x.h:5330
__IM uint32_t HS2_OC_IS
Definition: tle987x.h:5402
__IM uint32_t VS_UV_IS
Definition: tle987x.h:5206
__OM uint32_t PHV_ZCLOW_SCLR
Definition: tle987x.h:5147
__IOM uint32_t AMCLK1_LOW_TH
Definition: tle987x.h:5099
__IM uint32_t SBFSTS
Definition: tle987x.h:5479
__OM uint32_t VDD1V5_OV_SCLR
Definition: tle987x.h:5264
__IM uint32_t REFBG_UPTHWARN_IS
Definition: tle987x.h:5174
__IOM uint32_t CLKWDT_RES_SD_DIS
Definition: tle987x.h:5320
__IOM uint32_t LIN_OC_IE
Definition: tle987x.h:5274
__OM uint32_t MON_OV_SCLR
Definition: tle987x.h:5261
__IM uint32_t SYS_OT_IS
Definition: tle987x.h:5170
__IOM uint32_t VCP_UPTH_IE
Definition: tle987x.h:5454
__OM uint32_t VSD_LOWTH_ICLR
Definition: tle987x.h:5364
__IOM uint32_t LIN_TMOUT_IE
Definition: tle987x.h:5276
__IOM uint32_t LS1_DS_IE
Definition: tle987x.h:5436
__IOM uint32_t VSD_LOWTH_IE
Definition: tle987x.h:5455
__OM uint32_t PHV_ZCHI_ICLR
Definition: tle987x.h:5140
__OM uint32_t DBFSTSCLR
Definition: tle987x.h:5509
__IOM uint32_t MON_OV_IE
Definition: tle987x.h:5235
__IM uint32_t ADC4_EOC_IS
Definition: tle987x.h:5189
__IOM uint32_t AMCLK2_LOW_HYS
Definition: tle987x.h:5104
__IM uint32_t VREF5V_LOWTH_IS
Definition: tle987x.h:5176
__OM uint32_t PHW_ZCHI_ICLR
Definition: tle987x.h:5142
__OM uint32_t ADC2_ESM_ICLR
Definition: tle987x.h:5136
__OM uint32_t VDD5V_OV_ICLR
Definition: tle987x.h:5254
__IM uint32_t VCP_UPTH_STS
Definition: tle987x.h:5420
__IM uint32_t MON_UV_STS
Definition: tle987x.h:5214
__IM uint32_t DBFA
Definition: tle987x.h:5489
__IOM uint32_t STCALIB
Definition: tle987x.h:5467
__IOM uint32_t HS2_DS_IE
Definition: tle987x.h:5440
__OM uint32_t VS_UV_SCLR
Definition: tle987x.h:5258
__OM uint32_t PMU_OT_ICLR
Definition: tle987x.h:5121
__IOM uint32_t LS3_DS_IE
Definition: tle987x.h:5442
__OM uint32_t VREF5V_UPTH_ICLR
Definition: tle987x.h:5133
__IM uint32_t VS_OV_STS
Definition: tle987x.h:5219
__OM uint32_t PHU_ZCHI_SCLR
Definition: tle987x.h:5146
__IM uint32_t MON_OV_STS
Definition: tle987x.h:5218
__IM uint32_t LS3_OC_IS
Definition: tle987x.h:5403
__IM uint32_t VS_OV_IS
Definition: tle987x.h:5210
__IM uint32_t VCP_LOWTH1_IS
Definition: tle987x.h:5407
__IOM uint32_t VREF5V_UPTH_IE
Definition: tle987x.h:5288
__IM uint32_t PMU_OTWARN_IS
Definition: tle987x.h:5164
__OM uint32_t PHV_ZCHI_SCLR
Definition: tle987x.h:5148
__IOM uint32_t CLKWDT_SD_DIS
Definition: tle987x.h:5311
__IM uint32_t ADC3_EOC_IS
Definition: tle987x.h:5188
__IOM uint32_t PHU_ZCHI_IE
Definition: tle987x.h:5293
__OM uint32_t VS_OV_SCLR
Definition: tle987x.h:5262
__IOM uint32_t HS1_OC_IE
Definition: tle987x.h:5448
__OM uint32_t SYS_OTWARN_ICLR
Definition: tle987x.h:5123
__OM uint32_t PMU_OTWARN_ICLR
Definition: tle987x.h:5119
__OM uint32_t HS2_DS_ICLR
Definition: tle987x.h:5346
__OM uint32_t VDD5V_UV_SCLR
Definition: tle987x.h:5259
__OM uint32_t LS1_OC_ICLR
Definition: tle987x.h:5352
__IOM uint32_t VSD_UPTH_IE
Definition: tle987x.h:5456
__IM uint32_t RESERVED
Definition: tle987x.h:5089
__OM uint32_t HS1_DS_ICLR
Definition: tle987x.h:5344
__OM uint32_t HS1_OC_ICLR
Definition: tle987x.h:5354
__IM uint32_t SBFA
Definition: tle987x.h:5499
__OM uint32_t LIN_OC_ICLR
Definition: tle987x.h:5115
__OM uint32_t REFBG_LOTHWARN_ICLR
Definition: tle987x.h:5127
__OM uint32_t VSD_UPTH_ICLR
Definition: tle987x.h:5366
__IOM uint32_t VDD5V_OV_IE
Definition: tle987x.h:5237
__IOM uint32_t ADC2_ESM_IE
Definition: tle987x.h:5291
__IOM uint32_t reg
Definition: tle987x.h:5069
__IOM uint32_t VDD5V_UV_IE
Definition: tle987x.h:5233
__IM uint32_t HS1_DS_IS
Definition: tle987x.h:5391
__OM uint32_t PHW_ZCLOW_ICLR
Definition: tle987x.h:5141
__OM uint32_t PHV_ZCLOW_ICLR
Definition: tle987x.h:5139
__IOM uint32_t LS1_OC_IE
Definition: tle987x.h:5446
__OM uint32_t PHU_ZCLOW_ICLR
Definition: tle987x.h:5137
__OM uint32_t VREF5V_OVL_ICLR
Definition: tle987x.h:5135
__OM uint32_t VDD1V5_UV_ICLR
Definition: tle987x.h:5251
__IM uint32_t VSD_UPTH_STS
Definition: tle987x.h:5424
__IM uint32_t VSD_LOWTH_STS
Definition: tle987x.h:5422
__IM uint32_t LIN_TMOUT_IS
Definition: tle987x.h:5162
__IOM uint32_t PHW_ZCHI_IE
Definition: tle987x.h:5297
__IM uint32_t LIN_OC_IS
Definition: tle987x.h:5160
__OM uint32_t LS2_DS_ICLR
Definition: tle987x.h:5343
__IOM uint32_t HS3_OC_IE
Definition: tle987x.h:5451
__OM uint32_t LS3_OC_ICLR
Definition: tle987x.h:5356
__OM uint32_t VS_UV_ICLR
Definition: tle987x.h:5249
__IM uint32_t REFBG_LOTHWARN_IS
Definition: tle987x.h:5172
__IOM uint32_t PHV_ZCHI_IE
Definition: tle987x.h:5295
__IM uint32_t VDD5V_OV_IS
Definition: tle987x.h:5211
__IM uint32_t RESERVED2
Definition: tle987x.h:5302
__IM uint32_t LS1_DS_IS
Definition: tle987x.h:5389
__OM uint32_t SYS_OT_ICLR
Definition: tle987x.h:5125
__OM uint32_t LS2_OC_ICLR
Definition: tle987x.h:5353
__IOM uint32_t ADC4_EOC_IE
Definition: tle987x.h:5299
__IM uint32_t LS2_OC_IS
Definition: tle987x.h:5400
__OM uint32_t LS1_DS_ICLR
Definition: tle987x.h:5342
__IM uint32_t PMU_OT_IS
Definition: tle987x.h:5166
__IOM uint32_t VS_OV_IE
Definition: tle987x.h:5236
__OM uint32_t MON_UV_SCLR
Definition: tle987x.h:5257
__IM uint32_t VCP_LOWTH2_IS
Definition: tle987x.h:5405
__OM uint32_t PHU_ZCHI_ICLR
Definition: tle987x.h:5138
__IOM uint32_t LS2_DS_IE
Definition: tle987x.h:5437
__OM uint32_t VDD5V_OV_SCLR
Definition: tle987x.h:5263
__IOM uint32_t VREF5V_LOWTH_IE
Definition: tle987x.h:5286
__IM uint32_t PHW_ZCLOW_STS
Definition: tle987x.h:5194
__IM uint32_t RESERVED1
Definition: tle987x.h:5107
__OM uint32_t PHW_ZCHI_SCLR
Definition: tle987x.h:5150
__IOM uint32_t REFBG_UPTHWARN_IE
Definition: tle987x.h:5285
__OM uint32_t SBFSTSCLR
Definition: tle987x.h:5510
__IM uint32_t VCP_UPTH_IS
Definition: tle987x.h:5409
__OM uint32_t VCP_LOWTH2_SCLR
Definition: tle987x.h:5369
__IOM uint32_t AMCLK1_LOW_HYS
Definition: tle987x.h:5100
__OM uint32_t LIN_OT_ICLR
Definition: tle987x.h:5116
__OM uint32_t HS2_OC_ICLR
Definition: tle987x.h:5355
__OM uint32_t VDD1V5_UV_SCLR
Definition: tle987x.h:5260
__IM uint32_t VDD5V_UV_STS
Definition: tle987x.h:5216
__IM uint32_t MON_UV_IS
Definition: tle987x.h:5205
__OM uint32_t MON_UV_ICLR
Definition: tle987x.h:5248
__IM uint32_t VDD1V5_OV_STS
Definition: tle987x.h:5221
__IM uint32_t VDD5V_UV_IS
Definition: tle987x.h:5207
__IM uint32_t VSD_UPTH_IS
Definition: tle987x.h:5413
__IOM uint32_t SYS_OTWARN_IE
Definition: tle987x.h:5281
__IOM uint32_t PHW_ZCLOW_IE
Definition: tle987x.h:5296
__IOM uint32_t VCP_LOWTH2_IE
Definition: tle987x.h:5452
__IM uint32_t VDD1V5_UV_IS
Definition: tle987x.h:5208
__IM uint32_t VCP_LOWTH1_STS
Definition: tle987x.h:5418
__IOM uint32_t CLKWDT_PD_N
Definition: tle987x.h:5086
__IOM uint32_t PMU_OT_IE
Definition: tle987x.h:5279
SSC1 Module (SSC1)
Definition: tle987x.h:5527
__IM uint16_t TE
Definition: tle987x.h:5563
__IOM uint16_t BR_VALUE
Definition: tle987x.h:5603
__OM uint16_t PECLR
Definition: tle987x.h:5617
__IM uint16_t BSY
Definition: tle987x.h:5567
__OM uint16_t RECLR
Definition: tle987x.h:5616
__OM uint16_t BECLR
Definition: tle987x.h:5618
__IOM uint16_t MIS_0
Definition: tle987x.h:5535
__IM uint16_t RB_VALUE
Definition: tle987x.h:5592
__IM uint16_t RESERVED4
Definition: tle987x.h:5606
__IM uint16_t
Definition: tle987x.h:5562
__IOM uint16_t SIS
Definition: tle987x.h:5539
__IOM uint16_t reg
Definition: tle987x.h:5531
__IOM uint16_t MIS_1
Definition: tle987x.h:5549
__OM uint16_t TECLR
Definition: tle987x.h:5615
__IOM uint16_t TB_VALUE
Definition: tle987x.h:5581
__IM uint16_t PE
Definition: tle987x.h:5565
__IOM uint16_t CIS
Definition: tle987x.h:5544
__IM uint16_t BC
Definition: tle987x.h:5561
__IM uint16_t RE
Definition: tle987x.h:5564
__IOM uint16_t EN
Definition: tle987x.h:5570
__IM uint16_t RESERVED1
Definition: tle987x.h:5573
__IM uint16_t BE
Definition: tle987x.h:5566
__IM uint16_t RESERVED3
Definition: tle987x.h:5595
__IM uint16_t RESERVED
Definition: tle987x.h:5553
__IM uint16_t RESERVED2
Definition: tle987x.h:5584
__IOM uint16_t MS
Definition: tle987x.h:5569
SSC2 Module (SSC2)
Definition: tle987x.h:5635
__IM uint16_t TE
Definition: tle987x.h:5671
__IOM uint16_t BR_VALUE
Definition: tle987x.h:5711
__OM uint16_t PECLR
Definition: tle987x.h:5725
__IM uint16_t BSY
Definition: tle987x.h:5675
__OM uint16_t RECLR
Definition: tle987x.h:5724
__OM uint16_t BECLR
Definition: tle987x.h:5726
__IOM uint16_t MIS_0
Definition: tle987x.h:5643
__IM uint16_t RB_VALUE
Definition: tle987x.h:5700
__IM uint16_t RESERVED4
Definition: tle987x.h:5714
__IM uint16_t
Definition: tle987x.h:5670
__IOM uint16_t SIS
Definition: tle987x.h:5647
__IOM uint16_t reg
Definition: tle987x.h:5639
__IOM uint16_t MIS_1
Definition: tle987x.h:5657
__OM uint16_t TECLR
Definition: tle987x.h:5723
__IOM uint16_t TB_VALUE
Definition: tle987x.h:5689
__IM uint16_t PE
Definition: tle987x.h:5673
__IOM uint16_t CIS
Definition: tle987x.h:5652
__IM uint16_t BC
Definition: tle987x.h:5669
__IM uint16_t RE
Definition: tle987x.h:5672
__IOM uint16_t EN
Definition: tle987x.h:5678
__IM uint16_t RESERVED1
Definition: tle987x.h:5681
__IM uint16_t BE
Definition: tle987x.h:5674
__IM uint16_t RESERVED3
Definition: tle987x.h:5703
__IM uint16_t RESERVED
Definition: tle987x.h:5661
__IM uint16_t RESERVED2
Definition: tle987x.h:5692
__IOM uint16_t MS
Definition: tle987x.h:5677
TIMER2x Module (TIMER2x)
Definition: tle987x.h:5743
__IOM uint8_t EXF2EN
Definition: tle987x.h:5828
__IOM uint8_t PREN
Definition: tle987x.h:5770
__IOM uint8_t CP_RL2
Definition: tle987x.h:5751
__IOM uint8_t TR2
Definition: tle987x.h:5753
__IM uint8_t
Definition: tle987x.h:5755
__IOM uint8_t EXEN2
Definition: tle987x.h:5754
__IOM uint8_t T2REGS
Definition: tle987x.h:5773
__IOM uint8_t RC2
Definition: tle987x.h:5784
__IOM uint8_t DCEN
Definition: tle987x.h:5768
__IM uint8_t TF2
Definition: tle987x.h:5757
__IOM uint8_t T2L
Definition: tle987x.h:5806
__IM uint8_t EXF2
Definition: tle987x.h:5756
__IOM uint8_t TF2EN
Definition: tle987x.h:5829
__IOM uint8_t EDGESEL
Definition: tle987x.h:5771
__OM uint8_t EXF2CLR
Definition: tle987x.h:5841
__IOM uint8_t T2H
Definition: tle987x.h:5817
__IOM uint8_t T2PRE
Definition: tle987x.h:5769
__OM uint8_t TF2CLR
Definition: tle987x.h:5842
__IOM uint8_t T2RHEN
Definition: tle987x.h:5772
__IOM uint8_t reg
Definition: tle987x.h:5747
__IOM uint8_t C_T2
Definition: tle987x.h:5752
TIMER3 Module (TIMER3)
Definition: tle987x.h:5859
__IOM uint32_t T3_RD_REQ
Definition: tle987x.h:5904
__IOM uint32_t TR3H
Definition: tle987x.h:5907
__IOM uint32_t T3_RD_REQ_CONF
Definition: tle987x.h:5905
__IOM uint32_t T3_PD_N
Definition: tle987x.h:5903
__IM uint32_t T3H_OVF_STS
Definition: tle987x.h:5908
__IOM uint32_t T3_RES_CONF
Definition: tle987x.h:5869
__IOM uint32_t T3H_OVF_IE
Definition: tle987x.h:5912
__IOM uint32_t RETRIG
Definition: tle987x.h:5870
__IM uint32_t
Definition: tle987x.h:5868
__IOM uint32_t CNT_RDY
Definition: tle987x.h:5906
__IOM uint32_t T3_SUBM
Definition: tle987x.h:5924
__IOM uint32_t LO
Definition: tle987x.h:5881
__IM uint32_t T3L_OVF_STS
Definition: tle987x.h:5910
__IOM uint32_t TR3L
Definition: tle987x.h:5909
__IOM uint32_t reg
Definition: tle987x.h:5863
__IOM uint32_t T3L_OVF_IE
Definition: tle987x.h:5911
__IOM uint32_t HI
Definition: tle987x.h:5882
__IOM uint32_t T3_TRIGG_INP_SEL
Definition: tle987x.h:5867
__OM uint32_t T3L_OVF_ICLR
Definition: tle987x.h:5937
__OM uint32_t T3H_OVF_ICLR
Definition: tle987x.h:5935
__IOM uint32_t T3M
Definition: tle987x.h:5922
UARTx Module (UARTx)
Definition: tle987x.h:5954
__OM uint8_t TICLR
Definition: tle987x.h:5993
__IOM uint8_t TI
Definition: tle987x.h:5963
__IOM uint8_t REN
Definition: tle987x.h:5966
__IOM uint8_t SM0
Definition: tle987x.h:5970
__IOM uint8_t SM2
Definition: tle987x.h:5967
__IOM uint8_t SM1
Definition: tle987x.h:5969
__IOM uint8_t RI
Definition: tle987x.h:5962
__IOM uint8_t TB8
Definition: tle987x.h:5965
__IOM uint8_t RB8
Definition: tle987x.h:5964
__OM uint8_t RICLR
Definition: tle987x.h:5992
__IOM uint8_t VAL
Definition: tle987x.h:5981
__IOM uint8_t reg
Definition: tle987x.h:5958