Infineon MOTIX™ MCU TLE987x Device Family SDK
Data Fields
TIMER3_Type Struct Reference

Detailed Description

TIMER3 Module (TIMER3)

#include <tle987x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T3_TRIGG_INP_SEL: 3
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   T3_RES_CONF: 2
 
      __IOM uint32_t   RETRIG: 1
 
   }   bit
 
T3_TRIGG_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LO: 8
 
      __IOM uint32_t   HI: 8
 
   }   bit
 
CMP
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LO: 8
 
      __IOM uint32_t   HI: 8
 
   }   bit
 
CNT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T3_PD_N: 1
 
      __IOM uint32_t   T3_RD_REQ: 1
 
      __IOM uint32_t   T3_RD_REQ_CONF: 1
 
      __IOM uint32_t   CNT_RDY: 1
 
      __IOM uint32_t   TR3H: 1
 
      __IM uint32_t   T3H_OVF_STS: 1
 
      __IOM uint32_t   TR3L: 1
 
      __IM uint32_t   T3L_OVF_STS: 1
 
      __IOM uint32_t   T3L_OVF_IE: 1
 
      __IOM uint32_t   T3H_OVF_IE: 1
 
   }   bit
 
CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T3M: 2
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   T3_SUBM: 2
 
   }   bit
 
MODE_CONF
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 5
 
      __OM uint32_t   T3H_OVF_ICLR: 1
 
      __OM uint32_t   T3L_OVF_ICLR: 1
 
   }   bit
 
ISRCLR
 

Field Documentation

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struct { ... } bit

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union { ... } CMP

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union { ... } CNT

◆ CNT_RDY

__IOM uint32_t CNT_RDY

[3..3] Timer 3 Count Ready

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union { ... } CTRL

◆ HI

[15..8] Timer 3 Compare Value High Byte

[15..8] Timer 3 High Register or Preload Value

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union { ... } ISRCLR

◆ LO

[7..0] Timer 3 Compare Value Low Byte

[7..0] Timer 3 Low Register or Preload Value

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union { ... } MODE_CONF

◆ reg

(@ 0x00000000) T3 Trigger Control

(@ 0x00000004) Timer 3 Compare Value

(@ 0x00000008) Timer 3

(@ 0x0000000C) Timer 3 Control Register

(@ 0x00000010) Timer 3 Mode Configuration Register

(@ 0x00000014) Timer 3 Interrupt Status Clear Register

◆ RETRIG

__IOM uint32_t RETRIG

[6..6] Retrigger Condition (in mode 1b) for CCU6-T12 ZM and CCU6 PM

◆ T3_PD_N

__IOM uint32_t T3_PD_N

[0..0] Timer 3 Power Down

◆ T3_RD_REQ

__IOM uint32_t T3_RD_REQ

[1..1] Timer 3 Value Read Request

◆ T3_RD_REQ_CONF

__IOM uint32_t T3_RD_REQ_CONF

[2..2] Timer 3 Read Mode

◆ T3_RES_CONF

__IOM uint32_t T3_RES_CONF

[5..4] Timer 3 Trigger Reset Selection for Mode 1b

◆ T3_SUBM

__IOM uint32_t T3_SUBM

[7..6] Sub-Mode Select Bits

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union { ... } T3_TRIGG_CTRL

◆ T3_TRIGG_INP_SEL

__IOM uint32_t T3_TRIGG_INP_SEL

[2..0] Timer 3 Trigger Input Event Selection (only in mode3b)

◆ T3H_OVF_ICLR

__OM uint32_t T3H_OVF_ICLR

[5..5] Timer 3 Overflow Flag (High Byte Timer) Interrupt Clear

◆ T3H_OVF_IE

__IOM uint32_t T3H_OVF_IE

[9..9] Timer 3 Overflow Interrupt Enable (High Byte Timer)

◆ T3H_OVF_STS

__IM uint32_t T3H_OVF_STS

[5..5] Timer 3 Overflow Flag (High Byte Timer)

◆ T3L_OVF_ICLR

__OM uint32_t T3L_OVF_ICLR

[7..7] Timer 3 Overflow Flag (Low Byte Timer) Interrupt Clear

◆ T3L_OVF_IE

__IOM uint32_t T3L_OVF_IE

[8..8] Timer 3 Overflow Interrupt Enable (Low Byte Timer)

◆ T3L_OVF_STS

__IM uint32_t T3L_OVF_STS

[7..7] Timer 3 Overflow Flag (Low Byte Timer)

◆ T3M

[1..0] Mode Select Bits

◆ TR3H

[4..4] Timer 3 Run Control (High Byte Timer)

◆ TR3L

[6..6] Timer 3 Run Control (Low Byte Timer)

◆ uint32_t

__IM uint32_t

The documentation for this struct was generated from the following file: