Infineon MOTIX™ MCU TLE987x Device Family SDK
adc1.h
Go to the documentation of this file.
1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
22 /*******************************************************************************
23 ** Author(s) Identity **
24 ********************************************************************************
25 ** Initials Name **
26 ** ---------------------------------------------------------------------------**
27 ** DM Daniel Mysliwitz **
28 ** DCM Dragos C. Molocea **
29 ** BG Blandine Guillot **
30 ** JO Julia Ott **
31 ** VO Vanessa Ongaro **
32 *******************************************************************************/
33 
34 /*******************************************************************************
35 ** Revision Control History **
36 ********************************************************************************
37 ** V0.1.1: 2015-02-10, DM: Individual header file added **
38 ** V0.1.2: 2015-03-10, DM: MF->REF2_CTRL added **
39 ** V0.1.3: 2015-03-22, DM: ADC Busy function added **
40 ** V0.1.4: 2015-11-26, DM: VAREF enable function added **
41 ** V0.1.5: 2017-02-16, DM: the attenuator for Channel 6 (VDH) voltage **
42 ** calculation added **
43 ** Adc1 prefix changed to ADC1 **
44 ** V0.1.6: 2017-03-23, DM: ADC1 API extended **
45 ** V0.1.7: 2017-11-09, DM: Port2 analog input init added **
46 ** V0.1.8: 2017-11-13, DM: MISRA 2012 compliance, the following PC-Lint **
47 ** rules are globally deactivated: **
48 ** - Info 793: ANSI/ISO limit of 6 'significant **
49 ** characters in an external identifier **
50 ** - Info 835: A zero has been given as right **
51 ** argument to operator **
52 ** - Info 845: The left argument to operator '&' **
53 ** is certain to be 0 **
54 ** Replaced macros by INLINE functions **
55 ** Replaced register accesses within functions by **
56 ** function calls **
57 ** Replaced __STATIC_INLINE by INLINE **
58 ** V0.1.9: 2018-03-14, DM: VAREF_Enable() reworked for MISRA 2012 **
59 ** ADC1_MASK_CHx macros rworked for MISRA 2012 **
60 ** ADC1_ANON_Sts() converted to infline function **
61 ** due to MISRA 2012 **
62 ** V0.2.0: 2018-06-27, DCM: Conversion formula from digital value to **
63 ** millivolts changed based on the software unit **
64 ** test findings and simplified according to the **
65 ** new specifications **
66 ** V0.2.1: 2018-07-05, BG: In adc1.h: ADC1_Chx_Result_Get(), **
67 ** ADC1_EIM_Channel_Set(uint32), **
68 ** ADC1_SW_Ch_Sel(uint32), ADC1_SOC_Set(), **
69 ** ADC1_ANON_Set(uint32), ADC1_Power_On(), **
70 ** ADC1_EOC_Sts(), ADC1_Busy_Sts(), **
71 ** ADC1_EIM_Active_Sts(), ADC1_ESM_Active_Sts() **
72 ** reworked for testing lv2 functions **
73 ** V0.2.2: 2018-08-01, DM: DoxyGen comments updated, **
74 ** V0.2.3: 2018-11-09, JO: Renamed: **
75 ** - ADC1_VDH_Attenuator_Range_0_22V_Set to **
76 ** ADC1_VDH_Attenuator_Range_0_20V_Set **
77 ** - ADC1_VDH_Attenuator_Range_0_28V_Set to **
78 ** ADC1_VDH_Attenuator_Range_0_30V_Set **
79 ** - ADC1_VDH_Attenuator_Range_0_22V to **
80 ** ADC1_VDH_Attenuator_Range_0_20V **
81 ** - ADC1_VDH_Attenuator_Range_0_28V to **
82 ** ADC1_VDH_Attenuator_Range_0_30V **
83 ** V0.2.4: 2018-11-27, JO: Moved revision history from adc1.c to adc1.h **
84 ** V0.2.5: 2020-04-15, BG: Updated revision history format **
85 ** V0.2.6: 2020-07-13, JO: EP-431: remove ARMCC v6 Compiler warnings **
86 ** - Added typecasts to remove 'implicit typecast' **
87 ** warning **
88 ** V0.2.7: 2020-07-21, BG: EP-439: Formatted .h/.c files **
89 ** V0.2.8: 2021-04-23, BG: EP-726: Corrected MISRA 2012 violations **
90 ** V0.2.9: 2022-02-28, JO: EP-936: Updated copyright and branding **
91 ** V0.3.0: 2022-10-18, VO: EP-1252: Updated enum and union definitions **
92 ** V0.3.1: 2025-01-02, JO: EP-1493: Updated license **
93 *******************************************************************************/
94 
95 #ifndef ADC1_H
96 #define ADC1_H
97 
98 /*******************************************************************************
99 ** Includes **
100 *******************************************************************************/
101 #include "tle987x.h"
102 #include "types.h"
103 #include "adc1_defines.h"
104 #include "sfr_access.h"
105 
106 /*******************************************************************************
107 ** Global Constant Declarations **
108 *******************************************************************************/
109 
111 #define ADC1_VDH_Attenuator_Range_0_30V (1u)
113 #define ADC1_VDH_Attenuator_Range_0_20V (0u)
114 
116 #define SW_MODE 0u
118 #define SEQ_MODE 1u
119 
121 #define SKIP 0u
123 #define MEAS 1u
124 
126 #define BIT10 0u
128 #define BIT8 1u
129 
131 #define INTDIS 0u
133 #define INTEN 1u
134 
136 #define OVERWRITE 0u
138 #define WFR 1u
139 
141 #define ADC1_CH0 (0)
143 #define ADC1_CH1 (1)
145 #define ADC1_CH2 (2)
147 #define ADC1_CH3 (3)
149 #define ADC1_CH4 (4)
151 #define ADC1_CH5 (5)
153 #define ADC1_CH6 (6)
155 #define ADC1_EIM (8)
156 
158 #define ADC1_P20 ADC1_CH0
160 #define ADC1_CSA ADC1_CH1
162 #define ADC1_P22 ADC1_CH2
164 #define ADC1_P23 ADC1_CH3
166 #define ADC1_P24 ADC1_CH4
168 #define ADC1_P25 ADC1_CH5
170 #define ADC1_VDH ADC1_CH6
171 
172 /* ESM Channel */
174 #define ADC1_MASK_CH0 ((uint32)1u << ADC1_CH0)
176 #define ADC1_MASK_CH1 ((uint32)1u << ADC1_CH1)
178 #define ADC1_MASK_CH2 ((uint32)1u << ADC1_CH2)
180 #define ADC1_MASK_CH3 ((uint32)1u << ADC1_CH3)
182 #define ADC1_MASK_CH4 ((uint32)1u << ADC1_CH4)
184 #define ADC1_MASK_CH5 ((uint32)1u << ADC1_CH5)
186 #define ADC1_MASK_CH6 ((uint32)1u << ADC1_CH6)
187 
189 #define ADC1_MASK_P20 (ADC1_MASK_CH0)
191 #define ADC1_MASK_CSA (ADC1_MASK_CH1)
193 #define ADC1_MASK_P22 (ADC1_MASK_CH2)
195 #define ADC1_MASK_P23 (ADC1_MASK_CH3)
197 #define ADC1_MASK_P24 (ADC1_MASK_CH4)
199 #define ADC1_MASK_P25 (ADC1_MASK_CH5)
201 #define ADC1_MASK_VDH (ADC1_MASK_CH6)
202 
204 #define ADC1_VREF_5000mV 5000u
206 #define ADC1_VREF_22000mV 22000u
208 #define ADC1_VREF_30000mV 30000u
209 
210 /*******************************************************************************
211 ** ADC1 Analog Module select enum **
212 *******************************************************************************/
216 typedef enum ADC1_ANON
217 {
221  ADC1_ANON_NORMAL = 3
223 
224 typedef union ADC1_ANON_U
225 {
229 
230 /*******************************************************************************
231 ** ADC1 trigger select enum **
232 *******************************************************************************/
236 typedef enum ADC1_TRIGG_SEL
237 {
244  ADC1_Trigg_Timer3 = 6
246 
247 /*******************************************************************************
248 ** ADC1 EIM repeat count enum **
249 *******************************************************************************/
254 typedef enum ADC1_EIM_REP_CNT
255 {
263  ADC1_128_Meas = 7
265 
266 /*******************************************************************************
267 ** Global Function Declarations **
268 *******************************************************************************/
269 
270 /******************************************************************************/
275 void ADC1_Init(void);
276 
277 
298 bool VAREF_Enable(void);
299 
300 
332 bool ADC1_GetChResult(uint16 *pVar, uint8 channel);
333 
334 
365 bool ADC1_GetChResult_mV(uint16 *pVar_mV, uint8 channel);
366 
367 
399 
400 
432 
433 
463 INLINE void ADC1_SetEIMChannel(uint8 channel);
464 
465 
481 INLINE void ADC1_SetSwMode_Channel(uint8 channel);
482 
483 
501 INLINE void ADC1_SetMode(uint8 mode);
502 
503 
522 
523 
546 INLINE bool ADC1_GetEocSwMode(void);
547 
548 
580 
581 
612 INLINE bool ADC1_GetSwModeResult_mV(uint16 *pVar_mV);
613 
614 
642 INLINE bool ADC1_Busy(void);
643 
644 
663 
664 
683 
684 
703 
704 
727 INLINE bool ADC1_isEndOfConversion(void);
728 
729 
753 INLINE bool ADC1_isEIMactive(void);
754 
755 
779 INLINE bool ADC1_isESMactive(void);
780 
781 
800 
801 
802 /*******************************************************************************
803 ** Global Inline Function Definitions **
804 *******************************************************************************/
818 {
820 }
821 
835 {
837 }
838 
852 {
854 }
855 
872 {
874 }
875 
892 {
894 }
895 
911 {
913 }
914 
932 {
934 }
935 
955 {
957 }
958 
982 {
983  return ( u1_Field_Rd32(&ADC1->CTRL_STS.reg, ADC1_CTRL_STS_EOC_Pos, ADC1_CTRL_STS_EOC_Msk) );
984 }
985 
1012 {
1013  return ( u8_Field_Rd32(&ADC1->GLOBSTR.reg, ADC1_GLOBSTR_CHNR_Pos, ADC1_GLOBSTR_CHNR_Msk) );
1014 }
1015 
1045 {
1047 }
1048 
1077 {
1078  return ( u1_Field_Rd32(&ADC1->GLOBSTR.reg, ADC1_GLOBSTR_BUSY_Pos, ADC1_GLOBSTR_BUSY_Msk) );
1079 }
1080 
1103 {
1105 }
1106 
1129 {
1131 }
1132 
1153 {
1154  return ( u8_Field_Rd32(&ADC1->SQ_FB.reg, ADC1_SQ_FB_SQx_Pos, ADC1_SQ_FB_SQx_Msk) );
1155 }
1156 
1177 {
1178  return ( u8_Field_Rd32(&ADC1->SQ_FB.reg, ADC1_SQ_FB_CHx_Pos, ADC1_SQ_FB_CHx_Msk) );
1179 }
1180 
1199 {
1200  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ1_Pos, ADC1_SQ1_4_SQ1_Msk, (mask_ch));
1201 }
1202 
1222 {
1223  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ2_Pos, ADC1_SQ1_4_SQ2_Msk, (mask_ch));
1224 }
1225 
1245 {
1246  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ3_Pos, ADC1_SQ1_4_SQ3_Msk, (mask_ch));
1247 }
1248 
1268 {
1269  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ4_Pos, ADC1_SQ1_4_SQ4_Msk, (mask_ch));
1270 }
1271 
1291 {
1292  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ5_Pos, ADC1_SQ5_8_SQ5_Msk, (mask_ch));
1293 }
1294 
1314 {
1315  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ6_Pos, ADC1_SQ5_8_SQ6_Msk, (mask_ch));
1316 }
1317 
1337 {
1338  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ7_Pos, ADC1_SQ5_8_SQ7_Msk, (mask_ch));
1339 }
1340 
1360 {
1361  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ8_Pos, ADC1_SQ5_8_SQ8_Msk, (mask_ch));
1362 }
1363 
1390 {
1392 }
1393 
1420 {
1422 }
1423 
1450 {
1452 }
1453 
1480 {
1482 }
1483 
1510 {
1512 }
1513 
1540 {
1542 }
1543 
1570 {
1572 }
1573 
1601 {
1603 }
1604 
1631 {
1632  return ( ADC1_Ch0_Result_Get() );
1633 }
1634 
1661 {
1662  return ( ADC1_Ch1_Result_Get() );
1663 }
1664 
1691 {
1692  return ( ADC1_Ch2_Result_Get() );
1693 }
1694 
1721 {
1722  return ( ADC1_Ch3_Result_Get() );
1723 }
1724 
1751 {
1752  return ( ADC1_Ch4_Result_Get() );
1753 }
1754 
1781 {
1782  return ( ADC1_Ch5_Result_Get() );
1783 }
1784 
1811 {
1812  return ( ADC1_Ch6_Result_Get() );
1813 }
1814 
1843 {
1844  return ( u1_Field_Rd32(&ADC1->RES_OUT0.reg, ADC1_RES_OUT0_VF0_Pos, ADC1_RES_OUT0_VF0_Msk) );
1845 }
1846 
1875 {
1876  return ( u1_Field_Rd32(&ADC1->RES_OUT1.reg, ADC1_RES_OUT1_VF1_Pos, ADC1_RES_OUT1_VF1_Msk) );
1877 }
1878 
1907 {
1908  return ( u1_Field_Rd32(&ADC1->RES_OUT2.reg, ADC1_RES_OUT2_VF2_Pos, ADC1_RES_OUT2_VF2_Msk) );
1909 }
1910 
1939 {
1940  return ( u1_Field_Rd32(&ADC1->RES_OUT3.reg, ADC1_RES_OUT3_VF3_Pos, ADC1_RES_OUT3_VF3_Msk) );
1941 }
1942 
1971 {
1972  return ( u1_Field_Rd32(&ADC1->RES_OUT4.reg, ADC1_RES_OUT4_VF4_Pos, ADC1_RES_OUT4_VF4_Msk) );
1973 }
1974 
2003 {
2004  return ( u1_Field_Rd32(&ADC1->RES_OUT5.reg, ADC1_RES_OUT5_VF5_Pos, ADC1_RES_OUT5_VF5_Msk) );
2005 }
2006 
2035 {
2036  return ( u1_Field_Rd32(&ADC1->RES_OUT6.reg, ADC1_RES_OUT6_VF6_Pos, ADC1_RES_OUT6_VF6_Msk) );
2037 }
2038 
2068 {
2069  return ( u1_Field_Rd32(&ADC1->RES_OUT_EIM.reg, ADC1_RES_OUT_EIM_VF8_Pos, ADC1_RES_OUT_EIM_VF8_Msk) );
2070 }
2071 
2094 {
2096 }
2097 
2120 {
2122 }
2123 
2146 {
2148 }
2149 
2172 {
2174 }
2175 
2198 {
2200 }
2201 
2224 {
2226 }
2227 
2250 {
2252 }
2253 
2276 {
2278 }
2279 
2302 {
2304 }
2305 
2328 {
2330 }
2331 
2354 {
2356 }
2357 
2380 {
2382 }
2383 
2406 {
2408 }
2409 
2432 {
2434 }
2435 
2461 {
2463 }
2464 
2490 {
2492 }
2493 
2519 {
2521 }
2522 
2548 {
2550 }
2551 
2577 {
2579 }
2580 
2606 {
2608 }
2609 
2635 {
2637 }
2638 
2665 {
2667 }
2668 
2695 {
2697 }
2698 
2725 {
2727 }
2728 
2755 {
2757 }
2758 
2785 {
2787 }
2788 
2815 {
2817 }
2818 
2845 {
2847 }
2848 
2875 {
2877 }
2878 
2905 {
2907 }
2908 
2935 {
2937 }
2938 
2965 {
2967 }
2968 
2995 {
2997 }
2998 
3025 {
3027 }
3028 
3055 {
3057 }
3058 
3086 {
3088 }
3089 
3117 {
3118  Field_Mod32(&ADC1->CHx_ESM.reg, ADC1_CHx_ESM_ESM_0_Pos, ADC1_CHx_ESM_ESM_0_Msk, (mask_ch));
3119 }
3120 
3153 {
3155 }
3156 
3188 {
3190 }
3191 
3224 {
3226 }
3227 
3260 {
3262 }
3263 
3282 {
3284 }
3285 
3304 {
3306 }
3307 
3326 {
3328 }
3329 
3348 {
3350 }
3351 
3370 {
3372 }
3373 
3391 {
3393 }
3394 
3413 {
3415 }
3416 
3436 {
3438 }
3439 
3458 {
3460 }
3461 
3480 {
3482 }
3483 
3503 {
3505 }
3506 
3525 {
3527 }
3528 
3548 {
3550 }
3551 
3570 {
3572 }
3573 
3593 {
3595 }
3596 
3615 {
3617 }
3618 
3638 {
3640 }
3641 
3660 {
3662 }
3663 
3683 {
3685 }
3686 
3705 {
3707 }
3708 
3728 {
3730 }
3731 
3750 {
3752 }
3753 
3773 {
3775 }
3776 
3796 {
3798 }
3799 
3820 {
3822 }
3823 
3842 {
3844 }
3845 
3865 {
3867 }
3868 
3890 {
3892 }
3914 {
3916 }
3917 
3918 
3943 {
3945 }
3946 
3947 /*******************************************************************************
3948 ** Global Inline Function Definitions **
3949 *******************************************************************************/
3951 {
3952  ADC1_EIM_Channel_Set(channel);
3953 } /* End of ADC1_SetEIMChannel */
3954 
3956 {
3957  ADC1_SW_Ch_Sel(channel);
3958 } /* End of ADC1_SetSwMode_Channel */
3959 
3961 {
3962  /* Set the "mode" input to ADC1->SQ_FB.bit.SQ_RUN */
3964 } /* End of ADC1_SetMode */
3965 
3967 {
3968  ADC1_SW_Ch_Sel(Ch);
3969  ADC1_SOC_Set();
3970 } /* End of ADC1_SetSocSwMode */
3971 
3973 {
3974  bool res = false;
3975 
3976  if (ADC1_EOC_Sts() == (uint8)1)
3977  {
3978  res = true;
3979  }
3980 
3981  return (res);
3982 } /* End of ADC1_GetEocSwMode */
3983 
3985 {
3986  uint8 channel;
3988  return (ADC1_GetChResult(pVar, channel));
3989 } /* End of ADC1_GetSwModeResult */
3990 
3992 {
3993  uint8 channel;
3995  return (ADC1_GetChResult_mV(pVar_mV, channel));
3996 } /* End of ADC1_GetSwModeResult */
3997 
3998 INLINE bool ADC1_Busy(void)
3999 {
4000  bool res = false;
4001 
4002  if (ADC1_Busy_Sts() == (uint8)1)
4003  {
4004  res = true;
4005  }
4006 
4007  return (res);
4008 } /* End of ADC1_GetSwModeResult */
4009 
4011 {
4012  /* Set the "trigsel" input to ADC1->CHx_EIM.bit.TRIG_SEL */
4014 }
4015 
4017 {
4018  /* Set the "repcnt" input to ADC1->CHx_EIM.bit.REP */
4020 }
4021 
4023 {
4024  /* Set the "trigsel" input to ADC1->CHx_ESM.bit.TRIG_SEL */
4026 }
4027 
4029 {
4030  bool res = false;
4031 
4032  if (ADC1_EOC_Sts() == (uint8)1)
4033  {
4034  res = true;
4035  }
4036 
4037  return (res);
4038 }
4039 
4041 {
4042  bool res = false;
4043 
4044  if (ADC1_EIM_Active_Sts() == (uint8)1)
4045  {
4046  res = true;
4047  }
4048 
4049  return (res);
4050 }
4051 
4053 {
4054  bool res = false;
4055 
4056  if (ADC1_ESM_Active_Sts() == (uint8)1)
4057  {
4058  res = true;
4059  }
4060 
4061  return (res);
4062 }
4063 
4065 {
4066  TADC1_ANON_U res;
4068  return (res.adc1_anon);
4069 }
4070 
4071 #endif /* ADC1_H */
INLINE uint16 ADC1_P22_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1690
INLINE void ADC1_Ch6_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 6 number of sampling ticks.
Definition: adc1.h:2634
INLINE void ADC1_Sequence4_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 4, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1290
INLINE bool ADC1_isEIMactive(void)
checks Exceptional Interrupt Mode active
Definition: adc1.h:4040
INLINE uint16 ADC1_Ch5_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1539
INLINE uint8 ADC1_Ch3_ResultValid_Get(void)
Reads the valid flag for the channel 3 (P2.3) result.
Definition: adc1.h:1938
INLINE uint16 ADC1_VDH_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1810
INLINE void ADC1_Ch4_Int_Clr(void)
clears ADC1 Channel 4 Interrupt flag.
Definition: adc1.h:3369
INLINE void ADC1_Sequence7_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 7, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1359
INLINE void ADC1_Power_On(void)
Enables the ADC1 module.
Definition: adc1.h:817
INLINE uint16 ADC1_Ch4_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1509
INLINE uint16 ADC1_P23_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1720
INLINE void ADC1_Ch3_WaitForRead_Set(void)
Sets the ADC1 channel 3 result register to "wait for read".
Definition: adc1.h:2844
INLINE void ADC1_Ch1_Overwrite_Set(void)
Sets the ADC1 channel 1 result register to "overwrite".
Definition: adc1.h:2754
INLINE uint8 ADC1_EIM_Active_Sts(void)
Reads the active status of the Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:1102
INLINE uint16 ADC1_P25_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1780
INLINE void ADC1_EIM_Int_Dis(void)
disables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3819
INLINE void ADC1_Ch2_WaitForRead_Set(void)
Sets the ADC1 channel 2 result register to "wait for read".
Definition: adc1.h:2784
INLINE uint16 ADC1_P24_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1750
INLINE void ADC1_SetMode(uint8 mode)
Start ADC1 conversion mode selection.
Definition: adc1.h:3960
INLINE void ADC1_Ch5_Int_Clr(void)
clears ADC1 Channel 5 Interrupt flag.
Definition: adc1.h:3390
INLINE bool ADC1_GetSwModeResult_mV(uint16 *pVar_mV)
Get ADC1 software mode result in Millivolt.
Definition: adc1.h:3991
INLINE void ADC1_ESM_Int_En(void)
enables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3841
INLINE void ADC1_Ch4_Int_En(void)
enables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3659
INLINE void ADC1_Ch1_DataWidth_10bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 10-bit.
Definition: adc1.h:2171
INLINE void ADC1_Ch3_Int_En(void)
enables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3614
INLINE void ADC1_Ch6_Int_Clr(void)
clears ADC1 Channel 6 Interrupt flag.
Definition: adc1.h:3412
INLINE void ADC1_VDH_Attenuator_Range_0_20V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 22V.
Definition: adc1.h:3913
INLINE void ADC1_SetSocSwMode(uint8 Ch)
Starts ADC1 software mode conversion.
Definition: adc1.h:3966
INLINE void ADC1_Ch3_DataWidth_10bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 10-bit.
Definition: adc1.h:2275
INLINE uint8 ADC1_Ch0_ResultValid_Get(void)
Reads the valid flag for the channel 0 (P2.0) result.
Definition: adc1.h:1842
INLINE void ADC1_Ch5_WaitForRead_Set(void)
Sets the ADC1 channel 5 result register to "wait for read".
Definition: adc1.h:2964
INLINE uint8 ADC1_Current_Ch_Sts(void)
Reads the channel for currently ongoing conversion, if no conversion is ongoing, then it returns the ...
Definition: adc1.h:1011
INLINE void ADC1_Ch4_WaitForRead_Set(void)
Sets the ADC1 channel 4 result register to "wait for read".
Definition: adc1.h:2904
INLINE void ADC1_Ch1_WaitForRead_Set(void)
Sets ADC1 channel 1 the result register to "wait for read".
Definition: adc1.h:2724
INLINE uint8 ADC1_ESM_Active_Sts(void)
Reads the active status of the Exceptional Sequencer Measurement (ESM).
Definition: adc1.h:1128
INLINE void ADC1_Sequencer_Mode_Sel(void)
ADC1 selects the Sequencer Mode.
Definition: adc1.h:931
INLINE void ADC1_VDH_Attenuator_Zhigh_Set(void)
Enables the output attenuator for VDH.
Definition: adc1.h:3223
INLINE void ADC1_Ch5_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 5 number of sampling ticks.
Definition: adc1.h:2605
INLINE void ADC1_SetEIMChannel(uint8 channel)
Set(Change) ADC1 EIM channel.
Definition: adc1.h:3950
INLINE void ADC1_SetSwMode_Channel(uint8 channel)
Selects a channel for the software conversion.
Definition: adc1.h:3955
void ADC1_Init(void)
Initializes the ADC1 module based on the Config Wizard for MOTIX MCU configuration.
INLINE void ADC1_Ch2_Int_En(void)
enables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3569
INLINE void ADC1_Ch0_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 0 number of sampling ticks.
Definition: adc1.h:2460
INLINE void ADC1_Ch2_Int_Dis(void)
disables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3592
INLINE void ADC1_Ch0_Int_Dis(void)
disables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3502
INLINE void ADC1_Power_Off(void)
Disables the ADC1 module.
Definition: adc1.h:834
INLINE void ADC1_Ch3_Int_Dis(void)
disables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3637
INLINE void ADC1_VDH_Attenuator_Zlow_Set(void)
Disables the output attenuator for VDH.
Definition: adc1.h:3259
INLINE void ADC1_Ch5_Overwrite_Set(void)
Sets the ADC1 channel 5 result register to "overwrite".
Definition: adc1.h:2994
INLINE void ADC1_ESM_Channel_Set(uint32 mask_ch)
Set channels in ESM sequence.
Definition: adc1.h:3116
INLINE uint8 ADC1_Ch2_ResultValid_Get(void)
Reads the valid flag for the channel 2 (P2.2) result.
Definition: adc1.h:1906
INLINE void ADC1_VDH_Attenuator_Off(void)
Disables the input attenuator for VDH.
Definition: adc1.h:3187
INLINE void ADC1_ESM_Int_Clr(void)
clears Exceptional Sequence Measurement (ESM) flag.
Definition: adc1.h:3457
INLINE void ADC1_DIVA_Set(uint32 a)
ADC1 analog clock divider. .
Definition: adc1.h:891
INLINE void ADC1_Ch6_Int_Dis(void)
disables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3772
INLINE bool ADC1_Busy(void)
Reads the overall status of the ADC1.
Definition: adc1.h:3998
INLINE void ADC1_Ch5_DataWidth_8bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 8-bit.
Definition: adc1.h:2353
INLINE void ADC1_Ch6_DataWidth_10bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 10-bit.
Definition: adc1.h:2431
INLINE void ADC1_ESM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Set ADC1 ESM Trigger Selection.
Definition: adc1.h:4022
INLINE uint8 ADC1_Busy_Sts(void)
Reads the overall status of the ADC1.
Definition: adc1.h:1076
INLINE void ADC1_EIM_Int_Clr(void)
clears Exceptional Interrupt Measurement (EIM) flag.
Definition: adc1.h:3435
INLINE uint16 ADC1_Ch0_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1389
INLINE void ADC1_Ch0_Int_En(void)
enables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3479
INLINE uint8 ADC1_Ch1_ResultValid_Get(void)
Reads the valid flag for the channel 1 (CSA) result.
Definition: adc1.h:1874
ADC1_TRIGG_SEL
Definition: adc1.h:237
@ ADC1_Trigg_GPT12E_T3
Definition: adc1.h:241
@ ADC1_Trigg_Timer3
Definition: adc1.h:244
@ ADC1_Trigg_CCU6_Ch3
Definition: adc1.h:239
@ ADC1_Trigg_Timer21
Definition: adc1.h:243
@ ADC1_Trigg_Timer2
Definition: adc1.h:242
@ ADC1_Trigg_GPT12E_T6
Definition: adc1.h:240
@ ADC1_Trigg_None
Definition: adc1.h:238
INLINE void ADC1_Ch6_Int_En(void)
enables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3749
INLINE void ADC1_Ch4_Int_Dis(void)
disables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3682
enum ADC1_TRIGG_SEL TADC1_TRIGG_SEL
#define ADC1_VDH_Attenuator_Range_0_20V
ADC1 VDH Attenuator Selection, 0V..20V.
Definition: adc1.h:113
INLINE uint8 ADC1_Sample_Sts(void)
Reads the sample status of a ongoing measurement.
Definition: adc1.h:1044
INLINE void ADC1_SW_Ch_Sel(uint32 a)
Selects a channel for the software conversion.
Definition: adc1.h:871
ADC1_ANON
Definition: adc1.h:217
@ ADC1_ANON_NORMAL
Definition: adc1.h:221
@ ADC1_ANON_OFF
Definition: adc1.h:218
@ ADC1_ANON_S_STANDBY
Definition: adc1.h:219
@ ADC1_ANON_F_STANDBY
Definition: adc1.h:220
INLINE uint8 ADC1_Current_Active_Channel_Sts(void)
Reads the currently active channel.
Definition: adc1.h:1176
INLINE void ADC1_Sequence3_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 3, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1267
INLINE void ADC1_Sequence5_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 5, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1313
INLINE uint16 ADC1_P20_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1630
INLINE bool ADC1_isEndOfConversion(void)
checks EndOfConversion ready (Software Mode)
Definition: adc1.h:4028
INLINE uint16 ADC1_Ch2_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1449
INLINE void ADC1_Ch3_Overwrite_Set(void)
Sets the ADC1 channel 3 result register to "overwrite".
Definition: adc1.h:2874
INLINE void ADC1_Ch0_Overwrite_Set(void)
Sets the ADC1 channel 0 result register to "overwrite".
Definition: adc1.h:2694
INLINE bool ADC1_GetSwModeResult(uint16 *pVar)
Get ADC1 latest software mode result.
Definition: adc1.h:3984
INLINE void ADC1_Ch0_Int_Clr(void)
clears ADC1 Channel 0 Interrupt flag.
Definition: adc1.h:3281
INLINE void ADC1_Ch3_DataWidth_8bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 8-bit.
Definition: adc1.h:2249
INLINE void ADC1_Sequence1_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 1, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1221
INLINE void ADC1_Sequence2_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 2, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1244
bool ADC1_GetChResult(uint16 *pVar, uint8 channel)
Get the 10-bit/8-bit value of the ADC1 Result Register of the selected ADC1 channel and returns the v...
union ADC1_ANON_U TADC1_ANON_U
INLINE void ADC1_Software_Mode_Sel(void)
ADC1 selects the Software Mode, measurements are performed on user request.
Definition: adc1.h:954
INLINE void ADC1_Ch3_Int_Clr(void)
clears ADC1 Channel 3 Interrupt flag.
Definition: adc1.h:3347
INLINE void ADC1_Ch5_DataWidth_10bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 10-bit.
Definition: adc1.h:2379
INLINE void ADC1_Ch6_DataWidth_8bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 8-bit.
Definition: adc1.h:2405
ADC1_EIM_REP_CNT
Definition: adc1.h:255
@ ADC1_128_Meas
Definition: adc1.h:263
@ ADC1_1_Meas
Definition: adc1.h:256
@ ADC1_4_Meas
Definition: adc1.h:258
@ ADC1_2_Meas
Definition: adc1.h:257
@ ADC1_32_Meas
Definition: adc1.h:261
@ ADC1_16_Meas
Definition: adc1.h:260
@ ADC1_8_Meas
Definition: adc1.h:259
@ ADC1_64_Meas
Definition: adc1.h:262
INLINE bool ADC1_GetEocSwMode(void)
Get ADC1 end of conversion status.
Definition: adc1.h:3972
INLINE void ADC1_Ch1_Int_Clr(void)
clears ADC1 Channel 1 Interrupt flag.
Definition: adc1.h:3303
INLINE uint8 ADC1_EOC_Sts(void)
Reads the End-of-Conversion status.
Definition: adc1.h:981
INLINE uint8 ADC1_Current_Active_Sequence_Sts(void)
Reads the currently active channel in Sequencer Mode.
Definition: adc1.h:1152
INLINE uint16 ADC1_EIM_Result_Get(void)
Reads the converted value from the EIM result register.
Definition: adc1.h:1600
INLINE void ADC1_Ch4_DataWidth_8bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 8-bit.
Definition: adc1.h:2301
INLINE uint8 ADC1_EIM_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2067
INLINE void ADC1_Ch4_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 4 number of sampling ticks.
Definition: adc1.h:2576
enum ADC1_EIM_REP_CNT TADC1_EIM_REP_CNT
INLINE void ADC1_Sequence6_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 6, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1336
bool ADC1_GetEIMResult(uint16 *pVar)
Get the 10-bit/8-bit value of the ADC1 EIM Result Register and returns the validity info.
INLINE bool ADC1_isESMactive(void)
checks Exceptional Sequencer Mode active
Definition: adc1.h:4052
INLINE void ADC1_Ch1_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 1 number of sampling ticks.
Definition: adc1.h:2489
INLINE void ADC1_Ch5_Int_En(void)
enables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3704
INLINE void ADC1_ANON_Set(uint32 a)
ADC1 set the Analog Module Mode.
Definition: adc1.h:910
bool VAREF_Enable(void)
Re-enables the internal VAREF LDO in case it was shutdown due to a previous failure.
INLINE void ADC1_Ch2_Overwrite_Set(void)
Sets the ADC1 channel 2 result register to "overwrite".
Definition: adc1.h:2814
#define ADC1_VDH_Attenuator_Range_0_30V
ADC1 VDH Attenuator Selection, 0V..30V.
Definition: adc1.h:111
INLINE void ADC1_Ch1_DataWidth_8bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 8-bit.
Definition: adc1.h:2145
INLINE uint16 ADC1_Ch6_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1569
INLINE void ADC1_Ch4_Overwrite_Set(void)
Sets the ADC1 channel 4 result register to "overwrite".
Definition: adc1.h:2934
INLINE uint16 ADC1_CSA_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1660
INLINE void ADC1_Ch2_Int_Clr(void)
clears ADC1 Channel 2 Interrupt flag.
Definition: adc1.h:3325
INLINE void ADC1_Ch2_DataWidth_8bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 8-bit.
Definition: adc1.h:2197
INLINE void ADC1_Ch5_Int_Dis(void)
disables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3727
enum ADC1_ANON TADC1_ANON
INLINE void ADC1_SOC_Set(void)
ADC1 Start of Conversion, for Software mode only.
Definition: adc1.h:851
INLINE void ADC1_Ch1_Int_Dis(void)
disables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3547
INLINE void ADC1_Ch6_Overwrite_Set(void)
Sets the ADC1 channel 6 result register to "overwrite".
Definition: adc1.h:3054
INLINE void ADC1_Ch4_DataWidth_10bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 10-bit.
Definition: adc1.h:2327
INLINE uint16 ADC1_Ch1_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1419
INLINE void ADC1_Sequence0_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 0, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1198
INLINE uint8 ADC1_Ch5_ResultValid_Get(void)
Reads the valid flag for the channel 5 (P2.5) result.
Definition: adc1.h:2002
INLINE void ADC1_Ch3_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 3 number of sampling ticks.
Definition: adc1.h:2547
INLINE TADC1_ANON ADC1_ANON_Sts(void)
Reads the Analog Part Switched On Mode status.
Definition: adc1.h:4064
INLINE uint16 ADC1_Ch3_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1479
INLINE uint8 ADC1_Ch6_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2034
INLINE void ADC1_VDH_Attenuator_Range_0_30V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 30V.
Definition: adc1.h:3889
INLINE void ADC1_VDH_Attenuator_On(void)
Enables the input attenuator for VDH.
Definition: adc1.h:3152
INLINE void ADC1_EIM_Repeat_Counter_Set(TADC1_EIM_REP_CNT repcnt)
Set ADC1 EIM Repeat Counter.
Definition: adc1.h:4016
INLINE void ADC1_EIM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Get ADC1 EIM Trigger Selection.
Definition: adc1.h:4010
INLINE uint8 ADC1_Ch4_ResultValid_Get(void)
Reads the valid flag for the channel 4 (P2.4) result.
Definition: adc1.h:1970
INLINE void ADC1_EIM_Int_En(void)
enables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3795
INLINE uint8 ADC1_VDH_Attenuator_Range_Get(void)
Reads the VDH Monitoring Input Attenuator Input Range Configuration.
Definition: adc1.h:3942
INLINE void ADC1_ESM_Int_Dis(void)
disables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3864
INLINE void ADC1_EIM_Channel_Set(uint32 ch)
Set EIM channel for measurement.
Definition: adc1.h:3085
bool ADC1_GetChResult_mV(uint16 *pVar_mV, uint8 channel)
Get the value of the ADC1 Result Register of the selected ADC1 channel in Millivolt (mV) and returns ...
INLINE void ADC1_Ch0_DataWidth_10bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 10-bit.
Definition: adc1.h:2119
INLINE void ADC1_Ch2_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 2 number of sampling ticks.
Definition: adc1.h:2518
INLINE void ADC1_Ch0_WaitForRead_Set(void)
Sets the ADC1 channel 0 result register to "wait for read".
Definition: adc1.h:2664
INLINE void ADC1_Ch6_WaitForRead_Set(void)
Sets the ADC1 channel 6 result register to "wait for read".
Definition: adc1.h:3024
bool ADC1_GetEIMResult_mV(uint16 *pVar_mV)
Get the value of the ADC1 EIM Result Register in Millivolt (mV) and returns the validity info.
INLINE void ADC1_Ch1_Int_En(void)
enables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3524
INLINE void ADC1_Ch2_DataWidth_10bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 10-bit.
Definition: adc1.h:2223
INLINE void ADC1_Ch0_DataWidth_8bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 8-bit.
Definition: adc1.h:2093
#define MF
Definition: tle987x.h:6067
#define ADC1
Definition: tle987x.h:6057
#define ADC1_SQ_FB_SQx_Msk
Definition: tle987x.h:6344
#define ADC1_RES_OUT1_WFR1_Pos
Definition: tle987x.h:6255
#define ADC1_RES_OUT5_OUT_CH5_Msk
Definition: tle987x.h:6294
#define ADC1_RES_OUT6_VF6_Msk
Definition: tle987x.h:6299
#define ADC1_SQ_FB_ESM_ACTIVE_Pos
Definition: tle987x.h:6345
#define ADC1_STC_4_7_ch6_Pos
Definition: tle987x.h:6363
#define ADC1_IE_CH3_IE_Pos
Definition: tle987x.h:6212
#define ADC1_CHx_ESM_TRIG_SEL_Msk
Definition: tle987x.h:6135
#define ADC1_ICLR_CH3_ICLR_Msk
Definition: tle987x.h:6192
#define ADC1_CTRL_STS_EOC_Msk
Definition: tle987x.h:6142
#define ADC1_CHx_ESM_TRIG_SEL_Pos
Definition: tle987x.h:6134
#define ADC1_IE_CH1_IE_Pos
Definition: tle987x.h:6216
#define ADC1_IE_CH3_IE_Msk
Definition: tle987x.h:6213
#define ADC1_ICLR_CH4_ICLR_Pos
Definition: tle987x.h:6189
#define ADC1_DWSEL_ch4_Pos
Definition: tle987x.h:6154
#define ADC1_SQ1_4_SQ4_Msk
Definition: tle987x.h:6324
#define ADC1_RES_OUT4_WFR4_Msk
Definition: tle987x.h:6283
#define ADC1_GLOBSTR_ANON_ST_Msk
Definition: tle987x.h:6171
#define ADC1_DWSEL_ch2_Pos
Definition: tle987x.h:6158
#define ADC1_IE_CH0_IE_Pos
Definition: tle987x.h:6218
#define ADC1_DWSEL_ch0_Pos
Definition: tle987x.h:6162
#define ADC1_ICLR_CH1_ICLR_Pos
Definition: tle987x.h:6195
#define ADC1_RES_OUT5_VF5_Msk
Definition: tle987x.h:6290
#define ADC1_RES_OUT5_WFR5_Pos
Definition: tle987x.h:6291
#define ADC1_STC_0_3_ch0_Pos
Definition: tle987x.h:6358
#define ADC1_IE_CH6_IE_Pos
Definition: tle987x.h:6206
#define ADC1_RES_OUT2_VF2_Pos
Definition: tle987x.h:6262
#define ADC1_ICLR_CH2_ICLR_Msk
Definition: tle987x.h:6194
#define ADC1_RES_OUT0_VF0_Pos
Definition: tle987x.h:6244
#define ADC1_RES_OUT4_VF4_Msk
Definition: tle987x.h:6281
#define ADC1_RES_OUT_EIM_VF8_Msk
Definition: tle987x.h:6317
#define ADC1_RES_OUT6_WFR6_Msk
Definition: tle987x.h:6301
#define ADC1_STC_4_7_ch5_Msk
Definition: tle987x.h:6366
#define ADC1_CTRL_STS_IN_MUX_SEL_Msk
Definition: tle987x.h:6140
#define ADC1_RES_OUT5_WFR5_Msk
Definition: tle987x.h:6292
#define ADC1_STC_4_7_ch4_Pos
Definition: tle987x.h:6367
#define ADC1_STC_4_7_ch6_Msk
Definition: tle987x.h:6364
#define ADC1_IE_CH4_IE_Msk
Definition: tle987x.h:6211
#define ADC1_RES_OUT3_OUT_CH3_Msk
Definition: tle987x.h:6276
#define ADC1_SQ_FB_EIM_ACTIVE_Pos
Definition: tle987x.h:6347
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos
Definition: tle987x.h:8223
#define ADC1_IE_CH2_IE_Msk
Definition: tle987x.h:6215
#define ADC1_RES_OUT0_WFR0_Msk
Definition: tle987x.h:6247
#define ADC1_SQ1_4_SQ2_Pos
Definition: tle987x.h:6327
#define ADC1_RES_OUT5_VF5_Pos
Definition: tle987x.h:6289
#define ADC1_SQ_FB_EIM_ACTIVE_Msk
Definition: tle987x.h:6348
#define ADC1_SQ_FB_SQx_Pos
Definition: tle987x.h:6343
#define ADC1_IE_CH1_IE_Msk
Definition: tle987x.h:6217
#define ADC1_GLOBSTR_SAMPLE_Pos
Definition: tle987x.h:6174
#define ADC1_RES_OUT5_OUT_CH5_Pos
Definition: tle987x.h:6293
#define ADC1_GLOBSTR_CHNR_Pos
Definition: tle987x.h:6172
#define ADC1_CHx_EIM_TRIG_SEL_Pos
Definition: tle987x.h:6127
#define ADC1_SQ1_4_SQ3_Pos
Definition: tle987x.h:6325
#define ADC1_RES_OUT2_OUT_CH2_Msk
Definition: tle987x.h:6267
#define ADC1_ICLR_CH1_ICLR_Msk
Definition: tle987x.h:6196
#define ADC1_RES_OUT6_VF6_Pos
Definition: tle987x.h:6298
#define ADC1_DWSEL_ch4_Msk
Definition: tle987x.h:6155
#define ADC1_DWSEL_ch6_Pos
Definition: tle987x.h:6150
#define ADC1_SQ5_8_SQ7_Pos
Definition: tle987x.h:6334
#define ADC1_SQ_FB_SQ_RUN_Msk
Definition: tle987x.h:6350
#define ADC1_SQ1_4_SQ4_Pos
Definition: tle987x.h:6323
#define ADC1_CTRL_STS_IN_MUX_SEL_Pos
Definition: tle987x.h:6139
#define ADC1_DWSEL_ch3_Msk
Definition: tle987x.h:6157
#define ADC1_STC_0_3_ch3_Msk
Definition: tle987x.h:6353
#define ADC1_SQ1_4_SQ1_Msk
Definition: tle987x.h:6330
#define ADC1_STC_0_3_ch3_Pos
Definition: tle987x.h:6352
#define ADC1_GLOBSTR_SAMPLE_Msk
Definition: tle987x.h:6175
#define ADC1_RES_OUT1_VF1_Msk
Definition: tle987x.h:6254
#define ADC1_RES_OUT0_VF0_Msk
Definition: tle987x.h:6245
#define ADC1_RES_OUT4_OUT_CH4_Msk
Definition: tle987x.h:6285
#define ADC1_GLOBSTR_CHNR_Msk
Definition: tle987x.h:6173
#define ADC1_CHx_ESM_ESM_0_Msk
Definition: tle987x.h:6137
#define ADC1_CHx_EIM_CHx_Msk
Definition: tle987x.h:6132
#define ADC1_STC_4_7_ch5_Pos
Definition: tle987x.h:6365
#define ADC1_ICLR_ESM_ICLR_Pos
Definition: tle987x.h:6179
#define ADC1_DWSEL_ch2_Msk
Definition: tle987x.h:6159
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos
Definition: tle987x.h:8227
#define ADC1_SQ5_8_SQ8_Pos
Definition: tle987x.h:6332
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos
Definition: tle987x.h:6320
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk
Definition: tle987x.h:6321
#define ADC1_SQ5_8_SQ5_Pos
Definition: tle987x.h:6338
#define ADC1_ICLR_EIM_ICLR_Msk
Definition: tle987x.h:6182
#define ADC1_SQ5_8_SQ6_Pos
Definition: tle987x.h:6336
#define ADC1_IE_CH5_IE_Pos
Definition: tle987x.h:6208
#define ADC1_CTRL_STS_PD_N_Pos
Definition: tle987x.h:6145
#define ADC1_ICLR_CH6_ICLR_Msk
Definition: tle987x.h:6186
#define ADC1_RES_OUT3_WFR3_Msk
Definition: tle987x.h:6274
#define ADC1_RES_OUT3_OUT_CH3_Pos
Definition: tle987x.h:6275
#define ADC1_STC_0_3_ch1_Msk
Definition: tle987x.h:6357
#define ADC1_ICLR_CH2_ICLR_Pos
Definition: tle987x.h:6193
#define ADC1_RES_OUT1_OUT_CH1_Msk
Definition: tle987x.h:6258
#define ADC1_CHx_EIM_REP_Msk
Definition: tle987x.h:6130
#define ADC1_RES_OUT0_OUT_CH0_Msk
Definition: tle987x.h:6249
#define ADC1_DWSEL_ch1_Msk
Definition: tle987x.h:6161
#define ADC1_ICLR_CH6_ICLR_Pos
Definition: tle987x.h:6185
#define ADC1_SQ1_4_SQ2_Msk
Definition: tle987x.h:6328
#define ADC1_ICLR_CH0_ICLR_Msk
Definition: tle987x.h:6198
#define ADC1_SQ_FB_SQ_RUN_Pos
Definition: tle987x.h:6349
#define ADC1_IE_CH0_IE_Msk
Definition: tle987x.h:6219
#define ADC1_ICLR_CH3_ICLR_Pos
Definition: tle987x.h:6191
#define ADC1_CTRL_STS_EOC_Pos
Definition: tle987x.h:6141
#define ADC1_DWSEL_ch3_Pos
Definition: tle987x.h:6156
#define ADC1_SQ_FB_ESM_ACTIVE_Msk
Definition: tle987x.h:6346
#define ADC1_GLOBSTR_BUSY_Msk
Definition: tle987x.h:6177
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk
Definition: tle987x.h:8226
#define ADC1_RES_OUT1_VF1_Pos
Definition: tle987x.h:6253
#define ADC1_ICLR_CH5_ICLR_Msk
Definition: tle987x.h:6188
#define ADC1_RES_OUT4_WFR4_Pos
Definition: tle987x.h:6282
#define ADC1_STC_4_7_ch4_Msk
Definition: tle987x.h:6368
#define ADC1_RES_OUT3_VF3_Pos
Definition: tle987x.h:6271
#define ADC1_SQ5_8_SQ7_Msk
Definition: tle987x.h:6335
#define ADC1_IE_CH6_IE_Msk
Definition: tle987x.h:6207
#define ADC1_CTRL_STS_PD_N_Msk
Definition: tle987x.h:6146
#define ADC1_IE_CH5_IE_Msk
Definition: tle987x.h:6209
#define ADC1_SQ_FB_CHx_Msk
Definition: tle987x.h:6342
#define ADC1_RES_OUT0_OUT_CH0_Pos
Definition: tle987x.h:6248
#define ADC1_ICLR_CH5_ICLR_Pos
Definition: tle987x.h:6187
#define ADC1_STC_0_3_ch2_Pos
Definition: tle987x.h:6354
#define ADC1_CHx_EIM_CHx_Pos
Definition: tle987x.h:6131
#define ADC1_STC_0_3_ch2_Msk
Definition: tle987x.h:6355
#define ADC1_DWSEL_ch5_Msk
Definition: tle987x.h:6153
#define ADC1_CHx_EIM_TRIG_SEL_Msk
Definition: tle987x.h:6128
#define ADC1_IE_ESM_IE_Msk
Definition: tle987x.h:6201
#define ADC1_CTRL_STS_SOC_Msk
Definition: tle987x.h:6144
#define ADC1_RES_OUT2_OUT_CH2_Pos
Definition: tle987x.h:6266
#define ADC1_DWSEL_ch6_Msk
Definition: tle987x.h:6151
#define ADC1_ICLR_CH4_ICLR_Msk
Definition: tle987x.h:6190
#define ADC1_RES_OUT2_WFR2_Pos
Definition: tle987x.h:6264
#define ADC1_CHx_ESM_ESM_0_Pos
Definition: tle987x.h:6136
#define ADC1_ICLR_CH0_ICLR_Pos
Definition: tle987x.h:6197
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk
Definition: tle987x.h:8224
#define ADC1_SQ1_4_SQ1_Pos
Definition: tle987x.h:6329
#define ADC1_IE_EIM_IE_Pos
Definition: tle987x.h:6202
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk
Definition: tle987x.h:8228
#define ADC1_GLOBSTR_ANON_ST_Pos
Definition: tle987x.h:6170
#define ADC1_DWSEL_ch1_Pos
Definition: tle987x.h:6160
#define ADC1_IE_EIM_IE_Msk
Definition: tle987x.h:6203
#define ADC1_STC_0_3_ch0_Msk
Definition: tle987x.h:6359
#define ADC1_GLOBSTR_BUSY_Pos
Definition: tle987x.h:6176
#define ADC1_RES_OUT6_OUT_CH6_Msk
Definition: tle987x.h:6303
#define ADC1_SQ5_8_SQ5_Msk
Definition: tle987x.h:6339
#define ADC1_ICLR_EIM_ICLR_Pos
Definition: tle987x.h:6181
#define ADC1_RES_OUT3_VF3_Msk
Definition: tle987x.h:6272
#define ADC1_RES_OUT6_OUT_CH6_Pos
Definition: tle987x.h:6302
#define ADC1_STC_0_3_ch1_Pos
Definition: tle987x.h:6356
#define ADC1_RES_OUT_EIM_VF8_Pos
Definition: tle987x.h:6316
#define ADC1_GLOBCTR_ANON_Pos
Definition: tle987x.h:6165
#define ADC1_ICLR_ESM_ICLR_Msk
Definition: tle987x.h:6180
#define ADC1_CHx_EIM_REP_Pos
Definition: tle987x.h:6129
#define ADC1_IE_CH2_IE_Pos
Definition: tle987x.h:6214
#define ADC1_RES_OUT6_WFR6_Pos
Definition: tle987x.h:6300
#define ADC1_RES_OUT2_WFR2_Msk
Definition: tle987x.h:6265
#define ADC1_GLOBCTR_ANON_Msk
Definition: tle987x.h:6166
#define ADC1_SQ_FB_CHx_Pos
Definition: tle987x.h:6341
#define ADC1_IE_CH4_IE_Pos
Definition: tle987x.h:6210
#define ADC1_SQ5_8_SQ6_Msk
Definition: tle987x.h:6337
#define ADC1_SQ5_8_SQ8_Msk
Definition: tle987x.h:6333
#define ADC1_RES_OUT0_WFR0_Pos
Definition: tle987x.h:6246
#define ADC1_RES_OUT1_WFR1_Msk
Definition: tle987x.h:6256
#define ADC1_GLOBCTR_DIVA_Msk
Definition: tle987x.h:6168
#define ADC1_DWSEL_ch0_Msk
Definition: tle987x.h:6163
#define ADC1_RES_OUT3_WFR3_Pos
Definition: tle987x.h:6273
#define ADC1_IE_ESM_IE_Pos
Definition: tle987x.h:6200
#define ADC1_RES_OUT1_OUT_CH1_Pos
Definition: tle987x.h:6257
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos
Definition: tle987x.h:8225
#define ADC1_SQ1_4_SQ3_Msk
Definition: tle987x.h:6326
#define ADC1_DWSEL_ch5_Pos
Definition: tle987x.h:6152
#define ADC1_GLOBCTR_DIVA_Pos
Definition: tle987x.h:6167
#define ADC1_RES_OUT4_OUT_CH4_Pos
Definition: tle987x.h:6284
#define ADC1_CTRL_STS_SOC_Pos
Definition: tle987x.h:6143
#define ADC1_RES_OUT2_VF2_Msk
Definition: tle987x.h:6263
#define ADC1_RES_OUT4_VF4_Pos
Definition: tle987x.h:6280
SFR low level access library.
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:347
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:392
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:417
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:332
INLINE uint8 u8_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 8-bit field of a 32-bit register.
Definition: sfr_access.h:407
INLINE uint32 u32_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 32-bit field of a 32-bit register.
Definition: sfr_access.h:422
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:132
uint8_t uint8
8 bit unsigned value
Definition: types.h:137
uint16_t uint16
16 bit unsigned value
Definition: types.h:138
uint32_t uint32
32 bit unsigned value
Definition: types.h:139
Definition: adc1.h:225
uint32 dword
Definition: adc1.h:226
TADC1_ANON adc1_anon
Definition: adc1.h:227