Infineon MOTIX™ MCU TLE987x Device Family SDK
int.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
20 /*******************************************************************************
21 ** Author(s) Identity **
22 ********************************************************************************
23 ** Initials Name **
24 ** ---------------------------------------------------------------------------**
25 ** DM Daniel Mysliwitz **
26 ** AP Adriano Pereira **
27 ** BG Blandine Guillot **
28 ** JO Julia Ott **
29 *******************************************************************************/
30 
31 /*******************************************************************************
32 ** Revision Control History **
33 ********************************************************************************
34 ** V0.1.0: 2014-05-11, DM: Initial version **
35 ** V0.1.1: 2015-02-10, DM: Individual header file added **
36 ** V0.1.2: 2015-09-17, DM: SYS_IRQ_CTRL register init added **
37 ** V0.1.3: 2015-11-25, DM: SCU_DMAIENx added, SCU_DMAIRCx clear added **
38 ** V0.1.4: 2016-10-10, DM: Interrupt Enable/Disable macros added **
39 ** CPU->SHPR3 init (SysTick Prio) added **
40 ** V0.1.5: 2017-10-05, DM: MISRA 2012 compliance, the following PC-Lint **
41 ** rules are globally deactivated: **
42 ** - Info 793: ANSI/ISO limit of 6 'significant **
43 ** characters in an external identifier **
44 ** - Info 835: A zero has been given as right **
45 ** argument to operator **
46 ** - Info 845: The left argument to operator '&' **
47 ** is certain to be 0 **
48 ** V0.1.6: 2018-03-20, DM: #define NMI_xxx macros modified to meet MISRA2012**
49 ** #define EXINTx_xxx macros modified to meet **
50 ** MISRA2012 **
51 ** Replaced macros by INLINE functions **
52 ** Replaced register accesses within functions by **
53 ** function calls **
54 ** Replaced __STATIC_INLINE by INLINE **
55 ** V0.1.7: 2018-07-04, AP: Added functions to enable/disable NVIC nodes **
56 ** V0.1.8: 2018-11-27, JO: Doxygen update **
57 ** Moved revision history from int.c to int.h **
58 ** V0.1.9: 2019-04-18, JO: Corrected NVIC_NodeXYZ_En/Dis functions **
59 ** V0.2.0: 2019-10-14, JO: Bridge driver interrupts enabled for CW2 **
60 ** V0.2.1: 2020-04-15, BG: Updated revision history format **
61 ** V0.2.2: 2020-07-21, BG: EP-439: Formatted .h/.c files **
62 ** V0.2.3: 2022-02-28, JO: EP-936: Updated copyright and branding **
63 ** V0.2.4: 2025-01-02, JO: EP-1493: Updated license **
64 *******************************************************************************/
65 
66 #ifndef INT_H
67 #define INT_H
68 
69 /*******************************************************************************
70 ** Includes **
71 *******************************************************************************/
72 #include "tle987x.h"
73 #include "types.h"
74 #include "tle_variants.h"
75 #include "sfr_access.h"
76 
77 /*******************************************************************************
78 ** Global Macro Definitions **
79 *******************************************************************************/
81 #define NMI_WDT ((uint8)1u << 0u)
83 #define NMI_PLL ((uint8)1u << 1u)
85 #define NMI_NVM ((uint8)1u << 2u)
87 #define NMI_OT ((uint8)1u << 3u)
89 #define NMI_OWT ((uint8)1u << 4u)
91 #define NMI_MAP ((uint8)1u << 5u)
93 #define NMI_ECC ((uint8)1u << 6u)
95 #define NMI_SUP ((uint8)1u << 7u)
97 #define SCU_EXICON0_EXINT0_RE_Pos (0UL)
99 #define SCU_EXICON0_EXINT0_RE_Msk (0x01UL)
101 #define SCU_EXICON0_EXINT0_FE_Pos (1UL)
103 #define SCU_EXICON0_EXINT0_FE_Msk (0x02UL)
105 #define SCU_EXICON0_EXINT1_RE_Pos (2UL)
107 #define SCU_EXICON0_EXINT1_RE_Msk (0x04UL)
109 #define SCU_EXICON0_EXINT1_FE_Pos (3UL)
111 #define SCU_EXICON0_EXINT1_FE_Msk (0x08UL)
113 #define SCU_EXICON0_EXINT2_RE_Pos (4UL)
115 #define SCU_EXICON0_EXINT2_RE_Msk (0x10UL)
117 #define SCU_EXICON0_EXINT2_FE_Pos (5UL)
119 #define SCU_EXICON0_EXINT2_FE_Msk (0x20UL)
121 #define SCU_NMISR_Pos (0UL)
123 #define SCU_NMISR_Msk (0xFFUL)
125 #define SCU_NMICLR_Pos (0UL)
127 #define SCU_NMICLR_Msk (0xFFUL)
128 
129 
130 /*******************************************************************************
131 ** Inline Function Definitions **
132 *******************************************************************************/
146 {
148 }
149 
163 {
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989 {
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1565 
1566 #if (UC_SERIES == TLE987)
1585 {
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1608 {
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1653 {
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1943 {
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1965 {
1967 }
1968 #endif /* (UC_SERIES = TLE987) */
1969 
1970 /*******************************************************************************
1971 ** Global Function Declarations **
1972 *******************************************************************************/
1974 INLINE void INT_Clr_NMI_Status(uint8 Flags);
1975 INLINE void INT_Enable_Global_Int(void);
1976 INLINE void INT_Disable_Global_Int(void);
1977 
1982 void INT_Init(void);
1983 
1984 /*******************************************************************************
1985 ** Global Inline Function Definitions **
1986 *******************************************************************************/
2004 {
2005  return u8_Field_Rd8(&SCU->NMISR.reg, (uint8)SCU_NMISR_Pos, (uint8)SCU_NMISR_Msk);
2006 }
2007 
2023 {
2024  Field_Wrt8(&SCU->NMICLR.reg, (uint8)SCU_NMICLR_Pos, (uint8)SCU_NMICLR_Msk, Flags);
2025 }
2026 
2040 {
2041  Global_Int_En();
2042 }
2043 
2057 {
2058  Global_Int_Dis();
2059 }
2060 
2061 #endif
#define SCUPM
Definition: tle987x.h:6072
#define CPU
Definition: tle987x.h:6063
#define SCU
Definition: tle987x.h:6071
#define SCU_NMICLR_NMISUPC_Msk
Definition: tle987x.h:9192
#define CPU_NVIC_ISER0_Int_UART2_Pos
Definition: tle987x.h:7729
#define CPU_NVIC_ISER0_Int_BDRV_Msk
Definition: tle987x.h:7724
#define CPU_NVIC_ISER0_Int_SSC2_Msk
Definition: tle987x.h:7734
#define CPU_NVIC_ICER0_Int_ADC1_Pos
Definition: tle987x.h:7643
#define SCU_EDCSCLR_RDBEC_Pos
Definition: tle987x.h:8912
#define SCU_IRCON0CLR_EXINT0FC_Msk
Definition: tle987x.h:9015
#define CPU_NVIC_ISER0_Int_UART1_Msk
Definition: tle987x.h:7732
#define CPU_NVIC_ISER0_Int_SSC2_Pos
Definition: tle987x.h:7733
#define CPU_NVIC_ISER0_Int_GPT2_Pos
Definition: tle987x.h:7749
#define SCU_NMICLR_NMIMAPC_Msk
Definition: tle987x.h:9196
#define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Pos
Definition: tle987x.h:9666
#define SCU_IRCON0CLR_EXINT0RC_Msk
Definition: tle987x.h:9017
#define CPU_NVIC_ICER0_Int_CCU6SR2_Msk
Definition: tle987x.h:7638
#define CPU_NVIC_ICER0_Int_GPT1_Pos
Definition: tle987x.h:7649
#define CPU_NVIC_ISER0_Int_CCU6SR0_Msk
Definition: tle987x.h:7744
#define CPU_NVIC_ISER0_Int_EXINT0_Pos
Definition: tle987x.h:7727
#define CPU_NVIC_ISER0_Int_CCU6SR0_Pos
Definition: tle987x.h:7743
#define SCU_NMICLR_NMIOWDC_Pos
Definition: tle987x.h:9197
#define SCU_EDCSCLR_NVMDBEC_Msk
Definition: tle987x.h:8911
#define SCU_NMICLR_NMIOTC_Pos
Definition: tle987x.h:9199
#define CPU_NVIC_ICER0_Int_ADC1_Msk
Definition: tle987x.h:7644
#define CPU_NVIC_ICER0_Int_EXINT0_Pos
Definition: tle987x.h:7625
#define SCU_NMICON_NMIMAP_Pos
Definition: tle987x.h:9212
#define SCU_NMICON_NMIOWD_Msk
Definition: tle987x.h:9215
#define CPU_NVIC_ISER0_Int_ADC2_Msk
Definition: tle987x.h:7748
#define SCU_NMICLR_NMISUPC_Pos
Definition: tle987x.h:9191
#define CPU_NVIC_ISER0_Int_ADC1_Msk
Definition: tle987x.h:7746
#define SCU_IRCON0CLR_EXINT2RC_Pos
Definition: tle987x.h:9008
#define CPU_NVIC_ISER0_Int_EXINT1_Msk
Definition: tle987x.h:7726
#define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Msk
Definition: tle987x.h:9667
#define CPU_NVIC_ICER0_Int_CCU6SR1_Msk
Definition: tle987x.h:7640
#define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Msk
Definition: tle987x.h:9673
#define CPU_NVIC_ICER0_Int_SSC2_Pos
Definition: tle987x.h:7631
#define SCU_IRCON0CLR_EXINT1FC_Pos
Definition: tle987x.h:9010
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Msk
Definition: tle987x.h:9581
#define CPU_NVIC_ICER0_Int_UART1_Pos
Definition: tle987x.h:7629
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Msk
Definition: tle987x.h:9579
#define SCU_IRCON0CLR_EXINT1RC_Pos
Definition: tle987x.h:9012
#define CPU_NVIC_ICER0_Int_EXINT0_Msk
Definition: tle987x.h:7626
#define SCU_EDCSCLR_RSBEC_Msk
Definition: tle987x.h:8909
#define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Msk
Definition: tle987x.h:9675
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Pos
Definition: tle987x.h:9578
#define CPU_NVIC_ISER0_Int_CCU6SR2_Msk
Definition: tle987x.h:7740
#define SCU_NMICON_NMINVM_Pos
Definition: tle987x.h:9218
#define CPU_NVIC_ISER0_Int_CCU6SR2_Pos
Definition: tle987x.h:7739
#define CPU_NVIC_ISER0_Int_GPT1_Msk
Definition: tle987x.h:7752
#define CPU_NVIC_ICER0_Int_UART2_Msk
Definition: tle987x.h:7628
#define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Msk
Definition: tle987x.h:9671
#define SCU_IRCON0CLR_EXINT0RC_Pos
Definition: tle987x.h:9016
#define SCU_IRCON0CLR_EXINT1RC_Msk
Definition: tle987x.h:9013
#define CPU_NVIC_ICER0_Int_SSC1_Msk
Definition: tle987x.h:7634
#define CPU_NVIC_ICER0_Int_GPT2_Pos
Definition: tle987x.h:7647
#define CPU_NVIC_ISER0_Int_GPT1_Pos
Definition: tle987x.h:7751
#define SCU_IRCON0CLR_EXINT2RC_Msk
Definition: tle987x.h:9009
#define SCU_EDCCON_NVMIE_Pos
Definition: tle987x.h:8903
#define CPU_NVIC_ISER0_Int_BDRV_Pos
Definition: tle987x.h:7723
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Pos
Definition: tle987x.h:9572
#define CPU_NVIC_ICER0_Int_SSC1_Pos
Definition: tle987x.h:7633
#define SCU_IRCON0CLR_EXINT2FC_Pos
Definition: tle987x.h:9006
#define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Pos
Definition: tle987x.h:9668
#define CPU_NVIC_ICER0_Int_CCU6SR3_Msk
Definition: tle987x.h:7636
#define CPU_NVIC_ISER0_Int_CCU6SR1_Msk
Definition: tle987x.h:7742
#define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Msk
Definition: tle987x.h:9665
#define SCU_EDCCON_RIE_Msk
Definition: tle987x.h:8906
#define SCU_EDCSCLR_RSBEC_Pos
Definition: tle987x.h:8908
#define SCU_NMICON_NMINVM_Msk
Definition: tle987x.h:9219
#define SCU_IRCON0CLR_EXINT1FC_Msk
Definition: tle987x.h:9011
#define CPU_NVIC_ISER0_Int_SSC1_Msk
Definition: tle987x.h:7736
#define CPU_NVIC_ICER0_Int_BDRV_Pos
Definition: tle987x.h:7621
#define CPU_NVIC_ISER0_Int_DMA_Pos
Definition: tle987x.h:7721
#define SCU_NMICON_NMISUP_Msk
Definition: tle987x.h:9209
#define SCU_NMICON_NMIOWD_Pos
Definition: tle987x.h:9214
#define SCU_NMICON_NMIOT_Pos
Definition: tle987x.h:9216
#define SCU_NMICON_NMIECC_Msk
Definition: tle987x.h:9211
#define CPU_NVIC_ISER0_Int_EXINT1_Pos
Definition: tle987x.h:7725
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Pos
Definition: tle987x.h:9574
#define CPU_NVIC_ICER0_Int_DMA_Pos
Definition: tle987x.h:7619
#define SCU_NMICON_NMIPLL_Msk
Definition: tle987x.h:9221
#define SCU_IRCON0CLR_EXINT2FC_Msk
Definition: tle987x.h:9007
#define CPU_NVIC_ISER0_Int_ADC1_Pos
Definition: tle987x.h:7745
#define SCU_NMICON_NMISUP_Pos
Definition: tle987x.h:9208
#define CPU_NVIC_ICER0_Int_CCU6SR0_Msk
Definition: tle987x.h:7642
#define SCU_NMICLR_NMINVMC_Pos
Definition: tle987x.h:9201
#define CPU_NVIC_ICER0_Int_GPT1_Msk
Definition: tle987x.h:7650
#define CPU_NVIC_ISER0_Int_GPT2_Msk
Definition: tle987x.h:7750
#define CPU_NVIC_ICER0_Int_EXINT1_Pos
Definition: tle987x.h:7623
#define SCU_EDCSCLR_RDBEC_Msk
Definition: tle987x.h:8913
#define SCU_NMICLR_NMIECCC_Msk
Definition: tle987x.h:9194
#define CPU_NVIC_ICER0_Int_ADC2_Msk
Definition: tle987x.h:7646
#define CPU_NVIC_ISER0_Int_SSC1_Pos
Definition: tle987x.h:7735
#define CPU_NVIC_ICER0_Int_BDRV_Msk
Definition: tle987x.h:7622
#define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Msk
Definition: tle987x.h:9669
#define CPU_NVIC_ISER0_Int_ADC2_Pos
Definition: tle987x.h:7747
#define CPU_NVIC_ISER0_Int_CCU6SR3_Pos
Definition: tle987x.h:7737
#define SCU_NMICLR_NMIOWDC_Msk
Definition: tle987x.h:9198
#define CPU_NVIC_ISER0_Int_UART2_Msk
Definition: tle987x.h:7730
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Pos
Definition: tle987x.h:9576
#define SCU_NMICON_NMIPLL_Pos
Definition: tle987x.h:9220
#define SCU_IRCON0CLR_EXINT0FC_Pos
Definition: tle987x.h:9014
#define SCU_NMICON_NMIWDT_Msk
Definition: tle987x.h:9223
#define CPU_NVIC_ICER0_Int_UART1_Msk
Definition: tle987x.h:7630
#define SCU_EDCCON_NVMIE_Msk
Definition: tle987x.h:8904
#define SCU_NMICLR_NMIOTC_Msk
Definition: tle987x.h:9200
#define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Pos
Definition: tle987x.h:9664
#define SCU_IEN0_EA_Pos
Definition: tle987x.h:8982
#define CPU_NVIC_ICER0_Int_GPT2_Msk
Definition: tle987x.h:7648
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Pos
Definition: tle987x.h:9580
#define CPU_NVIC_ICER0_Int_CCU6SR1_Pos
Definition: tle987x.h:7639
#define SCU_NMICLR_NMIPLLC_Msk
Definition: tle987x.h:9204
#define CPU_NVIC_ICER0_Int_ADC2_Pos
Definition: tle987x.h:7645
#define SCU_NMICON_NMIWDT_Pos
Definition: tle987x.h:9222
#define SCU_NMICLR_NMIMAPC_Pos
Definition: tle987x.h:9195
#define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Pos
Definition: tle987x.h:9670
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Msk
Definition: tle987x.h:9575
#define SCU_EDCCON_RIE_Pos
Definition: tle987x.h:8905
#define SCU_NMICLR_NMINVMC_Msk
Definition: tle987x.h:9202
#define CPU_NVIC_ICER0_Int_DMA_Msk
Definition: tle987x.h:7620
#define CPU_NVIC_ICER0_Int_UART2_Pos
Definition: tle987x.h:7627
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Msk
Definition: tle987x.h:9573
#define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Pos
Definition: tle987x.h:9674
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Msk
Definition: tle987x.h:9577
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Msk
Definition: tle987x.h:9571
#define SCU_NMICLR_NMIECCC_Pos
Definition: tle987x.h:9193
#define CPU_NVIC_ICER0_Int_CCU6SR2_Pos
Definition: tle987x.h:7637
#define SCU_NMICLR_NMIPLLC_Pos
Definition: tle987x.h:9203
#define CPU_NVIC_ISER0_Int_DMA_Msk
Definition: tle987x.h:7722
#define CPU_NVIC_ICER0_Int_EXINT1_Msk
Definition: tle987x.h:7624
#define CPU_NVIC_ICER0_Int_SSC2_Msk
Definition: tle987x.h:7632
#define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Pos
Definition: tle987x.h:9672
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Pos
Definition: tle987x.h:9570
#define SCU_NMICLR_NMIWDTC_Msk
Definition: tle987x.h:9206
#define CPU_NVIC_ICER0_Int_CCU6SR0_Pos
Definition: tle987x.h:7641
#define SCU_EDCSCLR_NVMDBEC_Pos
Definition: tle987x.h:8910
#define SCU_NMICON_NMIOT_Msk
Definition: tle987x.h:9217
#define CPU_NVIC_ISER0_Int_EXINT0_Msk
Definition: tle987x.h:7728
#define CPU_NVIC_ISER0_Int_UART1_Pos
Definition: tle987x.h:7731
#define SCU_NMICLR_NMIWDTC_Pos
Definition: tle987x.h:9205
#define CPU_NVIC_ISER0_Int_CCU6SR1_Pos
Definition: tle987x.h:7741
#define SCU_NMICON_NMIECC_Pos
Definition: tle987x.h:9210
#define SCU_IEN0_EA_Msk
Definition: tle987x.h:8983
#define CPU_NVIC_ISER0_Int_CCU6SR3_Msk
Definition: tle987x.h:7738
#define SCU_NMICON_NMIMAP_Msk
Definition: tle987x.h:9213
#define CPU_NVIC_ICER0_Int_CCU6SR3_Pos
Definition: tle987x.h:7635
INLINE void EXINT2_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT2.
Definition: int.h:579
#define SCU_EXICON0_EXINT0_RE_Msk
External Interrupt 0 Rising Edge Bit Mask.
Definition: int.h:99
INLINE void NVIC_Node2_Dis(void)
Disables the NVIC node 2 (Int_ADC2)
Definition: int.h:1325
INLINE void NMI_PLL_Int_Dis(void)
disables PLL Loss of Lock NMI.
Definition: int.h:824
INLINE void EXINT0_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT0.
Definition: int.h:646
INLINE void INT_Enable_Global_Int(void)
enables the global interrupt IEN0.EA
Definition: int.h:2039
INLINE void NMI_MAP_Int_Dis(void)
disables NVM Map Error NMI.
Definition: int.h:967
INLINE void NVIC_Node8_Dis(void)
Disables the NVIC node 8 (Int_SSC1)
Definition: int.h:1433
INLINE void NMI_WDT_Int_Dis(void)
disables Watchdog Timer NMI.
Definition: int.h:779
INLINE void BEMF_Phase_W_Hi_Int_Dis(void)
disables Phase W Zero Crossing Comparator High Interrupt.
Definition: int.h:1787
INLINE void NMI_PLL_Int_Clr(void)
clears PLL Loss of Lock NMI Flag.
Definition: int.h:1142
#define SCU_EXICON0_EXINT0_FE_Pos
External Interrupt 0 Falling Edge Bit Position.
Definition: int.h:101
INLINE void EXINT1_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT1.
Definition: int.h:668
INLINE void BEMF_Phase_U_Lo_Int_Clr(void)
clears Phase U Zero Crossing Comparator Low Interrupt flag.
Definition: int.h:1876
INLINE void NVIC_Node5_En(void)
Enables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1370
INLINE void NVIC_Node15_Dis(void)
Disables the NVIC node 15 (Int_DMA)
Definition: int.h:1561
INLINE void BEMF_Phase_V_Hi_Int_Clr(void)
clears Phase V Zero Crossing Comparator High Interrupt flag.
Definition: int.h:1898
INLINE void NVIC_Node3_En(void)
Enables the NVIC node 3 (Int_ADC1)
Definition: int.h:1334
INLINE void BEMF_Phase_V_Lo_Int_Clr(void)
clears Phase V Zero Crossing Comparator Low Interrupt flag.
Definition: int.h:1920
INLINE void ECC_NVM_DoubleBit_Int_En(void)
enables NVM Double Bit ECC Error Interrupt.
Definition: int.h:241
INLINE void NVIC_Node10_En(void)
Enables the NVIC node 10 (Int_UART1)
Definition: int.h:1460
INLINE void EXINT1_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT1.
Definition: int.h:467
INLINE void NMI_OT_Int_En(void)
enables OT NMI.
Definition: int.h:1076
#define SCU_EXICON0_EXINT2_FE_Msk
External Interrupt 2 Falling Edge Bit Mask.
Definition: int.h:119
INLINE void NVIC_Node12_En(void)
Enables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1498
INLINE void Global_Int_En(void)
enables Global Interrupt (Pending interrupt requests are not blocked from the core).
Definition: int.h:145
INLINE void EXINT0_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT0.
Definition: int.h:354
#define SCU_EXICON0_EXINT1_FE_Msk
External Interrupt 1 Falling Edge Bit Mask.
Definition: int.h:111
#define SCU_EXICON0_EXINT1_RE_Msk
External Interrupt 1 Rising Edge Bit Mask.
Definition: int.h:107
INLINE void NVIC_Node6_En(void)
Enables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1388
INLINE void NVIC_Node12_Dis(void)
Disables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1507
#define SCU_EXICON0_EXINT1_RE_Pos
External Interrupt 1 Rising Edge Bit Position.
Definition: int.h:105
INLINE void ECC_NVM_DoubleBit_Int_Clr(void)
clears NVM Double Bit ECC Error Interrupt flag.
Definition: int.h:332
INLINE void EXINT0_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT0.
Definition: int.h:624
INLINE void NVIC_Node15_En(void)
Enables the NVIC node 15 (Int_DMA)
Definition: int.h:1552
INLINE void NMI_NVM_Int_Clr(void)
clears NVM Operation Complete NMI flag.
Definition: int.h:1164
INLINE void BEMF_Phase_W_Hi_Int_En(void)
enables Phase W Zero Crossing Comparator High Interrupt.
Definition: int.h:1764
#define SCU_NMICLR_Pos
NMI Clear Bit Position.
Definition: int.h:125
INLINE void NMI_ECC_Int_Clr(void)
clears ECC Error NMI Flag.
Definition: int.h:1250
INLINE void ECC_RAM_SingleBit_Int_Clr(void)
clears RAM Single Bit Error Status.
Definition: int.h:288
#define SCU_NMISR_Msk
NMI Status Read Bit Mask.
Definition: int.h:123
INLINE void EXINT2_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT2.
Definition: int.h:712
INLINE void EXINT1_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT1.
Definition: int.h:489
INLINE void NVIC_Node1_Dis(void)
Disables the NVIC node 1 (Int_GPT2)
Definition: int.h:1307
INLINE void NMI_OT_Int_Clr(void)
clears NMI OT Flag.
Definition: int.h:1185
INLINE void NMI_SUP_Int_Dis(void)
disables Supply Prewarning NMI.
Definition: int.h:1010
INLINE void NMI_WDT_Int_En(void)
enables Watchdog Timer NMI.
Definition: int.h:756
INLINE void NVIC_Node6_Dis(void)
Disables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1397
#define SCU_EXICON0_EXINT2_RE_Pos
External Interrupt 2 Rising Edge Bit Position.
Definition: int.h:113
INLINE void NVIC_Node8_En(void)
Enables the NVIC node 8 (Int_SSC1)
Definition: int.h:1424
INLINE void NMI_WDT_Int_Clr(void)
clears Watchdog Timer NMI Flag.
Definition: int.h:1120
INLINE void EXINT2_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT2.
Definition: int.h:534
INLINE void NVIC_Node11_Dis(void)
Disables the NVIC node 11 (Int_UART2)
Definition: int.h:1488
INLINE void ECC_RAM_DoubleBit_Int_Clr(void)
clears RAM Double Bit ECC Error Interrupt flag.
Definition: int.h:310
INLINE void NVIC_Node14_En(void)
Enables the NVIC node 14 (Int_BDRV)
Definition: int.h:1534
INLINE void BEMF_Phase_U_Hi_Int_Clr(void)
clears Phase U Zero Crossing Comparator High Interrupt flag.
Definition: int.h:1854
void INT_Init(void)
Initializes the Interrupt module based on the Config Wizard for MOTIX MCU configuration.
INLINE void NVIC_Node10_Dis(void)
Disables the NVIC node 10 (Int_UART1)
Definition: int.h:1469
INLINE void NMI_OT_Int_Dis(void)
disables OT NMI.
Definition: int.h:1098
INLINE void ECC_RAM_DoubleBit_Int_En(void)
enables RAM Double Bit ECC Error Interrupt.
Definition: int.h:188
INLINE void BEMF_Phase_V_Hi_Int_En(void)
enables Phase V Zero Crossing Comparator High Interrupt.
Definition: int.h:1674
INLINE void BEMF_Phase_W_Lo_Int_En(void)
enables Phase W Zero Crossing Comparator Low Interrupt.
Definition: int.h:1809
#define SCU_EXICON0_EXINT0_FE_Msk
External Interrupt 0 Falling Edge Bit Mask.
Definition: int.h:103
INLINE void NMI_OWD_Int_Clr(void)
clears Oscillator Watchdog NMI Flag.
Definition: int.h:1207
INLINE void NMI_OWD_Int_En(void)
enables Oscillator Watchdog NMI.
Definition: int.h:1032
INLINE void EXINT2_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT2.
Definition: int.h:734
INLINE void Global_Int_Dis(void)
disables Global Interrupt (All pending interrupt requests,except NMI, are blocked from the core).
Definition: int.h:162
INLINE void NVIC_Node7_En(void)
Enables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1406
INLINE void NMI_ECC_Int_En(void)
enables ECC Error NMI.
Definition: int.h:895
INLINE void BEMF_Phase_U_Lo_Int_En(void)
enables Phase U Zero Crossing Comparator Low Interrupt.
Definition: int.h:1629
INLINE void EXINT0_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT0.
Definition: int.h:377
INLINE void NMI_NVM_Int_Dis(void)
disables NVM Operation Complete NMI.
Definition: int.h:869
INLINE void EXINT1_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT1.
Definition: int.h:444
INLINE void BEMF_Phase_U_Hi_Int_En(void)
enables Phase U Zero Crossing Comparator High Interrupt.
Definition: int.h:1584
INLINE void NVIC_Node13_En(void)
Enables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1516
INLINE void NMI_MAP_Int_En(void)
enables NVM Map Error NMI.
Definition: int.h:944
INLINE void NVIC_Node11_En(void)
Enables the NVIC node 11 (Int_UART2)
Definition: int.h:1478
INLINE void NMI_OWD_Int_Dis(void)
disables Oscillator Watchdog NMI.
Definition: int.h:1055
INLINE void EXINT1_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT1.
Definition: int.h:512
INLINE void NMI_MAP_Int_Clr(void)
clears NVM Map Error NMI Flag.
Definition: int.h:1229
INLINE void NVIC_Node5_Dis(void)
Disables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1379
INLINE void NVIC_Node3_Dis(void)
Disables the NVIC node 3 (Int_ADC1)
Definition: int.h:1343
INLINE void NVIC_Node4_En(void)
Enables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1352
INLINE void NVIC_Node9_En(void)
Enables the NVIC node 9 (Int_SSC2)
Definition: int.h:1442
INLINE void NVIC_Node9_Dis(void)
Disables the NVIC node 9 (Int_SSC2)
Definition: int.h:1451
INLINE void NVIC_Node13_Dis(void)
Disables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1525
INLINE void BEMF_Phase_W_Lo_Int_Dis(void)
disables Phase W Zero Crossing Comparator Low Interrupt.
Definition: int.h:1832
#define SCU_NMISR_Pos
NMI Status Read Bit Position.
Definition: int.h:121
INLINE void EXINT2_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT2.
Definition: int.h:557
#define SCU_NMICLR_Msk
NMI Clear Bit Mask.
Definition: int.h:127
#define SCU_EXICON0_EXINT1_FE_Pos
External Interrupt 1 Falling Edge Bit Position.
Definition: int.h:109
INLINE void NVIC_Node2_En(void)
Enables the NVIC node 2 (Int_ADC2)
Definition: int.h:1316
#define SCU_EXICON0_EXINT2_FE_Pos
External Interrupt 2 Falling Edge Bit Position.
Definition: int.h:117
INLINE void BEMF_Phase_V_Lo_Int_Dis(void)
disables Phase V Zero Crossing Comparator Low Interrupt.
Definition: int.h:1742
INLINE uint8 INT_Get_NMI_Status(void)
Reads out the NMI Status.
Definition: int.h:2003
INLINE void BEMF_Phase_U_Lo_Int_Dis(void)
disables Phase U Zero Crossing Comparator Low Interrupt.
Definition: int.h:1652
INLINE void BEMF_Phase_W_Lo_Int_Clr(void)
clears Phase W Zero Crossing Comparator Low Interrupt flag.
Definition: int.h:1964
INLINE void ECC_RAM_DoubleBit_Int_Dis(void)
disables RAM Double Bit ECC Error Interrupt.
Definition: int.h:215
INLINE void EXINT0_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT0.
Definition: int.h:399
INLINE void EXINT0_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT0.
Definition: int.h:422
INLINE void NMI_SUP_Int_Clr(void)
clears Supply Prewarning NMI Flag.
Definition: int.h:1271
INLINE void NVIC_Node14_Dis(void)
Disables the NVIC node 14 (Int_BDRV)
Definition: int.h:1543
INLINE void NMI_NVM_Int_En(void)
enables NVM Operation Complete NMI.
Definition: int.h:846
#define SCU_EXICON0_EXINT2_RE_Msk
External Interrupt 2 Rising Edge Bit Mask.
Definition: int.h:115
INLINE void NMI_ECC_Int_Dis(void)
disables ECC Error NMI.
Definition: int.h:922
INLINE void BEMF_Phase_V_Lo_Int_En(void)
enables Phase V Zero Crossing Comparator Low Interrupt.
Definition: int.h:1719
INLINE void NVIC_Node7_Dis(void)
Disables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1415
INLINE void ECC_NVM_DoubleBit_Int_Dis(void)
disables NVM Double Bit ECC Error Interrupt.
Definition: int.h:268
INLINE void BEMF_Phase_U_Hi_Int_Dis(void)
disables Phase U Zero Crossing Comparator High Interrupt.
Definition: int.h:1607
INLINE void BEMF_Phase_V_Hi_Int_Dis(void)
disables Phase V Zero Crossing Comparator High Interrupt.
Definition: int.h:1697
INLINE void NVIC_Node1_En(void)
Enables the NVIC node 1 (Int_GPT2)
Definition: int.h:1298
INLINE void NMI_PLL_Int_En(void)
enables PLL Loss of Lock NMI.
Definition: int.h:801
INLINE void NVIC_Node0_Dis(void)
Disables the NVIC node 0 (Int_GPT1)
Definition: int.h:1289
INLINE void EXINT1_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT1.
Definition: int.h:690
INLINE void NVIC_Node4_Dis(void)
Disables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1361
INLINE void NMI_SUP_Int_En(void)
enables Supply Prewarning NMI.
Definition: int.h:988
INLINE void EXINT2_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT2.
Definition: int.h:602
INLINE void INT_Disable_Global_Int(void)
disables the global interrupt IEN0.EA
Definition: int.h:2056
INLINE void NVIC_Node0_En(void)
Enables the NVIC node 0 (Int_GPT1)
Definition: int.h:1280
INLINE void BEMF_Phase_W_Hi_Int_Clr(void)
clears Phase W Zero Crossing Comparator High Interrupt flag.
Definition: int.h:1942
#define SCU_EXICON0_EXINT0_RE_Pos
External Interrupt 0 Rising Edge Bit Position.
Definition: int.h:97
INLINE void INT_Clr_NMI_Status(uint8 Flags)
Clears the NMI Status flags.
Definition: int.h:2022
SFR low level access library.
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:322
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:347
INLINE uint8 u8_Field_Rd8(const volatile uint8 *reg, uint8 pos, uint8 msk)
This function reads a 8-bit field of a 8-bit register.
Definition: sfr_access.h:397
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:332
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
CMSIS register HeaderFile.
Device specific memory layout defines.
General type declarations.
#define INLINE
Definition: types.h:132
uint8_t uint8
8 bit unsigned value
Definition: types.h:137
uint32_t uint32
32 bit unsigned value
Definition: types.h:139