Infineon MOTIX™ MCU TLE987x Device Family SDK
Data Fields
PMU_Type Struct Reference

Detailed Description

Power Management Unit (PMU)

#include <tle987x.h>

Data Fields

union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   LIN_WAKE: 1
 
      __IM uint8_t   MON_WAKE: 1
 
      __IM uint8_t   GPIO0: 1
 
      __IM uint8_t   GPIO1: 1
 
      __IM uint8_t   CYC_WAKE: 1
 
      __IM uint8_t   FAIL: 1
 
   }   bit
 
WAKE_STATUS
 
__IM uint8_t RESERVED [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   PMU_1V5_OVERVOLT: 1
 
      __IM uint8_t   PMU_1V5_OVERLOAD: 1
 
      __IOM uint8_t   PMU_1V5_FAIL_EN: 1
 
      __IM   uint8_t: 1
 
      __IM uint8_t   PMU_5V_OVERVOLT: 1
 
      __IM uint8_t   PMU_5V_OVERLOAD: 1
 
      __IOM uint8_t   PMU_5V_FAIL_EN: 1
 
   }   bit
 
PMU_SUPPLY_STS
 
__IM uint8_t RESERVED1 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   ENABLE: 1
 
      __IOM uint8_t   CYC_EN: 1
 
      __IOM uint8_t   FAIL_EN: 1
 
      __IOM uint8_t   SHORT: 1
 
      __IOM uint8_t   OVERVOLT: 1
 
      __IOM uint8_t   OVERLOAD: 1
 
      __IM uint8_t   OK: 1
 
      __IM uint8_t   STABLE: 1
 
   }   bit
 
VDDEXT_CTRL
 
__IM uint8_t RESERVED2 [7]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   SYS_FAIL: 1
 
      __IOM uint8_t   PMU_WAKE: 1
 
      __IOM uint8_t   PMU_SleepEX: 1
 
      __IOM uint8_t   PMU_LPR: 1
 
      __IOM uint8_t   PMU_ClkWDT: 1
 
      __IOM uint8_t   PMU_ExtWDT: 1
 
      __IOM uint8_t   PMU_PIN: 1
 
      __IOM uint8_t   PMU_1V5DidPOR: 1
 
   }   bit
 
PMU_RESET_STS1
 
__IM uint8_t RESERVED3 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PMU_IntWDT: 1
 
      __IOM uint8_t   PMU_SOFT: 1
 
      __IOM uint8_t   LOCKUP: 1
 
   }   bit
 
PMU_RESET_STS2
 
__IM uint8_t RESERVED4 [11]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   WAKE_W_RST: 1
 
      __IOM uint8_t   EN_0V9_N: 1
 
      __IOM uint8_t   CYC_WAKE_EN: 1
 
      __IOM uint8_t   CYC_SENSE_EN: 1
 
      __IM   uint8_t: 3
 
      __IOM uint8_t   EN_VDDEXT_OC_OFF_N: 1
 
   }   bit
 
CNF_PMU_SETTINGS
 
__IM uint8_t RESERVED5 [7]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   M03: 4
 
      __IOM uint8_t   E01: 2
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   OSC_100kHz_EN: 1
 
   }   bit
 
CNF_CYC_SENSE
 
__IM uint8_t RESERVED6 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   M03: 4
 
      __IOM uint8_t   E01: 2
 
   }   bit
 
CNF_CYC_WAKE
 
__IM uint8_t RESERVED7 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   M03: 4
 
   }   bit
 
CNF_CYC_SAMPLE_DEL
 
__IM uint8_t RESERVED9 [31]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 7
 
      __IOM uint8_t   LIN_EN: 1
 
   }   bit
 
LIN_WAKE_EN
 
__IM uint8_t RESERVED10 [27]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   RST_TFB: 2
 
   }   bit
 
CNF_RST_TFB
 
__IM uint8_t RESERVED11 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   SUPP_SHORT: 1
 
      __IOM uint8_t   SUPP_TMOUT: 1
 
      __IOM uint8_t   PMU_1V5_OVL: 1
 
      __IOM uint8_t   PMU_5V_OVL: 1
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   SYS_OT: 1
 
      __IOM uint8_t   WDT1_SEQ_FAIL: 1
 
   }   bit
 
SYS_FAIL_STS
 
__IM uint8_t RESERVED12 [15]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   SUPPFAIL: 1
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   VDDEXTSHORT: 1
 
   }   bit
 
WAKE_STS_FAIL
 
__IM uint8_t RESERVED13 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   WAKE_STS: 1
 
   }   bit
 
WAKE_STS_MON
 
__IM uint8_t RESERVED14 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   GPIO0_STS_0: 1
 
      __IM uint8_t   GPIO0_STS_1: 1
 
      __IM uint8_t   GPIO0_STS_2: 1
 
      __IM uint8_t   GPIO0_STS_3: 1
 
      __IM uint8_t   GPIO0_STS_4: 1
 
   }   bit
 
WAKE_STS_GPIO0
 
__IM uint8_t RESERVED15 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   GPIO1_STS_0: 1
 
      __IM uint8_t   GPIO1_STS_1: 1
 
      __IM uint8_t   GPIO1_STS_2: 1
 
      __IM uint8_t   GPIO1_STS_3: 1
 
      __IM uint8_t   GPIO1_STS_4: 1
 
   }   bit
 
WAKE_STS_GPIO1
 
__IM uint8_t RESERVED16 [31]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   CNF_LIN_FT: 1
 
      __IOM uint8_t   CNF_MON_FT: 1
 
      __IOM uint8_t   CNF_GPIO_FT: 2
 
   }   bit
 
CNF_WAKE_FILTER
 
__IM uint8_t RESERVED17 [19]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   DATA0: 8
 
   }   bit
 
GPUDATA00
 
__IM uint8_t RESERVED18 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   DATA1: 8
 
   }   bit
 
GPUDATA01
 
__IM uint8_t RESERVED19 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   DATA2: 8
 
   }   bit
 
GPUDATA02
 
__IM uint8_t RESERVED20 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   DATA3: 8
 
   }   bit
 
GPUDATA03
 
__IM uint8_t RESERVED21 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   DATA4: 8
 
   }   bit
 
GPUDATA04
 
__IM uint8_t RESERVED22 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   DATA5: 8
 
   }   bit
 
GPUDATA05
 
__IM uint8_t RESERVED23 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPIO0_RI_0: 1
 
      __IOM uint8_t   GPIO0_RI_1: 1
 
      __IOM uint8_t   GPIO0_RI_2: 1
 
      __IOM uint8_t   GPIO0_RI_3: 1
 
      __IOM uint8_t   GPIO0_RI_4: 1
 
   }   bit
 
WAKE_CONF_GPIO0_RISE
 
__IM uint8_t RESERVED24 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPIO0_FA_0: 1
 
      __IOM uint8_t   GPIO0_FA_1: 1
 
      __IOM uint8_t   GPIO0_FA_2: 1
 
      __IOM uint8_t   GPIO0_FA_3: 1
 
      __IOM uint8_t   GPIO0_FA_4: 1
 
   }   bit
 
WAKE_CONF_GPIO0_FALL
 
__IM uint8_t RESERVED25 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPIO0_CYC_0: 1
 
      __IOM uint8_t   GPIO0_CYC_1: 1
 
      __IOM uint8_t   GPIO0_CYC_2: 1
 
      __IOM uint8_t   GPIO0_CYC_3: 1
 
      __IOM uint8_t   GPIO0_CYC_4: 1
 
   }   bit
 
WAKE_CONF_GPIO0_CYC
 
__IM uint8_t RESERVED26 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPIO1_RI_0: 1
 
      __IOM uint8_t   GPIO1_RI_1: 1
 
      __IOM uint8_t   GPIO1_RI_2: 1
 
      __IOM uint8_t   GPIO1_RI_3: 1
 
      __IOM uint8_t   GPIO1_RI_4: 1
 
   }   bit
 
WAKE_CONF_GPIO1_RISE
 
__IM uint8_t RESERVED27 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPIO1_FA_0: 1
 
      __IOM uint8_t   GPIO1_FA_1: 1
 
      __IOM uint8_t   GPIO1_FA_2: 1
 
      __IOM uint8_t   GPIO1_FA_3: 1
 
      __IOM uint8_t   GPIO1_FA_4: 1
 
   }   bit
 
WAKE_CONF_GPIO1_FALL
 
__IM uint8_t RESERVED28 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPIO1_CYC_0: 1
 
      __IOM uint8_t   GPIO1_CYC_1: 1
 
      __IOM uint8_t   GPIO1_CYC_2: 1
 
      __IOM uint8_t   GPIO1_CYC_3: 1
 
      __IOM uint8_t   GPIO1_CYC_4: 1
 
   }   bit
 
WAKE_CONF_GPIO1_CYC
 
__IM uint8_t RESERVED29 [487]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   MBIST_EN: 1
 
   }   bit
 
SystemStartConfig
 

Field Documentation

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union { ... } CNF_CYC_SAMPLE_DEL

◆ 

union { ... } CNF_CYC_SENSE

◆ 

union { ... } CNF_CYC_WAKE

◆ CNF_GPIO_FT

__IOM uint8_t CNF_GPIO_FT

[3..2] Wake-up Filter time for General Purpose IO

◆ CNF_LIN_FT

__IOM uint8_t CNF_LIN_FT

[0..0] Wake-up Filter time for LIN WAKE

◆ CNF_MON_FT

__IOM uint8_t CNF_MON_FT

[1..1] Wake-up Filter time for Monitoring Inputs

◆ 

union { ... } CNF_PMU_SETTINGS

◆ 

union { ... } CNF_RST_TFB

◆ 

union { ... } CNF_WAKE_FILTER

◆ CYC_EN

__IOM uint8_t CYC_EN

[1..1] VDDEXT Supply for Cyclic Sense Enable

◆ CYC_SENSE_EN

__IOM uint8_t CYC_SENSE_EN

[3..3] Enabling Cyclic Sense

◆ CYC_WAKE

__IM uint8_t CYC_WAKE

[4..4] Wake-up caused by Cyclic Wake

◆ CYC_WAKE_EN

__IOM uint8_t CYC_WAKE_EN

[2..2] Enabling Cyclic Wake

◆ DATA0

__IOM uint8_t DATA0

[7..0] DATA0 Storage Byte

◆ DATA1

__IOM uint8_t DATA1

[7..0] DATA1 Storage Byte

◆ DATA2

__IOM uint8_t DATA2

[7..0] DATA2 Storage Byte

◆ DATA3

__IOM uint8_t DATA3

[7..0] DATA3 Storage Byte

◆ DATA4

__IOM uint8_t DATA4

[7..0] DATA4 Storage Byte

◆ DATA5

__IOM uint8_t DATA5

[7..0] DATA5 Storage Byte

◆ E01

[5..4] Exponent

◆ EN_0V9_N

__IOM uint8_t EN_0V9_N

[1..1] Disables the reduction of the VDDC regulator output to 0.9 V during Stop-Mode

◆ EN_VDDEXT_OC_OFF_N

__IOM uint8_t EN_VDDEXT_OC_OFF_N

[7..7] Disabling VDDEXT Shutdown in Overload Condition

◆ ENABLE

__IOM uint8_t ENABLE

[0..0] VDDEXT Supply Enable

◆ FAIL

__IM uint8_t FAIL

[5..5] Wake-up after VDDEXT Fail

◆ FAIL_EN

__IOM uint8_t FAIL_EN

[2..2] Enabling of VDDEXT Supply status information as interrupt source

◆ GPIO0

__IM uint8_t GPIO0

[2..2] Wake-up via GPIO0 which is a logical OR combination of all Wake_STS_GPIO0 bits

◆ GPIO0_CYC_0

__IOM uint8_t GPIO0_CYC_0

[0..0] GPIO0_0 input for cycle sense enable

◆ GPIO0_CYC_1

__IOM uint8_t GPIO0_CYC_1

[1..1] GPIO0_1 input for cycle sense enable

◆ GPIO0_CYC_2

__IOM uint8_t GPIO0_CYC_2

[2..2] GPIO0_2 input for cycle sense enable

◆ GPIO0_CYC_3

__IOM uint8_t GPIO0_CYC_3

[3..3] GPIO0_3 input for cycle sense enable

◆ GPIO0_CYC_4

__IOM uint8_t GPIO0_CYC_4

[4..4] GPIO0_4 input for cycle sense enable

◆ GPIO0_FA_0

__IOM uint8_t GPIO0_FA_0

[0..0] Port 0_0 Wake-up on Falling Edge enable

◆ GPIO0_FA_1

__IOM uint8_t GPIO0_FA_1

[1..1] Port 0_1 Wake-up on Falling Edge enable

◆ GPIO0_FA_2

__IOM uint8_t GPIO0_FA_2

[2..2] Port 0_2 Wake-up on Falling Edge enable

◆ GPIO0_FA_3

__IOM uint8_t GPIO0_FA_3

[3..3] Port 0_3 Wake-up on Falling Edge enable

◆ GPIO0_FA_4

__IOM uint8_t GPIO0_FA_4

[4..4] Port 0_4 Wake-up on Falling Edge enable

◆ GPIO0_RI_0

__IOM uint8_t GPIO0_RI_0

[0..0] Port 0_0 Wake-up on Rising Edge enable

◆ GPIO0_RI_1

__IOM uint8_t GPIO0_RI_1

[1..1] Port 0_1 Wake-up on Rising Edge enable

◆ GPIO0_RI_2

__IOM uint8_t GPIO0_RI_2

[2..2] Port 0_2 Wake-up on Rising Edge enable

◆ GPIO0_RI_3

__IOM uint8_t GPIO0_RI_3

[3..3] Port 0_3 Wake-up on Rising Edge enable

◆ GPIO0_RI_4

__IOM uint8_t GPIO0_RI_4

[4..4] Port 0_4 Wake-up on Rising Edge enable

◆ GPIO0_STS_0

__IM uint8_t GPIO0_STS_0

[0..0] Status of GPIO0_0

◆ GPIO0_STS_1

__IM uint8_t GPIO0_STS_1

[1..1] Status of GPIO0_1

◆ GPIO0_STS_2

__IM uint8_t GPIO0_STS_2

[2..2] Status of GPIO0_2

◆ GPIO0_STS_3

__IM uint8_t GPIO0_STS_3

[3..3] Status of GPIO0_3

◆ GPIO0_STS_4

__IM uint8_t GPIO0_STS_4

[4..4] Status of GPIO0_4

◆ GPIO1

__IM uint8_t GPIO1

[3..3] Wake-up via GPIO1 which is a logical OR combination of all Wake_STS_GPIO1 bits

◆ GPIO1_CYC_0

__IOM uint8_t GPIO1_CYC_0

[0..0] GPIO1_0 input for cycle sense enable

◆ GPIO1_CYC_1

__IOM uint8_t GPIO1_CYC_1

[1..1] GPIO1_1 input for cycle sense enable

◆ GPIO1_CYC_2

__IOM uint8_t GPIO1_CYC_2

[2..2] GPIO1_2 input for cycle sense enable

◆ GPIO1_CYC_3

__IOM uint8_t GPIO1_CYC_3

[3..3] GPIO1_3 input for cycle sense enable

◆ GPIO1_CYC_4

__IOM uint8_t GPIO1_CYC_4

[4..4] GPIO1_4 input for cycle sense enable

◆ GPIO1_FA_0

__IOM uint8_t GPIO1_FA_0

[0..0] Port 1_0 Wake-up on Falling Edge enable

◆ GPIO1_FA_1

__IOM uint8_t GPIO1_FA_1

[1..1] Port 1_1 Wake-up on Falling Edge enable

◆ GPIO1_FA_2

__IOM uint8_t GPIO1_FA_2

[2..2] Port 1_2 Wake-up on Falling Edge enable

◆ GPIO1_FA_3

__IOM uint8_t GPIO1_FA_3

[3..3] Port 1_3 Wake-up on Falling Edge enable

◆ GPIO1_FA_4

__IOM uint8_t GPIO1_FA_4

[4..4] Port 1_4 Wake-up on Falling Edge enable

◆ GPIO1_RI_0

__IOM uint8_t GPIO1_RI_0

[0..0] Port 1_0 Wake-up on Rising Edge enable

◆ GPIO1_RI_1

__IOM uint8_t GPIO1_RI_1

[1..1] Port 1_1 Wake-up on Rising Edge enable

◆ GPIO1_RI_2

__IOM uint8_t GPIO1_RI_2

[2..2] Port 1_2 Wake-up on Rising Edge enable

◆ GPIO1_RI_3

__IOM uint8_t GPIO1_RI_3

[3..3] Port 1_3 Wake-up on Rising Edge enable

◆ GPIO1_RI_4

__IOM uint8_t GPIO1_RI_4

[4..4] Port 1_4 Wake-up on Rising Edge enable

◆ GPIO1_STS_0

__IM uint8_t GPIO1_STS_0

[0..0] Wake GPIO1_0

◆ GPIO1_STS_1

__IM uint8_t GPIO1_STS_1

[1..1] Wake GPIO1_1

◆ GPIO1_STS_2

__IM uint8_t GPIO1_STS_2

[2..2] Wake GPIO1_2

◆ GPIO1_STS_3

__IM uint8_t GPIO1_STS_3

[3..3] Wake GPIO1_3

◆ GPIO1_STS_4

__IM uint8_t GPIO1_STS_4

[4..4] Wake GPIO1_4

◆ 

union { ... } GPUDATA00

◆ 

union { ... } GPUDATA01

◆ 

union { ... } GPUDATA02

◆ 

union { ... } GPUDATA03

◆ 

union { ... } GPUDATA04

◆ 

union { ... } GPUDATA05

◆ LIN_EN

__IOM uint8_t LIN_EN

[7..7] Lin Wake enable

◆ LIN_WAKE

__IM uint8_t LIN_WAKE

[0..0] Wake-up via LIN- Message

◆ 

union { ... } LIN_WAKE_EN

◆ LOCKUP

__IOM uint8_t LOCKUP

[2..2] Lockup-Reset Flag

◆ M03

[3..0] Mantissa

◆ MBIST_EN

__IOM uint8_t MBIST_EN

[0..0] System Startup Configuration Bit for RAM MBIST at Sleep Mode exit

◆ MON_WAKE

__IM uint8_t MON_WAKE

[1..1] Wake-up via MON

◆ OK

[6..6] VDDEXT Supply works inside its specified range 2

◆ OSC_100kHz_EN

__IOM uint8_t OSC_100kHz_EN

[7..7] 100 kHz Oscillator Enable

◆ OVERLOAD

__IOM uint8_t OVERLOAD

[5..5] VDDEXT Supply Overload

◆ OVERVOLT

__IOM uint8_t OVERVOLT

[4..4] VDDEXT Supply Overvoltage

◆ PMU_1V5_FAIL_EN

__IOM uint8_t PMU_1V5_FAIL_EN

[2..2] Enabling of VDDC status information as interrupt source

◆ PMU_1V5_OVERLOAD

__IM uint8_t PMU_1V5_OVERLOAD

[1..1] Overload at VDDC regulator

◆ PMU_1V5_OVERVOLT

__IM uint8_t PMU_1V5_OVERVOLT

[0..0] Overvoltage at VDDC regulator

◆ PMU_1V5_OVL

__IOM uint8_t PMU_1V5_OVL

[2..2] VDDC Overload Flag

◆ PMU_1V5DidPOR

__IOM uint8_t PMU_1V5DidPOR

[7..7] Power-On Reset Flag

◆ PMU_5V_FAIL_EN

__IOM uint8_t PMU_5V_FAIL_EN

[6..6] Enabling of VDDP status information as interrupt source

◆ PMU_5V_OVERLOAD

__IM uint8_t PMU_5V_OVERLOAD

[5..5] Overload at VDDP regulator

◆ PMU_5V_OVERVOLT

__IM uint8_t PMU_5V_OVERVOLT

[4..4] Overvoltage at VDDP regulator

◆ PMU_5V_OVL

__IOM uint8_t PMU_5V_OVL

[3..3] VDDP Overload Flag

◆ PMU_ClkWDT

__IOM uint8_t PMU_ClkWDT

[4..4] Clock Watchdog (CLKWDT) Reset Flag

◆ PMU_ExtWDT

__IOM uint8_t PMU_ExtWDT

[5..5] External Watchdog (WDT1) Reset Flag

◆ PMU_IntWDT

__IOM uint8_t PMU_IntWDT

[0..0] Internal Watchdog Reset Flag

◆ PMU_LPR

__IOM uint8_t PMU_LPR

[3..3] Low Priority Resets (see PMU_RESET_STS2)

◆ PMU_PIN

__IOM uint8_t PMU_PIN

[6..6] PIN-Reset Flag

◆ 

union { ... } PMU_RESET_STS1

◆ 

union { ... } PMU_RESET_STS2

◆ PMU_SleepEX

__IOM uint8_t PMU_SleepEX

[2..2] Flag which indicates a reset caused by Sleep-Exit

◆ PMU_SOFT

__IOM uint8_t PMU_SOFT

[1..1] Soft-Reset Flag

◆ 

union { ... } PMU_SUPPLY_STS

◆ PMU_WAKE

__IOM uint8_t PMU_WAKE

[1..1] Flag which indicates a reset caused by Stop-Exit

◆ reg

(@ 0x00000000) Main wake status register

(@ 0x00000004) Voltage Reg Status Register

(@ 0x00000008) VDDEXT Control

(@ 0x00000010) Reset Status Hard Register

(@ 0x00000014) Reset Status Soft Register

(@ 0x00000020) PMU Settings Register

(@ 0x00000028) Dead Time in Cyclic Sense Register

(@ 0x0000002C) Dead Time in Cyclic Wake Register

(@ 0x00000030) Sample Delay in Cyclic Sense Register

(@ 0x00000050) LIN Wake Enable

(@ 0x0000006C) Reset Blind Time Register

(@ 0x00000070) System Fail Status Register

(@ 0x00000080) Wake Status Fail Register

(@ 0x00000084) Wake Source MON Input Register

(@ 0x00000088) Wake Status GPIO 0 Register

(@ 0x0000008C) Wake Status GPIO 1 Register

(@ 0x000000AC) PMU Wake-up Timing Register

(@ 0x000000C0) General Purpose User DATA0

(@ 0x000000C4) General Purpose User DATA1

(@ 0x000000C8) General Purpose User DATA2

(@ 0x000000CC) General Purpose User DATA3

(@ 0x000000D0) General Purpose User DATA4

(@ 0x000000D4) General Purpose User DATA5

(@ 0x000000D8) Wake Configuration GPIO Port 0 Rising Edge Register

(@ 0x000000DC) Wake Configuration GPIO Port 0 Falling Edge Register

(@ 0x000000E0) Wake Port 0 Cycle Enabled Register

(@ 0x000000E4) Wake Configuration GPIO Port 1 Rising Edge Register

(@ 0x000000E8) Wake Configuration GPIO Port 1 Falling Edge Register

(@ 0x000000EC) Wake Port 1 Cycle Enabled Register

(@ 0x000002D4) System Startup Config

◆ RESERVED

__IM uint8_t RESERVED[3]

◆ RESERVED1

__IM uint8_t RESERVED1[3]

◆ RESERVED10

__IM uint8_t RESERVED10[27]

◆ RESERVED11

__IM uint8_t RESERVED11[3]

◆ RESERVED12

__IM uint8_t RESERVED12[15]

◆ RESERVED13

__IM uint8_t RESERVED13[3]

◆ RESERVED14

__IM uint8_t RESERVED14[3]

◆ RESERVED15

__IM uint8_t RESERVED15[3]

◆ RESERVED16

__IM uint8_t RESERVED16[31]

◆ RESERVED17

__IM uint8_t RESERVED17[19]

◆ RESERVED18

__IM uint8_t RESERVED18[3]

◆ RESERVED19

__IM uint8_t RESERVED19[3]

◆ RESERVED2

__IM uint8_t RESERVED2[7]

◆ RESERVED20

__IM uint8_t RESERVED20[3]

◆ RESERVED21

__IM uint8_t RESERVED21[3]

◆ RESERVED22

__IM uint8_t RESERVED22[3]

◆ RESERVED23

__IM uint8_t RESERVED23[3]

◆ RESERVED24

__IM uint8_t RESERVED24[3]

◆ RESERVED25

__IM uint8_t RESERVED25[3]

◆ RESERVED26

__IM uint8_t RESERVED26[3]

◆ RESERVED27

__IM uint8_t RESERVED27[3]

◆ RESERVED28

__IM uint8_t RESERVED28[3]

◆ RESERVED29

__IM uint8_t RESERVED29[487]

◆ RESERVED3

__IM uint8_t RESERVED3[3]

◆ RESERVED4

__IM uint8_t RESERVED4[11]

◆ RESERVED5

__IM uint8_t RESERVED5[7]

◆ RESERVED6

__IM uint8_t RESERVED6[3]

◆ RESERVED7

__IM uint8_t RESERVED7[3]

◆ RESERVED9

__IM uint8_t RESERVED9[31]

◆ RST_TFB

__IOM uint8_t RST_TFB

[1..0] Reset Pin Blind Time Selection Bits

◆ SHORT

__IOM uint8_t SHORT

[3..3] VDDEXT Supply Shorted Output

◆ STABLE

__IM uint8_t STABLE

[7..7] VDDEXT Supply works inside its specified range 1

◆ SUPP_SHORT

__IOM uint8_t SUPP_SHORT

[0..0] Supply Short

◆ SUPP_TMOUT

__IOM uint8_t SUPP_TMOUT

[1..1] Supply Time Out

◆ SUPPFAIL

__IOM uint8_t SUPPFAIL

[0..0] Stop-Exit due to overvoltage at the VDDEXT Supply

◆ SYS_FAIL

__IOM uint8_t SYS_FAIL

[0..0] Flag which indicates a reset caused by a System Fail reported in the corresponding Fail Register

◆ 

union { ... } SYS_FAIL_STS

◆ SYS_OT

__IOM uint8_t SYS_OT

[5..5] System Overtemperature Indication Flag

◆ 

union { ... } SystemStartConfig

◆ uint8_t

__IM uint8_t

◆ 

union { ... } VDDEXT_CTRL

◆ VDDEXTSHORT

__IOM uint8_t VDDEXTSHORT

[2..2] Stop-Exit due to short circuit at the VDDEXT Supply

◆ 

union { ... } WAKE_CONF_GPIO0_CYC

◆ 

union { ... } WAKE_CONF_GPIO0_FALL

◆ 

union { ... } WAKE_CONF_GPIO0_RISE

◆ 

union { ... } WAKE_CONF_GPIO1_CYC

◆ 

union { ... } WAKE_CONF_GPIO1_FALL

◆ 

union { ... } WAKE_CONF_GPIO1_RISE

◆ 

union { ... } WAKE_STATUS

◆ WAKE_STS

__IM uint8_t WAKE_STS

[0..0] Status of MON

◆ 

union { ... } WAKE_STS_FAIL

◆ 

union { ... } WAKE_STS_GPIO0

◆ 

union { ... } WAKE_STS_GPIO1

◆ 

union { ... } WAKE_STS_MON

◆ WAKE_W_RST

__IOM uint8_t WAKE_W_RST

[0..0] Wake-up with reset execution

◆ WDT1_SEQ_FAIL

__IOM uint8_t WDT1_SEQ_FAIL

[6..6] External Watchdog (WDT1) Sequential Fail


The documentation for this struct was generated from the following file: