Infineon MOTIX™ MCU TLE987x Device Family SDK
Data Fields
ADC1_Type Struct Reference

Detailed Description

ADC1 Module (ADC1)

#include <tle987x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PD_N: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   SOC: 1
 
      __IM uint32_t   EOC: 1
 
      __IOM uint32_t   IN_MUX_SEL: 3
 
   }   bit
 
CTRL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DIVA: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   ANON: 2
 
   }   bit
 
GLOBCTR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHx: 3
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   REP: 3
 
      __IOM uint32_t   TRIG_SEL: 3
 
   }   bit
 
CHx_EIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ESM_0: 8
 
      __IM   uint32_t: 8
 
      __IOM uint32_t   TRIG_SEL: 3
 
   }   bit
 
CHx_ESM
 
__IM uint32_t RESERVED [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ1: 8
 
      __IOM uint32_t   SQ2: 8
 
      __IOM uint32_t   SQ3: 8
 
      __IOM uint32_t   SQ4: 8
 
   }   bit
 
SQ1_4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ5: 8
 
      __IOM uint32_t   SQ6: 8
 
      __IOM uint32_t   SQ7: 8
 
      __IOM uint32_t   SQ8: 8
 
   }   bit
 
SQ5_8
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ch0: 1
 
      __IOM uint32_t   ch1: 1
 
      __IOM uint32_t   ch2: 1
 
      __IOM uint32_t   ch3: 1
 
      __IOM uint32_t   ch4: 1
 
      __IOM uint32_t   ch5: 1
 
      __IOM uint32_t   ch6: 1
 
      __IOM uint32_t   ch7: 1
 
   }   bit
 
DWSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ch0: 8
 
      __IOM uint32_t   ch1: 8
 
      __IOM uint32_t   ch2: 8
 
      __IOM uint32_t   ch3: 8
 
   }   bit
 
STC_0_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ch4: 8
 
      __IOM uint32_t   ch5: 8
 
      __IOM uint32_t   ch6: 8
 
      __IOM uint32_t   ch7: 8
 
   }   bit
 
STC_4_7
 
__IM uint32_t RESERVED2 [4]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH_EIM: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR8: 1
 
      __IM uint32_t   VF8: 1
 
      __IM uint32_t   OF8: 1
 
   }   bit
 
RES_OUT_EIM
 
__IM uint32_t RESERVED3 [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 8
 
      __IOM uint32_t   SQ_RUN: 1
 
      __IM uint32_t   EIM_ACTIVE: 1
 
      __IM uint32_t   ESM_ACTIVE: 1
 
      __IM uint32_t   SQx: 3
 
      __IM uint32_t   CHx: 3
 
   }   bit
 
SQ_FB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH7: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR7: 1
 
      __IM uint32_t   VF7: 1
 
      __IM uint32_t   OF7: 1
 
   }   bit
 
RES_OUT7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH6: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR6: 1
 
      __IM uint32_t   VF6: 1
 
      __IM uint32_t   OF6: 1
 
   }   bit
 
RES_OUT6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH5: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR5: 1
 
      __IM uint32_t   VF5: 1
 
      __IM uint32_t   OF5: 1
 
   }   bit
 
RES_OUT5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH4: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR4: 1
 
      __IM uint32_t   VF4: 1
 
      __IM uint32_t   OF4: 1
 
   }   bit
 
RES_OUT4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH3: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR3: 1
 
      __IM uint32_t   VF3: 1
 
      __IM uint32_t   OF3: 1
 
   }   bit
 
RES_OUT3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH2: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR2: 1
 
      __IM uint32_t   VF2: 1
 
      __IM uint32_t   OF2: 1
 
   }   bit
 
RES_OUT2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH1: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR1: 1
 
      __IM uint32_t   VF1: 1
 
      __IM uint32_t   OF1: 1
 
   }   bit
 
RES_OUT1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH0: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR0: 1
 
      __IM uint32_t   VF0: 1
 
      __IM uint32_t   OF0: 1
 
   }   bit
 
RES_OUT0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   BUSY: 1
 
      __IM uint32_t   SAMPLE: 1
 
      __IM   uint32_t: 1
 
      __IM uint32_t   CHNR: 3
 
      __IM uint32_t   ANON_ST: 2
 
   }   bit
 
GLOBSTR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   CH0_STS: 1
 
      __IM uint32_t   CH1_STS: 1
 
      __IM uint32_t   CH2_STS: 1
 
      __IM uint32_t   CH3_STS: 1
 
      __IM uint32_t   CH4_STS: 1
 
      __IM uint32_t   CH5_STS: 1
 
      __IM uint32_t   CH6_STS: 1
 
      __IM uint32_t   CH7_STS: 1
 
      __IM uint32_t   EIM_STS: 1
 
      __IM uint32_t   ESM_STS: 1
 
   }   bit
 
IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH0_IE: 1
 
      __IOM uint32_t   CH1_IE: 1
 
      __IOM uint32_t   CH2_IE: 1
 
      __IOM uint32_t   CH3_IE: 1
 
      __IOM uint32_t   CH4_IE: 1
 
      __IOM uint32_t   CH5_IE: 1
 
      __IOM uint32_t   CH6_IE: 1
 
      __IOM uint32_t   CH7_IE: 1
 
      __IOM uint32_t   EIM_IE: 1
 
      __IOM uint32_t   ESM_IE: 1
 
   }   bit
 
IE
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CH0_ICLR: 1
 
      __OM uint32_t   CH1_ICLR: 1
 
      __OM uint32_t   CH2_ICLR: 1
 
      __OM uint32_t   CH3_ICLR: 1
 
      __OM uint32_t   CH4_ICLR: 1
 
      __OM uint32_t   CH5_ICLR: 1
 
      __OM uint32_t   CH6_ICLR: 1
 
      __OM uint32_t   CH7_ICLR: 1
 
      __OM uint32_t   EIM_ICLR: 1
 
      __OM uint32_t   ESM_ICLR: 1
 
   }   bit
 
ICLR
 

Field Documentation

◆ ANON

[9..8] Analog Part Switched On

◆ ANON_ST

__IM uint32_t ANON_ST

[9..8] Analog Part Switched On

◆  [1/23]

struct { ... } bit

◆  [2/23]

struct { ... } bit

◆  [3/23]

struct { ... } bit

◆  [4/23]

struct { ... } bit

◆  [5/23]

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◆  [6/23]

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◆  [7/23]

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◆  [8/23]

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◆  [9/23]

struct { ... } bit

◆  [10/23]

struct { ... } bit

◆  [11/23]

struct { ... } bit

◆  [12/23]

struct { ... } bit

◆  [13/23]

struct { ... } bit

◆  [14/23]

struct { ... } bit

◆  [15/23]

struct { ... } bit

◆  [16/23]

struct { ... } bit

◆  [17/23]

struct { ... } bit

◆  [18/23]

struct { ... } bit

◆  [19/23]

struct { ... } bit

◆  [20/23]

struct { ... } bit

◆  [21/23]

struct { ... } bit

◆  [22/23]

struct { ... } bit

◆  [23/23]

struct { ... } bit

◆ BUSY

__IM uint32_t BUSY

[0..0] Analog Part Busy

◆ ch0

[0..0] Data Width channel 0

[7..0] Sample Time Control for Channel 0

◆ CH0_ICLR

__OM uint32_t CH0_ICLR

[0..0] ADC1 Channel 0 Interrupt Status Clear

◆ CH0_IE

__IOM uint32_t CH0_IE

[0..0] ADC1 Channel 0 Interrupt Enable

◆ CH0_STS

__IM uint32_t CH0_STS

[0..0] ADC1 Channel 0 Interrupt Status

◆ ch1

[1..1] Data Width channel 1

[15..8] Sample Time Control for Channel 1

◆ CH1_ICLR

__OM uint32_t CH1_ICLR

[1..1] ADC1 Channel 1 Interrupt Status Clear

◆ CH1_IE

__IOM uint32_t CH1_IE

[1..1] ADC1 Channel 1 Interrupt Enable

◆ CH1_STS

__IM uint32_t CH1_STS

[1..1] ADC1 Channel 1 Interrupt Status

◆ ch2

[2..2] Data Width channel 2

[23..16] Sample Time Control for Channel 2

◆ CH2_ICLR

__OM uint32_t CH2_ICLR

[2..2] ADC1 Channel 2 Interrupt Status Clear

◆ CH2_IE

__IOM uint32_t CH2_IE

[2..2] ADC1 Channel 2 Interrupt Enable

◆ CH2_STS

__IM uint32_t CH2_STS

[2..2] ADC1 Channel 2 Interrupt Status

◆ ch3

[3..3] Data Width channel 3

[31..24] Sample Time Control for Channel 3

◆ CH3_ICLR

__OM uint32_t CH3_ICLR

[3..3] ADC1 Channel 3 Interrupt Status Clear

◆ CH3_IE

__IOM uint32_t CH3_IE

[3..3] ADC1 Channel 3 Interrupt Enable

◆ CH3_STS

__IM uint32_t CH3_STS

[3..3] ADC1 Channel 3 Interrupt Status

◆ ch4

[4..4] Data Width channel 4

[7..0] Sample Time Control for Channel 4

◆ CH4_ICLR

__OM uint32_t CH4_ICLR

[4..4] ADC1 Channel 4 Interrupt Status Clear

◆ CH4_IE

__IOM uint32_t CH4_IE

[4..4] ADC1 Channel 4 Interrupt Enable

◆ CH4_STS

__IM uint32_t CH4_STS

[4..4] ADC1 Channel 4 Interrupt Status

◆ ch5

[5..5] Data Width channel 5

[15..8] Sample Time Control for Channel 5

◆ CH5_ICLR

__OM uint32_t CH5_ICLR

[5..5] ADC1 Channel 5 Interrupt Status Clear

◆ CH5_IE

__IOM uint32_t CH5_IE

[5..5] ADC1 Channel 5 Interrupt Enable

◆ CH5_STS

__IM uint32_t CH5_STS

[5..5] ADC1 Channel 5 Interrupt Status

◆ ch6

[6..6] Data Width channel 6

[23..16] Sample Time Control for Channel 6

◆ CH6_ICLR

__OM uint32_t CH6_ICLR

[6..6] ADC1 Channel 6 Interrupt Status Clear

◆ CH6_IE

__IOM uint32_t CH6_IE

[6..6] ADC1 Channel 6 Interrupt Enable

◆ CH6_STS

__IM uint32_t CH6_STS

[6..6] ADC1 Channel 6 Interrupt Status

◆ ch7

[7..7] Data Width channel 7

[31..24] Sample Time Control for Channel 7

◆ CH7_ICLR

__OM uint32_t CH7_ICLR

[7..7] ADC1 Channel 7 Interrupt Status Clear

◆ CH7_IE

__IOM uint32_t CH7_IE

[7..7] ADC1 Channel 7 Interrupt Enable

◆ CH7_STS

__IM uint32_t CH7_STS

[7..7] ADC1 Channel 7 Interrupt Status

◆ CHNR

__IM uint32_t CHNR

[5..3] Channel Number

◆ CHx [1/2]

[2..0] Channel set for exceptional interrupt measurement (EIM)

◆ CHx [2/2]

[18..16] Current Channel

◆ 

union { ... } CHx_EIM

◆ 

union { ... } CHx_ESM

◆ 

union { ... } CTRL_STS

◆ DIVA

[5..0] Divide Factor for the Analog internal clock: 0x00=Fadci = Fadc, 0x01=Fadci = Fadc/2, 0x02=Fadci = Fadc/3, 0x02=..., 0x3F=Fadci = Fadc/64,

◆ 

union { ... } DWSEL

◆ EIM_ACTIVE

__IM uint32_t EIM_ACTIVE

[9..9] ADC1 EIM active

◆ EIM_ICLR

__OM uint32_t EIM_ICLR

[8..8] Exceptional Interrupt Measurement (EIM) Status Clear

◆ EIM_IE

__IOM uint32_t EIM_IE

[8..8] Exceptional Interrupt Measurement (EIM) Interrupt Enable

◆ EIM_STS

__IM uint32_t EIM_STS

[8..8] Exceptional Interrupt Measurement (EIM) Status

◆ EOC

[3..3] ADC1 End of Conversion (software mode)

◆ ESM_0

__IOM uint32_t ESM_0

[7..0] Channel Sequence for Exceptional Sequence Measurement (ESM)

◆ ESM_ACTIVE

__IM uint32_t ESM_ACTIVE

[10..10] ADC1 ESM active

◆ ESM_ICLR

__OM uint32_t ESM_ICLR

[9..9] Exceptional Sequence Measurement (ESM) Status Clear

◆ ESM_IE

__IOM uint32_t ESM_IE

[9..9] Exceptional Sequence Measurement (ESM) Interrupt Enable

◆ ESM_STS

__IM uint32_t ESM_STS

[9..9] Exceptional Sequence Measurement (ESM) Status

◆ 

union { ... } GLOBCTR

◆ 

union { ... } GLOBSTR

◆ 

union { ... } ICLR

◆ 

union { ... } IE

◆ IN_MUX_SEL

__IOM uint32_t IN_MUX_SEL

[6..4] Channel for software mode

◆ 

union { ... } IS

◆ OF0

[18..18] Overrun Flag

◆ OF1

[18..18] Overrun Flag

◆ OF2

[18..18] Overrun Flag

◆ OF3

[18..18] Overrun Flag

◆ OF4

[18..18] Overrun Flag

◆ OF5

[18..18] Overrun Flag

◆ OF6

[18..18] Overrun Flag

◆ OF7

[18..18] Overrun Flag

◆ OF8

[18..18] Overrun Flag

◆ OUT_CH0

__IM uint32_t OUT_CH0

[11..0] ADC1 output reset value channel 0

◆ OUT_CH1

__IM uint32_t OUT_CH1

[11..0] ADC1 output result value channel 1

◆ OUT_CH2

__IM uint32_t OUT_CH2

[11..0] ADC1 output result value channel 2

◆ OUT_CH3

__IM uint32_t OUT_CH3

[11..0] ADC1 output result value channel 3

◆ OUT_CH4

__IM uint32_t OUT_CH4

[11..0] ADC1 output result value channel 4

◆ OUT_CH5

__IM uint32_t OUT_CH5

[11..0] ADC1 output result value channel 5

◆ OUT_CH6

__IM uint32_t OUT_CH6

[11..0] ADC1 output result value channel 6

◆ OUT_CH7

__IM uint32_t OUT_CH7

[11..0] ADC1 output result value channel 7

◆ OUT_CH_EIM

__IM uint32_t OUT_CH_EIM

[11..0] ADC1 output result value EIM

◆ PD_N

[0..0] ADC1 Power Down Signal

◆ reg

(@ 0x00000000) ADC1 Control and Status Register

(@ 0x00000004) Global Control Register

(@ 0x00000008) Channel Settings Bits for Exceptional Interrupt Measurement

(@ 0x0000000C) Channel Settings Bits for Exceptional Sequence Measurement

(@ 0x00000018) Measurement Channel Enable Bits for Cycle 1 - 4

(@ 0x0000001C) Measurement Channel Enable Bits for Cycle 5 - 8

(@ 0x00000024) Measurement Channel Data Width Selection

(@ 0x00000028) Measurement Channel Sample Time Control 0 - 3

(@ 0x0000002C) Measurement Channel Sample Time Control 4 - 7

(@ 0x00000040) ADC1 Output Channel EIM

(@ 0x00000050) Sequencer Feedback Register

(@ 0x00000054) ADC1 Output Channel 7

(@ 0x00000058) ADC1 Output Channel 6

(@ 0x0000005C) ADC1 Output Channel 5

(@ 0x00000060) ADC1 Output Channel 4

(@ 0x00000064) ADC1 Output Channel 3

(@ 0x00000068) ADC1 Output Channel 2

(@ 0x0000006C) ADC1 Output Channel 1

(@ 0x00000070) ADC1 Output Channel 0

(@ 0x00000074) Global Status Register

(@ 0x00000078) ADC1 Interrupt Status Register

(@ 0x0000007C) ADC1 Interrupt Enable Register

(@ 0x00000080) ADC1 Interrupt Status Clear Register

◆ REP

[6..4] Repeat count for exceptional interrupt measurement (EIM)

◆ 

union { ... } RES_OUT0

◆ 

union { ... } RES_OUT1

◆ 

union { ... } RES_OUT2

◆ 

union { ... } RES_OUT3

◆ 

union { ... } RES_OUT4

◆ 

union { ... } RES_OUT5

◆ 

union { ... } RES_OUT6

◆ 

union { ... } RES_OUT7

◆ 

union { ... } RES_OUT_EIM

◆ RESERVED

__IM uint32_t RESERVED[2]

◆ RESERVED1

__IM uint32_t RESERVED1

◆ RESERVED2

__IM uint32_t RESERVED2[4]

◆ RESERVED3

__IM uint32_t RESERVED3[3]

◆ SAMPLE

__IM uint32_t SAMPLE

[1..1] Sample Phase Indication

◆ SOC

[2..2] ADC1 Start of Conversion (software mode)

◆ SQ1

[7..0] Sequence 1 channel enable

◆ 

union { ... } SQ1_4

◆ SQ2

[15..8] Sequence 2 channel enable

◆ SQ3

[23..16] Sequence 3 channel enable

◆ SQ4

[31..24] Sequence 4 channel enable

◆ SQ5

[7..0] Sequence 5 channel enable

◆ 

union { ... } SQ5_8

◆ SQ6

[15..8] Sequence 6 channel enable

◆ SQ7

[23..16] Sequence 7 channel enable

◆ SQ8

[31..24] Sequence 8 channel enable

◆ 

union { ... } SQ_FB

◆ SQ_RUN

__IOM uint32_t SQ_RUN

[8..8] ADC1 Sequencer RUN

◆ SQx

[13..11] Current Active Sequence in Sequencer Mode

◆ 

union { ... } STC_0_3

◆ 

union { ... } STC_4_7

◆ TRIG_SEL

__IOM uint32_t TRIG_SEL

[18..16] Trigger selection for exceptional interrupt measurement (EIM)

[18..16] Trigger selection for exceptional interrupt measurement (ESM)

◆ uint32_t

__IM uint32_t

◆ VF0

[17..17] Valid Flag

◆ VF1

[17..17] Valid Flag

◆ VF2

[17..17] Valid Flag

◆ VF3

[17..17] Valid Flag

◆ VF4

[17..17] Valid Flag

◆ VF5

[17..17] Valid Flag

◆ VF6

[17..17] Valid Flag

◆ VF7

[17..17] Valid Flag

◆ VF8

[17..17] Valid Flag

◆ WFR0

[16..16] Wait for Read Mode

◆ WFR1

[16..16] Wait for Read Mode

◆ WFR2

[16..16] Wait for Read Mode

◆ WFR3

[16..16] Wait for Read Mode

◆ WFR4

[16..16] Wait for Read Mode

◆ WFR5

[16..16] Wait for Read Mode

◆ WFR6

[16..16] Wait for Read Mode

◆ WFR7

[16..16] Wait for Read Mode

◆ WFR8

[16..16] Wait for Read Mode


The documentation for this struct was generated from the following file: