Infineon MOTIX™ MCU TLE987x Device Family SDK
Data Fields
BDRV_Type Struct Reference

Detailed Description

Bridge Driver (BDRV)

#include <tle987x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_EN: 1
 
      __IOM uint32_t   LS1_PWM: 1
 
      __IOM uint32_t   LS1_ON: 1
 
      __IOM uint32_t   LS1_DCS_EN: 1
 
      __IM uint32_t   LS1_DS_STS: 1
 
      __IM uint32_t   LS1_SUPERR_STS: 1
 
      __IM uint32_t   LS1_OC_STS: 1
 
      __IOM uint32_t   LS1_OC_DIS: 1
 
      __IOM uint32_t   LS2_EN: 1
 
      __IOM uint32_t   LS2_PWM: 1
 
      __IOM uint32_t   LS2_ON: 1
 
      __IOM uint32_t   LS2_DCS_EN: 1
 
      __IM uint32_t   LS2_DS_STS: 1
 
      __IM uint32_t   LS2_SUPERR_STS: 1
 
      __IM uint32_t   LS2_OC_STS: 1
 
      __IOM uint32_t   LS2_OC_DIS: 1
 
      __IOM uint32_t   HS1_EN: 1
 
      __IOM uint32_t   HS1_PWM: 1
 
      __IOM uint32_t   HS1_ON: 1
 
      __IOM uint32_t   HS1_DCS_EN: 1
 
      __IM uint32_t   HS1_DS_STS: 1
 
      __IM uint32_t   HS1_SUPERR_STS: 1
 
      __IM uint32_t   HS1_OC_STS: 1
 
      __IOM uint32_t   HS1_OC_DIS: 1
 
      __IOM uint32_t   HS2_EN: 1
 
      __IOM uint32_t   HS2_PWM: 1
 
      __IOM uint32_t   HS2_ON: 1
 
      __IOM uint32_t   HS2_DCS_EN: 1
 
      __IM uint32_t   HS2_DS_STS: 1
 
      __IM uint32_t   HS2_SUPERR_STS: 1
 
      __IM uint32_t   HS2_OC_STS: 1
 
      __IOM uint32_t   HS2_OC_DIS: 1
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS3_EN: 1
 
      __IOM uint32_t   LS3_PWM: 1
 
      __IOM uint32_t   LS3_ON: 1
 
      __IOM uint32_t   LS3_DCS_EN: 1
 
      __IM uint32_t   LS3_DS_STS: 1
 
      __IM uint32_t   LS3_SUPERR_STS: 1
 
      __IM uint32_t   LS3_OC_STS: 1
 
      __IOM uint32_t   LS3_OC_DIS: 1
 
      __IOM uint32_t   HS3_EN: 1
 
      __IOM uint32_t   HS3_PWM: 1
 
      __IOM uint32_t   HS3_ON: 1
 
      __IOM uint32_t   HS3_DCS_EN: 1
 
      __IM uint32_t   HS3_DS_STS: 1
 
      __IM uint32_t   HS3_SUPERR_STS: 1
 
      __IM uint32_t   HS3_OC_STS: 1
 
      __IOM uint32_t   HS3_OC_DIS: 1
 
      __IM uint32_t   DLY_DIAG_TIM: 10
 
      __OM uint32_t   DLY_DIAG_SCLR: 1
 
      __IM uint32_t   DLY_DIAG_STS: 1
 
      __IOM uint32_t   DLY_DIAG_CHSEL: 3
 
      __IOM uint32_t   DLY_DIAG_DIRSEL: 1
 
   }   bit
 
CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ICHARGE_TRIM: 5
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   ICHARGEDIV2_N: 1
 
      __IOM uint32_t   ON_SEQ_EN: 1
 
      __IOM uint32_t   IDISCHARGE_TRIM: 5
 
      __IOM uint32_t   IDISCHARGEDIV2_N: 1
 
      __IOM uint32_t   OFF_SEQ_EN: 1
 
      __IOM uint32_t   DSMONVTH: 3
 
      __IOM uint32_t   DRV_CCP_TIMSEL: 2
 
      __IOM uint32_t   DRV_CCP_DIS: 1
 
   }   bit
 
CTRL3
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DRV_OFF_t_4: 3
 
      __IOM uint32_t   DRV_OFF_I_4: 5
 
      __IOM uint32_t   DRV_OFF_t_3: 3
 
      __IOM uint32_t   DRV_OFF_I_3: 5
 
      __IOM uint32_t   DRV_OFF_t_2: 3
 
      __IOM uint32_t   DRV_OFF_I_2: 5
 
      __IOM uint32_t   DRV_OFF_t_1: 3
 
      __IOM uint32_t   DRV_OFF_I_1: 5
 
   }   bit
 
OFF_SEQ_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DRV_ON_t_4: 3
 
      __IOM uint32_t   DRV_ON_I_4: 5
 
      __IOM uint32_t   DRV_ON_t_3: 3
 
      __IOM uint32_t   DRV_ON_I_3: 5
 
      __IOM uint32_t   DRV_ON_t_2: 3
 
      __IOM uint32_t   DRV_ON_I_2: 5
 
      __IOM uint32_t   DRV_ON_t_1: 3
 
      __IOM uint32_t   DRV_ON_I_1: 5
 
   }   bit
 
ON_SEQ_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS_HS_BT_TFILT_SEL: 2
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   DRV_CCPTIMMUL: 2
 
      __IOM uint32_t   LSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   LS1DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   LS2DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   LS3DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   LS1DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   LS2DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   LS3DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   HSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   HS1DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   HS2DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   HS3DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   HS1DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   HS2DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   HS3DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   CPLOW_TFILT_SEL: 2
 
   }   bit
 
TRIM_DRVx
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CP_EN: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   CP_RDY_EN: 1
 
      __IM uint32_t   VCP_LOTH2_STS: 1
 
      __IOM uint32_t   VCP_LOWTH2: 3
 
      __IOM uint32_t   DRVx_VCPLO_DIS: 1
 
      __IM uint32_t   VCP_LOTH1_STS: 1
 
      __IOM uint32_t   DRVx_VCPUP_DIS: 1
 
      __IM uint32_t   VCP_UPTH_STS: 1
 
      __IOM uint32_t   DRVx_VSDLO_DIS: 1
 
      __IM uint32_t   VSD_LOTH_STS: 1
 
      __IOM uint32_t   DRVx_VSDUP_DIS: 1
 
      __IM uint32_t   VSD_UPTH_STS: 1
 
      __IOM uint32_t   CPLOPWRM_EN: 1
 
      __IOM uint32_t   VCP9V_SET: 1
 
      __IOM uint32_t   VTHVCP9V_TRIM: 2
 
   }   bit
 
CP_CTRL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DITH_LOWER: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   DITH_UPPER: 5
 
      __IOM uint32_t   F_CP: 2
 
      __IOM uint32_t   CPCLK_EN: 1
 
   }   bit
 
CP_CLK_CTRL
 

Field Documentation

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struct { ... } bit

◆ 

union { ... } CP_CLK_CTRL

◆ 

union { ... } CP_CTRL_STS

◆ CP_EN

__IOM uint32_t CP_EN

[0..0] Charge Pump Enable

◆ CP_RDY_EN

__IOM uint32_t CP_RDY_EN

[2..2] Bridge Driver on Charge Pump Ready Enable

◆ CPCLK_EN

__IOM uint32_t CPCLK_EN

[15..15] Charge Pump Clock Enable

◆ CPLOPWRM_EN

__IOM uint32_t CPLOPWRM_EN

[24..24] Charge Pump Low Power Mode Enable

◆ CPLOW_TFILT_SEL

__IOM uint32_t CPLOW_TFILT_SEL

[25..24] Filter Time for Charge Pump Voltage Low Diagnosis

◆ 

union { ... } CTRL1

◆ 

union { ... } CTRL2

◆ 

union { ... } CTRL3

◆ DITH_LOWER

__IOM uint32_t DITH_LOWER

[4..0] CP_CLK lower frequency boundary during dithering

◆ DITH_UPPER

__IOM uint32_t DITH_UPPER

[12..8] CP_CLK upper frequency boundary during dithering

◆ DLY_DIAG_CHSEL

__IOM uint32_t DLY_DIAG_CHSEL

[30..28] Ext. power on/off timer channel select

◆ DLY_DIAG_DIRSEL

__IOM uint32_t DLY_DIAG_DIRSEL

[31..31] Ext. power diag timer on / off select

◆ DLY_DIAG_SCLR

__OM uint32_t DLY_DIAG_SCLR

[26..26] Ext. power diag timer valid flag clear

◆ DLY_DIAG_STS

__IM uint32_t DLY_DIAG_STS

[27..27] Ext. power diag timer valid flag

◆ DLY_DIAG_TIM

__IM uint32_t DLY_DIAG_TIM

[25..16] Ext. power on/off diag timer result register

◆ DRV_CCP_DIS

__IOM uint32_t DRV_CCP_DIS

[26..26] Dynamic cross conduction protection Disable

◆ DRV_CCP_TIMSEL

__IOM uint32_t DRV_CCP_TIMSEL

[25..24] minimum cross conduction protection time setting

◆ DRV_CCPTIMMUL

__IOM uint32_t DRV_CCPTIMMUL

[6..5] Multiplier bits for cross conduction time settings in register DRV_CCP_TIMSEL

◆ DRV_OFF_I_1

__IOM uint32_t DRV_OFF_I_1

[31..27] Slew rate sequencer off phase 1 current

◆ DRV_OFF_I_2

__IOM uint32_t DRV_OFF_I_2

[23..19] Slew rate sequencer off phase 2 current

◆ DRV_OFF_I_3

__IOM uint32_t DRV_OFF_I_3

[15..11] Slew rate sequencer off phase 3 current

◆ DRV_OFF_I_4

__IOM uint32_t DRV_OFF_I_4

[7..3] Slew rate sequencer off phase 4 current

◆ DRV_OFF_t_1

__IOM uint32_t DRV_OFF_t_1

[26..24] Slew rate sequencer off phase 1 time

◆ DRV_OFF_t_2

__IOM uint32_t DRV_OFF_t_2

[18..16] Slew rate sequencer off phase 2 time

◆ DRV_OFF_t_3

__IOM uint32_t DRV_OFF_t_3

[10..8] Slew rate sequencer off phase 3 time

◆ DRV_OFF_t_4

__IOM uint32_t DRV_OFF_t_4

[2..0] Slew rate sequencer off phase 4 time

◆ DRV_ON_I_1

__IOM uint32_t DRV_ON_I_1

[31..27] Slew rate sequencer on phase 1 current

◆ DRV_ON_I_2

__IOM uint32_t DRV_ON_I_2

[23..19] Slew rate sequencer on phase 2 current

◆ DRV_ON_I_3

__IOM uint32_t DRV_ON_I_3

[15..11] Slew rate sequencer on phase 3 current

◆ DRV_ON_I_4

__IOM uint32_t DRV_ON_I_4

[7..3] Slew rate sequencer on phase 4 current

◆ DRV_ON_t_1

__IOM uint32_t DRV_ON_t_1

[26..24] Slew rate sequencer on phase 1 time

◆ DRV_ON_t_2

__IOM uint32_t DRV_ON_t_2

[18..16] Slew rate sequencer on phase 2 time

◆ DRV_ON_t_3

__IOM uint32_t DRV_ON_t_3

[10..8] Slew rate sequencer on phase 3 time

◆ DRV_ON_t_4

__IOM uint32_t DRV_ON_t_4

[2..0] Slew rate sequencer on phase 4 time

◆ DRVx_VCPLO_DIS

__IOM uint32_t DRVx_VCPLO_DIS

[16..16] Driver Shutdown on Charge Pump Low Voltage

◆ DRVx_VCPUP_DIS

__IOM uint32_t DRVx_VCPUP_DIS

[18..18] Driver shutdown on Charge Pump Upper Voltage

◆ DRVx_VSDLO_DIS

__IOM uint32_t DRVx_VSDLO_DIS

[20..20] Driver shutdown on VSD Lower Voltage

◆ DRVx_VSDUP_DIS

__IOM uint32_t DRVx_VSDUP_DIS

[22..22] Driver shutdown on VSD Upper Voltage

◆ DSMONVTH

__IOM uint32_t DSMONVTH

[18..16] Voltage Threshold for Drain-Source Monitoring of external FETs

◆ F_CP

[14..13] MSB of CP_CLK divider

◆ HS1_DCS_EN

__IOM uint32_t HS1_DCS_EN

[19..19] High Side Driver 1 Diagnosis Current Source Enable

◆ HS1_DS_STS

__IM uint32_t HS1_DS_STS

[20..20] High Side Driver 1 Drain Source Monitoring Status in OFF-State

◆ HS1_EN

__IOM uint32_t HS1_EN

[16..16] High Side Driver 1 Enable

◆ HS1_OC_DIS

__IOM uint32_t HS1_OC_DIS

[23..23] High Side Driver Overcurrent Shutdown Disable

◆ HS1_OC_STS

__IM uint32_t HS1_OC_STS

[22..22] External High Side 1 FET Over-current Status

◆ HS1_ON

__IOM uint32_t HS1_ON

[18..18] High Side Driver 1 On

◆ HS1_PWM

__IOM uint32_t HS1_PWM

[17..17] High Side Driver 1 PWM Enable

◆ HS1_SUPERR_STS

__IM uint32_t HS1_SUPERR_STS

[21..21] High Side Driver 1 Supply Error Status

◆ HS1DRV_FDISCHG_DIS

__IOM uint32_t HS1DRV_FDISCHG_DIS

[18..18] High Side 1 Predriver in overcurrent situation disable

◆ HS1DRV_OCSDN_DIS

__IOM uint32_t HS1DRV_OCSDN_DIS

[21..21] High Side 1 Predriver in overcurrent situation disable

◆ HS2_DCS_EN

__IOM uint32_t HS2_DCS_EN

[27..27] High Side Driver 2 Diagnosis Current Source Enable

◆ HS2_DS_STS

__IM uint32_t HS2_DS_STS

[28..28] High Side Driver 2 Drain Source Monitoring Status in OFF-State

◆ HS2_EN

__IOM uint32_t HS2_EN

[24..24] High Side Driver 2 Enable

◆ HS2_OC_DIS

__IOM uint32_t HS2_OC_DIS

[31..31] High Side Driver Overcurrent Shutdown Disable

◆ HS2_OC_STS

__IM uint32_t HS2_OC_STS

[30..30] External High Side 2 FET Over-current Status

◆ HS2_ON

__IOM uint32_t HS2_ON

[26..26] High Side Driver 2 On

◆ HS2_PWM

__IOM uint32_t HS2_PWM

[25..25] High Side Driver 2 PWM Enable

◆ HS2_SUPERR_STS

__IM uint32_t HS2_SUPERR_STS

[29..29] High Side Driver 2 Supply Error Status

◆ HS2DRV_FDISCHG_DIS

__IOM uint32_t HS2DRV_FDISCHG_DIS

[19..19] High Side 2 Predriver in overcurrent situation disable

◆ HS2DRV_OCSDN_DIS

__IOM uint32_t HS2DRV_OCSDN_DIS

[22..22] High Side 2 Predriver in overcurrent situation disable

◆ HS3_DCS_EN

__IOM uint32_t HS3_DCS_EN

[11..11] High Side Driver 3 Diagnosis Current Source Enable

◆ HS3_DS_STS

__IM uint32_t HS3_DS_STS

[12..12] High Side Driver 3 Drain Source Monitoring Status

◆ HS3_EN

__IOM uint32_t HS3_EN

[8..8] High Side Driver 3 Enable

◆ HS3_OC_DIS

__IOM uint32_t HS3_OC_DIS

[15..15] High Side Driver 3 Over-current Shutdown Disable

◆ HS3_OC_STS

__IM uint32_t HS3_OC_STS

[14..14] External High Side 3 FET Over-current Status

◆ HS3_ON

__IOM uint32_t HS3_ON

[10..10] High Side Driver 3 On

◆ HS3_PWM

__IOM uint32_t HS3_PWM

[9..9] High Side Driver 3 PWM Enable

◆ HS3_SUPERR_STS

__IM uint32_t HS3_SUPERR_STS

[13..13] High Side Driver 3 Supply Error Status

◆ HS3DRV_FDISCHG_DIS

__IOM uint32_t HS3DRV_FDISCHG_DIS

[20..20] High Side 3 Predriver in overcurrent situation disable

◆ HS3DRV_OCSDN_DIS

__IOM uint32_t HS3DRV_OCSDN_DIS

[23..23] High Side 3 Predriver in overcurrent situation disable

◆ HSDRV_DS_TFILT_SEL

__IOM uint32_t HSDRV_DS_TFILT_SEL

[17..16] Filter Time for Drain-Source Monitoring of High Side Drivers

◆ ICHARGE_TRIM

__IOM uint32_t ICHARGE_TRIM

[4..0] Trimming of the internal driver charge current

◆ ICHARGEDIV2_N

__IOM uint32_t ICHARGEDIV2_N

[6..6] ICHARGE Current divide by 2 not

◆ IDISCHARGE_TRIM

__IOM uint32_t IDISCHARGE_TRIM

[12..8] Trimming of the internal driver dis-charge current

◆ IDISCHARGEDIV2_N

__IOM uint32_t IDISCHARGEDIV2_N

[14..14] IDISCHARGE Current divide by 2 not

◆ LS1_DCS_EN

__IOM uint32_t LS1_DCS_EN

[3..3] Low Side Driver 1 Diagnosis Current Source Enable

◆ LS1_DS_STS

__IM uint32_t LS1_DS_STS

[4..4] Low Side Driver 1 Drain Source Monitoring Status in OFF-State

◆ LS1_EN

__IOM uint32_t LS1_EN

[0..0] Low Side Driver 1 Enable

◆ LS1_OC_DIS

__IOM uint32_t LS1_OC_DIS

[7..7] Low Side Driver 1 Overcurrent Shutdown Disable

◆ LS1_OC_STS

__IM uint32_t LS1_OC_STS

[6..6] External Low Side 1 FET Over-current Status

◆ LS1_ON

__IOM uint32_t LS1_ON

[2..2] Low Side Driver 1 On

◆ LS1_PWM

__IOM uint32_t LS1_PWM

[1..1] Low Side Driver 1 PWM Enable

◆ LS1_SUPERR_STS

__IM uint32_t LS1_SUPERR_STS

[5..5] Low Side Driver 1 Supply Error Status

◆ LS1DRV_FDISCHG_DIS

__IOM uint32_t LS1DRV_FDISCHG_DIS

[10..10] Low Side 1 Predriver in overcurrent situation disable

◆ LS1DRV_OCSDN_DIS

__IOM uint32_t LS1DRV_OCSDN_DIS

[13..13] Low Side 1 Predriver in overcurrent situation disable

◆ LS2_DCS_EN

__IOM uint32_t LS2_DCS_EN

[11..11] Low Side Driver 2 Diagnosis Current Source Enable

◆ LS2_DS_STS

__IM uint32_t LS2_DS_STS

[12..12] Low Side Driver 2 Drain Source Monitoring Status in OFF-State

◆ LS2_EN

__IOM uint32_t LS2_EN

[8..8] Low Side Driver 2 Enable

◆ LS2_OC_DIS

__IOM uint32_t LS2_OC_DIS

[15..15] Low Side Driver Overcurrent Shutdown Disable

◆ LS2_OC_STS

__IM uint32_t LS2_OC_STS

[14..14] External Low Side 2 FET Over-current Status

◆ LS2_ON

__IOM uint32_t LS2_ON

[10..10] Low Side Driver 2 On

◆ LS2_PWM

__IOM uint32_t LS2_PWM

[9..9] Low Side Driver 2 PWM Enable

◆ LS2_SUPERR_STS

__IM uint32_t LS2_SUPERR_STS

[13..13] Low Side Driver 2 Supply Error Status

◆ LS2DRV_FDISCHG_DIS

__IOM uint32_t LS2DRV_FDISCHG_DIS

[11..11] Low Side 2 Predriver in overcurrent situation disable

◆ LS2DRV_OCSDN_DIS

__IOM uint32_t LS2DRV_OCSDN_DIS

[14..14] Low Side 2 Predriver in overcurrent situation disable

◆ LS3_DCS_EN

__IOM uint32_t LS3_DCS_EN

[3..3] Low Side Driver 3 Diagnosis Current Source Enable

◆ LS3_DS_STS

__IM uint32_t LS3_DS_STS

[4..4] Low Side Driver 3 Drain Source Monitoring Status in OFF-State

◆ LS3_EN

__IOM uint32_t LS3_EN

[0..0] Low Side Driver 3 Enable

◆ LS3_OC_DIS

__IOM uint32_t LS3_OC_DIS

[7..7] Low Side Driver 3 Over-current Shutdown Disable

◆ LS3_OC_STS

__IM uint32_t LS3_OC_STS

[6..6] External Low Side 3 FET Over-current Status

◆ LS3_ON

__IOM uint32_t LS3_ON

[2..2] Low Side Driver 3 On

◆ LS3_PWM

__IOM uint32_t LS3_PWM

[1..1] Low Side Driver 3 PWM Enable

◆ LS3_SUPERR_STS

__IM uint32_t LS3_SUPERR_STS

[5..5] Low Side Driver 3 Supply Error Status

◆ LS3DRV_FDISCHG_DIS

__IOM uint32_t LS3DRV_FDISCHG_DIS

[12..12] Low Side 3 Predriver in overcurrent situation disable

◆ LS3DRV_OCSDN_DIS

__IOM uint32_t LS3DRV_OCSDN_DIS

[15..15] Low Side 3 Predriver in overcurrent situation disable

◆ LS_HS_BT_TFILT_SEL

__IOM uint32_t LS_HS_BT_TFILT_SEL

[1..0] Blanking Time for Drain-Source Monitoring of Low / High Side Drivers

◆ LSDRV_DS_TFILT_SEL

__IOM uint32_t LSDRV_DS_TFILT_SEL

[9..8] Filter Time for Drain-Source Monitoring of Low Side Drivers

◆ 

union { ... } OFF_SEQ_CTRL

◆ OFF_SEQ_EN

__IOM uint32_t OFF_SEQ_EN

[15..15] Turn Off Slewrate Sequencer enable

◆ 

union { ... } ON_SEQ_CTRL

◆ ON_SEQ_EN

__IOM uint32_t ON_SEQ_EN

[7..7] Turn On SlewrateSequencer enable

◆ reg

(@ 0x00000000) H-Bridge Driver Control 1

(@ 0x00000004) H-Bridge Driver Control 2

(@ 0x00000008) H-Bridge Driver Control 3

(@ 0x00000010) Turn on Slewrate Sequencer Control

(@ 0x00000014) Turn off Slewrate Sequencer Control

(@ 0x00000018) Trimming of Driver

(@ 0x00000020) Charge Pump Control and Status Register

(@ 0x00000024) Charge Pump Clock Control Register

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1

◆ 

union { ... } TRIM_DRVx

◆ uint32_t

__IM uint32_t

◆ VCP9V_SET

__IOM uint32_t VCP9V_SET

[25..25] Charge Pump 9 V Output Voltage Set

◆ VCP_LOTH1_STS

__IM uint32_t VCP_LOTH1_STS

[17..17] Charge Pump MU Low Status

◆ VCP_LOTH2_STS

__IM uint32_t VCP_LOTH2_STS

[5..5] Charge Pump Low Status

◆ VCP_LOWTH2

__IOM uint32_t VCP_LOWTH2

[10..8] Charge Pump Output Voltage Lower Threshold Detection Level

◆ VCP_UPTH_STS

__IM uint32_t VCP_UPTH_STS

[19..19] Charge Pump MU High Status

◆ VSD_LOTH_STS

__IM uint32_t VSD_LOTH_STS

[21..21] Driver Supply MU Low Status

◆ VSD_UPTH_STS

__IM uint32_t VSD_UPTH_STS

[23..23] Driver Supply MU High Status

◆ VTHVCP9V_TRIM

__IOM uint32_t VTHVCP9V_TRIM

[27..26] Charge Pump Output Voltage 9V Trimming


The documentation for this struct was generated from the following file: