Infineon MOTIX™ MCU TLE987x Device Family SDK
gpt12e.h
Go to the documentation of this file.
1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * The applicable license agreement can be found at this pack's installation directory in the file
8  * license/IFX_SW_Licence_MOTIX_LITIX.txt
9  *
10  **********************************************************************************************************************/
20 /*******************************************************************************
21 ** Author(s) Identity **
22 ********************************************************************************
23 ** Initials Name **
24 ** ---------------------------------------------------------------------------**
25 ** DM Daniel Mysliwitz **
26 ** BG Blandine Guillot **
27 ** JO Julia Ott **
28 ** VO Vanessa Ongaro **
29 *******************************************************************************/
30 
31 /*******************************************************************************
32 ** Revision Control History **
33 ********************************************************************************
34 ** V0.1.0: 2014-05-13, DM: Initial version **
35 ** V0.1.1: 2015-01-20, DM: GPT12E timer stop API added **
36 ** V0.1.2: 2015-02-10, DM: Individual header file added **
37 ** V0.1.3: 2015-08-27, DM: Timer readout functions added **
38 ** V0.1.4: 2017-05-26, DM: API extended **
39 ** V0.1.5: 2017-09-29, DM: MISRA 2012 compliance, the following PC-Lint **
40 ** rules are globally deactivated: **
41 ** - Info 793: ANSI/ISO limit of 6 'significant **
42 ** characters in an external identifier **
43 ** - Info 835: A zero has been given as right **
44 ** argument to operator **
45 ** - Info 845: The left argument to operator '&' **
46 ** is certain to be 0 **
47 ** Replaced macros by INLINE functions **
48 ** Replaced register accesses within functions by **
49 ** function calls **
50 ** V0.1.6: 2018-03-14, DM: GPT12E_T5_Capture_Trig_Rising_CapIn_En(), **
51 ** GPT12E_T5_Capture_Trig_Rising_CapIn_Dis(), **
52 ** GPT12E_T5_Capture_Trig_Falling_CapIn_En(), **
53 ** GPT12E_T5_Capture_Trig_Falling_CapIn_Dis(), **
54 ** GPT12E_T5_Capture_Trig_Any_T3In_En(), **
55 ** GPT12E_T5_Capture_Trig_Any_T3In_Dis(), **
56 ** GPT12E_T5_Capture_Trig_Any_T3EUD_En(), **
57 ** GPT12E_T5_Capture_Trig_Any_T3EUD_Dis() **
58 ** modified for MISRA 2012 **
59 ** V0.1.7: 2018-07-05, BG: Values for GPT12E_T4_Start_by_T3_En() and **
60 ** GPT12E_T4_Start_by_T3_Dis() **
61 ** corrected in gpt12e.h **
62 ** V0.1.8: 2018-11-27, JO: Doxygen update **
63 ** Moved revision history from gpt12e.c to gpt12e.h **
64 ** V0.1.9: 2020-04-15, BG: Updated revision history format **
65 ** V0.2.0: 2020-07-21, BG: EP-439: Formatted .h/.c files **
66 ** V0.2.1: 2022-02-28, JO: EP-936: Updated copyright and branding **
67 ** V0.2.2: 2022-10-18, VO: EP-1252: Updated enum definitions **
68 ** V0.2.3: 2025-01-02, JO: EP-1493: Updated license **
69 *******************************************************************************/
70 
71 #ifndef GPT12E_H
72 #define GPT12E_H
73 
74 /*******************************************************************************
75 ** Includes **
76 *******************************************************************************/
77 #include "tle987x.h"
78 #include "types.h"
79 #include "sfr_access.h"
80 #include "gpt12e_defines.h"
81 
82 /*******************************************************************************
83 ** Global Type Definitions **
84 *******************************************************************************/
88 typedef enum GPT1_Clk_Prescaler
89 {
93  GPT1_fSYS_Div_32 = 2u
95 
99 typedef enum GPT12E_CCU6_SEL
100 {
112  GPT12E_CCU6_ANY_CHx = 11u
114 
118 typedef enum GPT12E_T2IN
119 {
121  GPT12E_T2INB_P14 = 1u
123 
127 typedef enum GPT12E_T2EUD
128 {
130  GPT12E_T2EUDB_P24 = 1u
132 
136 typedef enum GPT12E_T3IN
137 {
141  GPT12E_T3IND_MON = 3u
143 
147 typedef enum GPT12E_T3EUD
148 {
150  GPT12E_T3EUDB_P25 = 1u
152 
156 typedef enum GPT12E_T4IN
157 {
163 
167 typedef enum GPT12E_T4EUD
168 {
170  GPT12E_T4EUDB_P10 = 1u
172 
176 typedef enum GPT2_Clk_Prescaler
177 {
181  GPT2_fSYS_Div_16 = 2u
183 
187 typedef enum GPT12E_T5IN
188 {
190  GPT12E_T5INB_P20 = 1u
192 
196 typedef enum GPT12E_T5EUD
197 {
199  GPT12E_T5EUDB_P20 = 1u
201 
205 typedef enum GPT12E_T6IN
206 {
208  GPT12E_T6INB_P13 = 1u
210 
214 typedef enum GPT12E_T6EUD
215 {
217  GPT12E_T6EUDB_P13 = 1u
219 
223 typedef enum GPT12E_CAPIN
224 {
230 
235 {
243  GPT_Clk_Div_128 = 7
245 
246 
247 /*******************************************************************************
248 ** Global Inline Function Definitions **
249 *******************************************************************************/
265 {
267 }
268 
286 {
288 }
289 
305 {
307 }
308 
309 /****************************************************************************/
310 /* Timer2 *******************************************************************/
311 /****************************************************************************/
325 {
327 }
328 
342 {
344 }
345 
359 {
361 }
362 
376 {
378 }
379 
393 {
395 }
396 
410 {
412 }
413 
427 {
429 }
430 
444 {
446 }
447 
464 {
466 }
467 
484 {
486 }
487 
502 {
503  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
504 }
505 
520 {
521  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
522 }
523 
538 {
539  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
540 }
541 
556 {
557  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
558 }
559 
574 {
575  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
576 }
577 
592 {
593  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 1u);
594 }
595 
610 {
611  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
612 }
613 
628 {
629  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
630 }
631 
646 {
647  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
648 }
649 
664 {
665  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
666 }
667 
682 {
683  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
684 }
685 
700 {
701  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
702 }
703 
718 {
719  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
720 }
721 
736 {
737  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
738 }
739 
754 {
755  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
756 }
757 
772 {
773  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
774 }
775 
790 {
791  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
792 }
793 
808 {
809  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
810 }
811 
826 {
827  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
828 }
829 
844 {
845  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
846 }
847 
862 {
863  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 1u);
864 }
865 
880 {
881  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
882 }
883 
898 {
899  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
900 }
901 
916 {
917  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
918 }
919 
934 {
935  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
936 }
937 
952 {
953  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
954 }
955 
970 {
971  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
972 }
973 
988 {
989  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
990 }
991 
1006 {
1007  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
1008 }
1009 
1024 {
1025  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
1026 }
1027 
1042 {
1044 }
1045 
1060 {
1062 }
1063 
1078 {
1080 }
1081 
1096 {
1098 }
1099 
1114 {
1116 }
1117 
1132 {
1134 }
1135 
1149 {
1151 }
1152 
1167 {
1169 }
1170 
1185 {
1187 }
1188 
1203 {
1205 }
1206 
1226 {
1228 }
1229 
1247 {
1249 }
1250 
1270 {
1272 }
1273 
1291 {
1293 }
1294 
1312 {
1314 }
1315 
1331 {
1333 }
1334 
1352 {
1354 }
1355 
1372 {
1374 }
1375 
1376 /****************************************************************************/
1377 /* Timer3 * Core Timer ******************************************************/
1378 /****************************************************************************/
1392 {
1394 }
1395 
1409 {
1411 }
1412 
1426 {
1428 }
1429 
1443 {
1445 }
1446 
1460 {
1462 }
1463 
1477 {
1479 }
1480 
1497 {
1499 }
1500 
1517 {
1519 }
1520 
1535 {
1536  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 1u);
1537 }
1538 
1553 {
1554  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 0u);
1555 }
1556 
1571 {
1572  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 1u);
1573 }
1574 
1589 {
1590  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 0u);
1591 }
1592 
1607 {
1608  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 1u);
1609 }
1610 
1625 {
1626  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 0u);
1627 }
1628 
1643 {
1644  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 1u);
1645 }
1646 
1661 {
1662  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 0u);
1663 }
1664 
1678 {
1680 }
1681 
1695 {
1697 }
1698 
1712 {
1714 }
1715 
1729 {
1731 }
1732 
1747 {
1749 }
1750 
1765 {
1767 }
1768 
1783 {
1785 }
1786 
1801 {
1803 }
1804 
1818 {
1820 }
1821 
1836 {
1838 }
1839 
1854 {
1856 }
1857 
1872 {
1874 }
1875 
1895 {
1897 }
1898 
1916 {
1918 }
1919 
1939 {
1941 }
1942 
1960 {
1962 }
1963 
1981 {
1983 }
1984 
2000 {
2002 }
2003 
2021 {
2023 }
2024 
2041 {
2043 }
2044 
2045 /****************************************************************************/
2046 /* Timer4 *******************************************************************/
2047 /****************************************************************************/
2061 {
2063 }
2064 
2078 {
2080 }
2081 
2095 {
2097 }
2098 
2112 {
2114 }
2115 
2129 {
2131 }
2132 
2146 {
2148 }
2149 
2163 {
2165 }
2166 
2180 {
2182 }
2183 
2200 {
2202 }
2203 
2220 {
2222 }
2223 
2238 {
2239  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2240 }
2241 
2256 {
2257  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2258 }
2259 
2274 {
2275  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2276 }
2277 
2292 {
2293  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2294 }
2295 
2310 {
2311  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2312 }
2313 
2328 {
2329  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 1u);
2330 }
2331 
2346 {
2347  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2348 }
2349 
2364 {
2365  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2366 }
2367 
2382 {
2383  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2384 }
2385 
2400 {
2401  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2402 }
2403 
2418 {
2419  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2420 }
2421 
2436 {
2437  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2438 }
2439 
2454 {
2455  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2456 }
2457 
2472 {
2473  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2474 }
2475 
2490 {
2491  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2492 }
2493 
2508 {
2509  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2510 }
2511 
2526 {
2527  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2528 }
2529 
2544 {
2545  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2546 }
2547 
2562 {
2563  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2564 }
2565 
2580 {
2581  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2582 }
2583 
2598 {
2599  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 1u);
2600 }
2601 
2616 {
2617  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2618 }
2619 
2634 {
2635  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2636 }
2637 
2652 {
2653  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2654 }
2655 
2670 {
2671  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2672 }
2673 
2688 {
2689  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2690 }
2691 
2706 {
2707  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2708 }
2709 
2724 {
2725  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2726 }
2727 
2742 {
2743  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2744 }
2745 
2760 {
2762 }
2763 
2778 {
2780 }
2781 
2796 {
2798 }
2799 
2814 {
2816 }
2817 
2832 {
2834 }
2835 
2850 {
2852 }
2853 
2867 {
2869 }
2870 
2885 {
2887 }
2888 
2903 {
2905 }
2906 
2921 {
2923 }
2924 
2940 {
2942 }
2943 
2957 {
2959 }
2960 
2976 {
2978 }
2979 
2993 {
2995 }
2996 
3016 {
3018 }
3019 
3037 {
3039 }
3040 
3060 {
3062 }
3063 
3081 {
3083 }
3084 
3102 {
3104 }
3105 
3121 {
3123 }
3124 
3142 {
3144 }
3145 
3162 {
3164 }
3165 
3166 /****************************************************************************/
3167 /* GPT2 *******************************************************************/
3168 /****************************************************************************/
3184 {
3186 }
3187 
3205 {
3207 }
3208 
3209 /****************************************************************************/
3210 /* Timer5 *******************************************************************/
3211 /****************************************************************************/
3225 {
3227 }
3228 
3242 {
3244 }
3245 
3259 {
3261 }
3262 
3276 {
3278 }
3279 
3296 {
3298 }
3299 
3316 {
3318 }
3319 
3334 {
3335  Field_Mod16(&GPT12E->T5CON.reg, 2u, 4u, 0u);
3336 }
3337 
3352 {
3353  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 1u);
3354 }
3355 
3370 {
3371  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 1u);
3372 }
3373 
3388 {
3389  Field_Mod16(&GPT12E->T5CON.reg, 0u, 3u, 3u);
3390 }
3391 
3406 {
3407  Field_Mod16(&GPT12E->T5CON.reg, 2u, 4u, 1u);
3408 }
3409 
3424 {
3425  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 1u);
3426 }
3427 
3442 {
3443  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 0u);
3444 }
3445 
3460 {
3461  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 1u);
3462 }
3463 
3478 {
3479  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 0u);
3480 }
3481 
3495 {
3497 }
3498 
3512 {
3514 }
3515 
3530 {
3532 }
3533 
3549 {
3550  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 1u);
3551 }
3552 
3568 {
3569  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 0u);
3570 }
3571 
3587 {
3588  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 1u);
3589 }
3590 
3606 {
3607  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 0u);
3608 }
3609 
3624 {
3626 }
3627 
3643 {
3644  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 1u);
3645 }
3646 
3662 {
3663  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 0u);
3664 }
3665 
3681 {
3682  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 1u);
3683 }
3684 
3700 {
3701  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 0u);
3702 }
3703 
3718 {
3720 }
3721 
3736 {
3738 }
3739 
3758 {
3760 }
3761 
3776 {
3778 }
3779 
3794 {
3796 }
3797 
3812 {
3814 }
3815 
3830 {
3832 }
3833 
3848 {
3850 }
3851 
3866 {
3868 }
3869 
3883 {
3885 }
3886 
3901 {
3903 }
3904 
3922 {
3924 }
3925 
3941 {
3943 }
3944 
3962 {
3964 }
3965 
3982 {
3984 }
3985 
3986 /****************************************************************************/
3987 /* Timer6 *******************************************************************/
3988 /****************************************************************************/
4002 {
4004 }
4005 
4019 {
4021 }
4022 
4036 {
4038 }
4039 
4053 {
4055 }
4056 
4073 {
4075 }
4076 
4093 {
4095 }
4096 
4111 {
4112  Field_Mod16(&GPT12E->T6CON.reg, (uint16)2u, (uint16)4u, 0u);
4113 }
4114 
4129 {
4130  Field_Mod16(&GPT12E->T6CON.reg, (uint16)0u, (uint16)1u, 1u);
4131 }
4132 
4147 {
4148  Field_Mod16(&GPT12E->T6CON.reg, (uint16)1u, (uint16)2u, 1u);
4149 }
4150 
4165 {
4166  Field_Mod16(&GPT12E->T6CON.reg, (uint16)0u, (uint16)3u, 3u);
4167 }
4168 
4182 {
4184 }
4185 
4199 {
4201 }
4202 
4219 {
4221 }
4222 
4237 {
4239 }
4240 
4255 {
4257 }
4258 
4272 {
4274 }
4275 
4289 {
4291 }
4292 
4306 {
4308 }
4309 
4323 {
4325 }
4326 
4341 {
4343 }
4344 
4359 {
4361 }
4362 
4377 {
4379 }
4380 
4395 {
4397 }
4398 
4412 {
4414 }
4415 
4430 {
4432 }
4433 
4451 {
4453 }
4454 
4470 {
4472 }
4473 
4491 {
4493 }
4494 
4511 {
4513 }
4514 
4515 /****************************************************************************/
4516 /* CAPREL *******************************************************************/
4517 /****************************************************************************/
4536 {
4538 }
4539 
4540 /****************************************************************************/
4541 /* Interrupt ****************************************************************/
4542 /****************************************************************************/
4563 {
4564  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T2_Pos, (uint8)SCU_GPT12IRC_T2_Msk) );
4565 }
4566 
4587 {
4588  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T3_Pos, (uint8)SCU_GPT12IRC_T3_Msk) );
4589 }
4590 
4611 {
4612  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T4_Pos, (uint8)SCU_GPT12IRC_T4_Msk) );
4613 }
4614 
4635 {
4636  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T5_Pos, (uint8)SCU_GPT12IRC_T5_Msk) );
4637 }
4638 
4659 {
4660  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T6_Pos, (uint8)SCU_GPT12IRC_T6_Msk) );
4661 }
4662 
4683 {
4684  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_CR_Pos, (uint8)SCU_GPT12IRC_CR_Msk) );
4685 }
4686 
4687 /* GPT12E Interrupt Clear Macros */
4707 {
4709 }
4710 
4730 {
4732 }
4733 
4753 {
4755 }
4756 
4776 {
4778 }
4779 
4799 {
4801 }
4802 
4822 {
4824 }
4825 
4845 {
4847 }
4848 
4868 {
4870 }
4871 
4891 {
4893 }
4894 
4914 {
4916 }
4917 
4937 {
4939 }
4940 
4960 {
4962 }
4963 
4983 {
4985 }
4986 
5006 {
5008 }
5009 
5029 {
5031 }
5032 
5052 {
5054 }
5055 
5075 {
5077 }
5078 
5098 {
5100 }
5101 
5102 /*******************************************************************************
5103 ** Global Function Declarations **
5104 *******************************************************************************/
5109 void GPT12E_Init(void);
5110 
5130 bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us);
5131 
5149 bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us);
5150 
5151 #endif
INLINE void GPT12E_T3_Int_Clr(void)
clears GPT Module 1 Timer 3 interrupt flag.
Definition: gpt12e.h:4729
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:645
INLINE void GPT12E_T4_Mode_Counter_Input_T4In_Sel(void)
selects T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2237
INLINE void GPT12E_T6_Mode_Timer_Sel(void)
selects T6 Timer Mode.
Definition: gpt12e.h:4001
INLINE void GPT12E_T6_T6EUD_Sel(uint16 ist6eud)
selects Input for T6EUD.
Definition: gpt12e.h:4510
INLINE void GPT12E_T2_Mode_IncEnc_Input_Sel(void)
selects T2 Incremental Interface Mode Input.
Definition: gpt12e.h:951
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:933
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:627
INLINE void GPT12E_T2_Int_En(void)
enables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:4844
INLINE void GPT12E_T4_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T4 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:2902
void GPT12E_Init(void)
Initializes the GPT12E module based on the Config Wizard for MOTIX MCU configuration.
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2435
INLINE void GPT12E_T5_Mode_Timer_Clk_Prescaler_Sel(uint16 t5i)
selects T5 Timer Mode Parameter.
Definition: gpt12e.h:3295
INLINE void GPT12E_T2_T2In_Sel(uint16 ist2in)
selects Input for T2IN.
Definition: gpt12e.h:1351
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:807
INLINE void GPT12E_T4_Mode_IncEnc_Rot_Sel(void)
selects T4 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:2162
INLINE void GPT12E_T3_T4_CCU6_Sel(uint8 gpt)
selects GPT12 TIN3B/TIN4D Input.
Definition: gpt12e.h:304
INLINE void GPT12E_T4_Mode_Counter_Input_T3Out_Sel(void)
selects T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2327
INLINE void GPT12E_T2_DownCount_Sel(void)
selects Timer T2 counts down.
Definition: gpt12e.h:1113
INLINE void GPT12E_GPT1_Clk_Prescaler_Sel(uint16 bps1)
selects GPT1 Clock Prescaler.
Definition: gpt12e.h:264
INLINE void GPT12E_T4_Mode_Capture_Sel(void)
selects T4 Capture Mode.
Definition: gpt12e.h:2145
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:717
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:879
GPT2_Clk_Prescaler
Definition: gpt12e.h:177
@ GPT2_fSYS_Div_16
Definition: gpt12e.h:181
@ GPT2_fSYS_Div_2
Definition: gpt12e.h:178
@ GPT2_fSYS_Div_4
Definition: gpt12e.h:179
@ GPT2_fSYS_Div_8
Definition: gpt12e.h:180
INLINE void GPT12E_T5_Capture_En(void)
enables T5 Capture Mode.
Definition: gpt12e.h:3494
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2723
INLINE void GPT12E_T2_Mode_Timer_Sel(void)
selects T2 Timer Mode.
Definition: gpt12e.h:324
INLINE uint8 GPT12E_T2_Int_Sts(void)
reads GPT Module 1 Timer 2 interrupt Status.
Definition: gpt12e.h:4562
INLINE void GPT12E_T5_Capture_Trig_T3In_T3EUD_Sel(void)
selects T3In and/or T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3623
GPT12E_T5IN
Definition: gpt12e.h:188
@ GPT12E_T5INB_P20
Definition: gpt12e.h:190
@ GPT12E_T5INA_P03
Definition: gpt12e.h:189
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:915
INLINE uint8 GPT12E_T6_Int_Sts(void)
reads GPT Module 2 Timer 6 interrupt Status.
Definition: gpt12e.h:4658
INLINE void GPT12E_T4_Clr_T2_En(void)
Enables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2939
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2561
enum GPT12E_T3EUD TGPT12E_T3EUD
enum GPT12E_CCU6_SEL TGPT12E_CCU6_SEL
INLINE void GPT12E_T6_Output_Set(void)
sets Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:4340
INLINE void GPT12E_T6_Start(void)
starts Timer T6.
Definition: gpt12e.h:4271
INLINE void GPT12E_T2_Mode_Gated_Timer_High_Sel(void)
selects T2 Gated high Mode.
Definition: gpt12e.h:375
INLINE uint8 GPT12E_T2_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:1269
INLINE uint8 GPT12E_T3_Int_Sts(void)
reads GPT Module 1 Timer 3 interrupt Status.
Definition: gpt12e.h:4586
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_Dis(void)
disables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3441
INLINE void GPT12E_T6_Reload_Value_Set(uint16 rl)
sets Current T6 Reload Value.
Definition: gpt12e.h:4218
INLINE void GPT12E_T3_UpCount_Sel(void)
selects Timer T3 counts up.
Definition: gpt12e.h:1800
INLINE void GPT12E_T3_Output_Rst(void)
clears Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:1764
INLINE void GPT12E_T4_Mode_Timer_Sel(void)
selects T4 Timer Mode.
Definition: gpt12e.h:2060
INLINE void GPT12E_T4_Clr_T3_En(void)
Enables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2975
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_En(void)
enables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3548
INLINE void GPT12E_CapRel_Int_Clr(void)
clears GPT Module 1 Capture Reload interrupt flag.
Definition: gpt12e.h:4821
INLINE uint16 GPT12E_T5_Capture_Value_Get(void)
reads Current T5 Capture Value.
Definition: gpt12e.h:3757
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2363
INLINE void GPT12E_T6_Stop(void)
stops Timer T6.
Definition: gpt12e.h:4288
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Sel(void)
selects T4 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:2179
INLINE void GPT12E_T2_Mode_IncEnc_Rot_Sel(void)
selects T2 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:426
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2543
INLINE void GPT12E_T4_Mode_Gated_Timer_High_Sel(void)
selects T4 Gated high Mode.
Definition: gpt12e.h:2111
INLINE void GPT12E_T3_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t3i)
selects T3 Gated Timer Mode Parameter.
Definition: gpt12e.h:1516
INLINE void GPT12E_T4_Start(void)
starts Timer T4.
Definition: gpt12e.h:2759
INLINE void GPT12E_T2_T2EUD_Sel(uint16 ist2eud)
selects Input for T2EUD.
Definition: gpt12e.h:1371
INLINE void GPT12E_T3_Mode_Timer_Clk_Prescaler_Sel(uint16 t3i)
selects T3 Timer Mode Parameter.
Definition: gpt12e.h:1496
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_Dis(void)
disables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3699
INLINE void GPT12E_T6_Mode_Gated_Timer_High_Sel(void)
selects T6 Gated high Mode.
Definition: gpt12e.h:4052
INLINE void GPT12E_T4_Stop(void)
stops Timer T4.
Definition: gpt12e.h:2777
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1246
INLINE void GPT12E_T2_Mode_Reload_Sel(void)
selects T2 Reload Mode.
Definition: gpt12e.h:392
INLINE void GPT12E_T6_On_Capture_Cleared_En(void)
enables clearing T6 on a Capture Event.
Definition: gpt12e.h:4236
INLINE void GPT12E_T3_Mode_Timer_Sel(void)
selects T3 Timer Mode.
Definition: gpt12e.h:1391
INLINE void GPT12E_T4_Mode_Reload_Input_T4In_Sel(void)
selects T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2507
INLINE void GPT12E_T5_Int_Dis(void)
disables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:5005
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:555
INLINE void GPT12E_T6_Mode_Counter_Input_Rising_T6In_Sel(void)
selects Rising Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4128
INLINE void GPT12E_T2_Value_Set(uint16 t2)
sets Timer T2 Value.
Definition: gpt12e.h:1330
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1624
enum GPT1_Clk_Prescaler TGPT1_Clk_Prescaler
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_Dis(void)
disables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:3661
INLINE void GPT12E_T3_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:1959
INLINE void GPT12E_T4_Mode_Counter_Sel(void)
selects T4 Counter Mode.
Definition: gpt12e.h:2077
INLINE void GPT12E_T3_Int_En(void)
enables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:4890
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2255
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2381
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2309
INLINE uint8 GPT12E_T5_Int_Sts(void)
reads GPT Module 2 Timer 5 interrupt Status.
Definition: gpt12e.h:4634
GPT12E_T2EUD
Definition: gpt12e.h:128
@ GPT12E_T2EUDA_P02
Definition: gpt12e.h:129
@ GPT12E_T2EUDB_P24
Definition: gpt12e.h:130
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2615
GPT12E_T5EUD
Definition: gpt12e.h:197
@ GPT12E_T5EUDA_P14
Definition: gpt12e.h:198
@ GPT12E_T5EUDB_P20
Definition: gpt12e.h:199
INLINE void GPT12E_T3_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:1835
INLINE void GPT12E_T3_Output_Set(void)
sets Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:1746
INLINE void GPT12E_T3_T3EUD_Sel(uint16 ist3eud)
selects Input for T3EUD.
Definition: gpt12e.h:2040
INLINE void GPT12E_T6_UpCount_Sel(void)
selects Timer T6 counts up.
Definition: gpt12e.h:4394
INLINE void GPT12E_T6_Reload_En(void)
enables T6 Reload Mode.
Definition: gpt12e.h:4181
enum GPT12E_T2EUD TGPT12E_T2EUD
INLINE void GPT12E_T4_Start_by_T3_Dis(void)
disables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:2813
INLINE void GPT12E_T2_Start_by_T3_Dis(void)
disables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:1095
bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T6 to be reloaded by CAPREL.
INLINE void GPT12E_T6_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:4411
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:825
INLINE void GPT12E_T4_T4In_Sel(uint16 ist4in)
selects Input for T4IN.
Definition: gpt12e.h:3141
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2291
INLINE uint16 GPT12E_T4_Value_Get(void)
reads Timer T4 Value.
Definition: gpt12e.h:3101
INLINE void GPT12E_T6_Int_Dis(void)
disables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5051
INLINE void GPT12E_T2_Mode_Capture_Input_T2In_Sel(void)
selects T2In as T2 Capture Mode Input.
Definition: gpt12e.h:681
INLINE void GPT12E_T2_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:1166
INLINE void GPT12E_T2_Mode_Gated_Timer_Low_Sel(void)
selects T2 Gated low Mode.
Definition: gpt12e.h:358
INLINE uint8 GPT12E_T3_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:1938
INLINE void GPT12E_T3_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T3 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:1853
INLINE void GPT12E_T3_Value_Set(uint16 t3)
sets Timer T3 Value.
Definition: gpt12e.h:1999
INLINE void GPT12E_T3_DownCount_Sel(void)
selects Timer T3 counts down.
Definition: gpt12e.h:1782
INLINE void GPT12E_T3_T3In_Sel(uint16 ist3in)
selects Input for T3IN.
Definition: gpt12e.h:2020
INLINE void GPT12E_T4_DownCount_Sel(void)
selects Timer T4 counts down.
Definition: gpt12e.h:2831
INLINE void GPT12E_T2_Stop(void)
stops Timer T2.
Definition: gpt12e.h:1059
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_En(void)
enables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1534
INLINE void GPT12E_T6_Int_En(void)
enables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5028
enum GPT12E_CAPIN TGPT12E_CAPIN
INLINE void GPT12E_T5_Mode_Counter_Sel(void)
selects T5 Counter Mode.
Definition: gpt12e.h:3241
INLINE void GPT12E_T6_Mode_Counter_Input_T6In_Sel(void)
selects T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4110
enum GPT12E_T3IN TGPT12E_T3IN
INLINE void GPT12E_T5_Mode_Gated_Timer_High_Sel(void)
selects T5 Gated high Mode.
Definition: gpt12e.h:3275
enum GPT12E_T4IN TGPT12E_T4IN
INLINE void GPT12E_T4_Int_Clr(void)
clears GPT Module 1 Timer 4 interrupt flag.
Definition: gpt12e.h:4752
INLINE void GPT12E_T3_Mode_Gated_Timer_Low_Sel(void)
selects T3 Gated low Mode.
Definition: gpt12e.h:1425
INLINE void GPT12E_T5_Capture_Dis(void)
disables T5 Capture Mode.
Definition: gpt12e.h:3511
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_En(void)
enables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1570
INLINE void GPT12E_T3_Output_En(void)
enables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:1711
GPT12E_T4IN
Definition: gpt12e.h:157
@ GPT12E_T4INB_CCU6_CH0
Definition: gpt12e.h:159
@ GPT12E_T4IND_CCU6_SEL
Definition: gpt12e.h:161
@ GPT12E_T4INC_P01
Definition: gpt12e.h:160
@ GPT12E_T4INA_P00
Definition: gpt12e.h:158
INLINE void GPT12E_T2_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T2 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:1184
INLINE uint16 GPT12E_T6_Value_Get(void)
reads Timer T6 Value.
Definition: gpt12e.h:4450
INLINE void GPT12E_T2_Int_Clr(void)
clears GPT Module 1 Timer 2 interrupt flag.
Definition: gpt12e.h:4706
INLINE void GPT12E_T4_Mode_Timer_Clk_Prescaler_Sel(uint16 t4i)
selects T4 Timer Mode Parameter.
Definition: gpt12e.h:2199
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_En(void)
enables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3423
GPT12E_CAPIN
Definition: gpt12e.h:224
@ GPT12E_CAPIND_T2_T3_T4_READ
Definition: gpt12e.h:228
@ GPT12E_CAPINA_P01
Definition: gpt12e.h:225
@ GPT12E_CAPINC_T3_READ
Definition: gpt12e.h:227
@ GPT12E_CAPINB_P03
Definition: gpt12e.h:226
INLINE void GPT12E_T6_Mode_Counter_Input_Any_T6In_Sel(void)
selects Any Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4164
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_Dis(void)
disables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3477
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2651
INLINE uint16 GPT12E_GPT1_Clk_Prescaler_Get(void)
reads GPT1 Clock Prescaler.
Definition: gpt12e.h:285
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:735
bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T3 to be reloaded by T2.
INLINE void GPT12E_T5_Cleared_On_Capture_Dis(void)
disables clearing T5 on a Capture Event.
Definition: gpt12e.h:3735
INLINE void GPT12E_T3_Mode_Gated_Timer_High_Sel(void)
selects T3 Gated high Mode.
Definition: gpt12e.h:1442
INLINE void GPT12E_T5_Mode_Counter_Input_T5In_Sel(void)
selects T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3333
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1642
INLINE void GPT12E_T5_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:3900
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2525
INLINE void GPT12E_T6_Output_En(void)
enables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:4305
INLINE void GPT12E_T4_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:2866
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:1005
INLINE void GPT12E_T6_Mode_Timer_Clk_Prescaler_Sel(uint16 t6i)
selects T6 Timer Mode Parameter.
Definition: gpt12e.h:4072
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:537
INLINE void GPT12E_T5_T5EUD_Sel(uint16 ist5eud)
selects Input for T5EUD.
Definition: gpt12e.h:3981
INLINE void GPT12E_T4_T4EUD_Sel(uint16 ist4eud)
selects Input for T4EUD.
Definition: gpt12e.h:3161
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_Dis(void)
disables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1552
enum GPT12E_T4EUD TGPT12E_T4EUD
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:573
INLINE void GPT12E_T5_Mode_Counter_Input_Any_T5In_Sel(void)
selects Any Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3387
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2399
INLINE void GPT12E_T3_Mode_IncEnc_Rot_Sel(void)
selects T3 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:1459
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T5In_Sel(void)
selects Rising Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3351
INLINE void GPT12E_T4_Mode_Reload_Sel(void)
selects T4 Reload Mode.
Definition: gpt12e.h:2128
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:969
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_Dis(void)
disables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3567
INLINE uint8 GPT12E_CapRel_Int_Sts(void)
reads GPT Module 1 Capture Reload interrupt Status.
Definition: gpt12e.h:4682
INLINE void GPT12E_T5_Stop(void)
stops Timer T5.
Definition: gpt12e.h:3793
INLINE void GPT12E_T4_Start_by_T3_En(void)
enables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:2795
INLINE void GPT12E_T6_On_Capture_Cleared_Dis(void)
disables clearing T6 on a Capture Event.
Definition: gpt12e.h:4254
INLINE void GPT12E_T5_Int_En(void)
enables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:4982
INLINE void GPT12E_CapRel_CAPIn_Sel(uint16 iscapin)
selects CAPIN.
Definition: gpt12e.h:4535
INLINE uint16 GPT12E_T5_Value_Get(void)
reads Timer T5 Value.
Definition: gpt12e.h:3921
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:519
INLINE void GPT12E_T6_Int_Clr(void)
clears GPT Module 2 Timer 6 interrupt flag.
Definition: gpt12e.h:4798
INLINE void GPT12E_T5_Start_by_T6_En(void)
enables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:3829
INLINE void GPT12E_T4_Value_Set(uint16 t4)
sets Timer T4 Value.
Definition: gpt12e.h:3120
INLINE void GPT12E_T6_Output_Rst(void)
clears Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:4358
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_En(void)
enables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:3642
enum GPT2_Clk_Prescaler TGPT2_Clk_Prescaler
INLINE void GPT12E_T5_Start_by_T6_Dis(void)
disables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:3811
INLINE void GPT12E_T4_Mode_Capture_Input_T4In_Sel(void)
selects T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2417
INLINE void GPT12E_T2_UpCount_Sel(void)
selects Timer T2 counts up.
Definition: gpt12e.h:1131
INLINE void GPT12E_T4_Int_En(void)
enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:4936
INLINE uint16 GPT12E_T2_Value_Get(void)
reads Timer T2 Value.
Definition: gpt12e.h:1311
INLINE void GPT12E_T6_T6In_Sel(uint16 ist6in)
selects Input for T6IN.
Definition: gpt12e.h:4490
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:753
INLINE void GPT12E_T5_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:3882
INLINE void GPT12E_T4_Mode_Gated_Timer_Low_Sel(void)
selects T4 Gated low Mode.
Definition: gpt12e.h:2094
INLINE void GPT12E_T5_Mode_Gated_Timer_Low_Sel(void)
selects T5 Gated low Mode.
Definition: gpt12e.h:3258
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:897
INLINE void GPT12E_T4_Mode_Reload_Input_T3Out_Sel(void)
selects T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2597
INLINE void GPT12E_CapRel_Int_Dis(void)
disables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5097
enum GPT12E_T6IN TGPT12E_T6IN
INLINE void GPT12E_T2_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T2 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:1202
INLINE void GPT12E_T2_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t2i)
selects T2 Gated Timer Mode Parameter.
Definition: gpt12e.h:483
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2705
INLINE void GPT12E_T6_Mode_Gated_Timer_Low_Sel(void)
selects T6 Gated low Mode.
Definition: gpt12e.h:4035
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:843
INLINE void GPT12E_T5_Int_Clr(void)
clears GPT Module 2 Timer 5 interrupt flag.
Definition: gpt12e.h:4775
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2741
INLINE void GPT12E_T2_Start_by_T3_En(void)
enables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:1077
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2471
GPT12E_T3IN
Definition: gpt12e.h:137
@ GPT12E_T3IND_MON
Definition: gpt12e.h:141
@ GPT12E_T3INC_P10
Definition: gpt12e.h:140
@ GPT12E_T3INA_CCU6_CH0
Definition: gpt12e.h:138
@ GPT12E_T3INB_CCU6_SEL
Definition: gpt12e.h:139
INLINE void GPT12E_T6_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:4429
INLINE void GPT12E_T2_Mode_Reload_Input_T3Out_Sel(void)
selects T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:861
INLINE void GPT12E_T6_Reload_Dis(void)
disables T6 Reload Mode.
Definition: gpt12e.h:4198
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:699
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:663
GPT1_Clk_Prescaler
Definition: gpt12e.h:89
@ GPT1_fSYS_Div_32
Definition: gpt12e.h:93
@ GPT1_fSYS_Div_16
Definition: gpt12e.h:92
@ GPT1_fSYS_Div_4
Definition: gpt12e.h:90
@ GPT1_fSYS_Div_8
Definition: gpt12e.h:91
INLINE void GPT12E_T6_Mode_Counter_Input_Falling_T6In_Sel(void)
selects Falling Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4146
INLINE void GPT12E_T6_Mode_Counter_Sel(void)
selects T6 Counter Mode.
Definition: gpt12e.h:4018
INLINE void GPT12E_T4_Clr_T3_Dis(void)
Disables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2992
GPT12E_T3EUD
Definition: gpt12e.h:148
@ GPT12E_T3EUDA_P04
Definition: gpt12e.h:149
@ GPT12E_T3EUDB_P25
Definition: gpt12e.h:150
INLINE void GPT12E_T4_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:2884
GPT12E_T6EUD
Definition: gpt12e.h:215
@ GPT12E_T6EUDA_P11
Definition: gpt12e.h:216
@ GPT12E_T6EUDB_P13
Definition: gpt12e.h:217
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T5In_Sel(void)
selects Falling Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3369
INLINE void GPT12E_T2_Mode_Reload_Input_T2In_Sel(void)
selects T2In as T2 Reload Mode Input.
Definition: gpt12e.h:771
INLINE void GPT12E_T5_Mode_Timer_Sel(void)
selects T5 Timer Mode.
Definition: gpt12e.h:3224
INLINE void GPT12E_T5_Mode_Counter_Input_T6Out_Sel(void)
selects T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3405
INLINE void GPT12E_T2_Mode_Counter_Sel(void)
selects T2 Counter Mode.
Definition: gpt12e.h:341
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_Dis(void)
disables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3605
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2345
INLINE void GPT12E_T2_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:1148
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2489
GPT12E_T6IN
Definition: gpt12e.h:206
@ GPT12E_T6INB_P13
Definition: gpt12e.h:208
@ GPT12E_T6INA_P02
Definition: gpt12e.h:207
INLINE void GPT12E_T3_Int_Dis(void)
disables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:4913
enum GPT12E_Mode_Timer_Prescaler TGPT12E_Mode_Timer_Prescaler
INLINE void GPT12E_T4_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:3080
INLINE uint16 GPT12E_T3_Value_Get(void)
reads Timer T3 Value.
Definition: gpt12e.h:1980
INLINE void GPT12E_T4_Int_Dis(void)
enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:4959
GPT12E_T4EUD
Definition: gpt12e.h:168
@ GPT12E_T4EUDA_P03
Definition: gpt12e.h:169
@ GPT12E_T4EUDB_P10
Definition: gpt12e.h:170
INLINE void GPT12E_T5_Start(void)
starts Timer T5.
Definition: gpt12e.h:3775
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2687
INLINE void GPT12E_T5_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t5i)
selects T5 Gated Timer Mode Parameter.
Definition: gpt12e.h:3315
INLINE uint8 GPT12E_T3_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1894
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_En(void)
enables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3459
INLINE void GPT12E_T5_DownCount_Sel(void)
selects Timer T5 counts down.
Definition: gpt12e.h:3847
INLINE void GPT12E_T5_Value_Set(uint16 t5)
sets Timer T5 Value.
Definition: gpt12e.h:3940
INLINE void GPT12E_T5_Cleared_On_Capture_En(void)
enables clearing T5 on a Capture Event.
Definition: gpt12e.h:3717
INLINE void GPT12E_T4_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t4i)
selects T4 Gated Timer Mode Parameter.
Definition: gpt12e.h:2219
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1915
INLINE void GPT12E_T3_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T3 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:1871
INLINE void GPT12E_T6_Value_Set(uint16 t6)
sets Timer T6 Value.
Definition: gpt12e.h:4469
INLINE void GPT12E_T2_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:1290
INLINE void GPT12E_CapRel_Int_En(void)
enables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5074
INLINE void GPT12E_T6_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t6i)
selects T6 Gated Timer Mode Parameter.
Definition: gpt12e.h:4092
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2273
INLINE void GPT12E_T2_Mode_Capture_Sel(void)
selects T2 Capture Mode.
Definition: gpt12e.h:409
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:3036
INLINE void GPT12E_T3_Mode_Counter_Sel(void)
selects T3 Counter Mode.
Definition: gpt12e.h:1408
INLINE void GPT12E_T2_Start(void)
starts Timer T2.
Definition: gpt12e.h:1041
INLINE void GPT12E_T4_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T4 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:2920
INLINE void GPT12E_T2_Int_Dis(void)
disables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:4867
enum GPT12E_T2IN TGPT12E_T2IN
INLINE void GPT12E_T2_Mode_Counter_Input_T3Out_Sel(void)
selects T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:591
INLINE void GPT12E_T2_Mode_Timer_Clk_Prescaler_Sel(uint16 t2i)
selects T2 Timer Mode Parameter.
Definition: gpt12e.h:463
INLINE uint8 GPT12E_T2_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1225
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:609
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:789
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:987
INLINE uint8 GPT12E_T4_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:3015
INLINE void GPT12E_T6_Output_Dis(void)
disables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:4322
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2453
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_En(void)
enables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3680
GPT12E_Mode_Timer_Prescaler
Definition: gpt12e.h:235
@ GPT_Clk_Div_2
Definition: gpt12e.h:237
@ GPT_Clk_Div_16
Definition: gpt12e.h:240
@ GPT_Clk_Div_64
Definition: gpt12e.h:242
@ GPT_Clk_Div_8
Definition: gpt12e.h:239
@ GPT_Clk_Div_32
Definition: gpt12e.h:241
@ GPT_Clk_Div_1
Definition: gpt12e.h:236
@ GPT_Clk_Div_128
Definition: gpt12e.h:243
@ GPT_Clk_Div_4
Definition: gpt12e.h:238
enum GPT12E_T5IN TGPT12E_T5IN
INLINE uint8 GPT12E_T4_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:3059
INLINE void GPT12E_T3_Output_Dis(void)
disables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:1728
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_En(void)
enables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3586
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:1023
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2633
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2579
INLINE void GPT12E_T3_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:1817
INLINE void GPT12E_T4_UpCount_Sel(void)
selects Timer T4 counts up.
Definition: gpt12e.h:2849
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1606
INLINE void GPT12E_T4_Clr_T2_Dis(void)
Disables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2956
INLINE void GPT12E_GPT2_Clk_Prescaler_Sel(uint16 bps2)
selects GPT2 Block Prescaler.
Definition: gpt12e.h:3183
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2669
INLINE void GPT12E_T3_Start(void)
starts Timer T3.
Definition: gpt12e.h:1677
enum GPT12E_T5EUD TGPT12E_T5EUD
INLINE void GPT12E_T5_Capture_Trig_CapIn_Sel(void)
selects CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3529
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1660
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_Dis(void)
disables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1588
INLINE void GPT12E_T3_Stop(void)
stops Timer T3.
Definition: gpt12e.h:1694
INLINE uint16 GPT12E_GPT2_Clk_Prescaler_Get(void)
reads GPT2 Block Prescaler.
Definition: gpt12e.h:3204
INLINE void GPT12E_T2_Mode_Counter_Input_T2In_Sel(void)
selects T2In as T2 Counter Mode Input.
Definition: gpt12e.h:501
GPT12E_T2IN
Definition: gpt12e.h:119
@ GPT12E_T2INA_P12
Definition: gpt12e.h:120
@ GPT12E_T2INB_P14
Definition: gpt12e.h:121
INLINE void GPT12E_T5_T5In_Sel(uint16 ist5in)
selects Input for T2IN.
Definition: gpt12e.h:3961
INLINE void GPT12E_T6_DownCount_Sel(void)
selects Timer T6 counts down.
Definition: gpt12e.h:4376
enum GPT12E_T6EUD TGPT12E_T6EUD
GPT12E_CCU6_SEL
Definition: gpt12e.h:100
@ GPT12E_CCU6_T12_CM_CH1
Definition: gpt12e.h:107
@ GPT12E_CCU6_T13_PM
Definition: gpt12e.h:109
@ GPT12E_CCU6_T13_CM
Definition: gpt12e.h:111
@ GPT12E_CCU6_T13_ZM
Definition: gpt12e.h:110
@ GPT12E_CCU6_CH1
Definition: gpt12e.h:102
@ GPT12E_CCU6_ANY_CHx
Definition: gpt12e.h:112
@ GPT12E_CCU6_T12_CM_CH0
Definition: gpt12e.h:106
@ GPT12E_CCU6_CH0
Definition: gpt12e.h:101
@ GPT12E_CCU6_CH2
Definition: gpt12e.h:103
@ GPT12E_CCU6_T12_ZM
Definition: gpt12e.h:104
@ GPT12E_CCU6_T12_PM
Definition: gpt12e.h:105
@ GPT12E_CCU6_T12_CM_CH2
Definition: gpt12e.h:108
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Sel(void)
selects T2 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:443
INLINE uint8 GPT12E_T4_Int_Sts(void)
reads GPT Module 1 Timer 4 interrupt Status.
Definition: gpt12e.h:4610
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Sel(void)
selects T3 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:1476
INLINE void GPT12E_T5_UpCount_Sel(void)
selects Timer T5 counts up.
Definition: gpt12e.h:3865
#define GPT12E
Definition: tle987x.h:6065
#define SCU
Definition: tle987x.h:6071
#define SCU_GPT12ICLR_CRC_Msk
Definition: tle987x.h:8932
#define GPT12E_PISEL_IST5EUD_Msk
Definition: tle987x.h:7967
#define GPT12E_T6CON_T6UD_Pos
Definition: tle987x.h:8086
#define GPT12E_T6_T6_Pos
Definition: tle987x.h:8077
#define GPT12E_T6CON_T6UDE_Pos
Definition: tle987x.h:8088
#define GPT12E_PISEL_IST4IN_Msk
Definition: tle987x.h:7961
#define GPT12E_T2CON_T2EDGE_Msk
Definition: tle987x.h:7993
#define GPT12E_PISEL_IST3EUD_Pos
Definition: tle987x.h:7958
#define GPT12E_T4CON_T4CHDIR_Pos
Definition: tle987x.h:8048
#define GPT12E_T2CON_T2UD_Pos
Definition: tle987x.h:7984
#define SCU_GPT12IEN_T5IE_Msk
Definition: tle987x.h:8949
#define GPT12E_PISEL_IST4EUD_Pos
Definition: tle987x.h:7962
#define GPT12E_T3CON_T3OTL_Pos
Definition: tle987x.h:8014
#define GPT12E_PISEL_ISCAPIN_Msk
Definition: tle987x.h:7973
#define GPT12E_T5CON_T5UD_Msk
Definition: tle987x.h:8063
#define GPT12E_CAPREL_CAPREL_Pos
Definition: tle987x.h:7944
#define SCU_GPT12IRC_T6_Msk
Definition: tle987x.h:8960
#define GPT12E_T3CON_T3UD_Pos
Definition: tle987x.h:8008
#define GPT12E_T5CON_T5I_Msk
Definition: tle987x.h:8057
#define SCU_GPT12ICLR_T2C_Pos
Definition: tle987x.h:8941
#define GPT12E_T3CON_T3EDGE_Pos
Definition: tle987x.h:8018
#define SCU_GPT12IEN_T3IE_Pos
Definition: tle987x.h:8952
#define GPT12E_T3CON_T3UDE_Pos
Definition: tle987x.h:8010
#define GPT12E_T2_T2_Msk
Definition: tle987x.h:7976
#define SCU_GPT12ICLR_T2C_Msk
Definition: tle987x.h:8942
#define GPT12E_T4_T4_Pos
Definition: tle987x.h:8025
#define GPT12E_T3CON_BPS1_Msk
Definition: tle987x.h:8017
#define GPT12E_T2CON_T2I_Pos
Definition: tle987x.h:7978
#define GPT12E_T4CON_T4EDGE_Msk
Definition: tle987x.h:8047
#define GPT12E_PISEL_IST4EUD_Msk
Definition: tle987x.h:7963
#define SCU_GPT12IEN_CRIE_Pos
Definition: tle987x.h:8944
#define GPT12E_T6CON_T6CLR_Msk
Definition: tle987x.h:8097
#define SCU_GPT12PISEL_GPT12_Msk
Definition: tle987x.h:8975
#define GPT12E_T3CON_T3OE_Pos
Definition: tle987x.h:8012
#define SCU_GPT12ICLR_T3C_Msk
Definition: tle987x.h:8940
#define GPT12E_T4CON_T4RC_Pos
Definition: tle987x.h:8038
#define GPT12E_T6CON_BPS2_Pos
Definition: tle987x.h:8094
#define GPT12E_T6CON_T6CLR_Pos
Definition: tle987x.h:8096
#define GPT12E_T3CON_BPS1_Pos
Definition: tle987x.h:8016
#define GPT12E_PISEL_IST6IN_Msk
Definition: tle987x.h:7969
#define GPT12E_T3CON_T3OTL_Msk
Definition: tle987x.h:8015
#define GPT12E_PISEL_IST3IN_Pos
Definition: tle987x.h:7956
#define SCU_GPT12ICLR_T3C_Pos
Definition: tle987x.h:8939
#define GPT12E_PISEL_ISCAPIN_Pos
Definition: tle987x.h:7972
#define GPT12E_T3_T3_Msk
Definition: tle987x.h:8000
#define GPT12E_T3CON_T3UD_Msk
Definition: tle987x.h:8009
#define GPT12E_T4CON_T4UDE_Msk
Definition: tle987x.h:8037
#define GPT12E_T4CON_T4M_Pos
Definition: tle987x.h:8030
#define GPT12E_T3CON_T3I_Pos
Definition: tle987x.h:8002
#define SCU_GPT12IRC_T5_Pos
Definition: tle987x.h:8961
#define GPT12E_T2CON_T2UD_Msk
Definition: tle987x.h:7985
#define GPT12E_T3CON_T3M_Pos
Definition: tle987x.h:8004
#define GPT12E_T4CON_CLRT3EN_Pos
Definition: tle987x.h:8042
#define GPT12E_T3CON_T3CHDIR_Msk
Definition: tle987x.h:8021
#define SCU_GPT12IEN_T2IE_Pos
Definition: tle987x.h:8954
#define SCU_GPT12IRC_T3_Pos
Definition: tle987x.h:8965
#define SCU_GPT12IEN_T3IE_Msk
Definition: tle987x.h:8953
#define GPT12E_T4CON_T4UD_Msk
Definition: tle987x.h:8035
#define SCU_GPT12PISEL_GPT12_Pos
Definition: tle987x.h:8974
#define GPT12E_T2CON_T2RC_Msk
Definition: tle987x.h:7989
#define SCU_GPT12ICLR_T5C_Msk
Definition: tle987x.h:8936
#define GPT12E_T2CON_T2R_Msk
Definition: tle987x.h:7983
#define GPT12E_T4CON_CLRT2EN_Pos
Definition: tle987x.h:8040
#define GPT12E_T5CON_T5M_Pos
Definition: tle987x.h:8058
#define GPT12E_T3CON_T3RDIR_Msk
Definition: tle987x.h:8023
#define GPT12E_PISEL_IST6IN_Pos
Definition: tle987x.h:7968
#define GPT12E_T3_T3_Pos
Definition: tle987x.h:7999
#define GPT12E_PISEL_IST5IN_Msk
Definition: tle987x.h:7965
#define GPT12E_T5CON_T5RC_Pos
Definition: tle987x.h:8066
#define SCU_GPT12ICLR_T4C_Msk
Definition: tle987x.h:8938
#define SCU_GPT12IRC_T2_Pos
Definition: tle987x.h:8967
#define SCU_GPT12IEN_T4IE_Msk
Definition: tle987x.h:8951
#define GPT12E_PISEL_IST4IN_Pos
Definition: tle987x.h:7960
#define GPT12E_PISEL_IST2EUD_Msk
Definition: tle987x.h:7955
#define GPT12E_T5CON_T5I_Pos
Definition: tle987x.h:8056
#define GPT12E_T4CON_T4RDIR_Pos
Definition: tle987x.h:8050
#define GPT12E_PISEL_IST3EUD_Msk
Definition: tle987x.h:7959
#define GPT12E_T6CON_T6OE_Pos
Definition: tle987x.h:8090
#define GPT12E_T5CON_T5CLR_Pos
Definition: tle987x.h:8072
#define GPT12E_PISEL_IST6EUD_Pos
Definition: tle987x.h:7970
#define GPT12E_T6CON_T6UDE_Msk
Definition: tle987x.h:8089
#define GPT12E_T6CON_T6R_Msk
Definition: tle987x.h:8085
#define GPT12E_T5CON_T5M_Msk
Definition: tle987x.h:8059
#define GPT12E_T3CON_T3M_Msk
Definition: tle987x.h:8005
#define GPT12E_T3CON_T3CHDIR_Pos
Definition: tle987x.h:8020
#define GPT12E_T6CON_T6R_Pos
Definition: tle987x.h:8084
#define GPT12E_T6CON_T6M_Pos
Definition: tle987x.h:8082
#define GPT12E_T5CON_T5CLR_Msk
Definition: tle987x.h:8073
#define GPT12E_T3CON_T3R_Pos
Definition: tle987x.h:8006
#define GPT12E_T6CON_T6I_Msk
Definition: tle987x.h:8081
#define SCU_GPT12IEN_T6IE_Pos
Definition: tle987x.h:8946
#define GPT12E_T6CON_T6UD_Msk
Definition: tle987x.h:8087
#define GPT12E_T4CON_T4EDGE_Pos
Definition: tle987x.h:8046
#define SCU_GPT12ICLR_T4C_Pos
Definition: tle987x.h:8937
#define GPT12E_T4_T4_Msk
Definition: tle987x.h:8026
#define GPT12E_T2CON_T2RDIR_Msk
Definition: tle987x.h:7997
#define SCU_GPT12IRC_T4_Pos
Definition: tle987x.h:8963
#define SCU_GPT12IRC_T6_Pos
Definition: tle987x.h:8959
#define GPT12E_T2CON_T2UDE_Pos
Definition: tle987x.h:7986
#define GPT12E_T5CON_T5SC_Pos
Definition: tle987x.h:8074
#define GPT12E_PISEL_IST2IN_Pos
Definition: tle987x.h:7952
#define GPT12E_PISEL_IST2IN_Msk
Definition: tle987x.h:7953
#define GPT12E_T4CON_T4R_Pos
Definition: tle987x.h:8032
#define GPT12E_T5CON_CT3_Msk
Definition: tle987x.h:8069
#define GPT12E_T3CON_T3EDGE_Msk
Definition: tle987x.h:8019
#define GPT12E_T4CON_T4RDIR_Msk
Definition: tle987x.h:8051
#define SCU_GPT12IEN_T4IE_Pos
Definition: tle987x.h:8950
#define GPT12E_T2CON_T2I_Msk
Definition: tle987x.h:7979
#define GPT12E_T6CON_T6SR_Msk
Definition: tle987x.h:8099
#define SCU_GPT12ICLR_T6C_Pos
Definition: tle987x.h:8933
#define GPT12E_T6CON_T6OTL_Pos
Definition: tle987x.h:8092
#define SCU_GPT12IRC_T2_Msk
Definition: tle987x.h:8968
#define GPT12E_T2CON_T2CHDIR_Msk
Definition: tle987x.h:7995
#define SCU_GPT12ICLR_T5C_Pos
Definition: tle987x.h:8935
#define GPT12E_T6CON_T6M_Msk
Definition: tle987x.h:8083
#define GPT12E_PISEL_IST6EUD_Msk
Definition: tle987x.h:7971
#define GPT12E_T3CON_T3I_Msk
Definition: tle987x.h:8003
#define GPT12E_CAPREL_CAPREL_Msk
Definition: tle987x.h:7945
#define SCU_GPT12IRC_T4_Msk
Definition: tle987x.h:8964
#define GPT12E_T5CON_T5UDE_Msk
Definition: tle987x.h:8065
#define GPT12E_PISEL_IST2EUD_Pos
Definition: tle987x.h:7954
#define GPT12E_PISEL_IST5IN_Pos
Definition: tle987x.h:7964
#define GPT12E_T2CON_T2EDGE_Pos
Definition: tle987x.h:7992
#define GPT12E_T4CON_T4UD_Pos
Definition: tle987x.h:8034
#define GPT12E_T2CON_T2CHDIR_Pos
Definition: tle987x.h:7994
#define SCU_GPT12IRC_T3_Msk
Definition: tle987x.h:8966
#define GPT12E_T5_T5_Msk
Definition: tle987x.h:8054
#define GPT12E_T4CON_T4I_Pos
Definition: tle987x.h:8028
#define GPT12E_T5CON_T5UD_Pos
Definition: tle987x.h:8062
#define GPT12E_PISEL_IST5EUD_Pos
Definition: tle987x.h:7966
#define GPT12E_T2_T2_Pos
Definition: tle987x.h:7975
#define GPT12E_T3CON_T3R_Msk
Definition: tle987x.h:8007
#define GPT12E_T4CON_CLRT2EN_Msk
Definition: tle987x.h:8041
#define SCU_GPT12ICLR_T6C_Msk
Definition: tle987x.h:8934
#define GPT12E_T3CON_T3OE_Msk
Definition: tle987x.h:8013
#define GPT12E_T5CON_T5R_Pos
Definition: tle987x.h:8060
#define GPT12E_T4CON_CLRT3EN_Msk
Definition: tle987x.h:8043
#define GPT12E_T5_T5_Pos
Definition: tle987x.h:8053
#define GPT12E_T6CON_T6I_Pos
Definition: tle987x.h:8080
#define GPT12E_T6_T6_Msk
Definition: tle987x.h:8078
#define SCU_GPT12IRC_CR_Msk
Definition: tle987x.h:8958
#define SCU_GPT12IEN_T5IE_Pos
Definition: tle987x.h:8948
#define SCU_GPT12IRC_T5_Msk
Definition: tle987x.h:8962
#define SCU_GPT12IEN_T6IE_Msk
Definition: tle987x.h:8947
#define SCU_GPT12IRC_CR_Pos
Definition: tle987x.h:8957
#define GPT12E_T5CON_T5RC_Msk
Definition: tle987x.h:8067
#define GPT12E_T5CON_T5R_Msk
Definition: tle987x.h:8061
#define GPT12E_T4CON_T4M_Msk
Definition: tle987x.h:8031
#define GPT12E_T5CON_T5SC_Msk
Definition: tle987x.h:8075
#define GPT12E_T4CON_T4I_Msk
Definition: tle987x.h:8029
#define GPT12E_T5CON_T5UDE_Pos
Definition: tle987x.h:8064
#define GPT12E_T2CON_T2R_Pos
Definition: tle987x.h:7982
#define GPT12E_T3CON_T3UDE_Msk
Definition: tle987x.h:8011
#define GPT12E_T2CON_T2RDIR_Pos
Definition: tle987x.h:7996
#define GPT12E_T4CON_T4UDE_Pos
Definition: tle987x.h:8036
#define GPT12E_T2CON_T2M_Pos
Definition: tle987x.h:7980
#define GPT12E_T4CON_T4CHDIR_Msk
Definition: tle987x.h:8049
#define SCU_GPT12IEN_T2IE_Msk
Definition: tle987x.h:8955
#define GPT12E_T6CON_BPS2_Msk
Definition: tle987x.h:8095
#define GPT12E_PISEL_IST3IN_Msk
Definition: tle987x.h:7957
#define SCU_GPT12IEN_CRIE_Msk
Definition: tle987x.h:8945
#define GPT12E_T2CON_T2RC_Pos
Definition: tle987x.h:7988
#define GPT12E_T3CON_T3RDIR_Pos
Definition: tle987x.h:8022
#define GPT12E_T6CON_T6OTL_Msk
Definition: tle987x.h:8093
#define GPT12E_T6CON_T6SR_Pos
Definition: tle987x.h:8098
#define GPT12E_T4CON_T4RC_Msk
Definition: tle987x.h:8039
#define GPT12E_T2CON_T2UDE_Msk
Definition: tle987x.h:7987
#define GPT12E_T5CON_CT3_Pos
Definition: tle987x.h:8068
#define GPT12E_T6CON_T6OE_Msk
Definition: tle987x.h:8091
#define SCU_GPT12ICLR_CRC_Pos
Definition: tle987x.h:8931
#define GPT12E_T4CON_T4R_Msk
Definition: tle987x.h:8033
#define GPT12E_T2CON_T2M_Msk
Definition: tle987x.h:7981
SFR low level access library.
INLINE void Field_Wrt16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:327
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:322
INLINE uint8 u1_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 1-bit field of a 16-bit register.
Definition: sfr_access.h:387
INLINE void Field_Mod16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:342
INLINE uint8 u1_Field_Rd8(const volatile uint8 *reg, uint8 pos, uint8 msk)
This function reads a 1-bit field of a 8-bit register.
Definition: sfr_access.h:382
INLINE uint16 u16_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 16-bit field of a 16-bit register.
Definition: sfr_access.h:412
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:132
uint8_t uint8
8 bit unsigned value
Definition: types.h:137
uint16_t uint16
16 bit unsigned value
Definition: types.h:138
uint32_t uint32
32 bit unsigned value
Definition: types.h:139