Infineon MOTIX™ MCU TLE987x Device Family SDK
tle987x.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** **
43 ** Initials Name **
44 ** ---------------------------------------------------------------------------**
45 ** BG Blandine Guillot **
46 ** JO Julia Ott **
47 *******************************************************************************/
48 
49 /*******************************************************************************
50 ** Revision Control History **
51 ********************************************************************************
52 ** V3.0.4: 2020-04-15, BG: Initial version of revision history **
53 ** V3.0.5: 2020-07-16, JO: EP-392: Added field ADC2->CTRL2.bit.SEL_TS_COUNT **
54 ** V3.0.6: 2020-07-14, JO: EP-431: Added '#pragma clang diagnostic ignored' **
55 ** to disable compiler warnings (-Wpadded, **
56 ** -Wcovered-switch-default, -Wself-assign) for **
57 ** ARMCC v6 **
58 ** V3.0.7: 2020-07-21, BG: EP-439: Formatted .h/.c files **
59 ** V3.0.8: 2021-08-25, JO: EP-919: Corrected ADC2 Ch assignment comments **
60 ** V3.0.9: 2022-02-28, JO: EP-936: Updated copyright and branding **
61 *******************************************************************************/
62 
63 
74 #ifndef TLE987X_H
75 #define TLE987X_H
76 
77 #ifdef __cplusplus
78 extern "C" {
79 #endif
80 
81 
88 /* =========================================================================================================================== */
89 /* ================ Interrupt Number Definition ================ */
90 /* =========================================================================================================================== */
91 
92 typedef enum
93 {
94  /* ======================================= ARM Cortex-M3 Specific Interrupt Numbers ======================================== */
95  Reset_IRQn = -15,
98  MemoryManagement_IRQn = -12,
100  BusFault_IRQn = -11,
103  SVCall_IRQn = -5,
105  PendSV_IRQn = -2,
107  /* ========================================== TLE987x Specific Interrupt Numbers =========================================== */
108  GPT1_Int = 0,
109  GPT2_Int = 1,
116  SSC1_Int = 8,
117  SSC2_Int = 9,
121  EXINT1_Int = 13,
122  BDRV_CP_Int = 14,
123  DMA_Int = 15
125 
126 
127 
128 /* =========================================================================================================================== */
129 /* ================ Processor and Core Peripheral Section ================ */
130 /* =========================================================================================================================== */
131 
132 /* =========================== Configuration of the ARM Cortex-M3 Processor and Core Peripherals =========================== */
133 #define __CM3_REV 0x0000U
134 #define __NVIC_PRIO_BITS 4
135 #define __Vendor_SysTickConfig 0
136 #define __MPU_PRESENT 0
137 #define __FPU_PRESENT 0 /* End of group Configuration_of_CMSIS */
141 
142 #include "core_cm3.h"
143 #include "system_tle987x.h"
145 #ifndef __IM
146 #define __IM __I
147 #endif
148 #ifndef __OM
149 #define __OM __O
150 #endif
151 #ifndef __IOM
152 #define __IOM __IO
153 #endif
154 
155 #ifdef UNIT_TESTING_LV2
156 #undef __IM
157 #define __IM volatile
158 #endif
159 
160 /* Ignore the following warnings from ARMCC v6:
161 * - tle987x.h: warning: padding size of 'struct ...' with ... bits to alignment boundary [-Wpadded] (~1000 occurences)
162 * - dma.c: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default] (2 occurences)
163 * - scu.c: warning: explicitly assigning value of variable of type 'uint8' (aka 'unsigned char') to itself [-Wself-assign] (2 occurences)
164 */
165 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6000000)
166 #pragma clang diagnostic push
167 #pragma clang diagnostic ignored "-Wpadded"
168 #pragma clang diagnostic ignored "-Wcovered-switch-default"
169 #pragma clang diagnostic ignored "-Wself-assign"
170 #endif
171 
172 /* =========================================================================================================================== */
173 /* ================ Device Specific Peripheral Section ================ */
174 /* =========================================================================================================================== */
175 
176 
183 /* =========================================================================================================================== */
184 /* ================ ADC1 ================ */
185 /* =========================================================================================================================== */
186 
187 
192 typedef struct
193 {
194 
195  union
196  {
197  __IOM uint32_t reg;
199  struct
200  {
201  __IOM uint32_t PD_N : 1;
203  __IOM uint32_t SOC : 1;
204  __IM uint32_t EOC : 1;
205  __IOM uint32_t IN_MUX_SEL : 3;
206  } bit;
207  } CTRL_STS;
208 
209  union
210  {
211  __IOM uint32_t reg;
213  struct
214  {
215  __IOM uint32_t DIVA : 6;
218  __IM uint32_t : 2;
219  __IOM uint32_t ANON : 2;
220  } bit;
221  } GLOBCTR;
222 
223  union
224  {
225  __IOM uint32_t reg;
228  struct
229  {
230  __IOM uint32_t CHx : 3;
231  __IM uint32_t : 1;
232  __IOM uint32_t REP : 3;
233  __IM uint32_t : 9;
234  __IOM uint32_t TRIG_SEL : 3;
236  } bit;
237  } CHx_EIM;
238 
239  union
240  {
241  __IOM uint32_t reg;
244  struct
245  {
246  __IOM uint32_t ESM_0 : 8;
248  __IM uint32_t : 8;
249  __IOM uint32_t TRIG_SEL : 3;
251  } bit;
252  } CHx_ESM;
253  __IM uint32_t RESERVED[2];
254 
255  union
256  {
257  __IOM uint32_t reg;
260  struct
261  {
262  __IOM uint32_t SQ1 : 8;
263  __IOM uint32_t SQ2 : 8;
264  __IOM uint32_t SQ3 : 8;
265  __IOM uint32_t SQ4 : 8;
266  } bit;
267  } SQ1_4;
268 
269  union
270  {
271  __IOM uint32_t reg;
274  struct
275  {
276  __IOM uint32_t SQ5 : 8;
277  __IOM uint32_t SQ6 : 8;
278  __IOM uint32_t SQ7 : 8;
279  __IOM uint32_t SQ8 : 8;
280  } bit;
281  } SQ5_8;
282  __IM uint32_t RESERVED1;
283 
284  union
285  {
286  __IOM uint32_t reg;
288  struct
289  {
290  __IOM uint32_t ch0 : 1;
291  __IOM uint32_t ch1 : 1;
292  __IOM uint32_t ch2 : 1;
293  __IOM uint32_t ch3 : 1;
294  __IOM uint32_t ch4 : 1;
295  __IOM uint32_t ch5 : 1;
296  __IOM uint32_t ch6 : 1;
297  __IOM uint32_t ch7 : 1;
298  } bit;
299  } DWSEL;
300 
301  union
302  {
303  __IOM uint32_t reg;
305  struct
306  {
307  __IOM uint32_t ch0 : 8;
308  __IOM uint32_t ch1 : 8;
309  __IOM uint32_t ch2 : 8;
310  __IOM uint32_t ch3 : 8;
311  } bit;
312  } STC_0_3;
313 
314  union
315  {
316  __IOM uint32_t reg;
318  struct
319  {
320  __IOM uint32_t ch4 : 8;
321  __IOM uint32_t ch5 : 8;
322  __IOM uint32_t ch6 : 8;
323  __IOM uint32_t ch7 : 8;
324  } bit;
325  } STC_4_7;
326  __IM uint32_t RESERVED2[4];
327 
328  union
329  {
330  __IOM uint32_t reg;
332  struct
333  {
334  __IM uint32_t OUT_CH_EIM : 12;
335  __IM uint32_t : 4;
336  __IOM uint32_t WFR8 : 1;
337  __IM uint32_t VF8 : 1;
338  __IM uint32_t OF8 : 1;
339  } bit;
340  } RES_OUT_EIM;
341  __IM uint32_t RESERVED3[3];
342 
343  union
344  {
345  __IOM uint32_t reg;
347  struct
348  {
349  __IM uint32_t : 8;
350  __IOM uint32_t SQ_RUN : 1;
351  __IM uint32_t EIM_ACTIVE : 1;
352  __IM uint32_t ESM_ACTIVE : 1;
353  __IM uint32_t SQx : 3;
354  __IM uint32_t : 2;
355  __IM uint32_t CHx : 3;
356  } bit;
357  } SQ_FB;
358 
359  union
360  {
361  __IOM uint32_t reg;
363  struct
364  {
365  __IM uint32_t OUT_CH7 : 12;
366  __IM uint32_t : 4;
367  __IOM uint32_t WFR7 : 1;
368  __IM uint32_t VF7 : 1;
369  __IM uint32_t OF7 : 1;
370  } bit;
371  } RES_OUT7;
372 
373  union
374  {
375  __IOM uint32_t reg;
377  struct
378  {
379  __IM uint32_t OUT_CH6 : 12;
380  __IM uint32_t : 4;
381  __IOM uint32_t WFR6 : 1;
382  __IM uint32_t VF6 : 1;
383  __IM uint32_t OF6 : 1;
384  } bit;
385  } RES_OUT6;
386 
387  union
388  {
389  __IOM uint32_t reg;
391  struct
392  {
393  __IM uint32_t OUT_CH5 : 12;
394  __IM uint32_t : 4;
395  __IOM uint32_t WFR5 : 1;
396  __IM uint32_t VF5 : 1;
397  __IM uint32_t OF5 : 1;
398  } bit;
399  } RES_OUT5;
400 
401  union
402  {
403  __IOM uint32_t reg;
405  struct
406  {
407  __IM uint32_t OUT_CH4 : 12;
408  __IM uint32_t : 4;
409  __IOM uint32_t WFR4 : 1;
410  __IM uint32_t VF4 : 1;
411  __IM uint32_t OF4 : 1;
412  } bit;
413  } RES_OUT4;
414 
415  union
416  {
417  __IOM uint32_t reg;
419  struct
420  {
421  __IM uint32_t OUT_CH3 : 12;
422  __IM uint32_t : 4;
423  __IOM uint32_t WFR3 : 1;
424  __IM uint32_t VF3 : 1;
425  __IM uint32_t OF3 : 1;
426  } bit;
427  } RES_OUT3;
428 
429  union
430  {
431  __IOM uint32_t reg;
433  struct
434  {
435  __IM uint32_t OUT_CH2 : 12;
436  __IM uint32_t : 4;
437  __IOM uint32_t WFR2 : 1;
438  __IM uint32_t VF2 : 1;
439  __IM uint32_t OF2 : 1;
440  } bit;
441  } RES_OUT2;
442 
443  union
444  {
445  __IOM uint32_t reg;
447  struct
448  {
449  __IM uint32_t OUT_CH1 : 12;
450  __IM uint32_t : 4;
451  __IOM uint32_t WFR1 : 1;
452  __IM uint32_t VF1 : 1;
453  __IM uint32_t OF1 : 1;
454  } bit;
455  } RES_OUT1;
456 
457  union
458  {
459  __IOM uint32_t reg;
461  struct
462  {
463  __IM uint32_t OUT_CH0 : 12;
464  __IM uint32_t : 4;
465  __IOM uint32_t WFR0 : 1;
466  __IM uint32_t VF0 : 1;
467  __IM uint32_t OF0 : 1;
468  } bit;
469  } RES_OUT0;
470 
471  union
472  {
473  __IOM uint32_t reg;
475  struct
476  {
477  __IM uint32_t BUSY : 1;
478  __IM uint32_t SAMPLE : 1;
479  __IM uint32_t : 1;
480  __IM uint32_t CHNR : 3;
481  __IM uint32_t : 2;
482  __IM uint32_t ANON_ST : 2;
483  } bit;
484  } GLOBSTR;
485 
486  union
487  {
488  __IOM uint32_t reg;
490  struct
491  {
492  __IM uint32_t CH0_STS : 1;
493  __IM uint32_t CH1_STS : 1;
494  __IM uint32_t CH2_STS : 1;
495  __IM uint32_t CH3_STS : 1;
496  __IM uint32_t CH4_STS : 1;
497  __IM uint32_t CH5_STS : 1;
498  __IM uint32_t CH6_STS : 1;
499  __IM uint32_t CH7_STS : 1;
500  __IM uint32_t EIM_STS : 1;
501  __IM uint32_t ESM_STS : 1;
502  } bit;
503  } IS;
504 
505  union
506  {
507  __IOM uint32_t reg;
509  struct
510  {
511  __IOM uint32_t CH0_IE : 1;
512  __IOM uint32_t CH1_IE : 1;
513  __IOM uint32_t CH2_IE : 1;
514  __IOM uint32_t CH3_IE : 1;
515  __IOM uint32_t CH4_IE : 1;
516  __IOM uint32_t CH5_IE : 1;
517  __IOM uint32_t CH6_IE : 1;
518  __IOM uint32_t CH7_IE : 1;
519  __IOM uint32_t EIM_IE : 1;
520  __IOM uint32_t ESM_IE : 1;
521  } bit;
522  } IE;
523 
524  union
525  {
526  __IOM uint32_t reg;
528  struct
529  {
530  __OM uint32_t CH0_ICLR : 1;
531  __OM uint32_t CH1_ICLR : 1;
532  __OM uint32_t CH2_ICLR : 1;
533  __OM uint32_t CH3_ICLR : 1;
534  __OM uint32_t CH4_ICLR : 1;
535  __OM uint32_t CH5_ICLR : 1;
536  __OM uint32_t CH6_ICLR : 1;
537  __OM uint32_t CH7_ICLR : 1;
538  __OM uint32_t EIM_ICLR : 1;
539  __OM uint32_t ESM_ICLR : 1;
540  } bit;
541  } ICLR;
542 } ADC1_Type;
546 /* =========================================================================================================================== */
547 /* ================ ADC2 ================ */
548 /* =========================================================================================================================== */
549 
550 
555 typedef struct
556 {
557 
558  union
559  {
560  __IOM uint32_t reg;
562  struct
563  {
565  __IOM uint32_t VS_RANGE : 1;
566  } bit;
567  } CTRL_STS;
568 
569  union
570  {
571  __IOM uint32_t reg;
573  struct
574  {
575  __IM uint32_t SQ_FB : 4;
576  __IM uint32_t : 4;
577  __IM uint32_t SQ_STOP : 1;
578  __IM uint32_t EIM_ACTIVE : 1;
579  __IM uint32_t ESM_ACTIVE : 1;
580  __IM uint32_t SQx : 4;
581  __IM uint32_t : 1;
582  __IM uint32_t CHx : 5;
583  } bit;
584  } SQ_FB;
585 
586  union
587  {
588  __IOM uint32_t reg;
591  struct
592  {
593  __IOM uint32_t CHx : 5;
594  __IM uint32_t : 3;
595  __IOM uint32_t REP : 3;
596  __IOM uint32_t EN : 1;
598  __IOM uint32_t SEL : 1;
600  } bit;
601  } CHx_EIM;
602 
603  union
604  {
605  __IOM uint32_t reg;
608  struct
609  {
610  __IOM uint32_t ESM_0 : 6;
612  __IOM uint32_t ESM_1 : 4;
614  __IOM uint32_t SEL : 1;
615  __IM uint32_t : 5;
616  __IOM uint32_t EN : 1;
618  __IM uint32_t STS : 1;
619  } bit;
620  } CHx_ESM;
621  __IM uint32_t RESERVED;
622 
623  union
624  {
625  __IOM uint32_t reg;
627  struct
628  {
629  __IOM uint32_t CALIB_EN : 6;
630  } bit;
631  } CTRL1;
632 
633  union
634  {
635  __IOM uint32_t reg;
637  struct
638  {
639  __IOM uint32_t MCM_PD_N : 1;
640  __IOM uint32_t TS_SD_SEL_CONF : 1;
641  __IOM uint32_t TSENSE_SD_SEL : 1;
642  __IM uint32_t : 4;
643  __IM uint32_t MCM_RDY : 1;
644  __IOM uint32_t SAMPLE_TIME_int : 4;
645  __IM uint32_t : 4;
646  __IOM uint32_t SEL_TS_COUNT : 4;
647  } bit;
648  } CTRL2;
649 
650  union
651  {
652  __IOM uint32_t reg;
654  struct
655  {
656  __IOM uint32_t FILT_OUT_SEL_5_0 : 6;
657  __IM uint32_t : 2;
658  __IOM uint32_t FILT_OUT_SEL_9_6 : 4;
659  } bit;
660  } CTRL4;
661 
662  union
663  {
664  __IOM uint32_t reg;
666  struct
667  {
668  __IOM uint32_t SQ1 : 6;
669  __IM uint32_t : 2;
670  __IOM uint32_t SQ2 : 6;
671  __IM uint32_t : 2;
672  __IOM uint32_t SQ3 : 6;
673  __IM uint32_t : 2;
674  __IOM uint32_t SQ4 : 6;
675  } bit;
676  } SQ1_4;
677 
678  union
679  {
680  __IOM uint32_t reg;
683  struct
684  {
685  __IOM uint32_t SQ5 : 6;
686  __IM uint32_t : 2;
687  __IOM uint32_t SQ6 : 6;
688  __IM uint32_t : 2;
689  __IOM uint32_t SQ7 : 6;
690  __IM uint32_t : 2;
691  __IOM uint32_t SQ8 : 6;
692  } bit;
693  } SQ5_8;
694 
695  union
696  {
697  __IOM uint32_t reg;
700  struct
701  {
702  __IOM uint32_t SQ9 : 6;
703  __IM uint32_t : 2;
704  __IOM uint32_t SQ10 : 6;
705  } bit;
706  } SQ9_10;
707 
708  union
709  {
710  __IOM uint32_t reg;
713  struct
714  {
715  __IM uint32_t SQ1_int : 4;
716  __IM uint32_t SQ2_int : 4;
717  __IM uint32_t SQ3_int : 4;
718  __IM uint32_t SQ4_int : 4;
719  __IM uint32_t SQ5_int : 4;
720  __IM uint32_t SQ6_int : 4;
721  __IM uint32_t SQ7_int : 4;
722  __IM uint32_t SQ8_int : 4;
723  } bit;
724  } SQ1_8_int;
725 
726  union
727  {
728  __IOM uint32_t reg;
731  struct
732  {
733  __IM uint32_t SQ9_int : 4;
734  __IM uint32_t SQ10_int : 4;
735  } bit;
736  } SQ9_10_int;
737 
738  union
739  {
740  __IOM uint32_t reg;
742  struct
743  {
744  __IOM uint32_t OFFS_CH0 : 8;
745  __IOM uint32_t GAIN_CH0 : 8;
746  __IOM uint32_t OFFS_CH1 : 8;
747  __IOM uint32_t GAIN_CH1 : 8;
748  } bit;
749  } CAL_CH0_1;
750 
751  union
752  {
753  __IOM uint32_t reg;
755  struct
756  {
757  __IOM uint32_t OFFS_CH2 : 8;
758  __IOM uint32_t GAIN_CH2 : 8;
759  __IOM uint32_t OFFS_CH3 : 8;
760  __IOM uint32_t GAIN_CH3 : 8;
761  } bit;
762  } CAL_CH2_3;
763 
764  union
765  {
766  __IOM uint32_t reg;
768  struct
769  {
770  __IOM uint32_t OFFS_CH4 : 8;
771  __IOM uint32_t GAIN_CH4 : 8;
772  __IOM uint32_t OFFS_CH5 : 8;
773  __IOM uint32_t GAIN_CH5 : 8;
774  } bit;
775  } CAL_CH4_5;
776 
777  union
778  {
779  __IOM uint32_t reg;
781  struct
782  {
783  __IM uint32_t OFFS_CH6 : 8;
784  __IM uint32_t GAIN_CH6 : 8;
785  __IM uint32_t OFFS_CH7 : 8;
786  __IM uint32_t GAIN_CH7 : 8;
787  } bit;
788  } CAL_CH6_7;
789 
790  union
791  {
792  __IOM uint32_t reg;
794  struct
795  {
796  __IM uint32_t OFFS_CH8 : 8;
797  __IM uint32_t GAIN_CH8 : 8;
798  __IM uint32_t OFFS_CH9 : 8;
799  __IM uint32_t GAIN_CH9 : 8;
800  } bit;
801  } CAL_CH8_9;
802 
803  union
804  {
805  __IOM uint32_t reg;
807  struct
808  {
809  __IOM uint32_t CH0 : 2;
810  __IOM uint32_t CH1 : 2;
811  __IOM uint32_t CH2 : 2;
812  __IOM uint32_t CH3 : 2;
813  __IOM uint32_t CH4 : 2;
814  __IOM uint32_t CH5 : 2;
815  } bit;
816  } FILTCOEFF0_5;
817 
818  union
819  {
820  __IOM uint32_t reg;
822  struct
823  {
824  __IM uint32_t CH6 : 2;
825  __IM uint32_t CH7 : 2;
826  __IM uint32_t CH8 : 2;
827  __IM uint32_t CH9 : 2;
828  } bit;
829  } FILTCOEFF6_9;
830 
831  union
832  {
833  __IOM uint32_t reg;
835  struct
836  {
837  __IM uint32_t OUT_CH0 : 10;
838  } bit;
839  } FILT_OUT0;
840 
841  union
842  {
843  __IOM uint32_t reg;
845  struct
846  {
847  __IM uint32_t OUT_CH1 : 10;
848  } bit;
849  } FILT_OUT1;
850 
851  union
852  {
853  __IOM uint32_t reg;
855  struct
856  {
857  __IM uint32_t OUT_CH2 : 10;
858  } bit;
859  } FILT_OUT2;
860 
861  union
862  {
863  __IOM uint32_t reg;
865  struct
866  {
867  __IM uint32_t OUT_CH3 : 10;
868  } bit;
869  } FILT_OUT3;
870 
871  union
872  {
873  __IOM uint32_t reg;
875  struct
876  {
877  __IM uint32_t OUT_CH4 : 10;
878  } bit;
879  } FILT_OUT4;
880 
881  union
882  {
883  __IOM uint32_t reg;
885  struct
886  {
887  __IM uint32_t OUT_CH5 : 10;
888  } bit;
889  } FILT_OUT5;
890 
891  union
892  {
893  __IOM uint32_t reg;
895  struct
896  {
897  __IM uint32_t OUT_CH6 : 10;
898  } bit;
899  } FILT_OUT6;
900 
901  union
902  {
903  __IOM uint32_t reg;
905  struct
906  {
907  __IM uint32_t OUT_CH7 : 10;
908  } bit;
909  } FILT_OUT7;
910 
911  union
912  {
913  __IOM uint32_t reg;
915  struct
916  {
917  __IM uint32_t OUT_CH8 : 10;
918  } bit;
919  } FILT_OUT8;
920 
921  union
922  {
923  __IOM uint32_t reg;
925  struct
926  {
927  __IM uint32_t OUT_CH9 : 10;
928  } bit;
929  } FILT_OUT9;
930 
931  union
932  {
933  __IOM uint32_t reg;
935  struct
936  {
937  __IOM uint32_t Ch0_EN : 1;
938  __IOM uint32_t Ch1_EN : 1;
939  __IOM uint32_t Ch2_EN : 1;
940  __IOM uint32_t Ch3_EN : 1;
941  __IOM uint32_t Ch4_EN : 1;
942  __IOM uint32_t Ch5_EN : 1;
943  } bit;
944  } FILT_UP_CTRL;
945 
946  union
947  {
948  __IOM uint32_t reg;
950  struct
951  {
952  __IOM uint32_t Ch0_EN : 1;
953  __IOM uint32_t Ch1_EN : 1;
954  __IOM uint32_t Ch2_EN : 1;
955  __IOM uint32_t Ch3_EN : 1;
956  __IOM uint32_t Ch4_EN : 1;
957  __IOM uint32_t Ch5_EN : 1;
958  } bit;
959  } FILT_LO_CTRL;
960 
961  union
962  {
963  __IOM uint32_t reg;
965  struct
966  {
967  __IOM uint32_t CH0 : 8;
968  __IOM uint32_t CH1 : 8;
969  __IOM uint32_t CH2 : 8;
970  __IOM uint32_t CH3 : 8;
971  } bit;
972  } TH0_3_LOWER;
973 
974  union
975  {
976  __IOM uint32_t reg;
979  struct
980  {
981  __IOM uint32_t CH4 : 8;
982  __IOM uint32_t CH5 : 8;
983  } bit;
984  } TH4_5_LOWER;
985 
986  union
987  {
988  __IOM uint32_t reg;
990  struct
991  {
992  __IOM uint32_t CH6 : 8;
993  __IM uint32_t CH7 : 8;
994  __IOM uint32_t CH8 : 8;
995  __IOM uint32_t CH9 : 8;
996  } bit;
997  } TH6_9_LOWER;
998 
999  union
1000  {
1001  __IOM uint32_t reg;
1003  struct
1004  {
1005  __IOM uint32_t CH0 : 8;
1006  __IOM uint32_t CH1 : 8;
1007  __IOM uint32_t CH2 : 8;
1008  __IOM uint32_t CH3 : 8;
1009  } bit;
1010  } TH0_3_UPPER;
1011 
1012  union
1013  {
1014  __IOM uint32_t reg;
1016  struct
1017  {
1018  __IOM uint32_t CH4 : 8;
1019  __IOM uint32_t CH5 : 8;
1020  } bit;
1021  } TH4_5_UPPER;
1022 
1023  union
1024  {
1025  __IOM uint32_t reg;
1027  struct
1028  {
1029  __IM uint32_t CH6 : 8;
1030  __IM uint32_t CH7 : 8;
1031  __IM uint32_t CH8 : 8;
1032  __IM uint32_t CH9 : 8;
1033  } bit;
1034  } TH6_9_UPPER;
1035 
1036  union
1037  {
1038  __IOM uint32_t reg;
1040  struct
1041  {
1042  __IOM uint32_t CNT_LO_CH0 : 3;
1043  __IOM uint32_t HYST_LO_CH0 : 2;
1044  __IM uint32_t : 3;
1045  __IOM uint32_t CNT_LO_CH1 : 3;
1046  __IOM uint32_t HYST_LO_CH1 : 2;
1047  __IM uint32_t : 3;
1048  __IOM uint32_t CNT_LO_CH2 : 3;
1049  __IOM uint32_t HYST_LO_CH2 : 2;
1050  __IM uint32_t : 3;
1051  __IOM uint32_t CNT_LO_CH3 : 3;
1052  __IOM uint32_t HYST_LO_CH3 : 2;
1053  } bit;
1054  } CNT0_3_LOWER;
1055 
1056  union
1057  {
1058  __IOM uint32_t reg;
1060  struct
1061  {
1062  __IOM uint32_t CNT_LO_CH4 : 3;
1063  __IOM uint32_t HYST_LO_CH4 : 2;
1064  __IM uint32_t : 3;
1065  __IOM uint32_t CNT_LO_CH5 : 3;
1066  __IOM uint32_t HYST_LO_CH5 : 2;
1067  } bit;
1068  } CNT4_5_LOWER;
1069 
1070  union
1071  {
1072  __IOM uint32_t reg;
1074  struct
1075  {
1076  __IM uint32_t CNT_LO_CH6 : 3;
1077  __IM uint32_t HYST_LO_CH6 : 2;
1078  __IM uint32_t : 3;
1079  __IM uint32_t CNT_LO_CH7 : 3;
1080  __IM uint32_t HYST_LO_CH7 : 2;
1081  __IM uint32_t : 3;
1082  __IM uint32_t CNT_LO_CH8 : 3;
1083  __IM uint32_t HYST_LO_CH8 : 2;
1084  __IM uint32_t : 3;
1085  __IM uint32_t CNT_LO_CH9 : 3;
1086  __IM uint32_t HYST_LO_CH9 : 2;
1087  } bit;
1088  } CNT6_9_LOWER;
1089 
1090  union
1091  {
1092  __IOM uint32_t reg;
1094  struct
1095  {
1096  __IOM uint32_t CNT_UP_CH0 : 3;
1097  __IOM uint32_t HYST_UP_CH0 : 2;
1098  __IM uint32_t : 3;
1099  __IOM uint32_t CNT_UP_CH1 : 3;
1100  __IOM uint32_t HYST_UP_CH1 : 2;
1101  __IM uint32_t : 3;
1102  __IOM uint32_t CNT_UP_CH2 : 3;
1103  __IOM uint32_t HYST_UP_CH2 : 2;
1104  __IM uint32_t : 3;
1105  __IOM uint32_t CNT_UP_CH3 : 3;
1106  __IOM uint32_t HYST_UP_CH3 : 2;
1107  } bit;
1108  } CNT0_3_UPPER;
1109 
1110  union
1111  {
1112  __IOM uint32_t reg;
1114  struct
1115  {
1116  __IOM uint32_t CNT_UP_CH4 : 3;
1117  __IOM uint32_t HYST_UP_CH4 : 2;
1118  __IM uint32_t : 3;
1119  __IOM uint32_t CNT_UP_CH5 : 3;
1120  __IOM uint32_t HYST_UP_CH5 : 2;
1121  } bit;
1122  } CNT4_5_UPPER;
1123 
1124  union
1125  {
1126  __IOM uint32_t reg;
1128  struct
1129  {
1130  __IM uint32_t CNT_UP_CH6 : 3;
1131  __IM uint32_t HYST_UP_CH6 : 2;
1132  __IM uint32_t : 3;
1133  __IM uint32_t CNT_UP_CH7 : 3;
1134  __IM uint32_t HYST_UP_CH7 : 2;
1135  __IM uint32_t : 3;
1136  __IM uint32_t CNT_UP_CH8 : 3;
1137  __IM uint32_t HYST_UP_CH8 : 2;
1138  __IM uint32_t : 3;
1139  __IM uint32_t CNT_UP_CH9 : 3;
1140  __IM uint32_t HYST_UP_CH9 : 2;
1141  } bit;
1142  } CNT6_9_UPPER;
1143 
1144  union
1145  {
1146  __IOM uint32_t reg;
1148  struct
1149  {
1150  __IOM uint32_t Ch0 : 2;
1151  __IOM uint32_t Ch1 : 2;
1152  __IOM uint32_t Ch2 : 2;
1153  __IOM uint32_t Ch3 : 2;
1154  __IOM uint32_t Ch4 : 2;
1155  __IOM uint32_t Ch5 : 2;
1156  } bit;
1157  } MMODE0_5;
1158  __IM uint32_t RESERVED1[2];
1159 
1160  union
1161  {
1162  __IOM uint32_t reg;
1164  struct
1165  {
1166  __IM uint32_t : 1;
1167  __IM uint32_t READY : 1;
1168  } bit;
1169  } HV_STS;
1170 } ADC2_Type;
1174 /* =========================================================================================================================== */
1175 /* ================ ADC34 ================ */
1176 /* =========================================================================================================================== */
1177 
1178 
1183 typedef struct
1184 {
1185 
1186  union
1187  {
1188  __IOM uint32_t reg;
1190  struct
1191  {
1192  __IOM uint32_t ADC3_EN : 1;
1193  __IOM uint32_t ADC3_OFS_MEAS_EN : 1;
1194  __IOM uint32_t ADC3_SOC : 1;
1197  __IM uint32_t ADC3_EoC_STS : 1;
1198  __IM uint32_t ADC34_DREQ_SEL : 2;
1199  __IM uint32_t : 4;
1200  __IOM uint32_t ADC34_REF_SEL : 1;
1201  __IOM uint32_t ADC3_OSR : 4;
1202  __IOM uint32_t ADC4_EN : 1;
1203  __IOM uint32_t ADC4_OFS_MEAS_EN : 1;
1204  __IOM uint32_t ADC4_SOC : 1;
1206  __IM uint32_t : 1;
1207  __IM uint32_t ADC4_EoC_STS : 1;
1208  __IOM uint32_t ADC34_EoC_CNT : 2;
1209  __IOM uint32_t ADC34_DITHEN : 1;
1210  __IOM uint32_t ADC34_DITHVAL : 4;
1211  __IOM uint32_t ADC4_OSR : 4;
1212  } bit;
1213  } CTRL_STS;
1214 
1215  union
1216  {
1217  __IOM uint32_t reg;
1219  struct
1220  {
1221  __IM uint32_t ADC3_RESU : 16;
1222  __IM uint32_t ADC4_RESU : 16;
1223  } bit;
1224  } RESU;
1225 } ADC34_Type;
1229 /* =========================================================================================================================== */
1230 /* ================ BDRV ================ */
1231 /* =========================================================================================================================== */
1232 
1233 
1238 typedef struct
1239 {
1240 
1241  union
1242  {
1243  __IOM uint32_t reg;
1245  struct
1246  {
1247  __IOM uint32_t LS1_EN : 1;
1248  __IOM uint32_t LS1_PWM : 1;
1249  __IOM uint32_t LS1_ON : 1;
1250  __IOM uint32_t LS1_DCS_EN : 1;
1251  __IM uint32_t LS1_DS_STS : 1;
1252  __IM uint32_t LS1_SUPERR_STS : 1;
1253  __IM uint32_t LS1_OC_STS : 1;
1254  __IOM uint32_t LS1_OC_DIS : 1;
1255  __IOM uint32_t LS2_EN : 1;
1256  __IOM uint32_t LS2_PWM : 1;
1257  __IOM uint32_t LS2_ON : 1;
1258  __IOM uint32_t LS2_DCS_EN : 1;
1259  __IM uint32_t LS2_DS_STS : 1;
1261  __IM uint32_t LS2_SUPERR_STS : 1;
1262  __IM uint32_t LS2_OC_STS : 1;
1263  __IOM uint32_t LS2_OC_DIS : 1;
1264  __IOM uint32_t HS1_EN : 1;
1265  __IOM uint32_t HS1_PWM : 1;
1266  __IOM uint32_t HS1_ON : 1;
1267  __IOM uint32_t HS1_DCS_EN : 1;
1268  __IM uint32_t HS1_DS_STS : 1;
1270  __IM uint32_t HS1_SUPERR_STS : 1;
1271  __IM uint32_t HS1_OC_STS : 1;
1272  __IOM uint32_t HS1_OC_DIS : 1;
1273  __IOM uint32_t HS2_EN : 1;
1274  __IOM uint32_t HS2_PWM : 1;
1275  __IOM uint32_t HS2_ON : 1;
1276  __IOM uint32_t HS2_DCS_EN : 1;
1277  __IM uint32_t HS2_DS_STS : 1;
1279  __IM uint32_t HS2_SUPERR_STS : 1;
1280  __IM uint32_t HS2_OC_STS : 1;
1281  __IOM uint32_t HS2_OC_DIS : 1;
1282  } bit;
1283  } CTRL1;
1284 
1285  union
1286  {
1287  __IOM uint32_t reg;
1289  struct
1290  {
1291  __IOM uint32_t LS3_EN : 1;
1292  __IOM uint32_t LS3_PWM : 1;
1293  __IOM uint32_t LS3_ON : 1;
1294  __IOM uint32_t LS3_DCS_EN : 1;
1295  __IM uint32_t LS3_DS_STS : 1;
1296  __IM uint32_t LS3_SUPERR_STS : 1;
1297  __IM uint32_t LS3_OC_STS : 1;
1298  __IOM uint32_t LS3_OC_DIS : 1;
1299  __IOM uint32_t HS3_EN : 1;
1300  __IOM uint32_t HS3_PWM : 1;
1301  __IOM uint32_t HS3_ON : 1;
1302  __IOM uint32_t HS3_DCS_EN : 1;
1303  __IM uint32_t HS3_DS_STS : 1;
1304  __IM uint32_t HS3_SUPERR_STS : 1;
1305  __IM uint32_t HS3_OC_STS : 1;
1306  __IOM uint32_t HS3_OC_DIS : 1;
1307  __IM uint32_t DLY_DIAG_TIM : 10;
1308  __OM uint32_t DLY_DIAG_SCLR : 1;
1309  __IM uint32_t DLY_DIAG_STS : 1;
1310  __IOM uint32_t DLY_DIAG_CHSEL : 3;
1311  __IOM uint32_t DLY_DIAG_DIRSEL : 1;
1312  } bit;
1313  } CTRL2;
1314 
1315  union
1316  {
1317  __IOM uint32_t reg;
1319  struct
1320  {
1321  __IOM uint32_t ICHARGE_TRIM : 5;
1323  __IOM uint32_t ICHARGEDIV2_N : 1;
1324  __IOM uint32_t ON_SEQ_EN : 1;
1325  __IOM uint32_t IDISCHARGE_TRIM : 5;
1326  __IM uint32_t : 1;
1327  __IOM uint32_t IDISCHARGEDIV2_N : 1;
1328  __IOM uint32_t OFF_SEQ_EN : 1;
1329  __IOM uint32_t DSMONVTH : 3;
1331  __IM uint32_t : 5;
1332  __IOM uint32_t DRV_CCP_TIMSEL : 2;
1333  __IOM uint32_t DRV_CCP_DIS : 1;
1334  } bit;
1335  } CTRL3;
1336  __IM uint32_t RESERVED;
1337 
1338  union
1339  {
1340  __IOM uint32_t reg;
1342  struct
1343  {
1344  __IOM uint32_t DRV_OFF_t_4 : 3;
1345  __IOM uint32_t DRV_OFF_I_4 : 5;
1346  __IOM uint32_t DRV_OFF_t_3 : 3;
1347  __IOM uint32_t DRV_OFF_I_3 : 5;
1348  __IOM uint32_t DRV_OFF_t_2 : 3;
1349  __IOM uint32_t DRV_OFF_I_2 : 5;
1350  __IOM uint32_t DRV_OFF_t_1 : 3;
1351  __IOM uint32_t DRV_OFF_I_1 : 5;
1352  } bit;
1353  } OFF_SEQ_CTRL;
1354 
1355  union
1356  {
1357  __IOM uint32_t reg;
1359  struct
1360  {
1361  __IOM uint32_t DRV_ON_t_4 : 3;
1362  __IOM uint32_t DRV_ON_I_4 : 5;
1363  __IOM uint32_t DRV_ON_t_3 : 3;
1364  __IOM uint32_t DRV_ON_I_3 : 5;
1365  __IOM uint32_t DRV_ON_t_2 : 3;
1366  __IOM uint32_t DRV_ON_I_2 : 5;
1367  __IOM uint32_t DRV_ON_t_1 : 3;
1368  __IOM uint32_t DRV_ON_I_1 : 5;
1369  } bit;
1370  } ON_SEQ_CTRL;
1371 
1372  union
1373  {
1374  __IOM uint32_t reg;
1376  struct
1377  {
1378  __IOM uint32_t LS_HS_BT_TFILT_SEL : 2;
1380  __IM uint32_t : 3;
1381  __IOM uint32_t DRV_CCPTIMMUL : 2;
1383  __IM uint32_t : 1;
1384  __IOM uint32_t LSDRV_DS_TFILT_SEL : 2;
1385  __IOM uint32_t LS1DRV_FDISCHG_DIS : 1;
1386  __IOM uint32_t LS2DRV_FDISCHG_DIS : 1;
1387  __IOM uint32_t LS3DRV_FDISCHG_DIS : 1;
1388  __IOM uint32_t LS1DRV_OCSDN_DIS : 1;
1389  __IOM uint32_t LS2DRV_OCSDN_DIS : 1;
1390  __IOM uint32_t LS3DRV_OCSDN_DIS : 1;
1391  __IOM uint32_t HSDRV_DS_TFILT_SEL : 2;
1393  __IOM uint32_t HS1DRV_FDISCHG_DIS : 1;
1394  __IOM uint32_t HS2DRV_FDISCHG_DIS : 1;
1395  __IOM uint32_t HS3DRV_FDISCHG_DIS : 1;
1396  __IOM uint32_t HS1DRV_OCSDN_DIS : 1;
1397  __IOM uint32_t HS2DRV_OCSDN_DIS : 1;
1398  __IOM uint32_t HS3DRV_OCSDN_DIS : 1;
1399  __IOM uint32_t CPLOW_TFILT_SEL : 2;
1400  } bit;
1401  } TRIM_DRVx;
1402  __IM uint32_t RESERVED1;
1403 
1404  union
1405  {
1406  __IOM uint32_t reg;
1408  struct
1409  {
1410  __IOM uint32_t CP_EN : 1;
1411  __IM uint32_t : 1;
1412  __IOM uint32_t CP_RDY_EN : 1;
1413  __IM uint32_t : 2;
1414  __IM uint32_t VCP_LOTH2_STS : 1;
1415  __IM uint32_t : 2;
1416  __IOM uint32_t VCP_LOWTH2 : 3;
1418  __IM uint32_t : 5;
1419  __IOM uint32_t DRVx_VCPLO_DIS : 1;
1420  __IM uint32_t VCP_LOTH1_STS : 1;
1421  __IOM uint32_t DRVx_VCPUP_DIS : 1;
1422  __IM uint32_t VCP_UPTH_STS : 1;
1423  __IOM uint32_t DRVx_VSDLO_DIS : 1;
1424  __IM uint32_t VSD_LOTH_STS : 1;
1425  __IOM uint32_t DRVx_VSDUP_DIS : 1;
1426  __IM uint32_t VSD_UPTH_STS : 1;
1427  __IOM uint32_t CPLOPWRM_EN : 1;
1428  __IOM uint32_t VCP9V_SET : 1;
1429  __IOM uint32_t VTHVCP9V_TRIM : 2;
1430  } bit;
1431  } CP_CTRL_STS;
1432 
1433  union
1434  {
1435  __IOM uint32_t reg;
1437  struct
1438  {
1439  __IOM uint32_t DITH_LOWER : 5;
1440  __IM uint32_t : 3;
1441  __IOM uint32_t DITH_UPPER : 5;
1442  __IOM uint32_t F_CP : 2;
1443  __IOM uint32_t CPCLK_EN : 1;
1444  } bit;
1445  } CP_CLK_CTRL;
1446 } BDRV_Type;
1450 /* =========================================================================================================================== */
1451 /* ================ CCU6 ================ */
1452 /* =========================================================================================================================== */
1453 
1454 
1459 typedef struct
1460 {
1461 
1462  union
1463  {
1464  __IOM uint16_t reg;
1466  struct
1467  {
1468  __IM uint16_t CCV : 16;
1469  } bit;
1470  } CC63R;
1471  __IM uint16_t RESERVED;
1472 
1473  union
1474  {
1475  __IOM uint16_t reg;
1477  struct
1478  {
1479  __OM uint16_t T12RR : 1;
1480  __OM uint16_t T12RS : 1;
1481  __OM uint16_t T12RES : 1;
1482  __OM uint16_t DTRES : 1;
1484  __OM uint16_t T12CNT : 1;
1485  __OM uint16_t T12STR : 1;
1486  __OM uint16_t T12STD : 1;
1487  __OM uint16_t T13RR : 1;
1488  __OM uint16_t T13RS : 1;
1489  __OM uint16_t T13RES : 1;
1490  __IM uint16_t : 2;
1491  __OM uint16_t T13CNT : 1;
1492  __OM uint16_t T13STR : 1;
1493  __OM uint16_t T13STD : 1;
1494  } bit;
1495  } TCTR4;
1496  __IM uint16_t RESERVED1;
1497 
1498  union
1499  {
1500  __IOM uint16_t reg;
1502  struct
1503  {
1504  __IOM uint16_t MCMPS : 6;
1505  __IM uint16_t : 1;
1506  __IOM uint16_t STRMCM : 1;
1507  __IOM uint16_t EXPHS : 3;
1508  __IOM uint16_t CURHS : 3;
1509  __IM uint16_t : 1;
1510  __IOM uint16_t STRHP : 1;
1511  } bit;
1512  } MCMOUTS;
1513  __IM uint16_t RESERVED2;
1514 
1515  union
1516  {
1517  __IOM uint16_t reg;
1519  struct
1520  {
1521  __OM uint16_t RCC60R : 1;
1522  __OM uint16_t RCC60F : 1;
1523  __OM uint16_t RCC61R : 1;
1524  __OM uint16_t RCC61F : 1;
1525  __OM uint16_t RCC62R : 1;
1526  __OM uint16_t RCC62F : 1;
1527  __OM uint16_t RT12OM : 1;
1528  __OM uint16_t RT12PM : 1;
1529  __OM uint16_t RT13CM : 1;
1530  __OM uint16_t RT13PM : 1;
1531  __OM uint16_t RTRPF : 1;
1532  __IM uint16_t : 1;
1533  __OM uint16_t RCHE : 1;
1534  __OM uint16_t RWHE : 1;
1535  __OM uint16_t RIDLE : 1;
1536  __OM uint16_t RSTR : 1;
1537  } bit;
1538  } ISR;
1539  __IM uint16_t RESERVED3;
1540 
1541  union
1542  {
1543  __IOM uint16_t reg;
1545  struct
1546  {
1547  __OM uint16_t MCC60S : 1;
1549  __OM uint16_t MCC61S : 1;
1551  __OM uint16_t MCC62S : 1;
1553  __IM uint16_t : 3;
1554  __OM uint16_t MCC63S : 1;
1556  __IM uint16_t : 1;
1557  __OM uint16_t MCC60R : 1;
1559  __OM uint16_t MCC61R : 1;
1561  __OM uint16_t MCC62R : 1;
1563  __IM uint16_t : 3;
1564  __OM uint16_t MCC63R : 1;
1566  } bit;
1567  } CMPMODIF;
1568  __IM uint16_t RESERVED4;
1569 
1570  union
1571  {
1572  __IOM uint16_t reg;
1574  struct
1575  {
1576  __IOM uint16_t CCS : 16;
1577  } bit;
1578  } CC60SR;
1579  __IM uint16_t RESERVED5;
1580 
1581  union
1582  {
1583  __IOM uint16_t reg;
1585  struct
1586  {
1587  __IOM uint16_t CCS : 16;
1588  } bit;
1589  } CC61SR;
1590  __IM uint16_t RESERVED6;
1591 
1592  union
1593  {
1594  __IOM uint16_t reg;
1596  struct
1597  {
1598  __IOM uint16_t CCS : 16;
1599  } bit;
1600  } CC62SR;
1601  __IM uint16_t RESERVED7;
1602 
1603  union
1604  {
1605  __IOM uint16_t reg;
1607  struct
1608  {
1609  __IOM uint16_t CCS : 16;
1610  } bit;
1611  } CC63SR;
1612  __IM uint16_t RESERVED8;
1613 
1614  union
1615  {
1616  __IOM uint16_t reg;
1618  struct
1619  {
1620  __IOM uint16_t T12PV : 16;
1621  } bit;
1622  } T12PR;
1623  __IM uint16_t RESERVED9;
1624 
1625  union
1626  {
1627  __IOM uint16_t reg;
1629  struct
1630  {
1631  __IOM uint16_t T13PV : 16;
1632  } bit;
1633  } T13PR;
1634  __IM uint16_t RESERVED10;
1635 
1636  union
1637  {
1638  __IOM uint16_t reg;
1640  struct
1641  {
1642  __IOM uint16_t DTM : 8;
1643  __IOM uint16_t DTE0 : 1;
1644  __IOM uint16_t DTE1 : 1;
1645  __IOM uint16_t DTE2 : 1;
1646  __IM uint16_t : 1;
1647  __IM uint16_t DTR0 : 1;
1648  __IM uint16_t DTR1 : 1;
1649  __IM uint16_t DTR2 : 1;
1650  } bit;
1651  } T12DTC;
1652  __IM uint16_t RESERVED11;
1653 
1654  union
1655  {
1656  __IOM uint16_t reg;
1658  struct
1659  {
1660  __IOM uint16_t T12CLK : 3;
1661  __IOM uint16_t T12PRE : 1;
1662  __IM uint16_t T12R : 1;
1663  __IM uint16_t STE12 : 1;
1664  __IM uint16_t CDIR : 1;
1665  __IOM uint16_t CTM : 1;
1666  __IOM uint16_t T13CLK : 3;
1667  __IOM uint16_t T13PRE : 1;
1668  __IM uint16_t T13R : 1;
1669  __IM uint16_t STE13 : 1;
1670  } bit;
1671  } TCTR0;
1672  __IM uint16_t RESERVED12;
1673 
1674  union
1675  {
1676  __IOM uint16_t reg;
1678  struct
1679  {
1680  __IM uint16_t CCV : 16;
1681  } bit;
1682  } CC60R;
1683  __IM uint16_t RESERVED13;
1684 
1685  union
1686  {
1687  __IOM uint16_t reg;
1689  struct
1690  {
1691  __IM uint16_t CCV : 16;
1692  } bit;
1693  } CC61R;
1694  __IM uint16_t RESERVED14;
1695 
1696  union
1697  {
1698  __IOM uint16_t reg;
1700  struct
1701  {
1702  __IM uint16_t CCV : 16;
1703  } bit;
1704  } CC62R;
1705  __IM uint16_t RESERVED15;
1706 
1707  union
1708  {
1709  __IOM uint16_t reg;
1711  struct
1712  {
1713  __IOM uint16_t MSEL60 : 4;
1714  __IOM uint16_t MSEL61 : 4;
1715  __IOM uint16_t MSEL62 : 4;
1716  __IOM uint16_t HSYNC : 3;
1717  __IOM uint16_t DBYP : 1;
1718  } bit;
1719  } T12MSEL;
1720  __IM uint16_t RESERVED16;
1721 
1722  union
1723  {
1724  __IOM uint16_t reg;
1726  struct
1727  {
1728  __IOM uint16_t ENCC60R : 1;
1730  __IOM uint16_t ENCC60F : 1;
1732  __IOM uint16_t ENCC61R : 1;
1734  __IOM uint16_t ENCC61F : 1;
1736  __IOM uint16_t ENCC62R : 1;
1738  __IOM uint16_t ENCC62F : 1;
1740  __IOM uint16_t ENT12OM : 1;
1741  __IOM uint16_t ENT12PM : 1;
1742  __IOM uint16_t ENT13CM : 1;
1743  __IOM uint16_t ENT13PM : 1;
1744  __IOM uint16_t ENTRPF : 1;
1745  __IM uint16_t : 1;
1746  __IOM uint16_t ENCHE : 1;
1747  __IOM uint16_t ENWHE : 1;
1748  __IOM uint16_t ENIDLE : 1;
1749  __IOM uint16_t ENSTR : 1;
1750  } bit;
1751  } IEN;
1752  __IM uint16_t RESERVED17;
1753 
1754  union
1755  {
1756  __IOM uint16_t reg;
1758  struct
1759  {
1760  __IOM uint16_t INPCC60 : 2;
1761  __IOM uint16_t INPCC61 : 2;
1762  __IOM uint16_t INPCC62 : 2;
1763  __IOM uint16_t INPCHE : 2;
1764  __IOM uint16_t INPERR : 2;
1765  __IOM uint16_t INPT12 : 2;
1766  __IOM uint16_t INPT13 : 2;
1767  } bit;
1768  } INP;
1769  __IM uint16_t RESERVED18;
1770 
1771  union
1772  {
1773  __IOM uint16_t reg;
1775  struct
1776  {
1777  __OM uint16_t SCC60R : 1;
1778  __OM uint16_t SCC60F : 1;
1779  __OM uint16_t SCC61R : 1;
1780  __OM uint16_t SCC61F : 1;
1781  __OM uint16_t SCC62R : 1;
1782  __OM uint16_t SCC62F : 1;
1783  __OM uint16_t ST12OM : 1;
1784  __OM uint16_t ST12PM : 1;
1785  __OM uint16_t ST13CM : 1;
1786  __OM uint16_t ST13PM : 1;
1787  __OM uint16_t STRPF : 1;
1788  __OM uint16_t SWHC : 1;
1789  __OM uint16_t SCHE : 1;
1790  __OM uint16_t SWHE : 1;
1791  __OM uint16_t SIDLE : 1;
1792  __OM uint16_t SSTR : 1;
1793  } bit;
1794  } ISS;
1795  __IM uint16_t RESERVED19;
1796 
1797  union
1798  {
1799  __IOM uint16_t reg;
1801  struct
1802  {
1803  __IOM uint16_t PSL : 6;
1804  __IM uint16_t : 1;
1805  __IOM uint16_t PSL63 : 1;
1806  } bit;
1807  } PSLR;
1808  __IM uint16_t RESERVED20;
1809 
1810  union
1811  {
1812  __IOM uint16_t reg;
1814  struct
1815  {
1816  __IOM uint16_t SWSEL : 3;
1817  __IM uint16_t : 1;
1818  __IOM uint16_t SWSYN : 2;
1819  __IM uint16_t : 2;
1820  __IOM uint16_t STE12U : 1;
1821  __IOM uint16_t STE12D : 1;
1822  __IOM uint16_t STE13U : 1;
1823  } bit;
1824  } MCMCTR;
1825  __IM uint16_t RESERVED21;
1826 
1827  union
1828  {
1829  __IOM uint16_t reg;
1831  struct
1832  {
1833  __IOM uint16_t T12SSC : 1;
1834  __IOM uint16_t T13SSC : 1;
1835  __IOM uint16_t T13TEC : 3;
1836  __IOM uint16_t T13TED : 2;
1837  __IM uint16_t : 1;
1838  __IOM uint16_t T12RSEL : 2;
1839  __IOM uint16_t T13RSEL : 2;
1840  } bit;
1841  } TCTR2;
1842  __IM uint16_t RESERVED22;
1843 
1844  union
1845  {
1846  __IOM uint16_t reg;
1848  struct
1849  {
1850  __IOM uint16_t T12MODEN : 6;
1851  __IM uint16_t : 1;
1852  __IOM uint16_t MCMEN : 1;
1853  __IOM uint16_t T13MODEN : 6;
1854  __IM uint16_t : 1;
1855  __IOM uint16_t ECT13O : 1;
1856  } bit;
1857  } MODCTR;
1858  __IM uint16_t RESERVED23;
1859 
1860  union
1861  {
1862  __IOM uint16_t reg;
1864  struct
1865  {
1866  __IOM uint16_t TRPM0 : 1;
1867  __IOM uint16_t TRPM1 : 1;
1868  __IOM uint16_t TRPM2 : 1;
1869  __IM uint16_t : 5;
1870  __IOM uint16_t TRPEN : 6;
1871  __IOM uint16_t TRPEN13 : 1;
1872  __IOM uint16_t TRPPEN : 1;
1873  } bit;
1874  } TRPCTR;
1875  __IM uint16_t RESERVED24;
1876 
1877  union
1878  {
1879  __IOM uint16_t reg;
1881  struct
1882  {
1883  __IM uint16_t MCMP : 6;
1884  __IM uint16_t R : 1;
1885  __IM uint16_t : 1;
1886  __IM uint16_t EXPH : 3;
1887  __IM uint16_t CURH : 3;
1888  } bit;
1889  } MCMOUT;
1890  __IM uint16_t RESERVED25;
1891 
1892  union
1893  {
1894  __IOM uint16_t reg;
1896  struct
1897  {
1898  __IM uint16_t ICC60R : 1;
1899  __IM uint16_t ICC60F : 1;
1900  __IM uint16_t ICC61R : 1;
1901  __IM uint16_t ICC61F : 1;
1902  __IM uint16_t ICC62R : 1;
1903  __IM uint16_t ICC62F : 1;
1904  __IM uint16_t T12OM : 1;
1905  __IM uint16_t T12PM : 1;
1906  __IM uint16_t T13CM : 1;
1907  __IM uint16_t T13PM : 1;
1908  __IM uint16_t TRPF : 1;
1909  __IM uint16_t TRPS : 1;
1910  __IM uint16_t CHE : 1;
1911  __IM uint16_t WHE : 1;
1912  __IM uint16_t IDLE : 1;
1913  __IM uint16_t STR : 1;
1914  } bit;
1915  } IS;
1916  __IM uint16_t RESERVED26;
1917 
1918  union
1919  {
1920  __IOM uint16_t reg;
1922  struct
1923  {
1924  __IOM uint16_t ISCC60 : 2;
1925  __IOM uint16_t ISCC61 : 2;
1926  __IOM uint16_t ISCC62 : 2;
1927  __IOM uint16_t ISTRP : 2;
1928  __IOM uint16_t ISPOS0 : 2;
1929  __IOM uint16_t ISPOS1 : 2;
1930  __IOM uint16_t ISPOS2 : 2;
1931  __IOM uint16_t IST12HR : 2;
1932  } bit;
1933  } PISEL0;
1934  __IM uint16_t RESERVED27[3];
1935 
1936  union
1937  {
1938  __IOM uint16_t reg;
1940  struct
1941  {
1942  __IOM uint16_t IST13HR : 2;
1943  __IOM uint16_t ISCNT12 : 2;
1944  __IOM uint16_t ISCNT13 : 2;
1945  __IOM uint16_t T12EXT : 1;
1946  __IOM uint16_t T13EXT : 1;
1947  } bit;
1948  } PISEL2;
1949  __IM uint16_t RESERVED28;
1950 
1951  union
1952  {
1953  __IOM uint16_t reg;
1955  struct
1956  {
1957  __IOM uint16_t T12CV : 16;
1958  } bit;
1959  } T12;
1960  __IM uint16_t RESERVED29;
1961 
1962  union
1963  {
1964  __IOM uint16_t reg;
1966  struct
1967  {
1968  __IOM uint16_t T13CV : 16;
1969  } bit;
1970  } T13;
1971  __IM uint16_t RESERVED30;
1972 
1973  union
1974  {
1975  __IOM uint16_t reg;
1977  struct
1978  {
1979  __IM uint16_t CC60ST : 1;
1980  __IM uint16_t CC61ST : 1;
1981  __IM uint16_t CC62ST : 1;
1982  __IM uint16_t CCPOS0 : 1;
1983  __IM uint16_t CCPOS1 : 1;
1984  __IM uint16_t CCPOS2 : 1;
1985  __IM uint16_t CC63ST : 1;
1986  __IM uint16_t : 1;
1987  __IOM uint16_t CC60PS : 1;
1988  __IOM uint16_t COUT60PS : 1;
1989  __IOM uint16_t CC61PS : 1;
1990  __IOM uint16_t COUT61PS : 1;
1991  __IOM uint16_t CC62PS : 1;
1992  __IOM uint16_t COUT62PS : 1;
1993  __IOM uint16_t COUT63PS : 1;
1994  __IOM uint16_t T13IM : 1;
1995  } bit;
1996  } CMPSTAT;
1997 } CCU6_Type;
2001 /* =========================================================================================================================== */
2002 /* ================ CPU ================ */
2003 /* =========================================================================================================================== */
2004 
2005 
2010 typedef struct
2011 {
2012  __IM uint32_t RESERVED;
2013 
2014  union
2015  {
2016  __IOM uint32_t reg;
2018  struct
2019  {
2020  __IM uint32_t INTLINESNUM : 5;
2021  } bit;
2022  } ICT;
2023  __IM uint32_t RESERVED1[2];
2024 
2025  union
2026  {
2027  __IOM uint32_t reg;
2029  struct
2030  {
2031  __IOM uint32_t ENABLE : 1;
2032  __IOM uint32_t TICKINT : 1;
2033  __IOM uint32_t CLKSOURCE : 1;
2035  __IOM uint32_t COUNTFLAG : 1;
2036  } bit;
2037  } SYSTICK_CS;
2038 
2039  union
2040  {
2041  __IOM uint32_t reg;
2043  struct
2044  {
2045  __IOM uint32_t RELOAD : 24;
2046  } bit;
2047  } SYSTICK_RL;
2048 
2049  union
2050  {
2051  __IOM uint32_t reg;
2053  struct
2054  {
2055  __IOM uint32_t CURRENT : 24;
2056  } bit;
2057  } SYSTICK_CUR;
2058 
2059  union
2060  {
2061  __IOM uint32_t reg;
2063  struct
2064  {
2065  __IM uint32_t TENMS : 24;
2066  __IM uint32_t : 6;
2067  __IM uint32_t SKEW : 1;
2068  __IM uint32_t NOREF : 1;
2069  } bit;
2070  } SYSTICK_CAL;
2071  __IM uint32_t RESERVED2[56];
2072 
2073  union
2074  {
2075  __IOM uint32_t reg;
2077  struct
2078  {
2079  __IOM uint32_t Int_GPT1 : 1;
2080  __IOM uint32_t Int_GPT2 : 1;
2081  __IOM uint32_t Int_ADC2 : 1;
2082  __IOM uint32_t Int_ADC1 : 1;
2083  __IOM uint32_t Int_CCU6SR0 : 1;
2084  __IOM uint32_t Int_CCU6SR1 : 1;
2085  __IOM uint32_t Int_CCU6SR2 : 1;
2086  __IOM uint32_t Int_CCU6SR3 : 1;
2087  __IOM uint32_t Int_SSC1 : 1;
2088  __IOM uint32_t Int_SSC2 : 1;
2089  __IOM uint32_t Int_UART1 : 1;
2090  __IOM uint32_t Int_UART2 : 1;
2091  __IOM uint32_t Int_EXINT0 : 1;
2092  __IOM uint32_t Int_EXINT1 : 1;
2093  __IOM uint32_t Int_BDRV : 1;
2094  __IOM uint32_t Int_DMA : 1;
2095  } bit;
2096  } NVIC_ISER0;
2097  __IM uint32_t RESERVED3[31];
2098 
2099  union
2100  {
2101  __IOM uint32_t reg;
2103  struct
2104  {
2105  __IOM uint32_t Int_GPT1 : 1;
2106  __IOM uint32_t Int_GPT2 : 1;
2107  __IOM uint32_t Int_ADC2 : 1;
2108  __IOM uint32_t Int_ADC1 : 1;
2109  __IOM uint32_t Int_CCU6SR0 : 1;
2110  __IOM uint32_t Int_CCU6SR1 : 1;
2111  __IOM uint32_t Int_CCU6SR2 : 1;
2112  __IOM uint32_t Int_CCU6SR3 : 1;
2113  __IOM uint32_t Int_SSC1 : 1;
2114  __IOM uint32_t Int_SSC2 : 1;
2115  __IOM uint32_t Int_UART1 : 1;
2116  __IOM uint32_t Int_UART2 : 1;
2117  __IOM uint32_t Int_EXINT0 : 1;
2118  __IOM uint32_t Int_EXINT1 : 1;
2119  __IOM uint32_t Int_BDRV : 1;
2120  __IOM uint32_t Int_DMA : 1;
2121  } bit;
2122  } NVIC_ICER0;
2123  __IM uint32_t RESERVED4[31];
2124 
2125  union
2126  {
2127  __IOM uint32_t reg;
2129  struct
2130  {
2131  __IOM uint32_t Int_GPT1 : 1;
2132  __IOM uint32_t Int_GPT2 : 1;
2133  __IOM uint32_t Int_ADC2 : 1;
2134  __IOM uint32_t Int_ADC1 : 1;
2135  __IOM uint32_t Int_CCU6SR0 : 1;
2136  __IOM uint32_t Int_CCU6SR1 : 1;
2137  __IOM uint32_t Int_CCU6SR2 : 1;
2138  __IOM uint32_t Int_CCU6SR3 : 1;
2139  __IOM uint32_t Int_SSC1 : 1;
2140  __IOM uint32_t Int_SSC2 : 1;
2141  __IOM uint32_t Int_UART1 : 1;
2142  __IOM uint32_t Int_UART2 : 1;
2143  __IOM uint32_t Int_EXINT0 : 1;
2144  __IOM uint32_t Int_EXINT1 : 1;
2145  __IOM uint32_t Int_BDRV : 1;
2146  __IOM uint32_t Int_DMA : 1;
2147  } bit;
2148  } NVIC_ISPR0;
2149  __IM uint32_t RESERVED5[31];
2150 
2151  union
2152  {
2153  __IOM uint32_t reg;
2155  struct
2156  {
2157  __IOM uint32_t Int_GPT1 : 1;
2158  __IOM uint32_t Int_GPT2 : 1;
2159  __IOM uint32_t Int_ADC2 : 1;
2160  __IOM uint32_t Int_ADC1 : 1;
2161  __IOM uint32_t Int_CCU6SR0 : 1;
2162  __IOM uint32_t Int_CCU6SR1 : 1;
2163  __IOM uint32_t Int_CCU6SR2 : 1;
2164  __IOM uint32_t Int_CCU6SR3 : 1;
2165  __IOM uint32_t Int_SSC1 : 1;
2166  __IOM uint32_t Int_SSC2 : 1;
2167  __IOM uint32_t Int_UART1 : 1;
2168  __IOM uint32_t Int_UART2 : 1;
2169  __IOM uint32_t Int_EXINT0 : 1;
2170  __IOM uint32_t Int_EXINT1 : 1;
2171  __IOM uint32_t Int_BDRV : 1;
2172  __IOM uint32_t Int_DMA : 1;
2173  } bit;
2174  } NVIC_ICPR0;
2175  __IM uint32_t RESERVED6[31];
2176 
2177  union
2178  {
2179  __IOM uint32_t reg;
2181  struct
2182  {
2183  __IM uint32_t Int_GPT1 : 1;
2184  __IM uint32_t Int_GPT2 : 1;
2185  __IM uint32_t Int_ADC2 : 1;
2186  __IM uint32_t Int_ADC1 : 1;
2187  __IM uint32_t Int_CCU6SR0 : 1;
2188  __IM uint32_t Int_CCU6SR1 : 1;
2189  __IM uint32_t Int_CCU6SR2 : 1;
2190  __IM uint32_t Int_CCU6SR3 : 1;
2191  __IM uint32_t Int_SSC1 : 1;
2192  __IM uint32_t Int_SSC2 : 1;
2193  __IM uint32_t Int_UART1 : 1;
2194  __IM uint32_t Int_UART2 : 1;
2195  __IM uint32_t Int_EXINT0 : 1;
2196  __IM uint32_t Int_EXINT1 : 1;
2197  __IM uint32_t Int_BDRV : 1;
2198  __IM uint32_t Int_DMA : 1;
2199  } bit;
2200  } NVIC_IABR0;
2201  __IM uint32_t RESERVED7[63];
2202 
2203  union
2204  {
2205  __IOM uint32_t reg;
2207  struct
2208  {
2209  __IOM uint32_t PRI_GPT1 : 8;
2210  __IOM uint32_t PRI_GPT2 : 8;
2211  __IOM uint32_t PRI_ADC2 : 8;
2212  __IOM uint32_t PRI_ADC1 : 8;
2213  } bit;
2214  } NVIC_IPR0;
2215 
2216  union
2217  {
2218  __IOM uint32_t reg;
2220  struct
2221  {
2222  __IOM uint32_t PRI_CCU6SR0 : 8;
2223  __IOM uint32_t PRI_CCU6SR1 : 8;
2224  __IOM uint32_t PRI_CCU6SR2 : 8;
2225  __IOM uint32_t PRI_CCU6SR3 : 8;
2226  } bit;
2227  } NVIC_IPR1;
2228 
2229  union
2230  {
2231  __IOM uint32_t reg;
2233  struct
2234  {
2235  __IOM uint32_t PRI_SSC1 : 8;
2236  __IOM uint32_t PRI_SSC2 : 8;
2237  __IOM uint32_t PRI_UART1 : 8;
2238  __IOM uint32_t PRI_UART2 : 8;
2239  } bit;
2240  } NVIC_IPR2;
2241 
2242  union
2243  {
2244  __IOM uint32_t reg;
2246  struct
2247  {
2248  __IOM uint32_t PRI_EXINT0 : 8;
2249  __IOM uint32_t PRI_EXINT1 : 8;
2250  __IOM uint32_t PRI_BDRV : 8;
2251  __IOM uint32_t PRI_DMA : 8;
2252  } bit;
2253  } NVIC_IPR3;
2254  __IM uint32_t RESERVED8[572];
2255 
2256  union
2257  {
2258  __IOM uint32_t reg;
2260  struct
2261  {
2262  __IM uint32_t REVISION : 4;
2263  __IM uint32_t PARTNO : 12;
2264  __IM uint32_t ARCHITECTURE : 4;
2265  __IM uint32_t VARIANT : 4;
2266  __IM uint32_t IMPLEMENTER : 8;
2267  } bit;
2268  } CPUID;
2269 
2270  union
2271  {
2272  __IOM uint32_t reg;
2274  struct
2275  {
2276  __IM uint32_t VECTACTIVE : 9;
2277  __IM uint32_t : 2;
2278  __IM uint32_t RETTOBASE : 1;
2279  __IM uint32_t VECTPENDING : 9;
2280  __IM uint32_t : 1;
2281  __IM uint32_t ISRPENDING : 1;
2282  __IM uint32_t ISRPREEMPT : 1;
2283  __IM uint32_t : 1;
2284  __OM uint32_t PENDSTCLR : 1;
2285  __IOM uint32_t PENDSTSET : 1;
2286  __OM uint32_t PENDSVCLR : 1;
2287  __IOM uint32_t PENDSVSET : 1;
2288  __IM uint32_t : 2;
2289  __IOM uint32_t NMIPENDSET : 1;
2290  } bit;
2291  } ICSR;
2292 
2293  union
2294  {
2295  __IOM uint32_t reg;
2297  struct
2298  {
2299  __IM uint32_t : 7;
2300  __IOM uint32_t TBLOFF : 25;
2301  } bit;
2302  } VTOR;
2303 
2304  union
2305  {
2306  __IOM uint32_t reg;
2308  struct
2309  {
2310  __IOM uint32_t VECTRESET : 1;
2311  __IOM uint32_t VECTCLRACTIVE : 1;
2312  __IOM uint32_t SYSRESETREQ : 1;
2313  __IM uint32_t : 5;
2314  __IOM uint32_t PRIGROUP : 3;
2315  __IM uint32_t : 4;
2316  __IM uint32_t ENDIANNESS : 1;
2317  __IOM uint32_t VECTKEY : 16;
2318  } bit;
2319  } AIRCR;
2320 
2321  union
2322  {
2323  __IOM uint32_t reg;
2325  struct
2326  {
2327  __IM uint32_t : 1;
2328  __IOM uint32_t SLEEPONEXIT : 1;
2329  __IOM uint32_t SLEEPDEEP : 1;
2330  __IM uint32_t : 1;
2331  __IOM uint32_t SEVONPEND : 1;
2332  } bit;
2333  } SCR;
2334 
2335  union
2336  {
2337  __IOM uint32_t reg;
2339  struct
2340  {
2341  __IOM uint32_t NONBASETHRDENA : 1;
2342  __IOM uint32_t USERSETMPEND : 1;
2343  __IM uint32_t : 1;
2344  __IOM uint32_t UNALIGN_TRP : 1;
2345  __IOM uint32_t DIV_0_TRP : 1;
2347  __IM uint32_t : 3;
2348  __IOM uint32_t BFHFMIGN : 1;
2350  __IOM uint32_t STKALIGN : 1;
2351  } bit;
2352  } CCR;
2353 
2354  union
2355  {
2356  __IOM uint32_t reg;
2358  struct
2359  {
2360  __IOM uint32_t PRI_4 : 8;
2361  __IOM uint32_t PRI_5 : 8;
2362  __IOM uint32_t PRI_6 : 8;
2363  __IOM uint32_t PRI_7 : 8;
2364  } bit;
2365  } SHPR1;
2366 
2367  union
2368  {
2369  __IOM uint32_t reg;
2371  struct
2372  {
2373  __IOM uint32_t PRI_8 : 8;
2374  __IOM uint32_t PRI_9 : 8;
2375  __IOM uint32_t PRI_10 : 8;
2376  __IOM uint32_t PRI_11 : 8;
2377  } bit;
2378  } SHPR2;
2379 
2380  union
2381  {
2382  __IOM uint32_t reg;
2384  struct
2385  {
2386  __IOM uint32_t PRI_12 : 8;
2387  __IOM uint32_t PRI_13 : 8;
2388  __IOM uint32_t PRI_14 : 8;
2389  __IOM uint32_t PRI_15 : 8;
2390  } bit;
2391  } SHPR3;
2392 
2393  union
2394  {
2395  __IOM uint32_t reg;
2397  struct
2398  {
2399  __IOM uint32_t MEMFAULTACT : 1;
2400  __IOM uint32_t BUSFAULTACT : 1;
2401  __IM uint32_t : 1;
2402  __IOM uint32_t USGFAULTACT : 1;
2403  __IM uint32_t : 3;
2404  __IOM uint32_t SVCALLACT : 1;
2405  __IOM uint32_t MONITORACT : 1;
2406  __IM uint32_t : 1;
2407  __IOM uint32_t PENDSVACT : 1;
2408  __IOM uint32_t SYSTICKACT : 1;
2409  __IOM uint32_t USGFAULTPENDED : 1;
2410  __IOM uint32_t MEMFAULTPENDED : 1;
2411  __IOM uint32_t BUSFAULTPENDED : 1;
2412  __IOM uint32_t SVCALLPENDED : 1;
2413  __IOM uint32_t MEMFAULTENA : 1;
2414  __IOM uint32_t BUSFAULTENA : 1;
2415  __IOM uint32_t USGFAULTENA : 1;
2416  } bit;
2417  } SHCSR;
2418 
2419  union
2420  {
2421  __IOM uint32_t reg;
2423  struct
2424  {
2425  __IOM uint32_t IACCVIOL : 1;
2426  __IOM uint32_t DACCVIOL : 1;
2427  __IM uint32_t : 1;
2428  __IOM uint32_t MUNSTKERR : 1;
2429  __IOM uint32_t MSTERR : 1;
2430  __IM uint32_t : 2;
2431  __IOM uint32_t MMARVALID : 1;
2432  __IOM uint32_t IBUSERR : 1;
2433  __IOM uint32_t PRECISERR : 1;
2434  __IOM uint32_t IMPRECISERR : 1;
2435  __IOM uint32_t UNSTKERR : 1;
2436  __IOM uint32_t STKERR : 1;
2437  __IM uint32_t : 2;
2438  __IOM uint32_t BFARVALID : 1;
2439  __IOM uint32_t UNDEFINSTR : 1;
2440  __IOM uint32_t INVSTATE : 1;
2441  __IOM uint32_t INVPC : 1;
2442  __IOM uint32_t NOCP : 1;
2443  __IM uint32_t : 4;
2444  __IOM uint32_t UNALIGNED : 1;
2445  __IOM uint32_t DIVBYZERO : 1;
2446  } bit;
2447  } CFSR;
2448 
2449  union
2450  {
2451  __IOM uint32_t reg;
2453  struct
2454  {
2455  __IM uint32_t : 1;
2456  __IOM uint32_t VECTTBL : 1;
2457  __IM uint32_t : 28;
2458  __IOM uint32_t FORCED : 1;
2459  __IOM uint32_t DEBUGEVT : 1;
2460  } bit;
2461  } HFSR;
2462 
2463  union
2464  {
2465  __IOM uint32_t reg;
2467  struct
2468  {
2469  __IOM uint32_t HALTED : 1;
2470  __IOM uint32_t BKPT : 1;
2471  __IOM uint32_t DWTTRAP : 1;
2472  __IOM uint32_t VCATCH : 1;
2473  __IOM uint32_t EXTERNAL : 1;
2474  } bit;
2475  } DFSR;
2476 
2477  union
2478  {
2479  __IOM uint32_t reg;
2481  struct
2482  {
2483  __IOM uint32_t ADDRESS : 32;
2484  } bit;
2485  } MMFAR;
2486 
2487  union
2488  {
2489  __IOM uint32_t reg;
2491  struct
2492  {
2493  __IOM uint32_t ADDRESS : 32;
2494  } bit;
2495  } BFAR;
2496 
2497  union
2498  {
2499  __IOM uint32_t reg;
2501  struct
2502  {
2503  __IOM uint32_t CP0 : 2;
2504  __IOM uint32_t CP1 : 2;
2505  __IOM uint32_t CP2 : 2;
2506  __IOM uint32_t CP3 : 2;
2507  __IOM uint32_t CP4 : 2;
2508  __IOM uint32_t CP5 : 2;
2509  __IOM uint32_t CP6 : 2;
2510  __IOM uint32_t CP7 : 2;
2511  __IM uint32_t : 4;
2512  __IOM uint32_t CP10 : 2;
2513  __IOM uint32_t CP11 : 2;
2514  } bit;
2515  } AFSR;
2516 } CPU_Type;
2520 /* ================================================================================ */
2521 /* ================ CSA ================ */
2522 /* ================================================================================ */
2523 
2524 
2529 typedef struct
2530 {
2531  __I uint32_t RESERVED0[3];
2532 
2533  union
2534  {
2535  __IO uint32_t reg;
2537  struct
2538  {
2539  __IO uint32_t EN : 1;
2540  __IO uint32_t GAIN : 2;
2541  uint32_t : 5;
2542  __IO uint32_t VZERO : 1;
2543  } bit;
2544  } CTRL;
2545 } CSA_Type;
2546 
2547 
2548 /* =========================================================================================================================== */
2549 /* ================ DMA ================ */
2550 /* =========================================================================================================================== */
2551 
2552 
2557 typedef struct
2558 {
2559 
2560  union
2561  {
2562  __IOM uint32_t reg;
2564  struct
2565  {
2566  __IM uint32_t MASTER_ENABLE : 1;
2568  __IM uint32_t STATE : 4;
2569  __IM uint32_t : 8;
2570  __IM uint32_t CHNLS_MINUS1 : 5;
2571  } bit;
2572  } STATUS;
2573 
2574  union
2575  {
2576  __IOM uint32_t reg;
2578  struct
2579  {
2580  __OM uint32_t MASTER_ENABLE : 1;
2581  __IM uint32_t : 4;
2582  __OM uint32_t CHN1_PROT_CTRL : 3;
2583  } bit;
2584  } CFG;
2585 
2586  union
2587  {
2588  __IOM uint32_t reg;
2590  struct
2591  {
2592  __IM uint32_t : 9;
2593  __IOM uint32_t CTRL_BASE_PTR : 23;
2594  } bit;
2595  } CTRL_BASE_PTR;
2596 
2597  union
2598  {
2599  __IOM uint32_t reg;
2601  struct
2602  {
2603  __IM uint32_t ALT_CTRL_BASE_PTR : 32;
2604  } bit;
2605  } ALT_CTRL_BASE_PTR;
2606 
2607  union
2608  {
2609  __IOM uint32_t reg;
2611  struct
2612  {
2613  __IM uint32_t WAITONREQ_STATUS : 14;
2614  } bit;
2615  } WAITONREQ_STATUS;
2616 
2617  union
2618  {
2619  __IOM uint32_t reg;
2621  struct
2622  {
2623  __OM uint32_t CHNL_SW_REQUEST : 14;
2624  } bit;
2625  } CHNL_SW_REQUEST;
2626 
2627  union
2628  {
2629  __IOM uint32_t reg;
2631  struct
2632  {
2633  __IOM uint32_t CHNL_USEBURST_SET : 14;
2642  } bit;
2643  } CHNL_USEBURST_SET;
2644 
2645  union
2646  {
2647  __IOM uint32_t reg;
2649  struct
2650  {
2651  __OM uint32_t CHNL_USEBURST_CLR : 14;
2652  } bit;
2653  } CHNL_USEBURST_CLR;
2654 
2655  union
2656  {
2657  __IOM uint32_t reg;
2659  struct
2660  {
2661  __IOM uint32_t CHNL_REQ_MASK_SET : 14;
2667  } bit;
2668  } CHNL_REQ_MASK_SET;
2669 
2670  union
2671  {
2672  __IOM uint32_t reg;
2674  struct
2675  {
2676  __OM uint32_t CHNL_REQ_MASK_CLR : 14;
2677  } bit;
2678  } CHNL_REQ_MASK_CLR;
2679 
2680  union
2681  {
2682  __IOM uint32_t reg;
2684  struct
2685  {
2686  __IOM uint32_t CHNL_ENABLE_SET : 14;
2690  } bit;
2691  } CHNL_ENABLE_SET;
2692 
2693  union
2694  {
2695  __IOM uint32_t reg;
2697  struct
2698  {
2699  __OM uint32_t CHNL_ENABLE_CLR : 14;
2700  } bit;
2701  } CHNL_ENABLE_CLR;
2702 
2703  union
2704  {
2705  __IOM uint32_t reg;
2707  struct
2708  {
2709  __IOM uint32_t CHNL_PRI_ALT_SET : 14;
2715  } bit;
2716  } CHNL_PRI_ALT_SET;
2717 
2718  union
2719  {
2720  __IOM uint32_t reg;
2722  struct
2723  {
2724  __OM uint32_t CHNL_PRI_ALT_CLR : 14;
2725  } bit;
2726  } CHNL_PRI_ALT_CLR;
2727 
2728  union
2729  {
2730  __IOM uint32_t reg;
2732  struct
2733  {
2734  __IOM uint32_t CHNL_PRIORITY_SET : 14;
2740  } bit;
2741  } CHNL_PRIORITY_SET;
2742 
2743  union
2744  {
2745  __IOM uint32_t reg;
2747  struct
2748  {
2749  __OM uint32_t CHNL_PRIORITY_CLR : 14;
2750  } bit;
2751  } CHNL_PRIORITY_CLR;
2752  __IM uint32_t RESERVED[3];
2753 
2754  union
2755  {
2756  __IOM uint32_t reg;
2758  struct
2759  {
2760  __IOM uint32_t ERR_CLR : 1;
2763  } bit;
2764  } ERR_CLR;
2765 } DMA_Type;
2769 /* =========================================================================================================================== */
2770 /* ================ GPT12E ================ */
2771 /* =========================================================================================================================== */
2772 
2773 
2778 typedef struct
2779 {
2780 
2781  union
2782  {
2783  __IOM uint16_t reg;
2785  struct
2786  {
2787  __IM uint16_t MOD_REV : 8;
2788  __IM uint16_t MOD_TYPE : 8;
2789  } bit;
2790  } ID;
2791  __IM uint16_t RESERVED;
2792 
2793  union
2794  {
2795  __IOM uint16_t reg;
2797  struct
2798  {
2799  __IOM uint16_t IST2IN : 1;
2800  __IOM uint16_t IST2EUD : 1;
2801  __IOM uint16_t IST3IN : 2;
2802  __IOM uint16_t IST3EUD : 2;
2803  __IOM uint16_t IST4IN : 2;
2804  __IOM uint16_t IST4EUD : 2;
2805  __IOM uint16_t IST5IN : 1;
2806  __IOM uint16_t IST5EUD : 1;
2807  __IOM uint16_t IST6IN : 1;
2808  __IOM uint16_t IST6EUD : 1;
2809  __IOM uint16_t ISCAPIN : 2;
2810  } bit;
2811  } PISEL;
2812  __IM uint16_t RESERVED1;
2813 
2814  union
2815  {
2816  __IOM uint16_t reg;
2818  struct
2819  {
2820  __IOM uint16_t T2I : 3;
2821  __IOM uint16_t T2M : 3;
2822  __IOM uint16_t T2R : 1;
2823  __IOM uint16_t T2UD : 1;
2824  __IOM uint16_t T2UDE : 1;
2825  __IOM uint16_t T2RC : 1;
2827  __IOM uint16_t T2IRDIS : 1;
2828  __IOM uint16_t T2EDGE : 1;
2829  __IOM uint16_t T2CHDIR : 1;
2830  __IM uint16_t T2RDIR : 1;
2831  } bit;
2832  } T2CON;
2833  __IM uint16_t RESERVED2;
2834 
2835  union
2836  {
2837  __IOM uint16_t reg;
2839  struct
2840  {
2841  __IOM uint16_t T3I : 3;
2842  __IOM uint16_t T3M : 3;
2843  __IOM uint16_t T3R : 1;
2844  __IOM uint16_t T3UD : 1;
2845  __IOM uint16_t T3UDE : 1;
2846  __IOM uint16_t T3OE : 1;
2847  __IOM uint16_t T3OTL : 1;
2848  __IOM uint16_t BPS1 : 2;
2849  __IOM uint16_t T3EDGE : 1;
2850  __IOM uint16_t T3CHDIR : 1;
2851  __IM uint16_t T3RDIR : 1;
2852  } bit;
2853  } T3CON;
2854  __IM uint16_t RESERVED3;
2855 
2856  union
2857  {
2858  __IOM uint16_t reg;
2860  struct
2861  {
2862  __IOM uint16_t T4I : 3;
2863  __IOM uint16_t T4M : 3;
2864  __IOM uint16_t T4R : 1;
2865  __IOM uint16_t T4UD : 1;
2866  __IOM uint16_t T4UDE : 1;
2867  __IOM uint16_t T4RC : 1;
2868  __IOM uint16_t CLRT2EN : 1;
2869  __IOM uint16_t CLRT3EN : 1;
2870  __IOM uint16_t T4IRDIS : 1;
2871  __IOM uint16_t T4EDGE : 1;
2872  __IOM uint16_t T4CHDIR : 1;
2873  __IM uint16_t T4RDIR : 1;
2874  } bit;
2875  } T4CON;
2876  __IM uint16_t RESERVED4;
2877 
2878  union
2879  {
2880  __IOM uint16_t reg;
2882  struct
2883  {
2884  __IOM uint16_t T5I : 3;
2885  __IOM uint16_t T5M : 2;
2886  __IM uint16_t : 1;
2887  __IOM uint16_t T5R : 1;
2888  __IOM uint16_t T5UD : 1;
2889  __IOM uint16_t T5UDE : 1;
2890  __IOM uint16_t T5RC : 1;
2891  __IOM uint16_t CT3 : 1;
2892  __IM uint16_t : 1;
2893  __IOM uint16_t CI : 2;
2894  __IOM uint16_t T5CLR : 1;
2895  __IOM uint16_t T5SC : 1;
2896  } bit;
2897  } T5CON;
2898  __IM uint16_t RESERVED5;
2899 
2900  union
2901  {
2902  __IOM uint16_t reg;
2904  struct
2905  {
2906  __IOM uint16_t T6I : 3;
2907  __IOM uint16_t T6M : 3;
2908  __IOM uint16_t T6R : 1;
2909  __IOM uint16_t T6UD : 1;
2910  __IOM uint16_t T6UDE : 1;
2911  __IOM uint16_t T6OE : 1;
2912  __IOM uint16_t T6OTL : 1;
2913  __IOM uint16_t BPS2 : 2;
2914  __IM uint16_t : 1;
2915  __IOM uint16_t T6CLR : 1;
2916  __IOM uint16_t T6SR : 1;
2917  } bit;
2918  } T6CON;
2919  __IM uint16_t RESERVED6;
2920 
2921  union
2922  {
2923  __IOM uint16_t reg;
2925  struct
2926  {
2927  __IOM uint16_t CAPREL : 16;
2928  } bit;
2929  } CAPREL;
2930  __IM uint16_t RESERVED7;
2931 
2932  union
2933  {
2934  __IOM uint16_t reg;
2936  struct
2937  {
2938  __IOM uint16_t T2 : 16;
2939  } bit;
2940  } T2;
2941  __IM uint16_t RESERVED8;
2942 
2943  union
2944  {
2945  __IOM uint16_t reg;
2947  struct
2948  {
2949  __IOM uint16_t T3 : 16;
2950  } bit;
2951  } T3;
2952  __IM uint16_t RESERVED9;
2953 
2954  union
2955  {
2956  __IOM uint16_t reg;
2958  struct
2959  {
2960  __IOM uint16_t T4 : 16;
2961  } bit;
2962  } T4;
2963  __IM uint16_t RESERVED10;
2964 
2965  union
2966  {
2967  __IOM uint16_t reg;
2969  struct
2970  {
2971  __IOM uint16_t T5 : 16;
2972  } bit;
2973  } T5;
2974  __IM uint16_t RESERVED11;
2975 
2976  union
2977  {
2978  __IOM uint16_t reg;
2980  struct
2981  {
2982  __IOM uint16_t T6 : 16;
2983  } bit;
2984  } T6;
2985 } GPT12E_Type;
2989 /* =========================================================================================================================== */
2990 /* ================ LIN ================ */
2991 /* =========================================================================================================================== */
2992 
2993 
2998 typedef struct
2999 {
3000 
3001  union
3002  {
3003  __IOM uint32_t reg;
3005  struct
3006  {
3008  __IOM uint32_t MODE : 2;
3009  __IM uint32_t M_SM_ERR : 1;
3010  __IM uint32_t OT_STS : 1;
3011  __IM uint32_t OC_STS : 1;
3012  __IM uint32_t TXD_TMOUT_STS : 1;
3013  __IM uint32_t : 2;
3014  __IOM uint32_t TXD : 1;
3016  __IM uint32_t RXD : 1;
3017  __IOM uint32_t SM : 2;
3018  __IM uint32_t FB_SM1 : 1;
3019  __IM uint32_t FB_SM2 : 1;
3020  __IM uint32_t FB_SM3 : 1;
3021  __IM uint32_t MODE_FB : 3;
3022  __IM uint32_t : 2;
3023  __IOM uint32_t HV_MODE : 1;
3024  __IM uint32_t : 2;
3025  __IOM uint32_t M_SM_ERR_CLR : 1;
3026  } bit;
3027  } CTRL_STS;
3028 } LIN_Type;
3032 /* =========================================================================================================================== */
3033 /* ================ MF ================ */
3034 /* =========================================================================================================================== */
3035 
3036 
3041 typedef struct
3042 {
3043 
3044  union
3045  {
3046  __IOM uint32_t reg;
3048  struct
3049  {
3050  __IOM uint32_t P2_0_ADC_SEL : 1;
3051  __IOM uint32_t P2_2_ADC_SEL : 1;
3052  __IOM uint32_t P2_3_ADC_SEL : 1;
3053  __IOM uint32_t P2_4_ADC_SEL : 1;
3054  __IOM uint32_t P2_5_ADC_SEL : 1;
3056  __IOM uint32_t ADC3_INP_SEL : 1;
3057  __IOM uint32_t ADC3_INN_SEL : 1;
3058  __IOM uint32_t ADC1_CH1_SEL : 1;
3059  } bit;
3060  } P2_ADCSEL_CTRL;
3061 
3062  union
3063  {
3064  __IOM uint32_t reg;
3066  struct
3067  {
3068  __IOM uint32_t VMON_SEN_PD_N : 1;
3069  __IM uint32_t : 3;
3070  __IOM uint32_t VMON_SEN_HRESO_5V : 1;
3072  } bit;
3073  } VMON_SEN_CTRL;
3074 
3075  union
3076  {
3077  __IOM uint32_t reg;
3079  struct
3080  {
3081  __IOM uint32_t PHUCOMP_EN : 1;
3082  __IOM uint32_t PHVCOMP_EN : 1;
3083  __IOM uint32_t PHWCOMP_EN : 1;
3084  __IOM uint32_t DEMGFILTDIS : 1;
3085  __IOM uint32_t FILTBYPS : 1;
3086  __IOM uint32_t GPT12CAPINSW : 1;
3087  __IM uint32_t : 2;
3088  __IOM uint32_t PHUCOMP_ON : 1;
3089  __IOM uint32_t PHVCOMP_ON : 1;
3090  __IOM uint32_t PHWCOMP_ON : 1;
3091  __IM uint32_t : 1;
3092  __IOM uint32_t CCPOS_INSEL : 1;
3093  __IM uint32_t : 3;
3094  __IM uint32_t PHU_ZC_STS : 1;
3095  __IM uint32_t PHV_ZC_STS : 1;
3096  __IM uint32_t PHW_ZC_STS : 1;
3097  } bit;
3098  } BEMFC_CTRL_STS;
3099  __IM uint32_t RESERVED0;
3100 
3101  union
3102  {
3103  __IOM uint32_t reg;
3105  struct
3106  {
3107  __IM uint32_t : 4;
3108  __IM uint32_t PMU_OTWARN_STS : 1;
3109  __IM uint32_t PMU_OT_STS : 1;
3110  __IM uint32_t SYS_OTWARN_STS : 1;
3111  __IM uint32_t SYS_OT_STS : 1;
3112  } bit;
3113  } TEMPSENSE_CTRL;
3114 
3115  union
3116  {
3117  __IOM uint32_t reg;
3119  struct
3120  {
3121  __IM uint32_t : 4;
3122  __IM uint32_t REFBG_LOTHWARN_STS : 1;
3124  __IM uint32_t REFBG_UPTHWARN_STS : 1;
3126  } bit;
3127  } REF1_STS;
3128 
3129  union
3130  {
3131  __IOM uint32_t reg;
3133  struct
3134  {
3135  __IOM uint32_t VREF5V_PD_N : 1;
3136  __IM uint32_t VREF5V_OVL_STS : 1;
3137  __IM uint32_t VREF5V_UV_STS : 1;
3138  __IM uint32_t VREF5V_OV_STS : 1;
3139  } bit;
3140  } REF2_CTRL;
3141  __IM uint32_t RESERVED1;
3142 
3143  union
3144  {
3145  __IOM uint32_t reg;
3147  struct
3148  {
3149  __IOM uint32_t BEMF_BT_TFILT_SEL : 3;
3150  __IM uint32_t : 1;
3151  __IOM uint32_t BEMF_GPT_CAPIN_SEL : 2;
3152  __IM uint32_t : 2;
3153  __IOM uint32_t BEMF_TFILT_SEL : 2;
3154  } bit;
3155  } TRIM_BEMFx;
3156 } MF_Type;
3159 /* =========================================================================================================================== */
3160 /* ================ MON ================ */
3161 /* =========================================================================================================================== */
3162 
3163 
3168 typedef struct
3169 {
3170  __I uint32_t RESERVED0[13];
3171 
3172  union
3173  {
3174  __IO uint8_t reg;
3176  struct
3177  {
3178  __IO uint8_t EN : 1;
3179  __IO uint8_t FALL : 1;
3180  __IO uint8_t RISE : 1;
3181  __IO uint8_t CYC : 1;
3182  __IO uint8_t PD : 1;
3183  __IO uint8_t PU : 1;
3184  uint8_t : 1;
3185  __I uint8_t STS : 1;
3186  } bit;
3187  } CNF;
3188 } MON_Type;
3189 
3190 
3191 /* =========================================================================================================================== */
3192 /* ================ PMU ================ */
3193 /* =========================================================================================================================== */
3194 
3195 
3200 typedef struct
3201 {
3202 
3203  union
3204  {
3205  __IOM uint8_t reg;
3207  struct
3208  {
3209  __IM uint8_t LIN_WAKE : 1;
3210  __IM uint8_t MON_WAKE : 1;
3211  __IM uint8_t GPIO0 : 1;
3213  __IM uint8_t GPIO1 : 1;
3215  __IM uint8_t CYC_WAKE : 1;
3216  __IM uint8_t FAIL : 1;
3217  } bit;
3218  } WAKE_STATUS;
3219  __IM uint8_t RESERVED[3];
3220 
3221  union
3222  {
3223  __IOM uint8_t reg;
3225  struct
3226  {
3227  __IM uint8_t PMU_1V5_OVERVOLT : 1;
3228  __IM uint8_t PMU_1V5_OVERLOAD : 1;
3229  __IOM uint8_t PMU_1V5_FAIL_EN : 1;
3231  __IM uint8_t PMU_5V_OVERVOLT : 1;
3232  __IM uint8_t PMU_5V_OVERLOAD : 1;
3233  __IOM uint8_t PMU_5V_FAIL_EN : 1;
3234  } bit;
3235  } PMU_SUPPLY_STS;
3236  __IM uint8_t RESERVED1[3];
3237 
3238  union
3239  {
3240  __IOM uint8_t reg;
3242  struct
3243  {
3244  __IOM uint8_t ENABLE : 1;
3245  __IOM uint8_t CYC_EN : 1;
3246  __IOM uint8_t FAIL_EN : 1;
3248  __IOM uint8_t SHORT : 1;
3249  __IOM uint8_t OVERVOLT : 1;
3250  __IOM uint8_t OVERLOAD : 1;
3251  __IM uint8_t OK : 1;
3252  __IM uint8_t STABLE : 1;
3253  } bit;
3254  } VDDEXT_CTRL;
3255  __IM uint8_t RESERVED2[7];
3256 
3257  union
3258  {
3259  __IOM uint8_t reg;
3261  struct
3262  {
3263  __IOM uint8_t SYS_FAIL : 1;
3265  __IOM uint8_t PMU_WAKE : 1;
3266  __IOM uint8_t PMU_SleepEX : 1;
3267  __IOM uint8_t PMU_LPR : 1;
3268  __IOM uint8_t PMU_ClkWDT : 1;
3269  __IOM uint8_t PMU_ExtWDT : 1;
3270  __IOM uint8_t PMU_PIN : 1;
3271  __IOM uint8_t PMU_1V5DidPOR : 1;
3272  } bit;
3273  } PMU_RESET_STS1;
3274  __IM uint8_t RESERVED3[3];
3275 
3276  union
3277  {
3278  __IOM uint8_t reg;
3280  struct
3281  {
3282  __IOM uint8_t PMU_IntWDT : 1;
3283  __IOM uint8_t PMU_SOFT : 1;
3284  __IOM uint8_t LOCKUP : 1;
3285  } bit;
3286  } PMU_RESET_STS2;
3287  __IM uint8_t RESERVED4[11];
3288 
3289  union
3290  {
3291  __IOM uint8_t reg;
3293  struct
3294  {
3295  __IOM uint8_t WAKE_W_RST : 1;
3296  __IOM uint8_t EN_0V9_N : 1;
3298  __IOM uint8_t CYC_WAKE_EN : 1;
3299  __IOM uint8_t CYC_SENSE_EN : 1;
3300  __IM uint8_t : 3;
3302  } bit;
3303  } CNF_PMU_SETTINGS;
3304  __IM uint8_t RESERVED5[7];
3305 
3306  union
3307  {
3308  __IOM uint8_t reg;
3310  struct
3311  {
3312  __IOM uint8_t M03 : 4;
3313  __IOM uint8_t E01 : 2;
3314  __IM uint8_t : 1;
3315  __IOM uint8_t OSC_100kHz_EN : 1;
3316  } bit;
3317  } CNF_CYC_SENSE;
3318  __IM uint8_t RESERVED6[3];
3319 
3320  union
3321  {
3322  __IOM uint8_t reg;
3324  struct
3325  {
3326  __IOM uint8_t M03 : 4;
3327  __IOM uint8_t E01 : 2;
3328  } bit;
3329  } CNF_CYC_WAKE;
3330  __IM uint8_t RESERVED7[3];
3331 
3332  union
3333  {
3334  __IOM uint8_t reg;
3336  struct
3337  {
3338  __IOM uint8_t M03 : 4;
3339  } bit;
3340  } CNF_CYC_SAMPLE_DEL;
3341  __IM uint8_t RESERVED9[31];
3342 
3343  union
3344  {
3345  __IOM uint8_t reg;
3347  struct
3348  {
3349  __IM uint8_t : 7;
3350  __IOM uint8_t LIN_EN : 1;
3351  } bit;
3352  } LIN_WAKE_EN;
3353  __IM uint8_t RESERVED10[27];
3354 
3355  union
3356  {
3357  __IOM uint8_t reg;
3359  struct
3360  {
3361  __IOM uint8_t RST_TFB : 2;
3362  } bit;
3363  } CNF_RST_TFB;
3364  __IM uint8_t RESERVED11[3];
3365 
3366  union
3367  {
3368  __IOM uint8_t reg;
3370  struct
3371  {
3372  __IOM uint8_t SUPP_SHORT : 1;
3373  __IOM uint8_t SUPP_TMOUT : 1;
3374  __IOM uint8_t PMU_1V5_OVL : 1;
3375  __IOM uint8_t PMU_5V_OVL : 1;
3376  __IM uint8_t : 1;
3377  __IOM uint8_t SYS_OT : 1;
3378  __IOM uint8_t WDT1_SEQ_FAIL : 1;
3379  } bit;
3380  } SYS_FAIL_STS;
3381  __IM uint8_t RESERVED12[15];
3382 
3383  union
3384  {
3385  __IOM uint8_t reg;
3387  struct
3388  {
3389  __IOM uint8_t SUPPFAIL : 1;
3390  __IM uint8_t : 1;
3391  __IOM uint8_t VDDEXTSHORT : 1;
3392  } bit;
3393  } WAKE_STS_FAIL;
3394  __IM uint8_t RESERVED13[3];
3395 
3396  union
3397  {
3398  __IOM uint8_t reg;
3400  struct
3401  {
3402  __IM uint8_t WAKE_STS : 1;
3403  } bit;
3404  } WAKE_STS_MON;
3405  __IM uint8_t RESERVED14[3];
3406 
3407  union
3408  {
3409  __IOM uint8_t reg;
3411  struct
3412  {
3413  __IM uint8_t GPIO0_STS_0 : 1;
3414  __IM uint8_t GPIO0_STS_1 : 1;
3415  __IM uint8_t GPIO0_STS_2 : 1;
3416  __IM uint8_t GPIO0_STS_3 : 1;
3417  __IM uint8_t GPIO0_STS_4 : 1;
3418  } bit;
3419  } WAKE_STS_GPIO0;
3420  __IM uint8_t RESERVED15[3];
3421 
3422  union
3423  {
3424  __IOM uint8_t reg;
3426  struct
3427  {
3428  __IM uint8_t GPIO1_STS_0 : 1;
3429  __IM uint8_t GPIO1_STS_1 : 1;
3430  __IM uint8_t GPIO1_STS_2 : 1;
3431  __IM uint8_t GPIO1_STS_3 : 1;
3432  __IM uint8_t GPIO1_STS_4 : 1;
3433  } bit;
3434  } WAKE_STS_GPIO1;
3435  __IM uint8_t RESERVED16[31];
3436 
3437  union
3438  {
3439  __IOM uint8_t reg;
3441  struct
3442  {
3443  __IOM uint8_t CNF_LIN_FT : 1;
3444  __IOM uint8_t CNF_MON_FT : 1;
3445  __IOM uint8_t CNF_GPIO_FT : 2;
3446  } bit;
3447  } CNF_WAKE_FILTER;
3448  __IM uint8_t RESERVED17[19];
3449 
3450  union
3451  {
3452  __IOM uint8_t reg;
3454  struct
3455  {
3456  __IOM uint8_t DATA0 : 8;
3457  } bit;
3458  } GPUDATA00;
3459  __IM uint8_t RESERVED18[3];
3460 
3461  union
3462  {
3463  __IOM uint8_t reg;
3465  struct
3466  {
3467  __IOM uint8_t DATA1 : 8;
3468  } bit;
3469  } GPUDATA01;
3470  __IM uint8_t RESERVED19[3];
3471 
3472  union
3473  {
3474  __IOM uint8_t reg;
3476  struct
3477  {
3478  __IOM uint8_t DATA2 : 8;
3479  } bit;
3480  } GPUDATA02;
3481  __IM uint8_t RESERVED20[3];
3482 
3483  union
3484  {
3485  __IOM uint8_t reg;
3487  struct
3488  {
3489  __IOM uint8_t DATA3 : 8;
3490  } bit;
3491  } GPUDATA03;
3492  __IM uint8_t RESERVED21[3];
3493 
3494  union
3495  {
3496  __IOM uint8_t reg;
3498  struct
3499  {
3500  __IOM uint8_t DATA4 : 8;
3501  } bit;
3502  } GPUDATA04;
3503  __IM uint8_t RESERVED22[3];
3504 
3505  union
3506  {
3507  __IOM uint8_t reg;
3509  struct
3510  {
3511  __IOM uint8_t DATA5 : 8;
3512  } bit;
3513  } GPUDATA05;
3514  __IM uint8_t RESERVED23[3];
3515 
3516  union
3517  {
3518  __IOM uint8_t reg;
3520  struct
3521  {
3522  __IOM uint8_t GPIO0_RI_0 : 1;
3523  __IOM uint8_t GPIO0_RI_1 : 1;
3524  __IOM uint8_t GPIO0_RI_2 : 1;
3525  __IOM uint8_t GPIO0_RI_3 : 1;
3526  __IOM uint8_t GPIO0_RI_4 : 1;
3527  } bit;
3528  } WAKE_CONF_GPIO0_RISE;
3529  __IM uint8_t RESERVED24[3];
3530 
3531  union
3532  {
3533  __IOM uint8_t reg;
3535  struct
3536  {
3537  __IOM uint8_t GPIO0_FA_0 : 1;
3538  __IOM uint8_t GPIO0_FA_1 : 1;
3539  __IOM uint8_t GPIO0_FA_2 : 1;
3540  __IOM uint8_t GPIO0_FA_3 : 1;
3541  __IOM uint8_t GPIO0_FA_4 : 1;
3542  } bit;
3543  } WAKE_CONF_GPIO0_FALL;
3544  __IM uint8_t RESERVED25[3];
3545 
3546  union
3547  {
3548  __IOM uint8_t reg;
3550  struct
3551  {
3552  __IOM uint8_t GPIO0_CYC_0 : 1;
3553  __IOM uint8_t GPIO0_CYC_1 : 1;
3554  __IOM uint8_t GPIO0_CYC_2 : 1;
3555  __IOM uint8_t GPIO0_CYC_3 : 1;
3556  __IOM uint8_t GPIO0_CYC_4 : 1;
3557  } bit;
3558  } WAKE_CONF_GPIO0_CYC;
3559  __IM uint8_t RESERVED26[3];
3560 
3561  union
3562  {
3563  __IOM uint8_t reg;
3565  struct
3566  {
3567  __IOM uint8_t GPIO1_RI_0 : 1;
3568  __IOM uint8_t GPIO1_RI_1 : 1;
3569  __IOM uint8_t GPIO1_RI_2 : 1;
3570  __IOM uint8_t GPIO1_RI_3 : 1;
3571  __IOM uint8_t GPIO1_RI_4 : 1;
3572  } bit;
3573  } WAKE_CONF_GPIO1_RISE;
3574  __IM uint8_t RESERVED27[3];
3575 
3576  union
3577  {
3578  __IOM uint8_t reg;
3580  struct
3581  {
3582  __IOM uint8_t GPIO1_FA_0 : 1;
3583  __IOM uint8_t GPIO1_FA_1 : 1;
3584  __IOM uint8_t GPIO1_FA_2 : 1;
3585  __IOM uint8_t GPIO1_FA_3 : 1;
3586  __IOM uint8_t GPIO1_FA_4 : 1;
3587  } bit;
3588  } WAKE_CONF_GPIO1_FALL;
3589  __IM uint8_t RESERVED28[3];
3590 
3591  union
3592  {
3593  __IOM uint8_t reg;
3595  struct
3596  {
3597  __IOM uint8_t GPIO1_CYC_0 : 1;
3598  __IOM uint8_t GPIO1_CYC_1 : 1;
3599  __IOM uint8_t GPIO1_CYC_2 : 1;
3600  __IOM uint8_t GPIO1_CYC_3 : 1;
3601  __IOM uint8_t GPIO1_CYC_4 : 1;
3602  } bit;
3603  } WAKE_CONF_GPIO1_CYC;
3604  __IM uint8_t RESERVED29[487];
3605 
3606  union
3607  {
3608  __IOM uint8_t reg;
3610  struct
3611  {
3612  __IOM uint8_t MBIST_EN : 1;
3614  } bit;
3615  } SystemStartConfig;
3616 } PMU_Type;
3620 /* =========================================================================================================================== */
3621 /* ================ PORT ================ */
3622 /* =========================================================================================================================== */
3623 
3624 
3629 typedef struct
3630 {
3631 
3632  union
3633  {
3634  __IOM uint8_t reg;
3636  struct
3637  {
3638  __IOM uint8_t P0 : 1;
3639  __IOM uint8_t P1 : 1;
3640  __IOM uint8_t P2 : 1;
3641  __IOM uint8_t P3 : 1;
3642  __IOM uint8_t P4 : 1;
3643  } bit;
3644  } P0_DATA;
3645  __IM uint8_t RESERVED[3];
3646 
3647  union
3648  {
3649  __IOM uint8_t reg;
3651  struct
3652  {
3653  __IOM uint8_t P0 : 1;
3654  __IOM uint8_t P1 : 1;
3655  __IOM uint8_t P2 : 1;
3656  __IOM uint8_t P3 : 1;
3657  __IOM uint8_t P4 : 1;
3658  } bit;
3659  } P0_DIR;
3660  __IM uint8_t RESERVED1[3];
3661 
3662  union
3663  {
3664  __IOM uint8_t reg;
3666  struct
3667  {
3668  __IOM uint8_t P0 : 1;
3669  __IOM uint8_t P1 : 1;
3670  __IOM uint8_t P2 : 1;
3671  __IOM uint8_t P3 : 1;
3672  __IOM uint8_t P4 : 1;
3673  } bit;
3674  } P1_DATA;
3675  __IM uint8_t RESERVED2[3];
3676 
3677  union
3678  {
3679  __IOM uint8_t reg;
3681  struct
3682  {
3683  __IOM uint8_t P0 : 1;
3684  __IOM uint8_t P1 : 1;
3685  __IOM uint8_t P2 : 1;
3686  __IOM uint8_t P3 : 1;
3687  __IOM uint8_t P4 : 1;
3688  } bit;
3689  } P1_DIR;
3690  __IM uint8_t RESERVED3[3];
3691 
3692  union
3693  {
3694  __IOM uint8_t reg;
3696  struct
3697  {
3698  __IM uint8_t P0 : 1;
3700  __IM uint8_t P2 : 1;
3701  __IM uint8_t P3 : 1;
3702  __IM uint8_t P4 : 1;
3703  __IM uint8_t P5 : 1;
3704  } bit;
3705  } P2_DATA;
3706  __IM uint8_t RESERVED4[3];
3707 
3708  union
3709  {
3710  __IOM uint8_t reg;
3712  struct
3713  {
3714  __IOM uint8_t P0 : 1;
3715  __IM uint8_t : 1;
3716  __IOM uint8_t P2 : 1;
3717  __IOM uint8_t P3 : 1;
3718  __IOM uint8_t P4 : 1;
3719  __IOM uint8_t P5 : 1;
3720  } bit;
3721  } P2_DIR;
3722  __IM uint8_t RESERVED5[3];
3723 
3724  union
3725  {
3726  __IOM uint8_t reg;
3728  struct
3729  {
3730  __IOM uint8_t P0 : 1;
3731  __IOM uint8_t P1 : 1;
3732  __IOM uint8_t P2 : 1;
3733  __IOM uint8_t P3 : 1;
3734  __IOM uint8_t P4 : 1;
3735  } bit;
3736  } P0_PUDSEL;
3737  __IM uint8_t RESERVED6[3];
3738 
3739  union
3740  {
3741  __IOM uint8_t reg;
3743  struct
3744  {
3745  __IOM uint8_t P0 : 1;
3746  __IOM uint8_t P1 : 1;
3747  __IOM uint8_t P2 : 1;
3748  __IOM uint8_t P3 : 1;
3749  __IOM uint8_t P4 : 1;
3750  } bit;
3751  } P0_PUDEN;
3752  __IM uint8_t RESERVED7[3];
3753 
3754  union
3755  {
3756  __IOM uint8_t reg;
3758  struct
3759  {
3760  __IOM uint8_t P0 : 1;
3761  __IOM uint8_t P1 : 1;
3762  __IOM uint8_t P2 : 1;
3763  __IOM uint8_t P3 : 1;
3764  __IOM uint8_t P4 : 1;
3765  } bit;
3766  } P1_PUDSEL;
3767  __IM uint8_t RESERVED8[3];
3768 
3769  union
3770  {
3771  __IOM uint8_t reg;
3773  struct
3774  {
3775  __IOM uint8_t P0 : 1;
3776  __IOM uint8_t P1 : 1;
3777  __IOM uint8_t P2 : 1;
3778  __IOM uint8_t P3 : 1;
3779  __IOM uint8_t P4 : 1;
3780  } bit;
3781  } P1_PUDEN;
3782  __IM uint8_t RESERVED9[3];
3783 
3784  union
3785  {
3786  __IOM uint8_t reg;
3788  struct
3789  {
3790  __IOM uint8_t P0 : 1;
3791  __IM uint8_t : 1;
3792  __IOM uint8_t P2 : 1;
3793  __IOM uint8_t P3 : 1;
3794  __IOM uint8_t P4 : 1;
3795  __IOM uint8_t P5 : 1;
3796  } bit;
3797  } P2_PUDSEL;
3798  __IM uint8_t RESERVED10[3];
3799 
3800  union
3801  {
3802  __IOM uint8_t reg;
3804  struct
3805  {
3806  __IOM uint8_t P0 : 1;
3807  __IM uint8_t : 1;
3808  __IOM uint8_t P2 : 1;
3809  __IOM uint8_t P3 : 1;
3810  __IOM uint8_t P4 : 1;
3811  __IOM uint8_t P5 : 1;
3812  } bit;
3813  } P2_PUDEN;
3814  __IM uint8_t RESERVED11[3];
3815 
3816  union
3817  {
3818  __IOM uint8_t reg;
3820  struct
3821  {
3822  __IOM uint8_t P0 : 1;
3823  __IOM uint8_t P1 : 1;
3824  __IOM uint8_t P2 : 1;
3825  __IOM uint8_t P3 : 1;
3826  __IOM uint8_t P4 : 1;
3827  } bit;
3828  } P0_ALTSEL0;
3829  __IM uint8_t RESERVED12[3];
3830 
3831  union
3832  {
3833  __IOM uint8_t reg;
3835  struct
3836  {
3837  __IOM uint8_t P0 : 1;
3838  __IOM uint8_t P1 : 1;
3839  __IOM uint8_t P2 : 1;
3840  __IOM uint8_t P3 : 1;
3841  __IOM uint8_t P4 : 1;
3842  } bit;
3843  } P0_ALTSEL1;
3844  __IM uint8_t RESERVED13[3];
3845 
3846  union
3847  {
3848  __IOM uint8_t reg;
3850  struct
3851  {
3852  __IOM uint8_t P0 : 1;
3853  __IOM uint8_t P1 : 1;
3854  __IOM uint8_t P2 : 1;
3855  __IOM uint8_t P3 : 1;
3856  __IOM uint8_t P4 : 1;
3857  } bit;
3858  } P1_ALTSEL0;
3859  __IM uint8_t RESERVED14[3];
3860 
3861  union
3862  {
3863  __IOM uint8_t reg;
3865  struct
3866  {
3867  __IOM uint8_t P0 : 1;
3868  __IOM uint8_t P1 : 1;
3869  __IOM uint8_t P2 : 1;
3870  __IOM uint8_t P3 : 1;
3871  __IOM uint8_t P4 : 1;
3872  } bit;
3873  } P1_ALTSEL1;
3874  __IM uint8_t RESERVED15[3];
3875 
3876  union
3877  {
3878  __IOM uint8_t reg;
3880  struct
3881  {
3882  __IOM uint8_t P0 : 1;
3883  __IOM uint8_t P1 : 1;
3884  __IOM uint8_t P2 : 1;
3885  __IOM uint8_t P3 : 1;
3886  __IOM uint8_t P4 : 1;
3887  } bit;
3888  } P0_OD;
3889  __IM uint8_t RESERVED16[3];
3890 
3891  union
3892  {
3893  __IOM uint8_t reg;
3895  struct
3896  {
3897  __IM uint8_t : 1;
3898  __IOM uint8_t P0 : 1;
3899  __IOM uint8_t P1 : 1;
3900  __IOM uint8_t P3_P2 : 1;
3901  __IOM uint8_t P4 : 1;
3902  } bit;
3903  } P1_OD;
3904 } PORT_Type;
3908 /* =========================================================================================================================== */
3909 /* ================ SCU ================ */
3910 /* =========================================================================================================================== */
3911 
3912 
3917 typedef struct
3918 {
3919 
3920  union
3921  {
3922  __IOM uint8_t reg;
3924  struct
3925  {
3926  __OM uint8_t NMIWDTC : 1;
3927  __OM uint8_t NMIPLLC : 1;
3928  __OM uint8_t NMINVMC : 1;
3929  __OM uint8_t NMIOTC : 1;
3930  __OM uint8_t NMIOWDC : 1;
3931  __OM uint8_t NMIMAPC : 1;
3932  __OM uint8_t NMIECCC : 1;
3933  __OM uint8_t NMISUPC : 1;
3934  } bit;
3935  } NMICLR;
3936  __IM uint8_t RESERVED[3];
3937 
3938  union
3939  {
3940  __IOM uint8_t reg;
3942  struct
3943  {
3944  __IM uint8_t EXINT0R : 1;
3945  __IM uint8_t EXINT0F : 1;
3946  __IM uint8_t EXINT1R : 1;
3947  __IM uint8_t EXINT1F : 1;
3948  __IM uint8_t EXINT2R : 1;
3949  __IM uint8_t EXINT2F : 1;
3950  __IM uint8_t MONR : 1;
3951  __IM uint8_t MONF : 1;
3953  } bit;
3954  } IRCON0;
3955  __IM uint8_t RESERVED1[3];
3956 
3957  union
3958  {
3959  __IOM uint8_t reg;
3961  struct
3962  {
3963  __IM uint8_t EIR : 1;
3964  __IM uint8_t TIR : 1;
3965  __IM uint8_t RIR : 1;
3966  } bit;
3967  } IRCON1;
3968  __IM uint8_t RESERVED2[3];
3969 
3970  union
3971  {
3972  __IOM uint8_t reg;
3974  struct
3975  {
3976  __IM uint8_t EIR : 1;
3977  __IM uint8_t TIR : 1;
3978  __IM uint8_t RIR : 1;
3979  } bit;
3980  } IRCON2;
3981  __IM uint8_t RESERVED3[3];
3982 
3983  union
3984  {
3985  __IOM uint8_t reg;
3987  struct
3988  {
3989  __IM uint8_t CCU6SR0 : 1;
3991  __IM uint8_t CCU6SR1 : 1;
3992  } bit;
3993  } IRCON3;
3994  __IM uint8_t RESERVED4[3];
3995 
3996  union
3997  {
3998  __IOM uint8_t reg;
4000  struct
4001  {
4002  __IM uint8_t CCU6SR2 : 1;
4003  __IM uint8_t : 3;
4004  __IM uint8_t CCU6SR3 : 1;
4005  } bit;
4006  } IRCON4;
4007  __IM uint8_t RESERVED5[3];
4008 
4009  union
4010  {
4011  __IOM uint8_t reg;
4013  struct
4014  {
4015  __IM uint8_t FNMIWDT : 1;
4016  __IM uint8_t FNMIPLL : 1;
4017  __IM uint8_t FNMINVM : 1;
4018  __IM uint8_t FNMIOT : 1;
4019  __IM uint8_t FNMIOWD : 1;
4020  __IM uint8_t FNMIMAP : 1;
4021  __IM uint8_t FNMIECC : 1;
4022  __IM uint8_t FNMISUP : 1;
4023  } bit;
4024  } NMISR;
4025  __IM uint8_t RESERVED6[3];
4026 
4027  union
4028  {
4029  __IOM uint8_t reg;
4031  struct
4032  {
4033  __IM uint8_t : 7;
4034  __IOM uint8_t EA : 1;
4035  } bit;
4036  } IEN0;
4037  __IM uint8_t RESERVED7[7];
4038 
4039  union
4040  {
4041  __IOM uint8_t reg;
4043  struct
4044  {
4045  __IOM uint8_t NMIWDT : 1;
4046  __IOM uint8_t NMIPLL : 1;
4047  __IOM uint8_t NMINVM : 1;
4048  __IOM uint8_t NMIOT : 1;
4049  __IOM uint8_t NMIOWD : 1;
4050  __IOM uint8_t NMIMAP : 1;
4051  __IOM uint8_t NMIECC : 1;
4052  __IOM uint8_t NMISUP : 1;
4053  } bit;
4054  } NMICON;
4055  __IM uint8_t RESERVED8[3];
4056 
4057  union
4058  {
4059  __IOM uint8_t reg;
4061  struct
4062  {
4063  __IOM uint8_t EXINT0 : 2;
4064  __IOM uint8_t EXINT1 : 2;
4065  __IOM uint8_t EXINT2 : 2;
4066  __IOM uint8_t MON_Trig_Sel : 2;
4067  } bit;
4068  } EXICON0;
4069  __IM uint8_t RESERVED9[3];
4070 
4071  union
4072  {
4073  __IOM uint8_t reg;
4075  struct
4076  {
4077  __OM uint8_t EXINT0RC : 1;
4079  __OM uint8_t EXINT0FC : 1;
4081  __OM uint8_t EXINT1RC : 1;
4083  __OM uint8_t EXINT1FC : 1;
4085  __OM uint8_t EXINT2RC : 1;
4087  __OM uint8_t EXINT2FC : 1;
4089  __OM uint8_t MONRC : 1;
4091  __OM uint8_t MONFC : 1;
4093  } bit;
4094  } IRCON0CLR;
4095  __IM uint8_t RESERVED10[3];
4096 
4097  union
4098  {
4099  __IOM uint8_t reg;
4101  struct
4102  {
4103  __IOM uint8_t EIREN1 : 1;
4104  __IOM uint8_t TIREN1 : 1;
4105  __IOM uint8_t RIREN1 : 1;
4106  __IM uint8_t : 3;
4107  __IOM uint8_t RIEN1 : 1;
4108  __IOM uint8_t TIEN1 : 1;
4109  } bit;
4110  } MODIEN1;
4111  __IM uint8_t RESERVED11[3];
4112 
4113  union
4114  {
4115  __IOM uint8_t reg;
4117  struct
4118  {
4119  __IOM uint8_t EIREN2 : 1;
4120  __IOM uint8_t TIREN2 : 1;
4121  __IOM uint8_t RIREN2 : 1;
4122  __IM uint8_t : 2;
4123  __IOM uint8_t EXINT2_EN : 1;
4124  __IOM uint8_t RIEN2 : 1;
4125  __IOM uint8_t TIEN2 : 1;
4126  } bit;
4127  } MODIEN2;
4128  __IM uint8_t RESERVED12[3];
4129 
4130  union
4131  {
4132  __IOM uint8_t reg;
4134  struct
4135  {
4136  __IOM uint8_t IE0 : 1;
4137  __IM uint8_t : 3;
4138  __IOM uint8_t MONIE : 1;
4139  __IM uint8_t MONSTS : 1;
4140  } bit;
4141  } MODIEN3;
4142  __IM uint8_t RESERVED13[3];
4143 
4144  union
4145  {
4146  __IOM uint8_t reg;
4148  struct
4149  {
4150  __IOM uint8_t IE1 : 1;
4151  } bit;
4152  } MODIEN4;
4153  __IM uint8_t RESERVED14[3];
4154 
4155  union
4156  {
4157  __IOM uint8_t reg;
4159  struct
4160  {
4161  __IOM uint8_t XTAL_ON : 1;
4162  __IOM uint8_t SL : 1;
4163  __IOM uint8_t PD : 1;
4164  __IOM uint8_t SD : 1;
4165  } bit;
4166  } PMCON0;
4167  __IM uint8_t RESERVED15[3];
4168 
4169  union
4170  {
4171  __IOM uint8_t reg;
4173  struct
4174  {
4175  __IM uint8_t LOCK : 1;
4176  __IOM uint8_t RESLD : 1;
4177  __IOM uint8_t OSCDISC : 1;
4178  __IOM uint8_t VCOBYP : 1;
4179  __IOM uint8_t NDIV : 4;
4180  } bit;
4181  } PLL_CON;
4182  __IM uint8_t RESERVED16[3];
4183 
4184  union
4185  {
4186  __IOM uint8_t reg;
4188  struct
4189  {
4190  __IOM uint8_t CLKREL : 4;
4191  __IOM uint8_t K2DIV : 2;
4192  __IOM uint8_t K1DIV : 1;
4193  __IOM uint8_t VCOSEL : 1;
4194  } bit;
4195  } CMCON1;
4196  __IM uint8_t RESERVED17[3];
4197 
4198  union
4199  {
4200  __IOM uint8_t reg;
4202  struct
4203  {
4204  __IOM uint8_t PBA0CLKREL : 1;
4205  } bit;
4206  } CMCON2;
4207  __IM uint8_t RESERVED18[3];
4208 
4209  union
4210  {
4211  __IOM uint8_t reg;
4213  struct
4214  {
4215  __IOM uint8_t WDTIN : 1;
4216  __IOM uint8_t WDTRS : 1;
4217  __IOM uint8_t WDTEN : 1;
4218  __IM uint8_t : 1;
4219  __IM uint8_t WDTPR : 1;
4220  __IOM uint8_t WINBEN : 1;
4221  } bit;
4222  } WDTCON;
4223  __IM uint8_t RESERVED19[3];
4224 
4225  union
4226  {
4227  __IOM uint8_t reg;
4229  struct
4230  {
4231  __IM uint8_t PLL_LOCK : 1;
4232  __IOM uint8_t APCLK_SET : 1;
4233  __IOM uint8_t T3CLK_SEL : 1;
4234  __IOM uint8_t CLKWDT_IE : 1;
4235  __IOM uint8_t BGCLK_SEL : 1;
4236  __IOM uint8_t BGCLK_DIV : 1;
4237  __IOM uint8_t CPCLK_SEL : 1;
4238  __IOM uint8_t CPCLK_DIV : 1;
4239  } bit;
4240  } APCLK_CTRL1;
4241  __IM uint8_t RESERVED20[3];
4242 
4243  union
4244  {
4245  __IOM uint8_t reg;
4247  struct
4248  {
4249  __IOM uint8_t APCLK1FAC : 2;
4250  __IOM uint8_t APCLK1SCLR : 1;
4251  __IM uint8_t : 1;
4252  __IM uint8_t APCLK1STS : 2;
4253  __IM uint8_t APCLK3STS : 1;
4254  __IOM uint8_t APCLK3SCLR : 1;
4255  } bit;
4256  } APCLK1;
4257  __IM uint8_t RESERVED21[3];
4258 
4259  union
4260  {
4261  __IOM uint8_t reg;
4263  struct
4264  {
4265  __IOM uint8_t APCLK2FAC : 5;
4266  __IM uint8_t APCLK2STS : 2;
4267  __IOM uint8_t APCLK2SCLR : 1;
4268  } bit;
4269  } APCLK2;
4270  __IM uint8_t RESERVED22[3];
4271 
4272  union
4273  {
4274  __IOM uint8_t reg;
4276  struct
4277  {
4278  __IOM uint8_t ADC1_DIS : 1;
4279  __IOM uint8_t SSC1_DIS : 1;
4280  __IOM uint8_t CCU6_DIS : 1;
4281  __IOM uint8_t T2_DIS : 1;
4282  __IOM uint8_t GPT12_DIS : 1;
4283  } bit;
4284  } PMCON1;
4285  __IM uint8_t RESERVED23[3];
4286 
4287  union
4288  {
4289  __IOM uint8_t reg;
4291  struct
4292  {
4293  __IM uint8_t : 1;
4294  __IOM uint8_t SSC2_DIS : 1;
4295  __IM uint8_t : 1;
4296  __IOM uint8_t T21_DIS : 1;
4297  __IM uint8_t : 1;
4298  __IOM uint8_t T3_DIS : 1;
4299  } bit;
4300  } PMCON2;
4301  __IM uint8_t RESERVED24[3];
4302 
4303  union
4304  {
4305  __IOM uint8_t reg;
4307  struct
4308  {
4309  __IOM uint8_t LOCKUP : 1;
4310  __IM uint8_t : 6;
4311  __IOM uint8_t LOCKUP_EN : 1;
4312  } bit;
4313  } RSTCON;
4314  __IM uint8_t RESERVED25[3];
4315 
4316  union
4317  {
4318  __IOM uint8_t reg;
4320  struct
4321  {
4322  __IOM uint8_t SDADCCLK_DIV : 2;
4323  __IOM uint8_t T3CLK_DIV : 2;
4324  } bit;
4325  } APCLK_CTRL2;
4326  __IM uint8_t RESERVED26[3];
4327 
4328  union
4329  {
4330  __IOM uint8_t reg;
4332  struct
4333  {
4334  __IM uint8_t : 4;
4335  __IOM uint8_t NVMCLKFAC : 2;
4336  __IOM uint8_t SYSCLKSEL : 2;
4337  } bit;
4338  } SYSCON0;
4339  __IM uint8_t RESERVED27[3];
4340 
4341  union
4342  {
4343  __IOM uint8_t reg;
4345  struct
4346  {
4347  __IOM uint8_t INIT_FAIL : 1;
4348  __IOM uint8_t MRAMINITSTS : 1;
4349  __IOM uint8_t PG100TP_CHKS_ERR : 1;
4350  } bit;
4351  } SYS_STRTUP_STS;
4352  __IM uint8_t RESERVED28[3];
4353 
4354  union
4355  {
4356  __IOM uint8_t reg;
4358  struct
4359  {
4360  __IOM uint8_t WDTREL : 8;
4361  } bit;
4362  } WDTREL;
4363  __IM uint8_t RESERVED29[3];
4364 
4365  union
4366  {
4367  __IOM uint8_t reg;
4369  struct
4370  {
4371  __IOM uint8_t WDTWINB : 8;
4372  } bit;
4373  } WDTWINB;
4374  __IM uint8_t RESERVED30[3];
4375 
4376  union
4377  {
4378  __IOM uint8_t reg;
4380  struct
4381  {
4382  __IM uint8_t WDT : 8;
4383  } bit;
4384  } WDTL;
4385  __IM uint8_t RESERVED31[3];
4386 
4387  union
4388  {
4389  __IOM uint8_t reg;
4391  struct
4392  {
4393  __IM uint8_t WDT : 8;
4394  } bit;
4395  } WDTH;
4396  __IM uint8_t RESERVED32[3];
4397 
4398  union
4399  {
4400  __IOM uint8_t reg;
4402  struct
4403  {
4404  __IOM uint8_t R : 1;
4405  __IOM uint8_t BRPRE : 3;
4406  } bit;
4407  } BCON1;
4408  __IM uint8_t RESERVED33[3];
4409 
4410  union
4411  {
4412  __IOM uint8_t reg;
4415  struct
4416  {
4417  __IOM uint8_t FD_SEL : 5;
4418  __IOM uint8_t BR_VALUE : 3;
4419  } bit;
4420  } BGL1;
4421  __IM uint8_t RESERVED34[3];
4422 
4423  union
4424  {
4425  __IOM uint8_t reg;
4427  struct
4428  {
4429  __IOM uint8_t BR_VALUE : 8;
4430  } bit;
4431  } BGH1;
4432  __IM uint8_t RESERVED35[3];
4433 
4434  union
4435  {
4436  __IOM uint8_t reg;
4438  struct
4439  {
4440  __IOM uint8_t BRDIS : 1;
4441  __IOM uint8_t BGSEL : 2;
4442  __IM uint8_t BRK : 1;
4443  __IM uint8_t EOFSYN : 1;
4444  __IM uint8_t ERRSYN : 1;
4445  __IOM uint8_t SYNEN : 1;
4446  } bit;
4447  } LINST;
4448  __IM uint8_t RESERVED36[3];
4449 
4450  union
4451  {
4452  __IOM uint8_t reg;
4454  struct
4455  {
4456  __IOM uint8_t R : 1;
4457  __IOM uint8_t BRPRE : 3;
4458  } bit;
4459  } BCON2;
4460  __IM uint8_t RESERVED37[3];
4461 
4462  union
4463  {
4464  __IOM uint8_t reg;
4467  struct
4468  {
4469  __IOM uint8_t FD_SEL : 5;
4470  __IOM uint8_t BR_VALUE : 3;
4471  } bit;
4472  } BGL2;
4473  __IM uint8_t RESERVED38[3];
4474 
4475  union
4476  {
4477  __IOM uint8_t reg;
4479  struct
4480  {
4481  __IOM uint8_t BR_VALUE : 8;
4482  } bit;
4483  } BGH2;
4484  __IM uint8_t RESERVED39[3];
4485 
4486  union
4487  {
4488  __IOM uint8_t reg;
4490  struct
4491  {
4492  __IM uint8_t : 3;
4493  __OM uint8_t BRKC : 1;
4494  __OM uint8_t EOFSYNC : 1;
4495  __OM uint8_t ERRSYNC : 1;
4496  } bit;
4497  } LINSCLR;
4498  __IM uint8_t RESERVED40[3];
4499 
4500  union
4501  {
4502  __IOM uint8_t reg;
4504  struct
4505  {
4506  __IM uint8_t VERID : 3;
4507  __IM uint8_t PRODID : 5;
4508  } bit;
4509  } ID;
4510  __IM uint8_t RESERVED41[3];
4511 
4512  union
4513  {
4514  __IOM uint8_t reg;
4516  struct
4517  {
4518  __IOM uint8_t MODE : 2;
4519  __IM uint8_t PROTECT_S : 1;
4520  __IOM uint8_t PASS : 5;
4521  } bit;
4522  } PASSWD;
4523  __IM uint8_t RESERVED42[3];
4524 
4525  union
4526  {
4527  __IOM uint8_t reg;
4529  struct
4530  {
4531  __IOM uint8_t OSCSS : 2;
4532  __IOM uint8_t OSCWDTRST : 1;
4533  __IM uint8_t OSC2L : 1;
4534  __IOM uint8_t XPD : 1;
4535  __IM uint8_t : 2;
4536  __IOM uint8_t OSCTRIM_8 : 1;
4537  } bit;
4538  } OSC_CON;
4539  __IM uint8_t RESERVED43[3];
4540 
4541  union
4542  {
4543  __IOM uint8_t reg;
4545  struct
4546  {
4547  __IOM uint8_t COREL : 4;
4548  __IOM uint8_t COUTS0 : 1;
4549  __IOM uint8_t TLEN : 1;
4550  __IOM uint8_t COUTS1 : 1;
4551  __IOM uint8_t EN : 1;
4552  } bit;
4553  } COCON;
4554  __IM uint8_t RESERVED44[3];
4555 
4556  union
4557  {
4558  __IOM uint8_t reg;
4560  struct
4561  {
4562  __IOM uint8_t EXINT0IS : 2;
4563  __IOM uint8_t EXINT1IS : 2;
4564  __IOM uint8_t EXINT2IS : 2;
4565  __IOM uint8_t URIOS1 : 1;
4566  __IOM uint8_t U_TX_CONDIS : 1;
4567  } bit;
4568  } MODPISEL;
4569  __IM uint8_t RESERVED45[3];
4570 
4571  union
4572  {
4573  __IOM uint8_t reg;
4575  struct
4576  {
4577  __IOM uint8_t GPT12CAPINB : 1;
4578  __IM uint8_t : 5;
4579  __IOM uint8_t T2EXCON : 1;
4580  __IOM uint8_t T21EXCON : 1;
4581  } bit;
4582  } MODPISEL1;
4583  __IM uint8_t RESERVED46[3];
4584 
4585  union
4586  {
4587  __IOM uint8_t reg;
4589  struct
4590  {
4591  __IOM uint8_t T2IS : 2;
4592  __IOM uint8_t T21IS : 2;
4593  __IOM uint8_t T2EXIS : 2;
4594  __IOM uint8_t T21EXIS : 2;
4595  } bit;
4596  } MODPISEL2;
4597  __IM uint8_t RESERVED47[3];
4598 
4599  union
4600  {
4601  __IOM uint8_t reg;
4603  struct
4604  {
4605  __IM uint8_t : 6;
4606  __IOM uint8_t URIOS2 : 1;
4607  } bit;
4608  } MODPISEL3;
4609  __IM uint8_t RESERVED48[3];
4610 
4611  union
4612  {
4613  __IOM uint8_t reg;
4615  struct
4616  {
4617  __IOM uint8_t WDTSUSP : 1;
4618  __IOM uint8_t T12SUSP : 1;
4619  __IOM uint8_t T13SUSP : 1;
4620  __IOM uint8_t T2_SUSP : 1;
4621  __IOM uint8_t GPT12_SUSP : 1;
4622  __IM uint8_t : 1;
4623  __IOM uint8_t T21_SUSP : 1;
4624  } bit;
4625  } MODSUSP1;
4626  __IM uint8_t RESERVED49[3];
4627 
4628  union
4629  {
4630  __IOM uint8_t reg;
4632  struct
4633  {
4634  __IOM uint8_t T3_SUSP : 1;
4635  __IOM uint8_t MU_SUSP : 1;
4636  __IOM uint8_t ADC1_SUSP : 1;
4637  } bit;
4638  } MODSUSP2;
4639  __IM uint8_t RESERVED50[3];
4640 
4641  union
4642  {
4643  __IOM uint8_t reg;
4645  struct
4646  {
4647  __IOM uint8_t GPT12 : 4;
4648  __IOM uint8_t TRIG_CONF : 1;
4649  __IOM uint8_t T3_GPT12_SEL : 1;
4650  } bit;
4651  } GPT12PISEL;
4652  __IM uint8_t RESERVED51[3];
4653 
4654  union
4655  {
4656  __IOM uint8_t reg;
4659  struct
4660  {
4661  __IOM uint8_t RIE : 1;
4662  __IM uint8_t : 1;
4663  __IOM uint8_t NVMIE : 1;
4664  } bit;
4665  } EDCCON;
4666  __IM uint8_t RESERVED52[3];
4667 
4668  union
4669  {
4670  __IOM uint8_t reg;
4673  struct
4674  {
4675  __IM uint8_t RDBE : 1;
4676  __IM uint8_t : 1;
4677  __IM uint8_t NVMDBE : 1;
4678  __IM uint8_t : 1;
4679  __IM uint8_t RSBE : 1;
4680  } bit;
4681  } EDCSTAT;
4682  __IM uint8_t RESERVED53[3];
4683 
4684  union
4685  {
4686  __IOM uint8_t reg;
4688  struct
4689  {
4690  __IOM uint8_t SECTORINFO : 6;
4691  __IOM uint8_t SASTATUS : 2;
4692  } bit;
4693  } MEMSTAT;
4694  __IM uint8_t RESERVED54[3];
4695 
4696  union
4697  {
4698  __IOM uint8_t reg;
4700  struct
4701  {
4702  __IOM uint8_t NVMPROTSTSL_0 : 1;
4703  __IOM uint8_t NVMPROTSTSL_1 : 1;
4704  __IOM uint8_t NVMPROTSTSL_2 : 1;
4705  __IOM uint8_t NVMPROTSTSL_3 : 1;
4706  } bit;
4707  } NVM_PROT_STS;
4708  __IM uint8_t RESERVED55[3];
4709 
4710  union
4711  {
4712  __IOM uint8_t reg;
4714  struct
4715  {
4716  __IM uint8_t NVM_PROT_ERR : 1;
4717  __IM uint8_t NVM_ADDR_ERR : 1;
4718  __IM uint8_t NVM_SFR_PROT_ERR : 1;
4719  __IM uint8_t NVM_SFR_ADDR_ERR : 1;
4720  __IM uint8_t ROM_PROT_ERR : 1;
4721  __IM uint8_t ROM_ADDR_ERR : 1;
4722  __IM uint8_t RAM_PROT_ERR : 1;
4723  } bit;
4724  } MEM_ACC_STS;
4725  __IM uint8_t RESERVED56[3];
4726 
4727  union
4728  {
4729  __IOM uint8_t reg;
4731  struct
4732  {
4733  __IOM uint8_t PDM0 : 3;
4734  __IM uint8_t : 1;
4735  __IOM uint8_t PDM1 : 3;
4736  } bit;
4737  } P0_POCON0;
4738  __IM uint8_t RESERVED57[3];
4739 
4740  union
4741  {
4742  __IOM uint8_t reg;
4744  struct
4745  {
4746  __IOM uint8_t PDM2 : 3;
4747  __IM uint8_t : 1;
4748  __IOM uint8_t PDM3 : 3;
4749  } bit;
4750  } P0_POCON1;
4751  __IM uint8_t RESERVED58[3];
4752 
4753  union
4754  {
4755  __IOM uint8_t reg;
4757  struct
4758  {
4759  __IOM uint8_t PDM4 : 3;
4760  } bit;
4761  } P0_POCON2;
4762  __IM uint8_t RESERVED59[3];
4763 
4764  union
4765  {
4766  __IOM uint8_t reg;
4768  struct
4769  {
4770  __IOM uint8_t TCC : 2;
4771  } bit;
4772  } TCCR;
4773  __IM uint8_t RESERVED60[3];
4774 
4775  union
4776  {
4777  __IOM uint8_t reg;
4779  struct
4780  {
4781  __IOM uint8_t PDM0 : 3;
4782  __IM uint8_t : 1;
4783  __IOM uint8_t PDM1 : 3;
4784  } bit;
4785  } P1_POCON0;
4786  __IM uint8_t RESERVED61[3];
4787 
4788  union
4789  {
4790  __IOM uint8_t reg;
4792  struct
4793  {
4794  __IOM uint8_t PDM2 : 3;
4795  __IM uint8_t : 1;
4796  __IOM uint8_t PDM3 : 3;
4797  } bit;
4798  } P1_POCON1;
4799  __IM uint8_t RESERVED62[3];
4800 
4801  union
4802  {
4803  __IOM uint8_t reg;
4805  struct
4806  {
4807  __IOM uint8_t PDM4 : 3;
4808  } bit;
4809  } P1_POCON2;
4810  __IM uint8_t RESERVED63[11];
4811 
4812  union
4813  {
4814  __IOM uint8_t reg;
4817  struct
4818  {
4819  __OM uint8_t RDBEC : 1;
4820  __IM uint8_t : 1;
4821  __OM uint8_t NVMDBEC : 1;
4822  __IM uint8_t : 1;
4823  __OM uint8_t RSBEC : 1;
4824  } bit;
4825  } EDCSCLR;
4826  __IM uint8_t RESERVED64[55];
4827 
4828  union
4829  {
4830  __IOM uint8_t reg;
4832  struct
4833  {
4834  __IOM uint8_t CH1IE : 1;
4835  __IOM uint8_t CH2IE : 1;
4836  __IOM uint8_t CH3IE : 1;
4837  __IOM uint8_t CH4IE : 1;
4838  __IOM uint8_t CH5IE : 1;
4839  __IOM uint8_t CH6IE : 1;
4840  __IOM uint8_t CH7IE : 1;
4841  __IOM uint8_t CH8IE : 1;
4842  } bit;
4843  } DMAIEN1;
4844  __IM uint8_t RESERVED65[3];
4845 
4846  union
4847  {
4848  __IOM uint8_t reg;
4850  struct
4851  {
4852  __IOM uint8_t TRERRIE : 1;
4853  __IOM uint8_t TRSEQ1RDYIE : 1;
4854  __IOM uint8_t TRSEQ2RDYIE : 1;
4855  __IOM uint8_t SSCTXIE : 1;
4856  __IOM uint8_t SSCRXIE : 1;
4857  __IOM uint8_t GPT12IE : 1;
4858  __IOM uint8_t SDADCIE : 1;
4859  } bit;
4860  } DMAIEN2;
4861  __IM uint8_t RESERVED66[3];
4862 
4863  union
4864  {
4865  __IOM uint8_t reg;
4867  struct
4868  {
4869  __IOM uint8_t SSCTXSRCSEL : 1;
4870  __IOM uint8_t SSCRXSRCSEL : 1;
4871  __IOM uint8_t T12ZM_DMAEN : 1;
4872  __IOM uint8_t T12PM_DMAEN : 1;
4873  __IM uint8_t : 1;
4874  __IM uint8_t SSCTX : 1;
4875  __IM uint8_t SSCRX : 1;
4876  __IM uint8_t GPT12_T3 : 1;
4877  } bit;
4878  } DMASRCSEL;
4879  __IM uint8_t RESERVED67[7];
4880 
4881  union
4882  {
4883  __IOM uint8_t reg;
4885  struct
4886  {
4887  __IM uint8_t CH1 : 1;
4888  __IM uint8_t CH2 : 1;
4889  __IM uint8_t CH3 : 1;
4890  __IM uint8_t CH4 : 1;
4891  __IM uint8_t CH5 : 1;
4892  __IM uint8_t CH6 : 1;
4893  __IM uint8_t CH7 : 1;
4894  __IM uint8_t CH8 : 1;
4895  } bit;
4896  } DMAIRC1;
4897  __IM uint8_t RESERVED68[3];
4898 
4899  union
4900  {
4901  __IOM uint8_t reg;
4903  struct
4904  {
4905  __IM uint8_t STRDY : 1;
4906  __IM uint8_t TRSEQ1DY : 1;
4907  __IM uint8_t TRSEQ2DY : 1;
4908  __IM uint8_t SSC1RDY : 1;
4909  __IM uint8_t SSC2RDY : 1;
4910  __IM uint8_t GPT12 : 1;
4911  __IM uint8_t SDADC : 1;
4912  } bit;
4913  } DMAIRC2;
4914  __IM uint8_t RESERVED69[3];
4915 
4916  union
4917  {
4918  __IOM uint8_t reg;
4921  struct
4922  {
4923  __IOM uint8_t T2IE : 1;
4924  __IOM uint8_t T3IE : 1;
4925  __IOM uint8_t T4IE : 1;
4926  __IOM uint8_t T5IE : 1;
4927  __IOM uint8_t T6IE : 1;
4928  __IOM uint8_t CRIE : 1;
4930  } bit;
4931  } GPT12IEN;
4932  __IM uint8_t RESERVED70[3];
4933 
4934  union
4935  {
4936  __IOM uint8_t reg;
4938  struct
4939  {
4940  __IM uint8_t T2 : 1;
4941  __IM uint8_t T3 : 1;
4942  __IM uint8_t T4 : 1;
4943  __IM uint8_t T5 : 1;
4944  __IM uint8_t T6 : 1;
4945  __IM uint8_t CR : 1;
4946  } bit;
4947  } GPT12IRC;
4948  __IM uint8_t RESERVED71[3];
4949 
4950  union
4951  {
4952  __IOM uint8_t reg;
4955  struct
4956  {
4957  __OM uint8_t T2C : 1;
4958  __OM uint8_t T3C : 1;
4959  __OM uint8_t T4C : 1;
4960  __OM uint8_t T5C : 1;
4961  __OM uint8_t T6C : 1;
4962  __OM uint8_t CRC : 1;
4963  } bit;
4964  } GPT12ICLR;
4965  __IM uint8_t RESERVED72[19];
4966 
4967  union
4968  {
4969  __IOM uint8_t reg;
4971  struct
4972  {
4973  __OM uint8_t EIRC : 1;
4974  __OM uint8_t TIRC : 1;
4975  __OM uint8_t RIRC : 1;
4976  } bit;
4977  } IRCON1CLR;
4978  __IM uint8_t RESERVED73[3];
4979 
4980  union
4981  {
4982  __IOM uint8_t reg;
4984  struct
4985  {
4986  __OM uint8_t EIRC : 1;
4987  __OM uint8_t TIRC : 1;
4988  __OM uint8_t RIRC : 1;
4989  } bit;
4990  } IRCON2CLR;
4991  __IM uint8_t RESERVED74[3];
4992 
4993  union
4994  {
4995  __IOM uint8_t reg;
4997  struct
4998  {
4999  __IOM uint8_t GPT12_DMAEN : 2;
5000  } bit;
5001  } DMASRCSEL2;
5002  __IM uint8_t RESERVED75[3];
5003 
5004  union
5005  {
5006  __IOM uint8_t reg;
5008  struct
5009  {
5010  __OM uint8_t CH1C : 1;
5011  __OM uint8_t CH2C : 1;
5012  __OM uint8_t CH3C : 1;
5013  __OM uint8_t CH4C : 1;
5014  __OM uint8_t CH5C : 1;
5015  __OM uint8_t CH6C : 1;
5016  __OM uint8_t CH7C : 1;
5017  __OM uint8_t CH8C : 1;
5018  } bit;
5019  } DMAIRC1CLR;
5020  __IM uint8_t RESERVED76[3];
5021 
5022  union
5023  {
5024  __IOM uint8_t reg;
5026  struct
5027  {
5028  __IM uint8_t : 1;
5029  __OM uint8_t TRSEQ1DYC : 1;
5030  __OM uint8_t TRSEQ2DYC : 1;
5031  __OM uint8_t SSC1C : 1;
5032  __OM uint8_t SSC2C : 1;
5033  __OM uint8_t GPT12C : 1;
5034  __OM uint8_t SDADCC : 1;
5035  } bit;
5036  } DMAIRC2CLR;
5037  __IM uint8_t RESERVED77[7];
5038 
5039  union
5040  {
5041  __IOM uint8_t reg;
5043  struct
5044  {
5045  __OM uint8_t CCU6SR0C : 1;
5046  __IM uint8_t : 3;
5047  __OM uint8_t CCU6SR1C : 1;
5048  } bit;
5049  } IRCON3CLR;
5050  __IM uint8_t RESERVED78[3];
5051 
5052  union
5053  {
5054  __IOM uint8_t reg;
5056  struct
5057  {
5058  __OM uint8_t CCU6SR2C : 1;
5059  __IM uint8_t : 3;
5060  __OM uint8_t CCU6SR3C : 1;
5061  } bit;
5062  } IRCON4CLR;
5063  __IM uint8_t RESERVED79[3];
5064 
5065  union
5066  {
5067  __IOM uint8_t reg;
5069  struct
5070  {
5071  __IM uint8_t : 5;
5072  __OM uint8_t SSCTXC : 1;
5073  __OM uint8_t SSCRXC : 1;
5074  __OM uint8_t GPT12_T3C : 1;
5075  } bit;
5076  } DMASRCCLR;
5077 } SCU_Type;
5081 /* =========================================================================================================================== */
5082 /* ================ SCUPM ================ */
5083 /* =========================================================================================================================== */
5084 
5085 
5090 typedef struct
5091 {
5092 
5093  union
5094  {
5095  __IOM uint32_t reg;
5097  struct
5098  {
5099  __IM uint32_t AMCLK1_FREQ : 6;
5102  __IM uint32_t AMCLK2_FREQ : 6;
5103  } bit;
5104  } AMCLK_FREQ_STS;
5105 
5106  union
5107  {
5108  __IOM uint32_t reg;
5110  struct
5111  {
5112  __IOM uint32_t CLKWDT_PD_N : 1;
5113  } bit;
5114  } AMCLK_CTRL;
5115  __IM uint32_t RESERVED;
5116 
5117  union
5118  {
5119  __IOM uint32_t reg;
5121  struct
5122  {
5123  __IOM uint32_t AMCLK1_UP_TH : 6;
5124  __IOM uint32_t AMCLK1_UP_HYS : 2;
5125  __IOM uint32_t AMCLK1_LOW_TH : 6;
5126  __IOM uint32_t AMCLK1_LOW_HYS : 2;
5127  __IOM uint32_t AMCLK2_UP_TH : 6;
5128  __IOM uint32_t AMCLK2_UP_HYS : 2;
5129  __IOM uint32_t AMCLK2_LOW_TH : 6;
5130  __IOM uint32_t AMCLK2_LOW_HYS : 2;
5131  } bit;
5132  } AMCLK_TH_HYS;
5133  __IM uint32_t RESERVED1;
5134 
5135  union
5136  {
5137  __IOM uint32_t reg;
5139  struct
5140  {
5141  __OM uint32_t LIN_OC_ICLR : 1;
5142  __OM uint32_t LIN_OT_ICLR : 1;
5143  __OM uint32_t LIN_TMOUT_ICLR : 1;
5144  __IM uint32_t : 3;
5145  __OM uint32_t PMU_OTWARN_ICLR : 1;
5147  __OM uint32_t PMU_OT_ICLR : 1;
5149  __OM uint32_t SYS_OTWARN_ICLR : 1;
5151  __OM uint32_t SYS_OT_ICLR : 1;
5153  __OM uint32_t REFBG_LOTHWARN_ICLR : 1;
5155  __OM uint32_t REFBG_UPTHWARN_ICLR : 1;
5157  __OM uint32_t VREF5V_LOWTH_ICLR : 1;
5159  __OM uint32_t VREF5V_UPTH_ICLR : 1;
5161  __OM uint32_t VREF5V_OVL_ICLR : 1;
5162  __OM uint32_t ADC2_ESM_ICLR : 1;
5163  __OM uint32_t PHU_ZCLOW_ICLR : 1;
5164  __OM uint32_t PHU_ZCHI_ICLR : 1;
5165  __OM uint32_t PHV_ZCLOW_ICLR : 1;
5166  __OM uint32_t PHV_ZCHI_ICLR : 1;
5167  __OM uint32_t PHW_ZCLOW_ICLR : 1;
5168  __OM uint32_t PHW_ZCHI_ICLR : 1;
5169  __OM uint32_t ADC3_EOC_ICLR : 1;
5170  __OM uint32_t ADC4_EOC_ICLR : 1;
5171  __OM uint32_t PHU_ZCLOW_SCLR : 1;
5172  __OM uint32_t PHU_ZCHI_SCLR : 1;
5173  __OM uint32_t PHV_ZCLOW_SCLR : 1;
5174  __OM uint32_t PHV_ZCHI_SCLR : 1;
5175  __OM uint32_t PHW_ZCLOW_SCLR : 1;
5176  __OM uint32_t PHW_ZCHI_SCLR : 1;
5177  } bit;
5178  } SYS_ISCLR;
5179 
5180  union
5181  {
5182  __IOM uint32_t reg;
5184  struct
5185  {
5186  __IM uint32_t LIN_OC_IS : 1;
5187  __IM uint32_t LIN_OT_IS : 1;
5188  __IM uint32_t LIN_TMOUT_IS : 1;
5189  __IM uint32_t : 3;
5190  __IM uint32_t PMU_OTWARN_IS : 1;
5192  __IM uint32_t PMU_OT_IS : 1;
5194  __IM uint32_t SYS_OTWARN_IS : 1;
5196  __IM uint32_t SYS_OT_IS : 1;
5198  __IM uint32_t REFBG_LOTHWARN_IS : 1;
5200  __IM uint32_t REFBG_UPTHWARN_IS : 1;
5202  __IM uint32_t VREF5V_LOWTH_IS : 1;
5204  __IM uint32_t VREF5V_UPTH_IS : 1;
5206  __IM uint32_t VREF5V_OVL_IS : 1;
5207  __IM uint32_t ADC2_ESM_IS : 1;
5208  __IM uint32_t PHU_ZCLOW_IS : 1;
5209  __IM uint32_t PHU_ZCHI_IS : 1;
5210  __IM uint32_t PHV_ZCLOW_IS : 1;
5211  __IM uint32_t PHV_ZCHI_IS : 1;
5212  __IM uint32_t PHW_ZCLOW_IS : 1;
5213  __IM uint32_t PHW_ZCHI_IS : 1;
5214  __IM uint32_t ADC3_EOC_IS : 1;
5215  __IM uint32_t ADC4_EOC_IS : 1;
5216  __IM uint32_t PHU_ZCLOW_STS : 1;
5217  __IM uint32_t PHU_ZCHI_STS : 1;
5218  __IM uint32_t PHV_ZCLOW_STS : 1;
5219  __IM uint32_t PHV_ZCHI_STS : 1;
5220  __IM uint32_t PHW_ZCLOW_STS : 1;
5221  __IM uint32_t PHW_ZCHI_STS : 1;
5222  } bit;
5223  } SYS_IS;
5224 
5225  union
5226  {
5227  __IOM uint32_t reg;
5229  struct
5230  {
5231  __IM uint32_t MON_UV_IS : 1;
5232  __IM uint32_t VS_UV_IS : 1;
5233  __IM uint32_t VDD5V_UV_IS : 1;
5234  __IM uint32_t VDD1V5_UV_IS : 1;
5235  __IM uint32_t MON_OV_IS : 1;
5236  __IM uint32_t VS_OV_IS : 1;
5237  __IM uint32_t VDD5V_OV_IS : 1;
5238  __IM uint32_t VDD1V5_OV_IS : 1;
5239  __IM uint32_t : 8;
5240  __IM uint32_t MON_UV_STS : 1;
5241  __IM uint32_t VS_UV_STS : 1;
5242  __IM uint32_t VDD5V_UV_STS : 1;
5243  __IM uint32_t VDD1V5_UV_STS : 1;
5244  __IM uint32_t MON_OV_STS : 1;
5245  __IM uint32_t VS_OV_STS : 1;
5246  __IM uint32_t VDD5V_OV_STS : 1;
5247  __IM uint32_t VDD1V5_OV_STS : 1;
5248  } bit;
5249  } SYS_SUPPLY_IRQ_STS;
5250 
5251  union
5252  {
5253  __IOM uint32_t reg;
5255  struct
5256  {
5257  __IOM uint32_t MON_UV_IE : 1;
5258  __IOM uint32_t VS_UV_IE : 1;
5259  __IOM uint32_t VDD5V_UV_IE : 1;
5260  __IOM uint32_t VDD1V5_UV_IE : 1;
5261  __IOM uint32_t MON_OV_IE : 1;
5262  __IOM uint32_t VS_OV_IE : 1;
5263  __IOM uint32_t VDD5V_OV_IE : 1;
5264  __IOM uint32_t VDD1V5_OV_IE : 1;
5265  } bit;
5266  } SYS_SUPPLY_IRQ_CTRL;
5267 
5268  union
5269  {
5270  __IOM uint32_t reg;
5272  struct
5273  {
5274  __OM uint32_t MON_UV_ICLR : 1;
5275  __OM uint32_t VS_UV_ICLR : 1;
5276  __OM uint32_t VDD5V_UV_ICLR : 1;
5277  __OM uint32_t VDD1V5_UV_ICLR : 1;
5278  __OM uint32_t MON_OV_ICLR : 1;
5279  __OM uint32_t VS_OV_ICLR : 1;
5280  __OM uint32_t VDD5V_OV_ICLR : 1;
5281  __OM uint32_t VDD1V5_OV_ICLR : 1;
5282  __IM uint32_t : 8;
5283  __OM uint32_t MON_UV_SCLR : 1;
5284  __OM uint32_t VS_UV_SCLR : 1;
5285  __OM uint32_t VDD5V_UV_SCLR : 1;
5286  __OM uint32_t VDD1V5_UV_SCLR : 1;
5287  __OM uint32_t MON_OV_SCLR : 1;
5288  __OM uint32_t VS_OV_SCLR : 1;
5289  __OM uint32_t VDD5V_OV_SCLR : 1;
5290  __OM uint32_t VDD1V5_OV_SCLR : 1;
5291  } bit;
5292  } SYS_SUPPLY_IRQ_CLR;
5293 
5294  union
5295  {
5296  __IOM uint32_t reg;
5298  struct
5299  {
5300  __IOM uint32_t LIN_OC_IE : 1;
5301  __IOM uint32_t LIN_OT_IE : 1;
5302  __IOM uint32_t LIN_TMOUT_IE : 1;
5303  __IM uint32_t : 3;
5304  __IOM uint32_t PMU_OTWARN_IE : 1;
5305  __IOM uint32_t PMU_OT_IE : 1;
5307  __IOM uint32_t SYS_OTWARN_IE : 1;
5308  __IOM uint32_t SYS_OT_IE : 1;
5310  __IOM uint32_t REFBG_LOTHWARN_IE : 1;
5311  __IOM uint32_t REFBG_UPTHWARN_IE : 1;
5312  __IOM uint32_t VREF5V_LOWTH_IE : 1;
5314  __IOM uint32_t VREF5V_UPTH_IE : 1;
5316  __IOM uint32_t VREF5V_OVL_IE : 1;
5317  __IOM uint32_t ADC2_ESM_IE : 1;
5318  __IOM uint32_t PHU_ZCLOW_IE : 1;
5319  __IOM uint32_t PHU_ZCHI_IE : 1;
5320  __IOM uint32_t PHV_ZCLOW_IE : 1;
5321  __IOM uint32_t PHV_ZCHI_IE : 1;
5322  __IOM uint32_t PHW_ZCLOW_IE : 1;
5323  __IOM uint32_t PHW_ZCHI_IE : 1;
5324  __IOM uint32_t ADC3_EOC_IE : 1;
5325  __IOM uint32_t ADC4_EOC_IE : 1;
5326  } bit;
5327  } SYS_IRQ_CTRL;
5328  __IM uint32_t RESERVED2;
5329 
5330  union
5331  {
5332  __IOM uint32_t reg;
5334  struct
5335  {
5336  __IM uint32_t : 1;
5337  __IOM uint32_t CLKWDT_SD_DIS : 1;
5338  __IM uint32_t : 5;
5339  __IOM uint32_t FAIL_PS_DIS : 1;
5340  __IOM uint32_t LIN_VS_UV_SD_DIS : 1;
5341  __IM uint32_t : 5;
5342  __IOM uint32_t SYS_VSD_OV_SLM_DIS : 1;
5343  __IM uint32_t : 9;
5344  __IOM uint32_t SYS_OT_PS_DIS : 1;
5345  __IOM uint32_t CLKLOSS_SD_DIS : 1;
5346  __IOM uint32_t CLKWDT_RES_SD_DIS : 1;
5347  } bit;
5348  } PCU_CTRL_STS;
5349 
5350  union
5351  {
5352  __IOM uint32_t reg;
5354  struct
5355  {
5356  __IOM uint32_t WDP_SEL : 6;
5357  __IOM uint32_t SOWCONF : 2;
5358  } bit;
5359  } WDT1_TRIG;
5360  __IM uint32_t RESERVED3[7];
5361 
5362  union
5363  {
5364  __IOM uint32_t reg;
5366  struct
5367  {
5368  __OM uint32_t LS1_DS_ICLR : 1;
5369  __OM uint32_t LS2_DS_ICLR : 1;
5370  __OM uint32_t HS1_DS_ICLR : 1;
5372  __OM uint32_t HS2_DS_ICLR : 1;
5374  __OM uint32_t LS3_DS_ICLR : 1;
5375  __OM uint32_t HS3_DS_ICLR : 1;
5377  __IM uint32_t : 4;
5378  __OM uint32_t LS1_OC_ICLR : 1;
5379  __OM uint32_t LS2_OC_ICLR : 1;
5380  __OM uint32_t HS1_OC_ICLR : 1;
5381  __OM uint32_t HS2_OC_ICLR : 1;
5382  __OM uint32_t LS3_OC_ICLR : 1;
5383  __OM uint32_t HS3_OC_ICLR : 1;
5384  __OM uint32_t VCP_LOWTH2_ICLR : 1;
5386  __OM uint32_t VCP_LOWTH1_ICLR : 1;
5388  __OM uint32_t VCP_UPTH_ICLR : 1;
5390  __OM uint32_t VSD_LOWTH_ICLR : 1;
5392  __OM uint32_t VSD_UPTH_ICLR : 1;
5394  __IM uint32_t : 3;
5395  __OM uint32_t VCP_LOWTH2_SCLR : 1;
5397  __OM uint32_t VCP_LOWTH1_SCLR : 1;
5399  __OM uint32_t VCP_UPTH_SCLR : 1;
5401  __OM uint32_t VSD_LOWTH_SCLR : 1;
5403  __OM uint32_t VSD_UPTH_SCLR : 1;
5406  } bit;
5407  } BDRV_ISCLR;
5408 
5409  union
5410  {
5411  __IOM uint32_t reg;
5413  struct
5414  {
5415  __IM uint32_t LS1_DS_IS : 1;
5416  __IM uint32_t LS2_DS_IS : 1;
5417  __IM uint32_t HS1_DS_IS : 1;
5419  __IM uint32_t HS2_DS_IS : 1;
5421  __IM uint32_t LS3_DS_IS : 1;
5422  __IM uint32_t HS3_DS_IS : 1;
5424  __IM uint32_t : 4;
5425  __IM uint32_t LS1_OC_IS : 1;
5426  __IM uint32_t LS2_OC_IS : 1;
5427  __IM uint32_t HS1_OC_IS : 1;
5428  __IM uint32_t HS2_OC_IS : 1;
5429  __IM uint32_t LS3_OC_IS : 1;
5430  __IM uint32_t HS3_OC_IS : 1;
5431  __IM uint32_t VCP_LOWTH2_IS : 1;
5433  __IM uint32_t VCP_LOWTH1_IS : 1;
5435  __IM uint32_t VCP_UPTH_IS : 1;
5437  __IM uint32_t VSD_LOWTH_IS : 1;
5439  __IM uint32_t VSD_UPTH_IS : 1;
5441  __IM uint32_t : 3;
5442  __IM uint32_t VCP_LOWTH2_STS : 1;
5444  __IM uint32_t VCP_LOWTH1_STS : 1;
5446  __IM uint32_t VCP_UPTH_STS : 1;
5448  __IM uint32_t VSD_LOWTH_STS : 1;
5450  __IM uint32_t VSD_UPTH_STS : 1;
5453  } bit;
5454  } BDRV_IS;
5455 
5456  union
5457  {
5458  __IOM uint32_t reg;
5460  struct
5461  {
5462  __IOM uint32_t LS1_DS_IE : 1;
5463  __IOM uint32_t LS2_DS_IE : 1;
5464  __IOM uint32_t HS1_DS_IE : 1;
5466  __IOM uint32_t HS2_DS_IE : 1;
5468  __IOM uint32_t LS3_DS_IE : 1;
5469  __IOM uint32_t HS3_DS_IE : 1;
5471  __IM uint32_t : 4;
5472  __IOM uint32_t LS1_OC_IE : 1;
5473  __IOM uint32_t LS2_OC_IE : 1;
5474  __IOM uint32_t HS1_OC_IE : 1;
5475  __IOM uint32_t HS2_OC_IE : 1;
5476  __IOM uint32_t LS3_OC_IE : 1;
5477  __IOM uint32_t HS3_OC_IE : 1;
5478  __IOM uint32_t VCP_LOWTH2_IE : 1;
5479  __IOM uint32_t VCP_LOWTH1_IE : 1;
5480  __IOM uint32_t VCP_UPTH_IE : 1;
5481  __IOM uint32_t VSD_LOWTH_IE : 1;
5482  __IOM uint32_t VSD_UPTH_IE : 1;
5483  } bit;
5484  } BDRV_IRQ_CTRL;
5485  __IM uint32_t RESERVED4[3];
5486 
5487  union
5488  {
5489  __IOM uint32_t reg;
5491  struct
5492  {
5493  __IOM uint32_t STCALIB : 26;
5494  } bit;
5495  } STCALIB;
5496  __IM uint32_t RESERVED5[4];
5497 
5498  union
5499  {
5500  __IOM uint32_t reg;
5502  struct
5503  {
5504  __IM uint32_t DBFSTS : 1;
5505  __IM uint32_t SBFSTS : 1;
5506  } bit;
5507  } BFSTS;
5508 
5509  union
5510  {
5511  __IOM uint32_t reg;
5513  struct
5514  {
5515  __IM uint32_t DBFA : 32;
5516  } bit;
5517  } DBFA;
5518 
5519  union
5520  {
5521  __IOM uint32_t reg;
5523  struct
5524  {
5525  __IM uint32_t SBFA : 32;
5526  } bit;
5527  } SBFA;
5528 
5529  union
5530  {
5531  __IOM uint32_t reg;
5533  struct
5534  {
5535  __OM uint32_t DBFSTSCLR : 1;
5536  __OM uint32_t SBFSTSCLR : 1;
5537  } bit;
5538  } BFSTS_CLR;
5539 } SCUPM_Type;
5543 /* =========================================================================================================================== */
5544 /* ================ SSC1 ================ */
5545 /* =========================================================================================================================== */
5546 
5547 
5552 typedef struct
5553 {
5554 
5555  union
5556  {
5557  __IOM uint16_t reg;
5559  struct
5560  {
5561  __IOM uint16_t MIS_0 : 1;
5565  __IOM uint16_t SIS : 1;
5570  __IOM uint16_t CIS : 1;
5575  __IOM uint16_t MIS_1 : 1;
5577  } bit;
5578  } PISEL;
5579  __IM uint16_t RESERVED;
5580 
5581  union
5582  {
5583  __IOM uint16_t reg;
5585  struct
5586  {
5587  __IM uint16_t BC : 4;
5589  __IM uint16_t TE : 1;
5590  __IM uint16_t RE : 1;
5591  __IM uint16_t PE : 1;
5592  __IM uint16_t BE : 1;
5593  __IM uint16_t BSY : 1;
5594  __IM uint16_t : 1;
5595  __IOM uint16_t MS : 1;
5596  __IOM uint16_t EN : 1;
5597  } bit;
5598  } CON;
5599  __IM uint16_t RESERVED1;
5600 
5601  union
5602  {
5603  __IOM uint16_t reg;
5605  struct
5606  {
5607  __IOM uint16_t TB_VALUE : 16;
5608  } bit;
5609  } TB;
5610  __IM uint16_t RESERVED2;
5611 
5612  union
5613  {
5614  __IOM uint16_t reg;
5616  struct
5617  {
5618  __IM uint16_t RB_VALUE : 16;
5619  } bit;
5620  } RB;
5621  __IM uint16_t RESERVED3;
5622 
5623  union
5624  {
5625  __IOM uint16_t reg;
5627  struct
5628  {
5629  __IOM uint16_t BR_VALUE : 16;
5630  } bit;
5631  } BR;
5632  __IM uint16_t RESERVED4;
5633 
5634  union
5635  {
5636  __IOM uint16_t reg;
5638  struct
5639  {
5640  __IM uint16_t : 8;
5641  __OM uint16_t TECLR : 1;
5642  __OM uint16_t RECLR : 1;
5643  __OM uint16_t PECLR : 1;
5644  __OM uint16_t BECLR : 1;
5645  } bit;
5646  } ISRCLR;
5647 } SSC1_Type;
5651 /* =========================================================================================================================== */
5652 /* ================ SSC2 ================ */
5653 /* =========================================================================================================================== */
5654 
5655 
5660 typedef struct
5661 {
5662 
5663  union
5664  {
5665  __IOM uint16_t reg;
5667  struct
5668  {
5669  __IOM uint16_t MIS_0 : 1;
5673  __IOM uint16_t SIS : 1;
5678  __IOM uint16_t CIS : 1;
5683  __IOM uint16_t MIS_1 : 1;
5685  } bit;
5686  } PISEL;
5687  __IM uint16_t RESERVED;
5688 
5689  union
5690  {
5691  __IOM uint16_t reg;
5693  struct
5694  {
5695  __IM uint16_t BC : 4;
5697  __IM uint16_t TE : 1;
5698  __IM uint16_t RE : 1;
5699  __IM uint16_t PE : 1;
5700  __IM uint16_t BE : 1;
5701  __IM uint16_t BSY : 1;
5702  __IM uint16_t : 1;
5703  __IOM uint16_t MS : 1;
5704  __IOM uint16_t EN : 1;
5705  } bit;
5706  } CON;
5707  __IM uint16_t RESERVED1;
5708 
5709  union
5710  {
5711  __IOM uint16_t reg;
5713  struct
5714  {
5715  __IOM uint16_t TB_VALUE : 16;
5716  } bit;
5717  } TB;
5718  __IM uint16_t RESERVED2;
5719 
5720  union
5721  {
5722  __IOM uint16_t reg;
5724  struct
5725  {
5726  __IM uint16_t RB_VALUE : 16;
5727  } bit;
5728  } RB;
5729  __IM uint16_t RESERVED3;
5730 
5731  union
5732  {
5733  __IOM uint16_t reg;
5735  struct
5736  {
5737  __IOM uint16_t BR_VALUE : 16;
5738  } bit;
5739  } BR;
5740  __IM uint16_t RESERVED4;
5741 
5742  union
5743  {
5744  __IOM uint16_t reg;
5746  struct
5747  {
5748  __IM uint16_t : 8;
5749  __OM uint16_t TECLR : 1;
5750  __OM uint16_t RECLR : 1;
5751  __OM uint16_t PECLR : 1;
5752  __OM uint16_t BECLR : 1;
5753  } bit;
5754  } ISRCLR;
5755 } SSC2_Type;
5759 /* =========================================================================================================================== */
5760 /* ================ TIMER2x ================ */
5761 /* =========================================================================================================================== */
5762 
5763 
5768 typedef struct
5769 {
5770 
5771  union
5772  {
5773  __IOM uint8_t reg;
5775  struct
5776  {
5777  __IOM uint8_t CP_RL2 : 1;
5778  __IOM uint8_t C_T2 : 1;
5779  __IOM uint8_t TR2 : 1;
5780  __IOM uint8_t EXEN2 : 1;
5782  __IM uint8_t EXF2 : 1;
5783  __IM uint8_t TF2 : 1;
5784  } bit;
5785  } T2CON;
5786  __IM uint8_t RESERVED[3];
5787 
5788  union
5789  {
5790  __IOM uint8_t reg;
5792  struct
5793  {
5794  __IOM uint8_t DCEN : 1;
5795  __IOM uint8_t T2PRE : 3;
5796  __IOM uint8_t PREN : 1;
5797  __IOM uint8_t EDGESEL : 1;
5798  __IOM uint8_t T2RHEN : 1;
5799  __IOM uint8_t T2REGS : 1;
5800  } bit;
5801  } T2MOD;
5802  __IM uint8_t RESERVED1[3];
5803 
5804  union
5805  {
5806  __IOM uint8_t reg;
5808  struct
5809  {
5810  __IOM uint8_t RC2 : 8;
5811  } bit;
5812  } RC2L;
5813  __IM uint8_t RESERVED2[3];
5814 
5815  union
5816  {
5817  __IOM uint8_t reg;
5819  struct
5820  {
5821  __IOM uint8_t RC2 : 8;
5822  } bit;
5823  } RC2H;
5824  __IM uint8_t RESERVED3[3];
5825 
5826  union
5827  {
5828  __IOM uint8_t reg;
5830  struct
5831  {
5832  __IOM uint8_t T2L : 8;
5833  } bit;
5834  } T2L;
5835  __IM uint8_t RESERVED4[3];
5836 
5837  union
5838  {
5839  __IOM uint8_t reg;
5841  struct
5842  {
5843  __IOM uint8_t T2H : 8;
5844  } bit;
5845  } T2H;
5846  __IM uint8_t RESERVED5[3];
5847 
5848  union
5849  {
5850  __IOM uint8_t reg;
5852  struct
5853  {
5854  __IOM uint8_t EXF2EN : 1;
5855  __IOM uint8_t TF2EN : 1;
5856  } bit;
5857  } T2CON1;
5858  __IM uint8_t RESERVED6[3];
5859 
5860  union
5861  {
5862  __IOM uint8_t reg;
5864  struct
5865  {
5866  __IM uint8_t : 6;
5867  __OM uint8_t EXF2CLR : 1;
5868  __OM uint8_t TF2CLR : 1;
5869  } bit;
5870  } T2ICLR;
5871 } TIMER2x_Type;
5875 /* =========================================================================================================================== */
5876 /* ================ TIMER3 ================ */
5877 /* =========================================================================================================================== */
5878 
5879 
5884 typedef struct
5885 {
5886 
5887  union
5888  {
5889  __IOM uint32_t reg;
5891  struct
5892  {
5893  __IOM uint32_t T3_TRIGG_INP_SEL : 3;
5895  __IOM uint32_t T3_RES_CONF : 2;
5896  __IOM uint32_t RETRIG : 1;
5898  } bit;
5899  } T3_TRIGG_CTRL;
5900 
5901  union
5902  {
5903  __IOM uint32_t reg;
5905  struct
5906  {
5907  __IOM uint32_t LO : 8;
5908  __IOM uint32_t HI : 8;
5909  } bit;
5910  } CMP;
5911 
5912  union
5913  {
5914  __IOM uint32_t reg;
5916  struct
5917  {
5918  __IOM uint32_t LO : 8;
5919  __IOM uint32_t HI : 8;
5920  } bit;
5921  } CNT;
5922 
5923  union
5924  {
5925  __IOM uint32_t reg;
5927  struct
5928  {
5929  __IOM uint32_t T3_PD_N : 1;
5930  __IOM uint32_t T3_RD_REQ : 1;
5931  __IOM uint32_t T3_RD_REQ_CONF : 1;
5932  __IOM uint32_t CNT_RDY : 1;
5933  __IOM uint32_t TR3H : 1;
5934  __IM uint32_t T3H_OVF_STS : 1;
5935  __IOM uint32_t TR3L : 1;
5936  __IM uint32_t T3L_OVF_STS : 1;
5937  __IOM uint32_t T3L_OVF_IE : 1;
5938  __IOM uint32_t T3H_OVF_IE : 1;
5939  } bit;
5940  } CTRL;
5941 
5942  union
5943  {
5944  __IOM uint32_t reg;
5946  struct
5947  {
5948  __IOM uint32_t T3M : 2;
5949  __IM uint32_t : 4;
5950  __IOM uint32_t T3_SUBM : 2;
5951  } bit;
5952  } MODE_CONF;
5953 
5954  union
5955  {
5956  __IOM uint32_t reg;
5958  struct
5959  {
5960  __IM uint32_t : 5;
5961  __OM uint32_t T3H_OVF_ICLR : 1;
5962  __IM uint32_t : 1;
5963  __OM uint32_t T3L_OVF_ICLR : 1;
5964  } bit;
5965  } ISRCLR;
5966 } TIMER3_Type;
5970 /* =========================================================================================================================== */
5971 /* ================ UARTx ================ */
5972 /* =========================================================================================================================== */
5973 
5974 
5979 typedef struct
5980 {
5981 
5982  union
5983  {
5984  __IOM uint8_t reg;
5986  struct
5987  {
5988  __IOM uint8_t RI : 1;
5989  __IOM uint8_t TI : 1;
5990  __IOM uint8_t RB8 : 1;
5991  __IOM uint8_t TB8 : 1;
5992  __IOM uint8_t REN : 1;
5993  __IOM uint8_t SM2 : 1;
5995  __IOM uint8_t SM1 : 1;
5996  __IOM uint8_t SM0 : 1;
5997  } bit;
5998  } SCON;
5999  __IM uint8_t RESERVED[3];
6000 
6001  union
6002  {
6003  __IOM uint8_t reg;
6005  struct
6006  {
6007  __IOM uint8_t VAL : 8;
6008  } bit;
6009  } SBUF;
6010  __IM uint8_t RESERVED1[3];
6011 
6012  union
6013  {
6014  __IOM uint8_t reg;
6016  struct
6017  {
6018  __OM uint8_t RICLR : 1;
6019  __OM uint8_t TICLR : 1;
6020  } bit;
6021  } SCONCLR;
6022 } UART_Type; /* End of group Device_Peripheral_peripherals */
6028 
6029 
6030 /* =========================================================================================================================== */
6031 /* ================ Device Specific Peripheral Address Map ================ */
6032 /* =========================================================================================================================== */
6033 
6034 
6039 #define ADC1_BASE 0x40004000UL
6040 #define ADC2_BASE 0x4801C000UL
6041 #define ADC34_BASE 0x40008000UL
6042 #define BDRV_BASE 0x40034000UL
6043 #define CCU6_BASE 0x4000C000UL
6044 #define CPU_BASE 0xE000E000UL
6045 #define CSA_BASE 0x48018000UL
6046 #define DMA_BASE 0x50014000UL
6047 #define GPT12E_BASE 0x40010000UL
6048 #define LIN_BASE 0x4801E000UL
6049 #define MF_BASE 0x48018000UL
6050 #define MON_BASE 0x50004000UL
6051 #define PMU_BASE 0x50004000UL
6052 #define PORT_BASE 0x48028000UL
6053 #define SCU_BASE 0x50005000UL
6054 #define SCUPM_BASE 0x50006000UL
6055 #define SSC1_BASE 0x48024000UL
6056 #define SSC2_BASE 0x48026000UL
6057 #define TIMER2_BASE 0x48004000UL
6058 #define TIMER21_BASE 0x48005000UL
6059 #define TIMER3_BASE 0x48006000UL
6060 #define UART1_BASE 0x48020000UL
6061 #define UART2_BASE 0x48022000UL
6062  /* End of group Device_Peripheral_peripheralAddr */
6064 
6065 
6066 /* =========================================================================================================================== */
6067 /* ================ Peripheral declaration ================ */
6068 /* =========================================================================================================================== */
6069 
6070 
6074 /* Note 923: cast from unsigned long to pointer [MISRA Rule 45] */
6075 /* disable lint warning 923, to accept the conversion of the */
6076 /* base address into a pointer of the peripheral type. */
6077 /* This is a preferable exception as it generates the fastest */
6078 /* code, compared to other solutions which do not require a */
6079 /* suppressing of this MISRA rule */
6080 
6081 
6082 #ifndef UNIT_TESTING_LV2
6083 #define ADC1 ((ADC1_Type*) ADC1_BASE)
6084 #define ADC2 ((ADC2_Type*) ADC2_BASE)
6085 #define ADC34 ((ADC34_Type*) ADC34_BASE)
6086 #define BDRV ((BDRV_Type*) BDRV_BASE)
6087 #define CCU6 ((CCU6_Type*) CCU6_BASE)
6088 #define CSA ((CSA_Type*) CSA_BASE)
6089 #define CPU ((CPU_Type*) CPU_BASE)
6090 #define DMA ((DMA_Type*) DMA_BASE)
6091 #define GPT12E ((GPT12E_Type*) GPT12E_BASE)
6092 #define LIN ((LIN_Type*) LIN_BASE)
6093 #define MF ((MF_Type*) MF_BASE)
6094 #define MON ((MON_Type*) MON_BASE)
6095 #define PMU ((PMU_Type*) PMU_BASE)
6096 #define PORT ((PORT_Type*) PORT_BASE)
6097 #define SCU ((SCU_Type*) SCU_BASE)
6098 #define SCUPM ((SCUPM_Type*) SCUPM_BASE)
6099 #define SSC1 ((SSC1_Type*) SSC1_BASE)
6100 #define SSC2 ((SSC2_Type*) SSC2_BASE)
6101 #define TIMER2 ((TIMER2x_Type*) TIMER2_BASE)
6102 #define TIMER21 ((TIMER2x_Type*) TIMER21_BASE)
6103 #define TIMER3 ((TIMER3_Type*) TIMER3_BASE)
6104 #define UART1 ((UART_Type*) UART1_BASE)
6105 #define UART2 ((UART_Type*) UART2_BASE)
6106 #else
6107 extern ADC1_Type *ADC1;
6108 extern ADC2_Type *ADC2;
6109 extern ADC34_Type *ADC34;
6110 extern BDRV_Type *BDRV;
6111 extern CCU6_Type *CCU6;
6112 extern CSA_Type *CSA;
6113 extern CPU_Type *CPU;
6114 extern DMA_Type *DMA;
6115 extern GPT12E_Type *GPT12E;
6116 extern LIN_Type *LIN;
6117 extern MF_Type *MF;
6118 extern MON_Type *MON;
6119 extern PMU_Type *PMU;
6120 extern PORT_Type *PORT;
6121 extern SCU_Type *SCU;
6122 extern SCUPM_Type *SCUPM;
6123 extern SSC1_Type *SSC1;
6124 extern SSC2_Type *SSC2;
6125 extern TIMER2x_Type *TIMER2;
6126 extern TIMER2x_Type *TIMER21;
6127 extern TIMER3_Type *TIMER3;
6128 extern UART_Type *UART1;
6129 extern UART_Type *UART2;
6130 #endif /* UNIT_TESTING_LV2 */
6131 
6132 
6133  /* End of group Device_Peripheral_declaration */
6135 
6136 
6137 /* =========================================================================================================================== */
6138 /* ================ Pos/Mask Peripheral Section ================ */
6139 /* =========================================================================================================================== */
6140 
6141 
6147 /* violation: Identifier clash */
6148 /* =========================================================================================================================== */
6149 /* ================ ADC1 ================ */
6150 /* =========================================================================================================================== */
6151 
6152 /* ======================================================== CHx_EIM ======================================================== */
6153 #define ADC1_CHx_EIM_TRIG_SEL_Pos (16UL)
6154 #define ADC1_CHx_EIM_TRIG_SEL_Msk (0x70000UL)
6155 #define ADC1_CHx_EIM_REP_Pos (4UL)
6156 #define ADC1_CHx_EIM_REP_Msk (0x70UL)
6157 #define ADC1_CHx_EIM_CHx_Pos (0UL)
6158 #define ADC1_CHx_EIM_CHx_Msk (0x7UL)
6159 /* ======================================================== CHx_ESM ======================================================== */
6160 #define ADC1_CHx_ESM_TRIG_SEL_Pos (16UL)
6161 #define ADC1_CHx_ESM_TRIG_SEL_Msk (0x70000UL)
6162 #define ADC1_CHx_ESM_ESM_0_Pos (0UL)
6163 #define ADC1_CHx_ESM_ESM_0_Msk (0xffUL)
6164 /* ======================================================= CTRL_STS ======================================================== */
6165 #define ADC1_CTRL_STS_IN_MUX_SEL_Pos (4UL)
6166 #define ADC1_CTRL_STS_IN_MUX_SEL_Msk (0x70UL)
6167 #define ADC1_CTRL_STS_EOC_Pos (3UL)
6168 #define ADC1_CTRL_STS_EOC_Msk (0x8UL)
6169 #define ADC1_CTRL_STS_SOC_Pos (2UL)
6170 #define ADC1_CTRL_STS_SOC_Msk (0x4UL)
6171 #define ADC1_CTRL_STS_PD_N_Pos (0UL)
6172 #define ADC1_CTRL_STS_PD_N_Msk (0x1UL)
6173 /* ========================================================= DWSEL ========================================================= */
6174 #define ADC1_DWSEL_ch7_Pos (7UL)
6175 #define ADC1_DWSEL_ch7_Msk (0x80UL)
6176 #define ADC1_DWSEL_ch6_Pos (6UL)
6177 #define ADC1_DWSEL_ch6_Msk (0x40UL)
6178 #define ADC1_DWSEL_ch5_Pos (5UL)
6179 #define ADC1_DWSEL_ch5_Msk (0x20UL)
6180 #define ADC1_DWSEL_ch4_Pos (4UL)
6181 #define ADC1_DWSEL_ch4_Msk (0x10UL)
6182 #define ADC1_DWSEL_ch3_Pos (3UL)
6183 #define ADC1_DWSEL_ch3_Msk (0x8UL)
6184 #define ADC1_DWSEL_ch2_Pos (2UL)
6185 #define ADC1_DWSEL_ch2_Msk (0x4UL)
6186 #define ADC1_DWSEL_ch1_Pos (1UL)
6187 #define ADC1_DWSEL_ch1_Msk (0x2UL)
6188 #define ADC1_DWSEL_ch0_Pos (0UL)
6189 #define ADC1_DWSEL_ch0_Msk (0x1UL)
6190 /* ======================================================== GLOBCTR ======================================================== */
6191 #define ADC1_GLOBCTR_ANON_Pos (8UL)
6192 #define ADC1_GLOBCTR_ANON_Msk (0x300UL)
6193 #define ADC1_GLOBCTR_DIVA_Pos (0UL)
6194 #define ADC1_GLOBCTR_DIVA_Msk (0x3fUL)
6195 /* ======================================================== GLOBSTR ======================================================== */
6196 #define ADC1_GLOBSTR_ANON_ST_Pos (8UL)
6197 #define ADC1_GLOBSTR_ANON_ST_Msk (0x300UL)
6198 #define ADC1_GLOBSTR_CHNR_Pos (3UL)
6199 #define ADC1_GLOBSTR_CHNR_Msk (0x38UL)
6200 #define ADC1_GLOBSTR_SAMPLE_Pos (1UL)
6201 #define ADC1_GLOBSTR_SAMPLE_Msk (0x2UL)
6202 #define ADC1_GLOBSTR_BUSY_Pos (0UL)
6203 #define ADC1_GLOBSTR_BUSY_Msk (0x1UL)
6204 /* ========================================================= ICLR ========================================================== */
6205 #define ADC1_ICLR_ESM_ICLR_Pos (9UL)
6206 #define ADC1_ICLR_ESM_ICLR_Msk (0x200UL)
6207 #define ADC1_ICLR_EIM_ICLR_Pos (8UL)
6208 #define ADC1_ICLR_EIM_ICLR_Msk (0x100UL)
6209 #define ADC1_ICLR_CH7_ICLR_Pos (7UL)
6210 #define ADC1_ICLR_CH7_ICLR_Msk (0x80UL)
6211 #define ADC1_ICLR_CH6_ICLR_Pos (6UL)
6212 #define ADC1_ICLR_CH6_ICLR_Msk (0x40UL)
6213 #define ADC1_ICLR_CH5_ICLR_Pos (5UL)
6214 #define ADC1_ICLR_CH5_ICLR_Msk (0x20UL)
6215 #define ADC1_ICLR_CH4_ICLR_Pos (4UL)
6216 #define ADC1_ICLR_CH4_ICLR_Msk (0x10UL)
6217 #define ADC1_ICLR_CH3_ICLR_Pos (3UL)
6218 #define ADC1_ICLR_CH3_ICLR_Msk (0x8UL)
6219 #define ADC1_ICLR_CH2_ICLR_Pos (2UL)
6220 #define ADC1_ICLR_CH2_ICLR_Msk (0x4UL)
6221 #define ADC1_ICLR_CH1_ICLR_Pos (1UL)
6222 #define ADC1_ICLR_CH1_ICLR_Msk (0x2UL)
6223 #define ADC1_ICLR_CH0_ICLR_Pos (0UL)
6224 #define ADC1_ICLR_CH0_ICLR_Msk (0x1UL)
6225 /* ========================================================== IE =========================================================== */
6226 #define ADC1_IE_ESM_IE_Pos (9UL)
6227 #define ADC1_IE_ESM_IE_Msk (0x200UL)
6228 #define ADC1_IE_EIM_IE_Pos (8UL)
6229 #define ADC1_IE_EIM_IE_Msk (0x100UL)
6230 #define ADC1_IE_CH7_IE_Pos (7UL)
6231 #define ADC1_IE_CH7_IE_Msk (0x80UL)
6232 #define ADC1_IE_CH6_IE_Pos (6UL)
6233 #define ADC1_IE_CH6_IE_Msk (0x40UL)
6234 #define ADC1_IE_CH5_IE_Pos (5UL)
6235 #define ADC1_IE_CH5_IE_Msk (0x20UL)
6236 #define ADC1_IE_CH4_IE_Pos (4UL)
6237 #define ADC1_IE_CH4_IE_Msk (0x10UL)
6238 #define ADC1_IE_CH3_IE_Pos (3UL)
6239 #define ADC1_IE_CH3_IE_Msk (0x8UL)
6240 #define ADC1_IE_CH2_IE_Pos (2UL)
6241 #define ADC1_IE_CH2_IE_Msk (0x4UL)
6242 #define ADC1_IE_CH1_IE_Pos (1UL)
6243 #define ADC1_IE_CH1_IE_Msk (0x2UL)
6244 #define ADC1_IE_CH0_IE_Pos (0UL)
6245 #define ADC1_IE_CH0_IE_Msk (0x1UL)
6246 /* ========================================================== IS =========================================================== */
6247 #define ADC1_IS_ESM_STS_Pos (9UL)
6248 #define ADC1_IS_ESM_STS_Msk (0x200UL)
6249 #define ADC1_IS_EIM_STS_Pos (8UL)
6250 #define ADC1_IS_EIM_STS_Msk (0x100UL)
6251 #define ADC1_IS_CH7_STS_Pos (7UL)
6252 #define ADC1_IS_CH7_STS_Msk (0x80UL)
6253 #define ADC1_IS_CH6_STS_Pos (6UL)
6254 #define ADC1_IS_CH6_STS_Msk (0x40UL)
6255 #define ADC1_IS_CH5_STS_Pos (5UL)
6256 #define ADC1_IS_CH5_STS_Msk (0x20UL)
6257 #define ADC1_IS_CH4_STS_Pos (4UL)
6258 #define ADC1_IS_CH4_STS_Msk (0x10UL)
6259 #define ADC1_IS_CH3_STS_Pos (3UL)
6260 #define ADC1_IS_CH3_STS_Msk (0x8UL)
6261 #define ADC1_IS_CH2_STS_Pos (2UL)
6262 #define ADC1_IS_CH2_STS_Msk (0x4UL)
6263 #define ADC1_IS_CH1_STS_Pos (1UL)
6264 #define ADC1_IS_CH1_STS_Msk (0x2UL)
6265 #define ADC1_IS_CH0_STS_Pos (0UL)
6266 #define ADC1_IS_CH0_STS_Msk (0x1UL)
6267 /* ======================================================= RES_OUT0 ======================================================== */
6268 #define ADC1_RES_OUT0_OF0_Pos (18UL)
6269 #define ADC1_RES_OUT0_OF0_Msk (0x40000UL)
6270 #define ADC1_RES_OUT0_VF0_Pos (17UL)
6271 #define ADC1_RES_OUT0_VF0_Msk (0x20000UL)
6272 #define ADC1_RES_OUT0_WFR0_Pos (16UL)
6273 #define ADC1_RES_OUT0_WFR0_Msk (0x10000UL)
6274 #define ADC1_RES_OUT0_OUT_CH0_Pos (0UL)
6275 #define ADC1_RES_OUT0_OUT_CH0_Msk (0xfffUL)
6276 /* ======================================================= RES_OUT1 ======================================================== */
6277 #define ADC1_RES_OUT1_OF1_Pos (18UL)
6278 #define ADC1_RES_OUT1_OF1_Msk (0x40000UL)
6279 #define ADC1_RES_OUT1_VF1_Pos (17UL)
6280 #define ADC1_RES_OUT1_VF1_Msk (0x20000UL)
6281 #define ADC1_RES_OUT1_WFR1_Pos (16UL)
6282 #define ADC1_RES_OUT1_WFR1_Msk (0x10000UL)
6283 #define ADC1_RES_OUT1_OUT_CH1_Pos (0UL)
6284 #define ADC1_RES_OUT1_OUT_CH1_Msk (0xfffUL)
6285 /* ======================================================= RES_OUT2 ======================================================== */
6286 #define ADC1_RES_OUT2_OF2_Pos (18UL)
6287 #define ADC1_RES_OUT2_OF2_Msk (0x40000UL)
6288 #define ADC1_RES_OUT2_VF2_Pos (17UL)
6289 #define ADC1_RES_OUT2_VF2_Msk (0x20000UL)
6290 #define ADC1_RES_OUT2_WFR2_Pos (16UL)
6291 #define ADC1_RES_OUT2_WFR2_Msk (0x10000UL)
6292 #define ADC1_RES_OUT2_OUT_CH2_Pos (0UL)
6293 #define ADC1_RES_OUT2_OUT_CH2_Msk (0xfffUL)
6294 /* ======================================================= RES_OUT3 ======================================================== */
6295 #define ADC1_RES_OUT3_OF3_Pos (18UL)
6296 #define ADC1_RES_OUT3_OF3_Msk (0x40000UL)
6297 #define ADC1_RES_OUT3_VF3_Pos (17UL)
6298 #define ADC1_RES_OUT3_VF3_Msk (0x20000UL)
6299 #define ADC1_RES_OUT3_WFR3_Pos (16UL)
6300 #define ADC1_RES_OUT3_WFR3_Msk (0x10000UL)
6301 #define ADC1_RES_OUT3_OUT_CH3_Pos (0UL)
6302 #define ADC1_RES_OUT3_OUT_CH3_Msk (0xfffUL)
6303 /* ======================================================= RES_OUT4 ======================================================== */
6304 #define ADC1_RES_OUT4_OF4_Pos (18UL)
6305 #define ADC1_RES_OUT4_OF4_Msk (0x40000UL)
6306 #define ADC1_RES_OUT4_VF4_Pos (17UL)
6307 #define ADC1_RES_OUT4_VF4_Msk (0x20000UL)
6308 #define ADC1_RES_OUT4_WFR4_Pos (16UL)
6309 #define ADC1_RES_OUT4_WFR4_Msk (0x10000UL)
6310 #define ADC1_RES_OUT4_OUT_CH4_Pos (0UL)
6311 #define ADC1_RES_OUT4_OUT_CH4_Msk (0xfffUL)
6312 /* ======================================================= RES_OUT5 ======================================================== */
6313 #define ADC1_RES_OUT5_OF5_Pos (18UL)
6314 #define ADC1_RES_OUT5_OF5_Msk (0x40000UL)
6315 #define ADC1_RES_OUT5_VF5_Pos (17UL)
6316 #define ADC1_RES_OUT5_VF5_Msk (0x20000UL)
6317 #define ADC1_RES_OUT5_WFR5_Pos (16UL)
6318 #define ADC1_RES_OUT5_WFR5_Msk (0x10000UL)
6319 #define ADC1_RES_OUT5_OUT_CH5_Pos (0UL)
6320 #define ADC1_RES_OUT5_OUT_CH5_Msk (0xfffUL)
6321 /* ======================================================= RES_OUT6 ======================================================== */
6322 #define ADC1_RES_OUT6_OF6_Pos (18UL)
6323 #define ADC1_RES_OUT6_OF6_Msk (0x40000UL)
6324 #define ADC1_RES_OUT6_VF6_Pos (17UL)
6325 #define ADC1_RES_OUT6_VF6_Msk (0x20000UL)
6326 #define ADC1_RES_OUT6_WFR6_Pos (16UL)
6327 #define ADC1_RES_OUT6_WFR6_Msk (0x10000UL)
6328 #define ADC1_RES_OUT6_OUT_CH6_Pos (0UL)
6329 #define ADC1_RES_OUT6_OUT_CH6_Msk (0xfffUL)
6330 /* ======================================================= RES_OUT7 ======================================================== */
6331 #define ADC1_RES_OUT7_OF7_Pos (18UL)
6332 #define ADC1_RES_OUT7_OF7_Msk (0x40000UL)
6333 #define ADC1_RES_OUT7_VF7_Pos (17UL)
6334 #define ADC1_RES_OUT7_VF7_Msk (0x20000UL)
6335 #define ADC1_RES_OUT7_WFR7_Pos (16UL)
6336 #define ADC1_RES_OUT7_WFR7_Msk (0x10000UL)
6337 #define ADC1_RES_OUT7_OUT_CH7_Pos (0UL)
6338 #define ADC1_RES_OUT7_OUT_CH7_Msk (0xfffUL)
6339 /* ====================================================== RES_OUT_EIM ====================================================== */
6340 #define ADC1_RES_OUT_EIM_OF8_Pos (18UL)
6341 #define ADC1_RES_OUT_EIM_OF8_Msk (0x40000UL)
6342 #define ADC1_RES_OUT_EIM_VF8_Pos (17UL)
6343 #define ADC1_RES_OUT_EIM_VF8_Msk (0x20000UL)
6344 #define ADC1_RES_OUT_EIM_WFR8_Pos (16UL)
6345 #define ADC1_RES_OUT_EIM_WFR8_Msk (0x10000UL)
6346 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos (0UL)
6347 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk (0xfffUL)
6348 /* ========================================================= SQ1_4 ========================================================= */
6349 #define ADC1_SQ1_4_SQ4_Pos (24UL)
6350 #define ADC1_SQ1_4_SQ4_Msk (0xff000000UL)
6351 #define ADC1_SQ1_4_SQ3_Pos (16UL)
6352 #define ADC1_SQ1_4_SQ3_Msk (0xff0000UL)
6353 #define ADC1_SQ1_4_SQ2_Pos (8UL)
6354 #define ADC1_SQ1_4_SQ2_Msk (0xff00UL)
6355 #define ADC1_SQ1_4_SQ1_Pos (0UL)
6356 #define ADC1_SQ1_4_SQ1_Msk (0xffUL)
6357 /* ========================================================= SQ5_8 ========================================================= */
6358 #define ADC1_SQ5_8_SQ8_Pos (24UL)
6359 #define ADC1_SQ5_8_SQ8_Msk (0xff000000UL)
6360 #define ADC1_SQ5_8_SQ7_Pos (16UL)
6361 #define ADC1_SQ5_8_SQ7_Msk (0xff0000UL)
6362 #define ADC1_SQ5_8_SQ6_Pos (8UL)
6363 #define ADC1_SQ5_8_SQ6_Msk (0xff00UL)
6364 #define ADC1_SQ5_8_SQ5_Pos (0UL)
6365 #define ADC1_SQ5_8_SQ5_Msk (0xffUL)
6366 /* ========================================================= SQ_FB ========================================================= */
6367 #define ADC1_SQ_FB_CHx_Pos (16UL)
6368 #define ADC1_SQ_FB_CHx_Msk (0x70000UL)
6369 #define ADC1_SQ_FB_SQx_Pos (11UL)
6370 #define ADC1_SQ_FB_SQx_Msk (0x3800UL)
6371 #define ADC1_SQ_FB_ESM_ACTIVE_Pos (10UL)
6372 #define ADC1_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6373 #define ADC1_SQ_FB_EIM_ACTIVE_Pos (9UL)
6374 #define ADC1_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6375 #define ADC1_SQ_FB_SQ_RUN_Pos (8UL)
6376 #define ADC1_SQ_FB_SQ_RUN_Msk (0x100UL)
6377 /* ======================================================== STC_0_3 ======================================================== */
6378 #define ADC1_STC_0_3_ch3_Pos (24UL)
6379 #define ADC1_STC_0_3_ch3_Msk (0xff000000UL)
6380 #define ADC1_STC_0_3_ch2_Pos (16UL)
6381 #define ADC1_STC_0_3_ch2_Msk (0xff0000UL)
6382 #define ADC1_STC_0_3_ch1_Pos (8UL)
6383 #define ADC1_STC_0_3_ch1_Msk (0xff00UL)
6384 #define ADC1_STC_0_3_ch0_Pos (0UL)
6385 #define ADC1_STC_0_3_ch0_Msk (0xffUL)
6386 /* ======================================================== STC_4_7 ======================================================== */
6387 #define ADC1_STC_4_7_ch7_Pos (24UL)
6388 #define ADC1_STC_4_7_ch7_Msk (0xff000000UL)
6389 #define ADC1_STC_4_7_ch6_Pos (16UL)
6390 #define ADC1_STC_4_7_ch6_Msk (0xff0000UL)
6391 #define ADC1_STC_4_7_ch5_Pos (8UL)
6392 #define ADC1_STC_4_7_ch5_Msk (0xff00UL)
6393 #define ADC1_STC_4_7_ch4_Pos (0UL)
6394 #define ADC1_STC_4_7_ch4_Msk (0xffUL)
6397 /* =========================================================================================================================== */
6398 /* ================ ADC2 ================ */
6399 /* =========================================================================================================================== */
6400 
6401 /* ======================================================= CAL_CH0_1 ======================================================= */
6402 #define ADC2_CAL_CH0_1_GAIN_CH1_Pos (24UL)
6403 #define ADC2_CAL_CH0_1_GAIN_CH1_Msk (0xff000000UL)
6404 #define ADC2_CAL_CH0_1_OFFS_CH1_Pos (16UL)
6405 #define ADC2_CAL_CH0_1_OFFS_CH1_Msk (0xff0000UL)
6406 #define ADC2_CAL_CH0_1_GAIN_CH0_Pos (8UL)
6407 #define ADC2_CAL_CH0_1_GAIN_CH0_Msk (0xff00UL)
6408 #define ADC2_CAL_CH0_1_OFFS_CH0_Pos (0UL)
6409 #define ADC2_CAL_CH0_1_OFFS_CH0_Msk (0xffUL)
6410 /* ======================================================= CAL_CH2_3 ======================================================= */
6411 #define ADC2_CAL_CH2_3_GAIN_CH3_Pos (24UL)
6412 #define ADC2_CAL_CH2_3_GAIN_CH3_Msk (0xff000000UL)
6413 #define ADC2_CAL_CH2_3_OFFS_CH3_Pos (16UL)
6414 #define ADC2_CAL_CH2_3_OFFS_CH3_Msk (0xff0000UL)
6415 #define ADC2_CAL_CH2_3_GAIN_CH2_Pos (8UL)
6416 #define ADC2_CAL_CH2_3_GAIN_CH2_Msk (0xff00UL)
6417 #define ADC2_CAL_CH2_3_OFFS_CH2_Pos (0UL)
6418 #define ADC2_CAL_CH2_3_OFFS_CH2_Msk (0xffUL)
6419 /* ======================================================= CAL_CH4_5 ======================================================= */
6420 #define ADC2_CAL_CH4_5_GAIN_CH5_Pos (24UL)
6421 #define ADC2_CAL_CH4_5_GAIN_CH5_Msk (0xff000000UL)
6422 #define ADC2_CAL_CH4_5_OFFS_CH5_Pos (16UL)
6423 #define ADC2_CAL_CH4_5_OFFS_CH5_Msk (0xff0000UL)
6424 #define ADC2_CAL_CH4_5_GAIN_CH4_Pos (8UL)
6425 #define ADC2_CAL_CH4_5_GAIN_CH4_Msk (0xff00UL)
6426 #define ADC2_CAL_CH4_5_OFFS_CH4_Pos (0UL)
6427 #define ADC2_CAL_CH4_5_OFFS_CH4_Msk (0xffUL)
6428 /* ======================================================= CAL_CH6_7 ======================================================= */
6429 #define ADC2_CAL_CH6_7_GAIN_CH7_Pos (24UL)
6430 #define ADC2_CAL_CH6_7_GAIN_CH7_Msk (0xff000000UL)
6431 #define ADC2_CAL_CH6_7_OFFS_CH7_Pos (16UL)
6432 #define ADC2_CAL_CH6_7_OFFS_CH7_Msk (0xff0000UL)
6433 #define ADC2_CAL_CH6_7_GAIN_CH6_Pos (8UL)
6434 #define ADC2_CAL_CH6_7_GAIN_CH6_Msk (0xff00UL)
6435 #define ADC2_CAL_CH6_7_OFFS_CH6_Pos (0UL)
6436 #define ADC2_CAL_CH6_7_OFFS_CH6_Msk (0xffUL)
6437 /* ======================================================= CAL_CH8_9 ======================================================= */
6438 #define ADC2_CAL_CH8_9_GAIN_CH9_Pos (24UL)
6439 #define ADC2_CAL_CH8_9_GAIN_CH9_Msk (0xff000000UL)
6440 #define ADC2_CAL_CH8_9_OFFS_CH9_Pos (16UL)
6441 #define ADC2_CAL_CH8_9_OFFS_CH9_Msk (0xff0000UL)
6442 #define ADC2_CAL_CH8_9_GAIN_CH8_Pos (8UL)
6443 #define ADC2_CAL_CH8_9_GAIN_CH8_Msk (0xff00UL)
6444 #define ADC2_CAL_CH8_9_OFFS_CH8_Pos (0UL)
6445 #define ADC2_CAL_CH8_9_OFFS_CH8_Msk (0xffUL)
6446 /* ======================================================== CHx_EIM ======================================================== */
6447 #define ADC2_CHx_EIM_SEL_Pos (12UL)
6448 #define ADC2_CHx_EIM_SEL_Msk (0x1000UL)
6449 #define ADC2_CHx_EIM_EN_Pos (11UL)
6450 #define ADC2_CHx_EIM_EN_Msk (0x800UL)
6451 #define ADC2_CHx_EIM_REP_Pos (8UL)
6452 #define ADC2_CHx_EIM_REP_Msk (0x700UL)
6453 #define ADC2_CHx_EIM_CHx_Pos (0UL)
6454 #define ADC2_CHx_EIM_CHx_Msk (0x1fUL)
6455 /* ======================================================== CHx_ESM ======================================================== */
6456 #define ADC2_CHx_ESM_STS_Pos (17UL)
6457 #define ADC2_CHx_ESM_STS_Msk (0x20000UL)
6458 #define ADC2_CHx_ESM_EN_Pos (16UL)
6459 #define ADC2_CHx_ESM_EN_Msk (0x10000UL)
6460 #define ADC2_CHx_ESM_SEL_Pos (10UL)
6461 #define ADC2_CHx_ESM_SEL_Msk (0x400UL)
6462 #define ADC2_CHx_ESM_ESM_1_Pos (6UL)
6463 #define ADC2_CHx_ESM_ESM_1_Msk (0x3c0UL)
6464 #define ADC2_CHx_ESM_ESM_0_Pos (0UL)
6465 #define ADC2_CHx_ESM_ESM_0_Msk (0x3fUL)
6466 /* ===================================================== CNT0_3_LOWER ====================================================== */
6467 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Pos (27UL)
6468 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Msk (0x18000000UL)
6469 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Pos (24UL)
6470 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Msk (0x7000000UL)
6471 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Pos (19UL)
6472 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Msk (0x180000UL)
6473 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Pos (16UL)
6474 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Msk (0x70000UL)
6475 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Pos (11UL)
6476 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Msk (0x1800UL)
6477 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Pos (8UL)
6478 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Msk (0x700UL)
6479 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Pos (3UL)
6480 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Msk (0x18UL)
6481 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Pos (0UL)
6482 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Msk (0x7UL)
6483 /* ===================================================== CNT0_3_UPPER ====================================================== */
6484 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Pos (27UL)
6485 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Msk (0x18000000UL)
6486 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Pos (24UL)
6487 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Msk (0x7000000UL)
6488 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Pos (19UL)
6489 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Msk (0x180000UL)
6490 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Pos (16UL)
6491 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Msk (0x70000UL)
6492 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Pos (11UL)
6493 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Msk (0x1800UL)
6494 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Pos (8UL)
6495 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Msk (0x700UL)
6496 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Pos (3UL)
6497 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Msk (0x18UL)
6498 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Pos (0UL)
6499 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Msk (0x7UL)
6500 /* ===================================================== CNT4_5_LOWER ====================================================== */
6501 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Pos (11UL)
6502 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Msk (0x1800UL)
6503 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Pos (8UL)
6504 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Msk (0x700UL)
6505 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Pos (3UL)
6506 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Msk (0x18UL)
6507 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Pos (0UL)
6508 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Msk (0x7UL)
6509 /* ===================================================== CNT4_5_UPPER ====================================================== */
6510 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Pos (11UL)
6511 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Msk (0x1800UL)
6512 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Pos (8UL)
6513 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Msk (0x700UL)
6514 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Pos (3UL)
6515 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Msk (0x18UL)
6516 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Pos (0UL)
6517 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Msk (0x7UL)
6518 /* ===================================================== CNT6_9_LOWER ====================================================== */
6519 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Pos (27UL)
6520 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Msk (0x18000000UL)
6521 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Pos (24UL)
6522 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Msk (0x7000000UL)
6523 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Pos (19UL)
6524 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Msk (0x180000UL)
6525 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Pos (16UL)
6526 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Msk (0x70000UL)
6527 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Pos (11UL)
6528 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Msk (0x1800UL)
6529 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Pos (8UL)
6530 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Msk (0x700UL)
6531 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Pos (3UL)
6532 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Msk (0x18UL)
6533 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Pos (0UL)
6534 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Msk (0x7UL)
6535 /* ===================================================== CNT6_9_UPPER ====================================================== */
6536 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Pos (27UL)
6537 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Msk (0x18000000UL)
6538 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Pos (24UL)
6539 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Msk (0x7000000UL)
6540 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Pos (19UL)
6541 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Msk (0x180000UL)
6542 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Pos (16UL)
6543 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Msk (0x70000UL)
6544 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Pos (11UL)
6545 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Msk (0x1800UL)
6546 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Pos (8UL)
6547 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Msk (0x700UL)
6548 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Pos (3UL)
6549 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Msk (0x18UL)
6550 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Pos (0UL)
6551 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Msk (0x7UL)
6552 /* ========================================================= CTRL1 ========================================================= */
6553 #define ADC2_CTRL1_CALIB_EN_Pos (0UL)
6554 #define ADC2_CTRL1_CALIB_EN_Msk (0x3fUL)
6555 /* ========================================================= CTRL2 ========================================================= */
6556 #define ADC2_CTRL2_SEL_TS_COUNT_Pos (16UL)
6557 #define ADC2_CTRL2_SEL_TS_COUNT_Msk (0xf0000UL)
6558 #define ADC2_CTRL2_SAMPLE_TIME_int_Pos (8UL)
6559 #define ADC2_CTRL2_SAMPLE_TIME_int_Msk (0xf00UL)
6560 #define ADC2_CTRL2_MCM_RDY_Pos (7UL)
6561 #define ADC2_CTRL2_MCM_RDY_Msk (0x80UL)
6562 #define ADC2_CTRL2_TSENSE_SD_SEL_Pos (2UL)
6563 #define ADC2_CTRL2_TSENSE_SD_SEL_Msk (0x4UL)
6564 #define ADC2_CTRL2_TS_SD_SEL_CONF_Pos (1UL)
6565 #define ADC2_CTRL2_TS_SD_SEL_CONF_Msk (0x2UL)
6566 #define ADC2_CTRL2_MCM_PD_N_Pos (0UL)
6567 #define ADC2_CTRL2_MCM_PD_N_Msk (0x1UL)
6568 /* ========================================================= CTRL4 ========================================================= */
6569 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Pos (8UL)
6570 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Msk (0xf00UL)
6571 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Pos (0UL)
6572 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Msk (0x3fUL)
6573 /* ======================================================= CTRL_STS ======================================================== */
6574 #define ADC2_CTRL_STS_VS_RANGE_Pos (17UL)
6575 #define ADC2_CTRL_STS_VS_RANGE_Msk (0x20000UL)
6576 /* ===================================================== FILT_LO_CTRL ====================================================== */
6577 #define ADC2_FILT_LO_CTRL_Ch5_EN_Pos (5UL)
6578 #define ADC2_FILT_LO_CTRL_Ch5_EN_Msk (0x20UL)
6579 #define ADC2_FILT_LO_CTRL_Ch4_EN_Pos (4UL)
6580 #define ADC2_FILT_LO_CTRL_Ch4_EN_Msk (0x10UL)
6581 #define ADC2_FILT_LO_CTRL_Ch3_EN_Pos (3UL)
6582 #define ADC2_FILT_LO_CTRL_Ch3_EN_Msk (0x8UL)
6583 #define ADC2_FILT_LO_CTRL_Ch2_EN_Pos (2UL)
6584 #define ADC2_FILT_LO_CTRL_Ch2_EN_Msk (0x4UL)
6585 #define ADC2_FILT_LO_CTRL_Ch1_EN_Pos (1UL)
6586 #define ADC2_FILT_LO_CTRL_Ch1_EN_Msk (0x2UL)
6587 #define ADC2_FILT_LO_CTRL_Ch0_EN_Pos (0UL)
6588 #define ADC2_FILT_LO_CTRL_Ch0_EN_Msk (0x1UL)
6589 /* ======================================================= FILT_OUT0 ======================================================= */
6590 #define ADC2_FILT_OUT0_OUT_CH0_Pos (0UL)
6591 #define ADC2_FILT_OUT0_OUT_CH0_Msk (0x3ffUL)
6592 /* ======================================================= FILT_OUT1 ======================================================= */
6593 #define ADC2_FILT_OUT1_OUT_CH1_Pos (0UL)
6594 #define ADC2_FILT_OUT1_OUT_CH1_Msk (0x3ffUL)
6595 /* ======================================================= FILT_OUT2 ======================================================= */
6596 #define ADC2_FILT_OUT2_OUT_CH2_Pos (0UL)
6597 #define ADC2_FILT_OUT2_OUT_CH2_Msk (0x3ffUL)
6598 /* ======================================================= FILT_OUT3 ======================================================= */
6599 #define ADC2_FILT_OUT3_OUT_CH3_Pos (0UL)
6600 #define ADC2_FILT_OUT3_OUT_CH3_Msk (0x3ffUL)
6601 /* ======================================================= FILT_OUT4 ======================================================= */
6602 #define ADC2_FILT_OUT4_OUT_CH4_Pos (0UL)
6603 #define ADC2_FILT_OUT4_OUT_CH4_Msk (0x3ffUL)
6604 /* ======================================================= FILT_OUT5 ======================================================= */
6605 #define ADC2_FILT_OUT5_OUT_CH5_Pos (0UL)
6606 #define ADC2_FILT_OUT5_OUT_CH5_Msk (0x3ffUL)
6607 /* ======================================================= FILT_OUT6 ======================================================= */
6608 #define ADC2_FILT_OUT6_OUT_CH6_Pos (0UL)
6609 #define ADC2_FILT_OUT6_OUT_CH6_Msk (0x3ffUL)
6610 /* ======================================================= FILT_OUT7 ======================================================= */
6611 #define ADC2_FILT_OUT7_OUT_CH7_Pos (0UL)
6612 #define ADC2_FILT_OUT7_OUT_CH7_Msk (0x3ffUL)
6613 /* ======================================================= FILT_OUT8 ======================================================= */
6614 #define ADC2_FILT_OUT8_OUT_CH8_Pos (0UL)
6615 #define ADC2_FILT_OUT8_OUT_CH8_Msk (0x3ffUL)
6616 /* ======================================================= FILT_OUT9 ======================================================= */
6617 #define ADC2_FILT_OUT9_OUT_CH9_Pos (0UL)
6618 #define ADC2_FILT_OUT9_OUT_CH9_Msk (0x3ffUL)
6619 /* ===================================================== FILT_UP_CTRL ====================================================== */
6620 #define ADC2_FILT_UP_CTRL_Ch5_EN_Pos (5UL)
6621 #define ADC2_FILT_UP_CTRL_Ch5_EN_Msk (0x20UL)
6622 #define ADC2_FILT_UP_CTRL_Ch4_EN_Pos (4UL)
6623 #define ADC2_FILT_UP_CTRL_Ch4_EN_Msk (0x10UL)
6624 #define ADC2_FILT_UP_CTRL_Ch3_EN_Pos (3UL)
6625 #define ADC2_FILT_UP_CTRL_Ch3_EN_Msk (0x8UL)
6626 #define ADC2_FILT_UP_CTRL_Ch2_EN_Pos (2UL)
6627 #define ADC2_FILT_UP_CTRL_Ch2_EN_Msk (0x4UL)
6628 #define ADC2_FILT_UP_CTRL_Ch1_EN_Pos (1UL)
6629 #define ADC2_FILT_UP_CTRL_Ch1_EN_Msk (0x2UL)
6630 #define ADC2_FILT_UP_CTRL_Ch0_EN_Pos (0UL)
6631 #define ADC2_FILT_UP_CTRL_Ch0_EN_Msk (0x1UL)
6632 /* ===================================================== FILTCOEFF0_5 ====================================================== */
6633 #define ADC2_FILTCOEFF0_5_CH5_Pos (10UL)
6634 #define ADC2_FILTCOEFF0_5_CH5_Msk (0xc00UL)
6635 #define ADC2_FILTCOEFF0_5_CH4_Pos (8UL)
6636 #define ADC2_FILTCOEFF0_5_CH4_Msk (0x300UL)
6637 #define ADC2_FILTCOEFF0_5_CH3_Pos (6UL)
6638 #define ADC2_FILTCOEFF0_5_CH3_Msk (0xc0UL)
6639 #define ADC2_FILTCOEFF0_5_CH2_Pos (4UL)
6640 #define ADC2_FILTCOEFF0_5_CH2_Msk (0x30UL)
6641 #define ADC2_FILTCOEFF0_5_CH1_Pos (2UL)
6642 #define ADC2_FILTCOEFF0_5_CH1_Msk (0xcUL)
6643 #define ADC2_FILTCOEFF0_5_CH0_Pos (0UL)
6644 #define ADC2_FILTCOEFF0_5_CH0_Msk (0x3UL)
6645 /* ===================================================== FILTCOEFF6_9 ====================================================== */
6646 #define ADC2_FILTCOEFF6_9_CH9_Pos (6UL)
6647 #define ADC2_FILTCOEFF6_9_CH9_Msk (0xc0UL)
6648 #define ADC2_FILTCOEFF6_9_CH8_Pos (4UL)
6649 #define ADC2_FILTCOEFF6_9_CH8_Msk (0x30UL)
6650 #define ADC2_FILTCOEFF6_9_CH7_Pos (2UL)
6651 #define ADC2_FILTCOEFF6_9_CH7_Msk (0xcUL)
6652 #define ADC2_FILTCOEFF6_9_CH6_Pos (0UL)
6653 #define ADC2_FILTCOEFF6_9_CH6_Msk (0x3UL)
6654 /* ======================================================== HV_STS ========================================================= */
6655 #define ADC2_HV_STS_READY_Pos (1UL)
6656 #define ADC2_HV_STS_READY_Msk (0x2UL)
6657 /* ======================================================= MMODE0_5 ======================================================== */
6658 #define ADC2_MMODE0_5_Ch5_Pos (10UL)
6659 #define ADC2_MMODE0_5_Ch5_Msk (0xc00UL)
6660 #define ADC2_MMODE0_5_Ch4_Pos (8UL)
6661 #define ADC2_MMODE0_5_Ch4_Msk (0x300UL)
6662 #define ADC2_MMODE0_5_Ch3_Pos (6UL)
6663 #define ADC2_MMODE0_5_Ch3_Msk (0xc0UL)
6664 #define ADC2_MMODE0_5_Ch2_Pos (4UL)
6665 #define ADC2_MMODE0_5_Ch2_Msk (0x30UL)
6666 #define ADC2_MMODE0_5_Ch1_Pos (2UL)
6667 #define ADC2_MMODE0_5_Ch1_Msk (0xcUL)
6668 #define ADC2_MMODE0_5_Ch0_Pos (0UL)
6669 #define ADC2_MMODE0_5_Ch0_Msk (0x3UL)
6670 /* ========================================================= SQ1_4 ========================================================= */
6671 #define ADC2_SQ1_4_SQ4_Pos (24UL)
6672 #define ADC2_SQ1_4_SQ4_Msk (0x3f000000UL)
6673 #define ADC2_SQ1_4_SQ3_Pos (16UL)
6674 #define ADC2_SQ1_4_SQ3_Msk (0x3f0000UL)
6675 #define ADC2_SQ1_4_SQ2_Pos (8UL)
6676 #define ADC2_SQ1_4_SQ2_Msk (0x3f00UL)
6677 #define ADC2_SQ1_4_SQ1_Pos (0UL)
6678 #define ADC2_SQ1_4_SQ1_Msk (0x3fUL)
6679 /* ======================================================= SQ1_8_int ======================================================= */
6680 #define ADC2_SQ1_8_int_SQ8_int_Pos (28UL)
6681 #define ADC2_SQ1_8_int_SQ8_int_Msk (0xf0000000UL)
6682 #define ADC2_SQ1_8_int_SQ7_int_Pos (24UL)
6683 #define ADC2_SQ1_8_int_SQ7_int_Msk (0xf000000UL)
6684 #define ADC2_SQ1_8_int_SQ6_int_Pos (20UL)
6685 #define ADC2_SQ1_8_int_SQ6_int_Msk (0xf00000UL)
6686 #define ADC2_SQ1_8_int_SQ5_int_Pos (16UL)
6687 #define ADC2_SQ1_8_int_SQ5_int_Msk (0xf0000UL)
6688 #define ADC2_SQ1_8_int_SQ4_int_Pos (12UL)
6689 #define ADC2_SQ1_8_int_SQ4_int_Msk (0xf000UL)
6690 #define ADC2_SQ1_8_int_SQ3_int_Pos (8UL)
6691 #define ADC2_SQ1_8_int_SQ3_int_Msk (0xf00UL)
6692 #define ADC2_SQ1_8_int_SQ2_int_Pos (4UL)
6693 #define ADC2_SQ1_8_int_SQ2_int_Msk (0xf0UL)
6694 #define ADC2_SQ1_8_int_SQ1_int_Pos (0UL)
6695 #define ADC2_SQ1_8_int_SQ1_int_Msk (0xfUL)
6696 /* ========================================================= SQ5_8 ========================================================= */
6697 #define ADC2_SQ5_8_SQ8_Pos (24UL)
6698 #define ADC2_SQ5_8_SQ8_Msk (0x3f000000UL)
6699 #define ADC2_SQ5_8_SQ7_Pos (16UL)
6700 #define ADC2_SQ5_8_SQ7_Msk (0x3f0000UL)
6701 #define ADC2_SQ5_8_SQ6_Pos (8UL)
6702 #define ADC2_SQ5_8_SQ6_Msk (0x3f00UL)
6703 #define ADC2_SQ5_8_SQ5_Pos (0UL)
6704 #define ADC2_SQ5_8_SQ5_Msk (0x3fUL)
6705 /* ======================================================== SQ9_10 ========================================================= */
6706 #define ADC2_SQ9_10_SQ10_Pos (8UL)
6707 #define ADC2_SQ9_10_SQ10_Msk (0x3f00UL)
6708 #define ADC2_SQ9_10_SQ9_Pos (0UL)
6709 #define ADC2_SQ9_10_SQ9_Msk (0x3fUL)
6710 /* ====================================================== SQ9_10_int ======================================================= */
6711 #define ADC2_SQ9_10_int_SQ10_int_Pos (4UL)
6712 #define ADC2_SQ9_10_int_SQ10_int_Msk (0xf0UL)
6713 #define ADC2_SQ9_10_int_SQ9_int_Pos (0UL)
6714 #define ADC2_SQ9_10_int_SQ9_int_Msk (0xfUL)
6715 /* ========================================================= SQ_FB ========================================================= */
6716 #define ADC2_SQ_FB_CHx_Pos (16UL)
6717 #define ADC2_SQ_FB_CHx_Msk (0x1f0000UL)
6718 #define ADC2_SQ_FB_SQx_Pos (11UL)
6719 #define ADC2_SQ_FB_SQx_Msk (0x7800UL)
6720 #define ADC2_SQ_FB_ESM_ACTIVE_Pos (10UL)
6721 #define ADC2_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6722 #define ADC2_SQ_FB_EIM_ACTIVE_Pos (9UL)
6723 #define ADC2_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6724 #define ADC2_SQ_FB_SQ_STOP_Pos (8UL)
6725 #define ADC2_SQ_FB_SQ_STOP_Msk (0x100UL)
6726 #define ADC2_SQ_FB_SQ_FB_Pos (0UL)
6727 #define ADC2_SQ_FB_SQ_FB_Msk (0xfUL)
6728 /* ====================================================== TH0_3_LOWER ====================================================== */
6729 #define ADC2_TH0_3_LOWER_CH3_Pos (24UL)
6730 #define ADC2_TH0_3_LOWER_CH3_Msk (0xff000000UL)
6731 #define ADC2_TH0_3_LOWER_CH2_Pos (16UL)
6732 #define ADC2_TH0_3_LOWER_CH2_Msk (0xff0000UL)
6733 #define ADC2_TH0_3_LOWER_CH1_Pos (8UL)
6734 #define ADC2_TH0_3_LOWER_CH1_Msk (0xff00UL)
6735 #define ADC2_TH0_3_LOWER_CH0_Pos (0UL)
6736 #define ADC2_TH0_3_LOWER_CH0_Msk (0xffUL)
6737 /* ====================================================== TH0_3_UPPER ====================================================== */
6738 #define ADC2_TH0_3_UPPER_CH3_Pos (24UL)
6739 #define ADC2_TH0_3_UPPER_CH3_Msk (0xff000000UL)
6740 #define ADC2_TH0_3_UPPER_CH2_Pos (16UL)
6741 #define ADC2_TH0_3_UPPER_CH2_Msk (0xff0000UL)
6742 #define ADC2_TH0_3_UPPER_CH1_Pos (8UL)
6743 #define ADC2_TH0_3_UPPER_CH1_Msk (0xff00UL)
6744 #define ADC2_TH0_3_UPPER_CH0_Pos (0UL)
6745 #define ADC2_TH0_3_UPPER_CH0_Msk (0xffUL)
6746 /* ====================================================== TH4_5_LOWER ====================================================== */
6747 #define ADC2_TH4_5_LOWER_CH5_Pos (8UL)
6748 #define ADC2_TH4_5_LOWER_CH5_Msk (0xff00UL)
6749 #define ADC2_TH4_5_LOWER_CH4_Pos (0UL)
6750 #define ADC2_TH4_5_LOWER_CH4_Msk (0xffUL)
6751 /* ====================================================== TH4_5_UPPER ====================================================== */
6752 #define ADC2_TH4_5_UPPER_CH5_Pos (8UL)
6753 #define ADC2_TH4_5_UPPER_CH5_Msk (0xff00UL)
6754 #define ADC2_TH4_5_UPPER_CH4_Pos (0UL)
6755 #define ADC2_TH4_5_UPPER_CH4_Msk (0xffUL)
6756 /* ====================================================== TH6_9_LOWER ====================================================== */
6757 #define ADC2_TH6_9_LOWER_CH9_Pos (24UL)
6758 #define ADC2_TH6_9_LOWER_CH9_Msk (0xff000000UL)
6759 #define ADC2_TH6_9_LOWER_CH8_Pos (16UL)
6760 #define ADC2_TH6_9_LOWER_CH8_Msk (0xff0000UL)
6761 #define ADC2_TH6_9_LOWER_CH7_Pos (8UL)
6762 #define ADC2_TH6_9_LOWER_CH7_Msk (0xff00UL)
6763 #define ADC2_TH6_9_LOWER_CH6_Pos (0UL)
6764 #define ADC2_TH6_9_LOWER_CH6_Msk (0xffUL)
6765 /* ====================================================== TH6_9_UPPER ====================================================== */
6766 #define ADC2_TH6_9_UPPER_CH9_Pos (24UL)
6767 #define ADC2_TH6_9_UPPER_CH9_Msk (0xff000000UL)
6768 #define ADC2_TH6_9_UPPER_CH8_Pos (16UL)
6769 #define ADC2_TH6_9_UPPER_CH8_Msk (0xff0000UL)
6770 #define ADC2_TH6_9_UPPER_CH7_Pos (8UL)
6771 #define ADC2_TH6_9_UPPER_CH7_Msk (0xff00UL)
6772 #define ADC2_TH6_9_UPPER_CH6_Pos (0UL)
6773 #define ADC2_TH6_9_UPPER_CH6_Msk (0xffUL)
6776 /* =========================================================================================================================== */
6777 /* ================ ADC34 ================ */
6778 /* =========================================================================================================================== */
6779 
6780 /* ======================================================= CTRL_STS ======================================================== */
6781 #define ADC34_CTRL_STS_ADC4_OSR_Pos (28UL)
6782 #define ADC34_CTRL_STS_ADC4_OSR_Msk (0xf0000000UL)
6783 #define ADC34_CTRL_STS_ADC34_DITHVAL_Pos (24UL)
6784 #define ADC34_CTRL_STS_ADC34_DITHVAL_Msk (0xf000000UL)
6785 #define ADC34_CTRL_STS_ADC34_DITHEN_Pos (23UL)
6786 #define ADC34_CTRL_STS_ADC34_DITHEN_Msk (0x800000UL)
6787 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Pos (21UL)
6788 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Msk (0x600000UL)
6789 #define ADC34_CTRL_STS_ADC4_EoC_STS_Pos (20UL)
6790 #define ADC34_CTRL_STS_ADC4_EoC_STS_Msk (0x100000UL)
6791 #define ADC34_CTRL_STS_ADC4_SOC_Pos (18UL)
6792 #define ADC34_CTRL_STS_ADC4_SOC_Msk (0x40000UL)
6793 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Pos (17UL)
6794 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Msk (0x20000UL)
6795 #define ADC34_CTRL_STS_ADC4_EN_Pos (16UL)
6796 #define ADC34_CTRL_STS_ADC4_EN_Msk (0x10000UL)
6797 #define ADC34_CTRL_STS_ADC3_OSR_Pos (12UL)
6798 #define ADC34_CTRL_STS_ADC3_OSR_Msk (0xf000UL)
6799 #define ADC34_CTRL_STS_ADC34_REF_SEL_Pos (11UL)
6800 #define ADC34_CTRL_STS_ADC34_REF_SEL_Msk (0x800UL)
6801 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Pos (5UL)
6802 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Msk (0x60UL)
6803 #define ADC34_CTRL_STS_ADC3_EoC_STS_Pos (4UL)
6804 #define ADC34_CTRL_STS_ADC3_EoC_STS_Msk (0x10UL)
6805 #define ADC34_CTRL_STS_ADC3_SOC_Pos (2UL)
6806 #define ADC34_CTRL_STS_ADC3_SOC_Msk (0x4UL)
6807 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Pos (1UL)
6808 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Msk (0x2UL)
6809 #define ADC34_CTRL_STS_ADC3_EN_Pos (0UL)
6810 #define ADC34_CTRL_STS_ADC3_EN_Msk (0x1UL)
6811 /* ========================================================= RESU ========================================================== */
6812 #define ADC34_RESU_ADC4_RESU_Pos (16UL)
6813 #define ADC34_RESU_ADC4_RESU_Msk (0xffff0000UL)
6814 #define ADC34_RESU_ADC3_RESU_Pos (0UL)
6815 #define ADC34_RESU_ADC3_RESU_Msk (0xffffUL)
6818 /* =========================================================================================================================== */
6819 /* ================ BDRV ================ */
6820 /* =========================================================================================================================== */
6821 
6822 /* ====================================================== CP_CLK_CTRL ====================================================== */
6823 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Pos (15UL)
6824 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Msk (0x8000UL)
6825 #define BDRV_CP_CLK_CTRL_F_CP_Pos (13UL)
6826 #define BDRV_CP_CLK_CTRL_F_CP_Msk (0x6000UL)
6827 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Pos (8UL)
6828 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Msk (0x1f00UL)
6829 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Pos (0UL)
6830 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Msk (0x1fUL)
6831 /* ====================================================== CP_CTRL_STS ====================================================== */
6832 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Pos (26UL)
6833 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Msk (0xc000000UL)
6834 #define BDRV_CP_CTRL_STS_VCP9V_SET_Pos (25UL)
6835 #define BDRV_CP_CTRL_STS_VCP9V_SET_Msk (0x2000000UL)
6836 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Pos (24UL)
6837 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Msk (0x1000000UL)
6838 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Pos (23UL)
6839 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Msk (0x800000UL)
6840 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Pos (22UL)
6841 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Msk (0x400000UL)
6842 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Pos (21UL)
6843 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Msk (0x200000UL)
6844 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Pos (20UL)
6845 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Msk (0x100000UL)
6846 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Pos (19UL)
6847 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Msk (0x80000UL)
6848 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Pos (18UL)
6849 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Msk (0x40000UL)
6850 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Pos (17UL)
6851 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Msk (0x20000UL)
6852 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Pos (16UL)
6853 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Msk (0x10000UL)
6854 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Pos (8UL)
6855 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Msk (0x700UL)
6856 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Pos (5UL)
6857 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Msk (0x20UL)
6858 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Pos (2UL)
6859 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Msk (0x4UL)
6860 #define BDRV_CP_CTRL_STS_CP_EN_Pos (0UL)
6861 #define BDRV_CP_CTRL_STS_CP_EN_Msk (0x1UL)
6862 /* ========================================================= CTRL1 ========================================================= */
6863 #define BDRV_CTRL1_HS2_OC_DIS_Pos (31UL)
6864 #define BDRV_CTRL1_HS2_OC_DIS_Msk (0x80000000UL)
6865 #define BDRV_CTRL1_HS2_OC_STS_Pos (30UL)
6866 #define BDRV_CTRL1_HS2_OC_STS_Msk (0x40000000UL)
6867 #define BDRV_CTRL1_HS2_SUPERR_STS_Pos (29UL)
6868 #define BDRV_CTRL1_HS2_SUPERR_STS_Msk (0x20000000UL)
6869 #define BDRV_CTRL1_HS2_DS_STS_Pos (28UL)
6870 #define BDRV_CTRL1_HS2_DS_STS_Msk (0x10000000UL)
6871 #define BDRV_CTRL1_HS2_DCS_EN_Pos (27UL)
6872 #define BDRV_CTRL1_HS2_DCS_EN_Msk (0x8000000UL)
6873 #define BDRV_CTRL1_HS2_ON_Pos (26UL)
6874 #define BDRV_CTRL1_HS2_ON_Msk (0x4000000UL)
6875 #define BDRV_CTRL1_HS2_PWM_Pos (25UL)
6876 #define BDRV_CTRL1_HS2_PWM_Msk (0x2000000UL)
6877 #define BDRV_CTRL1_HS2_EN_Pos (24UL)
6878 #define BDRV_CTRL1_HS2_EN_Msk (0x1000000UL)
6879 #define BDRV_CTRL1_HS1_OC_DIS_Pos (23UL)
6880 #define BDRV_CTRL1_HS1_OC_DIS_Msk (0x800000UL)
6881 #define BDRV_CTRL1_HS1_OC_STS_Pos (22UL)
6882 #define BDRV_CTRL1_HS1_OC_STS_Msk (0x400000UL)
6883 #define BDRV_CTRL1_HS1_SUPERR_STS_Pos (21UL)
6884 #define BDRV_CTRL1_HS1_SUPERR_STS_Msk (0x200000UL)
6885 #define BDRV_CTRL1_HS1_DS_STS_Pos (20UL)
6886 #define BDRV_CTRL1_HS1_DS_STS_Msk (0x100000UL)
6887 #define BDRV_CTRL1_HS1_DCS_EN_Pos (19UL)
6888 #define BDRV_CTRL1_HS1_DCS_EN_Msk (0x80000UL)
6889 #define BDRV_CTRL1_HS1_ON_Pos (18UL)
6890 #define BDRV_CTRL1_HS1_ON_Msk (0x40000UL)
6891 #define BDRV_CTRL1_HS1_PWM_Pos (17UL)
6892 #define BDRV_CTRL1_HS1_PWM_Msk (0x20000UL)
6893 #define BDRV_CTRL1_HS1_EN_Pos (16UL)
6894 #define BDRV_CTRL1_HS1_EN_Msk (0x10000UL)
6895 #define BDRV_CTRL1_LS2_OC_DIS_Pos (15UL)
6896 #define BDRV_CTRL1_LS2_OC_DIS_Msk (0x8000UL)
6897 #define BDRV_CTRL1_LS2_OC_STS_Pos (14UL)
6898 #define BDRV_CTRL1_LS2_OC_STS_Msk (0x4000UL)
6899 #define BDRV_CTRL1_LS2_SUPERR_STS_Pos (13UL)
6900 #define BDRV_CTRL1_LS2_SUPERR_STS_Msk (0x2000UL)
6901 #define BDRV_CTRL1_LS2_DS_STS_Pos (12UL)
6902 #define BDRV_CTRL1_LS2_DS_STS_Msk (0x1000UL)
6903 #define BDRV_CTRL1_LS2_DCS_EN_Pos (11UL)
6904 #define BDRV_CTRL1_LS2_DCS_EN_Msk (0x800UL)
6905 #define BDRV_CTRL1_LS2_ON_Pos (10UL)
6906 #define BDRV_CTRL1_LS2_ON_Msk (0x400UL)
6907 #define BDRV_CTRL1_LS2_PWM_Pos (9UL)
6908 #define BDRV_CTRL1_LS2_PWM_Msk (0x200UL)
6909 #define BDRV_CTRL1_LS2_EN_Pos (8UL)
6910 #define BDRV_CTRL1_LS2_EN_Msk (0x100UL)
6911 #define BDRV_CTRL1_LS1_OC_DIS_Pos (7UL)
6912 #define BDRV_CTRL1_LS1_OC_DIS_Msk (0x80UL)
6913 #define BDRV_CTRL1_LS1_OC_STS_Pos (6UL)
6914 #define BDRV_CTRL1_LS1_OC_STS_Msk (0x40UL)
6915 #define BDRV_CTRL1_LS1_SUPERR_STS_Pos (5UL)
6916 #define BDRV_CTRL1_LS1_SUPERR_STS_Msk (0x20UL)
6917 #define BDRV_CTRL1_LS1_DS_STS_Pos (4UL)
6918 #define BDRV_CTRL1_LS1_DS_STS_Msk (0x10UL)
6919 #define BDRV_CTRL1_LS1_DCS_EN_Pos (3UL)
6920 #define BDRV_CTRL1_LS1_DCS_EN_Msk (0x8UL)
6921 #define BDRV_CTRL1_LS1_ON_Pos (2UL)
6922 #define BDRV_CTRL1_LS1_ON_Msk (0x4UL)
6923 #define BDRV_CTRL1_LS1_PWM_Pos (1UL)
6924 #define BDRV_CTRL1_LS1_PWM_Msk (0x2UL)
6925 #define BDRV_CTRL1_LS1_EN_Pos (0UL)
6926 #define BDRV_CTRL1_LS1_EN_Msk (0x1UL)
6927 /* ========================================================= CTRL2 ========================================================= */
6928 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Pos (31UL)
6929 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Msk (0x80000000UL)
6930 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Pos (28UL)
6931 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Msk (0x70000000UL)
6932 #define BDRV_CTRL2_DLY_DIAG_STS_Pos (27UL)
6933 #define BDRV_CTRL2_DLY_DIAG_STS_Msk (0x8000000UL)
6934 #define BDRV_CTRL2_DLY_DIAG_SCLR_Pos (26UL)
6935 #define BDRV_CTRL2_DLY_DIAG_SCLR_Msk (0x4000000UL)
6936 #define BDRV_CTRL2_DLY_DIAG_TIM_Pos (16UL)
6937 #define BDRV_CTRL2_DLY_DIAG_TIM_Msk (0x3ff0000UL)
6938 #define BDRV_CTRL2_HS3_OC_DIS_Pos (15UL)
6939 #define BDRV_CTRL2_HS3_OC_DIS_Msk (0x8000UL)
6940 #define BDRV_CTRL2_HS3_OC_STS_Pos (14UL)
6941 #define BDRV_CTRL2_HS3_OC_STS_Msk (0x4000UL)
6942 #define BDRV_CTRL2_HS3_SUPERR_STS_Pos (13UL)
6943 #define BDRV_CTRL2_HS3_SUPERR_STS_Msk (0x2000UL)
6944 #define BDRV_CTRL2_HS3_DS_STS_Pos (12UL)
6945 #define BDRV_CTRL2_HS3_DS_STS_Msk (0x1000UL)
6946 #define BDRV_CTRL2_HS3_DCS_EN_Pos (11UL)
6947 #define BDRV_CTRL2_HS3_DCS_EN_Msk (0x800UL)
6948 #define BDRV_CTRL2_HS3_ON_Pos (10UL)
6949 #define BDRV_CTRL2_HS3_ON_Msk (0x400UL)
6950 #define BDRV_CTRL2_HS3_PWM_Pos (9UL)
6951 #define BDRV_CTRL2_HS3_PWM_Msk (0x200UL)
6952 #define BDRV_CTRL2_HS3_EN_Pos (8UL)
6953 #define BDRV_CTRL2_HS3_EN_Msk (0x100UL)
6954 #define BDRV_CTRL2_LS3_OC_DIS_Pos (7UL)
6955 #define BDRV_CTRL2_LS3_OC_DIS_Msk (0x80UL)
6956 #define BDRV_CTRL2_LS3_OC_STS_Pos (6UL)
6957 #define BDRV_CTRL2_LS3_OC_STS_Msk (0x40UL)
6958 #define BDRV_CTRL2_LS3_SUPERR_STS_Pos (5UL)
6959 #define BDRV_CTRL2_LS3_SUPERR_STS_Msk (0x20UL)
6960 #define BDRV_CTRL2_LS3_DS_STS_Pos (4UL)
6961 #define BDRV_CTRL2_LS3_DS_STS_Msk (0x10UL)
6962 #define BDRV_CTRL2_LS3_DCS_EN_Pos (3UL)
6963 #define BDRV_CTRL2_LS3_DCS_EN_Msk (0x8UL)
6964 #define BDRV_CTRL2_LS3_ON_Pos (2UL)
6965 #define BDRV_CTRL2_LS3_ON_Msk (0x4UL)
6966 #define BDRV_CTRL2_LS3_PWM_Pos (1UL)
6967 #define BDRV_CTRL2_LS3_PWM_Msk (0x2UL)
6968 #define BDRV_CTRL2_LS3_EN_Pos (0UL)
6969 #define BDRV_CTRL2_LS3_EN_Msk (0x1UL)
6970 /* ========================================================= CTRL3 ========================================================= */
6971 #define BDRV_CTRL3_DRV_CCP_DIS_Pos (26UL)
6972 #define BDRV_CTRL3_DRV_CCP_DIS_Msk (0x4000000UL)
6973 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Pos (24UL)
6974 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Msk (0x3000000UL)
6975 #define BDRV_CTRL3_DSMONVTH_Pos (16UL)
6976 #define BDRV_CTRL3_DSMONVTH_Msk (0x70000UL)
6977 #define BDRV_CTRL3_OFF_SEQ_EN_Pos (15UL)
6978 #define BDRV_CTRL3_OFF_SEQ_EN_Msk (0x8000UL)
6979 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Pos (14UL)
6980 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Msk (0x4000UL)
6981 #define BDRV_CTRL3_IDISCHARGE_TRIM_Pos (8UL)
6982 #define BDRV_CTRL3_IDISCHARGE_TRIM_Msk (0x1f00UL)
6983 #define BDRV_CTRL3_ON_SEQ_EN_Pos (7UL)
6984 #define BDRV_CTRL3_ON_SEQ_EN_Msk (0x80UL)
6985 #define BDRV_CTRL3_ICHARGEDIV2_N_Pos (6UL)
6986 #define BDRV_CTRL3_ICHARGEDIV2_N_Msk (0x40UL)
6987 #define BDRV_CTRL3_ICHARGE_TRIM_Pos (0UL)
6988 #define BDRV_CTRL3_ICHARGE_TRIM_Msk (0x1fUL)
6989 /* ===================================================== OFF_SEQ_CTRL ====================================================== */
6990 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Pos (27UL)
6991 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Msk (0xf8000000UL)
6992 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Pos (24UL)
6993 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Msk (0x7000000UL)
6994 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Pos (19UL)
6995 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Msk (0xf80000UL)
6996 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Pos (16UL)
6997 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Msk (0x70000UL)
6998 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Pos (11UL)
6999 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Msk (0xf800UL)
7000 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Pos (8UL)
7001 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Msk (0x700UL)
7002 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Pos (3UL)
7003 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Msk (0xf8UL)
7004 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Pos (0UL)
7005 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Msk (0x7UL)
7006 /* ====================================================== ON_SEQ_CTRL ====================================================== */
7007 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Pos (27UL)
7008 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Msk (0xf8000000UL)
7009 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Pos (24UL)
7010 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Msk (0x7000000UL)
7011 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Pos (19UL)
7012 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Msk (0xf80000UL)
7013 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Pos (16UL)
7014 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Msk (0x70000UL)
7015 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Pos (11UL)
7016 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Msk (0xf800UL)
7017 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Pos (8UL)
7018 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Msk (0x700UL)
7019 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Pos (3UL)
7020 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Msk (0xf8UL)
7021 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Pos (0UL)
7022 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Msk (0x7UL)
7023 /* ======================================================= TRIM_DRVx ======================================================= */
7024 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Pos (24UL)
7025 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Msk (0x3000000UL)
7026 #define BDRV_TRIM_DRVx_HS3DRV_OCSDN_DIS_Pos (23UL)
7027 #define BDRV_TRIM_DRVx_HS3DRV_OCSDN_DIS_Msk (0x800000UL)
7028 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Pos (22UL)
7029 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Msk (0x400000UL)
7030 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Pos (21UL)
7031 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Msk (0x200000UL)
7032 #define BDRV_TRIM_DRVx_HS3DRV_FDISCHG_DIS_Pos (20UL)
7033 #define BDRV_TRIM_DRVx_HS3DRV_FDISCHG_DIS_Msk (0x100000UL)
7034 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Pos (19UL)
7035 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Msk (0x80000UL)
7036 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Pos (18UL)
7037 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Msk (0x40000UL)
7038 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Pos (16UL)
7039 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Msk (0x30000UL)
7040 #define BDRV_TRIM_DRVx_LS3DRV_OCSDN_DIS_Pos (15UL)
7041 #define BDRV_TRIM_DRVx_LS3DRV_OCSDN_DIS_Msk (0x8000UL)
7042 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Pos (14UL)
7043 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Msk (0x4000UL)
7044 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Pos (13UL)
7045 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Msk (0x2000UL)
7046 #define BDRV_TRIM_DRVx_LS3DRV_FDISCHG_DIS_Pos (12UL)
7047 #define BDRV_TRIM_DRVx_LS3DRV_FDISCHG_DIS_Msk (0x1000UL)
7048 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Pos (11UL)
7049 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Msk (0x800UL)
7050 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Pos (10UL)
7051 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Msk (0x400UL)
7052 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Pos (8UL)
7053 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Msk (0x300UL)
7054 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Pos (5UL)
7055 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Msk (0x60UL)
7056 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Pos (0UL)
7057 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Msk (0x3UL)
7060 /* =========================================================================================================================== */
7061 /* ================ CCU6 ================ */
7062 /* =========================================================================================================================== */
7063 
7064 /* ========================================================= CC60R ========================================================= */
7065 #define CCU6_CC60R_CCV_Pos (0UL)
7066 #define CCU6_CC60R_CCV_Msk (0xffffUL)
7067 /* ======================================================== CC60SR ========================================================= */
7068 #define CCU6_CC60SR_CCS_Pos (0UL)
7069 #define CCU6_CC60SR_CCS_Msk (0xffffUL)
7070 /* ========================================================= CC61R ========================================================= */
7071 #define CCU6_CC61R_CCV_Pos (0UL)
7072 #define CCU6_CC61R_CCV_Msk (0xffffUL)
7073 /* ======================================================== CC61SR ========================================================= */
7074 #define CCU6_CC61SR_CCS_Pos (0UL)
7075 #define CCU6_CC61SR_CCS_Msk (0xffffUL)
7076 /* ========================================================= CC62R ========================================================= */
7077 #define CCU6_CC62R_CCV_Pos (0UL)
7078 #define CCU6_CC62R_CCV_Msk (0xffffUL)
7079 /* ======================================================== CC62SR ========================================================= */
7080 #define CCU6_CC62SR_CCS_Pos (0UL)
7081 #define CCU6_CC62SR_CCS_Msk (0xffffUL)
7082 /* ========================================================= CC63R ========================================================= */
7083 #define CCU6_CC63R_CCV_Pos (0UL)
7084 #define CCU6_CC63R_CCV_Msk (0xffffUL)
7085 /* ======================================================== CC63SR ========================================================= */
7086 #define CCU6_CC63SR_CCS_Pos (0UL)
7087 #define CCU6_CC63SR_CCS_Msk (0xffffUL)
7088 /* ======================================================= CMPMODIF ======================================================== */
7089 #define CCU6_CMPMODIF_MCC60S_Pos (0UL)
7090 #define CCU6_CMPMODIF_MCC60S_Msk (0x1UL)
7091 #define CCU6_CMPMODIF_MCC61S_Pos (1UL)
7092 #define CCU6_CMPMODIF_MCC61S_Msk (0x2UL)
7093 #define CCU6_CMPMODIF_MCC62S_Pos (2UL)
7094 #define CCU6_CMPMODIF_MCC62S_Msk (0x4UL)
7095 #define CCU6_CMPMODIF_MCC63S_Pos (6UL)
7096 #define CCU6_CMPMODIF_MCC63S_Msk (0x40UL)
7097 #define CCU6_CMPMODIF_MCC60R_Pos (8UL)
7098 #define CCU6_CMPMODIF_MCC60R_Msk (0x100UL)
7099 #define CCU6_CMPMODIF_MCC61R_Pos (9UL)
7100 #define CCU6_CMPMODIF_MCC61R_Msk (0x200UL)
7101 #define CCU6_CMPMODIF_MCC62R_Pos (10UL)
7102 #define CCU6_CMPMODIF_MCC62R_Msk (0x400UL)
7103 #define CCU6_CMPMODIF_MCC63R_Pos (14UL)
7104 #define CCU6_CMPMODIF_MCC63R_Msk (0x4000UL)
7105 /* ======================================================== CMPSTAT ======================================================== */
7106 #define CCU6_CMPSTAT_CC60ST_Pos (0UL)
7107 #define CCU6_CMPSTAT_CC60ST_Msk (0x1UL)
7108 #define CCU6_CMPSTAT_CC61ST_Pos (1UL)
7109 #define CCU6_CMPSTAT_CC61ST_Msk (0x2UL)
7110 #define CCU6_CMPSTAT_CC62ST_Pos (2UL)
7111 #define CCU6_CMPSTAT_CC62ST_Msk (0x4UL)
7112 #define CCU6_CMPSTAT_CC63ST_Pos (6UL)
7113 #define CCU6_CMPSTAT_CC63ST_Msk (0x40UL)
7114 #define CCU6_CMPSTAT_CCPOS0_Pos (3UL)
7115 #define CCU6_CMPSTAT_CCPOS0_Msk (0x8UL)
7116 #define CCU6_CMPSTAT_CCPOS1_Pos (4UL)
7117 #define CCU6_CMPSTAT_CCPOS1_Msk (0x10UL)
7118 #define CCU6_CMPSTAT_CCPOS2_Pos (5UL)
7119 #define CCU6_CMPSTAT_CCPOS2_Msk (0x20UL)
7120 #define CCU6_CMPSTAT_CC60PS_Pos (8UL)
7121 #define CCU6_CMPSTAT_CC60PS_Msk (0x100UL)
7122 #define CCU6_CMPSTAT_CC61PS_Pos (10UL)
7123 #define CCU6_CMPSTAT_CC61PS_Msk (0x400UL)
7124 #define CCU6_CMPSTAT_CC62PS_Pos (12UL)
7125 #define CCU6_CMPSTAT_CC62PS_Msk (0x1000UL)
7126 #define CCU6_CMPSTAT_COUT60PS_Pos (9UL)
7127 #define CCU6_CMPSTAT_COUT60PS_Msk (0x200UL)
7128 #define CCU6_CMPSTAT_COUT61PS_Pos (11UL)
7129 #define CCU6_CMPSTAT_COUT61PS_Msk (0x800UL)
7130 #define CCU6_CMPSTAT_COUT62PS_Pos (13UL)
7131 #define CCU6_CMPSTAT_COUT62PS_Msk (0x2000UL)
7132 #define CCU6_CMPSTAT_COUT63PS_Pos (14UL)
7133 #define CCU6_CMPSTAT_COUT63PS_Msk (0x4000UL)
7134 #define CCU6_CMPSTAT_T13IM_Pos (15UL)
7135 #define CCU6_CMPSTAT_T13IM_Msk (0x8000UL)
7136 /* ========================================================== IEN ========================================================== */
7137 #define CCU6_IEN_ENCC60R_Pos (0UL)
7138 #define CCU6_IEN_ENCC60R_Msk (0x1UL)
7139 #define CCU6_IEN_ENCC60F_Pos (1UL)
7140 #define CCU6_IEN_ENCC60F_Msk (0x2UL)
7141 #define CCU6_IEN_ENCC61R_Pos (2UL)
7142 #define CCU6_IEN_ENCC61R_Msk (0x4UL)
7143 #define CCU6_IEN_ENCC61F_Pos (3UL)
7144 #define CCU6_IEN_ENCC61F_Msk (0x8UL)
7145 #define CCU6_IEN_ENCC62R_Pos (4UL)
7146 #define CCU6_IEN_ENCC62R_Msk (0x10UL)
7147 #define CCU6_IEN_ENCC62F_Pos (5UL)
7148 #define CCU6_IEN_ENCC62F_Msk (0x20UL)
7149 #define CCU6_IEN_ENT12OM_Pos (6UL)
7150 #define CCU6_IEN_ENT12OM_Msk (0x40UL)
7151 #define CCU6_IEN_ENT12PM_Pos (7UL)
7152 #define CCU6_IEN_ENT12PM_Msk (0x80UL)
7153 #define CCU6_IEN_ENT13CM_Pos (8UL)
7154 #define CCU6_IEN_ENT13CM_Msk (0x100UL)
7155 #define CCU6_IEN_ENT13PM_Pos (9UL)
7156 #define CCU6_IEN_ENT13PM_Msk (0x200UL)
7157 #define CCU6_IEN_ENTRPF_Pos (10UL)
7158 #define CCU6_IEN_ENTRPF_Msk (0x400UL)
7159 #define CCU6_IEN_ENCHE_Pos (12UL)
7160 #define CCU6_IEN_ENCHE_Msk (0x1000UL)
7161 #define CCU6_IEN_ENWHE_Pos (13UL)
7162 #define CCU6_IEN_ENWHE_Msk (0x2000UL)
7163 #define CCU6_IEN_ENIDLE_Pos (14UL)
7164 #define CCU6_IEN_ENIDLE_Msk (0x4000UL)
7165 #define CCU6_IEN_ENSTR_Pos (15UL)
7166 #define CCU6_IEN_ENSTR_Msk (0x8000UL)
7167 /* ========================================================== INP ========================================================== */
7168 #define CCU6_INP_INPCC60_Pos (0UL)
7169 #define CCU6_INP_INPCC60_Msk (0x3UL)
7170 #define CCU6_INP_INPCC61_Pos (2UL)
7171 #define CCU6_INP_INPCC61_Msk (0xcUL)
7172 #define CCU6_INP_INPCC62_Pos (4UL)
7173 #define CCU6_INP_INPCC62_Msk (0x30UL)
7174 #define CCU6_INP_INPCHE_Pos (6UL)
7175 #define CCU6_INP_INPCHE_Msk (0xc0UL)
7176 #define CCU6_INP_INPERR_Pos (8UL)
7177 #define CCU6_INP_INPERR_Msk (0x300UL)
7178 #define CCU6_INP_INPT12_Pos (10UL)
7179 #define CCU6_INP_INPT12_Msk (0xc00UL)
7180 #define CCU6_INP_INPT13_Pos (12UL)
7181 #define CCU6_INP_INPT13_Msk (0x3000UL)
7182 /* ========================================================== IS =========================================================== */
7183 #define CCU6_IS_ICC60R_Pos (0UL)
7184 #define CCU6_IS_ICC60R_Msk (0x1UL)
7185 #define CCU6_IS_ICC61R_Pos (2UL)
7186 #define CCU6_IS_ICC61R_Msk (0x4UL)
7187 #define CCU6_IS_ICC62R_Pos (4UL)
7188 #define CCU6_IS_ICC62R_Msk (0x10UL)
7189 #define CCU6_IS_ICC60F_Pos (1UL)
7190 #define CCU6_IS_ICC60F_Msk (0x2UL)
7191 #define CCU6_IS_ICC61F_Pos (3UL)
7192 #define CCU6_IS_ICC61F_Msk (0x8UL)
7193 #define CCU6_IS_ICC62F_Pos (5UL)
7194 #define CCU6_IS_ICC62F_Msk (0x20UL)
7195 #define CCU6_IS_T12OM_Pos (6UL)
7196 #define CCU6_IS_T12OM_Msk (0x40UL)
7197 #define CCU6_IS_T12PM_Pos (7UL)
7198 #define CCU6_IS_T12PM_Msk (0x80UL)
7199 #define CCU6_IS_T13CM_Pos (8UL)
7200 #define CCU6_IS_T13CM_Msk (0x100UL)
7201 #define CCU6_IS_T13PM_Pos (9UL)
7202 #define CCU6_IS_T13PM_Msk (0x200UL)
7203 #define CCU6_IS_TRPF_Pos (10UL)
7204 #define CCU6_IS_TRPF_Msk (0x400UL)
7205 #define CCU6_IS_TRPS_Pos (11UL)
7206 #define CCU6_IS_TRPS_Msk (0x800UL)
7207 #define CCU6_IS_CHE_Pos (12UL)
7208 #define CCU6_IS_CHE_Msk (0x1000UL)
7209 #define CCU6_IS_WHE_Pos (13UL)
7210 #define CCU6_IS_WHE_Msk (0x2000UL)
7211 #define CCU6_IS_IDLE_Pos (14UL)
7212 #define CCU6_IS_IDLE_Msk (0x4000UL)
7213 #define CCU6_IS_STR_Pos (15UL)
7214 #define CCU6_IS_STR_Msk (0x8000UL)
7215 /* ========================================================== ISR ========================================================== */
7216 #define CCU6_ISR_RCC60R_Pos (0UL)
7217 #define CCU6_ISR_RCC60R_Msk (0x1UL)
7218 #define CCU6_ISR_RCC60F_Pos (1UL)
7219 #define CCU6_ISR_RCC60F_Msk (0x2UL)
7220 #define CCU6_ISR_RCC61R_Pos (2UL)
7221 #define CCU6_ISR_RCC61R_Msk (0x4UL)
7222 #define CCU6_ISR_RCC61F_Pos (3UL)
7223 #define CCU6_ISR_RCC61F_Msk (0x8UL)
7224 #define CCU6_ISR_RCC62R_Pos (4UL)
7225 #define CCU6_ISR_RCC62R_Msk (0x10UL)
7226 #define CCU6_ISR_RCC62F_Pos (5UL)
7227 #define CCU6_ISR_RCC62F_Msk (0x20UL)
7228 #define CCU6_ISR_RT12OM_Pos (6UL)
7229 #define CCU6_ISR_RT12OM_Msk (0x40UL)
7230 #define CCU6_ISR_RT12PM_Pos (7UL)
7231 #define CCU6_ISR_RT12PM_Msk (0x80UL)
7232 #define CCU6_ISR_RT13CM_Pos (8UL)
7233 #define CCU6_ISR_RT13CM_Msk (0x100UL)
7234 #define CCU6_ISR_RT13PM_Pos (9UL)
7235 #define CCU6_ISR_RT13PM_Msk (0x200UL)
7236 #define CCU6_ISR_RTRPF_Pos (10UL)
7237 #define CCU6_ISR_RTRPF_Msk (0x400UL)
7238 #define CCU6_ISR_RCHE_Pos (12UL)
7239 #define CCU6_ISR_RCHE_Msk (0x1000UL)
7240 #define CCU6_ISR_RWHE_Pos (13UL)
7241 #define CCU6_ISR_RWHE_Msk (0x2000UL)
7242 #define CCU6_ISR_RIDLE_Pos (14UL)
7243 #define CCU6_ISR_RIDLE_Msk (0x4000UL)
7244 #define CCU6_ISR_RSTR_Pos (15UL)
7245 #define CCU6_ISR_RSTR_Msk (0x8000UL)
7246 /* ========================================================== ISS ========================================================== */
7247 #define CCU6_ISS_SCC60R_Pos (0UL)
7248 #define CCU6_ISS_SCC60R_Msk (0x1UL)
7249 #define CCU6_ISS_SCC60F_Pos (1UL)
7250 #define CCU6_ISS_SCC60F_Msk (0x2UL)
7251 #define CCU6_ISS_SCC61R_Pos (2UL)
7252 #define CCU6_ISS_SCC61R_Msk (0x4UL)
7253 #define CCU6_ISS_SCC61F_Pos (3UL)
7254 #define CCU6_ISS_SCC61F_Msk (0x8UL)
7255 #define CCU6_ISS_SCC62R_Pos (4UL)
7256 #define CCU6_ISS_SCC62R_Msk (0x10UL)
7257 #define CCU6_ISS_SCC62F_Pos (5UL)
7258 #define CCU6_ISS_SCC62F_Msk (0x20UL)
7259 #define CCU6_ISS_ST12OM_Pos (6UL)
7260 #define CCU6_ISS_ST12OM_Msk (0x40UL)
7261 #define CCU6_ISS_ST12PM_Pos (7UL)
7262 #define CCU6_ISS_ST12PM_Msk (0x80UL)
7263 #define CCU6_ISS_ST13CM_Pos (8UL)
7264 #define CCU6_ISS_ST13CM_Msk (0x100UL)
7265 #define CCU6_ISS_ST13PM_Pos (9UL)
7266 #define CCU6_ISS_ST13PM_Msk (0x200UL)
7267 #define CCU6_ISS_STRPF_Pos (10UL)
7268 #define CCU6_ISS_STRPF_Msk (0x400UL)
7269 #define CCU6_ISS_SWHC_Pos (11UL)
7270 #define CCU6_ISS_SWHC_Msk (0x800UL)
7271 #define CCU6_ISS_SCHE_Pos (12UL)
7272 #define CCU6_ISS_SCHE_Msk (0x1000UL)
7273 #define CCU6_ISS_SWHE_Pos (13UL)
7274 #define CCU6_ISS_SWHE_Msk (0x2000UL)
7275 #define CCU6_ISS_SIDLE_Pos (14UL)
7276 #define CCU6_ISS_SIDLE_Msk (0x4000UL)
7277 #define CCU6_ISS_SSTR_Pos (15UL)
7278 #define CCU6_ISS_SSTR_Msk (0x8000UL)
7279 /* ======================================================== MCMCTR ========================================================= */
7280 #define CCU6_MCMCTR_SWSEL_Pos (0UL)
7281 #define CCU6_MCMCTR_SWSEL_Msk (0x7UL)
7282 #define CCU6_MCMCTR_SWSYN_Pos (4UL)
7283 #define CCU6_MCMCTR_SWSYN_Msk (0x30UL)
7284 #define CCU6_MCMCTR_STE12U_Pos (8UL)
7285 #define CCU6_MCMCTR_STE12U_Msk (0x100UL)
7286 #define CCU6_MCMCTR_STE12D_Pos (9UL)
7287 #define CCU6_MCMCTR_STE12D_Msk (0x200UL)
7288 #define CCU6_MCMCTR_STE13U_Pos (10UL)
7289 #define CCU6_MCMCTR_STE13U_Msk (0x400UL)
7290 /* ======================================================== MCMOUT ========================================================= */
7291 #define CCU6_MCMOUT_MCMP_Pos (0UL)
7292 #define CCU6_MCMOUT_MCMP_Msk (0x3fUL)
7293 #define CCU6_MCMOUT_R_Pos (6UL)
7294 #define CCU6_MCMOUT_R_Msk (0x40UL)
7295 #define CCU6_MCMOUT_EXPH_Pos (8UL)
7296 #define CCU6_MCMOUT_EXPH_Msk (0x700UL)
7297 #define CCU6_MCMOUT_CURH_Pos (11UL)
7298 #define CCU6_MCMOUT_CURH_Msk (0x3800UL)
7299 /* ======================================================== MCMOUTS ======================================================== */
7300 #define CCU6_MCMOUTS_MCMPS_Pos (0UL)
7301 #define CCU6_MCMOUTS_MCMPS_Msk (0x3fUL)
7302 #define CCU6_MCMOUTS_STRMCM_Pos (7UL)
7303 #define CCU6_MCMOUTS_STRMCM_Msk (0x80UL)
7304 #define CCU6_MCMOUTS_EXPHS_Pos (8UL)
7305 #define CCU6_MCMOUTS_EXPHS_Msk (0x700UL)
7306 #define CCU6_MCMOUTS_CURHS_Pos (11UL)
7307 #define CCU6_MCMOUTS_CURHS_Msk (0x3800UL)
7308 #define CCU6_MCMOUTS_STRHP_Pos (15UL)
7309 #define CCU6_MCMOUTS_STRHP_Msk (0x8000UL)
7310 /* ======================================================== MODCTR ========================================================= */
7311 #define CCU6_MODCTR_T12MODEN_Pos (0UL)
7312 #define CCU6_MODCTR_T12MODEN_Msk (0x3fUL)
7313 #define CCU6_MODCTR_MCMEN_Pos (7UL)
7314 #define CCU6_MODCTR_MCMEN_Msk (0x80UL)
7315 #define CCU6_MODCTR_T13MODEN_Pos (8UL)
7316 #define CCU6_MODCTR_T13MODEN_Msk (0x3f00UL)
7317 #define CCU6_MODCTR_ECT13O_Pos (15UL)
7318 #define CCU6_MODCTR_ECT13O_Msk (0x8000UL)
7319 /* ======================================================== PISEL0 ========================================================= */
7320 #define CCU6_PISEL0_ISCC60_Pos (0UL)
7321 #define CCU6_PISEL0_ISCC60_Msk (0x3UL)
7322 #define CCU6_PISEL0_ISCC61_Pos (2UL)
7323 #define CCU6_PISEL0_ISCC61_Msk (0xcUL)
7324 #define CCU6_PISEL0_ISCC62_Pos (4UL)
7325 #define CCU6_PISEL0_ISCC62_Msk (0x30UL)
7326 #define CCU6_PISEL0_ISTRP_Pos (6UL)
7327 #define CCU6_PISEL0_ISTRP_Msk (0xc0UL)
7328 #define CCU6_PISEL0_ISPOS0_Pos (8UL)
7329 #define CCU6_PISEL0_ISPOS0_Msk (0x300UL)
7330 #define CCU6_PISEL0_ISPOS1_Pos (10UL)
7331 #define CCU6_PISEL0_ISPOS1_Msk (0xc00UL)
7332 #define CCU6_PISEL0_ISPOS2_Pos (12UL)
7333 #define CCU6_PISEL0_ISPOS2_Msk (0x3000UL)
7334 #define CCU6_PISEL0_IST12HR_Pos (14UL)
7335 #define CCU6_PISEL0_IST12HR_Msk (0xc000UL)
7336 /* ======================================================== PISEL2 ========================================================= */
7337 #define CCU6_PISEL2_IST13HR_Pos (0UL)
7338 #define CCU6_PISEL2_IST13HR_Msk (0x3UL)
7339 #define CCU6_PISEL2_ISCNT12_Pos (2UL)
7340 #define CCU6_PISEL2_ISCNT12_Msk (0xcUL)
7341 #define CCU6_PISEL2_ISCNT13_Pos (4UL)
7342 #define CCU6_PISEL2_ISCNT13_Msk (0x30UL)
7343 #define CCU6_PISEL2_T12EXT_Pos (6UL)
7344 #define CCU6_PISEL2_T12EXT_Msk (0x40UL)
7345 #define CCU6_PISEL2_T13EXT_Pos (7UL)
7346 #define CCU6_PISEL2_T13EXT_Msk (0x80UL)
7347 /* ========================================================= PSLR ========================================================== */
7348 #define CCU6_PSLR_PSL_Pos (0UL)
7349 #define CCU6_PSLR_PSL_Msk (0x3fUL)
7350 #define CCU6_PSLR_PSL63_Pos (7UL)
7351 #define CCU6_PSLR_PSL63_Msk (0x80UL)
7352 /* ========================================================== T12 ========================================================== */
7353 #define CCU6_T12_T12CV_Pos (0UL)
7354 #define CCU6_T12_T12CV_Msk (0xffffUL)
7355 /* ======================================================== T12DTC ========================================================= */
7356 #define CCU6_T12DTC_DTM_Pos (0UL)
7357 #define CCU6_T12DTC_DTM_Msk (0xffUL)
7358 #define CCU6_T12DTC_DTE0_Pos (8UL)
7359 #define CCU6_T12DTC_DTE0_Msk (0x100UL)
7360 #define CCU6_T12DTC_DTE1_Pos (9UL)
7361 #define CCU6_T12DTC_DTE1_Msk (0x200UL)
7362 #define CCU6_T12DTC_DTE2_Pos (10UL)
7363 #define CCU6_T12DTC_DTE2_Msk (0x400UL)
7364 #define CCU6_T12DTC_DTR0_Pos (12UL)
7365 #define CCU6_T12DTC_DTR0_Msk (0x1000UL)
7366 #define CCU6_T12DTC_DTR1_Pos (13UL)
7367 #define CCU6_T12DTC_DTR1_Msk (0x2000UL)
7368 #define CCU6_T12DTC_DTR2_Pos (14UL)
7369 #define CCU6_T12DTC_DTR2_Msk (0x4000UL)
7370 /* ======================================================== T12MSEL ======================================================== */
7371 #define CCU6_T12MSEL_MSEL60_Pos (0UL)
7372 #define CCU6_T12MSEL_MSEL60_Msk (0xfUL)
7373 #define CCU6_T12MSEL_MSEL61_Pos (4UL)
7374 #define CCU6_T12MSEL_MSEL61_Msk (0xf0UL)
7375 #define CCU6_T12MSEL_MSEL62_Pos (8UL)
7376 #define CCU6_T12MSEL_MSEL62_Msk (0xf00UL)
7377 #define CCU6_T12MSEL_HSYNC_Pos (12UL)
7378 #define CCU6_T12MSEL_HSYNC_Msk (0x7000UL)
7379 #define CCU6_T12MSEL_DBYP_Pos (15UL)
7380 #define CCU6_T12MSEL_DBYP_Msk (0x8000UL)
7381 /* ========================================================= T12PR ========================================================= */
7382 #define CCU6_T12PR_T12PV_Pos (0UL)
7383 #define CCU6_T12PR_T12PV_Msk (0xffffUL)
7384 /* ========================================================== T13 ========================================================== */
7385 #define CCU6_T13_T13CV_Pos (0UL)
7386 #define CCU6_T13_T13CV_Msk (0xffffUL)
7387 /* ========================================================= T13PR ========================================================= */
7388 #define CCU6_T13PR_T13PV_Pos (0UL)
7389 #define CCU6_T13PR_T13PV_Msk (0xffffUL)
7390 /* ========================================================= TCTR0 ========================================================= */
7391 #define CCU6_TCTR0_T12CLK_Pos (0UL)
7392 #define CCU6_TCTR0_T12CLK_Msk (0x7UL)
7393 #define CCU6_TCTR0_T12PRE_Pos (3UL)
7394 #define CCU6_TCTR0_T12PRE_Msk (0x8UL)
7395 #define CCU6_TCTR0_T12R_Pos (4UL)
7396 #define CCU6_TCTR0_T12R_Msk (0x10UL)
7397 #define CCU6_TCTR0_STE12_Pos (5UL)
7398 #define CCU6_TCTR0_STE12_Msk (0x20UL)
7399 #define CCU6_TCTR0_CDIR_Pos (6UL)
7400 #define CCU6_TCTR0_CDIR_Msk (0x40UL)
7401 #define CCU6_TCTR0_CTM_Pos (7UL)
7402 #define CCU6_TCTR0_CTM_Msk (0x80UL)
7403 #define CCU6_TCTR0_T13CLK_Pos (8UL)
7404 #define CCU6_TCTR0_T13CLK_Msk (0x700UL)
7405 #define CCU6_TCTR0_T13PRE_Pos (11UL)
7406 #define CCU6_TCTR0_T13PRE_Msk (0x800UL)
7407 #define CCU6_TCTR0_T13R_Pos (12UL)
7408 #define CCU6_TCTR0_T13R_Msk (0x1000UL)
7409 #define CCU6_TCTR0_STE13_Pos (13UL)
7410 #define CCU6_TCTR0_STE13_Msk (0x2000UL)
7411 /* ========================================================= TCTR2 ========================================================= */
7412 #define CCU6_TCTR2_T12SSC_Pos (0UL)
7413 #define CCU6_TCTR2_T12SSC_Msk (0x1UL)
7414 #define CCU6_TCTR2_T13SSC_Pos (1UL)
7415 #define CCU6_TCTR2_T13SSC_Msk (0x2UL)
7416 #define CCU6_TCTR2_T13TEC_Pos (2UL)
7417 #define CCU6_TCTR2_T13TEC_Msk (0x1cUL)
7418 #define CCU6_TCTR2_T13TED_Pos (5UL)
7419 #define CCU6_TCTR2_T13TED_Msk (0x60UL)
7420 #define CCU6_TCTR2_T12RSEL_Pos (8UL)
7421 #define CCU6_TCTR2_T12RSEL_Msk (0x300UL)
7422 #define CCU6_TCTR2_T13RSEL_Pos (10UL)
7423 #define CCU6_TCTR2_T13RSEL_Msk (0xc00UL)
7424 /* ========================================================= TCTR4 ========================================================= */
7425 #define CCU6_TCTR4_T12RR_Pos (0UL)
7426 #define CCU6_TCTR4_T12RR_Msk (0x1UL)
7427 #define CCU6_TCTR4_T12RS_Pos (1UL)
7428 #define CCU6_TCTR4_T12RS_Msk (0x2UL)
7429 #define CCU6_TCTR4_T12RES_Pos (2UL)
7430 #define CCU6_TCTR4_T12RES_Msk (0x4UL)
7431 #define CCU6_TCTR4_DTRES_Pos (3UL)
7432 #define CCU6_TCTR4_DTRES_Msk (0x8UL)
7433 #define CCU6_TCTR4_T12CNT_Pos (5UL)
7434 #define CCU6_TCTR4_T12CNT_Msk (0x20UL)
7435 #define CCU6_TCTR4_T12STR_Pos (6UL)
7436 #define CCU6_TCTR4_T12STR_Msk (0x40UL)
7437 #define CCU6_TCTR4_T12STD_Pos (7UL)
7438 #define CCU6_TCTR4_T12STD_Msk (0x80UL)
7439 #define CCU6_TCTR4_T13RR_Pos (8UL)
7440 #define CCU6_TCTR4_T13RR_Msk (0x100UL)
7441 #define CCU6_TCTR4_T13RS_Pos (9UL)
7442 #define CCU6_TCTR4_T13RS_Msk (0x200UL)
7443 #define CCU6_TCTR4_T13RES_Pos (10UL)
7444 #define CCU6_TCTR4_T13RES_Msk (0x400UL)
7445 #define CCU6_TCTR4_T13CNT_Pos (13UL)
7446 #define CCU6_TCTR4_T13CNT_Msk (0x2000UL)
7447 #define CCU6_TCTR4_T13STR_Pos (14UL)
7448 #define CCU6_TCTR4_T13STR_Msk (0x4000UL)
7449 #define CCU6_TCTR4_T13STD_Pos (15UL)
7450 #define CCU6_TCTR4_T13STD_Msk (0x8000UL)
7451 /* ======================================================== TRPCTR ========================================================= */
7452 #define CCU6_TRPCTR_TRPM0_Pos (0UL)
7453 #define CCU6_TRPCTR_TRPM0_Msk (0x1UL)
7454 #define CCU6_TRPCTR_TRPM1_Pos (1UL)
7455 #define CCU6_TRPCTR_TRPM1_Msk (0x2UL)
7456 #define CCU6_TRPCTR_TRPM2_Pos (2UL)
7457 #define CCU6_TRPCTR_TRPM2_Msk (0x4UL)
7458 #define CCU6_TRPCTR_TRPEN_Pos (8UL)
7459 #define CCU6_TRPCTR_TRPEN_Msk (0x3f00UL)
7460 #define CCU6_TRPCTR_TRPEN13_Pos (14UL)
7461 #define CCU6_TRPCTR_TRPEN13_Msk (0x4000UL)
7462 #define CCU6_TRPCTR_TRPPEN_Pos (15UL)
7463 #define CCU6_TRPCTR_TRPPEN_Msk (0x8000UL)
7466 /* =========================================================================================================================== */
7467 /* ================ CPU ================ */
7468 /* =========================================================================================================================== */
7469 
7470 /* ========================================================= AFSR ========================================================== */
7471 #define CPU_AFSR_CP0_Pos (0UL)
7472 #define CPU_AFSR_CP0_Msk (0x3UL)
7473 #define CPU_AFSR_CP1_Pos (2UL)
7474 #define CPU_AFSR_CP1_Msk (0xcUL)
7475 #define CPU_AFSR_CP2_Pos (4UL)
7476 #define CPU_AFSR_CP2_Msk (0x30UL)
7477 #define CPU_AFSR_CP3_Pos (6UL)
7478 #define CPU_AFSR_CP3_Msk (0xc0UL)
7479 #define CPU_AFSR_CP4_Pos (8UL)
7480 #define CPU_AFSR_CP4_Msk (0x300UL)
7481 #define CPU_AFSR_CP5_Pos (10UL)
7482 #define CPU_AFSR_CP5_Msk (0xc00UL)
7483 #define CPU_AFSR_CP6_Pos (12UL)
7484 #define CPU_AFSR_CP6_Msk (0x3000UL)
7485 #define CPU_AFSR_CP7_Pos (14UL)
7486 #define CPU_AFSR_CP7_Msk (0xc000UL)
7487 #define CPU_AFSR_CP10_Pos (20UL)
7488 #define CPU_AFSR_CP10_Msk (0x300000UL)
7489 #define CPU_AFSR_CP11_Pos (22UL)
7490 #define CPU_AFSR_CP11_Msk (0xc00000UL)
7491 /* ========================================================= AIRCR ========================================================= */
7492 #define CPU_AIRCR_VECTKEY_Pos (16UL)
7493 #define CPU_AIRCR_VECTKEY_Msk (0xffff0000UL)
7494 #define CPU_AIRCR_ENDIANNESS_Pos (15UL)
7495 #define CPU_AIRCR_ENDIANNESS_Msk (0x8000UL)
7496 #define CPU_AIRCR_PRIGROUP_Pos (8UL)
7497 #define CPU_AIRCR_PRIGROUP_Msk (0x700UL)
7498 #define CPU_AIRCR_SYSRESETREQ_Pos (2UL)
7499 #define CPU_AIRCR_SYSRESETREQ_Msk (0x4UL)
7500 #define CPU_AIRCR_VECTCLRACTIVE_Pos (1UL)
7501 #define CPU_AIRCR_VECTCLRACTIVE_Msk (0x2UL)
7502 #define CPU_AIRCR_VECTRESET_Pos (0UL)
7503 #define CPU_AIRCR_VECTRESET_Msk (0x1UL)
7504 /* ========================================================= BFAR ========================================================== */
7505 #define CPU_BFAR_ADDRESS_Pos (0UL)
7506 #define CPU_BFAR_ADDRESS_Msk (0xffffffffUL)
7507 /* ========================================================== CCR ========================================================== */
7508 #define CPU_CCR_STKALIGN_Pos (9UL)
7509 #define CPU_CCR_STKALIGN_Msk (0x200UL)
7510 #define CPU_CCR_BFHFMIGN_Pos (8UL)
7511 #define CPU_CCR_BFHFMIGN_Msk (0x100UL)
7512 #define CPU_CCR_DIV_0_TRP_Pos (4UL)
7513 #define CPU_CCR_DIV_0_TRP_Msk (0x10UL)
7514 #define CPU_CCR_UNALIGN_TRP_Pos (3UL)
7515 #define CPU_CCR_UNALIGN_TRP_Msk (0x8UL)
7516 #define CPU_CCR_USERSETMPEND_Pos (1UL)
7517 #define CPU_CCR_USERSETMPEND_Msk (0x2UL)
7518 #define CPU_CCR_NONBASETHRDENA_Pos (0UL)
7519 #define CPU_CCR_NONBASETHRDENA_Msk (0x1UL)
7520 /* ========================================================= CFSR ========================================================== */
7521 #define CPU_CFSR_DIVBYZERO_Pos (25UL)
7522 #define CPU_CFSR_DIVBYZERO_Msk (0x2000000UL)
7523 #define CPU_CFSR_UNALIGNED_Pos (24UL)
7524 #define CPU_CFSR_UNALIGNED_Msk (0x1000000UL)
7525 #define CPU_CFSR_NOCP_Pos (19UL)
7526 #define CPU_CFSR_NOCP_Msk (0x80000UL)
7527 #define CPU_CFSR_INVPC_Pos (18UL)
7528 #define CPU_CFSR_INVPC_Msk (0x40000UL)
7529 #define CPU_CFSR_INVSTATE_Pos (17UL)
7530 #define CPU_CFSR_INVSTATE_Msk (0x20000UL)
7531 #define CPU_CFSR_UNDEFINSTR_Pos (16UL)
7532 #define CPU_CFSR_UNDEFINSTR_Msk (0x10000UL)
7533 #define CPU_CFSR_BFARVALID_Pos (15UL)
7534 #define CPU_CFSR_BFARVALID_Msk (0x8000UL)
7535 #define CPU_CFSR_STKERR_Pos (12UL)
7536 #define CPU_CFSR_STKERR_Msk (0x1000UL)
7537 #define CPU_CFSR_UNSTKERR_Pos (11UL)
7538 #define CPU_CFSR_UNSTKERR_Msk (0x800UL)
7539 #define CPU_CFSR_IMPRECISERR_Pos (10UL)
7540 #define CPU_CFSR_IMPRECISERR_Msk (0x400UL)
7541 #define CPU_CFSR_PRECISERR_Pos (9UL)
7542 #define CPU_CFSR_PRECISERR_Msk (0x200UL)
7543 #define CPU_CFSR_IBUSERR_Pos (8UL)
7544 #define CPU_CFSR_IBUSERR_Msk (0x100UL)
7545 #define CPU_CFSR_MMARVALID_Pos (7UL)
7546 #define CPU_CFSR_MMARVALID_Msk (0x80UL)
7547 #define CPU_CFSR_MSTERR_Pos (4UL)
7548 #define CPU_CFSR_MSTERR_Msk (0x10UL)
7549 #define CPU_CFSR_MUNSTKERR_Pos (3UL)
7550 #define CPU_CFSR_MUNSTKERR_Msk (0x8UL)
7551 #define CPU_CFSR_DACCVIOL_Pos (1UL)
7552 #define CPU_CFSR_DACCVIOL_Msk (0x2UL)
7553 #define CPU_CFSR_IACCVIOL_Pos (0UL)
7554 #define CPU_CFSR_IACCVIOL_Msk (0x1UL)
7555 /* ========================================================= CPUID ========================================================= */
7556 #define CPU_CPUID_IMPLEMENTER_Pos (24UL)
7557 #define CPU_CPUID_IMPLEMENTER_Msk (0xff000000UL)
7558 #define CPU_CPUID_VARIANT_Pos (20UL)
7559 #define CPU_CPUID_VARIANT_Msk (0xf00000UL)
7560 #define CPU_CPUID_ARCHITECTURE_Pos (16UL)
7561 #define CPU_CPUID_ARCHITECTURE_Msk (0xf0000UL)
7562 #define CPU_CPUID_PARTNO_Pos (4UL)
7563 #define CPU_CPUID_PARTNO_Msk (0xfff0UL)
7564 #define CPU_CPUID_REVISION_Pos (0UL)
7565 #define CPU_CPUID_REVISION_Msk (0xfUL)
7566 /* ========================================================= DFSR ========================================================== */
7567 #define CPU_DFSR_EXTERNAL_Pos (4UL)
7568 #define CPU_DFSR_EXTERNAL_Msk (0x10UL)
7569 #define CPU_DFSR_VCATCH_Pos (3UL)
7570 #define CPU_DFSR_VCATCH_Msk (0x8UL)
7571 #define CPU_DFSR_DWTTRAP_Pos (2UL)
7572 #define CPU_DFSR_DWTTRAP_Msk (0x4UL)
7573 #define CPU_DFSR_BKPT_Pos (1UL)
7574 #define CPU_DFSR_BKPT_Msk (0x2UL)
7575 #define CPU_DFSR_HALTED_Pos (0UL)
7576 #define CPU_DFSR_HALTED_Msk (0x1UL)
7577 /* ========================================================= HFSR ========================================================== */
7578 #define CPU_HFSR_DEBUGEVT_Pos (31UL)
7579 #define CPU_HFSR_DEBUGEVT_Msk (0x80000000UL)
7580 #define CPU_HFSR_FORCED_Pos (30UL)
7581 #define CPU_HFSR_FORCED_Msk (0x40000000UL)
7582 #define CPU_HFSR_VECTTBL_Pos (1UL)
7583 #define CPU_HFSR_VECTTBL_Msk (0x2UL)
7584 /* ========================================================= ICSR ========================================================== */
7585 #define CPU_ICSR_NMIPENDSET_Pos (31UL)
7586 #define CPU_ICSR_NMIPENDSET_Msk (0x80000000UL)
7587 #define CPU_ICSR_PENDSVSET_Pos (28UL)
7588 #define CPU_ICSR_PENDSVSET_Msk (0x10000000UL)
7589 #define CPU_ICSR_PENDSVCLR_Pos (27UL)
7590 #define CPU_ICSR_PENDSVCLR_Msk (0x8000000UL)
7591 #define CPU_ICSR_PENDSTSET_Pos (26UL)
7592 #define CPU_ICSR_PENDSTSET_Msk (0x4000000UL)
7593 #define CPU_ICSR_PENDSTCLR_Pos (25UL)
7594 #define CPU_ICSR_PENDSTCLR_Msk (0x2000000UL)
7595 #define CPU_ICSR_ISRPREEMPT_Pos (23UL)
7596 #define CPU_ICSR_ISRPREEMPT_Msk (0x800000UL)
7597 #define CPU_ICSR_ISRPENDING_Pos (22UL)
7598 #define CPU_ICSR_ISRPENDING_Msk (0x400000UL)
7599 #define CPU_ICSR_VECTPENDING_Pos (12UL)
7600 #define CPU_ICSR_VECTPENDING_Msk (0x1ff000UL)
7601 #define CPU_ICSR_RETTOBASE_Pos (11UL)
7602 #define CPU_ICSR_RETTOBASE_Msk (0x800UL)
7603 #define CPU_ICSR_VECTACTIVE_Pos (0UL)
7604 #define CPU_ICSR_VECTACTIVE_Msk (0x1ffUL)
7605 /* ========================================================== ICT ========================================================== */
7606 #define CPU_ICT_INTLINESNUM_Pos (0UL)
7607 #define CPU_ICT_INTLINESNUM_Msk (0x1fUL)
7608 /* ========================================================= MMFAR ========================================================= */
7609 #define CPU_MMFAR_ADDRESS_Pos (0UL)
7610 #define CPU_MMFAR_ADDRESS_Msk (0xffffffffUL)
7611 /* ====================================================== NVIC_IABR0 ======================================================= */
7612 #define CPU_NVIC_IABR0_Int_DMA_Pos (15UL)
7613 #define CPU_NVIC_IABR0_Int_DMA_Msk (0x8000UL)
7614 #define CPU_NVIC_IABR0_Int_BDRV_Pos (14UL)
7615 #define CPU_NVIC_IABR0_Int_BDRV_Msk (0x4000UL)
7616 #define CPU_NVIC_IABR0_Int_EXINT1_Pos (13UL)
7617 #define CPU_NVIC_IABR0_Int_EXINT1_Msk (0x2000UL)
7618 #define CPU_NVIC_IABR0_Int_EXINT0_Pos (12UL)
7619 #define CPU_NVIC_IABR0_Int_EXINT0_Msk (0x1000UL)
7620 #define CPU_NVIC_IABR0_Int_UART2_Pos (11UL)
7621 #define CPU_NVIC_IABR0_Int_UART2_Msk (0x800UL)
7622 #define CPU_NVIC_IABR0_Int_UART1_Pos (10UL)
7623 #define CPU_NVIC_IABR0_Int_UART1_Msk (0x400UL)
7624 #define CPU_NVIC_IABR0_Int_SSC2_Pos (9UL)
7625 #define CPU_NVIC_IABR0_Int_SSC2_Msk (0x200UL)
7626 #define CPU_NVIC_IABR0_Int_SSC1_Pos (8UL)
7627 #define CPU_NVIC_IABR0_Int_SSC1_Msk (0x100UL)
7628 #define CPU_NVIC_IABR0_Int_CCU6SR3_Pos (7UL)
7629 #define CPU_NVIC_IABR0_Int_CCU6SR3_Msk (0x80UL)
7630 #define CPU_NVIC_IABR0_Int_CCU6SR2_Pos (6UL)
7631 #define CPU_NVIC_IABR0_Int_CCU6SR2_Msk (0x40UL)
7632 #define CPU_NVIC_IABR0_Int_CCU6SR1_Pos (5UL)
7633 #define CPU_NVIC_IABR0_Int_CCU6SR1_Msk (0x20UL)
7634 #define CPU_NVIC_IABR0_Int_CCU6SR0_Pos (4UL)
7635 #define CPU_NVIC_IABR0_Int_CCU6SR0_Msk (0x10UL)
7636 #define CPU_NVIC_IABR0_Int_ADC1_Pos (3UL)
7637 #define CPU_NVIC_IABR0_Int_ADC1_Msk (0x8UL)
7638 #define CPU_NVIC_IABR0_Int_ADC2_Pos (2UL)
7639 #define CPU_NVIC_IABR0_Int_ADC2_Msk (0x4UL)
7640 #define CPU_NVIC_IABR0_Int_GPT2_Pos (1UL)
7641 #define CPU_NVIC_IABR0_Int_GPT2_Msk (0x2UL)
7642 #define CPU_NVIC_IABR0_Int_GPT1_Pos (0UL)
7643 #define CPU_NVIC_IABR0_Int_GPT1_Msk (0x1UL)
7644 /* ====================================================== NVIC_ICER0 ======================================================= */
7645 #define CPU_NVIC_ICER0_Int_DMA_Pos (15UL)
7646 #define CPU_NVIC_ICER0_Int_DMA_Msk (0x8000UL)
7647 #define CPU_NVIC_ICER0_Int_BDRV_Pos (14UL)
7648 #define CPU_NVIC_ICER0_Int_BDRV_Msk (0x4000UL)
7649 #define CPU_NVIC_ICER0_Int_EXINT1_Pos (13UL)
7650 #define CPU_NVIC_ICER0_Int_EXINT1_Msk (0x2000UL)
7651 #define CPU_NVIC_ICER0_Int_EXINT0_Pos (12UL)
7652 #define CPU_NVIC_ICER0_Int_EXINT0_Msk (0x1000UL)
7653 #define CPU_NVIC_ICER0_Int_UART2_Pos (11UL)
7654 #define CPU_NVIC_ICER0_Int_UART2_Msk (0x800UL)
7655 #define CPU_NVIC_ICER0_Int_UART1_Pos (10UL)
7656 #define CPU_NVIC_ICER0_Int_UART1_Msk (0x400UL)
7657 #define CPU_NVIC_ICER0_Int_SSC2_Pos (9UL)
7658 #define CPU_NVIC_ICER0_Int_SSC2_Msk (0x200UL)
7659 #define CPU_NVIC_ICER0_Int_SSC1_Pos (8UL)
7660 #define CPU_NVIC_ICER0_Int_SSC1_Msk (0x100UL)
7661 #define CPU_NVIC_ICER0_Int_CCU6SR3_Pos (7UL)
7662 #define CPU_NVIC_ICER0_Int_CCU6SR3_Msk (0x80UL)
7663 #define CPU_NVIC_ICER0_Int_CCU6SR2_Pos (6UL)
7664 #define CPU_NVIC_ICER0_Int_CCU6SR2_Msk (0x40UL)
7665 #define CPU_NVIC_ICER0_Int_CCU6SR1_Pos (5UL)
7666 #define CPU_NVIC_ICER0_Int_CCU6SR1_Msk (0x20UL)
7667 #define CPU_NVIC_ICER0_Int_CCU6SR0_Pos (4UL)
7668 #define CPU_NVIC_ICER0_Int_CCU6SR0_Msk (0x10UL)
7669 #define CPU_NVIC_ICER0_Int_ADC1_Pos (3UL)
7670 #define CPU_NVIC_ICER0_Int_ADC1_Msk (0x8UL)
7671 #define CPU_NVIC_ICER0_Int_ADC2_Pos (2UL)
7672 #define CPU_NVIC_ICER0_Int_ADC2_Msk (0x4UL)
7673 #define CPU_NVIC_ICER0_Int_GPT2_Pos (1UL)
7674 #define CPU_NVIC_ICER0_Int_GPT2_Msk (0x2UL)
7675 #define CPU_NVIC_ICER0_Int_GPT1_Pos (0UL)
7676 #define CPU_NVIC_ICER0_Int_GPT1_Msk (0x1UL)
7677 /* ====================================================== NVIC_ICPR0 ======================================================= */
7678 #define CPU_NVIC_ICPR0_Int_DMA_Pos (15UL)
7679 #define CPU_NVIC_ICPR0_Int_DMA_Msk (0x8000UL)
7680 #define CPU_NVIC_ICPR0_Int_BDRV_Pos (14UL)
7681 #define CPU_NVIC_ICPR0_Int_BDRV_Msk (0x4000UL)
7682 #define CPU_NVIC_ICPR0_Int_EXINT1_Pos (13UL)
7683 #define CPU_NVIC_ICPR0_Int_EXINT1_Msk (0x2000UL)
7684 #define CPU_NVIC_ICPR0_Int_EXINT0_Pos (12UL)
7685 #define CPU_NVIC_ICPR0_Int_EXINT0_Msk (0x1000UL)
7686 #define CPU_NVIC_ICPR0_Int_UART2_Pos (11UL)
7687 #define CPU_NVIC_ICPR0_Int_UART2_Msk (0x800UL)
7688 #define CPU_NVIC_ICPR0_Int_UART1_Pos (10UL)
7689 #define CPU_NVIC_ICPR0_Int_UART1_Msk (0x400UL)
7690 #define CPU_NVIC_ICPR0_Int_SSC2_Pos (9UL)
7691 #define CPU_NVIC_ICPR0_Int_SSC2_Msk (0x200UL)
7692 #define CPU_NVIC_ICPR0_Int_SSC1_Pos (8UL)
7693 #define CPU_NVIC_ICPR0_Int_SSC1_Msk (0x100UL)
7694 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Pos (7UL)
7695 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Msk (0x80UL)
7696 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Pos (6UL)
7697 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Msk (0x40UL)
7698 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Pos (5UL)
7699 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Msk (0x20UL)
7700 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Pos (4UL)
7701 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Msk (0x10UL)
7702 #define CPU_NVIC_ICPR0_Int_ADC1_Pos (3UL)
7703 #define CPU_NVIC_ICPR0_Int_ADC1_Msk (0x8UL)
7704 #define CPU_NVIC_ICPR0_Int_ADC2_Pos (2UL)
7705 #define CPU_NVIC_ICPR0_Int_ADC2_Msk (0x4UL)
7706 #define CPU_NVIC_ICPR0_Int_GPT2_Pos (1UL)
7707 #define CPU_NVIC_ICPR0_Int_GPT2_Msk (0x2UL)
7708 #define CPU_NVIC_ICPR0_Int_GPT1_Pos (0UL)
7709 #define CPU_NVIC_ICPR0_Int_GPT1_Msk (0x1UL)
7710 /* ======================================================= NVIC_IPR0 ======================================================= */
7711 #define CPU_NVIC_IPR0_PRI_ADC1_Pos (24UL)
7712 #define CPU_NVIC_IPR0_PRI_ADC1_Msk (0xff000000UL)
7713 #define CPU_NVIC_IPR0_PRI_ADC2_Pos (16UL)
7714 #define CPU_NVIC_IPR0_PRI_ADC2_Msk (0xff0000UL)
7715 #define CPU_NVIC_IPR0_PRI_GPT2_Pos (8UL)
7716 #define CPU_NVIC_IPR0_PRI_GPT2_Msk (0xff00UL)
7717 #define CPU_NVIC_IPR0_PRI_GPT1_Pos (0UL)
7718 #define CPU_NVIC_IPR0_PRI_GPT1_Msk (0xffUL)
7719 /* ======================================================= NVIC_IPR1 ======================================================= */
7720 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Pos (24UL)
7721 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Msk (0xff000000UL)
7722 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Pos (16UL)
7723 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Msk (0xff0000UL)
7724 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Pos (8UL)
7725 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Msk (0xff00UL)
7726 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Pos (0UL)
7727 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Msk (0xffUL)
7728 /* ======================================================= NVIC_IPR2 ======================================================= */
7729 #define CPU_NVIC_IPR2_PRI_UART2_Pos (24UL)
7730 #define CPU_NVIC_IPR2_PRI_UART2_Msk (0xff000000UL)
7731 #define CPU_NVIC_IPR2_PRI_UART1_Pos (16UL)
7732 #define CPU_NVIC_IPR2_PRI_UART1_Msk (0xff0000UL)
7733 #define CPU_NVIC_IPR2_PRI_SSC2_Pos (8UL)
7734 #define CPU_NVIC_IPR2_PRI_SSC2_Msk (0xff00UL)
7735 #define CPU_NVIC_IPR2_PRI_SSC1_Pos (0UL)
7736 #define CPU_NVIC_IPR2_PRI_SSC1_Msk (0xffUL)
7737 /* ======================================================= NVIC_IPR3 ======================================================= */
7738 #define CPU_NVIC_IPR3_PRI_DMA_Pos (24UL)
7739 #define CPU_NVIC_IPR3_PRI_DMA_Msk (0xff000000UL)
7740 #define CPU_NVIC_IPR3_PRI_BDRV_Pos (16UL)
7741 #define CPU_NVIC_IPR3_PRI_BDRV_Msk (0xff0000UL)
7742 #define CPU_NVIC_IPR3_PRI_EXINT1_Pos (8UL)
7743 #define CPU_NVIC_IPR3_PRI_EXINT1_Msk (0xff00UL)
7744 #define CPU_NVIC_IPR3_PRI_EXINT0_Pos (0UL)
7745 #define CPU_NVIC_IPR3_PRI_EXINT0_Msk (0xffUL)
7746 /* ====================================================== NVIC_ISER0 ======================================================= */
7747 #define CPU_NVIC_ISER0_Int_DMA_Pos (15UL)
7748 #define CPU_NVIC_ISER0_Int_DMA_Msk (0x8000UL)
7749 #define CPU_NVIC_ISER0_Int_BDRV_Pos (14UL)
7750 #define CPU_NVIC_ISER0_Int_BDRV_Msk (0x4000UL)
7751 #define CPU_NVIC_ISER0_Int_EXINT1_Pos (13UL)
7752 #define CPU_NVIC_ISER0_Int_EXINT1_Msk (0x2000UL)
7753 #define CPU_NVIC_ISER0_Int_EXINT0_Pos (12UL)
7754 #define CPU_NVIC_ISER0_Int_EXINT0_Msk (0x1000UL)
7755 #define CPU_NVIC_ISER0_Int_UART2_Pos (11UL)
7756 #define CPU_NVIC_ISER0_Int_UART2_Msk (0x800UL)
7757 #define CPU_NVIC_ISER0_Int_UART1_Pos (10UL)
7758 #define CPU_NVIC_ISER0_Int_UART1_Msk (0x400UL)
7759 #define CPU_NVIC_ISER0_Int_SSC2_Pos (9UL)
7760 #define CPU_NVIC_ISER0_Int_SSC2_Msk (0x200UL)
7761 #define CPU_NVIC_ISER0_Int_SSC1_Pos (8UL)
7762 #define CPU_NVIC_ISER0_Int_SSC1_Msk (0x100UL)
7763 #define CPU_NVIC_ISER0_Int_CCU6SR3_Pos (7UL)
7764 #define CPU_NVIC_ISER0_Int_CCU6SR3_Msk (0x80UL)
7765 #define CPU_NVIC_ISER0_Int_CCU6SR2_Pos (6UL)
7766 #define CPU_NVIC_ISER0_Int_CCU6SR2_Msk (0x40UL)
7767 #define CPU_NVIC_ISER0_Int_CCU6SR1_Pos (5UL)
7768 #define CPU_NVIC_ISER0_Int_CCU6SR1_Msk (0x20UL)
7769 #define CPU_NVIC_ISER0_Int_CCU6SR0_Pos (4UL)
7770 #define CPU_NVIC_ISER0_Int_CCU6SR0_Msk (0x10UL)
7771 #define CPU_NVIC_ISER0_Int_ADC1_Pos (3UL)
7772 #define CPU_NVIC_ISER0_Int_ADC1_Msk (0x8UL)
7773 #define CPU_NVIC_ISER0_Int_ADC2_Pos (2UL)
7774 #define CPU_NVIC_ISER0_Int_ADC2_Msk (0x4UL)
7775 #define CPU_NVIC_ISER0_Int_GPT2_Pos (1UL)
7776 #define CPU_NVIC_ISER0_Int_GPT2_Msk (0x2UL)
7777 #define CPU_NVIC_ISER0_Int_GPT1_Pos (0UL)
7778 #define CPU_NVIC_ISER0_Int_GPT1_Msk (0x1UL)
7779 /* ====================================================== NVIC_ISPR0 ======================================================= */
7780 #define CPU_NVIC_ISPR0_Int_DMA_Pos (15UL)
7781 #define CPU_NVIC_ISPR0_Int_DMA_Msk (0x8000UL)
7782 #define CPU_NVIC_ISPR0_Int_BDRV_Pos (14UL)
7783 #define CPU_NVIC_ISPR0_Int_BDRV_Msk (0x4000UL)
7784 #define CPU_NVIC_ISPR0_Int_EXINT1_Pos (13UL)
7785 #define CPU_NVIC_ISPR0_Int_EXINT1_Msk (0x2000UL)
7786 #define CPU_NVIC_ISPR0_Int_EXINT0_Pos (12UL)
7787 #define CPU_NVIC_ISPR0_Int_EXINT0_Msk (0x1000UL)
7788 #define CPU_NVIC_ISPR0_Int_UART2_Pos (11UL)
7789 #define CPU_NVIC_ISPR0_Int_UART2_Msk (0x800UL)
7790 #define CPU_NVIC_ISPR0_Int_UART1_Pos (10UL)
7791 #define CPU_NVIC_ISPR0_Int_UART1_Msk (0x400UL)
7792 #define CPU_NVIC_ISPR0_Int_SSC2_Pos (9UL)
7793 #define CPU_NVIC_ISPR0_Int_SSC2_Msk (0x200UL)
7794 #define CPU_NVIC_ISPR0_Int_SSC1_Pos (8UL)
7795 #define CPU_NVIC_ISPR0_Int_SSC1_Msk (0x100UL)
7796 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Pos (7UL)
7797 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Msk (0x80UL)
7798 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Pos (6UL)
7799 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Msk (0x40UL)
7800 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Pos (5UL)
7801 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Msk (0x20UL)
7802 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Pos (4UL)
7803 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Msk (0x10UL)
7804 #define CPU_NVIC_ISPR0_Int_ADC1_Pos (3UL)
7805 #define CPU_NVIC_ISPR0_Int_ADC1_Msk (0x8UL)
7806 #define CPU_NVIC_ISPR0_Int_ADC2_Pos (2UL)
7807 #define CPU_NVIC_ISPR0_Int_ADC2_Msk (0x4UL)
7808 #define CPU_NVIC_ISPR0_Int_GPT2_Pos (1UL)
7809 #define CPU_NVIC_ISPR0_Int_GPT2_Msk (0x2UL)
7810 #define CPU_NVIC_ISPR0_Int_GPT1_Pos (0UL)
7811 #define CPU_NVIC_ISPR0_Int_GPT1_Msk (0x1UL)
7812 /* ========================================================== SCR ========================================================== */
7813 #define CPU_SCR_SEVONPEND_Pos (4UL)
7814 #define CPU_SCR_SEVONPEND_Msk (0x10UL)
7815 #define CPU_SCR_SLEEPDEEP_Pos (2UL)
7816 #define CPU_SCR_SLEEPDEEP_Msk (0x4UL)
7817 #define CPU_SCR_SLEEPONEXIT_Pos (1UL)
7818 #define CPU_SCR_SLEEPONEXIT_Msk (0x2UL)
7819 /* ========================================================= SHCSR ========================================================= */
7820 #define CPU_SHCSR_USGFAULTENA_Pos (18UL)
7821 #define CPU_SHCSR_USGFAULTENA_Msk (0x40000UL)
7822 #define CPU_SHCSR_BUSFAULTENA_Pos (17UL)
7823 #define CPU_SHCSR_BUSFAULTENA_Msk (0x20000UL)
7824 #define CPU_SHCSR_MEMFAULTENA_Pos (16UL)
7825 #define CPU_SHCSR_MEMFAULTENA_Msk (0x10000UL)
7826 #define CPU_SHCSR_SVCALLPENDED_Pos (15UL)
7827 #define CPU_SHCSR_SVCALLPENDED_Msk (0x8000UL)
7828 #define CPU_SHCSR_BUSFAULTPENDED_Pos (14UL)
7829 #define CPU_SHCSR_BUSFAULTPENDED_Msk (0x4000UL)
7830 #define CPU_SHCSR_MEMFAULTPENDED_Pos (13UL)
7831 #define CPU_SHCSR_MEMFAULTPENDED_Msk (0x2000UL)
7832 #define CPU_SHCSR_USGFAULTPENDED_Pos (12UL)
7833 #define CPU_SHCSR_USGFAULTPENDED_Msk (0x1000UL)
7834 #define CPU_SHCSR_SYSTICKACT_Pos (11UL)
7835 #define CPU_SHCSR_SYSTICKACT_Msk (0x800UL)
7836 #define CPU_SHCSR_PENDSVACT_Pos (10UL)
7837 #define CPU_SHCSR_PENDSVACT_Msk (0x400UL)
7838 #define CPU_SHCSR_MONITORACT_Pos (8UL)
7839 #define CPU_SHCSR_MONITORACT_Msk (0x100UL)
7840 #define CPU_SHCSR_SVCALLACT_Pos (7UL)
7841 #define CPU_SHCSR_SVCALLACT_Msk (0x80UL)
7842 #define CPU_SHCSR_USGFAULTACT_Pos (3UL)
7843 #define CPU_SHCSR_USGFAULTACT_Msk (0x8UL)
7844 #define CPU_SHCSR_BUSFAULTACT_Pos (1UL)
7845 #define CPU_SHCSR_BUSFAULTACT_Msk (0x2UL)
7846 #define CPU_SHCSR_MEMFAULTACT_Pos (0UL)
7847 #define CPU_SHCSR_MEMFAULTACT_Msk (0x1UL)
7848 /* ========================================================= SHPR1 ========================================================= */
7849 #define CPU_SHPR1_PRI_7_Pos (24UL)
7850 #define CPU_SHPR1_PRI_7_Msk (0xff000000UL)
7851 #define CPU_SHPR1_PRI_6_Pos (16UL)
7852 #define CPU_SHPR1_PRI_6_Msk (0xff0000UL)
7853 #define CPU_SHPR1_PRI_5_Pos (8UL)
7854 #define CPU_SHPR1_PRI_5_Msk (0xff00UL)
7855 #define CPU_SHPR1_PRI_4_Pos (0UL)
7856 #define CPU_SHPR1_PRI_4_Msk (0xffUL)
7857 /* ========================================================= SHPR2 ========================================================= */
7858 #define CPU_SHPR2_PRI_11_Pos (24UL)
7859 #define CPU_SHPR2_PRI_11_Msk (0xff000000UL)
7860 #define CPU_SHPR2_PRI_10_Pos (16UL)
7861 #define CPU_SHPR2_PRI_10_Msk (0xff0000UL)
7862 #define CPU_SHPR2_PRI_9_Pos (8UL)
7863 #define CPU_SHPR2_PRI_9_Msk (0xff00UL)
7864 #define CPU_SHPR2_PRI_8_Pos (0UL)
7865 #define CPU_SHPR2_PRI_8_Msk (0xffUL)
7866 /* ========================================================= SHPR3 ========================================================= */
7867 #define CPU_SHPR3_PRI_15_Pos (24UL)
7868 #define CPU_SHPR3_PRI_15_Msk (0xff000000UL)
7869 #define CPU_SHPR3_PRI_14_Pos (16UL)
7870 #define CPU_SHPR3_PRI_14_Msk (0xff0000UL)
7871 #define CPU_SHPR3_PRI_13_Pos (8UL)
7872 #define CPU_SHPR3_PRI_13_Msk (0xff00UL)
7873 #define CPU_SHPR3_PRI_12_Pos (0UL)
7874 #define CPU_SHPR3_PRI_12_Msk (0xffUL)
7875 /* ====================================================== SYSTICK_CAL ====================================================== */
7876 #define CPU_SYSTICK_CAL_NOREF_Pos (31UL)
7877 #define CPU_SYSTICK_CAL_NOREF_Msk (0x80000000UL)
7878 #define CPU_SYSTICK_CAL_SKEW_Pos (30UL)
7879 #define CPU_SYSTICK_CAL_SKEW_Msk (0x40000000UL)
7880 #define CPU_SYSTICK_CAL_TENMS_Pos (0UL)
7881 #define CPU_SYSTICK_CAL_TENMS_Msk (0xffffffUL)
7882 /* ====================================================== SYSTICK_CS ======================================================= */
7883 #define CPU_SYSTICK_CS_COUNTFLAG_Pos (16UL)
7884 #define CPU_SYSTICK_CS_COUNTFLAG_Msk (0x10000UL)
7885 #define CPU_SYSTICK_CS_CLKSOURCE_Pos (2UL)
7886 #define CPU_SYSTICK_CS_CLKSOURCE_Msk (0x4UL)
7887 #define CPU_SYSTICK_CS_TICKINT_Pos (1UL)
7888 #define CPU_SYSTICK_CS_TICKINT_Msk (0x2UL)
7889 #define CPU_SYSTICK_CS_ENABLE_Pos (0UL)
7890 #define CPU_SYSTICK_CS_ENABLE_Msk (0x1UL)
7891 /* ====================================================== SYSTICK_CUR ====================================================== */
7892 #define CPU_SYSTICK_CUR_CURRENT_Pos (0UL)
7893 #define CPU_SYSTICK_CUR_CURRENT_Msk (0xffffffUL)
7894 /* ====================================================== SYSTICK_RL ======================================================= */
7895 #define CPU_SYSTICK_RL_RELOAD_Pos (0UL)
7896 #define CPU_SYSTICK_RL_RELOAD_Msk (0xffffffUL)
7897 /* ========================================================= VTOR ========================================================== */
7898 #define CPU_VTOR_TBLOFF_Pos (7UL)
7899 #define CPU_VTOR_TBLOFF_Msk (0xffffff80UL)
7902 /* =========================================================================================================================== */
7903 /* ================ DMA ================ */
7904 /* =========================================================================================================================== */
7905 
7906 /* =================================================== ALT_CTRL_BASE_PTR =================================================== */
7907 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Pos (0UL)
7908 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Msk (0xffffffffUL)
7909 /* ========================================================== CFG ========================================================== */
7910 #define DMA_CFG_CHN1_PROT_CTRL_Pos (5UL)
7911 #define DMA_CFG_CHN1_PROT_CTRL_Msk (0xe0UL)
7912 #define DMA_CFG_MASTER_ENABLE_Pos (0UL)
7913 #define DMA_CFG_MASTER_ENABLE_Msk (0x1UL)
7914 /* ==================================================== CHNL_ENABLE_CLR ==================================================== */
7915 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Pos (0UL)
7916 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Msk (0x3fffUL)
7917 /* ==================================================== CHNL_ENABLE_SET ==================================================== */
7918 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos (0UL)
7919 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk (0x3fffUL)
7920 /* =================================================== CHNL_PRI_ALT_CLR ==================================================== */
7921 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos (0UL)
7922 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk (0x3fffUL)
7923 /* =================================================== CHNL_PRI_ALT_SET ==================================================== */
7924 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos (0UL)
7925 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk (0x3fffUL)
7926 /* =================================================== CHNL_PRIORITY_CLR =================================================== */
7927 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Pos (0UL)
7928 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Msk (0x3fffUL)
7929 /* =================================================== CHNL_PRIORITY_SET =================================================== */
7930 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Pos (0UL)
7931 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Msk (0x3fffUL)
7932 /* =================================================== CHNL_REQ_MASK_CLR =================================================== */
7933 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Pos (0UL)
7934 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Msk (0x3fffUL)
7935 /* =================================================== CHNL_REQ_MASK_SET =================================================== */
7936 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Pos (0UL)
7937 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Msk (0x3fffUL)
7938 /* ==================================================== CHNL_SW_REQUEST ==================================================== */
7939 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos (0UL)
7940 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk (0x3fffUL)
7941 /* =================================================== CHNL_USEBURST_CLR =================================================== */
7942 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Pos (0UL)
7943 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Msk (0x3fffUL)
7944 /* =================================================== CHNL_USEBURST_SET =================================================== */
7945 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Pos (0UL)
7946 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Msk (0x3fffUL)
7947 /* ===================================================== CTRL_BASE_PTR ===================================================== */
7948 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos (9UL)
7949 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk (0xfffffe00UL)
7950 /* ======================================================== ERR_CLR ======================================================== */
7951 #define DMA_ERR_CLR_ERR_CLR_Pos (0UL)
7952 #define DMA_ERR_CLR_ERR_CLR_Msk (0x1UL)
7953 /* ======================================================== STATUS ========================================================= */
7954 #define DMA_STATUS_CHNLS_MINUS1_Pos (16UL)
7955 #define DMA_STATUS_CHNLS_MINUS1_Msk (0x1f0000UL)
7956 #define DMA_STATUS_STATE_Pos (4UL)
7957 #define DMA_STATUS_STATE_Msk (0xf0UL)
7958 #define DMA_STATUS_MASTER_ENABLE_Pos (0UL)
7959 #define DMA_STATUS_MASTER_ENABLE_Msk (0x1UL)
7960 /* =================================================== WAITONREQ_STATUS ==================================================== */
7961 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Pos (0UL)
7962 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Msk (0x3fffUL)
7965 /* =========================================================================================================================== */
7966 /* ================ GPT12E ================ */
7967 /* =========================================================================================================================== */
7968 
7969 /* ======================================================== CAPREL ========================================================= */
7970 #define GPT12E_CAPREL_CAPREL_Pos (0UL)
7971 #define GPT12E_CAPREL_CAPREL_Msk (0xffffUL)
7972 /* ========================================================== ID =========================================================== */
7973 #define GPT12E_ID_MOD_REV_Pos (0UL)
7974 #define GPT12E_ID_MOD_REV_Msk (0xffUL)
7975 #define GPT12E_ID_MOD_TYPE_Pos (8UL)
7976 #define GPT12E_ID_MOD_TYPE_Msk (0xff00UL)
7977 /* ========================================================= PISEL ========================================================= */
7978 #define GPT12E_PISEL_IST2IN_Pos (0UL)
7979 #define GPT12E_PISEL_IST2IN_Msk (0x1UL)
7980 #define GPT12E_PISEL_IST2EUD_Pos (1UL)
7981 #define GPT12E_PISEL_IST2EUD_Msk (0x2UL)
7982 #define GPT12E_PISEL_IST3IN_Pos (2UL)
7983 #define GPT12E_PISEL_IST3IN_Msk (0xcUL)
7984 #define GPT12E_PISEL_IST3EUD_Pos (4UL)
7985 #define GPT12E_PISEL_IST3EUD_Msk (0x30UL)
7986 #define GPT12E_PISEL_IST4IN_Pos (6UL)
7987 #define GPT12E_PISEL_IST4IN_Msk (0xc0UL)
7988 #define GPT12E_PISEL_IST4EUD_Pos (8UL)
7989 #define GPT12E_PISEL_IST4EUD_Msk (0x300UL)
7990 #define GPT12E_PISEL_IST5IN_Pos (10UL)
7991 #define GPT12E_PISEL_IST5IN_Msk (0x400UL)
7992 #define GPT12E_PISEL_IST5EUD_Pos (11UL)
7993 #define GPT12E_PISEL_IST5EUD_Msk (0x800UL)
7994 #define GPT12E_PISEL_IST6IN_Pos (12UL)
7995 #define GPT12E_PISEL_IST6IN_Msk (0x1000UL)
7996 #define GPT12E_PISEL_IST6EUD_Pos (13UL)
7997 #define GPT12E_PISEL_IST6EUD_Msk (0x2000UL)
7998 #define GPT12E_PISEL_ISCAPIN_Pos (14UL)
7999 #define GPT12E_PISEL_ISCAPIN_Msk (0xc000UL)
8000 /* ========================================================== T2 =========================================================== */
8001 #define GPT12E_T2_T2_Pos (0UL)
8002 #define GPT12E_T2_T2_Msk (0xffffUL)
8003 /* ========================================================= T2CON ========================================================= */
8004 #define GPT12E_T2CON_T2I_Pos (0UL)
8005 #define GPT12E_T2CON_T2I_Msk (0x7UL)
8006 #define GPT12E_T2CON_T2M_Pos (3UL)
8007 #define GPT12E_T2CON_T2M_Msk (0x38UL)
8008 #define GPT12E_T2CON_T2R_Pos (6UL)
8009 #define GPT12E_T2CON_T2R_Msk (0x40UL)
8010 #define GPT12E_T2CON_T2UD_Pos (7UL)
8011 #define GPT12E_T2CON_T2UD_Msk (0x80UL)
8012 #define GPT12E_T2CON_T2UDE_Pos (8UL)
8013 #define GPT12E_T2CON_T2UDE_Msk (0x100UL)
8014 #define GPT12E_T2CON_T2RC_Pos (9UL)
8015 #define GPT12E_T2CON_T2RC_Msk (0x200UL)
8016 #define GPT12E_T2CON_T2IRDIS_Pos (12UL)
8017 #define GPT12E_T2CON_T2IRDIS_Msk (0x1000UL)
8018 #define GPT12E_T2CON_T2EDGE_Pos (13UL)
8019 #define GPT12E_T2CON_T2EDGE_Msk (0x2000UL)
8020 #define GPT12E_T2CON_T2CHDIR_Pos (14UL)
8021 #define GPT12E_T2CON_T2CHDIR_Msk (0x4000UL)
8022 #define GPT12E_T2CON_T2RDIR_Pos (15UL)
8023 #define GPT12E_T2CON_T2RDIR_Msk (0x8000UL)
8024 /* ========================================================== T3 =========================================================== */
8025 #define GPT12E_T3_T3_Pos (0UL)
8026 #define GPT12E_T3_T3_Msk (0xffffUL)
8027 /* ========================================================= T3CON ========================================================= */
8028 #define GPT12E_T3CON_T3I_Pos (0UL)
8029 #define GPT12E_T3CON_T3I_Msk (0x7UL)
8030 #define GPT12E_T3CON_T3M_Pos (3UL)
8031 #define GPT12E_T3CON_T3M_Msk (0x38UL)
8032 #define GPT12E_T3CON_T3R_Pos (6UL)
8033 #define GPT12E_T3CON_T3R_Msk (0x40UL)
8034 #define GPT12E_T3CON_T3UD_Pos (7UL)
8035 #define GPT12E_T3CON_T3UD_Msk (0x80UL)
8036 #define GPT12E_T3CON_T3UDE_Pos (8UL)
8037 #define GPT12E_T3CON_T3UDE_Msk (0x100UL)
8038 #define GPT12E_T3CON_T3OE_Pos (9UL)
8039 #define GPT12E_T3CON_T3OE_Msk (0x200UL)
8040 #define GPT12E_T3CON_T3OTL_Pos (10UL)
8041 #define GPT12E_T3CON_T3OTL_Msk (0x400UL)
8042 #define GPT12E_T3CON_BPS1_Pos (11UL)
8043 #define GPT12E_T3CON_BPS1_Msk (0x1800UL)
8044 #define GPT12E_T3CON_T3EDGE_Pos (13UL)
8045 #define GPT12E_T3CON_T3EDGE_Msk (0x2000UL)
8046 #define GPT12E_T3CON_T3CHDIR_Pos (14UL)
8047 #define GPT12E_T3CON_T3CHDIR_Msk (0x4000UL)
8048 #define GPT12E_T3CON_T3RDIR_Pos (15UL)
8049 #define GPT12E_T3CON_T3RDIR_Msk (0x8000UL)
8050 /* ========================================================== T4 =========================================================== */
8051 #define GPT12E_T4_T4_Pos (0UL)
8052 #define GPT12E_T4_T4_Msk (0xffffUL)
8053 /* ========================================================= T4CON ========================================================= */
8054 #define GPT12E_T4CON_T4I_Pos (0UL)
8055 #define GPT12E_T4CON_T4I_Msk (0x7UL)
8056 #define GPT12E_T4CON_T4M_Pos (3UL)
8057 #define GPT12E_T4CON_T4M_Msk (0x38UL)
8058 #define GPT12E_T4CON_T4R_Pos (6UL)
8059 #define GPT12E_T4CON_T4R_Msk (0x40UL)
8060 #define GPT12E_T4CON_T4UD_Pos (7UL)
8061 #define GPT12E_T4CON_T4UD_Msk (0x80UL)
8062 #define GPT12E_T4CON_T4UDE_Pos (8UL)
8063 #define GPT12E_T4CON_T4UDE_Msk (0x100UL)
8064 #define GPT12E_T4CON_T4RC_Pos (9UL)
8065 #define GPT12E_T4CON_T4RC_Msk (0x200UL)
8066 #define GPT12E_T4CON_CLRT2EN_Pos (10UL)
8067 #define GPT12E_T4CON_CLRT2EN_Msk (0x400UL)
8068 #define GPT12E_T4CON_CLRT3EN_Pos (11UL)
8069 #define GPT12E_T4CON_CLRT3EN_Msk (0x800UL)
8070 #define GPT12E_T4CON_T4IRDIS_Pos (12UL)
8071 #define GPT12E_T4CON_T4IRDIS_Msk (0x1000UL)
8072 #define GPT12E_T4CON_T4EDGE_Pos (13UL)
8073 #define GPT12E_T4CON_T4EDGE_Msk (0x2000UL)
8074 #define GPT12E_T4CON_T4CHDIR_Pos (14UL)
8075 #define GPT12E_T4CON_T4CHDIR_Msk (0x4000UL)
8076 #define GPT12E_T4CON_T4RDIR_Pos (15UL)
8077 #define GPT12E_T4CON_T4RDIR_Msk (0x8000UL)
8078 /* ========================================================== T5 =========================================================== */
8079 #define GPT12E_T5_T5_Pos (0UL)
8080 #define GPT12E_T5_T5_Msk (0xffffUL)
8081 /* ========================================================= T5CON ========================================================= */
8082 #define GPT12E_T5CON_T5I_Pos (0UL)
8083 #define GPT12E_T5CON_T5I_Msk (0x7UL)
8084 #define GPT12E_T5CON_T5M_Pos (3UL)
8085 #define GPT12E_T5CON_T5M_Msk (0x18UL)
8086 #define GPT12E_T5CON_T5R_Pos (6UL)
8087 #define GPT12E_T5CON_T5R_Msk (0x40UL)
8088 #define GPT12E_T5CON_T5UD_Pos (7UL)
8089 #define GPT12E_T5CON_T5UD_Msk (0x80UL)
8090 #define GPT12E_T5CON_T5UDE_Pos (8UL)
8091 #define GPT12E_T5CON_T5UDE_Msk (0x100UL)
8092 #define GPT12E_T5CON_T5RC_Pos (9UL)
8093 #define GPT12E_T5CON_T5RC_Msk (0x200UL)
8094 #define GPT12E_T5CON_CT3_Pos (10UL)
8095 #define GPT12E_T5CON_CT3_Msk (0x400UL)
8096 #define GPT12E_T5CON_CI_Pos (12UL)
8097 #define GPT12E_T5CON_CI_Msk (0x3000UL)
8098 #define GPT12E_T5CON_T5CLR_Pos (14UL)
8099 #define GPT12E_T5CON_T5CLR_Msk (0x4000UL)
8100 #define GPT12E_T5CON_T5SC_Pos (15UL)
8101 #define GPT12E_T5CON_T5SC_Msk (0x8000UL)
8102 /* ========================================================== T6 =========================================================== */
8103 #define GPT12E_T6_T6_Pos (0UL)
8104 #define GPT12E_T6_T6_Msk (0xffffUL)
8105 /* ========================================================= T6CON ========================================================= */
8106 #define GPT12E_T6CON_T6I_Pos (0UL)
8107 #define GPT12E_T6CON_T6I_Msk (0x7UL)
8108 #define GPT12E_T6CON_T6M_Pos (3UL)
8109 #define GPT12E_T6CON_T6M_Msk (0x38UL)
8110 #define GPT12E_T6CON_T6R_Pos (6UL)
8111 #define GPT12E_T6CON_T6R_Msk (0x40UL)
8112 #define GPT12E_T6CON_T6UD_Pos (7UL)
8113 #define GPT12E_T6CON_T6UD_Msk (0x80UL)
8114 #define GPT12E_T6CON_T6UDE_Pos (8UL)
8115 #define GPT12E_T6CON_T6UDE_Msk (0x100UL)
8116 #define GPT12E_T6CON_T6OE_Pos (9UL)
8117 #define GPT12E_T6CON_T6OE_Msk (0x200UL)
8118 #define GPT12E_T6CON_T6OTL_Pos (10UL)
8119 #define GPT12E_T6CON_T6OTL_Msk (0x400UL)
8120 #define GPT12E_T6CON_BPS2_Pos (11UL)
8121 #define GPT12E_T6CON_BPS2_Msk (0x1800UL)
8122 #define GPT12E_T6CON_T6CLR_Pos (14UL)
8123 #define GPT12E_T6CON_T6CLR_Msk (0x4000UL)
8124 #define GPT12E_T6CON_T6SR_Pos (15UL)
8125 #define GPT12E_T6CON_T6SR_Msk (0x8000UL)
8128 /* =========================================================================================================================== */
8129 /* ================ LIN ================ */
8130 /* =========================================================================================================================== */
8131 
8132 /* ======================================================= CTRL_STS ======================================================== */
8133 #define LIN_CTRL_STS_M_SM_ERR_CLR_Pos (24UL)
8134 #define LIN_CTRL_STS_M_SM_ERR_CLR_Msk (0x1000000UL)
8135 #define LIN_CTRL_STS_HV_MODE_Pos (21UL)
8136 #define LIN_CTRL_STS_HV_MODE_Msk (0x200000UL)
8137 #define LIN_CTRL_STS_MODE_FB_Pos (16UL)
8138 #define LIN_CTRL_STS_MODE_FB_Msk (0x70000UL)
8139 #define LIN_CTRL_STS_FB_SM3_Pos (15UL)
8140 #define LIN_CTRL_STS_FB_SM3_Msk (0x8000UL)
8141 #define LIN_CTRL_STS_FB_SM2_Pos (14UL)
8142 #define LIN_CTRL_STS_FB_SM2_Msk (0x4000UL)
8143 #define LIN_CTRL_STS_FB_SM1_Pos (13UL)
8144 #define LIN_CTRL_STS_FB_SM1_Msk (0x2000UL)
8145 #define LIN_CTRL_STS_SM_Pos (11UL)
8146 #define LIN_CTRL_STS_SM_Msk (0x1800UL)
8147 #define LIN_CTRL_STS_RXD_Pos (10UL)
8148 #define LIN_CTRL_STS_RXD_Msk (0x400UL)
8149 #define LIN_CTRL_STS_TXD_Pos (9UL)
8150 #define LIN_CTRL_STS_TXD_Msk (0x200UL)
8151 #define LIN_CTRL_STS_TXD_TMOUT_STS_Pos (6UL)
8152 #define LIN_CTRL_STS_TXD_TMOUT_STS_Msk (0x40UL)
8153 #define LIN_CTRL_STS_OC_STS_Pos (5UL)
8154 #define LIN_CTRL_STS_OC_STS_Msk (0x20UL)
8155 #define LIN_CTRL_STS_OT_STS_Pos (4UL)
8156 #define LIN_CTRL_STS_OT_STS_Msk (0x10UL)
8157 #define LIN_CTRL_STS_M_SM_ERR_Pos (3UL)
8158 #define LIN_CTRL_STS_M_SM_ERR_Msk (0x8UL)
8159 #define LIN_CTRL_STS_MODE_Pos (1UL)
8160 #define LIN_CTRL_STS_MODE_Msk (0x6UL)
8163 /* =========================================================================================================================== */
8164 /* ================ MF ================ */
8165 /* =========================================================================================================================== */
8166 
8167 /* ==================================================== BEMFC_CTRL_STS ===================================================== */
8168 #define MF_BEMFC_CTRL_STS_PHW_ZC_STS_Pos (18UL)
8169 #define MF_BEMFC_CTRL_STS_PHW_ZC_STS_Msk (0x40000UL)
8170 #define MF_BEMFC_CTRL_STS_PHV_ZC_STS_Pos (17UL)
8171 #define MF_BEMFC_CTRL_STS_PHV_ZC_STS_Msk (0x20000UL)
8172 #define MF_BEMFC_CTRL_STS_PHU_ZC_STS_Pos (16UL)
8173 #define MF_BEMFC_CTRL_STS_PHU_ZC_STS_Msk (0x10000UL)
8174 #define MF_BEMFC_CTRL_STS_CCPOS_INSEL_Pos (12UL)
8175 #define MF_BEMFC_CTRL_STS_CCPOS_INSEL_Msk (0x1000UL)
8176 #define MF_BEMFC_CTRL_STS_PHWCOMP_ON_Pos (10UL)
8177 #define MF_BEMFC_CTRL_STS_PHWCOMP_ON_Msk (0x400UL)
8178 #define MF_BEMFC_CTRL_STS_PHVCOMP_ON_Pos (9UL)
8179 #define MF_BEMFC_CTRL_STS_PHVCOMP_ON_Msk (0x200UL)
8180 #define MF_BEMFC_CTRL_STS_PHUCOMP_ON_Pos (8UL)
8181 #define MF_BEMFC_CTRL_STS_PHUCOMP_ON_Msk (0x100UL)
8182 #define MF_BEMFC_CTRL_STS_GPT12CAPINSW_Pos (5UL)
8183 #define MF_BEMFC_CTRL_STS_GPT12CAPINSW_Msk (0x20UL)
8184 #define MF_BEMFC_CTRL_STS_FILTBYPS_Pos (4UL)
8185 #define MF_BEMFC_CTRL_STS_FILTBYPS_Msk (0x10UL)
8186 #define MF_BEMFC_CTRL_STS_DEMGFILTDIS_Pos (3UL)
8187 #define MF_BEMFC_CTRL_STS_DEMGFILTDIS_Msk (0x8UL)
8188 #define MF_BEMFC_CTRL_STS_PHWCOMP_EN_Pos (2UL)
8189 #define MF_BEMFC_CTRL_STS_PHWCOMP_EN_Msk (0x4UL)
8190 #define MF_BEMFC_CTRL_STS_PHVCOMP_EN_Pos (1UL)
8191 #define MF_BEMFC_CTRL_STS_PHVCOMP_EN_Msk (0x2UL)
8192 #define MF_BEMFC_CTRL_STS_PHUCOMP_EN_Pos (0UL)
8193 #define MF_BEMFC_CTRL_STS_PHUCOMP_EN_Msk (0x1UL)
8194 /* ======================================================= CSA_CTRL ======================================================== */
8195 #define MF_CSA_CTRL_VZERO_Pos (8UL)
8196 #define MF_CSA_CTRL_VZERO_Msk (0x100UL)
8197 #define MF_CSA_CTRL_GAIN_Pos (1UL)
8198 #define MF_CSA_CTRL_GAIN_Msk (0x6UL)
8199 #define MF_CSA_CTRL_EN_Pos (0UL)
8200 #define MF_CSA_CTRL_EN_Msk (0x1UL)
8201 /* ==================================================== P2_ADCSEL_CTRL ===================================================== */
8202 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Pos (10UL)
8203 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Msk (0x400UL)
8204 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Pos (9UL)
8205 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Msk (0x200UL)
8206 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Pos (8UL)
8207 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Msk (0x100UL)
8208 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Pos (0UL)
8209 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Msk (0x1UL)
8210 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Pos (1UL)
8211 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Msk (0x2UL)
8212 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Pos (2UL)
8213 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Msk (0x4UL)
8214 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Pos (3UL)
8215 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Msk (0x8UL)
8216 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Pos (4UL)
8217 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Msk (0x10UL)
8218 /* ======================================================= REF1_STS ======================================================== */
8219 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Pos (5UL)
8220 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Msk (0x20UL)
8221 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Pos (4UL)
8222 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Msk (0x10UL)
8223 /* ======================================================= REF2_CTRL ======================================================= */
8224 #define MF_REF2_CTRL_VREF5V_OV_STS_Pos (3UL)
8225 #define MF_REF2_CTRL_VREF5V_OV_STS_Msk (0x8UL)
8226 #define MF_REF2_CTRL_VREF5V_UV_STS_Pos (2UL)
8227 #define MF_REF2_CTRL_VREF5V_UV_STS_Msk (0x4UL)
8228 #define MF_REF2_CTRL_VREF5V_OVL_STS_Pos (1UL)
8229 #define MF_REF2_CTRL_VREF5V_OVL_STS_Msk (0x2UL)
8230 #define MF_REF2_CTRL_VREF5V_PD_N_Pos (0UL)
8231 #define MF_REF2_CTRL_VREF5V_PD_N_Msk (0x1UL)
8232 /* ==================================================== TEMPSENSE_CTRL ===================================================== */
8233 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Pos (7UL)
8234 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Msk (0x80UL)
8235 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Pos (6UL)
8236 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Msk (0x40UL)
8237 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Pos (5UL)
8238 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Msk (0x20UL)
8239 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Pos (4UL)
8240 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Msk (0x10UL)
8241 /* ====================================================== TRIM_BEMFx ======================================================= */
8242 #define MF_TRIM_BEMFx_BEMF_TFILT_SEL_Pos (8UL)
8243 #define MF_TRIM_BEMFx_BEMF_TFILT_SEL_Msk (0x300UL)
8244 #define MF_TRIM_BEMFx_BEMF_GPT_CAPIN_SEL_Pos (4UL)
8245 #define MF_TRIM_BEMFx_BEMF_GPT_CAPIN_SEL_Msk (0x30UL)
8246 #define MF_TRIM_BEMFx_BEMF_BT_TFILT_SEL_Pos (0UL)
8247 #define MF_TRIM_BEMFx_BEMF_BT_TFILT_SEL_Msk (0x7UL)
8248 /* ===================================================== VMON_SEN_CTRL ===================================================== */
8249 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos (5UL)
8250 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk (0x20UL)
8251 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos (4UL)
8252 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk (0x10UL)
8253 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos (0UL)
8254 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk (0x1UL)
8257 /* =========================================================================================================================== */
8258 /* ================ PMU ================ */
8259 /* =========================================================================================================================== */
8260 
8261 /* ================================================== CNF_CYC_SAMPLE_DEL =================================================== */
8262 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Pos (0UL)
8263 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Msk (0xfUL)
8264 /* ===================================================== CNF_CYC_SENSE ===================================================== */
8265 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Pos (7UL)
8266 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Msk (0x80UL)
8267 #define PMU_CNF_CYC_SENSE_E01_Pos (4UL)
8268 #define PMU_CNF_CYC_SENSE_E01_Msk (0x30UL)
8269 #define PMU_CNF_CYC_SENSE_M03_Pos (0UL)
8270 #define PMU_CNF_CYC_SENSE_M03_Msk (0xfUL)
8271 /* ===================================================== CNF_CYC_WAKE ====================================================== */
8272 #define PMU_CNF_CYC_WAKE_E01_Pos (4UL)
8273 #define PMU_CNF_CYC_WAKE_E01_Msk (0x30UL)
8274 #define PMU_CNF_CYC_WAKE_M03_Pos (0UL)
8275 #define PMU_CNF_CYC_WAKE_M03_Msk (0xfUL)
8276 /* =================================================== CNF_PMU_SETTINGS ==================================================== */
8277 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Pos (7UL)
8278 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Msk (0x80UL)
8279 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Pos (3UL)
8280 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Msk (0x8UL)
8281 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Pos (2UL)
8282 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Msk (0x4UL)
8283 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Pos (1UL)
8284 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Msk (0x2UL)
8285 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Pos (0UL)
8286 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Msk (0x1UL)
8287 /* ====================================================== CNF_RST_TFB ====================================================== */
8288 #define PMU_CNF_RST_TFB_RST_TFB_Pos (0UL)
8289 #define PMU_CNF_RST_TFB_RST_TFB_Msk (0x3UL)
8290 /* ==================================================== CNF_WAKE_FILTER ==================================================== */
8291 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Pos (2UL)
8292 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Msk (0xcUL)
8293 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Pos (1UL)
8294 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Msk (0x2UL)
8295 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Pos (0UL)
8296 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Msk (0x1UL)
8297 /* ======================================================= GPUDATA00 ======================================================= */
8298 #define PMU_GPUDATA00_DATA0_Pos (0UL)
8299 #define PMU_GPUDATA00_DATA0_Msk (0xffUL)
8300 /* ======================================================= GPUDATA01 ======================================================= */
8301 #define PMU_GPUDATA01_DATA1_Pos (0UL)
8302 #define PMU_GPUDATA01_DATA1_Msk (0xffUL)
8303 /* ======================================================= GPUDATA02 ======================================================= */
8304 #define PMU_GPUDATA02_DATA2_Pos (0UL)
8305 #define PMU_GPUDATA02_DATA2_Msk (0xffUL)
8306 /* ======================================================= GPUDATA03 ======================================================= */
8307 #define PMU_GPUDATA03_DATA3_Pos (0UL)
8308 #define PMU_GPUDATA03_DATA3_Msk (0xffUL)
8309 /* ======================================================= GPUDATA04 ======================================================= */
8310 #define PMU_GPUDATA04_DATA4_Pos (0UL)
8311 #define PMU_GPUDATA04_DATA4_Msk (0xffUL)
8312 /* ======================================================= GPUDATA05 ======================================================= */
8313 #define PMU_GPUDATA05_DATA5_Pos (0UL)
8314 #define PMU_GPUDATA05_DATA5_Msk (0xffUL)
8315 /* ====================================================== LIN_WAKE_EN ====================================================== */
8316 #define PMU_LIN_WAKE_EN_LIN_EN_Pos (7UL)
8317 #define PMU_LIN_WAKE_EN_LIN_EN_Msk (0x80UL)
8318 /* ======================================================== MON_CNF ======================================================== */
8319 #define PMU_MON_CNF_STS_Pos (7UL)
8320 #define PMU_MON_CNF_STS_Msk (0x80UL)
8321 #define PMU_MON_CNF_PU_Pos (5UL)
8322 #define PMU_MON_CNF_PU_Msk (0x20UL)
8323 #define PMU_MON_CNF_PD_Pos (4UL)
8324 #define PMU_MON_CNF_PD_Msk (0x10UL)
8325 #define PMU_MON_CNF_CYC_Pos (3UL)
8326 #define PMU_MON_CNF_CYC_Msk (0x8UL)
8327 #define PMU_MON_CNF_RISE_Pos (2UL)
8328 #define PMU_MON_CNF_RISE_Msk (0x4UL)
8329 #define PMU_MON_CNF_FALL_Pos (1UL)
8330 #define PMU_MON_CNF_FALL_Msk (0x2UL)
8331 #define PMU_MON_CNF_EN_Pos (0UL)
8332 #define PMU_MON_CNF_EN_Msk (0x1UL)
8333 /* ==================================================== PMU_RESET_STS1 ===================================================== */
8334 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Pos (7UL)
8335 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Msk (0x80UL)
8336 #define PMU_PMU_RESET_STS1_PMU_PIN_Pos (6UL)
8337 #define PMU_PMU_RESET_STS1_PMU_PIN_Msk (0x40UL)
8338 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Pos (5UL)
8339 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Msk (0x20UL)
8340 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Pos (4UL)
8341 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Msk (0x10UL)
8342 #define PMU_PMU_RESET_STS1_PMU_LPR_Pos (3UL)
8343 #define PMU_PMU_RESET_STS1_PMU_LPR_Msk (0x8UL)
8344 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Pos (2UL)
8345 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Msk (0x4UL)
8346 #define PMU_PMU_RESET_STS1_PMU_WAKE_Pos (1UL)
8347 #define PMU_PMU_RESET_STS1_PMU_WAKE_Msk (0x2UL)
8348 #define PMU_PMU_RESET_STS1_SYS_FAIL_Pos (0UL)
8349 #define PMU_PMU_RESET_STS1_SYS_FAIL_Msk (0x1UL)
8350 /* ==================================================== PMU_RESET_STS2 ===================================================== */
8351 #define PMU_PMU_RESET_STS2_LOCKUP_Pos (2UL)
8352 #define PMU_PMU_RESET_STS2_LOCKUP_Msk (0x4UL)
8353 #define PMU_PMU_RESET_STS2_PMU_SOFT_Pos (1UL)
8354 #define PMU_PMU_RESET_STS2_PMU_SOFT_Msk (0x2UL)
8355 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Pos (0UL)
8356 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Msk (0x1UL)
8357 /* ==================================================== PMU_SUPPLY_STS ===================================================== */
8358 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos (6UL)
8359 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk (0x40UL)
8360 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Pos (5UL)
8361 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Msk (0x20UL)
8362 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Pos (4UL)
8363 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Msk (0x10UL)
8364 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos (2UL)
8365 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk (0x4UL)
8366 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Pos (1UL)
8367 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Msk (0x2UL)
8368 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Pos (0UL)
8369 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Msk (0x1UL)
8370 /* ===================================================== SYS_FAIL_STS ====================================================== */
8371 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Pos (6UL)
8372 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Msk (0x40UL)
8373 #define PMU_SYS_FAIL_STS_SYS_OT_Pos (5UL)
8374 #define PMU_SYS_FAIL_STS_SYS_OT_Msk (0x20UL)
8375 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Pos (3UL)
8376 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Msk (0x8UL)
8377 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Pos (2UL)
8378 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Msk (0x4UL)
8379 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Pos (1UL)
8380 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Msk (0x2UL)
8381 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Pos (0UL)
8382 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Msk (0x1UL)
8383 /* =================================================== SystemStartConfig =================================================== */
8384 #define PMU_SystemStartConfig_MBIST_EN_Pos (0UL)
8385 #define PMU_SystemStartConfig_MBIST_EN_Msk (0x1UL)
8386 /* ====================================================== VDDEXT_CTRL ====================================================== */
8387 #define PMU_VDDEXT_CTRL_STABLE_Pos (7UL)
8388 #define PMU_VDDEXT_CTRL_STABLE_Msk (0x80UL)
8389 #define PMU_VDDEXT_CTRL_OK_Pos (6UL)
8390 #define PMU_VDDEXT_CTRL_OK_Msk (0x40UL)
8391 #define PMU_VDDEXT_CTRL_OVERLOAD_Pos (5UL)
8392 #define PMU_VDDEXT_CTRL_OVERLOAD_Msk (0x20UL)
8393 #define PMU_VDDEXT_CTRL_OVERVOLT_Pos (4UL)
8394 #define PMU_VDDEXT_CTRL_OVERVOLT_Msk (0x10UL)
8395 #define PMU_VDDEXT_CTRL_SHORT_Pos (3UL)
8396 #define PMU_VDDEXT_CTRL_SHORT_Msk (0x8UL)
8397 #define PMU_VDDEXT_CTRL_FAIL_EN_Pos (2UL)
8398 #define PMU_VDDEXT_CTRL_FAIL_EN_Msk (0x4UL)
8399 #define PMU_VDDEXT_CTRL_CYC_EN_Pos (1UL)
8400 #define PMU_VDDEXT_CTRL_CYC_EN_Msk (0x2UL)
8401 #define PMU_VDDEXT_CTRL_ENABLE_Pos (0UL)
8402 #define PMU_VDDEXT_CTRL_ENABLE_Msk (0x1UL)
8403 /* ================================================== WAKE_CONF_GPIO0_CYC ================================================== */
8404 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Pos (4UL)
8405 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Msk (0x10UL)
8406 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Pos (3UL)
8407 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Msk (0x8UL)
8408 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Pos (2UL)
8409 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Msk (0x4UL)
8410 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Pos (1UL)
8411 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Msk (0x2UL)
8412 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Pos (0UL)
8413 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Msk (0x1UL)
8414 /* ================================================= WAKE_CONF_GPIO0_FALL ================================================== */
8415 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Pos (4UL)
8416 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Msk (0x10UL)
8417 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Pos (3UL)
8418 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Msk (0x8UL)
8419 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Pos (2UL)
8420 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Msk (0x4UL)
8421 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Pos (1UL)
8422 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Msk (0x2UL)
8423 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Pos (0UL)
8424 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Msk (0x1UL)
8425 /* ================================================= WAKE_CONF_GPIO0_RISE ================================================== */
8426 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Pos (4UL)
8427 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Msk (0x10UL)
8428 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Pos (3UL)
8429 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Msk (0x8UL)
8430 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Pos (2UL)
8431 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Msk (0x4UL)
8432 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Pos (1UL)
8433 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Msk (0x2UL)
8434 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Pos (0UL)
8435 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Msk (0x1UL)
8436 /* ================================================== WAKE_CONF_GPIO1_CYC ================================================== */
8437 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Pos (4UL)
8438 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Msk (0x10UL)
8439 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Pos (3UL)
8440 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Msk (0x8UL)
8441 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Pos (2UL)
8442 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Msk (0x4UL)
8443 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Pos (1UL)
8444 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Msk (0x2UL)
8445 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Pos (0UL)
8446 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Msk (0x1UL)
8447 /* ================================================= WAKE_CONF_GPIO1_FALL ================================================== */
8448 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Pos (4UL)
8449 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Msk (0x10UL)
8450 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Pos (3UL)
8451 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Msk (0x8UL)
8452 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Pos (2UL)
8453 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Msk (0x4UL)
8454 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Pos (1UL)
8455 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Msk (0x2UL)
8456 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Pos (0UL)
8457 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Msk (0x1UL)
8458 /* ================================================= WAKE_CONF_GPIO1_RISE ================================================== */
8459 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Pos (4UL)
8460 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Msk (0x10UL)
8461 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Pos (3UL)
8462 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Msk (0x8UL)
8463 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Pos (2UL)
8464 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Msk (0x4UL)
8465 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Pos (1UL)
8466 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Msk (0x2UL)
8467 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Pos (0UL)
8468 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Msk (0x1UL)
8469 /* ====================================================== WAKE_STATUS ====================================================== */
8470 #define PMU_WAKE_STATUS_FAIL_Pos (5UL)
8471 #define PMU_WAKE_STATUS_FAIL_Msk (0x20UL)
8472 #define PMU_WAKE_STATUS_CYC_WAKE_Pos (4UL)
8473 #define PMU_WAKE_STATUS_CYC_WAKE_Msk (0x10UL)
8474 #define PMU_WAKE_STATUS_GPIO1_Pos (3UL)
8475 #define PMU_WAKE_STATUS_GPIO1_Msk (0x8UL)
8476 #define PMU_WAKE_STATUS_GPIO0_Pos (2UL)
8477 #define PMU_WAKE_STATUS_GPIO0_Msk (0x4UL)
8478 #define PMU_WAKE_STATUS_MON_WAKE_Pos (1UL)
8479 #define PMU_WAKE_STATUS_MON_WAKE_Msk (0x2UL)
8480 #define PMU_WAKE_STATUS_LIN_WAKE_Pos (0UL)
8481 #define PMU_WAKE_STATUS_LIN_WAKE_Msk (0x1UL)
8482 /* ===================================================== WAKE_STS_FAIL ===================================================== */
8483 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Pos (2UL)
8484 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Msk (0x4UL)
8485 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Pos (0UL)
8486 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Msk (0x1UL)
8487 /* ==================================================== WAKE_STS_GPIO0 ===================================================== */
8488 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Pos (4UL)
8489 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Msk (0x10UL)
8490 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Pos (3UL)
8491 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Msk (0x8UL)
8492 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Pos (2UL)
8493 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Msk (0x4UL)
8494 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Pos (1UL)
8495 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Msk (0x2UL)
8496 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Pos (0UL)
8497 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Msk (0x1UL)
8498 /* ==================================================== WAKE_STS_GPIO1 ===================================================== */
8499 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Pos (4UL)
8500 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Msk (0x10UL)
8501 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Pos (3UL)
8502 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Msk (0x8UL)
8503 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Pos (2UL)
8504 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Msk (0x4UL)
8505 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Pos (1UL)
8506 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Msk (0x2UL)
8507 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Pos (0UL)
8508 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Msk (0x1UL)
8509 /* ===================================================== WAKE_STS_MON ====================================================== */
8510 #define PMU_WAKE_STS_MON_WAKE_STS_Pos (0UL)
8511 #define PMU_WAKE_STS_MON_WAKE_STS_Msk (0x1UL)
8514 /* =========================================================================================================================== */
8515 /* ================ PORT ================ */
8516 /* =========================================================================================================================== */
8517 
8518 /* ====================================================== P0_ALTSEL0 ======================================================= */
8519 #define PORT_P0_ALTSEL0_P0_Pos (0UL)
8520 #define PORT_P0_ALTSEL0_P0_Msk (0x1UL)
8521 #define PORT_P0_ALTSEL0_P1_Pos (1UL)
8522 #define PORT_P0_ALTSEL0_P1_Msk (0x2UL)
8523 #define PORT_P0_ALTSEL0_P2_Pos (2UL)
8524 #define PORT_P0_ALTSEL0_P2_Msk (0x4UL)
8525 #define PORT_P0_ALTSEL0_P3_Pos (3UL)
8526 #define PORT_P0_ALTSEL0_P3_Msk (0x8UL)
8527 #define PORT_P0_ALTSEL0_P4_Pos (4UL)
8528 #define PORT_P0_ALTSEL0_P4_Msk (0x10UL)
8529 /* ====================================================== P0_ALTSEL1 ======================================================= */
8530 #define PORT_P0_ALTSEL1_P0_Pos (0UL)
8531 #define PORT_P0_ALTSEL1_P0_Msk (0x1UL)
8532 #define PORT_P0_ALTSEL1_P1_Pos (1UL)
8533 #define PORT_P0_ALTSEL1_P1_Msk (0x2UL)
8534 #define PORT_P0_ALTSEL1_P2_Pos (2UL)
8535 #define PORT_P0_ALTSEL1_P2_Msk (0x4UL)
8536 #define PORT_P0_ALTSEL1_P3_Pos (3UL)
8537 #define PORT_P0_ALTSEL1_P3_Msk (0x8UL)
8538 #define PORT_P0_ALTSEL1_P4_Pos (4UL)
8539 #define PORT_P0_ALTSEL1_P4_Msk (0x10UL)
8540 /* ======================================================== P0_DATA ======================================================== */
8541 #define PORT_P0_DATA_P0_Pos (0UL)
8542 #define PORT_P0_DATA_P0_Msk (0x1UL)
8543 #define PORT_P0_DATA_P1_Pos (1UL)
8544 #define PORT_P0_DATA_P1_Msk (0x2UL)
8545 #define PORT_P0_DATA_P2_Pos (2UL)
8546 #define PORT_P0_DATA_P2_Msk (0x4UL)
8547 #define PORT_P0_DATA_P3_Pos (3UL)
8548 #define PORT_P0_DATA_P3_Msk (0x8UL)
8549 #define PORT_P0_DATA_P4_Pos (4UL)
8550 #define PORT_P0_DATA_P4_Msk (0x10UL)
8551 /* ======================================================== P0_DIR ========================================================= */
8552 #define PORT_P0_DIR_P0_Pos (0UL)
8553 #define PORT_P0_DIR_P0_Msk (0x1UL)
8554 #define PORT_P0_DIR_P1_Pos (1UL)
8555 #define PORT_P0_DIR_P1_Msk (0x2UL)
8556 #define PORT_P0_DIR_P2_Pos (2UL)
8557 #define PORT_P0_DIR_P2_Msk (0x4UL)
8558 #define PORT_P0_DIR_P3_Pos (3UL)
8559 #define PORT_P0_DIR_P3_Msk (0x8UL)
8560 #define PORT_P0_DIR_P4_Pos (4UL)
8561 #define PORT_P0_DIR_P4_Msk (0x10UL)
8562 /* ========================================================= P0_OD ========================================================= */
8563 #define PORT_P0_OD_P0_Pos (0UL)
8564 #define PORT_P0_OD_P0_Msk (0x1UL)
8565 #define PORT_P0_OD_P1_Pos (1UL)
8566 #define PORT_P0_OD_P1_Msk (0x2UL)
8567 #define PORT_P0_OD_P2_Pos (2UL)
8568 #define PORT_P0_OD_P2_Msk (0x4UL)
8569 #define PORT_P0_OD_P3_Pos (3UL)
8570 #define PORT_P0_OD_P3_Msk (0x8UL)
8571 #define PORT_P0_OD_P4_Pos (4UL)
8572 #define PORT_P0_OD_P4_Msk (0x10UL)
8573 /* ======================================================= P0_PUDEN ======================================================== */
8574 #define PORT_P0_PUDEN_P0_Pos (0UL)
8575 #define PORT_P0_PUDEN_P0_Msk (0x1UL)
8576 #define PORT_P0_PUDEN_P1_Pos (1UL)
8577 #define PORT_P0_PUDEN_P1_Msk (0x2UL)
8578 #define PORT_P0_PUDEN_P2_Pos (2UL)
8579 #define PORT_P0_PUDEN_P2_Msk (0x4UL)
8580 #define PORT_P0_PUDEN_P3_Pos (3UL)
8581 #define PORT_P0_PUDEN_P3_Msk (0x8UL)
8582 #define PORT_P0_PUDEN_P4_Pos (4UL)
8583 #define PORT_P0_PUDEN_P4_Msk (0x10UL)
8584 /* ======================================================= P0_PUDSEL ======================================================= */
8585 #define PORT_P0_PUDSEL_P0_Pos (0UL)
8586 #define PORT_P0_PUDSEL_P0_Msk (0x1UL)
8587 #define PORT_P0_PUDSEL_P1_Pos (1UL)
8588 #define PORT_P0_PUDSEL_P1_Msk (0x2UL)
8589 #define PORT_P0_PUDSEL_P2_Pos (2UL)
8590 #define PORT_P0_PUDSEL_P2_Msk (0x4UL)
8591 #define PORT_P0_PUDSEL_P3_Pos (3UL)
8592 #define PORT_P0_PUDSEL_P3_Msk (0x8UL)
8593 #define PORT_P0_PUDSEL_P4_Pos (4UL)
8594 #define PORT_P0_PUDSEL_P4_Msk (0x10UL)
8595 /* ====================================================== P1_ALTSEL0 ======================================================= */
8596 #define PORT_P1_ALTSEL0_P0_Pos (0UL)
8597 #define PORT_P1_ALTSEL0_P0_Msk (0x1UL)
8598 #define PORT_P1_ALTSEL0_P1_Pos (1UL)
8599 #define PORT_P1_ALTSEL0_P1_Msk (0x2UL)
8600 #define PORT_P1_ALTSEL0_P2_Pos (2UL)
8601 #define PORT_P1_ALTSEL0_P2_Msk (0x4UL)
8602 #define PORT_P1_ALTSEL0_P3_Pos (3UL)
8603 #define PORT_P1_ALTSEL0_P3_Msk (0x8UL)
8604 #define PORT_P1_ALTSEL0_P4_Pos (4UL)
8605 #define PORT_P1_ALTSEL0_P4_Msk (0x10UL)
8606 /* ====================================================== P1_ALTSEL1 ======================================================= */
8607 #define PORT_P1_ALTSEL1_P0_Pos (0UL)
8608 #define PORT_P1_ALTSEL1_P0_Msk (0x1UL)
8609 #define PORT_P1_ALTSEL1_P1_Pos (1UL)
8610 #define PORT_P1_ALTSEL1_P1_Msk (0x2UL)
8611 #define PORT_P1_ALTSEL1_P2_Pos (2UL)
8612 #define PORT_P1_ALTSEL1_P2_Msk (0x4UL)
8613 #define PORT_P1_ALTSEL1_P3_Pos (3UL)
8614 #define PORT_P1_ALTSEL1_P3_Msk (0x8UL)
8615 #define PORT_P1_ALTSEL1_P4_Pos (4UL)
8616 #define PORT_P1_ALTSEL1_P4_Msk (0x10UL)
8617 /* ======================================================== P1_DATA ======================================================== */
8618 #define PORT_P1_DATA_P0_Pos (0UL)
8619 #define PORT_P1_DATA_P0_Msk (0x1UL)
8620 #define PORT_P1_DATA_P1_Pos (1UL)
8621 #define PORT_P1_DATA_P1_Msk (0x2UL)
8622 #define PORT_P1_DATA_P2_Pos (2UL)
8623 #define PORT_P1_DATA_P2_Msk (0x4UL)
8624 #define PORT_P1_DATA_P3_Pos (3UL)
8625 #define PORT_P1_DATA_P3_Msk (0x8UL)
8626 #define PORT_P1_DATA_P4_Pos (4UL)
8627 #define PORT_P1_DATA_P4_Msk (0x10UL)
8628 /* ======================================================== P1_DIR ========================================================= */
8629 #define PORT_P1_DIR_P0_Pos (0UL)
8630 #define PORT_P1_DIR_P0_Msk (0x1UL)
8631 #define PORT_P1_DIR_P1_Pos (1UL)
8632 #define PORT_P1_DIR_P1_Msk (0x2UL)
8633 #define PORT_P1_DIR_P2_Pos (2UL)
8634 #define PORT_P1_DIR_P2_Msk (0x4UL)
8635 #define PORT_P1_DIR_P3_Pos (3UL)
8636 #define PORT_P1_DIR_P3_Msk (0x8UL)
8637 #define PORT_P1_DIR_P4_Pos (4UL)
8638 #define PORT_P1_DIR_P4_Msk (0x10UL)
8639 /* ========================================================= P1_OD ========================================================= */
8640 #define PORT_P1_OD_P0_Pos (1UL)
8641 #define PORT_P1_OD_P0_Msk (0x2UL)
8642 #define PORT_P1_OD_P1_Pos (2UL)
8643 #define PORT_P1_OD_P1_Msk (0x4UL)
8644 #define PORT_P1_OD_P3_P2_Pos (3UL)
8645 #define PORT_P1_OD_P3_P2_Msk (0x8UL)
8646 #define PORT_P1_OD_P4_Pos (4UL)
8647 #define PORT_P1_OD_P4_Msk (0x10UL)
8648 /* ======================================================= P1_PUDEN ======================================================== */
8649 #define PORT_P1_PUDEN_P0_Pos (0UL)
8650 #define PORT_P1_PUDEN_P0_Msk (0x1UL)
8651 #define PORT_P1_PUDEN_P1_Pos (1UL)
8652 #define PORT_P1_PUDEN_P1_Msk (0x2UL)
8653 #define PORT_P1_PUDEN_P2_Pos (2UL)
8654 #define PORT_P1_PUDEN_P2_Msk (0x4UL)
8655 #define PORT_P1_PUDEN_P3_Pos (3UL)
8656 #define PORT_P1_PUDEN_P3_Msk (0x8UL)
8657 #define PORT_P1_PUDEN_P4_Pos (4UL)
8658 #define PORT_P1_PUDEN_P4_Msk (0x10UL)
8659 /* ======================================================= P1_PUDSEL ======================================================= */
8660 #define PORT_P1_PUDSEL_P0_Pos (0UL)
8661 #define PORT_P1_PUDSEL_P0_Msk (0x1UL)
8662 #define PORT_P1_PUDSEL_P1_Pos (1UL)
8663 #define PORT_P1_PUDSEL_P1_Msk (0x2UL)
8664 #define PORT_P1_PUDSEL_P2_Pos (2UL)
8665 #define PORT_P1_PUDSEL_P2_Msk (0x4UL)
8666 #define PORT_P1_PUDSEL_P3_Pos (3UL)
8667 #define PORT_P1_PUDSEL_P3_Msk (0x8UL)
8668 #define PORT_P1_PUDSEL_P4_Pos (4UL)
8669 #define PORT_P1_PUDSEL_P4_Msk (0x10UL)
8670 /* ======================================================== P2_DATA ======================================================== */
8671 #define PORT_P2_DATA_P0_Pos (0UL)
8672 #define PORT_P2_DATA_P0_Msk (0x1UL)
8673 #define PORT_P2_DATA_P2_Pos (2UL)
8674 #define PORT_P2_DATA_P2_Msk (0x4UL)
8675 #define PORT_P2_DATA_P3_Pos (3UL)
8676 #define PORT_P2_DATA_P3_Msk (0x8UL)
8677 #define PORT_P2_DATA_P4_Pos (4UL)
8678 #define PORT_P2_DATA_P4_Msk (0x10UL)
8679 #define PORT_P2_DATA_P5_Pos (5UL)
8680 #define PORT_P2_DATA_P5_Msk (0x20UL)
8681 /* ======================================================== P2_DIR ========================================================= */
8682 #define PORT_P2_DIR_P0_Pos (0UL)
8683 #define PORT_P2_DIR_P0_Msk (0x1UL)
8684 #define PORT_P2_DIR_P2_Pos (2UL)
8685 #define PORT_P2_DIR_P2_Msk (0x4UL)
8686 #define PORT_P2_DIR_P3_Pos (3UL)
8687 #define PORT_P2_DIR_P3_Msk (0x8UL)
8688 #define PORT_P2_DIR_P4_Pos (4UL)
8689 #define PORT_P2_DIR_P4_Msk (0x10UL)
8690 #define PORT_P2_DIR_P5_Pos (5UL)
8691 #define PORT_P2_DIR_P5_Msk (0x20UL)
8692 /* ======================================================= P2_PUDEN ======================================================== */
8693 #define PORT_P2_PUDEN_P0_Pos (0UL)
8694 #define PORT_P2_PUDEN_P0_Msk (0x1UL)
8695 #define PORT_P2_PUDEN_P2_Pos (2UL)
8696 #define PORT_P2_PUDEN_P2_Msk (0x4UL)
8697 #define PORT_P2_PUDEN_P3_Pos (3UL)
8698 #define PORT_P2_PUDEN_P3_Msk (0x8UL)
8699 #define PORT_P2_PUDEN_P4_Pos (4UL)
8700 #define PORT_P2_PUDEN_P4_Msk (0x10UL)
8701 #define PORT_P2_PUDEN_P5_Pos (5UL)
8702 #define PORT_P2_PUDEN_P5_Msk (0x20UL)
8703 /* ======================================================= P2_PUDSEL ======================================================= */
8704 #define PORT_P2_PUDSEL_P0_Pos (0UL)
8705 #define PORT_P2_PUDSEL_P0_Msk (0x1UL)
8706 #define PORT_P2_PUDSEL_P2_Pos (2UL)
8707 #define PORT_P2_PUDSEL_P2_Msk (0x4UL)
8708 #define PORT_P2_PUDSEL_P3_Pos (3UL)
8709 #define PORT_P2_PUDSEL_P3_Msk (0x8UL)
8710 #define PORT_P2_PUDSEL_P4_Pos (4UL)
8711 #define PORT_P2_PUDSEL_P4_Msk (0x10UL)
8712 #define PORT_P2_PUDSEL_P5_Pos (5UL)
8713 #define PORT_P2_PUDSEL_P5_Msk (0x20UL)
8716 /* =========================================================================================================================== */
8717 /* ================ SCU ================ */
8718 /* =========================================================================================================================== */
8719 
8720 /* ======================================================== APCLK1 ========================================================= */
8721 #define SCU_APCLK1_APCLK3SCLR_Pos (7UL)
8722 #define SCU_APCLK1_APCLK3SCLR_Msk (0x80UL)
8723 #define SCU_APCLK1_APCLK3STS_Pos (6UL)
8724 #define SCU_APCLK1_APCLK3STS_Msk (0x40UL)
8725 #define SCU_APCLK1_APCLK1STS_Pos (4UL)
8726 #define SCU_APCLK1_APCLK1STS_Msk (0x30UL)
8727 #define SCU_APCLK1_APCLK1SCLR_Pos (2UL)
8728 #define SCU_APCLK1_APCLK1SCLR_Msk (0x4UL)
8729 #define SCU_APCLK1_APCLK1FAC_Pos (0UL)
8730 #define SCU_APCLK1_APCLK1FAC_Msk (0x3UL)
8731 /* ======================================================== APCLK2 ========================================================= */
8732 #define SCU_APCLK2_APCLK2SCLR_Pos (7UL)
8733 #define SCU_APCLK2_APCLK2SCLR_Msk (0x80UL)
8734 #define SCU_APCLK2_APCLK2STS_Pos (5UL)
8735 #define SCU_APCLK2_APCLK2STS_Msk (0x60UL)
8736 #define SCU_APCLK2_APCLK2FAC_Pos (0UL)
8737 #define SCU_APCLK2_APCLK2FAC_Msk (0x1fUL)
8738 /* ====================================================== APCLK_CTRL1 ====================================================== */
8739 #define SCU_APCLK_CTRL1_CPCLK_DIV_Pos (7UL)
8740 #define SCU_APCLK_CTRL1_CPCLK_DIV_Msk (0x80UL)
8741 #define SCU_APCLK_CTRL1_CPCLK_SEL_Pos (6UL)
8742 #define SCU_APCLK_CTRL1_CPCLK_SEL_Msk (0x40UL)
8743 #define SCU_APCLK_CTRL1_BGCLK_DIV_Pos (5UL)
8744 #define SCU_APCLK_CTRL1_BGCLK_DIV_Msk (0x20UL)
8745 #define SCU_APCLK_CTRL1_BGCLK_SEL_Pos (4UL)
8746 #define SCU_APCLK_CTRL1_BGCLK_SEL_Msk (0x10UL)
8747 #define SCU_APCLK_CTRL1_CLKWDT_IE_Pos (3UL)
8748 #define SCU_APCLK_CTRL1_CLKWDT_IE_Msk (0x8UL)
8749 #define SCU_APCLK_CTRL1_T3CLK_SEL_Pos (2UL)
8750 #define SCU_APCLK_CTRL1_T3CLK_SEL_Msk (0x4UL)
8751 #define SCU_APCLK_CTRL1_APCLK_SET_Pos (1UL)
8752 #define SCU_APCLK_CTRL1_APCLK_SET_Msk (0x2UL)
8753 #define SCU_APCLK_CTRL1_PLL_LOCK_Pos (0UL)
8754 #define SCU_APCLK_CTRL1_PLL_LOCK_Msk (0x1UL)
8755 /* ====================================================== APCLK_CTRL2 ====================================================== */
8756 #define SCU_APCLK_CTRL2_T3CLK_DIV_Pos (2UL)
8757 #define SCU_APCLK_CTRL2_T3CLK_DIV_Msk (0xcUL)
8758 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Pos (0UL)
8759 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Msk (0x3UL)
8760 /* ========================================================= BCON1 ========================================================= */
8761 #define SCU_BCON1_R_Pos (0UL)
8762 #define SCU_BCON1_R_Msk (0x1UL)
8763 #define SCU_BCON1_BRPRE_Pos (1UL)
8764 #define SCU_BCON1_BRPRE_Msk (0xeUL)
8765 /* ========================================================= BCON2 ========================================================= */
8766 #define SCU_BCON2_R_Pos (0UL)
8767 #define SCU_BCON2_R_Msk (0x1UL)
8768 #define SCU_BCON2_BRPRE_Pos (1UL)
8769 #define SCU_BCON2_BRPRE_Msk (0xeUL)
8770 /* ========================================================= BGH1 ========================================================== */
8771 #define SCU_BGH1_BR_VALUE_Pos (0UL)
8772 #define SCU_BGH1_BR_VALUE_Msk (0xffUL)
8773 /* ========================================================= BGH2 ========================================================== */
8774 #define SCU_BGH2_BR_VALUE_Pos (0UL)
8775 #define SCU_BGH2_BR_VALUE_Msk (0xffUL)
8776 /* ========================================================= BGL1 ========================================================== */
8777 #define SCU_BGL1_FD_SEL_Pos (0UL)
8778 #define SCU_BGL1_FD_SEL_Msk (0x1fUL)
8779 #define SCU_BGL1_BR_VALUE_Pos (5UL)
8780 #define SCU_BGL1_BR_VALUE_Msk (0xe0UL)
8781 /* ========================================================= BGL2 ========================================================== */
8782 #define SCU_BGL2_FD_SEL_Pos (0UL)
8783 #define SCU_BGL2_FD_SEL_Msk (0x1fUL)
8784 #define SCU_BGL2_BR_VALUE_Pos (5UL)
8785 #define SCU_BGL2_BR_VALUE_Msk (0xe0UL)
8786 /* ======================================================== CMCON1 ========================================================= */
8787 #define SCU_CMCON1_VCOSEL_Pos (7UL)
8788 #define SCU_CMCON1_VCOSEL_Msk (0x80UL)
8789 #define SCU_CMCON1_K1DIV_Pos (6UL)
8790 #define SCU_CMCON1_K1DIV_Msk (0x40UL)
8791 #define SCU_CMCON1_K2DIV_Pos (4UL)
8792 #define SCU_CMCON1_K2DIV_Msk (0x30UL)
8793 #define SCU_CMCON1_CLKREL_Pos (0UL)
8794 #define SCU_CMCON1_CLKREL_Msk (0xfUL)
8795 /* ======================================================== CMCON2 ========================================================= */
8796 #define SCU_CMCON2_PBA0CLKREL_Pos (0UL)
8797 #define SCU_CMCON2_PBA0CLKREL_Msk (0x1UL)
8798 /* ========================================================= COCON ========================================================= */
8799 #define SCU_COCON_EN_Pos (7UL)
8800 #define SCU_COCON_EN_Msk (0x80UL)
8801 #define SCU_COCON_COUTS1_Pos (6UL)
8802 #define SCU_COCON_COUTS1_Msk (0x40UL)
8803 #define SCU_COCON_TLEN_Pos (5UL)
8804 #define SCU_COCON_TLEN_Msk (0x20UL)
8805 #define SCU_COCON_COUTS0_Pos (4UL)
8806 #define SCU_COCON_COUTS0_Msk (0x10UL)
8807 #define SCU_COCON_COREL_Pos (0UL)
8808 #define SCU_COCON_COREL_Msk (0xfUL)
8809 /* ======================================================== DMAIEN1 ======================================================== */
8810 #define SCU_DMAIEN1_CH8IE_Pos (7UL)
8811 #define SCU_DMAIEN1_CH8IE_Msk (0x80UL)
8812 #define SCU_DMAIEN1_CH7IE_Pos (6UL)
8813 #define SCU_DMAIEN1_CH7IE_Msk (0x40UL)
8814 #define SCU_DMAIEN1_CH6IE_Pos (5UL)
8815 #define SCU_DMAIEN1_CH6IE_Msk (0x20UL)
8816 #define SCU_DMAIEN1_CH5IE_Pos (4UL)
8817 #define SCU_DMAIEN1_CH5IE_Msk (0x10UL)
8818 #define SCU_DMAIEN1_CH4IE_Pos (3UL)
8819 #define SCU_DMAIEN1_CH4IE_Msk (0x8UL)
8820 #define SCU_DMAIEN1_CH3IE_Pos (2UL)
8821 #define SCU_DMAIEN1_CH3IE_Msk (0x4UL)
8822 #define SCU_DMAIEN1_CH2IE_Pos (1UL)
8823 #define SCU_DMAIEN1_CH2IE_Msk (0x2UL)
8824 #define SCU_DMAIEN1_CH1IE_Pos (0UL)
8825 #define SCU_DMAIEN1_CH1IE_Msk (0x1UL)
8826 /* ======================================================== DMAIEN2 ======================================================== */
8827 #define SCU_DMAIEN2_SDADCIE_Pos (6UL)
8828 #define SCU_DMAIEN2_SDADCIE_Msk (0x40UL)
8829 #define SCU_DMAIEN2_GPT12IE_Pos (5UL)
8830 #define SCU_DMAIEN2_GPT12IE_Msk (0x20UL)
8831 #define SCU_DMAIEN2_SSCRXIE_Pos (4UL)
8832 #define SCU_DMAIEN2_SSCRXIE_Msk (0x10UL)
8833 #define SCU_DMAIEN2_SSCTXIE_Pos (3UL)
8834 #define SCU_DMAIEN2_SSCTXIE_Msk (0x8UL)
8835 #define SCU_DMAIEN2_TRSEQ2RDYIE_Pos (2UL)
8836 #define SCU_DMAIEN2_TRSEQ2RDYIE_Msk (0x4UL)
8837 #define SCU_DMAIEN2_TRSEQ1RDYIE_Pos (1UL)
8838 #define SCU_DMAIEN2_TRSEQ1RDYIE_Msk (0x2UL)
8839 #define SCU_DMAIEN2_TRERRIE_Pos (0UL)
8840 #define SCU_DMAIEN2_TRERRIE_Msk (0x1UL)
8841 /* ======================================================== DMAIRC1 ======================================================== */
8842 #define SCU_DMAIRC1_CH8_Pos (7UL)
8843 #define SCU_DMAIRC1_CH8_Msk (0x80UL)
8844 #define SCU_DMAIRC1_CH7_Pos (6UL)
8845 #define SCU_DMAIRC1_CH7_Msk (0x40UL)
8846 #define SCU_DMAIRC1_CH6_Pos (5UL)
8847 #define SCU_DMAIRC1_CH6_Msk (0x20UL)
8848 #define SCU_DMAIRC1_CH5_Pos (4UL)
8849 #define SCU_DMAIRC1_CH5_Msk (0x10UL)
8850 #define SCU_DMAIRC1_CH4_Pos (3UL)
8851 #define SCU_DMAIRC1_CH4_Msk (0x8UL)
8852 #define SCU_DMAIRC1_CH3_Pos (2UL)
8853 #define SCU_DMAIRC1_CH3_Msk (0x4UL)
8854 #define SCU_DMAIRC1_CH2_Pos (1UL)
8855 #define SCU_DMAIRC1_CH2_Msk (0x2UL)
8856 #define SCU_DMAIRC1_CH1_Pos (0UL)
8857 #define SCU_DMAIRC1_CH1_Msk (0x1UL)
8858 /* ====================================================== DMAIRC1CLR ======================================================= */
8859 #define SCU_DMAIRC1CLR_CH8C_Pos (7UL)
8860 #define SCU_DMAIRC1CLR_CH8C_Msk (0x80UL)
8861 #define SCU_DMAIRC1CLR_CH7C_Pos (6UL)
8862 #define SCU_DMAIRC1CLR_CH7C_Msk (0x40UL)
8863 #define SCU_DMAIRC1CLR_CH6C_Pos (5UL)
8864 #define SCU_DMAIRC1CLR_CH6C_Msk (0x20UL)
8865 #define SCU_DMAIRC1CLR_CH5C_Pos (4UL)
8866 #define SCU_DMAIRC1CLR_CH5C_Msk (0x10UL)
8867 #define SCU_DMAIRC1CLR_CH4C_Pos (3UL)
8868 #define SCU_DMAIRC1CLR_CH4C_Msk (0x8UL)
8869 #define SCU_DMAIRC1CLR_CH3C_Pos (2UL)
8870 #define SCU_DMAIRC1CLR_CH3C_Msk (0x4UL)
8871 #define SCU_DMAIRC1CLR_CH2C_Pos (1UL)
8872 #define SCU_DMAIRC1CLR_CH2C_Msk (0x2UL)
8873 #define SCU_DMAIRC1CLR_CH1C_Pos (0UL)
8874 #define SCU_DMAIRC1CLR_CH1C_Msk (0x1UL)
8875 /* ======================================================== DMAIRC2 ======================================================== */
8876 #define SCU_DMAIRC2_SDADC_Pos (6UL)
8877 #define SCU_DMAIRC2_SDADC_Msk (0x40UL)
8878 #define SCU_DMAIRC2_GPT12_Pos (5UL)
8879 #define SCU_DMAIRC2_GPT12_Msk (0x20UL)
8880 #define SCU_DMAIRC2_SSC2RDY_Pos (4UL)
8881 #define SCU_DMAIRC2_SSC2RDY_Msk (0x10UL)
8882 #define SCU_DMAIRC2_SSC1RDY_Pos (3UL)
8883 #define SCU_DMAIRC2_SSC1RDY_Msk (0x8UL)
8884 #define SCU_DMAIRC2_TRSEQ2DY_Pos (2UL)
8885 #define SCU_DMAIRC2_TRSEQ2DY_Msk (0x4UL)
8886 #define SCU_DMAIRC2_TRSEQ1DY_Pos (1UL)
8887 #define SCU_DMAIRC2_TRSEQ1DY_Msk (0x2UL)
8888 #define SCU_DMAIRC2_STRDY_Pos (0UL)
8889 #define SCU_DMAIRC2_STRDY_Msk (0x1UL)
8890 /* ====================================================== DMAIRC2CLR ======================================================= */
8891 #define SCU_DMAIRC2CLR_SDADCC_Pos (6UL)
8892 #define SCU_DMAIRC2CLR_SDADCC_Msk (0x40UL)
8893 #define SCU_DMAIRC2CLR_GPT12C_Pos (5UL)
8894 #define SCU_DMAIRC2CLR_GPT12C_Msk (0x20UL)
8895 #define SCU_DMAIRC2CLR_SSC2C_Pos (4UL)
8896 #define SCU_DMAIRC2CLR_SSC2C_Msk (0x10UL)
8897 #define SCU_DMAIRC2CLR_SSC1C_Pos (3UL)
8898 #define SCU_DMAIRC2CLR_SSC1C_Msk (0x8UL)
8899 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos (2UL)
8900 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk (0x4UL)
8901 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos (1UL)
8902 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk (0x2UL)
8903 /* ======================================================= DMASRCCLR ======================================================= */
8904 #define SCU_DMASRCCLR_GPT12_T3C_Pos (7UL)
8905 #define SCU_DMASRCCLR_GPT12_T3C_Msk (0x80UL)
8906 #define SCU_DMASRCCLR_SSCRXC_Pos (6UL)
8907 #define SCU_DMASRCCLR_SSCRXC_Msk (0x40UL)
8908 #define SCU_DMASRCCLR_SSCTXC_Pos (5UL)
8909 #define SCU_DMASRCCLR_SSCTXC_Msk (0x20UL)
8910 /* ======================================================= DMASRCSEL ======================================================= */
8911 #define SCU_DMASRCSEL_GPT12_T3_Pos (7UL)
8912 #define SCU_DMASRCSEL_GPT12_T3_Msk (0x80UL)
8913 #define SCU_DMASRCSEL_SSCRX_Pos (6UL)
8914 #define SCU_DMASRCSEL_SSCRX_Msk (0x40UL)
8915 #define SCU_DMASRCSEL_SSCTX_Pos (5UL)
8916 #define SCU_DMASRCSEL_SSCTX_Msk (0x20UL)
8917 #define SCU_DMASRCSEL_T12PM_DMAEN_Pos (3UL)
8918 #define SCU_DMASRCSEL_T12PM_DMAEN_Msk (0x8UL)
8919 #define SCU_DMASRCSEL_T12ZM_DMAEN_Pos (2UL)
8920 #define SCU_DMASRCSEL_T12ZM_DMAEN_Msk (0x4UL)
8921 #define SCU_DMASRCSEL_SSCRXSRCSEL_Pos (1UL)
8922 #define SCU_DMASRCSEL_SSCRXSRCSEL_Msk (0x2UL)
8923 #define SCU_DMASRCSEL_SSCTXSRCSEL_Pos (0UL)
8924 #define SCU_DMASRCSEL_SSCTXSRCSEL_Msk (0x1UL)
8925 /* ====================================================== DMASRCSEL2 ======================================================= */
8926 #define SCU_DMASRCSEL2_GPT12_DMAEN_Pos (0UL)
8927 #define SCU_DMASRCSEL2_GPT12_DMAEN_Msk (0x3UL)
8928 /* ======================================================== EDCCON ========================================================= */
8929 #define SCU_EDCCON_NVMIE_Pos (2UL)
8930 #define SCU_EDCCON_NVMIE_Msk (0x4UL)
8931 #define SCU_EDCCON_RIE_Pos (0UL)
8932 #define SCU_EDCCON_RIE_Msk (0x1UL)
8933 /* ======================================================== EDCSCLR ======================================================== */
8934 #define SCU_EDCSCLR_RSBEC_Pos (4UL)
8935 #define SCU_EDCSCLR_RSBEC_Msk (0x10UL)
8936 #define SCU_EDCSCLR_NVMDBEC_Pos (2UL)
8937 #define SCU_EDCSCLR_NVMDBEC_Msk (0x4UL)
8938 #define SCU_EDCSCLR_RDBEC_Pos (0UL)
8939 #define SCU_EDCSCLR_RDBEC_Msk (0x1UL)
8940 /* ======================================================== EDCSTAT ======================================================== */
8941 #define SCU_EDCSTAT_RSBE_Pos (4UL)
8942 #define SCU_EDCSTAT_RSBE_Msk (0x10UL)
8943 #define SCU_EDCSTAT_NVMDBE_Pos (2UL)
8944 #define SCU_EDCSTAT_NVMDBE_Msk (0x4UL)
8945 #define SCU_EDCSTAT_RDBE_Pos (0UL)
8946 #define SCU_EDCSTAT_RDBE_Msk (0x1UL)
8947 /* ======================================================== EXICON0 ======================================================== */
8948 #define SCU_EXICON0_MON_Trig_Sel_Pos (6UL)
8949 #define SCU_EXICON0_MON_Trig_Sel_Msk (0xc0UL)
8950 #define SCU_EXICON0_EXINT2_Pos (4UL)
8951 #define SCU_EXICON0_EXINT2_Msk (0x30UL)
8952 #define SCU_EXICON0_EXINT1_Pos (2UL)
8953 #define SCU_EXICON0_EXINT1_Msk (0xcUL)
8954 #define SCU_EXICON0_EXINT0_Pos (0UL)
8955 #define SCU_EXICON0_EXINT0_Msk (0x3UL)
8956 /* ======================================================= GPT12ICLR ======================================================= */
8957 #define SCU_GPT12ICLR_CRC_Pos (5UL)
8958 #define SCU_GPT12ICLR_CRC_Msk (0x20UL)
8959 #define SCU_GPT12ICLR_T6C_Pos (4UL)
8960 #define SCU_GPT12ICLR_T6C_Msk (0x10UL)
8961 #define SCU_GPT12ICLR_T5C_Pos (3UL)
8962 #define SCU_GPT12ICLR_T5C_Msk (0x8UL)
8963 #define SCU_GPT12ICLR_T4C_Pos (2UL)
8964 #define SCU_GPT12ICLR_T4C_Msk (0x4UL)
8965 #define SCU_GPT12ICLR_T3C_Pos (1UL)
8966 #define SCU_GPT12ICLR_T3C_Msk (0x2UL)
8967 #define SCU_GPT12ICLR_T2C_Pos (0UL)
8968 #define SCU_GPT12ICLR_T2C_Msk (0x1UL)
8969 /* ======================================================= GPT12IEN ======================================================== */
8970 #define SCU_GPT12IEN_CRIE_Pos (5UL)
8971 #define SCU_GPT12IEN_CRIE_Msk (0x20UL)
8972 #define SCU_GPT12IEN_T6IE_Pos (4UL)
8973 #define SCU_GPT12IEN_T6IE_Msk (0x10UL)
8974 #define SCU_GPT12IEN_T5IE_Pos (3UL)
8975 #define SCU_GPT12IEN_T5IE_Msk (0x8UL)
8976 #define SCU_GPT12IEN_T4IE_Pos (2UL)
8977 #define SCU_GPT12IEN_T4IE_Msk (0x4UL)
8978 #define SCU_GPT12IEN_T3IE_Pos (1UL)
8979 #define SCU_GPT12IEN_T3IE_Msk (0x2UL)
8980 #define SCU_GPT12IEN_T2IE_Pos (0UL)
8981 #define SCU_GPT12IEN_T2IE_Msk (0x1UL)
8982 /* ======================================================= GPT12IRC ======================================================== */
8983 #define SCU_GPT12IRC_CR_Pos (5UL)
8984 #define SCU_GPT12IRC_CR_Msk (0x20UL)
8985 #define SCU_GPT12IRC_T6_Pos (4UL)
8986 #define SCU_GPT12IRC_T6_Msk (0x10UL)
8987 #define SCU_GPT12IRC_T5_Pos (3UL)
8988 #define SCU_GPT12IRC_T5_Msk (0x8UL)
8989 #define SCU_GPT12IRC_T4_Pos (2UL)
8990 #define SCU_GPT12IRC_T4_Msk (0x4UL)
8991 #define SCU_GPT12IRC_T3_Pos (1UL)
8992 #define SCU_GPT12IRC_T3_Msk (0x2UL)
8993 #define SCU_GPT12IRC_T2_Pos (0UL)
8994 #define SCU_GPT12IRC_T2_Msk (0x1UL)
8995 /* ====================================================== GPT12PISEL ======================================================= */
8996 #define SCU_GPT12PISEL_T3_GPT12_SEL_Pos (5UL)
8997 #define SCU_GPT12PISEL_T3_GPT12_SEL_Msk (0x20UL)
8998 #define SCU_GPT12PISEL_TRIG_CONF_Pos (4UL)
8999 #define SCU_GPT12PISEL_TRIG_CONF_Msk (0x10UL)
9000 #define SCU_GPT12PISEL_GPT12_Pos (0UL)
9001 #define SCU_GPT12PISEL_GPT12_Msk (0xfUL)
9002 /* ========================================================== ID =========================================================== */
9003 #define SCU_ID_PRODID_Pos (3UL)
9004 #define SCU_ID_PRODID_Msk (0xf8UL)
9005 #define SCU_ID_VERID_Pos (0UL)
9006 #define SCU_ID_VERID_Msk (0x7UL)
9007 /* ========================================================= IEN0 ========================================================== */
9008 #define SCU_IEN0_EA_Pos (7UL)
9009 #define SCU_IEN0_EA_Msk (0x80UL)
9010 /* ======================================================== IRCON0 ========================================================= */
9011 #define SCU_IRCON0_MONF_Pos (7UL)
9012 #define SCU_IRCON0_MONF_Msk (0x80UL)
9013 #define SCU_IRCON0_MONR_Pos (6UL)
9014 #define SCU_IRCON0_MONR_Msk (0x40UL)
9015 #define SCU_IRCON0_EXINT2F_Pos (5UL)
9016 #define SCU_IRCON0_EXINT2F_Msk (0x20UL)
9017 #define SCU_IRCON0_EXINT2R_Pos (4UL)
9018 #define SCU_IRCON0_EXINT2R_Msk (0x10UL)
9019 #define SCU_IRCON0_EXINT1F_Pos (3UL)
9020 #define SCU_IRCON0_EXINT1F_Msk (0x8UL)
9021 #define SCU_IRCON0_EXINT1R_Pos (2UL)
9022 #define SCU_IRCON0_EXINT1R_Msk (0x4UL)
9023 #define SCU_IRCON0_EXINT0F_Pos (1UL)
9024 #define SCU_IRCON0_EXINT0F_Msk (0x2UL)
9025 #define SCU_IRCON0_EXINT0R_Pos (0UL)
9026 #define SCU_IRCON0_EXINT0R_Msk (0x1UL)
9027 /* ======================================================= IRCON0CLR ======================================================= */
9028 #define SCU_IRCON0CLR_MONFC_Pos (7UL)
9029 #define SCU_IRCON0CLR_MONFC_Msk (0x80UL)
9030 #define SCU_IRCON0CLR_MONRC_Pos (6UL)
9031 #define SCU_IRCON0CLR_MONRC_Msk (0x40UL)
9032 #define SCU_IRCON0CLR_EXINT2FC_Pos (5UL)
9033 #define SCU_IRCON0CLR_EXINT2FC_Msk (0x20UL)
9034 #define SCU_IRCON0CLR_EXINT2RC_Pos (4UL)
9035 #define SCU_IRCON0CLR_EXINT2RC_Msk (0x10UL)
9036 #define SCU_IRCON0CLR_EXINT1FC_Pos (3UL)
9037 #define SCU_IRCON0CLR_EXINT1FC_Msk (0x8UL)
9038 #define SCU_IRCON0CLR_EXINT1RC_Pos (2UL)
9039 #define SCU_IRCON0CLR_EXINT1RC_Msk (0x4UL)
9040 #define SCU_IRCON0CLR_EXINT0FC_Pos (1UL)
9041 #define SCU_IRCON0CLR_EXINT0FC_Msk (0x2UL)
9042 #define SCU_IRCON0CLR_EXINT0RC_Pos (0UL)
9043 #define SCU_IRCON0CLR_EXINT0RC_Msk (0x1UL)
9044 /* ======================================================== IRCON1 ========================================================= */
9045 #define SCU_IRCON1_RIR_Pos (2UL)
9046 #define SCU_IRCON1_RIR_Msk (0x4UL)
9047 #define SCU_IRCON1_TIR_Pos (1UL)
9048 #define SCU_IRCON1_TIR_Msk (0x2UL)
9049 #define SCU_IRCON1_EIR_Pos (0UL)
9050 #define SCU_IRCON1_EIR_Msk (0x1UL)
9051 /* ======================================================= IRCON1CLR ======================================================= */
9052 #define SCU_IRCON1CLR_RIRC_Pos (2UL)
9053 #define SCU_IRCON1CLR_RIRC_Msk (0x4UL)
9054 #define SCU_IRCON1CLR_TIRC_Pos (1UL)
9055 #define SCU_IRCON1CLR_TIRC_Msk (0x2UL)
9056 #define SCU_IRCON1CLR_EIRC_Pos (0UL)
9057 #define SCU_IRCON1CLR_EIRC_Msk (0x1UL)
9058 /* ======================================================== IRCON2 ========================================================= */
9059 #define SCU_IRCON2_RIR_Pos (2UL)
9060 #define SCU_IRCON2_RIR_Msk (0x4UL)
9061 #define SCU_IRCON2_TIR_Pos (1UL)
9062 #define SCU_IRCON2_TIR_Msk (0x2UL)
9063 #define SCU_IRCON2_EIR_Pos (0UL)
9064 #define SCU_IRCON2_EIR_Msk (0x1UL)
9065 /* ======================================================= IRCON2CLR ======================================================= */
9066 #define SCU_IRCON2CLR_RIRC_Pos (2UL)
9067 #define SCU_IRCON2CLR_RIRC_Msk (0x4UL)
9068 #define SCU_IRCON2CLR_TIRC_Pos (1UL)
9069 #define SCU_IRCON2CLR_TIRC_Msk (0x2UL)
9070 #define SCU_IRCON2CLR_EIRC_Pos (0UL)
9071 #define SCU_IRCON2CLR_EIRC_Msk (0x1UL)
9072 /* ======================================================== IRCON3 ========================================================= */
9073 #define SCU_IRCON3_CCU6SR1_Pos (4UL)
9074 #define SCU_IRCON3_CCU6SR1_Msk (0x10UL)
9075 #define SCU_IRCON3_CCU6SR0_Pos (0UL)
9076 #define SCU_IRCON3_CCU6SR0_Msk (0x1UL)
9077 /* ======================================================= IRCON3CLR ======================================================= */
9078 #define SCU_IRCON3CLR_CCU6SR1C_Pos (4UL)
9079 #define SCU_IRCON3CLR_CCU6SR1C_Msk (0x10UL)
9080 #define SCU_IRCON3CLR_CCU6SR0C_Pos (0UL)
9081 #define SCU_IRCON3CLR_CCU6SR0C_Msk (0x1UL)
9082 /* ======================================================== IRCON4 ========================================================= */
9083 #define SCU_IRCON4_CCU6SR3_Pos (4UL)
9084 #define SCU_IRCON4_CCU6SR3_Msk (0x10UL)
9085 #define SCU_IRCON4_CCU6SR2_Pos (0UL)
9086 #define SCU_IRCON4_CCU6SR2_Msk (0x1UL)
9087 /* ======================================================= IRCON4CLR ======================================================= */
9088 #define SCU_IRCON4CLR_CCU6SR3C_Pos (4UL)
9089 #define SCU_IRCON4CLR_CCU6SR3C_Msk (0x10UL)
9090 #define SCU_IRCON4CLR_CCU6SR2C_Pos (0UL)
9091 #define SCU_IRCON4CLR_CCU6SR2C_Msk (0x1UL)
9092 /* ======================================================== LINSCLR ======================================================== */
9093 #define SCU_LINSCLR_BRKC_Pos (3UL)
9094 #define SCU_LINSCLR_BRKC_Msk (0x8UL)
9095 #define SCU_LINSCLR_EOFSYNC_Pos (4UL)
9096 #define SCU_LINSCLR_EOFSYNC_Msk (0x10UL)
9097 #define SCU_LINSCLR_ERRSYNC_Pos (5UL)
9098 #define SCU_LINSCLR_ERRSYNC_Msk (0x20UL)
9099 /* ========================================================= LINST ========================================================= */
9100 #define SCU_LINST_BRDIS_Pos (0UL)
9101 #define SCU_LINST_BRDIS_Msk (0x1UL)
9102 #define SCU_LINST_BGSEL_Pos (1UL)
9103 #define SCU_LINST_BGSEL_Msk (0x6UL)
9104 #define SCU_LINST_BRK_Pos (3UL)
9105 #define SCU_LINST_BRK_Msk (0x8UL)
9106 #define SCU_LINST_EOFSYN_Pos (4UL)
9107 #define SCU_LINST_EOFSYN_Msk (0x10UL)
9108 #define SCU_LINST_ERRSYN_Pos (5UL)
9109 #define SCU_LINST_ERRSYN_Msk (0x20UL)
9110 #define SCU_LINST_SYNEN_Pos (6UL)
9111 #define SCU_LINST_SYNEN_Msk (0x40UL)
9112 /* ====================================================== MEM_ACC_STS ====================================================== */
9113 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Pos (6UL)
9114 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Msk (0x40UL)
9115 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Pos (5UL)
9116 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Msk (0x20UL)
9117 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Pos (4UL)
9118 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Msk (0x10UL)
9119 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Pos (3UL)
9120 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Msk (0x8UL)
9121 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Pos (2UL)
9122 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Msk (0x4UL)
9123 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Pos (1UL)
9124 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Msk (0x2UL)
9125 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Pos (0UL)
9126 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Msk (0x1UL)
9127 /* ======================================================== MEMSTAT ======================================================== */
9128 #define SCU_MEMSTAT_SASTATUS_Pos (6UL)
9129 #define SCU_MEMSTAT_SASTATUS_Msk (0xc0UL)
9130 #define SCU_MEMSTAT_SECTORINFO_Pos (0UL)
9131 #define SCU_MEMSTAT_SECTORINFO_Msk (0x3fUL)
9132 /* ======================================================== MODIEN1 ======================================================== */
9133 #define SCU_MODIEN1_TIEN1_Pos (7UL)
9134 #define SCU_MODIEN1_TIEN1_Msk (0x80UL)
9135 #define SCU_MODIEN1_RIEN1_Pos (6UL)
9136 #define SCU_MODIEN1_RIEN1_Msk (0x40UL)
9137 #define SCU_MODIEN1_RIREN1_Pos (2UL)
9138 #define SCU_MODIEN1_RIREN1_Msk (0x4UL)
9139 #define SCU_MODIEN1_TIREN1_Pos (1UL)
9140 #define SCU_MODIEN1_TIREN1_Msk (0x2UL)
9141 #define SCU_MODIEN1_EIREN1_Pos (0UL)
9142 #define SCU_MODIEN1_EIREN1_Msk (0x1UL)
9143 /* ======================================================== MODIEN2 ======================================================== */
9144 #define SCU_MODIEN2_TIEN2_Pos (7UL)
9145 #define SCU_MODIEN2_TIEN2_Msk (0x80UL)
9146 #define SCU_MODIEN2_RIEN2_Pos (6UL)
9147 #define SCU_MODIEN2_RIEN2_Msk (0x40UL)
9148 #define SCU_MODIEN2_EXINT2_EN_Pos (5UL)
9149 #define SCU_MODIEN2_EXINT2_EN_Msk (0x20UL)
9150 #define SCU_MODIEN2_RIREN2_Pos (2UL)
9151 #define SCU_MODIEN2_RIREN2_Msk (0x4UL)
9152 #define SCU_MODIEN2_TIREN2_Pos (1UL)
9153 #define SCU_MODIEN2_TIREN2_Msk (0x2UL)
9154 #define SCU_MODIEN2_EIREN2_Pos (0UL)
9155 #define SCU_MODIEN2_EIREN2_Msk (0x1UL)
9156 /* ======================================================== MODIEN3 ======================================================== */
9157 #define SCU_MODIEN3_MONSTS_Pos (5UL)
9158 #define SCU_MODIEN3_MONSTS_Msk (0x20UL)
9159 #define SCU_MODIEN3_MONIE_Pos (4UL)
9160 #define SCU_MODIEN3_MONIE_Msk (0x10UL)
9161 #define SCU_MODIEN3_IE0_Pos (0UL)
9162 #define SCU_MODIEN3_IE0_Msk (0x1UL)
9163 /* ======================================================== MODIEN4 ======================================================== */
9164 #define SCU_MODIEN4_IE1_Pos (0UL)
9165 #define SCU_MODIEN4_IE1_Msk (0x1UL)
9166 /* ======================================================= MODPISEL ======================================================== */
9167 #define SCU_MODPISEL_U_TX_CONDIS_Pos (7UL)
9168 #define SCU_MODPISEL_U_TX_CONDIS_Msk (0x80UL)
9169 #define SCU_MODPISEL_URIOS1_Pos (6UL)
9170 #define SCU_MODPISEL_URIOS1_Msk (0x40UL)
9171 #define SCU_MODPISEL_EXINT2IS_Pos (4UL)
9172 #define SCU_MODPISEL_EXINT2IS_Msk (0x30UL)
9173 #define SCU_MODPISEL_EXINT1IS_Pos (2UL)
9174 #define SCU_MODPISEL_EXINT1IS_Msk (0xcUL)
9175 #define SCU_MODPISEL_EXINT0IS_Pos (0UL)
9176 #define SCU_MODPISEL_EXINT0IS_Msk (0x3UL)
9177 /* ======================================================= MODPISEL1 ======================================================= */
9178 #define SCU_MODPISEL1_T21EXCON_Pos (7UL)
9179 #define SCU_MODPISEL1_T21EXCON_Msk (0x80UL)
9180 #define SCU_MODPISEL1_T2EXCON_Pos (6UL)
9181 #define SCU_MODPISEL1_T2EXCON_Msk (0x40UL)
9182 #define SCU_MODPISEL1_GPT12CAPINB_Pos (0UL)
9183 #define SCU_MODPISEL1_GPT12CAPINB_Msk (0x1UL)
9184 /* ======================================================= MODPISEL2 ======================================================= */
9185 #define SCU_MODPISEL2_T21EXIS_Pos (6UL)
9186 #define SCU_MODPISEL2_T21EXIS_Msk (0xc0UL)
9187 #define SCU_MODPISEL2_T2EXIS_Pos (4UL)
9188 #define SCU_MODPISEL2_T2EXIS_Msk (0x30UL)
9189 #define SCU_MODPISEL2_T21IS_Pos (2UL)
9190 #define SCU_MODPISEL2_T21IS_Msk (0xcUL)
9191 #define SCU_MODPISEL2_T2IS_Pos (0UL)
9192 #define SCU_MODPISEL2_T2IS_Msk (0x3UL)
9193 /* ======================================================= MODPISEL3 ======================================================= */
9194 #define SCU_MODPISEL3_URIOS2_Pos (6UL)
9195 #define SCU_MODPISEL3_URIOS2_Msk (0x40UL)
9196 /* ======================================================= MODSUSP1 ======================================================== */
9197 #define SCU_MODSUSP1_T21_SUSP_Pos (6UL)
9198 #define SCU_MODSUSP1_T21_SUSP_Msk (0x40UL)
9199 #define SCU_MODSUSP1_GPT12_SUSP_Pos (4UL)
9200 #define SCU_MODSUSP1_GPT12_SUSP_Msk (0x10UL)
9201 #define SCU_MODSUSP1_T2_SUSP_Pos (3UL)
9202 #define SCU_MODSUSP1_T2_SUSP_Msk (0x8UL)
9203 #define SCU_MODSUSP1_T13SUSP_Pos (2UL)
9204 #define SCU_MODSUSP1_T13SUSP_Msk (0x4UL)
9205 #define SCU_MODSUSP1_T12SUSP_Pos (1UL)
9206 #define SCU_MODSUSP1_T12SUSP_Msk (0x2UL)
9207 #define SCU_MODSUSP1_WDTSUSP_Pos (0UL)
9208 #define SCU_MODSUSP1_WDTSUSP_Msk (0x1UL)
9209 /* ======================================================= MODSUSP2 ======================================================== */
9210 #define SCU_MODSUSP2_ADC1_SUSP_Pos (2UL)
9211 #define SCU_MODSUSP2_ADC1_SUSP_Msk (0x4UL)
9212 #define SCU_MODSUSP2_MU_SUSP_Pos (1UL)
9213 #define SCU_MODSUSP2_MU_SUSP_Msk (0x2UL)
9214 #define SCU_MODSUSP2_T3_SUSP_Pos (0UL)
9215 #define SCU_MODSUSP2_T3_SUSP_Msk (0x1UL)
9216 /* ======================================================== NMICLR ========================================================= */
9217 #define SCU_NMICLR_NMISUPC_Pos (7UL)
9218 #define SCU_NMICLR_NMISUPC_Msk (0x80UL)
9219 #define SCU_NMICLR_NMIECCC_Pos (6UL)
9220 #define SCU_NMICLR_NMIECCC_Msk (0x40UL)
9221 #define SCU_NMICLR_NMIMAPC_Pos (5UL)
9222 #define SCU_NMICLR_NMIMAPC_Msk (0x20UL)
9223 #define SCU_NMICLR_NMIOWDC_Pos (4UL)
9224 #define SCU_NMICLR_NMIOWDC_Msk (0x10UL)
9225 #define SCU_NMICLR_NMIOTC_Pos (3UL)
9226 #define SCU_NMICLR_NMIOTC_Msk (0x8UL)
9227 #define SCU_NMICLR_NMINVMC_Pos (2UL)
9228 #define SCU_NMICLR_NMINVMC_Msk (0x4UL)
9229 #define SCU_NMICLR_NMIPLLC_Pos (1UL)
9230 #define SCU_NMICLR_NMIPLLC_Msk (0x2UL)
9231 #define SCU_NMICLR_NMIWDTC_Pos (0UL)
9232 #define SCU_NMICLR_NMIWDTC_Msk (0x1UL)
9233 /* ======================================================== NMICON ========================================================= */
9234 #define SCU_NMICON_NMISUP_Pos (7UL)
9235 #define SCU_NMICON_NMISUP_Msk (0x80UL)
9236 #define SCU_NMICON_NMIECC_Pos (6UL)
9237 #define SCU_NMICON_NMIECC_Msk (0x40UL)
9238 #define SCU_NMICON_NMIMAP_Pos (5UL)
9239 #define SCU_NMICON_NMIMAP_Msk (0x20UL)
9240 #define SCU_NMICON_NMIOWD_Pos (4UL)
9241 #define SCU_NMICON_NMIOWD_Msk (0x10UL)
9242 #define SCU_NMICON_NMIOT_Pos (3UL)
9243 #define SCU_NMICON_NMIOT_Msk (0x8UL)
9244 #define SCU_NMICON_NMINVM_Pos (2UL)
9245 #define SCU_NMICON_NMINVM_Msk (0x4UL)
9246 #define SCU_NMICON_NMIPLL_Pos (1UL)
9247 #define SCU_NMICON_NMIPLL_Msk (0x2UL)
9248 #define SCU_NMICON_NMIWDT_Pos (0UL)
9249 #define SCU_NMICON_NMIWDT_Msk (0x1UL)
9250 /* ========================================================= NMISR ========================================================= */
9251 #define SCU_NMISR_FNMISUP_Pos (7UL)
9252 #define SCU_NMISR_FNMISUP_Msk (0x80UL)
9253 #define SCU_NMISR_FNMIECC_Pos (6UL)
9254 #define SCU_NMISR_FNMIECC_Msk (0x40UL)
9255 #define SCU_NMISR_FNMIMAP_Pos (5UL)
9256 #define SCU_NMISR_FNMIMAP_Msk (0x20UL)
9257 #define SCU_NMISR_FNMIOWD_Pos (4UL)
9258 #define SCU_NMISR_FNMIOWD_Msk (0x10UL)
9259 #define SCU_NMISR_FNMIOT_Pos (3UL)
9260 #define SCU_NMISR_FNMIOT_Msk (0x8UL)
9261 #define SCU_NMISR_FNMINVM_Pos (2UL)
9262 #define SCU_NMISR_FNMINVM_Msk (0x4UL)
9263 #define SCU_NMISR_FNMIPLL_Pos (1UL)
9264 #define SCU_NMISR_FNMIPLL_Msk (0x2UL)
9265 #define SCU_NMISR_FNMIWDT_Pos (0UL)
9266 #define SCU_NMISR_FNMIWDT_Msk (0x1UL)
9267 /* ===================================================== NVM_PROT_STS ====================================================== */
9268 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Pos (3UL)
9269 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Msk (0x8UL)
9270 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Pos (2UL)
9271 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Msk (0x4UL)
9272 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Pos (1UL)
9273 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Msk (0x2UL)
9274 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Pos (0UL)
9275 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Msk (0x1UL)
9276 /* ======================================================== OSC_CON ======================================================== */
9277 #define SCU_OSC_CON_OSCTRIM_8_Pos (7UL)
9278 #define SCU_OSC_CON_OSCTRIM_8_Msk (0x80UL)
9279 #define SCU_OSC_CON_XPD_Pos (4UL)
9280 #define SCU_OSC_CON_XPD_Msk (0x10UL)
9281 #define SCU_OSC_CON_OSC2L_Pos (3UL)
9282 #define SCU_OSC_CON_OSC2L_Msk (0x8UL)
9283 #define SCU_OSC_CON_OSCWDTRST_Pos (2UL)
9284 #define SCU_OSC_CON_OSCWDTRST_Msk (0x4UL)
9285 #define SCU_OSC_CON_OSCSS_Pos (0UL)
9286 #define SCU_OSC_CON_OSCSS_Msk (0x3UL)
9287 /* ======================================================= P0_POCON0 ======================================================= */
9288 #define SCU_P0_POCON0_PDM1_Pos (4UL)
9289 #define SCU_P0_POCON0_PDM1_Msk (0x70UL)
9290 #define SCU_P0_POCON0_PDM0_Pos (0UL)
9291 #define SCU_P0_POCON0_PDM0_Msk (0x7UL)
9292 /* ======================================================= P0_POCON1 ======================================================= */
9293 #define SCU_P0_POCON1_PDM3_Pos (4UL)
9294 #define SCU_P0_POCON1_PDM3_Msk (0x70UL)
9295 #define SCU_P0_POCON1_PDM2_Pos (0UL)
9296 #define SCU_P0_POCON1_PDM2_Msk (0x7UL)
9297 /* ======================================================= P0_POCON2 ======================================================= */
9298 #define SCU_P0_POCON2_PDM4_Pos (0UL)
9299 #define SCU_P0_POCON2_PDM4_Msk (0x7UL)
9300 /* ======================================================= P1_POCON0 ======================================================= */
9301 #define SCU_P1_POCON0_PDM1_Pos (4UL)
9302 #define SCU_P1_POCON0_PDM1_Msk (0x70UL)
9303 #define SCU_P1_POCON0_PDM0_Pos (0UL)
9304 #define SCU_P1_POCON0_PDM0_Msk (0x7UL)
9305 /* ======================================================= P1_POCON1 ======================================================= */
9306 #define SCU_P1_POCON1_PDM3_Pos (4UL)
9307 #define SCU_P1_POCON1_PDM3_Msk (0x70UL)
9308 #define SCU_P1_POCON1_PDM2_Pos (0UL)
9309 #define SCU_P1_POCON1_PDM2_Msk (0x7UL)
9310 /* ======================================================= P1_POCON2 ======================================================= */
9311 #define SCU_P1_POCON2_PDM4_Pos (0UL)
9312 #define SCU_P1_POCON2_PDM4_Msk (0x7UL)
9313 /* ======================================================== PASSWD ========================================================= */
9314 #define SCU_PASSWD_PASS_Pos (3UL)
9315 #define SCU_PASSWD_PASS_Msk (0xf8UL)
9316 #define SCU_PASSWD_PROTECT_S_Pos (2UL)
9317 #define SCU_PASSWD_PROTECT_S_Msk (0x4UL)
9318 #define SCU_PASSWD_MODE_Pos (0UL)
9319 #define SCU_PASSWD_MODE_Msk (0x3UL)
9320 /* ======================================================== PLL_CON ======================================================== */
9321 #define SCU_PLL_CON_NDIV_Pos (4UL)
9322 #define SCU_PLL_CON_NDIV_Msk (0xf0UL)
9323 #define SCU_PLL_CON_VCOBYP_Pos (3UL)
9324 #define SCU_PLL_CON_VCOBYP_Msk (0x8UL)
9325 #define SCU_PLL_CON_OSCDISC_Pos (2UL)
9326 #define SCU_PLL_CON_OSCDISC_Msk (0x4UL)
9327 #define SCU_PLL_CON_RESLD_Pos (1UL)
9328 #define SCU_PLL_CON_RESLD_Msk (0x2UL)
9329 #define SCU_PLL_CON_LOCK_Pos (0UL)
9330 #define SCU_PLL_CON_LOCK_Msk (0x1UL)
9331 /* ======================================================== PMCON0 ========================================================= */
9332 #define SCU_PMCON0_SD_Pos (3UL)
9333 #define SCU_PMCON0_SD_Msk (0x8UL)
9334 #define SCU_PMCON0_PD_Pos (2UL)
9335 #define SCU_PMCON0_PD_Msk (0x4UL)
9336 #define SCU_PMCON0_SL_Pos (1UL)
9337 #define SCU_PMCON0_SL_Msk (0x2UL)
9338 #define SCU_PMCON0_XTAL_ON_Pos (0UL)
9339 #define SCU_PMCON0_XTAL_ON_Msk (0x1UL)
9340 /* ======================================================== PMCON1 ========================================================= */
9341 #define SCU_PMCON1_GPT12_DIS_Pos (4UL)
9342 #define SCU_PMCON1_GPT12_DIS_Msk (0x10UL)
9343 #define SCU_PMCON1_T2_DIS_Pos (3UL)
9344 #define SCU_PMCON1_T2_DIS_Msk (0x8UL)
9345 #define SCU_PMCON1_CCU6_DIS_Pos (2UL)
9346 #define SCU_PMCON1_CCU6_DIS_Msk (0x4UL)
9347 #define SCU_PMCON1_SSC1_DIS_Pos (1UL)
9348 #define SCU_PMCON1_SSC1_DIS_Msk (0x2UL)
9349 #define SCU_PMCON1_ADC1_DIS_Pos (0UL)
9350 #define SCU_PMCON1_ADC1_DIS_Msk (0x1UL)
9351 /* ======================================================== PMCON2 ========================================================= */
9352 #define SCU_PMCON2_T3_DIS_Pos (5UL)
9353 #define SCU_PMCON2_T3_DIS_Msk (0x20UL)
9354 #define SCU_PMCON2_T21_DIS_Pos (3UL)
9355 #define SCU_PMCON2_T21_DIS_Msk (0x8UL)
9356 #define SCU_PMCON2_SSC2_DIS_Pos (1UL)
9357 #define SCU_PMCON2_SSC2_DIS_Msk (0x2UL)
9358 /* ======================================================== RSTCON ========================================================= */
9359 #define SCU_RSTCON_LOCKUP_EN_Pos (7UL)
9360 #define SCU_RSTCON_LOCKUP_EN_Msk (0x80UL)
9361 #define SCU_RSTCON_LOCKUP_Pos (0UL)
9362 #define SCU_RSTCON_LOCKUP_Msk (0x1UL)
9363 /* ==================================================== SYS_STRTUP_STS ===================================================== */
9364 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Pos (2UL)
9365 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Msk (0x4UL)
9366 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Pos (1UL)
9367 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Msk (0x2UL)
9368 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Pos (0UL)
9369 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Msk (0x1UL)
9370 /* ======================================================== SYSCON0 ======================================================== */
9371 #define SCU_SYSCON0_SYSCLKSEL_Pos (6UL)
9372 #define SCU_SYSCON0_SYSCLKSEL_Msk (0xc0UL)
9373 #define SCU_SYSCON0_NVMCLKFAC_Pos (4UL)
9374 #define SCU_SYSCON0_NVMCLKFAC_Msk (0x30UL)
9375 /* ========================================================= TCCR ========================================================== */
9376 #define SCU_TCCR_TCC_Pos (0UL)
9377 #define SCU_TCCR_TCC_Msk (0x3UL)
9378 /* ======================================================== WDTCON ========================================================= */
9379 #define SCU_WDTCON_WINBEN_Pos (5UL)
9380 #define SCU_WDTCON_WINBEN_Msk (0x20UL)
9381 #define SCU_WDTCON_WDTPR_Pos (4UL)
9382 #define SCU_WDTCON_WDTPR_Msk (0x10UL)
9383 #define SCU_WDTCON_WDTEN_Pos (2UL)
9384 #define SCU_WDTCON_WDTEN_Msk (0x4UL)
9385 #define SCU_WDTCON_WDTRS_Pos (1UL)
9386 #define SCU_WDTCON_WDTRS_Msk (0x2UL)
9387 #define SCU_WDTCON_WDTIN_Pos (0UL)
9388 #define SCU_WDTCON_WDTIN_Msk (0x1UL)
9389 /* ========================================================= WDTH ========================================================== */
9390 #define SCU_WDTH_WDT_Pos (0UL)
9391 #define SCU_WDTH_WDT_Msk (0xffUL)
9392 /* ========================================================= WDTL ========================================================== */
9393 #define SCU_WDTL_WDT_Pos (0UL)
9394 #define SCU_WDTL_WDT_Msk (0xffUL)
9395 /* ======================================================== WDTREL ========================================================= */
9396 #define SCU_WDTREL_WDTREL_Pos (0UL)
9397 #define SCU_WDTREL_WDTREL_Msk (0xffUL)
9398 /* ======================================================== WDTWINB ======================================================== */
9399 #define SCU_WDTWINB_WDTWINB_Pos (0UL)
9400 #define SCU_WDTWINB_WDTWINB_Msk (0xffUL)
9403 /* =========================================================================================================================== */
9404 /* ================ SCUPM ================ */
9405 /* =========================================================================================================================== */
9406 
9407 /* ====================================================== AMCLK_CTRL ======================================================= */
9408 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos (0UL)
9409 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk (0x1UL)
9410 /* ==================================================== AMCLK_FREQ_STS ===================================================== */
9411 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Pos (8UL)
9412 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Msk (0x3f00UL)
9413 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Pos (0UL)
9414 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Msk (0x3fUL)
9415 /* ===================================================== AMCLK_TH_HYS ====================================================== */
9416 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos (30UL)
9417 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk (0xc0000000UL)
9418 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos (24UL)
9419 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk (0x3f000000UL)
9420 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos (22UL)
9421 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk (0xc00000UL)
9422 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos (16UL)
9423 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk (0x3f0000UL)
9424 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos (14UL)
9425 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk (0xc000UL)
9426 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos (8UL)
9427 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk (0x3f00UL)
9428 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos (6UL)
9429 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk (0xc0UL)
9430 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos (0UL)
9431 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk (0x3fUL)
9432 /* ===================================================== BDRV_IRQ_CTRL ===================================================== */
9433 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Pos (20UL)
9434 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Msk (0x100000UL)
9435 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Pos (19UL)
9436 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Msk (0x80000UL)
9437 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Pos (18UL)
9438 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Msk (0x40000UL)
9439 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Pos (17UL)
9440 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Msk (0x20000UL)
9441 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos (16UL)
9442 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk (0x10000UL)
9443 #define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos (15UL)
9444 #define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk (0x8000UL)
9445 #define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos (14UL)
9446 #define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk (0x4000UL)
9447 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos (13UL)
9448 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk (0x2000UL)
9449 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos (12UL)
9450 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk (0x1000UL)
9451 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos (11UL)
9452 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk (0x800UL)
9453 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos (10UL)
9454 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk (0x400UL)
9455 #define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos (5UL)
9456 #define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk (0x20UL)
9457 #define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos (4UL)
9458 #define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk (0x10UL)
9459 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos (3UL)
9460 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk (0x8UL)
9461 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos (2UL)
9462 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk (0x4UL)
9463 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos (1UL)
9464 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk (0x2UL)
9465 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos (0UL)
9466 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk (0x1UL)
9467 /* ======================================================== BDRV_IS ======================================================== */
9468 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Pos (28UL)
9469 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Msk (0x10000000UL)
9470 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Pos (27UL)
9471 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Msk (0x8000000UL)
9472 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Pos (26UL)
9473 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Msk (0x4000000UL)
9474 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Pos (25UL)
9475 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Msk (0x2000000UL)
9476 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Pos (24UL)
9477 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Msk (0x1000000UL)
9478 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Pos (20UL)
9479 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Msk (0x100000UL)
9480 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Pos (19UL)
9481 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Msk (0x80000UL)
9482 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Pos (18UL)
9483 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Msk (0x40000UL)
9484 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Pos (17UL)
9485 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Msk (0x20000UL)
9486 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos (16UL)
9487 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk (0x10000UL)
9488 #define SCUPM_BDRV_IS_HS3_OC_IS_Pos (15UL)
9489 #define SCUPM_BDRV_IS_HS3_OC_IS_Msk (0x8000UL)
9490 #define SCUPM_BDRV_IS_LS3_OC_IS_Pos (14UL)
9491 #define SCUPM_BDRV_IS_LS3_OC_IS_Msk (0x4000UL)
9492 #define SCUPM_BDRV_IS_HS2_OC_IS_Pos (13UL)
9493 #define SCUPM_BDRV_IS_HS2_OC_IS_Msk (0x2000UL)
9494 #define SCUPM_BDRV_IS_HS1_OC_IS_Pos (12UL)
9495 #define SCUPM_BDRV_IS_HS1_OC_IS_Msk (0x1000UL)
9496 #define SCUPM_BDRV_IS_LS2_OC_IS_Pos (11UL)
9497 #define SCUPM_BDRV_IS_LS2_OC_IS_Msk (0x800UL)
9498 #define SCUPM_BDRV_IS_LS1_OC_IS_Pos (10UL)
9499 #define SCUPM_BDRV_IS_LS1_OC_IS_Msk (0x400UL)
9500 #define SCUPM_BDRV_IS_HS3_DS_IS_Pos (5UL)
9501 #define SCUPM_BDRV_IS_HS3_DS_IS_Msk (0x20UL)
9502 #define SCUPM_BDRV_IS_LS3_DS_IS_Pos (4UL)
9503 #define SCUPM_BDRV_IS_LS3_DS_IS_Msk (0x10UL)
9504 #define SCUPM_BDRV_IS_HS2_DS_IS_Pos (3UL)
9505 #define SCUPM_BDRV_IS_HS2_DS_IS_Msk (0x8UL)
9506 #define SCUPM_BDRV_IS_HS1_DS_IS_Pos (2UL)
9507 #define SCUPM_BDRV_IS_HS1_DS_IS_Msk (0x4UL)
9508 #define SCUPM_BDRV_IS_LS2_DS_IS_Pos (1UL)
9509 #define SCUPM_BDRV_IS_LS2_DS_IS_Msk (0x2UL)
9510 #define SCUPM_BDRV_IS_LS1_DS_IS_Pos (0UL)
9511 #define SCUPM_BDRV_IS_LS1_DS_IS_Msk (0x1UL)
9512 /* ====================================================== BDRV_ISCLR ======================================================= */
9513 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Pos (28UL)
9514 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Msk (0x10000000UL)
9515 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Pos (27UL)
9516 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Msk (0x8000000UL)
9517 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Pos (26UL)
9518 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Msk (0x4000000UL)
9519 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Pos (25UL)
9520 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Msk (0x2000000UL)
9521 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Pos (24UL)
9522 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Msk (0x1000000UL)
9523 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Pos (20UL)
9524 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Msk (0x100000UL)
9525 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Pos (19UL)
9526 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Msk (0x80000UL)
9527 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Pos (18UL)
9528 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Msk (0x40000UL)
9529 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Pos (17UL)
9530 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Msk (0x20000UL)
9531 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos (16UL)
9532 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk (0x10000UL)
9533 #define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Pos (15UL)
9534 #define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk (0x8000UL)
9535 #define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Pos (14UL)
9536 #define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk (0x4000UL)
9537 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos (13UL)
9538 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk (0x2000UL)
9539 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos (12UL)
9540 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk (0x1000UL)
9541 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos (11UL)
9542 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk (0x800UL)
9543 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos (10UL)
9544 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk (0x400UL)
9545 #define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Pos (5UL)
9546 #define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk (0x20UL)
9547 #define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Pos (4UL)
9548 #define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk (0x10UL)
9549 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos (3UL)
9550 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk (0x8UL)
9551 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos (2UL)
9552 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk (0x4UL)
9553 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos (1UL)
9554 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk (0x2UL)
9555 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos (0UL)
9556 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk (0x1UL)
9557 /* ========================================================= BFSTS ========================================================= */
9558 #define SCUPM_BFSTS_SBFSTS_Pos (1UL)
9559 #define SCUPM_BFSTS_SBFSTS_Msk (0x2UL)
9560 #define SCUPM_BFSTS_DBFSTS_Pos (0UL)
9561 #define SCUPM_BFSTS_DBFSTS_Msk (0x1UL)
9562 /* ======================================================= BFSTS_CLR ======================================================= */
9563 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Pos (1UL)
9564 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Msk (0x2UL)
9565 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Pos (0UL)
9566 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Msk (0x1UL)
9567 /* ========================================================= DBFA ========================================================== */
9568 #define SCUPM_DBFA_DBFA_Pos (0UL)
9569 #define SCUPM_DBFA_DBFA_Msk (0xffffffffUL)
9570 /* ===================================================== PCU_CTRL_STS ====================================================== */
9571 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos (26UL)
9572 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk (0x4000000UL)
9573 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos (25UL)
9574 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk (0x2000000UL)
9575 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Pos (24UL)
9576 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Msk (0x1000000UL)
9577 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Pos (14UL)
9578 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Msk (0x4000UL)
9579 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos (8UL)
9580 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk (0x100UL)
9581 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos (7UL)
9582 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk (0x80UL)
9583 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos (1UL)
9584 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk (0x2UL)
9585 /* ========================================================= SBFA ========================================================== */
9586 #define SCUPM_SBFA_SBFA_Pos (0UL)
9587 #define SCUPM_SBFA_SBFA_Msk (0xffffffffUL)
9588 /* ======================================================== STCALIB ======================================================== */
9589 #define SCUPM_STCALIB_STCALIB_Pos (0UL)
9590 #define SCUPM_STCALIB_STCALIB_Msk (0x3ffffffUL)
9591 /* ===================================================== SYS_IRQ_CTRL ====================================================== */
9592 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Pos (23UL)
9593 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Msk (0x800000UL)
9594 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Pos (22UL)
9595 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Msk (0x400000UL)
9596 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Pos (21UL)
9597 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Msk (0x200000UL)
9598 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Pos (20UL)
9599 #define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Msk (0x100000UL)
9600 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Pos (19UL)
9601 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Msk (0x80000UL)
9602 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Pos (18UL)
9603 #define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Msk (0x40000UL)
9604 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Pos (17UL)
9605 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Msk (0x20000UL)
9606 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Pos (16UL)
9607 #define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Msk (0x10000UL)
9608 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Pos (15UL)
9609 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Msk (0x8000UL)
9610 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Pos (14UL)
9611 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Msk (0x4000UL)
9612 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Pos (13UL)
9613 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Msk (0x2000UL)
9614 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Pos (12UL)
9615 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Msk (0x1000UL)
9616 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Pos (11UL)
9617 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Msk (0x800UL)
9618 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Pos (10UL)
9619 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Msk (0x400UL)
9620 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Pos (9UL)
9621 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Msk (0x200UL)
9622 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Pos (8UL)
9623 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Msk (0x100UL)
9624 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Pos (7UL)
9625 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Msk (0x80UL)
9626 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Pos (6UL)
9627 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Msk (0x40UL)
9628 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Pos (2UL)
9629 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Msk (0x4UL)
9630 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Pos (1UL)
9631 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Msk (0x2UL)
9632 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Pos (0UL)
9633 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Msk (0x1UL)
9634 /* ======================================================== SYS_IS ========================================================= */
9635 #define SCUPM_SYS_IS_PHW_ZCHI_STS_Pos (29UL)
9636 #define SCUPM_SYS_IS_PHW_ZCHI_STS_Msk (0x20000000UL)
9637 #define SCUPM_SYS_IS_PHW_ZCLOW_STS_Pos (28UL)
9638 #define SCUPM_SYS_IS_PHW_ZCLOW_STS_Msk (0x10000000UL)
9639 #define SCUPM_SYS_IS_PHV_ZCHI_STS_Pos (27UL)
9640 #define SCUPM_SYS_IS_PHV_ZCHI_STS_Msk (0x8000000UL)
9641 #define SCUPM_SYS_IS_PHV_ZCLOW_STS_Pos (26UL)
9642 #define SCUPM_SYS_IS_PHV_ZCLOW_STS_Msk (0x4000000UL)
9643 #define SCUPM_SYS_IS_PHU_ZCHI_STS_Pos (25UL)
9644 #define SCUPM_SYS_IS_PHU_ZCHI_STS_Msk (0x2000000UL)
9645 #define SCUPM_SYS_IS_PHU_ZCLOW_STS_Pos (24UL)
9646 #define SCUPM_SYS_IS_PHU_ZCLOW_STS_Msk (0x1000000UL)
9647 #define SCUPM_SYS_IS_ADC4_EOC_IS_Pos (23UL)
9648 #define SCUPM_SYS_IS_ADC4_EOC_IS_Msk (0x800000UL)
9649 #define SCUPM_SYS_IS_ADC3_EOC_IS_Pos (22UL)
9650 #define SCUPM_SYS_IS_ADC3_EOC_IS_Msk (0x400000UL)
9651 #define SCUPM_SYS_IS_PHW_ZCHI_IS_Pos (21UL)
9652 #define SCUPM_SYS_IS_PHW_ZCHI_IS_Msk (0x200000UL)
9653 #define SCUPM_SYS_IS_PHW_ZCLOW_IS_Pos (20UL)
9654 #define SCUPM_SYS_IS_PHW_ZCLOW_IS_Msk (0x100000UL)
9655 #define SCUPM_SYS_IS_PHV_ZCHI_IS_Pos (19UL)
9656 #define SCUPM_SYS_IS_PHV_ZCHI_IS_Msk (0x80000UL)
9657 #define SCUPM_SYS_IS_PHV_ZCLOW_IS_Pos (18UL)
9658 #define SCUPM_SYS_IS_PHV_ZCLOW_IS_Msk (0x40000UL)
9659 #define SCUPM_SYS_IS_PHU_ZCHI_IS_Pos (17UL)
9660 #define SCUPM_SYS_IS_PHU_ZCHI_IS_Msk (0x20000UL)
9661 #define SCUPM_SYS_IS_PHU_ZCLOW_IS_Pos (16UL)
9662 #define SCUPM_SYS_IS_PHU_ZCLOW_IS_Msk (0x10000UL)
9663 #define SCUPM_SYS_IS_ADC2_ESM_IS_Pos (15UL)
9664 #define SCUPM_SYS_IS_ADC2_ESM_IS_Msk (0x8000UL)
9665 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Pos (14UL)
9666 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Msk (0x4000UL)
9667 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Pos (13UL)
9668 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Msk (0x2000UL)
9669 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Pos (12UL)
9670 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Msk (0x1000UL)
9671 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Pos (11UL)
9672 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Msk (0x800UL)
9673 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Pos (10UL)
9674 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Msk (0x400UL)
9675 #define SCUPM_SYS_IS_SYS_OT_IS_Pos (9UL)
9676 #define SCUPM_SYS_IS_SYS_OT_IS_Msk (0x200UL)
9677 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Pos (8UL)
9678 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Msk (0x100UL)
9679 #define SCUPM_SYS_IS_PMU_OT_IS_Pos (7UL)
9680 #define SCUPM_SYS_IS_PMU_OT_IS_Msk (0x80UL)
9681 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Pos (6UL)
9682 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Msk (0x40UL)
9683 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Pos (2UL)
9684 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Msk (0x4UL)
9685 #define SCUPM_SYS_IS_LIN_OT_IS_Pos (1UL)
9686 #define SCUPM_SYS_IS_LIN_OT_IS_Msk (0x2UL)
9687 #define SCUPM_SYS_IS_LIN_OC_IS_Pos (0UL)
9688 #define SCUPM_SYS_IS_LIN_OC_IS_Msk (0x1UL)
9689 /* ======================================================= SYS_ISCLR ======================================================= */
9690 #define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Pos (29UL)
9691 #define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Msk (0x20000000UL)
9692 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Pos (28UL)
9693 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Msk (0x10000000UL)
9694 #define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Pos (27UL)
9695 #define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Msk (0x8000000UL)
9696 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Pos (26UL)
9697 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Msk (0x4000000UL)
9698 #define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Pos (25UL)
9699 #define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Msk (0x2000000UL)
9700 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Pos (24UL)
9701 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Msk (0x1000000UL)
9702 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Pos (23UL)
9703 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Msk (0x800000UL)
9704 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Pos (22UL)
9705 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Msk (0x400000UL)
9706 #define SCUPM_SYS_ISCLR_PHW_ZCHI_ICLR_Pos (21UL)
9707 #define SCUPM_SYS_ISCLR_PHW_ZCHI_ICLR_Msk (0x200000UL)
9708 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_ICLR_Pos (20UL)
9709 #define SCUPM_SYS_ISCLR_PHW_ZCLOW_ICLR_Msk (0x100000UL)
9710 #define SCUPM_SYS_ISCLR_PHV_ZCHI_ICLR_Pos (19UL)
9711 #define SCUPM_SYS_ISCLR_PHV_ZCHI_ICLR_Msk (0x80000UL)
9712 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_ICLR_Pos (18UL)
9713 #define SCUPM_SYS_ISCLR_PHV_ZCLOW_ICLR_Msk (0x40000UL)
9714 #define SCUPM_SYS_ISCLR_PHU_ZCHI_ICLR_Pos (17UL)
9715 #define SCUPM_SYS_ISCLR_PHU_ZCHI_ICLR_Msk (0x20000UL)
9716 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_ICLR_Pos (16UL)
9717 #define SCUPM_SYS_ISCLR_PHU_ZCLOW_ICLR_Msk (0x10000UL)
9718 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Pos (15UL)
9719 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Msk (0x8000UL)
9720 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Pos (14UL)
9721 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Msk (0x4000UL)
9722 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Pos (13UL)
9723 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Msk (0x2000UL)
9724 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Pos (12UL)
9725 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Msk (0x1000UL)
9726 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Pos (11UL)
9727 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Msk (0x800UL)
9728 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Pos (10UL)
9729 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Msk (0x400UL)
9730 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Pos (9UL)
9731 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Msk (0x200UL)
9732 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Pos (8UL)
9733 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Msk (0x100UL)
9734 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Pos (7UL)
9735 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Msk (0x80UL)
9736 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Pos (6UL)
9737 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Msk (0x40UL)
9738 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Pos (2UL)
9739 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Msk (0x4UL)
9740 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Pos (1UL)
9741 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Msk (0x2UL)
9742 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Pos (0UL)
9743 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Msk (0x1UL)
9744 /* ================================================== SYS_SUPPLY_IRQ_CLR =================================================== */
9745 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Pos (23UL)
9746 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Msk (0x800000UL)
9747 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Pos (22UL)
9748 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Msk (0x400000UL)
9749 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Pos (21UL)
9750 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Msk (0x200000UL)
9751 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_SCLR_Pos (20UL)
9752 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_SCLR_Msk (0x100000UL)
9753 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Pos (19UL)
9754 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Msk (0x80000UL)
9755 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Pos (18UL)
9756 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Msk (0x40000UL)
9757 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Pos (17UL)
9758 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Msk (0x20000UL)
9759 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_SCLR_Pos (16UL)
9760 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_SCLR_Msk (0x10000UL)
9761 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Pos (7UL)
9762 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Msk (0x80UL)
9763 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Pos (6UL)
9764 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Msk (0x40UL)
9765 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Pos (5UL)
9766 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Msk (0x20UL)
9767 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_ICLR_Pos (4UL)
9768 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_OV_ICLR_Msk (0x10UL)
9769 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Pos (3UL)
9770 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Msk (0x8UL)
9771 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Pos (2UL)
9772 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Msk (0x4UL)
9773 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Pos (1UL)
9774 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Msk (0x2UL)
9775 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_ICLR_Pos (0UL)
9776 #define SCUPM_SYS_SUPPLY_IRQ_CLR_MON_UV_ICLR_Msk (0x1UL)
9777 /* ================================================== SYS_SUPPLY_IRQ_CTRL ================================================== */
9778 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Pos (7UL)
9779 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Msk (0x80UL)
9780 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Pos (6UL)
9781 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Msk (0x40UL)
9782 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Pos (5UL)
9783 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Msk (0x20UL)
9784 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_OV_IE_Pos (4UL)
9785 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_OV_IE_Msk (0x10UL)
9786 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Pos (3UL)
9787 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Msk (0x8UL)
9788 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Pos (2UL)
9789 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Msk (0x4UL)
9790 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Pos (1UL)
9791 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Msk (0x2UL)
9792 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_UV_IE_Pos (0UL)
9793 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_MON_UV_IE_Msk (0x1UL)
9794 /* ================================================== SYS_SUPPLY_IRQ_STS =================================================== */
9795 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Pos (23UL)
9796 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Msk (0x800000UL)
9797 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Pos (22UL)
9798 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Msk (0x400000UL)
9799 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Pos (21UL)
9800 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Msk (0x200000UL)
9801 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_STS_Pos (20UL)
9802 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_STS_Msk (0x100000UL)
9803 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Pos (19UL)
9804 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Msk (0x80000UL)
9805 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Pos (18UL)
9806 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Msk (0x40000UL)
9807 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Pos (17UL)
9808 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Msk (0x20000UL)
9809 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_STS_Pos (16UL)
9810 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_STS_Msk (0x10000UL)
9811 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Pos (7UL)
9812 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Msk (0x80UL)
9813 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Pos (6UL)
9814 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Msk (0x40UL)
9815 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Pos (5UL)
9816 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Msk (0x20UL)
9817 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_IS_Pos (4UL)
9818 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_OV_IS_Msk (0x10UL)
9819 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Pos (3UL)
9820 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Msk (0x8UL)
9821 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Pos (2UL)
9822 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Msk (0x4UL)
9823 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Pos (1UL)
9824 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Msk (0x2UL)
9825 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_IS_Pos (0UL)
9826 #define SCUPM_SYS_SUPPLY_IRQ_STS_MON_UV_IS_Msk (0x1UL)
9827 /* ======================================================= WDT1_TRIG ======================================================= */
9828 #define SCUPM_WDT1_TRIG_SOWCONF_Pos (6UL)
9829 #define SCUPM_WDT1_TRIG_SOWCONF_Msk (0xc0UL)
9830 #define SCUPM_WDT1_TRIG_WDP_SEL_Pos (0UL)
9831 #define SCUPM_WDT1_TRIG_WDP_SEL_Msk (0x3fUL)
9834 /* =========================================================================================================================== */
9835 /* ================ SSC1 ================ */
9836 /* =========================================================================================================================== */
9837 
9838 /* ========================================================== BR =========================================================== */
9839 #define SSC1_BR_BR_VALUE_Pos (0UL)
9840 #define SSC1_BR_BR_VALUE_Msk (0xffffUL)
9841 /* ========================================================== CON ========================================================== */
9842 #define SSC1_CON_BC_Pos (0UL)
9843 #define SSC1_CON_BC_Msk (0xfUL)
9844 #define SSC1_CON_TE_Pos (8UL)
9845 #define SSC1_CON_TE_Msk (0x100UL)
9846 #define SSC1_CON_RE_Pos (9UL)
9847 #define SSC1_CON_RE_Msk (0x200UL)
9848 #define SSC1_CON_PE_Pos (10UL)
9849 #define SSC1_CON_PE_Msk (0x400UL)
9850 #define SSC1_CON_BE_Pos (11UL)
9851 #define SSC1_CON_BE_Msk (0x800UL)
9852 #define SSC1_CON_BSY_Pos (12UL)
9853 #define SSC1_CON_BSY_Msk (0x1000UL)
9854 #define SSC1_CON_MS_Pos (14UL)
9855 #define SSC1_CON_MS_Msk (0x4000UL)
9856 #define SSC1_CON_EN_Pos (15UL)
9857 #define SSC1_CON_EN_Msk (0x8000UL)
9858 /* ======================================================== ISRCLR ========================================================= */
9859 #define SSC1_ISRCLR_TECLR_Pos (8UL)
9860 #define SSC1_ISRCLR_TECLR_Msk (0x100UL)
9861 #define SSC1_ISRCLR_RECLR_Pos (9UL)
9862 #define SSC1_ISRCLR_RECLR_Msk (0x200UL)
9863 #define SSC1_ISRCLR_PECLR_Pos (10UL)
9864 #define SSC1_ISRCLR_PECLR_Msk (0x400UL)
9865 #define SSC1_ISRCLR_BECLR_Pos (11UL)
9866 #define SSC1_ISRCLR_BECLR_Msk (0x800UL)
9867 /* ========================================================= PISEL ========================================================= */
9868 #define SSC1_PISEL_MIS_0_Pos (0UL)
9869 #define SSC1_PISEL_MIS_0_Msk (0x1UL)
9870 #define SSC1_PISEL_SIS_Pos (1UL)
9871 #define SSC1_PISEL_SIS_Msk (0x2UL)
9872 #define SSC1_PISEL_CIS_Pos (2UL)
9873 #define SSC1_PISEL_CIS_Msk (0x4UL)
9874 #define SSC1_PISEL_MIS_1_Pos (3UL)
9875 #define SSC1_PISEL_MIS_1_Msk (0x8UL)
9876 /* ========================================================== RB =========================================================== */
9877 #define SSC1_RB_RB_VALUE_Pos (0UL)
9878 #define SSC1_RB_RB_VALUE_Msk (0xffffUL)
9879 /* ========================================================== TB =========================================================== */
9880 #define SSC1_TB_TB_VALUE_Pos (0UL)
9881 #define SSC1_TB_TB_VALUE_Msk (0xffffUL)
9884 /* =========================================================================================================================== */
9885 /* ================ SSC2 ================ */
9886 /* =========================================================================================================================== */
9887 
9888 /* ========================================================== BR =========================================================== */
9889 #define SSC2_BR_BR_VALUE_Pos (0UL)
9890 #define SSC2_BR_BR_VALUE_Msk (0xffffUL)
9891 /* ========================================================== CON ========================================================== */
9892 #define SSC2_CON_BC_Pos (0UL)
9893 #define SSC2_CON_BC_Msk (0xfUL)
9894 #define SSC2_CON_TE_Pos (8UL)
9895 #define SSC2_CON_TE_Msk (0x100UL)
9896 #define SSC2_CON_RE_Pos (9UL)
9897 #define SSC2_CON_RE_Msk (0x200UL)
9898 #define SSC2_CON_PE_Pos (10UL)
9899 #define SSC2_CON_PE_Msk (0x400UL)
9900 #define SSC2_CON_BE_Pos (11UL)
9901 #define SSC2_CON_BE_Msk (0x800UL)
9902 #define SSC2_CON_BSY_Pos (12UL)
9903 #define SSC2_CON_BSY_Msk (0x1000UL)
9904 #define SSC2_CON_MS_Pos (14UL)
9905 #define SSC2_CON_MS_Msk (0x4000UL)
9906 #define SSC2_CON_EN_Pos (15UL)
9907 #define SSC2_CON_EN_Msk (0x8000UL)
9908 /* ======================================================== ISRCLR ========================================================= */
9909 #define SSC2_ISRCLR_TECLR_Pos (8UL)
9910 #define SSC2_ISRCLR_TECLR_Msk (0x100UL)
9911 #define SSC2_ISRCLR_RECLR_Pos (9UL)
9912 #define SSC2_ISRCLR_RECLR_Msk (0x200UL)
9913 #define SSC2_ISRCLR_PECLR_Pos (10UL)
9914 #define SSC2_ISRCLR_PECLR_Msk (0x400UL)
9915 #define SSC2_ISRCLR_BECLR_Pos (11UL)
9916 #define SSC2_ISRCLR_BECLR_Msk (0x800UL)
9917 /* ========================================================= PISEL ========================================================= */
9918 #define SSC2_PISEL_MIS_0_Pos (0UL)
9919 #define SSC2_PISEL_MIS_0_Msk (0x1UL)
9920 #define SSC2_PISEL_SIS_Pos (1UL)
9921 #define SSC2_PISEL_SIS_Msk (0x2UL)
9922 #define SSC2_PISEL_CIS_Pos (2UL)
9923 #define SSC2_PISEL_CIS_Msk (0x4UL)
9924 #define SSC2_PISEL_MIS_1_Pos (3UL)
9925 #define SSC2_PISEL_MIS_1_Msk (0x8UL)
9926 /* ========================================================== RB =========================================================== */
9927 #define SSC2_RB_RB_VALUE_Pos (0UL)
9928 #define SSC2_RB_RB_VALUE_Msk (0xffffUL)
9929 /* ========================================================== TB =========================================================== */
9930 #define SSC2_TB_TB_VALUE_Pos (0UL)
9931 #define SSC2_TB_TB_VALUE_Msk (0xffffUL)
9934 /* =========================================================================================================================== */
9935 /* ================ TIMER2 ================ */
9936 /* =========================================================================================================================== */
9937 
9938 /* ========================================================= RC2H ========================================================== */
9939 #define TIMER2_RC2H_RC2_Pos (0UL)
9940 #define TIMER2_RC2H_RC2_Msk (0xffUL)
9941 /* ========================================================= RC2L ========================================================== */
9942 #define TIMER2_RC2L_RC2_Pos (0UL)
9943 #define TIMER2_RC2L_RC2_Msk (0xffUL)
9944 /* ========================================================= T2CON ========================================================= */
9945 #define TIMER2_T2CON_CP_RL2_Pos (0UL)
9946 #define TIMER2_T2CON_CP_RL2_Msk (0x1UL)
9947 #define TIMER2_T2CON_C_T2_Pos (1UL)
9948 #define TIMER2_T2CON_C_T2_Msk (0x2UL)
9949 #define TIMER2_T2CON_TR2_Pos (2UL)
9950 #define TIMER2_T2CON_TR2_Msk (0x4UL)
9951 #define TIMER2_T2CON_EXEN2_Pos (3UL)
9952 #define TIMER2_T2CON_EXEN2_Msk (0x8UL)
9953 #define TIMER2_T2CON_EXF2_Pos (6UL)
9954 #define TIMER2_T2CON_EXF2_Msk (0x40UL)
9955 #define TIMER2_T2CON_TF2_Pos (7UL)
9956 #define TIMER2_T2CON_TF2_Msk (0x80UL)
9957 /* ======================================================== T2CON1 ========================================================= */
9958 #define TIMER2_T2CON1_EXF2EN_Pos (0UL)
9959 #define TIMER2_T2CON1_EXF2EN_Msk (0x1UL)
9960 #define TIMER2_T2CON1_TF2EN_Pos (1UL)
9961 #define TIMER2_T2CON1_TF2EN_Msk (0x2UL)
9962 /* ========================================================== T2H ========================================================== */
9963 #define TIMER2_T2H_T2H_Pos (0UL)
9964 #define TIMER2_T2H_T2H_Msk (0xffUL)
9965 /* ======================================================== T2ICLR ========================================================= */
9966 #define TIMER2_T2ICLR_EXF2CLR_Pos (6UL)
9967 #define TIMER2_T2ICLR_EXF2CLR_Msk (0x40UL)
9968 #define TIMER2_T2ICLR_TF2CLR_Pos (7UL)
9969 #define TIMER2_T2ICLR_TF2CLR_Msk (0x80UL)
9970 /* ========================================================== T2L ========================================================== */
9971 #define TIMER2_T2L_T2L_Pos (0UL)
9972 #define TIMER2_T2L_T2L_Msk (0xffUL)
9973 /* ========================================================= T2MOD ========================================================= */
9974 #define TIMER2_T2MOD_DCEN_Pos (0UL)
9975 #define TIMER2_T2MOD_DCEN_Msk (0x1UL)
9976 #define TIMER2_T2MOD_T2PRE_Pos (1UL)
9977 #define TIMER2_T2MOD_T2PRE_Msk (0xeUL)
9978 #define TIMER2_T2MOD_PREN_Pos (4UL)
9979 #define TIMER2_T2MOD_PREN_Msk (0x10UL)
9980 #define TIMER2_T2MOD_EDGESEL_Pos (5UL)
9981 #define TIMER2_T2MOD_EDGESEL_Msk (0x20UL)
9982 #define TIMER2_T2MOD_T2RHEN_Pos (6UL)
9983 #define TIMER2_T2MOD_T2RHEN_Msk (0x40UL)
9984 #define TIMER2_T2MOD_T2REGS_Pos (7UL)
9985 #define TIMER2_T2MOD_T2REGS_Msk (0x80UL)
9988 /* =========================================================================================================================== */
9989 /* ================ TIMER21 ================ */
9990 /* =========================================================================================================================== */
9991 
9992 /* ========================================================= RC2H ========================================================== */
9993 #define TIMER21_RC2H_RC2_Pos (0UL)
9994 #define TIMER21_RC2H_RC2_Msk (0xffUL)
9995 /* ========================================================= RC2L ========================================================== */
9996 #define TIMER21_RC2L_RC2_Pos (0UL)
9997 #define TIMER21_RC2L_RC2_Msk (0xffUL)
9998 /* ========================================================= T2CON ========================================================= */
9999 #define TIMER21_T2CON_CP_RL2_Pos (0UL)
10000 #define TIMER21_T2CON_CP_RL2_Msk (0x1UL)
10001 #define TIMER21_T2CON_C_T2_Pos (1UL)
10002 #define TIMER21_T2CON_C_T2_Msk (0x2UL)
10003 #define TIMER21_T2CON_TR2_Pos (2UL)
10004 #define TIMER21_T2CON_TR2_Msk (0x4UL)
10005 #define TIMER21_T2CON_EXEN2_Pos (3UL)
10006 #define TIMER21_T2CON_EXEN2_Msk (0x8UL)
10007 #define TIMER21_T2CON_EXF2_Pos (6UL)
10008 #define TIMER21_T2CON_EXF2_Msk (0x40UL)
10009 #define TIMER21_T2CON_TF2_Pos (7UL)
10010 #define TIMER21_T2CON_TF2_Msk (0x80UL)
10011 /* ======================================================== T2CON1 ========================================================= */
10012 #define TIMER21_T2CON1_EXF2EN_Pos (0UL)
10013 #define TIMER21_T2CON1_EXF2EN_Msk (0x1UL)
10014 #define TIMER21_T2CON1_TF2EN_Pos (1UL)
10015 #define TIMER21_T2CON1_TF2EN_Msk (0x2UL)
10016 /* ========================================================== T2H ========================================================== */
10017 #define TIMER21_T2H_T2H_Pos (0UL)
10018 #define TIMER21_T2H_T2H_Msk (0xffUL)
10019 /* ======================================================== T2ICLR ========================================================= */
10020 #define TIMER21_T2ICLR_EXF2CLR_Pos (6UL)
10021 #define TIMER21_T2ICLR_EXF2CLR_Msk (0x40UL)
10022 #define TIMER21_T2ICLR_TF2CLR_Pos (7UL)
10023 #define TIMER21_T2ICLR_TF2CLR_Msk (0x80UL)
10024 /* ========================================================== T2L ========================================================== */
10025 #define TIMER21_T2L_T2L_Pos (0UL)
10026 #define TIMER21_T2L_T2L_Msk (0xffUL)
10027 /* ========================================================= T2MOD ========================================================= */
10028 #define TIMER21_T2MOD_DCEN_Pos (0UL)
10029 #define TIMER21_T2MOD_DCEN_Msk (0x1UL)
10030 #define TIMER21_T2MOD_T2PRE_Pos (1UL)
10031 #define TIMER21_T2MOD_T2PRE_Msk (0xeUL)
10032 #define TIMER21_T2MOD_PREN_Pos (4UL)
10033 #define TIMER21_T2MOD_PREN_Msk (0x10UL)
10034 #define TIMER21_T2MOD_EDGESEL_Pos (5UL)
10035 #define TIMER21_T2MOD_EDGESEL_Msk (0x20UL)
10036 #define TIMER21_T2MOD_T2RHEN_Pos (6UL)
10037 #define TIMER21_T2MOD_T2RHEN_Msk (0x40UL)
10038 #define TIMER21_T2MOD_T2REGS_Pos (7UL)
10039 #define TIMER21_T2MOD_T2REGS_Msk (0x80UL)
10042 /* =========================================================================================================================== */
10043 /* ================ TIMER3 ================ */
10044 /* =========================================================================================================================== */
10045 
10046 /* ========================================================== CMP ========================================================== */
10047 #define TIMER3_CMP_HI_Pos (8UL)
10048 #define TIMER3_CMP_HI_Msk (0xff00UL)
10049 #define TIMER3_CMP_LO_Pos (0UL)
10050 #define TIMER3_CMP_LO_Msk (0xffUL)
10051 /* ========================================================== CNT ========================================================== */
10052 #define TIMER3_CNT_HI_Pos (8UL)
10053 #define TIMER3_CNT_HI_Msk (0xff00UL)
10054 #define TIMER3_CNT_LO_Pos (0UL)
10055 #define TIMER3_CNT_LO_Msk (0xffUL)
10056 /* ========================================================= CTRL ========================================================== */
10057 #define TIMER3_CTRL_T3H_OVF_IE_Pos (9UL)
10058 #define TIMER3_CTRL_T3H_OVF_IE_Msk (0x200UL)
10059 #define TIMER3_CTRL_T3L_OVF_IE_Pos (8UL)
10060 #define TIMER3_CTRL_T3L_OVF_IE_Msk (0x100UL)
10061 #define TIMER3_CTRL_T3L_OVF_STS_Pos (7UL)
10062 #define TIMER3_CTRL_T3L_OVF_STS_Msk (0x80UL)
10063 #define TIMER3_CTRL_TR3L_Pos (6UL)
10064 #define TIMER3_CTRL_TR3L_Msk (0x40UL)
10065 #define TIMER3_CTRL_T3H_OVF_STS_Pos (5UL)
10066 #define TIMER3_CTRL_T3H_OVF_STS_Msk (0x20UL)
10067 #define TIMER3_CTRL_TR3H_Pos (4UL)
10068 #define TIMER3_CTRL_TR3H_Msk (0x10UL)
10069 #define TIMER3_CTRL_CNT_RDY_Pos (3UL)
10070 #define TIMER3_CTRL_CNT_RDY_Msk (0x8UL)
10071 #define TIMER3_CTRL_T3_RD_REQ_CONF_Pos (2UL)
10072 #define TIMER3_CTRL_T3_RD_REQ_CONF_Msk (0x4UL)
10073 #define TIMER3_CTRL_T3_RD_REQ_Pos (1UL)
10074 #define TIMER3_CTRL_T3_RD_REQ_Msk (0x2UL)
10075 #define TIMER3_CTRL_T3_PD_N_Pos (0UL)
10076 #define TIMER3_CTRL_T3_PD_N_Msk (0x1UL)
10077 /* ======================================================== ISRCLR ========================================================= */
10078 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Pos (7UL)
10079 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Msk (0x80UL)
10080 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Pos (5UL)
10081 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Msk (0x20UL)
10082 /* ======================================================= MODE_CONF ======================================================= */
10083 #define TIMER3_MODE_CONF_T3_SUBM_Pos (6UL)
10084 #define TIMER3_MODE_CONF_T3_SUBM_Msk (0xc0UL)
10085 #define TIMER3_MODE_CONF_T3M_Pos (0UL)
10086 #define TIMER3_MODE_CONF_T3M_Msk (0x3UL)
10087 /* ===================================================== T3_TRIGG_CTRL ===================================================== */
10088 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Pos (6UL)
10089 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Msk (0x40UL)
10090 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Pos (4UL)
10091 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Msk (0x30UL)
10092 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Pos (0UL)
10093 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Msk (0x7UL)
10096 /* =========================================================================================================================== */
10097 /* ================ UART1 ================ */
10098 /* =========================================================================================================================== */
10099 
10100 /* ========================================================= SBUF ========================================================== */
10101 #define UART1_SBUF_VAL_Pos (0UL)
10102 #define UART1_SBUF_VAL_Msk (0xffUL)
10103 /* ========================================================= SCON ========================================================== */
10104 #define UART1_SCON_RI_Pos (0UL)
10105 #define UART1_SCON_RI_Msk (0x1UL)
10106 #define UART1_SCON_TI_Pos (1UL)
10107 #define UART1_SCON_TI_Msk (0x2UL)
10108 #define UART1_SCON_RB8_Pos (2UL)
10109 #define UART1_SCON_RB8_Msk (0x4UL)
10110 #define UART1_SCON_TB8_Pos (3UL)
10111 #define UART1_SCON_TB8_Msk (0x8UL)
10112 #define UART1_SCON_REN_Pos (4UL)
10113 #define UART1_SCON_REN_Msk (0x10UL)
10114 #define UART1_SCON_SM2_Pos (5UL)
10115 #define UART1_SCON_SM2_Msk (0x20UL)
10116 #define UART1_SCON_SM1_Pos (6UL)
10117 #define UART1_SCON_SM1_Msk (0x40UL)
10118 #define UART1_SCON_SM0_Pos (7UL)
10119 #define UART1_SCON_SM0_Msk (0x80UL)
10120 /* ======================================================== SCONCLR ======================================================== */
10121 #define UART1_SCONCLR_RICLR_Pos (0UL)
10122 #define UART1_SCONCLR_RICLR_Msk (0x1UL)
10123 #define UART1_SCONCLR_TICLR_Pos (1UL)
10124 #define UART1_SCONCLR_TICLR_Msk (0x2UL)
10127 /* =========================================================================================================================== */
10128 /* ================ UART2 ================ */
10129 /* =========================================================================================================================== */
10130 
10131 /* ========================================================= SBUF ========================================================== */
10132 #define UART2_SBUF_VAL_Pos (0UL)
10133 #define UART2_SBUF_VAL_Msk (0xffUL)
10134 /* ========================================================= SCON ========================================================== */
10135 #define UART2_SCON_RI_Pos (0UL)
10136 #define UART2_SCON_RI_Msk (0x1UL)
10137 #define UART2_SCON_TI_Pos (1UL)
10138 #define UART2_SCON_TI_Msk (0x2UL)
10139 #define UART2_SCON_RB8_Pos (2UL)
10140 #define UART2_SCON_RB8_Msk (0x4UL)
10141 #define UART2_SCON_TB8_Pos (3UL)
10142 #define UART2_SCON_TB8_Msk (0x8UL)
10143 #define UART2_SCON_REN_Pos (4UL)
10144 #define UART2_SCON_REN_Msk (0x10UL)
10145 #define UART2_SCON_SM2_Pos (5UL)
10146 #define UART2_SCON_SM2_Msk (0x20UL)
10147 #define UART2_SCON_SM1_Pos (6UL)
10148 #define UART2_SCON_SM1_Msk (0x40UL)
10149 #define UART2_SCON_SM0_Pos (7UL)
10150 #define UART2_SCON_SM0_Msk (0x80UL)
10151 /* ======================================================== SCONCLR ======================================================== */
10152 #define UART2_SCONCLR_RICLR_Pos (0UL)
10153 #define UART2_SCONCLR_RICLR_Msk (0x1UL)
10154 #define UART2_SCONCLR_TICLR_Pos (1UL)
10155 #define UART2_SCONCLR_TICLR_Msk (0x2UL) /* End of group PosMask_peripherals */
10158 
10159 #ifdef __cplusplus
10160 }
10161 #endif
10162 
10163 #endif /* TLE987X_H */
10164 
10165  /* End of group TLE987x */
10167  /* End of group Infineon */
IRQn_Type
Definition: tle987x.h:93
@ PendSV_IRQn
Definition: tle987x.h:105
@ EXINT0_MON_Int
Definition: tle987x.h:120
@ SSC2_Int
Definition: tle987x.h:117
@ BDRV_CP_Int
Definition: tle987x.h:122
@ CCU6_SR2_Int
Definition: tle987x.h:114
@ GPT2_Int
Definition: tle987x.h:109
@ MemoryManagement_IRQn
Definition: tle987x.h:98
@ DMA_Int
Definition: tle987x.h:123
@ SVCall_IRQn
Definition: tle987x.h:103
@ Reset_IRQn
Definition: tle987x.h:95
@ SSC1_Int
Definition: tle987x.h:116
@ CCU6_SR0_Int
Definition: tle987x.h:112
@ UsageFault_IRQn
Definition: tle987x.h:102
@ SysTick_IRQn
Definition: tle987x.h:106
@ UART2_Tmr21_EINT2_Int
Definition: tle987x.h:119
@ BusFault_IRQn
Definition: tle987x.h:100
@ DebugMonitor_IRQn
Definition: tle987x.h:104
@ UART1_LIN_Tmr2_Int
Definition: tle987x.h:118
@ HardFault_IRQn
Definition: tle987x.h:97
@ CCU6_SR1_Int
Definition: tle987x.h:113
@ EXINT1_Int
Definition: tle987x.h:121
@ NonMaskableInt_IRQn
Definition: tle987x.h:96
@ ADC2_Tmr3_Int
Definition: tle987x.h:110
@ CCU6_SR3_Int
Definition: tle987x.h:115
@ GPT1_Int
Definition: tle987x.h:108
@ ADC1_VREF5_Int
Definition: tle987x.h:111
#define DMA
Definition: tle987x.h:6090
#define SCUPM
Definition: tle987x.h:6098
#define ADC34
Definition: tle987x.h:6085
#define TIMER21
Definition: tle987x.h:6102
#define MF
Definition: tle987x.h:6093
#define PORT
Definition: tle987x.h:6096
#define TIMER3
Definition: tle987x.h:6103
#define GPT12E
Definition: tle987x.h:6091
#define SSC2
Definition: tle987x.h:6100
#define UART2
Definition: tle987x.h:6105
#define UART1
Definition: tle987x.h:6104
#define BDRV
Definition: tle987x.h:6086
#define ADC1
Definition: tle987x.h:6083
#define MON
Definition: tle987x.h:6094
#define CCU6
Definition: tle987x.h:6087
#define CSA
Definition: tle987x.h:6088
#define ADC2
Definition: tle987x.h:6084
#define SSC1
Definition: tle987x.h:6099
#define TIMER2
Definition: tle987x.h:6101
#define PMU
Definition: tle987x.h:6095
#define CPU
Definition: tle987x.h:6089
#define SCU
Definition: tle987x.h:6097
#define LIN
Definition: tle987x.h:6092
#define __OM
Definition: tle987x.h:149
#define __IM
Definition: tle987x.h:146
#define __IOM
Definition: tle987x.h:152
ADC1 Module (ADC1)
Definition: tle987x.h:193
__IOM uint32_t CH0_IE
Definition: tle987x.h:511
__IM uint32_t OF7
Definition: tle987x.h:369
__OM uint32_t CH7_ICLR
Definition: tle987x.h:537
__IOM uint32_t IN_MUX_SEL
Definition: tle987x.h:205
__IM uint32_t VF8
Definition: tle987x.h:337
__IM uint32_t OUT_CH_EIM
Definition: tle987x.h:334
__OM uint32_t CH6_ICLR
Definition: tle987x.h:536
__IM uint32_t CH1_STS
Definition: tle987x.h:493
__IOM uint32_t SOC
Definition: tle987x.h:203
__IOM uint32_t SQ5
Definition: tle987x.h:276
__IM uint32_t CHNR
Definition: tle987x.h:480
__IM uint32_t VF6
Definition: tle987x.h:382
__IM uint32_t OUT_CH2
Definition: tle987x.h:435
__IOM uint32_t WFR0
Definition: tle987x.h:465
__IOM uint32_t WFR6
Definition: tle987x.h:381
__IOM uint32_t ch2
Definition: tle987x.h:292
__IOM uint32_t CH3_IE
Definition: tle987x.h:514
__IOM uint32_t ch0
Definition: tle987x.h:290
__IOM uint32_t ANON
Definition: tle987x.h:219
__IOM uint32_t ch3
Definition: tle987x.h:293
__IM uint32_t VF4
Definition: tle987x.h:410
__IOM uint32_t WFR5
Definition: tle987x.h:395
__IOM uint32_t SQ6
Definition: tle987x.h:277
__IOM uint32_t SQ2
Definition: tle987x.h:263
__IM uint32_t OF0
Definition: tle987x.h:467
__IM uint32_t OF6
Definition: tle987x.h:383
__IM uint32_t OF8
Definition: tle987x.h:338
__IOM uint32_t DIVA
Definition: tle987x.h:215
__OM uint32_t EIM_ICLR
Definition: tle987x.h:538
__OM uint32_t ESM_ICLR
Definition: tle987x.h:539
__IOM uint32_t ch7
Definition: tle987x.h:297
__IOM uint32_t WFR2
Definition: tle987x.h:437
__IOM uint32_t SQ1
Definition: tle987x.h:262
__IM uint32_t VF2
Definition: tle987x.h:438
__IM uint32_t BUSY
Definition: tle987x.h:477
__IM uint32_t
Definition: tle987x.h:202
__IOM uint32_t EIM_IE
Definition: tle987x.h:519
__IOM uint32_t ch4
Definition: tle987x.h:294
__IM uint32_t CHx
Definition: tle987x.h:355
__OM uint32_t CH1_ICLR
Definition: tle987x.h:531
__IM uint32_t CH7_STS
Definition: tle987x.h:499
__IM uint32_t VF0
Definition: tle987x.h:466
__IOM uint32_t REP
Definition: tle987x.h:232
__IM uint32_t OUT_CH4
Definition: tle987x.h:407
__OM uint32_t CH3_ICLR
Definition: tle987x.h:533
__OM uint32_t CH4_ICLR
Definition: tle987x.h:534
__IM uint32_t OF5
Definition: tle987x.h:397
__IM uint32_t OUT_CH6
Definition: tle987x.h:379
__IM uint32_t EIM_STS
Definition: tle987x.h:500
__IM uint32_t EOC
Definition: tle987x.h:204
__IOM uint32_t ESM_0
Definition: tle987x.h:246
__IM uint32_t SQx
Definition: tle987x.h:353
__IM uint32_t ESM_ACTIVE
Definition: tle987x.h:352
__IM uint32_t CH0_STS
Definition: tle987x.h:492
__IM uint32_t CH2_STS
Definition: tle987x.h:494
__IM uint32_t OF3
Definition: tle987x.h:425
__IOM uint32_t ch6
Definition: tle987x.h:296
__IM uint32_t OUT_CH5
Definition: tle987x.h:393
__IM uint32_t ANON_ST
Definition: tle987x.h:482
__IOM uint32_t SQ7
Definition: tle987x.h:278
__IM uint32_t VF1
Definition: tle987x.h:452
__IM uint32_t ESM_STS
Definition: tle987x.h:501
__IM uint32_t VF5
Definition: tle987x.h:396
__IOM uint32_t WFR8
Definition: tle987x.h:336
__IM uint32_t CH5_STS
Definition: tle987x.h:497
__IM uint32_t CH4_STS
Definition: tle987x.h:496
__IOM uint32_t ESM_IE
Definition: tle987x.h:520
__IOM uint32_t ch5
Definition: tle987x.h:295
__IOM uint32_t CH4_IE
Definition: tle987x.h:515
__IM uint32_t OF4
Definition: tle987x.h:411
__IOM uint32_t reg
Definition: tle987x.h:197
__IM uint32_t OUT_CH7
Definition: tle987x.h:365
__IM uint32_t VF7
Definition: tle987x.h:368
__IOM uint32_t PD_N
Definition: tle987x.h:201
__IM uint32_t OUT_CH1
Definition: tle987x.h:449
__OM uint32_t CH2_ICLR
Definition: tle987x.h:532
__IM uint32_t SAMPLE
Definition: tle987x.h:478
__IOM uint32_t WFR4
Definition: tle987x.h:409
__IM uint32_t OUT_CH3
Definition: tle987x.h:421
__IOM uint32_t CH6_IE
Definition: tle987x.h:517
__IOM uint32_t SQ_RUN
Definition: tle987x.h:350
__IOM uint32_t SQ8
Definition: tle987x.h:279
__IOM uint32_t CHx
Definition: tle987x.h:230
__IOM uint32_t WFR3
Definition: tle987x.h:423
__IOM uint32_t TRIG_SEL
Definition: tle987x.h:234
__IOM uint32_t SQ3
Definition: tle987x.h:264
__IOM uint32_t ch1
Definition: tle987x.h:291
__IM uint32_t RESERVED1
Definition: tle987x.h:282
__IM uint32_t OF2
Definition: tle987x.h:439
__IM uint32_t CH6_STS
Definition: tle987x.h:498
__IOM uint32_t WFR1
Definition: tle987x.h:451
__IOM uint32_t CH1_IE
Definition: tle987x.h:512
__IOM uint32_t CH2_IE
Definition: tle987x.h:513
__IOM uint32_t SQ4
Definition: tle987x.h:265
__IM uint32_t OUT_CH0
Definition: tle987x.h:463
__OM uint32_t CH5_ICLR
Definition: tle987x.h:535
__IOM uint32_t CH7_IE
Definition: tle987x.h:518
__OM uint32_t CH0_ICLR
Definition: tle987x.h:530
__IM uint32_t EIM_ACTIVE
Definition: tle987x.h:351
__IM uint32_t CH3_STS
Definition: tle987x.h:495
__IOM uint32_t CH5_IE
Definition: tle987x.h:516
__IOM uint32_t WFR7
Definition: tle987x.h:367
__IM uint32_t VF3
Definition: tle987x.h:424
__IM uint32_t OF1
Definition: tle987x.h:453
ADC2 Module (ADC2)
Definition: tle987x.h:556
__IOM uint32_t HYST_UP_CH2
Definition: tle987x.h:1103
__IOM uint32_t HYST_UP_CH3
Definition: tle987x.h:1106
__IOM uint32_t OFFS_CH3
Definition: tle987x.h:759
__IM uint32_t CNT_LO_CH6
Definition: tle987x.h:1076
__IM uint32_t SQ_FB
Definition: tle987x.h:575
__IOM uint32_t OFFS_CH5
Definition: tle987x.h:772
__IOM uint32_t GAIN_CH2
Definition: tle987x.h:758
__IOM uint32_t FILT_OUT_SEL_9_6
Definition: tle987x.h:658
__IOM uint32_t Ch0
Definition: tle987x.h:1150
__IOM uint32_t HYST_UP_CH1
Definition: tle987x.h:1100
__IOM uint32_t CNT_UP_CH5
Definition: tle987x.h:1119
__IM uint32_t GAIN_CH8
Definition: tle987x.h:797
__IOM uint32_t CH6
Definition: tle987x.h:992
__IM uint32_t GAIN_CH9
Definition: tle987x.h:799
__IOM uint32_t CH1
Definition: tle987x.h:810
__IM uint32_t CNT_LO_CH9
Definition: tle987x.h:1085
__IM uint32_t HYST_LO_CH6
Definition: tle987x.h:1077
__IM uint32_t OFFS_CH9
Definition: tle987x.h:798
__IOM uint32_t SQ5
Definition: tle987x.h:685
__IOM uint32_t CH3
Definition: tle987x.h:812
__IM uint32_t CNT_LO_CH7
Definition: tle987x.h:1079
__IM uint32_t SQ_STOP
Definition: tle987x.h:577
__IM uint32_t OUT_CH2
Definition: tle987x.h:857
__IM uint32_t GAIN_CH7
Definition: tle987x.h:786
__IOM uint32_t CNT_LO_CH1
Definition: tle987x.h:1045
__IM uint32_t CNT_UP_CH7
Definition: tle987x.h:1133
__IOM uint32_t SEL
Definition: tle987x.h:598
__IM uint32_t CH8
Definition: tle987x.h:826
__IM uint32_t HYST_LO_CH9
Definition: tle987x.h:1086
__IOM uint32_t CH9
Definition: tle987x.h:995
__IOM uint32_t SQ6
Definition: tle987x.h:687
__IM uint32_t HYST_UP_CH7
Definition: tle987x.h:1134
__IOM uint32_t GAIN_CH1
Definition: tle987x.h:747
__IM uint32_t STS
Definition: tle987x.h:618
__IOM uint32_t SQ2
Definition: tle987x.h:670
__IOM uint32_t CNT_UP_CH4
Definition: tle987x.h:1116
__IOM uint32_t FILT_OUT_SEL_5_0
Definition: tle987x.h:656
__IM uint32_t CH7
Definition: tle987x.h:825
__IOM uint32_t Ch1_EN
Definition: tle987x.h:938
__IM uint32_t CNT_LO_CH8
Definition: tle987x.h:1082
__IOM uint32_t CNT_UP_CH1
Definition: tle987x.h:1099
__IOM uint32_t HYST_LO_CH2
Definition: tle987x.h:1049
__IM uint32_t HYST_UP_CH6
Definition: tle987x.h:1131
__IOM uint32_t SQ1
Definition: tle987x.h:668
__IM uint32_t
Definition: tle987x.h:564
__IOM uint32_t GAIN_CH5
Definition: tle987x.h:773
__IM uint32_t OUT_CH9
Definition: tle987x.h:927
__IOM uint32_t Ch4_EN
Definition: tle987x.h:941
__IOM uint32_t CNT_UP_CH3
Definition: tle987x.h:1105
__IOM uint32_t OFFS_CH2
Definition: tle987x.h:757
__IOM uint32_t GAIN_CH4
Definition: tle987x.h:771
__IM uint32_t HYST_UP_CH9
Definition: tle987x.h:1140
__IOM uint32_t SEL_TS_COUNT
Definition: tle987x.h:646
__IM uint32_t CHx
Definition: tle987x.h:582
__IM uint32_t SQ5_int
Definition: tle987x.h:719
__IOM uint32_t REP
Definition: tle987x.h:595
__IM uint32_t OUT_CH4
Definition: tle987x.h:877
__IOM uint32_t CH8
Definition: tle987x.h:994
__IOM uint32_t CH5
Definition: tle987x.h:814
__IM uint32_t OFFS_CH6
Definition: tle987x.h:783
__IOM uint32_t HYST_LO_CH5
Definition: tle987x.h:1066
__IOM uint32_t OFFS_CH1
Definition: tle987x.h:746
__IM uint32_t CH6
Definition: tle987x.h:824
__IM uint32_t READY
Definition: tle987x.h:1167
__IM uint32_t OUT_CH6
Definition: tle987x.h:897
__IOM uint32_t HYST_LO_CH1
Definition: tle987x.h:1046
__IM uint32_t SQ1_int
Definition: tle987x.h:715
__IOM uint32_t Ch4
Definition: tle987x.h:1154
__IOM uint32_t CNT_LO_CH2
Definition: tle987x.h:1048
__IOM uint32_t ESM_0
Definition: tle987x.h:610
__IM uint32_t SQx
Definition: tle987x.h:580
__IOM uint32_t CNT_UP_CH0
Definition: tle987x.h:1096
__IM uint32_t SQ6_int
Definition: tle987x.h:720
__IOM uint32_t Ch3
Definition: tle987x.h:1153
__IOM uint32_t Ch1
Definition: tle987x.h:1151
__IOM uint32_t Ch2_EN
Definition: tle987x.h:939
__IM uint32_t SQ3_int
Definition: tle987x.h:717
__IOM uint32_t SQ9
Definition: tle987x.h:702
__IOM uint32_t GAIN_CH0
Definition: tle987x.h:745
__IM uint32_t ESM_ACTIVE
Definition: tle987x.h:579
__IOM uint32_t TSENSE_SD_SEL
Definition: tle987x.h:641
__IOM uint32_t Ch2
Definition: tle987x.h:1152
__IOM uint32_t SAMPLE_TIME_int
Definition: tle987x.h:644
__IOM uint32_t CNT_LO_CH4
Definition: tle987x.h:1062
__IOM uint32_t ESM_1
Definition: tle987x.h:612
__IM uint32_t CNT_UP_CH9
Definition: tle987x.h:1139
__IM uint32_t CH9
Definition: tle987x.h:827
__IOM uint32_t Ch5
Definition: tle987x.h:1155
__IM uint32_t OUT_CH5
Definition: tle987x.h:887
__IOM uint32_t Ch0_EN
Definition: tle987x.h:937
__IOM uint32_t SQ7
Definition: tle987x.h:689
__IOM uint32_t CALIB_EN
Definition: tle987x.h:629
__IOM uint32_t HYST_LO_CH4
Definition: tle987x.h:1063
__IOM uint32_t SQ10
Definition: tle987x.h:704
__IM uint32_t MCM_RDY
Definition: tle987x.h:643
__IM uint32_t RESERVED
Definition: tle987x.h:621
__IM uint32_t SQ4_int
Definition: tle987x.h:718
__IOM uint32_t Ch5_EN
Definition: tle987x.h:942
__IOM uint32_t CH2
Definition: tle987x.h:811
__IM uint32_t SQ9_int
Definition: tle987x.h:733
__IM uint32_t GAIN_CH6
Definition: tle987x.h:784
__IM uint32_t SQ10_int
Definition: tle987x.h:734
__IOM uint32_t CH4
Definition: tle987x.h:813
__IM uint32_t OUT_CH8
Definition: tle987x.h:917
__IOM uint32_t reg
Definition: tle987x.h:560
__IOM uint32_t CNT_UP_CH2
Definition: tle987x.h:1102
__IM uint32_t OUT_CH7
Definition: tle987x.h:907
__IOM uint32_t EN
Definition: tle987x.h:596
__IM uint32_t OFFS_CH7
Definition: tle987x.h:785
__IOM uint32_t CNT_LO_CH5
Definition: tle987x.h:1065
__IOM uint32_t TS_SD_SEL_CONF
Definition: tle987x.h:640
__IOM uint32_t CNT_LO_CH0
Definition: tle987x.h:1042
__IM uint32_t CNT_UP_CH8
Definition: tle987x.h:1136
__IM uint32_t SQ8_int
Definition: tle987x.h:722
__IOM uint32_t CH0
Definition: tle987x.h:809
__IOM uint32_t HYST_LO_CH0
Definition: tle987x.h:1043
__IOM uint32_t GAIN_CH3
Definition: tle987x.h:760
__IM uint32_t SQ7_int
Definition: tle987x.h:721
__IM uint32_t OUT_CH1
Definition: tle987x.h:847
__IM uint32_t OFFS_CH8
Definition: tle987x.h:796
__IM uint32_t OUT_CH3
Definition: tle987x.h:867
__IM uint32_t HYST_LO_CH8
Definition: tle987x.h:1083
__IM uint32_t HYST_UP_CH8
Definition: tle987x.h:1137
__IOM uint32_t HYST_UP_CH4
Definition: tle987x.h:1117
__IOM uint32_t SQ8
Definition: tle987x.h:691
__IOM uint32_t CHx
Definition: tle987x.h:593
__IM uint32_t HYST_LO_CH7
Definition: tle987x.h:1080
__IOM uint32_t SQ3
Definition: tle987x.h:672
__IOM uint32_t MCM_PD_N
Definition: tle987x.h:639
__IOM uint32_t HYST_LO_CH3
Definition: tle987x.h:1052
__IOM uint32_t CNT_LO_CH3
Definition: tle987x.h:1051
__IM uint32_t CNT_UP_CH6
Definition: tle987x.h:1130
__IOM uint32_t OFFS_CH0
Definition: tle987x.h:744
__IOM uint32_t SQ4
Definition: tle987x.h:674
__IOM uint32_t VS_RANGE
Definition: tle987x.h:565
__IOM uint32_t OFFS_CH4
Definition: tle987x.h:770
__IM uint32_t SQ2_int
Definition: tle987x.h:716
__IM uint32_t OUT_CH0
Definition: tle987x.h:837
__IOM uint32_t HYST_UP_CH5
Definition: tle987x.h:1120
__IM uint32_t EIM_ACTIVE
Definition: tle987x.h:578
__IOM uint32_t Ch3_EN
Definition: tle987x.h:940
__IOM uint32_t HYST_UP_CH0
Definition: tle987x.h:1097
ADC34 (ADC34)
Definition: tle987x.h:1184
__IOM uint32_t ADC4_SOC
Definition: tle987x.h:1204
__IOM uint32_t ADC4_OSR
Definition: tle987x.h:1211
__IM uint32_t ADC4_EoC_STS
Definition: tle987x.h:1207
__IM uint32_t ADC4_RESU
Definition: tle987x.h:1222
__IOM uint32_t ADC34_DITHVAL
Definition: tle987x.h:1210
__IOM uint32_t ADC3_SOC
Definition: tle987x.h:1194
__IM uint32_t ADC34_DREQ_SEL
Definition: tle987x.h:1198
__IM uint32_t
Definition: tle987x.h:1196
__IOM uint32_t ADC34_DITHEN
Definition: tle987x.h:1209
__IOM uint32_t ADC3_EN
Definition: tle987x.h:1192
__IM uint32_t ADC3_EoC_STS
Definition: tle987x.h:1197
__IOM uint32_t ADC34_REF_SEL
Definition: tle987x.h:1200
__IOM uint32_t ADC3_OSR
Definition: tle987x.h:1201
__IOM uint32_t ADC4_EN
Definition: tle987x.h:1202
__IOM uint32_t reg
Definition: tle987x.h:1188
__IOM uint32_t ADC4_OFS_MEAS_EN
Definition: tle987x.h:1203
__IOM uint32_t ADC3_OFS_MEAS_EN
Definition: tle987x.h:1193
__IOM uint32_t ADC34_EoC_CNT
Definition: tle987x.h:1208
__IM uint32_t ADC3_RESU
Definition: tle987x.h:1221
Bridge Driver (BDRV)
Definition: tle987x.h:1239
__IM uint32_t HS3_DS_STS
Definition: tle987x.h:1303
__IOM uint32_t LS1_PWM
Definition: tle987x.h:1248
__IOM uint32_t DRV_ON_I_3
Definition: tle987x.h:1364
__IOM uint32_t HS3_PWM
Definition: tle987x.h:1300
__IOM uint32_t DITH_LOWER
Definition: tle987x.h:1439
__IM uint32_t HS1_DS_STS
Definition: tle987x.h:1268
__IOM uint32_t HS2_DCS_EN
Definition: tle987x.h:1276
__IOM uint32_t LS2_PWM
Definition: tle987x.h:1256
__IOM uint32_t HS3DRV_FDISCHG_DIS
Definition: tle987x.h:1395
__IOM uint32_t ICHARGEDIV2_N
Definition: tle987x.h:1323
__IOM uint32_t LS2_OC_DIS
Definition: tle987x.h:1263
__IM uint32_t HS3_OC_STS
Definition: tle987x.h:1305
__IOM uint32_t LS3DRV_FDISCHG_DIS
Definition: tle987x.h:1387
__IOM uint32_t HS1_DCS_EN
Definition: tle987x.h:1267
__IOM uint32_t LS3_ON
Definition: tle987x.h:1293
__IM uint32_t LS1_OC_STS
Definition: tle987x.h:1253
__IOM uint32_t DITH_UPPER
Definition: tle987x.h:1441
__IM uint32_t VSD_LOTH_STS
Definition: tle987x.h:1424
__IOM uint32_t LS1_EN
Definition: tle987x.h:1247
__IOM uint32_t CPLOPWRM_EN
Definition: tle987x.h:1427
__IM uint32_t LS2_DS_STS
Definition: tle987x.h:1259
__IM uint32_t HS2_SUPERR_STS
Definition: tle987x.h:1279
__IOM uint32_t LS3DRV_OCSDN_DIS
Definition: tle987x.h:1390
__IOM uint32_t DRV_OFF_I_2
Definition: tle987x.h:1349
__IOM uint32_t HS3_OC_DIS
Definition: tle987x.h:1306
__IM uint32_t LS2_SUPERR_STS
Definition: tle987x.h:1261
__IOM uint32_t ICHARGE_TRIM
Definition: tle987x.h:1321
__IOM uint32_t HS3_ON
Definition: tle987x.h:1301
__IOM uint32_t HSDRV_DS_TFILT_SEL
Definition: tle987x.h:1391
__IOM uint32_t DRV_ON_t_3
Definition: tle987x.h:1363
__IOM uint32_t LS1DRV_OCSDN_DIS
Definition: tle987x.h:1388
__IM uint32_t HS3_SUPERR_STS
Definition: tle987x.h:1304
__IOM uint32_t LS2DRV_OCSDN_DIS
Definition: tle987x.h:1389
__IM uint32_t HS1_SUPERR_STS
Definition: tle987x.h:1270
__IM uint32_t LS1_DS_STS
Definition: tle987x.h:1251
__IOM uint32_t LS2_DCS_EN
Definition: tle987x.h:1258
__IOM uint32_t DRV_OFF_t_4
Definition: tle987x.h:1344
__IOM uint32_t VCP9V_SET
Definition: tle987x.h:1428
__IOM uint32_t HS3_EN
Definition: tle987x.h:1299
__IOM uint32_t DRV_ON_I_1
Definition: tle987x.h:1368
__IM uint32_t DLY_DIAG_TIM
Definition: tle987x.h:1307
__IOM uint32_t DRVx_VSDUP_DIS
Definition: tle987x.h:1425
__IOM uint32_t HS2DRV_FDISCHG_DIS
Definition: tle987x.h:1394
__IOM uint32_t HS1_PWM
Definition: tle987x.h:1265
__IOM uint32_t DRV_ON_I_4
Definition: tle987x.h:1362
__IOM uint32_t LS2DRV_FDISCHG_DIS
Definition: tle987x.h:1386
__IOM uint32_t LS3_PWM
Definition: tle987x.h:1292
__IOM uint32_t LS2_ON
Definition: tle987x.h:1257
__IOM uint32_t HS1_EN
Definition: tle987x.h:1264
__IOM uint32_t HS3DRV_OCSDN_DIS
Definition: tle987x.h:1398
__IOM uint32_t F_CP
Definition: tle987x.h:1442
__IOM uint32_t DRV_CCP_TIMSEL
Definition: tle987x.h:1332
__IM uint32_t HS1_OC_STS
Definition: tle987x.h:1271
__IM uint32_t
Definition: tle987x.h:1322
__IOM uint32_t DRV_OFF_t_2
Definition: tle987x.h:1348
__OM uint32_t DLY_DIAG_SCLR
Definition: tle987x.h:1308
__IOM uint32_t HS1_ON
Definition: tle987x.h:1266
__IOM uint32_t OFF_SEQ_EN
Definition: tle987x.h:1328
__IOM uint32_t LS_HS_BT_TFILT_SEL
Definition: tle987x.h:1378
__IOM uint32_t LS3_OC_DIS
Definition: tle987x.h:1298
__IOM uint32_t HS3_DCS_EN
Definition: tle987x.h:1302
__IOM uint32_t DRV_OFF_I_1
Definition: tle987x.h:1351
__IOM uint32_t DRV_ON_t_1
Definition: tle987x.h:1367
__IOM uint32_t DLY_DIAG_DIRSEL
Definition: tle987x.h:1311
__IOM uint32_t DRV_CCP_DIS
Definition: tle987x.h:1333
__IOM uint32_t HS2_PWM
Definition: tle987x.h:1274
__IOM uint32_t HS2_EN
Definition: tle987x.h:1273
__IOM uint32_t HS2_ON
Definition: tle987x.h:1275
__IOM uint32_t CPLOW_TFILT_SEL
Definition: tle987x.h:1399
__IM uint32_t VCP_LOTH1_STS
Definition: tle987x.h:1420
__IM uint32_t LS3_SUPERR_STS
Definition: tle987x.h:1296
__IOM uint32_t IDISCHARGE_TRIM
Definition: tle987x.h:1325
__IM uint32_t VCP_UPTH_STS
Definition: tle987x.h:1422
__IOM uint32_t LS3_EN
Definition: tle987x.h:1291
__IOM uint32_t HS1_OC_DIS
Definition: tle987x.h:1272
__IOM uint32_t CP_RDY_EN
Definition: tle987x.h:1412
__IOM uint32_t LS1_DCS_EN
Definition: tle987x.h:1250
__IOM uint32_t CPCLK_EN
Definition: tle987x.h:1443
__IOM uint32_t DRV_ON_t_2
Definition: tle987x.h:1365
__IM uint32_t DLY_DIAG_STS
Definition: tle987x.h:1309
__IOM uint32_t DRV_OFF_t_3
Definition: tle987x.h:1346
__IOM uint32_t DRV_CCPTIMMUL
Definition: tle987x.h:1381
__IOM uint32_t DRV_OFF_t_1
Definition: tle987x.h:1350
__IM uint32_t RESERVED
Definition: tle987x.h:1336
__IOM uint32_t LS1_OC_DIS
Definition: tle987x.h:1254
__IOM uint32_t LS1_ON
Definition: tle987x.h:1249
__IOM uint32_t DLY_DIAG_CHSEL
Definition: tle987x.h:1310
__IM uint32_t LS1_SUPERR_STS
Definition: tle987x.h:1252
__IOM uint32_t DRV_ON_t_4
Definition: tle987x.h:1361
__IM uint32_t HS2_DS_STS
Definition: tle987x.h:1277
__IOM uint32_t reg
Definition: tle987x.h:1243
__IOM uint32_t DRV_OFF_I_3
Definition: tle987x.h:1347
__IM uint32_t VSD_UPTH_STS
Definition: tle987x.h:1426
__IOM uint32_t HS1DRV_FDISCHG_DIS
Definition: tle987x.h:1393
__IM uint32_t VCP_LOTH2_STS
Definition: tle987x.h:1414
__IOM uint32_t VTHVCP9V_TRIM
Definition: tle987x.h:1429
__IOM uint32_t CP_EN
Definition: tle987x.h:1410
__IOM uint32_t DRVx_VSDLO_DIS
Definition: tle987x.h:1423
__IM uint32_t LS3_DS_STS
Definition: tle987x.h:1295
__IOM uint32_t DRVx_VCPUP_DIS
Definition: tle987x.h:1421
__IOM uint32_t LS3_DCS_EN
Definition: tle987x.h:1294
__IOM uint32_t LS2_EN
Definition: tle987x.h:1255
__IOM uint32_t LS1DRV_FDISCHG_DIS
Definition: tle987x.h:1385
__IOM uint32_t HS2DRV_OCSDN_DIS
Definition: tle987x.h:1397
__IOM uint32_t HS2_OC_DIS
Definition: tle987x.h:1281
__IM uint32_t RESERVED1
Definition: tle987x.h:1402
__IOM uint32_t IDISCHARGEDIV2_N
Definition: tle987x.h:1327
__IOM uint32_t DSMONVTH
Definition: tle987x.h:1329
__IOM uint32_t VCP_LOWTH2
Definition: tle987x.h:1416
__IOM uint32_t DRV_OFF_I_4
Definition: tle987x.h:1345
__IOM uint32_t HS1DRV_OCSDN_DIS
Definition: tle987x.h:1396
__IM uint32_t HS2_OC_STS
Definition: tle987x.h:1280
__IOM uint32_t ON_SEQ_EN
Definition: tle987x.h:1324
__IOM uint32_t DRVx_VCPLO_DIS
Definition: tle987x.h:1419
__IOM uint32_t DRV_ON_I_2
Definition: tle987x.h:1366
__IM uint32_t LS3_OC_STS
Definition: tle987x.h:1297
__IOM uint32_t LSDRV_DS_TFILT_SEL
Definition: tle987x.h:1384
__IM uint32_t LS2_OC_STS
Definition: tle987x.h:1262
Capture Compare Unit 6 (CCU6)
Definition: tle987x.h:1460
__IOM uint16_t T13MODEN
Definition: tle987x.h:1853
__IOM uint16_t INPCC62
Definition: tle987x.h:1762
__IOM uint16_t INPCHE
Definition: tle987x.h:1763
__IM uint16_t CC63ST
Definition: tle987x.h:1985
__IOM uint16_t ECT13O
Definition: tle987x.h:1855
__IOM uint16_t DTE2
Definition: tle987x.h:1645
__OM uint16_t MCC63R
Definition: tle987x.h:1564
__IOM uint16_t STRMCM
Definition: tle987x.h:1506
__OM uint16_t RT12PM
Definition: tle987x.h:1528
__IM uint16_t CHE
Definition: tle987x.h:1910
__OM uint16_t RCHE
Definition: tle987x.h:1533
__OM uint16_t MCC62S
Definition: tle987x.h:1551
__IOM uint16_t DBYP
Definition: tle987x.h:1717
__IOM uint16_t ENCC62R
Definition: tle987x.h:1736
__IM uint16_t T13R
Definition: tle987x.h:1668
__IOM uint16_t INPCC60
Definition: tle987x.h:1760
__IOM uint16_t ENT13PM
Definition: tle987x.h:1743
__IOM uint16_t ISCC61
Definition: tle987x.h:1925
__OM uint16_t RTRPF
Definition: tle987x.h:1531
__OM uint16_t T12RS
Definition: tle987x.h:1480
__IM uint16_t T12OM
Definition: tle987x.h:1904
__IM uint16_t IDLE
Definition: tle987x.h:1912
__IM uint16_t RESERVED26
Definition: tle987x.h:1916
__IM uint16_t DTR2
Definition: tle987x.h:1649
__IOM uint16_t T12PV
Definition: tle987x.h:1620
__OM uint16_t T13STD
Definition: tle987x.h:1493
__IM uint16_t RESERVED19
Definition: tle987x.h:1795
__IOM uint16_t ISPOS2
Definition: tle987x.h:1930
__IOM uint16_t T13TEC
Definition: tle987x.h:1835
__IM uint16_t RESERVED12
Definition: tle987x.h:1672
__IOM uint16_t T13RSEL
Definition: tle987x.h:1839
__OM uint16_t MCC60S
Definition: tle987x.h:1547
__IOM uint16_t T12MODEN
Definition: tle987x.h:1850
__IOM uint16_t INPT13
Definition: tle987x.h:1766
__OM uint16_t RCC62R
Definition: tle987x.h:1525
__IM uint16_t RESERVED13
Definition: tle987x.h:1683
__IM uint16_t CCV
Definition: tle987x.h:1468
__OM uint16_t SCHE
Definition: tle987x.h:1789
__IOM uint16_t ENIDLE
Definition: tle987x.h:1748
__IOM uint16_t ISPOS1
Definition: tle987x.h:1929
__IOM uint16_t PSL
Definition: tle987x.h:1803
__IOM uint16_t T12EXT
Definition: tle987x.h:1945
__IOM uint16_t T13CLK
Definition: tle987x.h:1666
__OM uint16_t ST12PM
Definition: tle987x.h:1784
__IOM uint16_t CC61PS
Definition: tle987x.h:1989
__OM uint16_t ST12OM
Definition: tle987x.h:1783
__OM uint16_t T12RES
Definition: tle987x.h:1481
__IM uint16_t RESERVED22
Definition: tle987x.h:1842
__OM uint16_t T12RR
Definition: tle987x.h:1479
__IOM uint16_t T12PRE
Definition: tle987x.h:1661
__IM uint16_t ICC60R
Definition: tle987x.h:1898
__IOM uint16_t HSYNC
Definition: tle987x.h:1716
__IOM uint16_t T13IM
Definition: tle987x.h:1994
__OM uint16_t SSTR
Definition: tle987x.h:1792
__OM uint16_t SCC61F
Definition: tle987x.h:1780
__IM uint16_t RESERVED8
Definition: tle987x.h:1612
__IM uint16_t STE13
Definition: tle987x.h:1669
__IOM uint16_t CTM
Definition: tle987x.h:1665
__IM uint16_t T12PM
Definition: tle987x.h:1905
__OM uint16_t MCC60R
Definition: tle987x.h:1557
__OM uint16_t SWHE
Definition: tle987x.h:1790
__IOM uint16_t DTE1
Definition: tle987x.h:1644
__OM uint16_t T13STR
Definition: tle987x.h:1492
__OM uint16_t MCC62R
Definition: tle987x.h:1561
__IOM uint16_t INPERR
Definition: tle987x.h:1764
__IM uint16_t RESERVED4
Definition: tle987x.h:1568
__OM uint16_t SCC62R
Definition: tle987x.h:1781
__OM uint16_t RCC60F
Definition: tle987x.h:1522
__IM uint16_t ICC60F
Definition: tle987x.h:1899
__IOM uint16_t DTM
Definition: tle987x.h:1642
__IM uint16_t STE12
Definition: tle987x.h:1663
__IOM uint16_t COUT60PS
Definition: tle987x.h:1988
__IOM uint16_t STE12D
Definition: tle987x.h:1821
__IOM uint16_t EXPHS
Definition: tle987x.h:1507
__IM uint16_t
Definition: tle987x.h:1483
__OM uint16_t RT12OM
Definition: tle987x.h:1527
__IOM uint16_t ISTRP
Definition: tle987x.h:1927
__OM uint16_t T13CNT
Definition: tle987x.h:1491
__IOM uint16_t ENCC60F
Definition: tle987x.h:1730
__IM uint16_t CCPOS2
Definition: tle987x.h:1984
__OM uint16_t RCC62F
Definition: tle987x.h:1526
__IOM uint16_t COUT63PS
Definition: tle987x.h:1993
__IOM uint16_t T12SSC
Definition: tle987x.h:1833
__OM uint16_t RCC60R
Definition: tle987x.h:1521
__IOM uint16_t SWSEL
Definition: tle987x.h:1816
__IM uint16_t TRPF
Definition: tle987x.h:1908
__IM uint16_t RESERVED10
Definition: tle987x.h:1634
__OM uint16_t SIDLE
Definition: tle987x.h:1791
__OM uint16_t STRPF
Definition: tle987x.h:1787
__OM uint16_t RWHE
Definition: tle987x.h:1534
__IOM uint16_t ENT12PM
Definition: tle987x.h:1741
__OM uint16_t MCC63S
Definition: tle987x.h:1554
__IOM uint16_t ENCC61F
Definition: tle987x.h:1734
__IM uint16_t RESERVED20
Definition: tle987x.h:1808
__IM uint16_t ICC62F
Definition: tle987x.h:1903
__IM uint16_t R
Definition: tle987x.h:1884
__OM uint16_t MCC61S
Definition: tle987x.h:1549
__IM uint16_t T12R
Definition: tle987x.h:1662
__IM uint16_t CCPOS0
Definition: tle987x.h:1982
__OM uint16_t ST13PM
Definition: tle987x.h:1786
__IOM uint16_t TRPM1
Definition: tle987x.h:1867
__OM uint16_t SWHC
Definition: tle987x.h:1788
__IM uint16_t RESERVED28
Definition: tle987x.h:1949
__IM uint16_t RESERVED14
Definition: tle987x.h:1694
__IOM uint16_t reg
Definition: tle987x.h:1464
__IOM uint16_t MSEL60
Definition: tle987x.h:1713
__IOM uint16_t COUT62PS
Definition: tle987x.h:1992
__IM uint16_t RESERVED25
Definition: tle987x.h:1890
__IOM uint16_t ISCNT13
Definition: tle987x.h:1944
__IOM uint16_t ENWHE
Definition: tle987x.h:1747
__IM uint16_t CCPOS1
Definition: tle987x.h:1983
__IM uint16_t RESERVED30
Definition: tle987x.h:1971
__OM uint16_t T13RS
Definition: tle987x.h:1488
__OM uint16_t RSTR
Definition: tle987x.h:1536
__IM uint16_t CDIR
Definition: tle987x.h:1664
__IOM uint16_t IST13HR
Definition: tle987x.h:1942
__OM uint16_t SCC61R
Definition: tle987x.h:1779
__IM uint16_t CC62ST
Definition: tle987x.h:1981
__OM uint16_t T12STR
Definition: tle987x.h:1485
__IM uint16_t RESERVED6
Definition: tle987x.h:1590
__IM uint16_t DTR1
Definition: tle987x.h:1648
__OM uint16_t T12CNT
Definition: tle987x.h:1484
__OM uint16_t SCC60F
Definition: tle987x.h:1778
__IOM uint16_t MCMPS
Definition: tle987x.h:1504
__IOM uint16_t T12CV
Definition: tle987x.h:1957
__IOM uint16_t STE13U
Definition: tle987x.h:1822
__IOM uint16_t ENCC60R
Definition: tle987x.h:1728
__OM uint16_t RCC61F
Definition: tle987x.h:1524
__IOM uint16_t ENCC61R
Definition: tle987x.h:1732
__IOM uint16_t CC60PS
Definition: tle987x.h:1987
__IM uint16_t DTR0
Definition: tle987x.h:1647
__IOM uint16_t T13EXT
Definition: tle987x.h:1946
__IOM uint16_t IST12HR
Definition: tle987x.h:1931
__IOM uint16_t T13SSC
Definition: tle987x.h:1834
__IOM uint16_t INPCC61
Definition: tle987x.h:1761
__OM uint16_t RCC61R
Definition: tle987x.h:1523
__IM uint16_t CC60ST
Definition: tle987x.h:1979
__IOM uint16_t MCMEN
Definition: tle987x.h:1852
__IOM uint16_t ENTRPF
Definition: tle987x.h:1744
__IM uint16_t RESERVED11
Definition: tle987x.h:1652
__IOM uint16_t TRPPEN
Definition: tle987x.h:1872
__IOM uint16_t CCS
Definition: tle987x.h:1576
__IOM uint16_t ENT13CM
Definition: tle987x.h:1742
__IM uint16_t MCMP
Definition: tle987x.h:1883
__IOM uint16_t T12CLK
Definition: tle987x.h:1660
__IM uint16_t RESERVED29
Definition: tle987x.h:1960
__IOM uint16_t TRPEN13
Definition: tle987x.h:1871
__IOM uint16_t CURHS
Definition: tle987x.h:1508
__OM uint16_t ST13CM
Definition: tle987x.h:1785
__IM uint16_t CC61ST
Definition: tle987x.h:1980
__IOM uint16_t T13TED
Definition: tle987x.h:1836
__IOM uint16_t CC62PS
Definition: tle987x.h:1991
__IOM uint16_t TRPEN
Definition: tle987x.h:1870
__OM uint16_t SCC62F
Definition: tle987x.h:1782
__IOM uint16_t T13PRE
Definition: tle987x.h:1667
__IOM uint16_t ISCNT12
Definition: tle987x.h:1943
__IOM uint16_t COUT61PS
Definition: tle987x.h:1990
__IM uint16_t STR
Definition: tle987x.h:1913
__IM uint16_t RESERVED23
Definition: tle987x.h:1858
__IM uint16_t RESERVED18
Definition: tle987x.h:1769
__IM uint16_t T13CM
Definition: tle987x.h:1906
__IOM uint16_t TRPM0
Definition: tle987x.h:1866
__IM uint16_t T13PM
Definition: tle987x.h:1907
__IM uint16_t CURH
Definition: tle987x.h:1887
__IM uint16_t RESERVED5
Definition: tle987x.h:1579
__IOM uint16_t DTE0
Definition: tle987x.h:1643
__IM uint16_t WHE
Definition: tle987x.h:1911
__IM uint16_t RESERVED17
Definition: tle987x.h:1752
__IOM uint16_t INPT12
Definition: tle987x.h:1765
__IOM uint16_t T13PV
Definition: tle987x.h:1631
__OM uint16_t T12STD
Definition: tle987x.h:1486
__OM uint16_t DTRES
Definition: tle987x.h:1482
__OM uint16_t MCC61R
Definition: tle987x.h:1559
__OM uint16_t T13RES
Definition: tle987x.h:1489
__OM uint16_t RIDLE
Definition: tle987x.h:1535
__IM uint16_t RESERVED9
Definition: tle987x.h:1623
__IOM uint16_t T13CV
Definition: tle987x.h:1968
__IOM uint16_t ENCC62F
Definition: tle987x.h:1738
__IOM uint16_t ENCHE
Definition: tle987x.h:1746
__IM uint16_t RESERVED1
Definition: tle987x.h:1496
__IOM uint16_t ISCC60
Definition: tle987x.h:1924
__IOM uint16_t TRPM2
Definition: tle987x.h:1868
__IOM uint16_t T12RSEL
Definition: tle987x.h:1838
__OM uint16_t SCC60R
Definition: tle987x.h:1777
__OM uint16_t RT13CM
Definition: tle987x.h:1529
__IOM uint16_t ENT12OM
Definition: tle987x.h:1740
__IOM uint16_t PSL63
Definition: tle987x.h:1805
__IM uint16_t RESERVED7
Definition: tle987x.h:1601
__IM uint16_t RESERVED15
Definition: tle987x.h:1705
__IM uint16_t RESERVED3
Definition: tle987x.h:1539
__IM uint16_t RESERVED21
Definition: tle987x.h:1825
__IOM uint16_t STE12U
Definition: tle987x.h:1820
__IM uint16_t EXPH
Definition: tle987x.h:1886
__IM uint16_t RESERVED
Definition: tle987x.h:1471
__IOM uint16_t STRHP
Definition: tle987x.h:1510
__IM uint16_t ICC62R
Definition: tle987x.h:1902
__IOM uint16_t ISPOS0
Definition: tle987x.h:1928
__IOM uint16_t ISCC62
Definition: tle987x.h:1926
__IM uint16_t ICC61R
Definition: tle987x.h:1900
__IM uint16_t RESERVED2
Definition: tle987x.h:1513
__IOM uint16_t SWSYN
Definition: tle987x.h:1818
__OM uint16_t RT13PM
Definition: tle987x.h:1530
__IM uint16_t RESERVED24
Definition: tle987x.h:1875
__IM uint16_t TRPS
Definition: tle987x.h:1909
__IM uint16_t RESERVED16
Definition: tle987x.h:1720
__OM uint16_t T13RR
Definition: tle987x.h:1487
__IM uint16_t ICC61F
Definition: tle987x.h:1901
__IOM uint16_t MSEL61
Definition: tle987x.h:1714
__IOM uint16_t ENSTR
Definition: tle987x.h:1749
__IOM uint16_t MSEL62
Definition: tle987x.h:1715
CPU Core (CPU)
Definition: tle987x.h:2011
__IM uint32_t Int_DMA
Definition: tle987x.h:2198
__IOM uint32_t CP10
Definition: tle987x.h:2512
__IM uint32_t Int_GPT2
Definition: tle987x.h:2184
__IOM uint32_t PRI_CCU6SR1
Definition: tle987x.h:2223
__IOM uint32_t SVCALLPENDED
Definition: tle987x.h:2412
__IOM uint32_t PRI_6
Definition: tle987x.h:2362
__IOM uint32_t Int_CCU6SR2
Definition: tle987x.h:2085
__IOM uint32_t RELOAD
Definition: tle987x.h:2045
__IOM uint32_t CLKSOURCE
Definition: tle987x.h:2033
__IM uint32_t Int_GPT1
Definition: tle987x.h:2183
__IOM uint32_t DWTTRAP
Definition: tle987x.h:2471
__IOM uint32_t PRI_GPT1
Definition: tle987x.h:2209
__IOM uint32_t CP0
Definition: tle987x.h:2503
__IOM uint32_t PRI_BDRV
Definition: tle987x.h:2250
__IOM uint32_t DIVBYZERO
Definition: tle987x.h:2445
__IOM uint32_t USGFAULTACT
Definition: tle987x.h:2402
__IOM uint32_t DEBUGEVT
Definition: tle987x.h:2459
__IOM uint32_t PRI_ADC2
Definition: tle987x.h:2211
__IOM uint32_t PRI_8
Definition: tle987x.h:2373
__IOM uint32_t DIV_0_TRP
Definition: tle987x.h:2345
__IOM uint32_t CP3
Definition: tle987x.h:2506
__IM uint32_t Int_CCU6SR0
Definition: tle987x.h:2187
__IOM uint32_t Int_SSC1
Definition: tle987x.h:2087
__IOM uint32_t PRI_UART2
Definition: tle987x.h:2238
__IM uint32_t Int_ADC2
Definition: tle987x.h:2185
__IOM uint32_t TBLOFF
Definition: tle987x.h:2300
__IOM uint32_t EXTERNAL
Definition: tle987x.h:2473
__IOM uint32_t PRI_13
Definition: tle987x.h:2387
__IOM uint32_t SLEEPONEXIT
Definition: tle987x.h:2328
__IOM uint32_t PENDSVACT
Definition: tle987x.h:2407
__IOM uint32_t SYSRESETREQ
Definition: tle987x.h:2312
__IM uint32_t ARCHITECTURE
Definition: tle987x.h:2264
__IOM uint32_t PRI_14
Definition: tle987x.h:2388
__IM uint32_t Int_ADC1
Definition: tle987x.h:2186
__IOM uint32_t Int_GPT2
Definition: tle987x.h:2080
__IOM uint32_t PRIGROUP
Definition: tle987x.h:2314
__IOM uint32_t Int_UART2
Definition: tle987x.h:2090
__IOM uint32_t Int_BDRV
Definition: tle987x.h:2093
__IOM uint32_t VECTTBL
Definition: tle987x.h:2456
__IM uint32_t VECTACTIVE
Definition: tle987x.h:2276
__OM uint32_t PENDSTCLR
Definition: tle987x.h:2284
__IOM uint32_t PRI_EXINT0
Definition: tle987x.h:2248
__IOM uint32_t Int_SSC2
Definition: tle987x.h:2088
__IOM uint32_t HALTED
Definition: tle987x.h:2469
__IOM uint32_t PRI_11
Definition: tle987x.h:2376
__IOM uint32_t USGFAULTPENDED
Definition: tle987x.h:2409
__IOM uint32_t PRI_GPT2
Definition: tle987x.h:2210
__IM uint32_t IMPLEMENTER
Definition: tle987x.h:2266
__IOM uint32_t PRI_15
Definition: tle987x.h:2389
__IOM uint32_t NONBASETHRDENA
Definition: tle987x.h:2341
__IOM uint32_t CP11
Definition: tle987x.h:2513
__IM uint32_t Int_EXINT1
Definition: tle987x.h:2196
__IOM uint32_t SEVONPEND
Definition: tle987x.h:2331
__IM uint32_t Int_UART1
Definition: tle987x.h:2193
__IOM uint32_t MEMFAULTENA
Definition: tle987x.h:2413
__IM uint32_t INTLINESNUM
Definition: tle987x.h:2020
__IOM uint32_t UNALIGN_TRP
Definition: tle987x.h:2344
__IOM uint32_t SVCALLACT
Definition: tle987x.h:2404
__IOM uint32_t Int_ADC1
Definition: tle987x.h:2082
__IOM uint32_t PRI_DMA
Definition: tle987x.h:2251
__IOM uint32_t MEMFAULTACT
Definition: tle987x.h:2399
__IOM uint32_t Int_GPT1
Definition: tle987x.h:2079
__IOM uint32_t CP5
Definition: tle987x.h:2508
__IOM uint32_t Int_EXINT1
Definition: tle987x.h:2092
__IM uint32_t
Definition: tle987x.h:2034
__IOM uint32_t PRECISERR
Definition: tle987x.h:2433
__IOM uint32_t BUSFAULTENA
Definition: tle987x.h:2414
__IOM uint32_t USGFAULTENA
Definition: tle987x.h:2415
__IOM uint32_t FORCED
Definition: tle987x.h:2458
__IOM uint32_t COUNTFLAG
Definition: tle987x.h:2035
__IOM uint32_t PRI_10
Definition: tle987x.h:2375
__IOM uint32_t ENABLE
Definition: tle987x.h:2031
__IM uint32_t Int_BDRV
Definition: tle987x.h:2197
__IOM uint32_t BFHFMIGN
Definition: tle987x.h:2348
__IOM uint32_t NOCP
Definition: tle987x.h:2442
__IOM uint32_t CURRENT
Definition: tle987x.h:2055
__IOM uint32_t Int_CCU6SR0
Definition: tle987x.h:2083
__IM uint32_t ISRPENDING
Definition: tle987x.h:2281
__IOM uint32_t IACCVIOL
Definition: tle987x.h:2425
__IOM uint32_t MUNSTKERR
Definition: tle987x.h:2428
__IM uint32_t Int_SSC1
Definition: tle987x.h:2191
__IM uint32_t Int_SSC2
Definition: tle987x.h:2192
__IOM uint32_t PRI_12
Definition: tle987x.h:2386
__IOM uint32_t MEMFAULTPENDED
Definition: tle987x.h:2410
__IOM uint32_t IMPRECISERR
Definition: tle987x.h:2434
__IOM uint32_t STKALIGN
Definition: tle987x.h:2350
__IOM uint32_t Int_UART1
Definition: tle987x.h:2089
__IM uint32_t TENMS
Definition: tle987x.h:2065
__IM uint32_t PARTNO
Definition: tle987x.h:2263
__IOM uint32_t PRI_CCU6SR3
Definition: tle987x.h:2225
__IOM uint32_t ADDRESS
Definition: tle987x.h:2483
__IOM uint32_t PRI_ADC1
Definition: tle987x.h:2212
__IOM uint32_t BUSFAULTPENDED
Definition: tle987x.h:2411
__IOM uint32_t PRI_CCU6SR2
Definition: tle987x.h:2224
__IOM uint32_t MSTERR
Definition: tle987x.h:2429
__IOM uint32_t VCATCH
Definition: tle987x.h:2472
__IOM uint32_t UNDEFINSTR
Definition: tle987x.h:2439
__IOM uint32_t SLEEPDEEP
Definition: tle987x.h:2329
__IOM uint32_t PRI_UART1
Definition: tle987x.h:2237
__IM uint32_t SKEW
Definition: tle987x.h:2067
__IM uint32_t RESERVED
Definition: tle987x.h:2012
__IOM uint32_t PRI_9
Definition: tle987x.h:2374
__IM uint32_t REVISION
Definition: tle987x.h:2262
__IOM uint32_t CP7
Definition: tle987x.h:2510
__IOM uint32_t CP4
Definition: tle987x.h:2507
__IOM uint32_t PRI_CCU6SR0
Definition: tle987x.h:2222
__IOM uint32_t PRI_SSC1
Definition: tle987x.h:2235
__IOM uint32_t PRI_5
Definition: tle987x.h:2361
__IM uint32_t Int_CCU6SR3
Definition: tle987x.h:2190
__IOM uint32_t VECTCLRACTIVE
Definition: tle987x.h:2311
__IOM uint32_t PRI_7
Definition: tle987x.h:2363
__IOM uint32_t TICKINT
Definition: tle987x.h:2032
__IM uint32_t Int_CCU6SR1
Definition: tle987x.h:2188
__IOM uint32_t INVSTATE
Definition: tle987x.h:2440
__IOM uint32_t reg
Definition: tle987x.h:2016
__IOM uint32_t VECTKEY
Definition: tle987x.h:2317
__IOM uint32_t PENDSVSET
Definition: tle987x.h:2287
__IOM uint32_t SYSTICKACT
Definition: tle987x.h:2408
__IOM uint32_t PRI_SSC2
Definition: tle987x.h:2236
__IM uint32_t Int_CCU6SR2
Definition: tle987x.h:2189
__IOM uint32_t INVPC
Definition: tle987x.h:2441
__IM uint32_t ENDIANNESS
Definition: tle987x.h:2316
__IM uint32_t Int_EXINT0
Definition: tle987x.h:2195
__IOM uint32_t CP1
Definition: tle987x.h:2504
__IM uint32_t RETTOBASE
Definition: tle987x.h:2278
__IOM uint32_t NMIPENDSET
Definition: tle987x.h:2289
__IOM uint32_t Int_CCU6SR3
Definition: tle987x.h:2086
__IOM uint32_t UNALIGNED
Definition: tle987x.h:2444
__IOM uint32_t Int_DMA
Definition: tle987x.h:2094
__IM uint32_t NOREF
Definition: tle987x.h:2068
__IOM uint32_t VECTRESET
Definition: tle987x.h:2310
__IOM uint32_t CP6
Definition: tle987x.h:2509
__IOM uint32_t MONITORACT
Definition: tle987x.h:2405
__IOM uint32_t CP2
Definition: tle987x.h:2505
__IM uint32_t VARIANT
Definition: tle987x.h:2265
__IOM uint32_t Int_EXINT0
Definition: tle987x.h:2091
__IOM uint32_t STKERR
Definition: tle987x.h:2436
__IOM uint32_t BKPT
Definition: tle987x.h:2470
__IOM uint32_t IBUSERR
Definition: tle987x.h:2432
__IOM uint32_t PENDSTSET
Definition: tle987x.h:2285
__IOM uint32_t Int_ADC2
Definition: tle987x.h:2081
__IOM uint32_t MMARVALID
Definition: tle987x.h:2431
__IOM uint32_t Int_CCU6SR1
Definition: tle987x.h:2084
__IM uint32_t ISRPREEMPT
Definition: tle987x.h:2282
__IOM uint32_t BFARVALID
Definition: tle987x.h:2438
__IOM uint32_t PRI_4
Definition: tle987x.h:2360
__IM uint32_t Int_UART2
Definition: tle987x.h:2194
__IOM uint32_t DACCVIOL
Definition: tle987x.h:2426
__IOM uint32_t USERSETMPEND
Definition: tle987x.h:2342
__IOM uint32_t UNSTKERR
Definition: tle987x.h:2435
__IOM uint32_t BUSFAULTACT
Definition: tle987x.h:2400
__IM uint32_t VECTPENDING
Definition: tle987x.h:2279
__OM uint32_t PENDSVCLR
Definition: tle987x.h:2286
__IOM uint32_t PRI_EXINT1
Definition: tle987x.h:2249
Current Sense Amplifier (CSA)
Definition: tle987x.h:2530
__IO uint32_t reg
Definition: tle987x.h:2535
__IO uint32_t EN
Definition: tle987x.h:2539
__IO uint32_t GAIN
Definition: tle987x.h:2540
__IO uint32_t VZERO
Definition: tle987x.h:2542
Direct Memeory Access (DMA)
Definition: tle987x.h:2558
__IM uint32_t MASTER_ENABLE
Definition: tle987x.h:2566
__IOM uint32_t CHNL_PRIORITY_SET
Definition: tle987x.h:2734
__IM uint32_t WAITONREQ_STATUS
Definition: tle987x.h:2613
__OM uint32_t MASTER_ENABLE
Definition: tle987x.h:2580
__IM uint32_t
Definition: tle987x.h:2567
__IM uint32_t STATE
Definition: tle987x.h:2568
__IOM uint32_t ERR_CLR
Definition: tle987x.h:2760
__OM uint32_t CHNL_SW_REQUEST
Definition: tle987x.h:2623
__OM uint32_t CHNL_USEBURST_CLR
Definition: tle987x.h:2651
__OM uint32_t CHNL_REQ_MASK_CLR
Definition: tle987x.h:2676
__IOM uint32_t reg
Definition: tle987x.h:2562
__OM uint32_t CHNL_PRIORITY_CLR
Definition: tle987x.h:2749
__OM uint32_t CHNL_ENABLE_CLR
Definition: tle987x.h:2699
__IM uint32_t CHNLS_MINUS1
Definition: tle987x.h:2570
__IM uint32_t ALT_CTRL_BASE_PTR
Definition: tle987x.h:2603
__IOM uint32_t CHNL_USEBURST_SET
Definition: tle987x.h:2633
__IOM uint32_t CHNL_REQ_MASK_SET
Definition: tle987x.h:2661
__IOM uint32_t CTRL_BASE_PTR
Definition: tle987x.h:2593
__IOM uint32_t CHNL_ENABLE_SET
Definition: tle987x.h:2686
__IOM uint32_t CHNL_PRI_ALT_SET
Definition: tle987x.h:2709
__OM uint32_t CHN1_PROT_CTRL
Definition: tle987x.h:2582
__OM uint32_t CHNL_PRI_ALT_CLR
Definition: tle987x.h:2724
General Purpose Timer 12E (GPT12E)
Definition: tle987x.h:2779
__IOM uint16_t T2I
Definition: tle987x.h:2820
__IOM uint16_t T4UD
Definition: tle987x.h:2865
__IOM uint16_t T3EDGE
Definition: tle987x.h:2849
__IOM uint16_t T3UDE
Definition: tle987x.h:2845
__IOM uint16_t T5R
Definition: tle987x.h:2887
__IOM uint16_t T4CHDIR
Definition: tle987x.h:2872
__IOM uint16_t IST6IN
Definition: tle987x.h:2807
__IOM uint16_t T4IRDIS
Definition: tle987x.h:2870
__IOM uint16_t IST4IN
Definition: tle987x.h:2803
__IOM uint16_t T4
Definition: tle987x.h:2960
__IOM uint16_t T2R
Definition: tle987x.h:2822
__IOM uint16_t T5UDE
Definition: tle987x.h:2889
__IM uint16_t T4RDIR
Definition: tle987x.h:2873
__IOM uint16_t T4RC
Definition: tle987x.h:2867
__IM uint16_t T3RDIR
Definition: tle987x.h:2851
__IOM uint16_t T6M
Definition: tle987x.h:2907
__IOM uint16_t CLRT2EN
Definition: tle987x.h:2868
__IOM uint16_t IST5EUD
Definition: tle987x.h:2806
__IOM uint16_t T6OTL
Definition: tle987x.h:2912
__IOM uint16_t T6OE
Definition: tle987x.h:2911
__IM uint16_t RESERVED8
Definition: tle987x.h:2941
__IOM uint16_t T6SR
Definition: tle987x.h:2916
__IOM uint16_t T5I
Definition: tle987x.h:2884
__IM uint16_t RESERVED4
Definition: tle987x.h:2876
__IOM uint16_t T5RC
Definition: tle987x.h:2890
__IOM uint16_t T3M
Definition: tle987x.h:2842
__IM uint16_t MOD_TYPE
Definition: tle987x.h:2788
__IM uint16_t
Definition: tle987x.h:2826
__IOM uint16_t T2IRDIS
Definition: tle987x.h:2827
__IOM uint16_t T3UD
Definition: tle987x.h:2844
__IOM uint16_t T6UD
Definition: tle987x.h:2909
__IOM uint16_t T6I
Definition: tle987x.h:2906
__IM uint16_t RESERVED10
Definition: tle987x.h:2963
__IOM uint16_t T4R
Definition: tle987x.h:2864
__IOM uint16_t T3R
Definition: tle987x.h:2843
__IOM uint16_t CT3
Definition: tle987x.h:2891
__IOM uint16_t T4EDGE
Definition: tle987x.h:2871
__IOM uint16_t CI
Definition: tle987x.h:2893
__IOM uint16_t T2EDGE
Definition: tle987x.h:2828
__IOM uint16_t reg
Definition: tle987x.h:2783
__IOM uint16_t BPS1
Definition: tle987x.h:2848
__IM uint16_t RESERVED6
Definition: tle987x.h:2919
__IOM uint16_t IST4EUD
Definition: tle987x.h:2804
__IOM uint16_t T2UDE
Definition: tle987x.h:2824
__IOM uint16_t ISCAPIN
Definition: tle987x.h:2809
__IOM uint16_t IST3IN
Definition: tle987x.h:2801
__IOM uint16_t T3CHDIR
Definition: tle987x.h:2850
__IOM uint16_t T6R
Definition: tle987x.h:2908
__IOM uint16_t T6
Definition: tle987x.h:2982
__IOM uint16_t T5
Definition: tle987x.h:2971
__IOM uint16_t IST2IN
Definition: tle987x.h:2799
__IOM uint16_t T4M
Definition: tle987x.h:2863
__IOM uint16_t T3OTL
Definition: tle987x.h:2847
__IOM uint16_t IST2EUD
Definition: tle987x.h:2800
__IOM uint16_t T5SC
Definition: tle987x.h:2895
__IOM uint16_t T2CHDIR
Definition: tle987x.h:2829
__IOM uint16_t T2M
Definition: tle987x.h:2821
__IM uint16_t RESERVED11
Definition: tle987x.h:2974
__IM uint16_t T2RDIR
Definition: tle987x.h:2830
__IM uint16_t MOD_REV
Definition: tle987x.h:2787
__IOM uint16_t T3OE
Definition: tle987x.h:2846
__IOM uint16_t IST3EUD
Definition: tle987x.h:2802
__IOM uint16_t IST5IN
Definition: tle987x.h:2805
__IOM uint16_t T4I
Definition: tle987x.h:2862
__IOM uint16_t T3
Definition: tle987x.h:2949
__IM uint16_t RESERVED5
Definition: tle987x.h:2898
__IOM uint16_t T5UD
Definition: tle987x.h:2888
__IM uint16_t RESERVED9
Definition: tle987x.h:2952
__IOM uint16_t T4UDE
Definition: tle987x.h:2866
__IOM uint16_t T6UDE
Definition: tle987x.h:2910
__IOM uint16_t CLRT3EN
Definition: tle987x.h:2869
__IOM uint16_t T5CLR
Definition: tle987x.h:2894
__IOM uint16_t T6CLR
Definition: tle987x.h:2915
__IOM uint16_t CAPREL
Definition: tle987x.h:2927
__IM uint16_t RESERVED1
Definition: tle987x.h:2812
__IOM uint16_t T3I
Definition: tle987x.h:2841
__IM uint16_t RESERVED7
Definition: tle987x.h:2930
__IM uint16_t RESERVED3
Definition: tle987x.h:2854
__IOM uint16_t BPS2
Definition: tle987x.h:2913
__IM uint16_t RESERVED
Definition: tle987x.h:2791
__IOM uint16_t T2
Definition: tle987x.h:2938
__IOM uint16_t T5M
Definition: tle987x.h:2885
__IM uint16_t RESERVED2
Definition: tle987x.h:2833
__IOM uint16_t IST6EUD
Definition: tle987x.h:2808
__IOM uint16_t T2RC
Definition: tle987x.h:2825
__IOM uint16_t T2UD
Definition: tle987x.h:2823
Local Interconnect Network (LIN)
Definition: tle987x.h:2999
__IM uint32_t FB_SM2
Definition: tle987x.h:3019
__IOM uint32_t SM
Definition: tle987x.h:3017
__IM uint32_t FB_SM1
Definition: tle987x.h:3018
__IOM uint32_t HV_MODE
Definition: tle987x.h:3023
__IM uint32_t MODE_FB
Definition: tle987x.h:3021
__IM uint32_t OT_STS
Definition: tle987x.h:3010
__IM uint32_t
Definition: tle987x.h:3007
__IM uint32_t TXD_TMOUT_STS
Definition: tle987x.h:3012
__IM uint32_t FB_SM3
Definition: tle987x.h:3020
__IM uint32_t RXD
Definition: tle987x.h:3016
__IOM uint32_t TXD
Definition: tle987x.h:3014
__IOM uint32_t M_SM_ERR_CLR
Definition: tle987x.h:3025
__IOM uint32_t reg
Definition: tle987x.h:3003
__IM uint32_t OC_STS
Definition: tle987x.h:3011
__IM uint32_t M_SM_ERR
Definition: tle987x.h:3009
__IOM uint32_t MODE
Definition: tle987x.h:3008
Measurement Function (MF)
Definition: tle987x.h:3042
__IM uint32_t REFBG_LOTHWARN_STS
Definition: tle987x.h:3122
__IM uint32_t PMU_OT_STS
Definition: tle987x.h:3109
__IOM uint32_t PHUCOMP_ON
Definition: tle987x.h:3088
__IOM uint32_t BEMF_TFILT_SEL
Definition: tle987x.h:3153
__IM uint32_t PHU_ZC_STS
Definition: tle987x.h:3094
__IM uint32_t PHW_ZC_STS
Definition: tle987x.h:3096
__IOM uint32_t PHWCOMP_ON
Definition: tle987x.h:3090
__IOM uint32_t ADC3_INN_SEL
Definition: tle987x.h:3057
__IOM uint32_t P2_3_ADC_SEL
Definition: tle987x.h:3052
__IOM uint32_t BEMF_BT_TFILT_SEL
Definition: tle987x.h:3149
__IM uint32_t PHV_ZC_STS
Definition: tle987x.h:3095
__IOM uint32_t VMON_SEN_HRESO_5V
Definition: tle987x.h:3070
__IM uint32_t VREF5V_OV_STS
Definition: tle987x.h:3138
__IM uint32_t REFBG_UPTHWARN_STS
Definition: tle987x.h:3124
__IM uint32_t
Definition: tle987x.h:3055
__IOM uint32_t P2_5_ADC_SEL
Definition: tle987x.h:3054
__IM uint32_t SYS_OT_STS
Definition: tle987x.h:3111
__IM uint32_t VREF5V_UV_STS
Definition: tle987x.h:3137
__IOM uint32_t VMON_SEN_PD_N
Definition: tle987x.h:3068
__IM uint32_t SYS_OTWARN_STS
Definition: tle987x.h:3110
__IOM uint32_t PHWCOMP_EN
Definition: tle987x.h:3083
__IOM uint32_t DEMGFILTDIS
Definition: tle987x.h:3084
__IOM uint32_t PHVCOMP_ON
Definition: tle987x.h:3089
__IOM uint32_t P2_4_ADC_SEL
Definition: tle987x.h:3053
__IOM uint32_t PHUCOMP_EN
Definition: tle987x.h:3081
__IM uint32_t PMU_OTWARN_STS
Definition: tle987x.h:3108
__IOM uint32_t P2_2_ADC_SEL
Definition: tle987x.h:3051
__IOM uint32_t VREF5V_PD_N
Definition: tle987x.h:3135
__IOM uint32_t reg
Definition: tle987x.h:3046
__IM uint32_t VREF5V_OVL_STS
Definition: tle987x.h:3136
__IOM uint32_t PHVCOMP_EN
Definition: tle987x.h:3082
__IOM uint32_t ADC1_CH1_SEL
Definition: tle987x.h:3058
__IOM uint32_t ADC3_INP_SEL
Definition: tle987x.h:3056
__IOM uint32_t GPT12CAPINSW
Definition: tle987x.h:3086
__IM uint32_t RESERVED1
Definition: tle987x.h:3141
__IOM uint32_t P2_0_ADC_SEL
Definition: tle987x.h:3050
__IOM uint32_t FILTBYPS
Definition: tle987x.h:3085
__IOM uint32_t VMON_SEN_SEL_INRANGE
Definition: tle987x.h:3071
__IOM uint32_t CCPOS_INSEL
Definition: tle987x.h:3092
__IOM uint32_t BEMF_GPT_CAPIN_SEL
Definition: tle987x.h:3151
__IM uint32_t RESERVED0
Definition: tle987x.h:3099
MON (MON)
Definition: tle987x.h:3169
__IO uint8_t CYC
Definition: tle987x.h:3181
__IO uint8_t PD
Definition: tle987x.h:3182
__IO uint8_t PU
Definition: tle987x.h:3183
__IO uint8_t EN
Definition: tle987x.h:3178
__IO uint8_t FALL
Definition: tle987x.h:3179
__IO uint8_t RISE
Definition: tle987x.h:3180
__I uint8_t STS
Definition: tle987x.h:3185
__IO uint8_t reg
Definition: tle987x.h:3174
Power Management Unit (PMU)
Definition: tle987x.h:3201
__IOM uint8_t LOCKUP
Definition: tle987x.h:3284
__IOM uint8_t GPIO0_FA_3
Definition: tle987x.h:3540
__IOM uint8_t GPIO0_RI_2
Definition: tle987x.h:3524
__IOM uint8_t GPIO0_RI_0
Definition: tle987x.h:3522
__IOM uint8_t CNF_MON_FT
Definition: tle987x.h:3444
__IOM uint8_t DATA1
Definition: tle987x.h:3467
__IM uint8_t GPIO0_STS_4
Definition: tle987x.h:3417
__IOM uint8_t PMU_1V5DidPOR
Definition: tle987x.h:3271
__IOM uint8_t CNF_LIN_FT
Definition: tle987x.h:3443
__IOM uint8_t GPIO1_RI_0
Definition: tle987x.h:3567
__IOM uint8_t GPIO1_RI_3
Definition: tle987x.h:3570
__IOM uint8_t CYC_WAKE_EN
Definition: tle987x.h:3298
__IOM uint8_t SUPPFAIL
Definition: tle987x.h:3389
__IM uint8_t PMU_5V_OVERLOAD
Definition: tle987x.h:3232
__IM uint8_t PMU_5V_OVERVOLT
Definition: tle987x.h:3231
__IOM uint8_t GPIO1_FA_0
Definition: tle987x.h:3582
__IOM uint8_t GPIO0_FA_4
Definition: tle987x.h:3541
__IOM uint8_t OVERLOAD
Definition: tle987x.h:3250
__IOM uint8_t PMU_1V5_OVL
Definition: tle987x.h:3374
__IOM uint8_t M03
Definition: tle987x.h:3312
__IM uint8_t GPIO1_STS_1
Definition: tle987x.h:3429
__IM uint8_t GPIO1_STS_4
Definition: tle987x.h:3432
__IOM uint8_t PMU_ClkWDT
Definition: tle987x.h:3268
__IM uint8_t GPIO1
Definition: tle987x.h:3213
__IOM uint8_t GPIO0_CYC_0
Definition: tle987x.h:3552
__IOM uint8_t PMU_5V_FAIL_EN
Definition: tle987x.h:3233
__IM uint8_t LIN_WAKE
Definition: tle987x.h:3209
__IOM uint8_t DATA2
Definition: tle987x.h:3478
__IOM uint8_t DATA5
Definition: tle987x.h:3511
__IOM uint8_t DATA0
Definition: tle987x.h:3456
__IOM uint8_t GPIO0_RI_4
Definition: tle987x.h:3526
__IM uint8_t
Definition: tle987x.h:3230
__IOM uint8_t GPIO1_RI_1
Definition: tle987x.h:3568
__IOM uint8_t OSC_100kHz_EN
Definition: tle987x.h:3315
__IOM uint8_t LIN_EN
Definition: tle987x.h:3350
__IM uint8_t GPIO0_STS_1
Definition: tle987x.h:3414
__IOM uint8_t GPIO0_CYC_2
Definition: tle987x.h:3554
__IM uint8_t GPIO1_STS_0
Definition: tle987x.h:3428
__IOM uint8_t GPIO1_RI_2
Definition: tle987x.h:3569
__IOM uint8_t E01
Definition: tle987x.h:3313
__IOM uint8_t WAKE_W_RST
Definition: tle987x.h:3295
__IOM uint8_t GPIO1_CYC_3
Definition: tle987x.h:3600
__IOM uint8_t GPIO0_RI_3
Definition: tle987x.h:3525
__IOM uint8_t GPIO0_CYC_1
Definition: tle987x.h:3553
__IOM uint8_t PMU_ExtWDT
Definition: tle987x.h:3269
__IOM uint8_t DATA4
Definition: tle987x.h:3500
__IOM uint8_t SUPP_SHORT
Definition: tle987x.h:3372
__IOM uint8_t GPIO1_FA_2
Definition: tle987x.h:3584
__IOM uint8_t MBIST_EN
Definition: tle987x.h:3612
__IM uint8_t WAKE_STS
Definition: tle987x.h:3402
__IOM uint8_t GPIO0_RI_1
Definition: tle987x.h:3523
__IM uint8_t GPIO0
Definition: tle987x.h:3211
__IOM uint8_t OVERVOLT
Definition: tle987x.h:3249
__IM uint8_t GPIO0_STS_3
Definition: tle987x.h:3416
__IOM uint8_t SHORT
Definition: tle987x.h:3248
__IOM uint8_t GPIO1_FA_3
Definition: tle987x.h:3585
__IOM uint8_t GPIO1_RI_4
Definition: tle987x.h:3571
__IOM uint8_t GPIO1_FA_4
Definition: tle987x.h:3586
__IOM uint8_t WDT1_SEQ_FAIL
Definition: tle987x.h:3378
__IM uint8_t MON_WAKE
Definition: tle987x.h:3210
__IOM uint8_t GPIO0_FA_0
Definition: tle987x.h:3537
__IM uint8_t FAIL
Definition: tle987x.h:3216
__IOM uint8_t CYC_EN
Definition: tle987x.h:3245
__IOM uint8_t GPIO0_CYC_3
Definition: tle987x.h:3555
__IM uint8_t STABLE
Definition: tle987x.h:3252
__IOM uint8_t RST_TFB
Definition: tle987x.h:3361
__IOM uint8_t SUPP_TMOUT
Definition: tle987x.h:3373
__IOM uint8_t VDDEXTSHORT
Definition: tle987x.h:3391
__IOM uint8_t GPIO0_CYC_4
Definition: tle987x.h:3556
__IOM uint8_t CNF_GPIO_FT
Definition: tle987x.h:3445
__IM uint8_t OK
Definition: tle987x.h:3251
__IOM uint8_t FAIL_EN
Definition: tle987x.h:3246
__IOM uint8_t PMU_WAKE
Definition: tle987x.h:3265
__IOM uint8_t GPIO1_CYC_4
Definition: tle987x.h:3601
__IM uint8_t GPIO1_STS_3
Definition: tle987x.h:3431
__IOM uint8_t PMU_5V_OVL
Definition: tle987x.h:3375
__IOM uint8_t PMU_IntWDT
Definition: tle987x.h:3282
__IM uint8_t CYC_WAKE
Definition: tle987x.h:3215
__IOM uint8_t GPIO0_FA_1
Definition: tle987x.h:3538
__IM uint8_t PMU_1V5_OVERVOLT
Definition: tle987x.h:3227
__IM uint8_t GPIO0_STS_2
Definition: tle987x.h:3415
__IM uint8_t GPIO0_STS_0
Definition: tle987x.h:3413
__IOM uint8_t GPIO0_FA_2
Definition: tle987x.h:3539
__IOM uint8_t SYS_FAIL
Definition: tle987x.h:3263
__IOM uint8_t PMU_PIN
Definition: tle987x.h:3270
__IOM uint8_t PMU_SOFT
Definition: tle987x.h:3283
__IOM uint8_t PMU_SleepEX
Definition: tle987x.h:3266
__IOM uint8_t DATA3
Definition: tle987x.h:3489
__IOM uint8_t GPIO1_FA_1
Definition: tle987x.h:3583
__IM uint8_t GPIO1_STS_2
Definition: tle987x.h:3430
__IOM uint8_t PMU_LPR
Definition: tle987x.h:3267
__IM uint8_t PMU_1V5_OVERLOAD
Definition: tle987x.h:3228
__IOM uint8_t GPIO1_CYC_0
Definition: tle987x.h:3597
__IOM uint8_t GPIO1_CYC_2
Definition: tle987x.h:3599
__IOM uint8_t reg
Definition: tle987x.h:3205
__IOM uint8_t GPIO1_CYC_1
Definition: tle987x.h:3598
__IOM uint8_t SYS_OT
Definition: tle987x.h:3377
__IOM uint8_t EN_VDDEXT_OC_OFF_N
Definition: tle987x.h:3301
__IOM uint8_t EN_0V9_N
Definition: tle987x.h:3296
__IOM uint8_t ENABLE
Definition: tle987x.h:3244
__IOM uint8_t PMU_1V5_FAIL_EN
Definition: tle987x.h:3229
__IOM uint8_t CYC_SENSE_EN
Definition: tle987x.h:3299
GPIO PORTs (PORT)
Definition: tle987x.h:3630
__IM uint8_t P4
Definition: tle987x.h:3702
__IOM uint8_t P1
Definition: tle987x.h:3639
__IM uint8_t P2
Definition: tle987x.h:3700
__IOM uint8_t P4
Definition: tle987x.h:3642
__IM uint8_t
Definition: tle987x.h:3699
__IOM uint8_t P0
Definition: tle987x.h:3638
__IM uint8_t P5
Definition: tle987x.h:3703
__IM uint8_t P0
Definition: tle987x.h:3698
__IOM uint8_t P2
Definition: tle987x.h:3640
__IOM uint8_t P3_P2
Definition: tle987x.h:3900
__IOM uint8_t P3
Definition: tle987x.h:3641
__IM uint8_t P3
Definition: tle987x.h:3701
__IOM uint8_t reg
Definition: tle987x.h:3634
__IOM uint8_t P5
Definition: tle987x.h:3719
System Control Unit (SCU)
Definition: tle987x.h:3918
__IOM uint8_t CH8IE
Definition: tle987x.h:4841
__OM uint8_t T2C
Definition: tle987x.h:4957
__OM uint8_t EXINT0RC
Definition: tle987x.h:4077
__IOM uint8_t NMIECC
Definition: tle987x.h:4051
__IM uint8_t FNMIECC
Definition: tle987x.h:4021
__IOM uint8_t LOCKUP
Definition: tle987x.h:4309
__IOM uint8_t K1DIV
Definition: tle987x.h:4192
__IOM uint8_t T2_DIS
Definition: tle987x.h:4281
__IOM uint8_t SECTORINFO
Definition: tle987x.h:4690
__IOM uint8_t TIREN1
Definition: tle987x.h:4104
__OM uint8_t CCU6SR2C
Definition: tle987x.h:5058
__IM uint8_t TRSEQ1DY
Definition: tle987x.h:4906
__IOM uint8_t T3IE
Definition: tle987x.h:4924
__IOM uint8_t T4IE
Definition: tle987x.h:4925
__OM uint8_t CH6C
Definition: tle987x.h:5015
__OM uint8_t NMINVMC
Definition: tle987x.h:3928
__IM uint8_t T2
Definition: tle987x.h:4940
__IOM uint8_t BR_VALUE
Definition: tle987x.h:4418
__IOM uint8_t PDM3
Definition: tle987x.h:4748
__IOM uint8_t EXINT1IS
Definition: tle987x.h:4563
__IM uint8_t NVM_ADDR_ERR
Definition: tle987x.h:4717
__OM uint8_t NMIWDTC
Definition: tle987x.h:3926
__IOM uint8_t SL
Definition: tle987x.h:4162
__IOM uint8_t T2_SUSP
Definition: tle987x.h:4620
__IOM uint8_t EXINT2IS
Definition: tle987x.h:4564
__OM uint8_t T3C
Definition: tle987x.h:4958
__IM uint8_t CCU6SR1
Definition: tle987x.h:3991
__IM uint8_t EXINT1R
Definition: tle987x.h:3946
__IM uint8_t CH7
Definition: tle987x.h:4893
__OM uint8_t NMIECCC
Definition: tle987x.h:3932
__IM uint8_t EXINT1F
Definition: tle987x.h:3947
__OM uint8_t RIRC
Definition: tle987x.h:4975
__IOM uint8_t OSCSS
Definition: tle987x.h:4531
__OM uint8_t RDBEC
Definition: tle987x.h:4819
__IOM uint8_t SSC2_DIS
Definition: tle987x.h:4294
__IOM uint8_t K2DIV
Definition: tle987x.h:4191
__IOM uint8_t COUTS0
Definition: tle987x.h:4548
__IOM uint8_t CRIE
Definition: tle987x.h:4928
__IOM uint8_t T12PM_DMAEN
Definition: tle987x.h:4872
__IOM uint8_t MU_SUSP
Definition: tle987x.h:4635
__IOM uint8_t VCOBYP
Definition: tle987x.h:4178
__IOM uint8_t EXINT0IS
Definition: tle987x.h:4562
__IOM uint8_t IE1
Definition: tle987x.h:4150
__IOM uint8_t CPCLK_DIV
Definition: tle987x.h:4238
__IOM uint8_t RIEN2
Definition: tle987x.h:4124
__IOM uint8_t WDTWINB
Definition: tle987x.h:4371
__IOM uint8_t CPCLK_SEL
Definition: tle987x.h:4237
__OM uint8_t CCU6SR1C
Definition: tle987x.h:5047
__IM uint8_t EXINT2R
Definition: tle987x.h:3948
__IOM uint8_t RIREN2
Definition: tle987x.h:4121
__OM uint8_t TIRC
Definition: tle987x.h:4974
__IM uint8_t T5
Definition: tle987x.h:4943
__IOM uint8_t NVMIE
Definition: tle987x.h:4663
__OM uint8_t EXINT1RC
Definition: tle987x.h:4081
__IOM uint8_t XTAL_ON
Definition: tle987x.h:4161
__IOM uint8_t NMIMAP
Definition: tle987x.h:4050
__IOM uint8_t CH6IE
Definition: tle987x.h:4839
__IOM uint8_t GPT12CAPINB
Definition: tle987x.h:4577
__OM uint8_t GPT12C
Definition: tle987x.h:5033
__OM uint8_t NMIOWDC
Definition: tle987x.h:3930
__OM uint8_t CCU6SR3C
Definition: tle987x.h:5060
__IOM uint8_t BRDIS
Definition: tle987x.h:4440
__OM uint8_t TRSEQ1DYC
Definition: tle987x.h:5029
__OM uint8_t BRKC
Definition: tle987x.h:4493
__IOM uint8_t COUTS1
Definition: tle987x.h:4550
__IOM uint8_t NMISUP
Definition: tle987x.h:4052
__OM uint8_t CH3C
Definition: tle987x.h:5012
__IOM uint8_t COREL
Definition: tle987x.h:4547
__IOM uint8_t T21_DIS
Definition: tle987x.h:4296
__IM uint8_t T6
Definition: tle987x.h:4944
__IOM uint8_t PDM0
Definition: tle987x.h:4733
__IOM uint8_t T5IE
Definition: tle987x.h:4926
__IOM uint8_t EN
Definition: tle987x.h:4551
__IOM uint8_t NVMPROTSTSL_2
Definition: tle987x.h:4704
__IOM uint8_t WINBEN
Definition: tle987x.h:4220
__IOM uint8_t RESLD
Definition: tle987x.h:4176
__IM uint8_t MONF
Definition: tle987x.h:3951
__IM uint8_t EIR
Definition: tle987x.h:3963
__IOM uint8_t CCU6_DIS
Definition: tle987x.h:4280
__IM uint8_t MONSTS
Definition: tle987x.h:4139
__OM uint8_t MONFC
Definition: tle987x.h:4091
__OM uint8_t SSC1C
Definition: tle987x.h:5031
__IOM uint8_t TRSEQ1RDYIE
Definition: tle987x.h:4853
__OM uint8_t CH5C
Definition: tle987x.h:5014
__IM uint8_t APCLK1STS
Definition: tle987x.h:4252
__IM uint8_t FNMINVM
Definition: tle987x.h:4017
__IOM uint8_t TLEN
Definition: tle987x.h:4549
__IOM uint8_t VCOSEL
Definition: tle987x.h:4193
__IOM uint8_t T21IS
Definition: tle987x.h:4592
__IM uint8_t FNMIOT
Definition: tle987x.h:4018
__IM uint8_t SSCTX
Definition: tle987x.h:4874
__IM uint8_t CR
Definition: tle987x.h:4945
__IOM uint8_t EXINT1
Definition: tle987x.h:4064
__IOM uint8_t BRPRE
Definition: tle987x.h:4405
__IOM uint8_t ADC1_SUSP
Definition: tle987x.h:4636
__IOM uint8_t APCLK1FAC
Definition: tle987x.h:4249
__IOM uint8_t IE0
Definition: tle987x.h:4136
__IOM uint8_t CH1IE
Definition: tle987x.h:4834
__IM uint8_t
Definition: tle987x.h:3990
__IOM uint8_t OSCDISC
Definition: tle987x.h:4177
__IOM uint8_t LOCKUP_EN
Definition: tle987x.h:4311
__IM uint8_t CCU6SR2
Definition: tle987x.h:4002
__IOM uint8_t TCC
Definition: tle987x.h:4770
__OM uint8_t GPT12_T3C
Definition: tle987x.h:5074
__IOM uint8_t SSCRXIE
Definition: tle987x.h:4856
__IOM uint8_t APCLK1SCLR
Definition: tle987x.h:4250
__OM uint8_t TRSEQ2DYC
Definition: tle987x.h:5030
__IOM uint8_t R
Definition: tle987x.h:4404
__IOM uint8_t T2IS
Definition: tle987x.h:4591
__OM uint8_t NMIMAPC
Definition: tle987x.h:3931
__IOM uint8_t T21EXCON
Definition: tle987x.h:4580
__IOM uint8_t SSCTXSRCSEL
Definition: tle987x.h:4869
__IM uint8_t BRK
Definition: tle987x.h:4442
__IOM uint8_t PDM1
Definition: tle987x.h:4735
__IOM uint8_t CH5IE
Definition: tle987x.h:4838
__IOM uint8_t WDTSUSP
Definition: tle987x.h:4617
__IM uint8_t CH2
Definition: tle987x.h:4888
__IOM uint8_t EA
Definition: tle987x.h:4034
__IM uint8_t FNMISUP
Definition: tle987x.h:4022
__OM uint8_t EIRC
Definition: tle987x.h:4973
__OM uint8_t EXINT1FC
Definition: tle987x.h:4083
__IOM uint8_t CLKWDT_IE
Definition: tle987x.h:4234
__OM uint8_t SDADCC
Definition: tle987x.h:5034
__IM uint8_t CH6
Definition: tle987x.h:4892
__IOM uint8_t TIEN1
Definition: tle987x.h:4108
__IOM uint8_t SDADCCLK_DIV
Definition: tle987x.h:4322
__OM uint8_t NMIPLLC
Definition: tle987x.h:3927
__IOM uint8_t APCLK3SCLR
Definition: tle987x.h:4254
__OM uint8_t EOFSYNC
Definition: tle987x.h:4494
__IOM uint8_t T12SUSP
Definition: tle987x.h:4618
__IM uint8_t EXINT0R
Definition: tle987x.h:3944
__IOM uint8_t TRSEQ2RDYIE
Definition: tle987x.h:4854
__IOM uint8_t T21_SUSP
Definition: tle987x.h:4623
__IOM uint8_t EIREN1
Definition: tle987x.h:4103
__IM uint8_t RDBE
Definition: tle987x.h:4675
__IOM uint8_t T12ZM_DMAEN
Definition: tle987x.h:4871
__IOM uint8_t T2EXCON
Definition: tle987x.h:4579
__IM uint8_t OSC2L
Definition: tle987x.h:4533
__IOM uint8_t TRIG_CONF
Definition: tle987x.h:4648
__IOM uint8_t URIOS1
Definition: tle987x.h:4565
__IOM uint8_t MRAMINITSTS
Definition: tle987x.h:4348
__IOM uint8_t INIT_FAIL
Definition: tle987x.h:4347
__IOM uint8_t SASTATUS
Definition: tle987x.h:4691
__IOM uint8_t T3_DIS
Definition: tle987x.h:4298
__IM uint8_t RSBE
Definition: tle987x.h:4679
__IM uint8_t FNMIWDT
Definition: tle987x.h:4015
__OM uint8_t EXINT0FC
Definition: tle987x.h:4079
__IOM uint8_t PD
Definition: tle987x.h:4163
__IOM uint8_t OSCWDTRST
Definition: tle987x.h:4532
__OM uint8_t T6C
Definition: tle987x.h:4961
__IM uint8_t VERID
Definition: tle987x.h:4506
__OM uint8_t MONRC
Definition: tle987x.h:4089
__IOM uint8_t BGSEL
Definition: tle987x.h:4441
__IM uint8_t EOFSYN
Definition: tle987x.h:4443
__IM uint8_t APCLK2STS
Definition: tle987x.h:4266
__IM uint8_t ROM_PROT_ERR
Definition: tle987x.h:4720
__IOM uint8_t APCLK2SCLR
Definition: tle987x.h:4267
__IOM uint8_t SD
Definition: tle987x.h:4164
__IOM uint8_t PBA0CLKREL
Definition: tle987x.h:4204
__IOM uint8_t NMIWDT
Definition: tle987x.h:4045
__IM uint8_t PLL_LOCK
Definition: tle987x.h:4231
__IOM uint8_t SYSCLKSEL
Definition: tle987x.h:4336
__IOM uint8_t NDIV
Definition: tle987x.h:4179
__IOM uint8_t WDTRS
Definition: tle987x.h:4216
__IM uint8_t FNMIOWD
Definition: tle987x.h:4019
__IM uint8_t GPT12_T3
Definition: tle987x.h:4876
__IM uint8_t CH8
Definition: tle987x.h:4894
__IOM uint8_t CLKREL
Definition: tle987x.h:4190
__IOM uint8_t APCLK_SET
Definition: tle987x.h:4232
__IOM uint8_t MODE
Definition: tle987x.h:4518
__IM uint8_t SSC1RDY
Definition: tle987x.h:4908
__IOM uint8_t RIE
Definition: tle987x.h:4661
__IM uint8_t EXINT0F
Definition: tle987x.h:3945
__IM uint8_t SSC2RDY
Definition: tle987x.h:4909
__OM uint8_t EXINT2FC
Definition: tle987x.h:4087
__OM uint8_t CH8C
Definition: tle987x.h:5017
__IM uint8_t APCLK3STS
Definition: tle987x.h:4253
__IOM uint8_t T2EXIS
Definition: tle987x.h:4593
__OM uint8_t CH1C
Definition: tle987x.h:5010
__IM uint8_t LOCK
Definition: tle987x.h:4175
__IOM uint8_t NVMPROTSTSL_1
Definition: tle987x.h:4703
__IM uint8_t CH1
Definition: tle987x.h:4887
__IM uint8_t CCU6SR3
Definition: tle987x.h:4004
__OM uint8_t T5C
Definition: tle987x.h:4960
__OM uint8_t CH4C
Definition: tle987x.h:5013
__IM uint8_t ERRSYN
Definition: tle987x.h:4444
__IOM uint8_t NMIOWD
Definition: tle987x.h:4049
__IOM uint8_t T13SUSP
Definition: tle987x.h:4619
__IOM uint8_t GPT12IE
Definition: tle987x.h:4857
__OM uint8_t RSBEC
Definition: tle987x.h:4823
__OM uint8_t NVMDBEC
Definition: tle987x.h:4821
__OM uint8_t CCU6SR0C
Definition: tle987x.h:5045
__IOM uint8_t RIEN1
Definition: tle987x.h:4107
__OM uint8_t SSC2C
Definition: tle987x.h:5032
__IM uint8_t PRODID
Definition: tle987x.h:4507
__OM uint8_t NMIOTC
Definition: tle987x.h:3929
__IOM uint8_t MONIE
Definition: tle987x.h:4138
__IOM uint8_t NVMPROTSTSL_3
Definition: tle987x.h:4705
__OM uint8_t CH2C
Definition: tle987x.h:5011
__IM uint8_t RAM_PROT_ERR
Definition: tle987x.h:4722
__IM uint8_t CCU6SR0
Definition: tle987x.h:3989
__IOM uint8_t NMIPLL
Definition: tle987x.h:4046
__IM uint8_t PROTECT_S
Definition: tle987x.h:4519
__IM uint8_t CH5
Definition: tle987x.h:4891
__IM uint8_t MONR
Definition: tle987x.h:3950
__IOM uint8_t CH7IE
Definition: tle987x.h:4840
__IOM uint8_t WDTREL
Definition: tle987x.h:4360
__IOM uint8_t ADC1_DIS
Definition: tle987x.h:4278
__IOM uint8_t PDM4
Definition: tle987x.h:4759
__IM uint8_t CH3
Definition: tle987x.h:4889
__IOM uint8_t RIREN1
Definition: tle987x.h:4105
__IOM uint8_t BGCLK_SEL
Definition: tle987x.h:4235
__IOM uint8_t T21EXIS
Definition: tle987x.h:4594
__IOM uint8_t NVMCLKFAC
Definition: tle987x.h:4335
__IOM uint8_t T3CLK_SEL
Definition: tle987x.h:4233
__IOM uint8_t NMINVM
Definition: tle987x.h:4047
__IOM uint8_t FD_SEL
Definition: tle987x.h:4417
__IM uint8_t EXINT2F
Definition: tle987x.h:3949
__IOM uint8_t SSCTXIE
Definition: tle987x.h:4855
__IOM uint8_t APCLK2FAC
Definition: tle987x.h:4265
__IOM uint8_t T6IE
Definition: tle987x.h:4927
__OM uint8_t SSCTXC
Definition: tle987x.h:5072
__IOM uint8_t T3CLK_DIV
Definition: tle987x.h:4323
__IOM uint8_t WDTEN
Definition: tle987x.h:4217
__OM uint8_t SSCRXC
Definition: tle987x.h:5073
__IOM uint8_t CH2IE
Definition: tle987x.h:4835
__IM uint8_t WDT
Definition: tle987x.h:4382
__IM uint8_t T4
Definition: tle987x.h:4942
__IOM uint8_t OSCTRIM_8
Definition: tle987x.h:4536
__IOM uint8_t GPT12_DIS
Definition: tle987x.h:4282
__IOM uint8_t XPD
Definition: tle987x.h:4534
__IOM uint8_t NMIOT
Definition: tle987x.h:4048
__IM uint8_t NVM_SFR_PROT_ERR
Definition: tle987x.h:4718
__IOM uint8_t BGCLK_DIV
Definition: tle987x.h:4236
__IOM uint8_t MON_Trig_Sel
Definition: tle987x.h:4066
__IOM uint8_t SYNEN
Definition: tle987x.h:4445
__IOM uint8_t GPT12_DMAEN
Definition: tle987x.h:4999
__IM uint8_t T3
Definition: tle987x.h:4941
__IM uint8_t NVM_PROT_ERR
Definition: tle987x.h:4716
__IOM uint8_t EXINT0
Definition: tle987x.h:4063
__IOM uint8_t SSCRXSRCSEL
Definition: tle987x.h:4870
__OM uint8_t CRC
Definition: tle987x.h:4962
__OM uint8_t EXINT2RC
Definition: tle987x.h:4085
__IOM uint8_t PG100TP_CHKS_ERR
Definition: tle987x.h:4349
__IOM uint8_t CH3IE
Definition: tle987x.h:4836
__IOM uint8_t TIREN2
Definition: tle987x.h:4120
__IOM uint8_t SDADCIE
Definition: tle987x.h:4858
__IM uint8_t SDADC
Definition: tle987x.h:4911
__IOM uint8_t GPT12
Definition: tle987x.h:4647
__IOM uint8_t NVMPROTSTSL_0
Definition: tle987x.h:4702
__IOM uint8_t CH4IE
Definition: tle987x.h:4837
__IM uint8_t STRDY
Definition: tle987x.h:4905
__IM uint8_t GPT12
Definition: tle987x.h:4910
__IM uint8_t ROM_ADDR_ERR
Definition: tle987x.h:4721
__IM uint8_t TRSEQ2DY
Definition: tle987x.h:4907
__IOM uint8_t T3_SUSP
Definition: tle987x.h:4634
__IOM uint8_t PDM2
Definition: tle987x.h:4746
__IOM uint8_t EXINT2_EN
Definition: tle987x.h:4123
__IM uint8_t SSCRX
Definition: tle987x.h:4875
__IM uint8_t CH4
Definition: tle987x.h:4890
__OM uint8_t ERRSYNC
Definition: tle987x.h:4495
__IM uint8_t FNMIPLL
Definition: tle987x.h:4016
__IM uint8_t TIR
Definition: tle987x.h:3964
__IOM uint8_t EXINT2
Definition: tle987x.h:4065
__IOM uint8_t reg
Definition: tle987x.h:3922
__IOM uint8_t GPT12_SUSP
Definition: tle987x.h:4621
__OM uint8_t NMISUPC
Definition: tle987x.h:3933
__IOM uint8_t EIREN2
Definition: tle987x.h:4119
__IM uint8_t FNMIMAP
Definition: tle987x.h:4020
__IOM uint8_t U_TX_CONDIS
Definition: tle987x.h:4566
__OM uint8_t CH7C
Definition: tle987x.h:5016
__IOM uint8_t SSC1_DIS
Definition: tle987x.h:4279
__IM uint8_t NVMDBE
Definition: tle987x.h:4677
__IOM uint8_t WDTIN
Definition: tle987x.h:4215
__IM uint8_t NVM_SFR_ADDR_ERR
Definition: tle987x.h:4719
__OM uint8_t T4C
Definition: tle987x.h:4959
__IOM uint8_t TRERRIE
Definition: tle987x.h:4852
__IOM uint8_t T2IE
Definition: tle987x.h:4923
__IM uint8_t RIR
Definition: tle987x.h:3965
__IOM uint8_t PASS
Definition: tle987x.h:4520
__IOM uint8_t T3_GPT12_SEL
Definition: tle987x.h:4649
__IOM uint8_t TIEN2
Definition: tle987x.h:4125
__IOM uint8_t URIOS2
Definition: tle987x.h:4606
__IM uint8_t WDTPR
Definition: tle987x.h:4219
System Control Unit for Power Modules (SCUPM)
Definition: tle987x.h:5091
__IM uint32_t PHU_ZCHI_STS
Definition: tle987x.h:5217
__IOM uint32_t SOWCONF
Definition: tle987x.h:5357
__IOM uint32_t PHV_ZCLOW_IE
Definition: tle987x.h:5320
__OM uint32_t HS3_OC_ICLR
Definition: tle987x.h:5383
__IOM uint32_t LS2_OC_IE
Definition: tle987x.h:5473
__IM uint32_t LIN_OT_IS
Definition: tle987x.h:5187
__IM uint32_t VDD5V_OV_STS
Definition: tle987x.h:5246
__IOM uint32_t PHU_ZCLOW_IE
Definition: tle987x.h:5318
__IM uint32_t PHU_ZCLOW_STS
Definition: tle987x.h:5216
__IM uint32_t VREF5V_UPTH_IS
Definition: tle987x.h:5204
__IM uint32_t PHW_ZCLOW_IS
Definition: tle987x.h:5212
__IM uint32_t ADC2_ESM_IS
Definition: tle987x.h:5207
__IOM uint32_t AMCLK2_UP_TH
Definition: tle987x.h:5127
__OM uint32_t VSD_UPTH_SCLR
Definition: tle987x.h:5403
__IM uint32_t LS3_DS_IS
Definition: tle987x.h:5421
__IM uint32_t VCP_LOWTH2_STS
Definition: tle987x.h:5442
__IM uint32_t VSD_LOWTH_IS
Definition: tle987x.h:5437
__IM uint32_t SYS_OTWARN_IS
Definition: tle987x.h:5194
__IOM uint32_t VREF5V_OVL_IE
Definition: tle987x.h:5316
__IM uint32_t PHW_ZCHI_STS
Definition: tle987x.h:5221
__IOM uint32_t HS3_DS_IE
Definition: tle987x.h:5469
__IOM uint32_t AMCLK2_LOW_TH
Definition: tle987x.h:5129
__IM uint32_t HS3_OC_IS
Definition: tle987x.h:5430
__IOM uint32_t HS2_OC_IE
Definition: tle987x.h:5475
__IM uint32_t PHV_ZCHI_STS
Definition: tle987x.h:5219
__OM uint32_t VCP_UPTH_ICLR
Definition: tle987x.h:5388
__OM uint32_t LIN_TMOUT_ICLR
Definition: tle987x.h:5143
__OM uint32_t VDD1V5_OV_ICLR
Definition: tle987x.h:5281
__OM uint32_t VSD_LOWTH_SCLR
Definition: tle987x.h:5401
__IOM uint32_t AMCLK1_UP_TH
Definition: tle987x.h:5123
__OM uint32_t HS3_DS_ICLR
Definition: tle987x.h:5375
__IOM uint32_t VS_UV_IE
Definition: tle987x.h:5258
__IM uint32_t PHV_ZCLOW_IS
Definition: tle987x.h:5210
__OM uint32_t MON_OV_ICLR
Definition: tle987x.h:5278
__IM uint32_t LS2_DS_IS
Definition: tle987x.h:5416
__IOM uint32_t VDD1V5_OV_IE
Definition: tle987x.h:5264
__IM uint32_t DBFSTS
Definition: tle987x.h:5504
__IOM uint32_t REFBG_LOTHWARN_IE
Definition: tle987x.h:5310
__IM uint32_t PHU_ZCHI_IS
Definition: tle987x.h:5209
__IM uint32_t VREF5V_OVL_IS
Definition: tle987x.h:5206
__IM uint32_t PHV_ZCHI_IS
Definition: tle987x.h:5211
__IOM uint32_t MON_UV_IE
Definition: tle987x.h:5257
__IM uint32_t LS1_OC_IS
Definition: tle987x.h:5425
__IOM uint32_t VCP_LOWTH1_IE
Definition: tle987x.h:5479
__IM uint32_t VS_UV_STS
Definition: tle987x.h:5241
__IM uint32_t MON_OV_IS
Definition: tle987x.h:5235
__IM uint32_t VDD1V5_UV_STS
Definition: tle987x.h:5243
__IM uint32_t HS1_OC_IS
Definition: tle987x.h:5427
__OM uint32_t REFBG_UPTHWARN_ICLR
Definition: tle987x.h:5155
__IOM uint32_t ADC3_EOC_IE
Definition: tle987x.h:5324
__OM uint32_t VCP_LOWTH1_SCLR
Definition: tle987x.h:5397
__IM uint32_t VDD1V5_OV_IS
Definition: tle987x.h:5238
__OM uint32_t VREF5V_LOWTH_ICLR
Definition: tle987x.h:5157
__IOM uint32_t LIN_OT_IE
Definition: tle987x.h:5301
__IOM uint32_t HS1_DS_IE
Definition: tle987x.h:5464
__OM uint32_t VS_OV_ICLR
Definition: tle987x.h:5279
__IM uint32_t HS3_DS_IS
Definition: tle987x.h:5422
__IOM uint32_t SYS_VSD_OV_SLM_DIS
Definition: tle987x.h:5342
__IOM uint32_t FAIL_PS_DIS
Definition: tle987x.h:5339
__OM uint32_t PHU_ZCLOW_SCLR
Definition: tle987x.h:5171
__IM uint32_t PHV_ZCLOW_STS
Definition: tle987x.h:5218
__OM uint32_t VCP_UPTH_SCLR
Definition: tle987x.h:5399
__OM uint32_t VDD5V_UV_ICLR
Definition: tle987x.h:5276
__IOM uint32_t LS3_OC_IE
Definition: tle987x.h:5476
__IM uint32_t HS2_DS_IS
Definition: tle987x.h:5419
__IOM uint32_t PMU_OTWARN_IE
Definition: tle987x.h:5304
__IOM uint32_t SYS_OT_IE
Definition: tle987x.h:5308
__IOM uint32_t VDD1V5_UV_IE
Definition: tle987x.h:5260
__IM uint32_t PHW_ZCHI_IS
Definition: tle987x.h:5213
__IOM uint32_t LIN_VS_UV_SD_DIS
Definition: tle987x.h:5340
__IM uint32_t AMCLK2_FREQ
Definition: tle987x.h:5102
__IM uint32_t PHU_ZCLOW_IS
Definition: tle987x.h:5208
__OM uint32_t LS3_DS_ICLR
Definition: tle987x.h:5374
__IM uint32_t AMCLK1_FREQ
Definition: tle987x.h:5099
__IOM uint32_t SYS_OT_PS_DIS
Definition: tle987x.h:5344
__OM uint32_t ADC3_EOC_ICLR
Definition: tle987x.h:5169
__IOM uint32_t AMCLK1_UP_HYS
Definition: tle987x.h:5124
__IM uint32_t
Definition: tle987x.h:5101
__OM uint32_t PHW_ZCLOW_SCLR
Definition: tle987x.h:5175
__IOM uint32_t AMCLK2_UP_HYS
Definition: tle987x.h:5128
__OM uint32_t VCP_LOWTH1_ICLR
Definition: tle987x.h:5386
__IOM uint32_t CLKLOSS_SD_DIS
Definition: tle987x.h:5345
__OM uint32_t ADC4_EOC_ICLR
Definition: tle987x.h:5170
__OM uint32_t VCP_LOWTH2_ICLR
Definition: tle987x.h:5384
__IOM uint32_t WDP_SEL
Definition: tle987x.h:5356
__IM uint32_t HS2_OC_IS
Definition: tle987x.h:5428
__IM uint32_t VS_UV_IS
Definition: tle987x.h:5232
__OM uint32_t PHV_ZCLOW_SCLR
Definition: tle987x.h:5173
__IOM uint32_t AMCLK1_LOW_TH
Definition: tle987x.h:5125
__IM uint32_t SBFSTS
Definition: tle987x.h:5505
__OM uint32_t VDD1V5_OV_SCLR
Definition: tle987x.h:5290
__IM uint32_t REFBG_UPTHWARN_IS
Definition: tle987x.h:5200
__IOM uint32_t CLKWDT_RES_SD_DIS
Definition: tle987x.h:5346
__IOM uint32_t LIN_OC_IE
Definition: tle987x.h:5300
__OM uint32_t MON_OV_SCLR
Definition: tle987x.h:5287
__IM uint32_t SYS_OT_IS
Definition: tle987x.h:5196
__IOM uint32_t VCP_UPTH_IE
Definition: tle987x.h:5480
__OM uint32_t VSD_LOWTH_ICLR
Definition: tle987x.h:5390
__IOM uint32_t LIN_TMOUT_IE
Definition: tle987x.h:5302
__IOM uint32_t LS1_DS_IE
Definition: tle987x.h:5462
__IOM uint32_t VSD_LOWTH_IE
Definition: tle987x.h:5481
__OM uint32_t PHV_ZCHI_ICLR
Definition: tle987x.h:5166
__OM uint32_t DBFSTSCLR
Definition: tle987x.h:5535
__IOM uint32_t MON_OV_IE
Definition: tle987x.h:5261
__IM uint32_t ADC4_EOC_IS
Definition: tle987x.h:5215
__IOM uint32_t AMCLK2_LOW_HYS
Definition: tle987x.h:5130
__IM uint32_t VREF5V_LOWTH_IS
Definition: tle987x.h:5202
__OM uint32_t PHW_ZCHI_ICLR
Definition: tle987x.h:5168
__OM uint32_t ADC2_ESM_ICLR
Definition: tle987x.h:5162
__OM uint32_t VDD5V_OV_ICLR
Definition: tle987x.h:5280
__IM uint32_t VCP_UPTH_STS
Definition: tle987x.h:5446
__IM uint32_t MON_UV_STS
Definition: tle987x.h:5240
__IM uint32_t DBFA
Definition: tle987x.h:5515
__IOM uint32_t STCALIB
Definition: tle987x.h:5493
__IOM uint32_t HS2_DS_IE
Definition: tle987x.h:5466
__OM uint32_t VS_UV_SCLR
Definition: tle987x.h:5284
__OM uint32_t PMU_OT_ICLR
Definition: tle987x.h:5147
__IOM uint32_t LS3_DS_IE
Definition: tle987x.h:5468
__OM uint32_t VREF5V_UPTH_ICLR
Definition: tle987x.h:5159
__IM uint32_t VS_OV_STS
Definition: tle987x.h:5245
__OM uint32_t PHU_ZCHI_SCLR
Definition: tle987x.h:5172
__IM uint32_t MON_OV_STS
Definition: tle987x.h:5244
__IM uint32_t LS3_OC_IS
Definition: tle987x.h:5429
__IM uint32_t VS_OV_IS
Definition: tle987x.h:5236
__IM uint32_t VCP_LOWTH1_IS
Definition: tle987x.h:5433
__IOM uint32_t VREF5V_UPTH_IE
Definition: tle987x.h:5314
__IM uint32_t PMU_OTWARN_IS
Definition: tle987x.h:5190
__OM uint32_t PHV_ZCHI_SCLR
Definition: tle987x.h:5174
__IOM uint32_t CLKWDT_SD_DIS
Definition: tle987x.h:5337
__IM uint32_t ADC3_EOC_IS
Definition: tle987x.h:5214
__IOM uint32_t PHU_ZCHI_IE
Definition: tle987x.h:5319
__OM uint32_t VS_OV_SCLR
Definition: tle987x.h:5288
__IOM uint32_t HS1_OC_IE
Definition: tle987x.h:5474
__OM uint32_t SYS_OTWARN_ICLR
Definition: tle987x.h:5149
__OM uint32_t PMU_OTWARN_ICLR
Definition: tle987x.h:5145
__OM uint32_t HS2_DS_ICLR
Definition: tle987x.h:5372
__OM uint32_t VDD5V_UV_SCLR
Definition: tle987x.h:5285
__OM uint32_t LS1_OC_ICLR
Definition: tle987x.h:5378
__IOM uint32_t VSD_UPTH_IE
Definition: tle987x.h:5482
__IM uint32_t RESERVED
Definition: tle987x.h:5115
__OM uint32_t HS1_DS_ICLR
Definition: tle987x.h:5370
__OM uint32_t HS1_OC_ICLR
Definition: tle987x.h:5380
__IM uint32_t SBFA
Definition: tle987x.h:5525
__OM uint32_t LIN_OC_ICLR
Definition: tle987x.h:5141
__OM uint32_t REFBG_LOTHWARN_ICLR
Definition: tle987x.h:5153
__OM uint32_t VSD_UPTH_ICLR
Definition: tle987x.h:5392
__IOM uint32_t VDD5V_OV_IE
Definition: tle987x.h:5263
__IOM uint32_t ADC2_ESM_IE
Definition: tle987x.h:5317
__IOM uint32_t reg
Definition: tle987x.h:5095
__IOM uint32_t VDD5V_UV_IE
Definition: tle987x.h:5259
__IM uint32_t HS1_DS_IS
Definition: tle987x.h:5417
__OM uint32_t PHW_ZCLOW_ICLR
Definition: tle987x.h:5167
__OM uint32_t PHV_ZCLOW_ICLR
Definition: tle987x.h:5165
__IOM uint32_t LS1_OC_IE
Definition: tle987x.h:5472
__OM uint32_t PHU_ZCLOW_ICLR
Definition: tle987x.h:5163
__OM uint32_t VREF5V_OVL_ICLR
Definition: tle987x.h:5161
__OM uint32_t VDD1V5_UV_ICLR
Definition: tle987x.h:5277
__IM uint32_t VSD_UPTH_STS
Definition: tle987x.h:5450
__IM uint32_t VSD_LOWTH_STS
Definition: tle987x.h:5448
__IM uint32_t LIN_TMOUT_IS
Definition: tle987x.h:5188
__IOM uint32_t PHW_ZCHI_IE
Definition: tle987x.h:5323
__IM uint32_t LIN_OC_IS
Definition: tle987x.h:5186
__OM uint32_t LS2_DS_ICLR
Definition: tle987x.h:5369
__IOM uint32_t HS3_OC_IE
Definition: tle987x.h:5477
__OM uint32_t LS3_OC_ICLR
Definition: tle987x.h:5382
__OM uint32_t VS_UV_ICLR
Definition: tle987x.h:5275
__IM uint32_t REFBG_LOTHWARN_IS
Definition: tle987x.h:5198
__IOM uint32_t PHV_ZCHI_IE
Definition: tle987x.h:5321
__IM uint32_t VDD5V_OV_IS
Definition: tle987x.h:5237
__IM uint32_t RESERVED2
Definition: tle987x.h:5328
__IM uint32_t LS1_DS_IS
Definition: tle987x.h:5415
__OM uint32_t SYS_OT_ICLR
Definition: tle987x.h:5151
__OM uint32_t LS2_OC_ICLR
Definition: tle987x.h:5379
__IOM uint32_t ADC4_EOC_IE
Definition: tle987x.h:5325
__IM uint32_t LS2_OC_IS
Definition: tle987x.h:5426
__OM uint32_t LS1_DS_ICLR
Definition: tle987x.h:5368
__IM uint32_t PMU_OT_IS
Definition: tle987x.h:5192
__IOM uint32_t VS_OV_IE
Definition: tle987x.h:5262
__OM uint32_t MON_UV_SCLR
Definition: tle987x.h:5283
__IM uint32_t VCP_LOWTH2_IS
Definition: tle987x.h:5431
__OM uint32_t PHU_ZCHI_ICLR
Definition: tle987x.h:5164
__IOM uint32_t LS2_DS_IE
Definition: tle987x.h:5463
__OM uint32_t VDD5V_OV_SCLR
Definition: tle987x.h:5289
__IOM uint32_t VREF5V_LOWTH_IE
Definition: tle987x.h:5312
__IM uint32_t PHW_ZCLOW_STS
Definition: tle987x.h:5220
__IM uint32_t RESERVED1
Definition: tle987x.h:5133
__OM uint32_t PHW_ZCHI_SCLR
Definition: tle987x.h:5176
__IOM uint32_t REFBG_UPTHWARN_IE
Definition: tle987x.h:5311
__OM uint32_t SBFSTSCLR
Definition: tle987x.h:5536
__IM uint32_t VCP_UPTH_IS
Definition: tle987x.h:5435
__OM uint32_t VCP_LOWTH2_SCLR
Definition: tle987x.h:5395
__IOM uint32_t AMCLK1_LOW_HYS
Definition: tle987x.h:5126
__OM uint32_t LIN_OT_ICLR
Definition: tle987x.h:5142
__OM uint32_t HS2_OC_ICLR
Definition: tle987x.h:5381
__OM uint32_t VDD1V5_UV_SCLR
Definition: tle987x.h:5286
__IM uint32_t VDD5V_UV_STS
Definition: tle987x.h:5242
__IM uint32_t MON_UV_IS
Definition: tle987x.h:5231
__OM uint32_t MON_UV_ICLR
Definition: tle987x.h:5274
__IM uint32_t VDD1V5_OV_STS
Definition: tle987x.h:5247
__IM uint32_t VDD5V_UV_IS
Definition: tle987x.h:5233
__IM uint32_t VSD_UPTH_IS
Definition: tle987x.h:5439
__IOM uint32_t SYS_OTWARN_IE
Definition: tle987x.h:5307
__IOM uint32_t PHW_ZCLOW_IE
Definition: tle987x.h:5322
__IOM uint32_t VCP_LOWTH2_IE
Definition: tle987x.h:5478
__IM uint32_t VDD1V5_UV_IS
Definition: tle987x.h:5234
__IM uint32_t VCP_LOWTH1_STS
Definition: tle987x.h:5444
__IOM uint32_t CLKWDT_PD_N
Definition: tle987x.h:5112
__IOM uint32_t PMU_OT_IE
Definition: tle987x.h:5305
SSC1 Module (SSC1)
Definition: tle987x.h:5553
__IM uint16_t TE
Definition: tle987x.h:5589
__IOM uint16_t BR_VALUE
Definition: tle987x.h:5629
__OM uint16_t PECLR
Definition: tle987x.h:5643
__IM uint16_t BSY
Definition: tle987x.h:5593
__OM uint16_t RECLR
Definition: tle987x.h:5642
__OM uint16_t BECLR
Definition: tle987x.h:5644
__IOM uint16_t MIS_0
Definition: tle987x.h:5561
__IM uint16_t RB_VALUE
Definition: tle987x.h:5618
__IM uint16_t RESERVED4
Definition: tle987x.h:5632
__IM uint16_t
Definition: tle987x.h:5588
__IOM uint16_t SIS
Definition: tle987x.h:5565
__IOM uint16_t reg
Definition: tle987x.h:5557
__IOM uint16_t MIS_1
Definition: tle987x.h:5575
__OM uint16_t TECLR
Definition: tle987x.h:5641
__IOM uint16_t TB_VALUE
Definition: tle987x.h:5607
__IM uint16_t PE
Definition: tle987x.h:5591
__IOM uint16_t CIS
Definition: tle987x.h:5570
__IM uint16_t BC
Definition: tle987x.h:5587
__IM uint16_t RE
Definition: tle987x.h:5590
__IOM uint16_t EN
Definition: tle987x.h:5596
__IM uint16_t RESERVED1
Definition: tle987x.h:5599
__IM uint16_t BE
Definition: tle987x.h:5592
__IM uint16_t RESERVED3
Definition: tle987x.h:5621
__IM uint16_t RESERVED
Definition: tle987x.h:5579
__IM uint16_t RESERVED2
Definition: tle987x.h:5610
__IOM uint16_t MS
Definition: tle987x.h:5595
SSC2 Module (SSC2)
Definition: tle987x.h:5661
__IM uint16_t TE
Definition: tle987x.h:5697
__IOM uint16_t BR_VALUE
Definition: tle987x.h:5737
__OM uint16_t PECLR
Definition: tle987x.h:5751
__IM uint16_t BSY
Definition: tle987x.h:5701
__OM uint16_t RECLR
Definition: tle987x.h:5750
__OM uint16_t BECLR
Definition: tle987x.h:5752
__IOM uint16_t MIS_0
Definition: tle987x.h:5669
__IM uint16_t RB_VALUE
Definition: tle987x.h:5726
__IM uint16_t RESERVED4
Definition: tle987x.h:5740
__IM uint16_t
Definition: tle987x.h:5696
__IOM uint16_t SIS
Definition: tle987x.h:5673
__IOM uint16_t reg
Definition: tle987x.h:5665
__IOM uint16_t MIS_1
Definition: tle987x.h:5683
__OM uint16_t TECLR
Definition: tle987x.h:5749
__IOM uint16_t TB_VALUE
Definition: tle987x.h:5715
__IM uint16_t PE
Definition: tle987x.h:5699
__IOM uint16_t CIS
Definition: tle987x.h:5678
__IM uint16_t BC
Definition: tle987x.h:5695
__IM uint16_t RE
Definition: tle987x.h:5698
__IOM uint16_t EN
Definition: tle987x.h:5704
__IM uint16_t RESERVED1
Definition: tle987x.h:5707
__IM uint16_t BE
Definition: tle987x.h:5700
__IM uint16_t RESERVED3
Definition: tle987x.h:5729
__IM uint16_t RESERVED
Definition: tle987x.h:5687
__IM uint16_t RESERVED2
Definition: tle987x.h:5718
__IOM uint16_t MS
Definition: tle987x.h:5703
TIMER2x Module (TIMER2x)
Definition: tle987x.h:5769
__IOM uint8_t EXF2EN
Definition: tle987x.h:5854
__IOM uint8_t PREN
Definition: tle987x.h:5796
__IOM uint8_t CP_RL2
Definition: tle987x.h:5777
__IOM uint8_t TR2
Definition: tle987x.h:5779
__IM uint8_t
Definition: tle987x.h:5781
__IOM uint8_t EXEN2
Definition: tle987x.h:5780
__IOM uint8_t T2REGS
Definition: tle987x.h:5799
__IOM uint8_t RC2
Definition: tle987x.h:5810
__IOM uint8_t DCEN
Definition: tle987x.h:5794
__IM uint8_t TF2
Definition: tle987x.h:5783
__IOM uint8_t T2L
Definition: tle987x.h:5832
__IM uint8_t EXF2
Definition: tle987x.h:5782
__IOM uint8_t TF2EN
Definition: tle987x.h:5855
__IOM uint8_t EDGESEL
Definition: tle987x.h:5797
__OM uint8_t EXF2CLR
Definition: tle987x.h:5867
__IOM uint8_t T2H
Definition: tle987x.h:5843
__IOM uint8_t T2PRE
Definition: tle987x.h:5795
__OM uint8_t TF2CLR
Definition: tle987x.h:5868
__IOM uint8_t T2RHEN
Definition: tle987x.h:5798
__IOM uint8_t reg
Definition: tle987x.h:5773
__IOM uint8_t C_T2
Definition: tle987x.h:5778
TIMER3 Module (TIMER3)
Definition: tle987x.h:5885
__IOM uint32_t T3_RD_REQ
Definition: tle987x.h:5930
__IOM uint32_t TR3H
Definition: tle987x.h:5933
__IOM uint32_t T3_RD_REQ_CONF
Definition: tle987x.h:5931
__IOM uint32_t T3_PD_N
Definition: tle987x.h:5929
__IM uint32_t T3H_OVF_STS
Definition: tle987x.h:5934
__IOM uint32_t T3_RES_CONF
Definition: tle987x.h:5895
__IOM uint32_t T3H_OVF_IE
Definition: tle987x.h:5938
__IOM uint32_t RETRIG
Definition: tle987x.h:5896
__IM uint32_t
Definition: tle987x.h:5894
__IOM uint32_t CNT_RDY
Definition: tle987x.h:5932
__IOM uint32_t T3_SUBM
Definition: tle987x.h:5950
__IOM uint32_t LO
Definition: tle987x.h:5907
__IM uint32_t T3L_OVF_STS
Definition: tle987x.h:5936
__IOM uint32_t TR3L
Definition: tle987x.h:5935
__IOM uint32_t reg
Definition: tle987x.h:5889
__IOM uint32_t T3L_OVF_IE
Definition: tle987x.h:5937
__IOM uint32_t HI
Definition: tle987x.h:5908
__IOM uint32_t T3_TRIGG_INP_SEL
Definition: tle987x.h:5893
__OM uint32_t T3L_OVF_ICLR
Definition: tle987x.h:5963
__OM uint32_t T3H_OVF_ICLR
Definition: tle987x.h:5961
__IOM uint32_t T3M
Definition: tle987x.h:5948
UARTx Module (UARTx)
Definition: tle987x.h:5980
__OM uint8_t TICLR
Definition: tle987x.h:6019
__IOM uint8_t TI
Definition: tle987x.h:5989
__IOM uint8_t REN
Definition: tle987x.h:5992
__IOM uint8_t SM0
Definition: tle987x.h:5996
__IOM uint8_t SM2
Definition: tle987x.h:5993
__IOM uint8_t SM1
Definition: tle987x.h:5995
__IOM uint8_t RI
Definition: tle987x.h:5988
__IOM uint8_t TB8
Definition: tle987x.h:5991
__IOM uint8_t RB8
Definition: tle987x.h:5990
__OM uint8_t RICLR
Definition: tle987x.h:6018
__IOM uint8_t VAL
Definition: tle987x.h:6007
__IOM uint8_t reg
Definition: tle987x.h:5984
System file for TLE987x.