Infineon MOTIX™ MCU TLE987x Device Family SDK
bdrv.h
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37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** TA Thomas Albersinger **
44 ** AP Adriano Pereira **
45 ** BG Blandine Guillot **
46 ** JO Julia Ott **
47 ** VO Vanessa Ongaro **
48 *******************************************************************************/
49 
50 /*******************************************************************************
51 ** Revision Control History **
52 ********************************************************************************
53 ** V0.1.0: 2013-02-10, DM: Initial version **
54 ** V0.1.1: 2013-05-24, DM: Bdrv_Diag functions removed **
55 ** Bdrv_Clr_Sts changed, to be robust against **
56 ** unintended flag clearing **
57 ** Open-Load detection function added **
58 ** V0.2.0: 2013-09-20, DM: Function and settings adapted to B-Step device **
59 ** V0.3.0: 2014-04-25, TA: Bdrv_Init(): use #defines from IFX Config Wizard **
60 ** V0.3.1: 2015-02-10, DM: Individual header file added **
61 ** V0.3.2: 2015-07-15, DM: BEMF register init added **
62 ** V0.3.3: 2015-11-12, DM: Disabled interrupts before writing TRIM_DRVx **
63 ** V0.3.4: 2016-07-28, DM: OpenLoad detection for 3-phase motors added **
64 ** V0.3.5: 2016-09-23, DM: OpenLoad detection current set to 1 **
65 ** V0.3.6: 2017-02-16, DM: Bdrv prefix changed to capital letter **
66 ** V0.3.7: 2017-07-25, DM: A nop was added after each status flag clear **
67 ** V0.3.8: 2017-09-26, DM: MISRA 2012 compliance, the following PC-Lint **
68 ** rules are globally deactivated: **
69 ** - Info 793: ANSI/ISO limit of 6 'significant **
70 ** characters in an external identifier **
71 ** - Info 835: A zero has been given as right **
72 ** argument to operator **
73 ** - Info 845: The left argument to operator '&' **
74 ** is certain to be 0 **
75 ** V0.3.9: 2018-02-02, DM: BDRV_Off_Diagnosis() function added **
76 ** V0.4.0: 2018-03-14, DM: BDRV_Clr_Sts() type of parameter changed to **
77 ** (uint32) due to MISRA 2012 **
78 ** typedef TBdrv_Sts replaced by #define macros **
79 ** due to MISRA 2012 **
80 ** Replaced macros by INLINE functions **
81 ** Replaced register accesses within functions by **
82 ** function calls **
83 ** V0.4.1: 2018-07-04, AP: Updated BDRV_Set_Bridge(), BDRV_Clr_Sts(), **
84 ** BDRV_Set_Channel() to use API functions (instead **
85 ** of direct access to registers) **
86 ** Fixed BDRV_Set_Int_Channel() to allow interrupt **
87 ** disabling **
88 ** V0.4.2: 2018-07-30, AP: Added functions to get BDRV interrupt status **
89 ** Added BDRV_Set_DSM_Threshold() and **
90 ** BDRV_Set_Discharge_Current() **
91 ** Updated BDRV_Diag_OpenLoad() and **
92 ** BDRV_Off_Diagnosis to use new APIs **
93 ** V0.4.3: 2018-11-27, JO: Doxygen update **
94 ** Moved revision history from bdrv.c to bdrv.h **
95 ** V0.4.4: 2020-04-15, BG: Updated revision history format **
96 ** V0.4.5: 2020-07-21, BG: EP-439: Formatted .h/.c files **
97 ** V0.4.6: 2021-02-26, JO: EP-715: Removed type TBdrv_Disch_Curr (not used **
98 ** anymore), added type TBDRV_Curr **
99 ** Removed function BDRV_Set_Discharge_Current **
100 ** Added functions to get/set the Chrg/Dischrg **
101 ** current and current range in mA via TBDRV_Curr **
102 ** (BDRV_getChrgCurrent_mA, BDRV_setChrgCurrent_mA, **
103 ** BDRV_getDischrgCurrent_mA, **
104 ** BDRV_setDischrgCurrent_mA) **
105 ** Added functions to get/set the Chrg/Dischrg **
106 ** current and current range (digital value) **
107 ** V0.4.7: 2021-04-23, BG: EP-726: Corrected MISRA 2012 violations **
108 ** V0.4.8: 2021-05-26, BG: EP-827: Corrected initialization of CTRL1 and **
109 ** CTRL2 registers with the CW defines **
110 ** V0.4.9: 2021-08-03, JO: EP-896: Disabled MISRA rule 9034 locally when **
111 ** casting int to enum (lint...) **
112 ** V0.5.0: 2022-02-25, JO: EP-1040: Corrected usage of CMSIS_Irq_Dis() **
113 ** V0.5.1: 2022-02-28, JO: EP-936: Updated copyright and branding **
114 ** V0.6.0: 2022-10-10, JO: EP-1142: Added functions BDRV_ChargePump_En/Dis **
115 ** V0.6.1: 2022-10-18, VO: EP-1252: Removed ARMCC V6.18 warnings **
116 *******************************************************************************/
117 
118 #ifndef _BDR_H
119 #define _BDR_H
120 
121 /*******************************************************************************
122 ** Includes **
123 *******************************************************************************/
124 #include "tle_variants.h"
125 #include "sfr_access.h"
126 #include "scu.h"
127 #include "int.h"
128 #include "wdt1.h"
129 
130 /*******************************************************************************
131 ** Global Macro Definitions **
132 *******************************************************************************/
133 #define TBDRV_Curr_RANGE_POS 5u
134 #define TBDRV_Curr_CURRENT_MASK 0x3Fu
135 
136 /*******************************************************************************
137 ** Global Type Definitions **
138 *******************************************************************************/
139 
143 typedef enum Bdrv_Ch_Cfg
144 {
145  Ch_Off = 0u,
146  Ch_En = 1u,
147  Ch_PWM = 3u,
148  Ch_On = 5u,
149  Ch_DCS = 9u
151 
155 typedef enum Bdrv_Ch
156 {
157  LS1 = 0u,
158  LS2 = 1u,
159  HS1 = 2u,
160  HS2 = 3u
161 #if (UC_SERIES == TLE987)
162  ,
163  LS3 = 4u,
164  HS3 = 5u
165 #endif
167 
169 #define LS1_DS SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk
170 #define LS2_DS SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk
171 #define HS1_DS SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk
172 #define HS2_DS SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk
173 #define LS1_OC SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk
174 #define LS2_OC SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk
175 #define HS1_OC SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk
176 #define HS2_OC SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk
177 #if (UC_SERIES == TLE987)
178  #define LS3_DS SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk
179  #define HS3_DS SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk
180  #define LS3_OC SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk
181  #define HS3_OC SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk
182 #endif
183 
187 typedef enum BDRV_Off_Diag_Sts
188 {
189  Ch_Ok = 0u,
191  Ch_Short_to_VBat = 2u
193 
197 typedef struct
198 {
202 #if (UC_SERIES == TLE987)
204 #endif
206 
210 typedef enum Bdrv_Ch_Int
211 {
212  Int_Off = 0U,
213  Int_DS = 1U,
214  Int_OC = 2U,
215  Int_DS_OC = 3U
217 
221 typedef enum Bdrv_DSM_Threshold
222 {
230  Threshold_2_00_V = 7U
232 
237 typedef enum BDRV_Curr
238 {
239  /* Half Range */
272  /* Full Range */
304  BDRV_Curr_FR_310mA = 63U
306 
307 #if (UC_SERIES == TLE987)
308  #define BDRV_ISCLR_OC (LS1_OC | HS1_OC | LS2_OC | HS2_OC | LS3_OC | HS3_OC)
309  #define BDRV_ISCLR_DS (LS1_DS | HS1_DS | LS2_DS | HS2_DS | LS3_DS | HS3_DS)
310 #else
311  #define BDRV_ISCLR_OC (LS1_OC | HS1_OC | LS2_OC | HS2_OC)
312  #define BDRV_ISCLR_DS (LS1_DS | HS1_DS | LS2_DS | HS2_DS)
313 #endif
314 #define BDRV_IRQ_BITS (BDRV_ISCLR_OC | BDRV_ISCLR_DS)
315 #define BDRV_DS_STS_BITS BDRV_ISCLR_DS
316 
317 /*******************************************************************************
318 ** Global Inline Function Definitions **
319 *******************************************************************************/
333 {
335 }
336 
350 {
352 }
353 
372 {
374 }
375 
394 {
396 }
397 
416 {
418 }
419 
438 {
440 }
441 
442 #if (UC_SERIES == TLE987)
461 {
463 }
464 #endif
465 
466 #if (UC_SERIES == TLE987)
485 {
487 }
488 #endif
489 
508 {
510 }
511 
530 {
532 }
533 
552 {
554 }
555 
574 {
576 }
577 
578 #if (UC_SERIES == TLE987)
597 {
599 }
600 #endif
601 
602 #if (UC_SERIES == TLE987)
621 {
623 }
624 #endif
625 
644 {
646 }
647 
666 {
668 }
669 
689 {
691 }
692 
711 {
713 }
714 
734 {
736 }
737 
756 {
758 }
759 
779 {
781 }
782 
801 {
803 }
804 
824 {
826 }
827 
828 #if (UC_SERIES == TLE987)
847 {
849 }
850 #endif
851 
852 #if (UC_SERIES == TLE987)
872 {
874 }
875 #endif
876 
877 #if (UC_SERIES == TLE987)
896 {
898 }
899 #endif
900 
901 #if (UC_SERIES == TLE987)
921 {
923 }
924 #endif
925 
944 {
946 }
947 
967 {
969 }
970 
989 {
991 }
992 
1012 {
1014 }
1015 
1034 {
1036 }
1037 
1057 {
1059 }
1060 
1079 {
1081 }
1082 
1102 {
1104 }
1105 
1106 #if (UC_SERIES == TLE987)
1125 {
1127 }
1128 #endif
1129 
1130 #if (UC_SERIES == TLE987)
1150 {
1152 }
1153 #endif
1154 
1155 #if (UC_SERIES == TLE987)
1174 {
1176 }
1177 #endif
1178 
1179 #if (UC_SERIES == TLE987)
1199 {
1201 }
1202 #endif
1203 
1222 {
1224 }
1225 
1245 {
1247 }
1248 
1254 {
1256 }
1257 
1263 {
1265 }
1266 
1272 {
1274 }
1275 
1281 {
1283 }
1284 
1285 #if (UC_SERIES == TLE987)
1291 {
1293 }
1294 #endif
1295 
1296 #if (UC_SERIES == TLE987)
1302 {
1304 }
1305 #endif
1306 
1312 {
1314 }
1315 
1321 {
1323 }
1324 
1330 {
1332 }
1333 
1339 {
1341 }
1342 
1343 #if (UC_SERIES == TLE987)
1349 {
1351 }
1352 #endif
1353 
1354 #if (UC_SERIES == TLE987)
1360 {
1362 }
1363 #endif
1364 
1370 {
1372 }
1373 
1379 {
1380  return BDRV->CTRL3.bit.ICHARGE_TRIM;
1381 }
1382 
1389 {
1390  BDRV->CTRL3.bit.ICHARGE_TRIM = u8_cur_dig;
1391 }
1392 
1398 {
1399  return BDRV->CTRL3.bit.ICHARGEDIV2_N;
1400 }
1401 
1408 {
1409  BDRV->CTRL3.bit.ICHARGEDIV2_N = u8_cur_range_dig;
1410 }
1411 
1417 {
1418  return BDRV->CTRL3.bit.IDISCHARGE_TRIM;
1419 }
1420 
1427 {
1428  BDRV->CTRL3.bit.IDISCHARGE_TRIM = u8_cur_dig;
1429 }
1430 
1436 {
1437  return BDRV->CTRL3.bit.IDISCHARGEDIV2_N;
1438 }
1439 
1446 {
1447  BDRV->CTRL3.bit.IDISCHARGEDIV2_N = u8_cur_range_dig;
1448 }
1449 
1450 /*******************************************************************************
1451 ** Global Variable Declarations **
1452 *******************************************************************************/
1457 void BDRV_Init(void);
1458 
1459 #if (UC_SERIES == TLE987)
1482  TBdrv_Ch_Cfg HS1_Cfg,
1483  TBdrv_Ch_Cfg LS2_Cfg,
1484  TBdrv_Ch_Cfg HS2_Cfg,
1485  TBdrv_Ch_Cfg LS3_Cfg,
1486  TBdrv_Ch_Cfg HS3_Cfg);
1487 #else
1506 void BDRV_Set_Bridge(TBdrv_Ch_Cfg LS1_Cfg,
1507  TBdrv_Ch_Cfg HS1_Cfg,
1508  TBdrv_Ch_Cfg LS2_Cfg,
1509  TBdrv_Ch_Cfg HS2_Cfg);
1510 #endif
1511 
1528 
1543 void BDRV_Clr_Sts(uint32 Sts_Bit);
1544 
1561 
1584 
1594 
1595 
1603 
1612 
1621 
1630 
1639 
1640 
1641 #endif
enum Bdrv_Ch_Cfg TBdrv_Ch_Cfg
bool BDRV_Diag_OpenLoad(void)
Open Load detection, detects whether a motor is connected.
INLINE void BDRV_HS3_DS_Int_En(void)
enables High Side Driver 3 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1124
INLINE void BDRV_LS1_OC_Int_Dis(void)
disables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:733
INLINE void BDRV_LS1_DS_Int_Dis(void)
disables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1011
INLINE uint8 BDRV_HS2_DS_Int_Sts(void)
Reads the Bridge Driver High-Side 2 Pre-Driver Short Status Flag.
Definition: bdrv.h:1329
INLINE void BDRV_setChrgCurrent_dig(uint8 u8_cur_dig)
Sets the Trimming of the internal driver charge current (Digital value)
Definition: bdrv.h:1388
INLINE void BDRV_LS1_OC_Int_En(void)
enables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:710
INLINE void BDRV_HS3_DS_Int_Clr(void)
clears High Side Driver 3 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:596
INLINE void BDRV_LS2_OC_Int_Clr(void)
clears External Low Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:437
void BDRV_Clr_Sts(uint32 Sts_Bit)
clears individual status flags and interrupt status flags of the BridgeDriver
INLINE uint8 BDRV_HS3_DS_Int_Sts(void)
Reads the Bridge Driver High-Side 3 Pre-Driver Short Status Flag.
Definition: bdrv.h:1348
INLINE uint8 BDRV_VCP_LO_Int_Sts(void)
Reads the Bridge Driver VCP Lower Threshold 2 Measurement Status Flag.
Definition: bdrv.h:1369
INLINE uint8 BDRV_LS2_OC_Int_Sts(void)
Reads the Bridge Driver Low-Side 2 Over-Current Status Flag.
Definition: bdrv.h:1280
INLINE uint8 BDRV_getDischrgCurrentRange_dig(void)
Returns the Discharge current range select (Digital value)
Definition: bdrv.h:1435
INLINE void BDRV_LS2_DS_Int_Clr(void)
clears Low Side Driver 2 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:573
Bdrv_Ch_Int
Definition: bdrv.h:211
@ Int_DS
Drain-Source interrupt enable (Off-Diagnosis)
Definition: bdrv.h:213
@ Int_Off
all interrupts disable
Definition: bdrv.h:212
@ Int_OC
Over-Current interrupt enable (On-Diagnosis)
Definition: bdrv.h:214
@ Int_DS_OC
Drain-Source and Over-Current interrupt enable.
Definition: bdrv.h:215
enum Bdrv_Ch_Int TBdrv_Ch_Int
INLINE void BDRV_HS2_OC_Int_Dis(void)
disables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:778
INLINE uint8 BDRV_LS2_DS_Int_Sts(void)
Reads the Bridge Driver Low-Side 2 Pre-Driver Short Status Flag.
Definition: bdrv.h:1338
INLINE void BDRV_HS2_DS_Int_En(void)
enables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1033
INLINE void BDRV_HS3_OC_Int_Clr(void)
clears External High Side 3 FET Over-current interrupt flag.
Definition: bdrv.h:460
INLINE void BDRV_ChargePump_En(void)
enables the Charge Pump.
Definition: bdrv.h:332
void BDRV_Set_Int_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Int Ch_Int)
sets Interrupt Enable for the individual MOSFETs (channels)
INLINE uint8 BDRV_HS3_OC_Int_Sts(void)
Reads the Bridge Driver High-Side 3 Over-Current Status Flag.
Definition: bdrv.h:1290
BDRV_Curr
Definition: bdrv.h:238
@ BDRV_Curr_FR_70mA
typ. current ~70 mA
Definition: bdrv.h:280
@ BDRV_Curr_HR_95mA
typ. current ~95 mA
Definition: bdrv.h:259
@ BDRV_Curr_HR_25mA
typ. current ~25 mA
Definition: bdrv.h:245
@ BDRV_Curr_FR_280mA
typ. current ~280 mA
Definition: bdrv.h:301
@ BDRV_Curr_FR_250mA
typ. current ~250 mA
Definition: bdrv.h:298
@ BDRV_Curr_FR_190mA
typ. current ~190 mA
Definition: bdrv.h:292
@ BDRV_Curr_HR_60mA
typ. current ~60 mA
Definition: bdrv.h:252
@ BDRV_Curr_FR_300mA
typ. current ~300 mA
Definition: bdrv.h:303
@ BDRV_Curr_HR_Disabled
(HiZ) Slew Rate Control is inactive
Definition: bdrv.h:240
@ BDRV_Curr_FR_120mA
typ. current ~120 mA
Definition: bdrv.h:285
@ BDRV_Curr_HR_120mA
typ. current ~120 mA
Definition: bdrv.h:264
@ BDRV_Curr_FR_270mA
typ. current ~270 mA
Definition: bdrv.h:300
@ BDRV_Curr_FR_110mA
typ. current ~110 mA
Definition: bdrv.h:284
@ BDRV_Curr_FR_30mA
typ. current ~30 mA
Definition: bdrv.h:276
@ BDRV_Curr_HR_130mA
typ. current ~130 mA
Definition: bdrv.h:266
@ BDRV_Curr_HR_125mA
typ. current ~125 mA
Definition: bdrv.h:265
@ BDRV_Curr_FR_210mA
typ. current ~210 mA
Definition: bdrv.h:294
@ BDRV_Curr_FR_20mA
typ. current ~20 mA
Definition: bdrv.h:275
@ BDRV_Curr_HR_155mA
typ. current ~155 mA
Definition: bdrv.h:271
@ BDRV_Curr_FR_90mA
typ. current ~90 mA
Definition: bdrv.h:282
@ BDRV_Curr_FR_140mA
typ. current ~140 mA
Definition: bdrv.h:287
@ BDRV_Curr_HR_85mA
typ. current ~85 mA
Definition: bdrv.h:257
@ BDRV_Curr_HR_80mA
typ. current ~80 mA
Definition: bdrv.h:256
@ BDRV_Curr_FR_100mA
typ. current ~100 mA
Definition: bdrv.h:283
@ BDRV_Curr_HR_50mA
typ. current ~50 mA
Definition: bdrv.h:250
@ BDRV_Curr_HR_55mA
typ. current ~55 mA
Definition: bdrv.h:251
@ BDRV_Curr_HR_140mA
typ. current ~140 mA
Definition: bdrv.h:268
@ BDRV_Curr_HR_40mA
typ. current ~40 mA
Definition: bdrv.h:248
@ BDRV_Curr_HR_105mA
typ. current ~105 mA
Definition: bdrv.h:261
@ BDRV_Curr_FR_310mA
typ. current ~310 mA
Definition: bdrv.h:304
@ BDRV_Curr_FR_60mA
typ. current ~60 mA
Definition: bdrv.h:279
@ BDRV_Curr_HR_45mA
typ. current ~45 mA
Definition: bdrv.h:249
@ BDRV_Curr_HR_65mA
typ. current ~65 mA
Definition: bdrv.h:253
@ BDRV_Curr_FR_170mA
typ. current ~170 mA
Definition: bdrv.h:290
@ BDRV_Curr_FR_290mA
typ. current ~290 mA
Definition: bdrv.h:302
@ BDRV_Curr_HR_10mA
typ. current ~10 mA
Definition: bdrv.h:242
@ BDRV_Curr_FR_220mA
typ. current ~220 mA
Definition: bdrv.h:295
@ BDRV_Curr_FR_260mA
typ. current ~260 mA
Definition: bdrv.h:299
@ BDRV_Curr_FR_80mA
typ. current ~80 mA
Definition: bdrv.h:281
@ BDRV_Curr_FR_Min
(min discharge current) lowest gate discharge current
Definition: bdrv.h:274
@ BDRV_Curr_HR_30mA
typ. current ~30 mA
Definition: bdrv.h:246
@ BDRV_Curr_HR_70mA
typ. current ~70 mA
Definition: bdrv.h:254
@ BDRV_Curr_FR_160mA
typ. current ~160 mA
Definition: bdrv.h:289
@ BDRV_Curr_HR_100mA
typ. current ~100 mA
Definition: bdrv.h:260
@ BDRV_Curr_HR_150mA
typ. current ~150 mA
Definition: bdrv.h:270
@ BDRV_Curr_HR_135mA
typ. current ~135 mA
Definition: bdrv.h:267
@ BDRV_Curr_HR_90mA
typ. current ~90 mA
Definition: bdrv.h:258
@ BDRV_Curr_FR_50mA
typ. current ~50 mA
Definition: bdrv.h:278
@ BDRV_Curr_HR_115mA
typ. current ~115 mA
Definition: bdrv.h:263
@ BDRV_Curr_HR_20mA
typ. current ~20 mA
Definition: bdrv.h:244
@ BDRV_Curr_FR_Disabled
(HiZ) Slew Rate Control is inactive
Definition: bdrv.h:273
@ BDRV_Curr_FR_130mA
typ. current ~130 mA
Definition: bdrv.h:286
@ BDRV_Curr_HR_15mA
typ. current ~15 mA
Definition: bdrv.h:243
@ BDRV_Curr_FR_40mA
typ. current ~40 mA
Definition: bdrv.h:277
@ BDRV_Curr_HR_110mA
typ. current ~110 mA
Definition: bdrv.h:262
@ BDRV_Curr_HR_Min
(min discharge current) lowest gate discharge current
Definition: bdrv.h:241
@ BDRV_Curr_FR_200mA
typ. current ~200 mA
Definition: bdrv.h:293
@ BDRV_Curr_HR_35mA
typ. current ~35 mA
Definition: bdrv.h:247
@ BDRV_Curr_HR_75mA
typ. current ~75 mA
Definition: bdrv.h:255
@ BDRV_Curr_FR_180mA
typ. current ~180 mA
Definition: bdrv.h:291
@ BDRV_Curr_HR_145mA
typ. current ~145 mA
Definition: bdrv.h:269
@ BDRV_Curr_FR_230mA
typ. current ~230 mA
Definition: bdrv.h:296
@ BDRV_Curr_FR_240mA
typ. current ~240 mA
Definition: bdrv.h:297
@ BDRV_Curr_FR_150mA
typ. current ~150 mA
Definition: bdrv.h:288
INLINE void BDRV_LS3_OC_Int_Clr(void)
clears External Low Side 3 FET Over-current interrupt flag.
Definition: bdrv.h:484
TBDRV_Curr BDRV_getChrgCurrent_mA(void)
Returns the BDRV charge current.
INLINE void BDRV_HS3_OC_Int_En(void)
enables External High Side 3 FET Over-current interrupt.
Definition: bdrv.h:846
INLINE void BDRV_setDischrgCurrentRange_dig(uint8 u8_cur_range_dig)
Sets the Discharge current range select (Digital value)
Definition: bdrv.h:1445
INLINE uint8 BDRV_getDischrgCurrent_dig(void)
Returns the Trimming of the internal driver dis-charge current (Digital value)
Definition: bdrv.h:1416
INLINE uint8 BDRV_HS1_OC_Int_Sts(void)
Reads the Bridge Driver High-Side 1 Over-Current Status Flag.
Definition: bdrv.h:1253
INLINE void BDRV_setDischrgCurrent_dig(uint8 u8_cur_dig)
Sets the Trimming of the internal driver dis-charge current (Digital value)
Definition: bdrv.h:1426
INLINE void BDRV_VCP_LO_Int_Dis(void)
disables Charge Pump Low interrupt.
Definition: bdrv.h:1244
Bdrv_Ch
Definition: bdrv.h:156
@ HS3
Phase3 High Side MOSFET.
Definition: bdrv.h:164
@ HS2
Phase2 High Side MOSFET.
Definition: bdrv.h:160
@ HS1
Phase1 High Side MOSFET.
Definition: bdrv.h:159
@ LS2
Phase2 Low Side MOSFET.
Definition: bdrv.h:158
@ LS1
Phase1 Low Side MOSFET.
Definition: bdrv.h:157
@ LS3
Phase3 Low Side MOSFET.
Definition: bdrv.h:163
void BDRV_setChrgCurrent_mA(TBDRV_Curr BDRV_Current)
Sets the BDRV charge current.
INLINE void BDRV_VCP_LO_Int_Clr(void)
clears Charge Pump Low interrupt flag.
Definition: bdrv.h:643
INLINE uint8 BDRV_HS2_OC_Int_Sts(void)
Reads the Bridge Driver High-Side 2 Over-Current Status Flag.
Definition: bdrv.h:1271
void BDRV_Set_Bridge(TBdrv_Ch_Cfg LS1_Cfg, TBdrv_Ch_Cfg HS1_Cfg, TBdrv_Ch_Cfg LS2_Cfg, TBdrv_Ch_Cfg HS2_Cfg, TBdrv_Ch_Cfg LS3_Cfg, TBdrv_Ch_Cfg HS3_Cfg)
Sets the bridge in the desired state. For each of the six drivers the state can be defined.
INLINE void BDRV_HS3_OC_Int_Dis(void)
disables External High Side 3 FET Over-current interrupt.
Definition: bdrv.h:871
INLINE void BDRV_HS2_OC_Int_Clr(void)
clears External High Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:415
TBDRV_Off_Diag BDRV_Off_Diagnosis(void)
Off-diagnosis.
INLINE uint8 BDRV_LS1_OC_Int_Sts(void)
Reads the Bridge Driver Low-Side 1 Over-Current Status Flag.
Definition: bdrv.h:1262
enum BDRV_Curr TBDRV_Curr
INLINE void BDRV_HS1_OC_Int_En(void)
enables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:665
INLINE void BDRV_LS1_DS_Int_Clr(void)
clears Low Side Driver 1 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:529
INLINE void BDRV_HS2_DS_Int_Clr(void)
clears High Side Driver 2 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:551
INLINE void BDRV_LS2_OC_Int_Dis(void)
disables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:823
void BDRV_Set_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Cfg Ch_Cfg)
sets an individual driver of the BridgeDriver in the desired state
TBDRV_Curr BDRV_getDischrgCurrent_mA(void)
Returns BDRV discharge current.
INLINE uint8 BDRV_LS3_DS_Int_Sts(void)
Reads the Bridge Driver Low-Side 3 Pre-Driver Short Status Flag.
Definition: bdrv.h:1359
INLINE void BDRV_HS1_DS_Int_En(void)
enables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:943
INLINE uint8 BDRV_HS1_DS_Int_Sts(void)
Reads the Bridge Driver High-Side 1 Pre-Driver Short Status Flag.
Definition: bdrv.h:1311
INLINE void BDRV_LS3_OC_Int_En(void)
enables External Low Side 3 FET Over-current interrupt.
Definition: bdrv.h:895
INLINE uint8 BDRV_getChrgCurrent_dig(void)
Returns the Trimming of the internal driver charge current (Digital value)
Definition: bdrv.h:1378
INLINE void BDRV_LS1_OC_Int_Clr(void)
clears External Low Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:393
INLINE void BDRV_LS2_OC_Int_En(void)
enables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:800
void BDRV_setDischrgCurrent_mA(TBDRV_Curr BDRV_Current)
Sets the BDRV discharge current.
INLINE void BDRV_LS2_DS_Int_Dis(void)
disables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1101
INLINE void BDRV_LS1_DS_Int_En(void)
enables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:988
INLINE void BDRV_HS2_OC_Int_En(void)
enables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:755
INLINE void BDRV_HS3_DS_Int_Dis(void)
disables High Side Driver 3 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1149
INLINE uint8 BDRV_getChrgCurrentRange_dig(void)
Returns the Charge current range select (Digital value)
Definition: bdrv.h:1397
INLINE void BDRV_LS2_DS_Int_En(void)
enables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1078
INLINE void BDRV_LS3_DS_Int_Clr(void)
clears Low Side Driver 3 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:620
enum Bdrv_DSM_Threshold TBdrv_DSM_Threshold
INLINE uint8 BDRV_LS3_OC_Int_Sts(void)
Reads the Bridge Driver Low-Side 3 Over-Current Status Flag.
Definition: bdrv.h:1301
INLINE void BDRV_setChrgCurrentRange_dig(uint8 u8_cur_range_dig)
Sets the Charge current range select (Digital value)
Definition: bdrv.h:1407
INLINE uint8 BDRV_LS1_DS_Int_Sts(void)
Reads the Bridge Driver Low-Side 1 Pre-Driver Short Status Flag.
Definition: bdrv.h:1320
void BDRV_Set_DSM_Threshold(TBdrv_DSM_Threshold BDRV_Threshold)
Sets the Voltage Threshold for Drain-Source Monitoring of external FETs.
INLINE void BDRV_VCP_LO_Int_En(void)
enables Charge Pump Low interrupt.
Definition: bdrv.h:1221
Bdrv_DSM_Threshold
Definition: bdrv.h:222
@ Threshold_0_75_V
Threshold 2 for VDS at 0.75 V.
Definition: bdrv.h:225
@ Threshold_0_50_V
Threshold 1 for VDS at 0.50 V.
Definition: bdrv.h:224
@ Threshold_1_75_V
Threshold 6 for VDS at 1.75 V.
Definition: bdrv.h:229
@ Threshold_1_00_V
Threshold 3 for VDS at 1.00 V.
Definition: bdrv.h:226
@ Threshold_1_50_V
Threshold 5 for VDS at 1.50 V.
Definition: bdrv.h:228
@ Threshold_1_25_V
Threshold 4 for VDS at 1.25 V.
Definition: bdrv.h:227
@ Threshold_2_00_V
Threshold 7 for VDS at 2.00 V.
Definition: bdrv.h:230
@ Threshold_0_25_V
Threshold 0 for VDS at 0.25 V.
Definition: bdrv.h:223
INLINE void BDRV_HS1_OC_Int_Dis(void)
disables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:688
INLINE void BDRV_ChargePump_Dis(void)
disables the Charge Pump.
Definition: bdrv.h:349
INLINE void BDRV_HS1_OC_Int_Clr(void)
clears External High Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:371
BDRV_Off_Diag_Sts
Definition: bdrv.h:188
@ Ch_Ok
Definition: bdrv.h:189
@ Ch_Short_to_Gnd
Definition: bdrv.h:190
@ Ch_Short_to_VBat
Definition: bdrv.h:191
void BDRV_Init(void)
Initializes the BDRV module based on the Config Wizard for MOTIX MCU configuration.
INLINE void BDRV_HS1_DS_Int_Clr(void)
enables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:507
INLINE void BDRV_LS3_DS_Int_Dis(void)
disables Low Side Driver 3 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1198
INLINE void BDRV_LS3_DS_Int_En(void)
enables Low Side Driver 3 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1173
enum Bdrv_Ch TBdrv_Ch
Bdrv_Ch_Cfg
Definition: bdrv.h:144
@ Ch_On
channel enabled and static on
Definition: bdrv.h:148
@ Ch_DCS
channel enabled with Diag.-Current Source
Definition: bdrv.h:149
@ Ch_Off
channel disabled
Definition: bdrv.h:145
@ Ch_En
channel enabled
Definition: bdrv.h:146
@ Ch_PWM
channel enabled with PWM (CCU6 connection)
Definition: bdrv.h:147
enum BDRV_Off_Diag_Sts TBDRV_Off_Diag_Sts
INLINE void BDRV_LS3_OC_Int_Dis(void)
disables External Low Side 3 FET Over-current interrupt.
Definition: bdrv.h:920
INLINE void BDRV_HS1_DS_Int_Dis(void)
disables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:966
INLINE void BDRV_HS2_DS_Int_Dis(void)
disables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1056
#define SCUPM
Definition: tle987x.h:6098
#define BDRV
Definition: tle987x.h:6086
#define SCUPM_BDRV_IS_HS2_DS_IS_Pos
Definition: tle987x.h:9504
#define SCUPM_BDRV_IS_HS2_OC_IS_Msk
Definition: tle987x.h:9493
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk
Definition: tle987x.h:9454
#define SCUPM_BDRV_IS_LS2_OC_IS_Msk
Definition: tle987x.h:9497
#define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Pos
Definition: tle987x.h:9535
#define BDRV_CP_CTRL_STS_CP_EN_Msk
Definition: tle987x.h:6861
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk
Definition: tle987x.h:9550
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk
Definition: tle987x.h:9554
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos
Definition: tle987x.h:9541
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk
Definition: tle987x.h:9460
#define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos
Definition: tle987x.h:9443
#define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos
Definition: tle987x.h:9455
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk
Definition: tle987x.h:9464
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk
Definition: tle987x.h:9450
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos
Definition: tle987x.h:9549
#define SCUPM_BDRV_IS_HS2_DS_IS_Msk
Definition: tle987x.h:9505
#define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk
Definition: tle987x.h:9546
#define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk
Definition: tle987x.h:9534
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk
Definition: tle987x.h:9552
#define SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk
Definition: tle987x.h:9456
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk
Definition: tle987x.h:9538
#define SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Pos
Definition: tle987x.h:9545
#define SCUPM_BDRV_IS_LS1_OC_IS_Msk
Definition: tle987x.h:9499
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos
Definition: tle987x.h:9531
#define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk
Definition: tle987x.h:9548
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos
Definition: tle987x.h:9447
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos
Definition: tle987x.h:9543
#define SCUPM_BDRV_IS_HS1_DS_IS_Pos
Definition: tle987x.h:9506
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos
Definition: tle987x.h:9551
#define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos
Definition: tle987x.h:9445
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk
Definition: tle987x.h:9442
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos
Definition: tle987x.h:9553
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk
Definition: tle987x.h:9487
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk
Definition: tle987x.h:9448
#define SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk
Definition: tle987x.h:9446
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk
Definition: tle987x.h:9540
#define SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk
Definition: tle987x.h:9444
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos
Definition: tle987x.h:9537
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos
Definition: tle987x.h:9459
#define SCUPM_BDRV_IS_LS3_DS_IS_Pos
Definition: tle987x.h:9502
#define SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Pos
Definition: tle987x.h:9533
#define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk
Definition: tle987x.h:9458
#define SCUPM_BDRV_IS_LS2_DS_IS_Pos
Definition: tle987x.h:9508
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk
Definition: tle987x.h:9452
#define SCUPM_BDRV_IS_HS3_OC_IS_Msk
Definition: tle987x.h:9489
#define SCUPM_BDRV_IS_HS1_DS_IS_Msk
Definition: tle987x.h:9507
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos
Definition: tle987x.h:9555
#define SCUPM_BDRV_IS_LS1_OC_IS_Pos
Definition: tle987x.h:9498
#define SCUPM_BDRV_IS_HS2_OC_IS_Pos
Definition: tle987x.h:9492
#define SCUPM_BDRV_IS_HS1_OC_IS_Pos
Definition: tle987x.h:9494
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk
Definition: tle987x.h:9532
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos
Definition: tle987x.h:9486
#define SCUPM_BDRV_IS_LS3_OC_IS_Pos
Definition: tle987x.h:9490
#define SCUPM_BDRV_IS_LS3_OC_IS_Msk
Definition: tle987x.h:9491
#define SCUPM_BDRV_IS_HS3_OC_IS_Pos
Definition: tle987x.h:9488
#define SCUPM_BDRV_IS_LS1_DS_IS_Msk
Definition: tle987x.h:9511
#define SCUPM_BDRV_IS_LS3_DS_IS_Msk
Definition: tle987x.h:9503
#define SCUPM_BDRV_IS_LS2_OC_IS_Pos
Definition: tle987x.h:9496
#define SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk
Definition: tle987x.h:9536
#define SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos
Definition: tle987x.h:9457
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos
Definition: tle987x.h:9461
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos
Definition: tle987x.h:9465
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos
Definition: tle987x.h:9539
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos
Definition: tle987x.h:9453
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk
Definition: tle987x.h:9462
#define SCUPM_BDRV_IS_HS1_OC_IS_Msk
Definition: tle987x.h:9495
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk
Definition: tle987x.h:9556
#define SCUPM_BDRV_IS_HS3_DS_IS_Pos
Definition: tle987x.h:9500
#define SCUPM_BDRV_IS_HS3_DS_IS_Msk
Definition: tle987x.h:9501
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos
Definition: tle987x.h:9463
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos
Definition: tle987x.h:9449
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk
Definition: tle987x.h:9544
#define SCUPM_BDRV_IS_LS1_DS_IS_Pos
Definition: tle987x.h:9510
#define SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Pos
Definition: tle987x.h:9547
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos
Definition: tle987x.h:9441
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk
Definition: tle987x.h:9542
#define SCUPM_BDRV_IS_LS2_DS_IS_Msk
Definition: tle987x.h:9509
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk
Definition: tle987x.h:9466
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos
Definition: tle987x.h:9451
#define BDRV_CP_CTRL_STS_CP_EN_Pos
Definition: tle987x.h:6860
Interrupt low level access library.
System Control Unit low level access library.
SFR low level access library.
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:362
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:407
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:347
This struct lists the Bridge Driver Off Diagnosis Status Phases configuration.
Definition: bdrv.h:198
TBDRV_Off_Diag_Sts Phase3
Definition: bdrv.h:203
TBDRV_Off_Diag_Sts Phase1
Definition: bdrv.h:200
bool GlobFailSts
Definition: bdrv.h:199
TBDRV_Off_Diag_Sts Phase2
Definition: bdrv.h:201
Device specific memory layout defines.
#define INLINE
Definition: types.h:148
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint32_t uint32
32 bit unsigned value
Definition: types.h:155
Window Watchdog 1 low level access library.