Infineon MOTIX™ MCU TLE987x Device Family SDK
Data Fields
SCUPM_Type Struct Reference

Detailed Description

System Control Unit for Power Modules (SCUPM)

#include <tle987x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   AMCLK1_FREQ: 6
 
      __IM   uint32_t: 2
 
      __IM uint32_t   AMCLK2_FREQ: 6
 
   }   bit
 
AMCLK_FREQ_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CLKWDT_PD_N: 1
 
   }   bit
 
AMCLK_CTRL
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   AMCLK1_UP_TH: 6
 
      __IOM uint32_t   AMCLK1_UP_HYS: 2
 
      __IOM uint32_t   AMCLK1_LOW_TH: 6
 
      __IOM uint32_t   AMCLK1_LOW_HYS: 2
 
      __IOM uint32_t   AMCLK2_UP_TH: 6
 
      __IOM uint32_t   AMCLK2_UP_HYS: 2
 
      __IOM uint32_t   AMCLK2_LOW_TH: 6
 
      __IOM uint32_t   AMCLK2_LOW_HYS: 2
 
   }   bit
 
AMCLK_TH_HYS
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LIN_OC_ICLR: 1
 
      __OM uint32_t   LIN_OT_ICLR: 1
 
      __OM uint32_t   LIN_TMOUT_ICLR: 1
 
      __IM   uint32_t: 3
 
      __OM uint32_t   PMU_OTWARN_ICLR: 1
 
      __OM uint32_t   PMU_OT_ICLR: 1
 
      __OM uint32_t   SYS_OTWARN_ICLR: 1
 
      __OM uint32_t   SYS_OT_ICLR: 1
 
      __OM uint32_t   REFBG_LOTHWARN_ICLR: 1
 
      __OM uint32_t   REFBG_UPTHWARN_ICLR: 1
 
      __OM uint32_t   VREF5V_LOWTH_ICLR: 1
 
      __OM uint32_t   VREF5V_UPTH_ICLR: 1
 
      __OM uint32_t   VREF5V_OVL_ICLR: 1
 
      __OM uint32_t   ADC2_ESM_ICLR: 1
 
      __OM uint32_t   PHU_ZCLOW_ICLR: 1
 
      __OM uint32_t   PHU_ZCHI_ICLR: 1
 
      __OM uint32_t   PHV_ZCLOW_ICLR: 1
 
      __OM uint32_t   PHV_ZCHI_ICLR: 1
 
      __OM uint32_t   PHW_ZCLOW_ICLR: 1
 
      __OM uint32_t   PHW_ZCHI_ICLR: 1
 
      __OM uint32_t   ADC3_EOC_ICLR: 1
 
      __OM uint32_t   ADC4_EOC_ICLR: 1
 
      __OM uint32_t   PHU_ZCLOW_SCLR: 1
 
      __OM uint32_t   PHU_ZCHI_SCLR: 1
 
      __OM uint32_t   PHV_ZCLOW_SCLR: 1
 
      __OM uint32_t   PHV_ZCHI_SCLR: 1
 
      __OM uint32_t   PHW_ZCLOW_SCLR: 1
 
      __OM uint32_t   PHW_ZCHI_SCLR: 1
 
   }   bit
 
SYS_ISCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   LIN_OC_IS: 1
 
      __IM uint32_t   LIN_OT_IS: 1
 
      __IM uint32_t   LIN_TMOUT_IS: 1
 
      __IM   uint32_t: 3
 
      __IM uint32_t   PMU_OTWARN_IS: 1
 
      __IM uint32_t   PMU_OT_IS: 1
 
      __IM uint32_t   SYS_OTWARN_IS: 1
 
      __IM uint32_t   SYS_OT_IS: 1
 
      __IM uint32_t   REFBG_LOTHWARN_IS: 1
 
      __IM uint32_t   REFBG_UPTHWARN_IS: 1
 
      __IM uint32_t   VREF5V_LOWTH_IS: 1
 
      __IM uint32_t   VREF5V_UPTH_IS: 1
 
      __IM uint32_t   VREF5V_OVL_IS: 1
 
      __IM uint32_t   ADC2_ESM_IS: 1
 
      __IM uint32_t   PHU_ZCLOW_IS: 1
 
      __IM uint32_t   PHU_ZCHI_IS: 1
 
      __IM uint32_t   PHV_ZCLOW_IS: 1
 
      __IM uint32_t   PHV_ZCHI_IS: 1
 
      __IM uint32_t   PHW_ZCLOW_IS: 1
 
      __IM uint32_t   PHW_ZCHI_IS: 1
 
      __IM uint32_t   ADC3_EOC_IS: 1
 
      __IM uint32_t   ADC4_EOC_IS: 1
 
      __IM uint32_t   PHU_ZCLOW_STS: 1
 
      __IM uint32_t   PHU_ZCHI_STS: 1
 
      __IM uint32_t   PHV_ZCLOW_STS: 1
 
      __IM uint32_t   PHV_ZCHI_STS: 1
 
      __IM uint32_t   PHW_ZCLOW_STS: 1
 
      __IM uint32_t   PHW_ZCHI_STS: 1
 
   }   bit
 
SYS_IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   MON_UV_IS: 1
 
      __IM uint32_t   VS_UV_IS: 1
 
      __IM uint32_t   VDD5V_UV_IS: 1
 
      __IM uint32_t   VDD1V5_UV_IS: 1
 
      __IM uint32_t   MON_OV_IS: 1
 
      __IM uint32_t   VS_OV_IS: 1
 
      __IM uint32_t   VDD5V_OV_IS: 1
 
      __IM uint32_t   VDD1V5_OV_IS: 1
 
      __IM   uint32_t: 8
 
      __IM uint32_t   MON_UV_STS: 1
 
      __IM uint32_t   VS_UV_STS: 1
 
      __IM uint32_t   VDD5V_UV_STS: 1
 
      __IM uint32_t   VDD1V5_UV_STS: 1
 
      __IM uint32_t   MON_OV_STS: 1
 
      __IM uint32_t   VS_OV_STS: 1
 
      __IM uint32_t   VDD5V_OV_STS: 1
 
      __IM uint32_t   VDD1V5_OV_STS: 1
 
   }   bit
 
SYS_SUPPLY_IRQ_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MON_UV_IE: 1
 
      __IOM uint32_t   VS_UV_IE: 1
 
      __IOM uint32_t   VDD5V_UV_IE: 1
 
      __IOM uint32_t   VDD1V5_UV_IE: 1
 
      __IOM uint32_t   MON_OV_IE: 1
 
      __IOM uint32_t   VS_OV_IE: 1
 
      __IOM uint32_t   VDD5V_OV_IE: 1
 
      __IOM uint32_t   VDD1V5_OV_IE: 1
 
   }   bit
 
SYS_SUPPLY_IRQ_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   MON_UV_ICLR: 1
 
      __OM uint32_t   VS_UV_ICLR: 1
 
      __OM uint32_t   VDD5V_UV_ICLR: 1
 
      __OM uint32_t   VDD1V5_UV_ICLR: 1
 
      __OM uint32_t   MON_OV_ICLR: 1
 
      __OM uint32_t   VS_OV_ICLR: 1
 
      __OM uint32_t   VDD5V_OV_ICLR: 1
 
      __OM uint32_t   VDD1V5_OV_ICLR: 1
 
      __IM   uint32_t: 8
 
      __OM uint32_t   MON_UV_SCLR: 1
 
      __OM uint32_t   VS_UV_SCLR: 1
 
      __OM uint32_t   VDD5V_UV_SCLR: 1
 
      __OM uint32_t   VDD1V5_UV_SCLR: 1
 
      __OM uint32_t   MON_OV_SCLR: 1
 
      __OM uint32_t   VS_OV_SCLR: 1
 
      __OM uint32_t   VDD5V_OV_SCLR: 1
 
      __OM uint32_t   VDD1V5_OV_SCLR: 1
 
   }   bit
 
SYS_SUPPLY_IRQ_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LIN_OC_IE: 1
 
      __IOM uint32_t   LIN_OT_IE: 1
 
      __IOM uint32_t   LIN_TMOUT_IE: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   PMU_OTWARN_IE: 1
 
      __IOM uint32_t   PMU_OT_IE: 1
 
      __IOM uint32_t   SYS_OTWARN_IE: 1
 
      __IOM uint32_t   SYS_OT_IE: 1
 
      __IOM uint32_t   REFBG_LOTHWARN_IE: 1
 
      __IOM uint32_t   REFBG_UPTHWARN_IE: 1
 
      __IOM uint32_t   VREF5V_LOWTH_IE: 1
 
      __IOM uint32_t   VREF5V_UPTH_IE: 1
 
      __IOM uint32_t   VREF5V_OVL_IE: 1
 
      __IOM uint32_t   ADC2_ESM_IE: 1
 
      __IOM uint32_t   PHU_ZCLOW_IE: 1
 
      __IOM uint32_t   PHU_ZCHI_IE: 1
 
      __IOM uint32_t   PHV_ZCLOW_IE: 1
 
      __IOM uint32_t   PHV_ZCHI_IE: 1
 
      __IOM uint32_t   PHW_ZCLOW_IE: 1
 
      __IOM uint32_t   PHW_ZCHI_IE: 1
 
      __IOM uint32_t   ADC3_EOC_IE: 1
 
      __IOM uint32_t   ADC4_EOC_IE: 1
 
   }   bit
 
SYS_IRQ_CTRL
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IOM uint32_t   CLKWDT_SD_DIS: 1
 
      __IOM uint32_t   FAIL_PS_DIS: 1
 
      __IOM uint32_t   LIN_VS_UV_SD_DIS: 1
 
      __IOM uint32_t   SYS_VSD_OV_SLM_DIS: 1
 
      __IOM uint32_t   SYS_OT_PS_DIS: 1
 
      __IOM uint32_t   CLKLOSS_SD_DIS: 1
 
      __IOM uint32_t   CLKWDT_RES_SD_DIS: 1
 
   }   bit
 
PCU_CTRL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDP_SEL: 6
 
      __IOM uint32_t   SOWCONF: 2
 
   }   bit
 
WDT1_TRIG
 
__IM uint32_t RESERVED3 [7]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   LS1_DS_ICLR: 1
 
      __OM uint32_t   LS2_DS_ICLR: 1
 
      __OM uint32_t   HS1_DS_ICLR: 1
 
      __OM uint32_t   HS2_DS_ICLR: 1
 
      __OM uint32_t   LS3_DS_ICLR: 1
 
      __OM uint32_t   HS3_DS_ICLR: 1
 
      __IM   uint32_t: 4
 
      __OM uint32_t   LS1_OC_ICLR: 1
 
      __OM uint32_t   LS2_OC_ICLR: 1
 
      __OM uint32_t   HS1_OC_ICLR: 1
 
      __OM uint32_t   HS2_OC_ICLR: 1
 
      __OM uint32_t   LS3_OC_ICLR: 1
 
      __OM uint32_t   HS3_OC_ICLR: 1
 
      __OM uint32_t   VCP_LOWTH2_ICLR: 1
 
      __OM uint32_t   VCP_LOWTH1_ICLR: 1
 
      __OM uint32_t   VCP_UPTH_ICLR: 1
 
      __OM uint32_t   VSD_LOWTH_ICLR: 1
 
      __OM uint32_t   VSD_UPTH_ICLR: 1
 
      __OM uint32_t   VCP_LOWTH2_SCLR: 1
 
      __OM uint32_t   VCP_LOWTH1_SCLR: 1
 
      __OM uint32_t   VCP_UPTH_SCLR: 1
 
      __OM uint32_t   VSD_LOWTH_SCLR: 1
 
      __OM uint32_t   VSD_UPTH_SCLR: 1
 
   }   bit
 
BDRV_ISCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   LS1_DS_IS: 1
 
      __IM uint32_t   LS2_DS_IS: 1
 
      __IM uint32_t   HS1_DS_IS: 1
 
      __IM uint32_t   HS2_DS_IS: 1
 
      __IM uint32_t   LS3_DS_IS: 1
 
      __IM uint32_t   HS3_DS_IS: 1
 
      __IM   uint32_t: 4
 
      __IM uint32_t   LS1_OC_IS: 1
 
      __IM uint32_t   LS2_OC_IS: 1
 
      __IM uint32_t   HS1_OC_IS: 1
 
      __IM uint32_t   HS2_OC_IS: 1
 
      __IM uint32_t   LS3_OC_IS: 1
 
      __IM uint32_t   HS3_OC_IS: 1
 
      __IM uint32_t   VCP_LOWTH2_IS: 1
 
      __IM uint32_t   VCP_LOWTH1_IS: 1
 
      __IM uint32_t   VCP_UPTH_IS: 1
 
      __IM uint32_t   VSD_LOWTH_IS: 1
 
      __IM uint32_t   VSD_UPTH_IS: 1
 
      __IM uint32_t   VCP_LOWTH2_STS: 1
 
      __IM uint32_t   VCP_LOWTH1_STS: 1
 
      __IM uint32_t   VCP_UPTH_STS: 1
 
      __IM uint32_t   VSD_LOWTH_STS: 1
 
      __IM uint32_t   VSD_UPTH_STS: 1
 
   }   bit
 
BDRV_IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_DS_IE: 1
 
      __IOM uint32_t   LS2_DS_IE: 1
 
      __IOM uint32_t   HS1_DS_IE: 1
 
      __IOM uint32_t   HS2_DS_IE: 1
 
      __IOM uint32_t   LS3_DS_IE: 1
 
      __IOM uint32_t   HS3_DS_IE: 1
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   LS1_OC_IE: 1
 
      __IOM uint32_t   LS2_OC_IE: 1
 
      __IOM uint32_t   HS1_OC_IE: 1
 
      __IOM uint32_t   HS2_OC_IE: 1
 
      __IOM uint32_t   LS3_OC_IE: 1
 
      __IOM uint32_t   HS3_OC_IE: 1
 
      __IOM uint32_t   VCP_LOWTH2_IE: 1
 
      __IOM uint32_t   VCP_LOWTH1_IE: 1
 
      __IOM uint32_t   VCP_UPTH_IE: 1
 
      __IOM uint32_t   VSD_LOWTH_IE: 1
 
      __IOM uint32_t   VSD_UPTH_IE: 1
 
   }   bit
 
BDRV_IRQ_CTRL
 
__IM uint32_t RESERVED4 [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STCALIB: 26
 
   }   bit
 
STCALIB
 
__IM uint32_t RESERVED5 [4]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFSTS: 1
 
      __IM uint32_t   SBFSTS: 1
 
   }   bit
 
BFSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   DBFA: 32
 
   }   bit
 
DBFA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   SBFA: 32
 
   }   bit
 
SBFA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DBFSTSCLR: 1
 
      __OM uint32_t   SBFSTSCLR: 1
 
   }   bit
 
BFSTS_CLR
 

Field Documentation

◆ ADC2_ESM_ICLR

__OM uint32_t ADC2_ESM_ICLR

[15..15] ADC2 Exceptional Sequence Measurement Interrupt Status

◆ ADC2_ESM_IE

__IOM uint32_t ADC2_ESM_IE

[15..15] ADC2 Exceptional Sequence Measurement Interrupt Enable

◆ ADC2_ESM_IS

__IM uint32_t ADC2_ESM_IS

[15..15] ADC2 Exceptional Sequence Measurement Interrupt Status

◆ ADC3_EOC_ICLR

__OM uint32_t ADC3_EOC_ICLR

[22..22] ADC3 EOC Interrupt Status

◆ ADC3_EOC_IE

__IOM uint32_t ADC3_EOC_IE

[22..22] ADC3 EOC Interrupt Enable

◆ ADC3_EOC_IS

__IM uint32_t ADC3_EOC_IS

[22..22] ADC3 EOC Interrupt Status

◆ ADC4_EOC_ICLR

__OM uint32_t ADC4_EOC_ICLR

[23..23] ADC4 EOC Interrupt Status

◆ ADC4_EOC_IE

__IOM uint32_t ADC4_EOC_IE

[23..23] ADC4 EOC Interrupt Enable

◆ ADC4_EOC_IS

__IM uint32_t ADC4_EOC_IS

[23..23] ADC4 EOC Interrupt Status

◆ AMCLK1_FREQ

__IM uint32_t AMCLK1_FREQ

[5..0] Current frequency of Analog Module Clock System Clock (MI_CLK)

◆ AMCLK1_LOW_HYS

__IOM uint32_t AMCLK1_LOW_HYS

[15..14] Analog Module Clock 1 (MI_CLK) Lower Hysteresis

◆ AMCLK1_LOW_TH

__IOM uint32_t AMCLK1_LOW_TH

[13..8] Analog Module Clock 1 (MI_CLK) Lower Limit Threshold

◆ AMCLK1_UP_HYS

__IOM uint32_t AMCLK1_UP_HYS

[7..6] Analog Module Clock 1 (MI_CLK) Upper Hysteresis

◆ AMCLK1_UP_TH

__IOM uint32_t AMCLK1_UP_TH

[5..0] Analog Module Clock 1 (MI_CLK) Upper Limit Threshold

◆ AMCLK2_FREQ

__IM uint32_t AMCLK2_FREQ

[13..8] Current frequency of Analog Module Clock 2 (TFILT_CLK)

◆ AMCLK2_LOW_HYS

__IOM uint32_t AMCLK2_LOW_HYS

[31..30] Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis

◆ AMCLK2_LOW_TH

__IOM uint32_t AMCLK2_LOW_TH

[29..24] Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold

◆ AMCLK2_UP_HYS

__IOM uint32_t AMCLK2_UP_HYS

[23..22] Analog Module Clock 2 (TFILT_CLK) Upper Hysteresis

◆ AMCLK2_UP_TH

__IOM uint32_t AMCLK2_UP_TH

[21..16] Analog Module Clock 2 (TFILT_CLK) Upper Limit Threshold

◆ 

union { ... } AMCLK_CTRL

◆ 

union { ... } AMCLK_FREQ_STS

◆ 

union { ... } AMCLK_TH_HYS

◆ 

union { ... } BDRV_IRQ_CTRL

◆ 

union { ... } BDRV_IS

◆ 

union { ... } BDRV_ISCLR

◆ 

union { ... } BFSTS

◆ 

union { ... } BFSTS_CLR

◆  [1/19]

struct { ... } bit

◆  [2/19]

struct { ... } bit

◆  [3/19]

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◆  [4/19]

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◆  [5/19]

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◆  [6/19]

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◆  [7/19]

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◆  [8/19]

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◆  [9/19]

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◆  [10/19]

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◆  [11/19]

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◆  [12/19]

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◆  [13/19]

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◆  [14/19]

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◆  [15/19]

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◆  [16/19]

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◆  [17/19]

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◆  [18/19]

struct { ... } bit

◆  [19/19]

struct { ... } bit

◆ CLKLOSS_SD_DIS

__IOM uint32_t CLKLOSS_SD_DIS

[25..25] Power Switches Loss of Clock Shutdown Disable (AMCLK3)

◆ CLKWDT_PD_N

__IOM uint32_t CLKWDT_PD_N

[0..0] Clock Watchdog Powerdown

◆ CLKWDT_RES_SD_DIS

__IOM uint32_t CLKWDT_RES_SD_DIS

[26..26] Clock Watchdog Reset Disable

◆ CLKWDT_SD_DIS

__IOM uint32_t CLKWDT_SD_DIS

[1..1] Power Modules Clock Watchdog Shutdown Disable

◆ DBFA [1/2]

__IM uint32_t DBFA

[31..0] Data Bus Fault Address Register

◆  [2/2]

union { ... } DBFA

◆ DBFSTS

__IM uint32_t DBFSTS

[0..0] Data Bus Fault Status Valid Flag

◆ DBFSTSCLR

__OM uint32_t DBFSTSCLR

[0..0] Data Bus Fault Status Clear Flag

◆ FAIL_PS_DIS

__IOM uint32_t FAIL_PS_DIS

[7..7] Disable LIN, BDRV and CP because of Overtemperature

◆ HS1_DS_ICLR

__OM uint32_t HS1_DS_ICLR

[2..2] Bridge Driver High Side 1 Pre-Driver short Interrupt Status

◆ HS1_DS_IE

__IOM uint32_t HS1_DS_IE

[2..2] Bridge Driver High Side 1 Pre-Driver Short Interrupt Enable

◆ HS1_DS_IS

__IM uint32_t HS1_DS_IS

[2..2] Bridge Driver High Side 1 Pre-Driver short Interrupt Status

◆ HS1_OC_ICLR

__OM uint32_t HS1_OC_ICLR

[12..12] External High 1 FET Over-current Status

◆ HS1_OC_IE

__IOM uint32_t HS1_OC_IE

[12..12] External High Side 1 FET Over-current Interrupt Enable

◆ HS1_OC_IS

__IM uint32_t HS1_OC_IS

[12..12] External High 1 FET Over-current Status

◆ HS2_DS_ICLR

__OM uint32_t HS2_DS_ICLR

[3..3] Bridge Driver High Side 2 Pre-Driver short Interrupt Status

◆ HS2_DS_IE

__IOM uint32_t HS2_DS_IE

[3..3] Bridge Driver High Side 2 Pre-Driver Short Interrupt Enable

◆ HS2_DS_IS

__IM uint32_t HS2_DS_IS

[3..3] Bridge Driver High Side 2 Pre-Driver short Interrupt Status

◆ HS2_OC_ICLR

__OM uint32_t HS2_OC_ICLR

[13..13] External High Side 2 FET Over-current Status

◆ HS2_OC_IE

__IOM uint32_t HS2_OC_IE

[13..13] External High Side 2 FET Over-current Interrupt Enable

◆ HS2_OC_IS

__IM uint32_t HS2_OC_IS

[13..13] External High Side 2 FET Over-current Status

◆ HS3_DS_ICLR

__OM uint32_t HS3_DS_ICLR

[5..5] Bridge Driver High Side 3 Pre-Driver short Interrupt Status

◆ HS3_DS_IE

__IOM uint32_t HS3_DS_IE

[5..5] Bridge Driver High Side 3 Pre-Driver Short Interrupt Enable

◆ HS3_DS_IS

__IM uint32_t HS3_DS_IS

[5..5] Bridge Driver High Side 3 Pre-Driver short Interrupt Status

◆ HS3_OC_ICLR

__OM uint32_t HS3_OC_ICLR

[15..15] External High Side 3 FET Over-current Status

◆ HS3_OC_IE

__IOM uint32_t HS3_OC_IE

[15..15] External High Side 3 FET Over-current Interrupt Enable

◆ HS3_OC_IS

__IM uint32_t HS3_OC_IS

[15..15] External High Side 3 FET Over-current Status

◆ LIN_OC_ICLR

__OM uint32_t LIN_OC_ICLR

[0..0] LIN Overcurrent interrupt status

◆ LIN_OC_IE

__IOM uint32_t LIN_OC_IE

[0..0] LIN Overcurrent Interrupt Enable

◆ LIN_OC_IS

__IM uint32_t LIN_OC_IS

[0..0] LIN Overcurrent interrupt status

◆ LIN_OT_ICLR

__OM uint32_t LIN_OT_ICLR

[1..1] LIN Overtemperature interrupt status

◆ LIN_OT_IE

__IOM uint32_t LIN_OT_IE

[1..1] LIN Overtemperature Interrupt Enable

◆ LIN_OT_IS

__IM uint32_t LIN_OT_IS

[1..1] LIN Overtemperature interrupt status

◆ LIN_TMOUT_ICLR

__OM uint32_t LIN_TMOUT_ICLR

[2..2] LIN TXD timeout

◆ LIN_TMOUT_IE

__IOM uint32_t LIN_TMOUT_IE

[2..2] LIN TXD timeout Interrupt Enable

◆ LIN_TMOUT_IS

__IM uint32_t LIN_TMOUT_IS

[2..2] LIN TXD timeout

◆ LIN_VS_UV_SD_DIS

__IOM uint32_t LIN_VS_UV_SD_DIS

[8..8] LIN Module VS Undervoltage Transmitter Shutdown

◆ LS1_DS_ICLR

__OM uint32_t LS1_DS_ICLR

[0..0] Bridge Driver Low Side 1 Pre-Driver short Interrupt Status

◆ LS1_DS_IE

__IOM uint32_t LS1_DS_IE

[0..0] Bridge Driver Low Side 1 Pre-Driver Short Interrupt Enable

◆ LS1_DS_IS

__IM uint32_t LS1_DS_IS

[0..0] Bridge Driver Low Side 1 Pre-Driver short Interrupt Status

◆ LS1_OC_ICLR

__OM uint32_t LS1_OC_ICLR

[10..10] External Low Side 1 FET Over-current Status

◆ LS1_OC_IE

__IOM uint32_t LS1_OC_IE

[10..10] External Low Side 1 FET Over-current Interrupt Enable

◆ LS1_OC_IS

__IM uint32_t LS1_OC_IS

[10..10] External Low Side 1 FET Over-current Status

◆ LS2_DS_ICLR

__OM uint32_t LS2_DS_ICLR

[1..1] Bridge Driver Low Side 2 Pre-Driver short Interrupt Status

◆ LS2_DS_IE

__IOM uint32_t LS2_DS_IE

[1..1] Bridge Driver Low Side 2 Pre-Driver Short Interrupt Enable

◆ LS2_DS_IS

__IM uint32_t LS2_DS_IS

[1..1] Bridge Driver Low Side 2 Pre-Driver short Interrupt Status

◆ LS2_OC_ICLR

__OM uint32_t LS2_OC_ICLR

[11..11] External Low Side 2 FET Over-current Status

◆ LS2_OC_IE

__IOM uint32_t LS2_OC_IE

[11..11] External Low Side 2 FET Over-current Interrupt Enable

◆ LS2_OC_IS

__IM uint32_t LS2_OC_IS

[11..11] External Low Side 2 FET Over-current Status

◆ LS3_DS_ICLR

__OM uint32_t LS3_DS_ICLR

[4..4] Bridge Driver Low Side 3 Pre-Driver short Interrupt Status

◆ LS3_DS_IE

__IOM uint32_t LS3_DS_IE

[4..4] Bridge Driver Low Side 3 Pre-Driver Short Interrupt Enable

◆ LS3_DS_IS

__IM uint32_t LS3_DS_IS

[4..4] Bridge Driver Low Side 3 Pre-Driver short Interrupt Status

◆ LS3_OC_ICLR

__OM uint32_t LS3_OC_ICLR

[14..14] External Low Side 3 FET Over-current Status

◆ LS3_OC_IE

__IOM uint32_t LS3_OC_IE

[14..14] External Low Side 3 FET Over-current Interrupt Enable

◆ LS3_OC_IS

__IM uint32_t LS3_OC_IS

[14..14] External Low Side 3 FET Over-current Status

◆ MON_OV_ICLR

__OM uint32_t MON_OV_ICLR

[4..4] MON Overvoltage Interrupt Status (ADC2 channel 4)

◆ MON_OV_IE

__IOM uint32_t MON_OV_IE

[4..4] MON Overvoltage Interrupt Enable

◆ MON_OV_IS

__IM uint32_t MON_OV_IS

[4..4] MON Overvoltage Interrupt Status (ADC2 channel 4)

◆ MON_OV_SCLR

__OM uint32_t MON_OV_SCLR

[20..20] MON Overvoltage Status

◆ MON_OV_STS

__IM uint32_t MON_OV_STS

[20..20] MON Overvoltage Status

◆ MON_UV_ICLR

__OM uint32_t MON_UV_ICLR

[0..0] MON Undervoltage Interrupt Status (ADC2 channel 4)

◆ MON_UV_IE

__IOM uint32_t MON_UV_IE

[0..0] MON Undervoltage Interrupt Enable

◆ MON_UV_IS

__IM uint32_t MON_UV_IS

[0..0] MON Undervoltage Interrupt Status (ADC2 channel 4)

◆ MON_UV_SCLR

__OM uint32_t MON_UV_SCLR

[16..16] MON Undervoltage Status

◆ MON_UV_STS

__IM uint32_t MON_UV_STS

[16..16] MON Undervoltage Status

◆ 

union { ... } PCU_CTRL_STS

◆ PHU_ZCHI_ICLR

__OM uint32_t PHU_ZCHI_ICLR

[17..17] Phase U Zero Crossing Comperator High Interrupt Status

◆ PHU_ZCHI_IE

__IOM uint32_t PHU_ZCHI_IE

[17..17] Phase U Zero Crossing Comperator High Interrupt Enable

◆ PHU_ZCHI_IS

__IM uint32_t PHU_ZCHI_IS

[17..17] Phase U Zero Crossing Comperator High Interrupt Status

◆ PHU_ZCHI_SCLR

__OM uint32_t PHU_ZCHI_SCLR

[25..25] Phase U Zero Crossing Comperator High Status

◆ PHU_ZCHI_STS

__IM uint32_t PHU_ZCHI_STS

[25..25] Phase U Zero Crossing Comperator High Status

◆ PHU_ZCLOW_ICLR

__OM uint32_t PHU_ZCLOW_ICLR

[16..16] Phase U Zero Crossing Comperator Low Interrupt Status

◆ PHU_ZCLOW_IE

__IOM uint32_t PHU_ZCLOW_IE

[16..16] Phase U Zero Crossing Comperator Low Interrupt Enable

◆ PHU_ZCLOW_IS

__IM uint32_t PHU_ZCLOW_IS

[16..16] Phase U Zero Crossing Comperator Low Interrupt Status

◆ PHU_ZCLOW_SCLR

__OM uint32_t PHU_ZCLOW_SCLR

[24..24] Phase U Zero Crossing Comperator Low Status

◆ PHU_ZCLOW_STS

__IM uint32_t PHU_ZCLOW_STS

[24..24] Phase U Zero Crossing Comperator Low Status

◆ PHV_ZCHI_ICLR

__OM uint32_t PHV_ZCHI_ICLR

[19..19] Phase V Zero Crossing Comperator High Interrupt Status

◆ PHV_ZCHI_IE

__IOM uint32_t PHV_ZCHI_IE

[19..19] Phase V Zero Crossing Comperator High Interrupt Enable

◆ PHV_ZCHI_IS

__IM uint32_t PHV_ZCHI_IS

[19..19] Phase V Zero Crossing Comperator High Interrupt Status

◆ PHV_ZCHI_SCLR

__OM uint32_t PHV_ZCHI_SCLR

[27..27] Phase V Zero Crossing Comperator High Status

◆ PHV_ZCHI_STS

__IM uint32_t PHV_ZCHI_STS

[27..27] Phase V Zero Crossing Comperator High Status

◆ PHV_ZCLOW_ICLR

__OM uint32_t PHV_ZCLOW_ICLR

[18..18] Phase V Zero Crossing Comperator Low Interrupt Status

◆ PHV_ZCLOW_IE

__IOM uint32_t PHV_ZCLOW_IE

[18..18] Phase V Zero Crossing Comperator Low Interrupt Enable

◆ PHV_ZCLOW_IS

__IM uint32_t PHV_ZCLOW_IS

[18..18] Phase V Zero Crossing Comperator Low Interrupt Status

◆ PHV_ZCLOW_SCLR

__OM uint32_t PHV_ZCLOW_SCLR

[26..26] Phase V Zero Crossing Comperator Low Status

◆ PHV_ZCLOW_STS

__IM uint32_t PHV_ZCLOW_STS

[26..26] Phase V Zero Crossing Comperator Low Status

◆ PHW_ZCHI_ICLR

__OM uint32_t PHW_ZCHI_ICLR

[21..21] Phase W Zero Crossing Comperator High Interrupt Status

◆ PHW_ZCHI_IE

__IOM uint32_t PHW_ZCHI_IE

[21..21] Phase W Zero Crossing Comperator High Interrupt Enable

◆ PHW_ZCHI_IS

__IM uint32_t PHW_ZCHI_IS

[21..21] Phase W Zero Crossing Comperator High Interrupt Status

◆ PHW_ZCHI_SCLR

__OM uint32_t PHW_ZCHI_SCLR

[29..29] Phase W Zero Crossing Comperator High Status

◆ PHW_ZCHI_STS

__IM uint32_t PHW_ZCHI_STS

[29..29] Phase W Zero Crossing Comperator High Status

◆ PHW_ZCLOW_ICLR

__OM uint32_t PHW_ZCLOW_ICLR

[20..20] Phase W Zero Crossing Comperator Low Interrupt Status

◆ PHW_ZCLOW_IE

__IOM uint32_t PHW_ZCLOW_IE

[20..20] Phase W Zero Crossing Comperator Low Interrupt Enable

◆ PHW_ZCLOW_IS

__IM uint32_t PHW_ZCLOW_IS

[20..20] Phase W Zero Crossing Comperator Low Interrupt Status

◆ PHW_ZCLOW_SCLR

__OM uint32_t PHW_ZCLOW_SCLR

[28..28] Phase W Zero Crossing Comperator Low Status

◆ PHW_ZCLOW_STS

__IM uint32_t PHW_ZCLOW_STS

[28..28] Phase W Zero Crossing Comperator Low Status

◆ PMU_OT_ICLR

__OM uint32_t PMU_OT_ICLR

[7..7] PMU Regulator Overtemperature Shutdown (ADC2, Channel 9) interrupt status

◆ PMU_OT_IE

__IOM uint32_t PMU_OT_IE

[7..7] PMU Regulator Overtemperature Shutdown Interrupt Enable (leads to shutdown of System)

◆ PMU_OT_IS

__IM uint32_t PMU_OT_IS

[7..7] PMU Regulator Overtemperature Shutdown (ADC2, Channel 9) interrupt status

◆ PMU_OTWARN_ICLR

__OM uint32_t PMU_OTWARN_ICLR

[6..6] PMU Regulator Overtemperature Prewarning (ADC2, Channel 9) interrupt status

◆ PMU_OTWARN_IE

__IOM uint32_t PMU_OTWARN_IE

[6..6] PMU Regulator Overtemperature Warning Interrupt Enable

◆ PMU_OTWARN_IS

__IM uint32_t PMU_OTWARN_IS

[6..6] PMU Regulator Overtemperature Prewarning (ADC2, Channel 9) interrupt status

◆ REFBG_LOTHWARN_ICLR

__OM uint32_t REFBG_LOTHWARN_ICLR

[10..10] 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status

◆ REFBG_LOTHWARN_IE

__IOM uint32_t REFBG_LOTHWARN_IE

[10..10] Reference Voltage Undervoltage Interrupt Enable

◆ REFBG_LOTHWARN_IS

__IM uint32_t REFBG_LOTHWARN_IS

[10..10] 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status

◆ REFBG_UPTHWARN_ICLR

__OM uint32_t REFBG_UPTHWARN_ICLR

[11..11] 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status

◆ REFBG_UPTHWARN_IE

__IOM uint32_t REFBG_UPTHWARN_IE

[11..11] Reference Voltage Overvoltage Interrupt Enable

◆ REFBG_UPTHWARN_IS

__IM uint32_t REFBG_UPTHWARN_IS

[11..11] 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status

◆ reg

(@ 0x00000000) Analog Module Clock Frequency Status Register

(@ 0x00000004) Analog Module Clock Control

(@ 0x0000000C) Analog Module Clock Limit Register

(@ 0x00000014) System Interrupt Status Clear

(@ 0x00000018) System Interrupt Status

(@ 0x0000001C) System Supply Interrupt Status

(@ 0x00000020) System Supply Interrupt Control

(@ 0x00000024) System Supply Interrupt Status Clear

(@ 0x00000028) System Interrupt Control

(@ 0x00000030) Power Control Unit Control Status

(@ 0x00000034) WDT1 Watchdog Control

(@ 0x00000054) Bridge Driver Interrrupt Status Clear

(@ 0x00000058) Bridge Driver Interrrupt Status

(@ 0x0000005C) Bridge Driver Interrupt Control

(@ 0x0000006C) System Tick Calibration Register

(@ 0x00000080) Bus Fault Status

(@ 0x00000084) Data Bus Fault Address Register

(@ 0x00000088) System Bus Fault Address Register

(@ 0x0000008C) Bus Fault Status Clear Register

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1

◆ RESERVED2

__IM uint32_t RESERVED2

◆ RESERVED3

__IM uint32_t RESERVED3[7]

◆ RESERVED4

__IM uint32_t RESERVED4[3]

◆ RESERVED5

__IM uint32_t RESERVED5[4]

◆ SBFA [1/2]

__IM uint32_t SBFA

[31..0] System Bus Fault Address Register

◆  [2/2]

union { ... } SBFA

◆ SBFSTS

__IM uint32_t SBFSTS

[1..1] System Bus Fault Status Valid Flag

◆ SBFSTSCLR

__OM uint32_t SBFSTSCLR

[1..1] System Bus Fault Status Clear Flag

◆ SOWCONF

__IOM uint32_t SOWCONF

[7..6] Short Open Window Configuration

◆ STCALIB [1/2]

__IOM uint32_t STCALIB

[25..0] System Tick Calibration

◆  [2/2]

union { ... } STCALIB

◆ 

union { ... } SYS_IRQ_CTRL

◆ 

union { ... } SYS_IS

◆ 

union { ... } SYS_ISCLR

◆ SYS_OT_ICLR

__OM uint32_t SYS_OT_ICLR

[9..9] System Overtemperature Shutdown (ADC2, Channel 8) interrupt status

◆ SYS_OT_IE

__IOM uint32_t SYS_OT_IE

[9..9] System Overtemperature Shutdown Interrupt Enable (leads to shutdown of System)

◆ SYS_OT_IS

__IM uint32_t SYS_OT_IS

[9..9] System Overtemperature Shutdown (ADC2, Channel 8) interrupt status

◆ SYS_OT_PS_DIS

__IOM uint32_t SYS_OT_PS_DIS

[24..24] System Overtemperature Power Switches Shutdown Disable

◆ SYS_OTWARN_ICLR

__OM uint32_t SYS_OTWARN_ICLR

[8..8] System Overtemperature Prewarning (ADC2, Channel 8) interrupt status

◆ SYS_OTWARN_IE

__IOM uint32_t SYS_OTWARN_IE

[8..8] System Overtemperature Warning Interrupt Enable

◆ SYS_OTWARN_IS

__IM uint32_t SYS_OTWARN_IS

[8..8] System Overtemperature Prewarning (ADC2, Channel 8) interrupt status

◆ 

union { ... } SYS_SUPPLY_IRQ_CLR

◆ 

union { ... } SYS_SUPPLY_IRQ_CTRL

◆ 

union { ... } SYS_SUPPLY_IRQ_STS

◆ SYS_VSD_OV_SLM_DIS

__IOM uint32_t SYS_VSD_OV_SLM_DIS

[14..14] VSD Overvoltage Shutdown for Peripherals Disable

◆ uint32_t

__IM uint32_t

◆ VCP_LOWTH1_ICLR

__OM uint32_t VCP_LOWTH1_ICLR

[17..17] Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Interrupt Status

◆ VCP_LOWTH1_IE

__IOM uint32_t VCP_LOWTH1_IE

[17..17] VCP Measurement Lower Threshold 1 Interrupt Enable

◆ VCP_LOWTH1_IS

__IM uint32_t VCP_LOWTH1_IS

[17..17] Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Interrupt Status

◆ VCP_LOWTH1_SCLR

__OM uint32_t VCP_LOWTH1_SCLR

[25..25] Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Status

◆ VCP_LOWTH1_STS

__IM uint32_t VCP_LOWTH1_STS

[25..25] Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Status

◆ VCP_LOWTH2_ICLR

__OM uint32_t VCP_LOWTH2_ICLR

[16..16] Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Interrupt Status

◆ VCP_LOWTH2_IE

__IOM uint32_t VCP_LOWTH2_IE

[16..16] VCP Measurement Lower Threshold 2 Interrupt Enable

◆ VCP_LOWTH2_IS

__IM uint32_t VCP_LOWTH2_IS

[16..16] Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Interrupt Status

◆ VCP_LOWTH2_SCLR

__OM uint32_t VCP_LOWTH2_SCLR

[24..24] Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Status

◆ VCP_LOWTH2_STS

__IM uint32_t VCP_LOWTH2_STS

[24..24] Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Status

◆ VCP_UPTH_ICLR

__OM uint32_t VCP_UPTH_ICLR

[18..18] Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Interrupt Status

◆ VCP_UPTH_IE

__IOM uint32_t VCP_UPTH_IE

[18..18] VCP Measurement Upper Threshold Interrupt Enable

◆ VCP_UPTH_IS

__IM uint32_t VCP_UPTH_IS

[18..18] Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Interrupt Status

◆ VCP_UPTH_SCLR

__OM uint32_t VCP_UPTH_SCLR

[26..26] Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Status

◆ VCP_UPTH_STS

__IM uint32_t VCP_UPTH_STS

[26..26] Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Status

◆ VDD1V5_OV_ICLR

__OM uint32_t VDD1V5_OV_ICLR

[7..7] VDDC Overvoltage Interrupt Status (ADC2 channel 8)

◆ VDD1V5_OV_IE

__IOM uint32_t VDD1V5_OV_IE

[7..7] VDD1V5 Overvoltage Interrupt Enable

◆ VDD1V5_OV_IS

__IM uint32_t VDD1V5_OV_IS

[7..7] VDDC Overvoltage Interrupt Status (ADC2 channel 8)

◆ VDD1V5_OV_SCLR

__OM uint32_t VDD1V5_OV_SCLR

[23..23] VDDC Overvoltage Status

◆ VDD1V5_OV_STS

__IM uint32_t VDD1V5_OV_STS

[23..23] VDDC Overvoltage Status

◆ VDD1V5_UV_ICLR

__OM uint32_t VDD1V5_UV_ICLR

[3..3] VDDC Undervoltage Interrupt Status (ADC2 channel 8)

◆ VDD1V5_UV_IE

__IOM uint32_t VDD1V5_UV_IE

[3..3] VDD1V5 Undervoltage Interrupt Enable

◆ VDD1V5_UV_IS

__IM uint32_t VDD1V5_UV_IS

[3..3] VDDC Undervoltage Interrupt Status (ADC2 channel 8)

◆ VDD1V5_UV_SCLR

__OM uint32_t VDD1V5_UV_SCLR

[19..19] VDDC Undervoltage Status

◆ VDD1V5_UV_STS

__IM uint32_t VDD1V5_UV_STS

[19..19] VDDC Undervoltage Status

◆ VDD5V_OV_ICLR

__OM uint32_t VDD5V_OV_ICLR

[6..6] VDDP Overvoltage Interrupt Status (ADC2 channel 5)

◆ VDD5V_OV_IE

__IOM uint32_t VDD5V_OV_IE

[6..6] VDD5V Overvoltage Interrupt Enable

◆ VDD5V_OV_IS

__IM uint32_t VDD5V_OV_IS

[6..6] VDDP Overvoltage Interrupt Status (ADC2 channel 5)

◆ VDD5V_OV_SCLR

__OM uint32_t VDD5V_OV_SCLR

[22..22] VDDP Overvoltage Status

◆ VDD5V_OV_STS

__IM uint32_t VDD5V_OV_STS

[22..22] VDDP Overvoltage Status

◆ VDD5V_UV_ICLR

__OM uint32_t VDD5V_UV_ICLR

[2..2] VDDP Undervoltage Interrupt Status (ADC2 channel 5)

◆ VDD5V_UV_IE

__IOM uint32_t VDD5V_UV_IE

[2..2] VDD5V Undervoltage Interrupt Enable

◆ VDD5V_UV_IS

__IM uint32_t VDD5V_UV_IS

[2..2] VDDP Undervoltage Interrupt Status (ADC2 channel 5)

◆ VDD5V_UV_SCLR

__OM uint32_t VDD5V_UV_SCLR

[18..18] VDDP Undervoltage Status

◆ VDD5V_UV_STS

__IM uint32_t VDD5V_UV_STS

[18..18] VDDP Undervoltage Status

◆ VREF5V_LOWTH_ICLR

__OM uint32_t VREF5V_LOWTH_ICLR

[12..12] VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Status

◆ VREF5V_LOWTH_IE

__IOM uint32_t VREF5V_LOWTH_IE

[12..12] VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Enable

◆ VREF5V_LOWTH_IS

__IM uint32_t VREF5V_LOWTH_IS

[12..12] VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Status

◆ VREF5V_OVL_ICLR

__OM uint32_t VREF5V_OVL_ICLR

[14..14] VREF5V Overload Interrupt Status

◆ VREF5V_OVL_IE

__IOM uint32_t VREF5V_OVL_IE

[14..14] VREF5V Overload Interrupt Enable

◆ VREF5V_OVL_IS

__IM uint32_t VREF5V_OVL_IS

[14..14] VREF5V Overload Interrupt Status

◆ VREF5V_UPTH_ICLR

__OM uint32_t VREF5V_UPTH_ICLR

[13..13] VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Status

◆ VREF5V_UPTH_IE

__IOM uint32_t VREF5V_UPTH_IE

[13..13] VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Enable

◆ VREF5V_UPTH_IS

__IM uint32_t VREF5V_UPTH_IS

[13..13] VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Status

◆ VS_OV_ICLR

__OM uint32_t VS_OV_ICLR

[5..5] VS Overvoltage Interrupt Status (ADC2 channel 1)

◆ VS_OV_IE

__IOM uint32_t VS_OV_IE

[5..5] VS Overvoltage Interrupt Enable

◆ VS_OV_IS

__IM uint32_t VS_OV_IS

[5..5] VS Overvoltage Interrupt Status (ADC2 channel 1)

◆ VS_OV_SCLR

__OM uint32_t VS_OV_SCLR

[21..21] VS Overvoltage Interrupt Status

◆ VS_OV_STS

__IM uint32_t VS_OV_STS

[21..21] VS Overvoltage Interrupt Status

◆ VS_UV_ICLR

__OM uint32_t VS_UV_ICLR

[1..1] VS Undervoltage Interrupt Status (ADC2 channel 1)

◆ VS_UV_IE

__IOM uint32_t VS_UV_IE

[1..1] VS Undervoltage Interrupt Enable

◆ VS_UV_IS

__IM uint32_t VS_UV_IS

[1..1] VS Undervoltage Interrupt Status (ADC2 channel 1)

◆ VS_UV_SCLR

__OM uint32_t VS_UV_SCLR

[17..17] VS Undervoltage Status

◆ VS_UV_STS

__IM uint32_t VS_UV_STS

[17..17] VS Undervoltage Status

◆ VSD_LOWTH_ICLR

__OM uint32_t VSD_LOWTH_ICLR

[19..19] Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Interrupt Status

◆ VSD_LOWTH_IE

__IOM uint32_t VSD_LOWTH_IE

[19..19] VSD Measurement Lower Threshold Interrupt Enable

◆ VSD_LOWTH_IS

__IM uint32_t VSD_LOWTH_IS

[19..19] Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Interrupt Status

◆ VSD_LOWTH_SCLR

__OM uint32_t VSD_LOWTH_SCLR

[27..27] Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Status

◆ VSD_LOWTH_STS

__IM uint32_t VSD_LOWTH_STS

[27..27] Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Status

◆ VSD_UPTH_ICLR

__OM uint32_t VSD_UPTH_ICLR

[20..20] Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Interrupt Status

◆ VSD_UPTH_IE

__IOM uint32_t VSD_UPTH_IE

[20..20] VSD Measurement Upper Threshold Interrupt Enable

◆ VSD_UPTH_IS

__IM uint32_t VSD_UPTH_IS

[20..20] Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Interrupt Status

◆ VSD_UPTH_SCLR

__OM uint32_t VSD_UPTH_SCLR

[28..28] Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Status

◆ VSD_UPTH_STS

__IM uint32_t VSD_UPTH_STS

[28..28] Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Status

◆ WDP_SEL

__IOM uint32_t WDP_SEL

[5..0] Watchdog Period Selection and trigger

◆ 

union { ... } WDT1_TRIG

The documentation for this struct was generated from the following file: