109 #include "dma_defines.h"
136 #define DMA_CH10 (10u)
138 #define DMA_CH11 (11u)
140 #define DMA_CH12 (12u)
141 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
143 #define DMA_CH13 (13u)
147 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
149 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
151 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
153 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
155 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
157 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
159 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
161 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
163 #define DMA_MASK_CH8 ((uint16)1u << DMA_CH8)
165 #define DMA_MASK_CH9 ((uint16)1u << DMA_CH9)
167 #define DMA_MASK_CH10 ((uint16)1u << DMA_CH10)
169 #define DMA_MASK_CH11 ((uint16)1u << DMA_CH11)
171 #define DMA_MASK_CH12 ((uint16)1u << DMA_CH12)
172 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
174 #define DMA_MASK_CH13 ((uint16)1u << DMA_CH13)
548 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
1157 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
1331 #if (DMA_XML_VERSION >= 10200)
1618 DMA->CFG.bit.MASTER_ENABLE = 1u;
1621 #error "use IFXConfigWizard XML Version V1.2.0 or greater"
INLINE void DMA_CH0_Int_Clr(void)
clears DMA Channel 0 Interrupt flag.
Definition: dma.h:279
INLINE void DMA_Master_En(void)
Enabled the DMA master.
Definition: dma.h:1615
INLINE void DMA_CH10_Int_Dis(void)
disables DMA Channel 10 Interrupt.
Definition: dma.h:1062
INLINE void DMA_CH10_Int_Clr(void)
clears DMA Channel 10 Interrupt flag.
Definition: dma.h:499
INLINE uint32 DMA_CHx_Entry_Alt(uint8 DMA_Ch)
This function returns the address inside the alternate structure in RAM for a given DMA channel.
Definition: dma.h:1311
INLINE void DMA_CH5_Int_Dis(void)
disables DMA Channel 5 Interrupt.
Definition: dma.h:837
enum DMA_Increment_Size TDMA_Increment_Size
INLINE void DMA_CH11_Int_En(void)
enables DMA Channel 11 Interrupt.
Definition: dma.h:1084
INLINE void DMA_CH3_Int_Clr(void)
clears DMA Channel 3 Interrupt flag.
Definition: dma.h:345
DMA_Transfer_Size
Definition: dma.h:181
@ DMA_32Bit_Transfer
Definition: dma.h:184
@ DMA_8Bit_Transfer
Definition: dma.h:182
@ DMA_16Bit_Transfer
Definition: dma.h:183
INLINE void DMA_CH5_Int_En(void)
enables DMA Channel 5 Interrupt.
Definition: dma.h:814
INLINE void DMA_CH6_Int_Dis(void)
disables DMA Channel 6 Interrupt.
Definition: dma.h:882
INLINE void DMA_CH9_Int_Dis(void)
disables DMA Channel 9 Interrupt.
Definition: dma.h:1017
enum DMA_Cycle_Types TDMA_Cycle_Types
INLINE void DMA_CH0_Int_En(void)
enables DMA Channel 0 Interrupt.
Definition: dma.h:589
INLINE void DMA_CH13_Int_Clr(void)
clears DMA Channel 13 Interrupt flag.
Definition: dma.h:566
INLINE void DMA_CH7_Int_Clr(void)
clears DMA Channel 7 Interrupt flag.
Definition: dma.h:433
INLINE void DMA_CH1_Int_Dis(void)
disables DMA Channel 1 Interrupt.
Definition: dma.h:657
INLINE void DMA_CH4_Int_Dis(void)
disables DMA Channel 4 Interrupt.
Definition: dma.h:792
enum DMA_Increment_Mode TDMA_Increment_Mode
INLINE void DMA_CH11_Int_Dis(void)
disables DMA Channel 11 Interrupt.
Definition: dma.h:1107
INLINE void DMA_Primary_Struct_Usage_Set(uint32 mask_ch)
selects the primary data structure for the corresponding DMA channel.
Definition: dma.h:1279
DMA_Increment_Mode
Definition: dma.h:201
@ DMA_No_Inc
Definition: dma.h:202
@ DMA_Src_Inc
Definition: dma.h:203
@ DMA_Dst_Inc
Definition: dma.h:204
@ DMA_Src_Dst_Inc
Definition: dma.h:205
INLINE void DMA_CH0_Int_Dis(void)
disables DMA Channel 0 Interrupt.
Definition: dma.h:612
void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt)
Resets the primary structure in RAM for a given channel and rearms it.
INLINE void DMA_CH13_Int_Dis(void)
disables DMA Channel 13 Interrupt.
Definition: dma.h:1198
INLINE void DMA_CH9_Int_En(void)
enables DMA Channel 9 Interrupt.
Definition: dma.h:994
INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
enables DMA Channels.
Definition: dma.h:1239
INLINE void DMA_CH4_Int_Clr(void)
clears DMA Channel 4 Interrupt flag.
Definition: dma.h:367
INLINE void DMA_CH11_Int_Clr(void)
clears DMA Channel 11 Interrupt flag.
Definition: dma.h:521
INLINE void DMA_CH2_Int_Dis(void)
disables DMA Channel 2 Interrupt.
Definition: dma.h:702
TDMA_Entry * DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up a task to be used in the Scatter-Gather modes.
INLINE void DMA_CH3_Int_En(void)
enables DMA Channel 3 Interrupt.
Definition: dma.h:724
INLINE void DMA_CH8_Int_En(void)
enables DMA Channel 8 Interrupt.
Definition: dma.h:949
INLINE void DMA_CH6_Int_En(void)
enables DMA Channel 6 Interrupt.
Definition: dma.h:859
INLINE void DMA_CH1_Int_Clr(void)
clears DMA Channel 1 Interrupt flag.
Definition: dma.h:301
DMA_Cycle_Types
Definition: dma.h:212
@ DMA_Cycle_Type_PerSctGthPrim
Definition: dma.h:219
@ DMA_Cycle_Type_Basic
Definition: dma.h:214
@ DMA_Cycle_Type_MemSctGthPrim
Definition: dma.h:217
@ DMA_Cycle_Type_Auto
Definition: dma.h:215
@ DMA_Cycle_Type_PingPong
Definition: dma.h:216
@ DMA_Cycle_Type_MemSctGthAlt
Definition: dma.h:218
@ DMA_Cycle_Type_PerSctGthAlt
Definition: dma.h:220
@ DMA_Cycle_Type_Invalid
Definition: dma.h:213
INLINE void DMA_CH7_Int_Dis(void)
disables DMA Channel 7 Interrupt.
Definition: dma.h:927
INLINE void DMA_CH5_Int_Clr(void)
clears DMA Channel 5 Interrupt flag.
Definition: dma.h:389
INLINE void DMA_CH12_Int_Dis(void)
disables DMA Channel 12 Interrupt.
Definition: dma.h:1152
void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up the desired DMA channel in the primary structure in RAM.
INLINE void DMA_CH2_Int_Clr(void)
clears DMA Channel 2 Interrupt flag.
Definition: dma.h:323
INLINE void DMA_CH1_Int_En(void)
enables DMA Channel 1 Interrupt.
Definition: dma.h:634
INLINE void DMA_Alternate_Struct_Usage_Set(uint32 mask_ch)
selects the alternate data structure for the corresponding DMA channel.
Definition: dma.h:1299
void DMA_Init(void)
Initializes the DMA structure in RAM and SFRs based on the Config Wizard for MOTIX MCU configuration.
INLINE void DMA_Software_Request_Set(uint32 mask_ch)
Set software request for DMA Channels.
Definition: dma.h:1259
INLINE void DMA_CH7_Int_En(void)
enables DMA Channel 7 Interrupt.
Definition: dma.h:904
enum DMA_Transfer_Size TDMA_Transfer_Size
INLINE void DMA_CH3_Int_Dis(void)
disables DMA Channel 3 Interrupt.
Definition: dma.h:747
INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
points to the base address of the primary data structure.
Definition: dma.h:1219
INLINE void DMA_CH13_Int_En(void)
enables DMA Channel 13 Interrupt.
Definition: dma.h:1175
INLINE void DMA_CH9_Int_Clr(void)
clears DMA Channel 9 Interrupt flag.
Definition: dma.h:477
INLINE void DMA_CH6_Int_Clr(void)
clears DMA Channel 6 Interrupt flag.
Definition: dma.h:411
void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.
void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
INLINE void DMA_CH2_Int_En(void)
enables DMA Channel 2 Interrupt.
Definition: dma.h:679
INLINE void DMA_CH4_Int_En(void)
enables DMA Channel 4 Interrupt.
Definition: dma.h:769
DMA_Increment_Size
Definition: dma.h:191
@ DMA_Inc_8bit
Definition: dma.h:192
@ DMA_Inc_32bit
Definition: dma.h:194
@ DMA_Inc_16bit
Definition: dma.h:193
INLINE uint32 DMA_CHx_Entry_Pri(uint8 DMA_Ch)
This function returns the address inside the primary structure in RAM for a given DMA channel.
Definition: dma.h:1323
INLINE void DMA_CH10_Int_En(void)
enables DMA Channel 10 Interrupt.
Definition: dma.h:1039
INLINE void DMA_CH8_Int_Dis(void)
disables DMA Channel 8 Interrupt.
Definition: dma.h:972
INLINE void DMA_CH12_Int_Clr(void)
clears DMA Channel 12 Interrupt flag.
Definition: dma.h:543
INLINE void DMA_CH8_Int_Clr(void)
clears DMA Channel 8 Interrupt flag.
Definition: dma.h:455
INLINE void DMA_CH12_Int_En(void)
enables DMA Channel 12 Interrupt.
Definition: dma.h:1129
TDMA_Entry * DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
Sets up a task to be used with memory scatter-gather mode.
#define DMA
Definition: tle987x.h:6090
#define SCU
Definition: tle987x.h:6097
#define SCU_DMAIRC1CLR_CH8C_Pos
Definition: tle987x.h:8859
#define SCU_DMAIEN1_CH1IE_Msk
Definition: tle987x.h:8825
#define SCU_DMAIEN1_CH7IE_Pos
Definition: tle987x.h:8812
#define SCU_DMAIRC2CLR_SDADCC_Pos
Definition: tle987x.h:8891
#define SCU_DMAIRC1CLR_CH7C_Pos
Definition: tle987x.h:8861
#define SCU_DMAIRC2CLR_SSC1C_Pos
Definition: tle987x.h:8897
#define SCU_DMAIRC1CLR_CH4C_Pos
Definition: tle987x.h:8867
#define SCU_DMAIRC2CLR_SSC1C_Msk
Definition: tle987x.h:8898
#define SCU_DMAIEN2_SSCTXIE_Pos
Definition: tle987x.h:8833
#define SCU_DMAIEN1_CH3IE_Pos
Definition: tle987x.h:8820
#define SCU_DMAIRC1CLR_CH5C_Pos
Definition: tle987x.h:8865
#define SCU_DMAIRC1CLR_CH1C_Msk
Definition: tle987x.h:8874
#define SCU_DMAIEN2_TRSEQ2RDYIE_Pos
Definition: tle987x.h:8835
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk
Definition: tle987x.h:7922
#define SCU_DMAIEN2_SDADCIE_Msk
Definition: tle987x.h:8828
#define SCU_DMAIRC1CLR_CH1C_Pos
Definition: tle987x.h:8873
#define SCU_DMAIEN1_CH8IE_Msk
Definition: tle987x.h:8811
#define SCU_DMAIRC1CLR_CH2C_Pos
Definition: tle987x.h:8871
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos
Definition: tle987x.h:7918
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos
Definition: tle987x.h:8901
#define SCU_DMAIEN2_GPT12IE_Pos
Definition: tle987x.h:8829
#define SCU_DMAIEN1_CH5IE_Pos
Definition: tle987x.h:8816
#define SCU_DMAIEN1_CH2IE_Pos
Definition: tle987x.h:8822
#define SCU_DMAIEN1_CH6IE_Msk
Definition: tle987x.h:8815
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos
Definition: tle987x.h:7921
#define SCU_DMAIRC1CLR_CH7C_Msk
Definition: tle987x.h:8862
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk
Definition: tle987x.h:7949
#define SCU_DMAIRC1CLR_CH3C_Msk
Definition: tle987x.h:8870
#define SCU_DMAIRC1CLR_CH2C_Msk
Definition: tle987x.h:8872
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos
Definition: tle987x.h:8899
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk
Definition: tle987x.h:7940
#define SCU_DMAIEN1_CH3IE_Msk
Definition: tle987x.h:8821
#define SCU_DMAIRC1CLR_CH5C_Msk
Definition: tle987x.h:8866
#define SCU_DMAIEN1_CH4IE_Pos
Definition: tle987x.h:8818
#define SCU_DMAIEN1_CH7IE_Msk
Definition: tle987x.h:8813
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk
Definition: tle987x.h:7925
#define SCU_DMAIRC1CLR_CH8C_Msk
Definition: tle987x.h:8860
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk
Definition: tle987x.h:8900
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos
Definition: tle987x.h:7924
#define SCU_DMAIEN2_SDADCIE_Pos
Definition: tle987x.h:8827
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos
Definition: tle987x.h:7939
#define SCU_DMAIRC2CLR_GPT12C_Msk
Definition: tle987x.h:8894
#define SCU_DMAIEN2_TRSEQ1RDYIE_Msk
Definition: tle987x.h:8838
#define SCU_DMAIEN1_CH4IE_Msk
Definition: tle987x.h:8819
#define SCU_DMAIEN2_SSCRXIE_Msk
Definition: tle987x.h:8832
#define SCU_DMAIRC1CLR_CH6C_Pos
Definition: tle987x.h:8863
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos
Definition: tle987x.h:7948
#define SCU_DMAIEN2_GPT12IE_Msk
Definition: tle987x.h:8830
#define SCU_DMAIEN1_CH5IE_Msk
Definition: tle987x.h:8817
#define SCU_DMAIRC2CLR_SSC2C_Msk
Definition: tle987x.h:8896
#define SCU_DMAIEN2_SSCRXIE_Pos
Definition: tle987x.h:8831
#define SCU_DMAIRC1CLR_CH6C_Msk
Definition: tle987x.h:8864
#define SCU_DMAIRC2CLR_GPT12C_Pos
Definition: tle987x.h:8893
#define SCU_DMAIEN1_CH6IE_Pos
Definition: tle987x.h:8814
#define SCU_DMAIEN1_CH8IE_Pos
Definition: tle987x.h:8810
#define SCU_DMAIEN1_CH2IE_Msk
Definition: tle987x.h:8823
#define SCU_DMAIEN2_TRSEQ2RDYIE_Msk
Definition: tle987x.h:8836
#define SCU_DMAIEN2_TRSEQ1RDYIE_Pos
Definition: tle987x.h:8837
#define SCU_DMAIEN1_CH1IE_Pos
Definition: tle987x.h:8824
#define SCU_DMAIRC1CLR_CH4C_Msk
Definition: tle987x.h:8868
#define SCU_DMAIRC2CLR_SSC2C_Pos
Definition: tle987x.h:8895
#define SCU_DMAIRC2CLR_SDADCC_Msk
Definition: tle987x.h:8892
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk
Definition: tle987x.h:8902
#define SCU_DMAIEN2_SSCTXIE_Msk
Definition: tle987x.h:8834
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk
Definition: tle987x.h:7919
#define SCU_DMAIRC1CLR_CH3C_Pos
Definition: tle987x.h:8869
SFR low level access library.
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:362
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:352
This structure lists the DMA transfer memory locations.
Definition: dma.h:251
uint32 Dst_End_Ptr
Definition: dma.h:253
uint32 Src_End_Ptr
Definition: dma.h:252
uint32 reserved
Definition: dma.h:255
TControl Control
Definition: dma.h:254
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:148
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint32_t uint32
32 bit unsigned value
Definition: types.h:155
This structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:230
uint32 Dst_Inc
Bit[31..30].
Definition: dma.h:243
uint32 Cycle_Ctrl
Bit[2..0].
Definition: dma.h:234
uint32 R_Power
Bit[17..14].
Definition: dma.h:237
uint32 Src_Prot_Ctrl
Bit[20..18].
Definition: dma.h:238
uint32 Dst_Size
Bit[29..28].
Definition: dma.h:242
uint32 Next_UseBurst
Bit[3].
Definition: dma.h:235
uint32 Src_Inc
Bit[27..26].
Definition: dma.h:241
uint32 Dst_Prot_Ctrl
Bit[23..21].
Definition: dma.h:239
uint32 N_Minus_1
Bit[13..4].
Definition: dma.h:236
uint32 reg
Definition: dma.h:231
uint32 Src_Size
Bit[25..24].
Definition: dma.h:240