Infineon MOTIX™ MCU TLE987x Device Family SDK
ccu6.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** TA Thomas Albersinger **
44 ** BG Blandine Guillot **
45 ** JO Julia Ott **
46 ** VO Vanessa Ongaro **
47 *******************************************************************************/
48 
49 /*******************************************************************************
50 ** Revision Control History **
51 ********************************************************************************
52 ** V0.2.0: 2014-04-25, TA: CCU6_Init(): use #defines from IFX Config Wizard **
53 ** V0.2.1: 2015-02-10, DM: Individual header file added **
54 ** V0.2.2: 2015-08-27, DM: new API functions added to ccu6.h **
55 ** V0.2.3: 2017-04-11, DM: Macros for interrupt set/reset/clear added **
56 ** V0.2.4: 2017-11-08, DM: CCU6_T12_Modulation_En() fixed **
57 ** CCU6_T13_Modulation_En() fixed **
58 ** V0.2.5: 2017-11-14, DM: MISRA 2012 compliance, the following PC-Lint **
59 ** rules are globally deactivated: **
60 ** - Info 793: ANSI/ISO limit of 6 'significant **
61 ** characters in an external identifier **
62 ** - Info 835: A zero has been given as right **
63 ** argument to operator **
64 ** - Info 845: The left argument to operator '&' **
65 ** is certain to be 0 **
66 ** CCU6_Init(): one CCU6_T12_Str_En() replaced by **
67 ** CCU6_T13_Str_En() **
68 ** Replaced macros by INLINE functions **
69 ** Replaced register accesses within functions by **
70 ** function calls **
71 ** Replaced __STATIC_INLINE by INLINE **
72 ** V0.2.6: 2018-03-14, DM: CCU6_Ch0_Deadtime_Sts(), CCU6_Ch1_Deadtime_Sts(),**
73 ** CCU6_Ch2_Deadtime_Sts() the register access **
74 ** macro changed to Field_Rd1() **
75 ** CCU6_MASK_CC6x and CCU6_MASK_COUT6x changed due **
76 ** to MISRA 2012 **
77 ** V0.2.7: 2018-12-04, JO: Doxygen update **
78 ** Moved revision history from ccu6.c to ccu6.h **
79 ** CCU6_Passive_State_After_Compare_Sel() added **
80 ** CCU6_Ch*t_Passive_State_After_Compare_Sel and **
81 ** CCU6_Ch*t_Passive_State_Before_Compare_Sel **
82 ** removed **
83 ** V0.2.8: 2019-01-29, DM: CCU6_ReadHallReg() fixed **
84 ** V0.2.9: 2019-02-27, JO: CCU6_SetT13Compare() changed (added range check, **
85 ** +1 instead of +10) **
86 ** V0.3.0: 2020-04-15, BG: Updated revision history format **
87 ** V0.3.1: 2020-07-13, JO: EP-431: remove ARMCC v6 Compiler warnings **
88 ** - Added typecasts to remove 'implicit typecast' **
89 ** warning **
90 ** V0.3.2: 2020-07-21, BG: EP-439: Formatted .h/.c files **
91 ** V0.3.3: 2022-02-28, JO: EP-936: Updated copyright and branding **
92 ** V0.4.0: 2022-10-10, JO: EP-1149: Added functions CCU6_T12_T13_Str_En/Dis **
93 ** V0.4.1: 2022-10-18, VO: EP-1252: Updated enum definitions **
94 *******************************************************************************/
95 
96 #ifndef _CCU6_H
97 #define _CCU6_H
98 
99 /*******************************************************************************
100 ** Includes **
101 *******************************************************************************/
102 #include "tle987x.h"
103 #include "types.h"
104 #include "ccu6_defines.h"
105 #include "sfr_access.h"
106 #include "tle_variants.h"
107 
108 /*******************************************************************************
109 ** Global Macro Definitions **
110 *******************************************************************************/
112 #define CCU6_MASK_TCTR4_STOP_T12 (CCU6_TCTR4_T12RR_Msk)
114 #define CCU6_MASK_TCTR4_START_T12 (CCU6_TCTR4_T12RS_Msk)
116 #define CCU6_MASK_TCTR4_RESET_T12 (CCU6_TCTR4_T12RES_Msk)
118 #define CCU6_MASK_TCTR4_SHADOW_T12 (CCU6_TCTR4_T12STR_Msk)
120 #define CCU6_MASK_TCTR4_STOP_T13 (CCU6_TCTR4_T13RR_Msk)
122 #define CCU6_MASK_TCTR4_START_T13 (CCU6_TCTR4_T13RS_Msk)
124 #define CCU6_MASK_TCTR4_RESET_T13 (CCU6_TCTR4_T13RES_Msk)
126 #define CCU6_MASK_TCTR4_SHADOW_T13 (CCU6_TCTR4_T13STR_Msk)
127 
129 #define CCU6_MASK_MCMOUTS_SHADOW_HALL (CCU6_MCMOUTS_STRHP_Msk)
131 #define CCU6_MASK_MCMOUTS_SHADOW_OUT (CCU6_MCMOUTS_STRMCM_Msk)
132 
134 #define CCU6_MASK_CC60 ((uint16)1u << 0u)
136 #define CCU6_MASK_COUT60 ((uint16)1u << 1u)
138 #define CCU6_MASK_CC61 ((uint16)1u << 2u)
140 #define CCU6_MASK_COUT61 ((uint16)1u << 3u)
142 #define CCU6_MASK_CC62 ((uint16)1u << 4u)
144 #define CCU6_MASK_COUT62 ((uint16)1u << 5u)
145 
147 #define CCU6_MASK_Ch0t CCU6_MASK_CC60
149 #define CCU6_MASK_Ch0c CCU6_MASK_COUT60
151 #define CCU6_MASK_Ch1t CCU6_MASK_CC61
153 #define CCU6_MASK_Ch1c CCU6_MASK_COUT61
155 #define CCU6_MASK_Ch2t CCU6_MASK_CC62
157 #define CCU6_MASK_Ch2c CCU6_MASK_COUT62
158 
159 /*******************************************************************************
160 ** Global Type Definitions **
161 *******************************************************************************/
165 typedef enum CCU6_Ch0_Input
166 {
168  CCU6_CC60_1_P23 = 1u
170 
174 typedef enum CCU6_Ch1_Input
175 {
176  CCU6_CC61_0_P10 = 0u
178 
182 typedef enum CCU6_Ch2_Input
183 {
185  CCU6_CC62_2_P22 = 2u
187 
191 typedef enum CCU6_Trap_Input
192 {
194  CCU6_CTRAP_1_P23 = 1u
196 
200 typedef enum CCU6_Pos0_Input
201 {
204  CCU6_CCPOS0_3_P20 = 3u
205 #if (UC_SERIES == TLE987)
206  ,
207  CCU6_CCPOS0_BEMF = 3u
208 #endif /* (UC_SERIES == TLE987) */
210 
214 typedef enum CCU6_Pos1_Input
215 {
218  CCU6_CCPOS1_2_P14 = 2u
219 #if (UC_SERIES == TLE987)
220  ,
221  CCU6_CCPOS1_BEMF = 3u
222 #endif /* (UC_SERIES == TLE987) */
224 
228 typedef enum CCU6_Pos2_Input
229 {
232  CCU6_CCPOS2_3_P22 = 3u
233 #if (UC_SERIES == TLE987)
234  ,
235  CCU6_CCPOS2_BEMF = 3u
236 #endif /* (UC_SERIES == TLE987) */
238 
242 typedef enum CCU6_T12HR_Input
243 {
245  CCU6_T12HR_2_P20 = 2u
247 
251 typedef enum CCU6_T13HR_Input
252 {
254  CCU6_T13HR_2_P22 = 2u
256 
260 typedef enum CCU6_T12_Cnt_Input
261 {
267 
271 typedef enum CCU6_T13_Cnt_Input
272 {
278 
282 typedef enum CCU6_T12_Ext_Input
283 {
285  CCU6_T12HR_H_E = 1u
287 
291 typedef enum CCU6_T13_Ext_Input
292 {
294  CCU6_T13HR_H_E = 1u
296 
300 typedef enum CCU6_HSYNC
301 {
303  CCU6_T13_CM = 1u,
304  CCU6_T13_PM = 2u,
306  CCU6_T12_PM = 4u,
307  CCU6_T12_OM = 5u,
311 
315 typedef enum CCU6_Clk_Prescaler
316 {
324  CCU6_Clk_Div_128 = 7
326 
330 typedef enum CCU6_T13TEC
331 {
339  CCU6_T13TEC_CCPOSx = 7
341 
345 typedef enum CCU6_T13ED
346 {
352 
356 typedef enum CCU6_T12RSEL
357 {
363 
367 typedef enum CCU6_T13RSEL
368 {
374 
378 typedef enum CCU6_PSL63
379 {
381  CCU6_PSL63_High = 1
383 
387 typedef enum CCU6_MCM_SWSEL
388 {
394  CCU6_SWSEL_T12_PM = 5
396 
400 typedef enum CCU6_Node_Sel
401 {
405  CCU6_Node3 = 3
407 
408 
409 
413 typedef enum CCU6_PWMMode
414 {
420 
421 
422 /*******************************************************************************
423 ** Global Inline Function Definitions **
424 *******************************************************************************/
438 {
440 }
441 
455 {
457 }
458 
472 {
474 }
475 
489 {
491 }
492 
508 {
510 }
511 
525 {
527 }
528 
542 {
544 }
545 
559 {
561 }
562 
576 {
578 }
579 
593 {
595 }
596 
612 {
614 }
615 
629 {
631 }
632 
646 {
648 }
649 
663 {
665 }
666 
680 {
682 }
683 
699 {
701 }
702 
718 {
720 }
721 
737 {
739 }
740 
756 {
758 }
759 
775 {
777 }
778 
794 {
796 }
797 
813 {
815 }
816 
833 {
835 }
836 
853 {
855 }
856 
874 {
876 }
877 
895 {
897 }
898 
915 {
917 }
918 
935 {
937 }
938 
952 {
954 }
955 
969 {
971 }
972 
988 {
990 }
991 
1007 {
1009 }
1010 
1026 {
1028 }
1029 
1045 {
1047 }
1048 
1066 {
1068 }
1069 
1086 {
1088 }
1089 
1108 {
1110 }
1111 
1128 {
1130 }
1131 
1149 {
1151 }
1152 
1168 {
1170 }
1171 
1189 {
1191 }
1192 
1208 {
1210 }
1211 
1229 {
1231 }
1232 
1248 {
1250 }
1251 
1269 {
1271 }
1272 
1288 {
1290 }
1291 
1305 {
1307 }
1308 
1322 {
1324 }
1325 
1339 {
1341 }
1342 
1356 {
1358 }
1359 
1373 {
1375 }
1376 
1390 {
1392 }
1393 
1412 {
1414 }
1415 
1434 {
1436 }
1437 
1456 {
1458 }
1459 
1477 {
1479 }
1480 
1496 {
1498 }
1499 
1517 {
1519 }
1520 
1536 {
1538 }
1539 
1557 {
1559 }
1560 
1576 {
1578 }
1579 
1599 {
1601 }
1602 
1622 {
1624 }
1625 
1645 {
1647 }
1648 
1668 {
1670 }
1671 
1690 {
1692 }
1693 
1712 {
1714 }
1715 
1734 {
1736 }
1737 
1745 {
1746  Field_Mod16(&CCU6->CMPSTAT.reg, (uint16)CCU6_CMPSTAT_CC60PS_Pos, (uint16)0x3F00, (uint16_t)mode);
1747  CCU6_T12_Str_En();
1748 }
1749 
1750 
1767 {
1769  CCU6_T13_Str_En();
1770 }
1771 
1788 {
1790  CCU6_T13_Str_En();
1791 }
1792 
1806 {
1808  CCU6_T13_Str_En();
1809 }
1810 
1824 {
1826  CCU6_T13_Str_En();
1827 }
1828 
1842 {
1844 }
1845 
1859 {
1861 }
1862 
1876 {
1878 }
1879 
1893 {
1895 }
1896 
1910 {
1912 }
1913 
1927 {
1929 }
1930 
1944 {
1946 }
1947 
1961 {
1963 }
1964 
1978 {
1980 }
1981 
1995 {
1997 }
1998 
2015 {
2017 }
2018 
2035 {
2037 }
2038 
2052 {
2054 }
2055 
2069 {
2071 }
2072 
2086 {
2088 }
2089 
2103 {
2105 }
2106 
2125 {
2127 }
2128 
2147 {
2149 }
2150 
2169 {
2171 }
2172 
2191 {
2193 }
2194 
2213 {
2215 }
2216 
2230 {
2232 }
2233 
2247 {
2249 }
2250 
2266 {
2268 }
2269 
2285 {
2287 }
2288 
2304 {
2306 }
2307 
2323 {
2325 }
2326 
2342 {
2344 }
2345 
2361 {
2363 }
2364 
2380 {
2382 }
2383 
2399 {
2401 }
2402 
2416 {
2418 }
2419 
2433 {
2435 }
2436 
2450 {
2452 }
2453 
2467 {
2469 }
2470 
2484 {
2486 }
2487 
2501 {
2503 }
2504 
2518 {
2520 }
2521 
2535 {
2537 }
2538 
2552 {
2554 }
2555 
2569 {
2571 }
2572 
2586 {
2588 }
2589 
2603 {
2605 }
2606 
2620 {
2622 }
2623 
2639 {
2641 }
2642 
2673 {
2674  Field_Mod16(&CCU6->CMPSTAT.reg, (uint16)CCU6_CMPSTAT_CC60PS_Pos, (uint16)0x3F00, ccu6_mask);
2675  CCU6_T12_Str_En();
2676 }
2677 
2691 {
2692  Field_Mod16(&CCU6->PSLR.reg, 0u, 0x01u, 1u);
2693 }
2694 
2708 {
2709  Field_Mod16(&CCU6->PSLR.reg, 0u, 0x01u, 0u);
2710 }
2711 
2725 {
2726  Field_Mod16(&CCU6->PSLR.reg, 1u, 0x02u, 1u);
2727 }
2728 
2742 {
2743  Field_Mod16(&CCU6->PSLR.reg, 1u, 0x02u, 0u);
2744 }
2745 
2759 {
2760  Field_Mod16(&CCU6->PSLR.reg, 2u, 0x04u, 1u);
2761 }
2762 
2776 {
2777  Field_Mod16(&CCU6->PSLR.reg, 2u, 0x04u, 0u);
2778 }
2779 
2793 {
2794  Field_Mod16(&CCU6->PSLR.reg, 3u, 0x08u, 1u);
2795 }
2796 
2810 {
2811  Field_Mod16(&CCU6->PSLR.reg, 3u, 0x08u, 0u);
2812 }
2813 
2827 {
2828  Field_Mod16(&CCU6->PSLR.reg, 4u, 0x10u, 1u);
2829 }
2830 
2844 {
2845  Field_Mod16(&CCU6->PSLR.reg, 4u, 0x10u, 0u);
2846 }
2847 
2861 {
2862  Field_Mod16(&CCU6->PSLR.reg, 5u, 0x20u, 1u);
2863 }
2864 
2878 {
2879  Field_Mod16(&CCU6->PSLR.reg, 5u, 0x20u, 0u);
2880 }
2881 
2911 {
2912  Field_Mod16(&CCU6->PSLR.reg, (uint16)CCU6_PSLR_PSL_Pos, (uint16)CCU6_PSLR_PSL_Msk, ccu6_mask);
2913 }
2914 
2930 {
2932 }
2933 
2949 {
2951 }
2952 
2966 {
2968 }
2969 
2983 {
2985 }
2986 
3002 {
3003  Field_Mod16(&CCU6->MCMOUTS.reg, (uint16)CCU6_MCMOUTS_EXPHS_Pos, (uint16)CCU6_MCMOUTS_EXPHS_Msk, mcm_mask_ccpos);
3004 }
3005 
3021 {
3022  Field_Mod16(&CCU6->MCMOUTS.reg, (uint16)CCU6_MCMOUTS_CURHS_Pos, (uint16)CCU6_MCMOUTS_CURHS_Msk, mcm_mask_ccpos);
3023 }
3024 
3038 {
3040 }
3041 
3055 {
3057 }
3058 
3076 {
3078 }
3079 
3098 {
3099  return ( u8_Field_Rd16(&CCU6->MCMOUT.reg, (uint16)CCU6_MCMOUT_R_Pos, (uint16)CCU6_MCMOUT_R_Msk) );
3100 }
3101 
3119 {
3121 }
3122 
3140 {
3142 }
3143 
3159 {
3161 }
3162 
3176 {
3178 }
3179 
3193 {
3195 }
3196 
3210 {
3212 }
3213 
3227 {
3229 }
3230 
3244 {
3246 }
3247 
3261 {
3263 }
3264 
3278 {
3280 }
3281 
3295 {
3297 }
3298 
3312 {
3314 }
3315 
3329 {
3331 }
3332 
3346 {
3348 }
3349 
3363 {
3365 }
3366 
3380 {
3382 }
3383 
3397 {
3399 }
3400 
3414 {
3416 }
3417 
3438 {
3440 }
3441 
3462 {
3464 }
3465 
3486 {
3488 }
3489 
3510 {
3512 }
3513 
3534 {
3536 }
3537 
3558 {
3560 }
3561 
3582 {
3584 }
3585 
3606 {
3608 }
3609 
3630 {
3632 }
3633 
3654 {
3656 }
3657 
3678 {
3680 }
3681 
3702 {
3704 }
3705 
3726 {
3728 }
3729 
3750 {
3752 }
3753 
3772 {
3774 }
3775 
3796 {
3798 }
3799 
3819 {
3821 }
3822 
3842 {
3844 }
3845 
3865 {
3867 }
3868 
3888 {
3890 }
3891 
3911 {
3913 }
3914 
3934 {
3936 }
3937 
3957 {
3959 }
3960 
3980 {
3982 }
3983 
4003 {
4005 }
4006 
4026 {
4028 }
4029 
4049 {
4051 }
4052 
4066 {
4068 }
4069 
4089 {
4091 }
4092 
4112 {
4114 }
4115 
4132 {
4134 }
4135 
4155 {
4157 }
4158 
4180 {
4182 }
4183 
4205 {
4207 }
4208 
4230 {
4232 }
4233 
4255 {
4257 }
4258 
4280 {
4282 }
4283 
4305 {
4307 }
4308 
4330 {
4332 }
4333 
4352 {
4354 }
4355 
4374 {
4376 }
4377 
4396 {
4398 }
4399 
4418 {
4420 }
4421 
4440 {
4442 }
4443 
4462 {
4464 }
4465 
4484 {
4486 }
4487 
4506 {
4508 }
4509 
4528 {
4530 }
4531 
4550 {
4552 }
4553 
4572 {
4574 }
4575 
4594 {
4596 }
4597 
4616 {
4618 }
4619 
4638 {
4640 }
4641 
4660 {
4662 }
4663 
4683 {
4685 }
4686 
4705 {
4707 }
4708 
4728 {
4730 }
4731 
4750 {
4752 }
4753 
4773 {
4775 }
4776 
4795 {
4797 }
4798 
4818 {
4820 }
4821 
4840 {
4842 }
4843 
4863 {
4865 }
4866 
4885 {
4887 }
4888 
4908 {
4910 }
4911 
4930 {
4932 }
4933 
4953 {
4955 }
4956 
4975 {
4977 }
4978 
4998 {
5000 }
5001 
5020 {
5022 }
5023 
5043 {
5045 }
5046 
5065 {
5067 }
5068 
5088 {
5090 }
5091 
5110 {
5112 }
5113 
5133 {
5135 }
5136 
5155 {
5157 }
5158 
5178 {
5180 }
5181 
5200 {
5202 }
5203 
5223 {
5225 }
5226 
5245 {
5247 }
5248 
5268 {
5270 }
5271 
5272 /*******************************************************************************
5273 ** Global Function Declarations **
5274 *******************************************************************************/
5279 void CCU6_Init(void);
5280 
5281 INLINE void CCU6_StartTmr_T12(void);
5282 INLINE void CCU6_StartTmr_T13(void);
5283 INLINE void CCU6_StopTmr_T12(void);
5284 INLINE void CCU6_StopTmr_T13(void);
5285 INLINE void CCU6_EnableST_T12(void);
5286 INLINE void CCU6_EnableST_T13(void);
5293 INLINE bool CCU6_IsT13Running(void);
5294 INLINE void CCU6_SetT13Trigger(uint16 Mask);
5295 INLINE void CCU6_SetT13Compare(uint16 Compare);
5302 INLINE void CCU6_EnableInt(uint16 Mask);
5303 INLINE void CCU6_ClearIntStatus(uint16 Mask);
5304 
5305 /*******************************************************************************
5306 ** Global Inline Function Definitions **
5307 *******************************************************************************/
5321 {
5322  CCU6_T12_Start();
5323 }
5324 
5338 {
5339  CCU6_T13_Start();
5340 }
5341 
5355 {
5356  CCU6_T12_Stop();
5357 }
5358 
5372 {
5373  CCU6_T13_Stop();
5374 }
5375 
5389 {
5390  CCU6_T12_Str_En();
5391 }
5392 
5406 {
5407  CCU6_T13_Str_En();
5408 }
5409 
5425 {
5426  CCU6_Ch0_Value_Set(tick);
5427 }
5428 
5444 {
5445  CCU6_Ch1_Value_Set(tick);
5446 }
5447 
5463 {
5464  CCU6_Ch2_Value_Set(tick);
5465 }
5466 
5482 {
5483  CCU6_Ch3_Value_Set(tick);
5484 }
5485 
5501 {
5502  CCU6_T13_Period_Value_Set((uint16)((uint32)CCU6_T13_CLK * us));
5503 }
5504 
5520 {
5522 }
5523 
5543 {
5544  bool res = false;
5545 
5546  if (CCU6_T13_Run_Sts() == (uint8)1)
5547  {
5548  res = true;
5549  }
5550 
5551  return (res);
5552 }
5553 
5569 {
5570  /* Set trigger mask */
5571  Field_Wrt16(&CCU6->TCTR2.reg, 0, (uint16)0xFFFF, Mask);
5572 }
5573 
5589 {
5590  if (Compare < CCU6_T13_Period_Value_Get())
5591  {
5592  /* Set only the requested compare value if no period change is needed */
5593  CCU6_Ch3_Value_Set(Compare);
5594  }
5595  else
5596  {
5597  /* Period value < compare value ? --> increase the period value */
5598  if (Compare <= (uint16)0xFFFE)
5599  {
5600  /* Set requested compare value */
5601  CCU6_Ch3_Value_Set(Compare);
5602  /* increase period value to ensure the compare match */
5603  CCU6_T13_Period_Value_Set((Compare + 1u));
5604  }
5605  else
5606  {
5607  /* Requested value is not possible */
5608  /* Set the highest possible values that ensure a compare match*/
5609  CCU6_Ch3_Value_Set((uint16)0xFFFE);
5611  }
5612  }
5613 
5614  /* Enable shadow transfer */
5615  CCU6_T13_Str_En();
5616 }
5617 
5633 {
5634  Field_Wrt16(&CCU6->TCTR4.reg, 0, (uint16)0xFFFF, Mask);
5635 }
5636 
5654 {
5655  return (uint32)u16_Field_Rd16(&CCU6->CMPSTAT.reg, (uint8)CCU6_CMPSTAT_CCPOS0_Pos, 0x38u);
5656 }
5657 
5675 {
5676  return u16_Field_Rd16(&CCU6->MCMOUT.reg, 0, (uint16)0xFFFF);
5677 }
5678 
5694 {
5695  Field_Wrt16(&CCU6->MCMOUTS.reg, 0, (uint16)0xFFFF, Patterns);
5696 }
5697 
5713 {
5714  Field_Wrt16(&CCU6->MCMCTR.reg, 0, (uint16)0xFFFF, Mode);
5715 }
5716 
5732 {
5733  Field_Wrt16(&CCU6->MODCTR.reg, 0, (uint16)0xFFFF, Mode);
5734 }
5735 
5751 {
5752  Field_Wrt16(&CCU6->IEN.reg, 0, (uint16)0xFFFF, Mask);
5753 }
5754 
5770 {
5771  Field_Wrt16(&CCU6->ISR.reg, 0, (uint16)0xFFFF, Mask);
5772 }
5773 
5774 #endif
INLINE uint16 CCU6_T13_Period_Value_Get(void)
reads Timer T13 Period Value.
Definition: ccu6.h:1516
INLINE void CCU6_T12_Modulation_En(uint16 ccu6_mask)
enables Timer T12 Modulation Configuration
Definition: ccu6.h:2341
INLINE void CCU6_MCM_Switch_T13_PM_Set(void)
sets T13 period-match Switching Mode.
Definition: ccu6.h:3209
INLINE void CCU6_Ch3c_Passive_State_After_Compare_Set(void)
sets Passive state for COUT63 after Compare.
Definition: ccu6.h:1766
INLINE void CCU6_T12_Period_Value_Set(uint16 t12pr)
sets Timer T12 Period Value.
Definition: ccu6.h:1127
INLINE void CCU6_T13_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Timer T13 Interrupts.
Definition: ccu6.h:4304
INLINE void CCU6_T13_PM_Int_Clr(void)
clears Interrupt for T13 Period-Match Flag.
Definition: ccu6.h:4549
INLINE void CCU6_StartTmr_T12(void)
Start CCU6 Timer T12.
Definition: ccu6.h:5320
INLINE void CCU6_StartTmr_T13(void)
Start CCU6 Timer T13.
Definition: ccu6.h:5337
INLINE void CCU6_MCM_Switch_Sync_direct_Sel(void)
sets Direct Switching Synchronization.
Definition: ccu6.h:3277
INLINE void CCU6_MCM_Hall_Str_HW_En(void)
enables Shadow Transfer Request for the Hall Pattern by Hardware.
Definition: ccu6.h:3054
INLINE void CCU6_Ch2_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 2 Interrupts.
Definition: ccu6.h:4229
INLINE void CCU6_CH1_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 1.
Definition: ccu6.h:4794
CCU6_Node_Sel
Definition: ccu6.h:401
@ CCU6_Node1
Definition: ccu6.h:403
@ CCU6_Node0
Definition: ccu6.h:402
@ CCU6_Node3
Definition: ccu6.h:405
@ CCU6_Node2
Definition: ccu6.h:404
INLINE uint8 CCU6_Ch1_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 1 Deadtime Status.
Definition: ccu6.h:1433
INLINE void CCU6_T13_Rst(void)
resets CCU6 T13.
Definition: ccu6.h:592
INLINE void CCU6_CH2_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 2.
Definition: ccu6.h:4884
INLINE void CCU6_T13_Period_Value_Set(uint16 t13pr)
sets Timer T13 Period Value.
Definition: ccu6.h:1535
INLINE void CCU6_T12_CM_CC62_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 2.
Definition: ccu6.h:3933
INLINE void CCU6_T12_PWMMode_Set(TCCU6_PWMMode mode)
sets mode of PWM signal for Channel0/1/2 and COUT0/1/2.
Definition: ccu6.h:1744
INLINE void CCU6_T13_CM_Int_Dis(void)
disables Interrupt for T13 Compare-Match.
Definition: ccu6.h:5042
CCU6_Pos1_Input
Definition: ccu6.h:215
@ CCU6_CCPOS1_BEMF
Definition: ccu6.h:221
@ CCU6_CCPOS1_1_P04
Definition: ccu6.h:217
@ CCU6_CCPOS1_0_P23
Definition: ccu6.h:216
@ CCU6_CCPOS1_2_P14
Definition: ccu6.h:218
INLINE void CCU6_Ch1_CapCom_Mode_Sel(uint16 msel61)
selects CCU6 T12 CH1 Capture/Compare Mode.
Definition: ccu6.h:1025
INLINE void CCU6_Passive_State_After_Compare_Sel(uint16 ccu6_mask)
Sets the passive state to "after" the compare value.
Definition: ccu6.h:2672
INLINE void CCU6_Passiv_Level_Ch3_Sel(uint16 lvl)
sets Passive State Level of Output COUT63.
Definition: ccu6.h:2929
INLINE void CCU6_Error_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Error Interrupts.
Definition: ccu6.h:4254
CCU6_T13HR_Input
Definition: ccu6.h:252
@ CCU6_T13HR_0_P01
Definition: ccu6.h:253
@ CCU6_T13HR_2_P22
Definition: ccu6.h:254
INLINE void CCU6_CH2_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 2.
Definition: ccu6.h:4907
INLINE void CCU6_Ch2t_Passive_Level_High_Set(void)
sets Passive High Level of CC62.
Definition: ccu6.h:2826
enum CCU6_T12_Ext_Input TCCU6_T12_Ext_Input
INLINE uint8 CCU6_T12_CM_CC60_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 0.
Definition: ccu6.h:3509
CCU6_T13RSEL
Definition: ccu6.h:368
@ CCU6_T13RSEL_Dis
Definition: ccu6.h:369
@ CCU6_T13RSEL_T13HR_Any
Definition: ccu6.h:372
@ CCU6_T13RSEL_T13HR_Fall
Definition: ccu6.h:371
@ CCU6_T13RSEL_T13HR_Rise
Definition: ccu6.h:370
INLINE uint8 CCU6_Trap_Flag_Int_Sts(void)
reads Trap Flag Status.
Definition: ccu6.h:3677
INLINE void CCU6_CH2_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 2.
Definition: ccu6.h:4862
INLINE void CCU6_T12_Single_Shot_En(void)
enables Timer T12 Single Shot.
Definition: ccu6.h:2229
INLINE void CCU6_Ch2_CapCom_Mode_Sel(uint16 msel62)
selects CCU6 T12 CH2 Capture/Compare Mode.
Definition: ccu6.h:1006
INLINE void CCU6_Ch2c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT62.
Definition: ccu6.h:2877
INLINE void CCU6_T12_Center_Aligned_Mode_En(void)
enables T12 Operating Center-aligned Mode.
Definition: ccu6.h:1994
INLINE void CCU6_CH0_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 0.
Definition: ccu6.h:4727
INLINE void CCU6_Trap_Flag_Int_Set(void)
sets Trap Flag.
Definition: ccu6.h:4048
INLINE uint32 CCU6_ReadHallReg(void)
Reads sampled Hall pattern from CCU6 CMPSTAT register.
Definition: ccu6.h:5653
INLINE void CCU6_CHE_Int_Clr(void)
clears Interrupt for Correct Hall Event flag.
Definition: ccu6.h:4593
INLINE void CCU6_MCM_PWM_Str_HW_En(void)
enables Shadow Transfer Request for MCMPS by Hardware.
Definition: ccu6.h:2982
void CCU6_Init(void)
Initializes the CCU6 module based on the Config Wizard for MOTIX MCU configuration.
INLINE void CCU6_MCM_PWM_Str_SW_En(void)
enables Shadow Transfer Request for MCMPS by Software.
Definition: ccu6.h:2965
INLINE void CCU6_Hall_Correct_Int_Set(void)
sets Interrupt for Correct Hall Event flag.
Definition: ccu6.h:4088
CCU6_Trap_Input
Definition: ccu6.h:192
@ CCU6_CTRAP_0_P24
Definition: ccu6.h:193
@ CCU6_CTRAP_1_P23
Definition: ccu6.h:194
INLINE void CCU6_T12_Ext_Input_Sel(uint16 t12ext)
selects Input of Extension for T12HR.
Definition: ccu6.h:914
INLINE void CCU6_T12_OM_Int_Set(void)
sets Interrupt for T12 One-Match Flag.
Definition: ccu6.h:3956
INLINE void CCU6_T13_Cnt_Input_Sel(uint16 iscnt13)
selects Input for T13 Counting.
Definition: ccu6.h:894
INLINE void CCU6_Trap_SW_Hall_Int_Set(void)
sets Interrupt for Trap SW Hall Event flag.
Definition: ccu6.h:4065
INLINE void CCU6_T12_CM_CC61_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 1.
Definition: ccu6.h:3841
INLINE void CCU6_Deadtime_Set(uint16 dtm)
sets CCU6 Timer T12 Deadtime.
Definition: ccu6.h:1287
INLINE void CCU6_MCM_Str_Int_Set(void)
sets Multi-Channel Mode Shadow Transfer Interrupt flag.
Definition: ccu6.h:4154
INLINE uint16 CCU6_T12_Period_Value_Get(void)
reads Timer T12 Period Value.
Definition: ccu6.h:1107
INLINE uint8 CCU6_T12_PM_Int_Sts(void)
reads Timer T12 Period-Match Flag Status.
Definition: ccu6.h:3605
INLINE uint8 CCU6_MCM_Idle_Int_Sts(void)
reads IDLE Status.
Definition: ccu6.h:3771
INLINE void CCU6_Ch2_Deadtime_En(void)
enables CCU6 Timer T12 Channel 2 Deadtime.
Definition: ccu6.h:1338
CCU6_T13ED
Definition: ccu6.h:346
@ CCU6_T13ED_No_Action
Definition: ccu6.h:347
@ CCU6_T13ED_T12_Up
Definition: ccu6.h:348
@ CCU6_T13ED_T12_Down
Definition: ccu6.h:349
@ CCU6_T13ED_T12_UpDown
Definition: ccu6.h:350
INLINE uint16 CCU6_Ch2_Value_Get(void)
reads Channel 2 Capture/Compare Value.
Definition: ccu6.h:1228
INLINE void CCU6_CCPOS0_Input_Sel(uint16 ispos0)
selects Input for CCPOS0.
Definition: ccu6.h:774
enum CCU6_Ch1_Input TCCU6_Ch1_Input
enum CCU6_MCM_SWSEL TCCU6_MCM_SWSEL
INLINE void CCU6_T13_Inv_Mod_En(void)
enables T13 inversion for further modulation.
Definition: ccu6.h:1805
INLINE uint16 CCU6_ReadMultichannelPatterns(void)
Reads actual Hall and PWM patterns for Multi-Channel Mode.
Definition: ccu6.h:5674
CCU6_T12_Cnt_Input
Definition: ccu6.h:261
@ CCU6_T12HR_Rising_Edge
Definition: ccu6.h:264
@ CCU6_TCTR4_T12CNT
Definition: ccu6.h:263
@ CCU6_T12_Prescaler
Definition: ccu6.h:262
@ CCU6_T12HR_Falling_Edge
Definition: ccu6.h:265
INLINE void CCU6_Ch1_Input_Sel(uint16 iscc61)
selects Input for CC61.
Definition: ccu6.h:717
INLINE void CCU6_T12_CM_CC60_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 0.
Definition: ccu6.h:3818
INLINE void CCU6_CH1_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 1.
Definition: ccu6.h:4749
INLINE void CCU6_T12_OM_Int_En(void)
enables Interrupt for T12 One-Match.
Definition: ccu6.h:4929
INLINE uint8 CCU6_Ch2_CompState_Sts(void)
reads CC62 Capture/Compare State.
Definition: ccu6.h:1644
INLINE void CCU6_EnableST_T13(void)
Enable T13 Shadow Transfer.
Definition: ccu6.h:5405
INLINE void CCU6_T12_Edge_Aligned_Mode_En(void)
enables T12 Operating Edge-aligned Mode.
Definition: ccu6.h:1977
INLINE void CCU6_MCM_Switch_Sel(uint16 swsel)
selects Switching Mode.
Definition: ccu6.h:3158
INLINE uint8 CCU6_Hall_Wrong_Int_Sts(void)
reads Wrong Hall Event Status.
Definition: ccu6.h:3749
INLINE void CCU6_Trap_HW_Clr_En(void)
enables Hardware reset of the Trap Mode.
Definition: ccu6.h:2534
INLINE void CCU6_Ch0c_Passive_Level_High_Set(void)
sets Passive High Level of COUT60.
Definition: ccu6.h:2724
CCU6_T13_Ext_Input
Definition: ccu6.h:292
@ CCU6_T13HR_D_A
Definition: ccu6.h:293
@ CCU6_T13HR_H_E
Definition: ccu6.h:294
enum CCU6_Node_Sel TCCU6_Node_Sel
INLINE void CCU6_Multi_Ch_PWM_Shadow_Reg_Load(uint16 ccu6_mask)
sets Multi-Channel PWM Pattern Shadow.
Definition: ccu6.h:2948
INLINE void CCU6_CH2_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 2.
Definition: ccu6.h:4839
INLINE void CCU6_T13_Str_En(void)
enables T13 Shadow Transfer.
Definition: ccu6.h:628
CCU6_Ch1_Input
Definition: ccu6.h:175
@ CCU6_CC61_0_P10
Definition: ccu6.h:176
enum CCU6_T12_Cnt_Input TCCU6_T12_Cnt_Input
INLINE uint16 CCU6_T12_Count_Value_Get(void)
reads Timer T12 Counter Value.
Definition: ccu6.h:1065
INLINE void CCU6_STR_Int_Dis(void)
disables Multi-Channel Mode Shadow Transfer Interrupt.
Definition: ccu6.h:5267
INLINE void CCU6_T12_PM_Int_Set(void)
sets Interrupt for T12 Period-Match Flag.
Definition: ccu6.h:3979
INLINE void CCU6_Ch0_Input_Sel(uint16 iscc60)
selects Input for CC60.
Definition: ccu6.h:698
CCU6_MCM_SWSEL
Definition: ccu6.h:388
@ CCU6_SWSEL_T12_PM
Definition: ccu6.h:394
@ CCU6_SWSEL_T12_Ch1_CM
Definition: ccu6.h:393
@ CCU6_SWSEL_T13_PM
Definition: ccu6.h:391
@ CCU6_SWSEL_No_Action
Definition: ccu6.h:389
@ CCU6_SWSEL_Correct_Hall
Definition: ccu6.h:390
@ CCU6_SWSEL_T12_OM
Definition: ccu6.h:392
INLINE void CCU6_Trap_Pin_En(void)
enables the trap functionality based on the input pin CTRAP.
Definition: ccu6.h:2602
INLINE void CCU6_T12_Str_Dis(void)
disables T12 Shadow Transfer.
Definition: ccu6.h:541
INLINE uint8 CCU6_Ch0_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 0 Deadtime Status.
Definition: ccu6.h:1411
INLINE void CCU6_TRAP_Int_Dis(void)
disables Interrupt for Trap Flag.
Definition: ccu6.h:5132
INLINE uint8 CCU6_T13_CM_Int_Sts(void)
reads Timer T13 Compare-Match Flag Status.
Definition: ccu6.h:3629
INLINE uint8 CCU6_T12_Run_Sts(void)
reads Timer T12 Run Bit.
Definition: ccu6.h:2124
INLINE void CCU6_WHE_Int_Clr(void)
clears Interrupt for Wrong Hall Event flag.
Definition: ccu6.h:4615
INLINE void CCU6_Trap_T13_Dis(void)
disables The trap functionality for T13.
Definition: ccu6.h:2585
INLINE void CCU6_MCM_Idle_Int_Set(void)
sets Interrupt for IDLE flag.
Definition: ccu6.h:4131
INLINE void CCU6_CCPOS1_Input_Sel(uint16 ispos1)
selects Input for CCPOS1.
Definition: ccu6.h:793
enum CCU6_Ch2_Input TCCU6_Ch2_Input
INLINE void CCU6_T12_PM_Int_Dis(void)
disables Interrupt for T12 Period-Match.
Definition: ccu6.h:4997
enum CCU6_T13_Cnt_Input TCCU6_T13_Cnt_Input
INLINE void CCU6_EnableST_T12(void)
Enable T12 Shadow Transfer.
Definition: ccu6.h:5388
INLINE void CCU6_CH1_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 1.
Definition: ccu6.h:4417
INLINE void CCU6_CH0_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 0.
Definition: ccu6.h:4373
INLINE void CCU6_T13_Trig_Event_Sel(uint16 t13tec)
selects Timer T13 Trigger Event Control.
Definition: ccu6.h:2265
INLINE void CCU6_CH1_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 1.
Definition: ccu6.h:4395
enum CCU6_HSYNC TCCU6_HSYNC
INLINE void CCU6_T13_Ext_Run_Sel(uint16 t13rsel)
selects Timer T13 External Run.
Definition: ccu6.h:2322
INLINE uint8 CCU6_Hall_Ch1_Sts(void)
reads Sampled Hall Pattern Bit 1.
Definition: ccu6.h:1711
INLINE void CCU6_T13_PM_Int_Set(void)
sets Interrupt for T13 Period-Match Flag.
Definition: ccu6.h:4025
INLINE void CCU6_T12_CM_CC62_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 2.
Definition: ccu6.h:3864
INLINE uint8 CCU6_Deadtime_Get(void)
reads CCU6 Timer T12 Deadtime.
Definition: ccu6.h:1268
INLINE void CCU6_T12_Ext_Run_Sel(uint16 t12rsel)
selects Timer T12 External Run.
Definition: ccu6.h:2303
INLINE uint8 CCU6_T13_PM_Int_Sts(void)
reads Timer T13 Period-Match Flag Status.
Definition: ccu6.h:3653
INLINE void CCU6_Deadtime_Rst(void)
resets CCU6 T12 Dead-Time Counter.
Definition: ccu6.h:488
INLINE void CCU6_Hall_Synchronizaion_Sel(uint16 hsync)
selects Hall Synchronization.
Definition: ccu6.h:987
INLINE void CCU6_Trap_T13_En(void)
enables the trap functionality for T13.
Definition: ccu6.h:2568
INLINE void CCU6_Ch0t_Passive_Level_High_Set(void)
sets Passive High Level of CC60.
Definition: ccu6.h:2690
INLINE void CCU6_Hall_Correct_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for CHE Interrupts.
Definition: ccu6.h:4329
INLINE void CCU6_T13_Compare_Out_En(void)
enables Compare Timer T13 Output
Definition: ccu6.h:2449
CCU6_T12HR_Input
Definition: ccu6.h:243
@ CCU6_T12HR_2_P20
Definition: ccu6.h:245
@ CCU6_T12HR_0_P00
Definition: ccu6.h:244
INLINE void CCU6_MCM_Switch_T12_ON_Set(void)
sets T12 one-match Switching Mode.
Definition: ccu6.h:3226
INLINE uint8 CCU6_T12_OM_Int_Sts(void)
reads Timer T12 One-Match Flag Status.
Definition: ccu6.h:3581
INLINE void CCU6_MCM_Current_Hall_Shadow_Reg_Load(uint16 mcm_mask_ccpos)
sets Current Hall Pattern Shadow of CCPOSx.
Definition: ccu6.h:3020
INLINE void CCU6_T13_Count_Value_Set(uint16 t13cv)
sets Timer T13 Counter Value.
Definition: ccu6.h:1495
enum CCU6_T13ED TCCU6_T13ED
INLINE void CCU6_T13_PM_Int_En(void)
enables Interrupt for T13 Period-Match.
Definition: ccu6.h:5064
INLINE uint16 CCU6_Ch1_Value_Get(void)
reads Channel 1 Capture/Compare Value.
Definition: ccu6.h:1188
INLINE void CCU6_MCM_Switch_CorrectHall_Set(void)
sets Correct Hall Switching Mode.
Definition: ccu6.h:3192
CCU6_Ch0_Input
Definition: ccu6.h:166
@ CCU6_CC60_0_P04
Definition: ccu6.h:167
@ CCU6_CC60_1_P23
Definition: ccu6.h:168
INLINE void CCU6_CCPOS2_Input_Sel(uint16 ispos2)
selects Input for CCPOS2.
Definition: ccu6.h:812
INLINE void CCU6_T12_Prescaler_En(void)
enables additional prescaler for Timer T12.
Definition: ccu6.h:2051
INLINE void CCU6_Ch2_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 2 Deadtime.
Definition: ccu6.h:1389
INLINE void CCU6_SetT12T13ControlBits(uint16 Mask)
Sets write-only control bits for T12 and/or T13 timer.
Definition: ccu6.h:5632
INLINE void CCU6_Trap_SW_Clr_En(void)
enables Software reset of the Trap Mode.
Definition: ccu6.h:2551
enum CCU6_Ch0_Input TCCU6_Ch0_Input
INLINE void CCU6_Ch2t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC62.
Definition: ccu6.h:2843
INLINE bool CCU6_IsT13Running(void)
reads Timer T13 Run Bit.
Definition: ccu6.h:5542
INLINE void CCU6_WHE_Int_Dis(void)
disables Interrupt for Wrong Hall Event.
Definition: ccu6.h:5222
INLINE uint8 CCU6_T12_CM_CC61_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 1.
Definition: ccu6.h:3533
INLINE void CCU6_Ch0_Deadtime_En(void)
enables CCU6 Timer T12 Channel 0 Deadtime.
Definition: ccu6.h:1304
INLINE uint8 CCU6_T13_Str_Sts(void)
reads Timer T13 Shadow Transfer Enable Bit.
Definition: ccu6.h:2212
INLINE void CCU6_Ch2_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 2 (CC62ST) by Software.
Definition: ccu6.h:1943
INLINE void CCU6_TRAP_Int_En(void)
enables Interrupt for Trap Flag.
Definition: ccu6.h:5109
INLINE void CCU6_WriteMultichannelPatterns(uint16 Patterns)
Writes Hall and/or PWM patterns for Multi-Channel Mode to shadow register.
Definition: ccu6.h:5693
CCU6_Pos0_Input
Definition: ccu6.h:201
@ CCU6_CCPOS0_3_P20
Definition: ccu6.h:204
@ CCU6_CCPOS0_1_P03
Definition: ccu6.h:202
@ CCU6_CCPOS0_2_P13
Definition: ccu6.h:203
@ CCU6_CCPOS0_BEMF
Definition: ccu6.h:207
INLINE void CCU6_Ch0_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 0 for CC60ST by Software.
Definition: ccu6.h:1909
INLINE void CCU6_T12_Prescaler_Dis(void)
disables additional prescaler for Timer T12.
Definition: ccu6.h:2068
INLINE void CCU6_Hall_Delay_Bypass_Dis(void)
disables Hall Delay Bypass.
Definition: ccu6.h:968
INLINE void CCU6_Ch1t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC61.
Definition: ccu6.h:2775
INLINE uint16 CCU6_T13_Count_Value_Get(void)
reads Timer T13 Counter Value.
Definition: ccu6.h:1476
INLINE uint8 CCU6_MCM_Expected_Hall_Sts(void)
reads Expected Hall Pattern of CCPOSx.
Definition: ccu6.h:3118
enum CCU6_T13TEC TCCU6_T13TEC
enum CCU6_T13RSEL TCCU6_T13RSEL
INLINE uint8 CCU6_T12_Count_Dir_Sts(void)
reads Count Direction of Timer T12 Bit.
Definition: ccu6.h:2168
CCU6_Pos2_Input
Definition: ccu6.h:229
@ CCU6_CCPOS2_2_P12
Definition: ccu6.h:231
@ CCU6_CCPOS2_1_P02
Definition: ccu6.h:230
@ CCU6_CCPOS2_3_P22
Definition: ccu6.h:232
@ CCU6_CCPOS2_BEMF
Definition: ccu6.h:235
INLINE uint8 CCU6_Ch0_CompState_Sts(void)
reads CC60 Capture/Compare State.
Definition: ccu6.h:1598
enum CCU6_PSL63 TCCU6_PSL63
enum CCU6_Pos1_Input TCCU6_Pos1_Input
INLINE void CCU6_Ch0t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC60.
Definition: ccu6.h:2707
INLINE void CCU6_STR_Int_Clr(void)
clears Multi-Channel Mode Shadow Transfer Interrupt flag.
Definition: ccu6.h:4637
INLINE void CCU6_Ch3c_Passive_State_Before_Compare_Set(void)
sets Passive state for COUT63 Before Compare.
Definition: ccu6.h:1787
CCU6_T13_Cnt_Input
Definition: ccu6.h:272
@ CCU6_TCTR4_T13CNT
Definition: ccu6.h:274
@ CCU6_T13HR_Falling_Edge
Definition: ccu6.h:276
@ CCU6_T13HR_Rising_Edge
Definition: ccu6.h:275
@ CCU6_T13_Prescaler
Definition: ccu6.h:273
INLINE void CCU6_T12_Str_En(void)
enables T12 Shadow Transfer.
Definition: ccu6.h:524
enum CCU6_Clk_Prescaler TCCU6_Clk_Prescaler
INLINE void CCU6_CH1_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 1.
Definition: ccu6.h:4817
INLINE void CCU6_T13_CM_Int_En(void)
enables Interrupt for T13 Compare-Match.
Definition: ccu6.h:5019
INLINE void CCU6_LoadShadowRegister_CC62(uint16 tick)
Load Channel 2 compare value to the shadow register.
Definition: ccu6.h:5462
INLINE void CCU6_MCM_Str_T13_Up_Cnt_En(void)
enables Shadow Transfer for T13 Upcounting.
Definition: ccu6.h:3396
INLINE uint8 CCU6_T13_Run_Sts(void)
reads Timer T13 Run Bit.
Definition: ccu6.h:2190
INLINE uint8 CCU6_MCM_PWM_Str_Req_Sts(void)
reads Reminder Flag Status.
Definition: ccu6.h:3097
INLINE uint8 CCU6_Hall_Ch2_Sts(void)
reads Sampled Hall Pattern Bit 2.
Definition: ccu6.h:1733
INLINE void CCU6_MCM_Str_T12_Down_Cnt_Dis(void)
disables Shadow Transfer for T12 Downcounting.
Definition: ccu6.h:3379
INLINE void CCU6_T13_Compare_Out_Dis(void)
disables Compare Timer T13 Output
Definition: ccu6.h:2466
INLINE void CCU6_T12_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Timer T12 Interrupts.
Definition: ccu6.h:4279
enum CCU6_T13HR_Input TCCU6_T13HR_Input
enum CCU6_Pos0_Input TCCU6_Pos0_Input
INLINE void CCU6_LoadPeriodRegister_T13_Tick(uint16 tick)
Load Timer13 Period Register as Time Value.
Definition: ccu6.h:5519
INLINE void CCU6_Ch1t_Passive_Level_High_Set(void)
sets Passive High Level of CC61.
Definition: ccu6.h:2758
INLINE void CCU6_T13HR_Input_Sel(uint16 ist13hr)
selects Input for T13HR.
Definition: ccu6.h:852
INLINE void CCU6_MCM_Hall_Str_SW_En(void)
enables Shadow Transfer Request for the Hall Pattern by Software.
Definition: ccu6.h:3037
INLINE void CCU6_MCM_Switch_NoTrigger_Set(void)
sets No Trigger Switching Mode.
Definition: ccu6.h:3175
INLINE void CCU6_T12_PM_Int_En(void)
enables Interrupt for T12 Period-Match.
Definition: ccu6.h:4974
INLINE void CCU6_T13_Str_Dis(void)
disables T13 Shadow Transfer.
Definition: ccu6.h:645
INLINE void CCU6_T12_Start(void)
starts CCU6 T12.
Definition: ccu6.h:454
INLINE void CCU6_CH0_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 0.
Definition: ccu6.h:4682
INLINE void CCU6_T12HR_Input_Sel(uint16 ist12hr)
selects Input for T12HR.
Definition: ccu6.h:832
INLINE void CCU6_Ch2_Value_Set(uint16 cc62sr)
sets Channel 2 Capture/Compare Value.
Definition: ccu6.h:1247
CCU6_T12_Ext_Input
Definition: ccu6.h:283
@ CCU6_T12HR_D_A
Definition: ccu6.h:284
@ CCU6_T12HR_H_E
Definition: ccu6.h:285
INLINE void CCU6_T13_CM_Int_Clr(void)
clears Interrupt for T13 Compare-Match Flag.
Definition: ccu6.h:4527
INLINE uint16 CCU6_Ch3_Value_Get(void)
reads Channel CC63 Compare Value.
Definition: ccu6.h:1556
INLINE void CCU6_Ch0_CapCom_Mode_Sel(uint16 msel60)
selects CCU6 T12 CH0 Capture/Compare Mode.
Definition: ccu6.h:1044
INLINE void CCU6_Ch1_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 1 Deadtime.
Definition: ccu6.h:1372
INLINE void CCU6_T12_T13_Str_En(void)
enables T12 and T13 Shadow Transfer.
Definition: ccu6.h:662
INLINE void CCU6_CH0_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 0.
Definition: ccu6.h:4704
INLINE void CCU6_Ch0_CompState_Set(void)
sets Capture/Compare Status Modification Bit 0 for (CC60ST) by Software.
Definition: ccu6.h:1841
INLINE void CCU6_T13_CM_Int_Set(void)
sets Interrupt for T13 Compare-Match Flag.
Definition: ccu6.h:4002
INLINE void CCU6_EnableInt(uint16 Mask)
Enables/disables interrupt(s).
Definition: ccu6.h:5750
CCU6_T12RSEL
Definition: ccu6.h:357
@ CCU6_T12RSEL_T12HR_Fall
Definition: ccu6.h:360
@ CCU6_T12RSEL_T12HR_Rise
Definition: ccu6.h:359
@ CCU6_T12RSEL_Dis
Definition: ccu6.h:358
@ CCU6_T12RSEL_T12HR_Any
Definition: ccu6.h:361
INLINE void CCU6_Ch3_Value_Set(uint16 cc63sr)
sets Channel CC63 Compare Value.
Definition: ccu6.h:1575
INLINE uint8 CCU6_Ch2_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 2 Deadtime Status.
Definition: ccu6.h:1455
INLINE void CCU6_Ch1c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT61.
Definition: ccu6.h:2809
INLINE void CCU6_T12_OM_Int_Clr(void)
clears Interrupt for T12 One-Match Flag.
Definition: ccu6.h:4483
INLINE uint8 CCU6_Ch1_CompState_Sts(void)
reads CC61 Capture/Compare State.
Definition: ccu6.h:1621
CCU6_HSYNC
Definition: ccu6.h:301
@ CCU6_T12_PM
Definition: ccu6.h:306
@ CCU6_T13_PM
Definition: ccu6.h:304
@ CCU6_CCPOS0x_Any_Edge
Definition: ccu6.h:302
@ CCU6_T12_OM
Definition: ccu6.h:307
@ CCU6_T12_CM_Ch1_up
Definition: ccu6.h:308
@ CCU6_HW_Hall_Sampling_Off
Definition: ccu6.h:305
@ CCU6_T13_CM
Definition: ccu6.h:303
@ CCU6_T12_CM_Ch1_down
Definition: ccu6.h:309
INLINE void CCU6_Ch2_CompState_Set(void)
sets Capture/Compare Status Modification Bit 2 for (CC62ST) by Software.
Definition: ccu6.h:1875
INLINE void CCU6_CH1_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 1.
Definition: ccu6.h:4772
CCU6_T13TEC
Definition: ccu6.h:331
@ CCU6_T13TEC_CCPOSx
Definition: ccu6.h:339
@ CCU6_T13TEC_T12_CM_Ch0
Definition: ccu6.h:333
@ CCU6_T13TEC_T12_PM
Definition: ccu6.h:337
@ CCU6_T13TEC_T12_CM_Chx
Definition: ccu6.h:336
@ CCU6_T13TEC_T12_CM_Ch2
Definition: ccu6.h:335
@ CCU6_T13TEC_No_Trigger
Definition: ccu6.h:332
@ CCU6_T13TEC_T12_CM_Ch1
Definition: ccu6.h:334
@ CCU6_T13TEC_T12_ZM
Definition: ccu6.h:338
INLINE uint8 CCU6_MCM_Current_Hall_Sts(void)
reads Current Hall Pattern of CCPOSx.
Definition: ccu6.h:3139
INLINE void CCU6_T13_PM_Int_Dis(void)
disables Interrupt for T13 Period-Match.
Definition: ccu6.h:5087
INLINE void CCU6_Trap_Channel_En(uint16 ccu6_mask)
enables the trap functionality of a corresponding output.
Definition: ccu6.h:2638
INLINE void CCU6_ConfigureGlobalModulation(uint16 Mode)
Sets global modulation control register.
Definition: ccu6.h:5731
INLINE uint16 CCU6_Ch0_Value_Get(void)
reads Channel 0 Capture/Compare Value.
Definition: ccu6.h:1148
INLINE void CCU6_SetT13Trigger(uint16 Mask)
Sets trigger event for the T13 timer.
Definition: ccu6.h:5568
INLINE void CCU6_Trap_T13_ZM_Exit_En(void)
enables T13 zero-match Trap Mode
Definition: ccu6.h:2500
INLINE void CCU6_ConfigureMultichannelModulation(uint16 Mode)
Sets Multi-Channel Mode control register.
Definition: ccu6.h:5712
INLINE void CCU6_T13_Start(void)
starts CCU6 T13.
Definition: ccu6.h:575
INLINE void CCU6_Ch0_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 0 Deadtime.
Definition: ccu6.h:1355
INLINE void CCU6_Ch1_Value_Set(uint16 cc61sr)
sets Channel 1 Capture/Compare Value.
Definition: ccu6.h:1207
INLINE void CCU6_ClearIntStatus(uint16 Mask)
Clears interrupt status bit(s).
Definition: ccu6.h:5769
CCU6_Ch2_Input
Definition: ccu6.h:183
@ CCU6_CC62_0_P13
Definition: ccu6.h:184
@ CCU6_CC62_2_P22
Definition: ccu6.h:185
INLINE void CCU6_T12_CM_CC61_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 1.
Definition: ccu6.h:3910
INLINE void CCU6_Ch3_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 3 (CC63ST) by Software.
Definition: ccu6.h:1960
INLINE void CCU6_TRAP_Int_Clr(void)
clears Trap Flag.
Definition: ccu6.h:4571
INLINE void CCU6_Trap_Asynch_Exit_En(void)
enables Trap Immediately without any synchronization to T12 or T13.
Definition: ccu6.h:2517
INLINE void CCU6_LoadPeriodRegister_T13_Time(uint32 us)
Load Timer13 Period Register as Time Value.
Definition: ccu6.h:5500
INLINE void CCU6_T13_Trig_Event_Dir_Sel(uint16 t13ted)
selects Timer T13 Trigger Event Direction.
Definition: ccu6.h:2284
INLINE void CCU6_T12_CM_CC60_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 0.
Definition: ccu6.h:3887
CCU6_PSL63
Definition: ccu6.h:379
@ CCU6_PSL63_Low
Definition: ccu6.h:380
@ CCU6_PSL63_High
Definition: ccu6.h:381
INLINE void CCU6_T12_Cnt(void)
counts 1 step for CCU6 T12 Event.
Definition: ccu6.h:507
INLINE uint8 CCU6_T12_Str_Sts(void)
reads Timer T12 Shadow Transfer Enable Bit.
Definition: ccu6.h:2146
INLINE void CCU6_MCM_Str_T12_Up_Cnt_Dis(void)
disables Shadow Transfer for T12 Upcounting.
Definition: ccu6.h:3345
INLINE uint8 CCU6_Hall_Correct_Int_Sts(void)
reads Correct Hall Event Status.
Definition: ccu6.h:3725
enum CCU6_T13_Ext_Input TCCU6_T13_Ext_Input
INLINE void CCU6_Ch1_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 1 Interrupts.
Definition: ccu6.h:4204
INLINE void CCU6_Trap_T12_ZM_Exit_En(void)
enables T12 zero-match Trap Mode
Definition: ccu6.h:2483
INLINE void CCU6_Passive_Level_High_Sel(uint16 ccu6_mask)
sets Compare Corresponding Outputs Passive High Level.
Definition: ccu6.h:2910
INLINE void CCU6_CH0_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 0.
Definition: ccu6.h:4659
enum CCU6_T12RSEL TCCU6_T12RSEL
INLINE uint8 CCU6_T12_CM_CC61_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 1.
Definition: ccu6.h:3461
INLINE uint8 CCU6_MCM_PWM_Pattern_Sts(void)
reads Multi-Channel PWM Pattern.
Definition: ccu6.h:3075
INLINE void CCU6_Ch1c_Passive_Level_High_Set(void)
sets Passive High Level of COUT61.
Definition: ccu6.h:2792
INLINE void CCU6_StopTmr_T13(void)
Stops CCU6 Timer T13.
Definition: ccu6.h:5371
INLINE uint8 CCU6_T12_CM_CC62_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 2.
Definition: ccu6.h:3557
INLINE void CCU6_Ch1_Deadtime_En(void)
enables CCU6 Timer T12 Channel 1 Deadtime.
Definition: ccu6.h:1321
INLINE uint8 CCU6_Hall_Ch0_Sts(void)
reads Sampled Hall Pattern Bit 0.
Definition: ccu6.h:1689
INLINE void CCU6_CH2_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 2.
Definition: ccu6.h:4461
INLINE void CCU6_MCM_Str_T12_Up_Cnt_En(void)
enables Shadow Transfer for T12 Upcounting.
Definition: ccu6.h:3328
INLINE void CCU6_Multi_Ch_Mode_En(void)
enables Multi-Channel Mode
Definition: ccu6.h:2415
INLINE void CCU6_MCM_Str_T13_Up_Cnt_Dis(void)
disables Shadow Transfer for T13 Upcounting.
Definition: ccu6.h:3413
INLINE void CCU6_T12_PM_Int_Clr(void)
clears Interrupt for T12 Period-Match Flag.
Definition: ccu6.h:4505
INLINE void CCU6_LoadShadowRegister_CC60(uint16 tick)
Load Channel 0 compare value to the shadow register.
Definition: ccu6.h:5424
INLINE void CCU6_T13_Inv_Mod_Dis(void)
disables T13 inversion for further modulation.
Definition: ccu6.h:1823
INLINE void CCU6_T12_OM_Int_Dis(void)
disables Interrupt for T12 One-Match.
Definition: ccu6.h:4952
INLINE void CCU6_MCM_Switch_Sync_T13_ZM_Sel(void)
sets T13 zero-match Switching Synchronization.
Definition: ccu6.h:3294
INLINE void CCU6_LoadShadowRegister_CC61(uint16 tick)
Load Channel 1 compare value to the shadow register.
Definition: ccu6.h:5443
INLINE void CCU6_Ch2_Input_Sel(uint16 iscc62)
selects Input for CC62.
Definition: ccu6.h:736
INLINE void CCU6_Ch3_CompState_Set(void)
sets Capture/Compare Status Modification Bit 3 for (CC63ST) by Software.
Definition: ccu6.h:1892
INLINE void CCU6_CHE_Int_En(void)
enables Interrupt for Correct Hall Event.
Definition: ccu6.h:5154
enum CCU6_T12HR_Input TCCU6_T12HR_Input
INLINE void CCU6_MCM_Str_T12_Down_Cnt_En(void)
enables Shadow Transfer for T12 Downcounting.
Definition: ccu6.h:3362
INLINE void CCU6_CHE_Int_Dis(void)
disables Interrupt for Correct Hall Event.
Definition: ccu6.h:5177
INLINE void CCU6_T13_Modulation_En(uint16 ccu6_mask)
enables Timer T13 Modulation Configuration
Definition: ccu6.h:2379
INLINE void CCU6_T13_Ext_Input_Sel(uint16 t13ext)
selects Input of Extension for T13HR.
Definition: ccu6.h:934
INLINE void CCU6_Hall_Delay_Bypass_En(void)
enables Hall Delay Bypass.
Definition: ccu6.h:951
INLINE void CCU6_Hall_Wrong_Int_Set(void)
sets Interrupt for Wrong Hall Event flag.
Definition: ccu6.h:4111
INLINE void CCU6_T12_Rst(void)
resets CCU6 T12.
Definition: ccu6.h:471
INLINE void CCU6_CH0_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 0.
Definition: ccu6.h:4351
INLINE void CCU6_Ch1_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 1 for CC61ST by Software.
Definition: ccu6.h:1926
INLINE uint8 CCU6_T12_CM_CC60_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 0.
Definition: ccu6.h:3437
INLINE uint8 CCU6_Ch3_CompState_Sts(void)
reads CC63 Capture/Compare State.
Definition: ccu6.h:1667
enum CCU6_Trap_Input TCCU6_Trap_Input
INLINE void CCU6_T12_Single_Shot_Dis(void)
disables Timer T12 Single Shot.
Definition: ccu6.h:2246
INLINE void CCU6_T13_Prescaler_En(void)
enables additional prescaler for Timer T13.
Definition: ccu6.h:2085
INLINE void CCU6_Ch1_CompState_Set(void)
sets Capture/Compare Status Modification Bit 1 for (CC61ST) by Software.
Definition: ccu6.h:1858
INLINE void CCU6_T13_Prescaler_Dis(void)
disables additional prescaler for Timer T13.
Definition: ccu6.h:2102
INLINE void CCU6_Trap_Input_Sel(uint16 istrp)
selects Input for CTRAP.
Definition: ccu6.h:755
INLINE void CCU6_T13_Cnt(void)
counts 1 step for CCU6 T13 Event.
Definition: ccu6.h:611
enum CCU6_PWMMode TCCU6_PWMMode
INLINE void CCU6_CH2_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 2.
Definition: ccu6.h:4439
INLINE void CCU6_T13_Stop(void)
stops CCU6 T13.
Definition: ccu6.h:558
INLINE void CCU6_Multi_Ch_Mode_Dis(void)
disables Multi-Channel Mode
Definition: ccu6.h:2432
INLINE void CCU6_T12_Stop(void)
stops CCU6 T12.
Definition: ccu6.h:437
INLINE uint8 CCU6_T12_CM_CC62_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 2.
Definition: ccu6.h:3485
INLINE void CCU6_Trap_Pin_Dis(void)
disables the trap functionality based on the input pin CTRAP.
Definition: ccu6.h:2619
INLINE void CCU6_Ch0_Value_Set(uint16 cc60sr)
sets Channel 0 Capture/Compare Value.
Definition: ccu6.h:1167
INLINE uint8 CCU6_MCM_Str_Int_Sts(void)
reads Multi-Channel Mode Shadow Transfer Request Status.
Definition: ccu6.h:3795
INLINE uint8 CCU6_Trap_State_Int_Sts(void)
reads Trap Status.
Definition: ccu6.h:3701
INLINE void CCU6_MCM_Expected_Hall_Shadow_Reg_Load(uint16 mcm_mask_ccpos)
sets Expected Hall Pattern Shadow of CCPOSx.
Definition: ccu6.h:3001
INLINE void CCU6_SetT13Compare(uint16 Compare)
Sets compare value for the T13 timer.
Definition: ccu6.h:5588
INLINE void CCU6_Ch0c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT60.
Definition: ccu6.h:2741
INLINE void CCU6_StopTmr_T12(void)
Stop CCU6 Timer T12.
Definition: ccu6.h:5354
CCU6_PWMMode
Definition: ccu6.h:414
@ CCU6_T12_ActiveRightAligned
Definition: ccu6.h:416
@ CCU6_T12_ActiveCenterAlignedInverted
Definition: ccu6.h:418
@ CCU6_T12_ActiveLeftAligned
Definition: ccu6.h:415
@ CCU6_T12_ActiveCenterAligned
Definition: ccu6.h:417
INLINE void CCU6_T12_Modulation_Dis(uint16 ccu6_mask)
disables Timer T12 Modulation Configuration
Definition: ccu6.h:2360
INLINE void CCU6_T13_Modulation_Dis(uint16 ccu6_mask)
disables Timer T13 Modulation Configuration
Definition: ccu6.h:2398
INLINE void CCU6_STR_Int_En(void)
enables Multi-Channel Mode Shadow Transfer Interrupt.
Definition: ccu6.h:5244
INLINE void CCU6_MCM_Switch_T12_PM_Set(void)
sets T12 period-match Switching Mode.
Definition: ccu6.h:3260
CCU6_Clk_Prescaler
Definition: ccu6.h:316
@ CCU6_Clk_Div_16
Definition: ccu6.h:321
@ CCU6_Clk_Div_64
Definition: ccu6.h:323
@ CCU6_Clk_Div_2
Definition: ccu6.h:318
@ CCU6_Clk_Div_4
Definition: ccu6.h:319
@ CCU6_Clk_Div_128
Definition: ccu6.h:324
@ CCU6_Clk_Div_1
Definition: ccu6.h:317
@ CCU6_Clk_Div_8
Definition: ccu6.h:320
@ CCU6_Clk_Div_32
Definition: ccu6.h:322
INLINE void CCU6_T12_Clk_Sel(uint16 t12clk)
selects Timer T12 Input Clock.
Definition: ccu6.h:2014
INLINE void CCU6_MCM_Switch_Sync_T12_ZM_Sel(void)
sets T12 zero-match Switching Synchronization.
Definition: ccu6.h:3311
INLINE void CCU6_T12_Cnt_Input_Sel(uint16 iscnt12)
selects Input for T12 Counting.
Definition: ccu6.h:873
INLINE void CCU6_T12_Count_Value_Set(uint16 t12cv)
sets Timer T12 Counter Value.
Definition: ccu6.h:1085
enum CCU6_Pos2_Input TCCU6_Pos2_Input
INLINE void CCU6_T13_Clk_Sel(uint16 t13clk)
selects Timer T13 Input Clock.
Definition: ccu6.h:2034
INLINE void CCU6_MCM_Switch_T12_Ch1_CM_Set(void)
sets T12 channel1 compare-match Switching Mode.
Definition: ccu6.h:3243
INLINE void CCU6_T12_T13_Str_Dis(void)
disables T12 and T13 Shadow Transfer.
Definition: ccu6.h:679
INLINE void CCU6_WHE_Int_En(void)
enables Interrupt for Wrong Hall Event.
Definition: ccu6.h:5199
INLINE void CCU6_Ch2c_Passive_Level_High_Set(void)
sets Passive High Level of COUT62.
Definition: ccu6.h:2860
INLINE void CCU6_Ch0_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 0 Interrupts.
Definition: ccu6.h:4179
INLINE void CCU6_LoadShadowRegister_CC63(uint16 tick)
Load Channel 3 compare value to the shadow register.
Definition: ccu6.h:5481
#define CCU6
Definition: tle987x.h:6087
#define CCU6_PISEL0_ISTRP_Pos
Definition: tle987x.h:7326
#define CCU6_T12DTC_DTE2_Pos
Definition: tle987x.h:7362
#define CCU6_IS_T12PM_Msk
Definition: tle987x.h:7198
#define CCU6_INP_INPT13_Msk
Definition: tle987x.h:7181
#define CCU6_CMPSTAT_CC60ST_Pos
Definition: tle987x.h:7106
#define CCU6_ISR_RCC61F_Pos
Definition: tle987x.h:7222
#define CCU6_CC63R_CCV_Pos
Definition: tle987x.h:7083
#define CCU6_ISS_SCC60R_Msk
Definition: tle987x.h:7248
#define CCU6_TCTR4_T12STR_Msk
Definition: tle987x.h:7436
#define CCU6_TCTR4_T13RES_Msk
Definition: tle987x.h:7444
#define CCU6_CMPSTAT_CCPOS1_Msk
Definition: tle987x.h:7117
#define CCU6_T12MSEL_HSYNC_Pos
Definition: tle987x.h:7377
#define CCU6_TCTR4_DTRES_Msk
Definition: tle987x.h:7432
#define CCU6_CMPSTAT_T13IM_Msk
Definition: tle987x.h:7135
#define CCU6_CMPSTAT_CC61ST_Msk
Definition: tle987x.h:7109
#define CCU6_IS_IDLE_Msk
Definition: tle987x.h:7212
#define CCU6_INP_INPERR_Pos
Definition: tle987x.h:7176
#define CCU6_PISEL2_T12EXT_Pos
Definition: tle987x.h:7343
#define CCU6_CMPSTAT_COUT63PS_Msk
Definition: tle987x.h:7133
#define CCU6_PISEL0_ISTRP_Msk
Definition: tle987x.h:7327
#define CCU6_PISEL2_T13EXT_Msk
Definition: tle987x.h:7346
#define CCU6_PISEL0_ISPOS1_Pos
Definition: tle987x.h:7330
#define CCU6_ISR_RCC61F_Msk
Definition: tle987x.h:7223
#define CCU6_ISR_RT13CM_Msk
Definition: tle987x.h:7233
#define CCU6_TCTR0_STE12_Pos
Definition: tle987x.h:7397
#define CCU6_IS_TRPS_Pos
Definition: tle987x.h:7205
#define CCU6_ISS_ST12OM_Msk
Definition: tle987x.h:7260
#define CCU6_ISR_RSTR_Msk
Definition: tle987x.h:7245
#define CCU6_CMPMODIF_MCC60R_Msk
Definition: tle987x.h:7098
#define CCU6_ISS_ST13PM_Msk
Definition: tle987x.h:7266
#define CCU6_ISR_RCC62F_Msk
Definition: tle987x.h:7227
#define CCU6_IS_T12OM_Msk
Definition: tle987x.h:7196
#define CCU6_IEN_ENT12OM_Pos
Definition: tle987x.h:7149
#define CCU6_ISS_SCHE_Pos
Definition: tle987x.h:7271
#define CCU6_IEN_ENCC61F_Pos
Definition: tle987x.h:7143
#define CCU6_ISS_SIDLE_Pos
Definition: tle987x.h:7275
#define CCU6_ISR_RT13PM_Msk
Definition: tle987x.h:7235
#define CCU6_MCMCTR_SWSEL_Msk
Definition: tle987x.h:7281
#define CCU6_MCMCTR_STE12D_Pos
Definition: tle987x.h:7286
#define CCU6_CC61R_CCV_Pos
Definition: tle987x.h:7071
#define CCU6_ISR_RTRPF_Msk
Definition: tle987x.h:7237
#define CCU6_MCMOUTS_EXPHS_Pos
Definition: tle987x.h:7304
#define CCU6_IS_STR_Pos
Definition: tle987x.h:7213
#define CCU6_INP_INPCC61_Pos
Definition: tle987x.h:7170
#define CCU6_CC62R_CCV_Msk
Definition: tle987x.h:7078
#define CCU6_IS_WHE_Pos
Definition: tle987x.h:7209
#define CCU6_PISEL0_IST12HR_Msk
Definition: tle987x.h:7335
#define CCU6_PISEL0_ISCC60_Msk
Definition: tle987x.h:7321
#define CCU6_ISS_SWHE_Msk
Definition: tle987x.h:7274
#define CCU6_CMPMODIF_MCC63R_Pos
Definition: tle987x.h:7103
#define CCU6_INP_INPCC62_Msk
Definition: tle987x.h:7173
#define CCU6_IS_ICC60R_Pos
Definition: tle987x.h:7183
#define CCU6_ISS_SCC62F_Pos
Definition: tle987x.h:7257
#define CCU6_TCTR0_T13CLK_Pos
Definition: tle987x.h:7403
#define CCU6_ISR_RT12PM_Pos
Definition: tle987x.h:7230
#define CCU6_T12DTC_DTR1_Pos
Definition: tle987x.h:7366
#define CCU6_MODCTR_T12MODEN_Msk
Definition: tle987x.h:7312
#define CCU6_IEN_ENT12PM_Pos
Definition: tle987x.h:7151
#define CCU6_IEN_ENSTR_Msk
Definition: tle987x.h:7166
#define CCU6_PISEL2_ISCNT13_Pos
Definition: tle987x.h:7341
#define CCU6_TCTR0_T12R_Pos
Definition: tle987x.h:7395
#define CCU6_TRPCTR_TRPM2_Msk
Definition: tle987x.h:7457
#define CCU6_INP_INPERR_Msk
Definition: tle987x.h:7177
#define CCU6_CMPSTAT_CCPOS2_Pos
Definition: tle987x.h:7118
#define CCU6_IS_ICC62R_Msk
Definition: tle987x.h:7188
#define CCU6_TCTR0_STE12_Msk
Definition: tle987x.h:7398
#define CCU6_IEN_ENCC60R_Pos
Definition: tle987x.h:7137
#define CCU6_MCMOUTS_STRMCM_Msk
Definition: tle987x.h:7303
#define CCU6_IS_T13CM_Pos
Definition: tle987x.h:7199
#define CCU6_MCMCTR_STE12U_Pos
Definition: tle987x.h:7284
#define CCU6_PISEL0_ISPOS1_Msk
Definition: tle987x.h:7331
#define CCU6_TCTR0_T13PRE_Pos
Definition: tle987x.h:7405
#define CCU6_IEN_ENCC62F_Pos
Definition: tle987x.h:7147
#define CCU6_IS_STR_Msk
Definition: tle987x.h:7214
#define CCU6_TCTR4_T12RR_Pos
Definition: tle987x.h:7425
#define CCU6_ISR_RCC60F_Msk
Definition: tle987x.h:7219
#define CCU6_IEN_ENCC60R_Msk
Definition: tle987x.h:7138
#define CCU6_MCMOUT_MCMP_Pos
Definition: tle987x.h:7291
#define CCU6_MCMCTR_STE12D_Msk
Definition: tle987x.h:7287
#define CCU6_PISEL2_IST13HR_Msk
Definition: tle987x.h:7338
#define CCU6_T12DTC_DTE0_Msk
Definition: tle987x.h:7359
#define CCU6_TCTR4_T13RES_Pos
Definition: tle987x.h:7443
#define CCU6_T13_T13CV_Pos
Definition: tle987x.h:7385
#define CCU6_CMPSTAT_CC62ST_Pos
Definition: tle987x.h:7110
#define CCU6_IEN_ENTRPF_Msk
Definition: tle987x.h:7158
#define CCU6_TCTR2_T13RSEL_Msk
Definition: tle987x.h:7423
#define CCU6_IS_ICC61R_Pos
Definition: tle987x.h:7185
#define CCU6_T12MSEL_MSEL60_Msk
Definition: tle987x.h:7372
#define CCU6_TCTR2_T13TED_Pos
Definition: tle987x.h:7418
#define CCU6_TCTR4_T12STR_Pos
Definition: tle987x.h:7435
#define CCU6_T12MSEL_MSEL60_Pos
Definition: tle987x.h:7371
#define CCU6_PISEL0_ISPOS2_Pos
Definition: tle987x.h:7332
#define CCU6_CMPSTAT_CC60ST_Msk
Definition: tle987x.h:7107
#define CCU6_ISS_SCC62R_Pos
Definition: tle987x.h:7255
#define CCU6_MCMOUTS_MCMPS_Pos
Definition: tle987x.h:7300
#define CCU6_TCTR4_T13STR_Pos
Definition: tle987x.h:7447
#define CCU6_ISR_RCC60R_Msk
Definition: tle987x.h:7217
#define CCU6_TCTR0_T12PRE_Pos
Definition: tle987x.h:7393
#define CCU6_ISS_STRPF_Msk
Definition: tle987x.h:7268
#define CCU6_IS_ICC60F_Pos
Definition: tle987x.h:7189
#define CCU6_IS_WHE_Msk
Definition: tle987x.h:7210
#define CCU6_ISS_ST13PM_Pos
Definition: tle987x.h:7265
#define CCU6_PSLR_PSL63_Msk
Definition: tle987x.h:7351
#define CCU6_TCTR4_T12STD_Msk
Definition: tle987x.h:7438
#define CCU6_PSLR_PSL63_Pos
Definition: tle987x.h:7350
#define CCU6_T13PR_T13PV_Msk
Definition: tle987x.h:7389
#define CCU6_MCMOUT_R_Msk
Definition: tle987x.h:7294
#define CCU6_MCMOUT_MCMP_Msk
Definition: tle987x.h:7292
#define CCU6_CMPMODIF_MCC62S_Msk
Definition: tle987x.h:7094
#define CCU6_CMPMODIF_MCC61S_Pos
Definition: tle987x.h:7091
#define CCU6_CMPMODIF_MCC60S_Msk
Definition: tle987x.h:7090
#define CCU6_T12_T12CV_Pos
Definition: tle987x.h:7353
#define CCU6_ISR_RTRPF_Pos
Definition: tle987x.h:7236
#define CCU6_TRPCTR_TRPPEN_Pos
Definition: tle987x.h:7462
#define CCU6_CMPSTAT_CCPOS2_Msk
Definition: tle987x.h:7119
#define CCU6_IS_ICC61F_Pos
Definition: tle987x.h:7191
#define CCU6_MCMOUT_EXPH_Pos
Definition: tle987x.h:7295
#define CCU6_T12PR_T12PV_Pos
Definition: tle987x.h:7382
#define CCU6_ISR_RSTR_Pos
Definition: tle987x.h:7244
#define CCU6_CMPMODIF_MCC61R_Msk
Definition: tle987x.h:7100
#define CCU6_IS_T13CM_Msk
Definition: tle987x.h:7200
#define CCU6_PSLR_PSL_Pos
Definition: tle987x.h:7348
#define CCU6_IEN_ENCC60F_Pos
Definition: tle987x.h:7139
#define CCU6_TCTR2_T12RSEL_Msk
Definition: tle987x.h:7421
#define CCU6_T12DTC_DTE1_Pos
Definition: tle987x.h:7360
#define CCU6_T12DTC_DTE2_Msk
Definition: tle987x.h:7363
#define CCU6_TCTR4_T12CNT_Msk
Definition: tle987x.h:7434
#define CCU6_IEN_ENCC62R_Msk
Definition: tle987x.h:7146
#define CCU6_TCTR4_T12RS_Msk
Definition: tle987x.h:7428
#define CCU6_ISR_RT13CM_Pos
Definition: tle987x.h:7232
#define CCU6_ISS_SCC61R_Pos
Definition: tle987x.h:7251
#define CCU6_TCTR0_CTM_Msk
Definition: tle987x.h:7402
#define CCU6_TCTR0_T12R_Msk
Definition: tle987x.h:7396
#define CCU6_MCMOUT_CURH_Pos
Definition: tle987x.h:7297
#define CCU6_ISS_SIDLE_Msk
Definition: tle987x.h:7276
#define CCU6_CMPSTAT_CCPOS0_Msk
Definition: tle987x.h:7115
#define CCU6_ISS_SWHC_Pos
Definition: tle987x.h:7269
#define CCU6_PISEL0_ISPOS0_Msk
Definition: tle987x.h:7329
#define CCU6_PISEL0_ISPOS0_Pos
Definition: tle987x.h:7328
#define CCU6_ISS_SCC60F_Pos
Definition: tle987x.h:7249
#define CCU6_IEN_ENCC61R_Pos
Definition: tle987x.h:7141
#define CCU6_INP_INPCHE_Msk
Definition: tle987x.h:7175
#define CCU6_ISS_ST13CM_Pos
Definition: tle987x.h:7263
#define CCU6_IEN_ENT13CM_Msk
Definition: tle987x.h:7154
#define CCU6_TCTR0_CDIR_Pos
Definition: tle987x.h:7399
#define CCU6_TCTR4_T13CNT_Msk
Definition: tle987x.h:7446
#define CCU6_T12_T12CV_Msk
Definition: tle987x.h:7354
#define CCU6_TCTR2_T12SSC_Pos
Definition: tle987x.h:7412
#define CCU6_INP_INPT12_Pos
Definition: tle987x.h:7178
#define CCU6_TCTR0_CDIR_Msk
Definition: tle987x.h:7400
#define CCU6_ISR_RCC62R_Pos
Definition: tle987x.h:7224
#define CCU6_IS_T13PM_Msk
Definition: tle987x.h:7202
#define CCU6_MODCTR_MCMEN_Pos
Definition: tle987x.h:7313
#define CCU6_CMPSTAT_CC61ST_Pos
Definition: tle987x.h:7108
#define CCU6_INP_INPCC60_Pos
Definition: tle987x.h:7168
#define CCU6_TRPCTR_TRPM2_Pos
Definition: tle987x.h:7456
#define CCU6_TRPCTR_TRPEN_Msk
Definition: tle987x.h:7459
#define CCU6_TRPCTR_TRPEN13_Pos
Definition: tle987x.h:7460
#define CCU6_TCTR4_T13RR_Pos
Definition: tle987x.h:7439
#define CCU6_TCTR0_STE13_Msk
Definition: tle987x.h:7410
#define CCU6_TCTR0_T13CLK_Msk
Definition: tle987x.h:7404
#define CCU6_TRPCTR_TRPPEN_Msk
Definition: tle987x.h:7463
#define CCU6_TRPCTR_TRPEN13_Msk
Definition: tle987x.h:7461
#define CCU6_ISR_RWHE_Pos
Definition: tle987x.h:7240
#define CCU6_IEN_ENCC62R_Pos
Definition: tle987x.h:7145
#define CCU6_TCTR4_T12CNT_Pos
Definition: tle987x.h:7433
#define CCU6_TCTR4_T13RS_Msk
Definition: tle987x.h:7442
#define CCU6_T12DTC_DTM_Msk
Definition: tle987x.h:7357
#define CCU6_CMPMODIF_MCC63R_Msk
Definition: tle987x.h:7104
#define CCU6_IEN_ENCC60F_Msk
Definition: tle987x.h:7140
#define CCU6_TCTR4_T13RR_Msk
Definition: tle987x.h:7440
#define CCU6_T12MSEL_HSYNC_Msk
Definition: tle987x.h:7378
#define CCU6_T12MSEL_MSEL61_Msk
Definition: tle987x.h:7374
#define CCU6_TCTR0_T12PRE_Msk
Definition: tle987x.h:7394
#define CCU6_TCTR2_T13RSEL_Pos
Definition: tle987x.h:7422
#define CCU6_CMPMODIF_MCC62S_Pos
Definition: tle987x.h:7093
#define CCU6_IS_ICC60R_Msk
Definition: tle987x.h:7184
#define CCU6_CMPSTAT_CCPOS0_Pos
Definition: tle987x.h:7114
#define CCU6_ISS_SWHE_Pos
Definition: tle987x.h:7273
#define CCU6_ISR_RCC62R_Msk
Definition: tle987x.h:7225
#define CCU6_CMPMODIF_MCC60S_Pos
Definition: tle987x.h:7089
#define CCU6_T12MSEL_DBYP_Pos
Definition: tle987x.h:7379
#define CCU6_IS_ICC62R_Pos
Definition: tle987x.h:7187
#define CCU6_TCTR4_T13STD_Pos
Definition: tle987x.h:7449
#define CCU6_ISR_RCC61R_Msk
Definition: tle987x.h:7221
#define CCU6_INP_INPCHE_Pos
Definition: tle987x.h:7174
#define CCU6_CMPMODIF_MCC63S_Msk
Definition: tle987x.h:7096
#define CCU6_TCTR4_T13CNT_Pos
Definition: tle987x.h:7445
#define CCU6_CC60R_CCV_Msk
Definition: tle987x.h:7066
#define CCU6_MCMOUTS_STRHP_Msk
Definition: tle987x.h:7309
#define CCU6_INP_INPCC62_Pos
Definition: tle987x.h:7172
#define CCU6_INP_INPT12_Msk
Definition: tle987x.h:7179
#define CCU6_IS_CHE_Pos
Definition: tle987x.h:7207
#define CCU6_TCTR0_T13PRE_Msk
Definition: tle987x.h:7406
#define CCU6_CMPMODIF_MCC60R_Pos
Definition: tle987x.h:7097
#define CCU6_T12MSEL_MSEL62_Pos
Definition: tle987x.h:7375
#define CCU6_IEN_ENCHE_Msk
Definition: tle987x.h:7160
#define CCU6_TCTR4_DTRES_Pos
Definition: tle987x.h:7431
#define CCU6_TRPCTR_TRPEN_Pos
Definition: tle987x.h:7458
#define CCU6_T12MSEL_MSEL62_Msk
Definition: tle987x.h:7376
#define CCU6_CMPSTAT_CC60PS_Pos
Definition: tle987x.h:7120
#define CCU6_ISR_RT12OM_Msk
Definition: tle987x.h:7229
#define CCU6_CC62R_CCV_Pos
Definition: tle987x.h:7077
#define CCU6_PISEL0_ISCC62_Msk
Definition: tle987x.h:7325
#define CCU6_CMPSTAT_CC63ST_Pos
Definition: tle987x.h:7112
#define CCU6_CMPMODIF_MCC62R_Msk
Definition: tle987x.h:7102
#define CCU6_ISR_RCC60R_Pos
Definition: tle987x.h:7216
#define CCU6_MODCTR_T12MODEN_Pos
Definition: tle987x.h:7311
#define CCU6_MCMOUTS_CURHS_Pos
Definition: tle987x.h:7306
#define CCU6_MCMCTR_STE13U_Msk
Definition: tle987x.h:7289
#define CCU6_MODCTR_T13MODEN_Pos
Definition: tle987x.h:7315
#define CCU6_ISS_SCC61F_Pos
Definition: tle987x.h:7253
#define CCU6_MCMOUTS_MCMPS_Msk
Definition: tle987x.h:7301
#define CCU6_MODCTR_ECT13O_Pos
Definition: tle987x.h:7317
#define CCU6_CMPMODIF_MCC62R_Pos
Definition: tle987x.h:7101
#define CCU6_IEN_ENCC61R_Msk
Definition: tle987x.h:7142
#define CCU6_TCTR4_T12RS_Pos
Definition: tle987x.h:7427
#define CCU6_T12DTC_DTR0_Msk
Definition: tle987x.h:7365
#define CCU6_TCTR2_T13TED_Msk
Definition: tle987x.h:7419
#define CCU6_MCMOUTS_CURHS_Msk
Definition: tle987x.h:7307
#define CCU6_T13PR_T13PV_Pos
Definition: tle987x.h:7388
#define CCU6_PISEL2_T13EXT_Pos
Definition: tle987x.h:7345
#define CCU6_TCTR0_T12CLK_Pos
Definition: tle987x.h:7391
#define CCU6_PISEL0_ISCC62_Pos
Definition: tle987x.h:7324
#define CCU6_PSLR_PSL_Msk
Definition: tle987x.h:7349
#define CCU6_ISR_RCHE_Pos
Definition: tle987x.h:7238
#define CCU6_PISEL0_ISPOS2_Msk
Definition: tle987x.h:7333
#define CCU6_T12MSEL_MSEL61_Pos
Definition: tle987x.h:7373
#define CCU6_PISEL2_ISCNT13_Msk
Definition: tle987x.h:7342
#define CCU6_IEN_ENCC61F_Msk
Definition: tle987x.h:7144
#define CCU6_TCTR2_T13TEC_Msk
Definition: tle987x.h:7417
#define CCU6_ISR_RWHE_Msk
Definition: tle987x.h:7241
#define CCU6_TCTR0_T13R_Msk
Definition: tle987x.h:7408
#define CCU6_T12DTC_DTR1_Msk
Definition: tle987x.h:7367
#define CCU6_IEN_ENCHE_Pos
Definition: tle987x.h:7159
#define CCU6_TRPCTR_TRPM0_Msk
Definition: tle987x.h:7453
#define CCU6_TCTR0_T12CLK_Msk
Definition: tle987x.h:7392
#define CCU6_TCTR4_T12RES_Pos
Definition: tle987x.h:7429
#define CCU6_TCTR2_T13TEC_Pos
Definition: tle987x.h:7416
#define CCU6_MODCTR_MCMEN_Msk
Definition: tle987x.h:7314
#define CCU6_TCTR0_T13R_Pos
Definition: tle987x.h:7407
#define CCU6_PISEL2_ISCNT12_Msk
Definition: tle987x.h:7340
#define CCU6_CMPMODIF_MCC61R_Pos
Definition: tle987x.h:7099
#define CCU6_ISS_ST12PM_Msk
Definition: tle987x.h:7262
#define CCU6_IEN_ENT13PM_Msk
Definition: tle987x.h:7156
#define CCU6_IEN_ENWHE_Pos
Definition: tle987x.h:7161
#define CCU6_ISR_RCC61R_Pos
Definition: tle987x.h:7220
#define CCU6_IS_TRPF_Pos
Definition: tle987x.h:7203
#define CCU6_ISS_SCC62F_Msk
Definition: tle987x.h:7258
#define CCU6_MCMCTR_SWSYN_Msk
Definition: tle987x.h:7283
#define CCU6_T13_T13CV_Msk
Definition: tle987x.h:7386
#define CCU6_MCMOUT_R_Pos
Definition: tle987x.h:7293
#define CCU6_ISR_RT12PM_Msk
Definition: tle987x.h:7231
#define CCU6_ISS_ST12PM_Pos
Definition: tle987x.h:7261
#define CCU6_TCTR2_T12SSC_Msk
Definition: tle987x.h:7413
#define CCU6_IS_T12PM_Pos
Definition: tle987x.h:7197
#define CCU6_INP_INPT13_Pos
Definition: tle987x.h:7180
#define CCU6_IS_ICC60F_Msk
Definition: tle987x.h:7190
#define CCU6_TCTR4_T12STD_Pos
Definition: tle987x.h:7437
#define CCU6_CMPSTAT_CC62ST_Msk
Definition: tle987x.h:7111
#define CCU6_CMPSTAT_CC63ST_Msk
Definition: tle987x.h:7113
#define CCU6_TRPCTR_TRPM1_Msk
Definition: tle987x.h:7455
#define CCU6_IS_T13PM_Pos
Definition: tle987x.h:7201
#define CCU6_ISS_SCC60F_Msk
Definition: tle987x.h:7250
#define CCU6_TCTR2_T12RSEL_Pos
Definition: tle987x.h:7420
#define CCU6_ISR_RT13PM_Pos
Definition: tle987x.h:7234
#define CCU6_ISS_SCC62R_Msk
Definition: tle987x.h:7256
#define CCU6_MCMOUTS_EXPHS_Msk
Definition: tle987x.h:7305
#define CCU6_TCTR0_STE13_Pos
Definition: tle987x.h:7409
#define CCU6_ISS_SCHE_Msk
Definition: tle987x.h:7272
#define CCU6_MCMOUTS_STRHP_Pos
Definition: tle987x.h:7308
#define CCU6_PISEL0_ISCC61_Pos
Definition: tle987x.h:7322
#define CCU6_TCTR0_CTM_Pos
Definition: tle987x.h:7401
#define CCU6_MCMOUTS_STRMCM_Pos
Definition: tle987x.h:7302
#define CCU6_CC63R_CCV_Msk
Definition: tle987x.h:7084
#define CCU6_IS_ICC62F_Pos
Definition: tle987x.h:7193
#define CCU6_TCTR4_T12RR_Msk
Definition: tle987x.h:7426
#define CCU6_IS_TRPF_Msk
Definition: tle987x.h:7204
#define CCU6_ISS_SSTR_Msk
Definition: tle987x.h:7278
#define CCU6_CMPSTAT_COUT63PS_Pos
Definition: tle987x.h:7132
#define CCU6_MCMCTR_STE12U_Msk
Definition: tle987x.h:7285
#define CCU6_TCTR4_T13STD_Msk
Definition: tle987x.h:7450
#define CCU6_IEN_ENT13CM_Pos
Definition: tle987x.h:7153
#define CCU6_CMPSTAT_T13IM_Pos
Definition: tle987x.h:7134
#define CCU6_IS_ICC62F_Msk
Definition: tle987x.h:7194
#define CCU6_PISEL2_T12EXT_Msk
Definition: tle987x.h:7344
#define CCU6_IEN_ENTRPF_Pos
Definition: tle987x.h:7157
#define CCU6_IS_ICC61R_Msk
Definition: tle987x.h:7186
#define CCU6_IS_T12OM_Pos
Definition: tle987x.h:7195
#define CCU6_IEN_ENT13PM_Pos
Definition: tle987x.h:7155
#define CCU6_CMPMODIF_MCC63S_Pos
Definition: tle987x.h:7095
#define CCU6_MCMOUT_EXPH_Msk
Definition: tle987x.h:7296
#define CCU6_PISEL0_ISCC61_Msk
Definition: tle987x.h:7323
#define CCU6_ISS_ST12OM_Pos
Definition: tle987x.h:7259
#define CCU6_ISR_RCHE_Msk
Definition: tle987x.h:7239
#define CCU6_IEN_ENSTR_Pos
Definition: tle987x.h:7165
#define CCU6_MCMCTR_SWSEL_Pos
Definition: tle987x.h:7280
#define CCU6_TCTR4_T13RS_Pos
Definition: tle987x.h:7441
#define CCU6_ISS_SCC61F_Msk
Definition: tle987x.h:7254
#define CCU6_MCMOUT_CURH_Msk
Definition: tle987x.h:7298
#define CCU6_T12DTC_DTE1_Msk
Definition: tle987x.h:7361
#define CCU6_IS_ICC61F_Msk
Definition: tle987x.h:7192
#define CCU6_T12DTC_DTE0_Pos
Definition: tle987x.h:7358
#define CCU6_T12DTC_DTR2_Pos
Definition: tle987x.h:7368
#define CCU6_T12DTC_DTR2_Msk
Definition: tle987x.h:7369
#define CCU6_CC60R_CCV_Pos
Definition: tle987x.h:7065
#define CCU6_ISS_SCC60R_Pos
Definition: tle987x.h:7247
#define CCU6_MODCTR_T13MODEN_Msk
Definition: tle987x.h:7316
#define CCU6_PISEL2_ISCNT12_Pos
Definition: tle987x.h:7339
#define CCU6_ISR_RCC62F_Pos
Definition: tle987x.h:7226
#define CCU6_IEN_ENWHE_Msk
Definition: tle987x.h:7162
#define CCU6_T12DTC_DTM_Pos
Definition: tle987x.h:7356
#define CCU6_IEN_ENT12OM_Msk
Definition: tle987x.h:7150
#define CCU6_IEN_ENT12PM_Msk
Definition: tle987x.h:7152
#define CCU6_IS_TRPS_Msk
Definition: tle987x.h:7206
#define CCU6_T12MSEL_DBYP_Msk
Definition: tle987x.h:7380
#define CCU6_T12DTC_DTR0_Pos
Definition: tle987x.h:7364
#define CCU6_ISS_SSTR_Pos
Definition: tle987x.h:7277
#define CCU6_ISS_ST13CM_Msk
Definition: tle987x.h:7264
#define CCU6_TCTR4_T13STR_Msk
Definition: tle987x.h:7448
#define CCU6_T12PR_T12PV_Msk
Definition: tle987x.h:7383
#define CCU6_INP_INPCC60_Msk
Definition: tle987x.h:7169
#define CCU6_PISEL0_IST12HR_Pos
Definition: tle987x.h:7334
#define CCU6_TRPCTR_TRPM0_Pos
Definition: tle987x.h:7452
#define CCU6_CMPMODIF_MCC61S_Msk
Definition: tle987x.h:7092
#define CCU6_IS_CHE_Msk
Definition: tle987x.h:7208
#define CCU6_ISS_STRPF_Pos
Definition: tle987x.h:7267
#define CCU6_IEN_ENCC62F_Msk
Definition: tle987x.h:7148
#define CCU6_IS_IDLE_Pos
Definition: tle987x.h:7211
#define CCU6_MODCTR_ECT13O_Msk
Definition: tle987x.h:7318
#define CCU6_PISEL0_ISCC60_Pos
Definition: tle987x.h:7320
#define CCU6_ISR_RCC60F_Pos
Definition: tle987x.h:7218
#define CCU6_ISR_RT12OM_Pos
Definition: tle987x.h:7228
#define CCU6_TCTR4_T12RES_Msk
Definition: tle987x.h:7430
#define CCU6_INP_INPCC61_Msk
Definition: tle987x.h:7171
#define CCU6_PISEL2_IST13HR_Pos
Definition: tle987x.h:7337
#define CCU6_CMPSTAT_CCPOS1_Pos
Definition: tle987x.h:7116
#define CCU6_ISS_SCC61R_Msk
Definition: tle987x.h:7252
#define CCU6_MCMCTR_SWSYN_Pos
Definition: tle987x.h:7282
#define CCU6_MCMCTR_STE13U_Pos
Definition: tle987x.h:7288
#define CCU6_ISS_SWHC_Msk
Definition: tle987x.h:7270
#define CCU6_CC61R_CCV_Msk
Definition: tle987x.h:7072
SFR low level access library.
INLINE void Field_Wrt16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:342
INLINE uint8 u1_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 1-bit field of a 16-bit register.
Definition: sfr_access.h:402
INLINE uint8 u8_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 8-bit field of a 16-bit register.
Definition: sfr_access.h:417
INLINE void Field_Mod16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:357
INLINE uint16 u16_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 16-bit field of a 16-bit register.
Definition: sfr_access.h:427
CMSIS register HeaderFile.
Device specific memory layout defines.
General type declarations.
#define INLINE
Definition: types.h:148
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155