Infineon MOTIX™ MCU TLE987x Device Family SDK
dma.h
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23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** DM Daniel Mysliwitz **
45 ** BG Blandine Guillot **
46 ** JO Julia Ott **
47 ** VO Vanessa Ongaro **
48 *******************************************************************************/
49 
50 /*******************************************************************************
51 ** Revision Control History **
52 ********************************************************************************
53 ** V0.1.0: 2015-11-25, DM: Initial version **
54 ** V0.1.1: 2017-07-09, DM: Interrupt macros added **
55 ** Scatter-gather support added **
56 ** V0.1.2: 2017-07-12, DM: Setup task for scatter-gather added **
57 ** V0.1.3: 2017-07-20, DM: API macros added **
58 ** V0.1.4: 2017-09-22, DM: MISRA 2012 compliance, the following PC-Lint **
59 ** rules are globally deactivated: **
60 ** - Info 793: ANSI/ISO limit of 6 'significant **
61 ** characters in an external identifier **
62 ** - Note 950: Non-ANSI reserved word or construct: **
63 ** '_to_brackets' [MISRA Rule 1] **
64 ** - Note 923: cast from unsigned int to pointer **
65 ** [MISRA Rule 45] **
66 ** - Note 923: cast from pointer to unsigned int **
67 ** [MISRA Rule 45] **
68 ** - Info 765: Info 765: external '...' could be **
69 ** made static [MISRA Rule 23] **
70 ** - Error 18: Symbol '..' redeclared (void/nonvoid)**
71 ** ... [MISRA Rule 26],[Encompasses MISRA Rule 72]**
72 ** V0.1.5: 2018-03-12, DM: DMA Ch13 (SDADC) added **
73 ** DMA_MASK_CHx macros changed due to MISRA 2012 **
74 ** Replaced macros by INLINE functions **
75 ** Replaced register accesses within functions by **
76 ** function calls **
77 ** Replaced __STATIC_INLINE by INLINE **
78 ** Renamed DMA entries according to channel number **
79 ** V0.1.6: 2018-11-27, JO: Doxygen update **
80 ** Moved revision history from dma.c to dma.h **
81 ** V0.1.7: 2019-02-21, DM: DMA structures modified to be ARMCC v6 compliant **
82 ** DMA base structure set to upper most address **
83 ** 3KB RAM: 0x18000A00..0x18000BFF **
84 ** 6KB RAM: 0x18001600..0x180017FF **
85 ** 8KB RAM: 0x18001E00..0x18001FFF **
86 ** V0.1.8: 2020-04-15, BG: Updated revision history format **
87 ** V0.1.9: 2020-07-14, JO: EP-431: remove ARMCC v6 Compiler warnings **
88 ** - Initialized alternate table entry **
89 ** - Disabled ARMCC v6 warnings -Wmissing-variable- **
90 ** declarations, -Wunreachable-code, and **
91 ** -Wpedantic locally in file dma.c **
92 ** V0.2.0: 2020-07-21, BG: EP-439: Formatted .h/.c files **
93 ** V0.2.1: 2020-10-28, DM: EP-565: Set DMA struct to volatile to remove **
94 ** ARMCC v6 O3 LTO problem **
95 ** V0.2.2: 2021-02-01, BG: EP-175: Updated code for compatibility with **
96 ** IAR compiler **
97 ** V0.2.3: 2022-02-28, JO: EP-936: Updated copyright and branding **
98 ** V0.2.4: 2022-10-18, VO: EP-1252: Removed ARMCC V6.18 warnings **
99 *******************************************************************************/
100 
101 #ifndef _DMA_H
102 #define _DMA_H
103 
104 /*******************************************************************************
105 ** Includes **
106 *******************************************************************************/
107 #include "tle987x.h"
108 #include "types.h"
109 #include "dma_defines.h"
110 #include "sfr_access.h"
111 
112 /*******************************************************************************
113 ** Global Macro Definitions **
114 *******************************************************************************/
116 #define DMA_CH0 (0u)
118 #define DMA_CH1 (1u)
120 #define DMA_CH2 (2u)
122 #define DMA_CH3 (3u)
124 #define DMA_CH4 (4u)
126 #define DMA_CH5 (5u)
128 #define DMA_CH6 (6u)
130 #define DMA_CH7 (7u)
132 #define DMA_CH8 (8u)
134 #define DMA_CH9 (9u)
136 #define DMA_CH10 (10u)
138 #define DMA_CH11 (11u)
140 #define DMA_CH12 (12u)
141 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
143  #define DMA_CH13 (13u)
144 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
145 
147 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
149 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
151 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
153 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
155 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
157 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
159 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
161 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
163 #define DMA_MASK_CH8 ((uint16)1u << DMA_CH8)
165 #define DMA_MASK_CH9 ((uint16)1u << DMA_CH9)
167 #define DMA_MASK_CH10 ((uint16)1u << DMA_CH10)
169 #define DMA_MASK_CH11 ((uint16)1u << DMA_CH11)
171 #define DMA_MASK_CH12 ((uint16)1u << DMA_CH12)
172 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
174  #define DMA_MASK_CH13 ((uint16)1u << DMA_CH13)
175 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
176 
180 typedef enum DMA_Transfer_Size
181 {
184  DMA_32Bit_Transfer = 2u
186 
190 typedef enum DMA_Increment_Size
191 {
194  DMA_Inc_32bit = 2u
196 
200 typedef enum DMA_Increment_Mode
201 {
202  DMA_No_Inc = 0u,
203  DMA_Src_Inc = 1u,
204  DMA_Dst_Inc = 2u,
205  DMA_Src_Dst_Inc = 3u
207 
211 typedef enum DMA_Cycle_Types
212 {
222 
223 /*******************************************************************************
224 ** Global Type Definitions **
225 *******************************************************************************/
229 typedef union
230 {
232  struct
233  {
244  } bit;
245 } TControl;
246 
250 typedef struct
251 {
256 } TDMA_Entry;
257 
258 
259 /*******************************************************************************
260 ** Global Inline Function Definitions **
261 *******************************************************************************/
280 {
282 }
283 
302 {
304 }
305 
324 {
326 }
327 
346 {
348 }
349 
368 {
370 }
371 
390 {
392 }
393 
412 {
414 }
415 
434 {
436 }
437 
456 {
458 }
459 
478 {
480 }
481 
500 {
502 }
503 
522 {
524 }
525 
544 {
546 }
547 
548 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
567 {
569 }
570 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
571 
590 {
592 }
593 
613 {
615 }
616 
635 {
637 }
638 
658 {
660 }
661 
680 {
682 }
683 
703 {
705 }
706 
725 {
727 }
728 
748 {
750 }
751 
770 {
772 }
773 
793 {
795 }
796 
815 {
817 }
818 
838 {
840 }
841 
860 {
862 }
863 
883 {
885 }
886 
905 {
907 }
908 
928 {
930 }
931 
950 {
952 }
953 
973 {
975 }
976 
995 {
997 }
998 
1018 {
1020 }
1021 
1040 {
1042 }
1043 
1063 {
1065 }
1066 
1085 {
1087 }
1088 
1108 {
1110 }
1111 
1130 {
1132 }
1133 
1153 {
1155 }
1156 
1157 #if defined TLE9879_2QXA40 || defined TLE9872_2QXW40
1176 {
1178 }
1179 
1199 {
1201 }
1202 #endif /* TLE9879_2QXA40 || defined TLE9872_2QXW40 */
1203 
1220 {
1222 }
1223 
1240 {
1242 }
1243 
1260 {
1262 }
1263 
1280 {
1282 }
1283 
1300 {
1302 }
1303 
1312 {
1313  return ( (uint32)(DMA->ALT_CTRL_BASE_PTR.reg + (DMA_Ch * sizeof(TDMA_Entry))) );
1314 }
1315 
1324 {
1325  return ( (uint32)(DMA->CTRL_BASE_PTR.reg + (DMA_Ch * sizeof(TDMA_Entry))) );
1326 }
1327 
1328 /*******************************************************************************
1329 ** Global Function Declarations **
1330 *******************************************************************************/
1331 #if (DMA_XML_VERSION >= 10200)
1332 
1337 void DMA_Init(void);
1338 
1371 void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst,
1372  uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment);
1373 
1374 
1409 void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt);
1410 
1456 TDMA_Entry *DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask);
1457 
1498 void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks);
1499 
1500 
1539 void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks);
1540 
1583 TDMA_Entry *DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst,
1584  uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment);
1585 
1610 INLINE void DMA_Master_En(void);
1611 
1612 /*******************************************************************************
1613 ** Global Inline Function Definitions **
1614 *******************************************************************************/
1616 {
1617  /* arm the DMA */
1618  DMA->CFG.bit.MASTER_ENABLE = 1u;
1619 }
1620 #else
1621 #error "use IFXConfigWizard XML Version V1.2.0 or greater"
1622 #endif
1623 
1624 #endif
INLINE void DMA_CH0_Int_Clr(void)
clears DMA Channel 0 Interrupt flag.
Definition: dma.h:279
INLINE void DMA_Master_En(void)
Enabled the DMA master.
Definition: dma.h:1615
INLINE void DMA_CH10_Int_Dis(void)
disables DMA Channel 10 Interrupt.
Definition: dma.h:1062
INLINE void DMA_CH10_Int_Clr(void)
clears DMA Channel 10 Interrupt flag.
Definition: dma.h:499
INLINE uint32 DMA_CHx_Entry_Alt(uint8 DMA_Ch)
This function returns the address inside the alternate structure in RAM for a given DMA channel.
Definition: dma.h:1311
INLINE void DMA_CH5_Int_Dis(void)
disables DMA Channel 5 Interrupt.
Definition: dma.h:837
enum DMA_Increment_Size TDMA_Increment_Size
INLINE void DMA_CH11_Int_En(void)
enables DMA Channel 11 Interrupt.
Definition: dma.h:1084
INLINE void DMA_CH3_Int_Clr(void)
clears DMA Channel 3 Interrupt flag.
Definition: dma.h:345
DMA_Transfer_Size
Definition: dma.h:181
@ DMA_32Bit_Transfer
Definition: dma.h:184
@ DMA_8Bit_Transfer
Definition: dma.h:182
@ DMA_16Bit_Transfer
Definition: dma.h:183
INLINE void DMA_CH5_Int_En(void)
enables DMA Channel 5 Interrupt.
Definition: dma.h:814
INLINE void DMA_CH6_Int_Dis(void)
disables DMA Channel 6 Interrupt.
Definition: dma.h:882
INLINE void DMA_CH9_Int_Dis(void)
disables DMA Channel 9 Interrupt.
Definition: dma.h:1017
enum DMA_Cycle_Types TDMA_Cycle_Types
INLINE void DMA_CH0_Int_En(void)
enables DMA Channel 0 Interrupt.
Definition: dma.h:589
INLINE void DMA_CH13_Int_Clr(void)
clears DMA Channel 13 Interrupt flag.
Definition: dma.h:566
INLINE void DMA_CH7_Int_Clr(void)
clears DMA Channel 7 Interrupt flag.
Definition: dma.h:433
INLINE void DMA_CH1_Int_Dis(void)
disables DMA Channel 1 Interrupt.
Definition: dma.h:657
INLINE void DMA_CH4_Int_Dis(void)
disables DMA Channel 4 Interrupt.
Definition: dma.h:792
enum DMA_Increment_Mode TDMA_Increment_Mode
INLINE void DMA_CH11_Int_Dis(void)
disables DMA Channel 11 Interrupt.
Definition: dma.h:1107
INLINE void DMA_Primary_Struct_Usage_Set(uint32 mask_ch)
selects the primary data structure for the corresponding DMA channel.
Definition: dma.h:1279
DMA_Increment_Mode
Definition: dma.h:201
@ DMA_No_Inc
Definition: dma.h:202
@ DMA_Src_Inc
Definition: dma.h:203
@ DMA_Dst_Inc
Definition: dma.h:204
@ DMA_Src_Dst_Inc
Definition: dma.h:205
INLINE void DMA_CH0_Int_Dis(void)
disables DMA Channel 0 Interrupt.
Definition: dma.h:612
void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt)
Resets the primary structure in RAM for a given channel and rearms it.
INLINE void DMA_CH13_Int_Dis(void)
disables DMA Channel 13 Interrupt.
Definition: dma.h:1198
INLINE void DMA_CH9_Int_En(void)
enables DMA Channel 9 Interrupt.
Definition: dma.h:994
INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
enables DMA Channels.
Definition: dma.h:1239
INLINE void DMA_CH4_Int_Clr(void)
clears DMA Channel 4 Interrupt flag.
Definition: dma.h:367
INLINE void DMA_CH11_Int_Clr(void)
clears DMA Channel 11 Interrupt flag.
Definition: dma.h:521
INLINE void DMA_CH2_Int_Dis(void)
disables DMA Channel 2 Interrupt.
Definition: dma.h:702
TDMA_Entry * DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up a task to be used in the Scatter-Gather modes.
INLINE void DMA_CH3_Int_En(void)
enables DMA Channel 3 Interrupt.
Definition: dma.h:724
INLINE void DMA_CH8_Int_En(void)
enables DMA Channel 8 Interrupt.
Definition: dma.h:949
INLINE void DMA_CH6_Int_En(void)
enables DMA Channel 6 Interrupt.
Definition: dma.h:859
INLINE void DMA_CH1_Int_Clr(void)
clears DMA Channel 1 Interrupt flag.
Definition: dma.h:301
DMA_Cycle_Types
Definition: dma.h:212
@ DMA_Cycle_Type_PerSctGthPrim
Definition: dma.h:219
@ DMA_Cycle_Type_Basic
Definition: dma.h:214
@ DMA_Cycle_Type_MemSctGthPrim
Definition: dma.h:217
@ DMA_Cycle_Type_Auto
Definition: dma.h:215
@ DMA_Cycle_Type_PingPong
Definition: dma.h:216
@ DMA_Cycle_Type_MemSctGthAlt
Definition: dma.h:218
@ DMA_Cycle_Type_PerSctGthAlt
Definition: dma.h:220
@ DMA_Cycle_Type_Invalid
Definition: dma.h:213
INLINE void DMA_CH7_Int_Dis(void)
disables DMA Channel 7 Interrupt.
Definition: dma.h:927
INLINE void DMA_CH5_Int_Clr(void)
clears DMA Channel 5 Interrupt flag.
Definition: dma.h:389
INLINE void DMA_CH12_Int_Dis(void)
disables DMA Channel 12 Interrupt.
Definition: dma.h:1152
void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up the desired DMA channel in the primary structure in RAM.
INLINE void DMA_CH2_Int_Clr(void)
clears DMA Channel 2 Interrupt flag.
Definition: dma.h:323
INLINE void DMA_CH1_Int_En(void)
enables DMA Channel 1 Interrupt.
Definition: dma.h:634
INLINE void DMA_Alternate_Struct_Usage_Set(uint32 mask_ch)
selects the alternate data structure for the corresponding DMA channel.
Definition: dma.h:1299
void DMA_Init(void)
Initializes the DMA structure in RAM and SFRs based on the Config Wizard for MOTIX MCU configuration.
INLINE void DMA_Software_Request_Set(uint32 mask_ch)
Set software request for DMA Channels.
Definition: dma.h:1259
INLINE void DMA_CH7_Int_En(void)
enables DMA Channel 7 Interrupt.
Definition: dma.h:904
enum DMA_Transfer_Size TDMA_Transfer_Size
INLINE void DMA_CH3_Int_Dis(void)
disables DMA Channel 3 Interrupt.
Definition: dma.h:747
INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
points to the base address of the primary data structure.
Definition: dma.h:1219
INLINE void DMA_CH13_Int_En(void)
enables DMA Channel 13 Interrupt.
Definition: dma.h:1175
INLINE void DMA_CH9_Int_Clr(void)
clears DMA Channel 9 Interrupt flag.
Definition: dma.h:477
INLINE void DMA_CH6_Int_Clr(void)
clears DMA Channel 6 Interrupt flag.
Definition: dma.h:411
void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.
void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
INLINE void DMA_CH2_Int_En(void)
enables DMA Channel 2 Interrupt.
Definition: dma.h:679
INLINE void DMA_CH4_Int_En(void)
enables DMA Channel 4 Interrupt.
Definition: dma.h:769
DMA_Increment_Size
Definition: dma.h:191
@ DMA_Inc_8bit
Definition: dma.h:192
@ DMA_Inc_32bit
Definition: dma.h:194
@ DMA_Inc_16bit
Definition: dma.h:193
INLINE uint32 DMA_CHx_Entry_Pri(uint8 DMA_Ch)
This function returns the address inside the primary structure in RAM for a given DMA channel.
Definition: dma.h:1323
INLINE void DMA_CH10_Int_En(void)
enables DMA Channel 10 Interrupt.
Definition: dma.h:1039
INLINE void DMA_CH8_Int_Dis(void)
disables DMA Channel 8 Interrupt.
Definition: dma.h:972
INLINE void DMA_CH12_Int_Clr(void)
clears DMA Channel 12 Interrupt flag.
Definition: dma.h:543
INLINE void DMA_CH8_Int_Clr(void)
clears DMA Channel 8 Interrupt flag.
Definition: dma.h:455
INLINE void DMA_CH12_Int_En(void)
enables DMA Channel 12 Interrupt.
Definition: dma.h:1129
TDMA_Entry * DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
Sets up a task to be used with memory scatter-gather mode.
#define DMA
Definition: tle987x.h:6090
#define SCU
Definition: tle987x.h:6097
#define SCU_DMAIRC1CLR_CH8C_Pos
Definition: tle987x.h:8859
#define SCU_DMAIEN1_CH1IE_Msk
Definition: tle987x.h:8825
#define SCU_DMAIEN1_CH7IE_Pos
Definition: tle987x.h:8812
#define SCU_DMAIRC2CLR_SDADCC_Pos
Definition: tle987x.h:8891
#define SCU_DMAIRC1CLR_CH7C_Pos
Definition: tle987x.h:8861
#define SCU_DMAIRC2CLR_SSC1C_Pos
Definition: tle987x.h:8897
#define SCU_DMAIRC1CLR_CH4C_Pos
Definition: tle987x.h:8867
#define SCU_DMAIRC2CLR_SSC1C_Msk
Definition: tle987x.h:8898
#define SCU_DMAIEN2_SSCTXIE_Pos
Definition: tle987x.h:8833
#define SCU_DMAIEN1_CH3IE_Pos
Definition: tle987x.h:8820
#define SCU_DMAIRC1CLR_CH5C_Pos
Definition: tle987x.h:8865
#define SCU_DMAIRC1CLR_CH1C_Msk
Definition: tle987x.h:8874
#define SCU_DMAIEN2_TRSEQ2RDYIE_Pos
Definition: tle987x.h:8835
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk
Definition: tle987x.h:7922
#define SCU_DMAIEN2_SDADCIE_Msk
Definition: tle987x.h:8828
#define SCU_DMAIRC1CLR_CH1C_Pos
Definition: tle987x.h:8873
#define SCU_DMAIEN1_CH8IE_Msk
Definition: tle987x.h:8811
#define SCU_DMAIRC1CLR_CH2C_Pos
Definition: tle987x.h:8871
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos
Definition: tle987x.h:7918
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos
Definition: tle987x.h:8901
#define SCU_DMAIEN2_GPT12IE_Pos
Definition: tle987x.h:8829
#define SCU_DMAIEN1_CH5IE_Pos
Definition: tle987x.h:8816
#define SCU_DMAIEN1_CH2IE_Pos
Definition: tle987x.h:8822
#define SCU_DMAIEN1_CH6IE_Msk
Definition: tle987x.h:8815
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos
Definition: tle987x.h:7921
#define SCU_DMAIRC1CLR_CH7C_Msk
Definition: tle987x.h:8862
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk
Definition: tle987x.h:7949
#define SCU_DMAIRC1CLR_CH3C_Msk
Definition: tle987x.h:8870
#define SCU_DMAIRC1CLR_CH2C_Msk
Definition: tle987x.h:8872
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos
Definition: tle987x.h:8899
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk
Definition: tle987x.h:7940
#define SCU_DMAIEN1_CH3IE_Msk
Definition: tle987x.h:8821
#define SCU_DMAIRC1CLR_CH5C_Msk
Definition: tle987x.h:8866
#define SCU_DMAIEN1_CH4IE_Pos
Definition: tle987x.h:8818
#define SCU_DMAIEN1_CH7IE_Msk
Definition: tle987x.h:8813
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk
Definition: tle987x.h:7925
#define SCU_DMAIRC1CLR_CH8C_Msk
Definition: tle987x.h:8860
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk
Definition: tle987x.h:8900
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos
Definition: tle987x.h:7924
#define SCU_DMAIEN2_SDADCIE_Pos
Definition: tle987x.h:8827
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos
Definition: tle987x.h:7939
#define SCU_DMAIRC2CLR_GPT12C_Msk
Definition: tle987x.h:8894
#define SCU_DMAIEN2_TRSEQ1RDYIE_Msk
Definition: tle987x.h:8838
#define SCU_DMAIEN1_CH4IE_Msk
Definition: tle987x.h:8819
#define SCU_DMAIEN2_SSCRXIE_Msk
Definition: tle987x.h:8832
#define SCU_DMAIRC1CLR_CH6C_Pos
Definition: tle987x.h:8863
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos
Definition: tle987x.h:7948
#define SCU_DMAIEN2_GPT12IE_Msk
Definition: tle987x.h:8830
#define SCU_DMAIEN1_CH5IE_Msk
Definition: tle987x.h:8817
#define SCU_DMAIRC2CLR_SSC2C_Msk
Definition: tle987x.h:8896
#define SCU_DMAIEN2_SSCRXIE_Pos
Definition: tle987x.h:8831
#define SCU_DMAIRC1CLR_CH6C_Msk
Definition: tle987x.h:8864
#define SCU_DMAIRC2CLR_GPT12C_Pos
Definition: tle987x.h:8893
#define SCU_DMAIEN1_CH6IE_Pos
Definition: tle987x.h:8814
#define SCU_DMAIEN1_CH8IE_Pos
Definition: tle987x.h:8810
#define SCU_DMAIEN1_CH2IE_Msk
Definition: tle987x.h:8823
#define SCU_DMAIEN2_TRSEQ2RDYIE_Msk
Definition: tle987x.h:8836
#define SCU_DMAIEN2_TRSEQ1RDYIE_Pos
Definition: tle987x.h:8837
#define SCU_DMAIEN1_CH1IE_Pos
Definition: tle987x.h:8824
#define SCU_DMAIRC1CLR_CH4C_Msk
Definition: tle987x.h:8868
#define SCU_DMAIRC2CLR_SSC2C_Pos
Definition: tle987x.h:8895
#define SCU_DMAIRC2CLR_SDADCC_Msk
Definition: tle987x.h:8892
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk
Definition: tle987x.h:8902
#define SCU_DMAIEN2_SSCTXIE_Msk
Definition: tle987x.h:8834
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk
Definition: tle987x.h:7919
#define SCU_DMAIRC1CLR_CH3C_Pos
Definition: tle987x.h:8869
SFR low level access library.
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:362
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:352
This structure lists the DMA transfer memory locations.
Definition: dma.h:251
uint32 Dst_End_Ptr
Definition: dma.h:253
uint32 Src_End_Ptr
Definition: dma.h:252
uint32 reserved
Definition: dma.h:255
TControl Control
Definition: dma.h:254
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:148
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint32_t uint32
32 bit unsigned value
Definition: types.h:155
This structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:230
uint32 Dst_Inc
Bit[31..30].
Definition: dma.h:243
uint32 Cycle_Ctrl
Bit[2..0].
Definition: dma.h:234
uint32 R_Power
Bit[17..14].
Definition: dma.h:237
uint32 Src_Prot_Ctrl
Bit[20..18].
Definition: dma.h:238
uint32 Dst_Size
Bit[29..28].
Definition: dma.h:242
uint32 Next_UseBurst
Bit[3].
Definition: dma.h:235
uint32 Src_Inc
Bit[27..26].
Definition: dma.h:241
uint32 Dst_Prot_Ctrl
Bit[23..21].
Definition: dma.h:239
uint32 N_Minus_1
Bit[13..4].
Definition: dma.h:236
uint32 reg
Definition: dma.h:231
uint32 Src_Size
Bit[25..24].
Definition: dma.h:240