Infineon MOTIX™ MCU TLE987x Device Family SDK
Data Fields
PORT_Type Struct Reference

Detailed Description

GPIO PORTs (PORT)

#include <tle987x.h>

Data Fields

union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P0_DATA
 
__IM uint8_t RESERVED [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P0_DIR
 
__IM uint8_t RESERVED1 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P1_DATA
 
__IM uint8_t RESERVED2 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P1_DIR
 
__IM uint8_t RESERVED3 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   P0: 1
 
      __IM   uint8_t: 1
 
      __IM uint8_t   P2: 1
 
      __IM uint8_t   P3: 1
 
      __IM uint8_t   P4: 1
 
      __IM uint8_t   P5: 1
 
   }   bit
 
P2_DATA
 
__IM uint8_t RESERVED4 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
      __IOM uint8_t   P5: 1
 
   }   bit
 
P2_DIR
 
__IM uint8_t RESERVED5 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P0_PUDSEL
 
__IM uint8_t RESERVED6 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P0_PUDEN
 
__IM uint8_t RESERVED7 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P1_PUDSEL
 
__IM uint8_t RESERVED8 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P1_PUDEN
 
__IM uint8_t RESERVED9 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
      __IOM uint8_t   P5: 1
 
   }   bit
 
P2_PUDSEL
 
__IM uint8_t RESERVED10 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
      __IOM uint8_t   P5: 1
 
   }   bit
 
P2_PUDEN
 
__IM uint8_t RESERVED11 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P0_ALTSEL0
 
__IM uint8_t RESERVED12 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P0_ALTSEL1
 
__IM uint8_t RESERVED13 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P1_ALTSEL0
 
__IM uint8_t RESERVED14 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P1_ALTSEL1
 
__IM uint8_t RESERVED15 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P2: 1
 
      __IOM uint8_t   P3: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P0_OD
 
__IM uint8_t RESERVED16 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 1
 
      __IOM uint8_t   P0: 1
 
      __IOM uint8_t   P1: 1
 
      __IOM uint8_t   P3_P2: 1
 
      __IOM uint8_t   P4: 1
 
   }   bit
 
P1_OD
 

Field Documentation

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struct { ... } bit

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struct { ... } bit

◆ P0 [1/2]

[0..0] Port 0 Pin 0 Data Value

[0..0] Port 0 Pin 0 Direction Control

[0..0] Port 1 Pin 0 Data Value

[0..0] Port 1 Pin 0 Direction Control

[0..0] Port 2 Pin 0 Driver Control

[0..0] Pull-Up/Pull-Down Select Port 0 Bit 0

[0..0] Pull-Up/Pull-Down Enable at Port 0 Bit 0

[0..0] Pull-Up/Pull-Down Select Port 1 Bit 0

[0..0] Pull-Up/Pull-Down Enable at Port 1 Bit 0

[0..0] Pull-Up/Pull-Down Select Port 2 Bit 0

[0..0] Pull-Up/Pull-Down Enable at Port 2 Bit 0

[0..0] Alternate Select Port 0 Bit 0

[0..0] Alternate Select Port 1 Bit 0

[0..0] Port 0 Pin 0 Open Drain Mode

[1..1] P1.0 Open Drain Mode

◆ P0 [2/2]

[0..0] Port 2 Pin 0 Data Value

◆ 

union { ... } P0_ALTSEL0

◆ 

union { ... } P0_ALTSEL1

◆ 

union { ... } P0_DATA

◆ 

union { ... } P0_DIR

◆ 

union { ... } P0_OD

◆ 

union { ... } P0_PUDEN

◆ 

union { ... } P0_PUDSEL

◆ P1

[1..1] Port 0 Pin 1 Data Value

[1..1] Port 0 Pin 1 Direction Control

[1..1] Port 1 Pin 1 Data Value

[1..1] Port 1 Pin 1 Direction Control

[1..1] Pull-Up/Pull-Down Select Port 0 Bit 1

[1..1] Pull-Up/Pull-Down Enable at Port 0 Bit 1

[1..1] Pull-Up/Pull-Down Select Port 1 Bit 1

[1..1] Pull-Up/Pull-Down Enable at Port 1 Bit 1

[1..1] Alternate Select Port 0 Bit 1

[1..1] Alternate Select Port 1 Bit 1

[1..1] Port 0 Pin 1 Open Drain Mode

[2..2] P1.1 Open Drain Mode

◆ 

union { ... } P1_ALTSEL0

◆ 

union { ... } P1_ALTSEL1

◆ 

union { ... } P1_DATA

◆ 

union { ... } P1_DIR

◆ 

union { ... } P1_OD

◆ 

union { ... } P1_PUDEN

◆ 

union { ... } P1_PUDSEL

◆ P2 [1/2]

[2..2] Port 0 Pin 2 Data Value

[2..2] Port 0 Pin 2 Direction Control

[2..2] Port 1 Pin 2 Data Value

[2..2] Port 1 Pin 2 Direction Control

[2..2] Port 2 Pin 2 Driver Control

[2..2] Pull-Up/Pull-Down Select Port 0 Bit 2

[2..2] Pull-Up/Pull-Down Enable at Port 0 Bit 2

[2..2] Pull-Up/Pull-Down Select Port 1 Bit 2

[2..2] Pull-Up/Pull-Down Enable at Port 1 Bit 2

[2..2] Pull-Up/Pull-Down Select Port 2 Bit 2

[2..2] Pull-Up/Pull-Down Enable at Port 2 Bit 2

[2..2] Alternate Select Port 0 Bit 2

[2..2] Alternate Select Port 1 Bit 2

[2..2] Port 0 Pin 2 Open Drain Mode

◆ P2 [2/2]

[2..2] Port 2 Pin 2 Data Value

◆ 

union { ... } P2_DATA

◆ 

union { ... } P2_DIR

◆ 

union { ... } P2_PUDEN

◆ 

union { ... } P2_PUDSEL

◆ P3 [1/2]

[3..3] Port 0 Pin 3 Data Value

[3..3] Port 0 Pin 3 Direction Control

[3..3] Port 1 Pin 3 Data Value

[3..3] Port 1 Pin 3 Direction Control

[3..3] Port 2 Pin 3 Driver Control

[3..3] Pull-Up/Pull-Down Select Port 0 Bit 3

[3..3] Pull-Up/Pull-Down Enable at Port 0 Bit 3

[3..3] Pull-Up/Pull-Down Select Port 1 Bit 3

[3..3] Pull-Up/Pull-Down Enable at Port 1 Bit 3

[3..3] Pull-Up/Pull-Down Select Port 2 Bit 3

[3..3] Pull-Up/Pull-Down Enable at Port 2 Bit 3

[3..3] Alternate Select Port 0 Bit 3

[3..3] Alternate Select Port 1 Bit 3

[3..3] Port 0 Pin 3 Open Drain Mode

◆ P3 [2/2]

[3..3] Port 2 Pin 3 Data Value

◆ P3_P2

__IOM uint8_t P3_P2

[3..3] P1.3/P1.2 Open Drain Mode

◆ P4 [1/2]

[4..4] Port 0 Pin 4 Data Value

[4..4] Port 0 Pin 4 Direction Control

[4..4] Port 1 Pin 4 Data Value

[4..4] Port 1 Pin 4 Direction Control

[4..4] Port 2 Pin 4 Driver Control

[4..4] Pull-Up/Pull-Down Select Port 0 Bit 4

[4..4] Pull-Up/Pull-Down Enable at Port 0 Bit 4

[4..4] Pull-Up/Pull-Down Select Port 1 Bit 4

[4..4] Pull-Up/Pull-Down Enable at Port 1 Bit 4

[4..4] Pull-Up/Pull-Down Select Port 2 Bit 4

[4..4] Pull-Up/Pull-Down Enable at Port 2 Bit 4

[4..4] Alternate Select Port 0 Bit 4

[4..4] Alternate Select Port 1 Bit 4

[4..4] Port 0 Pin 4 Open Drain Mode

[4..4] P1.4 Open Drain Mode

◆ P4 [2/2]

[4..4] Port 2 Pin 4 Data Value

◆ P5 [1/2]

[5..5] Port 2 Pin 5 Data Value

◆ P5 [2/2]

[5..5] Port 2 Pin 5 Driver Control

[5..5] Pull-Up/Pull-Down Select Port 2 Bit 5

[5..5] Pull-Up/Pull-Down Enable at Port 2 Bit 5

◆ reg

(@ 0x00000000) Port 0 Data Register

(@ 0x00000004) Port 0 Direction Register

(@ 0x00000008) Port 1 Data Register

(@ 0x0000000C) Port 1 Direction Register

(@ 0x00000010) Port 2 Data Register

(@ 0x00000014) Port 2 Direction Register

(@ 0x00000018) Port 0 Pull-Up/Pull-Down Select Register

(@ 0x0000001C) Port 0 Pull-Up/Pull-Down Enable Register

(@ 0x00000020) Port 1 Pull-Up/Pull-Down Select Register

(@ 0x00000024) Port 1 Pull-Up/Pull-Down Enable Register

(@ 0x00000028) Port 2 Pull-Up/Pull-Down Select Register

(@ 0x0000002C) Port 2 Pull-Up/Pull-Down Enable Register

(@ 0x00000030) Port 0 Alternate Select Register

(@ 0x00000034) Port 0 Alternate Select Register

(@ 0x00000038) Port 1 Alternate Select Register

(@ 0x0000003C) Port 1 Alternate Select Register

(@ 0x00000040) Port 0 Open Drain Control Register

(@ 0x00000044) Port 1 Open Drain Control Register

◆ RESERVED

__IM uint8_t RESERVED[3]

◆ RESERVED1

__IM uint8_t RESERVED1[3]

◆ RESERVED10

__IM uint8_t RESERVED10[3]

◆ RESERVED11

__IM uint8_t RESERVED11[3]

◆ RESERVED12

__IM uint8_t RESERVED12[3]

◆ RESERVED13

__IM uint8_t RESERVED13[3]

◆ RESERVED14

__IM uint8_t RESERVED14[3]

◆ RESERVED15

__IM uint8_t RESERVED15[3]

◆ RESERVED16

__IM uint8_t RESERVED16[3]

◆ RESERVED2

__IM uint8_t RESERVED2[3]

◆ RESERVED3

__IM uint8_t RESERVED3[3]

◆ RESERVED4

__IM uint8_t RESERVED4[3]

◆ RESERVED5

__IM uint8_t RESERVED5[3]

◆ RESERVED6

__IM uint8_t RESERVED6[3]

◆ RESERVED7

__IM uint8_t RESERVED7[3]

◆ RESERVED8

__IM uint8_t RESERVED8[3]

◆ RESERVED9

__IM uint8_t RESERVED9[3]

◆ uint8_t

__IM uint8_t

The documentation for this struct was generated from the following file: