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Infineon MOTIX™ MCU TLE987x Device Family SDK
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Direct Memeory Access (DMA)
#include <tle987x.h>
union { ... } ALT_CTRL_BASE_PTR |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
union { ... } CFG |
union { ... } CHNL_ENABLE_CLR |
[13..0] CHNL_ENABLE_SET: 0b0=on read: Channel C is disabled., 0b1=on read: Channel C is enabled., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to disable a channel., 0b1=on write: Enables channel C.,
union { ... } CHNL_ENABLE_SET |
union { ... } CHNL_PRI_ALT_CLR |
[13..0] CHNL_PRI_ALT_SET: 0b0=on read: DMA channel C is using the primary data structure., 0b1=on read: DMA channel C is using the alternate data structure., 0b0=on write: No effect. Use the CHNL_PRI_ALT_CLR Register to set bit [C] to 0., 0b1=on write: Selects the alternate data structure for channel C.,
union { ... } CHNL_PRI_ALT_SET |
union { ... } CHNL_PRIORITY_CLR |
[13..0] CHNL_PRIORITY_SET: 0b0=on read: DMA channel C is using the default priority level., 0b1=on read: DMA channel C is using a high priority level., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to set channel C to the default priority level., 0b1=on write: Channel C uses the high priority level.,
union { ... } CHNL_PRIORITY_SET |
union { ... } CHNL_REQ_MASK_CLR |
[13..0] CHNL_REQ_MASK_SET: 0b0=on read: External requests are enabled for channel C., 0b1=on read: External requests are disabled for channel C., 0b0=on write: No effect. Use the CHNL_REQ_MASK_CLR Register to enable DMA requests., 0b1=on write: Disables dma_req[C] and dma_sreq[C] from generating DMA requests.,
union { ... } CHNL_REQ_MASK_SET |
union { ... } CHNL_SW_REQUEST |
union { ... } CHNL_USEBURST_CLR |
[13..0] CHNL_USEBURST_SET: 0b0=on read: DMA channel n responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2, or single, bus transfers., 0b1=on read: DMA channel n does not respond to requests that it receives on dma_req[C] or dma_sreq[C]. The controller only reponds to dma_req[C] requests and performs 2 transfers., 0b0=on write: No effect. Use the CHNL_USEBURST_CLR Register to set bit [C] to 0., 0b1=on write: Disables dma_sreq[C] from generating DMA requests. The controller
union { ... } CHNL_USEBURST_SET |
union { ... } CTRL_BASE_PTR |
[0..0] ERR_CLR: 0b0=on read: dma_err is LOW., 0b1=on read: dma_err is HIGH., 0b0=on write: No effect, status of dma_err is unchanged., 0b1=on write: Sets dma_err LOW.,
union { ... } ERR_CLR |
(@ 0x00000000) DMA Status
(@ 0x00000004) DMA Configuration
(@ 0x00000008) Channel Control Data Base Pointer
(@ 0x0000000C) Channel Alternate Control Data Base Pointer
(@ 0x00000010) Channel Wait on Request Status
(@ 0x00000014) Channel Software Request
(@ 0x00000018) Channel Useburst Set
(@ 0x0000001C) Channel Useburst Clear
(@ 0x00000020) Channel Request Mask Set
(@ 0x00000024) Channel Request Mask Clear
(@ 0x00000028) Channel Enable Set
(@ 0x0000002C) Channel Enable Clear
(@ 0x00000030) Channel Primary-Alternate Set
(@ 0x00000034) Channel Primary-Alternate Clear
(@ 0x00000038) Channel Priority Set
(@ 0x0000003C) Channel Priority Clear
(@ 0x0000004C) Bus Error Clear
union { ... } STATUS |
__IM uint32_t |
union { ... } WAITONREQ_STATUS |