Infineon MOTIX™ MCU TLE987x Device Family SDK
gpt12e.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** BG Blandine Guillot **
44 ** JO Julia Ott **
45 ** VO Vanessa Ongaro **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.1.0: 2014-05-13, DM: Initial version **
52 ** V0.1.1: 2015-01-20, DM: GPT12E timer stop API added **
53 ** V0.1.2: 2015-02-10, DM: Individual header file added **
54 ** V0.1.3: 2015-08-27, DM: Timer readout functions added **
55 ** V0.1.4: 2017-05-26, DM: API extended **
56 ** V0.1.5: 2017-09-29, DM: MISRA 2012 compliance, the following PC-Lint **
57 ** rules are globally deactivated: **
58 ** - Info 793: ANSI/ISO limit of 6 'significant **
59 ** characters in an external identifier **
60 ** - Info 835: A zero has been given as right **
61 ** argument to operator **
62 ** - Info 845: The left argument to operator '&' **
63 ** is certain to be 0 **
64 ** Replaced macros by INLINE functions **
65 ** Replaced register accesses within functions by **
66 ** function calls **
67 ** V0.1.6: 2018-03-14, DM: GPT12E_T5_Capture_Trig_Rising_CapIn_En(), **
68 ** GPT12E_T5_Capture_Trig_Rising_CapIn_Dis(), **
69 ** GPT12E_T5_Capture_Trig_Falling_CapIn_En(), **
70 ** GPT12E_T5_Capture_Trig_Falling_CapIn_Dis(), **
71 ** GPT12E_T5_Capture_Trig_Any_T3In_En(), **
72 ** GPT12E_T5_Capture_Trig_Any_T3In_Dis(), **
73 ** GPT12E_T5_Capture_Trig_Any_T3EUD_En(), **
74 ** GPT12E_T5_Capture_Trig_Any_T3EUD_Dis() **
75 ** modified for MISRA 2012 **
76 ** V0.1.7: 2018-07-05, BG: Values for GPT12E_T4_Start_by_T3_En() and **
77 ** GPT12E_T4_Start_by_T3_Dis() **
78 ** corrected in gpt12e.h **
79 ** V0.1.8: 2018-11-27, JO: Doxygen update **
80 ** Moved revision history from gpt12e.c to gpt12e.h **
81 ** V0.1.9: 2020-04-15, BG: Updated revision history format **
82 ** V0.2.0: 2020-07-21, BG: EP-439: Formatted .h/.c files **
83 ** V0.2.1: 2022-02-28, JO: EP-936: Updated copyright and branding **
84 ** V0.2.2: 2022-10-18, VO: EP-1252: Updated enum definitions **
85 *******************************************************************************/
86 
87 #ifndef GPT12E_H
88 #define GPT12E_H
89 
90 /*******************************************************************************
91 ** Includes **
92 *******************************************************************************/
93 #include "tle987x.h"
94 #include "types.h"
95 #include "sfr_access.h"
96 #include "gpt12e_defines.h"
97 
98 /*******************************************************************************
99 ** Global Type Definitions **
100 *******************************************************************************/
104 typedef enum GPT1_Clk_Prescaler
105 {
109  GPT1_fSYS_Div_32 = 2u
111 
115 typedef enum GPT12E_CCU6_SEL
116 {
128  GPT12E_CCU6_ANY_CHx = 11u
130 
134 typedef enum GPT12E_T2IN
135 {
137  GPT12E_T2INB_P14 = 1u
139 
143 typedef enum GPT12E_T2EUD
144 {
146  GPT12E_T2EUDB_P24 = 1u
148 
152 typedef enum GPT12E_T3IN
153 {
157  GPT12E_T3IND_MON = 3u
159 
163 typedef enum GPT12E_T3EUD
164 {
166  GPT12E_T3EUDB_P25 = 1u
168 
172 typedef enum GPT12E_T4IN
173 {
179 
183 typedef enum GPT12E_T4EUD
184 {
186  GPT12E_T4EUDB_P10 = 1u
188 
192 typedef enum GPT2_Clk_Prescaler
193 {
197  GPT2_fSYS_Div_16 = 2u
199 
203 typedef enum GPT12E_T5IN
204 {
206  GPT12E_T5INB_P20 = 1u
208 
212 typedef enum GPT12E_T5EUD
213 {
215  GPT12E_T5EUDB_P20 = 1u
217 
221 typedef enum GPT12E_T6IN
222 {
224  GPT12E_T6INB_P13 = 1u
226 
230 typedef enum GPT12E_T6EUD
231 {
233  GPT12E_T6EUDB_P13 = 1u
235 
239 typedef enum GPT12E_CAPIN
240 {
246 
251 {
259  GPT_Clk_Div_128 = 7
261 
262 
263 /*******************************************************************************
264 ** Global Inline Function Definitions **
265 *******************************************************************************/
281 {
283 }
284 
302 {
304 }
305 
321 {
323 }
324 
325 /****************************************************************************/
326 /* Timer2 *******************************************************************/
327 /****************************************************************************/
341 {
343 }
344 
358 {
360 }
361 
375 {
377 }
378 
392 {
394 }
395 
409 {
411 }
412 
426 {
428 }
429 
443 {
445 }
446 
460 {
462 }
463 
480 {
482 }
483 
500 {
502 }
503 
518 {
519  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
520 }
521 
536 {
537  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
538 }
539 
554 {
555  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
556 }
557 
572 {
573  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
574 }
575 
590 {
591  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
592 }
593 
608 {
609  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 1u);
610 }
611 
626 {
627  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
628 }
629 
644 {
645  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
646 }
647 
662 {
663  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
664 }
665 
680 {
681  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
682 }
683 
698 {
699  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
700 }
701 
716 {
717  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
718 }
719 
734 {
735  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
736 }
737 
752 {
753  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
754 }
755 
770 {
771  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
772 }
773 
788 {
789  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
790 }
791 
806 {
807  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
808 }
809 
824 {
825  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
826 }
827 
842 {
843  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
844 }
845 
860 {
861  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
862 }
863 
878 {
879  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 1u);
880 }
881 
896 {
897  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
898 }
899 
914 {
915  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
916 }
917 
932 {
933  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
934 }
935 
950 {
951  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
952 }
953 
968 {
969  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
970 }
971 
986 {
987  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
988 }
989 
1004 {
1005  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
1006 }
1007 
1022 {
1023  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
1024 }
1025 
1040 {
1041  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
1042 }
1043 
1058 {
1060 }
1061 
1076 {
1078 }
1079 
1094 {
1096 }
1097 
1112 {
1114 }
1115 
1130 {
1132 }
1133 
1148 {
1150 }
1151 
1165 {
1167 }
1168 
1183 {
1185 }
1186 
1201 {
1203 }
1204 
1219 {
1221 }
1222 
1242 {
1244 }
1245 
1263 {
1265 }
1266 
1286 {
1288 }
1289 
1307 {
1309 }
1310 
1328 {
1330 }
1331 
1347 {
1349 }
1350 
1368 {
1370 }
1371 
1388 {
1390 }
1391 
1392 /****************************************************************************/
1393 /* Timer3 * Core Timer ******************************************************/
1394 /****************************************************************************/
1408 {
1410 }
1411 
1425 {
1427 }
1428 
1442 {
1444 }
1445 
1459 {
1461 }
1462 
1476 {
1478 }
1479 
1493 {
1495 }
1496 
1513 {
1515 }
1516 
1533 {
1535 }
1536 
1551 {
1552  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 1u);
1553 }
1554 
1569 {
1570  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 0u);
1571 }
1572 
1587 {
1588  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 1u);
1589 }
1590 
1605 {
1606  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 0u);
1607 }
1608 
1623 {
1624  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 1u);
1625 }
1626 
1641 {
1642  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 0u);
1643 }
1644 
1659 {
1660  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 1u);
1661 }
1662 
1677 {
1678  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 0u);
1679 }
1680 
1694 {
1696 }
1697 
1711 {
1713 }
1714 
1728 {
1730 }
1731 
1745 {
1747 }
1748 
1763 {
1765 }
1766 
1781 {
1783 }
1784 
1799 {
1801 }
1802 
1817 {
1819 }
1820 
1834 {
1836 }
1837 
1852 {
1854 }
1855 
1870 {
1872 }
1873 
1888 {
1890 }
1891 
1911 {
1913 }
1914 
1932 {
1934 }
1935 
1955 {
1957 }
1958 
1976 {
1978 }
1979 
1997 {
1999 }
2000 
2016 {
2018 }
2019 
2037 {
2039 }
2040 
2057 {
2059 }
2060 
2061 /****************************************************************************/
2062 /* Timer4 *******************************************************************/
2063 /****************************************************************************/
2077 {
2079 }
2080 
2094 {
2096 }
2097 
2111 {
2113 }
2114 
2128 {
2130 }
2131 
2145 {
2147 }
2148 
2162 {
2164 }
2165 
2179 {
2181 }
2182 
2196 {
2198 }
2199 
2216 {
2218 }
2219 
2236 {
2238 }
2239 
2254 {
2255  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2256 }
2257 
2272 {
2273  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2274 }
2275 
2290 {
2291  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2292 }
2293 
2308 {
2309  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2310 }
2311 
2326 {
2327  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2328 }
2329 
2344 {
2345  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 1u);
2346 }
2347 
2362 {
2363  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2364 }
2365 
2380 {
2381  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2382 }
2383 
2398 {
2399  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2400 }
2401 
2416 {
2417  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2418 }
2419 
2434 {
2435  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2436 }
2437 
2452 {
2453  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2454 }
2455 
2470 {
2471  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2472 }
2473 
2488 {
2489  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2490 }
2491 
2506 {
2507  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2508 }
2509 
2524 {
2525  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2526 }
2527 
2542 {
2543  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2544 }
2545 
2560 {
2561  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2562 }
2563 
2578 {
2579  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2580 }
2581 
2596 {
2597  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2598 }
2599 
2614 {
2615  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 1u);
2616 }
2617 
2632 {
2633  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2634 }
2635 
2650 {
2651  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2652 }
2653 
2668 {
2669  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2670 }
2671 
2686 {
2687  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2688 }
2689 
2704 {
2705  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2706 }
2707 
2722 {
2723  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2724 }
2725 
2740 {
2741  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2742 }
2743 
2758 {
2759  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2760 }
2761 
2776 {
2778 }
2779 
2794 {
2796 }
2797 
2812 {
2814 }
2815 
2830 {
2832 }
2833 
2848 {
2850 }
2851 
2866 {
2868 }
2869 
2883 {
2885 }
2886 
2901 {
2903 }
2904 
2919 {
2921 }
2922 
2937 {
2939 }
2940 
2956 {
2958 }
2959 
2973 {
2975 }
2976 
2992 {
2994 }
2995 
3009 {
3011 }
3012 
3032 {
3034 }
3035 
3053 {
3055 }
3056 
3076 {
3078 }
3079 
3097 {
3099 }
3100 
3118 {
3120 }
3121 
3137 {
3139 }
3140 
3158 {
3160 }
3161 
3178 {
3180 }
3181 
3182 /****************************************************************************/
3183 /* GPT2 *******************************************************************/
3184 /****************************************************************************/
3200 {
3202 }
3203 
3221 {
3223 }
3224 
3225 /****************************************************************************/
3226 /* Timer5 *******************************************************************/
3227 /****************************************************************************/
3241 {
3243 }
3244 
3258 {
3260 }
3261 
3275 {
3277 }
3278 
3292 {
3294 }
3295 
3312 {
3314 }
3315 
3332 {
3334 }
3335 
3350 {
3351  Field_Mod16(&GPT12E->T5CON.reg, 2u, 4u, 0u);
3352 }
3353 
3368 {
3369  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 1u);
3370 }
3371 
3386 {
3387  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 1u);
3388 }
3389 
3404 {
3405  Field_Mod16(&GPT12E->T5CON.reg, 0u, 3u, 3u);
3406 }
3407 
3422 {
3423  Field_Mod16(&GPT12E->T5CON.reg, 2u, 4u, 1u);
3424 }
3425 
3440 {
3441  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 1u);
3442 }
3443 
3458 {
3459  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 0u);
3460 }
3461 
3476 {
3477  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 1u);
3478 }
3479 
3494 {
3495  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 0u);
3496 }
3497 
3511 {
3513 }
3514 
3528 {
3530 }
3531 
3546 {
3548 }
3549 
3565 {
3566  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 1u);
3567 }
3568 
3584 {
3585  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 0u);
3586 }
3587 
3603 {
3604  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 1u);
3605 }
3606 
3622 {
3623  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 0u);
3624 }
3625 
3640 {
3642 }
3643 
3659 {
3660  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 1u);
3661 }
3662 
3678 {
3679  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 0u);
3680 }
3681 
3697 {
3698  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 1u);
3699 }
3700 
3716 {
3717  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 0u);
3718 }
3719 
3734 {
3736 }
3737 
3752 {
3754 }
3755 
3774 {
3776 }
3777 
3792 {
3794 }
3795 
3810 {
3812 }
3813 
3828 {
3830 }
3831 
3846 {
3848 }
3849 
3864 {
3866 }
3867 
3882 {
3884 }
3885 
3899 {
3901 }
3902 
3917 {
3919 }
3920 
3938 {
3940 }
3941 
3957 {
3959 }
3960 
3978 {
3980 }
3981 
3998 {
4000 }
4001 
4002 /****************************************************************************/
4003 /* Timer6 *******************************************************************/
4004 /****************************************************************************/
4018 {
4020 }
4021 
4035 {
4037 }
4038 
4052 {
4054 }
4055 
4069 {
4071 }
4072 
4089 {
4091 }
4092 
4109 {
4111 }
4112 
4127 {
4128  Field_Mod16(&GPT12E->T6CON.reg, (uint16)2u, (uint16)4u, 0u);
4129 }
4130 
4145 {
4146  Field_Mod16(&GPT12E->T6CON.reg, (uint16)0u, (uint16)1u, 1u);
4147 }
4148 
4163 {
4164  Field_Mod16(&GPT12E->T6CON.reg, (uint16)1u, (uint16)2u, 1u);
4165 }
4166 
4181 {
4182  Field_Mod16(&GPT12E->T6CON.reg, (uint16)0u, (uint16)3u, 3u);
4183 }
4184 
4198 {
4200 }
4201 
4215 {
4217 }
4218 
4235 {
4237 }
4238 
4253 {
4255 }
4256 
4271 {
4273 }
4274 
4288 {
4290 }
4291 
4305 {
4307 }
4308 
4322 {
4324 }
4325 
4339 {
4341 }
4342 
4357 {
4359 }
4360 
4375 {
4377 }
4378 
4393 {
4395 }
4396 
4411 {
4413 }
4414 
4428 {
4430 }
4431 
4446 {
4448 }
4449 
4467 {
4469 }
4470 
4486 {
4488 }
4489 
4507 {
4509 }
4510 
4527 {
4529 }
4530 
4531 /****************************************************************************/
4532 /* CAPREL *******************************************************************/
4533 /****************************************************************************/
4552 {
4554 }
4555 
4556 /****************************************************************************/
4557 /* Interrupt ****************************************************************/
4558 /****************************************************************************/
4579 {
4580  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T2_Pos, (uint8)SCU_GPT12IRC_T2_Msk) );
4581 }
4582 
4603 {
4604  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T3_Pos, (uint8)SCU_GPT12IRC_T3_Msk) );
4605 }
4606 
4627 {
4628  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T4_Pos, (uint8)SCU_GPT12IRC_T4_Msk) );
4629 }
4630 
4651 {
4652  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T5_Pos, (uint8)SCU_GPT12IRC_T5_Msk) );
4653 }
4654 
4675 {
4676  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T6_Pos, (uint8)SCU_GPT12IRC_T6_Msk) );
4677 }
4678 
4699 {
4700  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_CR_Pos, (uint8)SCU_GPT12IRC_CR_Msk) );
4701 }
4702 
4703 /* GPT12E Interrupt Clear Macros */
4723 {
4725 }
4726 
4746 {
4748 }
4749 
4769 {
4771 }
4772 
4792 {
4794 }
4795 
4815 {
4817 }
4818 
4838 {
4840 }
4841 
4861 {
4863 }
4864 
4884 {
4886 }
4887 
4907 {
4909 }
4910 
4930 {
4932 }
4933 
4953 {
4955 }
4956 
4976 {
4978 }
4979 
4999 {
5001 }
5002 
5022 {
5024 }
5025 
5045 {
5047 }
5048 
5068 {
5070 }
5071 
5091 {
5093 }
5094 
5114 {
5116 }
5117 
5118 /*******************************************************************************
5119 ** Global Function Declarations **
5120 *******************************************************************************/
5125 void GPT12E_Init(void);
5126 
5146 bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us);
5147 
5165 bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us);
5166 
5167 #endif
INLINE void GPT12E_T3_Int_Clr(void)
clears GPT Module 1 Timer 3 interrupt flag.
Definition: gpt12e.h:4745
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:661
INLINE void GPT12E_T4_Mode_Counter_Input_T4In_Sel(void)
selects T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2253
INLINE void GPT12E_T6_Mode_Timer_Sel(void)
selects T6 Timer Mode.
Definition: gpt12e.h:4017
INLINE void GPT12E_T6_T6EUD_Sel(uint16 ist6eud)
selects Input for T6EUD.
Definition: gpt12e.h:4526
INLINE void GPT12E_T2_Mode_IncEnc_Input_Sel(void)
selects T2 Incremental Interface Mode Input.
Definition: gpt12e.h:967
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:949
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:643
INLINE void GPT12E_T2_Int_En(void)
enables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:4860
INLINE void GPT12E_T4_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T4 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:2918
void GPT12E_Init(void)
Initializes the GPT12E module based on the Config Wizard for MOTIX MCU configuration.
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2451
INLINE void GPT12E_T5_Mode_Timer_Clk_Prescaler_Sel(uint16 t5i)
selects T5 Timer Mode Parameter.
Definition: gpt12e.h:3311
INLINE void GPT12E_T2_T2In_Sel(uint16 ist2in)
selects Input for T2IN.
Definition: gpt12e.h:1367
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:823
INLINE void GPT12E_T4_Mode_IncEnc_Rot_Sel(void)
selects T4 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:2178
INLINE void GPT12E_T3_T4_CCU6_Sel(uint8 gpt)
selects GPT12 TIN3B/TIN4D Input.
Definition: gpt12e.h:320
INLINE void GPT12E_T4_Mode_Counter_Input_T3Out_Sel(void)
selects T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2343
INLINE void GPT12E_T2_DownCount_Sel(void)
selects Timer T2 counts down.
Definition: gpt12e.h:1129
INLINE void GPT12E_GPT1_Clk_Prescaler_Sel(uint16 bps1)
selects GPT1 Clock Prescaler.
Definition: gpt12e.h:280
INLINE void GPT12E_T4_Mode_Capture_Sel(void)
selects T4 Capture Mode.
Definition: gpt12e.h:2161
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:733
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:895
GPT2_Clk_Prescaler
Definition: gpt12e.h:193
@ GPT2_fSYS_Div_16
Definition: gpt12e.h:197
@ GPT2_fSYS_Div_2
Definition: gpt12e.h:194
@ GPT2_fSYS_Div_4
Definition: gpt12e.h:195
@ GPT2_fSYS_Div_8
Definition: gpt12e.h:196
INLINE void GPT12E_T5_Capture_En(void)
enables T5 Capture Mode.
Definition: gpt12e.h:3510
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2739
INLINE void GPT12E_T2_Mode_Timer_Sel(void)
selects T2 Timer Mode.
Definition: gpt12e.h:340
INLINE uint8 GPT12E_T2_Int_Sts(void)
reads GPT Module 1 Timer 2 interrupt Status.
Definition: gpt12e.h:4578
INLINE void GPT12E_T5_Capture_Trig_T3In_T3EUD_Sel(void)
selects T3In and/or T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3639
GPT12E_T5IN
Definition: gpt12e.h:204
@ GPT12E_T5INB_P20
Definition: gpt12e.h:206
@ GPT12E_T5INA_P03
Definition: gpt12e.h:205
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:931
INLINE uint8 GPT12E_T6_Int_Sts(void)
reads GPT Module 2 Timer 6 interrupt Status.
Definition: gpt12e.h:4674
INLINE void GPT12E_T4_Clr_T2_En(void)
Enables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2955
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2577
enum GPT12E_T3EUD TGPT12E_T3EUD
enum GPT12E_CCU6_SEL TGPT12E_CCU6_SEL
INLINE void GPT12E_T6_Output_Set(void)
sets Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:4356
INLINE void GPT12E_T6_Start(void)
starts Timer T6.
Definition: gpt12e.h:4287
INLINE void GPT12E_T2_Mode_Gated_Timer_High_Sel(void)
selects T2 Gated high Mode.
Definition: gpt12e.h:391
INLINE uint8 GPT12E_T2_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:1285
INLINE uint8 GPT12E_T3_Int_Sts(void)
reads GPT Module 1 Timer 3 interrupt Status.
Definition: gpt12e.h:4602
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_Dis(void)
disables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3457
INLINE void GPT12E_T6_Reload_Value_Set(uint16 rl)
sets Current T6 Reload Value.
Definition: gpt12e.h:4234
INLINE void GPT12E_T3_UpCount_Sel(void)
selects Timer T3 counts up.
Definition: gpt12e.h:1816
INLINE void GPT12E_T3_Output_Rst(void)
clears Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:1780
INLINE void GPT12E_T4_Mode_Timer_Sel(void)
selects T4 Timer Mode.
Definition: gpt12e.h:2076
INLINE void GPT12E_T4_Clr_T3_En(void)
Enables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2991
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_En(void)
enables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3564
INLINE void GPT12E_CapRel_Int_Clr(void)
clears GPT Module 1 Capture Reload interrupt flag.
Definition: gpt12e.h:4837
INLINE uint16 GPT12E_T5_Capture_Value_Get(void)
reads Current T5 Capture Value.
Definition: gpt12e.h:3773
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2379
INLINE void GPT12E_T6_Stop(void)
stops Timer T6.
Definition: gpt12e.h:4304
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Sel(void)
selects T4 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:2195
INLINE void GPT12E_T2_Mode_IncEnc_Rot_Sel(void)
selects T2 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:442
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2559
INLINE void GPT12E_T4_Mode_Gated_Timer_High_Sel(void)
selects T4 Gated high Mode.
Definition: gpt12e.h:2127
INLINE void GPT12E_T3_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t3i)
selects T3 Gated Timer Mode Parameter.
Definition: gpt12e.h:1532
INLINE void GPT12E_T4_Start(void)
starts Timer T4.
Definition: gpt12e.h:2775
INLINE void GPT12E_T2_T2EUD_Sel(uint16 ist2eud)
selects Input for T2EUD.
Definition: gpt12e.h:1387
INLINE void GPT12E_T3_Mode_Timer_Clk_Prescaler_Sel(uint16 t3i)
selects T3 Timer Mode Parameter.
Definition: gpt12e.h:1512
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_Dis(void)
disables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3715
INLINE void GPT12E_T6_Mode_Gated_Timer_High_Sel(void)
selects T6 Gated high Mode.
Definition: gpt12e.h:4068
INLINE void GPT12E_T4_Stop(void)
stops Timer T4.
Definition: gpt12e.h:2793
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1262
INLINE void GPT12E_T2_Mode_Reload_Sel(void)
selects T2 Reload Mode.
Definition: gpt12e.h:408
INLINE void GPT12E_T6_On_Capture_Cleared_En(void)
enables clearing T6 on a Capture Event.
Definition: gpt12e.h:4252
INLINE void GPT12E_T3_Mode_Timer_Sel(void)
selects T3 Timer Mode.
Definition: gpt12e.h:1407
INLINE void GPT12E_T4_Mode_Reload_Input_T4In_Sel(void)
selects T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2523
INLINE void GPT12E_T5_Int_Dis(void)
disables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:5021
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:571
INLINE void GPT12E_T6_Mode_Counter_Input_Rising_T6In_Sel(void)
selects Rising Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4144
INLINE void GPT12E_T2_Value_Set(uint16 t2)
sets Timer T2 Value.
Definition: gpt12e.h:1346
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1640
enum GPT1_Clk_Prescaler TGPT1_Clk_Prescaler
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_Dis(void)
disables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:3677
INLINE void GPT12E_T3_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:1975
INLINE void GPT12E_T4_Mode_Counter_Sel(void)
selects T4 Counter Mode.
Definition: gpt12e.h:2093
INLINE void GPT12E_T3_Int_En(void)
enables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:4906
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2271
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2397
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2325
INLINE uint8 GPT12E_T5_Int_Sts(void)
reads GPT Module 2 Timer 5 interrupt Status.
Definition: gpt12e.h:4650
GPT12E_T2EUD
Definition: gpt12e.h:144
@ GPT12E_T2EUDA_P02
Definition: gpt12e.h:145
@ GPT12E_T2EUDB_P24
Definition: gpt12e.h:146
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2631
GPT12E_T5EUD
Definition: gpt12e.h:213
@ GPT12E_T5EUDA_P14
Definition: gpt12e.h:214
@ GPT12E_T5EUDB_P20
Definition: gpt12e.h:215
INLINE void GPT12E_T3_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:1851
INLINE void GPT12E_T3_Output_Set(void)
sets Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:1762
INLINE void GPT12E_T3_T3EUD_Sel(uint16 ist3eud)
selects Input for T3EUD.
Definition: gpt12e.h:2056
INLINE void GPT12E_T6_UpCount_Sel(void)
selects Timer T6 counts up.
Definition: gpt12e.h:4410
INLINE void GPT12E_T6_Reload_En(void)
enables T6 Reload Mode.
Definition: gpt12e.h:4197
enum GPT12E_T2EUD TGPT12E_T2EUD
INLINE void GPT12E_T4_Start_by_T3_Dis(void)
disables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:2829
INLINE void GPT12E_T2_Start_by_T3_Dis(void)
disables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:1111
bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T6 to be reloaded by CAPREL.
INLINE void GPT12E_T6_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:4427
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:841
INLINE void GPT12E_T4_T4In_Sel(uint16 ist4in)
selects Input for T4IN.
Definition: gpt12e.h:3157
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2307
INLINE uint16 GPT12E_T4_Value_Get(void)
reads Timer T4 Value.
Definition: gpt12e.h:3117
INLINE void GPT12E_T6_Int_Dis(void)
disables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5067
INLINE void GPT12E_T2_Mode_Capture_Input_T2In_Sel(void)
selects T2In as T2 Capture Mode Input.
Definition: gpt12e.h:697
INLINE void GPT12E_T2_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:1182
INLINE void GPT12E_T2_Mode_Gated_Timer_Low_Sel(void)
selects T2 Gated low Mode.
Definition: gpt12e.h:374
INLINE uint8 GPT12E_T3_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:1954
INLINE void GPT12E_T3_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T3 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:1869
INLINE void GPT12E_T3_Value_Set(uint16 t3)
sets Timer T3 Value.
Definition: gpt12e.h:2015
INLINE void GPT12E_T3_DownCount_Sel(void)
selects Timer T3 counts down.
Definition: gpt12e.h:1798
INLINE void GPT12E_T3_T3In_Sel(uint16 ist3in)
selects Input for T3IN.
Definition: gpt12e.h:2036
INLINE void GPT12E_T4_DownCount_Sel(void)
selects Timer T4 counts down.
Definition: gpt12e.h:2847
INLINE void GPT12E_T2_Stop(void)
stops Timer T2.
Definition: gpt12e.h:1075
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_En(void)
enables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1550
INLINE void GPT12E_T6_Int_En(void)
enables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5044
enum GPT12E_CAPIN TGPT12E_CAPIN
INLINE void GPT12E_T5_Mode_Counter_Sel(void)
selects T5 Counter Mode.
Definition: gpt12e.h:3257
INLINE void GPT12E_T6_Mode_Counter_Input_T6In_Sel(void)
selects T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4126
enum GPT12E_T3IN TGPT12E_T3IN
INLINE void GPT12E_T5_Mode_Gated_Timer_High_Sel(void)
selects T5 Gated high Mode.
Definition: gpt12e.h:3291
enum GPT12E_T4IN TGPT12E_T4IN
INLINE void GPT12E_T4_Int_Clr(void)
clears GPT Module 1 Timer 4 interrupt flag.
Definition: gpt12e.h:4768
INLINE void GPT12E_T3_Mode_Gated_Timer_Low_Sel(void)
selects T3 Gated low Mode.
Definition: gpt12e.h:1441
INLINE void GPT12E_T5_Capture_Dis(void)
disables T5 Capture Mode.
Definition: gpt12e.h:3527
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_En(void)
enables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1586
INLINE void GPT12E_T3_Output_En(void)
enables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:1727
GPT12E_T4IN
Definition: gpt12e.h:173
@ GPT12E_T4INB_CCU6_CH0
Definition: gpt12e.h:175
@ GPT12E_T4IND_CCU6_SEL
Definition: gpt12e.h:177
@ GPT12E_T4INC_P01
Definition: gpt12e.h:176
@ GPT12E_T4INA_P00
Definition: gpt12e.h:174
INLINE void GPT12E_T2_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T2 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:1200
INLINE uint16 GPT12E_T6_Value_Get(void)
reads Timer T6 Value.
Definition: gpt12e.h:4466
INLINE void GPT12E_T2_Int_Clr(void)
clears GPT Module 1 Timer 2 interrupt flag.
Definition: gpt12e.h:4722
INLINE void GPT12E_T4_Mode_Timer_Clk_Prescaler_Sel(uint16 t4i)
selects T4 Timer Mode Parameter.
Definition: gpt12e.h:2215
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_En(void)
enables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3439
GPT12E_CAPIN
Definition: gpt12e.h:240
@ GPT12E_CAPIND_T2_T3_T4_READ
Definition: gpt12e.h:244
@ GPT12E_CAPINA_P01
Definition: gpt12e.h:241
@ GPT12E_CAPINC_T3_READ
Definition: gpt12e.h:243
@ GPT12E_CAPINB_P03
Definition: gpt12e.h:242
INLINE void GPT12E_T6_Mode_Counter_Input_Any_T6In_Sel(void)
selects Any Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4180
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_Dis(void)
disables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3493
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2667
INLINE uint16 GPT12E_GPT1_Clk_Prescaler_Get(void)
reads GPT1 Clock Prescaler.
Definition: gpt12e.h:301
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:751
bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T3 to be reloaded by T2.
INLINE void GPT12E_T5_Cleared_On_Capture_Dis(void)
disables clearing T5 on a Capture Event.
Definition: gpt12e.h:3751
INLINE void GPT12E_T3_Mode_Gated_Timer_High_Sel(void)
selects T3 Gated high Mode.
Definition: gpt12e.h:1458
INLINE void GPT12E_T5_Mode_Counter_Input_T5In_Sel(void)
selects T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3349
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1658
INLINE void GPT12E_T5_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:3916
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2541
INLINE void GPT12E_T6_Output_En(void)
enables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:4321
INLINE void GPT12E_T4_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:2882
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:1021
INLINE void GPT12E_T6_Mode_Timer_Clk_Prescaler_Sel(uint16 t6i)
selects T6 Timer Mode Parameter.
Definition: gpt12e.h:4088
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:553
INLINE void GPT12E_T5_T5EUD_Sel(uint16 ist5eud)
selects Input for T5EUD.
Definition: gpt12e.h:3997
INLINE void GPT12E_T4_T4EUD_Sel(uint16 ist4eud)
selects Input for T4EUD.
Definition: gpt12e.h:3177
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_Dis(void)
disables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1568
enum GPT12E_T4EUD TGPT12E_T4EUD
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:589
INLINE void GPT12E_T5_Mode_Counter_Input_Any_T5In_Sel(void)
selects Any Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3403
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2415
INLINE void GPT12E_T3_Mode_IncEnc_Rot_Sel(void)
selects T3 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:1475
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T5In_Sel(void)
selects Rising Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3367
INLINE void GPT12E_T4_Mode_Reload_Sel(void)
selects T4 Reload Mode.
Definition: gpt12e.h:2144
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:985
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_Dis(void)
disables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3583
INLINE uint8 GPT12E_CapRel_Int_Sts(void)
reads GPT Module 1 Capture Reload interrupt Status.
Definition: gpt12e.h:4698
INLINE void GPT12E_T5_Stop(void)
stops Timer T5.
Definition: gpt12e.h:3809
INLINE void GPT12E_T4_Start_by_T3_En(void)
enables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:2811
INLINE void GPT12E_T6_On_Capture_Cleared_Dis(void)
disables clearing T6 on a Capture Event.
Definition: gpt12e.h:4270
INLINE void GPT12E_T5_Int_En(void)
enables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:4998
INLINE void GPT12E_CapRel_CAPIn_Sel(uint16 iscapin)
selects CAPIN.
Definition: gpt12e.h:4551
INLINE uint16 GPT12E_T5_Value_Get(void)
reads Timer T5 Value.
Definition: gpt12e.h:3937
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:535
INLINE void GPT12E_T6_Int_Clr(void)
clears GPT Module 2 Timer 6 interrupt flag.
Definition: gpt12e.h:4814
INLINE void GPT12E_T5_Start_by_T6_En(void)
enables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:3845
INLINE void GPT12E_T4_Value_Set(uint16 t4)
sets Timer T4 Value.
Definition: gpt12e.h:3136
INLINE void GPT12E_T6_Output_Rst(void)
clears Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:4374
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_En(void)
enables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:3658
enum GPT2_Clk_Prescaler TGPT2_Clk_Prescaler
INLINE void GPT12E_T5_Start_by_T6_Dis(void)
disables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:3827
INLINE void GPT12E_T4_Mode_Capture_Input_T4In_Sel(void)
selects T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2433
INLINE void GPT12E_T2_UpCount_Sel(void)
selects Timer T2 counts up.
Definition: gpt12e.h:1147
INLINE void GPT12E_T4_Int_En(void)
enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:4952
INLINE uint16 GPT12E_T2_Value_Get(void)
reads Timer T2 Value.
Definition: gpt12e.h:1327
INLINE void GPT12E_T6_T6In_Sel(uint16 ist6in)
selects Input for T6IN.
Definition: gpt12e.h:4506
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:769
INLINE void GPT12E_T5_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:3898
INLINE void GPT12E_T4_Mode_Gated_Timer_Low_Sel(void)
selects T4 Gated low Mode.
Definition: gpt12e.h:2110
INLINE void GPT12E_T5_Mode_Gated_Timer_Low_Sel(void)
selects T5 Gated low Mode.
Definition: gpt12e.h:3274
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:913
INLINE void GPT12E_T4_Mode_Reload_Input_T3Out_Sel(void)
selects T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2613
INLINE void GPT12E_CapRel_Int_Dis(void)
disables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5113
enum GPT12E_T6IN TGPT12E_T6IN
INLINE void GPT12E_T2_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T2 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:1218
INLINE void GPT12E_T2_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t2i)
selects T2 Gated Timer Mode Parameter.
Definition: gpt12e.h:499
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2721
INLINE void GPT12E_T6_Mode_Gated_Timer_Low_Sel(void)
selects T6 Gated low Mode.
Definition: gpt12e.h:4051
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:859
INLINE void GPT12E_T5_Int_Clr(void)
clears GPT Module 2 Timer 5 interrupt flag.
Definition: gpt12e.h:4791
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2757
INLINE void GPT12E_T2_Start_by_T3_En(void)
enables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:1093
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2487
GPT12E_T3IN
Definition: gpt12e.h:153
@ GPT12E_T3IND_MON
Definition: gpt12e.h:157
@ GPT12E_T3INC_P10
Definition: gpt12e.h:156
@ GPT12E_T3INA_CCU6_CH0
Definition: gpt12e.h:154
@ GPT12E_T3INB_CCU6_SEL
Definition: gpt12e.h:155
INLINE void GPT12E_T6_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:4445
INLINE void GPT12E_T2_Mode_Reload_Input_T3Out_Sel(void)
selects T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:877
INLINE void GPT12E_T6_Reload_Dis(void)
disables T6 Reload Mode.
Definition: gpt12e.h:4214
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:715
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:679
GPT1_Clk_Prescaler
Definition: gpt12e.h:105
@ GPT1_fSYS_Div_32
Definition: gpt12e.h:109
@ GPT1_fSYS_Div_16
Definition: gpt12e.h:108
@ GPT1_fSYS_Div_4
Definition: gpt12e.h:106
@ GPT1_fSYS_Div_8
Definition: gpt12e.h:107
INLINE void GPT12E_T6_Mode_Counter_Input_Falling_T6In_Sel(void)
selects Falling Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4162
INLINE void GPT12E_T6_Mode_Counter_Sel(void)
selects T6 Counter Mode.
Definition: gpt12e.h:4034
INLINE void GPT12E_T4_Clr_T3_Dis(void)
Disables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:3008
GPT12E_T3EUD
Definition: gpt12e.h:164
@ GPT12E_T3EUDA_P04
Definition: gpt12e.h:165
@ GPT12E_T3EUDB_P25
Definition: gpt12e.h:166
INLINE void GPT12E_T4_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:2900
GPT12E_T6EUD
Definition: gpt12e.h:231
@ GPT12E_T6EUDA_P11
Definition: gpt12e.h:232
@ GPT12E_T6EUDB_P13
Definition: gpt12e.h:233
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T5In_Sel(void)
selects Falling Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3385
INLINE void GPT12E_T2_Mode_Reload_Input_T2In_Sel(void)
selects T2In as T2 Reload Mode Input.
Definition: gpt12e.h:787
INLINE void GPT12E_T5_Mode_Timer_Sel(void)
selects T5 Timer Mode.
Definition: gpt12e.h:3240
INLINE void GPT12E_T5_Mode_Counter_Input_T6Out_Sel(void)
selects T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3421
INLINE void GPT12E_T2_Mode_Counter_Sel(void)
selects T2 Counter Mode.
Definition: gpt12e.h:357
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_Dis(void)
disables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3621
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2361
INLINE void GPT12E_T2_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:1164
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2505
GPT12E_T6IN
Definition: gpt12e.h:222
@ GPT12E_T6INB_P13
Definition: gpt12e.h:224
@ GPT12E_T6INA_P02
Definition: gpt12e.h:223
INLINE void GPT12E_T3_Int_Dis(void)
disables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:4929
enum GPT12E_Mode_Timer_Prescaler TGPT12E_Mode_Timer_Prescaler
INLINE void GPT12E_T4_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:3096
INLINE uint16 GPT12E_T3_Value_Get(void)
reads Timer T3 Value.
Definition: gpt12e.h:1996
INLINE void GPT12E_T4_Int_Dis(void)
enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:4975
GPT12E_T4EUD
Definition: gpt12e.h:184
@ GPT12E_T4EUDA_P03
Definition: gpt12e.h:185
@ GPT12E_T4EUDB_P10
Definition: gpt12e.h:186
INLINE void GPT12E_T5_Start(void)
starts Timer T5.
Definition: gpt12e.h:3791
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2703
INLINE void GPT12E_T5_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t5i)
selects T5 Gated Timer Mode Parameter.
Definition: gpt12e.h:3331
INLINE uint8 GPT12E_T3_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1910
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_En(void)
enables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3475
INLINE void GPT12E_T5_DownCount_Sel(void)
selects Timer T5 counts down.
Definition: gpt12e.h:3863
INLINE void GPT12E_T5_Value_Set(uint16 t5)
sets Timer T5 Value.
Definition: gpt12e.h:3956
INLINE void GPT12E_T5_Cleared_On_Capture_En(void)
enables clearing T5 on a Capture Event.
Definition: gpt12e.h:3733
INLINE void GPT12E_T4_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t4i)
selects T4 Gated Timer Mode Parameter.
Definition: gpt12e.h:2235
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1931
INLINE void GPT12E_T3_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T3 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:1887
INLINE void GPT12E_T6_Value_Set(uint16 t6)
sets Timer T6 Value.
Definition: gpt12e.h:4485
INLINE void GPT12E_T2_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:1306
INLINE void GPT12E_CapRel_Int_En(void)
enables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5090
INLINE void GPT12E_T6_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t6i)
selects T6 Gated Timer Mode Parameter.
Definition: gpt12e.h:4108
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2289
INLINE void GPT12E_T2_Mode_Capture_Sel(void)
selects T2 Capture Mode.
Definition: gpt12e.h:425
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:3052
INLINE void GPT12E_T3_Mode_Counter_Sel(void)
selects T3 Counter Mode.
Definition: gpt12e.h:1424
INLINE void GPT12E_T2_Start(void)
starts Timer T2.
Definition: gpt12e.h:1057
INLINE void GPT12E_T4_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T4 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:2936
INLINE void GPT12E_T2_Int_Dis(void)
disables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:4883
enum GPT12E_T2IN TGPT12E_T2IN
INLINE void GPT12E_T2_Mode_Counter_Input_T3Out_Sel(void)
selects T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:607
INLINE void GPT12E_T2_Mode_Timer_Clk_Prescaler_Sel(uint16 t2i)
selects T2 Timer Mode Parameter.
Definition: gpt12e.h:479
INLINE uint8 GPT12E_T2_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1241
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:625
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:805
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:1003
INLINE uint8 GPT12E_T4_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:3031
INLINE void GPT12E_T6_Output_Dis(void)
disables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:4338
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2469
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_En(void)
enables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3696
GPT12E_Mode_Timer_Prescaler
Definition: gpt12e.h:251
@ GPT_Clk_Div_2
Definition: gpt12e.h:253
@ GPT_Clk_Div_16
Definition: gpt12e.h:256
@ GPT_Clk_Div_64
Definition: gpt12e.h:258
@ GPT_Clk_Div_8
Definition: gpt12e.h:255
@ GPT_Clk_Div_32
Definition: gpt12e.h:257
@ GPT_Clk_Div_1
Definition: gpt12e.h:252
@ GPT_Clk_Div_128
Definition: gpt12e.h:259
@ GPT_Clk_Div_4
Definition: gpt12e.h:254
enum GPT12E_T5IN TGPT12E_T5IN
INLINE uint8 GPT12E_T4_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:3075
INLINE void GPT12E_T3_Output_Dis(void)
disables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:1744
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_En(void)
enables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3602
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:1039
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2649
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2595
INLINE void GPT12E_T3_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:1833
INLINE void GPT12E_T4_UpCount_Sel(void)
selects Timer T4 counts up.
Definition: gpt12e.h:2865
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1622
INLINE void GPT12E_T4_Clr_T2_Dis(void)
Disables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2972
INLINE void GPT12E_GPT2_Clk_Prescaler_Sel(uint16 bps2)
selects GPT2 Block Prescaler.
Definition: gpt12e.h:3199
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2685
INLINE void GPT12E_T3_Start(void)
starts Timer T3.
Definition: gpt12e.h:1693
enum GPT12E_T5EUD TGPT12E_T5EUD
INLINE void GPT12E_T5_Capture_Trig_CapIn_Sel(void)
selects CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3545
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1676
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_Dis(void)
disables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1604
INLINE void GPT12E_T3_Stop(void)
stops Timer T3.
Definition: gpt12e.h:1710
INLINE uint16 GPT12E_GPT2_Clk_Prescaler_Get(void)
reads GPT2 Block Prescaler.
Definition: gpt12e.h:3220
INLINE void GPT12E_T2_Mode_Counter_Input_T2In_Sel(void)
selects T2In as T2 Counter Mode Input.
Definition: gpt12e.h:517
GPT12E_T2IN
Definition: gpt12e.h:135
@ GPT12E_T2INA_P12
Definition: gpt12e.h:136
@ GPT12E_T2INB_P14
Definition: gpt12e.h:137
INLINE void GPT12E_T5_T5In_Sel(uint16 ist5in)
selects Input for T2IN.
Definition: gpt12e.h:3977
INLINE void GPT12E_T6_DownCount_Sel(void)
selects Timer T6 counts down.
Definition: gpt12e.h:4392
enum GPT12E_T6EUD TGPT12E_T6EUD
GPT12E_CCU6_SEL
Definition: gpt12e.h:116
@ GPT12E_CCU6_T12_CM_CH1
Definition: gpt12e.h:123
@ GPT12E_CCU6_T13_PM
Definition: gpt12e.h:125
@ GPT12E_CCU6_T13_CM
Definition: gpt12e.h:127
@ GPT12E_CCU6_T13_ZM
Definition: gpt12e.h:126
@ GPT12E_CCU6_CH1
Definition: gpt12e.h:118
@ GPT12E_CCU6_ANY_CHx
Definition: gpt12e.h:128
@ GPT12E_CCU6_T12_CM_CH0
Definition: gpt12e.h:122
@ GPT12E_CCU6_CH0
Definition: gpt12e.h:117
@ GPT12E_CCU6_CH2
Definition: gpt12e.h:119
@ GPT12E_CCU6_T12_ZM
Definition: gpt12e.h:120
@ GPT12E_CCU6_T12_PM
Definition: gpt12e.h:121
@ GPT12E_CCU6_T12_CM_CH2
Definition: gpt12e.h:124
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Sel(void)
selects T2 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:459
INLINE uint8 GPT12E_T4_Int_Sts(void)
reads GPT Module 1 Timer 4 interrupt Status.
Definition: gpt12e.h:4626
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Sel(void)
selects T3 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:1492
INLINE void GPT12E_T5_UpCount_Sel(void)
selects Timer T5 counts up.
Definition: gpt12e.h:3881
#define GPT12E
Definition: tle987x.h:6091
#define SCU
Definition: tle987x.h:6097
#define SCU_GPT12ICLR_CRC_Msk
Definition: tle987x.h:8958
#define GPT12E_PISEL_IST5EUD_Msk
Definition: tle987x.h:7993
#define GPT12E_T6CON_T6UD_Pos
Definition: tle987x.h:8112
#define GPT12E_T6_T6_Pos
Definition: tle987x.h:8103
#define GPT12E_T6CON_T6UDE_Pos
Definition: tle987x.h:8114
#define GPT12E_PISEL_IST4IN_Msk
Definition: tle987x.h:7987
#define GPT12E_T2CON_T2EDGE_Msk
Definition: tle987x.h:8019
#define GPT12E_PISEL_IST3EUD_Pos
Definition: tle987x.h:7984
#define GPT12E_T4CON_T4CHDIR_Pos
Definition: tle987x.h:8074
#define GPT12E_T2CON_T2UD_Pos
Definition: tle987x.h:8010
#define SCU_GPT12IEN_T5IE_Msk
Definition: tle987x.h:8975
#define GPT12E_PISEL_IST4EUD_Pos
Definition: tle987x.h:7988
#define GPT12E_T3CON_T3OTL_Pos
Definition: tle987x.h:8040
#define GPT12E_PISEL_ISCAPIN_Msk
Definition: tle987x.h:7999
#define GPT12E_T5CON_T5UD_Msk
Definition: tle987x.h:8089
#define GPT12E_CAPREL_CAPREL_Pos
Definition: tle987x.h:7970
#define SCU_GPT12IRC_T6_Msk
Definition: tle987x.h:8986
#define GPT12E_T3CON_T3UD_Pos
Definition: tle987x.h:8034
#define GPT12E_T5CON_T5I_Msk
Definition: tle987x.h:8083
#define SCU_GPT12ICLR_T2C_Pos
Definition: tle987x.h:8967
#define GPT12E_T3CON_T3EDGE_Pos
Definition: tle987x.h:8044
#define SCU_GPT12IEN_T3IE_Pos
Definition: tle987x.h:8978
#define GPT12E_T3CON_T3UDE_Pos
Definition: tle987x.h:8036
#define GPT12E_T2_T2_Msk
Definition: tle987x.h:8002
#define SCU_GPT12ICLR_T2C_Msk
Definition: tle987x.h:8968
#define GPT12E_T4_T4_Pos
Definition: tle987x.h:8051
#define GPT12E_T3CON_BPS1_Msk
Definition: tle987x.h:8043
#define GPT12E_T2CON_T2I_Pos
Definition: tle987x.h:8004
#define GPT12E_T4CON_T4EDGE_Msk
Definition: tle987x.h:8073
#define GPT12E_PISEL_IST4EUD_Msk
Definition: tle987x.h:7989
#define SCU_GPT12IEN_CRIE_Pos
Definition: tle987x.h:8970
#define GPT12E_T6CON_T6CLR_Msk
Definition: tle987x.h:8123
#define SCU_GPT12PISEL_GPT12_Msk
Definition: tle987x.h:9001
#define GPT12E_T3CON_T3OE_Pos
Definition: tle987x.h:8038
#define SCU_GPT12ICLR_T3C_Msk
Definition: tle987x.h:8966
#define GPT12E_T4CON_T4RC_Pos
Definition: tle987x.h:8064
#define GPT12E_T6CON_BPS2_Pos
Definition: tle987x.h:8120
#define GPT12E_T6CON_T6CLR_Pos
Definition: tle987x.h:8122
#define GPT12E_T3CON_BPS1_Pos
Definition: tle987x.h:8042
#define GPT12E_PISEL_IST6IN_Msk
Definition: tle987x.h:7995
#define GPT12E_T3CON_T3OTL_Msk
Definition: tle987x.h:8041
#define GPT12E_PISEL_IST3IN_Pos
Definition: tle987x.h:7982
#define SCU_GPT12ICLR_T3C_Pos
Definition: tle987x.h:8965
#define GPT12E_PISEL_ISCAPIN_Pos
Definition: tle987x.h:7998
#define GPT12E_T3_T3_Msk
Definition: tle987x.h:8026
#define GPT12E_T3CON_T3UD_Msk
Definition: tle987x.h:8035
#define GPT12E_T4CON_T4UDE_Msk
Definition: tle987x.h:8063
#define GPT12E_T4CON_T4M_Pos
Definition: tle987x.h:8056
#define GPT12E_T3CON_T3I_Pos
Definition: tle987x.h:8028
#define SCU_GPT12IRC_T5_Pos
Definition: tle987x.h:8987
#define GPT12E_T2CON_T2UD_Msk
Definition: tle987x.h:8011
#define GPT12E_T3CON_T3M_Pos
Definition: tle987x.h:8030
#define GPT12E_T4CON_CLRT3EN_Pos
Definition: tle987x.h:8068
#define GPT12E_T3CON_T3CHDIR_Msk
Definition: tle987x.h:8047
#define SCU_GPT12IEN_T2IE_Pos
Definition: tle987x.h:8980
#define SCU_GPT12IRC_T3_Pos
Definition: tle987x.h:8991
#define SCU_GPT12IEN_T3IE_Msk
Definition: tle987x.h:8979
#define GPT12E_T4CON_T4UD_Msk
Definition: tle987x.h:8061
#define SCU_GPT12PISEL_GPT12_Pos
Definition: tle987x.h:9000
#define GPT12E_T2CON_T2RC_Msk
Definition: tle987x.h:8015
#define SCU_GPT12ICLR_T5C_Msk
Definition: tle987x.h:8962
#define GPT12E_T2CON_T2R_Msk
Definition: tle987x.h:8009
#define GPT12E_T4CON_CLRT2EN_Pos
Definition: tle987x.h:8066
#define GPT12E_T5CON_T5M_Pos
Definition: tle987x.h:8084
#define GPT12E_T3CON_T3RDIR_Msk
Definition: tle987x.h:8049
#define GPT12E_PISEL_IST6IN_Pos
Definition: tle987x.h:7994
#define GPT12E_T3_T3_Pos
Definition: tle987x.h:8025
#define GPT12E_PISEL_IST5IN_Msk
Definition: tle987x.h:7991
#define GPT12E_T5CON_T5RC_Pos
Definition: tle987x.h:8092
#define SCU_GPT12ICLR_T4C_Msk
Definition: tle987x.h:8964
#define SCU_GPT12IRC_T2_Pos
Definition: tle987x.h:8993
#define SCU_GPT12IEN_T4IE_Msk
Definition: tle987x.h:8977
#define GPT12E_PISEL_IST4IN_Pos
Definition: tle987x.h:7986
#define GPT12E_PISEL_IST2EUD_Msk
Definition: tle987x.h:7981
#define GPT12E_T5CON_T5I_Pos
Definition: tle987x.h:8082
#define GPT12E_T4CON_T4RDIR_Pos
Definition: tle987x.h:8076
#define GPT12E_PISEL_IST3EUD_Msk
Definition: tle987x.h:7985
#define GPT12E_T6CON_T6OE_Pos
Definition: tle987x.h:8116
#define GPT12E_T5CON_T5CLR_Pos
Definition: tle987x.h:8098
#define GPT12E_PISEL_IST6EUD_Pos
Definition: tle987x.h:7996
#define GPT12E_T6CON_T6UDE_Msk
Definition: tle987x.h:8115
#define GPT12E_T6CON_T6R_Msk
Definition: tle987x.h:8111
#define GPT12E_T5CON_T5M_Msk
Definition: tle987x.h:8085
#define GPT12E_T3CON_T3M_Msk
Definition: tle987x.h:8031
#define GPT12E_T3CON_T3CHDIR_Pos
Definition: tle987x.h:8046
#define GPT12E_T6CON_T6R_Pos
Definition: tle987x.h:8110
#define GPT12E_T6CON_T6M_Pos
Definition: tle987x.h:8108
#define GPT12E_T5CON_T5CLR_Msk
Definition: tle987x.h:8099
#define GPT12E_T3CON_T3R_Pos
Definition: tle987x.h:8032
#define GPT12E_T6CON_T6I_Msk
Definition: tle987x.h:8107
#define SCU_GPT12IEN_T6IE_Pos
Definition: tle987x.h:8972
#define GPT12E_T6CON_T6UD_Msk
Definition: tle987x.h:8113
#define GPT12E_T4CON_T4EDGE_Pos
Definition: tle987x.h:8072
#define SCU_GPT12ICLR_T4C_Pos
Definition: tle987x.h:8963
#define GPT12E_T4_T4_Msk
Definition: tle987x.h:8052
#define GPT12E_T2CON_T2RDIR_Msk
Definition: tle987x.h:8023
#define SCU_GPT12IRC_T4_Pos
Definition: tle987x.h:8989
#define SCU_GPT12IRC_T6_Pos
Definition: tle987x.h:8985
#define GPT12E_T2CON_T2UDE_Pos
Definition: tle987x.h:8012
#define GPT12E_T5CON_T5SC_Pos
Definition: tle987x.h:8100
#define GPT12E_PISEL_IST2IN_Pos
Definition: tle987x.h:7978
#define GPT12E_PISEL_IST2IN_Msk
Definition: tle987x.h:7979
#define GPT12E_T4CON_T4R_Pos
Definition: tle987x.h:8058
#define GPT12E_T5CON_CT3_Msk
Definition: tle987x.h:8095
#define GPT12E_T3CON_T3EDGE_Msk
Definition: tle987x.h:8045
#define GPT12E_T4CON_T4RDIR_Msk
Definition: tle987x.h:8077
#define SCU_GPT12IEN_T4IE_Pos
Definition: tle987x.h:8976
#define GPT12E_T2CON_T2I_Msk
Definition: tle987x.h:8005
#define GPT12E_T6CON_T6SR_Msk
Definition: tle987x.h:8125
#define SCU_GPT12ICLR_T6C_Pos
Definition: tle987x.h:8959
#define GPT12E_T6CON_T6OTL_Pos
Definition: tle987x.h:8118
#define SCU_GPT12IRC_T2_Msk
Definition: tle987x.h:8994
#define GPT12E_T2CON_T2CHDIR_Msk
Definition: tle987x.h:8021
#define SCU_GPT12ICLR_T5C_Pos
Definition: tle987x.h:8961
#define GPT12E_T6CON_T6M_Msk
Definition: tle987x.h:8109
#define GPT12E_PISEL_IST6EUD_Msk
Definition: tle987x.h:7997
#define GPT12E_T3CON_T3I_Msk
Definition: tle987x.h:8029
#define GPT12E_CAPREL_CAPREL_Msk
Definition: tle987x.h:7971
#define SCU_GPT12IRC_T4_Msk
Definition: tle987x.h:8990
#define GPT12E_T5CON_T5UDE_Msk
Definition: tle987x.h:8091
#define GPT12E_PISEL_IST2EUD_Pos
Definition: tle987x.h:7980
#define GPT12E_PISEL_IST5IN_Pos
Definition: tle987x.h:7990
#define GPT12E_T2CON_T2EDGE_Pos
Definition: tle987x.h:8018
#define GPT12E_T4CON_T4UD_Pos
Definition: tle987x.h:8060
#define GPT12E_T2CON_T2CHDIR_Pos
Definition: tle987x.h:8020
#define SCU_GPT12IRC_T3_Msk
Definition: tle987x.h:8992
#define GPT12E_T5_T5_Msk
Definition: tle987x.h:8080
#define GPT12E_T4CON_T4I_Pos
Definition: tle987x.h:8054
#define GPT12E_T5CON_T5UD_Pos
Definition: tle987x.h:8088
#define GPT12E_PISEL_IST5EUD_Pos
Definition: tle987x.h:7992
#define GPT12E_T2_T2_Pos
Definition: tle987x.h:8001
#define GPT12E_T3CON_T3R_Msk
Definition: tle987x.h:8033
#define GPT12E_T4CON_CLRT2EN_Msk
Definition: tle987x.h:8067
#define SCU_GPT12ICLR_T6C_Msk
Definition: tle987x.h:8960
#define GPT12E_T3CON_T3OE_Msk
Definition: tle987x.h:8039
#define GPT12E_T5CON_T5R_Pos
Definition: tle987x.h:8086
#define GPT12E_T4CON_CLRT3EN_Msk
Definition: tle987x.h:8069
#define GPT12E_T5_T5_Pos
Definition: tle987x.h:8079
#define GPT12E_T6CON_T6I_Pos
Definition: tle987x.h:8106
#define GPT12E_T6_T6_Msk
Definition: tle987x.h:8104
#define SCU_GPT12IRC_CR_Msk
Definition: tle987x.h:8984
#define SCU_GPT12IEN_T5IE_Pos
Definition: tle987x.h:8974
#define SCU_GPT12IRC_T5_Msk
Definition: tle987x.h:8988
#define SCU_GPT12IEN_T6IE_Msk
Definition: tle987x.h:8973
#define SCU_GPT12IRC_CR_Pos
Definition: tle987x.h:8983
#define GPT12E_T5CON_T5RC_Msk
Definition: tle987x.h:8093
#define GPT12E_T5CON_T5R_Msk
Definition: tle987x.h:8087
#define GPT12E_T4CON_T4M_Msk
Definition: tle987x.h:8057
#define GPT12E_T5CON_T5SC_Msk
Definition: tle987x.h:8101
#define GPT12E_T4CON_T4I_Msk
Definition: tle987x.h:8055
#define GPT12E_T5CON_T5UDE_Pos
Definition: tle987x.h:8090
#define GPT12E_T2CON_T2R_Pos
Definition: tle987x.h:8008
#define GPT12E_T3CON_T3UDE_Msk
Definition: tle987x.h:8037
#define GPT12E_T2CON_T2RDIR_Pos
Definition: tle987x.h:8022
#define GPT12E_T4CON_T4UDE_Pos
Definition: tle987x.h:8062
#define GPT12E_T2CON_T2M_Pos
Definition: tle987x.h:8006
#define GPT12E_T4CON_T4CHDIR_Msk
Definition: tle987x.h:8075
#define SCU_GPT12IEN_T2IE_Msk
Definition: tle987x.h:8981
#define GPT12E_T6CON_BPS2_Msk
Definition: tle987x.h:8121
#define GPT12E_PISEL_IST3IN_Msk
Definition: tle987x.h:7983
#define SCU_GPT12IEN_CRIE_Msk
Definition: tle987x.h:8971
#define GPT12E_T2CON_T2RC_Pos
Definition: tle987x.h:8014
#define GPT12E_T3CON_T3RDIR_Pos
Definition: tle987x.h:8048
#define GPT12E_T6CON_T6OTL_Msk
Definition: tle987x.h:8119
#define GPT12E_T6CON_T6SR_Pos
Definition: tle987x.h:8124
#define GPT12E_T4CON_T4RC_Msk
Definition: tle987x.h:8065
#define GPT12E_T2CON_T2UDE_Msk
Definition: tle987x.h:8013
#define GPT12E_T5CON_CT3_Pos
Definition: tle987x.h:8094
#define GPT12E_T6CON_T6OE_Msk
Definition: tle987x.h:8117
#define SCU_GPT12ICLR_CRC_Pos
Definition: tle987x.h:8957
#define GPT12E_T4CON_T4R_Msk
Definition: tle987x.h:8059
#define GPT12E_T2CON_T2M_Msk
Definition: tle987x.h:8007
SFR low level access library.
INLINE void Field_Wrt16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:342
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
INLINE uint8 u1_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 1-bit field of a 16-bit register.
Definition: sfr_access.h:402
INLINE void Field_Mod16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:357
INLINE uint8 u1_Field_Rd8(const volatile uint8 *reg, uint8 pos, uint8 msk)
This function reads a 1-bit field of a 8-bit register.
Definition: sfr_access.h:397
INLINE uint16 u16_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 16-bit field of a 16-bit register.
Definition: sfr_access.h:427
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:352
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:148
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155