Infineon MOTIX™ MCU TLE987x Device Family SDK
int.h
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1 /*
2  ***********************************************************************************************************************
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23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27  **********************************************************************************************************************/
37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** AP Adriano Pereira **
44 ** BG Blandine Guillot **
45 ** JO Julia Ott **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.1.0: 2014-05-11, DM: Initial version **
52 ** V0.1.1: 2015-02-10, DM: Individual header file added **
53 ** V0.1.2: 2015-09-17, DM: SYS_IRQ_CTRL register init added **
54 ** V0.1.3: 2015-11-25, DM: SCU_DMAIENx added, SCU_DMAIRCx clear added **
55 ** V0.1.4: 2016-10-10, DM: Interrupt Enable/Disable macros added **
56 ** CPU->SHPR3 init (SysTick Prio) added **
57 ** V0.1.5: 2017-10-05, DM: MISRA 2012 compliance, the following PC-Lint **
58 ** rules are globally deactivated: **
59 ** - Info 793: ANSI/ISO limit of 6 'significant **
60 ** characters in an external identifier **
61 ** - Info 835: A zero has been given as right **
62 ** argument to operator **
63 ** - Info 845: The left argument to operator '&' **
64 ** is certain to be 0 **
65 ** V0.1.6: 2018-03-20, DM: #define NMI_xxx macros modified to meet MISRA2012**
66 ** #define EXINTx_xxx macros modified to meet **
67 ** MISRA2012 **
68 ** Replaced macros by INLINE functions **
69 ** Replaced register accesses within functions by **
70 ** function calls **
71 ** Replaced __STATIC_INLINE by INLINE **
72 ** V0.1.7: 2018-07-04, AP: Added functions to enable/disable NVIC nodes **
73 ** V0.1.8: 2018-11-27, JO: Doxygen update **
74 ** Moved revision history from int.c to int.h **
75 ** V0.1.9: 2019-04-18, JO: Corrected NVIC_NodeXYZ_En/Dis functions **
76 ** V0.2.0: 2019-10-14, JO: Bridge driver interrupts enabled for CW2 **
77 ** V0.2.1: 2020-04-15, BG: Updated revision history format **
78 ** V0.2.2: 2020-07-21, BG: EP-439: Formatted .h/.c files **
79 ** V0.2.3: 2022-02-28, JO: EP-936: Updated copyright and branding **
80 *******************************************************************************/
81 
82 #ifndef INT_H
83 #define INT_H
84 
85 /*******************************************************************************
86 ** Includes **
87 *******************************************************************************/
88 #include "tle987x.h"
89 #include "types.h"
90 #include "tle_variants.h"
91 #include "sfr_access.h"
92 
93 /*******************************************************************************
94 ** Global Macro Definitions **
95 *******************************************************************************/
97 #define NMI_WDT ((uint8)1u << 0u)
99 #define NMI_PLL ((uint8)1u << 1u)
101 #define NMI_NVM ((uint8)1u << 2u)
103 #define NMI_OT ((uint8)1u << 3u)
105 #define NMI_OWT ((uint8)1u << 4u)
107 #define NMI_MAP ((uint8)1u << 5u)
109 #define NMI_ECC ((uint8)1u << 6u)
111 #define NMI_SUP ((uint8)1u << 7u)
113 #define SCU_EXICON0_EXINT0_RE_Pos (0UL)
115 #define SCU_EXICON0_EXINT0_RE_Msk (0x01UL)
117 #define SCU_EXICON0_EXINT0_FE_Pos (1UL)
119 #define SCU_EXICON0_EXINT0_FE_Msk (0x02UL)
121 #define SCU_EXICON0_EXINT1_RE_Pos (2UL)
123 #define SCU_EXICON0_EXINT1_RE_Msk (0x04UL)
125 #define SCU_EXICON0_EXINT1_FE_Pos (3UL)
127 #define SCU_EXICON0_EXINT1_FE_Msk (0x08UL)
129 #define SCU_EXICON0_EXINT2_RE_Pos (4UL)
131 #define SCU_EXICON0_EXINT2_RE_Msk (0x10UL)
133 #define SCU_EXICON0_EXINT2_FE_Pos (5UL)
135 #define SCU_EXICON0_EXINT2_FE_Msk (0x20UL)
137 #define SCU_NMISR_Pos (0UL)
139 #define SCU_NMISR_Msk (0xFFUL)
141 #define SCU_NMICLR_Pos (0UL)
143 #define SCU_NMICLR_Msk (0xFFUL)
144 
145 
146 /*******************************************************************************
147 ** Inline Function Definitions **
148 *******************************************************************************/
162 {
164 }
165 
179 {
181 }
182 
205 {
207 }
208 
232 {
234 }
235 
258 {
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261 
285 {
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288 
305 {
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308 
327 {
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349 {
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352 
371 {
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374 
394 {
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416 {
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439 {
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442 
461 {
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464 
484 {
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487 
506 {
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509 
529 {
531 }
532 
551 {
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554 
574 {
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577 
596 {
598 }
599 
619 {
621 }
622 
641 {
643 }
644 
663 {
665 }
666 
685 {
687 }
688 
707 {
709 }
710 
729 {
731 }
732 
751 {
753 }
754 
773 {
775 }
776 
796 {
798 }
799 
818 {
820 }
821 
841 {
843 }
844 
863 {
865 }
866 
886 {
888 }
889 
912 {
914 }
915 
939 {
941 }
942 
961 {
963 }
964 
984 {
986 }
987 
1005 {
1007 }
1008 
1027 {
1029 }
1030 
1049 {
1051 }
1052 
1072 {
1074 }
1075 
1093 {
1095 }
1096 
1115 {
1117 }
1118 
1137 {
1139 }
1140 
1159 {
1161 }
1162 
1181 {
1183 }
1184 
1202 {
1204 }
1205 
1224 {
1226 }
1227 
1246 {
1248 }
1249 
1267 {
1269 }
1270 
1288 {
1290 }
1291 
1297 {
1299 }
1300 
1306 {
1308 }
1309 
1315 {
1317 }
1318 
1324 {
1326 }
1327 
1333 {
1335 }
1336 
1342 {
1344 }
1345 
1351 {
1353 }
1354 
1360 {
1362 }
1363 
1369 {
1371 }
1372 
1378 {
1380 }
1381 
1387 {
1389 }
1390 
1396 {
1398 }
1399 
1405 {
1407 }
1408 
1414 {
1416 }
1417 
1423 {
1425 }
1426 
1432 {
1434 }
1435 
1441 {
1443 }
1444 
1450 {
1452 }
1453 
1459 {
1461 }
1462 
1468 {
1470 }
1471 
1477 {
1479 }
1480 
1486 {
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1489 
1495 {
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1498 
1505 {
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1508 
1515 {
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1524 {
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1527 
1533 {
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1536 
1542 {
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1545 
1551 {
1553 }
1554 
1560 {
1562 }
1563 
1569 {
1571 }
1572 
1578 {
1580 }
1581 
1582 #if (UC_SERIES == TLE987)
1601 {
1603 }
1604 
1624 {
1626 }
1627 
1646 {
1648 }
1649 
1669 {
1671 }
1672 
1691 {
1693 }
1694 
1714 {
1716 }
1717 
1736 {
1738 }
1739 
1759 {
1761 }
1762 
1781 {
1783 }
1784 
1804 {
1806 }
1807 
1826 {
1828 }
1829 
1849 {
1851 }
1852 
1871 {
1873 }
1874 
1893 {
1895 }
1896 
1915 {
1917 }
1918 
1937 {
1939 }
1940 
1959 {
1961 }
1962 
1981 {
1983 }
1984 #endif /* (UC_SERIES = TLE987) */
1985 
1986 /*******************************************************************************
1987 ** Global Function Declarations **
1988 *******************************************************************************/
1990 INLINE void INT_Clr_NMI_Status(uint8 Flags);
1991 INLINE void INT_Enable_Global_Int(void);
1992 INLINE void INT_Disable_Global_Int(void);
1993 
1998 void INT_Init(void);
1999 
2000 /*******************************************************************************
2001 ** Global Inline Function Definitions **
2002 *******************************************************************************/
2020 {
2021  return u8_Field_Rd8(&SCU->NMISR.reg, (uint8)SCU_NMISR_Pos, (uint8)SCU_NMISR_Msk);
2022 }
2023 
2039 {
2040  Field_Wrt8(&SCU->NMICLR.reg, (uint8)SCU_NMICLR_Pos, (uint8)SCU_NMICLR_Msk, Flags);
2041 }
2042 
2056 {
2057  Global_Int_En();
2058 }
2059 
2073 {
2074  Global_Int_Dis();
2075 }
2076 
2077 #endif
#define SCUPM
Definition: tle987x.h:6098
#define CPU
Definition: tle987x.h:6089
#define SCU
Definition: tle987x.h:6097
#define SCU_NMICLR_NMISUPC_Msk
Definition: tle987x.h:9218
#define CPU_NVIC_ISER0_Int_UART2_Pos
Definition: tle987x.h:7755
#define CPU_NVIC_ISER0_Int_BDRV_Msk
Definition: tle987x.h:7750
#define CPU_NVIC_ISER0_Int_SSC2_Msk
Definition: tle987x.h:7760
#define CPU_NVIC_ICER0_Int_ADC1_Pos
Definition: tle987x.h:7669
#define SCU_EDCSCLR_RDBEC_Pos
Definition: tle987x.h:8938
#define SCU_IRCON0CLR_EXINT0FC_Msk
Definition: tle987x.h:9041
#define CPU_NVIC_ISER0_Int_UART1_Msk
Definition: tle987x.h:7758
#define CPU_NVIC_ISER0_Int_SSC2_Pos
Definition: tle987x.h:7759
#define CPU_NVIC_ISER0_Int_GPT2_Pos
Definition: tle987x.h:7775
#define SCU_NMICLR_NMIMAPC_Msk
Definition: tle987x.h:9222
#define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Pos
Definition: tle987x.h:9692
#define SCU_IRCON0CLR_EXINT0RC_Msk
Definition: tle987x.h:9043
#define CPU_NVIC_ICER0_Int_CCU6SR2_Msk
Definition: tle987x.h:7664
#define CPU_NVIC_ICER0_Int_GPT1_Pos
Definition: tle987x.h:7675
#define CPU_NVIC_ISER0_Int_CCU6SR0_Msk
Definition: tle987x.h:7770
#define CPU_NVIC_ISER0_Int_EXINT0_Pos
Definition: tle987x.h:7753
#define CPU_NVIC_ISER0_Int_CCU6SR0_Pos
Definition: tle987x.h:7769
#define SCU_NMICLR_NMIOWDC_Pos
Definition: tle987x.h:9223
#define SCU_EDCSCLR_NVMDBEC_Msk
Definition: tle987x.h:8937
#define SCU_NMICLR_NMIOTC_Pos
Definition: tle987x.h:9225
#define CPU_NVIC_ICER0_Int_ADC1_Msk
Definition: tle987x.h:7670
#define CPU_NVIC_ICER0_Int_EXINT0_Pos
Definition: tle987x.h:7651
#define SCU_NMICON_NMIMAP_Pos
Definition: tle987x.h:9238
#define SCU_NMICON_NMIOWD_Msk
Definition: tle987x.h:9241
#define CPU_NVIC_ISER0_Int_ADC2_Msk
Definition: tle987x.h:7774
#define SCU_NMICLR_NMISUPC_Pos
Definition: tle987x.h:9217
#define CPU_NVIC_ISER0_Int_ADC1_Msk
Definition: tle987x.h:7772
#define SCU_IRCON0CLR_EXINT2RC_Pos
Definition: tle987x.h:9034
#define CPU_NVIC_ISER0_Int_EXINT1_Msk
Definition: tle987x.h:7752
#define SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Msk
Definition: tle987x.h:9693
#define CPU_NVIC_ICER0_Int_CCU6SR1_Msk
Definition: tle987x.h:7666
#define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Msk
Definition: tle987x.h:9699
#define CPU_NVIC_ICER0_Int_SSC2_Pos
Definition: tle987x.h:7657
#define SCU_IRCON0CLR_EXINT1FC_Pos
Definition: tle987x.h:9036
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Msk
Definition: tle987x.h:9607
#define CPU_NVIC_ICER0_Int_UART1_Pos
Definition: tle987x.h:7655
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Msk
Definition: tle987x.h:9605
#define SCU_IRCON0CLR_EXINT1RC_Pos
Definition: tle987x.h:9038
#define CPU_NVIC_ICER0_Int_EXINT0_Msk
Definition: tle987x.h:7652
#define SCU_EDCSCLR_RSBEC_Msk
Definition: tle987x.h:8935
#define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Msk
Definition: tle987x.h:9701
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Pos
Definition: tle987x.h:9604
#define CPU_NVIC_ISER0_Int_CCU6SR2_Msk
Definition: tle987x.h:7766
#define SCU_NMICON_NMINVM_Pos
Definition: tle987x.h:9244
#define CPU_NVIC_ISER0_Int_CCU6SR2_Pos
Definition: tle987x.h:7765
#define CPU_NVIC_ISER0_Int_GPT1_Msk
Definition: tle987x.h:7778
#define CPU_NVIC_ICER0_Int_UART2_Msk
Definition: tle987x.h:7654
#define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Msk
Definition: tle987x.h:9697
#define SCU_IRCON0CLR_EXINT0RC_Pos
Definition: tle987x.h:9042
#define SCU_IRCON0CLR_EXINT1RC_Msk
Definition: tle987x.h:9039
#define CPU_NVIC_ICER0_Int_SSC1_Msk
Definition: tle987x.h:7660
#define CPU_NVIC_ICER0_Int_GPT2_Pos
Definition: tle987x.h:7673
#define CPU_NVIC_ISER0_Int_GPT1_Pos
Definition: tle987x.h:7777
#define SCU_IRCON0CLR_EXINT2RC_Msk
Definition: tle987x.h:9035
#define SCU_EDCCON_NVMIE_Pos
Definition: tle987x.h:8929
#define CPU_NVIC_ISER0_Int_BDRV_Pos
Definition: tle987x.h:7749
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Pos
Definition: tle987x.h:9598
#define CPU_NVIC_ICER0_Int_SSC1_Pos
Definition: tle987x.h:7659
#define SCU_IRCON0CLR_EXINT2FC_Pos
Definition: tle987x.h:9032
#define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Pos
Definition: tle987x.h:9694
#define CPU_NVIC_ICER0_Int_CCU6SR3_Msk
Definition: tle987x.h:7662
#define CPU_NVIC_ISER0_Int_CCU6SR1_Msk
Definition: tle987x.h:7768
#define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Msk
Definition: tle987x.h:9691
#define SCU_EDCCON_RIE_Msk
Definition: tle987x.h:8932
#define SCU_EDCSCLR_RSBEC_Pos
Definition: tle987x.h:8934
#define SCU_NMICON_NMINVM_Msk
Definition: tle987x.h:9245
#define SCU_IRCON0CLR_EXINT1FC_Msk
Definition: tle987x.h:9037
#define CPU_NVIC_ISER0_Int_SSC1_Msk
Definition: tle987x.h:7762
#define CPU_NVIC_ICER0_Int_BDRV_Pos
Definition: tle987x.h:7647
#define CPU_NVIC_ISER0_Int_DMA_Pos
Definition: tle987x.h:7747
#define SCU_NMICON_NMISUP_Msk
Definition: tle987x.h:9235
#define SCU_NMICON_NMIOWD_Pos
Definition: tle987x.h:9240
#define SCU_NMICON_NMIOT_Pos
Definition: tle987x.h:9242
#define SCU_NMICON_NMIECC_Msk
Definition: tle987x.h:9237
#define CPU_NVIC_ISER0_Int_EXINT1_Pos
Definition: tle987x.h:7751
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Pos
Definition: tle987x.h:9600
#define CPU_NVIC_ICER0_Int_DMA_Pos
Definition: tle987x.h:7645
#define SCU_NMICON_NMIPLL_Msk
Definition: tle987x.h:9247
#define SCU_IRCON0CLR_EXINT2FC_Msk
Definition: tle987x.h:9033
#define CPU_NVIC_ISER0_Int_ADC1_Pos
Definition: tle987x.h:7771
#define SCU_NMICON_NMISUP_Pos
Definition: tle987x.h:9234
#define CPU_NVIC_ICER0_Int_CCU6SR0_Msk
Definition: tle987x.h:7668
#define SCU_NMICLR_NMINVMC_Pos
Definition: tle987x.h:9227
#define CPU_NVIC_ICER0_Int_GPT1_Msk
Definition: tle987x.h:7676
#define CPU_NVIC_ISER0_Int_GPT2_Msk
Definition: tle987x.h:7776
#define CPU_NVIC_ICER0_Int_EXINT1_Pos
Definition: tle987x.h:7649
#define SCU_EDCSCLR_RDBEC_Msk
Definition: tle987x.h:8939
#define SCU_NMICLR_NMIECCC_Msk
Definition: tle987x.h:9220
#define CPU_NVIC_ICER0_Int_ADC2_Msk
Definition: tle987x.h:7672
#define CPU_NVIC_ISER0_Int_SSC1_Pos
Definition: tle987x.h:7761
#define CPU_NVIC_ICER0_Int_BDRV_Msk
Definition: tle987x.h:7648
#define SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Msk
Definition: tle987x.h:9695
#define CPU_NVIC_ISER0_Int_ADC2_Pos
Definition: tle987x.h:7773
#define CPU_NVIC_ISER0_Int_CCU6SR3_Pos
Definition: tle987x.h:7763
#define SCU_NMICLR_NMIOWDC_Msk
Definition: tle987x.h:9224
#define CPU_NVIC_ISER0_Int_UART2_Msk
Definition: tle987x.h:7756
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Pos
Definition: tle987x.h:9602
#define SCU_NMICON_NMIPLL_Pos
Definition: tle987x.h:9246
#define SCU_IRCON0CLR_EXINT0FC_Pos
Definition: tle987x.h:9040
#define SCU_NMICON_NMIWDT_Msk
Definition: tle987x.h:9249
#define CPU_NVIC_ICER0_Int_UART1_Msk
Definition: tle987x.h:7656
#define SCU_EDCCON_NVMIE_Msk
Definition: tle987x.h:8930
#define SCU_NMICLR_NMIOTC_Msk
Definition: tle987x.h:9226
#define SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Pos
Definition: tle987x.h:9690
#define SCU_IEN0_EA_Pos
Definition: tle987x.h:9008
#define CPU_NVIC_ICER0_Int_GPT2_Msk
Definition: tle987x.h:7674
#define SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Pos
Definition: tle987x.h:9606
#define CPU_NVIC_ICER0_Int_CCU6SR1_Pos
Definition: tle987x.h:7665
#define SCU_NMICLR_NMIPLLC_Msk
Definition: tle987x.h:9230
#define CPU_NVIC_ICER0_Int_ADC2_Pos
Definition: tle987x.h:7671
#define SCU_NMICON_NMIWDT_Pos
Definition: tle987x.h:9248
#define SCU_NMICLR_NMIMAPC_Pos
Definition: tle987x.h:9221
#define SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Pos
Definition: tle987x.h:9696
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Msk
Definition: tle987x.h:9601
#define SCU_EDCCON_RIE_Pos
Definition: tle987x.h:8931
#define SCU_NMICLR_NMINVMC_Msk
Definition: tle987x.h:9228
#define CPU_NVIC_ICER0_Int_DMA_Msk
Definition: tle987x.h:7646
#define CPU_NVIC_ICER0_Int_UART2_Pos
Definition: tle987x.h:7653
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Msk
Definition: tle987x.h:9599
#define SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Pos
Definition: tle987x.h:9700
#define SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Msk
Definition: tle987x.h:9603
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Msk
Definition: tle987x.h:9597
#define SCU_NMICLR_NMIECCC_Pos
Definition: tle987x.h:9219
#define CPU_NVIC_ICER0_Int_CCU6SR2_Pos
Definition: tle987x.h:7663
#define SCU_NMICLR_NMIPLLC_Pos
Definition: tle987x.h:9229
#define CPU_NVIC_ISER0_Int_DMA_Msk
Definition: tle987x.h:7748
#define CPU_NVIC_ICER0_Int_EXINT1_Msk
Definition: tle987x.h:7650
#define CPU_NVIC_ICER0_Int_SSC2_Msk
Definition: tle987x.h:7658
#define SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Pos
Definition: tle987x.h:9698
#define SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Pos
Definition: tle987x.h:9596
#define SCU_NMICLR_NMIWDTC_Msk
Definition: tle987x.h:9232
#define CPU_NVIC_ICER0_Int_CCU6SR0_Pos
Definition: tle987x.h:7667
#define SCU_EDCSCLR_NVMDBEC_Pos
Definition: tle987x.h:8936
#define SCU_NMICON_NMIOT_Msk
Definition: tle987x.h:9243
#define CPU_NVIC_ISER0_Int_EXINT0_Msk
Definition: tle987x.h:7754
#define CPU_NVIC_ISER0_Int_UART1_Pos
Definition: tle987x.h:7757
#define SCU_NMICLR_NMIWDTC_Pos
Definition: tle987x.h:9231
#define CPU_NVIC_ISER0_Int_CCU6SR1_Pos
Definition: tle987x.h:7767
#define SCU_NMICON_NMIECC_Pos
Definition: tle987x.h:9236
#define SCU_IEN0_EA_Msk
Definition: tle987x.h:9009
#define CPU_NVIC_ISER0_Int_CCU6SR3_Msk
Definition: tle987x.h:7764
#define SCU_NMICON_NMIMAP_Msk
Definition: tle987x.h:9239
#define CPU_NVIC_ICER0_Int_CCU6SR3_Pos
Definition: tle987x.h:7661
INLINE void EXINT2_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT2.
Definition: int.h:595
#define SCU_EXICON0_EXINT0_RE_Msk
External Interrupt 0 Rising Edge Bit Mask.
Definition: int.h:115
INLINE void NVIC_Node2_Dis(void)
Disables the NVIC node 2 (Int_ADC2)
Definition: int.h:1341
INLINE void NMI_PLL_Int_Dis(void)
disables PLL Loss of Lock NMI.
Definition: int.h:840
INLINE void EXINT0_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT0.
Definition: int.h:662
INLINE void INT_Enable_Global_Int(void)
enables the global interrupt IEN0.EA
Definition: int.h:2055
INLINE void NMI_MAP_Int_Dis(void)
disables NVM Map Error NMI.
Definition: int.h:983
INLINE void NVIC_Node8_Dis(void)
Disables the NVIC node 8 (Int_SSC1)
Definition: int.h:1449
INLINE void NMI_WDT_Int_Dis(void)
disables Watchdog Timer NMI.
Definition: int.h:795
INLINE void BEMF_Phase_W_Hi_Int_Dis(void)
disables Phase W Zero Crossing Comparator High Interrupt.
Definition: int.h:1803
INLINE void NMI_PLL_Int_Clr(void)
clears PLL Loss of Lock NMI Flag.
Definition: int.h:1158
#define SCU_EXICON0_EXINT0_FE_Pos
External Interrupt 0 Falling Edge Bit Position.
Definition: int.h:117
INLINE void EXINT1_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT1.
Definition: int.h:684
INLINE void BEMF_Phase_U_Lo_Int_Clr(void)
clears Phase U Zero Crossing Comparator Low Interrupt flag.
Definition: int.h:1892
INLINE void NVIC_Node5_En(void)
Enables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1386
INLINE void NVIC_Node15_Dis(void)
Disables the NVIC node 15 (Int_DMA)
Definition: int.h:1577
INLINE void BEMF_Phase_V_Hi_Int_Clr(void)
clears Phase V Zero Crossing Comparator High Interrupt flag.
Definition: int.h:1914
INLINE void NVIC_Node3_En(void)
Enables the NVIC node 3 (Int_ADC1)
Definition: int.h:1350
INLINE void BEMF_Phase_V_Lo_Int_Clr(void)
clears Phase V Zero Crossing Comparator Low Interrupt flag.
Definition: int.h:1936
INLINE void ECC_NVM_DoubleBit_Int_En(void)
enables NVM Double Bit ECC Error Interrupt.
Definition: int.h:257
INLINE void NVIC_Node10_En(void)
Enables the NVIC node 10 (Int_UART1)
Definition: int.h:1476
INLINE void EXINT1_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT1.
Definition: int.h:483
INLINE void NMI_OT_Int_En(void)
enables OT NMI.
Definition: int.h:1092
#define SCU_EXICON0_EXINT2_FE_Msk
External Interrupt 2 Falling Edge Bit Mask.
Definition: int.h:135
INLINE void NVIC_Node12_En(void)
Enables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1514
INLINE void Global_Int_En(void)
enables Global Interrupt (Pending interrupt requests are not blocked from the core).
Definition: int.h:161
INLINE void EXINT0_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT0.
Definition: int.h:370
#define SCU_EXICON0_EXINT1_FE_Msk
External Interrupt 1 Falling Edge Bit Mask.
Definition: int.h:127
#define SCU_EXICON0_EXINT1_RE_Msk
External Interrupt 1 Rising Edge Bit Mask.
Definition: int.h:123
INLINE void NVIC_Node6_En(void)
Enables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1404
INLINE void NVIC_Node12_Dis(void)
Disables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1523
#define SCU_EXICON0_EXINT1_RE_Pos
External Interrupt 1 Rising Edge Bit Position.
Definition: int.h:121
INLINE void ECC_NVM_DoubleBit_Int_Clr(void)
clears NVM Double Bit ECC Error Interrupt flag.
Definition: int.h:348
INLINE void EXINT0_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT0.
Definition: int.h:640
INLINE void NVIC_Node15_En(void)
Enables the NVIC node 15 (Int_DMA)
Definition: int.h:1568
INLINE void NMI_NVM_Int_Clr(void)
clears NVM Operation Complete NMI flag.
Definition: int.h:1180
INLINE void BEMF_Phase_W_Hi_Int_En(void)
enables Phase W Zero Crossing Comparator High Interrupt.
Definition: int.h:1780
#define SCU_NMICLR_Pos
NMI Clear Bit Position.
Definition: int.h:141
INLINE void NMI_ECC_Int_Clr(void)
clears ECC Error NMI Flag.
Definition: int.h:1266
INLINE void ECC_RAM_SingleBit_Int_Clr(void)
clears RAM Single Bit Error Status.
Definition: int.h:304
#define SCU_NMISR_Msk
NMI Status Read Bit Mask.
Definition: int.h:139
INLINE void EXINT2_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT2.
Definition: int.h:728
INLINE void EXINT1_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT1.
Definition: int.h:505
INLINE void NVIC_Node1_Dis(void)
Disables the NVIC node 1 (Int_GPT2)
Definition: int.h:1323
INLINE void NMI_OT_Int_Clr(void)
clears NMI OT Flag.
Definition: int.h:1201
INLINE void NMI_SUP_Int_Dis(void)
disables Supply Prewarning NMI.
Definition: int.h:1026
INLINE void NMI_WDT_Int_En(void)
enables Watchdog Timer NMI.
Definition: int.h:772
INLINE void NVIC_Node6_Dis(void)
Disables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1413
#define SCU_EXICON0_EXINT2_RE_Pos
External Interrupt 2 Rising Edge Bit Position.
Definition: int.h:129
INLINE void NVIC_Node8_En(void)
Enables the NVIC node 8 (Int_SSC1)
Definition: int.h:1440
INLINE void NMI_WDT_Int_Clr(void)
clears Watchdog Timer NMI Flag.
Definition: int.h:1136
INLINE void EXINT2_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT2.
Definition: int.h:550
INLINE void NVIC_Node11_Dis(void)
Disables the NVIC node 11 (Int_UART2)
Definition: int.h:1504
INLINE void ECC_RAM_DoubleBit_Int_Clr(void)
clears RAM Double Bit ECC Error Interrupt flag.
Definition: int.h:326
INLINE void NVIC_Node14_En(void)
Enables the NVIC node 14 (Int_BDRV)
Definition: int.h:1550
INLINE void BEMF_Phase_U_Hi_Int_Clr(void)
clears Phase U Zero Crossing Comparator High Interrupt flag.
Definition: int.h:1870
void INT_Init(void)
Initializes the Interrupt module based on the Config Wizard for MOTIX MCU configuration.
INLINE void NVIC_Node10_Dis(void)
Disables the NVIC node 10 (Int_UART1)
Definition: int.h:1485
INLINE void NMI_OT_Int_Dis(void)
disables OT NMI.
Definition: int.h:1114
INLINE void ECC_RAM_DoubleBit_Int_En(void)
enables RAM Double Bit ECC Error Interrupt.
Definition: int.h:204
INLINE void BEMF_Phase_V_Hi_Int_En(void)
enables Phase V Zero Crossing Comparator High Interrupt.
Definition: int.h:1690
INLINE void BEMF_Phase_W_Lo_Int_En(void)
enables Phase W Zero Crossing Comparator Low Interrupt.
Definition: int.h:1825
#define SCU_EXICON0_EXINT0_FE_Msk
External Interrupt 0 Falling Edge Bit Mask.
Definition: int.h:119
INLINE void NMI_OWD_Int_Clr(void)
clears Oscillator Watchdog NMI Flag.
Definition: int.h:1223
INLINE void NMI_OWD_Int_En(void)
enables Oscillator Watchdog NMI.
Definition: int.h:1048
INLINE void EXINT2_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT2.
Definition: int.h:750
INLINE void Global_Int_Dis(void)
disables Global Interrupt (All pending interrupt requests,except NMI, are blocked from the core).
Definition: int.h:178
INLINE void NVIC_Node7_En(void)
Enables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1422
INLINE void NMI_ECC_Int_En(void)
enables ECC Error NMI.
Definition: int.h:911
INLINE void BEMF_Phase_U_Lo_Int_En(void)
enables Phase U Zero Crossing Comparator Low Interrupt.
Definition: int.h:1645
INLINE void EXINT0_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT0.
Definition: int.h:393
INLINE void NMI_NVM_Int_Dis(void)
disables NVM Operation Complete NMI.
Definition: int.h:885
INLINE void EXINT1_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT1.
Definition: int.h:460
INLINE void BEMF_Phase_U_Hi_Int_En(void)
enables Phase U Zero Crossing Comparator High Interrupt.
Definition: int.h:1600
INLINE void NVIC_Node13_En(void)
Enables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1532
INLINE void NMI_MAP_Int_En(void)
enables NVM Map Error NMI.
Definition: int.h:960
INLINE void NVIC_Node11_En(void)
Enables the NVIC node 11 (Int_UART2)
Definition: int.h:1494
INLINE void NMI_OWD_Int_Dis(void)
disables Oscillator Watchdog NMI.
Definition: int.h:1071
INLINE void EXINT1_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT1.
Definition: int.h:528
INLINE void NMI_MAP_Int_Clr(void)
clears NVM Map Error NMI Flag.
Definition: int.h:1245
INLINE void NVIC_Node5_Dis(void)
Disables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1395
INLINE void NVIC_Node3_Dis(void)
Disables the NVIC node 3 (Int_ADC1)
Definition: int.h:1359
INLINE void NVIC_Node4_En(void)
Enables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1368
INLINE void NVIC_Node9_En(void)
Enables the NVIC node 9 (Int_SSC2)
Definition: int.h:1458
INLINE void NVIC_Node9_Dis(void)
Disables the NVIC node 9 (Int_SSC2)
Definition: int.h:1467
INLINE void NVIC_Node13_Dis(void)
Disables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1541
INLINE void BEMF_Phase_W_Lo_Int_Dis(void)
disables Phase W Zero Crossing Comparator Low Interrupt.
Definition: int.h:1848
#define SCU_NMISR_Pos
NMI Status Read Bit Position.
Definition: int.h:137
INLINE void EXINT2_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT2.
Definition: int.h:573
#define SCU_NMICLR_Msk
NMI Clear Bit Mask.
Definition: int.h:143
#define SCU_EXICON0_EXINT1_FE_Pos
External Interrupt 1 Falling Edge Bit Position.
Definition: int.h:125
INLINE void NVIC_Node2_En(void)
Enables the NVIC node 2 (Int_ADC2)
Definition: int.h:1332
#define SCU_EXICON0_EXINT2_FE_Pos
External Interrupt 2 Falling Edge Bit Position.
Definition: int.h:133
INLINE void BEMF_Phase_V_Lo_Int_Dis(void)
disables Phase V Zero Crossing Comparator Low Interrupt.
Definition: int.h:1758
INLINE uint8 INT_Get_NMI_Status(void)
Reads out the NMI Status.
Definition: int.h:2019
INLINE void BEMF_Phase_U_Lo_Int_Dis(void)
disables Phase U Zero Crossing Comparator Low Interrupt.
Definition: int.h:1668
INLINE void BEMF_Phase_W_Lo_Int_Clr(void)
clears Phase W Zero Crossing Comparator Low Interrupt flag.
Definition: int.h:1980
INLINE void ECC_RAM_DoubleBit_Int_Dis(void)
disables RAM Double Bit ECC Error Interrupt.
Definition: int.h:231
INLINE void EXINT0_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT0.
Definition: int.h:415
INLINE void EXINT0_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT0.
Definition: int.h:438
INLINE void NMI_SUP_Int_Clr(void)
clears Supply Prewarning NMI Flag.
Definition: int.h:1287
INLINE void NVIC_Node14_Dis(void)
Disables the NVIC node 14 (Int_BDRV)
Definition: int.h:1559
INLINE void NMI_NVM_Int_En(void)
enables NVM Operation Complete NMI.
Definition: int.h:862
#define SCU_EXICON0_EXINT2_RE_Msk
External Interrupt 2 Rising Edge Bit Mask.
Definition: int.h:131
INLINE void NMI_ECC_Int_Dis(void)
disables ECC Error NMI.
Definition: int.h:938
INLINE void BEMF_Phase_V_Lo_Int_En(void)
enables Phase V Zero Crossing Comparator Low Interrupt.
Definition: int.h:1735
INLINE void NVIC_Node7_Dis(void)
Disables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1431
INLINE void ECC_NVM_DoubleBit_Int_Dis(void)
disables NVM Double Bit ECC Error Interrupt.
Definition: int.h:284
INLINE void BEMF_Phase_U_Hi_Int_Dis(void)
disables Phase U Zero Crossing Comparator High Interrupt.
Definition: int.h:1623
INLINE void BEMF_Phase_V_Hi_Int_Dis(void)
disables Phase V Zero Crossing Comparator High Interrupt.
Definition: int.h:1713
INLINE void NVIC_Node1_En(void)
Enables the NVIC node 1 (Int_GPT2)
Definition: int.h:1314
INLINE void NMI_PLL_Int_En(void)
enables PLL Loss of Lock NMI.
Definition: int.h:817
INLINE void NVIC_Node0_Dis(void)
Disables the NVIC node 0 (Int_GPT1)
Definition: int.h:1305
INLINE void EXINT1_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT1.
Definition: int.h:706
INLINE void NVIC_Node4_Dis(void)
Disables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1377
INLINE void NMI_SUP_Int_En(void)
enables Supply Prewarning NMI.
Definition: int.h:1004
INLINE void EXINT2_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT2.
Definition: int.h:618
INLINE void INT_Disable_Global_Int(void)
disables the global interrupt IEN0.EA
Definition: int.h:2072
INLINE void NVIC_Node0_En(void)
Enables the NVIC node 0 (Int_GPT1)
Definition: int.h:1296
INLINE void BEMF_Phase_W_Hi_Int_Clr(void)
clears Phase W Zero Crossing Comparator High Interrupt flag.
Definition: int.h:1958
#define SCU_EXICON0_EXINT0_RE_Pos
External Interrupt 0 Rising Edge Bit Position.
Definition: int.h:113
INLINE void INT_Clr_NMI_Status(uint8 Flags)
Clears the NMI Status flags.
Definition: int.h:2038
SFR low level access library.
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:337
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:362
INLINE uint8 u8_Field_Rd8(const volatile uint8 *reg, uint8 pos, uint8 msk)
This function reads a 8-bit field of a 8-bit register.
Definition: sfr_access.h:412
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:347
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:352
CMSIS register HeaderFile.
Device specific memory layout defines.
General type declarations.
#define INLINE
Definition: types.h:148
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint32_t uint32
32 bit unsigned value
Definition: types.h:155