119 #include "adc1_defines.h"
127 #define ADC1_VDH_Attenuator_Range_0_30V (1u)
129 #define ADC1_VDH_Attenuator_Range_0_20V (0u)
174 #define ADC1_P20 ADC1_CH0
176 #define ADC1_CSA ADC1_CH1
178 #define ADC1_P22 ADC1_CH2
180 #define ADC1_P23 ADC1_CH3
182 #define ADC1_P24 ADC1_CH4
184 #define ADC1_P25 ADC1_CH5
186 #define ADC1_VDH ADC1_CH6
190 #define ADC1_MASK_CH0 ((uint32)1u << ADC1_CH0)
192 #define ADC1_MASK_CH1 ((uint32)1u << ADC1_CH1)
194 #define ADC1_MASK_CH2 ((uint32)1u << ADC1_CH2)
196 #define ADC1_MASK_CH3 ((uint32)1u << ADC1_CH3)
198 #define ADC1_MASK_CH4 ((uint32)1u << ADC1_CH4)
200 #define ADC1_MASK_CH5 ((uint32)1u << ADC1_CH5)
202 #define ADC1_MASK_CH6 ((uint32)1u << ADC1_CH6)
205 #define ADC1_MASK_P20 (ADC1_MASK_CH0)
207 #define ADC1_MASK_CSA (ADC1_MASK_CH1)
209 #define ADC1_MASK_P22 (ADC1_MASK_CH2)
211 #define ADC1_MASK_P23 (ADC1_MASK_CH3)
213 #define ADC1_MASK_P24 (ADC1_MASK_CH4)
215 #define ADC1_MASK_P25 (ADC1_MASK_CH5)
217 #define ADC1_MASK_VDH (ADC1_MASK_CH6)
220 #define ADC1_VREF_5000mV 5000u
222 #define ADC1_VREF_22000mV 22000u
224 #define ADC1_VREF_30000mV 30000u
INLINE uint16 ADC1_P22_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1706
INLINE void ADC1_Ch6_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 6 number of sampling ticks.
Definition: adc1.h:2650
INLINE void ADC1_Sequence4_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 4, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1306
INLINE bool ADC1_isEIMactive(void)
checks Exceptional Interrupt Mode active
Definition: adc1.h:4056
INLINE uint16 ADC1_Ch5_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1555
INLINE uint8 ADC1_Ch3_ResultValid_Get(void)
Reads the valid flag for the channel 3 (P2.3) result.
Definition: adc1.h:1954
INLINE uint16 ADC1_VDH_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1826
INLINE void ADC1_Ch4_Int_Clr(void)
clears ADC1 Channel 4 Interrupt flag.
Definition: adc1.h:3385
INLINE void ADC1_Sequence7_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 7, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1375
INLINE void ADC1_Power_On(void)
Enables the ADC1 module.
Definition: adc1.h:833
INLINE uint16 ADC1_Ch4_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1525
INLINE uint16 ADC1_P23_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1736
INLINE void ADC1_Ch3_WaitForRead_Set(void)
Sets the ADC1 channel 3 result register to "wait for read".
Definition: adc1.h:2860
INLINE void ADC1_Ch1_Overwrite_Set(void)
Sets the ADC1 channel 1 result register to "overwrite".
Definition: adc1.h:2770
INLINE uint8 ADC1_EIM_Active_Sts(void)
Reads the active status of the Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:1118
INLINE uint16 ADC1_P25_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1796
INLINE void ADC1_EIM_Int_Dis(void)
disables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3835
INLINE void ADC1_Ch2_WaitForRead_Set(void)
Sets the ADC1 channel 2 result register to "wait for read".
Definition: adc1.h:2800
INLINE uint16 ADC1_P24_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1766
INLINE void ADC1_SetMode(uint8 mode)
Start ADC1 conversion mode selection.
Definition: adc1.h:3976
INLINE void ADC1_Ch5_Int_Clr(void)
clears ADC1 Channel 5 Interrupt flag.
Definition: adc1.h:3406
INLINE bool ADC1_GetSwModeResult_mV(uint16 *pVar_mV)
Get ADC1 software mode result in Millivolt.
Definition: adc1.h:4007
INLINE void ADC1_ESM_Int_En(void)
enables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3857
INLINE void ADC1_Ch4_Int_En(void)
enables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3675
INLINE void ADC1_Ch1_DataWidth_10bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 10-bit.
Definition: adc1.h:2187
INLINE void ADC1_Ch3_Int_En(void)
enables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3630
INLINE void ADC1_Ch6_Int_Clr(void)
clears ADC1 Channel 6 Interrupt flag.
Definition: adc1.h:3428
INLINE void ADC1_VDH_Attenuator_Range_0_20V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 22V.
Definition: adc1.h:3929
INLINE void ADC1_SetSocSwMode(uint8 Ch)
Starts ADC1 software mode conversion.
Definition: adc1.h:3982
INLINE void ADC1_Ch3_DataWidth_10bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 10-bit.
Definition: adc1.h:2291
INLINE uint8 ADC1_Ch0_ResultValid_Get(void)
Reads the valid flag for the channel 0 (P2.0) result.
Definition: adc1.h:1858
INLINE void ADC1_Ch5_WaitForRead_Set(void)
Sets the ADC1 channel 5 result register to "wait for read".
Definition: adc1.h:2980
INLINE uint8 ADC1_Current_Ch_Sts(void)
Reads the channel for currently ongoing conversion, if no conversion is ongoing, then it returns the ...
Definition: adc1.h:1027
INLINE void ADC1_Ch4_WaitForRead_Set(void)
Sets the ADC1 channel 4 result register to "wait for read".
Definition: adc1.h:2920
INLINE void ADC1_Ch1_WaitForRead_Set(void)
Sets ADC1 channel 1 the result register to "wait for read".
Definition: adc1.h:2740
INLINE uint8 ADC1_ESM_Active_Sts(void)
Reads the active status of the Exceptional Sequencer Measurement (ESM).
Definition: adc1.h:1144
INLINE void ADC1_Sequencer_Mode_Sel(void)
ADC1 selects the Sequencer Mode.
Definition: adc1.h:947
INLINE void ADC1_VDH_Attenuator_Zhigh_Set(void)
Enables the output attenuator for VDH.
Definition: adc1.h:3239
INLINE void ADC1_Ch5_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 5 number of sampling ticks.
Definition: adc1.h:2621
INLINE void ADC1_SetEIMChannel(uint8 channel)
Set(Change) ADC1 EIM channel.
Definition: adc1.h:3966
INLINE void ADC1_SetSwMode_Channel(uint8 channel)
Selects a channel for the software conversion.
Definition: adc1.h:3971
void ADC1_Init(void)
Initializes the ADC1 module based on the Config Wizard for MOTIX MCU configuration.
INLINE void ADC1_Ch2_Int_En(void)
enables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3585
INLINE void ADC1_Ch0_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 0 number of sampling ticks.
Definition: adc1.h:2476
INLINE void ADC1_Ch2_Int_Dis(void)
disables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3608
INLINE void ADC1_Ch0_Int_Dis(void)
disables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3518
INLINE void ADC1_Power_Off(void)
Disables the ADC1 module.
Definition: adc1.h:850
INLINE void ADC1_Ch3_Int_Dis(void)
disables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3653
INLINE void ADC1_VDH_Attenuator_Zlow_Set(void)
Disables the output attenuator for VDH.
Definition: adc1.h:3275
INLINE void ADC1_Ch5_Overwrite_Set(void)
Sets the ADC1 channel 5 result register to "overwrite".
Definition: adc1.h:3010
INLINE void ADC1_ESM_Channel_Set(uint32 mask_ch)
Set channels in ESM sequence.
Definition: adc1.h:3132
INLINE uint8 ADC1_Ch2_ResultValid_Get(void)
Reads the valid flag for the channel 2 (P2.2) result.
Definition: adc1.h:1922
INLINE void ADC1_VDH_Attenuator_Off(void)
Disables the input attenuator for VDH.
Definition: adc1.h:3203
INLINE void ADC1_ESM_Int_Clr(void)
clears Exceptional Sequence Measurement (ESM) flag.
Definition: adc1.h:3473
INLINE void ADC1_DIVA_Set(uint32 a)
ADC1 analog clock divider. .
Definition: adc1.h:907
INLINE void ADC1_Ch6_Int_Dis(void)
disables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3788
INLINE bool ADC1_Busy(void)
Reads the overall status of the ADC1.
Definition: adc1.h:4014
INLINE void ADC1_Ch5_DataWidth_8bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 8-bit.
Definition: adc1.h:2369
INLINE void ADC1_Ch6_DataWidth_10bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 10-bit.
Definition: adc1.h:2447
INLINE void ADC1_ESM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Set ADC1 ESM Trigger Selection.
Definition: adc1.h:4038
INLINE uint8 ADC1_Busy_Sts(void)
Reads the overall status of the ADC1.
Definition: adc1.h:1092
INLINE void ADC1_EIM_Int_Clr(void)
clears Exceptional Interrupt Measurement (EIM) flag.
Definition: adc1.h:3451
INLINE uint16 ADC1_Ch0_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1405
INLINE void ADC1_Ch0_Int_En(void)
enables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3495
INLINE uint8 ADC1_Ch1_ResultValid_Get(void)
Reads the valid flag for the channel 1 (CSA) result.
Definition: adc1.h:1890
ADC1_TRIGG_SEL
Definition: adc1.h:253
@ ADC1_Trigg_GPT12E_T3
Definition: adc1.h:257
@ ADC1_Trigg_Timer3
Definition: adc1.h:260
@ ADC1_Trigg_CCU6_Ch3
Definition: adc1.h:255
@ ADC1_Trigg_Timer21
Definition: adc1.h:259
@ ADC1_Trigg_Timer2
Definition: adc1.h:258
@ ADC1_Trigg_GPT12E_T6
Definition: adc1.h:256
@ ADC1_Trigg_None
Definition: adc1.h:254
INLINE void ADC1_Ch6_Int_En(void)
enables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3765
INLINE void ADC1_Ch4_Int_Dis(void)
disables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3698
enum ADC1_TRIGG_SEL TADC1_TRIGG_SEL
#define ADC1_VDH_Attenuator_Range_0_20V
ADC1 VDH Attenuator Selection, 0V..20V.
Definition: adc1.h:129
INLINE uint8 ADC1_Sample_Sts(void)
Reads the sample status of a ongoing measurement.
Definition: adc1.h:1060
INLINE void ADC1_SW_Ch_Sel(uint32 a)
Selects a channel for the software conversion.
Definition: adc1.h:887
ADC1_ANON
Definition: adc1.h:233
@ ADC1_ANON_NORMAL
Definition: adc1.h:237
@ ADC1_ANON_OFF
Definition: adc1.h:234
@ ADC1_ANON_S_STANDBY
Definition: adc1.h:235
@ ADC1_ANON_F_STANDBY
Definition: adc1.h:236
INLINE uint8 ADC1_Current_Active_Channel_Sts(void)
Reads the currently active channel.
Definition: adc1.h:1192
INLINE void ADC1_Sequence3_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 3, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1283
INLINE void ADC1_Sequence5_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 5, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1329
INLINE uint16 ADC1_P20_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1646
INLINE bool ADC1_isEndOfConversion(void)
checks EndOfConversion ready (Software Mode)
Definition: adc1.h:4044
INLINE uint16 ADC1_Ch2_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1465
INLINE void ADC1_Ch3_Overwrite_Set(void)
Sets the ADC1 channel 3 result register to "overwrite".
Definition: adc1.h:2890
INLINE void ADC1_Ch0_Overwrite_Set(void)
Sets the ADC1 channel 0 result register to "overwrite".
Definition: adc1.h:2710
INLINE bool ADC1_GetSwModeResult(uint16 *pVar)
Get ADC1 latest software mode result.
Definition: adc1.h:4000
INLINE void ADC1_Ch0_Int_Clr(void)
clears ADC1 Channel 0 Interrupt flag.
Definition: adc1.h:3297
INLINE void ADC1_Ch3_DataWidth_8bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 8-bit.
Definition: adc1.h:2265
INLINE void ADC1_Sequence1_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 1, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1237
INLINE void ADC1_Sequence2_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 2, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1260
bool ADC1_GetChResult(uint16 *pVar, uint8 channel)
Get the 10-bit/8-bit value of the ADC1 Result Register of the selected ADC1 channel and returns the v...
union ADC1_ANON_U TADC1_ANON_U
INLINE void ADC1_Software_Mode_Sel(void)
ADC1 selects the Software Mode, measurements are performed on user request.
Definition: adc1.h:970
INLINE void ADC1_Ch3_Int_Clr(void)
clears ADC1 Channel 3 Interrupt flag.
Definition: adc1.h:3363
INLINE void ADC1_Ch5_DataWidth_10bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 10-bit.
Definition: adc1.h:2395
INLINE void ADC1_Ch6_DataWidth_8bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 8-bit.
Definition: adc1.h:2421
ADC1_EIM_REP_CNT
Definition: adc1.h:271
@ ADC1_128_Meas
Definition: adc1.h:279
@ ADC1_1_Meas
Definition: adc1.h:272
@ ADC1_4_Meas
Definition: adc1.h:274
@ ADC1_2_Meas
Definition: adc1.h:273
@ ADC1_32_Meas
Definition: adc1.h:277
@ ADC1_16_Meas
Definition: adc1.h:276
@ ADC1_8_Meas
Definition: adc1.h:275
@ ADC1_64_Meas
Definition: adc1.h:278
INLINE bool ADC1_GetEocSwMode(void)
Get ADC1 end of conversion status.
Definition: adc1.h:3988
INLINE void ADC1_Ch1_Int_Clr(void)
clears ADC1 Channel 1 Interrupt flag.
Definition: adc1.h:3319
INLINE uint8 ADC1_EOC_Sts(void)
Reads the End-of-Conversion status.
Definition: adc1.h:997
INLINE uint8 ADC1_Current_Active_Sequence_Sts(void)
Reads the currently active channel in Sequencer Mode.
Definition: adc1.h:1168
INLINE uint16 ADC1_EIM_Result_Get(void)
Reads the converted value from the EIM result register.
Definition: adc1.h:1616
INLINE void ADC1_Ch4_DataWidth_8bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 8-bit.
Definition: adc1.h:2317
INLINE uint8 ADC1_EIM_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2083
INLINE void ADC1_Ch4_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 4 number of sampling ticks.
Definition: adc1.h:2592
enum ADC1_EIM_REP_CNT TADC1_EIM_REP_CNT
INLINE void ADC1_Sequence6_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 6, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1352
bool ADC1_GetEIMResult(uint16 *pVar)
Get the 10-bit/8-bit value of the ADC1 EIM Result Register and returns the validity info.
INLINE bool ADC1_isESMactive(void)
checks Exceptional Sequencer Mode active
Definition: adc1.h:4068
INLINE void ADC1_Ch1_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 1 number of sampling ticks.
Definition: adc1.h:2505
INLINE void ADC1_Ch5_Int_En(void)
enables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3720
INLINE void ADC1_ANON_Set(uint32 a)
ADC1 set the Analog Module Mode.
Definition: adc1.h:926
bool VAREF_Enable(void)
Re-enables the internal VAREF LDO in case it was shutdown due to a previous failure.
INLINE void ADC1_Ch2_Overwrite_Set(void)
Sets the ADC1 channel 2 result register to "overwrite".
Definition: adc1.h:2830
#define ADC1_VDH_Attenuator_Range_0_30V
ADC1 VDH Attenuator Selection, 0V..30V.
Definition: adc1.h:127
INLINE void ADC1_Ch1_DataWidth_8bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 8-bit.
Definition: adc1.h:2161
INLINE uint16 ADC1_Ch6_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1585
INLINE void ADC1_Ch4_Overwrite_Set(void)
Sets the ADC1 channel 4 result register to "overwrite".
Definition: adc1.h:2950
INLINE uint16 ADC1_CSA_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1676
INLINE void ADC1_Ch2_Int_Clr(void)
clears ADC1 Channel 2 Interrupt flag.
Definition: adc1.h:3341
INLINE void ADC1_Ch2_DataWidth_8bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 8-bit.
Definition: adc1.h:2213
INLINE void ADC1_Ch5_Int_Dis(void)
disables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3743
enum ADC1_ANON TADC1_ANON
INLINE void ADC1_SOC_Set(void)
ADC1 Start of Conversion, for Software mode only.
Definition: adc1.h:867
INLINE void ADC1_Ch1_Int_Dis(void)
disables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3563
INLINE void ADC1_Ch6_Overwrite_Set(void)
Sets the ADC1 channel 6 result register to "overwrite".
Definition: adc1.h:3070
INLINE void ADC1_Ch4_DataWidth_10bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 10-bit.
Definition: adc1.h:2343
INLINE uint16 ADC1_Ch1_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1435
INLINE void ADC1_Sequence0_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 0, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1214
INLINE uint8 ADC1_Ch5_ResultValid_Get(void)
Reads the valid flag for the channel 5 (P2.5) result.
Definition: adc1.h:2018
INLINE void ADC1_Ch3_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 3 number of sampling ticks.
Definition: adc1.h:2563
INLINE TADC1_ANON ADC1_ANON_Sts(void)
Reads the Analog Part Switched On Mode status.
Definition: adc1.h:4080
INLINE uint16 ADC1_Ch3_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1495
INLINE uint8 ADC1_Ch6_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2050
INLINE void ADC1_VDH_Attenuator_Range_0_30V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 30V.
Definition: adc1.h:3905
INLINE void ADC1_VDH_Attenuator_On(void)
Enables the input attenuator for VDH.
Definition: adc1.h:3168
INLINE void ADC1_EIM_Repeat_Counter_Set(TADC1_EIM_REP_CNT repcnt)
Set ADC1 EIM Repeat Counter.
Definition: adc1.h:4032
INLINE void ADC1_EIM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Get ADC1 EIM Trigger Selection.
Definition: adc1.h:4026
INLINE uint8 ADC1_Ch4_ResultValid_Get(void)
Reads the valid flag for the channel 4 (P2.4) result.
Definition: adc1.h:1986
INLINE void ADC1_EIM_Int_En(void)
enables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3811
INLINE uint8 ADC1_VDH_Attenuator_Range_Get(void)
Reads the VDH Monitoring Input Attenuator Input Range Configuration.
Definition: adc1.h:3958
INLINE void ADC1_ESM_Int_Dis(void)
disables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3880
INLINE void ADC1_EIM_Channel_Set(uint32 ch)
Set EIM channel for measurement.
Definition: adc1.h:3101
bool ADC1_GetChResult_mV(uint16 *pVar_mV, uint8 channel)
Get the value of the ADC1 Result Register of the selected ADC1 channel in Millivolt (mV) and returns ...
INLINE void ADC1_Ch0_DataWidth_10bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 10-bit.
Definition: adc1.h:2135
INLINE void ADC1_Ch2_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 2 number of sampling ticks.
Definition: adc1.h:2534
INLINE void ADC1_Ch0_WaitForRead_Set(void)
Sets the ADC1 channel 0 result register to "wait for read".
Definition: adc1.h:2680
INLINE void ADC1_Ch6_WaitForRead_Set(void)
Sets the ADC1 channel 6 result register to "wait for read".
Definition: adc1.h:3040
bool ADC1_GetEIMResult_mV(uint16 *pVar_mV)
Get the value of the ADC1 EIM Result Register in Millivolt (mV) and returns the validity info.
INLINE void ADC1_Ch1_Int_En(void)
enables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3540
INLINE void ADC1_Ch2_DataWidth_10bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 10-bit.
Definition: adc1.h:2239
INLINE void ADC1_Ch0_DataWidth_8bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 8-bit.
Definition: adc1.h:2109
#define MF
Definition: tle987x.h:6093
#define ADC1
Definition: tle987x.h:6083
#define ADC1_SQ_FB_SQx_Msk
Definition: tle987x.h:6370
#define ADC1_RES_OUT1_WFR1_Pos
Definition: tle987x.h:6281
#define ADC1_RES_OUT5_OUT_CH5_Msk
Definition: tle987x.h:6320
#define ADC1_RES_OUT6_VF6_Msk
Definition: tle987x.h:6325
#define ADC1_SQ_FB_ESM_ACTIVE_Pos
Definition: tle987x.h:6371
#define ADC1_STC_4_7_ch6_Pos
Definition: tle987x.h:6389
#define ADC1_IE_CH3_IE_Pos
Definition: tle987x.h:6238
#define ADC1_CHx_ESM_TRIG_SEL_Msk
Definition: tle987x.h:6161
#define ADC1_ICLR_CH3_ICLR_Msk
Definition: tle987x.h:6218
#define ADC1_CTRL_STS_EOC_Msk
Definition: tle987x.h:6168
#define ADC1_CHx_ESM_TRIG_SEL_Pos
Definition: tle987x.h:6160
#define ADC1_IE_CH1_IE_Pos
Definition: tle987x.h:6242
#define ADC1_IE_CH3_IE_Msk
Definition: tle987x.h:6239
#define ADC1_ICLR_CH4_ICLR_Pos
Definition: tle987x.h:6215
#define ADC1_DWSEL_ch4_Pos
Definition: tle987x.h:6180
#define ADC1_SQ1_4_SQ4_Msk
Definition: tle987x.h:6350
#define ADC1_RES_OUT4_WFR4_Msk
Definition: tle987x.h:6309
#define ADC1_GLOBSTR_ANON_ST_Msk
Definition: tle987x.h:6197
#define ADC1_DWSEL_ch2_Pos
Definition: tle987x.h:6184
#define ADC1_IE_CH0_IE_Pos
Definition: tle987x.h:6244
#define ADC1_DWSEL_ch0_Pos
Definition: tle987x.h:6188
#define ADC1_ICLR_CH1_ICLR_Pos
Definition: tle987x.h:6221
#define ADC1_RES_OUT5_VF5_Msk
Definition: tle987x.h:6316
#define ADC1_RES_OUT5_WFR5_Pos
Definition: tle987x.h:6317
#define ADC1_STC_0_3_ch0_Pos
Definition: tle987x.h:6384
#define ADC1_IE_CH6_IE_Pos
Definition: tle987x.h:6232
#define ADC1_RES_OUT2_VF2_Pos
Definition: tle987x.h:6288
#define ADC1_ICLR_CH2_ICLR_Msk
Definition: tle987x.h:6220
#define ADC1_RES_OUT0_VF0_Pos
Definition: tle987x.h:6270
#define ADC1_RES_OUT4_VF4_Msk
Definition: tle987x.h:6307
#define ADC1_RES_OUT_EIM_VF8_Msk
Definition: tle987x.h:6343
#define ADC1_RES_OUT6_WFR6_Msk
Definition: tle987x.h:6327
#define ADC1_STC_4_7_ch5_Msk
Definition: tle987x.h:6392
#define ADC1_CTRL_STS_IN_MUX_SEL_Msk
Definition: tle987x.h:6166
#define ADC1_RES_OUT5_WFR5_Msk
Definition: tle987x.h:6318
#define ADC1_STC_4_7_ch4_Pos
Definition: tle987x.h:6393
#define ADC1_STC_4_7_ch6_Msk
Definition: tle987x.h:6390
#define ADC1_IE_CH4_IE_Msk
Definition: tle987x.h:6237
#define ADC1_RES_OUT3_OUT_CH3_Msk
Definition: tle987x.h:6302
#define ADC1_SQ_FB_EIM_ACTIVE_Pos
Definition: tle987x.h:6373
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos
Definition: tle987x.h:8249
#define ADC1_IE_CH2_IE_Msk
Definition: tle987x.h:6241
#define ADC1_RES_OUT0_WFR0_Msk
Definition: tle987x.h:6273
#define ADC1_SQ1_4_SQ2_Pos
Definition: tle987x.h:6353
#define ADC1_RES_OUT5_VF5_Pos
Definition: tle987x.h:6315
#define ADC1_SQ_FB_EIM_ACTIVE_Msk
Definition: tle987x.h:6374
#define ADC1_SQ_FB_SQx_Pos
Definition: tle987x.h:6369
#define ADC1_IE_CH1_IE_Msk
Definition: tle987x.h:6243
#define ADC1_GLOBSTR_SAMPLE_Pos
Definition: tle987x.h:6200
#define ADC1_RES_OUT5_OUT_CH5_Pos
Definition: tle987x.h:6319
#define ADC1_GLOBSTR_CHNR_Pos
Definition: tle987x.h:6198
#define ADC1_CHx_EIM_TRIG_SEL_Pos
Definition: tle987x.h:6153
#define ADC1_SQ1_4_SQ3_Pos
Definition: tle987x.h:6351
#define ADC1_RES_OUT2_OUT_CH2_Msk
Definition: tle987x.h:6293
#define ADC1_ICLR_CH1_ICLR_Msk
Definition: tle987x.h:6222
#define ADC1_RES_OUT6_VF6_Pos
Definition: tle987x.h:6324
#define ADC1_DWSEL_ch4_Msk
Definition: tle987x.h:6181
#define ADC1_DWSEL_ch6_Pos
Definition: tle987x.h:6176
#define ADC1_SQ5_8_SQ7_Pos
Definition: tle987x.h:6360
#define ADC1_SQ_FB_SQ_RUN_Msk
Definition: tle987x.h:6376
#define ADC1_SQ1_4_SQ4_Pos
Definition: tle987x.h:6349
#define ADC1_CTRL_STS_IN_MUX_SEL_Pos
Definition: tle987x.h:6165
#define ADC1_DWSEL_ch3_Msk
Definition: tle987x.h:6183
#define ADC1_STC_0_3_ch3_Msk
Definition: tle987x.h:6379
#define ADC1_SQ1_4_SQ1_Msk
Definition: tle987x.h:6356
#define ADC1_STC_0_3_ch3_Pos
Definition: tle987x.h:6378
#define ADC1_GLOBSTR_SAMPLE_Msk
Definition: tle987x.h:6201
#define ADC1_RES_OUT1_VF1_Msk
Definition: tle987x.h:6280
#define ADC1_RES_OUT0_VF0_Msk
Definition: tle987x.h:6271
#define ADC1_RES_OUT4_OUT_CH4_Msk
Definition: tle987x.h:6311
#define ADC1_GLOBSTR_CHNR_Msk
Definition: tle987x.h:6199
#define ADC1_CHx_ESM_ESM_0_Msk
Definition: tle987x.h:6163
#define ADC1_CHx_EIM_CHx_Msk
Definition: tle987x.h:6158
#define ADC1_STC_4_7_ch5_Pos
Definition: tle987x.h:6391
#define ADC1_ICLR_ESM_ICLR_Pos
Definition: tle987x.h:6205
#define ADC1_DWSEL_ch2_Msk
Definition: tle987x.h:6185
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos
Definition: tle987x.h:8253
#define ADC1_SQ5_8_SQ8_Pos
Definition: tle987x.h:6358
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos
Definition: tle987x.h:6346
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk
Definition: tle987x.h:6347
#define ADC1_SQ5_8_SQ5_Pos
Definition: tle987x.h:6364
#define ADC1_ICLR_EIM_ICLR_Msk
Definition: tle987x.h:6208
#define ADC1_SQ5_8_SQ6_Pos
Definition: tle987x.h:6362
#define ADC1_IE_CH5_IE_Pos
Definition: tle987x.h:6234
#define ADC1_CTRL_STS_PD_N_Pos
Definition: tle987x.h:6171
#define ADC1_ICLR_CH6_ICLR_Msk
Definition: tle987x.h:6212
#define ADC1_RES_OUT3_WFR3_Msk
Definition: tle987x.h:6300
#define ADC1_RES_OUT3_OUT_CH3_Pos
Definition: tle987x.h:6301
#define ADC1_STC_0_3_ch1_Msk
Definition: tle987x.h:6383
#define ADC1_ICLR_CH2_ICLR_Pos
Definition: tle987x.h:6219
#define ADC1_RES_OUT1_OUT_CH1_Msk
Definition: tle987x.h:6284
#define ADC1_CHx_EIM_REP_Msk
Definition: tle987x.h:6156
#define ADC1_RES_OUT0_OUT_CH0_Msk
Definition: tle987x.h:6275
#define ADC1_DWSEL_ch1_Msk
Definition: tle987x.h:6187
#define ADC1_ICLR_CH6_ICLR_Pos
Definition: tle987x.h:6211
#define ADC1_SQ1_4_SQ2_Msk
Definition: tle987x.h:6354
#define ADC1_ICLR_CH0_ICLR_Msk
Definition: tle987x.h:6224
#define ADC1_SQ_FB_SQ_RUN_Pos
Definition: tle987x.h:6375
#define ADC1_IE_CH0_IE_Msk
Definition: tle987x.h:6245
#define ADC1_ICLR_CH3_ICLR_Pos
Definition: tle987x.h:6217
#define ADC1_CTRL_STS_EOC_Pos
Definition: tle987x.h:6167
#define ADC1_DWSEL_ch3_Pos
Definition: tle987x.h:6182
#define ADC1_SQ_FB_ESM_ACTIVE_Msk
Definition: tle987x.h:6372
#define ADC1_GLOBSTR_BUSY_Msk
Definition: tle987x.h:6203
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk
Definition: tle987x.h:8252
#define ADC1_RES_OUT1_VF1_Pos
Definition: tle987x.h:6279
#define ADC1_ICLR_CH5_ICLR_Msk
Definition: tle987x.h:6214
#define ADC1_RES_OUT4_WFR4_Pos
Definition: tle987x.h:6308
#define ADC1_STC_4_7_ch4_Msk
Definition: tle987x.h:6394
#define ADC1_RES_OUT3_VF3_Pos
Definition: tle987x.h:6297
#define ADC1_SQ5_8_SQ7_Msk
Definition: tle987x.h:6361
#define ADC1_IE_CH6_IE_Msk
Definition: tle987x.h:6233
#define ADC1_CTRL_STS_PD_N_Msk
Definition: tle987x.h:6172
#define ADC1_IE_CH5_IE_Msk
Definition: tle987x.h:6235
#define ADC1_SQ_FB_CHx_Msk
Definition: tle987x.h:6368
#define ADC1_RES_OUT0_OUT_CH0_Pos
Definition: tle987x.h:6274
#define ADC1_ICLR_CH5_ICLR_Pos
Definition: tle987x.h:6213
#define ADC1_STC_0_3_ch2_Pos
Definition: tle987x.h:6380
#define ADC1_CHx_EIM_CHx_Pos
Definition: tle987x.h:6157
#define ADC1_STC_0_3_ch2_Msk
Definition: tle987x.h:6381
#define ADC1_DWSEL_ch5_Msk
Definition: tle987x.h:6179
#define ADC1_CHx_EIM_TRIG_SEL_Msk
Definition: tle987x.h:6154
#define ADC1_IE_ESM_IE_Msk
Definition: tle987x.h:6227
#define ADC1_CTRL_STS_SOC_Msk
Definition: tle987x.h:6170
#define ADC1_RES_OUT2_OUT_CH2_Pos
Definition: tle987x.h:6292
#define ADC1_DWSEL_ch6_Msk
Definition: tle987x.h:6177
#define ADC1_ICLR_CH4_ICLR_Msk
Definition: tle987x.h:6216
#define ADC1_RES_OUT2_WFR2_Pos
Definition: tle987x.h:6290
#define ADC1_CHx_ESM_ESM_0_Pos
Definition: tle987x.h:6162
#define ADC1_ICLR_CH0_ICLR_Pos
Definition: tle987x.h:6223
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk
Definition: tle987x.h:8250
#define ADC1_SQ1_4_SQ1_Pos
Definition: tle987x.h:6355
#define ADC1_IE_EIM_IE_Pos
Definition: tle987x.h:6228
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk
Definition: tle987x.h:8254
#define ADC1_GLOBSTR_ANON_ST_Pos
Definition: tle987x.h:6196
#define ADC1_DWSEL_ch1_Pos
Definition: tle987x.h:6186
#define ADC1_IE_EIM_IE_Msk
Definition: tle987x.h:6229
#define ADC1_STC_0_3_ch0_Msk
Definition: tle987x.h:6385
#define ADC1_GLOBSTR_BUSY_Pos
Definition: tle987x.h:6202
#define ADC1_RES_OUT6_OUT_CH6_Msk
Definition: tle987x.h:6329
#define ADC1_SQ5_8_SQ5_Msk
Definition: tle987x.h:6365
#define ADC1_ICLR_EIM_ICLR_Pos
Definition: tle987x.h:6207
#define ADC1_RES_OUT3_VF3_Msk
Definition: tle987x.h:6298
#define ADC1_RES_OUT6_OUT_CH6_Pos
Definition: tle987x.h:6328
#define ADC1_STC_0_3_ch1_Pos
Definition: tle987x.h:6382
#define ADC1_RES_OUT_EIM_VF8_Pos
Definition: tle987x.h:6342
#define ADC1_GLOBCTR_ANON_Pos
Definition: tle987x.h:6191
#define ADC1_ICLR_ESM_ICLR_Msk
Definition: tle987x.h:6206
#define ADC1_CHx_EIM_REP_Pos
Definition: tle987x.h:6155
#define ADC1_IE_CH2_IE_Pos
Definition: tle987x.h:6240
#define ADC1_RES_OUT6_WFR6_Pos
Definition: tle987x.h:6326
#define ADC1_RES_OUT2_WFR2_Msk
Definition: tle987x.h:6291
#define ADC1_GLOBCTR_ANON_Msk
Definition: tle987x.h:6192
#define ADC1_SQ_FB_CHx_Pos
Definition: tle987x.h:6367
#define ADC1_IE_CH4_IE_Pos
Definition: tle987x.h:6236
#define ADC1_SQ5_8_SQ6_Msk
Definition: tle987x.h:6363
#define ADC1_SQ5_8_SQ8_Msk
Definition: tle987x.h:6359
#define ADC1_RES_OUT0_WFR0_Pos
Definition: tle987x.h:6272
#define ADC1_RES_OUT1_WFR1_Msk
Definition: tle987x.h:6282
#define ADC1_GLOBCTR_DIVA_Msk
Definition: tle987x.h:6194
#define ADC1_DWSEL_ch0_Msk
Definition: tle987x.h:6189
#define ADC1_RES_OUT3_WFR3_Pos
Definition: tle987x.h:6299
#define ADC1_IE_ESM_IE_Pos
Definition: tle987x.h:6226
#define ADC1_RES_OUT1_OUT_CH1_Pos
Definition: tle987x.h:6283
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos
Definition: tle987x.h:8251
#define ADC1_SQ1_4_SQ3_Msk
Definition: tle987x.h:6352
#define ADC1_DWSEL_ch5_Pos
Definition: tle987x.h:6178
#define ADC1_GLOBCTR_DIVA_Pos
Definition: tle987x.h:6193
#define ADC1_RES_OUT4_OUT_CH4_Pos
Definition: tle987x.h:6310
#define ADC1_CTRL_STS_SOC_Pos
Definition: tle987x.h:6169
#define ADC1_RES_OUT2_VF2_Msk
Definition: tle987x.h:6289
#define ADC1_RES_OUT4_VF4_Pos
Definition: tle987x.h:6306
SFR low level access library.
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:362
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:407
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:432
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:347
INLINE uint8 u8_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 8-bit field of a 32-bit register.
Definition: sfr_access.h:422
INLINE uint32 u32_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 32-bit field of a 32-bit register.
Definition: sfr_access.h:437
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:148
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155
uint32 dword
Definition: adc1.h:242
TADC1_ANON adc1_anon
Definition: adc1.h:243