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Infineon MOTIX™ MCU TLE987x Device Family SDK
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ADC2 Module (ADC2)
#include <tle987x.h>
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union { ... } CAL_CH0_1 |
union { ... } CAL_CH2_3 |
union { ... } CAL_CH4_5 |
union { ... } CAL_CH6_7 |
union { ... } CAL_CH8_9 |
[1..0] Filter Coefficients ADC channel 0
[7..0] Channel 0 lower trigger level
[7..0] Channel 0 upper trigger level
[0..0] Upper threshold IIR filter enable ch 0
[0..0] Lower threshold IIR filter enable ch 0
[3..2] Filter Coefficients ADC channel 1
[15..8] Channel 1 lower trigger level
[15..8] Channel 1 upper trigger level
[1..1] Upper threshold IIR filter enable ch 1
[1..1] Lower threshold IIR filter enable ch 1
[5..4] Filter Coefficients ADC channel 2
[23..16] Channel 2 lower trigger level
[23..16] Channel 2 upper trigger level
[2..2] Upper threshold IIR filter enable ch 2
[2..2] Lower threshold IIR filter enable ch 2
[7..6] Filter Coefficients ADC channel 3
[31..24] Channel 3 lower trigger level
[31..24] Channel 3 upper trigger level
[3..3] Upper threshold IIR filter enable ch 3
[3..3] Lower threshold IIR filter enable ch 3
[9..8] Filter Coefficients ADC channel 4
[7..0] Channel 4 lower trigger level
[7..0] Channel 4 upper trigger level
[4..4] Upper threshold IIR filter enable ch 4
[4..4] Lower threshold IIR filter enable ch 4
[11..10] Filter Coefficients ADC channel 5
[15..8] Channel 5 lower trigger level
[15..8] Channel 5 upper trigger level
[5..5] Upper threshold IIR filter enable ch 5
[5..5] Lower threshold IIR filter enable ch 5
[3..2] Filter Coefficients ADC channel 7
[15..8] Channel 7 lower trigger level
[15..8] Channel 7 upper trigger level
union { ... } CHx_EIM |
union { ... } CHx_ESM |
union { ... } CNT0_3_LOWER |
union { ... } CNT0_3_UPPER |
union { ... } CNT4_5_LOWER |
union { ... } CNT4_5_UPPER |
union { ... } CNT6_9_LOWER |
union { ... } CNT6_9_UPPER |
union { ... } CTRL1 |
union { ... } CTRL2 |
union { ... } CTRL4 |
union { ... } CTRL_STS |
[11..11] Exceptional interrupt measurement (EIM) Trigger Event enable
[16..16] Enable for Exceptional Sequence Measurement Trigger Event
union { ... } FILT_LO_CTRL |
union { ... } FILT_OUT0 |
union { ... } FILT_OUT1 |
union { ... } FILT_OUT2 |
union { ... } FILT_OUT3 |
union { ... } FILT_OUT4 |
union { ... } FILT_OUT5 |
union { ... } FILT_OUT6 |
union { ... } FILT_OUT7 |
union { ... } FILT_OUT8 |
union { ... } FILT_OUT9 |
union { ... } FILT_UP_CTRL |
union { ... } FILTCOEFF0_5 |
union { ... } FILTCOEFF6_9 |
union { ... } HV_STS |
union { ... } MMODE0_5 |
(@ 0x00000000) ADC2 Control and Status Register
(@ 0x00000004) Sequencer Feedback Register
(@ 0x00000008) Channel Settings Bits for Exceptional Interrupt Measurement
(@ 0x0000000C) Channel Settings Bits for Exceptional Sequence Measurement
(@ 0x00000014) Measurement Unit Control Register 1
(@ 0x00000018) Measurement Unit Control Register 2
(@ 0x0000001C) Measurement Unit Control Register 4
(@ 0x00000020) Measurement Channel Enable Bits for Cycle 1-4
(@ 0x00000024) Measurement Channel Enable Bits for Cycle 5 - 8
(@ 0x00000028) Measurement Channel Enable Bits for Cycle 9 - 10
(@ 0x0000002C) Measurement Channel Enable Bits for Cycle 1 - 8
(@ 0x00000030) Measurement Channel Enable Bits for Cycle 9 and 10
(@ 0x00000034) Calibration for Channel 0 and 1
(@ 0x00000038) Calibration for Channel 2 and 3
(@ 0x0000003C) Calibration for Channel 4 and 5
(@ 0x00000040) Calibration for Channel 6 and 7
(@ 0x00000044) Calibration for Channel 8 and 9
(@ 0x00000048) Filter Coefficients ADC Channel 0-5
(@ 0x0000004C) Filter Coefficents ADC Channel 6-9
(@ 0x00000050) ADC or Filter Output Channel 0
(@ 0x00000054) ADC or Filter Output Channel 1
(@ 0x00000058) ADC or Filter Output Channel 2
(@ 0x0000005C) ADC or Filter Output Channel 3
(@ 0x00000060) ADC or Filter Output Channel 4
(@ 0x00000064) ADC or Filter Output Channel 5
(@ 0x00000068) ADC or Filter Output Channel 6
(@ 0x0000006C) ADC or Filter Output Channel 7
(@ 0x00000070) ADC or Filter Output Channel 8
(@ 0x00000074) ADC or Filter Output Channel 9
(@ 0x00000078) Upper Threshold Filter Enable
(@ 0x0000007C) Lower Threshold Filter Enable
(@ 0x00000080) Lower Comparator Trigger Level Channel 0 -3
(@ 0x00000084) Lower Comparator Trigger Level Channel 4 and 5
(@ 0x00000088) Lower Comparator Trigger Level Channel 6 -9
(@ 0x0000008C) Upper Comparator Trigger Level Channel 0-3
(@ 0x00000090) Upper Comparator Trigger Level Channel 4 -5
(@ 0x00000094) Upper Comparator Trigger Level Channel 6 -9
(@ 0x00000098) Lower Counter Trigger Level Channel 0 - 3
(@ 0x0000009C) Lower Counter Trigger Level Channel 4 and 5
(@ 0x000000A0) Lower Counter Trigger Level Channel 6 - 9
(@ 0x000000A4) Upper Counter Trigger Level Channel 0 - 3
(@ 0x000000A8) Upper Counter Trigger Level Channel 4 and 5
(@ 0x000000AC) Upper Counter Trigger Level Channel 6 -9
(@ 0x000000B0) Overvoltage Measurement Mode of Ch 0-5
(@ 0x000000BC) ADC2 HV Status Register
[12..12] Exceptional interrupt measurement (EIM) Trigger Trigger select
[10..10] Exceptional Sequence Measurement Trigger Select
union { ... } SQ1_4 |
union { ... } SQ1_8_int |
union { ... } SQ5_8 |
union { ... } SQ9_10 |
union { ... } SQ9_10_int |
union { ... } SQ_FB |
union { ... } TH0_3_LOWER |
union { ... } TH0_3_UPPER |
union { ... } TH4_5_LOWER |
union { ... } TH4_5_UPPER |
union { ... } TH6_9_LOWER |
union { ... } TH6_9_UPPER |
__IM uint32_t |