TLE986x Device Family SDK
dma.h
Go to the documentation of this file.
1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2015, Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** DM Daniel Mysliwitz **
45 ** JO Julia Ott **
46 ** BG Blandine Guillot **
47 *******************************************************************************/
48 
49 /*******************************************************************************
50 ** Revision Control History **
51 ********************************************************************************
52 ** V0.1.0: 2015-11-25, DM: Initial version **
53 ** V0.1.1: 2017-07-09, DM: Interrupt macros added, scatter-gather support **
54 ** added **
55 ** V0.1.2: 2017-07-12, DM: Setup task for scatter-gather added **
56 ** V0.1.3: 2017-07-20, DM: API macros added **
57 ** V0.1.4: 2017-09-22, DM: MISRA 2012 compliance, the following PC-Lint **
58 ** rules are globally deactivated: **
59 ** - Info 793: ANSI/ISO limit of 6 'significant **
60 ** characters in an external identifier **
61 ** - Note 950: Non-ANSI reserved word or construct: **
62 ** '_to_brackets' [MISRA Rule 1] **
63 ** - Note 923: cast from unsigned int to pointer **
64 ** [MISRA Rule 45] **
65 ** - Note 923: cast from pointer to unsigned int **
66 ** [MISRA Rule 45] **
67 ** - Info 765: Info 765: external '...' could be **
68 ** made static [MISRA Rule 23] **
69 ** - Error 18: Symbol '...' redeclared (void / **
70 ** nonvoid) ... [MISRA Rule 26], [Encompasses **
71 ** MISRA Rule 72] **
72 ** V0.1.5: 2018-03-12, DM: DMA Ch13 (SDADC) added **
73 ** DMA_MASK_CHx macros changed due to MISRA 2012 **
74 ** Replaced macros by INLINE functions **
75 ** Replaced register accesses within functions by **
76 ** function calls **
77 ** Replaced __STATIC_INLINE by INLINE **
78 ** Renamed DMA entries according to channel number **
79 ** V0.1.6: 2018-11-27, JO: Doxygen update, moved revision history from **
80 ** dma.c to dma.h **
81 ** V0.1.7: 2019-02-21, DM: DMA structures modified to be ARMCC v6 compliant **
82 ** DMA base struct fixed set to upper most address **
83 ** 3KB RAM: 0x18000A00..0x18000BFF **
84 ** 6KB RAM: 0x18001600..0x180017FF **
85 ** 8KB RAM: 0x18001E00..0x18001FFF **
86 ** V0.1.8: 2019-08-01, JO: Change from #ifdef TLE98xy to #ifdef UC_FEATURE_ **
87 ** V0.1.9: 2020-02-28, BG: Updated revision history format **
88 ** V0.2.0: 2020-10-12, JO: EP-506: remove ARMCC v6 Compiler warnings **
89 ** - Initialized alternate table entry **
90 ** - Disabled ARMCC v6 warnings -Wmissing-variable- **
91 ** declarations, -Wunreachable-code, -Wpedantic, **
92 ** and -Wcovered-switch-default locally **
93 ** in file dma.c **
94 ** V0.2.1: 2020-10-28, DM: EP-566: set DMA struct to volatile to remove **
95 ** ARMCC v6 O3 LTO problem **
96 *******************************************************************************/
97 
98 #ifndef _DMA_H
99 #define _DMA_H
100 
101 /*******************************************************************************
102 ** Includes **
103 *******************************************************************************/
104 #include "tle986x.h"
105 #include "types.h"
106 #include "dma_defines.h"
107 #include "sfr_access.h"
108 
109 /*******************************************************************************
110 ** Private Macro Definitions **
111 *******************************************************************************/
112 
113 /*******************************************************************************
114 ** Global Macro Definitions **
115 *******************************************************************************/
117 #define DMA_CH0 (0u)
118 
119 #define DMA_CH1 (1u)
120 
121 #define DMA_CH2 (2u)
122 
123 #define DMA_CH3 (3u)
124 
125 #define DMA_CH4 (4u)
126 
127 #define DMA_CH5 (5u)
128 
129 #define DMA_CH6 (6u)
130 
131 #define DMA_CH7 (7u)
132 
133 #define DMA_CH8 (8u)
134 
135 #define DMA_CH9 (9u)
136 
137 #define DMA_CH10 (10u)
138 
139 #define DMA_CH11 (11u)
140 
141 #define DMA_CH12 (12u)
142 #if defined UC_FEATURE_DMA_CH13
143 
144  #define DMA_CH13 (13u)
145 #endif /* UC_FEATURE_DMA_CH13 */
146 
148 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
149 
150 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
151 
152 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
153 
154 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
155 
156 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
157 
158 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
159 
160 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
161 
162 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
163 
164 #define DMA_MASK_CH8 ((uint16)1u << DMA_CH8)
165 
166 #define DMA_MASK_CH9 ((uint16)1u << DMA_CH9)
167 
168 #define DMA_MASK_CH10 ((uint16)1u << DMA_CH10)
169 
170 #define DMA_MASK_CH11 ((uint16)1u << DMA_CH11)
171 
172 #define DMA_MASK_CH12 ((uint16)1u << DMA_CH12)
173 #if defined UC_FEATURE_DMA_CH13
174 
175  #define DMA_MASK_CH13 ((uint16)1u << DMA_CH13)
176 #endif /* UC_FEATURE_DMA_CH13 */
177 
181 typedef enum _TDMA_Transfer_Size
182 {
183  DMA_8Bit_Transfer = 0u,
184  DMA_16Bit_Transfer = 1u,
185  DMA_32Bit_Transfer = 2u
187 
191 typedef enum _TDMA_Increment_Size
192 {
193  DMA_Inc_8bit = 0u,
194  DMA_Inc_16bit = 1u,
195  DMA_Inc_32bit = 2u
197 
202 {
203  DMA_No_Inc = 0u,
204  DMA_Src_Inc = 1u,
205  DMA_Dst_Inc = 2u,
206  DMA_Src_Dst_Inc = 3u
208 
212 typedef enum _TDMA_Cycle_Types
213 {
223 
224 /*******************************************************************************
225 ** Global Type Definitions **
226 *******************************************************************************/
230 typedef union
231 {
232  uint32 reg;
233  struct
234  {
235  uint32 Cycle_Ctrl: 3;
236  uint32 Next_UseBurst: 1;
237  uint32 N_Minus_1: 10;
238  uint32 R_Power: 4;
239  uint32 Src_Prot_Ctrl: 3;
240  uint32 Dst_Prot_Ctrl: 3;
241  uint32 Src_Size: 2;
242  uint32 Src_Inc: 2;
243  uint32 Dst_Size: 2;
244  uint32 Dst_Inc: 2;
245  } bit;
246 } TControl;
247 
251 typedef struct
252 {
253  uint32 Src_End_Ptr;
254  uint32 Dst_End_Ptr;
255  TControl Control;
256  uint32 reserved;
257 } TDMA_Entry;
258 
259 
260 /*******************************************************************************
261 ** Global Inline Function Definitions **
262 *******************************************************************************/
280 INLINE void DMA_CH0_Int_Clr(void)
281 {
283 }
284 
302 INLINE void DMA_CH1_Int_Clr(void)
303 {
305 }
306 
324 INLINE void DMA_CH2_Int_Clr(void)
325 {
327 }
328 
346 INLINE void DMA_CH3_Int_Clr(void)
347 {
349 }
350 
368 INLINE void DMA_CH4_Int_Clr(void)
369 {
371 }
372 
390 INLINE void DMA_CH5_Int_Clr(void)
391 {
393 }
394 
412 INLINE void DMA_CH6_Int_Clr(void)
413 {
415 }
416 
434 INLINE void DMA_CH7_Int_Clr(void)
435 {
437 }
438 
456 INLINE void DMA_CH8_Int_Clr(void)
457 {
459 }
460 
478 INLINE void DMA_CH9_Int_Clr(void)
479 {
481 }
482 
500 INLINE void DMA_CH10_Int_Clr(void)
501 {
503 }
504 
522 INLINE void DMA_CH11_Int_Clr(void)
523 {
525 }
526 
544 INLINE void DMA_CH12_Int_Clr(void)
545 {
547 }
548 
549 #if defined UC_FEATURE_DMA_CH13
550 
567 INLINE void DMA_CH13_Int_Clr(void)
568 {
570 }
571 #endif /* UC_FEATURE_DMA_CH13 */
572 
590 INLINE void DMA_CH0_Int_En(void)
591 {
593 }
594 
613 INLINE void DMA_CH0_Int_Dis(void)
614 {
616 }
617 
635 INLINE void DMA_CH1_Int_En(void)
636 {
638 }
639 
658 INLINE void DMA_CH1_Int_Dis(void)
659 {
661 }
662 
680 INLINE void DMA_CH2_Int_En(void)
681 {
683 }
684 
703 INLINE void DMA_CH2_Int_Dis(void)
704 {
706 }
707 
725 INLINE void DMA_CH3_Int_En(void)
726 {
728 }
729 
748 INLINE void DMA_CH3_Int_Dis(void)
749 {
751 }
752 
770 INLINE void DMA_CH4_Int_En(void)
771 {
773 }
774 
793 INLINE void DMA_CH4_Int_Dis(void)
794 {
796 }
797 
815 INLINE void DMA_CH5_Int_En(void)
816 {
818 }
819 
838 INLINE void DMA_CH5_Int_Dis(void)
839 {
841 }
842 
860 INLINE void DMA_CH6_Int_En(void)
861 {
863 }
864 
883 INLINE void DMA_CH6_Int_Dis(void)
884 {
886 }
887 
905 INLINE void DMA_CH7_Int_En(void)
906 {
908 }
909 
928 INLINE void DMA_CH7_Int_Dis(void)
929 {
931 }
932 
950 INLINE void DMA_CH8_Int_En(void)
951 {
953 }
954 
973 INLINE void DMA_CH8_Int_Dis(void)
974 {
976 }
977 
995 INLINE void DMA_CH9_Int_En(void)
996 {
998 }
999 
1018 INLINE void DMA_CH9_Int_Dis(void)
1019 {
1021 }
1022 
1040 INLINE void DMA_CH10_Int_En(void)
1041 {
1043 }
1044 
1063 INLINE void DMA_CH10_Int_Dis(void)
1064 {
1066 }
1067 
1085 INLINE void DMA_CH11_Int_En(void)
1086 {
1088 }
1089 
1108 INLINE void DMA_CH11_Int_Dis(void)
1109 {
1111 }
1112 
1130 INLINE void DMA_CH12_Int_En(void)
1131 {
1133 }
1134 
1153 INLINE void DMA_CH12_Int_Dis(void)
1154 {
1156 }
1157 
1158 #if defined UC_FEATURE_DMA_CH13
1159 
1176 INLINE void DMA_CH13_Int_En(void)
1177 {
1179 }
1180 
1199 INLINE void DMA_CH13_Int_Dis(void)
1200 {
1202 }
1203 #endif /* UC_FEATURE_DMA_CH13 */
1204 
1220 INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
1221 {
1223 }
1224 
1240 INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
1241 {
1243 }
1244 
1261 {
1263 }
1264 
1281 {
1283 }
1284 
1301 {
1303 }
1304 
1313 {
1314  return ( (uint32)(DMA->ALT_CTRL_BASE_PTR.reg + (DMA_Ch * sizeof(TDMA_Entry))) );
1315 }
1316 
1325 {
1326  return ( (uint32)(DMA->CTRL_BASE_PTR.reg + (DMA_Ch * sizeof(TDMA_Entry))) );
1327 }
1328 
1329 /*******************************************************************************
1330 ** Global Variable Declarations **
1331 *******************************************************************************/
1332 
1333 /*******************************************************************************
1334 ** Global Function Declarations **
1335 *******************************************************************************/
1336 #if (DMA_XML_VERSION >= 10200)
1337 
1342 void DMA_Init(void);
1343 
1376 void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst,
1377  uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment);
1378 
1379 
1414 void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt);
1415 
1461 TDMA_Entry *DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask);
1462 
1503 void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks);
1504 
1505 
1544 void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks);
1545 
1588 TDMA_Entry *DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst,
1589  uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment);
1590 
1615 INLINE void DMA_Master_En(void);
1616 
1617 /*******************************************************************************
1618 ** Global Inline Function Definitions **
1619 *******************************************************************************/
1620 INLINE void DMA_Master_En(void)
1621 {
1622  /* arm the DMA */
1623  DMA->CFG.bit.MASTER_ENABLE = 1u;
1624 }
1625 #else
1626 #error "use IFXConfigWizard XML Version V1.2.0 or greater"
1627 #endif
1628 
1629 #endif
DMA_CH6_Int_Clr
INLINE void DMA_CH6_Int_Clr(void)
clears DMA Channel 6 Interrupt flag.
Definition: dma.h:405
DMA_Alternate_Struct_Usage_Set
INLINE void DMA_Alternate_Struct_Usage_Set(uint32 mask_ch)
selects the alternate data structure for the corresponding DMA channel.
Definition: dma.h:1293
SCU_DMAIEN1_CH2IE_Msk
#define SCU_DMAIEN1_CH2IE_Msk
Definition: tle986x.h:8668
SCU_DMAIRC1CLR_CH8C_Msk
#define SCU_DMAIRC1CLR_CH8C_Msk
Definition: tle986x.h:8705
DMA_Master_En
INLINE void DMA_Master_En(void)
Enabled the DMA master.
Definition: dma.h:1610
DMA_CH12_Int_Dis
INLINE void DMA_CH12_Int_Dis(void)
disables DMA Channel 12 Interrupt.
Definition: dma.h:1146
DMA_Cycle_Type_Auto
Definition: dma.h:211
DMA_CH4_Int_En
INLINE void DMA_CH4_Int_En(void)
enables DMA Channel 4 Interrupt.
Definition: dma.h:763
DMA_Cycle_Type_PerSctGthAlt
Definition: dma.h:216
DMA_CHx_Entry_Pri
INLINE uint32 DMA_CHx_Entry_Pri(uint8 DMA_Ch)
This function returns the address inside the primary structure in RAM for a given DMA channel.
Definition: dma.h:1317
DMA_CH5_Int_Clr
INLINE void DMA_CH5_Int_Clr(void)
clears DMA Channel 5 Interrupt flag.
Definition: dma.h:383
SCU_DMAIRC1CLR_CH1C_Msk
#define SCU_DMAIRC1CLR_CH1C_Msk
Definition: tle986x.h:8719
SCU_DMAIRC2CLR_SSC2C_Pos
#define SCU_DMAIRC2CLR_SSC2C_Pos
Definition: tle986x.h:8740
SCU_DMAIEN2_TRSEQ2RDYIE_Pos
#define SCU_DMAIEN2_TRSEQ2RDYIE_Pos
Definition: tle986x.h:8680
SCU_DMAIRC2CLR_TRSEQ1DYC_Pos
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos
Definition: tle986x.h:8746
SCU_DMAIEN2_TRSEQ2RDYIE_Msk
#define SCU_DMAIEN2_TRSEQ2RDYIE_Msk
Definition: tle986x.h:8681
SCU_DMAIRC1CLR_CH5C_Msk
#define SCU_DMAIRC1CLR_CH5C_Msk
Definition: tle986x.h:8711
SCU_DMAIRC1CLR_CH7C_Pos
#define SCU_DMAIRC1CLR_CH7C_Pos
Definition: tle986x.h:8706
types.h
General type declarations.
SCU_DMAIEN2_GPT12IE_Msk
#define SCU_DMAIEN2_GPT12IE_Msk
Definition: tle986x.h:8675
DMA_CH4_Int_Dis
INLINE void DMA_CH4_Int_Dis(void)
disables DMA Channel 4 Interrupt.
Definition: dma.h:786
SCU_DMAIEN2_SSCTXIE_Pos
#define SCU_DMAIEN2_SSCTXIE_Pos
Definition: tle986x.h:8678
SCU_DMAIRC2CLR_TRSEQ2DYC_Msk
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk
Definition: tle986x.h:8745
DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk
Definition: tle986x.h:7788
DMA_CH6_Int_Dis
INLINE void DMA_CH6_Int_Dis(void)
disables DMA Channel 6 Interrupt.
Definition: dma.h:876
SCU_DMAIRC2CLR_GPT12C_Pos
#define SCU_DMAIRC2CLR_GPT12C_Pos
Definition: tle986x.h:8738
DMA_CH11_Int_Dis
INLINE void DMA_CH11_Int_Dis(void)
disables DMA Channel 11 Interrupt.
Definition: dma.h:1101
DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos
Definition: tle986x.h:7787
DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk
Definition: tle986x.h:7818
DMA_Inc_16bit
Definition: dma.h:189
_TDMA_Cycle_Types
_TDMA_Cycle_Types
This enum lists the cycle type options for the DMA.
Definition: dma.h:207
DMA_CH9_Int_En
INLINE void DMA_CH9_Int_En(void)
enables DMA Channel 9 Interrupt.
Definition: dma.h:988
SCU_DMAIRC1CLR_CH3C_Msk
#define SCU_DMAIRC1CLR_CH3C_Msk
Definition: tle986x.h:8715
DMA_CH11_Int_En
INLINE void DMA_CH11_Int_En(void)
enables DMA Channel 11 Interrupt.
Definition: dma.h:1078
SCU_DMAIEN1_CH7IE_Msk
#define SCU_DMAIEN1_CH7IE_Msk
Definition: tle986x.h:8658
DMA_Channel_MemSctGth_Set
void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.
DMA_CH10_Int_Clr
INLINE void DMA_CH10_Int_Clr(void)
clears DMA Channel 10 Interrupt flag.
Definition: dma.h:493
SCU_DMAIEN2_GPT12IE_Pos
#define SCU_DMAIEN2_GPT12IE_Pos
Definition: tle986x.h:8674
DMA_Task_SctGth_Set
TDMA_Entry * DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
Sets up a task to be used with memory scatter-gather mode.
DMA_CH2_Int_En
INLINE void DMA_CH2_Int_En(void)
enables DMA Channel 2 Interrupt.
Definition: dma.h:673
DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos
Definition: tle986x.h:7793
SCU_DMAIEN1_CH1IE_Pos
#define SCU_DMAIEN1_CH1IE_Pos
Definition: tle986x.h:8669
DMA_CH5_Int_En
INLINE void DMA_CH5_Int_En(void)
enables DMA Channel 5 Interrupt.
Definition: dma.h:808
sfr_access.h
SFR low level access library.
SCU_DMAIRC1CLR_CH6C_Pos
#define SCU_DMAIRC1CLR_CH6C_Pos
Definition: tle986x.h:8708
SCU_DMAIRC2CLR_SDADCC_Msk
#define SCU_DMAIRC2CLR_SDADCC_Msk
Definition: tle986x.h:8737
DMA_CH5_Int_Dis
INLINE void DMA_CH5_Int_Dis(void)
disables DMA Channel 5 Interrupt.
Definition: dma.h:831
SCU_DMAIRC1CLR_CH8C_Pos
#define SCU_DMAIRC1CLR_CH8C_Pos
Definition: tle986x.h:8704
SCU_DMAIRC1CLR_CH2C_Pos
#define SCU_DMAIRC1CLR_CH2C_Pos
Definition: tle986x.h:8716
INLINE
#define INLINE
Definition: types.h:134
Field_Mod8
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:346
DMA_Cycle_Type_Basic
Definition: dma.h:210
DMA_Init
void DMA_Init(void)
Initializes the DMA structure in RAM and SFRs according to the ConfigWizard settings.
SCU_DMAIEN1_CH8IE_Msk
#define SCU_DMAIEN1_CH8IE_Msk
Definition: tle986x.h:8656
SCU_DMAIEN1_CH5IE_Msk
#define SCU_DMAIEN1_CH5IE_Msk
Definition: tle986x.h:8662
SCU_DMAIRC2CLR_GPT12C_Msk
#define SCU_DMAIRC2CLR_GPT12C_Msk
Definition: tle986x.h:8739
SCU_DMAIRC2CLR_SSC2C_Msk
#define SCU_DMAIRC2CLR_SSC2C_Msk
Definition: tle986x.h:8741
DMA_CH2_Int_Dis
INLINE void DMA_CH2_Int_Dis(void)
disables DMA Channel 2 Interrupt.
Definition: dma.h:696
Field_Mod32
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
DMA_CH10_Int_En
INLINE void DMA_CH10_Int_En(void)
enables DMA Channel 10 Interrupt.
Definition: dma.h:1033
DMA_CH3_Int_Dis
INLINE void DMA_CH3_Int_Dis(void)
disables DMA Channel 3 Interrupt.
Definition: dma.h:741
DMA_CH0_Int_Dis
INLINE void DMA_CH0_Int_Dis(void)
disables DMA Channel 0 Interrupt.
Definition: dma.h:606
SCU_DMAIEN2_TRSEQ1RDYIE_Pos
#define SCU_DMAIEN2_TRSEQ1RDYIE_Pos
Definition: tle986x.h:8682
SCU_DMAIRC1CLR_CH3C_Pos
#define SCU_DMAIRC1CLR_CH3C_Pos
Definition: tle986x.h:8714
SCU_DMAIRC2CLR_SSC1C_Pos
#define SCU_DMAIRC2CLR_SSC1C_Pos
Definition: tle986x.h:8742
SCU_DMAIRC1CLR_CH5C_Pos
#define SCU_DMAIRC1CLR_CH5C_Pos
Definition: tle986x.h:8710
DMA_Dst_Inc
Definition: dma.h:200
DMA_Src_Dst_Inc
Definition: dma.h:201
SCU_DMAIRC2CLR_TRSEQ2DYC_Pos
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos
Definition: tle986x.h:8744
DMA_Software_Request_Set
INLINE void DMA_Software_Request_Set(uint32 mask_ch)
Set software request for DMA Channels.
Definition: dma.h:1253
DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk
Definition: tle986x.h:7791
DMA_CH1_Int_Clr
INLINE void DMA_CH1_Int_Clr(void)
clears DMA Channel 1 Interrupt flag.
Definition: dma.h:295
DMA_Channel_Enable_Set
INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
enables DMA Channels.
Definition: dma.h:1233
SCU_DMAIEN2_SDADCIE_Pos
#define SCU_DMAIEN2_SDADCIE_Pos
Definition: tle986x.h:8672
uint8
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos
Definition: tle986x.h:7790
DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk
Definition: tle986x.h:7809
TDMA_Transfer_Size
enum _TDMA_Transfer_Size TDMA_Transfer_Size
DMA_Reset_Channel
void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt)
Resets the primary structure in RAM for a given channel and rearms it.
DMA_CH12_Int_En
INLINE void DMA_CH12_Int_En(void)
enables DMA Channel 12 Interrupt.
Definition: dma.h:1123
SCU_DMAIEN2_SSCRXIE_Msk
#define SCU_DMAIEN2_SSCRXIE_Msk
Definition: tle986x.h:8677
SCU_DMAIEN2_SDADCIE_Msk
#define SCU_DMAIEN2_SDADCIE_Msk
Definition: tle986x.h:8673
DMA_CHx_Entry_Alt
INLINE uint32 DMA_CHx_Entry_Alt(uint8 DMA_Ch)
This function returns the address inside the alternate structure in RAM for a given DMA channel.
Definition: dma.h:1305
DMA_CH8_Int_Dis
INLINE void DMA_CH8_Int_Dis(void)
disables DMA Channel 8 Interrupt.
Definition: dma.h:966
DMA_CH6_Int_En
INLINE void DMA_CH6_Int_En(void)
enables DMA Channel 6 Interrupt.
Definition: dma.h:853
DMA_CH9_Int_Clr
INLINE void DMA_CH9_Int_Clr(void)
clears DMA Channel 9 Interrupt flag.
Definition: dma.h:471
DMA_Primary_Struct_Usage_Set
INLINE void DMA_Primary_Struct_Usage_Set(uint32 mask_ch)
selects the primary data structure for the corresponding DMA channel.
Definition: dma.h:1273
DMA_Src_Inc
Definition: dma.h:199
SCU_DMAIEN1_CH5IE_Pos
#define SCU_DMAIEN1_CH5IE_Pos
Definition: tle986x.h:8661
SCU_DMAIEN1_CH6IE_Pos
#define SCU_DMAIEN1_CH6IE_Pos
Definition: tle986x.h:8659
SCU_DMAIEN2_SSCRXIE_Pos
#define SCU_DMAIEN2_SSCRXIE_Pos
Definition: tle986x.h:8676
_TDMA_Increment_Size
_TDMA_Increment_Size
This enum lists the increment size options for the DMA.
Definition: dma.h:186
uint32
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
SCU_DMAIEN1_CH1IE_Msk
#define SCU_DMAIEN1_CH1IE_Msk
Definition: tle986x.h:8670
DMA_CH7_Int_Dis
INLINE void DMA_CH7_Int_Dis(void)
disables DMA Channel 7 Interrupt.
Definition: dma.h:921
DMA_CH12_Int_Clr
INLINE void DMA_CH12_Int_Clr(void)
clears DMA Channel 12 Interrupt flag.
Definition: dma.h:537
TControl
This structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:224
SCU_DMAIEN1_CH6IE_Msk
#define SCU_DMAIEN1_CH6IE_Msk
Definition: tle986x.h:8660
DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos
Definition: tle986x.h:7817
DMA_CH8_Int_En
INLINE void DMA_CH8_Int_En(void)
enables DMA Channel 8 Interrupt.
Definition: dma.h:943
DMA_Cycle_Type_PingPong
Definition: dma.h:212
DMA_Cycle_Type_MemSctGthPrim
Definition: dma.h:213
DMA_Inc_32bit
Definition: dma.h:190
SCU_DMAIEN1_CH8IE_Pos
#define SCU_DMAIEN1_CH8IE_Pos
Definition: tle986x.h:8655
DMA_CH3_Int_En
INLINE void DMA_CH3_Int_En(void)
enables DMA Channel 3 Interrupt.
Definition: dma.h:718
SCU_DMAIRC2CLR_TRSEQ1DYC_Msk
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk
Definition: tle986x.h:8747
SCU_DMAIEN1_CH4IE_Msk
#define SCU_DMAIEN1_CH4IE_Msk
Definition: tle986x.h:8664
DMA_Cycle_Type_MemSctGthAlt
Definition: dma.h:214
DMA_CH1_Int_En
INLINE void DMA_CH1_Int_En(void)
enables DMA Channel 1 Interrupt.
Definition: dma.h:628
DMA_8Bit_Transfer
Definition: dma.h:178
DMA_CH8_Int_Clr
INLINE void DMA_CH8_Int_Clr(void)
clears DMA Channel 8 Interrupt flag.
Definition: dma.h:449
DMA_CH1_Int_Dis
INLINE void DMA_CH1_Int_Dis(void)
disables DMA Channel 1 Interrupt.
Definition: dma.h:651
SCU_DMAIRC1CLR_CH4C_Pos
#define SCU_DMAIRC1CLR_CH4C_Pos
Definition: tle986x.h:8712
tle986x.h
CMSIS register HeaderFile.
SCU
#define SCU
Definition: tle986x.h:6004
SCU_DMAIRC1CLR_CH7C_Msk
#define SCU_DMAIRC1CLR_CH7C_Msk
Definition: tle986x.h:8707
DMA_Inc_8bit
Definition: dma.h:188
SCU_DMAIEN1_CH4IE_Pos
#define SCU_DMAIEN1_CH4IE_Pos
Definition: tle986x.h:8663
SCU_DMAIRC2CLR_SSC1C_Msk
#define SCU_DMAIRC2CLR_SSC1C_Msk
Definition: tle986x.h:8743
DMA_CH3_Int_Clr
INLINE void DMA_CH3_Int_Clr(void)
clears DMA Channel 3 Interrupt flag.
Definition: dma.h:339
DMA_32Bit_Transfer
Definition: dma.h:180
SCU_DMAIEN1_CH7IE_Pos
#define SCU_DMAIEN1_CH7IE_Pos
Definition: tle986x.h:8657
DMA_CH10_Int_Dis
INLINE void DMA_CH10_Int_Dis(void)
disables DMA Channel 10 Interrupt.
Definition: dma.h:1056
SCU_DMAIEN1_CH3IE_Pos
#define SCU_DMAIEN1_CH3IE_Pos
Definition: tle986x.h:8665
TDMA_Cycle_Types
enum _TDMA_Cycle_Types TDMA_Cycle_Types
DMA_CH0_Int_Clr
INLINE void DMA_CH0_Int_Clr(void)
clears DMA Channel 0 Interrupt flag.
Definition: dma.h:273
_TDMA_Transfer_Size
_TDMA_Transfer_Size
This enum lists the transfer size options for the DMA.
Definition: dma.h:176
DMA_CH4_Int_Clr
INLINE void DMA_CH4_Int_Clr(void)
clears DMA Channel 4 Interrupt flag.
Definition: dma.h:361
SCU_DMAIRC1CLR_CH2C_Msk
#define SCU_DMAIRC1CLR_CH2C_Msk
Definition: tle986x.h:8717
DMA_CH2_Int_Clr
INLINE void DMA_CH2_Int_Clr(void)
clears DMA Channel 2 Interrupt flag.
Definition: dma.h:317
SCU_DMAIRC1CLR_CH4C_Msk
#define SCU_DMAIRC1CLR_CH4C_Msk
Definition: tle986x.h:8713
DMA_Primary_Struct_Set
INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
points to the base address of the primary data structure.
Definition: dma.h:1213
SCU_DMAIRC2CLR_SDADCC_Pos
#define SCU_DMAIRC2CLR_SDADCC_Pos
Definition: tle986x.h:8736
DMA_No_Inc
Definition: dma.h:198
SCU_DMAIRC1CLR_CH1C_Pos
#define SCU_DMAIRC1CLR_CH1C_Pos
Definition: tle986x.h:8718
DMA_CH7_Int_Clr
INLINE void DMA_CH7_Int_Clr(void)
clears DMA Channel 7 Interrupt flag.
Definition: dma.h:427
TDMA_Entry
This structure lists the DMA transfer memory locations.
Definition: dma.h:245
SCU_DMAIEN1_CH2IE_Pos
#define SCU_DMAIEN1_CH2IE_Pos
Definition: tle986x.h:8667
DMA_Channel_PerSctGth_Set
void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
DMA_Cycle_Type_PerSctGthPrim
Definition: dma.h:215
SCU_DMAIEN2_TRSEQ1RDYIE_Msk
#define SCU_DMAIEN2_TRSEQ1RDYIE_Msk
Definition: tle986x.h:8683
DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos
Definition: tle986x.h:7808
TDMA_Increment_Mode
enum _TDMA_Increment_Mode TDMA_Increment_Mode
DMA_CH11_Int_Clr
INLINE void DMA_CH11_Int_Clr(void)
clears DMA Channel 11 Interrupt flag.
Definition: dma.h:515
SCU_DMAIRC1CLR_CH6C_Msk
#define SCU_DMAIRC1CLR_CH6C_Msk
Definition: tle986x.h:8709
Field_Wrt8
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:331
DMA_16Bit_Transfer
Definition: dma.h:179
TDMA_Increment_Size
enum _TDMA_Increment_Size TDMA_Increment_Size
DMA_CH0_Int_En
INLINE void DMA_CH0_Int_En(void)
enables DMA Channel 0 Interrupt.
Definition: dma.h:583
DMA_Setup_Channel
void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up the desired DMA channel in the primary structure in RAM.
SCU_DMAIEN1_CH3IE_Msk
#define SCU_DMAIEN1_CH3IE_Msk
Definition: tle986x.h:8666
DMA_CH7_Int_En
INLINE void DMA_CH7_Int_En(void)
enables DMA Channel 7 Interrupt.
Definition: dma.h:898
DMA_CH9_Int_Dis
INLINE void DMA_CH9_Int_Dis(void)
disables DMA Channel 9 Interrupt.
Definition: dma.h:1011
_TDMA_Increment_Mode
_TDMA_Increment_Mode
This enum lists the increment mode options for the DMA.
Definition: dma.h:196
DMA_Task_Set
TDMA_Entry * DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up a task to be used in the Scatter-Gather modes.
SCU_DMAIEN2_SSCTXIE_Msk
#define SCU_DMAIEN2_SSCTXIE_Msk
Definition: tle986x.h:8679
DMA_Cycle_Type_Invalid
Definition: dma.h:209
DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk
Definition: tle986x.h:7794
DMA
#define DMA
Definition: tle986x.h:5997