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TLE986x Device Family SDK
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97 #define NMI_WDT ((uint8)1u << 0u)
99 #define NMI_PLL ((uint8)1u << 1u)
101 #define NMI_NVM ((uint8)1u << 2u)
103 #define NMI_OT ((uint8)1u << 3u)
105 #define NMI_OWT ((uint8)1u << 4u)
107 #define NMI_MAP ((uint8)1u << 5u)
109 #define NMI_ECC ((uint8)1u << 6u)
111 #define NMI_SUP ((uint8)1u << 7u)
113 #define SCU_EXICON0_EXINT0_RE_Pos (0UL)
115 #define SCU_EXICON0_EXINT0_RE_Msk (0x01UL)
117 #define SCU_EXICON0_EXINT0_FE_Pos (1UL)
119 #define SCU_EXICON0_EXINT0_FE_Msk (0x02UL)
121 #define SCU_EXICON0_EXINT1_RE_Pos (2UL)
123 #define SCU_EXICON0_EXINT1_RE_Msk (0x04UL)
125 #define SCU_EXICON0_EXINT1_FE_Pos (3UL)
127 #define SCU_EXICON0_EXINT1_FE_Msk (0x08UL)
129 #define SCU_EXICON0_EXINT2_RE_Pos (4UL)
131 #define SCU_EXICON0_EXINT2_RE_Msk (0x10UL)
133 #define SCU_EXICON0_EXINT2_FE_Pos (5UL)
135 #define SCU_EXICON0_EXINT2_FE_Msk (0x20UL)
137 #define SCU_NMISR_Pos (0UL)
139 #define SCU_NMISR_Msk (0xFFUL)
141 #define SCU_NMICLR_Pos (0UL)
143 #define SCU_NMICLR_Msk (0xFFUL)
1582 #if (UC_SERIES == TLE987)
1600 INLINE void BEMF_Phase_U_Hi_Int_En(
void)
1623 INLINE void BEMF_Phase_U_Hi_Int_Dis(
void)
1645 INLINE void BEMF_Phase_U_Lo_Int_En(
void)
1668 INLINE void BEMF_Phase_U_Lo_Int_Dis(
void)
1690 INLINE void BEMF_Phase_V_Hi_Int_En(
void)
1713 INLINE void BEMF_Phase_V_Hi_Int_Dis(
void)
1735 INLINE void BEMF_Phase_V_Lo_Int_En(
void)
1758 INLINE void BEMF_Phase_V_Lo_Int_Dis(
void)
1780 INLINE void BEMF_Phase_W_Hi_Int_En(
void)
1803 INLINE void BEMF_Phase_W_Hi_Int_Dis(
void)
1825 INLINE void BEMF_Phase_W_Lo_Int_En(
void)
1848 INLINE void BEMF_Phase_W_Lo_Int_Dis(
void)
1870 INLINE void BEMF_Phase_U_Hi_Int_Clr(
void)
1892 INLINE void BEMF_Phase_U_Lo_Int_Clr(
void)
1914 INLINE void BEMF_Phase_V_Hi_Int_Clr(
void)
1936 INLINE void BEMF_Phase_V_Lo_Int_Clr(
void)
1958 INLINE void BEMF_Phase_W_Hi_Int_Clr(
void)
1980 INLINE void BEMF_Phase_W_Lo_Int_Clr(
void)
INLINE void ECC_NVM_DoubleBit_Int_Dis(void)
disables NVM Double Bit ECC Error Interrupt.
Definition: int.h:279
INLINE void EXINT2_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT2.
Definition: int.h:723
#define CPU_NVIC_ISER0_Int_GPT1_Pos
Definition: tle986x.h:7646
#define CPU_NVIC_ICER0_Int_CCU6SR1_Pos
Definition: tle986x.h:7534
#define CPU_NVIC_ISER0_Int_CCU6SR0_Msk
Definition: tle986x.h:7639
#define CPU_NVIC_ICER0_Int_GPT1_Msk
Definition: tle986x.h:7545
#define SCU_EXICON0_EXINT1_FE_Msk
External Interrupt 1 Falling Edge Bit Mask.
Definition: int.h:123
INLINE void EXINT1_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT1.
Definition: int.h:500
INLINE void ECC_RAM_DoubleBit_Int_En(void)
enables RAM Double Bit ECC Error Interrupt.
Definition: int.h:199
INLINE void EXINT1_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT1.
Definition: int.h:701
INLINE void EXINT1_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT1.
Definition: int.h:523
#define SCU_NMICLR_NMIOTC_Msk
Definition: tle986x.h:9071
#define CPU_NVIC_ISER0_Int_BDRV_Pos
Definition: tle986x.h:7618
#define SCU_EDCSCLR_RSBEC_Pos
Definition: tle986x.h:8779
#define SCU_NMICON_NMIPLL_Pos
Definition: tle986x.h:9091
INLINE void INT_Disable_Global_Int(void)
disables the global interrupt IEN0.EA
Definition: int.h:2065
INLINE void NVIC_Node6_Dis(void)
Disables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1408
#define CPU_NVIC_ICER0_Int_EXINT0_Msk
Definition: tle986x.h:7521
#define SCU_IRCON0CLR_EXINT1RC_Pos
Definition: tle986x.h:8883
General type declarations.
#define CPU_NVIC_ISER0_Int_CCU6SR2_Msk
Definition: tle986x.h:7635
#define CPU_NVIC_ISER0_Int_UART2_Pos
Definition: tle986x.h:7624
#define SCU_EDCCON_NVMIE_Msk
Definition: tle986x.h:8775
#define SCU_NMICON_NMINVM_Pos
Definition: tle986x.h:9089
#define CPU_NVIC_ICER0_Int_UART1_Msk
Definition: tle986x.h:7525
#define CPU_NVIC_ICER0_Int_UART1_Pos
Definition: tle986x.h:7524
#define SCU_NMICON_NMIOWD_Msk
Definition: tle986x.h:9086
#define SCU_NMICON_NMISUP_Msk
Definition: tle986x.h:9080
#define SCU_NMICLR_NMINVMC_Msk
Definition: tle986x.h:9073
INLINE void NVIC_Node0_En(void)
Enables the NVIC node 0 (Int_GPT1)
Definition: int.h:1291
INLINE void Global_Int_En(void)
enables Global Interrupt (Pending interrupt requests are not blocked from the core).
Definition: int.h:156
INLINE void NVIC_Node6_En(void)
Enables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1399
#define CPU_NVIC_ICER0_Int_CCU6SR3_Pos
Definition: tle986x.h:7530
#define CPU_NVIC_ISER0_Int_EXINT0_Pos
Definition: tle986x.h:7622
#define SCU_NMISR_Msk
NMI Status Read Bit Mask.
Definition: int.h:135
#define CPU_NVIC_ISER0_Int_UART1_Msk
Definition: tle986x.h:7627
#define CPU_NVIC_ICER0_Int_DMA_Msk
Definition: tle986x.h:7515
#define SCU_NMISR_Pos
NMI Status Read Bit Position.
Definition: int.h:133
#define CPU_NVIC_ISER0_Int_EXINT1_Pos
Definition: tle986x.h:7620
INLINE void ECC_RAM_SingleBit_Int_Clr(void)
clears RAM Single Bit Error Status.
Definition: int.h:299
#define CPU_NVIC_ISER0_Int_DMA_Pos
Definition: tle986x.h:7616
#define CPU_NVIC_ISER0_Int_ADC2_Msk
Definition: tle986x.h:7643
#define CPU_NVIC_ISER0_Int_SSC1_Msk
Definition: tle986x.h:7631
#define CPU_NVIC_ICER0_Int_ADC1_Msk
Definition: tle986x.h:7539
#define SCU_NMICLR_NMIECCC_Pos
Definition: tle986x.h:9064
INLINE void NVIC_Node2_En(void)
Enables the NVIC node 2 (Int_ADC2)
Definition: int.h:1327
INLINE void NVIC_Node4_En(void)
Enables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1363
#define SCU_NMICLR_NMIPLLC_Pos
Definition: tle986x.h:9074
#define SCU_NMICON_NMIECC_Msk
Definition: tle986x.h:9082
#define SCU_IRCON0CLR_EXINT0RC_Pos
Definition: tle986x.h:8887
SFR low level access library.
#define CPU_NVIC_ICER0_Int_EXINT0_Pos
Definition: tle986x.h:7520
#define SCU_EDCSCLR_RDBEC_Pos
Definition: tle986x.h:8783
#define SCUPM
Definition: tle986x.h:6005
#define SCU_EDCSCLR_NVMDBEC_Pos
Definition: tle986x.h:8781
#define CPU_NVIC_ISER0_Int_CCU6SR1_Pos
Definition: tle986x.h:7636
#define SCU_EXICON0_EXINT2_RE_Msk
External Interrupt 2 Rising Edge Bit Mask.
Definition: int.h:127
#define SCU_NMICLR_NMIOWDC_Pos
Definition: tle986x.h:9068
#define INLINE
Definition: types.h:134
#define SCU_EXICON0_EXINT0_FE_Pos
External Interrupt 0 Falling Edge Bit Position.
Definition: int.h:113
#define SCU_NMICLR_NMIMAPC_Pos
Definition: tle986x.h:9066
#define SCU_NMICON_NMIMAP_Pos
Definition: tle986x.h:9083
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:346
INLINE void NMI_WDT_Int_Dis(void)
disables Watchdog Timer NMI.
Definition: int.h:790
#define CPU_NVIC_ISER0_Int_CCU6SR1_Msk
Definition: tle986x.h:7637
#define CPU_NVIC_ISER0_Int_SSC2_Msk
Definition: tle986x.h:7629
INLINE void NMI_OT_Int_Clr(void)
clears NMI OT Flag.
Definition: int.h:1196
#define CPU_NVIC_ISER0_Int_ADC2_Pos
Definition: tle986x.h:7642
INLINE void INT_Enable_Global_Int(void)
enables the global interrupt IEN0.EA
Definition: int.h:2048
#define SCU_NMICLR_Pos
NMI Clear Bit Position.
Definition: int.h:137
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
#define SCU_NMICON_NMIPLL_Msk
Definition: tle986x.h:9092
INLINE void NMI_PLL_Int_Dis(void)
disables PLL Loss of Lock NMI.
Definition: int.h:835
#define CPU_NVIC_ISER0_Int_GPT1_Msk
Definition: tle986x.h:7647
INLINE void NVIC_Node8_En(void)
Enables the NVIC node 8 (Int_SSC1)
Definition: int.h:1435
#define SCU_EXICON0_EXINT0_RE_Msk
External Interrupt 0 Rising Edge Bit Mask.
Definition: int.h:111
INLINE void INT_Clr_NMI_Status(uint8 Flags)
Clears the NMI Status flags.
Definition: int.h:2031
#define SCU_IRCON0CLR_EXINT0RC_Msk
Definition: tle986x.h:8888
#define CPU_NVIC_ICER0_Int_ADC2_Msk
Definition: tle986x.h:7541
#define SCU_EXICON0_EXINT2_RE_Pos
External Interrupt 2 Rising Edge Bit Position.
Definition: int.h:125
#define CPU_NVIC_ICER0_Int_GPT1_Pos
Definition: tle986x.h:7544
#define CPU_NVIC_ISER0_Int_CCU6SR2_Pos
Definition: tle986x.h:7634
#define SCU_IRCON0CLR_EXINT2FC_Msk
Definition: tle986x.h:8878
#define CPU_NVIC_ICER0_Int_DMA_Pos
Definition: tle986x.h:7514
INLINE void EXINT1_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT1.
Definition: int.h:455
#define SCU_EXICON0_EXINT1_RE_Pos
External Interrupt 1 Rising Edge Bit Position.
Definition: int.h:117
#define CPU_NVIC_ICER0_Int_UART2_Msk
Definition: tle986x.h:7523
#define SCU_EDCSCLR_RSBEC_Msk
Definition: tle986x.h:8780
#define SCU_NMICON_NMIOT_Pos
Definition: tle986x.h:9087
INLINE void NMI_SUP_Int_En(void)
enables Supply Prewarning NMI.
Definition: int.h:999
INLINE void NVIC_Node7_Dis(void)
Disables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1426
INLINE void NMI_PLL_Int_Clr(void)
clears PLL Loss of Lock NMI Flag.
Definition: int.h:1153
#define CPU_NVIC_ICER0_Int_EXINT1_Msk
Definition: tle986x.h:7519
INLINE void NMI_ECC_Int_Clr(void)
clears ECC Error NMI Flag.
Definition: int.h:1261
#define SCU_EDCSCLR_NVMDBEC_Msk
Definition: tle986x.h:8782
INLINE void NVIC_Node10_Dis(void)
Disables the NVIC node 10 (Int_UART1)
Definition: int.h:1480
#define CPU_NVIC_ISER0_Int_EXINT0_Msk
Definition: tle986x.h:7623
#define SCU_EXICON0_EXINT2_FE_Msk
External Interrupt 2 Falling Edge Bit Mask.
Definition: int.h:131
Device specific memory layout defines.
#define SCU_EXICON0_EXINT1_FE_Pos
External Interrupt 1 Falling Edge Bit Position.
Definition: int.h:121
INLINE void EXINT2_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT2.
Definition: int.h:745
#define SCU_NMICLR_NMISUPC_Msk
Definition: tle986x.h:9063
#define SCU_IEN0_EA_Msk
Definition: tle986x.h:8854
#define SCU_NMICON_NMIOT_Msk
Definition: tle986x.h:9088
#define CPU_NVIC_ICER0_Int_BDRV_Msk
Definition: tle986x.h:7517
#define SCU_IEN0_EA_Pos
Definition: tle986x.h:8853
#define SCU_NMICON_NMIECC_Pos
Definition: tle986x.h:9081
INLINE void NMI_NVM_Int_Clr(void)
clears NVM Operation Complete NMI flag.
Definition: int.h:1175
INLINE void NMI_NVM_Int_En(void)
enables NVM Operation Complete NMI.
Definition: int.h:857
INLINE void EXINT2_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT2.
Definition: int.h:613
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
#define CPU_NVIC_ISER0_Int_UART1_Pos
Definition: tle986x.h:7626
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:341
INLINE void NVIC_Node15_Dis(void)
Disables the NVIC node 15 (Int_DMA)
Definition: int.h:1572
#define SCU_IRCON0CLR_EXINT1FC_Pos
Definition: tle986x.h:8881
#define SCU_NMICON_NMIWDT_Pos
Definition: tle986x.h:9093
#define SCU_EDCCON_RIE_Pos
Definition: tle986x.h:8776
void INT_Init(void)
Initializes the Interrupt module.
INLINE void NVIC_Node11_En(void)
Enables the NVIC node 11 (Int_UART2)
Definition: int.h:1489
#define SCU_NMICLR_NMINVMC_Pos
Definition: tle986x.h:9072
#define CPU_NVIC_ICER0_Int_SSC2_Msk
Definition: tle986x.h:7527
INLINE uint8 u8_Field_Rd8(const volatile uint8 *reg, uint8 pos, uint8 msk)
This function reads a 8-bit field of a 8-bit register.
Definition: sfr_access.h:406
INLINE void NMI_SUP_Int_Clr(void)
clears Supply Prewarning NMI Flag.
Definition: int.h:1282
#define CPU_NVIC_ICER0_Int_CCU6SR2_Pos
Definition: tle986x.h:7532
#define CPU_NVIC_ICER0_Int_BDRV_Pos
Definition: tle986x.h:7516
INLINE void NMI_WDT_Int_En(void)
enables Watchdog Timer NMI.
Definition: int.h:767
#define SCU_NMICON_NMINVM_Msk
Definition: tle986x.h:9090
INLINE void EXINT0_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT0.
Definition: int.h:388
#define SCU_NMICLR_NMIWDTC_Pos
Definition: tle986x.h:9076
#define SCU_EXICON0_EXINT0_FE_Msk
External Interrupt 0 Falling Edge Bit Mask.
Definition: int.h:115
#define CPU_NVIC_ICER0_Int_CCU6SR0_Msk
Definition: tle986x.h:7537
INLINE void NMI_OT_Int_En(void)
enables OT NMI.
Definition: int.h:1087
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
INLINE void NMI_OWD_Int_En(void)
enables Oscillator Watchdog NMI.
Definition: int.h:1043
#define CPU_NVIC_ICER0_Int_ADC2_Pos
Definition: tle986x.h:7540
INLINE void NVIC_Node12_En(void)
Enables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1509
#define CPU_NVIC_ISER0_Int_ADC1_Pos
Definition: tle986x.h:7640
INLINE void EXINT0_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT0.
Definition: int.h:365
#define SCU_NMICLR_NMIPLLC_Msk
Definition: tle986x.h:9075
INLINE void NVIC_Node14_En(void)
Enables the NVIC node 14 (Int_BDRV)
Definition: int.h:1545
INLINE void NMI_ECC_Int_Dis(void)
disables ECC Error NMI.
Definition: int.h:933
#define SCU_NMICON_NMIOWD_Pos
Definition: tle986x.h:9085
#define SCU_NMICLR_NMIWDTC_Msk
Definition: tle986x.h:9077
#define SCU_NMICLR_NMIOWDC_Msk
Definition: tle986x.h:9069
#define SCU_NMICON_NMIWDT_Msk
Definition: tle986x.h:9094
INLINE uint8 INT_Get_NMI_Status(void)
Reads out the NMI Status.
Definition: int.h:2012
#define SCU_EDCSCLR_RDBEC_Msk
Definition: tle986x.h:8784
#define CPU_NVIC_ICER0_Int_CCU6SR2_Msk
Definition: tle986x.h:7533
#define CPU_NVIC_ICER0_Int_CCU6SR3_Msk
Definition: tle986x.h:7531
INLINE void NVIC_Node5_En(void)
Enables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1381
INLINE void EXINT1_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT1.
Definition: int.h:679
INLINE void EXINT0_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT0.
Definition: int.h:635
INLINE void Global_Int_Dis(void)
disables Global Interrupt (All pending interrupt requests,except NMI, are blocked from the core).
Definition: int.h:173
#define SCU_NMICLR_NMIMAPC_Msk
Definition: tle986x.h:9067
#define SCU_NMICON_NMIMAP_Msk
Definition: tle986x.h:9084
#define CPU_NVIC_ISER0_Int_BDRV_Msk
Definition: tle986x.h:7619
INLINE void NVIC_Node5_Dis(void)
Disables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1390
#define CPU_NVIC_ICER0_Int_ADC1_Pos
Definition: tle986x.h:7538
#define SCU_IRCON0CLR_EXINT1RC_Msk
Definition: tle986x.h:8884
#define SCU_IRCON0CLR_EXINT1FC_Msk
Definition: tle986x.h:8882
INLINE void NVIC_Node1_Dis(void)
Disables the NVIC node 1 (Int_GPT2)
Definition: int.h:1318
INLINE void EXINT1_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT1.
Definition: int.h:478
INLINE void EXINT0_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT0.
Definition: int.h:657
#define CPU_NVIC_ISER0_Int_ADC1_Msk
Definition: tle986x.h:7641
#define CPU
Definition: tle986x.h:5996
INLINE void NMI_ECC_Int_En(void)
enables ECC Error NMI.
Definition: int.h:906
CMSIS register HeaderFile.
#define SCU
Definition: tle986x.h:6004
#define SCU_NMICLR_NMIOTC_Pos
Definition: tle986x.h:9070
#define CPU_NVIC_ICER0_Int_GPT2_Pos
Definition: tle986x.h:7542
#define CPU_NVIC_ISER0_Int_GPT2_Msk
Definition: tle986x.h:7645
#define SCU_NMICLR_NMIECCC_Msk
Definition: tle986x.h:9065
#define CPU_NVIC_ICER0_Int_CCU6SR0_Pos
Definition: tle986x.h:7536
#define SCU_EXICON0_EXINT2_FE_Pos
External Interrupt 2 Falling Edge Bit Position.
Definition: int.h:129
INLINE void ECC_NVM_DoubleBit_Int_En(void)
enables NVM Double Bit ECC Error Interrupt.
Definition: int.h:252
INLINE void NMI_NVM_Int_Dis(void)
disables NVM Operation Complete NMI.
Definition: int.h:880
INLINE void NVIC_Node3_Dis(void)
Disables the NVIC node 3 (Int_ADC1)
Definition: int.h:1354
#define SCU_IRCON0CLR_EXINT2RC_Msk
Definition: tle986x.h:8880
#define SCU_IRCON0CLR_EXINT2RC_Pos
Definition: tle986x.h:8879
#define SCU_NMICON_NMISUP_Pos
Definition: tle986x.h:9079
#define CPU_NVIC_ICER0_Int_CCU6SR1_Msk
Definition: tle986x.h:7535
#define CPU_NVIC_ISER0_Int_UART2_Msk
Definition: tle986x.h:7625
INLINE void NVIC_Node12_Dis(void)
Disables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1518
#define CPU_NVIC_ISER0_Int_EXINT1_Msk
Definition: tle986x.h:7621
#define CPU_NVIC_ISER0_Int_SSC2_Pos
Definition: tle986x.h:7628
INLINE void NVIC_Node13_Dis(void)
Disables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1536
INLINE void EXINT0_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT0.
Definition: int.h:433
#define CPU_NVIC_ICER0_Int_UART2_Pos
Definition: tle986x.h:7522
INLINE void NVIC_Node9_En(void)
Enables the NVIC node 9 (Int_SSC2)
Definition: int.h:1453
INLINE void NMI_SUP_Int_Dis(void)
disables Supply Prewarning NMI.
Definition: int.h:1021
#define CPU_NVIC_ISER0_Int_CCU6SR3_Msk
Definition: tle986x.h:7633
INLINE void ECC_RAM_DoubleBit_Int_Clr(void)
clears RAM Double Bit ECC Error Interrupt flag.
Definition: int.h:321
INLINE void NMI_WDT_Int_Clr(void)
clears Watchdog Timer NMI Flag.
Definition: int.h:1131
#define SCU_EXICON0_EXINT0_RE_Pos
External Interrupt 0 Rising Edge Bit Position.
Definition: int.h:109
#define CPU_NVIC_ICER0_Int_GPT2_Msk
Definition: tle986x.h:7543
INLINE void NMI_MAP_Int_Dis(void)
disables NVM Map Error NMI.
Definition: int.h:978
INLINE void NMI_OWD_Int_Dis(void)
disables Oscillator Watchdog NMI.
Definition: int.h:1066
INLINE void NVIC_Node1_En(void)
Enables the NVIC node 1 (Int_GPT2)
Definition: int.h:1309
#define CPU_NVIC_ISER0_Int_GPT2_Pos
Definition: tle986x.h:7644
INLINE void ECC_NVM_DoubleBit_Int_Clr(void)
clears NVM Double Bit ECC Error Interrupt flag.
Definition: int.h:343
INLINE void NVIC_Node8_Dis(void)
Disables the NVIC node 8 (Int_SSC1)
Definition: int.h:1444
#define SCU_EDCCON_NVMIE_Pos
Definition: tle986x.h:8774
INLINE void NVIC_Node13_En(void)
Enables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1527
INLINE void NVIC_Node0_Dis(void)
Disables the NVIC node 0 (Int_GPT1)
Definition: int.h:1300
INLINE void NVIC_Node3_En(void)
Enables the NVIC node 3 (Int_ADC1)
Definition: int.h:1345
#define SCU_IRCON0CLR_EXINT0FC_Pos
Definition: tle986x.h:8885
INLINE void EXINT2_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT2.
Definition: int.h:545
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:331
INLINE void NMI_PLL_Int_En(void)
enables PLL Loss of Lock NMI.
Definition: int.h:812
INLINE void NVIC_Node10_En(void)
Enables the NVIC node 10 (Int_UART1)
Definition: int.h:1471
INLINE void NMI_MAP_Int_Clr(void)
clears NVM Map Error NMI Flag.
Definition: int.h:1240
INLINE void NMI_OWD_Int_Clr(void)
clears Oscillator Watchdog NMI Flag.
Definition: int.h:1218
INLINE void NVIC_Node11_Dis(void)
Disables the NVIC node 11 (Int_UART2)
Definition: int.h:1499
#define CPU_NVIC_ISER0_Int_CCU6SR0_Pos
Definition: tle986x.h:7638
#define SCU_NMICLR_Msk
NMI Clear Bit Mask.
Definition: int.h:139
INLINE void EXINT2_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT2.
Definition: int.h:568
#define SCU_EXICON0_EXINT1_RE_Msk
External Interrupt 1 Rising Edge Bit Mask.
Definition: int.h:119
#define CPU_NVIC_ICER0_Int_SSC2_Pos
Definition: tle986x.h:7526
INLINE void NVIC_Node4_Dis(void)
Disables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1372
INLINE void EXINT2_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT2.
Definition: int.h:590
INLINE void NVIC_Node7_En(void)
Enables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1417
INLINE void ECC_RAM_DoubleBit_Int_Dis(void)
disables RAM Double Bit ECC Error Interrupt.
Definition: int.h:226
#define CPU_NVIC_ICER0_Int_SSC1_Pos
Definition: tle986x.h:7528
INLINE void EXINT0_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT0.
Definition: int.h:410
#define SCU_IRCON0CLR_EXINT2FC_Pos
Definition: tle986x.h:8877
INLINE void NVIC_Node9_Dis(void)
Disables the NVIC node 9 (Int_SSC2)
Definition: int.h:1462
#define CPU_NVIC_ICER0_Int_EXINT1_Pos
Definition: tle986x.h:7518
#define CPU_NVIC_ISER0_Int_SSC1_Pos
Definition: tle986x.h:7630
INLINE void NMI_MAP_Int_En(void)
enables NVM Map Error NMI.
Definition: int.h:955
INLINE void NVIC_Node15_En(void)
Enables the NVIC node 15 (Int_DMA)
Definition: int.h:1563
#define SCU_IRCON0CLR_EXINT0FC_Msk
Definition: tle986x.h:8886
INLINE void NMI_OT_Int_Dis(void)
disables OT NMI.
Definition: int.h:1109
#define SCU_NMICLR_NMISUPC_Pos
Definition: tle986x.h:9062
#define CPU_NVIC_ICER0_Int_SSC1_Msk
Definition: tle986x.h:7529
INLINE void NVIC_Node14_Dis(void)
Disables the NVIC node 14 (Int_BDRV)
Definition: int.h:1554
#define CPU_NVIC_ISER0_Int_CCU6SR3_Pos
Definition: tle986x.h:7632
INLINE void NVIC_Node2_Dis(void)
Disables the NVIC node 2 (Int_ADC2)
Definition: int.h:1336
#define SCU_EDCCON_RIE_Msk
Definition: tle986x.h:8777
#define CPU_NVIC_ISER0_Int_DMA_Msk
Definition: tle986x.h:7617