TLE986x Device Family SDK
Data Fields
ADC2_Type Struct Reference

Detailed Description

ADC2 Module (ADC2)

#include <tle986x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 16
 
      __IOM uint32_t   VBAT_RANGE: 1
 
      __IOM uint32_t   VS_RANGE: 1
 
   }   bit
 
CTRL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   SQ_FB: 4
 
      __IM   uint32_t: 4
 
      __IM uint32_t   SQ_STOP: 1
 
      __IM uint32_t   EIM_ACTIVE: 1
 
      __IM uint32_t   ESM_ACTIVE: 1
 
      __IM uint32_t   SQx: 4
 
      __IM uint32_t   CHx: 5
 
   }   bit
 
SQ_FB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHx: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   REP: 3
 
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   SEL: 1
 
   }   bit
 
CHx_EIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ESM_0: 6
 
      __IOM uint32_t   ESM_1: 4
 
      __IOM uint32_t   SEL: 1
 
      __IM   uint32_t: 5
 
      __IOM uint32_t   EN: 1
 
      __IM uint32_t   STS: 1
 
   }   bit
 
CHx_ESM
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALIB_EN: 6
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MCM_PD_N: 1
 
      __IOM uint32_t   TS_SD_SEL_CONF: 1
 
      __IOM uint32_t   TSENSE_SD_SEL: 1
 
      __IM   uint32_t: 4
 
      __IM uint32_t   MCM_RDY: 1
 
      __IOM uint32_t   SAMPLE_TIME_int: 4
 
      __IOM uint32_t   SEL_TS_COUNT: 4
 
   }   bit
 
CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FILT_OUT_SEL_5_0: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   FILT_OUT_SEL_9_6: 4
 
   }   bit
 
CTRL4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ1: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ2: 6
 
      __IOM uint32_t   SQ3: 6
 
      __IOM uint32_t   SQ4: 6
 
   }   bit
 
SQ1_4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ5: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ6: 6
 
      __IOM uint32_t   SQ7: 6
 
      __IOM uint32_t   SQ8: 6
 
   }   bit
 
SQ5_8
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ9: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ10: 6
 
   }   bit
 
SQ9_10
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   SQ1_int: 4
 
      __IM uint32_t   SQ2_int: 4
 
      __IM uint32_t   SQ3_int: 4
 
      __IM uint32_t   SQ4_int: 4
 
      __IM uint32_t   SQ5_int: 4
 
      __IM uint32_t   SQ6_int: 4
 
      __IM uint32_t   SQ7_int: 4
 
      __IM uint32_t   SQ8_int: 4
 
   }   bit
 
SQ1_8_int
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   SQ9_int: 4
 
      __IM uint32_t   SQ10_int: 4
 
   }   bit
 
SQ9_10_int
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH0: 8
 
      __IOM uint32_t   GAIN_CH0: 8
 
      __IOM uint32_t   OFFS_CH1: 8
 
      __IOM uint32_t   GAIN_CH1: 8
 
   }   bit
 
CAL_CH0_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH2: 8
 
      __IOM uint32_t   GAIN_CH2: 8
 
      __IOM uint32_t   OFFS_CH3: 8
 
      __IOM uint32_t   GAIN_CH3: 8
 
   }   bit
 
CAL_CH2_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH4: 8
 
      __IOM uint32_t   GAIN_CH4: 8
 
      __IOM uint32_t   OFFS_CH5: 8
 
      __IOM uint32_t   GAIN_CH5: 8
 
   }   bit
 
CAL_CH4_5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OFFS_CH6: 8
 
      __IM uint32_t   GAIN_CH6: 8
 
      __IM uint32_t   OFFS_CH7: 8
 
      __IM uint32_t   GAIN_CH7: 8
 
   }   bit
 
CAL_CH6_7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OFFS_CH8: 8
 
      __IM uint32_t   GAIN_CH8: 8
 
      __IM uint32_t   OFFS_CH9: 8
 
      __IM uint32_t   GAIN_CH9: 8
 
   }   bit
 
CAL_CH8_9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH0: 2
 
      __IOM uint32_t   CH1: 2
 
      __IOM uint32_t   CH2: 2
 
      __IOM uint32_t   CH3: 2
 
      __IOM uint32_t   CH4: 2
 
      __IOM uint32_t   CH5: 2
 
   }   bit
 
FILTCOEFF0_5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   CH6: 2
 
      __IM uint32_t   CH7: 2
 
      __IM uint32_t   CH8: 2
 
      __IM uint32_t   CH9: 2
 
   }   bit
 
FILTCOEFF6_9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH0: 10
 
   }   bit
 
FILT_OUT0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH1: 10
 
   }   bit
 
FILT_OUT1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH2: 10
 
   }   bit
 
FILT_OUT2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH3: 10
 
   }   bit
 
FILT_OUT3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH4: 10
 
   }   bit
 
FILT_OUT4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH5: 10
 
   }   bit
 
FILT_OUT5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH6: 10
 
   }   bit
 
FILT_OUT6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH7: 10
 
   }   bit
 
FILT_OUT7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH8: 10
 
   }   bit
 
FILT_OUT8
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH9: 10
 
   }   bit
 
FILT_OUT9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Ch0_EN: 1
 
      __IOM uint32_t   Ch1_EN: 1
 
      __IOM uint32_t   Ch2_EN: 1
 
      __IOM uint32_t   Ch3_EN: 1
 
      __IOM uint32_t   Ch4_EN: 1
 
      __IOM uint32_t   Ch5_EN: 1
 
   }   bit
 
FILT_UP_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Ch0_EN: 1
 
      __IOM uint32_t   Ch1_EN: 1
 
      __IOM uint32_t   Ch2_EN: 1
 
      __IOM uint32_t   Ch3_EN: 1
 
      __IOM uint32_t   Ch4_EN: 1
 
      __IOM uint32_t   Ch5_EN: 1
 
   }   bit
 
FILT_LO_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH0: 8
 
      __IOM uint32_t   CH1: 8
 
      __IOM uint32_t   CH2: 8
 
      __IOM uint32_t   CH3: 8
 
   }   bit
 
TH0_3_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH4: 8
 
      __IOM uint32_t   CH5: 8
 
   }   bit
 
TH4_5_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH6: 8
 
      __IM uint32_t   CH7: 8
 
      __IOM uint32_t   CH8: 8
 
      __IOM uint32_t   CH9: 8
 
   }   bit
 
TH6_9_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH0: 8
 
      __IOM uint32_t   CH1: 8
 
      __IOM uint32_t   CH2: 8
 
      __IOM uint32_t   CH3: 8
 
   }   bit
 
TH0_3_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH4: 8
 
      __IOM uint32_t   CH5: 8
 
   }   bit
 
TH4_5_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   CH6: 8
 
      __IM uint32_t   CH7: 8
 
      __IM uint32_t   CH8: 8
 
      __IM uint32_t   CH9: 8
 
   }   bit
 
TH6_9_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_CH0: 3
 
      __IOM uint32_t   HYST_LO_CH0: 2
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CNT_LO_CH1: 3
 
      __IOM uint32_t   HYST_LO_CH1: 2
 
      __IOM uint32_t   CNT_LO_CH2: 3
 
      __IOM uint32_t   HYST_LO_CH2: 2
 
      __IOM uint32_t   CNT_LO_CH3: 3
 
      __IOM uint32_t   HYST_LO_CH3: 2
 
   }   bit
 
CNT0_3_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_CH4: 3
 
      __IOM uint32_t   HYST_LO_CH4: 2
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CNT_LO_CH5: 3
 
      __IOM uint32_t   HYST_LO_CH5: 2
 
   }   bit
 
CNT4_5_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   CNT_LO_CH6: 3
 
      __IM uint32_t   HYST_LO_CH6: 2
 
      __IM   uint32_t: 3
 
      __IM uint32_t   CNT_LO_CH7: 3
 
      __IM uint32_t   HYST_LO_CH7: 2
 
      __IM uint32_t   CNT_LO_CH8: 3
 
      __IM uint32_t   HYST_LO_CH8: 2
 
      __IM uint32_t   CNT_LO_CH9: 3
 
      __IM uint32_t   HYST_LO_CH9: 2
 
   }   bit
 
CNT6_9_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_CH0: 3
 
      __IOM uint32_t   HYST_UP_CH0: 2
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CNT_UP_CH1: 3
 
      __IOM uint32_t   HYST_UP_CH1: 2
 
      __IOM uint32_t   CNT_UP_CH2: 3
 
      __IOM uint32_t   HYST_UP_CH2: 2
 
      __IOM uint32_t   CNT_UP_CH3: 3
 
      __IOM uint32_t   HYST_UP_CH3: 2
 
   }   bit
 
CNT0_3_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_CH4: 3
 
      __IOM uint32_t   HYST_UP_CH4: 2
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CNT_UP_CH5: 3
 
      __IOM uint32_t   HYST_UP_CH5: 2
 
   }   bit
 
CNT4_5_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   CNT_UP_CH6: 3
 
      __IM uint32_t   HYST_UP_CH6: 2
 
      __IM   uint32_t: 3
 
      __IM uint32_t   CNT_UP_CH7: 3
 
      __IM uint32_t   HYST_UP_CH7: 2
 
      __IM uint32_t   CNT_UP_CH8: 3
 
      __IM uint32_t   HYST_UP_CH8: 2
 
      __IM uint32_t   CNT_UP_CH9: 3
 
      __IM uint32_t   HYST_UP_CH9: 2
 
   }   bit
 
CNT6_9_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Ch0: 2
 
      __IOM uint32_t   Ch1: 2
 
      __IOM uint32_t   Ch2: 2
 
      __IOM uint32_t   Ch3: 2
 
      __IOM uint32_t   Ch4: 2
 
      __IOM uint32_t   Ch5: 2
 
   }   bit
 
MMODE0_5
 
__IM uint32_t RESERVED1 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IM uint32_t   READY: 1
 
   }   bit
 
HV_STS
 

Field Documentation

◆ bit [1/45]

struct { ... } bit

◆ bit [2/45]

struct { ... } bit

◆ bit [3/45]

struct { ... } bit

◆ bit [4/45]

struct { ... } bit

◆ bit [5/45]

struct { ... } bit

◆ bit [6/45]

struct { ... } bit

◆ bit [7/45]

struct { ... } bit

◆ bit [8/45]

struct { ... } bit

◆ bit [9/45]

struct { ... } bit

◆ bit [10/45]

struct { ... } bit

◆ bit [11/45]

struct { ... } bit

◆ bit [12/45]

struct { ... } bit

◆ bit [13/45]

struct { ... } bit

◆ bit [14/45]

struct { ... } bit

◆ bit [15/45]

struct { ... } bit

◆ bit [16/45]

struct { ... } bit

◆ bit [17/45]

struct { ... } bit

◆ bit [18/45]

struct { ... } bit

◆ bit [19/45]

struct { ... } bit

◆ bit [20/45]

struct { ... } bit

◆ bit [21/45]

struct { ... } bit

◆ bit [22/45]

struct { ... } bit

◆ bit [23/45]

struct { ... } bit

◆ bit [24/45]

struct { ... } bit

◆ bit [25/45]

struct { ... } bit

◆ bit [26/45]

struct { ... } bit

◆ bit [27/45]

struct { ... } bit

◆ bit [28/45]

struct { ... } bit

◆ bit [29/45]

struct { ... } bit

◆ bit [30/45]

struct { ... } bit

◆ bit [31/45]

struct { ... } bit

◆ bit [32/45]

struct { ... } bit

◆ bit [33/45]

struct { ... } bit

◆ bit [34/45]

struct { ... } bit

◆ bit [35/45]

struct { ... } bit

◆ bit [36/45]

struct { ... } bit

◆ bit [37/45]

struct { ... } bit

◆ bit [38/45]

struct { ... } bit

◆ bit [39/45]

struct { ... } bit

◆ bit [40/45]

struct { ... } bit

◆ bit [41/45]

struct { ... } bit

◆ bit [42/45]

struct { ... } bit

◆ bit [43/45]

struct { ... } bit

◆ bit [44/45]

struct { ... } bit

◆ bit [45/45]

struct { ... } bit

◆ CAL_CH0_1

union { ... } CAL_CH0_1

◆ CAL_CH2_3

union { ... } CAL_CH2_3

◆ CAL_CH4_5

union { ... } CAL_CH4_5

◆ CAL_CH6_7

union { ... } CAL_CH6_7

◆ CAL_CH8_9

union { ... } CAL_CH8_9

◆ CALIB_EN

__IOM uint32_t CALIB_EN

[5..0] Calibration Enable for Channels 0 to 5

◆ CH0

[1..0] Filter Coefficients ADC channel 0

[7..0] Channel 0 lower trigger level

[7..0] Channel 0 upper trigger level

◆ Ch0

[1..0] Measurement mode ch 0

◆ Ch0_EN

__IOM uint32_t Ch0_EN

[0..0] Upper threshold IIR filter enable ch 0

[0..0] Lower threshold IIR filter enable ch 0

◆ CH1

[3..2] Filter Coefficients ADC channel 1

[15..8] Channel 1 lower trigger level

[15..8] Channel 1 upper trigger level

◆ Ch1

[3..2] Measurement mode ch 1

◆ Ch1_EN

__IOM uint32_t Ch1_EN

[1..1] Upper threshold IIR filter enable ch 1

[1..1] Lower threshold IIR filter enable ch 1

◆ CH2

[5..4] Filter Coefficients ADC channel 2

[23..16] Channel 2 lower trigger level

[23..16] Channel 2 upper trigger level

◆ Ch2

[5..4] Measurement mode ch 2

◆ Ch2_EN

__IOM uint32_t Ch2_EN

[2..2] Upper threshold IIR filter enable ch 2

[2..2] Lower threshold IIR filter enable ch 2

◆ CH3

[7..6] Filter Coefficients ADC channel 3

[31..24] Channel 3 lower trigger level

[31..24] Channel 3 upper trigger level

◆ Ch3

[7..6] Measurement mode ch 3

◆ Ch3_EN

__IOM uint32_t Ch3_EN

[3..3] Upper threshold IIR filter enable ch 3

[3..3] Lower threshold IIR filter enable ch 3

◆ CH4

[9..8] Filter Coefficients ADC channel 4

[7..0] Channel 4 lower trigger level

[7..0] Channel 4 upper trigger level

◆ Ch4

[9..8] Measurement mode ch 4

◆ Ch4_EN

__IOM uint32_t Ch4_EN

[4..4] Upper threshold IIR filter enable ch 4

[4..4] Lower threshold IIR filter enable ch 4

◆ CH5

[11..10] Filter Coefficients ADC channel 5

[15..8] Channel 5 lower trigger level

[15..8] Channel 5 upper trigger level

◆ Ch5

[11..10] Measurement mode ch 5

◆ Ch5_EN

__IOM uint32_t Ch5_EN

[5..5] Upper threshold IIR filter enable ch 5

[5..5] Lower threshold IIR filter enable ch 5

◆ CH6 [1/2]

[1..0] Filter Coefficients ADC channel 6

[7..0] Channel 6 upper trigger level

◆ CH6 [2/2]

[7..0] Channel 6 lower trigger level

◆ CH7

[3..2] Filter Coefficients ADC channel 7

[15..8] Channel 7 lower trigger level

[15..8] Channel 7 upper trigger level

◆ CH8 [1/2]

[5..4] Filter Coefficients ADC channel 8

[23..16] Channel 8 upper trigger level

◆ CH8 [2/2]

[23..16] Channel 8 lower trigger level

◆ CH9 [1/2]

[7..6] Filter Coefficients ADC channel 9

[31..24] Channel 9 upper trigger level

◆ CH9 [2/2]

[31..24] Channel 9 lower trigger level

◆ CHx [1/2]

[20..16] Current ADC2 Channel

◆ CHx [2/2]

[4..0] Channel set for exceptional interrupt measurement (EIM)

◆ CHx_EIM

union { ... } CHx_EIM

◆ CHx_ESM

union { ... } CHx_ESM

◆ CNT0_3_LOWER

union { ... } CNT0_3_LOWER

◆ CNT0_3_UPPER

union { ... } CNT0_3_UPPER

◆ CNT4_5_LOWER

union { ... } CNT4_5_LOWER

◆ CNT4_5_UPPER

union { ... } CNT4_5_UPPER

◆ CNT6_9_LOWER

union { ... } CNT6_9_LOWER

◆ CNT6_9_UPPER

union { ... } CNT6_9_UPPER

◆ CNT_LO_CH0

__IOM uint32_t CNT_LO_CH0

[2..0] Lower timer trigger threshold channel 0

◆ CNT_LO_CH1

__IOM uint32_t CNT_LO_CH1

[10..8] Lower timer trigger threshold channel 1

◆ CNT_LO_CH2

__IOM uint32_t CNT_LO_CH2

[18..16] Lower timer trigger threshold channel 2

◆ CNT_LO_CH3

__IOM uint32_t CNT_LO_CH3

[26..24] Lower timer trigger threshold channel 3

◆ CNT_LO_CH4

__IOM uint32_t CNT_LO_CH4

[2..0] Lower timer trigger threshold channel 4

◆ CNT_LO_CH5

__IOM uint32_t CNT_LO_CH5

[10..8] Lower timer trigger threshold channel 5

◆ CNT_LO_CH6

__IM uint32_t CNT_LO_CH6

[2..0] Lower timer trigger threshold channel 6

◆ CNT_LO_CH7

__IM uint32_t CNT_LO_CH7

[10..8] Lower timer trigger threshold channel 7

◆ CNT_LO_CH8

__IM uint32_t CNT_LO_CH8

[18..16] Lower timer trigger threshold channel 8

◆ CNT_LO_CH9

__IM uint32_t CNT_LO_CH9

[26..24] Lower timer trigger threshold channel 9

◆ CNT_UP_CH0

__IOM uint32_t CNT_UP_CH0

[2..0] Upper timer trigger threshold channel 0

◆ CNT_UP_CH1

__IOM uint32_t CNT_UP_CH1

[10..8] Upper timer trigger threshold channel 1

◆ CNT_UP_CH2

__IOM uint32_t CNT_UP_CH2

[18..16] Upper timer trigger threshold channel 2

◆ CNT_UP_CH3

__IOM uint32_t CNT_UP_CH3

[26..24] Upper timer trigger threshold channel 3

◆ CNT_UP_CH4

__IOM uint32_t CNT_UP_CH4

[2..0] Upper timer trigger threshold channel 4

◆ CNT_UP_CH5

__IOM uint32_t CNT_UP_CH5

[10..8] Upper timer trigger threshold channel 5

◆ CNT_UP_CH6

__IM uint32_t CNT_UP_CH6

[2..0] Upper timer trigger threshold channel 6

◆ CNT_UP_CH7

__IM uint32_t CNT_UP_CH7

[10..8] Upper timer trigger threshold channel 7

◆ CNT_UP_CH8

__IM uint32_t CNT_UP_CH8

[18..16] Upper timer trigger threshold channel 8

◆ CNT_UP_CH9

__IM uint32_t CNT_UP_CH9

[26..24] Upper timer trigger threshold channel 9

◆ CTRL1

union { ... } CTRL1

◆ CTRL2

union { ... } CTRL2

◆ CTRL4

union { ... } CTRL4

◆ CTRL_STS

union { ... } CTRL_STS

◆ EIM_ACTIVE

__IM uint32_t EIM_ACTIVE

[9..9] ADC2 EIM active

◆ EN

[11..11] Exceptional interrupt measurement (EIM) Trigger Event enable

[16..16] Enable for Exceptional Sequence Measurement Trigger Event

◆ ESM_0

__IOM uint32_t ESM_0

[5..0] Channel Sequence for Exceptional Sequence Measurement (ESM)

◆ ESM_1

__IOM uint32_t ESM_1

[9..6] Channel Sequence for Exceptional Sequence Measurement (ESM)

◆ ESM_ACTIVE

__IM uint32_t ESM_ACTIVE

[10..10] ADC2 ESM active

◆ FILT_LO_CTRL

union { ... } FILT_LO_CTRL

◆ FILT_OUT0

union { ... } FILT_OUT0

◆ FILT_OUT1

union { ... } FILT_OUT1

◆ FILT_OUT2

union { ... } FILT_OUT2

◆ FILT_OUT3

union { ... } FILT_OUT3

◆ FILT_OUT4

union { ... } FILT_OUT4

◆ FILT_OUT5

union { ... } FILT_OUT5

◆ FILT_OUT6

union { ... } FILT_OUT6

◆ FILT_OUT7

union { ... } FILT_OUT7

◆ FILT_OUT8

union { ... } FILT_OUT8

◆ FILT_OUT9

union { ... } FILT_OUT9

◆ FILT_OUT_SEL_5_0

__IOM uint32_t FILT_OUT_SEL_5_0

[5..0] Output Filter Selection for Channels 0 to 5

◆ FILT_OUT_SEL_9_6

__IOM uint32_t FILT_OUT_SEL_9_6

[11..8] Output Filter Selection for Channels 6 to 9

◆ FILT_UP_CTRL

union { ... } FILT_UP_CTRL

◆ FILTCOEFF0_5

union { ... } FILTCOEFF0_5

◆ FILTCOEFF6_9

union { ... } FILTCOEFF6_9

◆ GAIN_CH0

__IOM uint32_t GAIN_CH0

[15..8] Gain Calibration for channel 0

◆ GAIN_CH1

__IOM uint32_t GAIN_CH1

[31..24] Gain Calibration for channel 1

◆ GAIN_CH2

__IOM uint32_t GAIN_CH2

[15..8] Gain Calibration for channel 2

◆ GAIN_CH3

__IOM uint32_t GAIN_CH3

[31..24] Gain Calibration for channel 3

◆ GAIN_CH4

__IOM uint32_t GAIN_CH4

[15..8] Gain Calibration for channel 4

◆ GAIN_CH5

__IOM uint32_t GAIN_CH5

[31..24] Gain Calibration for channel 5

◆ GAIN_CH6

__IM uint32_t GAIN_CH6

[15..8] Gain Calibration for channel 6

◆ GAIN_CH7

__IM uint32_t GAIN_CH7

[31..24] Gain Calibration for channel 7

◆ GAIN_CH8

__IM uint32_t GAIN_CH8

[15..8] Gain Calibration for channel 8

◆ GAIN_CH9

__IM uint32_t GAIN_CH9

[31..24] Gain Calibration for channel 9

◆ HV_STS

union { ... } HV_STS

◆ HYST_LO_CH0

__IOM uint32_t HYST_LO_CH0

[4..3] Channel 0 lower hysteresis

◆ HYST_LO_CH1

__IOM uint32_t HYST_LO_CH1

[12..11] Channel 1 lower hysteresis

◆ HYST_LO_CH2

__IOM uint32_t HYST_LO_CH2

[20..19] Channel 2 lower hysteresis

◆ HYST_LO_CH3

__IOM uint32_t HYST_LO_CH3

[28..27] Channel 3 lower hysteresis

◆ HYST_LO_CH4

__IOM uint32_t HYST_LO_CH4

[4..3] Channel 4 lower hysteresis

◆ HYST_LO_CH5

__IOM uint32_t HYST_LO_CH5

[12..11] Channel 5 lower hysteresis

◆ HYST_LO_CH6

__IM uint32_t HYST_LO_CH6

[4..3] Channel 6 lower hysteresis

◆ HYST_LO_CH7

__IM uint32_t HYST_LO_CH7

[12..11] Channel 7 lower hysteresis

◆ HYST_LO_CH8

__IM uint32_t HYST_LO_CH8

[20..19] Channel 8 lower hysteresis

◆ HYST_LO_CH9

__IM uint32_t HYST_LO_CH9

[28..27] Channel 9 lower hysteresis

◆ HYST_UP_CH0

__IOM uint32_t HYST_UP_CH0

[4..3] Channel 0 upper hysteresis

◆ HYST_UP_CH1

__IOM uint32_t HYST_UP_CH1

[12..11] Channel 1 upper hysteresis

◆ HYST_UP_CH2

__IOM uint32_t HYST_UP_CH2

[20..19] Channel 2 upper hysteresis

◆ HYST_UP_CH3

__IOM uint32_t HYST_UP_CH3

[28..27] Channel 3 upper hysteresis

◆ HYST_UP_CH4

__IOM uint32_t HYST_UP_CH4

[4..3] Channel 4 upper hysteresis

◆ HYST_UP_CH5

__IOM uint32_t HYST_UP_CH5

[12..11] Channel 5 upper hysteresis

◆ HYST_UP_CH6

__IM uint32_t HYST_UP_CH6

[4..3] Channel 6 upper hysteresis

◆ HYST_UP_CH7

__IM uint32_t HYST_UP_CH7

[12..11] Channel 7 upper hysteresis

◆ HYST_UP_CH8

__IM uint32_t HYST_UP_CH8

[20..19] Channel 8 upper hysteresis

◆ HYST_UP_CH9

__IM uint32_t HYST_UP_CH9

[28..27] Channel 9 upper hysteresis

◆ MCM_PD_N

__IOM uint32_t MCM_PD_N

[0..0] Power Down Signal for MCM

◆ MCM_RDY

__IM uint32_t MCM_RDY

[7..7] Ready Signal for MCM after Power On or Reset

◆ MMODE0_5

union { ... } MMODE0_5

◆ OFFS_CH0

__IOM uint32_t OFFS_CH0

[7..0] Offset Calibration for channel 0

◆ OFFS_CH1

__IOM uint32_t OFFS_CH1

[23..16] Offset Calibration for channel 1

◆ OFFS_CH2

__IOM uint32_t OFFS_CH2

[7..0] Offset Calibration for channel 2

◆ OFFS_CH3

__IOM uint32_t OFFS_CH3

[23..16] Offset Calibration for channel 3

◆ OFFS_CH4

__IOM uint32_t OFFS_CH4

[7..0] Offset Calibration for channel 4

◆ OFFS_CH5

__IOM uint32_t OFFS_CH5

[23..16] Offset Calibration for channel 5

◆ OFFS_CH6

__IM uint32_t OFFS_CH6

[7..0] Offset Calibration for channel 6

◆ OFFS_CH7

__IM uint32_t OFFS_CH7

[23..16] Offset Calibration for channel 7

◆ OFFS_CH8

__IM uint32_t OFFS_CH8

[7..0] Offset Calibration for channel 8

◆ OFFS_CH9

__IM uint32_t OFFS_CH9

[23..16] Offset Calibration for channel 9

◆ OUT_CH0

__IM uint32_t OUT_CH0

[9..0] ADC or filter output value channel 0

◆ OUT_CH1

__IM uint32_t OUT_CH1

[9..0] ADC or filter output value channel 1

◆ OUT_CH2

__IM uint32_t OUT_CH2

[9..0] ADC or filter output value channel 2

◆ OUT_CH3

__IM uint32_t OUT_CH3

[9..0] ADC or filter output value channel 3

◆ OUT_CH4

__IM uint32_t OUT_CH4

[9..0] ADC or filter output value channel 4

◆ OUT_CH5

__IM uint32_t OUT_CH5

[9..0] ADC or filter output value channel 5

◆ OUT_CH6

__IM uint32_t OUT_CH6

[9..0] ADC or filter output value channel 6

◆ OUT_CH7

__IM uint32_t OUT_CH7

[9..0] ADC or filter output value channel 7

◆ OUT_CH8

__IM uint32_t OUT_CH8

[9..0] ADC or filter output value channel 8

◆ OUT_CH9

__IM uint32_t OUT_CH9

[9..0] ADC or filter output value channel 9

◆ READY

__IM uint32_t READY

[1..1] HVADC Ready bit

◆ reg

(@ 0x00000000) ADC2 Control and Status Register

(@ 0x00000004) Sequencer Feedback Register

(@ 0x00000008) Channel Settings Bits for Exceptional Interrupt Measurement

(@ 0x0000000C) Channel Settings Bits for Exceptional Sequence Measurement

(@ 0x00000014) Measurement Unit Control Register 1

(@ 0x00000018) Measurement Unit Control Register 2

(@ 0x0000001C) Measurement Unit Control Register 4

(@ 0x00000020) Measurement Channel Enable Bits for Cycle 1-4

(@ 0x00000024) Measurement Channel Enable Bits for Cycle 5 - 8

(@ 0x00000028) Measurement Channel Enable Bits for Cycle 9 - 10

(@ 0x0000002C) Measurement Channel Enable Bits for Cycle 1 - 8

(@ 0x00000030) Measurement Channel Enable Bits for Cycle 9 and 10

(@ 0x00000034) Calibration for Channel 0 and 1

(@ 0x00000038) Calibration for Channel 2 and 3

(@ 0x0000003C) Calibration for Channel 4 and 5

(@ 0x00000040) Calibration for Channel 6 and 7

(@ 0x00000044) Calibration for Channel 8 and 9

(@ 0x00000048) Filter Coefficients ADC Channel 0-5

(@ 0x0000004C) Filter Coefficents ADC Channel 6-9

(@ 0x00000050) ADC or Filter Output Channel 0

(@ 0x00000054) ADC or Filter Output Channel 1

(@ 0x00000058) ADC or Filter Output Channel 2

(@ 0x0000005C) ADC or Filter Output Channel 3

(@ 0x00000060) ADC or Filter Output Channel 4

(@ 0x00000064) ADC or Filter Output Channel 5

(@ 0x00000068) ADC or Filter Output Channel 6

(@ 0x0000006C) ADC or Filter Output Channel 7

(@ 0x00000070) ADC or Filter Output Channel 8

(@ 0x00000074) ADC or Filter Output Channel 9

(@ 0x00000078) Upper Threshold Filter Enable

(@ 0x0000007C) Lower Threshold Filter Enable

(@ 0x00000080) Lower Comparator Trigger Level Channel 0 -3

(@ 0x00000084) Lower Comparator Trigger Level Channel 4 and 5

(@ 0x00000088) Lower Comparator Trigger Level Channel 6 -9

(@ 0x0000008C) Upper Comparator Trigger Level Channel 0-3

(@ 0x00000090) Upper Comparator Trigger Level Channel 4 -5

(@ 0x00000094) Upper Comparator Trigger Level Channel 6 -9

(@ 0x00000098) Lower Counter Trigger Level Channel 0 - 3

(@ 0x0000009C) Lower Counter Trigger Level Channel 4 and 5

(@ 0x000000A0) Lower Counter Trigger Level Channel 6 - 9

(@ 0x000000A4) Upper Counter Trigger Level Channel 0 - 3

(@ 0x000000A8) Upper Counter Trigger Level Channel 4 and 5

(@ 0x000000AC) Upper Counter Trigger Level Channel 6 -9

(@ 0x000000B0) Overvoltage Measurement Mode of Ch 0-5

(@ 0x000000BC) ADC2 HV Status Register

◆ REP

[10..8] Repeat count for exceptional interrupt measurement (EIM)

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1[2]

◆ SAMPLE_TIME_int

__IOM uint32_t SAMPLE_TIME_int

[11..8] Sample time of ADC2

◆ SEL

[12..12] Exceptional interrupt measurement (EIM) Trigger Trigger select

[10..10] Exceptional Sequence Measurement Trigger Select

◆ SEL_TS_COUNT

__IOM uint32_t SEL_TS_COUNT

[19..16] Time for automatic multiplexing of temperature sensor

◆ SQ1

[5..0] Sequence 1 channel enable

◆ SQ10

[13..8] Sequence 10 channel enable

◆ SQ10_int

__IM uint32_t SQ10_int

[7..4] Sequence 10 channel enable

◆ SQ1_4

union { ... } SQ1_4

◆ SQ1_8_int

union { ... } SQ1_8_int

◆ SQ1_int

__IM uint32_t SQ1_int

[3..0] Sequence 1 channel enable

◆ SQ2

[13..8] Sequence 2 channel enable

◆ SQ2_int

__IM uint32_t SQ2_int

[7..4] Sequence 2 channel enable

◆ SQ3

[21..16] Sequence 3 channel enable

◆ SQ3_int

__IM uint32_t SQ3_int

[11..8] Sequence 3 channel enable

◆ SQ4

[29..24] Sequence 4 channel enable

◆ SQ4_int

__IM uint32_t SQ4_int

[15..12] Sequence 4 channel enable

◆ SQ5

[5..0] Sequence 5 channel enable

◆ SQ5_8

union { ... } SQ5_8

◆ SQ5_int

__IM uint32_t SQ5_int

[19..16] Sequence 5 channel enable

◆ SQ6

[13..8] Sequence 6 channel enable

◆ SQ6_int

__IM uint32_t SQ6_int

[23..20] Sequence 6 channel enable

◆ SQ7

[21..16] Sequence 7 channel enable

◆ SQ7_int

__IM uint32_t SQ7_int

[27..24] Sequence 7 channel enable

◆ SQ8

[29..24] Sequence 8 channel enable

◆ SQ8_int

__IM uint32_t SQ8_int

[31..28] Sequence 8 channel enable

◆ SQ9

[5..0] Sequence 9 channel enable

◆ SQ9_10

union { ... } SQ9_10

◆ SQ9_10_int

union { ... } SQ9_10_int

◆ SQ9_int

__IM uint32_t SQ9_int

[3..0] Sequence 9 channel enable

◆ SQ_FB [1/2]

__IM uint32_t SQ_FB

[3..0] Current Sequence that caused software mode

◆ SQ_FB [2/2]

union { ... } SQ_FB

◆ SQ_STOP

__IM uint32_t SQ_STOP

[8..8] ADC2 Sequencer Stop Signal for DPP

◆ SQx

[14..11] Current Active Sequencer

◆ STS

[17..17] Exceptional Sequence Measurement is finished

◆ TH0_3_LOWER

union { ... } TH0_3_LOWER

◆ TH0_3_UPPER

union { ... } TH0_3_UPPER

◆ TH4_5_LOWER

union { ... } TH4_5_LOWER

◆ TH4_5_UPPER

union { ... } TH4_5_UPPER

◆ TH6_9_LOWER

union { ... } TH6_9_LOWER

◆ TH6_9_UPPER

union { ... } TH6_9_UPPER

◆ TS_SD_SEL_CONF

__IOM uint32_t TS_SD_SEL_CONF

[1..1] Temperature Sensor Control Configuration

◆ TSENSE_SD_SEL

__IOM uint32_t TSENSE_SD_SEL

[2..2] Temperature Sensor selection connected to Ch9

◆ uint32_t

__IM uint32_t

◆ VBAT_RANGE

__IOM uint32_t VBAT_RANGE

[16..16] ADC2 Channel 0 Range Selection

◆ VS_RANGE

__IOM uint32_t VS_RANGE

[17..17] ADC2 Channel 1 Range Selection


The documentation for this struct was generated from the following file: