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TLE986x Device Family SDK
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#define ADC1_CHx_EIM_CHx_Msk (0x7UL) |
ADC1 CHx_EIM: CHx (Bitfield-Mask: 0x07)
#define ADC1_CHx_EIM_CHx_Pos (0UL) |
ADC1 CHx_EIM: CHx (Bit 0)
#define ADC1_CHx_EIM_REP_Msk (0x70UL) |
ADC1 CHx_EIM: REP (Bitfield-Mask: 0x07)
#define ADC1_CHx_EIM_REP_Pos (4UL) |
ADC1 CHx_EIM: REP (Bit 4)
#define ADC1_CHx_EIM_TRIG_SEL_Msk (0x70000UL) |
ADC1 CHx_EIM: TRIG_SEL (Bitfield-Mask: 0x07)
#define ADC1_CHx_EIM_TRIG_SEL_Pos (16UL) |
ADC1 CHx_EIM: TRIG_SEL (Bit 16)
#define ADC1_CHx_ESM_ESM_0_Msk (0xffUL) |
ADC1 CHx_ESM: ESM_0 (Bitfield-Mask: 0xff)
#define ADC1_CHx_ESM_ESM_0_Pos (0UL) |
ADC1 CHx_ESM: ESM_0 (Bit 0)
#define ADC1_CHx_ESM_TRIG_SEL_Msk (0x70000UL) |
ADC1 CHx_ESM: TRIG_SEL (Bitfield-Mask: 0x07)
#define ADC1_CHx_ESM_TRIG_SEL_Pos (16UL) |
ADC1 CHx_ESM: TRIG_SEL (Bit 16)
#define ADC1_CTRL_STS_EOC_Msk (0x8UL) |
ADC1 CTRL_STS: EOC (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_EOC_Pos (3UL) |
ADC1 CTRL_STS: EOC (Bit 3)
#define ADC1_CTRL_STS_IN_MUX_SEL_Msk (0x70UL) |
ADC1 CTRL_STS: IN_MUX_SEL (Bitfield-Mask: 0x07)
#define ADC1_CTRL_STS_IN_MUX_SEL_Pos (4UL) |
ADC1 CTRL_STS: IN_MUX_SEL (Bit 4)
#define ADC1_CTRL_STS_PD_N_Msk (0x1UL) |
ADC1 CTRL_STS: PD_N (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_PD_N_Pos (0UL) |
ADC1 CTRL_STS: PD_N (Bit 0)
#define ADC1_CTRL_STS_SOC_Msk (0x4UL) |
ADC1 CTRL_STS: SOC (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_SOC_Pos (2UL) |
ADC1 CTRL_STS: SOC (Bit 2)
#define ADC1_DWSEL_ch0_Msk (0x1UL) |
ADC1 DWSEL: ch0 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch0_Pos (0UL) |
ADC1 DWSEL: ch0 (Bit 0)
#define ADC1_DWSEL_ch1_Msk (0x2UL) |
ADC1 DWSEL: ch1 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch1_Pos (1UL) |
ADC1 DWSEL: ch1 (Bit 1)
#define ADC1_DWSEL_ch2_Msk (0x4UL) |
ADC1 DWSEL: ch2 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch2_Pos (2UL) |
ADC1 DWSEL: ch2 (Bit 2)
#define ADC1_DWSEL_ch3_Msk (0x8UL) |
ADC1 DWSEL: ch3 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch3_Pos (3UL) |
ADC1 DWSEL: ch3 (Bit 3)
#define ADC1_DWSEL_ch4_Msk (0x10UL) |
ADC1 DWSEL: ch4 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch4_Pos (4UL) |
ADC1 DWSEL: ch4 (Bit 4)
#define ADC1_DWSEL_ch5_Msk (0x20UL) |
ADC1 DWSEL: ch5 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch5_Pos (5UL) |
ADC1 DWSEL: ch5 (Bit 5)
#define ADC1_DWSEL_ch6_Msk (0x40UL) |
ADC1 DWSEL: ch6 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch6_Pos (6UL) |
ADC1 DWSEL: ch6 (Bit 6)
#define ADC1_DWSEL_ch7_Msk (0x80UL) |
ADC1 DWSEL: ch7 (Bitfield-Mask: 0x01)
#define ADC1_DWSEL_ch7_Pos (7UL) |
ADC1 DWSEL: ch7 (Bit 7)
#define ADC1_GLOBCTR_ANON_Msk (0x300UL) |
ADC1 GLOBCTR: ANON (Bitfield-Mask: 0x03)
#define ADC1_GLOBCTR_ANON_Pos (8UL) |
ADC1 GLOBCTR: ANON (Bit 8)
#define ADC1_GLOBCTR_DIVA_Msk (0x3fUL) |
ADC1 GLOBCTR: DIVA (Bitfield-Mask: 0x3f)
#define ADC1_GLOBCTR_DIVA_Pos (0UL) |
ADC1 GLOBCTR: DIVA (Bit 0)
#define ADC1_GLOBSTR_ANON_ST_Msk (0x300UL) |
ADC1 GLOBSTR: ANON_ST (Bitfield-Mask: 0x03)
#define ADC1_GLOBSTR_ANON_ST_Pos (8UL) |
ADC1 GLOBSTR: ANON_ST (Bit 8)
#define ADC1_GLOBSTR_BUSY_Msk (0x1UL) |
ADC1 GLOBSTR: BUSY (Bitfield-Mask: 0x01)
#define ADC1_GLOBSTR_BUSY_Pos (0UL) |
ADC1 GLOBSTR: BUSY (Bit 0)
#define ADC1_GLOBSTR_CHNR_Msk (0x38UL) |
ADC1 GLOBSTR: CHNR (Bitfield-Mask: 0x07)
#define ADC1_GLOBSTR_CHNR_Pos (3UL) |
ADC1 GLOBSTR: CHNR (Bit 3)
#define ADC1_GLOBSTR_SAMPLE_Msk (0x2UL) |
ADC1 GLOBSTR: SAMPLE (Bitfield-Mask: 0x01)
#define ADC1_GLOBSTR_SAMPLE_Pos (1UL) |
ADC1 GLOBSTR: SAMPLE (Bit 1)
#define ADC1_ICLR_CH0_ICLR_Msk (0x1UL) |
ADC1 ICLR: CH0_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH0_ICLR_Pos (0UL) |
ADC1 ICLR: CH0_ICLR (Bit 0)
#define ADC1_ICLR_CH1_ICLR_Msk (0x2UL) |
ADC1 ICLR: CH1_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH1_ICLR_Pos (1UL) |
ADC1 ICLR: CH1_ICLR (Bit 1)
#define ADC1_ICLR_CH2_ICLR_Msk (0x4UL) |
ADC1 ICLR: CH2_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH2_ICLR_Pos (2UL) |
ADC1 ICLR: CH2_ICLR (Bit 2)
#define ADC1_ICLR_CH3_ICLR_Msk (0x8UL) |
ADC1 ICLR: CH3_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH3_ICLR_Pos (3UL) |
ADC1 ICLR: CH3_ICLR (Bit 3)
#define ADC1_ICLR_CH4_ICLR_Msk (0x10UL) |
ADC1 ICLR: CH4_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH4_ICLR_Pos (4UL) |
ADC1 ICLR: CH4_ICLR (Bit 4)
#define ADC1_ICLR_CH5_ICLR_Msk (0x20UL) |
ADC1 ICLR: CH5_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH5_ICLR_Pos (5UL) |
ADC1 ICLR: CH5_ICLR (Bit 5)
#define ADC1_ICLR_CH6_ICLR_Msk (0x40UL) |
ADC1 ICLR: CH6_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH6_ICLR_Pos (6UL) |
ADC1 ICLR: CH6_ICLR (Bit 6)
#define ADC1_ICLR_CH7_ICLR_Msk (0x80UL) |
ADC1 ICLR: CH7_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_CH7_ICLR_Pos (7UL) |
ADC1 ICLR: CH7_ICLR (Bit 7)
#define ADC1_ICLR_EIM_ICLR_Msk (0x100UL) |
ADC1 ICLR: EIM_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_EIM_ICLR_Pos (8UL) |
ADC1 ICLR: EIM_ICLR (Bit 8)
#define ADC1_ICLR_ESM_ICLR_Msk (0x200UL) |
ADC1 ICLR: ESM_ICLR (Bitfield-Mask: 0x01)
#define ADC1_ICLR_ESM_ICLR_Pos (9UL) |
ADC1 ICLR: ESM_ICLR (Bit 9)
#define ADC1_IE_CH0_IE_Msk (0x1UL) |
ADC1 IE: CH0_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH0_IE_Pos (0UL) |
ADC1 IE: CH0_IE (Bit 0)
#define ADC1_IE_CH1_IE_Msk (0x2UL) |
ADC1 IE: CH1_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH1_IE_Pos (1UL) |
ADC1 IE: CH1_IE (Bit 1)
#define ADC1_IE_CH2_IE_Msk (0x4UL) |
ADC1 IE: CH2_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH2_IE_Pos (2UL) |
ADC1 IE: CH2_IE (Bit 2)
#define ADC1_IE_CH3_IE_Msk (0x8UL) |
ADC1 IE: CH3_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH3_IE_Pos (3UL) |
ADC1 IE: CH3_IE (Bit 3)
#define ADC1_IE_CH4_IE_Msk (0x10UL) |
ADC1 IE: CH4_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH4_IE_Pos (4UL) |
ADC1 IE: CH4_IE (Bit 4)
#define ADC1_IE_CH5_IE_Msk (0x20UL) |
ADC1 IE: CH5_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH5_IE_Pos (5UL) |
ADC1 IE: CH5_IE (Bit 5)
#define ADC1_IE_CH6_IE_Msk (0x40UL) |
ADC1 IE: CH6_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH6_IE_Pos (6UL) |
ADC1 IE: CH6_IE (Bit 6)
#define ADC1_IE_CH7_IE_Msk (0x80UL) |
ADC1 IE: CH7_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_CH7_IE_Pos (7UL) |
ADC1 IE: CH7_IE (Bit 7)
#define ADC1_IE_EIM_IE_Msk (0x100UL) |
ADC1 IE: EIM_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_EIM_IE_Pos (8UL) |
ADC1 IE: EIM_IE (Bit 8)
#define ADC1_IE_ESM_IE_Msk (0x200UL) |
ADC1 IE: ESM_IE (Bitfield-Mask: 0x01)
#define ADC1_IE_ESM_IE_Pos (9UL) |
ADC1 IE: ESM_IE (Bit 9)
#define ADC1_IS_CH0_STS_Msk (0x1UL) |
ADC1 IS: CH0_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH0_STS_Pos (0UL) |
ADC1 IS: CH0_STS (Bit 0)
#define ADC1_IS_CH1_STS_Msk (0x2UL) |
ADC1 IS: CH1_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH1_STS_Pos (1UL) |
ADC1 IS: CH1_STS (Bit 1)
#define ADC1_IS_CH2_STS_Msk (0x4UL) |
ADC1 IS: CH2_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH2_STS_Pos (2UL) |
ADC1 IS: CH2_STS (Bit 2)
#define ADC1_IS_CH3_STS_Msk (0x8UL) |
ADC1 IS: CH3_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH3_STS_Pos (3UL) |
ADC1 IS: CH3_STS (Bit 3)
#define ADC1_IS_CH4_STS_Msk (0x10UL) |
ADC1 IS: CH4_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH4_STS_Pos (4UL) |
ADC1 IS: CH4_STS (Bit 4)
#define ADC1_IS_CH5_STS_Msk (0x20UL) |
ADC1 IS: CH5_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH5_STS_Pos (5UL) |
ADC1 IS: CH5_STS (Bit 5)
#define ADC1_IS_CH6_STS_Msk (0x40UL) |
ADC1 IS: CH6_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH6_STS_Pos (6UL) |
ADC1 IS: CH6_STS (Bit 6)
#define ADC1_IS_CH7_STS_Msk (0x80UL) |
ADC1 IS: CH7_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_CH7_STS_Pos (7UL) |
ADC1 IS: CH7_STS (Bit 7)
#define ADC1_IS_EIM_STS_Msk (0x100UL) |
ADC1 IS: EIM_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_EIM_STS_Pos (8UL) |
ADC1 IS: EIM_STS (Bit 8)
#define ADC1_IS_ESM_STS_Msk (0x200UL) |
ADC1 IS: ESM_STS (Bitfield-Mask: 0x01)
#define ADC1_IS_ESM_STS_Pos (9UL) |
ADC1 IS: ESM_STS (Bit 9)
#define ADC1_RES_OUT0_OF0_Msk (0x40000UL) |
ADC1 RES_OUT0: OF0 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT0_OF0_Pos (18UL) |
ADC1 RES_OUT0: OF0 (Bit 18)
#define ADC1_RES_OUT0_OUT_CH0_Msk (0xfffUL) |
ADC1 RES_OUT0: OUT_CH0 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT0_OUT_CH0_Pos (0UL) |
ADC1 RES_OUT0: OUT_CH0 (Bit 0)
#define ADC1_RES_OUT0_VF0_Msk (0x20000UL) |
ADC1 RES_OUT0: VF0 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT0_VF0_Pos (17UL) |
ADC1 RES_OUT0: VF0 (Bit 17)
#define ADC1_RES_OUT0_WFR0_Msk (0x10000UL) |
ADC1 RES_OUT0: WFR0 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT0_WFR0_Pos (16UL) |
ADC1 RES_OUT0: WFR0 (Bit 16)
#define ADC1_RES_OUT1_OF1_Msk (0x40000UL) |
ADC1 RES_OUT1: OF1 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT1_OF1_Pos (18UL) |
ADC1 RES_OUT1: OF1 (Bit 18)
#define ADC1_RES_OUT1_OUT_CH1_Msk (0xfffUL) |
ADC1 RES_OUT1: OUT_CH1 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT1_OUT_CH1_Pos (0UL) |
ADC1 RES_OUT1: OUT_CH1 (Bit 0)
#define ADC1_RES_OUT1_VF1_Msk (0x20000UL) |
ADC1 RES_OUT1: VF1 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT1_VF1_Pos (17UL) |
ADC1 RES_OUT1: VF1 (Bit 17)
#define ADC1_RES_OUT1_WFR1_Msk (0x10000UL) |
ADC1 RES_OUT1: WFR1 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT1_WFR1_Pos (16UL) |
ADC1 RES_OUT1: WFR1 (Bit 16)
#define ADC1_RES_OUT2_OF2_Msk (0x40000UL) |
ADC1 RES_OUT2: OF2 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT2_OF2_Pos (18UL) |
ADC1 RES_OUT2: OF2 (Bit 18)
#define ADC1_RES_OUT2_OUT_CH2_Msk (0xfffUL) |
ADC1 RES_OUT2: OUT_CH2 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT2_OUT_CH2_Pos (0UL) |
ADC1 RES_OUT2: OUT_CH2 (Bit 0)
#define ADC1_RES_OUT2_VF2_Msk (0x20000UL) |
ADC1 RES_OUT2: VF2 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT2_VF2_Pos (17UL) |
ADC1 RES_OUT2: VF2 (Bit 17)
#define ADC1_RES_OUT2_WFR2_Msk (0x10000UL) |
ADC1 RES_OUT2: WFR2 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT2_WFR2_Pos (16UL) |
ADC1 RES_OUT2: WFR2 (Bit 16)
#define ADC1_RES_OUT3_OF3_Msk (0x40000UL) |
ADC1 RES_OUT3: OF3 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT3_OF3_Pos (18UL) |
ADC1 RES_OUT3: OF3 (Bit 18)
#define ADC1_RES_OUT3_OUT_CH3_Msk (0xfffUL) |
ADC1 RES_OUT3: OUT_CH3 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT3_OUT_CH3_Pos (0UL) |
ADC1 RES_OUT3: OUT_CH3 (Bit 0)
#define ADC1_RES_OUT3_VF3_Msk (0x20000UL) |
ADC1 RES_OUT3: VF3 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT3_VF3_Pos (17UL) |
ADC1 RES_OUT3: VF3 (Bit 17)
#define ADC1_RES_OUT3_WFR3_Msk (0x10000UL) |
ADC1 RES_OUT3: WFR3 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT3_WFR3_Pos (16UL) |
ADC1 RES_OUT3: WFR3 (Bit 16)
#define ADC1_RES_OUT4_OF4_Msk (0x40000UL) |
ADC1 RES_OUT4: OF4 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT4_OF4_Pos (18UL) |
ADC1 RES_OUT4: OF4 (Bit 18)
#define ADC1_RES_OUT4_OUT_CH4_Msk (0xfffUL) |
ADC1 RES_OUT4: OUT_CH4 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT4_OUT_CH4_Pos (0UL) |
ADC1 RES_OUT4: OUT_CH4 (Bit 0)
#define ADC1_RES_OUT4_VF4_Msk (0x20000UL) |
ADC1 RES_OUT4: VF4 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT4_VF4_Pos (17UL) |
ADC1 RES_OUT4: VF4 (Bit 17)
#define ADC1_RES_OUT4_WFR4_Msk (0x10000UL) |
ADC1 RES_OUT4: WFR4 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT4_WFR4_Pos (16UL) |
ADC1 RES_OUT4: WFR4 (Bit 16)
#define ADC1_RES_OUT5_OF5_Msk (0x40000UL) |
ADC1 RES_OUT5: OF5 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT5_OF5_Pos (18UL) |
ADC1 RES_OUT5: OF5 (Bit 18)
#define ADC1_RES_OUT5_OUT_CH5_Msk (0xfffUL) |
ADC1 RES_OUT5: OUT_CH5 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT5_OUT_CH5_Pos (0UL) |
ADC1 RES_OUT5: OUT_CH5 (Bit 0)
#define ADC1_RES_OUT5_VF5_Msk (0x20000UL) |
ADC1 RES_OUT5: VF5 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT5_VF5_Pos (17UL) |
ADC1 RES_OUT5: VF5 (Bit 17)
#define ADC1_RES_OUT5_WFR5_Msk (0x10000UL) |
ADC1 RES_OUT5: WFR5 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT5_WFR5_Pos (16UL) |
ADC1 RES_OUT5: WFR5 (Bit 16)
#define ADC1_RES_OUT6_OF6_Msk (0x40000UL) |
ADC1 RES_OUT6: OF6 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT6_OF6_Pos (18UL) |
ADC1 RES_OUT6: OF6 (Bit 18)
#define ADC1_RES_OUT6_OUT_CH6_Msk (0xfffUL) |
ADC1 RES_OUT6: OUT_CH6 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT6_OUT_CH6_Pos (0UL) |
ADC1 RES_OUT6: OUT_CH6 (Bit 0)
#define ADC1_RES_OUT6_VF6_Msk (0x20000UL) |
ADC1 RES_OUT6: VF6 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT6_VF6_Pos (17UL) |
ADC1 RES_OUT6: VF6 (Bit 17)
#define ADC1_RES_OUT6_WFR6_Msk (0x10000UL) |
ADC1 RES_OUT6: WFR6 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT6_WFR6_Pos (16UL) |
ADC1 RES_OUT6: WFR6 (Bit 16)
#define ADC1_RES_OUT7_OF7_Msk (0x40000UL) |
ADC1 RES_OUT7: OF7 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT7_OF7_Pos (18UL) |
ADC1 RES_OUT7: OF7 (Bit 18)
#define ADC1_RES_OUT7_OUT_CH7_Msk (0xfffUL) |
ADC1 RES_OUT7: OUT_CH7 (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT7_OUT_CH7_Pos (0UL) |
ADC1 RES_OUT7: OUT_CH7 (Bit 0)
#define ADC1_RES_OUT7_VF7_Msk (0x20000UL) |
ADC1 RES_OUT7: VF7 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT7_VF7_Pos (17UL) |
ADC1 RES_OUT7: VF7 (Bit 17)
#define ADC1_RES_OUT7_WFR7_Msk (0x10000UL) |
ADC1 RES_OUT7: WFR7 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT7_WFR7_Pos (16UL) |
ADC1 RES_OUT7: WFR7 (Bit 16)
#define ADC1_RES_OUT_EIM_OF8_Msk (0x40000UL) |
ADC1 RES_OUT_EIM: OF8 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT_EIM_OF8_Pos (18UL) |
ADC1 RES_OUT_EIM: OF8 (Bit 18)
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk (0xfffUL) |
ADC1 RES_OUT_EIM: OUT_CH_EIM (Bitfield-Mask: 0xfff)
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos (0UL) |
ADC1 RES_OUT_EIM: OUT_CH_EIM (Bit 0)
#define ADC1_RES_OUT_EIM_VF8_Msk (0x20000UL) |
ADC1 RES_OUT_EIM: VF8 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT_EIM_VF8_Pos (17UL) |
ADC1 RES_OUT_EIM: VF8 (Bit 17)
#define ADC1_RES_OUT_EIM_WFR8_Msk (0x10000UL) |
ADC1 RES_OUT_EIM: WFR8 (Bitfield-Mask: 0x01)
#define ADC1_RES_OUT_EIM_WFR8_Pos (16UL) |
ADC1 RES_OUT_EIM: WFR8 (Bit 16)
#define ADC1_SQ1_4_SQ1_Msk (0xffUL) |
ADC1 SQ1_4: SQ1 (Bitfield-Mask: 0xff)
#define ADC1_SQ1_4_SQ1_Pos (0UL) |
ADC1 SQ1_4: SQ1 (Bit 0)
#define ADC1_SQ1_4_SQ2_Msk (0xff00UL) |
ADC1 SQ1_4: SQ2 (Bitfield-Mask: 0xff)
#define ADC1_SQ1_4_SQ2_Pos (8UL) |
ADC1 SQ1_4: SQ2 (Bit 8)
#define ADC1_SQ1_4_SQ3_Msk (0xff0000UL) |
ADC1 SQ1_4: SQ3 (Bitfield-Mask: 0xff)
#define ADC1_SQ1_4_SQ3_Pos (16UL) |
ADC1 SQ1_4: SQ3 (Bit 16)
#define ADC1_SQ1_4_SQ4_Msk (0xff000000UL) |
ADC1 SQ1_4: SQ4 (Bitfield-Mask: 0xff)
#define ADC1_SQ1_4_SQ4_Pos (24UL) |
ADC1 SQ1_4: SQ4 (Bit 24)
#define ADC1_SQ5_8_SQ5_Msk (0xffUL) |
ADC1 SQ5_8: SQ5 (Bitfield-Mask: 0xff)
#define ADC1_SQ5_8_SQ5_Pos (0UL) |
ADC1 SQ5_8: SQ5 (Bit 0)
#define ADC1_SQ5_8_SQ6_Msk (0xff00UL) |
ADC1 SQ5_8: SQ6 (Bitfield-Mask: 0xff)
#define ADC1_SQ5_8_SQ6_Pos (8UL) |
ADC1 SQ5_8: SQ6 (Bit 8)
#define ADC1_SQ5_8_SQ7_Msk (0xff0000UL) |
ADC1 SQ5_8: SQ7 (Bitfield-Mask: 0xff)
#define ADC1_SQ5_8_SQ7_Pos (16UL) |
ADC1 SQ5_8: SQ7 (Bit 16)
#define ADC1_SQ5_8_SQ8_Msk (0xff000000UL) |
ADC1 SQ5_8: SQ8 (Bitfield-Mask: 0xff)
#define ADC1_SQ5_8_SQ8_Pos (24UL) |
ADC1 SQ5_8: SQ8 (Bit 24)
#define ADC1_SQ_FB_CHx_Msk (0x70000UL) |
ADC1 SQ_FB: CHx (Bitfield-Mask: 0x07)
#define ADC1_SQ_FB_CHx_Pos (16UL) |
ADC1 SQ_FB: CHx (Bit 16)
#define ADC1_SQ_FB_EIM_ACTIVE_Msk (0x200UL) |
ADC1 SQ_FB: EIM_ACTIVE (Bitfield-Mask: 0x01)
#define ADC1_SQ_FB_EIM_ACTIVE_Pos (9UL) |
ADC1 SQ_FB: EIM_ACTIVE (Bit 9)
#define ADC1_SQ_FB_ESM_ACTIVE_Msk (0x400UL) |
ADC1 SQ_FB: ESM_ACTIVE (Bitfield-Mask: 0x01)
#define ADC1_SQ_FB_ESM_ACTIVE_Pos (10UL) |
ADC1 SQ_FB: ESM_ACTIVE (Bit 10)
#define ADC1_SQ_FB_SQ_RUN_Msk (0x100UL) |
ADC1 SQ_FB: SQ_RUN (Bitfield-Mask: 0x01)
#define ADC1_SQ_FB_SQ_RUN_Pos (8UL) |
ADC1 SQ_FB: SQ_RUN (Bit 8)
#define ADC1_SQ_FB_SQx_Msk (0x3800UL) |
ADC1 SQ_FB: SQx (Bitfield-Mask: 0x07)
#define ADC1_SQ_FB_SQx_Pos (11UL) |
ADC1 SQ_FB: SQx (Bit 11)
#define ADC1_STC_0_3_ch0_Msk (0xffUL) |
ADC1 STC_0_3: ch0 (Bitfield-Mask: 0xff)
#define ADC1_STC_0_3_ch0_Pos (0UL) |
ADC1 STC_0_3: ch0 (Bit 0)
#define ADC1_STC_0_3_ch1_Msk (0xff00UL) |
ADC1 STC_0_3: ch1 (Bitfield-Mask: 0xff)
#define ADC1_STC_0_3_ch1_Pos (8UL) |
ADC1 STC_0_3: ch1 (Bit 8)
#define ADC1_STC_0_3_ch2_Msk (0xff0000UL) |
ADC1 STC_0_3: ch2 (Bitfield-Mask: 0xff)
#define ADC1_STC_0_3_ch2_Pos (16UL) |
ADC1 STC_0_3: ch2 (Bit 16)
#define ADC1_STC_0_3_ch3_Msk (0xff000000UL) |
ADC1 STC_0_3: ch3 (Bitfield-Mask: 0xff)
#define ADC1_STC_0_3_ch3_Pos (24UL) |
ADC1 STC_0_3: ch3 (Bit 24)
#define ADC1_STC_4_7_ch4_Msk (0xffUL) |
ADC1 STC_4_7: ch4 (Bitfield-Mask: 0xff)
#define ADC1_STC_4_7_ch4_Pos (0UL) |
ADC1 STC_4_7: ch4 (Bit 0)
#define ADC1_STC_4_7_ch5_Msk (0xff00UL) |
ADC1 STC_4_7: ch5 (Bitfield-Mask: 0xff)
#define ADC1_STC_4_7_ch5_Pos (8UL) |
ADC1 STC_4_7: ch5 (Bit 8)
#define ADC1_STC_4_7_ch6_Msk (0xff0000UL) |
ADC1 STC_4_7: ch6 (Bitfield-Mask: 0xff)
#define ADC1_STC_4_7_ch6_Pos (16UL) |
ADC1 STC_4_7: ch6 (Bit 16)
#define ADC1_STC_4_7_ch7_Msk (0xff000000UL) |
ADC1 STC_4_7: ch7 (Bitfield-Mask: 0xff)
#define ADC1_STC_4_7_ch7_Pos (24UL) |
ADC1 STC_4_7: ch7 (Bit 24)
#define ADC2_CAL_CH0_1_GAIN_CH0_Msk (0xff00UL) |
ADC2 CAL_CH0_1: GAIN_CH0 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH0_1_GAIN_CH0_Pos (8UL) |
ADC2 CAL_CH0_1: GAIN_CH0 (Bit 8)
#define ADC2_CAL_CH0_1_GAIN_CH1_Msk (0xff000000UL) |
ADC2 CAL_CH0_1: GAIN_CH1 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH0_1_GAIN_CH1_Pos (24UL) |
ADC2 CAL_CH0_1: GAIN_CH1 (Bit 24)
#define ADC2_CAL_CH0_1_OFFS_CH0_Msk (0xffUL) |
ADC2 CAL_CH0_1: OFFS_CH0 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH0_1_OFFS_CH0_Pos (0UL) |
ADC2 CAL_CH0_1: OFFS_CH0 (Bit 0)
#define ADC2_CAL_CH0_1_OFFS_CH1_Msk (0xff0000UL) |
ADC2 CAL_CH0_1: OFFS_CH1 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH0_1_OFFS_CH1_Pos (16UL) |
ADC2 CAL_CH0_1: OFFS_CH1 (Bit 16)
#define ADC2_CAL_CH2_3_GAIN_CH2_Msk (0xff00UL) |
ADC2 CAL_CH2_3: GAIN_CH2 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH2_3_GAIN_CH2_Pos (8UL) |
ADC2 CAL_CH2_3: GAIN_CH2 (Bit 8)
#define ADC2_CAL_CH2_3_GAIN_CH3_Msk (0xff000000UL) |
ADC2 CAL_CH2_3: GAIN_CH3 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH2_3_GAIN_CH3_Pos (24UL) |
ADC2 CAL_CH2_3: GAIN_CH3 (Bit 24)
#define ADC2_CAL_CH2_3_OFFS_CH2_Msk (0xffUL) |
ADC2 CAL_CH2_3: OFFS_CH2 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH2_3_OFFS_CH2_Pos (0UL) |
ADC2 CAL_CH2_3: OFFS_CH2 (Bit 0)
#define ADC2_CAL_CH2_3_OFFS_CH3_Msk (0xff0000UL) |
ADC2 CAL_CH2_3: OFFS_CH3 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH2_3_OFFS_CH3_Pos (16UL) |
ADC2 CAL_CH2_3: OFFS_CH3 (Bit 16)
#define ADC2_CAL_CH4_5_GAIN_CH4_Msk (0xff00UL) |
ADC2 CAL_CH4_5: GAIN_CH4 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH4_5_GAIN_CH4_Pos (8UL) |
ADC2 CAL_CH4_5: GAIN_CH4 (Bit 8)
#define ADC2_CAL_CH4_5_GAIN_CH5_Msk (0xff000000UL) |
ADC2 CAL_CH4_5: GAIN_CH5 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH4_5_GAIN_CH5_Pos (24UL) |
ADC2 CAL_CH4_5: GAIN_CH5 (Bit 24)
#define ADC2_CAL_CH4_5_OFFS_CH4_Msk (0xffUL) |
ADC2 CAL_CH4_5: OFFS_CH4 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH4_5_OFFS_CH4_Pos (0UL) |
ADC2 CAL_CH4_5: OFFS_CH4 (Bit 0)
#define ADC2_CAL_CH4_5_OFFS_CH5_Msk (0xff0000UL) |
ADC2 CAL_CH4_5: OFFS_CH5 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH4_5_OFFS_CH5_Pos (16UL) |
ADC2 CAL_CH4_5: OFFS_CH5 (Bit 16)
#define ADC2_CAL_CH6_7_GAIN_CH6_Msk (0xff00UL) |
ADC2 CAL_CH6_7: GAIN_CH6 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH6_7_GAIN_CH6_Pos (8UL) |
ADC2 CAL_CH6_7: GAIN_CH6 (Bit 8)
#define ADC2_CAL_CH6_7_GAIN_CH7_Msk (0xff000000UL) |
ADC2 CAL_CH6_7: GAIN_CH7 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH6_7_GAIN_CH7_Pos (24UL) |
ADC2 CAL_CH6_7: GAIN_CH7 (Bit 24)
#define ADC2_CAL_CH6_7_OFFS_CH6_Msk (0xffUL) |
ADC2 CAL_CH6_7: OFFS_CH6 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH6_7_OFFS_CH6_Pos (0UL) |
ADC2 CAL_CH6_7: OFFS_CH6 (Bit 0)
#define ADC2_CAL_CH6_7_OFFS_CH7_Msk (0xff0000UL) |
ADC2 CAL_CH6_7: OFFS_CH7 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH6_7_OFFS_CH7_Pos (16UL) |
ADC2 CAL_CH6_7: OFFS_CH7 (Bit 16)
#define ADC2_CAL_CH8_9_GAIN_CH8_Msk (0xff00UL) |
ADC2 CAL_CH8_9: GAIN_CH8 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH8_9_GAIN_CH8_Pos (8UL) |
ADC2 CAL_CH8_9: GAIN_CH8 (Bit 8)
#define ADC2_CAL_CH8_9_GAIN_CH9_Msk (0xff000000UL) |
ADC2 CAL_CH8_9: GAIN_CH9 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH8_9_GAIN_CH9_Pos (24UL) |
ADC2 CAL_CH8_9: GAIN_CH9 (Bit 24)
#define ADC2_CAL_CH8_9_OFFS_CH8_Msk (0xffUL) |
ADC2 CAL_CH8_9: OFFS_CH8 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH8_9_OFFS_CH8_Pos (0UL) |
ADC2 CAL_CH8_9: OFFS_CH8 (Bit 0)
#define ADC2_CAL_CH8_9_OFFS_CH9_Msk (0xff0000UL) |
ADC2 CAL_CH8_9: OFFS_CH9 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH8_9_OFFS_CH9_Pos (16UL) |
ADC2 CAL_CH8_9: OFFS_CH9 (Bit 16)
#define ADC2_CHx_EIM_CHx_Msk (0x1fUL) |
ADC2 CHx_EIM: CHx (Bitfield-Mask: 0x1f)
#define ADC2_CHx_EIM_CHx_Pos (0UL) |
ADC2 CHx_EIM: CHx (Bit 0)
#define ADC2_CHx_EIM_EN_Msk (0x800UL) |
ADC2 CHx_EIM: EN (Bitfield-Mask: 0x01)
#define ADC2_CHx_EIM_EN_Pos (11UL) |
ADC2 CHx_EIM: EN (Bit 11)
#define ADC2_CHx_EIM_REP_Msk (0x700UL) |
ADC2 CHx_EIM: REP (Bitfield-Mask: 0x07)
#define ADC2_CHx_EIM_REP_Pos (8UL) |
ADC2 CHx_EIM: REP (Bit 8)
#define ADC2_CHx_EIM_SEL_Msk (0x1000UL) |
ADC2 CHx_EIM: SEL (Bitfield-Mask: 0x01)
#define ADC2_CHx_EIM_SEL_Pos (12UL) |
ADC2 CHx_EIM: SEL (Bit 12)
#define ADC2_CHx_ESM_EN_Msk (0x10000UL) |
ADC2 CHx_ESM: EN (Bitfield-Mask: 0x01)
#define ADC2_CHx_ESM_EN_Pos (16UL) |
ADC2 CHx_ESM: EN (Bit 16)
#define ADC2_CHx_ESM_ESM_0_Msk (0x3fUL) |
ADC2 CHx_ESM: ESM_0 (Bitfield-Mask: 0x3f)
#define ADC2_CHx_ESM_ESM_0_Pos (0UL) |
ADC2 CHx_ESM: ESM_0 (Bit 0)
#define ADC2_CHx_ESM_ESM_1_Msk (0x3c0UL) |
ADC2 CHx_ESM: ESM_1 (Bitfield-Mask: 0x0f)
#define ADC2_CHx_ESM_ESM_1_Pos (6UL) |
ADC2 CHx_ESM: ESM_1 (Bit 6)
#define ADC2_CHx_ESM_SEL_Msk (0x400UL) |
ADC2 CHx_ESM: SEL (Bitfield-Mask: 0x01)
#define ADC2_CHx_ESM_SEL_Pos (10UL) |
ADC2 CHx_ESM: SEL (Bit 10)
#define ADC2_CHx_ESM_STS_Msk (0x20000UL) |
ADC2 CHx_ESM: STS (Bitfield-Mask: 0x01)
#define ADC2_CHx_ESM_STS_Pos (17UL) |
ADC2 CHx_ESM: STS (Bit 17)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Msk (0x7UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH0 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Pos (0UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH0 (Bit 0)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Msk (0x700UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH1 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Pos (8UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH1 (Bit 8)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Msk (0x70000UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH2 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Pos (16UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH2 (Bit 16)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Msk (0x7000000UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH3 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Pos (24UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH3 (Bit 24)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Msk (0x18UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH0 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Pos (3UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH0 (Bit 3)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Msk (0x1800UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH1 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Pos (11UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH1 (Bit 11)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Msk (0x180000UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH2 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Pos (19UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH2 (Bit 19)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Msk (0x18000000UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH3 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Pos (27UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH3 (Bit 27)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Msk (0x7UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH0 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Pos (0UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH0 (Bit 0)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Msk (0x700UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH1 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Pos (8UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH1 (Bit 8)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Msk (0x70000UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH2 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Pos (16UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH2 (Bit 16)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Msk (0x7000000UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH3 (Bitfield-Mask: 0x07)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Pos (24UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH3 (Bit 24)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Msk (0x18UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH0 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Pos (3UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH0 (Bit 3)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Msk (0x1800UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH1 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Pos (11UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH1 (Bit 11)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Msk (0x180000UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH2 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Pos (19UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH2 (Bit 19)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Msk (0x18000000UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH3 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Pos (27UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH3 (Bit 27)
#define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Msk (0x7UL) |
ADC2 CNT4_5_LOWER: CNT_LO_CH4 (Bitfield-Mask: 0x07)
#define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Pos (0UL) |
ADC2 CNT4_5_LOWER: CNT_LO_CH4 (Bit 0)
#define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Msk (0x700UL) |
ADC2 CNT4_5_LOWER: CNT_LO_CH5 (Bitfield-Mask: 0x07)
#define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Pos (8UL) |
ADC2 CNT4_5_LOWER: CNT_LO_CH5 (Bit 8)
#define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Msk (0x18UL) |
ADC2 CNT4_5_LOWER: HYST_LO_CH4 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Pos (3UL) |
ADC2 CNT4_5_LOWER: HYST_LO_CH4 (Bit 3)
#define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Msk (0x1800UL) |
ADC2 CNT4_5_LOWER: HYST_LO_CH5 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Pos (11UL) |
ADC2 CNT4_5_LOWER: HYST_LO_CH5 (Bit 11)
#define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Msk (0x7UL) |
ADC2 CNT4_5_UPPER: CNT_UP_CH4 (Bitfield-Mask: 0x07)
#define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Pos (0UL) |
ADC2 CNT4_5_UPPER: CNT_UP_CH4 (Bit 0)
#define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Msk (0x700UL) |
ADC2 CNT4_5_UPPER: CNT_UP_CH5 (Bitfield-Mask: 0x07)
#define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Pos (8UL) |
ADC2 CNT4_5_UPPER: CNT_UP_CH5 (Bit 8)
#define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Msk (0x18UL) |
ADC2 CNT4_5_UPPER: HYST_UP_CH4 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Pos (3UL) |
ADC2 CNT4_5_UPPER: HYST_UP_CH4 (Bit 3)
#define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Msk (0x1800UL) |
ADC2 CNT4_5_UPPER: HYST_UP_CH5 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Pos (11UL) |
ADC2 CNT4_5_UPPER: HYST_UP_CH5 (Bit 11)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Msk (0x7UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH6 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Pos (0UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH6 (Bit 0)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Msk (0x700UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH7 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Pos (8UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH7 (Bit 8)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Msk (0x70000UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH8 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Pos (16UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH8 (Bit 16)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Msk (0x7000000UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH9 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Pos (24UL) |
ADC2 CNT6_9_LOWER: CNT_LO_CH9 (Bit 24)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Msk (0x18UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH6 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Pos (3UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH6 (Bit 3)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Msk (0x1800UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH7 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Pos (11UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH7 (Bit 11)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Msk (0x180000UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH8 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Pos (19UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH8 (Bit 19)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Msk (0x18000000UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH9 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Pos (27UL) |
ADC2 CNT6_9_LOWER: HYST_LO_CH9 (Bit 27)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Msk (0x7UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH6 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Pos (0UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH6 (Bit 0)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Msk (0x700UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH7 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Pos (8UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH7 (Bit 8)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Msk (0x70000UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH8 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Pos (16UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH8 (Bit 16)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Msk (0x7000000UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH9 (Bitfield-Mask: 0x07)
#define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Pos (24UL) |
ADC2 CNT6_9_UPPER: CNT_UP_CH9 (Bit 24)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Msk (0x18UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH6 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Pos (3UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH6 (Bit 3)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Msk (0x1800UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH7 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Pos (11UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH7 (Bit 11)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Msk (0x180000UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH8 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Pos (19UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH8 (Bit 19)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Msk (0x18000000UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH9 (Bitfield-Mask: 0x03)
#define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Pos (27UL) |
ADC2 CNT6_9_UPPER: HYST_UP_CH9 (Bit 27)
#define ADC2_CTRL1_CALIB_EN_Msk (0x3fUL) |
ADC2 CTRL1: CALIB_EN (Bitfield-Mask: 0x3f)
#define ADC2_CTRL1_CALIB_EN_Pos (0UL) |
ADC2 CTRL1: CALIB_EN (Bit 0)
#define ADC2_CTRL2_MCM_PD_N_Msk (0x1UL) |
ADC2 CTRL2: MCM_PD_N (Bitfield-Mask: 0x01)
#define ADC2_CTRL2_MCM_PD_N_Pos (0UL) |
ADC2 CTRL2: MCM_PD_N (Bit 0)
#define ADC2_CTRL2_MCM_RDY_Msk (0x80UL) |
ADC2 CTRL2: MCM_RDY (Bitfield-Mask: 0x01)
#define ADC2_CTRL2_MCM_RDY_Pos (7UL) |
ADC2 CTRL2: MCM_RDY (Bit 7)
#define ADC2_CTRL2_SAMPLE_TIME_int_Msk (0xf00UL) |
ADC2 CTRL2: SAMPLE_TIME_int (Bitfield-Mask: 0x0f)
#define ADC2_CTRL2_SAMPLE_TIME_int_Pos (8UL) |
ADC2 CTRL2: SAMPLE_TIME_int (Bit 8)
#define ADC2_CTRL2_SEL_TS_COUNT_Msk (0xf0000UL) |
ADC2 CTRL2: SEL_TS_COUNT (Bitfield-Mask: 0x0f)
#define ADC2_CTRL2_SEL_TS_COUNT_Pos (16UL) |
ADC2 CTRL2: SEL_TS_COUNT (Bit 16)
#define ADC2_CTRL2_TS_SD_SEL_CONF_Msk (0x2UL) |
ADC2 CTRL2: TS_SD_SEL_CONF (Bitfield-Mask: 0x01)
#define ADC2_CTRL2_TS_SD_SEL_CONF_Pos (1UL) |
ADC2 CTRL2: TS_SD_SEL_CONF (Bit 1)
#define ADC2_CTRL2_TSENSE_SD_SEL_Msk (0x4UL) |
ADC2 CTRL2: TSENSE_SD_SEL (Bitfield-Mask: 0x01)
#define ADC2_CTRL2_TSENSE_SD_SEL_Pos (2UL) |
ADC2 CTRL2: TSENSE_SD_SEL (Bit 2)
#define ADC2_CTRL4_FILT_OUT_SEL_5_0_Msk (0x3fUL) |
ADC2 CTRL4: FILT_OUT_SEL_5_0 (Bitfield-Mask: 0x3f)
#define ADC2_CTRL4_FILT_OUT_SEL_5_0_Pos (0UL) |
ADC2 CTRL4: FILT_OUT_SEL_5_0 (Bit 0)
#define ADC2_CTRL4_FILT_OUT_SEL_9_6_Msk (0xf00UL) |
ADC2 CTRL4: FILT_OUT_SEL_9_6 (Bitfield-Mask: 0x0f)
#define ADC2_CTRL4_FILT_OUT_SEL_9_6_Pos (8UL) |
ADC2 CTRL4: FILT_OUT_SEL_9_6 (Bit 8)
#define ADC2_CTRL_STS_VBAT_RANGE_Msk (0x10000UL) |
ADC2 CTRL_STS: VBAT_RANGE (Bitfield-Mask: 0x01)
#define ADC2_CTRL_STS_VBAT_RANGE_Pos (16UL) |
ADC2 CTRL_STS: VBAT_RANGE (Bit 16)
#define ADC2_CTRL_STS_VS_RANGE_Msk (0x20000UL) |
ADC2 CTRL_STS: VS_RANGE (Bitfield-Mask: 0x01)
#define ADC2_CTRL_STS_VS_RANGE_Pos (17UL) |
ADC2 CTRL_STS: VS_RANGE (Bit 17)
#define ADC2_FILT_LO_CTRL_Ch0_EN_Msk (0x1UL) |
ADC2 FILT_LO_CTRL: Ch0_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_LO_CTRL_Ch0_EN_Pos (0UL) |
ADC2 FILT_LO_CTRL: Ch0_EN (Bit 0)
#define ADC2_FILT_LO_CTRL_Ch1_EN_Msk (0x2UL) |
ADC2 FILT_LO_CTRL: Ch1_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_LO_CTRL_Ch1_EN_Pos (1UL) |
ADC2 FILT_LO_CTRL: Ch1_EN (Bit 1)
#define ADC2_FILT_LO_CTRL_Ch2_EN_Msk (0x4UL) |
ADC2 FILT_LO_CTRL: Ch2_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_LO_CTRL_Ch2_EN_Pos (2UL) |
ADC2 FILT_LO_CTRL: Ch2_EN (Bit 2)
#define ADC2_FILT_LO_CTRL_Ch3_EN_Msk (0x8UL) |
ADC2 FILT_LO_CTRL: Ch3_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_LO_CTRL_Ch3_EN_Pos (3UL) |
ADC2 FILT_LO_CTRL: Ch3_EN (Bit 3)
#define ADC2_FILT_LO_CTRL_Ch4_EN_Msk (0x10UL) |
ADC2 FILT_LO_CTRL: Ch4_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_LO_CTRL_Ch4_EN_Pos (4UL) |
ADC2 FILT_LO_CTRL: Ch4_EN (Bit 4)
#define ADC2_FILT_LO_CTRL_Ch5_EN_Msk (0x20UL) |
ADC2 FILT_LO_CTRL: Ch5_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_LO_CTRL_Ch5_EN_Pos (5UL) |
ADC2 FILT_LO_CTRL: Ch5_EN (Bit 5)
#define ADC2_FILT_OUT0_OUT_CH0_Msk (0x3ffUL) |
ADC2 FILT_OUT0: OUT_CH0 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT0_OUT_CH0_Pos (0UL) |
ADC2 FILT_OUT0: OUT_CH0 (Bit 0)
#define ADC2_FILT_OUT1_OUT_CH1_Msk (0x3ffUL) |
ADC2 FILT_OUT1: OUT_CH1 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT1_OUT_CH1_Pos (0UL) |
ADC2 FILT_OUT1: OUT_CH1 (Bit 0)
#define ADC2_FILT_OUT2_OUT_CH2_Msk (0x3ffUL) |
ADC2 FILT_OUT2: OUT_CH2 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT2_OUT_CH2_Pos (0UL) |
ADC2 FILT_OUT2: OUT_CH2 (Bit 0)
#define ADC2_FILT_OUT3_OUT_CH3_Msk (0x3ffUL) |
ADC2 FILT_OUT3: OUT_CH3 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT3_OUT_CH3_Pos (0UL) |
ADC2 FILT_OUT3: OUT_CH3 (Bit 0)
#define ADC2_FILT_OUT4_OUT_CH4_Msk (0x3ffUL) |
ADC2 FILT_OUT4: OUT_CH4 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT4_OUT_CH4_Pos (0UL) |
ADC2 FILT_OUT4: OUT_CH4 (Bit 0)
#define ADC2_FILT_OUT5_OUT_CH5_Msk (0x3ffUL) |
ADC2 FILT_OUT5: OUT_CH5 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT5_OUT_CH5_Pos (0UL) |
ADC2 FILT_OUT5: OUT_CH5 (Bit 0)
#define ADC2_FILT_OUT6_OUT_CH6_Msk (0x3ffUL) |
ADC2 FILT_OUT6: OUT_CH6 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT6_OUT_CH6_Pos (0UL) |
ADC2 FILT_OUT6: OUT_CH6 (Bit 0)
#define ADC2_FILT_OUT7_OUT_CH7_Msk (0x3ffUL) |
ADC2 FILT_OUT7: OUT_CH7 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT7_OUT_CH7_Pos (0UL) |
ADC2 FILT_OUT7: OUT_CH7 (Bit 0)
#define ADC2_FILT_OUT8_OUT_CH8_Msk (0x3ffUL) |
ADC2 FILT_OUT8: OUT_CH8 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT8_OUT_CH8_Pos (0UL) |
ADC2 FILT_OUT8: OUT_CH8 (Bit 0)
#define ADC2_FILT_OUT9_OUT_CH9_Msk (0x3ffUL) |
ADC2 FILT_OUT9: OUT_CH9 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT9_OUT_CH9_Pos (0UL) |
ADC2 FILT_OUT9: OUT_CH9 (Bit 0)
#define ADC2_FILT_UP_CTRL_Ch0_EN_Msk (0x1UL) |
ADC2 FILT_UP_CTRL: Ch0_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_UP_CTRL_Ch0_EN_Pos (0UL) |
ADC2 FILT_UP_CTRL: Ch0_EN (Bit 0)
#define ADC2_FILT_UP_CTRL_Ch1_EN_Msk (0x2UL) |
ADC2 FILT_UP_CTRL: Ch1_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_UP_CTRL_Ch1_EN_Pos (1UL) |
ADC2 FILT_UP_CTRL: Ch1_EN (Bit 1)
#define ADC2_FILT_UP_CTRL_Ch2_EN_Msk (0x4UL) |
ADC2 FILT_UP_CTRL: Ch2_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_UP_CTRL_Ch2_EN_Pos (2UL) |
ADC2 FILT_UP_CTRL: Ch2_EN (Bit 2)
#define ADC2_FILT_UP_CTRL_Ch3_EN_Msk (0x8UL) |
ADC2 FILT_UP_CTRL: Ch3_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_UP_CTRL_Ch3_EN_Pos (3UL) |
ADC2 FILT_UP_CTRL: Ch3_EN (Bit 3)
#define ADC2_FILT_UP_CTRL_Ch4_EN_Msk (0x10UL) |
ADC2 FILT_UP_CTRL: Ch4_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_UP_CTRL_Ch4_EN_Pos (4UL) |
ADC2 FILT_UP_CTRL: Ch4_EN (Bit 4)
#define ADC2_FILT_UP_CTRL_Ch5_EN_Msk (0x20UL) |
ADC2 FILT_UP_CTRL: Ch5_EN (Bitfield-Mask: 0x01)
#define ADC2_FILT_UP_CTRL_Ch5_EN_Pos (5UL) |
ADC2 FILT_UP_CTRL: Ch5_EN (Bit 5)
#define ADC2_FILTCOEFF0_5_CH0_Msk (0x3UL) |
ADC2 FILTCOEFF0_5: CH0 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_5_CH0_Pos (0UL) |
ADC2 FILTCOEFF0_5: CH0 (Bit 0)
#define ADC2_FILTCOEFF0_5_CH1_Msk (0xcUL) |
ADC2 FILTCOEFF0_5: CH1 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_5_CH1_Pos (2UL) |
ADC2 FILTCOEFF0_5: CH1 (Bit 2)
#define ADC2_FILTCOEFF0_5_CH2_Msk (0x30UL) |
ADC2 FILTCOEFF0_5: CH2 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_5_CH2_Pos (4UL) |
ADC2 FILTCOEFF0_5: CH2 (Bit 4)
#define ADC2_FILTCOEFF0_5_CH3_Msk (0xc0UL) |
ADC2 FILTCOEFF0_5: CH3 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_5_CH3_Pos (6UL) |
ADC2 FILTCOEFF0_5: CH3 (Bit 6)
#define ADC2_FILTCOEFF0_5_CH4_Msk (0x300UL) |
ADC2 FILTCOEFF0_5: CH4 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_5_CH4_Pos (8UL) |
ADC2 FILTCOEFF0_5: CH4 (Bit 8)
#define ADC2_FILTCOEFF0_5_CH5_Msk (0xc00UL) |
ADC2 FILTCOEFF0_5: CH5 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_5_CH5_Pos (10UL) |
ADC2 FILTCOEFF0_5: CH5 (Bit 10)
#define ADC2_FILTCOEFF6_9_CH6_Msk (0x3UL) |
ADC2 FILTCOEFF6_9: CH6 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF6_9_CH6_Pos (0UL) |
ADC2 FILTCOEFF6_9: CH6 (Bit 0)
#define ADC2_FILTCOEFF6_9_CH7_Msk (0xcUL) |
ADC2 FILTCOEFF6_9: CH7 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF6_9_CH7_Pos (2UL) |
ADC2 FILTCOEFF6_9: CH7 (Bit 2)
#define ADC2_FILTCOEFF6_9_CH8_Msk (0x30UL) |
ADC2 FILTCOEFF6_9: CH8 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF6_9_CH8_Pos (4UL) |
ADC2 FILTCOEFF6_9: CH8 (Bit 4)
#define ADC2_FILTCOEFF6_9_CH9_Msk (0xc0UL) |
ADC2 FILTCOEFF6_9: CH9 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF6_9_CH9_Pos (6UL) |
ADC2 FILTCOEFF6_9: CH9 (Bit 6)
#define ADC2_HV_STS_READY_Msk (0x2UL) |
ADC2 HV_STS: READY (Bitfield-Mask: 0x01)
#define ADC2_HV_STS_READY_Pos (1UL) |
ADC2 HV_STS: READY (Bit 1)
#define ADC2_MMODE0_5_Ch0_Msk (0x3UL) |
ADC2 MMODE0_5: Ch0 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_5_Ch0_Pos (0UL) |
ADC2 MMODE0_5: Ch0 (Bit 0)
#define ADC2_MMODE0_5_Ch1_Msk (0xcUL) |
ADC2 MMODE0_5: Ch1 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_5_Ch1_Pos (2UL) |
ADC2 MMODE0_5: Ch1 (Bit 2)
#define ADC2_MMODE0_5_Ch2_Msk (0x30UL) |
ADC2 MMODE0_5: Ch2 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_5_Ch2_Pos (4UL) |
ADC2 MMODE0_5: Ch2 (Bit 4)
#define ADC2_MMODE0_5_Ch3_Msk (0xc0UL) |
ADC2 MMODE0_5: Ch3 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_5_Ch3_Pos (6UL) |
ADC2 MMODE0_5: Ch3 (Bit 6)
#define ADC2_MMODE0_5_Ch4_Msk (0x300UL) |
ADC2 MMODE0_5: Ch4 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_5_Ch4_Pos (8UL) |
ADC2 MMODE0_5: Ch4 (Bit 8)
#define ADC2_MMODE0_5_Ch5_Msk (0xc00UL) |
ADC2 MMODE0_5: Ch5 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_5_Ch5_Pos (10UL) |
ADC2 MMODE0_5: Ch5 (Bit 10)
#define ADC2_SQ1_4_SQ1_Msk (0x3fUL) |
ADC2 SQ1_4: SQ1 (Bitfield-Mask: 0x3f)
#define ADC2_SQ1_4_SQ1_Pos (0UL) |
ADC2 SQ1_4: SQ1 (Bit 0)
#define ADC2_SQ1_4_SQ2_Msk (0x3f00UL) |
ADC2 SQ1_4: SQ2 (Bitfield-Mask: 0x3f)
#define ADC2_SQ1_4_SQ2_Pos (8UL) |
ADC2 SQ1_4: SQ2 (Bit 8)
#define ADC2_SQ1_4_SQ3_Msk (0x3f0000UL) |
ADC2 SQ1_4: SQ3 (Bitfield-Mask: 0x3f)
#define ADC2_SQ1_4_SQ3_Pos (16UL) |
ADC2 SQ1_4: SQ3 (Bit 16)
#define ADC2_SQ1_4_SQ4_Msk (0x3f000000UL) |
ADC2 SQ1_4: SQ4 (Bitfield-Mask: 0x3f)
#define ADC2_SQ1_4_SQ4_Pos (24UL) |
ADC2 SQ1_4: SQ4 (Bit 24)
#define ADC2_SQ1_8_int_SQ1_int_Msk (0xfUL) |
ADC2 SQ1_8_int: SQ1_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ1_int_Pos (0UL) |
ADC2 SQ1_8_int: SQ1_int (Bit 0)
#define ADC2_SQ1_8_int_SQ2_int_Msk (0xf0UL) |
ADC2 SQ1_8_int: SQ2_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ2_int_Pos (4UL) |
ADC2 SQ1_8_int: SQ2_int (Bit 4)
#define ADC2_SQ1_8_int_SQ3_int_Msk (0xf00UL) |
ADC2 SQ1_8_int: SQ3_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ3_int_Pos (8UL) |
ADC2 SQ1_8_int: SQ3_int (Bit 8)
#define ADC2_SQ1_8_int_SQ4_int_Msk (0xf000UL) |
ADC2 SQ1_8_int: SQ4_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ4_int_Pos (12UL) |
ADC2 SQ1_8_int: SQ4_int (Bit 12)
#define ADC2_SQ1_8_int_SQ5_int_Msk (0xf0000UL) |
ADC2 SQ1_8_int: SQ5_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ5_int_Pos (16UL) |
ADC2 SQ1_8_int: SQ5_int (Bit 16)
#define ADC2_SQ1_8_int_SQ6_int_Msk (0xf00000UL) |
ADC2 SQ1_8_int: SQ6_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ6_int_Pos (20UL) |
ADC2 SQ1_8_int: SQ6_int (Bit 20)
#define ADC2_SQ1_8_int_SQ7_int_Msk (0xf000000UL) |
ADC2 SQ1_8_int: SQ7_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ7_int_Pos (24UL) |
ADC2 SQ1_8_int: SQ7_int (Bit 24)
#define ADC2_SQ1_8_int_SQ8_int_Msk (0xf0000000UL) |
ADC2 SQ1_8_int: SQ8_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ1_8_int_SQ8_int_Pos (28UL) |
ADC2 SQ1_8_int: SQ8_int (Bit 28)
#define ADC2_SQ5_8_SQ5_Msk (0x3fUL) |
ADC2 SQ5_8: SQ5 (Bitfield-Mask: 0x3f)
#define ADC2_SQ5_8_SQ5_Pos (0UL) |
ADC2 SQ5_8: SQ5 (Bit 0)
#define ADC2_SQ5_8_SQ6_Msk (0x3f00UL) |
ADC2 SQ5_8: SQ6 (Bitfield-Mask: 0x3f)
#define ADC2_SQ5_8_SQ6_Pos (8UL) |
ADC2 SQ5_8: SQ6 (Bit 8)
#define ADC2_SQ5_8_SQ7_Msk (0x3f0000UL) |
ADC2 SQ5_8: SQ7 (Bitfield-Mask: 0x3f)
#define ADC2_SQ5_8_SQ7_Pos (16UL) |
ADC2 SQ5_8: SQ7 (Bit 16)
#define ADC2_SQ5_8_SQ8_Msk (0x3f000000UL) |
ADC2 SQ5_8: SQ8 (Bitfield-Mask: 0x3f)
#define ADC2_SQ5_8_SQ8_Pos (24UL) |
ADC2 SQ5_8: SQ8 (Bit 24)
#define ADC2_SQ9_10_int_SQ10_int_Msk (0xf0UL) |
ADC2 SQ9_10_int: SQ10_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ9_10_int_SQ10_int_Pos (4UL) |
ADC2 SQ9_10_int: SQ10_int (Bit 4)
#define ADC2_SQ9_10_int_SQ9_int_Msk (0xfUL) |
ADC2 SQ9_10_int: SQ9_int (Bitfield-Mask: 0x0f)
#define ADC2_SQ9_10_int_SQ9_int_Pos (0UL) |
ADC2 SQ9_10_int: SQ9_int (Bit 0)
#define ADC2_SQ9_10_SQ10_Msk (0x3f00UL) |
ADC2 SQ9_10: SQ10 (Bitfield-Mask: 0x3f)
#define ADC2_SQ9_10_SQ10_Pos (8UL) |
ADC2 SQ9_10: SQ10 (Bit 8)
#define ADC2_SQ9_10_SQ9_Msk (0x3fUL) |
ADC2 SQ9_10: SQ9 (Bitfield-Mask: 0x3f)
#define ADC2_SQ9_10_SQ9_Pos (0UL) |
ADC2 SQ9_10: SQ9 (Bit 0)
#define ADC2_SQ_FB_CHx_Msk (0x1f0000UL) |
ADC2 SQ_FB: CHx (Bitfield-Mask: 0x1f)
#define ADC2_SQ_FB_CHx_Pos (16UL) |
ADC2 SQ_FB: CHx (Bit 16)
#define ADC2_SQ_FB_EIM_ACTIVE_Msk (0x200UL) |
ADC2 SQ_FB: EIM_ACTIVE (Bitfield-Mask: 0x01)
#define ADC2_SQ_FB_EIM_ACTIVE_Pos (9UL) |
ADC2 SQ_FB: EIM_ACTIVE (Bit 9)
#define ADC2_SQ_FB_ESM_ACTIVE_Msk (0x400UL) |
ADC2 SQ_FB: ESM_ACTIVE (Bitfield-Mask: 0x01)
#define ADC2_SQ_FB_ESM_ACTIVE_Pos (10UL) |
ADC2 SQ_FB: ESM_ACTIVE (Bit 10)
#define ADC2_SQ_FB_SQ_FB_Msk (0xfUL) |
ADC2 SQ_FB: SQ_FB (Bitfield-Mask: 0x0f)
#define ADC2_SQ_FB_SQ_FB_Pos (0UL) |
ADC2 SQ_FB: SQ_FB (Bit 0)
#define ADC2_SQ_FB_SQ_STOP_Msk (0x100UL) |
ADC2 SQ_FB: SQ_STOP (Bitfield-Mask: 0x01)
#define ADC2_SQ_FB_SQ_STOP_Pos (8UL) |
ADC2 SQ_FB: SQ_STOP (Bit 8)
#define ADC2_SQ_FB_SQx_Msk (0x7800UL) |
ADC2 SQ_FB: SQx (Bitfield-Mask: 0x0f)
#define ADC2_SQ_FB_SQx_Pos (11UL) |
ADC2 SQ_FB: SQx (Bit 11)
#define ADC2_TH0_3_LOWER_CH0_Msk (0xffUL) |
ADC2 TH0_3_LOWER: CH0 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_CH0_Pos (0UL) |
ADC2 TH0_3_LOWER: CH0 (Bit 0)
#define ADC2_TH0_3_LOWER_CH1_Msk (0xff00UL) |
ADC2 TH0_3_LOWER: CH1 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_CH1_Pos (8UL) |
ADC2 TH0_3_LOWER: CH1 (Bit 8)
#define ADC2_TH0_3_LOWER_CH2_Msk (0xff0000UL) |
ADC2 TH0_3_LOWER: CH2 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_CH2_Pos (16UL) |
ADC2 TH0_3_LOWER: CH2 (Bit 16)
#define ADC2_TH0_3_LOWER_CH3_Msk (0xff000000UL) |
ADC2 TH0_3_LOWER: CH3 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_CH3_Pos (24UL) |
ADC2 TH0_3_LOWER: CH3 (Bit 24)
#define ADC2_TH0_3_UPPER_CH0_Msk (0xffUL) |
ADC2 TH0_3_UPPER: CH0 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_CH0_Pos (0UL) |
ADC2 TH0_3_UPPER: CH0 (Bit 0)
#define ADC2_TH0_3_UPPER_CH1_Msk (0xff00UL) |
ADC2 TH0_3_UPPER: CH1 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_CH1_Pos (8UL) |
ADC2 TH0_3_UPPER: CH1 (Bit 8)
#define ADC2_TH0_3_UPPER_CH2_Msk (0xff0000UL) |
ADC2 TH0_3_UPPER: CH2 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_CH2_Pos (16UL) |
ADC2 TH0_3_UPPER: CH2 (Bit 16)
#define ADC2_TH0_3_UPPER_CH3_Msk (0xff000000UL) |
ADC2 TH0_3_UPPER: CH3 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_CH3_Pos (24UL) |
ADC2 TH0_3_UPPER: CH3 (Bit 24)
#define ADC2_TH4_5_LOWER_CH4_Msk (0xffUL) |
ADC2 TH4_5_LOWER: CH4 (Bitfield-Mask: 0xff)
#define ADC2_TH4_5_LOWER_CH4_Pos (0UL) |
ADC2 TH4_5_LOWER: CH4 (Bit 0)
#define ADC2_TH4_5_LOWER_CH5_Msk (0xff00UL) |
ADC2 TH4_5_LOWER: CH5 (Bitfield-Mask: 0xff)
#define ADC2_TH4_5_LOWER_CH5_Pos (8UL) |
ADC2 TH4_5_LOWER: CH5 (Bit 8)
#define ADC2_TH4_5_UPPER_CH4_Msk (0xffUL) |
ADC2 TH4_5_UPPER: CH4 (Bitfield-Mask: 0xff)
#define ADC2_TH4_5_UPPER_CH4_Pos (0UL) |
ADC2 TH4_5_UPPER: CH4 (Bit 0)
#define ADC2_TH4_5_UPPER_CH5_Msk (0xff00UL) |
ADC2 TH4_5_UPPER: CH5 (Bitfield-Mask: 0xff)
#define ADC2_TH4_5_UPPER_CH5_Pos (8UL) |
ADC2 TH4_5_UPPER: CH5 (Bit 8)
#define ADC2_TH6_9_LOWER_CH6_Msk (0xffUL) |
ADC2 TH6_9_LOWER: CH6 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_LOWER_CH6_Pos (0UL) |
ADC2 TH6_9_LOWER: CH6 (Bit 0)
#define ADC2_TH6_9_LOWER_CH7_Msk (0xff00UL) |
ADC2 TH6_9_LOWER: CH7 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_LOWER_CH7_Pos (8UL) |
ADC2 TH6_9_LOWER: CH7 (Bit 8)
#define ADC2_TH6_9_LOWER_CH8_Msk (0xff0000UL) |
ADC2 TH6_9_LOWER: CH8 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_LOWER_CH8_Pos (16UL) |
ADC2 TH6_9_LOWER: CH8 (Bit 16)
#define ADC2_TH6_9_LOWER_CH9_Msk (0xff000000UL) |
ADC2 TH6_9_LOWER: CH9 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_LOWER_CH9_Pos (24UL) |
ADC2 TH6_9_LOWER: CH9 (Bit 24)
#define ADC2_TH6_9_UPPER_CH6_Msk (0xffUL) |
ADC2 TH6_9_UPPER: CH6 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_UPPER_CH6_Pos (0UL) |
ADC2 TH6_9_UPPER: CH6 (Bit 0)
#define ADC2_TH6_9_UPPER_CH7_Msk (0xff00UL) |
ADC2 TH6_9_UPPER: CH7 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_UPPER_CH7_Pos (8UL) |
ADC2 TH6_9_UPPER: CH7 (Bit 8)
#define ADC2_TH6_9_UPPER_CH8_Msk (0xff0000UL) |
ADC2 TH6_9_UPPER: CH8 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_UPPER_CH8_Pos (16UL) |
ADC2 TH6_9_UPPER: CH8 (Bit 16)
#define ADC2_TH6_9_UPPER_CH9_Msk (0xff000000UL) |
ADC2 TH6_9_UPPER: CH9 (Bitfield-Mask: 0xff)
#define ADC2_TH6_9_UPPER_CH9_Pos (24UL) |
ADC2 TH6_9_UPPER: CH9 (Bit 24)
#define ADC34_CTRL_STS_ADC34_DITHEN_Msk (0x800000UL) |
ADC34 CTRL_STS: ADC34_DITHEN (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC34_DITHEN_Pos (23UL) |
ADC34 CTRL_STS: ADC34_DITHEN (Bit 23)
#define ADC34_CTRL_STS_ADC34_DITHVAL_Msk (0xf000000UL) |
ADC34 CTRL_STS: ADC34_DITHVAL (Bitfield-Mask: 0x0f)
#define ADC34_CTRL_STS_ADC34_DITHVAL_Pos (24UL) |
ADC34 CTRL_STS: ADC34_DITHVAL (Bit 24)
#define ADC34_CTRL_STS_ADC34_DREQ_SEL_Msk (0x60UL) |
ADC34 CTRL_STS: ADC34_DREQ_SEL (Bitfield-Mask: 0x03)
#define ADC34_CTRL_STS_ADC34_DREQ_SEL_Pos (5UL) |
ADC34 CTRL_STS: ADC34_DREQ_SEL (Bit 5)
#define ADC34_CTRL_STS_ADC34_EoC_CNT_Msk (0x600000UL) |
ADC34 CTRL_STS: ADC34_EoC_CNT (Bitfield-Mask: 0x03)
#define ADC34_CTRL_STS_ADC34_EoC_CNT_Pos (21UL) |
ADC34 CTRL_STS: ADC34_EoC_CNT (Bit 21)
#define ADC34_CTRL_STS_ADC34_REF_SEL_Msk (0x800UL) |
ADC34 CTRL_STS: ADC34_REF_SEL (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC34_REF_SEL_Pos (11UL) |
ADC34 CTRL_STS: ADC34_REF_SEL (Bit 11)
#define ADC34_CTRL_STS_ADC3_EN_Msk (0x1UL) |
ADC34 CTRL_STS: ADC3_EN (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC3_EN_Pos (0UL) |
ADC34 CTRL_STS: ADC3_EN (Bit 0)
#define ADC34_CTRL_STS_ADC3_EoC_STS_Msk (0x10UL) |
ADC34 CTRL_STS: ADC3_EoC_STS (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC3_EoC_STS_Pos (4UL) |
ADC34 CTRL_STS: ADC3_EoC_STS (Bit 4)
#define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Msk (0x2UL) |
ADC34 CTRL_STS: ADC3_OFS_MEAS_EN (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Pos (1UL) |
ADC34 CTRL_STS: ADC3_OFS_MEAS_EN (Bit 1)
#define ADC34_CTRL_STS_ADC3_OSR_Msk (0xf000UL) |
ADC34 CTRL_STS: ADC3_OSR (Bitfield-Mask: 0x0f)
#define ADC34_CTRL_STS_ADC3_OSR_Pos (12UL) |
ADC34 CTRL_STS: ADC3_OSR (Bit 12)
#define ADC34_CTRL_STS_ADC3_SOC_Msk (0x4UL) |
ADC34 CTRL_STS: ADC3_SOC (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC3_SOC_Pos (2UL) |
ADC34 CTRL_STS: ADC3_SOC (Bit 2)
#define ADC34_CTRL_STS_ADC4_EN_Msk (0x10000UL) |
ADC34 CTRL_STS: ADC4_EN (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC4_EN_Pos (16UL) |
ADC34 CTRL_STS: ADC4_EN (Bit 16)
#define ADC34_CTRL_STS_ADC4_EoC_STS_Msk (0x100000UL) |
ADC34 CTRL_STS: ADC4_EoC_STS (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC4_EoC_STS_Pos (20UL) |
ADC34 CTRL_STS: ADC4_EoC_STS (Bit 20)
#define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Msk (0x20000UL) |
ADC34 CTRL_STS: ADC4_OFS_MEAS_EN (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Pos (17UL) |
ADC34 CTRL_STS: ADC4_OFS_MEAS_EN (Bit 17)
#define ADC34_CTRL_STS_ADC4_OSR_Msk (0xf0000000UL) |
ADC34 CTRL_STS: ADC4_OSR (Bitfield-Mask: 0x0f)
#define ADC34_CTRL_STS_ADC4_OSR_Pos (28UL) |
ADC34 CTRL_STS: ADC4_OSR (Bit 28)
#define ADC34_CTRL_STS_ADC4_SOC_Msk (0x40000UL) |
ADC34 CTRL_STS: ADC4_SOC (Bitfield-Mask: 0x01)
#define ADC34_CTRL_STS_ADC4_SOC_Pos (18UL) |
ADC34 CTRL_STS: ADC4_SOC (Bit 18)
#define ADC34_RESU_ADC3_RESU_Msk (0xffffUL) |
ADC34 RESU: ADC3_RESU (Bitfield-Mask: 0xffff)
#define ADC34_RESU_ADC3_RESU_Pos (0UL) |
ADC34 RESU: ADC3_RESU (Bit 0)
#define ADC34_RESU_ADC4_RESU_Msk (0xffff0000UL) |
ADC34 RESU: ADC4_RESU (Bitfield-Mask: 0xffff)
#define ADC34_RESU_ADC4_RESU_Pos (16UL) |
ADC34 RESU: ADC4_RESU (Bit 16)
#define BDRV_CP_CLK_CTRL_CPCLK_EN_Msk (0x8000UL) |
BDRV CP_CLK_CTRL: CPCLK_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CLK_CTRL_CPCLK_EN_Pos (15UL) |
BDRV CP_CLK_CTRL: CPCLK_EN (Bit 15)
#define BDRV_CP_CLK_CTRL_DITH_LOWER_Msk (0x1fUL) |
BDRV CP_CLK_CTRL: DITH_LOWER (Bitfield-Mask: 0x1f)
#define BDRV_CP_CLK_CTRL_DITH_LOWER_Pos (0UL) |
BDRV CP_CLK_CTRL: DITH_LOWER (Bit 0)
#define BDRV_CP_CLK_CTRL_DITH_UPPER_Msk (0x1f00UL) |
BDRV CP_CLK_CTRL: DITH_UPPER (Bitfield-Mask: 0x1f)
#define BDRV_CP_CLK_CTRL_DITH_UPPER_Pos (8UL) |
BDRV CP_CLK_CTRL: DITH_UPPER (Bit 8)
#define BDRV_CP_CLK_CTRL_F_CP_Msk (0x6000UL) |
BDRV CP_CLK_CTRL: F_CP (Bitfield-Mask: 0x03)
#define BDRV_CP_CLK_CTRL_F_CP_Pos (13UL) |
BDRV CP_CLK_CTRL: F_CP (Bit 13)
#define BDRV_CP_CTRL_STS_CP_EN_Msk (0x1UL) |
BDRV CP_CTRL_STS: CP_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_CP_EN_Pos (0UL) |
BDRV CP_CTRL_STS: CP_EN (Bit 0)
#define BDRV_CP_CTRL_STS_CP_RDY_EN_Msk (0x4UL) |
BDRV CP_CTRL_STS: CP_RDY_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_CP_RDY_EN_Pos (2UL) |
BDRV CP_CTRL_STS: CP_RDY_EN (Bit 2)
#define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Msk (0x1000000UL) |
BDRV CP_CTRL_STS: CPLOPWRM_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Pos (24UL) |
BDRV CP_CTRL_STS: CPLOPWRM_EN (Bit 24)
#define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Msk (0x10000UL) |
BDRV CP_CTRL_STS: DRVx_VCPLO_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Pos (16UL) |
BDRV CP_CTRL_STS: DRVx_VCPLO_DIS (Bit 16)
#define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Msk (0x40000UL) |
BDRV CP_CTRL_STS: DRVx_VCPUP_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Pos (18UL) |
BDRV CP_CTRL_STS: DRVx_VCPUP_DIS (Bit 18)
#define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Msk (0x100000UL) |
BDRV CP_CTRL_STS: DRVx_VSDLO_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Pos (20UL) |
BDRV CP_CTRL_STS: DRVx_VSDLO_DIS (Bit 20)
#define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Msk (0x400000UL) |
BDRV CP_CTRL_STS: DRVx_VSDUP_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Pos (22UL) |
BDRV CP_CTRL_STS: DRVx_VSDUP_DIS (Bit 22)
#define BDRV_CP_CTRL_STS_VCP9V_SET_Msk (0x2000000UL) |
BDRV CP_CTRL_STS: VCP9V_SET (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_VCP9V_SET_Pos (25UL) |
BDRV CP_CTRL_STS: VCP9V_SET (Bit 25)
#define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Msk (0x20000UL) |
BDRV CP_CTRL_STS: VCP_LOTH1_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Pos (17UL) |
BDRV CP_CTRL_STS: VCP_LOTH1_STS (Bit 17)
#define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Msk (0x20UL) |
BDRV CP_CTRL_STS: VCP_LOTH2_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Pos (5UL) |
BDRV CP_CTRL_STS: VCP_LOTH2_STS (Bit 5)
#define BDRV_CP_CTRL_STS_VCP_LOWTH2_Msk (0x700UL) |
BDRV CP_CTRL_STS: VCP_LOWTH2 (Bitfield-Mask: 0x07)
#define BDRV_CP_CTRL_STS_VCP_LOWTH2_Pos (8UL) |
BDRV CP_CTRL_STS: VCP_LOWTH2 (Bit 8)
#define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Msk (0x80000UL) |
BDRV CP_CTRL_STS: VCP_UPTH_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Pos (19UL) |
BDRV CP_CTRL_STS: VCP_UPTH_STS (Bit 19)
#define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Msk (0x200000UL) |
BDRV CP_CTRL_STS: VSD_LOTH_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Pos (21UL) |
BDRV CP_CTRL_STS: VSD_LOTH_STS (Bit 21)
#define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Msk (0x800000UL) |
BDRV CP_CTRL_STS: VSD_UPTH_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Pos (23UL) |
BDRV CP_CTRL_STS: VSD_UPTH_STS (Bit 23)
#define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Msk (0xc000000UL) |
BDRV CP_CTRL_STS: VTHVCP9V_TRIM (Bitfield-Mask: 0x03)
#define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Pos (26UL) |
BDRV CP_CTRL_STS: VTHVCP9V_TRIM (Bit 26)
#define BDRV_CTRL1_HS1_DCS_EN_Msk (0x80000UL) |
BDRV CTRL1: HS1_DCS_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_DCS_EN_Pos (19UL) |
BDRV CTRL1: HS1_DCS_EN (Bit 19)
#define BDRV_CTRL1_HS1_DS_STS_Msk (0x100000UL) |
BDRV CTRL1: HS1_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_DS_STS_Pos (20UL) |
BDRV CTRL1: HS1_DS_STS (Bit 20)
#define BDRV_CTRL1_HS1_EN_Msk (0x10000UL) |
BDRV CTRL1: HS1_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_EN_Pos (16UL) |
BDRV CTRL1: HS1_EN (Bit 16)
#define BDRV_CTRL1_HS1_OC_DIS_Msk (0x800000UL) |
BDRV CTRL1: HS1_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_OC_DIS_Pos (23UL) |
BDRV CTRL1: HS1_OC_DIS (Bit 23)
#define BDRV_CTRL1_HS1_OC_STS_Msk (0x400000UL) |
BDRV CTRL1: HS1_OC_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_OC_STS_Pos (22UL) |
BDRV CTRL1: HS1_OC_STS (Bit 22)
#define BDRV_CTRL1_HS1_ON_Msk (0x40000UL) |
BDRV CTRL1: HS1_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_ON_Pos (18UL) |
BDRV CTRL1: HS1_ON (Bit 18)
#define BDRV_CTRL1_HS1_PWM_Msk (0x20000UL) |
BDRV CTRL1: HS1_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_PWM_Pos (17UL) |
BDRV CTRL1: HS1_PWM (Bit 17)
#define BDRV_CTRL1_HS1_SUPERR_STS_Msk (0x200000UL) |
BDRV CTRL1: HS1_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_SUPERR_STS_Pos (21UL) |
BDRV CTRL1: HS1_SUPERR_STS (Bit 21)
#define BDRV_CTRL1_HS2_DCS_EN_Msk (0x8000000UL) |
BDRV CTRL1: HS2_DCS_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_DCS_EN_Pos (27UL) |
BDRV CTRL1: HS2_DCS_EN (Bit 27)
#define BDRV_CTRL1_HS2_DS_STS_Msk (0x10000000UL) |
BDRV CTRL1: HS2_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_DS_STS_Pos (28UL) |
BDRV CTRL1: HS2_DS_STS (Bit 28)
#define BDRV_CTRL1_HS2_EN_Msk (0x1000000UL) |
BDRV CTRL1: HS2_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_EN_Pos (24UL) |
BDRV CTRL1: HS2_EN (Bit 24)
#define BDRV_CTRL1_HS2_OC_DIS_Msk (0x80000000UL) |
BDRV CTRL1: HS2_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_OC_DIS_Pos (31UL) |
BDRV CTRL1: HS2_OC_DIS (Bit 31)
#define BDRV_CTRL1_HS2_OC_STS_Msk (0x40000000UL) |
BDRV CTRL1: HS2_OC_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_OC_STS_Pos (30UL) |
BDRV CTRL1: HS2_OC_STS (Bit 30)
#define BDRV_CTRL1_HS2_ON_Msk (0x4000000UL) |
BDRV CTRL1: HS2_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_ON_Pos (26UL) |
BDRV CTRL1: HS2_ON (Bit 26)
#define BDRV_CTRL1_HS2_PWM_Msk (0x2000000UL) |
BDRV CTRL1: HS2_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_PWM_Pos (25UL) |
BDRV CTRL1: HS2_PWM (Bit 25)
#define BDRV_CTRL1_HS2_SUPERR_STS_Msk (0x20000000UL) |
BDRV CTRL1: HS2_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_SUPERR_STS_Pos (29UL) |
BDRV CTRL1: HS2_SUPERR_STS (Bit 29)
#define BDRV_CTRL1_LS1_DCS_EN_Msk (0x8UL) |
BDRV CTRL1: LS1_DCS_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_DCS_EN_Pos (3UL) |
BDRV CTRL1: LS1_DCS_EN (Bit 3)
#define BDRV_CTRL1_LS1_DS_STS_Msk (0x10UL) |
BDRV CTRL1: LS1_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_DS_STS_Pos (4UL) |
BDRV CTRL1: LS1_DS_STS (Bit 4)
#define BDRV_CTRL1_LS1_EN_Msk (0x1UL) |
BDRV CTRL1: LS1_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_EN_Pos (0UL) |
BDRV CTRL1: LS1_EN (Bit 0)
#define BDRV_CTRL1_LS1_OC_DIS_Msk (0x80UL) |
BDRV CTRL1: LS1_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_OC_DIS_Pos (7UL) |
BDRV CTRL1: LS1_OC_DIS (Bit 7)
#define BDRV_CTRL1_LS1_OC_STS_Msk (0x40UL) |
BDRV CTRL1: LS1_OC_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_OC_STS_Pos (6UL) |
BDRV CTRL1: LS1_OC_STS (Bit 6)
#define BDRV_CTRL1_LS1_ON_Msk (0x4UL) |
BDRV CTRL1: LS1_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_ON_Pos (2UL) |
BDRV CTRL1: LS1_ON (Bit 2)
#define BDRV_CTRL1_LS1_PWM_Msk (0x2UL) |
BDRV CTRL1: LS1_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_PWM_Pos (1UL) |
BDRV CTRL1: LS1_PWM (Bit 1)
#define BDRV_CTRL1_LS1_SUPERR_STS_Msk (0x20UL) |
BDRV CTRL1: LS1_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_SUPERR_STS_Pos (5UL) |
BDRV CTRL1: LS1_SUPERR_STS (Bit 5)
#define BDRV_CTRL1_LS2_DCS_EN_Msk (0x800UL) |
BDRV CTRL1: LS2_DCS_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_DCS_EN_Pos (11UL) |
BDRV CTRL1: LS2_DCS_EN (Bit 11)
#define BDRV_CTRL1_LS2_DS_STS_Msk (0x1000UL) |
BDRV CTRL1: LS2_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_DS_STS_Pos (12UL) |
BDRV CTRL1: LS2_DS_STS (Bit 12)
#define BDRV_CTRL1_LS2_EN_Msk (0x100UL) |
BDRV CTRL1: LS2_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_EN_Pos (8UL) |
BDRV CTRL1: LS2_EN (Bit 8)
#define BDRV_CTRL1_LS2_OC_DIS_Msk (0x8000UL) |
BDRV CTRL1: LS2_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_OC_DIS_Pos (15UL) |
BDRV CTRL1: LS2_OC_DIS (Bit 15)
#define BDRV_CTRL1_LS2_OC_STS_Msk (0x4000UL) |
BDRV CTRL1: LS2_OC_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_OC_STS_Pos (14UL) |
BDRV CTRL1: LS2_OC_STS (Bit 14)
#define BDRV_CTRL1_LS2_ON_Msk (0x400UL) |
BDRV CTRL1: LS2_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_ON_Pos (10UL) |
BDRV CTRL1: LS2_ON (Bit 10)
#define BDRV_CTRL1_LS2_PWM_Msk (0x200UL) |
BDRV CTRL1: LS2_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_PWM_Pos (9UL) |
BDRV CTRL1: LS2_PWM (Bit 9)
#define BDRV_CTRL1_LS2_SUPERR_STS_Msk (0x2000UL) |
BDRV CTRL1: LS2_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_SUPERR_STS_Pos (13UL) |
BDRV CTRL1: LS2_SUPERR_STS (Bit 13)
#define BDRV_CTRL2_DLY_DIAG_CHSEL_Msk (0x70000000UL) |
BDRV CTRL2: DLY_DIAG_CHSEL (Bitfield-Mask: 0x07)
#define BDRV_CTRL2_DLY_DIAG_CHSEL_Pos (28UL) |
BDRV CTRL2: DLY_DIAG_CHSEL (Bit 28)
#define BDRV_CTRL2_DLY_DIAG_DIRSEL_Msk (0x80000000UL) |
BDRV CTRL2: DLY_DIAG_DIRSEL (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_DLY_DIAG_DIRSEL_Pos (31UL) |
BDRV CTRL2: DLY_DIAG_DIRSEL (Bit 31)
#define BDRV_CTRL2_DLY_DIAG_SCLR_Msk (0x4000000UL) |
BDRV CTRL2: DLY_DIAG_SCLR (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_DLY_DIAG_SCLR_Pos (26UL) |
BDRV CTRL2: DLY_DIAG_SCLR (Bit 26)
#define BDRV_CTRL2_DLY_DIAG_STS_Msk (0x8000000UL) |
BDRV CTRL2: DLY_DIAG_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_DLY_DIAG_STS_Pos (27UL) |
BDRV CTRL2: DLY_DIAG_STS (Bit 27)
#define BDRV_CTRL2_DLY_DIAG_TIM_Msk (0x3ff0000UL) |
BDRV CTRL2: DLY_DIAG_TIM (Bitfield-Mask: 0x3ff)
#define BDRV_CTRL2_DLY_DIAG_TIM_Pos (16UL) |
BDRV CTRL2: DLY_DIAG_TIM (Bit 16)
#define BDRV_CTRL3_DRV_CCP_DIS_Msk (0x4000000UL) |
BDRV CTRL3: DRV_CCP_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL3_DRV_CCP_DIS_Pos (26UL) |
BDRV CTRL3: DRV_CCP_DIS (Bit 26)
#define BDRV_CTRL3_DRV_CCP_TIMSEL_Msk (0x3000000UL) |
BDRV CTRL3: DRV_CCP_TIMSEL (Bitfield-Mask: 0x03)
#define BDRV_CTRL3_DRV_CCP_TIMSEL_Pos (24UL) |
BDRV CTRL3: DRV_CCP_TIMSEL (Bit 24)
#define BDRV_CTRL3_DSMONVTH_Msk (0x70000UL) |
BDRV CTRL3: DSMONVTH (Bitfield-Mask: 0x07)
#define BDRV_CTRL3_DSMONVTH_Pos (16UL) |
BDRV CTRL3: DSMONVTH (Bit 16)
#define BDRV_CTRL3_ICHARGE_TRIM_Msk (0x1fUL) |
BDRV CTRL3: ICHARGE_TRIM (Bitfield-Mask: 0x1f)
#define BDRV_CTRL3_ICHARGE_TRIM_Pos (0UL) |
BDRV CTRL3: ICHARGE_TRIM (Bit 0)
#define BDRV_CTRL3_ICHARGEDIV2_N_Msk (0x40UL) |
BDRV CTRL3: ICHARGEDIV2_N (Bitfield-Mask: 0x01)
#define BDRV_CTRL3_ICHARGEDIV2_N_Pos (6UL) |
BDRV CTRL3: ICHARGEDIV2_N (Bit 6)
#define BDRV_CTRL3_IDISCHARGE_TRIM_Msk (0x1f00UL) |
BDRV CTRL3: IDISCHARGE_TRIM (Bitfield-Mask: 0x1f)
#define BDRV_CTRL3_IDISCHARGE_TRIM_Pos (8UL) |
BDRV CTRL3: IDISCHARGE_TRIM (Bit 8)
#define BDRV_CTRL3_IDISCHARGEDIV2_N_Msk (0x4000UL) |
BDRV CTRL3: IDISCHARGEDIV2_N (Bitfield-Mask: 0x01)
#define BDRV_CTRL3_IDISCHARGEDIV2_N_Pos (14UL) |
BDRV CTRL3: IDISCHARGEDIV2_N (Bit 14)
#define BDRV_CTRL3_OFF_SEQ_EN_Msk (0x8000UL) |
BDRV CTRL3: OFF_SEQ_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL3_OFF_SEQ_EN_Pos (15UL) |
BDRV CTRL3: OFF_SEQ_EN (Bit 15)
#define BDRV_CTRL3_ON_SEQ_EN_Msk (0x80UL) |
BDRV CTRL3: ON_SEQ_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL3_ON_SEQ_EN_Pos (7UL) |
BDRV CTRL3: ON_SEQ_EN (Bit 7)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Msk (0xf8000000UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_1 (Bitfield-Mask: 0x1f)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Pos (27UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_1 (Bit 27)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Msk (0xf80000UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_2 (Bitfield-Mask: 0x1f)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Pos (19UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_2 (Bit 19)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Msk (0xf800UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_3 (Bitfield-Mask: 0x1f)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Pos (11UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_3 (Bit 11)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Msk (0xf8UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_4 (Bitfield-Mask: 0x1f)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Pos (3UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_I_4 (Bit 3)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Msk (0x7000000UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_1 (Bitfield-Mask: 0x07)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Pos (24UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_1 (Bit 24)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Msk (0x70000UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_2 (Bitfield-Mask: 0x07)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Pos (16UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_2 (Bit 16)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Msk (0x700UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_3 (Bitfield-Mask: 0x07)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Pos (8UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_3 (Bit 8)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Msk (0x7UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_4 (Bitfield-Mask: 0x07)
#define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Pos (0UL) |
BDRV OFF_SEQ_CTRL: DRV_OFF_t_4 (Bit 0)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Msk (0xf8000000UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_1 (Bitfield-Mask: 0x1f)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Pos (27UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_1 (Bit 27)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Msk (0xf80000UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_2 (Bitfield-Mask: 0x1f)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Pos (19UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_2 (Bit 19)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Msk (0xf800UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_3 (Bitfield-Mask: 0x1f)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Pos (11UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_3 (Bit 11)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Msk (0xf8UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_4 (Bitfield-Mask: 0x1f)
#define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Pos (3UL) |
BDRV ON_SEQ_CTRL: DRV_ON_I_4 (Bit 3)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Msk (0x7000000UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_1 (Bitfield-Mask: 0x07)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Pos (24UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_1 (Bit 24)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Msk (0x70000UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_2 (Bitfield-Mask: 0x07)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Pos (16UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_2 (Bit 16)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Msk (0x700UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_3 (Bitfield-Mask: 0x07)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Pos (8UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_3 (Bit 8)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Msk (0x7UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_4 (Bitfield-Mask: 0x07)
#define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Pos (0UL) |
BDRV ON_SEQ_CTRL: DRV_ON_t_4 (Bit 0)
#define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Msk (0x3000000UL) |
BDRV TRIM_DRVx: CPLOW_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Pos (24UL) |
BDRV TRIM_DRVx: CPLOW_TFILT_SEL (Bit 24)
#define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Msk (0x60UL) |
BDRV TRIM_DRVx: DRV_CCPTIMMUL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Pos (5UL) |
BDRV TRIM_DRVx: DRV_CCPTIMMUL (Bit 5)
#define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Msk (0x40000UL) |
BDRV TRIM_DRVx: HS1DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Pos (18UL) |
BDRV TRIM_DRVx: HS1DRV_FDISCHG_DIS (Bit 18)
#define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Msk (0x200000UL) |
BDRV TRIM_DRVx: HS1DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Pos (21UL) |
BDRV TRIM_DRVx: HS1DRV_OCSDN_DIS (Bit 21)
#define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Msk (0x80000UL) |
BDRV TRIM_DRVx: HS2DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Pos (19UL) |
BDRV TRIM_DRVx: HS2DRV_FDISCHG_DIS (Bit 19)
#define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Msk (0x400000UL) |
BDRV TRIM_DRVx: HS2DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Pos (22UL) |
BDRV TRIM_DRVx: HS2DRV_OCSDN_DIS (Bit 22)
#define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Msk (0x30000UL) |
BDRV TRIM_DRVx: HSDRV_DS_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Pos (16UL) |
BDRV TRIM_DRVx: HSDRV_DS_TFILT_SEL (Bit 16)
#define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Msk (0x400UL) |
BDRV TRIM_DRVx: LS1DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Pos (10UL) |
BDRV TRIM_DRVx: LS1DRV_FDISCHG_DIS (Bit 10)
#define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Msk (0x2000UL) |
BDRV TRIM_DRVx: LS1DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Pos (13UL) |
BDRV TRIM_DRVx: LS1DRV_OCSDN_DIS (Bit 13)
#define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Msk (0x800UL) |
BDRV TRIM_DRVx: LS2DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Pos (11UL) |
BDRV TRIM_DRVx: LS2DRV_FDISCHG_DIS (Bit 11)
#define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Msk (0x4000UL) |
BDRV TRIM_DRVx: LS2DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Pos (14UL) |
BDRV TRIM_DRVx: LS2DRV_OCSDN_DIS (Bit 14)
#define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Msk (0x3UL) |
BDRV TRIM_DRVx: LS_HS_BT_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Pos (0UL) |
BDRV TRIM_DRVx: LS_HS_BT_TFILT_SEL (Bit 0)
#define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Msk (0x300UL) |
BDRV TRIM_DRVx: LSDRV_DS_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Pos (8UL) |
BDRV TRIM_DRVx: LSDRV_DS_TFILT_SEL (Bit 8)
#define CCU6_CC60R_CCV_Msk (0xffffUL) |
CCU6 CC60R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC60R_CCV_Pos (0UL) |
CCU6 CC60R: CCV (Bit 0)
#define CCU6_CC60SR_CCS_Msk (0xffffUL) |
CCU6 CC60SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC60SR_CCS_Pos (0UL) |
CCU6 CC60SR: CCS (Bit 0)
#define CCU6_CC61R_CCV_Msk (0xffffUL) |
CCU6 CC61R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC61R_CCV_Pos (0UL) |
CCU6 CC61R: CCV (Bit 0)
#define CCU6_CC61SR_CCS_Msk (0xffffUL) |
CCU6 CC61SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC61SR_CCS_Pos (0UL) |
CCU6 CC61SR: CCS (Bit 0)
#define CCU6_CC62R_CCV_Msk (0xffffUL) |
CCU6 CC62R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC62R_CCV_Pos (0UL) |
CCU6 CC62R: CCV (Bit 0)
#define CCU6_CC62SR_CCS_Msk (0xffffUL) |
CCU6 CC62SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC62SR_CCS_Pos (0UL) |
CCU6 CC62SR: CCS (Bit 0)
#define CCU6_CC63R_CCV_Msk (0xffffUL) |
CCU6 CC63R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC63R_CCV_Pos (0UL) |
CCU6 CC63R: CCV (Bit 0)
#define CCU6_CC63SR_CCS_Msk (0xffffUL) |
CCU6 CC63SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC63SR_CCS_Pos (0UL) |
CCU6 CC63SR: CCS (Bit 0)
#define CCU6_CMPMODIF_MCC60R_Msk (0x100UL) |
CCU6 CMPMODIF: MCC60R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC60R_Pos (8UL) |
CCU6 CMPMODIF: MCC60R (Bit 8)
#define CCU6_CMPMODIF_MCC60S_Msk (0x1UL) |
CCU6 CMPMODIF: MCC60S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC60S_Pos (0UL) |
CCU6 CMPMODIF: MCC60S (Bit 0)
#define CCU6_CMPMODIF_MCC61R_Msk (0x200UL) |
CCU6 CMPMODIF: MCC61R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC61R_Pos (9UL) |
CCU6 CMPMODIF: MCC61R (Bit 9)
#define CCU6_CMPMODIF_MCC61S_Msk (0x2UL) |
CCU6 CMPMODIF: MCC61S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC61S_Pos (1UL) |
CCU6 CMPMODIF: MCC61S (Bit 1)
#define CCU6_CMPMODIF_MCC62R_Msk (0x400UL) |
CCU6 CMPMODIF: MCC62R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC62R_Pos (10UL) |
CCU6 CMPMODIF: MCC62R (Bit 10)
#define CCU6_CMPMODIF_MCC62S_Msk (0x4UL) |
CCU6 CMPMODIF: MCC62S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC62S_Pos (2UL) |
CCU6 CMPMODIF: MCC62S (Bit 2)
#define CCU6_CMPMODIF_MCC63R_Msk (0x4000UL) |
CCU6 CMPMODIF: MCC63R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC63R_Pos (14UL) |
CCU6 CMPMODIF: MCC63R (Bit 14)
#define CCU6_CMPMODIF_MCC63S_Msk (0x40UL) |
CCU6 CMPMODIF: MCC63S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC63S_Pos (6UL) |
CCU6 CMPMODIF: MCC63S (Bit 6)
#define CCU6_CMPSTAT_CC60PS_Msk (0x100UL) |
CCU6 CMPSTAT: CC60PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC60PS_Pos (8UL) |
CCU6 CMPSTAT: CC60PS (Bit 8)
#define CCU6_CMPSTAT_CC60ST_Msk (0x1UL) |
CCU6 CMPSTAT: CC60ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC60ST_Pos (0UL) |
CCU6 CMPSTAT: CC60ST (Bit 0)
#define CCU6_CMPSTAT_CC61PS_Msk (0x400UL) |
CCU6 CMPSTAT: CC61PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC61PS_Pos (10UL) |
CCU6 CMPSTAT: CC61PS (Bit 10)
#define CCU6_CMPSTAT_CC61ST_Msk (0x2UL) |
CCU6 CMPSTAT: CC61ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC61ST_Pos (1UL) |
CCU6 CMPSTAT: CC61ST (Bit 1)
#define CCU6_CMPSTAT_CC62PS_Msk (0x1000UL) |
CCU6 CMPSTAT: CC62PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC62PS_Pos (12UL) |
CCU6 CMPSTAT: CC62PS (Bit 12)
#define CCU6_CMPSTAT_CC62ST_Msk (0x4UL) |
CCU6 CMPSTAT: CC62ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC62ST_Pos (2UL) |
CCU6 CMPSTAT: CC62ST (Bit 2)
#define CCU6_CMPSTAT_CC63ST_Msk (0x40UL) |
CCU6 CMPSTAT: CC63ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC63ST_Pos (6UL) |
CCU6 CMPSTAT: CC63ST (Bit 6)
#define CCU6_CMPSTAT_CCPOS0_Msk (0x8UL) |
CCU6 CMPSTAT: CCPOS0 (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CCPOS0_Pos (3UL) |
CCU6 CMPSTAT: CCPOS0 (Bit 3)
#define CCU6_CMPSTAT_CCPOS1_Msk (0x10UL) |
CCU6 CMPSTAT: CCPOS1 (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CCPOS1_Pos (4UL) |
CCU6 CMPSTAT: CCPOS1 (Bit 4)
#define CCU6_CMPSTAT_CCPOS2_Msk (0x20UL) |
CCU6 CMPSTAT: CCPOS2 (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CCPOS2_Pos (5UL) |
CCU6 CMPSTAT: CCPOS2 (Bit 5)
#define CCU6_CMPSTAT_COUT60PS_Msk (0x200UL) |
CCU6 CMPSTAT: COUT60PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT60PS_Pos (9UL) |
CCU6 CMPSTAT: COUT60PS (Bit 9)
#define CCU6_CMPSTAT_COUT61PS_Msk (0x800UL) |
CCU6 CMPSTAT: COUT61PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT61PS_Pos (11UL) |
CCU6 CMPSTAT: COUT61PS (Bit 11)
#define CCU6_CMPSTAT_COUT62PS_Msk (0x2000UL) |
CCU6 CMPSTAT: COUT62PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT62PS_Pos (13UL) |
CCU6 CMPSTAT: COUT62PS (Bit 13)
#define CCU6_CMPSTAT_COUT63PS_Msk (0x4000UL) |
CCU6 CMPSTAT: COUT63PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT63PS_Pos (14UL) |
CCU6 CMPSTAT: COUT63PS (Bit 14)
#define CCU6_CMPSTAT_T13IM_Msk (0x8000UL) |
CCU6 CMPSTAT: T13IM (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_T13IM_Pos (15UL) |
CCU6 CMPSTAT: T13IM (Bit 15)
#define CCU6_IEN_ENCC60F_Msk (0x2UL) |
CCU6 IEN: ENCC60F (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC60F_Pos (1UL) |
CCU6 IEN: ENCC60F (Bit 1)
#define CCU6_IEN_ENCC60R_Msk (0x1UL) |
CCU6 IEN: ENCC60R (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC60R_Pos (0UL) |
CCU6 IEN: ENCC60R (Bit 0)
#define CCU6_IEN_ENCC61F_Msk (0x8UL) |
CCU6 IEN: ENCC61F (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC61F_Pos (3UL) |
CCU6 IEN: ENCC61F (Bit 3)
#define CCU6_IEN_ENCC61R_Msk (0x4UL) |
CCU6 IEN: ENCC61R (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC61R_Pos (2UL) |
CCU6 IEN: ENCC61R (Bit 2)
#define CCU6_IEN_ENCC62F_Msk (0x20UL) |
CCU6 IEN: ENCC62F (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC62F_Pos (5UL) |
CCU6 IEN: ENCC62F (Bit 5)
#define CCU6_IEN_ENCC62R_Msk (0x10UL) |
CCU6 IEN: ENCC62R (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC62R_Pos (4UL) |
CCU6 IEN: ENCC62R (Bit 4)
#define CCU6_IEN_ENCHE_Msk (0x1000UL) |
CCU6 IEN: ENCHE (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCHE_Pos (12UL) |
CCU6 IEN: ENCHE (Bit 12)
#define CCU6_IEN_ENIDLE_Msk (0x4000UL) |
CCU6 IEN: ENIDLE (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENIDLE_Pos (14UL) |
CCU6 IEN: ENIDLE (Bit 14)
#define CCU6_IEN_ENSTR_Msk (0x8000UL) |
CCU6 IEN: ENSTR (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENSTR_Pos (15UL) |
CCU6 IEN: ENSTR (Bit 15)
#define CCU6_IEN_ENT12OM_Msk (0x40UL) |
CCU6 IEN: ENT12OM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT12OM_Pos (6UL) |
CCU6 IEN: ENT12OM (Bit 6)
#define CCU6_IEN_ENT12PM_Msk (0x80UL) |
CCU6 IEN: ENT12PM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT12PM_Pos (7UL) |
CCU6 IEN: ENT12PM (Bit 7)
#define CCU6_IEN_ENT13CM_Msk (0x100UL) |
CCU6 IEN: ENT13CM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT13CM_Pos (8UL) |
CCU6 IEN: ENT13CM (Bit 8)
#define CCU6_IEN_ENT13PM_Msk (0x200UL) |
CCU6 IEN: ENT13PM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT13PM_Pos (9UL) |
CCU6 IEN: ENT13PM (Bit 9)
#define CCU6_IEN_ENTRPF_Msk (0x400UL) |
CCU6 IEN: ENTRPF (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENTRPF_Pos (10UL) |
CCU6 IEN: ENTRPF (Bit 10)
#define CCU6_IEN_ENWHE_Msk (0x2000UL) |
CCU6 IEN: ENWHE (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENWHE_Pos (13UL) |
CCU6 IEN: ENWHE (Bit 13)
#define CCU6_INP_INPCC60_Msk (0x3UL) |
CCU6 INP: INPCC60 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCC60_Pos (0UL) |
CCU6 INP: INPCC60 (Bit 0)
#define CCU6_INP_INPCC61_Msk (0xcUL) |
CCU6 INP: INPCC61 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCC61_Pos (2UL) |
CCU6 INP: INPCC61 (Bit 2)
#define CCU6_INP_INPCC62_Msk (0x30UL) |
CCU6 INP: INPCC62 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCC62_Pos (4UL) |
CCU6 INP: INPCC62 (Bit 4)
#define CCU6_INP_INPCHE_Msk (0xc0UL) |
CCU6 INP: INPCHE (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCHE_Pos (6UL) |
CCU6 INP: INPCHE (Bit 6)
#define CCU6_INP_INPERR_Msk (0x300UL) |
CCU6 INP: INPERR (Bitfield-Mask: 0x03)
#define CCU6_INP_INPERR_Pos (8UL) |
CCU6 INP: INPERR (Bit 8)
#define CCU6_INP_INPT12_Msk (0xc00UL) |
CCU6 INP: INPT12 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPT12_Pos (10UL) |
CCU6 INP: INPT12 (Bit 10)
#define CCU6_INP_INPT13_Msk (0x3000UL) |
CCU6 INP: INPT13 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPT13_Pos (12UL) |
CCU6 INP: INPT13 (Bit 12)
#define CCU6_IS_CHE_Msk (0x1000UL) |
CCU6 IS: CHE (Bitfield-Mask: 0x01)
#define CCU6_IS_CHE_Pos (12UL) |
CCU6 IS: CHE (Bit 12)
#define CCU6_IS_ICC60F_Msk (0x2UL) |
CCU6 IS: ICC60F (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC60F_Pos (1UL) |
CCU6 IS: ICC60F (Bit 1)
#define CCU6_IS_ICC60R_Msk (0x1UL) |
CCU6 IS: ICC60R (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC60R_Pos (0UL) |
CCU6 IS: ICC60R (Bit 0)
#define CCU6_IS_ICC61F_Msk (0x8UL) |
CCU6 IS: ICC61F (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC61F_Pos (3UL) |
CCU6 IS: ICC61F (Bit 3)
#define CCU6_IS_ICC61R_Msk (0x4UL) |
CCU6 IS: ICC61R (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC61R_Pos (2UL) |
CCU6 IS: ICC61R (Bit 2)
#define CCU6_IS_ICC62F_Msk (0x20UL) |
CCU6 IS: ICC62F (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC62F_Pos (5UL) |
CCU6 IS: ICC62F (Bit 5)
#define CCU6_IS_ICC62R_Msk (0x10UL) |
CCU6 IS: ICC62R (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC62R_Pos (4UL) |
CCU6 IS: ICC62R (Bit 4)
#define CCU6_IS_IDLE_Msk (0x4000UL) |
CCU6 IS: IDLE (Bitfield-Mask: 0x01)
#define CCU6_IS_IDLE_Pos (14UL) |
CCU6 IS: IDLE (Bit 14)
#define CCU6_IS_STR_Msk (0x8000UL) |
CCU6 IS: STR (Bitfield-Mask: 0x01)
#define CCU6_IS_STR_Pos (15UL) |
CCU6 IS: STR (Bit 15)
#define CCU6_IS_T12OM_Msk (0x40UL) |
CCU6 IS: T12OM (Bitfield-Mask: 0x01)
#define CCU6_IS_T12OM_Pos (6UL) |
CCU6 IS: T12OM (Bit 6)
#define CCU6_IS_T12PM_Msk (0x80UL) |
CCU6 IS: T12PM (Bitfield-Mask: 0x01)
#define CCU6_IS_T12PM_Pos (7UL) |
CCU6 IS: T12PM (Bit 7)
#define CCU6_IS_T13CM_Msk (0x100UL) |
CCU6 IS: T13CM (Bitfield-Mask: 0x01)
#define CCU6_IS_T13CM_Pos (8UL) |
CCU6 IS: T13CM (Bit 8)
#define CCU6_IS_T13PM_Msk (0x200UL) |
CCU6 IS: T13PM (Bitfield-Mask: 0x01)
#define CCU6_IS_T13PM_Pos (9UL) |
CCU6 IS: T13PM (Bit 9)
#define CCU6_IS_TRPF_Msk (0x400UL) |
CCU6 IS: TRPF (Bitfield-Mask: 0x01)
#define CCU6_IS_TRPF_Pos (10UL) |
CCU6 IS: TRPF (Bit 10)
#define CCU6_IS_TRPS_Msk (0x800UL) |
CCU6 IS: TRPS (Bitfield-Mask: 0x01)
#define CCU6_IS_TRPS_Pos (11UL) |
CCU6 IS: TRPS (Bit 11)
#define CCU6_IS_WHE_Msk (0x2000UL) |
CCU6 IS: WHE (Bitfield-Mask: 0x01)
#define CCU6_IS_WHE_Pos (13UL) |
CCU6 IS: WHE (Bit 13)
#define CCU6_ISR_RCC60F_Msk (0x2UL) |
CCU6 ISR: RCC60F (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC60F_Pos (1UL) |
CCU6 ISR: RCC60F (Bit 1)
#define CCU6_ISR_RCC60R_Msk (0x1UL) |
CCU6 ISR: RCC60R (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC60R_Pos (0UL) |
CCU6 ISR: RCC60R (Bit 0)
#define CCU6_ISR_RCC61F_Msk (0x8UL) |
CCU6 ISR: RCC61F (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC61F_Pos (3UL) |
CCU6 ISR: RCC61F (Bit 3)
#define CCU6_ISR_RCC61R_Msk (0x4UL) |
CCU6 ISR: RCC61R (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC61R_Pos (2UL) |
CCU6 ISR: RCC61R (Bit 2)
#define CCU6_ISR_RCC62F_Msk (0x20UL) |
CCU6 ISR: RCC62F (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC62F_Pos (5UL) |
CCU6 ISR: RCC62F (Bit 5)
#define CCU6_ISR_RCC62R_Msk (0x10UL) |
CCU6 ISR: RCC62R (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC62R_Pos (4UL) |
CCU6 ISR: RCC62R (Bit 4)
#define CCU6_ISR_RCHE_Msk (0x1000UL) |
CCU6 ISR: RCHE (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCHE_Pos (12UL) |
CCU6 ISR: RCHE (Bit 12)
#define CCU6_ISR_RIDLE_Msk (0x4000UL) |
CCU6 ISR: RIDLE (Bitfield-Mask: 0x01)
#define CCU6_ISR_RIDLE_Pos (14UL) |
CCU6 ISR: RIDLE (Bit 14)
#define CCU6_ISR_RSTR_Msk (0x8000UL) |
CCU6 ISR: RSTR (Bitfield-Mask: 0x01)
#define CCU6_ISR_RSTR_Pos (15UL) |
CCU6 ISR: RSTR (Bit 15)
#define CCU6_ISR_RT12OM_Msk (0x40UL) |
CCU6 ISR: RT12OM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT12OM_Pos (6UL) |
CCU6 ISR: RT12OM (Bit 6)
#define CCU6_ISR_RT12PM_Msk (0x80UL) |
CCU6 ISR: RT12PM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT12PM_Pos (7UL) |
CCU6 ISR: RT12PM (Bit 7)
#define CCU6_ISR_RT13CM_Msk (0x100UL) |
CCU6 ISR: RT13CM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT13CM_Pos (8UL) |
CCU6 ISR: RT13CM (Bit 8)
#define CCU6_ISR_RT13PM_Msk (0x200UL) |
CCU6 ISR: RT13PM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT13PM_Pos (9UL) |
CCU6 ISR: RT13PM (Bit 9)
#define CCU6_ISR_RTRPF_Msk (0x400UL) |
CCU6 ISR: RTRPF (Bitfield-Mask: 0x01)
#define CCU6_ISR_RTRPF_Pos (10UL) |
CCU6 ISR: RTRPF (Bit 10)
#define CCU6_ISR_RWHE_Msk (0x2000UL) |
CCU6 ISR: RWHE (Bitfield-Mask: 0x01)
#define CCU6_ISR_RWHE_Pos (13UL) |
CCU6 ISR: RWHE (Bit 13)
#define CCU6_ISS_SCC60F_Msk (0x2UL) |
CCU6 ISS: SCC60F (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC60F_Pos (1UL) |
CCU6 ISS: SCC60F (Bit 1)
#define CCU6_ISS_SCC60R_Msk (0x1UL) |
CCU6 ISS: SCC60R (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC60R_Pos (0UL) |
CCU6 ISS: SCC60R (Bit 0)
#define CCU6_ISS_SCC61F_Msk (0x8UL) |
CCU6 ISS: SCC61F (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC61F_Pos (3UL) |
CCU6 ISS: SCC61F (Bit 3)
#define CCU6_ISS_SCC61R_Msk (0x4UL) |
CCU6 ISS: SCC61R (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC61R_Pos (2UL) |
CCU6 ISS: SCC61R (Bit 2)
#define CCU6_ISS_SCC62F_Msk (0x20UL) |
CCU6 ISS: SCC62F (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC62F_Pos (5UL) |
CCU6 ISS: SCC62F (Bit 5)
#define CCU6_ISS_SCC62R_Msk (0x10UL) |
CCU6 ISS: SCC62R (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC62R_Pos (4UL) |
CCU6 ISS: SCC62R (Bit 4)
#define CCU6_ISS_SCHE_Msk (0x1000UL) |
CCU6 ISS: SCHE (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCHE_Pos (12UL) |
CCU6 ISS: SCHE (Bit 12)
#define CCU6_ISS_SIDLE_Msk (0x4000UL) |
CCU6 ISS: SIDLE (Bitfield-Mask: 0x01)
#define CCU6_ISS_SIDLE_Pos (14UL) |
CCU6 ISS: SIDLE (Bit 14)
#define CCU6_ISS_SSTR_Msk (0x8000UL) |
CCU6 ISS: SSTR (Bitfield-Mask: 0x01)
#define CCU6_ISS_SSTR_Pos (15UL) |
CCU6 ISS: SSTR (Bit 15)
#define CCU6_ISS_ST12OM_Msk (0x40UL) |
CCU6 ISS: ST12OM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST12OM_Pos (6UL) |
CCU6 ISS: ST12OM (Bit 6)
#define CCU6_ISS_ST12PM_Msk (0x80UL) |
CCU6 ISS: ST12PM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST12PM_Pos (7UL) |
CCU6 ISS: ST12PM (Bit 7)
#define CCU6_ISS_ST13CM_Msk (0x100UL) |
CCU6 ISS: ST13CM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST13CM_Pos (8UL) |
CCU6 ISS: ST13CM (Bit 8)
#define CCU6_ISS_ST13PM_Msk (0x200UL) |
CCU6 ISS: ST13PM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST13PM_Pos (9UL) |
CCU6 ISS: ST13PM (Bit 9)
#define CCU6_ISS_STRPF_Msk (0x400UL) |
CCU6 ISS: STRPF (Bitfield-Mask: 0x01)
#define CCU6_ISS_STRPF_Pos (10UL) |
CCU6 ISS: STRPF (Bit 10)
#define CCU6_ISS_SWHC_Msk (0x800UL) |
CCU6 ISS: SWHC (Bitfield-Mask: 0x01)
#define CCU6_ISS_SWHC_Pos (11UL) |
CCU6 ISS: SWHC (Bit 11)
#define CCU6_ISS_SWHE_Msk (0x2000UL) |
CCU6 ISS: SWHE (Bitfield-Mask: 0x01)
#define CCU6_ISS_SWHE_Pos (13UL) |
CCU6 ISS: SWHE (Bit 13)
#define CCU6_MCMCTR_STE12D_Msk (0x200UL) |
CCU6 MCMCTR: STE12D (Bitfield-Mask: 0x01)
#define CCU6_MCMCTR_STE12D_Pos (9UL) |
CCU6 MCMCTR: STE12D (Bit 9)
#define CCU6_MCMCTR_STE12U_Msk (0x100UL) |
CCU6 MCMCTR: STE12U (Bitfield-Mask: 0x01)
#define CCU6_MCMCTR_STE12U_Pos (8UL) |
CCU6 MCMCTR: STE12U (Bit 8)
#define CCU6_MCMCTR_STE13U_Msk (0x400UL) |
CCU6 MCMCTR: STE13U (Bitfield-Mask: 0x01)
#define CCU6_MCMCTR_STE13U_Pos (10UL) |
CCU6 MCMCTR: STE13U (Bit 10)
#define CCU6_MCMCTR_SWSEL_Msk (0x7UL) |
CCU6 MCMCTR: SWSEL (Bitfield-Mask: 0x07)
#define CCU6_MCMCTR_SWSEL_Pos (0UL) |
CCU6 MCMCTR: SWSEL (Bit 0)
#define CCU6_MCMCTR_SWSYN_Msk (0x30UL) |
CCU6 MCMCTR: SWSYN (Bitfield-Mask: 0x03)
#define CCU6_MCMCTR_SWSYN_Pos (4UL) |
CCU6 MCMCTR: SWSYN (Bit 4)
#define CCU6_MCMOUT_CURH_Msk (0x3800UL) |
CCU6 MCMOUT: CURH (Bitfield-Mask: 0x07)
#define CCU6_MCMOUT_CURH_Pos (11UL) |
CCU6 MCMOUT: CURH (Bit 11)
#define CCU6_MCMOUT_EXPH_Msk (0x700UL) |
CCU6 MCMOUT: EXPH (Bitfield-Mask: 0x07)
#define CCU6_MCMOUT_EXPH_Pos (8UL) |
CCU6 MCMOUT: EXPH (Bit 8)
#define CCU6_MCMOUT_MCMP_Msk (0x3fUL) |
CCU6 MCMOUT: MCMP (Bitfield-Mask: 0x3f)
#define CCU6_MCMOUT_MCMP_Pos (0UL) |
CCU6 MCMOUT: MCMP (Bit 0)
#define CCU6_MCMOUT_R_Msk (0x40UL) |
CCU6 MCMOUT: R (Bitfield-Mask: 0x01)
#define CCU6_MCMOUT_R_Pos (6UL) |
CCU6 MCMOUT: R (Bit 6)
#define CCU6_MCMOUTS_CURHS_Msk (0x3800UL) |
CCU6 MCMOUTS: CURHS (Bitfield-Mask: 0x07)
#define CCU6_MCMOUTS_CURHS_Pos (11UL) |
CCU6 MCMOUTS: CURHS (Bit 11)
#define CCU6_MCMOUTS_EXPHS_Msk (0x700UL) |
CCU6 MCMOUTS: EXPHS (Bitfield-Mask: 0x07)
#define CCU6_MCMOUTS_EXPHS_Pos (8UL) |
CCU6 MCMOUTS: EXPHS (Bit 8)
#define CCU6_MCMOUTS_MCMPS_Msk (0x3fUL) |
CCU6 MCMOUTS: MCMPS (Bitfield-Mask: 0x3f)
#define CCU6_MCMOUTS_MCMPS_Pos (0UL) |
CCU6 MCMOUTS: MCMPS (Bit 0)
#define CCU6_MCMOUTS_STRHP_Msk (0x8000UL) |
CCU6 MCMOUTS: STRHP (Bitfield-Mask: 0x01)
#define CCU6_MCMOUTS_STRHP_Pos (15UL) |
CCU6 MCMOUTS: STRHP (Bit 15)
#define CCU6_MCMOUTS_STRMCM_Msk (0x80UL) |
CCU6 MCMOUTS: STRMCM (Bitfield-Mask: 0x01)
#define CCU6_MCMOUTS_STRMCM_Pos (7UL) |
CCU6 MCMOUTS: STRMCM (Bit 7)
#define CCU6_MODCTR_ECT13O_Msk (0x8000UL) |
CCU6 MODCTR: ECT13O (Bitfield-Mask: 0x01)
#define CCU6_MODCTR_ECT13O_Pos (15UL) |
CCU6 MODCTR: ECT13O (Bit 15)
#define CCU6_MODCTR_MCMEN_Msk (0x80UL) |
CCU6 MODCTR: MCMEN (Bitfield-Mask: 0x01)
#define CCU6_MODCTR_MCMEN_Pos (7UL) |
CCU6 MODCTR: MCMEN (Bit 7)
#define CCU6_MODCTR_T12MODEN_Msk (0x3fUL) |
CCU6 MODCTR: T12MODEN (Bitfield-Mask: 0x3f)
#define CCU6_MODCTR_T12MODEN_Pos (0UL) |
CCU6 MODCTR: T12MODEN (Bit 0)
#define CCU6_MODCTR_T13MODEN_Msk (0x3f00UL) |
CCU6 MODCTR: T13MODEN (Bitfield-Mask: 0x3f)
#define CCU6_MODCTR_T13MODEN_Pos (8UL) |
CCU6 MODCTR: T13MODEN (Bit 8)
#define CCU6_PISEL0_ISCC60_Msk (0x3UL) |
CCU6 PISEL0: ISCC60 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISCC60_Pos (0UL) |
CCU6 PISEL0: ISCC60 (Bit 0)
#define CCU6_PISEL0_ISCC61_Msk (0xcUL) |
CCU6 PISEL0: ISCC61 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISCC61_Pos (2UL) |
CCU6 PISEL0: ISCC61 (Bit 2)
#define CCU6_PISEL0_ISCC62_Msk (0x30UL) |
CCU6 PISEL0: ISCC62 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISCC62_Pos (4UL) |
CCU6 PISEL0: ISCC62 (Bit 4)
#define CCU6_PISEL0_ISPOS0_Msk (0x300UL) |
CCU6 PISEL0: ISPOS0 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISPOS0_Pos (8UL) |
CCU6 PISEL0: ISPOS0 (Bit 8)
#define CCU6_PISEL0_ISPOS1_Msk (0xc00UL) |
CCU6 PISEL0: ISPOS1 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISPOS1_Pos (10UL) |
CCU6 PISEL0: ISPOS1 (Bit 10)
#define CCU6_PISEL0_ISPOS2_Msk (0x3000UL) |
CCU6 PISEL0: ISPOS2 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISPOS2_Pos (12UL) |
CCU6 PISEL0: ISPOS2 (Bit 12)
#define CCU6_PISEL0_IST12HR_Msk (0xc000UL) |
CCU6 PISEL0: IST12HR (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_IST12HR_Pos (14UL) |
CCU6 PISEL0: IST12HR (Bit 14)
#define CCU6_PISEL0_ISTRP_Msk (0xc0UL) |
CCU6 PISEL0: ISTRP (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISTRP_Pos (6UL) |
CCU6 PISEL0: ISTRP (Bit 6)
#define CCU6_PISEL2_ISCNT12_Msk (0xcUL) |
CCU6 PISEL2: ISCNT12 (Bitfield-Mask: 0x03)
#define CCU6_PISEL2_ISCNT12_Pos (2UL) |
CCU6 PISEL2: ISCNT12 (Bit 2)
#define CCU6_PISEL2_ISCNT13_Msk (0x30UL) |
CCU6 PISEL2: ISCNT13 (Bitfield-Mask: 0x03)
#define CCU6_PISEL2_ISCNT13_Pos (4UL) |
CCU6 PISEL2: ISCNT13 (Bit 4)
#define CCU6_PISEL2_IST13HR_Msk (0x3UL) |
CCU6 PISEL2: IST13HR (Bitfield-Mask: 0x03)
#define CCU6_PISEL2_IST13HR_Pos (0UL) |
CCU6 PISEL2: IST13HR (Bit 0)
#define CCU6_PISEL2_T12EXT_Msk (0x40UL) |
CCU6 PISEL2: T12EXT (Bitfield-Mask: 0x01)
#define CCU6_PISEL2_T12EXT_Pos (6UL) |
CCU6 PISEL2: T12EXT (Bit 6)
#define CCU6_PISEL2_T13EXT_Msk (0x80UL) |
CCU6 PISEL2: T13EXT (Bitfield-Mask: 0x01)
#define CCU6_PISEL2_T13EXT_Pos (7UL) |
CCU6 PISEL2: T13EXT (Bit 7)
#define CCU6_PSLR_PSL63_Msk (0x80UL) |
CCU6 PSLR: PSL63 (Bitfield-Mask: 0x01)
#define CCU6_PSLR_PSL63_Pos (7UL) |
CCU6 PSLR: PSL63 (Bit 7)
#define CCU6_PSLR_PSL_Msk (0x3fUL) |
CCU6 PSLR: PSL (Bitfield-Mask: 0x3f)
#define CCU6_PSLR_PSL_Pos (0UL) |
CCU6 PSLR: PSL (Bit 0)
#define CCU6_T12_T12CV_Msk (0xffffUL) |
CCU6 T12: T12CV (Bitfield-Mask: 0xffff)
#define CCU6_T12_T12CV_Pos (0UL) |
CCU6 T12: T12CV (Bit 0)
#define CCU6_T12DTC_DTE0_Msk (0x100UL) |
CCU6 T12DTC: DTE0 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTE0_Pos (8UL) |
CCU6 T12DTC: DTE0 (Bit 8)
#define CCU6_T12DTC_DTE1_Msk (0x200UL) |
CCU6 T12DTC: DTE1 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTE1_Pos (9UL) |
CCU6 T12DTC: DTE1 (Bit 9)
#define CCU6_T12DTC_DTE2_Msk (0x400UL) |
CCU6 T12DTC: DTE2 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTE2_Pos (10UL) |
CCU6 T12DTC: DTE2 (Bit 10)
#define CCU6_T12DTC_DTM_Msk (0xffUL) |
CCU6 T12DTC: DTM (Bitfield-Mask: 0xff)
#define CCU6_T12DTC_DTM_Pos (0UL) |
CCU6 T12DTC: DTM (Bit 0)
#define CCU6_T12DTC_DTR0_Msk (0x1000UL) |
CCU6 T12DTC: DTR0 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTR0_Pos (12UL) |
CCU6 T12DTC: DTR0 (Bit 12)
#define CCU6_T12DTC_DTR1_Msk (0x2000UL) |
CCU6 T12DTC: DTR1 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTR1_Pos (13UL) |
CCU6 T12DTC: DTR1 (Bit 13)
#define CCU6_T12DTC_DTR2_Msk (0x4000UL) |
CCU6 T12DTC: DTR2 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTR2_Pos (14UL) |
CCU6 T12DTC: DTR2 (Bit 14)
#define CCU6_T12MSEL_DBYP_Msk (0x8000UL) |
CCU6 T12MSEL: DBYP (Bitfield-Mask: 0x01)
#define CCU6_T12MSEL_DBYP_Pos (15UL) |
CCU6 T12MSEL: DBYP (Bit 15)
#define CCU6_T12MSEL_HSYNC_Msk (0x7000UL) |
CCU6 T12MSEL: HSYNC (Bitfield-Mask: 0x07)
#define CCU6_T12MSEL_HSYNC_Pos (12UL) |
CCU6 T12MSEL: HSYNC (Bit 12)
#define CCU6_T12MSEL_MSEL60_Msk (0xfUL) |
CCU6 T12MSEL: MSEL60 (Bitfield-Mask: 0x0f)
#define CCU6_T12MSEL_MSEL60_Pos (0UL) |
CCU6 T12MSEL: MSEL60 (Bit 0)
#define CCU6_T12MSEL_MSEL61_Msk (0xf0UL) |
CCU6 T12MSEL: MSEL61 (Bitfield-Mask: 0x0f)
#define CCU6_T12MSEL_MSEL61_Pos (4UL) |
CCU6 T12MSEL: MSEL61 (Bit 4)
#define CCU6_T12MSEL_MSEL62_Msk (0xf00UL) |
CCU6 T12MSEL: MSEL62 (Bitfield-Mask: 0x0f)
#define CCU6_T12MSEL_MSEL62_Pos (8UL) |
CCU6 T12MSEL: MSEL62 (Bit 8)
#define CCU6_T12PR_T12PV_Msk (0xffffUL) |
CCU6 T12PR: T12PV (Bitfield-Mask: 0xffff)
#define CCU6_T12PR_T12PV_Pos (0UL) |
CCU6 T12PR: T12PV (Bit 0)
#define CCU6_T13_T13CV_Msk (0xffffUL) |
CCU6 T13: T13CV (Bitfield-Mask: 0xffff)
#define CCU6_T13_T13CV_Pos (0UL) |
CCU6 T13: T13CV (Bit 0)
#define CCU6_T13PR_T13PV_Msk (0xffffUL) |
CCU6 T13PR: T13PV (Bitfield-Mask: 0xffff)
#define CCU6_T13PR_T13PV_Pos (0UL) |
CCU6 T13PR: T13PV (Bit 0)
#define CCU6_TCTR0_CDIR_Msk (0x40UL) |
CCU6 TCTR0: CDIR (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_CDIR_Pos (6UL) |
CCU6 TCTR0: CDIR (Bit 6)
#define CCU6_TCTR0_CTM_Msk (0x80UL) |
CCU6 TCTR0: CTM (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_CTM_Pos (7UL) |
CCU6 TCTR0: CTM (Bit 7)
#define CCU6_TCTR0_STE12_Msk (0x20UL) |
CCU6 TCTR0: STE12 (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_STE12_Pos (5UL) |
CCU6 TCTR0: STE12 (Bit 5)
#define CCU6_TCTR0_STE13_Msk (0x2000UL) |
CCU6 TCTR0: STE13 (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_STE13_Pos (13UL) |
CCU6 TCTR0: STE13 (Bit 13)
#define CCU6_TCTR0_T12CLK_Msk (0x7UL) |
CCU6 TCTR0: T12CLK (Bitfield-Mask: 0x07)
#define CCU6_TCTR0_T12CLK_Pos (0UL) |
CCU6 TCTR0: T12CLK (Bit 0)
#define CCU6_TCTR0_T12PRE_Msk (0x8UL) |
CCU6 TCTR0: T12PRE (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T12PRE_Pos (3UL) |
CCU6 TCTR0: T12PRE (Bit 3)
#define CCU6_TCTR0_T12R_Msk (0x10UL) |
CCU6 TCTR0: T12R (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T12R_Pos (4UL) |
CCU6 TCTR0: T12R (Bit 4)
#define CCU6_TCTR0_T13CLK_Msk (0x700UL) |
CCU6 TCTR0: T13CLK (Bitfield-Mask: 0x07)
#define CCU6_TCTR0_T13CLK_Pos (8UL) |
CCU6 TCTR0: T13CLK (Bit 8)
#define CCU6_TCTR0_T13PRE_Msk (0x800UL) |
CCU6 TCTR0: T13PRE (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T13PRE_Pos (11UL) |
CCU6 TCTR0: T13PRE (Bit 11)
#define CCU6_TCTR0_T13R_Msk (0x1000UL) |
CCU6 TCTR0: T13R (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T13R_Pos (12UL) |
CCU6 TCTR0: T13R (Bit 12)
#define CCU6_TCTR2_T12RSEL_Msk (0x300UL) |
CCU6 TCTR2: T12RSEL (Bitfield-Mask: 0x03)
#define CCU6_TCTR2_T12RSEL_Pos (8UL) |
CCU6 TCTR2: T12RSEL (Bit 8)
#define CCU6_TCTR2_T12SSC_Msk (0x1UL) |
CCU6 TCTR2: T12SSC (Bitfield-Mask: 0x01)
#define CCU6_TCTR2_T12SSC_Pos (0UL) |
CCU6 TCTR2: T12SSC (Bit 0)
#define CCU6_TCTR2_T13RSEL_Msk (0xc00UL) |
CCU6 TCTR2: T13RSEL (Bitfield-Mask: 0x03)
#define CCU6_TCTR2_T13RSEL_Pos (10UL) |
CCU6 TCTR2: T13RSEL (Bit 10)
#define CCU6_TCTR2_T13SSC_Msk (0x2UL) |
CCU6 TCTR2: T13SSC (Bitfield-Mask: 0x01)
#define CCU6_TCTR2_T13SSC_Pos (1UL) |
CCU6 TCTR2: T13SSC (Bit 1)
#define CCU6_TCTR2_T13TEC_Msk (0x1cUL) |
CCU6 TCTR2: T13TEC (Bitfield-Mask: 0x07)
#define CCU6_TCTR2_T13TEC_Pos (2UL) |
CCU6 TCTR2: T13TEC (Bit 2)
#define CCU6_TCTR2_T13TED_Msk (0x60UL) |
CCU6 TCTR2: T13TED (Bitfield-Mask: 0x03)
#define CCU6_TCTR2_T13TED_Pos (5UL) |
CCU6 TCTR2: T13TED (Bit 5)
#define CCU6_TCTR4_DTRES_Msk (0x8UL) |
CCU6 TCTR4: DTRES (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_DTRES_Pos (3UL) |
CCU6 TCTR4: DTRES (Bit 3)
#define CCU6_TCTR4_T12CNT_Msk (0x20UL) |
CCU6 TCTR4: T12CNT (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12CNT_Pos (5UL) |
CCU6 TCTR4: T12CNT (Bit 5)
#define CCU6_TCTR4_T12RES_Msk (0x4UL) |
CCU6 TCTR4: T12RES (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12RES_Pos (2UL) |
CCU6 TCTR4: T12RES (Bit 2)
#define CCU6_TCTR4_T12RR_Msk (0x1UL) |
CCU6 TCTR4: T12RR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12RR_Pos (0UL) |
CCU6 TCTR4: T12RR (Bit 0)
#define CCU6_TCTR4_T12RS_Msk (0x2UL) |
CCU6 TCTR4: T12RS (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12RS_Pos (1UL) |
CCU6 TCTR4: T12RS (Bit 1)
#define CCU6_TCTR4_T12STD_Msk (0x80UL) |
CCU6 TCTR4: T12STD (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12STD_Pos (7UL) |
CCU6 TCTR4: T12STD (Bit 7)
#define CCU6_TCTR4_T12STR_Msk (0x40UL) |
CCU6 TCTR4: T12STR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12STR_Pos (6UL) |
CCU6 TCTR4: T12STR (Bit 6)
#define CCU6_TCTR4_T13CNT_Msk (0x2000UL) |
CCU6 TCTR4: T13CNT (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13CNT_Pos (13UL) |
CCU6 TCTR4: T13CNT (Bit 13)
#define CCU6_TCTR4_T13RES_Msk (0x400UL) |
CCU6 TCTR4: T13RES (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13RES_Pos (10UL) |
CCU6 TCTR4: T13RES (Bit 10)
#define CCU6_TCTR4_T13RR_Msk (0x100UL) |
CCU6 TCTR4: T13RR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13RR_Pos (8UL) |
CCU6 TCTR4: T13RR (Bit 8)
#define CCU6_TCTR4_T13RS_Msk (0x200UL) |
CCU6 TCTR4: T13RS (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13RS_Pos (9UL) |
CCU6 TCTR4: T13RS (Bit 9)
#define CCU6_TCTR4_T13STD_Msk (0x8000UL) |
CCU6 TCTR4: T13STD (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13STD_Pos (15UL) |
CCU6 TCTR4: T13STD (Bit 15)
#define CCU6_TCTR4_T13STR_Msk (0x4000UL) |
CCU6 TCTR4: T13STR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13STR_Pos (14UL) |
CCU6 TCTR4: T13STR (Bit 14)
#define CCU6_TRPCTR_TRPEN13_Msk (0x4000UL) |
CCU6 TRPCTR: TRPEN13 (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPEN13_Pos (14UL) |
CCU6 TRPCTR: TRPEN13 (Bit 14)
#define CCU6_TRPCTR_TRPEN_Msk (0x3f00UL) |
CCU6 TRPCTR: TRPEN (Bitfield-Mask: 0x3f)
#define CCU6_TRPCTR_TRPEN_Pos (8UL) |
CCU6 TRPCTR: TRPEN (Bit 8)
#define CCU6_TRPCTR_TRPM0_Msk (0x1UL) |
CCU6 TRPCTR: TRPM0 (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPM0_Pos (0UL) |
CCU6 TRPCTR: TRPM0 (Bit 0)
#define CCU6_TRPCTR_TRPM1_Msk (0x2UL) |
CCU6 TRPCTR: TRPM1 (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPM1_Pos (1UL) |
CCU6 TRPCTR: TRPM1 (Bit 1)
#define CCU6_TRPCTR_TRPM2_Msk (0x4UL) |
CCU6 TRPCTR: TRPM2 (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPM2_Pos (2UL) |
CCU6 TRPCTR: TRPM2 (Bit 2)
#define CCU6_TRPCTR_TRPPEN_Msk (0x8000UL) |
CCU6 TRPCTR: TRPPEN (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPPEN_Pos (15UL) |
CCU6 TRPCTR: TRPPEN (Bit 15)
#define CPU_AFSR_CP0_Msk (0x3UL) |
CPU AFSR: CP0 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP0_Pos (0UL) |
CPU AFSR: CP0 (Bit 0)
#define CPU_AFSR_CP10_Msk (0x300000UL) |
CPU AFSR: CP10 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP10_Pos (20UL) |
CPU AFSR: CP10 (Bit 20)
#define CPU_AFSR_CP11_Msk (0xc00000UL) |
CPU AFSR: CP11 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP11_Pos (22UL) |
CPU AFSR: CP11 (Bit 22)
#define CPU_AFSR_CP1_Msk (0xcUL) |
CPU AFSR: CP1 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP1_Pos (2UL) |
CPU AFSR: CP1 (Bit 2)
#define CPU_AFSR_CP2_Msk (0x30UL) |
CPU AFSR: CP2 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP2_Pos (4UL) |
CPU AFSR: CP2 (Bit 4)
#define CPU_AFSR_CP3_Msk (0xc0UL) |
CPU AFSR: CP3 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP3_Pos (6UL) |
CPU AFSR: CP3 (Bit 6)
#define CPU_AFSR_CP4_Msk (0x300UL) |
CPU AFSR: CP4 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP4_Pos (8UL) |
CPU AFSR: CP4 (Bit 8)
#define CPU_AFSR_CP5_Msk (0xc00UL) |
CPU AFSR: CP5 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP5_Pos (10UL) |
CPU AFSR: CP5 (Bit 10)
#define CPU_AFSR_CP6_Msk (0x3000UL) |
CPU AFSR: CP6 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP6_Pos (12UL) |
CPU AFSR: CP6 (Bit 12)
#define CPU_AFSR_CP7_Msk (0xc000UL) |
CPU AFSR: CP7 (Bitfield-Mask: 0x03)
#define CPU_AFSR_CP7_Pos (14UL) |
CPU AFSR: CP7 (Bit 14)
#define CPU_AIRCR_ENDIANNESS_Msk (0x8000UL) |
CPU AIRCR: ENDIANNESS (Bitfield-Mask: 0x01)
#define CPU_AIRCR_ENDIANNESS_Pos (15UL) |
CPU AIRCR: ENDIANNESS (Bit 15)
#define CPU_AIRCR_PRIGROUP_Msk (0x700UL) |
CPU AIRCR: PRIGROUP (Bitfield-Mask: 0x07)
#define CPU_AIRCR_PRIGROUP_Pos (8UL) |
CPU AIRCR: PRIGROUP (Bit 8)
#define CPU_AIRCR_SYSRESETREQ_Msk (0x4UL) |
CPU AIRCR: SYSRESETREQ (Bitfield-Mask: 0x01)
#define CPU_AIRCR_SYSRESETREQ_Pos (2UL) |
CPU AIRCR: SYSRESETREQ (Bit 2)
#define CPU_AIRCR_VECTCLRACTIVE_Msk (0x2UL) |
CPU AIRCR: VECTCLRACTIVE (Bitfield-Mask: 0x01)
#define CPU_AIRCR_VECTCLRACTIVE_Pos (1UL) |
CPU AIRCR: VECTCLRACTIVE (Bit 1)
#define CPU_AIRCR_VECTKEY_Msk (0xffff0000UL) |
CPU AIRCR: VECTKEY (Bitfield-Mask: 0xffff)
#define CPU_AIRCR_VECTKEY_Pos (16UL) |
CPU AIRCR: VECTKEY (Bit 16)
#define CPU_AIRCR_VECTRESET_Msk (0x1UL) |
CPU AIRCR: VECTRESET (Bitfield-Mask: 0x01)
#define CPU_AIRCR_VECTRESET_Pos (0UL) |
CPU AIRCR: VECTRESET (Bit 0)
#define CPU_BFAR_ADDRESS_Msk (0xffffffffUL) |
CPU BFAR: ADDRESS (Bitfield-Mask: 0xffffffff)
#define CPU_BFAR_ADDRESS_Pos (0UL) |
CPU BFAR: ADDRESS (Bit 0)
#define CPU_CCR_BFHFMIGN_Msk (0x100UL) |
CPU CCR: BFHFMIGN (Bitfield-Mask: 0x01)
#define CPU_CCR_BFHFMIGN_Pos (8UL) |
CPU CCR: BFHFMIGN (Bit 8)
#define CPU_CCR_DIV_0_TRP_Msk (0x10UL) |
CPU CCR: DIV_0_TRP (Bitfield-Mask: 0x01)
#define CPU_CCR_DIV_0_TRP_Pos (4UL) |
CPU CCR: DIV_0_TRP (Bit 4)
#define CPU_CCR_NONBASETHRDENA_Msk (0x1UL) |
CPU CCR: NONBASETHRDENA (Bitfield-Mask: 0x01)
#define CPU_CCR_NONBASETHRDENA_Pos (0UL) |
CPU CCR: NONBASETHRDENA (Bit 0)
#define CPU_CCR_STKALIGN_Msk (0x200UL) |
CPU CCR: STKALIGN (Bitfield-Mask: 0x01)
#define CPU_CCR_STKALIGN_Pos (9UL) |
CPU CCR: STKALIGN (Bit 9)
#define CPU_CCR_UNALIGN_TRP_Msk (0x8UL) |
CPU CCR: UNALIGN_TRP (Bitfield-Mask: 0x01)
#define CPU_CCR_UNALIGN_TRP_Pos (3UL) |
CPU CCR: UNALIGN_TRP (Bit 3)
#define CPU_CCR_USERSETMPEND_Msk (0x2UL) |
CPU CCR: USERSETMPEND (Bitfield-Mask: 0x01)
#define CPU_CCR_USERSETMPEND_Pos (1UL) |
CPU CCR: USERSETMPEND (Bit 1)
#define CPU_CFSR_BFARVALID_Msk (0x8000UL) |
CPU CFSR: BFARVALID (Bitfield-Mask: 0x01)
#define CPU_CFSR_BFARVALID_Pos (15UL) |
CPU CFSR: BFARVALID (Bit 15)
#define CPU_CFSR_DACCVIOL_Msk (0x2UL) |
CPU CFSR: DACCVIOL (Bitfield-Mask: 0x01)
#define CPU_CFSR_DACCVIOL_Pos (1UL) |
CPU CFSR: DACCVIOL (Bit 1)
#define CPU_CFSR_DIVBYZERO_Msk (0x2000000UL) |
CPU CFSR: DIVBYZERO (Bitfield-Mask: 0x01)
#define CPU_CFSR_DIVBYZERO_Pos (25UL) |
CPU CFSR: DIVBYZERO (Bit 25)
#define CPU_CFSR_IACCVIOL_Msk (0x1UL) |
CPU CFSR: IACCVIOL (Bitfield-Mask: 0x01)
#define CPU_CFSR_IACCVIOL_Pos (0UL) |
CPU CFSR: IACCVIOL (Bit 0)
#define CPU_CFSR_IBUSERR_Msk (0x100UL) |
CPU CFSR: IBUSERR (Bitfield-Mask: 0x01)
#define CPU_CFSR_IBUSERR_Pos (8UL) |
CPU CFSR: IBUSERR (Bit 8)
#define CPU_CFSR_IMPRECISERR_Msk (0x400UL) |
CPU CFSR: IMPRECISERR (Bitfield-Mask: 0x01)
#define CPU_CFSR_IMPRECISERR_Pos (10UL) |
CPU CFSR: IMPRECISERR (Bit 10)
#define CPU_CFSR_INVPC_Msk (0x40000UL) |
CPU CFSR: INVPC (Bitfield-Mask: 0x01)
#define CPU_CFSR_INVPC_Pos (18UL) |
CPU CFSR: INVPC (Bit 18)
#define CPU_CFSR_INVSTATE_Msk (0x20000UL) |
CPU CFSR: INVSTATE (Bitfield-Mask: 0x01)
#define CPU_CFSR_INVSTATE_Pos (17UL) |
CPU CFSR: INVSTATE (Bit 17)
#define CPU_CFSR_MMARVALID_Msk (0x80UL) |
CPU CFSR: MMARVALID (Bitfield-Mask: 0x01)
#define CPU_CFSR_MMARVALID_Pos (7UL) |
CPU CFSR: MMARVALID (Bit 7)
#define CPU_CFSR_MSTERR_Msk (0x10UL) |
CPU CFSR: MSTERR (Bitfield-Mask: 0x01)
#define CPU_CFSR_MSTERR_Pos (4UL) |
CPU CFSR: MSTERR (Bit 4)
#define CPU_CFSR_MUNSTKERR_Msk (0x8UL) |
CPU CFSR: MUNSTKERR (Bitfield-Mask: 0x01)
#define CPU_CFSR_MUNSTKERR_Pos (3UL) |
CPU CFSR: MUNSTKERR (Bit 3)
#define CPU_CFSR_NOCP_Msk (0x80000UL) |
CPU CFSR: NOCP (Bitfield-Mask: 0x01)
#define CPU_CFSR_NOCP_Pos (19UL) |
CPU CFSR: NOCP (Bit 19)
#define CPU_CFSR_PRECISERR_Msk (0x200UL) |
CPU CFSR: PRECISERR (Bitfield-Mask: 0x01)
#define CPU_CFSR_PRECISERR_Pos (9UL) |
CPU CFSR: PRECISERR (Bit 9)
#define CPU_CFSR_STKERR_Msk (0x1000UL) |
CPU CFSR: STKERR (Bitfield-Mask: 0x01)
#define CPU_CFSR_STKERR_Pos (12UL) |
CPU CFSR: STKERR (Bit 12)
#define CPU_CFSR_UNALIGNED_Msk (0x1000000UL) |
CPU CFSR: UNALIGNED (Bitfield-Mask: 0x01)
#define CPU_CFSR_UNALIGNED_Pos (24UL) |
CPU CFSR: UNALIGNED (Bit 24)
#define CPU_CFSR_UNDEFINSTR_Msk (0x10000UL) |
CPU CFSR: UNDEFINSTR (Bitfield-Mask: 0x01)
#define CPU_CFSR_UNDEFINSTR_Pos (16UL) |
CPU CFSR: UNDEFINSTR (Bit 16)
#define CPU_CFSR_UNSTKERR_Msk (0x800UL) |
CPU CFSR: UNSTKERR (Bitfield-Mask: 0x01)
#define CPU_CFSR_UNSTKERR_Pos (11UL) |
CPU CFSR: UNSTKERR (Bit 11)
#define CPU_CPUID_ARCHITECTURE_Msk (0xf0000UL) |
CPU CPUID: ARCHITECTURE (Bitfield-Mask: 0x0f)
#define CPU_CPUID_ARCHITECTURE_Pos (16UL) |
CPU CPUID: ARCHITECTURE (Bit 16)
#define CPU_CPUID_IMPLEMENTER_Msk (0xff000000UL) |
CPU CPUID: IMPLEMENTER (Bitfield-Mask: 0xff)
#define CPU_CPUID_IMPLEMENTER_Pos (24UL) |
CPU CPUID: IMPLEMENTER (Bit 24)
#define CPU_CPUID_PARTNO_Msk (0xfff0UL) |
CPU CPUID: PARTNO (Bitfield-Mask: 0xfff)
#define CPU_CPUID_PARTNO_Pos (4UL) |
CPU CPUID: PARTNO (Bit 4)
#define CPU_CPUID_REVISION_Msk (0xfUL) |
CPU CPUID: REVISION (Bitfield-Mask: 0x0f)
#define CPU_CPUID_REVISION_Pos (0UL) |
CPU CPUID: REVISION (Bit 0)
#define CPU_CPUID_VARIANT_Msk (0xf00000UL) |
CPU CPUID: VARIANT (Bitfield-Mask: 0x0f)
#define CPU_CPUID_VARIANT_Pos (20UL) |
CPU CPUID: VARIANT (Bit 20)
#define CPU_DFSR_BKPT_Msk (0x2UL) |
CPU DFSR: BKPT (Bitfield-Mask: 0x01)
#define CPU_DFSR_BKPT_Pos (1UL) |
CPU DFSR: BKPT (Bit 1)
#define CPU_DFSR_DWTTRAP_Msk (0x4UL) |
CPU DFSR: DWTTRAP (Bitfield-Mask: 0x01)
#define CPU_DFSR_DWTTRAP_Pos (2UL) |
CPU DFSR: DWTTRAP (Bit 2)
#define CPU_DFSR_EXTERNAL_Msk (0x10UL) |
CPU DFSR: EXTERNAL (Bitfield-Mask: 0x01)
#define CPU_DFSR_EXTERNAL_Pos (4UL) |
CPU DFSR: EXTERNAL (Bit 4)
#define CPU_DFSR_HALTED_Msk (0x1UL) |
CPU DFSR: HALTED (Bitfield-Mask: 0x01)
#define CPU_DFSR_HALTED_Pos (0UL) |
CPU DFSR: HALTED (Bit 0)
#define CPU_DFSR_VCATCH_Msk (0x8UL) |
CPU DFSR: VCATCH (Bitfield-Mask: 0x01)
#define CPU_DFSR_VCATCH_Pos (3UL) |
CPU DFSR: VCATCH (Bit 3)
#define CPU_HFSR_DEBUGEVT_Msk (0x80000000UL) |
CPU HFSR: DEBUGEVT (Bitfield-Mask: 0x01)
#define CPU_HFSR_DEBUGEVT_Pos (31UL) |
CPU HFSR: DEBUGEVT (Bit 31)
#define CPU_HFSR_FORCED_Msk (0x40000000UL) |
CPU HFSR: FORCED (Bitfield-Mask: 0x01)
#define CPU_HFSR_FORCED_Pos (30UL) |
CPU HFSR: FORCED (Bit 30)
#define CPU_HFSR_VECTTBL_Msk (0x2UL) |
CPU HFSR: VECTTBL (Bitfield-Mask: 0x01)
#define CPU_HFSR_VECTTBL_Pos (1UL) |
CPU HFSR: VECTTBL (Bit 1)
#define CPU_ICSR_ISRPENDING_Msk (0x400000UL) |
CPU ICSR: ISRPENDING (Bitfield-Mask: 0x01)
#define CPU_ICSR_ISRPENDING_Pos (22UL) |
CPU ICSR: ISRPENDING (Bit 22)
#define CPU_ICSR_ISRPREEMPT_Msk (0x800000UL) |
CPU ICSR: ISRPREEMPT (Bitfield-Mask: 0x01)
#define CPU_ICSR_ISRPREEMPT_Pos (23UL) |
CPU ICSR: ISRPREEMPT (Bit 23)
#define CPU_ICSR_NMIPENDSET_Msk (0x80000000UL) |
CPU ICSR: NMIPENDSET (Bitfield-Mask: 0x01)
#define CPU_ICSR_NMIPENDSET_Pos (31UL) |
CPU ICSR: NMIPENDSET (Bit 31)
#define CPU_ICSR_PENDSTCLR_Msk (0x2000000UL) |
CPU ICSR: PENDSTCLR (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSTCLR_Pos (25UL) |
CPU ICSR: PENDSTCLR (Bit 25)
#define CPU_ICSR_PENDSTSET_Msk (0x4000000UL) |
CPU ICSR: PENDSTSET (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSTSET_Pos (26UL) |
CPU ICSR: PENDSTSET (Bit 26)
#define CPU_ICSR_PENDSVCLR_Msk (0x8000000UL) |
CPU ICSR: PENDSVCLR (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSVCLR_Pos (27UL) |
CPU ICSR: PENDSVCLR (Bit 27)
#define CPU_ICSR_PENDSVSET_Msk (0x10000000UL) |
CPU ICSR: PENDSVSET (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSVSET_Pos (28UL) |
CPU ICSR: PENDSVSET (Bit 28)
#define CPU_ICSR_RETTOBASE_Msk (0x800UL) |
CPU ICSR: RETTOBASE (Bitfield-Mask: 0x01)
#define CPU_ICSR_RETTOBASE_Pos (11UL) |
CPU ICSR: RETTOBASE (Bit 11)
#define CPU_ICSR_VECTACTIVE_Msk (0x1ffUL) |
CPU ICSR: VECTACTIVE (Bitfield-Mask: 0x1ff)
#define CPU_ICSR_VECTACTIVE_Pos (0UL) |
CPU ICSR: VECTACTIVE (Bit 0)
#define CPU_ICSR_VECTPENDING_Msk (0x1ff000UL) |
CPU ICSR: VECTPENDING (Bitfield-Mask: 0x1ff)
#define CPU_ICSR_VECTPENDING_Pos (12UL) |
CPU ICSR: VECTPENDING (Bit 12)
#define CPU_ICT_INTLINESNUM_Msk (0x1fUL) |
CPU ICT: INTLINESNUM (Bitfield-Mask: 0x1f)
#define CPU_ICT_INTLINESNUM_Pos (0UL) |
CPU ICT: INTLINESNUM (Bit 0)
#define CPU_MMFAR_ADDRESS_Msk (0xffffffffUL) |
CPU MMFAR: ADDRESS (Bitfield-Mask: 0xffffffff)
#define CPU_MMFAR_ADDRESS_Pos (0UL) |
CPU MMFAR: ADDRESS (Bit 0)
#define CPU_NVIC_IABR0_Int_ADC1_Msk (0x8UL) |
CPU NVIC_IABR0: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_ADC1_Pos (3UL) |
CPU NVIC_IABR0: Int_ADC1 (Bit 3)
#define CPU_NVIC_IABR0_Int_ADC2_Msk (0x4UL) |
CPU NVIC_IABR0: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_ADC2_Pos (2UL) |
CPU NVIC_IABR0: Int_ADC2 (Bit 2)
#define CPU_NVIC_IABR0_Int_BDRV_Msk (0x4000UL) |
CPU NVIC_IABR0: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_BDRV_Pos (14UL) |
CPU NVIC_IABR0: Int_BDRV (Bit 14)
#define CPU_NVIC_IABR0_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_IABR0: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_IABR0: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_IABR0_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_IABR0: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_IABR0: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_IABR0_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_IABR0: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_IABR0: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_IABR0_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_IABR0: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_IABR0: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_IABR0_Int_DMA_Msk (0x8000UL) |
CPU NVIC_IABR0: Int_DMA (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_DMA_Pos (15UL) |
CPU NVIC_IABR0: Int_DMA (Bit 15)
#define CPU_NVIC_IABR0_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_IABR0: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_EXINT0_Pos (12UL) |
CPU NVIC_IABR0: Int_EXINT0 (Bit 12)
#define CPU_NVIC_IABR0_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_IABR0: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_EXINT1_Pos (13UL) |
CPU NVIC_IABR0: Int_EXINT1 (Bit 13)
#define CPU_NVIC_IABR0_Int_GPT1_Msk (0x1UL) |
CPU NVIC_IABR0: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_GPT1_Pos (0UL) |
CPU NVIC_IABR0: Int_GPT1 (Bit 0)
#define CPU_NVIC_IABR0_Int_GPT2_Msk (0x2UL) |
CPU NVIC_IABR0: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_GPT2_Pos (1UL) |
CPU NVIC_IABR0: Int_GPT2 (Bit 1)
#define CPU_NVIC_IABR0_Int_SSC1_Msk (0x100UL) |
CPU NVIC_IABR0: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_SSC1_Pos (8UL) |
CPU NVIC_IABR0: Int_SSC1 (Bit 8)
#define CPU_NVIC_IABR0_Int_SSC2_Msk (0x200UL) |
CPU NVIC_IABR0: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_SSC2_Pos (9UL) |
CPU NVIC_IABR0: Int_SSC2 (Bit 9)
#define CPU_NVIC_IABR0_Int_UART1_Msk (0x400UL) |
CPU NVIC_IABR0: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_UART1_Pos (10UL) |
CPU NVIC_IABR0: Int_UART1 (Bit 10)
#define CPU_NVIC_IABR0_Int_UART2_Msk (0x800UL) |
CPU NVIC_IABR0: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_IABR0_Int_UART2_Pos (11UL) |
CPU NVIC_IABR0: Int_UART2 (Bit 11)
#define CPU_NVIC_ICER0_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ICER0: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_ADC1_Pos (3UL) |
CPU NVIC_ICER0: Int_ADC1 (Bit 3)
#define CPU_NVIC_ICER0_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ICER0: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_ADC2_Pos (2UL) |
CPU NVIC_ICER0: Int_ADC2 (Bit 2)
#define CPU_NVIC_ICER0_Int_BDRV_Msk (0x4000UL) |
CPU NVIC_ICER0: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_BDRV_Pos (14UL) |
CPU NVIC_ICER0: Int_BDRV (Bit 14)
#define CPU_NVIC_ICER0_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ICER0: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ICER0: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ICER0_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ICER0: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ICER0: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ICER0_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ICER0: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ICER0: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ICER0_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ICER0: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ICER0: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ICER0_Int_DMA_Msk (0x8000UL) |
CPU NVIC_ICER0: Int_DMA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_DMA_Pos (15UL) |
CPU NVIC_ICER0: Int_DMA (Bit 15)
#define CPU_NVIC_ICER0_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ICER0: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_EXINT0_Pos (12UL) |
CPU NVIC_ICER0: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ICER0_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ICER0: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_EXINT1_Pos (13UL) |
CPU NVIC_ICER0: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ICER0_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ICER0: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_GPT1_Pos (0UL) |
CPU NVIC_ICER0: Int_GPT1 (Bit 0)
#define CPU_NVIC_ICER0_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ICER0: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_GPT2_Pos (1UL) |
CPU NVIC_ICER0: Int_GPT2 (Bit 1)
#define CPU_NVIC_ICER0_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ICER0: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_SSC1_Pos (8UL) |
CPU NVIC_ICER0: Int_SSC1 (Bit 8)
#define CPU_NVIC_ICER0_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ICER0: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_SSC2_Pos (9UL) |
CPU NVIC_ICER0: Int_SSC2 (Bit 9)
#define CPU_NVIC_ICER0_Int_UART1_Msk (0x400UL) |
CPU NVIC_ICER0: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_UART1_Pos (10UL) |
CPU NVIC_ICER0: Int_UART1 (Bit 10)
#define CPU_NVIC_ICER0_Int_UART2_Msk (0x800UL) |
CPU NVIC_ICER0: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER0_Int_UART2_Pos (11UL) |
CPU NVIC_ICER0: Int_UART2 (Bit 11)
#define CPU_NVIC_ICPR0_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ICPR0: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_ADC1_Pos (3UL) |
CPU NVIC_ICPR0: Int_ADC1 (Bit 3)
#define CPU_NVIC_ICPR0_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ICPR0: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_ADC2_Pos (2UL) |
CPU NVIC_ICPR0: Int_ADC2 (Bit 2)
#define CPU_NVIC_ICPR0_Int_BDRV_Msk (0x4000UL) |
CPU NVIC_ICPR0: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_BDRV_Pos (14UL) |
CPU NVIC_ICPR0: Int_BDRV (Bit 14)
#define CPU_NVIC_ICPR0_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ICPR0: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ICPR0: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ICPR0_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ICPR0: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ICPR0: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ICPR0_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ICPR0: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ICPR0: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ICPR0_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ICPR0: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ICPR0: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ICPR0_Int_DMA_Msk (0x8000UL) |
CPU NVIC_ICPR0: Int_DMA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_DMA_Pos (15UL) |
CPU NVIC_ICPR0: Int_DMA (Bit 15)
#define CPU_NVIC_ICPR0_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ICPR0: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_EXINT0_Pos (12UL) |
CPU NVIC_ICPR0: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ICPR0_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ICPR0: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_EXINT1_Pos (13UL) |
CPU NVIC_ICPR0: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ICPR0_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ICPR0: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_GPT1_Pos (0UL) |
CPU NVIC_ICPR0: Int_GPT1 (Bit 0)
#define CPU_NVIC_ICPR0_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ICPR0: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_GPT2_Pos (1UL) |
CPU NVIC_ICPR0: Int_GPT2 (Bit 1)
#define CPU_NVIC_ICPR0_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ICPR0: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_SSC1_Pos (8UL) |
CPU NVIC_ICPR0: Int_SSC1 (Bit 8)
#define CPU_NVIC_ICPR0_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ICPR0: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_SSC2_Pos (9UL) |
CPU NVIC_ICPR0: Int_SSC2 (Bit 9)
#define CPU_NVIC_ICPR0_Int_UART1_Msk (0x400UL) |
CPU NVIC_ICPR0: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_UART1_Pos (10UL) |
CPU NVIC_ICPR0: Int_UART1 (Bit 10)
#define CPU_NVIC_ICPR0_Int_UART2_Msk (0x800UL) |
CPU NVIC_ICPR0: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR0_Int_UART2_Pos (11UL) |
CPU NVIC_ICPR0: Int_UART2 (Bit 11)
#define CPU_NVIC_IPR0_PRI_ADC1_Msk (0xff000000UL) |
CPU NVIC_IPR0: PRI_ADC1 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR0_PRI_ADC1_Pos (24UL) |
CPU NVIC_IPR0: PRI_ADC1 (Bit 24)
#define CPU_NVIC_IPR0_PRI_ADC2_Msk (0xff0000UL) |
CPU NVIC_IPR0: PRI_ADC2 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR0_PRI_ADC2_Pos (16UL) |
CPU NVIC_IPR0: PRI_ADC2 (Bit 16)
#define CPU_NVIC_IPR0_PRI_GPT1_Msk (0xffUL) |
CPU NVIC_IPR0: PRI_GPT1 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR0_PRI_GPT1_Pos (0UL) |
CPU NVIC_IPR0: PRI_GPT1 (Bit 0)
#define CPU_NVIC_IPR0_PRI_GPT2_Msk (0xff00UL) |
CPU NVIC_IPR0: PRI_GPT2 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR0_PRI_GPT2_Pos (8UL) |
CPU NVIC_IPR0: PRI_GPT2 (Bit 8)
#define CPU_NVIC_IPR1_PRI_CCU6SR0_Msk (0xffUL) |
CPU NVIC_IPR1: PRI_CCU6SR0 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR1_PRI_CCU6SR0_Pos (0UL) |
CPU NVIC_IPR1: PRI_CCU6SR0 (Bit 0)
#define CPU_NVIC_IPR1_PRI_CCU6SR1_Msk (0xff00UL) |
CPU NVIC_IPR1: PRI_CCU6SR1 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR1_PRI_CCU6SR1_Pos (8UL) |
CPU NVIC_IPR1: PRI_CCU6SR1 (Bit 8)
#define CPU_NVIC_IPR1_PRI_CCU6SR2_Msk (0xff0000UL) |
CPU NVIC_IPR1: PRI_CCU6SR2 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR1_PRI_CCU6SR2_Pos (16UL) |
CPU NVIC_IPR1: PRI_CCU6SR2 (Bit 16)
#define CPU_NVIC_IPR1_PRI_CCU6SR3_Msk (0xff000000UL) |
CPU NVIC_IPR1: PRI_CCU6SR3 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR1_PRI_CCU6SR3_Pos (24UL) |
CPU NVIC_IPR1: PRI_CCU6SR3 (Bit 24)
#define CPU_NVIC_IPR2_PRI_SSC1_Msk (0xffUL) |
CPU NVIC_IPR2: PRI_SSC1 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR2_PRI_SSC1_Pos (0UL) |
CPU NVIC_IPR2: PRI_SSC1 (Bit 0)
#define CPU_NVIC_IPR2_PRI_SSC2_Msk (0xff00UL) |
CPU NVIC_IPR2: PRI_SSC2 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR2_PRI_SSC2_Pos (8UL) |
CPU NVIC_IPR2: PRI_SSC2 (Bit 8)
#define CPU_NVIC_IPR2_PRI_UART1_Msk (0xff0000UL) |
CPU NVIC_IPR2: PRI_UART1 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR2_PRI_UART1_Pos (16UL) |
CPU NVIC_IPR2: PRI_UART1 (Bit 16)
#define CPU_NVIC_IPR2_PRI_UART2_Msk (0xff000000UL) |
CPU NVIC_IPR2: PRI_UART2 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR2_PRI_UART2_Pos (24UL) |
CPU NVIC_IPR2: PRI_UART2 (Bit 24)
#define CPU_NVIC_IPR3_PRI_BDRV_Msk (0xff0000UL) |
CPU NVIC_IPR3: PRI_BDRV (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR3_PRI_BDRV_Pos (16UL) |
CPU NVIC_IPR3: PRI_BDRV (Bit 16)
#define CPU_NVIC_IPR3_PRI_DMA_Msk (0xff000000UL) |
CPU NVIC_IPR3: PRI_DMA (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR3_PRI_DMA_Pos (24UL) |
CPU NVIC_IPR3: PRI_DMA (Bit 24)
#define CPU_NVIC_IPR3_PRI_EXINT0_Msk (0xffUL) |
CPU NVIC_IPR3: PRI_EXINT0 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR3_PRI_EXINT0_Pos (0UL) |
CPU NVIC_IPR3: PRI_EXINT0 (Bit 0)
#define CPU_NVIC_IPR3_PRI_EXINT1_Msk (0xff00UL) |
CPU NVIC_IPR3: PRI_EXINT1 (Bitfield-Mask: 0xff)
#define CPU_NVIC_IPR3_PRI_EXINT1_Pos (8UL) |
CPU NVIC_IPR3: PRI_EXINT1 (Bit 8)
#define CPU_NVIC_ISER0_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ISER0: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_ADC1_Pos (3UL) |
CPU NVIC_ISER0: Int_ADC1 (Bit 3)
#define CPU_NVIC_ISER0_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ISER0: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_ADC2_Pos (2UL) |
CPU NVIC_ISER0: Int_ADC2 (Bit 2)
#define CPU_NVIC_ISER0_Int_BDRV_Msk (0x4000UL) |
CPU NVIC_ISER0: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_BDRV_Pos (14UL) |
CPU NVIC_ISER0: Int_BDRV (Bit 14)
#define CPU_NVIC_ISER0_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ISER0: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ISER0: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ISER0_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ISER0: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ISER0: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ISER0_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ISER0: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ISER0: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ISER0_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ISER0: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ISER0: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ISER0_Int_DMA_Msk (0x8000UL) |
CPU NVIC_ISER0: Int_DMA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_DMA_Pos (15UL) |
CPU NVIC_ISER0: Int_DMA (Bit 15)
#define CPU_NVIC_ISER0_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ISER0: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_EXINT0_Pos (12UL) |
CPU NVIC_ISER0: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ISER0_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ISER0: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_EXINT1_Pos (13UL) |
CPU NVIC_ISER0: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ISER0_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ISER0: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_GPT1_Pos (0UL) |
CPU NVIC_ISER0: Int_GPT1 (Bit 0)
#define CPU_NVIC_ISER0_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ISER0: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_GPT2_Pos (1UL) |
CPU NVIC_ISER0: Int_GPT2 (Bit 1)
#define CPU_NVIC_ISER0_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ISER0: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_SSC1_Pos (8UL) |
CPU NVIC_ISER0: Int_SSC1 (Bit 8)
#define CPU_NVIC_ISER0_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ISER0: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_SSC2_Pos (9UL) |
CPU NVIC_ISER0: Int_SSC2 (Bit 9)
#define CPU_NVIC_ISER0_Int_UART1_Msk (0x400UL) |
CPU NVIC_ISER0: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_UART1_Pos (10UL) |
CPU NVIC_ISER0: Int_UART1 (Bit 10)
#define CPU_NVIC_ISER0_Int_UART2_Msk (0x800UL) |
CPU NVIC_ISER0: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER0_Int_UART2_Pos (11UL) |
CPU NVIC_ISER0: Int_UART2 (Bit 11)
#define CPU_NVIC_ISPR0_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ISPR0: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_ADC1_Pos (3UL) |
CPU NVIC_ISPR0: Int_ADC1 (Bit 3)
#define CPU_NVIC_ISPR0_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ISPR0: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_ADC2_Pos (2UL) |
CPU NVIC_ISPR0: Int_ADC2 (Bit 2)
#define CPU_NVIC_ISPR0_Int_BDRV_Msk (0x4000UL) |
CPU NVIC_ISPR0: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_BDRV_Pos (14UL) |
CPU NVIC_ISPR0: Int_BDRV (Bit 14)
#define CPU_NVIC_ISPR0_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ISPR0: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ISPR0: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ISPR0_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ISPR0: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ISPR0: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ISPR0_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ISPR0: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ISPR0: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ISPR0_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ISPR0: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ISPR0: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ISPR0_Int_DMA_Msk (0x8000UL) |
CPU NVIC_ISPR0: Int_DMA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_DMA_Pos (15UL) |
CPU NVIC_ISPR0: Int_DMA (Bit 15)
#define CPU_NVIC_ISPR0_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ISPR0: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_EXINT0_Pos (12UL) |
CPU NVIC_ISPR0: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ISPR0_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ISPR0: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_EXINT1_Pos (13UL) |
CPU NVIC_ISPR0: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ISPR0_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ISPR0: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_GPT1_Pos (0UL) |
CPU NVIC_ISPR0: Int_GPT1 (Bit 0)
#define CPU_NVIC_ISPR0_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ISPR0: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_GPT2_Pos (1UL) |
CPU NVIC_ISPR0: Int_GPT2 (Bit 1)
#define CPU_NVIC_ISPR0_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ISPR0: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_SSC1_Pos (8UL) |
CPU NVIC_ISPR0: Int_SSC1 (Bit 8)
#define CPU_NVIC_ISPR0_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ISPR0: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_SSC2_Pos (9UL) |
CPU NVIC_ISPR0: Int_SSC2 (Bit 9)
#define CPU_NVIC_ISPR0_Int_UART1_Msk (0x400UL) |
CPU NVIC_ISPR0: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_UART1_Pos (10UL) |
CPU NVIC_ISPR0: Int_UART1 (Bit 10)
#define CPU_NVIC_ISPR0_Int_UART2_Msk (0x800UL) |
CPU NVIC_ISPR0: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR0_Int_UART2_Pos (11UL) |
CPU NVIC_ISPR0: Int_UART2 (Bit 11)
#define CPU_SCR_SEVONPEND_Msk (0x10UL) |
CPU SCR: SEVONPEND (Bitfield-Mask: 0x01)
#define CPU_SCR_SEVONPEND_Pos (4UL) |
CPU SCR: SEVONPEND (Bit 4)
#define CPU_SCR_SLEEPDEEP_Msk (0x4UL) |
CPU SCR: SLEEPDEEP (Bitfield-Mask: 0x01)
#define CPU_SCR_SLEEPDEEP_Pos (2UL) |
CPU SCR: SLEEPDEEP (Bit 2)
#define CPU_SCR_SLEEPONEXIT_Msk (0x2UL) |
CPU SCR: SLEEPONEXIT (Bitfield-Mask: 0x01)
#define CPU_SCR_SLEEPONEXIT_Pos (1UL) |
CPU SCR: SLEEPONEXIT (Bit 1)
#define CPU_SHCSR_BUSFAULTACT_Msk (0x2UL) |
CPU SHCSR: BUSFAULTACT (Bitfield-Mask: 0x01)
#define CPU_SHCSR_BUSFAULTACT_Pos (1UL) |
CPU SHCSR: BUSFAULTACT (Bit 1)
#define CPU_SHCSR_BUSFAULTENA_Msk (0x20000UL) |
CPU SHCSR: BUSFAULTENA (Bitfield-Mask: 0x01)
#define CPU_SHCSR_BUSFAULTENA_Pos (17UL) |
CPU SHCSR: BUSFAULTENA (Bit 17)
#define CPU_SHCSR_BUSFAULTPENDED_Msk (0x4000UL) |
CPU SHCSR: BUSFAULTPENDED (Bitfield-Mask: 0x01)
#define CPU_SHCSR_BUSFAULTPENDED_Pos (14UL) |
CPU SHCSR: BUSFAULTPENDED (Bit 14)
#define CPU_SHCSR_MEMFAULTACT_Msk (0x1UL) |
CPU SHCSR: MEMFAULTACT (Bitfield-Mask: 0x01)
#define CPU_SHCSR_MEMFAULTACT_Pos (0UL) |
CPU SHCSR: MEMFAULTACT (Bit 0)
#define CPU_SHCSR_MEMFAULTENA_Msk (0x10000UL) |
CPU SHCSR: MEMFAULTENA (Bitfield-Mask: 0x01)
#define CPU_SHCSR_MEMFAULTENA_Pos (16UL) |
CPU SHCSR: MEMFAULTENA (Bit 16)
#define CPU_SHCSR_MEMFAULTPENDED_Msk (0x2000UL) |
CPU SHCSR: MEMFAULTPENDED (Bitfield-Mask: 0x01)
#define CPU_SHCSR_MEMFAULTPENDED_Pos (13UL) |
CPU SHCSR: MEMFAULTPENDED (Bit 13)
#define CPU_SHCSR_MONITORACT_Msk (0x100UL) |
CPU SHCSR: MONITORACT (Bitfield-Mask: 0x01)
#define CPU_SHCSR_MONITORACT_Pos (8UL) |
CPU SHCSR: MONITORACT (Bit 8)
#define CPU_SHCSR_PENDSVACT_Msk (0x400UL) |
CPU SHCSR: PENDSVACT (Bitfield-Mask: 0x01)
#define CPU_SHCSR_PENDSVACT_Pos (10UL) |
CPU SHCSR: PENDSVACT (Bit 10)
#define CPU_SHCSR_SVCALLACT_Msk (0x80UL) |
CPU SHCSR: SVCALLACT (Bitfield-Mask: 0x01)
#define CPU_SHCSR_SVCALLACT_Pos (7UL) |
CPU SHCSR: SVCALLACT (Bit 7)
#define CPU_SHCSR_SVCALLPENDED_Msk (0x8000UL) |
CPU SHCSR: SVCALLPENDED (Bitfield-Mask: 0x01)
#define CPU_SHCSR_SVCALLPENDED_Pos (15UL) |
CPU SHCSR: SVCALLPENDED (Bit 15)
#define CPU_SHCSR_SYSTICKACT_Msk (0x800UL) |
CPU SHCSR: SYSTICKACT (Bitfield-Mask: 0x01)
#define CPU_SHCSR_SYSTICKACT_Pos (11UL) |
CPU SHCSR: SYSTICKACT (Bit 11)
#define CPU_SHCSR_USGFAULTACT_Msk (0x8UL) |
CPU SHCSR: USGFAULTACT (Bitfield-Mask: 0x01)
#define CPU_SHCSR_USGFAULTACT_Pos (3UL) |
CPU SHCSR: USGFAULTACT (Bit 3)
#define CPU_SHCSR_USGFAULTENA_Msk (0x40000UL) |
CPU SHCSR: USGFAULTENA (Bitfield-Mask: 0x01)
#define CPU_SHCSR_USGFAULTENA_Pos (18UL) |
CPU SHCSR: USGFAULTENA (Bit 18)
#define CPU_SHCSR_USGFAULTPENDED_Msk (0x1000UL) |
CPU SHCSR: USGFAULTPENDED (Bitfield-Mask: 0x01)
#define CPU_SHCSR_USGFAULTPENDED_Pos (12UL) |
CPU SHCSR: USGFAULTPENDED (Bit 12)
#define CPU_SHPR1_PRI_4_Msk (0xffUL) |
CPU SHPR1: PRI_4 (Bitfield-Mask: 0xff)
#define CPU_SHPR1_PRI_4_Pos (0UL) |
CPU SHPR1: PRI_4 (Bit 0)
#define CPU_SHPR1_PRI_5_Msk (0xff00UL) |
CPU SHPR1: PRI_5 (Bitfield-Mask: 0xff)
#define CPU_SHPR1_PRI_5_Pos (8UL) |
CPU SHPR1: PRI_5 (Bit 8)
#define CPU_SHPR1_PRI_6_Msk (0xff0000UL) |
CPU SHPR1: PRI_6 (Bitfield-Mask: 0xff)
#define CPU_SHPR1_PRI_6_Pos (16UL) |
CPU SHPR1: PRI_6 (Bit 16)
#define CPU_SHPR1_PRI_7_Msk (0xff000000UL) |
CPU SHPR1: PRI_7 (Bitfield-Mask: 0xff)
#define CPU_SHPR1_PRI_7_Pos (24UL) |
CPU SHPR1: PRI_7 (Bit 24)
#define CPU_SHPR2_PRI_10_Msk (0xff0000UL) |
CPU SHPR2: PRI_10 (Bitfield-Mask: 0xff)
#define CPU_SHPR2_PRI_10_Pos (16UL) |
CPU SHPR2: PRI_10 (Bit 16)
#define CPU_SHPR2_PRI_11_Msk (0xff000000UL) |
CPU SHPR2: PRI_11 (Bitfield-Mask: 0xff)
#define CPU_SHPR2_PRI_11_Pos (24UL) |
CPU SHPR2: PRI_11 (Bit 24)
#define CPU_SHPR2_PRI_8_Msk (0xffUL) |
CPU SHPR2: PRI_8 (Bitfield-Mask: 0xff)
#define CPU_SHPR2_PRI_8_Pos (0UL) |
CPU SHPR2: PRI_8 (Bit 0)
#define CPU_SHPR2_PRI_9_Msk (0xff00UL) |
CPU SHPR2: PRI_9 (Bitfield-Mask: 0xff)
#define CPU_SHPR2_PRI_9_Pos (8UL) |
CPU SHPR2: PRI_9 (Bit 8)
#define CPU_SHPR3_PRI_12_Msk (0xffUL) |
CPU SHPR3: PRI_12 (Bitfield-Mask: 0xff)
#define CPU_SHPR3_PRI_12_Pos (0UL) |
CPU SHPR3: PRI_12 (Bit 0)
#define CPU_SHPR3_PRI_13_Msk (0xff00UL) |
CPU SHPR3: PRI_13 (Bitfield-Mask: 0xff)
#define CPU_SHPR3_PRI_13_Pos (8UL) |
CPU SHPR3: PRI_13 (Bit 8)
#define CPU_SHPR3_PRI_14_Msk (0xff0000UL) |
CPU SHPR3: PRI_14 (Bitfield-Mask: 0xff)
#define CPU_SHPR3_PRI_14_Pos (16UL) |
CPU SHPR3: PRI_14 (Bit 16)
#define CPU_SHPR3_PRI_15_Msk (0xff000000UL) |
CPU SHPR3: PRI_15 (Bitfield-Mask: 0xff)
#define CPU_SHPR3_PRI_15_Pos (24UL) |
CPU SHPR3: PRI_15 (Bit 24)
#define CPU_SYSTICK_CAL_NOREF_Msk (0x80000000UL) |
CPU SYSTICK_CAL: NOREF (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CAL_NOREF_Pos (31UL) |
CPU SYSTICK_CAL: NOREF (Bit 31)
#define CPU_SYSTICK_CAL_SKEW_Msk (0x40000000UL) |
CPU SYSTICK_CAL: SKEW (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CAL_SKEW_Pos (30UL) |
CPU SYSTICK_CAL: SKEW (Bit 30)
#define CPU_SYSTICK_CAL_TENMS_Msk (0xffffffUL) |
CPU SYSTICK_CAL: TENMS (Bitfield-Mask: 0xffffff)
#define CPU_SYSTICK_CAL_TENMS_Pos (0UL) |
CPU SYSTICK_CAL: TENMS (Bit 0)
#define CPU_SYSTICK_CS_CLKSOURCE_Msk (0x4UL) |
CPU SYSTICK_CS: CLKSOURCE (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CS_CLKSOURCE_Pos (2UL) |
CPU SYSTICK_CS: CLKSOURCE (Bit 2)
#define CPU_SYSTICK_CS_COUNTFLAG_Msk (0x10000UL) |
CPU SYSTICK_CS: COUNTFLAG (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CS_COUNTFLAG_Pos (16UL) |
CPU SYSTICK_CS: COUNTFLAG (Bit 16)
#define CPU_SYSTICK_CS_ENABLE_Msk (0x1UL) |
CPU SYSTICK_CS: ENABLE (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CS_ENABLE_Pos (0UL) |
CPU SYSTICK_CS: ENABLE (Bit 0)
#define CPU_SYSTICK_CS_TICKINT_Msk (0x2UL) |
CPU SYSTICK_CS: TICKINT (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CS_TICKINT_Pos (1UL) |
CPU SYSTICK_CS: TICKINT (Bit 1)
#define CPU_SYSTICK_CUR_CURRENT_Msk (0xffffffUL) |
CPU SYSTICK_CUR: CURRENT (Bitfield-Mask: 0xffffff)
#define CPU_SYSTICK_CUR_CURRENT_Pos (0UL) |
CPU SYSTICK_CUR: CURRENT (Bit 0)
#define CPU_SYSTICK_RL_RELOAD_Msk (0xffffffUL) |
CPU SYSTICK_RL: RELOAD (Bitfield-Mask: 0xffffff)
#define CPU_SYSTICK_RL_RELOAD_Pos (0UL) |
CPU SYSTICK_RL: RELOAD (Bit 0)
#define CPU_VTOR_TBLOFF_Msk (0xffffff80UL) |
CPU VTOR: TBLOFF (Bitfield-Mask: 0x1ffffff)
#define CPU_VTOR_TBLOFF_Pos (7UL) |
CPU VTOR: TBLOFF (Bit 7)
#define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Msk (0xffffffffUL) |
DMA ALT_CTRL_BASE_PTR: ALT_CTRL_BASE_PTR (Bitfield-Mask: 0xffffffff)
#define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Pos (0UL) |
DMA ALT_CTRL_BASE_PTR: ALT_CTRL_BASE_PTR (Bit 0)
#define DMA_CFG_CHN1_PROT_CTRL_Msk (0xe0UL) |
DMA CFG: CHN1_PROT_CTRL (Bitfield-Mask: 0x07)
#define DMA_CFG_CHN1_PROT_CTRL_Pos (5UL) |
DMA CFG: CHN1_PROT_CTRL (Bit 5)
#define DMA_CFG_MASTER_ENABLE_Msk (0x1UL) |
DMA CFG: MASTER_ENABLE (Bitfield-Mask: 0x01)
#define DMA_CFG_MASTER_ENABLE_Pos (0UL) |
DMA CFG: MASTER_ENABLE (Bit 0)
#define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Msk (0x3fffUL) |
DMA CHNL_ENABLE_CLR: CHNL_ENABLE_CLR (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Pos (0UL) |
DMA CHNL_ENABLE_CLR: CHNL_ENABLE_CLR (Bit 0)
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk (0x3fffUL) |
DMA CHNL_ENABLE_SET: CHNL_ENABLE_SET (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos (0UL) |
DMA CHNL_ENABLE_SET: CHNL_ENABLE_SET (Bit 0)
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk (0x3fffUL) |
DMA CHNL_PRI_ALT_CLR: CHNL_PRI_ALT_CLR (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos (0UL) |
DMA CHNL_PRI_ALT_CLR: CHNL_PRI_ALT_CLR (Bit 0)
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk (0x3fffUL) |
DMA CHNL_PRI_ALT_SET: CHNL_PRI_ALT_SET (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos (0UL) |
DMA CHNL_PRI_ALT_SET: CHNL_PRI_ALT_SET (Bit 0)
#define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Msk (0x3fffUL) |
DMA CHNL_PRIORITY_CLR: CHNL_PRIORITY_CLR (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Pos (0UL) |
DMA CHNL_PRIORITY_CLR: CHNL_PRIORITY_CLR (Bit 0)
#define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Msk (0x3fffUL) |
DMA CHNL_PRIORITY_SET: CHNL_PRIORITY_SET (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Pos (0UL) |
DMA CHNL_PRIORITY_SET: CHNL_PRIORITY_SET (Bit 0)
#define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Msk (0x3fffUL) |
DMA CHNL_REQ_MASK_CLR: CHNL_REQ_MASK_CLR (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Pos (0UL) |
DMA CHNL_REQ_MASK_CLR: CHNL_REQ_MASK_CLR (Bit 0)
#define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Msk (0x3fffUL) |
DMA CHNL_REQ_MASK_SET: CHNL_REQ_MASK_SET (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Pos (0UL) |
DMA CHNL_REQ_MASK_SET: CHNL_REQ_MASK_SET (Bit 0)
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk (0x3fffUL) |
DMA CHNL_SW_REQUEST: CHNL_SW_REQUEST (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos (0UL) |
DMA CHNL_SW_REQUEST: CHNL_SW_REQUEST (Bit 0)
#define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Msk (0x3fffUL) |
DMA CHNL_USEBURST_CLR: CHNL_USEBURST_CLR (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Pos (0UL) |
DMA CHNL_USEBURST_CLR: CHNL_USEBURST_CLR (Bit 0)
#define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Msk (0x3fffUL) |
DMA CHNL_USEBURST_SET: CHNL_USEBURST_SET (Bitfield-Mask: 0x3fff)
#define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Pos (0UL) |
DMA CHNL_USEBURST_SET: CHNL_USEBURST_SET (Bit 0)
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk (0xfffffe00UL) |
DMA CTRL_BASE_PTR: CTRL_BASE_PTR (Bitfield-Mask: 0x7fffff)
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos (9UL) |
DMA CTRL_BASE_PTR: CTRL_BASE_PTR (Bit 9)
#define DMA_ERR_CLR_ERR_CLR_Msk (0x1UL) |
DMA ERR_CLR: ERR_CLR (Bitfield-Mask: 0x01)
#define DMA_ERR_CLR_ERR_CLR_Pos (0UL) |
DMA ERR_CLR: ERR_CLR (Bit 0)
#define DMA_STATUS_CHNLS_MINUS1_Msk (0x1f0000UL) |
DMA STATUS: CHNLS_MINUS1 (Bitfield-Mask: 0x1f)
#define DMA_STATUS_CHNLS_MINUS1_Pos (16UL) |
DMA STATUS: CHNLS_MINUS1 (Bit 16)
#define DMA_STATUS_MASTER_ENABLE_Msk (0x1UL) |
DMA STATUS: MASTER_ENABLE (Bitfield-Mask: 0x01)
#define DMA_STATUS_MASTER_ENABLE_Pos (0UL) |
DMA STATUS: MASTER_ENABLE (Bit 0)
#define DMA_STATUS_STATE_Msk (0xf0UL) |
DMA STATUS: STATE (Bitfield-Mask: 0x0f)
#define DMA_STATUS_STATE_Pos (4UL) |
DMA STATUS: STATE (Bit 4)
#define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Msk (0x3fffUL) |
DMA WAITONREQ_STATUS: WAITONREQ_STATUS (Bitfield-Mask: 0x3fff)
#define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Pos (0UL) |
DMA WAITONREQ_STATUS: WAITONREQ_STATUS (Bit 0)
#define GPT12E_CAPREL_CAPREL_Msk (0xffffUL) |
GPT12E CAPREL: CAPREL (Bitfield-Mask: 0xffff)
#define GPT12E_CAPREL_CAPREL_Pos (0UL) |
GPT12E CAPREL: CAPREL (Bit 0)
#define GPT12E_ID_MOD_REV_Msk (0xffUL) |
GPT12E ID: MOD_REV (Bitfield-Mask: 0xff)
#define GPT12E_ID_MOD_REV_Pos (0UL) |
GPT12E ID: MOD_REV (Bit 0)
#define GPT12E_ID_MOD_TYPE_Msk (0xff00UL) |
GPT12E ID: MOD_TYPE (Bitfield-Mask: 0xff)
#define GPT12E_ID_MOD_TYPE_Pos (8UL) |
GPT12E ID: MOD_TYPE (Bit 8)
#define GPT12E_PISEL_ISCAPIN_Msk (0xc000UL) |
GPT12E PISEL: ISCAPIN (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_ISCAPIN_Pos (14UL) |
GPT12E PISEL: ISCAPIN (Bit 14)
#define GPT12E_PISEL_IST2EUD_Msk (0x2UL) |
GPT12E PISEL: IST2EUD (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST2EUD_Pos (1UL) |
GPT12E PISEL: IST2EUD (Bit 1)
#define GPT12E_PISEL_IST2IN_Msk (0x1UL) |
GPT12E PISEL: IST2IN (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST2IN_Pos (0UL) |
GPT12E PISEL: IST2IN (Bit 0)
#define GPT12E_PISEL_IST3EUD_Msk (0x30UL) |
GPT12E PISEL: IST3EUD (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST3EUD_Pos (4UL) |
GPT12E PISEL: IST3EUD (Bit 4)
#define GPT12E_PISEL_IST3IN_Msk (0xcUL) |
GPT12E PISEL: IST3IN (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST3IN_Pos (2UL) |
GPT12E PISEL: IST3IN (Bit 2)
#define GPT12E_PISEL_IST4EUD_Msk (0x300UL) |
GPT12E PISEL: IST4EUD (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST4EUD_Pos (8UL) |
GPT12E PISEL: IST4EUD (Bit 8)
#define GPT12E_PISEL_IST4IN_Msk (0xc0UL) |
GPT12E PISEL: IST4IN (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST4IN_Pos (6UL) |
GPT12E PISEL: IST4IN (Bit 6)
#define GPT12E_PISEL_IST5EUD_Msk (0x800UL) |
GPT12E PISEL: IST5EUD (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST5EUD_Pos (11UL) |
GPT12E PISEL: IST5EUD (Bit 11)
#define GPT12E_PISEL_IST5IN_Msk (0x400UL) |
GPT12E PISEL: IST5IN (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST5IN_Pos (10UL) |
GPT12E PISEL: IST5IN (Bit 10)
#define GPT12E_PISEL_IST6EUD_Msk (0x2000UL) |
GPT12E PISEL: IST6EUD (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST6EUD_Pos (13UL) |
GPT12E PISEL: IST6EUD (Bit 13)
#define GPT12E_PISEL_IST6IN_Msk (0x1000UL) |
GPT12E PISEL: IST6IN (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST6IN_Pos (12UL) |
GPT12E PISEL: IST6IN (Bit 12)
#define GPT12E_T2_T2_Msk (0xffffUL) |
GPT12E T2: T2 (Bitfield-Mask: 0xffff)
#define GPT12E_T2_T2_Pos (0UL) |
GPT12E T2: T2 (Bit 0)
#define GPT12E_T2CON_T2CHDIR_Msk (0x4000UL) |
GPT12E T2CON: T2CHDIR (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2CHDIR_Pos (14UL) |
GPT12E T2CON: T2CHDIR (Bit 14)
#define GPT12E_T2CON_T2EDGE_Msk (0x2000UL) |
GPT12E T2CON: T2EDGE (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2EDGE_Pos (13UL) |
GPT12E T2CON: T2EDGE (Bit 13)
#define GPT12E_T2CON_T2I_Msk (0x7UL) |
GPT12E T2CON: T2I (Bitfield-Mask: 0x07)
#define GPT12E_T2CON_T2I_Pos (0UL) |
GPT12E T2CON: T2I (Bit 0)
#define GPT12E_T2CON_T2IRDIS_Msk (0x1000UL) |
GPT12E T2CON: T2IRDIS (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2IRDIS_Pos (12UL) |
GPT12E T2CON: T2IRDIS (Bit 12)
#define GPT12E_T2CON_T2M_Msk (0x38UL) |
GPT12E T2CON: T2M (Bitfield-Mask: 0x07)
#define GPT12E_T2CON_T2M_Pos (3UL) |
GPT12E T2CON: T2M (Bit 3)
#define GPT12E_T2CON_T2R_Msk (0x40UL) |
GPT12E T2CON: T2R (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2R_Pos (6UL) |
GPT12E T2CON: T2R (Bit 6)
#define GPT12E_T2CON_T2RC_Msk (0x200UL) |
GPT12E T2CON: T2RC (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2RC_Pos (9UL) |
GPT12E T2CON: T2RC (Bit 9)
#define GPT12E_T2CON_T2RDIR_Msk (0x8000UL) |
GPT12E T2CON: T2RDIR (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2RDIR_Pos (15UL) |
GPT12E T2CON: T2RDIR (Bit 15)
#define GPT12E_T2CON_T2UD_Msk (0x80UL) |
GPT12E T2CON: T2UD (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2UD_Pos (7UL) |
GPT12E T2CON: T2UD (Bit 7)
#define GPT12E_T2CON_T2UDE_Msk (0x100UL) |
GPT12E T2CON: T2UDE (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2UDE_Pos (8UL) |
GPT12E T2CON: T2UDE (Bit 8)
#define GPT12E_T3_T3_Msk (0xffffUL) |
GPT12E T3: T3 (Bitfield-Mask: 0xffff)
#define GPT12E_T3_T3_Pos (0UL) |
GPT12E T3: T3 (Bit 0)
#define GPT12E_T3CON_BPS1_Msk (0x1800UL) |
GPT12E T3CON: BPS1 (Bitfield-Mask: 0x03)
#define GPT12E_T3CON_BPS1_Pos (11UL) |
GPT12E T3CON: BPS1 (Bit 11)
#define GPT12E_T3CON_T3CHDIR_Msk (0x4000UL) |
GPT12E T3CON: T3CHDIR (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3CHDIR_Pos (14UL) |
GPT12E T3CON: T3CHDIR (Bit 14)
#define GPT12E_T3CON_T3EDGE_Msk (0x2000UL) |
GPT12E T3CON: T3EDGE (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3EDGE_Pos (13UL) |
GPT12E T3CON: T3EDGE (Bit 13)
#define GPT12E_T3CON_T3I_Msk (0x7UL) |
GPT12E T3CON: T3I (Bitfield-Mask: 0x07)
#define GPT12E_T3CON_T3I_Pos (0UL) |
GPT12E T3CON: T3I (Bit 0)
#define GPT12E_T3CON_T3M_Msk (0x38UL) |
GPT12E T3CON: T3M (Bitfield-Mask: 0x07)
#define GPT12E_T3CON_T3M_Pos (3UL) |
GPT12E T3CON: T3M (Bit 3)
#define GPT12E_T3CON_T3OE_Msk (0x200UL) |
GPT12E T3CON: T3OE (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3OE_Pos (9UL) |
GPT12E T3CON: T3OE (Bit 9)
#define GPT12E_T3CON_T3OTL_Msk (0x400UL) |
GPT12E T3CON: T3OTL (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3OTL_Pos (10UL) |
GPT12E T3CON: T3OTL (Bit 10)
#define GPT12E_T3CON_T3R_Msk (0x40UL) |
GPT12E T3CON: T3R (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3R_Pos (6UL) |
GPT12E T3CON: T3R (Bit 6)
#define GPT12E_T3CON_T3RDIR_Msk (0x8000UL) |
GPT12E T3CON: T3RDIR (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3RDIR_Pos (15UL) |
GPT12E T3CON: T3RDIR (Bit 15)
#define GPT12E_T3CON_T3UD_Msk (0x80UL) |
GPT12E T3CON: T3UD (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3UD_Pos (7UL) |
GPT12E T3CON: T3UD (Bit 7)
#define GPT12E_T3CON_T3UDE_Msk (0x100UL) |
GPT12E T3CON: T3UDE (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3UDE_Pos (8UL) |
GPT12E T3CON: T3UDE (Bit 8)
#define GPT12E_T4_T4_Msk (0xffffUL) |
GPT12E T4: T4 (Bitfield-Mask: 0xffff)
#define GPT12E_T4_T4_Pos (0UL) |
GPT12E T4: T4 (Bit 0)
#define GPT12E_T4CON_CLRT2EN_Msk (0x400UL) |
GPT12E T4CON: CLRT2EN (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_CLRT2EN_Pos (10UL) |
GPT12E T4CON: CLRT2EN (Bit 10)
#define GPT12E_T4CON_CLRT3EN_Msk (0x800UL) |
GPT12E T4CON: CLRT3EN (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_CLRT3EN_Pos (11UL) |
GPT12E T4CON: CLRT3EN (Bit 11)
#define GPT12E_T4CON_T4CHDIR_Msk (0x4000UL) |
GPT12E T4CON: T4CHDIR (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4CHDIR_Pos (14UL) |
GPT12E T4CON: T4CHDIR (Bit 14)
#define GPT12E_T4CON_T4EDGE_Msk (0x2000UL) |
GPT12E T4CON: T4EDGE (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4EDGE_Pos (13UL) |
GPT12E T4CON: T4EDGE (Bit 13)
#define GPT12E_T4CON_T4I_Msk (0x7UL) |
GPT12E T4CON: T4I (Bitfield-Mask: 0x07)
#define GPT12E_T4CON_T4I_Pos (0UL) |
GPT12E T4CON: T4I (Bit 0)
#define GPT12E_T4CON_T4IRDIS_Msk (0x1000UL) |
GPT12E T4CON: T4IRDIS (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4IRDIS_Pos (12UL) |
GPT12E T4CON: T4IRDIS (Bit 12)
#define GPT12E_T4CON_T4M_Msk (0x38UL) |
GPT12E T4CON: T4M (Bitfield-Mask: 0x07)
#define GPT12E_T4CON_T4M_Pos (3UL) |
GPT12E T4CON: T4M (Bit 3)
#define GPT12E_T4CON_T4R_Msk (0x40UL) |
GPT12E T4CON: T4R (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4R_Pos (6UL) |
GPT12E T4CON: T4R (Bit 6)
#define GPT12E_T4CON_T4RC_Msk (0x200UL) |
GPT12E T4CON: T4RC (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4RC_Pos (9UL) |
GPT12E T4CON: T4RC (Bit 9)
#define GPT12E_T4CON_T4RDIR_Msk (0x8000UL) |
GPT12E T4CON: T4RDIR (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4RDIR_Pos (15UL) |
GPT12E T4CON: T4RDIR (Bit 15)
#define GPT12E_T4CON_T4UD_Msk (0x80UL) |
GPT12E T4CON: T4UD (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4UD_Pos (7UL) |
GPT12E T4CON: T4UD (Bit 7)
#define GPT12E_T4CON_T4UDE_Msk (0x100UL) |
GPT12E T4CON: T4UDE (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4UDE_Pos (8UL) |
GPT12E T4CON: T4UDE (Bit 8)
#define GPT12E_T5_T5_Msk (0xffffUL) |
GPT12E T5: T5 (Bitfield-Mask: 0xffff)
#define GPT12E_T5_T5_Pos (0UL) |
GPT12E T5: T5 (Bit 0)
#define GPT12E_T5CON_CI_Msk (0x3000UL) |
GPT12E T5CON: CI (Bitfield-Mask: 0x03)
#define GPT12E_T5CON_CI_Pos (12UL) |
GPT12E T5CON: CI (Bit 12)
#define GPT12E_T5CON_CT3_Msk (0x400UL) |
GPT12E T5CON: CT3 (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_CT3_Pos (10UL) |
GPT12E T5CON: CT3 (Bit 10)
#define GPT12E_T5CON_T5CLR_Msk (0x4000UL) |
GPT12E T5CON: T5CLR (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5CLR_Pos (14UL) |
GPT12E T5CON: T5CLR (Bit 14)
#define GPT12E_T5CON_T5I_Msk (0x7UL) |
GPT12E T5CON: T5I (Bitfield-Mask: 0x07)
#define GPT12E_T5CON_T5I_Pos (0UL) |
GPT12E T5CON: T5I (Bit 0)
#define GPT12E_T5CON_T5M_Msk (0x18UL) |
GPT12E T5CON: T5M (Bitfield-Mask: 0x03)
#define GPT12E_T5CON_T5M_Pos (3UL) |
GPT12E T5CON: T5M (Bit 3)
#define GPT12E_T5CON_T5R_Msk (0x40UL) |
GPT12E T5CON: T5R (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5R_Pos (6UL) |
GPT12E T5CON: T5R (Bit 6)
#define GPT12E_T5CON_T5RC_Msk (0x200UL) |
GPT12E T5CON: T5RC (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5RC_Pos (9UL) |
GPT12E T5CON: T5RC (Bit 9)
#define GPT12E_T5CON_T5SC_Msk (0x8000UL) |
GPT12E T5CON: T5SC (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5SC_Pos (15UL) |
GPT12E T5CON: T5SC (Bit 15)
#define GPT12E_T5CON_T5UD_Msk (0x80UL) |
GPT12E T5CON: T5UD (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5UD_Pos (7UL) |
GPT12E T5CON: T5UD (Bit 7)
#define GPT12E_T5CON_T5UDE_Msk (0x100UL) |
GPT12E T5CON: T5UDE (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5UDE_Pos (8UL) |
GPT12E T5CON: T5UDE (Bit 8)
#define GPT12E_T6_T6_Msk (0xffffUL) |
GPT12E T6: T6 (Bitfield-Mask: 0xffff)
#define GPT12E_T6_T6_Pos (0UL) |
GPT12E T6: T6 (Bit 0)
#define GPT12E_T6CON_BPS2_Msk (0x1800UL) |
GPT12E T6CON: BPS2 (Bitfield-Mask: 0x03)
#define GPT12E_T6CON_BPS2_Pos (11UL) |
GPT12E T6CON: BPS2 (Bit 11)
#define GPT12E_T6CON_T6CLR_Msk (0x4000UL) |
GPT12E T6CON: T6CLR (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6CLR_Pos (14UL) |
GPT12E T6CON: T6CLR (Bit 14)
#define GPT12E_T6CON_T6I_Msk (0x7UL) |
GPT12E T6CON: T6I (Bitfield-Mask: 0x07)
#define GPT12E_T6CON_T6I_Pos (0UL) |
GPT12E T6CON: T6I (Bit 0)
#define GPT12E_T6CON_T6M_Msk (0x38UL) |
GPT12E T6CON: T6M (Bitfield-Mask: 0x07)
#define GPT12E_T6CON_T6M_Pos (3UL) |
GPT12E T6CON: T6M (Bit 3)
#define GPT12E_T6CON_T6OE_Msk (0x200UL) |
GPT12E T6CON: T6OE (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6OE_Pos (9UL) |
GPT12E T6CON: T6OE (Bit 9)
#define GPT12E_T6CON_T6OTL_Msk (0x400UL) |
GPT12E T6CON: T6OTL (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6OTL_Pos (10UL) |
GPT12E T6CON: T6OTL (Bit 10)
#define GPT12E_T6CON_T6R_Msk (0x40UL) |
GPT12E T6CON: T6R (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6R_Pos (6UL) |
GPT12E T6CON: T6R (Bit 6)
#define GPT12E_T6CON_T6SR_Msk (0x8000UL) |
GPT12E T6CON: T6SR (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6SR_Pos (15UL) |
GPT12E T6CON: T6SR (Bit 15)
#define GPT12E_T6CON_T6UD_Msk (0x80UL) |
GPT12E T6CON: T6UD (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6UD_Pos (7UL) |
GPT12E T6CON: T6UD (Bit 7)
#define GPT12E_T6CON_T6UDE_Msk (0x100UL) |
GPT12E T6CON: T6UDE (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6UDE_Pos (8UL) |
GPT12E T6CON: T6UDE (Bit 8)
#define LIN_CTRL_STS_FB_SM1_Msk (0x2000UL) |
LIN CTRL_STS: FB_SM1 (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_FB_SM1_Pos (13UL) |
LIN CTRL_STS: FB_SM1 (Bit 13)
#define LIN_CTRL_STS_FB_SM2_Msk (0x4000UL) |
LIN CTRL_STS: FB_SM2 (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_FB_SM2_Pos (14UL) |
LIN CTRL_STS: FB_SM2 (Bit 14)
#define LIN_CTRL_STS_FB_SM3_Msk (0x8000UL) |
LIN CTRL_STS: FB_SM3 (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_FB_SM3_Pos (15UL) |
LIN CTRL_STS: FB_SM3 (Bit 15)
#define LIN_CTRL_STS_HV_MODE_Msk (0x200000UL) |
LIN CTRL_STS: HV_MODE (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_HV_MODE_Pos (21UL) |
LIN CTRL_STS: HV_MODE (Bit 21)
#define LIN_CTRL_STS_M_SM_ERR_CLR_Msk (0x1000000UL) |
LIN CTRL_STS: M_SM_ERR_CLR (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_M_SM_ERR_CLR_Pos (24UL) |
LIN CTRL_STS: M_SM_ERR_CLR (Bit 24)
#define LIN_CTRL_STS_M_SM_ERR_Msk (0x8UL) |
LIN CTRL_STS: M_SM_ERR (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_M_SM_ERR_Pos (3UL) |
LIN CTRL_STS: M_SM_ERR (Bit 3)
#define LIN_CTRL_STS_MODE_FB_Msk (0x70000UL) |
LIN CTRL_STS: MODE_FB (Bitfield-Mask: 0x07)
#define LIN_CTRL_STS_MODE_FB_Pos (16UL) |
LIN CTRL_STS: MODE_FB (Bit 16)
#define LIN_CTRL_STS_MODE_Msk (0x6UL) |
LIN CTRL_STS: MODE (Bitfield-Mask: 0x03)
#define LIN_CTRL_STS_MODE_Pos (1UL) |
LIN CTRL_STS: MODE (Bit 1)
#define LIN_CTRL_STS_OC_STS_Msk (0x20UL) |
LIN CTRL_STS: OC_STS (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_OC_STS_Pos (5UL) |
LIN CTRL_STS: OC_STS (Bit 5)
#define LIN_CTRL_STS_OT_STS_Msk (0x10UL) |
LIN CTRL_STS: OT_STS (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_OT_STS_Pos (4UL) |
LIN CTRL_STS: OT_STS (Bit 4)
#define LIN_CTRL_STS_RXD_Msk (0x400UL) |
LIN CTRL_STS: RXD (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_RXD_Pos (10UL) |
LIN CTRL_STS: RXD (Bit 10)
#define LIN_CTRL_STS_SM_Msk (0x1800UL) |
LIN CTRL_STS: SM (Bitfield-Mask: 0x03)
#define LIN_CTRL_STS_SM_Pos (11UL) |
LIN CTRL_STS: SM (Bit 11)
#define LIN_CTRL_STS_TXD_Msk (0x200UL) |
LIN CTRL_STS: TXD (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_TXD_Pos (9UL) |
LIN CTRL_STS: TXD (Bit 9)
#define LIN_CTRL_STS_TXD_TMOUT_STS_Msk (0x40UL) |
LIN CTRL_STS: TXD_TMOUT_STS (Bitfield-Mask: 0x01)
#define LIN_CTRL_STS_TXD_TMOUT_STS_Pos (6UL) |
LIN CTRL_STS: TXD_TMOUT_STS (Bit 6)
#define MF_CSA_CTRL_EN_Msk (0x1UL) |
MF CSA_CTRL: EN (Bitfield-Mask: 0x01)
#define MF_CSA_CTRL_EN_Pos (0UL) |
MF CSA_CTRL: EN (Bit 0)
#define MF_CSA_CTRL_GAIN_Msk (0x6UL) |
MF CSA_CTRL: GAIN (Bitfield-Mask: 0x03)
#define MF_CSA_CTRL_GAIN_Pos (1UL) |
MF CSA_CTRL: GAIN (Bit 1)
#define MF_CSA_CTRL_VZERO_Msk (0x100UL) |
MF CSA_CTRL: VZERO (Bitfield-Mask: 0x01)
#define MF_CSA_CTRL_VZERO_Pos (8UL) |
MF CSA_CTRL: VZERO (Bit 8)
#define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Msk (0x400UL) |
MF P2_ADCSEL_CTRL: ADC1_CH1_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Pos (10UL) |
MF P2_ADCSEL_CTRL: ADC1_CH1_SEL (Bit 10)
#define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Msk (0x200UL) |
MF P2_ADCSEL_CTRL: ADC3_INN_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Pos (9UL) |
MF P2_ADCSEL_CTRL: ADC3_INN_SEL (Bit 9)
#define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Msk (0x100UL) |
MF P2_ADCSEL_CTRL: ADC3_INP_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Pos (8UL) |
MF P2_ADCSEL_CTRL: ADC3_INP_SEL (Bit 8)
#define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Msk (0x1UL) |
MF P2_ADCSEL_CTRL: P2_0_ADC_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Pos (0UL) |
MF P2_ADCSEL_CTRL: P2_0_ADC_SEL (Bit 0)
#define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Msk (0x2UL) |
MF P2_ADCSEL_CTRL: P2_2_ADC_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Pos (1UL) |
MF P2_ADCSEL_CTRL: P2_2_ADC_SEL (Bit 1)
#define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Msk (0x4UL) |
MF P2_ADCSEL_CTRL: P2_3_ADC_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Pos (2UL) |
MF P2_ADCSEL_CTRL: P2_3_ADC_SEL (Bit 2)
#define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Msk (0x8UL) |
MF P2_ADCSEL_CTRL: P2_4_ADC_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Pos (3UL) |
MF P2_ADCSEL_CTRL: P2_4_ADC_SEL (Bit 3)
#define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Msk (0x10UL) |
MF P2_ADCSEL_CTRL: P2_5_ADC_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Pos (4UL) |
MF P2_ADCSEL_CTRL: P2_5_ADC_SEL (Bit 4)
#define MF_P2_ADCSEL_CTRL_P2_7_ADC_SEL_Msk (0x20UL) |
MF P2_ADCSEL_CTRL: P2_7_ADC_SEL (Bitfield-Mask: 0x01)
#define MF_P2_ADCSEL_CTRL_P2_7_ADC_SEL_Pos (5UL) |
MF P2_ADCSEL_CTRL: P2_7_ADC_SEL (Bit 5)
#define MF_REF1_STS_REFBG_LOTHWARN_STS_Msk (0x10UL) |
MF REF1_STS: REFBG_LOTHWARN_STS (Bitfield-Mask: 0x01)
#define MF_REF1_STS_REFBG_LOTHWARN_STS_Pos (4UL) |
MF REF1_STS: REFBG_LOTHWARN_STS (Bit 4)
#define MF_REF1_STS_REFBG_UPTHWARN_STS_Msk (0x20UL) |
MF REF1_STS: REFBG_UPTHWARN_STS (Bitfield-Mask: 0x01)
#define MF_REF1_STS_REFBG_UPTHWARN_STS_Pos (5UL) |
MF REF1_STS: REFBG_UPTHWARN_STS (Bit 5)
#define MF_REF2_CTRL_VREF5V_OV_STS_Msk (0x8UL) |
MF REF2_CTRL: VREF5V_OV_STS (Bitfield-Mask: 0x01)
#define MF_REF2_CTRL_VREF5V_OV_STS_Pos (3UL) |
MF REF2_CTRL: VREF5V_OV_STS (Bit 3)
#define MF_REF2_CTRL_VREF5V_OVL_STS_Msk (0x2UL) |
MF REF2_CTRL: VREF5V_OVL_STS (Bitfield-Mask: 0x01)
#define MF_REF2_CTRL_VREF5V_OVL_STS_Pos (1UL) |
MF REF2_CTRL: VREF5V_OVL_STS (Bit 1)
#define MF_REF2_CTRL_VREF5V_PD_N_Msk (0x1UL) |
MF REF2_CTRL: VREF5V_PD_N (Bitfield-Mask: 0x01)
#define MF_REF2_CTRL_VREF5V_PD_N_Pos (0UL) |
MF REF2_CTRL: VREF5V_PD_N (Bit 0)
#define MF_REF2_CTRL_VREF5V_UV_STS_Msk (0x4UL) |
MF REF2_CTRL: VREF5V_UV_STS (Bitfield-Mask: 0x01)
#define MF_REF2_CTRL_VREF5V_UV_STS_Pos (2UL) |
MF REF2_CTRL: VREF5V_UV_STS (Bit 2)
#define MF_TEMPSENSE_CTRL_PMU_OT_STS_Msk (0x20UL) |
MF TEMPSENSE_CTRL: PMU_OT_STS (Bitfield-Mask: 0x01)
#define MF_TEMPSENSE_CTRL_PMU_OT_STS_Pos (5UL) |
MF TEMPSENSE_CTRL: PMU_OT_STS (Bit 5)
#define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Msk (0x10UL) |
MF TEMPSENSE_CTRL: PMU_OTWARN_STS (Bitfield-Mask: 0x01)
#define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Pos (4UL) |
MF TEMPSENSE_CTRL: PMU_OTWARN_STS (Bit 4)
#define MF_TEMPSENSE_CTRL_SYS_OT_STS_Msk (0x80UL) |
MF TEMPSENSE_CTRL: SYS_OT_STS (Bitfield-Mask: 0x01)
#define MF_TEMPSENSE_CTRL_SYS_OT_STS_Pos (7UL) |
MF TEMPSENSE_CTRL: SYS_OT_STS (Bit 7)
#define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Msk (0x40UL) |
MF TEMPSENSE_CTRL: SYS_OTWARN_STS (Bitfield-Mask: 0x01)
#define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Pos (6UL) |
MF TEMPSENSE_CTRL: SYS_OTWARN_STS (Bit 6)
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk (0x10UL) |
MF VMON_SEN_CTRL: VMON_SEN_HRESO_5V (Bitfield-Mask: 0x01)
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos (4UL) |
MF VMON_SEN_CTRL: VMON_SEN_HRESO_5V (Bit 4)
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk (0x1UL) |
MF VMON_SEN_CTRL: VMON_SEN_PD_N (Bitfield-Mask: 0x01)
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos (0UL) |
MF VMON_SEN_CTRL: VMON_SEN_PD_N (Bit 0)
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk (0x20UL) |
MF VMON_SEN_CTRL: VMON_SEN_SEL_INRANGE (Bitfield-Mask: 0x01)
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos (5UL) |
MF VMON_SEN_CTRL: VMON_SEN_SEL_INRANGE (Bit 5)
#define PMU_CNF_CYC_SAMPLE_DEL_M03_Msk (0xfUL) |
PMU CNF_CYC_SAMPLE_DEL: M03 (Bitfield-Mask: 0x0f)
#define PMU_CNF_CYC_SAMPLE_DEL_M03_Pos (0UL) |
PMU CNF_CYC_SAMPLE_DEL: M03 (Bit 0)
#define PMU_CNF_CYC_SENSE_E01_Msk (0x30UL) |
PMU CNF_CYC_SENSE: E01 (Bitfield-Mask: 0x03)
#define PMU_CNF_CYC_SENSE_E01_Pos (4UL) |
PMU CNF_CYC_SENSE: E01 (Bit 4)
#define PMU_CNF_CYC_SENSE_M03_Msk (0xfUL) |
PMU CNF_CYC_SENSE: M03 (Bitfield-Mask: 0x0f)
#define PMU_CNF_CYC_SENSE_M03_Pos (0UL) |
PMU CNF_CYC_SENSE: M03 (Bit 0)
#define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Msk (0x80UL) |
PMU CNF_CYC_SENSE: OSC_100kHz_EN (Bitfield-Mask: 0x01)
#define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Pos (7UL) |
PMU CNF_CYC_SENSE: OSC_100kHz_EN (Bit 7)
#define PMU_CNF_CYC_WAKE_E01_Msk (0x30UL) |
PMU CNF_CYC_WAKE: E01 (Bitfield-Mask: 0x03)
#define PMU_CNF_CYC_WAKE_E01_Pos (4UL) |
PMU CNF_CYC_WAKE: E01 (Bit 4)
#define PMU_CNF_CYC_WAKE_M03_Msk (0xfUL) |
PMU CNF_CYC_WAKE: M03 (Bitfield-Mask: 0x0f)
#define PMU_CNF_CYC_WAKE_M03_Pos (0UL) |
PMU CNF_CYC_WAKE: M03 (Bit 0)
#define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Msk (0x8UL) |
PMU CNF_PMU_SETTINGS: CYC_SENSE_EN (Bitfield-Mask: 0x01)
#define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Pos (3UL) |
PMU CNF_PMU_SETTINGS: CYC_SENSE_EN (Bit 3)
#define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Msk (0x4UL) |
PMU CNF_PMU_SETTINGS: CYC_WAKE_EN (Bitfield-Mask: 0x01)
#define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Pos (2UL) |
PMU CNF_PMU_SETTINGS: CYC_WAKE_EN (Bit 2)
#define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Msk (0x2UL) |
PMU CNF_PMU_SETTINGS: EN_0V9_N (Bitfield-Mask: 0x01)
#define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Pos (1UL) |
PMU CNF_PMU_SETTINGS: EN_0V9_N (Bit 1)
#define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Msk (0x80UL) |
PMU CNF_PMU_SETTINGS: EN_VDDEXT_OC_OFF_N (Bitfield-Mask: 0x01)
#define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Pos (7UL) |
PMU CNF_PMU_SETTINGS: EN_VDDEXT_OC_OFF_N (Bit 7)
#define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Msk (0x1UL) |
PMU CNF_PMU_SETTINGS: WAKE_W_RST (Bitfield-Mask: 0x01)
#define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Pos (0UL) |
PMU CNF_PMU_SETTINGS: WAKE_W_RST (Bit 0)
#define PMU_CNF_RST_TFB_RST_TFB_Msk (0x3UL) |
PMU CNF_RST_TFB: RST_TFB (Bitfield-Mask: 0x03)
#define PMU_CNF_RST_TFB_RST_TFB_Pos (0UL) |
PMU CNF_RST_TFB: RST_TFB (Bit 0)
#define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Msk (0xcUL) |
PMU CNF_WAKE_FILTER: CNF_GPIO_FT (Bitfield-Mask: 0x03)
#define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Pos (2UL) |
PMU CNF_WAKE_FILTER: CNF_GPIO_FT (Bit 2)
#define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Msk (0x1UL) |
PMU CNF_WAKE_FILTER: CNF_LIN_FT (Bitfield-Mask: 0x01)
#define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Pos (0UL) |
PMU CNF_WAKE_FILTER: CNF_LIN_FT (Bit 0)
#define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Msk (0x2UL) |
PMU CNF_WAKE_FILTER: CNF_MON_FT (Bitfield-Mask: 0x01)
#define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Pos (1UL) |
PMU CNF_WAKE_FILTER: CNF_MON_FT (Bit 1)
#define PMU_GPUDATA00_DATA0_Msk (0xffUL) |
PMU GPUDATA00: DATA0 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA00_DATA0_Pos (0UL) |
PMU GPUDATA00: DATA0 (Bit 0)
#define PMU_GPUDATA01_DATA1_Msk (0xffUL) |
PMU GPUDATA01: DATA1 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA01_DATA1_Pos (0UL) |
PMU GPUDATA01: DATA1 (Bit 0)
#define PMU_GPUDATA02_DATA2_Msk (0xffUL) |
PMU GPUDATA02: DATA2 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA02_DATA2_Pos (0UL) |
PMU GPUDATA02: DATA2 (Bit 0)
#define PMU_GPUDATA03_DATA3_Msk (0xffUL) |
PMU GPUDATA03: DATA3 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA03_DATA3_Pos (0UL) |
PMU GPUDATA03: DATA3 (Bit 0)
#define PMU_GPUDATA04_DATA4_Msk (0xffUL) |
PMU GPUDATA04: DATA4 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA04_DATA4_Pos (0UL) |
PMU GPUDATA04: DATA4 (Bit 0)
#define PMU_GPUDATA05_DATA5_Msk (0xffUL) |
PMU GPUDATA05: DATA5 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA05_DATA5_Pos (0UL) |
PMU GPUDATA05: DATA5 (Bit 0)
#define PMU_LIN_WAKE_EN_LIN_EN_Msk (0x80UL) |
PMU LIN_WAKE_EN: LIN_EN (Bitfield-Mask: 0x01)
#define PMU_LIN_WAKE_EN_LIN_EN_Pos (7UL) |
PMU LIN_WAKE_EN: LIN_EN (Bit 7)
#define PMU_MON_CNF_CYC_Msk (0x8UL) |
PMU MON_CNF: CYC (Bitfield-Mask: 0x01)
#define PMU_MON_CNF_CYC_Pos (3UL) |
PMU MON_CNF: CYC (Bit 3)
#define PMU_MON_CNF_EN_Msk (0x1UL) |
PMU MON_CNF: EN (Bitfield-Mask: 0x01)
#define PMU_MON_CNF_EN_Pos (0UL) |
PMU MON_CNF: EN (Bit 0)
#define PMU_MON_CNF_FALL_Msk (0x2UL) |
PMU MON_CNF: FALL (Bitfield-Mask: 0x01)
#define PMU_MON_CNF_FALL_Pos (1UL) |
PMU MON_CNF: FALL (Bit 1)
#define PMU_MON_CNF_PD_Msk (0x10UL) |
PMU MON_CNF: PD (Bitfield-Mask: 0x01)
#define PMU_MON_CNF_PD_Pos (4UL) |
PMU MON_CNF: PD (Bit 4)
#define PMU_MON_CNF_PU_Msk (0x20UL) |
PMU MON_CNF: PU (Bitfield-Mask: 0x01)
#define PMU_MON_CNF_PU_Pos (5UL) |
PMU MON_CNF: PU (Bit 5)
#define PMU_MON_CNF_RISE_Msk (0x4UL) |
PMU MON_CNF: RISE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF_RISE_Pos (2UL) |
PMU MON_CNF: RISE (Bit 2)
#define PMU_MON_CNF_STS_Msk (0x80UL) |
PMU MON_CNF: STS (Bitfield-Mask: 0x01)
#define PMU_MON_CNF_STS_Pos (7UL) |
PMU MON_CNF: STS (Bit 7)
#define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Msk (0x80UL) |
PMU PMU_RESET_STS1: PMU_1V5DidPOR (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Pos (7UL) |
PMU PMU_RESET_STS1: PMU_1V5DidPOR (Bit 7)
#define PMU_PMU_RESET_STS1_PMU_ClkWDT_Msk (0x10UL) |
PMU PMU_RESET_STS1: PMU_ClkWDT (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_PMU_ClkWDT_Pos (4UL) |
PMU PMU_RESET_STS1: PMU_ClkWDT (Bit 4)
#define PMU_PMU_RESET_STS1_PMU_ExtWDT_Msk (0x20UL) |
PMU PMU_RESET_STS1: PMU_ExtWDT (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_PMU_ExtWDT_Pos (5UL) |
PMU PMU_RESET_STS1: PMU_ExtWDT (Bit 5)
#define PMU_PMU_RESET_STS1_PMU_LPR_Msk (0x8UL) |
PMU PMU_RESET_STS1: PMU_LPR (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_PMU_LPR_Pos (3UL) |
PMU PMU_RESET_STS1: PMU_LPR (Bit 3)
#define PMU_PMU_RESET_STS1_PMU_PIN_Msk (0x40UL) |
PMU PMU_RESET_STS1: PMU_PIN (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_PMU_PIN_Pos (6UL) |
PMU PMU_RESET_STS1: PMU_PIN (Bit 6)
#define PMU_PMU_RESET_STS1_PMU_SleepEX_Msk (0x4UL) |
PMU PMU_RESET_STS1: PMU_SleepEX (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_PMU_SleepEX_Pos (2UL) |
PMU PMU_RESET_STS1: PMU_SleepEX (Bit 2)
#define PMU_PMU_RESET_STS1_PMU_WAKE_Msk (0x2UL) |
PMU PMU_RESET_STS1: PMU_WAKE (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_PMU_WAKE_Pos (1UL) |
PMU PMU_RESET_STS1: PMU_WAKE (Bit 1)
#define PMU_PMU_RESET_STS1_SYS_FAIL_Msk (0x1UL) |
PMU PMU_RESET_STS1: SYS_FAIL (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS1_SYS_FAIL_Pos (0UL) |
PMU PMU_RESET_STS1: SYS_FAIL (Bit 0)
#define PMU_PMU_RESET_STS2_LOCKUP_Msk (0x4UL) |
PMU PMU_RESET_STS2: LOCKUP (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS2_LOCKUP_Pos (2UL) |
PMU PMU_RESET_STS2: LOCKUP (Bit 2)
#define PMU_PMU_RESET_STS2_PMU_IntWDT_Msk (0x1UL) |
PMU PMU_RESET_STS2: PMU_IntWDT (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS2_PMU_IntWDT_Pos (0UL) |
PMU PMU_RESET_STS2: PMU_IntWDT (Bit 0)
#define PMU_PMU_RESET_STS2_PMU_SOFT_Msk (0x2UL) |
PMU PMU_RESET_STS2: PMU_SOFT (Bitfield-Mask: 0x01)
#define PMU_PMU_RESET_STS2_PMU_SOFT_Pos (1UL) |
PMU PMU_RESET_STS2: PMU_SOFT (Bit 1)
#define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk (0x4UL) |
PMU PMU_SUPPLY_STS: PMU_1V5_FAIL_EN (Bitfield-Mask: 0x01)
#define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos (2UL) |
PMU PMU_SUPPLY_STS: PMU_1V5_FAIL_EN (Bit 2)
#define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Msk (0x2UL) |
PMU PMU_SUPPLY_STS: PMU_1V5_OVERLOAD (Bitfield-Mask: 0x01)
#define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Pos (1UL) |
PMU PMU_SUPPLY_STS: PMU_1V5_OVERLOAD (Bit 1)
#define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Msk (0x1UL) |
PMU PMU_SUPPLY_STS: PMU_1V5_OVERVOLT (Bitfield-Mask: 0x01)
#define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Pos (0UL) |
PMU PMU_SUPPLY_STS: PMU_1V5_OVERVOLT (Bit 0)
#define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk (0x40UL) |
PMU PMU_SUPPLY_STS: PMU_5V_FAIL_EN (Bitfield-Mask: 0x01)
#define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos (6UL) |
PMU PMU_SUPPLY_STS: PMU_5V_FAIL_EN (Bit 6)
#define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Msk (0x20UL) |
PMU PMU_SUPPLY_STS: PMU_5V_OVERLOAD (Bitfield-Mask: 0x01)
#define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Pos (5UL) |
PMU PMU_SUPPLY_STS: PMU_5V_OVERLOAD (Bit 5)
#define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Msk (0x10UL) |
PMU PMU_SUPPLY_STS: PMU_5V_OVERVOLT (Bitfield-Mask: 0x01)
#define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Pos (4UL) |
PMU PMU_SUPPLY_STS: PMU_5V_OVERVOLT (Bit 4)
#define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Msk (0x4UL) |
PMU SYS_FAIL_STS: PMU_1V5_OVL (Bitfield-Mask: 0x01)
#define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Pos (2UL) |
PMU SYS_FAIL_STS: PMU_1V5_OVL (Bit 2)
#define PMU_SYS_FAIL_STS_PMU_5V_OVL_Msk (0x8UL) |
PMU SYS_FAIL_STS: PMU_5V_OVL (Bitfield-Mask: 0x01)
#define PMU_SYS_FAIL_STS_PMU_5V_OVL_Pos (3UL) |
PMU SYS_FAIL_STS: PMU_5V_OVL (Bit 3)
#define PMU_SYS_FAIL_STS_SUPP_SHORT_Msk (0x1UL) |
PMU SYS_FAIL_STS: SUPP_SHORT (Bitfield-Mask: 0x01)
#define PMU_SYS_FAIL_STS_SUPP_SHORT_Pos (0UL) |
PMU SYS_FAIL_STS: SUPP_SHORT (Bit 0)
#define PMU_SYS_FAIL_STS_SUPP_TMOUT_Msk (0x2UL) |
PMU SYS_FAIL_STS: SUPP_TMOUT (Bitfield-Mask: 0x01)
#define PMU_SYS_FAIL_STS_SUPP_TMOUT_Pos (1UL) |
PMU SYS_FAIL_STS: SUPP_TMOUT (Bit 1)
#define PMU_SYS_FAIL_STS_SYS_OT_Msk (0x20UL) |
PMU SYS_FAIL_STS: SYS_OT (Bitfield-Mask: 0x01)
#define PMU_SYS_FAIL_STS_SYS_OT_Pos (5UL) |
PMU SYS_FAIL_STS: SYS_OT (Bit 5)
#define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Msk (0x40UL) |
PMU SYS_FAIL_STS: WDT1_SEQ_FAIL (Bitfield-Mask: 0x01)
#define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Pos (6UL) |
PMU SYS_FAIL_STS: WDT1_SEQ_FAIL (Bit 6)
#define PMU_SystemStartConfig_MBIST_EN_Msk (0x1UL) |
PMU SystemStartConfig: MBIST_EN (Bitfield-Mask: 0x01)
#define PMU_SystemStartConfig_MBIST_EN_Pos (0UL) |
PMU SystemStartConfig: MBIST_EN (Bit 0)
#define PMU_VDDEXT_CTRL_CYC_EN_Msk (0x2UL) |
PMU VDDEXT_CTRL: CYC_EN (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_CYC_EN_Pos (1UL) |
PMU VDDEXT_CTRL: CYC_EN (Bit 1)
#define PMU_VDDEXT_CTRL_ENABLE_Msk (0x1UL) |
PMU VDDEXT_CTRL: ENABLE (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_ENABLE_Pos (0UL) |
PMU VDDEXT_CTRL: ENABLE (Bit 0)
#define PMU_VDDEXT_CTRL_FAIL_EN_Msk (0x4UL) |
PMU VDDEXT_CTRL: FAIL_EN (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_FAIL_EN_Pos (2UL) |
PMU VDDEXT_CTRL: FAIL_EN (Bit 2)
#define PMU_VDDEXT_CTRL_OK_Msk (0x40UL) |
PMU VDDEXT_CTRL: OK (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_OK_Pos (6UL) |
PMU VDDEXT_CTRL: OK (Bit 6)
#define PMU_VDDEXT_CTRL_OVERLOAD_Msk (0x20UL) |
PMU VDDEXT_CTRL: OVERLOAD (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_OVERLOAD_Pos (5UL) |
PMU VDDEXT_CTRL: OVERLOAD (Bit 5)
#define PMU_VDDEXT_CTRL_OVERVOLT_Msk (0x10UL) |
PMU VDDEXT_CTRL: OVERVOLT (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_OVERVOLT_Pos (4UL) |
PMU VDDEXT_CTRL: OVERVOLT (Bit 4)
#define PMU_VDDEXT_CTRL_SHORT_Msk (0x8UL) |
PMU VDDEXT_CTRL: SHORT (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_SHORT_Pos (3UL) |
PMU VDDEXT_CTRL: SHORT (Bit 3)
#define PMU_VDDEXT_CTRL_STABLE_Msk (0x80UL) |
PMU VDDEXT_CTRL: STABLE (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_STABLE_Pos (7UL) |
PMU VDDEXT_CTRL: STABLE (Bit 7)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Msk (0x1UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Pos (0UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_0 (Bit 0)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Msk (0x2UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Pos (1UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_1 (Bit 1)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Msk (0x4UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Pos (2UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_2 (Bit 2)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Msk (0x8UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Pos (3UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_3 (Bit 3)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Msk (0x10UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Pos (4UL) |
PMU WAKE_CONF_GPIO0_CYC: GPIO0_CYC_4 (Bit 4)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Msk (0x1UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Pos (0UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_0 (Bit 0)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Msk (0x2UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Pos (1UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_1 (Bit 1)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Msk (0x4UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Pos (2UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_2 (Bit 2)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Msk (0x8UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Pos (3UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_3 (Bit 3)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Msk (0x10UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Pos (4UL) |
PMU WAKE_CONF_GPIO0_FALL: GPIO0_FA_4 (Bit 4)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Msk (0x1UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Pos (0UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_0 (Bit 0)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Msk (0x2UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Pos (1UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_1 (Bit 1)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Msk (0x4UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Pos (2UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_2 (Bit 2)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Msk (0x8UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Pos (3UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_3 (Bit 3)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Msk (0x10UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Pos (4UL) |
PMU WAKE_CONF_GPIO0_RISE: GPIO0_RI_4 (Bit 4)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Msk (0x1UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Pos (0UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_0 (Bit 0)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Msk (0x2UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Pos (1UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_1 (Bit 1)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Msk (0x4UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Pos (2UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_2 (Bit 2)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Msk (0x8UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Pos (3UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_3 (Bit 3)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Msk (0x10UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Pos (4UL) |
PMU WAKE_CONF_GPIO1_CYC: GPIO1_CYC_4 (Bit 4)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Msk (0x1UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Pos (0UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_0 (Bit 0)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Msk (0x2UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Pos (1UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_1 (Bit 1)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Msk (0x4UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Pos (2UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_2 (Bit 2)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Msk (0x8UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Pos (3UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_3 (Bit 3)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Msk (0x10UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Pos (4UL) |
PMU WAKE_CONF_GPIO1_FALL: GPIO1_FA_4 (Bit 4)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Msk (0x1UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Pos (0UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_0 (Bit 0)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Msk (0x2UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Pos (1UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_1 (Bit 1)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Msk (0x4UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Pos (2UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_2 (Bit 2)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Msk (0x8UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Pos (3UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_3 (Bit 3)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Msk (0x10UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Pos (4UL) |
PMU WAKE_CONF_GPIO1_RISE: GPIO1_RI_4 (Bit 4)
#define PMU_WAKE_STATUS_CYC_WAKE_Msk (0x10UL) |
PMU WAKE_STATUS: CYC_WAKE (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_CYC_WAKE_Pos (4UL) |
PMU WAKE_STATUS: CYC_WAKE (Bit 4)
#define PMU_WAKE_STATUS_FAIL_Msk (0x20UL) |
PMU WAKE_STATUS: FAIL (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_FAIL_Pos (5UL) |
PMU WAKE_STATUS: FAIL (Bit 5)
#define PMU_WAKE_STATUS_GPIO0_Msk (0x4UL) |
PMU WAKE_STATUS: GPIO0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_GPIO0_Pos (2UL) |
PMU WAKE_STATUS: GPIO0 (Bit 2)
#define PMU_WAKE_STATUS_GPIO1_Msk (0x8UL) |
PMU WAKE_STATUS: GPIO1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_GPIO1_Pos (3UL) |
PMU WAKE_STATUS: GPIO1 (Bit 3)
#define PMU_WAKE_STATUS_LIN_WAKE_Msk (0x1UL) |
PMU WAKE_STATUS: LIN_WAKE (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_LIN_WAKE_Pos (0UL) |
PMU WAKE_STATUS: LIN_WAKE (Bit 0)
#define PMU_WAKE_STATUS_MON_WAKE_Msk (0x2UL) |
PMU WAKE_STATUS: MON_WAKE (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_MON_WAKE_Pos (1UL) |
PMU WAKE_STATUS: MON_WAKE (Bit 1)
#define PMU_WAKE_STS_FAIL_SUPPFAIL_Msk (0x1UL) |
PMU WAKE_STS_FAIL: SUPPFAIL (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_FAIL_SUPPFAIL_Pos (0UL) |
PMU WAKE_STS_FAIL: SUPPFAIL (Bit 0)
#define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Msk (0x4UL) |
PMU WAKE_STS_FAIL: VDDEXTSHORT (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Pos (2UL) |
PMU WAKE_STS_FAIL: VDDEXTSHORT (Bit 2)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Msk (0x1UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Pos (0UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_0 (Bit 0)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Msk (0x2UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Pos (1UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_1 (Bit 1)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Msk (0x4UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Pos (2UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_2 (Bit 2)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Msk (0x8UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Pos (3UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_3 (Bit 3)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Msk (0x10UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Pos (4UL) |
PMU WAKE_STS_GPIO0: GPIO0_STS_4 (Bit 4)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Msk (0x1UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Pos (0UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_0 (Bit 0)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Msk (0x2UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Pos (1UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_1 (Bit 1)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Msk (0x4UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Pos (2UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_2 (Bit 2)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Msk (0x8UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Pos (3UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_3 (Bit 3)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Msk (0x10UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Pos (4UL) |
PMU WAKE_STS_GPIO1: GPIO1_STS_4 (Bit 4)
#define PMU_WAKE_STS_MON_WAKE_STS_Msk (0x1UL) |
PMU WAKE_STS_MON: WAKE_STS (Bitfield-Mask: 0x01)
#define PMU_WAKE_STS_MON_WAKE_STS_Pos (0UL) |
PMU WAKE_STS_MON: WAKE_STS (Bit 0)
#define PORT_P0_ALTSEL0_P0_Msk (0x1UL) |
PORT P0_ALTSEL0: P0 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_P0_Pos (0UL) |
PORT P0_ALTSEL0: P0 (Bit 0)
#define PORT_P0_ALTSEL0_P1_Msk (0x2UL) |
PORT P0_ALTSEL0: P1 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_P1_Pos (1UL) |
PORT P0_ALTSEL0: P1 (Bit 1)
#define PORT_P0_ALTSEL0_P2_Msk (0x4UL) |
PORT P0_ALTSEL0: P2 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_P2_Pos (2UL) |
PORT P0_ALTSEL0: P2 (Bit 2)
#define PORT_P0_ALTSEL0_P3_Msk (0x8UL) |
PORT P0_ALTSEL0: P3 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_P3_Pos (3UL) |
PORT P0_ALTSEL0: P3 (Bit 3)
#define PORT_P0_ALTSEL0_P4_Msk (0x10UL) |
PORT P0_ALTSEL0: P4 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_P4_Pos (4UL) |
PORT P0_ALTSEL0: P4 (Bit 4)
#define PORT_P0_ALTSEL1_P0_Msk (0x1UL) |
PORT P0_ALTSEL1: P0 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_P0_Pos (0UL) |
PORT P0_ALTSEL1: P0 (Bit 0)
#define PORT_P0_ALTSEL1_P1_Msk (0x2UL) |
PORT P0_ALTSEL1: P1 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_P1_Pos (1UL) |
PORT P0_ALTSEL1: P1 (Bit 1)
#define PORT_P0_ALTSEL1_P2_Msk (0x4UL) |
PORT P0_ALTSEL1: P2 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_P2_Pos (2UL) |
PORT P0_ALTSEL1: P2 (Bit 2)
#define PORT_P0_ALTSEL1_P3_Msk (0x8UL) |
PORT P0_ALTSEL1: P3 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_P3_Pos (3UL) |
PORT P0_ALTSEL1: P3 (Bit 3)
#define PORT_P0_ALTSEL1_P4_Msk (0x10UL) |
PORT P0_ALTSEL1: P4 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_P4_Pos (4UL) |
PORT P0_ALTSEL1: P4 (Bit 4)
#define PORT_P0_DATA_P0_Msk (0x1UL) |
PORT P0_DATA: P0 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_P0_Pos (0UL) |
PORT P0_DATA: P0 (Bit 0)
#define PORT_P0_DATA_P1_Msk (0x2UL) |
PORT P0_DATA: P1 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_P1_Pos (1UL) |
PORT P0_DATA: P1 (Bit 1)
#define PORT_P0_DATA_P2_Msk (0x4UL) |
PORT P0_DATA: P2 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_P2_Pos (2UL) |
PORT P0_DATA: P2 (Bit 2)
#define PORT_P0_DATA_P3_Msk (0x8UL) |
PORT P0_DATA: P3 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_P3_Pos (3UL) |
PORT P0_DATA: P3 (Bit 3)
#define PORT_P0_DATA_P4_Msk (0x10UL) |
PORT P0_DATA: P4 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_P4_Pos (4UL) |
PORT P0_DATA: P4 (Bit 4)
#define PORT_P0_DIR_P0_Msk (0x1UL) |
PORT P0_DIR: P0 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_P0_Pos (0UL) |
PORT P0_DIR: P0 (Bit 0)
#define PORT_P0_DIR_P1_Msk (0x2UL) |
PORT P0_DIR: P1 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_P1_Pos (1UL) |
PORT P0_DIR: P1 (Bit 1)
#define PORT_P0_DIR_P2_Msk (0x4UL) |
PORT P0_DIR: P2 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_P2_Pos (2UL) |
PORT P0_DIR: P2 (Bit 2)
#define PORT_P0_DIR_P3_Msk (0x8UL) |
PORT P0_DIR: P3 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_P3_Pos (3UL) |
PORT P0_DIR: P3 (Bit 3)
#define PORT_P0_DIR_P4_Msk (0x10UL) |
PORT P0_DIR: P4 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_P4_Pos (4UL) |
PORT P0_DIR: P4 (Bit 4)
#define PORT_P0_OD_P0_Msk (0x1UL) |
PORT P0_OD: P0 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_P0_Pos (0UL) |
PORT P0_OD: P0 (Bit 0)
#define PORT_P0_OD_P1_Msk (0x2UL) |
PORT P0_OD: P1 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_P1_Pos (1UL) |
PORT P0_OD: P1 (Bit 1)
#define PORT_P0_OD_P2_Msk (0x4UL) |
PORT P0_OD: P2 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_P2_Pos (2UL) |
PORT P0_OD: P2 (Bit 2)
#define PORT_P0_OD_P3_Msk (0x8UL) |
PORT P0_OD: P3 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_P3_Pos (3UL) |
PORT P0_OD: P3 (Bit 3)
#define PORT_P0_OD_P4_Msk (0x10UL) |
PORT P0_OD: P4 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_P4_Pos (4UL) |
PORT P0_OD: P4 (Bit 4)
#define PORT_P0_PUDEN_P0_Msk (0x1UL) |
PORT P0_PUDEN: P0 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_P0_Pos (0UL) |
PORT P0_PUDEN: P0 (Bit 0)
#define PORT_P0_PUDEN_P1_Msk (0x2UL) |
PORT P0_PUDEN: P1 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_P1_Pos (1UL) |
PORT P0_PUDEN: P1 (Bit 1)
#define PORT_P0_PUDEN_P2_Msk (0x4UL) |
PORT P0_PUDEN: P2 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_P2_Pos (2UL) |
PORT P0_PUDEN: P2 (Bit 2)
#define PORT_P0_PUDEN_P3_Msk (0x8UL) |
PORT P0_PUDEN: P3 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_P3_Pos (3UL) |
PORT P0_PUDEN: P3 (Bit 3)
#define PORT_P0_PUDEN_P4_Msk (0x10UL) |
PORT P0_PUDEN: P4 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_P4_Pos (4UL) |
PORT P0_PUDEN: P4 (Bit 4)
#define PORT_P0_PUDSEL_P0_Msk (0x1UL) |
PORT P0_PUDSEL: P0 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_P0_Pos (0UL) |
PORT P0_PUDSEL: P0 (Bit 0)
#define PORT_P0_PUDSEL_P1_Msk (0x2UL) |
PORT P0_PUDSEL: P1 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_P1_Pos (1UL) |
PORT P0_PUDSEL: P1 (Bit 1)
#define PORT_P0_PUDSEL_P2_Msk (0x4UL) |
PORT P0_PUDSEL: P2 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_P2_Pos (2UL) |
PORT P0_PUDSEL: P2 (Bit 2)
#define PORT_P0_PUDSEL_P3_Msk (0x8UL) |
PORT P0_PUDSEL: P3 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_P3_Pos (3UL) |
PORT P0_PUDSEL: P3 (Bit 3)
#define PORT_P0_PUDSEL_P4_Msk (0x10UL) |
PORT P0_PUDSEL: P4 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_P4_Pos (4UL) |
PORT P0_PUDSEL: P4 (Bit 4)
#define PORT_P1_ALTSEL0_P0_Msk (0x1UL) |
PORT P1_ALTSEL0: P0 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_P0_Pos (0UL) |
PORT P1_ALTSEL0: P0 (Bit 0)
#define PORT_P1_ALTSEL0_P1_Msk (0x2UL) |
PORT P1_ALTSEL0: P1 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_P1_Pos (1UL) |
PORT P1_ALTSEL0: P1 (Bit 1)
#define PORT_P1_ALTSEL0_P2_Msk (0x4UL) |
PORT P1_ALTSEL0: P2 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_P2_Pos (2UL) |
PORT P1_ALTSEL0: P2 (Bit 2)
#define PORT_P1_ALTSEL0_P3_Msk (0x8UL) |
PORT P1_ALTSEL0: P3 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_P3_Pos (3UL) |
PORT P1_ALTSEL0: P3 (Bit 3)
#define PORT_P1_ALTSEL0_P4_Msk (0x10UL) |
PORT P1_ALTSEL0: P4 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_P4_Pos (4UL) |
PORT P1_ALTSEL0: P4 (Bit 4)
#define PORT_P1_ALTSEL1_P0_Msk (0x1UL) |
PORT P1_ALTSEL1: P0 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_P0_Pos (0UL) |
PORT P1_ALTSEL1: P0 (Bit 0)
#define PORT_P1_ALTSEL1_P1_Msk (0x2UL) |
PORT P1_ALTSEL1: P1 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_P1_Pos (1UL) |
PORT P1_ALTSEL1: P1 (Bit 1)
#define PORT_P1_ALTSEL1_P2_Msk (0x4UL) |
PORT P1_ALTSEL1: P2 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_P2_Pos (2UL) |
PORT P1_ALTSEL1: P2 (Bit 2)
#define PORT_P1_ALTSEL1_P3_Msk (0x8UL) |
PORT P1_ALTSEL1: P3 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_P3_Pos (3UL) |
PORT P1_ALTSEL1: P3 (Bit 3)
#define PORT_P1_ALTSEL1_P4_Msk (0x10UL) |
PORT P1_ALTSEL1: P4 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_P4_Pos (4UL) |
PORT P1_ALTSEL1: P4 (Bit 4)
#define PORT_P1_DATA_P0_Msk (0x1UL) |
PORT P1_DATA: P0 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_P0_Pos (0UL) |
PORT P1_DATA: P0 (Bit 0)
#define PORT_P1_DATA_P1_Msk (0x2UL) |
PORT P1_DATA: P1 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_P1_Pos (1UL) |
PORT P1_DATA: P1 (Bit 1)
#define PORT_P1_DATA_P2_Msk (0x4UL) |
PORT P1_DATA: P2 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_P2_Pos (2UL) |
PORT P1_DATA: P2 (Bit 2)
#define PORT_P1_DATA_P3_Msk (0x8UL) |
PORT P1_DATA: P3 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_P3_Pos (3UL) |
PORT P1_DATA: P3 (Bit 3)
#define PORT_P1_DATA_P4_Msk (0x10UL) |
PORT P1_DATA: P4 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_P4_Pos (4UL) |
PORT P1_DATA: P4 (Bit 4)
#define PORT_P1_DIR_P0_Msk (0x1UL) |
PORT P1_DIR: P0 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_P0_Pos (0UL) |
PORT P1_DIR: P0 (Bit 0)
#define PORT_P1_DIR_P1_Msk (0x2UL) |
PORT P1_DIR: P1 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_P1_Pos (1UL) |
PORT P1_DIR: P1 (Bit 1)
#define PORT_P1_DIR_P2_Msk (0x4UL) |
PORT P1_DIR: P2 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_P2_Pos (2UL) |
PORT P1_DIR: P2 (Bit 2)
#define PORT_P1_DIR_P3_Msk (0x8UL) |
PORT P1_DIR: P3 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_P3_Pos (3UL) |
PORT P1_DIR: P3 (Bit 3)
#define PORT_P1_DIR_P4_Msk (0x10UL) |
PORT P1_DIR: P4 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_P4_Pos (4UL) |
PORT P1_DIR: P4 (Bit 4)
#define PORT_P1_OD_P0_Msk (0x2UL) |
PORT P1_OD: P0 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_P0_Pos (1UL) |
PORT P1_OD: P0 (Bit 1)
#define PORT_P1_OD_P1_Msk (0x4UL) |
PORT P1_OD: P1 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_P1_Pos (2UL) |
PORT P1_OD: P1 (Bit 2)
#define PORT_P1_OD_P3_P2_Msk (0x8UL) |
PORT P1_OD: P3_P2 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_P3_P2_Pos (3UL) |
PORT P1_OD: P3_P2 (Bit 3)
#define PORT_P1_OD_P4_Msk (0x10UL) |
PORT P1_OD: P4 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_P4_Pos (4UL) |
PORT P1_OD: P4 (Bit 4)
#define PORT_P1_PUDEN_P0_Msk (0x1UL) |
PORT P1_PUDEN: P0 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_P0_Pos (0UL) |
PORT P1_PUDEN: P0 (Bit 0)
#define PORT_P1_PUDEN_P1_Msk (0x2UL) |
PORT P1_PUDEN: P1 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_P1_Pos (1UL) |
PORT P1_PUDEN: P1 (Bit 1)
#define PORT_P1_PUDEN_P2_Msk (0x4UL) |
PORT P1_PUDEN: P2 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_P2_Pos (2UL) |
PORT P1_PUDEN: P2 (Bit 2)
#define PORT_P1_PUDEN_P3_Msk (0x8UL) |
PORT P1_PUDEN: P3 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_P3_Pos (3UL) |
PORT P1_PUDEN: P3 (Bit 3)
#define PORT_P1_PUDEN_P4_Msk (0x10UL) |
PORT P1_PUDEN: P4 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_P4_Pos (4UL) |
PORT P1_PUDEN: P4 (Bit 4)
#define PORT_P1_PUDSEL_P0_Msk (0x1UL) |
PORT P1_PUDSEL: P0 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_P0_Pos (0UL) |
PORT P1_PUDSEL: P0 (Bit 0)
#define PORT_P1_PUDSEL_P1_Msk (0x2UL) |
PORT P1_PUDSEL: P1 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_P1_Pos (1UL) |
PORT P1_PUDSEL: P1 (Bit 1)
#define PORT_P1_PUDSEL_P2_Msk (0x4UL) |
PORT P1_PUDSEL: P2 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_P2_Pos (2UL) |
PORT P1_PUDSEL: P2 (Bit 2)
#define PORT_P1_PUDSEL_P3_Msk (0x8UL) |
PORT P1_PUDSEL: P3 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_P3_Pos (3UL) |
PORT P1_PUDSEL: P3 (Bit 3)
#define PORT_P1_PUDSEL_P4_Msk (0x10UL) |
PORT P1_PUDSEL: P4 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_P4_Pos (4UL) |
PORT P1_PUDSEL: P4 (Bit 4)
#define PORT_P2_DATA_P0_Msk (0x1UL) |
PORT P2_DATA: P0 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_P0_Pos (0UL) |
PORT P2_DATA: P0 (Bit 0)
#define PORT_P2_DATA_P1_Msk (0x2UL) |
PORT P2_DATA: P1 (Bitfield-Mask: 0x02)
#define PORT_P2_DATA_P1_Pos (1UL) |
PORT P2_DATA: P1 (Bit 1)
#define PORT_P2_DATA_P2_Msk (0x4UL) |
PORT P2_DATA: P2 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_P2_Pos (2UL) |
PORT P2_DATA: P2 (Bit 2)
#define PORT_P2_DATA_P3_Msk (0x8UL) |
PORT P2_DATA: P3 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_P3_Pos (3UL) |
PORT P2_DATA: P3 (Bit 3)
#define PORT_P2_DATA_P4_Msk (0x10UL) |
PORT P2_DATA: P4 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_P4_Pos (4UL) |
PORT P2_DATA: P4 (Bit 4)
#define PORT_P2_DATA_P5_Msk (0x20UL) |
PORT P2_DATA: P5 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_P5_Pos (5UL) |
PORT P2_DATA: P5 (Bit 5)
#define PORT_P2_DIR_P0_Msk (0x1UL) |
PORT P2_DIR: P0 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_P0_Pos (0UL) |
PORT P2_DIR: P0 (Bit 0)
#define PORT_P2_DIR_P1_Msk (0x2UL) |
PORT P2_DIR: P1 (Bitfield-Mask: 0x02)
#define PORT_P2_DIR_P1_Pos (1UL) |
PORT P2_DIR: P1 (Bit 1)
#define PORT_P2_DIR_P2_Msk (0x4UL) |
PORT P2_DIR: P2 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_P2_Pos (2UL) |
PORT P2_DIR: P2 (Bit 2)
#define PORT_P2_DIR_P3_Msk (0x8UL) |
PORT P2_DIR: P3 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_P3_Pos (3UL) |
PORT P2_DIR: P3 (Bit 3)
#define PORT_P2_DIR_P4_Msk (0x10UL) |
PORT P2_DIR: P4 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_P4_Pos (4UL) |
PORT P2_DIR: P4 (Bit 4)
#define PORT_P2_DIR_P5_Msk (0x20UL) |
PORT P2_DIR: P5 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_P5_Pos (5UL) |
PORT P2_DIR: P5 (Bit 5)
#define PORT_P2_PUDEN_P0_Msk (0x1UL) |
PORT P2_PUDEN: P0 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_P0_Pos (0UL) |
PORT P2_PUDEN: P0 (Bit 0)
#define PORT_P2_PUDEN_P1_Msk (0x2UL) |
PORT P2_PUDEN: P1 (Bitfield-Mask: 0x02)
#define PORT_P2_PUDEN_P1_Pos (1UL) |
PORT P2_PUDEN: P1 (Bit 1)
#define PORT_P2_PUDEN_P2_Msk (0x4UL) |
PORT P2_PUDEN: P2 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_P2_Pos (2UL) |
PORT P2_PUDEN: P2 (Bit 2)
#define PORT_P2_PUDEN_P3_Msk (0x8UL) |
PORT P2_PUDEN: P3 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_P3_Pos (3UL) |
PORT P2_PUDEN: P3 (Bit 3)
#define PORT_P2_PUDEN_P4_Msk (0x10UL) |
PORT P2_PUDEN: P4 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_P4_Pos (4UL) |
PORT P2_PUDEN: P4 (Bit 4)
#define PORT_P2_PUDEN_P5_Msk (0x20UL) |
PORT P2_PUDEN: P5 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_P5_Pos (5UL) |
PORT P2_PUDEN: P5 (Bit 5)
#define PORT_P2_PUDSEL_P0_Msk (0x1UL) |
PORT P2_PUDSEL: P0 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_P0_Pos (0UL) |
PORT P2_PUDSEL: P0 (Bit 0)
#define PORT_P2_PUDSEL_P1_Msk (0x2UL) |
PORT P2_PUDSEL: P1 (Bitfield-Mask: 0x02)
#define PORT_P2_PUDSEL_P1_Pos (1UL) |
PORT P2_PUDSEL: P1 (Bit 1)
#define PORT_P2_PUDSEL_P2_Msk (0x4UL) |
PORT P2_PUDSEL: P2 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_P2_Pos (2UL) |
PORT P2_PUDSEL: P2 (Bit 2)
#define PORT_P2_PUDSEL_P3_Msk (0x8UL) |
PORT P2_PUDSEL: P3 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_P3_Pos (3UL) |
PORT P2_PUDSEL: P3 (Bit 3)
#define PORT_P2_PUDSEL_P4_Msk (0x10UL) |
PORT P2_PUDSEL: P4 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_P4_Pos (4UL) |
PORT P2_PUDSEL: P4 (Bit 4)
#define PORT_P2_PUDSEL_P5_Msk (0x20UL) |
PORT P2_PUDSEL: P5 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_P5_Pos (5UL) |
PORT P2_PUDSEL: P5 (Bit 5)
#define SCU_APCLK1_APCLK1FAC_Msk (0x3UL) |
SCU APCLK1: APCLK1FAC (Bitfield-Mask: 0x03)
#define SCU_APCLK1_APCLK1FAC_Pos (0UL) |
SCU APCLK1: APCLK1FAC (Bit 0)
#define SCU_APCLK1_APCLK1SCLR_Msk (0x4UL) |
SCU APCLK1: APCLK1SCLR (Bitfield-Mask: 0x01)
#define SCU_APCLK1_APCLK1SCLR_Pos (2UL) |
SCU APCLK1: APCLK1SCLR (Bit 2)
#define SCU_APCLK1_APCLK1STS_Msk (0x30UL) |
SCU APCLK1: APCLK1STS (Bitfield-Mask: 0x03)
#define SCU_APCLK1_APCLK1STS_Pos (4UL) |
SCU APCLK1: APCLK1STS (Bit 4)
#define SCU_APCLK1_APCLK3SCLR_Msk (0x80UL) |
SCU APCLK1: APCLK3SCLR (Bitfield-Mask: 0x01)
#define SCU_APCLK1_APCLK3SCLR_Pos (7UL) |
SCU APCLK1: APCLK3SCLR (Bit 7)
#define SCU_APCLK1_APCLK3STS_Msk (0x40UL) |
SCU APCLK1: APCLK3STS (Bitfield-Mask: 0x01)
#define SCU_APCLK1_APCLK3STS_Pos (6UL) |
SCU APCLK1: APCLK3STS (Bit 6)
#define SCU_APCLK2_APCLK2FAC_Msk (0x1fUL) |
SCU APCLK2: APCLK2FAC (Bitfield-Mask: 0x1f)
#define SCU_APCLK2_APCLK2FAC_Pos (0UL) |
SCU APCLK2: APCLK2FAC (Bit 0)
#define SCU_APCLK2_APCLK2SCLR_Msk (0x80UL) |
SCU APCLK2: APCLK2SCLR (Bitfield-Mask: 0x01)
#define SCU_APCLK2_APCLK2SCLR_Pos (7UL) |
SCU APCLK2: APCLK2SCLR (Bit 7)
#define SCU_APCLK2_APCLK2STS_Msk (0x60UL) |
SCU APCLK2: APCLK2STS (Bitfield-Mask: 0x03)
#define SCU_APCLK2_APCLK2STS_Pos (5UL) |
SCU APCLK2: APCLK2STS (Bit 5)
#define SCU_APCLK_CTRL1_APCLK_SET_Msk (0x2UL) |
SCU APCLK_CTRL1: APCLK_SET (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_APCLK_SET_Pos (1UL) |
SCU APCLK_CTRL1: APCLK_SET (Bit 1)
#define SCU_APCLK_CTRL1_BGCLK_DIV_Msk (0x20UL) |
SCU APCLK_CTRL1: BGCLK_DIV (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_BGCLK_DIV_Pos (5UL) |
SCU APCLK_CTRL1: BGCLK_DIV (Bit 5)
#define SCU_APCLK_CTRL1_BGCLK_SEL_Msk (0x10UL) |
SCU APCLK_CTRL1: BGCLK_SEL (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_BGCLK_SEL_Pos (4UL) |
SCU APCLK_CTRL1: BGCLK_SEL (Bit 4)
#define SCU_APCLK_CTRL1_CLKWDT_IE_Msk (0x8UL) |
SCU APCLK_CTRL1: CLKWDT_IE (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_CLKWDT_IE_Pos (3UL) |
SCU APCLK_CTRL1: CLKWDT_IE (Bit 3)
#define SCU_APCLK_CTRL1_CPCLK_DIV_Msk (0x80UL) |
SCU APCLK_CTRL1: CPCLK_DIV (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_CPCLK_DIV_Pos (7UL) |
SCU APCLK_CTRL1: CPCLK_DIV (Bit 7)
#define SCU_APCLK_CTRL1_CPCLK_SEL_Msk (0x40UL) |
SCU APCLK_CTRL1: CPCLK_SEL (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_CPCLK_SEL_Pos (6UL) |
SCU APCLK_CTRL1: CPCLK_SEL (Bit 6)
#define SCU_APCLK_CTRL1_PLL_LOCK_Msk (0x1UL) |
SCU APCLK_CTRL1: PLL_LOCK (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_PLL_LOCK_Pos (0UL) |
SCU APCLK_CTRL1: PLL_LOCK (Bit 0)
#define SCU_APCLK_CTRL1_T3CLK_SEL_Msk (0x4UL) |
SCU APCLK_CTRL1: T3CLK_SEL (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL1_T3CLK_SEL_Pos (2UL) |
SCU APCLK_CTRL1: T3CLK_SEL (Bit 2)
#define SCU_APCLK_CTRL2_SDADCCLK_DIV_Msk (0x3UL) |
SCU APCLK_CTRL2: SDADCCLK_DIV (Bitfield-Mask: 0x03)
#define SCU_APCLK_CTRL2_SDADCCLK_DIV_Pos (0UL) |
SCU APCLK_CTRL2: SDADCCLK_DIV (Bit 0)
#define SCU_APCLK_CTRL2_T3CLK_DIV_Msk (0xcUL) |
SCU APCLK_CTRL2: T3CLK_DIV (Bitfield-Mask: 0x03)
#define SCU_APCLK_CTRL2_T3CLK_DIV_Pos (2UL) |
SCU APCLK_CTRL2: T3CLK_DIV (Bit 2)
#define SCU_BCON1_BRPRE_Msk (0xeUL) |
SCU BCON1: BRPRE (Bitfield-Mask: 0x07)
#define SCU_BCON1_BRPRE_Pos (1UL) |
SCU BCON1: BRPRE (Bit 1)
#define SCU_BCON1_R_Msk (0x1UL) |
SCU BCON1: R (Bitfield-Mask: 0x01)
#define SCU_BCON1_R_Pos (0UL) |
SCU BCON1: R (Bit 0)
#define SCU_BCON2_BRPRE_Msk (0xeUL) |
SCU BCON2: BRPRE (Bitfield-Mask: 0x07)
#define SCU_BCON2_BRPRE_Pos (1UL) |
SCU BCON2: BRPRE (Bit 1)
#define SCU_BCON2_R_Msk (0x1UL) |
SCU BCON2: R (Bitfield-Mask: 0x01)
#define SCU_BCON2_R_Pos (0UL) |
SCU BCON2: R (Bit 0)
#define SCU_BGH1_BR_VALUE_Msk (0xffUL) |
SCU BGH1: BR_VALUE (Bitfield-Mask: 0xff)
#define SCU_BGH1_BR_VALUE_Pos (0UL) |
SCU BGH1: BR_VALUE (Bit 0)
#define SCU_BGH2_BR_VALUE_Msk (0xffUL) |
SCU BGH2: BR_VALUE (Bitfield-Mask: 0xff)
#define SCU_BGH2_BR_VALUE_Pos (0UL) |
SCU BGH2: BR_VALUE (Bit 0)
#define SCU_BGL1_BR_VALUE_Msk (0xe0UL) |
SCU BGL1: BR_VALUE (Bitfield-Mask: 0x07)
#define SCU_BGL1_BR_VALUE_Pos (5UL) |
SCU BGL1: BR_VALUE (Bit 5)
#define SCU_BGL1_FD_SEL_Msk (0x1fUL) |
SCU BGL1: FD_SEL (Bitfield-Mask: 0x1f)
#define SCU_BGL1_FD_SEL_Pos (0UL) |
SCU BGL1: FD_SEL (Bit 0)
#define SCU_BGL2_BR_VALUE_Msk (0xe0UL) |
SCU BGL2: BR_VALUE (Bitfield-Mask: 0x07)
#define SCU_BGL2_BR_VALUE_Pos (5UL) |
SCU BGL2: BR_VALUE (Bit 5)
#define SCU_BGL2_FD_SEL_Msk (0x1fUL) |
SCU BGL2: FD_SEL (Bitfield-Mask: 0x1f)
#define SCU_BGL2_FD_SEL_Pos (0UL) |
SCU BGL2: FD_SEL (Bit 0)
#define SCU_CMCON1_CLKREL_Msk (0xfUL) |
SCU CMCON1: CLKREL (Bitfield-Mask: 0x0f)
#define SCU_CMCON1_CLKREL_Pos (0UL) |
SCU CMCON1: CLKREL (Bit 0)
#define SCU_CMCON1_K1DIV_Msk (0x40UL) |
SCU CMCON1: K1DIV (Bitfield-Mask: 0x01)
#define SCU_CMCON1_K1DIV_Pos (6UL) |
SCU CMCON1: K1DIV (Bit 6)
#define SCU_CMCON1_K2DIV_Msk (0x30UL) |
SCU CMCON1: K2DIV (Bitfield-Mask: 0x03)
#define SCU_CMCON1_K2DIV_Pos (4UL) |
SCU CMCON1: K2DIV (Bit 4)
#define SCU_CMCON1_VCOSEL_Msk (0x80UL) |
SCU CMCON1: VCOSEL (Bitfield-Mask: 0x01)
#define SCU_CMCON1_VCOSEL_Pos (7UL) |
SCU CMCON1: VCOSEL (Bit 7)
#define SCU_CMCON2_PBA0CLKREL_Msk (0x1UL) |
SCU CMCON2: PBA0CLKREL (Bitfield-Mask: 0x01)
#define SCU_CMCON2_PBA0CLKREL_Pos (0UL) |
SCU CMCON2: PBA0CLKREL (Bit 0)
#define SCU_COCON_COREL_Msk (0xfUL) |
SCU COCON: COREL (Bitfield-Mask: 0x0f)
#define SCU_COCON_COREL_Pos (0UL) |
SCU COCON: COREL (Bit 0)
#define SCU_COCON_COUTS0_Msk (0x10UL) |
SCU COCON: COUTS0 (Bitfield-Mask: 0x01)
#define SCU_COCON_COUTS0_Pos (4UL) |
SCU COCON: COUTS0 (Bit 4)
#define SCU_COCON_COUTS1_Msk (0x40UL) |
SCU COCON: COUTS1 (Bitfield-Mask: 0x01)
#define SCU_COCON_COUTS1_Pos (6UL) |
SCU COCON: COUTS1 (Bit 6)
#define SCU_COCON_EN_Msk (0x80UL) |
SCU COCON: EN (Bitfield-Mask: 0x01)
#define SCU_COCON_EN_Pos (7UL) |
SCU COCON: EN (Bit 7)
#define SCU_COCON_TLEN_Msk (0x20UL) |
SCU COCON: TLEN (Bitfield-Mask: 0x01)
#define SCU_COCON_TLEN_Pos (5UL) |
SCU COCON: TLEN (Bit 5)
#define SCU_DMAIEN1_CH1IE_Msk (0x1UL) |
SCU DMAIEN1: CH1IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH1IE_Pos (0UL) |
SCU DMAIEN1: CH1IE (Bit 0)
#define SCU_DMAIEN1_CH2IE_Msk (0x2UL) |
SCU DMAIEN1: CH2IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH2IE_Pos (1UL) |
SCU DMAIEN1: CH2IE (Bit 1)
#define SCU_DMAIEN1_CH3IE_Msk (0x4UL) |
SCU DMAIEN1: CH3IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH3IE_Pos (2UL) |
SCU DMAIEN1: CH3IE (Bit 2)
#define SCU_DMAIEN1_CH4IE_Msk (0x8UL) |
SCU DMAIEN1: CH4IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH4IE_Pos (3UL) |
SCU DMAIEN1: CH4IE (Bit 3)
#define SCU_DMAIEN1_CH5IE_Msk (0x10UL) |
SCU DMAIEN1: CH5IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH5IE_Pos (4UL) |
SCU DMAIEN1: CH5IE (Bit 4)
#define SCU_DMAIEN1_CH6IE_Msk (0x20UL) |
SCU DMAIEN1: CH6IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH6IE_Pos (5UL) |
SCU DMAIEN1: CH6IE (Bit 5)
#define SCU_DMAIEN1_CH7IE_Msk (0x40UL) |
SCU DMAIEN1: CH7IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH7IE_Pos (6UL) |
SCU DMAIEN1: CH7IE (Bit 6)
#define SCU_DMAIEN1_CH8IE_Msk (0x80UL) |
SCU DMAIEN1: CH8IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN1_CH8IE_Pos (7UL) |
SCU DMAIEN1: CH8IE (Bit 7)
#define SCU_DMAIEN2_GPT12IE_Msk (0x20UL) |
SCU DMAIEN2: GPT12IE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN2_GPT12IE_Pos (5UL) |
SCU DMAIEN2: GPT12IE (Bit 5)
#define SCU_DMAIEN2_SDADCIE_Msk (0x40UL) |
SCU DMAIEN2: SDADCIE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN2_SDADCIE_Pos (6UL) |
SCU DMAIEN2: SDADCIE (Bit 6)
#define SCU_DMAIEN2_SSCRXIE_Msk (0x10UL) |
SCU DMAIEN2: SSCRXIE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN2_SSCRXIE_Pos (4UL) |
SCU DMAIEN2: SSCRXIE (Bit 4)
#define SCU_DMAIEN2_SSCTXIE_Msk (0x8UL) |
SCU DMAIEN2: SSCTXIE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN2_SSCTXIE_Pos (3UL) |
SCU DMAIEN2: SSCTXIE (Bit 3)
#define SCU_DMAIEN2_TRERRIE_Msk (0x1UL) |
SCU DMAIEN2: TRERRIE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN2_TRERRIE_Pos (0UL) |
SCU DMAIEN2: TRERRIE (Bit 0)
#define SCU_DMAIEN2_TRSEQ1RDYIE_Msk (0x2UL) |
SCU DMAIEN2: TRSEQ1RDYIE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN2_TRSEQ1RDYIE_Pos (1UL) |
SCU DMAIEN2: TRSEQ1RDYIE (Bit 1)
#define SCU_DMAIEN2_TRSEQ2RDYIE_Msk (0x4UL) |
SCU DMAIEN2: TRSEQ2RDYIE (Bitfield-Mask: 0x01)
#define SCU_DMAIEN2_TRSEQ2RDYIE_Pos (2UL) |
SCU DMAIEN2: TRSEQ2RDYIE (Bit 2)
#define SCU_DMAIRC1_CH1_Msk (0x1UL) |
SCU DMAIRC1: CH1 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH1_Pos (0UL) |
SCU DMAIRC1: CH1 (Bit 0)
#define SCU_DMAIRC1_CH2_Msk (0x2UL) |
SCU DMAIRC1: CH2 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH2_Pos (1UL) |
SCU DMAIRC1: CH2 (Bit 1)
#define SCU_DMAIRC1_CH3_Msk (0x4UL) |
SCU DMAIRC1: CH3 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH3_Pos (2UL) |
SCU DMAIRC1: CH3 (Bit 2)
#define SCU_DMAIRC1_CH4_Msk (0x8UL) |
SCU DMAIRC1: CH4 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH4_Pos (3UL) |
SCU DMAIRC1: CH4 (Bit 3)
#define SCU_DMAIRC1_CH5_Msk (0x10UL) |
SCU DMAIRC1: CH5 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH5_Pos (4UL) |
SCU DMAIRC1: CH5 (Bit 4)
#define SCU_DMAIRC1_CH6_Msk (0x20UL) |
SCU DMAIRC1: CH6 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH6_Pos (5UL) |
SCU DMAIRC1: CH6 (Bit 5)
#define SCU_DMAIRC1_CH7_Msk (0x40UL) |
SCU DMAIRC1: CH7 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH7_Pos (6UL) |
SCU DMAIRC1: CH7 (Bit 6)
#define SCU_DMAIRC1_CH8_Msk (0x80UL) |
SCU DMAIRC1: CH8 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1_CH8_Pos (7UL) |
SCU DMAIRC1: CH8 (Bit 7)
#define SCU_DMAIRC1CLR_CH1C_Msk (0x1UL) |
SCU DMAIRC1CLR: CH1C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH1C_Pos (0UL) |
SCU DMAIRC1CLR: CH1C (Bit 0)
#define SCU_DMAIRC1CLR_CH2C_Msk (0x2UL) |
SCU DMAIRC1CLR: CH2C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH2C_Pos (1UL) |
SCU DMAIRC1CLR: CH2C (Bit 1)
#define SCU_DMAIRC1CLR_CH3C_Msk (0x4UL) |
SCU DMAIRC1CLR: CH3C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH3C_Pos (2UL) |
SCU DMAIRC1CLR: CH3C (Bit 2)
#define SCU_DMAIRC1CLR_CH4C_Msk (0x8UL) |
SCU DMAIRC1CLR: CH4C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH4C_Pos (3UL) |
SCU DMAIRC1CLR: CH4C (Bit 3)
#define SCU_DMAIRC1CLR_CH5C_Msk (0x10UL) |
SCU DMAIRC1CLR: CH5C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH5C_Pos (4UL) |
SCU DMAIRC1CLR: CH5C (Bit 4)
#define SCU_DMAIRC1CLR_CH6C_Msk (0x20UL) |
SCU DMAIRC1CLR: CH6C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH6C_Pos (5UL) |
SCU DMAIRC1CLR: CH6C (Bit 5)
#define SCU_DMAIRC1CLR_CH7C_Msk (0x40UL) |
SCU DMAIRC1CLR: CH7C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH7C_Pos (6UL) |
SCU DMAIRC1CLR: CH7C (Bit 6)
#define SCU_DMAIRC1CLR_CH8C_Msk (0x80UL) |
SCU DMAIRC1CLR: CH8C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC1CLR_CH8C_Pos (7UL) |
SCU DMAIRC1CLR: CH8C (Bit 7)
#define SCU_DMAIRC2_GPT12_Msk (0x20UL) |
SCU DMAIRC2: GPT12 (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2_GPT12_Pos (5UL) |
SCU DMAIRC2: GPT12 (Bit 5)
#define SCU_DMAIRC2_SDADC_Msk (0x40UL) |
SCU DMAIRC2: SDADC (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2_SDADC_Pos (6UL) |
SCU DMAIRC2: SDADC (Bit 6)
#define SCU_DMAIRC2_SSC1RDY_Msk (0x8UL) |
SCU DMAIRC2: SSC1RDY (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2_SSC1RDY_Pos (3UL) |
SCU DMAIRC2: SSC1RDY (Bit 3)
#define SCU_DMAIRC2_SSC2RDY_Msk (0x10UL) |
SCU DMAIRC2: SSC2RDY (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2_SSC2RDY_Pos (4UL) |
SCU DMAIRC2: SSC2RDY (Bit 4)
#define SCU_DMAIRC2_STRDY_Msk (0x1UL) |
SCU DMAIRC2: STRDY (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2_STRDY_Pos (0UL) |
SCU DMAIRC2: STRDY (Bit 0)
#define SCU_DMAIRC2_TRSEQ1DY_Msk (0x2UL) |
SCU DMAIRC2: TRSEQ1DY (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2_TRSEQ1DY_Pos (1UL) |
SCU DMAIRC2: TRSEQ1DY (Bit 1)
#define SCU_DMAIRC2_TRSEQ2DY_Msk (0x4UL) |
SCU DMAIRC2: TRSEQ2DY (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2_TRSEQ2DY_Pos (2UL) |
SCU DMAIRC2: TRSEQ2DY (Bit 2)
#define SCU_DMAIRC2CLR_GPT12C_Msk (0x20UL) |
SCU DMAIRC2CLR: GPT12C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2CLR_GPT12C_Pos (5UL) |
SCU DMAIRC2CLR: GPT12C (Bit 5)
#define SCU_DMAIRC2CLR_SDADCC_Msk (0x40UL) |
SCU DMAIRC2CLR: SDADCC (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2CLR_SDADCC_Pos (6UL) |
SCU DMAIRC2CLR: SDADCC (Bit 6)
#define SCU_DMAIRC2CLR_SSC1C_Msk (0x8UL) |
SCU DMAIRC2CLR: SSC1C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2CLR_SSC1C_Pos (3UL) |
SCU DMAIRC2CLR: SSC1C (Bit 3)
#define SCU_DMAIRC2CLR_SSC2C_Msk (0x10UL) |
SCU DMAIRC2CLR: SSC2C (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2CLR_SSC2C_Pos (4UL) |
SCU DMAIRC2CLR: SSC2C (Bit 4)
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk (0x2UL) |
SCU DMAIRC2CLR: TRSEQ1DYC (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos (1UL) |
SCU DMAIRC2CLR: TRSEQ1DYC (Bit 1)
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk (0x4UL) |
SCU DMAIRC2CLR: TRSEQ2DYC (Bitfield-Mask: 0x01)
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos (2UL) |
SCU DMAIRC2CLR: TRSEQ2DYC (Bit 2)
#define SCU_DMASRCCLR_GPT12_T3C_Msk (0x80UL) |
SCU DMASRCCLR: GPT12_T3C (Bitfield-Mask: 0x01)
#define SCU_DMASRCCLR_GPT12_T3C_Pos (7UL) |
SCU DMASRCCLR: GPT12_T3C (Bit 7)
#define SCU_DMASRCCLR_SSCRXC_Msk (0x40UL) |
SCU DMASRCCLR: SSCRXC (Bitfield-Mask: 0x01)
#define SCU_DMASRCCLR_SSCRXC_Pos (6UL) |
SCU DMASRCCLR: SSCRXC (Bit 6)
#define SCU_DMASRCCLR_SSCTXC_Msk (0x20UL) |
SCU DMASRCCLR: SSCTXC (Bitfield-Mask: 0x01)
#define SCU_DMASRCCLR_SSCTXC_Pos (5UL) |
SCU DMASRCCLR: SSCTXC (Bit 5)
#define SCU_DMASRCSEL2_GPT12_DMAEN_Msk (0x3UL) |
SCU DMASRCSEL2: GPT12_DMAEN (Bitfield-Mask: 0x03)
#define SCU_DMASRCSEL2_GPT12_DMAEN_Pos (0UL) |
SCU DMASRCSEL2: GPT12_DMAEN (Bit 0)
#define SCU_DMASRCSEL_GPT12_T3_Msk (0x80UL) |
SCU DMASRCSEL: GPT12_T3 (Bitfield-Mask: 0x01)
#define SCU_DMASRCSEL_GPT12_T3_Pos (7UL) |
SCU DMASRCSEL: GPT12_T3 (Bit 7)
#define SCU_DMASRCSEL_SSCRX_Msk (0x40UL) |
SCU DMASRCSEL: SSCRX (Bitfield-Mask: 0x01)
#define SCU_DMASRCSEL_SSCRX_Pos (6UL) |
SCU DMASRCSEL: SSCRX (Bit 6)
#define SCU_DMASRCSEL_SSCRXSRCSEL_Msk (0x2UL) |
SCU DMASRCSEL: SSCRXSRCSEL (Bitfield-Mask: 0x01)
#define SCU_DMASRCSEL_SSCRXSRCSEL_Pos (1UL) |
SCU DMASRCSEL: SSCRXSRCSEL (Bit 1)
#define SCU_DMASRCSEL_SSCTX_Msk (0x20UL) |
SCU DMASRCSEL: SSCTX (Bitfield-Mask: 0x01)
#define SCU_DMASRCSEL_SSCTX_Pos (5UL) |
SCU DMASRCSEL: SSCTX (Bit 5)
#define SCU_DMASRCSEL_SSCTXSRCSEL_Msk (0x1UL) |
SCU DMASRCSEL: SSCTXSRCSEL (Bitfield-Mask: 0x01)
#define SCU_DMASRCSEL_SSCTXSRCSEL_Pos (0UL) |
SCU DMASRCSEL: SSCTXSRCSEL (Bit 0)
#define SCU_DMASRCSEL_T12PM_DMAEN_Msk (0x8UL) |
SCU DMASRCSEL: T12PM_DMAEN (Bitfield-Mask: 0x01)
#define SCU_DMASRCSEL_T12PM_DMAEN_Pos (3UL) |
SCU DMASRCSEL: T12PM_DMAEN (Bit 3)
#define SCU_DMASRCSEL_T12ZM_DMAEN_Msk (0x4UL) |
SCU DMASRCSEL: T12ZM_DMAEN (Bitfield-Mask: 0x01)
#define SCU_DMASRCSEL_T12ZM_DMAEN_Pos (2UL) |
SCU DMASRCSEL: T12ZM_DMAEN (Bit 2)
#define SCU_EDCCON_NVMIE_Msk (0x4UL) |
SCU EDCCON: NVMIE (Bitfield-Mask: 0x01)
#define SCU_EDCCON_NVMIE_Pos (2UL) |
SCU EDCCON: NVMIE (Bit 2)
#define SCU_EDCCON_RIE_Msk (0x1UL) |
SCU EDCCON: RIE (Bitfield-Mask: 0x01)
#define SCU_EDCCON_RIE_Pos (0UL) |
SCU EDCCON: RIE (Bit 0)
#define SCU_EDCSCLR_NVMDBEC_Msk (0x4UL) |
SCU EDCSCLR: NVMDBEC (Bitfield-Mask: 0x01)
#define SCU_EDCSCLR_NVMDBEC_Pos (2UL) |
SCU EDCSCLR: NVMDBEC (Bit 2)
#define SCU_EDCSCLR_RDBEC_Msk (0x1UL) |
SCU EDCSCLR: RDBEC (Bitfield-Mask: 0x01)
#define SCU_EDCSCLR_RDBEC_Pos (0UL) |
SCU EDCSCLR: RDBEC (Bit 0)
#define SCU_EDCSCLR_RSBEC_Msk (0x10UL) |
SCU EDCSCLR: RSBEC (Bitfield-Mask: 0x01)
#define SCU_EDCSCLR_RSBEC_Pos (4UL) |
SCU EDCSCLR: RSBEC (Bit 4)
#define SCU_EDCSTAT_NVMDBE_Msk (0x4UL) |
SCU EDCSTAT: NVMDBE (Bitfield-Mask: 0x01)
#define SCU_EDCSTAT_NVMDBE_Pos (2UL) |
SCU EDCSTAT: NVMDBE (Bit 2)
#define SCU_EDCSTAT_RDBE_Msk (0x1UL) |
SCU EDCSTAT: RDBE (Bitfield-Mask: 0x01)
#define SCU_EDCSTAT_RDBE_Pos (0UL) |
SCU EDCSTAT: RDBE (Bit 0)
#define SCU_EDCSTAT_RSBE_Msk (0x10UL) |
SCU EDCSTAT: RSBE (Bitfield-Mask: 0x01)
#define SCU_EDCSTAT_RSBE_Pos (4UL) |
SCU EDCSTAT: RSBE (Bit 4)
#define SCU_EXICON0_EXINT0_Msk (0x3UL) |
SCU EXICON0: EXINT0 (Bitfield-Mask: 0x03)
#define SCU_EXICON0_EXINT0_Pos (0UL) |
SCU EXICON0: EXINT0 (Bit 0)
#define SCU_EXICON0_EXINT1_Msk (0xcUL) |
SCU EXICON0: EXINT1 (Bitfield-Mask: 0x03)
#define SCU_EXICON0_EXINT1_Pos (2UL) |
SCU EXICON0: EXINT1 (Bit 2)
#define SCU_EXICON0_EXINT2_Msk (0x30UL) |
SCU EXICON0: EXINT2 (Bitfield-Mask: 0x03)
#define SCU_EXICON0_EXINT2_Pos (4UL) |
SCU EXICON0: EXINT2 (Bit 4)
#define SCU_EXICON0_MON_Trig_Sel_Msk (0xc0UL) |
SCU EXICON0: MON_Trig_Sel (Bitfield-Mask: 0x03)
#define SCU_EXICON0_MON_Trig_Sel_Pos (6UL) |
SCU EXICON0: MON_Trig_Sel (Bit 6)
#define SCU_GPT12ICLR_CRC_Msk (0x20UL) |
SCU GPT12ICLR: CRC (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_CRC_Pos (5UL) |
SCU GPT12ICLR: CRC (Bit 5)
#define SCU_GPT12ICLR_T2C_Msk (0x1UL) |
SCU GPT12ICLR: T2C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_T2C_Pos (0UL) |
SCU GPT12ICLR: T2C (Bit 0)
#define SCU_GPT12ICLR_T3C_Msk (0x2UL) |
SCU GPT12ICLR: T3C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_T3C_Pos (1UL) |
SCU GPT12ICLR: T3C (Bit 1)
#define SCU_GPT12ICLR_T4C_Msk (0x4UL) |
SCU GPT12ICLR: T4C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_T4C_Pos (2UL) |
SCU GPT12ICLR: T4C (Bit 2)
#define SCU_GPT12ICLR_T5C_Msk (0x8UL) |
SCU GPT12ICLR: T5C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_T5C_Pos (3UL) |
SCU GPT12ICLR: T5C (Bit 3)
#define SCU_GPT12ICLR_T6C_Msk (0x10UL) |
SCU GPT12ICLR: T6C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_T6C_Pos (4UL) |
SCU GPT12ICLR: T6C (Bit 4)
#define SCU_GPT12IEN_CRIE_Msk (0x20UL) |
SCU GPT12IEN: CRIE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_CRIE_Pos (5UL) |
SCU GPT12IEN: CRIE (Bit 5)
#define SCU_GPT12IEN_T2IE_Msk (0x1UL) |
SCU GPT12IEN: T2IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T2IE_Pos (0UL) |
SCU GPT12IEN: T2IE (Bit 0)
#define SCU_GPT12IEN_T3IE_Msk (0x2UL) |
SCU GPT12IEN: T3IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T3IE_Pos (1UL) |
SCU GPT12IEN: T3IE (Bit 1)
#define SCU_GPT12IEN_T4IE_Msk (0x4UL) |
SCU GPT12IEN: T4IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T4IE_Pos (2UL) |
SCU GPT12IEN: T4IE (Bit 2)
#define SCU_GPT12IEN_T5IE_Msk (0x8UL) |
SCU GPT12IEN: T5IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T5IE_Pos (3UL) |
SCU GPT12IEN: T5IE (Bit 3)
#define SCU_GPT12IEN_T6IE_Msk (0x10UL) |
SCU GPT12IEN: T6IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T6IE_Pos (4UL) |
SCU GPT12IEN: T6IE (Bit 4)
#define SCU_GPT12IRC_CR_Msk (0x20UL) |
SCU GPT12IRC: CR (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_CR_Pos (5UL) |
SCU GPT12IRC: CR (Bit 5)
#define SCU_GPT12IRC_T2_Msk (0x1UL) |
SCU GPT12IRC: T2 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_T2_Pos (0UL) |
SCU GPT12IRC: T2 (Bit 0)
#define SCU_GPT12IRC_T3_Msk (0x2UL) |
SCU GPT12IRC: T3 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_T3_Pos (1UL) |
SCU GPT12IRC: T3 (Bit 1)
#define SCU_GPT12IRC_T4_Msk (0x4UL) |
SCU GPT12IRC: T4 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_T4_Pos (2UL) |
SCU GPT12IRC: T4 (Bit 2)
#define SCU_GPT12IRC_T5_Msk (0x8UL) |
SCU GPT12IRC: T5 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_T5_Pos (3UL) |
SCU GPT12IRC: T5 (Bit 3)
#define SCU_GPT12IRC_T6_Msk (0x10UL) |
SCU GPT12IRC: T6 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_T6_Pos (4UL) |
SCU GPT12IRC: T6 (Bit 4)
#define SCU_GPT12PISEL_GPT12_Msk (0xfUL) |
SCU GPT12PISEL: GPT12 (Bitfield-Mask: 0x0f)
#define SCU_GPT12PISEL_GPT12_Pos (0UL) |
SCU GPT12PISEL: GPT12 (Bit 0)
#define SCU_GPT12PISEL_T3_GPT12_SEL_Msk (0x20UL) |
SCU GPT12PISEL: T3_GPT12_SEL (Bitfield-Mask: 0x01)
#define SCU_GPT12PISEL_T3_GPT12_SEL_Pos (5UL) |
SCU GPT12PISEL: T3_GPT12_SEL (Bit 5)
#define SCU_GPT12PISEL_TRIG_CONF_Msk (0x10UL) |
SCU GPT12PISEL: TRIG_CONF (Bitfield-Mask: 0x01)
#define SCU_GPT12PISEL_TRIG_CONF_Pos (4UL) |
SCU GPT12PISEL: TRIG_CONF (Bit 4)
#define SCU_ID_PRODID_Msk (0xf8UL) |
SCU ID: PRODID (Bitfield-Mask: 0x1f)
#define SCU_ID_PRODID_Pos (3UL) |
SCU ID: PRODID (Bit 3)
#define SCU_ID_VERID_Msk (0x7UL) |
SCU ID: VERID (Bitfield-Mask: 0x07)
#define SCU_ID_VERID_Pos (0UL) |
SCU ID: VERID (Bit 0)
#define SCU_IEN0_EA_Msk (0x80UL) |
SCU IEN0: EA (Bitfield-Mask: 0x01)
#define SCU_IEN0_EA_Pos (7UL) |
SCU IEN0: EA (Bit 7)
#define SCU_IRCON0_EXINT0F_Msk (0x2UL) |
SCU IRCON0: EXINT0F (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT0F_Pos (1UL) |
SCU IRCON0: EXINT0F (Bit 1)
#define SCU_IRCON0_EXINT0R_Msk (0x1UL) |
SCU IRCON0: EXINT0R (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT0R_Pos (0UL) |
SCU IRCON0: EXINT0R (Bit 0)
#define SCU_IRCON0_EXINT1F_Msk (0x8UL) |
SCU IRCON0: EXINT1F (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT1F_Pos (3UL) |
SCU IRCON0: EXINT1F (Bit 3)
#define SCU_IRCON0_EXINT1R_Msk (0x4UL) |
SCU IRCON0: EXINT1R (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT1R_Pos (2UL) |
SCU IRCON0: EXINT1R (Bit 2)
#define SCU_IRCON0_EXINT2F_Msk (0x20UL) |
SCU IRCON0: EXINT2F (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT2F_Pos (5UL) |
SCU IRCON0: EXINT2F (Bit 5)
#define SCU_IRCON0_EXINT2R_Msk (0x10UL) |
SCU IRCON0: EXINT2R (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT2R_Pos (4UL) |
SCU IRCON0: EXINT2R (Bit 4)
#define SCU_IRCON0_MONF_Msk (0x80UL) |
SCU IRCON0: MONF (Bitfield-Mask: 0x01)
#define SCU_IRCON0_MONF_Pos (7UL) |
SCU IRCON0: MONF (Bit 7)
#define SCU_IRCON0_MONR_Msk (0x40UL) |
SCU IRCON0: MONR (Bitfield-Mask: 0x01)
#define SCU_IRCON0_MONR_Pos (6UL) |
SCU IRCON0: MONR (Bit 6)
#define SCU_IRCON0CLR_EXINT0FC_Msk (0x2UL) |
SCU IRCON0CLR: EXINT0FC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT0FC_Pos (1UL) |
SCU IRCON0CLR: EXINT0FC (Bit 1)
#define SCU_IRCON0CLR_EXINT0RC_Msk (0x1UL) |
SCU IRCON0CLR: EXINT0RC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT0RC_Pos (0UL) |
SCU IRCON0CLR: EXINT0RC (Bit 0)
#define SCU_IRCON0CLR_EXINT1FC_Msk (0x8UL) |
SCU IRCON0CLR: EXINT1FC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT1FC_Pos (3UL) |
SCU IRCON0CLR: EXINT1FC (Bit 3)
#define SCU_IRCON0CLR_EXINT1RC_Msk (0x4UL) |
SCU IRCON0CLR: EXINT1RC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT1RC_Pos (2UL) |
SCU IRCON0CLR: EXINT1RC (Bit 2)
#define SCU_IRCON0CLR_EXINT2FC_Msk (0x20UL) |
SCU IRCON0CLR: EXINT2FC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT2FC_Pos (5UL) |
SCU IRCON0CLR: EXINT2FC (Bit 5)
#define SCU_IRCON0CLR_EXINT2RC_Msk (0x10UL) |
SCU IRCON0CLR: EXINT2RC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT2RC_Pos (4UL) |
SCU IRCON0CLR: EXINT2RC (Bit 4)
#define SCU_IRCON0CLR_MONFC_Msk (0x80UL) |
SCU IRCON0CLR: MONFC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_MONFC_Pos (7UL) |
SCU IRCON0CLR: MONFC (Bit 7)
#define SCU_IRCON0CLR_MONRC_Msk (0x40UL) |
SCU IRCON0CLR: MONRC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_MONRC_Pos (6UL) |
SCU IRCON0CLR: MONRC (Bit 6)
#define SCU_IRCON1_EIR_Msk (0x1UL) |
SCU IRCON1: EIR (Bitfield-Mask: 0x01)
#define SCU_IRCON1_EIR_Pos (0UL) |
SCU IRCON1: EIR (Bit 0)
#define SCU_IRCON1_RIR_Msk (0x4UL) |
SCU IRCON1: RIR (Bitfield-Mask: 0x01)
#define SCU_IRCON1_RIR_Pos (2UL) |
SCU IRCON1: RIR (Bit 2)
#define SCU_IRCON1_TIR_Msk (0x2UL) |
SCU IRCON1: TIR (Bitfield-Mask: 0x01)
#define SCU_IRCON1_TIR_Pos (1UL) |
SCU IRCON1: TIR (Bit 1)
#define SCU_IRCON1CLR_EIRC_Msk (0x1UL) |
SCU IRCON1CLR: EIRC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_EIRC_Pos (0UL) |
SCU IRCON1CLR: EIRC (Bit 0)
#define SCU_IRCON1CLR_RIRC_Msk (0x4UL) |
SCU IRCON1CLR: RIRC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_RIRC_Pos (2UL) |
SCU IRCON1CLR: RIRC (Bit 2)
#define SCU_IRCON1CLR_TIRC_Msk (0x2UL) |
SCU IRCON1CLR: TIRC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_TIRC_Pos (1UL) |
SCU IRCON1CLR: TIRC (Bit 1)
#define SCU_IRCON2_EIR_Msk (0x1UL) |
SCU IRCON2: EIR (Bitfield-Mask: 0x01)
#define SCU_IRCON2_EIR_Pos (0UL) |
SCU IRCON2: EIR (Bit 0)
#define SCU_IRCON2_RIR_Msk (0x4UL) |
SCU IRCON2: RIR (Bitfield-Mask: 0x01)
#define SCU_IRCON2_RIR_Pos (2UL) |
SCU IRCON2: RIR (Bit 2)
#define SCU_IRCON2_TIR_Msk (0x2UL) |
SCU IRCON2: TIR (Bitfield-Mask: 0x01)
#define SCU_IRCON2_TIR_Pos (1UL) |
SCU IRCON2: TIR (Bit 1)
#define SCU_IRCON2CLR_EIRC_Msk (0x1UL) |
SCU IRCON2CLR: EIRC (Bitfield-Mask: 0x01)
#define SCU_IRCON2CLR_EIRC_Pos (0UL) |
SCU IRCON2CLR: EIRC (Bit 0)
#define SCU_IRCON2CLR_RIRC_Msk (0x4UL) |
SCU IRCON2CLR: RIRC (Bitfield-Mask: 0x01)
#define SCU_IRCON2CLR_RIRC_Pos (2UL) |
SCU IRCON2CLR: RIRC (Bit 2)
#define SCU_IRCON2CLR_TIRC_Msk (0x2UL) |
SCU IRCON2CLR: TIRC (Bitfield-Mask: 0x01)
#define SCU_IRCON2CLR_TIRC_Pos (1UL) |
SCU IRCON2CLR: TIRC (Bit 1)
#define SCU_IRCON3_CCU6SR0_Msk (0x1UL) |
SCU IRCON3: CCU6SR0 (Bitfield-Mask: 0x01)
#define SCU_IRCON3_CCU6SR0_Pos (0UL) |
SCU IRCON3: CCU6SR0 (Bit 0)
#define SCU_IRCON3_CCU6SR1_Msk (0x10UL) |
SCU IRCON3: CCU6SR1 (Bitfield-Mask: 0x01)
#define SCU_IRCON3_CCU6SR1_Pos (4UL) |
SCU IRCON3: CCU6SR1 (Bit 4)
#define SCU_IRCON3CLR_CCU6SR0C_Msk (0x1UL) |
SCU IRCON3CLR: CCU6SR0C (Bitfield-Mask: 0x01)
#define SCU_IRCON3CLR_CCU6SR0C_Pos (0UL) |
SCU IRCON3CLR: CCU6SR0C (Bit 0)
#define SCU_IRCON3CLR_CCU6SR1C_Msk (0x10UL) |
SCU IRCON3CLR: CCU6SR1C (Bitfield-Mask: 0x01)
#define SCU_IRCON3CLR_CCU6SR1C_Pos (4UL) |
SCU IRCON3CLR: CCU6SR1C (Bit 4)
#define SCU_IRCON4_CCU6SR2_Msk (0x1UL) |
SCU IRCON4: CCU6SR2 (Bitfield-Mask: 0x01)
#define SCU_IRCON4_CCU6SR2_Pos (0UL) |
SCU IRCON4: CCU6SR2 (Bit 0)
#define SCU_IRCON4_CCU6SR3_Msk (0x10UL) |
SCU IRCON4: CCU6SR3 (Bitfield-Mask: 0x01)
#define SCU_IRCON4_CCU6SR3_Pos (4UL) |
SCU IRCON4: CCU6SR3 (Bit 4)
#define SCU_IRCON4CLR_CCU6SR2C_Msk (0x1UL) |
SCU IRCON4CLR: CCU6SR2C (Bitfield-Mask: 0x01)
#define SCU_IRCON4CLR_CCU6SR2C_Pos (0UL) |
SCU IRCON4CLR: CCU6SR2C (Bit 0)
#define SCU_IRCON4CLR_CCU6SR3C_Msk (0x10UL) |
SCU IRCON4CLR: CCU6SR3C (Bitfield-Mask: 0x01)
#define SCU_IRCON4CLR_CCU6SR3C_Pos (4UL) |
SCU IRCON4CLR: CCU6SR3C (Bit 4)
#define SCU_LINSCLR_BRKC_Msk (0x8UL) |
SCU LINSCLR: BRKC (Bitfield-Mask: 0x01)
#define SCU_LINSCLR_BRKC_Pos (3UL) |
SCU LINSCLR: BRKC (Bit 3)
#define SCU_LINSCLR_EOFSYNC_Msk (0x10UL) |
SCU LINSCLR: EOFSYNC (Bitfield-Mask: 0x01)
#define SCU_LINSCLR_EOFSYNC_Pos (4UL) |
SCU LINSCLR: EOFSYNC (Bit 4)
#define SCU_LINSCLR_ERRSYNC_Msk (0x20UL) |
SCU LINSCLR: ERRSYNC (Bitfield-Mask: 0x01)
#define SCU_LINSCLR_ERRSYNC_Pos (5UL) |
SCU LINSCLR: ERRSYNC (Bit 5)
#define SCU_LINST_BGSEL_Msk (0x6UL) |
SCU LINST: BGSEL (Bitfield-Mask: 0x03)
#define SCU_LINST_BGSEL_Pos (1UL) |
SCU LINST: BGSEL (Bit 1)
#define SCU_LINST_BRDIS_Msk (0x1UL) |
SCU LINST: BRDIS (Bitfield-Mask: 0x01)
#define SCU_LINST_BRDIS_Pos (0UL) |
SCU LINST: BRDIS (Bit 0)
#define SCU_LINST_BRK_Msk (0x8UL) |
SCU LINST: BRK (Bitfield-Mask: 0x01)
#define SCU_LINST_BRK_Pos (3UL) |
SCU LINST: BRK (Bit 3)
#define SCU_LINST_EOFSYN_Msk (0x10UL) |
SCU LINST: EOFSYN (Bitfield-Mask: 0x01)
#define SCU_LINST_EOFSYN_Pos (4UL) |
SCU LINST: EOFSYN (Bit 4)
#define SCU_LINST_ERRSYN_Msk (0x20UL) |
SCU LINST: ERRSYN (Bitfield-Mask: 0x01)
#define SCU_LINST_ERRSYN_Pos (5UL) |
SCU LINST: ERRSYN (Bit 5)
#define SCU_LINST_SYNEN_Msk (0x40UL) |
SCU LINST: SYNEN (Bitfield-Mask: 0x01)
#define SCU_LINST_SYNEN_Pos (6UL) |
SCU LINST: SYNEN (Bit 6)
#define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Msk (0x2UL) |
SCU MEM_ACC_STS: NVM_ADDR_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Pos (1UL) |
SCU MEM_ACC_STS: NVM_ADDR_ERR (Bit 1)
#define SCU_MEM_ACC_STS_NVM_PROT_ERR_Msk (0x1UL) |
SCU MEM_ACC_STS: NVM_PROT_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_PROT_ERR_Pos (0UL) |
SCU MEM_ACC_STS: NVM_PROT_ERR (Bit 0)
#define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Msk (0x8UL) |
SCU MEM_ACC_STS: NVM_SFR_ADDR_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Pos (3UL) |
SCU MEM_ACC_STS: NVM_SFR_ADDR_ERR (Bit 3)
#define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Msk (0x4UL) |
SCU MEM_ACC_STS: NVM_SFR_PROT_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Pos (2UL) |
SCU MEM_ACC_STS: NVM_SFR_PROT_ERR (Bit 2)
#define SCU_MEM_ACC_STS_RAM_PROT_ERR_Msk (0x40UL) |
SCU MEM_ACC_STS: RAM_PROT_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_RAM_PROT_ERR_Pos (6UL) |
SCU MEM_ACC_STS: RAM_PROT_ERR (Bit 6)
#define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Msk (0x20UL) |
SCU MEM_ACC_STS: ROM_ADDR_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Pos (5UL) |
SCU MEM_ACC_STS: ROM_ADDR_ERR (Bit 5)
#define SCU_MEM_ACC_STS_ROM_PROT_ERR_Msk (0x10UL) |
SCU MEM_ACC_STS: ROM_PROT_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_ROM_PROT_ERR_Pos (4UL) |
SCU MEM_ACC_STS: ROM_PROT_ERR (Bit 4)
#define SCU_MEMSTAT_SASTATUS_Msk (0xc0UL) |
SCU MEMSTAT: SASTATUS (Bitfield-Mask: 0x03)
#define SCU_MEMSTAT_SASTATUS_Pos (6UL) |
SCU MEMSTAT: SASTATUS (Bit 6)
#define SCU_MEMSTAT_SECTORINFO_Msk (0x3fUL) |
SCU MEMSTAT: SECTORINFO (Bitfield-Mask: 0x3f)
#define SCU_MEMSTAT_SECTORINFO_Pos (0UL) |
SCU MEMSTAT: SECTORINFO (Bit 0)
#define SCU_MODIEN1_EIREN1_Msk (0x1UL) |
SCU MODIEN1: EIREN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_EIREN1_Pos (0UL) |
SCU MODIEN1: EIREN1 (Bit 0)
#define SCU_MODIEN1_RIEN1_Msk (0x40UL) |
SCU MODIEN1: RIEN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_RIEN1_Pos (6UL) |
SCU MODIEN1: RIEN1 (Bit 6)
#define SCU_MODIEN1_RIREN1_Msk (0x4UL) |
SCU MODIEN1: RIREN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_RIREN1_Pos (2UL) |
SCU MODIEN1: RIREN1 (Bit 2)
#define SCU_MODIEN1_TIEN1_Msk (0x80UL) |
SCU MODIEN1: TIEN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_TIEN1_Pos (7UL) |
SCU MODIEN1: TIEN1 (Bit 7)
#define SCU_MODIEN1_TIREN1_Msk (0x2UL) |
SCU MODIEN1: TIREN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_TIREN1_Pos (1UL) |
SCU MODIEN1: TIREN1 (Bit 1)
#define SCU_MODIEN2_EIREN2_Msk (0x1UL) |
SCU MODIEN2: EIREN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_EIREN2_Pos (0UL) |
SCU MODIEN2: EIREN2 (Bit 0)
#define SCU_MODIEN2_EXINT2_EN_Msk (0x20UL) |
SCU MODIEN2: EXINT2_EN (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_EXINT2_EN_Pos (5UL) |
SCU MODIEN2: EXINT2_EN (Bit 5)
#define SCU_MODIEN2_RIEN2_Msk (0x40UL) |
SCU MODIEN2: RIEN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_RIEN2_Pos (6UL) |
SCU MODIEN2: RIEN2 (Bit 6)
#define SCU_MODIEN2_RIREN2_Msk (0x4UL) |
SCU MODIEN2: RIREN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_RIREN2_Pos (2UL) |
SCU MODIEN2: RIREN2 (Bit 2)
#define SCU_MODIEN2_TIEN2_Msk (0x80UL) |
SCU MODIEN2: TIEN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_TIEN2_Pos (7UL) |
SCU MODIEN2: TIEN2 (Bit 7)
#define SCU_MODIEN2_TIREN2_Msk (0x2UL) |
SCU MODIEN2: TIREN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_TIREN2_Pos (1UL) |
SCU MODIEN2: TIREN2 (Bit 1)
#define SCU_MODIEN3_IE0_Msk (0x1UL) |
SCU MODIEN3: IE0 (Bitfield-Mask: 0x01)
#define SCU_MODIEN3_IE0_Pos (0UL) |
SCU MODIEN3: IE0 (Bit 0)
#define SCU_MODIEN3_MONIE_Msk (0x10UL) |
SCU MODIEN3: MONIE (Bitfield-Mask: 0x01)
#define SCU_MODIEN3_MONIE_Pos (4UL) |
SCU MODIEN3: MONIE (Bit 4)
#define SCU_MODIEN3_MONSTS_Msk (0x20UL) |
SCU MODIEN3: MONSTS (Bitfield-Mask: 0x01)
#define SCU_MODIEN3_MONSTS_Pos (5UL) |
SCU MODIEN3: MONSTS (Bit 5)
#define SCU_MODIEN4_IE1_Msk (0x1UL) |
SCU MODIEN4: IE1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN4_IE1_Pos (0UL) |
SCU MODIEN4: IE1 (Bit 0)
#define SCU_MODPISEL1_GPT12CAPINB_Msk (0x1UL) |
SCU MODPISEL1: GPT12CAPINB (Bitfield-Mask: 0x01)
#define SCU_MODPISEL1_GPT12CAPINB_Pos (0UL) |
SCU MODPISEL1: GPT12CAPINB (Bit 0)
#define SCU_MODPISEL1_T21EXCON_Msk (0x80UL) |
SCU MODPISEL1: T21EXCON (Bitfield-Mask: 0x01)
#define SCU_MODPISEL1_T21EXCON_Pos (7UL) |
SCU MODPISEL1: T21EXCON (Bit 7)
#define SCU_MODPISEL1_T2EXCON_Msk (0x40UL) |
SCU MODPISEL1: T2EXCON (Bitfield-Mask: 0x01)
#define SCU_MODPISEL1_T2EXCON_Pos (6UL) |
SCU MODPISEL1: T2EXCON (Bit 6)
#define SCU_MODPISEL2_T21EXIS_Msk (0xc0UL) |
SCU MODPISEL2: T21EXIS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T21EXIS_Pos (6UL) |
SCU MODPISEL2: T21EXIS (Bit 6)
#define SCU_MODPISEL2_T21IS_Msk (0xcUL) |
SCU MODPISEL2: T21IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T21IS_Pos (2UL) |
SCU MODPISEL2: T21IS (Bit 2)
#define SCU_MODPISEL2_T2EXIS_Msk (0x30UL) |
SCU MODPISEL2: T2EXIS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T2EXIS_Pos (4UL) |
SCU MODPISEL2: T2EXIS (Bit 4)
#define SCU_MODPISEL2_T2IS_Msk (0x3UL) |
SCU MODPISEL2: T2IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T2IS_Pos (0UL) |
SCU MODPISEL2: T2IS (Bit 0)
#define SCU_MODPISEL3_URIOS2_Msk (0x40UL) |
SCU MODPISEL3: URIOS2 (Bitfield-Mask: 0x01)
#define SCU_MODPISEL3_URIOS2_Pos (6UL) |
SCU MODPISEL3: URIOS2 (Bit 6)
#define SCU_MODPISEL_EXINT0IS_Msk (0x3UL) |
SCU MODPISEL: EXINT0IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL_EXINT0IS_Pos (0UL) |
SCU MODPISEL: EXINT0IS (Bit 0)
#define SCU_MODPISEL_EXINT1IS_Msk (0xcUL) |
SCU MODPISEL: EXINT1IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL_EXINT1IS_Pos (2UL) |
SCU MODPISEL: EXINT1IS (Bit 2)
#define SCU_MODPISEL_EXINT2IS_Msk (0x30UL) |
SCU MODPISEL: EXINT2IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL_EXINT2IS_Pos (4UL) |
SCU MODPISEL: EXINT2IS (Bit 4)
#define SCU_MODPISEL_U_TX_CONDIS_Msk (0x80UL) |
SCU MODPISEL: U_TX_CONDIS (Bitfield-Mask: 0x01)
#define SCU_MODPISEL_U_TX_CONDIS_Pos (7UL) |
SCU MODPISEL: U_TX_CONDIS (Bit 7)
#define SCU_MODPISEL_URIOS1_Msk (0x40UL) |
SCU MODPISEL: URIOS1 (Bitfield-Mask: 0x01)
#define SCU_MODPISEL_URIOS1_Pos (6UL) |
SCU MODPISEL: URIOS1 (Bit 6)
#define SCU_MODSUSP1_GPT12_SUSP_Msk (0x10UL) |
SCU MODSUSP1: GPT12_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP1_GPT12_SUSP_Pos (4UL) |
SCU MODSUSP1: GPT12_SUSP (Bit 4)
#define SCU_MODSUSP1_T12SUSP_Msk (0x2UL) |
SCU MODSUSP1: T12SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP1_T12SUSP_Pos (1UL) |
SCU MODSUSP1: T12SUSP (Bit 1)
#define SCU_MODSUSP1_T13SUSP_Msk (0x4UL) |
SCU MODSUSP1: T13SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP1_T13SUSP_Pos (2UL) |
SCU MODSUSP1: T13SUSP (Bit 2)
#define SCU_MODSUSP1_T21_SUSP_Msk (0x40UL) |
SCU MODSUSP1: T21_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP1_T21_SUSP_Pos (6UL) |
SCU MODSUSP1: T21_SUSP (Bit 6)
#define SCU_MODSUSP1_T2_SUSP_Msk (0x8UL) |
SCU MODSUSP1: T2_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP1_T2_SUSP_Pos (3UL) |
SCU MODSUSP1: T2_SUSP (Bit 3)
#define SCU_MODSUSP1_WDTSUSP_Msk (0x1UL) |
SCU MODSUSP1: WDTSUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP1_WDTSUSP_Pos (0UL) |
SCU MODSUSP1: WDTSUSP (Bit 0)
#define SCU_MODSUSP2_ADC1_SUSP_Msk (0x4UL) |
SCU MODSUSP2: ADC1_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP2_ADC1_SUSP_Pos (2UL) |
SCU MODSUSP2: ADC1_SUSP (Bit 2)
#define SCU_MODSUSP2_MU_SUSP_Msk (0x2UL) |
SCU MODSUSP2: MU_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP2_MU_SUSP_Pos (1UL) |
SCU MODSUSP2: MU_SUSP (Bit 1)
#define SCU_MODSUSP2_T3_SUSP_Msk (0x1UL) |
SCU MODSUSP2: T3_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP2_T3_SUSP_Pos (0UL) |
SCU MODSUSP2: T3_SUSP (Bit 0)
#define SCU_NMICLR_NMIECCC_Msk (0x40UL) |
SCU NMICLR: NMIECCC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMIECCC_Pos (6UL) |
SCU NMICLR: NMIECCC (Bit 6)
#define SCU_NMICLR_NMIMAPC_Msk (0x20UL) |
SCU NMICLR: NMIMAPC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMIMAPC_Pos (5UL) |
SCU NMICLR: NMIMAPC (Bit 5)
#define SCU_NMICLR_NMINVMC_Msk (0x4UL) |
SCU NMICLR: NMINVMC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMINVMC_Pos (2UL) |
SCU NMICLR: NMINVMC (Bit 2)
#define SCU_NMICLR_NMIOTC_Msk (0x8UL) |
SCU NMICLR: NMIOTC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMIOTC_Pos (3UL) |
SCU NMICLR: NMIOTC (Bit 3)
#define SCU_NMICLR_NMIOWDC_Msk (0x10UL) |
SCU NMICLR: NMIOWDC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMIOWDC_Pos (4UL) |
SCU NMICLR: NMIOWDC (Bit 4)
#define SCU_NMICLR_NMIPLLC_Msk (0x2UL) |
SCU NMICLR: NMIPLLC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMIPLLC_Pos (1UL) |
SCU NMICLR: NMIPLLC (Bit 1)
#define SCU_NMICLR_NMISUPC_Msk (0x80UL) |
SCU NMICLR: NMISUPC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMISUPC_Pos (7UL) |
SCU NMICLR: NMISUPC (Bit 7)
#define SCU_NMICLR_NMIWDTC_Msk (0x1UL) |
SCU NMICLR: NMIWDTC (Bitfield-Mask: 0x01)
#define SCU_NMICLR_NMIWDTC_Pos (0UL) |
SCU NMICLR: NMIWDTC (Bit 0)
#define SCU_NMICON_NMIECC_Msk (0x40UL) |
SCU NMICON: NMIECC (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIECC_Pos (6UL) |
SCU NMICON: NMIECC (Bit 6)
#define SCU_NMICON_NMIMAP_Msk (0x20UL) |
SCU NMICON: NMIMAP (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIMAP_Pos (5UL) |
SCU NMICON: NMIMAP (Bit 5)
#define SCU_NMICON_NMINVM_Msk (0x4UL) |
SCU NMICON: NMINVM (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMINVM_Pos (2UL) |
SCU NMICON: NMINVM (Bit 2)
#define SCU_NMICON_NMIOT_Msk (0x8UL) |
SCU NMICON: NMIOT (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIOT_Pos (3UL) |
SCU NMICON: NMIOT (Bit 3)
#define SCU_NMICON_NMIOWD_Msk (0x10UL) |
SCU NMICON: NMIOWD (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIOWD_Pos (4UL) |
SCU NMICON: NMIOWD (Bit 4)
#define SCU_NMICON_NMIPLL_Msk (0x2UL) |
SCU NMICON: NMIPLL (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIPLL_Pos (1UL) |
SCU NMICON: NMIPLL (Bit 1)
#define SCU_NMICON_NMISUP_Msk (0x80UL) |
SCU NMICON: NMISUP (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMISUP_Pos (7UL) |
SCU NMICON: NMISUP (Bit 7)
#define SCU_NMICON_NMIWDT_Msk (0x1UL) |
SCU NMICON: NMIWDT (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIWDT_Pos (0UL) |
SCU NMICON: NMIWDT (Bit 0)
#define SCU_NMISR_FNMIECC_Msk (0x40UL) |
SCU NMISR: FNMIECC (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIECC_Pos (6UL) |
SCU NMISR: FNMIECC (Bit 6)
#define SCU_NMISR_FNMIMAP_Msk (0x20UL) |
SCU NMISR: FNMIMAP (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIMAP_Pos (5UL) |
SCU NMISR: FNMIMAP (Bit 5)
#define SCU_NMISR_FNMINVM_Msk (0x4UL) |
SCU NMISR: FNMINVM (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMINVM_Pos (2UL) |
SCU NMISR: FNMINVM (Bit 2)
#define SCU_NMISR_FNMIOT_Msk (0x8UL) |
SCU NMISR: FNMIOT (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIOT_Pos (3UL) |
SCU NMISR: FNMIOT (Bit 3)
#define SCU_NMISR_FNMIOWD_Msk (0x10UL) |
SCU NMISR: FNMIOWD (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIOWD_Pos (4UL) |
SCU NMISR: FNMIOWD (Bit 4)
#define SCU_NMISR_FNMIPLL_Msk (0x2UL) |
SCU NMISR: FNMIPLL (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIPLL_Pos (1UL) |
SCU NMISR: FNMIPLL (Bit 1)
#define SCU_NMISR_FNMISUP_Msk (0x80UL) |
SCU NMISR: FNMISUP (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMISUP_Pos (7UL) |
SCU NMISR: FNMISUP (Bit 7)
#define SCU_NMISR_FNMIWDT_Msk (0x1UL) |
SCU NMISR: FNMIWDT (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIWDT_Pos (0UL) |
SCU NMISR: FNMIWDT (Bit 0)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Msk (0x1UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_0 (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Pos (0UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_0 (Bit 0)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Msk (0x2UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_1 (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Pos (1UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_1 (Bit 1)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Msk (0x4UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_2 (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Pos (2UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_2 (Bit 2)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Msk (0x8UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_3 (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Pos (3UL) |
SCU NVM_PROT_STS: NVMPROTSTSL_3 (Bit 3)
#define SCU_OSC_CON_OSC2L_Msk (0x8UL) |
SCU OSC_CON: OSC2L (Bitfield-Mask: 0x01)
#define SCU_OSC_CON_OSC2L_Pos (3UL) |
SCU OSC_CON: OSC2L (Bit 3)
#define SCU_OSC_CON_OSCSS_Msk (0x3UL) |
SCU OSC_CON: OSCSS (Bitfield-Mask: 0x03)
#define SCU_OSC_CON_OSCSS_Pos (0UL) |
SCU OSC_CON: OSCSS (Bit 0)
#define SCU_OSC_CON_OSCTRIM_8_Msk (0x80UL) |
SCU OSC_CON: OSCTRIM_8 (Bitfield-Mask: 0x01)
#define SCU_OSC_CON_OSCTRIM_8_Pos (7UL) |
SCU OSC_CON: OSCTRIM_8 (Bit 7)
#define SCU_OSC_CON_OSCWDTRST_Msk (0x4UL) |
SCU OSC_CON: OSCWDTRST (Bitfield-Mask: 0x01)
#define SCU_OSC_CON_OSCWDTRST_Pos (2UL) |
SCU OSC_CON: OSCWDTRST (Bit 2)
#define SCU_OSC_CON_XPD_Msk (0x10UL) |
SCU OSC_CON: XPD (Bitfield-Mask: 0x01)
#define SCU_OSC_CON_XPD_Pos (4UL) |
SCU OSC_CON: XPD (Bit 4)
#define SCU_P0_POCON0_PDM0_Msk (0x7UL) |
SCU P0_POCON0: PDM0 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_PDM0_Pos (0UL) |
SCU P0_POCON0: PDM0 (Bit 0)
#define SCU_P0_POCON0_PDM1_Msk (0x70UL) |
SCU P0_POCON0: PDM1 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_PDM1_Pos (4UL) |
SCU P0_POCON0: PDM1 (Bit 4)
#define SCU_P0_POCON1_PDM2_Msk (0x7UL) |
SCU P0_POCON1: PDM2 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON1_PDM2_Pos (0UL) |
SCU P0_POCON1: PDM2 (Bit 0)
#define SCU_P0_POCON1_PDM3_Msk (0x70UL) |
SCU P0_POCON1: PDM3 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON1_PDM3_Pos (4UL) |
SCU P0_POCON1: PDM3 (Bit 4)
#define SCU_P0_POCON2_PDM4_Msk (0x7UL) |
SCU P0_POCON2: PDM4 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON2_PDM4_Pos (0UL) |
SCU P0_POCON2: PDM4 (Bit 0)
#define SCU_P1_POCON0_PDM0_Msk (0x7UL) |
SCU P1_POCON0: PDM0 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON0_PDM0_Pos (0UL) |
SCU P1_POCON0: PDM0 (Bit 0)
#define SCU_P1_POCON0_PDM1_Msk (0x70UL) |
SCU P1_POCON0: PDM1 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON0_PDM1_Pos (4UL) |
SCU P1_POCON0: PDM1 (Bit 4)
#define SCU_P1_POCON1_PDM2_Msk (0x7UL) |
SCU P1_POCON1: PDM2 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON1_PDM2_Pos (0UL) |
SCU P1_POCON1: PDM2 (Bit 0)
#define SCU_P1_POCON1_PDM3_Msk (0x70UL) |
SCU P1_POCON1: PDM3 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON1_PDM3_Pos (4UL) |
SCU P1_POCON1: PDM3 (Bit 4)
#define SCU_P1_POCON2_PDM4_Msk (0x7UL) |
SCU P1_POCON2: PDM4 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON2_PDM4_Pos (0UL) |
SCU P1_POCON2: PDM4 (Bit 0)
#define SCU_PASSWD_MODE_Msk (0x3UL) |
SCU PASSWD: MODE (Bitfield-Mask: 0x03)
#define SCU_PASSWD_MODE_Pos (0UL) |
SCU PASSWD: MODE (Bit 0)
#define SCU_PASSWD_PASS_Msk (0xf8UL) |
SCU PASSWD: PASS (Bitfield-Mask: 0x1f)
#define SCU_PASSWD_PASS_Pos (3UL) |
SCU PASSWD: PASS (Bit 3)
#define SCU_PASSWD_PROTECT_S_Msk (0x4UL) |
SCU PASSWD: PROTECT_S (Bitfield-Mask: 0x01)
#define SCU_PASSWD_PROTECT_S_Pos (2UL) |
SCU PASSWD: PROTECT_S (Bit 2)
#define SCU_PLL_CON_LOCK_Msk (0x1UL) |
SCU PLL_CON: LOCK (Bitfield-Mask: 0x01)
#define SCU_PLL_CON_LOCK_Pos (0UL) |
SCU PLL_CON: LOCK (Bit 0)
#define SCU_PLL_CON_NDIV_Msk (0xf0UL) |
SCU PLL_CON: NDIV (Bitfield-Mask: 0x0f)
#define SCU_PLL_CON_NDIV_Pos (4UL) |
SCU PLL_CON: NDIV (Bit 4)
#define SCU_PLL_CON_OSCDISC_Msk (0x4UL) |
SCU PLL_CON: OSCDISC (Bitfield-Mask: 0x01)
#define SCU_PLL_CON_OSCDISC_Pos (2UL) |
SCU PLL_CON: OSCDISC (Bit 2)
#define SCU_PLL_CON_RESLD_Msk (0x2UL) |
SCU PLL_CON: RESLD (Bitfield-Mask: 0x01)
#define SCU_PLL_CON_RESLD_Pos (1UL) |
SCU PLL_CON: RESLD (Bit 1)
#define SCU_PLL_CON_VCOBYP_Msk (0x8UL) |
SCU PLL_CON: VCOBYP (Bitfield-Mask: 0x01)
#define SCU_PLL_CON_VCOBYP_Pos (3UL) |
SCU PLL_CON: VCOBYP (Bit 3)
#define SCU_PMCON0_PD_Msk (0x4UL) |
SCU PMCON0: PD (Bitfield-Mask: 0x01)
#define SCU_PMCON0_PD_Pos (2UL) |
SCU PMCON0: PD (Bit 2)
#define SCU_PMCON0_SD_Msk (0x8UL) |
SCU PMCON0: SD (Bitfield-Mask: 0x01)
#define SCU_PMCON0_SD_Pos (3UL) |
SCU PMCON0: SD (Bit 3)
#define SCU_PMCON0_SL_Msk (0x2UL) |
SCU PMCON0: SL (Bitfield-Mask: 0x01)
#define SCU_PMCON0_SL_Pos (1UL) |
SCU PMCON0: SL (Bit 1)
#define SCU_PMCON0_XTAL_ON_Msk (0x1UL) |
SCU PMCON0: XTAL_ON (Bitfield-Mask: 0x01)
#define SCU_PMCON0_XTAL_ON_Pos (0UL) |
SCU PMCON0: XTAL_ON (Bit 0)
#define SCU_PMCON1_ADC1_DIS_Msk (0x1UL) |
SCU PMCON1: ADC1_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON1_ADC1_DIS_Pos (0UL) |
SCU PMCON1: ADC1_DIS (Bit 0)
#define SCU_PMCON1_CCU6_DIS_Msk (0x4UL) |
SCU PMCON1: CCU6_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON1_CCU6_DIS_Pos (2UL) |
SCU PMCON1: CCU6_DIS (Bit 2)
#define SCU_PMCON1_GPT12_DIS_Msk (0x10UL) |
SCU PMCON1: GPT12_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON1_GPT12_DIS_Pos (4UL) |
SCU PMCON1: GPT12_DIS (Bit 4)
#define SCU_PMCON1_SSC1_DIS_Msk (0x2UL) |
SCU PMCON1: SSC1_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON1_SSC1_DIS_Pos (1UL) |
SCU PMCON1: SSC1_DIS (Bit 1)
#define SCU_PMCON1_T2_DIS_Msk (0x8UL) |
SCU PMCON1: T2_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON1_T2_DIS_Pos (3UL) |
SCU PMCON1: T2_DIS (Bit 3)
#define SCU_PMCON2_SSC2_DIS_Msk (0x2UL) |
SCU PMCON2: SSC2_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON2_SSC2_DIS_Pos (1UL) |
SCU PMCON2: SSC2_DIS (Bit 1)
#define SCU_PMCON2_T21_DIS_Msk (0x8UL) |
SCU PMCON2: T21_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON2_T21_DIS_Pos (3UL) |
SCU PMCON2: T21_DIS (Bit 3)
#define SCU_PMCON2_T3_DIS_Msk (0x20UL) |
SCU PMCON2: T3_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON2_T3_DIS_Pos (5UL) |
SCU PMCON2: T3_DIS (Bit 5)
#define SCU_RSTCON_LOCKUP_EN_Msk (0x80UL) |
SCU RSTCON: LOCKUP_EN (Bitfield-Mask: 0x01)
#define SCU_RSTCON_LOCKUP_EN_Pos (7UL) |
SCU RSTCON: LOCKUP_EN (Bit 7)
#define SCU_RSTCON_LOCKUP_Msk (0x1UL) |
SCU RSTCON: LOCKUP (Bitfield-Mask: 0x01)
#define SCU_RSTCON_LOCKUP_Pos (0UL) |
SCU RSTCON: LOCKUP (Bit 0)
#define SCU_SYS_STRTUP_STS_INIT_FAIL_Msk (0x1UL) |
SCU SYS_STRTUP_STS: INIT_FAIL (Bitfield-Mask: 0x01)
#define SCU_SYS_STRTUP_STS_INIT_FAIL_Pos (0UL) |
SCU SYS_STRTUP_STS: INIT_FAIL (Bit 0)
#define SCU_SYS_STRTUP_STS_MRAMINITSTS_Msk (0x2UL) |
SCU SYS_STRTUP_STS: MRAMINITSTS (Bitfield-Mask: 0x01)
#define SCU_SYS_STRTUP_STS_MRAMINITSTS_Pos (1UL) |
SCU SYS_STRTUP_STS: MRAMINITSTS (Bit 1)
#define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Msk (0x4UL) |
SCU SYS_STRTUP_STS: PG100TP_CHKS_ERR (Bitfield-Mask: 0x01)
#define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Pos (2UL) |
SCU SYS_STRTUP_STS: PG100TP_CHKS_ERR (Bit 2)
#define SCU_SYSCON0_NVMCLKFAC_Msk (0x30UL) |
SCU SYSCON0: NVMCLKFAC (Bitfield-Mask: 0x03)
#define SCU_SYSCON0_NVMCLKFAC_Pos (4UL) |
SCU SYSCON0: NVMCLKFAC (Bit 4)
#define SCU_SYSCON0_SYSCLKSEL_Msk (0xc0UL) |
SCU SYSCON0: SYSCLKSEL (Bitfield-Mask: 0x03)
#define SCU_SYSCON0_SYSCLKSEL_Pos (6UL) |
SCU SYSCON0: SYSCLKSEL (Bit 6)
#define SCU_TCCR_TCC_Msk (0x3UL) |
SCU TCCR: TCC (Bitfield-Mask: 0x03)
#define SCU_TCCR_TCC_Pos (0UL) |
SCU TCCR: TCC (Bit 0)
#define SCU_WDTCON_WDTEN_Msk (0x4UL) |
SCU WDTCON: WDTEN (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTEN_Pos (2UL) |
SCU WDTCON: WDTEN (Bit 2)
#define SCU_WDTCON_WDTIN_Msk (0x1UL) |
SCU WDTCON: WDTIN (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTIN_Pos (0UL) |
SCU WDTCON: WDTIN (Bit 0)
#define SCU_WDTCON_WDTPR_Msk (0x10UL) |
SCU WDTCON: WDTPR (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTPR_Pos (4UL) |
SCU WDTCON: WDTPR (Bit 4)
#define SCU_WDTCON_WDTRS_Msk (0x2UL) |
SCU WDTCON: WDTRS (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTRS_Pos (1UL) |
SCU WDTCON: WDTRS (Bit 1)
#define SCU_WDTCON_WINBEN_Msk (0x20UL) |
SCU WDTCON: WINBEN (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WINBEN_Pos (5UL) |
SCU WDTCON: WINBEN (Bit 5)
#define SCU_WDTH_WDT_Msk (0xffUL) |
SCU WDTH: WDT (Bitfield-Mask: 0xff)
#define SCU_WDTH_WDT_Pos (0UL) |
SCU WDTH: WDT (Bit 0)
#define SCU_WDTL_WDT_Msk (0xffUL) |
SCU WDTL: WDT (Bitfield-Mask: 0xff)
#define SCU_WDTL_WDT_Pos (0UL) |
SCU WDTL: WDT (Bit 0)
#define SCU_WDTREL_WDTREL_Msk (0xffUL) |
SCU WDTREL: WDTREL (Bitfield-Mask: 0xff)
#define SCU_WDTREL_WDTREL_Pos (0UL) |
SCU WDTREL: WDTREL (Bit 0)
#define SCU_WDTWINB_WDTWINB_Msk (0xffUL) |
SCU WDTWINB: WDTWINB (Bitfield-Mask: 0xff)
#define SCU_WDTWINB_WDTWINB_Pos (0UL) |
SCU WDTWINB: WDTWINB (Bit 0)
#define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk (0x1UL) |
SCUPM AMCLK_CTRL: CLKWDT_PD_N (Bitfield-Mask: 0x01)
#define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos (0UL) |
SCUPM AMCLK_CTRL: CLKWDT_PD_N (Bit 0)
#define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Msk (0x3fUL) |
SCUPM AMCLK_FREQ_STS: AMCLK1_FREQ (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Pos (0UL) |
SCUPM AMCLK_FREQ_STS: AMCLK1_FREQ (Bit 0)
#define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Msk (0x3f00UL) |
SCUPM AMCLK_FREQ_STS: AMCLK2_FREQ (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Pos (8UL) |
SCUPM AMCLK_FREQ_STS: AMCLK2_FREQ (Bit 8)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk (0xc000UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos (14UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_HYS (Bit 14)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk (0x3f00UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos (8UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_TH (Bit 8)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk (0xc0UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos (6UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_HYS (Bit 6)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk (0x3fUL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos (0UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_TH (Bit 0)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk (0xc0000000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos (30UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_HYS (Bit 30)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk (0x3f000000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos (24UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_TH (Bit 24)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk (0xc00000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos (22UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_HYS (Bit 22)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk (0x3f0000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos (16UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_TH (Bit 16)
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk (0x4UL) |
SCUPM BDRV_IRQ_CTRL: HS1_DS_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos (2UL) |
SCUPM BDRV_IRQ_CTRL: HS1_DS_IE (Bit 2)
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk (0x1000UL) |
SCUPM BDRV_IRQ_CTRL: HS1_OC_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos (12UL) |
SCUPM BDRV_IRQ_CTRL: HS1_OC_IE (Bit 12)
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk (0x8UL) |
SCUPM BDRV_IRQ_CTRL: HS2_DS_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos (3UL) |
SCUPM BDRV_IRQ_CTRL: HS2_DS_IE (Bit 3)
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk (0x2000UL) |
SCUPM BDRV_IRQ_CTRL: HS2_OC_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos (13UL) |
SCUPM BDRV_IRQ_CTRL: HS2_OC_IE (Bit 13)
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk (0x1UL) |
SCUPM BDRV_IRQ_CTRL: LS1_DS_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos (0UL) |
SCUPM BDRV_IRQ_CTRL: LS1_DS_IE (Bit 0)
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk (0x400UL) |
SCUPM BDRV_IRQ_CTRL: LS1_OC_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos (10UL) |
SCUPM BDRV_IRQ_CTRL: LS1_OC_IE (Bit 10)
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk (0x2UL) |
SCUPM BDRV_IRQ_CTRL: LS2_DS_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos (1UL) |
SCUPM BDRV_IRQ_CTRL: LS2_DS_IE (Bit 1)
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk (0x800UL) |
SCUPM BDRV_IRQ_CTRL: LS2_OC_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos (11UL) |
SCUPM BDRV_IRQ_CTRL: LS2_OC_IE (Bit 11)
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Msk (0x20000UL) |
SCUPM BDRV_IRQ_CTRL: VCP_LOWTH1_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Pos (17UL) |
SCUPM BDRV_IRQ_CTRL: VCP_LOWTH1_IE (Bit 17)
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk (0x10000UL) |
SCUPM BDRV_IRQ_CTRL: VCP_LOWTH2_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos (16UL) |
SCUPM BDRV_IRQ_CTRL: VCP_LOWTH2_IE (Bit 16)
#define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Msk (0x40000UL) |
SCUPM BDRV_IRQ_CTRL: VCP_UPTH_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Pos (18UL) |
SCUPM BDRV_IRQ_CTRL: VCP_UPTH_IE (Bit 18)
#define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Msk (0x80000UL) |
SCUPM BDRV_IRQ_CTRL: VSD_LOWTH_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Pos (19UL) |
SCUPM BDRV_IRQ_CTRL: VSD_LOWTH_IE (Bit 19)
#define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Msk (0x100000UL) |
SCUPM BDRV_IRQ_CTRL: VSD_UPTH_IE (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Pos (20UL) |
SCUPM BDRV_IRQ_CTRL: VSD_UPTH_IE (Bit 20)
#define SCUPM_BDRV_IS_HS1_DS_IS_Msk (0x4UL) |
SCUPM BDRV_IS: HS1_DS_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_HS1_DS_IS_Pos (2UL) |
SCUPM BDRV_IS: HS1_DS_IS (Bit 2)
#define SCUPM_BDRV_IS_HS1_OC_IS_Msk (0x1000UL) |
SCUPM BDRV_IS: HS1_OC_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_HS1_OC_IS_Pos (12UL) |
SCUPM BDRV_IS: HS1_OC_IS (Bit 12)
#define SCUPM_BDRV_IS_HS2_DS_IS_Msk (0x8UL) |
SCUPM BDRV_IS: HS2_DS_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_HS2_DS_IS_Pos (3UL) |
SCUPM BDRV_IS: HS2_DS_IS (Bit 3)
#define SCUPM_BDRV_IS_HS2_OC_IS_Msk (0x2000UL) |
SCUPM BDRV_IS: HS2_OC_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_HS2_OC_IS_Pos (13UL) |
SCUPM BDRV_IS: HS2_OC_IS (Bit 13)
#define SCUPM_BDRV_IS_LS1_DS_IS_Msk (0x1UL) |
SCUPM BDRV_IS: LS1_DS_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_LS1_DS_IS_Pos (0UL) |
SCUPM BDRV_IS: LS1_DS_IS (Bit 0)
#define SCUPM_BDRV_IS_LS1_OC_IS_Msk (0x400UL) |
SCUPM BDRV_IS: LS1_OC_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_LS1_OC_IS_Pos (10UL) |
SCUPM BDRV_IS: LS1_OC_IS (Bit 10)
#define SCUPM_BDRV_IS_LS2_DS_IS_Msk (0x2UL) |
SCUPM BDRV_IS: LS2_DS_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_LS2_DS_IS_Pos (1UL) |
SCUPM BDRV_IS: LS2_DS_IS (Bit 1)
#define SCUPM_BDRV_IS_LS2_OC_IS_Msk (0x800UL) |
SCUPM BDRV_IS: LS2_OC_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_LS2_OC_IS_Pos (11UL) |
SCUPM BDRV_IS: LS2_OC_IS (Bit 11)
#define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Msk (0x20000UL) |
SCUPM BDRV_IS: VCP_LOWTH1_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Pos (17UL) |
SCUPM BDRV_IS: VCP_LOWTH1_IS (Bit 17)
#define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Msk (0x2000000UL) |
SCUPM BDRV_IS: VCP_LOWTH1_STS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Pos (25UL) |
SCUPM BDRV_IS: VCP_LOWTH1_STS (Bit 25)
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk (0x10000UL) |
SCUPM BDRV_IS: VCP_LOWTH2_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos (16UL) |
SCUPM BDRV_IS: VCP_LOWTH2_IS (Bit 16)
#define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Msk (0x1000000UL) |
SCUPM BDRV_IS: VCP_LOWTH2_STS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Pos (24UL) |
SCUPM BDRV_IS: VCP_LOWTH2_STS (Bit 24)
#define SCUPM_BDRV_IS_VCP_UPTH_IS_Msk (0x40000UL) |
SCUPM BDRV_IS: VCP_UPTH_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VCP_UPTH_IS_Pos (18UL) |
SCUPM BDRV_IS: VCP_UPTH_IS (Bit 18)
#define SCUPM_BDRV_IS_VCP_UPTH_STS_Msk (0x4000000UL) |
SCUPM BDRV_IS: VCP_UPTH_STS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VCP_UPTH_STS_Pos (26UL) |
SCUPM BDRV_IS: VCP_UPTH_STS (Bit 26)
#define SCUPM_BDRV_IS_VSD_LOWTH_IS_Msk (0x80000UL) |
SCUPM BDRV_IS: VSD_LOWTH_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VSD_LOWTH_IS_Pos (19UL) |
SCUPM BDRV_IS: VSD_LOWTH_IS (Bit 19)
#define SCUPM_BDRV_IS_VSD_LOWTH_STS_Msk (0x8000000UL) |
SCUPM BDRV_IS: VSD_LOWTH_STS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VSD_LOWTH_STS_Pos (27UL) |
SCUPM BDRV_IS: VSD_LOWTH_STS (Bit 27)
#define SCUPM_BDRV_IS_VSD_UPTH_IS_Msk (0x100000UL) |
SCUPM BDRV_IS: VSD_UPTH_IS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VSD_UPTH_IS_Pos (20UL) |
SCUPM BDRV_IS: VSD_UPTH_IS (Bit 20)
#define SCUPM_BDRV_IS_VSD_UPTH_STS_Msk (0x10000000UL) |
SCUPM BDRV_IS: VSD_UPTH_STS (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_IS_VSD_UPTH_STS_Pos (28UL) |
SCUPM BDRV_IS: VSD_UPTH_STS (Bit 28)
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk (0x4UL) |
SCUPM BDRV_ISCLR: HS1_DS_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos (2UL) |
SCUPM BDRV_ISCLR: HS1_DS_ICLR (Bit 2)
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk (0x1000UL) |
SCUPM BDRV_ISCLR: HS1_OC_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos (12UL) |
SCUPM BDRV_ISCLR: HS1_OC_ICLR (Bit 12)
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk (0x8UL) |
SCUPM BDRV_ISCLR: HS2_DS_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos (3UL) |
SCUPM BDRV_ISCLR: HS2_DS_ICLR (Bit 3)
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk (0x2000UL) |
SCUPM BDRV_ISCLR: HS2_OC_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos (13UL) |
SCUPM BDRV_ISCLR: HS2_OC_ICLR (Bit 13)
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk (0x1UL) |
SCUPM BDRV_ISCLR: LS1_DS_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos (0UL) |
SCUPM BDRV_ISCLR: LS1_DS_ICLR (Bit 0)
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk (0x400UL) |
SCUPM BDRV_ISCLR: LS1_OC_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos (10UL) |
SCUPM BDRV_ISCLR: LS1_OC_ICLR (Bit 10)
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk (0x2UL) |
SCUPM BDRV_ISCLR: LS2_DS_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos (1UL) |
SCUPM BDRV_ISCLR: LS2_DS_ICLR (Bit 1)
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk (0x800UL) |
SCUPM BDRV_ISCLR: LS2_OC_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos (11UL) |
SCUPM BDRV_ISCLR: LS2_OC_ICLR (Bit 11)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Msk (0x20000UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH1_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Pos (17UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH1_ICLR (Bit 17)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Msk (0x2000000UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH1_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Pos (25UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH1_SCLR (Bit 25)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk (0x10000UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH2_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos (16UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH2_ICLR (Bit 16)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Msk (0x1000000UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH2_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Pos (24UL) |
SCUPM BDRV_ISCLR: VCP_LOWTH2_SCLR (Bit 24)
#define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Msk (0x40000UL) |
SCUPM BDRV_ISCLR: VCP_UPTH_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Pos (18UL) |
SCUPM BDRV_ISCLR: VCP_UPTH_ICLR (Bit 18)
#define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Msk (0x4000000UL) |
SCUPM BDRV_ISCLR: VCP_UPTH_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Pos (26UL) |
SCUPM BDRV_ISCLR: VCP_UPTH_SCLR (Bit 26)
#define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Msk (0x80000UL) |
SCUPM BDRV_ISCLR: VSD_LOWTH_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Pos (19UL) |
SCUPM BDRV_ISCLR: VSD_LOWTH_ICLR (Bit 19)
#define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Msk (0x8000000UL) |
SCUPM BDRV_ISCLR: VSD_LOWTH_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Pos (27UL) |
SCUPM BDRV_ISCLR: VSD_LOWTH_SCLR (Bit 27)
#define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Msk (0x100000UL) |
SCUPM BDRV_ISCLR: VSD_UPTH_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Pos (20UL) |
SCUPM BDRV_ISCLR: VSD_UPTH_ICLR (Bit 20)
#define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Msk (0x10000000UL) |
SCUPM BDRV_ISCLR: VSD_UPTH_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Pos (28UL) |
SCUPM BDRV_ISCLR: VSD_UPTH_SCLR (Bit 28)
#define SCUPM_BFSTS_CLR_DBFSTSCLR_Msk (0x1UL) |
SCUPM BFSTS_CLR: DBFSTSCLR (Bitfield-Mask: 0x01)
#define SCUPM_BFSTS_CLR_DBFSTSCLR_Pos (0UL) |
SCUPM BFSTS_CLR: DBFSTSCLR (Bit 0)
#define SCUPM_BFSTS_CLR_SBFSTSCLR_Msk (0x2UL) |
SCUPM BFSTS_CLR: SBFSTSCLR (Bitfield-Mask: 0x01)
#define SCUPM_BFSTS_CLR_SBFSTSCLR_Pos (1UL) |
SCUPM BFSTS_CLR: SBFSTSCLR (Bit 1)
#define SCUPM_BFSTS_DBFSTS_Msk (0x1UL) |
SCUPM BFSTS: DBFSTS (Bitfield-Mask: 0x01)
#define SCUPM_BFSTS_DBFSTS_Pos (0UL) |
SCUPM BFSTS: DBFSTS (Bit 0)
#define SCUPM_BFSTS_SBFSTS_Msk (0x2UL) |
SCUPM BFSTS: SBFSTS (Bitfield-Mask: 0x01)
#define SCUPM_BFSTS_SBFSTS_Pos (1UL) |
SCUPM BFSTS: SBFSTS (Bit 1)
#define SCUPM_DBFA_DBFA_Msk (0xffffffffUL) |
SCUPM DBFA: DBFA (Bitfield-Mask: 0xffffffff)
#define SCUPM_DBFA_DBFA_Pos (0UL) |
SCUPM DBFA: DBFA (Bit 0)
#define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk (0x2000000UL) |
SCUPM PCU_CTRL_STS: CLKLOSS_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos (25UL) |
SCUPM PCU_CTRL_STS: CLKLOSS_SD_DIS (Bit 25)
#define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk (0x4000000UL) |
SCUPM PCU_CTRL_STS: CLKWDT_RES_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos (26UL) |
SCUPM PCU_CTRL_STS: CLKWDT_RES_SD_DIS (Bit 26)
#define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk (0x2UL) |
SCUPM PCU_CTRL_STS: CLKWDT_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos (1UL) |
SCUPM PCU_CTRL_STS: CLKWDT_SD_DIS (Bit 1)
#define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk (0x80UL) |
SCUPM PCU_CTRL_STS: FAIL_PS_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos (7UL) |
SCUPM PCU_CTRL_STS: FAIL_PS_DIS (Bit 7)
#define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk (0x100UL) |
SCUPM PCU_CTRL_STS: LIN_VS_UV_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos (8UL) |
SCUPM PCU_CTRL_STS: LIN_VS_UV_SD_DIS (Bit 8)
#define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Msk (0x1000000UL) |
SCUPM PCU_CTRL_STS: SYS_OT_PS_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Pos (24UL) |
SCUPM PCU_CTRL_STS: SYS_OT_PS_DIS (Bit 24)
#define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Msk (0x4000UL) |
SCUPM PCU_CTRL_STS: SYS_VSD_OV_SLM_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Pos (14UL) |
SCUPM PCU_CTRL_STS: SYS_VSD_OV_SLM_DIS (Bit 14)
#define SCUPM_SBFA_SBFA_Msk (0xffffffffUL) |
SCUPM SBFA: SBFA (Bitfield-Mask: 0xffffffff)
#define SCUPM_SBFA_SBFA_Pos (0UL) |
SCUPM SBFA: SBFA (Bit 0)
#define SCUPM_STCALIB_STCALIB_Msk (0x3ffffffUL) |
SCUPM STCALIB: STCALIB (Bitfield-Mask: 0x3ffffff)
#define SCUPM_STCALIB_STCALIB_Pos (0UL) |
SCUPM STCALIB: STCALIB (Bit 0)
#define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Msk (0x8000UL) |
SCUPM SYS_IRQ_CTRL: ADC2_ESM_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Pos (15UL) |
SCUPM SYS_IRQ_CTRL: ADC2_ESM_IE (Bit 15)
#define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Msk (0x400000UL) |
SCUPM SYS_IRQ_CTRL: ADC3_EOC_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Pos (22UL) |
SCUPM SYS_IRQ_CTRL: ADC3_EOC_IE (Bit 22)
#define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Msk (0x800000UL) |
SCUPM SYS_IRQ_CTRL: ADC4_EOC_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Pos (23UL) |
SCUPM SYS_IRQ_CTRL: ADC4_EOC_IE (Bit 23)
#define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Msk (0x1UL) |
SCUPM SYS_IRQ_CTRL: LIN_OC_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Pos (0UL) |
SCUPM SYS_IRQ_CTRL: LIN_OC_IE (Bit 0)
#define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Msk (0x2UL) |
SCUPM SYS_IRQ_CTRL: LIN_OT_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Pos (1UL) |
SCUPM SYS_IRQ_CTRL: LIN_OT_IE (Bit 1)
#define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Msk (0x4UL) |
SCUPM SYS_IRQ_CTRL: LIN_TMOUT_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Pos (2UL) |
SCUPM SYS_IRQ_CTRL: LIN_TMOUT_IE (Bit 2)
#define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Msk (0x80UL) |
SCUPM SYS_IRQ_CTRL: PMU_OT_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Pos (7UL) |
SCUPM SYS_IRQ_CTRL: PMU_OT_IE (Bit 7)
#define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Msk (0x40UL) |
SCUPM SYS_IRQ_CTRL: PMU_OTWARN_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Pos (6UL) |
SCUPM SYS_IRQ_CTRL: PMU_OTWARN_IE (Bit 6)
#define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Msk (0x400UL) |
SCUPM SYS_IRQ_CTRL: REFBG_LOTHWARN_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Pos (10UL) |
SCUPM SYS_IRQ_CTRL: REFBG_LOTHWARN_IE (Bit 10)
#define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Msk (0x800UL) |
SCUPM SYS_IRQ_CTRL: REFBG_UPTHWARN_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Pos (11UL) |
SCUPM SYS_IRQ_CTRL: REFBG_UPTHWARN_IE (Bit 11)
#define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Msk (0x200UL) |
SCUPM SYS_IRQ_CTRL: SYS_OT_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Pos (9UL) |
SCUPM SYS_IRQ_CTRL: SYS_OT_IE (Bit 9)
#define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Msk (0x100UL) |
SCUPM SYS_IRQ_CTRL: SYS_OTWARN_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Pos (8UL) |
SCUPM SYS_IRQ_CTRL: SYS_OTWARN_IE (Bit 8)
#define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Msk (0x1000UL) |
SCUPM SYS_IRQ_CTRL: VREF5V_LOWTH_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Pos (12UL) |
SCUPM SYS_IRQ_CTRL: VREF5V_LOWTH_IE (Bit 12)
#define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Msk (0x4000UL) |
SCUPM SYS_IRQ_CTRL: VREF5V_OVL_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Pos (14UL) |
SCUPM SYS_IRQ_CTRL: VREF5V_OVL_IE (Bit 14)
#define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Msk (0x2000UL) |
SCUPM SYS_IRQ_CTRL: VREF5V_UPTH_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Pos (13UL) |
SCUPM SYS_IRQ_CTRL: VREF5V_UPTH_IE (Bit 13)
#define SCUPM_SYS_IS_ADC2_ESM_IS_Msk (0x8000UL) |
SCUPM SYS_IS: ADC2_ESM_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_ADC2_ESM_IS_Pos (15UL) |
SCUPM SYS_IS: ADC2_ESM_IS (Bit 15)
#define SCUPM_SYS_IS_ADC3_EOC_IS_Msk (0x400000UL) |
SCUPM SYS_IS: ADC3_EOC_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_ADC3_EOC_IS_Pos (22UL) |
SCUPM SYS_IS: ADC3_EOC_IS (Bit 22)
#define SCUPM_SYS_IS_ADC4_EOC_IS_Msk (0x800000UL) |
SCUPM SYS_IS: ADC4_EOC_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_ADC4_EOC_IS_Pos (23UL) |
SCUPM SYS_IS: ADC4_EOC_IS (Bit 23)
#define SCUPM_SYS_IS_LIN_OC_IS_Msk (0x1UL) |
SCUPM SYS_IS: LIN_OC_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_LIN_OC_IS_Pos (0UL) |
SCUPM SYS_IS: LIN_OC_IS (Bit 0)
#define SCUPM_SYS_IS_LIN_OT_IS_Msk (0x2UL) |
SCUPM SYS_IS: LIN_OT_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_LIN_OT_IS_Pos (1UL) |
SCUPM SYS_IS: LIN_OT_IS (Bit 1)
#define SCUPM_SYS_IS_LIN_TMOUT_IS_Msk (0x4UL) |
SCUPM SYS_IS: LIN_TMOUT_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_LIN_TMOUT_IS_Pos (2UL) |
SCUPM SYS_IS: LIN_TMOUT_IS (Bit 2)
#define SCUPM_SYS_IS_PMU_OT_IS_Msk (0x80UL) |
SCUPM SYS_IS: PMU_OT_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_PMU_OT_IS_Pos (7UL) |
SCUPM SYS_IS: PMU_OT_IS (Bit 7)
#define SCUPM_SYS_IS_PMU_OTWARN_IS_Msk (0x40UL) |
SCUPM SYS_IS: PMU_OTWARN_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_PMU_OTWARN_IS_Pos (6UL) |
SCUPM SYS_IS: PMU_OTWARN_IS (Bit 6)
#define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Msk (0x400UL) |
SCUPM SYS_IS: REFBG_LOTHWARN_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Pos (10UL) |
SCUPM SYS_IS: REFBG_LOTHWARN_IS (Bit 10)
#define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Msk (0x800UL) |
SCUPM SYS_IS: REFBG_UPTHWARN_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Pos (11UL) |
SCUPM SYS_IS: REFBG_UPTHWARN_IS (Bit 11)
#define SCUPM_SYS_IS_SYS_OT_IS_Msk (0x200UL) |
SCUPM SYS_IS: SYS_OT_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_OT_IS_Pos (9UL) |
SCUPM SYS_IS: SYS_OT_IS (Bit 9)
#define SCUPM_SYS_IS_SYS_OTWARN_IS_Msk (0x100UL) |
SCUPM SYS_IS: SYS_OTWARN_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_OTWARN_IS_Pos (8UL) |
SCUPM SYS_IS: SYS_OTWARN_IS (Bit 8)
#define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Msk (0x1000UL) |
SCUPM SYS_IS: VREF5V_LOWTH_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Pos (12UL) |
SCUPM SYS_IS: VREF5V_LOWTH_IS (Bit 12)
#define SCUPM_SYS_IS_VREF5V_OVL_IS_Msk (0x4000UL) |
SCUPM SYS_IS: VREF5V_OVL_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_VREF5V_OVL_IS_Pos (14UL) |
SCUPM SYS_IS: VREF5V_OVL_IS (Bit 14)
#define SCUPM_SYS_IS_VREF5V_UPTH_IS_Msk (0x2000UL) |
SCUPM SYS_IS: VREF5V_UPTH_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_VREF5V_UPTH_IS_Pos (13UL) |
SCUPM SYS_IS: VREF5V_UPTH_IS (Bit 13)
#define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Msk (0x8000UL) |
SCUPM SYS_ISCLR: ADC2_ESM_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Pos (15UL) |
SCUPM SYS_ISCLR: ADC2_ESM_ICLR (Bit 15)
#define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Msk (0x400000UL) |
SCUPM SYS_ISCLR: ADC3_EOC_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Pos (22UL) |
SCUPM SYS_ISCLR: ADC3_EOC_ICLR (Bit 22)
#define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Msk (0x800000UL) |
SCUPM SYS_ISCLR: ADC4_EOC_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Pos (23UL) |
SCUPM SYS_ISCLR: ADC4_EOC_ICLR (Bit 23)
#define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Msk (0x1UL) |
SCUPM SYS_ISCLR: LIN_OC_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Pos (0UL) |
SCUPM SYS_ISCLR: LIN_OC_ICLR (Bit 0)
#define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Msk (0x2UL) |
SCUPM SYS_ISCLR: LIN_OT_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Pos (1UL) |
SCUPM SYS_ISCLR: LIN_OT_ICLR (Bit 1)
#define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Msk (0x4UL) |
SCUPM SYS_ISCLR: LIN_TMOUT_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Pos (2UL) |
SCUPM SYS_ISCLR: LIN_TMOUT_ICLR (Bit 2)
#define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Msk (0x80UL) |
SCUPM SYS_ISCLR: PMU_OT_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Pos (7UL) |
SCUPM SYS_ISCLR: PMU_OT_ICLR (Bit 7)
#define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Msk (0x40UL) |
SCUPM SYS_ISCLR: PMU_OTWARN_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Pos (6UL) |
SCUPM SYS_ISCLR: PMU_OTWARN_ICLR (Bit 6)
#define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Msk (0x400UL) |
SCUPM SYS_ISCLR: REFBG_LOTHWARN_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Pos (10UL) |
SCUPM SYS_ISCLR: REFBG_LOTHWARN_ICLR (Bit 10)
#define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Msk (0x800UL) |
SCUPM SYS_ISCLR: REFBG_UPTHWARN_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Pos (11UL) |
SCUPM SYS_ISCLR: REFBG_UPTHWARN_ICLR (Bit 11)
#define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Msk (0x200UL) |
SCUPM SYS_ISCLR: SYS_OT_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Pos (9UL) |
SCUPM SYS_ISCLR: SYS_OT_ICLR (Bit 9)
#define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Msk (0x100UL) |
SCUPM SYS_ISCLR: SYS_OTWARN_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Pos (8UL) |
SCUPM SYS_ISCLR: SYS_OTWARN_ICLR (Bit 8)
#define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Msk (0x1000UL) |
SCUPM SYS_ISCLR: VREF5V_LOWTH_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Pos (12UL) |
SCUPM SYS_ISCLR: VREF5V_LOWTH_ICLR (Bit 12)
#define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Msk (0x4000UL) |
SCUPM SYS_ISCLR: VREF5V_OVL_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Pos (14UL) |
SCUPM SYS_ISCLR: VREF5V_OVL_ICLR (Bit 14)
#define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Msk (0x2000UL) |
SCUPM SYS_ISCLR: VREF5V_UPTH_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Pos (13UL) |
SCUPM SYS_ISCLR: VREF5V_UPTH_ICLR (Bit 13)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_ICLR_Msk (0x10UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_OV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_ICLR_Pos (4UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_OV_ICLR (Bit 4)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_SCLR_Msk (0x100000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_OV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_SCLR_Pos (20UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_OV_SCLR (Bit 20)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_ICLR_Msk (0x1UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_UV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_ICLR_Pos (0UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_UV_ICLR (Bit 0)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_SCLR_Msk (0x10000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_UV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_SCLR_Pos (16UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VBAT_UV_SCLR (Bit 16)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Msk (0x80UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Pos (7UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_ICLR (Bit 7)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Msk (0x800000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Pos (23UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_SCLR (Bit 23)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Msk (0x8UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Pos (3UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_ICLR (Bit 3)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Msk (0x80000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Pos (19UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_SCLR (Bit 19)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Msk (0x40UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Pos (6UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_ICLR (Bit 6)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Msk (0x400000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Pos (22UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_SCLR (Bit 22)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Msk (0x4UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Pos (2UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_ICLR (Bit 2)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Msk (0x40000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Pos (18UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_SCLR (Bit 18)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Msk (0x20UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Pos (5UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_ICLR (Bit 5)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Msk (0x200000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Pos (21UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_SCLR (Bit 21)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Msk (0x2UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_ICLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Pos (1UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_ICLR (Bit 1)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Msk (0x20000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_SCLR (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Pos (17UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_SCLR (Bit 17)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_OV_IE_Msk (0x10UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VBAT_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_OV_IE_Pos (4UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VBAT_OV_IE (Bit 4)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_UV_IE_Msk (0x1UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VBAT_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_UV_IE_Pos (0UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VBAT_UV_IE (Bit 0)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Msk (0x80UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Pos (7UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_OV_IE (Bit 7)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Msk (0x8UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Pos (3UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_UV_IE (Bit 3)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Msk (0x40UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Pos (6UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_OV_IE (Bit 6)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Msk (0x4UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Pos (2UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_UV_IE (Bit 2)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Msk (0x20UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Pos (5UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_OV_IE (Bit 5)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Msk (0x2UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Pos (1UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_UV_IE (Bit 1)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_IS_Msk (0x10UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_IS_Pos (4UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_OV_IS (Bit 4)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_STS_Msk (0x100000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_STS_Pos (20UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_OV_STS (Bit 20)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_IS_Msk (0x1UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_IS_Pos (0UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_UV_IS (Bit 0)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_STS_Msk (0x10000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_STS_Pos (16UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VBAT_UV_STS (Bit 16)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Msk (0x80UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Pos (7UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_IS (Bit 7)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Msk (0x800000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Pos (23UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_STS (Bit 23)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Msk (0x8UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Pos (3UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_IS (Bit 3)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Msk (0x80000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Pos (19UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_STS (Bit 19)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Msk (0x40UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Pos (6UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_IS (Bit 6)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Msk (0x400000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Pos (22UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_STS (Bit 22)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Msk (0x4UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Pos (2UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_IS (Bit 2)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Msk (0x40000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Pos (18UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_STS (Bit 18)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Msk (0x20UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Pos (5UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_IS (Bit 5)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Msk (0x200000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Pos (21UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_STS (Bit 21)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Msk (0x2UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Pos (1UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_IS (Bit 1)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Msk (0x20000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Pos (17UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_STS (Bit 17)
#define SCUPM_WDT1_TRIG_SOWCONF_Msk (0xc0UL) |
SCUPM WDT1_TRIG: SOWCONF (Bitfield-Mask: 0x03)
#define SCUPM_WDT1_TRIG_SOWCONF_Pos (6UL) |
SCUPM WDT1_TRIG: SOWCONF (Bit 6)
#define SCUPM_WDT1_TRIG_WDP_SEL_Msk (0x3fUL) |
SCUPM WDT1_TRIG: WDP_SEL (Bitfield-Mask: 0x3f)
#define SCUPM_WDT1_TRIG_WDP_SEL_Pos (0UL) |
SCUPM WDT1_TRIG: WDP_SEL (Bit 0)
#define SSC1_BR_BR_VALUE_Msk (0xffffUL) |
SSC1 BR: BR_VALUE (Bitfield-Mask: 0xffff)
#define SSC1_BR_BR_VALUE_Pos (0UL) |
SSC1 BR: BR_VALUE (Bit 0)
#define SSC1_CON_BC_Msk (0xfUL) |
SSC1 CON: BC (Bitfield-Mask: 0x0f)
#define SSC1_CON_BC_Pos (0UL) |
SSC1 CON: BC (Bit 0)
#define SSC1_CON_BE_Msk (0x800UL) |
SSC1 CON: BE (Bitfield-Mask: 0x01)
#define SSC1_CON_BE_Pos (11UL) |
SSC1 CON: BE (Bit 11)
#define SSC1_CON_BSY_Msk (0x1000UL) |
SSC1 CON: BSY (Bitfield-Mask: 0x01)
#define SSC1_CON_BSY_Pos (12UL) |
SSC1 CON: BSY (Bit 12)
#define SSC1_CON_EN_Msk (0x8000UL) |
SSC1 CON: EN (Bitfield-Mask: 0x01)
#define SSC1_CON_EN_Pos (15UL) |
SSC1 CON: EN (Bit 15)
#define SSC1_CON_MS_Msk (0x4000UL) |
SSC1 CON: MS (Bitfield-Mask: 0x01)
#define SSC1_CON_MS_Pos (14UL) |
SSC1 CON: MS (Bit 14)
#define SSC1_CON_PE_Msk (0x400UL) |
SSC1 CON: PE (Bitfield-Mask: 0x01)
#define SSC1_CON_PE_Pos (10UL) |
SSC1 CON: PE (Bit 10)
#define SSC1_CON_RE_Msk (0x200UL) |
SSC1 CON: RE (Bitfield-Mask: 0x01)
#define SSC1_CON_RE_Pos (9UL) |
SSC1 CON: RE (Bit 9)
#define SSC1_CON_TE_Msk (0x100UL) |
SSC1 CON: TE (Bitfield-Mask: 0x01)
#define SSC1_CON_TE_Pos (8UL) |
SSC1 CON: TE (Bit 8)
#define SSC1_ISRCLR_BECLR_Msk (0x800UL) |
SSC1 ISRCLR: BECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_BECLR_Pos (11UL) |
SSC1 ISRCLR: BECLR (Bit 11)
#define SSC1_ISRCLR_PECLR_Msk (0x400UL) |
SSC1 ISRCLR: PECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_PECLR_Pos (10UL) |
SSC1 ISRCLR: PECLR (Bit 10)
#define SSC1_ISRCLR_RECLR_Msk (0x200UL) |
SSC1 ISRCLR: RECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_RECLR_Pos (9UL) |
SSC1 ISRCLR: RECLR (Bit 9)
#define SSC1_ISRCLR_TECLR_Msk (0x100UL) |
SSC1 ISRCLR: TECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_TECLR_Pos (8UL) |
SSC1 ISRCLR: TECLR (Bit 8)
#define SSC1_PISEL_CIS_Msk (0x4UL) |
SSC1 PISEL: CIS (Bitfield-Mask: 0x01)
#define SSC1_PISEL_CIS_Pos (2UL) |
SSC1 PISEL: CIS (Bit 2)
#define SSC1_PISEL_MIS_0_Msk (0x1UL) |
SSC1 PISEL: MIS_0 (Bitfield-Mask: 0x01)
#define SSC1_PISEL_MIS_0_Pos (0UL) |
SSC1 PISEL: MIS_0 (Bit 0)
#define SSC1_PISEL_MIS_1_Msk (0x8UL) |
SSC1 PISEL: MIS_1 (Bitfield-Mask: 0x01)
#define SSC1_PISEL_MIS_1_Pos (3UL) |
SSC1 PISEL: MIS_1 (Bit 3)
#define SSC1_PISEL_SIS_Msk (0x2UL) |
SSC1 PISEL: SIS (Bitfield-Mask: 0x01)
#define SSC1_PISEL_SIS_Pos (1UL) |
SSC1 PISEL: SIS (Bit 1)
#define SSC1_RB_RB_VALUE_Msk (0xffffUL) |
SSC1 RB: RB_VALUE (Bitfield-Mask: 0xffff)
#define SSC1_RB_RB_VALUE_Pos (0UL) |
SSC1 RB: RB_VALUE (Bit 0)
#define SSC1_TB_TB_VALUE_Msk (0xffffUL) |
SSC1 TB: TB_VALUE (Bitfield-Mask: 0xffff)
#define SSC1_TB_TB_VALUE_Pos (0UL) |
SSC1 TB: TB_VALUE (Bit 0)
#define SSC2_BR_BR_VALUE_Msk (0xffffUL) |
SSC2 BR: BR_VALUE (Bitfield-Mask: 0xffff)
#define SSC2_BR_BR_VALUE_Pos (0UL) |
SSC2 BR: BR_VALUE (Bit 0)
#define SSC2_CON_BC_Msk (0xfUL) |
SSC2 CON: BC (Bitfield-Mask: 0x0f)
#define SSC2_CON_BC_Pos (0UL) |
SSC2 CON: BC (Bit 0)
#define SSC2_CON_BE_Msk (0x800UL) |
SSC2 CON: BE (Bitfield-Mask: 0x01)
#define SSC2_CON_BE_Pos (11UL) |
SSC2 CON: BE (Bit 11)
#define SSC2_CON_BSY_Msk (0x1000UL) |
SSC2 CON: BSY (Bitfield-Mask: 0x01)
#define SSC2_CON_BSY_Pos (12UL) |
SSC2 CON: BSY (Bit 12)
#define SSC2_CON_EN_Msk (0x8000UL) |
SSC2 CON: EN (Bitfield-Mask: 0x01)
#define SSC2_CON_EN_Pos (15UL) |
SSC2 CON: EN (Bit 15)
#define SSC2_CON_MS_Msk (0x4000UL) |
SSC2 CON: MS (Bitfield-Mask: 0x01)
#define SSC2_CON_MS_Pos (14UL) |
SSC2 CON: MS (Bit 14)
#define SSC2_CON_PE_Msk (0x400UL) |
SSC2 CON: PE (Bitfield-Mask: 0x01)
#define SSC2_CON_PE_Pos (10UL) |
SSC2 CON: PE (Bit 10)
#define SSC2_CON_RE_Msk (0x200UL) |
SSC2 CON: RE (Bitfield-Mask: 0x01)
#define SSC2_CON_RE_Pos (9UL) |
SSC2 CON: RE (Bit 9)
#define SSC2_CON_TE_Msk (0x100UL) |
SSC2 CON: TE (Bitfield-Mask: 0x01)
#define SSC2_CON_TE_Pos (8UL) |
SSC2 CON: TE (Bit 8)
#define SSC2_ISRCLR_BECLR_Msk (0x800UL) |
SSC2 ISRCLR: BECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_BECLR_Pos (11UL) |
SSC2 ISRCLR: BECLR (Bit 11)
#define SSC2_ISRCLR_PECLR_Msk (0x400UL) |
SSC2 ISRCLR: PECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_PECLR_Pos (10UL) |
SSC2 ISRCLR: PECLR (Bit 10)
#define SSC2_ISRCLR_RECLR_Msk (0x200UL) |
SSC2 ISRCLR: RECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_RECLR_Pos (9UL) |
SSC2 ISRCLR: RECLR (Bit 9)
#define SSC2_ISRCLR_TECLR_Msk (0x100UL) |
SSC2 ISRCLR: TECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_TECLR_Pos (8UL) |
SSC2 ISRCLR: TECLR (Bit 8)
#define SSC2_PISEL_CIS_Msk (0x4UL) |
SSC2 PISEL: CIS (Bitfield-Mask: 0x01)
#define SSC2_PISEL_CIS_Pos (2UL) |
SSC2 PISEL: CIS (Bit 2)
#define SSC2_PISEL_MIS_0_Msk (0x1UL) |
SSC2 PISEL: MIS_0 (Bitfield-Mask: 0x01)
#define SSC2_PISEL_MIS_0_Pos (0UL) |
SSC2 PISEL: MIS_0 (Bit 0)
#define SSC2_PISEL_MIS_1_Msk (0x8UL) |
SSC2 PISEL: MIS_1 (Bitfield-Mask: 0x01)
#define SSC2_PISEL_MIS_1_Pos (3UL) |
SSC2 PISEL: MIS_1 (Bit 3)
#define SSC2_PISEL_SIS_Msk (0x2UL) |
SSC2 PISEL: SIS (Bitfield-Mask: 0x01)
#define SSC2_PISEL_SIS_Pos (1UL) |
SSC2 PISEL: SIS (Bit 1)
#define SSC2_RB_RB_VALUE_Msk (0xffffUL) |
SSC2 RB: RB_VALUE (Bitfield-Mask: 0xffff)
#define SSC2_RB_RB_VALUE_Pos (0UL) |
SSC2 RB: RB_VALUE (Bit 0)
#define SSC2_TB_TB_VALUE_Msk (0xffffUL) |
SSC2 TB: TB_VALUE (Bitfield-Mask: 0xffff)
#define SSC2_TB_TB_VALUE_Pos (0UL) |
SSC2 TB: TB_VALUE (Bit 0)
#define TIMER21_RC2H_RC2_Msk (0xffUL) |
TIMER21 RC2H: RC2 (Bitfield-Mask: 0xff)
#define TIMER21_RC2H_RC2_Pos (0UL) |
TIMER21 RC2H: RC2 (Bit 0)
#define TIMER21_RC2L_RC2_Msk (0xffUL) |
TIMER21 RC2L: RC2 (Bitfield-Mask: 0xff)
#define TIMER21_RC2L_RC2_Pos (0UL) |
TIMER21 RC2L: RC2 (Bit 0)
#define TIMER21_T2CON1_EXF2EN_Msk (0x1UL) |
TIMER21 T2CON1: EXF2EN (Bitfield-Mask: 0x01)
#define TIMER21_T2CON1_EXF2EN_Pos (0UL) |
TIMER21 T2CON1: EXF2EN (Bit 0)
#define TIMER21_T2CON1_TF2EN_Msk (0x2UL) |
TIMER21 T2CON1: TF2EN (Bitfield-Mask: 0x01)
#define TIMER21_T2CON1_TF2EN_Pos (1UL) |
TIMER21 T2CON1: TF2EN (Bit 1)
#define TIMER21_T2CON_C_T2_Msk (0x2UL) |
TIMER21 T2CON: C_T2 (Bitfield-Mask: 0x01)
#define TIMER21_T2CON_C_T2_Pos (1UL) |
TIMER21 T2CON: C_T2 (Bit 1)
#define TIMER21_T2CON_CP_RL2_Msk (0x1UL) |
TIMER21 T2CON: CP_RL2 (Bitfield-Mask: 0x01)
#define TIMER21_T2CON_CP_RL2_Pos (0UL) |
TIMER21 T2CON: CP_RL2 (Bit 0)
#define TIMER21_T2CON_EXEN2_Msk (0x8UL) |
TIMER21 T2CON: EXEN2 (Bitfield-Mask: 0x01)
#define TIMER21_T2CON_EXEN2_Pos (3UL) |
TIMER21 T2CON: EXEN2 (Bit 3)
#define TIMER21_T2CON_EXF2_Msk (0x40UL) |
TIMER21 T2CON: EXF2 (Bitfield-Mask: 0x01)
#define TIMER21_T2CON_EXF2_Pos (6UL) |
TIMER21 T2CON: EXF2 (Bit 6)
#define TIMER21_T2CON_TF2_Msk (0x80UL) |
TIMER21 T2CON: TF2 (Bitfield-Mask: 0x01)
#define TIMER21_T2CON_TF2_Pos (7UL) |
TIMER21 T2CON: TF2 (Bit 7)
#define TIMER21_T2CON_TR2_Msk (0x4UL) |
TIMER21 T2CON: TR2 (Bitfield-Mask: 0x01)
#define TIMER21_T2CON_TR2_Pos (2UL) |
TIMER21 T2CON: TR2 (Bit 2)
#define TIMER21_T2H_T2H_Msk (0xffUL) |
TIMER21 T2H: T2H (Bitfield-Mask: 0xff)
#define TIMER21_T2H_T2H_Pos (0UL) |
TIMER21 T2H: T2H (Bit 0)
#define TIMER21_T2ICLR_EXF2CLR_Msk (0x40UL) |
TIMER21 T2ICLR: EXF2CLR (Bitfield-Mask: 0x01)
#define TIMER21_T2ICLR_EXF2CLR_Pos (6UL) |
TIMER21 T2ICLR: EXF2CLR (Bit 6)
#define TIMER21_T2ICLR_TF2CLR_Msk (0x80UL) |
TIMER21 T2ICLR: TF2CLR (Bitfield-Mask: 0x01)
#define TIMER21_T2ICLR_TF2CLR_Pos (7UL) |
TIMER21 T2ICLR: TF2CLR (Bit 7)
#define TIMER21_T2L_T2L_Msk (0xffUL) |
TIMER21 T2L: T2L (Bitfield-Mask: 0xff)
#define TIMER21_T2L_T2L_Pos (0UL) |
TIMER21 T2L: T2L (Bit 0)
#define TIMER21_T2MOD_DCEN_Msk (0x1UL) |
TIMER21 T2MOD: DCEN (Bitfield-Mask: 0x01)
#define TIMER21_T2MOD_DCEN_Pos (0UL) |
TIMER21 T2MOD: DCEN (Bit 0)
#define TIMER21_T2MOD_EDGESEL_Msk (0x20UL) |
TIMER21 T2MOD: EDGESEL (Bitfield-Mask: 0x01)
#define TIMER21_T2MOD_EDGESEL_Pos (5UL) |
TIMER21 T2MOD: EDGESEL (Bit 5)
#define TIMER21_T2MOD_PREN_Msk (0x10UL) |
TIMER21 T2MOD: PREN (Bitfield-Mask: 0x01)
#define TIMER21_T2MOD_PREN_Pos (4UL) |
TIMER21 T2MOD: PREN (Bit 4)
#define TIMER21_T2MOD_T2PRE_Msk (0xeUL) |
TIMER21 T2MOD: T2PRE (Bitfield-Mask: 0x07)
#define TIMER21_T2MOD_T2PRE_Pos (1UL) |
TIMER21 T2MOD: T2PRE (Bit 1)
#define TIMER21_T2MOD_T2REGS_Msk (0x80UL) |
TIMER21 T2MOD: T2REGS (Bitfield-Mask: 0x01)
#define TIMER21_T2MOD_T2REGS_Pos (7UL) |
TIMER21 T2MOD: T2REGS (Bit 7)
#define TIMER21_T2MOD_T2RHEN_Msk (0x40UL) |
TIMER21 T2MOD: T2RHEN (Bitfield-Mask: 0x01)
#define TIMER21_T2MOD_T2RHEN_Pos (6UL) |
TIMER21 T2MOD: T2RHEN (Bit 6)
#define TIMER2_RC2H_RC2_Msk (0xffUL) |
TIMER2 RC2H: RC2 (Bitfield-Mask: 0xff)
#define TIMER2_RC2H_RC2_Pos (0UL) |
TIMER2 RC2H: RC2 (Bit 0)
#define TIMER2_RC2L_RC2_Msk (0xffUL) |
TIMER2 RC2L: RC2 (Bitfield-Mask: 0xff)
#define TIMER2_RC2L_RC2_Pos (0UL) |
TIMER2 RC2L: RC2 (Bit 0)
#define TIMER2_T2CON1_EXF2EN_Msk (0x1UL) |
TIMER2 T2CON1: EXF2EN (Bitfield-Mask: 0x01)
#define TIMER2_T2CON1_EXF2EN_Pos (0UL) |
TIMER2 T2CON1: EXF2EN (Bit 0)
#define TIMER2_T2CON1_TF2EN_Msk (0x2UL) |
TIMER2 T2CON1: TF2EN (Bitfield-Mask: 0x01)
#define TIMER2_T2CON1_TF2EN_Pos (1UL) |
TIMER2 T2CON1: TF2EN (Bit 1)
#define TIMER2_T2CON_C_T2_Msk (0x2UL) |
TIMER2 T2CON: C_T2 (Bitfield-Mask: 0x01)
#define TIMER2_T2CON_C_T2_Pos (1UL) |
TIMER2 T2CON: C_T2 (Bit 1)
#define TIMER2_T2CON_CP_RL2_Msk (0x1UL) |
TIMER2 T2CON: CP_RL2 (Bitfield-Mask: 0x01)
#define TIMER2_T2CON_CP_RL2_Pos (0UL) |
TIMER2 T2CON: CP_RL2 (Bit 0)
#define TIMER2_T2CON_EXEN2_Msk (0x8UL) |
TIMER2 T2CON: EXEN2 (Bitfield-Mask: 0x01)
#define TIMER2_T2CON_EXEN2_Pos (3UL) |
TIMER2 T2CON: EXEN2 (Bit 3)
#define TIMER2_T2CON_EXF2_Msk (0x40UL) |
TIMER2 T2CON: EXF2 (Bitfield-Mask: 0x01)
#define TIMER2_T2CON_EXF2_Pos (6UL) |
TIMER2 T2CON: EXF2 (Bit 6)
#define TIMER2_T2CON_TF2_Msk (0x80UL) |
TIMER2 T2CON: TF2 (Bitfield-Mask: 0x01)
#define TIMER2_T2CON_TF2_Pos (7UL) |
TIMER2 T2CON: TF2 (Bit 7)
#define TIMER2_T2CON_TR2_Msk (0x4UL) |
TIMER2 T2CON: TR2 (Bitfield-Mask: 0x01)
#define TIMER2_T2CON_TR2_Pos (2UL) |
TIMER2 T2CON: TR2 (Bit 2)
#define TIMER2_T2H_T2H_Msk (0xffUL) |
TIMER2 T2H: T2H (Bitfield-Mask: 0xff)
#define TIMER2_T2H_T2H_Pos (0UL) |
TIMER2 T2H: T2H (Bit 0)
#define TIMER2_T2ICLR_EXF2CLR_Msk (0x40UL) |
TIMER2 T2ICLR: EXF2CLR (Bitfield-Mask: 0x01)
#define TIMER2_T2ICLR_EXF2CLR_Pos (6UL) |
TIMER2 T2ICLR: EXF2CLR (Bit 6)
#define TIMER2_T2ICLR_TF2CLR_Msk (0x80UL) |
TIMER2 T2ICLR: TF2CLR (Bitfield-Mask: 0x01)
#define TIMER2_T2ICLR_TF2CLR_Pos (7UL) |
TIMER2 T2ICLR: TF2CLR (Bit 7)
#define TIMER2_T2L_T2L_Msk (0xffUL) |
TIMER2 T2L: T2L (Bitfield-Mask: 0xff)
#define TIMER2_T2L_T2L_Pos (0UL) |
TIMER2 T2L: T2L (Bit 0)
#define TIMER2_T2MOD_DCEN_Msk (0x1UL) |
TIMER2 T2MOD: DCEN (Bitfield-Mask: 0x01)
#define TIMER2_T2MOD_DCEN_Pos (0UL) |
TIMER2 T2MOD: DCEN (Bit 0)
#define TIMER2_T2MOD_EDGESEL_Msk (0x20UL) |
TIMER2 T2MOD: EDGESEL (Bitfield-Mask: 0x01)
#define TIMER2_T2MOD_EDGESEL_Pos (5UL) |
TIMER2 T2MOD: EDGESEL (Bit 5)
#define TIMER2_T2MOD_PREN_Msk (0x10UL) |
TIMER2 T2MOD: PREN (Bitfield-Mask: 0x01)
#define TIMER2_T2MOD_PREN_Pos (4UL) |
TIMER2 T2MOD: PREN (Bit 4)
#define TIMER2_T2MOD_T2PRE_Msk (0xeUL) |
TIMER2 T2MOD: T2PRE (Bitfield-Mask: 0x07)
#define TIMER2_T2MOD_T2PRE_Pos (1UL) |
TIMER2 T2MOD: T2PRE (Bit 1)
#define TIMER2_T2MOD_T2REGS_Msk (0x80UL) |
TIMER2 T2MOD: T2REGS (Bitfield-Mask: 0x01)
#define TIMER2_T2MOD_T2REGS_Pos (7UL) |
TIMER2 T2MOD: T2REGS (Bit 7)
#define TIMER2_T2MOD_T2RHEN_Msk (0x40UL) |
TIMER2 T2MOD: T2RHEN (Bitfield-Mask: 0x01)
#define TIMER2_T2MOD_T2RHEN_Pos (6UL) |
TIMER2 T2MOD: T2RHEN (Bit 6)
#define TIMER3_CMP_HI_Msk (0xff00UL) |
TIMER3 CMP: HI (Bitfield-Mask: 0xff)
#define TIMER3_CMP_HI_Pos (8UL) |
TIMER3 CMP: HI (Bit 8)
#define TIMER3_CMP_LO_Msk (0xffUL) |
TIMER3 CMP: LO (Bitfield-Mask: 0xff)
#define TIMER3_CMP_LO_Pos (0UL) |
TIMER3 CMP: LO (Bit 0)
#define TIMER3_CNT_HI_Msk (0xff00UL) |
TIMER3 CNT: HI (Bitfield-Mask: 0xff)
#define TIMER3_CNT_HI_Pos (8UL) |
TIMER3 CNT: HI (Bit 8)
#define TIMER3_CNT_LO_Msk (0xffUL) |
TIMER3 CNT: LO (Bitfield-Mask: 0xff)
#define TIMER3_CNT_LO_Pos (0UL) |
TIMER3 CNT: LO (Bit 0)
#define TIMER3_CTRL_CNT_RDY_Msk (0x8UL) |
TIMER3 CTRL: CNT_RDY (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_CNT_RDY_Pos (3UL) |
TIMER3 CTRL: CNT_RDY (Bit 3)
#define TIMER3_CTRL_T3_PD_N_Msk (0x1UL) |
TIMER3 CTRL: T3_PD_N (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_T3_PD_N_Pos (0UL) |
TIMER3 CTRL: T3_PD_N (Bit 0)
#define TIMER3_CTRL_T3_RD_REQ_CONF_Msk (0x4UL) |
TIMER3 CTRL: T3_RD_REQ_CONF (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_T3_RD_REQ_CONF_Pos (2UL) |
TIMER3 CTRL: T3_RD_REQ_CONF (Bit 2)
#define TIMER3_CTRL_T3_RD_REQ_Msk (0x2UL) |
TIMER3 CTRL: T3_RD_REQ (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_T3_RD_REQ_Pos (1UL) |
TIMER3 CTRL: T3_RD_REQ (Bit 1)
#define TIMER3_CTRL_T3H_OVF_IE_Msk (0x200UL) |
TIMER3 CTRL: T3H_OVF_IE (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_T3H_OVF_IE_Pos (9UL) |
TIMER3 CTRL: T3H_OVF_IE (Bit 9)
#define TIMER3_CTRL_T3H_OVF_STS_Msk (0x20UL) |
TIMER3 CTRL: T3H_OVF_STS (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_T3H_OVF_STS_Pos (5UL) |
TIMER3 CTRL: T3H_OVF_STS (Bit 5)
#define TIMER3_CTRL_T3L_OVF_IE_Msk (0x100UL) |
TIMER3 CTRL: T3L_OVF_IE (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_T3L_OVF_IE_Pos (8UL) |
TIMER3 CTRL: T3L_OVF_IE (Bit 8)
#define TIMER3_CTRL_T3L_OVF_STS_Msk (0x80UL) |
TIMER3 CTRL: T3L_OVF_STS (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_T3L_OVF_STS_Pos (7UL) |
TIMER3 CTRL: T3L_OVF_STS (Bit 7)
#define TIMER3_CTRL_TR3H_Msk (0x10UL) |
TIMER3 CTRL: TR3H (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_TR3H_Pos (4UL) |
TIMER3 CTRL: TR3H (Bit 4)
#define TIMER3_CTRL_TR3L_Msk (0x40UL) |
TIMER3 CTRL: TR3L (Bitfield-Mask: 0x01)
#define TIMER3_CTRL_TR3L_Pos (6UL) |
TIMER3 CTRL: TR3L (Bit 6)
#define TIMER3_ISRCLR_T3H_OVF_ICLR_Msk (0x20UL) |
TIMER3 ISRCLR: T3H_OVF_ICLR (Bitfield-Mask: 0x01)
#define TIMER3_ISRCLR_T3H_OVF_ICLR_Pos (5UL) |
TIMER3 ISRCLR: T3H_OVF_ICLR (Bit 5)
#define TIMER3_ISRCLR_T3L_OVF_ICLR_Msk (0x80UL) |
TIMER3 ISRCLR: T3L_OVF_ICLR (Bitfield-Mask: 0x01)
#define TIMER3_ISRCLR_T3L_OVF_ICLR_Pos (7UL) |
TIMER3 ISRCLR: T3L_OVF_ICLR (Bit 7)
#define TIMER3_MODE_CONF_T3_SUBM_Msk (0xc0UL) |
TIMER3 MODE_CONF: T3_SUBM (Bitfield-Mask: 0x03)
#define TIMER3_MODE_CONF_T3_SUBM_Pos (6UL) |
TIMER3 MODE_CONF: T3_SUBM (Bit 6)
#define TIMER3_MODE_CONF_T3M_Msk (0x3UL) |
TIMER3 MODE_CONF: T3M (Bitfield-Mask: 0x03)
#define TIMER3_MODE_CONF_T3M_Pos (0UL) |
TIMER3 MODE_CONF: T3M (Bit 0)
#define TIMER3_T3_TRIGG_CTRL_RETRIG_Msk (0x40UL) |
TIMER3 T3_TRIGG_CTRL: RETRIG (Bitfield-Mask: 0x01)
#define TIMER3_T3_TRIGG_CTRL_RETRIG_Pos (6UL) |
TIMER3 T3_TRIGG_CTRL: RETRIG (Bit 6)
#define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Msk (0x30UL) |
TIMER3 T3_TRIGG_CTRL: T3_RES_CONF (Bitfield-Mask: 0x03)
#define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Pos (4UL) |
TIMER3 T3_TRIGG_CTRL: T3_RES_CONF (Bit 4)
#define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Msk (0x7UL) |
TIMER3 T3_TRIGG_CTRL: T3_TRIGG_INP_SEL (Bitfield-Mask: 0x07)
#define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Pos (0UL) |
TIMER3 T3_TRIGG_CTRL: T3_TRIGG_INP_SEL (Bit 0)
#define UART1_SBUF_VAL_Msk (0xffUL) |
UART1 SBUF: VAL (Bitfield-Mask: 0xff)
#define UART1_SBUF_VAL_Pos (0UL) |
UART1 SBUF: VAL (Bit 0)
#define UART1_SCON_RB8_Msk (0x4UL) |
UART1 SCON: RB8 (Bitfield-Mask: 0x01)
#define UART1_SCON_RB8_Pos (2UL) |
UART1 SCON: RB8 (Bit 2)
#define UART1_SCON_REN_Msk (0x10UL) |
UART1 SCON: REN (Bitfield-Mask: 0x01)
#define UART1_SCON_REN_Pos (4UL) |
UART1 SCON: REN (Bit 4)
#define UART1_SCON_RI_Msk (0x1UL) |
UART1 SCON: RI (Bitfield-Mask: 0x01)
#define UART1_SCON_RI_Pos (0UL) |
UART1 SCON: RI (Bit 0)
#define UART1_SCON_SM0_Msk (0x80UL) |
UART1 SCON: SM0 (Bitfield-Mask: 0x01)
#define UART1_SCON_SM0_Pos (7UL) |
UART1 SCON: SM0 (Bit 7)
#define UART1_SCON_SM1_Msk (0x40UL) |
UART1 SCON: SM1 (Bitfield-Mask: 0x01)
#define UART1_SCON_SM1_Pos (6UL) |
UART1 SCON: SM1 (Bit 6)
#define UART1_SCON_SM2_Msk (0x20UL) |
UART1 SCON: SM2 (Bitfield-Mask: 0x01)
#define UART1_SCON_SM2_Pos (5UL) |
UART1 SCON: SM2 (Bit 5)
#define UART1_SCON_TB8_Msk (0x8UL) |
UART1 SCON: TB8 (Bitfield-Mask: 0x01)
#define UART1_SCON_TB8_Pos (3UL) |
UART1 SCON: TB8 (Bit 3)
#define UART1_SCON_TI_Msk (0x2UL) |
UART1 SCON: TI (Bitfield-Mask: 0x01)
#define UART1_SCON_TI_Pos (1UL) |
UART1 SCON: TI (Bit 1)
#define UART1_SCONCLR_RICLR_Msk (0x1UL) |
UART1 SCONCLR: RICLR (Bitfield-Mask: 0x01)
#define UART1_SCONCLR_RICLR_Pos (0UL) |
UART1 SCONCLR: RICLR (Bit 0)
#define UART1_SCONCLR_TICLR_Msk (0x2UL) |
UART1 SCONCLR: TICLR (Bitfield-Mask: 0x01)
#define UART1_SCONCLR_TICLR_Pos (1UL) |
UART1 SCONCLR: TICLR (Bit 1)
#define UART2_SBUF_VAL_Msk (0xffUL) |
UART2 SBUF: VAL (Bitfield-Mask: 0xff)
#define UART2_SBUF_VAL_Pos (0UL) |
UART2 SBUF: VAL (Bit 0)
#define UART2_SCON_RB8_Msk (0x4UL) |
UART2 SCON: RB8 (Bitfield-Mask: 0x01)
#define UART2_SCON_RB8_Pos (2UL) |
UART2 SCON: RB8 (Bit 2)
#define UART2_SCON_REN_Msk (0x10UL) |
UART2 SCON: REN (Bitfield-Mask: 0x01)
#define UART2_SCON_REN_Pos (4UL) |
UART2 SCON: REN (Bit 4)
#define UART2_SCON_RI_Msk (0x1UL) |
UART2 SCON: RI (Bitfield-Mask: 0x01)
#define UART2_SCON_RI_Pos (0UL) |
UART2 SCON: RI (Bit 0)
#define UART2_SCON_SM0_Msk (0x80UL) |
UART1 SCON: SM0 (Bitfield-Mask: 0x01)
#define UART2_SCON_SM0_Pos (7UL) |
UART1 SCON: SM0 (Bit 7)
#define UART2_SCON_SM1_Msk (0x40UL) |
UART1 SCON: SM1 (Bitfield-Mask: 0x01)
#define UART2_SCON_SM1_Pos (6UL) |
UART1 SCON: SM1 (Bit 6)
#define UART2_SCON_SM2_Msk (0x20UL) |
UART2 SCON: SM2 (Bitfield-Mask: 0x01)
#define UART2_SCON_SM2_Pos (5UL) |
UART2 SCON: SM2 (Bit 5)
#define UART2_SCON_TB8_Msk (0x8UL) |
UART2 SCON: TB8 (Bitfield-Mask: 0x01)
#define UART2_SCON_TB8_Pos (3UL) |
UART2 SCON: TB8 (Bit 3)
#define UART2_SCON_TI_Msk (0x2UL) |
UART2 SCON: TI (Bitfield-Mask: 0x01)
#define UART2_SCON_TI_Pos (1UL) |
UART2 SCON: TI (Bit 1)
#define UART2_SCONCLR_RICLR_Msk (0x1UL) |
UART2 SCONCLR: RICLR (Bitfield-Mask: 0x01)
#define UART2_SCONCLR_RICLR_Pos (0UL) |
UART2 SCONCLR: RICLR (Bit 0)
#define UART2_SCONCLR_TICLR_Msk (0x2UL) |
UART2 SCONCLR: TICLR (Bitfield-Mask: 0x01)
#define UART2_SCONCLR_TICLR_Pos (1UL) |
UART2 SCONCLR: TICLR (Bit 1)