TLE986x Device Family SDK
Data Fields
CPU_Type Struct Reference

Detailed Description

CPU Core (CPU)

#include <tle986x.h>

Data Fields

__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   INTLINESNUM: 5
 
   }   bit
 
ICT
 
__IM uint32_t RESERVED1 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ENABLE: 1
 
      __IOM uint32_t   TICKINT: 1
 
      __IOM uint32_t   CLKSOURCE: 1
 
      __IM   uint32_t: 13
 
      __IOM uint32_t   COUNTFLAG: 1
 
   }   bit
 
SYSTICK_CS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RELOAD: 24
 
   }   bit
 
SYSTICK_RL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CURRENT: 24
 
   }   bit
 
SYSTICK_CUR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   TENMS: 24
 
      __IM   uint32_t: 6
 
      __IM uint32_t   SKEW: 1
 
      __IM uint32_t   NOREF: 1
 
   }   bit
 
SYSTICK_CAL
 
__IM uint32_t RESERVED2 [56]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_DMA: 1
 
   }   bit
 
NVIC_ISER0
 
__IM uint32_t RESERVED3 [31]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_DMA: 1
 
   }   bit
 
NVIC_ICER0
 
__IM uint32_t RESERVED4 [31]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_DMA: 1
 
   }   bit
 
NVIC_ISPR0
 
__IM uint32_t RESERVED5 [31]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_DMA: 1
 
   }   bit
 
NVIC_ICPR0
 
__IM uint32_t RESERVED6 [31]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   Int_GPT1: 1
 
      __IM uint32_t   Int_GPT2: 1
 
      __IM uint32_t   Int_ADC2: 1
 
      __IM uint32_t   Int_ADC1: 1
 
      __IM uint32_t   Int_CCU6SR0: 1
 
      __IM uint32_t   Int_CCU6SR1: 1
 
      __IM uint32_t   Int_CCU6SR2: 1
 
      __IM uint32_t   Int_CCU6SR3: 1
 
      __IM uint32_t   Int_SSC1: 1
 
      __IM uint32_t   Int_SSC2: 1
 
      __IM uint32_t   Int_UART1: 1
 
      __IM uint32_t   Int_UART2: 1
 
      __IM uint32_t   Int_EXINT0: 1
 
      __IM uint32_t   Int_EXINT1: 1
 
      __IM uint32_t   Int_BDRV: 1
 
      __IM uint32_t   Int_DMA: 1
 
   }   bit
 
NVIC_IABR0
 
__IM uint32_t RESERVED7 [63]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRI_GPT1: 8
 
      __IOM uint32_t   PRI_GPT2: 8
 
      __IOM uint32_t   PRI_ADC2: 8
 
      __IOM uint32_t   PRI_ADC1: 8
 
   }   bit
 
NVIC_IPR0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRI_CCU6SR0: 8
 
      __IOM uint32_t   PRI_CCU6SR1: 8
 
      __IOM uint32_t   PRI_CCU6SR2: 8
 
      __IOM uint32_t   PRI_CCU6SR3: 8
 
   }   bit
 
NVIC_IPR1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRI_SSC1: 8
 
      __IOM uint32_t   PRI_SSC2: 8
 
      __IOM uint32_t   PRI_UART1: 8
 
      __IOM uint32_t   PRI_UART2: 8
 
   }   bit
 
NVIC_IPR2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRI_EXINT0: 8
 
      __IOM uint32_t   PRI_EXINT1: 8
 
      __IOM uint32_t   PRI_BDRV: 8
 
      __IOM uint32_t   PRI_DMA: 8
 
   }   bit
 
NVIC_IPR3
 
__IM uint32_t RESERVED8 [572]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   REVISION: 4
 
      __IM uint32_t   PARTNO: 12
 
      __IM uint32_t   ARCHITECTURE: 4
 
      __IM uint32_t   VARIANT: 4
 
      __IM uint32_t   IMPLEMENTER: 8
 
   }   bit
 
CPUID
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   VECTACTIVE: 9
 
      __IM   uint32_t: 2
 
      __IM uint32_t   RETTOBASE: 1
 
      __IM uint32_t   VECTPENDING: 9
 
      __IM uint32_t   ISRPENDING: 1
 
      __IM uint32_t   ISRPREEMPT: 1
 
      __OM uint32_t   PENDSTCLR: 1
 
      __IOM uint32_t   PENDSTSET: 1
 
      __OM uint32_t   PENDSVCLR: 1
 
      __IOM uint32_t   PENDSVSET: 1
 
      __IOM uint32_t   NMIPENDSET: 1
 
   }   bit
 
ICSR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 7
 
      __IOM uint32_t   TBLOFF: 25
 
   }   bit
 
VTOR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VECTRESET: 1
 
      __IOM uint32_t   VECTCLRACTIVE: 1
 
      __IOM uint32_t   SYSRESETREQ: 1
 
      __IM   uint32_t: 5
 
      __IOM uint32_t   PRIGROUP: 3
 
      __IM uint32_t   ENDIANNESS: 1
 
      __IOM uint32_t   VECTKEY: 16
 
   }   bit
 
AIRCR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IOM uint32_t   SLEEPONEXIT: 1
 
      __IOM uint32_t   SLEEPDEEP: 1
 
      __IOM uint32_t   SEVONPEND: 1
 
   }   bit
 
SCR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NONBASETHRDENA: 1
 
      __IOM uint32_t   USERSETMPEND: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   UNALIGN_TRP: 1
 
      __IOM uint32_t   DIV_0_TRP: 1
 
      __IOM uint32_t   BFHFMIGN: 1
 
      __IOM uint32_t   STKALIGN: 1
 
   }   bit
 
CCR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRI_4: 8
 
      __IOM uint32_t   PRI_5: 8
 
      __IOM uint32_t   PRI_6: 8
 
      __IOM uint32_t   PRI_7: 8
 
   }   bit
 
SHPR1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRI_8: 8
 
      __IOM uint32_t   PRI_9: 8
 
      __IOM uint32_t   PRI_10: 8
 
      __IOM uint32_t   PRI_11: 8
 
   }   bit
 
SHPR2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PRI_12: 8
 
      __IOM uint32_t   PRI_13: 8
 
      __IOM uint32_t   PRI_14: 8
 
      __IOM uint32_t   PRI_15: 8
 
   }   bit
 
SHPR3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MEMFAULTACT: 1
 
      __IOM uint32_t   BUSFAULTACT: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   USGFAULTACT: 1
 
      __IOM uint32_t   SVCALLACT: 1
 
      __IOM uint32_t   MONITORACT: 1
 
      __IOM uint32_t   PENDSVACT: 1
 
      __IOM uint32_t   SYSTICKACT: 1
 
      __IOM uint32_t   USGFAULTPENDED: 1
 
      __IOM uint32_t   MEMFAULTPENDED: 1
 
      __IOM uint32_t   BUSFAULTPENDED: 1
 
      __IOM uint32_t   SVCALLPENDED: 1
 
      __IOM uint32_t   MEMFAULTENA: 1
 
      __IOM uint32_t   BUSFAULTENA: 1
 
      __IOM uint32_t   USGFAULTENA: 1
 
   }   bit
 
SHCSR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IACCVIOL: 1
 
      __IOM uint32_t   DACCVIOL: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   MUNSTKERR: 1
 
      __IOM uint32_t   MSTERR: 1
 
      __IOM uint32_t   MMARVALID: 1
 
      __IOM uint32_t   IBUSERR: 1
 
      __IOM uint32_t   PRECISERR: 1
 
      __IOM uint32_t   IMPRECISERR: 1
 
      __IOM uint32_t   UNSTKERR: 1
 
      __IOM uint32_t   STKERR: 1
 
      __IOM uint32_t   BFARVALID: 1
 
      __IOM uint32_t   UNDEFINSTR: 1
 
      __IOM uint32_t   INVSTATE: 1
 
      __IOM uint32_t   INVPC: 1
 
      __IOM uint32_t   NOCP: 1
 
      __IOM uint32_t   UNALIGNED: 1
 
      __IOM uint32_t   DIVBYZERO: 1
 
   }   bit
 
CFSR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IOM uint32_t   VECTTBL: 1
 
      __IOM uint32_t   FORCED: 1
 
      __IOM uint32_t   DEBUGEVT: 1
 
   }   bit
 
HFSR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HALTED: 1
 
      __IOM uint32_t   BKPT: 1
 
      __IOM uint32_t   DWTTRAP: 1
 
      __IOM uint32_t   VCATCH: 1
 
      __IOM uint32_t   EXTERNAL: 1
 
   }   bit
 
DFSR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ADDRESS: 32
 
   }   bit
 
MMFAR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ADDRESS: 32
 
   }   bit
 
BFAR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CP0: 2
 
      __IOM uint32_t   CP1: 2
 
      __IOM uint32_t   CP2: 2
 
      __IOM uint32_t   CP3: 2
 
      __IOM uint32_t   CP4: 2
 
      __IOM uint32_t   CP5: 2
 
      __IOM uint32_t   CP6: 2
 
      __IOM uint32_t   CP7: 2
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   CP10: 2
 
      __IOM uint32_t   CP11: 2
 
   }   bit
 
AFSR
 

Field Documentation

◆ ADDRESS

__IOM uint32_t ADDRESS

[31..0] Data Address for an MPU Fault

[31..0] Data Address for a precise BusFault

◆ AFSR

union { ... } AFSR

◆ AIRCR

union { ... } AIRCR

◆ ARCHITECTURE

__IM uint32_t ARCHITECTURE

[19..16] Architecture

◆ BFAR

union { ... } BFAR

◆ BFARVALID

__IOM uint32_t BFARVALID

[15..15] BFAR Valid

◆ BFHFMIGN

__IOM uint32_t BFHFMIGN

[8..8] Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions

◆ bit [1/30]

struct { ... } bit

◆ bit [2/30]

struct { ... } bit

◆ bit [3/30]

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◆ bit [4/30]

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◆ bit [9/30]

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◆ bit [28/30]

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◆ bit [29/30]

struct { ... } bit

◆ bit [30/30]

struct { ... } bit

◆ BKPT

[1..1] BKPT

◆ BUSFAULTACT

__IOM uint32_t BUSFAULTACT

[1..1] BUSFAULTACT

◆ BUSFAULTENA

__IOM uint32_t BUSFAULTENA

[17..17] BUSFAULTENA

◆ BUSFAULTPENDED

__IOM uint32_t BUSFAULTPENDED

[14..14] BUSFAULTPENDED

◆ CCR

union { ... } CCR

◆ CFSR

union { ... } CFSR

◆ CLKSOURCE

__IOM uint32_t CLKSOURCE

[2..2] CLK Source

◆ COUNTFLAG

__IOM uint32_t COUNTFLAG

[16..16] Count Flag

◆ CP0

[1..0] Access Privileges for Coprocessor 0 (n= 0-7, 10, 11)

◆ CP1

[3..2] Access Privileges for Coprocessor 1 (n= 0-7, 10, 11)

◆ CP10

[21..20] Access Privileges for Coprocessor 10 (n= 0-7, 10, 11)

◆ CP11

[23..22] Access Privileges for Coprocessor 11 (n= 0-7, 10, 11)

◆ CP2

[5..4] Access Privileges for Coprocessor 2 (n= 0-7, 10, 11)

◆ CP3

[7..6] Access Privileges for Coprocessor 3 (n= 0-7, 10, 11)

◆ CP4

[9..8] Access Privileges for Coprocessor 4 (n= 0-7, 10, 11)

◆ CP5

[11..10] Access Privileges for Coprocessor 5 (n= 0-7, 10, 11)

◆ CP6

[13..12] Access Privileges for Coprocessor 6 (n= 0-7, 10, 11)

◆ CP7

[15..14] Access Privileges for Coprocessor 7 (n= 0-7, 10, 11)

◆ CPUID

union { ... } CPUID

◆ CURRENT

__IOM uint32_t CURRENT

[23..0] Current

◆ DACCVIOL

__IOM uint32_t DACCVIOL

[1..1] Data access violation flag

◆ DEBUGEVT

__IOM uint32_t DEBUGEVT

[31..31] Debug Event

◆ DFSR

union { ... } DFSR

◆ DIV_0_TRP

__IOM uint32_t DIV_0_TRP

[4..4] Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0

◆ DIVBYZERO

__IOM uint32_t DIVBYZERO

[25..25] Divide by Zero

◆ DWTTRAP

__IOM uint32_t DWTTRAP

[2..2] DWTTRAP

◆ ENABLE

__IOM uint32_t ENABLE

[0..0] Enable

◆ ENDIANNESS

__IM uint32_t ENDIANNESS

[15..15] Memory System Endianness

◆ EXTERNAL

__IOM uint32_t EXTERNAL

[4..4] External

◆ FORCED

__IOM uint32_t FORCED

[30..30] Forced

◆ HALTED

__IOM uint32_t HALTED

[0..0] HALTED

◆ HFSR

union { ... } HFSR

◆ IACCVIOL

__IOM uint32_t IACCVIOL

[0..0] Instruction access violation flag

◆ IBUSERR

__IOM uint32_t IBUSERR

[8..8] Instruction bus error

◆ ICSR

union { ... } ICSR

◆ ICT

union { ... } ICT

◆ IMPLEMENTER

__IM uint32_t IMPLEMENTER

[31..24] Implementer Code

◆ IMPRECISERR

__IOM uint32_t IMPRECISERR

[10..10] Imprecise data bus error

◆ Int_ADC1 [1/2]

__IOM uint32_t Int_ADC1

[3..3] Interrupt Set for ADC1

[3..3] Interrupt Clear for ADC1

[3..3] Interrupt Set Pending for ADC1

[3..3] Interrupt Clear Pending for ADC1

◆ Int_ADC1 [2/2]

__IM uint32_t Int_ADC1

[3..3] Interrupt Active for ADC1

◆ Int_ADC2 [1/2]

__IOM uint32_t Int_ADC2

[2..2] Interrupt Set for MU, ADC2

[2..2] Interrupt Clear for MU, ADC2

[2..2] Interrupt Set Pending for MU, ADC2

[2..2] Interrupt Clear Pending for MU, ADC2

◆ Int_ADC2 [2/2]

__IM uint32_t Int_ADC2

[2..2] Interrupt Active for MU, ADC2

◆ Int_BDRV [1/2]

__IOM uint32_t Int_BDRV

[14..14] Interrupt Set for Bridge Driver

[14..14] Interrupt Clear for Bridge Driver

[14..14] Interrupt Set Pending for Bridge Driver

[14..14] Interrupt Clear Pending for Bridge Driver

◆ Int_BDRV [2/2]

__IM uint32_t Int_BDRV

[14..14] Interrupt Active for Bridge Driver

◆ Int_CCU6SR0 [1/2]

__IOM uint32_t Int_CCU6SR0

[4..4] Interrupt Set for CCU6 SR0

[4..4] Interrupt Clear for CCU6 SR0

[4..4] Interrupt Set Pending for CCU6 SR0

[4..4] Interrupt Clear Pending for CCU6 SR0

◆ Int_CCU6SR0 [2/2]

__IM uint32_t Int_CCU6SR0

[4..4] Interrupt Active for CCU6 SR0

◆ Int_CCU6SR1 [1/2]

__IOM uint32_t Int_CCU6SR1

[5..5] Interrupt Set for CCU6 SR1

[5..5] Interrupt Clear for CCU6 SR1

[5..5] Interrupt Set Pending for CCU6 SR1

[5..5] Interrupt Clear Pending for CCU6 SR1

◆ Int_CCU6SR1 [2/2]

__IM uint32_t Int_CCU6SR1

[5..5] Interrupt Active for CCU6 SR1

◆ Int_CCU6SR2 [1/2]

__IOM uint32_t Int_CCU6SR2

[6..6] Interrupt Set for CCU6 SR2

[6..6] Interrupt Clear for CCU6 SR2

[6..6] Interrupt Set Pending for CCU6 SR2

[6..6] Interrupt Clear Pending for CCU6 SR2

◆ Int_CCU6SR2 [2/2]

__IM uint32_t Int_CCU6SR2

[6..6] Interrupt Active for CCU6 SR2

◆ Int_CCU6SR3 [1/2]

__IOM uint32_t Int_CCU6SR3

[7..7] Interrupt Set for CCU6 SR3

[7..7] Interrupt Clear for CCU6 SR3

[7..7] Interrupt Set Pending for CCU6 SR3

[7..7] Interrupt Clear Pending for CCU6 SR3

◆ Int_CCU6SR3 [2/2]

__IM uint32_t Int_CCU6SR3

[7..7] Interrupt Active for CCU6 SR3

◆ Int_DMA [1/2]

__IOM uint32_t Int_DMA

[15..15] Interrupt Set for DMA

[15..15] Interrupt Clr for DMA

[15..15] Interrupt Set Pend for DMA

[15..15] Interrupt Clr Pend for DMA

◆ Int_DMA [2/2]

__IM uint32_t Int_DMA

[15..15] Interrupt Active for DMA

◆ Int_EXINT0 [1/2]

__IOM uint32_t Int_EXINT0

[12..12] Interrupt Set for External Int 0

[12..12] Interrupt Clear for External Int 0

[12..12] Interrupt Set Pending for External Int 0

[12..12] Interrupt Clear Pending for External Int 0

◆ Int_EXINT0 [2/2]

__IM uint32_t Int_EXINT0

[12..12] Interrupt Active for External Int 0

◆ Int_EXINT1 [1/2]

__IOM uint32_t Int_EXINT1

[13..13] Interrupt Set for External Int 1

[13..13] Interrupt Clear for External Int 1

[13..13] Interrupt Set Pending for External Int 1

[13..13] Interrupt Clear Pending for External Int 1

◆ Int_EXINT1 [2/2]

__IM uint32_t Int_EXINT1

[13..13] Interrupt Active for External Int 1

◆ Int_GPT1 [1/2]

__IOM uint32_t Int_GPT1

[0..0] Interrupt Set for GPT1

[0..0] Interrupt Clear for GPT1

[0..0] Interrupt Set Pending for GPT1

[0..0] Interrupt Clear Pending for GPT1

◆ Int_GPT1 [2/2]

__IM uint32_t Int_GPT1

[0..0] Interrupt Active for GPT1

◆ Int_GPT2 [1/2]

__IOM uint32_t Int_GPT2

[1..1] Interrupt Set for GPT2

[1..1] Interrupt Clear for GPT2

[1..1] Interrupt Set Pending for GPT2

[1..1] Interrupt Clear Pending for GPT2

◆ Int_GPT2 [2/2]

__IM uint32_t Int_GPT2

[1..1] Interrupt Active for GPT2

◆ Int_SSC1 [1/2]

__IOM uint32_t Int_SSC1

[8..8] Interrupt Set for SSC1

[8..8] Interrupt Clear for SSC1

[8..8] Interrupt Set Pending for SSC1

[8..8] Interrupt Clear Pending for SSC1

◆ Int_SSC1 [2/2]

__IM uint32_t Int_SSC1

[8..8] Interrupt Active for SSC1

◆ Int_SSC2 [1/2]

__IOM uint32_t Int_SSC2

[9..9] Interrupt Set for SSC2

[9..9] Interrupt Clear for SSC2

[9..9] Interrupt Set Pending for SSC2

[9..9] Interrupt Clear Pending for SSC2

◆ Int_SSC2 [2/2]

__IM uint32_t Int_SSC2

[9..9] Interrupt Active for SSC2

◆ Int_UART1 [1/2]

__IOM uint32_t Int_UART1

[10..10] Interrupt Set for UART1

[10..10] Interrupt Clear for UART1

[10..10] Interrupt Set Pending for UART1

[10..10] Interrupt Clear Pending for UART1

◆ Int_UART1 [2/2]

__IM uint32_t Int_UART1

[10..10] Interrupt Active for UART1

◆ Int_UART2 [1/2]

__IOM uint32_t Int_UART2

[11..11] Interrupt Set for UART2

[11..11] Interrupt Clear for UART2

[11..11] Interrupt Set Pending for UART2

[11..11] Interrupt Clear Pending for UART2

◆ Int_UART2 [2/2]

__IM uint32_t Int_UART2

[11..11] Interrupt Active for UART2

◆ INTLINESNUM

__IM uint32_t INTLINESNUM

[4..0] Interrupt Lines

◆ INVPC

__IOM uint32_t INVPC

[18..18] Invalid PC load UsageFault

◆ INVSTATE

__IOM uint32_t INVSTATE

[17..17] Invalid state UsageFault

◆ ISRPENDING

__IM uint32_t ISRPENDING

[22..22] Interrupt pending flag. Excludes NMI and Faults

◆ ISRPREEMPT

__IM uint32_t ISRPREEMPT

[23..23] ISRPREEMPT

◆ MEMFAULTACT

__IOM uint32_t MEMFAULTACT

[0..0] MEMFAULTACT

◆ MEMFAULTENA

__IOM uint32_t MEMFAULTENA

[16..16] MEMFAULTENA

◆ MEMFAULTPENDED

__IOM uint32_t MEMFAULTPENDED

[13..13] MEMFAULTPENDED

◆ MMARVALID

__IOM uint32_t MMARVALID

[7..7] MemManage Fault Address Register (MMFAR) valid flag

◆ MMFAR

union { ... } MMFAR

◆ MONITORACT

__IOM uint32_t MONITORACT

[8..8] MONITORACT

◆ MSTERR

__IOM uint32_t MSTERR

[4..4] MemManage fault on stacking for exception entry

◆ MUNSTKERR

__IOM uint32_t MUNSTKERR

[3..3] MemManage fault on unstacking for a return from exception

◆ NMIPENDSET

__IOM uint32_t NMIPENDSET

[31..31] NMI PendSet

◆ NOCP

[19..19] No coprocessor UsageFault

◆ NONBASETHRDENA

__IOM uint32_t NONBASETHRDENA

[0..0] Indicates how the processor enters Thread mode

◆ NOREF

__IM uint32_t NOREF

[31..31] No Reference Clock

◆ NVIC_IABR0

union { ... } NVIC_IABR0

◆ NVIC_ICER0

union { ... } NVIC_ICER0

◆ NVIC_ICPR0

union { ... } NVIC_ICPR0

◆ NVIC_IPR0

union { ... } NVIC_IPR0

◆ NVIC_IPR1

union { ... } NVIC_IPR1

◆ NVIC_IPR2

union { ... } NVIC_IPR2

◆ NVIC_IPR3

union { ... } NVIC_IPR3

◆ NVIC_ISER0

union { ... } NVIC_ISER0

◆ NVIC_ISPR0

union { ... } NVIC_ISPR0

◆ PARTNO

__IM uint32_t PARTNO

[15..4] Part Number

◆ PENDSTCLR

__OM uint32_t PENDSTCLR

[25..25] SysTick exception clear-pending bit

◆ PENDSTSET

__IOM uint32_t PENDSTSET

[26..26] SysTick exception set-pending bit

◆ PENDSVACT

__IOM uint32_t PENDSVACT

[10..10] PENDSVACT

◆ PENDSVCLR

__OM uint32_t PENDSVCLR

[27..27] PendSV clear-pending bit

◆ PENDSVSET

__IOM uint32_t PENDSVSET

[28..28] PendSV set-pending bit

◆ PRECISERR

__IOM uint32_t PRECISERR

[9..9] Precise data bus error

◆ PRI_10

__IOM uint32_t PRI_10

[23..16] Reserved for Priority of System Handler 10

◆ PRI_11

__IOM uint32_t PRI_11

[31..24] Priority of System Handler 11, SVCall

◆ PRI_12

__IOM uint32_t PRI_12

[7..0] Priority of System Handler 12, DebugMonitor

◆ PRI_13

__IOM uint32_t PRI_13

[15..8] Reserved for Priority of System Handler 13

◆ PRI_14

__IOM uint32_t PRI_14

[23..16] Priority of System Handler 14, PendSV

◆ PRI_15

__IOM uint32_t PRI_15

[31..24] Priority of System Handler 15, SysTick

◆ PRI_4

__IOM uint32_t PRI_4

[7..0] Priority of System Handler 4, MemManage

◆ PRI_5

__IOM uint32_t PRI_5

[15..8] Priority of System Handler 5, BusFault

◆ PRI_6

__IOM uint32_t PRI_6

[23..16] Priority of System Handler 6, UsageFault

◆ PRI_7

__IOM uint32_t PRI_7

[31..24] Reserved for Priority of System Handler 7

◆ PRI_8

__IOM uint32_t PRI_8

[7..0] Reserved for Priority of System Handler 8

◆ PRI_9

__IOM uint32_t PRI_9

[15..8] Reserved for Priority of System Handler 9

◆ PRI_ADC1

__IOM uint32_t PRI_ADC1

[31..24] Priority for ADC1

◆ PRI_ADC2

__IOM uint32_t PRI_ADC2

[23..16] Priority for MU, ADC2

◆ PRI_BDRV

__IOM uint32_t PRI_BDRV

[23..16] Priority for Bridge Driver

◆ PRI_CCU6SR0

__IOM uint32_t PRI_CCU6SR0

[7..0] Priority for CCU6 SR0

◆ PRI_CCU6SR1

__IOM uint32_t PRI_CCU6SR1

[15..8] Priority for CCU6 SR1

◆ PRI_CCU6SR2

__IOM uint32_t PRI_CCU6SR2

[23..16] Priority for CCU6 SR2

◆ PRI_CCU6SR3

__IOM uint32_t PRI_CCU6SR3

[31..24] Priority for CCU6 SR3

◆ PRI_DMA

__IOM uint32_t PRI_DMA

[31..24] Priority for DMA

◆ PRI_EXINT0

__IOM uint32_t PRI_EXINT0

[7..0] Priority for Ext. Int 0

◆ PRI_EXINT1

__IOM uint32_t PRI_EXINT1

[15..8] Priority for Ext. Int 1

◆ PRI_GPT1

__IOM uint32_t PRI_GPT1

[7..0] Priority for GPT1

◆ PRI_GPT2

__IOM uint32_t PRI_GPT2

[15..8] Priority for GPT2

◆ PRI_SSC1

__IOM uint32_t PRI_SSC1

[7..0] Priority for SSC1

◆ PRI_SSC2

__IOM uint32_t PRI_SSC2

[15..8] Priority for SSC2

◆ PRI_UART1

__IOM uint32_t PRI_UART1

[23..16] Priority for UART1

◆ PRI_UART2

__IOM uint32_t PRI_UART2

[31..24] Priority for UART2

◆ PRIGROUP

__IOM uint32_t PRIGROUP

[10..8] Priority Grouping

◆ reg

(@ 0x00000004) Interrupt Controller Type

(@ 0x00000010) SysTick Control and Status

(@ 0x00000014) SysTick Reload Value

(@ 0x00000018) SysTick Current Value

(@ 0x0000001C) SysTick Calibration Value

(@ 0x00000100) Interrupt Set-Enable

(@ 0x00000180) Interrupt Clear-Enable

(@ 0x00000200) Interrupt Set-Pending

(@ 0x00000280) Interrupt Clear-Pending

(@ 0x00000300) Active Bit Register Interrupt Active Flags

(@ 0x00000400) Interrupt Priority

(@ 0x00000404) Interrupt Priority

(@ 0x00000408) Interrupt Priority

(@ 0x0000040C) Interrupt Priority

(@ 0x00000D00) CPU ID Base Register

(@ 0x00000D04) Interrupt Control State Register

(@ 0x00000D08) Vector Table Offset Register

(@ 0x00000D0C) Application Interrupt/Reset Control Register

(@ 0x00000D10) System Control Register

(@ 0x00000D14) Configuration Control Register

(@ 0x00000D18) System Handler Priority Register 1

(@ 0x00000D1C) System Handler Priority Register 2

(@ 0x00000D20) System Handler Priority Register 3

(@ 0x00000D24) System Handler Control and State Register

(@ 0x00000D28) Configurable Fault Status Register

(@ 0x00000D2C) Hard Fault Status Register

(@ 0x00000D30) Debug Fault Status Register

(@ 0x00000D34) MemManage Fault Status Register

(@ 0x00000D38) Bus Fault Status Register

(@ 0x00000D3C) Auxiliary Fault Status Register

◆ RELOAD

__IOM uint32_t RELOAD

[23..0] Reload

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1[2]

◆ RESERVED2

__IM uint32_t RESERVED2[56]

◆ RESERVED3

__IM uint32_t RESERVED3[31]

◆ RESERVED4

__IM uint32_t RESERVED4[31]

◆ RESERVED5

__IM uint32_t RESERVED5[31]

◆ RESERVED6

__IM uint32_t RESERVED6[31]

◆ RESERVED7

__IM uint32_t RESERVED7[63]

◆ RESERVED8

__IM uint32_t RESERVED8[572]

◆ RETTOBASE

__IM uint32_t RETTOBASE

[11..11] RETTOBASE

◆ REVISION

__IM uint32_t REVISION

[3..0] Revision Number

◆ SCR

union { ... } SCR

◆ SEVONPEND

__IOM uint32_t SEVONPEND

[4..4] SEVONPEND

◆ SHCSR

union { ... } SHCSR

◆ SHPR1

union { ... } SHPR1

◆ SHPR2

union { ... } SHPR2

◆ SHPR3

union { ... } SHPR3

◆ SKEW

__IM uint32_t SKEW

[30..30] Skew

◆ SLEEPDEEP

__IOM uint32_t SLEEPDEEP

[2..2] Sleep Deep

◆ SLEEPONEXIT

__IOM uint32_t SLEEPONEXIT

[1..1] Sleep on Exit

◆ STKALIGN

__IOM uint32_t STKALIGN

[9..9] stack alignment

◆ STKERR

__IOM uint32_t STKERR

[12..12] BusFault on stacking for exception entry

◆ SVCALLACT

__IOM uint32_t SVCALLACT

[7..7] SVCALLACT

◆ SVCALLPENDED

__IOM uint32_t SVCALLPENDED

[15..15] SVCALLPENDED

◆ SYSRESETREQ

__IOM uint32_t SYSRESETREQ

[2..2] System Reset Request

◆ SYSTICK_CAL

union { ... } SYSTICK_CAL

◆ SYSTICK_CS

union { ... } SYSTICK_CS

◆ SYSTICK_CUR

union { ... } SYSTICK_CUR

◆ SYSTICK_RL

union { ... } SYSTICK_RL

◆ SYSTICKACT

__IOM uint32_t SYSTICKACT

[11..11] SYSTICKACT

◆ TBLOFF

__IOM uint32_t TBLOFF

[31..7] Vector Table Offset

◆ TENMS

__IM uint32_t TENMS

[23..0] Tenms

◆ TICKINT

__IOM uint32_t TICKINT

[1..1] Enables SysTick exception request

◆ uint32_t

__IM uint32_t

◆ UNALIGN_TRP

__IOM uint32_t UNALIGN_TRP

[3..3] Enables unaligned access traps

◆ UNALIGNED

__IOM uint32_t UNALIGNED

[24..24] Unaligned access UsageFault

◆ UNDEFINSTR

__IOM uint32_t UNDEFINSTR

[16..16] Undefined instruction UsageFault

◆ UNSTKERR

__IOM uint32_t UNSTKERR

[11..11] BusFault on unstacking for a return from exception

◆ USERSETMPEND

__IOM uint32_t USERSETMPEND

[1..1] Enables unprivileged software access to the STIR

◆ USGFAULTACT

__IOM uint32_t USGFAULTACT

[3..3] USGFAULTACT

◆ USGFAULTENA

__IOM uint32_t USGFAULTENA

[18..18] USGFAULTENA

◆ USGFAULTPENDED

__IOM uint32_t USGFAULTPENDED

[12..12] USGFAULTPENDED

◆ VARIANT

__IM uint32_t VARIANT

[23..20] Variant Number

◆ VCATCH

__IOM uint32_t VCATCH

[3..3] Vector Catch

◆ VECTACTIVE

__IM uint32_t VECTACTIVE

[8..0] Active ISR number field

◆ VECTCLRACTIVE

__IOM uint32_t VECTCLRACTIVE

[1..1] VECTCLRACTIVE for debug only

◆ VECTKEY

__IOM uint32_t VECTKEY

[31..16] Vector Key

◆ VECTPENDING

__IM uint32_t VECTPENDING

[20..12] Pending ISR number field

◆ VECTRESET

__IOM uint32_t VECTRESET

[0..0] VECTRESET for debug only

◆ VECTTBL

__IOM uint32_t VECTTBL

[1..1] VECTTBL

◆ VTOR

union { ... } VTOR

The documentation for this struct was generated from the following file: