TLE986x Device Family SDK
int.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2015, Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** AP Adriano Pereira **
44 ** JO Julia Ott **
45 ** BG Blandine Guillot **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.1.0: 2014-05-11, DM: Initial version **
52 ** V0.1.1: 2015-02-10, DM: Individual header file added **
53 ** V0.1.2: 2015-09-17, DM: SYS_IRQ_CTRL register init added **
54 ** V0.1.3: 2015-11-25, DM: SCU_DMAIENx added, SCU_DMAIRCx clear added **
55 ** V0.1.4: 2016-10-10, DM: Interrupt Enable/Disable macros added **
56 ** CPU->SHPR3 init (SysTick Prio) added **
57 ** V0.1.5: 2017-10-05, DM: MISRA 2012 compliance, the following PC-Lint **
58 ** rules are globally deactivated: **
59 ** - Info 793: ANSI/ISO limit of 6 'significant **
60 ** characters in an external identifier **
61 ** - Info 835: A zero has been given as right **
62 ** argument to operator **
63 ** - Info 845: The left argument to operator '&' **
64 ** is certain to be 0 **
65 ** V0.1.6: 2018-03-20, DM: #define NMI_xxx macros modified to meet MISRA **
66 ** 2012 **
67 ** #define EXINTx_xxx macros modified to meet MISRA **
68 ** 2012 **
69 ** Replaced macros by INLINE functions **
70 ** Replaced register accesses within functions by **
71 ** function calls **
72 ** Replaced __STATIC_INLINE by INLINE **
73 ** V0.1.7: 2018-07-04, AP: Added functions to enable/disable NVIC nodes **
74 ** V0.1.8: 2018-11-27, JO: Doxygen update, moved revision history from **
75 ** int.c to int.h **
76 ** V0.1.9: 2019-04-18, JO: Corrected NVIC_NodeXYZ_En/Dis functions **
77 ** V0.2.0: 2019-10-17, BG: Bridge Driver interrupts enabled for Config **
78 ** Wizard 2 **
79 ** V0.2.1: 2020-02-28, BG: Updated revision history format **
80 *******************************************************************************/
81 
82 #ifndef INT_H
83 #define INT_H
84 
85 /*******************************************************************************
86 ** Includes **
87 *******************************************************************************/
88 #include "tle986x.h"
89 #include "types.h"
90 #include "tle_variants.h"
91 #include "sfr_access.h"
92 
93 /*******************************************************************************
94 ** Global Macro Definitions **
95 *******************************************************************************/
97 #define NMI_WDT ((uint8)1u << 0u)
98 
99 #define NMI_PLL ((uint8)1u << 1u)
100 
101 #define NMI_NVM ((uint8)1u << 2u)
102 
103 #define NMI_OT ((uint8)1u << 3u)
104 
105 #define NMI_OWT ((uint8)1u << 4u)
106 
107 #define NMI_MAP ((uint8)1u << 5u)
108 
109 #define NMI_ECC ((uint8)1u << 6u)
110 
111 #define NMI_SUP ((uint8)1u << 7u)
112 
113 #define SCU_EXICON0_EXINT0_RE_Pos (0UL)
114 
115 #define SCU_EXICON0_EXINT0_RE_Msk (0x01UL)
116 
117 #define SCU_EXICON0_EXINT0_FE_Pos (1UL)
118 
119 #define SCU_EXICON0_EXINT0_FE_Msk (0x02UL)
120 
121 #define SCU_EXICON0_EXINT1_RE_Pos (2UL)
122 
123 #define SCU_EXICON0_EXINT1_RE_Msk (0x04UL)
124 
125 #define SCU_EXICON0_EXINT1_FE_Pos (3UL)
126 
127 #define SCU_EXICON0_EXINT1_FE_Msk (0x08UL)
128 
129 #define SCU_EXICON0_EXINT2_RE_Pos (4UL)
130 
131 #define SCU_EXICON0_EXINT2_RE_Msk (0x10UL)
132 
133 #define SCU_EXICON0_EXINT2_FE_Pos (5UL)
134 
135 #define SCU_EXICON0_EXINT2_FE_Msk (0x20UL)
136 
137 #define SCU_NMISR_Pos (0UL)
138 
139 #define SCU_NMISR_Msk (0xFFUL)
140 
141 #define SCU_NMICLR_Pos (0UL)
142 
143 #define SCU_NMICLR_Msk (0xFFUL)
144 
145 
146 /******************************************************************************
147 ** INLINE Function Definitions **
148 *******************************************************************************/
161 INLINE void Global_Int_En(void)
162 {
164 }
165 
178 INLINE void Global_Int_Dis(void)
179 {
181 }
182 
205 {
207 }
208 
232 {
234 }
235 
258 {
260 }
261 
285 {
287 }
288 
305 {
307 }
308 
327 {
329 }
330 
349 {
351 }
352 
371 {
373 }
374 
394 {
396 }
397 
416 {
418 }
419 
439 {
441 }
442 
461 {
463 }
464 
484 {
486 }
487 
506 {
508 }
509 
529 {
531 }
532 
551 {
553 }
554 
574 {
576 }
577 
596 {
598 }
599 
619 {
621 }
622 
641 {
643 }
644 
663 {
665 }
666 
685 {
687 }
688 
707 {
709 }
710 
729 {
731 }
732 
751 {
753 }
754 
772 INLINE void NMI_WDT_Int_En(void)
773 {
775 }
776 
795 INLINE void NMI_WDT_Int_Dis(void)
796 {
798 }
799 
817 INLINE void NMI_PLL_Int_En(void)
818 {
820 }
821 
840 INLINE void NMI_PLL_Int_Dis(void)
841 {
843 }
844 
862 INLINE void NMI_NVM_Int_En(void)
863 {
865 }
866 
885 INLINE void NMI_NVM_Int_Dis(void)
886 {
888 }
889 
911 INLINE void NMI_ECC_Int_En(void)
912 {
914 }
915 
938 INLINE void NMI_ECC_Int_Dis(void)
939 {
941 }
942 
960 INLINE void NMI_MAP_Int_En(void)
961 {
963 }
964 
983 INLINE void NMI_MAP_Int_Dis(void)
984 {
986 }
987 
1004 INLINE void NMI_SUP_Int_En(void)
1005 {
1007 }
1008 
1026 INLINE void NMI_SUP_Int_Dis(void)
1027 {
1029 }
1030 
1048 INLINE void NMI_OWD_Int_En(void)
1049 {
1051 }
1052 
1071 INLINE void NMI_OWD_Int_Dis(void)
1072 {
1074 }
1075 
1092 INLINE void NMI_OT_Int_En(void)
1093 {
1095 }
1096 
1114 INLINE void NMI_OT_Int_Dis(void)
1115 {
1117 }
1118 
1136 INLINE void NMI_WDT_Int_Clr(void)
1137 {
1139 }
1140 
1158 INLINE void NMI_PLL_Int_Clr(void)
1159 {
1161 }
1162 
1180 INLINE void NMI_NVM_Int_Clr(void)
1181 {
1183 }
1184 
1201 INLINE void NMI_OT_Int_Clr(void)
1202 {
1204 }
1205 
1223 INLINE void NMI_OWD_Int_Clr(void)
1224 {
1226 }
1227 
1245 INLINE void NMI_MAP_Int_Clr(void)
1246 {
1248 }
1249 
1266 INLINE void NMI_ECC_Int_Clr(void)
1267 {
1269 }
1270 
1287 INLINE void NMI_SUP_Int_Clr(void)
1288 {
1290 }
1296 INLINE void NVIC_Node0_En(void)
1297 {
1299 }
1305 INLINE void NVIC_Node0_Dis(void)
1306 {
1308 }
1314 INLINE void NVIC_Node1_En(void)
1315 {
1317 }
1323 INLINE void NVIC_Node1_Dis(void)
1324 {
1326 }
1332 INLINE void NVIC_Node2_En(void)
1333 {
1335 }
1341 INLINE void NVIC_Node2_Dis(void)
1342 {
1344 }
1350 INLINE void NVIC_Node3_En(void)
1351 {
1353 }
1359 INLINE void NVIC_Node3_Dis(void)
1360 {
1362 }
1368 INLINE void NVIC_Node4_En(void)
1369 {
1371 }
1377 INLINE void NVIC_Node4_Dis(void)
1378 {
1380 }
1386 INLINE void NVIC_Node5_En(void)
1387 {
1389 }
1395 INLINE void NVIC_Node5_Dis(void)
1396 {
1398 }
1404 INLINE void NVIC_Node6_En(void)
1405 {
1407 }
1413 INLINE void NVIC_Node6_Dis(void)
1414 {
1416 }
1422 INLINE void NVIC_Node7_En(void)
1423 {
1425 }
1431 INLINE void NVIC_Node7_Dis(void)
1432 {
1434 }
1440 INLINE void NVIC_Node8_En(void)
1441 {
1443 }
1449 INLINE void NVIC_Node8_Dis(void)
1450 {
1452 }
1458 INLINE void NVIC_Node9_En(void)
1459 {
1461 }
1467 INLINE void NVIC_Node9_Dis(void)
1468 {
1470 }
1476 INLINE void NVIC_Node10_En(void)
1477 {
1479 }
1485 INLINE void NVIC_Node10_Dis(void)
1486 {
1488 }
1494 INLINE void NVIC_Node11_En(void)
1495 {
1497 }
1498 
1504 INLINE void NVIC_Node11_Dis(void)
1505 {
1507 }
1508 
1514 INLINE void NVIC_Node12_En(void)
1515 {
1517 }
1523 INLINE void NVIC_Node12_Dis(void)
1524 {
1526 }
1532 INLINE void NVIC_Node13_En(void)
1533 {
1535 }
1541 INLINE void NVIC_Node13_Dis(void)
1542 {
1544 }
1550 INLINE void NVIC_Node14_En(void)
1551 {
1553 }
1559 INLINE void NVIC_Node14_Dis(void)
1560 {
1562 }
1568 INLINE void NVIC_Node15_En(void)
1569 {
1571 }
1577 INLINE void NVIC_Node15_Dis(void)
1578 {
1580 }
1581 
1582 #if (UC_SERIES == TLE987)
1583 
1600 INLINE void BEMF_Phase_U_Hi_Int_En(void)
1601 {
1602  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Msk, 1u);
1603 }
1604 
1623 INLINE void BEMF_Phase_U_Hi_Int_Dis(void)
1624 {
1625  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCHI_IE_Msk, 0u);
1626 }
1627 
1645 INLINE void BEMF_Phase_U_Lo_Int_En(void)
1646 {
1647  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Msk, 1u);
1648 }
1649 
1668 INLINE void BEMF_Phase_U_Lo_Int_Dis(void)
1669 {
1670  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHU_ZCLOW_IE_Msk, 0u);
1671 }
1672 
1690 INLINE void BEMF_Phase_V_Hi_Int_En(void)
1691 {
1692  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Msk, 1u);
1693 }
1694 
1713 INLINE void BEMF_Phase_V_Hi_Int_Dis(void)
1714 {
1715  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCHI_IE_Msk, 0u);
1716 }
1717 
1735 INLINE void BEMF_Phase_V_Lo_Int_En(void)
1736 {
1737  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Msk, 1u);
1738 }
1739 
1758 INLINE void BEMF_Phase_V_Lo_Int_Dis(void)
1759 {
1760  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHV_ZCLOW_IE_Msk, 0u);
1761 }
1762 
1780 INLINE void BEMF_Phase_W_Hi_Int_En(void)
1781 {
1782  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Msk, 1u);
1783 }
1784 
1803 INLINE void BEMF_Phase_W_Hi_Int_Dis(void)
1804 {
1805  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCHI_IE_Msk, 0u);
1806 }
1807 
1825 INLINE void BEMF_Phase_W_Lo_Int_En(void)
1826 {
1827  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Msk, 1u);
1828 }
1829 
1848 INLINE void BEMF_Phase_W_Lo_Int_Dis(void)
1849 {
1850  Field_Mod32(&SCUPM->SYS_IRQ_CTRL.reg, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Pos, (uint32)SCUPM_SYS_IRQ_CTRL_PHW_ZCLOW_IE_Msk, 0u);
1851 }
1852 
1870 INLINE void BEMF_Phase_U_Hi_Int_Clr(void)
1871 {
1872  Field_Wrt32(&SCUPM->SYS_ISCLR.reg, (uint32)SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Pos, (uint32)SCUPM_SYS_ISCLR_PHU_ZCHI_SCLR_Msk, 1u);
1873 }
1874 
1892 INLINE void BEMF_Phase_U_Lo_Int_Clr(void)
1893 {
1894  Field_Wrt32(&SCUPM->SYS_ISCLR.reg, (uint32)SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Pos, (uint32)SCUPM_SYS_ISCLR_PHU_ZCLOW_SCLR_Msk, 1u);
1895 }
1896 
1914 INLINE void BEMF_Phase_V_Hi_Int_Clr(void)
1915 {
1916  Field_Wrt32(&SCUPM->SYS_ISCLR.reg, (uint32)SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Pos, (uint32)SCUPM_SYS_ISCLR_PHV_ZCHI_SCLR_Msk, 1u);
1917 }
1918 
1936 INLINE void BEMF_Phase_V_Lo_Int_Clr(void)
1937 {
1938  Field_Wrt32(&SCUPM->SYS_ISCLR.reg, (uint32)SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Pos, (uint32)SCUPM_SYS_ISCLR_PHV_ZCLOW_SCLR_Msk, 1u);
1939 }
1940 
1958 INLINE void BEMF_Phase_W_Hi_Int_Clr(void)
1959 {
1960  Field_Wrt32(&SCUPM->SYS_ISCLR.reg, (uint32)SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Pos, (uint32)SCUPM_SYS_ISCLR_PHW_ZCHI_SCLR_Msk, 1u);
1961 }
1962 
1980 INLINE void BEMF_Phase_W_Lo_Int_Clr(void)
1981 {
1982  Field_Wrt32(&SCUPM->SYS_ISCLR.reg, (uint32)SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Pos, (uint32)SCUPM_SYS_ISCLR_PHW_ZCLOW_SCLR_Msk, 1u);
1983 }
1984 #endif /* (UC_SERIES = TLE987) */
1985 
1986 /*******************************************************************************
1987 ** Global Function Declarations **
1988 *******************************************************************************/
1990 INLINE void INT_Clr_NMI_Status(uint8 Flags);
1991 INLINE void INT_Enable_Global_Int(void);
1992 INLINE void INT_Disable_Global_Int(void);
1993 
1998 void INT_Init(void);
1999 
2000 /*******************************************************************************
2001 ** Global Inline Function Definitions **
2002 *******************************************************************************/
2020 {
2021  return u8_Field_Rd8(&SCU->NMISR.reg, (uint8)SCU_NMISR_Pos, (uint8)SCU_NMISR_Msk);
2022 }
2023 
2038 INLINE void INT_Clr_NMI_Status(uint8 Flags)
2039 {
2040  Field_Wrt8(&SCU->NMICLR.reg, (uint8)SCU_NMICLR_Pos, (uint8)SCU_NMICLR_Msk, Flags);
2041 }
2042 
2055 INLINE void INT_Enable_Global_Int(void)
2056 {
2057  Global_Int_En();
2058 }
2059 
2072 INLINE void INT_Disable_Global_Int(void)
2073 {
2074  Global_Int_Dis();
2075 }
2076 
2077 #endif
ECC_NVM_DoubleBit_Int_Dis
INLINE void ECC_NVM_DoubleBit_Int_Dis(void)
disables NVM Double Bit ECC Error Interrupt.
Definition: int.h:279
EXINT2_Rising_Edge_Int_Clr
INLINE void EXINT2_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT2.
Definition: int.h:723
CPU_NVIC_ISER0_Int_GPT1_Pos
#define CPU_NVIC_ISER0_Int_GPT1_Pos
Definition: tle986x.h:7646
CPU_NVIC_ICER0_Int_CCU6SR1_Pos
#define CPU_NVIC_ICER0_Int_CCU6SR1_Pos
Definition: tle986x.h:7534
CPU_NVIC_ISER0_Int_CCU6SR0_Msk
#define CPU_NVIC_ISER0_Int_CCU6SR0_Msk
Definition: tle986x.h:7639
CPU_NVIC_ICER0_Int_GPT1_Msk
#define CPU_NVIC_ICER0_Int_GPT1_Msk
Definition: tle986x.h:7545
SCU_EXICON0_EXINT1_FE_Msk
#define SCU_EXICON0_EXINT1_FE_Msk
External Interrupt 1 Falling Edge Bit Mask.
Definition: int.h:123
EXINT1_Falling_Edge_Int_En
INLINE void EXINT1_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT1.
Definition: int.h:500
ECC_RAM_DoubleBit_Int_En
INLINE void ECC_RAM_DoubleBit_Int_En(void)
enables RAM Double Bit ECC Error Interrupt.
Definition: int.h:199
EXINT1_Falling_Edge_Int_Clr
INLINE void EXINT1_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT1.
Definition: int.h:701
EXINT1_Falling_Edge_Int_Dis
INLINE void EXINT1_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT1.
Definition: int.h:523
SCU_NMICLR_NMIOTC_Msk
#define SCU_NMICLR_NMIOTC_Msk
Definition: tle986x.h:9071
CPU_NVIC_ISER0_Int_BDRV_Pos
#define CPU_NVIC_ISER0_Int_BDRV_Pos
Definition: tle986x.h:7618
SCU_EDCSCLR_RSBEC_Pos
#define SCU_EDCSCLR_RSBEC_Pos
Definition: tle986x.h:8779
SCU_NMICON_NMIPLL_Pos
#define SCU_NMICON_NMIPLL_Pos
Definition: tle986x.h:9091
INT_Disable_Global_Int
INLINE void INT_Disable_Global_Int(void)
disables the global interrupt IEN0.EA
Definition: int.h:2065
NVIC_Node6_Dis
INLINE void NVIC_Node6_Dis(void)
Disables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1408
CPU_NVIC_ICER0_Int_EXINT0_Msk
#define CPU_NVIC_ICER0_Int_EXINT0_Msk
Definition: tle986x.h:7521
SCU_IRCON0CLR_EXINT1RC_Pos
#define SCU_IRCON0CLR_EXINT1RC_Pos
Definition: tle986x.h:8883
types.h
General type declarations.
CPU_NVIC_ISER0_Int_CCU6SR2_Msk
#define CPU_NVIC_ISER0_Int_CCU6SR2_Msk
Definition: tle986x.h:7635
CPU_NVIC_ISER0_Int_UART2_Pos
#define CPU_NVIC_ISER0_Int_UART2_Pos
Definition: tle986x.h:7624
SCU_EDCCON_NVMIE_Msk
#define SCU_EDCCON_NVMIE_Msk
Definition: tle986x.h:8775
SCU_NMICON_NMINVM_Pos
#define SCU_NMICON_NMINVM_Pos
Definition: tle986x.h:9089
CPU_NVIC_ICER0_Int_UART1_Msk
#define CPU_NVIC_ICER0_Int_UART1_Msk
Definition: tle986x.h:7525
CPU_NVIC_ICER0_Int_UART1_Pos
#define CPU_NVIC_ICER0_Int_UART1_Pos
Definition: tle986x.h:7524
SCU_NMICON_NMIOWD_Msk
#define SCU_NMICON_NMIOWD_Msk
Definition: tle986x.h:9086
SCU_NMICON_NMISUP_Msk
#define SCU_NMICON_NMISUP_Msk
Definition: tle986x.h:9080
SCU_NMICLR_NMINVMC_Msk
#define SCU_NMICLR_NMINVMC_Msk
Definition: tle986x.h:9073
NVIC_Node0_En
INLINE void NVIC_Node0_En(void)
Enables the NVIC node 0 (Int_GPT1)
Definition: int.h:1291
Global_Int_En
INLINE void Global_Int_En(void)
enables Global Interrupt (Pending interrupt requests are not blocked from the core).
Definition: int.h:156
NVIC_Node6_En
INLINE void NVIC_Node6_En(void)
Enables the NVIC node 6 (Int_CCU6SR2)
Definition: int.h:1399
CPU_NVIC_ICER0_Int_CCU6SR3_Pos
#define CPU_NVIC_ICER0_Int_CCU6SR3_Pos
Definition: tle986x.h:7530
CPU_NVIC_ISER0_Int_EXINT0_Pos
#define CPU_NVIC_ISER0_Int_EXINT0_Pos
Definition: tle986x.h:7622
SCU_NMISR_Msk
#define SCU_NMISR_Msk
NMI Status Read Bit Mask.
Definition: int.h:135
CPU_NVIC_ISER0_Int_UART1_Msk
#define CPU_NVIC_ISER0_Int_UART1_Msk
Definition: tle986x.h:7627
CPU_NVIC_ICER0_Int_DMA_Msk
#define CPU_NVIC_ICER0_Int_DMA_Msk
Definition: tle986x.h:7515
SCU_NMISR_Pos
#define SCU_NMISR_Pos
NMI Status Read Bit Position.
Definition: int.h:133
CPU_NVIC_ISER0_Int_EXINT1_Pos
#define CPU_NVIC_ISER0_Int_EXINT1_Pos
Definition: tle986x.h:7620
ECC_RAM_SingleBit_Int_Clr
INLINE void ECC_RAM_SingleBit_Int_Clr(void)
clears RAM Single Bit Error Status.
Definition: int.h:299
CPU_NVIC_ISER0_Int_DMA_Pos
#define CPU_NVIC_ISER0_Int_DMA_Pos
Definition: tle986x.h:7616
CPU_NVIC_ISER0_Int_ADC2_Msk
#define CPU_NVIC_ISER0_Int_ADC2_Msk
Definition: tle986x.h:7643
CPU_NVIC_ISER0_Int_SSC1_Msk
#define CPU_NVIC_ISER0_Int_SSC1_Msk
Definition: tle986x.h:7631
CPU_NVIC_ICER0_Int_ADC1_Msk
#define CPU_NVIC_ICER0_Int_ADC1_Msk
Definition: tle986x.h:7539
SCU_NMICLR_NMIECCC_Pos
#define SCU_NMICLR_NMIECCC_Pos
Definition: tle986x.h:9064
NVIC_Node2_En
INLINE void NVIC_Node2_En(void)
Enables the NVIC node 2 (Int_ADC2)
Definition: int.h:1327
NVIC_Node4_En
INLINE void NVIC_Node4_En(void)
Enables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1363
SCU_NMICLR_NMIPLLC_Pos
#define SCU_NMICLR_NMIPLLC_Pos
Definition: tle986x.h:9074
SCU_NMICON_NMIECC_Msk
#define SCU_NMICON_NMIECC_Msk
Definition: tle986x.h:9082
SCU_IRCON0CLR_EXINT0RC_Pos
#define SCU_IRCON0CLR_EXINT0RC_Pos
Definition: tle986x.h:8887
sfr_access.h
SFR low level access library.
CPU_NVIC_ICER0_Int_EXINT0_Pos
#define CPU_NVIC_ICER0_Int_EXINT0_Pos
Definition: tle986x.h:7520
SCU_EDCSCLR_RDBEC_Pos
#define SCU_EDCSCLR_RDBEC_Pos
Definition: tle986x.h:8783
SCUPM
#define SCUPM
Definition: tle986x.h:6005
SCU_EDCSCLR_NVMDBEC_Pos
#define SCU_EDCSCLR_NVMDBEC_Pos
Definition: tle986x.h:8781
CPU_NVIC_ISER0_Int_CCU6SR1_Pos
#define CPU_NVIC_ISER0_Int_CCU6SR1_Pos
Definition: tle986x.h:7636
SCU_EXICON0_EXINT2_RE_Msk
#define SCU_EXICON0_EXINT2_RE_Msk
External Interrupt 2 Rising Edge Bit Mask.
Definition: int.h:127
SCU_NMICLR_NMIOWDC_Pos
#define SCU_NMICLR_NMIOWDC_Pos
Definition: tle986x.h:9068
INLINE
#define INLINE
Definition: types.h:134
SCU_EXICON0_EXINT0_FE_Pos
#define SCU_EXICON0_EXINT0_FE_Pos
External Interrupt 0 Falling Edge Bit Position.
Definition: int.h:113
SCU_NMICLR_NMIMAPC_Pos
#define SCU_NMICLR_NMIMAPC_Pos
Definition: tle986x.h:9066
SCU_NMICON_NMIMAP_Pos
#define SCU_NMICON_NMIMAP_Pos
Definition: tle986x.h:9083
Field_Mod8
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:346
NMI_WDT_Int_Dis
INLINE void NMI_WDT_Int_Dis(void)
disables Watchdog Timer NMI.
Definition: int.h:790
CPU_NVIC_ISER0_Int_CCU6SR1_Msk
#define CPU_NVIC_ISER0_Int_CCU6SR1_Msk
Definition: tle986x.h:7637
CPU_NVIC_ISER0_Int_SSC2_Msk
#define CPU_NVIC_ISER0_Int_SSC2_Msk
Definition: tle986x.h:7629
NMI_OT_Int_Clr
INLINE void NMI_OT_Int_Clr(void)
clears NMI OT Flag.
Definition: int.h:1196
CPU_NVIC_ISER0_Int_ADC2_Pos
#define CPU_NVIC_ISER0_Int_ADC2_Pos
Definition: tle986x.h:7642
INT_Enable_Global_Int
INLINE void INT_Enable_Global_Int(void)
enables the global interrupt IEN0.EA
Definition: int.h:2048
SCU_NMICLR_Pos
#define SCU_NMICLR_Pos
NMI Clear Bit Position.
Definition: int.h:137
Field_Mod32
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
SCU_NMICON_NMIPLL_Msk
#define SCU_NMICON_NMIPLL_Msk
Definition: tle986x.h:9092
NMI_PLL_Int_Dis
INLINE void NMI_PLL_Int_Dis(void)
disables PLL Loss of Lock NMI.
Definition: int.h:835
CPU_NVIC_ISER0_Int_GPT1_Msk
#define CPU_NVIC_ISER0_Int_GPT1_Msk
Definition: tle986x.h:7647
NVIC_Node8_En
INLINE void NVIC_Node8_En(void)
Enables the NVIC node 8 (Int_SSC1)
Definition: int.h:1435
SCU_EXICON0_EXINT0_RE_Msk
#define SCU_EXICON0_EXINT0_RE_Msk
External Interrupt 0 Rising Edge Bit Mask.
Definition: int.h:111
INT_Clr_NMI_Status
INLINE void INT_Clr_NMI_Status(uint8 Flags)
Clears the NMI Status flags.
Definition: int.h:2031
SCU_IRCON0CLR_EXINT0RC_Msk
#define SCU_IRCON0CLR_EXINT0RC_Msk
Definition: tle986x.h:8888
CPU_NVIC_ICER0_Int_ADC2_Msk
#define CPU_NVIC_ICER0_Int_ADC2_Msk
Definition: tle986x.h:7541
SCU_EXICON0_EXINT2_RE_Pos
#define SCU_EXICON0_EXINT2_RE_Pos
External Interrupt 2 Rising Edge Bit Position.
Definition: int.h:125
CPU_NVIC_ICER0_Int_GPT1_Pos
#define CPU_NVIC_ICER0_Int_GPT1_Pos
Definition: tle986x.h:7544
CPU_NVIC_ISER0_Int_CCU6SR2_Pos
#define CPU_NVIC_ISER0_Int_CCU6SR2_Pos
Definition: tle986x.h:7634
SCU_IRCON0CLR_EXINT2FC_Msk
#define SCU_IRCON0CLR_EXINT2FC_Msk
Definition: tle986x.h:8878
CPU_NVIC_ICER0_Int_DMA_Pos
#define CPU_NVIC_ICER0_Int_DMA_Pos
Definition: tle986x.h:7514
EXINT1_Rising_Edge_Int_En
INLINE void EXINT1_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT1.
Definition: int.h:455
SCU_EXICON0_EXINT1_RE_Pos
#define SCU_EXICON0_EXINT1_RE_Pos
External Interrupt 1 Rising Edge Bit Position.
Definition: int.h:117
CPU_NVIC_ICER0_Int_UART2_Msk
#define CPU_NVIC_ICER0_Int_UART2_Msk
Definition: tle986x.h:7523
SCU_EDCSCLR_RSBEC_Msk
#define SCU_EDCSCLR_RSBEC_Msk
Definition: tle986x.h:8780
SCU_NMICON_NMIOT_Pos
#define SCU_NMICON_NMIOT_Pos
Definition: tle986x.h:9087
NMI_SUP_Int_En
INLINE void NMI_SUP_Int_En(void)
enables Supply Prewarning NMI.
Definition: int.h:999
NVIC_Node7_Dis
INLINE void NVIC_Node7_Dis(void)
Disables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1426
NMI_PLL_Int_Clr
INLINE void NMI_PLL_Int_Clr(void)
clears PLL Loss of Lock NMI Flag.
Definition: int.h:1153
CPU_NVIC_ICER0_Int_EXINT1_Msk
#define CPU_NVIC_ICER0_Int_EXINT1_Msk
Definition: tle986x.h:7519
NMI_ECC_Int_Clr
INLINE void NMI_ECC_Int_Clr(void)
clears ECC Error NMI Flag.
Definition: int.h:1261
SCU_EDCSCLR_NVMDBEC_Msk
#define SCU_EDCSCLR_NVMDBEC_Msk
Definition: tle986x.h:8782
NVIC_Node10_Dis
INLINE void NVIC_Node10_Dis(void)
Disables the NVIC node 10 (Int_UART1)
Definition: int.h:1480
CPU_NVIC_ISER0_Int_EXINT0_Msk
#define CPU_NVIC_ISER0_Int_EXINT0_Msk
Definition: tle986x.h:7623
SCU_EXICON0_EXINT2_FE_Msk
#define SCU_EXICON0_EXINT2_FE_Msk
External Interrupt 2 Falling Edge Bit Mask.
Definition: int.h:131
tle_variants.h
Device specific memory layout defines.
SCU_EXICON0_EXINT1_FE_Pos
#define SCU_EXICON0_EXINT1_FE_Pos
External Interrupt 1 Falling Edge Bit Position.
Definition: int.h:121
EXINT2_Falling_Edge_Int_Clr
INLINE void EXINT2_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT2.
Definition: int.h:745
SCU_NMICLR_NMISUPC_Msk
#define SCU_NMICLR_NMISUPC_Msk
Definition: tle986x.h:9063
SCU_IEN0_EA_Msk
#define SCU_IEN0_EA_Msk
Definition: tle986x.h:8854
SCU_NMICON_NMIOT_Msk
#define SCU_NMICON_NMIOT_Msk
Definition: tle986x.h:9088
CPU_NVIC_ICER0_Int_BDRV_Msk
#define CPU_NVIC_ICER0_Int_BDRV_Msk
Definition: tle986x.h:7517
SCU_IEN0_EA_Pos
#define SCU_IEN0_EA_Pos
Definition: tle986x.h:8853
SCU_NMICON_NMIECC_Pos
#define SCU_NMICON_NMIECC_Pos
Definition: tle986x.h:9081
NMI_NVM_Int_Clr
INLINE void NMI_NVM_Int_Clr(void)
clears NVM Operation Complete NMI flag.
Definition: int.h:1175
NMI_NVM_Int_En
INLINE void NMI_NVM_Int_En(void)
enables NVM Operation Complete NMI.
Definition: int.h:857
EXINT2_Falling_Edge_Int_Dis
INLINE void EXINT2_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT2.
Definition: int.h:613
uint8
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
CPU_NVIC_ISER0_Int_UART1_Pos
#define CPU_NVIC_ISER0_Int_UART1_Pos
Definition: tle986x.h:7626
Field_Wrt32
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:341
NVIC_Node15_Dis
INLINE void NVIC_Node15_Dis(void)
Disables the NVIC node 15 (Int_DMA)
Definition: int.h:1572
SCU_IRCON0CLR_EXINT1FC_Pos
#define SCU_IRCON0CLR_EXINT1FC_Pos
Definition: tle986x.h:8881
SCU_NMICON_NMIWDT_Pos
#define SCU_NMICON_NMIWDT_Pos
Definition: tle986x.h:9093
SCU_EDCCON_RIE_Pos
#define SCU_EDCCON_RIE_Pos
Definition: tle986x.h:8776
INT_Init
void INT_Init(void)
Initializes the Interrupt module.
NVIC_Node11_En
INLINE void NVIC_Node11_En(void)
Enables the NVIC node 11 (Int_UART2)
Definition: int.h:1489
SCU_NMICLR_NMINVMC_Pos
#define SCU_NMICLR_NMINVMC_Pos
Definition: tle986x.h:9072
CPU_NVIC_ICER0_Int_SSC2_Msk
#define CPU_NVIC_ICER0_Int_SSC2_Msk
Definition: tle986x.h:7527
u8_Field_Rd8
INLINE uint8 u8_Field_Rd8(const volatile uint8 *reg, uint8 pos, uint8 msk)
This function reads a 8-bit field of a 8-bit register.
Definition: sfr_access.h:406
NMI_SUP_Int_Clr
INLINE void NMI_SUP_Int_Clr(void)
clears Supply Prewarning NMI Flag.
Definition: int.h:1282
CPU_NVIC_ICER0_Int_CCU6SR2_Pos
#define CPU_NVIC_ICER0_Int_CCU6SR2_Pos
Definition: tle986x.h:7532
CPU_NVIC_ICER0_Int_BDRV_Pos
#define CPU_NVIC_ICER0_Int_BDRV_Pos
Definition: tle986x.h:7516
NMI_WDT_Int_En
INLINE void NMI_WDT_Int_En(void)
enables Watchdog Timer NMI.
Definition: int.h:767
SCU_NMICON_NMINVM_Msk
#define SCU_NMICON_NMINVM_Msk
Definition: tle986x.h:9090
EXINT0_Rising_Edge_Int_Dis
INLINE void EXINT0_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT0.
Definition: int.h:388
SCU_NMICLR_NMIWDTC_Pos
#define SCU_NMICLR_NMIWDTC_Pos
Definition: tle986x.h:9076
SCU_EXICON0_EXINT0_FE_Msk
#define SCU_EXICON0_EXINT0_FE_Msk
External Interrupt 0 Falling Edge Bit Mask.
Definition: int.h:115
CPU_NVIC_ICER0_Int_CCU6SR0_Msk
#define CPU_NVIC_ICER0_Int_CCU6SR0_Msk
Definition: tle986x.h:7537
NMI_OT_Int_En
INLINE void NMI_OT_Int_En(void)
enables OT NMI.
Definition: int.h:1087
uint32
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
NMI_OWD_Int_En
INLINE void NMI_OWD_Int_En(void)
enables Oscillator Watchdog NMI.
Definition: int.h:1043
CPU_NVIC_ICER0_Int_ADC2_Pos
#define CPU_NVIC_ICER0_Int_ADC2_Pos
Definition: tle986x.h:7540
NVIC_Node12_En
INLINE void NVIC_Node12_En(void)
Enables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1509
CPU_NVIC_ISER0_Int_ADC1_Pos
#define CPU_NVIC_ISER0_Int_ADC1_Pos
Definition: tle986x.h:7640
EXINT0_Rising_Edge_Int_En
INLINE void EXINT0_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT0.
Definition: int.h:365
SCU_NMICLR_NMIPLLC_Msk
#define SCU_NMICLR_NMIPLLC_Msk
Definition: tle986x.h:9075
NVIC_Node14_En
INLINE void NVIC_Node14_En(void)
Enables the NVIC node 14 (Int_BDRV)
Definition: int.h:1545
NMI_ECC_Int_Dis
INLINE void NMI_ECC_Int_Dis(void)
disables ECC Error NMI.
Definition: int.h:933
SCU_NMICON_NMIOWD_Pos
#define SCU_NMICON_NMIOWD_Pos
Definition: tle986x.h:9085
SCU_NMICLR_NMIWDTC_Msk
#define SCU_NMICLR_NMIWDTC_Msk
Definition: tle986x.h:9077
SCU_NMICLR_NMIOWDC_Msk
#define SCU_NMICLR_NMIOWDC_Msk
Definition: tle986x.h:9069
SCU_NMICON_NMIWDT_Msk
#define SCU_NMICON_NMIWDT_Msk
Definition: tle986x.h:9094
INT_Get_NMI_Status
INLINE uint8 INT_Get_NMI_Status(void)
Reads out the NMI Status.
Definition: int.h:2012
SCU_EDCSCLR_RDBEC_Msk
#define SCU_EDCSCLR_RDBEC_Msk
Definition: tle986x.h:8784
CPU_NVIC_ICER0_Int_CCU6SR2_Msk
#define CPU_NVIC_ICER0_Int_CCU6SR2_Msk
Definition: tle986x.h:7533
CPU_NVIC_ICER0_Int_CCU6SR3_Msk
#define CPU_NVIC_ICER0_Int_CCU6SR3_Msk
Definition: tle986x.h:7531
NVIC_Node5_En
INLINE void NVIC_Node5_En(void)
Enables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1381
EXINT1_Rising_Edge_Int_Clr
INLINE void EXINT1_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT1.
Definition: int.h:679
EXINT0_Rising_Edge_Int_Clr
INLINE void EXINT0_Rising_Edge_Int_Clr(void)
clear Interrupt status on rising edge at EXTINT0.
Definition: int.h:635
Global_Int_Dis
INLINE void Global_Int_Dis(void)
disables Global Interrupt (All pending interrupt requests,except NMI, are blocked from the core).
Definition: int.h:173
SCU_NMICLR_NMIMAPC_Msk
#define SCU_NMICLR_NMIMAPC_Msk
Definition: tle986x.h:9067
SCU_NMICON_NMIMAP_Msk
#define SCU_NMICON_NMIMAP_Msk
Definition: tle986x.h:9084
CPU_NVIC_ISER0_Int_BDRV_Msk
#define CPU_NVIC_ISER0_Int_BDRV_Msk
Definition: tle986x.h:7619
NVIC_Node5_Dis
INLINE void NVIC_Node5_Dis(void)
Disables the NVIC node 5 (Int_CCU6SR1)
Definition: int.h:1390
CPU_NVIC_ICER0_Int_ADC1_Pos
#define CPU_NVIC_ICER0_Int_ADC1_Pos
Definition: tle986x.h:7538
SCU_IRCON0CLR_EXINT1RC_Msk
#define SCU_IRCON0CLR_EXINT1RC_Msk
Definition: tle986x.h:8884
SCU_IRCON0CLR_EXINT1FC_Msk
#define SCU_IRCON0CLR_EXINT1FC_Msk
Definition: tle986x.h:8882
NVIC_Node1_Dis
INLINE void NVIC_Node1_Dis(void)
Disables the NVIC node 1 (Int_GPT2)
Definition: int.h:1318
EXINT1_Rising_Edge_Int_Dis
INLINE void EXINT1_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT1.
Definition: int.h:478
EXINT0_Falling_Edge_Int_Clr
INLINE void EXINT0_Falling_Edge_Int_Clr(void)
clear Interrupt status on falling edge at EXTINT0.
Definition: int.h:657
CPU_NVIC_ISER0_Int_ADC1_Msk
#define CPU_NVIC_ISER0_Int_ADC1_Msk
Definition: tle986x.h:7641
CPU
#define CPU
Definition: tle986x.h:5996
NMI_ECC_Int_En
INLINE void NMI_ECC_Int_En(void)
enables ECC Error NMI.
Definition: int.h:906
tle986x.h
CMSIS register HeaderFile.
SCU
#define SCU
Definition: tle986x.h:6004
SCU_NMICLR_NMIOTC_Pos
#define SCU_NMICLR_NMIOTC_Pos
Definition: tle986x.h:9070
CPU_NVIC_ICER0_Int_GPT2_Pos
#define CPU_NVIC_ICER0_Int_GPT2_Pos
Definition: tle986x.h:7542
CPU_NVIC_ISER0_Int_GPT2_Msk
#define CPU_NVIC_ISER0_Int_GPT2_Msk
Definition: tle986x.h:7645
SCU_NMICLR_NMIECCC_Msk
#define SCU_NMICLR_NMIECCC_Msk
Definition: tle986x.h:9065
CPU_NVIC_ICER0_Int_CCU6SR0_Pos
#define CPU_NVIC_ICER0_Int_CCU6SR0_Pos
Definition: tle986x.h:7536
SCU_EXICON0_EXINT2_FE_Pos
#define SCU_EXICON0_EXINT2_FE_Pos
External Interrupt 2 Falling Edge Bit Position.
Definition: int.h:129
ECC_NVM_DoubleBit_Int_En
INLINE void ECC_NVM_DoubleBit_Int_En(void)
enables NVM Double Bit ECC Error Interrupt.
Definition: int.h:252
NMI_NVM_Int_Dis
INLINE void NMI_NVM_Int_Dis(void)
disables NVM Operation Complete NMI.
Definition: int.h:880
NVIC_Node3_Dis
INLINE void NVIC_Node3_Dis(void)
Disables the NVIC node 3 (Int_ADC1)
Definition: int.h:1354
SCU_IRCON0CLR_EXINT2RC_Msk
#define SCU_IRCON0CLR_EXINT2RC_Msk
Definition: tle986x.h:8880
SCU_IRCON0CLR_EXINT2RC_Pos
#define SCU_IRCON0CLR_EXINT2RC_Pos
Definition: tle986x.h:8879
SCU_NMICON_NMISUP_Pos
#define SCU_NMICON_NMISUP_Pos
Definition: tle986x.h:9079
CPU_NVIC_ICER0_Int_CCU6SR1_Msk
#define CPU_NVIC_ICER0_Int_CCU6SR1_Msk
Definition: tle986x.h:7535
CPU_NVIC_ISER0_Int_UART2_Msk
#define CPU_NVIC_ISER0_Int_UART2_Msk
Definition: tle986x.h:7625
NVIC_Node12_Dis
INLINE void NVIC_Node12_Dis(void)
Disables the NVIC node 12 (Int_EXINT0)
Definition: int.h:1518
CPU_NVIC_ISER0_Int_EXINT1_Msk
#define CPU_NVIC_ISER0_Int_EXINT1_Msk
Definition: tle986x.h:7621
CPU_NVIC_ISER0_Int_SSC2_Pos
#define CPU_NVIC_ISER0_Int_SSC2_Pos
Definition: tle986x.h:7628
NVIC_Node13_Dis
INLINE void NVIC_Node13_Dis(void)
Disables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1536
EXINT0_Falling_Edge_Int_Dis
INLINE void EXINT0_Falling_Edge_Int_Dis(void)
disables Interrupt on falling edge at EXTINT0.
Definition: int.h:433
CPU_NVIC_ICER0_Int_UART2_Pos
#define CPU_NVIC_ICER0_Int_UART2_Pos
Definition: tle986x.h:7522
NVIC_Node9_En
INLINE void NVIC_Node9_En(void)
Enables the NVIC node 9 (Int_SSC2)
Definition: int.h:1453
NMI_SUP_Int_Dis
INLINE void NMI_SUP_Int_Dis(void)
disables Supply Prewarning NMI.
Definition: int.h:1021
CPU_NVIC_ISER0_Int_CCU6SR3_Msk
#define CPU_NVIC_ISER0_Int_CCU6SR3_Msk
Definition: tle986x.h:7633
ECC_RAM_DoubleBit_Int_Clr
INLINE void ECC_RAM_DoubleBit_Int_Clr(void)
clears RAM Double Bit ECC Error Interrupt flag.
Definition: int.h:321
NMI_WDT_Int_Clr
INLINE void NMI_WDT_Int_Clr(void)
clears Watchdog Timer NMI Flag.
Definition: int.h:1131
SCU_EXICON0_EXINT0_RE_Pos
#define SCU_EXICON0_EXINT0_RE_Pos
External Interrupt 0 Rising Edge Bit Position.
Definition: int.h:109
CPU_NVIC_ICER0_Int_GPT2_Msk
#define CPU_NVIC_ICER0_Int_GPT2_Msk
Definition: tle986x.h:7543
NMI_MAP_Int_Dis
INLINE void NMI_MAP_Int_Dis(void)
disables NVM Map Error NMI.
Definition: int.h:978
NMI_OWD_Int_Dis
INLINE void NMI_OWD_Int_Dis(void)
disables Oscillator Watchdog NMI.
Definition: int.h:1066
NVIC_Node1_En
INLINE void NVIC_Node1_En(void)
Enables the NVIC node 1 (Int_GPT2)
Definition: int.h:1309
CPU_NVIC_ISER0_Int_GPT2_Pos
#define CPU_NVIC_ISER0_Int_GPT2_Pos
Definition: tle986x.h:7644
ECC_NVM_DoubleBit_Int_Clr
INLINE void ECC_NVM_DoubleBit_Int_Clr(void)
clears NVM Double Bit ECC Error Interrupt flag.
Definition: int.h:343
NVIC_Node8_Dis
INLINE void NVIC_Node8_Dis(void)
Disables the NVIC node 8 (Int_SSC1)
Definition: int.h:1444
SCU_EDCCON_NVMIE_Pos
#define SCU_EDCCON_NVMIE_Pos
Definition: tle986x.h:8774
NVIC_Node13_En
INLINE void NVIC_Node13_En(void)
Enables the NVIC node 13 (Int_EXINT1)
Definition: int.h:1527
NVIC_Node0_Dis
INLINE void NVIC_Node0_Dis(void)
Disables the NVIC node 0 (Int_GPT1)
Definition: int.h:1300
NVIC_Node3_En
INLINE void NVIC_Node3_En(void)
Enables the NVIC node 3 (Int_ADC1)
Definition: int.h:1345
SCU_IRCON0CLR_EXINT0FC_Pos
#define SCU_IRCON0CLR_EXINT0FC_Pos
Definition: tle986x.h:8885
EXINT2_Rising_Edge_Int_En
INLINE void EXINT2_Rising_Edge_Int_En(void)
enables Interrupt on rising edge at EXTINT2.
Definition: int.h:545
Field_Wrt8
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:331
NMI_PLL_Int_En
INLINE void NMI_PLL_Int_En(void)
enables PLL Loss of Lock NMI.
Definition: int.h:812
NVIC_Node10_En
INLINE void NVIC_Node10_En(void)
Enables the NVIC node 10 (Int_UART1)
Definition: int.h:1471
NMI_MAP_Int_Clr
INLINE void NMI_MAP_Int_Clr(void)
clears NVM Map Error NMI Flag.
Definition: int.h:1240
NMI_OWD_Int_Clr
INLINE void NMI_OWD_Int_Clr(void)
clears Oscillator Watchdog NMI Flag.
Definition: int.h:1218
NVIC_Node11_Dis
INLINE void NVIC_Node11_Dis(void)
Disables the NVIC node 11 (Int_UART2)
Definition: int.h:1499
CPU_NVIC_ISER0_Int_CCU6SR0_Pos
#define CPU_NVIC_ISER0_Int_CCU6SR0_Pos
Definition: tle986x.h:7638
SCU_NMICLR_Msk
#define SCU_NMICLR_Msk
NMI Clear Bit Mask.
Definition: int.h:139
EXINT2_Rising_Edge_Int_Dis
INLINE void EXINT2_Rising_Edge_Int_Dis(void)
disables Interrupt on rising edge at EXTINT2.
Definition: int.h:568
SCU_EXICON0_EXINT1_RE_Msk
#define SCU_EXICON0_EXINT1_RE_Msk
External Interrupt 1 Rising Edge Bit Mask.
Definition: int.h:119
CPU_NVIC_ICER0_Int_SSC2_Pos
#define CPU_NVIC_ICER0_Int_SSC2_Pos
Definition: tle986x.h:7526
NVIC_Node4_Dis
INLINE void NVIC_Node4_Dis(void)
Disables the NVIC node 4 (Int_CCU6SR0)
Definition: int.h:1372
EXINT2_Falling_Edge_Int_En
INLINE void EXINT2_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT2.
Definition: int.h:590
NVIC_Node7_En
INLINE void NVIC_Node7_En(void)
Enables the NVIC node 7 (Int_CCU6SR3)
Definition: int.h:1417
ECC_RAM_DoubleBit_Int_Dis
INLINE void ECC_RAM_DoubleBit_Int_Dis(void)
disables RAM Double Bit ECC Error Interrupt.
Definition: int.h:226
CPU_NVIC_ICER0_Int_SSC1_Pos
#define CPU_NVIC_ICER0_Int_SSC1_Pos
Definition: tle986x.h:7528
EXINT0_Falling_Edge_Int_En
INLINE void EXINT0_Falling_Edge_Int_En(void)
enables Interrupt on falling edge at EXTINT0.
Definition: int.h:410
SCU_IRCON0CLR_EXINT2FC_Pos
#define SCU_IRCON0CLR_EXINT2FC_Pos
Definition: tle986x.h:8877
NVIC_Node9_Dis
INLINE void NVIC_Node9_Dis(void)
Disables the NVIC node 9 (Int_SSC2)
Definition: int.h:1462
CPU_NVIC_ICER0_Int_EXINT1_Pos
#define CPU_NVIC_ICER0_Int_EXINT1_Pos
Definition: tle986x.h:7518
CPU_NVIC_ISER0_Int_SSC1_Pos
#define CPU_NVIC_ISER0_Int_SSC1_Pos
Definition: tle986x.h:7630
NMI_MAP_Int_En
INLINE void NMI_MAP_Int_En(void)
enables NVM Map Error NMI.
Definition: int.h:955
NVIC_Node15_En
INLINE void NVIC_Node15_En(void)
Enables the NVIC node 15 (Int_DMA)
Definition: int.h:1563
SCU_IRCON0CLR_EXINT0FC_Msk
#define SCU_IRCON0CLR_EXINT0FC_Msk
Definition: tle986x.h:8886
NMI_OT_Int_Dis
INLINE void NMI_OT_Int_Dis(void)
disables OT NMI.
Definition: int.h:1109
SCU_NMICLR_NMISUPC_Pos
#define SCU_NMICLR_NMISUPC_Pos
Definition: tle986x.h:9062
CPU_NVIC_ICER0_Int_SSC1_Msk
#define CPU_NVIC_ICER0_Int_SSC1_Msk
Definition: tle986x.h:7529
NVIC_Node14_Dis
INLINE void NVIC_Node14_Dis(void)
Disables the NVIC node 14 (Int_BDRV)
Definition: int.h:1554
CPU_NVIC_ISER0_Int_CCU6SR3_Pos
#define CPU_NVIC_ISER0_Int_CCU6SR3_Pos
Definition: tle986x.h:7632
NVIC_Node2_Dis
INLINE void NVIC_Node2_Dis(void)
Disables the NVIC node 2 (Int_ADC2)
Definition: int.h:1336
SCU_EDCCON_RIE_Msk
#define SCU_EDCCON_RIE_Msk
Definition: tle986x.h:8777
CPU_NVIC_ISER0_Int_DMA_Msk
#define CPU_NVIC_ISER0_Int_DMA_Msk
Definition: tle986x.h:7617