TLE986x Device Family SDK
Data Structures | Macros | Typedefs | Enumerations | Functions
dma.h File Reference

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Detailed Description

Direct Memory Access low level access library.

Version
V0.2.1
Date
28. Oct 2020
Note
This file violates [MISRA Rule 1], [MISRA Rule 26], [MISRA Rule 45], [MISRA Rule 52], [MISRA Rule 72], [MISRA Rule 85], [MISRA 2012 Rule 12.1, advisory], [MISRA 2012 Rule 12.2, required], [MISRA 2012 Directive 4.9, advisory], [MISRA 2012 Rule 20.10, advisory]

Include Graph

Include dependency graph for dma.h:

Data Structures

struct  TControl
 This structure lists the bit assignments for the channel_cfg memory location. More...
 
struct  TDMA_Entry
 This structure lists the DMA transfer memory locations. More...
 

Macros

#define DMA_CH0   (0u)
 DMA channel selection macro, DMA CH0. More...
 
#define DMA_CH1   (1u)
 DMA channel selection macro, DMA CH1. More...
 
#define DMA_CH2   (2u)
 DMA channel selection macro, DMA CH2. More...
 
#define DMA_CH3   (3u)
 DMA channel selection macro, DMA CH3. More...
 
#define DMA_CH4   (4u)
 DMA channel selection macro, DMA CH4. More...
 
#define DMA_CH5   (5u)
 DMA channel selection macro, DMA CH5. More...
 
#define DMA_CH6   (6u)
 DMA channel selection macro, DMA CH6. More...
 
#define DMA_CH7   (7u)
 DMA channel selection macro, DMA CH7. More...
 
#define DMA_CH8   (8u)
 DMA channel selection macro, DMA CH8. More...
 
#define DMA_CH9   (9u)
 DMA channel selection macro, DMA CH9. More...
 
#define DMA_CH10   (10u)
 DMA channel selection macro, DMA CH10. More...
 
#define DMA_CH11   (11u)
 DMA channel selection macro, DMA CH11. More...
 
#define DMA_CH12   (12u)
 DMA channel selection macro, DMA CH12. More...
 
#define DMA_MASK_CH0   ((uint16)1u << DMA_CH0)
 DMA channel Mask macro, DMA CH0 MASK. More...
 
#define DMA_MASK_CH1   ((uint16)1u << DMA_CH1)
 DMA channel Mask macro, DMA CH1 MASK. More...
 
#define DMA_MASK_CH2   ((uint16)1u << DMA_CH2)
 DMA channel Mask macro, DMA CH2 MASK. More...
 
#define DMA_MASK_CH3   ((uint16)1u << DMA_CH3)
 DMA channel Mask macro, DMA CH3 MASK. More...
 
#define DMA_MASK_CH4   ((uint16)1u << DMA_CH4)
 DMA channel Mask macro, DMA CH4 MASK. More...
 
#define DMA_MASK_CH5   ((uint16)1u << DMA_CH5)
 DMA channel Mask macro, DMA CH5 MASK. More...
 
#define DMA_MASK_CH6   ((uint16)1u << DMA_CH6)
 DMA channel Mask macro, DMA CH6 MASK. More...
 
#define DMA_MASK_CH7   ((uint16)1u << DMA_CH7)
 DMA channel Mask macro, DMA CH7 MASK. More...
 
#define DMA_MASK_CH8   ((uint16)1u << DMA_CH8)
 DMA channel Mask macro, DMA CH8 MASK. More...
 
#define DMA_MASK_CH9   ((uint16)1u << DMA_CH9)
 DMA channel Mask macro, DMA CH9 MASK. More...
 
#define DMA_MASK_CH10   ((uint16)1u << DMA_CH10)
 DMA channel Mask macro, DMA CH10 MASK. More...
 
#define DMA_MASK_CH11   ((uint16)1u << DMA_CH11)
 DMA channel Mask macro, DMA CH11 MASK. More...
 
#define DMA_MASK_CH12   ((uint16)1u << DMA_CH12)
 DMA channel Mask macro, DMA CH12 MASK. More...
 

Typedefs

typedef enum _TDMA_Transfer_Size TDMA_Transfer_Size
 
typedef enum _TDMA_Increment_Size TDMA_Increment_Size
 
typedef enum _TDMA_Increment_Mode TDMA_Increment_Mode
 
typedef enum _TDMA_Cycle_Types TDMA_Cycle_Types
 

Enumerations

enum  _TDMA_Transfer_Size { DMA_8Bit_Transfer = 0u, DMA_16Bit_Transfer = 1u, DMA_32Bit_Transfer = 2u }
 This enum lists the transfer size options for the DMA. More...
 
enum  _TDMA_Increment_Size { DMA_Inc_8bit = 0u, DMA_Inc_16bit = 1u, DMA_Inc_32bit = 2u }
 This enum lists the increment size options for the DMA. More...
 
enum  _TDMA_Increment_Mode { DMA_No_Inc = 0u, DMA_Src_Inc = 1u, DMA_Dst_Inc = 2u, DMA_Src_Dst_Inc = 3u }
 This enum lists the increment mode options for the DMA. More...
 
enum  _TDMA_Cycle_Types {
  DMA_Cycle_Type_Invalid = 0u, DMA_Cycle_Type_Basic = 1u, DMA_Cycle_Type_Auto = 2u, DMA_Cycle_Type_PingPong = 3u,
  DMA_Cycle_Type_MemSctGthPrim = 4u, DMA_Cycle_Type_MemSctGthAlt = 5u, DMA_Cycle_Type_PerSctGthPrim = 6u, DMA_Cycle_Type_PerSctGthAlt = 7u
}
 This enum lists the cycle type options for the DMA. More...
 

Functions

INLINE void DMA_CH0_Int_Clr (void)
 clears DMA Channel 0 Interrupt flag. More...
 
INLINE void DMA_CH1_Int_Clr (void)
 clears DMA Channel 1 Interrupt flag. More...
 
INLINE void DMA_CH2_Int_Clr (void)
 clears DMA Channel 2 Interrupt flag. More...
 
INLINE void DMA_CH3_Int_Clr (void)
 clears DMA Channel 3 Interrupt flag. More...
 
INLINE void DMA_CH4_Int_Clr (void)
 clears DMA Channel 4 Interrupt flag. More...
 
INLINE void DMA_CH5_Int_Clr (void)
 clears DMA Channel 5 Interrupt flag. More...
 
INLINE void DMA_CH6_Int_Clr (void)
 clears DMA Channel 6 Interrupt flag. More...
 
INLINE void DMA_CH7_Int_Clr (void)
 clears DMA Channel 7 Interrupt flag. More...
 
INLINE void DMA_CH8_Int_Clr (void)
 clears DMA Channel 8 Interrupt flag. More...
 
INLINE void DMA_CH9_Int_Clr (void)
 clears DMA Channel 9 Interrupt flag. More...
 
INLINE void DMA_CH10_Int_Clr (void)
 clears DMA Channel 10 Interrupt flag. More...
 
INLINE void DMA_CH11_Int_Clr (void)
 clears DMA Channel 11 Interrupt flag. More...
 
INLINE void DMA_CH12_Int_Clr (void)
 clears DMA Channel 12 Interrupt flag. More...
 
INLINE void DMA_CH0_Int_En (void)
 enables DMA Channel 0 Interrupt. More...
 
INLINE void DMA_CH0_Int_Dis (void)
 disables DMA Channel 0 Interrupt. More...
 
INLINE void DMA_CH1_Int_En (void)
 enables DMA Channel 1 Interrupt. More...
 
INLINE void DMA_CH1_Int_Dis (void)
 disables DMA Channel 1 Interrupt. More...
 
INLINE void DMA_CH2_Int_En (void)
 enables DMA Channel 2 Interrupt. More...
 
INLINE void DMA_CH2_Int_Dis (void)
 disables DMA Channel 2 Interrupt. More...
 
INLINE void DMA_CH3_Int_En (void)
 enables DMA Channel 3 Interrupt. More...
 
INLINE void DMA_CH3_Int_Dis (void)
 disables DMA Channel 3 Interrupt. More...
 
INLINE void DMA_CH4_Int_En (void)
 enables DMA Channel 4 Interrupt. More...
 
INLINE void DMA_CH4_Int_Dis (void)
 disables DMA Channel 4 Interrupt. More...
 
INLINE void DMA_CH5_Int_En (void)
 enables DMA Channel 5 Interrupt. More...
 
INLINE void DMA_CH5_Int_Dis (void)
 disables DMA Channel 5 Interrupt. More...
 
INLINE void DMA_CH6_Int_En (void)
 enables DMA Channel 6 Interrupt. More...
 
INLINE void DMA_CH6_Int_Dis (void)
 disables DMA Channel 6 Interrupt. More...
 
INLINE void DMA_CH7_Int_En (void)
 enables DMA Channel 7 Interrupt. More...
 
INLINE void DMA_CH7_Int_Dis (void)
 disables DMA Channel 7 Interrupt. More...
 
INLINE void DMA_CH8_Int_En (void)
 enables DMA Channel 8 Interrupt. More...
 
INLINE void DMA_CH8_Int_Dis (void)
 disables DMA Channel 8 Interrupt. More...
 
INLINE void DMA_CH9_Int_En (void)
 enables DMA Channel 9 Interrupt. More...
 
INLINE void DMA_CH9_Int_Dis (void)
 disables DMA Channel 9 Interrupt. More...
 
INLINE void DMA_CH10_Int_En (void)
 enables DMA Channel 10 Interrupt. More...
 
INLINE void DMA_CH10_Int_Dis (void)
 disables DMA Channel 10 Interrupt. More...
 
INLINE void DMA_CH11_Int_En (void)
 enables DMA Channel 11 Interrupt. More...
 
INLINE void DMA_CH11_Int_Dis (void)
 disables DMA Channel 11 Interrupt. More...
 
INLINE void DMA_CH12_Int_En (void)
 enables DMA Channel 12 Interrupt. More...
 
INLINE void DMA_CH12_Int_Dis (void)
 disables DMA Channel 12 Interrupt. More...
 
INLINE void DMA_Primary_Struct_Set (uint32 mask_ch)
 points to the base address of the primary data structure. More...
 
INLINE void DMA_Channel_Enable_Set (uint32 mask_ch)
 enables DMA Channels. More...
 
INLINE void DMA_Software_Request_Set (uint32 mask_ch)
 Set software request for DMA Channels. More...
 
INLINE void DMA_Primary_Struct_Usage_Set (uint32 mask_ch)
 selects the primary data structure for the corresponding DMA channel. More...
 
INLINE void DMA_Alternate_Struct_Usage_Set (uint32 mask_ch)
 selects the alternate data structure for the corresponding DMA channel. More...
 
INLINE uint32 DMA_CHx_Entry_Alt (uint8 DMA_Ch)
 This function returns the address inside the alternate structure in RAM for a given DMA channel. More...
 
INLINE uint32 DMA_CHx_Entry_Pri (uint8 DMA_Ch)
 This function returns the address inside the primary structure in RAM for a given DMA channel. More...
 
void DMA_Init (void)
 Initializes the DMA structure in RAM and SFRs according to the ConfigWizard settings. More...
 
void DMA_Setup_Channel (uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
 Sets up the desired DMA channel in the primary structure in RAM. More...
 
void DMA_Reset_Channel (uint32 DMA_ChIdx, uint32 trans_cnt)
 Resets the primary structure in RAM for a given channel and rearms it. More...
 
TDMA_EntryDMA_Task_SctGth_Set (TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
 Sets up a task to be used with memory scatter-gather mode. More...
 
void DMA_Channel_MemSctGth_Set (uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
 Sets up a channel to operate in Memory Scatter-Gather mode on a given task list. More...
 
void DMA_Channel_PerSctGth_Set (uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
 Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list. More...
 
TDMA_EntryDMA_Task_Set (TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
 Sets up a task to be used in the Scatter-Gather modes. More...
 
INLINE void DMA_Master_En (void)
 Enabled the DMA master. More...
 

Macro Definition Documentation

◆ DMA_CH0

#define DMA_CH0   (0u)

DMA channel selection macro, DMA CH0.

◆ DMA_CH1

#define DMA_CH1   (1u)

DMA channel selection macro, DMA CH1.

◆ DMA_CH10

#define DMA_CH10   (10u)

DMA channel selection macro, DMA CH10.

◆ DMA_CH11

#define DMA_CH11   (11u)

DMA channel selection macro, DMA CH11.

◆ DMA_CH12

#define DMA_CH12   (12u)

DMA channel selection macro, DMA CH12.

◆ DMA_CH2

#define DMA_CH2   (2u)

DMA channel selection macro, DMA CH2.

◆ DMA_CH3

#define DMA_CH3   (3u)

DMA channel selection macro, DMA CH3.

◆ DMA_CH4

#define DMA_CH4   (4u)

DMA channel selection macro, DMA CH4.

◆ DMA_CH5

#define DMA_CH5   (5u)

DMA channel selection macro, DMA CH5.

◆ DMA_CH6

#define DMA_CH6   (6u)

DMA channel selection macro, DMA CH6.

◆ DMA_CH7

#define DMA_CH7   (7u)

DMA channel selection macro, DMA CH7.

◆ DMA_CH8

#define DMA_CH8   (8u)

DMA channel selection macro, DMA CH8.

◆ DMA_CH9

#define DMA_CH9   (9u)

DMA channel selection macro, DMA CH9.

◆ DMA_MASK_CH0

#define DMA_MASK_CH0   ((uint16)1u << DMA_CH0)

DMA channel Mask macro, DMA CH0 MASK.

◆ DMA_MASK_CH1

#define DMA_MASK_CH1   ((uint16)1u << DMA_CH1)

DMA channel Mask macro, DMA CH1 MASK.

◆ DMA_MASK_CH10

#define DMA_MASK_CH10   ((uint16)1u << DMA_CH10)

DMA channel Mask macro, DMA CH10 MASK.

◆ DMA_MASK_CH11

#define DMA_MASK_CH11   ((uint16)1u << DMA_CH11)

DMA channel Mask macro, DMA CH11 MASK.

◆ DMA_MASK_CH12

#define DMA_MASK_CH12   ((uint16)1u << DMA_CH12)

DMA channel Mask macro, DMA CH12 MASK.

◆ DMA_MASK_CH2

#define DMA_MASK_CH2   ((uint16)1u << DMA_CH2)

DMA channel Mask macro, DMA CH2 MASK.

◆ DMA_MASK_CH3

#define DMA_MASK_CH3   ((uint16)1u << DMA_CH3)

DMA channel Mask macro, DMA CH3 MASK.

◆ DMA_MASK_CH4

#define DMA_MASK_CH4   ((uint16)1u << DMA_CH4)

DMA channel Mask macro, DMA CH4 MASK.

◆ DMA_MASK_CH5

#define DMA_MASK_CH5   ((uint16)1u << DMA_CH5)

DMA channel Mask macro, DMA CH5 MASK.

◆ DMA_MASK_CH6

#define DMA_MASK_CH6   ((uint16)1u << DMA_CH6)

DMA channel Mask macro, DMA CH6 MASK.

◆ DMA_MASK_CH7

#define DMA_MASK_CH7   ((uint16)1u << DMA_CH7)

DMA channel Mask macro, DMA CH7 MASK.

◆ DMA_MASK_CH8

#define DMA_MASK_CH8   ((uint16)1u << DMA_CH8)

DMA channel Mask macro, DMA CH8 MASK.

◆ DMA_MASK_CH9

#define DMA_MASK_CH9   ((uint16)1u << DMA_CH9)

DMA channel Mask macro, DMA CH9 MASK.

Typedef Documentation

◆ TDMA_Cycle_Types

◆ TDMA_Increment_Mode

◆ TDMA_Increment_Size

◆ TDMA_Transfer_Size

Enumeration Type Documentation

◆ _TDMA_Cycle_Types

This enum lists the cycle type options for the DMA.

Enumerator
DMA_Cycle_Type_Invalid 

DMA Cycle Types macro, Invalid Mode

DMA_Cycle_Type_Basic 

DMA Cycle Types macro, Basic Mode

DMA_Cycle_Type_Auto 

DMA Cycle Types macro, Auto-request Mode

DMA_Cycle_Type_PingPong 

DMA Cycle Types macro, PingPong Mode

DMA_Cycle_Type_MemSctGthPrim 

DMA Cycle Types macro, Memory scatter/gather Primary Mode

DMA_Cycle_Type_MemSctGthAlt 

DMA Cycle Types macro, Memory scatter/gather Alternate Mode

DMA_Cycle_Type_PerSctGthPrim 

DMA Cycle Types macro, Peripheral scatter/gather Primary Mode

DMA_Cycle_Type_PerSctGthAlt 

DMA Cycle Types macro, Peripheral scatter/gather Alternate Mode

◆ _TDMA_Increment_Mode

This enum lists the increment mode options for the DMA.

Enumerator
DMA_No_Inc 

DMA Increment Codes macro, No Increment

DMA_Src_Inc 

DMA Increment Codes macro, Source Address Increment

DMA_Dst_Inc 

DMA Increment Codes macro, Destination Address Increment

DMA_Src_Dst_Inc 

DMA Increment Codes macro, Source and Destination Address Increment

◆ _TDMA_Increment_Size

This enum lists the increment size options for the DMA.

Enumerator
DMA_Inc_8bit 

DMA Increment macro, Increment 8Bit

DMA_Inc_16bit 

DMA Increment macro, Increment 16Bit

DMA_Inc_32bit 

DMA Increment macro, Increment 32Bit

◆ _TDMA_Transfer_Size

This enum lists the transfer size options for the DMA.

Enumerator
DMA_8Bit_Transfer 

DMA Transfer Codes macro, 8Bit Transfer

DMA_16Bit_Transfer 

DMA Transfer Codes macro, 16Bit Transfer

DMA_32Bit_Transfer 

DMA Transfer Codes macro, 32Bit Transfer

Function Documentation

◆ DMA_Alternate_Struct_Usage_Set()

INLINE void DMA_Alternate_Struct_Usage_Set ( uint32  mask_ch)

selects the alternate data structure for the corresponding DMA channel.

Parameters
mask_chDMA channel Mask

Example

This example selects the alternate data structure for DMA channel 0.

void Example_Function(void)
{
}

◆ DMA_CH0_Int_Clr()

INLINE void DMA_CH0_Int_Clr ( void  )

clears DMA Channel 0 Interrupt flag.

Example

This example treats the DMA Channel 0 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.TRSEQ1DY == (uint8)1)
{
DMA_SQ1_RDY_CALLBACK();
}
}

◆ DMA_CH0_Int_Dis()

INLINE void DMA_CH0_Int_Dis ( void  )

disables DMA Channel 0 Interrupt.

Example

This example treats the DMA Channel 0 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.TRSEQ1DY == (uint8)1)
{
DMA_SQ1_RDY_CALLBACK();
}
}

◆ DMA_CH0_Int_En()

INLINE void DMA_CH0_Int_En ( void  )

enables DMA Channel 0 Interrupt.

Example

This example treats the DMA Channel 0 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.TRSEQ1DY == (uint8)1)
{
DMA_SQ1_RDY_CALLBACK();
}
}

◆ DMA_CH10_Int_Clr()

INLINE void DMA_CH10_Int_Clr ( void  )

clears DMA Channel 10 Interrupt flag.

Example

This example treats the DMA Channel 10 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH7 == (uint8)1)
{
DMA_CH7_CALLBACK();
}
}

◆ DMA_CH10_Int_Dis()

INLINE void DMA_CH10_Int_Dis ( void  )

disables DMA Channel 10 Interrupt.

Example

This example treats the DMA Channel 10 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH7 == (uint8)1)
{
DMA_CH7_CALLBACK();
}
}

◆ DMA_CH10_Int_En()

INLINE void DMA_CH10_Int_En ( void  )

enables DMA Channel 10 Interrupt.

Example

This example treats the DMA Channel 10 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH7 == (uint8)1)
{
DMA_CH7_CALLBACK();
}
}

◆ DMA_CH11_Int_Clr()

INLINE void DMA_CH11_Int_Clr ( void  )

clears DMA Channel 11 Interrupt flag.

Example

This example treats the DMA Channel 11 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH8 == (uint8)1)
{
DMA_CH8_CALLBACK();
}
}

◆ DMA_CH11_Int_Dis()

INLINE void DMA_CH11_Int_Dis ( void  )

disables DMA Channel 11 Interrupt.

Example

This example treats the DMA Channel 11 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH8 == (uint8)1)
{
DMA_CH8_CALLBACK();
}
}

◆ DMA_CH11_Int_En()

INLINE void DMA_CH11_Int_En ( void  )

enables DMA Channel 11 Interrupt.

Example

This example treats the DMA Channel 11 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH8 == (uint8)1)
{
DMA_CH8_CALLBACK();
}
}

◆ DMA_CH12_Int_Clr()

INLINE void DMA_CH12_Int_Clr ( void  )

clears DMA Channel 12 Interrupt flag.

Example

This example treats the DMA Channel 12 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.GPT12 == (uint8)1)
{
DMA_GPT12E_CALLBACK();
}
}

◆ DMA_CH12_Int_Dis()

INLINE void DMA_CH12_Int_Dis ( void  )

disables DMA Channel 12 Interrupt.

Example

This example treats the DMA Channel 12 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.GPT12 == (uint8)1)
{
DMA_GPT12E_CALLBACK();
}
}

◆ DMA_CH12_Int_En()

INLINE void DMA_CH12_Int_En ( void  )

enables DMA Channel 12 Interrupt.

Example

This example treats the DMA Channel 12 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.GPT12 == (uint8)1)
{
DMA_GPT12E_CALLBACK();
}
}

◆ DMA_CH1_Int_Clr()

INLINE void DMA_CH1_Int_Clr ( void  )

clears DMA Channel 1 Interrupt flag.

Example

This example treats the DMA Channel 1 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.TRSEQ2DY == (uint8)1)
{
DMA_SQ2_RDY_CALLBACK();
}
}

◆ DMA_CH1_Int_Dis()

INLINE void DMA_CH1_Int_Dis ( void  )

disables DMA Channel 1 Interrupt.

Example

This example treats the DMA Channel 1 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.TRSEQ2DY == (uint8)1)
{
DMA_SQ2_RDY_CALLBACK();
}
}

◆ DMA_CH1_Int_En()

INLINE void DMA_CH1_Int_En ( void  )

enables DMA Channel 1 Interrupt.

Example

This example treats the DMA Channel 1 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.TRSEQ2DY == (uint8)1)
{
DMA_SQ2_RDY_CALLBACK();
}
}

◆ DMA_CH2_Int_Clr()

INLINE void DMA_CH2_Int_Clr ( void  )

clears DMA Channel 2 Interrupt flag.

Example

This example treats the DMA Channel 2 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.SSC1RDY == (uint8)1)
{
DMA_SSC_TX_CALLBACK();
}
}

◆ DMA_CH2_Int_Dis()

INLINE void DMA_CH2_Int_Dis ( void  )

disables DMA Channel 2 Interrupt.

Example

This example treats the DMA Channel 2 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.SSC1RDY == (uint8)1)
{
DMA_SSC_TX_CALLBACK();
}
}

◆ DMA_CH2_Int_En()

INLINE void DMA_CH2_Int_En ( void  )

enables DMA Channel 2 Interrupt.

Example

This example treats the DMA Channel 2 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.SSC1RDY == (uint8)1)
{
DMA_SSC_TX_CALLBACK();
}
}

◆ DMA_CH3_Int_Clr()

INLINE void DMA_CH3_Int_Clr ( void  )

clears DMA Channel 3 Interrupt flag.

Example

This example treats the DMA Channel 3 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.SSC2RDY == (uint8)1)
{
DMA_SSC_RX_CALLBACK();
}
}

◆ DMA_CH3_Int_Dis()

INLINE void DMA_CH3_Int_Dis ( void  )

disables DMA Channel 3 Interrupt.

Example

This example treats the DMA Channel 3 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.SSC2RDY == (uint8)1)
{
DMA_SSC_RX_CALLBACK();
}
}

◆ DMA_CH3_Int_En()

INLINE void DMA_CH3_Int_En ( void  )

enables DMA Channel 3 Interrupt.

Example

This example treats the DMA Channel 3 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC2.bit.SSC2RDY == (uint8)1)
{
DMA_SSC_RX_CALLBACK();
}
}

◆ DMA_CH4_Int_Clr()

INLINE void DMA_CH4_Int_Clr ( void  )

clears DMA Channel 4 Interrupt flag.

Example

This example treats the DMA Channel 4 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH1 == (uint8)1)
{
DMA_CH1_CALLBACK();
}
}

◆ DMA_CH4_Int_Dis()

INLINE void DMA_CH4_Int_Dis ( void  )

disables DMA Channel 4 Interrupt.

Example

This example treats the DMA Channel 4 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH1 == (uint8)1)
{
DMA_CH1_CALLBACK();
}
}

◆ DMA_CH4_Int_En()

INLINE void DMA_CH4_Int_En ( void  )

enables DMA Channel 4 Interrupt.

Example

This example treats the DMA Channel 4 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH1 == (uint8)1)
{
DMA_CH1_CALLBACK();
}
}

◆ DMA_CH5_Int_Clr()

INLINE void DMA_CH5_Int_Clr ( void  )

clears DMA Channel 5 Interrupt flag.

Example

This example treats the DMA Channel 5 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH2 == (uint8)1)
{
DMA_CH2_CALLBACK();
}
}

◆ DMA_CH5_Int_Dis()

INLINE void DMA_CH5_Int_Dis ( void  )

disables DMA Channel 5 Interrupt.

Example

This example treats the DMA Channel 5 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH2 == (uint8)1)
{
DMA_CH2_CALLBACK();
}
}

◆ DMA_CH5_Int_En()

INLINE void DMA_CH5_Int_En ( void  )

enables DMA Channel 5 Interrupt.

Example

This example treats the DMA Channel 5 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH2 == (uint8)1)
{
DMA_CH2_CALLBACK();
}
}

◆ DMA_CH6_Int_Clr()

INLINE void DMA_CH6_Int_Clr ( void  )

clears DMA Channel 6 Interrupt flag.

Example

This example treats the DMA Channel 6 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH3 == (uint8)1)
{
DMA_CH3_CALLBACK();
}
}

◆ DMA_CH6_Int_Dis()

INLINE void DMA_CH6_Int_Dis ( void  )

disables DMA Channel 6 Interrupt.

Example

This example treats the DMA Channel 6 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH3 == (uint8)1)
{
DMA_CH3_CALLBACK();
}
}

◆ DMA_CH6_Int_En()

INLINE void DMA_CH6_Int_En ( void  )

enables DMA Channel 6 Interrupt.

Example

This example treats the DMA Channel 6 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH3 == (uint8)1)
{
DMA_CH3_CALLBACK();
}
}

◆ DMA_CH7_Int_Clr()

INLINE void DMA_CH7_Int_Clr ( void  )

clears DMA Channel 7 Interrupt flag.

Example

This example treats the DMA Channel 7 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH4 == (uint8)1)
{
DMA_CH4_CALLBACK();
}
}

◆ DMA_CH7_Int_Dis()

INLINE void DMA_CH7_Int_Dis ( void  )

disables DMA Channel 7 Interrupt.

Example

This example treats the DMA Channel 7 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH4 == (uint8)1)
{
DMA_CH4_CALLBACK();
}
}

◆ DMA_CH7_Int_En()

INLINE void DMA_CH7_Int_En ( void  )

enables DMA Channel 7 Interrupt.

Example

This example treats the DMA Channel 7 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH4 == (uint8)1)
{
DMA_CH4_CALLBACK();
}
}

◆ DMA_CH8_Int_Clr()

INLINE void DMA_CH8_Int_Clr ( void  )

clears DMA Channel 8 Interrupt flag.

Example

This example treats the DMA Channel 8 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH5 == (uint8)1)
{
DMA_CH5_CALLBACK();
}
}

◆ DMA_CH8_Int_Dis()

INLINE void DMA_CH8_Int_Dis ( void  )

disables DMA Channel 8 Interrupt.

Example

This example treats the DMA Channel 8 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH5 == (uint8)1)
{
DMA_CH5_CALLBACK();
}
}

◆ DMA_CH8_Int_En()

INLINE void DMA_CH8_Int_En ( void  )

enables DMA Channel 8 Interrupt.

Example

This example treats the DMA Channel 8 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH5 == (uint8)1)
{
DMA_CH5_CALLBACK();
}
}

◆ DMA_CH9_Int_Clr()

INLINE void DMA_CH9_Int_Clr ( void  )

clears DMA Channel 9 Interrupt flag.

Example

This example treats the DMA Channel 9 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH6 == (uint8)1)
{
DMA_CH6_CALLBACK();
}
}

◆ DMA_CH9_Int_Dis()

INLINE void DMA_CH9_Int_Dis ( void  )

disables DMA Channel 9 Interrupt.

Example

This example treats the DMA Channel 9 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH6 == (uint8)1)
{
DMA_CH6_CALLBACK();
}
}

◆ DMA_CH9_Int_En()

INLINE void DMA_CH9_Int_En ( void  )

enables DMA Channel 9 Interrupt.

Example

This example treats the DMA Channel 9 Interrupt.

void Example_Function(void)
{
if ((uint8)SCU->DMAIRC1.bit.CH6 == (uint8)1)
{
DMA_CH6_CALLBACK();
}
}

◆ DMA_Channel_Enable_Set()

INLINE void DMA_Channel_Enable_Set ( uint32  mask_ch)

enables DMA Channels.

Parameters
mask_chDMA channel Mask

Example

This example enables DMA Channel 0.

void Example_Function(void)
{
}

◆ DMA_Channel_MemSctGth_Set()

void DMA_Channel_MemSctGth_Set ( uint32  DMA_ChIdx,
TDMA_Entry Task_List,
uint32  NoOfTasks 
)

Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.

Note
This function violates [MISRA Rule 45]
Parameters
DMA_ChIdxDMA channel to be set up
Task_Listpoints to the task structure defined in RAM, see DMA_Task_Set
NoOfTasksnumber of tasks in the Task_List

Example

This example transfers the result of ADC1.Ch4 into a local variable once the ADC1.Ch4 conversion is done.

#define no_of_tasks 2
TDMA_Entry tasks[no_of_tasks];
static uint32 data0, data1;
static uint32 data2, data3;
void Example_Function(void)
{
// tasks[0] copies data0 to data1
data0 = 0x12345678;
data1 = 0;
// tasks[1] copies data2 to data3
data2 = 0xABCD;
data3 = 0;
DMA_Channel_MemSctGth_Set(DMA_CH8, &tasks[0], no_of_tasks);
//arm DMA channel 8
//enable DMA
}

◆ DMA_Channel_PerSctGth_Set()

void DMA_Channel_PerSctGth_Set ( uint32  DMA_ChIdx,
TDMA_Entry Task_List,
uint32  NoOfTasks 
)

Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.

Note
This function violates [MISRA Rule 45]
Parameters
DMA_ChIdxDMA channel to be set up
Task_Listpoints to the task structure defined in RAM, see DMA_Task_Set
NoOfTasksnumber of tasks in the Task_List

Example

This example transfers the four SPI values from RAM to SSC1.

#define no_of_tasks 4
TDMA_Entry tasks[no_of_tasks];
#define no_of_spi_trans 4
uint16 spi_data[no_of_spi_trans] = {0xAAAA, 0x5555, 0xCCCC, 0x3333};
void Example_Function(void)
{
//setup tasks for SPI transfer
DMA_Task_Set(&tasks[3], DMA_Cycle_Type_Basic, 0, (uint32)&spi_data[3], (uint32)&SSC1->TB.reg, 1, DMA_16Bit_Transfer, DMA_No_Inc);
//initialize DMA.Ch2 to tasks list
DMA_Channel_PerSctGth_Set(DMA_CH2, &tasks[0], no_of_tasks);
//arm DMA channel 2
//enable DMA
//trigger DMA.Ch2 by software request
}

◆ DMA_CHx_Entry_Alt()

INLINE uint32 DMA_CHx_Entry_Alt ( uint8  DMA_Ch)

This function returns the address inside the alternate structure in RAM for a given DMA channel.

Parameters
DMA_ChDMA channel number
Returns
uint32 32bit address to entry inside alternate structure

◆ DMA_CHx_Entry_Pri()

INLINE uint32 DMA_CHx_Entry_Pri ( uint8  DMA_Ch)

This function returns the address inside the primary structure in RAM for a given DMA channel.

Parameters
DMA_ChDMA channel number
Returns
uint32 32bit address to entry inside primary structure

◆ DMA_Init()

void DMA_Init ( void  )

Initializes the DMA structure in RAM and SFRs according to the ConfigWizard settings.

Note
This function violates [MISRA Rule 45], [MISRA Rule 52], [MISRA Rule 85]

◆ DMA_Master_En()

INLINE void DMA_Master_En ( void  )

Enabled the DMA master.

Example

This example transfers the result of ADC1.Ch4 into a local variable once the ADC1.Ch4 conversion is done.

void Example_Function(void)
{
uint16 adc_val;
//setup DMA channel 8 to transfer ADC1.Ch4 result into local variable
//arm DMA channel 8
//enable DMA
//start ADC1.Ch4 conversion
}

◆ DMA_Primary_Struct_Set()

INLINE void DMA_Primary_Struct_Set ( uint32  mask_ch)

points to the base address of the primary data structure.

Parameters
mask_chDMA channel Mask

Example

This example points to the base address of Channel 0.

void Example_Function(void)
{
}

◆ DMA_Primary_Struct_Usage_Set()

INLINE void DMA_Primary_Struct_Usage_Set ( uint32  mask_ch)

selects the primary data structure for the corresponding DMA channel.

Parameters
mask_chDMA channel Mask

Example

This example selects the primary data structure for DMA channel 0.

void Example_Function(void)
{
}

◆ DMA_Reset_Channel()

void DMA_Reset_Channel ( uint32  DMA_ChIdx,
uint32  trans_cnt 
)

Resets the primary structure in RAM for a given channel and rearms it.

Note
This function violates [MISRA Rule 45]
Parameters
DMA_ChIdxDMA channel to be set up
trans_cntnumber of transfers

Example

This example transfers the result of ADC1.Ch4 into a local variable, inside the interrupt service callback the DMA channel 8 gets reset.

void Example_Function(void)
{
uint16 adc_val;
//setup DMA channel 8 to transfer ADC1.Ch4 result into local variable
//arm DMA channel 8
//enable DMA
//start ADC1.Ch4 conversion
}
void DMA_Ch8_ISR(void)
{
//reset channel parameter and rearm channel
}

◆ DMA_Setup_Channel()

void DMA_Setup_Channel ( uint32  DMA_ChIdx,
uint32  addr_src,
uint32  addr_dst,
uint32  trans_cnt,
TDMA_Transfer_Size  datawidth,
TDMA_Increment_Mode  increment 
)

Sets up the desired DMA channel in the primary structure in RAM.

Note
This function violates [MISRA Rule 45]
Parameters
DMA_ChIdxDMA channel to be set up
addr_srcaddress pointing to the source location
addr_dstaddress pointing to the destination location
trans_cntnumber of transfers
datawidthdata width for each transfer, see TDMA_Transfer_Size
incrementincrementing scheme used for the transfer, see TDMA_Increment_Mode

Example

This example transfers the result of ADC1.Ch4 into a local variable once the ADC1.Ch4 conversion is done.

void Example_Function(void)
{
uint16 adc_val;
//setup DMA channel 8 to transfer ADC1.Ch4 result into local variable
//arm DMA channel 8
//enable DMA
//start ADC1.Ch4 conversion
}

◆ DMA_Software_Request_Set()

INLINE void DMA_Software_Request_Set ( uint32  mask_ch)

Set software request for DMA Channels.

Parameters
mask_chDMA channel Mask

Example

This example enables DMA Channel 0.

void Example_Function(void)
{
}

◆ DMA_Task_SctGth_Set()

TDMA_Entry* DMA_Task_SctGth_Set ( TDMA_Entry entry,
uint8  DMA_Ch,
TDMA_Entry Task_List,
uint32  NoOfTask 
)

Sets up a task to be used with memory scatter-gather mode.

The DMA scather-gather mode can be used to perform multiple but different DMA transfers initiated with one trigger.

The last task can be used to self-arm this scatter-gather transfer again.

This function can be used to define the last, self-arming task for the scather-gather mode.

Parameters
entrypointer to the task
DMA_Chthe DMA channel for with the task is setup
Task_Listpointer to the task list to be executed with this DMA transfer
NoOfTasknumber of tasks defined in the task list
Returns
pointer to the task

Example

This example performs an endless scatter-gather transfer and toggles P0.1.

#define no_of_tasks 4+1
TDMA_Entry MainTask_Ch0;
TDMA_Entry Tasks_Ch0[no_of_tasks];
uint8 lport_p01_high = 2;
uint8 lport_p01_low = 0;
void Example_Function(void)
{
//initializes the primary structure task (MainTask_Ch0) to be used to reset the scatter-gather sequence
DMA_Task_SctGth_Set(&MainTask_Ch0, DMA_CH0, &Tasks_Ch0[0], DMA_CH0_TASK_NoOfTasks);
//initializes the task list 0
//tasks[3..0] are the tasks actually doing some real work, here causing P0.1 to toggle
DMA_Task_Set(&Tasks_Ch0[0], DMA_Cycle_Type_MemSctGthAlt, 0, (uint32)&lport_p01_high, (uint32)&PORT->P0_DATA.reg, 1, DMA_8Bit_Transfer, DMA_No_Inc);
DMA_Task_Set(&Tasks_Ch0[1], DMA_Cycle_Type_MemSctGthAlt, 0, (uint32)&lport_p01_low, (uint32)&PORT->P0_DATA.reg, 1, DMA_8Bit_Transfer, DMA_No_Inc);
DMA_Task_Set(&Tasks_Ch0[2], DMA_Cycle_Type_MemSctGthAlt, 0, (uint32)&lport_p01_high, (uint32)&PORT->P0_DATA.reg, 1, DMA_8Bit_Transfer, DMA_No_Inc);
DMA_Task_Set(&Tasks_Ch0[3], DMA_Cycle_Type_MemSctGthAlt, 0, (uint32)&lport_p01_low, (uint32)&PORT->P0_DATA.reg, 1, DMA_8Bit_Transfer, DMA_No_Inc);
//tasks[4] are used to reset Channel1, the fast that the last task is NOT of type 'DMA_Cycle_Type_Basic' keeps the scatter-gather running for ever
DMA_Task_Set(&Tasks_Ch0[4], DMA_Cycle_Type_MemSctGthAlt, 2, (uint32)&MainTask_Ch0, ui32_DMA_CHx_Entry_Pri(DMA_CH0), 4, DMA_32Bit_Transfer, DMA_Src_Dst_Inc);
//preloads the primary structure with the task list for Channel0
DMA_Channel_MemSctGth_Set(DMA_CH0, &Tasks_Ch0[0], DMA_CH0_TASK_NoOfTasks);
//enable DMA Channel0
//enable DMA master
//trigger DMA Channel0 by software
}

◆ DMA_Task_Set()

TDMA_Entry* DMA_Task_Set ( TDMA_Entry entry,
TDMA_Cycle_Types  cycle_type,
uint8  arb_rate,
uint32  addr_src,
uint32  addr_dst,
uint32  trans_cnt,
TDMA_Transfer_Size  datawidth,
TDMA_Increment_Mode  increment 
)

Sets up a task to be used in the Scatter-Gather modes.

Parameters
entrypointer to the task structure TDMA_Entry
cycle_typedefines the type of DMA transfer to be performed, see TDMA_Cycle_Types
arb_ratearbitration rate, defines after how many DMA transfer it rearbitrates, 2^arb_rate
addr_srcaddress pointing to the source location
addr_dstaddress pointing to the destination location
trans_cntnumber of transfers
datawidthdata width for each transfer, see TDMA_Transfer_Size
incrementincrementing scheme used for the transfer, see TDMA_Increment_Mode

Example

This example transfers the four SPI values from RAM to SSC1.

#define no_of_tasks 4
TDMA_Entry tasks[no_of_tasks];
#define no_of_spi_trans 4
uint16 spi_data[no_of_spi_trans] = {0xAAAA, 0x5555, 0xCCCC, 0x3333};
void Example_Function(void)
{
//setup tasks for SPI transfer
DMA_Task_Set(&tasks[3], DMA_Cycle_Type_Basic, 0, (uint32)&spi_data[3], (uint32)&SSC1->TB.reg, 1, DMA_16Bit_Transfer, DMA_No_Inc);
//initialize DMA.Ch2 to tasks list
DMA_Channel_PerSctGth_Set(DMA_CH2, &tasks[0], no_of_tasks);
//arm DMA channel 2
//enable DMA
//trigger DMA.Ch2 by software request
}
DMA_CH6_Int_Clr
INLINE void DMA_CH6_Int_Clr(void)
clears DMA Channel 6 Interrupt flag.
Definition: dma.h:405
DMA_Alternate_Struct_Usage_Set
INLINE void DMA_Alternate_Struct_Usage_Set(uint32 mask_ch)
selects the alternate data structure for the corresponding DMA channel.
Definition: dma.h:1293
DMA_Master_En
INLINE void DMA_Master_En(void)
Enabled the DMA master.
Definition: dma.h:1610
DMA_CH12_Int_Dis
INLINE void DMA_CH12_Int_Dis(void)
disables DMA Channel 12 Interrupt.
Definition: dma.h:1146
DMA_CH4_Int_En
INLINE void DMA_CH4_Int_En(void)
enables DMA Channel 4 Interrupt.
Definition: dma.h:763
ADC1_CH4
#define ADC1_CH4
ADC1 channel selection macro, channel 4 - P2.4.
Definition: adc1.h:154
DMA_Cycle_Type_PerSctGthAlt
Definition: dma.h:216
DMA_CH5_Int_Clr
INLINE void DMA_CH5_Int_Clr(void)
clears DMA Channel 5 Interrupt flag.
Definition: dma.h:383
DMA_CH4_Int_Dis
INLINE void DMA_CH4_Int_Dis(void)
disables DMA Channel 4 Interrupt.
Definition: dma.h:786
DMA_CH6_Int_Dis
INLINE void DMA_CH6_Int_Dis(void)
disables DMA Channel 6 Interrupt.
Definition: dma.h:876
DMA_CH11_Int_Dis
INLINE void DMA_CH11_Int_Dis(void)
disables DMA Channel 11 Interrupt.
Definition: dma.h:1101
DMA_CH9_Int_En
INLINE void DMA_CH9_Int_En(void)
enables DMA Channel 9 Interrupt.
Definition: dma.h:988
DMA_CH11_Int_En
INLINE void DMA_CH11_Int_En(void)
enables DMA Channel 11 Interrupt.
Definition: dma.h:1078
DMA_MASK_CH0
#define DMA_MASK_CH0
DMA channel Mask macro, DMA CH0 MASK.
Definition: dma.h:143
DMA_Channel_MemSctGth_Set
void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.
DMA_CH10_Int_Clr
INLINE void DMA_CH10_Int_Clr(void)
clears DMA Channel 10 Interrupt flag.
Definition: dma.h:493
DMA_CH8
#define DMA_CH8
DMA channel selection macro, DMA CH8.
Definition: dma.h:128
PORT
#define PORT
Definition: tle986x.h:6003
DMA_Task_SctGth_Set
TDMA_Entry * DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
Sets up a task to be used with memory scatter-gather mode.
DMA_CH2_Int_En
INLINE void DMA_CH2_Int_En(void)
enables DMA Channel 2 Interrupt.
Definition: dma.h:673
DMA_CH5_Int_En
INLINE void DMA_CH5_Int_En(void)
enables DMA Channel 5 Interrupt.
Definition: dma.h:808
DMA_CH5_Int_Dis
INLINE void DMA_CH5_Int_Dis(void)
disables DMA Channel 5 Interrupt.
Definition: dma.h:831
DMA_Cycle_Type_Basic
Definition: dma.h:210
DMA_CH2_Int_Dis
INLINE void DMA_CH2_Int_Dis(void)
disables DMA Channel 2 Interrupt.
Definition: dma.h:696
DMA_CH10_Int_En
INLINE void DMA_CH10_Int_En(void)
enables DMA Channel 10 Interrupt.
Definition: dma.h:1033
DMA_CH3_Int_Dis
INLINE void DMA_CH3_Int_Dis(void)
disables DMA Channel 3 Interrupt.
Definition: dma.h:741
DMA_CH0_Int_Dis
INLINE void DMA_CH0_Int_Dis(void)
disables DMA Channel 0 Interrupt.
Definition: dma.h:606
uint16
unsigned short uint16
16 bit unsigned value
Definition: types.h:140
ADC1
#define ADC1
Definition: tle986x.h:5990
DMA_Src_Dst_Inc
Definition: dma.h:201
DMA_Software_Request_Set
INLINE void DMA_Software_Request_Set(uint32 mask_ch)
Set software request for DMA Channels.
Definition: dma.h:1253
DMA_CH1_Int_Clr
INLINE void DMA_CH1_Int_Clr(void)
clears DMA Channel 1 Interrupt flag.
Definition: dma.h:295
DMA_Channel_Enable_Set
INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
enables DMA Channels.
Definition: dma.h:1233
uint8
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
DMA_Reset_Channel
void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt)
Resets the primary structure in RAM for a given channel and rearms it.
DMA_CH12_Int_En
INLINE void DMA_CH12_Int_En(void)
enables DMA Channel 12 Interrupt.
Definition: dma.h:1123
DMA_CH8_Int_Dis
INLINE void DMA_CH8_Int_Dis(void)
disables DMA Channel 8 Interrupt.
Definition: dma.h:966
DMA_CH6_Int_En
INLINE void DMA_CH6_Int_En(void)
enables DMA Channel 6 Interrupt.
Definition: dma.h:853
DMA_CH9_Int_Clr
INLINE void DMA_CH9_Int_Clr(void)
clears DMA Channel 9 Interrupt flag.
Definition: dma.h:471
DMA_Primary_Struct_Usage_Set
INLINE void DMA_Primary_Struct_Usage_Set(uint32 mask_ch)
selects the primary data structure for the corresponding DMA channel.
Definition: dma.h:1273
uint32
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
DMA_CH7_Int_Dis
INLINE void DMA_CH7_Int_Dis(void)
disables DMA Channel 7 Interrupt.
Definition: dma.h:921
DMA_CH12_Int_Clr
INLINE void DMA_CH12_Int_Clr(void)
clears DMA Channel 12 Interrupt flag.
Definition: dma.h:537
SSC1
#define SSC1
Definition: tle986x.h:6006
DMA_CH8_Int_En
INLINE void DMA_CH8_Int_En(void)
enables DMA Channel 8 Interrupt.
Definition: dma.h:943
DMA_CH3_Int_En
INLINE void DMA_CH3_Int_En(void)
enables DMA Channel 3 Interrupt.
Definition: dma.h:718
DMA_Cycle_Type_MemSctGthAlt
Definition: dma.h:214
DMA_CH0
#define DMA_CH0
DMA channel selection macro, DMA CH0.
Definition: dma.h:112
DMA_CH1_Int_En
INLINE void DMA_CH1_Int_En(void)
enables DMA Channel 1 Interrupt.
Definition: dma.h:628
DMA_8Bit_Transfer
Definition: dma.h:178
DMA_CH8_Int_Clr
INLINE void DMA_CH8_Int_Clr(void)
clears DMA Channel 8 Interrupt flag.
Definition: dma.h:449
DMA_MASK_CH2
#define DMA_MASK_CH2
DMA channel Mask macro, DMA CH2 MASK.
Definition: dma.h:147
DMA_CH1_Int_Dis
INLINE void DMA_CH1_Int_Dis(void)
disables DMA Channel 1 Interrupt.
Definition: dma.h:651
ADC1_SetSocSwMode
INLINE void ADC1_SetSocSwMode(uint8 Ch)
Starts ADC1 software mode conversion.
Definition: adc1.h:3968
SCU
#define SCU
Definition: tle986x.h:6004
DMA_CH3_Int_Clr
INLINE void DMA_CH3_Int_Clr(void)
clears DMA Channel 3 Interrupt flag.
Definition: dma.h:339
DMA_32Bit_Transfer
Definition: dma.h:180
DMA_CH10_Int_Dis
INLINE void DMA_CH10_Int_Dis(void)
disables DMA Channel 10 Interrupt.
Definition: dma.h:1056
DMA_CH0_Int_Clr
INLINE void DMA_CH0_Int_Clr(void)
clears DMA Channel 0 Interrupt flag.
Definition: dma.h:273
DMA_CH4_Int_Clr
INLINE void DMA_CH4_Int_Clr(void)
clears DMA Channel 4 Interrupt flag.
Definition: dma.h:361
DMA_CH2_Int_Clr
INLINE void DMA_CH2_Int_Clr(void)
clears DMA Channel 2 Interrupt flag.
Definition: dma.h:317
DMA_Primary_Struct_Set
INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
points to the base address of the primary data structure.
Definition: dma.h:1213
DMA_No_Inc
Definition: dma.h:198
DMA_CH2
#define DMA_CH2
DMA channel selection macro, DMA CH2.
Definition: dma.h:116
DMA_CH7_Int_Clr
INLINE void DMA_CH7_Int_Clr(void)
clears DMA Channel 7 Interrupt flag.
Definition: dma.h:427
TDMA_Entry
This structure lists the DMA transfer memory locations.
Definition: dma.h:245
DMA_MASK_CH8
#define DMA_MASK_CH8
DMA channel Mask macro, DMA CH8 MASK.
Definition: dma.h:159
DMA_Channel_PerSctGth_Set
void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
DMA_CH11_Int_Clr
INLINE void DMA_CH11_Int_Clr(void)
clears DMA Channel 11 Interrupt flag.
Definition: dma.h:515
DMA_16Bit_Transfer
Definition: dma.h:179
DMA_CH0_Int_En
INLINE void DMA_CH0_Int_En(void)
enables DMA Channel 0 Interrupt.
Definition: dma.h:583
DMA_Setup_Channel
void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up the desired DMA channel in the primary structure in RAM.
DMA_CH7_Int_En
INLINE void DMA_CH7_Int_En(void)
enables DMA Channel 7 Interrupt.
Definition: dma.h:898
DMA_CH9_Int_Dis
INLINE void DMA_CH9_Int_Dis(void)
disables DMA Channel 9 Interrupt.
Definition: dma.h:1011
DMA_Task_Set
TDMA_Entry * DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up a task to be used in the Scatter-Gather modes.