TLE986x Device Family SDK
Data Fields
DMA_Type Struct Reference

Detailed Description

Direct Memeory Access (DMA)

#include <tle986x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   MASTER_ENABLE: 1
 
      __IM   uint32_t: 3
 
      __IM uint32_t   STATE: 4
 
      __IM uint32_t   CHNLS_MINUS1: 5
 
   }   bit
 
STATUS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   MASTER_ENABLE: 1
 
      __IM   uint32_t: 4
 
      __OM uint32_t   CHN1_PROT_CTRL: 3
 
   }   bit
 
CFG
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 9
 
      __IOM uint32_t   CTRL_BASE_PTR: 23
 
   }   bit
 
CTRL_BASE_PTR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   ALT_CTRL_BASE_PTR: 32
 
   }   bit
 
ALT_CTRL_BASE_PTR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   WAITONREQ_STATUS: 14
 
   }   bit
 
WAITONREQ_STATUS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CHNL_SW_REQUEST: 14
 
   }   bit
 
CHNL_SW_REQUEST
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHNL_USEBURST_SET: 14
 
   }   bit
 
CHNL_USEBURST_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CHNL_USEBURST_CLR: 14
 
   }   bit
 
CHNL_USEBURST_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHNL_REQ_MASK_SET: 14
 
   }   bit
 
CHNL_REQ_MASK_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CHNL_REQ_MASK_CLR: 14
 
   }   bit
 
CHNL_REQ_MASK_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHNL_ENABLE_SET: 14
 
   }   bit
 
CHNL_ENABLE_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CHNL_ENABLE_CLR: 14
 
   }   bit
 
CHNL_ENABLE_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHNL_PRI_ALT_SET: 14
 
   }   bit
 
CHNL_PRI_ALT_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CHNL_PRI_ALT_CLR: 14
 
   }   bit
 
CHNL_PRI_ALT_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHNL_PRIORITY_SET: 14
 
   }   bit
 
CHNL_PRIORITY_SET
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CHNL_PRIORITY_CLR: 14
 
   }   bit
 
CHNL_PRIORITY_CLR
 
__IM uint32_t RESERVED [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ERR_CLR: 1
 
   }   bit
 
ERR_CLR
 

Field Documentation

◆ ALT_CTRL_BASE_PTR [1/2]

__IM uint32_t ALT_CTRL_BASE_PTR

[31..0] Base Address of the Alternate Data Structure

◆ ALT_CTRL_BASE_PTR [2/2]

union { ... } ALT_CTRL_BASE_PTR

◆ bit [1/17]

struct { ... } bit

◆ bit [2/17]

struct { ... } bit

◆ bit [3/17]

struct { ... } bit

◆ bit [4/17]

struct { ... } bit

◆ bit [5/17]

struct { ... } bit

◆ bit [6/17]

struct { ... } bit

◆ bit [7/17]

struct { ... } bit

◆ bit [8/17]

struct { ... } bit

◆ bit [9/17]

struct { ... } bit

◆ bit [10/17]

struct { ... } bit

◆ bit [11/17]

struct { ... } bit

◆ bit [12/17]

struct { ... } bit

◆ bit [13/17]

struct { ... } bit

◆ bit [14/17]

struct { ... } bit

◆ bit [15/17]

struct { ... } bit

◆ bit [16/17]

struct { ... } bit

◆ bit [17/17]

struct { ... } bit

◆ CFG

union { ... } CFG

◆ CHN1_PROT_CTRL

__OM uint32_t CHN1_PROT_CTRL

[7..5] CHN1_PROT_CTRL

◆ CHNL_ENABLE_CLR [1/2]

__OM uint32_t CHNL_ENABLE_CLR

[13..0] CHNL_ENABLE_CLR

◆ CHNL_ENABLE_CLR [2/2]

union { ... } CHNL_ENABLE_CLR

◆ CHNL_ENABLE_SET [1/2]

__IOM uint32_t CHNL_ENABLE_SET

[13..0] CHNL_ENABLE_SET: 0b0=on read: Channel C is disabled., 0b1=on read: Channel C is enabled., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to disable a channel., 0b1=on write: Enables channel C.,

◆ CHNL_ENABLE_SET [2/2]

union { ... } CHNL_ENABLE_SET

◆ CHNL_PRI_ALT_CLR [1/2]

__OM uint32_t CHNL_PRI_ALT_CLR

[13..0] CHNL_PRI_ALT_CLR

◆ CHNL_PRI_ALT_CLR [2/2]

union { ... } CHNL_PRI_ALT_CLR

◆ CHNL_PRI_ALT_SET [1/2]

__IOM uint32_t CHNL_PRI_ALT_SET

[13..0] CHNL_PRI_ALT_SET: 0b0=on read: DMA channel C is using the primary data structure., 0b1=on read: DMA channel C is using the alternate data structure., 0b0=on write: No effect. Use the CHNL_PRI_ALT_CLR Register to set bit [C] to 0., 0b1=on write: Selects the alternate data structure for channel C.,

◆ CHNL_PRI_ALT_SET [2/2]

union { ... } CHNL_PRI_ALT_SET

◆ CHNL_PRIORITY_CLR [1/2]

__OM uint32_t CHNL_PRIORITY_CLR

[13..0] CHNL_PRIORITY_CLR

◆ CHNL_PRIORITY_CLR [2/2]

union { ... } CHNL_PRIORITY_CLR

◆ CHNL_PRIORITY_SET [1/2]

__IOM uint32_t CHNL_PRIORITY_SET

[13..0] CHNL_PRIORITY_SET: 0b0=on read: DMA channel C is using the default priority level., 0b1=on read: DMA channel C is using a high priority level., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to set channel C to the default priority level., 0b1=on write: Channel C uses the high priority level.,

◆ CHNL_PRIORITY_SET [2/2]

union { ... } CHNL_PRIORITY_SET

◆ CHNL_REQ_MASK_CLR [1/2]

__OM uint32_t CHNL_REQ_MASK_CLR

[13..0] CHNL_REQ_MASK_CLR

◆ CHNL_REQ_MASK_CLR [2/2]

union { ... } CHNL_REQ_MASK_CLR

◆ CHNL_REQ_MASK_SET [1/2]

__IOM uint32_t CHNL_REQ_MASK_SET

[13..0] CHNL_REQ_MASK_SET: 0b0=on read: External requests are enabled for channel C., 0b1=on read: External requests are disabled for channel C., 0b0=on write: No effect. Use the CHNL_REQ_MASK_CLR Register to enable DMA requests., 0b1=on write: Disables dma_req[C] and dma_sreq[C] from generating DMA requests.,

◆ CHNL_REQ_MASK_SET [2/2]

union { ... } CHNL_REQ_MASK_SET

◆ CHNL_SW_REQUEST [1/2]

__OM uint32_t CHNL_SW_REQUEST

[13..0] CHNL_SW_REQUEST

◆ CHNL_SW_REQUEST [2/2]

union { ... } CHNL_SW_REQUEST

◆ CHNL_USEBURST_CLR [1/2]

__OM uint32_t CHNL_USEBURST_CLR

[13..0] CHNL_USEBURST_CLR

◆ CHNL_USEBURST_CLR [2/2]

union { ... } CHNL_USEBURST_CLR

◆ CHNL_USEBURST_SET [1/2]

__IOM uint32_t CHNL_USEBURST_SET

[13..0] CHNL_USEBURST_SET: 0b0=on read: DMA channel n responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2, or single, bus transfers., 0b1=on read: DMA channel n does not respond to requests that it receives on dma_req[C] or dma_sreq[C]. The controller only reponds to dma_req[C] requests and performs 2 transfers., 0b0=on write: No effect. Use the CHNL_USEBURST_CLR Register to set bit [C] to 0., 0b1=on write: Disables dma_sreq[C] from generating DMA requests. The controller

◆ CHNL_USEBURST_SET [2/2]

union { ... } CHNL_USEBURST_SET

◆ CHNLS_MINUS1

__IM uint32_t CHNLS_MINUS1

[20..16] Available Channels minus 1

◆ CTRL_BASE_PTR [1/2]

__IOM uint32_t CTRL_BASE_PTR

[31..9] CTRL_BASE_PTR

◆ CTRL_BASE_PTR [2/2]

union { ... } CTRL_BASE_PTR

◆ ERR_CLR [1/2]

__IOM uint32_t ERR_CLR

[0..0] ERR_CLR: 0b0=on read: dma_err is LOW., 0b1=on read: dma_err is HIGH., 0b0=on write: No effect, status of dma_err is unchanged., 0b1=on write: Sets dma_err LOW.,

◆ ERR_CLR [2/2]

union { ... } ERR_CLR

◆ MASTER_ENABLE [1/2]

__IM uint32_t MASTER_ENABLE

[0..0] Enable Status of the Controller

◆ MASTER_ENABLE [2/2]

__OM uint32_t MASTER_ENABLE

[0..0] Enable for the Controller

◆ reg

(@ 0x00000000) DMA Status

(@ 0x00000004) DMA Configuration

(@ 0x00000008) Channel Control Data Base Pointer

(@ 0x0000000C) Channel Alternate Control Data Base Pointer

(@ 0x00000010) Channel Wait on Request Status

(@ 0x00000014) Channel Software Request

(@ 0x00000018) Channel Useburst Set

(@ 0x0000001C) Channel Useburst Clear

(@ 0x00000020) Channel Request Mask Set

(@ 0x00000024) Channel Request Mask Clear

(@ 0x00000028) Channel Enable Set

(@ 0x0000002C) Channel Enable Clear

(@ 0x00000030) Channel Primary-Alternate Set

(@ 0x00000034) Channel Primary-Alternate Clear

(@ 0x00000038) Channel Priority Set

(@ 0x0000003C) Channel Priority Clear

(@ 0x0000004C) Bus Error Clear

◆ RESERVED

__IM uint32_t RESERVED[3]

◆ STATE

__IM uint32_t STATE

[7..4] Current State of the Control State Machine

◆ STATUS

union { ... } STATUS

◆ uint32_t

__IM uint32_t

◆ WAITONREQ_STATUS [1/2]

__IM uint32_t WAITONREQ_STATUS

[13..0] Channel Wait on Request Status

◆ WAITONREQ_STATUS [2/2]

union { ... } WAITONREQ_STATUS

The documentation for this struct was generated from the following file: