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TLE986x Device Family SDK
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CPU Core (CPU)
#include <tle986x.h>
[31..0] Data Address for an MPU Fault
[31..0] Data Address for a precise BusFault
union { ... } AFSR |
union { ... } AIRCR |
union { ... } BFAR |
[8..8] Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
union { ... } CCR |
union { ... } CFSR |
union { ... } CPUID |
union { ... } DFSR |
[4..4] Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
union { ... } HFSR |
union { ... } ICSR |
union { ... } ICT |
[3..3] Interrupt Set for ADC1
[3..3] Interrupt Clear for ADC1
[3..3] Interrupt Set Pending for ADC1
[3..3] Interrupt Clear Pending for ADC1
[2..2] Interrupt Set for MU, ADC2
[2..2] Interrupt Clear for MU, ADC2
[2..2] Interrupt Set Pending for MU, ADC2
[2..2] Interrupt Clear Pending for MU, ADC2
[14..14] Interrupt Set for Bridge Driver
[14..14] Interrupt Clear for Bridge Driver
[14..14] Interrupt Set Pending for Bridge Driver
[14..14] Interrupt Clear Pending for Bridge Driver
[4..4] Interrupt Set for CCU6 SR0
[4..4] Interrupt Clear for CCU6 SR0
[4..4] Interrupt Set Pending for CCU6 SR0
[4..4] Interrupt Clear Pending for CCU6 SR0
[5..5] Interrupt Set for CCU6 SR1
[5..5] Interrupt Clear for CCU6 SR1
[5..5] Interrupt Set Pending for CCU6 SR1
[5..5] Interrupt Clear Pending for CCU6 SR1
[6..6] Interrupt Set for CCU6 SR2
[6..6] Interrupt Clear for CCU6 SR2
[6..6] Interrupt Set Pending for CCU6 SR2
[6..6] Interrupt Clear Pending for CCU6 SR2
[7..7] Interrupt Set for CCU6 SR3
[7..7] Interrupt Clear for CCU6 SR3
[7..7] Interrupt Set Pending for CCU6 SR3
[7..7] Interrupt Clear Pending for CCU6 SR3
[15..15] Interrupt Set for DMA
[15..15] Interrupt Clr for DMA
[15..15] Interrupt Set Pend for DMA
[15..15] Interrupt Clr Pend for DMA
[12..12] Interrupt Set for External Int 0
[12..12] Interrupt Clear for External Int 0
[12..12] Interrupt Set Pending for External Int 0
[12..12] Interrupt Clear Pending for External Int 0
[13..13] Interrupt Set for External Int 1
[13..13] Interrupt Clear for External Int 1
[13..13] Interrupt Set Pending for External Int 1
[13..13] Interrupt Clear Pending for External Int 1
[0..0] Interrupt Set for GPT1
[0..0] Interrupt Clear for GPT1
[0..0] Interrupt Set Pending for GPT1
[0..0] Interrupt Clear Pending for GPT1
[1..1] Interrupt Set for GPT2
[1..1] Interrupt Clear for GPT2
[1..1] Interrupt Set Pending for GPT2
[1..1] Interrupt Clear Pending for GPT2
[8..8] Interrupt Set for SSC1
[8..8] Interrupt Clear for SSC1
[8..8] Interrupt Set Pending for SSC1
[8..8] Interrupt Clear Pending for SSC1
[9..9] Interrupt Set for SSC2
[9..9] Interrupt Clear for SSC2
[9..9] Interrupt Set Pending for SSC2
[9..9] Interrupt Clear Pending for SSC2
[10..10] Interrupt Set for UART1
[10..10] Interrupt Clear for UART1
[10..10] Interrupt Set Pending for UART1
[10..10] Interrupt Clear Pending for UART1
[11..11] Interrupt Set for UART2
[11..11] Interrupt Clear for UART2
[11..11] Interrupt Set Pending for UART2
[11..11] Interrupt Clear Pending for UART2
union { ... } MMFAR |
union { ... } NVIC_IABR0 |
union { ... } NVIC_ICER0 |
union { ... } NVIC_ICPR0 |
union { ... } NVIC_IPR0 |
union { ... } NVIC_IPR1 |
union { ... } NVIC_IPR2 |
union { ... } NVIC_IPR3 |
union { ... } NVIC_ISER0 |
union { ... } NVIC_ISPR0 |
(@ 0x00000004) Interrupt Controller Type
(@ 0x00000010) SysTick Control and Status
(@ 0x00000014) SysTick Reload Value
(@ 0x00000018) SysTick Current Value
(@ 0x0000001C) SysTick Calibration Value
(@ 0x00000100) Interrupt Set-Enable
(@ 0x00000180) Interrupt Clear-Enable
(@ 0x00000200) Interrupt Set-Pending
(@ 0x00000280) Interrupt Clear-Pending
(@ 0x00000300) Active Bit Register Interrupt Active Flags
(@ 0x00000400) Interrupt Priority
(@ 0x00000404) Interrupt Priority
(@ 0x00000408) Interrupt Priority
(@ 0x0000040C) Interrupt Priority
(@ 0x00000D00) CPU ID Base Register
(@ 0x00000D04) Interrupt Control State Register
(@ 0x00000D08) Vector Table Offset Register
(@ 0x00000D0C) Application Interrupt/Reset Control Register
(@ 0x00000D10) System Control Register
(@ 0x00000D14) Configuration Control Register
(@ 0x00000D18) System Handler Priority Register 1
(@ 0x00000D1C) System Handler Priority Register 2
(@ 0x00000D20) System Handler Priority Register 3
(@ 0x00000D24) System Handler Control and State Register
(@ 0x00000D28) Configurable Fault Status Register
(@ 0x00000D2C) Hard Fault Status Register
(@ 0x00000D30) Debug Fault Status Register
(@ 0x00000D34) MemManage Fault Status Register
(@ 0x00000D38) Bus Fault Status Register
(@ 0x00000D3C) Auxiliary Fault Status Register
union { ... } SCR |
union { ... } SHCSR |
union { ... } SHPR1 |
union { ... } SHPR2 |
union { ... } SHPR3 |
union { ... } SYSTICK_CAL |
union { ... } SYSTICK_CS |
union { ... } SYSTICK_CUR |
union { ... } SYSTICK_RL |
__IM uint32_t |
union { ... } VTOR |