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TLE986x Device Family SDK
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112 #include "adc1_defines.h"
120 #define ADC1_VDH_Attenuator_Range_0_30V (1u)
122 #define ADC1_VDH_Attenuator_Range_0_20V (0u)
167 #define ADC1_P20 ADC1_CH0
169 #define ADC1_CSA ADC1_CH1
171 #define ADC1_P22 ADC1_CH2
173 #define ADC1_P23 ADC1_CH3
175 #define ADC1_P24 ADC1_CH4
177 #define ADC1_P25 ADC1_CH5
179 #define ADC1_VDH ADC1_CH6
183 #define ADC1_MASK_CH0 ((uint32)1u << ADC1_CH0)
185 #define ADC1_MASK_CH1 ((uint32)1u << ADC1_CH1)
187 #define ADC1_MASK_CH2 ((uint32)1u << ADC1_CH2)
189 #define ADC1_MASK_CH3 ((uint32)1u << ADC1_CH3)
191 #define ADC1_MASK_CH4 ((uint32)1u << ADC1_CH4)
193 #define ADC1_MASK_CH5 ((uint32)1u << ADC1_CH5)
195 #define ADC1_MASK_CH6 ((uint32)1u << ADC1_CH6)
198 #define ADC1_MASK_P20 (ADC1_MASK_CH0)
200 #define ADC1_MASK_CSA (ADC1_MASK_CH1)
202 #define ADC1_MASK_P22 (ADC1_MASK_CH2)
204 #define ADC1_MASK_P23 (ADC1_MASK_CH3)
206 #define ADC1_MASK_P24 (ADC1_MASK_CH4)
208 #define ADC1_MASK_P25 (ADC1_MASK_CH5)
210 #define ADC1_MASK_VDH (ADC1_MASK_CH6)
213 #define ADC1_VREF_5000mV 5000u
215 #define ADC1_VREF_22000mV 22000u
217 #define ADC1_VREF_30000mV 30000u
#define ADC1_IE_CH4_IE_Pos
Definition: tle986x.h:6143
#define ADC1_RES_OUT1_WFR1_Pos
Definition: tle986x.h:6188
#define ADC1_CTRL_STS_SOC_Pos
Definition: tle986x.h:6076
INLINE void ADC1_Ch3_Overwrite_Set(void)
Sets the ADC1 channel 3 result register to "overwrite".
Definition: adc1.h:2877
#define ADC1_RES_OUT5_WFR5_Pos
Definition: tle986x.h:6224
#define ADC1_SQ5_8_SQ6_Msk
Definition: tle986x.h:6270
#define ADC1_RES_OUT0_WFR0_Pos
Definition: tle986x.h:6179
#define ADC1_SQ_FB_CHx_Pos
Definition: tle986x.h:6274
#define ADC1_RES_OUT0_OUT_CH0_Msk
Definition: tle986x.h:6182
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk
Definition: tle986x.h:8087
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:426
INLINE bool ADC1_GetSwModeResult_mV(uint16 *pVar_mV)
Get ADC1 software mode result in Millivolt.
Definition: adc1.h:3993
INLINE void ADC1_Ch4_WaitForRead_Set(void)
Sets the ADC1 channel 4 result register to "wait for read".
Definition: adc1.h:2907
#define ADC1_CHx_ESM_ESM_0_Msk
Definition: tle986x.h:6070
#define ADC1_SQ5_8_SQ8_Msk
Definition: tle986x.h:6266
INLINE uint16 ADC1_Ch6_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1572
#define ADC1_RES_OUT2_OUT_CH2_Pos
Definition: tle986x.h:6199
INLINE void ADC1_Ch3_Int_Clr(void)
clears ADC1 Channel 3 Interrupt flag.
Definition: adc1.h:3350
INLINE void ADC1_Ch2_DataWidth_10bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 10-bit.
Definition: adc1.h:2226
#define ADC1_GLOBCTR_ANON_Msk
Definition: tle986x.h:6099
INLINE void ADC1_Sequence3_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 3, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1270
INLINE uint16 ADC1_P22_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1693
#define ADC1_IE_ESM_IE_Pos
Definition: tle986x.h:6133
INLINE void ADC1_Ch1_Int_En(void)
enables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3527
#define ADC1_ICLR_CH6_ICLR_Pos
Definition: tle986x.h:6118
INLINE void ADC1_EIM_Int_En(void)
enables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3798
#define ADC1_STC_0_3_ch2_Msk
Definition: tle986x.h:6288
INLINE void ADC1_Ch5_Int_En(void)
enables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3707
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk
Definition: tle986x.h:8091
#define ADC1_ICLR_CH4_ICLR_Msk
Definition: tle986x.h:6123
INLINE void ADC1_Ch1_DataWidth_10bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 10-bit.
Definition: adc1.h:2174
INLINE uint16 ADC1_CSA_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1663
INLINE void ADC1_Ch5_Int_Clr(void)
clears ADC1 Channel 5 Interrupt flag.
Definition: adc1.h:3393
INLINE void ADC1_Ch6_DataWidth_8bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 8-bit.
Definition: adc1.h:2408
#define ADC1_DWSEL_ch3_Msk
Definition: tle986x.h:6090
TADC1_TRIGG_SEL
This enum lists the options for the trigger select for EIM and ESM.
Definition: adc1.h:239
#define ADC1_RES_OUT6_OUT_CH6_Msk
Definition: tle986x.h:6236
#define ADC1_DWSEL_ch3_Pos
Definition: tle986x.h:6089
INLINE void ADC1_Ch1_DataWidth_8bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 8-bit.
Definition: adc1.h:2148
General type declarations.
INLINE void ADC1_Ch2_Int_Clr(void)
clears ADC1 Channel 2 Interrupt flag.
Definition: adc1.h:3328
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos
Definition: tle986x.h:8090
#define ADC1_CTRL_STS_PD_N_Msk
Definition: tle986x.h:6079
INLINE void ADC1_Sequence2_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 2, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1247
#define ADC1_CHx_EIM_CHx_Msk
Definition: tle986x.h:6065
INLINE void ADC1_EIM_Int_Clr(void)
clears Exceptional Interrupt Measurement (EIM) flag.
Definition: adc1.h:3438
#define ADC1_DWSEL_ch1_Msk
Definition: tle986x.h:6094
INLINE void ADC1_Ch4_DataWidth_10bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 10-bit.
Definition: adc1.h:2330
#define ADC1_SQ_FB_EIM_ACTIVE_Msk
Definition: tle986x.h:6281
#define ADC1_SQ1_4_SQ3_Msk
Definition: tle986x.h:6259
INLINE bool ADC1_Busy(void)
Reads the overall status of the ADC1.
Definition: adc1.h:4000
#define ADC1_STC_4_7_ch6_Msk
Definition: tle986x.h:6297
INLINE uint16 ADC1_Ch2_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1452
INLINE void ADC1_ESM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Set ADC1 ESM Trigger Selection.
Definition: adc1.h:4024
INLINE void ADC1_ESM_Int_Dis(void)
disables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3867
INLINE uint8 ADC1_Current_Active_Channel_Sts(void)
Reads the currently active channel.
Definition: adc1.h:1179
#define ADC1_ICLR_CH3_ICLR_Msk
Definition: tle986x.h:6125
#define ADC1_RES_OUT6_WFR6_Msk
Definition: tle986x.h:6234
INLINE void ADC1_Software_Mode_Sel(void)
ADC1 selects the Software Mode, measurements are performed on user request.
Definition: adc1.h:957
TADC1_ANON adc1_anon
Definition: adc1.h:231
INLINE uint8 ADC1_Ch1_ResultValid_Get(void)
Reads the valid flag for the channel 1 (CSA) result.
Definition: adc1.h:1877
#define ADC1_SQ5_8_SQ7_Msk
Definition: tle986x.h:6268
INLINE void ADC1_Ch2_Int_Dis(void)
disables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3595
#define ADC1_RES_OUT_EIM_VF8_Msk
Definition: tle986x.h:6250
INLINE void ADC1_VDH_Attenuator_Zlow_Set(void)
Disables the output attenuator for VDH.
Definition: adc1.h:3262
INLINE void ADC1_Ch0_Overwrite_Set(void)
Sets the ADC1 channel 0 result register to "overwrite".
Definition: adc1.h:2697
#define ADC1_RES_OUT2_VF2_Pos
Definition: tle986x.h:6195
INLINE uint16 ADC1_Ch4_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1512
INLINE void ADC1_DIVA_Set(uint32 a)
ADC1 analog clock divider. .
Definition: adc1.h:894
#define ADC1_RES_OUT1_WFR1_Msk
Definition: tle986x.h:6189
#define ADC1_SQ1_4_SQ2_Msk
Definition: tle986x.h:6261
INLINE void ADC1_Ch6_Int_En(void)
enables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3752
#define ADC1_DWSEL_ch5_Msk
Definition: tle986x.h:6086
#define ADC1_SQ5_8_SQ5_Msk
Definition: tle986x.h:6272
#define ADC1_ICLR_CH1_ICLR_Pos
Definition: tle986x.h:6128
INLINE void ADC1_Ch1_Int_Clr(void)
clears ADC1 Channel 1 Interrupt flag.
Definition: adc1.h:3306
#define ADC1_RES_OUT0_WFR0_Msk
Definition: tle986x.h:6180
#define ADC1_STC_0_3_ch1_Msk
Definition: tle986x.h:6290
#define ADC1_DWSEL_ch0_Msk
Definition: tle986x.h:6096
#define ADC1_ICLR_EIM_ICLR_Pos
Definition: tle986x.h:6114
#define ADC1_IE_CH1_IE_Pos
Definition: tle986x.h:6149
bool ADC1_GetChResult_mV(uint16 *pVar_mV, uint8 channel)
Get the value of the ADC1 Result Register of the selected ADC1 channel in Millivolt (mV) and returns ...
INLINE void ADC1_Ch0_DataWidth_10bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 10-bit.
Definition: adc1.h:2122
INLINE uint8 ADC1_EOC_Sts(void)
Reads the End-of-Conversion status.
Definition: adc1.h:984
INLINE void ADC1_Ch4_DataWidth_8bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 8-bit.
Definition: adc1.h:2304
#define ADC1_IE_CH2_IE_Pos
Definition: tle986x.h:6147
#define ADC1_SQ1_4_SQ4_Pos
Definition: tle986x.h:6256
#define ADC1_CHx_ESM_TRIG_SEL_Msk
Definition: tle986x.h:6068
INLINE void ADC1_Power_Off(void)
Disables the ADC1 module.
Definition: adc1.h:837
INLINE uint16 ADC1_VDH_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1813
#define ADC1_IE_CH6_IE_Msk
Definition: tle986x.h:6140
#define ADC1_RES_OUT2_VF2_Msk
Definition: tle986x.h:6196
INLINE void ADC1_ESM_Channel_Set(uint32 mask_ch)
Set channels in ESM sequence.
Definition: adc1.h:3119
SFR low level access library.
#define ADC1_RES_OUT4_VF4_Msk
Definition: tle986x.h:6214
#define ADC1_DWSEL_ch4_Msk
Definition: tle986x.h:6088
#define ADC1_RES_OUT3_VF3_Pos
Definition: tle986x.h:6204
#define ADC1_SQ5_8_SQ8_Pos
Definition: tle986x.h:6265
#define ADC1_GLOBSTR_BUSY_Pos
Definition: tle986x.h:6109
INLINE uint8 ADC1_Sample_Sts(void)
Reads the sample status of a ongoing measurement.
Definition: adc1.h:1047
#define ADC1_CTRL_STS_IN_MUX_SEL_Msk
Definition: tle986x.h:6073
#define ADC1_DWSEL_ch6_Msk
Definition: tle986x.h:6084
#define INLINE
Definition: types.h:134
INLINE void ADC1_Sequence0_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 0, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1201
#define ADC1_STC_0_3_ch3_Pos
Definition: tle986x.h:6285
INLINE uint16 ADC1_EIM_Result_Get(void)
Reads the converted value from the EIM result register.
Definition: adc1.h:1603
#define ADC1_CHx_EIM_TRIG_SEL_Msk
Definition: tle986x.h:6061
#define ADC1_GLOBCTR_ANON_Pos
Definition: tle986x.h:6098
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk
Definition: tle986x.h:6254
INLINE void ADC1_EIM_Channel_Set(uint32 ch)
Set EIM channel for measurement.
Definition: adc1.h:3088
INLINE void ADC1_SetEIMChannel(uint8 channel)
Set(Change) ADC1 EIM channel.
Definition: adc1.h:3952
#define ADC1_ICLR_ESM_ICLR_Msk
Definition: tle986x.h:6113
#define ADC1_SQ1_4_SQ3_Pos
Definition: tle986x.h:6258
#define ADC1_STC_0_3_ch0_Msk
Definition: tle986x.h:6292
INLINE uint16 ADC1_P20_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1633
#define ADC1_RES_OUT4_WFR4_Pos
Definition: tle986x.h:6215
#define ADC1_SQ5_8_SQ5_Pos
Definition: tle986x.h:6271
INLINE void ADC1_Ch1_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 1 number of sampling ticks.
Definition: adc1.h:2492
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:401
unsigned short uint16
16 bit unsigned value
Definition: types.h:140
INLINE uint8 ADC1_Ch2_ResultValid_Get(void)
Reads the valid flag for the channel 2 (P2.2) result.
Definition: adc1.h:1909
#define ADC1_IE_CH1_IE_Msk
Definition: tle986x.h:6150
#define ADC1_ICLR_ESM_ICLR_Pos
Definition: tle986x.h:6112
#define ADC1
Definition: tle986x.h:5990
#define ADC1_RES_OUT2_OUT_CH2_Msk
Definition: tle986x.h:6200
INLINE uint8 ADC1_Ch6_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2037
INLINE void ADC1_Ch5_DataWidth_8bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 8-bit.
Definition: adc1.h:2356
#define ADC1_SQ_FB_EIM_ACTIVE_Pos
Definition: tle986x.h:6280
INLINE void ADC1_Sequence5_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 5, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1316
INLINE void ADC1_VDH_Attenuator_Zhigh_Set(void)
Enables the output attenuator for VDH.
Definition: adc1.h:3226
bool VAREF_Enable(void)
Re-enables the internal VAREF LDO in case it was shutdown due to a previous failure.
INLINE void ADC1_SW_Ch_Sel(uint32 a)
Selects a channel for the software conversion.
Definition: adc1.h:874
INLINE uint32 u32_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 32-bit field of a 32-bit register.
Definition: sfr_access.h:431
INLINE uint8 ADC1_Busy_Sts(void)
Reads the overall status of the ADC1.
Definition: adc1.h:1079
#define ADC1_RES_OUT1_VF1_Pos
Definition: tle986x.h:6186
INLINE void ADC1_Ch3_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 3 number of sampling ticks.
Definition: adc1.h:2550
INLINE void ADC1_Ch6_DataWidth_10bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 10-bit.
Definition: adc1.h:2434
INLINE uint8 ADC1_Current_Active_Sequence_Sts(void)
Reads the currently active channel in Sequencer Mode.
Definition: adc1.h:1155
INLINE void ADC1_Ch3_DataWidth_10bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 10-bit.
Definition: adc1.h:2278
#define ADC1_DWSEL_ch5_Pos
Definition: tle986x.h:6085
INLINE void ADC1_EIM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Get ADC1 EIM Trigger Selection.
Definition: adc1.h:4012
#define ADC1_RES_OUT_EIM_VF8_Pos
Definition: tle986x.h:6249
INLINE bool ADC1_isEndOfConversion(void)
checks EndOfConversion ready (Software Mode)
Definition: adc1.h:4030
bool ADC1_GetEIMResult(uint16 *pVar)
Get the 10-bit/8-bit value of the ADC1 EIM Result Register and returns the validity info.
#define ADC1_RES_OUT4_OUT_CH4_Msk
Definition: tle986x.h:6218
INLINE void ADC1_Ch2_Overwrite_Set(void)
Sets the ADC1 channel 2 result register to "overwrite".
Definition: adc1.h:2817
#define ADC1_RES_OUT3_OUT_CH3_Pos
Definition: tle986x.h:6208
#define ADC1_GLOBSTR_SAMPLE_Pos
Definition: tle986x.h:6107
#define ADC1_CHx_EIM_REP_Pos
Definition: tle986x.h:6062
#define ADC1_GLOBSTR_SAMPLE_Msk
Definition: tle986x.h:6108
#define ADC1_IE_CH3_IE_Pos
Definition: tle986x.h:6145
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk
Definition: tle986x.h:8089
#define ADC1_RES_OUT1_OUT_CH1_Msk
Definition: tle986x.h:6191
#define ADC1_RES_OUT2_WFR2_Pos
Definition: tle986x.h:6197
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
INLINE void ADC1_VDH_Attenuator_Off(void)
Disables the input attenuator for VDH.
Definition: adc1.h:3190
#define ADC1_RES_OUT0_VF0_Pos
Definition: tle986x.h:6177
INLINE bool ADC1_GetSwModeResult(uint16 *pVar)
Get ADC1 latest software mode result.
Definition: adc1.h:3986
INLINE uint16 ADC1_Ch0_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1392
#define ADC1_CHx_ESM_TRIG_SEL_Pos
Definition: tle986x.h:6067
INLINE bool ADC1_isESMactive(void)
checks Exceptional Sequencer Mode active
Definition: adc1.h:4054
INLINE uint8 ADC1_EIM_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2070
#define ADC1_IE_CH5_IE_Msk
Definition: tle986x.h:6142
#define ADC1_RES_OUT3_OUT_CH3_Msk
Definition: tle986x.h:6209
INLINE void ADC1_Ch6_Overwrite_Set(void)
Sets the ADC1 channel 6 result register to "overwrite".
Definition: adc1.h:3057
#define ADC1_RES_OUT4_VF4_Pos
Definition: tle986x.h:6213
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:341
INLINE void ADC1_Ch0_Int_Clr(void)
clears ADC1 Channel 0 Interrupt flag.
Definition: adc1.h:3284
#define ADC1_VDH_Attenuator_Range_0_20V
ADC1 VDH Attenuator Selection, 0V..20V.
Definition: adc1.h:118
#define ADC1_DWSEL_ch1_Pos
Definition: tle986x.h:6093
INLINE uint8 u8_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 8-bit field of a 32-bit register.
Definition: sfr_access.h:416
INLINE void ADC1_Ch4_Int_Dis(void)
disables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3685
INLINE void ADC1_Ch4_Overwrite_Set(void)
Sets the ADC1 channel 4 result register to "overwrite".
Definition: adc1.h:2937
INLINE void ADC1_Sequencer_Mode_Sel(void)
ADC1 selects the Sequencer Mode.
Definition: adc1.h:934
#define ADC1_DWSEL_ch2_Msk
Definition: tle986x.h:6092
#define ADC1_IE_EIM_IE_Pos
Definition: tle986x.h:6135
#define ADC1_STC_4_7_ch5_Pos
Definition: tle986x.h:6298
#define ADC1_RES_OUT1_OUT_CH1_Pos
Definition: tle986x.h:6190
INLINE void ADC1_Ch2_Int_En(void)
enables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3572
#define ADC1_ICLR_CH6_ICLR_Msk
Definition: tle986x.h:6119
#define ADC1_ICLR_EIM_ICLR_Msk
Definition: tle986x.h:6115
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos
Definition: tle986x.h:8086
#define ADC1_GLOBSTR_CHNR_Msk
Definition: tle986x.h:6106
INLINE uint8 ADC1_Ch3_ResultValid_Get(void)
Reads the valid flag for the channel 3 (P2.3) result.
Definition: adc1.h:1941
#define ADC1_RES_OUT0_VF0_Msk
Definition: tle986x.h:6178
#define ADC1_ICLR_CH5_ICLR_Pos
Definition: tle986x.h:6120
INLINE void ADC1_Ch0_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 0 number of sampling ticks.
Definition: adc1.h:2463
#define ADC1_STC_0_3_ch3_Msk
Definition: tle986x.h:6286
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
#define ADC1_ICLR_CH5_ICLR_Msk
Definition: tle986x.h:6121
uint32 dword
Definition: adc1.h:230
#define ADC1_GLOBSTR_CHNR_Pos
Definition: tle986x.h:6105
INLINE uint16 ADC1_P23_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1723
INLINE void ADC1_Ch0_Int_Dis(void)
disables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3505
#define ADC1_ICLR_CH0_ICLR_Msk
Definition: tle986x.h:6131
#define ADC1_RES_OUT5_OUT_CH5_Msk
Definition: tle986x.h:6227
#define ADC1_RES_OUT3_WFR3_Msk
Definition: tle986x.h:6207
INLINE void ADC1_Ch2_DataWidth_8bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 8-bit.
Definition: adc1.h:2200
INLINE void ADC1_Ch0_Int_En(void)
enables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3482
#define ADC1_STC_4_7_ch6_Pos
Definition: tle986x.h:6296
INLINE void ADC1_ESM_Int_Clr(void)
clears Exceptional Sequence Measurement (ESM) flag.
Definition: adc1.h:3460
INLINE void ADC1_Ch6_Int_Clr(void)
clears ADC1 Channel 6 Interrupt flag.
Definition: adc1.h:3415
INLINE void ADC1_Ch2_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 2 number of sampling ticks.
Definition: adc1.h:2521
#define ADC1_STC_4_7_ch4_Msk
Definition: tle986x.h:6301
bool ADC1_GetChResult(uint16 *pVar, uint8 channel)
Get the 10-bit/8-bit value of the ADC1 Result Register of the selected ADC1 channel and returns the v...
#define ADC1_RES_OUT6_VF6_Msk
Definition: tle986x.h:6232
bool ADC1_GetEIMResult_mV(uint16 *pVar_mV)
Get the value of the ADC1 EIM Result Register in Millivolt (mV) and returns the validity info.
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos
Definition: tle986x.h:8088
INLINE void ADC1_EIM_Repeat_Counter_Set(TADC1_EIM_REP_CNT repcnt)
Set ADC1 EIM Repeat Counter.
Definition: adc1.h:4018
#define ADC1_DWSEL_ch6_Pos
Definition: tle986x.h:6083
#define ADC1_SQ_FB_SQ_RUN_Msk
Definition: tle986x.h:6283
#define ADC1_RES_OUT6_VF6_Pos
Definition: tle986x.h:6231
#define ADC1_IE_CH0_IE_Pos
Definition: tle986x.h:6151
INLINE uint16 ADC1_Ch5_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1542
INLINE void ADC1_Sequence6_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 6, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1339
#define ADC1_DWSEL_ch4_Pos
Definition: tle986x.h:6087
INLINE void ADC1_Ch3_Int_Dis(void)
disables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3640
INLINE void ADC1_EIM_Int_Dis(void)
disables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3822
#define ADC1_RES_OUT0_OUT_CH0_Pos
Definition: tle986x.h:6181
#define ADC1_ICLR_CH1_ICLR_Msk
Definition: tle986x.h:6129
#define ADC1_SQ_FB_CHx_Msk
Definition: tle986x.h:6275
INLINE TADC1_ANON ADC1_ANON_Sts(void)
Reads the Analog Part Switched On Mode status.
Definition: adc1.h:4066
#define ADC1_ICLR_CH0_ICLR_Pos
Definition: tle986x.h:6130
#define ADC1_SQ_FB_SQx_Msk
Definition: tle986x.h:6277
INLINE uint8 ADC1_Ch4_ResultValid_Get(void)
Reads the valid flag for the channel 4 (P2.4) result.
Definition: adc1.h:1973
#define MF
Definition: tle986x.h:6000
#define ADC1_RES_OUT3_VF3_Msk
Definition: tle986x.h:6205
#define ADC1_ICLR_CH2_ICLR_Pos
Definition: tle986x.h:6126
INLINE uint8 ADC1_ESM_Active_Sts(void)
Reads the active status of the Exceptional Sequencer Measurement (ESM).
Definition: adc1.h:1131
INLINE void ADC1_ANON_Set(uint32 a)
ADC1 set the Analog Module Mode.
Definition: adc1.h:913
INLINE void ADC1_Ch5_Overwrite_Set(void)
Sets the ADC1 channel 5 result register to "overwrite".
Definition: adc1.h:2997
#define ADC1_GLOBCTR_DIVA_Pos
Definition: tle986x.h:6100
INLINE void ADC1_SetSocSwMode(uint8 Ch)
Starts ADC1 software mode conversion.
Definition: adc1.h:3968
INLINE void ADC1_Ch5_DataWidth_10bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 10-bit.
Definition: adc1.h:2382
#define ADC1_SQ5_8_SQ7_Pos
Definition: tle986x.h:6267
INLINE void ADC1_Power_On(void)
Enables the ADC1 module.
Definition: adc1.h:820
CMSIS register HeaderFile.
#define ADC1_IE_CH4_IE_Msk
Definition: tle986x.h:6144
INLINE void ADC1_VDH_Attenuator_Range_0_30V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 30V.
Definition: adc1.h:3892
INLINE uint8 ADC1_Ch0_ResultValid_Get(void)
Reads the valid flag for the channel 0 (P2.0) result.
Definition: adc1.h:1845
#define ADC1_RES_OUT5_VF5_Pos
Definition: tle986x.h:6222
TADC1_ANON
This enum lists the options for the Analog Module.
Definition: adc1.h:220
#define ADC1_STC_0_3_ch0_Pos
Definition: tle986x.h:6291
INLINE void ADC1_Ch3_Int_En(void)
enables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3617
#define ADC1_SQ_FB_ESM_ACTIVE_Pos
Definition: tle986x.h:6278
INLINE void ADC1_Ch5_Int_Dis(void)
disables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3730
#define ADC1_ICLR_CH2_ICLR_Msk
Definition: tle986x.h:6127
INLINE uint16 ADC1_P25_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1783
void ADC1_Init(void)
Initializes the ADC1 based on the IFXConfigWizard configuration.
INLINE uint16 ADC1_Ch1_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1422
#define ADC1_VDH_Attenuator_Range_0_30V
ADC1 VDH Attenuator Selection, 0V..30V.
Definition: adc1.h:116
INLINE bool ADC1_isEIMactive(void)
checks Exceptional Interrupt Mode active
Definition: adc1.h:4042
INLINE uint16 ADC1_P24_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1753
#define ADC1_GLOBSTR_ANON_ST_Msk
Definition: tle986x.h:6104
#define ADC1_DWSEL_ch0_Pos
Definition: tle986x.h:6095
#define ADC1_RES_OUT4_WFR4_Msk
Definition: tle986x.h:6216
INLINE void ADC1_Ch6_WaitForRead_Set(void)
Sets the ADC1 channel 6 result register to "wait for read".
Definition: adc1.h:3027
#define ADC1_SQ1_4_SQ1_Pos
Definition: tle986x.h:6262
INLINE void ADC1_Ch6_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 6 number of sampling ticks.
Definition: adc1.h:2637
#define ADC1_SQ1_4_SQ4_Msk
Definition: tle986x.h:6257
INLINE uint16 ADC1_Ch3_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1482
#define ADC1_RES_OUT4_OUT_CH4_Pos
Definition: tle986x.h:6217
#define ADC1_RES_OUT1_VF1_Msk
Definition: tle986x.h:6187
#define ADC1_SQ_FB_ESM_ACTIVE_Msk
Definition: tle986x.h:6279
TADC1_EIM_REP_CNT
This enum lists the options for the EIM repeat count setting.
Definition: adc1.h:256
INLINE uint8 ADC1_VDH_Attenuator_Range_Get(void)
Reads the VDH Monitoring Input Attenuator Input Range Configuration.
Definition: adc1.h:3945
#define ADC1_CHx_EIM_TRIG_SEL_Pos
Definition: tle986x.h:6060
INLINE void ADC1_SetMode(uint8 mode)
Start ADC1 conversion mode selection.
Definition: adc1.h:3962
INLINE void ADC1_Sequence1_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 1, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1224
#define ADC1_RES_OUT3_WFR3_Pos
Definition: tle986x.h:6206
#define ADC1_SQ_FB_SQx_Pos
Definition: tle986x.h:6276
#define ADC1_STC_0_3_ch2_Pos
Definition: tle986x.h:6287
#define ADC1_IE_CH6_IE_Pos
Definition: tle986x.h:6139
#define ADC1_SQ5_8_SQ6_Pos
Definition: tle986x.h:6269
INLINE void ADC1_Ch1_Overwrite_Set(void)
Sets the ADC1 channel 1 result register to "overwrite".
Definition: adc1.h:2757
#define ADC1_GLOBSTR_BUSY_Msk
Definition: tle986x.h:6110
#define ADC1_STC_4_7_ch4_Pos
Definition: tle986x.h:6300
INLINE void ADC1_VDH_Attenuator_On(void)
Enables the input attenuator for VDH.
Definition: adc1.h:3155
INLINE void ADC1_SetSwMode_Channel(uint8 channel)
Selects a channel for the software conversion.
Definition: adc1.h:3957
INLINE void ADC1_Ch6_Int_Dis(void)
disables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3775
INLINE uint8 ADC1_EIM_Active_Sts(void)
Reads the active status of the Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:1105
#define ADC1_STC_0_3_ch1_Pos
Definition: tle986x.h:6289
INLINE void ADC1_Ch5_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 5 number of sampling ticks.
Definition: adc1.h:2608
#define ADC1_CHx_EIM_REP_Msk
Definition: tle986x.h:6063
#define ADC1_IE_CH0_IE_Msk
Definition: tle986x.h:6152
#define ADC1_ICLR_CH4_ICLR_Pos
Definition: tle986x.h:6122
#define ADC1_RES_OUT6_OUT_CH6_Pos
Definition: tle986x.h:6235
#define ADC1_CTRL_STS_EOC_Msk
Definition: tle986x.h:6075
INLINE void ADC1_Sequence7_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 7, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1362
INLINE bool ADC1_GetEocSwMode(void)
Get ADC1 end of conversion status.
Definition: adc1.h:3974
#define ADC1_ICLR_CH3_ICLR_Pos
Definition: tle986x.h:6124
#define ADC1_RES_OUT5_WFR5_Msk
Definition: tle986x.h:6225
INLINE void ADC1_SOC_Set(void)
ADC1 Start of Conversion, for Software mode only.
Definition: adc1.h:854
#define ADC1_IE_CH2_IE_Msk
Definition: tle986x.h:6148
#define ADC1_CHx_EIM_CHx_Pos
Definition: tle986x.h:6064
INLINE void ADC1_Ch0_WaitForRead_Set(void)
Sets the ADC1 channel 0 result register to "wait for read".
Definition: adc1.h:2667
#define ADC1_CHx_ESM_ESM_0_Pos
Definition: tle986x.h:6069
INLINE void ADC1_ESM_Int_En(void)
enables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3844
INLINE void ADC1_Ch3_WaitForRead_Set(void)
Sets the ADC1 channel 3 result register to "wait for read".
Definition: adc1.h:2847
#define ADC1_RES_OUT5_OUT_CH5_Pos
Definition: tle986x.h:6226
INLINE void ADC1_Ch3_DataWidth_8bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 8-bit.
Definition: adc1.h:2252
INLINE void ADC1_Ch1_Int_Dis(void)
disables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3550
#define ADC1_STC_4_7_ch5_Msk
Definition: tle986x.h:6299
#define ADC1_CTRL_STS_PD_N_Pos
Definition: tle986x.h:6078
INLINE uint8 ADC1_Ch5_ResultValid_Get(void)
Reads the valid flag for the channel 5 (P2.5) result.
Definition: adc1.h:2005
INLINE void ADC1_Ch0_DataWidth_8bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 8-bit.
Definition: adc1.h:2096
#define ADC1_SQ1_4_SQ1_Msk
Definition: tle986x.h:6263
INLINE void ADC1_Ch2_WaitForRead_Set(void)
Sets the ADC1 channel 2 result register to "wait for read".
Definition: adc1.h:2787
#define ADC1_IE_ESM_IE_Msk
Definition: tle986x.h:6134
#define ADC1_IE_CH3_IE_Msk
Definition: tle986x.h:6146
INLINE void ADC1_VDH_Attenuator_Range_0_20V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 22V.
Definition: adc1.h:3916
#define ADC1_RES_OUT5_VF5_Msk
Definition: tle986x.h:6223
INLINE void ADC1_Sequence4_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 4, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1293
#define ADC1_RES_OUT6_WFR6_Pos
Definition: tle986x.h:6233
#define ADC1_CTRL_STS_EOC_Pos
Definition: tle986x.h:6074
#define ADC1_GLOBCTR_DIVA_Msk
Definition: tle986x.h:6101
#define ADC1_IE_EIM_IE_Msk
Definition: tle986x.h:6136
#define ADC1_GLOBSTR_ANON_ST_Pos
Definition: tle986x.h:6103
#define ADC1_DWSEL_ch2_Pos
Definition: tle986x.h:6091
INLINE uint8 ADC1_Current_Ch_Sts(void)
Reads the channel for currently ongoing conversion, if no conversion is ongoing, then it returns the ...
Definition: adc1.h:1014
INLINE void ADC1_Ch4_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 4 number of sampling ticks.
Definition: adc1.h:2579
#define ADC1_IE_CH5_IE_Pos
Definition: tle986x.h:6141
INLINE void ADC1_Ch1_WaitForRead_Set(void)
Sets ADC1 channel 1 the result register to "wait for read".
Definition: adc1.h:2727
#define ADC1_CTRL_STS_SOC_Msk
Definition: tle986x.h:6077
#define ADC1_RES_OUT2_WFR2_Msk
Definition: tle986x.h:6198
INLINE void ADC1_Ch4_Int_En(void)
enables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3662
INLINE void ADC1_Ch5_WaitForRead_Set(void)
Sets the ADC1 channel 5 result register to "wait for read".
Definition: adc1.h:2967
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos
Definition: tle986x.h:6253
#define ADC1_SQ1_4_SQ2_Pos
Definition: tle986x.h:6260
INLINE void ADC1_Ch4_Int_Clr(void)
clears ADC1 Channel 4 Interrupt flag.
Definition: adc1.h:3372
#define ADC1_SQ_FB_SQ_RUN_Pos
Definition: tle986x.h:6282
#define ADC1_CTRL_STS_IN_MUX_SEL_Pos
Definition: tle986x.h:6072