TLE986x Device Family SDK
Data Fields
SSC1_Type Struct Reference

Detailed Description

SSC1 Module (SSC1)

#include <tle986x.h>

Data Fields

union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   MIS_0: 1
 
      __IOM uint16_t   SIS: 1
 
      __IOM uint16_t   CIS: 1
 
      __IOM uint16_t   MIS_1: 1
 
   }   bit
 
PISEL
 
__IM uint16_t RESERVED
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   BC: 4
 
      __IM   uint16_t: 4
 
      __IM uint16_t   TE: 1
 
      __IM uint16_t   RE: 1
 
      __IM uint16_t   PE: 1
 
      __IM uint16_t   BE: 1
 
      __IM uint16_t   BSY: 1
 
      __IOM uint16_t   MS: 1
 
      __IOM uint16_t   EN: 1
 
   }   bit
 
CON
 
__IM uint16_t RESERVED1
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   TB_VALUE: 16
 
   }   bit
 
TB
 
__IM uint16_t RESERVED2
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   RB_VALUE: 16
 
   }   bit
 
RB
 
__IM uint16_t RESERVED3
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   BR_VALUE: 16
 
   }   bit
 
BR
 
__IM uint16_t RESERVED4
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM   uint16_t: 8
 
      __OM uint16_t   TECLR: 1
 
      __OM uint16_t   RECLR: 1
 
      __OM uint16_t   PECLR: 1
 
      __OM uint16_t   BECLR: 1
 
   }   bit
 
ISRCLR
 

Field Documentation

◆ BC

[3..0] Bit Count Field

◆ BE

[11..11] Baud Rate Error Flag

◆ BECLR

__OM uint16_t BECLR

[11..11] Baud Rate Error Flag Clear

◆ bit [1/6]

struct { ... } bit

◆ bit [2/6]

struct { ... } bit

◆ bit [3/6]

struct { ... } bit

◆ bit [4/6]

struct { ... } bit

◆ bit [5/6]

struct { ... } bit

◆ bit [6/6]

struct { ... } bit

◆ BR

union { ... } BR

◆ BR_VALUE

__IOM uint16_t BR_VALUE

[15..0] Baud Rate Timer/Reload Register Value

◆ BSY

[12..12] Busy Flag

◆ CIS

[2..2] Slave Mode Clock Input Select: 0b0=Clock input (Port A: P0.3) is selected (SSC1)., 0b1=Clock input (Port B: P0.3) is selected (SSC1)., 0b0=Clock input (Port A: P1.0) is selected (SSC2)., 0b1=Clock input (Port B: P1.0) is selected (SSC2).,

◆ CON

union { ... } CON

◆ EN

[15..15] Enable Bit = 1

◆ ISRCLR

union { ... } ISRCLR

◆ MIS_0

__IOM uint16_t MIS_0

[0..0] Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=Receiver input (Port A: P1.2) is selected (SSC2)., 0b1=Receiver input (Port B: P2.5) is selected (SSC2).,

◆ MIS_1

__IOM uint16_t MIS_1

[3..3] Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=n/a (SSC2)., 0b1=n/a (SSC2).,

◆ MS

[14..14] Master Select Bit

◆ PE

[10..10] Phase Error Flag

◆ PECLR

__OM uint16_t PECLR

[10..10] Phase Error Flag Clear

◆ PISEL

union { ... } PISEL

◆ RB

union { ... } RB

◆ RB_VALUE

__IM uint16_t RB_VALUE

[15..0] Receive Data Register Value

◆ RE

[9..9] Receive Error Flag

◆ RECLR

__OM uint16_t RECLR

[9..9] Receive Error Flag Clear

◆ reg

(@ 0x00000000) Port Input Select Register, RESET_TYPE_3

(@ 0x00000004) Control Register

(@ 0x00000008) Transmitter Buffer Register

(@ 0x0000000C) Receiver Buffer Register

(@ 0x00000010) Baud Rate Timer Reload Register

(@ 0x00000014) Interrupt Status Register Clear

◆ RESERVED

__IM uint16_t RESERVED

◆ RESERVED1

__IM uint16_t RESERVED1

◆ RESERVED2

__IM uint16_t RESERVED2

◆ RESERVED3

__IM uint16_t RESERVED3

◆ RESERVED4

__IM uint16_t RESERVED4

◆ SIS

[1..1] Slave Mode Receiver Input Select: 0b0=Receiver input (Port A: P0.2) is selected (SSC1)., 0b1=Receiver input (Port B: P0.2) is selected (SSC1)., 0b0=Receiver input (Port A: P1.1) is selected (SSC2)., 0b1=Receiver input (Port B: P1.1) is selected (SSC2).,

◆ TB

union { ... } TB

◆ TB_VALUE

__IOM uint16_t TB_VALUE

[15..0] Transmit Data Register Value

◆ TE

[8..8] Transmit Error Flag

◆ TECLR

__OM uint16_t TECLR

[8..8] Transmit Error Flag Clear

◆ uint16_t

__IM uint16_t

The documentation for this struct was generated from the following file: