TLE986x Device Family SDK
ccu6.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2015, Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** TA Thomas Albersinger **
44 ** BG Blandine Guillot **
45 ** JO Julia Ott **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.1.0: ? , DM: Initial version **
52 ** V0.2.0: 2014-04-25, TA: CCU6_Init(): use #defines from Config Wizard **
53 ** V0.2.1: 2015-02-10, DM: Individual header file added **
54 ** V0.2.2: 2015-08-27, DM: New API functions added to ccu6.h **
55 ** V0.2.3: 2017-04-11, DM: Macros for interrupt set/reset/clear added **
56 ** V0.2.4: 2017-11-08, DM: CCU6_T12_Modulation_En() fixed **
57 ** CCU6_T13_Modulation_En() fixed **
58 ** V0.2.5: 2017-11-14, DM: MISRA 2012 compliance, the following PC-Lint **
59 ** rules are globally deactivated: **
60 ** - Info 793: ANSI/ISO limit of 6 'significant **
61 ** characters in an external identifier **
62 ** - Info 835: A zero has been given as right **
63 ** argument to operator **
64 ** - Info 845: The left argument to operator '&' **
65 ** is certain to be 0 **
66 ** CCU6_Init(): one CCU6_T12_Str_En() replaced by **
67 ** CCU6_T13_Str_En() **
68 ** Replaced macros by INLINE functions **
69 ** Replaced register accesses within functions by **
70 ** function calls **
71 ** Replaced __STATIC_INLINE by INLINE **
72 ** V0.2.6: 2018-03-14, DM: CCU6_Ch0_Deadtime_Sts(), CCU6_Ch1_Deadtime_Sts(),**
73 ** CCU6_Ch2_Deadtime_Sts() the register access **
74 ** macro changed to Field_Rd1() **
75 ** CCU6_MASK_CC6x and CCU6_MASK_COUT6x changed due **
76 ** to MISRA 2012 **
77 ** V0.2.7: 2018-12-04, JO: Doxygen update, moved revision history from **
78 ** ccu6.c to ccu6.h **
79 ** CCU6_Passive_State_After_Compare_Sel() function **
80 ** added **
81 ** CCU6_Ch*t_Passive_State_After_Compare_Sel() and **
82 ** CCU6_Ch*t_Passive_State_Before_Compare_Sel() **
83 ** removed **
84 ** V0.2.8: 2019-01-29, DM: CCU6_ReadHallReg() fixed **
85 ** V0.2.9: 2019-02-27, JO: CCU6_SetT13Compare() changed (added range check, **
86 ** +1 instead of +10) **
87 ** V0.3.0: 2020-02-28, BG: Updated revision history format **
88 ** V0.3.1: 2020-10-12, JO: EP-506: remove ARMCC v6 Compiler warnings **
89 ** - Added typecasts to remove 'implicit typecast' **
90 ** warning **
91 *******************************************************************************/
92 
93 #ifndef _CCU6_H
94 #define _CCU6_H
95 
96 /*******************************************************************************
97 ** Includes **
98 *******************************************************************************/
99 #include "tle986x.h"
100 #include "types.h"
101 #include "ccu6_defines.h"
102 #include "sfr_access.h"
103 #include "tle_variants.h"
104 
105 /*******************************************************************************
106 ** Global Macro Definitions **
107 *******************************************************************************/
109 #define CCU6_MASK_TCTR4_STOP_T12 (CCU6_TCTR4_T12RR_Msk)
110 
111 #define CCU6_MASK_TCTR4_START_T12 (CCU6_TCTR4_T12RS_Msk)
112 
113 #define CCU6_MASK_TCTR4_RESET_T12 (CCU6_TCTR4_T12RES_Msk)
114 
115 #define CCU6_MASK_TCTR4_SHADOW_T12 (CCU6_TCTR4_T12STR_Msk)
116 
117 #define CCU6_MASK_TCTR4_STOP_T13 (CCU6_TCTR4_T13RR_Msk)
118 
119 #define CCU6_MASK_TCTR4_START_T13 (CCU6_TCTR4_T13RS_Msk)
120 
121 #define CCU6_MASK_TCTR4_RESET_T13 (CCU6_TCTR4_T13RES_Msk)
122 
123 #define CCU6_MASK_TCTR4_SHADOW_T13 (CCU6_TCTR4_T13STR_Msk)
124 
126 #define CCU6_MASK_MCMOUTS_SHADOW_HALL (CCU6_MCMOUTS_STRHP_Msk)
127 
128 #define CCU6_MASK_MCMOUTS_SHADOW_OUT (CCU6_MCMOUTS_STRMCM_Msk)
129 
131 #define CCU6_MASK_CC60 ((uint16)1u << 0u)
132 
133 #define CCU6_MASK_COUT60 ((uint16)1u << 1u)
134 
135 #define CCU6_MASK_CC61 ((uint16)1u << 2u)
136 
137 #define CCU6_MASK_COUT61 ((uint16)1u << 3u)
138 
139 #define CCU6_MASK_CC62 ((uint16)1u << 4u)
140 
141 #define CCU6_MASK_COUT62 ((uint16)1u << 5u)
142 
144 #define CCU6_MASK_Ch0t CCU6_MASK_CC60
145 
146 #define CCU6_MASK_Ch0c CCU6_MASK_COUT60
147 
148 #define CCU6_MASK_Ch1t CCU6_MASK_CC61
149 
150 #define CCU6_MASK_Ch1c CCU6_MASK_COUT61
151 
152 #define CCU6_MASK_Ch2t CCU6_MASK_CC62
153 
154 #define CCU6_MASK_Ch2c CCU6_MASK_COUT62
155 
156 /******************************************************************************
157 ** Global Type Definitions **
158 ******************************************************************************/
162 typedef enum
163 {
164  CCU6_CC60_0_P04 = 0u,
165  CCU6_CC60_1_P23 = 1u
167 
171 typedef enum
172 {
173  CCU6_CC61_0_P10 = 0u
175 
179 typedef enum
180 {
181  CCU6_CC62_0_P13 = 0u,
182  CCU6_CC62_2_P22 = 2u
184 
188 typedef enum
189 {
190  CCU6_CTRAP_0_P24 = 0u,
191  CCU6_CTRAP_1_P23 = 1u
193 
197 typedef enum
198 {
199  CCU6_CCPOS0_1_P03 = 1u,
200  CCU6_CCPOS0_2_P13 = 2u,
201  CCU6_CCPOS0_3_P20 = 3u
202 #if (UC_SERIES == TLE987)
203  ,
204  CCU6_CCPOS0_BEMF = 3u
205 #endif /* (UC_SERIES == TLE987) */
207 
211 typedef enum
212 {
213  CCU6_CCPOS1_0_P23 = 0u,
214  CCU6_CCPOS1_1_P04 = 1u,
215  CCU6_CCPOS1_2_P14 = 2u
216 #if (UC_SERIES == TLE987)
217  ,
218  CCU6_CCPOS1_BEMF = 3u
219 #endif /* (UC_SERIES == TLE987) */
221 
225 typedef enum
226 {
227  CCU6_CCPOS2_1_P02 = 1u,
228  CCU6_CCPOS2_2_P12 = 2u,
229  CCU6_CCPOS2_3_P22 = 3u
230 #if (UC_SERIES == TLE987)
231  ,
232  CCU6_CCPOS2_BEMF = 3u
233 #endif /* (UC_SERIES == TLE987) */
235 
239 typedef enum
240 {
241  CCU6_T12HR_0_P00 = 0u,
242  CCU6_T12HR_2_P20 = 2u
244 
248 typedef enum
249 {
250  CCU6_T13HR_0_P01 = 0u,
251  CCU6_T13HR_2_P22 = 2u
253 
257 typedef enum
258 {
259  CCU6_T12_Prescaler = 0u,
260  CCU6_TCTR4_T12CNT = 1u,
264 
268 typedef enum
269 {
270  CCU6_T13_Prescaler = 0u,
271  CCU6_TCTR4_T13CNT = 1u,
275 
279 typedef enum
280 {
281  CCU6_T12HR_D_A = 0u,
282  CCU6_T12HR_H_E = 1u
284 
288 typedef enum
289 {
290  CCU6_T13HR_D_A = 0u,
291  CCU6_T13HR_H_E = 1u
293 
297 typedef enum
298 {
300  CCU6_T13_CM = 1u,
301  CCU6_T13_PM = 2u,
303  CCU6_T12_PM = 4u,
304  CCU6_T12_OM = 5u,
305  CCU6_T12_CM_Ch1_up = 6u,
308 
312 typedef enum
313 {
317  CCU6_Clk_Div_8 = 3,
318  CCU6_Clk_Div_16 = 4,
319  CCU6_Clk_Div_32 = 5,
320  CCU6_Clk_Div_64 = 6,
321  CCU6_Clk_Div_128 = 7
323 
327 typedef enum
328 {
334  CCU6_T13TEC_T12_PM = 5,
335  CCU6_T13TEC_T12_ZM = 6,
336  CCU6_T13TEC_CCPOSx = 7
338 
342 typedef enum
343 {
345  CCU6_T13ED_T12_Up = 1,
346  CCU6_T13ED_T12_Down = 2,
349 
353 typedef enum
354 {
355  CCU6_T12RSEL_Dis = 0,
360 
364 typedef enum
365 {
366  CCU6_T13RSEL_Dis = 0,
371 
375 typedef enum
376 {
377  CCU6_PSL63_Low = 0,
378  CCU6_PSL63_High = 1
380 
384 typedef enum
385 {
388  CCU6_SWSEL_T13_PM = 2,
389  CCU6_SWSEL_T12_OM = 3,
391  CCU6_SWSEL_T12_PM = 5
393 
397 typedef enum
398 {
399  CCU6_Node0 = 0,
400  CCU6_Node1 = 1,
401  CCU6_Node2 = 2,
402  CCU6_Node3 = 3
404 
405 
406 
410 typedef enum
411 {
416 } TCCU6_PWMMode;
417 /*******************************************************************************
418 ** Global Inline Function Definitions **
419 *******************************************************************************/
432 INLINE void CCU6_T12_Stop(void)
433 {
435 }
436 
449 INLINE void CCU6_T12_Start(void)
450 {
452 }
453 
466 INLINE void CCU6_T12_Rst(void)
467 {
469 }
470 
483 INLINE void CCU6_Deadtime_Rst(void)
484 {
486 }
487 
502 INLINE void CCU6_T12_Cnt(void)
503 {
505 }
506 
519 INLINE void CCU6_T12_Str_En(void)
520 {
522 }
523 
536 INLINE void CCU6_T12_Str_Dis(void)
537 {
539 }
540 
553 INLINE void CCU6_T13_Stop(void)
554 {
556 }
557 
570 INLINE void CCU6_T13_Start(void)
571 {
573 }
574 
587 INLINE void CCU6_T13_Rst(void)
588 {
590 }
591 
606 INLINE void CCU6_T13_Cnt(void)
607 {
609 }
610 
623 INLINE void CCU6_T13_Str_En(void)
624 {
626 }
627 
640 INLINE void CCU6_T13_Str_Dis(void)
641 {
643 }
644 
659 INLINE void CCU6_Ch0_Input_Sel(uint16 iscc60)
660 {
662 }
663 
678 INLINE void CCU6_Ch1_Input_Sel(uint16 iscc61)
679 {
681 }
682 
697 INLINE void CCU6_Ch2_Input_Sel(uint16 iscc62)
698 {
700 }
701 
717 {
719 }
720 
736 {
738 }
739 
755 {
757 }
758 
774 {
776 }
777 
793 INLINE void CCU6_T12HR_Input_Sel(uint16 ist12hr)
794 {
796 }
797 
813 INLINE void CCU6_T13HR_Input_Sel(uint16 ist13hr)
814 {
816 }
817 
835 {
837 }
838 
856 {
858 }
859 
876 {
878 }
879 
896 {
898 }
899 
913 {
915 }
916 
930 {
932 }
933 
949 {
951 }
952 
968 {
970 }
971 
987 {
989 }
990 
1006 {
1008 }
1009 
1027 {
1029 }
1030 
1047 {
1049 }
1050 
1069 {
1071 }
1072 
1089 {
1091 }
1092 
1110 {
1112 }
1113 
1128 INLINE void CCU6_Ch0_Value_Set(uint16 cc60sr)
1129 {
1131 }
1132 
1150 {
1152 }
1153 
1168 INLINE void CCU6_Ch1_Value_Set(uint16 cc61sr)
1169 {
1171 }
1172 
1190 {
1192 }
1193 
1208 INLINE void CCU6_Ch2_Value_Set(uint16 cc62sr)
1209 {
1211 }
1212 
1230 {
1232 }
1233 
1249 {
1251 }
1252 
1265 INLINE void CCU6_Ch0_Deadtime_En(void)
1266 {
1268 }
1269 
1282 INLINE void CCU6_Ch1_Deadtime_En(void)
1283 {
1285 }
1286 
1299 INLINE void CCU6_Ch2_Deadtime_En(void)
1300 {
1302 }
1303 
1316 INLINE void CCU6_Ch0_Deadtime_Dis(void)
1317 {
1319 }
1320 
1333 INLINE void CCU6_Ch1_Deadtime_Dis(void)
1334 {
1336 }
1337 
1350 INLINE void CCU6_Ch2_Deadtime_Dis(void)
1351 {
1353 }
1354 
1373 {
1375 }
1376 
1395 {
1397 }
1398 
1417 {
1419 }
1420 
1438 {
1440 }
1441 
1457 {
1459 }
1460 
1478 {
1480 }
1481 
1497 {
1499 }
1500 
1518 {
1520 }
1521 
1536 INLINE void CCU6_Ch3_Value_Set(uint16 cc63sr)
1537 {
1539 }
1540 
1560 {
1562 }
1563 
1583 {
1585 }
1586 
1606 {
1608 }
1609 
1629 {
1631 }
1632 
1651 {
1653 }
1654 
1673 {
1675 }
1676 
1695 {
1697 }
1698 
1706 {
1707  Field_Mod16(&CCU6->CMPSTAT.reg, (uint16)CCU6_CMPSTAT_CC60PS_Pos, (uint16)0x3F00, (uint16_t)mode);
1708  CCU6_T12_Str_En();
1709 }
1710 
1711 
1728 {
1730  CCU6_T13_Str_En();
1731 }
1732 
1749 {
1751  CCU6_T13_Str_En();
1752 }
1753 
1766 INLINE void CCU6_T13_Inv_Mod_En(void)
1767 {
1769  CCU6_T13_Str_En();
1770 }
1771 
1784 INLINE void CCU6_T13_Inv_Mod_Dis(void)
1785 {
1787  CCU6_T13_Str_En();
1788 }
1789 
1802 INLINE void CCU6_Ch0_CompState_Set(void)
1803 {
1805 }
1806 
1819 INLINE void CCU6_Ch1_CompState_Set(void)
1820 {
1822 }
1823 
1836 INLINE void CCU6_Ch2_CompState_Set(void)
1837 {
1839 }
1840 
1853 INLINE void CCU6_Ch3_CompState_Set(void)
1854 {
1856 }
1857 
1870 INLINE void CCU6_Ch0_CompState_Rst(void)
1871 {
1873 }
1874 
1887 INLINE void CCU6_Ch1_CompState_Rst(void)
1888 {
1890 }
1891 
1904 INLINE void CCU6_Ch2_CompState_Rst(void)
1905 {
1907 }
1908 
1921 INLINE void CCU6_Ch3_CompState_Rst(void)
1922 {
1924 }
1925 
1939 {
1941 }
1942 
1956 {
1958 }
1959 
1975 INLINE void CCU6_T12_Clk_Sel(uint16 t12clk)
1976 {
1978 }
1979 
1995 INLINE void CCU6_T13_Clk_Sel(uint16 t13clk)
1996 {
1998 }
1999 
2012 INLINE void CCU6_T12_Prescaler_En(void)
2013 {
2015 }
2016 
2029 INLINE void CCU6_T12_Prescaler_Dis(void)
2030 {
2032 }
2033 
2046 INLINE void CCU6_T13_Prescaler_En(void)
2047 {
2049 }
2050 
2063 INLINE void CCU6_T13_Prescaler_Dis(void)
2064 {
2066 }
2067 
2086 {
2088 }
2089 
2108 {
2110 }
2111 
2130 {
2132 }
2133 
2152 {
2154 }
2155 
2174 {
2176 }
2177 
2191 {
2193 }
2194 
2208 {
2210 }
2211 
2227 {
2229 }
2230 
2246 {
2248 }
2249 
2264 INLINE void CCU6_T12_Ext_Run_Sel(uint16 t12rsel)
2265 {
2267 }
2268 
2283 INLINE void CCU6_T13_Ext_Run_Sel(uint16 t13rsel)
2284 {
2286 }
2287 
2302 INLINE void CCU6_T12_Modulation_En(uint16 ccu6_mask)
2303 {
2305 }
2306 
2321 INLINE void CCU6_T12_Modulation_Dis(uint16 ccu6_mask)
2322 {
2324 }
2325 
2340 INLINE void CCU6_T13_Modulation_En(uint16 ccu6_mask)
2341 {
2343 }
2344 
2359 INLINE void CCU6_T13_Modulation_Dis(uint16 ccu6_mask)
2360 {
2362 }
2363 
2376 INLINE void CCU6_Multi_Ch_Mode_En(void)
2377 {
2379 }
2380 
2393 INLINE void CCU6_Multi_Ch_Mode_Dis(void)
2394 {
2396 }
2397 
2411 {
2413 }
2414 
2428 {
2430 }
2431 
2445 {
2447 }
2448 
2462 {
2464 }
2465 
2479 {
2481 }
2482 
2495 INLINE void CCU6_Trap_HW_Clr_En(void)
2496 {
2498 }
2499 
2512 INLINE void CCU6_Trap_SW_Clr_En(void)
2513 {
2515 }
2516 
2529 INLINE void CCU6_Trap_T13_En(void)
2530 {
2532 }
2533 
2546 INLINE void CCU6_Trap_T13_Dis(void)
2547 {
2549 }
2550 
2563 INLINE void CCU6_Trap_Pin_En(void)
2564 {
2566 }
2567 
2580 INLINE void CCU6_Trap_Pin_Dis(void)
2581 {
2583 }
2584 
2599 INLINE void CCU6_Trap_Channel_En(uint16 ccu6_mask)
2600 {
2602 }
2603 
2634 {
2635  Field_Mod16(&CCU6->CMPSTAT.reg, (uint16)CCU6_CMPSTAT_CC60PS_Pos, (uint16)0x3F00, ccu6_mask);
2636  CCU6_T12_Str_En();
2637 }
2638 
2652 {
2653  Field_Mod16(&CCU6->PSLR.reg, 0u, 0x01u, 1u);
2654 }
2655 
2669 {
2670  Field_Mod16(&CCU6->PSLR.reg, 0u, 0x01u, 0u);
2671 }
2672 
2686 {
2687  Field_Mod16(&CCU6->PSLR.reg, 1u, 0x02u, 1u);
2688 }
2689 
2703 {
2704  Field_Mod16(&CCU6->PSLR.reg, 1u, 0x02u, 0u);
2705 }
2706 
2720 {
2721  Field_Mod16(&CCU6->PSLR.reg, 2u, 0x04u, 1u);
2722 }
2723 
2737 {
2738  Field_Mod16(&CCU6->PSLR.reg, 2u, 0x04u, 0u);
2739 }
2740 
2754 {
2755  Field_Mod16(&CCU6->PSLR.reg, 3u, 0x08u, 1u);
2756 }
2757 
2771 {
2772  Field_Mod16(&CCU6->PSLR.reg, 3u, 0x08u, 0u);
2773 }
2774 
2788 {
2789  Field_Mod16(&CCU6->PSLR.reg, 4u, 0x10u, 1u);
2790 }
2791 
2805 {
2806  Field_Mod16(&CCU6->PSLR.reg, 4u, 0x10u, 0u);
2807 }
2808 
2822 {
2823  Field_Mod16(&CCU6->PSLR.reg, 5u, 0x20u, 1u);
2824 }
2825 
2839 {
2840  Field_Mod16(&CCU6->PSLR.reg, 5u, 0x20u, 0u);
2841 }
2842 
2872 {
2873  Field_Mod16(&CCU6->PSLR.reg, (uint16)CCU6_PSLR_PSL_Pos, (uint16)CCU6_PSLR_PSL_Msk, ccu6_mask);
2874 }
2875 
2891 {
2893 }
2894 
2910 {
2912 }
2913 
2926 INLINE void CCU6_MCM_PWM_Str_SW_En(void)
2927 {
2929 }
2930 
2943 INLINE void CCU6_MCM_PWM_Str_HW_En(void)
2944 {
2946 }
2947 
2963 {
2964  Field_Mod16(&CCU6->MCMOUTS.reg, (uint16)CCU6_MCMOUTS_EXPHS_Pos, (uint16)CCU6_MCMOUTS_EXPHS_Msk, mcm_mask_ccpos);
2965 }
2966 
2982 {
2983  Field_Mod16(&CCU6->MCMOUTS.reg, (uint16)CCU6_MCMOUTS_CURHS_Pos, (uint16)CCU6_MCMOUTS_CURHS_Msk, mcm_mask_ccpos);
2984 }
2985 
2999 {
3001 }
3002 
3016 {
3018 }
3019 
3037 {
3039 }
3040 
3059 {
3060  return ( u8_Field_Rd16(&CCU6->MCMOUT.reg, (uint16)CCU6_MCMOUT_R_Pos, (uint16)CCU6_MCMOUT_R_Msk) );
3061 }
3062 
3080 {
3082 }
3083 
3101 {
3103 }
3104 
3119 INLINE void CCU6_MCM_Switch_Sel(uint16 swsel)
3120 {
3122 }
3123 
3137 {
3139 }
3140 
3154 {
3156 }
3157 
3171 {
3173 }
3174 
3188 {
3190 }
3191 
3205 {
3207 }
3208 
3222 {
3224 }
3225 
3239 {
3241 }
3242 
3256 {
3258 }
3259 
3273 {
3275 }
3276 
3290 {
3292 }
3293 
3307 {
3309 }
3310 
3324 {
3326 }
3327 
3341 {
3343 }
3344 
3358 {
3360 }
3361 
3375 {
3377 }
3378 
3399 {
3401 }
3402 
3423 {
3425 }
3426 
3447 {
3449 }
3450 
3471 {
3473 }
3474 
3495 {
3497 }
3498 
3519 {
3521 }
3522 
3543 {
3545 }
3546 
3567 {
3569 }
3570 
3591 {
3593 }
3594 
3615 {
3617 }
3618 
3639 {
3641 }
3642 
3663 {
3665 }
3666 
3687 {
3689 }
3690 
3711 {
3713 }
3714 
3733 {
3735 }
3736 
3757 {
3759 }
3760 
3780 {
3782 }
3783 
3803 {
3805 }
3806 
3826 {
3828 }
3829 
3849 {
3851 }
3852 
3872 {
3874 }
3875 
3895 {
3897 }
3898 
3917 INLINE void CCU6_T12_OM_Int_Set(void)
3918 {
3920 }
3921 
3940 INLINE void CCU6_T12_PM_Int_Set(void)
3941 {
3943 }
3944 
3963 INLINE void CCU6_T13_CM_Int_Set(void)
3964 {
3966 }
3967 
3986 INLINE void CCU6_T13_PM_Int_Set(void)
3987 {
3989 }
3990 
4009 INLINE void CCU6_Trap_Flag_Int_Set(void)
4010 {
4012 }
4013 
4027 {
4029 }
4030 
4050 {
4052 }
4053 
4073 {
4075 }
4076 
4092 INLINE void CCU6_MCM_Idle_Int_Set(void)
4093 {
4095 }
4096 
4115 INLINE void CCU6_MCM_Str_Int_Set(void)
4116 {
4118 }
4119 
4141 {
4143 }
4144 
4166 {
4168 }
4169 
4191 {
4193 }
4194 
4216 {
4218 }
4219 
4241 {
4243 }
4244 
4266 {
4268 }
4269 
4291 {
4293 }
4294 
4312 INLINE void CCU6_CH0_CM_R_Int_Clr(void)
4313 {
4315 }
4316 
4334 INLINE void CCU6_CH0_CM_F_Int_Clr(void)
4335 {
4337 }
4338 
4356 INLINE void CCU6_CH1_CM_R_Int_Clr(void)
4357 {
4359 }
4360 
4378 INLINE void CCU6_CH1_CM_F_Int_Clr(void)
4379 {
4381 }
4382 
4400 INLINE void CCU6_CH2_CM_R_Int_Clr(void)
4401 {
4403 }
4404 
4422 INLINE void CCU6_CH2_CM_F_Int_Clr(void)
4423 {
4425 }
4426 
4444 INLINE void CCU6_T12_OM_Int_Clr(void)
4445 {
4447 }
4448 
4466 INLINE void CCU6_T12_PM_Int_Clr(void)
4467 {
4469 }
4470 
4488 INLINE void CCU6_T13_CM_Int_Clr(void)
4489 {
4491 }
4492 
4510 INLINE void CCU6_T13_PM_Int_Clr(void)
4511 {
4513 }
4514 
4532 INLINE void CCU6_TRAP_Int_Clr(void)
4533 {
4535 }
4536 
4554 INLINE void CCU6_CHE_Int_Clr(void)
4555 {
4557 }
4558 
4576 INLINE void CCU6_WHE_Int_Clr(void)
4577 {
4579 }
4580 
4598 INLINE void CCU6_STR_Int_Clr(void)
4599 {
4601 }
4602 
4620 INLINE void CCU6_CH0_CM_R_Int_En(void)
4621 {
4623 }
4624 
4643 INLINE void CCU6_CH0_CM_R_Int_Dis(void)
4644 {
4646 }
4647 
4665 INLINE void CCU6_CH0_CM_F_Int_En(void)
4666 {
4668 }
4669 
4688 INLINE void CCU6_CH0_CM_F_Int_Dis(void)
4689 {
4691 }
4692 
4710 INLINE void CCU6_CH1_CM_R_Int_En(void)
4711 {
4713 }
4714 
4733 INLINE void CCU6_CH1_CM_R_Int_Dis(void)
4734 {
4736 }
4737 
4755 INLINE void CCU6_CH1_CM_F_Int_En(void)
4756 {
4758 }
4759 
4778 INLINE void CCU6_CH1_CM_F_Int_Dis(void)
4779 {
4781 }
4782 
4800 INLINE void CCU6_CH2_CM_R_Int_En(void)
4801 {
4803 }
4804 
4823 INLINE void CCU6_CH2_CM_R_Int_Dis(void)
4824 {
4826 }
4827 
4845 INLINE void CCU6_CH2_CM_F_Int_En(void)
4846 {
4848 }
4849 
4868 INLINE void CCU6_CH2_CM_F_Int_Dis(void)
4869 {
4871 }
4872 
4890 INLINE void CCU6_T12_OM_Int_En(void)
4891 {
4893 }
4894 
4913 INLINE void CCU6_T12_OM_Int_Dis(void)
4914 {
4916 }
4917 
4935 INLINE void CCU6_T12_PM_Int_En(void)
4936 {
4938 }
4939 
4958 INLINE void CCU6_T12_PM_Int_Dis(void)
4959 {
4961 }
4962 
4980 INLINE void CCU6_T13_CM_Int_En(void)
4981 {
4983 }
4984 
5003 INLINE void CCU6_T13_CM_Int_Dis(void)
5004 {
5006 }
5007 
5025 INLINE void CCU6_T13_PM_Int_En(void)
5026 {
5028 }
5029 
5048 INLINE void CCU6_T13_PM_Int_Dis(void)
5049 {
5051 }
5052 
5070 INLINE void CCU6_TRAP_Int_En(void)
5071 {
5073 }
5074 
5093 INLINE void CCU6_TRAP_Int_Dis(void)
5094 {
5096 }
5097 
5115 INLINE void CCU6_CHE_Int_En(void)
5116 {
5118 }
5119 
5138 INLINE void CCU6_CHE_Int_Dis(void)
5139 {
5141 }
5142 
5160 INLINE void CCU6_WHE_Int_En(void)
5161 {
5163 }
5164 
5183 INLINE void CCU6_WHE_Int_Dis(void)
5184 {
5186 }
5187 
5205 INLINE void CCU6_STR_Int_En(void)
5206 {
5208 }
5209 
5228 INLINE void CCU6_STR_Int_Dis(void)
5229 {
5231 }
5232 
5233 /*******************************************************************************
5234 ** Global Variable Declarations **
5235 *******************************************************************************/
5236 
5237 /*******************************************************************************
5238 ** Global Function Declarations **
5239 *******************************************************************************/
5244 void CCU6_Init(void);
5245 
5246 INLINE void CCU6_StartTmr_T12(void);
5247 INLINE void CCU6_StartTmr_T13(void);
5248 INLINE void CCU6_StopTmr_T12(void);
5249 INLINE void CCU6_StopTmr_T13(void);
5250 INLINE void CCU6_EnableST_T12(void);
5251 INLINE void CCU6_EnableST_T13(void);
5258 INLINE bool CCU6_IsT13Running(void);
5259 INLINE void CCU6_SetT13Trigger(uint16 Mask);
5260 INLINE void CCU6_SetT13Compare(uint16 Compare);
5267 INLINE void CCU6_EnableInt(uint16 Mask);
5268 INLINE void CCU6_ClearIntStatus(uint16 Mask);
5269 
5270 /*******************************************************************************
5271 ** Global Inline Function Definitions **
5272 *******************************************************************************/
5285 INLINE void CCU6_StartTmr_T12(void)
5286 {
5287  CCU6_T12_Start();
5288 }
5289 
5302 INLINE void CCU6_StartTmr_T13(void)
5303 {
5304  CCU6_T13_Start();
5305 }
5306 
5319 INLINE void CCU6_StopTmr_T12(void)
5320 {
5321  CCU6_T12_Stop();
5322 }
5323 
5336 INLINE void CCU6_StopTmr_T13(void)
5337 {
5338  CCU6_T13_Stop();
5339 }
5340 
5353 INLINE void CCU6_EnableST_T12(void)
5354 {
5355  CCU6_T12_Str_En();
5356 }
5357 
5370 INLINE void CCU6_EnableST_T13(void)
5371 {
5372  CCU6_T13_Str_En();
5373 }
5374 
5390 {
5391  CCU6_Ch0_Value_Set(tick);
5392 }
5393 
5409 {
5410  CCU6_Ch1_Value_Set(tick);
5411 }
5412 
5428 {
5429  CCU6_Ch2_Value_Set(tick);
5430 }
5431 
5447 {
5448  CCU6_Ch3_Value_Set(tick);
5449 }
5450 
5466 {
5467  CCU6_T13_Period_Value_Set((uint16)((uint32)CCU6_T13_CLK * us));
5468 }
5469 
5485 {
5487 }
5488 
5507 INLINE bool CCU6_IsT13Running(void)
5508 {
5509  bool res = false;
5510 
5511  if (CCU6_T13_Run_Sts() == (uint8)1)
5512  {
5513  res = true;
5514  }
5515 
5516  return (res);
5517 }
5518 
5533 INLINE void CCU6_SetT13Trigger(uint16 Mask)
5534 {
5535  /* Set trigger mask */
5536  Field_Wrt16(&CCU6->TCTR2.reg, 0, (uint16)0xFFFF, Mask);
5537 }
5538 
5553 INLINE void CCU6_SetT13Compare(uint16 Compare)
5554 {
5555  if (Compare < CCU6_T13_Period_Value_Get())
5556  {
5557  /* Set only the requested compare value if no period change is needed */
5558  CCU6_Ch3_Value_Set(Compare);
5559  }
5560  else
5561  {
5562  /* Period value < compare value ? --> increase the period value */
5563  if (Compare <= (uint16)0xFFFE)
5564  {
5565  /* Set requested compare value */
5566  CCU6_Ch3_Value_Set(Compare);
5567  /* increase period value to ensure the compare match */
5568  CCU6_T13_Period_Value_Set((Compare + 1u));
5569  }
5570  else
5571  {
5572  /* Requested value is not possible */
5573  /* Set the highest possible values that ensure a compare match*/
5574  CCU6_Ch3_Value_Set((uint16)0xFFFE);
5576  }
5577  }
5578 
5579  /* Enable shadow transfer */
5580  CCU6_T13_Str_En();
5581 }
5582 
5598 {
5599  Field_Wrt16(&CCU6->TCTR4.reg, 0, (uint16)0xFFFF, Mask);
5600 }
5601 
5619 {
5620  return (uint32)u16_Field_Rd16(&CCU6->CMPSTAT.reg, (uint8)CCU6_CMPSTAT_CCPOS0_Pos, 0x38u);
5621 }
5622 
5640 {
5641  return u16_Field_Rd16(&CCU6->MCMOUT.reg, 0, (uint16)0xFFFF);
5642 }
5643 
5659 {
5660  Field_Wrt16(&CCU6->MCMOUTS.reg, 0, (uint16)0xFFFF, Patterns);
5661 }
5662 
5678 {
5679  Field_Wrt16(&CCU6->MCMCTR.reg, 0, (uint16)0xFFFF, Mode);
5680 }
5681 
5697 {
5698  Field_Wrt16(&CCU6->MODCTR.reg, 0, (uint16)0xFFFF, Mode);
5699 }
5700 
5715 INLINE void CCU6_EnableInt(uint16 Mask)
5716 {
5717  Field_Wrt16(&CCU6->IEN.reg, 0, (uint16)0xFFFF, Mask);
5718 }
5719 
5735 {
5736  Field_Wrt16(&CCU6->ISR.reg, 0, (uint16)0xFFFF, Mask);
5737 }
5738 
5739 #endif
CCU6_STR_Int_Clr
INLINE void CCU6_STR_Int_Clr(void)
clears Multi-Channel Mode Shadow Transfer Interrupt flag.
Definition: ccu6.h:4592
CCU6_MCM_Str_T12_Up_Cnt_Dis
INLINE void CCU6_MCM_Str_T12_Up_Cnt_Dis(void)
disables Shadow Transfer for T12 Upcounting.
Definition: ccu6.h:3300
CCU6_CCPOS0_Input_Sel
INLINE void CCU6_CCPOS0_Input_Sel(uint16 ispos0)
selects Input for CCPOS0.
Definition: ccu6.h:729
CCU6_T12RSEL_T12HR_Rise
Definition: ccu6.h:351
CCU6_T13_PM_Int_Dis
INLINE void CCU6_T13_PM_Int_Dis(void)
disables Interrupt for T13 Period-Match.
Definition: ccu6.h:5042
CCU6_T13_Rst
INLINE void CCU6_T13_Rst(void)
resets CCU6 T13.
Definition: ccu6.h:581
CCU6_T12RSEL_Dis
Definition: ccu6.h:350
CCU6_PISEL2_ISCNT12_Msk
#define CCU6_PISEL2_ISCNT12_Msk
Definition: tle986x.h:7209
CCU6_IEN_ENCC60R_Pos
#define CCU6_IEN_ENCC60R_Pos
Definition: tle986x.h:7006
CCU6_IS_CHE_Pos
#define CCU6_IS_CHE_Pos
Definition: tle986x.h:7076
CCU6_T12_Count_Value_Set
INLINE void CCU6_T12_Count_Value_Set(uint16 t12cv)
sets Timer T12 Counter Value.
Definition: ccu6.h:1040
CCU6_CCPOS0_1_P03
Definition: ccu6.h:194
CCU6_PISEL0_IST12HR_Pos
#define CCU6_PISEL0_IST12HR_Pos
Definition: tle986x.h:7203
CCU6_TCTR0_STE13_Pos
#define CCU6_TCTR0_STE13_Pos
Definition: tle986x.h:7278
CCU6_TCTR4_T12CNT
Definition: ccu6.h:255
CCU6_CC63R_CCV_Msk
#define CCU6_CC63R_CCV_Msk
Definition: tle986x.h:6953
Field_Mod16
INLINE void Field_Mod16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:351
CCU6_IEN_ENT13CM_Pos
#define CCU6_IEN_ENT13CM_Pos
Definition: tle986x.h:7022
CCU6_MCMOUTS_STRHP_Pos
#define CCU6_MCMOUTS_STRHP_Pos
Definition: tle986x.h:7177
CCU6_Ch3_Value_Get
INLINE uint16 CCU6_Ch3_Value_Get(void)
reads Channel CC63 Compare Value.
Definition: ccu6.h:1511
CCU6_EnableST_T12
INLINE void CCU6_EnableST_T12(void)
Enable T12 Shadow Transfer.
Definition: ccu6.h:5344
CCU6_ISS_ST12OM_Msk
#define CCU6_ISS_ST12OM_Msk
Definition: tle986x.h:7129
CCU6_TCTR2_T13TED_Msk
#define CCU6_TCTR2_T13TED_Msk
Definition: tle986x.h:7288
CCU6_ISS_SCC61R_Msk
#define CCU6_ISS_SCC61R_Msk
Definition: tle986x.h:7121
CCU6_Ch0c_Passive_Level_High_Set
INLINE void CCU6_Ch0c_Passive_Level_High_Set(void)
sets Passive High Level of COUT60.
Definition: ccu6.h:2679
CCU6_CMPMODIF_MCC61R_Msk
#define CCU6_CMPMODIF_MCC61R_Msk
Definition: tle986x.h:6969
CCU6_TCTR4_T13RS_Pos
#define CCU6_TCTR4_T13RS_Pos
Definition: tle986x.h:7310
CCU6_TRPCTR_TRPEN13_Pos
#define CCU6_TRPCTR_TRPEN13_Pos
Definition: tle986x.h:7329
CCU6_ISR_RCC61F_Msk
#define CCU6_ISR_RCC61F_Msk
Definition: tle986x.h:7092
CCU6_INP_INPT13_Msk
#define CCU6_INP_INPT13_Msk
Definition: tle986x.h:7050
CCU6_CMPMODIF_MCC61S_Msk
#define CCU6_CMPMODIF_MCC61S_Msk
Definition: tle986x.h:6961
CCU6_PISEL2_T13EXT_Pos
#define CCU6_PISEL2_T13EXT_Pos
Definition: tle986x.h:7214
CCU6_TCTR4_T12RS_Msk
#define CCU6_TCTR4_T12RS_Msk
Definition: tle986x.h:7297
CCU6_ISR_RWHE_Pos
#define CCU6_ISR_RWHE_Pos
Definition: tle986x.h:7109
CCU6_ISR_RSTR_Msk
#define CCU6_ISR_RSTR_Msk
Definition: tle986x.h:7114
CCU6_ISR_RCC60F_Msk
#define CCU6_ISR_RCC60F_Msk
Definition: tle986x.h:7088
CCU6_Ch1_Input_Sel
INLINE void CCU6_Ch1_Input_Sel(uint16 iscc61)
selects Input for CC61.
Definition: ccu6.h:672
CCU6_T13HR_Rising_Edge
Definition: ccu6.h:267
CCU6_ISR_RCHE_Msk
#define CCU6_ISR_RCHE_Msk
Definition: tle986x.h:7108
CCU6_MCM_Str_T12_Down_Cnt_En
INLINE void CCU6_MCM_Str_T12_Down_Cnt_En(void)
enables Shadow Transfer for T12 Downcounting.
Definition: ccu6.h:3317
CCU6_TCTR0_T13CLK_Msk
#define CCU6_TCTR0_T13CLK_Msk
Definition: tle986x.h:7273
CCU6_T12_CM_CC60_Int_Fall_Set
INLINE void CCU6_T12_CM_CC60_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 0.
Definition: ccu6.h:3842
CCU6_MCMOUTS_EXPHS_Msk
#define CCU6_MCMOUTS_EXPHS_Msk
Definition: tle986x.h:7174
CCU6_MCM_Switch_Sel
INLINE void CCU6_MCM_Switch_Sel(uint16 swsel)
selects Switching Mode.
Definition: ccu6.h:3113
CCU6_T13HR_0_P01
Definition: ccu6.h:245
CCU6_TRAP_Int_En
INLINE void CCU6_TRAP_Int_En(void)
enables Interrupt for Trap Flag.
Definition: ccu6.h:5064
CCU6_PSLR_PSL_Pos
#define CCU6_PSLR_PSL_Pos
Definition: tle986x.h:7217
CCU6_T13_PM_Int_Sts
INLINE uint8 CCU6_T13_PM_Int_Sts(void)
reads Timer T13 Period-Match Flag Status.
Definition: ccu6.h:3608
CCU6_TCTR0_T12CLK_Msk
#define CCU6_TCTR0_T12CLK_Msk
Definition: tle986x.h:7261
CCU6_Trap_Asynch_Exit_En
INLINE void CCU6_Trap_Asynch_Exit_En(void)
enables Trap Immediately without any synchronization to T12 or T13.
Definition: ccu6.h:2472
CCU6_T13_CM_Int_Sts
INLINE uint8 CCU6_T13_CM_Int_Sts(void)
reads Timer T13 Compare-Match Flag Status.
Definition: ccu6.h:3584
CCU6_MODCTR_MCMEN_Pos
#define CCU6_MODCTR_MCMEN_Pos
Definition: tle986x.h:7182
CCU6_T12_Prescaler_En
INLINE void CCU6_T12_Prescaler_En(void)
enables additional prescaler for Timer T12.
Definition: ccu6.h:2006
CCU6_T12DTC_DTM_Pos
#define CCU6_T12DTC_DTM_Pos
Definition: tle986x.h:7225
CCU6_IEN_ENT12OM_Msk
#define CCU6_IEN_ENT12OM_Msk
Definition: tle986x.h:7019
CCU6_MCMCTR_SWSEL_Pos
#define CCU6_MCMCTR_SWSEL_Pos
Definition: tle986x.h:7149
CCU6_Ch3c_Passive_State_After_Compare_Set
INLINE void CCU6_Ch3c_Passive_State_After_Compare_Set(void)
sets Passive state for COUT63 after Compare.
Definition: ccu6.h:1721
TCCU6_T13ED
TCCU6_T13ED
This enum lists the CCU6 T13 Trigger Event Direction.
Definition: ccu6.h:337
CCU6_MCMOUT_CURH_Msk
#define CCU6_MCMOUT_CURH_Msk
Definition: tle986x.h:7167
CCU6_T12_CM_CC62_Int_Rise_Sts
INLINE uint8 CCU6_T12_CM_CC62_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 2.
Definition: ccu6.h:3440
CCU6_Clk_Div_64
Definition: ccu6.h:315
CCU6_TCTR4_T12RES_Msk
#define CCU6_TCTR4_T12RES_Msk
Definition: tle986x.h:7299
CCU6_ISR_RTRPF_Msk
#define CCU6_ISR_RTRPF_Msk
Definition: tle986x.h:7106
CCU6_LoadPeriodRegister_T13_Tick
INLINE void CCU6_LoadPeriodRegister_T13_Tick(uint16 tick)
Load Timer13 Period Register as Time Value.
Definition: ccu6.h:5475
CCU6_Ch2_Deadtime_Dis
INLINE void CCU6_Ch2_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 2 Deadtime.
Definition: ccu6.h:1344
CCU6_T13_CM_Int_Dis
INLINE void CCU6_T13_CM_Int_Dis(void)
disables Interrupt for T13 Compare-Match.
Definition: ccu6.h:4997
CCU6_SWSEL_T13_PM
Definition: ccu6.h:383
CCU6_T13PR_T13PV_Msk
#define CCU6_T13PR_T13PV_Msk
Definition: tle986x.h:7258
CCU6_CH1_CM_F_Int_Clr
INLINE void CCU6_CH1_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 1.
Definition: ccu6.h:4372
CCU6_ISR_RCC62R_Msk
#define CCU6_ISR_RCC62R_Msk
Definition: tle986x.h:7094
CCU6_PISEL0_ISCC60_Msk
#define CCU6_PISEL0_ISCC60_Msk
Definition: tle986x.h:7190
CCU6_ISS_SWHC_Pos
#define CCU6_ISS_SWHC_Pos
Definition: tle986x.h:7138
CCU6_CMPSTAT_COUT63PS_Pos
#define CCU6_CMPSTAT_COUT63PS_Pos
Definition: tle986x.h:7001
CCU6_T12_ActiveCenterAligned
Definition: ccu6.h:409
CCU6_T13ED_T12_Down
Definition: ccu6.h:341
CCU6_T13_Str_En
INLINE void CCU6_T13_Str_En(void)
enables T13 Shadow Transfer.
Definition: ccu6.h:617
CCU6_CH0_CM_F_Int_Clr
INLINE void CCU6_CH0_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 0.
Definition: ccu6.h:4328
CCU6_CHE_Int_Clr
INLINE void CCU6_CHE_Int_Clr(void)
clears Interrupt for Correct Hall Event flag.
Definition: ccu6.h:4548
types.h
General type declarations.
CCU6_ISR_RCC61R_Msk
#define CCU6_ISR_RCC61R_Msk
Definition: tle986x.h:7090
CCU6_T12_CM_CC61_Int_Rise_Set
INLINE void CCU6_T12_CM_CC61_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 1.
Definition: ccu6.h:3796
CCU6_MCMOUTS_EXPHS_Pos
#define CCU6_MCMOUTS_EXPHS_Pos
Definition: tle986x.h:7173
CCU6_INP_INPT12_Pos
#define CCU6_INP_INPT12_Pos
Definition: tle986x.h:7047
CCU6_T12_PM_Int_Clr
INLINE void CCU6_T12_PM_Int_Clr(void)
clears Interrupt for T12 Period-Match Flag.
Definition: ccu6.h:4460
CCU6_MCM_Switch_Sync_T13_ZM_Sel
INLINE void CCU6_MCM_Switch_Sync_T13_ZM_Sel(void)
sets T13 zero-match Switching Synchronization.
Definition: ccu6.h:3249
CCU6_ISS_SSTR_Pos
#define CCU6_ISS_SSTR_Pos
Definition: tle986x.h:7146
CCU6_HW_Hall_Sampling_Off
Definition: ccu6.h:297
CCU6_MCMOUT_CURH_Pos
#define CCU6_MCMOUT_CURH_Pos
Definition: tle986x.h:7166
CCU6_Ch3_CompState_Rst
INLINE void CCU6_Ch3_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 3 (CC63ST) by Software.
Definition: ccu6.h:1915
CCU6_TCTR4_T12RES_Pos
#define CCU6_TCTR4_T12RES_Pos
Definition: tle986x.h:7298
CCU6_MCM_Idle_Int_Set
INLINE void CCU6_MCM_Idle_Int_Set(void)
sets Interrupt for IDLE flag.
Definition: ccu6.h:4086
CCU6_PISEL0_ISPOS2_Msk
#define CCU6_PISEL0_ISPOS2_Msk
Definition: tle986x.h:7202
CCU6_TCTR0_STE12_Msk
#define CCU6_TCTR0_STE12_Msk
Definition: tle986x.h:7267
CCU6_Trap_Input_Sel
INLINE void CCU6_Trap_Input_Sel(uint16 istrp)
selects Input for CTRAP.
Definition: ccu6.h:710
CCU6_TRPCTR_TRPEN_Msk
#define CCU6_TRPCTR_TRPEN_Msk
Definition: tle986x.h:7328
CCU6_Ch0_Value_Set
INLINE void CCU6_Ch0_Value_Set(uint16 cc60sr)
sets Channel 0 Capture/Compare Value.
Definition: ccu6.h:1122
CCU6_T12_OM_Int_Sts
INLINE uint8 CCU6_T12_OM_Int_Sts(void)
reads Timer T12 One-Match Flag Status.
Definition: ccu6.h:3536
CCU6_INP_INPCC61_Pos
#define CCU6_INP_INPCC61_Pos
Definition: tle986x.h:7039
CCU6_PSLR_PSL_Msk
#define CCU6_PSLR_PSL_Msk
Definition: tle986x.h:7218
CCU6_T12_OM_Int_Dis
INLINE void CCU6_T12_OM_Int_Dis(void)
disables Interrupt for T12 One-Match.
Definition: ccu6.h:4907
CCU6_Hall_Wrong_Int_Set
INLINE void CCU6_Hall_Wrong_Int_Set(void)
sets Interrupt for Wrong Hall Event flag.
Definition: ccu6.h:4066
CCU6_ISR_RSTR_Pos
#define CCU6_ISR_RSTR_Pos
Definition: tle986x.h:7113
CCU6_EnableST_T13
INLINE void CCU6_EnableST_T13(void)
Enable T13 Shadow Transfer.
Definition: ccu6.h:5361
CCU6_T12MSEL_MSEL62_Msk
#define CCU6_T12MSEL_MSEL62_Msk
Definition: tle986x.h:7245
CCU6_ISS_ST13PM_Msk
#define CCU6_ISS_ST13PM_Msk
Definition: tle986x.h:7135
CCU6_T12HR_0_P00
Definition: ccu6.h:236
CCU6_CMPSTAT_CC62ST_Pos
#define CCU6_CMPSTAT_CC62ST_Pos
Definition: tle986x.h:6979
CCU6_MCM_PWM_Str_HW_En
INLINE void CCU6_MCM_PWM_Str_HW_En(void)
enables Shadow Transfer Request for MCMPS by Hardware.
Definition: ccu6.h:2937
CCU6_Ch2_Deadtime_Sts
INLINE uint8 CCU6_Ch2_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 2 Deadtime Status.
Definition: ccu6.h:1410
CCU6_T12DTC_DTR1_Pos
#define CCU6_T12DTC_DTR1_Pos
Definition: tle986x.h:7235
CCU6_ISS_SCC60F_Msk
#define CCU6_ISS_SCC60F_Msk
Definition: tle986x.h:7119
CCU6_Clk_Div_2
Definition: ccu6.h:310
CCU6_T12_OM_Int_Set
INLINE void CCU6_T12_OM_Int_Set(void)
sets Interrupt for T12 One-Match Flag.
Definition: ccu6.h:3911
CCU6_PISEL0_ISPOS0_Pos
#define CCU6_PISEL0_ISPOS0_Pos
Definition: tle986x.h:7197
CCU6_TCTR4_T12RS_Pos
#define CCU6_TCTR4_T12RS_Pos
Definition: tle986x.h:7296
CCU6_CMPSTAT_CCPOS2_Msk
#define CCU6_CMPSTAT_CCPOS2_Msk
Definition: tle986x.h:6988
CCU6_T12_Count_Value_Get
INLINE uint16 CCU6_T12_Count_Value_Get(void)
reads Timer T12 Counter Value.
Definition: ccu6.h:1020
CCU6_T12DTC_DTE2_Msk
#define CCU6_T12DTC_DTE2_Msk
Definition: tle986x.h:7232
CCU6_PISEL2_IST13HR_Pos
#define CCU6_PISEL2_IST13HR_Pos
Definition: tle986x.h:7206
CCU6_Deadtime_Rst
INLINE void CCU6_Deadtime_Rst(void)
resets CCU6 T12 Dead-Time Counter.
Definition: ccu6.h:477
CCU6_TCTR4_T12RR_Pos
#define CCU6_TCTR4_T12RR_Pos
Definition: tle986x.h:7294
CCU6_T13HR_2_P22
Definition: ccu6.h:246
CCU6_ISR_RT12OM_Pos
#define CCU6_ISR_RT12OM_Pos
Definition: tle986x.h:7097
TCCU6_T13_Ext_Input
TCCU6_T13_Ext_Input
This enum lists the CCU6 T13EXT Inputs.
Definition: ccu6.h:283
CCU6_TCTR4_T13RR_Pos
#define CCU6_TCTR4_T13RR_Pos
Definition: tle986x.h:7308
CCU6_Hall_Ch1_Sts
INLINE uint8 CCU6_Hall_Ch1_Sts(void)
reads Sampled Hall Pattern Bit 1.
Definition: ccu6.h:1666
CCU6_CTRAP_1_P23
Definition: ccu6.h:186
CCU6_MCM_Switch_T12_PM_Set
INLINE void CCU6_MCM_Switch_T12_PM_Set(void)
sets T12 period-match Switching Mode.
Definition: ccu6.h:3215
CCU6_T12_OM_Int_En
INLINE void CCU6_T12_OM_Int_En(void)
enables Interrupt for T12 One-Match.
Definition: ccu6.h:4884
CCU6_T12_CM_CC60_Int_Rise_Sts
INLINE uint8 CCU6_T12_CM_CC60_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 0.
Definition: ccu6.h:3392
CCU6_ISS_SCC60R_Msk
#define CCU6_ISS_SCC60R_Msk
Definition: tle986x.h:7117
CCU6_MCMOUT_EXPH_Msk
#define CCU6_MCMOUT_EXPH_Msk
Definition: tle986x.h:7165
CCU6_Ch1_Value_Get
INLINE uint16 CCU6_Ch1_Value_Get(void)
reads Channel 1 Capture/Compare Value.
Definition: ccu6.h:1143
CCU6_T12_PM_Int_Set
INLINE void CCU6_T12_PM_Int_Set(void)
sets Interrupt for T12 Period-Match Flag.
Definition: ccu6.h:3934
CCU6_IEN_ENTRPF_Msk
#define CCU6_IEN_ENTRPF_Msk
Definition: tle986x.h:7027
CCU6_T12PR_T12PV_Pos
#define CCU6_T12PR_T12PV_Pos
Definition: tle986x.h:7251
CCU6_T12_Rst
INLINE void CCU6_T12_Rst(void)
resets CCU6 T12.
Definition: ccu6.h:460
CCU6_T13_Compare_Out_En
INLINE void CCU6_T13_Compare_Out_En(void)
enables Compare Timer T13 Output
Definition: ccu6.h:2404
CCU6_T12RSEL_T12HR_Fall
Definition: ccu6.h:352
CCU6_LoadShadowRegister_CC62
INLINE void CCU6_LoadShadowRegister_CC62(uint16 tick)
Load Channel 2 compare value to the shadow register.
Definition: ccu6.h:5418
CCU6_MCMOUT_MCMP_Msk
#define CCU6_MCMOUT_MCMP_Msk
Definition: tle986x.h:7161
CCU6_T12_OM_Int_Clr
INLINE void CCU6_T12_OM_Int_Clr(void)
clears Interrupt for T12 One-Match Flag.
Definition: ccu6.h:4438
CCU6_Ch0_Input_Sel
INLINE void CCU6_Ch0_Input_Sel(uint16 iscc60)
selects Input for CC60.
Definition: ccu6.h:653
CCU6_Ch0_Value_Get
INLINE uint16 CCU6_Ch0_Value_Get(void)
reads Channel 0 Capture/Compare Value.
Definition: ccu6.h:1103
CCU6_SetT12T13ControlBits
INLINE void CCU6_SetT12T13ControlBits(uint16 Mask)
Sets write-only control bits for T12 and/or T13 timer.
Definition: ccu6.h:5588
CCU6_T13_Period_Value_Get
INLINE uint16 CCU6_T13_Period_Value_Get(void)
reads Timer T13 Period Value.
Definition: ccu6.h:1471
CCU6_T12_PWMMode_Set
INLINE void CCU6_T12_PWMMode_Set(TCCU6_PWMMode mode)
sets mode of PWM signal for Channel0/1/2 and COUT0/1/2.
Definition: ccu6.h:1699
CCU6_Trap_Flag_Int_Sts
INLINE uint8 CCU6_Trap_Flag_Int_Sts(void)
reads Trap Flag Status.
Definition: ccu6.h:3632
CCU6_Ch1c_Passive_Level_Low_Set
INLINE void CCU6_Ch1c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT61.
Definition: ccu6.h:2764
CCU6_TCTR4_T12STD_Msk
#define CCU6_TCTR4_T12STD_Msk
Definition: tle986x.h:7307
CCU6_T13RSEL_T13HR_Rise
Definition: ccu6.h:362
CCU6_CC61R_CCV_Msk
#define CCU6_CC61R_CCV_Msk
Definition: tle986x.h:6941
CCU6_CC62_2_P22
Definition: ccu6.h:177
CCU6_CTRAP_0_P24
Definition: ccu6.h:185
CCU6_Ch0c_Passive_Level_Low_Set
INLINE void CCU6_Ch0c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT60.
Definition: ccu6.h:2696
CCU6_TCTR4_T12STD_Pos
#define CCU6_TCTR4_T12STD_Pos
Definition: tle986x.h:7306
CCU6_MCM_Hall_Str_HW_En
INLINE void CCU6_MCM_Hall_Str_HW_En(void)
enables Shadow Transfer Request for the Hall Pattern by Hardware.
Definition: ccu6.h:3009
CCU6_Ch2c_Passive_Level_High_Set
INLINE void CCU6_Ch2c_Passive_Level_High_Set(void)
sets Passive High Level of COUT62.
Definition: ccu6.h:2815
CCU6_StartTmr_T13
INLINE void CCU6_StartTmr_T13(void)
Start CCU6 Timer T13.
Definition: ccu6.h:5293
CCU6_CMPSTAT_CC61ST_Pos
#define CCU6_CMPSTAT_CC61ST_Pos
Definition: tle986x.h:6977
CCU6_TCTR2_T12SSC_Pos
#define CCU6_TCTR2_T12SSC_Pos
Definition: tle986x.h:7281
CCU6_Ch2_Input_Sel
INLINE void CCU6_Ch2_Input_Sel(uint16 iscc62)
selects Input for CC62.
Definition: ccu6.h:691
CCU6_WHE_Int_En
INLINE void CCU6_WHE_Int_En(void)
enables Interrupt for Wrong Hall Event.
Definition: ccu6.h:5154
CCU6_IS_ICC60F_Pos
#define CCU6_IS_ICC60F_Pos
Definition: tle986x.h:7058
CCU6_Hall_Ch0_Sts
INLINE uint8 CCU6_Hall_Ch0_Sts(void)
reads Sampled Hall Pattern Bit 0.
Definition: ccu6.h:1644
CCU6_CC60R_CCV_Pos
#define CCU6_CC60R_CCV_Pos
Definition: tle986x.h:6934
CCU6_T12_Center_Aligned_Mode_En
INLINE void CCU6_T12_Center_Aligned_Mode_En(void)
enables T12 Operating Center-aligned Mode.
Definition: ccu6.h:1949
CCU6_CH0_CM_R_Int_Dis
INLINE void CCU6_CH0_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 0.
Definition: ccu6.h:4637
CCU6_StartTmr_T12
INLINE void CCU6_StartTmr_T12(void)
Start CCU6 Timer T12.
Definition: ccu6.h:5276
CCU6_MODCTR_T13MODEN_Msk
#define CCU6_MODCTR_T13MODEN_Msk
Definition: tle986x.h:7185
CCU6_CMPMODIF_MCC60R_Pos
#define CCU6_CMPMODIF_MCC60R_Pos
Definition: tle986x.h:6966
CCU6_LoadPeriodRegister_T13_Time
INLINE void CCU6_LoadPeriodRegister_T13_Time(uint32 us)
Load Timer13 Period Register as Time Value.
Definition: ccu6.h:5456
CCU6_Trap_HW_Clr_En
INLINE void CCU6_Trap_HW_Clr_En(void)
enables Hardware reset of the Trap Mode.
Definition: ccu6.h:2489
CCU6_T12_Prescaler
Definition: ccu6.h:254
CCU6_TCTR2_T13TEC_Msk
#define CCU6_TCTR2_T13TEC_Msk
Definition: tle986x.h:7286
CCU6_TCTR2_T13TED_Pos
#define CCU6_TCTR2_T13TED_Pos
Definition: tle986x.h:7287
CCU6_T13_Run_Sts
INLINE uint8 CCU6_T13_Run_Sts(void)
reads Timer T13 Run Bit.
Definition: ccu6.h:2145
CCU6_T12DTC_DTR0_Msk
#define CCU6_T12DTC_DTR0_Msk
Definition: tle986x.h:7234
CCU6_MCMOUT_EXPH_Pos
#define CCU6_MCMOUT_EXPH_Pos
Definition: tle986x.h:7164
CCU6_Clk_Div_1
Definition: ccu6.h:309
CCU6_TCTR4_T13RR_Msk
#define CCU6_TCTR4_T13RR_Msk
Definition: tle986x.h:7309
CCU6_Node0
Definition: ccu6.h:394
CCU6_IS_WHE_Pos
#define CCU6_IS_WHE_Pos
Definition: tle986x.h:7078
CCU6_CH1_CM_R_Int_En
INLINE void CCU6_CH1_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 1.
Definition: ccu6.h:4704
u8_Field_Rd16
INLINE uint8 u8_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 8-bit field of a 16-bit register.
Definition: sfr_access.h:411
CCU6_T13TEC_T12_CM_Chx
Definition: ccu6.h:328
CCU6_Ch3_CompState_Sts
INLINE uint8 CCU6_Ch3_CompState_Sts(void)
reads CC63 Capture/Compare State.
Definition: ccu6.h:1622
CCU6_ISS_SCC62F_Pos
#define CCU6_ISS_SCC62F_Pos
Definition: tle986x.h:7126
CCU6_CC60_1_P23
Definition: ccu6.h:160
CCU6_IsT13Running
INLINE bool CCU6_IsT13Running(void)
reads Timer T13 Run Bit.
Definition: ccu6.h:5498
sfr_access.h
SFR low level access library.
CCU6_CC62_0_P13
Definition: ccu6.h:176
CCU6_T13_Period_Value_Set
INLINE void CCU6_T13_Period_Value_Set(uint16 t13pr)
sets Timer T13 Period Value.
Definition: ccu6.h:1490
CCU6_T12_CM_CC60_Int_Fall_Sts
INLINE uint8 CCU6_T12_CM_CC60_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 0.
Definition: ccu6.h:3464
CCU6_T12_Int_Node_Sel
INLINE void CCU6_T12_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Timer T12 Interrupts.
Definition: ccu6.h:4234
CCU6_CMPSTAT_T13IM_Msk
#define CCU6_CMPSTAT_T13IM_Msk
Definition: tle986x.h:7004
CCU6_Ch1c_Passive_Level_High_Set
INLINE void CCU6_Ch1c_Passive_Level_High_Set(void)
sets Passive High Level of COUT61.
Definition: ccu6.h:2747
CCU6_T12MSEL_HSYNC_Msk
#define CCU6_T12MSEL_HSYNC_Msk
Definition: tle986x.h:7247
CCU6_ISR_RCHE_Pos
#define CCU6_ISR_RCHE_Pos
Definition: tle986x.h:7107
CCU6_T12DTC_DTR2_Msk
#define CCU6_T12DTC_DTR2_Msk
Definition: tle986x.h:7238
CCU6_ISS_ST12OM_Pos
#define CCU6_ISS_ST12OM_Pos
Definition: tle986x.h:7128
u16_Field_Rd16
INLINE uint16 u16_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 16-bit field of a 16-bit register.
Definition: sfr_access.h:421
CCU6_ISR_RCC61F_Pos
#define CCU6_ISR_RCC61F_Pos
Definition: tle986x.h:7091
CCU6_T13_PM_Int_En
INLINE void CCU6_T13_PM_Int_En(void)
enables Interrupt for T13 Period-Match.
Definition: ccu6.h:5019
CCU6_Clk_Div_32
Definition: ccu6.h:314
CCU6_T12DTC_DTR0_Pos
#define CCU6_T12DTC_DTR0_Pos
Definition: tle986x.h:7233
CCU6_Node3
Definition: ccu6.h:397
CCU6_PISEL0_ISCC61_Pos
#define CCU6_PISEL0_ISCC61_Pos
Definition: tle986x.h:7191
CCU6_T13RSEL_T13HR_Any
Definition: ccu6.h:364
CCU6_MCMCTR_SWSYN_Msk
#define CCU6_MCMCTR_SWSYN_Msk
Definition: tle986x.h:7152
CCU6_MCMOUTS_MCMPS_Msk
#define CCU6_MCMOUTS_MCMPS_Msk
Definition: tle986x.h:7170
CCU6_MCM_Hall_Str_SW_En
INLINE void CCU6_MCM_Hall_Str_SW_En(void)
enables Shadow Transfer Request for the Hall Pattern by Software.
Definition: ccu6.h:2992
INLINE
#define INLINE
Definition: types.h:134
CCU6_CH2_CM_F_Int_Dis
INLINE void CCU6_CH2_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 2.
Definition: ccu6.h:4862
CCU6_PISEL0_IST12HR_Msk
#define CCU6_PISEL0_IST12HR_Msk
Definition: tle986x.h:7204
CCU6_T13_T13CV_Msk
#define CCU6_T13_T13CV_Msk
Definition: tle986x.h:7255
CCU6_TCTR2_T12RSEL_Pos
#define CCU6_TCTR2_T12RSEL_Pos
Definition: tle986x.h:7289
CCU6_MCM_Switch_T12_Ch1_CM_Set
INLINE void CCU6_MCM_Switch_T12_Ch1_CM_Set(void)
sets T12 channel1 compare-match Switching Mode.
Definition: ccu6.h:3198
CCU6_CMPMODIF_MCC61R_Pos
#define CCU6_CMPMODIF_MCC61R_Pos
Definition: tle986x.h:6968
CCU6_EnableInt
INLINE void CCU6_EnableInt(uint16 Mask)
Enables/disables interrupt(s).
Definition: ccu6.h:5706
CCU6_T12_CM_CC62_Int_Rise_Set
INLINE void CCU6_T12_CM_CC62_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 2.
Definition: ccu6.h:3819
CCU6_T13_Start
INLINE void CCU6_T13_Start(void)
starts CCU6 T13.
Definition: ccu6.h:564
CCU6_Trap_State_Int_Sts
INLINE uint8 CCU6_Trap_State_Int_Sts(void)
reads Trap Status.
Definition: ccu6.h:3656
CCU6_Ch0_CompState_Sts
INLINE uint8 CCU6_Ch0_CompState_Sts(void)
reads CC60 Capture/Compare State.
Definition: ccu6.h:1553
CCU6_T12MSEL_MSEL61_Pos
#define CCU6_T12MSEL_MSEL61_Pos
Definition: tle986x.h:7242
CCU6_LoadShadowRegister_CC60
INLINE void CCU6_LoadShadowRegister_CC60(uint16 tick)
Load Channel 0 compare value to the shadow register.
Definition: ccu6.h:5380
CCU6_Ch0_Deadtime_En
INLINE void CCU6_Ch0_Deadtime_En(void)
enables CCU6 Timer T12 Channel 0 Deadtime.
Definition: ccu6.h:1259
CCU6_SetT13Compare
INLINE void CCU6_SetT13Compare(uint16 Compare)
Sets compare value for the T13 timer.
Definition: ccu6.h:5544
CCU6_T13TEC_T12_CM_Ch1
Definition: ccu6.h:326
CCU6_CH1_CM_F_Int_En
INLINE void CCU6_CH1_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 1.
Definition: ccu6.h:4749
CCU6_MCMOUTS_STRMCM_Msk
#define CCU6_MCMOUTS_STRMCM_Msk
Definition: tle986x.h:7172
CCU6_TCTR4_T12STR_Pos
#define CCU6_TCTR4_T12STR_Pos
Definition: tle986x.h:7304
CCU6_T13TEC_No_Trigger
Definition: ccu6.h:324
CCU6_CH2_CM_F_Int_Clr
INLINE void CCU6_CH2_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 2.
Definition: ccu6.h:4416
CCU6_CC61R_CCV_Pos
#define CCU6_CC61R_CCV_Pos
Definition: tle986x.h:6940
CCU6_CMPMODIF_MCC62S_Msk
#define CCU6_CMPMODIF_MCC62S_Msk
Definition: tle986x.h:6963
CCU6_TRPCTR_TRPEN13_Msk
#define CCU6_TRPCTR_TRPEN13_Msk
Definition: tle986x.h:7330
CCU6_T12HR_H_E
Definition: ccu6.h:277
CCU6_CCPOS0_2_P13
Definition: ccu6.h:195
CCU6_ISS_ST12PM_Pos
#define CCU6_ISS_ST12PM_Pos
Definition: tle986x.h:7130
CCU6_TCTR2_T13TEC_Pos
#define CCU6_TCTR2_T13TEC_Pos
Definition: tle986x.h:7285
TCCU6_Ch2_Input
TCCU6_Ch2_Input
This enum lists the CCU6 channel 2 Inputs.
Definition: ccu6.h:174
CCU6_T13_Count_Value_Get
INLINE uint16 CCU6_T13_Count_Value_Get(void)
reads Timer T13 Counter Value.
Definition: ccu6.h:1431
CCU6_CMPSTAT_CCPOS0_Msk
#define CCU6_CMPSTAT_CCPOS0_Msk
Definition: tle986x.h:6984
CCU6_IEN_ENCC60F_Pos
#define CCU6_IEN_ENCC60F_Pos
Definition: tle986x.h:7008
CCU6_TCTR0_T12PRE_Pos
#define CCU6_TCTR0_T12PRE_Pos
Definition: tle986x.h:7262
CCU6_MCM_Str_T13_Up_Cnt_En
INLINE void CCU6_MCM_Str_T13_Up_Cnt_En(void)
enables Shadow Transfer for T13 Upcounting.
Definition: ccu6.h:3351
CCU6_T12HR_Input_Sel
INLINE void CCU6_T12HR_Input_Sel(uint16 ist12hr)
selects Input for T12HR.
Definition: ccu6.h:787
CCU6_ISS_SCC61F_Pos
#define CCU6_ISS_SCC61F_Pos
Definition: tle986x.h:7122
CCU6_Ch1t_Passive_Level_Low_Set
INLINE void CCU6_Ch1t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC61.
Definition: ccu6.h:2730
CCU6_T12DTC_DTE1_Msk
#define CCU6_T12DTC_DTE1_Msk
Definition: tle986x.h:7230
CCU6_TCTR0_T13R_Pos
#define CCU6_TCTR0_T13R_Pos
Definition: tle986x.h:7276
CCU6_Hall_Correct_Int_Set
INLINE void CCU6_Hall_Correct_Int_Set(void)
sets Interrupt for Correct Hall Event flag.
Definition: ccu6.h:4043
uint16
unsigned short uint16
16 bit unsigned value
Definition: types.h:140
CCU6_Ch0_Int_Node_Sel
INLINE void CCU6_Ch0_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 0 Interrupts.
Definition: ccu6.h:4134
CCU6_Ch0_CapCom_Mode_Sel
INLINE void CCU6_Ch0_CapCom_Mode_Sel(uint16 msel60)
selects CCU6 T12 CH0 Capture/Compare Mode.
Definition: ccu6.h:999
CCU6_T13_Cnt
INLINE void CCU6_T13_Cnt(void)
counts 1 step for CCU6 T13 Event.
Definition: ccu6.h:600
CCU6_PISEL2_T12EXT_Msk
#define CCU6_PISEL2_T12EXT_Msk
Definition: tle986x.h:7213
CCU6_IS_T13PM_Msk
#define CCU6_IS_T13PM_Msk
Definition: tle986x.h:7071
CCU6_T13_CM_Int_Set
INLINE void CCU6_T13_CM_Int_Set(void)
sets Interrupt for T13 Compare-Match Flag.
Definition: ccu6.h:3957
CCU6_T12_Ext_Input_Sel
INLINE void CCU6_T12_Ext_Input_Sel(uint16 t12ext)
selects Input of Extension for T12HR.
Definition: ccu6.h:869
CCU6_IS_ICC61F_Msk
#define CCU6_IS_ICC61F_Msk
Definition: tle986x.h:7061
CCU6_IEN_ENWHE_Msk
#define CCU6_IEN_ENWHE_Msk
Definition: tle986x.h:7031
CCU6_T12_T12CV_Msk
#define CCU6_T12_T12CV_Msk
Definition: tle986x.h:7223
TCCU6_PSL63
TCCU6_PSL63
This enum lists the CCU6 COUT63 Passive Level.
Definition: ccu6.h:370
CCU6_ISR_RCC60R_Msk
#define CCU6_ISR_RCC60R_Msk
Definition: tle986x.h:7086
CCU6_TCTR4_T12RR_Msk
#define CCU6_TCTR4_T12RR_Msk
Definition: tle986x.h:7295
CCU6_Ch2_CompState_Sts
INLINE uint8 CCU6_Ch2_CompState_Sts(void)
reads CC62 Capture/Compare State.
Definition: ccu6.h:1599
CCU6_ISR_RT13CM_Msk
#define CCU6_ISR_RT13CM_Msk
Definition: tle986x.h:7102
CCU6_CMPMODIF_MCC63S_Pos
#define CCU6_CMPMODIF_MCC63S_Pos
Definition: tle986x.h:6964
CCU6_Passive_State_After_Compare_Sel
INLINE void CCU6_Passive_State_After_Compare_Sel(uint16 ccu6_mask)
Sets the passive state to "after" the compare value.
Definition: ccu6.h:2627
CCU6_PISEL0_ISTRP_Msk
#define CCU6_PISEL0_ISTRP_Msk
Definition: tle986x.h:7196
CCU6_IS_T13PM_Pos
#define CCU6_IS_T13PM_Pos
Definition: tle986x.h:7070
CCU6_T13_Trig_Event_Dir_Sel
INLINE void CCU6_T13_Trig_Event_Dir_Sel(uint16 t13ted)
selects Timer T13 Trigger Event Direction.
Definition: ccu6.h:2239
CCU6_MCMCTR_STE13U_Msk
#define CCU6_MCMCTR_STE13U_Msk
Definition: tle986x.h:7158
CCU6_ISS_ST13CM_Pos
#define CCU6_ISS_ST13CM_Pos
Definition: tle986x.h:7132
CCU6_Hall_Delay_Bypass_En
INLINE void CCU6_Hall_Delay_Bypass_En(void)
enables Hall Delay Bypass.
Definition: ccu6.h:906
CCU6_T13_Cnt_Input_Sel
INLINE void CCU6_T13_Cnt_Input_Sel(uint16 iscnt13)
selects Input for T13 Counting.
Definition: ccu6.h:849
CCU6_IEN_ENT13PM_Pos
#define CCU6_IEN_ENT13PM_Pos
Definition: tle986x.h:7024
CCU6_T12_Single_Shot_En
INLINE void CCU6_T12_Single_Shot_En(void)
enables Timer T12 Single Shot.
Definition: ccu6.h:2184
CCU6_CC60R_CCV_Msk
#define CCU6_CC60R_CCV_Msk
Definition: tle986x.h:6935
CCU6_IEN_ENT12OM_Pos
#define CCU6_IEN_ENT12OM_Pos
Definition: tle986x.h:7018
CCU6_Trap_Flag_Int_Set
INLINE void CCU6_Trap_Flag_Int_Set(void)
sets Trap Flag.
Definition: ccu6.h:4003
CCU6_CMPSTAT_CC63ST_Pos
#define CCU6_CMPSTAT_CC63ST_Pos
Definition: tle986x.h:6981
CCU6_T13TEC_T12_ZM
Definition: ccu6.h:330
CCU6_CH2_CM_R_Int_Clr
INLINE void CCU6_CH2_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 2.
Definition: ccu6.h:4394
CCU6_T13_PM_Int_Set
INLINE void CCU6_T13_PM_Int_Set(void)
sets Interrupt for T13 Period-Match Flag.
Definition: ccu6.h:3980
CCU6_T13HR_H_E
Definition: ccu6.h:286
CCU6_Trap_SW_Clr_En
INLINE void CCU6_Trap_SW_Clr_En(void)
enables Software reset of the Trap Mode.
Definition: ccu6.h:2506
CCU6_MCMOUT_R_Pos
#define CCU6_MCMOUT_R_Pos
Definition: tle986x.h:7162
CCU6_MCMOUT_R_Msk
#define CCU6_MCMOUT_R_Msk
Definition: tle986x.h:7163
CCU6_Ch1_Deadtime_En
INLINE void CCU6_Ch1_Deadtime_En(void)
enables CCU6 Timer T12 Channel 1 Deadtime.
Definition: ccu6.h:1276
CCU6_IS_STR_Pos
#define CCU6_IS_STR_Pos
Definition: tle986x.h:7082
CCU6_T13_T13CV_Pos
#define CCU6_T13_T13CV_Pos
Definition: tle986x.h:7254
CCU6_IEN_ENCC62F_Msk
#define CCU6_IEN_ENCC62F_Msk
Definition: tle986x.h:7017
CCU6_MCM_Switch_Sync_direct_Sel
INLINE void CCU6_MCM_Switch_Sync_direct_Sel(void)
sets Direct Switching Synchronization.
Definition: ccu6.h:3232
CCU6_T12_Single_Shot_Dis
INLINE void CCU6_T12_Single_Shot_Dis(void)
disables Timer T12 Single Shot.
Definition: ccu6.h:2201
CCU6_MODCTR_ECT13O_Msk
#define CCU6_MODCTR_ECT13O_Msk
Definition: tle986x.h:7187
CCU6_IEN_ENCC62R_Pos
#define CCU6_IEN_ENCC62R_Pos
Definition: tle986x.h:7014
CCU6_ISS_SCC62F_Msk
#define CCU6_ISS_SCC62F_Msk
Definition: tle986x.h:7127
CCU6_T12_Prescaler_Dis
INLINE void CCU6_T12_Prescaler_Dis(void)
disables additional prescaler for Timer T12.
Definition: ccu6.h:2023
CCU6_CCPOS1_2_P14
Definition: ccu6.h:210
CCU6_Ch2_Value_Set
INLINE void CCU6_Ch2_Value_Set(uint16 cc62sr)
sets Channel 2 Capture/Compare Value.
Definition: ccu6.h:1202
CCU6_TCTR0_T12R_Pos
#define CCU6_TCTR0_T12R_Pos
Definition: tle986x.h:7264
CCU6_T13_Str_Dis
INLINE void CCU6_T13_Str_Dis(void)
disables T13 Shadow Transfer.
Definition: ccu6.h:634
CCU6_Trap_T12_ZM_Exit_En
INLINE void CCU6_Trap_T12_ZM_Exit_En(void)
enables T12 zero-match Trap Mode
Definition: ccu6.h:2438
CCU6_T12_CM_CC61_Int_Rise_Sts
INLINE uint8 CCU6_T12_CM_CC61_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 1.
Definition: ccu6.h:3416
CCU6_CMPMODIF_MCC63R_Pos
#define CCU6_CMPMODIF_MCC63R_Pos
Definition: tle986x.h:6972
CCU6_TCTR4_T13STR_Pos
#define CCU6_TCTR4_T13STR_Pos
Definition: tle986x.h:7316
CCU6_MCM_PWM_Str_SW_En
INLINE void CCU6_MCM_PWM_Str_SW_En(void)
enables Shadow Transfer Request for MCMPS by Software.
Definition: ccu6.h:2920
tle_variants.h
Device specific memory layout defines.
CCU6_CMPSTAT_CC63ST_Msk
#define CCU6_CMPSTAT_CC63ST_Msk
Definition: tle986x.h:6982
CCU6_T12_PM_Int_Sts
INLINE uint8 CCU6_T12_PM_Int_Sts(void)
reads Timer T12 Period-Match Flag Status.
Definition: ccu6.h:3560
CCU6_Ch2c_Passive_Level_Low_Set
INLINE void CCU6_Ch2c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT62.
Definition: ccu6.h:2832
CCU6_Trap_Pin_En
INLINE void CCU6_Trap_Pin_En(void)
enables the trap functionality based on the input pin CTRAP.
Definition: ccu6.h:2557
CCU6_Node2
Definition: ccu6.h:396
CCU6_IS_WHE_Msk
#define CCU6_IS_WHE_Msk
Definition: tle986x.h:7079
TCCU6_PWMMode
TCCU6_PWMMode
This enum lists the CCU6 modulation modes for T12.
Definition: ccu6.h:405
CCU6_Hall_Correct_Int_Node_Sel
INLINE void CCU6_Hall_Correct_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for CHE Interrupts.
Definition: ccu6.h:4284
CCU6_Clk_Div_16
Definition: ccu6.h:313
CCU6_IEN_ENCC61F_Pos
#define CCU6_IEN_ENCC61F_Pos
Definition: tle986x.h:7012
CCU6_IEN_ENCC61F_Msk
#define CCU6_IEN_ENCC61F_Msk
Definition: tle986x.h:7013
CCU6_WriteMultichannelPatterns
INLINE void CCU6_WriteMultichannelPatterns(uint16 Patterns)
Writes Hall and/or PWM patterns for Multi-Channel Mode to shadow register.
Definition: ccu6.h:5649
CCU6_TCTR0_T13R_Msk
#define CCU6_TCTR0_T13R_Msk
Definition: tle986x.h:7277
CCU6_T13_Modulation_En
INLINE void CCU6_T13_Modulation_En(uint16 ccu6_mask)
enables Timer T13 Modulation Configuration
Definition: ccu6.h:2334
CCU6_IS_ICC60R_Msk
#define CCU6_IS_ICC60R_Msk
Definition: tle986x.h:7053
CCU6_IS_ICC60F_Msk
#define CCU6_IS_ICC60F_Msk
Definition: tle986x.h:7059
CCU6_Ch0_Deadtime_Sts
INLINE uint8 CCU6_Ch0_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 0 Deadtime Status.
Definition: ccu6.h:1366
CCU6_T13HR_D_A
Definition: ccu6.h:285
CCU6_Hall_Synchronizaion_Sel
INLINE void CCU6_Hall_Synchronizaion_Sel(uint16 hsync)
selects Hall Synchronization.
Definition: ccu6.h:942
TCCU6_T13_Cnt_Input
TCCU6_T13_Cnt_Input
This enum lists the CCU6 ISCNT13 Inputs.
Definition: ccu6.h:263
CCU6_T13ED_No_Action
Definition: ccu6.h:339
uint8
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
CCU6_Deadtime_Set
INLINE void CCU6_Deadtime_Set(uint16 dtm)
sets CCU6 Timer T12 Deadtime.
Definition: ccu6.h:1242
CCU6_T13_Inv_Mod_Dis
INLINE void CCU6_T13_Inv_Mod_Dis(void)
disables T13 inversion for further modulation.
Definition: ccu6.h:1778
CCU6_T13_PM_Int_Clr
INLINE void CCU6_T13_PM_Int_Clr(void)
clears Interrupt for T13 Period-Match Flag.
Definition: ccu6.h:4504
CCU6_MCM_Switch_T13_PM_Set
INLINE void CCU6_MCM_Switch_T13_PM_Set(void)
sets T13 period-match Switching Mode.
Definition: ccu6.h:3164
CCU6_IS_T12PM_Msk
#define CCU6_IS_T12PM_Msk
Definition: tle986x.h:7067
CCU6_T12_Modulation_En
INLINE void CCU6_T12_Modulation_En(uint16 ccu6_mask)
enables Timer T12 Modulation Configuration
Definition: ccu6.h:2296
CCU6_TRAP_Int_Dis
INLINE void CCU6_TRAP_Int_Dis(void)
disables Interrupt for Trap Flag.
Definition: ccu6.h:5087
CCU6_T12_T12CV_Pos
#define CCU6_T12_T12CV_Pos
Definition: tle986x.h:7222
CCU6_T12_Stop
INLINE void CCU6_T12_Stop(void)
stops CCU6 T12.
Definition: ccu6.h:426
CCU6_MCMCTR_SWSYN_Pos
#define CCU6_MCMCTR_SWSYN_Pos
Definition: tle986x.h:7151
CCU6_MCM_PWM_Pattern_Sts
INLINE uint8 CCU6_MCM_PWM_Pattern_Sts(void)
reads Multi-Channel PWM Pattern.
Definition: ccu6.h:3030
CCU6_T13RSEL_Dis
Definition: ccu6.h:361
CCU6_Multi_Ch_Mode_En
INLINE void CCU6_Multi_Ch_Mode_En(void)
enables Multi-Channel Mode
Definition: ccu6.h:2370
CCU6_T12DTC_DTE1_Pos
#define CCU6_T12DTC_DTE1_Pos
Definition: tle986x.h:7229
CCU6_CMPSTAT_COUT63PS_Msk
#define CCU6_CMPSTAT_COUT63PS_Msk
Definition: tle986x.h:7002
CCU6_ISS_ST13CM_Msk
#define CCU6_ISS_ST13CM_Msk
Definition: tle986x.h:7133
CCU6_T13RSEL_T13HR_Fall
Definition: ccu6.h:363
CCU6_T12PR_T12PV_Msk
#define CCU6_T12PR_T12PV_Msk
Definition: tle986x.h:7252
CCU6_T12DTC_DTM_Msk
#define CCU6_T12DTC_DTM_Msk
Definition: tle986x.h:7226
CCU6_T12_OM
Definition: ccu6.h:299
CCU6_INP_INPCC60_Pos
#define CCU6_INP_INPCC60_Pos
Definition: tle986x.h:7037
CCU6_Ch2t_Passive_Level_High_Set
INLINE void CCU6_Ch2t_Passive_Level_High_Set(void)
sets Passive High Level of CC62.
Definition: ccu6.h:2781
CCU6_ISS_SCC62R_Msk
#define CCU6_ISS_SCC62R_Msk
Definition: tle986x.h:7125
CCU6_ISS_SIDLE_Msk
#define CCU6_ISS_SIDLE_Msk
Definition: tle986x.h:7145
CCU6_T12_CM_CC61_Int_Fall_Set
INLINE void CCU6_T12_CM_CC61_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 1.
Definition: ccu6.h:3865
TCCU6_Clk_Prescaler
TCCU6_Clk_Prescaler
This enum lists the CCU6 T12/T13 Clock Prescaler divider.
Definition: ccu6.h:307
CCU6_CCPOS1_Input_Sel
INLINE void CCU6_CCPOS1_Input_Sel(uint16 ispos1)
selects Input for CCPOS1.
Definition: ccu6.h:748
CCU6_INP_INPT13_Pos
#define CCU6_INP_INPT13_Pos
Definition: tle986x.h:7049
CCU6_IS_ICC61R_Msk
#define CCU6_IS_ICC61R_Msk
Definition: tle986x.h:7055
CCU6_ISR_RT12PM_Msk
#define CCU6_ISR_RT12PM_Msk
Definition: tle986x.h:7100
CCU6_Clk_Div_128
Definition: ccu6.h:316
CCU6_MCMOUTS_CURHS_Pos
#define CCU6_MCMOUTS_CURHS_Pos
Definition: tle986x.h:7175
CCU6_MODCTR_T12MODEN_Pos
#define CCU6_MODCTR_T12MODEN_Pos
Definition: tle986x.h:7180
CCU6_CCPOS2_2_P12
Definition: ccu6.h:223
CCU6_T12_Count_Dir_Sts
INLINE uint8 CCU6_T12_Count_Dir_Sts(void)
reads Count Direction of Timer T12 Bit.
Definition: ccu6.h:2123
CCU6_ISS_SSTR_Msk
#define CCU6_ISS_SSTR_Msk
Definition: tle986x.h:7147
CCU6_MCM_Str_Int_Set
INLINE void CCU6_MCM_Str_Int_Set(void)
sets Multi-Channel Mode Shadow Transfer Interrupt flag.
Definition: ccu6.h:4109
CCU6_T13_Str_Sts
INLINE uint8 CCU6_T13_Str_Sts(void)
reads Timer T13 Shadow Transfer Enable Bit.
Definition: ccu6.h:2167
uint32
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
CCU6_T13_Count_Value_Set
INLINE void CCU6_T13_Count_Value_Set(uint16 t13cv)
sets Timer T13 Counter Value.
Definition: ccu6.h:1450
CCU6_Trap_T13_Dis
INLINE void CCU6_Trap_T13_Dis(void)
disables The trap functionality for T13.
Definition: ccu6.h:2540
CCU6_TCTR0_STE12_Pos
#define CCU6_TCTR0_STE12_Pos
Definition: tle986x.h:7266
CCU6_MCMCTR_STE12U_Pos
#define CCU6_MCMCTR_STE12U_Pos
Definition: tle986x.h:7153
CCU6_TCTR4_T13RES_Msk
#define CCU6_TCTR4_T13RES_Msk
Definition: tle986x.h:7313
CCU6_MCM_Str_T12_Down_Cnt_Dis
INLINE void CCU6_MCM_Str_T12_Down_Cnt_Dis(void)
disables Shadow Transfer for T12 Downcounting.
Definition: ccu6.h:3334
TCCU6_T13TEC
TCCU6_T13TEC
This enum lists the CCU6 T13 Trigger Event Control.
Definition: ccu6.h:322
CCU6_TCTR2_T12SSC_Msk
#define CCU6_TCTR2_T12SSC_Msk
Definition: tle986x.h:7282
CCU6_Node1
Definition: ccu6.h:395
CCU6_Ch3_CompState_Set
INLINE void CCU6_Ch3_CompState_Set(void)
sets Capture/Compare Status Modification Bit 3 for (CC63ST) by Software.
Definition: ccu6.h:1847
CCU6_PSLR_PSL63_Pos
#define CCU6_PSLR_PSL63_Pos
Definition: tle986x.h:7219
CCU6_INP_INPERR_Msk
#define CCU6_INP_INPERR_Msk
Definition: tle986x.h:7046
CCU6_T12_Clk_Sel
INLINE void CCU6_T12_Clk_Sel(uint16 t12clk)
selects Timer T12 Input Clock.
Definition: ccu6.h:1969
CCU6_IEN_ENT13CM_Msk
#define CCU6_IEN_ENT13CM_Msk
Definition: tle986x.h:7023
CCU6_CMPMODIF_MCC62R_Msk
#define CCU6_CMPMODIF_MCC62R_Msk
Definition: tle986x.h:6971
CCU6_ISR_RT13PM_Msk
#define CCU6_ISR_RT13PM_Msk
Definition: tle986x.h:7104
CCU6_T13_Compare_Out_Dis
INLINE void CCU6_T13_Compare_Out_Dis(void)
disables Compare Timer T13 Output
Definition: ccu6.h:2421
CCU6_PISEL0_ISPOS0_Msk
#define CCU6_PISEL0_ISPOS0_Msk
Definition: tle986x.h:7198
CCU6_MCMOUTS_STRHP_Msk
#define CCU6_MCMOUTS_STRHP_Msk
Definition: tle986x.h:7178
CCU6_TCTR4_T13CNT_Pos
#define CCU6_TCTR4_T13CNT_Pos
Definition: tle986x.h:7314
CCU6_T12_PM
Definition: ccu6.h:298
CCU6_T12DTC_DTE2_Pos
#define CCU6_T12DTC_DTE2_Pos
Definition: tle986x.h:7231
CCU6_PISEL0_ISCC61_Msk
#define CCU6_PISEL0_ISCC61_Msk
Definition: tle986x.h:7192
CCU6_T13TEC_T12_PM
Definition: ccu6.h:329
CCU6_T12_Ext_Run_Sel
INLINE void CCU6_T12_Ext_Run_Sel(uint16 t12rsel)
selects Timer T12 External Run.
Definition: ccu6.h:2258
CCU6_ISS_SCHE_Pos
#define CCU6_ISS_SCHE_Pos
Definition: tle986x.h:7140
CCU6_T12_ActiveLeftAligned
Definition: ccu6.h:407
CCU6_CMPSTAT_CCPOS1_Pos
#define CCU6_CMPSTAT_CCPOS1_Pos
Definition: tle986x.h:6985
CCU6_MCM_Idle_Int_Sts
INLINE uint8 CCU6_MCM_Idle_Int_Sts(void)
reads IDLE Status.
Definition: ccu6.h:3726
CCU6_TCTR0_STE13_Msk
#define CCU6_TCTR0_STE13_Msk
Definition: tle986x.h:7279
TCCU6_Ch0_Input
TCCU6_Ch0_Input
This enum lists the CCU6 channel 0 Inputs.
Definition: ccu6.h:157
CCU6_T12_Edge_Aligned_Mode_En
INLINE void CCU6_T12_Edge_Aligned_Mode_En(void)
enables T12 Operating Edge-aligned Mode.
Definition: ccu6.h:1932
CCU6_CMPMODIF_MCC62R_Pos
#define CCU6_CMPMODIF_MCC62R_Pos
Definition: tle986x.h:6970
CCU6_CMPSTAT_CCPOS1_Msk
#define CCU6_CMPSTAT_CCPOS1_Msk
Definition: tle986x.h:6986
CCU6_T13TEC_T12_CM_Ch0
Definition: ccu6.h:325
CCU6_Trap_Channel_En
INLINE void CCU6_Trap_Channel_En(uint16 ccu6_mask)
enables the trap functionality of a corresponding output.
Definition: ccu6.h:2593
CCU6
#define CCU6
Definition: tle986x.h:5994
CCU6_ISS_SCC61R_Pos
#define CCU6_ISS_SCC61R_Pos
Definition: tle986x.h:7120
CCU6_TCTR4_T13RES_Pos
#define CCU6_TCTR4_T13RES_Pos
Definition: tle986x.h:7312
CCU6_Ch0_Deadtime_Dis
INLINE void CCU6_Ch0_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 0 Deadtime.
Definition: ccu6.h:1310
CCU6_Ch1t_Passive_Level_High_Set
INLINE void CCU6_Ch1t_Passive_Level_High_Set(void)
sets Passive High Level of CC61.
Definition: ccu6.h:2713
CCU6_IS_T13CM_Pos
#define CCU6_IS_T13CM_Pos
Definition: tle986x.h:7068
CCU6_SetT13Trigger
INLINE void CCU6_SetT13Trigger(uint16 Mask)
Sets trigger event for the T13 timer.
Definition: ccu6.h:5524
CCU6_T13HR_Input_Sel
INLINE void CCU6_T13HR_Input_Sel(uint16 ist13hr)
selects Input for T13HR.
Definition: ccu6.h:807
CCU6_T12_PM_Int_Dis
INLINE void CCU6_T12_PM_Int_Dis(void)
disables Interrupt for T12 Period-Match.
Definition: ccu6.h:4952
TCCU6_HSYNC
TCCU6_HSYNC
This enum lists the CCU6 Hall Synch Configuration.
Definition: ccu6.h:292
CCU6_Deadtime_Get
INLINE uint8 CCU6_Deadtime_Get(void)
reads CCU6 Timer T12 Deadtime.
Definition: ccu6.h:1223
CCU6_T12HR_D_A
Definition: ccu6.h:276
CCU6_MCM_Expected_Hall_Shadow_Reg_Load
INLINE void CCU6_MCM_Expected_Hall_Shadow_Reg_Load(uint16 mcm_mask_ccpos)
sets Expected Hall Pattern Shadow of CCPOSx.
Definition: ccu6.h:2956
CCU6_INP_INPCC62_Pos
#define CCU6_INP_INPCC62_Pos
Definition: tle986x.h:7041
CCU6_IS_T13CM_Msk
#define CCU6_IS_T13CM_Msk
Definition: tle986x.h:7069
CCU6_CC60_0_P04
Definition: ccu6.h:159
CCU6_Ch1_Value_Set
INLINE void CCU6_Ch1_Value_Set(uint16 cc61sr)
sets Channel 1 Capture/Compare Value.
Definition: ccu6.h:1162
CCU6_MCM_Expected_Hall_Sts
INLINE uint8 CCU6_MCM_Expected_Hall_Sts(void)
reads Expected Hall Pattern of CCPOSx.
Definition: ccu6.h:3073
CCU6_TCTR0_T12CLK_Pos
#define CCU6_TCTR0_T12CLK_Pos
Definition: tle986x.h:7260
CCU6_IS_ICC62R_Msk
#define CCU6_IS_ICC62R_Msk
Definition: tle986x.h:7057
CCU6_IS_ICC62F_Msk
#define CCU6_IS_ICC62F_Msk
Definition: tle986x.h:7063
CCU6_IEN_ENCC61R_Pos
#define CCU6_IEN_ENCC61R_Pos
Definition: tle986x.h:7010
CCU6_Ch2t_Passive_Level_Low_Set
INLINE void CCU6_Ch2t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC62.
Definition: ccu6.h:2798
CCU6_PISEL0_ISCC62_Msk
#define CCU6_PISEL0_ISCC62_Msk
Definition: tle986x.h:7194
CCU6_ISR_RT12PM_Pos
#define CCU6_ISR_RT12PM_Pos
Definition: tle986x.h:7099
CCU6_Ch1_Int_Node_Sel
INLINE void CCU6_Ch1_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 1 Interrupts.
Definition: ccu6.h:4159
CCU6_T12_Str_Dis
INLINE void CCU6_T12_Str_Dis(void)
disables T12 Shadow Transfer.
Definition: ccu6.h:530
CCU6_IS_TRPS_Msk
#define CCU6_IS_TRPS_Msk
Definition: tle986x.h:7075
CCU6_ReadMultichannelPatterns
INLINE uint16 CCU6_ReadMultichannelPatterns(void)
Reads actual Hall and PWM patterns for Multi-Channel Mode.
Definition: ccu6.h:5630
CCU6_SWSEL_T12_PM
Definition: ccu6.h:386
CCU6_T12_Str_En
INLINE void CCU6_T12_Str_En(void)
enables T12 Shadow Transfer.
Definition: ccu6.h:513
TCCU6_Node_Sel
TCCU6_Node_Sel
This enum lists the CCU6 Interrupt Node Select.
Definition: ccu6.h:392
CCU6_T12_Period_Value_Set
INLINE void CCU6_T12_Period_Value_Set(uint16 t12pr)
sets Timer T12 Period Value.
Definition: ccu6.h:1082
CCU6_LoadShadowRegister_CC63
INLINE void CCU6_LoadShadowRegister_CC63(uint16 tick)
Load Channel 3 compare value to the shadow register.
Definition: ccu6.h:5437
CCU6_IEN_ENT12PM_Msk
#define CCU6_IEN_ENT12PM_Msk
Definition: tle986x.h:7021
CCU6_T12_CM_CC60_Int_Rise_Set
INLINE void CCU6_T12_CM_CC60_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 0.
Definition: ccu6.h:3773
CCU6_CMPSTAT_T13IM_Pos
#define CCU6_CMPSTAT_T13IM_Pos
Definition: tle986x.h:7003
CCU6_MCM_Current_Hall_Shadow_Reg_Load
INLINE void CCU6_MCM_Current_Hall_Shadow_Reg_Load(uint16 mcm_mask_ccpos)
sets Current Hall Pattern Shadow of CCPOSx.
Definition: ccu6.h:2975
CCU6_ISS_SWHC_Msk
#define CCU6_ISS_SWHC_Msk
Definition: tle986x.h:7139
CCU6_Trap_T13_ZM_Exit_En
INLINE void CCU6_Trap_T13_ZM_Exit_En(void)
enables T13 zero-match Trap Mode
Definition: ccu6.h:2455
CCU6_Hall_Ch2_Sts
INLINE uint8 CCU6_Hall_Ch2_Sts(void)
reads Sampled Hall Pattern Bit 2.
Definition: ccu6.h:1688
CCU6_CMPSTAT_CC60PS_Pos
#define CCU6_CMPSTAT_CC60PS_Pos
Definition: tle986x.h:6989
CCU6_T12_CM_Ch1_down
Definition: ccu6.h:301
CCU6_INP_INPCC61_Msk
#define CCU6_INP_INPCC61_Msk
Definition: tle986x.h:7040
TCCU6_T12_Cnt_Input
TCCU6_T12_Cnt_Input
This enum lists the CCU6 ISCNT12 Inputs.
Definition: ccu6.h:252
CCU6_MCM_Switch_NoTrigger_Set
INLINE void CCU6_MCM_Switch_NoTrigger_Set(void)
sets No Trigger Switching Mode.
Definition: ccu6.h:3130
CCU6_CH1_CM_R_Int_Clr
INLINE void CCU6_CH1_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 1.
Definition: ccu6.h:4350
CCU6_CC62R_CCV_Msk
#define CCU6_CC62R_CCV_Msk
Definition: tle986x.h:6947
CCU6_ClearIntStatus
INLINE void CCU6_ClearIntStatus(uint16 Mask)
Clears interrupt status bit(s).
Definition: ccu6.h:5725
CCU6_Multi_Ch_Mode_Dis
INLINE void CCU6_Multi_Ch_Mode_Dis(void)
disables Multi-Channel Mode
Definition: ccu6.h:2387
CCU6_TCTR4_DTRES_Pos
#define CCU6_TCTR4_DTRES_Pos
Definition: tle986x.h:7300
CCU6_IEN_ENCHE_Pos
#define CCU6_IEN_ENCHE_Pos
Definition: tle986x.h:7028
CCU6_PISEL2_IST13HR_Msk
#define CCU6_PISEL2_IST13HR_Msk
Definition: tle986x.h:7207
TCCU6_T13HR_Input
TCCU6_T13HR_Input
This enum lists the CCU6 T13HR Inputs.
Definition: ccu6.h:243
CCU6_ISR_RCC61R_Pos
#define CCU6_ISR_RCC61R_Pos
Definition: tle986x.h:7089
CCU6_PISEL0_ISCC60_Pos
#define CCU6_PISEL0_ISCC60_Pos
Definition: tle986x.h:7189
CCU6_STR_Int_En
INLINE void CCU6_STR_Int_En(void)
enables Multi-Channel Mode Shadow Transfer Interrupt.
Definition: ccu6.h:5199
CCU6_Passiv_Level_Ch3_Sel
INLINE void CCU6_Passiv_Level_Ch3_Sel(uint16 lvl)
sets Passive State Level of Output COUT63.
Definition: ccu6.h:2884
CCU6_PISEL0_ISPOS1_Msk
#define CCU6_PISEL0_ISPOS1_Msk
Definition: tle986x.h:7200
CCU6_Trap_T13_En
INLINE void CCU6_Trap_T13_En(void)
enables the trap functionality for T13.
Definition: ccu6.h:2523
CCU6_CH2_CM_R_Int_En
INLINE void CCU6_CH2_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 2.
Definition: ccu6.h:4794
CCU6_Ch0_CompState_Set
INLINE void CCU6_Ch0_CompState_Set(void)
sets Capture/Compare Status Modification Bit 0 for (CC60ST) by Software.
Definition: ccu6.h:1796
TCCU6_Pos0_Input
TCCU6_Pos0_Input
This enum lists the CCU6 ISPOS0 Inputs.
Definition: ccu6.h:192
CCU6_T13PR_T13PV_Pos
#define CCU6_T13PR_T13PV_Pos
Definition: tle986x.h:7257
CCU6_IEN_ENCC62R_Msk
#define CCU6_IEN_ENCC62R_Msk
Definition: tle986x.h:7015
CCU6_CCPOS1_0_P23
Definition: ccu6.h:208
CCU6_T12DTC_DTR1_Msk
#define CCU6_T12DTC_DTR1_Msk
Definition: tle986x.h:7236
CCU6_CMPMODIF_MCC62S_Pos
#define CCU6_CMPMODIF_MCC62S_Pos
Definition: tle986x.h:6962
CCU6_T13_Inv_Mod_En
INLINE void CCU6_T13_Inv_Mod_En(void)
enables T13 inversion for further modulation.
Definition: ccu6.h:1760
CCU6_T12_CM_CC62_Int_Fall_Set
INLINE void CCU6_T12_CM_CC62_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 2.
Definition: ccu6.h:3888
CCU6_TRPCTR_TRPPEN_Msk
#define CCU6_TRPCTR_TRPPEN_Msk
Definition: tle986x.h:7332
CCU6_CMPMODIF_MCC60S_Msk
#define CCU6_CMPMODIF_MCC60S_Msk
Definition: tle986x.h:6959
CCU6_CMPSTAT_CC61ST_Msk
#define CCU6_CMPSTAT_CC61ST_Msk
Definition: tle986x.h:6978
CCU6_Ch2_Int_Node_Sel
INLINE void CCU6_Ch2_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 2 Interrupts.
Definition: ccu6.h:4184
CCU6_T13_Stop
INLINE void CCU6_T13_Stop(void)
stops CCU6 T13.
Definition: ccu6.h:547
TCCU6_T12RSEL
TCCU6_T12RSEL
This enum lists the CCU6 T12 Run Select.
Definition: ccu6.h:348
CCU6_CH2_CM_R_Int_Dis
INLINE void CCU6_CH2_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 2.
Definition: ccu6.h:4817
CCU6_TRPCTR_TRPM1_Msk
#define CCU6_TRPCTR_TRPM1_Msk
Definition: tle986x.h:7324
CCU6_T13_CM_Int_En
INLINE void CCU6_T13_CM_Int_En(void)
enables Interrupt for T13 Compare-Match.
Definition: ccu6.h:4974
CCU6_CC63R_CCV_Pos
#define CCU6_CC63R_CCV_Pos
Definition: tle986x.h:6952
CCU6_ISS_SIDLE_Pos
#define CCU6_ISS_SIDLE_Pos
Definition: tle986x.h:7144
CCU6_Ch1_CompState_Rst
INLINE void CCU6_Ch1_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 1 for CC61ST by Software.
Definition: ccu6.h:1881
CCU6_IEN_ENT13PM_Msk
#define CCU6_IEN_ENT13PM_Msk
Definition: tle986x.h:7025
CCU6_IS_CHE_Msk
#define CCU6_IS_CHE_Msk
Definition: tle986x.h:7077
CCU6_MCMCTR_STE12D_Pos
#define CCU6_MCMCTR_STE12D_Pos
Definition: tle986x.h:7155
CCU6_LoadShadowRegister_CC61
INLINE void CCU6_LoadShadowRegister_CC61(uint16 tick)
Load Channel 1 compare value to the shadow register.
Definition: ccu6.h:5399
CCU6_ISS_STRPF_Msk
#define CCU6_ISS_STRPF_Msk
Definition: tle986x.h:7137
CCU6_T13_Modulation_Dis
INLINE void CCU6_T13_Modulation_Dis(uint16 ccu6_mask)
disables Timer T13 Modulation Configuration
Definition: ccu6.h:2353
CCU6_T12DTC_DTE0_Msk
#define CCU6_T12DTC_DTE0_Msk
Definition: tle986x.h:7228
CCU6_Passive_Level_High_Sel
INLINE void CCU6_Passive_Level_High_Sel(uint16 ccu6_mask)
sets Compare Corresponding Outputs Passive High Level.
Definition: ccu6.h:2865
CCU6_CMPSTAT_CCPOS2_Pos
#define CCU6_CMPSTAT_CCPOS2_Pos
Definition: tle986x.h:6987
CCU6_StopTmr_T13
INLINE void CCU6_StopTmr_T13(void)
Stops CCU6 Timer T13.
Definition: ccu6.h:5327
CCU6_CH0_CM_F_Int_En
INLINE void CCU6_CH0_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 0.
Definition: ccu6.h:4659
CCU6_ISS_SCHE_Msk
#define CCU6_ISS_SCHE_Msk
Definition: tle986x.h:7141
CCU6_TRPCTR_TRPPEN_Pos
#define CCU6_TRPCTR_TRPPEN_Pos
Definition: tle986x.h:7331
CCU6_CH2_CM_F_Int_En
INLINE void CCU6_CH2_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 2.
Definition: ccu6.h:4839
CCU6_MODCTR_T12MODEN_Msk
#define CCU6_MODCTR_T12MODEN_Msk
Definition: tle986x.h:7181
CCU6_PISEL0_ISPOS2_Pos
#define CCU6_PISEL0_ISPOS2_Pos
Definition: tle986x.h:7201
u1_Field_Rd16
INLINE uint8 u1_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 1-bit field of a 16-bit register.
Definition: sfr_access.h:396
tle986x.h
CMSIS register HeaderFile.
CCU6_T13_Prescaler_Dis
INLINE void CCU6_T13_Prescaler_Dis(void)
disables additional prescaler for Timer T13.
Definition: ccu6.h:2057
CCU6_T12_CM_CC62_Int_Fall_Sts
INLINE uint8 CCU6_T12_CM_CC62_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 2.
Definition: ccu6.h:3512
CCU6_CCPOS2_3_P22
Definition: ccu6.h:224
CCU6_MCM_PWM_Str_Req_Sts
INLINE uint8 CCU6_MCM_PWM_Str_Req_Sts(void)
reads Reminder Flag Status.
Definition: ccu6.h:3052
CCU6_CMPMODIF_MCC63S_Msk
#define CCU6_CMPMODIF_MCC63S_Msk
Definition: tle986x.h:6965
CCU6_TRPCTR_TRPM2_Msk
#define CCU6_TRPCTR_TRPM2_Msk
Definition: tle986x.h:7326
CCU6_CH1_CM_R_Int_Dis
INLINE void CCU6_CH1_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 1.
Definition: ccu6.h:4727
CCU6_IS_ICC61R_Pos
#define CCU6_IS_ICC61R_Pos
Definition: tle986x.h:7054
CCU6_T12_Start
INLINE void CCU6_T12_Start(void)
starts CCU6 T12.
Definition: ccu6.h:443
CCU6_T12HR_2_P20
Definition: ccu6.h:237
CCU6_CH1_CM_F_Int_Dis
INLINE void CCU6_CH1_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 1.
Definition: ccu6.h:4772
TCCU6_MCM_SWSEL
TCCU6_MCM_SWSEL
This enum lists the CCU6 Multi Channel Mode Switching Selection.
Definition: ccu6.h:379
CCU6_T12HR_Falling_Edge
Definition: ccu6.h:257
CCU6_SWSEL_Correct_Hall
Definition: ccu6.h:382
TCCU6_Ch1_Input
TCCU6_Ch1_Input
This enum lists the CCU6 channel 1 Inputs.
Definition: ccu6.h:166
CCU6_MCM_Current_Hall_Sts
INLINE uint8 CCU6_MCM_Current_Hall_Sts(void)
reads Current Hall Pattern of CCPOSx.
Definition: ccu6.h:3094
CCU6_TRPCTR_TRPM2_Pos
#define CCU6_TRPCTR_TRPM2_Pos
Definition: tle986x.h:7325
CCU6_IEN_ENCC61R_Msk
#define CCU6_IEN_ENCC61R_Msk
Definition: tle986x.h:7011
CCU6_Ch0t_Passive_Level_High_Set
INLINE void CCU6_Ch0t_Passive_Level_High_Set(void)
sets Passive High Level of CC60.
Definition: ccu6.h:2645
CCU6_ISS_ST12PM_Msk
#define CCU6_ISS_ST12PM_Msk
Definition: tle986x.h:7131
CCU6_STR_Int_Dis
INLINE void CCU6_STR_Int_Dis(void)
disables Multi-Channel Mode Shadow Transfer Interrupt.
Definition: ccu6.h:5222
CCU6_T12RSEL_T12HR_Any
Definition: ccu6.h:353
CCU6_MCM_Switch_Sync_T12_ZM_Sel
INLINE void CCU6_MCM_Switch_Sync_T12_ZM_Sel(void)
sets T12 zero-match Switching Synchronization.
Definition: ccu6.h:3266
CCU6_T12_PM_Int_En
INLINE void CCU6_T12_PM_Int_En(void)
enables Interrupt for T12 Period-Match.
Definition: ccu6.h:4929
CCU6_Multi_Ch_PWM_Shadow_Reg_Load
INLINE void CCU6_Multi_Ch_PWM_Shadow_Reg_Load(uint16 ccu6_mask)
sets Multi-Channel PWM Pattern Shadow.
Definition: ccu6.h:2903
CCU6_CH0_CM_R_Int_Clr
INLINE void CCU6_CH0_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 0.
Definition: ccu6.h:4306
CCU6_T13_Ext_Input_Sel
INLINE void CCU6_T13_Ext_Input_Sel(uint16 t13ext)
selects Input of Extension for T13HR.
Definition: ccu6.h:889
CCU6_PSLR_PSL63_Msk
#define CCU6_PSLR_PSL63_Msk
Definition: tle986x.h:7220
CCU6_Trap_SW_Hall_Int_Set
INLINE void CCU6_Trap_SW_Hall_Int_Set(void)
sets Interrupt for Trap SW Hall Event flag.
Definition: ccu6.h:4020
CCU6_INP_INPT12_Msk
#define CCU6_INP_INPT12_Msk
Definition: tle986x.h:7048
CCU6_Ch3c_Passive_State_Before_Compare_Set
INLINE void CCU6_Ch3c_Passive_State_Before_Compare_Set(void)
sets Passive state for COUT63 Before Compare.
Definition: ccu6.h:1742
CCU6_T12_Period_Value_Get
INLINE uint16 CCU6_T12_Period_Value_Get(void)
reads Timer T12 Period Value.
Definition: ccu6.h:1062
CCU6_IEN_ENCHE_Msk
#define CCU6_IEN_ENCHE_Msk
Definition: tle986x.h:7029
CCU6_SWSEL_T12_Ch1_CM
Definition: ccu6.h:385
CCU6_CC62R_CCV_Pos
#define CCU6_CC62R_CCV_Pos
Definition: tle986x.h:6946
CCU6_TCTR4_T13STD_Msk
#define CCU6_TCTR4_T13STD_Msk
Definition: tle986x.h:7319
CCU6_ISR_RT13PM_Pos
#define CCU6_ISR_RT13PM_Pos
Definition: tle986x.h:7103
CCU6_WHE_Int_Clr
INLINE void CCU6_WHE_Int_Clr(void)
clears Interrupt for Wrong Hall Event flag.
Definition: ccu6.h:4570
CCU6_IS_TRPF_Msk
#define CCU6_IS_TRPF_Msk
Definition: tle986x.h:7073
CCU6_T12_CM_CC61_Int_Fall_Sts
INLINE uint8 CCU6_T12_CM_CC61_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 1.
Definition: ccu6.h:3488
CCU6_PISEL0_ISCC62_Pos
#define CCU6_PISEL0_ISCC62_Pos
Definition: tle986x.h:7193
CCU6_IEN_ENCC60R_Msk
#define CCU6_IEN_ENCC60R_Msk
Definition: tle986x.h:7007
CCU6_PISEL0_ISPOS1_Pos
#define CCU6_PISEL0_ISPOS1_Pos
Definition: tle986x.h:7199
CCU6_T12_Str_Sts
INLINE uint8 CCU6_T12_Str_Sts(void)
reads Timer T12 Shadow Transfer Enable Bit.
Definition: ccu6.h:2101
CCU6_T12MSEL_MSEL61_Msk
#define CCU6_T12MSEL_MSEL61_Msk
Definition: tle986x.h:7243
CCU6_CMPMODIF_MCC60R_Msk
#define CCU6_CMPMODIF_MCC60R_Msk
Definition: tle986x.h:6967
CCU6_TCTR0_CTM_Pos
#define CCU6_TCTR0_CTM_Pos
Definition: tle986x.h:7270
CCU6_IEN_ENCC62F_Pos
#define CCU6_IEN_ENCC62F_Pos
Definition: tle986x.h:7016
CCU6_T12_CM_Ch1_up
Definition: ccu6.h:300
CCU6_CCPOS0x_Any_Edge
Definition: ccu6.h:294
CCU6_ISR_RT13CM_Pos
#define CCU6_ISR_RT13CM_Pos
Definition: tle986x.h:7101
CCU6_PISEL2_ISCNT13_Msk
#define CCU6_PISEL2_ISCNT13_Msk
Definition: tle986x.h:7211
CCU6_TCTR2_T12RSEL_Msk
#define CCU6_TCTR2_T12RSEL_Msk
Definition: tle986x.h:7290
CCU6_ISR_RCC62R_Pos
#define CCU6_ISR_RCC62R_Pos
Definition: tle986x.h:7093
CCU6_MCM_Switch_CorrectHall_Set
INLINE void CCU6_MCM_Switch_CorrectHall_Set(void)
sets Correct Hall Switching Mode.
Definition: ccu6.h:3147
CCU6_TCTR0_T12R_Msk
#define CCU6_TCTR0_T12R_Msk
Definition: tle986x.h:7265
CCU6_INP_INPCC60_Msk
#define CCU6_INP_INPCC60_Msk
Definition: tle986x.h:7038
CCU6_INP_INPCC62_Msk
#define CCU6_INP_INPCC62_Msk
Definition: tle986x.h:7042
CCU6_IS_TRPS_Pos
#define CCU6_IS_TRPS_Pos
Definition: tle986x.h:7074
CCU6_ISS_SCC62R_Pos
#define CCU6_ISS_SCC62R_Pos
Definition: tle986x.h:7124
CCU6_TCTR4_T12CNT_Pos
#define CCU6_TCTR4_T12CNT_Pos
Definition: tle986x.h:7302
CCU6_T13_Prescaler
Definition: ccu6.h:265
CCU6_Ch2_CompState_Rst
INLINE void CCU6_Ch2_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 2 (CC62ST) by Software.
Definition: ccu6.h:1898
CCU6_TCTR4_T13STD_Pos
#define CCU6_TCTR4_T13STD_Pos
Definition: tle986x.h:7318
CCU6_CCPOS0_3_P20
Definition: ccu6.h:196
CCU6_PISEL2_T13EXT_Msk
#define CCU6_PISEL2_T13EXT_Msk
Definition: tle986x.h:7215
TCCU6_T13RSEL
TCCU6_T13RSEL
This enum lists the CCU6 T13 Run Select.
Definition: ccu6.h:359
CCU6_ISS_ST13PM_Pos
#define CCU6_ISS_ST13PM_Pos
Definition: tle986x.h:7134
CCU6_ISR_RTRPF_Pos
#define CCU6_ISR_RTRPF_Pos
Definition: tle986x.h:7105
CCU6_CMPSTAT_CCPOS0_Pos
#define CCU6_CMPSTAT_CCPOS0_Pos
Definition: tle986x.h:6983
CCU6_MCMOUTS_STRMCM_Pos
#define CCU6_MCMOUTS_STRMCM_Pos
Definition: tle986x.h:7171
CCU6_CHE_Int_Dis
INLINE void CCU6_CHE_Int_Dis(void)
disables Interrupt for Correct Hall Event.
Definition: ccu6.h:5132
CCU6_CMPSTAT_CC60ST_Pos
#define CCU6_CMPSTAT_CC60ST_Pos
Definition: tle986x.h:6975
CCU6_Ch3_Value_Set
INLINE void CCU6_Ch3_Value_Set(uint16 cc63sr)
sets Channel CC63 Compare Value.
Definition: ccu6.h:1530
TCCU6_T12_Ext_Input
TCCU6_T12_Ext_Input
This enum lists the CCU6 T12EXT Inputs.
Definition: ccu6.h:274
CCU6_IEN_ENSTR_Msk
#define CCU6_IEN_ENSTR_Msk
Definition: tle986x.h:7035
CCU6_IS_T12PM_Pos
#define CCU6_IS_T12PM_Pos
Definition: tle986x.h:7066
CCU6_IEN_ENT12PM_Pos
#define CCU6_IEN_ENT12PM_Pos
Definition: tle986x.h:7020
CCU6_TCTR2_T13RSEL_Msk
#define CCU6_TCTR2_T13RSEL_Msk
Definition: tle986x.h:7292
CCU6_MCM_Str_T13_Up_Cnt_Dis
INLINE void CCU6_MCM_Str_T13_Up_Cnt_Dis(void)
disables Shadow Transfer for T13 Upcounting.
Definition: ccu6.h:3368
CCU6_T13_Prescaler_En
INLINE void CCU6_T13_Prescaler_En(void)
enables additional prescaler for Timer T13.
Definition: ccu6.h:2040
CCU6_MCMOUTS_CURHS_Msk
#define CCU6_MCMOUTS_CURHS_Msk
Definition: tle986x.h:7176
CCU6_PISEL2_T12EXT_Pos
#define CCU6_PISEL2_T12EXT_Pos
Definition: tle986x.h:7212
CCU6_MODCTR_ECT13O_Pos
#define CCU6_MODCTR_ECT13O_Pos
Definition: tle986x.h:7186
CCU6_WHE_Int_Dis
INLINE void CCU6_WHE_Int_Dis(void)
disables Interrupt for Wrong Hall Event.
Definition: ccu6.h:5177
CCU6_IS_TRPF_Pos
#define CCU6_IS_TRPF_Pos
Definition: tle986x.h:7072
CCU6_PISEL2_ISCNT12_Pos
#define CCU6_PISEL2_ISCNT12_Pos
Definition: tle986x.h:7208
CCU6_MCMOUTS_MCMPS_Pos
#define CCU6_MCMOUTS_MCMPS_Pos
Definition: tle986x.h:7169
CCU6_T13_Int_Node_Sel
INLINE void CCU6_T13_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Timer T13 Interrupts.
Definition: ccu6.h:4259
CCU6_T13HR_Falling_Edge
Definition: ccu6.h:268
CCU6_MODCTR_MCMEN_Msk
#define CCU6_MODCTR_MCMEN_Msk
Definition: tle986x.h:7183
CCU6_T13_Clk_Sel
INLINE void CCU6_T13_Clk_Sel(uint16 t13clk)
selects Timer T13 Input Clock.
Definition: ccu6.h:1989
CCU6_MCMCTR_STE12D_Msk
#define CCU6_MCMCTR_STE12D_Msk
Definition: tle986x.h:7156
CCU6_IS_IDLE_Msk
#define CCU6_IS_IDLE_Msk
Definition: tle986x.h:7081
CCU6_Ch2_Value_Get
INLINE uint16 CCU6_Ch2_Value_Get(void)
reads Channel 2 Capture/Compare Value.
Definition: ccu6.h:1183
CCU6_IEN_ENWHE_Pos
#define CCU6_IEN_ENWHE_Pos
Definition: tle986x.h:7030
CCU6_ISS_SWHE_Msk
#define CCU6_ISS_SWHE_Msk
Definition: tle986x.h:7143
CCU6_ConfigureGlobalModulation
INLINE void CCU6_ConfigureGlobalModulation(uint16 Mode)
Sets global modulation control register.
Definition: ccu6.h:5687
Field_Wrt16
INLINE void Field_Wrt16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:336
CCU6_T13_CM
Definition: ccu6.h:295
CCU6_ISR_RCC60R_Pos
#define CCU6_ISR_RCC60R_Pos
Definition: tle986x.h:7085
CCU6_T12MSEL_MSEL60_Pos
#define CCU6_T12MSEL_MSEL60_Pos
Definition: tle986x.h:7240
CCU6_IEN_ENCC60F_Msk
#define CCU6_IEN_ENCC60F_Msk
Definition: tle986x.h:7009
CCU6_IEN_ENTRPF_Pos
#define CCU6_IEN_ENTRPF_Pos
Definition: tle986x.h:7026
CCU6_CH0_CM_F_Int_Dis
INLINE void CCU6_CH0_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 0.
Definition: ccu6.h:4682
CCU6_IS_STR_Msk
#define CCU6_IS_STR_Msk
Definition: tle986x.h:7083
CCU6_ConfigureMultichannelModulation
INLINE void CCU6_ConfigureMultichannelModulation(uint16 Mode)
Sets Multi-Channel Mode control register.
Definition: ccu6.h:5668
CCU6_Clk_Div_4
Definition: ccu6.h:311
CCU6_ISS_SCC60F_Pos
#define CCU6_ISS_SCC60F_Pos
Definition: tle986x.h:7118
CCU6_Clk_Div_8
Definition: ccu6.h:312
CCU6_IS_ICC60R_Pos
#define CCU6_IS_ICC60R_Pos
Definition: tle986x.h:7052
CCU6_TCTR4_T13RS_Msk
#define CCU6_TCTR4_T13RS_Msk
Definition: tle986x.h:7311
CCU6_CH0_CM_R_Int_En
INLINE void CCU6_CH0_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 0.
Definition: ccu6.h:4614
CCU6_Error_Int_Node_Sel
INLINE void CCU6_Error_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Error Interrupts.
Definition: ccu6.h:4209
CCU6_T12_Modulation_Dis
INLINE void CCU6_T12_Modulation_Dis(uint16 ccu6_mask)
disables Timer T12 Modulation Configuration
Definition: ccu6.h:2315
CCU6_T13_CM_Int_Clr
INLINE void CCU6_T13_CM_Int_Clr(void)
clears Interrupt for T13 Compare-Match Flag.
Definition: ccu6.h:4482
CCU6_MODCTR_T13MODEN_Pos
#define CCU6_MODCTR_T13MODEN_Pos
Definition: tle986x.h:7184
CCU6_TCTR4_T13STR_Msk
#define CCU6_TCTR4_T13STR_Msk
Definition: tle986x.h:7317
CCU6_CC61_0_P10
Definition: ccu6.h:168
CCU6_TCTR4_DTRES_Msk
#define CCU6_TCTR4_DTRES_Msk
Definition: tle986x.h:7301
CCU6_TRPCTR_TRPM0_Pos
#define CCU6_TRPCTR_TRPM0_Pos
Definition: tle986x.h:7321
CCU6_Ch1_Deadtime_Sts
INLINE uint8 CCU6_Ch1_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 1 Deadtime Status.
Definition: ccu6.h:1388
CCU6_Hall_Wrong_Int_Sts
INLINE uint8 CCU6_Hall_Wrong_Int_Sts(void)
reads Wrong Hall Event Status.
Definition: ccu6.h:3704
CCU6_Ch2_CapCom_Mode_Sel
INLINE void CCU6_Ch2_CapCom_Mode_Sel(uint16 msel62)
selects CCU6 T12 CH2 Capture/Compare Mode.
Definition: ccu6.h:961
CCU6_ReadHallReg
INLINE uint32 CCU6_ReadHallReg(void)
Reads sampled Hall pattern from CCU6 CMPSTAT register.
Definition: ccu6.h:5609
CCU6_Ch1_CompState_Sts
INLINE uint8 CCU6_Ch1_CompState_Sts(void)
reads CC61 Capture/Compare State.
Definition: ccu6.h:1576
CCU6_TCTR0_T13PRE_Msk
#define CCU6_TCTR0_T13PRE_Msk
Definition: tle986x.h:7275
CCU6_Ch1_CompState_Set
INLINE void CCU6_Ch1_CompState_Set(void)
sets Capture/Compare Status Modification Bit 1 for (CC61ST) by Software.
Definition: ccu6.h:1813
CCU6_MCM_Str_T12_Up_Cnt_En
INLINE void CCU6_MCM_Str_T12_Up_Cnt_En(void)
enables Shadow Transfer for T12 Upcounting.
Definition: ccu6.h:3283
CCU6_ISR_RCC60F_Pos
#define CCU6_ISR_RCC60F_Pos
Definition: tle986x.h:7087
CCU6_TCTR0_CDIR_Pos
#define CCU6_TCTR0_CDIR_Pos
Definition: tle986x.h:7268
CCU6_MCM_Switch_T12_ON_Set
INLINE void CCU6_MCM_Switch_T12_ON_Set(void)
sets T12 one-match Switching Mode.
Definition: ccu6.h:3181
CCU6_ISS_SCC60R_Pos
#define CCU6_ISS_SCC60R_Pos
Definition: tle986x.h:7116
CCU6_T13_Trig_Event_Sel
INLINE void CCU6_T13_Trig_Event_Sel(uint16 t13tec)
selects Timer T13 Trigger Event Control.
Definition: ccu6.h:2220
CCU6_TCTR4_T12CNT_Msk
#define CCU6_TCTR4_T12CNT_Msk
Definition: tle986x.h:7303
CCU6_T13TEC_T12_CM_Ch2
Definition: ccu6.h:327
CCU6_T12MSEL_DBYP_Msk
#define CCU6_T12MSEL_DBYP_Msk
Definition: tle986x.h:7249
CCU6_TRAP_Int_Clr
INLINE void CCU6_TRAP_Int_Clr(void)
clears Trap Flag.
Definition: ccu6.h:4526
CCU6_PSL63_Low
Definition: ccu6.h:372
CCU6_Ch1_CapCom_Mode_Sel
INLINE void CCU6_Ch1_CapCom_Mode_Sel(uint16 msel61)
selects CCU6 T12 CH1 Capture/Compare Mode.
Definition: ccu6.h:980
TCCU6_Pos1_Input
TCCU6_Pos1_Input
This enum lists the CCU6 ISPOS1 Inputs.
Definition: ccu6.h:206
CCU6_IS_T12OM_Msk
#define CCU6_IS_T12OM_Msk
Definition: tle986x.h:7065
CCU6_TCTR4_T13CNT_Msk
#define CCU6_TCTR4_T13CNT_Msk
Definition: tle986x.h:7315
CCU6_CCPOS2_1_P02
Definition: ccu6.h:222
CCU6_MCMCTR_STE12U_Msk
#define CCU6_MCMCTR_STE12U_Msk
Definition: tle986x.h:7154
CCU6_MCMCTR_SWSEL_Msk
#define CCU6_MCMCTR_SWSEL_Msk
Definition: tle986x.h:7150
CCU6_TCTR0_T13PRE_Pos
#define CCU6_TCTR0_T13PRE_Pos
Definition: tle986x.h:7274
CCU6_T12MSEL_HSYNC_Pos
#define CCU6_T12MSEL_HSYNC_Pos
Definition: tle986x.h:7246
CCU6_SWSEL_No_Action
Definition: ccu6.h:381
CCU6_T12MSEL_DBYP_Pos
#define CCU6_T12MSEL_DBYP_Pos
Definition: tle986x.h:7248
CCU6_T12DTC_DTE0_Pos
#define CCU6_T12DTC_DTE0_Pos
Definition: tle986x.h:7227
CCU6_PISEL2_ISCNT13_Pos
#define CCU6_PISEL2_ISCNT13_Pos
Definition: tle986x.h:7210
CCU6_T12DTC_DTR2_Pos
#define CCU6_T12DTC_DTR2_Pos
Definition: tle986x.h:7237
CCU6_T13ED_T12_UpDown
Definition: ccu6.h:342
CCU6_INP_INPERR_Pos
#define CCU6_INP_INPERR_Pos
Definition: tle986x.h:7045
CCU6_TCTR0_CTM_Msk
#define CCU6_TCTR0_CTM_Msk
Definition: tle986x.h:7271
CCU6_MCMOUT_MCMP_Pos
#define CCU6_MCMOUT_MCMP_Pos
Definition: tle986x.h:7160
TCCU6_T12HR_Input
TCCU6_T12HR_Input
This enum lists the CCU6 T12HR Inputs.
Definition: ccu6.h:234
CCU6_T12_Run_Sts
INLINE uint8 CCU6_T12_Run_Sts(void)
reads Timer T12 Run Bit.
Definition: ccu6.h:2079
CCU6_TCTR0_T13CLK_Pos
#define CCU6_TCTR0_T13CLK_Pos
Definition: tle986x.h:7272
CCU6_PSL63_High
Definition: ccu6.h:373
CCU6_T13TEC_CCPOSx
Definition: ccu6.h:331
CCU6_TCTR0_T12PRE_Msk
#define CCU6_TCTR0_T12PRE_Msk
Definition: tle986x.h:7263
CCU6_T13ED_T12_Up
Definition: ccu6.h:340
CCU6_ISR_RT12OM_Msk
#define CCU6_ISR_RT12OM_Msk
Definition: tle986x.h:7098
CCU6_INP_INPCHE_Msk
#define CCU6_INP_INPCHE_Msk
Definition: tle986x.h:7044
CCU6_IEN_ENSTR_Pos
#define CCU6_IEN_ENSTR_Pos
Definition: tle986x.h:7034
CCU6_Ch2_CompState_Set
INLINE void CCU6_Ch2_CompState_Set(void)
sets Capture/Compare Status Modification Bit 2 for (CC62ST) by Software.
Definition: ccu6.h:1830
CCU6_T12MSEL_MSEL62_Pos
#define CCU6_T12MSEL_MSEL62_Pos
Definition: tle986x.h:7244
CCU6_StopTmr_T12
INLINE void CCU6_StopTmr_T12(void)
Stop CCU6 Timer T12.
Definition: ccu6.h:5310
CCU6_T12HR_Rising_Edge
Definition: ccu6.h:256
TCCU6_Pos2_Input
TCCU6_Pos2_Input
This enum lists the CCU6 ISPOS2 Inputs.
Definition: ccu6.h:220
CCU6_Ch0_CompState_Rst
INLINE void CCU6_Ch0_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 0 for CC60ST by Software.
Definition: ccu6.h:1864
CCU6_T13_Ext_Run_Sel
INLINE void CCU6_T13_Ext_Run_Sel(uint16 t13rsel)
selects Timer T13 External Run.
Definition: ccu6.h:2277
CCU6_CCPOS2_Input_Sel
INLINE void CCU6_CCPOS2_Input_Sel(uint16 ispos2)
selects Input for CCPOS2.
Definition: ccu6.h:767
CCU6_Ch2_Deadtime_En
INLINE void CCU6_Ch2_Deadtime_En(void)
enables CCU6 Timer T12 Channel 2 Deadtime.
Definition: ccu6.h:1293
CCU6_CCPOS1_1_P04
Definition: ccu6.h:209
CCU6_MCM_Str_Int_Sts
INLINE uint8 CCU6_MCM_Str_Int_Sts(void)
reads Multi-Channel Mode Shadow Transfer Request Status.
Definition: ccu6.h:3750
CCU6_SWSEL_T12_OM
Definition: ccu6.h:384
CCU6_ISR_RCC62F_Pos
#define CCU6_ISR_RCC62F_Pos
Definition: tle986x.h:7095
CCU6_TRPCTR_TRPM0_Msk
#define CCU6_TRPCTR_TRPM0_Msk
Definition: tle986x.h:7322
CCU6_PISEL0_ISTRP_Pos
#define CCU6_PISEL0_ISTRP_Pos
Definition: tle986x.h:7195
CCU6_T12_ActiveRightAligned
Definition: ccu6.h:408
CCU6_ISS_SWHE_Pos
#define CCU6_ISS_SWHE_Pos
Definition: tle986x.h:7142
CCU6_TCTR0_CDIR_Msk
#define CCU6_TCTR0_CDIR_Msk
Definition: tle986x.h:7269
CCU6_ISS_STRPF_Pos
#define CCU6_ISS_STRPF_Pos
Definition: tle986x.h:7136
CCU6_ISR_RCC62F_Msk
#define CCU6_ISR_RCC62F_Msk
Definition: tle986x.h:7096
CCU6_T13_PM
Definition: ccu6.h:296
CCU6_CMPMODIF_MCC60S_Pos
#define CCU6_CMPMODIF_MCC60S_Pos
Definition: tle986x.h:6958
CCU6_CHE_Int_En
INLINE void CCU6_CHE_Int_En(void)
enables Interrupt for Correct Hall Event.
Definition: ccu6.h:5109
CCU6_CMPMODIF_MCC63R_Msk
#define CCU6_CMPMODIF_MCC63R_Msk
Definition: tle986x.h:6973
CCU6_T12MSEL_MSEL60_Msk
#define CCU6_T12MSEL_MSEL60_Msk
Definition: tle986x.h:7241
CCU6_IS_IDLE_Pos
#define CCU6_IS_IDLE_Pos
Definition: tle986x.h:7080
CCU6_IS_T12OM_Pos
#define CCU6_IS_T12OM_Pos
Definition: tle986x.h:7064
CCU6_Hall_Correct_Int_Sts
INLINE uint8 CCU6_Hall_Correct_Int_Sts(void)
reads Correct Hall Event Status.
Definition: ccu6.h:3680
CCU6_Init
void CCU6_Init(void)
Initializes the CCU6 module.
CCU6_CMPSTAT_CC60ST_Msk
#define CCU6_CMPSTAT_CC60ST_Msk
Definition: tle986x.h:6976
CCU6_Trap_Pin_Dis
INLINE void CCU6_Trap_Pin_Dis(void)
disables the trap functionality based on the input pin CTRAP.
Definition: ccu6.h:2574
CCU6_T12_Cnt_Input_Sel
INLINE void CCU6_T12_Cnt_Input_Sel(uint16 iscnt12)
selects Input for T12 Counting.
Definition: ccu6.h:828
CCU6_TRPCTR_TRPEN_Pos
#define CCU6_TRPCTR_TRPEN_Pos
Definition: tle986x.h:7327
CCU6_TCTR4_T12STR_Msk
#define CCU6_TCTR4_T12STR_Msk
Definition: tle986x.h:7305
CCU6_IS_ICC61F_Pos
#define CCU6_IS_ICC61F_Pos
Definition: tle986x.h:7060
CCU6_Ch0t_Passive_Level_Low_Set
INLINE void CCU6_Ch0t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC60.
Definition: ccu6.h:2662
CCU6_T12_ActiveCenterAlignedInverted
Definition: ccu6.h:410
CCU6_CMPSTAT_CC62ST_Msk
#define CCU6_CMPSTAT_CC62ST_Msk
Definition: tle986x.h:6980
CCU6_MCMCTR_STE13U_Pos
#define CCU6_MCMCTR_STE13U_Pos
Definition: tle986x.h:7157
CCU6_TCTR2_T13RSEL_Pos
#define CCU6_TCTR2_T13RSEL_Pos
Definition: tle986x.h:7291
CCU6_TCTR4_T13CNT
Definition: ccu6.h:266
CCU6_IS_ICC62F_Pos
#define CCU6_IS_ICC62F_Pos
Definition: tle986x.h:7062
TCCU6_Trap_Input
TCCU6_Trap_Input
This enum lists the CCU6 Trap Inputs.
Definition: ccu6.h:183
CCU6_Ch1_Deadtime_Dis
INLINE void CCU6_Ch1_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 1 Deadtime.
Definition: ccu6.h:1327
CCU6_CMPMODIF_MCC61S_Pos
#define CCU6_CMPMODIF_MCC61S_Pos
Definition: tle986x.h:6960
CCU6_ISR_RWHE_Msk
#define CCU6_ISR_RWHE_Msk
Definition: tle986x.h:7110
CCU6_INP_INPCHE_Pos
#define CCU6_INP_INPCHE_Pos
Definition: tle986x.h:7043
CCU6_T12_Cnt
INLINE void CCU6_T12_Cnt(void)
counts 1 step for CCU6 T12 Event.
Definition: ccu6.h:496
CCU6_IS_ICC62R_Pos
#define CCU6_IS_ICC62R_Pos
Definition: tle986x.h:7056
CCU6_ISS_SCC61F_Msk
#define CCU6_ISS_SCC61F_Msk
Definition: tle986x.h:7123
CCU6_Hall_Delay_Bypass_Dis
INLINE void CCU6_Hall_Delay_Bypass_Dis(void)
disables Hall Delay Bypass.
Definition: ccu6.h:923