TLE986x Device Family SDK
bdrv.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2015, Infineon Technologies AG
5  * All rights reserved.
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20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27  **********************************************************************************************************************/
37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** JO Julia Ott **
44 ** TA Thomas Albersinger **
45 ** AP Adriano Pereira **
46 ** BG Blandine Guillot **
47 *******************************************************************************/
48 
49 /*******************************************************************************
50 ** Revision Control History **
51 ********************************************************************************
52 ** V0.1.0: 2013-02-10, DM: Initial version **
53 ** V0.1.1: 2013-05-24, DM: Bdrv_Diag functions removed **
54 ** Bdrv_Clr_Sts changed, to be robust against **
55 ** unintended flag clearing **
56 ** OpenLoad detection function added **
57 ** V0.2.0: 2013-09-20, DM: Function and settings adapted to B-Step device **
58 ** V0.3.0: 2014-04-25, TA: Bdrv_Init(): use #defines from Config Wizard **
59 ** V0.3.1: 2015-02-10, DM: Individual header file added **
60 ** V0.3.2: 2015-07-15, DM: BEMF register init added **
61 ** V0.3.3: 2015-11-12, DM: Disable interrupts before writing TRIM_DRVx **
62 ** V0.3.4: 2016-07-28, DM: OpenLoad detection for 3-phase motors added **
63 ** V0.3.5: 2016-09-23, DM: OpenLoad detection current set to 1 **
64 ** V0.3.6: 2017-02-16, DM: Bdrv prefix changed to capital letter **
65 ** V0.3.7: 2017-07-25, DM: A nop was added after each status flag clear **
66 ** V0.3.8: 2017-09-26, DM: MISRA 2012 compliance, the following PC-Lint **
67 ** rules are globally deactivated: **
68 ** - Info 793: ANSI/ISO limit of 6 'significant **
69 ** characters in an external identifier **
70 ** - Info 835: A zero has been given as right **
71 ** argument to operator **
72 ** - Info 845: The left argument to operator '&' **
73 ** is certain to be 0 **
74 ** V0.3.9: 2018-02-02, DM: BDRV_Off_Diagnosis() function added **
75 ** V0.4.0: 2018-03-14, DM: BDRV_Clr_Sts() type of parameter changed to **
76 ** (uint32) due to MISRA **
77 ** typedef TBdrv_Sts replaced by #define macros due **
78 ** to MISRA 2012 **
79 ** Replaced macros by INLINE functions **
80 ** Replaced register accesses within functions by **
81 ** function calls **
82 ** V0.4.1: 2018-07-04, AP: Updated BDRV_Set_Bridge(), BDRV_Clr_Sts(), **
83 ** BDRV_Set_Channel() to use API functions (instead **
84 ** of direct access to registers) **
85 ** Fixed BDRV_Set_Int_Channel() to allow interrupt **
86 ** disabling **
87 ** V0.4.2: 2018-07-30, AP: Added functions to get BDRV interrupt status **
88 ** Added BDRV_Set_DSM_Threshold() and **
89 ** BDRV_Set_Discharge_Current() **
90 ** Updated BDRV_Diag_OpenLoad() and **
91 ** BDRV_Off_Diagnosis to use new APIs **
92 ** V0.4.3: 2018-11-27, JO: Doxygen update, moved revision history from **
93 ** bdrv.c to bdrv.h **
94 ** V0.4.4: 2020-02-28, BG: Updated revision history format **
95 *******************************************************************************/
96 
97 #ifndef _BDR_H
98 #define _BDR_H
99 
100 /*******************************************************************************
101 ** Includes **
102 *******************************************************************************/
103 #include "tle_variants.h"
104 #include "sfr_access.h"
105 #include "scu.h"
106 #include "int.h"
107 #include "wdt1.h"
108 
109 /*******************************************************************************
110 ** Global Macro Declarations **
111 *******************************************************************************/
112 
113 /*******************************************************************************
114 ** Global Type Definitions **
115 *******************************************************************************/
119 typedef enum
120 {
121  Ch_Off = 0u,
122  Ch_En = 1u,
123  Ch_PWM = 3u,
124  Ch_On = 5u,
125  Ch_DCS = 9u
126 } TBdrv_Ch_Cfg;
127 
131 typedef enum
132 {
133  LS1 = 0u,
134  LS2 = 1u,
135  HS1 = 2u,
136  HS2 = 3u
137 #if (UC_SERIES == TLE987)
138  ,
139  LS3 = 4u,
140  HS3 = 5u
141 #endif
142 } TBdrv_Ch;
143 
145 #define LS1_DS SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk
146 #define LS2_DS SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk
147 #define HS1_DS SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk
148 #define HS2_DS SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk
149 #define LS1_OC SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk
150 #define LS2_OC SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk
151 #define HS1_OC SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk
152 #define HS2_OC SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk
153 #if (UC_SERIES == TLE987)
154  #define LS3_DS SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk
155  #define HS3_DS SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk
156  #define LS3_OC SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk
157  #define HS3_OC SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk
158 #endif
159 
163 typedef enum
164 {
165  Ch_Ok = 0u,
166  Ch_Short_to_Gnd = 1u,
167  Ch_Short_to_VBat = 2u
169 
173 typedef struct
174 {
175  bool GlobFailSts;
176  TBDRV_Off_Diag_Sts Phase1;
177  TBDRV_Off_Diag_Sts Phase2;
178 #if (UC_SERIES == TLE987)
179  TBDRV_Off_Diag_Sts Phase3;
180 #endif
182 
186 typedef enum
187 {
188  Int_Off = 0U,
189  Int_DS = 1U,
190  Int_OC = 2U,
191  Int_DS_OC = 3U
193 
194 typedef enum
195 {
202  Threshold_1_75_V = 6U,
203  Threshold_2_00_V = 7U
205 
206 typedef enum
207 {
209  Current_Min = 1U,
238  Current_295_90_mA = 30U,
239  Current_304_00_mA = 31U
241 
242 #if (UC_SERIES == TLE987)
243  #define BDRV_ISCLR_OC (LS1_OC | HS1_OC | LS2_OC | HS2_OC | LS3_OC | HS3_OC)
244  #define BDRV_ISCLR_DS (LS1_DS | HS1_DS | LS2_DS | HS2_DS | LS3_DS | HS3_DS)
245 #else
246  #define BDRV_ISCLR_OC (LS1_OC | HS1_OC | LS2_OC | HS2_OC)
247  #define BDRV_ISCLR_DS (LS1_DS | HS1_DS | LS2_DS | HS2_DS)
248 #endif
249 #define BDRV_IRQ_BITS (BDRV_ISCLR_OC | BDRV_ISCLR_DS)
250 #define BDRV_DS_STS_BITS BDRV_ISCLR_DS
251 
252 /*******************************************************************************
253 ** Global Inline Function Definitions **
254 *******************************************************************************/
272 INLINE void BDRV_HS1_OC_Int_Clr(void)
273 {
275 }
276 
294 INLINE void BDRV_LS1_OC_Int_Clr(void)
295 {
297 }
298 
316 INLINE void BDRV_HS2_OC_Int_Clr(void)
317 {
319 }
320 
338 INLINE void BDRV_LS2_OC_Int_Clr(void)
339 {
341 }
342 
343 #if (UC_SERIES == TLE987)
344 
361 INLINE void BDRV_HS3_OC_Int_Clr(void)
362 {
363  Field_Wrt32(&SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Pos, SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk, 1u);
364 }
365 #endif
366 
367 #if (UC_SERIES == TLE987)
368 
385 INLINE void BDRV_LS3_OC_Int_Clr(void)
386 {
387  Field_Wrt32(&SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Pos, SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk, 1u);
388 }
389 #endif
390 
408 INLINE void BDRV_HS1_DS_Int_Clr(void)
409 {
411 }
412 
430 INLINE void BDRV_LS1_DS_Int_Clr(void)
431 {
433 }
434 
452 INLINE void BDRV_HS2_DS_Int_Clr(void)
453 {
455 }
456 
474 INLINE void BDRV_LS2_DS_Int_Clr(void)
475 {
477 }
478 
479 #if (UC_SERIES == TLE987)
480 
497 INLINE void BDRV_HS3_DS_Int_Clr(void)
498 {
499  Field_Wrt32(&SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Pos, SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk, 1u);
500 }
501 #endif
502 
503 #if (UC_SERIES == TLE987)
504 
521 INLINE void BDRV_LS3_DS_Int_Clr(void)
522 {
523  Field_Wrt32(&SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Pos, SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk, 1u);
524 }
525 #endif
526 
544 INLINE void BDRV_VCP_LO_Int_Clr(void)
545 {
547 }
548 
566 INLINE void BDRV_HS1_OC_Int_En(void)
567 {
569 }
570 
589 INLINE void BDRV_HS1_OC_Int_Dis(void)
590 {
592 }
593 
611 INLINE void BDRV_LS1_OC_Int_En(void)
612 {
614 }
615 
634 INLINE void BDRV_LS1_OC_Int_Dis(void)
635 {
637 }
638 
656 INLINE void BDRV_HS2_OC_Int_En(void)
657 {
659 }
660 
679 INLINE void BDRV_HS2_OC_Int_Dis(void)
680 {
682 }
683 
701 INLINE void BDRV_LS2_OC_Int_En(void)
702 {
704 }
705 
724 INLINE void BDRV_LS2_OC_Int_Dis(void)
725 {
727 }
728 
729 #if (UC_SERIES == TLE987)
730 
747 INLINE void BDRV_HS3_OC_Int_En(void)
748 {
749  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk, 1u);
750 }
751 #endif
752 
753 #if (UC_SERIES == TLE987)
754 
772 INLINE void BDRV_HS3_OC_Int_Dis(void)
773 {
774  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk, 0u);
775 }
776 #endif
777 
778 #if (UC_SERIES == TLE987)
779 
796 INLINE void BDRV_LS3_OC_Int_En(void)
797 {
798  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk, 1u);
799 }
800 #endif
801 
802 #if (UC_SERIES == TLE987)
803 
821 INLINE void BDRV_LS3_OC_Int_Dis(void)
822 {
823  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk, 0u);
824 }
825 #endif
826 
844 INLINE void BDRV_HS1_DS_Int_En(void)
845 {
847 }
848 
867 INLINE void BDRV_HS1_DS_Int_Dis(void)
868 {
870 }
871 
889 INLINE void BDRV_LS1_DS_Int_En(void)
890 {
892 }
893 
912 INLINE void BDRV_LS1_DS_Int_Dis(void)
913 {
915 }
916 
934 INLINE void BDRV_HS2_DS_Int_En(void)
935 {
937 }
938 
957 INLINE void BDRV_HS2_DS_Int_Dis(void)
958 {
960 }
961 
979 INLINE void BDRV_LS2_DS_Int_En(void)
980 {
982 }
983 
1002 INLINE void BDRV_LS2_DS_Int_Dis(void)
1003 {
1005 }
1006 
1007 #if (UC_SERIES == TLE987)
1008 
1025 INLINE void BDRV_HS3_DS_Int_En(void)
1026 {
1027  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk, 1u);
1028 }
1029 #endif
1030 
1031 #if (UC_SERIES == TLE987)
1032 
1050 INLINE void BDRV_HS3_DS_Int_Dis(void)
1051 {
1052  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk, 0u);
1053 }
1054 #endif
1055 
1056 #if (UC_SERIES == TLE987)
1057 
1074 INLINE void BDRV_LS3_DS_Int_En(void)
1075 {
1076  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk, 1u);
1077 }
1078 #endif
1079 
1080 #if (UC_SERIES == TLE987)
1081 
1099 INLINE void BDRV_LS3_DS_Int_Dis(void)
1100 {
1101  Field_Mod32(&SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk, 0u);
1102 }
1103 #endif
1104 
1122 INLINE void BDRV_VCP_LO_Int_En(void)
1123 {
1125 }
1126 
1145 INLINE void BDRV_VCP_LO_Int_Dis(void)
1146 {
1148 }
1149 
1155 {
1157 }
1158 
1164 {
1166 }
1167 
1173 {
1175 }
1176 
1182 {
1184 }
1185 
1186 #if (UC_SERIES == TLE987)
1187 
1191 INLINE uint8 BDRV_HS3_OC_Int_Sts(void)
1192 {
1193  return u1_Field_Rd32(&SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_HS3_OC_IS_Pos, SCUPM_BDRV_IS_HS3_OC_IS_Msk);
1194 }
1195 #endif
1196 
1197 #if (UC_SERIES == TLE987)
1198 
1202 INLINE uint8 BDRV_LS3_OC_Int_Sts(void)
1203 {
1204  return u1_Field_Rd32(&SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_LS3_OC_IS_Pos, SCUPM_BDRV_IS_LS3_OC_IS_Msk);
1205 }
1206 #endif
1207 
1213 {
1215 }
1216 
1222 {
1224 }
1225 
1231 {
1233 }
1234 
1240 {
1242 }
1243 
1244 #if (UC_SERIES == TLE987)
1245 
1249 INLINE uint8 BDRV_HS3_DS_Int_Sts(void)
1250 {
1251  return u1_Field_Rd32(&SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_HS3_DS_IS_Pos, SCUPM_BDRV_IS_HS3_DS_IS_Msk);
1252 }
1253 #endif
1254 
1255 #if (UC_SERIES == TLE987)
1256 
1260 INLINE uint8 BDRV_LS3_DS_Int_Sts(void)
1261 {
1262  return u1_Field_Rd32(&SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_LS3_DS_IS_Pos, SCUPM_BDRV_IS_LS3_DS_IS_Msk);
1263 }
1264 #endif
1265 
1271 {
1273 }
1274 
1275 /*******************************************************************************
1276 ** Global Variable Declarations **
1277 *******************************************************************************/
1282 void BDRV_Init(void);
1283 
1284 #if (UC_SERIES == TLE987)
1285 
1306 void BDRV_Set_Bridge(TBdrv_Ch_Cfg LS1_Cfg,
1307  TBdrv_Ch_Cfg HS1_Cfg,
1308  TBdrv_Ch_Cfg LS2_Cfg,
1309  TBdrv_Ch_Cfg HS2_Cfg,
1310  TBdrv_Ch_Cfg LS3_Cfg,
1311  TBdrv_Ch_Cfg HS3_Cfg);
1312 #else
1313 
1331 void BDRV_Set_Bridge(TBdrv_Ch_Cfg LS1_Cfg,
1332  TBdrv_Ch_Cfg HS1_Cfg,
1333  TBdrv_Ch_Cfg LS2_Cfg,
1334  TBdrv_Ch_Cfg HS2_Cfg);
1335 #endif
1336 
1352 void BDRV_Set_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Cfg Ch_Cfg);
1353 
1368 void BDRV_Clr_Sts(uint32 Sts_Bit);
1369 
1385 void BDRV_Set_Int_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Int Ch_Int);
1386 
1408 bool BDRV_Diag_OpenLoad(void);
1409 
1419 
1420 
1427 void BDRV_Set_DSM_Threshold(TBdrv_DSM_Threshold BDRV_Threshold);
1428 
1429 
1436 void BDRV_Set_Discharge_Current(TBdrv_Disch_Curr BDRV_Current);
1437 
1438 #endif
BDRV_HS1_DS_Int_En
INLINE void BDRV_HS1_DS_Int_En(void)
enables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:841
Current_199_60_mA
typ. current 199.60 mA
Definition: bdrv.h:225
Current_119_40_mA
typ. current 119.40 mA
Definition: bdrv.h:217
SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos
Definition: tle986x.h:9300
Current_129_70_mA
typ. current 129.70 mA
Definition: bdrv.h:218
SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos
Definition: tle986x.h:9288
Current_140_30_mA
typ. current 140.30 mA
Definition: bdrv.h:219
Threshold_1_00_V
Threshold 3 for VDS at 1.00 V.
Definition: bdrv.h:197
SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk
Definition: tle986x.h:9377
SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos
Definition: tle986x.h:9294
SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk
Definition: tle986x.h:9371
TBdrv_Ch_Int
TBdrv_Ch_Int
This enum lists the Bridge Driver channel Interrupt configuration.
Definition: bdrv.h:184
BDRV_VCP_LO_Int_Dis
INLINE void BDRV_VCP_LO_Int_Dis(void)
disables Charge Pump Low interrupt.
Definition: bdrv.h:1142
SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos
Definition: tle986x.h:9366
Current_295_90_mA
typ. current 295.90 mA
Definition: bdrv.h:236
BDRV_LS2_OC_Int_Dis
INLINE void BDRV_LS2_OC_Int_Dis(void)
disables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:721
SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos
Definition: tle986x.h:9323
Threshold_0_75_V
Threshold 2 for VDS at 0.75 V.
Definition: bdrv.h:196
Current_189_80_mA
typ. current 189.80 mA
Definition: bdrv.h:224
BDRV_LS2_DS_Int_Clr
INLINE void BDRV_LS2_DS_Int_Clr(void)
clears Low Side Driver 2 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:471
SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos
Definition: tle986x.h:9376
Ch_On
channel enabled and static on
Definition: bdrv.h:122
BDRV_LS2_OC_Int_Sts
INLINE uint8 BDRV_LS2_OC_Int_Sts(void)
Reads the Bridge Driver Low-Side 2 Over-Current Status Flag.
Definition: bdrv.h:1178
BDRV_HS2_OC_Int_Clr
INLINE void BDRV_HS2_OC_Int_Clr(void)
clears External High Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:313
Ch_En
channel enabled
Definition: bdrv.h:120
SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk
Definition: tle986x.h:9287
BDRV_LS2_OC_Int_En
INLINE void BDRV_LS2_OC_Int_En(void)
enables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:698
BDRV_VCP_LO_Int_Clr
INLINE void BDRV_VCP_LO_Int_Clr(void)
clears Charge Pump Low interrupt flag.
Definition: bdrv.h:541
LS2
Phase2 Low Side MOSFET.
Definition: bdrv.h:132
Threshold_1_25_V
Threshold 4 for VDS at 1.25 V.
Definition: bdrv.h:198
Current_86_80_mA
typ. current 86.80 mA
Definition: bdrv.h:214
BDRV_HS1_OC_Int_En
INLINE void BDRV_HS1_OC_Int_En(void)
enables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:563
Current_180_30_mA
typ. current 180.30 mA
Definition: bdrv.h:223
Threshold_1_75_V
Threshold 6 for VDS at 1.75 V.
Definition: bdrv.h:200
SCUPM_BDRV_IS_LS2_DS_IS_Msk
#define SCUPM_BDRV_IS_LS2_DS_IS_Msk
Definition: tle986x.h:9338
sfr_access.h
SFR low level access library.
SCUPM_BDRV_IS_LS1_OC_IS_Pos
#define SCUPM_BDRV_IS_LS1_OC_IS_Pos
Definition: tle986x.h:9331
Current_98_00_mA
typ. current 98.00 mA
Definition: bdrv.h:215
SCUPM
#define SCUPM
Definition: tle986x.h:6005
SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk
Definition: tle986x.h:9365
Current_53_90_mA
typ. current 53.90 mA
Definition: bdrv.h:211
BDRV_VCP_LO_Int_En
INLINE void BDRV_VCP_LO_Int_En(void)
enables Charge Pump Low interrupt.
Definition: bdrv.h:1119
INLINE
#define INLINE
Definition: types.h:134
SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk
Definition: tle986x.h:9324
SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos
Definition: tle986x.h:9302
SCUPM_BDRV_IS_HS1_OC_IS_Msk
#define SCUPM_BDRV_IS_HS1_OC_IS_Msk
Definition: tle986x.h:9328
Field_Mod32
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
Int_Off
all interrupts disable
Definition: bdrv.h:186
u1_Field_Rd32
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:401
Current_150_40_mA
typ. current 150.40 mA
Definition: bdrv.h:220
SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk
Definition: tle986x.h:9369
SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk
Definition: tle986x.h:9367
Int_OC
Over-Current interrupt enable (On-Diagnosis)
Definition: bdrv.h:188
SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk
Definition: tle986x.h:9363
BDRV_HS1_DS_Int_Clr
INLINE void BDRV_HS1_DS_Int_Clr(void)
enables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:405
Ch_DCS
channel enabled with Diag.-Current Source
Definition: bdrv.h:123
Current_108_50_mA
typ. current 108.50 mA
Definition: bdrv.h:216
TBDRV_Off_Diag
This struct lists the Bridge Driver Off Diagnosis Status Phases configuration.
Definition: bdrv.h:171
SCUPM_BDRV_IS_HS2_OC_IS_Msk
#define SCUPM_BDRV_IS_HS2_OC_IS_Msk
Definition: tle986x.h:9326
Ch_Short_to_VBat
Definition: bdrv.h:165
SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos
Definition: tle986x.h:9286
Current_31_10_mA
typ. current 31.10 mA
Definition: bdrv.h:209
wdt1.h
Window Watchdog 1 low level access library.
BDRV_Set_Discharge_Current
void BDRV_Set_Discharge_Current(TBdrv_Disch_Curr BDRV_Current)
Sets the trimming of the internal driver discharge current.
SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos
Definition: tle986x.h:9372
Threshold_2_00_V
Threshold 7 for VDS at 2.00 V.
Definition: bdrv.h:201
SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk
Definition: tle986x.h:9293
Threshold_1_50_V
Threshold 5 for VDS at 1.50 V.
Definition: bdrv.h:199
BDRV_LS1_OC_Int_Sts
INLINE uint8 BDRV_LS1_OC_Int_Sts(void)
Reads the Bridge Driver Low-Side 1 Over-Current Status Flag.
Definition: bdrv.h:1160
SCUPM_BDRV_IS_HS2_OC_IS_Pos
#define SCUPM_BDRV_IS_HS2_OC_IS_Pos
Definition: tle986x.h:9325
tle_variants.h
Device specific memory layout defines.
BDRV_LS1_DS_Int_En
INLINE void BDRV_LS1_DS_Int_En(void)
enables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:886
Current_Min
(min discharge current) lowest gate discharge current
Definition: bdrv.h:207
Current_218_40_mA
typ. current 218.40 mA
Definition: bdrv.h:227
Current_304_00_mA
(max charge current) typ. current 304 mA
Definition: bdrv.h:237
Threshold_0_50_V
Threshold 1 for VDS at 0.50 V.
Definition: bdrv.h:195
SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos
Definition: tle986x.h:9374
SCUPM_BDRV_IS_HS1_DS_IS_Pos
#define SCUPM_BDRV_IS_HS1_DS_IS_Pos
Definition: tle986x.h:9335
SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk
Definition: tle986x.h:9373
SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk
Definition: tle986x.h:9375
uint8
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
Int_DS
Drain-Source interrupt enable (Off-Diagnosis)
Definition: bdrv.h:187
Field_Wrt32
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:341
BDRV_LS1_OC_Int_En
INLINE void BDRV_LS1_OC_Int_En(void)
enables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:608
TBdrv_DSM_Threshold
TBdrv_DSM_Threshold
Definition: bdrv.h:192
BDRV_Init
void BDRV_Init(void)
Initializes the BridgeDriver based on the IFXConfigWizard configuration.
BDRV_HS1_OC_Int_Sts
INLINE uint8 BDRV_HS1_OC_Int_Sts(void)
Reads the Bridge Driver High-Side 1 Over-Current Status Flag.
Definition: bdrv.h:1151
TBdrv_Ch_Cfg
TBdrv_Ch_Cfg
This enum lists the Bridge Driver High Side channel configuration.
Definition: bdrv.h:117
SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos
Definition: tle986x.h:9296
TBdrv_Disch_Curr
TBdrv_Disch_Curr
Definition: bdrv.h:204
BDRV_Clr_Sts
void BDRV_Clr_Sts(uint32 Sts_Bit)
clears individual status flags and interrupt status flags of the BridgeDriver
BDRV_HS2_DS_Int_Clr
INLINE void BDRV_HS2_DS_Int_Clr(void)
clears High Side Driver 2 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:449
uint32
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
Current_160_80_mA
typ. current 160.80 mA
Definition: bdrv.h:221
SCUPM_BDRV_IS_HS1_DS_IS_Msk
#define SCUPM_BDRV_IS_HS1_DS_IS_Msk
Definition: tle986x.h:9336
BDRV_HS2_DS_Int_Sts
INLINE uint8 BDRV_HS2_DS_Int_Sts(void)
Reads the Bridge Driver High-Side 2 Pre-Driver Short Status Flag.
Definition: bdrv.h:1227
Int_DS_OC
Drain-Source and Over-Current interrupt enable.
Definition: bdrv.h:189
Ch_Ok
Definition: bdrv.h:163
Current_170_10_mA
typ. current 170.10 mA
Definition: bdrv.h:222
SCUPM_BDRV_IS_LS2_OC_IS_Msk
#define SCUPM_BDRV_IS_LS2_OC_IS_Msk
Definition: tle986x.h:9330
BDRV_LS1_DS_Int_Clr
INLINE void BDRV_LS1_DS_Int_Clr(void)
clears Low Side Driver 1 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:427
SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk
Definition: tle986x.h:9301
HS2
Phase2 High Side MOSFET.
Definition: bdrv.h:134
SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk
Definition: tle986x.h:9361
BDRV_LS1_DS_Int_Dis
INLINE void BDRV_LS1_DS_Int_Dis(void)
disables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:909
SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk
Definition: tle986x.h:9297
Current_254_30_mA
typ. current 254.30 mA
Definition: bdrv.h:231
BDRV_Diag_OpenLoad
bool BDRV_Diag_OpenLoad(void)
Open Load detection, detects whether a motor is connected.
BDRV_LS1_OC_Int_Dis
INLINE void BDRV_LS1_OC_Int_Dis(void)
disables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:631
BDRV_HS1_OC_Int_Dis
INLINE void BDRV_HS1_OC_Int_Dis(void)
disables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:586
SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos
Definition: tle986x.h:9364
SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos
Definition: tle986x.h:9362
HS1
Phase1 High Side MOSFET.
Definition: bdrv.h:133
SCUPM_BDRV_IS_LS2_DS_IS_Pos
#define SCUPM_BDRV_IS_LS2_DS_IS_Pos
Definition: tle986x.h:9337
BDRV_HS1_DS_Int_Sts
INLINE uint8 BDRV_HS1_DS_Int_Sts(void)
Reads the Bridge Driver High-Side 1 Pre-Driver Short Status Flag.
Definition: bdrv.h:1209
Current_245_30_mA
typ. current 245.30 mA
Definition: bdrv.h:230
TBDRV_Off_Diag_Sts
TBDRV_Off_Diag_Sts
This enum lists the Bridge Driver Off Diagnosis Status configuration.
Definition: bdrv.h:161
BDRV_Set_Int_Channel
void BDRV_Set_Int_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Int Ch_Int)
sets Interrupt Enable for the individual MOSFETs (channels)
BDRV_HS2_DS_Int_Dis
INLINE void BDRV_HS2_DS_Int_Dis(void)
disables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:954
BDRV_LS2_DS_Int_En
INLINE void BDRV_LS2_DS_Int_En(void)
enables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:976
BDRV_HS2_OC_Int_Sts
INLINE uint8 BDRV_HS2_OC_Int_Sts(void)
Reads the Bridge Driver High-Side 2 Over-Current Status Flag.
Definition: bdrv.h:1169
SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos
Definition: tle986x.h:9292
Current_279_60_mA
typ. current 279.60 mA
Definition: bdrv.h:234
BDRV_LS2_DS_Int_Dis
INLINE void BDRV_LS2_DS_Int_Dis(void)
disables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:999
SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos
Definition: tle986x.h:9290
BDRV_HS2_OC_Int_Dis
INLINE void BDRV_HS2_OC_Int_Dis(void)
disables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:676
Current_288_00_mA
typ. current 288.00 mA
Definition: bdrv.h:235
BDRV_HS2_OC_Int_En
INLINE void BDRV_HS2_OC_Int_En(void)
enables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:653
BDRV_Set_Bridge
void BDRV_Set_Bridge(TBdrv_Ch_Cfg LS1_Cfg, TBdrv_Ch_Cfg HS1_Cfg, TBdrv_Ch_Cfg LS2_Cfg, TBdrv_Ch_Cfg HS2_Cfg)
Sets the bridge in the desired state. For each of the four drivers the state can be defined.
SCUPM_BDRV_IS_HS1_OC_IS_Pos
#define SCUPM_BDRV_IS_HS1_OC_IS_Pos
Definition: tle986x.h:9327
BDRV_HS2_DS_Int_En
INLINE void BDRV_HS2_DS_Int_En(void)
enables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:931
SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk
Definition: tle986x.h:9303
LS1
Phase1 Low Side MOSFET.
Definition: bdrv.h:131
scu.h
System Control Unit low level access library.
Current_19_80_mA
typ. current 19.80 mA
Definition: bdrv.h:208
BDRV_Off_Diagnosis
TBDRV_Off_Diag BDRV_Off_Diagnosis(void)
Off-diagnosis.
SCUPM_BDRV_IS_LS1_DS_IS_Msk
#define SCUPM_BDRV_IS_LS1_DS_IS_Msk
Definition: tle986x.h:9340
BDRV_HS1_DS_Int_Dis
INLINE void BDRV_HS1_DS_Int_Dis(void)
disables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:864
Current_42_30_mA
typ. current 42.30 mA
Definition: bdrv.h:210
SCUPM_BDRV_IS_LS1_DS_IS_Pos
#define SCUPM_BDRV_IS_LS1_DS_IS_Pos
Definition: tle986x.h:9339
BDRV_Set_Channel
void BDRV_Set_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Cfg Ch_Cfg)
sets an individual driver of the BridgeDriver in the desired state
SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos
Definition: tle986x.h:9360
TBdrv_Ch
TBdrv_Ch
This enum lists the Bridge Driver channel configuration.
Definition: bdrv.h:129
BDRV_VCP_LO_Int_Sts
INLINE uint8 BDRV_VCP_LO_Int_Sts(void)
Reads the Bridge Driver VCP Lower Threshold 2 Measurement Status Flag.
Definition: bdrv.h:1267
Current_Disabled
(HiZ) Slew Rate Control is inactive
Definition: bdrv.h:206
BDRV_HS1_OC_Int_Clr
INLINE void BDRV_HS1_OC_Int_Clr(void)
clears External High Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:269
SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk
Definition: tle986x.h:9295
SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos
Definition: tle986x.h:9368
Current_227_40_mA
typ. current 227.40 mA
Definition: bdrv.h:228
SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos
Definition: tle986x.h:9370
Current_208_90_mA
typ. current 208.90 mA
Definition: bdrv.h:226
SCUPM_BDRV_IS_LS2_OC_IS_Pos
#define SCUPM_BDRV_IS_LS2_OC_IS_Pos
Definition: tle986x.h:9329
BDRV_LS2_OC_Int_Clr
INLINE void BDRV_LS2_OC_Int_Clr(void)
clears External Low Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:335
Ch_Short_to_Gnd
Definition: bdrv.h:164
Ch_Off
channel disabled
Definition: bdrv.h:119
SCUPM_BDRV_IS_LS1_OC_IS_Msk
#define SCUPM_BDRV_IS_LS1_OC_IS_Msk
Definition: tle986x.h:9332
Threshold_0_25_V
Threshold 0 for VDS at 0.25 V.
Definition: bdrv.h:194
BDRV_LS2_DS_Int_Sts
INLINE uint8 BDRV_LS2_DS_Int_Sts(void)
Reads the Bridge Driver Low-Side 2 Pre-Driver Short Status Flag.
Definition: bdrv.h:1236
Current_236_70_mA
typ. current 236.70 mA
Definition: bdrv.h:229
BDRV_LS1_DS_Int_Sts
INLINE uint8 BDRV_LS1_DS_Int_Sts(void)
Reads the Bridge Driver Low-Side 1 Pre-Driver Short Status Flag.
Definition: bdrv.h:1218
SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk
Definition: tle986x.h:9289
BDRV_LS1_OC_Int_Clr
INLINE void BDRV_LS1_OC_Int_Clr(void)
clears External Low Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:291
Current_64_90_mA
typ. current 64.90 mA
Definition: bdrv.h:212
BDRV_Set_DSM_Threshold
void BDRV_Set_DSM_Threshold(TBdrv_DSM_Threshold BDRV_Threshold)
Sets the Voltage Threshold for Drain-Source Monitoring of external FETs.
int.h
Interrupt low level access library.
Ch_PWM
channel enabled with PWM (CCU6 connection)
Definition: bdrv.h:121
SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk
Definition: tle986x.h:9291
SCUPM_BDRV_IS_HS2_DS_IS_Msk
#define SCUPM_BDRV_IS_HS2_DS_IS_Msk
Definition: tle986x.h:9334
Current_76_20_mA
typ. current 76.20 mA
Definition: bdrv.h:213
SCUPM_BDRV_IS_HS2_DS_IS_Pos
#define SCUPM_BDRV_IS_HS2_DS_IS_Pos
Definition: tle986x.h:9333
SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos
Definition: tle986x.h:9298
SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk
Definition: tle986x.h:9299
Current_262_80_mA
typ. current 262.80 mA
Definition: bdrv.h:232
Current_271_50_mA
typ. current 271.50 mA
Definition: bdrv.h:233