TLE986x Device Family SDK
Data Fields
CCU6_Type Struct Reference

Detailed Description

Capture Compare Unit 6 (CCU6)

#include <tle986x.h>

Data Fields

union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   CCV: 16
 
   }   bit
 
CC63R
 
__IM uint16_t RESERVED
 
union {
   __IOM uint16_t   reg
 
   struct {
      __OM uint16_t   T12RR: 1
 
      __OM uint16_t   T12RS: 1
 
      __OM uint16_t   T12RES: 1
 
      __OM uint16_t   DTRES: 1
 
      __IM   uint16_t: 1
 
      __OM uint16_t   T12CNT: 1
 
      __OM uint16_t   T12STR: 1
 
      __OM uint16_t   T12STD: 1
 
      __OM uint16_t   T13RR: 1
 
      __OM uint16_t   T13RS: 1
 
      __OM uint16_t   T13RES: 1
 
      __OM uint16_t   T13CNT: 1
 
      __OM uint16_t   T13STR: 1
 
      __OM uint16_t   T13STD: 1
 
   }   bit
 
TCTR4
 
__IM uint16_t RESERVED1
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   MCMPS: 6
 
      __IM   uint16_t: 1
 
      __IOM uint16_t   STRMCM: 1
 
      __IOM uint16_t   EXPHS: 3
 
      __IOM uint16_t   CURHS: 3
 
      __IOM uint16_t   STRHP: 1
 
   }   bit
 
MCMOUTS
 
__IM uint16_t RESERVED2
 
union {
   __IOM uint16_t   reg
 
   struct {
      __OM uint16_t   RCC60R: 1
 
      __OM uint16_t   RCC60F: 1
 
      __OM uint16_t   RCC61R: 1
 
      __OM uint16_t   RCC61F: 1
 
      __OM uint16_t   RCC62R: 1
 
      __OM uint16_t   RCC62F: 1
 
      __OM uint16_t   RT12OM: 1
 
      __OM uint16_t   RT12PM: 1
 
      __OM uint16_t   RT13CM: 1
 
      __OM uint16_t   RT13PM: 1
 
      __OM uint16_t   RTRPF: 1
 
      __IM   uint16_t: 1
 
      __OM uint16_t   RCHE: 1
 
      __OM uint16_t   RWHE: 1
 
      __OM uint16_t   RIDLE: 1
 
      __OM uint16_t   RSTR: 1
 
   }   bit
 
ISR
 
__IM uint16_t RESERVED3
 
union {
   __IOM uint16_t   reg
 
   struct {
      __OM uint16_t   MCC60S: 1
 
      __OM uint16_t   MCC61S: 1
 
      __OM uint16_t   MCC62S: 1
 
      __IM   uint16_t: 3
 
      __OM uint16_t   MCC63S: 1
 
      __OM uint16_t   MCC60R: 1
 
      __OM uint16_t   MCC61R: 1
 
      __OM uint16_t   MCC62R: 1
 
      __OM uint16_t   MCC63R: 1
 
   }   bit
 
CMPMODIF
 
__IM uint16_t RESERVED4
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   CCS: 16
 
   }   bit
 
CC60SR
 
__IM uint16_t RESERVED5
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   CCS: 16
 
   }   bit
 
CC61SR
 
__IM uint16_t RESERVED6
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   CCS: 16
 
   }   bit
 
CC62SR
 
__IM uint16_t RESERVED7
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   CCS: 16
 
   }   bit
 
CC63SR
 
__IM uint16_t RESERVED8
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   T12PV: 16
 
   }   bit
 
T12PR
 
__IM uint16_t RESERVED9
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   T13PV: 16
 
   }   bit
 
T13PR
 
__IM uint16_t RESERVED10
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   DTM: 8
 
      __IOM uint16_t   DTE0: 1
 
      __IOM uint16_t   DTE1: 1
 
      __IOM uint16_t   DTE2: 1
 
      __IM   uint16_t: 1
 
      __IM uint16_t   DTR0: 1
 
      __IM uint16_t   DTR1: 1
 
      __IM uint16_t   DTR2: 1
 
   }   bit
 
T12DTC
 
__IM uint16_t RESERVED11
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   T12CLK: 3
 
      __IOM uint16_t   T12PRE: 1
 
      __IM uint16_t   T12R: 1
 
      __IM uint16_t   STE12: 1
 
      __IM uint16_t   CDIR: 1
 
      __IOM uint16_t   CTM: 1
 
      __IOM uint16_t   T13CLK: 3
 
      __IOM uint16_t   T13PRE: 1
 
      __IM uint16_t   T13R: 1
 
      __IM uint16_t   STE13: 1
 
   }   bit
 
TCTR0
 
__IM uint16_t RESERVED12
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   CCV: 16
 
   }   bit
 
CC60R
 
__IM uint16_t RESERVED13
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   CCV: 16
 
   }   bit
 
CC61R
 
__IM uint16_t RESERVED14
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   CCV: 16
 
   }   bit
 
CC62R
 
__IM uint16_t RESERVED15
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   MSEL60: 4
 
      __IOM uint16_t   MSEL61: 4
 
      __IOM uint16_t   MSEL62: 4
 
      __IOM uint16_t   HSYNC: 3
 
      __IOM uint16_t   DBYP: 1
 
   }   bit
 
T12MSEL
 
__IM uint16_t RESERVED16
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   ENCC60R: 1
 
      __IOM uint16_t   ENCC60F: 1
 
      __IOM uint16_t   ENCC61R: 1
 
      __IOM uint16_t   ENCC61F: 1
 
      __IOM uint16_t   ENCC62R: 1
 
      __IOM uint16_t   ENCC62F: 1
 
      __IOM uint16_t   ENT12OM: 1
 
      __IOM uint16_t   ENT12PM: 1
 
      __IOM uint16_t   ENT13CM: 1
 
      __IOM uint16_t   ENT13PM: 1
 
      __IOM uint16_t   ENTRPF: 1
 
      __IM   uint16_t: 1
 
      __IOM uint16_t   ENCHE: 1
 
      __IOM uint16_t   ENWHE: 1
 
      __IOM uint16_t   ENIDLE: 1
 
      __IOM uint16_t   ENSTR: 1
 
   }   bit
 
IEN
 
__IM uint16_t RESERVED17
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   INPCC60: 2
 
      __IOM uint16_t   INPCC61: 2
 
      __IOM uint16_t   INPCC62: 2
 
      __IOM uint16_t   INPCHE: 2
 
      __IOM uint16_t   INPERR: 2
 
      __IOM uint16_t   INPT12: 2
 
      __IOM uint16_t   INPT13: 2
 
   }   bit
 
INP
 
__IM uint16_t RESERVED18
 
union {
   __IOM uint16_t   reg
 
   struct {
      __OM uint16_t   SCC60R: 1
 
      __OM uint16_t   SCC60F: 1
 
      __OM uint16_t   SCC61R: 1
 
      __OM uint16_t   SCC61F: 1
 
      __OM uint16_t   SCC62R: 1
 
      __OM uint16_t   SCC62F: 1
 
      __OM uint16_t   ST12OM: 1
 
      __OM uint16_t   ST12PM: 1
 
      __OM uint16_t   ST13CM: 1
 
      __OM uint16_t   ST13PM: 1
 
      __OM uint16_t   STRPF: 1
 
      __OM uint16_t   SWHC: 1
 
      __OM uint16_t   SCHE: 1
 
      __OM uint16_t   SWHE: 1
 
      __OM uint16_t   SIDLE: 1
 
      __OM uint16_t   SSTR: 1
 
   }   bit
 
ISS
 
__IM uint16_t RESERVED19
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   PSL: 6
 
      __IM   uint16_t: 1
 
      __IOM uint16_t   PSL63: 1
 
   }   bit
 
PSLR
 
__IM uint16_t RESERVED20
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   SWSEL: 3
 
      __IM   uint16_t: 1
 
      __IOM uint16_t   SWSYN: 2
 
      __IOM uint16_t   STE12U: 1
 
      __IOM uint16_t   STE12D: 1
 
      __IOM uint16_t   STE13U: 1
 
   }   bit
 
MCMCTR
 
__IM uint16_t RESERVED21
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   T12SSC: 1
 
      __IOM uint16_t   T13SSC: 1
 
      __IOM uint16_t   T13TEC: 3
 
      __IOM uint16_t   T13TED: 2
 
      __IM   uint16_t: 1
 
      __IOM uint16_t   T12RSEL: 2
 
      __IOM uint16_t   T13RSEL: 2
 
   }   bit
 
TCTR2
 
__IM uint16_t RESERVED22
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   T12MODEN: 6
 
      __IM   uint16_t: 1
 
      __IOM uint16_t   MCMEN: 1
 
      __IOM uint16_t   T13MODEN: 6
 
      __IOM uint16_t   ECT13O: 1
 
   }   bit
 
MODCTR
 
__IM uint16_t RESERVED23
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   TRPM0: 1
 
      __IOM uint16_t   TRPM1: 1
 
      __IOM uint16_t   TRPM2: 1
 
      __IM   uint16_t: 5
 
      __IOM uint16_t   TRPEN: 6
 
      __IOM uint16_t   TRPEN13: 1
 
      __IOM uint16_t   TRPPEN: 1
 
   }   bit
 
TRPCTR
 
__IM uint16_t RESERVED24
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   MCMP: 6
 
      __IM uint16_t   R: 1
 
      __IM   uint16_t: 1
 
      __IM uint16_t   EXPH: 3
 
      __IM uint16_t   CURH: 3
 
   }   bit
 
MCMOUT
 
__IM uint16_t RESERVED25
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   ICC60R: 1
 
      __IM uint16_t   ICC60F: 1
 
      __IM uint16_t   ICC61R: 1
 
      __IM uint16_t   ICC61F: 1
 
      __IM uint16_t   ICC62R: 1
 
      __IM uint16_t   ICC62F: 1
 
      __IM uint16_t   T12OM: 1
 
      __IM uint16_t   T12PM: 1
 
      __IM uint16_t   T13CM: 1
 
      __IM uint16_t   T13PM: 1
 
      __IM uint16_t   TRPF: 1
 
      __IM uint16_t   TRPS: 1
 
      __IM uint16_t   CHE: 1
 
      __IM uint16_t   WHE: 1
 
      __IM uint16_t   IDLE: 1
 
      __IM uint16_t   STR: 1
 
   }   bit
 
IS
 
__IM uint16_t RESERVED26
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   ISCC60: 2
 
      __IOM uint16_t   ISCC61: 2
 
      __IOM uint16_t   ISCC62: 2
 
      __IOM uint16_t   ISTRP: 2
 
      __IOM uint16_t   ISPOS0: 2
 
      __IOM uint16_t   ISPOS1: 2
 
      __IOM uint16_t   ISPOS2: 2
 
      __IOM uint16_t   IST12HR: 2
 
   }   bit
 
PISEL0
 
__IM uint16_t RESERVED27 [3]
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   IST13HR: 2
 
      __IOM uint16_t   ISCNT12: 2
 
      __IOM uint16_t   ISCNT13: 2
 
      __IOM uint16_t   T12EXT: 1
 
      __IOM uint16_t   T13EXT: 1
 
   }   bit
 
PISEL2
 
__IM uint16_t RESERVED28
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   T12CV: 16
 
   }   bit
 
T12
 
__IM uint16_t RESERVED29
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IOM uint16_t   T13CV: 16
 
   }   bit
 
T13
 
__IM uint16_t RESERVED30
 
union {
   __IOM uint16_t   reg
 
   struct {
      __IM uint16_t   CC60ST: 1
 
      __IM uint16_t   CC61ST: 1
 
      __IM uint16_t   CC62ST: 1
 
      __IM uint16_t   CCPOS0: 1
 
      __IM uint16_t   CCPOS1: 1
 
      __IM uint16_t   CCPOS2: 1
 
      __IM uint16_t   CC63ST: 1
 
      __IM   uint16_t: 1
 
      __IOM uint16_t   CC60PS: 1
 
      __IOM uint16_t   COUT60PS: 1
 
      __IOM uint16_t   CC61PS: 1
 
      __IOM uint16_t   COUT61PS: 1
 
      __IOM uint16_t   CC62PS: 1
 
      __IOM uint16_t   COUT62PS: 1
 
      __IOM uint16_t   COUT63PS: 1
 
      __IOM uint16_t   T13IM: 1
 
   }   bit
 
CMPSTAT
 

Field Documentation

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struct { ... } bit

◆ CC60PS

__IOM uint16_t CC60PS

[8..8] Passive State Select for Compare Outputs

◆ CC60R

union { ... } CC60R

◆ CC60SR

union { ... } CC60SR

◆ CC60ST

__IM uint16_t CC60ST

[0..0] Capture/Compare State Bits (x = 0, 1, 2, 3)

◆ CC61PS

__IOM uint16_t CC61PS

[10..10] Passive State Select for Compare Outputs

◆ CC61R

union { ... } CC61R

◆ CC61SR

union { ... } CC61SR

◆ CC61ST

__IM uint16_t CC61ST

[1..1] Capture/Compare State Bits (x = 0, 1, 2, 3)

◆ CC62PS

__IOM uint16_t CC62PS

[12..12] Passive State Select for Compare Outputs

◆ CC62R

union { ... } CC62R

◆ CC62SR

union { ... } CC62SR

◆ CC62ST

__IM uint16_t CC62ST

[2..2] Capture/Compare State Bits (x = 0, 1, 2, 3)

◆ CC63R

union { ... } CC63R

◆ CC63SR

union { ... } CC63SR

◆ CC63ST

__IM uint16_t CC63ST

[6..6] Capture/Compare State Bits (x = 0, 1, 2, 3)

◆ CCPOS0

__IM uint16_t CCPOS0

[3..3] Sampled Hall Pattern Bits (x = 0, 1, 2)

◆ CCPOS1

__IM uint16_t CCPOS1

[4..4] Sampled Hall Pattern Bits (x = 0, 1, 2)

◆ CCPOS2

__IM uint16_t CCPOS2

[5..5] Sampled Hall Pattern Bits (x = 0, 1, 2)

◆ CCS

[15..0] Shadow Register for Channel x Capture/Compare Value

[15..0] Shadow Register for Channel CC63 Compare Value

◆ CCV

[15..0] Channel CC63 Compare Value

[15..0] Channel x Capture/Compare Value

◆ CDIR

__IM uint16_t CDIR

[6..6] Count Direction of Timer T12

◆ CHE

[12..12] Correct Hall Event

◆ CMPMODIF

union { ... } CMPMODIF

◆ CMPSTAT

union { ... } CMPSTAT

◆ COUT60PS

__IOM uint16_t COUT60PS

[9..9] Passive State Select for Compare Outputs

◆ COUT61PS

__IOM uint16_t COUT61PS

[11..11] Passive State Select for Compare Outputs

◆ COUT62PS

__IOM uint16_t COUT62PS

[13..13] Passive State Select for Compare Outputs

◆ COUT63PS

__IOM uint16_t COUT63PS

[14..14] Passive State Select for Compare Outputs

◆ CTM

[7..7] T12 Operating Mode

◆ CURH

__IM uint16_t CURH

[13..11] Current Hall Pattern

◆ CURHS

__IOM uint16_t CURHS

[13..11] Current Hall Pattern Shadow

◆ DBYP

[15..15] Delay Bypass

◆ DTE0

[8..8] Dead-Time Enable Bits

◆ DTE1

[9..9] Dead-Time Enable Bits

◆ DTE2

[10..10] Dead-Time Enable Bits

◆ DTM

[7..0] Dead-Time

◆ DTR0

__IM uint16_t DTR0

[12..12] Dead-Time Run Indication Bits

◆ DTR1

__IM uint16_t DTR1

[13..13] Dead-Time Run Indication Bits

◆ DTR2

__IM uint16_t DTR2

[14..14] Dead-Time Run Indication Bits

◆ DTRES

__OM uint16_t DTRES

[3..3] Dead-Time Counter Reset

◆ ECT13O

__IOM uint16_t ECT13O

[15..15] Enable Compare Timer T13 Output

◆ ENCC60F

__IOM uint16_t ENCC60F

[1..1] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0

◆ ENCC60R

__IOM uint16_t ENCC60R

[0..0] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0

◆ ENCC61F

__IOM uint16_t ENCC61F

[3..3] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1

◆ ENCC61R

__IOM uint16_t ENCC61R

[2..2] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 1

◆ ENCC62F

__IOM uint16_t ENCC62F

[5..5] Capture, Compare-Match Falling Edge Interrupt Enable for Channel 2

◆ ENCC62R

__IOM uint16_t ENCC62R

[4..4] Capture, Compare-Match Rising Edge Interrupt Enable for Channel 2

◆ ENCHE

__IOM uint16_t ENCHE

[12..12] Enable Interrupt for Correct Hall Event

◆ ENIDLE

__IOM uint16_t ENIDLE

[14..14] Enable Idle

◆ ENSTR

__IOM uint16_t ENSTR

[15..15] Enable Multi-Channel Mode Shadow Transfer Interrupt

◆ ENT12OM

__IOM uint16_t ENT12OM

[6..6] Enable Interrupt for T12 One-Match

◆ ENT12PM

__IOM uint16_t ENT12PM

[7..7] Enable Interrupt for T12 Period-Match

◆ ENT13CM

__IOM uint16_t ENT13CM

[8..8] Enable Interrupt for T13 Compare-Match

◆ ENT13PM

__IOM uint16_t ENT13PM

[9..9] Enable Interrupt for T13 Period-Match

◆ ENTRPF

__IOM uint16_t ENTRPF

[10..10] Enable Interrupt for Trap Flag

◆ ENWHE

__IOM uint16_t ENWHE

[13..13] Enable Interrupt for Wrong Hall Event

◆ EXPH

__IM uint16_t EXPH

[10..8] Expected Hall Pattern

◆ EXPHS

__IOM uint16_t EXPHS

[10..8] Expected Hall Pattern Shadow

◆ HSYNC

__IOM uint16_t HSYNC

[14..12] Hall Synchronization

◆ ICC60F

__IM uint16_t ICC60F

[1..1] Capture, Compare-Match Falling Edge Flag (x = 0, 1, 2)

◆ ICC60R

__IM uint16_t ICC60R

[0..0] Capture, Compare-Match Rising Edge Flag (x = 0, 1, 2)

◆ ICC61F

__IM uint16_t ICC61F

[3..3] Capture, Compare-Match Falling Edge Flag (x = 0, 1, 2)

◆ ICC61R

__IM uint16_t ICC61R

[2..2] Capture, Compare-Match Rising Edge Flag (x = 0, 1, 2)

◆ ICC62F

__IM uint16_t ICC62F

[5..5] Capture, Compare-Match Falling Edge Flag (x = 0, 1, 2)

◆ ICC62R

__IM uint16_t ICC62R

[4..4] Capture, Compare-Match Rising Edge Flag (x = 0, 1, 2)

◆ IDLE

__IM uint16_t IDLE

[14..14] IDLE State

◆ IEN

union { ... } IEN

◆ INP

union { ... } INP

◆ INPCC60

__IOM uint16_t INPCC60

[1..0] Interrupt Node Pointer for Channel 0 Interrupts

◆ INPCC61

__IOM uint16_t INPCC61

[3..2] Interrupt Node Pointer for Channel 1 Interrupts

◆ INPCC62

__IOM uint16_t INPCC62

[5..4] Interrupt Node Pointer for Channel 2 Interrupts

◆ INPCHE

__IOM uint16_t INPCHE

[7..6] Interrupt Node Pointer for the CHE Interrupt

◆ INPERR

__IOM uint16_t INPERR

[9..8] Interrupt Node Pointer for Error Interrupts

◆ INPT12

__IOM uint16_t INPT12

[11..10] Interrupt Node Pointer for Timer T12 Interrupts

◆ INPT13

__IOM uint16_t INPT13

[13..12] Interrupt Node Pointer for Timer T13 Interrupts

◆ IS

union { ... } IS

◆ ISCC60

__IOM uint16_t ISCC60

[1..0] Input Select for CC60

◆ ISCC61

__IOM uint16_t ISCC61

[3..2] Input Select for CC61

◆ ISCC62

__IOM uint16_t ISCC62

[5..4] Input Select for CC62

◆ ISCNT12

__IOM uint16_t ISCNT12

[3..2] Input Select for T12 Counting Input

◆ ISCNT13

__IOM uint16_t ISCNT13

[5..4] Input Select for T13 Counting Input

◆ ISPOS0

__IOM uint16_t ISPOS0

[9..8] Input Select for CCPOS0

◆ ISPOS1

__IOM uint16_t ISPOS1

[11..10] Input Select for CCPOS1

◆ ISPOS2

__IOM uint16_t ISPOS2

[13..12] Input Select for CCPOS2

◆ ISR

union { ... } ISR

◆ ISS

union { ... } ISS

◆ IST12HR

__IOM uint16_t IST12HR

[15..14] Input Select for T12HR

◆ IST13HR

__IOM uint16_t IST13HR

[1..0] Input Select for T13HR

◆ ISTRP

__IOM uint16_t ISTRP

[7..6] Input Select for CTRAP

◆ MCC60R

__OM uint16_t MCC60R

[8..8] Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3)

◆ MCC60S

__OM uint16_t MCC60S

[0..0] Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3)

◆ MCC61R

__OM uint16_t MCC61R

[9..9] Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3)

◆ MCC61S

__OM uint16_t MCC61S

[1..1] Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3)

◆ MCC62R

__OM uint16_t MCC62R

[10..10] Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3)

◆ MCC62S

__OM uint16_t MCC62S

[2..2] Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3)

◆ MCC63R

__OM uint16_t MCC63R

[14..14] Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3)

◆ MCC63S

__OM uint16_t MCC63S

[6..6] Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3)

◆ MCMCTR

union { ... } MCMCTR

◆ MCMEN

__IOM uint16_t MCMEN

[7..7] Multi-Channel Mode Enable

◆ MCMOUT

union { ... } MCMOUT

◆ MCMOUTS

union { ... } MCMOUTS

◆ MCMP

__IM uint16_t MCMP

[5..0] Multi-Channel PWM Pattern

◆ MCMPS

__IOM uint16_t MCMPS

[5..0] Multi-Channel PWM Pattern Shadow

◆ MODCTR

union { ... } MODCTR

◆ MSEL60

__IOM uint16_t MSEL60

[3..0] Capture/Compare Mode Selection

◆ MSEL61

__IOM uint16_t MSEL61

[7..4] Capture/Compare Mode Selection

◆ MSEL62

__IOM uint16_t MSEL62

[11..8] Capture/Compare Mode Selection

◆ PISEL0

union { ... } PISEL0

◆ PISEL2

union { ... } PISEL2

◆ PSL

[5..0] Compare Outputs Passive State Level

◆ PSL63

__IOM uint16_t PSL63

[7..7] Passive State Level of Output COUT63

◆ PSLR

union { ... } PSLR

◆ R

[6..6] Reminder Flag

◆ RCC60F

__OM uint16_t RCC60F

[1..1] Reset Capture, Compare-Match Falling Edge Flag

◆ RCC60R

__OM uint16_t RCC60R

[0..0] Reset Capture, Compare-Match Rising Edge Flag

◆ RCC61F

__OM uint16_t RCC61F

[3..3] Reset Capture, Compare-Match Falling Edge Flag

◆ RCC61R

__OM uint16_t RCC61R

[2..2] Reset Capture, Compare-Match Rising Edge Flag

◆ RCC62F

__OM uint16_t RCC62F

[5..5] Reset Capture, Compare-Match Falling Edge Flag

◆ RCC62R

__OM uint16_t RCC62R

[4..4] Reset Capture, Compare-Match Rising Edge Flag

◆ RCHE

__OM uint16_t RCHE

[12..12] Reset Correct Hall Event Flag

◆ reg

(@ 0x00000000) Capture/Compare Register for Channel CC63

(@ 0x00000004) Timer Control Register 4

(@ 0x00000008) Multi-Channel Mode Output Shadow Register

(@ 0x0000000C) Capture/Compare Interrupt Status Reset Register

(@ 0x00000010) Compare State Modification Register

(@ 0x00000014) Capture/Compare Shadow Register for Channel CC60

(@ 0x00000018) Capture/Compare Shadow Register for Channel CC61

(@ 0x0000001C) Capture/Compare Shadow Register for Channel CC62

(@ 0x00000020) Capture/Compare Shadow Register for Channel CC63

(@ 0x00000024) Timer T12 Period Register

(@ 0x00000028) Timer T13 Period Register

(@ 0x0000002C) Timer T12 Dead-Time Control Register

(@ 0x00000030) Timer Control Register 0

(@ 0x00000034) Capture/Compare Register for Channel CC60

(@ 0x00000038) Capture/Compare Register for Channel CC61

(@ 0x0000003C) Capture/Compare Register for Channel CC62

(@ 0x00000040) Capture/Compare T12 Mode Select Register

(@ 0x00000044) Capture/Compare Interrupt Enable Register

(@ 0x00000048) Capture/Compare Interrupt Node Pointer Register

(@ 0x0000004C) Capture/Compare Interrupt Status Set Register

(@ 0x00000050) Passive State Level Register

(@ 0x00000054) Multi-Channel Mode Control Register

(@ 0x00000058) Timer Control Register 2

(@ 0x0000005C) Modulation Control Register

(@ 0x00000060) Trap Control Register

(@ 0x00000064) Multi-Channel Mode Output Register

(@ 0x00000068) Capture/Compare Interrupt Status Register

(@ 0x0000006C) Port Input Select Register 0

(@ 0x00000074) Port Input Select Register 2

(@ 0x00000078) Timer T12 Counter Register

(@ 0x0000007C) Timer T13 Counter Register

(@ 0x00000080) Compare State Register

◆ RESERVED

__IM uint16_t RESERVED

◆ RESERVED1

__IM uint16_t RESERVED1

◆ RESERVED10

__IM uint16_t RESERVED10

◆ RESERVED11

__IM uint16_t RESERVED11

◆ RESERVED12

__IM uint16_t RESERVED12

◆ RESERVED13

__IM uint16_t RESERVED13

◆ RESERVED14

__IM uint16_t RESERVED14

◆ RESERVED15

__IM uint16_t RESERVED15

◆ RESERVED16

__IM uint16_t RESERVED16

◆ RESERVED17

__IM uint16_t RESERVED17

◆ RESERVED18

__IM uint16_t RESERVED18

◆ RESERVED19

__IM uint16_t RESERVED19

◆ RESERVED2

__IM uint16_t RESERVED2

◆ RESERVED20

__IM uint16_t RESERVED20

◆ RESERVED21

__IM uint16_t RESERVED21

◆ RESERVED22

__IM uint16_t RESERVED22

◆ RESERVED23

__IM uint16_t RESERVED23

◆ RESERVED24

__IM uint16_t RESERVED24

◆ RESERVED25

__IM uint16_t RESERVED25

◆ RESERVED26

__IM uint16_t RESERVED26

◆ RESERVED27

__IM uint16_t RESERVED27[3]

◆ RESERVED28

__IM uint16_t RESERVED28

◆ RESERVED29

__IM uint16_t RESERVED29

◆ RESERVED3

__IM uint16_t RESERVED3

◆ RESERVED30

__IM uint16_t RESERVED30

◆ RESERVED4

__IM uint16_t RESERVED4

◆ RESERVED5

__IM uint16_t RESERVED5

◆ RESERVED6

__IM uint16_t RESERVED6

◆ RESERVED7

__IM uint16_t RESERVED7

◆ RESERVED8

__IM uint16_t RESERVED8

◆ RESERVED9

__IM uint16_t RESERVED9

◆ RIDLE

__OM uint16_t RIDLE

[14..14] Reset IDLE Flag

◆ RSTR

__OM uint16_t RSTR

[15..15] Reset STR Flag

◆ RT12OM

__OM uint16_t RT12OM

[6..6] Reset Timer T12 One-Match Flag

◆ RT12PM

__OM uint16_t RT12PM

[7..7] Reset Timer T12 Period-Match Flag

◆ RT13CM

__OM uint16_t RT13CM

[8..8] Reset Timer T13 Compare-Match Flag

◆ RT13PM

__OM uint16_t RT13PM

[9..9] Reset Timer T13 Period-Match Flag

◆ RTRPF

__OM uint16_t RTRPF

[10..10] Reset Trap Flag

◆ RWHE

__OM uint16_t RWHE

[13..13] Reset Wrong Hall Event Flag

◆ SCC60F

__OM uint16_t SCC60F

[1..1] Set Capture, Compare-Match Falling Edge Flag

◆ SCC60R

__OM uint16_t SCC60R

[0..0] Set Capture, Compare-Match Rising Edge Flag

◆ SCC61F

__OM uint16_t SCC61F

[3..3] Set Capture, Compare-Match Falling Edge Flag

◆ SCC61R

__OM uint16_t SCC61R

[2..2] Set Capture, Compare-Match Rising Edge Flag

◆ SCC62F

__OM uint16_t SCC62F

[5..5] Set Capture, Compare-Match Falling Edge Flag

◆ SCC62R

__OM uint16_t SCC62R

[4..4] Set Capture, Compare-Match Rising Edge Flag

◆ SCHE

__OM uint16_t SCHE

[12..12] Set Correct Hall Event Flag

◆ SIDLE

__OM uint16_t SIDLE

[14..14] Set IDLE Flag

◆ SSTR

__OM uint16_t SSTR

[15..15] Set STR Flag

◆ ST12OM

__OM uint16_t ST12OM

[6..6] Set Timer T12 One-Match Flag

◆ ST12PM

__OM uint16_t ST12PM

[7..7] Set Timer T12 Period-Match Flag

◆ ST13CM

__OM uint16_t ST13CM

[8..8] Set Timer T13 Compare-Match Flag

◆ ST13PM

__OM uint16_t ST13PM

[9..9] Set Timer T13 Period-Match Flag

◆ STE12

__IM uint16_t STE12

[5..5] Timer T12 Shadow Transfer Enable

◆ STE12D

__IOM uint16_t STE12D

[9..9] Shadow Transfer Enable for T12 Downcounting

◆ STE12U

__IOM uint16_t STE12U

[8..8] Shadow Transfer Enable for T12 Upcounting

◆ STE13

__IM uint16_t STE13

[13..13] Timer T13 Shadow Transfer Enable

◆ STE13U

__IOM uint16_t STE13U

[10..10] Shadow Transfer Enable for T13 Upcounting

◆ STR

[15..15] Multi-Channel Mode Shadow Transfer Request

◆ STRHP

__IOM uint16_t STRHP

[15..15] Shadow Transfer Request for the Hall Pattern

◆ STRMCM

__IOM uint16_t STRMCM

[7..7] Shadow Transfer Request for MCMPS

◆ STRPF

__OM uint16_t STRPF

[10..10] Set Trap Flag

◆ SWHC

__OM uint16_t SWHC

[11..11] Software Hall Compare

◆ SWHE

__OM uint16_t SWHE

[13..13] Set Wrong Hall Event Flag

◆ SWSEL

__IOM uint16_t SWSEL

[2..0] Switching Selection

◆ SWSYN

__IOM uint16_t SWSYN

[5..4] Switching Synchronization

◆ T12

union { ... } T12

◆ T12CLK

__IOM uint16_t T12CLK

[2..0] Timer T12 Input Clock Select

◆ T12CNT

__OM uint16_t T12CNT

[5..5] Timer T12 Count Event

◆ T12CV

__IOM uint16_t T12CV

[15..0] Timer T12 Counter Value

◆ T12DTC

union { ... } T12DTC

◆ T12EXT

__IOM uint16_t T12EXT

[6..6] Extension for T12HR Inputs

◆ T12MODEN

__IOM uint16_t T12MODEN

[5..0] T12 Modulation Enable

◆ T12MSEL

union { ... } T12MSEL

◆ T12OM

__IM uint16_t T12OM

[6..6] Timer T12 One-Match Flag

◆ T12PM

__IM uint16_t T12PM

[7..7] Timer T12 Period-Match Flag

◆ T12PR

union { ... } T12PR

◆ T12PRE

__IOM uint16_t T12PRE

[3..3] Timer T12 Prescaler Bit

◆ T12PV

__IOM uint16_t T12PV

[15..0] T12 Period Value

◆ T12R

__IM uint16_t T12R

[4..4] Timer T12 Run Bit

◆ T12RES

__OM uint16_t T12RES

[2..2] Timer T12 Reset

◆ T12RR

__OM uint16_t T12RR

[0..0] Timer T12 Run Reset

◆ T12RS

__OM uint16_t T12RS

[1..1] Timer T12 Run Set

◆ T12RSEL

__IOM uint16_t T12RSEL

[9..8] Timer T12 External Run Selection

◆ T12SSC

__IOM uint16_t T12SSC

[0..0] Timer T12 Single Shot Control

◆ T12STD

__OM uint16_t T12STD

[7..7] Timer T12 Shadow Transfer Disable

◆ T12STR

__OM uint16_t T12STR

[6..6] Timer T12 Shadow Transfer Request

◆ T13

union { ... } T13

◆ T13CLK

__IOM uint16_t T13CLK

[10..8] Timer T13 Input Clock Select

◆ T13CM

__IM uint16_t T13CM

[8..8] Timer T13 Compare-Match Flag

◆ T13CNT

__OM uint16_t T13CNT

[13..13] Timer T13 Count Event

◆ T13CV

__IOM uint16_t T13CV

[15..0] Timer T13 Counter Value

◆ T13EXT

__IOM uint16_t T13EXT

[7..7] Extension for T13HR Inputs

◆ T13IM

__IOM uint16_t T13IM

[15..15] T13 Inverted Modulation

◆ T13MODEN

__IOM uint16_t T13MODEN

[13..8] T13 Modulation Enable

◆ T13PM

__IM uint16_t T13PM

[9..9] Timer T13 Period-Match Flag

◆ T13PR

union { ... } T13PR

◆ T13PRE

__IOM uint16_t T13PRE

[11..11] Timer T13 Prescaler Bit

◆ T13PV

__IOM uint16_t T13PV

[15..0] T13 Period Value

◆ T13R

__IM uint16_t T13R

[12..12] Timer T13 Run Bit

◆ T13RES

__OM uint16_t T13RES

[10..10] Timer T13 Reset

◆ T13RR

__OM uint16_t T13RR

[8..8] Timer T13 Run Reset

◆ T13RS

__OM uint16_t T13RS

[9..9] Timer T13 Run Set

◆ T13RSEL

__IOM uint16_t T13RSEL

[11..10] Timer T13 External Run Selection

◆ T13SSC

__IOM uint16_t T13SSC

[1..1] Timer T13 Single Shot Control

◆ T13STD

__OM uint16_t T13STD

[15..15] Timer T13 Shadow Transfer Disable

◆ T13STR

__OM uint16_t T13STR

[14..14] Timer T13 Shadow Transfer Request

◆ T13TEC

__IOM uint16_t T13TEC

[4..2] T13 Trigger Event Control

◆ T13TED

__IOM uint16_t T13TED

[6..5] Timer T13 Trigger Event Direction

◆ TCTR0

union { ... } TCTR0

◆ TCTR2

union { ... } TCTR2

◆ TCTR4

union { ... } TCTR4

◆ TRPCTR

union { ... } TRPCTR

◆ TRPEN

__IOM uint16_t TRPEN

[13..8] Trap Enable Control

◆ TRPEN13

__IOM uint16_t TRPEN13

[14..14] Trap Enable Control for Timer T13

◆ TRPF

__IM uint16_t TRPF

[10..10] Trap Flag

◆ TRPM0

__IOM uint16_t TRPM0

[0..0] Trap Mode Control Bits 1, 0

◆ TRPM1

__IOM uint16_t TRPM1

[1..1] Trap Mode Control Bits 1, 0

◆ TRPM2

__IOM uint16_t TRPM2

[2..2] Trap Mode Control Bit 2

◆ TRPPEN

__IOM uint16_t TRPPEN

[15..15] Trap Pin Enable

◆ TRPS

__IM uint16_t TRPS

[11..11] Trap State

◆ uint16_t

__IM uint16_t

◆ WHE

[13..13] Wrong Hall Event


The documentation for this struct was generated from the following file: