TLE986x Device Family SDK
gpt12e.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2015, Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
37 /*******************************************************************************
38 ** Author(s) Identity **
39 ********************************************************************************
40 ** Initials Name **
41 ** ---------------------------------------------------------------------------**
42 ** DM Daniel Mysliwitz **
43 ** JO Julia Ott **
44 ** BG Blandine Guillot **
45 *******************************************************************************/
46 
47 /*******************************************************************************
48 ** Revision Control History **
49 ********************************************************************************
50 ** V0.1.0: 2014-05-13, DM: Initial version **
51 ** V0.1.1: 2015-01-20, DM: GPT12E timer stop API added **
52 ** V0.1.2: 2015-02-10, DM: Individual header file added **
53 ** V0.1.3: 2015-08-27, DM: Timer readout functions added **
54 ** V0.1.4: 2017-05-26, DM: API extended **
55 ** V0.1.5: 2017-09-29, DM: MISRA 2012 compliance, the following PC-Lint **
56 ** rules are globally deactivated: **
57 ** - Info 793: ANSI/ISO limit of 6 'significant **
58 ** characters in an external identifier **
59 ** - Info 835: A zero has been given as right **
60 ** argument to operator **
61 ** - Info 845: The left argument to operator '&' **
62 ** is certain to be 0 **
63 ** Replaced macros by INLINE functions **
64 ** Replaced register accesses within functions by **
65 ** function calls **
66 ** V0.1.6: 2018-03-14, DM: GPT12E_T5_Capture_Trig_Rising_CapIn_En(), **
67 ** GPT12E_T5_Capture_Trig_Rising_CapIn_Dis(), **
68 ** GPT12E_T5_Capture_Trig_Falling_CapIn_En(), **
69 ** GPT12E_T5_Capture_Trig_Falling_CapIn_Dis(), **
70 ** GPT12E_T5_Capture_Trig_Any_T3In_En(), **
71 ** GPT12E_T5_Capture_Trig_Any_T3In_Dis(), **
72 ** GPT12E_T5_Capture_Trig_Any_T3EUD_En(), **
73 ** GPT12E_T5_Capture_Trig_Any_T3EUD_Dis() modified **
74 ** for MISRA 2012 **
75 ** V0.1.7: 2018-07-05, BG: Values for GPT12E_T4_Start_by_T3_En() and **
76 ** GPT12E_T4_Start_by_T3_Dis() corrected in gpt12e.h**
77 ** V0.1.8: 2018-11-27, JO: Doxygen update, moved revision history from **
78 ** gpt12e.c to gpt12e.h **
79 ** V0.1.9: 2020-02-28, BG: Updated revision history format **
80 *******************************************************************************/
81 
82 #ifndef GPT12E_H
83 #define GPT12E_H
84 
85 /*******************************************************************************
86 ** Includes **
87 *******************************************************************************/
88 #include "tle986x.h"
89 #include "types.h"
90 #include "sfr_access.h"
91 #include "gpt12e_defines.h"
92 
93 /******************************************************************************
94 ** Global Type Definitions **
95 *******************************************************************************/
99 typedef enum
100 {
101  GPT1_fSYS_Div_4 = 1u,
102  GPT1_fSYS_Div_8 = 0u,
103  GPT1_fSYS_Div_16 = 3u,
104  GPT1_fSYS_Div_32 = 2u
106 
110 typedef enum
111 {
120  GPT12E_CCU6_T13_PM = 8u,
121  GPT12E_CCU6_T13_ZM = 9u,
122  GPT12E_CCU6_T13_CM = 10u,
123  GPT12E_CCU6_ANY_CHx = 11u
125 
129 typedef enum
130 {
131  GPT12E_T2INA_P12 = 0u,
132  GPT12E_T2INB_P14 = 1u
133 } TGPT12E_T2IN;
134 
138 typedef enum
139 {
140  GPT12E_T2EUDA_P02 = 0u,
141  GPT12E_T2EUDB_P24 = 1u
142 } TGPT12E_T2EUD;
143 
147 typedef enum
148 {
149  GPT12E_T3INA_CCU6_CH0 = 0u,
150  GPT12E_T3INB_CCU6_SEL = 1u,
151  GPT12E_T3INC_P10 = 2u,
152  GPT12E_T3IND_MON = 3u
153 } TGPT12E_T3IN;
154 
158 typedef enum
159 {
160  GPT12E_T3EUDA_P04 = 0u,
161  GPT12E_T3EUDB_P25 = 1u
162 } TGPT12E_T3EUD;
163 
167 typedef enum
168 {
169  GPT12E_T4INA_P00 = 0u,
170  GPT12E_T4INB_CCU6_CH0 = 1u,
171  GPT12E_T4INC_P01 = 2u,
173 } TGPT12E_T4IN;
174 
178 typedef enum
179 {
180  GPT12E_T4EUDA_P03 = 0u,
181  GPT12E_T4EUDB_P10 = 1u
182 } TGPT12E_T4EUD;
183 
187 typedef enum
188 {
189  GPT2_fSYS_Div_2 = 1u,
190  GPT2_fSYS_Div_4 = 0u,
191  GPT2_fSYS_Div_8 = 3u,
192  GPT2_fSYS_Div_16 = 2u
194 
198 typedef enum
199 {
200  GPT12E_T5INA_P03 = 0u,
201  GPT12E_T5INB_P20 = 1u
202 } TGPT12E_T5IN;
203 
207 typedef enum
208 {
209  GPT12E_T5EUDA_P14 = 0u,
210  GPT12E_T5EUDB_P20 = 1u
211 } TGPT12E_T5EUD;
212 
216 typedef enum
217 {
218  GPT12E_T6INA_P02 = 0u,
219  GPT12E_T6INB_P13 = 1u
220 } TGPT12E_T6IN;
221 
225 typedef enum
226 {
227  GPT12E_T6EUDA_P11 = 0u,
228  GPT12E_T6EUDB_P13 = 1u
229 } TGPT12E_T6EUD;
230 
234 typedef enum
235 {
236  GPT12E_CAPINA_P01 = 0u,
237  GPT12E_CAPINB_P03 = 1u,
238  GPT12E_CAPINC_T3_READ = 2u,
240 } TGPT12E_CAPIN;
241 
245 typedef enum
246 {
251  GPT_Clk_Div_16 = 4,
252  GPT_Clk_Div_32 = 5,
253  GPT_Clk_Div_64 = 6,
254  GPT_Clk_Div_128 = 7
256 
257 
258 /*******************************************************************************
259 ** Global Inline Function Definitions **
260 *******************************************************************************/
276 {
278 }
279 
297 {
299 }
300 
316 {
318 }
319 
320 /****************************************************************************/
321 /* Timer2 *******************************************************************/
322 /****************************************************************************/
336 {
338 }
339 
353 {
355 }
356 
370 {
372 }
373 
387 {
389 }
390 
404 {
406 }
407 
421 {
423 }
424 
438 {
440 }
441 
455 {
457 }
458 
475 {
477 }
478 
495 {
497 }
498 
513 {
514  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
515 }
516 
531 {
532  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
533 }
534 
549 {
550  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
551 }
552 
567 {
568  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
569 }
570 
585 {
586  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
587 }
588 
603 {
604  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 1u);
605 }
606 
621 {
622  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
623 }
624 
639 {
640  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
641 }
642 
657 {
658  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
659 }
660 
675 {
676  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
677 }
678 
693 {
694  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
695 }
696 
711 {
712  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
713 }
714 
729 {
730  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
731 }
732 
747 {
748  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
749 }
750 
765 {
766  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
767 }
768 
783 {
784  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
785 }
786 
801 {
802  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
803 }
804 
819 {
820  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
821 }
822 
837 {
838  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
839 }
840 
855 {
856  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
857 }
858 
873 {
874  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 1u);
875 }
876 
891 {
892  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
893 }
894 
909 {
910  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
911 }
912 
927 {
928  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
929 }
930 
945 {
946  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
947 }
948 
963 {
964  Field_Mod16(&GPT12E->T2CON.reg, 2u, 4u, 0u);
965 }
966 
981 {
982  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 1u);
983 }
984 
999 {
1000  Field_Mod16(&GPT12E->T2CON.reg, 0u, 1u, 0u);
1001 }
1002 
1017 {
1018  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 1u);
1019 }
1020 
1035 {
1036  Field_Mod16(&GPT12E->T2CON.reg, 1u, 2u, 0u);
1037 }
1038 
1052 INLINE void GPT12E_T2_Start(void)
1053 {
1055 }
1056 
1070 INLINE void GPT12E_T2_Stop(void)
1071 {
1073 }
1074 
1089 {
1091 }
1092 
1107 {
1109 }
1110 
1125 {
1127 }
1128 
1142 INLINE void GPT12E_T2_UpCount_Sel(void)
1143 {
1145 }
1146 
1160 {
1162 }
1163 
1178 {
1180 }
1181 
1196 {
1198 }
1199 
1214 {
1216 }
1217 
1237 {
1239 }
1240 
1258 {
1260 }
1261 
1281 {
1283 }
1284 
1302 {
1304 }
1305 
1323 {
1325 }
1326 
1342 {
1344 }
1345 
1362 INLINE void GPT12E_T2_T2In_Sel(uint16 ist2in)
1363 {
1365 }
1366 
1382 INLINE void GPT12E_T2_T2EUD_Sel(uint16 ist2eud)
1383 {
1385 }
1386 
1387 /****************************************************************************/
1388 /* Timer3 * Core Timer ******************************************************/
1389 /****************************************************************************/
1403 {
1405 }
1406 
1420 {
1422 }
1423 
1437 {
1439 }
1440 
1454 {
1456 }
1457 
1471 {
1473 }
1474 
1488 {
1490 }
1491 
1508 {
1510 }
1511 
1528 {
1530 }
1531 
1546 {
1547  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 1u);
1548 }
1549 
1564 {
1565  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 0u);
1566 }
1567 
1582 {
1583  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 1u);
1584 }
1585 
1600 {
1601  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 0u);
1602 }
1603 
1618 {
1619  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 1u);
1620 }
1621 
1636 {
1637  Field_Mod16(&GPT12E->T3CON.reg, 0u, 1u, 0u);
1638 }
1639 
1654 {
1655  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 1u);
1656 }
1657 
1672 {
1673  Field_Mod16(&GPT12E->T3CON.reg, 1u, 2u, 0u);
1674 }
1675 
1688 INLINE void GPT12E_T3_Start(void)
1689 {
1691 }
1692 
1705 INLINE void GPT12E_T3_Stop(void)
1706 {
1708 }
1709 
1722 INLINE void GPT12E_T3_Output_En(void)
1723 {
1725 }
1726 
1739 INLINE void GPT12E_T3_Output_Dis(void)
1740 {
1742 }
1743 
1757 INLINE void GPT12E_T3_Output_Set(void)
1758 {
1760 }
1761 
1775 INLINE void GPT12E_T3_Output_Rst(void)
1776 {
1778 }
1779 
1794 {
1796 }
1797 
1811 INLINE void GPT12E_T3_UpCount_Sel(void)
1812 {
1814 }
1815 
1829 {
1831 }
1832 
1847 {
1849 }
1850 
1865 {
1867 }
1868 
1883 {
1885 }
1886 
1906 {
1908 }
1909 
1927 {
1929 }
1930 
1950 {
1952 }
1953 
1971 {
1973 }
1974 
1992 {
1994 }
1995 
2011 {
2013 }
2014 
2031 INLINE void GPT12E_T3_T3In_Sel(uint16 ist3in)
2032 {
2034 }
2035 
2051 INLINE void GPT12E_T3_T3EUD_Sel(uint16 ist3eud)
2052 {
2054 }
2055 
2056 /****************************************************************************/
2057 /* Timer4 *******************************************************************/
2058 /****************************************************************************/
2072 {
2074 }
2075 
2089 {
2091 }
2092 
2106 {
2108 }
2109 
2123 {
2125 }
2126 
2140 {
2142 }
2143 
2157 {
2159 }
2160 
2174 {
2176 }
2177 
2191 {
2193 }
2194 
2211 {
2213 }
2214 
2231 {
2233 }
2234 
2249 {
2250  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2251 }
2252 
2267 {
2268  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2269 }
2270 
2285 {
2286  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2287 }
2288 
2303 {
2304  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2305 }
2306 
2321 {
2322  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2323 }
2324 
2339 {
2340  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 1u);
2341 }
2342 
2357 {
2358  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2359 }
2360 
2375 {
2376  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2377 }
2378 
2393 {
2394  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2395 }
2396 
2411 {
2412  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2413 }
2414 
2429 {
2430  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2431 }
2432 
2447 {
2448  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2449 }
2450 
2465 {
2466  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2467 }
2468 
2483 {
2484  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2485 }
2486 
2501 {
2502  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2503 }
2504 
2519 {
2520  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 0u);
2521 }
2522 
2537 {
2538  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2539 }
2540 
2555 {
2556  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2557 }
2558 
2573 {
2574  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2575 }
2576 
2591 {
2592  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2593 }
2594 
2609 {
2610  Field_Mod16(&GPT12E->T4CON.reg, 2u, 4u, 1u);
2611 }
2612 
2627 {
2628  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2629 }
2630 
2645 {
2646  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2647 }
2648 
2663 {
2664  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2665 }
2666 
2681 {
2682  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2683 }
2684 
2699 {
2700  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 1u);
2701 }
2702 
2717 {
2718  Field_Mod16(&GPT12E->T4CON.reg, 0u, 1u, 0u);
2719 }
2720 
2735 {
2736  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 1u);
2737 }
2738 
2753 {
2754  Field_Mod16(&GPT12E->T4CON.reg, 1u, 2u, 0u);
2755 }
2756 
2770 INLINE void GPT12E_T4_Start(void)
2771 {
2773 }
2774 
2788 INLINE void GPT12E_T4_Stop(void)
2789 {
2791 }
2792 
2807 {
2809 }
2810 
2825 {
2827 }
2828 
2843 {
2845 }
2846 
2860 INLINE void GPT12E_T4_UpCount_Sel(void)
2861 {
2863 }
2864 
2878 {
2880 }
2881 
2896 {
2898 }
2899 
2914 {
2916 }
2917 
2932 {
2934 }
2935 
2950 INLINE void GPT12E_T4_Clr_T2_En(void)
2951 {
2953 }
2954 
2967 INLINE void GPT12E_T4_Clr_T2_Dis(void)
2968 {
2970 }
2971 
2986 INLINE void GPT12E_T4_Clr_T3_En(void)
2987 {
2989 }
2990 
3003 INLINE void GPT12E_T4_Clr_T3_Dis(void)
3004 {
3006 }
3007 
3027 {
3029 }
3030 
3048 {
3050 }
3051 
3071 {
3073 }
3074 
3092 {
3094 }
3095 
3113 {
3115 }
3116 
3132 {
3134 }
3135 
3152 INLINE void GPT12E_T4_T4In_Sel(uint16 ist4in)
3153 {
3155 }
3156 
3172 INLINE void GPT12E_T4_T4EUD_Sel(uint16 ist4eud)
3173 {
3175 }
3176 
3177 /****************************************************************************/
3178 /* GPT2 *******************************************************************/
3179 /****************************************************************************/
3195 {
3197 }
3198 
3216 {
3218 }
3219 
3220 /****************************************************************************/
3221 /* Timer5 *******************************************************************/
3222 /****************************************************************************/
3236 {
3238 }
3239 
3253 {
3255 }
3256 
3270 {
3272 }
3273 
3287 {
3289 }
3290 
3307 {
3309 }
3310 
3327 {
3329 }
3330 
3345 {
3346  Field_Mod16(&GPT12E->T5CON.reg, 2u, 4u, 0u);
3347 }
3348 
3363 {
3364  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 1u);
3365 }
3366 
3381 {
3382  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 1u);
3383 }
3384 
3399 {
3400  Field_Mod16(&GPT12E->T5CON.reg, 0u, 3u, 3u);
3401 }
3402 
3417 {
3418  Field_Mod16(&GPT12E->T5CON.reg, 2u, 4u, 1u);
3419 }
3420 
3435 {
3436  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 1u);
3437 }
3438 
3453 {
3454  Field_Mod16(&GPT12E->T5CON.reg, 0u, 1u, 0u);
3455 }
3456 
3471 {
3472  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 1u);
3473 }
3474 
3489 {
3490  Field_Mod16(&GPT12E->T5CON.reg, 1u, 2u, 0u);
3491 }
3492 
3505 INLINE void GPT12E_T5_Capture_En(void)
3506 {
3508 }
3509 
3522 INLINE void GPT12E_T5_Capture_Dis(void)
3523 {
3525 }
3526 
3541 {
3543 }
3544 
3560 {
3561  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 1u);
3562 }
3563 
3579 {
3580  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 0u);
3581 }
3582 
3598 {
3599  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 1u);
3600 }
3601 
3617 {
3618  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 0u);
3619 }
3620 
3635 {
3637 }
3638 
3654 {
3655  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 1u);
3656 }
3657 
3673 {
3674  Field_Mod16(&GPT12E->T5CON.reg, 12u, ((uint16)1u << 12u), 0u);
3675 }
3676 
3692 {
3693  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 1u);
3694 }
3695 
3711 {
3712  Field_Mod16(&GPT12E->T5CON.reg, 13u, ((uint16)1u << 13u), 0u);
3713 }
3714 
3729 {
3731 }
3732 
3747 {
3749 }
3750 
3769 {
3771 }
3772 
3786 INLINE void GPT12E_T5_Start(void)
3787 {
3789 }
3790 
3804 INLINE void GPT12E_T5_Stop(void)
3805 {
3807 }
3808 
3823 {
3825 }
3826 
3841 {
3843 }
3844 
3859 {
3861 }
3862 
3876 INLINE void GPT12E_T5_UpCount_Sel(void)
3877 {
3879 }
3880 
3894 {
3896 }
3897 
3912 {
3914 }
3915 
3933 {
3935 }
3936 
3952 {
3954 }
3955 
3972 INLINE void GPT12E_T5_T5In_Sel(uint16 ist5in)
3973 {
3975 }
3976 
3992 INLINE void GPT12E_T5_T5EUD_Sel(uint16 ist5eud)
3993 {
3995 }
3996 
3997 /****************************************************************************/
3998 /* Timer6 *******************************************************************/
3999 /****************************************************************************/
4013 {
4015 }
4016 
4030 {
4032 }
4033 
4047 {
4049 }
4050 
4064 {
4066 }
4067 
4084 {
4086 }
4087 
4104 {
4106 }
4107 
4122 {
4123  Field_Mod16(&GPT12E->T6CON.reg, (uint16)2u, (uint16)4u, 0u);
4124 }
4125 
4140 {
4141  Field_Mod16(&GPT12E->T6CON.reg, (uint16)0u, (uint16)1u, 1u);
4142 }
4143 
4158 {
4159  Field_Mod16(&GPT12E->T6CON.reg, (uint16)1u, (uint16)2u, 1u);
4160 }
4161 
4176 {
4177  Field_Mod16(&GPT12E->T6CON.reg, (uint16)0u, (uint16)3u, 3u);
4178 }
4179 
4192 INLINE void GPT12E_T6_Reload_En(void)
4193 {
4195 }
4196 
4209 INLINE void GPT12E_T6_Reload_Dis(void)
4210 {
4212 }
4213 
4230 {
4232 }
4233 
4248 {
4250 }
4251 
4266 {
4268 }
4269 
4282 INLINE void GPT12E_T6_Start(void)
4283 {
4285 }
4286 
4299 INLINE void GPT12E_T6_Stop(void)
4300 {
4302 }
4303 
4316 INLINE void GPT12E_T6_Output_En(void)
4317 {
4319 }
4320 
4333 INLINE void GPT12E_T6_Output_Dis(void)
4334 {
4336 }
4337 
4351 INLINE void GPT12E_T6_Output_Set(void)
4352 {
4354 }
4355 
4369 INLINE void GPT12E_T6_Output_Rst(void)
4370 {
4372 }
4373 
4388 {
4390 }
4391 
4405 INLINE void GPT12E_T6_UpCount_Sel(void)
4406 {
4408 }
4409 
4423 {
4425 }
4426 
4441 {
4443 }
4444 
4462 {
4464 }
4465 
4481 {
4483 }
4484 
4501 INLINE void GPT12E_T6_T6In_Sel(uint16 ist6in)
4502 {
4504 }
4505 
4521 INLINE void GPT12E_T6_T6EUD_Sel(uint16 ist6eud)
4522 {
4524 }
4525 
4526 /****************************************************************************/
4527 /* CAPREL *******************************************************************/
4528 /****************************************************************************/
4547 {
4549 }
4550 
4551 /****************************************************************************/
4552 /* Interrupt ****************************************************************/
4553 /****************************************************************************/
4574 {
4575  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T2_Pos, (uint8)SCU_GPT12IRC_T2_Msk) );
4576 }
4577 
4598 {
4599  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T3_Pos, (uint8)SCU_GPT12IRC_T3_Msk) );
4600 }
4601 
4622 {
4623  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T4_Pos, (uint8)SCU_GPT12IRC_T4_Msk) );
4624 }
4625 
4646 {
4647  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T5_Pos, (uint8)SCU_GPT12IRC_T5_Msk) );
4648 }
4649 
4670 {
4671  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_T6_Pos, (uint8)SCU_GPT12IRC_T6_Msk) );
4672 }
4673 
4694 {
4695  return ( u1_Field_Rd8(&SCU->GPT12IRC.reg, (uint8)SCU_GPT12IRC_CR_Pos, (uint8)SCU_GPT12IRC_CR_Msk) );
4696 }
4697 
4698 /* GPT12E Interrupt Clear Macros */
4717 INLINE void GPT12E_T2_Int_Clr(void)
4718 {
4720 }
4721 
4740 INLINE void GPT12E_T3_Int_Clr(void)
4741 {
4743 }
4744 
4763 INLINE void GPT12E_T4_Int_Clr(void)
4764 {
4766 }
4767 
4786 INLINE void GPT12E_T5_Int_Clr(void)
4787 {
4789 }
4790 
4809 INLINE void GPT12E_T6_Int_Clr(void)
4810 {
4812 }
4813 
4832 INLINE void GPT12E_CapRel_Int_Clr(void)
4833 {
4835 }
4836 
4855 INLINE void GPT12E_T2_Int_En(void)
4856 {
4858 }
4859 
4878 INLINE void GPT12E_T2_Int_Dis(void)
4879 {
4881 }
4882 
4901 INLINE void GPT12E_T3_Int_En(void)
4902 {
4904 }
4905 
4924 INLINE void GPT12E_T3_Int_Dis(void)
4925 {
4927 }
4928 
4947 INLINE void GPT12E_T4_Int_En(void)
4948 {
4950 }
4951 
4970 INLINE void GPT12E_T4_Int_Dis(void)
4971 {
4973 }
4974 
4993 INLINE void GPT12E_T5_Int_En(void)
4994 {
4996 }
4997 
5016 INLINE void GPT12E_T5_Int_Dis(void)
5017 {
5019 }
5020 
5039 INLINE void GPT12E_T6_Int_En(void)
5040 {
5042 }
5043 
5062 INLINE void GPT12E_T6_Int_Dis(void)
5063 {
5065 }
5066 
5085 INLINE void GPT12E_CapRel_Int_En(void)
5086 {
5088 }
5089 
5108 INLINE void GPT12E_CapRel_Int_Dis(void)
5109 {
5111 }
5112 
5113 /*******************************************************************************
5114 ** Global Function Declarations **
5115 *******************************************************************************/
5120 void GPT12E_Init(void);
5121 
5141 bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us);
5142 
5160 bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us);
5161 
5162 #endif
GPT12E_T3_Output_Dis
INLINE void GPT12E_T3_Output_Dis(void)
disables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:1734
SCU_GPT12IRC_T6_Msk
#define SCU_GPT12IRC_T6_Msk
Definition: tle986x.h:8831
GPT12E_T6CON_T6I_Pos
#define GPT12E_T6CON_T6I_Pos
Definition: tle986x.h:7975
GPT12E_T4_Mode_IncEnc_Edge_Detect_Clr
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:3042
GPT12E_T3INA_CCU6_CH0
Definition: gpt12e.h:145
GPT12E_T2INA_P12
Definition: gpt12e.h:127
GPT12E_T6CON_T6OE_Pos
#define GPT12E_T6CON_T6OE_Pos
Definition: tle986x.h:7985
SCU_GPT12ICLR_T3C_Msk
#define SCU_GPT12ICLR_T3C_Msk
Definition: tle986x.h:8811
GPT12E_T2CON_T2I_Msk
#define GPT12E_T2CON_T2I_Msk
Definition: tle986x.h:7874
GPT12E_T2CON_T2M_Msk
#define GPT12E_T2CON_T2M_Msk
Definition: tle986x.h:7876
GPT12E_T2_UpCount_Sel
INLINE void GPT12E_T2_UpCount_Sel(void)
selects Timer T2 counts up.
Definition: gpt12e.h:1137
GPT12E_T6_UpDownCount_Ext_En
INLINE void GPT12E_T6_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:4417
GPT12E_T6_Output_Set
INLINE void GPT12E_T6_Output_Set(void)
sets Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:4346
GPT12E_T4_Stop
INLINE void GPT12E_T4_Stop(void)
stops Timer T4.
Definition: gpt12e.h:2783
GPT12E_T2CON_T2CHDIR_Pos
#define GPT12E_T2CON_T2CHDIR_Pos
Definition: tle986x.h:7889
GPT12E_T4CON_T4CHDIR_Pos
#define GPT12E_T4CON_T4CHDIR_Pos
Definition: tle986x.h:7943
Field_Mod16
INLINE void Field_Mod16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:351
GPT12E_T2_Mode_Counter_Input_Rising_T3Out_En
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:615
GPT12E_T4_Start_by_T3_En
INLINE void GPT12E_T4_Start_by_T3_En(void)
enables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:2801
GPT12E_T3_Mode_IncEnc_Any_T3EUD_En
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1648
GPT12E_T4_T4_Msk
#define GPT12E_T4_T4_Msk
Definition: tle986x.h:7921
GPT12E_T4_Mode_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T4_Mode_Timer_Clk_Prescaler_Sel(uint16 t4i)
selects T4 Timer Mode Parameter.
Definition: gpt12e.h:2205
GPT12E_PISEL_ISCAPIN_Msk
#define GPT12E_PISEL_ISCAPIN_Msk
Definition: tle986x.h:7868
GPT12E_T6_Stop
INLINE void GPT12E_T6_Stop(void)
stops Timer T6.
Definition: gpt12e.h:4294
GPT12E_T6CON_T6OTL_Msk
#define GPT12E_T6CON_T6OTL_Msk
Definition: tle986x.h:7988
GPT12E_CAPINB_P03
Definition: gpt12e.h:233
GPT12E_T2CON_T2RC_Pos
#define GPT12E_T2CON_T2RC_Pos
Definition: tle986x.h:7883
GPT12E_T5INB_P20
Definition: gpt12e.h:197
GPT12E_T2_Mode_Capture_Input_Rising_T2In_Dis
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:723
GPT12E_T5EUDA_P14
Definition: gpt12e.h:205
GPT12E_CCU6_T13_ZM
Definition: gpt12e.h:117
GPT12E_T5_UpDownCount_Ext_Dis
INLINE void GPT12E_T5_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:3906
GPT_Clk_Div_2
Definition: gpt12e.h:244
GPT12E_T4_Mode_IncEnc_Any_T3In_En
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2693
GPT12E_T6_Interval_Timer_Setup
bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T6 to be reloaded by CAPREL.
GPT12E_T3_Output_Rst
INLINE void GPT12E_T3_Output_Rst(void)
clears Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:1770
GPT12E_T5_Capture_En
INLINE void GPT12E_T5_Capture_En(void)
enables T5 Capture Mode.
Definition: gpt12e.h:3500
GPT12E_T3_Mode_Counter_Input_Rising_T3In_En
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_En(void)
enables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1540
SCU_GPT12ICLR_T6C_Pos
#define SCU_GPT12ICLR_T6C_Pos
Definition: tle986x.h:8804
SCU_GPT12IRC_T3_Pos
#define SCU_GPT12IRC_T3_Pos
Definition: tle986x.h:8836
GPT12E_T6_Value_Set
INLINE void GPT12E_T6_Value_Set(uint16 t6)
sets Timer T6 Value.
Definition: gpt12e.h:4475
GPT12E_T4_Clr_T2_Dis
INLINE void GPT12E_T4_Clr_T2_Dis(void)
Disables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2962
GPT12E_T2_Mode_Timer_Sel
INLINE void GPT12E_T2_Mode_Timer_Sel(void)
selects T2 Timer Mode.
Definition: gpt12e.h:330
GPT12E_T2_Stop
INLINE void GPT12E_T2_Stop(void)
stops Timer T2.
Definition: gpt12e.h:1065
GPT12E_T2CON_T2CHDIR_Msk
#define GPT12E_T2CON_T2CHDIR_Msk
Definition: tle986x.h:7890
GPT12E_T3CON_T3I_Pos
#define GPT12E_T3CON_T3I_Pos
Definition: tle986x.h:7897
GPT12E_T4_Mode_Reload_Input_Rising_T3Out_En
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2621
GPT12E_T6CON_T6CLR_Pos
#define GPT12E_T6CON_T6CLR_Pos
Definition: tle986x.h:7991
GPT12E_T4_Mode_Capture_Sel
INLINE void GPT12E_T4_Mode_Capture_Sel(void)
selects T4 Capture Mode.
Definition: gpt12e.h:2151
GPT12E_T2_Mode_Counter_Input_Rising_T2In_Dis
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:543
GPT12E_PISEL_IST6IN_Msk
#define GPT12E_PISEL_IST6IN_Msk
Definition: tle986x.h:7864
GPT12E_T4_Mode_Counter_Input_Rising_T4In_Dis
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2279
GPT12E_T4_Int_Sts
INLINE uint8 GPT12E_T4_Int_Sts(void)
reads GPT Module 1 Timer 4 interrupt Status.
Definition: gpt12e.h:4616
GPT12E
#define GPT12E
Definition: tle986x.h:5998
types.h
General type declarations.
GPT12E_T4CON_T4RC_Msk
#define GPT12E_T4CON_T4RC_Msk
Definition: tle986x.h:7934
GPT12E_T3_Int_En
INLINE void GPT12E_T3_Int_En(void)
enables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:4896
GPT12E_T2_Mode_Counter_Input_Falling_T2In_En
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:561
GPT12E_CapRel_Int_Clr
INLINE void GPT12E_CapRel_Int_Clr(void)
clears GPT Module 1 Capture Reload interrupt flag.
Definition: gpt12e.h:4827
GPT12E_T5CON_T5CLR_Msk
#define GPT12E_T5CON_T5CLR_Msk
Definition: tle986x.h:7968
GPT12E_T5_Cleared_On_Capture_En
INLINE void GPT12E_T5_Cleared_On_Capture_En(void)
enables clearing T5 on a Capture Event.
Definition: gpt12e.h:3723
GPT12E_T2_Mode_Reload_Input_Falling_T3Out_Dis
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:939
GPT12E_T2_Mode_Capture_Input_Rising_T2In_En
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:705
GPT12E_T5_Int_Clr
INLINE void GPT12E_T5_Int_Clr(void)
clears GPT Module 2 Timer 5 interrupt flag.
Definition: gpt12e.h:4781
TGPT12E_CAPIN
TGPT12E_CAPIN
This enum lists the GPT12E CAPINx Inputs.
Definition: gpt12e.h:230
GPT12E_T6CON_T6UD_Msk
#define GPT12E_T6CON_T6UD_Msk
Definition: tle986x.h:7982
GPT12E_T4_Mode_Counter_Input_Rising_T3Out_Dis
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2369
GPT12E_T2_Start_by_T3_Dis
INLINE void GPT12E_T2_Start_by_T3_Dis(void)
disables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:1101
GPT12E_T4_Mode_Capture_Input_T4In_Sel
INLINE void GPT12E_T4_Mode_Capture_Input_T4In_Sel(void)
selects T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2423
GPT12E_T6_Value_Get
INLINE uint16 GPT12E_T6_Value_Get(void)
reads Timer T6 Value.
Definition: gpt12e.h:4456
GPT12E_CCU6_T12_CM_CH1
Definition: gpt12e.h:114
GPT12E_T5CON_T5UDE_Pos
#define GPT12E_T5CON_T5UDE_Pos
Definition: tle986x.h:7959
GPT2_fSYS_Div_2
Definition: gpt12e.h:185
GPT12E_T4_Mode_Gated_Timer_High_Sel
INLINE void GPT12E_T4_Mode_Gated_Timer_High_Sel(void)
selects T4 Gated high Mode.
Definition: gpt12e.h:2117
GPT12E_T2_Mode_IncEnc_Dir_Change_Clr
INLINE void GPT12E_T2_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:1296
SCU_GPT12ICLR_T5C_Msk
#define SCU_GPT12ICLR_T5C_Msk
Definition: tle986x.h:8807
GPT12E_T6_Int_Sts
INLINE uint8 GPT12E_T6_Int_Sts(void)
reads GPT Module 2 Timer 6 interrupt Status.
Definition: gpt12e.h:4664
GPT12E_T3CON_T3RDIR_Pos
#define GPT12E_T3CON_T3RDIR_Pos
Definition: tle986x.h:7917
GPT12E_T2_Mode_IncEnc_DownCount_RotDir_Sel
INLINE void GPT12E_T2_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T2 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:1190
GPT12E_T3CON_T3I_Msk
#define GPT12E_T3CON_T3I_Msk
Definition: tle986x.h:7898
GPT12E_CapRel_CAPIn_Sel
INLINE void GPT12E_CapRel_CAPIn_Sel(uint16 iscapin)
selects CAPIN.
Definition: gpt12e.h:4541
GPT12E_T5_Int_Sts
INLINE uint8 GPT12E_T5_Int_Sts(void)
reads GPT Module 2 Timer 5 interrupt Status.
Definition: gpt12e.h:4640
SCU_GPT12ICLR_T3C_Pos
#define SCU_GPT12ICLR_T3C_Pos
Definition: tle986x.h:8810
GPT12E_T6_Mode_Counter_Input_Any_T6In_Sel
INLINE void GPT12E_T6_Mode_Counter_Input_Any_T6In_Sel(void)
selects Any Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4170
GPT1_fSYS_Div_16
Definition: gpt12e.h:99
SCU_GPT12IEN_T2IE_Msk
#define SCU_GPT12IEN_T2IE_Msk
Definition: tle986x.h:8826
GPT12E_T6CON_T6UDE_Msk
#define GPT12E_T6CON_T6UDE_Msk
Definition: tle986x.h:7984
GPT12E_T6_Mode_Timer_Sel
INLINE void GPT12E_T6_Mode_Timer_Sel(void)
selects T6 Timer Mode.
Definition: gpt12e.h:4007
GPT12E_T6EUDA_P11
Definition: gpt12e.h:223
GPT12E_T2_Mode_IncEnc_Edge_Sel
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Sel(void)
selects T2 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:449
GPT12E_T3_Mode_Gated_Timer_High_Sel
INLINE void GPT12E_T3_Mode_Gated_Timer_High_Sel(void)
selects T3 Gated high Mode.
Definition: gpt12e.h:1448
GPT12E_T6_Int_Clr
INLINE void GPT12E_T6_Int_Clr(void)
clears GPT Module 2 Timer 6 interrupt flag.
Definition: gpt12e.h:4804
GPT12E_T6CON_T6R_Msk
#define GPT12E_T6CON_T6R_Msk
Definition: tle986x.h:7980
GPT12E_CapRel_Int_Sts
INLINE uint8 GPT12E_CapRel_Int_Sts(void)
reads GPT Module 1 Capture Reload interrupt Status.
Definition: gpt12e.h:4688
GPT12E_T6_T6EUD_Sel
INLINE void GPT12E_T6_T6EUD_Sel(uint16 ist6eud)
selects Input for T6EUD.
Definition: gpt12e.h:4516
GPT12E_T3INB_CCU6_SEL
Definition: gpt12e.h:146
GPT12E_T2CON_T2UDE_Pos
#define GPT12E_T2CON_T2UDE_Pos
Definition: tle986x.h:7881
TGPT12E_Mode_Timer_Prescaler
TGPT12E_Mode_Timer_Prescaler
This enum lists the GPT12E Mode Timer Prescaler.
Definition: gpt12e.h:241
GPT12E_CCU6_CH1
Definition: gpt12e.h:109
GPT12E_T5_Mode_Counter_Input_T6Out_Sel
INLINE void GPT12E_T5_Mode_Counter_Input_T6Out_Sel(void)
selects T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3411
GPT12E_T2CON_T2I_Pos
#define GPT12E_T2CON_T2I_Pos
Definition: tle986x.h:7873
GPT12E_PISEL_ISCAPIN_Pos
#define GPT12E_PISEL_ISCAPIN_Pos
Definition: tle986x.h:7867
GPT12E_T2_Mode_Capture_Sel
INLINE void GPT12E_T2_Mode_Capture_Sel(void)
selects T2 Capture Mode.
Definition: gpt12e.h:415
GPT12E_T2_Mode_Counter_Input_Falling_T3Out_En
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:651
GPT12E_T2EUDB_P24
Definition: gpt12e.h:137
GPT12E_CCU6_CH0
Definition: gpt12e.h:108
SCU_GPT12IRC_T6_Pos
#define SCU_GPT12IRC_T6_Pos
Definition: tle986x.h:8830
GPT12E_T2_Mode_IncEnc_UpCount_RotDir_Sel
INLINE void GPT12E_T2_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T2 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:1208
GPT12E_CCU6_T12_PM
Definition: gpt12e.h:112
GPT12E_T3CON_BPS1_Pos
#define GPT12E_T3CON_BPS1_Pos
Definition: tle986x.h:7911
GPT12E_T4EUDA_P03
Definition: gpt12e.h:176
GPT12E_T3_Mode_IncEnc_Rot_Sel
INLINE void GPT12E_T3_Mode_IncEnc_Rot_Sel(void)
selects T3 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:1465
GPT12E_T5_Cleared_On_Capture_Dis
INLINE void GPT12E_T5_Cleared_On_Capture_Dis(void)
disables clearing T5 on a Capture Event.
Definition: gpt12e.h:3741
GPT12E_T6CON_T6UD_Pos
#define GPT12E_T6CON_T6UD_Pos
Definition: tle986x.h:7981
GPT12E_T4_T4EUD_Sel
INLINE void GPT12E_T4_T4EUD_Sel(uint16 ist4eud)
selects Input for T4EUD.
Definition: gpt12e.h:3167
GPT12E_T2_Mode_Capture_Input_Falling_T2In_En
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:741
TGPT12E_T3IN
TGPT12E_T3IN
This enum lists the GPT12E T3INx Inputs.
Definition: gpt12e.h:143
GPT12E_T3_Interval_Timer_Setup
bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T3 to be reloaded by T2.
GPT12E_T4_Mode_Capture_Input_Falling_T4In_En
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2477
GPT1_fSYS_Div_8
Definition: gpt12e.h:98
GPT12E_CCU6_T13_PM
Definition: gpt12e.h:116
GPT12E_T5_T5_Pos
#define GPT12E_T5_T5_Pos
Definition: tle986x.h:7948
TGPT12E_T6EUD
TGPT12E_T6EUD
This enum lists the GPT12E T6EUDx Inputs.
Definition: gpt12e.h:221
GPT12E_PISEL_IST5EUD_Pos
#define GPT12E_PISEL_IST5EUD_Pos
Definition: tle986x.h:7861
GPT12E_T4_Mode_Counter_Input_T3Out_Sel
INLINE void GPT12E_T4_Mode_Counter_Input_T3Out_Sel(void)
selects T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2333
GPT12E_T4CON_T4I_Pos
#define GPT12E_T4CON_T4I_Pos
Definition: tle986x.h:7923
GPT12E_T5CON_T5R_Msk
#define GPT12E_T5CON_T5R_Msk
Definition: tle986x.h:7956
GPT12E_T2_Mode_Counter_Input_T3Out_Sel
INLINE void GPT12E_T2_Mode_Counter_Input_T3Out_Sel(void)
selects T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:597
GPT_Clk_Div_1
Definition: gpt12e.h:243
GPT12E_T5_T5EUD_Sel
INLINE void GPT12E_T5_T5EUD_Sel(uint16 ist5eud)
selects Input for T5EUD.
Definition: gpt12e.h:3987
GPT12E_T6_Int_En
INLINE void GPT12E_T6_Int_En(void)
enables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5034
GPT12E_T2_DownCount_Sel
INLINE void GPT12E_T2_DownCount_Sel(void)
selects Timer T2 counts down.
Definition: gpt12e.h:1119
GPT12E_T3_Output_En
INLINE void GPT12E_T3_Output_En(void)
enables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:1717
GPT12E_T4_T4In_Sel
INLINE void GPT12E_T4_T4In_Sel(uint16 ist4in)
selects Input for T4IN.
Definition: gpt12e.h:3147
GPT12E_T5CON_T5I_Pos
#define GPT12E_T5CON_T5I_Pos
Definition: tle986x.h:7951
GPT12E_T2_Int_Sts
INLINE uint8 GPT12E_T2_Int_Sts(void)
reads GPT Module 1 Timer 2 interrupt Status.
Definition: gpt12e.h:4568
GPT12E_T4CON_T4UDE_Msk
#define GPT12E_T4CON_T4UDE_Msk
Definition: tle986x.h:7932
GPT12E_T4_Mode_IncEnc_Any_T3In_Dis
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2711
GPT12E_T3_Mode_Gated_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T3_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t3i)
selects T3 Gated Timer Mode Parameter.
Definition: gpt12e.h:1522
sfr_access.h
SFR low level access library.
GPT12E_T6_Mode_Counter_Sel
INLINE void GPT12E_T6_Mode_Counter_Sel(void)
selects T6 Counter Mode.
Definition: gpt12e.h:4024
TGPT12E_T2EUD
TGPT12E_T2EUD
This enum lists the GPT12E T2EUDx Inputs.
Definition: gpt12e.h:134
GPT12E_CAPREL_CAPREL_Pos
#define GPT12E_CAPREL_CAPREL_Pos
Definition: tle986x.h:7839
SCU_GPT12IRC_CR_Pos
#define SCU_GPT12IRC_CR_Pos
Definition: tle986x.h:8828
GPT12E_T5_Capture_Trig_Rising_CapIn_En
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_En(void)
enables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3554
GPT12E_T4CON_T4R_Pos
#define GPT12E_T4CON_T4R_Pos
Definition: tle986x.h:7927
SCU_GPT12ICLR_T2C_Pos
#define SCU_GPT12ICLR_T2C_Pos
Definition: tle986x.h:8812
GPT12E_T6CON_T6SR_Pos
#define GPT12E_T6CON_T6SR_Pos
Definition: tle986x.h:7993
u16_Field_Rd16
INLINE uint16 u16_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 16-bit field of a 16-bit register.
Definition: sfr_access.h:421
GPT12E_T3CON_T3OE_Pos
#define GPT12E_T3CON_T3OE_Pos
Definition: tle986x.h:7907
GPT12E_T5_Capture_Trig_Any_T3EUD_En
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_En(void)
enables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3686
GPT12E_T3_Mode_Gated_Timer_Low_Sel
INLINE void GPT12E_T3_Mode_Gated_Timer_Low_Sel(void)
selects T3 Gated low Mode.
Definition: gpt12e.h:1431
GPT12E_T5_Value_Get
INLINE uint16 GPT12E_T5_Value_Get(void)
reads Timer T5 Value.
Definition: gpt12e.h:3927
GPT12E_T6_T6_Msk
#define GPT12E_T6_T6_Msk
Definition: tle986x.h:7973
GPT12E_CCU6_T12_CM_CH2
Definition: gpt12e.h:115
GPT12E_PISEL_IST4EUD_Pos
#define GPT12E_PISEL_IST4EUD_Pos
Definition: tle986x.h:7857
SCU_GPT12IEN_CRIE_Msk
#define SCU_GPT12IEN_CRIE_Msk
Definition: tle986x.h:8816
INLINE
#define INLINE
Definition: types.h:134
Field_Mod8
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:346
u1_Field_Rd8
INLINE uint8 u1_Field_Rd8(const volatile uint8 *reg, uint8 pos, uint8 msk)
This function reads a 1-bit field of a 8-bit register.
Definition: sfr_access.h:391
GPT12E_T6INA_P02
Definition: gpt12e.h:214
GPT12E_T5CON_T5R_Pos
#define GPT12E_T5CON_T5R_Pos
Definition: tle986x.h:7955
TGPT12E_T4IN
TGPT12E_T4IN
This enum lists the GPT12E T4INx Inputs.
Definition: gpt12e.h:163
GPT12E_T3_DownCount_Sel
INLINE void GPT12E_T3_DownCount_Sel(void)
selects Timer T3 counts down.
Definition: gpt12e.h:1788
GPT12E_T3_Mode_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T3_Mode_Timer_Clk_Prescaler_Sel(uint16 t3i)
selects T3 Timer Mode Parameter.
Definition: gpt12e.h:1502
GPT12E_T4_T4_Pos
#define GPT12E_T4_T4_Pos
Definition: tle986x.h:7920
GPT12E_T4_Mode_Capture_Input_Falling_T4In_Dis
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2495
GPT12E_T2_Mode_Counter_Input_Rising_T2In_En
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:525
GPT12E_T5CON_T5UD_Msk
#define GPT12E_T5CON_T5UD_Msk
Definition: tle986x.h:7958
GPT12E_T5CON_T5M_Msk
#define GPT12E_T5CON_T5M_Msk
Definition: tle986x.h:7954
GPT12E_T3CON_T3M_Pos
#define GPT12E_T3CON_T3M_Pos
Definition: tle986x.h:7899
GPT12E_T4_Start_by_T3_Dis
INLINE void GPT12E_T4_Start_by_T3_Dis(void)
disables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:2819
GPT12E_T5_Mode_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T5_Mode_Timer_Clk_Prescaler_Sel(uint16 t5i)
selects T5 Timer Mode Parameter.
Definition: gpt12e.h:3301
GPT12E_T5_Capture_Trig_Rising_CapIn_Dis
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_Dis(void)
disables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3573
GPT_Clk_Div_4
Definition: gpt12e.h:245
GPT12E_T4_DownCount_Sel
INLINE void GPT12E_T4_DownCount_Sel(void)
selects Timer T4 counts down.
Definition: gpt12e.h:2837
GPT12E_T2_Mode_Counter_Input_Rising_T3Out_Dis
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:633
GPT12E_T5_Mode_Counter_Input_Rising_T6Out_En
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_En(void)
enables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3429
GPT12E_T5CON_T5RC_Pos
#define GPT12E_T5CON_T5RC_Pos
Definition: tle986x.h:7961
GPT12E_T5CON_T5I_Msk
#define GPT12E_T5CON_T5I_Msk
Definition: tle986x.h:7952
GPT12E_T3_Mode_Counter_Sel
INLINE void GPT12E_T3_Mode_Counter_Sel(void)
selects T3 Counter Mode.
Definition: gpt12e.h:1414
GPT12E_T4_Start
INLINE void GPT12E_T4_Start(void)
starts Timer T4.
Definition: gpt12e.h:2765
GPT12E_T2_Mode_IncEnc_Any_T3EUD_En
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:1011
GPT12E_T4_Mode_IncEnc_Rot_Sel
INLINE void GPT12E_T4_Mode_IncEnc_Rot_Sel(void)
selects T4 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:2168
GPT12E_T4CON_T4CHDIR_Msk
#define GPT12E_T4CON_T4CHDIR_Msk
Definition: tle986x.h:7944
GPT12E_T4_Mode_Reload_Input_Rising_T3Out_Dis
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2639
GPT12E_T4_Mode_Reload_Input_Falling_T4In_En
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2567
GPT12E_T5_DownCount_Sel
INLINE void GPT12E_T5_DownCount_Sel(void)
selects Timer T5 counts down.
Definition: gpt12e.h:3853
GPT12E_T3CON_T3CHDIR_Msk
#define GPT12E_T3CON_T3CHDIR_Msk
Definition: tle986x.h:7916
GPT12E_T3CON_T3OE_Msk
#define GPT12E_T3CON_T3OE_Msk
Definition: tle986x.h:7908
GPT12E_T4_UpDownCount_Ext_Dis
INLINE void GPT12E_T4_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:2890
GPT12E_T2CON_T2UDE_Msk
#define GPT12E_T2CON_T2UDE_Msk
Definition: tle986x.h:7882
GPT12E_T6CON_T6OTL_Pos
#define GPT12E_T6CON_T6OTL_Pos
Definition: tle986x.h:7987
GPT12E_T6_Output_En
INLINE void GPT12E_T6_Output_En(void)
enables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:4311
uint16
unsigned short uint16
16 bit unsigned value
Definition: types.h:140
GPT12E_T4_Mode_Reload_Input_T4In_Sel
INLINE void GPT12E_T4_Mode_Reload_Input_T4In_Sel(void)
selects T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2513
GPT12E_T5CON_T5SC_Pos
#define GPT12E_T5CON_T5SC_Pos
Definition: tle986x.h:7969
GPT12E_T3_T3EUD_Sel
INLINE void GPT12E_T3_T3EUD_Sel(uint16 ist3eud)
selects Input for T3EUD.
Definition: gpt12e.h:2046
GPT12E_T6_Mode_Counter_Input_Falling_T6In_Sel
INLINE void GPT12E_T6_Mode_Counter_Input_Falling_T6In_Sel(void)
selects Falling Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4152
GPT12E_T2_Mode_Reload_Input_Rising_T3Out_En
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:885
GPT12E_T2_Value_Get
INLINE uint16 GPT12E_T2_Value_Get(void)
reads Timer T2 Value.
Definition: gpt12e.h:1317
GPT12E_T4_Int_En
INLINE void GPT12E_T4_Int_En(void)
enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:4942
GPT12E_T4_Mode_Counter_Sel
INLINE void GPT12E_T4_Mode_Counter_Sel(void)
selects T4 Counter Mode.
Definition: gpt12e.h:2083
GPT12E_T5_Int_En
INLINE void GPT12E_T5_Int_En(void)
enables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:4988
GPT12E_T4CON_T4EDGE_Pos
#define GPT12E_T4CON_T4EDGE_Pos
Definition: tle986x.h:7941
GPT12E_T2_UpDownCount_Ext_Dis
INLINE void GPT12E_T2_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:1172
GPT12E_T4CON_CLRT3EN_Pos
#define GPT12E_T4CON_CLRT3EN_Pos
Definition: tle986x.h:7937
SCU_GPT12IEN_T4IE_Pos
#define SCU_GPT12IEN_T4IE_Pos
Definition: tle986x.h:8821
GPT12E_T2CON_T2UD_Msk
#define GPT12E_T2CON_T2UD_Msk
Definition: tle986x.h:7880
GPT12E_T3CON_T3CHDIR_Pos
#define GPT12E_T3CON_T3CHDIR_Pos
Definition: tle986x.h:7915
GPT12E_T4CON_CLRT2EN_Msk
#define GPT12E_T4CON_CLRT2EN_Msk
Definition: tle986x.h:7936
GPT12E_T3_Mode_IncEnc_Edge_Sel
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Sel(void)
selects T3 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:1482
SCU_GPT12ICLR_CRC_Msk
#define SCU_GPT12ICLR_CRC_Msk
Definition: tle986x.h:8803
GPT12E_T4_Value_Set
INLINE void GPT12E_T4_Value_Set(uint16 t4)
sets Timer T4 Value.
Definition: gpt12e.h:3126
GPT12E_T3_T4_CCU6_Sel
INLINE void GPT12E_T3_T4_CCU6_Sel(uint8 gpt)
selects GPT12 TIN3B/TIN4D Input.
Definition: gpt12e.h:310
GPT12E_T2_Mode_Gated_Timer_High_Sel
INLINE void GPT12E_T2_Mode_Gated_Timer_High_Sel(void)
selects T2 Gated high Mode.
Definition: gpt12e.h:381
GPT12E_PISEL_IST4IN_Pos
#define GPT12E_PISEL_IST4IN_Pos
Definition: tle986x.h:7855
GPT12E_T2INB_P14
Definition: gpt12e.h:128
GPT12E_T5CON_T5SC_Msk
#define GPT12E_T5CON_T5SC_Msk
Definition: tle986x.h:7970
GPT12E_T5CON_T5UD_Pos
#define GPT12E_T5CON_T5UD_Pos
Definition: tle986x.h:7957
GPT12E_T3_Mode_Counter_Input_Rising_T3In_Dis
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_Dis(void)
disables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1558
GPT12E_T4_Mode_Counter_Input_Falling_T4In_Dis
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2315
GPT12E_T5_Mode_Gated_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T5_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t5i)
selects T5 Gated Timer Mode Parameter.
Definition: gpt12e.h:3321
GPT12E_PISEL_IST6EUD_Pos
#define GPT12E_PISEL_IST6EUD_Pos
Definition: tle986x.h:7865
GPT12E_T5_Capture_Dis
INLINE void GPT12E_T5_Capture_Dis(void)
disables T5 Capture Mode.
Definition: gpt12e.h:3517
GPT12E_T3CON_T3OTL_Msk
#define GPT12E_T3CON_T3OTL_Msk
Definition: tle986x.h:7910
GPT12E_T3_Mode_Counter_Input_Falling_T3In_En
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_En(void)
enables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1576
GPT12E_T3CON_BPS1_Msk
#define GPT12E_T3CON_BPS1_Msk
Definition: tle986x.h:7912
GPT12E_T4_Mode_Reload_Input_Falling_T4In_Dis
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_Dis(void)
disables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2585
GPT12E_T6CON_BPS2_Pos
#define GPT12E_T6CON_BPS2_Pos
Definition: tle986x.h:7989
SCU_GPT12IEN_T4IE_Msk
#define SCU_GPT12IEN_T4IE_Msk
Definition: tle986x.h:8822
GPT12E_GPT1_Clk_Prescaler_Get
INLINE uint16 GPT12E_GPT1_Clk_Prescaler_Get(void)
reads GPT1 Clock Prescaler.
Definition: gpt12e.h:291
GPT12E_T4INB_CCU6_CH0
Definition: gpt12e.h:166
GPT12E_T6_Output_Dis
INLINE void GPT12E_T6_Output_Dis(void)
disables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:4328
SCU_GPT12ICLR_T4C_Msk
#define SCU_GPT12ICLR_T4C_Msk
Definition: tle986x.h:8809
GPT1_fSYS_Div_32
Definition: gpt12e.h:100
GPT12E_T2_Mode_Capture_Input_T2In_Sel
INLINE void GPT12E_T2_Mode_Capture_Input_T2In_Sel(void)
selects T2In as T2 Capture Mode Input.
Definition: gpt12e.h:687
GPT12E_T3_Mode_Counter_Input_Falling_T3In_Dis
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_Dis(void)
disables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:1594
GPT_Clk_Div_32
Definition: gpt12e.h:248
GPT12E_T6_T6In_Sel
INLINE void GPT12E_T6_T6In_Sel(uint16 ist6in)
selects Input for T6IN.
Definition: gpt12e.h:4496
GPT12E_T6_Reload_En
INLINE void GPT12E_T6_Reload_En(void)
enables T6 Reload Mode.
Definition: gpt12e.h:4187
GPT12E_T3CON_T3OTL_Pos
#define GPT12E_T3CON_T3OTL_Pos
Definition: tle986x.h:7909
GPT12E_T6CON_T6M_Pos
#define GPT12E_T6CON_T6M_Pos
Definition: tle986x.h:7977
GPT12E_T4CON_CLRT2EN_Pos
#define GPT12E_T4CON_CLRT2EN_Pos
Definition: tle986x.h:7935
GPT12E_T4_Int_Dis
INLINE void GPT12E_T4_Int_Dis(void)
enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:4965
GPT12E_T5_Stop
INLINE void GPT12E_T5_Stop(void)
stops Timer T5.
Definition: gpt12e.h:3799
GPT12E_T5_UpCount_Sel
INLINE void GPT12E_T5_UpCount_Sel(void)
selects Timer T5 counts up.
Definition: gpt12e.h:3871
GPT12E_T6_Start
INLINE void GPT12E_T6_Start(void)
starts Timer T6.
Definition: gpt12e.h:4277
GPT12E_T3_Mode_IncEnc_DownCount_RotDir_Sel
INLINE void GPT12E_T3_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T3 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:1859
GPT12E_T2_T2_Msk
#define GPT12E_T2_T2_Msk
Definition: tle986x.h:7871
GPT12E_T5_Start
INLINE void GPT12E_T5_Start(void)
starts Timer T5.
Definition: gpt12e.h:3781
GPT12E_PISEL_IST6EUD_Msk
#define GPT12E_PISEL_IST6EUD_Msk
Definition: tle986x.h:7866
uint8
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
GPT12E_T2CON_T2R_Pos
#define GPT12E_T2CON_T2R_Pos
Definition: tle986x.h:7877
GPT12E_T5INA_P03
Definition: gpt12e.h:196
GPT12E_T5CON_T5CLR_Pos
#define GPT12E_T5CON_T5CLR_Pos
Definition: tle986x.h:7967
GPT12E_T4INA_P00
Definition: gpt12e.h:165
GPT12E_T6_UpDownCount_Ext_Dis
INLINE void GPT12E_T6_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:4435
GPT12E_CCU6_T12_ZM
Definition: gpt12e.h:111
GPT12E_T2_Start_by_T3_En
INLINE void GPT12E_T2_Start_by_T3_En(void)
enables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:1083
GPT12E_CCU6_T13_CM
Definition: gpt12e.h:118
GPT12E_T2_Mode_IncEnc_Any_T3In_En
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:975
GPT12E_T2_Mode_Counter_Input_Falling_T2In_Dis
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:579
GPT12E_T5_Mode_Timer_Sel
INLINE void GPT12E_T5_Mode_Timer_Sel(void)
selects T5 Timer Mode.
Definition: gpt12e.h:3230
GPT12E_T2_T2EUD_Sel
INLINE void GPT12E_T2_T2EUD_Sel(uint16 ist2eud)
selects Input for T2EUD.
Definition: gpt12e.h:1377
GPT12E_T4CON_T4RC_Pos
#define GPT12E_T4CON_T4RC_Pos
Definition: tle986x.h:7933
GPT12E_T6_On_Capture_Cleared_En
INLINE void GPT12E_T6_On_Capture_Cleared_En(void)
enables clearing T6 on a Capture Event.
Definition: gpt12e.h:4242
GPT_Clk_Div_8
Definition: gpt12e.h:246
GPT12E_T4CON_CLRT3EN_Msk
#define GPT12E_T4CON_CLRT3EN_Msk
Definition: tle986x.h:7938
GPT2_fSYS_Div_4
Definition: gpt12e.h:186
GPT12E_T2CON_T2EDGE_Msk
#define GPT12E_T2CON_T2EDGE_Msk
Definition: tle986x.h:7888
GPT12E_PISEL_IST4IN_Msk
#define GPT12E_PISEL_IST4IN_Msk
Definition: tle986x.h:7856
TGPT12E_T2IN
TGPT12E_T2IN
This enum lists the GPT12E T2INx Inputs.
Definition: gpt12e.h:125
GPT12E_PISEL_IST2EUD_Msk
#define GPT12E_PISEL_IST2EUD_Msk
Definition: tle986x.h:7850
GPT12E_T6CON_T6M_Msk
#define GPT12E_T6CON_T6M_Msk
Definition: tle986x.h:7978
SCU_GPT12IRC_T2_Pos
#define SCU_GPT12IRC_T2_Pos
Definition: tle986x.h:8838
GPT12E_T6_On_Capture_Cleared_Dis
INLINE void GPT12E_T6_On_Capture_Cleared_Dis(void)
disables clearing T6 on a Capture Event.
Definition: gpt12e.h:4260
GPT12E_T4_Clr_T2_En
INLINE void GPT12E_T4_Clr_T2_En(void)
Enables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2945
GPT12E_T6_UpCount_Sel
INLINE void GPT12E_T6_UpCount_Sel(void)
selects Timer T6 counts up.
Definition: gpt12e.h:4400
GPT12E_T5_Mode_Counter_Input_Rising_T5In_Sel
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T5In_Sel(void)
selects Rising Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3357
GPT12E_PISEL_IST5EUD_Msk
#define GPT12E_PISEL_IST5EUD_Msk
Definition: tle986x.h:7862
GPT12E_T2_Mode_IncEnc_Edge_Detect_Sts
INLINE uint8 GPT12E_T2_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1231
GPT12E_T5CON_T5M_Pos
#define GPT12E_T5CON_T5M_Pos
Definition: tle986x.h:7953
GPT12E_T2CON_T2RC_Msk
#define GPT12E_T2CON_T2RC_Msk
Definition: tle986x.h:7884
GPT12E_T3CON_T3EDGE_Msk
#define GPT12E_T3CON_T3EDGE_Msk
Definition: tle986x.h:7914
uint32
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
GPT12E_T2_T2_Pos
#define GPT12E_T2_T2_Pos
Definition: tle986x.h:7870
GPT12E_PISEL_IST5IN_Pos
#define GPT12E_PISEL_IST5IN_Pos
Definition: tle986x.h:7859
TGPT12E_CCU6_SEL
TGPT12E_CCU6_SEL
This enum lists the GPT12E CCU6 Selection.
Definition: gpt12e.h:106
GPT12E_T6_Mode_Gated_Timer_High_Sel
INLINE void GPT12E_T6_Mode_Gated_Timer_High_Sel(void)
selects T6 Gated high Mode.
Definition: gpt12e.h:4058
SCU_GPT12IRC_T2_Msk
#define SCU_GPT12IRC_T2_Msk
Definition: tle986x.h:8839
GPT12E_T3_Int_Dis
INLINE void GPT12E_T3_Int_Dis(void)
disables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:4919
GPT12E_T3_Mode_IncEnc_Edge_Detect_Sts
INLINE uint8 GPT12E_T3_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1900
GPT12E_T2_Mode_Reload_Input_Falling_T2In_En
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_En(void)
enables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:831
GPT12E_T4CON_T4M_Msk
#define GPT12E_T4CON_T4M_Msk
Definition: tle986x.h:7926
GPT12E_T2_Mode_IncEnc_Rot_Sel
INLINE void GPT12E_T2_Mode_IncEnc_Rot_Sel(void)
selects T2 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:432
SCU_GPT12IEN_T2IE_Pos
#define SCU_GPT12IEN_T2IE_Pos
Definition: tle986x.h:8825
GPT12E_T6_Mode_Gated_Timer_Low_Sel
INLINE void GPT12E_T6_Mode_Gated_Timer_Low_Sel(void)
selects T6 Gated low Mode.
Definition: gpt12e.h:4041
GPT12E_T5_Int_Dis
INLINE void GPT12E_T5_Int_Dis(void)
disables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:5011
GPT12E_T6CON_BPS2_Msk
#define GPT12E_T6CON_BPS2_Msk
Definition: tle986x.h:7990
GPT12E_CAPIND_T2_T3_T4_READ
Definition: gpt12e.h:235
GPT12E_CapRel_Int_Dis
INLINE void GPT12E_CapRel_Int_Dis(void)
disables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5103
GPT12E_T4_Int_Clr
INLINE void GPT12E_T4_Int_Clr(void)
clears GPT Module 1 Timer 4 interrupt flag.
Definition: gpt12e.h:4758
GPT12E_PISEL_IST2EUD_Pos
#define GPT12E_PISEL_IST2EUD_Pos
Definition: tle986x.h:7849
GPT12E_T2_Mode_Reload_Input_T3Out_Sel
INLINE void GPT12E_T2_Mode_Reload_Input_T3Out_Sel(void)
selects T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:867
TGPT1_Clk_Prescaler
TGPT1_Clk_Prescaler
This enum lists the GPT1 Mode Timer Prescaler.
Definition: gpt12e.h:95
GPT12E_T2_Mode_IncEnc_Any_T3EUD_Dis
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:1029
GPT12E_T5_Mode_Counter_Input_Falling_T6Out_Dis
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_Dis(void)
disables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3483
GPT12E_T2_Mode_IncEnc_Any_T3In_Dis
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:993
GPT12E_T4_Value_Get
INLINE uint16 GPT12E_T4_Value_Get(void)
reads Timer T4 Value.
Definition: gpt12e.h:3107
GPT12E_T2_Mode_Reload_Input_Falling_T2In_Dis
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:849
GPT12E_T3EUDA_P04
Definition: gpt12e.h:156
GPT12E_T2_UpDownCount_Ext_En
INLINE void GPT12E_T2_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:1154
GPT12E_T4_Mode_Counter_Input_Falling_T4In_En
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_En(void)
enables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2297
GPT12E_T4_Mode_Reload_Sel
INLINE void GPT12E_T4_Mode_Reload_Sel(void)
selects T4 Reload Mode.
Definition: gpt12e.h:2134
GPT12E_T3_Int_Clr
INLINE void GPT12E_T3_Int_Clr(void)
clears GPT Module 1 Timer 3 interrupt flag.
Definition: gpt12e.h:4735
GPT12E_PISEL_IST6IN_Pos
#define GPT12E_PISEL_IST6IN_Pos
Definition: tle986x.h:7863
TGPT12E_T3EUD
TGPT12E_T3EUD
This enum lists the GPT12E T3EUDx Inputs.
Definition: gpt12e.h:154
GPT12E_T3CON_T3RDIR_Msk
#define GPT12E_T3CON_T3RDIR_Msk
Definition: tle986x.h:7918
GPT12E_T4_Mode_IncEnc_Edge_Detect_Sts
INLINE uint8 GPT12E_T4_Mode_IncEnc_Edge_Detect_Sts(void)
reads Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:3021
GPT12E_T5_T5In_Sel
INLINE void GPT12E_T5_T5In_Sel(uint16 ist5in)
selects Input for T2IN.
Definition: gpt12e.h:3967
GPT12E_T4CON_T4EDGE_Msk
#define GPT12E_T4CON_T4EDGE_Msk
Definition: tle986x.h:7942
SCU_GPT12IRC_T3_Msk
#define SCU_GPT12IRC_T3_Msk
Definition: tle986x.h:8837
GPT12E_CAPINC_T3_READ
Definition: gpt12e.h:234
GPT12E_T3CON_T3M_Msk
#define GPT12E_T3CON_T3M_Msk
Definition: tle986x.h:7900
GPT12E_T4_Clr_T3_Dis
INLINE void GPT12E_T4_Clr_T3_Dis(void)
Disables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2998
GPT12E_T6_T6_Pos
#define GPT12E_T6_T6_Pos
Definition: tle986x.h:7972
GPT12E_T2CON_T2M_Pos
#define GPT12E_T2CON_T2M_Pos
Definition: tle986x.h:7875
GPT12E_Init
void GPT12E_Init(void)
Initializes the GPT12E module.
GPT12E_T4_Mode_Reload_Input_Falling_T3Out_En
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2657
GPT12E_T2_Mode_Reload_Input_T2In_Sel
INLINE void GPT12E_T2_Mode_Reload_Input_T2In_Sel(void)
selects T2In as T2 Reload Mode Input.
Definition: gpt12e.h:777
GPT12E_T3CON_T3EDGE_Pos
#define GPT12E_T3CON_T3EDGE_Pos
Definition: tle986x.h:7913
GPT12E_T2_Mode_Capture_Input_Falling_T2In_Dis
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_Dis(void)
disables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:759
GPT12E_GPT2_Clk_Prescaler_Get
INLINE uint16 GPT12E_GPT2_Clk_Prescaler_Get(void)
reads GPT2 Block Prescaler.
Definition: gpt12e.h:3210
GPT12E_PISEL_IST5IN_Msk
#define GPT12E_PISEL_IST5IN_Msk
Definition: tle986x.h:7860
GPT12E_PISEL_IST3IN_Msk
#define GPT12E_PISEL_IST3IN_Msk
Definition: tle986x.h:7852
SCU_GPT12IRC_CR_Msk
#define SCU_GPT12IRC_CR_Msk
Definition: tle986x.h:8829
SCU_GPT12IRC_T4_Msk
#define SCU_GPT12IRC_T4_Msk
Definition: tle986x.h:8835
GPT12E_T5_Mode_Counter_Input_Any_T5In_Sel
INLINE void GPT12E_T5_Mode_Counter_Input_Any_T5In_Sel(void)
selects Any Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3393
GPT12E_T4CON_T4R_Msk
#define GPT12E_T4CON_T4R_Msk
Definition: tle986x.h:7928
GPT12E_T4_Mode_IncEnc_Any_T3EUD_Dis
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2747
SCU_GPT12IRC_T5_Msk
#define SCU_GPT12IRC_T5_Msk
Definition: tle986x.h:8833
GPT12E_T3CON_T3UD_Pos
#define GPT12E_T3CON_T3UD_Pos
Definition: tle986x.h:7903
GPT12E_T5_Mode_Counter_Input_T5In_Sel
INLINE void GPT12E_T5_Mode_Counter_Input_T5In_Sel(void)
selects T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3339
GPT12E_T3CON_T3R_Pos
#define GPT12E_T3CON_T3R_Pos
Definition: tle986x.h:7901
GPT12E_T4CON_T4RDIR_Pos
#define GPT12E_T4CON_T4RDIR_Pos
Definition: tle986x.h:7945
GPT12E_T6_Reload_Dis
INLINE void GPT12E_T6_Reload_Dis(void)
disables T6 Reload Mode.
Definition: gpt12e.h:4204
GPT12E_T3_Mode_IncEnc_Any_T3EUD_Dis
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_Dis(void)
disables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1666
GPT12E_T6CON_T6SR_Msk
#define GPT12E_T6CON_T6SR_Msk
Definition: tle986x.h:7994
GPT12E_T6CON_T6I_Msk
#define GPT12E_T6CON_T6I_Msk
Definition: tle986x.h:7976
GPT12E_T5CON_T5RC_Msk
#define GPT12E_T5CON_T5RC_Msk
Definition: tle986x.h:7962
GPT12E_T4_Mode_IncEnc_Dir_Change_Sts
INLINE uint8 GPT12E_T4_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:3065
GPT12E_T6INB_P13
Definition: gpt12e.h:215
u1_Field_Rd16
INLINE uint8 u1_Field_Rd16(const volatile uint16 *reg, uint16 pos, uint16 msk)
This function reads a 1-bit field of a 16-bit register.
Definition: sfr_access.h:396
tle986x.h
CMSIS register HeaderFile.
GPT12E_T2_Int_Dis
INLINE void GPT12E_T2_Int_Dis(void)
disables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:4873
SCU
#define SCU
Definition: tle986x.h:6004
GPT12E_T2_Mode_Reload_Sel
INLINE void GPT12E_T2_Mode_Reload_Sel(void)
selects T2 Reload Mode.
Definition: gpt12e.h:398
SCU_GPT12IEN_T5IE_Msk
#define SCU_GPT12IEN_T5IE_Msk
Definition: tle986x.h:8820
GPT12E_T4_Mode_Reload_Input_Rising_T4In_Dis
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2549
GPT12E_T5_Start_by_T6_Dis
INLINE void GPT12E_T5_Start_by_T6_Dis(void)
disables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:3817
GPT12E_T2EUDA_P02
Definition: gpt12e.h:136
GPT12E_T5_Capture_Trig_Any_T3EUD_Dis
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_Dis(void)
disables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3705
GPT12E_T2_Mode_Reload_Input_Rising_T3Out_Dis
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_Dis(void)
disables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:903
GPT12E_T4CON_T4I_Msk
#define GPT12E_T4CON_T4I_Msk
Definition: tle986x.h:7924
GPT12E_T4_Mode_Counter_Input_Falling_T3Out_En
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2387
GPT12E_T3_Mode_IncEnc_Any_T3In_Dis
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_Dis(void)
disables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1630
GPT12E_T4CON_T4UD_Pos
#define GPT12E_T4CON_T4UD_Pos
Definition: tle986x.h:7929
GPT2_fSYS_Div_16
Definition: gpt12e.h:188
GPT12E_T3_Value_Set
INLINE void GPT12E_T3_Value_Set(uint16 t3)
sets Timer T3 Value.
Definition: gpt12e.h:2005
SCU_GPT12ICLR_T5C_Pos
#define SCU_GPT12ICLR_T5C_Pos
Definition: tle986x.h:8806
GPT12E_PISEL_IST2IN_Msk
#define GPT12E_PISEL_IST2IN_Msk
Definition: tle986x.h:7848
GPT12E_T4_Mode_IncEnc_Any_T3EUD_En
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_En(void)
enables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:2729
GPT12E_T2_T2In_Sel
INLINE void GPT12E_T2_T2In_Sel(uint16 ist2in)
selects Input for T2IN.
Definition: gpt12e.h:1357
GPT12E_T2_Mode_Gated_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T2_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t2i)
selects T2 Gated Timer Mode Parameter.
Definition: gpt12e.h:489
GPT12E_T5_Start_by_T6_En
INLINE void GPT12E_T5_Start_by_T6_En(void)
enables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:3835
GPT12E_T3_T3_Pos
#define GPT12E_T3_T3_Pos
Definition: tle986x.h:7894
SCU_GPT12IEN_T6IE_Pos
#define SCU_GPT12IEN_T6IE_Pos
Definition: tle986x.h:8817
GPT12E_CCU6_CH2
Definition: gpt12e.h:110
TGPT2_Clk_Prescaler
TGPT2_Clk_Prescaler
This enum lists the GPT2 Mode Timer Prescaler.
Definition: gpt12e.h:183
GPT12E_T3_Start
INLINE void GPT12E_T3_Start(void)
starts Timer T3.
Definition: gpt12e.h:1683
GPT12E_T2CON_T2R_Msk
#define GPT12E_T2CON_T2R_Msk
Definition: tle986x.h:7878
SCU_GPT12PISEL_GPT12_Msk
#define SCU_GPT12PISEL_GPT12_Msk
Definition: tle986x.h:8846
GPT12E_T4_Mode_Reload_Input_Rising_T4In_En
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:2531
TGPT12E_T4EUD
TGPT12E_T4EUD
This enum lists the GPT12E T4EUDx Inputs.
Definition: gpt12e.h:174
GPT12E_T2CON_T2RDIR_Pos
#define GPT12E_T2CON_T2RDIR_Pos
Definition: tle986x.h:7891
GPT12E_T6_DownCount_Sel
INLINE void GPT12E_T6_DownCount_Sel(void)
selects Timer T6 counts down.
Definition: gpt12e.h:4382
GPT12E_T3_Mode_IncEnc_Edge_Detect_Clr
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1921
GPT12E_CCU6_ANY_CHx
Definition: gpt12e.h:119
GPT12E_T4_Clr_T3_En
INLINE void GPT12E_T4_Clr_T3_En(void)
Enables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:2981
GPT12E_T4_Mode_Gated_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T4_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t4i)
selects T4 Gated Timer Mode Parameter.
Definition: gpt12e.h:2225
GPT12E_T4_Mode_Counter_Input_Falling_T3Out_Dis
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2405
GPT12E_T4_Mode_Gated_Timer_Low_Sel
INLINE void GPT12E_T4_Mode_Gated_Timer_Low_Sel(void)
selects T4 Gated low Mode.
Definition: gpt12e.h:2100
GPT12E_T4_Mode_IncEnc_Edge_Sel
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Sel(void)
selects T4 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:2185
SCU_GPT12IRC_T5_Pos
#define SCU_GPT12IRC_T5_Pos
Definition: tle986x.h:8832
GPT12E_T2_Mode_IncEnc_Dir_Change_Sts
INLINE uint8 GPT12E_T2_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:1275
GPT12E_T6CON_T6OE_Msk
#define GPT12E_T6CON_T6OE_Msk
Definition: tle986x.h:7986
GPT12E_T3_Mode_IncEnc_Dir_Change_Clr
INLINE void GPT12E_T3_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:1965
GPT12E_T4_Mode_Capture_Input_Rising_T4In_Dis
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_Dis(void)
disables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2459
GPT12E_T6_Mode_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T6_Mode_Timer_Clk_Prescaler_Sel(uint16 t6i)
selects T6 Timer Mode Parameter.
Definition: gpt12e.h:4078
GPT12E_T4CON_T4UDE_Pos
#define GPT12E_T4CON_T4UDE_Pos
Definition: tle986x.h:7931
GPT12E_T5_T5_Msk
#define GPT12E_T5_T5_Msk
Definition: tle986x.h:7949
GPT12E_T2_Mode_Counter_Input_Falling_T3Out_Dis
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:669
GPT12E_T3CON_T3UDE_Msk
#define GPT12E_T3CON_T3UDE_Msk
Definition: tle986x.h:7906
GPT12E_T2_Mode_Reload_Input_Falling_T3Out_En
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_En(void)
enables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:921
GPT12E_T2_Int_En
INLINE void GPT12E_T2_Int_En(void)
enables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:4850
GPT12E_T3IND_MON
Definition: gpt12e.h:148
GPT12E_T2_Int_Clr
INLINE void GPT12E_T2_Int_Clr(void)
clears GPT Module 1 Timer 2 interrupt flag.
Definition: gpt12e.h:4712
GPT_Clk_Div_64
Definition: gpt12e.h:249
GPT12E_T3_Mode_IncEnc_Dir_Change_Sts
INLINE uint8 GPT12E_T3_Mode_IncEnc_Dir_Change_Sts(void)
reads Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:1944
GPT12E_T6_Mode_Gated_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T6_Mode_Gated_Timer_Clk_Prescaler_Sel(uint16 t6i)
selects T6 Gated Timer Mode Parameter.
Definition: gpt12e.h:4098
GPT12E_T6CON_T6CLR_Msk
#define GPT12E_T6CON_T6CLR_Msk
Definition: tle986x.h:7992
GPT12E_T3CON_T3UDE_Pos
#define GPT12E_T3CON_T3UDE_Pos
Definition: tle986x.h:7905
GPT12E_T5_Mode_Counter_Input_Falling_T5In_Sel
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T5In_Sel(void)
selects Falling Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:3375
GPT12E_T4EUDB_P10
Definition: gpt12e.h:177
GPT12E_T6_Reload_Value_Set
INLINE void GPT12E_T6_Reload_Value_Set(uint16 rl)
sets Current T6 Reload Value.
Definition: gpt12e.h:4224
GPT12E_T5_Capture_Trig_Falling_CapIn_En
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_En(void)
enables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3592
GPT12E_T3_UpDownCount_Ext_Dis
INLINE void GPT12E_T3_UpDownCount_Ext_Dis(void)
disables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:1841
GPT12E_T2_Mode_IncEnc_Input_Sel
INLINE void GPT12E_T2_Mode_IncEnc_Input_Sel(void)
selects T2 Incremental Interface Mode Input.
Definition: gpt12e.h:957
GPT12E_CapRel_Int_En
INLINE void GPT12E_CapRel_Int_En(void)
enables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5080
GPT12E_T3CON_T3R_Msk
#define GPT12E_T3CON_T3R_Msk
Definition: tle986x.h:7902
TGPT12E_T5EUD
TGPT12E_T5EUD
This enum lists the GPT12E T5EUDx Inputs.
Definition: gpt12e.h:203
GPT12E_T2_Mode_Reload_Input_Rising_T2In_En
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_En(void)
enables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:795
GPT12E_T3_Int_Sts
INLINE uint8 GPT12E_T3_Int_Sts(void)
reads GPT Module 1 Timer 3 interrupt Status.
Definition: gpt12e.h:4592
GPT12E_T5CON_T5UDE_Msk
#define GPT12E_T5CON_T5UDE_Msk
Definition: tle986x.h:7960
GPT12E_T6CON_T6R_Pos
#define GPT12E_T6CON_T6R_Pos
Definition: tle986x.h:7979
Field_Wrt16
INLINE void Field_Wrt16(volatile uint16 *reg, uint16 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:336
GPT12E_PISEL_IST2IN_Pos
#define GPT12E_PISEL_IST2IN_Pos
Definition: tle986x.h:7847
GPT12E_T4_Mode_Counter_Input_Rising_T3Out_En
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_En(void)
enables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:2351
GPT12E_T3EUDB_P25
Definition: gpt12e.h:157
GPT12E_T2_Mode_Gated_Timer_Low_Sel
INLINE void GPT12E_T2_Mode_Gated_Timer_Low_Sel(void)
selects T2 Gated low Mode.
Definition: gpt12e.h:364
SCU_GPT12ICLR_T4C_Pos
#define SCU_GPT12ICLR_T4C_Pos
Definition: tle986x.h:8808
GPT12E_T2_Value_Set
INLINE void GPT12E_T2_Value_Set(uint16 t2)
sets Timer T2 Value.
Definition: gpt12e.h:1336
GPT12E_PISEL_IST3IN_Pos
#define GPT12E_PISEL_IST3IN_Pos
Definition: tle986x.h:7851
GPT12E_T4_Mode_Counter_Input_Rising_T4In_En
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2261
GPT12E_T4INC_P01
Definition: gpt12e.h:167
GPT12E_T3CON_T3UD_Msk
#define GPT12E_T3CON_T3UD_Msk
Definition: tle986x.h:7904
GPT12E_T2_Start
INLINE void GPT12E_T2_Start(void)
starts Timer T2.
Definition: gpt12e.h:1047
GPT12E_T5_Value_Set
INLINE void GPT12E_T5_Value_Set(uint16 t5)
sets Timer T5 Value.
Definition: gpt12e.h:3946
GPT12E_T5_Capture_Trig_Falling_CapIn_Dis
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_Dis(void)
disables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3611
GPT12E_T5_Capture_Trig_T3In_T3EUD_Sel
INLINE void GPT12E_T5_Capture_Trig_T3In_T3EUD_Sel(void)
selects T3In and/or T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:3629
SCU_GPT12IRC_T4_Pos
#define SCU_GPT12IRC_T4_Pos
Definition: tle986x.h:8834
GPT12E_PISEL_IST3EUD_Msk
#define GPT12E_PISEL_IST3EUD_Msk
Definition: tle986x.h:7854
GPT12E_T5_Capture_Trig_Any_T3In_Dis
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_Dis(void)
disables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:3667
GPT12E_T6_Output_Rst
INLINE void GPT12E_T6_Output_Rst(void)
clears Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:4364
GPT12E_T4IND_CCU6_SEL
Definition: gpt12e.h:168
GPT_Clk_Div_128
Definition: gpt12e.h:250
GPT12E_T4_Mode_Counter_Input_T4In_Sel
INLINE void GPT12E_T4_Mode_Counter_Input_T4In_Sel(void)
selects T4In as T4 Counter Mode Input.
Definition: gpt12e.h:2243
Field_Wrt8
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:331
SCU_GPT12IEN_T6IE_Msk
#define SCU_GPT12IEN_T6IE_Msk
Definition: tle986x.h:8818
GPT12E_T5_Capture_Value_Get
INLINE uint16 GPT12E_T5_Capture_Value_Get(void)
reads Current T5 Capture Value.
Definition: gpt12e.h:3763
SCU_GPT12IEN_T5IE_Pos
#define SCU_GPT12IEN_T5IE_Pos
Definition: tle986x.h:8819
GPT12E_T3_Stop
INLINE void GPT12E_T3_Stop(void)
stops Timer T3.
Definition: gpt12e.h:1700
GPT12E_T3_Value_Get
INLINE uint16 GPT12E_T3_Value_Get(void)
reads Timer T3 Value.
Definition: gpt12e.h:1986
GPT12E_T4_Mode_Timer_Sel
INLINE void GPT12E_T4_Mode_Timer_Sel(void)
selects T4 Timer Mode.
Definition: gpt12e.h:2066
GPT12E_T2CON_T2RDIR_Msk
#define GPT12E_T2CON_T2RDIR_Msk
Definition: tle986x.h:7892
GPT12E_T3_T3In_Sel
INLINE void GPT12E_T3_T3In_Sel(uint16 ist3in)
selects Input for T3IN.
Definition: gpt12e.h:2026
SCU_GPT12ICLR_T6C_Msk
#define SCU_GPT12ICLR_T6C_Msk
Definition: tle986x.h:8805
GPT12E_T3_Mode_IncEnc_Any_T3In_En
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_En(void)
enables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:1612
SCU_GPT12PISEL_GPT12_Pos
#define SCU_GPT12PISEL_GPT12_Pos
Definition: tle986x.h:8845
GPT12E_T5_Mode_Counter_Sel
INLINE void GPT12E_T5_Mode_Counter_Sel(void)
selects T5 Counter Mode.
Definition: gpt12e.h:3247
GPT12E_T2_Mode_Counter_Sel
INLINE void GPT12E_T2_Mode_Counter_Sel(void)
selects T2 Counter Mode.
Definition: gpt12e.h:347
GPT12E_T5_Capture_Trig_CapIn_Sel
INLINE void GPT12E_T5_Capture_Trig_CapIn_Sel(void)
selects CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:3535
GPT12E_T2_Mode_Counter_Input_T2In_Sel
INLINE void GPT12E_T2_Mode_Counter_Input_T2In_Sel(void)
selects T2In as T2 Counter Mode Input.
Definition: gpt12e.h:507
GPT12E_GPT2_Clk_Prescaler_Sel
INLINE void GPT12E_GPT2_Clk_Prescaler_Sel(uint16 bps2)
selects GPT2 Block Prescaler.
Definition: gpt12e.h:3189
GPT12E_T4_Mode_Reload_Input_Falling_T3Out_Dis
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_Dis(void)
disables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2675
SCU_GPT12IEN_CRIE_Pos
#define SCU_GPT12IEN_CRIE_Pos
Definition: tle986x.h:8815
GPT12E_T5_UpDownCount_Ext_En
INLINE void GPT12E_T5_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:3888
GPT12E_PISEL_IST4EUD_Msk
#define GPT12E_PISEL_IST4EUD_Msk
Definition: tle986x.h:7858
GPT12E_T2_Mode_Timer_Clk_Prescaler_Sel
INLINE void GPT12E_T2_Mode_Timer_Clk_Prescaler_Sel(uint16 t2i)
selects T2 Timer Mode Parameter.
Definition: gpt12e.h:469
GPT12E_T2_Mode_IncEnc_Edge_Detect_Clr
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Detect_Clr(void)
clears Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:1252
GPT12E_T5_Mode_Counter_Input_Falling_T6Out_En
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_En(void)
enables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3465
GPT12E_T3_UpDownCount_Ext_En
INLINE void GPT12E_T3_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:1823
GPT12E_T3_Output_Set
INLINE void GPT12E_T3_Output_Set(void)
sets Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:1752
GPT12E_T3_T3_Msk
#define GPT12E_T3_T3_Msk
Definition: tle986x.h:7895
GPT12E_T3INC_P10
Definition: gpt12e.h:147
GPT12E_T6CON_T6UDE_Pos
#define GPT12E_T6CON_T6UDE_Pos
Definition: tle986x.h:7983
GPT12E_T3_Mode_Timer_Sel
INLINE void GPT12E_T3_Mode_Timer_Sel(void)
selects T3 Timer Mode.
Definition: gpt12e.h:1397
SCU_GPT12IEN_T3IE_Pos
#define SCU_GPT12IEN_T3IE_Pos
Definition: tle986x.h:8823
GPT12E_T4_Mode_IncEnc_Dir_Change_Clr
INLINE void GPT12E_T4_Mode_IncEnc_Dir_Change_Clr(void)
clears Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:3086
SCU_GPT12ICLR_T2C_Msk
#define SCU_GPT12ICLR_T2C_Msk
Definition: tle986x.h:8813
GPT12E_T5_Capture_Trig_Any_T3In_En
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_En(void)
enables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:3648
GPT12E_T6_Mode_Counter_Input_Rising_T6In_Sel
INLINE void GPT12E_T6_Mode_Counter_Input_Rising_T6In_Sel(void)
selects Rising Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4134
GPT12E_T2CON_T2EDGE_Pos
#define GPT12E_T2CON_T2EDGE_Pos
Definition: tle986x.h:7887
GPT12E_T6_Mode_Counter_Input_T6In_Sel
INLINE void GPT12E_T6_Mode_Counter_Input_T6In_Sel(void)
selects T6In as T6 Counter Mode Input.
Definition: gpt12e.h:4116
GPT12E_T6_Int_Dis
INLINE void GPT12E_T6_Int_Dis(void)
disables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5057
GPT12E_T4_Mode_IncEnc_UpCount_RotDir_Sel
INLINE void GPT12E_T4_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T4 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:2926
GPT12E_CCU6_T12_CM_CH0
Definition: gpt12e.h:113
TGPT12E_T5IN
TGPT12E_T5IN
This enum lists the GPT12E T5INx Inputs.
Definition: gpt12e.h:194
GPT12E_CAPREL_CAPREL_Msk
#define GPT12E_CAPREL_CAPREL_Msk
Definition: tle986x.h:7840
GPT_Clk_Div_16
Definition: gpt12e.h:247
GPT12E_T4_Mode_Reload_Input_T3Out_Sel
INLINE void GPT12E_T4_Mode_Reload_Input_T3Out_Sel(void)
selects T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:2603
GPT12E_T4_UpDownCount_Ext_En
INLINE void GPT12E_T4_UpDownCount_Ext_En(void)
enables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:2872
GPT12E_T3_Mode_IncEnc_UpCount_RotDir_Sel
INLINE void GPT12E_T3_Mode_IncEnc_UpCount_RotDir_Sel(void)
selects Timer T3 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:1877
GPT12E_T5EUDB_P20
Definition: gpt12e.h:206
GPT12E_T4_Mode_Capture_Input_Rising_T4In_En
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_En(void)
enables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:2441
GPT12E_T5_Mode_Gated_Timer_High_Sel
INLINE void GPT12E_T5_Mode_Gated_Timer_High_Sel(void)
selects T5 Gated high Mode.
Definition: gpt12e.h:3281
GPT12E_T6EUDB_P13
Definition: gpt12e.h:224
GPT2_fSYS_Div_8
Definition: gpt12e.h:187
GPT12E_T5_Mode_Gated_Timer_Low_Sel
INLINE void GPT12E_T5_Mode_Gated_Timer_Low_Sel(void)
selects T5 Gated low Mode.
Definition: gpt12e.h:3264
GPT12E_T4CON_T4M_Pos
#define GPT12E_T4CON_T4M_Pos
Definition: tle986x.h:7925
GPT12E_T4CON_T4UD_Msk
#define GPT12E_T4CON_T4UD_Msk
Definition: tle986x.h:7930
GPT12E_GPT1_Clk_Prescaler_Sel
INLINE void GPT12E_GPT1_Clk_Prescaler_Sel(uint16 bps1)
selects GPT1 Clock Prescaler.
Definition: gpt12e.h:270
SCU_GPT12ICLR_CRC_Pos
#define SCU_GPT12ICLR_CRC_Pos
Definition: tle986x.h:8802
TGPT12E_T6IN
TGPT12E_T6IN
This enum lists the GPT12E T6INx Inputs.
Definition: gpt12e.h:212
GPT12E_T2CON_T2UD_Pos
#define GPT12E_T2CON_T2UD_Pos
Definition: tle986x.h:7879
SCU_GPT12IEN_T3IE_Msk
#define SCU_GPT12IEN_T3IE_Msk
Definition: tle986x.h:8824
GPT12E_T3_UpCount_Sel
INLINE void GPT12E_T3_UpCount_Sel(void)
selects Timer T3 counts up.
Definition: gpt12e.h:1806
GPT12E_T5_Mode_Counter_Input_Rising_T6Out_Dis
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_Dis(void)
disables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:3447
GPT12E_T4_UpCount_Sel
INLINE void GPT12E_T4_UpCount_Sel(void)
selects Timer T4 counts up.
Definition: gpt12e.h:2855
GPT12E_PISEL_IST3EUD_Pos
#define GPT12E_PISEL_IST3EUD_Pos
Definition: tle986x.h:7853
GPT12E_T2_Mode_Reload_Input_Rising_T2In_Dis
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_Dis(void)
disables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:813
GPT1_fSYS_Div_4
Definition: gpt12e.h:97
GPT12E_T5CON_CT3_Msk
#define GPT12E_T5CON_CT3_Msk
Definition: tle986x.h:7964
GPT12E_T5CON_CT3_Pos
#define GPT12E_T5CON_CT3_Pos
Definition: tle986x.h:7963
GPT12E_T4CON_T4RDIR_Msk
#define GPT12E_T4CON_T4RDIR_Msk
Definition: tle986x.h:7946
GPT12E_CAPINA_P01
Definition: gpt12e.h:232
GPT12E_T4_Mode_IncEnc_DownCount_RotDir_Sel
INLINE void GPT12E_T4_Mode_IncEnc_DownCount_RotDir_Sel(void)
selects Timer T4 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:2908