#include <tle986x.h>
◆ BC
◆ BE
[11..11] Baud Rate Error Flag
◆ BECLR
[11..11] Baud Rate Error Flag Clear
◆ bit [1/6]
◆ bit [2/6]
◆ bit [3/6]
◆ bit [4/6]
◆ bit [5/6]
◆ bit [6/6]
◆ BR
◆ BR_VALUE
[15..0] Baud Rate Timer/Reload Register Value
◆ BSY
◆ CIS
[2..2] Slave Mode Clock Input Select: 0b0=Clock input (Port A: P0.3) is selected (SSC1)., 0b1=Clock input (Port B: P0.3) is selected (SSC1)., 0b0=Clock input (Port A: P1.0) is selected (SSC2)., 0b1=Clock input (Port B: P1.0) is selected (SSC2).,
◆ CON
◆ EN
◆ ISRCLR
◆ MIS_0
[0..0] Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=Receiver input (Port A: P1.2) is selected (SSC2)., 0b1=Receiver input (Port B: P2.5) is selected (SSC2).,
◆ MIS_1
[3..3] Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=n/a (SSC2)., 0b1=n/a (SSC2).,
◆ MS
[14..14] Master Select Bit
◆ PE
[10..10] Phase Error Flag
◆ PECLR
[10..10] Phase Error Flag Clear
◆ PISEL
◆ RB
◆ RB_VALUE
[15..0] Receive Data Register Value
◆ RE
[9..9] Receive Error Flag
◆ RECLR
[9..9] Receive Error Flag Clear
◆ reg
(@ 0x00000000) Port Input Select Register, RESET_TYPE_3
(@ 0x00000004) Control Register
(@ 0x00000008) Transmitter Buffer Register
(@ 0x0000000C) Receiver Buffer Register
(@ 0x00000010) Baud Rate Timer Reload Register
(@ 0x00000014) Interrupt Status Register Clear
◆ RESERVED
◆ RESERVED1
◆ RESERVED2
◆ RESERVED3
◆ RESERVED4
◆ SIS
[1..1] Slave Mode Receiver Input Select: 0b0=Receiver input (Port A: P0.2) is selected (SSC1)., 0b1=Receiver input (Port B: P0.2) is selected (SSC1)., 0b0=Receiver input (Port A: P1.1) is selected (SSC2)., 0b1=Receiver input (Port B: P1.1) is selected (SSC2).,
◆ TB
◆ TB_VALUE
[15..0] Transmit Data Register Value
◆ TE
[8..8] Transmit Error Flag
◆ TECLR
[8..8] Transmit Error Flag Clear
◆ uint16_t
The documentation for this struct was generated from the following file: