TLE986x Device Family SDK
tle986x.h
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1 /*
2 ***********************************************************************************************************************
3 *
4 * Copyright (c) 2015, Infineon Technologies AG
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8 * following conditions are met:
9 *
10 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11 * disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14 * following disclaimer in the documentation and/or other materials provided with the distribution.
15 *
16 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17 * products derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** **
43 ** Initials Name **
44 ** ---------------------------------------------------------------------------**
45 ** BG Blandine Guillot **
46 ** JO Julia Ott **
47 *******************************************************************************/
48 
49 /*******************************************************************************
50 ** Revision Control History **
51 ********************************************************************************
52 ** V3.0.5: 2020-01-09, BG: Initial version of revision history **
53 ** V3.0.6: 2020-09-28, BG: EP-393: Added field ADC2->CTRL2.bit.SEL_TS_COUNT **
54 ** V3.0.7: 2020-10-12, JO: EP-506: remove ARMCC v6 Compiler warnings **
55 ** - Added '#pragma clang diagnostic ignored' **
56 ** to disable compiler warnings (-Wpadded, **
57 ** -Wcovered-switch-default, -Wself-assign) for **
58 ** ARMCC v6 **
59 *******************************************************************************/
60 
71 #ifndef TLE986x_H
72 #define TLE986x_H
73 
74 #ifdef __cplusplus
75 extern "C" {
76 #endif
77 
78 
85 /* =========================================================================================================================== */
86 /* ================ Interrupt Number Definition ================ */
87 /* =========================================================================================================================== */
88 
89 typedef enum
90 {
91  /* ======================================= ARM Cortex-M3 Specific Interrupt Numbers ======================================== */
92  Reset_IRQn = -15,
94  HardFault_IRQn = -13,
97  BusFault_IRQn = -11,
100  SVCall_IRQn = -5,
102  PendSV_IRQn = -2,
104  /* -------------------- TLE986x Specific Interrupt Numbers -------------------- */
105  GPT1_Int = 0,
106  GPT2_Int = 1,
113  SSC1_Int = 8,
114  SSC2_Int = 9,
118  EXINT1_Int = 13,
119  BDRV_CP_Int = 14,
120  DMA_Int = 15
121 } IRQn_Type;
122 
123 
124 
125 /* =========================================================================================================================== */
126 /* ================ Processor and Core Peripheral Section ================ */
127 /* =========================================================================================================================== */
128 
129 /* =========================== Configuration of the ARM Cortex-M3 Processor and Core Peripherals =========================== */
130 #define __CM3_REV 0x0000U
131 #define __NVIC_PRIO_BITS 4
132 #define __Vendor_SysTickConfig 0
133 #define __MPU_PRESENT 0
134 #define __FPU_PRESENT 0 /* End of group Configuration_of_CMSIS */
138 
139 #include "core_cm3.h"
140 #include "system_tle986x.h"
142 #ifndef __IM
143 #define __IM __I
144 #endif
145 #ifndef __OM
146 #define __OM __O
147 #endif
148 #ifndef __IOM
149 #define __IOM __IO
150 #endif
151 
152 #ifdef UNIT_TESTING_LV2
153 #undef __IM
154 #define __IM volatile
155 #endif
156 
157 /* Ignore the following warnings from ARMCC v6:
158 * - tle987x.h: warning: padding size of 'struct ...' with ... bits to alignment boundary [-Wpadded] (~1000 occurences)
159 */
160 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6000000)
161 #pragma clang diagnostic push
162 #pragma clang diagnostic ignored "-Wpadded"
163 #endif
164 
165 /* =========================================================================================================================== */
166 /* ================ Device Specific Peripheral Section ================ */
167 /* =========================================================================================================================== */
168 
169 
176 /* =========================================================================================================================== */
177 /* ================ ADC1 ================ */
178 /* =========================================================================================================================== */
179 
180 
185 typedef struct
186 {
187 
188  union
189  {
190  __IOM uint32_t reg;
192  struct
193  {
194  __IOM uint32_t PD_N : 1;
196  __IOM uint32_t SOC : 1;
197  __IM uint32_t EOC : 1;
198  __IOM uint32_t IN_MUX_SEL : 3;
199  } bit;
200  } CTRL_STS;
201 
202  union
203  {
204  __IOM uint32_t reg;
206  struct
207  {
208  __IOM uint32_t DIVA : 6;
211  __IM uint32_t : 2;
212  __IOM uint32_t ANON : 2;
213  } bit;
214  } GLOBCTR;
215 
216  union
217  {
218  __IOM uint32_t reg;
221  struct
222  {
223  __IOM uint32_t CHx : 3;
224  __IM uint32_t : 1;
225  __IOM uint32_t REP : 3;
226  __IM uint32_t : 9;
227  __IOM uint32_t TRIG_SEL : 3;
229  } bit;
230  } CHx_EIM;
231 
232  union
233  {
234  __IOM uint32_t reg;
237  struct
238  {
239  __IOM uint32_t ESM_0 : 8;
241  __IM uint32_t : 8;
242  __IOM uint32_t TRIG_SEL : 3;
244  } bit;
245  } CHx_ESM;
246  __IM uint32_t RESERVED[2];
247 
248  union
249  {
250  __IOM uint32_t reg;
253  struct
254  {
255  __IOM uint32_t SQ1 : 8;
256  __IOM uint32_t SQ2 : 8;
257  __IOM uint32_t SQ3 : 8;
258  __IOM uint32_t SQ4 : 8;
259  } bit;
260  } SQ1_4;
261 
262  union
263  {
264  __IOM uint32_t reg;
267  struct
268  {
269  __IOM uint32_t SQ5 : 8;
270  __IOM uint32_t SQ6 : 8;
271  __IOM uint32_t SQ7 : 8;
272  __IOM uint32_t SQ8 : 8;
273  } bit;
274  } SQ5_8;
275  __IM uint32_t RESERVED1;
276 
277  union
278  {
279  __IOM uint32_t reg;
281  struct
282  {
283  __IOM uint32_t ch0 : 1;
284  __IOM uint32_t ch1 : 1;
285  __IOM uint32_t ch2 : 1;
286  __IOM uint32_t ch3 : 1;
287  __IOM uint32_t ch4 : 1;
288  __IOM uint32_t ch5 : 1;
289  __IOM uint32_t ch6 : 1;
290  __IOM uint32_t ch7 : 1;
291  } bit;
292  } DWSEL;
293 
294  union
295  {
296  __IOM uint32_t reg;
298  struct
299  {
300  __IOM uint32_t ch0 : 8;
301  __IOM uint32_t ch1 : 8;
302  __IOM uint32_t ch2 : 8;
303  __IOM uint32_t ch3 : 8;
304  } bit;
305  } STC_0_3;
306 
307  union
308  {
309  __IOM uint32_t reg;
311  struct
312  {
313  __IOM uint32_t ch4 : 8;
314  __IOM uint32_t ch5 : 8;
315  __IOM uint32_t ch6 : 8;
316  __IOM uint32_t ch7 : 8;
317  } bit;
318  } STC_4_7;
319  __IM uint32_t RESERVED2[4];
320 
321  union
322  {
323  __IOM uint32_t reg;
325  struct
326  {
327  __IM uint32_t OUT_CH_EIM : 12;
328  __IM uint32_t : 4;
329  __IOM uint32_t WFR8 : 1;
330  __IM uint32_t VF8 : 1;
331  __IM uint32_t OF8 : 1;
332  } bit;
333  } RES_OUT_EIM;
334  __IM uint32_t RESERVED3[3];
335 
336  union
337  {
338  __IOM uint32_t reg;
340  struct
341  {
342  __IM uint32_t : 8;
343  __IOM uint32_t SQ_RUN : 1;
344  __IM uint32_t EIM_ACTIVE : 1;
345  __IM uint32_t ESM_ACTIVE : 1;
346  __IM uint32_t SQx : 3;
347  __IM uint32_t : 2;
348  __IM uint32_t CHx : 3;
349  } bit;
350  } SQ_FB;
351 
352  union
353  {
354  __IOM uint32_t reg;
356  struct
357  {
358  __IM uint32_t OUT_CH7 : 12;
359  __IM uint32_t : 4;
360  __IOM uint32_t WFR7 : 1;
361  __IM uint32_t VF7 : 1;
362  __IM uint32_t OF7 : 1;
363  } bit;
364  } RES_OUT7;
365 
366  union
367  {
368  __IOM uint32_t reg;
370  struct
371  {
372  __IM uint32_t OUT_CH6 : 12;
373  __IM uint32_t : 4;
374  __IOM uint32_t WFR6 : 1;
375  __IM uint32_t VF6 : 1;
376  __IM uint32_t OF6 : 1;
377  } bit;
378  } RES_OUT6;
379 
380  union
381  {
382  __IOM uint32_t reg;
384  struct
385  {
386  __IM uint32_t OUT_CH5 : 12;
387  __IM uint32_t : 4;
388  __IOM uint32_t WFR5 : 1;
389  __IM uint32_t VF5 : 1;
390  __IM uint32_t OF5 : 1;
391  } bit;
392  } RES_OUT5;
393 
394  union
395  {
396  __IOM uint32_t reg;
398  struct
399  {
400  __IM uint32_t OUT_CH4 : 12;
401  __IM uint32_t : 4;
402  __IOM uint32_t WFR4 : 1;
403  __IM uint32_t VF4 : 1;
404  __IM uint32_t OF4 : 1;
405  } bit;
406  } RES_OUT4;
407 
408  union
409  {
410  __IOM uint32_t reg;
412  struct
413  {
414  __IM uint32_t OUT_CH3 : 12;
415  __IM uint32_t : 4;
416  __IOM uint32_t WFR3 : 1;
417  __IM uint32_t VF3 : 1;
418  __IM uint32_t OF3 : 1;
419  } bit;
420  } RES_OUT3;
421 
422  union
423  {
424  __IOM uint32_t reg;
426  struct
427  {
428  __IM uint32_t OUT_CH2 : 12;
429  __IM uint32_t : 4;
430  __IOM uint32_t WFR2 : 1;
431  __IM uint32_t VF2 : 1;
432  __IM uint32_t OF2 : 1;
433  } bit;
434  } RES_OUT2;
435 
436  union
437  {
438  __IOM uint32_t reg;
440  struct
441  {
442  __IM uint32_t OUT_CH1 : 12;
443  __IM uint32_t : 4;
444  __IOM uint32_t WFR1 : 1;
445  __IM uint32_t VF1 : 1;
446  __IM uint32_t OF1 : 1;
447  } bit;
448  } RES_OUT1;
449 
450  union
451  {
452  __IOM uint32_t reg;
454  struct
455  {
456  __IM uint32_t OUT_CH0 : 12;
457  __IM uint32_t : 4;
458  __IOM uint32_t WFR0 : 1;
459  __IM uint32_t VF0 : 1;
460  __IM uint32_t OF0 : 1;
461  } bit;
462  } RES_OUT0;
463 
464  union
465  {
466  __IOM uint32_t reg;
468  struct
469  {
470  __IM uint32_t BUSY : 1;
471  __IM uint32_t SAMPLE : 1;
472  __IM uint32_t : 1;
473  __IM uint32_t CHNR : 3;
474  __IM uint32_t : 2;
475  __IM uint32_t ANON_ST : 2;
476  } bit;
477  } GLOBSTR;
478 
479  union
480  {
481  __IOM uint32_t reg;
483  struct
484  {
485  __IM uint32_t CH0_STS : 1;
486  __IM uint32_t CH1_STS : 1;
487  __IM uint32_t CH2_STS : 1;
488  __IM uint32_t CH3_STS : 1;
489  __IM uint32_t CH4_STS : 1;
490  __IM uint32_t CH5_STS : 1;
491  __IM uint32_t CH6_STS : 1;
492  __IM uint32_t CH7_STS : 1;
493  __IM uint32_t EIM_STS : 1;
494  __IM uint32_t ESM_STS : 1;
495  } bit;
496  } IS;
497 
498  union
499  {
500  __IOM uint32_t reg;
502  struct
503  {
504  __IOM uint32_t CH0_IE : 1;
505  __IOM uint32_t CH1_IE : 1;
506  __IOM uint32_t CH2_IE : 1;
507  __IOM uint32_t CH3_IE : 1;
508  __IOM uint32_t CH4_IE : 1;
509  __IOM uint32_t CH5_IE : 1;
510  __IOM uint32_t CH6_IE : 1;
511  __IOM uint32_t CH7_IE : 1;
512  __IOM uint32_t EIM_IE : 1;
513  __IOM uint32_t ESM_IE : 1;
514  } bit;
515  } IE;
516 
517  union
518  {
519  __IOM uint32_t reg;
521  struct
522  {
523  __OM uint32_t CH0_ICLR : 1;
524  __OM uint32_t CH1_ICLR : 1;
525  __OM uint32_t CH2_ICLR : 1;
526  __OM uint32_t CH3_ICLR : 1;
527  __OM uint32_t CH4_ICLR : 1;
528  __OM uint32_t CH5_ICLR : 1;
529  __OM uint32_t CH6_ICLR : 1;
530  __OM uint32_t CH7_ICLR : 1;
531  __OM uint32_t EIM_ICLR : 1;
532  __OM uint32_t ESM_ICLR : 1;
533  } bit;
534  } ICLR;
535 } ADC1_Type;
539 /* =========================================================================================================================== */
540 /* ================ ADC2 ================ */
541 /* =========================================================================================================================== */
542 
543 
548 typedef struct
549 {
550 
551  union
552  {
553  __IOM uint32_t reg;
555  struct
556  {
558  __IOM uint32_t VBAT_RANGE : 1;
559  __IOM uint32_t VS_RANGE : 1;
560  } bit;
561  } CTRL_STS;
562 
563  union
564  {
565  __IOM uint32_t reg;
567  struct
568  {
569  __IM uint32_t SQ_FB : 4;
570  __IM uint32_t : 4;
571  __IM uint32_t SQ_STOP : 1;
572  __IM uint32_t EIM_ACTIVE : 1;
573  __IM uint32_t ESM_ACTIVE : 1;
574  __IM uint32_t SQx : 4;
575  __IM uint32_t : 1;
576  __IM uint32_t CHx : 5;
577  } bit;
578  } SQ_FB;
579 
580  union
581  {
582  __IOM uint32_t reg;
585  struct
586  {
587  __IOM uint32_t CHx : 5;
588  __IM uint32_t : 3;
589  __IOM uint32_t REP : 3;
590  __IOM uint32_t EN : 1;
592  __IOM uint32_t SEL : 1;
594  } bit;
595  } CHx_EIM;
596 
597  union
598  {
599  __IOM uint32_t reg;
602  struct
603  {
604  __IOM uint32_t ESM_0 : 6;
606  __IOM uint32_t ESM_1 : 4;
608  __IOM uint32_t SEL : 1;
609  __IM uint32_t : 5;
610  __IOM uint32_t EN : 1;
612  __IM uint32_t STS : 1;
613  } bit;
614  } CHx_ESM;
615  __IM uint32_t RESERVED;
616 
617  union
618  {
619  __IOM uint32_t reg;
621  struct
622  {
623  __IOM uint32_t CALIB_EN : 6;
624  } bit;
625  } CTRL1;
626 
627  union
628  {
629  __IOM uint32_t reg;
631  struct
632  {
633  __IOM uint32_t MCM_PD_N : 1;
634  __IOM uint32_t TS_SD_SEL_CONF : 1;
635  __IOM uint32_t TSENSE_SD_SEL : 1;
636  __IM uint32_t : 4;
637  __IM uint32_t MCM_RDY : 1;
638  __IOM uint32_t SAMPLE_TIME_int : 4;
639  __IM uint32_t : 4;
640  __IOM uint32_t SEL_TS_COUNT : 4;
641  } bit;
642  } CTRL2;
643 
644  union
645  {
646  __IOM uint32_t reg;
648  struct
649  {
650  __IOM uint32_t FILT_OUT_SEL_5_0 : 6;
651  __IM uint32_t : 2;
652  __IOM uint32_t FILT_OUT_SEL_9_6 : 4;
653  } bit;
654  } CTRL4;
655 
656  union
657  {
658  __IOM uint32_t reg;
660  struct
661  {
662  __IOM uint32_t SQ1 : 6;
663  __IM uint32_t : 2;
664  __IOM uint32_t SQ2 : 6;
665  __IM uint32_t : 2;
666  __IOM uint32_t SQ3 : 6;
667  __IM uint32_t : 2;
668  __IOM uint32_t SQ4 : 6;
669  } bit;
670  } SQ1_4;
671 
672  union
673  {
674  __IOM uint32_t reg;
677  struct
678  {
679  __IOM uint32_t SQ5 : 6;
680  __IM uint32_t : 2;
681  __IOM uint32_t SQ6 : 6;
682  __IM uint32_t : 2;
683  __IOM uint32_t SQ7 : 6;
684  __IM uint32_t : 2;
685  __IOM uint32_t SQ8 : 6;
686  } bit;
687  } SQ5_8;
688 
689  union
690  {
691  __IOM uint32_t reg;
694  struct
695  {
696  __IOM uint32_t SQ9 : 6;
697  __IM uint32_t : 2;
698  __IOM uint32_t SQ10 : 6;
699  } bit;
700  } SQ9_10;
701 
702  union
703  {
704  __IOM uint32_t reg;
707  struct
708  {
709  __IM uint32_t SQ1_int : 4;
710  __IM uint32_t SQ2_int : 4;
711  __IM uint32_t SQ3_int : 4;
712  __IM uint32_t SQ4_int : 4;
713  __IM uint32_t SQ5_int : 4;
714  __IM uint32_t SQ6_int : 4;
715  __IM uint32_t SQ7_int : 4;
716  __IM uint32_t SQ8_int : 4;
717  } bit;
718  } SQ1_8_int;
719 
720  union
721  {
722  __IOM uint32_t reg;
725  struct
726  {
727  __IM uint32_t SQ9_int : 4;
728  __IM uint32_t SQ10_int : 4;
729  } bit;
730  } SQ9_10_int;
731 
732  union
733  {
734  __IOM uint32_t reg;
736  struct
737  {
738  __IOM uint32_t OFFS_CH0 : 8;
739  __IOM uint32_t GAIN_CH0 : 8;
740  __IOM uint32_t OFFS_CH1 : 8;
741  __IOM uint32_t GAIN_CH1 : 8;
742  } bit;
743  } CAL_CH0_1;
744 
745  union
746  {
747  __IOM uint32_t reg;
749  struct
750  {
751  __IOM uint32_t OFFS_CH2 : 8;
752  __IOM uint32_t GAIN_CH2 : 8;
753  __IOM uint32_t OFFS_CH3 : 8;
754  __IOM uint32_t GAIN_CH3 : 8;
755  } bit;
756  } CAL_CH2_3;
757 
758  union
759  {
760  __IOM uint32_t reg;
762  struct
763  {
764  __IOM uint32_t OFFS_CH4 : 8;
765  __IOM uint32_t GAIN_CH4 : 8;
766  __IOM uint32_t OFFS_CH5 : 8;
767  __IOM uint32_t GAIN_CH5 : 8;
768  } bit;
769  } CAL_CH4_5;
770 
771  union
772  {
773  __IOM uint32_t reg;
775  struct
776  {
777  __IM uint32_t OFFS_CH6 : 8;
778  __IM uint32_t GAIN_CH6 : 8;
779  __IM uint32_t OFFS_CH7 : 8;
780  __IM uint32_t GAIN_CH7 : 8;
781  } bit;
782  } CAL_CH6_7;
783 
784  union
785  {
786  __IOM uint32_t reg;
788  struct
789  {
790  __IM uint32_t OFFS_CH8 : 8;
791  __IM uint32_t GAIN_CH8 : 8;
792  __IM uint32_t OFFS_CH9 : 8;
793  __IM uint32_t GAIN_CH9 : 8;
794  } bit;
795  } CAL_CH8_9;
796 
797  union
798  {
799  __IOM uint32_t reg;
801  struct
802  {
803  __IOM uint32_t CH0 : 2;
804  __IOM uint32_t CH1 : 2;
805  __IOM uint32_t CH2 : 2;
806  __IOM uint32_t CH3 : 2;
807  __IOM uint32_t CH4 : 2;
808  __IOM uint32_t CH5 : 2;
809  } bit;
810  } FILTCOEFF0_5;
811 
812  union
813  {
814  __IOM uint32_t reg;
816  struct
817  {
818  __IM uint32_t CH6 : 2;
819  __IM uint32_t CH7 : 2;
820  __IM uint32_t CH8 : 2;
821  __IM uint32_t CH9 : 2;
822  } bit;
823  } FILTCOEFF6_9;
824 
825  union
826  {
827  __IOM uint32_t reg;
829  struct
830  {
831  __IM uint32_t OUT_CH0 : 10;
832  } bit;
833  } FILT_OUT0;
834 
835  union
836  {
837  __IOM uint32_t reg;
839  struct
840  {
841  __IM uint32_t OUT_CH1 : 10;
842  } bit;
843  } FILT_OUT1;
844 
845  union
846  {
847  __IOM uint32_t reg;
849  struct
850  {
851  __IM uint32_t OUT_CH2 : 10;
852  } bit;
853  } FILT_OUT2;
854 
855  union
856  {
857  __IOM uint32_t reg;
859  struct
860  {
861  __IM uint32_t OUT_CH3 : 10;
862  } bit;
863  } FILT_OUT3;
864 
865  union
866  {
867  __IOM uint32_t reg;
869  struct
870  {
871  __IM uint32_t OUT_CH4 : 10;
872  } bit;
873  } FILT_OUT4;
874 
875  union
876  {
877  __IOM uint32_t reg;
879  struct
880  {
881  __IM uint32_t OUT_CH5 : 10;
882  } bit;
883  } FILT_OUT5;
884 
885  union
886  {
887  __IOM uint32_t reg;
889  struct
890  {
891  __IM uint32_t OUT_CH6 : 10;
892  } bit;
893  } FILT_OUT6;
894 
895  union
896  {
897  __IOM uint32_t reg;
899  struct
900  {
901  __IM uint32_t OUT_CH7 : 10;
902  } bit;
903  } FILT_OUT7;
904 
905  union
906  {
907  __IOM uint32_t reg;
909  struct
910  {
911  __IM uint32_t OUT_CH8 : 10;
912  } bit;
913  } FILT_OUT8;
914 
915  union
916  {
917  __IOM uint32_t reg;
919  struct
920  {
921  __IM uint32_t OUT_CH9 : 10;
922  } bit;
923  } FILT_OUT9;
924 
925  union
926  {
927  __IOM uint32_t reg;
929  struct
930  {
931  __IOM uint32_t Ch0_EN : 1;
932  __IOM uint32_t Ch1_EN : 1;
933  __IOM uint32_t Ch2_EN : 1;
934  __IOM uint32_t Ch3_EN : 1;
935  __IOM uint32_t Ch4_EN : 1;
936  __IOM uint32_t Ch5_EN : 1;
937  } bit;
938  } FILT_UP_CTRL;
939 
940  union
941  {
942  __IOM uint32_t reg;
944  struct
945  {
946  __IOM uint32_t Ch0_EN : 1;
947  __IOM uint32_t Ch1_EN : 1;
948  __IOM uint32_t Ch2_EN : 1;
949  __IOM uint32_t Ch3_EN : 1;
950  __IOM uint32_t Ch4_EN : 1;
951  __IOM uint32_t Ch5_EN : 1;
952  } bit;
953  } FILT_LO_CTRL;
954 
955  union
956  {
957  __IOM uint32_t reg;
959  struct
960  {
961  __IOM uint32_t CH0 : 8;
962  __IOM uint32_t CH1 : 8;
963  __IOM uint32_t CH2 : 8;
964  __IOM uint32_t CH3 : 8;
965  } bit;
966  } TH0_3_LOWER;
967 
968  union
969  {
970  __IOM uint32_t reg;
973  struct
974  {
975  __IOM uint32_t CH4 : 8;
976  __IOM uint32_t CH5 : 8;
977  } bit;
978  } TH4_5_LOWER;
979 
980  union
981  {
982  __IOM uint32_t reg;
984  struct
985  {
986  __IOM uint32_t CH6 : 8;
987  __IM uint32_t CH7 : 8;
988  __IOM uint32_t CH8 : 8;
989  __IOM uint32_t CH9 : 8;
990  } bit;
991  } TH6_9_LOWER;
992 
993  union
994  {
995  __IOM uint32_t reg;
997  struct
998  {
999  __IOM uint32_t CH0 : 8;
1000  __IOM uint32_t CH1 : 8;
1001  __IOM uint32_t CH2 : 8;
1002  __IOM uint32_t CH3 : 8;
1003  } bit;
1004  } TH0_3_UPPER;
1005 
1006  union
1007  {
1008  __IOM uint32_t reg;
1010  struct
1011  {
1012  __IOM uint32_t CH4 : 8;
1013  __IOM uint32_t CH5 : 8;
1014  } bit;
1015  } TH4_5_UPPER;
1016 
1017  union
1018  {
1019  __IOM uint32_t reg;
1021  struct
1022  {
1023  __IM uint32_t CH6 : 8;
1024  __IM uint32_t CH7 : 8;
1025  __IM uint32_t CH8 : 8;
1026  __IM uint32_t CH9 : 8;
1027  } bit;
1028  } TH6_9_UPPER;
1029 
1030  union
1031  {
1032  __IOM uint32_t reg;
1034  struct
1035  {
1036  __IOM uint32_t CNT_LO_CH0 : 3;
1037  __IOM uint32_t HYST_LO_CH0 : 2;
1038  __IM uint32_t : 3;
1039  __IOM uint32_t CNT_LO_CH1 : 3;
1040  __IOM uint32_t HYST_LO_CH1 : 2;
1041  __IM uint32_t : 3;
1042  __IOM uint32_t CNT_LO_CH2 : 3;
1043  __IOM uint32_t HYST_LO_CH2 : 2;
1044  __IM uint32_t : 3;
1045  __IOM uint32_t CNT_LO_CH3 : 3;
1046  __IOM uint32_t HYST_LO_CH3 : 2;
1047  } bit;
1048  } CNT0_3_LOWER;
1049 
1050  union
1051  {
1052  __IOM uint32_t reg;
1054  struct
1055  {
1056  __IOM uint32_t CNT_LO_CH4 : 3;
1057  __IOM uint32_t HYST_LO_CH4 : 2;
1058  __IM uint32_t : 3;
1059  __IOM uint32_t CNT_LO_CH5 : 3;
1060  __IOM uint32_t HYST_LO_CH5 : 2;
1061  } bit;
1062  } CNT4_5_LOWER;
1063 
1064  union
1065  {
1066  __IOM uint32_t reg;
1068  struct
1069  {
1070  __IM uint32_t CNT_LO_CH6 : 3;
1071  __IM uint32_t HYST_LO_CH6 : 2;
1072  __IM uint32_t : 3;
1073  __IM uint32_t CNT_LO_CH7 : 3;
1074  __IM uint32_t HYST_LO_CH7 : 2;
1075  __IM uint32_t : 3;
1076  __IM uint32_t CNT_LO_CH8 : 3;
1077  __IM uint32_t HYST_LO_CH8 : 2;
1078  __IM uint32_t : 3;
1079  __IM uint32_t CNT_LO_CH9 : 3;
1080  __IM uint32_t HYST_LO_CH9 : 2;
1081  } bit;
1082  } CNT6_9_LOWER;
1083 
1084  union
1085  {
1086  __IOM uint32_t reg;
1088  struct
1089  {
1090  __IOM uint32_t CNT_UP_CH0 : 3;
1091  __IOM uint32_t HYST_UP_CH0 : 2;
1092  __IM uint32_t : 3;
1093  __IOM uint32_t CNT_UP_CH1 : 3;
1094  __IOM uint32_t HYST_UP_CH1 : 2;
1095  __IM uint32_t : 3;
1096  __IOM uint32_t CNT_UP_CH2 : 3;
1097  __IOM uint32_t HYST_UP_CH2 : 2;
1098  __IM uint32_t : 3;
1099  __IOM uint32_t CNT_UP_CH3 : 3;
1100  __IOM uint32_t HYST_UP_CH3 : 2;
1101  } bit;
1102  } CNT0_3_UPPER;
1103 
1104  union
1105  {
1106  __IOM uint32_t reg;
1108  struct
1109  {
1110  __IOM uint32_t CNT_UP_CH4 : 3;
1111  __IOM uint32_t HYST_UP_CH4 : 2;
1112  __IM uint32_t : 3;
1113  __IOM uint32_t CNT_UP_CH5 : 3;
1114  __IOM uint32_t HYST_UP_CH5 : 2;
1115  } bit;
1116  } CNT4_5_UPPER;
1117 
1118  union
1119  {
1120  __IOM uint32_t reg;
1122  struct
1123  {
1124  __IM uint32_t CNT_UP_CH6 : 3;
1125  __IM uint32_t HYST_UP_CH6 : 2;
1126  __IM uint32_t : 3;
1127  __IM uint32_t CNT_UP_CH7 : 3;
1128  __IM uint32_t HYST_UP_CH7 : 2;
1129  __IM uint32_t : 3;
1130  __IM uint32_t CNT_UP_CH8 : 3;
1131  __IM uint32_t HYST_UP_CH8 : 2;
1132  __IM uint32_t : 3;
1133  __IM uint32_t CNT_UP_CH9 : 3;
1134  __IM uint32_t HYST_UP_CH9 : 2;
1135  } bit;
1136  } CNT6_9_UPPER;
1137 
1138  union
1139  {
1140  __IOM uint32_t reg;
1142  struct
1143  {
1144  __IOM uint32_t Ch0 : 2;
1145  __IOM uint32_t Ch1 : 2;
1146  __IOM uint32_t Ch2 : 2;
1147  __IOM uint32_t Ch3 : 2;
1148  __IOM uint32_t Ch4 : 2;
1149  __IOM uint32_t Ch5 : 2;
1150  } bit;
1151  } MMODE0_5;
1152  __IM uint32_t RESERVED1[2];
1153 
1154  union
1155  {
1156  __IOM uint32_t reg;
1158  struct
1159  {
1160  __IM uint32_t : 1;
1161  __IM uint32_t READY : 1;
1162  } bit;
1163  } HV_STS;
1164 } ADC2_Type;
1168 /* =========================================================================================================================== */
1169 /* ================ ADC34 ================ */
1170 /* =========================================================================================================================== */
1171 
1172 
1177 typedef struct
1178 {
1179 
1180  union
1181  {
1182  __IOM uint32_t reg;
1184  struct
1185  {
1186  __IOM uint32_t ADC3_EN : 1;
1187  __IOM uint32_t ADC3_OFS_MEAS_EN : 1;
1188  __IOM uint32_t ADC3_SOC : 1;
1191  __IM uint32_t ADC3_EoC_STS : 1;
1192  __IM uint32_t ADC34_DREQ_SEL : 2;
1193  __IM uint32_t : 4;
1194  __IOM uint32_t ADC34_REF_SEL : 1;
1195  __IOM uint32_t ADC3_OSR : 4;
1196  __IOM uint32_t ADC4_EN : 1;
1197  __IOM uint32_t ADC4_OFS_MEAS_EN : 1;
1198  __IOM uint32_t ADC4_SOC : 1;
1200  __IM uint32_t : 1;
1201  __IM uint32_t ADC4_EoC_STS : 1;
1202  __IOM uint32_t ADC34_EoC_CNT : 2;
1203  __IOM uint32_t ADC34_DITHEN : 1;
1204  __IOM uint32_t ADC34_DITHVAL : 4;
1205  __IOM uint32_t ADC4_OSR : 4;
1206  } bit;
1207  } CTRL_STS;
1208 
1209  union
1210  {
1211  __IOM uint32_t reg;
1213  struct
1214  {
1215  __IM uint32_t ADC3_RESU : 16;
1216  __IM uint32_t ADC4_RESU : 16;
1217  } bit;
1218  } RESU;
1219 } ADC34_Type;
1223 /* =========================================================================================================================== */
1224 /* ================ BDRV ================ */
1225 /* =========================================================================================================================== */
1226 
1227 
1232 typedef struct
1233 {
1234 
1235  union
1236  {
1237  __IOM uint32_t reg;
1239  struct
1240  {
1241  __IOM uint32_t LS1_EN : 1;
1242  __IOM uint32_t LS1_PWM : 1;
1243  __IOM uint32_t LS1_ON : 1;
1244  __IOM uint32_t LS1_DCS_EN : 1;
1245  __IM uint32_t LS1_DS_STS : 1;
1246  __IM uint32_t LS1_SUPERR_STS : 1;
1247  __IM uint32_t LS1_OC_STS : 1;
1248  __IOM uint32_t LS1_OC_DIS : 1;
1249  __IOM uint32_t LS2_EN : 1;
1250  __IOM uint32_t LS2_PWM : 1;
1251  __IOM uint32_t LS2_ON : 1;
1252  __IOM uint32_t LS2_DCS_EN : 1;
1253  __IM uint32_t LS2_DS_STS : 1;
1255  __IM uint32_t LS2_SUPERR_STS : 1;
1256  __IM uint32_t LS2_OC_STS : 1;
1257  __IOM uint32_t LS2_OC_DIS : 1;
1258  __IOM uint32_t HS1_EN : 1;
1259  __IOM uint32_t HS1_PWM : 1;
1260  __IOM uint32_t HS1_ON : 1;
1261  __IOM uint32_t HS1_DCS_EN : 1;
1262  __IM uint32_t HS1_DS_STS : 1;
1264  __IM uint32_t HS1_SUPERR_STS : 1;
1265  __IM uint32_t HS1_OC_STS : 1;
1266  __IOM uint32_t HS1_OC_DIS : 1;
1267  __IOM uint32_t HS2_EN : 1;
1268  __IOM uint32_t HS2_PWM : 1;
1269  __IOM uint32_t HS2_ON : 1;
1270  __IOM uint32_t HS2_DCS_EN : 1;
1271  __IM uint32_t HS2_DS_STS : 1;
1273  __IM uint32_t HS2_SUPERR_STS : 1;
1274  __IM uint32_t HS2_OC_STS : 1;
1275  __IOM uint32_t HS2_OC_DIS : 1;
1276  } bit;
1277  } CTRL1;
1278 
1279  union
1280  {
1281  __IOM uint32_t reg;
1283  struct
1284  {
1286  __IM uint32_t DLY_DIAG_TIM : 10;
1287  __OM uint32_t DLY_DIAG_SCLR : 1;
1288  __IM uint32_t DLY_DIAG_STS : 1;
1289  __IOM uint32_t DLY_DIAG_CHSEL : 3;
1290  __IOM uint32_t DLY_DIAG_DIRSEL : 1;
1291  } bit;
1292  } CTRL2;
1293 
1294  union
1295  {
1296  __IOM uint32_t reg;
1298  struct
1299  {
1300  __IOM uint32_t ICHARGE_TRIM : 5;
1301  __IM uint32_t : 1;
1302  __IOM uint32_t ICHARGEDIV2_N : 1;
1303  __IOM uint32_t ON_SEQ_EN : 1;
1304  __IOM uint32_t IDISCHARGE_TRIM : 5;
1305  __IM uint32_t : 1;
1306  __IOM uint32_t IDISCHARGEDIV2_N : 1;
1307  __IOM uint32_t OFF_SEQ_EN : 1;
1308  __IOM uint32_t DSMONVTH : 3;
1310  __IM uint32_t : 5;
1311  __IOM uint32_t DRV_CCP_TIMSEL : 2;
1312  __IOM uint32_t DRV_CCP_DIS : 1;
1313  } bit;
1314  } CTRL3;
1315  __IM uint32_t RESERVED;
1316 
1317  union
1318  {
1319  __IOM uint32_t reg;
1321  struct
1322  {
1323  __IOM uint32_t DRV_OFF_t_4 : 3;
1324  __IOM uint32_t DRV_OFF_I_4 : 5;
1325  __IOM uint32_t DRV_OFF_t_3 : 3;
1326  __IOM uint32_t DRV_OFF_I_3 : 5;
1327  __IOM uint32_t DRV_OFF_t_2 : 3;
1328  __IOM uint32_t DRV_OFF_I_2 : 5;
1329  __IOM uint32_t DRV_OFF_t_1 : 3;
1330  __IOM uint32_t DRV_OFF_I_1 : 5;
1331  } bit;
1332  } OFF_SEQ_CTRL;
1333 
1334  union
1335  {
1336  __IOM uint32_t reg;
1338  struct
1339  {
1340  __IOM uint32_t DRV_ON_t_4 : 3;
1341  __IOM uint32_t DRV_ON_I_4 : 5;
1342  __IOM uint32_t DRV_ON_t_3 : 3;
1343  __IOM uint32_t DRV_ON_I_3 : 5;
1344  __IOM uint32_t DRV_ON_t_2 : 3;
1345  __IOM uint32_t DRV_ON_I_2 : 5;
1346  __IOM uint32_t DRV_ON_t_1 : 3;
1347  __IOM uint32_t DRV_ON_I_1 : 5;
1348  } bit;
1349  } ON_SEQ_CTRL;
1350 
1351  union
1352  {
1353  __IOM uint32_t reg;
1355  struct
1356  {
1357  __IOM uint32_t LS_HS_BT_TFILT_SEL : 2;
1359  __IM uint32_t : 3;
1360  __IOM uint32_t DRV_CCPTIMMUL : 2;
1362  __IM uint32_t : 1;
1363  __IOM uint32_t LSDRV_DS_TFILT_SEL : 2;
1364  __IOM uint32_t LS1DRV_FDISCHG_DIS : 1;
1365  __IOM uint32_t LS2DRV_FDISCHG_DIS : 1;
1366  __IM uint32_t : 1;
1367  __IOM uint32_t LS1DRV_OCSDN_DIS : 1;
1368  __IOM uint32_t LS2DRV_OCSDN_DIS : 1;
1369  __IM uint32_t : 1;
1370  __IOM uint32_t HSDRV_DS_TFILT_SEL : 2;
1372  __IOM uint32_t HS1DRV_FDISCHG_DIS : 1;
1373  __IOM uint32_t HS2DRV_FDISCHG_DIS : 1;
1374  __IM uint32_t : 1;
1375  __IOM uint32_t HS1DRV_OCSDN_DIS : 1;
1376  __IOM uint32_t HS2DRV_OCSDN_DIS : 1;
1377  __IM uint32_t : 1;
1378  __IOM uint32_t CPLOW_TFILT_SEL : 2;
1379  } bit;
1380  } TRIM_DRVx;
1381  __IM uint32_t RESERVED1;
1382 
1383  union
1384  {
1385  __IOM uint32_t reg;
1387  struct
1388  {
1389  __IOM uint32_t CP_EN : 1;
1390  __IM uint32_t : 1;
1391  __IOM uint32_t CP_RDY_EN : 1;
1392  __IM uint32_t : 2;
1393  __IM uint32_t VCP_LOTH2_STS : 1;
1394  __IM uint32_t : 2;
1395  __IOM uint32_t VCP_LOWTH2 : 3;
1397  __IM uint32_t : 5;
1398  __IOM uint32_t DRVx_VCPLO_DIS : 1;
1399  __IM uint32_t VCP_LOTH1_STS : 1;
1400  __IOM uint32_t DRVx_VCPUP_DIS : 1;
1401  __IM uint32_t VCP_UPTH_STS : 1;
1402  __IOM uint32_t DRVx_VSDLO_DIS : 1;
1403  __IM uint32_t VSD_LOTH_STS : 1;
1404  __IOM uint32_t DRVx_VSDUP_DIS : 1;
1405  __IM uint32_t VSD_UPTH_STS : 1;
1406  __IOM uint32_t CPLOPWRM_EN : 1;
1407  __IOM uint32_t VCP9V_SET : 1;
1408  __IOM uint32_t VTHVCP9V_TRIM : 2;
1409  } bit;
1410  } CP_CTRL_STS;
1411 
1412  union
1413  {
1414  __IOM uint32_t reg;
1416  struct
1417  {
1418  __IOM uint32_t DITH_LOWER : 5;
1419  __IM uint32_t : 3;
1420  __IOM uint32_t DITH_UPPER : 5;
1421  __IOM uint32_t F_CP : 2;
1422  __IOM uint32_t CPCLK_EN : 1;
1423  } bit;
1424  } CP_CLK_CTRL;
1425 } BDRV_Type;
1429 /* =========================================================================================================================== */
1430 /* ================ CCU6 ================ */
1431 /* =========================================================================================================================== */
1432 
1433 
1438 typedef struct
1439 {
1440 
1441  union
1442  {
1443  __IOM uint16_t reg;
1445  struct
1446  {
1447  __IM uint16_t CCV : 16;
1448  } bit;
1449  } CC63R;
1450  __IM uint16_t RESERVED;
1451 
1452  union
1453  {
1454  __IOM uint16_t reg;
1456  struct
1457  {
1458  __OM uint16_t T12RR : 1;
1459  __OM uint16_t T12RS : 1;
1460  __OM uint16_t T12RES : 1;
1461  __OM uint16_t DTRES : 1;
1463  __OM uint16_t T12CNT : 1;
1464  __OM uint16_t T12STR : 1;
1465  __OM uint16_t T12STD : 1;
1466  __OM uint16_t T13RR : 1;
1467  __OM uint16_t T13RS : 1;
1468  __OM uint16_t T13RES : 1;
1469  __IM uint16_t : 2;
1470  __OM uint16_t T13CNT : 1;
1471  __OM uint16_t T13STR : 1;
1472  __OM uint16_t T13STD : 1;
1473  } bit;
1474  } TCTR4;
1475  __IM uint16_t RESERVED1;
1476 
1477  union
1478  {
1479  __IOM uint16_t reg;
1481  struct
1482  {
1483  __IOM uint16_t MCMPS : 6;
1484  __IM uint16_t : 1;
1485  __IOM uint16_t STRMCM : 1;
1486  __IOM uint16_t EXPHS : 3;
1487  __IOM uint16_t CURHS : 3;
1488  __IM uint16_t : 1;
1489  __IOM uint16_t STRHP : 1;
1490  } bit;
1491  } MCMOUTS;
1492  __IM uint16_t RESERVED2;
1493 
1494  union
1495  {
1496  __IOM uint16_t reg;
1498  struct
1499  {
1500  __OM uint16_t RCC60R : 1;
1501  __OM uint16_t RCC60F : 1;
1502  __OM uint16_t RCC61R : 1;
1503  __OM uint16_t RCC61F : 1;
1504  __OM uint16_t RCC62R : 1;
1505  __OM uint16_t RCC62F : 1;
1506  __OM uint16_t RT12OM : 1;
1507  __OM uint16_t RT12PM : 1;
1508  __OM uint16_t RT13CM : 1;
1509  __OM uint16_t RT13PM : 1;
1510  __OM uint16_t RTRPF : 1;
1511  __IM uint16_t : 1;
1512  __OM uint16_t RCHE : 1;
1513  __OM uint16_t RWHE : 1;
1514  __OM uint16_t RIDLE : 1;
1515  __OM uint16_t RSTR : 1;
1516  } bit;
1517  } ISR;
1518  __IM uint16_t RESERVED3;
1519 
1520  union
1521  {
1522  __IOM uint16_t reg;
1524  struct
1525  {
1526  __OM uint16_t MCC60S : 1;
1528  __OM uint16_t MCC61S : 1;
1530  __OM uint16_t MCC62S : 1;
1532  __IM uint16_t : 3;
1533  __OM uint16_t MCC63S : 1;
1535  __IM uint16_t : 1;
1536  __OM uint16_t MCC60R : 1;
1538  __OM uint16_t MCC61R : 1;
1540  __OM uint16_t MCC62R : 1;
1542  __IM uint16_t : 3;
1543  __OM uint16_t MCC63R : 1;
1545  } bit;
1546  } CMPMODIF;
1547  __IM uint16_t RESERVED4;
1548 
1549  union
1550  {
1551  __IOM uint16_t reg;
1553  struct
1554  {
1555  __IOM uint16_t CCS : 16;
1556  } bit;
1557  } CC60SR;
1558  __IM uint16_t RESERVED5;
1559 
1560  union
1561  {
1562  __IOM uint16_t reg;
1564  struct
1565  {
1566  __IOM uint16_t CCS : 16;
1567  } bit;
1568  } CC61SR;
1569  __IM uint16_t RESERVED6;
1570 
1571  union
1572  {
1573  __IOM uint16_t reg;
1575  struct
1576  {
1577  __IOM uint16_t CCS : 16;
1578  } bit;
1579  } CC62SR;
1580  __IM uint16_t RESERVED7;
1581 
1582  union
1583  {
1584  __IOM uint16_t reg;
1586  struct
1587  {
1588  __IOM uint16_t CCS : 16;
1589  } bit;
1590  } CC63SR;
1591  __IM uint16_t RESERVED8;
1592 
1593  union
1594  {
1595  __IOM uint16_t reg;
1597  struct
1598  {
1599  __IOM uint16_t T12PV : 16;
1600  } bit;
1601  } T12PR;
1602  __IM uint16_t RESERVED9;
1603 
1604  union
1605  {
1606  __IOM uint16_t reg;
1608  struct
1609  {
1610  __IOM uint16_t T13PV : 16;
1611  } bit;
1612  } T13PR;
1613  __IM uint16_t RESERVED10;
1614 
1615  union
1616  {
1617  __IOM uint16_t reg;
1619  struct
1620  {
1621  __IOM uint16_t DTM : 8;
1622  __IOM uint16_t DTE0 : 1;
1623  __IOM uint16_t DTE1 : 1;
1624  __IOM uint16_t DTE2 : 1;
1625  __IM uint16_t : 1;
1626  __IM uint16_t DTR0 : 1;
1627  __IM uint16_t DTR1 : 1;
1628  __IM uint16_t DTR2 : 1;
1629  } bit;
1630  } T12DTC;
1631  __IM uint16_t RESERVED11;
1632 
1633  union
1634  {
1635  __IOM uint16_t reg;
1637  struct
1638  {
1639  __IOM uint16_t T12CLK : 3;
1640  __IOM uint16_t T12PRE : 1;
1641  __IM uint16_t T12R : 1;
1642  __IM uint16_t STE12 : 1;
1643  __IM uint16_t CDIR : 1;
1644  __IOM uint16_t CTM : 1;
1645  __IOM uint16_t T13CLK : 3;
1646  __IOM uint16_t T13PRE : 1;
1647  __IM uint16_t T13R : 1;
1648  __IM uint16_t STE13 : 1;
1649  } bit;
1650  } TCTR0;
1651  __IM uint16_t RESERVED12;
1652 
1653  union
1654  {
1655  __IOM uint16_t reg;
1657  struct
1658  {
1659  __IM uint16_t CCV : 16;
1660  } bit;
1661  } CC60R;
1662  __IM uint16_t RESERVED13;
1663 
1664  union
1665  {
1666  __IOM uint16_t reg;
1668  struct
1669  {
1670  __IM uint16_t CCV : 16;
1671  } bit;
1672  } CC61R;
1673  __IM uint16_t RESERVED14;
1674 
1675  union
1676  {
1677  __IOM uint16_t reg;
1679  struct
1680  {
1681  __IM uint16_t CCV : 16;
1682  } bit;
1683  } CC62R;
1684  __IM uint16_t RESERVED15;
1685 
1686  union
1687  {
1688  __IOM uint16_t reg;
1690  struct
1691  {
1692  __IOM uint16_t MSEL60 : 4;
1693  __IOM uint16_t MSEL61 : 4;
1694  __IOM uint16_t MSEL62 : 4;
1695  __IOM uint16_t HSYNC : 3;
1696  __IOM uint16_t DBYP : 1;
1697  } bit;
1698  } T12MSEL;
1699  __IM uint16_t RESERVED16;
1700 
1701  union
1702  {
1703  __IOM uint16_t reg;
1705  struct
1706  {
1707  __IOM uint16_t ENCC60R : 1;
1709  __IOM uint16_t ENCC60F : 1;
1711  __IOM uint16_t ENCC61R : 1;
1713  __IOM uint16_t ENCC61F : 1;
1715  __IOM uint16_t ENCC62R : 1;
1717  __IOM uint16_t ENCC62F : 1;
1719  __IOM uint16_t ENT12OM : 1;
1720  __IOM uint16_t ENT12PM : 1;
1721  __IOM uint16_t ENT13CM : 1;
1722  __IOM uint16_t ENT13PM : 1;
1723  __IOM uint16_t ENTRPF : 1;
1724  __IM uint16_t : 1;
1725  __IOM uint16_t ENCHE : 1;
1726  __IOM uint16_t ENWHE : 1;
1727  __IOM uint16_t ENIDLE : 1;
1728  __IOM uint16_t ENSTR : 1;
1729  } bit;
1730  } IEN;
1731  __IM uint16_t RESERVED17;
1732 
1733  union
1734  {
1735  __IOM uint16_t reg;
1737  struct
1738  {
1739  __IOM uint16_t INPCC60 : 2;
1740  __IOM uint16_t INPCC61 : 2;
1741  __IOM uint16_t INPCC62 : 2;
1742  __IOM uint16_t INPCHE : 2;
1743  __IOM uint16_t INPERR : 2;
1744  __IOM uint16_t INPT12 : 2;
1745  __IOM uint16_t INPT13 : 2;
1746  } bit;
1747  } INP;
1748  __IM uint16_t RESERVED18;
1749 
1750  union
1751  {
1752  __IOM uint16_t reg;
1754  struct
1755  {
1756  __OM uint16_t SCC60R : 1;
1757  __OM uint16_t SCC60F : 1;
1758  __OM uint16_t SCC61R : 1;
1759  __OM uint16_t SCC61F : 1;
1760  __OM uint16_t SCC62R : 1;
1761  __OM uint16_t SCC62F : 1;
1762  __OM uint16_t ST12OM : 1;
1763  __OM uint16_t ST12PM : 1;
1764  __OM uint16_t ST13CM : 1;
1765  __OM uint16_t ST13PM : 1;
1766  __OM uint16_t STRPF : 1;
1767  __OM uint16_t SWHC : 1;
1768  __OM uint16_t SCHE : 1;
1769  __OM uint16_t SWHE : 1;
1770  __OM uint16_t SIDLE : 1;
1771  __OM uint16_t SSTR : 1;
1772  } bit;
1773  } ISS;
1774  __IM uint16_t RESERVED19;
1775 
1776  union
1777  {
1778  __IOM uint16_t reg;
1780  struct
1781  {
1782  __IOM uint16_t PSL : 6;
1783  __IM uint16_t : 1;
1784  __IOM uint16_t PSL63 : 1;
1785  } bit;
1786  } PSLR;
1787  __IM uint16_t RESERVED20;
1788 
1789  union
1790  {
1791  __IOM uint16_t reg;
1793  struct
1794  {
1795  __IOM uint16_t SWSEL : 3;
1796  __IM uint16_t : 1;
1797  __IOM uint16_t SWSYN : 2;
1798  __IM uint16_t : 2;
1799  __IOM uint16_t STE12U : 1;
1800  __IOM uint16_t STE12D : 1;
1801  __IOM uint16_t STE13U : 1;
1802  } bit;
1803  } MCMCTR;
1804  __IM uint16_t RESERVED21;
1805 
1806  union
1807  {
1808  __IOM uint16_t reg;
1810  struct
1811  {
1812  __IOM uint16_t T12SSC : 1;
1813  __IOM uint16_t T13SSC : 1;
1814  __IOM uint16_t T13TEC : 3;
1815  __IOM uint16_t T13TED : 2;
1816  __IM uint16_t : 1;
1817  __IOM uint16_t T12RSEL : 2;
1818  __IOM uint16_t T13RSEL : 2;
1819  } bit;
1820  } TCTR2;
1821  __IM uint16_t RESERVED22;
1822 
1823  union
1824  {
1825  __IOM uint16_t reg;
1827  struct
1828  {
1829  __IOM uint16_t T12MODEN : 6;
1830  __IM uint16_t : 1;
1831  __IOM uint16_t MCMEN : 1;
1832  __IOM uint16_t T13MODEN : 6;
1833  __IM uint16_t : 1;
1834  __IOM uint16_t ECT13O : 1;
1835  } bit;
1836  } MODCTR;
1837  __IM uint16_t RESERVED23;
1838 
1839  union
1840  {
1841  __IOM uint16_t reg;
1843  struct
1844  {
1845  __IOM uint16_t TRPM0 : 1;
1846  __IOM uint16_t TRPM1 : 1;
1847  __IOM uint16_t TRPM2 : 1;
1848  __IM uint16_t : 5;
1849  __IOM uint16_t TRPEN : 6;
1850  __IOM uint16_t TRPEN13 : 1;
1851  __IOM uint16_t TRPPEN : 1;
1852  } bit;
1853  } TRPCTR;
1854  __IM uint16_t RESERVED24;
1855 
1856  union
1857  {
1858  __IOM uint16_t reg;
1860  struct
1861  {
1862  __IM uint16_t MCMP : 6;
1863  __IM uint16_t R : 1;
1864  __IM uint16_t : 1;
1865  __IM uint16_t EXPH : 3;
1866  __IM uint16_t CURH : 3;
1867  } bit;
1868  } MCMOUT;
1869  __IM uint16_t RESERVED25;
1870 
1871  union
1872  {
1873  __IOM uint16_t reg;
1875  struct
1876  {
1877  __IM uint16_t ICC60R : 1;
1878  __IM uint16_t ICC60F : 1;
1879  __IM uint16_t ICC61R : 1;
1880  __IM uint16_t ICC61F : 1;
1881  __IM uint16_t ICC62R : 1;
1882  __IM uint16_t ICC62F : 1;
1883  __IM uint16_t T12OM : 1;
1884  __IM uint16_t T12PM : 1;
1885  __IM uint16_t T13CM : 1;
1886  __IM uint16_t T13PM : 1;
1887  __IM uint16_t TRPF : 1;
1888  __IM uint16_t TRPS : 1;
1889  __IM uint16_t CHE : 1;
1890  __IM uint16_t WHE : 1;
1891  __IM uint16_t IDLE : 1;
1892  __IM uint16_t STR : 1;
1893  } bit;
1894  } IS;
1895  __IM uint16_t RESERVED26;
1896 
1897  union
1898  {
1899  __IOM uint16_t reg;
1901  struct
1902  {
1903  __IOM uint16_t ISCC60 : 2;
1904  __IOM uint16_t ISCC61 : 2;
1905  __IOM uint16_t ISCC62 : 2;
1906  __IOM uint16_t ISTRP : 2;
1907  __IOM uint16_t ISPOS0 : 2;
1908  __IOM uint16_t ISPOS1 : 2;
1909  __IOM uint16_t ISPOS2 : 2;
1910  __IOM uint16_t IST12HR : 2;
1911  } bit;
1912  } PISEL0;
1913  __IM uint16_t RESERVED27[3];
1914 
1915  union
1916  {
1917  __IOM uint16_t reg;
1919  struct
1920  {
1921  __IOM uint16_t IST13HR : 2;
1922  __IOM uint16_t ISCNT12 : 2;
1923  __IOM uint16_t ISCNT13 : 2;
1924  __IOM uint16_t T12EXT : 1;
1925  __IOM uint16_t T13EXT : 1;
1926  } bit;
1927  } PISEL2;
1928  __IM uint16_t RESERVED28;
1929 
1930  union
1931  {
1932  __IOM uint16_t reg;
1934  struct
1935  {
1936  __IOM uint16_t T12CV : 16;
1937  } bit;
1938  } T12;
1939  __IM uint16_t RESERVED29;
1940 
1941  union
1942  {
1943  __IOM uint16_t reg;
1945  struct
1946  {
1947  __IOM uint16_t T13CV : 16;
1948  } bit;
1949  } T13;
1950  __IM uint16_t RESERVED30;
1951 
1952  union
1953  {
1954  __IOM uint16_t reg;
1956  struct
1957  {
1958  __IM uint16_t CC60ST : 1;
1959  __IM uint16_t CC61ST : 1;
1960  __IM uint16_t CC62ST : 1;
1961  __IM uint16_t CCPOS0 : 1;
1962  __IM uint16_t CCPOS1 : 1;
1963  __IM uint16_t CCPOS2 : 1;
1964  __IM uint16_t CC63ST : 1;
1965  __IM uint16_t : 1;
1966  __IOM uint16_t CC60PS : 1;
1967  __IOM uint16_t COUT60PS : 1;
1968  __IOM uint16_t CC61PS : 1;
1969  __IOM uint16_t COUT61PS : 1;
1970  __IOM uint16_t CC62PS : 1;
1971  __IOM uint16_t COUT62PS : 1;
1972  __IOM uint16_t COUT63PS : 1;
1973  __IOM uint16_t T13IM : 1;
1974  } bit;
1975  } CMPSTAT;
1976 } CCU6_Type;
1980 /* =========================================================================================================================== */
1981 /* ================ CPU ================ */
1982 /* =========================================================================================================================== */
1983 
1984 
1989 typedef struct
1990 {
1991  __IM uint32_t RESERVED;
1992 
1993  union
1994  {
1995  __IOM uint32_t reg;
1997  struct
1998  {
1999  __IM uint32_t INTLINESNUM : 5;
2000  } bit;
2001  } ICT;
2002  __IM uint32_t RESERVED1[2];
2003 
2004  union
2005  {
2006  __IOM uint32_t reg;
2008  struct
2009  {
2010  __IOM uint32_t ENABLE : 1;
2011  __IOM uint32_t TICKINT : 1;
2012  __IOM uint32_t CLKSOURCE : 1;
2014  __IOM uint32_t COUNTFLAG : 1;
2015  } bit;
2016  } SYSTICK_CS;
2017 
2018  union
2019  {
2020  __IOM uint32_t reg;
2022  struct
2023  {
2024  __IOM uint32_t RELOAD : 24;
2025  } bit;
2026  } SYSTICK_RL;
2027 
2028  union
2029  {
2030  __IOM uint32_t reg;
2032  struct
2033  {
2034  __IOM uint32_t CURRENT : 24;
2035  } bit;
2036  } SYSTICK_CUR;
2037 
2038  union
2039  {
2040  __IOM uint32_t reg;
2042  struct
2043  {
2044  __IM uint32_t TENMS : 24;
2045  __IM uint32_t : 6;
2046  __IM uint32_t SKEW : 1;
2047  __IM uint32_t NOREF : 1;
2048  } bit;
2049  } SYSTICK_CAL;
2050  __IM uint32_t RESERVED2[56];
2051 
2052  union
2053  {
2054  __IOM uint32_t reg;
2056  struct
2057  {
2058  __IOM uint32_t Int_GPT1 : 1;
2059  __IOM uint32_t Int_GPT2 : 1;
2060  __IOM uint32_t Int_ADC2 : 1;
2061  __IOM uint32_t Int_ADC1 : 1;
2062  __IOM uint32_t Int_CCU6SR0 : 1;
2063  __IOM uint32_t Int_CCU6SR1 : 1;
2064  __IOM uint32_t Int_CCU6SR2 : 1;
2065  __IOM uint32_t Int_CCU6SR3 : 1;
2066  __IOM uint32_t Int_SSC1 : 1;
2067  __IOM uint32_t Int_SSC2 : 1;
2068  __IOM uint32_t Int_UART1 : 1;
2069  __IOM uint32_t Int_UART2 : 1;
2070  __IOM uint32_t Int_EXINT0 : 1;
2071  __IOM uint32_t Int_EXINT1 : 1;
2072  __IOM uint32_t Int_BDRV : 1;
2073  __IOM uint32_t Int_DMA : 1;
2074  } bit;
2075  } NVIC_ISER0;
2076  __IM uint32_t RESERVED3[31];
2077 
2078  union
2079  {
2080  __IOM uint32_t reg;
2082  struct
2083  {
2084  __IOM uint32_t Int_GPT1 : 1;
2085  __IOM uint32_t Int_GPT2 : 1;
2086  __IOM uint32_t Int_ADC2 : 1;
2087  __IOM uint32_t Int_ADC1 : 1;
2088  __IOM uint32_t Int_CCU6SR0 : 1;
2089  __IOM uint32_t Int_CCU6SR1 : 1;
2090  __IOM uint32_t Int_CCU6SR2 : 1;
2091  __IOM uint32_t Int_CCU6SR3 : 1;
2092  __IOM uint32_t Int_SSC1 : 1;
2093  __IOM uint32_t Int_SSC2 : 1;
2094  __IOM uint32_t Int_UART1 : 1;
2095  __IOM uint32_t Int_UART2 : 1;
2096  __IOM uint32_t Int_EXINT0 : 1;
2097  __IOM uint32_t Int_EXINT1 : 1;
2098  __IOM uint32_t Int_BDRV : 1;
2099  __IOM uint32_t Int_DMA : 1;
2100  } bit;
2101  } NVIC_ICER0;
2102  __IM uint32_t RESERVED4[31];
2103 
2104  union
2105  {
2106  __IOM uint32_t reg;
2108  struct
2109  {
2110  __IOM uint32_t Int_GPT1 : 1;
2111  __IOM uint32_t Int_GPT2 : 1;
2112  __IOM uint32_t Int_ADC2 : 1;
2113  __IOM uint32_t Int_ADC1 : 1;
2114  __IOM uint32_t Int_CCU6SR0 : 1;
2115  __IOM uint32_t Int_CCU6SR1 : 1;
2116  __IOM uint32_t Int_CCU6SR2 : 1;
2117  __IOM uint32_t Int_CCU6SR3 : 1;
2118  __IOM uint32_t Int_SSC1 : 1;
2119  __IOM uint32_t Int_SSC2 : 1;
2120  __IOM uint32_t Int_UART1 : 1;
2121  __IOM uint32_t Int_UART2 : 1;
2122  __IOM uint32_t Int_EXINT0 : 1;
2123  __IOM uint32_t Int_EXINT1 : 1;
2124  __IOM uint32_t Int_BDRV : 1;
2125  __IOM uint32_t Int_DMA : 1;
2126  } bit;
2127  } NVIC_ISPR0;
2128  __IM uint32_t RESERVED5[31];
2129 
2130  union
2131  {
2132  __IOM uint32_t reg;
2134  struct
2135  {
2136  __IOM uint32_t Int_GPT1 : 1;
2137  __IOM uint32_t Int_GPT2 : 1;
2138  __IOM uint32_t Int_ADC2 : 1;
2139  __IOM uint32_t Int_ADC1 : 1;
2140  __IOM uint32_t Int_CCU6SR0 : 1;
2141  __IOM uint32_t Int_CCU6SR1 : 1;
2142  __IOM uint32_t Int_CCU6SR2 : 1;
2143  __IOM uint32_t Int_CCU6SR3 : 1;
2144  __IOM uint32_t Int_SSC1 : 1;
2145  __IOM uint32_t Int_SSC2 : 1;
2146  __IOM uint32_t Int_UART1 : 1;
2147  __IOM uint32_t Int_UART2 : 1;
2148  __IOM uint32_t Int_EXINT0 : 1;
2149  __IOM uint32_t Int_EXINT1 : 1;
2150  __IOM uint32_t Int_BDRV : 1;
2151  __IOM uint32_t Int_DMA : 1;
2152  } bit;
2153  } NVIC_ICPR0;
2154  __IM uint32_t RESERVED6[31];
2155 
2156  union
2157  {
2158  __IOM uint32_t reg;
2160  struct
2161  {
2162  __IM uint32_t Int_GPT1 : 1;
2163  __IM uint32_t Int_GPT2 : 1;
2164  __IM uint32_t Int_ADC2 : 1;
2165  __IM uint32_t Int_ADC1 : 1;
2166  __IM uint32_t Int_CCU6SR0 : 1;
2167  __IM uint32_t Int_CCU6SR1 : 1;
2168  __IM uint32_t Int_CCU6SR2 : 1;
2169  __IM uint32_t Int_CCU6SR3 : 1;
2170  __IM uint32_t Int_SSC1 : 1;
2171  __IM uint32_t Int_SSC2 : 1;
2172  __IM uint32_t Int_UART1 : 1;
2173  __IM uint32_t Int_UART2 : 1;
2174  __IM uint32_t Int_EXINT0 : 1;
2175  __IM uint32_t Int_EXINT1 : 1;
2176  __IM uint32_t Int_BDRV : 1;
2177  __IM uint32_t Int_DMA : 1;
2178  } bit;
2179  } NVIC_IABR0;
2180  __IM uint32_t RESERVED7[63];
2181 
2182  union
2183  {
2184  __IOM uint32_t reg;
2186  struct
2187  {
2188  __IOM uint32_t PRI_GPT1 : 8;
2189  __IOM uint32_t PRI_GPT2 : 8;
2190  __IOM uint32_t PRI_ADC2 : 8;
2191  __IOM uint32_t PRI_ADC1 : 8;
2192  } bit;
2193  } NVIC_IPR0;
2194 
2195  union
2196  {
2197  __IOM uint32_t reg;
2199  struct
2200  {
2201  __IOM uint32_t PRI_CCU6SR0 : 8;
2202  __IOM uint32_t PRI_CCU6SR1 : 8;
2203  __IOM uint32_t PRI_CCU6SR2 : 8;
2204  __IOM uint32_t PRI_CCU6SR3 : 8;
2205  } bit;
2206  } NVIC_IPR1;
2207 
2208  union
2209  {
2210  __IOM uint32_t reg;
2212  struct
2213  {
2214  __IOM uint32_t PRI_SSC1 : 8;
2215  __IOM uint32_t PRI_SSC2 : 8;
2216  __IOM uint32_t PRI_UART1 : 8;
2217  __IOM uint32_t PRI_UART2 : 8;
2218  } bit;
2219  } NVIC_IPR2;
2220 
2221  union
2222  {
2223  __IOM uint32_t reg;
2225  struct
2226  {
2227  __IOM uint32_t PRI_EXINT0 : 8;
2228  __IOM uint32_t PRI_EXINT1 : 8;
2229  __IOM uint32_t PRI_BDRV : 8;
2230  __IOM uint32_t PRI_DMA : 8;
2231  } bit;
2232  } NVIC_IPR3;
2233  __IM uint32_t RESERVED8[572];
2234 
2235  union
2236  {
2237  __IOM uint32_t reg;
2239  struct
2240  {
2241  __IM uint32_t REVISION : 4;
2242  __IM uint32_t PARTNO : 12;
2243  __IM uint32_t ARCHITECTURE : 4;
2244  __IM uint32_t VARIANT : 4;
2245  __IM uint32_t IMPLEMENTER : 8;
2246  } bit;
2247  } CPUID;
2248 
2249  union
2250  {
2251  __IOM uint32_t reg;
2253  struct
2254  {
2255  __IM uint32_t VECTACTIVE : 9;
2256  __IM uint32_t : 2;
2257  __IM uint32_t RETTOBASE : 1;
2258  __IM uint32_t VECTPENDING : 9;
2259  __IM uint32_t : 1;
2260  __IM uint32_t ISRPENDING : 1;
2261  __IM uint32_t ISRPREEMPT : 1;
2262  __IM uint32_t : 1;
2263  __OM uint32_t PENDSTCLR : 1;
2264  __IOM uint32_t PENDSTSET : 1;
2265  __OM uint32_t PENDSVCLR : 1;
2266  __IOM uint32_t PENDSVSET : 1;
2267  __IM uint32_t : 2;
2268  __IOM uint32_t NMIPENDSET : 1;
2269  } bit;
2270  } ICSR;
2271 
2272  union
2273  {
2274  __IOM uint32_t reg;
2276  struct
2277  {
2278  __IM uint32_t : 7;
2279  __IOM uint32_t TBLOFF : 25;
2280  } bit;
2281  } VTOR;
2282 
2283  union
2284  {
2285  __IOM uint32_t reg;
2287  struct
2288  {
2289  __IOM uint32_t VECTRESET : 1;
2290  __IOM uint32_t VECTCLRACTIVE : 1;
2291  __IOM uint32_t SYSRESETREQ : 1;
2292  __IM uint32_t : 5;
2293  __IOM uint32_t PRIGROUP : 3;
2294  __IM uint32_t : 4;
2295  __IM uint32_t ENDIANNESS : 1;
2296  __IOM uint32_t VECTKEY : 16;
2297  } bit;
2298  } AIRCR;
2299 
2300  union
2301  {
2302  __IOM uint32_t reg;
2304  struct
2305  {
2306  __IM uint32_t : 1;
2307  __IOM uint32_t SLEEPONEXIT : 1;
2308  __IOM uint32_t SLEEPDEEP : 1;
2309  __IM uint32_t : 1;
2310  __IOM uint32_t SEVONPEND : 1;
2311  } bit;
2312  } SCR;
2313 
2314  union
2315  {
2316  __IOM uint32_t reg;
2318  struct
2319  {
2320  __IOM uint32_t NONBASETHRDENA : 1;
2321  __IOM uint32_t USERSETMPEND : 1;
2322  __IM uint32_t : 1;
2323  __IOM uint32_t UNALIGN_TRP : 1;
2324  __IOM uint32_t DIV_0_TRP : 1;
2326  __IM uint32_t : 3;
2327  __IOM uint32_t BFHFMIGN : 1;
2329  __IOM uint32_t STKALIGN : 1;
2330  } bit;
2331  } CCR;
2332 
2333  union
2334  {
2335  __IOM uint32_t reg;
2337  struct
2338  {
2339  __IOM uint32_t PRI_4 : 8;
2340  __IOM uint32_t PRI_5 : 8;
2341  __IOM uint32_t PRI_6 : 8;
2342  __IOM uint32_t PRI_7 : 8;
2343  } bit;
2344  } SHPR1;
2345 
2346  union
2347  {
2348  __IOM uint32_t reg;
2350  struct
2351  {
2352  __IOM uint32_t PRI_8 : 8;
2353  __IOM uint32_t PRI_9 : 8;
2354  __IOM uint32_t PRI_10 : 8;
2355  __IOM uint32_t PRI_11 : 8;
2356  } bit;
2357  } SHPR2;
2358 
2359  union
2360  {
2361  __IOM uint32_t reg;
2363  struct
2364  {
2365  __IOM uint32_t PRI_12 : 8;
2366  __IOM uint32_t PRI_13 : 8;
2367  __IOM uint32_t PRI_14 : 8;
2368  __IOM uint32_t PRI_15 : 8;
2369  } bit;
2370  } SHPR3;
2371 
2372  union
2373  {
2374  __IOM uint32_t reg;
2376  struct
2377  {
2378  __IOM uint32_t MEMFAULTACT : 1;
2379  __IOM uint32_t BUSFAULTACT : 1;
2380  __IM uint32_t : 1;
2381  __IOM uint32_t USGFAULTACT : 1;
2382  __IM uint32_t : 3;
2383  __IOM uint32_t SVCALLACT : 1;
2384  __IOM uint32_t MONITORACT : 1;
2385  __IM uint32_t : 1;
2386  __IOM uint32_t PENDSVACT : 1;
2387  __IOM uint32_t SYSTICKACT : 1;
2388  __IOM uint32_t USGFAULTPENDED : 1;
2389  __IOM uint32_t MEMFAULTPENDED : 1;
2390  __IOM uint32_t BUSFAULTPENDED : 1;
2391  __IOM uint32_t SVCALLPENDED : 1;
2392  __IOM uint32_t MEMFAULTENA : 1;
2393  __IOM uint32_t BUSFAULTENA : 1;
2394  __IOM uint32_t USGFAULTENA : 1;
2395  } bit;
2396  } SHCSR;
2397 
2398  union
2399  {
2400  __IOM uint32_t reg;
2402  struct
2403  {
2404  __IOM uint32_t IACCVIOL : 1;
2405  __IOM uint32_t DACCVIOL : 1;
2406  __IM uint32_t : 1;
2407  __IOM uint32_t MUNSTKERR : 1;
2408  __IOM uint32_t MSTERR : 1;
2409  __IM uint32_t : 2;
2410  __IOM uint32_t MMARVALID : 1;
2411  __IOM uint32_t IBUSERR : 1;
2412  __IOM uint32_t PRECISERR : 1;
2413  __IOM uint32_t IMPRECISERR : 1;
2414  __IOM uint32_t UNSTKERR : 1;
2415  __IOM uint32_t STKERR : 1;
2416  __IM uint32_t : 2;
2417  __IOM uint32_t BFARVALID : 1;
2418  __IOM uint32_t UNDEFINSTR : 1;
2419  __IOM uint32_t INVSTATE : 1;
2420  __IOM uint32_t INVPC : 1;
2421  __IOM uint32_t NOCP : 1;
2422  __IM uint32_t : 4;
2423  __IOM uint32_t UNALIGNED : 1;
2424  __IOM uint32_t DIVBYZERO : 1;
2425  } bit;
2426  } CFSR;
2427 
2428  union
2429  {
2430  __IOM uint32_t reg;
2432  struct
2433  {
2434  __IM uint32_t : 1;
2435  __IOM uint32_t VECTTBL : 1;
2436  __IM uint32_t : 28;
2437  __IOM uint32_t FORCED : 1;
2438  __IOM uint32_t DEBUGEVT : 1;
2439  } bit;
2440  } HFSR;
2441 
2442  union
2443  {
2444  __IOM uint32_t reg;
2446  struct
2447  {
2448  __IOM uint32_t HALTED : 1;
2449  __IOM uint32_t BKPT : 1;
2450  __IOM uint32_t DWTTRAP : 1;
2451  __IOM uint32_t VCATCH : 1;
2452  __IOM uint32_t EXTERNAL : 1;
2453  } bit;
2454  } DFSR;
2455 
2456  union
2457  {
2458  __IOM uint32_t reg;
2460  struct
2461  {
2462  __IOM uint32_t ADDRESS : 32;
2463  } bit;
2464  } MMFAR;
2465 
2466  union
2467  {
2468  __IOM uint32_t reg;
2470  struct
2471  {
2472  __IOM uint32_t ADDRESS : 32;
2473  } bit;
2474  } BFAR;
2475 
2476  union
2477  {
2478  __IOM uint32_t reg;
2480  struct
2481  {
2482  __IOM uint32_t CP0 : 2;
2483  __IOM uint32_t CP1 : 2;
2484  __IOM uint32_t CP2 : 2;
2485  __IOM uint32_t CP3 : 2;
2486  __IOM uint32_t CP4 : 2;
2487  __IOM uint32_t CP5 : 2;
2488  __IOM uint32_t CP6 : 2;
2489  __IOM uint32_t CP7 : 2;
2490  __IM uint32_t : 4;
2491  __IOM uint32_t CP10 : 2;
2492  __IOM uint32_t CP11 : 2;
2493  } bit;
2494  } AFSR;
2495 } CPU_Type;
2499 /* ================================================================================ */
2500 /* ================ CSA ================ */
2501 /* ================================================================================ */
2502 
2503 
2508 typedef struct
2509 {
2510  __I uint32_t RESERVED0[3];
2511 
2512  union
2513  {
2514  __IO uint32_t reg;
2516  struct
2517  {
2518  __IO uint32_t EN : 1;
2519  __IO uint32_t GAIN : 2;
2520  uint32_t : 5;
2521  __IO uint32_t VZERO : 1;
2522  } bit;
2523  } CTRL;
2524 } CSA_Type;
2525 
2526 
2527 /* =========================================================================================================================== */
2528 /* ================ DMA ================ */
2529 /* =========================================================================================================================== */
2530 
2531 
2536 typedef struct
2537 {
2538 
2539  union
2540  {
2541  __IOM uint32_t reg;
2543  struct
2544  {
2545  __IM uint32_t MASTER_ENABLE : 1;
2547  __IM uint32_t STATE : 4;
2548  __IM uint32_t : 8;
2549  __IM uint32_t CHNLS_MINUS1 : 5;
2550  } bit;
2551  } STATUS;
2552 
2553  union
2554  {
2555  __IOM uint32_t reg;
2557  struct
2558  {
2559  __OM uint32_t MASTER_ENABLE : 1;
2560  __IM uint32_t : 4;
2561  __OM uint32_t CHN1_PROT_CTRL : 3;
2562  } bit;
2563  } CFG;
2564 
2565  union
2566  {
2567  __IOM uint32_t reg;
2569  struct
2570  {
2571  __IM uint32_t : 9;
2572  __IOM uint32_t CTRL_BASE_PTR : 23;
2573  } bit;
2574  } CTRL_BASE_PTR;
2575 
2576  union
2577  {
2578  __IOM uint32_t reg;
2580  struct
2581  {
2582  __IM uint32_t ALT_CTRL_BASE_PTR : 32;
2583  } bit;
2584  } ALT_CTRL_BASE_PTR;
2585 
2586  union
2587  {
2588  __IOM uint32_t reg;
2590  struct
2591  {
2592  __IM uint32_t WAITONREQ_STATUS : 14;
2593  } bit;
2594  } WAITONREQ_STATUS;
2595 
2596  union
2597  {
2598  __IOM uint32_t reg;
2600  struct
2601  {
2602  __OM uint32_t CHNL_SW_REQUEST : 14;
2603  } bit;
2604  } CHNL_SW_REQUEST;
2605 
2606  union
2607  {
2608  __IOM uint32_t reg;
2610  struct
2611  {
2612  __IOM uint32_t CHNL_USEBURST_SET : 14;
2621  } bit;
2622  } CHNL_USEBURST_SET;
2623 
2624  union
2625  {
2626  __IOM uint32_t reg;
2628  struct
2629  {
2630  __OM uint32_t CHNL_USEBURST_CLR : 14;
2631  } bit;
2632  } CHNL_USEBURST_CLR;
2633 
2634  union
2635  {
2636  __IOM uint32_t reg;
2638  struct
2639  {
2640  __IOM uint32_t CHNL_REQ_MASK_SET : 14;
2646  } bit;
2647  } CHNL_REQ_MASK_SET;
2648 
2649  union
2650  {
2651  __IOM uint32_t reg;
2653  struct
2654  {
2655  __OM uint32_t CHNL_REQ_MASK_CLR : 14;
2656  } bit;
2657  } CHNL_REQ_MASK_CLR;
2658 
2659  union
2660  {
2661  __IOM uint32_t reg;
2663  struct
2664  {
2665  __IOM uint32_t CHNL_ENABLE_SET : 14;
2669  } bit;
2670  } CHNL_ENABLE_SET;
2671 
2672  union
2673  {
2674  __IOM uint32_t reg;
2676  struct
2677  {
2678  __OM uint32_t CHNL_ENABLE_CLR : 14;
2679  } bit;
2680  } CHNL_ENABLE_CLR;
2681 
2682  union
2683  {
2684  __IOM uint32_t reg;
2686  struct
2687  {
2688  __IOM uint32_t CHNL_PRI_ALT_SET : 14;
2694  } bit;
2695  } CHNL_PRI_ALT_SET;
2696 
2697  union
2698  {
2699  __IOM uint32_t reg;
2701  struct
2702  {
2703  __OM uint32_t CHNL_PRI_ALT_CLR : 14;
2704  } bit;
2705  } CHNL_PRI_ALT_CLR;
2706 
2707  union
2708  {
2709  __IOM uint32_t reg;
2711  struct
2712  {
2713  __IOM uint32_t CHNL_PRIORITY_SET : 14;
2719  } bit;
2720  } CHNL_PRIORITY_SET;
2721 
2722  union
2723  {
2724  __IOM uint32_t reg;
2726  struct
2727  {
2728  __OM uint32_t CHNL_PRIORITY_CLR : 14;
2729  } bit;
2730  } CHNL_PRIORITY_CLR;
2731  __IM uint32_t RESERVED[3];
2732 
2733  union
2734  {
2735  __IOM uint32_t reg;
2737  struct
2738  {
2739  __IOM uint32_t ERR_CLR : 1;
2742  } bit;
2743  } ERR_CLR;
2744 } DMA_Type;
2748 /* =========================================================================================================================== */
2749 /* ================ GPT12E ================ */
2750 /* =========================================================================================================================== */
2751 
2752 
2757 typedef struct
2758 {
2759 
2760  union
2761  {
2762  __IOM uint16_t reg;
2764  struct
2765  {
2766  __IM uint16_t MOD_REV : 8;
2767  __IM uint16_t MOD_TYPE : 8;
2768  } bit;
2769  } ID;
2770  __IM uint16_t RESERVED;
2771 
2772  union
2773  {
2774  __IOM uint16_t reg;
2776  struct
2777  {
2778  __IOM uint16_t IST2IN : 1;
2779  __IOM uint16_t IST2EUD : 1;
2780  __IOM uint16_t IST3IN : 2;
2781  __IOM uint16_t IST3EUD : 2;
2782  __IOM uint16_t IST4IN : 2;
2783  __IOM uint16_t IST4EUD : 2;
2784  __IOM uint16_t IST5IN : 1;
2785  __IOM uint16_t IST5EUD : 1;
2786  __IOM uint16_t IST6IN : 1;
2787  __IOM uint16_t IST6EUD : 1;
2788  __IOM uint16_t ISCAPIN : 2;
2789  } bit;
2790  } PISEL;
2791  __IM uint16_t RESERVED1;
2792 
2793  union
2794  {
2795  __IOM uint16_t reg;
2797  struct
2798  {
2799  __IOM uint16_t T2I : 3;
2800  __IOM uint16_t T2M : 3;
2801  __IOM uint16_t T2R : 1;
2802  __IOM uint16_t T2UD : 1;
2803  __IOM uint16_t T2UDE : 1;
2804  __IOM uint16_t T2RC : 1;
2806  __IOM uint16_t T2IRDIS : 1;
2807  __IOM uint16_t T2EDGE : 1;
2808  __IOM uint16_t T2CHDIR : 1;
2809  __IM uint16_t T2RDIR : 1;
2810  } bit;
2811  } T2CON;
2812  __IM uint16_t RESERVED2;
2813 
2814  union
2815  {
2816  __IOM uint16_t reg;
2818  struct
2819  {
2820  __IOM uint16_t T3I : 3;
2821  __IOM uint16_t T3M : 3;
2822  __IOM uint16_t T3R : 1;
2823  __IOM uint16_t T3UD : 1;
2824  __IOM uint16_t T3UDE : 1;
2825  __IOM uint16_t T3OE : 1;
2826  __IOM uint16_t T3OTL : 1;
2827  __IOM uint16_t BPS1 : 2;
2828  __IOM uint16_t T3EDGE : 1;
2829  __IOM uint16_t T3CHDIR : 1;
2830  __IM uint16_t T3RDIR : 1;
2831  } bit;
2832  } T3CON;
2833  __IM uint16_t RESERVED3;
2834 
2835  union
2836  {
2837  __IOM uint16_t reg;
2839  struct
2840  {
2841  __IOM uint16_t T4I : 3;
2842  __IOM uint16_t T4M : 3;
2843  __IOM uint16_t T4R : 1;
2844  __IOM uint16_t T4UD : 1;
2845  __IOM uint16_t T4UDE : 1;
2846  __IOM uint16_t T4RC : 1;
2847  __IOM uint16_t CLRT2EN : 1;
2848  __IOM uint16_t CLRT3EN : 1;
2849  __IOM uint16_t T4IRDIS : 1;
2850  __IOM uint16_t T4EDGE : 1;
2851  __IOM uint16_t T4CHDIR : 1;
2852  __IM uint16_t T4RDIR : 1;
2853  } bit;
2854  } T4CON;
2855  __IM uint16_t RESERVED4;
2856 
2857  union
2858  {
2859  __IOM uint16_t reg;
2861  struct
2862  {
2863  __IOM uint16_t T5I : 3;
2864  __IOM uint16_t T5M : 2;
2865  __IM uint16_t : 1;
2866  __IOM uint16_t T5R : 1;
2867  __IOM uint16_t T5UD : 1;
2868  __IOM uint16_t T5UDE : 1;
2869  __IOM uint16_t T5RC : 1;
2870  __IOM uint16_t CT3 : 1;
2871  __IM uint16_t : 1;
2872  __IOM uint16_t CI : 2;
2873  __IOM uint16_t T5CLR : 1;
2874  __IOM uint16_t T5SC : 1;
2875  } bit;
2876  } T5CON;
2877  __IM uint16_t RESERVED5;
2878 
2879  union
2880  {
2881  __IOM uint16_t reg;
2883  struct
2884  {
2885  __IOM uint16_t T6I : 3;
2886  __IOM uint16_t T6M : 3;
2887  __IOM uint16_t T6R : 1;
2888  __IOM uint16_t T6UD : 1;
2889  __IOM uint16_t T6UDE : 1;
2890  __IOM uint16_t T6OE : 1;
2891  __IOM uint16_t T6OTL : 1;
2892  __IOM uint16_t BPS2 : 2;
2893  __IM uint16_t : 1;
2894  __IOM uint16_t T6CLR : 1;
2895  __IOM uint16_t T6SR : 1;
2896  } bit;
2897  } T6CON;
2898  __IM uint16_t RESERVED6;
2899 
2900  union
2901  {
2902  __IOM uint16_t reg;
2904  struct
2905  {
2906  __IOM uint16_t CAPREL : 16;
2907  } bit;
2908  } CAPREL;
2909  __IM uint16_t RESERVED7;
2910 
2911  union
2912  {
2913  __IOM uint16_t reg;
2915  struct
2916  {
2917  __IOM uint16_t T2 : 16;
2918  } bit;
2919  } T2;
2920  __IM uint16_t RESERVED8;
2921 
2922  union
2923  {
2924  __IOM uint16_t reg;
2926  struct
2927  {
2928  __IOM uint16_t T3 : 16;
2929  } bit;
2930  } T3;
2931  __IM uint16_t RESERVED9;
2932 
2933  union
2934  {
2935  __IOM uint16_t reg;
2937  struct
2938  {
2939  __IOM uint16_t T4 : 16;
2940  } bit;
2941  } T4;
2942  __IM uint16_t RESERVED10;
2943 
2944  union
2945  {
2946  __IOM uint16_t reg;
2948  struct
2949  {
2950  __IOM uint16_t T5 : 16;
2951  } bit;
2952  } T5;
2953  __IM uint16_t RESERVED11;
2954 
2955  union
2956  {
2957  __IOM uint16_t reg;
2959  struct
2960  {
2961  __IOM uint16_t T6 : 16;
2962  } bit;
2963  } T6;
2964 } GPT12E_Type;
2968 /* =========================================================================================================================== */
2969 /* ================ LIN ================ */
2970 /* =========================================================================================================================== */
2971 
2972 
2977 typedef struct
2978 {
2979 
2980  union
2981  {
2982  __IOM uint32_t reg;
2984  struct
2985  {
2987  __IOM uint32_t MODE : 2;
2988  __IM uint32_t M_SM_ERR : 1;
2989  __IM uint32_t OT_STS : 1;
2990  __IM uint32_t OC_STS : 1;
2991  __IM uint32_t TXD_TMOUT_STS : 1;
2992  __IM uint32_t : 2;
2993  __IOM uint32_t TXD : 1;
2995  __IM uint32_t RXD : 1;
2996  __IOM uint32_t SM : 2;
2997  __IM uint32_t FB_SM1 : 1;
2998  __IM uint32_t FB_SM2 : 1;
2999  __IM uint32_t FB_SM3 : 1;
3000  __IM uint32_t MODE_FB : 3;
3001  __IM uint32_t : 2;
3002  __IOM uint32_t HV_MODE : 1;
3003  __IM uint32_t : 2;
3004  __IOM uint32_t M_SM_ERR_CLR : 1;
3005  } bit;
3006  } CTRL_STS;
3007 } LIN_Type;
3011 /* =========================================================================================================================== */
3012 /* ================ MF ================ */
3013 /* =========================================================================================================================== */
3014 
3015 
3020 typedef struct
3021 {
3022 
3023  union
3024  {
3025  __IOM uint32_t reg;
3027  struct
3028  {
3029  __IOM uint32_t P2_0_ADC_SEL : 1;
3030  __IOM uint32_t P2_2_ADC_SEL : 1;
3031  __IOM uint32_t P2_3_ADC_SEL : 1;
3032  __IOM uint32_t P2_4_ADC_SEL : 1;
3033  __IOM uint32_t P2_5_ADC_SEL : 1;
3034  __IOM uint32_t P2_7_ADC_SEL: 1;
3036  __IOM uint32_t ADC3_INP_SEL : 1;
3037  __IOM uint32_t ADC3_INN_SEL : 1;
3038  __IOM uint32_t ADC1_CH1_SEL : 1;
3039  } bit;
3040  } P2_ADCSEL_CTRL;
3041 
3042  union
3043  {
3044  __IOM uint32_t reg;
3046  struct
3047  {
3048  __IOM uint32_t VMON_SEN_PD_N : 1;
3049  __IM uint32_t : 3;
3050  __IOM uint32_t VMON_SEN_HRESO_5V : 1;
3052  } bit;
3053  } VMON_SEN_CTRL;
3054  __IM uint32_t RESERVED[2];
3055 
3056  union
3057  {
3058  __IOM uint32_t reg;
3060  struct
3061  {
3062  __IM uint32_t : 4;
3063  __IM uint32_t PMU_OTWARN_STS : 1;
3064  __IM uint32_t PMU_OT_STS : 1;
3065  __IM uint32_t SYS_OTWARN_STS : 1;
3066  __IM uint32_t SYS_OT_STS : 1;
3067  } bit;
3068  } TEMPSENSE_CTRL;
3069 
3070  union
3071  {
3072  __IOM uint32_t reg;
3074  struct
3075  {
3076  __IM uint32_t : 4;
3077  __IM uint32_t REFBG_LOTHWARN_STS : 1;
3079  __IM uint32_t REFBG_UPTHWARN_STS : 1;
3081  } bit;
3082  } REF1_STS;
3083 
3084  union
3085  {
3086  __IOM uint32_t reg;
3088  struct
3089  {
3090  __IOM uint32_t VREF5V_PD_N : 1;
3091  __IM uint32_t VREF5V_OVL_STS : 1;
3092  __IM uint32_t VREF5V_UV_STS : 1;
3093  __IM uint32_t VREF5V_OV_STS : 1;
3094  } bit;
3095  } REF2_CTRL;
3096 } MF_Type;
3098 /* =========================================================================================================================== */
3099 /* ================ MON ================ */
3100 /* =========================================================================================================================== */
3101 
3102 
3107 typedef struct
3108 {
3109  __I uint32_t RESERVED0[13];
3110 
3111  union
3112  {
3113  __IO uint8_t reg;
3115  struct
3116  {
3117  __IO uint8_t EN : 1;
3118  __IO uint8_t FALL : 1;
3119  __IO uint8_t RISE : 1;
3120  __IO uint8_t CYC : 1;
3121  __IO uint8_t PD : 1;
3122  __IO uint8_t PU : 1;
3123  uint8_t : 1;
3124  __I uint8_t STS : 1;
3125  } bit;
3126  } CNF;
3127 } MON_Type;
3128 
3129 
3130 /* =========================================================================================================================== */
3131 /* ================ PMU ================ */
3132 /* =========================================================================================================================== */
3133 
3134 
3139 typedef struct
3140 {
3141 
3142  union
3143  {
3144  __IOM uint8_t reg;
3146  struct
3147  {
3148  __IM uint8_t LIN_WAKE : 1;
3149  __IM uint8_t MON_WAKE : 1;
3150  __IM uint8_t GPIO0 : 1;
3152  __IM uint8_t GPIO1 : 1;
3154  __IM uint8_t CYC_WAKE : 1;
3155  __IM uint8_t FAIL : 1;
3156  } bit;
3157  } WAKE_STATUS;
3158  __IM uint8_t RESERVED[3];
3159 
3160  union
3161  {
3162  __IOM uint8_t reg;
3164  struct
3165  {
3166  __IM uint8_t PMU_1V5_OVERVOLT : 1;
3167  __IM uint8_t PMU_1V5_OVERLOAD : 1;
3168  __IOM uint8_t PMU_1V5_FAIL_EN : 1;
3170  __IM uint8_t PMU_5V_OVERVOLT : 1;
3171  __IM uint8_t PMU_5V_OVERLOAD : 1;
3172  __IOM uint8_t PMU_5V_FAIL_EN : 1;
3173  } bit;
3174  } PMU_SUPPLY_STS;
3175  __IM uint8_t RESERVED1[3];
3176 
3177  union
3178  {
3179  __IOM uint8_t reg;
3181  struct
3182  {
3183  __IOM uint8_t ENABLE : 1;
3184  __IOM uint8_t CYC_EN : 1;
3185  __IOM uint8_t FAIL_EN : 1;
3187  __IOM uint8_t SHORT : 1;
3188  __IOM uint8_t OVERVOLT : 1;
3189  __IOM uint8_t OVERLOAD : 1;
3190  __IM uint8_t OK : 1;
3191  __IM uint8_t STABLE : 1;
3192  } bit;
3193  } VDDEXT_CTRL;
3194  __IM uint8_t RESERVED2[7];
3195 
3196  union
3197  {
3198  __IOM uint8_t reg;
3200  struct
3201  {
3202  __IOM uint8_t SYS_FAIL : 1;
3204  __IOM uint8_t PMU_WAKE : 1;
3205  __IOM uint8_t PMU_SleepEX : 1;
3206  __IOM uint8_t PMU_LPR : 1;
3207  __IOM uint8_t PMU_ClkWDT : 1;
3208  __IOM uint8_t PMU_ExtWDT : 1;
3209  __IOM uint8_t PMU_PIN : 1;
3210  __IOM uint8_t PMU_1V5DidPOR : 1;
3211  } bit;
3212  } PMU_RESET_STS1;
3213  __IM uint8_t RESERVED3[3];
3214 
3215  union
3216  {
3217  __IOM uint8_t reg;
3219  struct
3220  {
3221  __IOM uint8_t PMU_IntWDT : 1;
3222  __IOM uint8_t PMU_SOFT : 1;
3223  __IOM uint8_t LOCKUP : 1;
3224  } bit;
3225  } PMU_RESET_STS2;
3226  __IM uint8_t RESERVED4[11];
3227 
3228  union
3229  {
3230  __IOM uint8_t reg;
3232  struct
3233  {
3234  __IOM uint8_t WAKE_W_RST : 1;
3235  __IOM uint8_t EN_0V9_N : 1;
3237  __IOM uint8_t CYC_WAKE_EN : 1;
3238  __IOM uint8_t CYC_SENSE_EN : 1;
3239  __IM uint8_t : 3;
3241  } bit;
3242  } CNF_PMU_SETTINGS;
3243  __IM uint8_t RESERVED5[7];
3244 
3245  union
3246  {
3247  __IOM uint8_t reg;
3249  struct
3250  {
3251  __IOM uint8_t M03 : 4;
3252  __IOM uint8_t E01 : 2;
3253  __IM uint8_t : 1;
3254  __IOM uint8_t OSC_100kHz_EN : 1;
3255  } bit;
3256  } CNF_CYC_SENSE;
3257  __IM uint8_t RESERVED6[3];
3258 
3259  union
3260  {
3261  __IOM uint8_t reg;
3263  struct
3264  {
3265  __IOM uint8_t M03 : 4;
3266  __IOM uint8_t E01 : 2;
3267  } bit;
3268  } CNF_CYC_WAKE;
3269  __IM uint8_t RESERVED7[3];
3270 
3271  union
3272  {
3273  __IOM uint8_t reg;
3275  struct
3276  {
3277  __IOM uint8_t M03 : 4;
3278  } bit;
3279  } CNF_CYC_SAMPLE_DEL;
3280  __IM uint8_t RESERVED9[31];
3281 
3282  union
3283  {
3284  __IOM uint8_t reg;
3286  struct
3287  {
3288  __IM uint8_t : 7;
3289  __IOM uint8_t LIN_EN : 1;
3290  } bit;
3291  } LIN_WAKE_EN;
3292  __IM uint8_t RESERVED10[27];
3293 
3294  union
3295  {
3296  __IOM uint8_t reg;
3298  struct
3299  {
3300  __IOM uint8_t RST_TFB : 2;
3301  } bit;
3302  } CNF_RST_TFB;
3303  __IM uint8_t RESERVED11[3];
3304 
3305  union
3306  {
3307  __IOM uint8_t reg;
3309  struct
3310  {
3311  __IOM uint8_t SUPP_SHORT : 1;
3312  __IOM uint8_t SUPP_TMOUT : 1;
3313  __IOM uint8_t PMU_1V5_OVL : 1;
3314  __IOM uint8_t PMU_5V_OVL : 1;
3315  __IM uint8_t : 1;
3316  __IOM uint8_t SYS_OT : 1;
3317  __IOM uint8_t WDT1_SEQ_FAIL : 1;
3318  } bit;
3319  } SYS_FAIL_STS;
3320  __IM uint8_t RESERVED12[15];
3321 
3322  union
3323  {
3324  __IOM uint8_t reg;
3326  struct
3327  {
3328  __IOM uint8_t SUPPFAIL : 1;
3329  __IM uint8_t : 1;
3330  __IOM uint8_t VDDEXTSHORT : 1;
3331  } bit;
3332  } WAKE_STS_FAIL;
3333  __IM uint8_t RESERVED13[3];
3334 
3335  union
3336  {
3337  __IOM uint8_t reg;
3339  struct
3340  {
3341  __IM uint8_t WAKE_STS : 1;
3342  } bit;
3343  } WAKE_STS_MON;
3344  __IM uint8_t RESERVED14[3];
3345 
3346  union
3347  {
3348  __IOM uint8_t reg;
3350  struct
3351  {
3352  __IM uint8_t GPIO0_STS_0 : 1;
3353  __IM uint8_t GPIO0_STS_1 : 1;
3354  __IM uint8_t GPIO0_STS_2 : 1;
3355  __IM uint8_t GPIO0_STS_3 : 1;
3356  __IM uint8_t GPIO0_STS_4 : 1;
3357  } bit;
3358  } WAKE_STS_GPIO0;
3359  __IM uint8_t RESERVED15[3];
3360 
3361  union
3362  {
3363  __IOM uint8_t reg;
3365  struct
3366  {
3367  __IM uint8_t GPIO1_STS_0 : 1;
3368  __IM uint8_t GPIO1_STS_1 : 1;
3369  __IM uint8_t GPIO1_STS_2 : 1;
3370  __IM uint8_t GPIO1_STS_3 : 1;
3371  __IM uint8_t GPIO1_STS_4 : 1;
3372  } bit;
3373  } WAKE_STS_GPIO1;
3374  __IM uint8_t RESERVED16[31];
3375 
3376  union
3377  {
3378  __IOM uint8_t reg;
3380  struct
3381  {
3382  __IOM uint8_t CNF_LIN_FT : 1;
3383  __IOM uint8_t CNF_MON_FT : 1;
3384  __IOM uint8_t CNF_GPIO_FT : 2;
3385  } bit;
3386  } CNF_WAKE_FILTER;
3387  __IM uint8_t RESERVED17[19];
3388 
3389  union
3390  {
3391  __IOM uint8_t reg;
3393  struct
3394  {
3395  __IOM uint8_t DATA0 : 8;
3396  } bit;
3397  } GPUDATA00;
3398  __IM uint8_t RESERVED18[3];
3399 
3400  union
3401  {
3402  __IOM uint8_t reg;
3404  struct
3405  {
3406  __IOM uint8_t DATA1 : 8;
3407  } bit;
3408  } GPUDATA01;
3409  __IM uint8_t RESERVED19[3];
3410 
3411  union
3412  {
3413  __IOM uint8_t reg;
3415  struct
3416  {
3417  __IOM uint8_t DATA2 : 8;
3418  } bit;
3419  } GPUDATA02;
3420  __IM uint8_t RESERVED20[3];
3421 
3422  union
3423  {
3424  __IOM uint8_t reg;
3426  struct
3427  {
3428  __IOM uint8_t DATA3 : 8;
3429  } bit;
3430  } GPUDATA03;
3431  __IM uint8_t RESERVED21[3];
3432 
3433  union
3434  {
3435  __IOM uint8_t reg;
3437  struct
3438  {
3439  __IOM uint8_t DATA4 : 8;
3440  } bit;
3441  } GPUDATA04;
3442  __IM uint8_t RESERVED22[3];
3443 
3444  union
3445  {
3446  __IOM uint8_t reg;
3448  struct
3449  {
3450  __IOM uint8_t DATA5 : 8;
3451  } bit;
3452  } GPUDATA05;
3453  __IM uint8_t RESERVED23[3];
3454 
3455  union
3456  {
3457  __IOM uint8_t reg;
3459  struct
3460  {
3461  __IOM uint8_t GPIO0_RI_0 : 1;
3462  __IOM uint8_t GPIO0_RI_1 : 1;
3463  __IOM uint8_t GPIO0_RI_2 : 1;
3464  __IOM uint8_t GPIO0_RI_3 : 1;
3465  __IOM uint8_t GPIO0_RI_4 : 1;
3466  } bit;
3467  } WAKE_CONF_GPIO0_RISE;
3468  __IM uint8_t RESERVED24[3];
3469 
3470  union
3471  {
3472  __IOM uint8_t reg;
3474  struct
3475  {
3476  __IOM uint8_t GPIO0_FA_0 : 1;
3477  __IOM uint8_t GPIO0_FA_1 : 1;
3478  __IOM uint8_t GPIO0_FA_2 : 1;
3479  __IOM uint8_t GPIO0_FA_3 : 1;
3480  __IOM uint8_t GPIO0_FA_4 : 1;
3481  } bit;
3482  } WAKE_CONF_GPIO0_FALL;
3483  __IM uint8_t RESERVED25[3];
3484 
3485  union
3486  {
3487  __IOM uint8_t reg;
3489  struct
3490  {
3491  __IOM uint8_t GPIO0_CYC_0 : 1;
3492  __IOM uint8_t GPIO0_CYC_1 : 1;
3493  __IOM uint8_t GPIO0_CYC_2 : 1;
3494  __IOM uint8_t GPIO0_CYC_3 : 1;
3495  __IOM uint8_t GPIO0_CYC_4 : 1;
3496  } bit;
3497  } WAKE_CONF_GPIO0_CYC;
3498  __IM uint8_t RESERVED26[3];
3499 
3500  union
3501  {
3502  __IOM uint8_t reg;
3504  struct
3505  {
3506  __IOM uint8_t GPIO1_RI_0 : 1;
3507  __IOM uint8_t GPIO1_RI_1 : 1;
3508  __IOM uint8_t GPIO1_RI_2 : 1;
3509  __IOM uint8_t GPIO1_RI_3 : 1;
3510  __IOM uint8_t GPIO1_RI_4 : 1;
3511  } bit;
3512  } WAKE_CONF_GPIO1_RISE;
3513  __IM uint8_t RESERVED27[3];
3514 
3515  union
3516  {
3517  __IOM uint8_t reg;
3519  struct
3520  {
3521  __IOM uint8_t GPIO1_FA_0 : 1;
3522  __IOM uint8_t GPIO1_FA_1 : 1;
3523  __IOM uint8_t GPIO1_FA_2 : 1;
3524  __IOM uint8_t GPIO1_FA_3 : 1;
3525  __IOM uint8_t GPIO1_FA_4 : 1;
3526  } bit;
3527  } WAKE_CONF_GPIO1_FALL;
3528  __IM uint8_t RESERVED28[3];
3529 
3530  union
3531  {
3532  __IOM uint8_t reg;
3534  struct
3535  {
3536  __IOM uint8_t GPIO1_CYC_0 : 1;
3537  __IOM uint8_t GPIO1_CYC_1 : 1;
3538  __IOM uint8_t GPIO1_CYC_2 : 1;
3539  __IOM uint8_t GPIO1_CYC_3 : 1;
3540  __IOM uint8_t GPIO1_CYC_4 : 1;
3541  } bit;
3542  } WAKE_CONF_GPIO1_CYC;
3543  __IM uint8_t RESERVED29[487];
3544 
3545  union
3546  {
3547  __IOM uint8_t reg;
3549  struct
3550  {
3551  __IOM uint8_t MBIST_EN : 1;
3553  } bit;
3554  } SystemStartConfig;
3555 } PMU_Type;
3559 /* =========================================================================================================================== */
3560 /* ================ PORT ================ */
3561 /* =========================================================================================================================== */
3562 
3563 
3568 typedef struct
3569 {
3570 
3571  union
3572  {
3573  __IOM uint8_t reg;
3575  struct
3576  {
3577  __IOM uint8_t P0 : 1;
3578  __IOM uint8_t P1 : 1;
3579  __IOM uint8_t P2 : 1;
3580  __IOM uint8_t P3 : 1;
3581  __IOM uint8_t P4 : 1;
3582  } bit;
3583  } P0_DATA;
3584  __IM uint8_t RESERVED[3];
3585 
3586  union
3587  {
3588  __IOM uint8_t reg;
3590  struct
3591  {
3592  __IOM uint8_t P0 : 1;
3593  __IOM uint8_t P1 : 1;
3594  __IOM uint8_t P2 : 1;
3595  __IOM uint8_t P3 : 1;
3596  __IOM uint8_t P4 : 1;
3597  } bit;
3598  } P0_DIR;
3599  __IM uint8_t RESERVED1[3];
3600 
3601  union
3602  {
3603  __IOM uint8_t reg;
3605  struct
3606  {
3607  __IOM uint8_t P0 : 1;
3608  __IOM uint8_t P1 : 1;
3609  __IOM uint8_t P2 : 1;
3610  __IOM uint8_t P3 : 1;
3611  __IOM uint8_t P4 : 1;
3612  } bit;
3613  } P1_DATA;
3614  __IM uint8_t RESERVED2[3];
3615 
3616  union
3617  {
3618  __IOM uint8_t reg;
3620  struct
3621  {
3622  __IOM uint8_t P0 : 1;
3623  __IOM uint8_t P1 : 1;
3624  __IOM uint8_t P2 : 1;
3625  __IOM uint8_t P3 : 1;
3626  __IOM uint8_t P4 : 1;
3627  } bit;
3628  } P1_DIR;
3629  __IM uint8_t RESERVED3[3];
3630 
3631  union
3632  {
3633  __IOM uint8_t reg;
3635  struct
3636  {
3637  __IM uint8_t P0 : 1;
3638  __IM uint8_t P1 : 1;
3639  __IM uint8_t P2 : 1;
3640  __IM uint8_t P3 : 1;
3641  __IM uint8_t P4 : 1;
3642  __IM uint8_t P5 : 1;
3643  uint8_t : 1;
3644  __IM uint8_t P7 : 1;
3645  } bit;
3646  } P2_DATA;
3647  __IM uint8_t RESERVED4[3];
3648 
3649  union
3650  {
3651  __IOM uint8_t reg;
3653  struct
3654  {
3655  __IOM uint8_t P0 : 1;
3656  __IM uint8_t P1 : 1;
3657  __IOM uint8_t P2 : 1;
3658  __IOM uint8_t P3 : 1;
3659  __IOM uint8_t P4 : 1;
3660  __IOM uint8_t P5 : 1;
3661  uint8_t : 1;
3662  __IOM uint8_t P7 : 1;
3663  } bit;
3664  } P2_DIR;
3665  __IM uint8_t RESERVED5[3];
3666 
3667  union
3668  {
3669  __IOM uint8_t reg;
3671  struct
3672  {
3673  __IOM uint8_t P0 : 1;
3674  __IOM uint8_t P1 : 1;
3675  __IOM uint8_t P2 : 1;
3676  __IOM uint8_t P3 : 1;
3677  __IOM uint8_t P4 : 1;
3678  } bit;
3679  } P0_PUDSEL;
3680  __IM uint8_t RESERVED6[3];
3681 
3682  union
3683  {
3684  __IOM uint8_t reg;
3686  struct
3687  {
3688  __IOM uint8_t P0 : 1;
3689  __IOM uint8_t P1 : 1;
3690  __IOM uint8_t P2 : 1;
3691  __IOM uint8_t P3 : 1;
3692  __IOM uint8_t P4 : 1;
3693  } bit;
3694  } P0_PUDEN;
3695  __IM uint8_t RESERVED7[3];
3696 
3697  union
3698  {
3699  __IOM uint8_t reg;
3701  struct
3702  {
3703  __IOM uint8_t P0 : 1;
3704  __IOM uint8_t P1 : 1;
3705  __IOM uint8_t P2 : 1;
3706  __IOM uint8_t P3 : 1;
3707  __IOM uint8_t P4 : 1;
3708  } bit;
3709  } P1_PUDSEL;
3710  __IM uint8_t RESERVED8[3];
3711 
3712  union
3713  {
3714  __IOM uint8_t reg;
3716  struct
3717  {
3718  __IOM uint8_t P0 : 1;
3719  __IOM uint8_t P1 : 1;
3720  __IOM uint8_t P2 : 1;
3721  __IOM uint8_t P3 : 1;
3722  __IOM uint8_t P4 : 1;
3723  } bit;
3724  } P1_PUDEN;
3725  __IM uint8_t RESERVED9[3];
3726 
3727  union
3728  {
3729  __IOM uint8_t reg;
3731  struct
3732  {
3733  __IOM uint8_t P0 : 1;
3734  __IM uint8_t P1 : 1;
3735  __IOM uint8_t P2 : 1;
3736  __IOM uint8_t P3 : 1;
3737  __IOM uint8_t P4 : 1;
3738  __IOM uint8_t P5 : 1;
3739  uint8_t : 1;
3740  __IOM uint8_t P7 : 1;
3741  } bit;
3742  } P2_PUDSEL;
3743  __IM uint8_t RESERVED10[3];
3744 
3745  union
3746  {
3747  __IOM uint8_t reg;
3749  struct
3750  {
3751  __IOM uint8_t P0 : 1;
3752  __IM uint8_t P1 : 1;
3753  __IOM uint8_t P2 : 1;
3754  __IOM uint8_t P3 : 1;
3755  __IOM uint8_t P4 : 1;
3756  __IOM uint8_t P5 : 1;
3757  uint8_t : 1;
3758  __IOM uint8_t P7 : 1;
3759  } bit;
3760  } P2_PUDEN;
3761  __IM uint8_t RESERVED11[3];
3762 
3763  union
3764  {
3765  __IOM uint8_t reg;
3767  struct
3768  {
3769  __IOM uint8_t P0 : 1;
3770  __IOM uint8_t P1 : 1;
3771  __IOM uint8_t P2 : 1;
3772  __IOM uint8_t P3 : 1;
3773  __IOM uint8_t P4 : 1;
3774  } bit;
3775  } P0_ALTSEL0;
3776  __IM uint8_t RESERVED12[3];
3777 
3778  union
3779  {
3780  __IOM uint8_t reg;
3782  struct
3783  {
3784  __IOM uint8_t P0 : 1;
3785  __IOM uint8_t P1 : 1;
3786  __IOM uint8_t P2 : 1;
3787  __IOM uint8_t P3 : 1;
3788  __IOM uint8_t P4 : 1;
3789  } bit;
3790  } P0_ALTSEL1;
3791  __IM uint8_t RESERVED13[3];
3792 
3793  union
3794  {
3795  __IOM uint8_t reg;
3797  struct
3798  {
3799  __IOM uint8_t P0 : 1;
3800  __IOM uint8_t P1 : 1;
3801  __IOM uint8_t P2 : 1;
3802  __IOM uint8_t P3 : 1;
3803  __IOM uint8_t P4 : 1;
3804  } bit;
3805  } P1_ALTSEL0;
3806  __IM uint8_t RESERVED14[3];
3807 
3808  union
3809  {
3810  __IOM uint8_t reg;
3812  struct
3813  {
3814  __IOM uint8_t P0 : 1;
3815  __IOM uint8_t P1 : 1;
3816  __IOM uint8_t P2 : 1;
3817  __IOM uint8_t P3 : 1;
3818  __IOM uint8_t P4 : 1;
3819  } bit;
3820  } P1_ALTSEL1;
3821  __IM uint8_t RESERVED15[3];
3822 
3823  union
3824  {
3825  __IOM uint8_t reg;
3827  struct
3828  {
3829  __IOM uint8_t P0 : 1;
3830  __IOM uint8_t P1 : 1;
3831  __IOM uint8_t P2 : 1;
3832  __IOM uint8_t P3 : 1;
3833  __IOM uint8_t P4 : 1;
3834  } bit;
3835  } P0_OD;
3836  __IM uint8_t RESERVED16[3];
3837 
3838  union
3839  {
3840  __IOM uint8_t reg;
3842  struct
3843  {
3845  __IOM uint8_t P0 : 1;
3846  __IOM uint8_t P1 : 1;
3847  __IOM uint8_t P3_P2 : 1;
3848  __IOM uint8_t P4 : 1;
3849  } bit;
3850  } P1_OD;
3851 } PORT_Type;
3855 /* =========================================================================================================================== */
3856 /* ================ SCU ================ */
3857 /* =========================================================================================================================== */
3858 
3859 
3864 typedef struct
3865 {
3866 
3867  union
3868  {
3869  __IOM uint8_t reg;
3871  struct
3872  {
3873  __OM uint8_t NMIWDTC : 1;
3874  __OM uint8_t NMIPLLC : 1;
3875  __OM uint8_t NMINVMC : 1;
3876  __OM uint8_t NMIOTC : 1;
3877  __OM uint8_t NMIOWDC : 1;
3878  __OM uint8_t NMIMAPC : 1;
3879  __OM uint8_t NMIECCC : 1;
3880  __OM uint8_t NMISUPC : 1;
3881  } bit;
3882  } NMICLR;
3883  __IM uint8_t RESERVED[3];
3884 
3885  union
3886  {
3887  __IOM uint8_t reg;
3889  struct
3890  {
3891  __IM uint8_t EXINT0R : 1;
3892  __IM uint8_t EXINT0F : 1;
3893  __IM uint8_t EXINT1R : 1;
3894  __IM uint8_t EXINT1F : 1;
3895  __IM uint8_t EXINT2R : 1;
3896  __IM uint8_t EXINT2F : 1;
3897  __IM uint8_t MONR : 1;
3898  __IM uint8_t MONF : 1;
3900  } bit;
3901  } IRCON0;
3902  __IM uint8_t RESERVED1[3];
3903 
3904  union
3905  {
3906  __IOM uint8_t reg;
3908  struct
3909  {
3910  __IM uint8_t EIR : 1;
3911  __IM uint8_t TIR : 1;
3912  __IM uint8_t RIR : 1;
3913  } bit;
3914  } IRCON1;
3915  __IM uint8_t RESERVED2[3];
3916 
3917  union
3918  {
3919  __IOM uint8_t reg;
3921  struct
3922  {
3923  __IM uint8_t EIR : 1;
3924  __IM uint8_t TIR : 1;
3925  __IM uint8_t RIR : 1;
3926  } bit;
3927  } IRCON2;
3928  __IM uint8_t RESERVED3[3];
3929 
3930  union
3931  {
3932  __IOM uint8_t reg;
3934  struct
3935  {
3936  __IM uint8_t CCU6SR0 : 1;
3938  __IM uint8_t CCU6SR1 : 1;
3939  } bit;
3940  } IRCON3;
3941  __IM uint8_t RESERVED4[3];
3942 
3943  union
3944  {
3945  __IOM uint8_t reg;
3947  struct
3948  {
3949  __IM uint8_t CCU6SR2 : 1;
3950  __IM uint8_t : 3;
3951  __IM uint8_t CCU6SR3 : 1;
3952  } bit;
3953  } IRCON4;
3954  __IM uint8_t RESERVED5[3];
3955 
3956  union
3957  {
3958  __IOM uint8_t reg;
3960  struct
3961  {
3962  __IM uint8_t FNMIWDT : 1;
3963  __IM uint8_t FNMIPLL : 1;
3964  __IM uint8_t FNMINVM : 1;
3965  __IM uint8_t FNMIOT : 1;
3966  __IM uint8_t FNMIOWD : 1;
3967  __IM uint8_t FNMIMAP : 1;
3968  __IM uint8_t FNMIECC : 1;
3969  __IM uint8_t FNMISUP : 1;
3970  } bit;
3971  } NMISR;
3972  __IM uint8_t RESERVED6[3];
3973 
3974  union
3975  {
3976  __IOM uint8_t reg;
3978  struct
3979  {
3980  __IM uint8_t : 7;
3981  __IOM uint8_t EA : 1;
3982  } bit;
3983  } IEN0;
3984  __IM uint8_t RESERVED7[7];
3985 
3986  union
3987  {
3988  __IOM uint8_t reg;
3990  struct
3991  {
3992  __IOM uint8_t NMIWDT : 1;
3993  __IOM uint8_t NMIPLL : 1;
3994  __IOM uint8_t NMINVM : 1;
3995  __IOM uint8_t NMIOT : 1;
3996  __IOM uint8_t NMIOWD : 1;
3997  __IOM uint8_t NMIMAP : 1;
3998  __IOM uint8_t NMIECC : 1;
3999  __IOM uint8_t NMISUP : 1;
4000  } bit;
4001  } NMICON;
4002  __IM uint8_t RESERVED8[3];
4003 
4004  union
4005  {
4006  __IOM uint8_t reg;
4008  struct
4009  {
4010  __IOM uint8_t EXINT0 : 2;
4011  __IOM uint8_t EXINT1 : 2;
4012  __IOM uint8_t EXINT2 : 2;
4013  __IOM uint8_t MON_Trig_Sel : 2;
4014  } bit;
4015  } EXICON0;
4016  __IM uint8_t RESERVED9[3];
4017 
4018  union
4019  {
4020  __IOM uint8_t reg;
4022  struct
4023  {
4024  __OM uint8_t EXINT0RC : 1;
4026  __OM uint8_t EXINT0FC : 1;
4028  __OM uint8_t EXINT1RC : 1;
4030  __OM uint8_t EXINT1FC : 1;
4032  __OM uint8_t EXINT2RC : 1;
4034  __OM uint8_t EXINT2FC : 1;
4036  __OM uint8_t MONRC : 1;
4038  __OM uint8_t MONFC : 1;
4040  } bit;
4041  } IRCON0CLR;
4042  __IM uint8_t RESERVED10[3];
4043 
4044  union
4045  {
4046  __IOM uint8_t reg;
4048  struct
4049  {
4050  __IOM uint8_t EIREN1 : 1;
4051  __IOM uint8_t TIREN1 : 1;
4052  __IOM uint8_t RIREN1 : 1;
4053  __IM uint8_t : 3;
4054  __IOM uint8_t RIEN1 : 1;
4055  __IOM uint8_t TIEN1 : 1;
4056  } bit;
4057  } MODIEN1;
4058  __IM uint8_t RESERVED11[3];
4059 
4060  union
4061  {
4062  __IOM uint8_t reg;
4064  struct
4065  {
4066  __IOM uint8_t EIREN2 : 1;
4067  __IOM uint8_t TIREN2 : 1;
4068  __IOM uint8_t RIREN2 : 1;
4069  __IM uint8_t : 2;
4070  __IOM uint8_t EXINT2_EN : 1;
4071  __IOM uint8_t RIEN2 : 1;
4072  __IOM uint8_t TIEN2 : 1;
4073  } bit;
4074  } MODIEN2;
4075  __IM uint8_t RESERVED12[3];
4076 
4077  union
4078  {
4079  __IOM uint8_t reg;
4081  struct
4082  {
4083  __IOM uint8_t IE0 : 1;
4084  __IM uint8_t : 3;
4085  __IOM uint8_t MONIE : 1;
4086  __IM uint8_t MONSTS : 1;
4087  } bit;
4088  } MODIEN3;
4089  __IM uint8_t RESERVED13[3];
4090 
4091  union
4092  {
4093  __IOM uint8_t reg;
4095  struct
4096  {
4097  __IOM uint8_t IE1 : 1;
4098  } bit;
4099  } MODIEN4;
4100  __IM uint8_t RESERVED14[3];
4101 
4102  union
4103  {
4104  __IOM uint8_t reg;
4106  struct
4107  {
4108  __IOM uint8_t XTAL_ON : 1;
4109  __IOM uint8_t SL : 1;
4110  __IOM uint8_t PD : 1;
4111  __IOM uint8_t SD : 1;
4112  } bit;
4113  } PMCON0;
4114  __IM uint8_t RESERVED15[3];
4115 
4116  union
4117  {
4118  __IOM uint8_t reg;
4120  struct
4121  {
4122  __IM uint8_t LOCK : 1;
4123  __IOM uint8_t RESLD : 1;
4124  __IOM uint8_t OSCDISC : 1;
4125  __IOM uint8_t VCOBYP : 1;
4126  __IOM uint8_t NDIV : 4;
4127  } bit;
4128  } PLL_CON;
4129  __IM uint8_t RESERVED16[3];
4130 
4131  union
4132  {
4133  __IOM uint8_t reg;
4135  struct
4136  {
4137  __IOM uint8_t CLKREL : 4;
4138  __IOM uint8_t K2DIV : 2;
4139  __IOM uint8_t K1DIV : 1;
4140  __IOM uint8_t VCOSEL : 1;
4141  } bit;
4142  } CMCON1;
4143  __IM uint8_t RESERVED17[3];
4144 
4145  union
4146  {
4147  __IOM uint8_t reg;
4149  struct
4150  {
4151  __IOM uint8_t PBA0CLKREL : 1;
4152  } bit;
4153  } CMCON2;
4154  __IM uint8_t RESERVED18[3];
4155 
4156  union
4157  {
4158  __IOM uint8_t reg;
4160  struct
4161  {
4162  __IOM uint8_t WDTIN : 1;
4163  __IOM uint8_t WDTRS : 1;
4164  __IOM uint8_t WDTEN : 1;
4165  __IM uint8_t : 1;
4166  __IM uint8_t WDTPR : 1;
4167  __IOM uint8_t WINBEN : 1;
4168  } bit;
4169  } WDTCON;
4170  __IM uint8_t RESERVED19[3];
4171 
4172  union
4173  {
4174  __IOM uint8_t reg;
4176  struct
4177  {
4178  __IM uint8_t PLL_LOCK : 1;
4179  __IOM uint8_t APCLK_SET : 1;
4180  __IOM uint8_t T3CLK_SEL : 1;
4181  __IOM uint8_t CLKWDT_IE : 1;
4182  __IOM uint8_t BGCLK_SEL : 1;
4183  __IOM uint8_t BGCLK_DIV : 1;
4184  __IOM uint8_t CPCLK_SEL : 1;
4185  __IOM uint8_t CPCLK_DIV : 1;
4186  } bit;
4187  } APCLK_CTRL1;
4188  __IM uint8_t RESERVED20[3];
4189 
4190  union
4191  {
4192  __IOM uint8_t reg;
4194  struct
4195  {
4196  __IOM uint8_t APCLK1FAC : 2;
4197  __IOM uint8_t APCLK1SCLR : 1;
4198  __IM uint8_t : 1;
4199  __IM uint8_t APCLK1STS : 2;
4200  __IM uint8_t APCLK3STS : 1;
4201  __IOM uint8_t APCLK3SCLR : 1;
4202  } bit;
4203  } APCLK1;
4204  __IM uint8_t RESERVED21[3];
4205 
4206  union
4207  {
4208  __IOM uint8_t reg;
4210  struct
4211  {
4212  __IOM uint8_t APCLK2FAC : 5;
4213  __IM uint8_t APCLK2STS : 2;
4214  __IOM uint8_t APCLK2SCLR : 1;
4215  } bit;
4216  } APCLK2;
4217  __IM uint8_t RESERVED22[3];
4218 
4219  union
4220  {
4221  __IOM uint8_t reg;
4223  struct
4224  {
4225  __IOM uint8_t ADC1_DIS : 1;
4226  __IOM uint8_t SSC1_DIS : 1;
4227  __IOM uint8_t CCU6_DIS : 1;
4228  __IOM uint8_t T2_DIS : 1;
4229  __IOM uint8_t GPT12_DIS : 1;
4230  } bit;
4231  } PMCON1;
4232  __IM uint8_t RESERVED23[3];
4233 
4234  union
4235  {
4236  __IOM uint8_t reg;
4238  struct
4239  {
4240  __IM uint8_t : 1;
4241  __IOM uint8_t SSC2_DIS : 1;
4242  __IM uint8_t : 1;
4243  __IOM uint8_t T21_DIS : 1;
4244  __IM uint8_t : 1;
4245  __IOM uint8_t T3_DIS : 1;
4246  } bit;
4247  } PMCON2;
4248  __IM uint8_t RESERVED24[3];
4249 
4250  union
4251  {
4252  __IOM uint8_t reg;
4254  struct
4255  {
4256  __IOM uint8_t LOCKUP : 1;
4257  __IM uint8_t : 6;
4258  __IOM uint8_t LOCKUP_EN : 1;
4259  } bit;
4260  } RSTCON;
4261  __IM uint8_t RESERVED25[3];
4262 
4263  union
4264  {
4265  __IOM uint8_t reg;
4267  struct
4268  {
4269  __IOM uint8_t SDADCCLK_DIV : 2;
4270  __IOM uint8_t T3CLK_DIV : 2;
4271  } bit;
4272  } APCLK_CTRL2;
4273  __IM uint8_t RESERVED26[3];
4274 
4275  union
4276  {
4277  __IOM uint8_t reg;
4279  struct
4280  {
4281  __IM uint8_t : 4;
4282  __IOM uint8_t NVMCLKFAC : 2;
4283  __IOM uint8_t SYSCLKSEL : 2;
4284  } bit;
4285  } SYSCON0;
4286  __IM uint8_t RESERVED27[3];
4287 
4288  union
4289  {
4290  __IOM uint8_t reg;
4292  struct
4293  {
4294  __IOM uint8_t INIT_FAIL : 1;
4295  __IOM uint8_t MRAMINITSTS : 1;
4296  __IOM uint8_t PG100TP_CHKS_ERR : 1;
4297  } bit;
4298  } SYS_STRTUP_STS;
4299  __IM uint8_t RESERVED28[3];
4300 
4301  union
4302  {
4303  __IOM uint8_t reg;
4305  struct
4306  {
4307  __IOM uint8_t WDTREL : 8;
4308  } bit;
4309  } WDTREL;
4310  __IM uint8_t RESERVED29[3];
4311 
4312  union
4313  {
4314  __IOM uint8_t reg;
4316  struct
4317  {
4318  __IOM uint8_t WDTWINB : 8;
4319  } bit;
4320  } WDTWINB;
4321  __IM uint8_t RESERVED30[3];
4322 
4323  union
4324  {
4325  __IOM uint8_t reg;
4327  struct
4328  {
4329  __IM uint8_t WDT : 8;
4330  } bit;
4331  } WDTL;
4332  __IM uint8_t RESERVED31[3];
4333 
4334  union
4335  {
4336  __IOM uint8_t reg;
4338  struct
4339  {
4340  __IM uint8_t WDT : 8;
4341  } bit;
4342  } WDTH;
4343  __IM uint8_t RESERVED32[3];
4344 
4345  union
4346  {
4347  __IOM uint8_t reg;
4349  struct
4350  {
4351  __IOM uint8_t R : 1;
4352  __IOM uint8_t BRPRE : 3;
4353  } bit;
4354  } BCON1;
4355  __IM uint8_t RESERVED33[3];
4356 
4357  union
4358  {
4359  __IOM uint8_t reg;
4362  struct
4363  {
4364  __IOM uint8_t FD_SEL : 5;
4365  __IOM uint8_t BR_VALUE : 3;
4366  } bit;
4367  } BGL1;
4368  __IM uint8_t RESERVED34[3];
4369 
4370  union
4371  {
4372  __IOM uint8_t reg;
4374  struct
4375  {
4376  __IOM uint8_t BR_VALUE : 8;
4377  } bit;
4378  } BGH1;
4379  __IM uint8_t RESERVED35[3];
4380 
4381  union
4382  {
4383  __IOM uint8_t reg;
4385  struct
4386  {
4387  __IOM uint8_t BRDIS : 1;
4388  __IOM uint8_t BGSEL : 2;
4389  __IM uint8_t BRK : 1;
4390  __IM uint8_t EOFSYN : 1;
4391  __IM uint8_t ERRSYN : 1;
4392  __IOM uint8_t SYNEN : 1;
4393  } bit;
4394  } LINST;
4395  __IM uint8_t RESERVED36[3];
4396 
4397  union
4398  {
4399  __IOM uint8_t reg;
4401  struct
4402  {
4403  __IOM uint8_t R : 1;
4404  __IOM uint8_t BRPRE : 3;
4405  } bit;
4406  } BCON2;
4407  __IM uint8_t RESERVED37[3];
4408 
4409  union
4410  {
4411  __IOM uint8_t reg;
4414  struct
4415  {
4416  __IOM uint8_t FD_SEL : 5;
4417  __IOM uint8_t BR_VALUE : 3;
4418  } bit;
4419  } BGL2;
4420  __IM uint8_t RESERVED38[3];
4421 
4422  union
4423  {
4424  __IOM uint8_t reg;
4426  struct
4427  {
4428  __IOM uint8_t BR_VALUE : 8;
4429  } bit;
4430  } BGH2;
4431  __IM uint8_t RESERVED39[3];
4432 
4433  union
4434  {
4435  __IOM uint8_t reg;
4437  struct
4438  {
4439  __IM uint8_t : 3;
4440  __OM uint8_t BRKC : 1;
4441  __OM uint8_t EOFSYNC : 1;
4442  __OM uint8_t ERRSYNC : 1;
4443  } bit;
4444  } LINSCLR;
4445  __IM uint8_t RESERVED40[3];
4446 
4447  union
4448  {
4449  __IOM uint8_t reg;
4451  struct
4452  {
4453  __IM uint8_t VERID : 3;
4454  __IM uint8_t PRODID : 5;
4455  } bit;
4456  } ID;
4457  __IM uint8_t RESERVED41[3];
4458 
4459  union
4460  {
4461  __IOM uint8_t reg;
4463  struct
4464  {
4465  __IOM uint8_t MODE : 2;
4466  __IM uint8_t PROTECT_S : 1;
4467  __IOM uint8_t PASS : 5;
4468  } bit;
4469  } PASSWD;
4470  __IM uint8_t RESERVED42[3];
4471 
4472  union
4473  {
4474  __IOM uint8_t reg;
4476  struct
4477  {
4478  __IOM uint8_t OSCSS : 2;
4479  __IOM uint8_t OSCWDTRST : 1;
4480  __IM uint8_t OSC2L : 1;
4481  __IOM uint8_t XPD : 1;
4482  __IM uint8_t : 2;
4483  __IOM uint8_t OSCTRIM_8 : 1;
4484  } bit;
4485  } OSC_CON;
4486  __IM uint8_t RESERVED43[3];
4487 
4488  union
4489  {
4490  __IOM uint8_t reg;
4492  struct
4493  {
4494  __IOM uint8_t COREL : 4;
4495  __IOM uint8_t COUTS0 : 1;
4496  __IOM uint8_t TLEN : 1;
4497  __IOM uint8_t COUTS1 : 1;
4498  __IOM uint8_t EN : 1;
4499  } bit;
4500  } COCON;
4501  __IM uint8_t RESERVED44[3];
4502 
4503  union
4504  {
4505  __IOM uint8_t reg;
4507  struct
4508  {
4509  __IOM uint8_t EXINT0IS : 2;
4510  __IOM uint8_t EXINT1IS : 2;
4511  __IOM uint8_t EXINT2IS : 2;
4512  __IOM uint8_t URIOS1 : 1;
4513  __IOM uint8_t U_TX_CONDIS : 1;
4514  } bit;
4515  } MODPISEL;
4516  __IM uint8_t RESERVED45[3];
4517 
4518  union
4519  {
4520  __IOM uint8_t reg;
4522  struct
4523  {
4524  __IOM uint8_t GPT12CAPINB : 1;
4525  __IM uint8_t : 5;
4526  __IOM uint8_t T2EXCON : 1;
4527  __IOM uint8_t T21EXCON : 1;
4528  } bit;
4529  } MODPISEL1;
4530  __IM uint8_t RESERVED46[3];
4531 
4532  union
4533  {
4534  __IOM uint8_t reg;
4536  struct
4537  {
4538  __IOM uint8_t T2IS : 2;
4539  __IOM uint8_t T21IS : 2;
4540  __IOM uint8_t T2EXIS : 2;
4541  __IOM uint8_t T21EXIS : 2;
4542  } bit;
4543  } MODPISEL2;
4544  __IM uint8_t RESERVED47[3];
4545 
4546  union
4547  {
4548  __IOM uint8_t reg;
4550  struct
4551  {
4552  __IM uint8_t : 6;
4553  __IOM uint8_t URIOS2 : 1;
4554  } bit;
4555  } MODPISEL3;
4556  __IM uint8_t RESERVED48[3];
4557 
4558  union
4559  {
4560  __IOM uint8_t reg;
4562  struct
4563  {
4564  __IOM uint8_t WDTSUSP : 1;
4565  __IOM uint8_t T12SUSP : 1;
4566  __IOM uint8_t T13SUSP : 1;
4567  __IOM uint8_t T2_SUSP : 1;
4568  __IOM uint8_t GPT12_SUSP : 1;
4569  __IM uint8_t : 1;
4570  __IOM uint8_t T21_SUSP : 1;
4571  } bit;
4572  } MODSUSP1;
4573  __IM uint8_t RESERVED49[3];
4574 
4575  union
4576  {
4577  __IOM uint8_t reg;
4579  struct
4580  {
4581  __IOM uint8_t T3_SUSP : 1;
4582  __IOM uint8_t MU_SUSP : 1;
4583  __IOM uint8_t ADC1_SUSP : 1;
4584  } bit;
4585  } MODSUSP2;
4586  __IM uint8_t RESERVED50[3];
4587 
4588  union
4589  {
4590  __IOM uint8_t reg;
4592  struct
4593  {
4594  __IOM uint8_t GPT12 : 4;
4595  __IOM uint8_t TRIG_CONF : 1;
4596  __IOM uint8_t T3_GPT12_SEL : 1;
4597  } bit;
4598  } GPT12PISEL;
4599  __IM uint8_t RESERVED51[3];
4600 
4601  union
4602  {
4603  __IOM uint8_t reg;
4606  struct
4607  {
4608  __IOM uint8_t RIE : 1;
4609  __IM uint8_t : 1;
4610  __IOM uint8_t NVMIE : 1;
4611  } bit;
4612  } EDCCON;
4613  __IM uint8_t RESERVED52[3];
4614 
4615  union
4616  {
4617  __IOM uint8_t reg;
4620  struct
4621  {
4622  __IM uint8_t RDBE : 1;
4623  __IM uint8_t : 1;
4624  __IM uint8_t NVMDBE : 1;
4625  __IM uint8_t : 1;
4626  __IM uint8_t RSBE : 1;
4627  } bit;
4628  } EDCSTAT;
4629  __IM uint8_t RESERVED53[3];
4630 
4631  union
4632  {
4633  __IOM uint8_t reg;
4635  struct
4636  {
4637  __IOM uint8_t SECTORINFO : 6;
4638  __IOM uint8_t SASTATUS : 2;
4639  } bit;
4640  } MEMSTAT;
4641  __IM uint8_t RESERVED54[3];
4642 
4643  union
4644  {
4645  __IOM uint8_t reg;
4647  struct
4648  {
4649  __IOM uint8_t NVMPROTSTSL_0 : 1;
4650  __IOM uint8_t NVMPROTSTSL_1 : 1;
4651  __IOM uint8_t NVMPROTSTSL_2 : 1;
4652  __IOM uint8_t NVMPROTSTSL_3 : 1;
4653  } bit;
4654  } NVM_PROT_STS;
4655  __IM uint8_t RESERVED55[3];
4656 
4657  union
4658  {
4659  __IOM uint8_t reg;
4661  struct
4662  {
4663  __IM uint8_t NVM_PROT_ERR : 1;
4664  __IM uint8_t NVM_ADDR_ERR : 1;
4665  __IM uint8_t NVM_SFR_PROT_ERR : 1;
4666  __IM uint8_t NVM_SFR_ADDR_ERR : 1;
4667  __IM uint8_t ROM_PROT_ERR : 1;
4668  __IM uint8_t ROM_ADDR_ERR : 1;
4669  __IM uint8_t RAM_PROT_ERR : 1;
4670  } bit;
4671  } MEM_ACC_STS;
4672  __IM uint8_t RESERVED56[3];
4673 
4674  union
4675  {
4676  __IOM uint8_t reg;
4678  struct
4679  {
4680  __IOM uint8_t PDM0 : 3;
4681  __IM uint8_t : 1;
4682  __IOM uint8_t PDM1 : 3;
4683  } bit;
4684  } P0_POCON0;
4685  __IM uint8_t RESERVED57[3];
4686 
4687  union
4688  {
4689  __IOM uint8_t reg;
4691  struct
4692  {
4693  __IOM uint8_t PDM2 : 3;
4694  __IM uint8_t : 1;
4695  __IOM uint8_t PDM3 : 3;
4696  } bit;
4697  } P0_POCON1;
4698  __IM uint8_t RESERVED58[3];
4699 
4700  union
4701  {
4702  __IOM uint8_t reg;
4704  struct
4705  {
4706  __IOM uint8_t PDM4 : 3;
4707  } bit;
4708  } P0_POCON2;
4709  __IM uint8_t RESERVED59[3];
4710 
4711  union
4712  {
4713  __IOM uint8_t reg;
4715  struct
4716  {
4717  __IOM uint8_t TCC : 2;
4718  } bit;
4719  } TCCR;
4720  __IM uint8_t RESERVED60[3];
4721 
4722  union
4723  {
4724  __IOM uint8_t reg;
4726  struct
4727  {
4728  __IOM uint8_t PDM0 : 3;
4729  __IM uint8_t : 1;
4730  __IOM uint8_t PDM1 : 3;
4731  } bit;
4732  } P1_POCON0;
4733  __IM uint8_t RESERVED61[3];
4734 
4735  union
4736  {
4737  __IOM uint8_t reg;
4739  struct
4740  {
4741  __IOM uint8_t PDM2 : 3;
4742  __IM uint8_t : 1;
4743  __IOM uint8_t PDM3 : 3;
4744  } bit;
4745  } P1_POCON1;
4746  __IM uint8_t RESERVED62[3];
4747 
4748  union
4749  {
4750  __IOM uint8_t reg;
4752  struct
4753  {
4754  __IOM uint8_t PDM4 : 3;
4755  } bit;
4756  } P1_POCON2;
4757  __IM uint8_t RESERVED63[11];
4758 
4759  union
4760  {
4761  __IOM uint8_t reg;
4764  struct
4765  {
4766  __OM uint8_t RDBEC : 1;
4767  __IM uint8_t : 1;
4768  __OM uint8_t NVMDBEC : 1;
4769  __IM uint8_t : 1;
4770  __OM uint8_t RSBEC : 1;
4771  } bit;
4772  } EDCSCLR;
4773  __IM uint8_t RESERVED64[55];
4774 
4775  union
4776  {
4777  __IOM uint8_t reg;
4779  struct
4780  {
4781  __IOM uint8_t CH1IE : 1;
4782  __IOM uint8_t CH2IE : 1;
4783  __IOM uint8_t CH3IE : 1;
4784  __IOM uint8_t CH4IE : 1;
4785  __IOM uint8_t CH5IE : 1;
4786  __IOM uint8_t CH6IE : 1;
4787  __IOM uint8_t CH7IE : 1;
4788  __IOM uint8_t CH8IE : 1;
4789  } bit;
4790  } DMAIEN1;
4791  __IM uint8_t RESERVED65[3];
4792 
4793  union
4794  {
4795  __IOM uint8_t reg;
4797  struct
4798  {
4799  __IOM uint8_t TRERRIE : 1;
4800  __IOM uint8_t TRSEQ1RDYIE : 1;
4801  __IOM uint8_t TRSEQ2RDYIE : 1;
4802  __IOM uint8_t SSCTXIE : 1;
4803  __IOM uint8_t SSCRXIE : 1;
4804  __IOM uint8_t GPT12IE : 1;
4805  __IOM uint8_t SDADCIE : 1;
4806  } bit;
4807  } DMAIEN2;
4808  __IM uint8_t RESERVED66[3];
4809 
4810  union
4811  {
4812  __IOM uint8_t reg;
4814  struct
4815  {
4816  __IOM uint8_t SSCTXSRCSEL : 1;
4817  __IOM uint8_t SSCRXSRCSEL : 1;
4818  __IOM uint8_t T12ZM_DMAEN : 1;
4819  __IOM uint8_t T12PM_DMAEN : 1;
4820  __IM uint8_t : 1;
4821  __IM uint8_t SSCTX : 1;
4822  __IM uint8_t SSCRX : 1;
4823  __IM uint8_t GPT12_T3 : 1;
4824  } bit;
4825  } DMASRCSEL;
4826  __IM uint8_t RESERVED67[7];
4827 
4828  union
4829  {
4830  __IOM uint8_t reg;
4832  struct
4833  {
4834  __IM uint8_t CH1 : 1;
4835  __IM uint8_t CH2 : 1;
4836  __IM uint8_t CH3 : 1;
4837  __IM uint8_t CH4 : 1;
4838  __IM uint8_t CH5 : 1;
4839  __IM uint8_t CH6 : 1;
4840  __IM uint8_t CH7 : 1;
4841  __IM uint8_t CH8 : 1;
4842  } bit;
4843  } DMAIRC1;
4844  __IM uint8_t RESERVED68[3];
4845 
4846  union
4847  {
4848  __IOM uint8_t reg;
4850  struct
4851  {
4852  __IM uint8_t STRDY : 1;
4853  __IM uint8_t TRSEQ1DY : 1;
4854  __IM uint8_t TRSEQ2DY : 1;
4855  __IM uint8_t SSC1RDY : 1;
4856  __IM uint8_t SSC2RDY : 1;
4857  __IM uint8_t GPT12 : 1;
4858  __IM uint8_t SDADC : 1;
4859  } bit;
4860  } DMAIRC2;
4861  __IM uint8_t RESERVED69[3];
4862 
4863  union
4864  {
4865  __IOM uint8_t reg;
4868  struct
4869  {
4870  __IOM uint8_t T2IE : 1;
4871  __IOM uint8_t T3IE : 1;
4872  __IOM uint8_t T4IE : 1;
4873  __IOM uint8_t T5IE : 1;
4874  __IOM uint8_t T6IE : 1;
4875  __IOM uint8_t CRIE : 1;
4877  } bit;
4878  } GPT12IEN;
4879  __IM uint8_t RESERVED70[3];
4880 
4881  union
4882  {
4883  __IOM uint8_t reg;
4885  struct
4886  {
4887  __IM uint8_t T2 : 1;
4888  __IM uint8_t T3 : 1;
4889  __IM uint8_t T4 : 1;
4890  __IM uint8_t T5 : 1;
4891  __IM uint8_t T6 : 1;
4892  __IM uint8_t CR : 1;
4893  } bit;
4894  } GPT12IRC;
4895  __IM uint8_t RESERVED71[3];
4896 
4897  union
4898  {
4899  __IOM uint8_t reg;
4902  struct
4903  {
4904  __OM uint8_t T2C : 1;
4905  __OM uint8_t T3C : 1;
4906  __OM uint8_t T4C : 1;
4907  __OM uint8_t T5C : 1;
4908  __OM uint8_t T6C : 1;
4909  __OM uint8_t CRC : 1;
4910  } bit;
4911  } GPT12ICLR;
4912  __IM uint8_t RESERVED72[19];
4913 
4914  union
4915  {
4916  __IOM uint8_t reg;
4918  struct
4919  {
4920  __OM uint8_t EIRC : 1;
4921  __OM uint8_t TIRC : 1;
4922  __OM uint8_t RIRC : 1;
4923  } bit;
4924  } IRCON1CLR;
4925  __IM uint8_t RESERVED73[3];
4926 
4927  union
4928  {
4929  __IOM uint8_t reg;
4931  struct
4932  {
4933  __OM uint8_t EIRC : 1;
4934  __OM uint8_t TIRC : 1;
4935  __OM uint8_t RIRC : 1;
4936  } bit;
4937  } IRCON2CLR;
4938  __IM uint8_t RESERVED74[3];
4939 
4940  union
4941  {
4942  __IOM uint8_t reg;
4944  struct
4945  {
4946  __IOM uint8_t GPT12_DMAEN : 2;
4947  } bit;
4948  } DMASRCSEL2;
4949  __IM uint8_t RESERVED75[3];
4950 
4951  union
4952  {
4953  __IOM uint8_t reg;
4955  struct
4956  {
4957  __OM uint8_t CH1C : 1;
4958  __OM uint8_t CH2C : 1;
4959  __OM uint8_t CH3C : 1;
4960  __OM uint8_t CH4C : 1;
4961  __OM uint8_t CH5C : 1;
4962  __OM uint8_t CH6C : 1;
4963  __OM uint8_t CH7C : 1;
4964  __OM uint8_t CH8C : 1;
4965  } bit;
4966  } DMAIRC1CLR;
4967  __IM uint8_t RESERVED76[3];
4968 
4969  union
4970  {
4971  __IOM uint8_t reg;
4973  struct
4974  {
4975  __IM uint8_t : 1;
4976  __OM uint8_t TRSEQ1DYC : 1;
4977  __OM uint8_t TRSEQ2DYC : 1;
4978  __OM uint8_t SSC1C : 1;
4979  __OM uint8_t SSC2C : 1;
4980  __OM uint8_t GPT12C : 1;
4981  __OM uint8_t SDADCC : 1;
4982  } bit;
4983  } DMAIRC2CLR;
4984  __IM uint8_t RESERVED77[7];
4985 
4986  union
4987  {
4988  __IOM uint8_t reg;
4990  struct
4991  {
4992  __OM uint8_t CCU6SR0C : 1;
4993  __IM uint8_t : 3;
4994  __OM uint8_t CCU6SR1C : 1;
4995  } bit;
4996  } IRCON3CLR;
4997  __IM uint8_t RESERVED78[3];
4998 
4999  union
5000  {
5001  __IOM uint8_t reg;
5003  struct
5004  {
5005  __OM uint8_t CCU6SR2C : 1;
5006  __IM uint8_t : 3;
5007  __OM uint8_t CCU6SR3C : 1;
5008  } bit;
5009  } IRCON4CLR;
5010  __IM uint8_t RESERVED79[3];
5011 
5012  union
5013  {
5014  __IOM uint8_t reg;
5016  struct
5017  {
5018  __IM uint8_t : 5;
5019  __OM uint8_t SSCTXC : 1;
5020  __OM uint8_t SSCRXC : 1;
5021  __OM uint8_t GPT12_T3C : 1;
5022  } bit;
5023  } DMASRCCLR;
5024 } SCU_Type;
5028 /* =========================================================================================================================== */
5029 /* ================ SCUPM ================ */
5030 /* =========================================================================================================================== */
5031 
5032 
5037 typedef struct
5038 {
5039 
5040  union
5041  {
5042  __IOM uint32_t reg;
5044  struct
5045  {
5046  __IM uint32_t AMCLK1_FREQ : 6;
5049  __IM uint32_t AMCLK2_FREQ : 6;
5050  } bit;
5051  } AMCLK_FREQ_STS;
5052 
5053  union
5054  {
5055  __IOM uint32_t reg;
5057  struct
5058  {
5059  __IOM uint32_t CLKWDT_PD_N : 1;
5060  } bit;
5061  } AMCLK_CTRL;
5062  __IM uint32_t RESERVED;
5063 
5064  union
5065  {
5066  __IOM uint32_t reg;
5068  struct
5069  {
5070  __IOM uint32_t AMCLK1_UP_TH : 6;
5071  __IOM uint32_t AMCLK1_UP_HYS : 2;
5072  __IOM uint32_t AMCLK1_LOW_TH : 6;
5073  __IOM uint32_t AMCLK1_LOW_HYS : 2;
5074  __IOM uint32_t AMCLK2_UP_TH : 6;
5075  __IOM uint32_t AMCLK2_UP_HYS : 2;
5076  __IOM uint32_t AMCLK2_LOW_TH : 6;
5077  __IOM uint32_t AMCLK2_LOW_HYS : 2;
5078  } bit;
5079  } AMCLK_TH_HYS;
5080  __IM uint32_t RESERVED1;
5081 
5082  union
5083  {
5084  __IOM uint32_t reg;
5086  struct
5087  {
5088  __OM uint32_t LIN_OC_ICLR : 1;
5089  __OM uint32_t LIN_OT_ICLR : 1;
5090  __OM uint32_t LIN_TMOUT_ICLR : 1;
5091  __IM uint32_t : 3;
5092  __OM uint32_t PMU_OTWARN_ICLR : 1;
5094  __OM uint32_t PMU_OT_ICLR : 1;
5096  __OM uint32_t SYS_OTWARN_ICLR : 1;
5098  __OM uint32_t SYS_OT_ICLR : 1;
5100  __OM uint32_t REFBG_LOTHWARN_ICLR : 1;
5102  __OM uint32_t REFBG_UPTHWARN_ICLR : 1;
5104  __OM uint32_t VREF5V_LOWTH_ICLR : 1;
5106  __OM uint32_t VREF5V_UPTH_ICLR : 1;
5108  __OM uint32_t VREF5V_OVL_ICLR : 1;
5109  __OM uint32_t ADC2_ESM_ICLR : 1;
5110  uint32_t : 6;
5111  __OM uint32_t ADC3_EOC_ICLR: 1;
5112  __OM uint32_t ADC4_EOC_ICLR: 1;
5113  } bit;
5114  } SYS_ISCLR;
5115 
5116  union
5117  {
5118  __IOM uint32_t reg;
5120  struct
5121  {
5122  __IM uint32_t LIN_OC_IS : 1;
5123  __IM uint32_t LIN_OT_IS : 1;
5124  __IM uint32_t LIN_TMOUT_IS : 1;
5125  __IM uint32_t : 3;
5126  __IM uint32_t PMU_OTWARN_IS : 1;
5128  __IM uint32_t PMU_OT_IS : 1;
5130  __IM uint32_t SYS_OTWARN_IS : 1;
5132  __IM uint32_t SYS_OT_IS : 1;
5134  __IM uint32_t REFBG_LOTHWARN_IS : 1;
5136  __IM uint32_t REFBG_UPTHWARN_IS : 1;
5138  __IM uint32_t VREF5V_LOWTH_IS : 1;
5140  __IM uint32_t VREF5V_UPTH_IS : 1;
5142  __IM uint32_t VREF5V_OVL_IS : 1;
5143  __IM uint32_t ADC2_ESM_IS : 1;
5144  __IM uint32_t : 6;
5145  __IM uint32_t ADC3_EOC_IS : 1;
5146  __IM uint32_t ADC4_EOC_IS : 1;
5148  } bit;
5149  } SYS_IS;
5150 
5151  union
5152  {
5153  __IOM uint32_t reg;
5155  struct
5156  {
5157  __IM uint32_t VBAT_UV_IS : 1;
5158  __IM uint32_t VS_UV_IS : 1;
5159  __IM uint32_t VDD5V_UV_IS : 1;
5160  __IM uint32_t VDD1V5_UV_IS : 1;
5161  __IM uint32_t VBAT_OV_IS : 1;
5162  __IM uint32_t VS_OV_IS : 1;
5163  __IM uint32_t VDD5V_OV_IS : 1;
5164  __IM uint32_t VDD1V5_OV_IS : 1;
5165  __IM uint32_t : 8;
5166  __IM uint32_t VBAT_UV_STS : 1;
5167  __IM uint32_t VS_UV_STS : 1;
5168  __IM uint32_t VDD5V_UV_STS : 1;
5169  __IM uint32_t VDD1V5_UV_STS : 1;
5170  __IM uint32_t VBAT_OV_STS : 1;
5171  __IM uint32_t VS_OV_STS : 1;
5172  __IM uint32_t VDD5V_OV_STS : 1;
5173  __IM uint32_t VDD1V5_OV_STS : 1;
5174  } bit;
5175  } SYS_SUPPLY_IRQ_STS;
5176 
5177  union
5178  {
5179  __IOM uint32_t reg;
5181  struct
5182  {
5183  __IOM uint32_t VBAT_UV_IE : 1;
5184  __IOM uint32_t VS_UV_IE : 1;
5185  __IOM uint32_t VDD5V_UV_IE : 1;
5186  __IOM uint32_t VDD1V5_UV_IE : 1;
5187  __IOM uint32_t VBAT_OV_IE : 1;
5188  __IOM uint32_t VS_OV_IE : 1;
5189  __IOM uint32_t VDD5V_OV_IE : 1;
5190  __IOM uint32_t VDD1V5_OV_IE : 1;
5191  } bit;
5192  } SYS_SUPPLY_IRQ_CTRL;
5193 
5194  union
5195  {
5196  __IOM uint32_t reg;
5198  struct
5199  {
5200  __OM uint32_t VBAT_UV_ICLR : 1;
5201  __OM uint32_t VS_UV_ICLR : 1;
5202  __OM uint32_t VDD5V_UV_ICLR : 1;
5203  __OM uint32_t VDD1V5_UV_ICLR : 1;
5204  __OM uint32_t VBAT_OV_ICLR : 1;
5205  __OM uint32_t VS_OV_ICLR : 1;
5206  __OM uint32_t VDD5V_OV_ICLR : 1;
5207  __OM uint32_t VDD1V5_OV_ICLR : 1;
5208  __IM uint32_t : 8;
5209  __OM uint32_t VBAT_UV_SCLR : 1;
5210  __OM uint32_t VS_UV_SCLR : 1;
5211  __OM uint32_t VDD5V_UV_SCLR : 1;
5212  __OM uint32_t VDD1V5_UV_SCLR : 1;
5213  __OM uint32_t VBAT_OV_SCLR : 1;
5214  __OM uint32_t VS_OV_SCLR : 1;
5215  __OM uint32_t VDD5V_OV_SCLR : 1;
5216  __OM uint32_t VDD1V5_OV_SCLR : 1;
5217  } bit;
5218  } SYS_SUPPLY_IRQ_CLR;
5219 
5220  union
5221  {
5222  __IOM uint32_t reg;
5224  struct
5225  {
5226  __IOM uint32_t LIN_OC_IE : 1;
5227  __IOM uint32_t LIN_OT_IE : 1;
5228  __IOM uint32_t LIN_TMOUT_IE : 1;
5229  __IM uint32_t : 3;
5230  __IOM uint32_t PMU_OTWARN_IE : 1;
5231  __IOM uint32_t PMU_OT_IE : 1;
5233  __IOM uint32_t SYS_OTWARN_IE : 1;
5234  __IOM uint32_t SYS_OT_IE : 1;
5236  __IOM uint32_t REFBG_LOTHWARN_IE : 1;
5237  __IOM uint32_t REFBG_UPTHWARN_IE : 1;
5238  __IOM uint32_t VREF5V_LOWTH_IE : 1;
5240  __IOM uint32_t VREF5V_UPTH_IE : 1;
5242  __IOM uint32_t VREF5V_OVL_IE : 1;
5243  __IOM uint32_t ADC2_ESM_IE : 1;
5244  __IM uint32_t : 6;
5245  __IOM uint32_t ADC3_EOC_IE : 1;
5246  __IOM uint32_t ADC4_EOC_IE : 1;
5247  } bit;
5248  } SYS_IRQ_CTRL;
5249  __IM uint32_t RESERVED2;
5250 
5251  union
5252  {
5253  __IOM uint32_t reg;
5255  struct
5256  {
5257  __IM uint32_t : 1;
5258  __IOM uint32_t CLKWDT_SD_DIS : 1;
5259  __IM uint32_t : 5;
5260  __IOM uint32_t FAIL_PS_DIS : 1;
5261  __IOM uint32_t LIN_VS_UV_SD_DIS : 1;
5262  __IM uint32_t : 5;
5263  __IOM uint32_t SYS_VSD_OV_SLM_DIS : 1;
5264  __IM uint32_t : 9;
5265  __IOM uint32_t SYS_OT_PS_DIS : 1;
5266  __IOM uint32_t CLKLOSS_SD_DIS : 1;
5267  __IOM uint32_t CLKWDT_RES_SD_DIS : 1;
5268  } bit;
5269  } PCU_CTRL_STS;
5270 
5271  union
5272  {
5273  __IOM uint32_t reg;
5275  struct
5276  {
5277  __IOM uint32_t WDP_SEL : 6;
5278  __IOM uint32_t SOWCONF : 2;
5279  } bit;
5280  } WDT1_TRIG;
5281  __IM uint32_t RESERVED3[7];
5282 
5283  union
5284  {
5285  __IOM uint32_t reg;
5287  struct
5288  {
5289  __OM uint32_t LS1_DS_ICLR : 1;
5290  __OM uint32_t LS2_DS_ICLR : 1;
5291  __OM uint32_t HS1_DS_ICLR : 1;
5293  __OM uint32_t HS2_DS_ICLR : 1;
5295  __IM uint32_t : 6;
5296  __OM uint32_t LS1_OC_ICLR : 1;
5297  __OM uint32_t LS2_OC_ICLR : 1;
5298  __OM uint32_t HS1_OC_ICLR : 1;
5299  __OM uint32_t HS2_OC_ICLR : 1;
5300  __IM uint32_t : 2;
5301  __OM uint32_t VCP_LOWTH2_ICLR : 1;
5303  __OM uint32_t VCP_LOWTH1_ICLR : 1;
5305  __OM uint32_t VCP_UPTH_ICLR : 1;
5307  __OM uint32_t VSD_LOWTH_ICLR : 1;
5309  __OM uint32_t VSD_UPTH_ICLR : 1;
5311  __IM uint32_t : 3;
5312  __OM uint32_t VCP_LOWTH2_SCLR : 1;
5314  __OM uint32_t VCP_LOWTH1_SCLR : 1;
5316  __OM uint32_t VCP_UPTH_SCLR : 1;
5318  __OM uint32_t VSD_LOWTH_SCLR : 1;
5320  __OM uint32_t VSD_UPTH_SCLR : 1;
5322  } bit;
5323  } BDRV_ISCLR;
5324 
5325  union
5326  {
5327  __IOM uint32_t reg;
5329  struct
5330  {
5331  __IM uint32_t LS1_DS_IS : 1;
5332  __IM uint32_t LS2_DS_IS : 1;
5333  __IM uint32_t HS1_DS_IS : 1;
5335  __IM uint32_t HS2_DS_IS : 1;
5337  __IM uint32_t : 6;
5338  __IM uint32_t LS1_OC_IS : 1;
5339  __IM uint32_t LS2_OC_IS : 1;
5340  __IM uint32_t HS1_OC_IS : 1;
5341  __IM uint32_t HS2_OC_IS : 1;
5342  __IM uint32_t : 2;
5343  __IM uint32_t VCP_LOWTH2_IS : 1;
5345  __IM uint32_t VCP_LOWTH1_IS : 1;
5347  __IM uint32_t VCP_UPTH_IS : 1;
5349  __IM uint32_t VSD_LOWTH_IS : 1;
5351  __IM uint32_t VSD_UPTH_IS : 1;
5353  __IM uint32_t : 3;
5354  __IM uint32_t VCP_LOWTH2_STS : 1;
5356  __IM uint32_t VCP_LOWTH1_STS : 1;
5358  __IM uint32_t VCP_UPTH_STS : 1;
5360  __IM uint32_t VSD_LOWTH_STS : 1;
5362  __IM uint32_t VSD_UPTH_STS : 1;
5364  } bit;
5365  } BDRV_IS;
5366 
5367  union
5368  {
5369  __IOM uint32_t reg;
5371  struct
5372  {
5373  __IOM uint32_t LS1_DS_IE : 1;
5374  __IOM uint32_t LS2_DS_IE : 1;
5375  __IOM uint32_t HS1_DS_IE : 1;
5377  __IOM uint32_t HS2_DS_IE : 1;
5379  __IM uint32_t : 6;
5380  __IOM uint32_t LS1_OC_IE : 1;
5381  __IOM uint32_t LS2_OC_IE : 1;
5382  __IOM uint32_t HS1_OC_IE : 1;
5383  __IOM uint32_t HS2_OC_IE : 1;
5384  __IM uint32_t : 2;
5385  __IOM uint32_t VCP_LOWTH2_IE : 1;
5386  __IOM uint32_t VCP_LOWTH1_IE : 1;
5387  __IOM uint32_t VCP_UPTH_IE : 1;
5388  __IOM uint32_t VSD_LOWTH_IE : 1;
5389  __IOM uint32_t VSD_UPTH_IE : 1;
5390  } bit;
5391  } BDRV_IRQ_CTRL;
5392  __IM uint32_t RESERVED4[3];
5393 
5394  union
5395  {
5396  __IOM uint32_t reg;
5398  struct
5399  {
5400  __IOM uint32_t STCALIB : 26;
5401  } bit;
5402  } STCALIB;
5403  __IM uint32_t RESERVED5[4];
5404 
5405  union
5406  {
5407  __IOM uint32_t reg;
5409  struct
5410  {
5411  __IM uint32_t DBFSTS : 1;
5412  __IM uint32_t SBFSTS : 1;
5413  } bit;
5414  } BFSTS;
5415 
5416  union
5417  {
5418  __IOM uint32_t reg;
5420  struct
5421  {
5422  __IM uint32_t DBFA : 32;
5423  } bit;
5424  } DBFA;
5425 
5426  union
5427  {
5428  __IOM uint32_t reg;
5430  struct
5431  {
5432  __IM uint32_t SBFA : 32;
5433  } bit;
5434  } SBFA;
5435 
5436  union
5437  {
5438  __IOM uint32_t reg;
5440  struct
5441  {
5442  __OM uint32_t DBFSTSCLR : 1;
5443  __OM uint32_t SBFSTSCLR : 1;
5444  } bit;
5445  } BFSTS_CLR;
5446 } SCUPM_Type;
5450 /* =========================================================================================================================== */
5451 /* ================ SSC1 ================ */
5452 /* =========================================================================================================================== */
5453 
5454 
5459 typedef struct
5460 {
5461 
5462  union
5463  {
5464  __IOM uint16_t reg;
5466  struct
5467  {
5468  __IOM uint16_t MIS_0 : 1;
5472  __IOM uint16_t SIS : 1;
5477  __IOM uint16_t CIS : 1;
5482  __IOM uint16_t MIS_1 : 1;
5484  } bit;
5485  } PISEL;
5486  __IM uint16_t RESERVED;
5487 
5488  union
5489  {
5490  __IOM uint16_t reg;
5492  struct
5493  {
5494  __IM uint16_t BC : 4;
5496  __IM uint16_t TE : 1;
5497  __IM uint16_t RE : 1;
5498  __IM uint16_t PE : 1;
5499  __IM uint16_t BE : 1;
5500  __IM uint16_t BSY : 1;
5501  __IM uint16_t : 1;
5502  __IOM uint16_t MS : 1;
5503  __IOM uint16_t EN : 1;
5504  } bit;
5505  } CON;
5506  __IM uint16_t RESERVED1;
5507 
5508  union
5509  {
5510  __IOM uint16_t reg;
5512  struct
5513  {
5514  __IOM uint16_t TB_VALUE : 16;
5515  } bit;
5516  } TB;
5517  __IM uint16_t RESERVED2;
5518 
5519  union
5520  {
5521  __IOM uint16_t reg;
5523  struct
5524  {
5525  __IM uint16_t RB_VALUE : 16;
5526  } bit;
5527  } RB;
5528  __IM uint16_t RESERVED3;
5529 
5530  union
5531  {
5532  __IOM uint16_t reg;
5534  struct
5535  {
5536  __IOM uint16_t BR_VALUE : 16;
5537  } bit;
5538  } BR;
5539  __IM uint16_t RESERVED4;
5540 
5541  union
5542  {
5543  __IOM uint16_t reg;
5545  struct
5546  {
5547  __IM uint16_t : 8;
5548  __OM uint16_t TECLR : 1;
5549  __OM uint16_t RECLR : 1;
5550  __OM uint16_t PECLR : 1;
5551  __OM uint16_t BECLR : 1;
5552  } bit;
5553  } ISRCLR;
5554 } SSC1_Type;
5558 /* =========================================================================================================================== */
5559 /* ================ SSC2 ================ */
5560 /* =========================================================================================================================== */
5561 
5562 
5567 typedef struct
5568 {
5569 
5570  union
5571  {
5572  __IOM uint16_t reg;
5574  struct
5575  {
5576  __IOM uint16_t MIS_0 : 1;
5580  __IOM uint16_t SIS : 1;
5585  __IOM uint16_t CIS : 1;
5590  __IOM uint16_t MIS_1 : 1;
5592  } bit;
5593  } PISEL;
5594  __IM uint16_t RESERVED;
5595 
5596  union
5597  {
5598  __IOM uint16_t reg;
5600  struct
5601  {
5602  __IM uint16_t BC : 4;
5604  __IM uint16_t TE : 1;
5605  __IM uint16_t RE : 1;
5606  __IM uint16_t PE : 1;
5607  __IM uint16_t BE : 1;
5608  __IM uint16_t BSY : 1;
5609  __IM uint16_t : 1;
5610  __IOM uint16_t MS : 1;
5611  __IOM uint16_t EN : 1;
5612  } bit;
5613  } CON;
5614  __IM uint16_t RESERVED1;
5615 
5616  union
5617  {
5618  __IOM uint16_t reg;
5620  struct
5621  {
5622  __IOM uint16_t TB_VALUE : 16;
5623  } bit;
5624  } TB;
5625  __IM uint16_t RESERVED2;
5626 
5627  union
5628  {
5629  __IOM uint16_t reg;
5631  struct
5632  {
5633  __IM uint16_t RB_VALUE : 16;
5634  } bit;
5635  } RB;
5636  __IM uint16_t RESERVED3;
5637 
5638  union
5639  {
5640  __IOM uint16_t reg;
5642  struct
5643  {
5644  __IOM uint16_t BR_VALUE : 16;
5645  } bit;
5646  } BR;
5647  __IM uint16_t RESERVED4;
5648 
5649  union
5650  {
5651  __IOM uint16_t reg;
5653  struct
5654  {
5655  __IM uint16_t : 8;
5656  __OM uint16_t TECLR : 1;
5657  __OM uint16_t RECLR : 1;
5658  __OM uint16_t PECLR : 1;
5659  __OM uint16_t BECLR : 1;
5660  } bit;
5661  } ISRCLR;
5662 } SSC2_Type;
5666 /* =========================================================================================================================== */
5667 /* ================ TIMER2x ================ */
5668 /* =========================================================================================================================== */
5669 
5670 
5675 typedef struct
5676 {
5677 
5678  union
5679  {
5680  __IOM uint8_t reg;
5682  struct
5683  {
5684  __IOM uint8_t CP_RL2 : 1;
5685  __IOM uint8_t C_T2 : 1;
5686  __IOM uint8_t TR2 : 1;
5687  __IOM uint8_t EXEN2 : 1;
5689  __IM uint8_t EXF2 : 1;
5690  __IM uint8_t TF2 : 1;
5691  } bit;
5692  } T2CON;
5693  __IM uint8_t RESERVED[3];
5694 
5695  union
5696  {
5697  __IOM uint8_t reg;
5699  struct
5700  {
5701  __IOM uint8_t DCEN : 1;
5702  __IOM uint8_t T2PRE : 3;
5703  __IOM uint8_t PREN : 1;
5704  __IOM uint8_t EDGESEL : 1;
5705  __IOM uint8_t T2RHEN : 1;
5706  __IOM uint8_t T2REGS : 1;
5707  } bit;
5708  } T2MOD;
5709  __IM uint8_t RESERVED1[3];
5710 
5711  union
5712  {
5713  __IOM uint8_t reg;
5715  struct
5716  {
5717  __IOM uint8_t RC2 : 8;
5718  } bit;
5719  } RC2L;
5720  __IM uint8_t RESERVED2[3];
5721 
5722  union
5723  {
5724  __IOM uint8_t reg;
5726  struct
5727  {
5728  __IOM uint8_t RC2 : 8;
5729  } bit;
5730  } RC2H;
5731  __IM uint8_t RESERVED3[3];
5732 
5733  union
5734  {
5735  __IOM uint8_t reg;
5737  struct
5738  {
5739  __IOM uint8_t T2L : 8;
5740  } bit;
5741  } T2L;
5742  __IM uint8_t RESERVED4[3];
5743 
5744  union
5745  {
5746  __IOM uint8_t reg;
5748  struct
5749  {
5750  __IOM uint8_t T2H : 8;
5751  } bit;
5752  } T2H;
5753  __IM uint8_t RESERVED5[3];
5754 
5755  union
5756  {
5757  __IOM uint8_t reg;
5759  struct
5760  {
5761  __IOM uint8_t EXF2EN : 1;
5762  __IOM uint8_t TF2EN : 1;
5763  } bit;
5764  } T2CON1;
5765  __IM uint8_t RESERVED6[3];
5766 
5767  union
5768  {
5769  __IOM uint8_t reg;
5771  struct
5772  {
5773  __IM uint8_t : 6;
5774  __OM uint8_t EXF2CLR : 1;
5775  __OM uint8_t TF2CLR : 1;
5776  } bit;
5777  } T2ICLR;
5778 } TIMER2x_Type;
5782 /* =========================================================================================================================== */
5783 /* ================ TIMER3 ================ */
5784 /* =========================================================================================================================== */
5785 
5786 
5791 typedef struct
5792 {
5793 
5794  union
5795  {
5796  __IOM uint32_t reg;
5798  struct
5799  {
5800  __IOM uint32_t T3_TRIGG_INP_SEL : 3;
5802  __IOM uint32_t T3_RES_CONF : 2;
5803  __IOM uint32_t RETRIG : 1;
5805  } bit;
5806  } T3_TRIGG_CTRL;
5807 
5808  union
5809  {
5810  __IOM uint32_t reg;
5812  struct
5813  {
5814  __IOM uint32_t LO : 8;
5815  __IOM uint32_t HI : 8;
5816  } bit;
5817  } CMP;
5818 
5819  union
5820  {
5821  __IOM uint32_t reg;
5823  struct
5824  {
5825  __IOM uint32_t LO : 8;
5826  __IOM uint32_t HI : 8;
5827  } bit;
5828  } CNT;
5829 
5830  union
5831  {
5832  __IOM uint32_t reg;
5834  struct
5835  {
5836  __IOM uint32_t T3_PD_N : 1;
5837  __IOM uint32_t T3_RD_REQ : 1;
5838  __IOM uint32_t T3_RD_REQ_CONF : 1;
5839  __IOM uint32_t CNT_RDY : 1;
5840  __IOM uint32_t TR3H : 1;
5841  __IM uint32_t T3H_OVF_STS : 1;
5842  __IOM uint32_t TR3L : 1;
5843  __IM uint32_t T3L_OVF_STS : 1;
5844  __IOM uint32_t T3L_OVF_IE : 1;
5845  __IOM uint32_t T3H_OVF_IE : 1;
5846  } bit;
5847  } CTRL;
5848 
5849  union
5850  {
5851  __IOM uint32_t reg;
5853  struct
5854  {
5855  __IOM uint32_t T3M : 2;
5856  __IM uint32_t : 4;
5857  __IOM uint32_t T3_SUBM : 2;
5858  } bit;
5859  } MODE_CONF;
5860 
5861  union
5862  {
5863  __IOM uint32_t reg;
5865  struct
5866  {
5867  __IM uint32_t : 5;
5868  __OM uint32_t T3H_OVF_ICLR : 1;
5869  __IM uint32_t : 1;
5870  __OM uint32_t T3L_OVF_ICLR : 1;
5871  } bit;
5872  } ISRCLR;
5873 } TIMER3_Type;
5877 /* =========================================================================================================================== */
5878 /* ================ UARTx ================ */
5879 /* =========================================================================================================================== */
5880 
5881 
5886 typedef struct
5887 {
5888 
5889  union
5890  {
5891  __IOM uint8_t reg;
5893  struct
5894  {
5895  __IOM uint8_t RI : 1;
5896  __IOM uint8_t TI : 1;
5897  __IOM uint8_t RB8 : 1;
5898  __IOM uint8_t TB8 : 1;
5899  __IOM uint8_t REN : 1;
5900  __IOM uint8_t SM2 : 1;
5902  __IOM uint8_t SM1 : 1;
5903  __IOM uint8_t SM0 : 1;
5904  } bit;
5905  } SCON;
5906  __IM uint8_t RESERVED[3];
5907 
5908  union
5909  {
5910  __IOM uint8_t reg;
5912  struct
5913  {
5914  __IOM uint8_t VAL : 8;
5915  } bit;
5916  } SBUF;
5917  __IM uint8_t RESERVED1[3];
5918 
5919  union
5920  {
5921  __IOM uint8_t reg;
5923  struct
5924  {
5925  __OM uint8_t RICLR : 1;
5926  __OM uint8_t TICLR : 1;
5927  } bit;
5928  } SCONCLR;
5929 } UART_Type; /* End of group Device_Peripheral_peripherals */
5935 
5936 
5937 /* =========================================================================================================================== */
5938 /* ================ Device Specific Peripheral Address Map ================ */
5939 /* =========================================================================================================================== */
5940 
5941 
5946 #define ADC1_BASE 0x40004000UL
5947 #define ADC2_BASE 0x4801C000UL
5948 #define ADC34_BASE 0x40008000UL
5949 #define BDRV_BASE 0x40034000UL
5950 #define CCU6_BASE 0x4000C000UL
5951 #define CPU_BASE 0xE000E000UL
5952 #define CSA_BASE 0x48018000UL
5953 #define DMA_BASE 0x50014000UL
5954 #define GPT12E_BASE 0x40010000UL
5955 #define LIN_BASE 0x4801E000UL
5956 #define MF_BASE 0x48018000UL
5957 #define MON_BASE 0x50004000UL
5958 #define PMU_BASE 0x50004000UL
5959 #define PORT_BASE 0x48028000UL
5960 #define SCU_BASE 0x50005000UL
5961 #define SCUPM_BASE 0x50006000UL
5962 #define SSC1_BASE 0x48024000UL
5963 #define SSC2_BASE 0x48026000UL
5964 #define TIMER2_BASE 0x48004000UL
5965 #define TIMER21_BASE 0x48005000UL
5966 #define TIMER3_BASE 0x48006000UL
5967 #define UART1_BASE 0x48020000UL
5968 #define UART2_BASE 0x48022000UL
5969  /* End of group Device_Peripheral_peripheralAddr */
5971 
5972 
5973 /* =========================================================================================================================== */
5974 /* ================ Peripheral declaration ================ */
5975 /* =========================================================================================================================== */
5976 
5977 
5981 /* Note 923: cast from unsigned long to pointer [MISRA Rule 45] */
5982 /* disable lint warning 923, to accept the conversion of the */
5983 /* base address into a pointer of the peripheral type. */
5984 /* This is a preferable exception as it generates the fastest */
5985 /* code, compared to other solutions which do not require a */
5986 /* suppressing of this MISRA rule */
5987 
5988 
5989 #ifndef UNIT_TESTING_LV2
5990 #define ADC1 ((ADC1_Type*) ADC1_BASE)
5991 #define ADC2 ((ADC2_Type*) ADC2_BASE)
5992 #define ADC34 ((ADC34_Type*) ADC34_BASE)
5993 #define BDRV ((BDRV_Type*) BDRV_BASE)
5994 #define CCU6 ((CCU6_Type*) CCU6_BASE)
5995 #define CSA ((CSA_Type*) CSA_BASE)
5996 #define CPU ((CPU_Type*) CPU_BASE)
5997 #define DMA ((DMA_Type*) DMA_BASE)
5998 #define GPT12E ((GPT12E_Type*) GPT12E_BASE)
5999 #define LIN ((LIN_Type*) LIN_BASE)
6000 #define MF ((MF_Type*) MF_BASE)
6001 #define MON ((MON_Type*) MON_BASE)
6002 #define PMU ((PMU_Type*) PMU_BASE)
6003 #define PORT ((PORT_Type*) PORT_BASE)
6004 #define SCU ((SCU_Type*) SCU_BASE)
6005 #define SCUPM ((SCUPM_Type*) SCUPM_BASE)
6006 #define SSC1 ((SSC1_Type*) SSC1_BASE)
6007 #define SSC2 ((SSC2_Type*) SSC2_BASE)
6008 #define TIMER2 ((TIMER2x_Type*) TIMER2_BASE)
6009 #define TIMER21 ((TIMER2x_Type*) TIMER21_BASE)
6010 #define TIMER3 ((TIMER3_Type*) TIMER3_BASE)
6011 #define UART1 ((UART_Type*) UART1_BASE)
6012 #define UART2 ((UART_Type*) UART2_BASE)
6013 #else
6014 extern ADC1_Type *ADC1;
6015 extern ADC2_Type *ADC2;
6016 extern ADC34_Type *ADC34;
6017 extern BDRV_Type *BDRV;
6018 extern CCU6_Type *CCU6;
6019 extern CSA_Type *CSA;
6020 extern CPU_Type *CPU;
6021 extern DMA_Type *DMA;
6022 extern GPT12E_Type *GPT12E;
6023 extern LIN_Type *LIN;
6024 extern MF_Type *MF;
6025 extern MON_Type *MON;
6026 extern PMU_Type *PMU;
6027 extern PORT_Type *PORT;
6028 extern SCU_Type *SCU;
6029 extern SCUPM_Type *SCUPM;
6030 extern SSC1_Type *SSC1;
6031 extern SSC2_Type *SSC2;
6032 extern TIMER2x_Type *TIMER2;
6033 extern TIMER2x_Type *TIMER21;
6034 extern TIMER3_Type *TIMER3;
6035 extern UART_Type *UART1;
6036 extern UART_Type *UART2;
6037 #endif /* UNIT_TESTING_LV2 */
6038 
6039 
6040  /* End of group Device_Peripheral_declaration */
6042 
6043 
6044 /* =========================================================================================================================== */
6045 /* ================ Pos/Mask Peripheral Section ================ */
6046 /* =========================================================================================================================== */
6047 
6048 
6054 /* violation: Identifier clash */
6055 /* =========================================================================================================================== */
6056 /* ================ ADC1 ================ */
6057 /* =========================================================================================================================== */
6058 
6059 /* ======================================================== CHx_EIM ======================================================== */
6060 #define ADC1_CHx_EIM_TRIG_SEL_Pos (16UL)
6061 #define ADC1_CHx_EIM_TRIG_SEL_Msk (0x70000UL)
6062 #define ADC1_CHx_EIM_REP_Pos (4UL)
6063 #define ADC1_CHx_EIM_REP_Msk (0x70UL)
6064 #define ADC1_CHx_EIM_CHx_Pos (0UL)
6065 #define ADC1_CHx_EIM_CHx_Msk (0x7UL)
6066 /* ======================================================== CHx_ESM ======================================================== */
6067 #define ADC1_CHx_ESM_TRIG_SEL_Pos (16UL)
6068 #define ADC1_CHx_ESM_TRIG_SEL_Msk (0x70000UL)
6069 #define ADC1_CHx_ESM_ESM_0_Pos (0UL)
6070 #define ADC1_CHx_ESM_ESM_0_Msk (0xffUL)
6071 /* ======================================================= CTRL_STS ======================================================== */
6072 #define ADC1_CTRL_STS_IN_MUX_SEL_Pos (4UL)
6073 #define ADC1_CTRL_STS_IN_MUX_SEL_Msk (0x70UL)
6074 #define ADC1_CTRL_STS_EOC_Pos (3UL)
6075 #define ADC1_CTRL_STS_EOC_Msk (0x8UL)
6076 #define ADC1_CTRL_STS_SOC_Pos (2UL)
6077 #define ADC1_CTRL_STS_SOC_Msk (0x4UL)
6078 #define ADC1_CTRL_STS_PD_N_Pos (0UL)
6079 #define ADC1_CTRL_STS_PD_N_Msk (0x1UL)
6080 /* ========================================================= DWSEL ========================================================= */
6081 #define ADC1_DWSEL_ch7_Pos (7UL)
6082 #define ADC1_DWSEL_ch7_Msk (0x80UL)
6083 #define ADC1_DWSEL_ch6_Pos (6UL)
6084 #define ADC1_DWSEL_ch6_Msk (0x40UL)
6085 #define ADC1_DWSEL_ch5_Pos (5UL)
6086 #define ADC1_DWSEL_ch5_Msk (0x20UL)
6087 #define ADC1_DWSEL_ch4_Pos (4UL)
6088 #define ADC1_DWSEL_ch4_Msk (0x10UL)
6089 #define ADC1_DWSEL_ch3_Pos (3UL)
6090 #define ADC1_DWSEL_ch3_Msk (0x8UL)
6091 #define ADC1_DWSEL_ch2_Pos (2UL)
6092 #define ADC1_DWSEL_ch2_Msk (0x4UL)
6093 #define ADC1_DWSEL_ch1_Pos (1UL)
6094 #define ADC1_DWSEL_ch1_Msk (0x2UL)
6095 #define ADC1_DWSEL_ch0_Pos (0UL)
6096 #define ADC1_DWSEL_ch0_Msk (0x1UL)
6097 /* ======================================================== GLOBCTR ======================================================== */
6098 #define ADC1_GLOBCTR_ANON_Pos (8UL)
6099 #define ADC1_GLOBCTR_ANON_Msk (0x300UL)
6100 #define ADC1_GLOBCTR_DIVA_Pos (0UL)
6101 #define ADC1_GLOBCTR_DIVA_Msk (0x3fUL)
6102 /* ======================================================== GLOBSTR ======================================================== */
6103 #define ADC1_GLOBSTR_ANON_ST_Pos (8UL)
6104 #define ADC1_GLOBSTR_ANON_ST_Msk (0x300UL)
6105 #define ADC1_GLOBSTR_CHNR_Pos (3UL)
6106 #define ADC1_GLOBSTR_CHNR_Msk (0x38UL)
6107 #define ADC1_GLOBSTR_SAMPLE_Pos (1UL)
6108 #define ADC1_GLOBSTR_SAMPLE_Msk (0x2UL)
6109 #define ADC1_GLOBSTR_BUSY_Pos (0UL)
6110 #define ADC1_GLOBSTR_BUSY_Msk (0x1UL)
6111 /* ========================================================= ICLR ========================================================== */
6112 #define ADC1_ICLR_ESM_ICLR_Pos (9UL)
6113 #define ADC1_ICLR_ESM_ICLR_Msk (0x200UL)
6114 #define ADC1_ICLR_EIM_ICLR_Pos (8UL)
6115 #define ADC1_ICLR_EIM_ICLR_Msk (0x100UL)
6116 #define ADC1_ICLR_CH7_ICLR_Pos (7UL)
6117 #define ADC1_ICLR_CH7_ICLR_Msk (0x80UL)
6118 #define ADC1_ICLR_CH6_ICLR_Pos (6UL)
6119 #define ADC1_ICLR_CH6_ICLR_Msk (0x40UL)
6120 #define ADC1_ICLR_CH5_ICLR_Pos (5UL)
6121 #define ADC1_ICLR_CH5_ICLR_Msk (0x20UL)
6122 #define ADC1_ICLR_CH4_ICLR_Pos (4UL)
6123 #define ADC1_ICLR_CH4_ICLR_Msk (0x10UL)
6124 #define ADC1_ICLR_CH3_ICLR_Pos (3UL)
6125 #define ADC1_ICLR_CH3_ICLR_Msk (0x8UL)
6126 #define ADC1_ICLR_CH2_ICLR_Pos (2UL)
6127 #define ADC1_ICLR_CH2_ICLR_Msk (0x4UL)
6128 #define ADC1_ICLR_CH1_ICLR_Pos (1UL)
6129 #define ADC1_ICLR_CH1_ICLR_Msk (0x2UL)
6130 #define ADC1_ICLR_CH0_ICLR_Pos (0UL)
6131 #define ADC1_ICLR_CH0_ICLR_Msk (0x1UL)
6132 /* ========================================================== IE =========================================================== */
6133 #define ADC1_IE_ESM_IE_Pos (9UL)
6134 #define ADC1_IE_ESM_IE_Msk (0x200UL)
6135 #define ADC1_IE_EIM_IE_Pos (8UL)
6136 #define ADC1_IE_EIM_IE_Msk (0x100UL)
6137 #define ADC1_IE_CH7_IE_Pos (7UL)
6138 #define ADC1_IE_CH7_IE_Msk (0x80UL)
6139 #define ADC1_IE_CH6_IE_Pos (6UL)
6140 #define ADC1_IE_CH6_IE_Msk (0x40UL)
6141 #define ADC1_IE_CH5_IE_Pos (5UL)
6142 #define ADC1_IE_CH5_IE_Msk (0x20UL)
6143 #define ADC1_IE_CH4_IE_Pos (4UL)
6144 #define ADC1_IE_CH4_IE_Msk (0x10UL)
6145 #define ADC1_IE_CH3_IE_Pos (3UL)
6146 #define ADC1_IE_CH3_IE_Msk (0x8UL)
6147 #define ADC1_IE_CH2_IE_Pos (2UL)
6148 #define ADC1_IE_CH2_IE_Msk (0x4UL)
6149 #define ADC1_IE_CH1_IE_Pos (1UL)
6150 #define ADC1_IE_CH1_IE_Msk (0x2UL)
6151 #define ADC1_IE_CH0_IE_Pos (0UL)
6152 #define ADC1_IE_CH0_IE_Msk (0x1UL)
6153 /* ========================================================== IS =========================================================== */
6154 #define ADC1_IS_ESM_STS_Pos (9UL)
6155 #define ADC1_IS_ESM_STS_Msk (0x200UL)
6156 #define ADC1_IS_EIM_STS_Pos (8UL)
6157 #define ADC1_IS_EIM_STS_Msk (0x100UL)
6158 #define ADC1_IS_CH7_STS_Pos (7UL)
6159 #define ADC1_IS_CH7_STS_Msk (0x80UL)
6160 #define ADC1_IS_CH6_STS_Pos (6UL)
6161 #define ADC1_IS_CH6_STS_Msk (0x40UL)
6162 #define ADC1_IS_CH5_STS_Pos (5UL)
6163 #define ADC1_IS_CH5_STS_Msk (0x20UL)
6164 #define ADC1_IS_CH4_STS_Pos (4UL)
6165 #define ADC1_IS_CH4_STS_Msk (0x10UL)
6166 #define ADC1_IS_CH3_STS_Pos (3UL)
6167 #define ADC1_IS_CH3_STS_Msk (0x8UL)
6168 #define ADC1_IS_CH2_STS_Pos (2UL)
6169 #define ADC1_IS_CH2_STS_Msk (0x4UL)
6170 #define ADC1_IS_CH1_STS_Pos (1UL)
6171 #define ADC1_IS_CH1_STS_Msk (0x2UL)
6172 #define ADC1_IS_CH0_STS_Pos (0UL)
6173 #define ADC1_IS_CH0_STS_Msk (0x1UL)
6174 /* ======================================================= RES_OUT0 ======================================================== */
6175 #define ADC1_RES_OUT0_OF0_Pos (18UL)
6176 #define ADC1_RES_OUT0_OF0_Msk (0x40000UL)
6177 #define ADC1_RES_OUT0_VF0_Pos (17UL)
6178 #define ADC1_RES_OUT0_VF0_Msk (0x20000UL)
6179 #define ADC1_RES_OUT0_WFR0_Pos (16UL)
6180 #define ADC1_RES_OUT0_WFR0_Msk (0x10000UL)
6181 #define ADC1_RES_OUT0_OUT_CH0_Pos (0UL)
6182 #define ADC1_RES_OUT0_OUT_CH0_Msk (0xfffUL)
6183 /* ======================================================= RES_OUT1 ======================================================== */
6184 #define ADC1_RES_OUT1_OF1_Pos (18UL)
6185 #define ADC1_RES_OUT1_OF1_Msk (0x40000UL)
6186 #define ADC1_RES_OUT1_VF1_Pos (17UL)
6187 #define ADC1_RES_OUT1_VF1_Msk (0x20000UL)
6188 #define ADC1_RES_OUT1_WFR1_Pos (16UL)
6189 #define ADC1_RES_OUT1_WFR1_Msk (0x10000UL)
6190 #define ADC1_RES_OUT1_OUT_CH1_Pos (0UL)
6191 #define ADC1_RES_OUT1_OUT_CH1_Msk (0xfffUL)
6192 /* ======================================================= RES_OUT2 ======================================================== */
6193 #define ADC1_RES_OUT2_OF2_Pos (18UL)
6194 #define ADC1_RES_OUT2_OF2_Msk (0x40000UL)
6195 #define ADC1_RES_OUT2_VF2_Pos (17UL)
6196 #define ADC1_RES_OUT2_VF2_Msk (0x20000UL)
6197 #define ADC1_RES_OUT2_WFR2_Pos (16UL)
6198 #define ADC1_RES_OUT2_WFR2_Msk (0x10000UL)
6199 #define ADC1_RES_OUT2_OUT_CH2_Pos (0UL)
6200 #define ADC1_RES_OUT2_OUT_CH2_Msk (0xfffUL)
6201 /* ======================================================= RES_OUT3 ======================================================== */
6202 #define ADC1_RES_OUT3_OF3_Pos (18UL)
6203 #define ADC1_RES_OUT3_OF3_Msk (0x40000UL)
6204 #define ADC1_RES_OUT3_VF3_Pos (17UL)
6205 #define ADC1_RES_OUT3_VF3_Msk (0x20000UL)
6206 #define ADC1_RES_OUT3_WFR3_Pos (16UL)
6207 #define ADC1_RES_OUT3_WFR3_Msk (0x10000UL)
6208 #define ADC1_RES_OUT3_OUT_CH3_Pos (0UL)
6209 #define ADC1_RES_OUT3_OUT_CH3_Msk (0xfffUL)
6210 /* ======================================================= RES_OUT4 ======================================================== */
6211 #define ADC1_RES_OUT4_OF4_Pos (18UL)
6212 #define ADC1_RES_OUT4_OF4_Msk (0x40000UL)
6213 #define ADC1_RES_OUT4_VF4_Pos (17UL)
6214 #define ADC1_RES_OUT4_VF4_Msk (0x20000UL)
6215 #define ADC1_RES_OUT4_WFR4_Pos (16UL)
6216 #define ADC1_RES_OUT4_WFR4_Msk (0x10000UL)
6217 #define ADC1_RES_OUT4_OUT_CH4_Pos (0UL)
6218 #define ADC1_RES_OUT4_OUT_CH4_Msk (0xfffUL)
6219 /* ======================================================= RES_OUT5 ======================================================== */
6220 #define ADC1_RES_OUT5_OF5_Pos (18UL)
6221 #define ADC1_RES_OUT5_OF5_Msk (0x40000UL)
6222 #define ADC1_RES_OUT5_VF5_Pos (17UL)
6223 #define ADC1_RES_OUT5_VF5_Msk (0x20000UL)
6224 #define ADC1_RES_OUT5_WFR5_Pos (16UL)
6225 #define ADC1_RES_OUT5_WFR5_Msk (0x10000UL)
6226 #define ADC1_RES_OUT5_OUT_CH5_Pos (0UL)
6227 #define ADC1_RES_OUT5_OUT_CH5_Msk (0xfffUL)
6228 /* ======================================================= RES_OUT6 ======================================================== */
6229 #define ADC1_RES_OUT6_OF6_Pos (18UL)
6230 #define ADC1_RES_OUT6_OF6_Msk (0x40000UL)
6231 #define ADC1_RES_OUT6_VF6_Pos (17UL)
6232 #define ADC1_RES_OUT6_VF6_Msk (0x20000UL)
6233 #define ADC1_RES_OUT6_WFR6_Pos (16UL)
6234 #define ADC1_RES_OUT6_WFR6_Msk (0x10000UL)
6235 #define ADC1_RES_OUT6_OUT_CH6_Pos (0UL)
6236 #define ADC1_RES_OUT6_OUT_CH6_Msk (0xfffUL)
6237 /* ======================================================= RES_OUT7 ======================================================== */
6238 #define ADC1_RES_OUT7_OF7_Pos (18UL)
6239 #define ADC1_RES_OUT7_OF7_Msk (0x40000UL)
6240 #define ADC1_RES_OUT7_VF7_Pos (17UL)
6241 #define ADC1_RES_OUT7_VF7_Msk (0x20000UL)
6242 #define ADC1_RES_OUT7_WFR7_Pos (16UL)
6243 #define ADC1_RES_OUT7_WFR7_Msk (0x10000UL)
6244 #define ADC1_RES_OUT7_OUT_CH7_Pos (0UL)
6245 #define ADC1_RES_OUT7_OUT_CH7_Msk (0xfffUL)
6246 /* ====================================================== RES_OUT_EIM ====================================================== */
6247 #define ADC1_RES_OUT_EIM_OF8_Pos (18UL)
6248 #define ADC1_RES_OUT_EIM_OF8_Msk (0x40000UL)
6249 #define ADC1_RES_OUT_EIM_VF8_Pos (17UL)
6250 #define ADC1_RES_OUT_EIM_VF8_Msk (0x20000UL)
6251 #define ADC1_RES_OUT_EIM_WFR8_Pos (16UL)
6252 #define ADC1_RES_OUT_EIM_WFR8_Msk (0x10000UL)
6253 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos (0UL)
6254 #define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk (0xfffUL)
6255 /* ========================================================= SQ1_4 ========================================================= */
6256 #define ADC1_SQ1_4_SQ4_Pos (24UL)
6257 #define ADC1_SQ1_4_SQ4_Msk (0xff000000UL)
6258 #define ADC1_SQ1_4_SQ3_Pos (16UL)
6259 #define ADC1_SQ1_4_SQ3_Msk (0xff0000UL)
6260 #define ADC1_SQ1_4_SQ2_Pos (8UL)
6261 #define ADC1_SQ1_4_SQ2_Msk (0xff00UL)
6262 #define ADC1_SQ1_4_SQ1_Pos (0UL)
6263 #define ADC1_SQ1_4_SQ1_Msk (0xffUL)
6264 /* ========================================================= SQ5_8 ========================================================= */
6265 #define ADC1_SQ5_8_SQ8_Pos (24UL)
6266 #define ADC1_SQ5_8_SQ8_Msk (0xff000000UL)
6267 #define ADC1_SQ5_8_SQ7_Pos (16UL)
6268 #define ADC1_SQ5_8_SQ7_Msk (0xff0000UL)
6269 #define ADC1_SQ5_8_SQ6_Pos (8UL)
6270 #define ADC1_SQ5_8_SQ6_Msk (0xff00UL)
6271 #define ADC1_SQ5_8_SQ5_Pos (0UL)
6272 #define ADC1_SQ5_8_SQ5_Msk (0xffUL)
6273 /* ========================================================= SQ_FB ========================================================= */
6274 #define ADC1_SQ_FB_CHx_Pos (16UL)
6275 #define ADC1_SQ_FB_CHx_Msk (0x70000UL)
6276 #define ADC1_SQ_FB_SQx_Pos (11UL)
6277 #define ADC1_SQ_FB_SQx_Msk (0x3800UL)
6278 #define ADC1_SQ_FB_ESM_ACTIVE_Pos (10UL)
6279 #define ADC1_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6280 #define ADC1_SQ_FB_EIM_ACTIVE_Pos (9UL)
6281 #define ADC1_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6282 #define ADC1_SQ_FB_SQ_RUN_Pos (8UL)
6283 #define ADC1_SQ_FB_SQ_RUN_Msk (0x100UL)
6284 /* ======================================================== STC_0_3 ======================================================== */
6285 #define ADC1_STC_0_3_ch3_Pos (24UL)
6286 #define ADC1_STC_0_3_ch3_Msk (0xff000000UL)
6287 #define ADC1_STC_0_3_ch2_Pos (16UL)
6288 #define ADC1_STC_0_3_ch2_Msk (0xff0000UL)
6289 #define ADC1_STC_0_3_ch1_Pos (8UL)
6290 #define ADC1_STC_0_3_ch1_Msk (0xff00UL)
6291 #define ADC1_STC_0_3_ch0_Pos (0UL)
6292 #define ADC1_STC_0_3_ch0_Msk (0xffUL)
6293 /* ======================================================== STC_4_7 ======================================================== */
6294 #define ADC1_STC_4_7_ch7_Pos (24UL)
6295 #define ADC1_STC_4_7_ch7_Msk (0xff000000UL)
6296 #define ADC1_STC_4_7_ch6_Pos (16UL)
6297 #define ADC1_STC_4_7_ch6_Msk (0xff0000UL)
6298 #define ADC1_STC_4_7_ch5_Pos (8UL)
6299 #define ADC1_STC_4_7_ch5_Msk (0xff00UL)
6300 #define ADC1_STC_4_7_ch4_Pos (0UL)
6301 #define ADC1_STC_4_7_ch4_Msk (0xffUL)
6304 /* =========================================================================================================================== */
6305 /* ================ ADC2 ================ */
6306 /* =========================================================================================================================== */
6307 
6308 /* ======================================================= CAL_CH0_1 ======================================================= */
6309 #define ADC2_CAL_CH0_1_GAIN_CH1_Pos (24UL)
6310 #define ADC2_CAL_CH0_1_GAIN_CH1_Msk (0xff000000UL)
6311 #define ADC2_CAL_CH0_1_OFFS_CH1_Pos (16UL)
6312 #define ADC2_CAL_CH0_1_OFFS_CH1_Msk (0xff0000UL)
6313 #define ADC2_CAL_CH0_1_GAIN_CH0_Pos (8UL)
6314 #define ADC2_CAL_CH0_1_GAIN_CH0_Msk (0xff00UL)
6315 #define ADC2_CAL_CH0_1_OFFS_CH0_Pos (0UL)
6316 #define ADC2_CAL_CH0_1_OFFS_CH0_Msk (0xffUL)
6317 /* ======================================================= CAL_CH2_3 ======================================================= */
6318 #define ADC2_CAL_CH2_3_GAIN_CH3_Pos (24UL)
6319 #define ADC2_CAL_CH2_3_GAIN_CH3_Msk (0xff000000UL)
6320 #define ADC2_CAL_CH2_3_OFFS_CH3_Pos (16UL)
6321 #define ADC2_CAL_CH2_3_OFFS_CH3_Msk (0xff0000UL)
6322 #define ADC2_CAL_CH2_3_GAIN_CH2_Pos (8UL)
6323 #define ADC2_CAL_CH2_3_GAIN_CH2_Msk (0xff00UL)
6324 #define ADC2_CAL_CH2_3_OFFS_CH2_Pos (0UL)
6325 #define ADC2_CAL_CH2_3_OFFS_CH2_Msk (0xffUL)
6326 /* ======================================================= CAL_CH4_5 ======================================================= */
6327 #define ADC2_CAL_CH4_5_GAIN_CH5_Pos (24UL)
6328 #define ADC2_CAL_CH4_5_GAIN_CH5_Msk (0xff000000UL)
6329 #define ADC2_CAL_CH4_5_OFFS_CH5_Pos (16UL)
6330 #define ADC2_CAL_CH4_5_OFFS_CH5_Msk (0xff0000UL)
6331 #define ADC2_CAL_CH4_5_GAIN_CH4_Pos (8UL)
6332 #define ADC2_CAL_CH4_5_GAIN_CH4_Msk (0xff00UL)
6333 #define ADC2_CAL_CH4_5_OFFS_CH4_Pos (0UL)
6334 #define ADC2_CAL_CH4_5_OFFS_CH4_Msk (0xffUL)
6335 /* ======================================================= CAL_CH6_7 ======================================================= */
6336 #define ADC2_CAL_CH6_7_GAIN_CH7_Pos (24UL)
6337 #define ADC2_CAL_CH6_7_GAIN_CH7_Msk (0xff000000UL)
6338 #define ADC2_CAL_CH6_7_OFFS_CH7_Pos (16UL)
6339 #define ADC2_CAL_CH6_7_OFFS_CH7_Msk (0xff0000UL)
6340 #define ADC2_CAL_CH6_7_GAIN_CH6_Pos (8UL)
6341 #define ADC2_CAL_CH6_7_GAIN_CH6_Msk (0xff00UL)
6342 #define ADC2_CAL_CH6_7_OFFS_CH6_Pos (0UL)
6343 #define ADC2_CAL_CH6_7_OFFS_CH6_Msk (0xffUL)
6344 /* ======================================================= CAL_CH8_9 ======================================================= */
6345 #define ADC2_CAL_CH8_9_GAIN_CH9_Pos (24UL)
6346 #define ADC2_CAL_CH8_9_GAIN_CH9_Msk (0xff000000UL)
6347 #define ADC2_CAL_CH8_9_OFFS_CH9_Pos (16UL)
6348 #define ADC2_CAL_CH8_9_OFFS_CH9_Msk (0xff0000UL)
6349 #define ADC2_CAL_CH8_9_GAIN_CH8_Pos (8UL)
6350 #define ADC2_CAL_CH8_9_GAIN_CH8_Msk (0xff00UL)
6351 #define ADC2_CAL_CH8_9_OFFS_CH8_Pos (0UL)
6352 #define ADC2_CAL_CH8_9_OFFS_CH8_Msk (0xffUL)
6353 /* ======================================================== CHx_EIM ======================================================== */
6354 #define ADC2_CHx_EIM_SEL_Pos (12UL)
6355 #define ADC2_CHx_EIM_SEL_Msk (0x1000UL)
6356 #define ADC2_CHx_EIM_EN_Pos (11UL)
6357 #define ADC2_CHx_EIM_EN_Msk (0x800UL)
6358 #define ADC2_CHx_EIM_REP_Pos (8UL)
6359 #define ADC2_CHx_EIM_REP_Msk (0x700UL)
6360 #define ADC2_CHx_EIM_CHx_Pos (0UL)
6361 #define ADC2_CHx_EIM_CHx_Msk (0x1fUL)
6362 /* ======================================================== CHx_ESM ======================================================== */
6363 #define ADC2_CHx_ESM_STS_Pos (17UL)
6364 #define ADC2_CHx_ESM_STS_Msk (0x20000UL)
6365 #define ADC2_CHx_ESM_EN_Pos (16UL)
6366 #define ADC2_CHx_ESM_EN_Msk (0x10000UL)
6367 #define ADC2_CHx_ESM_SEL_Pos (10UL)
6368 #define ADC2_CHx_ESM_SEL_Msk (0x400UL)
6369 #define ADC2_CHx_ESM_ESM_1_Pos (6UL)
6370 #define ADC2_CHx_ESM_ESM_1_Msk (0x3c0UL)
6371 #define ADC2_CHx_ESM_ESM_0_Pos (0UL)
6372 #define ADC2_CHx_ESM_ESM_0_Msk (0x3fUL)
6373 /* ===================================================== CNT0_3_LOWER ====================================================== */
6374 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Pos (27UL)
6375 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Msk (0x18000000UL)
6376 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Pos (24UL)
6377 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Msk (0x7000000UL)
6378 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Pos (19UL)
6379 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Msk (0x180000UL)
6380 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Pos (16UL)
6381 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Msk (0x70000UL)
6382 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Pos (11UL)
6383 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Msk (0x1800UL)
6384 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Pos (8UL)
6385 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Msk (0x700UL)
6386 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Pos (3UL)
6387 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Msk (0x18UL)
6388 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Pos (0UL)
6389 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Msk (0x7UL)
6390 /* ===================================================== CNT0_3_UPPER ====================================================== */
6391 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Pos (27UL)
6392 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Msk (0x18000000UL)
6393 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Pos (24UL)
6394 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Msk (0x7000000UL)
6395 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Pos (19UL)
6396 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Msk (0x180000UL)
6397 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Pos (16UL)
6398 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Msk (0x70000UL)
6399 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Pos (11UL)
6400 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Msk (0x1800UL)
6401 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Pos (8UL)
6402 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Msk (0x700UL)
6403 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Pos (3UL)
6404 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Msk (0x18UL)
6405 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Pos (0UL)
6406 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Msk (0x7UL)
6407 /* ===================================================== CNT4_5_LOWER ====================================================== */
6408 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Pos (11UL)
6409 #define ADC2_CNT4_5_LOWER_HYST_LO_CH5_Msk (0x1800UL)
6410 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Pos (8UL)
6411 #define ADC2_CNT4_5_LOWER_CNT_LO_CH5_Msk (0x700UL)
6412 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Pos (3UL)
6413 #define ADC2_CNT4_5_LOWER_HYST_LO_CH4_Msk (0x18UL)
6414 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Pos (0UL)
6415 #define ADC2_CNT4_5_LOWER_CNT_LO_CH4_Msk (0x7UL)
6416 /* ===================================================== CNT4_5_UPPER ====================================================== */
6417 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Pos (11UL)
6418 #define ADC2_CNT4_5_UPPER_HYST_UP_CH5_Msk (0x1800UL)
6419 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Pos (8UL)
6420 #define ADC2_CNT4_5_UPPER_CNT_UP_CH5_Msk (0x700UL)
6421 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Pos (3UL)
6422 #define ADC2_CNT4_5_UPPER_HYST_UP_CH4_Msk (0x18UL)
6423 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Pos (0UL)
6424 #define ADC2_CNT4_5_UPPER_CNT_UP_CH4_Msk (0x7UL)
6425 /* ===================================================== CNT6_9_LOWER ====================================================== */
6426 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Pos (27UL)
6427 #define ADC2_CNT6_9_LOWER_HYST_LO_CH9_Msk (0x18000000UL)
6428 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Pos (24UL)
6429 #define ADC2_CNT6_9_LOWER_CNT_LO_CH9_Msk (0x7000000UL)
6430 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Pos (19UL)
6431 #define ADC2_CNT6_9_LOWER_HYST_LO_CH8_Msk (0x180000UL)
6432 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Pos (16UL)
6433 #define ADC2_CNT6_9_LOWER_CNT_LO_CH8_Msk (0x70000UL)
6434 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Pos (11UL)
6435 #define ADC2_CNT6_9_LOWER_HYST_LO_CH7_Msk (0x1800UL)
6436 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Pos (8UL)
6437 #define ADC2_CNT6_9_LOWER_CNT_LO_CH7_Msk (0x700UL)
6438 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Pos (3UL)
6439 #define ADC2_CNT6_9_LOWER_HYST_LO_CH6_Msk (0x18UL)
6440 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Pos (0UL)
6441 #define ADC2_CNT6_9_LOWER_CNT_LO_CH6_Msk (0x7UL)
6442 /* ===================================================== CNT6_9_UPPER ====================================================== */
6443 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Pos (27UL)
6444 #define ADC2_CNT6_9_UPPER_HYST_UP_CH9_Msk (0x18000000UL)
6445 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Pos (24UL)
6446 #define ADC2_CNT6_9_UPPER_CNT_UP_CH9_Msk (0x7000000UL)
6447 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Pos (19UL)
6448 #define ADC2_CNT6_9_UPPER_HYST_UP_CH8_Msk (0x180000UL)
6449 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Pos (16UL)
6450 #define ADC2_CNT6_9_UPPER_CNT_UP_CH8_Msk (0x70000UL)
6451 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Pos (11UL)
6452 #define ADC2_CNT6_9_UPPER_HYST_UP_CH7_Msk (0x1800UL)
6453 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Pos (8UL)
6454 #define ADC2_CNT6_9_UPPER_CNT_UP_CH7_Msk (0x700UL)
6455 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Pos (3UL)
6456 #define ADC2_CNT6_9_UPPER_HYST_UP_CH6_Msk (0x18UL)
6457 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Pos (0UL)
6458 #define ADC2_CNT6_9_UPPER_CNT_UP_CH6_Msk (0x7UL)
6459 /* ========================================================= CTRL1 ========================================================= */
6460 #define ADC2_CTRL1_CALIB_EN_Pos (0UL)
6461 #define ADC2_CTRL1_CALIB_EN_Msk (0x3fUL)
6462 /* ========================================================= CTRL2 ========================================================= */
6463 #define ADC2_CTRL2_SEL_TS_COUNT_Pos (16UL)
6464 #define ADC2_CTRL2_SEL_TS_COUNT_Msk (0xf0000UL)
6465 #define ADC2_CTRL2_SAMPLE_TIME_int_Pos (8UL)
6466 #define ADC2_CTRL2_SAMPLE_TIME_int_Msk (0xf00UL)
6467 #define ADC2_CTRL2_MCM_RDY_Pos (7UL)
6468 #define ADC2_CTRL2_MCM_RDY_Msk (0x80UL)
6469 #define ADC2_CTRL2_TSENSE_SD_SEL_Pos (2UL)
6470 #define ADC2_CTRL2_TSENSE_SD_SEL_Msk (0x4UL)
6471 #define ADC2_CTRL2_TS_SD_SEL_CONF_Pos (1UL)
6472 #define ADC2_CTRL2_TS_SD_SEL_CONF_Msk (0x2UL)
6473 #define ADC2_CTRL2_MCM_PD_N_Pos (0UL)
6474 #define ADC2_CTRL2_MCM_PD_N_Msk (0x1UL)
6475 /* ========================================================= CTRL4 ========================================================= */
6476 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Pos (8UL)
6477 #define ADC2_CTRL4_FILT_OUT_SEL_9_6_Msk (0xf00UL)
6478 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Pos (0UL)
6479 #define ADC2_CTRL4_FILT_OUT_SEL_5_0_Msk (0x3fUL)
6480 /* ======================================================= CTRL_STS ======================================================== */
6481 #define ADC2_CTRL_STS_VS_RANGE_Pos (17UL)
6482 #define ADC2_CTRL_STS_VS_RANGE_Msk (0x20000UL)
6483 #define ADC2_CTRL_STS_VBAT_RANGE_Pos (16UL)
6484 #define ADC2_CTRL_STS_VBAT_RANGE_Msk (0x10000UL)
6485 /* ===================================================== FILT_LO_CTRL ====================================================== */
6486 #define ADC2_FILT_LO_CTRL_Ch5_EN_Pos (5UL)
6487 #define ADC2_FILT_LO_CTRL_Ch5_EN_Msk (0x20UL)
6488 #define ADC2_FILT_LO_CTRL_Ch4_EN_Pos (4UL)
6489 #define ADC2_FILT_LO_CTRL_Ch4_EN_Msk (0x10UL)
6490 #define ADC2_FILT_LO_CTRL_Ch3_EN_Pos (3UL)
6491 #define ADC2_FILT_LO_CTRL_Ch3_EN_Msk (0x8UL)
6492 #define ADC2_FILT_LO_CTRL_Ch2_EN_Pos (2UL)
6493 #define ADC2_FILT_LO_CTRL_Ch2_EN_Msk (0x4UL)
6494 #define ADC2_FILT_LO_CTRL_Ch1_EN_Pos (1UL)
6495 #define ADC2_FILT_LO_CTRL_Ch1_EN_Msk (0x2UL)
6496 #define ADC2_FILT_LO_CTRL_Ch0_EN_Pos (0UL)
6497 #define ADC2_FILT_LO_CTRL_Ch0_EN_Msk (0x1UL)
6498 /* ======================================================= FILT_OUT0 ======================================================= */
6499 #define ADC2_FILT_OUT0_OUT_CH0_Pos (0UL)
6500 #define ADC2_FILT_OUT0_OUT_CH0_Msk (0x3ffUL)
6501 /* ======================================================= FILT_OUT1 ======================================================= */
6502 #define ADC2_FILT_OUT1_OUT_CH1_Pos (0UL)
6503 #define ADC2_FILT_OUT1_OUT_CH1_Msk (0x3ffUL)
6504 /* ======================================================= FILT_OUT2 ======================================================= */
6505 #define ADC2_FILT_OUT2_OUT_CH2_Pos (0UL)
6506 #define ADC2_FILT_OUT2_OUT_CH2_Msk (0x3ffUL)
6507 /* ======================================================= FILT_OUT3 ======================================================= */
6508 #define ADC2_FILT_OUT3_OUT_CH3_Pos (0UL)
6509 #define ADC2_FILT_OUT3_OUT_CH3_Msk (0x3ffUL)
6510 /* ======================================================= FILT_OUT4 ======================================================= */
6511 #define ADC2_FILT_OUT4_OUT_CH4_Pos (0UL)
6512 #define ADC2_FILT_OUT4_OUT_CH4_Msk (0x3ffUL)
6513 /* ======================================================= FILT_OUT5 ======================================================= */
6514 #define ADC2_FILT_OUT5_OUT_CH5_Pos (0UL)
6515 #define ADC2_FILT_OUT5_OUT_CH5_Msk (0x3ffUL)
6516 /* ======================================================= FILT_OUT6 ======================================================= */
6517 #define ADC2_FILT_OUT6_OUT_CH6_Pos (0UL)
6518 #define ADC2_FILT_OUT6_OUT_CH6_Msk (0x3ffUL)
6519 /* ======================================================= FILT_OUT7 ======================================================= */
6520 #define ADC2_FILT_OUT7_OUT_CH7_Pos (0UL)
6521 #define ADC2_FILT_OUT7_OUT_CH7_Msk (0x3ffUL)
6522 /* ======================================================= FILT_OUT8 ======================================================= */
6523 #define ADC2_FILT_OUT8_OUT_CH8_Pos (0UL)
6524 #define ADC2_FILT_OUT8_OUT_CH8_Msk (0x3ffUL)
6525 /* ======================================================= FILT_OUT9 ======================================================= */
6526 #define ADC2_FILT_OUT9_OUT_CH9_Pos (0UL)
6527 #define ADC2_FILT_OUT9_OUT_CH9_Msk (0x3ffUL)
6528 /* ===================================================== FILT_UP_CTRL ====================================================== */
6529 #define ADC2_FILT_UP_CTRL_Ch5_EN_Pos (5UL)
6530 #define ADC2_FILT_UP_CTRL_Ch5_EN_Msk (0x20UL)
6531 #define ADC2_FILT_UP_CTRL_Ch4_EN_Pos (4UL)
6532 #define ADC2_FILT_UP_CTRL_Ch4_EN_Msk (0x10UL)
6533 #define ADC2_FILT_UP_CTRL_Ch3_EN_Pos (3UL)
6534 #define ADC2_FILT_UP_CTRL_Ch3_EN_Msk (0x8UL)
6535 #define ADC2_FILT_UP_CTRL_Ch2_EN_Pos (2UL)
6536 #define ADC2_FILT_UP_CTRL_Ch2_EN_Msk (0x4UL)
6537 #define ADC2_FILT_UP_CTRL_Ch1_EN_Pos (1UL)
6538 #define ADC2_FILT_UP_CTRL_Ch1_EN_Msk (0x2UL)
6539 #define ADC2_FILT_UP_CTRL_Ch0_EN_Pos (0UL)
6540 #define ADC2_FILT_UP_CTRL_Ch0_EN_Msk (0x1UL)
6541 /* ===================================================== FILTCOEFF0_5 ====================================================== */
6542 #define ADC2_FILTCOEFF0_5_CH5_Pos (10UL)
6543 #define ADC2_FILTCOEFF0_5_CH5_Msk (0xc00UL)
6544 #define ADC2_FILTCOEFF0_5_CH4_Pos (8UL)
6545 #define ADC2_FILTCOEFF0_5_CH4_Msk (0x300UL)
6546 #define ADC2_FILTCOEFF0_5_CH3_Pos (6UL)
6547 #define ADC2_FILTCOEFF0_5_CH3_Msk (0xc0UL)
6548 #define ADC2_FILTCOEFF0_5_CH2_Pos (4UL)
6549 #define ADC2_FILTCOEFF0_5_CH2_Msk (0x30UL)
6550 #define ADC2_FILTCOEFF0_5_CH1_Pos (2UL)
6551 #define ADC2_FILTCOEFF0_5_CH1_Msk (0xcUL)
6552 #define ADC2_FILTCOEFF0_5_CH0_Pos (0UL)
6553 #define ADC2_FILTCOEFF0_5_CH0_Msk (0x3UL)
6554 /* ===================================================== FILTCOEFF6_9 ====================================================== */
6555 #define ADC2_FILTCOEFF6_9_CH9_Pos (6UL)
6556 #define ADC2_FILTCOEFF6_9_CH9_Msk (0xc0UL)
6557 #define ADC2_FILTCOEFF6_9_CH8_Pos (4UL)
6558 #define ADC2_FILTCOEFF6_9_CH8_Msk (0x30UL)
6559 #define ADC2_FILTCOEFF6_9_CH7_Pos (2UL)
6560 #define ADC2_FILTCOEFF6_9_CH7_Msk (0xcUL)
6561 #define ADC2_FILTCOEFF6_9_CH6_Pos (0UL)
6562 #define ADC2_FILTCOEFF6_9_CH6_Msk (0x3UL)
6563 /* ======================================================== HV_STS ========================================================= */
6564 #define ADC2_HV_STS_READY_Pos (1UL)
6565 #define ADC2_HV_STS_READY_Msk (0x2UL)
6566 /* ======================================================= MMODE0_5 ======================================================== */
6567 #define ADC2_MMODE0_5_Ch5_Pos (10UL)
6568 #define ADC2_MMODE0_5_Ch5_Msk (0xc00UL)
6569 #define ADC2_MMODE0_5_Ch4_Pos (8UL)
6570 #define ADC2_MMODE0_5_Ch4_Msk (0x300UL)
6571 #define ADC2_MMODE0_5_Ch3_Pos (6UL)
6572 #define ADC2_MMODE0_5_Ch3_Msk (0xc0UL)
6573 #define ADC2_MMODE0_5_Ch2_Pos (4UL)
6574 #define ADC2_MMODE0_5_Ch2_Msk (0x30UL)
6575 #define ADC2_MMODE0_5_Ch1_Pos (2UL)
6576 #define ADC2_MMODE0_5_Ch1_Msk (0xcUL)
6577 #define ADC2_MMODE0_5_Ch0_Pos (0UL)
6578 #define ADC2_MMODE0_5_Ch0_Msk (0x3UL)
6579 /* ========================================================= SQ1_4 ========================================================= */
6580 #define ADC2_SQ1_4_SQ4_Pos (24UL)
6581 #define ADC2_SQ1_4_SQ4_Msk (0x3f000000UL)
6582 #define ADC2_SQ1_4_SQ3_Pos (16UL)
6583 #define ADC2_SQ1_4_SQ3_Msk (0x3f0000UL)
6584 #define ADC2_SQ1_4_SQ2_Pos (8UL)
6585 #define ADC2_SQ1_4_SQ2_Msk (0x3f00UL)
6586 #define ADC2_SQ1_4_SQ1_Pos (0UL)
6587 #define ADC2_SQ1_4_SQ1_Msk (0x3fUL)
6588 /* ======================================================= SQ1_8_int ======================================================= */
6589 #define ADC2_SQ1_8_int_SQ8_int_Pos (28UL)
6590 #define ADC2_SQ1_8_int_SQ8_int_Msk (0xf0000000UL)
6591 #define ADC2_SQ1_8_int_SQ7_int_Pos (24UL)
6592 #define ADC2_SQ1_8_int_SQ7_int_Msk (0xf000000UL)
6593 #define ADC2_SQ1_8_int_SQ6_int_Pos (20UL)
6594 #define ADC2_SQ1_8_int_SQ6_int_Msk (0xf00000UL)
6595 #define ADC2_SQ1_8_int_SQ5_int_Pos (16UL)
6596 #define ADC2_SQ1_8_int_SQ5_int_Msk (0xf0000UL)
6597 #define ADC2_SQ1_8_int_SQ4_int_Pos (12UL)
6598 #define ADC2_SQ1_8_int_SQ4_int_Msk (0xf000UL)
6599 #define ADC2_SQ1_8_int_SQ3_int_Pos (8UL)
6600 #define ADC2_SQ1_8_int_SQ3_int_Msk (0xf00UL)
6601 #define ADC2_SQ1_8_int_SQ2_int_Pos (4UL)
6602 #define ADC2_SQ1_8_int_SQ2_int_Msk (0xf0UL)
6603 #define ADC2_SQ1_8_int_SQ1_int_Pos (0UL)
6604 #define ADC2_SQ1_8_int_SQ1_int_Msk (0xfUL)
6605 /* ========================================================= SQ5_8 ========================================================= */
6606 #define ADC2_SQ5_8_SQ8_Pos (24UL)
6607 #define ADC2_SQ5_8_SQ8_Msk (0x3f000000UL)
6608 #define ADC2_SQ5_8_SQ7_Pos (16UL)
6609 #define ADC2_SQ5_8_SQ7_Msk (0x3f0000UL)
6610 #define ADC2_SQ5_8_SQ6_Pos (8UL)
6611 #define ADC2_SQ5_8_SQ6_Msk (0x3f00UL)
6612 #define ADC2_SQ5_8_SQ5_Pos (0UL)
6613 #define ADC2_SQ5_8_SQ5_Msk (0x3fUL)
6614 /* ======================================================== SQ9_10 ========================================================= */
6615 #define ADC2_SQ9_10_SQ10_Pos (8UL)
6616 #define ADC2_SQ9_10_SQ10_Msk (0x3f00UL)
6617 #define ADC2_SQ9_10_SQ9_Pos (0UL)
6618 #define ADC2_SQ9_10_SQ9_Msk (0x3fUL)
6619 /* ====================================================== SQ9_10_int ======================================================= */
6620 #define ADC2_SQ9_10_int_SQ10_int_Pos (4UL)
6621 #define ADC2_SQ9_10_int_SQ10_int_Msk (0xf0UL)
6622 #define ADC2_SQ9_10_int_SQ9_int_Pos (0UL)
6623 #define ADC2_SQ9_10_int_SQ9_int_Msk (0xfUL)
6624 /* ========================================================= SQ_FB ========================================================= */
6625 #define ADC2_SQ_FB_CHx_Pos (16UL)
6626 #define ADC2_SQ_FB_CHx_Msk (0x1f0000UL)
6627 #define ADC2_SQ_FB_SQx_Pos (11UL)
6628 #define ADC2_SQ_FB_SQx_Msk (0x7800UL)
6629 #define ADC2_SQ_FB_ESM_ACTIVE_Pos (10UL)
6630 #define ADC2_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
6631 #define ADC2_SQ_FB_EIM_ACTIVE_Pos (9UL)
6632 #define ADC2_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
6633 #define ADC2_SQ_FB_SQ_STOP_Pos (8UL)
6634 #define ADC2_SQ_FB_SQ_STOP_Msk (0x100UL)
6635 #define ADC2_SQ_FB_SQ_FB_Pos (0UL)
6636 #define ADC2_SQ_FB_SQ_FB_Msk (0xfUL)
6637 /* ====================================================== TH0_3_LOWER ====================================================== */
6638 #define ADC2_TH0_3_LOWER_CH3_Pos (24UL)
6639 #define ADC2_TH0_3_LOWER_CH3_Msk (0xff000000UL)
6640 #define ADC2_TH0_3_LOWER_CH2_Pos (16UL)
6641 #define ADC2_TH0_3_LOWER_CH2_Msk (0xff0000UL)
6642 #define ADC2_TH0_3_LOWER_CH1_Pos (8UL)
6643 #define ADC2_TH0_3_LOWER_CH1_Msk (0xff00UL)
6644 #define ADC2_TH0_3_LOWER_CH0_Pos (0UL)
6645 #define ADC2_TH0_3_LOWER_CH0_Msk (0xffUL)
6646 /* ====================================================== TH0_3_UPPER ====================================================== */
6647 #define ADC2_TH0_3_UPPER_CH3_Pos (24UL)
6648 #define ADC2_TH0_3_UPPER_CH3_Msk (0xff000000UL)
6649 #define ADC2_TH0_3_UPPER_CH2_Pos (16UL)
6650 #define ADC2_TH0_3_UPPER_CH2_Msk (0xff0000UL)
6651 #define ADC2_TH0_3_UPPER_CH1_Pos (8UL)
6652 #define ADC2_TH0_3_UPPER_CH1_Msk (0xff00UL)
6653 #define ADC2_TH0_3_UPPER_CH0_Pos (0UL)
6654 #define ADC2_TH0_3_UPPER_CH0_Msk (0xffUL)
6655 /* ====================================================== TH4_5_LOWER ====================================================== */
6656 #define ADC2_TH4_5_LOWER_CH5_Pos (8UL)
6657 #define ADC2_TH4_5_LOWER_CH5_Msk (0xff00UL)
6658 #define ADC2_TH4_5_LOWER_CH4_Pos (0UL)
6659 #define ADC2_TH4_5_LOWER_CH4_Msk (0xffUL)
6660 /* ====================================================== TH4_5_UPPER ====================================================== */
6661 #define ADC2_TH4_5_UPPER_CH5_Pos (8UL)
6662 #define ADC2_TH4_5_UPPER_CH5_Msk (0xff00UL)
6663 #define ADC2_TH4_5_UPPER_CH4_Pos (0UL)
6664 #define ADC2_TH4_5_UPPER_CH4_Msk (0xffUL)
6665 /* ====================================================== TH6_9_LOWER ====================================================== */
6666 #define ADC2_TH6_9_LOWER_CH9_Pos (24UL)
6667 #define ADC2_TH6_9_LOWER_CH9_Msk (0xff000000UL)
6668 #define ADC2_TH6_9_LOWER_CH8_Pos (16UL)
6669 #define ADC2_TH6_9_LOWER_CH8_Msk (0xff0000UL)
6670 #define ADC2_TH6_9_LOWER_CH7_Pos (8UL)
6671 #define ADC2_TH6_9_LOWER_CH7_Msk (0xff00UL)
6672 #define ADC2_TH6_9_LOWER_CH6_Pos (0UL)
6673 #define ADC2_TH6_9_LOWER_CH6_Msk (0xffUL)
6674 /* ====================================================== TH6_9_UPPER ====================================================== */
6675 #define ADC2_TH6_9_UPPER_CH9_Pos (24UL)
6676 #define ADC2_TH6_9_UPPER_CH9_Msk (0xff000000UL)
6677 #define ADC2_TH6_9_UPPER_CH8_Pos (16UL)
6678 #define ADC2_TH6_9_UPPER_CH8_Msk (0xff0000UL)
6679 #define ADC2_TH6_9_UPPER_CH7_Pos (8UL)
6680 #define ADC2_TH6_9_UPPER_CH7_Msk (0xff00UL)
6681 #define ADC2_TH6_9_UPPER_CH6_Pos (0UL)
6682 #define ADC2_TH6_9_UPPER_CH6_Msk (0xffUL)
6685 /* =========================================================================================================================== */
6686 /* ================ ADC34 ================ */
6687 /* =========================================================================================================================== */
6688 
6689 /* ======================================================= CTRL_STS ======================================================== */
6690 #define ADC34_CTRL_STS_ADC4_OSR_Pos (28UL)
6691 #define ADC34_CTRL_STS_ADC4_OSR_Msk (0xf0000000UL)
6692 #define ADC34_CTRL_STS_ADC34_DITHVAL_Pos (24UL)
6693 #define ADC34_CTRL_STS_ADC34_DITHVAL_Msk (0xf000000UL)
6694 #define ADC34_CTRL_STS_ADC34_DITHEN_Pos (23UL)
6695 #define ADC34_CTRL_STS_ADC34_DITHEN_Msk (0x800000UL)
6696 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Pos (21UL)
6697 #define ADC34_CTRL_STS_ADC34_EoC_CNT_Msk (0x600000UL)
6698 #define ADC34_CTRL_STS_ADC4_EoC_STS_Pos (20UL)
6699 #define ADC34_CTRL_STS_ADC4_EoC_STS_Msk (0x100000UL)
6700 #define ADC34_CTRL_STS_ADC4_SOC_Pos (18UL)
6701 #define ADC34_CTRL_STS_ADC4_SOC_Msk (0x40000UL)
6702 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Pos (17UL)
6703 #define ADC34_CTRL_STS_ADC4_OFS_MEAS_EN_Msk (0x20000UL)
6704 #define ADC34_CTRL_STS_ADC4_EN_Pos (16UL)
6705 #define ADC34_CTRL_STS_ADC4_EN_Msk (0x10000UL)
6706 #define ADC34_CTRL_STS_ADC3_OSR_Pos (12UL)
6707 #define ADC34_CTRL_STS_ADC3_OSR_Msk (0xf000UL)
6708 #define ADC34_CTRL_STS_ADC34_REF_SEL_Pos (11UL)
6709 #define ADC34_CTRL_STS_ADC34_REF_SEL_Msk (0x800UL)
6710 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Pos (5UL)
6711 #define ADC34_CTRL_STS_ADC34_DREQ_SEL_Msk (0x60UL)
6712 #define ADC34_CTRL_STS_ADC3_EoC_STS_Pos (4UL)
6713 #define ADC34_CTRL_STS_ADC3_EoC_STS_Msk (0x10UL)
6714 #define ADC34_CTRL_STS_ADC3_SOC_Pos (2UL)
6715 #define ADC34_CTRL_STS_ADC3_SOC_Msk (0x4UL)
6716 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Pos (1UL)
6717 #define ADC34_CTRL_STS_ADC3_OFS_MEAS_EN_Msk (0x2UL)
6718 #define ADC34_CTRL_STS_ADC3_EN_Pos (0UL)
6719 #define ADC34_CTRL_STS_ADC3_EN_Msk (0x1UL)
6720 /* ========================================================= RESU ========================================================== */
6721 #define ADC34_RESU_ADC4_RESU_Pos (16UL)
6722 #define ADC34_RESU_ADC4_RESU_Msk (0xffff0000UL)
6723 #define ADC34_RESU_ADC3_RESU_Pos (0UL)
6724 #define ADC34_RESU_ADC3_RESU_Msk (0xffffUL)
6727 /* =========================================================================================================================== */
6728 /* ================ BDRV ================ */
6729 /* =========================================================================================================================== */
6730 
6731 /* ====================================================== CP_CLK_CTRL ====================================================== */
6732 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Pos (15UL)
6733 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Msk (0x8000UL)
6734 #define BDRV_CP_CLK_CTRL_F_CP_Pos (13UL)
6735 #define BDRV_CP_CLK_CTRL_F_CP_Msk (0x6000UL)
6736 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Pos (8UL)
6737 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Msk (0x1f00UL)
6738 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Pos (0UL)
6739 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Msk (0x1fUL)
6740 /* ====================================================== CP_CTRL_STS ====================================================== */
6741 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Pos (26UL)
6742 #define BDRV_CP_CTRL_STS_VTHVCP9V_TRIM_Msk (0xc000000UL)
6743 #define BDRV_CP_CTRL_STS_VCP9V_SET_Pos (25UL)
6744 #define BDRV_CP_CTRL_STS_VCP9V_SET_Msk (0x2000000UL)
6745 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Pos (24UL)
6746 #define BDRV_CP_CTRL_STS_CPLOPWRM_EN_Msk (0x1000000UL)
6747 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Pos (23UL)
6748 #define BDRV_CP_CTRL_STS_VSD_UPTH_STS_Msk (0x800000UL)
6749 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Pos (22UL)
6750 #define BDRV_CP_CTRL_STS_DRVx_VSDUP_DIS_Msk (0x400000UL)
6751 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Pos (21UL)
6752 #define BDRV_CP_CTRL_STS_VSD_LOTH_STS_Msk (0x200000UL)
6753 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Pos (20UL)
6754 #define BDRV_CP_CTRL_STS_DRVx_VSDLO_DIS_Msk (0x100000UL)
6755 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Pos (19UL)
6756 #define BDRV_CP_CTRL_STS_VCP_UPTH_STS_Msk (0x80000UL)
6757 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Pos (18UL)
6758 #define BDRV_CP_CTRL_STS_DRVx_VCPUP_DIS_Msk (0x40000UL)
6759 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Pos (17UL)
6760 #define BDRV_CP_CTRL_STS_VCP_LOTH1_STS_Msk (0x20000UL)
6761 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Pos (16UL)
6762 #define BDRV_CP_CTRL_STS_DRVx_VCPLO_DIS_Msk (0x10000UL)
6763 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Pos (8UL)
6764 #define BDRV_CP_CTRL_STS_VCP_LOWTH2_Msk (0x700UL)
6765 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Pos (5UL)
6766 #define BDRV_CP_CTRL_STS_VCP_LOTH2_STS_Msk (0x20UL)
6767 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Pos (2UL)
6768 #define BDRV_CP_CTRL_STS_CP_RDY_EN_Msk (0x4UL)
6769 #define BDRV_CP_CTRL_STS_CP_EN_Pos (0UL)
6770 #define BDRV_CP_CTRL_STS_CP_EN_Msk (0x1UL)
6771 /* ========================================================= CTRL1 ========================================================= */
6772 #define BDRV_CTRL1_HS2_OC_DIS_Pos (31UL)
6773 #define BDRV_CTRL1_HS2_OC_DIS_Msk (0x80000000UL)
6774 #define BDRV_CTRL1_HS2_OC_STS_Pos (30UL)
6775 #define BDRV_CTRL1_HS2_OC_STS_Msk (0x40000000UL)
6776 #define BDRV_CTRL1_HS2_SUPERR_STS_Pos (29UL)
6777 #define BDRV_CTRL1_HS2_SUPERR_STS_Msk (0x20000000UL)
6778 #define BDRV_CTRL1_HS2_DS_STS_Pos (28UL)
6779 #define BDRV_CTRL1_HS2_DS_STS_Msk (0x10000000UL)
6780 #define BDRV_CTRL1_HS2_DCS_EN_Pos (27UL)
6781 #define BDRV_CTRL1_HS2_DCS_EN_Msk (0x8000000UL)
6782 #define BDRV_CTRL1_HS2_ON_Pos (26UL)
6783 #define BDRV_CTRL1_HS2_ON_Msk (0x4000000UL)
6784 #define BDRV_CTRL1_HS2_PWM_Pos (25UL)
6785 #define BDRV_CTRL1_HS2_PWM_Msk (0x2000000UL)
6786 #define BDRV_CTRL1_HS2_EN_Pos (24UL)
6787 #define BDRV_CTRL1_HS2_EN_Msk (0x1000000UL)
6788 #define BDRV_CTRL1_HS1_OC_DIS_Pos (23UL)
6789 #define BDRV_CTRL1_HS1_OC_DIS_Msk (0x800000UL)
6790 #define BDRV_CTRL1_HS1_OC_STS_Pos (22UL)
6791 #define BDRV_CTRL1_HS1_OC_STS_Msk (0x400000UL)
6792 #define BDRV_CTRL1_HS1_SUPERR_STS_Pos (21UL)
6793 #define BDRV_CTRL1_HS1_SUPERR_STS_Msk (0x200000UL)
6794 #define BDRV_CTRL1_HS1_DS_STS_Pos (20UL)
6795 #define BDRV_CTRL1_HS1_DS_STS_Msk (0x100000UL)
6796 #define BDRV_CTRL1_HS1_DCS_EN_Pos (19UL)
6797 #define BDRV_CTRL1_HS1_DCS_EN_Msk (0x80000UL)
6798 #define BDRV_CTRL1_HS1_ON_Pos (18UL)
6799 #define BDRV_CTRL1_HS1_ON_Msk (0x40000UL)
6800 #define BDRV_CTRL1_HS1_PWM_Pos (17UL)
6801 #define BDRV_CTRL1_HS1_PWM_Msk (0x20000UL)
6802 #define BDRV_CTRL1_HS1_EN_Pos (16UL)
6803 #define BDRV_CTRL1_HS1_EN_Msk (0x10000UL)
6804 #define BDRV_CTRL1_LS2_OC_DIS_Pos (15UL)
6805 #define BDRV_CTRL1_LS2_OC_DIS_Msk (0x8000UL)
6806 #define BDRV_CTRL1_LS2_OC_STS_Pos (14UL)
6807 #define BDRV_CTRL1_LS2_OC_STS_Msk (0x4000UL)
6808 #define BDRV_CTRL1_LS2_SUPERR_STS_Pos (13UL)
6809 #define BDRV_CTRL1_LS2_SUPERR_STS_Msk (0x2000UL)
6810 #define BDRV_CTRL1_LS2_DS_STS_Pos (12UL)
6811 #define BDRV_CTRL1_LS2_DS_STS_Msk (0x1000UL)
6812 #define BDRV_CTRL1_LS2_DCS_EN_Pos (11UL)
6813 #define BDRV_CTRL1_LS2_DCS_EN_Msk (0x800UL)
6814 #define BDRV_CTRL1_LS2_ON_Pos (10UL)
6815 #define BDRV_CTRL1_LS2_ON_Msk (0x400UL)
6816 #define BDRV_CTRL1_LS2_PWM_Pos (9UL)
6817 #define BDRV_CTRL1_LS2_PWM_Msk (0x200UL)
6818 #define BDRV_CTRL1_LS2_EN_Pos (8UL)
6819 #define BDRV_CTRL1_LS2_EN_Msk (0x100UL)
6820 #define BDRV_CTRL1_LS1_OC_DIS_Pos (7UL)
6821 #define BDRV_CTRL1_LS1_OC_DIS_Msk (0x80UL)
6822 #define BDRV_CTRL1_LS1_OC_STS_Pos (6UL)
6823 #define BDRV_CTRL1_LS1_OC_STS_Msk (0x40UL)
6824 #define BDRV_CTRL1_LS1_SUPERR_STS_Pos (5UL)
6825 #define BDRV_CTRL1_LS1_SUPERR_STS_Msk (0x20UL)
6826 #define BDRV_CTRL1_LS1_DS_STS_Pos (4UL)
6827 #define BDRV_CTRL1_LS1_DS_STS_Msk (0x10UL)
6828 #define BDRV_CTRL1_LS1_DCS_EN_Pos (3UL)
6829 #define BDRV_CTRL1_LS1_DCS_EN_Msk (0x8UL)
6830 #define BDRV_CTRL1_LS1_ON_Pos (2UL)
6831 #define BDRV_CTRL1_LS1_ON_Msk (0x4UL)
6832 #define BDRV_CTRL1_LS1_PWM_Pos (1UL)
6833 #define BDRV_CTRL1_LS1_PWM_Msk (0x2UL)
6834 #define BDRV_CTRL1_LS1_EN_Pos (0UL)
6835 #define BDRV_CTRL1_LS1_EN_Msk (0x1UL)
6836 /* ========================================================= CTRL2 ========================================================= */
6837 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Pos (31UL)
6838 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Msk (0x80000000UL)
6839 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Pos (28UL)
6840 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Msk (0x70000000UL)
6841 #define BDRV_CTRL2_DLY_DIAG_STS_Pos (27UL)
6842 #define BDRV_CTRL2_DLY_DIAG_STS_Msk (0x8000000UL)
6843 #define BDRV_CTRL2_DLY_DIAG_SCLR_Pos (26UL)
6844 #define BDRV_CTRL2_DLY_DIAG_SCLR_Msk (0x4000000UL)
6845 #define BDRV_CTRL2_DLY_DIAG_TIM_Pos (16UL)
6846 #define BDRV_CTRL2_DLY_DIAG_TIM_Msk (0x3ff0000UL)
6847 /* ========================================================= CTRL3 ========================================================= */
6848 #define BDRV_CTRL3_DRV_CCP_DIS_Pos (26UL)
6849 #define BDRV_CTRL3_DRV_CCP_DIS_Msk (0x4000000UL)
6850 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Pos (24UL)
6851 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Msk (0x3000000UL)
6852 #define BDRV_CTRL3_DSMONVTH_Pos (16UL)
6853 #define BDRV_CTRL3_DSMONVTH_Msk (0x70000UL)
6854 #define BDRV_CTRL3_OFF_SEQ_EN_Pos (15UL)
6855 #define BDRV_CTRL3_OFF_SEQ_EN_Msk (0x8000UL)
6856 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Pos (14UL)
6857 #define BDRV_CTRL3_IDISCHARGEDIV2_N_Msk (0x4000UL)
6858 #define BDRV_CTRL3_IDISCHARGE_TRIM_Pos (8UL)
6859 #define BDRV_CTRL3_IDISCHARGE_TRIM_Msk (0x1f00UL)
6860 #define BDRV_CTRL3_ON_SEQ_EN_Pos (7UL)
6861 #define BDRV_CTRL3_ON_SEQ_EN_Msk (0x80UL)
6862 #define BDRV_CTRL3_ICHARGEDIV2_N_Pos (6UL)
6863 #define BDRV_CTRL3_ICHARGEDIV2_N_Msk (0x40UL)
6864 #define BDRV_CTRL3_ICHARGE_TRIM_Pos (0UL)
6865 #define BDRV_CTRL3_ICHARGE_TRIM_Msk (0x1fUL)
6866 /* ===================================================== OFF_SEQ_CTRL ====================================================== */
6867 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Pos (27UL)
6868 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_1_Msk (0xf8000000UL)
6869 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Pos (24UL)
6870 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_1_Msk (0x7000000UL)
6871 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Pos (19UL)
6872 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_2_Msk (0xf80000UL)
6873 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Pos (16UL)
6874 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_2_Msk (0x70000UL)
6875 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Pos (11UL)
6876 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_3_Msk (0xf800UL)
6877 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Pos (8UL)
6878 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_3_Msk (0x700UL)
6879 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Pos (3UL)
6880 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_I_4_Msk (0xf8UL)
6881 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Pos (0UL)
6882 #define BDRV_OFF_SEQ_CTRL_DRV_OFF_t_4_Msk (0x7UL)
6883 /* ====================================================== ON_SEQ_CTRL ====================================================== */
6884 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Pos (27UL)
6885 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_1_Msk (0xf8000000UL)
6886 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Pos (24UL)
6887 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_1_Msk (0x7000000UL)
6888 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Pos (19UL)
6889 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_2_Msk (0xf80000UL)
6890 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Pos (16UL)
6891 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_2_Msk (0x70000UL)
6892 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Pos (11UL)
6893 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_3_Msk (0xf800UL)
6894 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Pos (8UL)
6895 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_3_Msk (0x700UL)
6896 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Pos (3UL)
6897 #define BDRV_ON_SEQ_CTRL_DRV_ON_I_4_Msk (0xf8UL)
6898 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Pos (0UL)
6899 #define BDRV_ON_SEQ_CTRL_DRV_ON_t_4_Msk (0x7UL)
6900 /* ======================================================= TRIM_DRVx ======================================================= */
6901 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Pos (24UL)
6902 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Msk (0x3000000UL)
6903 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Pos (22UL)
6904 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Msk (0x400000UL)
6905 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Pos (21UL)
6906 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Msk (0x200000UL)
6907 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Pos (19UL)
6908 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Msk (0x80000UL)
6909 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Pos (18UL)
6910 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Msk (0x40000UL)
6911 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Pos (16UL)
6912 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Msk (0x30000UL)
6913 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Pos (14UL)
6914 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Msk (0x4000UL)
6915 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Pos (13UL)
6916 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Msk (0x2000UL)
6917 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Pos (11UL)
6918 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Msk (0x800UL)
6919 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Pos (10UL)
6920 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Msk (0x400UL)
6921 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Pos (8UL)
6922 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Msk (0x300UL)
6923 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Pos (5UL)
6924 #define BDRV_TRIM_DRVx_DRV_CCPTIMMUL_Msk (0x60UL)
6925 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Pos (0UL)
6926 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Msk (0x3UL)
6929 /* =========================================================================================================================== */
6930 /* ================ CCU6 ================ */
6931 /* =========================================================================================================================== */
6932 
6933 /* ========================================================= CC60R ========================================================= */
6934 #define CCU6_CC60R_CCV_Pos (0UL)
6935 #define CCU6_CC60R_CCV_Msk (0xffffUL)
6936 /* ======================================================== CC60SR ========================================================= */
6937 #define CCU6_CC60SR_CCS_Pos (0UL)
6938 #define CCU6_CC60SR_CCS_Msk (0xffffUL)
6939 /* ========================================================= CC61R ========================================================= */
6940 #define CCU6_CC61R_CCV_Pos (0UL)
6941 #define CCU6_CC61R_CCV_Msk (0xffffUL)
6942 /* ======================================================== CC61SR ========================================================= */
6943 #define CCU6_CC61SR_CCS_Pos (0UL)
6944 #define CCU6_CC61SR_CCS_Msk (0xffffUL)
6945 /* ========================================================= CC62R ========================================================= */
6946 #define CCU6_CC62R_CCV_Pos (0UL)
6947 #define CCU6_CC62R_CCV_Msk (0xffffUL)
6948 /* ======================================================== CC62SR ========================================================= */
6949 #define CCU6_CC62SR_CCS_Pos (0UL)
6950 #define CCU6_CC62SR_CCS_Msk (0xffffUL)
6951 /* ========================================================= CC63R ========================================================= */
6952 #define CCU6_CC63R_CCV_Pos (0UL)
6953 #define CCU6_CC63R_CCV_Msk (0xffffUL)
6954 /* ======================================================== CC63SR ========================================================= */
6955 #define CCU6_CC63SR_CCS_Pos (0UL)
6956 #define CCU6_CC63SR_CCS_Msk (0xffffUL)
6957 /* ======================================================= CMPMODIF ======================================================== */
6958 #define CCU6_CMPMODIF_MCC60S_Pos (0UL)
6959 #define CCU6_CMPMODIF_MCC60S_Msk (0x1UL)
6960 #define CCU6_CMPMODIF_MCC61S_Pos (1UL)
6961 #define CCU6_CMPMODIF_MCC61S_Msk (0x2UL)
6962 #define CCU6_CMPMODIF_MCC62S_Pos (2UL)
6963 #define CCU6_CMPMODIF_MCC62S_Msk (0x4UL)
6964 #define CCU6_CMPMODIF_MCC63S_Pos (6UL)
6965 #define CCU6_CMPMODIF_MCC63S_Msk (0x40UL)
6966 #define CCU6_CMPMODIF_MCC60R_Pos (8UL)
6967 #define CCU6_CMPMODIF_MCC60R_Msk (0x100UL)
6968 #define CCU6_CMPMODIF_MCC61R_Pos (9UL)
6969 #define CCU6_CMPMODIF_MCC61R_Msk (0x200UL)
6970 #define CCU6_CMPMODIF_MCC62R_Pos (10UL)
6971 #define CCU6_CMPMODIF_MCC62R_Msk (0x400UL)
6972 #define CCU6_CMPMODIF_MCC63R_Pos (14UL)
6973 #define CCU6_CMPMODIF_MCC63R_Msk (0x4000UL)
6974 /* ======================================================== CMPSTAT ======================================================== */
6975 #define CCU6_CMPSTAT_CC60ST_Pos (0UL)
6976 #define CCU6_CMPSTAT_CC60ST_Msk (0x1UL)
6977 #define CCU6_CMPSTAT_CC61ST_Pos (1UL)
6978 #define CCU6_CMPSTAT_CC61ST_Msk (0x2UL)
6979 #define CCU6_CMPSTAT_CC62ST_Pos (2UL)
6980 #define CCU6_CMPSTAT_CC62ST_Msk (0x4UL)
6981 #define CCU6_CMPSTAT_CC63ST_Pos (6UL)
6982 #define CCU6_CMPSTAT_CC63ST_Msk (0x40UL)
6983 #define CCU6_CMPSTAT_CCPOS0_Pos (3UL)
6984 #define CCU6_CMPSTAT_CCPOS0_Msk (0x8UL)
6985 #define CCU6_CMPSTAT_CCPOS1_Pos (4UL)
6986 #define CCU6_CMPSTAT_CCPOS1_Msk (0x10UL)
6987 #define CCU6_CMPSTAT_CCPOS2_Pos (5UL)
6988 #define CCU6_CMPSTAT_CCPOS2_Msk (0x20UL)
6989 #define CCU6_CMPSTAT_CC60PS_Pos (8UL)
6990 #define CCU6_CMPSTAT_CC60PS_Msk (0x100UL)
6991 #define CCU6_CMPSTAT_CC61PS_Pos (10UL)
6992 #define CCU6_CMPSTAT_CC61PS_Msk (0x400UL)
6993 #define CCU6_CMPSTAT_CC62PS_Pos (12UL)
6994 #define CCU6_CMPSTAT_CC62PS_Msk (0x1000UL)
6995 #define CCU6_CMPSTAT_COUT60PS_Pos (9UL)
6996 #define CCU6_CMPSTAT_COUT60PS_Msk (0x200UL)
6997 #define CCU6_CMPSTAT_COUT61PS_Pos (11UL)
6998 #define CCU6_CMPSTAT_COUT61PS_Msk (0x800UL)
6999 #define CCU6_CMPSTAT_COUT62PS_Pos (13UL)
7000 #define CCU6_CMPSTAT_COUT62PS_Msk (0x2000UL)
7001 #define CCU6_CMPSTAT_COUT63PS_Pos (14UL)
7002 #define CCU6_CMPSTAT_COUT63PS_Msk (0x4000UL)
7003 #define CCU6_CMPSTAT_T13IM_Pos (15UL)
7004 #define CCU6_CMPSTAT_T13IM_Msk (0x8000UL)
7005 /* ========================================================== IEN ========================================================== */
7006 #define CCU6_IEN_ENCC60R_Pos (0UL)
7007 #define CCU6_IEN_ENCC60R_Msk (0x1UL)
7008 #define CCU6_IEN_ENCC60F_Pos (1UL)
7009 #define CCU6_IEN_ENCC60F_Msk (0x2UL)
7010 #define CCU6_IEN_ENCC61R_Pos (2UL)
7011 #define CCU6_IEN_ENCC61R_Msk (0x4UL)
7012 #define CCU6_IEN_ENCC61F_Pos (3UL)
7013 #define CCU6_IEN_ENCC61F_Msk (0x8UL)
7014 #define CCU6_IEN_ENCC62R_Pos (4UL)
7015 #define CCU6_IEN_ENCC62R_Msk (0x10UL)
7016 #define CCU6_IEN_ENCC62F_Pos (5UL)
7017 #define CCU6_IEN_ENCC62F_Msk (0x20UL)
7018 #define CCU6_IEN_ENT12OM_Pos (6UL)
7019 #define CCU6_IEN_ENT12OM_Msk (0x40UL)
7020 #define CCU6_IEN_ENT12PM_Pos (7UL)
7021 #define CCU6_IEN_ENT12PM_Msk (0x80UL)
7022 #define CCU6_IEN_ENT13CM_Pos (8UL)
7023 #define CCU6_IEN_ENT13CM_Msk (0x100UL)
7024 #define CCU6_IEN_ENT13PM_Pos (9UL)
7025 #define CCU6_IEN_ENT13PM_Msk (0x200UL)
7026 #define CCU6_IEN_ENTRPF_Pos (10UL)
7027 #define CCU6_IEN_ENTRPF_Msk (0x400UL)
7028 #define CCU6_IEN_ENCHE_Pos (12UL)
7029 #define CCU6_IEN_ENCHE_Msk (0x1000UL)
7030 #define CCU6_IEN_ENWHE_Pos (13UL)
7031 #define CCU6_IEN_ENWHE_Msk (0x2000UL)
7032 #define CCU6_IEN_ENIDLE_Pos (14UL)
7033 #define CCU6_IEN_ENIDLE_Msk (0x4000UL)
7034 #define CCU6_IEN_ENSTR_Pos (15UL)
7035 #define CCU6_IEN_ENSTR_Msk (0x8000UL)
7036 /* ========================================================== INP ========================================================== */
7037 #define CCU6_INP_INPCC60_Pos (0UL)
7038 #define CCU6_INP_INPCC60_Msk (0x3UL)
7039 #define CCU6_INP_INPCC61_Pos (2UL)
7040 #define CCU6_INP_INPCC61_Msk (0xcUL)
7041 #define CCU6_INP_INPCC62_Pos (4UL)
7042 #define CCU6_INP_INPCC62_Msk (0x30UL)
7043 #define CCU6_INP_INPCHE_Pos (6UL)
7044 #define CCU6_INP_INPCHE_Msk (0xc0UL)
7045 #define CCU6_INP_INPERR_Pos (8UL)
7046 #define CCU6_INP_INPERR_Msk (0x300UL)
7047 #define CCU6_INP_INPT12_Pos (10UL)
7048 #define CCU6_INP_INPT12_Msk (0xc00UL)
7049 #define CCU6_INP_INPT13_Pos (12UL)
7050 #define CCU6_INP_INPT13_Msk (0x3000UL)
7051 /* ========================================================== IS =========================================================== */
7052 #define CCU6_IS_ICC60R_Pos (0UL)
7053 #define CCU6_IS_ICC60R_Msk (0x1UL)
7054 #define CCU6_IS_ICC61R_Pos (2UL)
7055 #define CCU6_IS_ICC61R_Msk (0x4UL)
7056 #define CCU6_IS_ICC62R_Pos (4UL)
7057 #define CCU6_IS_ICC62R_Msk (0x10UL)
7058 #define CCU6_IS_ICC60F_Pos (1UL)
7059 #define CCU6_IS_ICC60F_Msk (0x2UL)
7060 #define CCU6_IS_ICC61F_Pos (3UL)
7061 #define CCU6_IS_ICC61F_Msk (0x8UL)
7062 #define CCU6_IS_ICC62F_Pos (5UL)
7063 #define CCU6_IS_ICC62F_Msk (0x20UL)
7064 #define CCU6_IS_T12OM_Pos (6UL)
7065 #define CCU6_IS_T12OM_Msk (0x40UL)
7066 #define CCU6_IS_T12PM_Pos (7UL)
7067 #define CCU6_IS_T12PM_Msk (0x80UL)
7068 #define CCU6_IS_T13CM_Pos (8UL)
7069 #define CCU6_IS_T13CM_Msk (0x100UL)
7070 #define CCU6_IS_T13PM_Pos (9UL)
7071 #define CCU6_IS_T13PM_Msk (0x200UL)
7072 #define CCU6_IS_TRPF_Pos (10UL)
7073 #define CCU6_IS_TRPF_Msk (0x400UL)
7074 #define CCU6_IS_TRPS_Pos (11UL)
7075 #define CCU6_IS_TRPS_Msk (0x800UL)
7076 #define CCU6_IS_CHE_Pos (12UL)
7077 #define CCU6_IS_CHE_Msk (0x1000UL)
7078 #define CCU6_IS_WHE_Pos (13UL)
7079 #define CCU6_IS_WHE_Msk (0x2000UL)
7080 #define CCU6_IS_IDLE_Pos (14UL)
7081 #define CCU6_IS_IDLE_Msk (0x4000UL)
7082 #define CCU6_IS_STR_Pos (15UL)
7083 #define CCU6_IS_STR_Msk (0x8000UL)
7084 /* ========================================================== ISR ========================================================== */
7085 #define CCU6_ISR_RCC60R_Pos (0UL)
7086 #define CCU6_ISR_RCC60R_Msk (0x1UL)
7087 #define CCU6_ISR_RCC60F_Pos (1UL)
7088 #define CCU6_ISR_RCC60F_Msk (0x2UL)
7089 #define CCU6_ISR_RCC61R_Pos (2UL)
7090 #define CCU6_ISR_RCC61R_Msk (0x4UL)
7091 #define CCU6_ISR_RCC61F_Pos (3UL)
7092 #define CCU6_ISR_RCC61F_Msk (0x8UL)
7093 #define CCU6_ISR_RCC62R_Pos (4UL)
7094 #define CCU6_ISR_RCC62R_Msk (0x10UL)
7095 #define CCU6_ISR_RCC62F_Pos (5UL)
7096 #define CCU6_ISR_RCC62F_Msk (0x20UL)
7097 #define CCU6_ISR_RT12OM_Pos (6UL)
7098 #define CCU6_ISR_RT12OM_Msk (0x40UL)
7099 #define CCU6_ISR_RT12PM_Pos (7UL)
7100 #define CCU6_ISR_RT12PM_Msk (0x80UL)
7101 #define CCU6_ISR_RT13CM_Pos (8UL)
7102 #define CCU6_ISR_RT13CM_Msk (0x100UL)
7103 #define CCU6_ISR_RT13PM_Pos (9UL)
7104 #define CCU6_ISR_RT13PM_Msk (0x200UL)
7105 #define CCU6_ISR_RTRPF_Pos (10UL)
7106 #define CCU6_ISR_RTRPF_Msk (0x400UL)
7107 #define CCU6_ISR_RCHE_Pos (12UL)
7108 #define CCU6_ISR_RCHE_Msk (0x1000UL)
7109 #define CCU6_ISR_RWHE_Pos (13UL)
7110 #define CCU6_ISR_RWHE_Msk (0x2000UL)
7111 #define CCU6_ISR_RIDLE_Pos (14UL)
7112 #define CCU6_ISR_RIDLE_Msk (0x4000UL)
7113 #define CCU6_ISR_RSTR_Pos (15UL)
7114 #define CCU6_ISR_RSTR_Msk (0x8000UL)
7115 /* ========================================================== ISS ========================================================== */
7116 #define CCU6_ISS_SCC60R_Pos (0UL)
7117 #define CCU6_ISS_SCC60R_Msk (0x1UL)
7118 #define CCU6_ISS_SCC60F_Pos (1UL)
7119 #define CCU6_ISS_SCC60F_Msk (0x2UL)
7120 #define CCU6_ISS_SCC61R_Pos (2UL)
7121 #define CCU6_ISS_SCC61R_Msk (0x4UL)
7122 #define CCU6_ISS_SCC61F_Pos (3UL)
7123 #define CCU6_ISS_SCC61F_Msk (0x8UL)
7124 #define CCU6_ISS_SCC62R_Pos (4UL)
7125 #define CCU6_ISS_SCC62R_Msk (0x10UL)
7126 #define CCU6_ISS_SCC62F_Pos (5UL)
7127 #define CCU6_ISS_SCC62F_Msk (0x20UL)
7128 #define CCU6_ISS_ST12OM_Pos (6UL)
7129 #define CCU6_ISS_ST12OM_Msk (0x40UL)
7130 #define CCU6_ISS_ST12PM_Pos (7UL)
7131 #define CCU6_ISS_ST12PM_Msk (0x80UL)
7132 #define CCU6_ISS_ST13CM_Pos (8UL)
7133 #define CCU6_ISS_ST13CM_Msk (0x100UL)
7134 #define CCU6_ISS_ST13PM_Pos (9UL)
7135 #define CCU6_ISS_ST13PM_Msk (0x200UL)
7136 #define CCU6_ISS_STRPF_Pos (10UL)
7137 #define CCU6_ISS_STRPF_Msk (0x400UL)
7138 #define CCU6_ISS_SWHC_Pos (11UL)
7139 #define CCU6_ISS_SWHC_Msk (0x800UL)
7140 #define CCU6_ISS_SCHE_Pos (12UL)
7141 #define CCU6_ISS_SCHE_Msk (0x1000UL)
7142 #define CCU6_ISS_SWHE_Pos (13UL)
7143 #define CCU6_ISS_SWHE_Msk (0x2000UL)
7144 #define CCU6_ISS_SIDLE_Pos (14UL)
7145 #define CCU6_ISS_SIDLE_Msk (0x4000UL)
7146 #define CCU6_ISS_SSTR_Pos (15UL)
7147 #define CCU6_ISS_SSTR_Msk (0x8000UL)
7148 /* ======================================================== MCMCTR ========================================================= */
7149 #define CCU6_MCMCTR_SWSEL_Pos (0UL)
7150 #define CCU6_MCMCTR_SWSEL_Msk (0x7UL)
7151 #define CCU6_MCMCTR_SWSYN_Pos (4UL)
7152 #define CCU6_MCMCTR_SWSYN_Msk (0x30UL)
7153 #define CCU6_MCMCTR_STE12U_Pos (8UL)
7154 #define CCU6_MCMCTR_STE12U_Msk (0x100UL)
7155 #define CCU6_MCMCTR_STE12D_Pos (9UL)
7156 #define CCU6_MCMCTR_STE12D_Msk (0x200UL)
7157 #define CCU6_MCMCTR_STE13U_Pos (10UL)
7158 #define CCU6_MCMCTR_STE13U_Msk (0x400UL)
7159 /* ======================================================== MCMOUT ========================================================= */
7160 #define CCU6_MCMOUT_MCMP_Pos (0UL)
7161 #define CCU6_MCMOUT_MCMP_Msk (0x3fUL)
7162 #define CCU6_MCMOUT_R_Pos (6UL)
7163 #define CCU6_MCMOUT_R_Msk (0x40UL)
7164 #define CCU6_MCMOUT_EXPH_Pos (8UL)
7165 #define CCU6_MCMOUT_EXPH_Msk (0x700UL)
7166 #define CCU6_MCMOUT_CURH_Pos (11UL)
7167 #define CCU6_MCMOUT_CURH_Msk (0x3800UL)
7168 /* ======================================================== MCMOUTS ======================================================== */
7169 #define CCU6_MCMOUTS_MCMPS_Pos (0UL)
7170 #define CCU6_MCMOUTS_MCMPS_Msk (0x3fUL)
7171 #define CCU6_MCMOUTS_STRMCM_Pos (7UL)
7172 #define CCU6_MCMOUTS_STRMCM_Msk (0x80UL)
7173 #define CCU6_MCMOUTS_EXPHS_Pos (8UL)
7174 #define CCU6_MCMOUTS_EXPHS_Msk (0x700UL)
7175 #define CCU6_MCMOUTS_CURHS_Pos (11UL)
7176 #define CCU6_MCMOUTS_CURHS_Msk (0x3800UL)
7177 #define CCU6_MCMOUTS_STRHP_Pos (15UL)
7178 #define CCU6_MCMOUTS_STRHP_Msk (0x8000UL)
7179 /* ======================================================== MODCTR ========================================================= */
7180 #define CCU6_MODCTR_T12MODEN_Pos (0UL)
7181 #define CCU6_MODCTR_T12MODEN_Msk (0x3fUL)
7182 #define CCU6_MODCTR_MCMEN_Pos (7UL)
7183 #define CCU6_MODCTR_MCMEN_Msk (0x80UL)
7184 #define CCU6_MODCTR_T13MODEN_Pos (8UL)
7185 #define CCU6_MODCTR_T13MODEN_Msk (0x3f00UL)
7186 #define CCU6_MODCTR_ECT13O_Pos (15UL)
7187 #define CCU6_MODCTR_ECT13O_Msk (0x8000UL)
7188 /* ======================================================== PISEL0 ========================================================= */
7189 #define CCU6_PISEL0_ISCC60_Pos (0UL)
7190 #define CCU6_PISEL0_ISCC60_Msk (0x3UL)
7191 #define CCU6_PISEL0_ISCC61_Pos (2UL)
7192 #define CCU6_PISEL0_ISCC61_Msk (0xcUL)
7193 #define CCU6_PISEL0_ISCC62_Pos (4UL)
7194 #define CCU6_PISEL0_ISCC62_Msk (0x30UL)
7195 #define CCU6_PISEL0_ISTRP_Pos (6UL)
7196 #define CCU6_PISEL0_ISTRP_Msk (0xc0UL)
7197 #define CCU6_PISEL0_ISPOS0_Pos (8UL)
7198 #define CCU6_PISEL0_ISPOS0_Msk (0x300UL)
7199 #define CCU6_PISEL0_ISPOS1_Pos (10UL)
7200 #define CCU6_PISEL0_ISPOS1_Msk (0xc00UL)
7201 #define CCU6_PISEL0_ISPOS2_Pos (12UL)
7202 #define CCU6_PISEL0_ISPOS2_Msk (0x3000UL)
7203 #define CCU6_PISEL0_IST12HR_Pos (14UL)
7204 #define CCU6_PISEL0_IST12HR_Msk (0xc000UL)
7205 /* ======================================================== PISEL2 ========================================================= */
7206 #define CCU6_PISEL2_IST13HR_Pos (0UL)
7207 #define CCU6_PISEL2_IST13HR_Msk (0x3UL)
7208 #define CCU6_PISEL2_ISCNT12_Pos (2UL)
7209 #define CCU6_PISEL2_ISCNT12_Msk (0xcUL)
7210 #define CCU6_PISEL2_ISCNT13_Pos (4UL)
7211 #define CCU6_PISEL2_ISCNT13_Msk (0x30UL)
7212 #define CCU6_PISEL2_T12EXT_Pos (6UL)
7213 #define CCU6_PISEL2_T12EXT_Msk (0x40UL)
7214 #define CCU6_PISEL2_T13EXT_Pos (7UL)
7215 #define CCU6_PISEL2_T13EXT_Msk (0x80UL)
7216 /* ========================================================= PSLR ========================================================== */
7217 #define CCU6_PSLR_PSL_Pos (0UL)
7218 #define CCU6_PSLR_PSL_Msk (0x3fUL)
7219 #define CCU6_PSLR_PSL63_Pos (7UL)
7220 #define CCU6_PSLR_PSL63_Msk (0x80UL)
7221 /* ========================================================== T12 ========================================================== */
7222 #define CCU6_T12_T12CV_Pos (0UL)
7223 #define CCU6_T12_T12CV_Msk (0xffffUL)
7224 /* ======================================================== T12DTC ========================================================= */
7225 #define CCU6_T12DTC_DTM_Pos (0UL)
7226 #define CCU6_T12DTC_DTM_Msk (0xffUL)
7227 #define CCU6_T12DTC_DTE0_Pos (8UL)
7228 #define CCU6_T12DTC_DTE0_Msk (0x100UL)
7229 #define CCU6_T12DTC_DTE1_Pos (9UL)
7230 #define CCU6_T12DTC_DTE1_Msk (0x200UL)
7231 #define CCU6_T12DTC_DTE2_Pos (10UL)
7232 #define CCU6_T12DTC_DTE2_Msk (0x400UL)
7233 #define CCU6_T12DTC_DTR0_Pos (12UL)
7234 #define CCU6_T12DTC_DTR0_Msk (0x1000UL)
7235 #define CCU6_T12DTC_DTR1_Pos (13UL)
7236 #define CCU6_T12DTC_DTR1_Msk (0x2000UL)
7237 #define CCU6_T12DTC_DTR2_Pos (14UL)
7238 #define CCU6_T12DTC_DTR2_Msk (0x4000UL)
7239 /* ======================================================== T12MSEL ======================================================== */
7240 #define CCU6_T12MSEL_MSEL60_Pos (0UL)
7241 #define CCU6_T12MSEL_MSEL60_Msk (0xfUL)
7242 #define CCU6_T12MSEL_MSEL61_Pos (4UL)
7243 #define CCU6_T12MSEL_MSEL61_Msk (0xf0UL)
7244 #define CCU6_T12MSEL_MSEL62_Pos (8UL)
7245 #define CCU6_T12MSEL_MSEL62_Msk (0xf00UL)
7246 #define CCU6_T12MSEL_HSYNC_Pos (12UL)
7247 #define CCU6_T12MSEL_HSYNC_Msk (0x7000UL)
7248 #define CCU6_T12MSEL_DBYP_Pos (15UL)
7249 #define CCU6_T12MSEL_DBYP_Msk (0x8000UL)
7250 /* ========================================================= T12PR ========================================================= */
7251 #define CCU6_T12PR_T12PV_Pos (0UL)
7252 #define CCU6_T12PR_T12PV_Msk (0xffffUL)
7253 /* ========================================================== T13 ========================================================== */
7254 #define CCU6_T13_T13CV_Pos (0UL)
7255 #define CCU6_T13_T13CV_Msk (0xffffUL)
7256 /* ========================================================= T13PR ========================================================= */
7257 #define CCU6_T13PR_T13PV_Pos (0UL)
7258 #define CCU6_T13PR_T13PV_Msk (0xffffUL)
7259 /* ========================================================= TCTR0 ========================================================= */
7260 #define CCU6_TCTR0_T12CLK_Pos (0UL)
7261 #define CCU6_TCTR0_T12CLK_Msk (0x7UL)
7262 #define CCU6_TCTR0_T12PRE_Pos (3UL)
7263 #define CCU6_TCTR0_T12PRE_Msk (0x8UL)
7264 #define CCU6_TCTR0_T12R_Pos (4UL)
7265 #define CCU6_TCTR0_T12R_Msk (0x10UL)
7266 #define CCU6_TCTR0_STE12_Pos (5UL)
7267 #define CCU6_TCTR0_STE12_Msk (0x20UL)
7268 #define CCU6_TCTR0_CDIR_Pos (6UL)
7269 #define CCU6_TCTR0_CDIR_Msk (0x40UL)
7270 #define CCU6_TCTR0_CTM_Pos (7UL)
7271 #define CCU6_TCTR0_CTM_Msk (0x80UL)
7272 #define CCU6_TCTR0_T13CLK_Pos (8UL)
7273 #define CCU6_TCTR0_T13CLK_Msk (0x700UL)
7274 #define CCU6_TCTR0_T13PRE_Pos (11UL)
7275 #define CCU6_TCTR0_T13PRE_Msk (0x800UL)
7276 #define CCU6_TCTR0_T13R_Pos (12UL)
7277 #define CCU6_TCTR0_T13R_Msk (0x1000UL)
7278 #define CCU6_TCTR0_STE13_Pos (13UL)
7279 #define CCU6_TCTR0_STE13_Msk (0x2000UL)
7280 /* ========================================================= TCTR2 ========================================================= */
7281 #define CCU6_TCTR2_T12SSC_Pos (0UL)
7282 #define CCU6_TCTR2_T12SSC_Msk (0x1UL)
7283 #define CCU6_TCTR2_T13SSC_Pos (1UL)
7284 #define CCU6_TCTR2_T13SSC_Msk (0x2UL)
7285 #define CCU6_TCTR2_T13TEC_Pos (2UL)
7286 #define CCU6_TCTR2_T13TEC_Msk (0x1cUL)
7287 #define CCU6_TCTR2_T13TED_Pos (5UL)
7288 #define CCU6_TCTR2_T13TED_Msk (0x60UL)
7289 #define CCU6_TCTR2_T12RSEL_Pos (8UL)
7290 #define CCU6_TCTR2_T12RSEL_Msk (0x300UL)
7291 #define CCU6_TCTR2_T13RSEL_Pos (10UL)
7292 #define CCU6_TCTR2_T13RSEL_Msk (0xc00UL)
7293 /* ========================================================= TCTR4 ========================================================= */
7294 #define CCU6_TCTR4_T12RR_Pos (0UL)
7295 #define CCU6_TCTR4_T12RR_Msk (0x1UL)
7296 #define CCU6_TCTR4_T12RS_Pos (1UL)
7297 #define CCU6_TCTR4_T12RS_Msk (0x2UL)
7298 #define CCU6_TCTR4_T12RES_Pos (2UL)
7299 #define CCU6_TCTR4_T12RES_Msk (0x4UL)
7300 #define CCU6_TCTR4_DTRES_Pos (3UL)
7301 #define CCU6_TCTR4_DTRES_Msk (0x8UL)
7302 #define CCU6_TCTR4_T12CNT_Pos (5UL)
7303 #define CCU6_TCTR4_T12CNT_Msk (0x20UL)
7304 #define CCU6_TCTR4_T12STR_Pos (6UL)
7305 #define CCU6_TCTR4_T12STR_Msk (0x40UL)
7306 #define CCU6_TCTR4_T12STD_Pos (7UL)
7307 #define CCU6_TCTR4_T12STD_Msk (0x80UL)
7308 #define CCU6_TCTR4_T13RR_Pos (8UL)
7309 #define CCU6_TCTR4_T13RR_Msk (0x100UL)
7310 #define CCU6_TCTR4_T13RS_Pos (9UL)
7311 #define CCU6_TCTR4_T13RS_Msk (0x200UL)
7312 #define CCU6_TCTR4_T13RES_Pos (10UL)
7313 #define CCU6_TCTR4_T13RES_Msk (0x400UL)
7314 #define CCU6_TCTR4_T13CNT_Pos (13UL)
7315 #define CCU6_TCTR4_T13CNT_Msk (0x2000UL)
7316 #define CCU6_TCTR4_T13STR_Pos (14UL)
7317 #define CCU6_TCTR4_T13STR_Msk (0x4000UL)
7318 #define CCU6_TCTR4_T13STD_Pos (15UL)
7319 #define CCU6_TCTR4_T13STD_Msk (0x8000UL)
7320 /* ======================================================== TRPCTR ========================================================= */
7321 #define CCU6_TRPCTR_TRPM0_Pos (0UL)
7322 #define CCU6_TRPCTR_TRPM0_Msk (0x1UL)
7323 #define CCU6_TRPCTR_TRPM1_Pos (1UL)
7324 #define CCU6_TRPCTR_TRPM1_Msk (0x2UL)
7325 #define CCU6_TRPCTR_TRPM2_Pos (2UL)
7326 #define CCU6_TRPCTR_TRPM2_Msk (0x4UL)
7327 #define CCU6_TRPCTR_TRPEN_Pos (8UL)
7328 #define CCU6_TRPCTR_TRPEN_Msk (0x3f00UL)
7329 #define CCU6_TRPCTR_TRPEN13_Pos (14UL)
7330 #define CCU6_TRPCTR_TRPEN13_Msk (0x4000UL)
7331 #define CCU6_TRPCTR_TRPPEN_Pos (15UL)
7332 #define CCU6_TRPCTR_TRPPEN_Msk (0x8000UL)
7335 /* =========================================================================================================================== */
7336 /* ================ CPU ================ */
7337 /* =========================================================================================================================== */
7338 
7339 /* ========================================================= AFSR ========================================================== */
7340 #define CPU_AFSR_CP0_Pos (0UL)
7341 #define CPU_AFSR_CP0_Msk (0x3UL)
7342 #define CPU_AFSR_CP1_Pos (2UL)
7343 #define CPU_AFSR_CP1_Msk (0xcUL)
7344 #define CPU_AFSR_CP2_Pos (4UL)
7345 #define CPU_AFSR_CP2_Msk (0x30UL)
7346 #define CPU_AFSR_CP3_Pos (6UL)
7347 #define CPU_AFSR_CP3_Msk (0xc0UL)
7348 #define CPU_AFSR_CP4_Pos (8UL)
7349 #define CPU_AFSR_CP4_Msk (0x300UL)
7350 #define CPU_AFSR_CP5_Pos (10UL)
7351 #define CPU_AFSR_CP5_Msk (0xc00UL)
7352 #define CPU_AFSR_CP6_Pos (12UL)
7353 #define CPU_AFSR_CP6_Msk (0x3000UL)
7354 #define CPU_AFSR_CP7_Pos (14UL)
7355 #define CPU_AFSR_CP7_Msk (0xc000UL)
7356 #define CPU_AFSR_CP10_Pos (20UL)
7357 #define CPU_AFSR_CP10_Msk (0x300000UL)
7358 #define CPU_AFSR_CP11_Pos (22UL)
7359 #define CPU_AFSR_CP11_Msk (0xc00000UL)
7360 /* ========================================================= AIRCR ========================================================= */
7361 #define CPU_AIRCR_VECTKEY_Pos (16UL)
7362 #define CPU_AIRCR_VECTKEY_Msk (0xffff0000UL)
7363 #define CPU_AIRCR_ENDIANNESS_Pos (15UL)
7364 #define CPU_AIRCR_ENDIANNESS_Msk (0x8000UL)
7365 #define CPU_AIRCR_PRIGROUP_Pos (8UL)
7366 #define CPU_AIRCR_PRIGROUP_Msk (0x700UL)
7367 #define CPU_AIRCR_SYSRESETREQ_Pos (2UL)
7368 #define CPU_AIRCR_SYSRESETREQ_Msk (0x4UL)
7369 #define CPU_AIRCR_VECTCLRACTIVE_Pos (1UL)
7370 #define CPU_AIRCR_VECTCLRACTIVE_Msk (0x2UL)
7371 #define CPU_AIRCR_VECTRESET_Pos (0UL)
7372 #define CPU_AIRCR_VECTRESET_Msk (0x1UL)
7373 /* ========================================================= BFAR ========================================================== */
7374 #define CPU_BFAR_ADDRESS_Pos (0UL)
7375 #define CPU_BFAR_ADDRESS_Msk (0xffffffffUL)
7376 /* ========================================================== CCR ========================================================== */
7377 #define CPU_CCR_STKALIGN_Pos (9UL)
7378 #define CPU_CCR_STKALIGN_Msk (0x200UL)
7379 #define CPU_CCR_BFHFMIGN_Pos (8UL)
7380 #define CPU_CCR_BFHFMIGN_Msk (0x100UL)
7381 #define CPU_CCR_DIV_0_TRP_Pos (4UL)
7382 #define CPU_CCR_DIV_0_TRP_Msk (0x10UL)
7383 #define CPU_CCR_UNALIGN_TRP_Pos (3UL)
7384 #define CPU_CCR_UNALIGN_TRP_Msk (0x8UL)
7385 #define CPU_CCR_USERSETMPEND_Pos (1UL)
7386 #define CPU_CCR_USERSETMPEND_Msk (0x2UL)
7387 #define CPU_CCR_NONBASETHRDENA_Pos (0UL)
7388 #define CPU_CCR_NONBASETHRDENA_Msk (0x1UL)
7389 /* ========================================================= CFSR ========================================================== */
7390 #define CPU_CFSR_DIVBYZERO_Pos (25UL)
7391 #define CPU_CFSR_DIVBYZERO_Msk (0x2000000UL)
7392 #define CPU_CFSR_UNALIGNED_Pos (24UL)
7393 #define CPU_CFSR_UNALIGNED_Msk (0x1000000UL)
7394 #define CPU_CFSR_NOCP_Pos (19UL)
7395 #define CPU_CFSR_NOCP_Msk (0x80000UL)
7396 #define CPU_CFSR_INVPC_Pos (18UL)
7397 #define CPU_CFSR_INVPC_Msk (0x40000UL)
7398 #define CPU_CFSR_INVSTATE_Pos (17UL)
7399 #define CPU_CFSR_INVSTATE_Msk (0x20000UL)
7400 #define CPU_CFSR_UNDEFINSTR_Pos (16UL)
7401 #define CPU_CFSR_UNDEFINSTR_Msk (0x10000UL)
7402 #define CPU_CFSR_BFARVALID_Pos (15UL)
7403 #define CPU_CFSR_BFARVALID_Msk (0x8000UL)
7404 #define CPU_CFSR_STKERR_Pos (12UL)
7405 #define CPU_CFSR_STKERR_Msk (0x1000UL)
7406 #define CPU_CFSR_UNSTKERR_Pos (11UL)
7407 #define CPU_CFSR_UNSTKERR_Msk (0x800UL)
7408 #define CPU_CFSR_IMPRECISERR_Pos (10UL)
7409 #define CPU_CFSR_IMPRECISERR_Msk (0x400UL)
7410 #define CPU_CFSR_PRECISERR_Pos (9UL)
7411 #define CPU_CFSR_PRECISERR_Msk (0x200UL)
7412 #define CPU_CFSR_IBUSERR_Pos (8UL)
7413 #define CPU_CFSR_IBUSERR_Msk (0x100UL)
7414 #define CPU_CFSR_MMARVALID_Pos (7UL)
7415 #define CPU_CFSR_MMARVALID_Msk (0x80UL)
7416 #define CPU_CFSR_MSTERR_Pos (4UL)
7417 #define CPU_CFSR_MSTERR_Msk (0x10UL)
7418 #define CPU_CFSR_MUNSTKERR_Pos (3UL)
7419 #define CPU_CFSR_MUNSTKERR_Msk (0x8UL)
7420 #define CPU_CFSR_DACCVIOL_Pos (1UL)
7421 #define CPU_CFSR_DACCVIOL_Msk (0x2UL)
7422 #define CPU_CFSR_IACCVIOL_Pos (0UL)
7423 #define CPU_CFSR_IACCVIOL_Msk (0x1UL)
7424 /* ========================================================= CPUID ========================================================= */
7425 #define CPU_CPUID_IMPLEMENTER_Pos (24UL)
7426 #define CPU_CPUID_IMPLEMENTER_Msk (0xff000000UL)
7427 #define CPU_CPUID_VARIANT_Pos (20UL)
7428 #define CPU_CPUID_VARIANT_Msk (0xf00000UL)
7429 #define CPU_CPUID_ARCHITECTURE_Pos (16UL)
7430 #define CPU_CPUID_ARCHITECTURE_Msk (0xf0000UL)
7431 #define CPU_CPUID_PARTNO_Pos (4UL)
7432 #define CPU_CPUID_PARTNO_Msk (0xfff0UL)
7433 #define CPU_CPUID_REVISION_Pos (0UL)
7434 #define CPU_CPUID_REVISION_Msk (0xfUL)
7435 /* ========================================================= DFSR ========================================================== */
7436 #define CPU_DFSR_EXTERNAL_Pos (4UL)
7437 #define CPU_DFSR_EXTERNAL_Msk (0x10UL)
7438 #define CPU_DFSR_VCATCH_Pos (3UL)
7439 #define CPU_DFSR_VCATCH_Msk (0x8UL)
7440 #define CPU_DFSR_DWTTRAP_Pos (2UL)
7441 #define CPU_DFSR_DWTTRAP_Msk (0x4UL)
7442 #define CPU_DFSR_BKPT_Pos (1UL)
7443 #define CPU_DFSR_BKPT_Msk (0x2UL)
7444 #define CPU_DFSR_HALTED_Pos (0UL)
7445 #define CPU_DFSR_HALTED_Msk (0x1UL)
7446 /* ========================================================= HFSR ========================================================== */
7447 #define CPU_HFSR_DEBUGEVT_Pos (31UL)
7448 #define CPU_HFSR_DEBUGEVT_Msk (0x80000000UL)
7449 #define CPU_HFSR_FORCED_Pos (30UL)
7450 #define CPU_HFSR_FORCED_Msk (0x40000000UL)
7451 #define CPU_HFSR_VECTTBL_Pos (1UL)
7452 #define CPU_HFSR_VECTTBL_Msk (0x2UL)
7453 /* ========================================================= ICSR ========================================================== */
7454 #define CPU_ICSR_NMIPENDSET_Pos (31UL)
7455 #define CPU_ICSR_NMIPENDSET_Msk (0x80000000UL)
7456 #define CPU_ICSR_PENDSVSET_Pos (28UL)
7457 #define CPU_ICSR_PENDSVSET_Msk (0x10000000UL)
7458 #define CPU_ICSR_PENDSVCLR_Pos (27UL)
7459 #define CPU_ICSR_PENDSVCLR_Msk (0x8000000UL)
7460 #define CPU_ICSR_PENDSTSET_Pos (26UL)
7461 #define CPU_ICSR_PENDSTSET_Msk (0x4000000UL)
7462 #define CPU_ICSR_PENDSTCLR_Pos (25UL)
7463 #define CPU_ICSR_PENDSTCLR_Msk (0x2000000UL)
7464 #define CPU_ICSR_ISRPREEMPT_Pos (23UL)
7465 #define CPU_ICSR_ISRPREEMPT_Msk (0x800000UL)
7466 #define CPU_ICSR_ISRPENDING_Pos (22UL)
7467 #define CPU_ICSR_ISRPENDING_Msk (0x400000UL)
7468 #define CPU_ICSR_VECTPENDING_Pos (12UL)
7469 #define CPU_ICSR_VECTPENDING_Msk (0x1ff000UL)
7470 #define CPU_ICSR_RETTOBASE_Pos (11UL)
7471 #define CPU_ICSR_RETTOBASE_Msk (0x800UL)
7472 #define CPU_ICSR_VECTACTIVE_Pos (0UL)
7473 #define CPU_ICSR_VECTACTIVE_Msk (0x1ffUL)
7474 /* ========================================================== ICT ========================================================== */
7475 #define CPU_ICT_INTLINESNUM_Pos (0UL)
7476 #define CPU_ICT_INTLINESNUM_Msk (0x1fUL)
7477 /* ========================================================= MMFAR ========================================================= */
7478 #define CPU_MMFAR_ADDRESS_Pos (0UL)
7479 #define CPU_MMFAR_ADDRESS_Msk (0xffffffffUL)
7480 /* ====================================================== NVIC_IABR0 ======================================================= */
7481 #define CPU_NVIC_IABR0_Int_DMA_Pos (15UL)
7482 #define CPU_NVIC_IABR0_Int_DMA_Msk (0x8000UL)
7483 #define CPU_NVIC_IABR0_Int_BDRV_Pos (14UL)
7484 #define CPU_NVIC_IABR0_Int_BDRV_Msk (0x4000UL)
7485 #define CPU_NVIC_IABR0_Int_EXINT1_Pos (13UL)
7486 #define CPU_NVIC_IABR0_Int_EXINT1_Msk (0x2000UL)
7487 #define CPU_NVIC_IABR0_Int_EXINT0_Pos (12UL)
7488 #define CPU_NVIC_IABR0_Int_EXINT0_Msk (0x1000UL)
7489 #define CPU_NVIC_IABR0_Int_UART2_Pos (11UL)
7490 #define CPU_NVIC_IABR0_Int_UART2_Msk (0x800UL)
7491 #define CPU_NVIC_IABR0_Int_UART1_Pos (10UL)
7492 #define CPU_NVIC_IABR0_Int_UART1_Msk (0x400UL)
7493 #define CPU_NVIC_IABR0_Int_SSC2_Pos (9UL)
7494 #define CPU_NVIC_IABR0_Int_SSC2_Msk (0x200UL)
7495 #define CPU_NVIC_IABR0_Int_SSC1_Pos (8UL)
7496 #define CPU_NVIC_IABR0_Int_SSC1_Msk (0x100UL)
7497 #define CPU_NVIC_IABR0_Int_CCU6SR3_Pos (7UL)
7498 #define CPU_NVIC_IABR0_Int_CCU6SR3_Msk (0x80UL)
7499 #define CPU_NVIC_IABR0_Int_CCU6SR2_Pos (6UL)
7500 #define CPU_NVIC_IABR0_Int_CCU6SR2_Msk (0x40UL)
7501 #define CPU_NVIC_IABR0_Int_CCU6SR1_Pos (5UL)
7502 #define CPU_NVIC_IABR0_Int_CCU6SR1_Msk (0x20UL)
7503 #define CPU_NVIC_IABR0_Int_CCU6SR0_Pos (4UL)
7504 #define CPU_NVIC_IABR0_Int_CCU6SR0_Msk (0x10UL)
7505 #define CPU_NVIC_IABR0_Int_ADC1_Pos (3UL)
7506 #define CPU_NVIC_IABR0_Int_ADC1_Msk (0x8UL)
7507 #define CPU_NVIC_IABR0_Int_ADC2_Pos (2UL)
7508 #define CPU_NVIC_IABR0_Int_ADC2_Msk (0x4UL)
7509 #define CPU_NVIC_IABR0_Int_GPT2_Pos (1UL)
7510 #define CPU_NVIC_IABR0_Int_GPT2_Msk (0x2UL)
7511 #define CPU_NVIC_IABR0_Int_GPT1_Pos (0UL)
7512 #define CPU_NVIC_IABR0_Int_GPT1_Msk (0x1UL)
7513 /* ====================================================== NVIC_ICER0 ======================================================= */
7514 #define CPU_NVIC_ICER0_Int_DMA_Pos (15UL)
7515 #define CPU_NVIC_ICER0_Int_DMA_Msk (0x8000UL)
7516 #define CPU_NVIC_ICER0_Int_BDRV_Pos (14UL)
7517 #define CPU_NVIC_ICER0_Int_BDRV_Msk (0x4000UL)
7518 #define CPU_NVIC_ICER0_Int_EXINT1_Pos (13UL)
7519 #define CPU_NVIC_ICER0_Int_EXINT1_Msk (0x2000UL)
7520 #define CPU_NVIC_ICER0_Int_EXINT0_Pos (12UL)
7521 #define CPU_NVIC_ICER0_Int_EXINT0_Msk (0x1000UL)
7522 #define CPU_NVIC_ICER0_Int_UART2_Pos (11UL)
7523 #define CPU_NVIC_ICER0_Int_UART2_Msk (0x800UL)
7524 #define CPU_NVIC_ICER0_Int_UART1_Pos (10UL)
7525 #define CPU_NVIC_ICER0_Int_UART1_Msk (0x400UL)
7526 #define CPU_NVIC_ICER0_Int_SSC2_Pos (9UL)
7527 #define CPU_NVIC_ICER0_Int_SSC2_Msk (0x200UL)
7528 #define CPU_NVIC_ICER0_Int_SSC1_Pos (8UL)
7529 #define CPU_NVIC_ICER0_Int_SSC1_Msk (0x100UL)
7530 #define CPU_NVIC_ICER0_Int_CCU6SR3_Pos (7UL)
7531 #define CPU_NVIC_ICER0_Int_CCU6SR3_Msk (0x80UL)
7532 #define CPU_NVIC_ICER0_Int_CCU6SR2_Pos (6UL)
7533 #define CPU_NVIC_ICER0_Int_CCU6SR2_Msk (0x40UL)
7534 #define CPU_NVIC_ICER0_Int_CCU6SR1_Pos (5UL)
7535 #define CPU_NVIC_ICER0_Int_CCU6SR1_Msk (0x20UL)
7536 #define CPU_NVIC_ICER0_Int_CCU6SR0_Pos (4UL)
7537 #define CPU_NVIC_ICER0_Int_CCU6SR0_Msk (0x10UL)
7538 #define CPU_NVIC_ICER0_Int_ADC1_Pos (3UL)
7539 #define CPU_NVIC_ICER0_Int_ADC1_Msk (0x8UL)
7540 #define CPU_NVIC_ICER0_Int_ADC2_Pos (2UL)
7541 #define CPU_NVIC_ICER0_Int_ADC2_Msk (0x4UL)
7542 #define CPU_NVIC_ICER0_Int_GPT2_Pos (1UL)
7543 #define CPU_NVIC_ICER0_Int_GPT2_Msk (0x2UL)
7544 #define CPU_NVIC_ICER0_Int_GPT1_Pos (0UL)
7545 #define CPU_NVIC_ICER0_Int_GPT1_Msk (0x1UL)
7546 /* ====================================================== NVIC_ICPR0 ======================================================= */
7547 #define CPU_NVIC_ICPR0_Int_DMA_Pos (15UL)
7548 #define CPU_NVIC_ICPR0_Int_DMA_Msk (0x8000UL)
7549 #define CPU_NVIC_ICPR0_Int_BDRV_Pos (14UL)
7550 #define CPU_NVIC_ICPR0_Int_BDRV_Msk (0x4000UL)
7551 #define CPU_NVIC_ICPR0_Int_EXINT1_Pos (13UL)
7552 #define CPU_NVIC_ICPR0_Int_EXINT1_Msk (0x2000UL)
7553 #define CPU_NVIC_ICPR0_Int_EXINT0_Pos (12UL)
7554 #define CPU_NVIC_ICPR0_Int_EXINT0_Msk (0x1000UL)
7555 #define CPU_NVIC_ICPR0_Int_UART2_Pos (11UL)
7556 #define CPU_NVIC_ICPR0_Int_UART2_Msk (0x800UL)
7557 #define CPU_NVIC_ICPR0_Int_UART1_Pos (10UL)
7558 #define CPU_NVIC_ICPR0_Int_UART1_Msk (0x400UL)
7559 #define CPU_NVIC_ICPR0_Int_SSC2_Pos (9UL)
7560 #define CPU_NVIC_ICPR0_Int_SSC2_Msk (0x200UL)
7561 #define CPU_NVIC_ICPR0_Int_SSC1_Pos (8UL)
7562 #define CPU_NVIC_ICPR0_Int_SSC1_Msk (0x100UL)
7563 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Pos (7UL)
7564 #define CPU_NVIC_ICPR0_Int_CCU6SR3_Msk (0x80UL)
7565 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Pos (6UL)
7566 #define CPU_NVIC_ICPR0_Int_CCU6SR2_Msk (0x40UL)
7567 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Pos (5UL)
7568 #define CPU_NVIC_ICPR0_Int_CCU6SR1_Msk (0x20UL)
7569 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Pos (4UL)
7570 #define CPU_NVIC_ICPR0_Int_CCU6SR0_Msk (0x10UL)
7571 #define CPU_NVIC_ICPR0_Int_ADC1_Pos (3UL)
7572 #define CPU_NVIC_ICPR0_Int_ADC1_Msk (0x8UL)
7573 #define CPU_NVIC_ICPR0_Int_ADC2_Pos (2UL)
7574 #define CPU_NVIC_ICPR0_Int_ADC2_Msk (0x4UL)
7575 #define CPU_NVIC_ICPR0_Int_GPT2_Pos (1UL)
7576 #define CPU_NVIC_ICPR0_Int_GPT2_Msk (0x2UL)
7577 #define CPU_NVIC_ICPR0_Int_GPT1_Pos (0UL)
7578 #define CPU_NVIC_ICPR0_Int_GPT1_Msk (0x1UL)
7579 /* ======================================================= NVIC_IPR0 ======================================================= */
7580 #define CPU_NVIC_IPR0_PRI_ADC1_Pos (24UL)
7581 #define CPU_NVIC_IPR0_PRI_ADC1_Msk (0xff000000UL)
7582 #define CPU_NVIC_IPR0_PRI_ADC2_Pos (16UL)
7583 #define CPU_NVIC_IPR0_PRI_ADC2_Msk (0xff0000UL)
7584 #define CPU_NVIC_IPR0_PRI_GPT2_Pos (8UL)
7585 #define CPU_NVIC_IPR0_PRI_GPT2_Msk (0xff00UL)
7586 #define CPU_NVIC_IPR0_PRI_GPT1_Pos (0UL)
7587 #define CPU_NVIC_IPR0_PRI_GPT1_Msk (0xffUL)
7588 /* ======================================================= NVIC_IPR1 ======================================================= */
7589 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Pos (24UL)
7590 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Msk (0xff000000UL)
7591 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Pos (16UL)
7592 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Msk (0xff0000UL)
7593 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Pos (8UL)
7594 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Msk (0xff00UL)
7595 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Pos (0UL)
7596 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Msk (0xffUL)
7597 /* ======================================================= NVIC_IPR2 ======================================================= */
7598 #define CPU_NVIC_IPR2_PRI_UART2_Pos (24UL)
7599 #define CPU_NVIC_IPR2_PRI_UART2_Msk (0xff000000UL)
7600 #define CPU_NVIC_IPR2_PRI_UART1_Pos (16UL)
7601 #define CPU_NVIC_IPR2_PRI_UART1_Msk (0xff0000UL)
7602 #define CPU_NVIC_IPR2_PRI_SSC2_Pos (8UL)
7603 #define CPU_NVIC_IPR2_PRI_SSC2_Msk (0xff00UL)
7604 #define CPU_NVIC_IPR2_PRI_SSC1_Pos (0UL)
7605 #define CPU_NVIC_IPR2_PRI_SSC1_Msk (0xffUL)
7606 /* ======================================================= NVIC_IPR3 ======================================================= */
7607 #define CPU_NVIC_IPR3_PRI_DMA_Pos (24UL)
7608 #define CPU_NVIC_IPR3_PRI_DMA_Msk (0xff000000UL)
7609 #define CPU_NVIC_IPR3_PRI_BDRV_Pos (16UL)
7610 #define CPU_NVIC_IPR3_PRI_BDRV_Msk (0xff0000UL)
7611 #define CPU_NVIC_IPR3_PRI_EXINT1_Pos (8UL)
7612 #define CPU_NVIC_IPR3_PRI_EXINT1_Msk (0xff00UL)
7613 #define CPU_NVIC_IPR3_PRI_EXINT0_Pos (0UL)
7614 #define CPU_NVIC_IPR3_PRI_EXINT0_Msk (0xffUL)
7615 /* ====================================================== NVIC_ISER0 ======================================================= */
7616 #define CPU_NVIC_ISER0_Int_DMA_Pos (15UL)
7617 #define CPU_NVIC_ISER0_Int_DMA_Msk (0x8000UL)
7618 #define CPU_NVIC_ISER0_Int_BDRV_Pos (14UL)
7619 #define CPU_NVIC_ISER0_Int_BDRV_Msk (0x4000UL)
7620 #define CPU_NVIC_ISER0_Int_EXINT1_Pos (13UL)
7621 #define CPU_NVIC_ISER0_Int_EXINT1_Msk (0x2000UL)
7622 #define CPU_NVIC_ISER0_Int_EXINT0_Pos (12UL)
7623 #define CPU_NVIC_ISER0_Int_EXINT0_Msk (0x1000UL)
7624 #define CPU_NVIC_ISER0_Int_UART2_Pos (11UL)
7625 #define CPU_NVIC_ISER0_Int_UART2_Msk (0x800UL)
7626 #define CPU_NVIC_ISER0_Int_UART1_Pos (10UL)
7627 #define CPU_NVIC_ISER0_Int_UART1_Msk (0x400UL)
7628 #define CPU_NVIC_ISER0_Int_SSC2_Pos (9UL)
7629 #define CPU_NVIC_ISER0_Int_SSC2_Msk (0x200UL)
7630 #define CPU_NVIC_ISER0_Int_SSC1_Pos (8UL)
7631 #define CPU_NVIC_ISER0_Int_SSC1_Msk (0x100UL)
7632 #define CPU_NVIC_ISER0_Int_CCU6SR3_Pos (7UL)
7633 #define CPU_NVIC_ISER0_Int_CCU6SR3_Msk (0x80UL)
7634 #define CPU_NVIC_ISER0_Int_CCU6SR2_Pos (6UL)
7635 #define CPU_NVIC_ISER0_Int_CCU6SR2_Msk (0x40UL)
7636 #define CPU_NVIC_ISER0_Int_CCU6SR1_Pos (5UL)
7637 #define CPU_NVIC_ISER0_Int_CCU6SR1_Msk (0x20UL)
7638 #define CPU_NVIC_ISER0_Int_CCU6SR0_Pos (4UL)
7639 #define CPU_NVIC_ISER0_Int_CCU6SR0_Msk (0x10UL)
7640 #define CPU_NVIC_ISER0_Int_ADC1_Pos (3UL)
7641 #define CPU_NVIC_ISER0_Int_ADC1_Msk (0x8UL)
7642 #define CPU_NVIC_ISER0_Int_ADC2_Pos (2UL)
7643 #define CPU_NVIC_ISER0_Int_ADC2_Msk (0x4UL)
7644 #define CPU_NVIC_ISER0_Int_GPT2_Pos (1UL)
7645 #define CPU_NVIC_ISER0_Int_GPT2_Msk (0x2UL)
7646 #define CPU_NVIC_ISER0_Int_GPT1_Pos (0UL)
7647 #define CPU_NVIC_ISER0_Int_GPT1_Msk (0x1UL)
7648 /* ====================================================== NVIC_ISPR0 ======================================================= */
7649 #define CPU_NVIC_ISPR0_Int_DMA_Pos (15UL)
7650 #define CPU_NVIC_ISPR0_Int_DMA_Msk (0x8000UL)
7651 #define CPU_NVIC_ISPR0_Int_BDRV_Pos (14UL)
7652 #define CPU_NVIC_ISPR0_Int_BDRV_Msk (0x4000UL)
7653 #define CPU_NVIC_ISPR0_Int_EXINT1_Pos (13UL)
7654 #define CPU_NVIC_ISPR0_Int_EXINT1_Msk (0x2000UL)
7655 #define CPU_NVIC_ISPR0_Int_EXINT0_Pos (12UL)
7656 #define CPU_NVIC_ISPR0_Int_EXINT0_Msk (0x1000UL)
7657 #define CPU_NVIC_ISPR0_Int_UART2_Pos (11UL)
7658 #define CPU_NVIC_ISPR0_Int_UART2_Msk (0x800UL)
7659 #define CPU_NVIC_ISPR0_Int_UART1_Pos (10UL)
7660 #define CPU_NVIC_ISPR0_Int_UART1_Msk (0x400UL)
7661 #define CPU_NVIC_ISPR0_Int_SSC2_Pos (9UL)
7662 #define CPU_NVIC_ISPR0_Int_SSC2_Msk (0x200UL)
7663 #define CPU_NVIC_ISPR0_Int_SSC1_Pos (8UL)
7664 #define CPU_NVIC_ISPR0_Int_SSC1_Msk (0x100UL)
7665 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Pos (7UL)
7666 #define CPU_NVIC_ISPR0_Int_CCU6SR3_Msk (0x80UL)
7667 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Pos (6UL)
7668 #define CPU_NVIC_ISPR0_Int_CCU6SR2_Msk (0x40UL)
7669 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Pos (5UL)
7670 #define CPU_NVIC_ISPR0_Int_CCU6SR1_Msk (0x20UL)
7671 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Pos (4UL)
7672 #define CPU_NVIC_ISPR0_Int_CCU6SR0_Msk (0x10UL)
7673 #define CPU_NVIC_ISPR0_Int_ADC1_Pos (3UL)
7674 #define CPU_NVIC_ISPR0_Int_ADC1_Msk (0x8UL)
7675 #define CPU_NVIC_ISPR0_Int_ADC2_Pos (2UL)
7676 #define CPU_NVIC_ISPR0_Int_ADC2_Msk (0x4UL)
7677 #define CPU_NVIC_ISPR0_Int_GPT2_Pos (1UL)
7678 #define CPU_NVIC_ISPR0_Int_GPT2_Msk (0x2UL)
7679 #define CPU_NVIC_ISPR0_Int_GPT1_Pos (0UL)
7680 #define CPU_NVIC_ISPR0_Int_GPT1_Msk (0x1UL)
7681 /* ========================================================== SCR ========================================================== */
7682 #define CPU_SCR_SEVONPEND_Pos (4UL)
7683 #define CPU_SCR_SEVONPEND_Msk (0x10UL)
7684 #define CPU_SCR_SLEEPDEEP_Pos (2UL)
7685 #define CPU_SCR_SLEEPDEEP_Msk (0x4UL)
7686 #define CPU_SCR_SLEEPONEXIT_Pos (1UL)
7687 #define CPU_SCR_SLEEPONEXIT_Msk (0x2UL)
7688 /* ========================================================= SHCSR ========================================================= */
7689 #define CPU_SHCSR_USGFAULTENA_Pos (18UL)
7690 #define CPU_SHCSR_USGFAULTENA_Msk (0x40000UL)
7691 #define CPU_SHCSR_BUSFAULTENA_Pos (17UL)
7692 #define CPU_SHCSR_BUSFAULTENA_Msk (0x20000UL)
7693 #define CPU_SHCSR_MEMFAULTENA_Pos (16UL)
7694 #define CPU_SHCSR_MEMFAULTENA_Msk (0x10000UL)
7695 #define CPU_SHCSR_SVCALLPENDED_Pos (15UL)
7696 #define CPU_SHCSR_SVCALLPENDED_Msk (0x8000UL)
7697 #define CPU_SHCSR_BUSFAULTPENDED_Pos (14UL)
7698 #define CPU_SHCSR_BUSFAULTPENDED_Msk (0x4000UL)
7699 #define CPU_SHCSR_MEMFAULTPENDED_Pos (13UL)
7700 #define CPU_SHCSR_MEMFAULTPENDED_Msk (0x2000UL)
7701 #define CPU_SHCSR_USGFAULTPENDED_Pos (12UL)
7702 #define CPU_SHCSR_USGFAULTPENDED_Msk (0x1000UL)
7703 #define CPU_SHCSR_SYSTICKACT_Pos (11UL)
7704 #define CPU_SHCSR_SYSTICKACT_Msk (0x800UL)
7705 #define CPU_SHCSR_PENDSVACT_Pos (10UL)
7706 #define CPU_SHCSR_PENDSVACT_Msk (0x400UL)
7707 #define CPU_SHCSR_MONITORACT_Pos (8UL)
7708 #define CPU_SHCSR_MONITORACT_Msk (0x100UL)
7709 #define CPU_SHCSR_SVCALLACT_Pos (7UL)
7710 #define CPU_SHCSR_SVCALLACT_Msk (0x80UL)
7711 #define CPU_SHCSR_USGFAULTACT_Pos (3UL)
7712 #define CPU_SHCSR_USGFAULTACT_Msk (0x8UL)
7713 #define CPU_SHCSR_BUSFAULTACT_Pos (1UL)
7714 #define CPU_SHCSR_BUSFAULTACT_Msk (0x2UL)
7715 #define CPU_SHCSR_MEMFAULTACT_Pos (0UL)
7716 #define CPU_SHCSR_MEMFAULTACT_Msk (0x1UL)
7717 /* ========================================================= SHPR1 ========================================================= */
7718 #define CPU_SHPR1_PRI_7_Pos (24UL)
7719 #define CPU_SHPR1_PRI_7_Msk (0xff000000UL)
7720 #define CPU_SHPR1_PRI_6_Pos (16UL)
7721 #define CPU_SHPR1_PRI_6_Msk (0xff0000UL)
7722 #define CPU_SHPR1_PRI_5_Pos (8UL)
7723 #define CPU_SHPR1_PRI_5_Msk (0xff00UL)
7724 #define CPU_SHPR1_PRI_4_Pos (0UL)
7725 #define CPU_SHPR1_PRI_4_Msk (0xffUL)
7726 /* ========================================================= SHPR2 ========================================================= */
7727 #define CPU_SHPR2_PRI_11_Pos (24UL)
7728 #define CPU_SHPR2_PRI_11_Msk (0xff000000UL)
7729 #define CPU_SHPR2_PRI_10_Pos (16UL)
7730 #define CPU_SHPR2_PRI_10_Msk (0xff0000UL)
7731 #define CPU_SHPR2_PRI_9_Pos (8UL)
7732 #define CPU_SHPR2_PRI_9_Msk (0xff00UL)
7733 #define CPU_SHPR2_PRI_8_Pos (0UL)
7734 #define CPU_SHPR2_PRI_8_Msk (0xffUL)
7735 /* ========================================================= SHPR3 ========================================================= */
7736 #define CPU_SHPR3_PRI_15_Pos (24UL)
7737 #define CPU_SHPR3_PRI_15_Msk (0xff000000UL)
7738 #define CPU_SHPR3_PRI_14_Pos (16UL)
7739 #define CPU_SHPR3_PRI_14_Msk (0xff0000UL)
7740 #define CPU_SHPR3_PRI_13_Pos (8UL)
7741 #define CPU_SHPR3_PRI_13_Msk (0xff00UL)
7742 #define CPU_SHPR3_PRI_12_Pos (0UL)
7743 #define CPU_SHPR3_PRI_12_Msk (0xffUL)
7744 /* ====================================================== SYSTICK_CAL ====================================================== */
7745 #define CPU_SYSTICK_CAL_NOREF_Pos (31UL)
7746 #define CPU_SYSTICK_CAL_NOREF_Msk (0x80000000UL)
7747 #define CPU_SYSTICK_CAL_SKEW_Pos (30UL)
7748 #define CPU_SYSTICK_CAL_SKEW_Msk (0x40000000UL)
7749 #define CPU_SYSTICK_CAL_TENMS_Pos (0UL)
7750 #define CPU_SYSTICK_CAL_TENMS_Msk (0xffffffUL)
7751 /* ====================================================== SYSTICK_CS ======================================================= */
7752 #define CPU_SYSTICK_CS_COUNTFLAG_Pos (16UL)
7753 #define CPU_SYSTICK_CS_COUNTFLAG_Msk (0x10000UL)
7754 #define CPU_SYSTICK_CS_CLKSOURCE_Pos (2UL)
7755 #define CPU_SYSTICK_CS_CLKSOURCE_Msk (0x4UL)
7756 #define CPU_SYSTICK_CS_TICKINT_Pos (1UL)
7757 #define CPU_SYSTICK_CS_TICKINT_Msk (0x2UL)
7758 #define CPU_SYSTICK_CS_ENABLE_Pos (0UL)
7759 #define CPU_SYSTICK_CS_ENABLE_Msk (0x1UL)
7760 /* ====================================================== SYSTICK_CUR ====================================================== */
7761 #define CPU_SYSTICK_CUR_CURRENT_Pos (0UL)
7762 #define CPU_SYSTICK_CUR_CURRENT_Msk (0xffffffUL)
7763 /* ====================================================== SYSTICK_RL ======================================================= */
7764 #define CPU_SYSTICK_RL_RELOAD_Pos (0UL)
7765 #define CPU_SYSTICK_RL_RELOAD_Msk (0xffffffUL)
7766 /* ========================================================= VTOR ========================================================== */
7767 #define CPU_VTOR_TBLOFF_Pos (7UL)
7768 #define CPU_VTOR_TBLOFF_Msk (0xffffff80UL)
7771 /* =========================================================================================================================== */
7772 /* ================ DMA ================ */
7773 /* =========================================================================================================================== */
7774 
7775 /* =================================================== ALT_CTRL_BASE_PTR =================================================== */
7776 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Pos (0UL)
7777 #define DMA_ALT_CTRL_BASE_PTR_ALT_CTRL_BASE_PTR_Msk (0xffffffffUL)
7778 /* ========================================================== CFG ========================================================== */
7779 #define DMA_CFG_CHN1_PROT_CTRL_Pos (5UL)
7780 #define DMA_CFG_CHN1_PROT_CTRL_Msk (0xe0UL)
7781 #define DMA_CFG_MASTER_ENABLE_Pos (0UL)
7782 #define DMA_CFG_MASTER_ENABLE_Msk (0x1UL)
7783 /* ==================================================== CHNL_ENABLE_CLR ==================================================== */
7784 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Pos (0UL)
7785 #define DMA_CHNL_ENABLE_CLR_CHNL_ENABLE_CLR_Msk (0x3fffUL)
7786 /* ==================================================== CHNL_ENABLE_SET ==================================================== */
7787 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos (0UL)
7788 #define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk (0x3fffUL)
7789 /* =================================================== CHNL_PRI_ALT_CLR ==================================================== */
7790 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos (0UL)
7791 #define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk (0x3fffUL)
7792 /* =================================================== CHNL_PRI_ALT_SET ==================================================== */
7793 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos (0UL)
7794 #define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk (0x3fffUL)
7795 /* =================================================== CHNL_PRIORITY_CLR =================================================== */
7796 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Pos (0UL)
7797 #define DMA_CHNL_PRIORITY_CLR_CHNL_PRIORITY_CLR_Msk (0x3fffUL)
7798 /* =================================================== CHNL_PRIORITY_SET =================================================== */
7799 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Pos (0UL)
7800 #define DMA_CHNL_PRIORITY_SET_CHNL_PRIORITY_SET_Msk (0x3fffUL)
7801 /* =================================================== CHNL_REQ_MASK_CLR =================================================== */
7802 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Pos (0UL)
7803 #define DMA_CHNL_REQ_MASK_CLR_CHNL_REQ_MASK_CLR_Msk (0x3fffUL)
7804 /* =================================================== CHNL_REQ_MASK_SET =================================================== */
7805 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Pos (0UL)
7806 #define DMA_CHNL_REQ_MASK_SET_CHNL_REQ_MASK_SET_Msk (0x3fffUL)
7807 /* ==================================================== CHNL_SW_REQUEST ==================================================== */
7808 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos (0UL)
7809 #define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk (0x3fffUL)
7810 /* =================================================== CHNL_USEBURST_CLR =================================================== */
7811 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Pos (0UL)
7812 #define DMA_CHNL_USEBURST_CLR_CHNL_USEBURST_CLR_Msk (0x3fffUL)
7813 /* =================================================== CHNL_USEBURST_SET =================================================== */
7814 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Pos (0UL)
7815 #define DMA_CHNL_USEBURST_SET_CHNL_USEBURST_SET_Msk (0x3fffUL)
7816 /* ===================================================== CTRL_BASE_PTR ===================================================== */
7817 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos (9UL)
7818 #define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk (0xfffffe00UL)
7819 /* ======================================================== ERR_CLR ======================================================== */
7820 #define DMA_ERR_CLR_ERR_CLR_Pos (0UL)
7821 #define DMA_ERR_CLR_ERR_CLR_Msk (0x1UL)
7822 /* ======================================================== STATUS ========================================================= */
7823 #define DMA_STATUS_CHNLS_MINUS1_Pos (16UL)
7824 #define DMA_STATUS_CHNLS_MINUS1_Msk (0x1f0000UL)
7825 #define DMA_STATUS_STATE_Pos (4UL)
7826 #define DMA_STATUS_STATE_Msk (0xf0UL)
7827 #define DMA_STATUS_MASTER_ENABLE_Pos (0UL)
7828 #define DMA_STATUS_MASTER_ENABLE_Msk (0x1UL)
7829 /* =================================================== WAITONREQ_STATUS ==================================================== */
7830 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Pos (0UL)
7831 #define DMA_WAITONREQ_STATUS_WAITONREQ_STATUS_Msk (0x3fffUL)
7834 /* =========================================================================================================================== */
7835 /* ================ GPT12E ================ */
7836 /* =========================================================================================================================== */
7837 
7838 /* ======================================================== CAPREL ========================================================= */
7839 #define GPT12E_CAPREL_CAPREL_Pos (0UL)
7840 #define GPT12E_CAPREL_CAPREL_Msk (0xffffUL)
7841 /* ========================================================== ID =========================================================== */
7842 #define GPT12E_ID_MOD_REV_Pos (0UL)
7843 #define GPT12E_ID_MOD_REV_Msk (0xffUL)
7844 #define GPT12E_ID_MOD_TYPE_Pos (8UL)
7845 #define GPT12E_ID_MOD_TYPE_Msk (0xff00UL)
7846 /* ========================================================= PISEL ========================================================= */
7847 #define GPT12E_PISEL_IST2IN_Pos (0UL)
7848 #define GPT12E_PISEL_IST2IN_Msk (0x1UL)
7849 #define GPT12E_PISEL_IST2EUD_Pos (1UL)
7850 #define GPT12E_PISEL_IST2EUD_Msk (0x2UL)
7851 #define GPT12E_PISEL_IST3IN_Pos (2UL)
7852 #define GPT12E_PISEL_IST3IN_Msk (0xcUL)
7853 #define GPT12E_PISEL_IST3EUD_Pos (4UL)
7854 #define GPT12E_PISEL_IST3EUD_Msk (0x30UL)
7855 #define GPT12E_PISEL_IST4IN_Pos (6UL)
7856 #define GPT12E_PISEL_IST4IN_Msk (0xc0UL)
7857 #define GPT12E_PISEL_IST4EUD_Pos (8UL)
7858 #define GPT12E_PISEL_IST4EUD_Msk (0x300UL)
7859 #define GPT12E_PISEL_IST5IN_Pos (10UL)
7860 #define GPT12E_PISEL_IST5IN_Msk (0x400UL)
7861 #define GPT12E_PISEL_IST5EUD_Pos (11UL)
7862 #define GPT12E_PISEL_IST5EUD_Msk (0x800UL)
7863 #define GPT12E_PISEL_IST6IN_Pos (12UL)
7864 #define GPT12E_PISEL_IST6IN_Msk (0x1000UL)
7865 #define GPT12E_PISEL_IST6EUD_Pos (13UL)
7866 #define GPT12E_PISEL_IST6EUD_Msk (0x2000UL)
7867 #define GPT12E_PISEL_ISCAPIN_Pos (14UL)
7868 #define GPT12E_PISEL_ISCAPIN_Msk (0xc000UL)
7869 /* ========================================================== T2 =========================================================== */
7870 #define GPT12E_T2_T2_Pos (0UL)
7871 #define GPT12E_T2_T2_Msk (0xffffUL)
7872 /* ========================================================= T2CON ========================================================= */
7873 #define GPT12E_T2CON_T2I_Pos (0UL)
7874 #define GPT12E_T2CON_T2I_Msk (0x7UL)
7875 #define GPT12E_T2CON_T2M_Pos (3UL)
7876 #define GPT12E_T2CON_T2M_Msk (0x38UL)
7877 #define GPT12E_T2CON_T2R_Pos (6UL)
7878 #define GPT12E_T2CON_T2R_Msk (0x40UL)
7879 #define GPT12E_T2CON_T2UD_Pos (7UL)
7880 #define GPT12E_T2CON_T2UD_Msk (0x80UL)
7881 #define GPT12E_T2CON_T2UDE_Pos (8UL)
7882 #define GPT12E_T2CON_T2UDE_Msk (0x100UL)
7883 #define GPT12E_T2CON_T2RC_Pos (9UL)
7884 #define GPT12E_T2CON_T2RC_Msk (0x200UL)
7885 #define GPT12E_T2CON_T2IRDIS_Pos (12UL)
7886 #define GPT12E_T2CON_T2IRDIS_Msk (0x1000UL)
7887 #define GPT12E_T2CON_T2EDGE_Pos (13UL)
7888 #define GPT12E_T2CON_T2EDGE_Msk (0x2000UL)
7889 #define GPT12E_T2CON_T2CHDIR_Pos (14UL)
7890 #define GPT12E_T2CON_T2CHDIR_Msk (0x4000UL)
7891 #define GPT12E_T2CON_T2RDIR_Pos (15UL)
7892 #define GPT12E_T2CON_T2RDIR_Msk (0x8000UL)
7893 /* ========================================================== T3 =========================================================== */
7894 #define GPT12E_T3_T3_Pos (0UL)
7895 #define GPT12E_T3_T3_Msk (0xffffUL)
7896 /* ========================================================= T3CON ========================================================= */
7897 #define GPT12E_T3CON_T3I_Pos (0UL)
7898 #define GPT12E_T3CON_T3I_Msk (0x7UL)
7899 #define GPT12E_T3CON_T3M_Pos (3UL)
7900 #define GPT12E_T3CON_T3M_Msk (0x38UL)
7901 #define GPT12E_T3CON_T3R_Pos (6UL)
7902 #define GPT12E_T3CON_T3R_Msk (0x40UL)
7903 #define GPT12E_T3CON_T3UD_Pos (7UL)
7904 #define GPT12E_T3CON_T3UD_Msk (0x80UL)
7905 #define GPT12E_T3CON_T3UDE_Pos (8UL)
7906 #define GPT12E_T3CON_T3UDE_Msk (0x100UL)
7907 #define GPT12E_T3CON_T3OE_Pos (9UL)
7908 #define GPT12E_T3CON_T3OE_Msk (0x200UL)
7909 #define GPT12E_T3CON_T3OTL_Pos (10UL)
7910 #define GPT12E_T3CON_T3OTL_Msk (0x400UL)
7911 #define GPT12E_T3CON_BPS1_Pos (11UL)
7912 #define GPT12E_T3CON_BPS1_Msk (0x1800UL)
7913 #define GPT12E_T3CON_T3EDGE_Pos (13UL)
7914 #define GPT12E_T3CON_T3EDGE_Msk (0x2000UL)
7915 #define GPT12E_T3CON_T3CHDIR_Pos (14UL)
7916 #define GPT12E_T3CON_T3CHDIR_Msk (0x4000UL)
7917 #define GPT12E_T3CON_T3RDIR_Pos (15UL)
7918 #define GPT12E_T3CON_T3RDIR_Msk (0x8000UL)
7919 /* ========================================================== T4 =========================================================== */
7920 #define GPT12E_T4_T4_Pos (0UL)
7921 #define GPT12E_T4_T4_Msk (0xffffUL)
7922 /* ========================================================= T4CON ========================================================= */
7923 #define GPT12E_T4CON_T4I_Pos (0UL)
7924 #define GPT12E_T4CON_T4I_Msk (0x7UL)
7925 #define GPT12E_T4CON_T4M_Pos (3UL)
7926 #define GPT12E_T4CON_T4M_Msk (0x38UL)
7927 #define GPT12E_T4CON_T4R_Pos (6UL)
7928 #define GPT12E_T4CON_T4R_Msk (0x40UL)
7929 #define GPT12E_T4CON_T4UD_Pos (7UL)
7930 #define GPT12E_T4CON_T4UD_Msk (0x80UL)
7931 #define GPT12E_T4CON_T4UDE_Pos (8UL)
7932 #define GPT12E_T4CON_T4UDE_Msk (0x100UL)
7933 #define GPT12E_T4CON_T4RC_Pos (9UL)
7934 #define GPT12E_T4CON_T4RC_Msk (0x200UL)
7935 #define GPT12E_T4CON_CLRT2EN_Pos (10UL)
7936 #define GPT12E_T4CON_CLRT2EN_Msk (0x400UL)
7937 #define GPT12E_T4CON_CLRT3EN_Pos (11UL)
7938 #define GPT12E_T4CON_CLRT3EN_Msk (0x800UL)
7939 #define GPT12E_T4CON_T4IRDIS_Pos (12UL)
7940 #define GPT12E_T4CON_T4IRDIS_Msk (0x1000UL)
7941 #define GPT12E_T4CON_T4EDGE_Pos (13UL)
7942 #define GPT12E_T4CON_T4EDGE_Msk (0x2000UL)
7943 #define GPT12E_T4CON_T4CHDIR_Pos (14UL)
7944 #define GPT12E_T4CON_T4CHDIR_Msk (0x4000UL)
7945 #define GPT12E_T4CON_T4RDIR_Pos (15UL)
7946 #define GPT12E_T4CON_T4RDIR_Msk (0x8000UL)
7947 /* ========================================================== T5 =========================================================== */
7948 #define GPT12E_T5_T5_Pos (0UL)
7949 #define GPT12E_T5_T5_Msk (0xffffUL)
7950 /* ========================================================= T5CON ========================================================= */
7951 #define GPT12E_T5CON_T5I_Pos (0UL)
7952 #define GPT12E_T5CON_T5I_Msk (0x7UL)
7953 #define GPT12E_T5CON_T5M_Pos (3UL)
7954 #define GPT12E_T5CON_T5M_Msk (0x18UL)
7955 #define GPT12E_T5CON_T5R_Pos (6UL)
7956 #define GPT12E_T5CON_T5R_Msk (0x40UL)
7957 #define GPT12E_T5CON_T5UD_Pos (7UL)
7958 #define GPT12E_T5CON_T5UD_Msk (0x80UL)
7959 #define GPT12E_T5CON_T5UDE_Pos (8UL)
7960 #define GPT12E_T5CON_T5UDE_Msk (0x100UL)
7961 #define GPT12E_T5CON_T5RC_Pos (9UL)
7962 #define GPT12E_T5CON_T5RC_Msk (0x200UL)
7963 #define GPT12E_T5CON_CT3_Pos (10UL)
7964 #define GPT12E_T5CON_CT3_Msk (0x400UL)
7965 #define GPT12E_T5CON_CI_Pos (12UL)
7966 #define GPT12E_T5CON_CI_Msk (0x3000UL)
7967 #define GPT12E_T5CON_T5CLR_Pos (14UL)
7968 #define GPT12E_T5CON_T5CLR_Msk (0x4000UL)
7969 #define GPT12E_T5CON_T5SC_Pos (15UL)
7970 #define GPT12E_T5CON_T5SC_Msk (0x8000UL)
7971 /* ========================================================== T6 =========================================================== */
7972 #define GPT12E_T6_T6_Pos (0UL)
7973 #define GPT12E_T6_T6_Msk (0xffffUL)
7974 /* ========================================================= T6CON ========================================================= */
7975 #define GPT12E_T6CON_T6I_Pos (0UL)
7976 #define GPT12E_T6CON_T6I_Msk (0x7UL)
7977 #define GPT12E_T6CON_T6M_Pos (3UL)
7978 #define GPT12E_T6CON_T6M_Msk (0x38UL)
7979 #define GPT12E_T6CON_T6R_Pos (6UL)
7980 #define GPT12E_T6CON_T6R_Msk (0x40UL)
7981 #define GPT12E_T6CON_T6UD_Pos (7UL)
7982 #define GPT12E_T6CON_T6UD_Msk (0x80UL)
7983 #define GPT12E_T6CON_T6UDE_Pos (8UL)
7984 #define GPT12E_T6CON_T6UDE_Msk (0x100UL)
7985 #define GPT12E_T6CON_T6OE_Pos (9UL)
7986 #define GPT12E_T6CON_T6OE_Msk (0x200UL)
7987 #define GPT12E_T6CON_T6OTL_Pos (10UL)
7988 #define GPT12E_T6CON_T6OTL_Msk (0x400UL)
7989 #define GPT12E_T6CON_BPS2_Pos (11UL)
7990 #define GPT12E_T6CON_BPS2_Msk (0x1800UL)
7991 #define GPT12E_T6CON_T6CLR_Pos (14UL)
7992 #define GPT12E_T6CON_T6CLR_Msk (0x4000UL)
7993 #define GPT12E_T6CON_T6SR_Pos (15UL)
7994 #define GPT12E_T6CON_T6SR_Msk (0x8000UL)
7997 /* =========================================================================================================================== */
7998 /* ================ LIN ================ */
7999 /* =========================================================================================================================== */
8000 
8001 /* ======================================================= CTRL_STS ======================================================== */
8002 #define LIN_CTRL_STS_M_SM_ERR_CLR_Pos (24UL)
8003 #define LIN_CTRL_STS_M_SM_ERR_CLR_Msk (0x1000000UL)
8004 #define LIN_CTRL_STS_HV_MODE_Pos (21UL)
8005 #define LIN_CTRL_STS_HV_MODE_Msk (0x200000UL)
8006 #define LIN_CTRL_STS_MODE_FB_Pos (16UL)
8007 #define LIN_CTRL_STS_MODE_FB_Msk (0x70000UL)
8008 #define LIN_CTRL_STS_FB_SM3_Pos (15UL)
8009 #define LIN_CTRL_STS_FB_SM3_Msk (0x8000UL)
8010 #define LIN_CTRL_STS_FB_SM2_Pos (14UL)
8011 #define LIN_CTRL_STS_FB_SM2_Msk (0x4000UL)
8012 #define LIN_CTRL_STS_FB_SM1_Pos (13UL)
8013 #define LIN_CTRL_STS_FB_SM1_Msk (0x2000UL)
8014 #define LIN_CTRL_STS_SM_Pos (11UL)
8015 #define LIN_CTRL_STS_SM_Msk (0x1800UL)
8016 #define LIN_CTRL_STS_RXD_Pos (10UL)
8017 #define LIN_CTRL_STS_RXD_Msk (0x400UL)
8018 #define LIN_CTRL_STS_TXD_Pos (9UL)
8019 #define LIN_CTRL_STS_TXD_Msk (0x200UL)
8020 #define LIN_CTRL_STS_TXD_TMOUT_STS_Pos (6UL)
8021 #define LIN_CTRL_STS_TXD_TMOUT_STS_Msk (0x40UL)
8022 #define LIN_CTRL_STS_OC_STS_Pos (5UL)
8023 #define LIN_CTRL_STS_OC_STS_Msk (0x20UL)
8024 #define LIN_CTRL_STS_OT_STS_Pos (4UL)
8025 #define LIN_CTRL_STS_OT_STS_Msk (0x10UL)
8026 #define LIN_CTRL_STS_M_SM_ERR_Pos (3UL)
8027 #define LIN_CTRL_STS_M_SM_ERR_Msk (0x8UL)
8028 #define LIN_CTRL_STS_MODE_Pos (1UL)
8029 #define LIN_CTRL_STS_MODE_Msk (0x6UL)
8032 /* =========================================================================================================================== */
8033 /* ================ MF ================ */
8034 /* =========================================================================================================================== */
8035 
8036 /* ======================================================= CSA_CTRL ======================================================== */
8037 #define MF_CSA_CTRL_VZERO_Pos (8UL)
8038 #define MF_CSA_CTRL_VZERO_Msk (0x100UL)
8039 #define MF_CSA_CTRL_GAIN_Pos (1UL)
8040 #define MF_CSA_CTRL_GAIN_Msk (0x6UL)
8041 #define MF_CSA_CTRL_EN_Pos (0UL)
8042 #define MF_CSA_CTRL_EN_Msk (0x1UL)
8043 /* ==================================================== P2_ADCSEL_CTRL ===================================================== */
8044 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Pos (10UL)
8045 #define MF_P2_ADCSEL_CTRL_ADC1_CH1_SEL_Msk (0x400UL)
8046 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Pos (9UL)
8047 #define MF_P2_ADCSEL_CTRL_ADC3_INN_SEL_Msk (0x200UL)
8048 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Pos (8UL)
8049 #define MF_P2_ADCSEL_CTRL_ADC3_INP_SEL_Msk (0x100UL)
8050 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Pos (0UL)
8051 #define MF_P2_ADCSEL_CTRL_P2_0_ADC_SEL_Msk (0x1UL)
8052 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Pos (1UL)
8053 #define MF_P2_ADCSEL_CTRL_P2_2_ADC_SEL_Msk (0x2UL)
8054 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Pos (2UL)
8055 #define MF_P2_ADCSEL_CTRL_P2_3_ADC_SEL_Msk (0x4UL)
8056 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Pos (3UL)
8057 #define MF_P2_ADCSEL_CTRL_P2_4_ADC_SEL_Msk (0x8UL)
8058 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Pos (4UL)
8059 #define MF_P2_ADCSEL_CTRL_P2_5_ADC_SEL_Msk (0x10UL)
8060 #define MF_P2_ADCSEL_CTRL_P2_7_ADC_SEL_Pos (5UL)
8061 #define MF_P2_ADCSEL_CTRL_P2_7_ADC_SEL_Msk (0x20UL)
8062 /* ======================================================= REF1_STS ======================================================== */
8063 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Pos (5UL)
8064 #define MF_REF1_STS_REFBG_UPTHWARN_STS_Msk (0x20UL)
8065 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Pos (4UL)
8066 #define MF_REF1_STS_REFBG_LOTHWARN_STS_Msk (0x10UL)
8067 /* ======================================================= REF2_CTRL ======================================================= */
8068 #define MF_REF2_CTRL_VREF5V_OV_STS_Pos (3UL)
8069 #define MF_REF2_CTRL_VREF5V_OV_STS_Msk (0x8UL)
8070 #define MF_REF2_CTRL_VREF5V_UV_STS_Pos (2UL)
8071 #define MF_REF2_CTRL_VREF5V_UV_STS_Msk (0x4UL)
8072 #define MF_REF2_CTRL_VREF5V_OVL_STS_Pos (1UL)
8073 #define MF_REF2_CTRL_VREF5V_OVL_STS_Msk (0x2UL)
8074 #define MF_REF2_CTRL_VREF5V_PD_N_Pos (0UL)
8075 #define MF_REF2_CTRL_VREF5V_PD_N_Msk (0x1UL)
8076 /* ==================================================== TEMPSENSE_CTRL ===================================================== */
8077 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Pos (7UL)
8078 #define MF_TEMPSENSE_CTRL_SYS_OT_STS_Msk (0x80UL)
8079 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Pos (6UL)
8080 #define MF_TEMPSENSE_CTRL_SYS_OTWARN_STS_Msk (0x40UL)
8081 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Pos (5UL)
8082 #define MF_TEMPSENSE_CTRL_PMU_OT_STS_Msk (0x20UL)
8083 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Pos (4UL)
8084 #define MF_TEMPSENSE_CTRL_PMU_OTWARN_STS_Msk (0x10UL)
8085 /* ===================================================== VMON_SEN_CTRL ===================================================== */
8086 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos (5UL)
8087 #define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk (0x20UL)
8088 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos (4UL)
8089 #define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk (0x10UL)
8090 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos (0UL)
8091 #define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk (0x1UL)
8094 /* =========================================================================================================================== */
8095 /* ================ PMU ================ */
8096 /* =========================================================================================================================== */
8097 
8098 /* ================================================== CNF_CYC_SAMPLE_DEL =================================================== */
8099 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Pos (0UL)
8100 #define PMU_CNF_CYC_SAMPLE_DEL_M03_Msk (0xfUL)
8101 /* ===================================================== CNF_CYC_SENSE ===================================================== */
8102 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Pos (7UL)
8103 #define PMU_CNF_CYC_SENSE_OSC_100kHz_EN_Msk (0x80UL)
8104 #define PMU_CNF_CYC_SENSE_E01_Pos (4UL)
8105 #define PMU_CNF_CYC_SENSE_E01_Msk (0x30UL)
8106 #define PMU_CNF_CYC_SENSE_M03_Pos (0UL)
8107 #define PMU_CNF_CYC_SENSE_M03_Msk (0xfUL)
8108 /* ===================================================== CNF_CYC_WAKE ====================================================== */
8109 #define PMU_CNF_CYC_WAKE_E01_Pos (4UL)
8110 #define PMU_CNF_CYC_WAKE_E01_Msk (0x30UL)
8111 #define PMU_CNF_CYC_WAKE_M03_Pos (0UL)
8112 #define PMU_CNF_CYC_WAKE_M03_Msk (0xfUL)
8113 /* =================================================== CNF_PMU_SETTINGS ==================================================== */
8114 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Pos (7UL)
8115 #define PMU_CNF_PMU_SETTINGS_EN_VDDEXT_OC_OFF_N_Msk (0x80UL)
8116 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Pos (3UL)
8117 #define PMU_CNF_PMU_SETTINGS_CYC_SENSE_EN_Msk (0x8UL)
8118 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Pos (2UL)
8119 #define PMU_CNF_PMU_SETTINGS_CYC_WAKE_EN_Msk (0x4UL)
8120 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Pos (1UL)
8121 #define PMU_CNF_PMU_SETTINGS_EN_0V9_N_Msk (0x2UL)
8122 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Pos (0UL)
8123 #define PMU_CNF_PMU_SETTINGS_WAKE_W_RST_Msk (0x1UL)
8124 /* ====================================================== CNF_RST_TFB ====================================================== */
8125 #define PMU_CNF_RST_TFB_RST_TFB_Pos (0UL)
8126 #define PMU_CNF_RST_TFB_RST_TFB_Msk (0x3UL)
8127 /* ==================================================== CNF_WAKE_FILTER ==================================================== */
8128 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Pos (2UL)
8129 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Msk (0xcUL)
8130 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Pos (1UL)
8131 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Msk (0x2UL)
8132 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Pos (0UL)
8133 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Msk (0x1UL)
8134 /* ======================================================= GPUDATA00 ======================================================= */
8135 #define PMU_GPUDATA00_DATA0_Pos (0UL)
8136 #define PMU_GPUDATA00_DATA0_Msk (0xffUL)
8137 /* ======================================================= GPUDATA01 ======================================================= */
8138 #define PMU_GPUDATA01_DATA1_Pos (0UL)
8139 #define PMU_GPUDATA01_DATA1_Msk (0xffUL)
8140 /* ======================================================= GPUDATA02 ======================================================= */
8141 #define PMU_GPUDATA02_DATA2_Pos (0UL)
8142 #define PMU_GPUDATA02_DATA2_Msk (0xffUL)
8143 /* ======================================================= GPUDATA03 ======================================================= */
8144 #define PMU_GPUDATA03_DATA3_Pos (0UL)
8145 #define PMU_GPUDATA03_DATA3_Msk (0xffUL)
8146 /* ======================================================= GPUDATA04 ======================================================= */
8147 #define PMU_GPUDATA04_DATA4_Pos (0UL)
8148 #define PMU_GPUDATA04_DATA4_Msk (0xffUL)
8149 /* ======================================================= GPUDATA05 ======================================================= */
8150 #define PMU_GPUDATA05_DATA5_Pos (0UL)
8151 #define PMU_GPUDATA05_DATA5_Msk (0xffUL)
8152 /* ====================================================== LIN_WAKE_EN ====================================================== */
8153 #define PMU_LIN_WAKE_EN_LIN_EN_Pos (7UL)
8154 #define PMU_LIN_WAKE_EN_LIN_EN_Msk (0x80UL)
8155 /* ======================================================== MON_CNF ======================================================== */
8156 #define PMU_MON_CNF_STS_Pos (7UL)
8157 #define PMU_MON_CNF_STS_Msk (0x80UL)
8158 #define PMU_MON_CNF_PU_Pos (5UL)
8159 #define PMU_MON_CNF_PU_Msk (0x20UL)
8160 #define PMU_MON_CNF_PD_Pos (4UL)
8161 #define PMU_MON_CNF_PD_Msk (0x10UL)
8162 #define PMU_MON_CNF_CYC_Pos (3UL)
8163 #define PMU_MON_CNF_CYC_Msk (0x8UL)
8164 #define PMU_MON_CNF_RISE_Pos (2UL)
8165 #define PMU_MON_CNF_RISE_Msk (0x4UL)
8166 #define PMU_MON_CNF_FALL_Pos (1UL)
8167 #define PMU_MON_CNF_FALL_Msk (0x2UL)
8168 #define PMU_MON_CNF_EN_Pos (0UL)
8169 #define PMU_MON_CNF_EN_Msk (0x1UL)
8170 /* ==================================================== PMU_RESET_STS1 ===================================================== */
8171 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Pos (7UL)
8172 #define PMU_PMU_RESET_STS1_PMU_1V5DidPOR_Msk (0x80UL)
8173 #define PMU_PMU_RESET_STS1_PMU_PIN_Pos (6UL)
8174 #define PMU_PMU_RESET_STS1_PMU_PIN_Msk (0x40UL)
8175 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Pos (5UL)
8176 #define PMU_PMU_RESET_STS1_PMU_ExtWDT_Msk (0x20UL)
8177 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Pos (4UL)
8178 #define PMU_PMU_RESET_STS1_PMU_ClkWDT_Msk (0x10UL)
8179 #define PMU_PMU_RESET_STS1_PMU_LPR_Pos (3UL)
8180 #define PMU_PMU_RESET_STS1_PMU_LPR_Msk (0x8UL)
8181 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Pos (2UL)
8182 #define PMU_PMU_RESET_STS1_PMU_SleepEX_Msk (0x4UL)
8183 #define PMU_PMU_RESET_STS1_PMU_WAKE_Pos (1UL)
8184 #define PMU_PMU_RESET_STS1_PMU_WAKE_Msk (0x2UL)
8185 #define PMU_PMU_RESET_STS1_SYS_FAIL_Pos (0UL)
8186 #define PMU_PMU_RESET_STS1_SYS_FAIL_Msk (0x1UL)
8187 /* ==================================================== PMU_RESET_STS2 ===================================================== */
8188 #define PMU_PMU_RESET_STS2_LOCKUP_Pos (2UL)
8189 #define PMU_PMU_RESET_STS2_LOCKUP_Msk (0x4UL)
8190 #define PMU_PMU_RESET_STS2_PMU_SOFT_Pos (1UL)
8191 #define PMU_PMU_RESET_STS2_PMU_SOFT_Msk (0x2UL)
8192 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Pos (0UL)
8193 #define PMU_PMU_RESET_STS2_PMU_IntWDT_Msk (0x1UL)
8194 /* ==================================================== PMU_SUPPLY_STS ===================================================== */
8195 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos (6UL)
8196 #define PMU_PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk (0x40UL)
8197 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Pos (5UL)
8198 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Msk (0x20UL)
8199 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Pos (4UL)
8200 #define PMU_PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Msk (0x10UL)
8201 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos (2UL)
8202 #define PMU_PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk (0x4UL)
8203 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Pos (1UL)
8204 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Msk (0x2UL)
8205 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Pos (0UL)
8206 #define PMU_PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Msk (0x1UL)
8207 /* ===================================================== SYS_FAIL_STS ====================================================== */
8208 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Pos (6UL)
8209 #define PMU_SYS_FAIL_STS_WDT1_SEQ_FAIL_Msk (0x40UL)
8210 #define PMU_SYS_FAIL_STS_SYS_OT_Pos (5UL)
8211 #define PMU_SYS_FAIL_STS_SYS_OT_Msk (0x20UL)
8212 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Pos (3UL)
8213 #define PMU_SYS_FAIL_STS_PMU_5V_OVL_Msk (0x8UL)
8214 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Pos (2UL)
8215 #define PMU_SYS_FAIL_STS_PMU_1V5_OVL_Msk (0x4UL)
8216 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Pos (1UL)
8217 #define PMU_SYS_FAIL_STS_SUPP_TMOUT_Msk (0x2UL)
8218 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Pos (0UL)
8219 #define PMU_SYS_FAIL_STS_SUPP_SHORT_Msk (0x1UL)
8220 /* =================================================== SystemStartConfig =================================================== */
8221 #define PMU_SystemStartConfig_MBIST_EN_Pos (0UL)
8222 #define PMU_SystemStartConfig_MBIST_EN_Msk (0x1UL)
8223 /* ====================================================== VDDEXT_CTRL ====================================================== */
8224 #define PMU_VDDEXT_CTRL_STABLE_Pos (7UL)
8225 #define PMU_VDDEXT_CTRL_STABLE_Msk (0x80UL)
8226 #define PMU_VDDEXT_CTRL_OK_Pos (6UL)
8227 #define PMU_VDDEXT_CTRL_OK_Msk (0x40UL)
8228 #define PMU_VDDEXT_CTRL_OVERLOAD_Pos (5UL)
8229 #define PMU_VDDEXT_CTRL_OVERLOAD_Msk (0x20UL)
8230 #define PMU_VDDEXT_CTRL_OVERVOLT_Pos (4UL)
8231 #define PMU_VDDEXT_CTRL_OVERVOLT_Msk (0x10UL)
8232 #define PMU_VDDEXT_CTRL_SHORT_Pos (3UL)
8233 #define PMU_VDDEXT_CTRL_SHORT_Msk (0x8UL)
8234 #define PMU_VDDEXT_CTRL_FAIL_EN_Pos (2UL)
8235 #define PMU_VDDEXT_CTRL_FAIL_EN_Msk (0x4UL)
8236 #define PMU_VDDEXT_CTRL_CYC_EN_Pos (1UL)
8237 #define PMU_VDDEXT_CTRL_CYC_EN_Msk (0x2UL)
8238 #define PMU_VDDEXT_CTRL_ENABLE_Pos (0UL)
8239 #define PMU_VDDEXT_CTRL_ENABLE_Msk (0x1UL)
8240 /* ================================================== WAKE_CONF_GPIO0_CYC ================================================== */
8241 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Pos (4UL)
8242 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_4_Msk (0x10UL)
8243 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Pos (3UL)
8244 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_3_Msk (0x8UL)
8245 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Pos (2UL)
8246 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_2_Msk (0x4UL)
8247 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Pos (1UL)
8248 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_1_Msk (0x2UL)
8249 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Pos (0UL)
8250 #define PMU_WAKE_CONF_GPIO0_CYC_GPIO0_CYC_0_Msk (0x1UL)
8251 /* ================================================= WAKE_CONF_GPIO0_FALL ================================================== */
8252 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Pos (4UL)
8253 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_4_Msk (0x10UL)
8254 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Pos (3UL)
8255 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_3_Msk (0x8UL)
8256 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Pos (2UL)
8257 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_2_Msk (0x4UL)
8258 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Pos (1UL)
8259 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_1_Msk (0x2UL)
8260 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Pos (0UL)
8261 #define PMU_WAKE_CONF_GPIO0_FALL_GPIO0_FA_0_Msk (0x1UL)
8262 /* ================================================= WAKE_CONF_GPIO0_RISE ================================================== */
8263 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Pos (4UL)
8264 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_4_Msk (0x10UL)
8265 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Pos (3UL)
8266 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_3_Msk (0x8UL)
8267 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Pos (2UL)
8268 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_2_Msk (0x4UL)
8269 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Pos (1UL)
8270 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_1_Msk (0x2UL)
8271 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Pos (0UL)
8272 #define PMU_WAKE_CONF_GPIO0_RISE_GPIO0_RI_0_Msk (0x1UL)
8273 /* ================================================== WAKE_CONF_GPIO1_CYC ================================================== */
8274 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Pos (4UL)
8275 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_4_Msk (0x10UL)
8276 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Pos (3UL)
8277 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_3_Msk (0x8UL)
8278 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Pos (2UL)
8279 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_2_Msk (0x4UL)
8280 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Pos (1UL)
8281 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_1_Msk (0x2UL)
8282 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Pos (0UL)
8283 #define PMU_WAKE_CONF_GPIO1_CYC_GPIO1_CYC_0_Msk (0x1UL)
8284 /* ================================================= WAKE_CONF_GPIO1_FALL ================================================== */
8285 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Pos (4UL)
8286 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_4_Msk (0x10UL)
8287 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Pos (3UL)
8288 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_3_Msk (0x8UL)
8289 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Pos (2UL)
8290 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_2_Msk (0x4UL)
8291 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Pos (1UL)
8292 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_1_Msk (0x2UL)
8293 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Pos (0UL)
8294 #define PMU_WAKE_CONF_GPIO1_FALL_GPIO1_FA_0_Msk (0x1UL)
8295 /* ================================================= WAKE_CONF_GPIO1_RISE ================================================== */
8296 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Pos (4UL)
8297 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_4_Msk (0x10UL)
8298 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Pos (3UL)
8299 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_3_Msk (0x8UL)
8300 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Pos (2UL)
8301 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_2_Msk (0x4UL)
8302 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Pos (1UL)
8303 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_1_Msk (0x2UL)
8304 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Pos (0UL)
8305 #define PMU_WAKE_CONF_GPIO1_RISE_GPIO1_RI_0_Msk (0x1UL)
8306 /* ====================================================== WAKE_STATUS ====================================================== */
8307 #define PMU_WAKE_STATUS_FAIL_Pos (5UL)
8308 #define PMU_WAKE_STATUS_FAIL_Msk (0x20UL)
8309 #define PMU_WAKE_STATUS_CYC_WAKE_Pos (4UL)
8310 #define PMU_WAKE_STATUS_CYC_WAKE_Msk (0x10UL)
8311 #define PMU_WAKE_STATUS_GPIO1_Pos (3UL)
8312 #define PMU_WAKE_STATUS_GPIO1_Msk (0x8UL)
8313 #define PMU_WAKE_STATUS_GPIO0_Pos (2UL)
8314 #define PMU_WAKE_STATUS_GPIO0_Msk (0x4UL)
8315 #define PMU_WAKE_STATUS_MON_WAKE_Pos (1UL)
8316 #define PMU_WAKE_STATUS_MON_WAKE_Msk (0x2UL)
8317 #define PMU_WAKE_STATUS_LIN_WAKE_Pos (0UL)
8318 #define PMU_WAKE_STATUS_LIN_WAKE_Msk (0x1UL)
8319 /* ===================================================== WAKE_STS_FAIL ===================================================== */
8320 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Pos (2UL)
8321 #define PMU_WAKE_STS_FAIL_VDDEXTSHORT_Msk (0x4UL)
8322 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Pos (0UL)
8323 #define PMU_WAKE_STS_FAIL_SUPPFAIL_Msk (0x1UL)
8324 /* ==================================================== WAKE_STS_GPIO0 ===================================================== */
8325 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Pos (4UL)
8326 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_4_Msk (0x10UL)
8327 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Pos (3UL)
8328 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_3_Msk (0x8UL)
8329 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Pos (2UL)
8330 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_2_Msk (0x4UL)
8331 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Pos (1UL)
8332 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_1_Msk (0x2UL)
8333 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Pos (0UL)
8334 #define PMU_WAKE_STS_GPIO0_GPIO0_STS_0_Msk (0x1UL)
8335 /* ==================================================== WAKE_STS_GPIO1 ===================================================== */
8336 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Pos (4UL)
8337 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_4_Msk (0x10UL)
8338 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Pos (3UL)
8339 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_3_Msk (0x8UL)
8340 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Pos (2UL)
8341 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_2_Msk (0x4UL)
8342 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Pos (1UL)
8343 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_1_Msk (0x2UL)
8344 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Pos (0UL)
8345 #define PMU_WAKE_STS_GPIO1_GPIO1_STS_0_Msk (0x1UL)
8346 /* ===================================================== WAKE_STS_MON ====================================================== */
8347 #define PMU_WAKE_STS_MON_WAKE_STS_Pos (0UL)
8348 #define PMU_WAKE_STS_MON_WAKE_STS_Msk (0x1UL)
8351 /* =========================================================================================================================== */
8352 /* ================ PORT ================ */
8353 /* =========================================================================================================================== */
8354 
8355 /* ====================================================== P0_ALTSEL0 ======================================================= */
8356 #define PORT_P0_ALTSEL0_P0_Pos (0UL)
8357 #define PORT_P0_ALTSEL0_P0_Msk (0x1UL)
8358 #define PORT_P0_ALTSEL0_P1_Pos (1UL)
8359 #define PORT_P0_ALTSEL0_P1_Msk (0x2UL)
8360 #define PORT_P0_ALTSEL0_P2_Pos (2UL)
8361 #define PORT_P0_ALTSEL0_P2_Msk (0x4UL)
8362 #define PORT_P0_ALTSEL0_P3_Pos (3UL)
8363 #define PORT_P0_ALTSEL0_P3_Msk (0x8UL)
8364 #define PORT_P0_ALTSEL0_P4_Pos (4UL)
8365 #define PORT_P0_ALTSEL0_P4_Msk (0x10UL)
8366 /* ====================================================== P0_ALTSEL1 ======================================================= */
8367 #define PORT_P0_ALTSEL1_P0_Pos (0UL)
8368 #define PORT_P0_ALTSEL1_P0_Msk (0x1UL)
8369 #define PORT_P0_ALTSEL1_P1_Pos (1UL)
8370 #define PORT_P0_ALTSEL1_P1_Msk (0x2UL)
8371 #define PORT_P0_ALTSEL1_P2_Pos (2UL)
8372 #define PORT_P0_ALTSEL1_P2_Msk (0x4UL)
8373 #define PORT_P0_ALTSEL1_P3_Pos (3UL)
8374 #define PORT_P0_ALTSEL1_P3_Msk (0x8UL)
8375 #define PORT_P0_ALTSEL1_P4_Pos (4UL)
8376 #define PORT_P0_ALTSEL1_P4_Msk (0x10UL)
8377 /* ======================================================== P0_DATA ======================================================== */
8378 #define PORT_P0_DATA_P0_Pos (0UL)
8379 #define PORT_P0_DATA_P0_Msk (0x1UL)
8380 #define PORT_P0_DATA_P1_Pos (1UL)
8381 #define PORT_P0_DATA_P1_Msk (0x2UL)
8382 #define PORT_P0_DATA_P2_Pos (2UL)
8383 #define PORT_P0_DATA_P2_Msk (0x4UL)
8384 #define PORT_P0_DATA_P3_Pos (3UL)
8385 #define PORT_P0_DATA_P3_Msk (0x8UL)
8386 #define PORT_P0_DATA_P4_Pos (4UL)
8387 #define PORT_P0_DATA_P4_Msk (0x10UL)
8388 /* ======================================================== P0_DIR ========================================================= */
8389 #define PORT_P0_DIR_P0_Pos (0UL)
8390 #define PORT_P0_DIR_P0_Msk (0x1UL)
8391 #define PORT_P0_DIR_P1_Pos (1UL)
8392 #define PORT_P0_DIR_P1_Msk (0x2UL)
8393 #define PORT_P0_DIR_P2_Pos (2UL)
8394 #define PORT_P0_DIR_P2_Msk (0x4UL)
8395 #define PORT_P0_DIR_P3_Pos (3UL)
8396 #define PORT_P0_DIR_P3_Msk (0x8UL)
8397 #define PORT_P0_DIR_P4_Pos (4UL)
8398 #define PORT_P0_DIR_P4_Msk (0x10UL)
8399 /* ========================================================= P0_OD ========================================================= */
8400 #define PORT_P0_OD_P0_Pos (0UL)
8401 #define PORT_P0_OD_P0_Msk (0x1UL)
8402 #define PORT_P0_OD_P1_Pos (1UL)
8403 #define PORT_P0_OD_P1_Msk (0x2UL)
8404 #define PORT_P0_OD_P2_Pos (2UL)
8405 #define PORT_P0_OD_P2_Msk (0x4UL)
8406 #define PORT_P0_OD_P3_Pos (3UL)
8407 #define PORT_P0_OD_P3_Msk (0x8UL)
8408 #define PORT_P0_OD_P4_Pos (4UL)
8409 #define PORT_P0_OD_P4_Msk (0x10UL)
8410 /* ======================================================= P0_PUDEN ======================================================== */
8411 #define PORT_P0_PUDEN_P0_Pos (0UL)
8412 #define PORT_P0_PUDEN_P0_Msk (0x1UL)
8413 #define PORT_P0_PUDEN_P1_Pos (1UL)
8414 #define PORT_P0_PUDEN_P1_Msk (0x2UL)
8415 #define PORT_P0_PUDEN_P2_Pos (2UL)
8416 #define PORT_P0_PUDEN_P2_Msk (0x4UL)
8417 #define PORT_P0_PUDEN_P3_Pos (3UL)
8418 #define PORT_P0_PUDEN_P3_Msk (0x8UL)
8419 #define PORT_P0_PUDEN_P4_Pos (4UL)
8420 #define PORT_P0_PUDEN_P4_Msk (0x10UL)
8421 /* ======================================================= P0_PUDSEL ======================================================= */
8422 #define PORT_P0_PUDSEL_P0_Pos (0UL)
8423 #define PORT_P0_PUDSEL_P0_Msk (0x1UL)
8424 #define PORT_P0_PUDSEL_P1_Pos (1UL)
8425 #define PORT_P0_PUDSEL_P1_Msk (0x2UL)
8426 #define PORT_P0_PUDSEL_P2_Pos (2UL)
8427 #define PORT_P0_PUDSEL_P2_Msk (0x4UL)
8428 #define PORT_P0_PUDSEL_P3_Pos (3UL)
8429 #define PORT_P0_PUDSEL_P3_Msk (0x8UL)
8430 #define PORT_P0_PUDSEL_P4_Pos (4UL)
8431 #define PORT_P0_PUDSEL_P4_Msk (0x10UL)
8432 /* ====================================================== P1_ALTSEL0 ======================================================= */
8433 #define PORT_P1_ALTSEL0_P0_Pos (0UL)
8434 #define PORT_P1_ALTSEL0_P0_Msk (0x1UL)
8435 #define PORT_P1_ALTSEL0_P1_Pos (1UL)
8436 #define PORT_P1_ALTSEL0_P1_Msk (0x2UL)
8437 #define PORT_P1_ALTSEL0_P2_Pos (2UL)
8438 #define PORT_P1_ALTSEL0_P2_Msk (0x4UL)
8439 #define PORT_P1_ALTSEL0_P3_Pos (3UL)
8440 #define PORT_P1_ALTSEL0_P3_Msk (0x8UL)
8441 #define PORT_P1_ALTSEL0_P4_Pos (4UL)
8442 #define PORT_P1_ALTSEL0_P4_Msk (0x10UL)
8443 /* ====================================================== P1_ALTSEL1 ======================================================= */
8444 #define PORT_P1_ALTSEL1_P0_Pos (0UL)
8445 #define PORT_P1_ALTSEL1_P0_Msk (0x1UL)
8446 #define PORT_P1_ALTSEL1_P1_Pos (1UL)
8447 #define PORT_P1_ALTSEL1_P1_Msk (0x2UL)
8448 #define PORT_P1_ALTSEL1_P2_Pos (2UL)
8449 #define PORT_P1_ALTSEL1_P2_Msk (0x4UL)
8450 #define PORT_P1_ALTSEL1_P3_Pos (3UL)
8451 #define PORT_P1_ALTSEL1_P3_Msk (0x8UL)
8452 #define PORT_P1_ALTSEL1_P4_Pos (4UL)
8453 #define PORT_P1_ALTSEL1_P4_Msk (0x10UL)
8454 /* ======================================================== P1_DATA ======================================================== */
8455 #define PORT_P1_DATA_P0_Pos (0UL)
8456 #define PORT_P1_DATA_P0_Msk (0x1UL)
8457 #define PORT_P1_DATA_P1_Pos (1UL)
8458 #define PORT_P1_DATA_P1_Msk (0x2UL)
8459 #define PORT_P1_DATA_P2_Pos (2UL)
8460 #define PORT_P1_DATA_P2_Msk (0x4UL)
8461 #define PORT_P1_DATA_P3_Pos (3UL)
8462 #define PORT_P1_DATA_P3_Msk (0x8UL)
8463 #define PORT_P1_DATA_P4_Pos (4UL)
8464 #define PORT_P1_DATA_P4_Msk (0x10UL)
8465 /* ======================================================== P1_DIR ========================================================= */
8466 #define PORT_P1_DIR_P0_Pos (0UL)
8467 #define PORT_P1_DIR_P0_Msk (0x1UL)
8468 #define PORT_P1_DIR_P1_Pos (1UL)
8469 #define PORT_P1_DIR_P1_Msk (0x2UL)
8470 #define PORT_P1_DIR_P2_Pos (2UL)
8471 #define PORT_P1_DIR_P2_Msk (0x4UL)
8472 #define PORT_P1_DIR_P3_Pos (3UL)
8473 #define PORT_P1_DIR_P3_Msk (0x8UL)
8474 #define PORT_P1_DIR_P4_Pos (4UL)
8475 #define PORT_P1_DIR_P4_Msk (0x10UL)
8476 /* ========================================================= P1_OD ========================================================= */
8477 #define PORT_P1_OD_P0_Pos (1UL)
8478 #define PORT_P1_OD_P0_Msk (0x2UL)
8479 #define PORT_P1_OD_P1_Pos (2UL)
8480 #define PORT_P1_OD_P1_Msk (0x4UL)
8481 #define PORT_P1_OD_P3_P2_Pos (3UL)
8482 #define PORT_P1_OD_P3_P2_Msk (0x8UL)
8483 #define PORT_P1_OD_P4_Pos (4UL)
8484 #define PORT_P1_OD_P4_Msk (0x10UL)
8485 /* ======================================================= P1_PUDEN ======================================================== */
8486 #define PORT_P1_PUDEN_P0_Pos (0UL)
8487 #define PORT_P1_PUDEN_P0_Msk (0x1UL)
8488 #define PORT_P1_PUDEN_P1_Pos (1UL)
8489 #define PORT_P1_PUDEN_P1_Msk (0x2UL)
8490 #define PORT_P1_PUDEN_P2_Pos (2UL)
8491 #define PORT_P1_PUDEN_P2_Msk (0x4UL)
8492 #define PORT_P1_PUDEN_P3_Pos (3UL)
8493 #define PORT_P1_PUDEN_P3_Msk (0x8UL)
8494 #define PORT_P1_PUDEN_P4_Pos (4UL)
8495 #define PORT_P1_PUDEN_P4_Msk (0x10UL)
8496 /* ======================================================= P1_PUDSEL ======================================================= */
8497 #define PORT_P1_PUDSEL_P0_Pos (0UL)
8498 #define PORT_P1_PUDSEL_P0_Msk (0x1UL)
8499 #define PORT_P1_PUDSEL_P1_Pos (1UL)
8500 #define PORT_P1_PUDSEL_P1_Msk (0x2UL)
8501 #define PORT_P1_PUDSEL_P2_Pos (2UL)
8502 #define PORT_P1_PUDSEL_P2_Msk (0x4UL)
8503 #define PORT_P1_PUDSEL_P3_Pos (3UL)
8504 #define PORT_P1_PUDSEL_P3_Msk (0x8UL)
8505 #define PORT_P1_PUDSEL_P4_Pos (4UL)
8506 #define PORT_P1_PUDSEL_P4_Msk (0x10UL)
8507 /* ======================================================== P2_DATA ======================================================== */
8508 #define PORT_P2_DATA_P0_Pos (0UL)
8509 #define PORT_P2_DATA_P0_Msk (0x1UL)
8510 #define PORT_P2_DATA_P1_Pos (1UL)
8511 #define PORT_P2_DATA_P1_Msk (0x2UL)
8512 #define PORT_P2_DATA_P2_Pos (2UL)
8513 #define PORT_P2_DATA_P2_Msk (0x4UL)
8514 #define PORT_P2_DATA_P3_Pos (3UL)
8515 #define PORT_P2_DATA_P3_Msk (0x8UL)
8516 #define PORT_P2_DATA_P4_Pos (4UL)
8517 #define PORT_P2_DATA_P4_Msk (0x10UL)
8518 #define PORT_P2_DATA_P5_Pos (5UL)
8519 #define PORT_P2_DATA_P5_Msk (0x20UL)
8520 /* ======================================================== P2_DIR ========================================================= */
8521 #define PORT_P2_DIR_P0_Pos (0UL)
8522 #define PORT_P2_DIR_P0_Msk (0x1UL)
8523 #define PORT_P2_DIR_P1_Pos (1UL)
8524 #define PORT_P2_DIR_P1_Msk (0x2UL)
8525 #define PORT_P2_DIR_P2_Pos (2UL)
8526 #define PORT_P2_DIR_P2_Msk (0x4UL)
8527 #define PORT_P2_DIR_P3_Pos (3UL)
8528 #define PORT_P2_DIR_P3_Msk (0x8UL)
8529 #define PORT_P2_DIR_P4_Pos (4UL)
8530 #define PORT_P2_DIR_P4_Msk (0x10UL)
8531 #define PORT_P2_DIR_P5_Pos (5UL)
8532 #define PORT_P2_DIR_P5_Msk (0x20UL)
8533 /* ======================================================= P2_PUDEN ======================================================== */
8534 #define PORT_P2_PUDEN_P0_Pos (0UL)
8535 #define PORT_P2_PUDEN_P0_Msk (0x1UL)
8536 #define PORT_P2_PUDEN_P1_Pos (1UL)
8537 #define PORT_P2_PUDEN_P1_Msk (0x2UL)
8538 #define PORT_P2_PUDEN_P2_Pos (2UL)
8539 #define PORT_P2_PUDEN_P2_Msk (0x4UL)
8540 #define PORT_P2_PUDEN_P3_Pos (3UL)
8541 #define PORT_P2_PUDEN_P3_Msk (0x8UL)
8542 #define PORT_P2_PUDEN_P4_Pos (4UL)
8543 #define PORT_P2_PUDEN_P4_Msk (0x10UL)
8544 #define PORT_P2_PUDEN_P5_Pos (5UL)
8545 #define PORT_P2_PUDEN_P5_Msk (0x20UL)
8546 /* ======================================================= P2_PUDSEL ======================================================= */
8547 #define PORT_P2_PUDSEL_P0_Pos (0UL)
8548 #define PORT_P2_PUDSEL_P0_Msk (0x1UL)
8549 #define PORT_P2_PUDSEL_P1_Pos (1UL)
8550 #define PORT_P2_PUDSEL_P1_Msk (0x2UL)
8551 #define PORT_P2_PUDSEL_P2_Pos (2UL)
8552 #define PORT_P2_PUDSEL_P2_Msk (0x4UL)
8553 #define PORT_P2_PUDSEL_P3_Pos (3UL)
8554 #define PORT_P2_PUDSEL_P3_Msk (0x8UL)
8555 #define PORT_P2_PUDSEL_P4_Pos (4UL)
8556 #define PORT_P2_PUDSEL_P4_Msk (0x10UL)
8557 #define PORT_P2_PUDSEL_P5_Pos (5UL)
8558 #define PORT_P2_PUDSEL_P5_Msk (0x20UL)
8561 /* =========================================================================================================================== */
8562 /* ================ SCU ================ */
8563 /* =========================================================================================================================== */
8564 
8565 /* ======================================================== APCLK1 ========================================================= */
8566 #define SCU_APCLK1_APCLK3SCLR_Pos (7UL)
8567 #define SCU_APCLK1_APCLK3SCLR_Msk (0x80UL)
8568 #define SCU_APCLK1_APCLK3STS_Pos (6UL)
8569 #define SCU_APCLK1_APCLK3STS_Msk (0x40UL)
8570 #define SCU_APCLK1_APCLK1STS_Pos (4UL)
8571 #define SCU_APCLK1_APCLK1STS_Msk (0x30UL)
8572 #define SCU_APCLK1_APCLK1SCLR_Pos (2UL)
8573 #define SCU_APCLK1_APCLK1SCLR_Msk (0x4UL)
8574 #define SCU_APCLK1_APCLK1FAC_Pos (0UL)
8575 #define SCU_APCLK1_APCLK1FAC_Msk (0x3UL)
8576 /* ======================================================== APCLK2 ========================================================= */
8577 #define SCU_APCLK2_APCLK2SCLR_Pos (7UL)
8578 #define SCU_APCLK2_APCLK2SCLR_Msk (0x80UL)
8579 #define SCU_APCLK2_APCLK2STS_Pos (5UL)
8580 #define SCU_APCLK2_APCLK2STS_Msk (0x60UL)
8581 #define SCU_APCLK2_APCLK2FAC_Pos (0UL)
8582 #define SCU_APCLK2_APCLK2FAC_Msk (0x1fUL)
8583 /* ====================================================== APCLK_CTRL1 ====================================================== */
8584 #define SCU_APCLK_CTRL1_CPCLK_DIV_Pos (7UL)
8585 #define SCU_APCLK_CTRL1_CPCLK_DIV_Msk (0x80UL)
8586 #define SCU_APCLK_CTRL1_CPCLK_SEL_Pos (6UL)
8587 #define SCU_APCLK_CTRL1_CPCLK_SEL_Msk (0x40UL)
8588 #define SCU_APCLK_CTRL1_BGCLK_DIV_Pos (5UL)
8589 #define SCU_APCLK_CTRL1_BGCLK_DIV_Msk (0x20UL)
8590 #define SCU_APCLK_CTRL1_BGCLK_SEL_Pos (4UL)
8591 #define SCU_APCLK_CTRL1_BGCLK_SEL_Msk (0x10UL)
8592 #define SCU_APCLK_CTRL1_CLKWDT_IE_Pos (3UL)
8593 #define SCU_APCLK_CTRL1_CLKWDT_IE_Msk (0x8UL)
8594 #define SCU_APCLK_CTRL1_T3CLK_SEL_Pos (2UL)
8595 #define SCU_APCLK_CTRL1_T3CLK_SEL_Msk (0x4UL)
8596 #define SCU_APCLK_CTRL1_APCLK_SET_Pos (1UL)
8597 #define SCU_APCLK_CTRL1_APCLK_SET_Msk (0x2UL)
8598 #define SCU_APCLK_CTRL1_PLL_LOCK_Pos (0UL)
8599 #define SCU_APCLK_CTRL1_PLL_LOCK_Msk (0x1UL)
8600 /* ====================================================== APCLK_CTRL2 ====================================================== */
8601 #define SCU_APCLK_CTRL2_T3CLK_DIV_Pos (2UL)
8602 #define SCU_APCLK_CTRL2_T3CLK_DIV_Msk (0xcUL)
8603 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Pos (0UL)
8604 #define SCU_APCLK_CTRL2_SDADCCLK_DIV_Msk (0x3UL)
8605 /* ========================================================= BCON1 ========================================================= */
8606 #define SCU_BCON1_R_Pos (0UL)
8607 #define SCU_BCON1_R_Msk (0x1UL)
8608 #define SCU_BCON1_BRPRE_Pos (1UL)
8609 #define SCU_BCON1_BRPRE_Msk (0xeUL)
8610 /* ========================================================= BCON2 ========================================================= */
8611 #define SCU_BCON2_R_Pos (0UL)
8612 #define SCU_BCON2_R_Msk (0x1UL)
8613 #define SCU_BCON2_BRPRE_Pos (1UL)
8614 #define SCU_BCON2_BRPRE_Msk (0xeUL)
8615 /* ========================================================= BGH1 ========================================================== */
8616 #define SCU_BGH1_BR_VALUE_Pos (0UL)
8617 #define SCU_BGH1_BR_VALUE_Msk (0xffUL)
8618 /* ========================================================= BGH2 ========================================================== */
8619 #define SCU_BGH2_BR_VALUE_Pos (0UL)
8620 #define SCU_BGH2_BR_VALUE_Msk (0xffUL)
8621 /* ========================================================= BGL1 ========================================================== */
8622 #define SCU_BGL1_FD_SEL_Pos (0UL)
8623 #define SCU_BGL1_FD_SEL_Msk (0x1fUL)
8624 #define SCU_BGL1_BR_VALUE_Pos (5UL)
8625 #define SCU_BGL1_BR_VALUE_Msk (0xe0UL)
8626 /* ========================================================= BGL2 ========================================================== */
8627 #define SCU_BGL2_FD_SEL_Pos (0UL)
8628 #define SCU_BGL2_FD_SEL_Msk (0x1fUL)
8629 #define SCU_BGL2_BR_VALUE_Pos (5UL)
8630 #define SCU_BGL2_BR_VALUE_Msk (0xe0UL)
8631 /* ======================================================== CMCON1 ========================================================= */
8632 #define SCU_CMCON1_VCOSEL_Pos (7UL)
8633 #define SCU_CMCON1_VCOSEL_Msk (0x80UL)
8634 #define SCU_CMCON1_K1DIV_Pos (6UL)
8635 #define SCU_CMCON1_K1DIV_Msk (0x40UL)
8636 #define SCU_CMCON1_K2DIV_Pos (4UL)
8637 #define SCU_CMCON1_K2DIV_Msk (0x30UL)
8638 #define SCU_CMCON1_CLKREL_Pos (0UL)
8639 #define SCU_CMCON1_CLKREL_Msk (0xfUL)
8640 /* ======================================================== CMCON2 ========================================================= */
8641 #define SCU_CMCON2_PBA0CLKREL_Pos (0UL)
8642 #define SCU_CMCON2_PBA0CLKREL_Msk (0x1UL)
8643 /* ========================================================= COCON ========================================================= */
8644 #define SCU_COCON_EN_Pos (7UL)
8645 #define SCU_COCON_EN_Msk (0x80UL)
8646 #define SCU_COCON_COUTS1_Pos (6UL)
8647 #define SCU_COCON_COUTS1_Msk (0x40UL)
8648 #define SCU_COCON_TLEN_Pos (5UL)
8649 #define SCU_COCON_TLEN_Msk (0x20UL)
8650 #define SCU_COCON_COUTS0_Pos (4UL)
8651 #define SCU_COCON_COUTS0_Msk (0x10UL)
8652 #define SCU_COCON_COREL_Pos (0UL)
8653 #define SCU_COCON_COREL_Msk (0xfUL)
8654 /* ======================================================== DMAIEN1 ======================================================== */
8655 #define SCU_DMAIEN1_CH8IE_Pos (7UL)
8656 #define SCU_DMAIEN1_CH8IE_Msk (0x80UL)
8657 #define SCU_DMAIEN1_CH7IE_Pos (6UL)
8658 #define SCU_DMAIEN1_CH7IE_Msk (0x40UL)
8659 #define SCU_DMAIEN1_CH6IE_Pos (5UL)
8660 #define SCU_DMAIEN1_CH6IE_Msk (0x20UL)
8661 #define SCU_DMAIEN1_CH5IE_Pos (4UL)
8662 #define SCU_DMAIEN1_CH5IE_Msk (0x10UL)
8663 #define SCU_DMAIEN1_CH4IE_Pos (3UL)
8664 #define SCU_DMAIEN1_CH4IE_Msk (0x8UL)
8665 #define SCU_DMAIEN1_CH3IE_Pos (2UL)
8666 #define SCU_DMAIEN1_CH3IE_Msk (0x4UL)
8667 #define SCU_DMAIEN1_CH2IE_Pos (1UL)
8668 #define SCU_DMAIEN1_CH2IE_Msk (0x2UL)
8669 #define SCU_DMAIEN1_CH1IE_Pos (0UL)
8670 #define SCU_DMAIEN1_CH1IE_Msk (0x1UL)
8671 /* ======================================================== DMAIEN2 ======================================================== */
8672 #define SCU_DMAIEN2_SDADCIE_Pos (6UL)
8673 #define SCU_DMAIEN2_SDADCIE_Msk (0x40UL)
8674 #define SCU_DMAIEN2_GPT12IE_Pos (5UL)
8675 #define SCU_DMAIEN2_GPT12IE_Msk (0x20UL)
8676 #define SCU_DMAIEN2_SSCRXIE_Pos (4UL)
8677 #define SCU_DMAIEN2_SSCRXIE_Msk (0x10UL)
8678 #define SCU_DMAIEN2_SSCTXIE_Pos (3UL)
8679 #define SCU_DMAIEN2_SSCTXIE_Msk (0x8UL)
8680 #define SCU_DMAIEN2_TRSEQ2RDYIE_Pos (2UL)
8681 #define SCU_DMAIEN2_TRSEQ2RDYIE_Msk (0x4UL)
8682 #define SCU_DMAIEN2_TRSEQ1RDYIE_Pos (1UL)
8683 #define SCU_DMAIEN2_TRSEQ1RDYIE_Msk (0x2UL)
8684 #define SCU_DMAIEN2_TRERRIE_Pos (0UL)
8685 #define SCU_DMAIEN2_TRERRIE_Msk (0x1UL)
8686 /* ======================================================== DMAIRC1 ======================================================== */
8687 #define SCU_DMAIRC1_CH8_Pos (7UL)
8688 #define SCU_DMAIRC1_CH8_Msk (0x80UL)
8689 #define SCU_DMAIRC1_CH7_Pos (6UL)
8690 #define SCU_DMAIRC1_CH7_Msk (0x40UL)
8691 #define SCU_DMAIRC1_CH6_Pos (5UL)
8692 #define SCU_DMAIRC1_CH6_Msk (0x20UL)
8693 #define SCU_DMAIRC1_CH5_Pos (4UL)
8694 #define SCU_DMAIRC1_CH5_Msk (0x10UL)
8695 #define SCU_DMAIRC1_CH4_Pos (3UL)
8696 #define SCU_DMAIRC1_CH4_Msk (0x8UL)
8697 #define SCU_DMAIRC1_CH3_Pos (2UL)
8698 #define SCU_DMAIRC1_CH3_Msk (0x4UL)
8699 #define SCU_DMAIRC1_CH2_Pos (1UL)
8700 #define SCU_DMAIRC1_CH2_Msk (0x2UL)
8701 #define SCU_DMAIRC1_CH1_Pos (0UL)
8702 #define SCU_DMAIRC1_CH1_Msk (0x1UL)
8703 /* ====================================================== DMAIRC1CLR ======================================================= */
8704 #define SCU_DMAIRC1CLR_CH8C_Pos (7UL)
8705 #define SCU_DMAIRC1CLR_CH8C_Msk (0x80UL)
8706 #define SCU_DMAIRC1CLR_CH7C_Pos (6UL)
8707 #define SCU_DMAIRC1CLR_CH7C_Msk (0x40UL)
8708 #define SCU_DMAIRC1CLR_CH6C_Pos (5UL)
8709 #define SCU_DMAIRC1CLR_CH6C_Msk (0x20UL)
8710 #define SCU_DMAIRC1CLR_CH5C_Pos (4UL)
8711 #define SCU_DMAIRC1CLR_CH5C_Msk (0x10UL)
8712 #define SCU_DMAIRC1CLR_CH4C_Pos (3UL)
8713 #define SCU_DMAIRC1CLR_CH4C_Msk (0x8UL)
8714 #define SCU_DMAIRC1CLR_CH3C_Pos (2UL)
8715 #define SCU_DMAIRC1CLR_CH3C_Msk (0x4UL)
8716 #define SCU_DMAIRC1CLR_CH2C_Pos (1UL)
8717 #define SCU_DMAIRC1CLR_CH2C_Msk (0x2UL)
8718 #define SCU_DMAIRC1CLR_CH1C_Pos (0UL)
8719 #define SCU_DMAIRC1CLR_CH1C_Msk (0x1UL)
8720 /* ======================================================== DMAIRC2 ======================================================== */
8721 #define SCU_DMAIRC2_SDADC_Pos (6UL)
8722 #define SCU_DMAIRC2_SDADC_Msk (0x40UL)
8723 #define SCU_DMAIRC2_GPT12_Pos (5UL)
8724 #define SCU_DMAIRC2_GPT12_Msk (0x20UL)
8725 #define SCU_DMAIRC2_SSC2RDY_Pos (4UL)
8726 #define SCU_DMAIRC2_SSC2RDY_Msk (0x10UL)
8727 #define SCU_DMAIRC2_SSC1RDY_Pos (3UL)
8728 #define SCU_DMAIRC2_SSC1RDY_Msk (0x8UL)
8729 #define SCU_DMAIRC2_TRSEQ2DY_Pos (2UL)
8730 #define SCU_DMAIRC2_TRSEQ2DY_Msk (0x4UL)
8731 #define SCU_DMAIRC2_TRSEQ1DY_Pos (1UL)
8732 #define SCU_DMAIRC2_TRSEQ1DY_Msk (0x2UL)
8733 #define SCU_DMAIRC2_STRDY_Pos (0UL)
8734 #define SCU_DMAIRC2_STRDY_Msk (0x1UL)
8735 /* ====================================================== DMAIRC2CLR ======================================================= */
8736 #define SCU_DMAIRC2CLR_SDADCC_Pos (6UL)
8737 #define SCU_DMAIRC2CLR_SDADCC_Msk (0x40UL)
8738 #define SCU_DMAIRC2CLR_GPT12C_Pos (5UL)
8739 #define SCU_DMAIRC2CLR_GPT12C_Msk (0x20UL)
8740 #define SCU_DMAIRC2CLR_SSC2C_Pos (4UL)
8741 #define SCU_DMAIRC2CLR_SSC2C_Msk (0x10UL)
8742 #define SCU_DMAIRC2CLR_SSC1C_Pos (3UL)
8743 #define SCU_DMAIRC2CLR_SSC1C_Msk (0x8UL)
8744 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos (2UL)
8745 #define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk (0x4UL)
8746 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos (1UL)
8747 #define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk (0x2UL)
8748 /* ======================================================= DMASRCCLR ======================================================= */
8749 #define SCU_DMASRCCLR_GPT12_T3C_Pos (7UL)
8750 #define SCU_DMASRCCLR_GPT12_T3C_Msk (0x80UL)
8751 #define SCU_DMASRCCLR_SSCRXC_Pos (6UL)
8752 #define SCU_DMASRCCLR_SSCRXC_Msk (0x40UL)
8753 #define SCU_DMASRCCLR_SSCTXC_Pos (5UL)
8754 #define SCU_DMASRCCLR_SSCTXC_Msk (0x20UL)
8755 /* ======================================================= DMASRCSEL ======================================================= */
8756 #define SCU_DMASRCSEL_GPT12_T3_Pos (7UL)
8757 #define SCU_DMASRCSEL_GPT12_T3_Msk (0x80UL)
8758 #define SCU_DMASRCSEL_SSCRX_Pos (6UL)
8759 #define SCU_DMASRCSEL_SSCRX_Msk (0x40UL)
8760 #define SCU_DMASRCSEL_SSCTX_Pos (5UL)
8761 #define SCU_DMASRCSEL_SSCTX_Msk (0x20UL)
8762 #define SCU_DMASRCSEL_T12PM_DMAEN_Pos (3UL)
8763 #define SCU_DMASRCSEL_T12PM_DMAEN_Msk (0x8UL)
8764 #define SCU_DMASRCSEL_T12ZM_DMAEN_Pos (2UL)
8765 #define SCU_DMASRCSEL_T12ZM_DMAEN_Msk (0x4UL)
8766 #define SCU_DMASRCSEL_SSCRXSRCSEL_Pos (1UL)
8767 #define SCU_DMASRCSEL_SSCRXSRCSEL_Msk (0x2UL)
8768 #define SCU_DMASRCSEL_SSCTXSRCSEL_Pos (0UL)
8769 #define SCU_DMASRCSEL_SSCTXSRCSEL_Msk (0x1UL)
8770 /* ====================================================== DMASRCSEL2 ======================================================= */
8771 #define SCU_DMASRCSEL2_GPT12_DMAEN_Pos (0UL)
8772 #define SCU_DMASRCSEL2_GPT12_DMAEN_Msk (0x3UL)
8773 /* ======================================================== EDCCON ========================================================= */
8774 #define SCU_EDCCON_NVMIE_Pos (2UL)
8775 #define SCU_EDCCON_NVMIE_Msk (0x4UL)
8776 #define SCU_EDCCON_RIE_Pos (0UL)
8777 #define SCU_EDCCON_RIE_Msk (0x1UL)
8778 /* ======================================================== EDCSCLR ======================================================== */
8779 #define SCU_EDCSCLR_RSBEC_Pos (4UL)
8780 #define SCU_EDCSCLR_RSBEC_Msk (0x10UL)
8781 #define SCU_EDCSCLR_NVMDBEC_Pos (2UL)
8782 #define SCU_EDCSCLR_NVMDBEC_Msk (0x4UL)
8783 #define SCU_EDCSCLR_RDBEC_Pos (0UL)
8784 #define SCU_EDCSCLR_RDBEC_Msk (0x1UL)
8785 /* ======================================================== EDCSTAT ======================================================== */
8786 #define SCU_EDCSTAT_RSBE_Pos (4UL)
8787 #define SCU_EDCSTAT_RSBE_Msk (0x10UL)
8788 #define SCU_EDCSTAT_NVMDBE_Pos (2UL)
8789 #define SCU_EDCSTAT_NVMDBE_Msk (0x4UL)
8790 #define SCU_EDCSTAT_RDBE_Pos (0UL)
8791 #define SCU_EDCSTAT_RDBE_Msk (0x1UL)
8792 /* ======================================================== EXICON0 ======================================================== */
8793 #define SCU_EXICON0_MON_Trig_Sel_Pos (6UL)
8794 #define SCU_EXICON0_MON_Trig_Sel_Msk (0xc0UL)
8795 #define SCU_EXICON0_EXINT2_Pos (4UL)
8796 #define SCU_EXICON0_EXINT2_Msk (0x30UL)
8797 #define SCU_EXICON0_EXINT1_Pos (2UL)
8798 #define SCU_EXICON0_EXINT1_Msk (0xcUL)
8799 #define SCU_EXICON0_EXINT0_Pos (0UL)
8800 #define SCU_EXICON0_EXINT0_Msk (0x3UL)
8801 /* ======================================================= GPT12ICLR ======================================================= */
8802 #define SCU_GPT12ICLR_CRC_Pos (5UL)
8803 #define SCU_GPT12ICLR_CRC_Msk (0x20UL)
8804 #define SCU_GPT12ICLR_T6C_Pos (4UL)
8805 #define SCU_GPT12ICLR_T6C_Msk (0x10UL)
8806 #define SCU_GPT12ICLR_T5C_Pos (3UL)
8807 #define SCU_GPT12ICLR_T5C_Msk (0x8UL)
8808 #define SCU_GPT12ICLR_T4C_Pos (2UL)
8809 #define SCU_GPT12ICLR_T4C_Msk (0x4UL)
8810 #define SCU_GPT12ICLR_T3C_Pos (1UL)
8811 #define SCU_GPT12ICLR_T3C_Msk (0x2UL)
8812 #define SCU_GPT12ICLR_T2C_Pos (0UL)
8813 #define SCU_GPT12ICLR_T2C_Msk (0x1UL)
8814 /* ======================================================= GPT12IEN ======================================================== */
8815 #define SCU_GPT12IEN_CRIE_Pos (5UL)
8816 #define SCU_GPT12IEN_CRIE_Msk (0x20UL)
8817 #define SCU_GPT12IEN_T6IE_Pos (4UL)
8818 #define SCU_GPT12IEN_T6IE_Msk (0x10UL)
8819 #define SCU_GPT12IEN_T5IE_Pos (3UL)
8820 #define SCU_GPT12IEN_T5IE_Msk (0x8UL)
8821 #define SCU_GPT12IEN_T4IE_Pos (2UL)
8822 #define SCU_GPT12IEN_T4IE_Msk (0x4UL)
8823 #define SCU_GPT12IEN_T3IE_Pos (1UL)
8824 #define SCU_GPT12IEN_T3IE_Msk (0x2UL)
8825 #define SCU_GPT12IEN_T2IE_Pos (0UL)
8826 #define SCU_GPT12IEN_T2IE_Msk (0x1UL)
8827 /* ======================================================= GPT12IRC ======================================================== */
8828 #define SCU_GPT12IRC_CR_Pos (5UL)
8829 #define SCU_GPT12IRC_CR_Msk (0x20UL)
8830 #define SCU_GPT12IRC_T6_Pos (4UL)
8831 #define SCU_GPT12IRC_T6_Msk (0x10UL)
8832 #define SCU_GPT12IRC_T5_Pos (3UL)
8833 #define SCU_GPT12IRC_T5_Msk (0x8UL)
8834 #define SCU_GPT12IRC_T4_Pos (2UL)
8835 #define SCU_GPT12IRC_T4_Msk (0x4UL)
8836 #define SCU_GPT12IRC_T3_Pos (1UL)
8837 #define SCU_GPT12IRC_T3_Msk (0x2UL)
8838 #define SCU_GPT12IRC_T2_Pos (0UL)
8839 #define SCU_GPT12IRC_T2_Msk (0x1UL)
8840 /* ====================================================== GPT12PISEL ======================================================= */
8841 #define SCU_GPT12PISEL_T3_GPT12_SEL_Pos (5UL)
8842 #define SCU_GPT12PISEL_T3_GPT12_SEL_Msk (0x20UL)
8843 #define SCU_GPT12PISEL_TRIG_CONF_Pos (4UL)
8844 #define SCU_GPT12PISEL_TRIG_CONF_Msk (0x10UL)
8845 #define SCU_GPT12PISEL_GPT12_Pos (0UL)
8846 #define SCU_GPT12PISEL_GPT12_Msk (0xfUL)
8847 /* ========================================================== ID =========================================================== */
8848 #define SCU_ID_PRODID_Pos (3UL)
8849 #define SCU_ID_PRODID_Msk (0xf8UL)
8850 #define SCU_ID_VERID_Pos (0UL)
8851 #define SCU_ID_VERID_Msk (0x7UL)
8852 /* ========================================================= IEN0 ========================================================== */
8853 #define SCU_IEN0_EA_Pos (7UL)
8854 #define SCU_IEN0_EA_Msk (0x80UL)
8855 /* ======================================================== IRCON0 ========================================================= */
8856 #define SCU_IRCON0_MONF_Pos (7UL)
8857 #define SCU_IRCON0_MONF_Msk (0x80UL)
8858 #define SCU_IRCON0_MONR_Pos (6UL)
8859 #define SCU_IRCON0_MONR_Msk (0x40UL)
8860 #define SCU_IRCON0_EXINT2F_Pos (5UL)
8861 #define SCU_IRCON0_EXINT2F_Msk (0x20UL)
8862 #define SCU_IRCON0_EXINT2R_Pos (4UL)
8863 #define SCU_IRCON0_EXINT2R_Msk (0x10UL)
8864 #define SCU_IRCON0_EXINT1F_Pos (3UL)
8865 #define SCU_IRCON0_EXINT1F_Msk (0x8UL)
8866 #define SCU_IRCON0_EXINT1R_Pos (2UL)
8867 #define SCU_IRCON0_EXINT1R_Msk (0x4UL)
8868 #define SCU_IRCON0_EXINT0F_Pos (1UL)
8869 #define SCU_IRCON0_EXINT0F_Msk (0x2UL)
8870 #define SCU_IRCON0_EXINT0R_Pos (0UL)
8871 #define SCU_IRCON0_EXINT0R_Msk (0x1UL)
8872 /* ======================================================= IRCON0CLR ======================================================= */
8873 #define SCU_IRCON0CLR_MONFC_Pos (7UL)
8874 #define SCU_IRCON0CLR_MONFC_Msk (0x80UL)
8875 #define SCU_IRCON0CLR_MONRC_Pos (6UL)
8876 #define SCU_IRCON0CLR_MONRC_Msk (0x40UL)
8877 #define SCU_IRCON0CLR_EXINT2FC_Pos (5UL)
8878 #define SCU_IRCON0CLR_EXINT2FC_Msk (0x20UL)
8879 #define SCU_IRCON0CLR_EXINT2RC_Pos (4UL)
8880 #define SCU_IRCON0CLR_EXINT2RC_Msk (0x10UL)
8881 #define SCU_IRCON0CLR_EXINT1FC_Pos (3UL)
8882 #define SCU_IRCON0CLR_EXINT1FC_Msk (0x8UL)
8883 #define SCU_IRCON0CLR_EXINT1RC_Pos (2UL)
8884 #define SCU_IRCON0CLR_EXINT1RC_Msk (0x4UL)
8885 #define SCU_IRCON0CLR_EXINT0FC_Pos (1UL)
8886 #define SCU_IRCON0CLR_EXINT0FC_Msk (0x2UL)
8887 #define SCU_IRCON0CLR_EXINT0RC_Pos (0UL)
8888 #define SCU_IRCON0CLR_EXINT0RC_Msk (0x1UL)
8889 /* ======================================================== IRCON1 ========================================================= */
8890 #define SCU_IRCON1_RIR_Pos (2UL)
8891 #define SCU_IRCON1_RIR_Msk (0x4UL)
8892 #define SCU_IRCON1_TIR_Pos (1UL)
8893 #define SCU_IRCON1_TIR_Msk (0x2UL)
8894 #define SCU_IRCON1_EIR_Pos (0UL)
8895 #define SCU_IRCON1_EIR_Msk (0x1UL)
8896 /* ======================================================= IRCON1CLR ======================================================= */
8897 #define SCU_IRCON1CLR_RIRC_Pos (2UL)
8898 #define SCU_IRCON1CLR_RIRC_Msk (0x4UL)
8899 #define SCU_IRCON1CLR_TIRC_Pos (1UL)
8900 #define SCU_IRCON1CLR_TIRC_Msk (0x2UL)
8901 #define SCU_IRCON1CLR_EIRC_Pos (0UL)
8902 #define SCU_IRCON1CLR_EIRC_Msk (0x1UL)
8903 /* ======================================================== IRCON2 ========================================================= */
8904 #define SCU_IRCON2_RIR_Pos (2UL)
8905 #define SCU_IRCON2_RIR_Msk (0x4UL)
8906 #define SCU_IRCON2_TIR_Pos (1UL)
8907 #define SCU_IRCON2_TIR_Msk (0x2UL)
8908 #define SCU_IRCON2_EIR_Pos (0UL)
8909 #define SCU_IRCON2_EIR_Msk (0x1UL)
8910 /* ======================================================= IRCON2CLR ======================================================= */
8911 #define SCU_IRCON2CLR_RIRC_Pos (2UL)
8912 #define SCU_IRCON2CLR_RIRC_Msk (0x4UL)
8913 #define SCU_IRCON2CLR_TIRC_Pos (1UL)
8914 #define SCU_IRCON2CLR_TIRC_Msk (0x2UL)
8915 #define SCU_IRCON2CLR_EIRC_Pos (0UL)
8916 #define SCU_IRCON2CLR_EIRC_Msk (0x1UL)
8917 /* ======================================================== IRCON3 ========================================================= */
8918 #define SCU_IRCON3_CCU6SR1_Pos (4UL)
8919 #define SCU_IRCON3_CCU6SR1_Msk (0x10UL)
8920 #define SCU_IRCON3_CCU6SR0_Pos (0UL)
8921 #define SCU_IRCON3_CCU6SR0_Msk (0x1UL)
8922 /* ======================================================= IRCON3CLR ======================================================= */
8923 #define SCU_IRCON3CLR_CCU6SR1C_Pos (4UL)
8924 #define SCU_IRCON3CLR_CCU6SR1C_Msk (0x10UL)
8925 #define SCU_IRCON3CLR_CCU6SR0C_Pos (0UL)
8926 #define SCU_IRCON3CLR_CCU6SR0C_Msk (0x1UL)
8927 /* ======================================================== IRCON4 ========================================================= */
8928 #define SCU_IRCON4_CCU6SR3_Pos (4UL)
8929 #define SCU_IRCON4_CCU6SR3_Msk (0x10UL)
8930 #define SCU_IRCON4_CCU6SR2_Pos (0UL)
8931 #define SCU_IRCON4_CCU6SR2_Msk (0x1UL)
8932 /* ======================================================= IRCON4CLR ======================================================= */
8933 #define SCU_IRCON4CLR_CCU6SR3C_Pos (4UL)
8934 #define SCU_IRCON4CLR_CCU6SR3C_Msk (0x10UL)
8935 #define SCU_IRCON4CLR_CCU6SR2C_Pos (0UL)
8936 #define SCU_IRCON4CLR_CCU6SR2C_Msk (0x1UL)
8937 /* ======================================================== LINSCLR ======================================================== */
8938 #define SCU_LINSCLR_BRKC_Pos (3UL)
8939 #define SCU_LINSCLR_BRKC_Msk (0x8UL)
8940 #define SCU_LINSCLR_EOFSYNC_Pos (4UL)
8941 #define SCU_LINSCLR_EOFSYNC_Msk (0x10UL)
8942 #define SCU_LINSCLR_ERRSYNC_Pos (5UL)
8943 #define SCU_LINSCLR_ERRSYNC_Msk (0x20UL)
8944 /* ========================================================= LINST ========================================================= */
8945 #define SCU_LINST_BRDIS_Pos (0UL)
8946 #define SCU_LINST_BRDIS_Msk (0x1UL)
8947 #define SCU_LINST_BGSEL_Pos (1UL)
8948 #define SCU_LINST_BGSEL_Msk (0x6UL)
8949 #define SCU_LINST_BRK_Pos (3UL)
8950 #define SCU_LINST_BRK_Msk (0x8UL)
8951 #define SCU_LINST_EOFSYN_Pos (4UL)
8952 #define SCU_LINST_EOFSYN_Msk (0x10UL)
8953 #define SCU_LINST_ERRSYN_Pos (5UL)
8954 #define SCU_LINST_ERRSYN_Msk (0x20UL)
8955 #define SCU_LINST_SYNEN_Pos (6UL)
8956 #define SCU_LINST_SYNEN_Msk (0x40UL)
8957 /* ====================================================== MEM_ACC_STS ====================================================== */
8958 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Pos (6UL)
8959 #define SCU_MEM_ACC_STS_RAM_PROT_ERR_Msk (0x40UL)
8960 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Pos (5UL)
8961 #define SCU_MEM_ACC_STS_ROM_ADDR_ERR_Msk (0x20UL)
8962 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Pos (4UL)
8963 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Msk (0x10UL)
8964 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Pos (3UL)
8965 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Msk (0x8UL)
8966 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Pos (2UL)
8967 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Msk (0x4UL)
8968 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Pos (1UL)
8969 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Msk (0x2UL)
8970 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Pos (0UL)
8971 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Msk (0x1UL)
8972 /* ======================================================== MEMSTAT ======================================================== */
8973 #define SCU_MEMSTAT_SASTATUS_Pos (6UL)
8974 #define SCU_MEMSTAT_SASTATUS_Msk (0xc0UL)
8975 #define SCU_MEMSTAT_SECTORINFO_Pos (0UL)
8976 #define SCU_MEMSTAT_SECTORINFO_Msk (0x3fUL)
8977 /* ======================================================== MODIEN1 ======================================================== */
8978 #define SCU_MODIEN1_TIEN1_Pos (7UL)
8979 #define SCU_MODIEN1_TIEN1_Msk (0x80UL)
8980 #define SCU_MODIEN1_RIEN1_Pos (6UL)
8981 #define SCU_MODIEN1_RIEN1_Msk (0x40UL)
8982 #define SCU_MODIEN1_RIREN1_Pos (2UL)
8983 #define SCU_MODIEN1_RIREN1_Msk (0x4UL)
8984 #define SCU_MODIEN1_TIREN1_Pos (1UL)
8985 #define SCU_MODIEN1_TIREN1_Msk (0x2UL)
8986 #define SCU_MODIEN1_EIREN1_Pos (0UL)
8987 #define SCU_MODIEN1_EIREN1_Msk (0x1UL)
8988 /* ======================================================== MODIEN2 ======================================================== */
8989 #define SCU_MODIEN2_TIEN2_Pos (7UL)
8990 #define SCU_MODIEN2_TIEN2_Msk (0x80UL)
8991 #define SCU_MODIEN2_RIEN2_Pos (6UL)
8992 #define SCU_MODIEN2_RIEN2_Msk (0x40UL)
8993 #define SCU_MODIEN2_EXINT2_EN_Pos (5UL)
8994 #define SCU_MODIEN2_EXINT2_EN_Msk (0x20UL)
8995 #define SCU_MODIEN2_RIREN2_Pos (2UL)
8996 #define SCU_MODIEN2_RIREN2_Msk (0x4UL)
8997 #define SCU_MODIEN2_TIREN2_Pos (1UL)
8998 #define SCU_MODIEN2_TIREN2_Msk (0x2UL)
8999 #define SCU_MODIEN2_EIREN2_Pos (0UL)
9000 #define SCU_MODIEN2_EIREN2_Msk (0x1UL)
9001 /* ======================================================== MODIEN3 ======================================================== */
9002 #define SCU_MODIEN3_MONSTS_Pos (5UL)
9003 #define SCU_MODIEN3_MONSTS_Msk (0x20UL)
9004 #define SCU_MODIEN3_MONIE_Pos (4UL)
9005 #define SCU_MODIEN3_MONIE_Msk (0x10UL)
9006 #define SCU_MODIEN3_IE0_Pos (0UL)
9007 #define SCU_MODIEN3_IE0_Msk (0x1UL)
9008 /* ======================================================== MODIEN4 ======================================================== */
9009 #define SCU_MODIEN4_IE1_Pos (0UL)
9010 #define SCU_MODIEN4_IE1_Msk (0x1UL)
9011 /* ======================================================= MODPISEL ======================================================== */
9012 #define SCU_MODPISEL_U_TX_CONDIS_Pos (7UL)
9013 #define SCU_MODPISEL_U_TX_CONDIS_Msk (0x80UL)
9014 #define SCU_MODPISEL_URIOS1_Pos (6UL)
9015 #define SCU_MODPISEL_URIOS1_Msk (0x40UL)
9016 #define SCU_MODPISEL_EXINT2IS_Pos (4UL)
9017 #define SCU_MODPISEL_EXINT2IS_Msk (0x30UL)
9018 #define SCU_MODPISEL_EXINT1IS_Pos (2UL)
9019 #define SCU_MODPISEL_EXINT1IS_Msk (0xcUL)
9020 #define SCU_MODPISEL_EXINT0IS_Pos (0UL)
9021 #define SCU_MODPISEL_EXINT0IS_Msk (0x3UL)
9022 /* ======================================================= MODPISEL1 ======================================================= */
9023 #define SCU_MODPISEL1_T21EXCON_Pos (7UL)
9024 #define SCU_MODPISEL1_T21EXCON_Msk (0x80UL)
9025 #define SCU_MODPISEL1_T2EXCON_Pos (6UL)
9026 #define SCU_MODPISEL1_T2EXCON_Msk (0x40UL)
9027 #define SCU_MODPISEL1_GPT12CAPINB_Pos (0UL)
9028 #define SCU_MODPISEL1_GPT12CAPINB_Msk (0x1UL)
9029 /* ======================================================= MODPISEL2 ======================================================= */
9030 #define SCU_MODPISEL2_T21EXIS_Pos (6UL)
9031 #define SCU_MODPISEL2_T21EXIS_Msk (0xc0UL)
9032 #define SCU_MODPISEL2_T2EXIS_Pos (4UL)
9033 #define SCU_MODPISEL2_T2EXIS_Msk (0x30UL)
9034 #define SCU_MODPISEL2_T21IS_Pos (2UL)
9035 #define SCU_MODPISEL2_T21IS_Msk (0xcUL)
9036 #define SCU_MODPISEL2_T2IS_Pos (0UL)
9037 #define SCU_MODPISEL2_T2IS_Msk (0x3UL)
9038 /* ======================================================= MODPISEL3 ======================================================= */
9039 #define SCU_MODPISEL3_URIOS2_Pos (6UL)
9040 #define SCU_MODPISEL3_URIOS2_Msk (0x40UL)
9041 /* ======================================================= MODSUSP1 ======================================================== */
9042 #define SCU_MODSUSP1_T21_SUSP_Pos (6UL)
9043 #define SCU_MODSUSP1_T21_SUSP_Msk (0x40UL)
9044 #define SCU_MODSUSP1_GPT12_SUSP_Pos (4UL)
9045 #define SCU_MODSUSP1_GPT12_SUSP_Msk (0x10UL)
9046 #define SCU_MODSUSP1_T2_SUSP_Pos (3UL)
9047 #define SCU_MODSUSP1_T2_SUSP_Msk (0x8UL)
9048 #define SCU_MODSUSP1_T13SUSP_Pos (2UL)
9049 #define SCU_MODSUSP1_T13SUSP_Msk (0x4UL)
9050 #define SCU_MODSUSP1_T12SUSP_Pos (1UL)
9051 #define SCU_MODSUSP1_T12SUSP_Msk (0x2UL)
9052 #define SCU_MODSUSP1_WDTSUSP_Pos (0UL)
9053 #define SCU_MODSUSP1_WDTSUSP_Msk (0x1UL)
9054 /* ======================================================= MODSUSP2 ======================================================== */
9055 #define SCU_MODSUSP2_ADC1_SUSP_Pos (2UL)
9056 #define SCU_MODSUSP2_ADC1_SUSP_Msk (0x4UL)
9057 #define SCU_MODSUSP2_MU_SUSP_Pos (1UL)
9058 #define SCU_MODSUSP2_MU_SUSP_Msk (0x2UL)
9059 #define SCU_MODSUSP2_T3_SUSP_Pos (0UL)
9060 #define SCU_MODSUSP2_T3_SUSP_Msk (0x1UL)
9061 /* ======================================================== NMICLR ========================================================= */
9062 #define SCU_NMICLR_NMISUPC_Pos (7UL)
9063 #define SCU_NMICLR_NMISUPC_Msk (0x80UL)
9064 #define SCU_NMICLR_NMIECCC_Pos (6UL)
9065 #define SCU_NMICLR_NMIECCC_Msk (0x40UL)
9066 #define SCU_NMICLR_NMIMAPC_Pos (5UL)
9067 #define SCU_NMICLR_NMIMAPC_Msk (0x20UL)
9068 #define SCU_NMICLR_NMIOWDC_Pos (4UL)
9069 #define SCU_NMICLR_NMIOWDC_Msk (0x10UL)
9070 #define SCU_NMICLR_NMIOTC_Pos (3UL)
9071 #define SCU_NMICLR_NMIOTC_Msk (0x8UL)
9072 #define SCU_NMICLR_NMINVMC_Pos (2UL)
9073 #define SCU_NMICLR_NMINVMC_Msk (0x4UL)
9074 #define SCU_NMICLR_NMIPLLC_Pos (1UL)
9075 #define SCU_NMICLR_NMIPLLC_Msk (0x2UL)
9076 #define SCU_NMICLR_NMIWDTC_Pos (0UL)
9077 #define SCU_NMICLR_NMIWDTC_Msk (0x1UL)
9078 /* ======================================================== NMICON ========================================================= */
9079 #define SCU_NMICON_NMISUP_Pos (7UL)
9080 #define SCU_NMICON_NMISUP_Msk (0x80UL)
9081 #define SCU_NMICON_NMIECC_Pos (6UL)
9082 #define SCU_NMICON_NMIECC_Msk (0x40UL)
9083 #define SCU_NMICON_NMIMAP_Pos (5UL)
9084 #define SCU_NMICON_NMIMAP_Msk (0x20UL)
9085 #define SCU_NMICON_NMIOWD_Pos (4UL)
9086 #define SCU_NMICON_NMIOWD_Msk (0x10UL)
9087 #define SCU_NMICON_NMIOT_Pos (3UL)
9088 #define SCU_NMICON_NMIOT_Msk (0x8UL)
9089 #define SCU_NMICON_NMINVM_Pos (2UL)
9090 #define SCU_NMICON_NMINVM_Msk (0x4UL)
9091 #define SCU_NMICON_NMIPLL_Pos (1UL)
9092 #define SCU_NMICON_NMIPLL_Msk (0x2UL)
9093 #define SCU_NMICON_NMIWDT_Pos (0UL)
9094 #define SCU_NMICON_NMIWDT_Msk (0x1UL)
9095 /* ========================================================= NMISR ========================================================= */
9096 #define SCU_NMISR_FNMISUP_Pos (7UL)
9097 #define SCU_NMISR_FNMISUP_Msk (0x80UL)
9098 #define SCU_NMISR_FNMIECC_Pos (6UL)
9099 #define SCU_NMISR_FNMIECC_Msk (0x40UL)
9100 #define SCU_NMISR_FNMIMAP_Pos (5UL)
9101 #define SCU_NMISR_FNMIMAP_Msk (0x20UL)
9102 #define SCU_NMISR_FNMIOWD_Pos (4UL)
9103 #define SCU_NMISR_FNMIOWD_Msk (0x10UL)
9104 #define SCU_NMISR_FNMIOT_Pos (3UL)
9105 #define SCU_NMISR_FNMIOT_Msk (0x8UL)
9106 #define SCU_NMISR_FNMINVM_Pos (2UL)
9107 #define SCU_NMISR_FNMINVM_Msk (0x4UL)
9108 #define SCU_NMISR_FNMIPLL_Pos (1UL)
9109 #define SCU_NMISR_FNMIPLL_Msk (0x2UL)
9110 #define SCU_NMISR_FNMIWDT_Pos (0UL)
9111 #define SCU_NMISR_FNMIWDT_Msk (0x1UL)
9112 /* ===================================================== NVM_PROT_STS ====================================================== */
9113 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Pos (3UL)
9114 #define SCU_NVM_PROT_STS_NVMPROTSTSL_3_Msk (0x8UL)
9115 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Pos (2UL)
9116 #define SCU_NVM_PROT_STS_NVMPROTSTSL_2_Msk (0x4UL)
9117 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Pos (1UL)
9118 #define SCU_NVM_PROT_STS_NVMPROTSTSL_1_Msk (0x2UL)
9119 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Pos (0UL)
9120 #define SCU_NVM_PROT_STS_NVMPROTSTSL_0_Msk (0x1UL)
9121 /* ======================================================== OSC_CON ======================================================== */
9122 #define SCU_OSC_CON_OSCTRIM_8_Pos (7UL)
9123 #define SCU_OSC_CON_OSCTRIM_8_Msk (0x80UL)
9124 #define SCU_OSC_CON_XPD_Pos (4UL)
9125 #define SCU_OSC_CON_XPD_Msk (0x10UL)
9126 #define SCU_OSC_CON_OSC2L_Pos (3UL)
9127 #define SCU_OSC_CON_OSC2L_Msk (0x8UL)
9128 #define SCU_OSC_CON_OSCWDTRST_Pos (2UL)
9129 #define SCU_OSC_CON_OSCWDTRST_Msk (0x4UL)
9130 #define SCU_OSC_CON_OSCSS_Pos (0UL)
9131 #define SCU_OSC_CON_OSCSS_Msk (0x3UL)
9132 /* ======================================================= P0_POCON0 ======================================================= */
9133 #define SCU_P0_POCON0_PDM1_Pos (4UL)
9134 #define SCU_P0_POCON0_PDM1_Msk (0x70UL)
9135 #define SCU_P0_POCON0_PDM0_Pos (0UL)
9136 #define SCU_P0_POCON0_PDM0_Msk (0x7UL)
9137 /* ======================================================= P0_POCON1 ======================================================= */
9138 #define SCU_P0_POCON1_PDM3_Pos (4UL)
9139 #define SCU_P0_POCON1_PDM3_Msk (0x70UL)
9140 #define SCU_P0_POCON1_PDM2_Pos (0UL)
9141 #define SCU_P0_POCON1_PDM2_Msk (0x7UL)
9142 /* ======================================================= P0_POCON2 ======================================================= */
9143 #define SCU_P0_POCON2_PDM4_Pos (0UL)
9144 #define SCU_P0_POCON2_PDM4_Msk (0x7UL)
9145 /* ======================================================= P1_POCON0 ======================================================= */
9146 #define SCU_P1_POCON0_PDM1_Pos (4UL)
9147 #define SCU_P1_POCON0_PDM1_Msk (0x70UL)
9148 #define SCU_P1_POCON0_PDM0_Pos (0UL)
9149 #define SCU_P1_POCON0_PDM0_Msk (0x7UL)
9150 /* ======================================================= P1_POCON1 ======================================================= */
9151 #define SCU_P1_POCON1_PDM3_Pos (4UL)
9152 #define SCU_P1_POCON1_PDM3_Msk (0x70UL)
9153 #define SCU_P1_POCON1_PDM2_Pos (0UL)
9154 #define SCU_P1_POCON1_PDM2_Msk (0x7UL)
9155 /* ======================================================= P1_POCON2 ======================================================= */
9156 #define SCU_P1_POCON2_PDM4_Pos (0UL)
9157 #define SCU_P1_POCON2_PDM4_Msk (0x7UL)
9158 /* ======================================================== PASSWD ========================================================= */
9159 #define SCU_PASSWD_PASS_Pos (3UL)
9160 #define SCU_PASSWD_PASS_Msk (0xf8UL)
9161 #define SCU_PASSWD_PROTECT_S_Pos (2UL)
9162 #define SCU_PASSWD_PROTECT_S_Msk (0x4UL)
9163 #define SCU_PASSWD_MODE_Pos (0UL)
9164 #define SCU_PASSWD_MODE_Msk (0x3UL)
9165 /* ======================================================== PLL_CON ======================================================== */
9166 #define SCU_PLL_CON_NDIV_Pos (4UL)
9167 #define SCU_PLL_CON_NDIV_Msk (0xf0UL)
9168 #define SCU_PLL_CON_VCOBYP_Pos (3UL)
9169 #define SCU_PLL_CON_VCOBYP_Msk (0x8UL)
9170 #define SCU_PLL_CON_OSCDISC_Pos (2UL)
9171 #define SCU_PLL_CON_OSCDISC_Msk (0x4UL)
9172 #define SCU_PLL_CON_RESLD_Pos (1UL)
9173 #define SCU_PLL_CON_RESLD_Msk (0x2UL)
9174 #define SCU_PLL_CON_LOCK_Pos (0UL)
9175 #define SCU_PLL_CON_LOCK_Msk (0x1UL)
9176 /* ======================================================== PMCON0 ========================================================= */
9177 #define SCU_PMCON0_SD_Pos (3UL)
9178 #define SCU_PMCON0_SD_Msk (0x8UL)
9179 #define SCU_PMCON0_PD_Pos (2UL)
9180 #define SCU_PMCON0_PD_Msk (0x4UL)
9181 #define SCU_PMCON0_SL_Pos (1UL)
9182 #define SCU_PMCON0_SL_Msk (0x2UL)
9183 #define SCU_PMCON0_XTAL_ON_Pos (0UL)
9184 #define SCU_PMCON0_XTAL_ON_Msk (0x1UL)
9185 /* ======================================================== PMCON1 ========================================================= */
9186 #define SCU_PMCON1_GPT12_DIS_Pos (4UL)
9187 #define SCU_PMCON1_GPT12_DIS_Msk (0x10UL)
9188 #define SCU_PMCON1_T2_DIS_Pos (3UL)
9189 #define SCU_PMCON1_T2_DIS_Msk (0x8UL)
9190 #define SCU_PMCON1_CCU6_DIS_Pos (2UL)
9191 #define SCU_PMCON1_CCU6_DIS_Msk (0x4UL)
9192 #define SCU_PMCON1_SSC1_DIS_Pos (1UL)
9193 #define SCU_PMCON1_SSC1_DIS_Msk (0x2UL)
9194 #define SCU_PMCON1_ADC1_DIS_Pos (0UL)
9195 #define SCU_PMCON1_ADC1_DIS_Msk (0x1UL)
9196 /* ======================================================== PMCON2 ========================================================= */
9197 #define SCU_PMCON2_T3_DIS_Pos (5UL)
9198 #define SCU_PMCON2_T3_DIS_Msk (0x20UL)
9199 #define SCU_PMCON2_T21_DIS_Pos (3UL)
9200 #define SCU_PMCON2_T21_DIS_Msk (0x8UL)
9201 #define SCU_PMCON2_SSC2_DIS_Pos (1UL)
9202 #define SCU_PMCON2_SSC2_DIS_Msk (0x2UL)
9203 /* ======================================================== RSTCON ========================================================= */
9204 #define SCU_RSTCON_LOCKUP_EN_Pos (7UL)
9205 #define SCU_RSTCON_LOCKUP_EN_Msk (0x80UL)
9206 #define SCU_RSTCON_LOCKUP_Pos (0UL)
9207 #define SCU_RSTCON_LOCKUP_Msk (0x1UL)
9208 /* ==================================================== SYS_STRTUP_STS ===================================================== */
9209 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Pos (2UL)
9210 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Msk (0x4UL)
9211 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Pos (1UL)
9212 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Msk (0x2UL)
9213 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Pos (0UL)
9214 #define SCU_SYS_STRTUP_STS_INIT_FAIL_Msk (0x1UL)
9215 /* ======================================================== SYSCON0 ======================================================== */
9216 #define SCU_SYSCON0_SYSCLKSEL_Pos (6UL)
9217 #define SCU_SYSCON0_SYSCLKSEL_Msk (0xc0UL)
9218 #define SCU_SYSCON0_NVMCLKFAC_Pos (4UL)
9219 #define SCU_SYSCON0_NVMCLKFAC_Msk (0x30UL)
9220 /* ========================================================= TCCR ========================================================== */
9221 #define SCU_TCCR_TCC_Pos (0UL)
9222 #define SCU_TCCR_TCC_Msk (0x3UL)
9223 /* ======================================================== WDTCON ========================================================= */
9224 #define SCU_WDTCON_WINBEN_Pos (5UL)
9225 #define SCU_WDTCON_WINBEN_Msk (0x20UL)
9226 #define SCU_WDTCON_WDTPR_Pos (4UL)
9227 #define SCU_WDTCON_WDTPR_Msk (0x10UL)
9228 #define SCU_WDTCON_WDTEN_Pos (2UL)
9229 #define SCU_WDTCON_WDTEN_Msk (0x4UL)
9230 #define SCU_WDTCON_WDTRS_Pos (1UL)
9231 #define SCU_WDTCON_WDTRS_Msk (0x2UL)
9232 #define SCU_WDTCON_WDTIN_Pos (0UL)
9233 #define SCU_WDTCON_WDTIN_Msk (0x1UL)
9234 /* ========================================================= WDTH ========================================================== */
9235 #define SCU_WDTH_WDT_Pos (0UL)
9236 #define SCU_WDTH_WDT_Msk (0xffUL)
9237 /* ========================================================= WDTL ========================================================== */
9238 #define SCU_WDTL_WDT_Pos (0UL)
9239 #define SCU_WDTL_WDT_Msk (0xffUL)
9240 /* ======================================================== WDTREL ========================================================= */
9241 #define SCU_WDTREL_WDTREL_Pos (0UL)
9242 #define SCU_WDTREL_WDTREL_Msk (0xffUL)
9243 /* ======================================================== WDTWINB ======================================================== */
9244 #define SCU_WDTWINB_WDTWINB_Pos (0UL)
9245 #define SCU_WDTWINB_WDTWINB_Msk (0xffUL)
9248 /* =========================================================================================================================== */
9249 /* ================ SCUPM ================ */
9250 /* =========================================================================================================================== */
9251 
9252 /* ====================================================== AMCLK_CTRL ======================================================= */
9253 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos (0UL)
9254 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk (0x1UL)
9255 /* ==================================================== AMCLK_FREQ_STS ===================================================== */
9256 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Pos (8UL)
9257 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Msk (0x3f00UL)
9258 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Pos (0UL)
9259 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Msk (0x3fUL)
9260 /* ===================================================== AMCLK_TH_HYS ====================================================== */
9261 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos (30UL)
9262 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk (0xc0000000UL)
9263 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos (24UL)
9264 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk (0x3f000000UL)
9265 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos (22UL)
9266 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk (0xc00000UL)
9267 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos (16UL)
9268 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk (0x3f0000UL)
9269 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos (14UL)
9270 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk (0xc000UL)
9271 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos (8UL)
9272 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk (0x3f00UL)
9273 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos (6UL)
9274 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk (0xc0UL)
9275 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos (0UL)
9276 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk (0x3fUL)
9277 /* ===================================================== BDRV_IRQ_CTRL ===================================================== */
9278 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Pos (20UL)
9279 #define SCUPM_BDRV_IRQ_CTRL_VSD_UPTH_IE_Msk (0x100000UL)
9280 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Pos (19UL)
9281 #define SCUPM_BDRV_IRQ_CTRL_VSD_LOWTH_IE_Msk (0x80000UL)
9282 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Pos (18UL)
9283 #define SCUPM_BDRV_IRQ_CTRL_VCP_UPTH_IE_Msk (0x40000UL)
9284 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Pos (17UL)
9285 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH1_IE_Msk (0x20000UL)
9286 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos (16UL)
9287 #define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk (0x10000UL)
9288 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos (13UL)
9289 #define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk (0x2000UL)
9290 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos (12UL)
9291 #define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk (0x1000UL)
9292 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos (11UL)
9293 #define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk (0x800UL)
9294 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos (10UL)
9295 #define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk (0x400UL)
9296 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos (3UL)
9297 #define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk (0x8UL)
9298 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos (2UL)
9299 #define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk (0x4UL)
9300 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos (1UL)
9301 #define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk (0x2UL)
9302 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos (0UL)
9303 #define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk (0x1UL)
9304 /* ======================================================== BDRV_IS ======================================================== */
9305 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Pos (28UL)
9306 #define SCUPM_BDRV_IS_VSD_UPTH_STS_Msk (0x10000000UL)
9307 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Pos (27UL)
9308 #define SCUPM_BDRV_IS_VSD_LOWTH_STS_Msk (0x8000000UL)
9309 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Pos (26UL)
9310 #define SCUPM_BDRV_IS_VCP_UPTH_STS_Msk (0x4000000UL)
9311 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Pos (25UL)
9312 #define SCUPM_BDRV_IS_VCP_LOWTH1_STS_Msk (0x2000000UL)
9313 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Pos (24UL)
9314 #define SCUPM_BDRV_IS_VCP_LOWTH2_STS_Msk (0x1000000UL)
9315 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Pos (20UL)
9316 #define SCUPM_BDRV_IS_VSD_UPTH_IS_Msk (0x100000UL)
9317 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Pos (19UL)
9318 #define SCUPM_BDRV_IS_VSD_LOWTH_IS_Msk (0x80000UL)
9319 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Pos (18UL)
9320 #define SCUPM_BDRV_IS_VCP_UPTH_IS_Msk (0x40000UL)
9321 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Pos (17UL)
9322 #define SCUPM_BDRV_IS_VCP_LOWTH1_IS_Msk (0x20000UL)
9323 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos (16UL)
9324 #define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk (0x10000UL)
9325 #define SCUPM_BDRV_IS_HS2_OC_IS_Pos (13UL)
9326 #define SCUPM_BDRV_IS_HS2_OC_IS_Msk (0x2000UL)
9327 #define SCUPM_BDRV_IS_HS1_OC_IS_Pos (12UL)
9328 #define SCUPM_BDRV_IS_HS1_OC_IS_Msk (0x1000UL)
9329 #define SCUPM_BDRV_IS_LS2_OC_IS_Pos (11UL)
9330 #define SCUPM_BDRV_IS_LS2_OC_IS_Msk (0x800UL)
9331 #define SCUPM_BDRV_IS_LS1_OC_IS_Pos (10UL)
9332 #define SCUPM_BDRV_IS_LS1_OC_IS_Msk (0x400UL)
9333 #define SCUPM_BDRV_IS_HS2_DS_IS_Pos (3UL)
9334 #define SCUPM_BDRV_IS_HS2_DS_IS_Msk (0x8UL)
9335 #define SCUPM_BDRV_IS_HS1_DS_IS_Pos (2UL)
9336 #define SCUPM_BDRV_IS_HS1_DS_IS_Msk (0x4UL)
9337 #define SCUPM_BDRV_IS_LS2_DS_IS_Pos (1UL)
9338 #define SCUPM_BDRV_IS_LS2_DS_IS_Msk (0x2UL)
9339 #define SCUPM_BDRV_IS_LS1_DS_IS_Pos (0UL)
9340 #define SCUPM_BDRV_IS_LS1_DS_IS_Msk (0x1UL)
9341 /* ====================================================== BDRV_ISCLR ======================================================= */
9342 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Pos (28UL)
9343 #define SCUPM_BDRV_ISCLR_VSD_UPTH_SCLR_Msk (0x10000000UL)
9344 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Pos (27UL)
9345 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_SCLR_Msk (0x8000000UL)
9346 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Pos (26UL)
9347 #define SCUPM_BDRV_ISCLR_VCP_UPTH_SCLR_Msk (0x4000000UL)
9348 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Pos (25UL)
9349 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_SCLR_Msk (0x2000000UL)
9350 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Pos (24UL)
9351 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_SCLR_Msk (0x1000000UL)
9352 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Pos (20UL)
9353 #define SCUPM_BDRV_ISCLR_VSD_UPTH_ICLR_Msk (0x100000UL)
9354 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Pos (19UL)
9355 #define SCUPM_BDRV_ISCLR_VSD_LOWTH_ICLR_Msk (0x80000UL)
9356 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Pos (18UL)
9357 #define SCUPM_BDRV_ISCLR_VCP_UPTH_ICLR_Msk (0x40000UL)
9358 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Pos (17UL)
9359 #define SCUPM_BDRV_ISCLR_VCP_LOWTH1_ICLR_Msk (0x20000UL)
9360 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos (16UL)
9361 #define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk (0x10000UL)
9362 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos (13UL)
9363 #define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk (0x2000UL)
9364 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos (12UL)
9365 #define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk (0x1000UL)
9366 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos (11UL)
9367 #define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk (0x800UL)
9368 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos (10UL)
9369 #define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk (0x400UL)
9370 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos (3UL)
9371 #define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk (0x8UL)
9372 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos (2UL)
9373 #define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk (0x4UL)
9374 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos (1UL)
9375 #define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk (0x2UL)
9376 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos (0UL)
9377 #define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk (0x1UL)
9378 /* ========================================================= BFSTS ========================================================= */
9379 #define SCUPM_BFSTS_SBFSTS_Pos (1UL)
9380 #define SCUPM_BFSTS_SBFSTS_Msk (0x2UL)
9381 #define SCUPM_BFSTS_DBFSTS_Pos (0UL)
9382 #define SCUPM_BFSTS_DBFSTS_Msk (0x1UL)
9383 /* ======================================================= BFSTS_CLR ======================================================= */
9384 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Pos (1UL)
9385 #define SCUPM_BFSTS_CLR_SBFSTSCLR_Msk (0x2UL)
9386 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Pos (0UL)
9387 #define SCUPM_BFSTS_CLR_DBFSTSCLR_Msk (0x1UL)
9388 /* ========================================================= DBFA ========================================================== */
9389 #define SCUPM_DBFA_DBFA_Pos (0UL)
9390 #define SCUPM_DBFA_DBFA_Msk (0xffffffffUL)
9391 /* ===================================================== PCU_CTRL_STS ====================================================== */
9392 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos (26UL)
9393 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk (0x4000000UL)
9394 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos (25UL)
9395 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk (0x2000000UL)
9396 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Pos (24UL)
9397 #define SCUPM_PCU_CTRL_STS_SYS_OT_PS_DIS_Msk (0x1000000UL)
9398 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Pos (14UL)
9399 #define SCUPM_PCU_CTRL_STS_SYS_VSD_OV_SLM_DIS_Msk (0x4000UL)
9400 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos (8UL)
9401 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk (0x100UL)
9402 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos (7UL)
9403 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk (0x80UL)
9404 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos (1UL)
9405 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk (0x2UL)
9406 /* ========================================================= SBFA ========================================================== */
9407 #define SCUPM_SBFA_SBFA_Pos (0UL)
9408 #define SCUPM_SBFA_SBFA_Msk (0xffffffffUL)
9409 /* ======================================================== STCALIB ======================================================== */
9410 #define SCUPM_STCALIB_STCALIB_Pos (0UL)
9411 #define SCUPM_STCALIB_STCALIB_Msk (0x3ffffffUL)
9412 /* ===================================================== SYS_IRQ_CTRL ====================================================== */
9413 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Pos (23UL)
9414 #define SCUPM_SYS_IRQ_CTRL_ADC4_EOC_IE_Msk (0x800000UL)
9415 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Pos (22UL)
9416 #define SCUPM_SYS_IRQ_CTRL_ADC3_EOC_IE_Msk (0x400000UL)
9417 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Pos (15UL)
9418 #define SCUPM_SYS_IRQ_CTRL_ADC2_ESM_IE_Msk (0x8000UL)
9419 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Pos (14UL)
9420 #define SCUPM_SYS_IRQ_CTRL_VREF5V_OVL_IE_Msk (0x4000UL)
9421 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Pos (13UL)
9422 #define SCUPM_SYS_IRQ_CTRL_VREF5V_UPTH_IE_Msk (0x2000UL)
9423 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Pos (12UL)
9424 #define SCUPM_SYS_IRQ_CTRL_VREF5V_LOWTH_IE_Msk (0x1000UL)
9425 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Pos (11UL)
9426 #define SCUPM_SYS_IRQ_CTRL_REFBG_UPTHWARN_IE_Msk (0x800UL)
9427 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Pos (10UL)
9428 #define SCUPM_SYS_IRQ_CTRL_REFBG_LOTHWARN_IE_Msk (0x400UL)
9429 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Pos (9UL)
9430 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Msk (0x200UL)
9431 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Pos (8UL)
9432 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Msk (0x100UL)
9433 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Pos (7UL)
9434 #define SCUPM_SYS_IRQ_CTRL_PMU_OT_IE_Msk (0x80UL)
9435 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Pos (6UL)
9436 #define SCUPM_SYS_IRQ_CTRL_PMU_OTWARN_IE_Msk (0x40UL)
9437 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Pos (2UL)
9438 #define SCUPM_SYS_IRQ_CTRL_LIN_TMOUT_IE_Msk (0x4UL)
9439 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Pos (1UL)
9440 #define SCUPM_SYS_IRQ_CTRL_LIN_OT_IE_Msk (0x2UL)
9441 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Pos (0UL)
9442 #define SCUPM_SYS_IRQ_CTRL_LIN_OC_IE_Msk (0x1UL)
9443 /* ======================================================== SYS_IS ========================================================= */
9444 #define SCUPM_SYS_IS_ADC4_EOC_IS_Pos (23UL)
9445 #define SCUPM_SYS_IS_ADC4_EOC_IS_Msk (0x800000UL)
9446 #define SCUPM_SYS_IS_ADC3_EOC_IS_Pos (22UL)
9447 #define SCUPM_SYS_IS_ADC3_EOC_IS_Msk (0x400000UL)
9448 #define SCUPM_SYS_IS_ADC2_ESM_IS_Pos (15UL)
9449 #define SCUPM_SYS_IS_ADC2_ESM_IS_Msk (0x8000UL)
9450 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Pos (14UL)
9451 #define SCUPM_SYS_IS_VREF5V_OVL_IS_Msk (0x4000UL)
9452 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Pos (13UL)
9453 #define SCUPM_SYS_IS_VREF5V_UPTH_IS_Msk (0x2000UL)
9454 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Pos (12UL)
9455 #define SCUPM_SYS_IS_VREF5V_LOWTH_IS_Msk (0x1000UL)
9456 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Pos (11UL)
9457 #define SCUPM_SYS_IS_REFBG_UPTHWARN_IS_Msk (0x800UL)
9458 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Pos (10UL)
9459 #define SCUPM_SYS_IS_REFBG_LOTHWARN_IS_Msk (0x400UL)
9460 #define SCUPM_SYS_IS_SYS_OT_IS_Pos (9UL)
9461 #define SCUPM_SYS_IS_SYS_OT_IS_Msk (0x200UL)
9462 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Pos (8UL)
9463 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Msk (0x100UL)
9464 #define SCUPM_SYS_IS_PMU_OT_IS_Pos (7UL)
9465 #define SCUPM_SYS_IS_PMU_OT_IS_Msk (0x80UL)
9466 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Pos (6UL)
9467 #define SCUPM_SYS_IS_PMU_OTWARN_IS_Msk (0x40UL)
9468 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Pos (2UL)
9469 #define SCUPM_SYS_IS_LIN_TMOUT_IS_Msk (0x4UL)
9470 #define SCUPM_SYS_IS_LIN_OT_IS_Pos (1UL)
9471 #define SCUPM_SYS_IS_LIN_OT_IS_Msk (0x2UL)
9472 #define SCUPM_SYS_IS_LIN_OC_IS_Pos (0UL)
9473 #define SCUPM_SYS_IS_LIN_OC_IS_Msk (0x1UL)
9474 /* ======================================================= SYS_ISCLR ======================================================= */
9475 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Pos (23UL)
9476 #define SCUPM_SYS_ISCLR_ADC4_EOC_ICLR_Msk (0x800000UL)
9477 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Pos (22UL)
9478 #define SCUPM_SYS_ISCLR_ADC3_EOC_ICLR_Msk (0x400000UL)
9479 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Pos (15UL)
9480 #define SCUPM_SYS_ISCLR_ADC2_ESM_ICLR_Msk (0x8000UL)
9481 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Pos (14UL)
9482 #define SCUPM_SYS_ISCLR_VREF5V_OVL_ICLR_Msk (0x4000UL)
9483 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Pos (13UL)
9484 #define SCUPM_SYS_ISCLR_VREF5V_UPTH_ICLR_Msk (0x2000UL)
9485 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Pos (12UL)
9486 #define SCUPM_SYS_ISCLR_VREF5V_LOWTH_ICLR_Msk (0x1000UL)
9487 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Pos (11UL)
9488 #define SCUPM_SYS_ISCLR_REFBG_UPTHWARN_ICLR_Msk (0x800UL)
9489 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Pos (10UL)
9490 #define SCUPM_SYS_ISCLR_REFBG_LOTHWARN_ICLR_Msk (0x400UL)
9491 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Pos (9UL)
9492 #define SCUPM_SYS_ISCLR_SYS_OT_ICLR_Msk (0x200UL)
9493 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Pos (8UL)
9494 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ICLR_Msk (0x100UL)
9495 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Pos (7UL)
9496 #define SCUPM_SYS_ISCLR_PMU_OT_ICLR_Msk (0x80UL)
9497 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Pos (6UL)
9498 #define SCUPM_SYS_ISCLR_PMU_OTWARN_ICLR_Msk (0x40UL)
9499 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Pos (2UL)
9500 #define SCUPM_SYS_ISCLR_LIN_TMOUT_ICLR_Msk (0x4UL)
9501 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Pos (1UL)
9502 #define SCUPM_SYS_ISCLR_LIN_OT_ICLR_Msk (0x2UL)
9503 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Pos (0UL)
9504 #define SCUPM_SYS_ISCLR_LIN_OC_ICLR_Msk (0x1UL)
9505 /* ================================================== SYS_SUPPLY_IRQ_CLR =================================================== */
9506 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Pos (23UL)
9507 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SCLR_Msk (0x800000UL)
9508 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Pos (22UL)
9509 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SCLR_Msk (0x400000UL)
9510 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Pos (21UL)
9511 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SCLR_Msk (0x200000UL)
9512 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_SCLR_Pos (20UL)
9513 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_SCLR_Msk (0x100000UL)
9514 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Pos (19UL)
9515 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SCLR_Msk (0x80000UL)
9516 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Pos (18UL)
9517 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SCLR_Msk (0x40000UL)
9518 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Pos (17UL)
9519 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SCLR_Msk (0x20000UL)
9520 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_SCLR_Pos (16UL)
9521 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_SCLR_Msk (0x10000UL)
9522 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Pos (7UL)
9523 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ICLR_Msk (0x80UL)
9524 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Pos (6UL)
9525 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ICLR_Msk (0x40UL)
9526 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Pos (5UL)
9527 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ICLR_Msk (0x20UL)
9528 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_ICLR_Pos (4UL)
9529 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_OV_ICLR_Msk (0x10UL)
9530 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Pos (3UL)
9531 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ICLR_Msk (0x8UL)
9532 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Pos (2UL)
9533 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ICLR_Msk (0x4UL)
9534 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Pos (1UL)
9535 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ICLR_Msk (0x2UL)
9536 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_ICLR_Pos (0UL)
9537 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VBAT_UV_ICLR_Msk (0x1UL)
9538 /* ================================================== SYS_SUPPLY_IRQ_CTRL ================================================== */
9539 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Pos (7UL)
9540 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Msk (0x80UL)
9541 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Pos (6UL)
9542 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Msk (0x40UL)
9543 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Pos (5UL)
9544 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Msk (0x20UL)
9545 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_OV_IE_Pos (4UL)
9546 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_OV_IE_Msk (0x10UL)
9547 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Pos (3UL)
9548 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Msk (0x8UL)
9549 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Pos (2UL)
9550 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Msk (0x4UL)
9551 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Pos (1UL)
9552 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Msk (0x2UL)
9553 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_UV_IE_Pos (0UL)
9554 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VBAT_UV_IE_Msk (0x1UL)
9555 /* ================================================== SYS_SUPPLY_IRQ_STS =================================================== */
9556 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Pos (23UL)
9557 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Msk (0x800000UL)
9558 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Pos (22UL)
9559 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Msk (0x400000UL)
9560 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Pos (21UL)
9561 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Msk (0x200000UL)
9562 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_STS_Pos (20UL)
9563 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_STS_Msk (0x100000UL)
9564 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Pos (19UL)
9565 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Msk (0x80000UL)
9566 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Pos (18UL)
9567 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Msk (0x40000UL)
9568 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Pos (17UL)
9569 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Msk (0x20000UL)
9570 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_STS_Pos (16UL)
9571 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_STS_Msk (0x10000UL)
9572 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Pos (7UL)
9573 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Msk (0x80UL)
9574 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Pos (6UL)
9575 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Msk (0x40UL)
9576 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Pos (5UL)
9577 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Msk (0x20UL)
9578 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_IS_Pos (4UL)
9579 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_OV_IS_Msk (0x10UL)
9580 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Pos (3UL)
9581 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Msk (0x8UL)
9582 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Pos (2UL)
9583 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Msk (0x4UL)
9584 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Pos (1UL)
9585 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Msk (0x2UL)
9586 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_IS_Pos (0UL)
9587 #define SCUPM_SYS_SUPPLY_IRQ_STS_VBAT_UV_IS_Msk (0x1UL)
9588 /* ======================================================= WDT1_TRIG ======================================================= */
9589 #define SCUPM_WDT1_TRIG_SOWCONF_Pos (6UL)
9590 #define SCUPM_WDT1_TRIG_SOWCONF_Msk (0xc0UL)
9591 #define SCUPM_WDT1_TRIG_WDP_SEL_Pos (0UL)
9592 #define SCUPM_WDT1_TRIG_WDP_SEL_Msk (0x3fUL)
9595 /* =========================================================================================================================== */
9596 /* ================ SSC1 ================ */
9597 /* =========================================================================================================================== */
9598 
9599 /* ========================================================== BR =========================================================== */
9600 #define SSC1_BR_BR_VALUE_Pos (0UL)
9601 #define SSC1_BR_BR_VALUE_Msk (0xffffUL)
9602 /* ========================================================== CON ========================================================== */
9603 #define SSC1_CON_BC_Pos (0UL)
9604 #define SSC1_CON_BC_Msk (0xfUL)
9605 #define SSC1_CON_TE_Pos (8UL)
9606 #define SSC1_CON_TE_Msk (0x100UL)
9607 #define SSC1_CON_RE_Pos (9UL)
9608 #define SSC1_CON_RE_Msk (0x200UL)
9609 #define SSC1_CON_PE_Pos (10UL)
9610 #define SSC1_CON_PE_Msk (0x400UL)
9611 #define SSC1_CON_BE_Pos (11UL)
9612 #define SSC1_CON_BE_Msk (0x800UL)
9613 #define SSC1_CON_BSY_Pos (12UL)
9614 #define SSC1_CON_BSY_Msk (0x1000UL)
9615 #define SSC1_CON_MS_Pos (14UL)
9616 #define SSC1_CON_MS_Msk (0x4000UL)
9617 #define SSC1_CON_EN_Pos (15UL)
9618 #define SSC1_CON_EN_Msk (0x8000UL)
9619 /* ======================================================== ISRCLR ========================================================= */
9620 #define SSC1_ISRCLR_TECLR_Pos (8UL)
9621 #define SSC1_ISRCLR_TECLR_Msk (0x100UL)
9622 #define SSC1_ISRCLR_RECLR_Pos (9UL)
9623 #define SSC1_ISRCLR_RECLR_Msk (0x200UL)
9624 #define SSC1_ISRCLR_PECLR_Pos (10UL)
9625 #define SSC1_ISRCLR_PECLR_Msk (0x400UL)
9626 #define SSC1_ISRCLR_BECLR_Pos (11UL)
9627 #define SSC1_ISRCLR_BECLR_Msk (0x800UL)
9628 /* ========================================================= PISEL ========================================================= */
9629 #define SSC1_PISEL_MIS_0_Pos (0UL)
9630 #define SSC1_PISEL_MIS_0_Msk (0x1UL)
9631 #define SSC1_PISEL_SIS_Pos (1UL)
9632 #define SSC1_PISEL_SIS_Msk (0x2UL)
9633 #define SSC1_PISEL_CIS_Pos (2UL)
9634 #define SSC1_PISEL_CIS_Msk (0x4UL)
9635 #define SSC1_PISEL_MIS_1_Pos (3UL)
9636 #define SSC1_PISEL_MIS_1_Msk (0x8UL)
9637 /* ========================================================== RB =========================================================== */
9638 #define SSC1_RB_RB_VALUE_Pos (0UL)
9639 #define SSC1_RB_RB_VALUE_Msk (0xffffUL)
9640 /* ========================================================== TB =========================================================== */
9641 #define SSC1_TB_TB_VALUE_Pos (0UL)
9642 #define SSC1_TB_TB_VALUE_Msk (0xffffUL)
9645 /* =========================================================================================================================== */
9646 /* ================ SSC2 ================ */
9647 /* =========================================================================================================================== */
9648 
9649 /* ========================================================== BR =========================================================== */
9650 #define SSC2_BR_BR_VALUE_Pos (0UL)
9651 #define SSC2_BR_BR_VALUE_Msk (0xffffUL)
9652 /* ========================================================== CON ========================================================== */
9653 #define SSC2_CON_BC_Pos (0UL)
9654 #define SSC2_CON_BC_Msk (0xfUL)
9655 #define SSC2_CON_TE_Pos (8UL)
9656 #define SSC2_CON_TE_Msk (0x100UL)
9657 #define SSC2_CON_RE_Pos (9UL)
9658 #define SSC2_CON_RE_Msk (0x200UL)
9659 #define SSC2_CON_PE_Pos (10UL)
9660 #define SSC2_CON_PE_Msk (0x400UL)
9661 #define SSC2_CON_BE_Pos (11UL)
9662 #define SSC2_CON_BE_Msk (0x800UL)
9663 #define SSC2_CON_BSY_Pos (12UL)
9664 #define SSC2_CON_BSY_Msk (0x1000UL)
9665 #define SSC2_CON_MS_Pos (14UL)
9666 #define SSC2_CON_MS_Msk (0x4000UL)
9667 #define SSC2_CON_EN_Pos (15UL)
9668 #define SSC2_CON_EN_Msk (0x8000UL)
9669 /* ======================================================== ISRCLR ========================================================= */
9670 #define SSC2_ISRCLR_TECLR_Pos (8UL)
9671 #define SSC2_ISRCLR_TECLR_Msk (0x100UL)
9672 #define SSC2_ISRCLR_RECLR_Pos (9UL)
9673 #define SSC2_ISRCLR_RECLR_Msk (0x200UL)
9674 #define SSC2_ISRCLR_PECLR_Pos (10UL)
9675 #define SSC2_ISRCLR_PECLR_Msk (0x400UL)
9676 #define SSC2_ISRCLR_BECLR_Pos (11UL)
9677 #define SSC2_ISRCLR_BECLR_Msk (0x800UL)
9678 /* ========================================================= PISEL ========================================================= */
9679 #define SSC2_PISEL_MIS_0_Pos (0UL)
9680 #define SSC2_PISEL_MIS_0_Msk (0x1UL)
9681 #define SSC2_PISEL_SIS_Pos (1UL)
9682 #define SSC2_PISEL_SIS_Msk (0x2UL)
9683 #define SSC2_PISEL_CIS_Pos (2UL)
9684 #define SSC2_PISEL_CIS_Msk (0x4UL)
9685 #define SSC2_PISEL_MIS_1_Pos (3UL)
9686 #define SSC2_PISEL_MIS_1_Msk (0x8UL)
9687 /* ========================================================== RB =========================================================== */
9688 #define SSC2_RB_RB_VALUE_Pos (0UL)
9689 #define SSC2_RB_RB_VALUE_Msk (0xffffUL)
9690 /* ========================================================== TB =========================================================== */
9691 #define SSC2_TB_TB_VALUE_Pos (0UL)
9692 #define SSC2_TB_TB_VALUE_Msk (0xffffUL)
9695 /* =========================================================================================================================== */
9696 /* ================ TIMER2 ================ */
9697 /* =========================================================================================================================== */
9698 
9699 /* ========================================================= RC2H ========================================================== */
9700 #define TIMER2_RC2H_RC2_Pos (0UL)
9701 #define TIMER2_RC2H_RC2_Msk (0xffUL)
9702 /* ========================================================= RC2L ========================================================== */
9703 #define TIMER2_RC2L_RC2_Pos (0UL)
9704 #define TIMER2_RC2L_RC2_Msk (0xffUL)
9705 /* ========================================================= T2CON ========================================================= */
9706 #define TIMER2_T2CON_CP_RL2_Pos (0UL)
9707 #define TIMER2_T2CON_CP_RL2_Msk (0x1UL)
9708 #define TIMER2_T2CON_C_T2_Pos (1UL)
9709 #define TIMER2_T2CON_C_T2_Msk (0x2UL)
9710 #define TIMER2_T2CON_TR2_Pos (2UL)
9711 #define TIMER2_T2CON_TR2_Msk (0x4UL)
9712 #define TIMER2_T2CON_EXEN2_Pos (3UL)
9713 #define TIMER2_T2CON_EXEN2_Msk (0x8UL)
9714 #define TIMER2_T2CON_EXF2_Pos (6UL)
9715 #define TIMER2_T2CON_EXF2_Msk (0x40UL)
9716 #define TIMER2_T2CON_TF2_Pos (7UL)
9717 #define TIMER2_T2CON_TF2_Msk (0x80UL)
9718 /* ======================================================== T2CON1 ========================================================= */
9719 #define TIMER2_T2CON1_EXF2EN_Pos (0UL)
9720 #define TIMER2_T2CON1_EXF2EN_Msk (0x1UL)
9721 #define TIMER2_T2CON1_TF2EN_Pos (1UL)
9722 #define TIMER2_T2CON1_TF2EN_Msk (0x2UL)
9723 /* ========================================================== T2H ========================================================== */
9724 #define TIMER2_T2H_T2H_Pos (0UL)
9725 #define TIMER2_T2H_T2H_Msk (0xffUL)
9726 /* ======================================================== T2ICLR ========================================================= */
9727 #define TIMER2_T2ICLR_EXF2CLR_Pos (6UL)
9728 #define TIMER2_T2ICLR_EXF2CLR_Msk (0x40UL)
9729 #define TIMER2_T2ICLR_TF2CLR_Pos (7UL)
9730 #define TIMER2_T2ICLR_TF2CLR_Msk (0x80UL)
9731 /* ========================================================== T2L ========================================================== */
9732 #define TIMER2_T2L_T2L_Pos (0UL)
9733 #define TIMER2_T2L_T2L_Msk (0xffUL)
9734 /* ========================================================= T2MOD ========================================================= */
9735 #define TIMER2_T2MOD_DCEN_Pos (0UL)
9736 #define TIMER2_T2MOD_DCEN_Msk (0x1UL)
9737 #define TIMER2_T2MOD_T2PRE_Pos (1UL)
9738 #define TIMER2_T2MOD_T2PRE_Msk (0xeUL)
9739 #define TIMER2_T2MOD_PREN_Pos (4UL)
9740 #define TIMER2_T2MOD_PREN_Msk (0x10UL)
9741 #define TIMER2_T2MOD_EDGESEL_Pos (5UL)
9742 #define TIMER2_T2MOD_EDGESEL_Msk (0x20UL)
9743 #define TIMER2_T2MOD_T2RHEN_Pos (6UL)
9744 #define TIMER2_T2MOD_T2RHEN_Msk (0x40UL)
9745 #define TIMER2_T2MOD_T2REGS_Pos (7UL)
9746 #define TIMER2_T2MOD_T2REGS_Msk (0x80UL)
9749 /* =========================================================================================================================== */
9750 /* ================ TIMER21 ================ */
9751 /* =========================================================================================================================== */
9752 
9753 /* ========================================================= RC2H ========================================================== */
9754 #define TIMER21_RC2H_RC2_Pos (0UL)
9755 #define TIMER21_RC2H_RC2_Msk (0xffUL)
9756 /* ========================================================= RC2L ========================================================== */
9757 #define TIMER21_RC2L_RC2_Pos (0UL)
9758 #define TIMER21_RC2L_RC2_Msk (0xffUL)
9759 /* ========================================================= T2CON ========================================================= */
9760 #define TIMER21_T2CON_CP_RL2_Pos (0UL)
9761 #define TIMER21_T2CON_CP_RL2_Msk (0x1UL)
9762 #define TIMER21_T2CON_C_T2_Pos (1UL)
9763 #define TIMER21_T2CON_C_T2_Msk (0x2UL)
9764 #define TIMER21_T2CON_TR2_Pos (2UL)
9765 #define TIMER21_T2CON_TR2_Msk (0x4UL)
9766 #define TIMER21_T2CON_EXEN2_Pos (3UL)
9767 #define TIMER21_T2CON_EXEN2_Msk (0x8UL)
9768 #define TIMER21_T2CON_EXF2_Pos (6UL)
9769 #define TIMER21_T2CON_EXF2_Msk (0x40UL)
9770 #define TIMER21_T2CON_TF2_Pos (7UL)
9771 #define TIMER21_T2CON_TF2_Msk (0x80UL)
9772 /* ======================================================== T2CON1 ========================================================= */
9773 #define TIMER21_T2CON1_EXF2EN_Pos (0UL)
9774 #define TIMER21_T2CON1_EXF2EN_Msk (0x1UL)
9775 #define TIMER21_T2CON1_TF2EN_Pos (1UL)
9776 #define TIMER21_T2CON1_TF2EN_Msk (0x2UL)
9777 /* ========================================================== T2H ========================================================== */
9778 #define TIMER21_T2H_T2H_Pos (0UL)
9779 #define TIMER21_T2H_T2H_Msk (0xffUL)
9780 /* ======================================================== T2ICLR ========================================================= */
9781 #define TIMER21_T2ICLR_EXF2CLR_Pos (6UL)
9782 #define TIMER21_T2ICLR_EXF2CLR_Msk (0x40UL)
9783 #define TIMER21_T2ICLR_TF2CLR_Pos (7UL)
9784 #define TIMER21_T2ICLR_TF2CLR_Msk (0x80UL)
9785 /* ========================================================== T2L ========================================================== */
9786 #define TIMER21_T2L_T2L_Pos (0UL)
9787 #define TIMER21_T2L_T2L_Msk (0xffUL)
9788 /* ========================================================= T2MOD ========================================================= */
9789 #define TIMER21_T2MOD_DCEN_Pos (0UL)
9790 #define TIMER21_T2MOD_DCEN_Msk (0x1UL)
9791 #define TIMER21_T2MOD_T2PRE_Pos (1UL)
9792 #define TIMER21_T2MOD_T2PRE_Msk (0xeUL)
9793 #define TIMER21_T2MOD_PREN_Pos (4UL)
9794 #define TIMER21_T2MOD_PREN_Msk (0x10UL)
9795 #define TIMER21_T2MOD_EDGESEL_Pos (5UL)
9796 #define TIMER21_T2MOD_EDGESEL_Msk (0x20UL)
9797 #define TIMER21_T2MOD_T2RHEN_Pos (6UL)
9798 #define TIMER21_T2MOD_T2RHEN_Msk (0x40UL)
9799 #define TIMER21_T2MOD_T2REGS_Pos (7UL)
9800 #define TIMER21_T2MOD_T2REGS_Msk (0x80UL)
9803 /* =========================================================================================================================== */
9804 /* ================ TIMER3 ================ */
9805 /* =========================================================================================================================== */
9806 
9807 /* ========================================================== CMP ========================================================== */
9808 #define TIMER3_CMP_HI_Pos (8UL)
9809 #define TIMER3_CMP_HI_Msk (0xff00UL)
9810 #define TIMER3_CMP_LO_Pos (0UL)
9811 #define TIMER3_CMP_LO_Msk (0xffUL)
9812 /* ========================================================== CNT ========================================================== */
9813 #define TIMER3_CNT_HI_Pos (8UL)
9814 #define TIMER3_CNT_HI_Msk (0xff00UL)
9815 #define TIMER3_CNT_LO_Pos (0UL)
9816 #define TIMER3_CNT_LO_Msk (0xffUL)
9817 /* ========================================================= CTRL ========================================================== */
9818 #define TIMER3_CTRL_T3H_OVF_IE_Pos (9UL)
9819 #define TIMER3_CTRL_T3H_OVF_IE_Msk (0x200UL)
9820 #define TIMER3_CTRL_T3L_OVF_IE_Pos (8UL)
9821 #define TIMER3_CTRL_T3L_OVF_IE_Msk (0x100UL)
9822 #define TIMER3_CTRL_T3L_OVF_STS_Pos (7UL)
9823 #define TIMER3_CTRL_T3L_OVF_STS_Msk (0x80UL)
9824 #define TIMER3_CTRL_TR3L_Pos (6UL)
9825 #define TIMER3_CTRL_TR3L_Msk (0x40UL)
9826 #define TIMER3_CTRL_T3H_OVF_STS_Pos (5UL)
9827 #define TIMER3_CTRL_T3H_OVF_STS_Msk (0x20UL)
9828 #define TIMER3_CTRL_TR3H_Pos (4UL)
9829 #define TIMER3_CTRL_TR3H_Msk (0x10UL)
9830 #define TIMER3_CTRL_CNT_RDY_Pos (3UL)
9831 #define TIMER3_CTRL_CNT_RDY_Msk (0x8UL)
9832 #define TIMER3_CTRL_T3_RD_REQ_CONF_Pos (2UL)
9833 #define TIMER3_CTRL_T3_RD_REQ_CONF_Msk (0x4UL)
9834 #define TIMER3_CTRL_T3_RD_REQ_Pos (1UL)
9835 #define TIMER3_CTRL_T3_RD_REQ_Msk (0x2UL)
9836 #define TIMER3_CTRL_T3_PD_N_Pos (0UL)
9837 #define TIMER3_CTRL_T3_PD_N_Msk (0x1UL)
9838 /* ======================================================== ISRCLR ========================================================= */
9839 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Pos (7UL)
9840 #define TIMER3_ISRCLR_T3L_OVF_ICLR_Msk (0x80UL)
9841 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Pos (5UL)
9842 #define TIMER3_ISRCLR_T3H_OVF_ICLR_Msk (0x20UL)
9843 /* ======================================================= MODE_CONF ======================================================= */
9844 #define TIMER3_MODE_CONF_T3_SUBM_Pos (6UL)
9845 #define TIMER3_MODE_CONF_T3_SUBM_Msk (0xc0UL)
9846 #define TIMER3_MODE_CONF_T3M_Pos (0UL)
9847 #define TIMER3_MODE_CONF_T3M_Msk (0x3UL)
9848 /* ===================================================== T3_TRIGG_CTRL ===================================================== */
9849 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Pos (6UL)
9850 #define TIMER3_T3_TRIGG_CTRL_RETRIG_Msk (0x40UL)
9851 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Pos (4UL)
9852 #define TIMER3_T3_TRIGG_CTRL_T3_RES_CONF_Msk (0x30UL)
9853 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Pos (0UL)
9854 #define TIMER3_T3_TRIGG_CTRL_T3_TRIGG_INP_SEL_Msk (0x7UL)
9857 /* =========================================================================================================================== */
9858 /* ================ UART1 ================ */
9859 /* =========================================================================================================================== */
9860 
9861 /* ========================================================= SBUF ========================================================== */
9862 #define UART1_SBUF_VAL_Pos (0UL)
9863 #define UART1_SBUF_VAL_Msk (0xffUL)
9864 /* ========================================================= SCON ========================================================== */
9865 #define UART1_SCON_RI_Pos (0UL)
9866 #define UART1_SCON_RI_Msk (0x1UL)
9867 #define UART1_SCON_TI_Pos (1UL)
9868 #define UART1_SCON_TI_Msk (0x2UL)
9869 #define UART1_SCON_RB8_Pos (2UL)
9870 #define UART1_SCON_RB8_Msk (0x4UL)
9871 #define UART1_SCON_TB8_Pos (3UL)
9872 #define UART1_SCON_TB8_Msk (0x8UL)
9873 #define UART1_SCON_REN_Pos (4UL)
9874 #define UART1_SCON_REN_Msk (0x10UL)
9875 #define UART1_SCON_SM2_Pos (5UL)
9876 #define UART1_SCON_SM2_Msk (0x20UL)
9877 #define UART1_SCON_SM1_Pos (6UL)
9878 #define UART1_SCON_SM1_Msk (0x40UL)
9879 #define UART1_SCON_SM0_Pos (7UL)
9880 #define UART1_SCON_SM0_Msk (0x80UL)
9881 /* ======================================================== SCONCLR ======================================================== */
9882 #define UART1_SCONCLR_RICLR_Pos (0UL)
9883 #define UART1_SCONCLR_RICLR_Msk (0x1UL)
9884 #define UART1_SCONCLR_TICLR_Pos (1UL)
9885 #define UART1_SCONCLR_TICLR_Msk (0x2UL)
9888 /* =========================================================================================================================== */
9889 /* ================ UART2 ================ */
9890 /* =========================================================================================================================== */
9891 
9892 /* ========================================================= SBUF ========================================================== */
9893 #define UART2_SBUF_VAL_Pos (0UL)
9894 #define UART2_SBUF_VAL_Msk (0xffUL)
9895 /* ========================================================= SCON ========================================================== */
9896 #define UART2_SCON_RI_Pos (0UL)
9897 #define UART2_SCON_RI_Msk (0x1UL)
9898 #define UART2_SCON_TI_Pos (1UL)
9899 #define UART2_SCON_TI_Msk (0x2UL)
9900 #define UART2_SCON_RB8_Pos (2UL)
9901 #define UART2_SCON_RB8_Msk (0x4UL)
9902 #define UART2_SCON_TB8_Pos (3UL)
9903 #define UART2_SCON_TB8_Msk (0x8UL)
9904 #define UART2_SCON_REN_Pos (4UL)
9905 #define UART2_SCON_REN_Msk (0x10UL)
9906 #define UART2_SCON_SM2_Pos (5UL)
9907 #define UART2_SCON_SM2_Msk (0x20UL)
9908 #define UART2_SCON_SM1_Pos (6UL)
9909 #define UART2_SCON_SM1_Msk (0x40UL)
9910 #define UART2_SCON_SM0_Pos (7UL)
9911 #define UART2_SCON_SM0_Msk (0x80UL)
9912 /* ======================================================== SCONCLR ======================================================== */
9913 #define UART2_SCONCLR_RICLR_Pos (0UL)
9914 #define UART2_SCONCLR_RICLR_Msk (0x1UL)
9915 #define UART2_SCONCLR_TICLR_Pos (1UL)
9916 #define UART2_SCONCLR_TICLR_Msk (0x2UL) /* End of group PosMask_peripherals */
9919 
9920 #ifdef __cplusplus
9921 }
9922 #endif
9923 
9924 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
9925  #pragma clang diagnostic pop
9926 #endif
9927 
9928 #endif /* TLE986x_H */
9929 
9930  /* End of group TLE986x */
9932  /* End of group Infineon */
PMU_Type::GPIO0_CYC_4
__IOM uint8_t GPIO0_CYC_4
Definition: tle986x.h:3495
MF_Type::P2_4_ADC_SEL
__IOM uint32_t P2_4_ADC_SEL
Definition: tle986x.h:3032
SCU_Type::GPT12_DMAEN
__IOM uint8_t GPT12_DMAEN
Definition: tle986x.h:4946
PMU_Type::GPIO1_RI_4
__IOM uint8_t GPIO1_RI_4
Definition: tle986x.h:3510
SCUPM_Type::ADC4_EOC_IE
__IOM uint32_t ADC4_EOC_IE
Definition: tle986x.h:5246
CPU_Type::UNSTKERR
__IOM uint32_t UNSTKERR
Definition: tle986x.h:2414
BDRV_Type::DRV_ON_I_1
__IOM uint32_t DRV_ON_I_1
Definition: tle986x.h:1347
CCU6_Type::RESERVED29
__IM uint16_t RESERVED29
Definition: tle986x.h:1939
SCUPM_Type::VDD1V5_OV_IS
__IM uint32_t VDD1V5_OV_IS
Definition: tle986x.h:5164
SCU_Type::T3
__IM uint8_t T3
Definition: tle986x.h:4888
SCU_Type::ADC1_DIS
__IOM uint8_t ADC1_DIS
Definition: tle986x.h:4225
CCU6_Type::DTRES
__OM uint16_t DTRES
Definition: tle986x.h:1461
BDRV_Type::VTHVCP9V_TRIM
__IOM uint32_t VTHVCP9V_TRIM
Definition: tle986x.h:1408
SCU_Type::NVMPROTSTSL_1
__IOM uint8_t NVMPROTSTSL_1
Definition: tle986x.h:4650
DMA_Type::MASTER_ENABLE
__OM uint32_t MASTER_ENABLE
Definition: tle986x.h:2559
TIMER2x_Type::CP_RL2
__IOM uint8_t CP_RL2
Definition: tle986x.h:5684
CCU6_Type::T13EXT
__IOM uint16_t T13EXT
Definition: tle986x.h:1925
SCUPM_Type::CLKLOSS_SD_DIS
__IOM uint32_t CLKLOSS_SD_DIS
Definition: tle986x.h:5266
SCUPM_Type::RESERVED
__IM uint32_t RESERVED
Definition: tle986x.h:5062
SCU_Type::SSC2C
__OM uint8_t SSC2C
Definition: tle986x.h:4979
SCU_Type::TIREN1
__IOM uint8_t TIREN1
Definition: tle986x.h:4051
ADC2_Type::HYST_LO_CH0
__IOM uint32_t HYST_LO_CH0
Definition: tle986x.h:1037
SCU_Type::TLEN
__IOM uint8_t TLEN
Definition: tle986x.h:4496
CPU_Type::Int_CCU6SR3
__IOM uint32_t Int_CCU6SR3
Definition: tle986x.h:2065
SCUPM_Type::VS_UV_STS
__IM uint32_t VS_UV_STS
Definition: tle986x.h:5167
__IOM
#define __IOM
Definition: tle986x.h:149
SCU_Type::CH5C
__OM uint8_t CH5C
Definition: tle986x.h:4961
GPT12E_Type::RESERVED5
__IM uint16_t RESERVED5
Definition: tle986x.h:2877
CCU6_Type::RESERVED6
__IM uint16_t RESERVED6
Definition: tle986x.h:1569
EXINT1_Int
Definition: tle986x.h:116
PMU_Type::DATA4
__IOM uint8_t DATA4
Definition: tle986x.h:3439
PMU_Type::GPIO0_RI_3
__IOM uint8_t GPIO0_RI_3
Definition: tle986x.h:3464
SCU_Type::RDBE
__IM uint8_t RDBE
Definition: tle986x.h:4622
SCU_Type::TIEN1
__IOM uint8_t TIEN1
Definition: tle986x.h:4055
SSC2_Type::TE
__IM uint16_t TE
Definition: tle986x.h:5604
SCUPM_Type::LIN_TMOUT_IE
__IOM uint32_t LIN_TMOUT_IE
Definition: tle986x.h:5228
ADC2_Type::CNT_UP_CH7
__IM uint32_t CNT_UP_CH7
Definition: tle986x.h:1127
SCU_Type::URIOS1
__IOM uint8_t URIOS1
Definition: tle986x.h:4512
CCU6_Type::STRPF
__OM uint16_t STRPF
Definition: tle986x.h:1766
SCU_Type::T21EXCON
__IOM uint8_t T21EXCON
Definition: tle986x.h:4527
PORT_Type::P3_P2
__IOM uint8_t P3_P2
Definition: tle986x.h:3847
ADC2_Type::OUT_CH1
__IM uint32_t OUT_CH1
Definition: tle986x.h:841
PORT_Type::reg
__IOM uint8_t reg
Definition: tle986x.h:3573
BDRV_Type::ICHARGEDIV2_N
__IOM uint32_t ICHARGEDIV2_N
Definition: tle986x.h:1302
CCU6_Type::T12RES
__OM uint16_t T12RES
Definition: tle986x.h:1460
ADC2_Type::Ch0_EN
__IOM uint32_t Ch0_EN
Definition: tle986x.h:931
SCUPM_Type::VDD5V_OV_IS
__IM uint32_t VDD5V_OV_IS
Definition: tle986x.h:5163
BDRV_Type::DRV_CCPTIMMUL
__IOM uint32_t DRV_CCPTIMMUL
Definition: tle986x.h:1360
PMU_Type::CNF_GPIO_FT
__IOM uint8_t CNF_GPIO_FT
Definition: tle986x.h:3384
DMA_Type::CHNL_USEBURST_CLR
__OM uint32_t CHNL_USEBURST_CLR
Definition: tle986x.h:2630
CPU_Type::REVISION
__IM uint32_t REVISION
Definition: tle986x.h:2241
GPT12E_Type::uint16_t
__IM uint16_t
Definition: tle986x.h:2805
GPT12E_Type::T2UD
__IOM uint16_t T2UD
Definition: tle986x.h:2802
CCU6_Type::RCC62R
__OM uint16_t RCC62R
Definition: tle986x.h:1504
SCU_Type::EXINT2F
__IM uint8_t EXINT2F
Definition: tle986x.h:3896
CPU_Type::NOREF
__IM uint32_t NOREF
Definition: tle986x.h:2047
SCUPM_Type::HS2_DS_IS
__IM uint32_t HS2_DS_IS
Definition: tle986x.h:5335
CCU6_Type::T12CLK
__IOM uint16_t T12CLK
Definition: tle986x.h:1639
BDRV_Type::DLY_DIAG_TIM
__IM uint32_t DLY_DIAG_TIM
Definition: tle986x.h:1286
CCU6_Type::COUT62PS
__IOM uint16_t COUT62PS
Definition: tle986x.h:1971
CPU_Type::ARCHITECTURE
__IM uint32_t ARCHITECTURE
Definition: tle986x.h:2243
CCU6_Type::T12R
__IM uint16_t T12R
Definition: tle986x.h:1641
CCU6_Type::CCPOS1
__IM uint16_t CCPOS1
Definition: tle986x.h:1962
HardFault_IRQn
Definition: tle986x.h:92
SCU_Type::GPT12_T3C
__OM uint8_t GPT12_T3C
Definition: tle986x.h:5021
SCUPM_Type::AMCLK1_LOW_HYS
__IOM uint32_t AMCLK1_LOW_HYS
Definition: tle986x.h:5073
PMU_Type::E01
__IOM uint8_t E01
Definition: tle986x.h:3252
GPT12E_Type::IST6IN
__IOM uint16_t IST6IN
Definition: tle986x.h:2786
DMA_Type::CHNL_ENABLE_CLR
__OM uint32_t CHNL_ENABLE_CLR
Definition: tle986x.h:2678
SCU_Type::MONFC
__OM uint8_t MONFC
Definition: tle986x.h:4038
BDRV_Type::DRV_ON_t_3
__IOM uint32_t DRV_ON_t_3
Definition: tle986x.h:1342
PMU_Type::PMU_1V5_OVERVOLT
__IM uint8_t PMU_1V5_OVERVOLT
Definition: tle986x.h:3166
SCU_Type::CH5
__IM uint8_t CH5
Definition: tle986x.h:4838
ADC2_Type::CH8
__IM uint32_t CH8
Definition: tle986x.h:820
CPU_Type::Int_UART2
__IM uint32_t Int_UART2
Definition: tle986x.h:2173
ADC2_Type::EIM_ACTIVE
__IM uint32_t EIM_ACTIVE
Definition: tle986x.h:572
SCU_Type::TRSEQ2DY
__IM uint8_t TRSEQ2DY
Definition: tle986x.h:4854
BDRV_Type::LS1DRV_OCSDN_DIS
__IOM uint32_t LS1DRV_OCSDN_DIS
Definition: tle986x.h:1367
MON_Type::PU
__IO uint8_t PU
Definition: tle986x.h:3122
SCUPM_Type::LS1_DS_ICLR
__OM uint32_t LS1_DS_ICLR
Definition: tle986x.h:5289
CCU6_Type::INPCC62
__IOM uint16_t INPCC62
Definition: tle986x.h:1741
GPT12E_Type::T6OTL
__IOM uint16_t T6OTL
Definition: tle986x.h:2891
LIN_Type::MODE_FB
__IM uint32_t MODE_FB
Definition: tle986x.h:3000
ADC2_Type::OUT_CH4
__IM uint32_t OUT_CH4
Definition: tle986x.h:871
MF_Type
Measurement Function (MF)
Definition: tle986x.h:3020
CCU6_Type::CHE
__IM uint16_t CHE
Definition: tle986x.h:1889
PMU_Type::GPIO1_FA_3
__IOM uint8_t GPIO1_FA_3
Definition: tle986x.h:3524
MF_Type::VMON_SEN_SEL_INRANGE
__IOM uint32_t VMON_SEN_SEL_INRANGE
Definition: tle986x.h:3051
ADC1_Type::OUT_CH5
__IM uint32_t OUT_CH5
Definition: tle986x.h:386
BDRV_Type::LS1_EN
__IOM uint32_t LS1_EN
Definition: tle986x.h:1241
PMU_Type::GPIO1
__IM uint8_t GPIO1
Definition: tle986x.h:3152
ADC2_Type::SQ1
__IOM uint32_t SQ1
Definition: tle986x.h:662
GPT12E_Type::T5UD
__IOM uint16_t T5UD
Definition: tle986x.h:2867
GPT12E_Type::RESERVED6
__IM uint16_t RESERVED6
Definition: tle986x.h:2898
ADC2_Type::SQ1_int
__IM uint32_t SQ1_int
Definition: tle986x.h:709
SSC2
#define SSC2
Definition: tle986x.h:6007
SCU_Type::NVM_ADDR_ERR
__IM uint8_t NVM_ADDR_ERR
Definition: tle986x.h:4664
SCU_Type::SECTORINFO
__IOM uint8_t SECTORINFO
Definition: tle986x.h:4637
SSC1_Type::BSY
__IM uint16_t BSY
Definition: tle986x.h:5500
GPT12E_Type::CLRT3EN
__IOM uint16_t CLRT3EN
Definition: tle986x.h:2848
ADC1_Type::CH5_ICLR
__OM uint32_t CH5_ICLR
Definition: tle986x.h:528
DMA_Type::CTRL_BASE_PTR
__IOM uint32_t CTRL_BASE_PTR
Definition: tle986x.h:2572
GPT12E_Type::T2EDGE
__IOM uint16_t T2EDGE
Definition: tle986x.h:2807
SCU_Type::VCOBYP
__IOM uint8_t VCOBYP
Definition: tle986x.h:4125
CCU6_SR3_Int
Definition: tle986x.h:110
SSC2_Type::RESERVED2
__IM uint16_t RESERVED2
Definition: tle986x.h:5625
SCUPM_Type::REFBG_LOTHWARN_IE
__IOM uint32_t REFBG_LOTHWARN_IE
Definition: tle986x.h:5236
CPU_Type::STKERR
__IOM uint32_t STKERR
Definition: tle986x.h:2415
CPU_Type::STKALIGN
__IOM uint32_t STKALIGN
Definition: tle986x.h:2329
CPU_Type::Int_EXINT0
__IOM uint32_t Int_EXINT0
Definition: tle986x.h:2070
CCU6_Type::SCHE
__OM uint16_t SCHE
Definition: tle986x.h:1768
ADC34_Type::ADC3_OFS_MEAS_EN
__IOM uint32_t ADC3_OFS_MEAS_EN
Definition: tle986x.h:1187
SSC1_Type
SSC1 Module (SSC1)
Definition: tle986x.h:5459
CCU6_Type::CC62PS
__IOM uint16_t CC62PS
Definition: tle986x.h:1970
ADC2_Type::GAIN_CH1
__IOM uint32_t GAIN_CH1
Definition: tle986x.h:741
GPT12E_Type::CT3
__IOM uint16_t CT3
Definition: tle986x.h:2870
CCU6_Type::STE13
__IM uint16_t STE13
Definition: tle986x.h:1648
CPU_Type::IBUSERR
__IOM uint32_t IBUSERR
Definition: tle986x.h:2411
PMU_Type::DATA2
__IOM uint8_t DATA2
Definition: tle986x.h:3417
ADC2_Type::GAIN_CH7
__IM uint32_t GAIN_CH7
Definition: tle986x.h:780
CPU_Type::Int_GPT2
__IOM uint32_t Int_GPT2
Definition: tle986x.h:2059
ADC2_Type::SQ7
__IOM uint32_t SQ7
Definition: tle986x.h:683
ADC34_Type::ADC4_OSR
__IOM uint32_t ADC4_OSR
Definition: tle986x.h:1205
ADC1_Type::ch3
__IOM uint32_t ch3
Definition: tle986x.h:286
CCU6_Type::T12MODEN
__IOM uint16_t T12MODEN
Definition: tle986x.h:1829
ADC34_Type::ADC4_EN
__IOM uint32_t ADC4_EN
Definition: tle986x.h:1196
__IM
#define __IM
Definition: tle986x.h:143
BDRV_Type::DRV_OFF_I_1
__IOM uint32_t DRV_OFF_I_1
Definition: tle986x.h:1330
CPU_Type::MMARVALID
__IOM uint32_t MMARVALID
Definition: tle986x.h:2410
SCU_Type::NVMIE
__IOM uint8_t NVMIE
Definition: tle986x.h:4610
SCUPM_Type::HS1_DS_IE
__IOM uint32_t HS1_DS_IE
Definition: tle986x.h:5375
ADC2_Type::CNT_UP_CH4
__IOM uint32_t CNT_UP_CH4
Definition: tle986x.h:1110
GPT12E_Type::MOD_REV
__IM uint16_t MOD_REV
Definition: tle986x.h:2766
CCU6_Type::CC62ST
__IM uint16_t CC62ST
Definition: tle986x.h:1960
ADC2_Type::SQ7_int
__IM uint32_t SQ7_int
Definition: tle986x.h:715
SCUPM_Type::VDD1V5_OV_SCLR
__OM uint32_t VDD1V5_OV_SCLR
Definition: tle986x.h:5216
ADC2_Type::CNT_LO_CH7
__IM uint32_t CNT_LO_CH7
Definition: tle986x.h:1073
TIMER2x_Type::EDGESEL
__IOM uint8_t EDGESEL
Definition: tle986x.h:5704
SCUPM_Type::LS1_OC_IS
__IM uint32_t LS1_OC_IS
Definition: tle986x.h:5338
GPT12E_Type::T3OE
__IOM uint16_t T3OE
Definition: tle986x.h:2825
ADC1_Type::ch2
__IOM uint32_t ch2
Definition: tle986x.h:285
SCU_Type::T12ZM_DMAEN
__IOM uint8_t T12ZM_DMAEN
Definition: tle986x.h:4818
PMU_Type::SHORT
__IOM uint8_t SHORT
Definition: tle986x.h:3187
TIMER2x_Type::T2REGS
__IOM uint8_t T2REGS
Definition: tle986x.h:5706
CPU_Type::DACCVIOL
__IOM uint32_t DACCVIOL
Definition: tle986x.h:2405
ADC1_Type::WFR8
__IOM uint32_t WFR8
Definition: tle986x.h:329
CCU6_Type::ICC61F
__IM uint16_t ICC61F
Definition: tle986x.h:1880
MF_Type::VMON_SEN_HRESO_5V
__IOM uint32_t VMON_SEN_HRESO_5V
Definition: tle986x.h:3050
ADC2_Type::CH9
__IOM uint32_t CH9
Definition: tle986x.h:989
SSC2_Type::TB_VALUE
__IOM uint16_t TB_VALUE
Definition: tle986x.h:5622
ADC2_Type::SQ2_int
__IM uint32_t SQ2_int
Definition: tle986x.h:710
CCU6_Type::TRPM1
__IOM uint16_t TRPM1
Definition: tle986x.h:1846
SCU_Type::CH2
__IM uint8_t CH2
Definition: tle986x.h:4835
PMU_Type::LOCKUP
__IOM uint8_t LOCKUP
Definition: tle986x.h:3223
CCU6_Type::TRPEN
__IOM uint16_t TRPEN
Definition: tle986x.h:1849
ADC2_Type::HYST_LO_CH8
__IM uint32_t HYST_LO_CH8
Definition: tle986x.h:1077
GPT2_Int
Definition: tle986x.h:104
SCU_Type::CRC
__OM uint8_t CRC
Definition: tle986x.h:4909
SCU_Type::T6C
__OM uint8_t T6C
Definition: tle986x.h:4908
ADC1_Type
ADC1 Module (ADC1)
Definition: tle986x.h:185
ADC2_Type::SQ6_int
__IM uint32_t SQ6_int
Definition: tle986x.h:714
CCU6_Type::MCMEN
__IOM uint16_t MCMEN
Definition: tle986x.h:1831
SCU_Type::K1DIV
__IOM uint8_t K1DIV
Definition: tle986x.h:4139
SCU_Type::NVM_SFR_PROT_ERR
__IM uint8_t NVM_SFR_PROT_ERR
Definition: tle986x.h:4665
SCUPM_Type::HS1_OC_IS
__IM uint32_t HS1_OC_IS
Definition: tle986x.h:5340
CCU6_Type::RESERVED13
__IM uint16_t RESERVED13
Definition: tle986x.h:1662
ADC1_Type::OF0
__IM uint32_t OF0
Definition: tle986x.h:460
CPU_Type::MONITORACT
__IOM uint32_t MONITORACT
Definition: tle986x.h:2384
CCU6_Type::TRPF
__IM uint16_t TRPF
Definition: tle986x.h:1887
SSC1_Type::uint16_t
__IM uint16_t
Definition: tle986x.h:5495
CPU_Type::NONBASETHRDENA
__IOM uint32_t NONBASETHRDENA
Definition: tle986x.h:2320
CPU_Type::EXTERNAL
__IOM uint32_t EXTERNAL
Definition: tle986x.h:2452
BDRV_Type::DRV_ON_t_1
__IOM uint32_t DRV_ON_t_1
Definition: tle986x.h:1346
ADC2_Type::STS
__IM uint32_t STS
Definition: tle986x.h:612
UART_Type::RB8
__IOM uint8_t RB8
Definition: tle986x.h:5897
ADC2_Type::OUT_CH8
__IM uint32_t OUT_CH8
Definition: tle986x.h:911
SCU_Type::T3IE
__IOM uint8_t T3IE
Definition: tle986x.h:4871
UART2_Tmr21_EINT2_Int
Definition: tle986x.h:114
ADC2_Type::SEL_TS_COUNT
__IOM uint32_t SEL_TS_COUNT
Definition: tle986x.h:640
GPT12E_Type::T3
__IOM uint16_t T3
Definition: tle986x.h:2928
ADC2_Type::MCM_PD_N
__IOM uint32_t MCM_PD_N
Definition: tle986x.h:633
SCU_Type::NMISUPC
__OM uint8_t NMISUPC
Definition: tle986x.h:3880
PORT_Type::P4
__IM uint8_t P4
Definition: tle986x.h:3641
CCU6_Type::COUT63PS
__IOM uint16_t COUT63PS
Definition: tle986x.h:1972
ADC1_Type::CH4_IE
__IOM uint32_t CH4_IE
Definition: tle986x.h:508
TIMER3_Type::T3_PD_N
__IOM uint32_t T3_PD_N
Definition: tle986x.h:5836
ADC1_Type::VF5
__IM uint32_t VF5
Definition: tle986x.h:389
SSC1_Type::PE
__IM uint16_t PE
Definition: tle986x.h:5498
BDRV_Type::DSMONVTH
__IOM uint32_t DSMONVTH
Definition: tle986x.h:1308
CCU6_Type::ISCNT12
__IOM uint16_t ISCNT12
Definition: tle986x.h:1922
CCU6_Type::RCC62F
__OM uint16_t RCC62F
Definition: tle986x.h:1505
BDRV_CP_Int
Definition: tle986x.h:117
CPU_Type::PRECISERR
__IOM uint32_t PRECISERR
Definition: tle986x.h:2412
GPT12E_Type::T2M
__IOM uint16_t T2M
Definition: tle986x.h:2800
ADC34_Type::ADC3_SOC
__IOM uint32_t ADC3_SOC
Definition: tle986x.h:1188
SCU_Type::CH4C
__OM uint8_t CH4C
Definition: tle986x.h:4960
GPT12E
#define GPT12E
Definition: tle986x.h:5998
UART_Type::SM0
__IOM uint8_t SM0
Definition: tle986x.h:5903
SCU_Type::T6
__IM uint8_t T6
Definition: tle986x.h:4891
CCU6_Type::T13CNT
__OM uint16_t T13CNT
Definition: tle986x.h:1470
CPU_Type::DWTTRAP
__IOM uint32_t DWTTRAP
Definition: tle986x.h:2450
SCUPM_Type::PMU_OTWARN_IE
__IOM uint32_t PMU_OTWARN_IE
Definition: tle986x.h:5230
CPU_Type::Int_DMA
__IOM uint32_t Int_DMA
Definition: tle986x.h:2073
SCU_Type::BRKC
__OM uint8_t BRKC
Definition: tle986x.h:4440
SCUPM_Type::VREF5V_UPTH_ICLR
__OM uint32_t VREF5V_UPTH_ICLR
Definition: tle986x.h:5106
CPU_Type::SKEW
__IM uint32_t SKEW
Definition: tle986x.h:2046
BDRV_Type::CPLOPWRM_EN
__IOM uint32_t CPLOPWRM_EN
Definition: tle986x.h:1406
CCU6_Type::ENTRPF
__IOM uint16_t ENTRPF
Definition: tle986x.h:1723
SCU_Type::MODE
__IOM uint8_t MODE
Definition: tle986x.h:4465
ADC2_Type::SQ9_int
__IM uint32_t SQ9_int
Definition: tle986x.h:727
MON
#define MON
Definition: tle986x.h:6001
SCU_Type::CH6
__IM uint8_t CH6
Definition: tle986x.h:4839
SCU_Type::FNMIOWD
__IM uint8_t FNMIOWD
Definition: tle986x.h:3966
CCU6_Type::T12CV
__IOM uint16_t T12CV
Definition: tle986x.h:1936
SCU_Type::SYNEN
__IOM uint8_t SYNEN
Definition: tle986x.h:4392
CCU6_Type::T13R
__IM uint16_t T13R
Definition: tle986x.h:1647
MF_Type::PMU_OT_STS
__IM uint32_t PMU_OT_STS
Definition: tle986x.h:3064
CCU6_Type::RCC61R
__OM uint16_t RCC61R
Definition: tle986x.h:1502
CCU6_Type::RESERVED24
__IM uint16_t RESERVED24
Definition: tle986x.h:1854
BDRV_Type::HS1DRV_FDISCHG_DIS
__IOM uint32_t HS1DRV_FDISCHG_DIS
Definition: tle986x.h:1372
ADC2_Type::SQ4
__IOM uint32_t SQ4
Definition: tle986x.h:668
SCUPM_Type::SYS_VSD_OV_SLM_DIS
__IOM uint32_t SYS_VSD_OV_SLM_DIS
Definition: tle986x.h:5263
GPT12E_Type::T3I
__IOM uint16_t T3I
Definition: tle986x.h:2820
ADC2_Type::SQ_STOP
__IM uint32_t SQ_STOP
Definition: tle986x.h:571
CPU_Type::PRI_CCU6SR1
__IOM uint32_t PRI_CCU6SR1
Definition: tle986x.h:2202
BDRV_Type::DITH_UPPER
__IOM uint32_t DITH_UPPER
Definition: tle986x.h:1420
CCU6_Type::ISTRP
__IOM uint16_t ISTRP
Definition: tle986x.h:1906
SCUPM_Type::VSD_LOWTH_SCLR
__OM uint32_t VSD_LOWTH_SCLR
Definition: tle986x.h:5318
SCUPM_Type::HS2_DS_IE
__IOM uint32_t HS2_DS_IE
Definition: tle986x.h:5377
DMA_Type::ERR_CLR
__IOM uint32_t ERR_CLR
Definition: tle986x.h:2739
SCU_Type::APCLK1SCLR
__IOM uint8_t APCLK1SCLR
Definition: tle986x.h:4197
ADC2_Type::HYST_LO_CH5
__IOM uint32_t HYST_LO_CH5
Definition: tle986x.h:1060
CPU_Type::PRI_CCU6SR3
__IOM uint32_t PRI_CCU6SR3
Definition: tle986x.h:2204
CPU_Type::PRI_4
__IOM uint32_t PRI_4
Definition: tle986x.h:2339
MF_Type::VREF5V_OV_STS
__IM uint32_t VREF5V_OV_STS
Definition: tle986x.h:3093
SCU_Type::CH8
__IM uint8_t CH8
Definition: tle986x.h:4841
CCU6_Type::CURHS
__IOM uint16_t CURHS
Definition: tle986x.h:1487
SCU_Type::SSCRX
__IM uint8_t SSCRX
Definition: tle986x.h:4822
ADC1_Type::ESM_STS
__IM uint32_t ESM_STS
Definition: tle986x.h:494
GPT12E_Type::RESERVED10
__IM uint16_t RESERVED10
Definition: tle986x.h:2942
SCU_Type::APCLK2SCLR
__IOM uint8_t APCLK2SCLR
Definition: tle986x.h:4214
SCU_Type::GPT12_T3
__IM uint8_t GPT12_T3
Definition: tle986x.h:4823
CCU6_Type::RCC60R
__OM uint16_t RCC60R
Definition: tle986x.h:1500
ADC1_Type::OUT_CH3
__IM uint32_t OUT_CH3
Definition: tle986x.h:414
BDRV_Type::LS2_OC_DIS
__IOM uint32_t LS2_OC_DIS
Definition: tle986x.h:1257
CCU6_Type::ENCC60F
__IOM uint16_t ENCC60F
Definition: tle986x.h:1709
CCU6_Type::T12CNT
__OM uint16_t T12CNT
Definition: tle986x.h:1463
SCUPM_Type::LS2_OC_ICLR
__OM uint32_t LS2_OC_ICLR
Definition: tle986x.h:5297
SCU_Type::T21IS
__IOM uint8_t T21IS
Definition: tle986x.h:4539
TIMER2x_Type::RC2
__IOM uint8_t RC2
Definition: tle986x.h:5717
TIMER2
#define TIMER2
Definition: tle986x.h:6008
SCUPM_Type::VCP_LOWTH1_STS
__IM uint32_t VCP_LOWTH1_STS
Definition: tle986x.h:5356
BDRV_Type::LS2_ON
__IOM uint32_t LS2_ON
Definition: tle986x.h:1251
CPU_Type::CLKSOURCE
__IOM uint32_t CLKSOURCE
Definition: tle986x.h:2012
CPU_Type::Int_DMA
__IM uint32_t Int_DMA
Definition: tle986x.h:2177
SCUPM_Type::VCP_UPTH_STS
__IM uint32_t VCP_UPTH_STS
Definition: tle986x.h:5358
SCU_Type::SSC1C
__OM uint8_t SSC1C
Definition: tle986x.h:4978
ADC2_Type::Ch1
__IOM uint32_t Ch1
Definition: tle986x.h:1145
PMU_Type::PMU_5V_OVERVOLT
__IM uint8_t PMU_5V_OVERVOLT
Definition: tle986x.h:3170
SCU_Type::TRSEQ1DY
__IM uint8_t TRSEQ1DY
Definition: tle986x.h:4853
DMA_Type
Direct Memeory Access (DMA)
Definition: tle986x.h:2536
TIMER3
#define TIMER3
Definition: tle986x.h:6010
SCUPM_Type::LIN_OC_IE
__IOM uint32_t LIN_OC_IE
Definition: tle986x.h:5226
ADC2_Type::OFFS_CH1
__IOM uint32_t OFFS_CH1
Definition: tle986x.h:740
SSC1_Type::CIS
__IOM uint16_t CIS
Definition: tle986x.h:5477
ADC2
#define ADC2
Definition: tle986x.h:5991
CCU6_Type::EXPH
__IM uint16_t EXPH
Definition: tle986x.h:1865
CPU_Type::PARTNO
__IM uint32_t PARTNO
Definition: tle986x.h:2242
CCU6_Type::ENT13CM
__IOM uint16_t ENT13CM
Definition: tle986x.h:1721
CCU6_Type::R
__IM uint16_t R
Definition: tle986x.h:1863
SCU_Type::BR_VALUE
__IOM uint8_t BR_VALUE
Definition: tle986x.h:4365
ADC1_Type::SQ3
__IOM uint32_t SQ3
Definition: tle986x.h:257
PMU_Type::LIN_EN
__IOM uint8_t LIN_EN
Definition: tle986x.h:3289
SCUPM_Type::VDD5V_UV_IS
__IM uint32_t VDD5V_UV_IS
Definition: tle986x.h:5159
UART1_LIN_Tmr2_Int
Definition: tle986x.h:113
ADC1_Type::ESM_ICLR
__OM uint32_t ESM_ICLR
Definition: tle986x.h:532
SCUPM_Type::VCP_LOWTH1_IS
__IM uint32_t VCP_LOWTH1_IS
Definition: tle986x.h:5345
PMU_Type::GPIO0_CYC_0
__IOM uint8_t GPIO0_CYC_0
Definition: tle986x.h:3491
PMU_Type::FAIL
__IM uint8_t FAIL
Definition: tle986x.h:3155
CCU6_Type::RESERVED12
__IM uint16_t RESERVED12
Definition: tle986x.h:1651
ADC2_Type::GAIN_CH9
__IM uint32_t GAIN_CH9
Definition: tle986x.h:793
ADC1_Type::CH1_ICLR
__OM uint32_t CH1_ICLR
Definition: tle986x.h:524
SCU_Type::CPCLK_DIV
__IOM uint8_t CPCLK_DIV
Definition: tle986x.h:4185
LIN_Type::FB_SM2
__IM uint32_t FB_SM2
Definition: tle986x.h:2998
BDRV_Type::DLY_DIAG_STS
__IM uint32_t DLY_DIAG_STS
Definition: tle986x.h:1288
ADC34_Type::ADC3_EN
__IOM uint32_t ADC3_EN
Definition: tle986x.h:1186
ADC2_Type::CH1
__IOM uint32_t CH1
Definition: tle986x.h:804
SCU_Type::BRPRE
__IOM uint8_t BRPRE
Definition: tle986x.h:4352
ADC2_Type::CH7
__IM uint32_t CH7
Definition: tle986x.h:819
PORT_Type::P0
__IOM uint8_t P0
Definition: tle986x.h:3577
GPT12E_Type::CAPREL
__IOM uint16_t CAPREL
Definition: tle986x.h:2906
PMU_Type::M03
__IOM uint8_t M03
Definition: tle986x.h:3251
PMU_Type::EN_VDDEXT_OC_OFF_N
__IOM uint8_t EN_VDDEXT_OC_OFF_N
Definition: tle986x.h:3240
PMU_Type
Power Management Unit (PMU)
Definition: tle986x.h:3139
GPT12E_Type::T6UD
__IOM uint16_t T6UD
Definition: tle986x.h:2888
SCU_Type::NMIWDTC
__OM uint8_t NMIWDTC
Definition: tle986x.h:3873
SCU_Type::CH7C
__OM uint8_t CH7C
Definition: tle986x.h:4963
PMU_Type::GPIO1_CYC_0
__IOM uint8_t GPIO1_CYC_0
Definition: tle986x.h:3536
CPU_Type::SYSTICKACT
__IOM uint32_t SYSTICKACT
Definition: tle986x.h:2387
SCU_Type::APCLK1FAC
__IOM uint8_t APCLK1FAC
Definition: tle986x.h:4196
ADC1_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:195
SSC2_Type::RECLR
__OM uint16_t RECLR
Definition: tle986x.h:5657
PMU_Type::OSC_100kHz_EN
__IOM uint8_t OSC_100kHz_EN
Definition: tle986x.h:3254
DMA_Type::WAITONREQ_STATUS
__IM uint32_t WAITONREQ_STATUS
Definition: tle986x.h:2592
CCU6_Type::EXPHS
__IOM uint16_t EXPHS
Definition: tle986x.h:1486
SSC1_Int
Definition: tle986x.h:111
CPU_Type::SVCALLACT
__IOM uint32_t SVCALLACT
Definition: tle986x.h:2383
PMU_Type::WDT1_SEQ_FAIL
__IOM uint8_t WDT1_SEQ_FAIL
Definition: tle986x.h:3317
SCUPM_Type::VBAT_UV_IS
__IM uint32_t VBAT_UV_IS
Definition: tle986x.h:5157
MF_Type::P2_0_ADC_SEL
__IOM uint32_t P2_0_ADC_SEL
Definition: tle986x.h:3029
ADC2_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:553
ADC1_Type::OF8
__IM uint32_t OF8
Definition: tle986x.h:331
BDRV_Type::HS1_OC_DIS
__IOM uint32_t HS1_OC_DIS
Definition: tle986x.h:1266
SCU_Type::FNMIWDT
__IM uint8_t FNMIWDT
Definition: tle986x.h:3962
SCUPM_Type::REFBG_LOTHWARN_ICLR
__OM uint32_t REFBG_LOTHWARN_ICLR
Definition: tle986x.h:5100
ADC1_Type::WFR1
__IOM uint32_t WFR1
Definition: tle986x.h:444
BDRV_Type
Bridge Driver (BDRV)
Definition: tle986x.h:1232
SSC1_Type::BECLR
__OM uint16_t BECLR
Definition: tle986x.h:5551
PMU_Type::PMU_SleepEX
__IOM uint8_t PMU_SleepEX
Definition: tle986x.h:3205
PORT_Type::P7
__IOM uint8_t P7
Definition: tle986x.h:3662
GPT12E_Type::T2I
__IOM uint16_t T2I
Definition: tle986x.h:2799
ADC1_Type::WFR7
__IOM uint32_t WFR7
Definition: tle986x.h:360
GPT12E_Type::T6UDE
__IOM uint16_t T6UDE
Definition: tle986x.h:2889
TIMER3_Type::T3H_OVF_STS
__IM uint32_t T3H_OVF_STS
Definition: tle986x.h:5841
SCU_Type::BRK
__IM uint8_t BRK
Definition: tle986x.h:4389
CCU6_Type::CC61ST
__IM uint16_t CC61ST
Definition: tle986x.h:1959
ADC2_Type::SQ2
__IOM uint32_t SQ2
Definition: tle986x.h:664
SCUPM_Type::VS_UV_ICLR
__OM uint32_t VS_UV_ICLR
Definition: tle986x.h:5201
GPT12E_Type::IST5EUD
__IOM uint16_t IST5EUD
Definition: tle986x.h:2785
CCU6_Type::INPCHE
__IOM uint16_t INPCHE
Definition: tle986x.h:1742
ADC2_Type::FILT_OUT_SEL_5_0
__IOM uint32_t FILT_OUT_SEL_5_0
Definition: tle986x.h:650
ADC1_Type::CH7_STS
__IM uint32_t CH7_STS
Definition: tle986x.h:492
ADC1_Type::CH7_ICLR
__OM uint32_t CH7_ICLR
Definition: tle986x.h:530
ADC1_Type::OF4
__IM uint32_t OF4
Definition: tle986x.h:404
SCUPM_Type::VCP_LOWTH2_ICLR
__OM uint32_t VCP_LOWTH2_ICLR
Definition: tle986x.h:5301
SCU_Type::RIRC
__OM uint8_t RIRC
Definition: tle986x.h:4922
NonMaskableInt_IRQn
Definition: tle986x.h:91
SSC1_Type::RESERVED1
__IM uint16_t RESERVED1
Definition: tle986x.h:5506
ADC2_Type::CNT_LO_CH2
__IOM uint32_t CNT_LO_CH2
Definition: tle986x.h:1042
SCUPM_Type::VSD_LOWTH_ICLR
__OM uint32_t VSD_LOWTH_ICLR
Definition: tle986x.h:5307
CPU_Type::CP5
__IOM uint32_t CP5
Definition: tle986x.h:2487
GPT12E_Type::T6M
__IOM uint16_t T6M
Definition: tle986x.h:2886
ADC1_Type::ch1
__IOM uint32_t ch1
Definition: tle986x.h:284
CCU6_Type
Capture Compare Unit 6 (CCU6)
Definition: tle986x.h:1438
SCUPM_Type::RESERVED2
__IM uint32_t RESERVED2
Definition: tle986x.h:5249
CPU_Type::MEMFAULTACT
__IOM uint32_t MEMFAULTACT
Definition: tle986x.h:2378
PMU_Type::GPIO0_RI_1
__IOM uint8_t GPIO0_RI_1
Definition: tle986x.h:3462
GPT12E_Type::IST2IN
__IOM uint16_t IST2IN
Definition: tle986x.h:2778
SCU_Type::FNMISUP
__IM uint8_t FNMISUP
Definition: tle986x.h:3969
SCU_Type::T2_DIS
__IOM uint8_t T2_DIS
Definition: tle986x.h:4228
BDRV_Type::DRV_OFF_t_4
__IOM uint32_t DRV_OFF_t_4
Definition: tle986x.h:1323
ADC2_Type::VBAT_RANGE
__IOM uint32_t VBAT_RANGE
Definition: tle986x.h:558
ADC2_Type::EN
__IOM uint32_t EN
Definition: tle986x.h:590
TIMER2x_Type::T2L
__IOM uint8_t T2L
Definition: tle986x.h:5739
SCU_Type::K2DIV
__IOM uint8_t K2DIV
Definition: tle986x.h:4138
PORT
#define PORT
Definition: tle986x.h:6003
CPU_Type::PRI_CCU6SR0
__IOM uint32_t PRI_CCU6SR0
Definition: tle986x.h:2201
CCU6_Type::ICC60F
__IM uint16_t ICC60F
Definition: tle986x.h:1878
SCUPM_Type::ADC4_EOC_IS
__IM uint32_t ADC4_EOC_IS
Definition: tle986x.h:5146
SCUPM_Type::AMCLK2_LOW_HYS
__IOM uint32_t AMCLK2_LOW_HYS
Definition: tle986x.h:5077
SCUPM_Type::VDD1V5_OV_IE
__IOM uint32_t VDD1V5_OV_IE
Definition: tle986x.h:5190
CCU6_Type::WHE
__IM uint16_t WHE
Definition: tle986x.h:1890
ADC1_Type::CH5_IE
__IOM uint32_t CH5_IE
Definition: tle986x.h:509
CPU_Type::IACCVIOL
__IOM uint32_t IACCVIOL
Definition: tle986x.h:2404
CPU_Type::FORCED
__IOM uint32_t FORCED
Definition: tle986x.h:2437
ADC1_Type::BUSY
__IM uint32_t BUSY
Definition: tle986x.h:470
CCU6_Type::T13RS
__OM uint16_t T13RS
Definition: tle986x.h:1467
CCU6_Type::DTR1
__IM uint16_t DTR1
Definition: tle986x.h:1627
PMU_Type::SUPP_SHORT
__IOM uint8_t SUPP_SHORT
Definition: tle986x.h:3311
CCU6_Type::ENCC62F
__IOM uint16_t ENCC62F
Definition: tle986x.h:1717
ADC1_Type::OUT_CH0
__IM uint32_t OUT_CH0
Definition: tle986x.h:456
GPT12E_Type::T5I
__IOM uint16_t T5I
Definition: tle986x.h:2863
SCU_Type::BGCLK_SEL
__IOM uint8_t BGCLK_SEL
Definition: tle986x.h:4182
PMU_Type::GPIO1_RI_1
__IOM uint8_t GPIO1_RI_1
Definition: tle986x.h:3507
CCU6_Type::ISPOS2
__IOM uint16_t ISPOS2
Definition: tle986x.h:1909
MON_Type::STS
__I uint8_t STS
Definition: tle986x.h:3124
CCU6_SR1_Int
Definition: tle986x.h:108
SSC2_Int
Definition: tle986x.h:112
CPU_Type::Int_BDRV
__IM uint32_t Int_BDRV
Definition: tle986x.h:2176
ADC1_Type::OUT_CH2
__IM uint32_t OUT_CH2
Definition: tle986x.h:428
ADC2_Type::CNT_UP_CH0
__IOM uint32_t CNT_UP_CH0
Definition: tle986x.h:1090
CPU_Type::VECTTBL
__IOM uint32_t VECTTBL
Definition: tle986x.h:2435
SCUPM_Type::ADC2_ESM_ICLR
__OM uint32_t ADC2_ESM_ICLR
Definition: tle986x.h:5109
PMU_Type::GPIO1_RI_0
__IOM uint8_t GPIO1_RI_0
Definition: tle986x.h:3506
BDRV
#define BDRV
Definition: tle986x.h:5993
ADC2_Type::CNT_UP_CH3
__IOM uint32_t CNT_UP_CH3
Definition: tle986x.h:1099
SCU_Type::PDM2
__IOM uint8_t PDM2
Definition: tle986x.h:4693
CPU_Type::PRI_ADC1
__IOM uint32_t PRI_ADC1
Definition: tle986x.h:2191
ADC1_Type::OUT_CH6
__IM uint32_t OUT_CH6
Definition: tle986x.h:372
MF_Type::SYS_OT_STS
__IM uint32_t SYS_OT_STS
Definition: tle986x.h:3066
CCU6_Type::SWSYN
__IOM uint16_t SWSYN
Definition: tle986x.h:1797
TIMER2x_Type::T2PRE
__IOM uint8_t T2PRE
Definition: tle986x.h:5702
SSC2_Type::TECLR
__OM uint16_t TECLR
Definition: tle986x.h:5656
__OM
#define __OM
Definition: tle986x.h:146
ADC2_Type::HYST_UP_CH7
__IM uint32_t HYST_UP_CH7
Definition: tle986x.h:1128
BDRV_Type::VSD_UPTH_STS
__IM uint32_t VSD_UPTH_STS
Definition: tle986x.h:1405
CCU6_Type::STE13U
__IOM uint16_t STE13U
Definition: tle986x.h:1801
CPU_Type::Int_EXINT1
__IOM uint32_t Int_EXINT1
Definition: tle986x.h:2071
TIMER2x_Type::reg
__IOM uint8_t reg
Definition: tle986x.h:5680
SCU_Type::PDM4
__IOM uint8_t PDM4
Definition: tle986x.h:4706
GPT12E_Type::T5M
__IOM uint16_t T5M
Definition: tle986x.h:2864
CCU6_Type::TRPEN13
__IOM uint16_t TRPEN13
Definition: tle986x.h:1850
CPU_Type::Int_UART1
__IOM uint32_t Int_UART1
Definition: tle986x.h:2068
BDRV_Type::LS1_OC_DIS
__IOM uint32_t LS1_OC_DIS
Definition: tle986x.h:1248
SCU_Type::SSC2_DIS
__IOM uint8_t SSC2_DIS
Definition: tle986x.h:4241
CCU6_Type::INPT13
__IOM uint16_t INPT13
Definition: tle986x.h:1745
GPT12E_Type::T3M
__IOM uint16_t T3M
Definition: tle986x.h:2821
ADC1_Type::OUT_CH_EIM
__IM uint32_t OUT_CH_EIM
Definition: tle986x.h:327
CCU6_Type::ST12PM
__OM uint16_t ST12PM
Definition: tle986x.h:1763
DMA_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:2546
CPU_Type::Int_CCU6SR1
__IM uint32_t Int_CCU6SR1
Definition: tle986x.h:2167
Reset_IRQn
Definition: tle986x.h:90
SCUPM_Type::DBFSTS
__IM uint32_t DBFSTS
Definition: tle986x.h:5411
ADC2_Type::SQ5_int
__IM uint32_t SQ5_int
Definition: tle986x.h:713
SCUPM_Type::VREF5V_LOWTH_ICLR
__OM uint32_t VREF5V_LOWTH_ICLR
Definition: tle986x.h:5104
CSA_Type::VZERO
__IO uint32_t VZERO
Definition: tle986x.h:2521
PMU_Type::GPIO0_RI_4
__IOM uint8_t GPIO0_RI_4
Definition: tle986x.h:3465
TIMER3_Type::T3_RD_REQ_CONF
__IOM uint32_t T3_RD_REQ_CONF
Definition: tle986x.h:5838
PMU_Type::DATA0
__IOM uint8_t DATA0
Definition: tle986x.h:3395
SCU_Type::RIE
__IOM uint8_t RIE
Definition: tle986x.h:4608
ADC2_Type::HYST_LO_CH1
__IOM uint32_t HYST_LO_CH1
Definition: tle986x.h:1040
TIMER3_Type::T3L_OVF_STS
__IM uint32_t T3L_OVF_STS
Definition: tle986x.h:5843
CPU_Type::MEMFAULTENA
__IOM uint32_t MEMFAULTENA
Definition: tle986x.h:2392
CCU6_Type::T12SSC
__IOM uint16_t T12SSC
Definition: tle986x.h:1812
CPU_Type::PRI_EXINT1
__IOM uint32_t PRI_EXINT1
Definition: tle986x.h:2228
SCU_Type::MON_Trig_Sel
__IOM uint8_t MON_Trig_Sel
Definition: tle986x.h:4013
SCUPM_Type::VS_OV_IS
__IM uint32_t VS_OV_IS
Definition: tle986x.h:5162
SCU_Type::SASTATUS
__IOM uint8_t SASTATUS
Definition: tle986x.h:4638
SCU_Type::T3CLK_SEL
__IOM uint8_t T3CLK_SEL
Definition: tle986x.h:4180
BDRV_Type::DRVx_VCPUP_DIS
__IOM uint32_t DRVx_VCPUP_DIS
Definition: tle986x.h:1400
SCU_Type::EXINT2IS
__IOM uint8_t EXINT2IS
Definition: tle986x.h:4511
CPU_Type::BUSFAULTENA
__IOM uint32_t BUSFAULTENA
Definition: tle986x.h:2393
CCU6_Type::T12RSEL
__IOM uint16_t T12RSEL
Definition: tle986x.h:1817
SCUPM_Type::VDD5V_OV_ICLR
__OM uint32_t VDD5V_OV_ICLR
Definition: tle986x.h:5206
CCU6_Type::MSEL60
__IOM uint16_t MSEL60
Definition: tle986x.h:1692
CCU6_Type::T13CM
__IM uint16_t T13CM
Definition: tle986x.h:1885
SCU_Type::EXINT1FC
__OM uint8_t EXINT1FC
Definition: tle986x.h:4030
SCUPM_Type::ADC3_EOC_IS
__IM uint32_t ADC3_EOC_IS
Definition: tle986x.h:5145
TIMER3_Type::RETRIG
__IOM uint32_t RETRIG
Definition: tle986x.h:5803
SCU_Type::TRIG_CONF
__IOM uint8_t TRIG_CONF
Definition: tle986x.h:4595
SCU_Type::T5C
__OM uint8_t T5C
Definition: tle986x.h:4907
SCU_Type::GPT12_SUSP
__IOM uint8_t GPT12_SUSP
Definition: tle986x.h:4568
CPU_Type::Int_ADC1
__IOM uint32_t Int_ADC1
Definition: tle986x.h:2061
ADC2_Type::OFFS_CH8
__IM uint32_t OFFS_CH8
Definition: tle986x.h:790
SCU_Type::SDADC
__IM uint8_t SDADC
Definition: tle986x.h:4858
SCU_Type::APCLK3STS
__IM uint8_t APCLK3STS
Definition: tle986x.h:4200
SCU_Type::NVMPROTSTSL_2
__IOM uint8_t NVMPROTSTSL_2
Definition: tle986x.h:4651
CCU6_Type::INPERR
__IOM uint16_t INPERR
Definition: tle986x.h:1743
ADC1_Type::VF2
__IM uint32_t VF2
Definition: tle986x.h:431
ADC1_Type::ESM_IE
__IOM uint32_t ESM_IE
Definition: tle986x.h:513
SCU_Type::LOCKUP
__IOM uint8_t LOCKUP
Definition: tle986x.h:4256
DMA_Type::CHNL_REQ_MASK_CLR
__OM uint32_t CHNL_REQ_MASK_CLR
Definition: tle986x.h:2655
ADC1_Type::WFR5
__IOM uint32_t WFR5
Definition: tle986x.h:388
ADC1_Type::DIVA
__IOM uint32_t DIVA
Definition: tle986x.h:208
SCUPM_Type::VDD5V_UV_SCLR
__OM uint32_t VDD5V_UV_SCLR
Definition: tle986x.h:5211
CCU6_Type::MCC61R
__OM uint16_t MCC61R
Definition: tle986x.h:1538
CCU6_Type::ISPOS1
__IOM uint16_t ISPOS1
Definition: tle986x.h:1908
ADC2_Type::HYST_UP_CH8
__IM uint32_t HYST_UP_CH8
Definition: tle986x.h:1131
SSC1_Type::MIS_1
__IOM uint16_t MIS_1
Definition: tle986x.h:5482
MON_Type::CYC
__IO uint8_t CYC
Definition: tle986x.h:3120
MON_Type::FALL
__IO uint8_t FALL
Definition: tle986x.h:3118
SSC1_Type::BR_VALUE
__IOM uint16_t BR_VALUE
Definition: tle986x.h:5536
ADC2_Type::Ch4_EN
__IOM uint32_t Ch4_EN
Definition: tle986x.h:935
GPT12E_Type::CI
__IOM uint16_t CI
Definition: tle986x.h:2872
SCUPM
#define SCUPM
Definition: tle986x.h:6005
SCUPM_Type::PMU_OT_IE
__IOM uint32_t PMU_OT_IE
Definition: tle986x.h:5231
SCU_Type::APCLK2STS
__IM uint8_t APCLK2STS
Definition: tle986x.h:4213
CCU6_Type::DTM
__IOM uint16_t DTM
Definition: tle986x.h:1621
CPU_Type::USGFAULTENA
__IOM uint32_t USGFAULTENA
Definition: tle986x.h:2394
BDRV_Type::DRV_OFF_I_2
__IOM uint32_t DRV_OFF_I_2
Definition: tle986x.h:1328
CCU6_Type::ISPOS0
__IOM uint16_t ISPOS0
Definition: tle986x.h:1907
CPU_Type::SLEEPONEXIT
__IOM uint32_t SLEEPONEXIT
Definition: tle986x.h:2307
ADC1_Type::EOC
__IM uint32_t EOC
Definition: tle986x.h:197
ADC2_Type::CNT_LO_CH1
__IOM uint32_t CNT_LO_CH1
Definition: tle986x.h:1039
SCUPM_Type::REFBG_UPTHWARN_IS
__IM uint32_t REFBG_UPTHWARN_IS
Definition: tle986x.h:5136
CPU_Type::PRI_6
__IOM uint32_t PRI_6
Definition: tle986x.h:2341
SCU_Type::MONF
__IM uint8_t MONF
Definition: tle986x.h:3898
CPU_Type::PENDSVACT
__IOM uint32_t PENDSVACT
Definition: tle986x.h:2386
PMU_Type::SYS_FAIL
__IOM uint8_t SYS_FAIL
Definition: tle986x.h:3202
CCU6_Type::RESERVED15
__IM uint16_t RESERVED15
Definition: tle986x.h:1684
CPU_Type::VCATCH
__IOM uint32_t VCATCH
Definition: tle986x.h:2451
GPT1_Int
Definition: tle986x.h:103
SCU_Type::CCU6SR2
__IM uint8_t CCU6SR2
Definition: tle986x.h:3949
ADC2_Type::CHx
__IOM uint32_t CHx
Definition: tle986x.h:587
ADC2_Type::CNT_UP_CH5
__IOM uint32_t CNT_UP_CH5
Definition: tle986x.h:1113
SCU_Type::TIRC
__OM uint8_t TIRC
Definition: tle986x.h:4921
SCU_Type::NDIV
__IOM uint8_t NDIV
Definition: tle986x.h:4126
ADC2_Type::GAIN_CH5
__IOM uint32_t GAIN_CH5
Definition: tle986x.h:767
SCUPM_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:5042
CCU6_Type::reg
__IOM uint16_t reg
Definition: tle986x.h:1443
SCUPM_Type::ADC3_EOC_IE
__IOM uint32_t ADC3_EOC_IE
Definition: tle986x.h:5245
SCU_Type::APCLK2FAC
__IOM uint8_t APCLK2FAC
Definition: tle986x.h:4212
ADC34_Type::ADC34_DREQ_SEL
__IM uint32_t ADC34_DREQ_SEL
Definition: tle986x.h:1192
CPU_Type::Int_CCU6SR2
__IOM uint32_t Int_CCU6SR2
Definition: tle986x.h:2064
PMU_Type::PMU_SOFT
__IOM uint8_t PMU_SOFT
Definition: tle986x.h:3222
SSC1_Type::PECLR
__OM uint16_t PECLR
Definition: tle986x.h:5550
CPU_Type::PENDSVSET
__IOM uint32_t PENDSVSET
Definition: tle986x.h:2266
SSC1_Type::BC
__IM uint16_t BC
Definition: tle986x.h:5494
CCU6_Type::T13PM
__IM uint16_t T13PM
Definition: tle986x.h:1886
SSC2_Type::RB_VALUE
__IM uint16_t RB_VALUE
Definition: tle986x.h:5633
PORT_Type::P4
__IOM uint8_t P4
Definition: tle986x.h:3581
MF_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:3035
ADC2_Type::CH8
__IOM uint32_t CH8
Definition: tle986x.h:988
SCUPM_Type::ADC3_EOC_ICLR
__OM uint32_t ADC3_EOC_ICLR
Definition: tle986x.h:5111
CPU_Type::HALTED
__IOM uint32_t HALTED
Definition: tle986x.h:2448
CCU6_Type::MCMPS
__IOM uint16_t MCMPS
Definition: tle986x.h:1483
SCU_Type::SSCRXIE
__IOM uint8_t SSCRXIE
Definition: tle986x.h:4803
CCU6_Type::IST12HR
__IOM uint16_t IST12HR
Definition: tle986x.h:1910
UsageFault_IRQn
Definition: tle986x.h:97
SCUPM_Type::VS_OV_SCLR
__OM uint32_t VS_OV_SCLR
Definition: tle986x.h:5214
SCU_Type::OSCTRIM_8
__IOM uint8_t OSCTRIM_8
Definition: tle986x.h:4483
BDRV_Type::DRV_ON_t_4
__IOM uint32_t DRV_ON_t_4
Definition: tle986x.h:1340
SCU_Type::MRAMINITSTS
__IOM uint8_t MRAMINITSTS
Definition: tle986x.h:4295
DMA_Type::STATE
__IM uint32_t STATE
Definition: tle986x.h:2547
SCUPM_Type::VDD5V_UV_ICLR
__OM uint32_t VDD5V_UV_ICLR
Definition: tle986x.h:5202
GPT12E_Type::reg
__IOM uint16_t reg
Definition: tle986x.h:2762
LIN_Type::FB_SM3
__IM uint32_t FB_SM3
Definition: tle986x.h:2999
CCU6_Type::T13PV
__IOM uint16_t T13PV
Definition: tle986x.h:1610
BDRV_Type::VCP_LOWTH2
__IOM uint32_t VCP_LOWTH2
Definition: tle986x.h:1395
ADC2_Type::SQ10_int
__IM uint32_t SQ10_int
Definition: tle986x.h:728
SCU_Type::TRSEQ1DYC
__OM uint8_t TRSEQ1DYC
Definition: tle986x.h:4976
PMU_Type::GPIO1_CYC_4
__IOM uint8_t GPIO1_CYC_4
Definition: tle986x.h:3540
ADC1_Type::REP
__IOM uint32_t REP
Definition: tle986x.h:225
IRQn_Type
IRQn_Type
Definition: tle986x.h:87
CPU_Type::UNALIGNED
__IOM uint32_t UNALIGNED
Definition: tle986x.h:2423
ADC2_Type::SQ_FB
__IM uint32_t SQ_FB
Definition: tle986x.h:569
CPU_Type::Int_GPT2
__IM uint32_t Int_GPT2
Definition: tle986x.h:2163
SCUPM_Type::LIN_OC_IS
__IM uint32_t LIN_OC_IS
Definition: tle986x.h:5122
ADC34_Type::ADC3_OSR
__IOM uint32_t ADC3_OSR
Definition: tle986x.h:1195
ADC1_Type::ESM_0
__IOM uint32_t ESM_0
Definition: tle986x.h:239
SCUPM_Type::VREF5V_UPTH_IS
__IM uint32_t VREF5V_UPTH_IS
Definition: tle986x.h:5140
ADC1_Type::SQ5
__IOM uint32_t SQ5
Definition: tle986x.h:269
ADC2_Type::FILT_OUT_SEL_9_6
__IOM uint32_t FILT_OUT_SEL_9_6
Definition: tle986x.h:652
SCU_Type::RIR
__IM uint8_t RIR
Definition: tle986x.h:3912
SCUPM_Type::CLKWDT_RES_SD_DIS
__IOM uint32_t CLKWDT_RES_SD_DIS
Definition: tle986x.h:5267
PMU_Type::GPIO1_CYC_3
__IOM uint8_t GPIO1_CYC_3
Definition: tle986x.h:3539
GPT12E_Type::RESERVED11
__IM uint16_t RESERVED11
Definition: tle986x.h:2953
CCU6_Type::T12RR
__OM uint16_t T12RR
Definition: tle986x.h:1458
CCU6_Type::SWSEL
__IOM uint16_t SWSEL
Definition: tle986x.h:1795
CCU6_Type::RESERVED23
__IM uint16_t RESERVED23
Definition: tle986x.h:1837
PMU_Type::GPIO0_FA_1
__IOM uint8_t GPIO0_FA_1
Definition: tle986x.h:3477
SCU_Type::T4IE
__IOM uint8_t T4IE
Definition: tle986x.h:4872
SCU_Type::WDTEN
__IOM uint8_t WDTEN
Definition: tle986x.h:4164
TIMER2x_Type::PREN
__IOM uint8_t PREN
Definition: tle986x.h:5703
MF_Type::ADC3_INP_SEL
__IOM uint32_t ADC3_INP_SEL
Definition: tle986x.h:3036
SCUPM_Type::LS2_DS_ICLR
__OM uint32_t LS2_DS_ICLR
Definition: tle986x.h:5290
CCU6_Type::MCC62R
__OM uint16_t MCC62R
Definition: tle986x.h:1540
DMA_Type::CHN1_PROT_CTRL
__OM uint32_t CHN1_PROT_CTRL
Definition: tle986x.h:2561
CCU6_Type::ISCC61
__IOM uint16_t ISCC61
Definition: tle986x.h:1904
SCUPM_Type::VCP_LOWTH1_IE
__IOM uint32_t VCP_LOWTH1_IE
Definition: tle986x.h:5386
CPU_Type::Int_GPT1
__IOM uint32_t Int_GPT1
Definition: tle986x.h:2058
CCU6_Type::DTE0
__IOM uint16_t DTE0
Definition: tle986x.h:1622
SCU_Type::CH8C
__OM uint8_t CH8C
Definition: tle986x.h:4964
SCUPM_Type::VS_OV_ICLR
__OM uint32_t VS_OV_ICLR
Definition: tle986x.h:5205
SCU_Type::T21EXIS
__IOM uint8_t T21EXIS
Definition: tle986x.h:4541
BDRV_Type::HS1_OC_STS
__IM uint32_t HS1_OC_STS
Definition: tle986x.h:1265
CCU6_Type::T13RES
__OM uint16_t T13RES
Definition: tle986x.h:1468
GPT12E_Type::T6
__IOM uint16_t T6
Definition: tle986x.h:2961
SCU_Type::FNMIECC
__IM uint8_t FNMIECC
Definition: tle986x.h:3968
TIMER3_Type::T3H_OVF_IE
__IOM uint32_t T3H_OVF_IE
Definition: tle986x.h:5845
SCUPM_Type::LIN_OC_ICLR
__OM uint32_t LIN_OC_ICLR
Definition: tle986x.h:5088
TIMER2x_Type::uint8_t
__IM uint8_t
Definition: tle986x.h:5688
CPU_Type::CP7
__IOM uint32_t CP7
Definition: tle986x.h:2489
ADC2_Type::Ch0
__IOM uint32_t Ch0
Definition: tle986x.h:1144
MF_Type::P2_7_ADC_SEL
__IOM uint32_t P2_7_ADC_SEL
Definition: tle986x.h:3034
GPT12E_Type::T5RC
__IOM uint16_t T5RC
Definition: tle986x.h:2869
CPU_Type::PRI_13
__IOM uint32_t PRI_13
Definition: tle986x.h:2366
ADC1_Type::OF3
__IM uint32_t OF3
Definition: tle986x.h:418
SCU_Type::WDT
__IM uint8_t WDT
Definition: tle986x.h:4329
ADC1_Type::CHNR
__IM uint32_t CHNR
Definition: tle986x.h:473
TIMER2x_Type::TF2CLR
__OM uint8_t TF2CLR
Definition: tle986x.h:5775
SSC2_Type::EN
__IOM uint16_t EN
Definition: tle986x.h:5611
ADC1_Type::SAMPLE
__IM uint32_t SAMPLE
Definition: tle986x.h:471
PMU_Type::CYC_EN
__IOM uint8_t CYC_EN
Definition: tle986x.h:3184
SSC2_Type::BE
__IM uint16_t BE
Definition: tle986x.h:5607
SCUPM_Type::LIN_OT_ICLR
__OM uint32_t LIN_OT_ICLR
Definition: tle986x.h:5089
BDRV_Type::F_CP
__IOM uint32_t F_CP
Definition: tle986x.h:1421
ADC2_Type::OFFS_CH7
__IM uint32_t OFFS_CH7
Definition: tle986x.h:779
SCU_Type::CH3
__IM uint8_t CH3
Definition: tle986x.h:4836
SCU_Type::NMIPLL
__IOM uint8_t NMIPLL
Definition: tle986x.h:3993
PMU_Type::GPIO0_RI_0
__IOM uint8_t GPIO0_RI_0
Definition: tle986x.h:3461
GPT12E_Type::RESERVED4
__IM uint16_t RESERVED4
Definition: tle986x.h:2855
SSC2_Type::RE
__IM uint16_t RE
Definition: tle986x.h:5605
GPT12E_Type::T3CHDIR
__IOM uint16_t T3CHDIR
Definition: tle986x.h:2829
SCUPM_Type::SYS_OTWARN_ICLR
__OM uint32_t SYS_OTWARN_ICLR
Definition: tle986x.h:5096
SCU_Type::EXINT2RC
__OM uint8_t EXINT2RC
Definition: tle986x.h:4032
CCU6_Type::ST13PM
__OM uint16_t ST13PM
Definition: tle986x.h:1765
SCUPM_Type::AMCLK1_UP_TH
__IOM uint32_t AMCLK1_UP_TH
Definition: tle986x.h:5070
ADC2_Type::CNT_UP_CH8
__IM uint32_t CNT_UP_CH8
Definition: tle986x.h:1130
SCU_Type::NVM_PROT_ERR
__IM uint8_t NVM_PROT_ERR
Definition: tle986x.h:4663
TIMER21
#define TIMER21
Definition: tle986x.h:6009
ADC2_Type::HYST_LO_CH2
__IOM uint32_t HYST_LO_CH2
Definition: tle986x.h:1043
ADC1_Type::SQx
__IM uint32_t SQx
Definition: tle986x.h:346
GPT12E_Type::T3UD
__IOM uint16_t T3UD
Definition: tle986x.h:2823
CCU6_Type::RTRPF
__OM uint16_t RTRPF
Definition: tle986x.h:1510
PMU_Type::GPIO1_FA_1
__IOM uint8_t GPIO1_FA_1
Definition: tle986x.h:3522
CPU_Type::Int_CCU6SR0
__IOM uint32_t Int_CCU6SR0
Definition: tle986x.h:2062
SCU_Type::CH1
__IM uint8_t CH1
Definition: tle986x.h:4834
CCU6_Type::IST13HR
__IOM uint16_t IST13HR
Definition: tle986x.h:1921
MF_Type::VREF5V_PD_N
__IOM uint32_t VREF5V_PD_N
Definition: tle986x.h:3090
SCUPM_Type::VDD1V5_UV_SCLR
__OM uint32_t VDD1V5_UV_SCLR
Definition: tle986x.h:5212
CCU6_Type::T13TEC
__IOM uint16_t T13TEC
Definition: tle986x.h:1814
LIN_Type::TXD
__IOM uint32_t TXD
Definition: tle986x.h:2993
DMA_Type::CHNL_REQ_MASK_SET
__IOM uint32_t CHNL_REQ_MASK_SET
Definition: tle986x.h:2640
ADC1_Type::CH1_IE
__IOM uint32_t CH1_IE
Definition: tle986x.h:505
SCU_Type::FNMIPLL
__IM uint8_t FNMIPLL
Definition: tle986x.h:3963
BDRV_Type::LSDRV_DS_TFILT_SEL
__IOM uint32_t LSDRV_DS_TFILT_SEL
Definition: tle986x.h:1363
ADC1_Type::VF3
__IM uint32_t VF3
Definition: tle986x.h:417
CPU_Type::CP2
__IOM uint32_t CP2
Definition: tle986x.h:2484
LIN_Type::SM
__IOM uint32_t SM
Definition: tle986x.h:2996
CCU6_Type::ENT12OM
__IOM uint16_t ENT12OM
Definition: tle986x.h:1719
BDRV_Type::CPLOW_TFILT_SEL
__IOM uint32_t CPLOW_TFILT_SEL
Definition: tle986x.h:1378
SCUPM_Type::PMU_OTWARN_IS
__IM uint32_t PMU_OTWARN_IS
Definition: tle986x.h:5126
CPU_Type::VECTRESET
__IOM uint32_t VECTRESET
Definition: tle986x.h:2289
ADC2_Type::SQ4_int
__IM uint32_t SQ4_int
Definition: tle986x.h:712
ADC1_Type::ch5
__IOM uint32_t ch5
Definition: tle986x.h:288
CPU_Type::CURRENT
__IOM uint32_t CURRENT
Definition: tle986x.h:2034
CCU6_Type::MCC60S
__OM uint16_t MCC60S
Definition: tle986x.h:1526
GPT12E_Type::BPS1
__IOM uint16_t BPS1
Definition: tle986x.h:2827
PMU_Type::SUPP_TMOUT
__IOM uint8_t SUPP_TMOUT
Definition: tle986x.h:3312
ADC2_Type::HYST_UP_CH6
__IM uint32_t HYST_UP_CH6
Definition: tle986x.h:1125
SSC2_Type::MIS_0
__IOM uint16_t MIS_0
Definition: tle986x.h:5576
SCUPM_Type::VSD_LOWTH_STS
__IM uint32_t VSD_LOWTH_STS
Definition: tle986x.h:5360
CCU6_Type::RESERVED16
__IM uint16_t RESERVED16
Definition: tle986x.h:1699
SCUPM_Type::VBAT_OV_SCLR
__OM uint32_t VBAT_OV_SCLR
Definition: tle986x.h:5213
CPU_Type::PRI_SSC2
__IOM uint32_t PRI_SSC2
Definition: tle986x.h:2215
SCU_Type::T13SUSP
__IOM uint8_t T13SUSP
Definition: tle986x.h:4566
ADC2_Type::SAMPLE_TIME_int
__IOM uint32_t SAMPLE_TIME_int
Definition: tle986x.h:638
CPU_Type::NOCP
__IOM uint32_t NOCP
Definition: tle986x.h:2421
SCUPM_Type::VBAT_UV_IE
__IOM uint32_t VBAT_UV_IE
Definition: tle986x.h:5183
BDRV_Type::DRVx_VSDUP_DIS
__IOM uint32_t DRVx_VSDUP_DIS
Definition: tle986x.h:1404
ADC1
#define ADC1
Definition: tle986x.h:5990
GPT12E_Type::IST2EUD
__IOM uint16_t IST2EUD
Definition: tle986x.h:2779
CPU_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:2013
SSC1_Type::reg
__IOM uint16_t reg
Definition: tle986x.h:5464
CPU_Type::VECTACTIVE
__IM uint32_t VECTACTIVE
Definition: tle986x.h:2255
SCUPM_Type::VDD5V_UV_STS
__IM uint32_t VDD5V_UV_STS
Definition: tle986x.h:5168
CCU6_Type::STE12
__IM uint16_t STE12
Definition: tle986x.h:1642
SCUPM_Type::DBFA
__IM uint32_t DBFA
Definition: tle986x.h:5422
CCU6_Type::STRHP
__IOM uint16_t STRHP
Definition: tle986x.h:1489
SCUPM_Type::SBFA
__IM uint32_t SBFA
Definition: tle986x.h:5432
GPT12E_Type::IST3IN
__IOM uint16_t IST3IN
Definition: tle986x.h:2780
DMA_Type::CHNL_PRIORITY_SET
__IOM uint32_t CHNL_PRIORITY_SET
Definition: tle986x.h:2713
CCU6_Type::CDIR
__IM uint16_t CDIR
Definition: tle986x.h:1643
EXINT0_MON_Int
Definition: tle986x.h:115
SCUPM_Type::VDD1V5_UV_STS
__IM uint32_t VDD1V5_UV_STS
Definition: tle986x.h:5169
SCU_Type::URIOS2
__IOM uint8_t URIOS2
Definition: tle986x.h:4553
SCU_Type::PROTECT_S
__IM uint8_t PROTECT_S
Definition: tle986x.h:4466
MF_Type::VMON_SEN_PD_N
__IOM uint32_t VMON_SEN_PD_N
Definition: tle986x.h:3048
CPU_Type::VARIANT
__IM uint32_t VARIANT
Definition: tle986x.h:2244
CCU6_Type::RESERVED20
__IM uint16_t RESERVED20
Definition: tle986x.h:1787
CCU6_Type::TRPPEN
__IOM uint16_t TRPPEN
Definition: tle986x.h:1851
CCU6_Type::T13STD
__OM uint16_t T13STD
Definition: tle986x.h:1472
SCU_Type::T3C
__OM uint8_t T3C
Definition: tle986x.h:4905
ADC1_Type::WFR4
__IOM uint32_t WFR4
Definition: tle986x.h:402
CCU6_Type::CCPOS0
__IM uint16_t CCPOS0
Definition: tle986x.h:1961
ADC2_Type::OFFS_CH9
__IM uint32_t OFFS_CH9
Definition: tle986x.h:792
ADC2_Type::SQ8
__IOM uint32_t SQ8
Definition: tle986x.h:685
CSA_Type::reg
__IO uint32_t reg
Definition: tle986x.h:2514
MemoryManagement_IRQn
Definition: tle986x.h:93
GPT12E_Type::T5UDE
__IOM uint16_t T5UDE
Definition: tle986x.h:2868
ADC2_Type::MCM_RDY
__IM uint32_t MCM_RDY
Definition: tle986x.h:637
CPU_Type::PRI_9
__IOM uint32_t PRI_9
Definition: tle986x.h:2353
SCU_Type::EXINT1RC
__OM uint8_t EXINT1RC
Definition: tle986x.h:4028
GPT12E_Type::T4RC
__IOM uint16_t T4RC
Definition: tle986x.h:2846
CPU_Type::PRI_BDRV
__IOM uint32_t PRI_BDRV
Definition: tle986x.h:2229
PMU_Type::CYC_WAKE_EN
__IOM uint8_t CYC_WAKE_EN
Definition: tle986x.h:3237
PMU_Type::RST_TFB
__IOM uint8_t RST_TFB
Definition: tle986x.h:3300
CPU_Type::VECTKEY
__IOM uint32_t VECTKEY
Definition: tle986x.h:2296
CPU_Type::PRI_UART1
__IOM uint32_t PRI_UART1
Definition: tle986x.h:2216
SCU_Type::CH6C
__OM uint8_t CH6C
Definition: tle986x.h:4962
SCUPM_Type::VDD1V5_UV_ICLR
__OM uint32_t VDD1V5_UV_ICLR
Definition: tle986x.h:5203
SCU_Type::T5IE
__IOM uint8_t T5IE
Definition: tle986x.h:4873
CPU_Type::PRI_14
__IOM uint32_t PRI_14
Definition: tle986x.h:2367
SCUPM_Type::PMU_OT_ICLR
__OM uint32_t PMU_OT_ICLR
Definition: tle986x.h:5094
SCU_Type::BRDIS
__IOM uint8_t BRDIS
Definition: tle986x.h:4387
SCU_Type::NMINVM
__IOM uint8_t NMINVM
Definition: tle986x.h:3994
SCU_Type::SSCTXIE
__IOM uint8_t SSCTXIE
Definition: tle986x.h:4802
SCU_Type::GPT12_DIS
__IOM uint8_t GPT12_DIS
Definition: tle986x.h:4229
ADC1_Type::CH4_ICLR
__OM uint32_t CH4_ICLR
Definition: tle986x.h:527
SCU_Type::FNMIOT
__IM uint8_t FNMIOT
Definition: tle986x.h:3965
SCUPM_Type::VS_OV_IE
__IOM uint32_t VS_OV_IE
Definition: tle986x.h:5188
CCU6_Type::IDLE
__IM uint16_t IDLE
Definition: tle986x.h:1891
SCU_Type::WINBEN
__IOM uint8_t WINBEN
Definition: tle986x.h:4167
ADC1_Type::WFR2
__IOM uint32_t WFR2
Definition: tle986x.h:430
CCU6_Type::DTR0
__IM uint16_t DTR0
Definition: tle986x.h:1626
TIMER2x_Type::EXF2
__IM uint8_t EXF2
Definition: tle986x.h:5689
SCUPM_Type::LS1_OC_IE
__IOM uint32_t LS1_OC_IE
Definition: tle986x.h:5380
SCU_Type::SSCRXSRCSEL
__IOM uint8_t SSCRXSRCSEL
Definition: tle986x.h:4817
SCU_Type::IE1
__IOM uint8_t IE1
Definition: tle986x.h:4097
CPU_Type::Int_SSC1
__IOM uint32_t Int_SSC1
Definition: tle986x.h:2066
SCU_Type::CH4IE
__IOM uint8_t CH4IE
Definition: tle986x.h:4784
SCU_Type::CCU6SR1
__IM uint8_t CCU6SR1
Definition: tle986x.h:3938
CPU_Type::PRI_GPT1
__IOM uint32_t PRI_GPT1
Definition: tle986x.h:2188
CPU_Type::Int_UART2
__IOM uint32_t Int_UART2
Definition: tle986x.h:2069
ADC1_Type::CHx
__IM uint32_t CHx
Definition: tle986x.h:348
CCU6_Type::ENIDLE
__IOM uint16_t ENIDLE
Definition: tle986x.h:1727
CPU_Type::ADDRESS
__IOM uint32_t ADDRESS
Definition: tle986x.h:2462
BDRV_Type::ON_SEQ_EN
__IOM uint32_t ON_SEQ_EN
Definition: tle986x.h:1303
SCUPM_Type::AMCLK1_UP_HYS
__IOM uint32_t AMCLK1_UP_HYS
Definition: tle986x.h:5071
PMU_Type::LIN_WAKE
__IM uint8_t LIN_WAKE
Definition: tle986x.h:3148
SSC2_Type
SSC2 Module (SSC2)
Definition: tle986x.h:5567
SCU_Type::CH8IE
__IOM uint8_t CH8IE
Definition: tle986x.h:4788
SSC2_Type::RESERVED
__IM uint16_t RESERVED
Definition: tle986x.h:5594
CPU_Type::Int_ADC2
__IM uint32_t Int_ADC2
Definition: tle986x.h:2164
CCU6_Type::SIDLE
__OM uint16_t SIDLE
Definition: tle986x.h:1770
CPU_Type::MSTERR
__IOM uint32_t MSTERR
Definition: tle986x.h:2408
TIMER2x_Type::C_T2
__IOM uint8_t C_T2
Definition: tle986x.h:5685
SCUPM_Type::PMU_OTWARN_ICLR
__OM uint32_t PMU_OTWARN_ICLR
Definition: tle986x.h:5092
LIN_Type::M_SM_ERR_CLR
__IOM uint32_t M_SM_ERR_CLR
Definition: tle986x.h:3004
CCU6_Type::ICC61R
__IM uint16_t ICC61R
Definition: tle986x.h:1879
MF_Type::ADC1_CH1_SEL
__IOM uint32_t ADC1_CH1_SEL
Definition: tle986x.h:3038
CCU6_Type::ICC62F
__IM uint16_t ICC62F
Definition: tle986x.h:1882
CCU6_Type::RESERVED8
__IM uint16_t RESERVED8
Definition: tle986x.h:1591
CCU6_Type::ENCC61F
__IOM uint16_t ENCC61F
Definition: tle986x.h:1713
GPT12E_Type::IST3EUD
__IOM uint16_t IST3EUD
Definition: tle986x.h:2781
CCU6_Type::RESERVED7
__IM uint16_t RESERVED7
Definition: tle986x.h:1580
SCU_Type::EXINT1IS
__IOM uint8_t EXINT1IS
Definition: tle986x.h:4510
TIMER3_Type
TIMER3 Module (TIMER3)
Definition: tle986x.h:5791
MF_Type::ADC3_INN_SEL
__IOM uint32_t ADC3_INN_SEL
Definition: tle986x.h:3037
ADC2_Type::CNT_UP_CH9
__IM uint32_t CNT_UP_CH9
Definition: tle986x.h:1133
BDRV_Type::LS2_DCS_EN
__IOM uint32_t LS2_DCS_EN
Definition: tle986x.h:1252
SCU_Type::SSCTXSRCSEL
__IOM uint8_t SSCTXSRCSEL
Definition: tle986x.h:4816
SCU_Type::RSBEC
__OM uint8_t RSBEC
Definition: tle986x.h:4770
BDRV_Type::HS2_DS_STS
__IM uint32_t HS2_DS_STS
Definition: tle986x.h:1271
CPU_Type::ISRPENDING
__IM uint32_t ISRPENDING
Definition: tle986x.h:2260
SCU_Type::T2EXIS
__IOM uint8_t T2EXIS
Definition: tle986x.h:4540
CPU_Type::Int_SSC1
__IM uint32_t Int_SSC1
Definition: tle986x.h:2170
SCUPM_Type::VREF5V_LOWTH_IS
__IM uint32_t VREF5V_LOWTH_IS
Definition: tle986x.h:5138
SCU_Type::EXINT0R
__IM uint8_t EXINT0R
Definition: tle986x.h:3891
SCU_Type::CH2IE
__IOM uint8_t CH2IE
Definition: tle986x.h:4782
ADC1_Type::ESM_ACTIVE
__IM uint32_t ESM_ACTIVE
Definition: tle986x.h:345
SCU_Type::CLKREL
__IOM uint8_t CLKREL
Definition: tle986x.h:4137
ADC1_Type::OF6
__IM uint32_t OF6
Definition: tle986x.h:376
CCU6_Type::T12STD
__OM uint16_t T12STD
Definition: tle986x.h:1465
PMU_Type::SUPPFAIL
__IOM uint8_t SUPPFAIL
Definition: tle986x.h:3328
SCU_Type::NMISUP
__IOM uint8_t NMISUP
Definition: tle986x.h:3999
CCU6_Type::RT12PM
__OM uint16_t RT12PM
Definition: tle986x.h:1507
DMA_Type::CHNL_PRI_ALT_SET
__IOM uint32_t CHNL_PRI_ALT_SET
Definition: tle986x.h:2688
SCUPM_Type::VBAT_UV_STS
__IM uint32_t VBAT_UV_STS
Definition: tle986x.h:5166
CCU6_Type::ENT12PM
__IOM uint16_t ENT12PM
Definition: tle986x.h:1720
CCU6_Type::STE12D
__IOM uint16_t STE12D
Definition: tle986x.h:1800
SCU_Type::CCU6SR0C
__OM uint8_t CCU6SR0C
Definition: tle986x.h:4992
MF_Type::REFBG_LOTHWARN_STS
__IM uint32_t REFBG_LOTHWARN_STS
Definition: tle986x.h:3077
BDRV_Type::VCP_LOTH1_STS
__IM uint32_t VCP_LOTH1_STS
Definition: tle986x.h:1399
SCU_Type::EXINT1
__IOM uint8_t EXINT1
Definition: tle986x.h:4011
SCU_Type::EXINT0F
__IM uint8_t EXINT0F
Definition: tle986x.h:3892
SCUPM_Type::VSD_LOWTH_IE
__IOM uint32_t VSD_LOWTH_IE
Definition: tle986x.h:5388
SCUPM_Type::STCALIB
__IOM uint32_t STCALIB
Definition: tle986x.h:5400
PMU_Type::CNF_MON_FT
__IOM uint8_t CNF_MON_FT
Definition: tle986x.h:3383
BDRV_Type::LS2_DS_STS
__IM uint32_t LS2_DS_STS
Definition: tle986x.h:1253
ADC34_Type::ADC4_RESU
__IM uint32_t ADC4_RESU
Definition: tle986x.h:1216
GPT12E_Type::T5CLR
__IOM uint16_t T5CLR
Definition: tle986x.h:2873
SCU_Type::NVMDBEC
__OM uint8_t NVMDBEC
Definition: tle986x.h:4768
CCU6_Type::SCC60R
__OM uint16_t SCC60R
Definition: tle986x.h:1756
SCU_Type::NMIPLLC
__OM uint8_t NMIPLLC
Definition: tle986x.h:3874
SCU_Type::TIEN2
__IOM uint8_t TIEN2
Definition: tle986x.h:4072
ADC2_Type::CNT_LO_CH0
__IOM uint32_t CNT_LO_CH0
Definition: tle986x.h:1036
ADC1_Type::CH7_IE
__IOM uint32_t CH7_IE
Definition: tle986x.h:511
BDRV_Type::DRV_OFF_t_1
__IOM uint32_t DRV_OFF_t_1
Definition: tle986x.h:1329
ADC2_Type::GAIN_CH0
__IOM uint32_t GAIN_CH0
Definition: tle986x.h:739
SCU_Type::CH7
__IM uint8_t CH7
Definition: tle986x.h:4840
CCU6_Type::ENCC62R
__IOM uint16_t ENCC62R
Definition: tle986x.h:1715
SCUPM_Type::VCP_LOWTH2_STS
__IM uint32_t VCP_LOWTH2_STS
Definition: tle986x.h:5354
GPT12E_Type::IST4IN
__IOM uint16_t IST4IN
Definition: tle986x.h:2782
SCU_Type::VERID
__IM uint8_t VERID
Definition: tle986x.h:4453
CCU6_Type::RT13PM
__OM uint16_t RT13PM
Definition: tle986x.h:1509
SSC1_Type::TE
__IM uint16_t TE
Definition: tle986x.h:5496
SCU_Type::ERRSYNC
__OM uint8_t ERRSYNC
Definition: tle986x.h:4442
SCU_Type::SSC1_DIS
__IOM uint8_t SSC1_DIS
Definition: tle986x.h:4226
PMU_Type::OVERVOLT
__IOM uint8_t OVERVOLT
Definition: tle986x.h:3188
SCU_Type::NVMPROTSTSL_0
__IOM uint8_t NVMPROTSTSL_0
Definition: tle986x.h:4649
SCU_Type::CPCLK_SEL
__IOM uint8_t CPCLK_SEL
Definition: tle986x.h:4184
CCU6_Type::RESERVED22
__IM uint16_t RESERVED22
Definition: tle986x.h:1821
CPU_Type::MUNSTKERR
__IOM uint32_t MUNSTKERR
Definition: tle986x.h:2407
SCUPM_Type::VSD_LOWTH_IS
__IM uint32_t VSD_LOWTH_IS
Definition: tle986x.h:5349
GPT12E_Type::T4
__IOM uint16_t T4
Definition: tle986x.h:2939
ADC1_Type::VF8
__IM uint32_t VF8
Definition: tle986x.h:330
SCUPM_Type::VREF5V_OVL_ICLR
__OM uint32_t VREF5V_OVL_ICLR
Definition: tle986x.h:5108
TIMER2x_Type::TR2
__IOM uint8_t TR2
Definition: tle986x.h:5686
GPT12E_Type::T2IRDIS
__IOM uint16_t T2IRDIS
Definition: tle986x.h:2806
ADC1_Type::OUT_CH1
__IM uint32_t OUT_CH1
Definition: tle986x.h:442
SSC1_Type::SIS
__IOM uint16_t SIS
Definition: tle986x.h:5472
PMU_Type::GPIO1_STS_3
__IM uint8_t GPIO1_STS_3
Definition: tle986x.h:3370
SCU_Type::SDADCCLK_DIV
__IOM uint8_t SDADCCLK_DIV
Definition: tle986x.h:4269
BDRV_Type::HS1DRV_OCSDN_DIS
__IOM uint32_t HS1DRV_OCSDN_DIS
Definition: tle986x.h:1375
SCU_Type::SYSCLKSEL
__IOM uint8_t SYSCLKSEL
Definition: tle986x.h:4283
PMU_Type::GPIO1_STS_2
__IM uint8_t GPIO1_STS_2
Definition: tle986x.h:3369
SCU_Type::INIT_FAIL
__IOM uint8_t INIT_FAIL
Definition: tle986x.h:4294
PMU_Type::GPIO0_FA_2
__IOM uint8_t GPIO0_FA_2
Definition: tle986x.h:3478
CPU_Type::USERSETMPEND
__IOM uint32_t USERSETMPEND
Definition: tle986x.h:2321
PORT_Type::P3
__IOM uint8_t P3
Definition: tle986x.h:3580
SCUPM_Type::CLKWDT_SD_DIS
__IOM uint32_t CLKWDT_SD_DIS
Definition: tle986x.h:5258
CCU6_Type::DTR2
__IM uint16_t DTR2
Definition: tle986x.h:1628
CPU_Type::USGFAULTACT
__IOM uint32_t USGFAULTACT
Definition: tle986x.h:2381
SSC1_Type::MS
__IOM uint16_t MS
Definition: tle986x.h:5502
SCUPM_Type::VS_UV_IE
__IOM uint32_t VS_UV_IE
Definition: tle986x.h:5184
SCU_Type
System Control Unit (SCU)
Definition: tle986x.h:3864
PORT_Type
GPIO PORTs (PORT)
Definition: tle986x.h:3568
SCU_Type::CR
__IM uint8_t CR
Definition: tle986x.h:4892
ADC1_Type::VF1
__IM uint32_t VF1
Definition: tle986x.h:445
CCU6_Type::ST12OM
__OM uint16_t ST12OM
Definition: tle986x.h:1762
SCU_Type::EXINT0RC
__OM uint8_t EXINT0RC
Definition: tle986x.h:4024
CCU6_Type::CC63ST
__IM uint16_t CC63ST
Definition: tle986x.h:1964
CPU_Type::CP0
__IOM uint32_t CP0
Definition: tle986x.h:2482
CCU6_Type::COUT61PS
__IOM uint16_t COUT61PS
Definition: tle986x.h:1969
BDRV_Type::DLY_DIAG_DIRSEL
__IOM uint32_t DLY_DIAG_DIRSEL
Definition: tle986x.h:1290
SCU_Type::NVMDBE
__IM uint8_t NVMDBE
Definition: tle986x.h:4624
SSC2_Type::RESERVED3
__IM uint16_t RESERVED3
Definition: tle986x.h:5636
ADC1_Type::EIM_ACTIVE
__IM uint32_t EIM_ACTIVE
Definition: tle986x.h:344
SSC2_Type::RESERVED4
__IM uint16_t RESERVED4
Definition: tle986x.h:5647
CPU_Type::Int_BDRV
__IOM uint32_t Int_BDRV
Definition: tle986x.h:2072
CCU6_Type::DBYP
__IOM uint16_t DBYP
Definition: tle986x.h:1696
ADC1_Type::OUT_CH4
__IM uint32_t OUT_CH4
Definition: tle986x.h:400
SCUPM_Type::VSD_UPTH_SCLR
__OM uint32_t VSD_UPTH_SCLR
Definition: tle986x.h:5320
GPT12E_Type::T4EDGE
__IOM uint16_t T4EDGE
Definition: tle986x.h:2850
SCU_Type::PLL_LOCK
__IM uint8_t PLL_LOCK
Definition: tle986x.h:4178
ADC2_Type::CNT_LO_CH5
__IOM uint32_t CNT_LO_CH5
Definition: tle986x.h:1059
SCUPM_Type::SYS_OT_ICLR
__OM uint32_t SYS_OT_ICLR
Definition: tle986x.h:5098
BDRV_Type::IDISCHARGEDIV2_N
__IOM uint32_t IDISCHARGEDIV2_N
Definition: tle986x.h:1306
SCUPM_Type::LS2_DS_IS
__IM uint32_t LS2_DS_IS
Definition: tle986x.h:5332
ADC2_Type::OUT_CH5
__IM uint32_t OUT_CH5
Definition: tle986x.h:881
CPU_Type::INTLINESNUM
__IM uint32_t INTLINESNUM
Definition: tle986x.h:1999
SCUPM_Type::PMU_OT_IS
__IM uint32_t PMU_OT_IS
Definition: tle986x.h:5128
ADC1_Type::ANON
__IOM uint32_t ANON
Definition: tle986x.h:212
SCU_Type::EXINT1R
__IM uint8_t EXINT1R
Definition: tle986x.h:3893
ADC1_Type::ch6
__IOM uint32_t ch6
Definition: tle986x.h:289
BDRV_Type::HS2_OC_STS
__IM uint32_t HS2_OC_STS
Definition: tle986x.h:1274
TIMER3_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:5801
CPU_Type::IMPRECISERR
__IOM uint32_t IMPRECISERR
Definition: tle986x.h:2413
CSA
#define CSA
Definition: tle986x.h:5995
TIMER2x_Type::TF2EN
__IOM uint8_t TF2EN
Definition: tle986x.h:5762
SSC2_Type::BSY
__IM uint16_t BSY
Definition: tle986x.h:5608
SCUPM_Type::VDD5V_OV_STS
__IM uint32_t VDD5V_OV_STS
Definition: tle986x.h:5172
CCU6_Type::CTM
__IOM uint16_t CTM
Definition: tle986x.h:1644
ADC2_Type::CNT_LO_CH6
__IM uint32_t CNT_LO_CH6
Definition: tle986x.h:1070
SCUPM_Type::AMCLK2_UP_HYS
__IOM uint32_t AMCLK2_UP_HYS
Definition: tle986x.h:5075
CPU_Type::Int_CCU6SR0
__IM uint32_t Int_CCU6SR0
Definition: tle986x.h:2166
SCU_Type::OSCDISC
__IOM uint8_t OSCDISC
Definition: tle986x.h:4124
PMU_Type::PMU_LPR
__IOM uint8_t PMU_LPR
Definition: tle986x.h:3206
PMU
#define PMU
Definition: tle986x.h:6002
BDRV_Type::HS2DRV_OCSDN_DIS
__IOM uint32_t HS2DRV_OCSDN_DIS
Definition: tle986x.h:1376
SSC1_Type::RESERVED2
__IM uint16_t RESERVED2
Definition: tle986x.h:5517
SCUPM_Type::ADC2_ESM_IE
__IOM uint32_t ADC2_ESM_IE
Definition: tle986x.h:5243
SCU_Type::uint8_t
__IM uint8_t
Definition: tle986x.h:3937
PMU_Type::MBIST_EN
__IOM uint8_t MBIST_EN
Definition: tle986x.h:3551
SCUPM_Type::VDD1V5_OV_STS
__IM uint32_t VDD1V5_OV_STS
Definition: tle986x.h:5173
PMU_Type::OVERLOAD
__IOM uint8_t OVERLOAD
Definition: tle986x.h:3189
ADC1_Type::WFR0
__IOM uint32_t WFR0
Definition: tle986x.h:458
BDRV_Type::DRV_CCP_DIS
__IOM uint32_t DRV_CCP_DIS
Definition: tle986x.h:1312
CCU6_Type::T12PM
__IM uint16_t T12PM
Definition: tle986x.h:1884
SCU_Type::EA
__IOM uint8_t EA
Definition: tle986x.h:3981
ADC2_Type::OFFS_CH3
__IOM uint32_t OFFS_CH3
Definition: tle986x.h:753
GPT12E_Type::T3EDGE
__IOM uint16_t T3EDGE
Definition: tle986x.h:2828
ADC1_Type::SQ7
__IOM uint32_t SQ7
Definition: tle986x.h:271
SCUPM_Type::SBFSTSCLR
__OM uint32_t SBFSTSCLR
Definition: tle986x.h:5443
CCU6_Type::T13MODEN
__IOM uint16_t T13MODEN
Definition: tle986x.h:1832
CCU6_Type::TRPM2
__IOM uint16_t TRPM2
Definition: tle986x.h:1847
SCUPM_Type::VSD_UPTH_ICLR
__OM uint32_t VSD_UPTH_ICLR
Definition: tle986x.h:5309
CPU_Type::Int_SSC2
__IM uint32_t Int_SSC2
Definition: tle986x.h:2171
ADC1_Type::CH6_STS
__IM uint32_t CH6_STS
Definition: tle986x.h:491
ADC1_Type::CH3_STS
__IM uint32_t CH3_STS
Definition: tle986x.h:488
SCU_Type::GPT12CAPINB
__IOM uint8_t GPT12CAPINB
Definition: tle986x.h:4524
CPU_Type::NMIPENDSET
__IOM uint32_t NMIPENDSET
Definition: tle986x.h:2268
ADC2_Type::OFFS_CH0
__IOM uint32_t OFFS_CH0
Definition: tle986x.h:738
BDRV_Type::VCP_UPTH_STS
__IM uint32_t VCP_UPTH_STS
Definition: tle986x.h:1401
CPU_Type::ISRPREEMPT
__IM uint32_t ISRPREEMPT
Definition: tle986x.h:2261
SCU_Type::WDTRS
__IOM uint8_t WDTRS
Definition: tle986x.h:4163
ADC2_Type::ESM_1
__IOM uint32_t ESM_1
Definition: tle986x.h:606
ADC1_Type::OUT_CH7
__IM uint32_t OUT_CH7
Definition: tle986x.h:358
CPU_Type::Int_CCU6SR2
__IM uint32_t Int_CCU6SR2
Definition: tle986x.h:2168
TIMER3_Type::T3_SUBM
__IOM uint32_t T3_SUBM
Definition: tle986x.h:5857
SCU_Type::CH7IE
__IOM uint8_t CH7IE
Definition: tle986x.h:4787
CCU6_Type::RT13CM
__OM uint16_t RT13CM
Definition: tle986x.h:1508
SCU_Type::T12SUSP
__IOM uint8_t T12SUSP
Definition: tle986x.h:4565
SCU_Type::NMIECCC
__OM uint8_t NMIECCC
Definition: tle986x.h:3879
ADC2_Type::SQ6
__IOM uint32_t SQ6
Definition: tle986x.h:681
ADC34_Type::ADC4_OFS_MEAS_EN
__IOM uint32_t ADC4_OFS_MEAS_EN
Definition: tle986x.h:1197
SCU_Type::EXINT2
__IOM uint8_t EXINT2
Definition: tle986x.h:4012
CPU_Type::CP3
__IOM uint32_t CP3
Definition: tle986x.h:2485
ADC2_Type::Ch2
__IOM uint32_t Ch2
Definition: tle986x.h:1146
SCU_Type::PASS
__IOM uint8_t PASS
Definition: tle986x.h:4467
SCU_Type::T3CLK_DIV
__IOM uint8_t T3CLK_DIV
Definition: tle986x.h:4270
MON_Type::PD
__IO uint8_t PD
Definition: tle986x.h:3121
SCU_Type::T2C
__OM uint8_t T2C
Definition: tle986x.h:4904
ADC2_Type::CH0
__IOM uint32_t CH0
Definition: tle986x.h:803
SSC1_Type::TB_VALUE
__IOM uint16_t TB_VALUE
Definition: tle986x.h:5514
CCU6_Type::CC61PS
__IOM uint16_t CC61PS
Definition: tle986x.h:1968
CCU6_Type::RESERVED18
__IM uint16_t RESERVED18
Definition: tle986x.h:1748
CPU_Type::SEVONPEND
__IOM uint32_t SEVONPEND
Definition: tle986x.h:2310
BDRV_Type::LS2_SUPERR_STS
__IM uint32_t LS2_SUPERR_STS
Definition: tle986x.h:1255
SCU_Type::FNMIMAP
__IM uint8_t FNMIMAP
Definition: tle986x.h:3967
SCU_Type::NVM_SFR_ADDR_ERR
__IM uint8_t NVM_SFR_ADDR_ERR
Definition: tle986x.h:4666
ADC2_Type::OFFS_CH2
__IOM uint32_t OFFS_CH2
Definition: tle986x.h:751
SCU_Type::CCU6SR2C
__OM uint8_t CCU6SR2C
Definition: tle986x.h:5005
SCUPM_Type::HS2_OC_IE
__IOM uint32_t HS2_OC_IE
Definition: tle986x.h:5383
PORT_Type::P1
__IM uint8_t P1
Definition: tle986x.h:3638
PORT_Type::P1
__IOM uint8_t P1
Definition: tle986x.h:3578
BDRV_Type::CPCLK_EN
__IOM uint32_t CPCLK_EN
Definition: tle986x.h:1422
ADC34_Type::ADC3_RESU
__IM uint32_t ADC3_RESU
Definition: tle986x.h:1215
CPU_Type::PRI_5
__IOM uint32_t PRI_5
Definition: tle986x.h:2340
CCU6_Type::INPCC61
__IOM uint16_t INPCC61
Definition: tle986x.h:1740
BDRV_Type::DRV_ON_I_4
__IOM uint32_t DRV_ON_I_4
Definition: tle986x.h:1341
DMA_Type::CHNL_ENABLE_SET
__IOM uint32_t CHNL_ENABLE_SET
Definition: tle986x.h:2665
MON_Type::RISE
__IO uint8_t RISE
Definition: tle986x.h:3119
ADC2_Type::HYST_LO_CH7
__IM uint32_t HYST_LO_CH7
Definition: tle986x.h:1074
SCUPM_Type::VDD1V5_UV_IE
__IOM uint32_t VDD1V5_UV_IE
Definition: tle986x.h:5186
SCUPM_Type::VCP_UPTH_IE
__IOM uint32_t VCP_UPTH_IE
Definition: tle986x.h:5387
CPU_Type::PRI_7
__IOM uint32_t PRI_7
Definition: tle986x.h:2342
PMU_Type::PMU_ExtWDT
__IOM uint8_t PMU_ExtWDT
Definition: tle986x.h:3208
CCU6_Type::TRPM0
__IOM uint16_t TRPM0
Definition: tle986x.h:1845
SCU_Type::EIRC
__OM uint8_t EIRC
Definition: tle986x.h:4920
SCU_Type::U_TX_CONDIS
__IOM uint8_t U_TX_CONDIS
Definition: tle986x.h:4513
ADC1_Type::CH4_STS
__IM uint32_t CH4_STS
Definition: tle986x.h:489
SCU_Type::T5
__IM uint8_t T5
Definition: tle986x.h:4890
GPT12E_Type::T4CHDIR
__IOM uint16_t T4CHDIR
Definition: tle986x.h:2851
SCU_Type::T2EXCON
__IOM uint8_t T2EXCON
Definition: tle986x.h:4526
CPU_Type::PENDSVCLR
__OM uint32_t PENDSVCLR
Definition: tle986x.h:2265
SCUPM_Type::LS2_DS_IE
__IOM uint32_t LS2_DS_IE
Definition: tle986x.h:5374
BDRV_Type::CP_RDY_EN
__IOM uint32_t CP_RDY_EN
Definition: tle986x.h:1391
SCU_Type::NVMPROTSTSL_3
__IOM uint8_t NVMPROTSTSL_3
Definition: tle986x.h:4652
SCUPM_Type
System Control Unit for Power Modules (SCUPM)
Definition: tle986x.h:5037
GPT12E_Type::T4UD
__IOM uint16_t T4UD
Definition: tle986x.h:2844
BDRV_Type::LS1_DS_STS
__IM uint32_t LS1_DS_STS
Definition: tle986x.h:1245
SCU_Type::TCC
__IOM uint8_t TCC
Definition: tle986x.h:4717
ADC2_Type::OFFS_CH4
__IOM uint32_t OFFS_CH4
Definition: tle986x.h:764
GPT12E_Type::T6SR
__IOM uint16_t T6SR
Definition: tle986x.h:2895
CCU6_Type::CC60ST
__IM uint16_t CC60ST
Definition: tle986x.h:1958
ADC34_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:1182
SCU_Type::SSCTX
__IM uint8_t SSCTX
Definition: tle986x.h:4821
SSC2_Type::PE
__IM uint16_t PE
Definition: tle986x.h:5606
SCU_Type::T3_SUSP
__IOM uint8_t T3_SUSP
Definition: tle986x.h:4581
ADC34_Type::ADC34_DITHEN
__IOM uint32_t ADC34_DITHEN
Definition: tle986x.h:1203
SCUPM_Type::VCP_LOWTH2_IE
__IOM uint32_t VCP_LOWTH2_IE
Definition: tle986x.h:5385
ADC2_Type::HYST_LO_CH6
__IM uint32_t HYST_LO_CH6
Definition: tle986x.h:1071
MF_Type::P2_5_ADC_SEL
__IOM uint32_t P2_5_ADC_SEL
Definition: tle986x.h:3033
SCU_Type::ROM_ADDR_ERR
__IM uint8_t ROM_ADDR_ERR
Definition: tle986x.h:4668
CCU6_Type::ISCC62
__IOM uint16_t ISCC62
Definition: tle986x.h:1905
SCU_Type::CCU6SR3C
__OM uint8_t CCU6SR3C
Definition: tle986x.h:5007
CPU_Type::CP10
__IOM uint32_t CP10
Definition: tle986x.h:2491
LIN_Type::M_SM_ERR
__IM uint32_t M_SM_ERR
Definition: tle986x.h:2988
MF_Type::SYS_OTWARN_STS
__IM uint32_t SYS_OTWARN_STS
Definition: tle986x.h:3065
ADC1_Type::CH0_IE
__IOM uint32_t CH0_IE
Definition: tle986x.h:504
ADC2_Type::GAIN_CH4
__IOM uint32_t GAIN_CH4
Definition: tle986x.h:765
CPU_Type::Int_SSC2
__IOM uint32_t Int_SSC2
Definition: tle986x.h:2067
BDRV_Type::LS1_DCS_EN
__IOM uint32_t LS1_DCS_EN
Definition: tle986x.h:1244
GPT12E_Type::T6OE
__IOM uint16_t T6OE
Definition: tle986x.h:2890
ADC2_Type::CALIB_EN
__IOM uint32_t CALIB_EN
Definition: tle986x.h:623
GPT12E_Type::T3RDIR
__IM uint16_t T3RDIR
Definition: tle986x.h:2830
CCU6_Type::STRMCM
__IOM uint16_t STRMCM
Definition: tle986x.h:1485
SCUPM_Type::VREF5V_LOWTH_IE
__IOM uint32_t VREF5V_LOWTH_IE
Definition: tle986x.h:5238
SCU_Type::T2
__IM uint8_t T2
Definition: tle986x.h:4887
PMU_Type::MON_WAKE
__IM uint8_t MON_WAKE
Definition: tle986x.h:3149
ADC2_Type::OFFS_CH6
__IM uint32_t OFFS_CH6
Definition: tle986x.h:777
SCU_Type::TRSEQ2DYC
__OM uint8_t TRSEQ2DYC
Definition: tle986x.h:4977
ADC2_Type::HYST_UP_CH2
__IOM uint32_t HYST_UP_CH2
Definition: tle986x.h:1097
ADC34_Type::ADC34_EoC_CNT
__IOM uint32_t ADC34_EoC_CNT
Definition: tle986x.h:1202
TIMER3_Type::TR3H
__IOM uint32_t TR3H
Definition: tle986x.h:5840
SCUPM_Type::WDP_SEL
__IOM uint32_t WDP_SEL
Definition: tle986x.h:5277
PMU_Type::PMU_1V5_OVL
__IOM uint8_t PMU_1V5_OVL
Definition: tle986x.h:3313
BDRV_Type::HS1_ON
__IOM uint32_t HS1_ON
Definition: tle986x.h:1260
PMU_Type::PMU_ClkWDT
__IOM uint8_t PMU_ClkWDT
Definition: tle986x.h:3207
SCU_Type::PRODID
__IM uint8_t PRODID
Definition: tle986x.h:4454
SCU_Type::TIR
__IM uint8_t TIR
Definition: tle986x.h:3911
ADC2_Type::CH4
__IOM uint32_t CH4
Definition: tle986x.h:807
CCU6_Type::CCS
__IOM uint16_t CCS
Definition: tle986x.h:1555
SCUPM_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:5048
SSC1
#define SSC1
Definition: tle986x.h:6006
CCU6_Type::TRPS
__IM uint16_t TRPS
Definition: tle986x.h:1888
ADC2_Type::HYST_UP_CH5
__IOM uint32_t HYST_UP_CH5
Definition: tle986x.h:1114
CCU6
#define CCU6
Definition: tle986x.h:5994
BDRV_Type::DRV_ON_I_2
__IOM uint32_t DRV_ON_I_2
Definition: tle986x.h:1345
SCU_Type::APCLK1STS
__IM uint8_t APCLK1STS
Definition: tle986x.h:4199
PORT_Type::P2
__IM uint8_t P2
Definition: tle986x.h:3639
ADC2_Type::OUT_CH3
__IM uint32_t OUT_CH3
Definition: tle986x.h:861
CCU6_Type::T12OM
__IM uint16_t T12OM
Definition: tle986x.h:1883
SCUPM_Type::DBFSTSCLR
__OM uint32_t DBFSTSCLR
Definition: tle986x.h:5442
TIMER2x_Type::TF2
__IM uint8_t TF2
Definition: tle986x.h:5690
SCU_Type::NMINVMC
__OM uint8_t NMINVMC
Definition: tle986x.h:3875
SCUPM_Type::VS_UV_IS
__IM uint32_t VS_UV_IS
Definition: tle986x.h:5158
SCUPM_Type::CLKWDT_PD_N
__IOM uint32_t CLKWDT_PD_N
Definition: tle986x.h:5059
SCU_Type::EN
__IOM uint8_t EN
Definition: tle986x.h:4498
BDRV_Type::DRV_CCP_TIMSEL
__IOM uint32_t DRV_CCP_TIMSEL
Definition: tle986x.h:1311
SCUPM_Type::LS1_DS_IS
__IM uint32_t LS1_DS_IS
Definition: tle986x.h:5331
ADC1_Type::IN_MUX_SEL
__IOM uint32_t IN_MUX_SEL
Definition: tle986x.h:198
ADC2_Type::HYST_LO_CH3
__IOM uint32_t HYST_LO_CH3
Definition: tle986x.h:1046
CCU6_Type::RESERVED3
__IM uint16_t RESERVED3
Definition: tle986x.h:1518
SCUPM_Type::AMCLK1_LOW_TH
__IOM uint32_t AMCLK1_LOW_TH
Definition: tle986x.h:5072
ADC2_Type::CNT_LO_CH3
__IOM uint32_t CNT_LO_CH3
Definition: tle986x.h:1045
PMU_Type::GPIO0_STS_1
__IM uint8_t GPIO0_STS_1
Definition: tle986x.h:3353
LIN_Type::MODE
__IOM uint32_t MODE
Definition: tle986x.h:2987
ADC1_Type::SQ1
__IOM uint32_t SQ1
Definition: tle986x.h:255
CPU_Type::PRI_ADC2
__IOM uint32_t PRI_ADC2
Definition: tle986x.h:2190
CCU6_Type::T13IM
__IOM uint16_t T13IM
Definition: tle986x.h:1973
SCUPM_Type::HS1_OC_IE
__IOM uint32_t HS1_OC_IE
Definition: tle986x.h:5382
SCUPM_Type::HS1_DS_ICLR
__OM uint32_t HS1_DS_ICLR
Definition: tle986x.h:5291
PMU_Type::GPIO0_STS_4
__IM uint8_t GPIO0_STS_4
Definition: tle986x.h:3356
GPT12E_Type::BPS2
__IOM uint16_t BPS2
Definition: tle986x.h:2892
PMU_Type::FAIL_EN
__IOM uint8_t FAIL_EN
Definition: tle986x.h:3185
SCUPM_Type::VBAT_OV_IS
__IM uint32_t VBAT_OV_IS
Definition: tle986x.h:5161
CCU6_Type::RESERVED19
__IM uint16_t RESERVED19
Definition: tle986x.h:1774
GPT12E_Type::T2RDIR
__IM uint16_t T2RDIR
Definition: tle986x.h:2809
ADC2_Type::GAIN_CH2
__IOM uint32_t GAIN_CH2
Definition: tle986x.h:752
ADC2_Type::CNT_LO_CH8
__IM uint32_t CNT_LO_CH8
Definition: tle986x.h:1076
GPT12E_Type::T2RC
__IOM uint16_t T2RC
Definition: tle986x.h:2804
ADC34_Type::ADC3_EoC_STS
__IM uint32_t ADC3_EoC_STS
Definition: tle986x.h:1191
GPT12E_Type::RESERVED7
__IM uint16_t RESERVED7
Definition: tle986x.h:2909
SCUPM_Type::SOWCONF
__IOM uint32_t SOWCONF
Definition: tle986x.h:5278
SCU_Type::GPT12
__IOM uint8_t GPT12
Definition: tle986x.h:4594
SCUPM_Type::VBAT_OV_STS
__IM uint32_t VBAT_OV_STS
Definition: tle986x.h:5170
SCU_Type::RESLD
__IOM uint8_t RESLD
Definition: tle986x.h:4123
CCU6_Type::HSYNC
__IOM uint16_t HSYNC
Definition: tle986x.h:1695
CCU6_Type::T12PV
__IOM uint16_t T12PV
Definition: tle986x.h:1599
GPT12E_Type::ISCAPIN
__IOM uint16_t ISCAPIN
Definition: tle986x.h:2788
ADC2_Type::SQ3
__IOM uint32_t SQ3
Definition: tle986x.h:666
SCUPM_Type::AMCLK2_UP_TH
__IOM uint32_t AMCLK2_UP_TH
Definition: tle986x.h:5074
PMU_Type::PMU_1V5_FAIL_EN
__IOM uint8_t PMU_1V5_FAIL_EN
Definition: tle986x.h:3168
BDRV_Type::DLY_DIAG_SCLR
__OM uint32_t DLY_DIAG_SCLR
Definition: tle986x.h:1287
SCU_Type::SDADCIE
__IOM uint8_t SDADCIE
Definition: tle986x.h:4805
CCU6_Type::RESERVED1
__IM uint16_t RESERVED1
Definition: tle986x.h:1475
TIMER3_Type::T3H_OVF_ICLR
__OM uint32_t T3H_OVF_ICLR
Definition: tle986x.h:5868
SCU_Type::PG100TP_CHKS_ERR
__IOM uint8_t PG100TP_CHKS_ERR
Definition: tle986x.h:4296
SCU_Type::NVMCLKFAC
__IOM uint8_t NVMCLKFAC
Definition: tle986x.h:4282
PORT_Type::P7
__IM uint8_t P7
Definition: tle986x.h:3644
CPU_Type::PRI_15
__IOM uint32_t PRI_15
Definition: tle986x.h:2368
TIMER3_Type::TR3L
__IOM uint32_t TR3L
Definition: tle986x.h:5842
ADC34_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:1190
SCU_Type::XPD
__IOM uint8_t XPD
Definition: tle986x.h:4481
CCU6_Type::SSTR
__OM uint16_t SSTR
Definition: tle986x.h:1771
SCUPM_Type::VCP_LOWTH1_ICLR
__OM uint32_t VCP_LOWTH1_ICLR
Definition: tle986x.h:5303
PMU_Type::PMU_5V_OVERLOAD
__IM uint8_t PMU_5V_OVERLOAD
Definition: tle986x.h:3171
GPT12E_Type::T4R
__IOM uint16_t T4R
Definition: tle986x.h:2843
BDRV_Type::LS2DRV_OCSDN_DIS
__IOM uint32_t LS2DRV_OCSDN_DIS
Definition: tle986x.h:1368
CPU_Type::Int_UART1
__IM uint32_t Int_UART1
Definition: tle986x.h:2172
SCUPM_Type::LIN_OT_IS
__IM uint32_t LIN_OT_IS
Definition: tle986x.h:5123
MF_Type::P2_2_ADC_SEL
__IOM uint32_t P2_2_ADC_SEL
Definition: tle986x.h:3030
MF_Type::VREF5V_UV_STS
__IM uint32_t VREF5V_UV_STS
Definition: tle986x.h:3092
PORT_Type::P5
__IOM uint8_t P5
Definition: tle986x.h:3660
PMU_Type::GPIO0_RI_2
__IOM uint8_t GPIO0_RI_2
Definition: tle986x.h:3463
SCU_Type::RSBE
__IM uint8_t RSBE
Definition: tle986x.h:4626
PMU_Type::GPIO1_STS_4
__IM uint8_t GPIO1_STS_4
Definition: tle986x.h:3371
CCU6_Type::RESERVED5
__IM uint16_t RESERVED5
Definition: tle986x.h:1558
SCUPM_Type::HS2_OC_IS
__IM uint32_t HS2_OC_IS
Definition: tle986x.h:5341
ADC2_Type::OFFS_CH5
__IOM uint32_t OFFS_CH5
Definition: tle986x.h:766
CCU6_Type::RCHE
__OM uint16_t RCHE
Definition: tle986x.h:1512
MON_Type::EN
__IO uint8_t EN
Definition: tle986x.h:3117
BDRV_Type::HS1_SUPERR_STS
__IM uint32_t HS1_SUPERR_STS
Definition: tle986x.h:1264
ADC2_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:557
SSC1_Type::RECLR
__OM uint16_t RECLR
Definition: tle986x.h:5549
CCU6_Type::RESERVED26
__IM uint16_t RESERVED26
Definition: tle986x.h:1895
MF_Type::REFBG_UPTHWARN_STS
__IM uint32_t REFBG_UPTHWARN_STS
Definition: tle986x.h:3079
GPT12E_Type::T5SC
__IOM uint16_t T5SC
Definition: tle986x.h:2874
TIMER2x_Type::EXF2CLR
__OM uint8_t EXF2CLR
Definition: tle986x.h:5774
PMU_Type::EN_0V9_N
__IOM uint8_t EN_0V9_N
Definition: tle986x.h:3235
PMU_Type::GPIO0_FA_0
__IOM uint8_t GPIO0_FA_0
Definition: tle986x.h:3476
SCU_Type::SSCTXC
__OM uint8_t SSCTXC
Definition: tle986x.h:5019
CCU6_Type::MCC61S
__OM uint16_t MCC61S
Definition: tle986x.h:1528
ADC2_Type::SQ3_int
__IM uint32_t SQ3_int
Definition: tle986x.h:711
SCU_Type::SSC2RDY
__IM uint8_t SSC2RDY
Definition: tle986x.h:4856
PMU_Type::CYC_SENSE_EN
__IOM uint8_t CYC_SENSE_EN
Definition: tle986x.h:3238
ADC2_Type::Ch3
__IOM uint32_t Ch3
Definition: tle986x.h:1147
ADC2_Type::GAIN_CH6
__IM uint32_t GAIN_CH6
Definition: tle986x.h:778
SCU_Type::SSCRXC
__OM uint8_t SSCRXC
Definition: tle986x.h:5020
CCU6_Type::RSTR
__OM uint16_t RSTR
Definition: tle986x.h:1515
ADC34_Type::ADC34_REF_SEL
__IOM uint32_t ADC34_REF_SEL
Definition: tle986x.h:1194
BDRV_Type::DRVx_VCPLO_DIS
__IOM uint32_t DRVx_VCPLO_DIS
Definition: tle986x.h:1398
CCU6_Type::MSEL62
__IOM uint16_t MSEL62
Definition: tle986x.h:1694
UART_Type::SM1
__IOM uint8_t SM1
Definition: tle986x.h:5902
SCU_Type::COUTS0
__IOM uint8_t COUTS0
Definition: tle986x.h:4495
BDRV_Type::LS2_EN
__IOM uint32_t LS2_EN
Definition: tle986x.h:1249
PMU_Type::VDDEXTSHORT
__IOM uint8_t VDDEXTSHORT
Definition: tle986x.h:3330
CCU6_Type::MCC63R
__OM uint16_t MCC63R
Definition: tle986x.h:1543
CCU6_Type::DTE1
__IOM uint16_t DTE1
Definition: tle986x.h:1623
SCUPM_Type::LIN_VS_UV_SD_DIS
__IOM uint32_t LIN_VS_UV_SD_DIS
Definition: tle986x.h:5261
SSC2_Type::uint16_t
__IM uint16_t
Definition: tle986x.h:5603
SCU_Type::CCU6SR1C
__OM uint8_t CCU6SR1C
Definition: tle986x.h:4994
ADC1_Type::SQ2
__IOM uint32_t SQ2
Definition: tle986x.h:256
LIN_Type::TXD_TMOUT_STS
__IM uint32_t TXD_TMOUT_STS
Definition: tle986x.h:2991
SCUPM_Type::VCP_LOWTH2_IS
__IM uint32_t VCP_LOWTH2_IS
Definition: tle986x.h:5343
SCU_Type::NMIOWDC
__OM uint8_t NMIOWDC
Definition: tle986x.h:3877
SCU_Type::CH3IE
__IOM uint8_t CH3IE
Definition: tle986x.h:4783
BDRV_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:1237
PMU_Type::PMU_WAKE
__IOM uint8_t PMU_WAKE
Definition: tle986x.h:3204
PMU_Type::PMU_IntWDT
__IOM uint8_t PMU_IntWDT
Definition: tle986x.h:3221
ADC2_Type::TSENSE_SD_SEL
__IOM uint32_t TSENSE_SD_SEL
Definition: tle986x.h:635
TIMER2x_Type::T2RHEN
__IOM uint8_t T2RHEN
Definition: tle986x.h:5705
ADC1_Type::CH6_IE
__IOM uint32_t CH6_IE
Definition: tle986x.h:510
SCU_Type::T21_SUSP
__IOM uint8_t T21_SUSP
Definition: tle986x.h:4570
CCU6_Type::SCC61F
__OM uint16_t SCC61F
Definition: tle986x.h:1759
PMU_Type::GPIO0
__IM uint8_t GPIO0
Definition: tle986x.h:3150
SCU_Type::GPT12
__IM uint8_t GPT12
Definition: tle986x.h:4857
BDRV_Type::VCP9V_SET
__IOM uint32_t VCP9V_SET
Definition: tle986x.h:1407
SCU_Type::EXINT2FC
__OM uint8_t EXINT2FC
Definition: tle986x.h:4034
SCU_Type::OSC2L
__IM uint8_t OSC2L
Definition: tle986x.h:4480
SSC2_Type::RESERVED1
__IM uint16_t RESERVED1
Definition: tle986x.h:5614
GPT12E_Type::T5R
__IOM uint16_t T5R
Definition: tle986x.h:2866
PMU_Type::GPIO1_STS_1
__IM uint8_t GPIO1_STS_1
Definition: tle986x.h:3368
SCU_Type::PD
__IOM uint8_t PD
Definition: tle986x.h:4110
CCU6_Type::PSL
__IOM uint16_t PSL
Definition: tle986x.h:1782
TIMER3_Type::T3_RES_CONF
__IOM uint32_t T3_RES_CONF
Definition: tle986x.h:5802
CPU_Type::Int_EXINT1
__IM uint32_t Int_EXINT1
Definition: tle986x.h:2175
TIMER2x_Type::T2H
__IOM uint8_t T2H
Definition: tle986x.h:5750
SCUPM_Type::HS1_OC_ICLR
__OM uint32_t HS1_OC_ICLR
Definition: tle986x.h:5298
CCU6_Type::uint16_t
__IM uint16_t
Definition: tle986x.h:1462
TIMER3_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:5796
ADC2_Type::CH6
__IM uint32_t CH6
Definition: tle986x.h:818
ADC2_Type::Ch5_EN
__IOM uint32_t Ch5_EN
Definition: tle986x.h:936
GPT12E_Type::CLRT2EN
__IOM uint16_t CLRT2EN
Definition: tle986x.h:2847
LIN_Type::HV_MODE
__IOM uint32_t HV_MODE
Definition: tle986x.h:3002
SCU_Type::COREL
__IOM uint8_t COREL
Definition: tle986x.h:4494
ADC1_Type::VF6
__IM uint32_t VF6
Definition: tle986x.h:375
TIMER3_Type::HI
__IOM uint32_t HI
Definition: tle986x.h:5815
SCUPM_Type::VBAT_OV_ICLR
__OM uint32_t VBAT_OV_ICLR
Definition: tle986x.h:5204
CCU6_Type::RESERVED21
__IM uint16_t RESERVED21
Definition: tle986x.h:1804
PMU_Type::GPIO0_CYC_1
__IOM uint8_t GPIO0_CYC_1
Definition: tle986x.h:3492
MF
#define MF
Definition: tle986x.h:6000
BDRV_Type::VCP_LOTH2_STS
__IM uint32_t VCP_LOTH2_STS
Definition: tle986x.h:1393
BDRV_Type::LS1_PWM
__IOM uint32_t LS1_PWM
Definition: tle986x.h:1242
CCU6_Type::ISCNT13
__IOM uint16_t ISCNT13
Definition: tle986x.h:1923
SCU_Type::NMIOTC
__OM uint8_t NMIOTC
Definition: tle986x.h:3876
DMA_Type::CHNL_USEBURST_SET
__IOM uint32_t CHNL_USEBURST_SET
Definition: tle986x.h:2612
UART2
#define UART2
Definition: tle986x.h:6012
UART_Type
UARTx Module (UARTx)
Definition: tle986x.h:5886
CSA_Type
Current Sense Amplifier (CSA)
Definition: tle986x.h:2508
CPU_Type::VECTCLRACTIVE
__IOM uint32_t VECTCLRACTIVE
Definition: tle986x.h:2290
BDRV_Type::DRV_OFF_I_4
__IOM uint32_t DRV_OFF_I_4
Definition: tle986x.h:1324
SCU_Type::reg
__IOM uint8_t reg
Definition: tle986x.h:3869
SVCall_IRQn
Definition: tle986x.h:98
SCU_Type::MONR
__IM uint8_t MONR
Definition: tle986x.h:3897
LIN_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:2986
SCU_Type::CH5IE
__IOM uint8_t CH5IE
Definition: tle986x.h:4785
SCUPM_Type::VDD5V_UV_IE
__IOM uint32_t VDD5V_UV_IE
Definition: tle986x.h:5185
GPT12E_Type::T5
__IOM uint16_t T5
Definition: tle986x.h:2950
ADC2_Type::OUT_CH0
__IM uint32_t OUT_CH0
Definition: tle986x.h:831
SCU_Type::T21_DIS
__IOM uint8_t T21_DIS
Definition: tle986x.h:4243
ADC1_Type::ANON_ST
__IM uint32_t ANON_ST
Definition: tle986x.h:475
SCUPM_Type::VCP_LOWTH2_SCLR
__OM uint32_t VCP_LOWTH2_SCLR
Definition: tle986x.h:5312
GPT12E_Type::T2UDE
__IOM uint16_t T2UDE
Definition: tle986x.h:2803
SCU_Type::EOFSYNC
__OM uint8_t EOFSYNC
Definition: tle986x.h:4441
CPU_Type::Int_GPT1
__IM uint32_t Int_GPT1
Definition: tle986x.h:2162
ADC1_Type::SQ4
__IOM uint32_t SQ4
Definition: tle986x.h:258
ADC1_Type::EIM_ICLR
__OM uint32_t EIM_ICLR
Definition: tle986x.h:531
CCU6_SR0_Int
Definition: tle986x.h:107
CCU6_Type::RCC61F
__OM uint16_t RCC61F
Definition: tle986x.h:1503
CPU_Type::BKPT
__IOM uint32_t BKPT
Definition: tle986x.h:2449
SCUPM_Type::AMCLK2_FREQ
__IM uint32_t AMCLK2_FREQ
Definition: tle986x.h:5049
CPU_Type::UNALIGN_TRP
__IOM uint32_t UNALIGN_TRP
Definition: tle986x.h:2323
MF_Type::P2_3_ADC_SEL
__IOM uint32_t P2_3_ADC_SEL
Definition: tle986x.h:3031
ADC2_Type::OUT_CH2
__IM uint32_t OUT_CH2
Definition: tle986x.h:851
ADC1_Type::SQ_RUN
__IOM uint32_t SQ_RUN
Definition: tle986x.h:343
CPU_Type::PRI_10
__IOM uint32_t PRI_10
Definition: tle986x.h:2354
SCUPM_Type::VDD1V5_OV_ICLR
__OM uint32_t VDD1V5_OV_ICLR
Definition: tle986x.h:5207
CPU_Type::VECTPENDING
__IM uint32_t VECTPENDING
Definition: tle986x.h:2258
SCU_Type::EXINT0IS
__IOM uint8_t EXINT0IS
Definition: tle986x.h:4509
ADC2_Type::OUT_CH6
__IM uint32_t OUT_CH6
Definition: tle986x.h:891
ADC1_Type::WFR6
__IOM uint32_t WFR6
Definition: tle986x.h:374
PMU_Type::GPIO0_STS_2
__IM uint8_t GPIO0_STS_2
Definition: tle986x.h:3354
SCUPM_Type::SYS_OTWARN_IS
__IM uint32_t SYS_OTWARN_IS
Definition: tle986x.h:5130
ADC1_Type::CH2_STS
__IM uint32_t CH2_STS
Definition: tle986x.h:487
SCUPM_Type::VREF5V_OVL_IS
__IM uint32_t VREF5V_OVL_IS
Definition: tle986x.h:5142
SSC1_Type::TECLR
__OM uint16_t TECLR
Definition: tle986x.h:5548
SCU_Type::FNMINVM
__IM uint8_t FNMINVM
Definition: tle986x.h:3964
PMU_Type::PMU_5V_OVL
__IOM uint8_t PMU_5V_OVL
Definition: tle986x.h:3314
SCUPM_Type::HS2_DS_ICLR
__OM uint32_t HS2_DS_ICLR
Definition: tle986x.h:5293
SCU_Type::SDADCC
__OM uint8_t SDADCC
Definition: tle986x.h:4981
GPT12E_Type::T4M
__IOM uint16_t T4M
Definition: tle986x.h:2842
CCU6_Type::SWHC
__OM uint16_t SWHC
Definition: tle986x.h:1767
SCU_Type::COUTS1
__IOM uint8_t COUTS1
Definition: tle986x.h:4497
GPT12E_Type::T3UDE
__IOM uint16_t T3UDE
Definition: tle986x.h:2824
SCU_Type::MONSTS
__IM uint8_t MONSTS
Definition: tle986x.h:4086
CPU
#define CPU
Definition: tle986x.h:5996
GPT12E_Type::T6CLR
__IOM uint16_t T6CLR
Definition: tle986x.h:2894
TIMER3_Type::T3L_OVF_IE
__IOM uint32_t T3L_OVF_IE
Definition: tle986x.h:5844
ADC2_Type::CH5
__IOM uint32_t CH5
Definition: tle986x.h:808
SCU_Type::PDM1
__IOM uint8_t PDM1
Definition: tle986x.h:4682
TIMER2x_Type::DCEN
__IOM uint8_t DCEN
Definition: tle986x.h:5701
SCU
#define SCU
Definition: tle986x.h:6004
CCU6_Type::T12STR
__OM uint16_t T12STR
Definition: tle986x.h:1464
SCUPM_Type::VBAT_OV_IE
__IOM uint32_t VBAT_OV_IE
Definition: tle986x.h:5187
TIMER3_Type::T3M
__IOM uint32_t T3M
Definition: tle986x.h:5855
SSC2_Type::CIS
__IOM uint16_t CIS
Definition: tle986x.h:5585
CCU6_Type::CCPOS2
__IM uint16_t CCPOS2
Definition: tle986x.h:1963
ADC1_Type::VF7
__IM uint32_t VF7
Definition: tle986x.h:361
CPU_Type::CP4
__IOM uint32_t CP4
Definition: tle986x.h:2486
SCUPM_Type::LIN_TMOUT_IS
__IM uint32_t LIN_TMOUT_IS
Definition: tle986x.h:5124
ADC34
#define ADC34
Definition: tle986x.h:5992
SCUPM_Type::SBFSTS
__IM uint32_t SBFSTS
Definition: tle986x.h:5412
GPT12E_Type::T3OTL
__IOM uint16_t T3OTL
Definition: tle986x.h:2826
CCU6_Type::ENWHE
__IOM uint16_t ENWHE
Definition: tle986x.h:1726
ADC2_Type::CNT_UP_CH2
__IOM uint32_t CNT_UP_CH2
Definition: tle986x.h:1096
SCU_Type::TIREN2
__IOM uint8_t TIREN2
Definition: tle986x.h:4067
CCU6_Type::PSL63
__IOM uint16_t PSL63
Definition: tle986x.h:1784
CCU6_Type::RT12OM
__OM uint16_t RT12OM
Definition: tle986x.h:1506
SCUPM_Type::AMCLK1_FREQ
__IM uint32_t AMCLK1_FREQ
Definition: tle986x.h:5046
CCU6_Type::SCC62R
__OM uint16_t SCC62R
Definition: tle986x.h:1760
PMU_Type::WAKE_W_RST
__IOM uint8_t WAKE_W_RST
Definition: tle986x.h:3234
CPU_Type::BUSFAULTPENDED
__IOM uint32_t BUSFAULTPENDED
Definition: tle986x.h:2390
SCUPM_Type::VSD_UPTH_IE
__IOM uint32_t VSD_UPTH_IE
Definition: tle986x.h:5389
ADC1_Type::CH2_IE
__IOM uint32_t CH2_IE
Definition: tle986x.h:506
ADC2_Type::Ch4
__IOM uint32_t Ch4
Definition: tle986x.h:1148
CSA_Type::GAIN
__IO uint32_t GAIN
Definition: tle986x.h:2519
BDRV_Type::DRV_OFF_t_2
__IOM uint32_t DRV_OFF_t_2
Definition: tle986x.h:1327
BDRV_Type::RESERVED1
__IM uint32_t RESERVED1
Definition: tle986x.h:1381
SCU_Type::T2IS
__IOM uint8_t T2IS
Definition: tle986x.h:4538
SCU_Type::TRERRIE
__IOM uint8_t TRERRIE
Definition: tle986x.h:4799
CCU6_Type::T13SSC
__IOM uint16_t T13SSC
Definition: tle986x.h:1813
SCU_Type::EIREN2
__IOM uint8_t EIREN2
Definition: tle986x.h:4066
PMU_Type::DATA1
__IOM uint8_t DATA1
Definition: tle986x.h:3406
DebugMonitor_IRQn
Definition: tle986x.h:99
TIMER2x_Type::EXF2EN
__IOM uint8_t EXF2EN
Definition: tle986x.h:5761
UART_Type::SM2
__IOM uint8_t SM2
Definition: tle986x.h:5900
CPU_Type::USGFAULTPENDED
__IOM uint32_t USGFAULTPENDED
Definition: tle986x.h:2388
PMU_Type::GPIO0_CYC_3
__IOM uint8_t GPIO0_CYC_3
Definition: tle986x.h:3494
ADC2_Type
ADC2 Module (ADC2)
Definition: tle986x.h:548
CCU6_Type::T13CLK
__IOM uint16_t T13CLK
Definition: tle986x.h:1645
PMU_Type::uint8_t
__IM uint8_t
Definition: tle986x.h:3169
CCU6_Type::RIDLE
__OM uint16_t RIDLE
Definition: tle986x.h:1514
SCUPM_Type::LS2_OC_IE
__IOM uint32_t LS2_OC_IE
Definition: tle986x.h:5381
ADC1_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:190
ADC1_Type::ch0
__IOM uint32_t ch0
Definition: tle986x.h:283
PORT_Type::P2
__IOM uint8_t P2
Definition: tle986x.h:3579
CSA_Type::EN
__IO uint32_t EN
Definition: tle986x.h:2518
SCU_Type::T4C
__OM uint8_t T4C
Definition: tle986x.h:4906
SCUPM_Type::ADC2_ESM_IS
__IM uint32_t ADC2_ESM_IS
Definition: tle986x.h:5143
SSC2_Type::BECLR
__OM uint16_t BECLR
Definition: tle986x.h:5659
SCU_Type::WDTIN
__IOM uint8_t WDTIN
Definition: tle986x.h:4162
PMU_Type::CNF_LIN_FT
__IOM uint8_t CNF_LIN_FT
Definition: tle986x.h:3382
GPT12E_Type::T2CHDIR
__IOM uint16_t T2CHDIR
Definition: tle986x.h:2808
GPT12E_Type::MOD_TYPE
__IM uint16_t MOD_TYPE
Definition: tle986x.h:2767
ADC1_Type::CHx
__IOM uint32_t CHx
Definition: tle986x.h:223
ADC2_Type::SQ10
__IOM uint32_t SQ10
Definition: tle986x.h:698
SCU_Type::NMIECC
__IOM uint8_t NMIECC
Definition: tle986x.h:3998
CCU6_Type::DTE2
__IOM uint16_t DTE2
Definition: tle986x.h:1624
CPU_Type::TENMS
__IM uint32_t TENMS
Definition: tle986x.h:2044
CPU_Type::BFHFMIGN
__IOM uint32_t BFHFMIGN
Definition: tle986x.h:2327
LIN_Type::OC_STS
__IM uint32_t OC_STS
Definition: tle986x.h:2990
CPU_Type::DIVBYZERO
__IOM uint32_t DIVBYZERO
Definition: tle986x.h:2424
CPU_Type::SVCALLPENDED
__IOM uint32_t SVCALLPENDED
Definition: tle986x.h:2391
SCU_Type::T3_GPT12_SEL
__IOM uint8_t T3_GPT12_SEL
Definition: tle986x.h:4596
ADC1_Type::CH0_ICLR
__OM uint32_t CH0_ICLR
Definition: tle986x.h:523
CCU6_Type::SCC62F
__OM uint16_t SCC62F
Definition: tle986x.h:1761
SCUPM_Type::REFBG_UPTHWARN_IE
__IOM uint32_t REFBG_UPTHWARN_IE
Definition: tle986x.h:5237
CCU6_Type::ENCHE
__IOM uint16_t ENCHE
Definition: tle986x.h:1725
BDRV_Type::LS1_ON
__IOM uint32_t LS1_ON
Definition: tle986x.h:1243
ADC1_Type::EIM_STS
__IM uint32_t EIM_STS
Definition: tle986x.h:493
PendSV_IRQn
Definition: tle986x.h:100
SCUPM_Type::VREF5V_UPTH_IE
__IOM uint32_t VREF5V_UPTH_IE
Definition: tle986x.h:5240
SCU_Type::MU_SUSP
__IOM uint8_t MU_SUSP
Definition: tle986x.h:4582
ADC1_Type::CH2_ICLR
__OM uint32_t CH2_ICLR
Definition: tle986x.h:525
PMU_Type::GPIO1_FA_0
__IOM uint8_t GPIO1_FA_0
Definition: tle986x.h:3521
SSC2_Type::BC
__IM uint16_t BC
Definition: tle986x.h:5602
SCU_Type::RIEN2
__IOM uint8_t RIEN2
Definition: tle986x.h:4071
GPT12E_Type::IST5IN
__IOM uint16_t IST5IN
Definition: tle986x.h:2784
CPU_Type::TICKINT
__IOM uint32_t TICKINT
Definition: tle986x.h:2011
BDRV_Type::LS2_PWM
__IOM uint32_t LS2_PWM
Definition: tle986x.h:1250
CPU_Type::MEMFAULTPENDED
__IOM uint32_t MEMFAULTPENDED
Definition: tle986x.h:2389
ADC1_Type::CH5_STS
__IM uint32_t CH5_STS
Definition: tle986x.h:490
SCU_Type::RDBEC
__OM uint8_t RDBEC
Definition: tle986x.h:4766
SCUPM_Type::VCP_UPTH_ICLR
__OM uint32_t VCP_UPTH_ICLR
Definition: tle986x.h:5305
ADC2_Type::SQ8_int
__IM uint32_t SQ8_int
Definition: tle986x.h:716
ADC2_Type::SEL
__IOM uint32_t SEL
Definition: tle986x.h:592
UART_Type::REN
__IOM uint8_t REN
Definition: tle986x.h:5899
CCU6_Type::ICC60R
__IM uint16_t ICC60R
Definition: tle986x.h:1877
SCUPM_Type::VBAT_UV_SCLR
__OM uint32_t VBAT_UV_SCLR
Definition: tle986x.h:5209
PMU_Type::GPIO1_RI_3
__IOM uint8_t GPIO1_RI_3
Definition: tle986x.h:3509
ADC2_Type::ESM_0
__IOM uint32_t ESM_0
Definition: tle986x.h:604
CPU_Type::INVPC
__IOM uint32_t INVPC
Definition: tle986x.h:2420
SCU_Type::EXINT2R
__IM uint8_t EXINT2R
Definition: tle986x.h:3895
DMA_Type::CHNLS_MINUS1
__IM uint32_t CHNLS_MINUS1
Definition: tle986x.h:2549
CCU6_Type::T13STR
__OM uint16_t T13STR
Definition: tle986x.h:1471
CPU_Type::PRI_CCU6SR2
__IOM uint32_t PRI_CCU6SR2
Definition: tle986x.h:2203
TIMER2x_Type
TIMER2x Module (TIMER2x)
Definition: tle986x.h:5675
SCU_Type::WDTWINB
__IOM uint8_t WDTWINB
Definition: tle986x.h:4318
CCU6_Type::T12PRE
__IOM uint16_t T12PRE
Definition: tle986x.h:1640
SCU_Type::TRSEQ1RDYIE
__IOM uint8_t TRSEQ1RDYIE
Definition: tle986x.h:4800
ADC2_Type::Ch3_EN
__IOM uint32_t Ch3_EN
Definition: tle986x.h:934
UART1
#define UART1
Definition: tle986x.h:6011
SCUPM_Type::VS_UV_SCLR
__OM uint32_t VS_UV_SCLR
Definition: tle986x.h:5210
PMU_Type::PMU_1V5_OVERLOAD
__IM uint8_t PMU_1V5_OVERLOAD
Definition: tle986x.h:3167
CPU_Type::ENABLE
__IOM uint32_t ENABLE
Definition: tle986x.h:2010
GPT12E_Type::T4IRDIS
__IOM uint16_t T4IRDIS
Definition: tle986x.h:2849
ADC2_Type::READY
__IM uint32_t READY
Definition: tle986x.h:1161
CCU6_Type::SWHE
__OM uint16_t SWHE
Definition: tle986x.h:1769
UART_Type::TB8
__IOM uint8_t TB8
Definition: tle986x.h:5898
PMU_Type::GPIO1_CYC_1
__IOM uint8_t GPIO1_CYC_1
Definition: tle986x.h:3537
CPU_Type::Int_EXINT0
__IM uint32_t Int_EXINT0
Definition: tle986x.h:2174
CPU_Type::PENDSTSET
__IOM uint32_t PENDSTSET
Definition: tle986x.h:2264
CCU6_Type::T13RR
__OM uint16_t T13RR
Definition: tle986x.h:1466
PMU_Type::ENABLE
__IOM uint8_t ENABLE
Definition: tle986x.h:3183
BDRV_Type::HS2_EN
__IOM uint32_t HS2_EN
Definition: tle986x.h:1267
CPU_Type
CPU Core (CPU)
Definition: tle986x.h:1989
SCU_Type::T3_DIS
__IOM uint8_t T3_DIS
Definition: tle986x.h:4245
ADC2_Type::Ch2_EN
__IOM uint32_t Ch2_EN
Definition: tle986x.h:933
SCUPM_Type::VREF5V_OVL_IE
__IOM uint32_t VREF5V_OVL_IE
Definition: tle986x.h:5242
BDRV_Type::HS1_EN
__IOM uint32_t HS1_EN
Definition: tle986x.h:1258
PMU_Type::PMU_1V5DidPOR
__IOM uint8_t PMU_1V5DidPOR
Definition: tle986x.h:3210
GPT12E_Type
General Purpose Timer 12E (GPT12E)
Definition: tle986x.h:2757
BDRV_Type::LS_HS_BT_TFILT_SEL
__IOM uint32_t LS_HS_BT_TFILT_SEL
Definition: tle986x.h:1357
CPU_Type::PRI_GPT2
__IOM uint32_t PRI_GPT2
Definition: tle986x.h:2189
ADC1_Type::OF7
__IM uint32_t OF7
Definition: tle986x.h:362
ADC2_Type::Ch5
__IOM uint32_t Ch5
Definition: tle986x.h:1149
BusFault_IRQn
Definition: tle986x.h:95
PMU_Type::GPIO0_CYC_2
__IOM uint8_t GPIO0_CYC_2
Definition: tle986x.h:3493
DMA_Type::ALT_CTRL_BASE_PTR
__IM uint32_t ALT_CTRL_BASE_PTR
Definition: tle986x.h:2582
GPT12E_Type::RESERVED
__IM uint16_t RESERVED
Definition: tle986x.h:2770
SCUPM_Type::VCP_UPTH_IS
__IM uint32_t VCP_UPTH_IS
Definition: tle986x.h:5347
BDRV_Type::DRV_OFF_I_3
__IOM uint32_t DRV_OFF_I_3
Definition: tle986x.h:1326
SCUPM_Type::SYS_OT_IE
__IOM uint32_t SYS_OT_IE
Definition: tle986x.h:5234
SCUPM_Type::HS2_OC_ICLR
__OM uint32_t HS2_OC_ICLR
Definition: tle986x.h:5299
SSC1_Type::BE
__IM uint16_t BE
Definition: tle986x.h:5499
MON_Type::reg
__IO uint8_t reg
Definition: tle986x.h:3113
PMU_Type::CYC_WAKE
__IM uint8_t CYC_WAKE
Definition: tle986x.h:3154
SCUPM_Type::REFBG_LOTHWARN_IS
__IM uint32_t REFBG_LOTHWARN_IS
Definition: tle986x.h:5134
BDRV_Type::RESERVED
__IM uint32_t RESERVED
Definition: tle986x.h:1315
CCU6_Type::RWHE
__OM uint16_t RWHE
Definition: tle986x.h:1513
SCU_Type::CCU6SR3
__IM uint8_t CCU6SR3
Definition: tle986x.h:3951
UART_Type::TICLR
__OM uint8_t TICLR
Definition: tle986x.h:5926
SCU_Type::OSCSS
__IOM uint8_t OSCSS
Definition: tle986x.h:4478
CCU6_Type::MSEL61
__IOM uint16_t MSEL61
Definition: tle986x.h:1693
CCU6_Type::RESERVED10
__IM uint16_t RESERVED10
Definition: tle986x.h:1613
DMA_Int
Definition: tle986x.h:118
SCU_Type::RIEN1
__IOM uint8_t RIEN1
Definition: tle986x.h:4054
CPU_Type::Int_ADC2
__IOM uint32_t Int_ADC2
Definition: tle986x.h:2060
PMU_Type::OK
__IM uint8_t OK
Definition: tle986x.h:3190
SCU_Type::EXINT0
__IOM uint8_t EXINT0
Definition: tle986x.h:4010
CCU6_Type::T13PRE
__IOM uint16_t T13PRE
Definition: tle986x.h:1646
SCU_Type::CH4
__IM uint8_t CH4
Definition: tle986x.h:4837
LIN
#define LIN
Definition: tle986x.h:5999
ADC2_Type::CNT_UP_CH1
__IOM uint32_t CNT_UP_CH1
Definition: tle986x.h:1093
CCU6_Type::T13CV
__IOM uint16_t T13CV
Definition: tle986x.h:1947
GPT12E_Type::RESERVED3
__IM uint16_t RESERVED3
Definition: tle986x.h:2833
GPT12E_Type::RESERVED2
__IM uint16_t RESERVED2
Definition: tle986x.h:2812
CCU6_Type::COUT60PS
__IOM uint16_t COUT60PS
Definition: tle986x.h:1967
SCU_Type::PDM0
__IOM uint8_t PDM0
Definition: tle986x.h:4680
PORT_Type::P3
__IM uint8_t P3
Definition: tle986x.h:3640
CCU6_Type::RESERVED9
__IM uint16_t RESERVED9
Definition: tle986x.h:1602
LIN_Type::OT_STS
__IM uint32_t OT_STS
Definition: tle986x.h:2989
SCUPM_Type::LS2_OC_IS
__IM uint32_t LS2_OC_IS
Definition: tle986x.h:5339
BDRV_Type::VSD_LOTH_STS
__IM uint32_t VSD_LOTH_STS
Definition: tle986x.h:1403
UART_Type::VAL
__IOM uint8_t VAL
Definition: tle986x.h:5914
GPT12E_Type::T2
__IOM uint16_t T2
Definition: tle986x.h:2917
CPU_Type::RELOAD
__IOM uint32_t RELOAD
Definition: tle986x.h:2024
DMA_Type::CHNL_SW_REQUEST
__OM uint32_t CHNL_SW_REQUEST
Definition: tle986x.h:2602
CPU_Type::PRI_SSC1
__IOM uint32_t PRI_SSC1
Definition: tle986x.h:2214
ADC2_Type::OUT_CH9
__IM uint32_t OUT_CH9
Definition: tle986x.h:921
SCUPM_Type::AMCLK2_LOW_TH
__IOM uint32_t AMCLK2_LOW_TH
Definition: tle986x.h:5076
CPU_Type::BFARVALID
__IOM uint32_t BFARVALID
Definition: tle986x.h:2417
SCU_Type::WDTPR
__IM uint8_t WDTPR
Definition: tle986x.h:4166
CCU6_Type::RESERVED
__IM uint16_t RESERVED
Definition: tle986x.h:1450
SCU_Type::BGCLK_DIV
__IOM uint8_t BGCLK_DIV
Definition: tle986x.h:4183
CCU6_Type::RESERVED30
__IM uint16_t RESERVED30
Definition: tle986x.h:1950
PMU_Type::SYS_OT
__IOM uint8_t SYS_OT
Definition: tle986x.h:3316
CCU6_Type::INPCC60
__IOM uint16_t INPCC60
Definition: tle986x.h:1739
PORT_Type::P0
__IM uint8_t P0
Definition: tle986x.h:3637
CPU_Type::SLEEPDEEP
__IOM uint32_t SLEEPDEEP
Definition: tle986x.h:2308
TIMER3_Type::T3_RD_REQ
__IOM uint32_t T3_RD_REQ
Definition: tle986x.h:5837
CPU_Type::RESERVED
__IM uint32_t RESERVED
Definition: tle986x.h:1991
CPU_Type::PRIGROUP
__IOM uint32_t PRIGROUP
Definition: tle986x.h:2293
GPT12E_Type::RESERVED1
__IM uint16_t RESERVED1
Definition: tle986x.h:2791
SSC2_Type::MIS_1
__IOM uint16_t MIS_1
Definition: tle986x.h:5590
SSC2_Type::BR_VALUE
__IOM uint16_t BR_VALUE
Definition: tle986x.h:5644
CCU6_Type::RESERVED14
__IM uint16_t RESERVED14
Definition: tle986x.h:1673
SCU_Type::CH2C
__OM uint8_t CH2C
Definition: tle986x.h:4958
SSC2_Type::reg
__IOM uint16_t reg
Definition: tle986x.h:5572
ADC2_Type::RESERVED
__IM uint32_t RESERVED
Definition: tle986x.h:615
SCU_Type::CH1C
__OM uint8_t CH1C
Definition: tle986x.h:4957
SCUPM_Type::LS1_OC_ICLR
__OM uint32_t LS1_OC_ICLR
Definition: tle986x.h:5296
SCU_Type::MONRC
__OM uint8_t MONRC
Definition: tle986x.h:4036
ADC1_VREF5_Int
Definition: tle986x.h:106
SCUPM_Type::SYS_OTWARN_IE
__IOM uint32_t SYS_OTWARN_IE
Definition: tle986x.h:5233
CCU6_Type::ECT13O
__IOM uint16_t ECT13O
Definition: tle986x.h:1834
ADC34_Type
ADC34 (ADC34)
Definition: tle986x.h:1177
SCU_Type::RIREN2
__IOM uint8_t RIREN2
Definition: tle986x.h:4068
BDRV_Type::CP_EN
__IOM uint32_t CP_EN
Definition: tle986x.h:1389
SCU_Type::PDM3
__IOM uint8_t PDM3
Definition: tle986x.h:4695
GPT12E_Type::IST6EUD
__IOM uint16_t IST6EUD
Definition: tle986x.h:2787
MF_Type::VREF5V_OVL_STS
__IM uint32_t VREF5V_OVL_STS
Definition: tle986x.h:3091
ADC34_Type::ADC4_SOC
__IOM uint32_t ADC4_SOC
Definition: tle986x.h:1198
LIN_Type::FB_SM1
__IM uint32_t FB_SM1
Definition: tle986x.h:2997
BDRV_Type::DRVx_VSDLO_DIS
__IOM uint32_t DRVx_VSDLO_DIS
Definition: tle986x.h:1402
GPT12E_Type::T3R
__IOM uint16_t T3R
Definition: tle986x.h:2822
SCUPM_Type::FAIL_PS_DIS
__IOM uint32_t FAIL_PS_DIS
Definition: tle986x.h:5260
TIMER2x_Type::EXEN2
__IOM uint8_t EXEN2
Definition: tle986x.h:5687
CCU6_Type::RESERVED4
__IM uint16_t RESERVED4
Definition: tle986x.h:1547
TIMER3_Type::CNT_RDY
__IOM uint32_t CNT_RDY
Definition: tle986x.h:5839
CPU_Type::Int_ADC1
__IM uint32_t Int_ADC1
Definition: tle986x.h:2165
CCU6_Type::RESERVED11
__IM uint16_t RESERVED11
Definition: tle986x.h:1631
CCU6_Type::MCC60R
__OM uint16_t MCC60R
Definition: tle986x.h:1536
PMU_Type::PMU_PIN
__IOM uint8_t PMU_PIN
Definition: tle986x.h:3209
SCU_Type::CLKWDT_IE
__IOM uint8_t CLKWDT_IE
Definition: tle986x.h:4181
ADC1_Type::CH6_ICLR
__OM uint32_t CH6_ICLR
Definition: tle986x.h:529
CCU6_Type::ENSTR
__IOM uint16_t ENSTR
Definition: tle986x.h:1728
CCU6_Type::T12EXT
__IOM uint16_t T12EXT
Definition: tle986x.h:1924
SCUPM_Type::VDD1V5_UV_IS
__IM uint32_t VDD1V5_UV_IS
Definition: tle986x.h:5160
LIN_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:2982
ADC1_Type::SQ8
__IOM uint32_t SQ8
Definition: tle986x.h:272
SCUPM_Type::VCP_UPTH_SCLR
__OM uint32_t VCP_UPTH_SCLR
Definition: tle986x.h:5316
ADC1_Type::WFR3
__IOM uint32_t WFR3
Definition: tle986x.h:416
ADC2_Type::CH9
__IM uint32_t CH9
Definition: tle986x.h:821
SSC2_Type::PECLR
__OM uint16_t PECLR
Definition: tle986x.h:5658
PMU_Type::GPIO1_RI_2
__IOM uint8_t GPIO1_RI_2
Definition: tle986x.h:3508
SCU_Type::GPT12C
__OM uint8_t GPT12C
Definition: tle986x.h:4980
PMU_Type::GPIO0_FA_3
__IOM uint8_t GPIO0_FA_3
Definition: tle986x.h:3479
MF_Type::PMU_OTWARN_STS
__IM uint32_t PMU_OTWARN_STS
Definition: tle986x.h:3063
GPT12E_Type::T6I
__IOM uint16_t T6I
Definition: tle986x.h:2885
SSC1_Type::RB_VALUE
__IM uint16_t RB_VALUE
Definition: tle986x.h:5525
BDRV_Type::LS2_OC_STS
__IM uint32_t LS2_OC_STS
Definition: tle986x.h:1256
ADC2_Type::GAIN_CH3
__IOM uint32_t GAIN_CH3
Definition: tle986x.h:754
CPU_Type::PENDSTCLR
__OM uint32_t PENDSTCLR
Definition: tle986x.h:2263
SCU_Type::PBA0CLKREL
__IOM uint8_t PBA0CLKREL
Definition: tle986x.h:4151
CCU6_Type::INPT12
__IOM uint16_t INPT12
Definition: tle986x.h:1744
SCU_Type::CH3C
__OM uint8_t CH3C
Definition: tle986x.h:4959
CCU6_SR2_Int
Definition: tle986x.h:109
SCU_Type::NMIOWD
__IOM uint8_t NMIOWD
Definition: tle986x.h:3996
ADC2_Type::HYST_UP_CH1
__IOM uint32_t HYST_UP_CH1
Definition: tle986x.h:1094
SCUPM_Type::VBAT_UV_ICLR
__OM uint32_t VBAT_UV_ICLR
Definition: tle986x.h:5200
GPT12E_Type::RESERVED8
__IM uint16_t RESERVED8
Definition: tle986x.h:2920
UART_Type::TI
__IOM uint8_t TI
Definition: tle986x.h:5896
BDRV_Type::HS2_DCS_EN
__IOM uint32_t HS2_DCS_EN
Definition: tle986x.h:1270
SCUPM_Type::VDD5V_OV_IE
__IOM uint32_t VDD5V_OV_IE
Definition: tle986x.h:5189
ADC1_Type::PD_N
__IOM uint32_t PD_N
Definition: tle986x.h:194
ADC2_Type::REP
__IOM uint32_t REP
Definition: tle986x.h:589
UART_Type::reg
__IOM uint8_t reg
Definition: tle986x.h:5891
SCUPM_Type::VSD_UPTH_STS
__IM uint32_t VSD_UPTH_STS
Definition: tle986x.h:5362
CPU_Type::PRI_8
__IOM uint32_t PRI_8
Definition: tle986x.h:2352
BDRV_Type::DRV_ON_I_3
__IOM uint32_t DRV_ON_I_3
Definition: tle986x.h:1343
SCU_Type::ROM_PROT_ERR
__IM uint8_t ROM_PROT_ERR
Definition: tle986x.h:4667
PMU_Type::GPIO1_FA_4
__IOM uint8_t GPIO1_FA_4
Definition: tle986x.h:3525
BDRV_Type::LS1_SUPERR_STS
__IM uint32_t LS1_SUPERR_STS
Definition: tle986x.h:1246
ADC2_Type::SQ5
__IOM uint32_t SQ5
Definition: tle986x.h:679
SCUPM_Type::REFBG_UPTHWARN_ICLR
__OM uint32_t REFBG_UPTHWARN_ICLR
Definition: tle986x.h:5102
BDRV_Type::OFF_SEQ_EN
__IOM uint32_t OFF_SEQ_EN
Definition: tle986x.h:1307
CCU6_Type::MCC63S
__OM uint16_t MCC63S
Definition: tle986x.h:1533
CPU_Type::SYSRESETREQ
__IOM uint32_t SYSRESETREQ
Definition: tle986x.h:2291
CPU_Type::RETTOBASE
__IM uint32_t RETTOBASE
Definition: tle986x.h:2257
SSC1_Type::RESERVED
__IM uint16_t RESERVED
Definition: tle986x.h:5486
GPT12E_Type::T4I
__IOM uint16_t T4I
Definition: tle986x.h:2841
ADC2_Type::CH3
__IOM uint32_t CH3
Definition: tle986x.h:806
CPU_Type::PRI_EXINT0
__IOM uint32_t PRI_EXINT0
Definition: tle986x.h:2227
ADC2_Type::HYST_LO_CH4
__IOM uint32_t HYST_LO_CH4
Definition: tle986x.h:1057
PMU_Type::DATA3
__IOM uint8_t DATA3
Definition: tle986x.h:3428
CPU_Type::Int_CCU6SR1
__IOM uint32_t Int_CCU6SR1
Definition: tle986x.h:2063
CPU_Type::PRI_UART2
__IOM uint32_t PRI_UART2
Definition: tle986x.h:2217
CPU_Type::BUSFAULTACT
__IOM uint32_t BUSFAULTACT
Definition: tle986x.h:2379
PMU_Type::PMU_5V_FAIL_EN
__IOM uint8_t PMU_5V_FAIL_EN
Definition: tle986x.h:3172
SCU_Type::R
__IOM uint8_t R
Definition: tle986x.h:4351
PMU_Type::GPIO1_CYC_2
__IOM uint8_t GPIO1_CYC_2
Definition: tle986x.h:3538
GPT12E_Type::IST4EUD
__IOM uint16_t IST4EUD
Definition: tle986x.h:2783
SCU_Type::T6IE
__IOM uint8_t T6IE
Definition: tle986x.h:4874
SCU_Type::NMIMAP
__IOM uint8_t NMIMAP
Definition: tle986x.h:3997
BDRV_Type::HS1_PWM
__IOM uint32_t HS1_PWM
Definition: tle986x.h:1259
PMU_Type::GPIO0_FA_4
__IOM uint8_t GPIO0_FA_4
Definition: tle986x.h:3480
SCUPM_Type::SYS_OT_IS
__IM uint32_t SYS_OT_IS
Definition: tle986x.h:5132
ADC2_Type::HYST_LO_CH9
__IM uint32_t HYST_LO_CH9
Definition: tle986x.h:1080
DMA_Type::CHNL_PRIORITY_CLR
__OM uint32_t CHNL_PRIORITY_CLR
Definition: tle986x.h:2728
ADC1_Type::TRIG_SEL
__IOM uint32_t TRIG_SEL
Definition: tle986x.h:227
SCUPM_Type::ADC4_EOC_ICLR
__OM uint32_t ADC4_EOC_ICLR
Definition: tle986x.h:5112
SCU_Type::T4
__IM uint8_t T4
Definition: tle986x.h:4889
SCU_Type::CH6IE
__IOM uint8_t CH6IE
Definition: tle986x.h:4786
CCU6_Type::RESERVED28
__IM uint16_t RESERVED28
Definition: tle986x.h:1928
SCU_Type::OSCWDTRST
__IOM uint8_t OSCWDTRST
Definition: tle986x.h:4479
ADC2_Type::Ch1_EN
__IOM uint32_t Ch1_EN
Definition: tle986x.h:932
SCU_Type::VCOSEL
__IOM uint8_t VCOSEL
Definition: tle986x.h:4140
CCU6_Type::MCMP
__IM uint16_t MCMP
Definition: tle986x.h:1862
ADC1_Type::EIM_IE
__IOM uint32_t EIM_IE
Definition: tle986x.h:512
SCU_Type::FD_SEL
__IOM uint8_t FD_SEL
Definition: tle986x.h:4364
ADC1_Type::VF0
__IM uint32_t VF0
Definition: tle986x.h:459
CPU_Type::CP11
__IOM uint32_t CP11
Definition: tle986x.h:2492
CCU6_Type::T12RS
__OM uint16_t T12RS
Definition: tle986x.h:1459
ADC1_Type::SOC
__IOM uint32_t SOC
Definition: tle986x.h:196
SCUPM_Type::LS1_DS_IE
__IOM uint32_t LS1_DS_IE
Definition: tle986x.h:5373
CPU_Type::ENDIANNESS
__IM uint32_t ENDIANNESS
Definition: tle986x.h:2295
SSC1_Type::EN
__IOM uint16_t EN
Definition: tle986x.h:5503
CPU_Type::PRI_12
__IOM uint32_t PRI_12
Definition: tle986x.h:2365
SCU_Type::CH1IE
__IOM uint8_t CH1IE
Definition: tle986x.h:4781
ADC2_Type::CNT_LO_CH9
__IM uint32_t CNT_LO_CH9
Definition: tle986x.h:1079
CCU6_Type::CURH
__IM uint16_t CURH
Definition: tle986x.h:1866
SSC1_Type::RE
__IM uint16_t RE
Definition: tle986x.h:5497
PMU_Type::reg
__IOM uint8_t reg
Definition: tle986x.h:3144
ADC2_Type::HYST_UP_CH4
__IOM uint32_t HYST_UP_CH4
Definition: tle986x.h:1111
SCU_Type::RAM_PROT_ERR
__IM uint8_t RAM_PROT_ERR
Definition: tle986x.h:4669
SCU_Type::BGSEL
__IOM uint8_t BGSEL
Definition: tle986x.h:4388
SCU_Type::WDTREL
__IOM uint8_t WDTREL
Definition: tle986x.h:4307
SCUPM_Type::RESERVED1
__IM uint32_t RESERVED1
Definition: tle986x.h:5080
PMU_Type::STABLE
__IM uint8_t STABLE
Definition: tle986x.h:3191
CPU_Type::INVSTATE
__IOM uint32_t INVSTATE
Definition: tle986x.h:2419
system_tle986x.h
System file for TLE986x.
ADC2_Type::SQx
__IM uint32_t SQx
Definition: tle986x.h:574
CCU6_Type::RCC60F
__OM uint16_t RCC60F
Definition: tle986x.h:1501
ADC1_Type::OF2
__IM uint32_t OF2
Definition: tle986x.h:432
UART_Type::RI
__IOM uint8_t RI
Definition: tle986x.h:5895
SCU_Type::CCU6_DIS
__IOM uint8_t CCU6_DIS
Definition: tle986x.h:4227
SCU_Type::T12PM_DMAEN
__IOM uint8_t T12PM_DMAEN
Definition: tle986x.h:4819
CPU_Type::DEBUGEVT
__IOM uint32_t DEBUGEVT
Definition: tle986x.h:2438
TIMER3_Type::T3L_OVF_ICLR
__OM uint32_t T3L_OVF_ICLR
Definition: tle986x.h:5870
SCU_Type::EOFSYN
__IM uint8_t EOFSYN
Definition: tle986x.h:4390
BDRV_Type::HS2_OC_DIS
__IOM uint32_t HS2_OC_DIS
Definition: tle986x.h:1275
CPU_Type::CP1
__IOM uint32_t CP1
Definition: tle986x.h:2483
ADC34_Type::ADC34_DITHVAL
__IOM uint32_t ADC34_DITHVAL
Definition: tle986x.h:1204
MF_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:3025
PMU_Type::WAKE_STS
__IM uint8_t WAKE_STS
Definition: tle986x.h:3341
CPU_Type::PRI_11
__IOM uint32_t PRI_11
Definition: tle986x.h:2355
SCU_Type::TRSEQ2RDYIE
__IOM uint8_t TRSEQ2RDYIE
Definition: tle986x.h:4801
BDRV_Type::DRV_ON_t_2
__IOM uint32_t DRV_ON_t_2
Definition: tle986x.h:1344
CCU6_Type::T13RSEL
__IOM uint16_t T13RSEL
Definition: tle986x.h:1818
BDRV_Type::DLY_DIAG_CHSEL
__IOM uint32_t DLY_DIAG_CHSEL
Definition: tle986x.h:1289
PORT_Type::P5
__IM uint8_t P5
Definition: tle986x.h:3642
CPU_Type::CP6
__IOM uint32_t CP6
Definition: tle986x.h:2488
CCU6_Type::ST13CM
__OM uint16_t ST13CM
Definition: tle986x.h:1764
CPU_Type::Int_CCU6SR3
__IM uint32_t Int_CCU6SR3
Definition: tle986x.h:2169
SCU_Type::SD
__IOM uint8_t SD
Definition: tle986x.h:4111
BDRV_Type::HS2_ON
__IOM uint32_t HS2_ON
Definition: tle986x.h:1269
SCU_Type::APCLK3SCLR
__IOM uint8_t APCLK3SCLR
Definition: tle986x.h:4201
PORT_Type::uint8_t
__IM uint8_t
Definition: tle986x.h:3844
DMA_Type::CHNL_PRI_ALT_CLR
__OM uint32_t CHNL_PRI_ALT_CLR
Definition: tle986x.h:2703
ADC1_Type::VF4
__IM uint32_t VF4
Definition: tle986x.h:403
SCUPM_Type::LIN_TMOUT_ICLR
__OM uint32_t LIN_TMOUT_ICLR
Definition: tle986x.h:5090
BDRV_Type::LS2DRV_FDISCHG_DIS
__IOM uint32_t LS2DRV_FDISCHG_DIS
Definition: tle986x.h:1365
SCU_Type::NMIOT
__IOM uint8_t NMIOT
Definition: tle986x.h:3995
SSC1_Type::MIS_0
__IOM uint16_t MIS_0
Definition: tle986x.h:5468
GPT12E_Type::T2R
__IOM uint16_t T2R
Definition: tle986x.h:2801
CCU6_Type::STE12U
__IOM uint16_t STE12U
Definition: tle986x.h:1799
BDRV_Type::LS1DRV_FDISCHG_DIS
__IOM uint32_t LS1DRV_FDISCHG_DIS
Definition: tle986x.h:1364
GPT12E_Type::T4UDE
__IOM uint16_t T4UDE
Definition: tle986x.h:2845
SSC2_Type::SIS
__IOM uint16_t SIS
Definition: tle986x.h:5580
BDRV_Type::HS2_SUPERR_STS
__IM uint32_t HS2_SUPERR_STS
Definition: tle986x.h:1273
SysTick_IRQn
Definition: tle986x.h:101
BDRV_Type::DITH_LOWER
__IOM uint32_t DITH_LOWER
Definition: tle986x.h:1418
SCU_Type::SL
__IOM uint8_t SL
Definition: tle986x.h:4109
SCU_Type::EXINT2_EN
__IOM uint8_t EXINT2_EN
Definition: tle986x.h:4070
SCU_Type::STRDY
__IM uint8_t STRDY
Definition: tle986x.h:4852
TIMER3_Type::T3_TRIGG_INP_SEL
__IOM uint32_t T3_TRIGG_INP_SEL
Definition: tle986x.h:5800
BDRV_Type::HS2_PWM
__IOM uint32_t HS2_PWM
Definition: tle986x.h:1268
LIN_Type::RXD
__IM uint32_t RXD
Definition: tle986x.h:2995
ADC1_Type::CH1_STS
__IM uint32_t CH1_STS
Definition: tle986x.h:486
MON_Type
MON (MON)
Definition: tle986x.h:3107
ADC1_Type::OF5
__IM uint32_t OF5
Definition: tle986x.h:390
CCU6_Type::ENCC61R
__IOM uint16_t ENCC61R
Definition: tle986x.h:1711
CCU6_Type::RESERVED17
__IM uint16_t RESERVED17
Definition: tle986x.h:1731
ADC2_Type::VS_RANGE
__IOM uint32_t VS_RANGE
Definition: tle986x.h:559
SSC2_Type::MS
__IOM uint16_t MS
Definition: tle986x.h:5610
CCU6_Type::SCC61R
__OM uint16_t SCC61R
Definition: tle986x.h:1758
BDRV_Type::HS1_DCS_EN
__IOM uint32_t HS1_DCS_EN
Definition: tle986x.h:1261
SCUPM_Type::LIN_OT_IE
__IOM uint32_t LIN_OT_IE
Definition: tle986x.h:5227
ADC2_Type::CNT_UP_CH6
__IM uint32_t CNT_UP_CH6
Definition: tle986x.h:1124
CPU_Type::UNDEFINSTR
__IOM uint32_t UNDEFINSTR
Definition: tle986x.h:2418
SCU_Type::WDTSUSP
__IOM uint8_t WDTSUSP
Definition: tle986x.h:4564
SCUPM_Type::SYS_OT_PS_DIS
__IOM uint32_t SYS_OT_PS_DIS
Definition: tle986x.h:5265
ADC2_Type::CH2
__IOM uint32_t CH2
Definition: tle986x.h:805
SCU_Type::ADC1_SUSP
__IOM uint8_t ADC1_SUSP
Definition: tle986x.h:4583
SCU_Type::NMIWDT
__IOM uint8_t NMIWDT
Definition: tle986x.h:3992
ADC2_Type::SQ9
__IOM uint32_t SQ9
Definition: tle986x.h:696
SSC1_Type::RESERVED3
__IM uint16_t RESERVED3
Definition: tle986x.h:5528
SCU_Type::ERRSYN
__IM uint8_t ERRSYN
Definition: tle986x.h:4391
BDRV_Type::HS1_DS_STS
__IM uint32_t HS1_DS_STS
Definition: tle986x.h:1262
SSC1_Type::RESERVED4
__IM uint16_t RESERVED4
Definition: tle986x.h:5539
BDRV_Type::uint32_t
__IM uint32_t
Definition: tle986x.h:1285
BDRV_Type::DRV_OFF_t_3
__IOM uint32_t DRV_OFF_t_3
Definition: tle986x.h:1325
CCU6_Type::ISCC60
__IOM uint16_t ISCC60
Definition: tle986x.h:1903
CCU6_Type::MCC62S
__OM uint16_t MCC62S
Definition: tle986x.h:1530
BDRV_Type::IDISCHARGE_TRIM
__IOM uint32_t IDISCHARGE_TRIM
Definition: tle986x.h:1304
ADC1_Type::OF1
__IM uint32_t OF1
Definition: tle986x.h:446
CCU6_Type::CCV
__IM uint16_t CCV
Definition: tle986x.h:1447
ADC1_Type::ch4
__IOM uint32_t ch4
Definition: tle986x.h:287
CPU_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:1995
ADC34_Type::ADC4_EoC_STS
__IM uint32_t ADC4_EoC_STS
Definition: tle986x.h:1201
ADC2_Type::HYST_UP_CH3
__IOM uint32_t HYST_UP_CH3
Definition: tle986x.h:1100
SCU_Type::GPT12IE
__IOM uint8_t GPT12IE
Definition: tle986x.h:4804
ADC1_Type::CH0_STS
__IM uint32_t CH0_STS
Definition: tle986x.h:485
PMU_Type::GPIO0_STS_3
__IM uint8_t GPIO0_STS_3
Definition: tle986x.h:3355
PMU_Type::GPIO0_STS_0
__IM uint8_t GPIO0_STS_0
Definition: tle986x.h:3352
PMU_Type::DATA5
__IOM uint8_t DATA5
Definition: tle986x.h:3450
SCU_Type::EIR
__IM uint8_t EIR
Definition: tle986x.h:3910
SCU_Type::LOCK
__IM uint8_t LOCK
Definition: tle986x.h:4122
PMU_Type::GPIO1_STS_0
__IM uint8_t GPIO1_STS_0
Definition: tle986x.h:3367
GPT12E_Type::T6R
__IOM uint16_t T6R
Definition: tle986x.h:2887
UART_Type::RICLR
__OM uint8_t RICLR
Definition: tle986x.h:5925
ADC1_Type::ch7
__IOM uint32_t ch7
Definition: tle986x.h:290
SCU_Type::LOCKUP_EN
__IOM uint8_t LOCKUP_EN
Definition: tle986x.h:4258
CCU6_Type::RESERVED25
__IM uint16_t RESERVED25
Definition: tle986x.h:1869
CCU6_Type::RESERVED2
__IM uint16_t RESERVED2
Definition: tle986x.h:1492
ADC2_Type::TS_SD_SEL_CONF
__IOM uint32_t TS_SD_SEL_CONF
Definition: tle986x.h:634
CPU_Type::DIV_0_TRP
__IOM uint32_t DIV_0_TRP
Definition: tle986x.h:2324
SCU_Type::XTAL_ON
__IOM uint8_t XTAL_ON
Definition: tle986x.h:4108
BDRV_Type::LS1_OC_STS
__IM uint32_t LS1_OC_STS
Definition: tle986x.h:1247
ADC2_Type::CNT_LO_CH4
__IOM uint32_t CNT_LO_CH4
Definition: tle986x.h:1056
LIN_Type
Local Interconnect Network (LIN)
Definition: tle986x.h:2977
CCU6_Type::STR
__IM uint16_t STR
Definition: tle986x.h:1892
SCU_Type::NMIMAPC
__OM uint8_t NMIMAPC
Definition: tle986x.h:3878
ADC2_Type::CHx
__IM uint32_t CHx
Definition: tle986x.h:576
CCU6_Type::T13TED
__IOM uint16_t T13TED
Definition: tle986x.h:1815
SCUPM_Type::VSD_UPTH_IS
__IM uint32_t VSD_UPTH_IS
Definition: tle986x.h:5351
SCU_Type::EXINT1F
__IM uint8_t EXINT1F
Definition: tle986x.h:3894
CCU6_Type::SCC60F
__OM uint16_t SCC60F
Definition: tle986x.h:1757
SCU_Type::APCLK_SET
__IOM uint8_t APCLK_SET
Definition: tle986x.h:4179
SCUPM_Type::VCP_LOWTH1_SCLR
__OM uint32_t VCP_LOWTH1_SCLR
Definition: tle986x.h:5314
SCU_Type::T2IE
__IOM uint8_t T2IE
Definition: tle986x.h:4870
DMA_Type::reg
__IOM uint32_t reg
Definition: tle986x.h:2541
CCU6_Type::ENCC60R
__IOM uint16_t ENCC60R
Definition: tle986x.h:1707
CPU_Type::IMPLEMENTER
__IM uint32_t IMPLEMENTER
Definition: tle986x.h:2245
BDRV_Type::ICHARGE_TRIM
__IOM uint32_t ICHARGE_TRIM
Definition: tle986x.h:1300
DMA
#define DMA
Definition: tle986x.h:5997
BDRV_Type::HS2DRV_FDISCHG_DIS
__IOM uint32_t HS2DRV_FDISCHG_DIS
Definition: tle986x.h:1373
BDRV_Type::HSDRV_DS_TFILT_SEL
__IOM uint32_t HSDRV_DS_TFILT_SEL
Definition: tle986x.h:1370
SCU_Type::IE0
__IOM uint8_t IE0
Definition: tle986x.h:4083
SCU_Type::MONIE
__IOM uint8_t MONIE
Definition: tle986x.h:4085
ADC1_Type::CH3_ICLR
__OM uint32_t CH3_ICLR
Definition: tle986x.h:526
PMU_Type::GPIO1_FA_2
__IOM uint8_t GPIO1_FA_2
Definition: tle986x.h:3523
SCU_Type::RIREN1
__IOM uint8_t RIREN1
Definition: tle986x.h:4052
ADC2_Type::HYST_UP_CH0
__IOM uint32_t HYST_UP_CH0
Definition: tle986x.h:1091
ADC1_Type::RESERVED1
__IM uint32_t RESERVED1
Definition: tle986x.h:275
ADC1_Type::CH3_IE
__IOM uint32_t CH3_IE
Definition: tle986x.h:507
ADC2_Type::OUT_CH7
__IM uint32_t OUT_CH7
Definition: tle986x.h:901
CCU6_Type::ENT13PM
__IOM uint16_t ENT13PM
Definition: tle986x.h:1722
SCUPM_Type::VS_OV_STS
__IM uint32_t VS_OV_STS
Definition: tle986x.h:5171
CCU6_Type::CC60PS
__IOM uint16_t CC60PS
Definition: tle986x.h:1966
ADC2_Tmr3_Int
Definition: tle986x.h:105
SCU_Type::EXINT0FC
__OM uint8_t EXINT0FC
Definition: tle986x.h:4026
GPT12E_Type::T4RDIR
__IM uint16_t T4RDIR
Definition: tle986x.h:2852
CPU_Type::PRI_DMA
__IOM uint32_t PRI_DMA
Definition: tle986x.h:2230
GPT12E_Type::RESERVED9
__IM uint16_t RESERVED9
Definition: tle986x.h:2931
ADC1_Type::SQ6
__IOM uint32_t SQ6
Definition: tle986x.h:270
SCU_Type::SSC1RDY
__IM uint8_t SSC1RDY
Definition: tle986x.h:4855
ADC2_Type::CH6
__IOM uint32_t CH6
Definition: tle986x.h:986
SCU_Type::T2_SUSP
__IOM uint8_t T2_SUSP
Definition: tle986x.h:4567
ADC2_Type::GAIN_CH8
__IM uint32_t GAIN_CH8
Definition: tle986x.h:791
ADC2_Type::ESM_ACTIVE
__IM uint32_t ESM_ACTIVE
Definition: tle986x.h:573
DMA_Type::MASTER_ENABLE
__IM uint32_t MASTER_ENABLE
Definition: tle986x.h:2545
SCU_Type::CCU6SR0
__IM uint8_t CCU6SR0
Definition: tle986x.h:3936
CPU_Type::TBLOFF
__IOM uint32_t TBLOFF
Definition: tle986x.h:2279
CPU_Type::COUNTFLAG
__IOM uint32_t COUNTFLAG
Definition: tle986x.h:2014
SCUPM_Type::HS1_DS_IS
__IM uint32_t HS1_DS_IS
Definition: tle986x.h:5333
SCUPM_Type::VDD5V_OV_SCLR
__OM uint32_t VDD5V_OV_SCLR
Definition: tle986x.h:5215
SCU_Type::CRIE
__IOM uint8_t CRIE
Definition: tle986x.h:4875
SCU_Type::EIREN1
__IOM uint8_t EIREN1
Definition: tle986x.h:4050
CCU6_Type::ICC62R
__IM uint16_t ICC62R
Definition: tle986x.h:1881
ADC2_Type::HYST_UP_CH9
__IM uint32_t HYST_UP_CH9
Definition: tle986x.h:1134
TIMER3_Type::LO
__IOM uint32_t LO
Definition: tle986x.h:5814