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TLE986x Device Family SDK
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137 #if (UC_SERIES == TLE987)
145 #define LS1_DS SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk
146 #define LS2_DS SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk
147 #define HS1_DS SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk
148 #define HS2_DS SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk
149 #define LS1_OC SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk
150 #define LS2_OC SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk
151 #define HS1_OC SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk
152 #define HS2_OC SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk
153 #if (UC_SERIES == TLE987)
154 #define LS3_DS SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk
155 #define HS3_DS SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk
156 #define LS3_OC SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk
157 #define HS3_OC SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk
178 #if (UC_SERIES == TLE987)
242 #if (UC_SERIES == TLE987)
243 #define BDRV_ISCLR_OC (LS1_OC | HS1_OC | LS2_OC | HS2_OC | LS3_OC | HS3_OC)
244 #define BDRV_ISCLR_DS (LS1_DS | HS1_DS | LS2_DS | HS2_DS | LS3_DS | HS3_DS)
246 #define BDRV_ISCLR_OC (LS1_OC | HS1_OC | LS2_OC | HS2_OC)
247 #define BDRV_ISCLR_DS (LS1_DS | HS1_DS | LS2_DS | HS2_DS)
249 #define BDRV_IRQ_BITS (BDRV_ISCLR_OC | BDRV_ISCLR_DS)
250 #define BDRV_DS_STS_BITS BDRV_ISCLR_DS
343 #if (UC_SERIES == TLE987)
361 INLINE void BDRV_HS3_OC_Int_Clr(
void)
363 Field_Wrt32(&
SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Pos, SCUPM_BDRV_ISCLR_HS3_OC_ICLR_Msk, 1u);
367 #if (UC_SERIES == TLE987)
385 INLINE void BDRV_LS3_OC_Int_Clr(
void)
387 Field_Wrt32(&
SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Pos, SCUPM_BDRV_ISCLR_LS3_OC_ICLR_Msk, 1u);
479 #if (UC_SERIES == TLE987)
497 INLINE void BDRV_HS3_DS_Int_Clr(
void)
499 Field_Wrt32(&
SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Pos, SCUPM_BDRV_ISCLR_HS3_DS_ICLR_Msk, 1u);
503 #if (UC_SERIES == TLE987)
521 INLINE void BDRV_LS3_DS_Int_Clr(
void)
523 Field_Wrt32(&
SCUPM->BDRV_ISCLR.reg, SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Pos, SCUPM_BDRV_ISCLR_LS3_DS_ICLR_Msk, 1u);
729 #if (UC_SERIES == TLE987)
747 INLINE void BDRV_HS3_OC_Int_En(
void)
749 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk, 1u);
753 #if (UC_SERIES == TLE987)
772 INLINE void BDRV_HS3_OC_Int_Dis(
void)
774 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_OC_IE_Msk, 0u);
778 #if (UC_SERIES == TLE987)
796 INLINE void BDRV_LS3_OC_Int_En(
void)
798 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk, 1u);
802 #if (UC_SERIES == TLE987)
821 INLINE void BDRV_LS3_OC_Int_Dis(
void)
823 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_OC_IE_Msk, 0u);
1007 #if (UC_SERIES == TLE987)
1025 INLINE void BDRV_HS3_DS_Int_En(
void)
1027 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk, 1u);
1031 #if (UC_SERIES == TLE987)
1050 INLINE void BDRV_HS3_DS_Int_Dis(
void)
1052 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_HS3_DS_IE_Msk, 0u);
1056 #if (UC_SERIES == TLE987)
1074 INLINE void BDRV_LS3_DS_Int_En(
void)
1076 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk, 1u);
1080 #if (UC_SERIES == TLE987)
1099 INLINE void BDRV_LS3_DS_Int_Dis(
void)
1101 Field_Mod32(&
SCUPM->BDRV_IRQ_CTRL.reg, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Pos, SCUPM_BDRV_IRQ_CTRL_LS3_DS_IE_Msk, 0u);
1186 #if (UC_SERIES == TLE987)
1193 return u1_Field_Rd32(&
SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_HS3_OC_IS_Pos, SCUPM_BDRV_IS_HS3_OC_IS_Msk);
1197 #if (UC_SERIES == TLE987)
1204 return u1_Field_Rd32(&
SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_LS3_OC_IS_Pos, SCUPM_BDRV_IS_LS3_OC_IS_Msk);
1244 #if (UC_SERIES == TLE987)
1251 return u1_Field_Rd32(&
SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_HS3_DS_IS_Pos, SCUPM_BDRV_IS_HS3_DS_IS_Msk);
1255 #if (UC_SERIES == TLE987)
1262 return u1_Field_Rd32(&
SCUPM->BDRV_IS.reg, SCUPM_BDRV_IS_LS3_DS_IS_Pos, SCUPM_BDRV_IS_LS3_DS_IS_Msk);
1284 #if (UC_SERIES == TLE987)
INLINE void BDRV_HS1_DS_Int_En(void)
enables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:841
typ. current 199.60 mA
Definition: bdrv.h:225
typ. current 119.40 mA
Definition: bdrv.h:217
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Pos
Definition: tle986x.h:9300
typ. current 129.70 mA
Definition: bdrv.h:218
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Pos
Definition: tle986x.h:9288
typ. current 140.30 mA
Definition: bdrv.h:219
Threshold 3 for VDS at 1.00 V.
Definition: bdrv.h:197
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Msk
Definition: tle986x.h:9377
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Pos
Definition: tle986x.h:9294
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Msk
Definition: tle986x.h:9371
TBdrv_Ch_Int
This enum lists the Bridge Driver channel Interrupt configuration.
Definition: bdrv.h:184
INLINE void BDRV_VCP_LO_Int_Dis(void)
disables Charge Pump Low interrupt.
Definition: bdrv.h:1142
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Pos
Definition: tle986x.h:9366
typ. current 295.90 mA
Definition: bdrv.h:236
INLINE void BDRV_LS2_OC_Int_Dis(void)
disables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:721
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Pos
Definition: tle986x.h:9323
Threshold 2 for VDS at 0.75 V.
Definition: bdrv.h:196
typ. current 189.80 mA
Definition: bdrv.h:224
INLINE void BDRV_LS2_DS_Int_Clr(void)
clears Low Side Driver 2 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:471
#define SCUPM_BDRV_ISCLR_LS1_DS_ICLR_Pos
Definition: tle986x.h:9376
channel enabled and static on
Definition: bdrv.h:122
INLINE uint8 BDRV_LS2_OC_Int_Sts(void)
Reads the Bridge Driver Low-Side 2 Over-Current Status Flag.
Definition: bdrv.h:1178
INLINE void BDRV_HS2_OC_Int_Clr(void)
clears External High Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:313
channel enabled
Definition: bdrv.h:120
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Msk
Definition: tle986x.h:9287
INLINE void BDRV_LS2_OC_Int_En(void)
enables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:698
INLINE void BDRV_VCP_LO_Int_Clr(void)
clears Charge Pump Low interrupt flag.
Definition: bdrv.h:541
Phase2 Low Side MOSFET.
Definition: bdrv.h:132
Threshold 4 for VDS at 1.25 V.
Definition: bdrv.h:198
typ. current 86.80 mA
Definition: bdrv.h:214
INLINE void BDRV_HS1_OC_Int_En(void)
enables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:563
typ. current 180.30 mA
Definition: bdrv.h:223
Threshold 6 for VDS at 1.75 V.
Definition: bdrv.h:200
#define SCUPM_BDRV_IS_LS2_DS_IS_Msk
Definition: tle986x.h:9338
SFR low level access library.
#define SCUPM_BDRV_IS_LS1_OC_IS_Pos
Definition: tle986x.h:9331
typ. current 98.00 mA
Definition: bdrv.h:215
#define SCUPM
Definition: tle986x.h:6005
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Msk
Definition: tle986x.h:9365
typ. current 53.90 mA
Definition: bdrv.h:211
INLINE void BDRV_VCP_LO_Int_En(void)
enables Charge Pump Low interrupt.
Definition: bdrv.h:1119
#define INLINE
Definition: types.h:134
#define SCUPM_BDRV_IS_VCP_LOWTH2_IS_Msk
Definition: tle986x.h:9324
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Pos
Definition: tle986x.h:9302
#define SCUPM_BDRV_IS_HS1_OC_IS_Msk
Definition: tle986x.h:9328
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
all interrupts disable
Definition: bdrv.h:186
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:401
typ. current 150.40 mA
Definition: bdrv.h:220
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Msk
Definition: tle986x.h:9369
#define SCUPM_BDRV_ISCLR_LS2_OC_ICLR_Msk
Definition: tle986x.h:9367
Over-Current interrupt enable (On-Diagnosis)
Definition: bdrv.h:188
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Msk
Definition: tle986x.h:9363
INLINE void BDRV_HS1_DS_Int_Clr(void)
enables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:405
channel enabled with Diag.-Current Source
Definition: bdrv.h:123
typ. current 108.50 mA
Definition: bdrv.h:216
This struct lists the Bridge Driver Off Diagnosis Status Phases configuration.
Definition: bdrv.h:171
#define SCUPM_BDRV_IS_HS2_OC_IS_Msk
Definition: tle986x.h:9326
#define SCUPM_BDRV_IRQ_CTRL_VCP_LOWTH2_IE_Pos
Definition: tle986x.h:9286
typ. current 31.10 mA
Definition: bdrv.h:209
Window Watchdog 1 low level access library.
void BDRV_Set_Discharge_Current(TBdrv_Disch_Curr BDRV_Current)
Sets the trimming of the internal driver discharge current.
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Pos
Definition: tle986x.h:9372
Threshold 7 for VDS at 2.00 V.
Definition: bdrv.h:201
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Msk
Definition: tle986x.h:9293
Threshold 5 for VDS at 1.50 V.
Definition: bdrv.h:199
INLINE uint8 BDRV_LS1_OC_Int_Sts(void)
Reads the Bridge Driver Low-Side 1 Over-Current Status Flag.
Definition: bdrv.h:1160
#define SCUPM_BDRV_IS_HS2_OC_IS_Pos
Definition: tle986x.h:9325
Device specific memory layout defines.
INLINE void BDRV_LS1_DS_Int_En(void)
enables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:886
(min discharge current) lowest gate discharge current
Definition: bdrv.h:207
typ. current 218.40 mA
Definition: bdrv.h:227
(max charge current) typ. current 304 mA
Definition: bdrv.h:237
Threshold 1 for VDS at 0.50 V.
Definition: bdrv.h:195
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Pos
Definition: tle986x.h:9374
#define SCUPM_BDRV_IS_HS1_DS_IS_Pos
Definition: tle986x.h:9335
#define SCUPM_BDRV_ISCLR_HS1_DS_ICLR_Msk
Definition: tle986x.h:9373
#define SCUPM_BDRV_ISCLR_LS2_DS_ICLR_Msk
Definition: tle986x.h:9375
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
Drain-Source interrupt enable (Off-Diagnosis)
Definition: bdrv.h:187
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:341
INLINE void BDRV_LS1_OC_Int_En(void)
enables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:608
TBdrv_DSM_Threshold
Definition: bdrv.h:192
void BDRV_Init(void)
Initializes the BridgeDriver based on the IFXConfigWizard configuration.
INLINE uint8 BDRV_HS1_OC_Int_Sts(void)
Reads the Bridge Driver High-Side 1 Over-Current Status Flag.
Definition: bdrv.h:1151
TBdrv_Ch_Cfg
This enum lists the Bridge Driver High Side channel configuration.
Definition: bdrv.h:117
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Pos
Definition: tle986x.h:9296
TBdrv_Disch_Curr
Definition: bdrv.h:204
void BDRV_Clr_Sts(uint32 Sts_Bit)
clears individual status flags and interrupt status flags of the BridgeDriver
INLINE void BDRV_HS2_DS_Int_Clr(void)
clears High Side Driver 2 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:449
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
typ. current 160.80 mA
Definition: bdrv.h:221
#define SCUPM_BDRV_IS_HS1_DS_IS_Msk
Definition: tle986x.h:9336
INLINE uint8 BDRV_HS2_DS_Int_Sts(void)
Reads the Bridge Driver High-Side 2 Pre-Driver Short Status Flag.
Definition: bdrv.h:1227
Drain-Source and Over-Current interrupt enable.
Definition: bdrv.h:189
typ. current 170.10 mA
Definition: bdrv.h:222
#define SCUPM_BDRV_IS_LS2_OC_IS_Msk
Definition: tle986x.h:9330
INLINE void BDRV_LS1_DS_Int_Clr(void)
clears Low Side Driver 1 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:427
#define SCUPM_BDRV_IRQ_CTRL_LS2_DS_IE_Msk
Definition: tle986x.h:9301
Phase2 High Side MOSFET.
Definition: bdrv.h:134
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Msk
Definition: tle986x.h:9361
INLINE void BDRV_LS1_DS_Int_Dis(void)
disables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:909
#define SCUPM_BDRV_IRQ_CTRL_HS2_DS_IE_Msk
Definition: tle986x.h:9297
typ. current 254.30 mA
Definition: bdrv.h:231
bool BDRV_Diag_OpenLoad(void)
Open Load detection, detects whether a motor is connected.
INLINE void BDRV_LS1_OC_Int_Dis(void)
disables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:631
INLINE void BDRV_HS1_OC_Int_Dis(void)
disables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:586
#define SCUPM_BDRV_ISCLR_HS1_OC_ICLR_Pos
Definition: tle986x.h:9364
#define SCUPM_BDRV_ISCLR_HS2_OC_ICLR_Pos
Definition: tle986x.h:9362
Phase1 High Side MOSFET.
Definition: bdrv.h:133
#define SCUPM_BDRV_IS_LS2_DS_IS_Pos
Definition: tle986x.h:9337
INLINE uint8 BDRV_HS1_DS_Int_Sts(void)
Reads the Bridge Driver High-Side 1 Pre-Driver Short Status Flag.
Definition: bdrv.h:1209
typ. current 245.30 mA
Definition: bdrv.h:230
TBDRV_Off_Diag_Sts
This enum lists the Bridge Driver Off Diagnosis Status configuration.
Definition: bdrv.h:161
void BDRV_Set_Int_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Int Ch_Int)
sets Interrupt Enable for the individual MOSFETs (channels)
INLINE void BDRV_HS2_DS_Int_Dis(void)
disables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:954
INLINE void BDRV_LS2_DS_Int_En(void)
enables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:976
INLINE uint8 BDRV_HS2_OC_Int_Sts(void)
Reads the Bridge Driver High-Side 2 Over-Current Status Flag.
Definition: bdrv.h:1169
#define SCUPM_BDRV_IRQ_CTRL_LS2_OC_IE_Pos
Definition: tle986x.h:9292
typ. current 279.60 mA
Definition: bdrv.h:234
INLINE void BDRV_LS2_DS_Int_Dis(void)
disables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:999
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Pos
Definition: tle986x.h:9290
INLINE void BDRV_HS2_OC_Int_Dis(void)
disables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:676
typ. current 288.00 mA
Definition: bdrv.h:235
INLINE void BDRV_HS2_OC_Int_En(void)
enables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:653
void BDRV_Set_Bridge(TBdrv_Ch_Cfg LS1_Cfg, TBdrv_Ch_Cfg HS1_Cfg, TBdrv_Ch_Cfg LS2_Cfg, TBdrv_Ch_Cfg HS2_Cfg)
Sets the bridge in the desired state. For each of the four drivers the state can be defined.
#define SCUPM_BDRV_IS_HS1_OC_IS_Pos
Definition: tle986x.h:9327
INLINE void BDRV_HS2_DS_Int_En(void)
enables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:931
#define SCUPM_BDRV_IRQ_CTRL_LS1_DS_IE_Msk
Definition: tle986x.h:9303
Phase1 Low Side MOSFET.
Definition: bdrv.h:131
System Control Unit low level access library.
typ. current 19.80 mA
Definition: bdrv.h:208
TBDRV_Off_Diag BDRV_Off_Diagnosis(void)
Off-diagnosis.
#define SCUPM_BDRV_IS_LS1_DS_IS_Msk
Definition: tle986x.h:9340
INLINE void BDRV_HS1_DS_Int_Dis(void)
disables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:864
typ. current 42.30 mA
Definition: bdrv.h:210
#define SCUPM_BDRV_IS_LS1_DS_IS_Pos
Definition: tle986x.h:9339
void BDRV_Set_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Cfg Ch_Cfg)
sets an individual driver of the BridgeDriver in the desired state
#define SCUPM_BDRV_ISCLR_VCP_LOWTH2_ICLR_Pos
Definition: tle986x.h:9360
TBdrv_Ch
This enum lists the Bridge Driver channel configuration.
Definition: bdrv.h:129
INLINE uint8 BDRV_VCP_LO_Int_Sts(void)
Reads the Bridge Driver VCP Lower Threshold 2 Measurement Status Flag.
Definition: bdrv.h:1267
(HiZ) Slew Rate Control is inactive
Definition: bdrv.h:206
INLINE void BDRV_HS1_OC_Int_Clr(void)
clears External High Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:269
#define SCUPM_BDRV_IRQ_CTRL_LS1_OC_IE_Msk
Definition: tle986x.h:9295
#define SCUPM_BDRV_ISCLR_LS1_OC_ICLR_Pos
Definition: tle986x.h:9368
typ. current 227.40 mA
Definition: bdrv.h:228
#define SCUPM_BDRV_ISCLR_HS2_DS_ICLR_Pos
Definition: tle986x.h:9370
typ. current 208.90 mA
Definition: bdrv.h:226
#define SCUPM_BDRV_IS_LS2_OC_IS_Pos
Definition: tle986x.h:9329
INLINE void BDRV_LS2_OC_Int_Clr(void)
clears External Low Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:335
channel disabled
Definition: bdrv.h:119
#define SCUPM_BDRV_IS_LS1_OC_IS_Msk
Definition: tle986x.h:9332
Threshold 0 for VDS at 0.25 V.
Definition: bdrv.h:194
INLINE uint8 BDRV_LS2_DS_Int_Sts(void)
Reads the Bridge Driver Low-Side 2 Pre-Driver Short Status Flag.
Definition: bdrv.h:1236
typ. current 236.70 mA
Definition: bdrv.h:229
INLINE uint8 BDRV_LS1_DS_Int_Sts(void)
Reads the Bridge Driver Low-Side 1 Pre-Driver Short Status Flag.
Definition: bdrv.h:1218
#define SCUPM_BDRV_IRQ_CTRL_HS2_OC_IE_Msk
Definition: tle986x.h:9289
INLINE void BDRV_LS1_OC_Int_Clr(void)
clears External Low Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:291
typ. current 64.90 mA
Definition: bdrv.h:212
void BDRV_Set_DSM_Threshold(TBdrv_DSM_Threshold BDRV_Threshold)
Sets the Voltage Threshold for Drain-Source Monitoring of external FETs.
Interrupt low level access library.
channel enabled with PWM (CCU6 connection)
Definition: bdrv.h:121
#define SCUPM_BDRV_IRQ_CTRL_HS1_OC_IE_Msk
Definition: tle986x.h:9291
#define SCUPM_BDRV_IS_HS2_DS_IS_Msk
Definition: tle986x.h:9334
typ. current 76.20 mA
Definition: bdrv.h:213
#define SCUPM_BDRV_IS_HS2_DS_IS_Pos
Definition: tle986x.h:9333
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Pos
Definition: tle986x.h:9298
#define SCUPM_BDRV_IRQ_CTRL_HS1_DS_IE_Msk
Definition: tle986x.h:9299
typ. current 262.80 mA
Definition: bdrv.h:232
typ. current 271.50 mA
Definition: bdrv.h:233