 |
TLE986x Device Family SDK
|
Go to the documentation of this file.
106 #include "dma_defines.h"
137 #define DMA_CH10 (10u)
139 #define DMA_CH11 (11u)
141 #define DMA_CH12 (12u)
142 #if defined UC_FEATURE_DMA_CH13
144 #define DMA_CH13 (13u)
148 #define DMA_MASK_CH0 ((uint16)1u << DMA_CH0)
150 #define DMA_MASK_CH1 ((uint16)1u << DMA_CH1)
152 #define DMA_MASK_CH2 ((uint16)1u << DMA_CH2)
154 #define DMA_MASK_CH3 ((uint16)1u << DMA_CH3)
156 #define DMA_MASK_CH4 ((uint16)1u << DMA_CH4)
158 #define DMA_MASK_CH5 ((uint16)1u << DMA_CH5)
160 #define DMA_MASK_CH6 ((uint16)1u << DMA_CH6)
162 #define DMA_MASK_CH7 ((uint16)1u << DMA_CH7)
164 #define DMA_MASK_CH8 ((uint16)1u << DMA_CH8)
166 #define DMA_MASK_CH9 ((uint16)1u << DMA_CH9)
168 #define DMA_MASK_CH10 ((uint16)1u << DMA_CH10)
170 #define DMA_MASK_CH11 ((uint16)1u << DMA_CH11)
172 #define DMA_MASK_CH12 ((uint16)1u << DMA_CH12)
173 #if defined UC_FEATURE_DMA_CH13
175 #define DMA_MASK_CH13 ((uint16)1u << DMA_CH13)
549 #if defined UC_FEATURE_DMA_CH13
567 INLINE void DMA_CH13_Int_Clr(
void)
1158 #if defined UC_FEATURE_DMA_CH13
1176 INLINE void DMA_CH13_Int_En(
void)
1199 INLINE void DMA_CH13_Int_Dis(
void)
1336 #if (DMA_XML_VERSION >= 10200)
1623 DMA->CFG.bit.MASTER_ENABLE = 1u;
1626 #error "use IFXConfigWizard XML Version V1.2.0 or greater"
INLINE void DMA_CH6_Int_Clr(void)
clears DMA Channel 6 Interrupt flag.
Definition: dma.h:405
INLINE void DMA_Alternate_Struct_Usage_Set(uint32 mask_ch)
selects the alternate data structure for the corresponding DMA channel.
Definition: dma.h:1293
#define SCU_DMAIEN1_CH2IE_Msk
Definition: tle986x.h:8668
#define SCU_DMAIRC1CLR_CH8C_Msk
Definition: tle986x.h:8705
INLINE void DMA_Master_En(void)
Enabled the DMA master.
Definition: dma.h:1610
INLINE void DMA_CH12_Int_Dis(void)
disables DMA Channel 12 Interrupt.
Definition: dma.h:1146
INLINE void DMA_CH4_Int_En(void)
enables DMA Channel 4 Interrupt.
Definition: dma.h:763
INLINE uint32 DMA_CHx_Entry_Pri(uint8 DMA_Ch)
This function returns the address inside the primary structure in RAM for a given DMA channel.
Definition: dma.h:1317
INLINE void DMA_CH5_Int_Clr(void)
clears DMA Channel 5 Interrupt flag.
Definition: dma.h:383
#define SCU_DMAIRC1CLR_CH1C_Msk
Definition: tle986x.h:8719
#define SCU_DMAIRC2CLR_SSC2C_Pos
Definition: tle986x.h:8740
#define SCU_DMAIEN2_TRSEQ2RDYIE_Pos
Definition: tle986x.h:8680
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Pos
Definition: tle986x.h:8746
#define SCU_DMAIEN2_TRSEQ2RDYIE_Msk
Definition: tle986x.h:8681
#define SCU_DMAIRC1CLR_CH5C_Msk
Definition: tle986x.h:8711
#define SCU_DMAIRC1CLR_CH7C_Pos
Definition: tle986x.h:8706
General type declarations.
#define SCU_DMAIEN2_GPT12IE_Msk
Definition: tle986x.h:8675
INLINE void DMA_CH4_Int_Dis(void)
disables DMA Channel 4 Interrupt.
Definition: dma.h:786
#define SCU_DMAIEN2_SSCTXIE_Pos
Definition: tle986x.h:8678
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Msk
Definition: tle986x.h:8745
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Msk
Definition: tle986x.h:7788
INLINE void DMA_CH6_Int_Dis(void)
disables DMA Channel 6 Interrupt.
Definition: dma.h:876
#define SCU_DMAIRC2CLR_GPT12C_Pos
Definition: tle986x.h:8738
INLINE void DMA_CH11_Int_Dis(void)
disables DMA Channel 11 Interrupt.
Definition: dma.h:1101
#define DMA_CHNL_ENABLE_SET_CHNL_ENABLE_SET_Pos
Definition: tle986x.h:7787
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Msk
Definition: tle986x.h:7818
_TDMA_Cycle_Types
This enum lists the cycle type options for the DMA.
Definition: dma.h:207
INLINE void DMA_CH9_Int_En(void)
enables DMA Channel 9 Interrupt.
Definition: dma.h:988
#define SCU_DMAIRC1CLR_CH3C_Msk
Definition: tle986x.h:8715
INLINE void DMA_CH11_Int_En(void)
enables DMA Channel 11 Interrupt.
Definition: dma.h:1078
#define SCU_DMAIEN1_CH7IE_Msk
Definition: tle986x.h:8658
void DMA_Channel_MemSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Memory Scatter-Gather mode on a given task list.
INLINE void DMA_CH10_Int_Clr(void)
clears DMA Channel 10 Interrupt flag.
Definition: dma.h:493
#define SCU_DMAIEN2_GPT12IE_Pos
Definition: tle986x.h:8674
TDMA_Entry * DMA_Task_SctGth_Set(TDMA_Entry *entry, uint8 DMA_Ch, TDMA_Entry *Task_List, uint32 NoOfTask)
Sets up a task to be used with memory scatter-gather mode.
INLINE void DMA_CH2_Int_En(void)
enables DMA Channel 2 Interrupt.
Definition: dma.h:673
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Pos
Definition: tle986x.h:7793
#define SCU_DMAIEN1_CH1IE_Pos
Definition: tle986x.h:8669
INLINE void DMA_CH5_Int_En(void)
enables DMA Channel 5 Interrupt.
Definition: dma.h:808
SFR low level access library.
#define SCU_DMAIRC1CLR_CH6C_Pos
Definition: tle986x.h:8708
#define SCU_DMAIRC2CLR_SDADCC_Msk
Definition: tle986x.h:8737
INLINE void DMA_CH5_Int_Dis(void)
disables DMA Channel 5 Interrupt.
Definition: dma.h:831
#define SCU_DMAIRC1CLR_CH8C_Pos
Definition: tle986x.h:8704
#define SCU_DMAIRC1CLR_CH2C_Pos
Definition: tle986x.h:8716
#define INLINE
Definition: types.h:134
INLINE void Field_Mod8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:346
void DMA_Init(void)
Initializes the DMA structure in RAM and SFRs according to the ConfigWizard settings.
#define SCU_DMAIEN1_CH8IE_Msk
Definition: tle986x.h:8656
#define SCU_DMAIEN1_CH5IE_Msk
Definition: tle986x.h:8662
#define SCU_DMAIRC2CLR_GPT12C_Msk
Definition: tle986x.h:8739
#define SCU_DMAIRC2CLR_SSC2C_Msk
Definition: tle986x.h:8741
INLINE void DMA_CH2_Int_Dis(void)
disables DMA Channel 2 Interrupt.
Definition: dma.h:696
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
INLINE void DMA_CH10_Int_En(void)
enables DMA Channel 10 Interrupt.
Definition: dma.h:1033
INLINE void DMA_CH3_Int_Dis(void)
disables DMA Channel 3 Interrupt.
Definition: dma.h:741
INLINE void DMA_CH0_Int_Dis(void)
disables DMA Channel 0 Interrupt.
Definition: dma.h:606
#define SCU_DMAIEN2_TRSEQ1RDYIE_Pos
Definition: tle986x.h:8682
#define SCU_DMAIRC1CLR_CH3C_Pos
Definition: tle986x.h:8714
#define SCU_DMAIRC2CLR_SSC1C_Pos
Definition: tle986x.h:8742
#define SCU_DMAIRC1CLR_CH5C_Pos
Definition: tle986x.h:8710
#define SCU_DMAIRC2CLR_TRSEQ2DYC_Pos
Definition: tle986x.h:8744
INLINE void DMA_Software_Request_Set(uint32 mask_ch)
Set software request for DMA Channels.
Definition: dma.h:1253
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Msk
Definition: tle986x.h:7791
INLINE void DMA_CH1_Int_Clr(void)
clears DMA Channel 1 Interrupt flag.
Definition: dma.h:295
INLINE void DMA_Channel_Enable_Set(uint32 mask_ch)
enables DMA Channels.
Definition: dma.h:1233
#define SCU_DMAIEN2_SDADCIE_Pos
Definition: tle986x.h:8672
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
#define DMA_CHNL_PRI_ALT_CLR_CHNL_PRI_ALT_CLR_Pos
Definition: tle986x.h:7790
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Msk
Definition: tle986x.h:7809
enum _TDMA_Transfer_Size TDMA_Transfer_Size
void DMA_Reset_Channel(uint32 DMA_ChIdx, uint32 trans_cnt)
Resets the primary structure in RAM for a given channel and rearms it.
INLINE void DMA_CH12_Int_En(void)
enables DMA Channel 12 Interrupt.
Definition: dma.h:1123
#define SCU_DMAIEN2_SSCRXIE_Msk
Definition: tle986x.h:8677
#define SCU_DMAIEN2_SDADCIE_Msk
Definition: tle986x.h:8673
INLINE uint32 DMA_CHx_Entry_Alt(uint8 DMA_Ch)
This function returns the address inside the alternate structure in RAM for a given DMA channel.
Definition: dma.h:1305
INLINE void DMA_CH8_Int_Dis(void)
disables DMA Channel 8 Interrupt.
Definition: dma.h:966
INLINE void DMA_CH6_Int_En(void)
enables DMA Channel 6 Interrupt.
Definition: dma.h:853
INLINE void DMA_CH9_Int_Clr(void)
clears DMA Channel 9 Interrupt flag.
Definition: dma.h:471
INLINE void DMA_Primary_Struct_Usage_Set(uint32 mask_ch)
selects the primary data structure for the corresponding DMA channel.
Definition: dma.h:1273
#define SCU_DMAIEN1_CH5IE_Pos
Definition: tle986x.h:8661
#define SCU_DMAIEN1_CH6IE_Pos
Definition: tle986x.h:8659
#define SCU_DMAIEN2_SSCRXIE_Pos
Definition: tle986x.h:8676
_TDMA_Increment_Size
This enum lists the increment size options for the DMA.
Definition: dma.h:186
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
#define SCU_DMAIEN1_CH1IE_Msk
Definition: tle986x.h:8670
INLINE void DMA_CH7_Int_Dis(void)
disables DMA Channel 7 Interrupt.
Definition: dma.h:921
INLINE void DMA_CH12_Int_Clr(void)
clears DMA Channel 12 Interrupt flag.
Definition: dma.h:537
This structure lists the bit assignments for the channel_cfg memory location.
Definition: dma.h:224
#define SCU_DMAIEN1_CH6IE_Msk
Definition: tle986x.h:8660
#define DMA_CTRL_BASE_PTR_CTRL_BASE_PTR_Pos
Definition: tle986x.h:7817
INLINE void DMA_CH8_Int_En(void)
enables DMA Channel 8 Interrupt.
Definition: dma.h:943
#define SCU_DMAIEN1_CH8IE_Pos
Definition: tle986x.h:8655
INLINE void DMA_CH3_Int_En(void)
enables DMA Channel 3 Interrupt.
Definition: dma.h:718
#define SCU_DMAIRC2CLR_TRSEQ1DYC_Msk
Definition: tle986x.h:8747
#define SCU_DMAIEN1_CH4IE_Msk
Definition: tle986x.h:8664
INLINE void DMA_CH1_Int_En(void)
enables DMA Channel 1 Interrupt.
Definition: dma.h:628
INLINE void DMA_CH8_Int_Clr(void)
clears DMA Channel 8 Interrupt flag.
Definition: dma.h:449
INLINE void DMA_CH1_Int_Dis(void)
disables DMA Channel 1 Interrupt.
Definition: dma.h:651
#define SCU_DMAIRC1CLR_CH4C_Pos
Definition: tle986x.h:8712
CMSIS register HeaderFile.
#define SCU
Definition: tle986x.h:6004
#define SCU_DMAIRC1CLR_CH7C_Msk
Definition: tle986x.h:8707
#define SCU_DMAIEN1_CH4IE_Pos
Definition: tle986x.h:8663
#define SCU_DMAIRC2CLR_SSC1C_Msk
Definition: tle986x.h:8743
INLINE void DMA_CH3_Int_Clr(void)
clears DMA Channel 3 Interrupt flag.
Definition: dma.h:339
#define SCU_DMAIEN1_CH7IE_Pos
Definition: tle986x.h:8657
INLINE void DMA_CH10_Int_Dis(void)
disables DMA Channel 10 Interrupt.
Definition: dma.h:1056
#define SCU_DMAIEN1_CH3IE_Pos
Definition: tle986x.h:8665
enum _TDMA_Cycle_Types TDMA_Cycle_Types
INLINE void DMA_CH0_Int_Clr(void)
clears DMA Channel 0 Interrupt flag.
Definition: dma.h:273
_TDMA_Transfer_Size
This enum lists the transfer size options for the DMA.
Definition: dma.h:176
INLINE void DMA_CH4_Int_Clr(void)
clears DMA Channel 4 Interrupt flag.
Definition: dma.h:361
#define SCU_DMAIRC1CLR_CH2C_Msk
Definition: tle986x.h:8717
INLINE void DMA_CH2_Int_Clr(void)
clears DMA Channel 2 Interrupt flag.
Definition: dma.h:317
#define SCU_DMAIRC1CLR_CH4C_Msk
Definition: tle986x.h:8713
INLINE void DMA_Primary_Struct_Set(uint32 mask_ch)
points to the base address of the primary data structure.
Definition: dma.h:1213
#define SCU_DMAIRC2CLR_SDADCC_Pos
Definition: tle986x.h:8736
#define SCU_DMAIRC1CLR_CH1C_Pos
Definition: tle986x.h:8718
INLINE void DMA_CH7_Int_Clr(void)
clears DMA Channel 7 Interrupt flag.
Definition: dma.h:427
This structure lists the DMA transfer memory locations.
Definition: dma.h:245
#define SCU_DMAIEN1_CH2IE_Pos
Definition: tle986x.h:8667
void DMA_Channel_PerSctGth_Set(uint32 DMA_ChIdx, TDMA_Entry *Task_List, uint32 NoOfTasks)
Sets up a channel to operate in Peripheral Scatter-Gather mode on a given task list.
#define SCU_DMAIEN2_TRSEQ1RDYIE_Msk
Definition: tle986x.h:8683
#define DMA_CHNL_SW_REQUEST_CHNL_SW_REQUEST_Pos
Definition: tle986x.h:7808
enum _TDMA_Increment_Mode TDMA_Increment_Mode
INLINE void DMA_CH11_Int_Clr(void)
clears DMA Channel 11 Interrupt flag.
Definition: dma.h:515
#define SCU_DMAIRC1CLR_CH6C_Msk
Definition: tle986x.h:8709
INLINE void Field_Wrt8(volatile uint8 *reg, uint8 pos, uint8 msk, uint8 val)
This function writes a bit field in a 8-bit register.
Definition: sfr_access.h:331
enum _TDMA_Increment_Size TDMA_Increment_Size
INLINE void DMA_CH0_Int_En(void)
enables DMA Channel 0 Interrupt.
Definition: dma.h:583
void DMA_Setup_Channel(uint32 DMA_ChIdx, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up the desired DMA channel in the primary structure in RAM.
#define SCU_DMAIEN1_CH3IE_Msk
Definition: tle986x.h:8666
INLINE void DMA_CH7_Int_En(void)
enables DMA Channel 7 Interrupt.
Definition: dma.h:898
INLINE void DMA_CH9_Int_Dis(void)
disables DMA Channel 9 Interrupt.
Definition: dma.h:1011
_TDMA_Increment_Mode
This enum lists the increment mode options for the DMA.
Definition: dma.h:196
TDMA_Entry * DMA_Task_Set(TDMA_Entry *entry, TDMA_Cycle_Types cycle_type, uint8 arb_rate, uint32 addr_src, uint32 addr_dst, uint32 trans_cnt, TDMA_Transfer_Size datawidth, TDMA_Increment_Mode increment)
Sets up a task to be used in the Scatter-Gather modes.
#define SCU_DMAIEN2_SSCTXIE_Msk
Definition: tle986x.h:8679
#define DMA_CHNL_PRI_ALT_SET_CHNL_PRI_ALT_SET_Msk
Definition: tle986x.h:7794
#define DMA
Definition: tle986x.h:5997