TLE986x Device Family SDK
Data Fields
SCU_Type Struct Reference

Detailed Description

System Control Unit (SCU)

#include <tle986x.h>

Data Fields

union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   NMIWDTC: 1
 
      __OM uint8_t   NMIPLLC: 1
 
      __OM uint8_t   NMINVMC: 1
 
      __OM uint8_t   NMIOTC: 1
 
      __OM uint8_t   NMIOWDC: 1
 
      __OM uint8_t   NMIMAPC: 1
 
      __OM uint8_t   NMIECCC: 1
 
      __OM uint8_t   NMISUPC: 1
 
   }   bit
 
NMICLR
 
__IM uint8_t RESERVED [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   EXINT0R: 1
 
      __IM uint8_t   EXINT0F: 1
 
      __IM uint8_t   EXINT1R: 1
 
      __IM uint8_t   EXINT1F: 1
 
      __IM uint8_t   EXINT2R: 1
 
      __IM uint8_t   EXINT2F: 1
 
      __IM uint8_t   MONR: 1
 
      __IM uint8_t   MONF: 1
 
   }   bit
 
IRCON0
 
__IM uint8_t RESERVED1 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   EIR: 1
 
      __IM uint8_t   TIR: 1
 
      __IM uint8_t   RIR: 1
 
   }   bit
 
IRCON1
 
__IM uint8_t RESERVED2 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   EIR: 1
 
      __IM uint8_t   TIR: 1
 
      __IM uint8_t   RIR: 1
 
   }   bit
 
IRCON2
 
__IM uint8_t RESERVED3 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   CCU6SR0: 1
 
      __IM   uint8_t: 3
 
      __IM uint8_t   CCU6SR1: 1
 
   }   bit
 
IRCON3
 
__IM uint8_t RESERVED4 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   CCU6SR2: 1
 
      __IM   uint8_t: 3
 
      __IM uint8_t   CCU6SR3: 1
 
   }   bit
 
IRCON4
 
__IM uint8_t RESERVED5 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   FNMIWDT: 1
 
      __IM uint8_t   FNMIPLL: 1
 
      __IM uint8_t   FNMINVM: 1
 
      __IM uint8_t   FNMIOT: 1
 
      __IM uint8_t   FNMIOWD: 1
 
      __IM uint8_t   FNMIMAP: 1
 
      __IM uint8_t   FNMIECC: 1
 
      __IM uint8_t   FNMISUP: 1
 
   }   bit
 
NMISR
 
__IM uint8_t RESERVED6 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 7
 
      __IOM uint8_t   EA: 1
 
   }   bit
 
IEN0
 
__IM uint8_t RESERVED7 [7]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   NMIWDT: 1
 
      __IOM uint8_t   NMIPLL: 1
 
      __IOM uint8_t   NMINVM: 1
 
      __IOM uint8_t   NMIOT: 1
 
      __IOM uint8_t   NMIOWD: 1
 
      __IOM uint8_t   NMIMAP: 1
 
      __IOM uint8_t   NMIECC: 1
 
      __IOM uint8_t   NMISUP: 1
 
   }   bit
 
NMICON
 
__IM uint8_t RESERVED8 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   EXINT0: 2
 
      __IOM uint8_t   EXINT1: 2
 
      __IOM uint8_t   EXINT2: 2
 
      __IOM uint8_t   MON_Trig_Sel: 2
 
   }   bit
 
EXICON0
 
__IM uint8_t RESERVED9 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   EXINT0RC: 1
 
      __OM uint8_t   EXINT0FC: 1
 
      __OM uint8_t   EXINT1RC: 1
 
      __OM uint8_t   EXINT1FC: 1
 
      __OM uint8_t   EXINT2RC: 1
 
      __OM uint8_t   EXINT2FC: 1
 
      __OM uint8_t   MONRC: 1
 
      __OM uint8_t   MONFC: 1
 
   }   bit
 
IRCON0CLR
 
__IM uint8_t RESERVED10 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   EIREN1: 1
 
      __IOM uint8_t   TIREN1: 1
 
      __IOM uint8_t   RIREN1: 1
 
      __IM   uint8_t: 3
 
      __IOM uint8_t   RIEN1: 1
 
      __IOM uint8_t   TIEN1: 1
 
   }   bit
 
MODIEN1
 
__IM uint8_t RESERVED11 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   EIREN2: 1
 
      __IOM uint8_t   TIREN2: 1
 
      __IOM uint8_t   RIREN2: 1
 
      __IM   uint8_t: 2
 
      __IOM uint8_t   EXINT2_EN: 1
 
      __IOM uint8_t   RIEN2: 1
 
      __IOM uint8_t   TIEN2: 1
 
   }   bit
 
MODIEN2
 
__IM uint8_t RESERVED12 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   IE0: 1
 
      __IM   uint8_t: 3
 
      __IOM uint8_t   MONIE: 1
 
      __IM uint8_t   MONSTS: 1
 
   }   bit
 
MODIEN3
 
__IM uint8_t RESERVED13 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   IE1: 1
 
   }   bit
 
MODIEN4
 
__IM uint8_t RESERVED14 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   XTAL_ON: 1
 
      __IOM uint8_t   SL: 1
 
      __IOM uint8_t   PD: 1
 
      __IOM uint8_t   SD: 1
 
   }   bit
 
PMCON0
 
__IM uint8_t RESERVED15 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   LOCK: 1
 
      __IOM uint8_t   RESLD: 1
 
      __IOM uint8_t   OSCDISC: 1
 
      __IOM uint8_t   VCOBYP: 1
 
      __IOM uint8_t   NDIV: 4
 
   }   bit
 
PLL_CON
 
__IM uint8_t RESERVED16 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   CLKREL: 4
 
      __IOM uint8_t   K2DIV: 2
 
      __IOM uint8_t   K1DIV: 1
 
      __IOM uint8_t   VCOSEL: 1
 
   }   bit
 
CMCON1
 
__IM uint8_t RESERVED17 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PBA0CLKREL: 1
 
   }   bit
 
CMCON2
 
__IM uint8_t RESERVED18 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   WDTIN: 1
 
      __IOM uint8_t   WDTRS: 1
 
      __IOM uint8_t   WDTEN: 1
 
      __IM   uint8_t: 1
 
      __IM uint8_t   WDTPR: 1
 
      __IOM uint8_t   WINBEN: 1
 
   }   bit
 
WDTCON
 
__IM uint8_t RESERVED19 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   PLL_LOCK: 1
 
      __IOM uint8_t   APCLK_SET: 1
 
      __IOM uint8_t   T3CLK_SEL: 1
 
      __IOM uint8_t   CLKWDT_IE: 1
 
      __IOM uint8_t   BGCLK_SEL: 1
 
      __IOM uint8_t   BGCLK_DIV: 1
 
      __IOM uint8_t   CPCLK_SEL: 1
 
      __IOM uint8_t   CPCLK_DIV: 1
 
   }   bit
 
APCLK_CTRL1
 
__IM uint8_t RESERVED20 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   APCLK1FAC: 2
 
      __IOM uint8_t   APCLK1SCLR: 1
 
      __IM   uint8_t: 1
 
      __IM uint8_t   APCLK1STS: 2
 
      __IM uint8_t   APCLK3STS: 1
 
      __IOM uint8_t   APCLK3SCLR: 1
 
   }   bit
 
APCLK1
 
__IM uint8_t RESERVED21 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   APCLK2FAC: 5
 
      __IM uint8_t   APCLK2STS: 2
 
      __IOM uint8_t   APCLK2SCLR: 1
 
   }   bit
 
APCLK2
 
__IM uint8_t RESERVED22 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   ADC1_DIS: 1
 
      __IOM uint8_t   SSC1_DIS: 1
 
      __IOM uint8_t   CCU6_DIS: 1
 
      __IOM uint8_t   T2_DIS: 1
 
      __IOM uint8_t   GPT12_DIS: 1
 
   }   bit
 
PMCON1
 
__IM uint8_t RESERVED23 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 1
 
      __IOM uint8_t   SSC2_DIS: 1
 
      __IOM uint8_t   T21_DIS: 1
 
      __IOM uint8_t   T3_DIS: 1
 
   }   bit
 
PMCON2
 
__IM uint8_t RESERVED24 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   LOCKUP: 1
 
      __IM   uint8_t: 6
 
      __IOM uint8_t   LOCKUP_EN: 1
 
   }   bit
 
RSTCON
 
__IM uint8_t RESERVED25 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   SDADCCLK_DIV: 2
 
      __IOM uint8_t   T3CLK_DIV: 2
 
   }   bit
 
APCLK_CTRL2
 
__IM uint8_t RESERVED26 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 4
 
      __IOM uint8_t   NVMCLKFAC: 2
 
      __IOM uint8_t   SYSCLKSEL: 2
 
   }   bit
 
SYSCON0
 
__IM uint8_t RESERVED27 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   INIT_FAIL: 1
 
      __IOM uint8_t   MRAMINITSTS: 1
 
      __IOM uint8_t   PG100TP_CHKS_ERR: 1
 
   }   bit
 
SYS_STRTUP_STS
 
__IM uint8_t RESERVED28 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   WDTREL: 8
 
   }   bit
 
WDTREL
 
__IM uint8_t RESERVED29 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   WDTWINB: 8
 
   }   bit
 
WDTWINB
 
__IM uint8_t RESERVED30 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   WDT: 8
 
   }   bit
 
WDTL
 
__IM uint8_t RESERVED31 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   WDT: 8
 
   }   bit
 
WDTH
 
__IM uint8_t RESERVED32 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   R: 1
 
      __IOM uint8_t   BRPRE: 3
 
   }   bit
 
BCON1
 
__IM uint8_t RESERVED33 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   FD_SEL: 5
 
      __IOM uint8_t   BR_VALUE: 3
 
   }   bit
 
BGL1
 
__IM uint8_t RESERVED34 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   BR_VALUE: 8
 
   }   bit
 
BGH1
 
__IM uint8_t RESERVED35 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   BRDIS: 1
 
      __IOM uint8_t   BGSEL: 2
 
      __IM uint8_t   BRK: 1
 
      __IM uint8_t   EOFSYN: 1
 
      __IM uint8_t   ERRSYN: 1
 
      __IOM uint8_t   SYNEN: 1
 
   }   bit
 
LINST
 
__IM uint8_t RESERVED36 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   R: 1
 
      __IOM uint8_t   BRPRE: 3
 
   }   bit
 
BCON2
 
__IM uint8_t RESERVED37 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   FD_SEL: 5
 
      __IOM uint8_t   BR_VALUE: 3
 
   }   bit
 
BGL2
 
__IM uint8_t RESERVED38 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   BR_VALUE: 8
 
   }   bit
 
BGH2
 
__IM uint8_t RESERVED39 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 3
 
      __OM uint8_t   BRKC: 1
 
      __OM uint8_t   EOFSYNC: 1
 
      __OM uint8_t   ERRSYNC: 1
 
   }   bit
 
LINSCLR
 
__IM uint8_t RESERVED40 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   VERID: 3
 
      __IM uint8_t   PRODID: 5
 
   }   bit
 
ID
 
__IM uint8_t RESERVED41 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   MODE: 2
 
      __IM uint8_t   PROTECT_S: 1
 
      __IOM uint8_t   PASS: 5
 
   }   bit
 
PASSWD
 
__IM uint8_t RESERVED42 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   OSCSS: 2
 
      __IOM uint8_t   OSCWDTRST: 1
 
      __IM uint8_t   OSC2L: 1
 
      __IOM uint8_t   XPD: 1
 
      __IM   uint8_t: 2
 
      __IOM uint8_t   OSCTRIM_8: 1
 
   }   bit
 
OSC_CON
 
__IM uint8_t RESERVED43 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   COREL: 4
 
      __IOM uint8_t   COUTS0: 1
 
      __IOM uint8_t   TLEN: 1
 
      __IOM uint8_t   COUTS1: 1
 
      __IOM uint8_t   EN: 1
 
   }   bit
 
COCON
 
__IM uint8_t RESERVED44 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   EXINT0IS: 2
 
      __IOM uint8_t   EXINT1IS: 2
 
      __IOM uint8_t   EXINT2IS: 2
 
      __IOM uint8_t   URIOS1: 1
 
      __IOM uint8_t   U_TX_CONDIS: 1
 
   }   bit
 
MODPISEL
 
__IM uint8_t RESERVED45 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPT12CAPINB: 1
 
      __IM   uint8_t: 5
 
      __IOM uint8_t   T2EXCON: 1
 
      __IOM uint8_t   T21EXCON: 1
 
   }   bit
 
MODPISEL1
 
__IM uint8_t RESERVED46 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   T2IS: 2
 
      __IOM uint8_t   T21IS: 2
 
      __IOM uint8_t   T2EXIS: 2
 
      __IOM uint8_t   T21EXIS: 2
 
   }   bit
 
MODPISEL2
 
__IM uint8_t RESERVED47 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 6
 
      __IOM uint8_t   URIOS2: 1
 
   }   bit
 
MODPISEL3
 
__IM uint8_t RESERVED48 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   WDTSUSP: 1
 
      __IOM uint8_t   T12SUSP: 1
 
      __IOM uint8_t   T13SUSP: 1
 
      __IOM uint8_t   T2_SUSP: 1
 
      __IOM uint8_t   GPT12_SUSP: 1
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   T21_SUSP: 1
 
   }   bit
 
MODSUSP1
 
__IM uint8_t RESERVED49 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   T3_SUSP: 1
 
      __IOM uint8_t   MU_SUSP: 1
 
      __IOM uint8_t   ADC1_SUSP: 1
 
   }   bit
 
MODSUSP2
 
__IM uint8_t RESERVED50 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPT12: 4
 
      __IOM uint8_t   TRIG_CONF: 1
 
      __IOM uint8_t   T3_GPT12_SEL: 1
 
   }   bit
 
GPT12PISEL
 
__IM uint8_t RESERVED51 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   RIE: 1
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   NVMIE: 1
 
   }   bit
 
EDCCON
 
__IM uint8_t RESERVED52 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   RDBE: 1
 
      __IM   uint8_t: 1
 
      __IM uint8_t   NVMDBE: 1
 
      __IM uint8_t   RSBE: 1
 
   }   bit
 
EDCSTAT
 
__IM uint8_t RESERVED53 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   SECTORINFO: 6
 
      __IOM uint8_t   SASTATUS: 2
 
   }   bit
 
MEMSTAT
 
__IM uint8_t RESERVED54 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   NVMPROTSTSL_0: 1
 
      __IOM uint8_t   NVMPROTSTSL_1: 1
 
      __IOM uint8_t   NVMPROTSTSL_2: 1
 
      __IOM uint8_t   NVMPROTSTSL_3: 1
 
   }   bit
 
NVM_PROT_STS
 
__IM uint8_t RESERVED55 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   NVM_PROT_ERR: 1
 
      __IM uint8_t   NVM_ADDR_ERR: 1
 
      __IM uint8_t   NVM_SFR_PROT_ERR: 1
 
      __IM uint8_t   NVM_SFR_ADDR_ERR: 1
 
      __IM uint8_t   ROM_PROT_ERR: 1
 
      __IM uint8_t   ROM_ADDR_ERR: 1
 
      __IM uint8_t   RAM_PROT_ERR: 1
 
   }   bit
 
MEM_ACC_STS
 
__IM uint8_t RESERVED56 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PDM0: 3
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   PDM1: 3
 
   }   bit
 
P0_POCON0
 
__IM uint8_t RESERVED57 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PDM2: 3
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   PDM3: 3
 
   }   bit
 
P0_POCON1
 
__IM uint8_t RESERVED58 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PDM4: 3
 
   }   bit
 
P0_POCON2
 
__IM uint8_t RESERVED59 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   TCC: 2
 
   }   bit
 
TCCR
 
__IM uint8_t RESERVED60 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PDM0: 3
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   PDM1: 3
 
   }   bit
 
P1_POCON0
 
__IM uint8_t RESERVED61 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PDM2: 3
 
      __IM   uint8_t: 1
 
      __IOM uint8_t   PDM3: 3
 
   }   bit
 
P1_POCON1
 
__IM uint8_t RESERVED62 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   PDM4: 3
 
   }   bit
 
P1_POCON2
 
__IM uint8_t RESERVED63 [11]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   RDBEC: 1
 
      __IM   uint8_t: 1
 
      __OM uint8_t   NVMDBEC: 1
 
      __OM uint8_t   RSBEC: 1
 
   }   bit
 
EDCSCLR
 
__IM uint8_t RESERVED64 [55]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   CH1IE: 1
 
      __IOM uint8_t   CH2IE: 1
 
      __IOM uint8_t   CH3IE: 1
 
      __IOM uint8_t   CH4IE: 1
 
      __IOM uint8_t   CH5IE: 1
 
      __IOM uint8_t   CH6IE: 1
 
      __IOM uint8_t   CH7IE: 1
 
      __IOM uint8_t   CH8IE: 1
 
   }   bit
 
DMAIEN1
 
__IM uint8_t RESERVED65 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   TRERRIE: 1
 
      __IOM uint8_t   TRSEQ1RDYIE: 1
 
      __IOM uint8_t   TRSEQ2RDYIE: 1
 
      __IOM uint8_t   SSCTXIE: 1
 
      __IOM uint8_t   SSCRXIE: 1
 
      __IOM uint8_t   GPT12IE: 1
 
      __IOM uint8_t   SDADCIE: 1
 
   }   bit
 
DMAIEN2
 
__IM uint8_t RESERVED66 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   SSCTXSRCSEL: 1
 
      __IOM uint8_t   SSCRXSRCSEL: 1
 
      __IOM uint8_t   T12ZM_DMAEN: 1
 
      __IOM uint8_t   T12PM_DMAEN: 1
 
      __IM   uint8_t: 1
 
      __IM uint8_t   SSCTX: 1
 
      __IM uint8_t   SSCRX: 1
 
      __IM uint8_t   GPT12_T3: 1
 
   }   bit
 
DMASRCSEL
 
__IM uint8_t RESERVED67 [7]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   CH1: 1
 
      __IM uint8_t   CH2: 1
 
      __IM uint8_t   CH3: 1
 
      __IM uint8_t   CH4: 1
 
      __IM uint8_t   CH5: 1
 
      __IM uint8_t   CH6: 1
 
      __IM uint8_t   CH7: 1
 
      __IM uint8_t   CH8: 1
 
   }   bit
 
DMAIRC1
 
__IM uint8_t RESERVED68 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   STRDY: 1
 
      __IM uint8_t   TRSEQ1DY: 1
 
      __IM uint8_t   TRSEQ2DY: 1
 
      __IM uint8_t   SSC1RDY: 1
 
      __IM uint8_t   SSC2RDY: 1
 
      __IM uint8_t   GPT12: 1
 
      __IM uint8_t   SDADC: 1
 
   }   bit
 
DMAIRC2
 
__IM uint8_t RESERVED69 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   T2IE: 1
 
      __IOM uint8_t   T3IE: 1
 
      __IOM uint8_t   T4IE: 1
 
      __IOM uint8_t   T5IE: 1
 
      __IOM uint8_t   T6IE: 1
 
      __IOM uint8_t   CRIE: 1
 
   }   bit
 
GPT12IEN
 
__IM uint8_t RESERVED70 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM uint8_t   T2: 1
 
      __IM uint8_t   T3: 1
 
      __IM uint8_t   T4: 1
 
      __IM uint8_t   T5: 1
 
      __IM uint8_t   T6: 1
 
      __IM uint8_t   CR: 1
 
   }   bit
 
GPT12IRC
 
__IM uint8_t RESERVED71 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   T2C: 1
 
      __OM uint8_t   T3C: 1
 
      __OM uint8_t   T4C: 1
 
      __OM uint8_t   T5C: 1
 
      __OM uint8_t   T6C: 1
 
      __OM uint8_t   CRC: 1
 
   }   bit
 
GPT12ICLR
 
__IM uint8_t RESERVED72 [19]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   EIRC: 1
 
      __OM uint8_t   TIRC: 1
 
      __OM uint8_t   RIRC: 1
 
   }   bit
 
IRCON1CLR
 
__IM uint8_t RESERVED73 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   EIRC: 1
 
      __OM uint8_t   TIRC: 1
 
      __OM uint8_t   RIRC: 1
 
   }   bit
 
IRCON2CLR
 
__IM uint8_t RESERVED74 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IOM uint8_t   GPT12_DMAEN: 2
 
   }   bit
 
DMASRCSEL2
 
__IM uint8_t RESERVED75 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   CH1C: 1
 
      __OM uint8_t   CH2C: 1
 
      __OM uint8_t   CH3C: 1
 
      __OM uint8_t   CH4C: 1
 
      __OM uint8_t   CH5C: 1
 
      __OM uint8_t   CH6C: 1
 
      __OM uint8_t   CH7C: 1
 
      __OM uint8_t   CH8C: 1
 
   }   bit
 
DMAIRC1CLR
 
__IM uint8_t RESERVED76 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 1
 
      __OM uint8_t   TRSEQ1DYC: 1
 
      __OM uint8_t   TRSEQ2DYC: 1
 
      __OM uint8_t   SSC1C: 1
 
      __OM uint8_t   SSC2C: 1
 
      __OM uint8_t   GPT12C: 1
 
      __OM uint8_t   SDADCC: 1
 
   }   bit
 
DMAIRC2CLR
 
__IM uint8_t RESERVED77 [7]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   CCU6SR0C: 1
 
      __IM   uint8_t: 3
 
      __OM uint8_t   CCU6SR1C: 1
 
   }   bit
 
IRCON3CLR
 
__IM uint8_t RESERVED78 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __OM uint8_t   CCU6SR2C: 1
 
      __IM   uint8_t: 3
 
      __OM uint8_t   CCU6SR3C: 1
 
   }   bit
 
IRCON4CLR
 
__IM uint8_t RESERVED79 [3]
 
union {
   __IOM uint8_t   reg
 
   struct {
      __IM   uint8_t: 5
 
      __OM uint8_t   SSCTXC: 1
 
      __OM uint8_t   SSCRXC: 1
 
      __OM uint8_t   GPT12_T3C: 1
 
   }   bit
 
DMASRCCLR
 

Field Documentation

◆ ADC1_DIS

__IOM uint8_t ADC1_DIS

[0..0] ADC1 Disable Request. Active high.

◆ ADC1_SUSP

__IOM uint8_t ADC1_SUSP

[2..2] ADC1 Unit Debug Suspend Bit

◆ APCLK1

union { ... } APCLK1

◆ APCLK1FAC

__IOM uint8_t APCLK1FAC

[1..0] Analog Module Clock Factor

◆ APCLK1SCLR

__IOM uint8_t APCLK1SCLR

[2..2] Analog Peripherals Clock Status Clear

◆ APCLK1STS

__IM uint8_t APCLK1STS

[5..4] Analog Peripherals Clock Status

◆ APCLK2

union { ... } APCLK2

◆ APCLK2FAC

__IOM uint8_t APCLK2FAC

[4..0] Slow Down Clock Divider for TFILT_CLK Generation

◆ APCLK2SCLR

__IOM uint8_t APCLK2SCLR

[7..7] Analog Peripherals Clock Status Clear

◆ APCLK2STS

__IM uint8_t APCLK2STS

[6..5] Analog Peripherals Clock Status

◆ APCLK3SCLR

__IOM uint8_t APCLK3SCLR

[7..7] Analog Peripherals Clock Status Clear

◆ APCLK3STS

__IM uint8_t APCLK3STS

[6..6] Loss of Clock Status

◆ APCLK_CTRL1

union { ... } APCLK_CTRL1

◆ APCLK_CTRL2

union { ... } APCLK_CTRL2

◆ APCLK_SET

__IOM uint8_t APCLK_SET

[1..1] Set and Overtake Flag for Clock Settings

◆ BCON1

union { ... } BCON1

◆ BCON2

union { ... } BCON2

◆ BGCLK_DIV

__IOM uint8_t BGCLK_DIV

[5..5] Bandgap Clock Divider

◆ BGCLK_SEL

__IOM uint8_t BGCLK_SEL

[4..4] Bandgap Clock Selection

◆ BGH1

union { ... } BGH1

◆ BGH2

union { ... } BGH2

◆ BGL1

union { ... } BGL1

◆ BGL2

union { ... } BGL2

◆ BGSEL

__IOM uint8_t BGSEL

[2..1] Baud Rate Select for Detection

◆ bit [1/81]

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◆ BR_VALUE

__IOM uint8_t BR_VALUE

[7..5] Baud Rate Timer/Reload Value

[7..0] Baud Rate Timer/Reload Value

◆ BRDIS

__IOM uint8_t BRDIS

[0..0] Baud Rate Detection Disable

◆ BRK

[3..3] Break Field Flag

◆ BRKC

__OM uint8_t BRKC

[3..3] Break Field Flag Clear

◆ BRPRE

__IOM uint8_t BRPRE

[3..1] Prescaler Bit

◆ CCU6_DIS

__IOM uint8_t CCU6_DIS

[2..2] CCU6 Disable Request. Active high.

◆ CCU6SR0

__IM uint8_t CCU6SR0

[0..0] Interrupt Flag 0 for CCU6

◆ CCU6SR0C

__OM uint8_t CCU6SR0C

[0..0] Interrupt Flag 0 for CCU6 Clear

◆ CCU6SR1

__IM uint8_t CCU6SR1

[4..4] Interrupt Flag 1 for CCU6

◆ CCU6SR1C

__OM uint8_t CCU6SR1C

[4..4] Interrupt Flag 1 for CCU6 Clear

◆ CCU6SR2

__IM uint8_t CCU6SR2

[0..0] Interrupt Flag 2 for CCU6

◆ CCU6SR2C

__OM uint8_t CCU6SR2C

[0..0] Interrupt Flag 2 for CCU6 Clear

◆ CCU6SR3

__IM uint8_t CCU6SR3

[4..4] Interrupt Flag 3 for CCU6

◆ CCU6SR3C

__OM uint8_t CCU6SR3C

[4..4] Interrupt Flag 3 for CCU6 Clear

◆ CH1

[0..0] DMA Channel 4 Interrupt Status (ADC1 Channel 0)

◆ CH1C

__OM uint8_t CH1C

[0..0] DMA Channel 4 Interrupt Status Clear (ADC1 Channel 0)

◆ CH1IE

__IOM uint8_t CH1IE

[0..0] DMA Channel 4 Interrupt Enable (ADC1 Channel 0)

◆ CH2

[1..1] DMA Channel 5 Interrupt Status (ADC1 Channel 1)

◆ CH2C

__OM uint8_t CH2C

[1..1] DMA Channel 5 Interrupt Status Clear (ADC1 Channel 1)

◆ CH2IE

__IOM uint8_t CH2IE

[1..1] DMA Channel 5 Interrupt Enable (ADC1 Channel 1)

◆ CH3

[2..2] DMA Channel 6 Interrupt Status (ADC1 Channel 2)

◆ CH3C

__OM uint8_t CH3C

[2..2] DMA Channel 6 Interrupt Status Clear (ADC1 Channel 2)

◆ CH3IE

__IOM uint8_t CH3IE

[2..2] DMA Channel 6 Interrupt Enable (ADC1 Channel 2)

◆ CH4

[3..3] DMA Channel 7 Interrupt Status (ADC1 Channel 3)

◆ CH4C

__OM uint8_t CH4C

[3..3] DMA Channel 7 Interrupt Status Clear (ADC1 Channel 3)

◆ CH4IE

__IOM uint8_t CH4IE

[3..3] DMA Channel 7 Interrupt Enable (ADC1 Channel 3)

◆ CH5

[4..4] DMA Channel 8 Interrupt Status (ADC1 Channel 4)

◆ CH5C

__OM uint8_t CH5C

[4..4] DMA Channel 8 Interrupt Status Clear (ADC1 Channel 4)

◆ CH5IE

__IOM uint8_t CH5IE

[4..4] DMA Channel 8 Interrupt Enable (ADC1 Channel 4)

◆ CH6

[5..5] DMA Channel 9 Interrupt Status (ADC1 Channel 5)

◆ CH6C

__OM uint8_t CH6C

[5..5] DMA Channel 9 Interrupt Status Clear (ADC1 Channel 5)

◆ CH6IE

__IOM uint8_t CH6IE

[5..5] DMA Channel 9 Interrupt Enable (ADC1 Channel 5)

◆ CH7

[6..6] DMA Channel 10 Interrupt Status (ADC1 Channel 6)

◆ CH7C

__OM uint8_t CH7C

[6..6] DMA Channel 10 Interrupt Status Clear (ADC1 Channel 6)

◆ CH7IE

__IOM uint8_t CH7IE

[6..6] DMA Channel 10 Interrupt Enable (ADC1 Channel 6)

◆ CH8

[7..7] DMA Channel 11 Interrupt Status (ADC1 Channel 7)

◆ CH8C

__OM uint8_t CH8C

[7..7] DMA Channel 11 Interrupt Status Clear (ADC1 Channel 7)

◆ CH8IE

__IOM uint8_t CH8IE

[7..7] DMA Channel 11 Interrupt Enable (ADC1 Channel 7)

◆ CLKREL

__IOM uint8_t CLKREL

[3..0] Slow Down Clock Divider for fCCLK Generation

◆ CLKWDT_IE

__IOM uint8_t CLKWDT_IE

[3..3] Clock Watchdog Interrupt Enable

◆ CMCON1

union { ... } CMCON1

◆ CMCON2

union { ... } CMCON2

◆ COCON

union { ... } COCON

◆ COREL

__IOM uint8_t COREL

[3..0] Clock Output Divider

◆ COUTS0

__IOM uint8_t COUTS0

[4..4] Clock Out Source Select Bit 0

◆ COUTS1

__IOM uint8_t COUTS1

[6..6] Clock Out Source Select Bit 1

◆ CPCLK_DIV

__IOM uint8_t CPCLK_DIV

[7..7] Charge Pump Clock Divider

◆ CPCLK_SEL

__IOM uint8_t CPCLK_SEL

[6..6] Charge Pump Clock Selection

◆ CR

[5..5] GPT Module 2 Capture Reload Interrupt Status

◆ CRC

[5..5] GPT Module 2 Capture Reload Interrupt Status Clear

◆ CRIE

__IOM uint8_t CRIE

[5..5] General Purpose Timer 12 Capture and Reload Interrupt Enable

◆ DMAIEN1

union { ... } DMAIEN1

◆ DMAIEN2

union { ... } DMAIEN2

◆ DMAIRC1

union { ... } DMAIRC1

◆ DMAIRC1CLR

union { ... } DMAIRC1CLR

◆ DMAIRC2

union { ... } DMAIRC2

◆ DMAIRC2CLR

union { ... } DMAIRC2CLR

◆ DMASRCCLR

union { ... } DMASRCCLR

◆ DMASRCSEL

union { ... } DMASRCSEL

◆ DMASRCSEL2

union { ... } DMASRCSEL2

◆ EA

[7..7] Global Interrupt Mask

◆ EDCCON

union { ... } EDCCON

◆ EDCSCLR

union { ... } EDCSCLR

◆ EDCSTAT

union { ... } EDCSTAT

◆ EIR

[0..0] Error Interrupt Flag for SSC1

[0..0] Error Interrupt Flag for SSC2

◆ EIRC

__OM uint8_t EIRC

[0..0] Error Interrupt Flag for SSC1 Clear

[0..0] Error Interrupt Flag for SSC2 Clear

◆ EIREN1

__IOM uint8_t EIREN1

[0..0] SSC 1 Error Interrupt Enable

◆ EIREN2

__IOM uint8_t EIREN2

[0..0] SSC 2 Error Interrupt Enable

◆ EN

[7..7] CLKOUT Enable

◆ EOFSYN

__IM uint8_t EOFSYN

[4..4] End of SYN Byte Interrupt Flag

◆ EOFSYNC

__OM uint8_t EOFSYNC

[4..4] End of SYN Byte Interrupt Flag Clear

◆ ERRSYN

__IM uint8_t ERRSYN

[5..5] SYN Byte Error Interrupt Flag

◆ ERRSYNC

__OM uint8_t ERRSYNC

[5..5] SYN Byte Error Interrupt Flag

◆ EXICON0

union { ... } EXICON0

◆ EXINT0

__IOM uint8_t EXINT0

[1..0] External Interrupt 0 Trigger Select

◆ EXINT0F

__IM uint8_t EXINT0F

[1..1] Interrupt Flag for External Interrupt 0x on falling edge

◆ EXINT0FC

__OM uint8_t EXINT0FC

[1..1] Interrupt Flag for External Interrupt 0x on falling edge clear

◆ EXINT0IS

__IOM uint8_t EXINT0IS

[1..0] External Interrupt 0 Input Select

◆ EXINT0R

__IM uint8_t EXINT0R

[0..0] Interrupt Flag for External Interrupt 0x on rising edge

◆ EXINT0RC

__OM uint8_t EXINT0RC

[0..0] Interrupt Flag for External Interrupt 0x on rising edge clear

◆ EXINT1

__IOM uint8_t EXINT1

[3..2] External Interrupt 1 Trigger Select

◆ EXINT1F

__IM uint8_t EXINT1F

[3..3] Interrupt Flag for External Interrupt 1x on falling edge

◆ EXINT1FC

__OM uint8_t EXINT1FC

[3..3] Interrupt Flag for External Interrupt 1x on falling edge clear

◆ EXINT1IS

__IOM uint8_t EXINT1IS

[3..2] External Interrupt 1 Input Select

◆ EXINT1R

__IM uint8_t EXINT1R

[2..2] Interrupt Flag for External Interrupt 1x on rising edge

◆ EXINT1RC

__OM uint8_t EXINT1RC

[2..2] Interrupt Flag for External Interrupt 1x on rising edge clear

◆ EXINT2

__IOM uint8_t EXINT2

[5..4] External Interrupt 2 Trigger Select

◆ EXINT2_EN

__IOM uint8_t EXINT2_EN

[5..5] External Interrupt 2 Enable

◆ EXINT2F

__IM uint8_t EXINT2F

[5..5] Interrupt Flag for External Interrupt 2x on falling edge

◆ EXINT2FC

__OM uint8_t EXINT2FC

[5..5] Interrupt Flag for External Interrupt 2x on falling edge clear

◆ EXINT2IS

__IOM uint8_t EXINT2IS

[5..4] External Interrupt 2 Input Select

◆ EXINT2R

__IM uint8_t EXINT2R

[4..4] Interrupt Flag for External Interrupt 2x on rising edge

◆ EXINT2RC

__OM uint8_t EXINT2RC

[4..4] Interrupt Flag for External Interrupt 2x on rising edge clear

◆ FD_SEL

__IOM uint8_t FD_SEL

[4..0] Fractional Divider Selection

◆ FNMIECC

__IM uint8_t FNMIECC

[6..6] ECC Error NMI Flag

◆ FNMIMAP

__IM uint8_t FNMIMAP

[5..5] NVM Map Error NMI Flag

◆ FNMINVM

__IM uint8_t FNMINVM

[2..2] NVM Operation Complete NMI Flag

◆ FNMIOT

__IM uint8_t FNMIOT

[3..3] Over-temperature NMI Flag

◆ FNMIOWD

__IM uint8_t FNMIOWD

[4..4] Oscillator Watchdog or MI_CLK Watchdog NMI Flag

◆ FNMIPLL

__IM uint8_t FNMIPLL

[1..1] PLL NMI Flag

◆ FNMISUP

__IM uint8_t FNMISUP

[7..7] Supply Prewarning NMI Flag

◆ FNMIWDT

__IM uint8_t FNMIWDT

[0..0] Watchdog Timer NMI Flag

◆ GPT12 [1/2]

__IOM uint8_t GPT12

[3..0] GPT12 TIN3B / TIN4D Input Select

◆ GPT12 [2/2]

__IM uint8_t GPT12

[5..5] DMA Channel 12 Interrupt Status (GPT12/Timer3)

◆ GPT12_DIS

__IOM uint8_t GPT12_DIS

[4..4] General Purpose Timer 12 Disable Request. Active high.

◆ GPT12_DMAEN

__IOM uint8_t GPT12_DMAEN

[1..0] GPT12 T3 DMA muxer, DMA channel 12

◆ GPT12_SUSP

__IOM uint8_t GPT12_SUSP

[4..4] GPT12 Debug Suspend Bit

◆ GPT12_T3

__IM uint8_t GPT12_T3

[7..7] DMA Channel 12 Request (GPT12E, Timer3)

◆ GPT12_T3C

__OM uint8_t GPT12_T3C

[7..7] GPT12 Transmit Request Clear

◆ GPT12C

__OM uint8_t GPT12C

[5..5] DMA Channel 12 Interrupt Status Clear (GPT12/Timer3)

◆ GPT12CAPINB

__IOM uint8_t GPT12CAPINB

[0..0] GPT12 CAPINB Input Control

◆ GPT12ICLR

union { ... } GPT12ICLR

◆ GPT12IE

__IOM uint8_t GPT12IE

[5..5] DMA Channel 12 Interrupt Enable (GPT12/Timer3)

◆ GPT12IEN

union { ... } GPT12IEN

◆ GPT12IRC

union { ... } GPT12IRC

◆ GPT12PISEL

union { ... } GPT12PISEL

◆ ID

union { ... } ID

◆ IE0

[0..0] External Interrupt Enable

◆ IE1

[0..0] External Interrupt Enable

◆ IEN0

union { ... } IEN0

◆ INIT_FAIL

__IOM uint8_t INIT_FAIL

[0..0] Initialization at startup failed

◆ IRCON0

union { ... } IRCON0

◆ IRCON0CLR

union { ... } IRCON0CLR

◆ IRCON1

union { ... } IRCON1

◆ IRCON1CLR

union { ... } IRCON1CLR

◆ IRCON2

union { ... } IRCON2

◆ IRCON2CLR

union { ... } IRCON2CLR

◆ IRCON3

union { ... } IRCON3

◆ IRCON3CLR

union { ... } IRCON3CLR

◆ IRCON4

union { ... } IRCON4

◆ IRCON4CLR

union { ... } IRCON4CLR

◆ K1DIV

__IOM uint8_t K1DIV

[6..6] PLL K1-Divider

◆ K2DIV

__IOM uint8_t K2DIV

[5..4] PLL K2-Divider

◆ LINSCLR

union { ... } LINSCLR

◆ LINST

union { ... } LINST

◆ LOCK

__IM uint8_t LOCK

[0..0] PLL Lock Status Flag

◆ LOCKUP

__IOM uint8_t LOCKUP

[0..0] Lockup Flag

◆ LOCKUP_EN

__IOM uint8_t LOCKUP_EN

[7..7] Lockup Reset Enable Flag

◆ MEM_ACC_STS

union { ... } MEM_ACC_STS

◆ MEMSTAT

union { ... } MEMSTAT

◆ MODE

__IOM uint8_t MODE

[1..0] Bit-Protection Scheme Control Bit

◆ MODIEN1

union { ... } MODIEN1

◆ MODIEN2

union { ... } MODIEN2

◆ MODIEN3

union { ... } MODIEN3

◆ MODIEN4

union { ... } MODIEN4

◆ MODPISEL

union { ... } MODPISEL

◆ MODPISEL1

union { ... } MODPISEL1

◆ MODPISEL2

union { ... } MODPISEL2

◆ MODPISEL3

union { ... } MODPISEL3

◆ MODSUSP1

union { ... } MODSUSP1

◆ MODSUSP2

union { ... } MODSUSP2

◆ MON_Trig_Sel

__IOM uint8_t MON_Trig_Sel

[7..6] MON Input Trigger Select

◆ MONF

__IM uint8_t MONF

[7..7] Interrupt Flag for External Interrupt MON on falling edge

◆ MONFC

__OM uint8_t MONFC

[7..7] Interrupt Flag for External Interrupt MON on falling edge clear

◆ MONIE

__IOM uint8_t MONIE

[4..4] MON Interrupt Enable

◆ MONR

__IM uint8_t MONR

[6..6] Interrupt Flag for External Interrupt MON on rising edge

◆ MONRC

__OM uint8_t MONRC

[6..6] Interrupt Flag for External Interrupt MON on rising edge clear

◆ MONSTS

__IM uint8_t MONSTS

[5..5] MON Input Status

◆ MRAMINITSTS

__IOM uint8_t MRAMINITSTS

[1..1] Map RAM Initialization Status

◆ MU_SUSP

__IOM uint8_t MU_SUSP

[1..1] Measurement Unit Debug Suspend Bit

◆ NDIV

__IOM uint8_t NDIV

[7..4] PLL N-Divider

◆ NMICLR

union { ... } NMICLR

◆ NMICON

union { ... } NMICON

◆ NMIECC

__IOM uint8_t NMIECC

[6..6] ECC Error NMI Enable

◆ NMIECCC

__OM uint8_t NMIECCC

[6..6] ECC Error NMI Clear

◆ NMIMAP

__IOM uint8_t NMIMAP

[5..5] NVM Map Error NMI Enable

◆ NMIMAPC

__OM uint8_t NMIMAPC

[5..5] NVM Map Error NMI Clear

◆ NMINVM

__IOM uint8_t NMINVM

[2..2] NVM Operation Complete NMI Enable

◆ NMINVMC

__OM uint8_t NMINVMC

[2..2] NVM Operation Complete NMI Clear

◆ NMIOT

__IOM uint8_t NMIOT

[3..3] NMI OT Enable

◆ NMIOTC

__OM uint8_t NMIOTC

[3..3] NMI OT Clear

◆ NMIOWD

__IOM uint8_t NMIOWD

[4..4] Oscillator Watchdog NMI Enable

◆ NMIOWDC

__OM uint8_t NMIOWDC

[4..4] Oscillator Watchdog NMI Clear

◆ NMIPLL

__IOM uint8_t NMIPLL

[1..1] PLL Loss of Lock NMI Enable

◆ NMIPLLC

__OM uint8_t NMIPLLC

[1..1] PLL Loss of Lock NMI Clear

◆ NMISR

union { ... } NMISR

◆ NMISUP

__IOM uint8_t NMISUP

[7..7] Supply Prewarning NMI Enable

◆ NMISUPC

__OM uint8_t NMISUPC

[7..7] Supply Prewarning NMI Clear

◆ NMIWDT

__IOM uint8_t NMIWDT

[0..0] Watchdog Timer NMI Enable

◆ NMIWDTC

__OM uint8_t NMIWDTC

[0..0] Watchdog Timer NMI Clear

◆ NVM_ADDR_ERR

__IM uint8_t NVM_ADDR_ERR

[1..1] NVM Address Protection

◆ NVM_PROT_ERR

__IM uint8_t NVM_PROT_ERR

[0..0] NVM Access Protection

◆ NVM_PROT_STS

union { ... } NVM_PROT_STS

◆ NVM_SFR_ADDR_ERR

__IM uint8_t NVM_SFR_ADDR_ERR

[3..3] NVM SFR Address Protection

◆ NVM_SFR_PROT_ERR

__IM uint8_t NVM_SFR_PROT_ERR

[2..2] NVM SFR Access Protection

◆ NVMCLKFAC

__IOM uint8_t NVMCLKFAC

[5..4] NVM Access Clock Factor

◆ NVMDBE

__IM uint8_t NVMDBE

[2..2] NVM Double Bit Error

◆ NVMDBEC

__OM uint8_t NVMDBEC

[2..2] NVM Double Bit Error Clear

◆ NVMIE

__IOM uint8_t NVMIE

[2..2] NVM Double Bit ECC Error Interrupt Enable

◆ NVMPROTSTSL_0

__IOM uint8_t NVMPROTSTSL_0

[0..0] NVM Protection Status Register Low Flags

◆ NVMPROTSTSL_1

__IOM uint8_t NVMPROTSTSL_1

[1..1] NVM Protection Status Register Low Flags

◆ NVMPROTSTSL_2

__IOM uint8_t NVMPROTSTSL_2

[2..2] NVM Protection Status Register Low Flags

◆ NVMPROTSTSL_3

__IOM uint8_t NVMPROTSTSL_3

[3..3] NVM Protection Status Register Low Flags

◆ OSC2L

__IM uint8_t OSC2L

[3..3] OSC-Too-Low Condition Flag

◆ OSC_CON

union { ... } OSC_CON

◆ OSCDISC

__IOM uint8_t OSCDISC

[2..2] Oscillator Disconnect

◆ OSCSS

__IOM uint8_t OSCSS

[1..0] Oscillator Source Select

◆ OSCTRIM_8

__IOM uint8_t OSCTRIM_8

[7..7] OSC_PLL Trim Configuration Bit [8]

◆ OSCWDTRST

__IOM uint8_t OSCWDTRST

[2..2] Oscillator Watchdog Reset

◆ P0_POCON0

union { ... } P0_POCON0

◆ P0_POCON1

union { ... } P0_POCON1

◆ P0_POCON2

union { ... } P0_POCON2

◆ P1_POCON0

union { ... } P1_POCON0

◆ P1_POCON1

union { ... } P1_POCON1

◆ P1_POCON2

union { ... } P1_POCON2

◆ PASS

__IOM uint8_t PASS

[7..3] Password Bits

◆ PASSWD

union { ... } PASSWD

◆ PBA0CLKREL

__IOM uint8_t PBA0CLKREL

[0..0] PBA0 Clock Divider

◆ PD

[2..2] Power Down Mode Enable. Active High.

◆ PDM0

__IOM uint8_t PDM0

[2..0] P0.0 Port Driver Mode

[2..0] P1.0 Port Driver Mode

◆ PDM1

__IOM uint8_t PDM1

[6..4] P0.1 Port Driver Mode

[6..4] P1.1 Port Driver Mode

◆ PDM2

__IOM uint8_t PDM2

[2..0] P0.2 Port Driver Mode

[2..0] P1.2 Port Driver Mode

◆ PDM3

__IOM uint8_t PDM3

[6..4] P0.3 Port Driver Mode

[6..4] P1.3 Port Driver Mode

◆ PDM4

__IOM uint8_t PDM4

[2..0] P0.4 Port Driver Mode

[2..0] P1.4 Port Driver Mode

◆ PG100TP_CHKS_ERR

__IOM uint8_t PG100TP_CHKS_ERR

[2..2] 100 TP Page Checksum Error

◆ PLL_CON

union { ... } PLL_CON

◆ PLL_LOCK

__IM uint8_t PLL_LOCK

[0..0] PLL Lock Indicator

◆ PMCON0

union { ... } PMCON0

◆ PMCON1

union { ... } PMCON1

◆ PMCON2

union { ... } PMCON2

◆ PRODID

__IM uint8_t PRODID

[7..3] Product ID

◆ PROTECT_S

__IM uint8_t PROTECT_S

[2..2] Bit-Protection Signal Status Bit

◆ R

[0..0] Baud Rate Generator Run Control Bit

◆ RAM_PROT_ERR

__IM uint8_t RAM_PROT_ERR

[6..6] RAM Access Protection

◆ RDBE

__IM uint8_t RDBE

[0..0] RAM Double Bit Error

◆ RDBEC

__OM uint8_t RDBEC

[0..0] RAM Double Bit Error Clear

◆ reg

(@ 0x00000000) NMI Clear Register, RESET_TYPE_3

(@ 0x00000004) Interrupt Request Register 0, RESET_TYPE_3

(@ 0x00000008) Interrupt Request Register 1, RESET_TYPE_3

(@ 0x0000000C) Interrupt Request Register 2, RESET_TYPE_3

(@ 0x00000010) Interrupt Request Register 3, RESET_TYPE_3

(@ 0x00000014) Interrupt Request Register 4, RESET_TYPE_3

(@ 0x00000018) NMI Status Register, RESET_TYPE_4

(@ 0x0000001C) Interrupt Enable Register 0, RESET_TYPE_4

(@ 0x00000024) NMI Control Register, RESET_TYPE_4

(@ 0x00000028) External Interrupt Control Register 0, RESET_TYPE_3

(@ 0x0000002C) Interrupt Request 0 Clear Register, RESET_TYPE_3

(@ 0x00000030) Peripheral Interrupt Enable Register 1, RESET_TYPE_3

(@ 0x00000034) Peripheral Interrupt Enable Register 2, RESET_TYPE_3

(@ 0x00000038) Peripheral Interrupt Enable Register 3, RESET_TYPE_3

(@ 0x0000003C) Peripheral Interrupt Enable Register 4, RESET_TYPE_3

(@ 0x00000040) Power Mode Control Register 0, RESET_TYPE_3

(@ 0x00000044) PLL Control Register, RESET_TYPE_4

(@ 0x00000048) Clock Control Register 1, RESET_TYPE_4

(@ 0x0000004C) Clock Control Register 2, RESET_TYPE_4

(@ 0x00000050) Watchdog Timer Control Register, RESET_TYPE_3

(@ 0x00000054) Analog Peripheral Clock Control 1 Register, RESET_TYPE_4

(@ 0x00000058) Analog Peripheral Clock Register 1, RESET_TYPE_4

(@ 0x0000005C) Analog Peripheral Clock Register 2, RESET_TYPE_4

(@ 0x00000060) Peripheral Management Control Register 1, RESET_TYPE_3

(@ 0x00000064) Peripheral Management Control Register 2, RESET_TYPE_3

(@ 0x00000068) Reset Control Register, RESET_TYPE_3

(@ 0x0000006C) Analog Peripheral Clock Control 2 Register, RESET_TYPE_4

(@ 0x00000070) System Control Register 0, RESET_TYPE_4

(@ 0x00000074) System Startup Status Register

(@ 0x00000078) Watchdog Timer Reload Register, RESET_TYPE_3

(@ 0x0000007C) Watchdog Window-Boundary Count, RESET_TYPE_3

(@ 0x00000080) Watchdog Timer, Low Byte, RESET_TYPE_3

(@ 0x00000084) Watchdog Timer, High Byte, RESET_TYPE_3

(@ 0x00000088) Baud Rate Control Register 1, RESET_TYPE_3

(@ 0x0000008C) Baud Rate Timer/Reload Register, Low Byte 1, RESET_TYPE_3

(@ 0x00000090) Baud Rate Timer/Reload Register, High Byte, RESET_TYPE_3

(@ 0x00000094) LIN Status Register, RESET_TYPE_3

(@ 0x00000098) Baud Rate Control Register 2, RESET_TYPE_3

(@ 0x0000009C) Baud Rate Timer/Reload Register, Low Byte 2, RESET_TYPE_3

(@ 0x000000A0) Baud Rate Timer/Reload Register, High Byte, RESET_TYPE_3

(@ 0x000000A4) LIN Status Clear Register, RESET_TYPE_3

(@ 0x000000A8) Identity Register, RESET_TYPE_3

(@ 0x000000AC) Password Register, RESET_TYPE_3

(@ 0x000000B0) OSC Control Register, RESET_TYPE_4

(@ 0x000000B4) Clock Output Control Register, RESET_TYPE_4

(@ 0x000000B8) Peripheral Input Select Register, RESET_TYPE_3

(@ 0x000000BC) Peripheral Input Select Register 1, RESET_TYPE_3

(@ 0x000000C0) Peripheral Input Select Register 2, RESET_TYPE_3

(@ 0x000000C4) Peripheral Input Select Register, RESET_TYPE_3

(@ 0x000000C8) Module Suspend Control Register 1, RESET_TYPE_3

(@ 0x000000CC) Module Suspend Control Register 2, RESET_TYPE_3

(@ 0x000000D0) GPT12 Peripheral Input Select Register, RESET_TYPE_3

(@ 0x000000D4) Error Detection and Correction Control Register, RESET_TYPE_3

(@ 0x000000D8) Error Detection and Correction Status Register, RESET_TYPE_4

(@ 0x000000DC) Memory Status Register, RESET_TYPE_3

(@ 0x000000E0) NVM Protection Status Register, RESET_TYPE_4

(@ 0x000000E4) Memory Access Status Register, RESET_TYPE_3

(@ 0x000000E8) Port Output Control Register, RESET_TYPE_3

(@ 0x000000EC) Port Output Control Register, RESET_TYPE_3

(@ 0x000000F0) Port Output Control Register, RESET_TYPE_3

(@ 0x000000F4) Temperature Compensation Control Register, RESET_TYPE_3

(@ 0x000000F8) Port Output Control Register, RESET_TYPE_3

(@ 0x000000FC) Port Output Control Register, RESET_TYPE_3

(@ 0x00000100) Port Output Control Register, RESET_TYPE_3

(@ 0x0000010C) Error Detection and Correction Status Clear Register, RESET_TYPE_3

(@ 0x00000144) DMA Interrupt Enable Register 1, RESET_TYPE_3

(@ 0x00000148) DMA Interrupt Enable Register 2, RESET_TYPE_3

(@ 0x0000014C) DMA Source Selection Register, RESET_TYPE_3

(@ 0x00000154) DMA Interrupt Control Register 1, RESET_TYPE_3

(@ 0x00000158) ADC1 Interrupt Control Register 2, RESET_TYPE_3

(@ 0x0000015C) General Purpose Timer 12 Interrupt Enable Register , RESET_TYPE_3

(@ 0x00000160) Timer and Counter Control/Status Register, RESET_TYPE_3

(@ 0x00000164) Timer and Counter Control/Status Clear Register, RESET_TYPE_3

(@ 0x00000178) Interrupt Request 1 Clear Register, RESET_TYPE_3

(@ 0x0000017C) Interrupt Request 2 Clear Register, RESET_TYPE_3

(@ 0x00000180) DMA Source Selection Register 2, RESET_TYPE_3

(@ 0x00000184) DMA Interrupt Control 1 Clear Register, RESET_TYPE_3

(@ 0x00000188) ADC1 Interrupt Control 2 Clear Register, RESET_TYPE_3

(@ 0x00000190) Interrupt Request 3 Clear Register, RESET_TYPE_3

(@ 0x00000194) Interrupt Request 4 Clear Register, RESET_TYPE_3

(@ 0x00000198) DMA Source Selection Clear Register, RESET_TYPE_3

◆ RESERVED

__IM uint8_t RESERVED[3]

◆ RESERVED1

__IM uint8_t RESERVED1[3]

◆ RESERVED10

__IM uint8_t RESERVED10[3]

◆ RESERVED11

__IM uint8_t RESERVED11[3]

◆ RESERVED12

__IM uint8_t RESERVED12[3]

◆ RESERVED13

__IM uint8_t RESERVED13[3]

◆ RESERVED14

__IM uint8_t RESERVED14[3]

◆ RESERVED15

__IM uint8_t RESERVED15[3]

◆ RESERVED16

__IM uint8_t RESERVED16[3]

◆ RESERVED17

__IM uint8_t RESERVED17[3]

◆ RESERVED18

__IM uint8_t RESERVED18[3]

◆ RESERVED19

__IM uint8_t RESERVED19[3]

◆ RESERVED2

__IM uint8_t RESERVED2[3]

◆ RESERVED20

__IM uint8_t RESERVED20[3]

◆ RESERVED21

__IM uint8_t RESERVED21[3]

◆ RESERVED22

__IM uint8_t RESERVED22[3]

◆ RESERVED23

__IM uint8_t RESERVED23[3]

◆ RESERVED24

__IM uint8_t RESERVED24[3]

◆ RESERVED25

__IM uint8_t RESERVED25[3]

◆ RESERVED26

__IM uint8_t RESERVED26[3]

◆ RESERVED27

__IM uint8_t RESERVED27[3]

◆ RESERVED28

__IM uint8_t RESERVED28[3]

◆ RESERVED29

__IM uint8_t RESERVED29[3]

◆ RESERVED3

__IM uint8_t RESERVED3[3]

◆ RESERVED30

__IM uint8_t RESERVED30[3]

◆ RESERVED31

__IM uint8_t RESERVED31[3]

◆ RESERVED32

__IM uint8_t RESERVED32[3]

◆ RESERVED33

__IM uint8_t RESERVED33[3]

◆ RESERVED34

__IM uint8_t RESERVED34[3]

◆ RESERVED35

__IM uint8_t RESERVED35[3]

◆ RESERVED36

__IM uint8_t RESERVED36[3]

◆ RESERVED37

__IM uint8_t RESERVED37[3]

◆ RESERVED38

__IM uint8_t RESERVED38[3]

◆ RESERVED39

__IM uint8_t RESERVED39[3]

◆ RESERVED4

__IM uint8_t RESERVED4[3]

◆ RESERVED40

__IM uint8_t RESERVED40[3]

◆ RESERVED41

__IM uint8_t RESERVED41[3]

◆ RESERVED42

__IM uint8_t RESERVED42[3]

◆ RESERVED43

__IM uint8_t RESERVED43[3]

◆ RESERVED44

__IM uint8_t RESERVED44[3]

◆ RESERVED45

__IM uint8_t RESERVED45[3]

◆ RESERVED46

__IM uint8_t RESERVED46[3]

◆ RESERVED47

__IM uint8_t RESERVED47[3]

◆ RESERVED48

__IM uint8_t RESERVED48[3]

◆ RESERVED49

__IM uint8_t RESERVED49[3]

◆ RESERVED5

__IM uint8_t RESERVED5[3]

◆ RESERVED50

__IM uint8_t RESERVED50[3]

◆ RESERVED51

__IM uint8_t RESERVED51[3]

◆ RESERVED52

__IM uint8_t RESERVED52[3]

◆ RESERVED53

__IM uint8_t RESERVED53[3]

◆ RESERVED54

__IM uint8_t RESERVED54[3]

◆ RESERVED55

__IM uint8_t RESERVED55[3]

◆ RESERVED56

__IM uint8_t RESERVED56[3]

◆ RESERVED57

__IM uint8_t RESERVED57[3]

◆ RESERVED58

__IM uint8_t RESERVED58[3]

◆ RESERVED59

__IM uint8_t RESERVED59[3]

◆ RESERVED6

__IM uint8_t RESERVED6[3]

◆ RESERVED60

__IM uint8_t RESERVED60[3]

◆ RESERVED61

__IM uint8_t RESERVED61[3]

◆ RESERVED62

__IM uint8_t RESERVED62[3]

◆ RESERVED63

__IM uint8_t RESERVED63[11]

◆ RESERVED64

__IM uint8_t RESERVED64[55]

◆ RESERVED65

__IM uint8_t RESERVED65[3]

◆ RESERVED66

__IM uint8_t RESERVED66[3]

◆ RESERVED67

__IM uint8_t RESERVED67[7]

◆ RESERVED68

__IM uint8_t RESERVED68[3]

◆ RESERVED69

__IM uint8_t RESERVED69[3]

◆ RESERVED7

__IM uint8_t RESERVED7[7]

◆ RESERVED70

__IM uint8_t RESERVED70[3]

◆ RESERVED71

__IM uint8_t RESERVED71[3]

◆ RESERVED72

__IM uint8_t RESERVED72[19]

◆ RESERVED73

__IM uint8_t RESERVED73[3]

◆ RESERVED74

__IM uint8_t RESERVED74[3]

◆ RESERVED75

__IM uint8_t RESERVED75[3]

◆ RESERVED76

__IM uint8_t RESERVED76[3]

◆ RESERVED77

__IM uint8_t RESERVED77[7]

◆ RESERVED78

__IM uint8_t RESERVED78[3]

◆ RESERVED79

__IM uint8_t RESERVED79[3]

◆ RESERVED8

__IM uint8_t RESERVED8[3]

◆ RESERVED9

__IM uint8_t RESERVED9[3]

◆ RESLD

__IOM uint8_t RESLD

[1..1] Restart Lock Detection

◆ RIE

[0..0] RAM Double Bit ECC Error Interrupt Enable

◆ RIEN1

__IOM uint8_t RIEN1

[6..6] UART 1 Receive Interrupt Enable

◆ RIEN2

__IOM uint8_t RIEN2

[6..6] UART 2 Receive Interrupt Enable

◆ RIR

[2..2] Receive Interrupt Flag for SSC1

[2..2] Receive Interrupt Flag for SSC2

◆ RIRC

__OM uint8_t RIRC

[2..2] Receive Interrupt Flag for SSC1 Clear

[2..2] Receive Interrupt Flag for SSC2 Clear

◆ RIREN1

__IOM uint8_t RIREN1

[2..2] SSC 1 Receive Interrupt Enable

◆ RIREN2

__IOM uint8_t RIREN2

[2..2] SSC 2 Receive Interrupt Enable

◆ ROM_ADDR_ERR

__IM uint8_t ROM_ADDR_ERR

[5..5] ROM Address Protection

◆ ROM_PROT_ERR

__IM uint8_t ROM_PROT_ERR

[4..4] ROM Access Protection

◆ RSBE

__IM uint8_t RSBE

[4..4] RAM Single Bit Error

◆ RSBEC

__OM uint8_t RSBEC

[4..4] RAM Single Bit Error Clear

◆ RSTCON

union { ... } RSTCON

◆ SASTATUS

__IOM uint8_t SASTATUS

[7..6] Service Algorithm Status

◆ SD

[3..3] Slow Down Mode Enable. Active High.

◆ SDADC

__IM uint8_t SDADC

[6..6] DMA Channel 13 Interrupt Status (SDADC)

◆ SDADCC

__OM uint8_t SDADCC

[6..6] DMA Channel 13 Interrupt Status Clear (SDADC)

◆ SDADCCLK_DIV

__IOM uint8_t SDADCCLK_DIV

[1..0] SD-ADC Clock Divider

◆ SDADCIE

__IOM uint8_t SDADCIE

[6..6] DMA Channel 13 Interrupt Enable (SDADC)

◆ SECTORINFO

__IOM uint8_t SECTORINFO

[5..0] Sector Information

◆ SL

[1..1] Sleep Mode Enable. Active High.

◆ SSC1_DIS

__IOM uint8_t SSC1_DIS

[1..1] SSC1 Disable Request. Active high.

◆ SSC1C

__OM uint8_t SSC1C

[3..3] DMA Channel 2 Interrupt Status Clear (SSCx Transmit)

◆ SSC1RDY

__IM uint8_t SSC1RDY

[3..3] DMA Channel 2 Interrupt Status (SSCx Transmit)

◆ SSC2_DIS

__IOM uint8_t SSC2_DIS

[1..1] SSC2 Disable Request. Active high.

◆ SSC2C

__OM uint8_t SSC2C

[4..4] DMA Channel 3 Interrupt Status Clear (SSCx Receive)

◆ SSC2RDY

__IM uint8_t SSC2RDY

[4..4] DMA Channel 3 Interrupt Status (SSCx Receive)

◆ SSCRX

__IM uint8_t SSCRX

[6..6] DMA Channel 3 Request (SSCx Receive)

◆ SSCRXC

__OM uint8_t SSCRXC

[6..6] SSC Receive Request Clear

◆ SSCRXIE

__IOM uint8_t SSCRXIE

[4..4] DMA Channel 3 Interrupt Enable (SSCx Receive)

◆ SSCRXSRCSEL

__IOM uint8_t SSCRXSRCSEL

[1..1] SSCx Receive Source Select

◆ SSCTX

__IM uint8_t SSCTX

[5..5] DMA Channel 2 Request (SSCx Transmit)

◆ SSCTXC

__OM uint8_t SSCTXC

[5..5] SSC Transmit Request Clear

◆ SSCTXIE

__IOM uint8_t SSCTXIE

[3..3] DMA Channel 2 Interrupt Enable (SSCx Transmit)

◆ SSCTXSRCSEL

__IOM uint8_t SSCTXSRCSEL

[0..0] SSCx Transmit Source Select

◆ STRDY

__IM uint8_t STRDY

[0..0] DMA Single Transfer Ready

◆ SYNEN

__IOM uint8_t SYNEN

[6..6] End of SYN Byte and SYN Byte Error Interrupts Enable

◆ SYS_STRTUP_STS

union { ... } SYS_STRTUP_STS

◆ SYSCLKSEL

__IOM uint8_t SYSCLKSEL

[7..6] System Clock Select

◆ SYSCON0

union { ... } SYSCON0

◆ T12PM_DMAEN

__IOM uint8_t T12PM_DMAEN

[3..3] CC6_T12_PM (Period Match) DMA muxer, DMA channel 11

◆ T12SUSP

__IOM uint8_t T12SUSP

[1..1] Timer 12 Debug Suspend Bit

◆ T12ZM_DMAEN

__IOM uint8_t T12ZM_DMAEN

[2..2] CC6_T12_ZM (Zero Match) DMA muxer, DMA channel 9

◆ T13SUSP

__IOM uint8_t T13SUSP

[2..2] Timer 13 Debug Suspend Bit

◆ T2

[0..0] GPT Module 1 Timer 2 Interrupt Status

◆ T21_DIS

__IOM uint8_t T21_DIS

[3..3] T21 Disable Request. Active high.

◆ T21_SUSP

__IOM uint8_t T21_SUSP

[6..6] Timer21 Debug Suspend Bit

◆ T21EXCON

__IOM uint8_t T21EXCON

[7..7] Timer 21 External Input Control

◆ T21EXIS

__IOM uint8_t T21EXIS

[7..6] Timer 21 External Input Select

◆ T21IS

__IOM uint8_t T21IS

[3..2] Timer 21 Input Select

◆ T2_DIS

__IOM uint8_t T2_DIS

[3..3] T2 Disable Request. Active high.

◆ T2_SUSP

__IOM uint8_t T2_SUSP

[3..3] Timer2 Debug Suspend Bit

◆ T2C

[0..0] GPT Module 1 Timer 2 Interrupt Status Clear

◆ T2EXCON

__IOM uint8_t T2EXCON

[6..6] Timer 2 External Input Control

◆ T2EXIS

__IOM uint8_t T2EXIS

[5..4] Timer 2 External Input Select

◆ T2IE

__IOM uint8_t T2IE

[0..0] General Purpose Timer 12 T2 Interrupt Enable

◆ T2IS

__IOM uint8_t T2IS

[1..0] Timer 2 Input Select

◆ T3

[1..1] GPT Module 1 Timer3 Interrupt Status

◆ T3_DIS

__IOM uint8_t T3_DIS

[5..5] T3 Disable Request. Active high.

◆ T3_GPT12_SEL

__IOM uint8_t T3_GPT12_SEL

[5..5] CCU6_INT_SEL.

◆ T3_SUSP

__IOM uint8_t T3_SUSP

[0..0] Measurement Unit Debug Suspend Bit

◆ T3C

[1..1] GPT Module 1 Timer3 Interrupt Status Clear

◆ T3CLK_DIV

__IOM uint8_t T3CLK_DIV

[3..2] Timer 3 Clock Divider

◆ T3CLK_SEL

__IOM uint8_t T3CLK_SEL

[2..2] Timer 3 Clock Selection

◆ T3IE

__IOM uint8_t T3IE

[1..1] General Purpose Timer 12 T3 Interrupt Enable

◆ T4

[2..2] GPT Module 1 Timer4 Interrupt Status

◆ T4C

[2..2] GPT Module 1 Timer4 Interrupt Status Clear

◆ T4IE

__IOM uint8_t T4IE

[2..2] General Purpose Timer 12 T4 Interrupt Enable

◆ T5

[3..3] GPT Module 2 Timer5 Interrupt Status

◆ T5C

[3..3] GPT Module 2 Timer5 Interrupt Status Clear

◆ T5IE

__IOM uint8_t T5IE

[3..3] General Purpose Timer 12 T5 Interrupt Enable

◆ T6

[4..4] GPT Module 2Timer6 Interrupt Status

◆ T6C

[4..4] GPT Module 2Timer6 Interrupt Status Clear

◆ T6IE

__IOM uint8_t T6IE

[4..4] General Purpose Timer 12 T6 Interrupt Enable

◆ TCC

[1..0] Temperature Compensation Control

◆ TCCR

union { ... } TCCR

◆ TIEN1

__IOM uint8_t TIEN1

[7..7] UART 1 Transmit Interrupt Enable

◆ TIEN2

__IOM uint8_t TIEN2

[7..7] UART 2 Transmit Interrupt Enable

◆ TIR

[1..1] Transmit Interrupt Flag for SSC1

[1..1] Transmit Interrupt Flag for SSC2

◆ TIRC

__OM uint8_t TIRC

[1..1] Transmit Interrupt Flag for SSC1 Clear

[1..1] Transmit Interrupt Flag for SSC2 Clear

◆ TIREN1

__IOM uint8_t TIREN1

[1..1] SSC 1 Transmit Interrupt Enable

◆ TIREN2

__IOM uint8_t TIREN2

[1..1] SSC 2 Transmit Interrupt Enable

◆ TLEN

__IOM uint8_t TLEN

[5..5] Toggle Latch Enable

◆ TRERRIE

__IOM uint8_t TRERRIE

[0..0] DMA Transfer Error Interrupt Enable

◆ TRIG_CONF

__IOM uint8_t TRIG_CONF

[4..4] CCU6 Trigger Configuration.

◆ TRSEQ1DY

__IM uint8_t TRSEQ1DY

[1..1] DMA Channel 0 Interrupt Status (ADC1 Sequence)

◆ TRSEQ1DYC

__OM uint8_t TRSEQ1DYC

[1..1] DMA Channel 0 Interrupt Status Clear (ADC1 Sequence)

◆ TRSEQ1RDYIE

__IOM uint8_t TRSEQ1RDYIE

[1..1] DMA Channel 0 Interrupt Enable (ADC1 Sequence)

◆ TRSEQ2DY

__IM uint8_t TRSEQ2DY

[2..2] DMA Channel 1 Interrupt Status (ADC1 ESM)

◆ TRSEQ2DYC

__OM uint8_t TRSEQ2DYC

[2..2] DMA Channel 1 Interrupt Status Clear (ADC1 ESM)

◆ TRSEQ2RDYIE

__IOM uint8_t TRSEQ2RDYIE

[2..2] DMA Channel 1 Interrupt Enable (ADC1 ESM)

◆ U_TX_CONDIS

__IOM uint8_t U_TX_CONDIS

[7..7] UART1 TxD Connection Disable

◆ uint8_t

__IM uint8_t

◆ URIOS1

__IOM uint8_t URIOS1

[6..6] UART1 Input/Output Select

◆ URIOS2

__IOM uint8_t URIOS2

[6..6] UART2 Input/Output Select

◆ VCOBYP

__IOM uint8_t VCOBYP

[3..3] PLL VCO Bypass Mode Select

◆ VCOSEL

__IOM uint8_t VCOSEL

[7..7] VCOSEL Setting

◆ VERID

__IM uint8_t VERID

[2..0] Version ID

◆ WDT

[7..0] Watchdog Timer Current Value

◆ WDTCON

union { ... } WDTCON

◆ WDTEN

__IOM uint8_t WDTEN

[2..2] WDT Enable

◆ WDTH

union { ... } WDTH

◆ WDTIN

__IOM uint8_t WDTIN

[0..0] Watchdog Timer Input Frequency Selection

◆ WDTL

union { ... } WDTL

◆ WDTPR

__IM uint8_t WDTPR

[4..4] Watchdog Prewarning Mode Flag

◆ WDTREL [1/2]

__IOM uint8_t WDTREL

[7..0] Watchdog Timer Reload Value

◆ WDTREL [2/2]

union { ... } WDTREL

◆ WDTRS

__IOM uint8_t WDTRS

[1..1] WDT Refresh Start

◆ WDTSUSP

__IOM uint8_t WDTSUSP

[0..0] SCU Watchdog Timer Debug Suspend Bit

◆ WDTWINB [1/2]

__IOM uint8_t WDTWINB

[7..0] Watchdog Window-Boundary Count Value

◆ WDTWINB [2/2]

union { ... } WDTWINB

◆ WINBEN

__IOM uint8_t WINBEN

[5..5] Watchdog Window-Boundary Enable

◆ XPD

[4..4] XTAL (OSC_HP) Power Down Control

◆ XTAL_ON

__IOM uint8_t XTAL_ON

[0..0] OSC_HP Operation in Power Down Mode


The documentation for this struct was generated from the following file: