TLE986x Device Family SDK
adc1.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2015, Infineon Technologies AG
5  * All rights reserved.
6  *
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9  *
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11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** DM Daniel Mysliwitz **
45 ** DCM Dragos C. Molocea **
46 ** JO Julia Ott **
47 ** BG Blandine Guillot **
48 *******************************************************************************/
49 
50 /*******************************************************************************
51 ** Revision Control History **
52 ********************************************************************************
53 ** V0.1.0: ? , DM: Initial version **
54 ** V0.1.1: 2015-02-10, DM: Individual header file added **
55 ** V0.1.2: 2015-03-10, DM: MF->REF2_CTRL added **
56 ** V0.1.3: 2015-03-22, DM: ADC Busy function added **
57 ** V0.1.4: 2015-11-26, DM: VAREF enable function added **
58 ** V0.1.5: 2017-02-16, DM: Attenuator for Ch6(VDH) voltage calculation added**
59 ** Adc1 prefix changed to ADC1 **
60 ** V0.1.6: 2017-03-23, DM: ADC1 API extended **
61 ** V0.1.7: 2017-11-09, DM: Port2 analog input init added **
62 ** V0.1.8: 2017-11-13, DM: MISRA 2012 compliance, the following PC-Lint **
63 ** rules are globally deactivated: **
64 ** - Info 793: ANSI/ISO limit of 6 'significant **
65 ** characters in an external identifier **
66 ** - Info 835: A zero has been given as right **
67 ** argument to operator **
68 ** - Info 845: The left argument to operator '&' **
69 ** is certain to be 0 **
70 ** Replaced macros by INLINE functions **
71 ** Replaced register accesses within functions by **
72 ** function calls **
73 ** Replaced __STATIC_INLINE by INLINE **
74 ** V0.1.9: 2018-03-14, DM: VAREF_Enable() reworked for MISRA 2012 **
75 ** ADC1_MASK_CHx macros rworked for MISRA 2012 **
76 ** ADC1_ANON_Sts() converted to infline function **
77 ** due to MISRA 2012 **
78 ** V0.2.0: 2018-06-27, DCM: Conversion formula from digital value to mv **
79 ** changed based on the software unit test findings **
80 ** and simplified according to new specifications **
81 ** V0.2.1: 2018-07-05, BG: In adc1.h: ADC1_Chx_Result_Get(), **
82 ** ADC1_EIM_Channel_Set(u32), ADC1_SW_Ch_Sel(u32), **
83 ** ADC1_SOC_Set(), ADC1_ANON_Set(u32), **
84 ** ADC1_Power_On(), ADC1_EOC_Sts(), ADC1_Busy_Sts(),**
85 ** ADC1_EIM_Active_Sts(), ADC1_ESM_Active_Sts() **
86 ** reworked for testing lv2 functions **
87 ** V0.2.2: 2018-08-01, DM: DoxyGen comments updated **
88 ** V0.2.3: 2018-11-09, JO: Renamed **
89 ** - ADC1_VDH_Attenuator_Range_0_22V_Set -> **
90 ** ADC1_VDH_Attenuator_Range_0_20V_Set **
91 ** - ADC1_VDH_Attenuator_Range_0_28V_Set -> **
92 ** ADC1_VDH_Attenuator_Range_0_30V_Set **
93 ** - ADC1_VDH_Attenuator_Range_0_22V -> **
94 ** ADC1_VDH_Attenuator_Range_0_20V **
95 ** - ADC1_VDH_Attenuator_Range_0_28V -> **
96 ** ADC1_VDH_Attenuator_Range_0_30V **
97 ** V0.2.4: 2018-11-27, JO: moved revision history from adc1.c to adc1.h **
98 ** V0.2.5: 2020-02-28, BG: Updated revision history format **
99 ** V0.2.6: 2020-10-12, JO: EP-506: remove ARMCC v6 Compiler warnings **
100 ** - Added typecasts to remove 'implicit typecast' **
101 ** warning **
102 *******************************************************************************/
103 
104 #ifndef ADC1_H
105 #define ADC1_H
106 
107 /*******************************************************************************
108 ** Includes **
109 *******************************************************************************/
110 #include "tle986x.h"
111 #include "types.h"
112 #include "adc1_defines.h"
113 #include "sfr_access.h"
114 
115 /*******************************************************************************
116 ** Global Constant Declarations **
117 *******************************************************************************/
118 
120 #define ADC1_VDH_Attenuator_Range_0_30V (1u)
121 
122 #define ADC1_VDH_Attenuator_Range_0_20V (0u)
123 
125 #define SW_MODE 0u
126 
127 #define SEQ_MODE 1u
128 
130 #define SKIP 0u
131 
132 #define MEAS 1u
133 
135 #define BIT10 0u
136 
137 #define BIT8 1u
138 
140 #define INTDIS 0u
141 
142 #define INTEN 1u
143 
145 #define OVERWRITE 0u
146 
147 #define WFR 1u
148 
150 #define ADC1_CH0 (0)
151 
152 #define ADC1_CH1 (1)
153 
154 #define ADC1_CH2 (2)
155 
156 #define ADC1_CH3 (3)
157 
158 #define ADC1_CH4 (4)
159 
160 #define ADC1_CH5 (5)
161 
162 #define ADC1_CH6 (6)
163 
164 #define ADC1_EIM (8)
165 
167 #define ADC1_P20 ADC1_CH0
168 
169 #define ADC1_CSA ADC1_CH1
170 
171 #define ADC1_P22 ADC1_CH2
172 
173 #define ADC1_P23 ADC1_CH3
174 
175 #define ADC1_P24 ADC1_CH4
176 
177 #define ADC1_P25 ADC1_CH5
178 
179 #define ADC1_VDH ADC1_CH6
180 
181 /* ESM Channel */
183 #define ADC1_MASK_CH0 ((uint32)1u << ADC1_CH0)
184 
185 #define ADC1_MASK_CH1 ((uint32)1u << ADC1_CH1)
186 
187 #define ADC1_MASK_CH2 ((uint32)1u << ADC1_CH2)
188 
189 #define ADC1_MASK_CH3 ((uint32)1u << ADC1_CH3)
190 
191 #define ADC1_MASK_CH4 ((uint32)1u << ADC1_CH4)
192 
193 #define ADC1_MASK_CH5 ((uint32)1u << ADC1_CH5)
194 
195 #define ADC1_MASK_CH6 ((uint32)1u << ADC1_CH6)
196 
198 #define ADC1_MASK_P20 (ADC1_MASK_CH0)
199 
200 #define ADC1_MASK_CSA (ADC1_MASK_CH1)
201 
202 #define ADC1_MASK_P22 (ADC1_MASK_CH2)
203 
204 #define ADC1_MASK_P23 (ADC1_MASK_CH3)
205 
206 #define ADC1_MASK_P24 (ADC1_MASK_CH4)
207 
208 #define ADC1_MASK_P25 (ADC1_MASK_CH5)
209 
210 #define ADC1_MASK_VDH (ADC1_MASK_CH6)
211 
213 #define ADC1_VREF_5000mV 5000u
214 
215 #define ADC1_VREF_22000mV 22000u
216 
217 #define ADC1_VREF_30000mV 30000u
218 
219 /*******************************************************************************
220 ** ADC1 Analog Module select enum **
221 *******************************************************************************/
225 typedef enum
226 {
227  ADC1_ANON_OFF = 0,
229  ADC1_ANON_F_STANDBY = 2,
232 
233 typedef union
234 {
235  uint32 dword;
236  TADC1_ANON adc1_anon;
237 } TADC1_ANON_U;
238 
239 /*******************************************************************************
240 ** ADC1 trigger select enum **
241 *******************************************************************************/
245 typedef enum
246 {
248  ADC1_Trigg_CCU6_Ch3 = 1,
251  ADC1_Trigg_Timer2 = 4,
252  ADC1_Trigg_Timer21 = 5,
253  ADC1_Trigg_Timer3 = 6
255 
256 /*******************************************************************************
257 ** ADC1 EIM repeat count enum **
258 *******************************************************************************/
263 typedef enum
264 {
266  ADC1_2_Meas = 1,
267  ADC1_4_Meas = 2,
268  ADC1_8_Meas = 3,
269  ADC1_16_Meas = 4,
270  ADC1_32_Meas = 5,
271  ADC1_64_Meas = 6,
272  ADC1_128_Meas = 7
274 
275 /*******************************************************************************
276 ** Global Macro Declarations **
277 *******************************************************************************/
278 
279 /*******************************************************************************
280 ** Global Function Declarations **
281 *******************************************************************************/
282 
283 /******************************************************************************/
288 void ADC1_Init(void);
289 
290 
311 bool VAREF_Enable(void);
312 
313 
345 bool ADC1_GetChResult(uint16 *pVar, uint8 channel);
346 
347 
378 bool ADC1_GetChResult_mV(uint16 *pVar_mV, uint8 channel);
379 
380 
411 bool ADC1_GetEIMResult(uint16 *pVar);
412 
413 
444 bool ADC1_GetEIMResult_mV(uint16 *pVar_mV);
445 
446 
476 INLINE void ADC1_SetEIMChannel(uint8 channel);
477 
478 
494 INLINE void ADC1_SetSwMode_Channel(uint8 channel);
495 
496 
514 INLINE void ADC1_SetMode(uint8 mode);
515 
516 
535 
536 
559 INLINE bool ADC1_GetEocSwMode(void);
560 
561 
593 
594 
625 INLINE bool ADC1_GetSwModeResult_mV(uint16 *pVar_mV);
626 
627 
655 INLINE bool ADC1_Busy(void);
656 
657 
676 
677 
696 
697 
716 
717 
740 INLINE bool ADC1_isEndOfConversion(void);
741 
742 
766 INLINE bool ADC1_isEIMactive(void);
767 
768 
792 INLINE bool ADC1_isESMactive(void);
793 
794 
813 
814 
815 /*******************************************************************************
816 ** Global Inline Function Definitions **
817 *******************************************************************************/
830 INLINE void ADC1_Power_On(void)
831 {
833 }
834 
847 INLINE void ADC1_Power_Off(void)
848 {
850 }
851 
864 INLINE void ADC1_SOC_Set(void)
865 {
867 }
868 
885 {
887 }
888 
905 {
907 }
908 
924 {
926 }
927 
945 {
947 }
948 
968 {
970 }
971 
995 {
996  return ( u1_Field_Rd32(&ADC1->CTRL_STS.reg, ADC1_CTRL_STS_EOC_Pos, ADC1_CTRL_STS_EOC_Msk) );
997 }
998 
1025 {
1026  return ( u8_Field_Rd32(&ADC1->GLOBSTR.reg, ADC1_GLOBSTR_CHNR_Pos, ADC1_GLOBSTR_CHNR_Msk) );
1027 }
1028 
1058 {
1060 }
1061 
1090 {
1091  return ( u1_Field_Rd32(&ADC1->GLOBSTR.reg, ADC1_GLOBSTR_BUSY_Pos, ADC1_GLOBSTR_BUSY_Msk) );
1092 }
1093 
1116 {
1118 }
1119 
1142 {
1144 }
1145 
1166 {
1167  return ( u8_Field_Rd32(&ADC1->SQ_FB.reg, ADC1_SQ_FB_SQx_Pos, ADC1_SQ_FB_SQx_Msk) );
1168 }
1169 
1190 {
1191  return ( u8_Field_Rd32(&ADC1->SQ_FB.reg, ADC1_SQ_FB_CHx_Pos, ADC1_SQ_FB_CHx_Msk) );
1192 }
1193 
1211 INLINE void ADC1_Sequence0_Set(uint32 mask_ch)
1212 {
1213  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ1_Pos, ADC1_SQ1_4_SQ1_Msk, (mask_ch));
1214 }
1215 
1234 INLINE void ADC1_Sequence1_Set(uint32 mask_ch)
1235 {
1236  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ2_Pos, ADC1_SQ1_4_SQ2_Msk, (mask_ch));
1237 }
1238 
1257 INLINE void ADC1_Sequence2_Set(uint32 mask_ch)
1258 {
1259  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ3_Pos, ADC1_SQ1_4_SQ3_Msk, (mask_ch));
1260 }
1261 
1280 INLINE void ADC1_Sequence3_Set(uint32 mask_ch)
1281 {
1282  Field_Mod32(&ADC1->SQ1_4.reg, ADC1_SQ1_4_SQ4_Pos, ADC1_SQ1_4_SQ4_Msk, (mask_ch));
1283 }
1284 
1303 INLINE void ADC1_Sequence4_Set(uint32 mask_ch)
1304 {
1305  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ5_Pos, ADC1_SQ5_8_SQ5_Msk, (mask_ch));
1306 }
1307 
1326 INLINE void ADC1_Sequence5_Set(uint32 mask_ch)
1327 {
1328  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ6_Pos, ADC1_SQ5_8_SQ6_Msk, (mask_ch));
1329 }
1330 
1349 INLINE void ADC1_Sequence6_Set(uint32 mask_ch)
1350 {
1351  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ7_Pos, ADC1_SQ5_8_SQ7_Msk, (mask_ch));
1352 }
1353 
1372 INLINE void ADC1_Sequence7_Set(uint32 mask_ch)
1373 {
1374  Field_Mod32(&ADC1->SQ5_8.reg, ADC1_SQ5_8_SQ8_Pos, ADC1_SQ5_8_SQ8_Msk, (mask_ch));
1375 }
1376 
1403 {
1405 }
1406 
1433 {
1435 }
1436 
1463 {
1465 }
1466 
1493 {
1495 }
1496 
1523 {
1525 }
1526 
1553 {
1555 }
1556 
1583 {
1585 }
1586 
1614 {
1616 }
1617 
1644 {
1645  return ( ADC1_Ch0_Result_Get() );
1646 }
1647 
1674 {
1675  return ( ADC1_Ch1_Result_Get() );
1676 }
1677 
1704 {
1705  return ( ADC1_Ch2_Result_Get() );
1706 }
1707 
1734 {
1735  return ( ADC1_Ch3_Result_Get() );
1736 }
1737 
1764 {
1765  return ( ADC1_Ch4_Result_Get() );
1766 }
1767 
1794 {
1795  return ( ADC1_Ch5_Result_Get() );
1796 }
1797 
1824 {
1825  return ( ADC1_Ch6_Result_Get() );
1826 }
1827 
1856 {
1857  return ( u1_Field_Rd32(&ADC1->RES_OUT0.reg, ADC1_RES_OUT0_VF0_Pos, ADC1_RES_OUT0_VF0_Msk) );
1858 }
1859 
1888 {
1889  return ( u1_Field_Rd32(&ADC1->RES_OUT1.reg, ADC1_RES_OUT1_VF1_Pos, ADC1_RES_OUT1_VF1_Msk) );
1890 }
1891 
1920 {
1921  return ( u1_Field_Rd32(&ADC1->RES_OUT2.reg, ADC1_RES_OUT2_VF2_Pos, ADC1_RES_OUT2_VF2_Msk) );
1922 }
1923 
1952 {
1953  return ( u1_Field_Rd32(&ADC1->RES_OUT3.reg, ADC1_RES_OUT3_VF3_Pos, ADC1_RES_OUT3_VF3_Msk) );
1954 }
1955 
1984 {
1985  return ( u1_Field_Rd32(&ADC1->RES_OUT4.reg, ADC1_RES_OUT4_VF4_Pos, ADC1_RES_OUT4_VF4_Msk) );
1986 }
1987 
2016 {
2017  return ( u1_Field_Rd32(&ADC1->RES_OUT5.reg, ADC1_RES_OUT5_VF5_Pos, ADC1_RES_OUT5_VF5_Msk) );
2018 }
2019 
2048 {
2049  return ( u1_Field_Rd32(&ADC1->RES_OUT6.reg, ADC1_RES_OUT6_VF6_Pos, ADC1_RES_OUT6_VF6_Msk) );
2050 }
2051 
2081 {
2082  return ( u1_Field_Rd32(&ADC1->RES_OUT_EIM.reg, ADC1_RES_OUT_EIM_VF8_Pos, ADC1_RES_OUT_EIM_VF8_Msk) );
2083 }
2084 
2107 {
2109 }
2110 
2133 {
2135 }
2136 
2159 {
2161 }
2162 
2185 {
2187 }
2188 
2211 {
2213 }
2214 
2237 {
2239 }
2240 
2263 {
2265 }
2266 
2289 {
2291 }
2292 
2315 {
2317 }
2318 
2341 {
2343 }
2344 
2367 {
2369 }
2370 
2393 {
2395 }
2396 
2419 {
2421 }
2422 
2445 {
2447 }
2448 
2474 {
2476 }
2477 
2503 {
2505 }
2506 
2532 {
2534 }
2535 
2561 {
2563 }
2564 
2590 {
2592 }
2593 
2619 {
2621 }
2622 
2648 {
2650 }
2651 
2678 {
2680 }
2681 
2707 INLINE void ADC1_Ch0_Overwrite_Set(void)
2708 {
2710 }
2711 
2738 {
2740 }
2741 
2767 INLINE void ADC1_Ch1_Overwrite_Set(void)
2768 {
2770 }
2771 
2798 {
2800 }
2801 
2827 INLINE void ADC1_Ch2_Overwrite_Set(void)
2828 {
2830 }
2831 
2858 {
2860 }
2861 
2887 INLINE void ADC1_Ch3_Overwrite_Set(void)
2888 {
2890 }
2891 
2918 {
2920 }
2921 
2947 INLINE void ADC1_Ch4_Overwrite_Set(void)
2948 {
2950 }
2951 
2978 {
2980 }
2981 
3007 INLINE void ADC1_Ch5_Overwrite_Set(void)
3008 {
3010 }
3011 
3038 {
3040 }
3041 
3067 INLINE void ADC1_Ch6_Overwrite_Set(void)
3068 {
3070 }
3071 
3099 {
3101 }
3102 
3129 INLINE void ADC1_ESM_Channel_Set(uint32 mask_ch)
3130 {
3131  Field_Mod32(&ADC1->CHx_ESM.reg, ADC1_CHx_ESM_ESM_0_Pos, ADC1_CHx_ESM_ESM_0_Msk, (mask_ch));
3132 }
3133 
3165 INLINE void ADC1_VDH_Attenuator_On(void)
3166 {
3168 }
3169 
3201 {
3203 }
3204 
3237 {
3239 }
3240 
3273 {
3275 }
3276 
3294 INLINE void ADC1_Ch0_Int_Clr(void)
3295 {
3297 }
3298 
3316 INLINE void ADC1_Ch1_Int_Clr(void)
3317 {
3319 }
3320 
3338 INLINE void ADC1_Ch2_Int_Clr(void)
3339 {
3341 }
3342 
3360 INLINE void ADC1_Ch3_Int_Clr(void)
3361 {
3363 }
3364 
3382 INLINE void ADC1_Ch4_Int_Clr(void)
3383 {
3385 }
3386 
3403 INLINE void ADC1_Ch5_Int_Clr(void)
3404 {
3406 }
3407 
3425 INLINE void ADC1_Ch6_Int_Clr(void)
3426 {
3428 }
3429 
3448 INLINE void ADC1_EIM_Int_Clr(void)
3449 {
3451 }
3452 
3470 INLINE void ADC1_ESM_Int_Clr(void)
3471 {
3473 }
3474 
3492 INLINE void ADC1_Ch0_Int_En(void)
3493 {
3495 }
3496 
3515 INLINE void ADC1_Ch0_Int_Dis(void)
3516 {
3518 }
3519 
3537 INLINE void ADC1_Ch1_Int_En(void)
3538 {
3540 }
3541 
3560 INLINE void ADC1_Ch1_Int_Dis(void)
3561 {
3563 }
3564 
3582 INLINE void ADC1_Ch2_Int_En(void)
3583 {
3585 }
3586 
3605 INLINE void ADC1_Ch2_Int_Dis(void)
3606 {
3608 }
3609 
3627 INLINE void ADC1_Ch3_Int_En(void)
3628 {
3630 }
3631 
3650 INLINE void ADC1_Ch3_Int_Dis(void)
3651 {
3653 }
3654 
3672 INLINE void ADC1_Ch4_Int_En(void)
3673 {
3675 }
3676 
3695 INLINE void ADC1_Ch4_Int_Dis(void)
3696 {
3698 }
3699 
3717 INLINE void ADC1_Ch5_Int_En(void)
3718 {
3720 }
3721 
3740 INLINE void ADC1_Ch5_Int_Dis(void)
3741 {
3743 }
3744 
3762 INLINE void ADC1_Ch6_Int_En(void)
3763 {
3765 }
3766 
3785 INLINE void ADC1_Ch6_Int_Dis(void)
3786 {
3788 }
3789 
3808 INLINE void ADC1_EIM_Int_En(void)
3809 {
3811 }
3812 
3832 INLINE void ADC1_EIM_Int_Dis(void)
3833 {
3835 }
3836 
3854 INLINE void ADC1_ESM_Int_En(void)
3855 {
3857 }
3858 
3877 INLINE void ADC1_ESM_Int_Dis(void)
3878 {
3880 }
3881 
3903 {
3905 }
3927 {
3929 }
3930 
3931 
3956 {
3958 }
3959 
3960 /*******************************************************************************
3961 ** Global Inline Function Definitions **
3962 *******************************************************************************/
3963 INLINE void ADC1_SetEIMChannel(uint8 channel)
3964 {
3965  ADC1_EIM_Channel_Set(channel);
3966 } /* End of ADC1_SetEIMChannel */
3967 
3969 {
3970  ADC1_SW_Ch_Sel(channel);
3971 } /* End of ADC1_SetSwMode_Channel */
3972 
3973 INLINE void ADC1_SetMode(uint8 mode)
3975  /* Set the "mode" input to ADC1->SQ_FB.bit.SQ_RUN */
3977 } /* End of ADC1_SetMode */
3978 
3980 {
3981  ADC1_SW_Ch_Sel(Ch);
3982  ADC1_SOC_Set();
3983 } /* End of ADC1_SetSocSwMode */
3984 
3985 INLINE bool ADC1_GetEocSwMode(void)
3987  bool res = false;
3988 
3989  if (ADC1_EOC_Sts() == (uint8)1)
3990  {
3991  res = true;
3992  }
3994  return (res);
3995 } /* End of ADC1_GetEocSwMode */
3996 
3998 {
3999  uint8 channel;
4001  return (ADC1_GetChResult(pVar, channel));
4002 } /* End of ADC1_GetSwModeResult */
4003 
4004 INLINE bool ADC1_GetSwModeResult_mV(uint16 *pVar_mV)
4005 {
4006  uint8 channel;
4008  return (ADC1_GetChResult_mV(pVar_mV, channel));
4009 } /* End of ADC1_GetSwModeResult */
4010 
4011 INLINE bool ADC1_Busy(void)
4013  bool res = false;
4014 
4015  if (ADC1_Busy_Sts() == (uint8)1)
4016  {
4017  res = true;
4018  }
4019 
4020  return (res);
4021 } /* End of ADC1_GetSwModeResult */
4022 
4025  /* Set the "trigsel" input to ADC1->CHx_EIM.bit.TRIG_SEL */
4027 }
4028 
4031  /* Set the "repcnt" input to ADC1->CHx_EIM.bit.REP */
4033 }
4034 
4036 {
4037  /* Set the "trigsel" input to ADC1->CHx_ESM.bit.TRIG_SEL */
4039 }
4040 
4041 INLINE bool ADC1_isEndOfConversion(void)
4043  bool res = false;
4044 
4045  if (ADC1_EOC_Sts() == (uint8)1)
4046  {
4047  res = true;
4048  }
4049 
4050  return (res);
4051 }
4052 
4053 INLINE bool ADC1_isEIMactive(void)
4055  bool res = false;
4056 
4057  if (ADC1_EIM_Active_Sts() == (uint8)1)
4058  {
4059  res = true;
4060  }
4061 
4062  return (res);
4063 }
4064 
4065 INLINE bool ADC1_isESMactive(void)
4067  bool res = false;
4068 
4069  if (ADC1_ESM_Active_Sts() == (uint8)1)
4070  {
4071  res = true;
4072  }
4073 
4074  return (res);
4075 }
4076 
4078 {
4079  TADC1_ANON_U res;
4081  return (res.adc1_anon);
4082 }
4083 
4084 #endif /* ADC1_H */
ADC1_IE_CH4_IE_Pos
#define ADC1_IE_CH4_IE_Pos
Definition: tle986x.h:6143
ADC1_RES_OUT1_WFR1_Pos
#define ADC1_RES_OUT1_WFR1_Pos
Definition: tle986x.h:6188
ADC1_CTRL_STS_SOC_Pos
#define ADC1_CTRL_STS_SOC_Pos
Definition: tle986x.h:6076
ADC1_Ch3_Overwrite_Set
INLINE void ADC1_Ch3_Overwrite_Set(void)
Sets the ADC1 channel 3 result register to "overwrite".
Definition: adc1.h:2877
ADC1_RES_OUT5_WFR5_Pos
#define ADC1_RES_OUT5_WFR5_Pos
Definition: tle986x.h:6224
ADC1_SQ5_8_SQ6_Msk
#define ADC1_SQ5_8_SQ6_Msk
Definition: tle986x.h:6270
ADC1_RES_OUT0_WFR0_Pos
#define ADC1_RES_OUT0_WFR0_Pos
Definition: tle986x.h:6179
ADC1_SQ_FB_CHx_Pos
#define ADC1_SQ_FB_CHx_Pos
Definition: tle986x.h:6274
ADC1_RES_OUT0_OUT_CH0_Msk
#define ADC1_RES_OUT0_OUT_CH0_Msk
Definition: tle986x.h:6182
MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Msk
Definition: tle986x.h:8087
u16_Field_Rd32
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:426
ADC1_GetSwModeResult_mV
INLINE bool ADC1_GetSwModeResult_mV(uint16 *pVar_mV)
Get ADC1 software mode result in Millivolt.
Definition: adc1.h:3993
ADC1_Ch4_WaitForRead_Set
INLINE void ADC1_Ch4_WaitForRead_Set(void)
Sets the ADC1 channel 4 result register to "wait for read".
Definition: adc1.h:2907
ADC1_CHx_ESM_ESM_0_Msk
#define ADC1_CHx_ESM_ESM_0_Msk
Definition: tle986x.h:6070
ADC1_SQ5_8_SQ8_Msk
#define ADC1_SQ5_8_SQ8_Msk
Definition: tle986x.h:6266
ADC1_Ch6_Result_Get
INLINE uint16 ADC1_Ch6_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1572
ADC1_RES_OUT2_OUT_CH2_Pos
#define ADC1_RES_OUT2_OUT_CH2_Pos
Definition: tle986x.h:6199
ADC1_Ch3_Int_Clr
INLINE void ADC1_Ch3_Int_Clr(void)
clears ADC1 Channel 3 Interrupt flag.
Definition: adc1.h:3350
ADC1_Ch2_DataWidth_10bit_Set
INLINE void ADC1_Ch2_DataWidth_10bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 10-bit.
Definition: adc1.h:2226
ADC1_GLOBCTR_ANON_Msk
#define ADC1_GLOBCTR_ANON_Msk
Definition: tle986x.h:6099
ADC1_Sequence3_Set
INLINE void ADC1_Sequence3_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 3, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1270
ADC1_P22_Result_Get
INLINE uint16 ADC1_P22_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1693
ADC1_IE_ESM_IE_Pos
#define ADC1_IE_ESM_IE_Pos
Definition: tle986x.h:6133
ADC1_Ch1_Int_En
INLINE void ADC1_Ch1_Int_En(void)
enables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3527
ADC1_ICLR_CH6_ICLR_Pos
#define ADC1_ICLR_CH6_ICLR_Pos
Definition: tle986x.h:6118
ADC1_EIM_Int_En
INLINE void ADC1_EIM_Int_En(void)
enables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3798
ADC1_STC_0_3_ch2_Msk
#define ADC1_STC_0_3_ch2_Msk
Definition: tle986x.h:6288
ADC1_Ch5_Int_En
INLINE void ADC1_Ch5_Int_En(void)
enables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3707
MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Msk
Definition: tle986x.h:8091
ADC1_ICLR_CH4_ICLR_Msk
#define ADC1_ICLR_CH4_ICLR_Msk
Definition: tle986x.h:6123
ADC1_1_Meas
Definition: adc1.h:258
ADC1_Ch1_DataWidth_10bit_Set
INLINE void ADC1_Ch1_DataWidth_10bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 10-bit.
Definition: adc1.h:2174
ADC1_CSA_Result_Get
INLINE uint16 ADC1_CSA_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1663
ADC1_Ch5_Int_Clr
INLINE void ADC1_Ch5_Int_Clr(void)
clears ADC1 Channel 5 Interrupt flag.
Definition: adc1.h:3393
ADC1_Ch6_DataWidth_8bit_Set
INLINE void ADC1_Ch6_DataWidth_8bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 8-bit.
Definition: adc1.h:2408
ADC1_DWSEL_ch3_Msk
#define ADC1_DWSEL_ch3_Msk
Definition: tle986x.h:6090
TADC1_TRIGG_SEL
TADC1_TRIGG_SEL
This enum lists the options for the trigger select for EIM and ESM.
Definition: adc1.h:239
ADC1_RES_OUT6_OUT_CH6_Msk
#define ADC1_RES_OUT6_OUT_CH6_Msk
Definition: tle986x.h:6236
ADC1_DWSEL_ch3_Pos
#define ADC1_DWSEL_ch3_Pos
Definition: tle986x.h:6089
ADC1_Ch1_DataWidth_8bit_Set
INLINE void ADC1_Ch1_DataWidth_8bit_Set(void)
Sets the ADC1 channel 1 conversion data width to 8-bit.
Definition: adc1.h:2148
types.h
General type declarations.
ADC1_Ch2_Int_Clr
INLINE void ADC1_Ch2_Int_Clr(void)
clears ADC1 Channel 2 Interrupt flag.
Definition: adc1.h:3328
MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos
#define MF_VMON_SEN_CTRL_VMON_SEN_PD_N_Pos
Definition: tle986x.h:8090
ADC1_CTRL_STS_PD_N_Msk
#define ADC1_CTRL_STS_PD_N_Msk
Definition: tle986x.h:6079
ADC1_Sequence2_Set
INLINE void ADC1_Sequence2_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 2, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1247
ADC1_CHx_EIM_CHx_Msk
#define ADC1_CHx_EIM_CHx_Msk
Definition: tle986x.h:6065
ADC1_EIM_Int_Clr
INLINE void ADC1_EIM_Int_Clr(void)
clears Exceptional Interrupt Measurement (EIM) flag.
Definition: adc1.h:3438
ADC1_DWSEL_ch1_Msk
#define ADC1_DWSEL_ch1_Msk
Definition: tle986x.h:6094
ADC1_Ch4_DataWidth_10bit_Set
INLINE void ADC1_Ch4_DataWidth_10bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 10-bit.
Definition: adc1.h:2330
ADC1_SQ_FB_EIM_ACTIVE_Msk
#define ADC1_SQ_FB_EIM_ACTIVE_Msk
Definition: tle986x.h:6281
ADC1_SQ1_4_SQ3_Msk
#define ADC1_SQ1_4_SQ3_Msk
Definition: tle986x.h:6259
ADC1_Busy
INLINE bool ADC1_Busy(void)
Reads the overall status of the ADC1.
Definition: adc1.h:4000
ADC1_STC_4_7_ch6_Msk
#define ADC1_STC_4_7_ch6_Msk
Definition: tle986x.h:6297
ADC1_Ch2_Result_Get
INLINE uint16 ADC1_Ch2_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:1452
ADC1_ESM_Trigger_Select
INLINE void ADC1_ESM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Set ADC1 ESM Trigger Selection.
Definition: adc1.h:4024
ADC1_ESM_Int_Dis
INLINE void ADC1_ESM_Int_Dis(void)
disables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3867
ADC1_Current_Active_Channel_Sts
INLINE uint8 ADC1_Current_Active_Channel_Sts(void)
Reads the currently active channel.
Definition: adc1.h:1179
ADC1_ICLR_CH3_ICLR_Msk
#define ADC1_ICLR_CH3_ICLR_Msk
Definition: tle986x.h:6125
ADC1_RES_OUT6_WFR6_Msk
#define ADC1_RES_OUT6_WFR6_Msk
Definition: tle986x.h:6234
ADC1_Software_Mode_Sel
INLINE void ADC1_Software_Mode_Sel(void)
ADC1 selects the Software Mode, measurements are performed on user request.
Definition: adc1.h:957
TADC1_ANON_U::adc1_anon
TADC1_ANON adc1_anon
Definition: adc1.h:231
ADC1_Ch1_ResultValid_Get
INLINE uint8 ADC1_Ch1_ResultValid_Get(void)
Reads the valid flag for the channel 1 (CSA) result.
Definition: adc1.h:1877
ADC1_SQ5_8_SQ7_Msk
#define ADC1_SQ5_8_SQ7_Msk
Definition: tle986x.h:6268
ADC1_Ch2_Int_Dis
INLINE void ADC1_Ch2_Int_Dis(void)
disables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3595
ADC1_RES_OUT_EIM_VF8_Msk
#define ADC1_RES_OUT_EIM_VF8_Msk
Definition: tle986x.h:6250
ADC1_VDH_Attenuator_Zlow_Set
INLINE void ADC1_VDH_Attenuator_Zlow_Set(void)
Disables the output attenuator for VDH.
Definition: adc1.h:3262
ADC1_Ch0_Overwrite_Set
INLINE void ADC1_Ch0_Overwrite_Set(void)
Sets the ADC1 channel 0 result register to "overwrite".
Definition: adc1.h:2697
ADC1_RES_OUT2_VF2_Pos
#define ADC1_RES_OUT2_VF2_Pos
Definition: tle986x.h:6195
ADC1_Ch4_Result_Get
INLINE uint16 ADC1_Ch4_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1512
ADC1_DIVA_Set
INLINE void ADC1_DIVA_Set(uint32 a)
ADC1 analog clock divider. .
Definition: adc1.h:894
ADC1_RES_OUT1_WFR1_Msk
#define ADC1_RES_OUT1_WFR1_Msk
Definition: tle986x.h:6189
ADC1_SQ1_4_SQ2_Msk
#define ADC1_SQ1_4_SQ2_Msk
Definition: tle986x.h:6261
ADC1_4_Meas
Definition: adc1.h:260
ADC1_Ch6_Int_En
INLINE void ADC1_Ch6_Int_En(void)
enables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3752
ADC1_DWSEL_ch5_Msk
#define ADC1_DWSEL_ch5_Msk
Definition: tle986x.h:6086
ADC1_SQ5_8_SQ5_Msk
#define ADC1_SQ5_8_SQ5_Msk
Definition: tle986x.h:6272
ADC1_ICLR_CH1_ICLR_Pos
#define ADC1_ICLR_CH1_ICLR_Pos
Definition: tle986x.h:6128
ADC1_Ch1_Int_Clr
INLINE void ADC1_Ch1_Int_Clr(void)
clears ADC1 Channel 1 Interrupt flag.
Definition: adc1.h:3306
ADC1_RES_OUT0_WFR0_Msk
#define ADC1_RES_OUT0_WFR0_Msk
Definition: tle986x.h:6180
ADC1_128_Meas
Definition: adc1.h:265
ADC1_STC_0_3_ch1_Msk
#define ADC1_STC_0_3_ch1_Msk
Definition: tle986x.h:6290
ADC1_DWSEL_ch0_Msk
#define ADC1_DWSEL_ch0_Msk
Definition: tle986x.h:6096
ADC1_ICLR_EIM_ICLR_Pos
#define ADC1_ICLR_EIM_ICLR_Pos
Definition: tle986x.h:6114
ADC1_IE_CH1_IE_Pos
#define ADC1_IE_CH1_IE_Pos
Definition: tle986x.h:6149
ADC1_GetChResult_mV
bool ADC1_GetChResult_mV(uint16 *pVar_mV, uint8 channel)
Get the value of the ADC1 Result Register of the selected ADC1 channel in Millivolt (mV) and returns ...
ADC1_Ch0_DataWidth_10bit_Set
INLINE void ADC1_Ch0_DataWidth_10bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 10-bit.
Definition: adc1.h:2122
ADC1_EOC_Sts
INLINE uint8 ADC1_EOC_Sts(void)
Reads the End-of-Conversion status.
Definition: adc1.h:984
ADC1_Ch4_DataWidth_8bit_Set
INLINE void ADC1_Ch4_DataWidth_8bit_Set(void)
Sets the ADC1 channel 4 conversion data width to 8-bit.
Definition: adc1.h:2304
ADC1_IE_CH2_IE_Pos
#define ADC1_IE_CH2_IE_Pos
Definition: tle986x.h:6147
TADC1_ANON_U
Definition: adc1.h:228
ADC1_SQ1_4_SQ4_Pos
#define ADC1_SQ1_4_SQ4_Pos
Definition: tle986x.h:6256
ADC1_CHx_ESM_TRIG_SEL_Msk
#define ADC1_CHx_ESM_TRIG_SEL_Msk
Definition: tle986x.h:6068
ADC1_Power_Off
INLINE void ADC1_Power_Off(void)
Disables the ADC1 module.
Definition: adc1.h:837
ADC1_VDH_Result_Get
INLINE uint16 ADC1_VDH_Result_Get(void)
Reads the converted value from the channel 6 (VDH) result register.
Definition: adc1.h:1813
ADC1_IE_CH6_IE_Msk
#define ADC1_IE_CH6_IE_Msk
Definition: tle986x.h:6140
ADC1_RES_OUT2_VF2_Msk
#define ADC1_RES_OUT2_VF2_Msk
Definition: tle986x.h:6196
ADC1_ESM_Channel_Set
INLINE void ADC1_ESM_Channel_Set(uint32 mask_ch)
Set channels in ESM sequence.
Definition: adc1.h:3119
sfr_access.h
SFR low level access library.
ADC1_RES_OUT4_VF4_Msk
#define ADC1_RES_OUT4_VF4_Msk
Definition: tle986x.h:6214
ADC1_DWSEL_ch4_Msk
#define ADC1_DWSEL_ch4_Msk
Definition: tle986x.h:6088
ADC1_RES_OUT3_VF3_Pos
#define ADC1_RES_OUT3_VF3_Pos
Definition: tle986x.h:6204
ADC1_SQ5_8_SQ8_Pos
#define ADC1_SQ5_8_SQ8_Pos
Definition: tle986x.h:6265
ADC1_GLOBSTR_BUSY_Pos
#define ADC1_GLOBSTR_BUSY_Pos
Definition: tle986x.h:6109
ADC1_Sample_Sts
INLINE uint8 ADC1_Sample_Sts(void)
Reads the sample status of a ongoing measurement.
Definition: adc1.h:1047
ADC1_CTRL_STS_IN_MUX_SEL_Msk
#define ADC1_CTRL_STS_IN_MUX_SEL_Msk
Definition: tle986x.h:6073
ADC1_DWSEL_ch6_Msk
#define ADC1_DWSEL_ch6_Msk
Definition: tle986x.h:6084
INLINE
#define INLINE
Definition: types.h:134
ADC1_Sequence0_Set
INLINE void ADC1_Sequence0_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 0, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1201
ADC1_STC_0_3_ch3_Pos
#define ADC1_STC_0_3_ch3_Pos
Definition: tle986x.h:6285
ADC1_EIM_Result_Get
INLINE uint16 ADC1_EIM_Result_Get(void)
Reads the converted value from the EIM result register.
Definition: adc1.h:1603
ADC1_CHx_EIM_TRIG_SEL_Msk
#define ADC1_CHx_EIM_TRIG_SEL_Msk
Definition: tle986x.h:6061
ADC1_Trigg_Timer21
Definition: adc1.h:246
ADC1_GLOBCTR_ANON_Pos
#define ADC1_GLOBCTR_ANON_Pos
Definition: tle986x.h:6098
Field_Mod32
INLINE void Field_Mod32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:356
ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Msk
Definition: tle986x.h:6254
ADC1_EIM_Channel_Set
INLINE void ADC1_EIM_Channel_Set(uint32 ch)
Set EIM channel for measurement.
Definition: adc1.h:3088
ADC1_SetEIMChannel
INLINE void ADC1_SetEIMChannel(uint8 channel)
Set(Change) ADC1 EIM channel.
Definition: adc1.h:3952
ADC1_ICLR_ESM_ICLR_Msk
#define ADC1_ICLR_ESM_ICLR_Msk
Definition: tle986x.h:6113
ADC1_SQ1_4_SQ3_Pos
#define ADC1_SQ1_4_SQ3_Pos
Definition: tle986x.h:6258
ADC1_STC_0_3_ch0_Msk
#define ADC1_STC_0_3_ch0_Msk
Definition: tle986x.h:6292
ADC1_P20_Result_Get
INLINE uint16 ADC1_P20_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1633
ADC1_Trigg_GPT12E_T6
Definition: adc1.h:243
ADC1_RES_OUT4_WFR4_Pos
#define ADC1_RES_OUT4_WFR4_Pos
Definition: tle986x.h:6215
ADC1_SQ5_8_SQ5_Pos
#define ADC1_SQ5_8_SQ5_Pos
Definition: tle986x.h:6271
ADC1_Ch1_Sample_Time_Set
INLINE void ADC1_Ch1_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 1 number of sampling ticks.
Definition: adc1.h:2492
u1_Field_Rd32
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:401
uint16
unsigned short uint16
16 bit unsigned value
Definition: types.h:140
ADC1_Ch2_ResultValid_Get
INLINE uint8 ADC1_Ch2_ResultValid_Get(void)
Reads the valid flag for the channel 2 (P2.2) result.
Definition: adc1.h:1909
ADC1_IE_CH1_IE_Msk
#define ADC1_IE_CH1_IE_Msk
Definition: tle986x.h:6150
ADC1_ICLR_ESM_ICLR_Pos
#define ADC1_ICLR_ESM_ICLR_Pos
Definition: tle986x.h:6112
ADC1
#define ADC1
Definition: tle986x.h:5990
ADC1_RES_OUT2_OUT_CH2_Msk
#define ADC1_RES_OUT2_OUT_CH2_Msk
Definition: tle986x.h:6200
ADC1_Ch6_ResultValid_Get
INLINE uint8 ADC1_Ch6_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2037
ADC1_16_Meas
Definition: adc1.h:262
ADC1_32_Meas
Definition: adc1.h:263
ADC1_Ch5_DataWidth_8bit_Set
INLINE void ADC1_Ch5_DataWidth_8bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 8-bit.
Definition: adc1.h:2356
ADC1_SQ_FB_EIM_ACTIVE_Pos
#define ADC1_SQ_FB_EIM_ACTIVE_Pos
Definition: tle986x.h:6280
ADC1_Sequence5_Set
INLINE void ADC1_Sequence5_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 5, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1316
ADC1_VDH_Attenuator_Zhigh_Set
INLINE void ADC1_VDH_Attenuator_Zhigh_Set(void)
Enables the output attenuator for VDH.
Definition: adc1.h:3226
VAREF_Enable
bool VAREF_Enable(void)
Re-enables the internal VAREF LDO in case it was shutdown due to a previous failure.
ADC1_SW_Ch_Sel
INLINE void ADC1_SW_Ch_Sel(uint32 a)
Selects a channel for the software conversion.
Definition: adc1.h:874
u32_Field_Rd32
INLINE uint32 u32_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 32-bit field of a 32-bit register.
Definition: sfr_access.h:431
ADC1_Busy_Sts
INLINE uint8 ADC1_Busy_Sts(void)
Reads the overall status of the ADC1.
Definition: adc1.h:1079
ADC1_RES_OUT1_VF1_Pos
#define ADC1_RES_OUT1_VF1_Pos
Definition: tle986x.h:6186
ADC1_Ch3_Sample_Time_Set
INLINE void ADC1_Ch3_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 3 number of sampling ticks.
Definition: adc1.h:2550
ADC1_Ch6_DataWidth_10bit_Set
INLINE void ADC1_Ch6_DataWidth_10bit_Set(void)
Sets the ADC1 channel 6 conversion data width to 10-bit.
Definition: adc1.h:2434
ADC1_Current_Active_Sequence_Sts
INLINE uint8 ADC1_Current_Active_Sequence_Sts(void)
Reads the currently active channel in Sequencer Mode.
Definition: adc1.h:1155
ADC1_Ch3_DataWidth_10bit_Set
INLINE void ADC1_Ch3_DataWidth_10bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 10-bit.
Definition: adc1.h:2278
ADC1_8_Meas
Definition: adc1.h:261
ADC1_DWSEL_ch5_Pos
#define ADC1_DWSEL_ch5_Pos
Definition: tle986x.h:6085
ADC1_EIM_Trigger_Select
INLINE void ADC1_EIM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Get ADC1 EIM Trigger Selection.
Definition: adc1.h:4012
ADC1_RES_OUT_EIM_VF8_Pos
#define ADC1_RES_OUT_EIM_VF8_Pos
Definition: tle986x.h:6249
ADC1_isEndOfConversion
INLINE bool ADC1_isEndOfConversion(void)
checks EndOfConversion ready (Software Mode)
Definition: adc1.h:4030
ADC1_GetEIMResult
bool ADC1_GetEIMResult(uint16 *pVar)
Get the 10-bit/8-bit value of the ADC1 EIM Result Register and returns the validity info.
ADC1_RES_OUT4_OUT_CH4_Msk
#define ADC1_RES_OUT4_OUT_CH4_Msk
Definition: tle986x.h:6218
ADC1_Ch2_Overwrite_Set
INLINE void ADC1_Ch2_Overwrite_Set(void)
Sets the ADC1 channel 2 result register to "overwrite".
Definition: adc1.h:2817
ADC1_RES_OUT3_OUT_CH3_Pos
#define ADC1_RES_OUT3_OUT_CH3_Pos
Definition: tle986x.h:6208
ADC1_GLOBSTR_SAMPLE_Pos
#define ADC1_GLOBSTR_SAMPLE_Pos
Definition: tle986x.h:6107
ADC1_CHx_EIM_REP_Pos
#define ADC1_CHx_EIM_REP_Pos
Definition: tle986x.h:6062
ADC1_ANON_F_STANDBY
Definition: adc1.h:224
ADC1_GLOBSTR_SAMPLE_Msk
#define ADC1_GLOBSTR_SAMPLE_Msk
Definition: tle986x.h:6108
ADC1_IE_CH3_IE_Pos
#define ADC1_IE_CH3_IE_Pos
Definition: tle986x.h:6145
ADC1_Trigg_Timer2
Definition: adc1.h:245
MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Msk
Definition: tle986x.h:8089
ADC1_RES_OUT1_OUT_CH1_Msk
#define ADC1_RES_OUT1_OUT_CH1_Msk
Definition: tle986x.h:6191
ADC1_RES_OUT2_WFR2_Pos
#define ADC1_RES_OUT2_WFR2_Pos
Definition: tle986x.h:6197
uint8
unsigned char uint8
8 bit unsigned value
Definition: types.h:139
ADC1_VDH_Attenuator_Off
INLINE void ADC1_VDH_Attenuator_Off(void)
Disables the input attenuator for VDH.
Definition: adc1.h:3190
ADC1_RES_OUT0_VF0_Pos
#define ADC1_RES_OUT0_VF0_Pos
Definition: tle986x.h:6177
ADC1_GetSwModeResult
INLINE bool ADC1_GetSwModeResult(uint16 *pVar)
Get ADC1 latest software mode result.
Definition: adc1.h:3986
ADC1_Ch0_Result_Get
INLINE uint16 ADC1_Ch0_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:1392
ADC1_CHx_ESM_TRIG_SEL_Pos
#define ADC1_CHx_ESM_TRIG_SEL_Pos
Definition: tle986x.h:6067
ADC1_isESMactive
INLINE bool ADC1_isESMactive(void)
checks Exceptional Sequencer Mode active
Definition: adc1.h:4054
ADC1_EIM_ResultValid_Get
INLINE uint8 ADC1_EIM_ResultValid_Get(void)
Reads the valid flag for the channel 6 (VDH) result.
Definition: adc1.h:2070
ADC1_IE_CH5_IE_Msk
#define ADC1_IE_CH5_IE_Msk
Definition: tle986x.h:6142
ADC1_RES_OUT3_OUT_CH3_Msk
#define ADC1_RES_OUT3_OUT_CH3_Msk
Definition: tle986x.h:6209
ADC1_Ch6_Overwrite_Set
INLINE void ADC1_Ch6_Overwrite_Set(void)
Sets the ADC1 channel 6 result register to "overwrite".
Definition: adc1.h:3057
ADC1_RES_OUT4_VF4_Pos
#define ADC1_RES_OUT4_VF4_Pos
Definition: tle986x.h:6213
Field_Wrt32
INLINE void Field_Wrt32(volatile uint32 *reg, uint32 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:341
ADC1_Ch0_Int_Clr
INLINE void ADC1_Ch0_Int_Clr(void)
clears ADC1 Channel 0 Interrupt flag.
Definition: adc1.h:3284
ADC1_VDH_Attenuator_Range_0_20V
#define ADC1_VDH_Attenuator_Range_0_20V
ADC1 VDH Attenuator Selection, 0V..20V.
Definition: adc1.h:118
ADC1_DWSEL_ch1_Pos
#define ADC1_DWSEL_ch1_Pos
Definition: tle986x.h:6093
u8_Field_Rd32
INLINE uint8 u8_Field_Rd32(const volatile uint32 *reg, uint32 pos, uint32 msk)
This function reads a 8-bit field of a 32-bit register.
Definition: sfr_access.h:416
ADC1_Ch4_Int_Dis
INLINE void ADC1_Ch4_Int_Dis(void)
disables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3685
ADC1_Ch4_Overwrite_Set
INLINE void ADC1_Ch4_Overwrite_Set(void)
Sets the ADC1 channel 4 result register to "overwrite".
Definition: adc1.h:2937
ADC1_Sequencer_Mode_Sel
INLINE void ADC1_Sequencer_Mode_Sel(void)
ADC1 selects the Sequencer Mode.
Definition: adc1.h:934
ADC1_DWSEL_ch2_Msk
#define ADC1_DWSEL_ch2_Msk
Definition: tle986x.h:6092
ADC1_IE_EIM_IE_Pos
#define ADC1_IE_EIM_IE_Pos
Definition: tle986x.h:6135
ADC1_STC_4_7_ch5_Pos
#define ADC1_STC_4_7_ch5_Pos
Definition: tle986x.h:6298
ADC1_RES_OUT1_OUT_CH1_Pos
#define ADC1_RES_OUT1_OUT_CH1_Pos
Definition: tle986x.h:6190
ADC1_Ch2_Int_En
INLINE void ADC1_Ch2_Int_En(void)
enables ADC1 Channel 2 Interrupt.
Definition: adc1.h:3572
ADC1_ICLR_CH6_ICLR_Msk
#define ADC1_ICLR_CH6_ICLR_Msk
Definition: tle986x.h:6119
ADC1_ICLR_EIM_ICLR_Msk
#define ADC1_ICLR_EIM_ICLR_Msk
Definition: tle986x.h:6115
MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos
#define MF_VMON_SEN_CTRL_VMON_SEN_SEL_INRANGE_Pos
Definition: tle986x.h:8086
ADC1_GLOBSTR_CHNR_Msk
#define ADC1_GLOBSTR_CHNR_Msk
Definition: tle986x.h:6106
ADC1_Ch3_ResultValid_Get
INLINE uint8 ADC1_Ch3_ResultValid_Get(void)
Reads the valid flag for the channel 3 (P2.3) result.
Definition: adc1.h:1941
ADC1_RES_OUT0_VF0_Msk
#define ADC1_RES_OUT0_VF0_Msk
Definition: tle986x.h:6178
ADC1_ICLR_CH5_ICLR_Pos
#define ADC1_ICLR_CH5_ICLR_Pos
Definition: tle986x.h:6120
ADC1_Ch0_Sample_Time_Set
INLINE void ADC1_Ch0_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 0 number of sampling ticks.
Definition: adc1.h:2463
ADC1_STC_0_3_ch3_Msk
#define ADC1_STC_0_3_ch3_Msk
Definition: tle986x.h:6286
uint32
unsigned int uint32
32 bit unsigned value
Definition: types.h:141
ADC1_ICLR_CH5_ICLR_Msk
#define ADC1_ICLR_CH5_ICLR_Msk
Definition: tle986x.h:6121
TADC1_ANON_U::dword
uint32 dword
Definition: adc1.h:230
ADC1_GLOBSTR_CHNR_Pos
#define ADC1_GLOBSTR_CHNR_Pos
Definition: tle986x.h:6105
ADC1_P23_Result_Get
INLINE uint16 ADC1_P23_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1723
ADC1_Ch0_Int_Dis
INLINE void ADC1_Ch0_Int_Dis(void)
disables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3505
ADC1_ICLR_CH0_ICLR_Msk
#define ADC1_ICLR_CH0_ICLR_Msk
Definition: tle986x.h:6131
ADC1_RES_OUT5_OUT_CH5_Msk
#define ADC1_RES_OUT5_OUT_CH5_Msk
Definition: tle986x.h:6227
ADC1_RES_OUT3_WFR3_Msk
#define ADC1_RES_OUT3_WFR3_Msk
Definition: tle986x.h:6207
ADC1_Ch2_DataWidth_8bit_Set
INLINE void ADC1_Ch2_DataWidth_8bit_Set(void)
Sets the ADC1 channel 2 conversion data width to 8-bit.
Definition: adc1.h:2200
ADC1_Ch0_Int_En
INLINE void ADC1_Ch0_Int_En(void)
enables ADC1 Channel 0 Interrupt.
Definition: adc1.h:3482
ADC1_STC_4_7_ch6_Pos
#define ADC1_STC_4_7_ch6_Pos
Definition: tle986x.h:6296
ADC1_ESM_Int_Clr
INLINE void ADC1_ESM_Int_Clr(void)
clears Exceptional Sequence Measurement (ESM) flag.
Definition: adc1.h:3460
ADC1_Ch6_Int_Clr
INLINE void ADC1_Ch6_Int_Clr(void)
clears ADC1 Channel 6 Interrupt flag.
Definition: adc1.h:3415
ADC1_Ch2_Sample_Time_Set
INLINE void ADC1_Ch2_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 2 number of sampling ticks.
Definition: adc1.h:2521
ADC1_STC_4_7_ch4_Msk
#define ADC1_STC_4_7_ch4_Msk
Definition: tle986x.h:6301
ADC1_GetChResult
bool ADC1_GetChResult(uint16 *pVar, uint8 channel)
Get the 10-bit/8-bit value of the ADC1 Result Register of the selected ADC1 channel and returns the v...
ADC1_RES_OUT6_VF6_Msk
#define ADC1_RES_OUT6_VF6_Msk
Definition: tle986x.h:6232
ADC1_GetEIMResult_mV
bool ADC1_GetEIMResult_mV(uint16 *pVar_mV)
Get the value of the ADC1 EIM Result Register in Millivolt (mV) and returns the validity info.
MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos
#define MF_VMON_SEN_CTRL_VMON_SEN_HRESO_5V_Pos
Definition: tle986x.h:8088
ADC1_EIM_Repeat_Counter_Set
INLINE void ADC1_EIM_Repeat_Counter_Set(TADC1_EIM_REP_CNT repcnt)
Set ADC1 EIM Repeat Counter.
Definition: adc1.h:4018
ADC1_DWSEL_ch6_Pos
#define ADC1_DWSEL_ch6_Pos
Definition: tle986x.h:6083
ADC1_SQ_FB_SQ_RUN_Msk
#define ADC1_SQ_FB_SQ_RUN_Msk
Definition: tle986x.h:6283
ADC1_RES_OUT6_VF6_Pos
#define ADC1_RES_OUT6_VF6_Pos
Definition: tle986x.h:6231
ADC1_IE_CH0_IE_Pos
#define ADC1_IE_CH0_IE_Pos
Definition: tle986x.h:6151
ADC1_Ch5_Result_Get
INLINE uint16 ADC1_Ch5_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1542
ADC1_Sequence6_Set
INLINE void ADC1_Sequence6_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 6, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1339
ADC1_DWSEL_ch4_Pos
#define ADC1_DWSEL_ch4_Pos
Definition: tle986x.h:6087
ADC1_Ch3_Int_Dis
INLINE void ADC1_Ch3_Int_Dis(void)
disables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3640
ADC1_EIM_Int_Dis
INLINE void ADC1_EIM_Int_Dis(void)
disables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:3822
ADC1_RES_OUT0_OUT_CH0_Pos
#define ADC1_RES_OUT0_OUT_CH0_Pos
Definition: tle986x.h:6181
ADC1_ICLR_CH1_ICLR_Msk
#define ADC1_ICLR_CH1_ICLR_Msk
Definition: tle986x.h:6129
ADC1_SQ_FB_CHx_Msk
#define ADC1_SQ_FB_CHx_Msk
Definition: tle986x.h:6275
ADC1_ANON_Sts
INLINE TADC1_ANON ADC1_ANON_Sts(void)
Reads the Analog Part Switched On Mode status.
Definition: adc1.h:4066
ADC1_ICLR_CH0_ICLR_Pos
#define ADC1_ICLR_CH0_ICLR_Pos
Definition: tle986x.h:6130
ADC1_SQ_FB_SQx_Msk
#define ADC1_SQ_FB_SQx_Msk
Definition: tle986x.h:6277
ADC1_Ch4_ResultValid_Get
INLINE uint8 ADC1_Ch4_ResultValid_Get(void)
Reads the valid flag for the channel 4 (P2.4) result.
Definition: adc1.h:1973
MF
#define MF
Definition: tle986x.h:6000
ADC1_RES_OUT3_VF3_Msk
#define ADC1_RES_OUT3_VF3_Msk
Definition: tle986x.h:6205
ADC1_ICLR_CH2_ICLR_Pos
#define ADC1_ICLR_CH2_ICLR_Pos
Definition: tle986x.h:6126
ADC1_ESM_Active_Sts
INLINE uint8 ADC1_ESM_Active_Sts(void)
Reads the active status of the Exceptional Sequencer Measurement (ESM).
Definition: adc1.h:1131
ADC1_ANON_Set
INLINE void ADC1_ANON_Set(uint32 a)
ADC1 set the Analog Module Mode.
Definition: adc1.h:913
ADC1_Ch5_Overwrite_Set
INLINE void ADC1_Ch5_Overwrite_Set(void)
Sets the ADC1 channel 5 result register to "overwrite".
Definition: adc1.h:2997
ADC1_GLOBCTR_DIVA_Pos
#define ADC1_GLOBCTR_DIVA_Pos
Definition: tle986x.h:6100
ADC1_SetSocSwMode
INLINE void ADC1_SetSocSwMode(uint8 Ch)
Starts ADC1 software mode conversion.
Definition: adc1.h:3968
ADC1_Ch5_DataWidth_10bit_Set
INLINE void ADC1_Ch5_DataWidth_10bit_Set(void)
Sets the ADC1 channel 5 conversion data width to 10-bit.
Definition: adc1.h:2382
ADC1_SQ5_8_SQ7_Pos
#define ADC1_SQ5_8_SQ7_Pos
Definition: tle986x.h:6267
ADC1_Power_On
INLINE void ADC1_Power_On(void)
Enables the ADC1 module.
Definition: adc1.h:820
tle986x.h
CMSIS register HeaderFile.
ADC1_IE_CH4_IE_Msk
#define ADC1_IE_CH4_IE_Msk
Definition: tle986x.h:6144
ADC1_VDH_Attenuator_Range_0_30V_Set
INLINE void ADC1_VDH_Attenuator_Range_0_30V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 30V.
Definition: adc1.h:3892
ADC1_Ch0_ResultValid_Get
INLINE uint8 ADC1_Ch0_ResultValid_Get(void)
Reads the valid flag for the channel 0 (P2.0) result.
Definition: adc1.h:1845
ADC1_RES_OUT5_VF5_Pos
#define ADC1_RES_OUT5_VF5_Pos
Definition: tle986x.h:6222
TADC1_ANON
TADC1_ANON
This enum lists the options for the Analog Module.
Definition: adc1.h:220
ADC1_STC_0_3_ch0_Pos
#define ADC1_STC_0_3_ch0_Pos
Definition: tle986x.h:6291
ADC1_Trigg_CCU6_Ch3
Definition: adc1.h:242
ADC1_Trigg_None
Definition: adc1.h:241
ADC1_Ch3_Int_En
INLINE void ADC1_Ch3_Int_En(void)
enables ADC1 Channel 3 Interrupt.
Definition: adc1.h:3617
ADC1_SQ_FB_ESM_ACTIVE_Pos
#define ADC1_SQ_FB_ESM_ACTIVE_Pos
Definition: tle986x.h:6278
ADC1_Ch5_Int_Dis
INLINE void ADC1_Ch5_Int_Dis(void)
disables ADC1 Channel 5 Interrupt.
Definition: adc1.h:3730
ADC1_ICLR_CH2_ICLR_Msk
#define ADC1_ICLR_CH2_ICLR_Msk
Definition: tle986x.h:6127
ADC1_P25_Result_Get
INLINE uint16 ADC1_P25_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:1783
ADC1_Init
void ADC1_Init(void)
Initializes the ADC1 based on the IFXConfigWizard configuration.
ADC1_Ch1_Result_Get
INLINE uint16 ADC1_Ch1_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:1422
ADC1_VDH_Attenuator_Range_0_30V
#define ADC1_VDH_Attenuator_Range_0_30V
ADC1 VDH Attenuator Selection, 0V..30V.
Definition: adc1.h:116
ADC1_isEIMactive
INLINE bool ADC1_isEIMactive(void)
checks Exceptional Interrupt Mode active
Definition: adc1.h:4042
ADC1_P24_Result_Get
INLINE uint16 ADC1_P24_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:1753
ADC1_GLOBSTR_ANON_ST_Msk
#define ADC1_GLOBSTR_ANON_ST_Msk
Definition: tle986x.h:6104
ADC1_DWSEL_ch0_Pos
#define ADC1_DWSEL_ch0_Pos
Definition: tle986x.h:6095
ADC1_RES_OUT4_WFR4_Msk
#define ADC1_RES_OUT4_WFR4_Msk
Definition: tle986x.h:6216
ADC1_Ch6_WaitForRead_Set
INLINE void ADC1_Ch6_WaitForRead_Set(void)
Sets the ADC1 channel 6 result register to "wait for read".
Definition: adc1.h:3027
ADC1_SQ1_4_SQ1_Pos
#define ADC1_SQ1_4_SQ1_Pos
Definition: tle986x.h:6262
ADC1_Ch6_Sample_Time_Set
INLINE void ADC1_Ch6_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 6 number of sampling ticks.
Definition: adc1.h:2637
ADC1_SQ1_4_SQ4_Msk
#define ADC1_SQ1_4_SQ4_Msk
Definition: tle986x.h:6257
ADC1_Ch3_Result_Get
INLINE uint16 ADC1_Ch3_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:1482
ADC1_RES_OUT4_OUT_CH4_Pos
#define ADC1_RES_OUT4_OUT_CH4_Pos
Definition: tle986x.h:6217
ADC1_RES_OUT1_VF1_Msk
#define ADC1_RES_OUT1_VF1_Msk
Definition: tle986x.h:6187
ADC1_SQ_FB_ESM_ACTIVE_Msk
#define ADC1_SQ_FB_ESM_ACTIVE_Msk
Definition: tle986x.h:6279
TADC1_EIM_REP_CNT
TADC1_EIM_REP_CNT
This enum lists the options for the EIM repeat count setting.
Definition: adc1.h:256
ADC1_VDH_Attenuator_Range_Get
INLINE uint8 ADC1_VDH_Attenuator_Range_Get(void)
Reads the VDH Monitoring Input Attenuator Input Range Configuration.
Definition: adc1.h:3945
ADC1_CHx_EIM_TRIG_SEL_Pos
#define ADC1_CHx_EIM_TRIG_SEL_Pos
Definition: tle986x.h:6060
ADC1_SetMode
INLINE void ADC1_SetMode(uint8 mode)
Start ADC1 conversion mode selection.
Definition: adc1.h:3962
ADC1_Sequence1_Set
INLINE void ADC1_Sequence1_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 1, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1224
ADC1_RES_OUT3_WFR3_Pos
#define ADC1_RES_OUT3_WFR3_Pos
Definition: tle986x.h:6206
ADC1_SQ_FB_SQx_Pos
#define ADC1_SQ_FB_SQx_Pos
Definition: tle986x.h:6276
ADC1_ANON_NORMAL
Definition: adc1.h:225
ADC1_STC_0_3_ch2_Pos
#define ADC1_STC_0_3_ch2_Pos
Definition: tle986x.h:6287
ADC1_ANON_OFF
Definition: adc1.h:222
ADC1_64_Meas
Definition: adc1.h:264
ADC1_IE_CH6_IE_Pos
#define ADC1_IE_CH6_IE_Pos
Definition: tle986x.h:6139
ADC1_SQ5_8_SQ6_Pos
#define ADC1_SQ5_8_SQ6_Pos
Definition: tle986x.h:6269
ADC1_Ch1_Overwrite_Set
INLINE void ADC1_Ch1_Overwrite_Set(void)
Sets the ADC1 channel 1 result register to "overwrite".
Definition: adc1.h:2757
ADC1_Trigg_Timer3
Definition: adc1.h:247
ADC1_GLOBSTR_BUSY_Msk
#define ADC1_GLOBSTR_BUSY_Msk
Definition: tle986x.h:6110
ADC1_STC_4_7_ch4_Pos
#define ADC1_STC_4_7_ch4_Pos
Definition: tle986x.h:6300
ADC1_VDH_Attenuator_On
INLINE void ADC1_VDH_Attenuator_On(void)
Enables the input attenuator for VDH.
Definition: adc1.h:3155
ADC1_SetSwMode_Channel
INLINE void ADC1_SetSwMode_Channel(uint8 channel)
Selects a channel for the software conversion.
Definition: adc1.h:3957
ADC1_Ch6_Int_Dis
INLINE void ADC1_Ch6_Int_Dis(void)
disables ADC1 Channel 6 Interrupt.
Definition: adc1.h:3775
ADC1_EIM_Active_Sts
INLINE uint8 ADC1_EIM_Active_Sts(void)
Reads the active status of the Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:1105
ADC1_STC_0_3_ch1_Pos
#define ADC1_STC_0_3_ch1_Pos
Definition: tle986x.h:6289
ADC1_Ch5_Sample_Time_Set
INLINE void ADC1_Ch5_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 5 number of sampling ticks.
Definition: adc1.h:2608
ADC1_ANON_S_STANDBY
Definition: adc1.h:223
ADC1_CHx_EIM_REP_Msk
#define ADC1_CHx_EIM_REP_Msk
Definition: tle986x.h:6063
ADC1_IE_CH0_IE_Msk
#define ADC1_IE_CH0_IE_Msk
Definition: tle986x.h:6152
ADC1_ICLR_CH4_ICLR_Pos
#define ADC1_ICLR_CH4_ICLR_Pos
Definition: tle986x.h:6122
ADC1_RES_OUT6_OUT_CH6_Pos
#define ADC1_RES_OUT6_OUT_CH6_Pos
Definition: tle986x.h:6235
ADC1_CTRL_STS_EOC_Msk
#define ADC1_CTRL_STS_EOC_Msk
Definition: tle986x.h:6075
ADC1_Trigg_GPT12E_T3
Definition: adc1.h:244
ADC1_Sequence7_Set
INLINE void ADC1_Sequence7_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 7, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1362
ADC1_GetEocSwMode
INLINE bool ADC1_GetEocSwMode(void)
Get ADC1 end of conversion status.
Definition: adc1.h:3974
ADC1_ICLR_CH3_ICLR_Pos
#define ADC1_ICLR_CH3_ICLR_Pos
Definition: tle986x.h:6124
ADC1_RES_OUT5_WFR5_Msk
#define ADC1_RES_OUT5_WFR5_Msk
Definition: tle986x.h:6225
ADC1_SOC_Set
INLINE void ADC1_SOC_Set(void)
ADC1 Start of Conversion, for Software mode only.
Definition: adc1.h:854
ADC1_IE_CH2_IE_Msk
#define ADC1_IE_CH2_IE_Msk
Definition: tle986x.h:6148
ADC1_CHx_EIM_CHx_Pos
#define ADC1_CHx_EIM_CHx_Pos
Definition: tle986x.h:6064
ADC1_Ch0_WaitForRead_Set
INLINE void ADC1_Ch0_WaitForRead_Set(void)
Sets the ADC1 channel 0 result register to "wait for read".
Definition: adc1.h:2667
ADC1_CHx_ESM_ESM_0_Pos
#define ADC1_CHx_ESM_ESM_0_Pos
Definition: tle986x.h:6069
ADC1_ESM_Int_En
INLINE void ADC1_ESM_Int_En(void)
enables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:3844
ADC1_Ch3_WaitForRead_Set
INLINE void ADC1_Ch3_WaitForRead_Set(void)
Sets the ADC1 channel 3 result register to "wait for read".
Definition: adc1.h:2847
ADC1_RES_OUT5_OUT_CH5_Pos
#define ADC1_RES_OUT5_OUT_CH5_Pos
Definition: tle986x.h:6226
ADC1_Ch3_DataWidth_8bit_Set
INLINE void ADC1_Ch3_DataWidth_8bit_Set(void)
Sets the ADC1 channel 3 conversion data width to 8-bit.
Definition: adc1.h:2252
ADC1_Ch1_Int_Dis
INLINE void ADC1_Ch1_Int_Dis(void)
disables ADC1 Channel 1 Interrupt.
Definition: adc1.h:3550
ADC1_STC_4_7_ch5_Msk
#define ADC1_STC_4_7_ch5_Msk
Definition: tle986x.h:6299
ADC1_CTRL_STS_PD_N_Pos
#define ADC1_CTRL_STS_PD_N_Pos
Definition: tle986x.h:6078
ADC1_Ch5_ResultValid_Get
INLINE uint8 ADC1_Ch5_ResultValid_Get(void)
Reads the valid flag for the channel 5 (P2.5) result.
Definition: adc1.h:2005
ADC1_Ch0_DataWidth_8bit_Set
INLINE void ADC1_Ch0_DataWidth_8bit_Set(void)
Sets the ADC1 channel 0 conversion data width to 8-bit.
Definition: adc1.h:2096
ADC1_SQ1_4_SQ1_Msk
#define ADC1_SQ1_4_SQ1_Msk
Definition: tle986x.h:6263
ADC1_Ch2_WaitForRead_Set
INLINE void ADC1_Ch2_WaitForRead_Set(void)
Sets the ADC1 channel 2 result register to "wait for read".
Definition: adc1.h:2787
ADC1_IE_ESM_IE_Msk
#define ADC1_IE_ESM_IE_Msk
Definition: tle986x.h:6134
ADC1_IE_CH3_IE_Msk
#define ADC1_IE_CH3_IE_Msk
Definition: tle986x.h:6146
ADC1_VDH_Attenuator_Range_0_20V_Set
INLINE void ADC1_VDH_Attenuator_Range_0_20V_Set(void)
sets the VDH Monitoring Input Attenuator Input Range to 0 - 22V.
Definition: adc1.h:3916
ADC1_RES_OUT5_VF5_Msk
#define ADC1_RES_OUT5_VF5_Msk
Definition: tle986x.h:6223
ADC1_Sequence4_Set
INLINE void ADC1_Sequence4_Set(uint32 mask_ch)
Defines the channels to be measured in Sequence 4, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:1293
ADC1_RES_OUT6_WFR6_Pos
#define ADC1_RES_OUT6_WFR6_Pos
Definition: tle986x.h:6233
ADC1_CTRL_STS_EOC_Pos
#define ADC1_CTRL_STS_EOC_Pos
Definition: tle986x.h:6074
ADC1_GLOBCTR_DIVA_Msk
#define ADC1_GLOBCTR_DIVA_Msk
Definition: tle986x.h:6101
ADC1_IE_EIM_IE_Msk
#define ADC1_IE_EIM_IE_Msk
Definition: tle986x.h:6136
ADC1_GLOBSTR_ANON_ST_Pos
#define ADC1_GLOBSTR_ANON_ST_Pos
Definition: tle986x.h:6103
ADC1_DWSEL_ch2_Pos
#define ADC1_DWSEL_ch2_Pos
Definition: tle986x.h:6091
ADC1_Current_Ch_Sts
INLINE uint8 ADC1_Current_Ch_Sts(void)
Reads the channel for currently ongoing conversion, if no conversion is ongoing, then it returns the ...
Definition: adc1.h:1014
ADC1_Ch4_Sample_Time_Set
INLINE void ADC1_Ch4_Sample_Time_Set(uint32 stc)
Sets the ADC1 channel 4 number of sampling ticks.
Definition: adc1.h:2579
ADC1_IE_CH5_IE_Pos
#define ADC1_IE_CH5_IE_Pos
Definition: tle986x.h:6141
ADC1_Ch1_WaitForRead_Set
INLINE void ADC1_Ch1_WaitForRead_Set(void)
Sets ADC1 channel 1 the result register to "wait for read".
Definition: adc1.h:2727
ADC1_CTRL_STS_SOC_Msk
#define ADC1_CTRL_STS_SOC_Msk
Definition: tle986x.h:6077
ADC1_RES_OUT2_WFR2_Msk
#define ADC1_RES_OUT2_WFR2_Msk
Definition: tle986x.h:6198
ADC1_Ch4_Int_En
INLINE void ADC1_Ch4_Int_En(void)
enables ADC1 Channel 4 Interrupt.
Definition: adc1.h:3662
ADC1_Ch5_WaitForRead_Set
INLINE void ADC1_Ch5_WaitForRead_Set(void)
Sets the ADC1 channel 5 result register to "wait for read".
Definition: adc1.h:2967
ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos
#define ADC1_RES_OUT_EIM_OUT_CH_EIM_Pos
Definition: tle986x.h:6253
ADC1_SQ1_4_SQ2_Pos
#define ADC1_SQ1_4_SQ2_Pos
Definition: tle986x.h:6260
ADC1_Ch4_Int_Clr
INLINE void ADC1_Ch4_Int_Clr(void)
clears ADC1 Channel 4 Interrupt flag.
Definition: adc1.h:3372
ADC1_SQ_FB_SQ_RUN_Pos
#define ADC1_SQ_FB_SQ_RUN_Pos
Definition: tle986x.h:6282
ADC1_CTRL_STS_IN_MUX_SEL_Pos
#define ADC1_CTRL_STS_IN_MUX_SEL_Pos
Definition: tle986x.h:6072
ADC1_2_Meas
Definition: adc1.h:259