TLE986x Device Family SDK
Macros | Enumerations
Configuration_of_CMSIS

Detailed Description

Collaboration diagram for Configuration_of_CMSIS:

Macros

#define __CM3_REV   0x0000U
 
#define __NVIC_PRIO_BITS   4
 
#define __Vendor_SysTickConfig   0
 
#define __MPU_PRESENT   0
 
#define __FPU_PRESENT   0
 

Enumerations

enum  IRQn_Type {
  Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, GPT1_Int = 0, GPT2_Int = 1,
  ADC2_Tmr3_Int = 2, ADC1_VREF5_Int = 3, CCU6_SR0_Int = 4, CCU6_SR1_Int = 5,
  CCU6_SR2_Int = 6, CCU6_SR3_Int = 7, SSC1_Int = 8, SSC2_Int = 9,
  UART1_LIN_Tmr2_Int = 10, UART2_Tmr21_EINT2_Int = 11, EXINT0_MON_Int = 12, EXINT1_Int = 13,
  BDRV_CP_Int = 14, DMA_Int = 15
}
 

Macro Definition Documentation

◆ __CM3_REV

#define __CM3_REV   0x0000U

CM3 Core Revision

◆ __FPU_PRESENT

#define __FPU_PRESENT   0

FPU present or not

◆ __MPU_PRESENT

#define __MPU_PRESENT   0

MPU present or not

◆ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS   4

Number of Bits used for Priority Levels

◆ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

Enumeration Type Documentation

◆ IRQn_Type

enum IRQn_Type
Enumerator
Reset_IRQn 

1 Reset Vector, invoked on Power up and warm reset

NonMaskableInt_IRQn 

2 Non maskable Interrupt, cannot be stopped or preempted

HardFault_IRQn 

3 Hard Fault, all classes of Fault

MemoryManagement_IRQn 

4 Memory Management, MPU mismatch, including Access Violation and No Match

BusFault_IRQn 

5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault

UsageFault_IRQn 

6 Usage Fault, i.e. Undef Instruction, Illegal State Transition

SVCall_IRQn 

11 System Service Call via SVC instruction

DebugMonitor_IRQn 

12 Debug Monitor

PendSV_IRQn 

14 Pendable request for system service

SysTick_IRQn 

15 System Tick Timer

GPT1_Int 

Interrupt node 0: GPT1 Block

GPT2_Int 

Interrupt node 1: GPT2 Block

ADC2_Tmr3_Int 

Interrupt node 2: ADC2, Timer3, BEMF

ADC1_VREF5_Int 

Interrupt node 3: ADC1, VREF5V

CCU6_SR0_Int 

Interrupt node 4: CCU6 node0

CCU6_SR1_Int 

Interrupt node 5: CCU6 node1

CCU6_SR2_Int 

Interrupt node 6: CCU6 node2

CCU6_SR3_Int 

Interrupt node 7: CCU6 node3

SSC1_Int 

Interrupt node 8: SSC1

SSC2_Int 

Interrupt node 9: SSC2

UART1_LIN_Tmr2_Int 

Interrupt node10: UART1(ASC,LIN), Timer2

UART2_Tmr21_EINT2_Int 

Interrupt node11: UART2, Timer21, EINT2

EXINT0_MON_Int 

Interrupt node12: EINT0, MON

EXINT1_Int 

Interrupt node13: EINT1

BDRV_CP_Int 

Interrupt node14: BDRV, Charge Pump

DMA_Int 

Interrupt node15: DMA