Infineon MOTIX™ MCU TLE985x Device Family SDK
Functions
isr.h File Reference

Go to the source code of this file.

Detailed Description

Interrupt Service Routines low level access library.

Version
V0.3.1
Date
19. Jul 2023
Note
This file violates [MISRA 2012 Rule 12.2, required], [MISRA 2012 Rule 8.7, advisory]

Functions

void GPT1_IRQHandler (void)
 The GPT1_IRQHandler checks which interrupt caused the call of the node handler 0 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. GPT1_IRQHandler is responsible for: GPT1 T2 INT, GPT1 T3 INT, GPT1 T4 INT. More...
 
void GPT2_IRQHandler (void)
 The GPT2_IRQHandler checks which interrupt caused the call of the node handler 1 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. GPT2_IRQHandler is responsible for: GPT2 T5 INT, GPT2 T6 INT, GPT2 CAPREL INT. More...
 
void ADC2_IRQHandler (void)
 The ADC2_IRQHandler checks which interrupt caused the call of the node handler 2 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC2_IRQHandler is responsible for: ADC2 VBG UP INT, ADC2 VBG LO INT. More...
 
void ADC1_IRQHandler (void)
 The ADC1_IRQHandler checks which interrupt caused the call of the node handler 3 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1_IRQHandler is responsible for: ADC1 CH0 INT, ADC1 CH1 INT, ADC1 CH2 INT, ADC1 CH3 INT, ADC1 CH4 INT, ADC1 CH5 INT, ADC1 CH6 INT, ADC1 CH7 INT, ADC1 CH8 INT, ADC1 CH9 INT, ADC1 CH12 INT, ADC1 CH13 INT, ADC1 EIM INT, ADC1 ESM INT. More...
 
void CCU6SR0_IRQHandler (void)
 The SSU6SR0_IRQHandler checks which interrupt caused the call of the node handler 4 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR0_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT. More...
 
void CCU6SR1_IRQHandler (void)
 The SSU6SR1_IRQHandler checks which interrupt caused the call of the node handler 5 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR1_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT. More...
 
void CCU6SR2_IRQHandler (void)
 The SSU6SR2_IRQHandler checks which interrupt caused the call of the node handler 6 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR2_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT. More...
 
void CCU6SR3_IRQHandler (void)
 The SSU6SR3_IRQHandler checks which interrupt caused the call of the node handler 7 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR3_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT. More...
 
void SSC1_IRQHandler (void)
 The SSC1_IRQHandler checks which interrupt caused the call of the node handler 8 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSC1_IRQHandler is responsible for: SSC1 RX INT, SSC1 TX INT, SSC1 ERR INT. More...
 
void SSC2_IRQHandler (void)
 The SSC2_IRQHandler checks which interrupt caused the call of the node handler 9 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSC2_IRQHandler is responsible for: SSC2 RX INT, SSC2 TX INT, SSC2 ERR INT. More...
 
void UART1_IRQHandler (void)
 The UART1_IRQHandler checks which interrupt caused the call of the node handler 10 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. UART1_IRQHandler is responsible for: UART1 RX INT, UART1 TX INT, TIMER2 EXF2 INT, TIMER2 TF2 INT, LIN EOF INT, LIN ERR INT, LIN OC INT, LIN OT INT, LIN TMOUT INT, LIN M SM ERR INT. More...
 
void UART2_IRQHandler (void)
 The UART2_IRQHandler checks which interrupt caused the call of the node handler 11 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. UART2_IRQHandler is responsible for: UART2 RX INT, UART2 TX INT, TIMER21 EXF2 INT, TIMER21 TF2 INT, SCU EXINT2 RISING INT, SCU EXINT2 FALLING INT. More...
 
void EXINT0_IRQHandler (void)
 The EXINT0_IRQHandler checks which interrupt caused the call of the node handler 12 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. EXINT0_IRQHandler is responsible for: SCU EXINT0 RISING INT, SCU EXINT0 FALLING INT,. More...
 
void EXINT1_IRQHandler (void)
 The EXINT1_IRQHandler checks which interrupt caused the call of the node handler 13 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. EXINT1_IRQHandler is responsible for: SCU EXINT1 RISING INT, SCU EXINT1 FALLING INT,. More...
 
void WAKEUP_IRQHandler (void)
 The WAKEUP_IRQHandler checks which interrupt caused the call of the node handler 14 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. WAKEUP_IRQHandler is responsible for: PMU WAKEUP INT. More...
 
void DIV_IRQHandler (void)
 The DIV_IRQHandler checks which interrupt caused the call of the node handler 15 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. DIV_IRQHandler is responsible for: MATH DIVERR INT, MATH DIVEOC INT. More...
 
void CP_IRQHandler (void)
 The CP_IRQHandler checks which interrupt caused the call of the node handler 17 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. CP_IRQHandler is responsible for: ADC2 VSD UP INT, ADC2 VSD LO INT, ADC2 VCP UP INT, ADC2 VCP LO INT, ADC2 CP TEMP UP INT, ADC2 CP TEMP LO INT, BDRV VCP LO2 INT. More...
 
void BDRV_IRQHandler (void)
 The BDRV_IRQHandler checks which interrupt caused the call of the node handler 18 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. BDRV_IRQHandler is responsible for: BDRV HS1 OC INT, BDRV LS1 OC INT, BDRV HS2 OC INT, BDRV LS2 OC INT, BDRV HS1 DS INT, BDRV LS1 DS INT, BDRV HS2 DS INT, BDRV LS2 DS INT, BDRV SEQ ERR INT. More...
 
void HS_IRQHandler (void)
 The HS_IRQHandler checks which interrupt caused the call of the node handler 19 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. HS_IRQHandler is responsible for: HS HS1 OT INT, HS HS1 OL INT, HS HS1 OC INT. More...
 
void CSA_IRQHandler (void)
 The CSA_IRQHandler checks which interrupt caused the call of the node handler 20 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1 Post processing channel must be linked to interupt node 20. CSA_IRQHandler is responsible for: ADC1 PP CH2 UP INT, ADC1 PP CH2 LO INT, ADC1 PP CH3 UP INT, ADC1 PP CH3 LO INT, ADC1 PP CH4 UP INT, ADC1 PP CH4 LO INT, ADC1 PP CH5 UP INT, ADC1 PP CH5 LO INT, ADC1 PP CH6 UP INT, ADC1 PP CH6 LO INT, ADC1 PP CH7 UP INT, ADC1 PP CH7 LO INT. More...
 
void DU1_IRQHandler (void)
 The DU1_IRQHandler checks which interrupt caused the call of the node handler 21 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. DU1_IRQHandler is responsible for: ADC1 DU1UP INT, ADC1 DU1LO INT. More...
 
void MONx_IRQHandler (void)
 The MONx_IRQHandler checks which interrupt caused the call of the node handler 22 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1 Post processing channel is linked to interupt node 22 (for ADC1 PP Channel interrupts). MONx_IRQHandler is responsible for: MON1 RISING INT, MON1 FALLING INT, MON2 RISING INT, MON2 FALLING INT, MON3 RISING INT, MON3 FALLING INT, MON4 RISING INT, MON4 FALLING INT, ADC1 PP CH2 UP INT, ADC1 PP CH2 LO INT, ADC1 PP CH3 UP INT, ADC1 PP CH3 LO INT, ADC1 PP CH4 UP INT, ADC1 PP CH4 LO INT, ADC1 PP CH5 UP INT, ADC1 PP CH5 LO INT, ADC1 PP CH6 UP INT, ADC1 PP CH6 LO INT, ADC1 PP CH7 UP INT, ADC1 PP CH7 LO INT. More...
 
void PORT2_IRQHandler (void)
 The PORT2_IRQHandler checks which interrupt caused the call of the node handler 23 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1 Post processing channels must be linked to interupt node 23. PORT2_IRQHandler is responsible for: ADC1 PP CH2 UP INT, ADC1 PP CH2 LO INT, ADC1 PP CH3 UP INT, ADC1 PP CH3 LO INT, ADC1 PP CH4 UP INT, ADC1 PP CH4 LO INT, ADC1 PP CH5 UP INT, ADC1 PP CH5 LO INT, ADC1 PP CH6 UP INT, ADC1 PP CH6 LO INT, ADC1 PP CH7 UP INT, ADC1 PP CH7 LO INT. More...
 
void NMI_Handler (void)
 The NMI_Handler checks which interrupt caused the call of the node handler NMI (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. NMI_Handler is responsible for: SCU NMI WDT INT, SCU NMI PLL INT, SCU NMI STOF INT, SCU NMI OWD INT, SCU NMI MAP INT, SCU ECC RAM DB INT, SCU ECC NVM DB INT, ADC2 SYS TEMP UP INT, ADC2 SYS TEMP LO INT, ADC2 VS UP INT, ADC2 VS LO INT, ADC2 VDDC UP INT, ADC2 VDDC LO INT, ADC2 VDDP UP INT, ADC2 VDDP LO INT, PMU VDDEXT UV INT, PMU VDDEXT OT INT, PMU VDDC OV INT, PMU VDDC OL INT, PMU VDDP OV INT, PMU VDDP OL INT, PMU PMU OT INT, ADC2 VDDEXT UP INT, ADC2 VDDEXT LO INT, ADC1 PP CH0 UP INT, ADC1 PP CH0 LO INT, ADC1 PP CH1 UP INT, ADC1 PP CH1 LO INT,. More...
 
void HardFault_Handler (void)
 The HardFault_Handler handles the HardFault exception. More...
 
void SysTick_Handler (void)
 The SysTick_Handler handles the SysTick exception. More...
 

Function Documentation

◆ ADC1_IRQHandler()

void ADC1_IRQHandler ( void  )

The ADC1_IRQHandler checks which interrupt caused the call of the node handler 3 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1_IRQHandler is responsible for: ADC1 CH0 INT, ADC1 CH1 INT, ADC1 CH2 INT, ADC1 CH3 INT, ADC1 CH4 INT, ADC1 CH5 INT, ADC1 CH6 INT, ADC1 CH7 INT, ADC1 CH8 INT, ADC1 CH9 INT, ADC1 CH12 INT, ADC1 CH13 INT, ADC1 EIM INT, ADC1 ESM INT.

◆ ADC2_IRQHandler()

void ADC2_IRQHandler ( void  )

The ADC2_IRQHandler checks which interrupt caused the call of the node handler 2 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC2_IRQHandler is responsible for: ADC2 VBG UP INT, ADC2 VBG LO INT.

◆ BDRV_IRQHandler()

void BDRV_IRQHandler ( void  )

The BDRV_IRQHandler checks which interrupt caused the call of the node handler 18 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. BDRV_IRQHandler is responsible for: BDRV HS1 OC INT, BDRV LS1 OC INT, BDRV HS2 OC INT, BDRV LS2 OC INT, BDRV HS1 DS INT, BDRV LS1 DS INT, BDRV HS2 DS INT, BDRV LS2 DS INT, BDRV SEQ ERR INT.

◆ CCU6SR0_IRQHandler()

void CCU6SR0_IRQHandler ( void  )

The SSU6SR0_IRQHandler checks which interrupt caused the call of the node handler 4 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR0_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT.

◆ CCU6SR1_IRQHandler()

void CCU6SR1_IRQHandler ( void  )

The SSU6SR1_IRQHandler checks which interrupt caused the call of the node handler 5 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR1_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT.

◆ CCU6SR2_IRQHandler()

void CCU6SR2_IRQHandler ( void  )

The SSU6SR2_IRQHandler checks which interrupt caused the call of the node handler 6 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR2_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT.

◆ CCU6SR3_IRQHandler()

void CCU6SR3_IRQHandler ( void  )

The SSU6SR3_IRQHandler checks which interrupt caused the call of the node handler 7 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSU6SR3_IRQHandler is responsible for: CCU6 CH0 CMR INT, CCU6 CH0CMF INT, CCU6 CH1 CMR INT, CCU6 CH1CMF INT, CCU6 CH2 CMR INT, CCU6 CH2CMF INT, CCU6 T12 OM INT, CCU6 T12PM INT CCU6 T13 CM INT, CCU6 T13PM INT, CCU6 TRAP INT, CCU6 WHE INT, CCU6 CHE INT, CCU6 MCM STR INT.

◆ CP_IRQHandler()

void CP_IRQHandler ( void  )

The CP_IRQHandler checks which interrupt caused the call of the node handler 17 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. CP_IRQHandler is responsible for: ADC2 VSD UP INT, ADC2 VSD LO INT, ADC2 VCP UP INT, ADC2 VCP LO INT, ADC2 CP TEMP UP INT, ADC2 CP TEMP LO INT, BDRV VCP LO2 INT.

◆ CSA_IRQHandler()

void CSA_IRQHandler ( void  )

The CSA_IRQHandler checks which interrupt caused the call of the node handler 20 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1 Post processing channel must be linked to interupt node 20. CSA_IRQHandler is responsible for: ADC1 PP CH2 UP INT, ADC1 PP CH2 LO INT, ADC1 PP CH3 UP INT, ADC1 PP CH3 LO INT, ADC1 PP CH4 UP INT, ADC1 PP CH4 LO INT, ADC1 PP CH5 UP INT, ADC1 PP CH5 LO INT, ADC1 PP CH6 UP INT, ADC1 PP CH6 LO INT, ADC1 PP CH7 UP INT, ADC1 PP CH7 LO INT.

◆ DIV_IRQHandler()

void DIV_IRQHandler ( void  )

The DIV_IRQHandler checks which interrupt caused the call of the node handler 15 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. DIV_IRQHandler is responsible for: MATH DIVERR INT, MATH DIVEOC INT.

◆ DU1_IRQHandler()

void DU1_IRQHandler ( void  )

The DU1_IRQHandler checks which interrupt caused the call of the node handler 21 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. DU1_IRQHandler is responsible for: ADC1 DU1UP INT, ADC1 DU1LO INT.

◆ EXINT0_IRQHandler()

void EXINT0_IRQHandler ( void  )

The EXINT0_IRQHandler checks which interrupt caused the call of the node handler 12 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. EXINT0_IRQHandler is responsible for: SCU EXINT0 RISING INT, SCU EXINT0 FALLING INT,.

◆ EXINT1_IRQHandler()

void EXINT1_IRQHandler ( void  )

The EXINT1_IRQHandler checks which interrupt caused the call of the node handler 13 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. EXINT1_IRQHandler is responsible for: SCU EXINT1 RISING INT, SCU EXINT1 FALLING INT,.

◆ GPT1_IRQHandler()

void GPT1_IRQHandler ( void  )

The GPT1_IRQHandler checks which interrupt caused the call of the node handler 0 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. GPT1_IRQHandler is responsible for: GPT1 T2 INT, GPT1 T3 INT, GPT1 T4 INT.

◆ GPT2_IRQHandler()

void GPT2_IRQHandler ( void  )

The GPT2_IRQHandler checks which interrupt caused the call of the node handler 1 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. GPT2_IRQHandler is responsible for: GPT2 T5 INT, GPT2 T6 INT, GPT2 CAPREL INT.

◆ HardFault_Handler()

void HardFault_Handler ( void  )

The HardFault_Handler handles the HardFault exception.

◆ HS_IRQHandler()

void HS_IRQHandler ( void  )

The HS_IRQHandler checks which interrupt caused the call of the node handler 19 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. HS_IRQHandler is responsible for: HS HS1 OT INT, HS HS1 OL INT, HS HS1 OC INT.

◆ MONx_IRQHandler()

void MONx_IRQHandler ( void  )

The MONx_IRQHandler checks which interrupt caused the call of the node handler 22 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1 Post processing channel is linked to interupt node 22 (for ADC1 PP Channel interrupts). MONx_IRQHandler is responsible for: MON1 RISING INT, MON1 FALLING INT, MON2 RISING INT, MON2 FALLING INT, MON3 RISING INT, MON3 FALLING INT, MON4 RISING INT, MON4 FALLING INT, ADC1 PP CH2 UP INT, ADC1 PP CH2 LO INT, ADC1 PP CH3 UP INT, ADC1 PP CH3 LO INT, ADC1 PP CH4 UP INT, ADC1 PP CH4 LO INT, ADC1 PP CH5 UP INT, ADC1 PP CH5 LO INT, ADC1 PP CH6 UP INT, ADC1 PP CH6 LO INT, ADC1 PP CH7 UP INT, ADC1 PP CH7 LO INT.

◆ NMI_Handler()

void NMI_Handler ( void  )

The NMI_Handler checks which interrupt caused the call of the node handler NMI (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. NMI_Handler is responsible for: SCU NMI WDT INT, SCU NMI PLL INT, SCU NMI STOF INT, SCU NMI OWD INT, SCU NMI MAP INT, SCU ECC RAM DB INT, SCU ECC NVM DB INT, ADC2 SYS TEMP UP INT, ADC2 SYS TEMP LO INT, ADC2 VS UP INT, ADC2 VS LO INT, ADC2 VDDC UP INT, ADC2 VDDC LO INT, ADC2 VDDP UP INT, ADC2 VDDP LO INT, PMU VDDEXT UV INT, PMU VDDEXT OT INT, PMU VDDC OV INT, PMU VDDC OL INT, PMU VDDP OV INT, PMU VDDP OL INT, PMU PMU OT INT, ADC2 VDDEXT UP INT, ADC2 VDDEXT LO INT, ADC1 PP CH0 UP INT, ADC1 PP CH0 LO INT, ADC1 PP CH1 UP INT, ADC1 PP CH1 LO INT,.

◆ PORT2_IRQHandler()

void PORT2_IRQHandler ( void  )

The PORT2_IRQHandler checks which interrupt caused the call of the node handler 23 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. ADC1 Post processing channels must be linked to interupt node 23. PORT2_IRQHandler is responsible for: ADC1 PP CH2 UP INT, ADC1 PP CH2 LO INT, ADC1 PP CH3 UP INT, ADC1 PP CH3 LO INT, ADC1 PP CH4 UP INT, ADC1 PP CH4 LO INT, ADC1 PP CH5 UP INT, ADC1 PP CH5 LO INT, ADC1 PP CH6 UP INT, ADC1 PP CH6 LO INT, ADC1 PP CH7 UP INT, ADC1 PP CH7 LO INT.

◆ SSC1_IRQHandler()

void SSC1_IRQHandler ( void  )

The SSC1_IRQHandler checks which interrupt caused the call of the node handler 8 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSC1_IRQHandler is responsible for: SSC1 RX INT, SSC1 TX INT, SSC1 ERR INT.

◆ SSC2_IRQHandler()

void SSC2_IRQHandler ( void  )

The SSC2_IRQHandler checks which interrupt caused the call of the node handler 9 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. SSC2_IRQHandler is responsible for: SSC2 RX INT, SSC2 TX INT, SSC2 ERR INT.

◆ SysTick_Handler()

void SysTick_Handler ( void  )

The SysTick_Handler handles the SysTick exception.

◆ UART1_IRQHandler()

void UART1_IRQHandler ( void  )

The UART1_IRQHandler checks which interrupt caused the call of the node handler 10 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. UART1_IRQHandler is responsible for: UART1 RX INT, UART1 TX INT, TIMER2 EXF2 INT, TIMER2 TF2 INT, LIN EOF INT, LIN ERR INT, LIN OC INT, LIN OT INT, LIN TMOUT INT, LIN M SM ERR INT.

◆ UART2_IRQHandler()

void UART2_IRQHandler ( void  )

The UART2_IRQHandler checks which interrupt caused the call of the node handler 11 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. UART2_IRQHandler is responsible for: UART2 RX INT, UART2 TX INT, TIMER21 EXF2 INT, TIMER21 TF2 INT, SCU EXINT2 RISING INT, SCU EXINT2 FALLING INT.

◆ WAKEUP_IRQHandler()

void WAKEUP_IRQHandler ( void  )

The WAKEUP_IRQHandler checks which interrupt caused the call of the node handler 14 (interrupt enabled and status bit indicates that this interrupt occurred). Then it calls the corresponding interrupt handler and clears the interrupt status bit. WAKEUP_IRQHandler is responsible for: PMU WAKEUP INT.