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Infineon MOTIX™ MCU TLE985x Device Family SDK
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#define ADC1_CAL_CH0_1_CALGAIN_CH0_Msk (0xff00UL) |
ADC1 CAL_CH0_1: CALGAIN_CH0 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH0_1_CALGAIN_CH0_Pos (8UL) |
ADC1 CAL_CH0_1: CALGAIN_CH0 (Bit 8)
#define ADC1_CAL_CH0_1_CALGAIN_CH1_Msk (0xff000000UL) |
ADC1 CAL_CH0_1: CALGAIN_CH1 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH0_1_CALGAIN_CH1_Pos (24UL) |
ADC1 CAL_CH0_1: CALGAIN_CH1 (Bit 24)
#define ADC1_CAL_CH0_1_CALOFFS_CH0_Msk (0x1fUL) |
ADC1 CAL_CH0_1: CALOFFS_CH0 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH0_1_CALOFFS_CH0_Pos (0UL) |
ADC1 CAL_CH0_1: CALOFFS_CH0 (Bit 0)
#define ADC1_CAL_CH0_1_CALOFFS_CH1_Msk (0x1f0000UL) |
ADC1 CAL_CH0_1: CALOFFS_CH1 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH0_1_CALOFFS_CH1_Pos (16UL) |
ADC1 CAL_CH0_1: CALOFFS_CH1 (Bit 16)
#define ADC1_CAL_CH10_11_CALGAIN_CH10_Msk (0xff00UL) |
ADC1 CAL_CH10_11: CALGAIN_CH10 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH10_11_CALGAIN_CH10_Pos (8UL) |
ADC1 CAL_CH10_11: CALGAIN_CH10 (Bit 8)
#define ADC1_CAL_CH10_11_CALGAIN_CH11_Msk (0xff000000UL) |
ADC1 CAL_CH10_11: CALGAIN_CH11 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH10_11_CALGAIN_CH11_Pos (24UL) |
ADC1 CAL_CH10_11: CALGAIN_CH11 (Bit 24)
#define ADC1_CAL_CH10_11_CALOFFS_CH10_Msk (0x1fUL) |
ADC1 CAL_CH10_11: CALOFFS_CH10 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH10_11_CALOFFS_CH10_Pos (0UL) |
ADC1 CAL_CH10_11: CALOFFS_CH10 (Bit 0)
#define ADC1_CAL_CH10_11_CALOFFS_CH11_Msk (0x1f0000UL) |
ADC1 CAL_CH10_11: CALOFFS_CH11 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH10_11_CALOFFS_CH11_Pos (16UL) |
ADC1 CAL_CH10_11: CALOFFS_CH11 (Bit 16)
#define ADC1_CAL_CH12_13_CALGAIN_CH12_Msk (0xff00UL) |
ADC1 CAL_CH12_13: CALGAIN_CH12 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH12_13_CALGAIN_CH12_Pos (8UL) |
ADC1 CAL_CH12_13: CALGAIN_CH12 (Bit 8)
#define ADC1_CAL_CH12_13_CALGAIN_CH13_Msk (0xff000000UL) |
ADC1 CAL_CH12_13: CALGAIN_CH13 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH12_13_CALGAIN_CH13_Pos (24UL) |
ADC1 CAL_CH12_13: CALGAIN_CH13 (Bit 24)
#define ADC1_CAL_CH12_13_CALOFFS_CH12_Msk (0x1fUL) |
ADC1 CAL_CH12_13: CALOFFS_CH12 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH12_13_CALOFFS_CH12_Pos (0UL) |
ADC1 CAL_CH12_13: CALOFFS_CH12 (Bit 0)
#define ADC1_CAL_CH12_13_CALOFFS_CH13_Msk (0x1f0000UL) |
ADC1 CAL_CH12_13: CALOFFS_CH13 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH12_13_CALOFFS_CH13_Pos (16UL) |
ADC1 CAL_CH12_13: CALOFFS_CH13 (Bit 16)
#define ADC1_CAL_CH2_3_CALGAIN_CH2_Msk (0xff00UL) |
ADC1 CAL_CH2_3: CALGAIN_CH2 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH2_3_CALGAIN_CH2_Pos (8UL) |
ADC1 CAL_CH2_3: CALGAIN_CH2 (Bit 8)
#define ADC1_CAL_CH2_3_CALGAIN_CH3_Msk (0xff000000UL) |
ADC1 CAL_CH2_3: CALGAIN_CH3 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH2_3_CALGAIN_CH3_Pos (24UL) |
ADC1 CAL_CH2_3: CALGAIN_CH3 (Bit 24)
#define ADC1_CAL_CH2_3_CALOFFS_CH2_Msk (0x1fUL) |
ADC1 CAL_CH2_3: CALOFFS_CH2 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH2_3_CALOFFS_CH2_Pos (0UL) |
ADC1 CAL_CH2_3: CALOFFS_CH2 (Bit 0)
#define ADC1_CAL_CH2_3_CALOFFS_CH3_Msk (0x1f0000UL) |
ADC1 CAL_CH2_3: CALOFFS_CH3 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH2_3_CALOFFS_CH3_Pos (16UL) |
ADC1 CAL_CH2_3: CALOFFS_CH3 (Bit 16)
#define ADC1_CAL_CH4_5_CALGAIN_CH4_Msk (0xff00UL) |
ADC1 CAL_CH4_5: CALGAIN_CH4 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH4_5_CALGAIN_CH4_Pos (8UL) |
ADC1 CAL_CH4_5: CALGAIN_CH4 (Bit 8)
#define ADC1_CAL_CH4_5_CALGAIN_CH5_Msk (0xff000000UL) |
ADC1 CAL_CH4_5: CALGAIN_CH5 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH4_5_CALGAIN_CH5_Pos (24UL) |
ADC1 CAL_CH4_5: CALGAIN_CH5 (Bit 24)
#define ADC1_CAL_CH4_5_CALOFFS_CH4_Msk (0x1fUL) |
ADC1 CAL_CH4_5: CALOFFS_CH4 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH4_5_CALOFFS_CH4_Pos (0UL) |
ADC1 CAL_CH4_5: CALOFFS_CH4 (Bit 0)
#define ADC1_CAL_CH4_5_CALOFFS_CH5_Msk (0x1f0000UL) |
ADC1 CAL_CH4_5: CALOFFS_CH5 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH4_5_CALOFFS_CH5_Pos (16UL) |
ADC1 CAL_CH4_5: CALOFFS_CH5 (Bit 16)
#define ADC1_CAL_CH6_7_CALGAIN_CH6_Msk (0xff00UL) |
ADC1 CAL_CH6_7: CALGAIN_CH6 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH6_7_CALGAIN_CH6_Pos (8UL) |
ADC1 CAL_CH6_7: CALGAIN_CH6 (Bit 8)
#define ADC1_CAL_CH6_7_CALGAIN_CH7_Msk (0xff000000UL) |
ADC1 CAL_CH6_7: CALGAIN_CH7 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH6_7_CALGAIN_CH7_Pos (24UL) |
ADC1 CAL_CH6_7: CALGAIN_CH7 (Bit 24)
#define ADC1_CAL_CH6_7_CALOFFS_CH6_Msk (0x1fUL) |
ADC1 CAL_CH6_7: CALOFFS_CH6 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH6_7_CALOFFS_CH6_Pos (0UL) |
ADC1 CAL_CH6_7: CALOFFS_CH6 (Bit 0)
#define ADC1_CAL_CH6_7_CALOFFS_CH7_Msk (0x1f0000UL) |
ADC1 CAL_CH6_7: CALOFFS_CH7 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH6_7_CALOFFS_CH7_Pos (16UL) |
ADC1 CAL_CH6_7: CALOFFS_CH7 (Bit 16)
#define ADC1_CAL_CH8_9_CALGAIN_CH8_Msk (0xff00UL) |
ADC1 CAL_CH8_9: CALGAIN_CH8 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH8_9_CALGAIN_CH8_Pos (8UL) |
ADC1 CAL_CH8_9: CALGAIN_CH8 (Bit 8)
#define ADC1_CAL_CH8_9_CALGAIN_CH9_Msk (0xff000000UL) |
ADC1 CAL_CH8_9: CALGAIN_CH9 (Bitfield-Mask: 0xff)
#define ADC1_CAL_CH8_9_CALGAIN_CH9_Pos (24UL) |
ADC1 CAL_CH8_9: CALGAIN_CH9 (Bit 24)
#define ADC1_CAL_CH8_9_CALOFFS_CH8_Msk (0x1fUL) |
ADC1 CAL_CH8_9: CALOFFS_CH8 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH8_9_CALOFFS_CH8_Pos (0UL) |
ADC1 CAL_CH8_9: CALOFFS_CH8 (Bit 0)
#define ADC1_CAL_CH8_9_CALOFFS_CH9_Msk (0x1f0000UL) |
ADC1 CAL_CH8_9: CALOFFS_CH9 (Bitfield-Mask: 0x1f)
#define ADC1_CAL_CH8_9_CALOFFS_CH9_Pos (16UL) |
ADC1 CAL_CH8_9: CALOFFS_CH9 (Bit 16)
#define ADC1_CHx_EIM_ADC1_EIM_TRIG_SEL_Msk (0x70000UL) |
ADC1 CHx_EIM: ADC1_EIM_TRIG_SEL (Bitfield-Mask: 0x07)
#define ADC1_CHx_EIM_ADC1_EIM_TRIG_SEL_Pos (16UL) |
ADC1 CHx_EIM: ADC1_EIM_TRIG_SEL (Bit 16)
#define ADC1_CHx_EIM_EIM_CHx_Msk (0xfUL) |
ADC1 CHx_EIM: EIM_CHx (Bitfield-Mask: 0x0f)
#define ADC1_CHx_EIM_EIM_CHx_Pos (0UL) |
ADC1 CHx_EIM: EIM_CHx (Bit 0)
#define ADC1_CHx_EIM_EIM_EN_Msk (0x800UL) |
ADC1 CHx_EIM: EIM_EN (Bitfield-Mask: 0x01)
#define ADC1_CHx_EIM_EIM_EN_Pos (11UL) |
ADC1 CHx_EIM: EIM_EN (Bit 11)
#define ADC1_CHx_EIM_EIM_REP_Msk (0x700UL) |
ADC1 CHx_EIM: EIM_REP (Bitfield-Mask: 0x07)
#define ADC1_CHx_EIM_EIM_REP_Pos (8UL) |
ADC1 CHx_EIM: EIM_REP (Bit 8)
#define ADC1_CHx_ESM_ADC1_ESM_TRIG_SEL_Msk (0x70000UL) |
ADC1 CHx_ESM: ADC1_ESM_TRIG_SEL (Bitfield-Mask: 0x07)
#define ADC1_CHx_ESM_ADC1_ESM_TRIG_SEL_Pos (16UL) |
ADC1 CHx_ESM: ADC1_ESM_TRIG_SEL (Bit 16)
#define ADC1_CHx_ESM_ESM_0_Msk (0x3fffUL) |
ADC1 CHx_ESM: ESM_0 (Bitfield-Mask: 0x3fff)
#define ADC1_CHx_ESM_ESM_0_Pos (0UL) |
ADC1 CHx_ESM: ESM_0 (Bit 0)
#define ADC1_CHx_ESM_ESM_EN_Msk (0x40000000UL) |
ADC1 CHx_ESM: ESM_EN (Bitfield-Mask: 0x01)
#define ADC1_CHx_ESM_ESM_EN_Pos (30UL) |
ADC1 CHx_ESM: ESM_EN (Bit 30)
#define ADC1_CHx_ESM_ESM_STS_Msk (0x80000000UL) |
ADC1 CHx_ESM: ESM_STS (Bitfield-Mask: 0x01)
#define ADC1_CHx_ESM_ESM_STS_Pos (31UL) |
ADC1 CHx_ESM: ESM_STS (Bit 31)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP0_Msk (0x3UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP0 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP0_Pos (0UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP0 (Bit 0)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP1_Msk (0x300UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP1 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP1_Pos (8UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP1 (Bit 8)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP2_Msk (0x30000UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP2 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP2_Pos (16UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP2 (Bit 16)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP3_Msk (0x3000000UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP3 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_CNT_LO_PP3_Pos (24UL) |
ADC1 CNT0_3_LOWER: CNT_LO_PP3 (Bit 24)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP0_Msk (0x18UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP0 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP0_Pos (3UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP0 (Bit 3)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP1_Msk (0x1800UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP1 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP1_Pos (11UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP1 (Bit 11)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP2_Msk (0x180000UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP2 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP2_Pos (19UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP2 (Bit 19)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP3_Msk (0x18000000UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP3 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_LOWER_HYST_LO_PP3_Pos (27UL) |
ADC1 CNT0_3_LOWER: HYST_LO_PP3 (Bit 27)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP0_Msk (0x3UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP0 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP0_Pos (0UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP0 (Bit 0)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP1_Msk (0x300UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP1 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP1_Pos (8UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP1 (Bit 8)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP2_Msk (0x30000UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP2 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP2_Pos (16UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP2 (Bit 16)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP3_Msk (0x3000000UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP3 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_CNT_UP_PP3_Pos (24UL) |
ADC1 CNT0_3_UPPER: CNT_UP_PP3 (Bit 24)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP0_Msk (0x18UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP0 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP0_Pos (3UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP0 (Bit 3)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP1_Msk (0x1800UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP1 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP1_Pos (11UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP1 (Bit 11)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP2_Msk (0x180000UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP2 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP2_Pos (19UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP2 (Bit 19)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP3_Msk (0x18000000UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP3 (Bitfield-Mask: 0x03)
#define ADC1_CNT0_3_UPPER_HYST_UP_PP3_Pos (27UL) |
ADC1 CNT0_3_UPPER: HYST_UP_PP3 (Bit 27)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP4_Msk (0x3UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP4 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP4_Pos (0UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP4 (Bit 0)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP5_Msk (0x300UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP5 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP5_Pos (8UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP5 (Bit 8)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP6_Msk (0x30000UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP6 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP6_Pos (16UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP6 (Bit 16)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP7_Msk (0x3000000UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP7 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_CNT_LO_PP7_Pos (24UL) |
ADC1 CNT4_7_LOWER: CNT_LO_PP7 (Bit 24)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP4_Msk (0x18UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP4 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP4_Pos (3UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP4 (Bit 3)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP5_Msk (0x1800UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP5 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP5_Pos (11UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP5 (Bit 11)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP6_Msk (0x180000UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP6 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP6_Pos (19UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP6 (Bit 19)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP7_Msk (0x18000000UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP7 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_LOWER_HYST_LO_PP7_Pos (27UL) |
ADC1 CNT4_7_LOWER: HYST_LO_PP7 (Bit 27)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP4_Msk (0x3UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP4 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP4_Pos (0UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP4 (Bit 0)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP5_Msk (0x300UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP5 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP5_Pos (8UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP5 (Bit 8)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP6_Msk (0x30000UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP6 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP6_Pos (16UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP6 (Bit 16)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP7_Msk (0x3000000UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP7 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_CNT_UP_PP7_Pos (24UL) |
ADC1 CNT4_7_UPPER: CNT_UP_PP7 (Bit 24)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP4_Msk (0x18UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP4 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP4_Pos (3UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP4 (Bit 3)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP5_Msk (0x1800UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP5 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP5_Pos (11UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP5 (Bit 11)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP6_Msk (0x180000UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP6 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP6_Pos (19UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP6 (Bit 19)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP7_Msk (0x18000000UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP7 (Bitfield-Mask: 0x03)
#define ADC1_CNT4_7_UPPER_HYST_UP_PP7_Pos (27UL) |
ADC1 CNT4_7_UPPER: HYST_UP_PP7 (Bit 27)
#define ADC1_CTRL2_CAL_EN_Msk (0x3fffUL) |
ADC1 CTRL2: CAL_EN (Bitfield-Mask: 0x3fff)
#define ADC1_CTRL2_CAL_EN_Pos (0UL) |
ADC1 CTRL2: CAL_EN (Bit 0)
#define ADC1_CTRL3_EoC_FAIL_CLR_Msk (0x10UL) |
ADC1 CTRL3: EoC_FAIL_CLR (Bitfield-Mask: 0x01)
#define ADC1_CTRL3_EoC_FAIL_CLR_Pos (4UL) |
ADC1 CTRL3: EoC_FAIL_CLR (Bit 4)
#define ADC1_CTRL3_EoC_FAIL_Msk (0x40UL) |
ADC1 CTRL3: EoC_FAIL (Bitfield-Mask: 0x01)
#define ADC1_CTRL3_EoC_FAIL_Pos (6UL) |
ADC1 CTRL3: EoC_FAIL (Bit 6)
#define ADC1_CTRL3_MCM_PD_N_Msk (0x1UL) |
ADC1 CTRL3: MCM_PD_N (Bitfield-Mask: 0x01)
#define ADC1_CTRL3_MCM_PD_N_Pos (0UL) |
ADC1 CTRL3: MCM_PD_N (Bit 0)
#define ADC1_CTRL3_MCM_RDY_Msk (0x80UL) |
ADC1 CTRL3: MCM_RDY (Bitfield-Mask: 0x01)
#define ADC1_CTRL3_MCM_RDY_Pos (7UL) |
ADC1 CTRL3: MCM_RDY (Bit 7)
#define ADC1_CTRL3_SAMPLE_TIME_HVCH_Msk (0x1f00UL) |
ADC1 CTRL3: SAMPLE_TIME_HVCH (Bitfield-Mask: 0x1f)
#define ADC1_CTRL3_SAMPLE_TIME_HVCH_Pos (8UL) |
ADC1 CTRL3: SAMPLE_TIME_HVCH (Bit 8)
#define ADC1_CTRL3_SAMPLE_TIME_LVCH_Msk (0xf0000UL) |
ADC1 CTRL3: SAMPLE_TIME_LVCH (Bitfield-Mask: 0x0f)
#define ADC1_CTRL3_SAMPLE_TIME_LVCH_Pos (16UL) |
ADC1 CTRL3: SAMPLE_TIME_LVCH (Bit 16)
#define ADC1_CTRL3_SW_MODE_Msk (0x2UL) |
ADC1 CTRL3: SW_MODE (Bitfield-Mask: 0x01)
#define ADC1_CTRL3_SW_MODE_Pos (1UL) |
ADC1 CTRL3: SW_MODE (Bit 1)
#define ADC1_CTRL5_FILT_OUT_SEL_13_0_Msk (0x3fffUL) |
ADC1 CTRL5: FILT_OUT_SEL_13_0 (Bitfield-Mask: 0x3fff)
#define ADC1_CTRL5_FILT_OUT_SEL_13_0_Pos (0UL) |
ADC1 CTRL5: FILT_OUT_SEL_13_0 (Bit 0)
#define ADC1_CTRL_STS_CAL_SIGN_Msk (0x20UL) |
ADC1 CTRL_STS: CAL_SIGN (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_CAL_SIGN_Pos (5UL) |
ADC1 CTRL_STS: CAL_SIGN (Bit 5)
#define ADC1_CTRL_STS_EOC_Msk (0x80UL) |
ADC1 CTRL_STS: EOC (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_EOC_Pos (7UL) |
ADC1 CTRL_STS: EOC (Bit 7)
#define ADC1_CTRL_STS_PD_N_Msk (0x1UL) |
ADC1 CTRL_STS: PD_N (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_PD_N_Pos (0UL) |
ADC1 CTRL_STS: PD_N (Bit 0)
#define ADC1_CTRL_STS_READY_Msk (0x10UL) |
ADC1 CTRL_STS: READY (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_READY_Pos (4UL) |
ADC1 CTRL_STS: READY (Bit 4)
#define ADC1_CTRL_STS_SOOC_Msk (0x2UL) |
ADC1 CTRL_STS: SOOC (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_SOOC_Pos (1UL) |
ADC1 CTRL_STS: SOOC (Bit 1)
#define ADC1_CTRL_STS_SOS_Msk (0x4UL) |
ADC1 CTRL_STS: SOS (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_SOS_Pos (2UL) |
ADC1 CTRL_STS: SOS (Bit 2)
#define ADC1_CTRL_STS_STRTUP_DIS_Msk (0x40000UL) |
ADC1 CTRL_STS: STRTUP_DIS (Bitfield-Mask: 0x01)
#define ADC1_CTRL_STS_STRTUP_DIS_Pos (18UL) |
ADC1 CTRL_STS: STRTUP_DIS (Bit 18)
#define ADC1_CTRL_STS_SW_CH_SEL_Msk (0xf00UL) |
ADC1 CTRL_STS: SW_CH_SEL (Bitfield-Mask: 0x0f)
#define ADC1_CTRL_STS_SW_CH_SEL_Pos (8UL) |
ADC1 CTRL_STS: SW_CH_SEL (Bit 8)
#define ADC1_DCHCNT1_4_LOWER_CNT_LO_DCH1_Msk (0x3UL) |
ADC1 DCHCNT1_4_LOWER: CNT_LO_DCH1 (Bitfield-Mask: 0x03)
#define ADC1_DCHCNT1_4_LOWER_CNT_LO_DCH1_Pos (0UL) |
ADC1 DCHCNT1_4_LOWER: CNT_LO_DCH1 (Bit 0)
#define ADC1_DCHCNT1_4_LOWER_HYST_LO_DCH1_Msk (0x18UL) |
ADC1 DCHCNT1_4_LOWER: HYST_LO_DCH1 (Bitfield-Mask: 0x03)
#define ADC1_DCHCNT1_4_LOWER_HYST_LO_DCH1_Pos (3UL) |
ADC1 DCHCNT1_4_LOWER: HYST_LO_DCH1 (Bit 3)
#define ADC1_DCHCNT1_4_UPPER_CNT_UP_DCH1_Msk (0x3UL) |
ADC1 DCHCNT1_4_UPPER: CNT_UP_DCH1 (Bitfield-Mask: 0x03)
#define ADC1_DCHCNT1_4_UPPER_CNT_UP_DCH1_Pos (0UL) |
ADC1 DCHCNT1_4_UPPER: CNT_UP_DCH1 (Bit 0)
#define ADC1_DCHCNT1_4_UPPER_HYST_UP_DCH1_Msk (0x18UL) |
ADC1 DCHCNT1_4_UPPER: HYST_UP_DCH1 (Bitfield-Mask: 0x03)
#define ADC1_DCHCNT1_4_UPPER_HYST_UP_DCH1_Pos (3UL) |
ADC1 DCHCNT1_4_UPPER: HYST_UP_DCH1 (Bit 3)
#define ADC1_DCHTH1_4_LOWER_DCH1_LOW_Msk (0xffUL) |
ADC1 DCHTH1_4_LOWER: DCH1_LOW (Bitfield-Mask: 0xff)
#define ADC1_DCHTH1_4_LOWER_DCH1_LOW_Pos (0UL) |
ADC1 DCHTH1_4_LOWER: DCH1_LOW (Bit 0)
#define ADC1_DCHTH1_4_UPPER_DCH1_UP_Msk (0xffUL) |
ADC1 DCHTH1_4_UPPER: DCH1_UP (Bitfield-Mask: 0xff)
#define ADC1_DCHTH1_4_UPPER_DCH1_UP_Pos (0UL) |
ADC1 DCHTH1_4_UPPER: DCH1_UP (Bit 0)
#define ADC1_DIFFCH_OUT1_DCH1_Msk (0xfffUL) |
ADC1 DIFFCH_OUT1: DCH1 (Bitfield-Mask: 0xfff)
#define ADC1_DIFFCH_OUT1_DCH1_Pos (0UL) |
ADC1 DIFFCH_OUT1: DCH1 (Bit 0)
#define ADC1_DIFFCH_OUT1_DOF1_Msk (0x40000UL) |
ADC1 DIFFCH_OUT1: DOF1 (Bitfield-Mask: 0x01)
#define ADC1_DIFFCH_OUT1_DOF1_Pos (18UL) |
ADC1 DIFFCH_OUT1: DOF1 (Bit 18)
#define ADC1_DIFFCH_OUT1_DVF1_Msk (0x20000UL) |
ADC1 DIFFCH_OUT1: DVF1 (Bitfield-Mask: 0x01)
#define ADC1_DIFFCH_OUT1_DVF1_Pos (17UL) |
ADC1 DIFFCH_OUT1: DVF1 (Bit 17)
#define ADC1_DIFFCH_OUT1_DWFR1_Msk (0x10000UL) |
ADC1 DIFFCH_OUT1: DWFR1 (Bitfield-Mask: 0x01)
#define ADC1_DIFFCH_OUT1_DWFR1_Pos (16UL) |
ADC1 DIFFCH_OUT1: DWFR1 (Bit 16)
#define ADC1_DUIN_SEL_DU1_EN_Msk (0x1UL) |
ADC1 DUIN_SEL: DU1_EN (Bitfield-Mask: 0x01)
#define ADC1_DUIN_SEL_DU1_EN_Pos (0UL) |
ADC1 DUIN_SEL: DU1_EN (Bit 0)
#define ADC1_DUIN_SEL_DU1RES_NEG_Msk (0x10UL) |
ADC1 DUIN_SEL: DU1RES_NEG (Bitfield-Mask: 0x01)
#define ADC1_DUIN_SEL_DU1RES_NEG_Pos (4UL) |
ADC1 DUIN_SEL: DU1RES_NEG (Bit 4)
#define ADC1_FILT_OUT0_FILT_OUT_CH0_Msk (0xfffUL) |
ADC1 FILT_OUT0: FILT_OUT_CH0 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT0_FILT_OUT_CH0_Pos (0UL) |
ADC1 FILT_OUT0: FILT_OUT_CH0 (Bit 0)
#define ADC1_FILT_OUT0_OF0_Msk (0x40000UL) |
ADC1 FILT_OUT0: OF0 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT0_OF0_Pos (18UL) |
ADC1 FILT_OUT0: OF0 (Bit 18)
#define ADC1_FILT_OUT0_VF0_Msk (0x20000UL) |
ADC1 FILT_OUT0: VF0 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT0_VF0_Pos (17UL) |
ADC1 FILT_OUT0: VF0 (Bit 17)
#define ADC1_FILT_OUT0_WFR0_Msk (0x10000UL) |
ADC1 FILT_OUT0: WFR0 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT0_WFR0_Pos (16UL) |
ADC1 FILT_OUT0: WFR0 (Bit 16)
#define ADC1_FILT_OUT10_FILT_OUT_CH10_Msk (0xfffUL) |
ADC1 FILT_OUT10: FILT_OUT_CH10 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT10_FILT_OUT_CH10_Pos (0UL) |
ADC1 FILT_OUT10: FILT_OUT_CH10 (Bit 0)
#define ADC1_FILT_OUT10_OF10_Msk (0x40000UL) |
ADC1 FILT_OUT10: OF10 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT10_OF10_Pos (18UL) |
ADC1 FILT_OUT10: OF10 (Bit 18)
#define ADC1_FILT_OUT10_VF10_Msk (0x20000UL) |
ADC1 FILT_OUT10: VF10 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT10_VF10_Pos (17UL) |
ADC1 FILT_OUT10: VF10 (Bit 17)
#define ADC1_FILT_OUT10_WFR10_Msk (0x10000UL) |
ADC1 FILT_OUT10: WFR10 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT10_WFR10_Pos (16UL) |
ADC1 FILT_OUT10: WFR10 (Bit 16)
#define ADC1_FILT_OUT11_FILT_OUT_CH11_Msk (0xfffUL) |
ADC1 FILT_OUT11: FILT_OUT_CH11 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT11_FILT_OUT_CH11_Pos (0UL) |
ADC1 FILT_OUT11: FILT_OUT_CH11 (Bit 0)
#define ADC1_FILT_OUT11_OF11_Msk (0x40000UL) |
ADC1 FILT_OUT11: OF11 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT11_OF11_Pos (18UL) |
ADC1 FILT_OUT11: OF11 (Bit 18)
#define ADC1_FILT_OUT11_VF11_Msk (0x20000UL) |
ADC1 FILT_OUT11: VF11 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT11_VF11_Pos (17UL) |
ADC1 FILT_OUT11: VF11 (Bit 17)
#define ADC1_FILT_OUT11_WFR11_Msk (0x10000UL) |
ADC1 FILT_OUT11: WFR11 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT11_WFR11_Pos (16UL) |
ADC1 FILT_OUT11: WFR11 (Bit 16)
#define ADC1_FILT_OUT12_FILT_OUT_CH12_Msk (0xfffUL) |
ADC1 FILT_OUT12: FILT_OUT_CH12 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT12_FILT_OUT_CH12_Pos (0UL) |
ADC1 FILT_OUT12: FILT_OUT_CH12 (Bit 0)
#define ADC1_FILT_OUT12_OF12_Msk (0x40000UL) |
ADC1 FILT_OUT12: OF12 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT12_OF12_Pos (18UL) |
ADC1 FILT_OUT12: OF12 (Bit 18)
#define ADC1_FILT_OUT12_VF12_Msk (0x20000UL) |
ADC1 FILT_OUT12: VF12 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT12_VF12_Pos (17UL) |
ADC1 FILT_OUT12: VF12 (Bit 17)
#define ADC1_FILT_OUT12_WFR12_Msk (0x10000UL) |
ADC1 FILT_OUT12: WFR12 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT12_WFR12_Pos (16UL) |
ADC1 FILT_OUT12: WFR12 (Bit 16)
#define ADC1_FILT_OUT13_FILT_OUT_CH13_Msk (0xfffUL) |
ADC1 FILT_OUT13: FILT_OUT_CH13 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT13_FILT_OUT_CH13_Pos (0UL) |
ADC1 FILT_OUT13: FILT_OUT_CH13 (Bit 0)
#define ADC1_FILT_OUT13_OF13_Msk (0x40000UL) |
ADC1 FILT_OUT13: OF13 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT13_OF13_Pos (18UL) |
ADC1 FILT_OUT13: OF13 (Bit 18)
#define ADC1_FILT_OUT13_VF13_Msk (0x20000UL) |
ADC1 FILT_OUT13: VF13 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT13_VF13_Pos (17UL) |
ADC1 FILT_OUT13: VF13 (Bit 17)
#define ADC1_FILT_OUT13_WFR13_Msk (0x10000UL) |
ADC1 FILT_OUT13: WFR13 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT13_WFR13_Pos (16UL) |
ADC1 FILT_OUT13: WFR13 (Bit 16)
#define ADC1_FILT_OUT1_FILT_OUT_CH1_Msk (0xfffUL) |
ADC1 FILT_OUT1: FILT_OUT_CH1 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT1_FILT_OUT_CH1_Pos (0UL) |
ADC1 FILT_OUT1: FILT_OUT_CH1 (Bit 0)
#define ADC1_FILT_OUT1_OF1_Msk (0x40000UL) |
ADC1 FILT_OUT1: OF1 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT1_OF1_Pos (18UL) |
ADC1 FILT_OUT1: OF1 (Bit 18)
#define ADC1_FILT_OUT1_VF1_Msk (0x20000UL) |
ADC1 FILT_OUT1: VF1 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT1_VF1_Pos (17UL) |
ADC1 FILT_OUT1: VF1 (Bit 17)
#define ADC1_FILT_OUT1_WFR1_Msk (0x10000UL) |
ADC1 FILT_OUT1: WFR1 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT1_WFR1_Pos (16UL) |
ADC1 FILT_OUT1: WFR1 (Bit 16)
#define ADC1_FILT_OUT2_FILT_OUT_CH2_Msk (0xfffUL) |
ADC1 FILT_OUT2: FILT_OUT_CH2 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT2_FILT_OUT_CH2_Pos (0UL) |
ADC1 FILT_OUT2: FILT_OUT_CH2 (Bit 0)
#define ADC1_FILT_OUT2_OF2_Msk (0x40000UL) |
ADC1 FILT_OUT2: OF2 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT2_OF2_Pos (18UL) |
ADC1 FILT_OUT2: OF2 (Bit 18)
#define ADC1_FILT_OUT2_VF2_Msk (0x20000UL) |
ADC1 FILT_OUT2: VF2 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT2_VF2_Pos (17UL) |
ADC1 FILT_OUT2: VF2 (Bit 17)
#define ADC1_FILT_OUT2_WFR2_Msk (0x10000UL) |
ADC1 FILT_OUT2: WFR2 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT2_WFR2_Pos (16UL) |
ADC1 FILT_OUT2: WFR2 (Bit 16)
#define ADC1_FILT_OUT3_FILT_OUT_CH3_Msk (0xfffUL) |
ADC1 FILT_OUT3: FILT_OUT_CH3 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT3_FILT_OUT_CH3_Pos (0UL) |
ADC1 FILT_OUT3: FILT_OUT_CH3 (Bit 0)
#define ADC1_FILT_OUT3_OF3_Msk (0x40000UL) |
ADC1 FILT_OUT3: OF3 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT3_OF3_Pos (18UL) |
ADC1 FILT_OUT3: OF3 (Bit 18)
#define ADC1_FILT_OUT3_VF3_Msk (0x20000UL) |
ADC1 FILT_OUT3: VF3 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT3_VF3_Pos (17UL) |
ADC1 FILT_OUT3: VF3 (Bit 17)
#define ADC1_FILT_OUT3_WFR3_Msk (0x10000UL) |
ADC1 FILT_OUT3: WFR3 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT3_WFR3_Pos (16UL) |
ADC1 FILT_OUT3: WFR3 (Bit 16)
#define ADC1_FILT_OUT4_FILT_OUT_CH4_Msk (0xfffUL) |
ADC1 FILT_OUT4: FILT_OUT_CH4 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT4_FILT_OUT_CH4_Pos (0UL) |
ADC1 FILT_OUT4: FILT_OUT_CH4 (Bit 0)
#define ADC1_FILT_OUT4_OF4_Msk (0x40000UL) |
ADC1 FILT_OUT4: OF4 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT4_OF4_Pos (18UL) |
ADC1 FILT_OUT4: OF4 (Bit 18)
#define ADC1_FILT_OUT4_VF4_Msk (0x20000UL) |
ADC1 FILT_OUT4: VF4 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT4_VF4_Pos (17UL) |
ADC1 FILT_OUT4: VF4 (Bit 17)
#define ADC1_FILT_OUT4_WFR4_Msk (0x10000UL) |
ADC1 FILT_OUT4: WFR4 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT4_WFR4_Pos (16UL) |
ADC1 FILT_OUT4: WFR4 (Bit 16)
#define ADC1_FILT_OUT5_FILT_OUT_CH5_Msk (0xfffUL) |
ADC1 FILT_OUT5: FILT_OUT_CH5 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT5_FILT_OUT_CH5_Pos (0UL) |
ADC1 FILT_OUT5: FILT_OUT_CH5 (Bit 0)
#define ADC1_FILT_OUT5_OF5_Msk (0x40000UL) |
ADC1 FILT_OUT5: OF5 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT5_OF5_Pos (18UL) |
ADC1 FILT_OUT5: OF5 (Bit 18)
#define ADC1_FILT_OUT5_VF5_Msk (0x20000UL) |
ADC1 FILT_OUT5: VF5 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT5_VF5_Pos (17UL) |
ADC1 FILT_OUT5: VF5 (Bit 17)
#define ADC1_FILT_OUT5_WFR5_Msk (0x10000UL) |
ADC1 FILT_OUT5: WFR5 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT5_WFR5_Pos (16UL) |
ADC1 FILT_OUT5: WFR5 (Bit 16)
#define ADC1_FILT_OUT6_FILT_OUT_CH6_Msk (0xfffUL) |
ADC1 FILT_OUT6: FILT_OUT_CH6 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT6_FILT_OUT_CH6_Pos (0UL) |
ADC1 FILT_OUT6: FILT_OUT_CH6 (Bit 0)
#define ADC1_FILT_OUT6_OF6_Msk (0x40000UL) |
ADC1 FILT_OUT6: OF6 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT6_OF6_Pos (18UL) |
ADC1 FILT_OUT6: OF6 (Bit 18)
#define ADC1_FILT_OUT6_VF6_Msk (0x20000UL) |
ADC1 FILT_OUT6: VF6 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT6_VF6_Pos (17UL) |
ADC1 FILT_OUT6: VF6 (Bit 17)
#define ADC1_FILT_OUT6_WFR6_Msk (0x10000UL) |
ADC1 FILT_OUT6: WFR6 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT6_WFR6_Pos (16UL) |
ADC1 FILT_OUT6: WFR6 (Bit 16)
#define ADC1_FILT_OUT7_FILT_OUT_CH7_Msk (0xfffUL) |
ADC1 FILT_OUT7: FILT_OUT_CH7 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT7_FILT_OUT_CH7_Pos (0UL) |
ADC1 FILT_OUT7: FILT_OUT_CH7 (Bit 0)
#define ADC1_FILT_OUT7_OF7_Msk (0x40000UL) |
ADC1 FILT_OUT7: OF7 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT7_OF7_Pos (18UL) |
ADC1 FILT_OUT7: OF7 (Bit 18)
#define ADC1_FILT_OUT7_VF7_Msk (0x20000UL) |
ADC1 FILT_OUT7: VF7 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT7_VF7_Pos (17UL) |
ADC1 FILT_OUT7: VF7 (Bit 17)
#define ADC1_FILT_OUT7_WFR7_Msk (0x10000UL) |
ADC1 FILT_OUT7: WFR7 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT7_WFR7_Pos (16UL) |
ADC1 FILT_OUT7: WFR7 (Bit 16)
#define ADC1_FILT_OUT8_FILT_OUT_CH8_Msk (0xfffUL) |
ADC1 FILT_OUT8: FILT_OUT_CH8 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT8_FILT_OUT_CH8_Pos (0UL) |
ADC1 FILT_OUT8: FILT_OUT_CH8 (Bit 0)
#define ADC1_FILT_OUT8_OF8_Msk (0x40000UL) |
ADC1 FILT_OUT8: OF8 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT8_OF8_Pos (18UL) |
ADC1 FILT_OUT8: OF8 (Bit 18)
#define ADC1_FILT_OUT8_VF8_Msk (0x20000UL) |
ADC1 FILT_OUT8: VF8 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT8_VF8_Pos (17UL) |
ADC1 FILT_OUT8: VF8 (Bit 17)
#define ADC1_FILT_OUT8_WFR8_Msk (0x10000UL) |
ADC1 FILT_OUT8: WFR8 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT8_WFR8_Pos (16UL) |
ADC1 FILT_OUT8: WFR8 (Bit 16)
#define ADC1_FILT_OUT9_FILT_OUT_CH9_Msk (0xfffUL) |
ADC1 FILT_OUT9: FILT_OUT_CH9 (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUT9_FILT_OUT_CH9_Pos (0UL) |
ADC1 FILT_OUT9: FILT_OUT_CH9 (Bit 0)
#define ADC1_FILT_OUT9_OF9_Msk (0x40000UL) |
ADC1 FILT_OUT9: OF9 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT9_OF9_Pos (18UL) |
ADC1 FILT_OUT9: OF9 (Bit 18)
#define ADC1_FILT_OUT9_VF9_Msk (0x20000UL) |
ADC1 FILT_OUT9: VF9 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT9_VF9_Pos (17UL) |
ADC1 FILT_OUT9: VF9 (Bit 17)
#define ADC1_FILT_OUT9_WFR9_Msk (0x10000UL) |
ADC1 FILT_OUT9: WFR9 (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUT9_WFR9_Pos (16UL) |
ADC1 FILT_OUT9: WFR9 (Bit 16)
#define ADC1_FILT_OUTEIM_FILT_OUT_EIM_Msk (0xfffUL) |
ADC1 FILT_OUTEIM: FILT_OUT_EIM (Bitfield-Mask: 0xfff)
#define ADC1_FILT_OUTEIM_FILT_OUT_EIM_Pos (0UL) |
ADC1 FILT_OUTEIM: FILT_OUT_EIM (Bit 0)
#define ADC1_FILT_OUTEIM_OF_EIM_Msk (0x40000UL) |
ADC1 FILT_OUTEIM: OF_EIM (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUTEIM_OF_EIM_Pos (18UL) |
ADC1 FILT_OUTEIM: OF_EIM (Bit 18)
#define ADC1_FILT_OUTEIM_VF_EIM_Msk (0x20000UL) |
ADC1 FILT_OUTEIM: VF_EIM (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUTEIM_VF_EIM_Pos (17UL) |
ADC1 FILT_OUTEIM: VF_EIM (Bit 17)
#define ADC1_FILT_OUTEIM_WFR_EIM_Msk (0x10000UL) |
ADC1 FILT_OUTEIM: WFR_EIM (Bitfield-Mask: 0x01)
#define ADC1_FILT_OUTEIM_WFR_EIM_Pos (16UL) |
ADC1 FILT_OUTEIM: WFR_EIM (Bit 16)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH0_EN_Msk (0x1UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH0_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH0_EN_Pos (0UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH0_EN (Bit 0)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH1_EN_Msk (0x2UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH1_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH1_EN_Pos (1UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH1_EN (Bit 1)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH2_EN_Msk (0x4UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH2_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH2_EN_Pos (2UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH2_EN (Bit 2)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH3_EN_Msk (0x8UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH3_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH3_EN_Pos (3UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH3_EN (Bit 3)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH4_EN_Msk (0x10UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH4_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH4_EN_Pos (4UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH4_EN (Bit 4)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH5_EN_Msk (0x20UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH5_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH5_EN_Pos (5UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH5_EN (Bit 5)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH6_EN_Msk (0x40UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH6_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH6_EN_Pos (6UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH6_EN (Bit 6)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH7_EN_Msk (0x80UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH7_EN (Bitfield-Mask: 0x01)
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH7_EN_Pos (7UL) |
ADC1 FILT_UPLO_CTRL: FUL_PP_CH7_EN (Bit 7)
#define ADC1_FILTCOEFF0_13_CH0_Msk (0x3UL) |
ADC1 FILTCOEFF0_13: CH0 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH0_Pos (0UL) |
ADC1 FILTCOEFF0_13: CH0 (Bit 0)
#define ADC1_FILTCOEFF0_13_CH10_Msk (0x300000UL) |
ADC1 FILTCOEFF0_13: CH10 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH10_Pos (20UL) |
ADC1 FILTCOEFF0_13: CH10 (Bit 20)
#define ADC1_FILTCOEFF0_13_CH11_Msk (0xc00000UL) |
ADC1 FILTCOEFF0_13: CH11 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH11_Pos (22UL) |
ADC1 FILTCOEFF0_13: CH11 (Bit 22)
#define ADC1_FILTCOEFF0_13_CH12_Msk (0x3000000UL) |
ADC1 FILTCOEFF0_13: CH12 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH12_Pos (24UL) |
ADC1 FILTCOEFF0_13: CH12 (Bit 24)
#define ADC1_FILTCOEFF0_13_CH13_Msk (0xc000000UL) |
ADC1 FILTCOEFF0_13: CH13 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH13_Pos (26UL) |
ADC1 FILTCOEFF0_13: CH13 (Bit 26)
#define ADC1_FILTCOEFF0_13_CH1_Msk (0xcUL) |
ADC1 FILTCOEFF0_13: CH1 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH1_Pos (2UL) |
ADC1 FILTCOEFF0_13: CH1 (Bit 2)
#define ADC1_FILTCOEFF0_13_CH2_Msk (0x30UL) |
ADC1 FILTCOEFF0_13: CH2 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH2_Pos (4UL) |
ADC1 FILTCOEFF0_13: CH2 (Bit 4)
#define ADC1_FILTCOEFF0_13_CH3_Msk (0xc0UL) |
ADC1 FILTCOEFF0_13: CH3 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH3_Pos (6UL) |
ADC1 FILTCOEFF0_13: CH3 (Bit 6)
#define ADC1_FILTCOEFF0_13_CH4_Msk (0x300UL) |
ADC1 FILTCOEFF0_13: CH4 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH4_Pos (8UL) |
ADC1 FILTCOEFF0_13: CH4 (Bit 8)
#define ADC1_FILTCOEFF0_13_CH5_Msk (0xc00UL) |
ADC1 FILTCOEFF0_13: CH5 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH5_Pos (10UL) |
ADC1 FILTCOEFF0_13: CH5 (Bit 10)
#define ADC1_FILTCOEFF0_13_CH6_Msk (0x3000UL) |
ADC1 FILTCOEFF0_13: CH6 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH6_Pos (12UL) |
ADC1 FILTCOEFF0_13: CH6 (Bit 12)
#define ADC1_FILTCOEFF0_13_CH7_Msk (0xc000UL) |
ADC1 FILTCOEFF0_13: CH7 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH7_Pos (14UL) |
ADC1 FILTCOEFF0_13: CH7 (Bit 14)
#define ADC1_FILTCOEFF0_13_CH8_Msk (0x30000UL) |
ADC1 FILTCOEFF0_13: CH8 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH8_Pos (16UL) |
ADC1 FILTCOEFF0_13: CH8 (Bit 16)
#define ADC1_FILTCOEFF0_13_CH9_Msk (0xc0000UL) |
ADC1 FILTCOEFF0_13: CH9 (Bitfield-Mask: 0x03)
#define ADC1_FILTCOEFF0_13_CH9_Pos (18UL) |
ADC1 FILTCOEFF0_13: CH9 (Bit 18)
#define ADC1_IRQCLR_1_DU1LO_ISC_Msk (0x1000000UL) |
ADC1 IRQCLR_1: DU1LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_DU1LO_ISC_Pos (24UL) |
ADC1 IRQCLR_1: DU1LO_ISC (Bit 24)
#define ADC1_IRQCLR_1_DU1UP_ISC_Msk (0x2000000UL) |
ADC1 IRQCLR_1: DU1UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_DU1UP_ISC_Pos (25UL) |
ADC1 IRQCLR_1: DU1UP_ISC (Bit 25)
#define ADC1_IRQCLR_1_EIM_ISC_Msk (0x10000UL) |
ADC1 IRQCLR_1: EIM_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_EIM_ISC_Pos (16UL) |
ADC1 IRQCLR_1: EIM_ISC (Bit 16)
#define ADC1_IRQCLR_1_ESM_ISC_Msk (0x20000UL) |
ADC1 IRQCLR_1: ESM_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_ESM_ISC_Pos (17UL) |
ADC1 IRQCLR_1: ESM_ISC (Bit 17)
#define ADC1_IRQCLR_1_IIR_CH0_ISC_Msk (0x1UL) |
ADC1 IRQCLR_1: IIR_CH0_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH0_ISC_Pos (0UL) |
ADC1 IRQCLR_1: IIR_CH0_ISC (Bit 0)
#define ADC1_IRQCLR_1_IIR_CH10_ISC_Msk (0x400UL) |
ADC1 IRQCLR_1: IIR_CH10_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH10_ISC_Pos (10UL) |
ADC1 IRQCLR_1: IIR_CH10_ISC (Bit 10)
#define ADC1_IRQCLR_1_IIR_CH11_ISC_Msk (0x800UL) |
ADC1 IRQCLR_1: IIR_CH11_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH11_ISC_Pos (11UL) |
ADC1 IRQCLR_1: IIR_CH11_ISC (Bit 11)
#define ADC1_IRQCLR_1_IIR_CH12_ISC_Msk (0x1000UL) |
ADC1 IRQCLR_1: IIR_CH12_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH12_ISC_Pos (12UL) |
ADC1 IRQCLR_1: IIR_CH12_ISC (Bit 12)
#define ADC1_IRQCLR_1_IIR_CH13_ISC_Msk (0x2000UL) |
ADC1 IRQCLR_1: IIR_CH13_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH13_ISC_Pos (13UL) |
ADC1 IRQCLR_1: IIR_CH13_ISC (Bit 13)
#define ADC1_IRQCLR_1_IIR_CH2_ISC_Msk (0x4UL) |
ADC1 IRQCLR_1: IIR_CH2_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH2_ISC_Pos (2UL) |
ADC1 IRQCLR_1: IIR_CH2_ISC (Bit 2)
#define ADC1_IRQCLR_1_IIR_CH3_ISC_Msk (0x8UL) |
ADC1 IRQCLR_1: IIR_CH3_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH3_ISC_Pos (3UL) |
ADC1 IRQCLR_1: IIR_CH3_ISC (Bit 3)
#define ADC1_IRQCLR_1_IIR_CH4_ISC_Msk (0x10UL) |
ADC1 IRQCLR_1: IIR_CH4_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH4_ISC_Pos (4UL) |
ADC1 IRQCLR_1: IIR_CH4_ISC (Bit 4)
#define ADC1_IRQCLR_1_IIR_CH5_ISC_Msk (0x20UL) |
ADC1 IRQCLR_1: IIR_CH5_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH5_ISC_Pos (5UL) |
ADC1 IRQCLR_1: IIR_CH5_ISC (Bit 5)
#define ADC1_IRQCLR_1_IIR_CH6_ISC_Msk (0x40UL) |
ADC1 IRQCLR_1: IIR_CH6_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH6_ISC_Pos (6UL) |
ADC1 IRQCLR_1: IIR_CH6_ISC (Bit 6)
#define ADC1_IRQCLR_1_IIR_CH7_ISC_Msk (0x80UL) |
ADC1 IRQCLR_1: IIR_CH7_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH7_ISC_Pos (7UL) |
ADC1 IRQCLR_1: IIR_CH7_ISC (Bit 7)
#define ADC1_IRQCLR_1_IIR_CH8_ISC_Msk (0x100UL) |
ADC1 IRQCLR_1: IIR_CH8_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH8_ISC_Pos (8UL) |
ADC1 IRQCLR_1: IIR_CH8_ISC (Bit 8)
#define ADC1_IRQCLR_1_IIR_CH9_ISC_Msk (0x200UL) |
ADC1 IRQCLR_1: IIR_CH9_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_IIR_CH9_ISC_Pos (9UL) |
ADC1 IRQCLR_1: IIR_CH9_ISC (Bit 9)
#define ADC1_IRQCLR_1_VS_ISC_Msk (0x2UL) |
ADC1 IRQCLR_1: VS_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_1_VS_ISC_Pos (1UL) |
ADC1 IRQCLR_1: VS_ISC (Bit 1)
#define ADC1_IRQCLR_2_PP_CH0_LO_ISC_Msk (0x1UL) |
ADC1 IRQCLR_2: PP_CH0_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH0_LO_ISC_Pos (0UL) |
ADC1 IRQCLR_2: PP_CH0_LO_ISC (Bit 0)
#define ADC1_IRQCLR_2_PP_CH0_UP_ISC_Msk (0x10000UL) |
ADC1 IRQCLR_2: PP_CH0_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH0_UP_ISC_Pos (16UL) |
ADC1 IRQCLR_2: PP_CH0_UP_ISC (Bit 16)
#define ADC1_IRQCLR_2_PP_CH2_LO_ISC_Msk (0x4UL) |
ADC1 IRQCLR_2: PP_CH2_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH2_LO_ISC_Pos (2UL) |
ADC1 IRQCLR_2: PP_CH2_LO_ISC (Bit 2)
#define ADC1_IRQCLR_2_PP_CH2_UP_ISC_Msk (0x40000UL) |
ADC1 IRQCLR_2: PP_CH2_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH2_UP_ISC_Pos (18UL) |
ADC1 IRQCLR_2: PP_CH2_UP_ISC (Bit 18)
#define ADC1_IRQCLR_2_PP_CH3_LO_ISC_Msk (0x8UL) |
ADC1 IRQCLR_2: PP_CH3_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH3_LO_ISC_Pos (3UL) |
ADC1 IRQCLR_2: PP_CH3_LO_ISC (Bit 3)
#define ADC1_IRQCLR_2_PP_CH3_UP_ISC_Msk (0x80000UL) |
ADC1 IRQCLR_2: PP_CH3_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH3_UP_ISC_Pos (19UL) |
ADC1 IRQCLR_2: PP_CH3_UP_ISC (Bit 19)
#define ADC1_IRQCLR_2_PP_CH4_LO_ISC_Msk (0x10UL) |
ADC1 IRQCLR_2: PP_CH4_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH4_LO_ISC_Pos (4UL) |
ADC1 IRQCLR_2: PP_CH4_LO_ISC (Bit 4)
#define ADC1_IRQCLR_2_PP_CH4_UP_ISC_Msk (0x100000UL) |
ADC1 IRQCLR_2: PP_CH4_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH4_UP_ISC_Pos (20UL) |
ADC1 IRQCLR_2: PP_CH4_UP_ISC (Bit 20)
#define ADC1_IRQCLR_2_PP_CH5_LO_ISC_Msk (0x20UL) |
ADC1 IRQCLR_2: PP_CH5_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH5_LO_ISC_Pos (5UL) |
ADC1 IRQCLR_2: PP_CH5_LO_ISC (Bit 5)
#define ADC1_IRQCLR_2_PP_CH5_UP_ISC_Msk (0x200000UL) |
ADC1 IRQCLR_2: PP_CH5_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH5_UP_ISC_Pos (21UL) |
ADC1 IRQCLR_2: PP_CH5_UP_ISC (Bit 21)
#define ADC1_IRQCLR_2_PP_CH6_LO_ISC_Msk (0x40UL) |
ADC1 IRQCLR_2: PP_CH6_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH6_LO_ISC_Pos (6UL) |
ADC1 IRQCLR_2: PP_CH6_LO_ISC (Bit 6)
#define ADC1_IRQCLR_2_PP_CH6_UP_ISC_Msk (0x400000UL) |
ADC1 IRQCLR_2: PP_CH6_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH6_UP_ISC_Pos (22UL) |
ADC1 IRQCLR_2: PP_CH6_UP_ISC (Bit 22)
#define ADC1_IRQCLR_2_PP_CH7_LO_ISC_Msk (0x80UL) |
ADC1 IRQCLR_2: PP_CH7_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH7_LO_ISC_Pos (7UL) |
ADC1 IRQCLR_2: PP_CH7_LO_ISC (Bit 7)
#define ADC1_IRQCLR_2_PP_CH7_UP_ISC_Msk (0x800000UL) |
ADC1 IRQCLR_2: PP_CH7_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_PP_CH7_UP_ISC_Pos (23UL) |
ADC1 IRQCLR_2: PP_CH7_UP_ISC (Bit 23)
#define ADC1_IRQCLR_2_VS_LO_ISC_Msk (0x2UL) |
ADC1 IRQCLR_2: VS_LO_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_VS_LO_ISC_Pos (1UL) |
ADC1 IRQCLR_2: VS_LO_ISC (Bit 1)
#define ADC1_IRQCLR_2_VS_UP_ISC_Msk (0x20000UL) |
ADC1 IRQCLR_2: VS_UP_ISC (Bitfield-Mask: 0x01)
#define ADC1_IRQCLR_2_VS_UP_ISC_Pos (17UL) |
ADC1 IRQCLR_2: VS_UP_ISC (Bit 17)
#define ADC1_IRQEN_1_DU1LO_IEN_Msk (0x1000000UL) |
ADC1 IRQEN_1: DU1LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_DU1LO_IEN_Pos (24UL) |
ADC1 IRQEN_1: DU1LO_IEN (Bit 24)
#define ADC1_IRQEN_1_DU1UP_IEN_Msk (0x2000000UL) |
ADC1 IRQEN_1: DU1UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_DU1UP_IEN_Pos (25UL) |
ADC1 IRQEN_1: DU1UP_IEN (Bit 25)
#define ADC1_IRQEN_1_EIM_IEN_Msk (0x10000UL) |
ADC1 IRQEN_1: EIM_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_EIM_IEN_Pos (16UL) |
ADC1 IRQEN_1: EIM_IEN (Bit 16)
#define ADC1_IRQEN_1_ESM_IEN_Msk (0x20000UL) |
ADC1 IRQEN_1: ESM_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_ESM_IEN_Pos (17UL) |
ADC1 IRQEN_1: ESM_IEN (Bit 17)
#define ADC1_IRQEN_1_IIR_CH0_IEN_Msk (0x1UL) |
ADC1 IRQEN_1: IIR_CH0_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH0_IEN_Pos (0UL) |
ADC1 IRQEN_1: IIR_CH0_IEN (Bit 0)
#define ADC1_IRQEN_1_IIR_CH10_IEN_Msk (0x400UL) |
ADC1 IRQEN_1: IIR_CH10_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH10_IEN_Pos (10UL) |
ADC1 IRQEN_1: IIR_CH10_IEN (Bit 10)
#define ADC1_IRQEN_1_IIR_CH11_IEN_Msk (0x800UL) |
ADC1 IRQEN_1: IIR_CH11_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH11_IEN_Pos (11UL) |
ADC1 IRQEN_1: IIR_CH11_IEN (Bit 11)
#define ADC1_IRQEN_1_IIR_CH12_IEN_Msk (0x1000UL) |
ADC1 IRQEN_1: IIR_CH12_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH12_IEN_Pos (12UL) |
ADC1 IRQEN_1: IIR_CH12_IEN (Bit 12)
#define ADC1_IRQEN_1_IIR_CH13_IEN_Msk (0x2000UL) |
ADC1 IRQEN_1: IIR_CH13_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH13_IEN_Pos (13UL) |
ADC1 IRQEN_1: IIR_CH13_IEN (Bit 13)
#define ADC1_IRQEN_1_IIR_CH2_IEN_Msk (0x4UL) |
ADC1 IRQEN_1: IIR_CH2_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH2_IEN_Pos (2UL) |
ADC1 IRQEN_1: IIR_CH2_IEN (Bit 2)
#define ADC1_IRQEN_1_IIR_CH3_IEN_Msk (0x8UL) |
ADC1 IRQEN_1: IIR_CH3_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH3_IEN_Pos (3UL) |
ADC1 IRQEN_1: IIR_CH3_IEN (Bit 3)
#define ADC1_IRQEN_1_IIR_CH4_IEN_Msk (0x10UL) |
ADC1 IRQEN_1: IIR_CH4_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH4_IEN_Pos (4UL) |
ADC1 IRQEN_1: IIR_CH4_IEN (Bit 4)
#define ADC1_IRQEN_1_IIR_CH5_IEN_Msk (0x20UL) |
ADC1 IRQEN_1: IIR_CH5_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH5_IEN_Pos (5UL) |
ADC1 IRQEN_1: IIR_CH5_IEN (Bit 5)
#define ADC1_IRQEN_1_IIR_CH6_IEN_Msk (0x40UL) |
ADC1 IRQEN_1: IIR_CH6_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH6_IEN_Pos (6UL) |
ADC1 IRQEN_1: IIR_CH6_IEN (Bit 6)
#define ADC1_IRQEN_1_IIR_CH7_IEN_Msk (0x80UL) |
ADC1 IRQEN_1: IIR_CH7_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH7_IEN_Pos (7UL) |
ADC1 IRQEN_1: IIR_CH7_IEN (Bit 7)
#define ADC1_IRQEN_1_IIR_CH8_IEN_Msk (0x100UL) |
ADC1 IRQEN_1: IIR_CH8_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH8_IEN_Pos (8UL) |
ADC1 IRQEN_1: IIR_CH8_IEN (Bit 8)
#define ADC1_IRQEN_1_IIR_CH9_IEN_Msk (0x200UL) |
ADC1 IRQEN_1: IIR_CH9_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_IIR_CH9_IEN_Pos (9UL) |
ADC1 IRQEN_1: IIR_CH9_IEN (Bit 9)
#define ADC1_IRQEN_1_VS_IEN_Msk (0x2UL) |
ADC1 IRQEN_1: VS_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_1_VS_IEN_Pos (1UL) |
ADC1 IRQEN_1: VS_IEN (Bit 1)
#define ADC1_IRQEN_2_PP_CH0_LO_IEN_Msk (0x1UL) |
ADC1 IRQEN_2: PP_CH0_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH0_LO_IEN_Pos (0UL) |
ADC1 IRQEN_2: PP_CH0_LO_IEN (Bit 0)
#define ADC1_IRQEN_2_PP_CH0_UP_IEN_Msk (0x10000UL) |
ADC1 IRQEN_2: PP_CH0_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH0_UP_IEN_Pos (16UL) |
ADC1 IRQEN_2: PP_CH0_UP_IEN (Bit 16)
#define ADC1_IRQEN_2_PP_CH2_LO_IEN_Msk (0x4UL) |
ADC1 IRQEN_2: PP_CH2_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH2_LO_IEN_Pos (2UL) |
ADC1 IRQEN_2: PP_CH2_LO_IEN (Bit 2)
#define ADC1_IRQEN_2_PP_CH2_UP_IEN_Msk (0x40000UL) |
ADC1 IRQEN_2: PP_CH2_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH2_UP_IEN_Pos (18UL) |
ADC1 IRQEN_2: PP_CH2_UP_IEN (Bit 18)
#define ADC1_IRQEN_2_PP_CH3_LO_IEN_Msk (0x8UL) |
ADC1 IRQEN_2: PP_CH3_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH3_LO_IEN_Pos (3UL) |
ADC1 IRQEN_2: PP_CH3_LO_IEN (Bit 3)
#define ADC1_IRQEN_2_PP_CH3_UP_IEN_Msk (0x80000UL) |
ADC1 IRQEN_2: PP_CH3_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH3_UP_IEN_Pos (19UL) |
ADC1 IRQEN_2: PP_CH3_UP_IEN (Bit 19)
#define ADC1_IRQEN_2_PP_CH4_LO_IEN_Msk (0x10UL) |
ADC1 IRQEN_2: PP_CH4_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH4_LO_IEN_Pos (4UL) |
ADC1 IRQEN_2: PP_CH4_LO_IEN (Bit 4)
#define ADC1_IRQEN_2_PP_CH4_UP_IEN_Msk (0x100000UL) |
ADC1 IRQEN_2: PP_CH4_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH4_UP_IEN_Pos (20UL) |
ADC1 IRQEN_2: PP_CH4_UP_IEN (Bit 20)
#define ADC1_IRQEN_2_PP_CH5_LO_IEN_Msk (0x20UL) |
ADC1 IRQEN_2: PP_CH5_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH5_LO_IEN_Pos (5UL) |
ADC1 IRQEN_2: PP_CH5_LO_IEN (Bit 5)
#define ADC1_IRQEN_2_PP_CH5_UP_IEN_Msk (0x200000UL) |
ADC1 IRQEN_2: PP_CH5_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH5_UP_IEN_Pos (21UL) |
ADC1 IRQEN_2: PP_CH5_UP_IEN (Bit 21)
#define ADC1_IRQEN_2_PP_CH6_LO_IEN_Msk (0x40UL) |
ADC1 IRQEN_2: PP_CH6_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH6_LO_IEN_Pos (6UL) |
ADC1 IRQEN_2: PP_CH6_LO_IEN (Bit 6)
#define ADC1_IRQEN_2_PP_CH6_UP_IEN_Msk (0x400000UL) |
ADC1 IRQEN_2: PP_CH6_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH6_UP_IEN_Pos (22UL) |
ADC1 IRQEN_2: PP_CH6_UP_IEN (Bit 22)
#define ADC1_IRQEN_2_PP_CH7_LO_IEN_Msk (0x80UL) |
ADC1 IRQEN_2: PP_CH7_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH7_LO_IEN_Pos (7UL) |
ADC1 IRQEN_2: PP_CH7_LO_IEN (Bit 7)
#define ADC1_IRQEN_2_PP_CH7_UP_IEN_Msk (0x800000UL) |
ADC1 IRQEN_2: PP_CH7_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_PP_CH7_UP_IEN_Pos (23UL) |
ADC1 IRQEN_2: PP_CH7_UP_IEN (Bit 23)
#define ADC1_IRQEN_2_VS_LO_IEN_Msk (0x2UL) |
ADC1 IRQEN_2: VS_LO_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_VS_LO_IEN_Pos (1UL) |
ADC1 IRQEN_2: VS_LO_IEN (Bit 1)
#define ADC1_IRQEN_2_VS_UP_IEN_Msk (0x20000UL) |
ADC1 IRQEN_2: VS_UP_IEN (Bitfield-Mask: 0x01)
#define ADC1_IRQEN_2_VS_UP_IEN_Pos (17UL) |
ADC1 IRQEN_2: VS_UP_IEN (Bit 17)
#define ADC1_IRQS_1_DU1LO_IS_Msk (0x1000000UL) |
ADC1 IRQS_1: DU1LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_DU1LO_IS_Pos (24UL) |
ADC1 IRQS_1: DU1LO_IS (Bit 24)
#define ADC1_IRQS_1_DU1UP_IS_Msk (0x2000000UL) |
ADC1 IRQS_1: DU1UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_DU1UP_IS_Pos (25UL) |
ADC1 IRQS_1: DU1UP_IS (Bit 25)
#define ADC1_IRQS_1_EIM_IS_Msk (0x10000UL) |
ADC1 IRQS_1: EIM_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_EIM_IS_Pos (16UL) |
ADC1 IRQS_1: EIM_IS (Bit 16)
#define ADC1_IRQS_1_ESM_IS_Msk (0x20000UL) |
ADC1 IRQS_1: ESM_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_ESM_IS_Pos (17UL) |
ADC1 IRQS_1: ESM_IS (Bit 17)
#define ADC1_IRQS_1_IIR_CH0_IS_Msk (0x1UL) |
ADC1 IRQS_1: IIR_CH0_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH0_IS_Pos (0UL) |
ADC1 IRQS_1: IIR_CH0_IS (Bit 0)
#define ADC1_IRQS_1_IIR_CH10_IS_Msk (0x400UL) |
ADC1 IRQS_1: IIR_CH10_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH10_IS_Pos (10UL) |
ADC1 IRQS_1: IIR_CH10_IS (Bit 10)
#define ADC1_IRQS_1_IIR_CH11_IS_Msk (0x800UL) |
ADC1 IRQS_1: IIR_CH11_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH11_IS_Pos (11UL) |
ADC1 IRQS_1: IIR_CH11_IS (Bit 11)
#define ADC1_IRQS_1_IIR_CH12_IS_Msk (0x1000UL) |
ADC1 IRQS_1: IIR_CH12_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH12_IS_Pos (12UL) |
ADC1 IRQS_1: IIR_CH12_IS (Bit 12)
#define ADC1_IRQS_1_IIR_CH13_IS_Msk (0x2000UL) |
ADC1 IRQS_1: IIR_CH13_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH13_IS_Pos (13UL) |
ADC1 IRQS_1: IIR_CH13_IS (Bit 13)
#define ADC1_IRQS_1_IIR_CH2_IS_Msk (0x4UL) |
ADC1 IRQS_1: IIR_CH2_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH2_IS_Pos (2UL) |
ADC1 IRQS_1: IIR_CH2_IS (Bit 2)
#define ADC1_IRQS_1_IIR_CH3_IS_Msk (0x8UL) |
ADC1 IRQS_1: IIR_CH3_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH3_IS_Pos (3UL) |
ADC1 IRQS_1: IIR_CH3_IS (Bit 3)
#define ADC1_IRQS_1_IIR_CH4_IS_Msk (0x10UL) |
ADC1 IRQS_1: IIR_CH4_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH4_IS_Pos (4UL) |
ADC1 IRQS_1: IIR_CH4_IS (Bit 4)
#define ADC1_IRQS_1_IIR_CH5_IS_Msk (0x20UL) |
ADC1 IRQS_1: IIR_CH5_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH5_IS_Pos (5UL) |
ADC1 IRQS_1: IIR_CH5_IS (Bit 5)
#define ADC1_IRQS_1_IIR_CH6_IS_Msk (0x40UL) |
ADC1 IRQS_1: IIR_CH6_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH6_IS_Pos (6UL) |
ADC1 IRQS_1: IIR_CH6_IS (Bit 6)
#define ADC1_IRQS_1_IIR_CH7_IS_Msk (0x80UL) |
ADC1 IRQS_1: IIR_CH7_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH7_IS_Pos (7UL) |
ADC1 IRQS_1: IIR_CH7_IS (Bit 7)
#define ADC1_IRQS_1_IIR_CH8_IS_Msk (0x100UL) |
ADC1 IRQS_1: IIR_CH8_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH8_IS_Pos (8UL) |
ADC1 IRQS_1: IIR_CH8_IS (Bit 8)
#define ADC1_IRQS_1_IIR_CH9_IS_Msk (0x200UL) |
ADC1 IRQS_1: IIR_CH9_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_IIR_CH9_IS_Pos (9UL) |
ADC1 IRQS_1: IIR_CH9_IS (Bit 9)
#define ADC1_IRQS_1_VS_IS_Msk (0x2UL) |
ADC1 IRQS_1: VS_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_1_VS_IS_Pos (1UL) |
ADC1 IRQS_1: VS_IS (Bit 1)
#define ADC1_IRQS_2_PP_CH0_LO_IS_Msk (0x1UL) |
ADC1 IRQS_2: PP_CH0_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH0_LO_IS_Pos (0UL) |
ADC1 IRQS_2: PP_CH0_LO_IS (Bit 0)
#define ADC1_IRQS_2_PP_CH0_UP_IS_Msk (0x10000UL) |
ADC1 IRQS_2: PP_CH0_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH0_UP_IS_Pos (16UL) |
ADC1 IRQS_2: PP_CH0_UP_IS (Bit 16)
#define ADC1_IRQS_2_PP_CH2_LO_IS_Msk (0x4UL) |
ADC1 IRQS_2: PP_CH2_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH2_LO_IS_Pos (2UL) |
ADC1 IRQS_2: PP_CH2_LO_IS (Bit 2)
#define ADC1_IRQS_2_PP_CH2_UP_IS_Msk (0x40000UL) |
ADC1 IRQS_2: PP_CH2_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH2_UP_IS_Pos (18UL) |
ADC1 IRQS_2: PP_CH2_UP_IS (Bit 18)
#define ADC1_IRQS_2_PP_CH3_LO_IS_Msk (0x8UL) |
ADC1 IRQS_2: PP_CH3_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH3_LO_IS_Pos (3UL) |
ADC1 IRQS_2: PP_CH3_LO_IS (Bit 3)
#define ADC1_IRQS_2_PP_CH3_UP_IS_Msk (0x80000UL) |
ADC1 IRQS_2: PP_CH3_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH3_UP_IS_Pos (19UL) |
ADC1 IRQS_2: PP_CH3_UP_IS (Bit 19)
#define ADC1_IRQS_2_PP_CH4_LO_IS_Msk (0x10UL) |
ADC1 IRQS_2: PP_CH4_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH4_LO_IS_Pos (4UL) |
ADC1 IRQS_2: PP_CH4_LO_IS (Bit 4)
#define ADC1_IRQS_2_PP_CH4_UP_IS_Msk (0x100000UL) |
ADC1 IRQS_2: PP_CH4_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH4_UP_IS_Pos (20UL) |
ADC1 IRQS_2: PP_CH4_UP_IS (Bit 20)
#define ADC1_IRQS_2_PP_CH5_LO_IS_Msk (0x20UL) |
ADC1 IRQS_2: PP_CH5_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH5_LO_IS_Pos (5UL) |
ADC1 IRQS_2: PP_CH5_LO_IS (Bit 5)
#define ADC1_IRQS_2_PP_CH5_UP_IS_Msk (0x200000UL) |
ADC1 IRQS_2: PP_CH5_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH5_UP_IS_Pos (21UL) |
ADC1 IRQS_2: PP_CH5_UP_IS (Bit 21)
#define ADC1_IRQS_2_PP_CH6_LO_IS_Msk (0x40UL) |
ADC1 IRQS_2: PP_CH6_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH6_LO_IS_Pos (6UL) |
ADC1 IRQS_2: PP_CH6_LO_IS (Bit 6)
#define ADC1_IRQS_2_PP_CH6_UP_IS_Msk (0x400000UL) |
ADC1 IRQS_2: PP_CH6_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH6_UP_IS_Pos (22UL) |
ADC1 IRQS_2: PP_CH6_UP_IS (Bit 22)
#define ADC1_IRQS_2_PP_CH7_LO_IS_Msk (0x80UL) |
ADC1 IRQS_2: PP_CH7_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH7_LO_IS_Pos (7UL) |
ADC1 IRQS_2: PP_CH7_LO_IS (Bit 7)
#define ADC1_IRQS_2_PP_CH7_UP_IS_Msk (0x800000UL) |
ADC1 IRQS_2: PP_CH7_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_PP_CH7_UP_IS_Pos (23UL) |
ADC1 IRQS_2: PP_CH7_UP_IS (Bit 23)
#define ADC1_IRQS_2_VS_LO_IS_Msk (0x2UL) |
ADC1 IRQS_2: VS_LO_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_VS_LO_IS_Pos (1UL) |
ADC1 IRQS_2: VS_LO_IS (Bit 1)
#define ADC1_IRQS_2_VS_UP_IS_Msk (0x20000UL) |
ADC1 IRQS_2: VS_UP_IS (Bitfield-Mask: 0x01)
#define ADC1_IRQS_2_VS_UP_IS_Pos (17UL) |
ADC1 IRQS_2: VS_UP_IS (Bit 17)
#define ADC1_MAX_TIME_MAX_TIME_Msk (0xffUL) |
ADC1 MAX_TIME: MAX_TIME (Bitfield-Mask: 0xff)
#define ADC1_MAX_TIME_MAX_TIME_Pos (0UL) |
ADC1 MAX_TIME: MAX_TIME (Bit 0)
#define ADC1_MMODE0_7_MMODE_0_Msk (0x3UL) |
ADC1 MMODE0_7: MMODE_0 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_0_Pos (0UL) |
ADC1 MMODE0_7: MMODE_0 (Bit 0)
#define ADC1_MMODE0_7_MMODE_1_Msk (0xcUL) |
ADC1 MMODE0_7: MMODE_1 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_1_Pos (2UL) |
ADC1 MMODE0_7: MMODE_1 (Bit 2)
#define ADC1_MMODE0_7_MMODE_2_Msk (0x30UL) |
ADC1 MMODE0_7: MMODE_2 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_2_Pos (4UL) |
ADC1 MMODE0_7: MMODE_2 (Bit 4)
#define ADC1_MMODE0_7_MMODE_3_Msk (0xc0UL) |
ADC1 MMODE0_7: MMODE_3 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_3_Pos (6UL) |
ADC1 MMODE0_7: MMODE_3 (Bit 6)
#define ADC1_MMODE0_7_MMODE_4_Msk (0x300UL) |
ADC1 MMODE0_7: MMODE_4 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_4_Pos (8UL) |
ADC1 MMODE0_7: MMODE_4 (Bit 8)
#define ADC1_MMODE0_7_MMODE_5_Msk (0xc00UL) |
ADC1 MMODE0_7: MMODE_5 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_5_Pos (10UL) |
ADC1 MMODE0_7: MMODE_5 (Bit 10)
#define ADC1_MMODE0_7_MMODE_6_Msk (0x3000UL) |
ADC1 MMODE0_7: MMODE_6 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_6_Pos (12UL) |
ADC1 MMODE0_7: MMODE_6 (Bit 12)
#define ADC1_MMODE0_7_MMODE_7_Msk (0xc000UL) |
ADC1 MMODE0_7: MMODE_7 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_7_Pos (14UL) |
ADC1 MMODE0_7: MMODE_7 (Bit 14)
#define ADC1_MMODE0_7_MMODE_D1_Msk (0x3000000UL) |
ADC1 MMODE0_7: MMODE_D1 (Bitfield-Mask: 0x03)
#define ADC1_MMODE0_7_MMODE_D1_Pos (24UL) |
ADC1 MMODE0_7: MMODE_D1 (Bit 24)
#define ADC1_OFFSETCALIB_OFFSET_DAC_Msk (0x1f00UL) |
ADC1 OFFSETCALIB: OFFSET_DAC (Bitfield-Mask: 0x1f)
#define ADC1_OFFSETCALIB_OFFSET_DAC_Pos (8UL) |
ADC1 OFFSETCALIB: OFFSET_DAC (Bit 8)
#define ADC1_OFFSETCALIB_OFFSET_SHIFT_Msk (0x7UL) |
ADC1 OFFSETCALIB: OFFSET_SHIFT (Bitfield-Mask: 0x07)
#define ADC1_OFFSETCALIB_OFFSET_SHIFT_Pos (0UL) |
ADC1 OFFSETCALIB: OFFSET_SHIFT (Bit 0)
#define ADC1_PP_MAP0_3_EN_PP_MAP0_Msk (0x80UL) |
ADC1 PP_MAP0_3: EN_PP_MAP0 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_EN_PP_MAP0_Pos (7UL) |
ADC1 PP_MAP0_3: EN_PP_MAP0 (Bit 7)
#define ADC1_PP_MAP0_3_EN_PP_MAP1_Msk (0x8000UL) |
ADC1 PP_MAP0_3: EN_PP_MAP1 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_EN_PP_MAP1_Pos (15UL) |
ADC1 PP_MAP0_3: EN_PP_MAP1 (Bit 15)
#define ADC1_PP_MAP0_3_EN_PP_MAP2_Msk (0x800000UL) |
ADC1 PP_MAP0_3: EN_PP_MAP2 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_EN_PP_MAP2_Pos (23UL) |
ADC1 PP_MAP0_3: EN_PP_MAP2 (Bit 23)
#define ADC1_PP_MAP0_3_EN_PP_MAP3_Msk (0x80000000UL) |
ADC1 PP_MAP0_3: EN_PP_MAP3 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_EN_PP_MAP3_Pos (31UL) |
ADC1 PP_MAP0_3: EN_PP_MAP3 (Bit 31)
#define ADC1_PP_MAP0_3_PP_MAP2_Msk (0xf0000UL) |
ADC1 PP_MAP0_3: PP_MAP2 (Bitfield-Mask: 0x0f)
#define ADC1_PP_MAP0_3_PP_MAP2_Pos (16UL) |
ADC1 PP_MAP0_3: PP_MAP2 (Bit 16)
#define ADC1_PP_MAP0_3_PP_MAP3_Msk (0xf000000UL) |
ADC1 PP_MAP0_3: PP_MAP3 (Bitfield-Mask: 0x0f)
#define ADC1_PP_MAP0_3_PP_MAP3_Pos (24UL) |
ADC1 PP_MAP0_3: PP_MAP3 (Bit 24)
#define ADC1_PP_MAP0_3_RESET_PP_MAP0_Msk (0x40UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP0 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_RESET_PP_MAP0_Pos (6UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP0 (Bit 6)
#define ADC1_PP_MAP0_3_RESET_PP_MAP1_Msk (0x4000UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP1 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_RESET_PP_MAP1_Pos (14UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP1 (Bit 14)
#define ADC1_PP_MAP0_3_RESET_PP_MAP2_Msk (0x400000UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP2 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_RESET_PP_MAP2_Pos (22UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP2 (Bit 22)
#define ADC1_PP_MAP0_3_RESET_PP_MAP3_Msk (0x40000000UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP3 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP0_3_RESET_PP_MAP3_Pos (30UL) |
ADC1 PP_MAP0_3: RESET_PP_MAP3 (Bit 30)
#define ADC1_PP_MAP4_7_EN_PP_MAP4_Msk (0x80UL) |
ADC1 PP_MAP4_7: EN_PP_MAP4 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_EN_PP_MAP4_Pos (7UL) |
ADC1 PP_MAP4_7: EN_PP_MAP4 (Bit 7)
#define ADC1_PP_MAP4_7_EN_PP_MAP5_Msk (0x8000UL) |
ADC1 PP_MAP4_7: EN_PP_MAP5 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_EN_PP_MAP5_Pos (15UL) |
ADC1 PP_MAP4_7: EN_PP_MAP5 (Bit 15)
#define ADC1_PP_MAP4_7_EN_PP_MAP6_Msk (0x800000UL) |
ADC1 PP_MAP4_7: EN_PP_MAP6 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_EN_PP_MAP6_Pos (23UL) |
ADC1 PP_MAP4_7: EN_PP_MAP6 (Bit 23)
#define ADC1_PP_MAP4_7_EN_PP_MAP7_Msk (0x80000000UL) |
ADC1 PP_MAP4_7: EN_PP_MAP7 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_EN_PP_MAP7_Pos (31UL) |
ADC1 PP_MAP4_7: EN_PP_MAP7 (Bit 31)
#define ADC1_PP_MAP4_7_PP_MAP4_Msk (0xfUL) |
ADC1 PP_MAP4_7: PP_MAP4 (Bitfield-Mask: 0x0f)
#define ADC1_PP_MAP4_7_PP_MAP4_Pos (0UL) |
ADC1 PP_MAP4_7: PP_MAP4 (Bit 0)
#define ADC1_PP_MAP4_7_PP_MAP5_Msk (0xf00UL) |
ADC1 PP_MAP4_7: PP_MAP5 (Bitfield-Mask: 0x0f)
#define ADC1_PP_MAP4_7_PP_MAP5_Pos (8UL) |
ADC1 PP_MAP4_7: PP_MAP5 (Bit 8)
#define ADC1_PP_MAP4_7_PP_MAP6_Msk (0xf0000UL) |
ADC1 PP_MAP4_7: PP_MAP6 (Bitfield-Mask: 0x0f)
#define ADC1_PP_MAP4_7_PP_MAP6_Pos (16UL) |
ADC1 PP_MAP4_7: PP_MAP6 (Bit 16)
#define ADC1_PP_MAP4_7_PP_MAP7_Msk (0xf000000UL) |
ADC1 PP_MAP4_7: PP_MAP7 (Bitfield-Mask: 0x0f)
#define ADC1_PP_MAP4_7_PP_MAP7_Pos (24UL) |
ADC1 PP_MAP4_7: PP_MAP7 (Bit 24)
#define ADC1_PP_MAP4_7_RESET_PP_MAP4_Msk (0x40UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP4 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_RESET_PP_MAP4_Pos (6UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP4 (Bit 6)
#define ADC1_PP_MAP4_7_RESET_PP_MAP5_Msk (0x4000UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP5 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_RESET_PP_MAP5_Pos (14UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP5 (Bit 14)
#define ADC1_PP_MAP4_7_RESET_PP_MAP6_Msk (0x400000UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP6 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_RESET_PP_MAP6_Pos (22UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP6 (Bit 22)
#define ADC1_PP_MAP4_7_RESET_PP_MAP7_Msk (0x40000000UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP7 (Bitfield-Mask: 0x01)
#define ADC1_PP_MAP4_7_RESET_PP_MAP7_Pos (30UL) |
ADC1 PP_MAP4_7: RESET_PP_MAP7 (Bit 30)
#define ADC1_SQ0_1_SQ0_Msk (0x3fffUL) |
ADC1 SQ0_1: SQ0 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ0_1_SQ0_Pos (0UL) |
ADC1 SQ0_1: SQ0 (Bit 0)
#define ADC1_SQ0_1_SQ1_Msk (0x3fff0000UL) |
ADC1 SQ0_1: SQ1 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ0_1_SQ1_Pos (16UL) |
ADC1 SQ0_1: SQ1 (Bit 16)
#define ADC1_SQ10_11_SQ10_Msk (0x3fffUL) |
ADC1 SQ10_11: SQ10 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ10_11_SQ10_Pos (0UL) |
ADC1 SQ10_11: SQ10 (Bit 0)
#define ADC1_SQ10_11_SQ11_Msk (0x3fff0000UL) |
ADC1 SQ10_11: SQ11 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ10_11_SQ11_Pos (16UL) |
ADC1 SQ10_11: SQ11 (Bit 16)
#define ADC1_SQ12_13_SQ12_Msk (0x3fffUL) |
ADC1 SQ12_13: SQ12 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ12_13_SQ12_Pos (0UL) |
ADC1 SQ12_13: SQ12 (Bit 0)
#define ADC1_SQ12_13_SQ13_Msk (0x3fff0000UL) |
ADC1 SQ12_13: SQ13 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ12_13_SQ13_Pos (16UL) |
ADC1 SQ12_13: SQ13 (Bit 16)
#define ADC1_SQ2_3_SQ2_Msk (0x3fffUL) |
ADC1 SQ2_3: SQ2 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ2_3_SQ2_Pos (0UL) |
ADC1 SQ2_3: SQ2 (Bit 0)
#define ADC1_SQ2_3_SQ3_Msk (0x3fff0000UL) |
ADC1 SQ2_3: SQ3 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ2_3_SQ3_Pos (16UL) |
ADC1 SQ2_3: SQ3 (Bit 16)
#define ADC1_SQ4_5_SQ4_Msk (0x3fffUL) |
ADC1 SQ4_5: SQ4 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ4_5_SQ4_Pos (0UL) |
ADC1 SQ4_5: SQ4 (Bit 0)
#define ADC1_SQ4_5_SQ5_Msk (0x3fff0000UL) |
ADC1 SQ4_5: SQ5 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ4_5_SQ5_Pos (16UL) |
ADC1 SQ4_5: SQ5 (Bit 16)
#define ADC1_SQ6_7_SQ6_Msk (0x3fffUL) |
ADC1 SQ6_7: SQ6 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ6_7_SQ6_Pos (0UL) |
ADC1 SQ6_7: SQ6 (Bit 0)
#define ADC1_SQ6_7_SQ7_Msk (0x3fff0000UL) |
ADC1 SQ6_7: SQ7 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ6_7_SQ7_Pos (16UL) |
ADC1 SQ6_7: SQ7 (Bit 16)
#define ADC1_SQ8_9_SQ8_Msk (0x3fffUL) |
ADC1 SQ8_9: SQ8 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ8_9_SQ8_Pos (0UL) |
ADC1 SQ8_9: SQ8 (Bit 0)
#define ADC1_SQ8_9_SQ9_Msk (0x3fff0000UL) |
ADC1 SQ8_9: SQ9 (Bitfield-Mask: 0x3fff)
#define ADC1_SQ8_9_SQ9_Pos (16UL) |
ADC1 SQ8_9: SQ9 (Bit 16)
#define ADC1_SQ_CH_MAP_SQ_CH12_MAP_Msk (0x1000UL) |
ADC1 SQ_CH_MAP: SQ_CH12_MAP (Bitfield-Mask: 0x01)
#define ADC1_SQ_CH_MAP_SQ_CH12_MAP_Pos (12UL) |
ADC1 SQ_CH_MAP: SQ_CH12_MAP (Bit 12)
#define ADC1_SQ_CH_MAP_SQ_CH5_MAP_Msk (0x20UL) |
ADC1 SQ_CH_MAP: SQ_CH5_MAP (Bitfield-Mask: 0x01)
#define ADC1_SQ_CH_MAP_SQ_CH5_MAP_Pos (5UL) |
ADC1 SQ_CH_MAP: SQ_CH5_MAP (Bit 5)
#define ADC1_SQ_CH_MAP_SQ_CH6_MAP_Msk (0x40UL) |
ADC1 SQ_CH_MAP: SQ_CH6_MAP (Bitfield-Mask: 0x01)
#define ADC1_SQ_CH_MAP_SQ_CH6_MAP_Pos (6UL) |
ADC1 SQ_CH_MAP: SQ_CH6_MAP (Bit 6)
#define ADC1_SQ_FB_CHx_Msk (0xf0000UL) |
ADC1 SQ_FB: CHx (Bitfield-Mask: 0x0f)
#define ADC1_SQ_FB_CHx_Pos (16UL) |
ADC1 SQ_FB: CHx (Bit 16)
#define ADC1_SQ_FB_EIM_ACTIVE_Msk (0x200UL) |
ADC1 SQ_FB: EIM_ACTIVE (Bitfield-Mask: 0x01)
#define ADC1_SQ_FB_EIM_ACTIVE_Pos (9UL) |
ADC1 SQ_FB: EIM_ACTIVE (Bit 9)
#define ADC1_SQ_FB_ESM_ACTIVE_Msk (0x400UL) |
ADC1 SQ_FB: ESM_ACTIVE (Bitfield-Mask: 0x01)
#define ADC1_SQ_FB_ESM_ACTIVE_Pos (10UL) |
ADC1 SQ_FB: ESM_ACTIVE (Bit 10)
#define ADC1_SQ_FB_SQ_FB_Msk (0x1fUL) |
ADC1 SQ_FB: SQ_FB (Bitfield-Mask: 0x1f)
#define ADC1_SQ_FB_SQ_FB_Pos (0UL) |
ADC1 SQ_FB: SQ_FB (Bit 0)
#define ADC1_SQ_FB_SQ_STOP_Msk (0x100UL) |
ADC1 SQ_FB: SQ_STOP (Bitfield-Mask: 0x01)
#define ADC1_SQ_FB_SQ_STOP_Pos (8UL) |
ADC1 SQ_FB: SQ_STOP (Bit 8)
#define ADC1_SQ_FB_SQx_Msk (0x7800UL) |
ADC1 SQ_FB: SQx (Bitfield-Mask: 0x0f)
#define ADC1_SQ_FB_SQx_Pos (11UL) |
ADC1 SQ_FB: SQx (Bit 11)
#define ADC1_STATUS_DAC_IN_Msk (0x7UL) |
ADC1 STATUS: DAC_IN (Bitfield-Mask: 0x07)
#define ADC1_STATUS_DAC_IN_Pos (0UL) |
ADC1 STATUS: DAC_IN (Bit 0)
#define ADC1_STATUS_SD_FEEDB_ON_Msk (0x80000000UL) |
ADC1 STATUS: SD_FEEDB_ON (Bitfield-Mask: 0x01)
#define ADC1_STATUS_SD_FEEDB_ON_Pos (31UL) |
ADC1 STATUS: SD_FEEDB_ON (Bit 31)
#define ADC1_STATUS_SOC_JITTER_Msk (0x30000UL) |
ADC1 STATUS: SOC_JITTER (Bitfield-Mask: 0x03)
#define ADC1_STATUS_SOC_JITTER_Pos (16UL) |
ADC1 STATUS: SOC_JITTER (Bit 16)
#define ADC1_STS_1_DU1LO_STS_Msk (0x1000000UL) |
ADC1 STS_1: DU1LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_1_DU1LO_STS_Pos (24UL) |
ADC1 STS_1: DU1LO_STS (Bit 24)
#define ADC1_STS_1_DU1UP_STS_Msk (0x2000000UL) |
ADC1 STS_1: DU1UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_1_DU1UP_STS_Pos (25UL) |
ADC1 STS_1: DU1UP_STS (Bit 25)
#define ADC1_STS_2_PP_CH0_LO_STS_Msk (0x1UL) |
ADC1 STS_2: PP_CH0_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH0_LO_STS_Pos (0UL) |
ADC1 STS_2: PP_CH0_LO_STS (Bit 0)
#define ADC1_STS_2_PP_CH0_UP_STS_Msk (0x10000UL) |
ADC1 STS_2: PP_CH0_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH0_UP_STS_Pos (16UL) |
ADC1 STS_2: PP_CH0_UP_STS (Bit 16)
#define ADC1_STS_2_PP_CH2_LO_STS_Msk (0x4UL) |
ADC1 STS_2: PP_CH2_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH2_LO_STS_Pos (2UL) |
ADC1 STS_2: PP_CH2_LO_STS (Bit 2)
#define ADC1_STS_2_PP_CH2_UP_STS_Msk (0x40000UL) |
ADC1 STS_2: PP_CH2_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH2_UP_STS_Pos (18UL) |
ADC1 STS_2: PP_CH2_UP_STS (Bit 18)
#define ADC1_STS_2_PP_CH3_LO_STS_Msk (0x8UL) |
ADC1 STS_2: PP_CH3_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH3_LO_STS_Pos (3UL) |
ADC1 STS_2: PP_CH3_LO_STS (Bit 3)
#define ADC1_STS_2_PP_CH3_UP_STS_Msk (0x80000UL) |
ADC1 STS_2: PP_CH3_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH3_UP_STS_Pos (19UL) |
ADC1 STS_2: PP_CH3_UP_STS (Bit 19)
#define ADC1_STS_2_PP_CH4_LO_STS_Msk (0x10UL) |
ADC1 STS_2: PP_CH4_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH4_LO_STS_Pos (4UL) |
ADC1 STS_2: PP_CH4_LO_STS (Bit 4)
#define ADC1_STS_2_PP_CH4_UP_STS_Msk (0x100000UL) |
ADC1 STS_2: PP_CH4_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH4_UP_STS_Pos (20UL) |
ADC1 STS_2: PP_CH4_UP_STS (Bit 20)
#define ADC1_STS_2_PP_CH5_LO_STS_Msk (0x20UL) |
ADC1 STS_2: PP_CH5_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH5_LO_STS_Pos (5UL) |
ADC1 STS_2: PP_CH5_LO_STS (Bit 5)
#define ADC1_STS_2_PP_CH5_UP_STS_Msk (0x200000UL) |
ADC1 STS_2: PP_CH5_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH5_UP_STS_Pos (21UL) |
ADC1 STS_2: PP_CH5_UP_STS (Bit 21)
#define ADC1_STS_2_PP_CH6_LO_STS_Msk (0x40UL) |
ADC1 STS_2: PP_CH6_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH6_LO_STS_Pos (6UL) |
ADC1 STS_2: PP_CH6_LO_STS (Bit 6)
#define ADC1_STS_2_PP_CH6_UP_STS_Msk (0x400000UL) |
ADC1 STS_2: PP_CH6_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH6_UP_STS_Pos (22UL) |
ADC1 STS_2: PP_CH6_UP_STS (Bit 22)
#define ADC1_STS_2_PP_CH7_LO_STS_Msk (0x80UL) |
ADC1 STS_2: PP_CH7_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH7_LO_STS_Pos (7UL) |
ADC1 STS_2: PP_CH7_LO_STS (Bit 7)
#define ADC1_STS_2_PP_CH7_UP_STS_Msk (0x800000UL) |
ADC1 STS_2: PP_CH7_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_PP_CH7_UP_STS_Pos (23UL) |
ADC1 STS_2: PP_CH7_UP_STS (Bit 23)
#define ADC1_STS_2_VS_LO_STS_Msk (0x2UL) |
ADC1 STS_2: VS_LO_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_VS_LO_STS_Pos (1UL) |
ADC1 STS_2: VS_LO_STS (Bit 1)
#define ADC1_STS_2_VS_UP_STS_Msk (0x20000UL) |
ADC1 STS_2: VS_UP_STS (Bitfield-Mask: 0x01)
#define ADC1_STS_2_VS_UP_STS_Pos (17UL) |
ADC1 STS_2: VS_UP_STS (Bit 17)
#define ADC1_STSCLR_1_DU1LO_SC_Msk (0x1000000UL) |
ADC1 STSCLR_1: DU1LO_SC (Bitfield-Mask: 0x01)
#define ADC1_STSCLR_1_DU1LO_SC_Pos (24UL) |
ADC1 STSCLR_1: DU1LO_SC (Bit 24)
#define ADC1_STSCLR_1_DU1UP_SC_Msk (0x2000000UL) |
ADC1 STSCLR_1: DU1UP_SC (Bitfield-Mask: 0x01)
#define ADC1_STSCLR_1_DU1UP_SC_Pos (25UL) |
ADC1 STSCLR_1: DU1UP_SC (Bit 25)
#define ADC1_TH0_3_LOWER_PP_CH0_LOW_Msk (0xffUL) |
ADC1 TH0_3_LOWER: PP_CH0_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_LOWER_PP_CH0_LOW_Pos (0UL) |
ADC1 TH0_3_LOWER: PP_CH0_LOW (Bit 0)
#define ADC1_TH0_3_LOWER_PP_CH1_LOW_Msk (0xff00UL) |
ADC1 TH0_3_LOWER: PP_CH1_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_LOWER_PP_CH1_LOW_Pos (8UL) |
ADC1 TH0_3_LOWER: PP_CH1_LOW (Bit 8)
#define ADC1_TH0_3_LOWER_PP_CH2_LOW_Msk (0xff0000UL) |
ADC1 TH0_3_LOWER: PP_CH2_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_LOWER_PP_CH2_LOW_Pos (16UL) |
ADC1 TH0_3_LOWER: PP_CH2_LOW (Bit 16)
#define ADC1_TH0_3_LOWER_PP_CH3_LOW_Msk (0xff000000UL) |
ADC1 TH0_3_LOWER: PP_CH3_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_LOWER_PP_CH3_LOW_Pos (24UL) |
ADC1 TH0_3_LOWER: PP_CH3_LOW (Bit 24)
#define ADC1_TH0_3_UPPER_PP_CH0_UP_Msk (0xffUL) |
ADC1 TH0_3_UPPER: PP_CH0_UP (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_UPPER_PP_CH0_UP_Pos (0UL) |
ADC1 TH0_3_UPPER: PP_CH0_UP (Bit 0)
#define ADC1_TH0_3_UPPER_PP_CH1_UP_Msk (0xff00UL) |
ADC1 TH0_3_UPPER: PP_CH1_UP (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_UPPER_PP_CH1_UP_Pos (8UL) |
ADC1 TH0_3_UPPER: PP_CH1_UP (Bit 8)
#define ADC1_TH0_3_UPPER_PP_CH2_UP_Msk (0xff0000UL) |
ADC1 TH0_3_UPPER: PP_CH2_UP (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_UPPER_PP_CH2_UP_Pos (16UL) |
ADC1 TH0_3_UPPER: PP_CH2_UP (Bit 16)
#define ADC1_TH0_3_UPPER_PP_CH3_UP_Msk (0xff000000UL) |
ADC1 TH0_3_UPPER: PP_CH3_UP (Bitfield-Mask: 0xff)
#define ADC1_TH0_3_UPPER_PP_CH3_UP_Pos (24UL) |
ADC1 TH0_3_UPPER: PP_CH3_UP (Bit 24)
#define ADC1_TH4_7_LOWER_PP_CH4_LOW_Msk (0xffUL) |
ADC1 TH4_7_LOWER: PP_CH4_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_LOWER_PP_CH4_LOW_Pos (0UL) |
ADC1 TH4_7_LOWER: PP_CH4_LOW (Bit 0)
#define ADC1_TH4_7_LOWER_PP_CH5_LOW_Msk (0xff00UL) |
ADC1 TH4_7_LOWER: PP_CH5_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_LOWER_PP_CH5_LOW_Pos (8UL) |
ADC1 TH4_7_LOWER: PP_CH5_LOW (Bit 8)
#define ADC1_TH4_7_LOWER_PP_CH6_LOW_Msk (0xff0000UL) |
ADC1 TH4_7_LOWER: PP_CH6_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_LOWER_PP_CH6_LOW_Pos (16UL) |
ADC1 TH4_7_LOWER: PP_CH6_LOW (Bit 16)
#define ADC1_TH4_7_LOWER_PP_CH7_LOW_Msk (0xff000000UL) |
ADC1 TH4_7_LOWER: PP_CH7_LOW (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_LOWER_PP_CH7_LOW_Pos (24UL) |
ADC1 TH4_7_LOWER: PP_CH7_LOW (Bit 24)
#define ADC1_TH4_7_UPPER_PP_CH4_UP_Msk (0xffUL) |
ADC1 TH4_7_UPPER: PP_CH4_UP (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_UPPER_PP_CH4_UP_Pos (0UL) |
ADC1 TH4_7_UPPER: PP_CH4_UP (Bit 0)
#define ADC1_TH4_7_UPPER_PP_CH5_UP_Msk (0xff00UL) |
ADC1 TH4_7_UPPER: PP_CH5_UP (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_UPPER_PP_CH5_UP_Pos (8UL) |
ADC1 TH4_7_UPPER: PP_CH5_UP (Bit 8)
#define ADC1_TH4_7_UPPER_PP_CH6_UP_Msk (0xff0000UL) |
ADC1 TH4_7_UPPER: PP_CH6_UP (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_UPPER_PP_CH6_UP_Pos (16UL) |
ADC1 TH4_7_UPPER: PP_CH6_UP (Bit 16)
#define ADC1_TH4_7_UPPER_PP_CH7_UP_Msk (0xff000000UL) |
ADC1 TH4_7_UPPER: PP_CH7_UP (Bitfield-Mask: 0xff)
#define ADC1_TH4_7_UPPER_PP_CH7_UP_Pos (24UL) |
ADC1 TH4_7_UPPER: PP_CH7_UP (Bit 24)
#define ADC2_CAL_CH0_1_GAIN_CH0_Msk (0xff00UL) |
ADC2 CAL_CH0_1: GAIN_CH0 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH0_1_GAIN_CH0_Pos (8UL) |
ADC2 CAL_CH0_1: GAIN_CH0 (Bit 8)
#define ADC2_CAL_CH0_1_GAIN_CH1_Msk (0xff000000UL) |
ADC2 CAL_CH0_1: GAIN_CH1 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH0_1_GAIN_CH1_Pos (24UL) |
ADC2 CAL_CH0_1: GAIN_CH1 (Bit 24)
#define ADC2_CAL_CH0_1_OFFS_CH0_Msk (0x1fUL) |
ADC2 CAL_CH0_1: OFFS_CH0 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH0_1_OFFS_CH0_Pos (0UL) |
ADC2 CAL_CH0_1: OFFS_CH0 (Bit 0)
#define ADC2_CAL_CH0_1_OFFS_CH1_Msk (0x1f0000UL) |
ADC2 CAL_CH0_1: OFFS_CH1 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH0_1_OFFS_CH1_Pos (16UL) |
ADC2 CAL_CH0_1: OFFS_CH1 (Bit 16)
#define ADC2_CAL_CH2_3_GAIN_CH2_Msk (0xff00UL) |
ADC2 CAL_CH2_3: GAIN_CH2 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH2_3_GAIN_CH2_Pos (8UL) |
ADC2 CAL_CH2_3: GAIN_CH2 (Bit 8)
#define ADC2_CAL_CH2_3_GAIN_CH3_Msk (0xff000000UL) |
ADC2 CAL_CH2_3: GAIN_CH3 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH2_3_GAIN_CH3_Pos (24UL) |
ADC2 CAL_CH2_3: GAIN_CH3 (Bit 24)
#define ADC2_CAL_CH2_3_OFFS_CH2_Msk (0x1fUL) |
ADC2 CAL_CH2_3: OFFS_CH2 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH2_3_OFFS_CH2_Pos (0UL) |
ADC2 CAL_CH2_3: OFFS_CH2 (Bit 0)
#define ADC2_CAL_CH2_3_OFFS_CH3_Msk (0x1f0000UL) |
ADC2 CAL_CH2_3: OFFS_CH3 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH2_3_OFFS_CH3_Pos (16UL) |
ADC2 CAL_CH2_3: OFFS_CH3 (Bit 16)
#define ADC2_CAL_CH4_5_GAIN_CH4_Msk (0xff00UL) |
ADC2 CAL_CH4_5: GAIN_CH4 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH4_5_GAIN_CH4_Pos (8UL) |
ADC2 CAL_CH4_5: GAIN_CH4 (Bit 8)
#define ADC2_CAL_CH4_5_GAIN_CH5_Msk (0xff000000UL) |
ADC2 CAL_CH4_5: GAIN_CH5 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH4_5_GAIN_CH5_Pos (24UL) |
ADC2 CAL_CH4_5: GAIN_CH5 (Bit 24)
#define ADC2_CAL_CH4_5_OFFS_CH4_Msk (0x1fUL) |
ADC2 CAL_CH4_5: OFFS_CH4 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH4_5_OFFS_CH4_Pos (0UL) |
ADC2 CAL_CH4_5: OFFS_CH4 (Bit 0)
#define ADC2_CAL_CH4_5_OFFS_CH5_Msk (0x1f0000UL) |
ADC2 CAL_CH4_5: OFFS_CH5 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH4_5_OFFS_CH5_Pos (16UL) |
ADC2 CAL_CH4_5: OFFS_CH5 (Bit 16)
#define ADC2_CAL_CH6_7_GAIN_CH6_Msk (0xff00UL) |
ADC2 CAL_CH6_7: GAIN_CH6 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH6_7_GAIN_CH6_Pos (8UL) |
ADC2 CAL_CH6_7: GAIN_CH6 (Bit 8)
#define ADC2_CAL_CH6_7_GAIN_CH7_Msk (0xff000000UL) |
ADC2 CAL_CH6_7: GAIN_CH7 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH6_7_GAIN_CH7_Pos (24UL) |
ADC2 CAL_CH6_7: GAIN_CH7 (Bit 24)
#define ADC2_CAL_CH6_7_OFFS_CH6_Msk (0x1fUL) |
ADC2 CAL_CH6_7: OFFS_CH6 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH6_7_OFFS_CH6_Pos (0UL) |
ADC2 CAL_CH6_7: OFFS_CH6 (Bit 0)
#define ADC2_CAL_CH6_7_OFFS_CH7_Msk (0x1f0000UL) |
ADC2 CAL_CH6_7: OFFS_CH7 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH6_7_OFFS_CH7_Pos (16UL) |
ADC2 CAL_CH6_7: OFFS_CH7 (Bit 16)
#define ADC2_CAL_CH8_9_GAIN_CH8_Msk (0xff00UL) |
ADC2 CAL_CH8_9: GAIN_CH8 (Bitfield-Mask: 0xff)
#define ADC2_CAL_CH8_9_GAIN_CH8_Pos (8UL) |
ADC2 CAL_CH8_9: GAIN_CH8 (Bit 8)
#define ADC2_CAL_CH8_9_OFFS_CH8_Msk (0x1fUL) |
ADC2 CAL_CH8_9: OFFS_CH8 (Bitfield-Mask: 0x1f)
#define ADC2_CAL_CH8_9_OFFS_CH8_Pos (0UL) |
ADC2 CAL_CH8_9: OFFS_CH8 (Bit 0)
#define ADC2_CHx_EIM_CHx_SEL_Msk (0xfUL) |
ADC2 CHx_EIM: CHx_SEL (Bitfield-Mask: 0x0f)
#define ADC2_CHx_EIM_CHx_SEL_Pos (0UL) |
ADC2 CHx_EIM: CHx_SEL (Bit 0)
#define ADC2_CHx_EIM_EN_Msk (0x800UL) |
ADC2 CHx_EIM: EN (Bitfield-Mask: 0x01)
#define ADC2_CHx_EIM_EN_Pos (11UL) |
ADC2 CHx_EIM: EN (Bit 11)
#define ADC2_CHx_EIM_REP_Msk (0x700UL) |
ADC2 CHx_EIM: REP (Bitfield-Mask: 0x07)
#define ADC2_CHx_EIM_REP_Pos (8UL) |
ADC2 CHx_EIM: REP (Bit 8)
#define ADC2_CHx_EIM_SEL_Msk (0x1000UL) |
ADC2 CHx_EIM: SEL (Bitfield-Mask: 0x01)
#define ADC2_CHx_EIM_SEL_Pos (12UL) |
ADC2 CHx_EIM: SEL (Bit 12)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Msk (0x3UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH0 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Pos (0UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH0 (Bit 0)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Msk (0x300UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH1 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Pos (8UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH1 (Bit 8)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Msk (0x30000UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH2 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Pos (16UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH2 (Bit 16)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Msk (0x3000000UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH3 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Pos (24UL) |
ADC2 CNT0_3_LOWER: CNT_LO_CH3 (Bit 24)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Msk (0x18UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH0 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Pos (3UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH0 (Bit 3)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Msk (0x1800UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH1 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Pos (11UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH1 (Bit 11)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Msk (0x180000UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH2 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Pos (19UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH2 (Bit 19)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Msk (0x18000000UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH3 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Pos (27UL) |
ADC2 CNT0_3_LOWER: HYST_LO_CH3 (Bit 27)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Msk (0x3UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH0 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Pos (0UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH0 (Bit 0)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Msk (0x300UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH1 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Pos (8UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH1 (Bit 8)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Msk (0x30000UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH2 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Pos (16UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH2 (Bit 16)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Msk (0x3000000UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH3 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Pos (24UL) |
ADC2 CNT0_3_UPPER: CNT_UP_CH3 (Bit 24)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Msk (0x18UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH0 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Pos (3UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH0 (Bit 3)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Msk (0x1800UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH1 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Pos (11UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH1 (Bit 11)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Msk (0x180000UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH2 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Pos (19UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH2 (Bit 19)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Msk (0x18000000UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH3 (Bitfield-Mask: 0x03)
#define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Pos (27UL) |
ADC2 CNT0_3_UPPER: HYST_UP_CH3 (Bit 27)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH4_Msk (0x3UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH4 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH4_Pos (0UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH4 (Bit 0)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH5_Msk (0x300UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH5 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH5_Pos (8UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH5 (Bit 8)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH6_Msk (0x30000UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH6 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH6_Pos (16UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH6 (Bit 16)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH7_Msk (0x3000000UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH7 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_CNT_LO_CH7_Pos (24UL) |
ADC2 CNT4_7_LOWER: CNT_LO_CH7 (Bit 24)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH4_Msk (0x18UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH4 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH4_Pos (3UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH4 (Bit 3)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH5_Msk (0x1800UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH5 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH5_Pos (11UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH5 (Bit 11)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH6_Msk (0x180000UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH6 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH6_Pos (19UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH6 (Bit 19)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH7_Msk (0x18000000UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH7 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_LOWER_HYST_LO_CH7_Pos (27UL) |
ADC2 CNT4_7_LOWER: HYST_LO_CH7 (Bit 27)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH4_Msk (0x3UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH4 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH4_Pos (0UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH4 (Bit 0)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH5_Msk (0x300UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH5 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH5_Pos (8UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH5 (Bit 8)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH6_Msk (0x30000UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH6 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH6_Pos (16UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH6 (Bit 16)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH7_Msk (0x3000000UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH7 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_CNT_UP_CH7_Pos (24UL) |
ADC2 CNT4_7_UPPER: CNT_UP_CH7 (Bit 24)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH4_Msk (0x18UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH4 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH4_Pos (3UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH4 (Bit 3)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH5_Msk (0x1800UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH5 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH5_Pos (11UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH5 (Bit 11)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH6_Msk (0x180000UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH6 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH6_Pos (19UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH6 (Bit 19)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH7_Msk (0x18000000UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH7 (Bitfield-Mask: 0x03)
#define ADC2_CNT4_7_UPPER_HYST_UP_CH7_Pos (27UL) |
ADC2 CNT4_7_UPPER: HYST_UP_CH7 (Bit 27)
#define ADC2_CNT8_11_LOWER_CNT_LO_CH8_Msk (0x3UL) |
ADC2 CNT8_11_LOWER: CNT_LO_CH8 (Bitfield-Mask: 0x03)
#define ADC2_CNT8_11_LOWER_CNT_LO_CH8_Pos (0UL) |
ADC2 CNT8_11_LOWER: CNT_LO_CH8 (Bit 0)
#define ADC2_CNT8_11_LOWER_HYST_LO_CH8_Msk (0x18UL) |
ADC2 CNT8_11_LOWER: HYST_LO_CH8 (Bitfield-Mask: 0x03)
#define ADC2_CNT8_11_LOWER_HYST_LO_CH8_Pos (3UL) |
ADC2 CNT8_11_LOWER: HYST_LO_CH8 (Bit 3)
#define ADC2_CNT8_11_UPPER_CNT_UP_CH8_Msk (0x3UL) |
ADC2 CNT8_11_UPPER: CNT_UP_CH8 (Bitfield-Mask: 0x03)
#define ADC2_CNT8_11_UPPER_CNT_UP_CH8_Pos (0UL) |
ADC2 CNT8_11_UPPER: CNT_UP_CH8 (Bit 0)
#define ADC2_CNT8_11_UPPER_HYST_UP_CH8_Msk (0x18UL) |
ADC2 CNT8_11_UPPER: HYST_UP_CH8 (Bitfield-Mask: 0x03)
#define ADC2_CNT8_11_UPPER_HYST_UP_CH8_Pos (3UL) |
ADC2 CNT8_11_UPPER: HYST_UP_CH8 (Bit 3)
#define ADC2_CTRL1_CALIB_EN_8_0_Msk (0x1ffUL) |
ADC2 CTRL1: CALIB_EN_8_0 (Bitfield-Mask: 0x1ff)
#define ADC2_CTRL1_CALIB_EN_8_0_Pos (0UL) |
ADC2 CTRL1: CALIB_EN_8_0 (Bit 0)
#define ADC2_CTRL2_MCM_PD_N_Msk (0x1UL) |
ADC2 CTRL2: MCM_PD_N (Bitfield-Mask: 0x01)
#define ADC2_CTRL2_MCM_PD_N_Pos (0UL) |
ADC2 CTRL2: MCM_PD_N (Bit 0)
#define ADC2_CTRL2_MCM_RDY_Msk (0x80UL) |
ADC2 CTRL2: MCM_RDY (Bitfield-Mask: 0x01)
#define ADC2_CTRL2_MCM_RDY_Pos (7UL) |
ADC2 CTRL2: MCM_RDY (Bit 7)
#define ADC2_CTRL2_SAMPLE_TIME_int_Msk (0xf00UL) |
ADC2 CTRL2: SAMPLE_TIME_int (Bitfield-Mask: 0x0f)
#define ADC2_CTRL2_SAMPLE_TIME_int_Pos (8UL) |
ADC2 CTRL2: SAMPLE_TIME_int (Bit 8)
#define ADC2_CTRL4_FILT_OUT_SEL_8_0_Msk (0x1ffUL) |
ADC2 CTRL4: FILT_OUT_SEL_8_0 (Bitfield-Mask: 0x1ff)
#define ADC2_CTRL4_FILT_OUT_SEL_8_0_Pos (0UL) |
ADC2 CTRL4: FILT_OUT_SEL_8_0 (Bit 0)
#define ADC2_CTRL_STS_EOC_Msk (0x8UL) |
ADC2 CTRL_STS: EOC (Bitfield-Mask: 0x01)
#define ADC2_CTRL_STS_EOC_Pos (3UL) |
ADC2 CTRL_STS: EOC (Bit 3)
#define ADC2_CTRL_STS_IN_MUX_SEL_Msk (0xf00UL) |
ADC2 CTRL_STS: IN_MUX_SEL (Bitfield-Mask: 0x0f)
#define ADC2_CTRL_STS_IN_MUX_SEL_Pos (8UL) |
ADC2 CTRL_STS: IN_MUX_SEL (Bit 8)
#define ADC2_CTRL_STS_PD_N_Msk (0x1UL) |
ADC2 CTRL_STS: PD_N (Bitfield-Mask: 0x01)
#define ADC2_CTRL_STS_PD_N_Pos (0UL) |
ADC2 CTRL_STS: PD_N (Bit 0)
#define ADC2_CTRL_STS_SOS_Msk (0x4UL) |
ADC2 CTRL_STS: SOS (Bitfield-Mask: 0x01)
#define ADC2_CTRL_STS_SOS_Pos (2UL) |
ADC2 CTRL_STS: SOS (Bit 2)
#define ADC2_FILT_OUT0_OUT_CH0_Msk (0x3ffUL) |
ADC2 FILT_OUT0: OUT_CH0 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT0_OUT_CH0_Pos (0UL) |
ADC2 FILT_OUT0: OUT_CH0 (Bit 0)
#define ADC2_FILT_OUT1_OUT_CH1_Msk (0x3ffUL) |
ADC2 FILT_OUT1: OUT_CH1 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT1_OUT_CH1_Pos (0UL) |
ADC2 FILT_OUT1: OUT_CH1 (Bit 0)
#define ADC2_FILT_OUT2_OUT_CH2_Msk (0x3ffUL) |
ADC2 FILT_OUT2: OUT_CH2 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT2_OUT_CH2_Pos (0UL) |
ADC2 FILT_OUT2: OUT_CH2 (Bit 0)
#define ADC2_FILT_OUT3_OUT_CH3_Msk (0x3ffUL) |
ADC2 FILT_OUT3: OUT_CH3 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT3_OUT_CH3_Pos (0UL) |
ADC2 FILT_OUT3: OUT_CH3 (Bit 0)
#define ADC2_FILT_OUT4_OUT_CH4_Msk (0x3ffUL) |
ADC2 FILT_OUT4: OUT_CH4 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT4_OUT_CH4_Pos (0UL) |
ADC2 FILT_OUT4: OUT_CH4 (Bit 0)
#define ADC2_FILT_OUT5_OUT_CH5_Msk (0x3ffUL) |
ADC2 FILT_OUT5: OUT_CH5 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT5_OUT_CH5_Pos (0UL) |
ADC2 FILT_OUT5: OUT_CH5 (Bit 0)
#define ADC2_FILT_OUT6_OUT_CH6_Msk (0x3ffUL) |
ADC2 FILT_OUT6: OUT_CH6 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT6_OUT_CH6_Pos (0UL) |
ADC2 FILT_OUT6: OUT_CH6 (Bit 0)
#define ADC2_FILT_OUT7_OUT_CH7_Msk (0x3ffUL) |
ADC2 FILT_OUT7: OUT_CH7 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT7_OUT_CH7_Pos (0UL) |
ADC2 FILT_OUT7: OUT_CH7 (Bit 0)
#define ADC2_FILT_OUT8_OUT_CH8_Msk (0x3ffUL) |
ADC2 FILT_OUT8: OUT_CH8 (Bitfield-Mask: 0x3ff)
#define ADC2_FILT_OUT8_OUT_CH8_Pos (0UL) |
ADC2 FILT_OUT8: OUT_CH8 (Bit 0)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch0_Msk (0x1UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch0 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch0_Pos (0UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch0 (Bit 0)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch1_Msk (0x2UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch1 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch1_Pos (1UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch1 (Bit 1)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch2_Msk (0x4UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch2 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch2_Pos (2UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch2 (Bit 2)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch3_Msk (0x8UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch3 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch3_Pos (3UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch3 (Bit 3)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch4_Msk (0x10UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch4 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch4_Pos (4UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch4 (Bit 4)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch5_Msk (0x20UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch5 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch5_Pos (5UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch5 (Bit 5)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch6_Msk (0x40UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch6 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch6_Pos (6UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch6 (Bit 6)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch7_Msk (0x80UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch7 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch7_Pos (7UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch7 (Bit 7)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch8_Msk (0x100UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch8 (Bitfield-Mask: 0x01)
#define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch8_Pos (8UL) |
ADC2 FILT_UPLO_CTRL: UPLOEN_Ch8 (Bit 8)
#define ADC2_FILTCOEFF0_8_A_CH0_Msk (0x3UL) |
ADC2 FILTCOEFF0_8: A_CH0 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH0_Pos (0UL) |
ADC2 FILTCOEFF0_8: A_CH0 (Bit 0)
#define ADC2_FILTCOEFF0_8_A_CH1_Msk (0xcUL) |
ADC2 FILTCOEFF0_8: A_CH1 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH1_Pos (2UL) |
ADC2 FILTCOEFF0_8: A_CH1 (Bit 2)
#define ADC2_FILTCOEFF0_8_A_CH2_Msk (0x30UL) |
ADC2 FILTCOEFF0_8: A_CH2 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH2_Pos (4UL) |
ADC2 FILTCOEFF0_8: A_CH2 (Bit 4)
#define ADC2_FILTCOEFF0_8_A_CH3_Msk (0xc0UL) |
ADC2 FILTCOEFF0_8: A_CH3 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH3_Pos (6UL) |
ADC2 FILTCOEFF0_8: A_CH3 (Bit 6)
#define ADC2_FILTCOEFF0_8_A_CH4_Msk (0x300UL) |
ADC2 FILTCOEFF0_8: A_CH4 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH4_Pos (8UL) |
ADC2 FILTCOEFF0_8: A_CH4 (Bit 8)
#define ADC2_FILTCOEFF0_8_A_CH5_Msk (0xc00UL) |
ADC2 FILTCOEFF0_8: A_CH5 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH5_Pos (10UL) |
ADC2 FILTCOEFF0_8: A_CH5 (Bit 10)
#define ADC2_FILTCOEFF0_8_A_CH6_Msk (0x3000UL) |
ADC2 FILTCOEFF0_8: A_CH6 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH6_Pos (12UL) |
ADC2 FILTCOEFF0_8: A_CH6 (Bit 12)
#define ADC2_FILTCOEFF0_8_A_CH7_Msk (0xc000UL) |
ADC2 FILTCOEFF0_8: A_CH7 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH7_Pos (14UL) |
ADC2 FILTCOEFF0_8: A_CH7 (Bit 14)
#define ADC2_FILTCOEFF0_8_A_CH8_Msk (0x30000UL) |
ADC2 FILTCOEFF0_8: A_CH8 (Bitfield-Mask: 0x03)
#define ADC2_FILTCOEFF0_8_A_CH8_Pos (16UL) |
ADC2 FILTCOEFF0_8: A_CH8 (Bit 16)
#define ADC2_MAX_TIME_MAX_TIME_Msk (0xffUL) |
ADC2 MAX_TIME: MAX_TIME (Bitfield-Mask: 0xff)
#define ADC2_MAX_TIME_MAX_TIME_Pos (0UL) |
ADC2 MAX_TIME: MAX_TIME (Bit 0)
#define ADC2_MMODE0_8_MSEL_Ch0_Msk (0x3UL) |
ADC2 MMODE0_8: MSEL_Ch0 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch0_Pos (0UL) |
ADC2 MMODE0_8: MSEL_Ch0 (Bit 0)
#define ADC2_MMODE0_8_MSEL_Ch1_Msk (0xcUL) |
ADC2 MMODE0_8: MSEL_Ch1 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch1_Pos (2UL) |
ADC2 MMODE0_8: MSEL_Ch1 (Bit 2)
#define ADC2_MMODE0_8_MSEL_Ch2_Msk (0x30UL) |
ADC2 MMODE0_8: MSEL_Ch2 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch2_Pos (4UL) |
ADC2 MMODE0_8: MSEL_Ch2 (Bit 4)
#define ADC2_MMODE0_8_MSEL_Ch3_Msk (0xc0UL) |
ADC2 MMODE0_8: MSEL_Ch3 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch3_Pos (6UL) |
ADC2 MMODE0_8: MSEL_Ch3 (Bit 6)
#define ADC2_MMODE0_8_MSEL_Ch4_Msk (0x300UL) |
ADC2 MMODE0_8: MSEL_Ch4 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch4_Pos (8UL) |
ADC2 MMODE0_8: MSEL_Ch4 (Bit 8)
#define ADC2_MMODE0_8_MSEL_Ch5_Msk (0xc00UL) |
ADC2 MMODE0_8: MSEL_Ch5 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch5_Pos (10UL) |
ADC2 MMODE0_8: MSEL_Ch5 (Bit 10)
#define ADC2_MMODE0_8_MSEL_Ch6_Msk (0x3000UL) |
ADC2 MMODE0_8: MSEL_Ch6 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch6_Pos (12UL) |
ADC2 MMODE0_8: MSEL_Ch6 (Bit 12)
#define ADC2_MMODE0_8_MSEL_Ch7_Msk (0xc000UL) |
ADC2 MMODE0_8: MSEL_Ch7 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch7_Pos (14UL) |
ADC2 MMODE0_8: MSEL_Ch7 (Bit 14)
#define ADC2_MMODE0_8_MSEL_Ch8_Msk (0x30000UL) |
ADC2 MMODE0_8: MSEL_Ch8 (Bitfield-Mask: 0x03)
#define ADC2_MMODE0_8_MSEL_Ch8_Pos (16UL) |
ADC2 MMODE0_8: MSEL_Ch8 (Bit 16)
#define ADC2_SQ0_1_SQ0_Msk (0x1ffUL) |
ADC2 SQ0_1: SQ0 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ0_1_SQ0_Pos (0UL) |
ADC2 SQ0_1: SQ0 (Bit 0)
#define ADC2_SQ0_1_SQ1_Msk (0x1ff0000UL) |
ADC2 SQ0_1: SQ1 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ0_1_SQ1_Pos (16UL) |
ADC2 SQ0_1: SQ1 (Bit 16)
#define ADC2_SQ2_3_SQ2_Msk (0x1ffUL) |
ADC2 SQ2_3: SQ2 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ2_3_SQ2_Pos (0UL) |
ADC2 SQ2_3: SQ2 (Bit 0)
#define ADC2_SQ2_3_SQ3_Msk (0x1ff0000UL) |
ADC2 SQ2_3: SQ3 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ2_3_SQ3_Pos (16UL) |
ADC2 SQ2_3: SQ3 (Bit 16)
#define ADC2_SQ4_5_SQ4_Msk (0x1ffUL) |
ADC2 SQ4_5: SQ4 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ4_5_SQ4_Pos (0UL) |
ADC2 SQ4_5: SQ4 (Bit 0)
#define ADC2_SQ4_5_SQ5_Msk (0x1ff0000UL) |
ADC2 SQ4_5: SQ5 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ4_5_SQ5_Pos (16UL) |
ADC2 SQ4_5: SQ5 (Bit 16)
#define ADC2_SQ6_7_SQ6_Msk (0x1ffUL) |
ADC2 SQ6_7: SQ6 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ6_7_SQ6_Pos (0UL) |
ADC2 SQ6_7: SQ6 (Bit 0)
#define ADC2_SQ6_7_SQ7_Msk (0x1ff0000UL) |
ADC2 SQ6_7: SQ7 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ6_7_SQ7_Pos (16UL) |
ADC2 SQ6_7: SQ7 (Bit 16)
#define ADC2_SQ8_9_SQ8_Msk (0x1ffUL) |
ADC2 SQ8_9: SQ8 (Bitfield-Mask: 0x1ff)
#define ADC2_SQ8_9_SQ8_Pos (0UL) |
ADC2 SQ8_9: SQ8 (Bit 0)
#define ADC2_SQ_FB_CHx_Msk (0xf0000UL) |
ADC2 SQ_FB: CHx (Bitfield-Mask: 0x0f)
#define ADC2_SQ_FB_CHx_Pos (16UL) |
ADC2 SQ_FB: CHx (Bit 16)
#define ADC2_SQ_FB_EIM_ACTIVE_Msk (0x200UL) |
ADC2 SQ_FB: EIM_ACTIVE (Bitfield-Mask: 0x01)
#define ADC2_SQ_FB_EIM_ACTIVE_Pos (9UL) |
ADC2 SQ_FB: EIM_ACTIVE (Bit 9)
#define ADC2_SQ_FB_SQ_FB_Msk (0xfUL) |
ADC2 SQ_FB: SQ_FB (Bitfield-Mask: 0x0f)
#define ADC2_SQ_FB_SQ_FB_Pos (0UL) |
ADC2 SQ_FB: SQ_FB (Bit 0)
#define ADC2_SQ_FB_SQ_STOP_Msk (0x100UL) |
ADC2 SQ_FB: SQ_STOP (Bitfield-Mask: 0x01)
#define ADC2_SQ_FB_SQ_STOP_Pos (8UL) |
ADC2 SQ_FB: SQ_STOP (Bit 8)
#define ADC2_SQ_FB_SQx_Msk (0x7800UL) |
ADC2 SQ_FB: SQx (Bitfield-Mask: 0x0f)
#define ADC2_SQ_FB_SQx_Pos (11UL) |
ADC2 SQ_FB: SQx (Bit 11)
#define ADC2_STATUS_READY_Msk (0x2UL) |
ADC2 STATUS: READY (Bitfield-Mask: 0x01)
#define ADC2_STATUS_READY_Pos (1UL) |
ADC2 STATUS: READY (Bit 1)
#define ADC2_TH0_3_LOWER_THLO_CH0_Msk (0xffUL) |
ADC2 TH0_3_LOWER: THLO_CH0 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_THLO_CH0_Pos (0UL) |
ADC2 TH0_3_LOWER: THLO_CH0 (Bit 0)
#define ADC2_TH0_3_LOWER_THLO_CH1_Msk (0xff00UL) |
ADC2 TH0_3_LOWER: THLO_CH1 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_THLO_CH1_Pos (8UL) |
ADC2 TH0_3_LOWER: THLO_CH1 (Bit 8)
#define ADC2_TH0_3_LOWER_THLO_CH2_Msk (0xff0000UL) |
ADC2 TH0_3_LOWER: THLO_CH2 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_THLO_CH2_Pos (16UL) |
ADC2 TH0_3_LOWER: THLO_CH2 (Bit 16)
#define ADC2_TH0_3_LOWER_THLO_CH3_Msk (0xff000000UL) |
ADC2 TH0_3_LOWER: THLO_CH3 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_LOWER_THLO_CH3_Pos (24UL) |
ADC2 TH0_3_LOWER: THLO_CH3 (Bit 24)
#define ADC2_TH0_3_UPPER_THUP_CH0_Msk (0xffUL) |
ADC2 TH0_3_UPPER: THUP_CH0 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_THUP_CH0_Pos (0UL) |
ADC2 TH0_3_UPPER: THUP_CH0 (Bit 0)
#define ADC2_TH0_3_UPPER_THUP_CH1_Msk (0xff00UL) |
ADC2 TH0_3_UPPER: THUP_CH1 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_THUP_CH1_Pos (8UL) |
ADC2 TH0_3_UPPER: THUP_CH1 (Bit 8)
#define ADC2_TH0_3_UPPER_THUP_CH2_Msk (0xff0000UL) |
ADC2 TH0_3_UPPER: THUP_CH2 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_THUP_CH2_Pos (16UL) |
ADC2 TH0_3_UPPER: THUP_CH2 (Bit 16)
#define ADC2_TH0_3_UPPER_THUP_CH3_Msk (0xff000000UL) |
ADC2 TH0_3_UPPER: THUP_CH3 (Bitfield-Mask: 0xff)
#define ADC2_TH0_3_UPPER_THUP_CH3_Pos (24UL) |
ADC2 TH0_3_UPPER: THUP_CH3 (Bit 24)
#define ADC2_TH4_7_LOWER_THLO_CH4_Msk (0xffUL) |
ADC2 TH4_7_LOWER: THLO_CH4 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_LOWER_THLO_CH4_Pos (0UL) |
ADC2 TH4_7_LOWER: THLO_CH4 (Bit 0)
#define ADC2_TH4_7_LOWER_THLO_CH5_Msk (0xff00UL) |
ADC2 TH4_7_LOWER: THLO_CH5 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_LOWER_THLO_CH5_Pos (8UL) |
ADC2 TH4_7_LOWER: THLO_CH5 (Bit 8)
#define ADC2_TH4_7_LOWER_THLO_CH6_Msk (0xff0000UL) |
ADC2 TH4_7_LOWER: THLO_CH6 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_LOWER_THLO_CH6_Pos (16UL) |
ADC2 TH4_7_LOWER: THLO_CH6 (Bit 16)
#define ADC2_TH4_7_LOWER_THLO_CH7_Msk (0xff000000UL) |
ADC2 TH4_7_LOWER: THLO_CH7 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_LOWER_THLO_CH7_Pos (24UL) |
ADC2 TH4_7_LOWER: THLO_CH7 (Bit 24)
#define ADC2_TH4_7_UPPER_THUP_CH4_Msk (0xffUL) |
ADC2 TH4_7_UPPER: THUP_CH4 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_UPPER_THUP_CH4_Pos (0UL) |
ADC2 TH4_7_UPPER: THUP_CH4 (Bit 0)
#define ADC2_TH4_7_UPPER_THUP_CH5_Msk (0xff00UL) |
ADC2 TH4_7_UPPER: THUP_CH5 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_UPPER_THUP_CH5_Pos (8UL) |
ADC2 TH4_7_UPPER: THUP_CH5 (Bit 8)
#define ADC2_TH4_7_UPPER_THUP_CH6_Msk (0xff0000UL) |
ADC2 TH4_7_UPPER: THUP_CH6 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_UPPER_THUP_CH6_Pos (16UL) |
ADC2 TH4_7_UPPER: THUP_CH6 (Bit 16)
#define ADC2_TH4_7_UPPER_THUP_CH7_Msk (0xff000000UL) |
ADC2 TH4_7_UPPER: THUP_CH7 (Bitfield-Mask: 0xff)
#define ADC2_TH4_7_UPPER_THUP_CH7_Pos (24UL) |
ADC2 TH4_7_UPPER: THUP_CH7 (Bit 24)
#define ADC2_TH8_11_LOWER_THLO_CH8_Msk (0xffUL) |
ADC2 TH8_11_LOWER: THLO_CH8 (Bitfield-Mask: 0xff)
#define ADC2_TH8_11_LOWER_THLO_CH8_Pos (0UL) |
ADC2 TH8_11_LOWER: THLO_CH8 (Bit 0)
#define ADC2_TH8_11_UPPER_THUP_CH8_Msk (0xffUL) |
ADC2 TH8_11_UPPER: THUP_CH8 (Bitfield-Mask: 0xff)
#define ADC2_TH8_11_UPPER_THUP_CH8_Pos (0UL) |
ADC2 TH8_11_UPPER: THUP_CH8 (Bit 0)
#define BDRV_ASEQC_HB1ASMOFFEN_Msk (0x2UL) |
BDRV ASEQC: HB1ASMOFFEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB1ASMOFFEN_Pos (1UL) |
BDRV ASEQC: HB1ASMOFFEN (Bit 1)
#define BDRV_ASEQC_HB1ASMONEN_Msk (0x1UL) |
BDRV ASEQC: HB1ASMONEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB1ASMONEN_Pos (0UL) |
BDRV ASEQC: HB1ASMONEN (Bit 0)
#define BDRV_ASEQC_HB1OFFHYSTEN_Msk (0x80UL) |
BDRV ASEQC: HB1OFFHYSTEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB1OFFHYSTEN_Pos (7UL) |
BDRV ASEQC: HB1OFFHYSTEN (Bit 7)
#define BDRV_ASEQC_HB1ONHYSTEN_Msk (0x40UL) |
BDRV ASEQC: HB1ONHYSTEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB1ONHYSTEN_Pos (6UL) |
BDRV ASEQC: HB1ONHYSTEN (Bit 6)
#define BDRV_ASEQC_HB1OPTOFFACT_Msk (0x20UL) |
BDRV ASEQC: HB1OPTOFFACT (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB1OPTOFFACT_Pos (5UL) |
BDRV ASEQC: HB1OPTOFFACT (Bit 5)
#define BDRV_ASEQC_HB1OPTONACT_Msk (0x10UL) |
BDRV ASEQC: HB1OPTONACT (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB1OPTONACT_Pos (4UL) |
BDRV ASEQC: HB1OPTONACT (Bit 4)
#define BDRV_ASEQC_HB2ASMOFFEN_Msk (0x20000UL) |
BDRV ASEQC: HB2ASMOFFEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB2ASMOFFEN_Pos (17UL) |
BDRV ASEQC: HB2ASMOFFEN (Bit 17)
#define BDRV_ASEQC_HB2ASMONEN_Msk (0x10000UL) |
BDRV ASEQC: HB2ASMONEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB2ASMONEN_Pos (16UL) |
BDRV ASEQC: HB2ASMONEN (Bit 16)
#define BDRV_ASEQC_HB2OFFHYSTEN_Msk (0x800000UL) |
BDRV ASEQC: HB2OFFHYSTEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB2OFFHYSTEN_Pos (23UL) |
BDRV ASEQC: HB2OFFHYSTEN (Bit 23)
#define BDRV_ASEQC_HB2ONHYSTEN_Msk (0x400000UL) |
BDRV ASEQC: HB2ONHYSTEN (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB2ONHYSTEN_Pos (22UL) |
BDRV ASEQC: HB2ONHYSTEN (Bit 22)
#define BDRV_ASEQC_HB2OPTOFFACT_Msk (0x200000UL) |
BDRV ASEQC: HB2OPTOFFACT (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB2OPTOFFACT_Pos (21UL) |
BDRV ASEQC: HB2OPTOFFACT (Bit 21)
#define BDRV_ASEQC_HB2OPTONACT_Msk (0x100000UL) |
BDRV ASEQC: HB2OPTONACT (Bitfield-Mask: 0x01)
#define BDRV_ASEQC_HB2OPTONACT_Pos (20UL) |
BDRV ASEQC: HB2OPTONACT (Bit 20)
#define BDRV_ASEQERRCNT_HB1MFERRCNT_Msk (0x30UL) |
BDRV ASEQERRCNT: HB1MFERRCNT (Bitfield-Mask: 0x03)
#define BDRV_ASEQERRCNT_HB1MFERRCNT_Pos (4UL) |
BDRV ASEQERRCNT: HB1MFERRCNT (Bit 4)
#define BDRV_ASEQERRCNT_HB1T12ONERRCNT_Msk (0xcUL) |
BDRV ASEQERRCNT: HB1T12ONERRCNT (Bitfield-Mask: 0x03)
#define BDRV_ASEQERRCNT_HB1T12ONERRCNT_Pos (2UL) |
BDRV ASEQERRCNT: HB1T12ONERRCNT (Bit 2)
#define BDRV_ASEQERRCNT_HB1T1OFFERRCNT_Msk (0x3UL) |
BDRV ASEQERRCNT: HB1T1OFFERRCNT (Bitfield-Mask: 0x03)
#define BDRV_ASEQERRCNT_HB1T1OFFERRCNT_Pos (0UL) |
BDRV ASEQERRCNT: HB1T1OFFERRCNT (Bit 0)
#define BDRV_ASEQERRCNT_HB2MFERRCNT_Msk (0x300000UL) |
BDRV ASEQERRCNT: HB2MFERRCNT (Bitfield-Mask: 0x03)
#define BDRV_ASEQERRCNT_HB2MFERRCNT_Pos (20UL) |
BDRV ASEQERRCNT: HB2MFERRCNT (Bit 20)
#define BDRV_ASEQERRCNT_HB2T12ONERRCNT_Msk (0xc0000UL) |
BDRV ASEQERRCNT: HB2T12ONERRCNT (Bitfield-Mask: 0x03)
#define BDRV_ASEQERRCNT_HB2T12ONERRCNT_Pos (18UL) |
BDRV ASEQERRCNT: HB2T12ONERRCNT (Bit 18)
#define BDRV_ASEQERRCNT_HB2T1OFFERRCNT_Msk (0x30000UL) |
BDRV ASEQERRCNT: HB2T1OFFERRCNT (Bitfield-Mask: 0x03)
#define BDRV_ASEQERRCNT_HB2T1OFFERRCNT_Pos (16UL) |
BDRV ASEQERRCNT: HB2T1OFFERRCNT (Bit 16)
#define BDRV_ASEQIOFFMAX_I1OFFMAX_Msk (0x3fUL) |
BDRV ASEQIOFFMAX: I1OFFMAX (Bitfield-Mask: 0x3f)
#define BDRV_ASEQIOFFMAX_I1OFFMAX_Pos (0UL) |
BDRV ASEQIOFFMAX: I1OFFMAX (Bit 0)
#define BDRV_ASEQIOFFMIN_I1OFFMIN_Msk (0x3fUL) |
BDRV ASEQIOFFMIN: I1OFFMIN (Bitfield-Mask: 0x3f)
#define BDRV_ASEQIOFFMIN_I1OFFMIN_Pos (0UL) |
BDRV ASEQIOFFMIN: I1OFFMIN (Bit 0)
#define BDRV_ASEQIONMAX_I1ONMAX_Msk (0x3fUL) |
BDRV ASEQIONMAX: I1ONMAX (Bitfield-Mask: 0x3f)
#define BDRV_ASEQIONMAX_I1ONMAX_Pos (0UL) |
BDRV ASEQIONMAX: I1ONMAX (Bit 0)
#define BDRV_ASEQIONMIN_I1ONMIN_Msk (0x3fUL) |
BDRV ASEQIONMIN: I1ONMIN (Bitfield-Mask: 0x3f)
#define BDRV_ASEQIONMIN_I1ONMIN_Pos (0UL) |
BDRV ASEQIONMIN: I1ONMIN (Bit 0)
#define BDRV_ASEQSTS_HB1I1OFFMAX_Msk (0x2UL) |
BDRV ASEQSTS: HB1I1OFFMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1I1OFFMAX_Pos (1UL) |
BDRV ASEQSTS: HB1I1OFFMAX (Bit 1)
#define BDRV_ASEQSTS_HB1I1OFFMIN_Msk (0x8UL) |
BDRV ASEQSTS: HB1I1OFFMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1I1OFFMIN_Pos (3UL) |
BDRV ASEQSTS: HB1I1OFFMIN (Bit 3)
#define BDRV_ASEQSTS_HB1I1ONMAX_Msk (0x20UL) |
BDRV ASEQSTS: HB1I1ONMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1I1ONMAX_Pos (5UL) |
BDRV ASEQSTS: HB1I1ONMAX (Bit 5)
#define BDRV_ASEQSTS_HB1I1ONMIN_Msk (0x80UL) |
BDRV ASEQSTS: HB1I1ONMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1I1ONMIN_Pos (7UL) |
BDRV ASEQSTS: HB1I1ONMIN (Bit 7)
#define BDRV_ASEQSTS_HB1OFFMF_Msk (0x4000UL) |
BDRV ASEQSTS: HB1OFFMF (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1OFFMF_Pos (14UL) |
BDRV ASEQSTS: HB1OFFMF (Bit 14)
#define BDRV_ASEQSTS_HB1ONMF_Msk (0x8000UL) |
BDRV ASEQSTS: HB1ONMF (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1ONMF_Pos (15UL) |
BDRV ASEQSTS: HB1ONMF (Bit 15)
#define BDRV_ASEQSTS_HB1T12ONMAX_Msk (0x10UL) |
BDRV ASEQSTS: HB1T12ONMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1T12ONMAX_Pos (4UL) |
BDRV ASEQSTS: HB1T12ONMAX (Bit 4)
#define BDRV_ASEQSTS_HB1T12ONMIN_Msk (0x40UL) |
BDRV ASEQSTS: HB1T12ONMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1T12ONMIN_Pos (6UL) |
BDRV ASEQSTS: HB1T12ONMIN (Bit 6)
#define BDRV_ASEQSTS_HB1T1OFFMAX_Msk (0x1UL) |
BDRV ASEQSTS: HB1T1OFFMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1T1OFFMAX_Pos (0UL) |
BDRV ASEQSTS: HB1T1OFFMAX (Bit 0)
#define BDRV_ASEQSTS_HB1T1OFFMIN_Msk (0x4UL) |
BDRV ASEQSTS: HB1T1OFFMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB1T1OFFMIN_Pos (2UL) |
BDRV ASEQSTS: HB1T1OFFMIN (Bit 2)
#define BDRV_ASEQSTS_HB2I1OFFMAX_Msk (0x20000UL) |
BDRV ASEQSTS: HB2I1OFFMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2I1OFFMAX_Pos (17UL) |
BDRV ASEQSTS: HB2I1OFFMAX (Bit 17)
#define BDRV_ASEQSTS_HB2I1OFFMIN_Msk (0x80000UL) |
BDRV ASEQSTS: HB2I1OFFMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2I1OFFMIN_Pos (19UL) |
BDRV ASEQSTS: HB2I1OFFMIN (Bit 19)
#define BDRV_ASEQSTS_HB2I1ONMAX_Msk (0x200000UL) |
BDRV ASEQSTS: HB2I1ONMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2I1ONMAX_Pos (21UL) |
BDRV ASEQSTS: HB2I1ONMAX (Bit 21)
#define BDRV_ASEQSTS_HB2I1ONMIN_Msk (0x800000UL) |
BDRV ASEQSTS: HB2I1ONMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2I1ONMIN_Pos (23UL) |
BDRV ASEQSTS: HB2I1ONMIN (Bit 23)
#define BDRV_ASEQSTS_HB2OFFMF_Msk (0x40000000UL) |
BDRV ASEQSTS: HB2OFFMF (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2OFFMF_Pos (30UL) |
BDRV ASEQSTS: HB2OFFMF (Bit 30)
#define BDRV_ASEQSTS_HB2ONMF_Msk (0x80000000UL) |
BDRV ASEQSTS: HB2ONMF (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2ONMF_Pos (31UL) |
BDRV ASEQSTS: HB2ONMF (Bit 31)
#define BDRV_ASEQSTS_HB2T12ONMAX_Msk (0x100000UL) |
BDRV ASEQSTS: HB2T12ONMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2T12ONMAX_Pos (20UL) |
BDRV ASEQSTS: HB2T12ONMAX (Bit 20)
#define BDRV_ASEQSTS_HB2T12ONMIN_Msk (0x400000UL) |
BDRV ASEQSTS: HB2T12ONMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2T12ONMIN_Pos (22UL) |
BDRV ASEQSTS: HB2T12ONMIN (Bit 22)
#define BDRV_ASEQSTS_HB2T1OFFMAX_Msk (0x10000UL) |
BDRV ASEQSTS: HB2T1OFFMAX (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2T1OFFMAX_Pos (16UL) |
BDRV ASEQSTS: HB2T1OFFMAX (Bit 16)
#define BDRV_ASEQSTS_HB2T1OFFMIN_Msk (0x40000UL) |
BDRV ASEQSTS: HB2T1OFFMIN (Bitfield-Mask: 0x01)
#define BDRV_ASEQSTS_HB2T1OFFMIN_Pos (18UL) |
BDRV ASEQSTS: HB2T1OFFMIN (Bit 18)
#define BDRV_CP_CLK_CTRL_CPCLK_EN_Msk (0x8000UL) |
BDRV CP_CLK_CTRL: CPCLK_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CLK_CTRL_CPCLK_EN_Pos (15UL) |
BDRV CP_CLK_CTRL: CPCLK_EN (Bit 15)
#define BDRV_CP_CLK_CTRL_CPCLKDIS_SET_Msk (0x10000UL) |
BDRV CP_CLK_CTRL: CPCLKDIS_SET (Bitfield-Mask: 0x01)
#define BDRV_CP_CLK_CTRL_CPCLKDIS_SET_Pos (16UL) |
BDRV CP_CLK_CTRL: CPCLKDIS_SET (Bit 16)
#define BDRV_CP_CLK_CTRL_DITH_LOWER_Msk (0x1fUL) |
BDRV CP_CLK_CTRL: DITH_LOWER (Bitfield-Mask: 0x1f)
#define BDRV_CP_CLK_CTRL_DITH_LOWER_Pos (0UL) |
BDRV CP_CLK_CTRL: DITH_LOWER (Bit 0)
#define BDRV_CP_CLK_CTRL_DITH_UPPER_Msk (0x1f00UL) |
BDRV CP_CLK_CTRL: DITH_UPPER (Bitfield-Mask: 0x1f)
#define BDRV_CP_CLK_CTRL_DITH_UPPER_Pos (8UL) |
BDRV CP_CLK_CTRL: DITH_UPPER (Bit 8)
#define BDRV_CP_CLK_CTRL_F_CP_Msk (0x6000UL) |
BDRV CP_CLK_CTRL: F_CP (Bitfield-Mask: 0x03)
#define BDRV_CP_CLK_CTRL_F_CP_Pos (13UL) |
BDRV CP_CLK_CTRL: F_CP (Bit 13)
#define BDRV_CP_CTRL_CP_EN_Msk (0x1UL) |
BDRV CP_CTRL: CP_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_CP_EN_Pos (0UL) |
BDRV CP_CTRL: CP_EN (Bit 0)
#define BDRV_CP_CTRL_CP_RDY_EN_Msk (0x4UL) |
BDRV CP_CTRL: CP_RDY_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_CP_RDY_EN_Pos (2UL) |
BDRV CP_CTRL: CP_RDY_EN (Bit 2)
#define BDRV_CP_CTRL_CP_STAGE_SEL_Msk (0x60000000UL) |
BDRV CP_CTRL: CP_STAGE_SEL (Bitfield-Mask: 0x03)
#define BDRV_CP_CTRL_CP_STAGE_SEL_Pos (29UL) |
BDRV CP_CTRL: CP_STAGE_SEL (Bit 29)
#define BDRV_CP_CTRL_CPLOPWRM_EN_Msk (0x1000000UL) |
BDRV CP_CTRL: CPLOPWRM_EN (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_CPLOPWRM_EN_Pos (24UL) |
BDRV CP_CTRL: CPLOPWRM_EN (Bit 24)
#define BDRV_CP_CTRL_DRVx_VCPLO_DIS_Msk (0x10000UL) |
BDRV CP_CTRL: DRVx_VCPLO_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_DRVx_VCPLO_DIS_Pos (16UL) |
BDRV CP_CTRL: DRVx_VCPLO_DIS (Bit 16)
#define BDRV_CP_CTRL_DRVx_VCPLO_SDEN_Msk (0x20000UL) |
BDRV CP_CTRL: DRVx_VCPLO_SDEN (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_DRVx_VCPLO_SDEN_Pos (17UL) |
BDRV CP_CTRL: DRVx_VCPLO_SDEN (Bit 17)
#define BDRV_CP_CTRL_DRVx_VCPUP_DIS_Msk (0x40000UL) |
BDRV CP_CTRL: DRVx_VCPUP_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_DRVx_VCPUP_DIS_Pos (18UL) |
BDRV CP_CTRL: DRVx_VCPUP_DIS (Bit 18)
#define BDRV_CP_CTRL_DRVx_VSDLO_DIS_Msk (0x100000UL) |
BDRV CP_CTRL: DRVx_VSDLO_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_DRVx_VSDLO_DIS_Pos (20UL) |
BDRV CP_CTRL: DRVx_VSDLO_DIS (Bit 20)
#define BDRV_CP_CTRL_DRVx_VSDUP_DIS_Msk (0x400000UL) |
BDRV CP_CTRL: DRVx_VSDUP_DIS (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_DRVx_VSDUP_DIS_Pos (22UL) |
BDRV CP_CTRL: DRVx_VSDUP_DIS (Bit 22)
#define BDRV_CP_CTRL_VCP14_15V_SEL_Msk (0x10000000UL) |
BDRV CP_CTRL: VCP14_15V_SEL (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_VCP14_15V_SEL_Pos (28UL) |
BDRV CP_CTRL: VCP14_15V_SEL (Bit 28)
#define BDRV_CP_CTRL_VCP9V_SET_Msk (0x2000000UL) |
BDRV CP_CTRL: VCP9V_SET (Bitfield-Mask: 0x01)
#define BDRV_CP_CTRL_VCP9V_SET_Pos (25UL) |
BDRV CP_CTRL: VCP9V_SET (Bit 25)
#define BDRV_CP_CTRL_VTHVCP_TRIM_Msk (0xc000000UL) |
BDRV CP_CTRL: VTHVCP_TRIM (Bitfield-Mask: 0x03)
#define BDRV_CP_CTRL_VTHVCP_TRIM_Pos (26UL) |
BDRV CP_CTRL: VTHVCP_TRIM (Bit 26)
#define BDRV_CP_IRQCLR_VCP_LOTH1_ISC_Msk (0x200UL) |
BDRV CP_IRQCLR: VCP_LOTH1_ISC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_LOTH1_ISC_Pos (9UL) |
BDRV CP_IRQCLR: VCP_LOTH1_ISC (Bit 9)
#define BDRV_CP_IRQCLR_VCP_LOTH1_SC_Msk (0x2000000UL) |
BDRV CP_IRQCLR: VCP_LOTH1_SC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_LOTH1_SC_Pos (25UL) |
BDRV CP_IRQCLR: VCP_LOTH1_SC (Bit 25)
#define BDRV_CP_IRQCLR_VCP_OTSD_ISC_Msk (0x10UL) |
BDRV CP_IRQCLR: VCP_OTSD_ISC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_OTSD_ISC_Pos (4UL) |
BDRV CP_IRQCLR: VCP_OTSD_ISC (Bit 4)
#define BDRV_CP_IRQCLR_VCP_OTSD_SC_Msk (0x100000UL) |
BDRV CP_IRQCLR: VCP_OTSD_SC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_OTSD_SC_Pos (20UL) |
BDRV CP_IRQCLR: VCP_OTSD_SC (Bit 20)
#define BDRV_CP_IRQCLR_VCP_OTW_ISC_Msk (0x1UL) |
BDRV CP_IRQCLR: VCP_OTW_ISC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_OTW_ISC_Pos (0UL) |
BDRV CP_IRQCLR: VCP_OTW_ISC (Bit 0)
#define BDRV_CP_IRQCLR_VCP_OTW_SC_Msk (0x10000UL) |
BDRV CP_IRQCLR: VCP_OTW_SC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_OTW_SC_Pos (16UL) |
BDRV CP_IRQCLR: VCP_OTW_SC (Bit 16)
#define BDRV_CP_IRQCLR_VCP_UPTH_ISC_Msk (0x800UL) |
BDRV CP_IRQCLR: VCP_UPTH_ISC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_UPTH_ISC_Pos (11UL) |
BDRV CP_IRQCLR: VCP_UPTH_ISC (Bit 11)
#define BDRV_CP_IRQCLR_VCP_UPTH_SC_Msk (0x8000000UL) |
BDRV CP_IRQCLR: VCP_UPTH_SC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VCP_UPTH_SC_Pos (27UL) |
BDRV CP_IRQCLR: VCP_UPTH_SC (Bit 27)
#define BDRV_CP_IRQCLR_VSD_LOTH_ISC_Msk (0x2000UL) |
BDRV CP_IRQCLR: VSD_LOTH_ISC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VSD_LOTH_ISC_Pos (13UL) |
BDRV CP_IRQCLR: VSD_LOTH_ISC (Bit 13)
#define BDRV_CP_IRQCLR_VSD_LOTH_SC_Msk (0x20000000UL) |
BDRV CP_IRQCLR: VSD_LOTH_SC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VSD_LOTH_SC_Pos (29UL) |
BDRV CP_IRQCLR: VSD_LOTH_SC (Bit 29)
#define BDRV_CP_IRQCLR_VSD_UPTH_ISC_Msk (0x8000UL) |
BDRV CP_IRQCLR: VSD_UPTH_ISC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VSD_UPTH_ISC_Pos (15UL) |
BDRV CP_IRQCLR: VSD_UPTH_ISC (Bit 15)
#define BDRV_CP_IRQCLR_VSD_UPTH_SC_Msk (0x80000000UL) |
BDRV CP_IRQCLR: VSD_UPTH_SC (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQCLR_VSD_UPTH_SC_Pos (31UL) |
BDRV CP_IRQCLR: VSD_UPTH_SC (Bit 31)
#define BDRV_CP_IRQEN_VCP_LOTH1_IEN_Msk (0x200UL) |
BDRV CP_IRQEN: VCP_LOTH1_IEN (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQEN_VCP_LOTH1_IEN_Pos (9UL) |
BDRV CP_IRQEN: VCP_LOTH1_IEN (Bit 9)
#define BDRV_CP_IRQEN_VCP_OTSD_IEN_Msk (0x10UL) |
BDRV CP_IRQEN: VCP_OTSD_IEN (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQEN_VCP_OTSD_IEN_Pos (4UL) |
BDRV CP_IRQEN: VCP_OTSD_IEN (Bit 4)
#define BDRV_CP_IRQEN_VCP_OTW_IEN_Msk (0x1UL) |
BDRV CP_IRQEN: VCP_OTW_IEN (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQEN_VCP_OTW_IEN_Pos (0UL) |
BDRV CP_IRQEN: VCP_OTW_IEN (Bit 0)
#define BDRV_CP_IRQEN_VCP_UPTH_IEN_Msk (0x800UL) |
BDRV CP_IRQEN: VCP_UPTH_IEN (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQEN_VCP_UPTH_IEN_Pos (11UL) |
BDRV CP_IRQEN: VCP_UPTH_IEN (Bit 11)
#define BDRV_CP_IRQEN_VSD_LOTH_IEN_Msk (0x2000UL) |
BDRV CP_IRQEN: VSD_LOTH_IEN (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQEN_VSD_LOTH_IEN_Pos (13UL) |
BDRV CP_IRQEN: VSD_LOTH_IEN (Bit 13)
#define BDRV_CP_IRQEN_VSD_UPTH_IEN_Msk (0x8000UL) |
BDRV CP_IRQEN: VSD_UPTH_IEN (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQEN_VSD_UPTH_IEN_Pos (15UL) |
BDRV CP_IRQEN: VSD_UPTH_IEN (Bit 15)
#define BDRV_CP_IRQS_VCP_LOTH1_IS_Msk (0x200UL) |
BDRV CP_IRQS: VCP_LOTH1_IS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_LOTH1_IS_Pos (9UL) |
BDRV CP_IRQS: VCP_LOTH1_IS (Bit 9)
#define BDRV_CP_IRQS_VCP_LOTH1_STS_Msk (0x2000000UL) |
BDRV CP_IRQS: VCP_LOTH1_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_LOTH1_STS_Pos (25UL) |
BDRV CP_IRQS: VCP_LOTH1_STS (Bit 25)
#define BDRV_CP_IRQS_VCP_OTSD_IS_Msk (0x10UL) |
BDRV CP_IRQS: VCP_OTSD_IS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_OTSD_IS_Pos (4UL) |
BDRV CP_IRQS: VCP_OTSD_IS (Bit 4)
#define BDRV_CP_IRQS_VCP_OTSD_STS_Msk (0x100000UL) |
BDRV CP_IRQS: VCP_OTSD_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_OTSD_STS_Pos (20UL) |
BDRV CP_IRQS: VCP_OTSD_STS (Bit 20)
#define BDRV_CP_IRQS_VCP_OTW_IS_Msk (0x1UL) |
BDRV CP_IRQS: VCP_OTW_IS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_OTW_IS_Pos (0UL) |
BDRV CP_IRQS: VCP_OTW_IS (Bit 0)
#define BDRV_CP_IRQS_VCP_OTW_STS_Msk (0x10000UL) |
BDRV CP_IRQS: VCP_OTW_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_OTW_STS_Pos (16UL) |
BDRV CP_IRQS: VCP_OTW_STS (Bit 16)
#define BDRV_CP_IRQS_VCP_UPTH_IS_Msk (0x800UL) |
BDRV CP_IRQS: VCP_UPTH_IS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_UPTH_IS_Pos (11UL) |
BDRV CP_IRQS: VCP_UPTH_IS (Bit 11)
#define BDRV_CP_IRQS_VCP_UPTH_STS_Msk (0x8000000UL) |
BDRV CP_IRQS: VCP_UPTH_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VCP_UPTH_STS_Pos (27UL) |
BDRV CP_IRQS: VCP_UPTH_STS (Bit 27)
#define BDRV_CP_IRQS_VSD_LOTH_IS_Msk (0x2000UL) |
BDRV CP_IRQS: VSD_LOTH_IS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VSD_LOTH_IS_Pos (13UL) |
BDRV CP_IRQS: VSD_LOTH_IS (Bit 13)
#define BDRV_CP_IRQS_VSD_LOTH_STS_Msk (0x20000000UL) |
BDRV CP_IRQS: VSD_LOTH_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VSD_LOTH_STS_Pos (29UL) |
BDRV CP_IRQS: VSD_LOTH_STS (Bit 29)
#define BDRV_CP_IRQS_VSD_UPTH_IS_Msk (0x8000UL) |
BDRV CP_IRQS: VSD_UPTH_IS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VSD_UPTH_IS_Pos (15UL) |
BDRV CP_IRQS: VSD_UPTH_IS (Bit 15)
#define BDRV_CP_IRQS_VSD_UPTH_STS_Msk (0x80000000UL) |
BDRV CP_IRQS: VSD_UPTH_STS (Bitfield-Mask: 0x01)
#define BDRV_CP_IRQS_VSD_UPTH_STS_Pos (31UL) |
BDRV CP_IRQS: VSD_UPTH_STS (Bit 31)
#define BDRV_CTRL1_HS1_DCS_EN_Msk (0x80000UL) |
BDRV CTRL1: HS1_DCS_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_DCS_EN_Pos (19UL) |
BDRV CTRL1: HS1_DCS_EN (Bit 19)
#define BDRV_CTRL1_HS1_EN_Msk (0x10000UL) |
BDRV CTRL1: HS1_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_EN_Pos (16UL) |
BDRV CTRL1: HS1_EN (Bit 16)
#define BDRV_CTRL1_HS1_OC_DIS_Msk (0x800000UL) |
BDRV CTRL1: HS1_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_OC_DIS_Pos (23UL) |
BDRV CTRL1: HS1_OC_DIS (Bit 23)
#define BDRV_CTRL1_HS1_ON_Msk (0x40000UL) |
BDRV CTRL1: HS1_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_ON_Pos (18UL) |
BDRV CTRL1: HS1_ON (Bit 18)
#define BDRV_CTRL1_HS1_PWM_Msk (0x20000UL) |
BDRV CTRL1: HS1_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_PWM_Pos (17UL) |
BDRV CTRL1: HS1_PWM (Bit 17)
#define BDRV_CTRL1_HS1_SUPERR_STS_Msk (0x200000UL) |
BDRV CTRL1: HS1_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS1_SUPERR_STS_Pos (21UL) |
BDRV CTRL1: HS1_SUPERR_STS (Bit 21)
#define BDRV_CTRL1_HS2_DCS_EN_Msk (0x8000000UL) |
BDRV CTRL1: HS2_DCS_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_DCS_EN_Pos (27UL) |
BDRV CTRL1: HS2_DCS_EN (Bit 27)
#define BDRV_CTRL1_HS2_EN_Msk (0x1000000UL) |
BDRV CTRL1: HS2_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_EN_Pos (24UL) |
BDRV CTRL1: HS2_EN (Bit 24)
#define BDRV_CTRL1_HS2_OC_DIS_Msk (0x80000000UL) |
BDRV CTRL1: HS2_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_OC_DIS_Pos (31UL) |
BDRV CTRL1: HS2_OC_DIS (Bit 31)
#define BDRV_CTRL1_HS2_ON_Msk (0x4000000UL) |
BDRV CTRL1: HS2_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_ON_Pos (26UL) |
BDRV CTRL1: HS2_ON (Bit 26)
#define BDRV_CTRL1_HS2_PWM_Msk (0x2000000UL) |
BDRV CTRL1: HS2_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_PWM_Pos (25UL) |
BDRV CTRL1: HS2_PWM (Bit 25)
#define BDRV_CTRL1_HS2_SUPERR_STS_Msk (0x20000000UL) |
BDRV CTRL1: HS2_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_HS2_SUPERR_STS_Pos (29UL) |
BDRV CTRL1: HS2_SUPERR_STS (Bit 29)
#define BDRV_CTRL1_LS1_EN_Msk (0x1UL) |
BDRV CTRL1: LS1_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_EN_Pos (0UL) |
BDRV CTRL1: LS1_EN (Bit 0)
#define BDRV_CTRL1_LS1_OC_DIS_Msk (0x80UL) |
BDRV CTRL1: LS1_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_OC_DIS_Pos (7UL) |
BDRV CTRL1: LS1_OC_DIS (Bit 7)
#define BDRV_CTRL1_LS1_ON_Msk (0x4UL) |
BDRV CTRL1: LS1_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_ON_Pos (2UL) |
BDRV CTRL1: LS1_ON (Bit 2)
#define BDRV_CTRL1_LS1_PWM_Msk (0x2UL) |
BDRV CTRL1: LS1_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_PWM_Pos (1UL) |
BDRV CTRL1: LS1_PWM (Bit 1)
#define BDRV_CTRL1_LS1_SUPERR_STS_Msk (0x20UL) |
BDRV CTRL1: LS1_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS1_SUPERR_STS_Pos (5UL) |
BDRV CTRL1: LS1_SUPERR_STS (Bit 5)
#define BDRV_CTRL1_LS2_EN_Msk (0x100UL) |
BDRV CTRL1: LS2_EN (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_EN_Pos (8UL) |
BDRV CTRL1: LS2_EN (Bit 8)
#define BDRV_CTRL1_LS2_OC_DIS_Msk (0x8000UL) |
BDRV CTRL1: LS2_OC_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_OC_DIS_Pos (15UL) |
BDRV CTRL1: LS2_OC_DIS (Bit 15)
#define BDRV_CTRL1_LS2_ON_Msk (0x400UL) |
BDRV CTRL1: LS2_ON (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_ON_Pos (10UL) |
BDRV CTRL1: LS2_ON (Bit 10)
#define BDRV_CTRL1_LS2_PWM_Msk (0x200UL) |
BDRV CTRL1: LS2_PWM (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_PWM_Pos (9UL) |
BDRV CTRL1: LS2_PWM (Bit 9)
#define BDRV_CTRL1_LS2_SUPERR_STS_Msk (0x2000UL) |
BDRV CTRL1: LS2_SUPERR_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL1_LS2_SUPERR_STS_Pos (13UL) |
BDRV CTRL1: LS2_SUPERR_STS (Bit 13)
#define BDRV_CTRL2_DLY_DIAG_CHSEL_Msk (0x70000000UL) |
BDRV CTRL2: DLY_DIAG_CHSEL (Bitfield-Mask: 0x07)
#define BDRV_CTRL2_DLY_DIAG_CHSEL_Pos (28UL) |
BDRV CTRL2: DLY_DIAG_CHSEL (Bit 28)
#define BDRV_CTRL2_DLY_DIAG_DIRSEL_Msk (0x80000000UL) |
BDRV CTRL2: DLY_DIAG_DIRSEL (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_DLY_DIAG_DIRSEL_Pos (31UL) |
BDRV CTRL2: DLY_DIAG_DIRSEL (Bit 31)
#define BDRV_CTRL2_DLY_DIAG_SCLR_Msk (0x4000000UL) |
BDRV CTRL2: DLY_DIAG_SCLR (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_DLY_DIAG_SCLR_Pos (26UL) |
BDRV CTRL2: DLY_DIAG_SCLR (Bit 26)
#define BDRV_CTRL2_DLY_DIAG_STS_Msk (0x8000000UL) |
BDRV CTRL2: DLY_DIAG_STS (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_DLY_DIAG_STS_Pos (27UL) |
BDRV CTRL2: DLY_DIAG_STS (Bit 27)
#define BDRV_CTRL2_DLY_DIAG_TIM_Msk (0x3ff0000UL) |
BDRV CTRL2: DLY_DIAG_TIM (Bitfield-Mask: 0x3ff)
#define BDRV_CTRL2_DLY_DIAG_TIM_Pos (16UL) |
BDRV CTRL2: DLY_DIAG_TIM (Bit 16)
#define BDRV_CTRL2_HB1OFFSEQCNF_Msk (0x4UL) |
BDRV CTRL2: HB1OFFSEQCNF (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_HB1OFFSEQCNF_Pos (2UL) |
BDRV CTRL2: HB1OFFSEQCNF (Bit 2)
#define BDRV_CTRL2_HB1ONSEQCNF_Msk (0x1UL) |
BDRV CTRL2: HB1ONSEQCNF (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_HB1ONSEQCNF_Pos (0UL) |
BDRV CTRL2: HB1ONSEQCNF (Bit 0)
#define BDRV_CTRL2_HB2OFFSEQCNF_Msk (0x8UL) |
BDRV CTRL2: HB2OFFSEQCNF (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_HB2OFFSEQCNF_Pos (3UL) |
BDRV CTRL2: HB2OFFSEQCNF (Bit 3)
#define BDRV_CTRL2_HB2ONSEQCNF_Msk (0x2UL) |
BDRV CTRL2: HB2ONSEQCNF (Bitfield-Mask: 0x01)
#define BDRV_CTRL2_HB2ONSEQCNF_Pos (1UL) |
BDRV CTRL2: HB2ONSEQCNF (Bit 1)
#define BDRV_CTRL3_DRV_CCP_DIS_Msk (0x40000000UL) |
BDRV CTRL3: DRV_CCP_DIS (Bitfield-Mask: 0x01)
#define BDRV_CTRL3_DRV_CCP_DIS_Pos (30UL) |
BDRV CTRL3: DRV_CCP_DIS (Bit 30)
#define BDRV_CTRL3_DRV_CCP_TIMSEL_Msk (0x3000000UL) |
BDRV CTRL3: DRV_CCP_TIMSEL (Bitfield-Mask: 0x03)
#define BDRV_CTRL3_DRV_CCP_TIMSEL_Pos (24UL) |
BDRV CTRL3: DRV_CCP_TIMSEL (Bit 24)
#define BDRV_CTRL3_DRV_CCP_TMUL_Msk (0x30000000UL) |
BDRV CTRL3: DRV_CCP_TMUL (Bitfield-Mask: 0x03)
#define BDRV_CTRL3_DRV_CCP_TMUL_Pos (28UL) |
BDRV CTRL3: DRV_CCP_TMUL (Bit 28)
#define BDRV_CTRL3_DSMONVTH_Msk (0x70000UL) |
BDRV CTRL3: DSMONVTH (Bitfield-Mask: 0x07)
#define BDRV_CTRL3_DSMONVTH_Pos (16UL) |
BDRV CTRL3: DSMONVTH (Bit 16)
#define BDRV_DCTRIM_DRVx_COMPENS_HS_Msk (0x700UL) |
BDRV DCTRIM_DRVx: COMPENS_HS (Bitfield-Mask: 0x07)
#define BDRV_DCTRIM_DRVx_COMPENS_HS_Pos (8UL) |
BDRV DCTRIM_DRVx: COMPENS_HS (Bit 8)
#define BDRV_DCTRIM_DRVx_COMPENS_LS_Msk (0x70000UL) |
BDRV DCTRIM_DRVx: COMPENS_LS (Bitfield-Mask: 0x07)
#define BDRV_DCTRIM_DRVx_COMPENS_LS_Pos (16UL) |
BDRV DCTRIM_DRVx: COMPENS_LS (Bit 16)
#define BDRV_HB1ASEQOFFVAL_HB1_I1OFFVAL_Msk (0x3f00UL) |
BDRV HB1ASEQOFFVAL: HB1_I1OFFVAL (Bitfield-Mask: 0x3f)
#define BDRV_HB1ASEQOFFVAL_HB1_I1OFFVAL_Pos (8UL) |
BDRV HB1ASEQOFFVAL: HB1_I1OFFVAL (Bit 8)
#define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_CLR_Msk (0x80000000UL) |
BDRV HB1ASEQOFFVAL: HB1_OFFVALVF_CLR (Bitfield-Mask: 0x01)
#define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_CLR_Pos (31UL) |
BDRV HB1ASEQOFFVAL: HB1_OFFVALVF_CLR (Bit 31)
#define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_Msk (0x40000000UL) |
BDRV HB1ASEQOFFVAL: HB1_OFFVALVF (Bitfield-Mask: 0x01)
#define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_Pos (30UL) |
BDRV HB1ASEQOFFVAL: HB1_OFFVALVF (Bit 30)
#define BDRV_HB1ASEQOFFVAL_HB1_T1OFFCNT_Msk (0xffUL) |
BDRV HB1ASEQOFFVAL: HB1_T1OFFCNT (Bitfield-Mask: 0xff)
#define BDRV_HB1ASEQOFFVAL_HB1_T1OFFCNT_Pos (0UL) |
BDRV HB1ASEQOFFVAL: HB1_T1OFFCNT (Bit 0)
#define BDRV_HB1ASEQOFFVAL_HB1_T2MERR_Msk (0x400000UL) |
BDRV HB1ASEQOFFVAL: HB1_T2MERR (Bitfield-Mask: 0x01)
#define BDRV_HB1ASEQOFFVAL_HB1_T2MERR_Pos (22UL) |
BDRV HB1ASEQOFFVAL: HB1_T2MERR (Bit 22)
#define BDRV_HB1ASEQOFFVAL_HB1_T2OFFCNT_Msk (0x3f0000UL) |
BDRV HB1ASEQOFFVAL: HB1_T2OFFCNT (Bitfield-Mask: 0x3f)
#define BDRV_HB1ASEQOFFVAL_HB1_T2OFFCNT_Pos (16UL) |
BDRV HB1ASEQOFFVAL: HB1_T2OFFCNT (Bit 16)
#define BDRV_HB1ASEQONVAL_HB1_I1ONVAL_Msk (0x3f00UL) |
BDRV HB1ASEQONVAL: HB1_I1ONVAL (Bitfield-Mask: 0x3f)
#define BDRV_HB1ASEQONVAL_HB1_I1ONVAL_Pos (8UL) |
BDRV HB1ASEQONVAL: HB1_I1ONVAL (Bit 8)
#define BDRV_HB1ASEQONVAL_HB1_ONVALVF_CLR_Msk (0x80000000UL) |
BDRV HB1ASEQONVAL: HB1_ONVALVF_CLR (Bitfield-Mask: 0x01)
#define BDRV_HB1ASEQONVAL_HB1_ONVALVF_CLR_Pos (31UL) |
BDRV HB1ASEQONVAL: HB1_ONVALVF_CLR (Bit 31)
#define BDRV_HB1ASEQONVAL_HB1_ONVALVF_Msk (0x40000000UL) |
BDRV HB1ASEQONVAL: HB1_ONVALVF (Bitfield-Mask: 0x01)
#define BDRV_HB1ASEQONVAL_HB1_ONVALVF_Pos (30UL) |
BDRV HB1ASEQONVAL: HB1_ONVALVF (Bit 30)
#define BDRV_HB1ASEQONVAL_HB1_T12ONCNT_Msk (0xffUL) |
BDRV HB1ASEQONVAL: HB1_T12ONCNT (Bitfield-Mask: 0xff)
#define BDRV_HB1ASEQONVAL_HB1_T12ONCNT_Pos (0UL) |
BDRV HB1ASEQONVAL: HB1_T12ONCNT (Bit 0)
#define BDRV_HB1ASEQONVAL_HB1_T3MERR_Msk (0x400000UL) |
BDRV HB1ASEQONVAL: HB1_T3MERR (Bitfield-Mask: 0x01)
#define BDRV_HB1ASEQONVAL_HB1_T3MERR_Pos (22UL) |
BDRV HB1ASEQONVAL: HB1_T3MERR (Bit 22)
#define BDRV_HB1ASEQONVAL_HB1_T3ONCNT_Msk (0x3f0000UL) |
BDRV HB1ASEQONVAL: HB1_T3ONCNT (Bitfield-Mask: 0x3f)
#define BDRV_HB1ASEQONVAL_HB1_T3ONCNT_Pos (16UL) |
BDRV HB1ASEQONVAL: HB1_T3ONCNT (Bit 16)
#define BDRV_HB2ASEQOFFVAL_HB2_I1OFFVAL_Msk (0x3f00UL) |
BDRV HB2ASEQOFFVAL: HB2_I1OFFVAL (Bitfield-Mask: 0x3f)
#define BDRV_HB2ASEQOFFVAL_HB2_I1OFFVAL_Pos (8UL) |
BDRV HB2ASEQOFFVAL: HB2_I1OFFVAL (Bit 8)
#define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_CLR_Msk (0x80000000UL) |
BDRV HB2ASEQOFFVAL: HB2_OFFVALVF_CLR (Bitfield-Mask: 0x01)
#define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_CLR_Pos (31UL) |
BDRV HB2ASEQOFFVAL: HB2_OFFVALVF_CLR (Bit 31)
#define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_Msk (0x40000000UL) |
BDRV HB2ASEQOFFVAL: HB2_OFFVALVF (Bitfield-Mask: 0x01)
#define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_Pos (30UL) |
BDRV HB2ASEQOFFVAL: HB2_OFFVALVF (Bit 30)
#define BDRV_HB2ASEQOFFVAL_HB2_T1OFFCNT_Msk (0xffUL) |
BDRV HB2ASEQOFFVAL: HB2_T1OFFCNT (Bitfield-Mask: 0xff)
#define BDRV_HB2ASEQOFFVAL_HB2_T1OFFCNT_Pos (0UL) |
BDRV HB2ASEQOFFVAL: HB2_T1OFFCNT (Bit 0)
#define BDRV_HB2ASEQOFFVAL_HB2_T2MERR_Msk (0x400000UL) |
BDRV HB2ASEQOFFVAL: HB2_T2MERR (Bitfield-Mask: 0x01)
#define BDRV_HB2ASEQOFFVAL_HB2_T2MERR_Pos (22UL) |
BDRV HB2ASEQOFFVAL: HB2_T2MERR (Bit 22)
#define BDRV_HB2ASEQOFFVAL_HB2_T2OFFCNT_Msk (0x3f0000UL) |
BDRV HB2ASEQOFFVAL: HB2_T2OFFCNT (Bitfield-Mask: 0x3f)
#define BDRV_HB2ASEQOFFVAL_HB2_T2OFFCNT_Pos (16UL) |
BDRV HB2ASEQOFFVAL: HB2_T2OFFCNT (Bit 16)
#define BDRV_HB2ASEQONVAL_HB2_I1ONVAL_Msk (0x3f00UL) |
BDRV HB2ASEQONVAL: HB2_I1ONVAL (Bitfield-Mask: 0x3f)
#define BDRV_HB2ASEQONVAL_HB2_I1ONVAL_Pos (8UL) |
BDRV HB2ASEQONVAL: HB2_I1ONVAL (Bit 8)
#define BDRV_HB2ASEQONVAL_HB2_ONVALVF_CLR_Msk (0x80000000UL) |
BDRV HB2ASEQONVAL: HB2_ONVALVF_CLR (Bitfield-Mask: 0x01)
#define BDRV_HB2ASEQONVAL_HB2_ONVALVF_CLR_Pos (31UL) |
BDRV HB2ASEQONVAL: HB2_ONVALVF_CLR (Bit 31)
#define BDRV_HB2ASEQONVAL_HB2_ONVALVF_Msk (0x40000000UL) |
BDRV HB2ASEQONVAL: HB2_ONVALVF (Bitfield-Mask: 0x01)
#define BDRV_HB2ASEQONVAL_HB2_ONVALVF_Pos (30UL) |
BDRV HB2ASEQONVAL: HB2_ONVALVF (Bit 30)
#define BDRV_HB2ASEQONVAL_HB2_T12ONCNT_Msk (0xffUL) |
BDRV HB2ASEQONVAL: HB2_T12ONCNT (Bitfield-Mask: 0xff)
#define BDRV_HB2ASEQONVAL_HB2_T12ONCNT_Pos (0UL) |
BDRV HB2ASEQONVAL: HB2_T12ONCNT (Bit 0)
#define BDRV_HB2ASEQONVAL_HB2_T3MERR_Msk (0x400000UL) |
BDRV HB2ASEQONVAL: HB2_T3MERR (Bitfield-Mask: 0x01)
#define BDRV_HB2ASEQONVAL_HB2_T3MERR_Pos (22UL) |
BDRV HB2ASEQONVAL: HB2_T3MERR (Bit 22)
#define BDRV_HB2ASEQONVAL_HB2_T3ONCNT_Msk (0x3f0000UL) |
BDRV HB2ASEQONVAL: HB2_T3ONCNT (Bitfield-Mask: 0x3f)
#define BDRV_HB2ASEQONVAL_HB2_T3ONCNT_Pos (16UL) |
BDRV HB2ASEQONVAL: HB2_T3ONCNT (Bit 16)
#define BDRV_IGATECLMPOFFC_HB1_ICLMPOFF_Msk (0x3fUL) |
BDRV IGATECLMPOFFC: HB1_ICLMPOFF (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPOFFC_HB1_ICLMPOFF_Pos (0UL) |
BDRV IGATECLMPOFFC: HB1_ICLMPOFF (Bit 0)
#define BDRV_IGATECLMPOFFC_HB1AF_ICLMPOFF_Msk (0x3f0000UL) |
BDRV IGATECLMPOFFC: HB1AF_ICLMPOFF (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPOFFC_HB1AF_ICLMPOFF_Pos (16UL) |
BDRV IGATECLMPOFFC: HB1AF_ICLMPOFF (Bit 16)
#define BDRV_IGATECLMPOFFC_HB2_ICLMPOFF_Msk (0x3f00UL) |
BDRV IGATECLMPOFFC: HB2_ICLMPOFF (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPOFFC_HB2_ICLMPOFF_Pos (8UL) |
BDRV IGATECLMPOFFC: HB2_ICLMPOFF (Bit 8)
#define BDRV_IGATECLMPOFFC_HB2AF_ICLMPOFF_Msk (0x3f000000UL) |
BDRV IGATECLMPOFFC: HB2AF_ICLMPOFF (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPOFFC_HB2AF_ICLMPOFF_Pos (24UL) |
BDRV IGATECLMPOFFC: HB2AF_ICLMPOFF (Bit 24)
#define BDRV_IGATECLMPONC_HB1_ICLMPON_Msk (0x3fUL) |
BDRV IGATECLMPONC: HB1_ICLMPON (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPONC_HB1_ICLMPON_Pos (0UL) |
BDRV IGATECLMPONC: HB1_ICLMPON (Bit 0)
#define BDRV_IGATECLMPONC_HB1AF_ICLMPON_Msk (0x3f0000UL) |
BDRV IGATECLMPONC: HB1AF_ICLMPON (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPONC_HB1AF_ICLMPON_Pos (16UL) |
BDRV IGATECLMPONC: HB1AF_ICLMPON (Bit 16)
#define BDRV_IGATECLMPONC_HB2_ICLMPON_Msk (0x3f00UL) |
BDRV IGATECLMPONC: HB2_ICLMPON (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPONC_HB2_ICLMPON_Pos (8UL) |
BDRV IGATECLMPONC: HB2_ICLMPON (Bit 8)
#define BDRV_IGATECLMPONC_HB2AF_ICLMPON_Msk (0x3f000000UL) |
BDRV IGATECLMPONC: HB2AF_ICLMPON (Bitfield-Mask: 0x3f)
#define BDRV_IGATECLMPONC_HB2AF_ICLMPON_Pos (24UL) |
BDRV IGATECLMPONC: HB2AF_ICLMPON (Bit 24)
#define BDRV_IRQCLR_HB1_ASEQ_ISC_Msk (0x1UL) |
BDRV IRQCLR: HB1_ASEQ_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HB1_ASEQ_ISC_Pos (0UL) |
BDRV IRQCLR: HB1_ASEQ_ISC (Bit 0)
#define BDRV_IRQCLR_HB2_ASEQ_ISC_Msk (0x2UL) |
BDRV IRQCLR: HB2_ASEQ_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HB2_ASEQ_ISC_Pos (1UL) |
BDRV IRQCLR: HB2_ASEQ_ISC (Bit 1)
#define BDRV_IRQCLR_HS1_DS_ISC_Msk (0x100000UL) |
BDRV IRQCLR: HS1_DS_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HS1_DS_ISC_Pos (20UL) |
BDRV IRQCLR: HS1_DS_ISC (Bit 20)
#define BDRV_IRQCLR_HS1_DS_SC_Msk (0x200000UL) |
BDRV IRQCLR: HS1_DS_SC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HS1_DS_SC_Pos (21UL) |
BDRV IRQCLR: HS1_DS_SC (Bit 21)
#define BDRV_IRQCLR_HS1_OC_ISC_Msk (0x400000UL) |
BDRV IRQCLR: HS1_OC_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HS1_OC_ISC_Pos (22UL) |
BDRV IRQCLR: HS1_OC_ISC (Bit 22)
#define BDRV_IRQCLR_HS2_DS_ISC_Msk (0x10000000UL) |
BDRV IRQCLR: HS2_DS_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HS2_DS_ISC_Pos (28UL) |
BDRV IRQCLR: HS2_DS_ISC (Bit 28)
#define BDRV_IRQCLR_HS2_DS_SC_Msk (0x20000000UL) |
BDRV IRQCLR: HS2_DS_SC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HS2_DS_SC_Pos (29UL) |
BDRV IRQCLR: HS2_DS_SC (Bit 29)
#define BDRV_IRQCLR_HS2_OC_ISC_Msk (0x40000000UL) |
BDRV IRQCLR: HS2_OC_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_HS2_OC_ISC_Pos (30UL) |
BDRV IRQCLR: HS2_OC_ISC (Bit 30)
#define BDRV_IRQCLR_LS1_DS_ISC_Msk (0x10UL) |
BDRV IRQCLR: LS1_DS_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_LS1_DS_ISC_Pos (4UL) |
BDRV IRQCLR: LS1_DS_ISC (Bit 4)
#define BDRV_IRQCLR_LS1_DS_SC_Msk (0x20UL) |
BDRV IRQCLR: LS1_DS_SC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_LS1_DS_SC_Pos (5UL) |
BDRV IRQCLR: LS1_DS_SC (Bit 5)
#define BDRV_IRQCLR_LS1_OC_ISC_Msk (0x40UL) |
BDRV IRQCLR: LS1_OC_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_LS1_OC_ISC_Pos (6UL) |
BDRV IRQCLR: LS1_OC_ISC (Bit 6)
#define BDRV_IRQCLR_LS2_DS_ISC_Msk (0x1000UL) |
BDRV IRQCLR: LS2_DS_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_LS2_DS_ISC_Pos (12UL) |
BDRV IRQCLR: LS2_DS_ISC (Bit 12)
#define BDRV_IRQCLR_LS2_DS_SC_Msk (0x2000UL) |
BDRV IRQCLR: LS2_DS_SC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_LS2_DS_SC_Pos (13UL) |
BDRV IRQCLR: LS2_DS_SC (Bit 13)
#define BDRV_IRQCLR_LS2_OC_ISC_Msk (0x4000UL) |
BDRV IRQCLR: LS2_OC_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_LS2_OC_ISC_Pos (14UL) |
BDRV IRQCLR: LS2_OC_ISC (Bit 14)
#define BDRV_IRQCLR_SEQ_ERR_ISC_Msk (0x80000000UL) |
BDRV IRQCLR: SEQ_ERR_ISC (Bitfield-Mask: 0x01)
#define BDRV_IRQCLR_SEQ_ERR_ISC_Pos (31UL) |
BDRV IRQCLR: SEQ_ERR_ISC (Bit 31)
#define BDRV_IRQEN_HB1_ASEQ_IEN_Msk (0x1UL) |
BDRV IRQEN: HB1_ASEQ_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_HB1_ASEQ_IEN_Pos (0UL) |
BDRV IRQEN: HB1_ASEQ_IEN (Bit 0)
#define BDRV_IRQEN_HB2_ASEQ_IEN_Msk (0x2UL) |
BDRV IRQEN: HB2_ASEQ_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_HB2_ASEQ_IEN_Pos (1UL) |
BDRV IRQEN: HB2_ASEQ_IEN (Bit 1)
#define BDRV_IRQEN_HS1_DS_IEN_Msk (0x100000UL) |
BDRV IRQEN: HS1_DS_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_HS1_DS_IEN_Pos (20UL) |
BDRV IRQEN: HS1_DS_IEN (Bit 20)
#define BDRV_IRQEN_HS1_OC_IEN_Msk (0x400000UL) |
BDRV IRQEN: HS1_OC_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_HS1_OC_IEN_Pos (22UL) |
BDRV IRQEN: HS1_OC_IEN (Bit 22)
#define BDRV_IRQEN_HS2_DS_IEN_Msk (0x10000000UL) |
BDRV IRQEN: HS2_DS_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_HS2_DS_IEN_Pos (28UL) |
BDRV IRQEN: HS2_DS_IEN (Bit 28)
#define BDRV_IRQEN_HS2_OC_IEN_Msk (0x40000000UL) |
BDRV IRQEN: HS2_OC_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_HS2_OC_IEN_Pos (30UL) |
BDRV IRQEN: HS2_OC_IEN (Bit 30)
#define BDRV_IRQEN_LS1_DS_IEN_Msk (0x10UL) |
BDRV IRQEN: LS1_DS_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_LS1_DS_IEN_Pos (4UL) |
BDRV IRQEN: LS1_DS_IEN (Bit 4)
#define BDRV_IRQEN_LS1_OC_IEN_Msk (0x40UL) |
BDRV IRQEN: LS1_OC_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_LS1_OC_IEN_Pos (6UL) |
BDRV IRQEN: LS1_OC_IEN (Bit 6)
#define BDRV_IRQEN_LS2_DS_IEN_Msk (0x1000UL) |
BDRV IRQEN: LS2_DS_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_LS2_DS_IEN_Pos (12UL) |
BDRV IRQEN: LS2_DS_IEN (Bit 12)
#define BDRV_IRQEN_LS2_OC_IEN_Msk (0x4000UL) |
BDRV IRQEN: LS2_OC_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_LS2_OC_IEN_Pos (14UL) |
BDRV IRQEN: LS2_OC_IEN (Bit 14)
#define BDRV_IRQEN_SEQ_ERR_IEN_Msk (0x80000000UL) |
BDRV IRQEN: SEQ_ERR_IEN (Bitfield-Mask: 0x01)
#define BDRV_IRQEN_SEQ_ERR_IEN_Pos (31UL) |
BDRV IRQEN: SEQ_ERR_IEN (Bit 31)
#define BDRV_IRQS_HB1_ASEQ_IS_Msk (0x1UL) |
BDRV IRQS: HB1_ASEQ_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HB1_ASEQ_IS_Pos (0UL) |
BDRV IRQS: HB1_ASEQ_IS (Bit 0)
#define BDRV_IRQS_HB2_ASEQ_IS_Msk (0x2UL) |
BDRV IRQS: HB2_ASEQ_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HB2_ASEQ_IS_Pos (1UL) |
BDRV IRQS: HB2_ASEQ_IS (Bit 1)
#define BDRV_IRQS_HS1_DS_IS_Msk (0x100000UL) |
BDRV IRQS: HS1_DS_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HS1_DS_IS_Pos (20UL) |
BDRV IRQS: HS1_DS_IS (Bit 20)
#define BDRV_IRQS_HS1_DS_STS_Msk (0x200000UL) |
BDRV IRQS: HS1_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HS1_DS_STS_Pos (21UL) |
BDRV IRQS: HS1_DS_STS (Bit 21)
#define BDRV_IRQS_HS1_OC_IS_Msk (0x400000UL) |
BDRV IRQS: HS1_OC_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HS1_OC_IS_Pos (22UL) |
BDRV IRQS: HS1_OC_IS (Bit 22)
#define BDRV_IRQS_HS2_DS_IS_Msk (0x10000000UL) |
BDRV IRQS: HS2_DS_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HS2_DS_IS_Pos (28UL) |
BDRV IRQS: HS2_DS_IS (Bit 28)
#define BDRV_IRQS_HS2_DS_STS_Msk (0x20000000UL) |
BDRV IRQS: HS2_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HS2_DS_STS_Pos (29UL) |
BDRV IRQS: HS2_DS_STS (Bit 29)
#define BDRV_IRQS_HS2_OC_IS_Msk (0x40000000UL) |
BDRV IRQS: HS2_OC_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_HS2_OC_IS_Pos (30UL) |
BDRV IRQS: HS2_OC_IS (Bit 30)
#define BDRV_IRQS_LS1_DS_IS_Msk (0x10UL) |
BDRV IRQS: LS1_DS_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_LS1_DS_IS_Pos (4UL) |
BDRV IRQS: LS1_DS_IS (Bit 4)
#define BDRV_IRQS_LS1_DS_STS_Msk (0x20UL) |
BDRV IRQS: LS1_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_LS1_DS_STS_Pos (5UL) |
BDRV IRQS: LS1_DS_STS (Bit 5)
#define BDRV_IRQS_LS1_OC_IS_Msk (0x40UL) |
BDRV IRQS: LS1_OC_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_LS1_OC_IS_Pos (6UL) |
BDRV IRQS: LS1_OC_IS (Bit 6)
#define BDRV_IRQS_LS2_DS_IS_Msk (0x1000UL) |
BDRV IRQS: LS2_DS_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_LS2_DS_IS_Pos (12UL) |
BDRV IRQS: LS2_DS_IS (Bit 12)
#define BDRV_IRQS_LS2_DS_STS_Msk (0x2000UL) |
BDRV IRQS: LS2_DS_STS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_LS2_DS_STS_Pos (13UL) |
BDRV IRQS: LS2_DS_STS (Bit 13)
#define BDRV_IRQS_LS2_OC_IS_Msk (0x4000UL) |
BDRV IRQS: LS2_OC_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_LS2_OC_IS_Pos (14UL) |
BDRV IRQS: LS2_OC_IS (Bit 14)
#define BDRV_IRQS_SEQ_ERR_IS_Msk (0x80000000UL) |
BDRV IRQS: SEQ_ERR_IS (Bitfield-Mask: 0x01)
#define BDRV_IRQS_SEQ_ERR_IS_Pos (31UL) |
BDRV IRQS: SEQ_ERR_IS (Bit 31)
#define BDRV_OFFASEQTMAX_T1OFFMAX_Msk (0xffUL) |
BDRV OFFASEQTMAX: T1OFFMAX (Bitfield-Mask: 0xff)
#define BDRV_OFFASEQTMAX_T1OFFMAX_Pos (0UL) |
BDRV OFFASEQTMAX: T1OFFMAX (Bit 0)
#define BDRV_OFFASEQTMIN_HB1T1OFFADDDLY_Msk (0xf00UL) |
BDRV OFFASEQTMIN: HB1T1OFFADDDLY (Bitfield-Mask: 0x0f)
#define BDRV_OFFASEQTMIN_HB1T1OFFADDDLY_Pos (8UL) |
BDRV OFFASEQTMIN: HB1T1OFFADDDLY (Bit 8)
#define BDRV_OFFASEQTMIN_HB2T1OFFADDDLY_Msk (0xf000UL) |
BDRV OFFASEQTMIN: HB2T1OFFADDDLY (Bitfield-Mask: 0x0f)
#define BDRV_OFFASEQTMIN_HB2T1OFFADDDLY_Pos (12UL) |
BDRV OFFASEQTMIN: HB2T1OFFADDDLY (Bit 12)
#define BDRV_OFFASEQTMIN_T1OFFMIN_Msk (0xffUL) |
BDRV OFFASEQTMIN: T1OFFMIN (Bitfield-Mask: 0xff)
#define BDRV_OFFASEQTMIN_T1OFFMIN_Pos (0UL) |
BDRV OFFASEQTMIN: T1OFFMIN (Bit 0)
#define BDRV_OFFSEQHB1IC_HB1_I1OFF_Msk (0x3fUL) |
BDRV OFFSEQHB1IC: HB1_I1OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB1IC_HB1_I1OFF_Pos (0UL) |
BDRV OFFSEQHB1IC: HB1_I1OFF (Bit 0)
#define BDRV_OFFSEQHB1IC_HB1_I2OFF_Msk (0x3f00UL) |
BDRV OFFSEQHB1IC: HB1_I2OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB1IC_HB1_I2OFF_Pos (8UL) |
BDRV OFFSEQHB1IC: HB1_I2OFF (Bit 8)
#define BDRV_OFFSEQHB1IC_HB1_I3OFF_Msk (0x3f0000UL) |
BDRV OFFSEQHB1IC: HB1_I3OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB1IC_HB1_I3OFF_Pos (16UL) |
BDRV OFFSEQHB1IC: HB1_I3OFF (Bit 16)
#define BDRV_OFFSEQHB1IC_HB1_I4OFF_Msk (0x3f000000UL) |
BDRV OFFSEQHB1IC: HB1_I4OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB1IC_HB1_I4OFF_Pos (24UL) |
BDRV OFFSEQHB1IC: HB1_I4OFF (Bit 24)
#define BDRV_OFFSEQHB1TC_HB1_T1OFF_Msk (0xffUL) |
BDRV OFFSEQHB1TC: HB1_T1OFF (Bitfield-Mask: 0xff)
#define BDRV_OFFSEQHB1TC_HB1_T1OFF_Pos (0UL) |
BDRV OFFSEQHB1TC: HB1_T1OFF (Bit 0)
#define BDRV_OFFSEQHB1TC_HB1_T2OFF_Msk (0x3f00UL) |
BDRV OFFSEQHB1TC: HB1_T2OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB1TC_HB1_T2OFF_Pos (8UL) |
BDRV OFFSEQHB1TC: HB1_T2OFF (Bit 8)
#define BDRV_OFFSEQHB1TC_HB1_T3OFF_Msk (0x3f0000UL) |
BDRV OFFSEQHB1TC: HB1_T3OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB1TC_HB1_T3OFF_Pos (16UL) |
BDRV OFFSEQHB1TC: HB1_T3OFF (Bit 16)
#define BDRV_OFFSEQHB1TC_HB1_T4OFF_Msk (0xff000000UL) |
BDRV OFFSEQHB1TC: HB1_T4OFF (Bitfield-Mask: 0xff)
#define BDRV_OFFSEQHB1TC_HB1_T4OFF_Pos (24UL) |
BDRV OFFSEQHB1TC: HB1_T4OFF (Bit 24)
#define BDRV_OFFSEQHB2IC_HB2_I1OFF_Msk (0x3fUL) |
BDRV OFFSEQHB2IC: HB2_I1OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB2IC_HB2_I1OFF_Pos (0UL) |
BDRV OFFSEQHB2IC: HB2_I1OFF (Bit 0)
#define BDRV_OFFSEQHB2IC_HB2_I2OFF_Msk (0x3f00UL) |
BDRV OFFSEQHB2IC: HB2_I2OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB2IC_HB2_I2OFF_Pos (8UL) |
BDRV OFFSEQHB2IC: HB2_I2OFF (Bit 8)
#define BDRV_OFFSEQHB2IC_HB2_I3OFF_Msk (0x3f0000UL) |
BDRV OFFSEQHB2IC: HB2_I3OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB2IC_HB2_I3OFF_Pos (16UL) |
BDRV OFFSEQHB2IC: HB2_I3OFF (Bit 16)
#define BDRV_OFFSEQHB2IC_HB2_I4OFF_Msk (0x3f000000UL) |
BDRV OFFSEQHB2IC: HB2_I4OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB2IC_HB2_I4OFF_Pos (24UL) |
BDRV OFFSEQHB2IC: HB2_I4OFF (Bit 24)
#define BDRV_OFFSEQHB2TC_HB2_T1OFF_Msk (0xffUL) |
BDRV OFFSEQHB2TC: HB2_T1OFF (Bitfield-Mask: 0xff)
#define BDRV_OFFSEQHB2TC_HB2_T1OFF_Pos (0UL) |
BDRV OFFSEQHB2TC: HB2_T1OFF (Bit 0)
#define BDRV_OFFSEQHB2TC_HB2_T2OFF_Msk (0x3f00UL) |
BDRV OFFSEQHB2TC: HB2_T2OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB2TC_HB2_T2OFF_Pos (8UL) |
BDRV OFFSEQHB2TC: HB2_T2OFF (Bit 8)
#define BDRV_OFFSEQHB2TC_HB2_T3OFF_Msk (0x3f0000UL) |
BDRV OFFSEQHB2TC: HB2_T3OFF (Bitfield-Mask: 0x3f)
#define BDRV_OFFSEQHB2TC_HB2_T3OFF_Pos (16UL) |
BDRV OFFSEQHB2TC: HB2_T3OFF (Bit 16)
#define BDRV_OFFSEQHB2TC_HB2_T4OFF_Msk (0xff000000UL) |
BDRV OFFSEQHB2TC: HB2_T4OFF (Bitfield-Mask: 0xff)
#define BDRV_OFFSEQHB2TC_HB2_T4OFF_Pos (24UL) |
BDRV OFFSEQHB2TC: HB2_T4OFF (Bit 24)
#define BDRV_ONASEQTMAX_T12ONMAX_Msk (0xffUL) |
BDRV ONASEQTMAX: T12ONMAX (Bitfield-Mask: 0xff)
#define BDRV_ONASEQTMAX_T12ONMAX_Pos (0UL) |
BDRV ONASEQTMAX: T12ONMAX (Bit 0)
#define BDRV_ONASEQTMIN_T12ONMIN_Msk (0xffUL) |
BDRV ONASEQTMIN: T12ONMIN (Bitfield-Mask: 0xff)
#define BDRV_ONASEQTMIN_T12ONMIN_Pos (0UL) |
BDRV ONASEQTMIN: T12ONMIN (Bit 0)
#define BDRV_ONSEQHB1IC_HB1_I1ON_Msk (0x3fUL) |
BDRV ONSEQHB1IC: HB1_I1ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB1IC_HB1_I1ON_Pos (0UL) |
BDRV ONSEQHB1IC: HB1_I1ON (Bit 0)
#define BDRV_ONSEQHB1IC_HB1_I2ON_Msk (0x3f00UL) |
BDRV ONSEQHB1IC: HB1_I2ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB1IC_HB1_I2ON_Pos (8UL) |
BDRV ONSEQHB1IC: HB1_I2ON (Bit 8)
#define BDRV_ONSEQHB1IC_HB1_I3ON_Msk (0x3f0000UL) |
BDRV ONSEQHB1IC: HB1_I3ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB1IC_HB1_I3ON_Pos (16UL) |
BDRV ONSEQHB1IC: HB1_I3ON (Bit 16)
#define BDRV_ONSEQHB1IC_HB1_I4ON_Msk (0x3f000000UL) |
BDRV ONSEQHB1IC: HB1_I4ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB1IC_HB1_I4ON_Pos (24UL) |
BDRV ONSEQHB1IC: HB1_I4ON (Bit 24)
#define BDRV_ONSEQHB1TC_HB1_T1ON_Msk (0xffUL) |
BDRV ONSEQHB1TC: HB1_T1ON (Bitfield-Mask: 0xff)
#define BDRV_ONSEQHB1TC_HB1_T1ON_Pos (0UL) |
BDRV ONSEQHB1TC: HB1_T1ON (Bit 0)
#define BDRV_ONSEQHB1TC_HB1_T2ON_Msk (0x3f00UL) |
BDRV ONSEQHB1TC: HB1_T2ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB1TC_HB1_T2ON_Pos (8UL) |
BDRV ONSEQHB1TC: HB1_T2ON (Bit 8)
#define BDRV_ONSEQHB1TC_HB1_T3ON_Msk (0x3f0000UL) |
BDRV ONSEQHB1TC: HB1_T3ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB1TC_HB1_T3ON_Pos (16UL) |
BDRV ONSEQHB1TC: HB1_T3ON (Bit 16)
#define BDRV_ONSEQHB1TC_HB1_T4ON_Msk (0xff000000UL) |
BDRV ONSEQHB1TC: HB1_T4ON (Bitfield-Mask: 0xff)
#define BDRV_ONSEQHB1TC_HB1_T4ON_Pos (24UL) |
BDRV ONSEQHB1TC: HB1_T4ON (Bit 24)
#define BDRV_ONSEQHB2IC_HB2_I1ON_Msk (0x3fUL) |
BDRV ONSEQHB2IC: HB2_I1ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB2IC_HB2_I1ON_Pos (0UL) |
BDRV ONSEQHB2IC: HB2_I1ON (Bit 0)
#define BDRV_ONSEQHB2IC_HB2_I2ON_Msk (0x3f00UL) |
BDRV ONSEQHB2IC: HB2_I2ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB2IC_HB2_I2ON_Pos (8UL) |
BDRV ONSEQHB2IC: HB2_I2ON (Bit 8)
#define BDRV_ONSEQHB2IC_HB2_I3ON_Msk (0x3f0000UL) |
BDRV ONSEQHB2IC: HB2_I3ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB2IC_HB2_I3ON_Pos (16UL) |
BDRV ONSEQHB2IC: HB2_I3ON (Bit 16)
#define BDRV_ONSEQHB2IC_HB2_I4ON_Msk (0x3f000000UL) |
BDRV ONSEQHB2IC: HB2_I4ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB2IC_HB2_I4ON_Pos (24UL) |
BDRV ONSEQHB2IC: HB2_I4ON (Bit 24)
#define BDRV_ONSEQHB2TC_HB2_T1ON_Msk (0xffUL) |
BDRV ONSEQHB2TC: HB2_T1ON (Bitfield-Mask: 0xff)
#define BDRV_ONSEQHB2TC_HB2_T1ON_Pos (0UL) |
BDRV ONSEQHB2TC: HB2_T1ON (Bit 0)
#define BDRV_ONSEQHB2TC_HB2_T2ON_Msk (0x3f00UL) |
BDRV ONSEQHB2TC: HB2_T2ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB2TC_HB2_T2ON_Pos (8UL) |
BDRV ONSEQHB2TC: HB2_T2ON (Bit 8)
#define BDRV_ONSEQHB2TC_HB2_T3ON_Msk (0x3f0000UL) |
BDRV ONSEQHB2TC: HB2_T3ON (Bitfield-Mask: 0x3f)
#define BDRV_ONSEQHB2TC_HB2_T3ON_Pos (16UL) |
BDRV ONSEQHB2TC: HB2_T3ON (Bit 16)
#define BDRV_ONSEQHB2TC_HB2_T4ON_Msk (0xff000000UL) |
BDRV ONSEQHB2TC: HB2_T4ON (Bitfield-Mask: 0xff)
#define BDRV_ONSEQHB2TC_HB2_T4ON_Pos (24UL) |
BDRV ONSEQHB2TC: HB2_T4ON (Bit 24)
#define BDRV_PWMSRCSEL_HS1_SRC_SEL_Msk (0x30000UL) |
BDRV PWMSRCSEL: HS1_SRC_SEL (Bitfield-Mask: 0x03)
#define BDRV_PWMSRCSEL_HS1_SRC_SEL_Pos (16UL) |
BDRV PWMSRCSEL: HS1_SRC_SEL (Bit 16)
#define BDRV_PWMSRCSEL_HS2_SRC_SEL_Msk (0x180000UL) |
BDRV PWMSRCSEL: HS2_SRC_SEL (Bitfield-Mask: 0x03)
#define BDRV_PWMSRCSEL_HS2_SRC_SEL_Pos (19UL) |
BDRV PWMSRCSEL: HS2_SRC_SEL (Bit 19)
#define BDRV_PWMSRCSEL_LS1_SRC_SEL_Msk (0x3UL) |
BDRV PWMSRCSEL: LS1_SRC_SEL (Bitfield-Mask: 0x03)
#define BDRV_PWMSRCSEL_LS1_SRC_SEL_Pos (0UL) |
BDRV PWMSRCSEL: LS1_SRC_SEL (Bit 0)
#define BDRV_PWMSRCSEL_LS2_SRC_SEL_Msk (0x18UL) |
BDRV PWMSRCSEL: LS2_SRC_SEL (Bitfield-Mask: 0x03)
#define BDRV_PWMSRCSEL_LS2_SRC_SEL_Pos (3UL) |
BDRV PWMSRCSEL: LS2_SRC_SEL (Bit 3)
#define BDRV_SEQAFHB1CD_HB1AF_TDICLMPOFF_Msk (0xffUL) |
BDRV SEQAFHB1CD: HB1AF_TDICLMPOFF (Bitfield-Mask: 0xff)
#define BDRV_SEQAFHB1CD_HB1AF_TDICLMPOFF_Pos (0UL) |
BDRV SEQAFHB1CD: HB1AF_TDICLMPOFF (Bit 0)
#define BDRV_SEQAFHB1CD_HB1AF_TDICLMPON_Msk (0xff00UL) |
BDRV SEQAFHB1CD: HB1AF_TDICLMPON (Bitfield-Mask: 0xff)
#define BDRV_SEQAFHB1CD_HB1AF_TDICLMPON_Pos (8UL) |
BDRV SEQAFHB1CD: HB1AF_TDICLMPON (Bit 8)
#define BDRV_SEQAFHB1IC_HB1AF_IOFF_Msk (0x3fUL) |
BDRV SEQAFHB1IC: HB1AF_IOFF (Bitfield-Mask: 0x3f)
#define BDRV_SEQAFHB1IC_HB1AF_IOFF_Pos (0UL) |
BDRV SEQAFHB1IC: HB1AF_IOFF (Bit 0)
#define BDRV_SEQAFHB1IC_HB1AF_ION_Msk (0x3f0000UL) |
BDRV SEQAFHB1IC: HB1AF_ION (Bitfield-Mask: 0x3f)
#define BDRV_SEQAFHB1IC_HB1AF_ION_Pos (16UL) |
BDRV SEQAFHB1IC: HB1AF_ION (Bit 16)
#define BDRV_SEQAFHB2CD_HB2AF_TDICLMPOFF_Msk (0xffUL) |
BDRV SEQAFHB2CD: HB2AF_TDICLMPOFF (Bitfield-Mask: 0xff)
#define BDRV_SEQAFHB2CD_HB2AF_TDICLMPOFF_Pos (0UL) |
BDRV SEQAFHB2CD: HB2AF_TDICLMPOFF (Bit 0)
#define BDRV_SEQAFHB2CD_HB2AF_TDICLMPON_Msk (0xff00UL) |
BDRV SEQAFHB2CD: HB2AF_TDICLMPON (Bitfield-Mask: 0xff)
#define BDRV_SEQAFHB2CD_HB2AF_TDICLMPON_Pos (8UL) |
BDRV SEQAFHB2CD: HB2AF_TDICLMPON (Bit 8)
#define BDRV_SEQAFHB2IC_HB2AF_IOFF_Msk (0x3fUL) |
BDRV SEQAFHB2IC: HB2AF_IOFF (Bitfield-Mask: 0x3f)
#define BDRV_SEQAFHB2IC_HB2AF_IOFF_Pos (0UL) |
BDRV SEQAFHB2IC: HB2AF_IOFF (Bit 0)
#define BDRV_SEQAFHB2IC_HB2AF_ION_Msk (0x3f0000UL) |
BDRV SEQAFHB2IC: HB2AF_ION (Bitfield-Mask: 0x3f)
#define BDRV_SEQAFHB2IC_HB2AF_ION_Pos (16UL) |
BDRV SEQAFHB2IC: HB2AF_ION (Bit 16)
#define BDRV_SEQMAP_HB1_SEQMAP_Msk (0x1UL) |
BDRV SEQMAP: HB1_SEQMAP (Bitfield-Mask: 0x01)
#define BDRV_SEQMAP_HB1_SEQMAP_Pos (0UL) |
BDRV SEQMAP: HB1_SEQMAP (Bit 0)
#define BDRV_SEQMAP_HB2_SEQMAP_Msk (0x4UL) |
BDRV SEQMAP: HB2_SEQMAP (Bitfield-Mask: 0x01)
#define BDRV_SEQMAP_HB2_SEQMAP_Pos (2UL) |
BDRV SEQMAP: HB2_SEQMAP (Bit 2)
#define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Msk (0x30000000UL) |
BDRV TRIM_DRVx: CPLOW_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Pos (28UL) |
BDRV TRIM_DRVx: CPLOW_TFILT_SEL (Bit 28)
#define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Msk (0x100000UL) |
BDRV TRIM_DRVx: HS1DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Pos (20UL) |
BDRV TRIM_DRVx: HS1DRV_FDISCHG_DIS (Bit 20)
#define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Msk (0x1000000UL) |
BDRV TRIM_DRVx: HS1DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Pos (24UL) |
BDRV TRIM_DRVx: HS1DRV_OCSDN_DIS (Bit 24)
#define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Msk (0x200000UL) |
BDRV TRIM_DRVx: HS2DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Pos (21UL) |
BDRV TRIM_DRVx: HS2DRV_FDISCHG_DIS (Bit 21)
#define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Msk (0x2000000UL) |
BDRV TRIM_DRVx: HS2DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Pos (25UL) |
BDRV TRIM_DRVx: HS2DRV_OCSDN_DIS (Bit 25)
#define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Msk (0xc0000UL) |
BDRV TRIM_DRVx: HSDRV_DS_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Pos (18UL) |
BDRV TRIM_DRVx: HSDRV_DS_TFILT_SEL (Bit 18)
#define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Msk (0x400UL) |
BDRV TRIM_DRVx: LS1DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Pos (10UL) |
BDRV TRIM_DRVx: LS1DRV_FDISCHG_DIS (Bit 10)
#define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Msk (0x4000UL) |
BDRV TRIM_DRVx: LS1DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Pos (14UL) |
BDRV TRIM_DRVx: LS1DRV_OCSDN_DIS (Bit 14)
#define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Msk (0x800UL) |
BDRV TRIM_DRVx: LS2DRV_FDISCHG_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Pos (11UL) |
BDRV TRIM_DRVx: LS2DRV_FDISCHG_DIS (Bit 11)
#define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Msk (0x8000UL) |
BDRV TRIM_DRVx: LS2DRV_OCSDN_DIS (Bitfield-Mask: 0x01)
#define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Pos (15UL) |
BDRV TRIM_DRVx: LS2DRV_OCSDN_DIS (Bit 15)
#define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Msk (0x3UL) |
BDRV TRIM_DRVx: LS_HS_BT_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Pos (0UL) |
BDRV TRIM_DRVx: LS_HS_BT_TFILT_SEL (Bit 0)
#define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Msk (0x300UL) |
BDRV TRIM_DRVx: LSDRV_DS_TFILT_SEL (Bitfield-Mask: 0x03)
#define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Pos (8UL) |
BDRV TRIM_DRVx: LSDRV_DS_TFILT_SEL (Bit 8)
#define CCU6_CC60R_CCV_Msk (0xffffUL) |
CCU6 CC60R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC60R_CCV_Pos (0UL) |
CCU6 CC60R: CCV (Bit 0)
#define CCU6_CC60SR_CCS_Msk (0xffffUL) |
CCU6 CC60SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC60SR_CCS_Pos (0UL) |
CCU6 CC60SR: CCS (Bit 0)
#define CCU6_CC61R_CCV_Msk (0xffffUL) |
CCU6 CC61R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC61R_CCV_Pos (0UL) |
CCU6 CC61R: CCV (Bit 0)
#define CCU6_CC61SR_CCS_Msk (0xffffUL) |
CCU6 CC61SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC61SR_CCS_Pos (0UL) |
CCU6 CC61SR: CCS (Bit 0)
#define CCU6_CC62R_CCV_Msk (0xffffUL) |
CCU6 CC62R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC62R_CCV_Pos (0UL) |
CCU6 CC62R: CCV (Bit 0)
#define CCU6_CC62SR_CCS_Msk (0xffffUL) |
CCU6 CC62SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC62SR_CCS_Pos (0UL) |
CCU6 CC62SR: CCS (Bit 0)
#define CCU6_CC63R_CCV_Msk (0xffffUL) |
CCU6 CC63R: CCV (Bitfield-Mask: 0xffff)
#define CCU6_CC63R_CCV_Pos (0UL) |
CCU6 CC63R: CCV (Bit 0)
#define CCU6_CC63SR_CCS_Msk (0xffffUL) |
CCU6 CC63SR: CCS (Bitfield-Mask: 0xffff)
#define CCU6_CC63SR_CCS_Pos (0UL) |
CCU6 CC63SR: CCS (Bit 0)
#define CCU6_CMPMODIF_MCC60R_Msk (0x100UL) |
CCU6 CMPMODIF: MCC60R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC60R_Pos (8UL) |
CCU6 CMPMODIF: MCC60R (Bit 8)
#define CCU6_CMPMODIF_MCC60S_Msk (0x1UL) |
CCU6 CMPMODIF: MCC60S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC60S_Pos (0UL) |
CCU6 CMPMODIF: MCC60S (Bit 0)
#define CCU6_CMPMODIF_MCC61R_Msk (0x200UL) |
CCU6 CMPMODIF: MCC61R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC61R_Pos (9UL) |
CCU6 CMPMODIF: MCC61R (Bit 9)
#define CCU6_CMPMODIF_MCC61S_Msk (0x2UL) |
CCU6 CMPMODIF: MCC61S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC61S_Pos (1UL) |
CCU6 CMPMODIF: MCC61S (Bit 1)
#define CCU6_CMPMODIF_MCC62R_Msk (0x400UL) |
CCU6 CMPMODIF: MCC62R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC62R_Pos (10UL) |
CCU6 CMPMODIF: MCC62R (Bit 10)
#define CCU6_CMPMODIF_MCC62S_Msk (0x4UL) |
CCU6 CMPMODIF: MCC62S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC62S_Pos (2UL) |
CCU6 CMPMODIF: MCC62S (Bit 2)
#define CCU6_CMPMODIF_MCC63R_Msk (0x4000UL) |
CCU6 CMPMODIF: MCC63R (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC63R_Pos (14UL) |
CCU6 CMPMODIF: MCC63R (Bit 14)
#define CCU6_CMPMODIF_MCC63S_Msk (0x40UL) |
CCU6 CMPMODIF: MCC63S (Bitfield-Mask: 0x01)
#define CCU6_CMPMODIF_MCC63S_Pos (6UL) |
CCU6 CMPMODIF: MCC63S (Bit 6)
#define CCU6_CMPSTAT_CC60PS_Msk (0x100UL) |
CCU6 CMPSTAT: CC60PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC60PS_Pos (8UL) |
CCU6 CMPSTAT: CC60PS (Bit 8)
#define CCU6_CMPSTAT_CC60ST_Msk (0x1UL) |
CCU6 CMPSTAT: CC60ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC60ST_Pos (0UL) |
CCU6 CMPSTAT: CC60ST (Bit 0)
#define CCU6_CMPSTAT_CC61PS_Msk (0x400UL) |
CCU6 CMPSTAT: CC61PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC61PS_Pos (10UL) |
CCU6 CMPSTAT: CC61PS (Bit 10)
#define CCU6_CMPSTAT_CC61ST_Msk (0x2UL) |
CCU6 CMPSTAT: CC61ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC61ST_Pos (1UL) |
CCU6 CMPSTAT: CC61ST (Bit 1)
#define CCU6_CMPSTAT_CC62PS_Msk (0x1000UL) |
CCU6 CMPSTAT: CC62PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC62PS_Pos (12UL) |
CCU6 CMPSTAT: CC62PS (Bit 12)
#define CCU6_CMPSTAT_CC62ST_Msk (0x4UL) |
CCU6 CMPSTAT: CC62ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC62ST_Pos (2UL) |
CCU6 CMPSTAT: CC62ST (Bit 2)
#define CCU6_CMPSTAT_CC63ST_Msk (0x40UL) |
CCU6 CMPSTAT: CC63ST (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CC63ST_Pos (6UL) |
CCU6 CMPSTAT: CC63ST (Bit 6)
#define CCU6_CMPSTAT_CCPOS0_Msk (0x8UL) |
CCU6 CMPSTAT: CCPOS0 (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CCPOS0_Pos (3UL) |
CCU6 CMPSTAT: CCPOS0 (Bit 3)
#define CCU6_CMPSTAT_CCPOS1_Msk (0x10UL) |
CCU6 CMPSTAT: CCPOS1 (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CCPOS1_Pos (4UL) |
CCU6 CMPSTAT: CCPOS1 (Bit 4)
#define CCU6_CMPSTAT_CCPOS2_Msk (0x20UL) |
CCU6 CMPSTAT: CCPOS2 (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_CCPOS2_Pos (5UL) |
CCU6 CMPSTAT: CCPOS2 (Bit 5)
#define CCU6_CMPSTAT_COUT60PS_Msk (0x200UL) |
CCU6 CMPSTAT: COUT60PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT60PS_Pos (9UL) |
CCU6 CMPSTAT: COUT60PS (Bit 9)
#define CCU6_CMPSTAT_COUT61PS_Msk (0x800UL) |
CCU6 CMPSTAT: COUT61PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT61PS_Pos (11UL) |
CCU6 CMPSTAT: COUT61PS (Bit 11)
#define CCU6_CMPSTAT_COUT62PS_Msk (0x2000UL) |
CCU6 CMPSTAT: COUT62PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT62PS_Pos (13UL) |
CCU6 CMPSTAT: COUT62PS (Bit 13)
#define CCU6_CMPSTAT_COUT63PS_Msk (0x4000UL) |
CCU6 CMPSTAT: COUT63PS (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_COUT63PS_Pos (14UL) |
CCU6 CMPSTAT: COUT63PS (Bit 14)
#define CCU6_CMPSTAT_T13IM_Msk (0x8000UL) |
CCU6 CMPSTAT: T13IM (Bitfield-Mask: 0x01)
#define CCU6_CMPSTAT_T13IM_Pos (15UL) |
CCU6 CMPSTAT: T13IM (Bit 15)
#define CCU6_IEN_ENCC60F_Msk (0x2UL) |
CCU6 IEN: ENCC60F (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC60F_Pos (1UL) |
CCU6 IEN: ENCC60F (Bit 1)
#define CCU6_IEN_ENCC60R_Msk (0x1UL) |
CCU6 IEN: ENCC60R (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC60R_Pos (0UL) |
CCU6 IEN: ENCC60R (Bit 0)
#define CCU6_IEN_ENCC61F_Msk (0x8UL) |
CCU6 IEN: ENCC61F (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC61F_Pos (3UL) |
CCU6 IEN: ENCC61F (Bit 3)
#define CCU6_IEN_ENCC61R_Msk (0x4UL) |
CCU6 IEN: ENCC61R (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC61R_Pos (2UL) |
CCU6 IEN: ENCC61R (Bit 2)
#define CCU6_IEN_ENCC62F_Msk (0x20UL) |
CCU6 IEN: ENCC62F (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC62F_Pos (5UL) |
CCU6 IEN: ENCC62F (Bit 5)
#define CCU6_IEN_ENCC62R_Msk (0x10UL) |
CCU6 IEN: ENCC62R (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCC62R_Pos (4UL) |
CCU6 IEN: ENCC62R (Bit 4)
#define CCU6_IEN_ENCHE_Msk (0x1000UL) |
CCU6 IEN: ENCHE (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENCHE_Pos (12UL) |
CCU6 IEN: ENCHE (Bit 12)
#define CCU6_IEN_ENIDLE_Msk (0x4000UL) |
CCU6 IEN: ENIDLE (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENIDLE_Pos (14UL) |
CCU6 IEN: ENIDLE (Bit 14)
#define CCU6_IEN_ENSTR_Msk (0x8000UL) |
CCU6 IEN: ENSTR (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENSTR_Pos (15UL) |
CCU6 IEN: ENSTR (Bit 15)
#define CCU6_IEN_ENT12OM_Msk (0x40UL) |
CCU6 IEN: ENT12OM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT12OM_Pos (6UL) |
CCU6 IEN: ENT12OM (Bit 6)
#define CCU6_IEN_ENT12PM_Msk (0x80UL) |
CCU6 IEN: ENT12PM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT12PM_Pos (7UL) |
CCU6 IEN: ENT12PM (Bit 7)
#define CCU6_IEN_ENT13CM_Msk (0x100UL) |
CCU6 IEN: ENT13CM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT13CM_Pos (8UL) |
CCU6 IEN: ENT13CM (Bit 8)
#define CCU6_IEN_ENT13PM_Msk (0x200UL) |
CCU6 IEN: ENT13PM (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENT13PM_Pos (9UL) |
CCU6 IEN: ENT13PM (Bit 9)
#define CCU6_IEN_ENTRPF_Msk (0x400UL) |
CCU6 IEN: ENTRPF (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENTRPF_Pos (10UL) |
CCU6 IEN: ENTRPF (Bit 10)
#define CCU6_IEN_ENWHE_Msk (0x2000UL) |
CCU6 IEN: ENWHE (Bitfield-Mask: 0x01)
#define CCU6_IEN_ENWHE_Pos (13UL) |
CCU6 IEN: ENWHE (Bit 13)
#define CCU6_INP_INPCC60_Msk (0x3UL) |
CCU6 INP: INPCC60 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCC60_Pos (0UL) |
CCU6 INP: INPCC60 (Bit 0)
#define CCU6_INP_INPCC61_Msk (0xcUL) |
CCU6 INP: INPCC61 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCC61_Pos (2UL) |
CCU6 INP: INPCC61 (Bit 2)
#define CCU6_INP_INPCC62_Msk (0x30UL) |
CCU6 INP: INPCC62 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCC62_Pos (4UL) |
CCU6 INP: INPCC62 (Bit 4)
#define CCU6_INP_INPCHE_Msk (0xc0UL) |
CCU6 INP: INPCHE (Bitfield-Mask: 0x03)
#define CCU6_INP_INPCHE_Pos (6UL) |
CCU6 INP: INPCHE (Bit 6)
#define CCU6_INP_INPERR_Msk (0x300UL) |
CCU6 INP: INPERR (Bitfield-Mask: 0x03)
#define CCU6_INP_INPERR_Pos (8UL) |
CCU6 INP: INPERR (Bit 8)
#define CCU6_INP_INPT12_Msk (0xc00UL) |
CCU6 INP: INPT12 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPT12_Pos (10UL) |
CCU6 INP: INPT12 (Bit 10)
#define CCU6_INP_INPT13_Msk (0x3000UL) |
CCU6 INP: INPT13 (Bitfield-Mask: 0x03)
#define CCU6_INP_INPT13_Pos (12UL) |
CCU6 INP: INPT13 (Bit 12)
#define CCU6_IS_CHE_Msk (0x1000UL) |
CCU6 IS: CHE (Bitfield-Mask: 0x01)
#define CCU6_IS_CHE_Pos (12UL) |
CCU6 IS: CHE (Bit 12)
#define CCU6_IS_ICC60F_Msk (0x2UL) |
CCU6 IS: ICC60F (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC60F_Pos (1UL) |
CCU6 IS: ICC60F (Bit 1)
#define CCU6_IS_ICC60R_Msk (0x1UL) |
CCU6 IS: ICC60R (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC60R_Pos (0UL) |
CCU6 IS: ICC60R (Bit 0)
#define CCU6_IS_ICC61F_Msk (0x8UL) |
CCU6 IS: ICC61F (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC61F_Pos (3UL) |
CCU6 IS: ICC61F (Bit 3)
#define CCU6_IS_ICC61R_Msk (0x4UL) |
CCU6 IS: ICC61R (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC61R_Pos (2UL) |
CCU6 IS: ICC61R (Bit 2)
#define CCU6_IS_ICC62F_Msk (0x20UL) |
CCU6 IS: ICC62F (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC62F_Pos (5UL) |
CCU6 IS: ICC62F (Bit 5)
#define CCU6_IS_ICC62R_Msk (0x10UL) |
CCU6 IS: ICC62R (Bitfield-Mask: 0x01)
#define CCU6_IS_ICC62R_Pos (4UL) |
CCU6 IS: ICC62R (Bit 4)
#define CCU6_IS_IDLE_Msk (0x4000UL) |
CCU6 IS: IDLE (Bitfield-Mask: 0x01)
#define CCU6_IS_IDLE_Pos (14UL) |
CCU6 IS: IDLE (Bit 14)
#define CCU6_IS_STR_Msk (0x8000UL) |
CCU6 IS: STR (Bitfield-Mask: 0x01)
#define CCU6_IS_STR_Pos (15UL) |
CCU6 IS: STR (Bit 15)
#define CCU6_IS_T12OM_Msk (0x40UL) |
CCU6 IS: T12OM (Bitfield-Mask: 0x01)
#define CCU6_IS_T12OM_Pos (6UL) |
CCU6 IS: T12OM (Bit 6)
#define CCU6_IS_T12PM_Msk (0x80UL) |
CCU6 IS: T12PM (Bitfield-Mask: 0x01)
#define CCU6_IS_T12PM_Pos (7UL) |
CCU6 IS: T12PM (Bit 7)
#define CCU6_IS_T13CM_Msk (0x100UL) |
CCU6 IS: T13CM (Bitfield-Mask: 0x01)
#define CCU6_IS_T13CM_Pos (8UL) |
CCU6 IS: T13CM (Bit 8)
#define CCU6_IS_T13PM_Msk (0x200UL) |
CCU6 IS: T13PM (Bitfield-Mask: 0x01)
#define CCU6_IS_T13PM_Pos (9UL) |
CCU6 IS: T13PM (Bit 9)
#define CCU6_IS_TRPF_Msk (0x400UL) |
CCU6 IS: TRPF (Bitfield-Mask: 0x01)
#define CCU6_IS_TRPF_Pos (10UL) |
CCU6 IS: TRPF (Bit 10)
#define CCU6_IS_TRPS_Msk (0x800UL) |
CCU6 IS: TRPS (Bitfield-Mask: 0x01)
#define CCU6_IS_TRPS_Pos (11UL) |
CCU6 IS: TRPS (Bit 11)
#define CCU6_IS_WHE_Msk (0x2000UL) |
CCU6 IS: WHE (Bitfield-Mask: 0x01)
#define CCU6_IS_WHE_Pos (13UL) |
CCU6 IS: WHE (Bit 13)
#define CCU6_ISR_RCC60F_Msk (0x2UL) |
CCU6 ISR: RCC60F (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC60F_Pos (1UL) |
CCU6 ISR: RCC60F (Bit 1)
#define CCU6_ISR_RCC60R_Msk (0x1UL) |
CCU6 ISR: RCC60R (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC60R_Pos (0UL) |
CCU6 ISR: RCC60R (Bit 0)
#define CCU6_ISR_RCC61F_Msk (0x8UL) |
CCU6 ISR: RCC61F (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC61F_Pos (3UL) |
CCU6 ISR: RCC61F (Bit 3)
#define CCU6_ISR_RCC61R_Msk (0x4UL) |
CCU6 ISR: RCC61R (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC61R_Pos (2UL) |
CCU6 ISR: RCC61R (Bit 2)
#define CCU6_ISR_RCC62F_Msk (0x20UL) |
CCU6 ISR: RCC62F (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC62F_Pos (5UL) |
CCU6 ISR: RCC62F (Bit 5)
#define CCU6_ISR_RCC62R_Msk (0x10UL) |
CCU6 ISR: RCC62R (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCC62R_Pos (4UL) |
CCU6 ISR: RCC62R (Bit 4)
#define CCU6_ISR_RCHE_Msk (0x1000UL) |
CCU6 ISR: RCHE (Bitfield-Mask: 0x01)
#define CCU6_ISR_RCHE_Pos (12UL) |
CCU6 ISR: RCHE (Bit 12)
#define CCU6_ISR_RIDLE_Msk (0x4000UL) |
CCU6 ISR: RIDLE (Bitfield-Mask: 0x01)
#define CCU6_ISR_RIDLE_Pos (14UL) |
CCU6 ISR: RIDLE (Bit 14)
#define CCU6_ISR_RSTR_Msk (0x8000UL) |
CCU6 ISR: RSTR (Bitfield-Mask: 0x01)
#define CCU6_ISR_RSTR_Pos (15UL) |
CCU6 ISR: RSTR (Bit 15)
#define CCU6_ISR_RT12OM_Msk (0x40UL) |
CCU6 ISR: RT12OM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT12OM_Pos (6UL) |
CCU6 ISR: RT12OM (Bit 6)
#define CCU6_ISR_RT12PM_Msk (0x80UL) |
CCU6 ISR: RT12PM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT12PM_Pos (7UL) |
CCU6 ISR: RT12PM (Bit 7)
#define CCU6_ISR_RT13CM_Msk (0x100UL) |
CCU6 ISR: RT13CM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT13CM_Pos (8UL) |
CCU6 ISR: RT13CM (Bit 8)
#define CCU6_ISR_RT13PM_Msk (0x200UL) |
CCU6 ISR: RT13PM (Bitfield-Mask: 0x01)
#define CCU6_ISR_RT13PM_Pos (9UL) |
CCU6 ISR: RT13PM (Bit 9)
#define CCU6_ISR_RTRPF_Msk (0x400UL) |
CCU6 ISR: RTRPF (Bitfield-Mask: 0x01)
#define CCU6_ISR_RTRPF_Pos (10UL) |
CCU6 ISR: RTRPF (Bit 10)
#define CCU6_ISR_RWHE_Msk (0x2000UL) |
CCU6 ISR: RWHE (Bitfield-Mask: 0x01)
#define CCU6_ISR_RWHE_Pos (13UL) |
CCU6 ISR: RWHE (Bit 13)
#define CCU6_ISS_SCC60F_Msk (0x2UL) |
CCU6 ISS: SCC60F (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC60F_Pos (1UL) |
CCU6 ISS: SCC60F (Bit 1)
#define CCU6_ISS_SCC60R_Msk (0x1UL) |
CCU6 ISS: SCC60R (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC60R_Pos (0UL) |
CCU6 ISS: SCC60R (Bit 0)
#define CCU6_ISS_SCC61F_Msk (0x8UL) |
CCU6 ISS: SCC61F (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC61F_Pos (3UL) |
CCU6 ISS: SCC61F (Bit 3)
#define CCU6_ISS_SCC61R_Msk (0x4UL) |
CCU6 ISS: SCC61R (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC61R_Pos (2UL) |
CCU6 ISS: SCC61R (Bit 2)
#define CCU6_ISS_SCC62F_Msk (0x20UL) |
CCU6 ISS: SCC62F (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC62F_Pos (5UL) |
CCU6 ISS: SCC62F (Bit 5)
#define CCU6_ISS_SCC62R_Msk (0x10UL) |
CCU6 ISS: SCC62R (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCC62R_Pos (4UL) |
CCU6 ISS: SCC62R (Bit 4)
#define CCU6_ISS_SCHE_Msk (0x1000UL) |
CCU6 ISS: SCHE (Bitfield-Mask: 0x01)
#define CCU6_ISS_SCHE_Pos (12UL) |
CCU6 ISS: SCHE (Bit 12)
#define CCU6_ISS_SIDLE_Msk (0x4000UL) |
CCU6 ISS: SIDLE (Bitfield-Mask: 0x01)
#define CCU6_ISS_SIDLE_Pos (14UL) |
CCU6 ISS: SIDLE (Bit 14)
#define CCU6_ISS_SSTR_Msk (0x8000UL) |
CCU6 ISS: SSTR (Bitfield-Mask: 0x01)
#define CCU6_ISS_SSTR_Pos (15UL) |
CCU6 ISS: SSTR (Bit 15)
#define CCU6_ISS_ST12OM_Msk (0x40UL) |
CCU6 ISS: ST12OM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST12OM_Pos (6UL) |
CCU6 ISS: ST12OM (Bit 6)
#define CCU6_ISS_ST12PM_Msk (0x80UL) |
CCU6 ISS: ST12PM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST12PM_Pos (7UL) |
CCU6 ISS: ST12PM (Bit 7)
#define CCU6_ISS_ST13CM_Msk (0x100UL) |
CCU6 ISS: ST13CM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST13CM_Pos (8UL) |
CCU6 ISS: ST13CM (Bit 8)
#define CCU6_ISS_ST13PM_Msk (0x200UL) |
CCU6 ISS: ST13PM (Bitfield-Mask: 0x01)
#define CCU6_ISS_ST13PM_Pos (9UL) |
CCU6 ISS: ST13PM (Bit 9)
#define CCU6_ISS_STRPF_Msk (0x400UL) |
CCU6 ISS: STRPF (Bitfield-Mask: 0x01)
#define CCU6_ISS_STRPF_Pos (10UL) |
CCU6 ISS: STRPF (Bit 10)
#define CCU6_ISS_SWHC_Msk (0x800UL) |
CCU6 ISS: SWHC (Bitfield-Mask: 0x01)
#define CCU6_ISS_SWHC_Pos (11UL) |
CCU6 ISS: SWHC (Bit 11)
#define CCU6_ISS_SWHE_Msk (0x2000UL) |
CCU6 ISS: SWHE (Bitfield-Mask: 0x01)
#define CCU6_ISS_SWHE_Pos (13UL) |
CCU6 ISS: SWHE (Bit 13)
#define CCU6_MCMCTR_STE12D_Msk (0x200UL) |
CCU6 MCMCTR: STE12D (Bitfield-Mask: 0x01)
#define CCU6_MCMCTR_STE12D_Pos (9UL) |
CCU6 MCMCTR: STE12D (Bit 9)
#define CCU6_MCMCTR_STE12U_Msk (0x100UL) |
CCU6 MCMCTR: STE12U (Bitfield-Mask: 0x01)
#define CCU6_MCMCTR_STE12U_Pos (8UL) |
CCU6 MCMCTR: STE12U (Bit 8)
#define CCU6_MCMCTR_STE13U_Msk (0x400UL) |
CCU6 MCMCTR: STE13U (Bitfield-Mask: 0x01)
#define CCU6_MCMCTR_STE13U_Pos (10UL) |
CCU6 MCMCTR: STE13U (Bit 10)
#define CCU6_MCMCTR_SWSEL_Msk (0x7UL) |
CCU6 MCMCTR: SWSEL (Bitfield-Mask: 0x07)
#define CCU6_MCMCTR_SWSEL_Pos (0UL) |
CCU6 MCMCTR: SWSEL (Bit 0)
#define CCU6_MCMCTR_SWSYN_Msk (0x30UL) |
CCU6 MCMCTR: SWSYN (Bitfield-Mask: 0x03)
#define CCU6_MCMCTR_SWSYN_Pos (4UL) |
CCU6 MCMCTR: SWSYN (Bit 4)
#define CCU6_MCMOUT_CURH_Msk (0x3800UL) |
CCU6 MCMOUT: CURH (Bitfield-Mask: 0x07)
#define CCU6_MCMOUT_CURH_Pos (11UL) |
CCU6 MCMOUT: CURH (Bit 11)
#define CCU6_MCMOUT_EXPH_Msk (0x700UL) |
CCU6 MCMOUT: EXPH (Bitfield-Mask: 0x07)
#define CCU6_MCMOUT_EXPH_Pos (8UL) |
CCU6 MCMOUT: EXPH (Bit 8)
#define CCU6_MCMOUT_MCMP_Msk (0x3fUL) |
CCU6 MCMOUT: MCMP (Bitfield-Mask: 0x3f)
#define CCU6_MCMOUT_MCMP_Pos (0UL) |
CCU6 MCMOUT: MCMP (Bit 0)
#define CCU6_MCMOUT_R_Msk (0x40UL) |
CCU6 MCMOUT: R (Bitfield-Mask: 0x01)
#define CCU6_MCMOUT_R_Pos (6UL) |
CCU6 MCMOUT: R (Bit 6)
#define CCU6_MCMOUTS_CURHS_Msk (0x3800UL) |
CCU6 MCMOUTS: CURHS (Bitfield-Mask: 0x07)
#define CCU6_MCMOUTS_CURHS_Pos (11UL) |
CCU6 MCMOUTS: CURHS (Bit 11)
#define CCU6_MCMOUTS_EXPHS_Msk (0x700UL) |
CCU6 MCMOUTS: EXPHS (Bitfield-Mask: 0x07)
#define CCU6_MCMOUTS_EXPHS_Pos (8UL) |
CCU6 MCMOUTS: EXPHS (Bit 8)
#define CCU6_MCMOUTS_MCMPS_Msk (0x3fUL) |
CCU6 MCMOUTS: MCMPS (Bitfield-Mask: 0x3f)
#define CCU6_MCMOUTS_MCMPS_Pos (0UL) |
CCU6 MCMOUTS: MCMPS (Bit 0)
#define CCU6_MCMOUTS_STRHP_Msk (0x8000UL) |
CCU6 MCMOUTS: STRHP (Bitfield-Mask: 0x01)
#define CCU6_MCMOUTS_STRHP_Pos (15UL) |
CCU6 MCMOUTS: STRHP (Bit 15)
#define CCU6_MCMOUTS_STRMCM_Msk (0x80UL) |
CCU6 MCMOUTS: STRMCM (Bitfield-Mask: 0x01)
#define CCU6_MCMOUTS_STRMCM_Pos (7UL) |
CCU6 MCMOUTS: STRMCM (Bit 7)
#define CCU6_MODCTR_ECT13O_Msk (0x8000UL) |
CCU6 MODCTR: ECT13O (Bitfield-Mask: 0x01)
#define CCU6_MODCTR_ECT13O_Pos (15UL) |
CCU6 MODCTR: ECT13O (Bit 15)
#define CCU6_MODCTR_MCMEN_Msk (0x80UL) |
CCU6 MODCTR: MCMEN (Bitfield-Mask: 0x01)
#define CCU6_MODCTR_MCMEN_Pos (7UL) |
CCU6 MODCTR: MCMEN (Bit 7)
#define CCU6_MODCTR_T12MODEN_Msk (0x3fUL) |
CCU6 MODCTR: T12MODEN (Bitfield-Mask: 0x3f)
#define CCU6_MODCTR_T12MODEN_Pos (0UL) |
CCU6 MODCTR: T12MODEN (Bit 0)
#define CCU6_MODCTR_T13MODEN_Msk (0x3f00UL) |
CCU6 MODCTR: T13MODEN (Bitfield-Mask: 0x3f)
#define CCU6_MODCTR_T13MODEN_Pos (8UL) |
CCU6 MODCTR: T13MODEN (Bit 8)
#define CCU6_PISEL0_ISCC60_Msk (0x3UL) |
CCU6 PISEL0: ISCC60 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISCC60_Pos (0UL) |
CCU6 PISEL0: ISCC60 (Bit 0)
#define CCU6_PISEL0_ISCC61_Msk (0xcUL) |
CCU6 PISEL0: ISCC61 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISCC61_Pos (2UL) |
CCU6 PISEL0: ISCC61 (Bit 2)
#define CCU6_PISEL0_ISCC62_Msk (0x30UL) |
CCU6 PISEL0: ISCC62 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISCC62_Pos (4UL) |
CCU6 PISEL0: ISCC62 (Bit 4)
#define CCU6_PISEL0_ISPOS0_Msk (0x300UL) |
CCU6 PISEL0: ISPOS0 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISPOS0_Pos (8UL) |
CCU6 PISEL0: ISPOS0 (Bit 8)
#define CCU6_PISEL0_ISPOS1_Msk (0xc00UL) |
CCU6 PISEL0: ISPOS1 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISPOS1_Pos (10UL) |
CCU6 PISEL0: ISPOS1 (Bit 10)
#define CCU6_PISEL0_ISPOS2_Msk (0x3000UL) |
CCU6 PISEL0: ISPOS2 (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISPOS2_Pos (12UL) |
CCU6 PISEL0: ISPOS2 (Bit 12)
#define CCU6_PISEL0_IST12HR_Msk (0xc000UL) |
CCU6 PISEL0: IST12HR (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_IST12HR_Pos (14UL) |
CCU6 PISEL0: IST12HR (Bit 14)
#define CCU6_PISEL0_ISTRP_Msk (0xc0UL) |
CCU6 PISEL0: ISTRP (Bitfield-Mask: 0x03)
#define CCU6_PISEL0_ISTRP_Pos (6UL) |
CCU6 PISEL0: ISTRP (Bit 6)
#define CCU6_PISEL2_ISCNT12_Msk (0xcUL) |
CCU6 PISEL2: ISCNT12 (Bitfield-Mask: 0x03)
#define CCU6_PISEL2_ISCNT12_Pos (2UL) |
CCU6 PISEL2: ISCNT12 (Bit 2)
#define CCU6_PISEL2_ISCNT13_Msk (0x30UL) |
CCU6 PISEL2: ISCNT13 (Bitfield-Mask: 0x03)
#define CCU6_PISEL2_ISCNT13_Pos (4UL) |
CCU6 PISEL2: ISCNT13 (Bit 4)
#define CCU6_PISEL2_IST13HR_Msk (0x3UL) |
CCU6 PISEL2: IST13HR (Bitfield-Mask: 0x03)
#define CCU6_PISEL2_IST13HR_Pos (0UL) |
CCU6 PISEL2: IST13HR (Bit 0)
#define CCU6_PISEL2_T12EXT_Msk (0x40UL) |
CCU6 PISEL2: T12EXT (Bitfield-Mask: 0x01)
#define CCU6_PISEL2_T12EXT_Pos (6UL) |
CCU6 PISEL2: T12EXT (Bit 6)
#define CCU6_PISEL2_T13EXT_Msk (0x80UL) |
CCU6 PISEL2: T13EXT (Bitfield-Mask: 0x01)
#define CCU6_PISEL2_T13EXT_Pos (7UL) |
CCU6 PISEL2: T13EXT (Bit 7)
#define CCU6_PSLR_PSL63_Msk (0x80UL) |
CCU6 PSLR: PSL63 (Bitfield-Mask: 0x01)
#define CCU6_PSLR_PSL63_Pos (7UL) |
CCU6 PSLR: PSL63 (Bit 7)
#define CCU6_PSLR_PSL_Msk (0x3fUL) |
CCU6 PSLR: PSL (Bitfield-Mask: 0x3f)
#define CCU6_PSLR_PSL_Pos (0UL) |
CCU6 PSLR: PSL (Bit 0)
#define CCU6_T12_T12CV_Msk (0xffffUL) |
CCU6 T12: T12CV (Bitfield-Mask: 0xffff)
#define CCU6_T12_T12CV_Pos (0UL) |
CCU6 T12: T12CV (Bit 0)
#define CCU6_T12DTC_DTE0_Msk (0x100UL) |
CCU6 T12DTC: DTE0 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTE0_Pos (8UL) |
CCU6 T12DTC: DTE0 (Bit 8)
#define CCU6_T12DTC_DTE1_Msk (0x200UL) |
CCU6 T12DTC: DTE1 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTE1_Pos (9UL) |
CCU6 T12DTC: DTE1 (Bit 9)
#define CCU6_T12DTC_DTE2_Msk (0x400UL) |
CCU6 T12DTC: DTE2 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTE2_Pos (10UL) |
CCU6 T12DTC: DTE2 (Bit 10)
#define CCU6_T12DTC_DTM_Msk (0xffUL) |
CCU6 T12DTC: DTM (Bitfield-Mask: 0xff)
#define CCU6_T12DTC_DTM_Pos (0UL) |
CCU6 T12DTC: DTM (Bit 0)
#define CCU6_T12DTC_DTR0_Msk (0x1000UL) |
CCU6 T12DTC: DTR0 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTR0_Pos (12UL) |
CCU6 T12DTC: DTR0 (Bit 12)
#define CCU6_T12DTC_DTR1_Msk (0x2000UL) |
CCU6 T12DTC: DTR1 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTR1_Pos (13UL) |
CCU6 T12DTC: DTR1 (Bit 13)
#define CCU6_T12DTC_DTR2_Msk (0x4000UL) |
CCU6 T12DTC: DTR2 (Bitfield-Mask: 0x01)
#define CCU6_T12DTC_DTR2_Pos (14UL) |
CCU6 T12DTC: DTR2 (Bit 14)
#define CCU6_T12MSEL_DBYP_Msk (0x8000UL) |
CCU6 T12MSEL: DBYP (Bitfield-Mask: 0x01)
#define CCU6_T12MSEL_DBYP_Pos (15UL) |
CCU6 T12MSEL: DBYP (Bit 15)
#define CCU6_T12MSEL_HSYNC_Msk (0x7000UL) |
CCU6 T12MSEL: HSYNC (Bitfield-Mask: 0x07)
#define CCU6_T12MSEL_HSYNC_Pos (12UL) |
CCU6 T12MSEL: HSYNC (Bit 12)
#define CCU6_T12MSEL_MSEL60_Msk (0xfUL) |
CCU6 T12MSEL: MSEL60 (Bitfield-Mask: 0x0f)
#define CCU6_T12MSEL_MSEL60_Pos (0UL) |
CCU6 T12MSEL: MSEL60 (Bit 0)
#define CCU6_T12MSEL_MSEL61_Msk (0xf0UL) |
CCU6 T12MSEL: MSEL61 (Bitfield-Mask: 0x0f)
#define CCU6_T12MSEL_MSEL61_Pos (4UL) |
CCU6 T12MSEL: MSEL61 (Bit 4)
#define CCU6_T12MSEL_MSEL62_Msk (0xf00UL) |
CCU6 T12MSEL: MSEL62 (Bitfield-Mask: 0x0f)
#define CCU6_T12MSEL_MSEL62_Pos (8UL) |
CCU6 T12MSEL: MSEL62 (Bit 8)
#define CCU6_T12PR_T12PV_Msk (0xffffUL) |
CCU6 T12PR: T12PV (Bitfield-Mask: 0xffff)
#define CCU6_T12PR_T12PV_Pos (0UL) |
CCU6 T12PR: T12PV (Bit 0)
#define CCU6_T13_T13CV_Msk (0xffffUL) |
CCU6 T13: T13CV (Bitfield-Mask: 0xffff)
#define CCU6_T13_T13CV_Pos (0UL) |
CCU6 T13: T13CV (Bit 0)
#define CCU6_T13PR_T13PV_Msk (0xffffUL) |
CCU6 T13PR: T13PV (Bitfield-Mask: 0xffff)
#define CCU6_T13PR_T13PV_Pos (0UL) |
CCU6 T13PR: T13PV (Bit 0)
#define CCU6_TCTR0_CDIR_Msk (0x40UL) |
CCU6 TCTR0: CDIR (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_CDIR_Pos (6UL) |
CCU6 TCTR0: CDIR (Bit 6)
#define CCU6_TCTR0_CTM_Msk (0x80UL) |
CCU6 TCTR0: CTM (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_CTM_Pos (7UL) |
CCU6 TCTR0: CTM (Bit 7)
#define CCU6_TCTR0_STE12_Msk (0x20UL) |
CCU6 TCTR0: STE12 (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_STE12_Pos (5UL) |
CCU6 TCTR0: STE12 (Bit 5)
#define CCU6_TCTR0_STE13_Msk (0x2000UL) |
CCU6 TCTR0: STE13 (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_STE13_Pos (13UL) |
CCU6 TCTR0: STE13 (Bit 13)
#define CCU6_TCTR0_T12CLK_Msk (0x7UL) |
CCU6 TCTR0: T12CLK (Bitfield-Mask: 0x07)
#define CCU6_TCTR0_T12CLK_Pos (0UL) |
CCU6 TCTR0: T12CLK (Bit 0)
#define CCU6_TCTR0_T12PRE_Msk (0x8UL) |
CCU6 TCTR0: T12PRE (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T12PRE_Pos (3UL) |
CCU6 TCTR0: T12PRE (Bit 3)
#define CCU6_TCTR0_T12R_Msk (0x10UL) |
CCU6 TCTR0: T12R (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T12R_Pos (4UL) |
CCU6 TCTR0: T12R (Bit 4)
#define CCU6_TCTR0_T13CLK_Msk (0x700UL) |
CCU6 TCTR0: T13CLK (Bitfield-Mask: 0x07)
#define CCU6_TCTR0_T13CLK_Pos (8UL) |
CCU6 TCTR0: T13CLK (Bit 8)
#define CCU6_TCTR0_T13PRE_Msk (0x800UL) |
CCU6 TCTR0: T13PRE (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T13PRE_Pos (11UL) |
CCU6 TCTR0: T13PRE (Bit 11)
#define CCU6_TCTR0_T13R_Msk (0x1000UL) |
CCU6 TCTR0: T13R (Bitfield-Mask: 0x01)
#define CCU6_TCTR0_T13R_Pos (12UL) |
CCU6 TCTR0: T13R (Bit 12)
#define CCU6_TCTR2_T12RSEL_Msk (0x300UL) |
CCU6 TCTR2: T12RSEL (Bitfield-Mask: 0x03)
#define CCU6_TCTR2_T12RSEL_Pos (8UL) |
CCU6 TCTR2: T12RSEL (Bit 8)
#define CCU6_TCTR2_T12SSC_Msk (0x1UL) |
CCU6 TCTR2: T12SSC (Bitfield-Mask: 0x01)
#define CCU6_TCTR2_T12SSC_Pos (0UL) |
CCU6 TCTR2: T12SSC (Bit 0)
#define CCU6_TCTR2_T13RSEL_Msk (0xc00UL) |
CCU6 TCTR2: T13RSEL (Bitfield-Mask: 0x03)
#define CCU6_TCTR2_T13RSEL_Pos (10UL) |
CCU6 TCTR2: T13RSEL (Bit 10)
#define CCU6_TCTR2_T13SSC_Msk (0x2UL) |
CCU6 TCTR2: T13SSC (Bitfield-Mask: 0x01)
#define CCU6_TCTR2_T13SSC_Pos (1UL) |
CCU6 TCTR2: T13SSC (Bit 1)
#define CCU6_TCTR2_T13TEC_Msk (0x1cUL) |
CCU6 TCTR2: T13TEC (Bitfield-Mask: 0x07)
#define CCU6_TCTR2_T13TEC_Pos (2UL) |
CCU6 TCTR2: T13TEC (Bit 2)
#define CCU6_TCTR2_T13TED_Msk (0x60UL) |
CCU6 TCTR2: T13TED (Bitfield-Mask: 0x03)
#define CCU6_TCTR2_T13TED_Pos (5UL) |
CCU6 TCTR2: T13TED (Bit 5)
#define CCU6_TCTR4_DTRES_Msk (0x8UL) |
CCU6 TCTR4: DTRES (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_DTRES_Pos (3UL) |
CCU6 TCTR4: DTRES (Bit 3)
#define CCU6_TCTR4_T12CNT_Msk (0x20UL) |
CCU6 TCTR4: T12CNT (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12CNT_Pos (5UL) |
CCU6 TCTR4: T12CNT (Bit 5)
#define CCU6_TCTR4_T12RES_Msk (0x4UL) |
CCU6 TCTR4: T12RES (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12RES_Pos (2UL) |
CCU6 TCTR4: T12RES (Bit 2)
#define CCU6_TCTR4_T12RR_Msk (0x1UL) |
CCU6 TCTR4: T12RR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12RR_Pos (0UL) |
CCU6 TCTR4: T12RR (Bit 0)
#define CCU6_TCTR4_T12RS_Msk (0x2UL) |
CCU6 TCTR4: T12RS (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12RS_Pos (1UL) |
CCU6 TCTR4: T12RS (Bit 1)
#define CCU6_TCTR4_T12STD_Msk (0x80UL) |
CCU6 TCTR4: T12STD (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12STD_Pos (7UL) |
CCU6 TCTR4: T12STD (Bit 7)
#define CCU6_TCTR4_T12STR_Msk (0x40UL) |
CCU6 TCTR4: T12STR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T12STR_Pos (6UL) |
CCU6 TCTR4: T12STR (Bit 6)
#define CCU6_TCTR4_T13CNT_Msk (0x2000UL) |
CCU6 TCTR4: T13CNT (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13CNT_Pos (13UL) |
CCU6 TCTR4: T13CNT (Bit 13)
#define CCU6_TCTR4_T13RES_Msk (0x400UL) |
CCU6 TCTR4: T13RES (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13RES_Pos (10UL) |
CCU6 TCTR4: T13RES (Bit 10)
#define CCU6_TCTR4_T13RR_Msk (0x100UL) |
CCU6 TCTR4: T13RR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13RR_Pos (8UL) |
CCU6 TCTR4: T13RR (Bit 8)
#define CCU6_TCTR4_T13RS_Msk (0x200UL) |
CCU6 TCTR4: T13RS (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13RS_Pos (9UL) |
CCU6 TCTR4: T13RS (Bit 9)
#define CCU6_TCTR4_T13STD_Msk (0x8000UL) |
CCU6 TCTR4: T13STD (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13STD_Pos (15UL) |
CCU6 TCTR4: T13STD (Bit 15)
#define CCU6_TCTR4_T13STR_Msk (0x4000UL) |
CCU6 TCTR4: T13STR (Bitfield-Mask: 0x01)
#define CCU6_TCTR4_T13STR_Pos (14UL) |
CCU6 TCTR4: T13STR (Bit 14)
#define CCU6_TRPCTR_TRPEN13_Msk (0x4000UL) |
CCU6 TRPCTR: TRPEN13 (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPEN13_Pos (14UL) |
CCU6 TRPCTR: TRPEN13 (Bit 14)
#define CCU6_TRPCTR_TRPEN_Msk (0x3f00UL) |
CCU6 TRPCTR: TRPEN (Bitfield-Mask: 0x3f)
#define CCU6_TRPCTR_TRPEN_Pos (8UL) |
CCU6 TRPCTR: TRPEN (Bit 8)
#define CCU6_TRPCTR_TRPM10_Msk (0x3UL) |
CCU6 TRPCTR: TRPM10 (Bitfield-Mask: 0x03)
#define CCU6_TRPCTR_TRPM10_Pos (0UL) |
CCU6 TRPCTR: TRPM10 (Bit 0)
#define CCU6_TRPCTR_TRPM2_Msk (0x4UL) |
CCU6 TRPCTR: TRPM2 (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPM2_Pos (2UL) |
CCU6 TRPCTR: TRPM2 (Bit 2)
#define CCU6_TRPCTR_TRPPEN_Msk (0x8000UL) |
CCU6 TRPCTR: TRPPEN (Bitfield-Mask: 0x01)
#define CCU6_TRPCTR_TRPPEN_Pos (15UL) |
CCU6 TRPCTR: TRPPEN (Bit 15)
#define CPU_AIRCR_ENDIANNESS_Msk (0x8000UL) |
CPU AIRCR: ENDIANNESS (Bitfield-Mask: 0x01)
#define CPU_AIRCR_ENDIANNESS_Pos (15UL) |
CPU AIRCR: ENDIANNESS (Bit 15)
#define CPU_AIRCR_SYSRESETREQ_Msk (0x4UL) |
CPU AIRCR: SYSRESETREQ (Bitfield-Mask: 0x01)
#define CPU_AIRCR_SYSRESETREQ_Pos (2UL) |
CPU AIRCR: SYSRESETREQ (Bit 2)
#define CPU_AIRCR_VECTCLRACTIVE_Msk (0x2UL) |
CPU AIRCR: VECTCLRACTIVE (Bitfield-Mask: 0x01)
#define CPU_AIRCR_VECTCLRACTIVE_Pos (1UL) |
CPU AIRCR: VECTCLRACTIVE (Bit 1)
#define CPU_AIRCR_VECTKEY_Msk (0xffff0000UL) |
CPU AIRCR: VECTKEY (Bitfield-Mask: 0xffff)
#define CPU_AIRCR_VECTKEY_Pos (16UL) |
CPU AIRCR: VECTKEY (Bit 16)
#define CPU_CCR_STKALIGN_Msk (0x200UL) |
CPU CCR: STKALIGN (Bitfield-Mask: 0x01)
#define CPU_CCR_STKALIGN_Pos (9UL) |
CPU CCR: STKALIGN (Bit 9)
#define CPU_CCR_UNALIGN_TRP_Msk (0x8UL) |
CPU CCR: UNALIGN_TRP (Bitfield-Mask: 0x01)
#define CPU_CCR_UNALIGN_TRP_Pos (3UL) |
CPU CCR: UNALIGN_TRP (Bit 3)
#define CPU_CPUID_CONSTANT_Msk (0xf0000UL) |
CPU CPUID: CONSTANT (Bitfield-Mask: 0x0f)
#define CPU_CPUID_CONSTANT_Pos (16UL) |
CPU CPUID: CONSTANT (Bit 16)
#define CPU_CPUID_IMPLEMENTER_Msk (0xff000000UL) |
CPU CPUID: IMPLEMENTER (Bitfield-Mask: 0xff)
#define CPU_CPUID_IMPLEMENTER_Pos (24UL) |
CPU CPUID: IMPLEMENTER (Bit 24)
#define CPU_CPUID_PARTNO_Msk (0xfff0UL) |
CPU CPUID: PARTNO (Bitfield-Mask: 0xfff)
#define CPU_CPUID_PARTNO_Pos (4UL) |
CPU CPUID: PARTNO (Bit 4)
#define CPU_CPUID_REVISION_Msk (0xfUL) |
CPU CPUID: REVISION (Bitfield-Mask: 0x0f)
#define CPU_CPUID_REVISION_Pos (0UL) |
CPU CPUID: REVISION (Bit 0)
#define CPU_CPUID_VARIANT_Msk (0xf00000UL) |
CPU CPUID: VARIANT (Bitfield-Mask: 0x0f)
#define CPU_CPUID_VARIANT_Pos (20UL) |
CPU CPUID: VARIANT (Bit 20)
#define CPU_ICSR_ISRPENDING_Msk (0x400000UL) |
CPU ICSR: ISRPENDING (Bitfield-Mask: 0x01)
#define CPU_ICSR_ISRPENDING_Pos (22UL) |
CPU ICSR: ISRPENDING (Bit 22)
#define CPU_ICSR_NMIPENDSET_Msk (0x80000000UL) |
CPU ICSR: NMIPENDSET (Bitfield-Mask: 0x01)
#define CPU_ICSR_NMIPENDSET_Pos (31UL) |
CPU ICSR: NMIPENDSET (Bit 31)
#define CPU_ICSR_PENDSTCLR_Msk (0x2000000UL) |
CPU ICSR: PENDSTCLR (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSTCLR_Pos (25UL) |
CPU ICSR: PENDSTCLR (Bit 25)
#define CPU_ICSR_PENDSTSET_Msk (0x4000000UL) |
CPU ICSR: PENDSTSET (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSTSET_Pos (26UL) |
CPU ICSR: PENDSTSET (Bit 26)
#define CPU_ICSR_PENDSVCLR_Msk (0x8000000UL) |
CPU ICSR: PENDSVCLR (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSVCLR_Pos (27UL) |
CPU ICSR: PENDSVCLR (Bit 27)
#define CPU_ICSR_PENDSVSET_Msk (0x10000000UL) |
CPU ICSR: PENDSVSET (Bitfield-Mask: 0x01)
#define CPU_ICSR_PENDSVSET_Pos (28UL) |
CPU ICSR: PENDSVSET (Bit 28)
#define CPU_ICSR_VECTACTIVE_Msk (0x3fUL) |
CPU ICSR: VECTACTIVE (Bitfield-Mask: 0x3f)
#define CPU_ICSR_VECTACTIVE_Pos (0UL) |
CPU ICSR: VECTACTIVE (Bit 0)
#define CPU_ICSR_VECTPENDING_Msk (0x3f000UL) |
CPU ICSR: VECTPENDING (Bitfield-Mask: 0x3f)
#define CPU_ICSR_VECTPENDING_Pos (12UL) |
CPU ICSR: VECTPENDING (Bit 12)
#define CPU_NVIC_ICER_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ICER: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_ADC1_Pos (3UL) |
CPU NVIC_ICER: Int_ADC1 (Bit 3)
#define CPU_NVIC_ICER_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ICER: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_ADC2_Pos (2UL) |
CPU NVIC_ICER: Int_ADC2 (Bit 2)
#define CPU_NVIC_ICER_Int_BDRV_Msk (0x40000UL) |
CPU NVIC_ICER: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_BDRV_Pos (18UL) |
CPU NVIC_ICER: Int_BDRV (Bit 18)
#define CPU_NVIC_ICER_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ICER: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ICER: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ICER_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ICER: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ICER: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ICER_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ICER: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ICER: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ICER_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ICER: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ICER: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ICER_Int_CP_Msk (0x20000UL) |
CPU NVIC_ICER: Int_CP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_CP_Pos (17UL) |
CPU NVIC_ICER: Int_CP (Bit 17)
#define CPU_NVIC_ICER_Int_DU_Msk (0x200000UL) |
CPU NVIC_ICER: Int_DU (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_DU_Pos (21UL) |
CPU NVIC_ICER: Int_DU (Bit 21)
#define CPU_NVIC_ICER_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ICER: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_EXINT0_Pos (12UL) |
CPU NVIC_ICER: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ICER_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ICER: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_EXINT1_Pos (13UL) |
CPU NVIC_ICER: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ICER_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ICER: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_GPT1_Pos (0UL) |
CPU NVIC_ICER: Int_GPT1 (Bit 0)
#define CPU_NVIC_ICER_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ICER: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_GPT2_Pos (1UL) |
CPU NVIC_ICER: Int_GPT2 (Bit 1)
#define CPU_NVIC_ICER_Int_HS_Msk (0x80000UL) |
CPU NVIC_ICER: Int_HS (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_HS_Pos (19UL) |
CPU NVIC_ICER: Int_HS (Bit 19)
#define CPU_NVIC_ICER_Int_MATHDIV_Msk (0x8000UL) |
CPU NVIC_ICER: Int_MATHDIV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_MATHDIV_Pos (15UL) |
CPU NVIC_ICER: Int_MATHDIV (Bit 15)
#define CPU_NVIC_ICER_Int_MON_Msk (0x400000UL) |
CPU NVIC_ICER: Int_MON (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_MON_Pos (22UL) |
CPU NVIC_ICER: Int_MON (Bit 22)
#define CPU_NVIC_ICER_Int_OPA_Msk (0x100000UL) |
CPU NVIC_ICER: Int_OPA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_OPA_Pos (20UL) |
CPU NVIC_ICER: Int_OPA (Bit 20)
#define CPU_NVIC_ICER_Int_PORT2_Msk (0x800000UL) |
CPU NVIC_ICER: Int_PORT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_PORT2_Pos (23UL) |
CPU NVIC_ICER: Int_PORT2 (Bit 23)
#define CPU_NVIC_ICER_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ICER: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_SSC1_Pos (8UL) |
CPU NVIC_ICER: Int_SSC1 (Bit 8)
#define CPU_NVIC_ICER_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ICER: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_SSC2_Pos (9UL) |
CPU NVIC_ICER: Int_SSC2 (Bit 9)
#define CPU_NVIC_ICER_Int_UART1_Msk (0x400UL) |
CPU NVIC_ICER: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_UART1_Pos (10UL) |
CPU NVIC_ICER: Int_UART1 (Bit 10)
#define CPU_NVIC_ICER_Int_UART2_Msk (0x800UL) |
CPU NVIC_ICER: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_UART2_Pos (11UL) |
CPU NVIC_ICER: Int_UART2 (Bit 11)
#define CPU_NVIC_ICER_Int_WAKEUP_Msk (0x4000UL) |
CPU NVIC_ICER: Int_WAKEUP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICER_Int_WAKEUP_Pos (14UL) |
CPU NVIC_ICER: Int_WAKEUP (Bit 14)
#define CPU_NVIC_ICPR_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ICPR: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_ADC1_Pos (3UL) |
CPU NVIC_ICPR: Int_ADC1 (Bit 3)
#define CPU_NVIC_ICPR_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ICPR: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_ADC2_Pos (2UL) |
CPU NVIC_ICPR: Int_ADC2 (Bit 2)
#define CPU_NVIC_ICPR_Int_BDRV_Msk (0x40000UL) |
CPU NVIC_ICPR: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_BDRV_Pos (18UL) |
CPU NVIC_ICPR: Int_BDRV (Bit 18)
#define CPU_NVIC_ICPR_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ICPR: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ICPR: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ICPR_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ICPR: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ICPR: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ICPR_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ICPR: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ICPR: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ICPR_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ICPR: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ICPR: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ICPR_Int_CP_Msk (0x20000UL) |
CPU NVIC_ICPR: Int_CP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_CP_Pos (17UL) |
CPU NVIC_ICPR: Int_CP (Bit 17)
#define CPU_NVIC_ICPR_Int_DU_Msk (0x200000UL) |
CPU NVIC_ICPR: Int_DU (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_DU_Pos (21UL) |
CPU NVIC_ICPR: Int_DU (Bit 21)
#define CPU_NVIC_ICPR_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ICPR: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_EXINT0_Pos (12UL) |
CPU NVIC_ICPR: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ICPR_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ICPR: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_EXINT1_Pos (13UL) |
CPU NVIC_ICPR: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ICPR_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ICPR: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_GPT1_Pos (0UL) |
CPU NVIC_ICPR: Int_GPT1 (Bit 0)
#define CPU_NVIC_ICPR_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ICPR: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_GPT2_Pos (1UL) |
CPU NVIC_ICPR: Int_GPT2 (Bit 1)
#define CPU_NVIC_ICPR_Int_HS_Msk (0x80000UL) |
CPU NVIC_ICPR: Int_HS (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_HS_Pos (19UL) |
CPU NVIC_ICPR: Int_HS (Bit 19)
#define CPU_NVIC_ICPR_Int_MATHDIV_Msk (0x8000UL) |
CPU NVIC_ICPR: Int_MATHDIV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_MATHDIV_Pos (15UL) |
CPU NVIC_ICPR: Int_MATHDIV (Bit 15)
#define CPU_NVIC_ICPR_Int_MON_Msk (0x400000UL) |
CPU NVIC_ICPR: Int_MON (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_MON_Pos (22UL) |
CPU NVIC_ICPR: Int_MON (Bit 22)
#define CPU_NVIC_ICPR_Int_OPA_Msk (0x100000UL) |
CPU NVIC_ICPR: Int_OPA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_OPA_Pos (20UL) |
CPU NVIC_ICPR: Int_OPA (Bit 20)
#define CPU_NVIC_ICPR_Int_PORT2_Msk (0x800000UL) |
CPU NVIC_ICPR: Int_PORT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_PORT2_Pos (23UL) |
CPU NVIC_ICPR: Int_PORT2 (Bit 23)
#define CPU_NVIC_ICPR_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ICPR: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_SSC1_Pos (8UL) |
CPU NVIC_ICPR: Int_SSC1 (Bit 8)
#define CPU_NVIC_ICPR_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ICPR: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_SSC2_Pos (9UL) |
CPU NVIC_ICPR: Int_SSC2 (Bit 9)
#define CPU_NVIC_ICPR_Int_UART1_Msk (0x400UL) |
CPU NVIC_ICPR: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_UART1_Pos (10UL) |
CPU NVIC_ICPR: Int_UART1 (Bit 10)
#define CPU_NVIC_ICPR_Int_UART2_Msk (0x800UL) |
CPU NVIC_ICPR: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_UART2_Pos (11UL) |
CPU NVIC_ICPR: Int_UART2 (Bit 11)
#define CPU_NVIC_ICPR_Int_WAKEUP_Msk (0x4000UL) |
CPU NVIC_ICPR: Int_WAKEUP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ICPR_Int_WAKEUP_Pos (14UL) |
CPU NVIC_ICPR: Int_WAKEUP (Bit 14)
#define CPU_NVIC_IPR0_PRI_ADC1_Msk (0xc0000000UL) |
CPU NVIC_IPR0: PRI_ADC1 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR0_PRI_ADC1_Pos (30UL) |
CPU NVIC_IPR0: PRI_ADC1 (Bit 30)
#define CPU_NVIC_IPR0_PRI_ADC2_Msk (0xc00000UL) |
CPU NVIC_IPR0: PRI_ADC2 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR0_PRI_ADC2_Pos (22UL) |
CPU NVIC_IPR0: PRI_ADC2 (Bit 22)
#define CPU_NVIC_IPR0_PRI_GPT1_Msk (0xc0UL) |
CPU NVIC_IPR0: PRI_GPT1 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR0_PRI_GPT1_Pos (6UL) |
CPU NVIC_IPR0: PRI_GPT1 (Bit 6)
#define CPU_NVIC_IPR0_PRI_GPT2_Msk (0xc000UL) |
CPU NVIC_IPR0: PRI_GPT2 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR0_PRI_GPT2_Pos (14UL) |
CPU NVIC_IPR0: PRI_GPT2 (Bit 14)
#define CPU_NVIC_IPR1_PRI_CCU6SR0_Msk (0xc0UL) |
CPU NVIC_IPR1: PRI_CCU6SR0 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR1_PRI_CCU6SR0_Pos (6UL) |
CPU NVIC_IPR1: PRI_CCU6SR0 (Bit 6)
#define CPU_NVIC_IPR1_PRI_CCU6SR1_Msk (0xc000UL) |
CPU NVIC_IPR1: PRI_CCU6SR1 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR1_PRI_CCU6SR1_Pos (14UL) |
CPU NVIC_IPR1: PRI_CCU6SR1 (Bit 14)
#define CPU_NVIC_IPR1_PRI_CCU6SR2_Msk (0xc00000UL) |
CPU NVIC_IPR1: PRI_CCU6SR2 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR1_PRI_CCU6SR2_Pos (22UL) |
CPU NVIC_IPR1: PRI_CCU6SR2 (Bit 22)
#define CPU_NVIC_IPR1_PRI_CCU6SR3_Msk (0xc0000000UL) |
CPU NVIC_IPR1: PRI_CCU6SR3 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR1_PRI_CCU6SR3_Pos (30UL) |
CPU NVIC_IPR1: PRI_CCU6SR3 (Bit 30)
#define CPU_NVIC_IPR2_PRI_SSC1_Msk (0xc0UL) |
CPU NVIC_IPR2: PRI_SSC1 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR2_PRI_SSC1_Pos (6UL) |
CPU NVIC_IPR2: PRI_SSC1 (Bit 6)
#define CPU_NVIC_IPR2_PRI_SSC2_Msk (0xc000UL) |
CPU NVIC_IPR2: PRI_SSC2 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR2_PRI_SSC2_Pos (14UL) |
CPU NVIC_IPR2: PRI_SSC2 (Bit 14)
#define CPU_NVIC_IPR2_PRI_UART1_Msk (0xc00000UL) |
CPU NVIC_IPR2: PRI_UART1 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR2_PRI_UART1_Pos (22UL) |
CPU NVIC_IPR2: PRI_UART1 (Bit 22)
#define CPU_NVIC_IPR2_PRI_UART2_Msk (0xc0000000UL) |
CPU NVIC_IPR2: PRI_UART2 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR2_PRI_UART2_Pos (30UL) |
CPU NVIC_IPR2: PRI_UART2 (Bit 30)
#define CPU_NVIC_IPR3_PRI_EXINT0_Msk (0xc0UL) |
CPU NVIC_IPR3: PRI_EXINT0 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR3_PRI_EXINT0_Pos (6UL) |
CPU NVIC_IPR3: PRI_EXINT0 (Bit 6)
#define CPU_NVIC_IPR3_PRI_EXINT1_Msk (0xc000UL) |
CPU NVIC_IPR3: PRI_EXINT1 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR3_PRI_EXINT1_Pos (14UL) |
CPU NVIC_IPR3: PRI_EXINT1 (Bit 14)
#define CPU_NVIC_IPR3_PRI_MATHDIV_Msk (0xc0000000UL) |
CPU NVIC_IPR3: PRI_MATHDIV (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR3_PRI_MATHDIV_Pos (30UL) |
CPU NVIC_IPR3: PRI_MATHDIV (Bit 30)
#define CPU_NVIC_IPR3_PRI_WAKEUP_Msk (0xc00000UL) |
CPU NVIC_IPR3: PRI_WAKEUP (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR3_PRI_WAKEUP_Pos (22UL) |
CPU NVIC_IPR3: PRI_WAKEUP (Bit 22)
#define CPU_NVIC_IPR4_PRI_BDRV_Msk (0xc00000UL) |
CPU NVIC_IPR4: PRI_BDRV (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR4_PRI_BDRV_Pos (22UL) |
CPU NVIC_IPR4: PRI_BDRV (Bit 22)
#define CPU_NVIC_IPR4_PRI_CP_Msk (0xc000UL) |
CPU NVIC_IPR4: PRI_CP (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR4_PRI_CP_Pos (14UL) |
CPU NVIC_IPR4: PRI_CP (Bit 14)
#define CPU_NVIC_IPR4_PRI_HS_Msk (0xc0000000UL) |
CPU NVIC_IPR4: PRI_HS (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR4_PRI_HS_Pos (30UL) |
CPU NVIC_IPR4: PRI_HS (Bit 30)
#define CPU_NVIC_IPR5_PRI_DU_Msk (0xc000UL) |
CPU NVIC_IPR5: PRI_DU (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR5_PRI_DU_Pos (14UL) |
CPU NVIC_IPR5: PRI_DU (Bit 14)
#define CPU_NVIC_IPR5_PRI_MON_Msk (0xc00000UL) |
CPU NVIC_IPR5: PRI_MON (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR5_PRI_MON_Pos (22UL) |
CPU NVIC_IPR5: PRI_MON (Bit 22)
#define CPU_NVIC_IPR5_PRI_OPA_Msk (0xc0UL) |
CPU NVIC_IPR5: PRI_OPA (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR5_PRI_OPA_Pos (6UL) |
CPU NVIC_IPR5: PRI_OPA (Bit 6)
#define CPU_NVIC_IPR5_PRI_PORT2_Msk (0xc0000000UL) |
CPU NVIC_IPR5: PRI_PORT2 (Bitfield-Mask: 0x03)
#define CPU_NVIC_IPR5_PRI_PORT2_Pos (30UL) |
CPU NVIC_IPR5: PRI_PORT2 (Bit 30)
#define CPU_NVIC_ISER_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ISER: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_ADC1_Pos (3UL) |
CPU NVIC_ISER: Int_ADC1 (Bit 3)
#define CPU_NVIC_ISER_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ISER: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_ADC2_Pos (2UL) |
CPU NVIC_ISER: Int_ADC2 (Bit 2)
#define CPU_NVIC_ISER_Int_BDRV_Msk (0x40000UL) |
CPU NVIC_ISER: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_BDRV_Pos (18UL) |
CPU NVIC_ISER: Int_BDRV (Bit 18)
#define CPU_NVIC_ISER_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ISER: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ISER: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ISER_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ISER: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ISER: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ISER_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ISER: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ISER: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ISER_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ISER: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ISER: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ISER_Int_CP_Msk (0x20000UL) |
CPU NVIC_ISER: Int_CP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_CP_Pos (17UL) |
CPU NVIC_ISER: Int_CP (Bit 17)
#define CPU_NVIC_ISER_Int_DU_Msk (0x200000UL) |
CPU NVIC_ISER: Int_DU (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_DU_Pos (21UL) |
CPU NVIC_ISER: Int_DU (Bit 21)
#define CPU_NVIC_ISER_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ISER: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_EXINT0_Pos (12UL) |
CPU NVIC_ISER: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ISER_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ISER: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_EXINT1_Pos (13UL) |
CPU NVIC_ISER: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ISER_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ISER: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_GPT1_Pos (0UL) |
CPU NVIC_ISER: Int_GPT1 (Bit 0)
#define CPU_NVIC_ISER_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ISER: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_GPT2_Pos (1UL) |
CPU NVIC_ISER: Int_GPT2 (Bit 1)
#define CPU_NVIC_ISER_Int_HS_Msk (0x80000UL) |
CPU NVIC_ISER: Int_HS (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_HS_Pos (19UL) |
CPU NVIC_ISER: Int_HS (Bit 19)
#define CPU_NVIC_ISER_Int_MATHDIV_Msk (0x8000UL) |
CPU NVIC_ISER: Int_MATHDIV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_MATHDIV_Pos (15UL) |
CPU NVIC_ISER: Int_MATHDIV (Bit 15)
#define CPU_NVIC_ISER_Int_MON_Msk (0x400000UL) |
CPU NVIC_ISER: Int_MON (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_MON_Pos (22UL) |
CPU NVIC_ISER: Int_MON (Bit 22)
#define CPU_NVIC_ISER_Int_OPA_Msk (0x100000UL) |
CPU NVIC_ISER: Int_OPA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_OPA_Pos (20UL) |
CPU NVIC_ISER: Int_OPA (Bit 20)
#define CPU_NVIC_ISER_Int_PORT2_Msk (0x800000UL) |
CPU NVIC_ISER: Int_PORT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_PORT2_Pos (23UL) |
CPU NVIC_ISER: Int_PORT2 (Bit 23)
#define CPU_NVIC_ISER_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ISER: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_SSC1_Pos (8UL) |
CPU NVIC_ISER: Int_SSC1 (Bit 8)
#define CPU_NVIC_ISER_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ISER: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_SSC2_Pos (9UL) |
CPU NVIC_ISER: Int_SSC2 (Bit 9)
#define CPU_NVIC_ISER_Int_UART1_Msk (0x400UL) |
CPU NVIC_ISER: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_UART1_Pos (10UL) |
CPU NVIC_ISER: Int_UART1 (Bit 10)
#define CPU_NVIC_ISER_Int_UART2_Msk (0x800UL) |
CPU NVIC_ISER: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_UART2_Pos (11UL) |
CPU NVIC_ISER: Int_UART2 (Bit 11)
#define CPU_NVIC_ISER_Int_WAKEUP_Msk (0x4000UL) |
CPU NVIC_ISER: Int_WAKEUP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISER_Int_WAKEUP_Pos (14UL) |
CPU NVIC_ISER: Int_WAKEUP (Bit 14)
#define CPU_NVIC_ISPR_Int_ADC1_Msk (0x8UL) |
CPU NVIC_ISPR: Int_ADC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_ADC1_Pos (3UL) |
CPU NVIC_ISPR: Int_ADC1 (Bit 3)
#define CPU_NVIC_ISPR_Int_ADC2_Msk (0x4UL) |
CPU NVIC_ISPR: Int_ADC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_ADC2_Pos (2UL) |
CPU NVIC_ISPR: Int_ADC2 (Bit 2)
#define CPU_NVIC_ISPR_Int_BDRV_Msk (0x40000UL) |
CPU NVIC_ISPR: Int_BDRV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_BDRV_Pos (18UL) |
CPU NVIC_ISPR: Int_BDRV (Bit 18)
#define CPU_NVIC_ISPR_Int_CCU6SR0_Msk (0x10UL) |
CPU NVIC_ISPR: Int_CCU6SR0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_CCU6SR0_Pos (4UL) |
CPU NVIC_ISPR: Int_CCU6SR0 (Bit 4)
#define CPU_NVIC_ISPR_Int_CCU6SR1_Msk (0x20UL) |
CPU NVIC_ISPR: Int_CCU6SR1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_CCU6SR1_Pos (5UL) |
CPU NVIC_ISPR: Int_CCU6SR1 (Bit 5)
#define CPU_NVIC_ISPR_Int_CCU6SR2_Msk (0x40UL) |
CPU NVIC_ISPR: Int_CCU6SR2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_CCU6SR2_Pos (6UL) |
CPU NVIC_ISPR: Int_CCU6SR2 (Bit 6)
#define CPU_NVIC_ISPR_Int_CCU6SR3_Msk (0x80UL) |
CPU NVIC_ISPR: Int_CCU6SR3 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_CCU6SR3_Pos (7UL) |
CPU NVIC_ISPR: Int_CCU6SR3 (Bit 7)
#define CPU_NVIC_ISPR_Int_CP_Msk (0x20000UL) |
CPU NVIC_ISPR: Int_CP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_CP_Pos (17UL) |
CPU NVIC_ISPR: Int_CP (Bit 17)
#define CPU_NVIC_ISPR_Int_DU_Msk (0x200000UL) |
CPU NVIC_ISPR: Int_DU (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_DU_Pos (21UL) |
CPU NVIC_ISPR: Int_DU (Bit 21)
#define CPU_NVIC_ISPR_Int_EXINT0_Msk (0x1000UL) |
CPU NVIC_ISPR: Int_EXINT0 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_EXINT0_Pos (12UL) |
CPU NVIC_ISPR: Int_EXINT0 (Bit 12)
#define CPU_NVIC_ISPR_Int_EXINT1_Msk (0x2000UL) |
CPU NVIC_ISPR: Int_EXINT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_EXINT1_Pos (13UL) |
CPU NVIC_ISPR: Int_EXINT1 (Bit 13)
#define CPU_NVIC_ISPR_Int_GPT1_Msk (0x1UL) |
CPU NVIC_ISPR: Int_GPT1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_GPT1_Pos (0UL) |
CPU NVIC_ISPR: Int_GPT1 (Bit 0)
#define CPU_NVIC_ISPR_Int_GPT2_Msk (0x2UL) |
CPU NVIC_ISPR: Int_GPT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_GPT2_Pos (1UL) |
CPU NVIC_ISPR: Int_GPT2 (Bit 1)
#define CPU_NVIC_ISPR_Int_HS_Msk (0x80000UL) |
CPU NVIC_ISPR: Int_HS (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_HS_Pos (19UL) |
CPU NVIC_ISPR: Int_HS (Bit 19)
#define CPU_NVIC_ISPR_Int_MATHDIV_Msk (0x8000UL) |
CPU NVIC_ISPR: Int_MATHDIV (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_MATHDIV_Pos (15UL) |
CPU NVIC_ISPR: Int_MATHDIV (Bit 15)
#define CPU_NVIC_ISPR_Int_MON_Msk (0x400000UL) |
CPU NVIC_ISPR: Int_MON (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_MON_Pos (22UL) |
CPU NVIC_ISPR: Int_MON (Bit 22)
#define CPU_NVIC_ISPR_Int_OPA_Msk (0x100000UL) |
CPU NVIC_ISPR: Int_OPA (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_OPA_Pos (20UL) |
CPU NVIC_ISPR: Int_OPA (Bit 20)
#define CPU_NVIC_ISPR_Int_PORT2_Msk (0x800000UL) |
CPU NVIC_ISPR: Int_PORT2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_PORT2_Pos (23UL) |
CPU NVIC_ISPR: Int_PORT2 (Bit 23)
#define CPU_NVIC_ISPR_Int_SSC1_Msk (0x100UL) |
CPU NVIC_ISPR: Int_SSC1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_SSC1_Pos (8UL) |
CPU NVIC_ISPR: Int_SSC1 (Bit 8)
#define CPU_NVIC_ISPR_Int_SSC2_Msk (0x200UL) |
CPU NVIC_ISPR: Int_SSC2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_SSC2_Pos (9UL) |
CPU NVIC_ISPR: Int_SSC2 (Bit 9)
#define CPU_NVIC_ISPR_Int_UART1_Msk (0x400UL) |
CPU NVIC_ISPR: Int_UART1 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_UART1_Pos (10UL) |
CPU NVIC_ISPR: Int_UART1 (Bit 10)
#define CPU_NVIC_ISPR_Int_UART2_Msk (0x800UL) |
CPU NVIC_ISPR: Int_UART2 (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_UART2_Pos (11UL) |
CPU NVIC_ISPR: Int_UART2 (Bit 11)
#define CPU_NVIC_ISPR_Int_WAKEUP_Msk (0x4000UL) |
CPU NVIC_ISPR: Int_WAKEUP (Bitfield-Mask: 0x01)
#define CPU_NVIC_ISPR_Int_WAKEUP_Pos (14UL) |
CPU NVIC_ISPR: Int_WAKEUP (Bit 14)
#define CPU_SCR_SEVONPEND_Msk (0x10UL) |
CPU SCR: SEVONPEND (Bitfield-Mask: 0x01)
#define CPU_SCR_SEVONPEND_Pos (4UL) |
CPU SCR: SEVONPEND (Bit 4)
#define CPU_SCR_SLEEPDEEP_Msk (0x4UL) |
CPU SCR: SLEEPDEEP (Bitfield-Mask: 0x01)
#define CPU_SCR_SLEEPDEEP_Pos (2UL) |
CPU SCR: SLEEPDEEP (Bit 2)
#define CPU_SCR_SLEEPONEXIT_Msk (0x2UL) |
CPU SCR: SLEEPONEXIT (Bitfield-Mask: 0x01)
#define CPU_SCR_SLEEPONEXIT_Pos (1UL) |
CPU SCR: SLEEPONEXIT (Bit 1)
#define CPU_SHCSR_SVCALLPENDED_Msk (0x8000UL) |
CPU SHCSR: SVCALLPENDED (Bitfield-Mask: 0x01)
#define CPU_SHCSR_SVCALLPENDED_Pos (15UL) |
CPU SHCSR: SVCALLPENDED (Bit 15)
#define CPU_SHPR2_PRI_11_Msk (0xc0000000UL) |
CPU SHPR2: PRI_11 (Bitfield-Mask: 0x03)
#define CPU_SHPR2_PRI_11_Pos (30UL) |
CPU SHPR2: PRI_11 (Bit 30)
#define CPU_SHPR3_PRI_14_Msk (0xc00000UL) |
CPU SHPR3: PRI_14 (Bitfield-Mask: 0x03)
#define CPU_SHPR3_PRI_14_Pos (22UL) |
CPU SHPR3: PRI_14 (Bit 22)
#define CPU_SHPR3_PRI_15_Msk (0xc0000000UL) |
CPU SHPR3: PRI_15 (Bitfield-Mask: 0x03)
#define CPU_SHPR3_PRI_15_Pos (30UL) |
CPU SHPR3: PRI_15 (Bit 30)
#define CPU_SYSTICK_CALIB_NOREF_Msk (0x80000000UL) |
CPU SYSTICK_CALIB: NOREF (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CALIB_NOREF_Pos (31UL) |
CPU SYSTICK_CALIB: NOREF (Bit 31)
#define CPU_SYSTICK_CALIB_SKEW_Msk (0x40000000UL) |
CPU SYSTICK_CALIB: SKEW (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CALIB_SKEW_Pos (30UL) |
CPU SYSTICK_CALIB: SKEW (Bit 30)
#define CPU_SYSTICK_CALIB_TENMS_Msk (0xffffffUL) |
CPU SYSTICK_CALIB: TENMS (Bitfield-Mask: 0xffffff)
#define CPU_SYSTICK_CALIB_TENMS_Pos (0UL) |
CPU SYSTICK_CALIB: TENMS (Bit 0)
#define CPU_SYSTICK_CSR_CLKSOURCE_Msk (0x4UL) |
CPU SYSTICK_CSR: CLKSOURCE (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CSR_CLKSOURCE_Pos (2UL) |
CPU SYSTICK_CSR: CLKSOURCE (Bit 2)
#define CPU_SYSTICK_CSR_COUNTFLAG_Msk (0x10000UL) |
CPU SYSTICK_CSR: COUNTFLAG (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CSR_COUNTFLAG_Pos (16UL) |
CPU SYSTICK_CSR: COUNTFLAG (Bit 16)
#define CPU_SYSTICK_CSR_ENABLE_Msk (0x1UL) |
CPU SYSTICK_CSR: ENABLE (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CSR_ENABLE_Pos (0UL) |
CPU SYSTICK_CSR: ENABLE (Bit 0)
#define CPU_SYSTICK_CSR_TICKINT_Msk (0x2UL) |
CPU SYSTICK_CSR: TICKINT (Bitfield-Mask: 0x01)
#define CPU_SYSTICK_CSR_TICKINT_Pos (1UL) |
CPU SYSTICK_CSR: TICKINT (Bit 1)
#define CPU_SYSTICK_CVR_CURRENT_Msk (0xffffffUL) |
CPU SYSTICK_CVR: CURRENT (Bitfield-Mask: 0xffffff)
#define CPU_SYSTICK_CVR_CURRENT_Pos (0UL) |
CPU SYSTICK_CVR: CURRENT (Bit 0)
#define CPU_SYSTICK_RVR_RELOAD_Msk (0xffffffUL) |
CPU SYSTICK_RVR: RELOAD (Bitfield-Mask: 0xffffff)
#define CPU_SYSTICK_RVR_RELOAD_Pos (0UL) |
CPU SYSTICK_RVR: RELOAD (Bit 0)
#define GPT12E_CAPREL_CAPREL_Msk (0xffffUL) |
GPT12E CAPREL: CAPREL (Bitfield-Mask: 0xffff)
#define GPT12E_CAPREL_CAPREL_Pos (0UL) |
GPT12E CAPREL: CAPREL (Bit 0)
#define GPT12E_ID_MOD_REV_Msk (0xffUL) |
GPT12E ID: MOD_REV (Bitfield-Mask: 0xff)
#define GPT12E_ID_MOD_REV_Pos (0UL) |
GPT12E ID: MOD_REV (Bit 0)
#define GPT12E_ID_MOD_TYPE_Msk (0xff00UL) |
GPT12E ID: MOD_TYPE (Bitfield-Mask: 0xff)
#define GPT12E_ID_MOD_TYPE_Pos (8UL) |
GPT12E ID: MOD_TYPE (Bit 8)
#define GPT12E_PISEL_ISCAPIN_Msk (0xc000UL) |
GPT12E PISEL: ISCAPIN (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_ISCAPIN_Pos (14UL) |
GPT12E PISEL: ISCAPIN (Bit 14)
#define GPT12E_PISEL_IST2EUD_Msk (0x2UL) |
GPT12E PISEL: IST2EUD (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST2EUD_Pos (1UL) |
GPT12E PISEL: IST2EUD (Bit 1)
#define GPT12E_PISEL_IST2IN_Msk (0x1UL) |
GPT12E PISEL: IST2IN (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST2IN_Pos (0UL) |
GPT12E PISEL: IST2IN (Bit 0)
#define GPT12E_PISEL_IST3EUD_Msk (0x30UL) |
GPT12E PISEL: IST3EUD (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST3EUD_Pos (4UL) |
GPT12E PISEL: IST3EUD (Bit 4)
#define GPT12E_PISEL_IST3IN_Msk (0xcUL) |
GPT12E PISEL: IST3IN (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST3IN_Pos (2UL) |
GPT12E PISEL: IST3IN (Bit 2)
#define GPT12E_PISEL_IST4EUD_Msk (0x300UL) |
GPT12E PISEL: IST4EUD (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST4EUD_Pos (8UL) |
GPT12E PISEL: IST4EUD (Bit 8)
#define GPT12E_PISEL_IST4IN_Msk (0xc0UL) |
GPT12E PISEL: IST4IN (Bitfield-Mask: 0x03)
#define GPT12E_PISEL_IST4IN_Pos (6UL) |
GPT12E PISEL: IST4IN (Bit 6)
#define GPT12E_PISEL_IST5EUD_Msk (0x800UL) |
GPT12E PISEL: IST5EUD (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST5EUD_Pos (11UL) |
GPT12E PISEL: IST5EUD (Bit 11)
#define GPT12E_PISEL_IST5IN_Msk (0x400UL) |
GPT12E PISEL: IST5IN (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST5IN_Pos (10UL) |
GPT12E PISEL: IST5IN (Bit 10)
#define GPT12E_PISEL_IST6EUD_Msk (0x2000UL) |
GPT12E PISEL: IST6EUD (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST6EUD_Pos (13UL) |
GPT12E PISEL: IST6EUD (Bit 13)
#define GPT12E_PISEL_IST6IN_Msk (0x1000UL) |
GPT12E PISEL: IST6IN (Bitfield-Mask: 0x01)
#define GPT12E_PISEL_IST6IN_Pos (12UL) |
GPT12E PISEL: IST6IN (Bit 12)
#define GPT12E_T2_T2_Msk (0xffffUL) |
GPT12E T2: T2 (Bitfield-Mask: 0xffff)
#define GPT12E_T2_T2_Pos (0UL) |
GPT12E T2: T2 (Bit 0)
#define GPT12E_T2CON_T2CHDIR_Msk (0x4000UL) |
GPT12E T2CON: T2CHDIR (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2CHDIR_Pos (14UL) |
GPT12E T2CON: T2CHDIR (Bit 14)
#define GPT12E_T2CON_T2DIR_Msk (0x8000UL) |
GPT12E T2CON: T2DIR (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2DIR_Pos (15UL) |
GPT12E T2CON: T2DIR (Bit 15)
#define GPT12E_T2CON_T2EDGE_Msk (0x2000UL) |
GPT12E T2CON: T2EDGE (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2EDGE_Pos (13UL) |
GPT12E T2CON: T2EDGE (Bit 13)
#define GPT12E_T2CON_T2I_Msk (0x7UL) |
GPT12E T2CON: T2I (Bitfield-Mask: 0x07)
#define GPT12E_T2CON_T2I_Pos (0UL) |
GPT12E T2CON: T2I (Bit 0)
#define GPT12E_T2CON_T2IRIDIS_Msk (0x1000UL) |
GPT12E T2CON: T2IRIDIS (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2IRIDIS_Pos (12UL) |
GPT12E T2CON: T2IRIDIS (Bit 12)
#define GPT12E_T2CON_T2M_Msk (0x38UL) |
GPT12E T2CON: T2M (Bitfield-Mask: 0x07)
#define GPT12E_T2CON_T2M_Pos (3UL) |
GPT12E T2CON: T2M (Bit 3)
#define GPT12E_T2CON_T2R_Msk (0x40UL) |
GPT12E T2CON: T2R (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2R_Pos (6UL) |
GPT12E T2CON: T2R (Bit 6)
#define GPT12E_T2CON_T2RC_Msk (0x200UL) |
GPT12E T2CON: T2RC (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2RC_Pos (9UL) |
GPT12E T2CON: T2RC (Bit 9)
#define GPT12E_T2CON_T2UD_Msk (0x80UL) |
GPT12E T2CON: T2UD (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2UD_Pos (7UL) |
GPT12E T2CON: T2UD (Bit 7)
#define GPT12E_T2CON_T2UDE_Msk (0x100UL) |
GPT12E T2CON: T2UDE (Bitfield-Mask: 0x01)
#define GPT12E_T2CON_T2UDE_Pos (8UL) |
GPT12E T2CON: T2UDE (Bit 8)
#define GPT12E_T3_T3_Msk (0xffffUL) |
GPT12E T3: T3 (Bitfield-Mask: 0xffff)
#define GPT12E_T3_T3_Pos (0UL) |
GPT12E T3: T3 (Bit 0)
#define GPT12E_T3CON_BPS1_Msk (0x1800UL) |
GPT12E T3CON: BPS1 (Bitfield-Mask: 0x03)
#define GPT12E_T3CON_BPS1_Pos (11UL) |
GPT12E T3CON: BPS1 (Bit 11)
#define GPT12E_T3CON_T3CHDIR_Msk (0x4000UL) |
GPT12E T3CON: T3CHDIR (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3CHDIR_Pos (14UL) |
GPT12E T3CON: T3CHDIR (Bit 14)
#define GPT12E_T3CON_T3DIR_Msk (0x8000UL) |
GPT12E T3CON: T3DIR (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3DIR_Pos (15UL) |
GPT12E T3CON: T3DIR (Bit 15)
#define GPT12E_T3CON_T3EDGE_Msk (0x2000UL) |
GPT12E T3CON: T3EDGE (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3EDGE_Pos (13UL) |
GPT12E T3CON: T3EDGE (Bit 13)
#define GPT12E_T3CON_T3I_Msk (0x7UL) |
GPT12E T3CON: T3I (Bitfield-Mask: 0x07)
#define GPT12E_T3CON_T3I_Pos (0UL) |
GPT12E T3CON: T3I (Bit 0)
#define GPT12E_T3CON_T3M_Msk (0x38UL) |
GPT12E T3CON: T3M (Bitfield-Mask: 0x07)
#define GPT12E_T3CON_T3M_Pos (3UL) |
GPT12E T3CON: T3M (Bit 3)
#define GPT12E_T3CON_T3OE_Msk (0x200UL) |
GPT12E T3CON: T3OE (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3OE_Pos (9UL) |
GPT12E T3CON: T3OE (Bit 9)
#define GPT12E_T3CON_T3OTL_Msk (0x400UL) |
GPT12E T3CON: T3OTL (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3OTL_Pos (10UL) |
GPT12E T3CON: T3OTL (Bit 10)
#define GPT12E_T3CON_T3R_Msk (0x40UL) |
GPT12E T3CON: T3R (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3R_Pos (6UL) |
GPT12E T3CON: T3R (Bit 6)
#define GPT12E_T3CON_T3UD_Msk (0x80UL) |
GPT12E T3CON: T3UD (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3UD_Pos (7UL) |
GPT12E T3CON: T3UD (Bit 7)
#define GPT12E_T3CON_T3UDE_Msk (0x100UL) |
GPT12E T3CON: T3UDE (Bitfield-Mask: 0x01)
#define GPT12E_T3CON_T3UDE_Pos (8UL) |
GPT12E T3CON: T3UDE (Bit 8)
#define GPT12E_T4_T4_Msk (0xffffUL) |
GPT12E T4: T4 (Bitfield-Mask: 0xffff)
#define GPT12E_T4_T4_Pos (0UL) |
GPT12E T4: T4 (Bit 0)
#define GPT12E_T4CON_CLRT2EN_Msk (0x400UL) |
GPT12E T4CON: CLRT2EN (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_CLRT2EN_Pos (10UL) |
GPT12E T4CON: CLRT2EN (Bit 10)
#define GPT12E_T4CON_CLRT3EN_Msk (0x800UL) |
GPT12E T4CON: CLRT3EN (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_CLRT3EN_Pos (11UL) |
GPT12E T4CON: CLRT3EN (Bit 11)
#define GPT12E_T4CON_T4CHDIR_Msk (0x4000UL) |
GPT12E T4CON: T4CHDIR (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4CHDIR_Pos (14UL) |
GPT12E T4CON: T4CHDIR (Bit 14)
#define GPT12E_T4CON_T4EDGE_Msk (0x2000UL) |
GPT12E T4CON: T4EDGE (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4EDGE_Pos (13UL) |
GPT12E T4CON: T4EDGE (Bit 13)
#define GPT12E_T4CON_T4I_Msk (0x7UL) |
GPT12E T4CON: T4I (Bitfield-Mask: 0x07)
#define GPT12E_T4CON_T4I_Pos (0UL) |
GPT12E T4CON: T4I (Bit 0)
#define GPT12E_T4CON_T4IRDIS_Msk (0x1000UL) |
GPT12E T4CON: T4IRDIS (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4IRDIS_Pos (12UL) |
GPT12E T4CON: T4IRDIS (Bit 12)
#define GPT12E_T4CON_T4M_Msk (0x38UL) |
GPT12E T4CON: T4M (Bitfield-Mask: 0x07)
#define GPT12E_T4CON_T4M_Pos (3UL) |
GPT12E T4CON: T4M (Bit 3)
#define GPT12E_T4CON_T4R_Msk (0x40UL) |
GPT12E T4CON: T4R (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4R_Pos (6UL) |
GPT12E T4CON: T4R (Bit 6)
#define GPT12E_T4CON_T4RC_Msk (0x200UL) |
GPT12E T4CON: T4RC (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4RC_Pos (9UL) |
GPT12E T4CON: T4RC (Bit 9)
#define GPT12E_T4CON_T4RDIR_Msk (0x8000UL) |
GPT12E T4CON: T4RDIR (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4RDIR_Pos (15UL) |
GPT12E T4CON: T4RDIR (Bit 15)
#define GPT12E_T4CON_T4UD_Msk (0x80UL) |
GPT12E T4CON: T4UD (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4UD_Pos (7UL) |
GPT12E T4CON: T4UD (Bit 7)
#define GPT12E_T4CON_T4UDE_Msk (0x100UL) |
GPT12E T4CON: T4UDE (Bitfield-Mask: 0x01)
#define GPT12E_T4CON_T4UDE_Pos (8UL) |
GPT12E T4CON: T4UDE (Bit 8)
#define GPT12E_T5_T5_Msk (0xffffUL) |
GPT12E T5: T5 (Bitfield-Mask: 0xffff)
#define GPT12E_T5_T5_Pos (0UL) |
GPT12E T5: T5 (Bit 0)
#define GPT12E_T5CON_CI_Msk (0x3000UL) |
GPT12E T5CON: CI (Bitfield-Mask: 0x03)
#define GPT12E_T5CON_CI_Pos (12UL) |
GPT12E T5CON: CI (Bit 12)
#define GPT12E_T5CON_CT3_Msk (0x400UL) |
GPT12E T5CON: CT3 (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_CT3_Pos (10UL) |
GPT12E T5CON: CT3 (Bit 10)
#define GPT12E_T5CON_T5CLR_Msk (0x4000UL) |
GPT12E T5CON: T5CLR (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5CLR_Pos (14UL) |
GPT12E T5CON: T5CLR (Bit 14)
#define GPT12E_T5CON_T5I_Msk (0x7UL) |
GPT12E T5CON: T5I (Bitfield-Mask: 0x07)
#define GPT12E_T5CON_T5I_Pos (0UL) |
GPT12E T5CON: T5I (Bit 0)
#define GPT12E_T5CON_T5M_Msk (0x18UL) |
GPT12E T5CON: T5M (Bitfield-Mask: 0x03)
#define GPT12E_T5CON_T5M_Pos (3UL) |
GPT12E T5CON: T5M (Bit 3)
#define GPT12E_T5CON_T5R_Msk (0x40UL) |
GPT12E T5CON: T5R (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5R_Pos (6UL) |
GPT12E T5CON: T5R (Bit 6)
#define GPT12E_T5CON_T5RC_Msk (0x200UL) |
GPT12E T5CON: T5RC (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5RC_Pos (9UL) |
GPT12E T5CON: T5RC (Bit 9)
#define GPT12E_T5CON_T5SC_Msk (0x8000UL) |
GPT12E T5CON: T5SC (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5SC_Pos (15UL) |
GPT12E T5CON: T5SC (Bit 15)
#define GPT12E_T5CON_T5UD_Msk (0x80UL) |
GPT12E T5CON: T5UD (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5UD_Pos (7UL) |
GPT12E T5CON: T5UD (Bit 7)
#define GPT12E_T5CON_T5UDE_Msk (0x100UL) |
GPT12E T5CON: T5UDE (Bitfield-Mask: 0x01)
#define GPT12E_T5CON_T5UDE_Pos (8UL) |
GPT12E T5CON: T5UDE (Bit 8)
#define GPT12E_T6_T6_Msk (0xffffUL) |
GPT12E T6: T6 (Bitfield-Mask: 0xffff)
#define GPT12E_T6_T6_Pos (0UL) |
GPT12E T6: T6 (Bit 0)
#define GPT12E_T6CON_BPS2_Msk (0x1800UL) |
GPT12E T6CON: BPS2 (Bitfield-Mask: 0x03)
#define GPT12E_T6CON_BPS2_Pos (11UL) |
GPT12E T6CON: BPS2 (Bit 11)
#define GPT12E_T6CON_T6CLR_Msk (0x4000UL) |
GPT12E T6CON: T6CLR (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6CLR_Pos (14UL) |
GPT12E T6CON: T6CLR (Bit 14)
#define GPT12E_T6CON_T6I_Msk (0x7UL) |
GPT12E T6CON: T6I (Bitfield-Mask: 0x07)
#define GPT12E_T6CON_T6I_Pos (0UL) |
GPT12E T6CON: T6I (Bit 0)
#define GPT12E_T6CON_T6M_Msk (0x38UL) |
GPT12E T6CON: T6M (Bitfield-Mask: 0x07)
#define GPT12E_T6CON_T6M_Pos (3UL) |
GPT12E T6CON: T6M (Bit 3)
#define GPT12E_T6CON_T6OE_Msk (0x200UL) |
GPT12E T6CON: T6OE (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6OE_Pos (9UL) |
GPT12E T6CON: T6OE (Bit 9)
#define GPT12E_T6CON_T6OTL_Msk (0x400UL) |
GPT12E T6CON: T6OTL (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6OTL_Pos (10UL) |
GPT12E T6CON: T6OTL (Bit 10)
#define GPT12E_T6CON_T6R_Msk (0x40UL) |
GPT12E T6CON: T6R (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6R_Pos (6UL) |
GPT12E T6CON: T6R (Bit 6)
#define GPT12E_T6CON_T6SR_Msk (0x8000UL) |
GPT12E T6CON: T6SR (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6SR_Pos (15UL) |
GPT12E T6CON: T6SR (Bit 15)
#define GPT12E_T6CON_T6UD_Msk (0x80UL) |
GPT12E T6CON: T6UD (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6UD_Pos (7UL) |
GPT12E T6CON: T6UD (Bit 7)
#define GPT12E_T6CON_T6UDE_Msk (0x100UL) |
GPT12E T6CON: T6UDE (Bitfield-Mask: 0x01)
#define GPT12E_T6CON_T6UDE_Pos (8UL) |
GPT12E T6CON: T6UDE (Bit 8)
#define HS_CTRL_HS1_EN_Msk (0x1UL) |
HS CTRL: HS1_EN (Bitfield-Mask: 0x01)
#define HS_CTRL_HS1_EN_Pos (0UL) |
HS CTRL: HS1_EN (Bit 0)
#define HS_CTRL_HS1_OC_SEL_Msk (0x3000UL) |
HS CTRL: HS1_OC_SEL (Bitfield-Mask: 0x03)
#define HS_CTRL_HS1_OC_SEL_Pos (12UL) |
HS CTRL: HS1_OC_SEL (Bit 12)
#define HS_CTRL_HS1_OL_EN_Msk (0x8UL) |
HS CTRL: HS1_OL_EN (Bitfield-Mask: 0x01)
#define HS_CTRL_HS1_OL_EN_Pos (3UL) |
HS CTRL: HS1_OL_EN (Bit 3)
#define HS_CTRL_HS1_ON_Msk (0x4UL) |
HS CTRL: HS1_ON (Bitfield-Mask: 0x01)
#define HS_CTRL_HS1_ON_Pos (2UL) |
HS CTRL: HS1_ON (Bit 2)
#define HS_CTRL_HS1_PWM_Msk (0x2UL) |
HS CTRL: HS1_PWM (Bitfield-Mask: 0x01)
#define HS_CTRL_HS1_PWM_Pos (1UL) |
HS CTRL: HS1_PWM (Bit 1)
#define HS_CTRL_HS1_SR_CTRL_SEL_Msk (0x300UL) |
HS CTRL: HS1_SR_CTRL_SEL (Bitfield-Mask: 0x03)
#define HS_CTRL_HS1_SR_CTRL_SEL_Pos (8UL) |
HS CTRL: HS1_SR_CTRL_SEL (Bit 8)
#define HS_IRQCLR_HS1_OC_ISC_Msk (0x80UL) |
HS IRQCLR: HS1_OC_ISC (Bitfield-Mask: 0x01)
#define HS_IRQCLR_HS1_OC_ISC_Pos (7UL) |
HS IRQCLR: HS1_OC_ISC (Bit 7)
#define HS_IRQCLR_HS1_OL_ISC_Msk (0x40UL) |
HS IRQCLR: HS1_OL_ISC (Bitfield-Mask: 0x01)
#define HS_IRQCLR_HS1_OL_ISC_Pos (6UL) |
HS IRQCLR: HS1_OL_ISC (Bit 6)
#define HS_IRQCLR_HS1_OL_SC_Msk (0x4000UL) |
HS IRQCLR: HS1_OL_SC (Bitfield-Mask: 0x01)
#define HS_IRQCLR_HS1_OL_SC_Pos (14UL) |
HS IRQCLR: HS1_OL_SC (Bit 14)
#define HS_IRQCLR_HS1_OT_ISC_Msk (0x20UL) |
HS IRQCLR: HS1_OT_ISC (Bitfield-Mask: 0x01)
#define HS_IRQCLR_HS1_OT_ISC_Pos (5UL) |
HS IRQCLR: HS1_OT_ISC (Bit 5)
#define HS_IRQCLR_HS1_OT_SC_Msk (0x2000UL) |
HS IRQCLR: HS1_OT_SC (Bitfield-Mask: 0x01)
#define HS_IRQCLR_HS1_OT_SC_Pos (13UL) |
HS IRQCLR: HS1_OT_SC (Bit 13)
#define HS_IRQEN_HS1_OC_IEN_Msk (0x80UL) |
HS IRQEN: HS1_OC_IEN (Bitfield-Mask: 0x01)
#define HS_IRQEN_HS1_OC_IEN_Pos (7UL) |
HS IRQEN: HS1_OC_IEN (Bit 7)
#define HS_IRQEN_HS1_OL_IEN_Msk (0x40UL) |
HS IRQEN: HS1_OL_IEN (Bitfield-Mask: 0x01)
#define HS_IRQEN_HS1_OL_IEN_Pos (6UL) |
HS IRQEN: HS1_OL_IEN (Bit 6)
#define HS_IRQEN_HS1_OT_IEN_Msk (0x20UL) |
HS IRQEN: HS1_OT_IEN (Bitfield-Mask: 0x01)
#define HS_IRQEN_HS1_OT_IEN_Pos (5UL) |
HS IRQEN: HS1_OT_IEN (Bit 5)
#define HS_IRQS_HS1_OC_IS_Msk (0x80UL) |
HS IRQS: HS1_OC_IS (Bitfield-Mask: 0x01)
#define HS_IRQS_HS1_OC_IS_Pos (7UL) |
HS IRQS: HS1_OC_IS (Bit 7)
#define HS_IRQS_HS1_OL_IS_Msk (0x40UL) |
HS IRQS: HS1_OL_IS (Bitfield-Mask: 0x01)
#define HS_IRQS_HS1_OL_IS_Pos (6UL) |
HS IRQS: HS1_OL_IS (Bit 6)
#define HS_IRQS_HS1_OL_STS_Msk (0x4000UL) |
HS IRQS: HS1_OL_STS (Bitfield-Mask: 0x01)
#define HS_IRQS_HS1_OL_STS_Pos (14UL) |
HS IRQS: HS1_OL_STS (Bit 14)
#define HS_IRQS_HS1_OT_IS_Msk (0x20UL) |
HS IRQS: HS1_OT_IS (Bitfield-Mask: 0x01)
#define HS_IRQS_HS1_OT_IS_Pos (5UL) |
HS IRQS: HS1_OT_IS (Bit 5)
#define HS_IRQS_HS1_OT_STS_Msk (0x2000UL) |
HS IRQS: HS1_OT_STS (Bitfield-Mask: 0x01)
#define HS_IRQS_HS1_OT_STS_Pos (13UL) |
HS IRQS: HS1_OT_STS (Bit 13)
#define HS_PWMSRCSEL_HS1_SRC_SEL_Msk (0x38UL) |
HS PWMSRCSEL: HS1_SRC_SEL (Bitfield-Mask: 0x07)
#define HS_PWMSRCSEL_HS1_SRC_SEL_Pos (3UL) |
HS PWMSRCSEL: HS1_SRC_SEL (Bit 3)
#define HS_TRIM_HS1_OC_OT_BTFILT_SEL_Msk (0x300UL) |
HS TRIM: HS1_OC_OT_BTFILT_SEL (Bitfield-Mask: 0x03)
#define HS_TRIM_HS1_OC_OT_BTFILT_SEL_Pos (8UL) |
HS TRIM: HS1_OC_OT_BTFILT_SEL (Bit 8)
#define HS_TRIM_HS1_OL_BTFILT_SEL_Msk (0x3UL) |
HS TRIM: HS1_OL_BTFILT_SEL (Bitfield-Mask: 0x03)
#define HS_TRIM_HS1_OL_BTFILT_SEL_Pos (0UL) |
HS TRIM: HS1_OL_BTFILT_SEL (Bit 0)
#define LIN_CTRL_EN_Msk (0x1UL) |
LIN CTRL: EN (Bitfield-Mask: 0x01)
#define LIN_CTRL_EN_Pos (0UL) |
LIN CTRL: EN (Bit 0)
#define LIN_CTRL_FB_SM1_Msk (0x2000UL) |
LIN CTRL: FB_SM1 (Bitfield-Mask: 0x01)
#define LIN_CTRL_FB_SM1_Pos (13UL) |
LIN CTRL: FB_SM1 (Bit 13)
#define LIN_CTRL_FB_SM2_Msk (0x4000UL) |
LIN CTRL: FB_SM2 (Bitfield-Mask: 0x01)
#define LIN_CTRL_FB_SM2_Pos (14UL) |
LIN CTRL: FB_SM2 (Bit 14)
#define LIN_CTRL_FB_SM3_Msk (0x8000UL) |
LIN CTRL: FB_SM3 (Bitfield-Mask: 0x01)
#define LIN_CTRL_FB_SM3_Pos (15UL) |
LIN CTRL: FB_SM3 (Bit 15)
#define LIN_CTRL_HV_MODE_Msk (0x200000UL) |
LIN CTRL: HV_MODE (Bitfield-Mask: 0x01)
#define LIN_CTRL_HV_MODE_Pos (21UL) |
LIN CTRL: HV_MODE (Bit 21)
#define LIN_CTRL_MODE_FB_Msk (0x70UL) |
LIN CTRL: MODE_FB (Bitfield-Mask: 0x07)
#define LIN_CTRL_MODE_FB_Pos (4UL) |
LIN CTRL: MODE_FB (Bit 4)
#define LIN_CTRL_MODE_Msk (0x6UL) |
LIN CTRL: MODE (Bitfield-Mask: 0x03)
#define LIN_CTRL_MODE_Pos (1UL) |
LIN CTRL: MODE (Bit 1)
#define LIN_CTRL_RXD_Msk (0x400UL) |
LIN CTRL: RXD (Bitfield-Mask: 0x01)
#define LIN_CTRL_RXD_Pos (10UL) |
LIN CTRL: RXD (Bit 10)
#define LIN_CTRL_SM_Msk (0x1800UL) |
LIN CTRL: SM (Bitfield-Mask: 0x03)
#define LIN_CTRL_SM_Pos (11UL) |
LIN CTRL: SM (Bit 11)
#define LIN_CTRL_TXD_Msk (0x200UL) |
LIN CTRL: TXD (Bitfield-Mask: 0x01)
#define LIN_CTRL_TXD_Pos (9UL) |
LIN CTRL: TXD (Bit 9)
#define LIN_IRQCLR_M_SM_ERR_ISC_Msk (0x8UL) |
LIN IRQCLR: M_SM_ERR_ISC (Bitfield-Mask: 0x01)
#define LIN_IRQCLR_M_SM_ERR_ISC_Pos (3UL) |
LIN IRQCLR: M_SM_ERR_ISC (Bit 3)
#define LIN_IRQCLR_M_SM_ERR_SC_Msk (0x100UL) |
LIN IRQCLR: M_SM_ERR_SC (Bitfield-Mask: 0x01)
#define LIN_IRQCLR_M_SM_ERR_SC_Pos (8UL) |
LIN IRQCLR: M_SM_ERR_SC (Bit 8)
#define LIN_IRQCLR_OC_ISC_Msk (0x20UL) |
LIN IRQCLR: OC_ISC (Bitfield-Mask: 0x01)
#define LIN_IRQCLR_OC_ISC_Pos (5UL) |
LIN IRQCLR: OC_ISC (Bit 5)
#define LIN_IRQCLR_OT_ISC_Msk (0x10UL) |
LIN IRQCLR: OT_ISC (Bitfield-Mask: 0x01)
#define LIN_IRQCLR_OT_ISC_Pos (4UL) |
LIN IRQCLR: OT_ISC (Bit 4)
#define LIN_IRQCLR_OT_SC_Msk (0x200UL) |
LIN IRQCLR: OT_SC (Bitfield-Mask: 0x01)
#define LIN_IRQCLR_OT_SC_Pos (9UL) |
LIN IRQCLR: OT_SC (Bit 9)
#define LIN_IRQCLR_TXD_TMOUT_ISC_Msk (0x40UL) |
LIN IRQCLR: TXD_TMOUT_ISC (Bitfield-Mask: 0x01)
#define LIN_IRQCLR_TXD_TMOUT_ISC_Pos (6UL) |
LIN IRQCLR: TXD_TMOUT_ISC (Bit 6)
#define LIN_IRQCLR_TXD_TMOUT_SC_Msk (0x800UL) |
LIN IRQCLR: TXD_TMOUT_SC (Bitfield-Mask: 0x01)
#define LIN_IRQCLR_TXD_TMOUT_SC_Pos (11UL) |
LIN IRQCLR: TXD_TMOUT_SC (Bit 11)
#define LIN_IRQEN_M_SM_ERR_IEN_Msk (0x8UL) |
LIN IRQEN: M_SM_ERR_IEN (Bitfield-Mask: 0x01)
#define LIN_IRQEN_M_SM_ERR_IEN_Pos (3UL) |
LIN IRQEN: M_SM_ERR_IEN (Bit 3)
#define LIN_IRQEN_OC_IEN_Msk (0x20UL) |
LIN IRQEN: OC_IEN (Bitfield-Mask: 0x01)
#define LIN_IRQEN_OC_IEN_Pos (5UL) |
LIN IRQEN: OC_IEN (Bit 5)
#define LIN_IRQEN_OT_IEN_Msk (0x10UL) |
LIN IRQEN: OT_IEN (Bitfield-Mask: 0x01)
#define LIN_IRQEN_OT_IEN_Pos (4UL) |
LIN IRQEN: OT_IEN (Bit 4)
#define LIN_IRQEN_TXD_TMOUT_IEN_Msk (0x40UL) |
LIN IRQEN: TXD_TMOUT_IEN (Bitfield-Mask: 0x01)
#define LIN_IRQEN_TXD_TMOUT_IEN_Pos (6UL) |
LIN IRQEN: TXD_TMOUT_IEN (Bit 6)
#define LIN_IRQS_M_SM_ERR_IS_Msk (0x8UL) |
LIN IRQS: M_SM_ERR_IS (Bitfield-Mask: 0x01)
#define LIN_IRQS_M_SM_ERR_IS_Pos (3UL) |
LIN IRQS: M_SM_ERR_IS (Bit 3)
#define LIN_IRQS_M_SM_ERR_STS_Msk (0x100UL) |
LIN IRQS: M_SM_ERR_STS (Bitfield-Mask: 0x01)
#define LIN_IRQS_M_SM_ERR_STS_Pos (8UL) |
LIN IRQS: M_SM_ERR_STS (Bit 8)
#define LIN_IRQS_OC_IS_Msk (0x20UL) |
LIN IRQS: OC_IS (Bitfield-Mask: 0x01)
#define LIN_IRQS_OC_IS_Pos (5UL) |
LIN IRQS: OC_IS (Bit 5)
#define LIN_IRQS_OT_IS_Msk (0x10UL) |
LIN IRQS: OT_IS (Bitfield-Mask: 0x01)
#define LIN_IRQS_OT_IS_Pos (4UL) |
LIN IRQS: OT_IS (Bit 4)
#define LIN_IRQS_OT_STS_Msk (0x200UL) |
LIN IRQS: OT_STS (Bitfield-Mask: 0x01)
#define LIN_IRQS_OT_STS_Pos (9UL) |
LIN IRQS: OT_STS (Bit 9)
#define LIN_IRQS_TXD_TMOUT_IS_Msk (0x40UL) |
LIN IRQS: TXD_TMOUT_IS (Bitfield-Mask: 0x01)
#define LIN_IRQS_TXD_TMOUT_IS_Pos (6UL) |
LIN IRQS: TXD_TMOUT_IS (Bit 6)
#define LIN_IRQS_TXD_TMOUT_STS_Msk (0x800UL) |
LIN IRQS: TXD_TMOUT_STS (Bitfield-Mask: 0x01)
#define LIN_IRQS_TXD_TMOUT_STS_Pos (11UL) |
LIN IRQS: TXD_TMOUT_STS (Bit 11)
#define MATH_DIVCON_DIVMODE_Msk (0x18UL) |
MATH DIVCON: DIVMODE (Bitfield-Mask: 0x03)
#define MATH_DIVCON_DIVMODE_Pos (3UL) |
MATH DIVCON: DIVMODE (Bit 3)
#define MATH_DIVCON_DVDSLC_Msk (0x1f0000UL) |
MATH DIVCON: DVDSLC (Bitfield-Mask: 0x1f)
#define MATH_DIVCON_DVDSLC_Pos (16UL) |
MATH DIVCON: DVDSLC (Bit 16)
#define MATH_DIVCON_DVSSRC_Msk (0x1f000000UL) |
MATH DIVCON: DVSSRC (Bitfield-Mask: 0x1f)
#define MATH_DIVCON_DVSSRC_Pos (24UL) |
MATH DIVCON: DVSSRC (Bit 24)
#define MATH_DIVCON_QSCNT_Msk (0x1f00UL) |
MATH DIVCON: QSCNT (Bitfield-Mask: 0x1f)
#define MATH_DIVCON_QSCNT_Pos (8UL) |
MATH DIVCON: QSCNT (Bit 8)
#define MATH_DIVCON_QSDIR_Msk (0x8000UL) |
MATH DIVCON: QSDIR (Bitfield-Mask: 0x01)
#define MATH_DIVCON_QSDIR_Pos (15UL) |
MATH DIVCON: QSDIR (Bit 15)
#define MATH_DIVCON_ST_Msk (0x1UL) |
MATH DIVCON: ST (Bitfield-Mask: 0x01)
#define MATH_DIVCON_ST_Pos (0UL) |
MATH DIVCON: ST (Bit 0)
#define MATH_DIVCON_STMODE_Msk (0x2UL) |
MATH DIVCON: STMODE (Bitfield-Mask: 0x01)
#define MATH_DIVCON_STMODE_Pos (1UL) |
MATH DIVCON: STMODE (Bit 1)
#define MATH_DIVCON_USIGN_Msk (0x4UL) |
MATH DIVCON: USIGN (Bitfield-Mask: 0x01)
#define MATH_DIVCON_USIGN_Pos (2UL) |
MATH DIVCON: USIGN (Bit 2)
#define MATH_DIVST_BSY_Msk (0x1UL) |
MATH DIVST: BSY (Bitfield-Mask: 0x01)
#define MATH_DIVST_BSY_Pos (0UL) |
MATH DIVST: BSY (Bit 0)
#define MATH_DVD_VAL_Msk (0xffffffffUL) |
MATH DVD: VAL (Bitfield-Mask: 0xffffffff)
#define MATH_DVD_VAL_Pos (0UL) |
MATH DVD: VAL (Bit 0)
#define MATH_DVS_VAL_Msk (0xffffffffUL) |
MATH DVS: VAL (Bitfield-Mask: 0xffffffff)
#define MATH_DVS_VAL_Pos (0UL) |
MATH DVS: VAL (Bit 0)
#define MATH_EVFCR_DIVEOCC_Msk (0x1UL) |
MATH EVFCR: DIVEOCC (Bitfield-Mask: 0x01)
#define MATH_EVFCR_DIVEOCC_Pos (0UL) |
MATH EVFCR: DIVEOCC (Bit 0)
#define MATH_EVFCR_DIVERRC_Msk (0x2UL) |
MATH EVFCR: DIVERRC (Bitfield-Mask: 0x01)
#define MATH_EVFCR_DIVERRC_Pos (1UL) |
MATH EVFCR: DIVERRC (Bit 1)
#define MATH_EVFR_DIVEOC_Msk (0x1UL) |
MATH EVFR: DIVEOC (Bitfield-Mask: 0x01)
#define MATH_EVFR_DIVEOC_Pos (0UL) |
MATH EVFR: DIVEOC (Bit 0)
#define MATH_EVFR_DIVERR_Msk (0x2UL) |
MATH EVFR: DIVERR (Bitfield-Mask: 0x01)
#define MATH_EVFR_DIVERR_Pos (1UL) |
MATH EVFR: DIVERR (Bit 1)
#define MATH_EVIER_DIVEOCIEN_Msk (0x1UL) |
MATH EVIER: DIVEOCIEN (Bitfield-Mask: 0x01)
#define MATH_EVIER_DIVEOCIEN_Pos (0UL) |
MATH EVIER: DIVEOCIEN (Bit 0)
#define MATH_EVIER_DIVERRIEN_Msk (0x2UL) |
MATH EVIER: DIVERRIEN (Bitfield-Mask: 0x01)
#define MATH_EVIER_DIVERRIEN_Pos (1UL) |
MATH EVIER: DIVERRIEN (Bit 1)
#define MATH_EVSFR_DIVEOCS_Msk (0x1UL) |
MATH EVSFR: DIVEOCS (Bitfield-Mask: 0x01)
#define MATH_EVSFR_DIVEOCS_Pos (0UL) |
MATH EVSFR: DIVEOCS (Bit 0)
#define MATH_EVSFR_DIVERRS_Msk (0x2UL) |
MATH EVSFR: DIVERRS (Bitfield-Mask: 0x01)
#define MATH_EVSFR_DIVERRS_Pos (1UL) |
MATH EVSFR: DIVERRS (Bit 1)
#define MATH_GLBCON_DVDRC_Msk (0x3UL) |
MATH GLBCON: DVDRC (Bitfield-Mask: 0x03)
#define MATH_GLBCON_DVDRC_Pos (0UL) |
MATH GLBCON: DVDRC (Bit 0)
#define MATH_GLBCON_DVSRC_Msk (0x18UL) |
MATH GLBCON: DVSRC (Bitfield-Mask: 0x03)
#define MATH_GLBCON_DVSRC_Pos (3UL) |
MATH GLBCON: DVSRC (Bit 3)
#define MATH_GLBCON_MATH_EN_Msk (0x80000000UL) |
MATH GLBCON: MATH_EN (Bitfield-Mask: 0x01)
#define MATH_GLBCON_MATH_EN_Pos (31UL) |
MATH GLBCON: MATH_EN (Bit 31)
#define MATH_GLBCON_SUSCFG_Msk (0x30000UL) |
MATH GLBCON: SUSCFG (Bitfield-Mask: 0x03)
#define MATH_GLBCON_SUSCFG_Pos (16UL) |
MATH GLBCON: SUSCFG (Bit 16)
#define MATH_MATH_ID_MOD_NUMBER_Msk (0xffff0000UL) |
MATH MATH_ID: MOD_NUMBER (Bitfield-Mask: 0xffff)
#define MATH_MATH_ID_MOD_NUMBER_Pos (16UL) |
MATH MATH_ID: MOD_NUMBER (Bit 16)
#define MATH_MATH_ID_MOD_REV_Msk (0xffUL) |
MATH MATH_ID: MOD_REV (Bitfield-Mask: 0xff)
#define MATH_MATH_ID_MOD_REV_Pos (0UL) |
MATH MATH_ID: MOD_REV (Bit 0)
#define MATH_MATH_ID_MOD_TYPE_Msk (0xff00UL) |
MATH MATH_ID: MOD_TYPE (Bitfield-Mask: 0xff)
#define MATH_MATH_ID_MOD_TYPE_Pos (8UL) |
MATH MATH_ID: MOD_TYPE (Bit 8)
#define MATH_QUOT_VAL_Msk (0xffffffffUL) |
MATH QUOT: VAL (Bitfield-Mask: 0xffffffff)
#define MATH_QUOT_VAL_Pos (0UL) |
MATH QUOT: VAL (Bit 0)
#define MATH_RMD_VAL_Msk (0xffffffffUL) |
MATH RMD: VAL (Bitfield-Mask: 0xffffffff)
#define MATH_RMD_VAL_Pos (0UL) |
MATH RMD: VAL (Bit 0)
#define MF_CSA_CTRL_CSA_EN_Msk (0x1UL) |
MF CSA_CTRL: CSA_EN (Bitfield-Mask: 0x01)
#define MF_CSA_CTRL_CSA_EN_Pos (0UL) |
MF CSA_CTRL: CSA_EN (Bit 0)
#define MF_CSA_CTRL_CSA_GAIN_Msk (0x6UL) |
MF CSA_CTRL: CSA_GAIN (Bitfield-Mask: 0x03)
#define MF_CSA_CTRL_CSA_GAIN_Pos (1UL) |
MF CSA_CTRL: CSA_GAIN (Bit 1)
#define MF_CSA_CTRL_CSA_MI_EN_Msk (0x10UL) |
MF CSA_CTRL: CSA_MI_EN (Bitfield-Mask: 0x01)
#define MF_CSA_CTRL_CSA_MI_EN_Pos (4UL) |
MF CSA_CTRL: CSA_MI_EN (Bit 4)
#define MF_CSA_CTRL_CSA_VZERO_Msk (0x100UL) |
MF CSA_CTRL: CSA_VZERO (Bitfield-Mask: 0x01)
#define MF_CSA_CTRL_CSA_VZERO_Pos (8UL) |
MF CSA_CTRL: CSA_VZERO (Bit 8)
#define MF_REF1_STS_VREF1V2_LOTHWARN_STS_Msk (0x10UL) |
MF REF1_STS: VREF1V2_LOTHWARN_STS (Bitfield-Mask: 0x01)
#define MF_REF1_STS_VREF1V2_LOTHWARN_STS_Pos (4UL) |
MF REF1_STS: VREF1V2_LOTHWARN_STS (Bit 4)
#define MF_REF1_STS_VREF1V2_UPTHWARN_STS_Msk (0x20UL) |
MF REF1_STS: VREF1V2_UPTHWARN_STS (Bitfield-Mask: 0x01)
#define MF_REF1_STS_VREF1V2_UPTHWARN_STS_Pos (5UL) |
MF REF1_STS: VREF1V2_UPTHWARN_STS (Bit 5)
#define PMU_CNF_RST_TFB_RST_TFB_Msk (0x3UL) |
PMU CNF_RST_TFB: RST_TFB (Bitfield-Mask: 0x03)
#define PMU_CNF_RST_TFB_RST_TFB_Pos (0UL) |
PMU CNF_RST_TFB: RST_TFB (Bit 0)
#define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Msk (0xcUL) |
PMU CNF_WAKE_FILTER: CNF_GPIO_FT (Bitfield-Mask: 0x03)
#define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Pos (2UL) |
PMU CNF_WAKE_FILTER: CNF_GPIO_FT (Bit 2)
#define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Msk (0x1UL) |
PMU CNF_WAKE_FILTER: CNF_LIN_FT (Bitfield-Mask: 0x01)
#define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Pos (0UL) |
PMU CNF_WAKE_FILTER: CNF_LIN_FT (Bit 0)
#define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Msk (0x2UL) |
PMU CNF_WAKE_FILTER: CNF_MON_FT (Bitfield-Mask: 0x01)
#define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Pos (1UL) |
PMU CNF_WAKE_FILTER: CNF_MON_FT (Bit 1)
#define PMU_DRV_CTRL_CNF_OFF_Msk (0xc0UL) |
PMU DRV_CTRL: CNF_OFF (Bitfield-Mask: 0x03)
#define PMU_DRV_CTRL_CNF_OFF_Pos (6UL) |
PMU DRV_CTRL: CNF_OFF (Bit 6)
#define PMU_DRV_CTRL_CNF_ON_Msk (0x30UL) |
PMU DRV_CTRL: CNF_ON (Bitfield-Mask: 0x03)
#define PMU_DRV_CTRL_CNF_ON_Pos (4UL) |
PMU DRV_CTRL: CNF_ON (Bit 4)
#define PMU_DRV_CTRL_GL1_CYC_ON_Msk (0x1UL) |
PMU DRV_CTRL: GL1_CYC_ON (Bitfield-Mask: 0x01)
#define PMU_DRV_CTRL_GL1_CYC_ON_Pos (0UL) |
PMU DRV_CTRL: GL1_CYC_ON (Bit 0)
#define PMU_DRV_CTRL_GL1_HOLD_ON_Msk (0x2UL) |
PMU DRV_CTRL: GL1_HOLD_ON (Bitfield-Mask: 0x01)
#define PMU_DRV_CTRL_GL1_HOLD_ON_Pos (1UL) |
PMU DRV_CTRL: GL1_HOLD_ON (Bit 1)
#define PMU_DRV_CTRL_GL2_CYC_ON_Msk (0x4UL) |
PMU DRV_CTRL: GL2_CYC_ON (Bitfield-Mask: 0x01)
#define PMU_DRV_CTRL_GL2_CYC_ON_Pos (2UL) |
PMU DRV_CTRL: GL2_CYC_ON (Bit 2)
#define PMU_DRV_CTRL_GL2_HOLD_ON_Msk (0x8UL) |
PMU DRV_CTRL: GL2_HOLD_ON (Bitfield-Mask: 0x01)
#define PMU_DRV_CTRL_GL2_HOLD_ON_Pos (3UL) |
PMU DRV_CTRL: GL2_HOLD_ON (Bit 3)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_0_Msk (0x1UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_0 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_0_Pos (0UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_0 (Bit 0)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_1_Msk (0x2UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_1 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_1_Pos (1UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_1 (Bit 1)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_2_Msk (0x4UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_2 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_2_Pos (2UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_2 (Bit 2)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_3_Msk (0x8UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_3 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_3_Pos (3UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_3 (Bit 3)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_4_Msk (0x10UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_4 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_4_Pos (4UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_4 (Bit 4)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_5_Msk (0x20UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_5 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO0_STS_5_Pos (5UL) |
PMU GPIO_WAKE_STATUS: GPIO0_STS_5 (Bit 5)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_0_Msk (0x100UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_0 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_0_Pos (8UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_0 (Bit 8)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_1_Msk (0x200UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_1 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_1_Pos (9UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_1 (Bit 9)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_2_Msk (0x400UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_2 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_2_Pos (10UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_2 (Bit 10)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_4_Msk (0x1000UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_4 (Bitfield-Mask: 0x01)
#define PMU_GPIO_WAKE_STATUS_GPIO1_STS_4_Pos (12UL) |
PMU GPIO_WAKE_STATUS: GPIO1_STS_4 (Bit 12)
#define PMU_GPUDATA0to3_DATA0_Msk (0xffUL) |
PMU GPUDATA0to3: DATA0 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA0to3_DATA0_Pos (0UL) |
PMU GPUDATA0to3: DATA0 (Bit 0)
#define PMU_GPUDATA0to3_DATA1_Msk (0xff00UL) |
PMU GPUDATA0to3: DATA1 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA0to3_DATA1_Pos (8UL) |
PMU GPUDATA0to3: DATA1 (Bit 8)
#define PMU_GPUDATA0to3_DATA2_Msk (0xff0000UL) |
PMU GPUDATA0to3: DATA2 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA0to3_DATA2_Pos (16UL) |
PMU GPUDATA0to3: DATA2 (Bit 16)
#define PMU_GPUDATA0to3_DATA3_Msk (0xff000000UL) |
PMU GPUDATA0to3: DATA3 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA0to3_DATA3_Pos (24UL) |
PMU GPUDATA0to3: DATA3 (Bit 24)
#define PMU_GPUDATA4to7_DATA4_Msk (0xffUL) |
PMU GPUDATA4to7: DATA4 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA4to7_DATA4_Pos (0UL) |
PMU GPUDATA4to7: DATA4 (Bit 0)
#define PMU_GPUDATA4to7_DATA5_Msk (0xff00UL) |
PMU GPUDATA4to7: DATA5 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA4to7_DATA5_Pos (8UL) |
PMU GPUDATA4to7: DATA5 (Bit 8)
#define PMU_GPUDATA4to7_DATA6_Msk (0xff0000UL) |
PMU GPUDATA4to7: DATA6 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA4to7_DATA6_Pos (16UL) |
PMU GPUDATA4to7: DATA6 (Bit 16)
#define PMU_GPUDATA4to7_DATA7_Msk (0xff000000UL) |
PMU GPUDATA4to7: DATA7 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA4to7_DATA7_Pos (24UL) |
PMU GPUDATA4to7: DATA7 (Bit 24)
#define PMU_GPUDATA8to11_DATA10_Msk (0xff0000UL) |
PMU GPUDATA8to11: DATA10 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA8to11_DATA10_Pos (16UL) |
PMU GPUDATA8to11: DATA10 (Bit 16)
#define PMU_GPUDATA8to11_DATA11_Msk (0xff000000UL) |
PMU GPUDATA8to11: DATA11 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA8to11_DATA11_Pos (24UL) |
PMU GPUDATA8to11: DATA11 (Bit 24)
#define PMU_GPUDATA8to11_DATA8_Msk (0xffUL) |
PMU GPUDATA8to11: DATA8 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA8to11_DATA8_Pos (0UL) |
PMU GPUDATA8to11: DATA8 (Bit 0)
#define PMU_GPUDATA8to11_DATA9_Msk (0xff00UL) |
PMU GPUDATA8to11: DATA9 (Bitfield-Mask: 0xff)
#define PMU_GPUDATA8to11_DATA9_Pos (8UL) |
PMU GPUDATA8to11: DATA9 (Bit 8)
#define PMU_HIGHSIDE_CTRL_HS1_CYC_EN_Msk (0x4UL) |
PMU HIGHSIDE_CTRL: HS1_CYC_EN (Bitfield-Mask: 0x01)
#define PMU_HIGHSIDE_CTRL_HS1_CYC_EN_Pos (2UL) |
PMU HIGHSIDE_CTRL: HS1_CYC_EN (Bit 2)
#define PMU_HIGHSIDE_CTRL_SPARE_Msk (0x400UL) |
PMU HIGHSIDE_CTRL: SPARE (Bitfield-Mask: 0x01)
#define PMU_HIGHSIDE_CTRL_SPARE_Pos (10UL) |
PMU HIGHSIDE_CTRL: SPARE (Bit 10)
#define PMU_LIN_WAKE_EN_LIN_WAKE_EN_Msk (0x80UL) |
PMU LIN_WAKE_EN: LIN_WAKE_EN (Bitfield-Mask: 0x01)
#define PMU_LIN_WAKE_EN_LIN_WAKE_EN_Pos (7UL) |
PMU LIN_WAKE_EN: LIN_WAKE_EN (Bit 7)
#define PMU_MON_CNF1_MON1_CYC_Msk (0x8UL) |
PMU MON_CNF1: MON1_CYC (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_CYC_Pos (3UL) |
PMU MON_CNF1: MON1_CYC (Bit 3)
#define PMU_MON_CNF1_MON1_EN_Msk (0x1UL) |
PMU MON_CNF1: MON1_EN (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_EN_Pos (0UL) |
PMU MON_CNF1: MON1_EN (Bit 0)
#define PMU_MON_CNF1_MON1_FALL_Msk (0x2UL) |
PMU MON_CNF1: MON1_FALL (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_FALL_Pos (1UL) |
PMU MON_CNF1: MON1_FALL (Bit 1)
#define PMU_MON_CNF1_MON1_NSLEEP_SPARE_Msk (0x40UL) |
PMU MON_CNF1: MON1_NSLEEP_SPARE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_NSLEEP_SPARE_Pos (6UL) |
PMU MON_CNF1: MON1_NSLEEP_SPARE (Bit 6)
#define PMU_MON_CNF1_MON1_PD_Msk (0x10UL) |
PMU MON_CNF1: MON1_PD (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_PD_Pos (4UL) |
PMU MON_CNF1: MON1_PD (Bit 4)
#define PMU_MON_CNF1_MON1_PU_Msk (0x20UL) |
PMU MON_CNF1: MON1_PU (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_PU_Pos (5UL) |
PMU MON_CNF1: MON1_PU (Bit 5)
#define PMU_MON_CNF1_MON1_RISE_Msk (0x4UL) |
PMU MON_CNF1: MON1_RISE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_RISE_Pos (2UL) |
PMU MON_CNF1: MON1_RISE (Bit 2)
#define PMU_MON_CNF1_MON1_STS_Msk (0x80UL) |
PMU MON_CNF1: MON1_STS (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON1_STS_Pos (7UL) |
PMU MON_CNF1: MON1_STS (Bit 7)
#define PMU_MON_CNF1_MON2_CYC_Msk (0x800UL) |
PMU MON_CNF1: MON2_CYC (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_CYC_Pos (11UL) |
PMU MON_CNF1: MON2_CYC (Bit 11)
#define PMU_MON_CNF1_MON2_EN_Msk (0x100UL) |
PMU MON_CNF1: MON2_EN (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_EN_Pos (8UL) |
PMU MON_CNF1: MON2_EN (Bit 8)
#define PMU_MON_CNF1_MON2_FALL_Msk (0x200UL) |
PMU MON_CNF1: MON2_FALL (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_FALL_Pos (9UL) |
PMU MON_CNF1: MON2_FALL (Bit 9)
#define PMU_MON_CNF1_MON2_NSLEEP_SPARE_Msk (0x4000UL) |
PMU MON_CNF1: MON2_NSLEEP_SPARE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_NSLEEP_SPARE_Pos (14UL) |
PMU MON_CNF1: MON2_NSLEEP_SPARE (Bit 14)
#define PMU_MON_CNF1_MON2_PD_Msk (0x1000UL) |
PMU MON_CNF1: MON2_PD (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_PD_Pos (12UL) |
PMU MON_CNF1: MON2_PD (Bit 12)
#define PMU_MON_CNF1_MON2_PU_Msk (0x2000UL) |
PMU MON_CNF1: MON2_PU (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_PU_Pos (13UL) |
PMU MON_CNF1: MON2_PU (Bit 13)
#define PMU_MON_CNF1_MON2_RISE_Msk (0x400UL) |
PMU MON_CNF1: MON2_RISE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_RISE_Pos (10UL) |
PMU MON_CNF1: MON2_RISE (Bit 10)
#define PMU_MON_CNF1_MON2_STS_Msk (0x8000UL) |
PMU MON_CNF1: MON2_STS (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON2_STS_Pos (15UL) |
PMU MON_CNF1: MON2_STS (Bit 15)
#define PMU_MON_CNF1_MON3_CYC_Msk (0x80000UL) |
PMU MON_CNF1: MON3_CYC (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_CYC_Pos (19UL) |
PMU MON_CNF1: MON3_CYC (Bit 19)
#define PMU_MON_CNF1_MON3_EN_Msk (0x10000UL) |
PMU MON_CNF1: MON3_EN (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_EN_Pos (16UL) |
PMU MON_CNF1: MON3_EN (Bit 16)
#define PMU_MON_CNF1_MON3_FALL_Msk (0x20000UL) |
PMU MON_CNF1: MON3_FALL (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_FALL_Pos (17UL) |
PMU MON_CNF1: MON3_FALL (Bit 17)
#define PMU_MON_CNF1_MON3_NSLEEP_SPARE_Msk (0x400000UL) |
PMU MON_CNF1: MON3_NSLEEP_SPARE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_NSLEEP_SPARE_Pos (22UL) |
PMU MON_CNF1: MON3_NSLEEP_SPARE (Bit 22)
#define PMU_MON_CNF1_MON3_PD_Msk (0x100000UL) |
PMU MON_CNF1: MON3_PD (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_PD_Pos (20UL) |
PMU MON_CNF1: MON3_PD (Bit 20)
#define PMU_MON_CNF1_MON3_PU_Msk (0x200000UL) |
PMU MON_CNF1: MON3_PU (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_PU_Pos (21UL) |
PMU MON_CNF1: MON3_PU (Bit 21)
#define PMU_MON_CNF1_MON3_RISE_Msk (0x40000UL) |
PMU MON_CNF1: MON3_RISE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_RISE_Pos (18UL) |
PMU MON_CNF1: MON3_RISE (Bit 18)
#define PMU_MON_CNF1_MON3_STS_Msk (0x800000UL) |
PMU MON_CNF1: MON3_STS (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON3_STS_Pos (23UL) |
PMU MON_CNF1: MON3_STS (Bit 23)
#define PMU_MON_CNF1_MON4_CYC_Msk (0x8000000UL) |
PMU MON_CNF1: MON4_CYC (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_CYC_Pos (27UL) |
PMU MON_CNF1: MON4_CYC (Bit 27)
#define PMU_MON_CNF1_MON4_EN_Msk (0x1000000UL) |
PMU MON_CNF1: MON4_EN (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_EN_Pos (24UL) |
PMU MON_CNF1: MON4_EN (Bit 24)
#define PMU_MON_CNF1_MON4_FALL_Msk (0x2000000UL) |
PMU MON_CNF1: MON4_FALL (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_FALL_Pos (25UL) |
PMU MON_CNF1: MON4_FALL (Bit 25)
#define PMU_MON_CNF1_MON4_NSLEEP_SPARE_Msk (0x40000000UL) |
PMU MON_CNF1: MON4_NSLEEP_SPARE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_NSLEEP_SPARE_Pos (30UL) |
PMU MON_CNF1: MON4_NSLEEP_SPARE (Bit 30)
#define PMU_MON_CNF1_MON4_PD_Msk (0x10000000UL) |
PMU MON_CNF1: MON4_PD (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_PD_Pos (28UL) |
PMU MON_CNF1: MON4_PD (Bit 28)
#define PMU_MON_CNF1_MON4_PU_Msk (0x20000000UL) |
PMU MON_CNF1: MON4_PU (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_PU_Pos (29UL) |
PMU MON_CNF1: MON4_PU (Bit 29)
#define PMU_MON_CNF1_MON4_RISE_Msk (0x4000000UL) |
PMU MON_CNF1: MON4_RISE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_RISE_Pos (26UL) |
PMU MON_CNF1: MON4_RISE (Bit 26)
#define PMU_MON_CNF1_MON4_STS_Msk (0x80000000UL) |
PMU MON_CNF1: MON4_STS (Bitfield-Mask: 0x01)
#define PMU_MON_CNF1_MON4_STS_Pos (31UL) |
PMU MON_CNF1: MON4_STS (Bit 31)
#define PMU_MON_CNF2_MON5_CYC_Msk (0x8UL) |
PMU MON_CNF2: MON5_CYC (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_CYC_Pos (3UL) |
PMU MON_CNF2: MON5_CYC (Bit 3)
#define PMU_MON_CNF2_MON5_EN_Msk (0x1UL) |
PMU MON_CNF2: MON5_EN (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_EN_Pos (0UL) |
PMU MON_CNF2: MON5_EN (Bit 0)
#define PMU_MON_CNF2_MON5_FALL_Msk (0x2UL) |
PMU MON_CNF2: MON5_FALL (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_FALL_Pos (1UL) |
PMU MON_CNF2: MON5_FALL (Bit 1)
#define PMU_MON_CNF2_MON5_NSLEEP_SPARE_Msk (0x40UL) |
PMU MON_CNF2: MON5_NSLEEP_SPARE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_NSLEEP_SPARE_Pos (6UL) |
PMU MON_CNF2: MON5_NSLEEP_SPARE (Bit 6)
#define PMU_MON_CNF2_MON5_PD_Msk (0x10UL) |
PMU MON_CNF2: MON5_PD (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_PD_Pos (4UL) |
PMU MON_CNF2: MON5_PD (Bit 4)
#define PMU_MON_CNF2_MON5_PU_Msk (0x20UL) |
PMU MON_CNF2: MON5_PU (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_PU_Pos (5UL) |
PMU MON_CNF2: MON5_PU (Bit 5)
#define PMU_MON_CNF2_MON5_RISE_Msk (0x4UL) |
PMU MON_CNF2: MON5_RISE (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_RISE_Pos (2UL) |
PMU MON_CNF2: MON5_RISE (Bit 2)
#define PMU_MON_CNF2_MON5_STS_Msk (0x80UL) |
PMU MON_CNF2: MON5_STS (Bitfield-Mask: 0x01)
#define PMU_MON_CNF2_MON5_STS_Pos (7UL) |
PMU MON_CNF2: MON5_STS (Bit 7)
#define PMU_OT_CTRL_PMU_OT_EN_Msk (0x80UL) |
PMU OT_CTRL: PMU_OT_EN (Bitfield-Mask: 0x01)
#define PMU_OT_CTRL_PMU_OT_EN_Pos (7UL) |
PMU OT_CTRL: PMU_OT_EN (Bit 7)
#define PMU_OT_CTRL_PMU_OT_INT_EN_Msk (0x20UL) |
PMU OT_CTRL: PMU_OT_INT_EN (Bitfield-Mask: 0x01)
#define PMU_OT_CTRL_PMU_OT_INT_EN_Pos (5UL) |
PMU OT_CTRL: PMU_OT_INT_EN (Bit 5)
#define PMU_OT_CTRL_PMU_OT_TH_CNF_Msk (0xfUL) |
PMU OT_CTRL: PMU_OT_TH_CNF (Bitfield-Mask: 0x0f)
#define PMU_OT_CTRL_PMU_OT_TH_CNF_Pos (0UL) |
PMU OT_CTRL: PMU_OT_TH_CNF (Bit 0)
#define PMU_OT_CTRL_PMU_OT_WAKE_EN_Msk (0x40UL) |
PMU OT_CTRL: PMU_OT_WAKE_EN (Bitfield-Mask: 0x01)
#define PMU_OT_CTRL_PMU_OT_WAKE_EN_Pos (6UL) |
PMU OT_CTRL: PMU_OT_WAKE_EN (Bit 6)
#define PMU_PORCFG_CNF_FILT_Msk (0x3UL) |
PMU PORCFG: CNF_FILT (Bitfield-Mask: 0x03)
#define PMU_PORCFG_CNF_FILT_Pos (0UL) |
PMU PORCFG: CNF_FILT (Bit 0)
#define PMU_RESET_STS_LOCKUP_Msk (0x400UL) |
PMU RESET_STS: LOCKUP (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_LOCKUP_Pos (10UL) |
PMU RESET_STS: LOCKUP (Bit 10)
#define PMU_RESET_STS_PMU_ClkWDT_Msk (0x10UL) |
PMU RESET_STS: PMU_ClkWDT (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_ClkWDT_Pos (4UL) |
PMU RESET_STS: PMU_ClkWDT (Bit 4)
#define PMU_RESET_STS_PMU_ExtWDT_Msk (0x20UL) |
PMU RESET_STS: PMU_ExtWDT (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_ExtWDT_Pos (5UL) |
PMU RESET_STS: PMU_ExtWDT (Bit 5)
#define PMU_RESET_STS_PMU_IntWDT_Msk (0x100UL) |
PMU RESET_STS: PMU_IntWDT (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_IntWDT_Pos (8UL) |
PMU RESET_STS: PMU_IntWDT (Bit 8)
#define PMU_RESET_STS_PMU_LPR_Msk (0x8UL) |
PMU RESET_STS: PMU_LPR (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_LPR_Pos (3UL) |
PMU RESET_STS: PMU_LPR (Bit 3)
#define PMU_RESET_STS_PMU_PIN_Msk (0x40UL) |
PMU RESET_STS: PMU_PIN (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_PIN_Pos (6UL) |
PMU RESET_STS: PMU_PIN (Bit 6)
#define PMU_RESET_STS_PMU_SleepEX_Msk (0x4UL) |
PMU RESET_STS: PMU_SleepEX (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_SleepEX_Pos (2UL) |
PMU RESET_STS: PMU_SleepEX (Bit 2)
#define PMU_RESET_STS_PMU_SOFT_Msk (0x200UL) |
PMU RESET_STS: PMU_SOFT (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_SOFT_Pos (9UL) |
PMU RESET_STS: PMU_SOFT (Bit 9)
#define PMU_RESET_STS_PMU_VS_POR_Msk (0x80UL) |
PMU RESET_STS: PMU_VS_POR (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_VS_POR_Pos (7UL) |
PMU RESET_STS: PMU_VS_POR (Bit 7)
#define PMU_RESET_STS_PMU_WAKE_Msk (0x2UL) |
PMU RESET_STS: PMU_WAKE (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_PMU_WAKE_Pos (1UL) |
PMU RESET_STS: PMU_WAKE (Bit 1)
#define PMU_RESET_STS_SYS_FAIL_Msk (0x1UL) |
PMU RESET_STS: SYS_FAIL (Bitfield-Mask: 0x01)
#define PMU_RESET_STS_SYS_FAIL_Pos (0UL) |
PMU RESET_STS: SYS_FAIL (Bit 0)
#define PMU_SLEEP_CYC_SENSE_E01_Msk (0x3000UL) |
PMU SLEEP: CYC_SENSE_E01 (Bitfield-Mask: 0x03)
#define PMU_SLEEP_CYC_SENSE_E01_Pos (12UL) |
PMU SLEEP: CYC_SENSE_E01 (Bit 12)
#define PMU_SLEEP_CYC_SENSE_EN_Msk (0x8UL) |
PMU SLEEP: CYC_SENSE_EN (Bitfield-Mask: 0x01)
#define PMU_SLEEP_CYC_SENSE_EN_Pos (3UL) |
PMU SLEEP: CYC_SENSE_EN (Bit 3)
#define PMU_SLEEP_CYC_SENSE_M03_Msk (0xf00UL) |
PMU SLEEP: CYC_SENSE_M03 (Bitfield-Mask: 0x0f)
#define PMU_SLEEP_CYC_SENSE_M03_Pos (8UL) |
PMU SLEEP: CYC_SENSE_M03 (Bit 8)
#define PMU_SLEEP_CYC_SENSE_S_DEL_Msk (0x7000000UL) |
PMU SLEEP: CYC_SENSE_S_DEL (Bitfield-Mask: 0x07)
#define PMU_SLEEP_CYC_SENSE_S_DEL_Pos (24UL) |
PMU SLEEP: CYC_SENSE_S_DEL (Bit 24)
#define PMU_SLEEP_CYC_WAKE_E01_Msk (0x300000UL) |
PMU SLEEP: CYC_WAKE_E01 (Bitfield-Mask: 0x03)
#define PMU_SLEEP_CYC_WAKE_E01_Pos (20UL) |
PMU SLEEP: CYC_WAKE_E01 (Bit 20)
#define PMU_SLEEP_CYC_WAKE_EN_Msk (0x4UL) |
PMU SLEEP: CYC_WAKE_EN (Bitfield-Mask: 0x01)
#define PMU_SLEEP_CYC_WAKE_EN_Pos (2UL) |
PMU SLEEP: CYC_WAKE_EN (Bit 2)
#define PMU_SLEEP_CYC_WAKE_M03_Msk (0xf0000UL) |
PMU SLEEP: CYC_WAKE_M03 (Bitfield-Mask: 0x0f)
#define PMU_SLEEP_CYC_WAKE_M03_Pos (16UL) |
PMU SLEEP: CYC_WAKE_M03 (Bit 16)
#define PMU_SLEEP_EN_0V9_N_Msk (0x2UL) |
PMU SLEEP: EN_0V9_N (Bitfield-Mask: 0x01)
#define PMU_SLEEP_EN_0V9_N_Pos (1UL) |
PMU SLEEP: EN_0V9_N (Bit 1)
#define PMU_SLEEP_WAKE_W_RST_Msk (0x1UL) |
PMU SLEEP: WAKE_W_RST (Bitfield-Mask: 0x01)
#define PMU_SLEEP_WAKE_W_RST_Pos (0UL) |
PMU SLEEP: WAKE_W_RST (Bit 0)
#define PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk (0x4UL) |
PMU SUPPLY_STS: PMU_1V5_FAIL_EN (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos (2UL) |
PMU SUPPLY_STS: PMU_1V5_FAIL_EN (Bit 2)
#define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Msk (0x2UL) |
PMU SUPPLY_STS: PMU_1V5_OVERLOAD (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Pos (1UL) |
PMU SUPPLY_STS: PMU_1V5_OVERLOAD (Bit 1)
#define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_SC_Msk (0x200UL) |
PMU SUPPLY_STS: PMU_1V5_OVERLOAD_SC (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_SC_Pos (9UL) |
PMU SUPPLY_STS: PMU_1V5_OVERLOAD_SC (Bit 9)
#define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Msk (0x1UL) |
PMU SUPPLY_STS: PMU_1V5_OVERVOLT (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Pos (0UL) |
PMU SUPPLY_STS: PMU_1V5_OVERVOLT (Bit 0)
#define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_SC_Msk (0x100UL) |
PMU SUPPLY_STS: PMU_1V5_OVERVOLT_SC (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_SC_Pos (8UL) |
PMU SUPPLY_STS: PMU_1V5_OVERVOLT_SC (Bit 8)
#define PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk (0x40UL) |
PMU SUPPLY_STS: PMU_5V_FAIL_EN (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos (6UL) |
PMU SUPPLY_STS: PMU_5V_FAIL_EN (Bit 6)
#define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Msk (0x20UL) |
PMU SUPPLY_STS: PMU_5V_OVERLOAD (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Pos (5UL) |
PMU SUPPLY_STS: PMU_5V_OVERLOAD (Bit 5)
#define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_SC_Msk (0x2000UL) |
PMU SUPPLY_STS: PMU_5V_OVERLOAD_SC (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_SC_Pos (13UL) |
PMU SUPPLY_STS: PMU_5V_OVERLOAD_SC (Bit 13)
#define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Msk (0x10UL) |
PMU SUPPLY_STS: PMU_5V_OVERVOLT (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Pos (4UL) |
PMU SUPPLY_STS: PMU_5V_OVERVOLT (Bit 4)
#define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_SC_Msk (0x1000UL) |
PMU SUPPLY_STS: PMU_5V_OVERVOLT_SC (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_SC_Pos (12UL) |
PMU SUPPLY_STS: PMU_5V_OVERVOLT_SC (Bit 12)
#define PMU_SUPPLY_STS_PMU_OVERTEMP_Msk (0x8UL) |
PMU SUPPLY_STS: PMU_OVERTEMP (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_OVERTEMP_Pos (3UL) |
PMU SUPPLY_STS: PMU_OVERTEMP (Bit 3)
#define PMU_SUPPLY_STS_PMU_OVERTEMP_SC_Msk (0x800UL) |
PMU SUPPLY_STS: PMU_OVERTEMP_SC (Bitfield-Mask: 0x01)
#define PMU_SUPPLY_STS_PMU_OVERTEMP_SC_Pos (11UL) |
PMU SUPPLY_STS: PMU_OVERTEMP_SC (Bit 11)
#define PMU_VDDEXT_CTRL_VDDEXT_CYC_EN_Msk (0x2UL) |
PMU VDDEXT_CTRL: VDDEXT_CYC_EN (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_CYC_EN_Pos (1UL) |
PMU VDDEXT_CTRL: VDDEXT_CYC_EN (Bit 1)
#define PMU_VDDEXT_CTRL_VDDEXT_ENABLE_Msk (0x1UL) |
PMU VDDEXT_CTRL: VDDEXT_ENABLE (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_ENABLE_Pos (0UL) |
PMU VDDEXT_CTRL: VDDEXT_ENABLE (Bit 0)
#define PMU_VDDEXT_CTRL_VDDEXT_FAIL_EN_Msk (0x4UL) |
PMU VDDEXT_CTRL: VDDEXT_FAIL_EN (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_FAIL_EN_Pos (2UL) |
PMU VDDEXT_CTRL: VDDEXT_FAIL_EN (Bit 2)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_IS_Msk (0x8UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_IS (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_IS_Pos (3UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_IS (Bit 3)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_ISC_Msk (0x800UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_ISC (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_ISC_Pos (11UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_ISC (Bit 11)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_Msk (0x40UL) |
PMU VDDEXT_CTRL: VDDEXT_OT (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_Pos (6UL) |
PMU VDDEXT_CTRL: VDDEXT_OT (Bit 6)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_SC_Msk (0x2000UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_SC (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_SC_Pos (13UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_SC (Bit 13)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_STS_Msk (0x20UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_STS (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_OT_STS_Pos (5UL) |
PMU VDDEXT_CTRL: VDDEXT_OT_STS (Bit 5)
#define PMU_VDDEXT_CTRL_VDDEXT_STABLE_Msk (0x80UL) |
PMU VDDEXT_CTRL: VDDEXT_STABLE (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_STABLE_Pos (7UL) |
PMU VDDEXT_CTRL: VDDEXT_STABLE (Bit 7)
#define PMU_VDDEXT_CTRL_VDDEXT_UV_IS_Msk (0x10UL) |
PMU VDDEXT_CTRL: VDDEXT_UV_IS (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_UV_IS_Pos (4UL) |
PMU VDDEXT_CTRL: VDDEXT_UV_IS (Bit 4)
#define PMU_VDDEXT_CTRL_VDDEXT_UV_ISC_Msk (0x1000UL) |
PMU VDDEXT_CTRL: VDDEXT_UV_ISC (Bitfield-Mask: 0x01)
#define PMU_VDDEXT_CTRL_VDDEXT_UV_ISC_Pos (12UL) |
PMU VDDEXT_CTRL: VDDEXT_UV_ISC (Bit 12)
#define PMU_WAKE_CNF_GPIO0_CYC_0_Msk (0x10000UL) |
PMU WAKE_CNF_GPIO0: CYC_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_CYC_0_Pos (16UL) |
PMU WAKE_CNF_GPIO0: CYC_0 (Bit 16)
#define PMU_WAKE_CNF_GPIO0_CYC_1_Msk (0x20000UL) |
PMU WAKE_CNF_GPIO0: CYC_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_CYC_1_Pos (17UL) |
PMU WAKE_CNF_GPIO0: CYC_1 (Bit 17)
#define PMU_WAKE_CNF_GPIO0_CYC_2_Msk (0x40000UL) |
PMU WAKE_CNF_GPIO0: CYC_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_CYC_2_Pos (18UL) |
PMU WAKE_CNF_GPIO0: CYC_2 (Bit 18)
#define PMU_WAKE_CNF_GPIO0_CYC_3_Msk (0x80000UL) |
PMU WAKE_CNF_GPIO0: CYC_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_CYC_3_Pos (19UL) |
PMU WAKE_CNF_GPIO0: CYC_3 (Bit 19)
#define PMU_WAKE_CNF_GPIO0_CYC_4_Msk (0x100000UL) |
PMU WAKE_CNF_GPIO0: CYC_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_CYC_4_Pos (20UL) |
PMU WAKE_CNF_GPIO0: CYC_4 (Bit 20)
#define PMU_WAKE_CNF_GPIO0_CYC_5_Msk (0x200000UL) |
PMU WAKE_CNF_GPIO0: CYC_5 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_CYC_5_Pos (21UL) |
PMU WAKE_CNF_GPIO0: CYC_5 (Bit 21)
#define PMU_WAKE_CNF_GPIO0_FA_0_Msk (0x100UL) |
PMU WAKE_CNF_GPIO0: FA_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_FA_0_Pos (8UL) |
PMU WAKE_CNF_GPIO0: FA_0 (Bit 8)
#define PMU_WAKE_CNF_GPIO0_FA_1_Msk (0x200UL) |
PMU WAKE_CNF_GPIO0: FA_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_FA_1_Pos (9UL) |
PMU WAKE_CNF_GPIO0: FA_1 (Bit 9)
#define PMU_WAKE_CNF_GPIO0_FA_2_Msk (0x400UL) |
PMU WAKE_CNF_GPIO0: FA_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_FA_2_Pos (10UL) |
PMU WAKE_CNF_GPIO0: FA_2 (Bit 10)
#define PMU_WAKE_CNF_GPIO0_FA_3_Msk (0x800UL) |
PMU WAKE_CNF_GPIO0: FA_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_FA_3_Pos (11UL) |
PMU WAKE_CNF_GPIO0: FA_3 (Bit 11)
#define PMU_WAKE_CNF_GPIO0_FA_4_Msk (0x1000UL) |
PMU WAKE_CNF_GPIO0: FA_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_FA_4_Pos (12UL) |
PMU WAKE_CNF_GPIO0: FA_4 (Bit 12)
#define PMU_WAKE_CNF_GPIO0_FA_5_Msk (0x2000UL) |
PMU WAKE_CNF_GPIO0: FA_5 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_FA_5_Pos (13UL) |
PMU WAKE_CNF_GPIO0: FA_5 (Bit 13)
#define PMU_WAKE_CNF_GPIO0_RI_0_Msk (0x1UL) |
PMU WAKE_CNF_GPIO0: RI_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_RI_0_Pos (0UL) |
PMU WAKE_CNF_GPIO0: RI_0 (Bit 0)
#define PMU_WAKE_CNF_GPIO0_RI_1_Msk (0x2UL) |
PMU WAKE_CNF_GPIO0: RI_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_RI_1_Pos (1UL) |
PMU WAKE_CNF_GPIO0: RI_1 (Bit 1)
#define PMU_WAKE_CNF_GPIO0_RI_2_Msk (0x4UL) |
PMU WAKE_CNF_GPIO0: RI_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_RI_2_Pos (2UL) |
PMU WAKE_CNF_GPIO0: RI_2 (Bit 2)
#define PMU_WAKE_CNF_GPIO0_RI_3_Msk (0x8UL) |
PMU WAKE_CNF_GPIO0: RI_3 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_RI_3_Pos (3UL) |
PMU WAKE_CNF_GPIO0: RI_3 (Bit 3)
#define PMU_WAKE_CNF_GPIO0_RI_4_Msk (0x10UL) |
PMU WAKE_CNF_GPIO0: RI_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_RI_4_Pos (4UL) |
PMU WAKE_CNF_GPIO0: RI_4 (Bit 4)
#define PMU_WAKE_CNF_GPIO0_RI_5_Msk (0x20UL) |
PMU WAKE_CNF_GPIO0: RI_5 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO0_RI_5_Pos (5UL) |
PMU WAKE_CNF_GPIO0: RI_5 (Bit 5)
#define PMU_WAKE_CNF_GPIO1_CYC_0_Msk (0x10000UL) |
PMU WAKE_CNF_GPIO1: CYC_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_CYC_0_Pos (16UL) |
PMU WAKE_CNF_GPIO1: CYC_0 (Bit 16)
#define PMU_WAKE_CNF_GPIO1_CYC_1_Msk (0x20000UL) |
PMU WAKE_CNF_GPIO1: CYC_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_CYC_1_Pos (17UL) |
PMU WAKE_CNF_GPIO1: CYC_1 (Bit 17)
#define PMU_WAKE_CNF_GPIO1_CYC_2_Msk (0x40000UL) |
PMU WAKE_CNF_GPIO1: CYC_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_CYC_2_Pos (18UL) |
PMU WAKE_CNF_GPIO1: CYC_2 (Bit 18)
#define PMU_WAKE_CNF_GPIO1_CYC_4_Msk (0x100000UL) |
PMU WAKE_CNF_GPIO1: CYC_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_CYC_4_Pos (20UL) |
PMU WAKE_CNF_GPIO1: CYC_4 (Bit 20)
#define PMU_WAKE_CNF_GPIO1_FA_0_Msk (0x100UL) |
PMU WAKE_CNF_GPIO1: FA_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_FA_0_Pos (8UL) |
PMU WAKE_CNF_GPIO1: FA_0 (Bit 8)
#define PMU_WAKE_CNF_GPIO1_FA_1_Msk (0x200UL) |
PMU WAKE_CNF_GPIO1: FA_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_FA_1_Pos (9UL) |
PMU WAKE_CNF_GPIO1: FA_1 (Bit 9)
#define PMU_WAKE_CNF_GPIO1_FA_2_Msk (0x400UL) |
PMU WAKE_CNF_GPIO1: FA_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_FA_2_Pos (10UL) |
PMU WAKE_CNF_GPIO1: FA_2 (Bit 10)
#define PMU_WAKE_CNF_GPIO1_FA_4_Msk (0x1000UL) |
PMU WAKE_CNF_GPIO1: FA_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_FA_4_Pos (12UL) |
PMU WAKE_CNF_GPIO1: FA_4 (Bit 12)
#define PMU_WAKE_CNF_GPIO1_RI_0_Msk (0x1UL) |
PMU WAKE_CNF_GPIO1: RI_0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_RI_0_Pos (0UL) |
PMU WAKE_CNF_GPIO1: RI_0 (Bit 0)
#define PMU_WAKE_CNF_GPIO1_RI_1_Msk (0x2UL) |
PMU WAKE_CNF_GPIO1: RI_1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_RI_1_Pos (1UL) |
PMU WAKE_CNF_GPIO1: RI_1 (Bit 1)
#define PMU_WAKE_CNF_GPIO1_RI_2_Msk (0x4UL) |
PMU WAKE_CNF_GPIO1: RI_2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_RI_2_Pos (2UL) |
PMU WAKE_CNF_GPIO1: RI_2 (Bit 2)
#define PMU_WAKE_CNF_GPIO1_RI_4_Msk (0x10UL) |
PMU WAKE_CNF_GPIO1: RI_4 (Bitfield-Mask: 0x01)
#define PMU_WAKE_CNF_GPIO1_RI_4_Pos (4UL) |
PMU WAKE_CNF_GPIO1: RI_4 (Bit 4)
#define PMU_WAKE_STATUS_CYC_WAKE_Msk (0x10UL) |
PMU WAKE_STATUS: CYC_WAKE (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_CYC_WAKE_Pos (4UL) |
PMU WAKE_STATUS: CYC_WAKE (Bit 4)
#define PMU_WAKE_STATUS_FAIL_Msk (0x20UL) |
PMU WAKE_STATUS: FAIL (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_FAIL_Pos (5UL) |
PMU WAKE_STATUS: FAIL (Bit 5)
#define PMU_WAKE_STATUS_GPIO0_Msk (0x4UL) |
PMU WAKE_STATUS: GPIO0 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_GPIO0_Pos (2UL) |
PMU WAKE_STATUS: GPIO0 (Bit 2)
#define PMU_WAKE_STATUS_GPIO1_Msk (0x8UL) |
PMU WAKE_STATUS: GPIO1 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_GPIO1_Pos (3UL) |
PMU WAKE_STATUS: GPIO1 (Bit 3)
#define PMU_WAKE_STATUS_GPIO2_Msk (0x40UL) |
PMU WAKE_STATUS: GPIO2 (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_GPIO2_Pos (6UL) |
PMU WAKE_STATUS: GPIO2 (Bit 6)
#define PMU_WAKE_STATUS_LIN_WAKE_Msk (0x1UL) |
PMU WAKE_STATUS: LIN_WAKE (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_LIN_WAKE_Pos (0UL) |
PMU WAKE_STATUS: LIN_WAKE (Bit 0)
#define PMU_WAKE_STATUS_MON1_WAKE_STS_Msk (0x100UL) |
PMU WAKE_STATUS: MON1_WAKE_STS (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_MON1_WAKE_STS_Pos (8UL) |
PMU WAKE_STATUS: MON1_WAKE_STS (Bit 8)
#define PMU_WAKE_STATUS_MON2_WAKE_STS_Msk (0x200UL) |
PMU WAKE_STATUS: MON2_WAKE_STS (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_MON2_WAKE_STS_Pos (9UL) |
PMU WAKE_STATUS: MON2_WAKE_STS (Bit 9)
#define PMU_WAKE_STATUS_MON3_WAKE_STS_Msk (0x400UL) |
PMU WAKE_STATUS: MON3_WAKE_STS (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_MON3_WAKE_STS_Pos (10UL) |
PMU WAKE_STATUS: MON3_WAKE_STS (Bit 10)
#define PMU_WAKE_STATUS_MON4_WAKE_STS_Msk (0x800UL) |
PMU WAKE_STATUS: MON4_WAKE_STS (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_MON4_WAKE_STS_Pos (11UL) |
PMU WAKE_STATUS: MON4_WAKE_STS (Bit 11)
#define PMU_WAKE_STATUS_MON5_WAKE_STS_Msk (0x1000UL) |
PMU WAKE_STATUS: MON5_WAKE_STS (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_MON5_WAKE_STS_Pos (12UL) |
PMU WAKE_STATUS: MON5_WAKE_STS (Bit 12)
#define PMU_WAKE_STATUS_MON_Msk (0x2UL) |
PMU WAKE_STATUS: MON (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_MON_Pos (1UL) |
PMU WAKE_STATUS: MON (Bit 1)
#define PMU_WAKE_STATUS_PMU_OT_Msk (0x10000UL) |
PMU WAKE_STATUS: PMU_OT (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_PMU_OT_Pos (16UL) |
PMU WAKE_STATUS: PMU_OT (Bit 16)
#define PMU_WAKE_STATUS_VDDEXT_OT_Msk (0x20000UL) |
PMU WAKE_STATUS: VDDEXT_OT (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_VDDEXT_OT_Pos (17UL) |
PMU WAKE_STATUS: VDDEXT_OT (Bit 17)
#define PMU_WAKE_STATUS_VDDEXT_UV_Msk (0x40000UL) |
PMU WAKE_STATUS: VDDEXT_UV (Bitfield-Mask: 0x01)
#define PMU_WAKE_STATUS_VDDEXT_UV_Pos (18UL) |
PMU WAKE_STATUS: VDDEXT_UV (Bit 18)
#define PMU_WFS_LP_CLKWD_Msk (0x80UL) |
PMU WFS: LP_CLKWD (Bitfield-Mask: 0x01)
#define PMU_WFS_LP_CLKWD_Pos (7UL) |
PMU WFS: LP_CLKWD (Bit 7)
#define PMU_WFS_PMU_1V5_OVL_Msk (0x4UL) |
PMU WFS: PMU_1V5_OVL (Bitfield-Mask: 0x01)
#define PMU_WFS_PMU_1V5_OVL_Pos (2UL) |
PMU WFS: PMU_1V5_OVL (Bit 2)
#define PMU_WFS_PMU_5V_OVL_Msk (0x8UL) |
PMU WFS: PMU_5V_OVL (Bitfield-Mask: 0x01)
#define PMU_WFS_PMU_5V_OVL_Pos (3UL) |
PMU WFS: PMU_5V_OVL (Bit 3)
#define PMU_WFS_PMU_OT_FAIL_Msk (0x100UL) |
PMU WFS: PMU_OT_FAIL (Bitfield-Mask: 0x01)
#define PMU_WFS_PMU_OT_FAIL_Pos (8UL) |
PMU WFS: PMU_OT_FAIL (Bit 8)
#define PMU_WFS_SUPP_SHORT_Msk (0x1UL) |
PMU WFS: SUPP_SHORT (Bitfield-Mask: 0x01)
#define PMU_WFS_SUPP_SHORT_Pos (0UL) |
PMU WFS: SUPP_SHORT (Bit 0)
#define PMU_WFS_SUPP_TMOUT_Msk (0x2UL) |
PMU WFS: SUPP_TMOUT (Bitfield-Mask: 0x01)
#define PMU_WFS_SUPP_TMOUT_Pos (1UL) |
PMU WFS: SUPP_TMOUT (Bit 1)
#define PMU_WFS_SYS_CLK_WDT_Msk (0x10UL) |
PMU WFS: SYS_CLK_WDT (Bitfield-Mask: 0x01)
#define PMU_WFS_SYS_CLK_WDT_Pos (4UL) |
PMU WFS: SYS_CLK_WDT (Bit 4)
#define PMU_WFS_SYS_OT_Msk (0x20UL) |
PMU WFS: SYS_OT (Bitfield-Mask: 0x01)
#define PMU_WFS_SYS_OT_Pos (5UL) |
PMU WFS: SYS_OT (Bit 5)
#define PMU_WFS_WDT1_SEQ_FAIL_Msk (0x40UL) |
PMU WFS: WDT1_SEQ_FAIL (Bitfield-Mask: 0x01)
#define PMU_WFS_WDT1_SEQ_FAIL_Pos (6UL) |
PMU WFS: WDT1_SEQ_FAIL (Bit 6)
#define PORT_P0_ALTSEL0_PP0_Msk (0x1UL) |
PORT P0_ALTSEL0: PP0 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_PP0_Pos (0UL) |
PORT P0_ALTSEL0: PP0 (Bit 0)
#define PORT_P0_ALTSEL0_PP1_Msk (0x2UL) |
PORT P0_ALTSEL0: PP1 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_PP1_Pos (1UL) |
PORT P0_ALTSEL0: PP1 (Bit 1)
#define PORT_P0_ALTSEL0_PP2_Msk (0x4UL) |
PORT P0_ALTSEL0: PP2 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_PP2_Pos (2UL) |
PORT P0_ALTSEL0: PP2 (Bit 2)
#define PORT_P0_ALTSEL0_PP3_Msk (0x8UL) |
PORT P0_ALTSEL0: PP3 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_PP3_Pos (3UL) |
PORT P0_ALTSEL0: PP3 (Bit 3)
#define PORT_P0_ALTSEL0_PP4_Msk (0x10UL) |
PORT P0_ALTSEL0: PP4 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_PP4_Pos (4UL) |
PORT P0_ALTSEL0: PP4 (Bit 4)
#define PORT_P0_ALTSEL0_PP5_Msk (0x20UL) |
PORT P0_ALTSEL0: PP5 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL0_PP5_Pos (5UL) |
PORT P0_ALTSEL0: PP5 (Bit 5)
#define PORT_P0_ALTSEL1_PP0_Msk (0x1UL) |
PORT P0_ALTSEL1: PP0 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_PP0_Pos (0UL) |
PORT P0_ALTSEL1: PP0 (Bit 0)
#define PORT_P0_ALTSEL1_PP1_Msk (0x2UL) |
PORT P0_ALTSEL1: PP1 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_PP1_Pos (1UL) |
PORT P0_ALTSEL1: PP1 (Bit 1)
#define PORT_P0_ALTSEL1_PP2_Msk (0x4UL) |
PORT P0_ALTSEL1: PP2 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_PP2_Pos (2UL) |
PORT P0_ALTSEL1: PP2 (Bit 2)
#define PORT_P0_ALTSEL1_PP3_Msk (0x8UL) |
PORT P0_ALTSEL1: PP3 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_PP3_Pos (3UL) |
PORT P0_ALTSEL1: PP3 (Bit 3)
#define PORT_P0_ALTSEL1_PP4_Msk (0x10UL) |
PORT P0_ALTSEL1: PP4 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_PP4_Pos (4UL) |
PORT P0_ALTSEL1: PP4 (Bit 4)
#define PORT_P0_ALTSEL1_PP5_Msk (0x20UL) |
PORT P0_ALTSEL1: PP5 (Bitfield-Mask: 0x01)
#define PORT_P0_ALTSEL1_PP5_Pos (5UL) |
PORT P0_ALTSEL1: PP5 (Bit 5)
#define PORT_P0_DATA_PP0_Msk (0x1UL) |
PORT P0_DATA: PP0 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP0_Pos (0UL) |
PORT P0_DATA: PP0 (Bit 0)
#define PORT_P0_DATA_PP0_STS_Msk (0x10000UL) |
PORT P0_DATA: PP0_STS (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP0_STS_Pos (16UL) |
PORT P0_DATA: PP0_STS (Bit 16)
#define PORT_P0_DATA_PP1_Msk (0x2UL) |
PORT P0_DATA: PP1 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP1_Pos (1UL) |
PORT P0_DATA: PP1 (Bit 1)
#define PORT_P0_DATA_PP1_STS_Msk (0x20000UL) |
PORT P0_DATA: PP1_STS (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP1_STS_Pos (17UL) |
PORT P0_DATA: PP1_STS (Bit 17)
#define PORT_P0_DATA_PP2_Msk (0x4UL) |
PORT P0_DATA: PP2 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP2_Pos (2UL) |
PORT P0_DATA: PP2 (Bit 2)
#define PORT_P0_DATA_PP2_STS_Msk (0x40000UL) |
PORT P0_DATA: PP2_STS (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP2_STS_Pos (18UL) |
PORT P0_DATA: PP2_STS (Bit 18)
#define PORT_P0_DATA_PP3_Msk (0x8UL) |
PORT P0_DATA: PP3 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP3_Pos (3UL) |
PORT P0_DATA: PP3 (Bit 3)
#define PORT_P0_DATA_PP3_STS_Msk (0x80000UL) |
PORT P0_DATA: PP3_STS (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP3_STS_Pos (19UL) |
PORT P0_DATA: PP3_STS (Bit 19)
#define PORT_P0_DATA_PP4_Msk (0x10UL) |
PORT P0_DATA: PP4 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP4_Pos (4UL) |
PORT P0_DATA: PP4 (Bit 4)
#define PORT_P0_DATA_PP4_STS_Msk (0x100000UL) |
PORT P0_DATA: PP4_STS (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP4_STS_Pos (20UL) |
PORT P0_DATA: PP4_STS (Bit 20)
#define PORT_P0_DATA_PP5_Msk (0x20UL) |
PORT P0_DATA: PP5 (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP5_Pos (5UL) |
PORT P0_DATA: PP5 (Bit 5)
#define PORT_P0_DATA_PP5_STS_Msk (0x200000UL) |
PORT P0_DATA: PP5_STS (Bitfield-Mask: 0x01)
#define PORT_P0_DATA_PP5_STS_Pos (21UL) |
PORT P0_DATA: PP5_STS (Bit 21)
#define PORT_P0_DIR_PP0_INEN_Msk (0x10000UL) |
PORT P0_DIR: PP0_INEN (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP0_INEN_Pos (16UL) |
PORT P0_DIR: PP0_INEN (Bit 16)
#define PORT_P0_DIR_PP0_Msk (0x1UL) |
PORT P0_DIR: PP0 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP0_Pos (0UL) |
PORT P0_DIR: PP0 (Bit 0)
#define PORT_P0_DIR_PP1_INEN_Msk (0x20000UL) |
PORT P0_DIR: PP1_INEN (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP1_INEN_Pos (17UL) |
PORT P0_DIR: PP1_INEN (Bit 17)
#define PORT_P0_DIR_PP1_Msk (0x2UL) |
PORT P0_DIR: PP1 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP1_Pos (1UL) |
PORT P0_DIR: PP1 (Bit 1)
#define PORT_P0_DIR_PP2_INEN_Msk (0x40000UL) |
PORT P0_DIR: PP2_INEN (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP2_INEN_Pos (18UL) |
PORT P0_DIR: PP2_INEN (Bit 18)
#define PORT_P0_DIR_PP2_Msk (0x4UL) |
PORT P0_DIR: PP2 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP2_Pos (2UL) |
PORT P0_DIR: PP2 (Bit 2)
#define PORT_P0_DIR_PP3_INEN_Msk (0x80000UL) |
PORT P0_DIR: PP3_INEN (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP3_INEN_Pos (19UL) |
PORT P0_DIR: PP3_INEN (Bit 19)
#define PORT_P0_DIR_PP3_Msk (0x8UL) |
PORT P0_DIR: PP3 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP3_Pos (3UL) |
PORT P0_DIR: PP3 (Bit 3)
#define PORT_P0_DIR_PP4_INEN_Msk (0x100000UL) |
PORT P0_DIR: PP4_INEN (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP4_INEN_Pos (20UL) |
PORT P0_DIR: PP4_INEN (Bit 20)
#define PORT_P0_DIR_PP4_Msk (0x10UL) |
PORT P0_DIR: PP4 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP4_Pos (4UL) |
PORT P0_DIR: PP4 (Bit 4)
#define PORT_P0_DIR_PP5_INEN_Msk (0x200000UL) |
PORT P0_DIR: PP5_INEN (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP5_INEN_Pos (21UL) |
PORT P0_DIR: PP5_INEN (Bit 21)
#define PORT_P0_DIR_PP5_Msk (0x20UL) |
PORT P0_DIR: PP5 (Bitfield-Mask: 0x01)
#define PORT_P0_DIR_PP5_Pos (5UL) |
PORT P0_DIR: PP5 (Bit 5)
#define PORT_P0_OD_PP0_Msk (0x1UL) |
PORT P0_OD: PP0 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_PP0_Pos (0UL) |
PORT P0_OD: PP0 (Bit 0)
#define PORT_P0_OD_PP1_Msk (0x2UL) |
PORT P0_OD: PP1 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_PP1_Pos (1UL) |
PORT P0_OD: PP1 (Bit 1)
#define PORT_P0_OD_PP2_Msk (0x4UL) |
PORT P0_OD: PP2 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_PP2_Pos (2UL) |
PORT P0_OD: PP2 (Bit 2)
#define PORT_P0_OD_PP3_Msk (0x8UL) |
PORT P0_OD: PP3 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_PP3_Pos (3UL) |
PORT P0_OD: PP3 (Bit 3)
#define PORT_P0_OD_PP4_Msk (0x10UL) |
PORT P0_OD: PP4 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_PP4_Pos (4UL) |
PORT P0_OD: PP4 (Bit 4)
#define PORT_P0_OD_PP5_Msk (0x20UL) |
PORT P0_OD: PP5 (Bitfield-Mask: 0x01)
#define PORT_P0_OD_PP5_Pos (5UL) |
PORT P0_OD: PP5 (Bit 5)
#define PORT_P0_PUDEN_PP0_Msk (0x1UL) |
PORT P0_PUDEN: PP0 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_PP0_Pos (0UL) |
PORT P0_PUDEN: PP0 (Bit 0)
#define PORT_P0_PUDEN_PP1_Msk (0x2UL) |
PORT P0_PUDEN: PP1 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_PP1_Pos (1UL) |
PORT P0_PUDEN: PP1 (Bit 1)
#define PORT_P0_PUDEN_PP2_Msk (0x4UL) |
PORT P0_PUDEN: PP2 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_PP2_Pos (2UL) |
PORT P0_PUDEN: PP2 (Bit 2)
#define PORT_P0_PUDEN_PP3_Msk (0x8UL) |
PORT P0_PUDEN: PP3 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_PP3_Pos (3UL) |
PORT P0_PUDEN: PP3 (Bit 3)
#define PORT_P0_PUDEN_PP4_Msk (0x10UL) |
PORT P0_PUDEN: PP4 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_PP4_Pos (4UL) |
PORT P0_PUDEN: PP4 (Bit 4)
#define PORT_P0_PUDEN_PP5_Msk (0x20UL) |
PORT P0_PUDEN: PP5 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDEN_PP5_Pos (5UL) |
PORT P0_PUDEN: PP5 (Bit 5)
#define PORT_P0_PUDSEL_PP0_Msk (0x1UL) |
PORT P0_PUDSEL: PP0 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_PP0_Pos (0UL) |
PORT P0_PUDSEL: PP0 (Bit 0)
#define PORT_P0_PUDSEL_PP1_Msk (0x2UL) |
PORT P0_PUDSEL: PP1 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_PP1_Pos (1UL) |
PORT P0_PUDSEL: PP1 (Bit 1)
#define PORT_P0_PUDSEL_PP2_Msk (0x4UL) |
PORT P0_PUDSEL: PP2 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_PP2_Pos (2UL) |
PORT P0_PUDSEL: PP2 (Bit 2)
#define PORT_P0_PUDSEL_PP3_Msk (0x8UL) |
PORT P0_PUDSEL: PP3 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_PP3_Pos (3UL) |
PORT P0_PUDSEL: PP3 (Bit 3)
#define PORT_P0_PUDSEL_PP4_Msk (0x10UL) |
PORT P0_PUDSEL: PP4 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_PP4_Pos (4UL) |
PORT P0_PUDSEL: PP4 (Bit 4)
#define PORT_P0_PUDSEL_PP5_Msk (0x20UL) |
PORT P0_PUDSEL: PP5 (Bitfield-Mask: 0x01)
#define PORT_P0_PUDSEL_PP5_Pos (5UL) |
PORT P0_PUDSEL: PP5 (Bit 5)
#define PORT_P1_ALTSEL0_PP0_Msk (0x1UL) |
PORT P1_ALTSEL0: PP0 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_PP0_Pos (0UL) |
PORT P1_ALTSEL0: PP0 (Bit 0)
#define PORT_P1_ALTSEL0_PP1_Msk (0x2UL) |
PORT P1_ALTSEL0: PP1 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_PP1_Pos (1UL) |
PORT P1_ALTSEL0: PP1 (Bit 1)
#define PORT_P1_ALTSEL0_PP2_Msk (0x4UL) |
PORT P1_ALTSEL0: PP2 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_PP2_Pos (2UL) |
PORT P1_ALTSEL0: PP2 (Bit 2)
#define PORT_P1_ALTSEL0_PP4_Msk (0x10UL) |
PORT P1_ALTSEL0: PP4 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL0_PP4_Pos (4UL) |
PORT P1_ALTSEL0: PP4 (Bit 4)
#define PORT_P1_ALTSEL1_PP0_Msk (0x1UL) |
PORT P1_ALTSEL1: PP0 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_PP0_Pos (0UL) |
PORT P1_ALTSEL1: PP0 (Bit 0)
#define PORT_P1_ALTSEL1_PP1_Msk (0x2UL) |
PORT P1_ALTSEL1: PP1 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_PP1_Pos (1UL) |
PORT P1_ALTSEL1: PP1 (Bit 1)
#define PORT_P1_ALTSEL1_PP2_Msk (0x4UL) |
PORT P1_ALTSEL1: PP2 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_PP2_Pos (2UL) |
PORT P1_ALTSEL1: PP2 (Bit 2)
#define PORT_P1_ALTSEL1_PP4_Msk (0x10UL) |
PORT P1_ALTSEL1: PP4 (Bitfield-Mask: 0x01)
#define PORT_P1_ALTSEL1_PP4_Pos (4UL) |
PORT P1_ALTSEL1: PP4 (Bit 4)
#define PORT_P1_DATA_PP0_Msk (0x1UL) |
PORT P1_DATA: PP0 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP0_Pos (0UL) |
PORT P1_DATA: PP0 (Bit 0)
#define PORT_P1_DATA_PP0_STS_Msk (0x10000UL) |
PORT P1_DATA: PP0_STS (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP0_STS_Pos (16UL) |
PORT P1_DATA: PP0_STS (Bit 16)
#define PORT_P1_DATA_PP1_Msk (0x2UL) |
PORT P1_DATA: PP1 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP1_Pos (1UL) |
PORT P1_DATA: PP1 (Bit 1)
#define PORT_P1_DATA_PP1_STS_Msk (0x20000UL) |
PORT P1_DATA: PP1_STS (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP1_STS_Pos (17UL) |
PORT P1_DATA: PP1_STS (Bit 17)
#define PORT_P1_DATA_PP2_Msk (0x4UL) |
PORT P1_DATA: PP2 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP2_Pos (2UL) |
PORT P1_DATA: PP2 (Bit 2)
#define PORT_P1_DATA_PP2_STS_Msk (0x40000UL) |
PORT P1_DATA: PP2_STS (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP2_STS_Pos (18UL) |
PORT P1_DATA: PP2_STS (Bit 18)
#define PORT_P1_DATA_PP4_Msk (0x10UL) |
PORT P1_DATA: PP4 (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP4_Pos (4UL) |
PORT P1_DATA: PP4 (Bit 4)
#define PORT_P1_DATA_PP4_STS_Msk (0x100000UL) |
PORT P1_DATA: PP4_STS (Bitfield-Mask: 0x01)
#define PORT_P1_DATA_PP4_STS_Pos (20UL) |
PORT P1_DATA: PP4_STS (Bit 20)
#define PORT_P1_DIR_PP0_INEN_Msk (0x10000UL) |
PORT P1_DIR: PP0_INEN (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP0_INEN_Pos (16UL) |
PORT P1_DIR: PP0_INEN (Bit 16)
#define PORT_P1_DIR_PP0_Msk (0x1UL) |
PORT P1_DIR: PP0 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP0_Pos (0UL) |
PORT P1_DIR: PP0 (Bit 0)
#define PORT_P1_DIR_PP1_INEN_Msk (0x20000UL) |
PORT P1_DIR: PP1_INEN (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP1_INEN_Pos (17UL) |
PORT P1_DIR: PP1_INEN (Bit 17)
#define PORT_P1_DIR_PP1_Msk (0x2UL) |
PORT P1_DIR: PP1 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP1_Pos (1UL) |
PORT P1_DIR: PP1 (Bit 1)
#define PORT_P1_DIR_PP2_INEN_Msk (0x40000UL) |
PORT P1_DIR: PP2_INEN (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP2_INEN_Pos (18UL) |
PORT P1_DIR: PP2_INEN (Bit 18)
#define PORT_P1_DIR_PP2_Msk (0x4UL) |
PORT P1_DIR: PP2 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP2_Pos (2UL) |
PORT P1_DIR: PP2 (Bit 2)
#define PORT_P1_DIR_PP4_INEN_Msk (0x100000UL) |
PORT P1_DIR: PP4_INEN (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP4_INEN_Pos (20UL) |
PORT P1_DIR: PP4_INEN (Bit 20)
#define PORT_P1_DIR_PP4_Msk (0x10UL) |
PORT P1_DIR: PP4 (Bitfield-Mask: 0x01)
#define PORT_P1_DIR_PP4_Pos (4UL) |
PORT P1_DIR: PP4 (Bit 4)
#define PORT_P1_OD_PP0_Msk (0x1UL) |
PORT P1_OD: PP0 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_PP0_Pos (0UL) |
PORT P1_OD: PP0 (Bit 0)
#define PORT_P1_OD_PP1_Msk (0x2UL) |
PORT P1_OD: PP1 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_PP1_Pos (1UL) |
PORT P1_OD: PP1 (Bit 1)
#define PORT_P1_OD_PP2_Msk (0x4UL) |
PORT P1_OD: PP2 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_PP2_Pos (2UL) |
PORT P1_OD: PP2 (Bit 2)
#define PORT_P1_OD_PP4_Msk (0x10UL) |
PORT P1_OD: PP4 (Bitfield-Mask: 0x01)
#define PORT_P1_OD_PP4_Pos (4UL) |
PORT P1_OD: PP4 (Bit 4)
#define PORT_P1_PUDEN_PP0_Msk (0x1UL) |
PORT P1_PUDEN: PP0 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_PP0_Pos (0UL) |
PORT P1_PUDEN: PP0 (Bit 0)
#define PORT_P1_PUDEN_PP1_Msk (0x2UL) |
PORT P1_PUDEN: PP1 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_PP1_Pos (1UL) |
PORT P1_PUDEN: PP1 (Bit 1)
#define PORT_P1_PUDEN_PP2_Msk (0x4UL) |
PORT P1_PUDEN: PP2 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_PP2_Pos (2UL) |
PORT P1_PUDEN: PP2 (Bit 2)
#define PORT_P1_PUDEN_PP4_Msk (0x10UL) |
PORT P1_PUDEN: PP4 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDEN_PP4_Pos (4UL) |
PORT P1_PUDEN: PP4 (Bit 4)
#define PORT_P1_PUDSEL_PP0_Msk (0x1UL) |
PORT P1_PUDSEL: PP0 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_PP0_Pos (0UL) |
PORT P1_PUDSEL: PP0 (Bit 0)
#define PORT_P1_PUDSEL_PP1_Msk (0x2UL) |
PORT P1_PUDSEL: PP1 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_PP1_Pos (1UL) |
PORT P1_PUDSEL: PP1 (Bit 1)
#define PORT_P1_PUDSEL_PP2_Msk (0x4UL) |
PORT P1_PUDSEL: PP2 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_PP2_Pos (2UL) |
PORT P1_PUDSEL: PP2 (Bit 2)
#define PORT_P1_PUDSEL_PP4_Msk (0x10UL) |
PORT P1_PUDSEL: PP4 (Bitfield-Mask: 0x01)
#define PORT_P1_PUDSEL_PP4_Pos (4UL) |
PORT P1_PUDSEL: PP4 (Bit 4)
#define PORT_P2_DATA_PP0_Msk (0x1UL) |
PORT P2_DATA: PP0 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_PP0_Pos (0UL) |
PORT P2_DATA: PP0 (Bit 0)
#define PORT_P2_DATA_PP1_Msk (0x2UL) |
PORT P2_DATA: PP1 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_PP1_Pos (1UL) |
PORT P2_DATA: PP1 (Bit 1)
#define PORT_P2_DATA_PP2_Msk (0x4UL) |
PORT P2_DATA: PP2 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_PP2_Pos (2UL) |
PORT P2_DATA: PP2 (Bit 2)
#define PORT_P2_DATA_PP3_Msk (0x8UL) |
PORT P2_DATA: PP3 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_PP3_Pos (3UL) |
PORT P2_DATA: PP3 (Bit 3)
#define PORT_P2_DATA_PP7_Msk (0x80UL) |
PORT P2_DATA: PP7 (Bitfield-Mask: 0x01)
#define PORT_P2_DATA_PP7_Pos (7UL) |
PORT P2_DATA: PP7 (Bit 7)
#define PORT_P2_DIR_PP0_Msk (0x1UL) |
PORT P2_DIR: PP0 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_PP0_Pos (0UL) |
PORT P2_DIR: PP0 (Bit 0)
#define PORT_P2_DIR_PP1_Msk (0x2UL) |
PORT P2_DIR: PP1 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_PP1_Pos (1UL) |
PORT P2_DIR: PP1 (Bit 1)
#define PORT_P2_DIR_PP2_Msk (0x4UL) |
PORT P2_DIR: PP2 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_PP2_Pos (2UL) |
PORT P2_DIR: PP2 (Bit 2)
#define PORT_P2_DIR_PP3_Msk (0x8UL) |
PORT P2_DIR: PP3 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_PP3_Pos (3UL) |
PORT P2_DIR: PP3 (Bit 3)
#define PORT_P2_DIR_PP7_Msk (0x80UL) |
PORT P2_DIR: PP7 (Bitfield-Mask: 0x01)
#define PORT_P2_DIR_PP7_Pos (7UL) |
PORT P2_DIR: PP7 (Bit 7)
#define PORT_P2_PUDEN_PP0_Msk (0x1UL) |
PORT P2_PUDEN: PP0 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_PP0_Pos (0UL) |
PORT P2_PUDEN: PP0 (Bit 0)
#define PORT_P2_PUDEN_PP1_Msk (0x2UL) |
PORT P2_PUDEN: PP1 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_PP1_Pos (1UL) |
PORT P2_PUDEN: PP1 (Bit 1)
#define PORT_P2_PUDEN_PP2_Msk (0x4UL) |
PORT P2_PUDEN: PP2 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_PP2_Pos (2UL) |
PORT P2_PUDEN: PP2 (Bit 2)
#define PORT_P2_PUDEN_PP3_Msk (0x8UL) |
PORT P2_PUDEN: PP3 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_PP3_Pos (3UL) |
PORT P2_PUDEN: PP3 (Bit 3)
#define PORT_P2_PUDEN_PP7_Msk (0x80UL) |
PORT P2_PUDEN: PP7 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDEN_PP7_Pos (7UL) |
PORT P2_PUDEN: PP7 (Bit 7)
#define PORT_P2_PUDSEL_PP0_Msk (0x1UL) |
PORT P2_PUDSEL: PP0 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_PP0_Pos (0UL) |
PORT P2_PUDSEL: PP0 (Bit 0)
#define PORT_P2_PUDSEL_PP1_Msk (0x2UL) |
PORT P2_PUDSEL: PP1 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_PP1_Pos (1UL) |
PORT P2_PUDSEL: PP1 (Bit 1)
#define PORT_P2_PUDSEL_PP2_Msk (0x4UL) |
PORT P2_PUDSEL: PP2 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_PP2_Pos (2UL) |
PORT P2_PUDSEL: PP2 (Bit 2)
#define PORT_P2_PUDSEL_PP3_Msk (0x8UL) |
PORT P2_PUDSEL: PP3 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_PP3_Pos (3UL) |
PORT P2_PUDSEL: PP3 (Bit 3)
#define PORT_P2_PUDSEL_PP7_Msk (0x80UL) |
PORT P2_PUDSEL: PP7 (Bitfield-Mask: 0x01)
#define PORT_P2_PUDSEL_PP7_Pos (7UL) |
PORT P2_PUDSEL: PP7 (Bit 7)
#define SCU_ADC1_CLK_ADC1_CLK_DIV_Msk (0xfUL) |
SCU ADC1_CLK: ADC1_CLK_DIV (Bitfield-Mask: 0x0f)
#define SCU_ADC1_CLK_ADC1_CLK_DIV_Pos (0UL) |
SCU ADC1_CLK: ADC1_CLK_DIV (Bit 0)
#define SCU_ADC1_CLK_DPP1_CLK_DIV_Msk (0x300UL) |
SCU ADC1_CLK: DPP1_CLK_DIV (Bitfield-Mask: 0x03)
#define SCU_ADC1_CLK_DPP1_CLK_DIV_Pos (8UL) |
SCU ADC1_CLK: DPP1_CLK_DIV (Bit 8)
#define SCU_APCLK_APCLK1FAC_Msk (0x3UL) |
SCU APCLK: APCLK1FAC (Bitfield-Mask: 0x03)
#define SCU_APCLK_APCLK1FAC_Pos (0UL) |
SCU APCLK: APCLK1FAC (Bit 0)
#define SCU_APCLK_APCLK2FAC_Msk (0x1f00UL) |
SCU APCLK: APCLK2FAC (Bitfield-Mask: 0x1f)
#define SCU_APCLK_APCLK2FAC_Pos (8UL) |
SCU APCLK: APCLK2FAC (Bit 8)
#define SCU_APCLK_BGCLK_DIV_Msk (0x2000000UL) |
SCU APCLK: BGCLK_DIV (Bitfield-Mask: 0x01)
#define SCU_APCLK_BGCLK_DIV_Pos (25UL) |
SCU APCLK: BGCLK_DIV (Bit 25)
#define SCU_APCLK_BGCLK_SEL_Msk (0x1000000UL) |
SCU APCLK: BGCLK_SEL (Bitfield-Mask: 0x01)
#define SCU_APCLK_BGCLK_SEL_Pos (24UL) |
SCU APCLK: BGCLK_SEL (Bit 24)
#define SCU_APCLK_CPCLK_DIV_Msk (0x20000000UL) |
SCU APCLK: CPCLK_DIV (Bitfield-Mask: 0x01)
#define SCU_APCLK_CPCLK_DIV_Pos (29UL) |
SCU APCLK: CPCLK_DIV (Bit 29)
#define SCU_APCLK_CPCLK_SEL_Msk (0x10000000UL) |
SCU APCLK: CPCLK_SEL (Bitfield-Mask: 0x01)
#define SCU_APCLK_CPCLK_SEL_Pos (28UL) |
SCU APCLK: CPCLK_SEL (Bit 28)
#define SCU_APCLK_CTRL_APCLK_SET_Msk (0x1UL) |
SCU APCLK_CTRL: APCLK_SET (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL_APCLK_SET_Pos (0UL) |
SCU APCLK_CTRL: APCLK_SET (Bit 0)
#define SCU_APCLK_CTRL_CLKWDT_IE_Msk (0x100UL) |
SCU APCLK_CTRL: CLKWDT_IE (Bitfield-Mask: 0x01)
#define SCU_APCLK_CTRL_CLKWDT_IE_Pos (8UL) |
SCU APCLK_CTRL: CLKWDT_IE (Bit 8)
#define SCU_APCLK_SCLR_APCLK1SCLR_Msk (0x1UL) |
SCU APCLK_SCLR: APCLK1SCLR (Bitfield-Mask: 0x01)
#define SCU_APCLK_SCLR_APCLK1SCLR_Pos (0UL) |
SCU APCLK_SCLR: APCLK1SCLR (Bit 0)
#define SCU_APCLK_SCLR_APCLK2SCLR_Msk (0x100UL) |
SCU APCLK_SCLR: APCLK2SCLR (Bitfield-Mask: 0x01)
#define SCU_APCLK_SCLR_APCLK2SCLR_Pos (8UL) |
SCU APCLK_SCLR: APCLK2SCLR (Bit 8)
#define SCU_APCLK_SCLR_APCLK3SCLR_Msk (0x10000UL) |
SCU APCLK_SCLR: APCLK3SCLR (Bitfield-Mask: 0x01)
#define SCU_APCLK_SCLR_APCLK3SCLR_Pos (16UL) |
SCU APCLK_SCLR: APCLK3SCLR (Bit 16)
#define SCU_APCLK_STS_APCLK1STS_Msk (0x3UL) |
SCU APCLK_STS: APCLK1STS (Bitfield-Mask: 0x03)
#define SCU_APCLK_STS_APCLK1STS_Pos (0UL) |
SCU APCLK_STS: APCLK1STS (Bit 0)
#define SCU_APCLK_STS_APCLK2STS_Msk (0x300UL) |
SCU APCLK_STS: APCLK2STS (Bitfield-Mask: 0x03)
#define SCU_APCLK_STS_APCLK2STS_Pos (8UL) |
SCU APCLK_STS: APCLK2STS (Bit 8)
#define SCU_APCLK_STS_APCLK3STS_Msk (0x10000UL) |
SCU APCLK_STS: APCLK3STS (Bitfield-Mask: 0x01)
#define SCU_APCLK_STS_APCLK3STS_Pos (16UL) |
SCU APCLK_STS: APCLK3STS (Bit 16)
#define SCU_APCLK_STS_APCLK_ERR_STS_Msk (0x10UL) |
SCU APCLK_STS: APCLK_ERR_STS (Bitfield-Mask: 0x01)
#define SCU_APCLK_STS_APCLK_ERR_STS_Pos (4UL) |
SCU APCLK_STS: APCLK_ERR_STS (Bit 4)
#define SCU_APCLK_STS_BRDRV_CLK_ERR_STS_Msk (0x100000UL) |
SCU APCLK_STS: BRDRV_CLK_ERR_STS (Bitfield-Mask: 0x01)
#define SCU_APCLK_STS_BRDRV_CLK_ERR_STS_Pos (20UL) |
SCU APCLK_STS: BRDRV_CLK_ERR_STS (Bit 20)
#define SCU_BCON1_BR1_PRE_Msk (0xeUL) |
SCU BCON1: BR1_PRE (Bitfield-Mask: 0x07)
#define SCU_BCON1_BR1_PRE_Pos (1UL) |
SCU BCON1: BR1_PRE (Bit 1)
#define SCU_BCON1_BR1_R_Msk (0x1UL) |
SCU BCON1: BR1_R (Bitfield-Mask: 0x01)
#define SCU_BCON1_BR1_R_Pos (0UL) |
SCU BCON1: BR1_R (Bit 0)
#define SCU_BCON2_BR2_PRE_Msk (0xeUL) |
SCU BCON2: BR2_PRE (Bitfield-Mask: 0x07)
#define SCU_BCON2_BR2_PRE_Pos (1UL) |
SCU BCON2: BR2_PRE (Bit 1)
#define SCU_BCON2_BR2_R_Msk (0x1UL) |
SCU BCON2: BR2_R (Bitfield-Mask: 0x01)
#define SCU_BCON2_BR2_R_Pos (0UL) |
SCU BCON2: BR2_R (Bit 0)
#define SCU_BG1_BG1_BR_VALUE_Msk (0x7ffUL) |
SCU BG1: BG1_BR_VALUE (Bitfield-Mask: 0x7ff)
#define SCU_BG1_BG1_BR_VALUE_Pos (0UL) |
SCU BG1: BG1_BR_VALUE (Bit 0)
#define SCU_BG1_BG1_TIM_VALUE_Msk (0x7ff0000UL) |
SCU BG1: BG1_TIM_VALUE (Bitfield-Mask: 0x7ff)
#define SCU_BG1_BG1_TIM_VALUE_Pos (16UL) |
SCU BG1: BG1_TIM_VALUE (Bit 16)
#define SCU_BG2_BG2_BR_VALUE_Msk (0x7ffUL) |
SCU BG2: BG2_BR_VALUE (Bitfield-Mask: 0x7ff)
#define SCU_BG2_BG2_BR_VALUE_Pos (0UL) |
SCU BG2: BG2_BR_VALUE (Bit 0)
#define SCU_BG2_BG2_TIM_VALUE_Msk (0x7ff0000UL) |
SCU BG2: BG2_TIM_VALUE (Bitfield-Mask: 0x7ff)
#define SCU_BG2_BG2_TIM_VALUE_Pos (16UL) |
SCU BG2: BG2_TIM_VALUE (Bit 16)
#define SCU_BGL1_BG1_FD_SEL_Msk (0x1fUL) |
SCU BGL1: BG1_FD_SEL (Bitfield-Mask: 0x1f)
#define SCU_BGL1_BG1_FD_SEL_Pos (0UL) |
SCU BGL1: BG1_FD_SEL (Bit 0)
#define SCU_BGL2_BG2_FD_SEL_Msk (0x1fUL) |
SCU BGL2: BG2_FD_SEL (Bitfield-Mask: 0x1f)
#define SCU_BGL2_BG2_FD_SEL_Pos (0UL) |
SCU BGL2: BG2_FD_SEL (Bit 0)
#define SCU_BRDRV_CLK_BRDRV_CLK_DIV_Msk (0x3UL) |
SCU BRDRV_CLK: BRDRV_CLK_DIV (Bitfield-Mask: 0x03)
#define SCU_BRDRV_CLK_BRDRV_CLK_DIV_Pos (0UL) |
SCU BRDRV_CLK: BRDRV_CLK_DIV (Bit 0)
#define SCU_BRDRV_CLK_BRDRV_TFILT_DIV_Msk (0x1f00UL) |
SCU BRDRV_CLK: BRDRV_TFILT_DIV (Bitfield-Mask: 0x1f)
#define SCU_BRDRV_CLK_BRDRV_TFILT_DIV_Pos (8UL) |
SCU BRDRV_CLK: BRDRV_TFILT_DIV (Bit 8)
#define SCU_CMCON2_PBA0CLKREL_Msk (0x1UL) |
SCU CMCON2: PBA0CLKREL (Bitfield-Mask: 0x01)
#define SCU_CMCON2_PBA0CLKREL_Pos (0UL) |
SCU CMCON2: PBA0CLKREL (Bit 0)
#define SCU_COCON_COREL_Msk (0xfUL) |
SCU COCON: COREL (Bitfield-Mask: 0x0f)
#define SCU_COCON_COREL_Pos (0UL) |
SCU COCON: COREL (Bit 0)
#define SCU_COCON_COUTS0_Msk (0x10UL) |
SCU COCON: COUTS0 (Bitfield-Mask: 0x01)
#define SCU_COCON_COUTS0_Pos (4UL) |
SCU COCON: COUTS0 (Bit 4)
#define SCU_COCON_COUTS1_Msk (0x40UL) |
SCU COCON: COUTS1 (Bitfield-Mask: 0x01)
#define SCU_COCON_COUTS1_Pos (6UL) |
SCU COCON: COUTS1 (Bit 6)
#define SCU_COCON_EN_Msk (0x80UL) |
SCU COCON: EN (Bitfield-Mask: 0x01)
#define SCU_COCON_EN_Pos (7UL) |
SCU COCON: EN (Bit 7)
#define SCU_COCON_TLEN_Msk (0x20UL) |
SCU COCON: TLEN (Bitfield-Mask: 0x01)
#define SCU_COCON_TLEN_Pos (5UL) |
SCU COCON: TLEN (Bit 5)
#define SCU_EDCCON_NVMIE_Msk (0x4UL) |
SCU EDCCON: NVMIE (Bitfield-Mask: 0x01)
#define SCU_EDCCON_NVMIE_Pos (2UL) |
SCU EDCCON: NVMIE (Bit 2)
#define SCU_EDCCON_RIE_Msk (0x1UL) |
SCU EDCCON: RIE (Bitfield-Mask: 0x01)
#define SCU_EDCCON_RIE_Pos (0UL) |
SCU EDCCON: RIE (Bit 0)
#define SCU_EDCSCLR_NVMDBEC_Msk (0x4UL) |
SCU EDCSCLR: NVMDBEC (Bitfield-Mask: 0x01)
#define SCU_EDCSCLR_NVMDBEC_Pos (2UL) |
SCU EDCSCLR: NVMDBEC (Bit 2)
#define SCU_EDCSCLR_RDBEC_Msk (0x1UL) |
SCU EDCSCLR: RDBEC (Bitfield-Mask: 0x01)
#define SCU_EDCSCLR_RDBEC_Pos (0UL) |
SCU EDCSCLR: RDBEC (Bit 0)
#define SCU_EDCSCLR_RSBEC_Msk (0x10UL) |
SCU EDCSCLR: RSBEC (Bitfield-Mask: 0x01)
#define SCU_EDCSCLR_RSBEC_Pos (4UL) |
SCU EDCSCLR: RSBEC (Bit 4)
#define SCU_EDCSTAT_NVMDBE_Msk (0x4UL) |
SCU EDCSTAT: NVMDBE (Bitfield-Mask: 0x01)
#define SCU_EDCSTAT_NVMDBE_Pos (2UL) |
SCU EDCSTAT: NVMDBE (Bit 2)
#define SCU_EDCSTAT_RDBE_Msk (0x1UL) |
SCU EDCSTAT: RDBE (Bitfield-Mask: 0x01)
#define SCU_EDCSTAT_RDBE_Pos (0UL) |
SCU EDCSTAT: RDBE (Bit 0)
#define SCU_EDCSTAT_RSBE_Msk (0x10UL) |
SCU EDCSTAT: RSBE (Bitfield-Mask: 0x01)
#define SCU_EDCSTAT_RSBE_Pos (4UL) |
SCU EDCSTAT: RSBE (Bit 4)
#define SCU_EXICON0_EXINT0_Msk (0x3UL) |
SCU EXICON0: EXINT0 (Bitfield-Mask: 0x03)
#define SCU_EXICON0_EXINT0_Pos (0UL) |
SCU EXICON0: EXINT0 (Bit 0)
#define SCU_EXICON0_EXINT1_Msk (0xcUL) |
SCU EXICON0: EXINT1 (Bitfield-Mask: 0x03)
#define SCU_EXICON0_EXINT1_Pos (2UL) |
SCU EXICON0: EXINT1 (Bit 2)
#define SCU_EXICON0_EXINT2_Msk (0x30UL) |
SCU EXICON0: EXINT2 (Bitfield-Mask: 0x03)
#define SCU_EXICON0_EXINT2_Pos (4UL) |
SCU EXICON0: EXINT2 (Bit 4)
#define SCU_EXICON1_MON1_Msk (0x3UL) |
SCU EXICON1: MON1 (Bitfield-Mask: 0x03)
#define SCU_EXICON1_MON1_Pos (0UL) |
SCU EXICON1: MON1 (Bit 0)
#define SCU_EXICON1_MON2_Msk (0xcUL) |
SCU EXICON1: MON2 (Bitfield-Mask: 0x03)
#define SCU_EXICON1_MON2_Pos (2UL) |
SCU EXICON1: MON2 (Bit 2)
#define SCU_EXICON1_MON3_Msk (0x30UL) |
SCU EXICON1: MON3 (Bitfield-Mask: 0x03)
#define SCU_EXICON1_MON3_Pos (4UL) |
SCU EXICON1: MON3 (Bit 4)
#define SCU_EXICON1_MON4_Msk (0xc0UL) |
SCU EXICON1: MON4 (Bitfield-Mask: 0x03)
#define SCU_EXICON1_MON4_Pos (6UL) |
SCU EXICON1: MON4 (Bit 6)
#define SCU_GPT12ICLR_GPT12CRC_Msk (0x20UL) |
SCU GPT12ICLR: GPT12CRC (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_GPT12CRC_Pos (5UL) |
SCU GPT12ICLR: GPT12CRC (Bit 5)
#define SCU_GPT12ICLR_GPT1T2C_Msk (0x1UL) |
SCU GPT12ICLR: GPT1T2C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_GPT1T2C_Pos (0UL) |
SCU GPT12ICLR: GPT1T2C (Bit 0)
#define SCU_GPT12ICLR_GPT1T3C_Msk (0x2UL) |
SCU GPT12ICLR: GPT1T3C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_GPT1T3C_Pos (1UL) |
SCU GPT12ICLR: GPT1T3C (Bit 1)
#define SCU_GPT12ICLR_GPT1T4C_Msk (0x4UL) |
SCU GPT12ICLR: GPT1T4C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_GPT1T4C_Pos (2UL) |
SCU GPT12ICLR: GPT1T4C (Bit 2)
#define SCU_GPT12ICLR_GPT2T5C_Msk (0x8UL) |
SCU GPT12ICLR: GPT2T5C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_GPT2T5C_Pos (3UL) |
SCU GPT12ICLR: GPT2T5C (Bit 3)
#define SCU_GPT12ICLR_GPT2T6C_Msk (0x10UL) |
SCU GPT12ICLR: GPT2T6C (Bitfield-Mask: 0x01)
#define SCU_GPT12ICLR_GPT2T6C_Pos (4UL) |
SCU GPT12ICLR: GPT2T6C (Bit 4)
#define SCU_GPT12IEN_CRIE_Msk (0x20UL) |
SCU GPT12IEN: CRIE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_CRIE_Pos (5UL) |
SCU GPT12IEN: CRIE (Bit 5)
#define SCU_GPT12IEN_T2IE_Msk (0x1UL) |
SCU GPT12IEN: T2IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T2IE_Pos (0UL) |
SCU GPT12IEN: T2IE (Bit 0)
#define SCU_GPT12IEN_T3IE_Msk (0x2UL) |
SCU GPT12IEN: T3IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T3IE_Pos (1UL) |
SCU GPT12IEN: T3IE (Bit 1)
#define SCU_GPT12IEN_T4IE_Msk (0x4UL) |
SCU GPT12IEN: T4IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T4IE_Pos (2UL) |
SCU GPT12IEN: T4IE (Bit 2)
#define SCU_GPT12IEN_T5IE_Msk (0x8UL) |
SCU GPT12IEN: T5IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T5IE_Pos (3UL) |
SCU GPT12IEN: T5IE (Bit 3)
#define SCU_GPT12IEN_T6IE_Msk (0x10UL) |
SCU GPT12IEN: T6IE (Bitfield-Mask: 0x01)
#define SCU_GPT12IEN_T6IE_Pos (4UL) |
SCU GPT12IEN: T6IE (Bit 4)
#define SCU_GPT12IRC_GPT12CR_Msk (0x20UL) |
SCU GPT12IRC: GPT12CR (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_GPT12CR_Pos (5UL) |
SCU GPT12IRC: GPT12CR (Bit 5)
#define SCU_GPT12IRC_GPT1T2_Msk (0x1UL) |
SCU GPT12IRC: GPT1T2 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_GPT1T2_Pos (0UL) |
SCU GPT12IRC: GPT1T2 (Bit 0)
#define SCU_GPT12IRC_GPT1T3_Msk (0x2UL) |
SCU GPT12IRC: GPT1T3 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_GPT1T3_Pos (1UL) |
SCU GPT12IRC: GPT1T3 (Bit 1)
#define SCU_GPT12IRC_GPT1T4_Msk (0x4UL) |
SCU GPT12IRC: GPT1T4 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_GPT1T4_Pos (2UL) |
SCU GPT12IRC: GPT1T4 (Bit 2)
#define SCU_GPT12IRC_GPT2T5_Msk (0x8UL) |
SCU GPT12IRC: GPT2T5 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_GPT2T5_Pos (3UL) |
SCU GPT12IRC: GPT2T5 (Bit 3)
#define SCU_GPT12IRC_GPT2T6_Msk (0x10UL) |
SCU GPT12IRC: GPT2T6 (Bitfield-Mask: 0x01)
#define SCU_GPT12IRC_GPT2T6_Pos (4UL) |
SCU GPT12IRC: GPT2T6 (Bit 4)
#define SCU_GPT12PISEL_GPT12_Msk (0xfUL) |
SCU GPT12PISEL: GPT12 (Bitfield-Mask: 0x0f)
#define SCU_GPT12PISEL_GPT12_Pos (0UL) |
SCU GPT12PISEL: GPT12 (Bit 0)
#define SCU_GPT12PISEL_GPT12_SEL_Msk (0x20UL) |
SCU GPT12PISEL: GPT12_SEL (Bitfield-Mask: 0x01)
#define SCU_GPT12PISEL_GPT12_SEL_Pos (5UL) |
SCU GPT12PISEL: GPT12_SEL (Bit 5)
#define SCU_GPT12PISEL_TRIG_CONF_Msk (0x10UL) |
SCU GPT12PISEL: TRIG_CONF (Bitfield-Mask: 0x01)
#define SCU_GPT12PISEL_TRIG_CONF_Pos (4UL) |
SCU GPT12PISEL: TRIG_CONF (Bit 4)
#define SCU_ID_PRODID_Msk (0xf8UL) |
SCU ID: PRODID (Bitfield-Mask: 0x1f)
#define SCU_ID_PRODID_Pos (3UL) |
SCU ID: PRODID (Bit 3)
#define SCU_ID_VERID_Msk (0x7UL) |
SCU ID: VERID (Bitfield-Mask: 0x07)
#define SCU_ID_VERID_Pos (0UL) |
SCU ID: VERID (Bit 0)
#define SCU_IEN0_EA_Msk (0x80000000UL) |
SCU IEN0: EA (Bitfield-Mask: 0x01)
#define SCU_IEN0_EA_Pos (31UL) |
SCU IEN0: EA (Bit 31)
#define SCU_IRCON0_EXINT0F_Msk (0x2UL) |
SCU IRCON0: EXINT0F (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT0F_Pos (1UL) |
SCU IRCON0: EXINT0F (Bit 1)
#define SCU_IRCON0_EXINT0R_Msk (0x1UL) |
SCU IRCON0: EXINT0R (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT0R_Pos (0UL) |
SCU IRCON0: EXINT0R (Bit 0)
#define SCU_IRCON0_EXINT1F_Msk (0x8UL) |
SCU IRCON0: EXINT1F (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT1F_Pos (3UL) |
SCU IRCON0: EXINT1F (Bit 3)
#define SCU_IRCON0_EXINT1R_Msk (0x4UL) |
SCU IRCON0: EXINT1R (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT1R_Pos (2UL) |
SCU IRCON0: EXINT1R (Bit 2)
#define SCU_IRCON0_EXINT2F_Msk (0x20UL) |
SCU IRCON0: EXINT2F (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT2F_Pos (5UL) |
SCU IRCON0: EXINT2F (Bit 5)
#define SCU_IRCON0_EXINT2R_Msk (0x10UL) |
SCU IRCON0: EXINT2R (Bitfield-Mask: 0x01)
#define SCU_IRCON0_EXINT2R_Pos (4UL) |
SCU IRCON0: EXINT2R (Bit 4)
#define SCU_IRCON0CLR_EXINT0FC_Msk (0x2UL) |
SCU IRCON0CLR: EXINT0FC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT0FC_Pos (1UL) |
SCU IRCON0CLR: EXINT0FC (Bit 1)
#define SCU_IRCON0CLR_EXINT0RC_Msk (0x1UL) |
SCU IRCON0CLR: EXINT0RC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT0RC_Pos (0UL) |
SCU IRCON0CLR: EXINT0RC (Bit 0)
#define SCU_IRCON0CLR_EXINT1FC_Msk (0x8UL) |
SCU IRCON0CLR: EXINT1FC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT1FC_Pos (3UL) |
SCU IRCON0CLR: EXINT1FC (Bit 3)
#define SCU_IRCON0CLR_EXINT1RC_Msk (0x4UL) |
SCU IRCON0CLR: EXINT1RC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT1RC_Pos (2UL) |
SCU IRCON0CLR: EXINT1RC (Bit 2)
#define SCU_IRCON0CLR_EXINT2FC_Msk (0x20UL) |
SCU IRCON0CLR: EXINT2FC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT2FC_Pos (5UL) |
SCU IRCON0CLR: EXINT2FC (Bit 5)
#define SCU_IRCON0CLR_EXINT2RC_Msk (0x10UL) |
SCU IRCON0CLR: EXINT2RC (Bitfield-Mask: 0x01)
#define SCU_IRCON0CLR_EXINT2RC_Pos (4UL) |
SCU IRCON0CLR: EXINT2RC (Bit 4)
#define SCU_IRCON1_MON1F_Msk (0x2UL) |
SCU IRCON1: MON1F (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON1F_Pos (1UL) |
SCU IRCON1: MON1F (Bit 1)
#define SCU_IRCON1_MON1R_Msk (0x1UL) |
SCU IRCON1: MON1R (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON1R_Pos (0UL) |
SCU IRCON1: MON1R (Bit 0)
#define SCU_IRCON1_MON2F_Msk (0x8UL) |
SCU IRCON1: MON2F (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON2F_Pos (3UL) |
SCU IRCON1: MON2F (Bit 3)
#define SCU_IRCON1_MON2R_Msk (0x4UL) |
SCU IRCON1: MON2R (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON2R_Pos (2UL) |
SCU IRCON1: MON2R (Bit 2)
#define SCU_IRCON1_MON3F_Msk (0x20UL) |
SCU IRCON1: MON3F (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON3F_Pos (5UL) |
SCU IRCON1: MON3F (Bit 5)
#define SCU_IRCON1_MON3R_Msk (0x10UL) |
SCU IRCON1: MON3R (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON3R_Pos (4UL) |
SCU IRCON1: MON3R (Bit 4)
#define SCU_IRCON1_MON4F_Msk (0x80UL) |
SCU IRCON1: MON4F (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON4F_Pos (7UL) |
SCU IRCON1: MON4F (Bit 7)
#define SCU_IRCON1_MON4R_Msk (0x40UL) |
SCU IRCON1: MON4R (Bitfield-Mask: 0x01)
#define SCU_IRCON1_MON4R_Pos (6UL) |
SCU IRCON1: MON4R (Bit 6)
#define SCU_IRCON1CLR_MON1FC_Msk (0x2UL) |
SCU IRCON1CLR: MON1FC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON1FC_Pos (1UL) |
SCU IRCON1CLR: MON1FC (Bit 1)
#define SCU_IRCON1CLR_MON1RC_Msk (0x1UL) |
SCU IRCON1CLR: MON1RC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON1RC_Pos (0UL) |
SCU IRCON1CLR: MON1RC (Bit 0)
#define SCU_IRCON1CLR_MON2FC_Msk (0x8UL) |
SCU IRCON1CLR: MON2FC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON2FC_Pos (3UL) |
SCU IRCON1CLR: MON2FC (Bit 3)
#define SCU_IRCON1CLR_MON2RC_Msk (0x4UL) |
SCU IRCON1CLR: MON2RC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON2RC_Pos (2UL) |
SCU IRCON1CLR: MON2RC (Bit 2)
#define SCU_IRCON1CLR_MON3FC_Msk (0x20UL) |
SCU IRCON1CLR: MON3FC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON3FC_Pos (5UL) |
SCU IRCON1CLR: MON3FC (Bit 5)
#define SCU_IRCON1CLR_MON3RC_Msk (0x10UL) |
SCU IRCON1CLR: MON3RC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON3RC_Pos (4UL) |
SCU IRCON1CLR: MON3RC (Bit 4)
#define SCU_IRCON1CLR_MON4FC_Msk (0x80UL) |
SCU IRCON1CLR: MON4FC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON4FC_Pos (7UL) |
SCU IRCON1CLR: MON4FC (Bit 7)
#define SCU_IRCON1CLR_MON4RC_Msk (0x40UL) |
SCU IRCON1CLR: MON4RC (Bitfield-Mask: 0x01)
#define SCU_IRCON1CLR_MON4RC_Pos (6UL) |
SCU IRCON1CLR: MON4RC (Bit 6)
#define SCU_IRCON2_EIR1_Msk (0x1UL) |
SCU IRCON2: EIR1 (Bitfield-Mask: 0x01)
#define SCU_IRCON2_EIR1_Pos (0UL) |
SCU IRCON2: EIR1 (Bit 0)
#define SCU_IRCON2_RIR1_Msk (0x4UL) |
SCU IRCON2: RIR1 (Bitfield-Mask: 0x01)
#define SCU_IRCON2_RIR1_Pos (2UL) |
SCU IRCON2: RIR1 (Bit 2)
#define SCU_IRCON2_TIR1_Msk (0x2UL) |
SCU IRCON2: TIR1 (Bitfield-Mask: 0x01)
#define SCU_IRCON2_TIR1_Pos (1UL) |
SCU IRCON2: TIR1 (Bit 1)
#define SCU_IRCON2CLR_EIR1C_Msk (0x1UL) |
SCU IRCON2CLR: EIR1C (Bitfield-Mask: 0x01)
#define SCU_IRCON2CLR_EIR1C_Pos (0UL) |
SCU IRCON2CLR: EIR1C (Bit 0)
#define SCU_IRCON2CLR_RIR1C_Msk (0x4UL) |
SCU IRCON2CLR: RIR1C (Bitfield-Mask: 0x01)
#define SCU_IRCON2CLR_RIR1C_Pos (2UL) |
SCU IRCON2CLR: RIR1C (Bit 2)
#define SCU_IRCON2CLR_TIR1C_Msk (0x2UL) |
SCU IRCON2CLR: TIR1C (Bitfield-Mask: 0x01)
#define SCU_IRCON2CLR_TIR1C_Pos (1UL) |
SCU IRCON2CLR: TIR1C (Bit 1)
#define SCU_IRCON3_EIR2_Msk (0x1UL) |
SCU IRCON3: EIR2 (Bitfield-Mask: 0x01)
#define SCU_IRCON3_EIR2_Pos (0UL) |
SCU IRCON3: EIR2 (Bit 0)
#define SCU_IRCON3_RIR2_Msk (0x4UL) |
SCU IRCON3: RIR2 (Bitfield-Mask: 0x01)
#define SCU_IRCON3_RIR2_Pos (2UL) |
SCU IRCON3: RIR2 (Bit 2)
#define SCU_IRCON3_TIR2_Msk (0x2UL) |
SCU IRCON3: TIR2 (Bitfield-Mask: 0x01)
#define SCU_IRCON3_TIR2_Pos (1UL) |
SCU IRCON3: TIR2 (Bit 1)
#define SCU_IRCON3CLR_EIR2C_Msk (0x1UL) |
SCU IRCON3CLR: EIR2C (Bitfield-Mask: 0x01)
#define SCU_IRCON3CLR_EIR2C_Pos (0UL) |
SCU IRCON3CLR: EIR2C (Bit 0)
#define SCU_IRCON3CLR_RIR2C_Msk (0x4UL) |
SCU IRCON3CLR: RIR2C (Bitfield-Mask: 0x01)
#define SCU_IRCON3CLR_RIR2C_Pos (2UL) |
SCU IRCON3CLR: RIR2C (Bit 2)
#define SCU_IRCON3CLR_TIR2C_Msk (0x2UL) |
SCU IRCON3CLR: TIR2C (Bitfield-Mask: 0x01)
#define SCU_IRCON3CLR_TIR2C_Pos (1UL) |
SCU IRCON3CLR: TIR2C (Bit 1)
#define SCU_IRCON4_CCU6SR0_Msk (0x1UL) |
SCU IRCON4: CCU6SR0 (Bitfield-Mask: 0x01)
#define SCU_IRCON4_CCU6SR0_Pos (0UL) |
SCU IRCON4: CCU6SR0 (Bit 0)
#define SCU_IRCON4_CCU6SR1_Msk (0x10UL) |
SCU IRCON4: CCU6SR1 (Bitfield-Mask: 0x01)
#define SCU_IRCON4_CCU6SR1_Pos (4UL) |
SCU IRCON4: CCU6SR1 (Bit 4)
#define SCU_IRCON4_CCU6SR2_Msk (0x10000UL) |
SCU IRCON4: CCU6SR2 (Bitfield-Mask: 0x01)
#define SCU_IRCON4_CCU6SR2_Pos (16UL) |
SCU IRCON4: CCU6SR2 (Bit 16)
#define SCU_IRCON4_CCU6SR3_Msk (0x100000UL) |
SCU IRCON4: CCU6SR3 (Bitfield-Mask: 0x01)
#define SCU_IRCON4_CCU6SR3_Pos (20UL) |
SCU IRCON4: CCU6SR3 (Bit 20)
#define SCU_IRCON4CLR_CCU6SR0C_Msk (0x1UL) |
SCU IRCON4CLR: CCU6SR0C (Bitfield-Mask: 0x01)
#define SCU_IRCON4CLR_CCU6SR0C_Pos (0UL) |
SCU IRCON4CLR: CCU6SR0C (Bit 0)
#define SCU_IRCON4CLR_CCU6SR1C_Msk (0x10UL) |
SCU IRCON4CLR: CCU6SR1C (Bitfield-Mask: 0x01)
#define SCU_IRCON4CLR_CCU6SR1C_Pos (4UL) |
SCU IRCON4CLR: CCU6SR1C (Bit 4)
#define SCU_IRCON4CLR_CCU6SR2C_Msk (0x10000UL) |
SCU IRCON4CLR: CCU6SR2C (Bitfield-Mask: 0x01)
#define SCU_IRCON4CLR_CCU6SR2C_Pos (16UL) |
SCU IRCON4CLR: CCU6SR2C (Bit 16)
#define SCU_IRCON4CLR_CCU6SR3C_Msk (0x100000UL) |
SCU IRCON4CLR: CCU6SR3C (Bitfield-Mask: 0x01)
#define SCU_IRCON4CLR_CCU6SR3C_Pos (20UL) |
SCU IRCON4CLR: CCU6SR3C (Bit 20)
#define SCU_IRCON5_WAKEUP_Msk (0x1UL) |
SCU IRCON5: WAKEUP (Bitfield-Mask: 0x01)
#define SCU_IRCON5_WAKEUP_Pos (0UL) |
SCU IRCON5: WAKEUP (Bit 0)
#define SCU_IRCON5CLR_WAKEUPC_Msk (0x1UL) |
SCU IRCON5CLR: WAKEUPC (Bitfield-Mask: 0x01)
#define SCU_IRCON5CLR_WAKEUPC_Pos (0UL) |
SCU IRCON5CLR: WAKEUPC (Bit 0)
#define SCU_LINSCLR_BRKC_Msk (0x8UL) |
SCU LINSCLR: BRKC (Bitfield-Mask: 0x01)
#define SCU_LINSCLR_BRKC_Pos (3UL) |
SCU LINSCLR: BRKC (Bit 3)
#define SCU_LINSCLR_EOFSYNC_Msk (0x10UL) |
SCU LINSCLR: EOFSYNC (Bitfield-Mask: 0x01)
#define SCU_LINSCLR_EOFSYNC_Pos (4UL) |
SCU LINSCLR: EOFSYNC (Bit 4)
#define SCU_LINSCLR_ERRSYNC_Msk (0x20UL) |
SCU LINSCLR: ERRSYNC (Bitfield-Mask: 0x01)
#define SCU_LINSCLR_ERRSYNC_Pos (5UL) |
SCU LINSCLR: ERRSYNC (Bit 5)
#define SCU_LINST_BGSEL_Msk (0x6UL) |
SCU LINST: BGSEL (Bitfield-Mask: 0x03)
#define SCU_LINST_BGSEL_Pos (1UL) |
SCU LINST: BGSEL (Bit 1)
#define SCU_LINST_BRDIS_Msk (0x1UL) |
SCU LINST: BRDIS (Bitfield-Mask: 0x01)
#define SCU_LINST_BRDIS_Pos (0UL) |
SCU LINST: BRDIS (Bit 0)
#define SCU_LINST_BRK_Msk (0x8UL) |
SCU LINST: BRK (Bitfield-Mask: 0x01)
#define SCU_LINST_BRK_Pos (3UL) |
SCU LINST: BRK (Bit 3)
#define SCU_LINST_EOFSYN_Msk (0x10UL) |
SCU LINST: EOFSYN (Bitfield-Mask: 0x01)
#define SCU_LINST_EOFSYN_Pos (4UL) |
SCU LINST: EOFSYN (Bit 4)
#define SCU_LINST_ERRSYN_Msk (0x20UL) |
SCU LINST: ERRSYN (Bitfield-Mask: 0x01)
#define SCU_LINST_ERRSYN_Pos (5UL) |
SCU LINST: ERRSYN (Bit 5)
#define SCU_LINST_SYNEN_Msk (0x40UL) |
SCU LINST: SYNEN (Bitfield-Mask: 0x01)
#define SCU_LINST_SYNEN_Pos (6UL) |
SCU LINST: SYNEN (Bit 6)
#define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Msk (0x2UL) |
SCU MEM_ACC_STS: NVM_ADDR_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Pos (1UL) |
SCU MEM_ACC_STS: NVM_ADDR_ERR (Bit 1)
#define SCU_MEM_ACC_STS_NVM_PROT_ERR_Msk (0x1UL) |
SCU MEM_ACC_STS: NVM_PROT_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_PROT_ERR_Pos (0UL) |
SCU MEM_ACC_STS: NVM_PROT_ERR (Bit 0)
#define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Msk (0x8UL) |
SCU MEM_ACC_STS: NVM_SFR_ADDR_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Pos (3UL) |
SCU MEM_ACC_STS: NVM_SFR_ADDR_ERR (Bit 3)
#define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Msk (0x4UL) |
SCU MEM_ACC_STS: NVM_SFR_PROT_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Pos (2UL) |
SCU MEM_ACC_STS: NVM_SFR_PROT_ERR (Bit 2)
#define SCU_MEM_ACC_STS_ROM_PROT_ERR_Msk (0x10UL) |
SCU MEM_ACC_STS: ROM_PROT_ERR (Bitfield-Mask: 0x01)
#define SCU_MEM_ACC_STS_ROM_PROT_ERR_Pos (4UL) |
SCU MEM_ACC_STS: ROM_PROT_ERR (Bit 4)
#define SCU_MEMSTAT_NVM_DATA_MODE_Msk (0x40000UL) |
SCU MEMSTAT: NVM_DATA_MODE (Bitfield-Mask: 0x01)
#define SCU_MEMSTAT_NVM_DATA_MODE_Pos (18UL) |
SCU MEMSTAT: NVM_DATA_MODE (Bit 18)
#define SCU_MEMSTAT_NVM_VAL_KEYS_Msk (0x30000UL) |
SCU MEMSTAT: NVM_VAL_KEYS (Bitfield-Mask: 0x03)
#define SCU_MEMSTAT_NVM_VAL_KEYS_Pos (16UL) |
SCU MEMSTAT: NVM_VAL_KEYS (Bit 16)
#define SCU_MEMSTAT_RAM_TEST_MODE_Msk (0x400000UL) |
SCU MEMSTAT: RAM_TEST_MODE (Bitfield-Mask: 0x01)
#define SCU_MEMSTAT_RAM_TEST_MODE_Pos (22UL) |
SCU MEMSTAT: RAM_TEST_MODE (Bit 22)
#define SCU_MEMSTAT_RAM_VAL_KEYS_Msk (0x300000UL) |
SCU MEMSTAT: RAM_VAL_KEYS (Bitfield-Mask: 0x03)
#define SCU_MEMSTAT_RAM_VAL_KEYS_Pos (20UL) |
SCU MEMSTAT: RAM_VAL_KEYS (Bit 20)
#define SCU_MEMSTAT_SASTATUS_Msk (0xc0UL) |
SCU MEMSTAT: SASTATUS (Bitfield-Mask: 0x03)
#define SCU_MEMSTAT_SASTATUS_Pos (6UL) |
SCU MEMSTAT: SASTATUS (Bit 6)
#define SCU_MEMSTAT_SECTORINFO_Msk (0x3fUL) |
SCU MEMSTAT: SECTORINFO (Bitfield-Mask: 0x3f)
#define SCU_MEMSTAT_SECTORINFO_Pos (0UL) |
SCU MEMSTAT: SECTORINFO (Bit 0)
#define SCU_MODIEN1_EIREN1_Msk (0x1UL) |
SCU MODIEN1: EIREN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_EIREN1_Pos (0UL) |
SCU MODIEN1: EIREN1 (Bit 0)
#define SCU_MODIEN1_EIREN2_Msk (0x100UL) |
SCU MODIEN1: EIREN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_EIREN2_Pos (8UL) |
SCU MODIEN1: EIREN2 (Bit 8)
#define SCU_MODIEN1_RIREN1_Msk (0x4UL) |
SCU MODIEN1: RIREN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_RIREN1_Pos (2UL) |
SCU MODIEN1: RIREN1 (Bit 2)
#define SCU_MODIEN1_RIREN2_Msk (0x400UL) |
SCU MODIEN1: RIREN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_RIREN2_Pos (10UL) |
SCU MODIEN1: RIREN2 (Bit 10)
#define SCU_MODIEN1_TIREN1_Msk (0x2UL) |
SCU MODIEN1: TIREN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_TIREN1_Pos (1UL) |
SCU MODIEN1: TIREN1 (Bit 1)
#define SCU_MODIEN1_TIREN2_Msk (0x200UL) |
SCU MODIEN1: TIREN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN1_TIREN2_Pos (9UL) |
SCU MODIEN1: TIREN2 (Bit 9)
#define SCU_MODIEN2_EXINT2_EN_Msk (0x20UL) |
SCU MODIEN2: EXINT2_EN (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_EXINT2_EN_Pos (5UL) |
SCU MODIEN2: EXINT2_EN (Bit 5)
#define SCU_MODIEN2_RIEN1_Msk (0x1UL) |
SCU MODIEN2: RIEN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_RIEN1_Pos (0UL) |
SCU MODIEN2: RIEN1 (Bit 0)
#define SCU_MODIEN2_RIEN2_Msk (0x40UL) |
SCU MODIEN2: RIEN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_RIEN2_Pos (6UL) |
SCU MODIEN2: RIEN2 (Bit 6)
#define SCU_MODIEN2_TIEN1_Msk (0x2UL) |
SCU MODIEN2: TIEN1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_TIEN1_Pos (1UL) |
SCU MODIEN2: TIEN1 (Bit 1)
#define SCU_MODIEN2_TIEN2_Msk (0x80UL) |
SCU MODIEN2: TIEN2 (Bitfield-Mask: 0x01)
#define SCU_MODIEN2_TIEN2_Pos (7UL) |
SCU MODIEN2: TIEN2 (Bit 7)
#define SCU_MODIEN3_IE0_Msk (0x1UL) |
SCU MODIEN3: IE0 (Bitfield-Mask: 0x01)
#define SCU_MODIEN3_IE0_Pos (0UL) |
SCU MODIEN3: IE0 (Bit 0)
#define SCU_MODIEN4_IE1_Msk (0x1UL) |
SCU MODIEN4: IE1 (Bitfield-Mask: 0x01)
#define SCU_MODIEN4_IE1_Pos (0UL) |
SCU MODIEN4: IE1 (Bit 0)
#define SCU_MODPISEL1_T21EXCON_Msk (0x80UL) |
SCU MODPISEL1: T21EXCON (Bitfield-Mask: 0x01)
#define SCU_MODPISEL1_T21EXCON_Pos (7UL) |
SCU MODPISEL1: T21EXCON (Bit 7)
#define SCU_MODPISEL1_T2EXCON_Msk (0x40UL) |
SCU MODPISEL1: T2EXCON (Bitfield-Mask: 0x01)
#define SCU_MODPISEL1_T2EXCON_Pos (6UL) |
SCU MODPISEL1: T2EXCON (Bit 6)
#define SCU_MODPISEL2_T21EXIS_Msk (0xc0UL) |
SCU MODPISEL2: T21EXIS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T21EXIS_Pos (6UL) |
SCU MODPISEL2: T21EXIS (Bit 6)
#define SCU_MODPISEL2_T21EXISCNF_Msk (0xc00UL) |
SCU MODPISEL2: T21EXISCNF (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T21EXISCNF_Pos (10UL) |
SCU MODPISEL2: T21EXISCNF (Bit 10)
#define SCU_MODPISEL2_T21IS_Msk (0xcUL) |
SCU MODPISEL2: T21IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T21IS_Pos (2UL) |
SCU MODPISEL2: T21IS (Bit 2)
#define SCU_MODPISEL2_T2EXIS_Msk (0x30UL) |
SCU MODPISEL2: T2EXIS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T2EXIS_Pos (4UL) |
SCU MODPISEL2: T2EXIS (Bit 4)
#define SCU_MODPISEL2_T2EXISCNF_Msk (0x300UL) |
SCU MODPISEL2: T2EXISCNF (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T2EXISCNF_Pos (8UL) |
SCU MODPISEL2: T2EXISCNF (Bit 8)
#define SCU_MODPISEL2_T2IS_Msk (0x3UL) |
SCU MODPISEL2: T2IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL2_T2IS_Pos (0UL) |
SCU MODPISEL2: T2IS (Bit 0)
#define SCU_MODPISEL3_URIOS2_Msk (0x40UL) |
SCU MODPISEL3: URIOS2 (Bitfield-Mask: 0x01)
#define SCU_MODPISEL3_URIOS2_Pos (6UL) |
SCU MODPISEL3: URIOS2 (Bit 6)
#define SCU_MODPISEL4_DU1TRIGGEN_Msk (0x7UL) |
SCU MODPISEL4: DU1TRIGGEN (Bitfield-Mask: 0x07)
#define SCU_MODPISEL4_DU1TRIGGEN_Pos (0UL) |
SCU MODPISEL4: DU1TRIGGEN (Bit 0)
#define SCU_MODPISEL4_DU2TRIGGEN_Msk (0x700UL) |
SCU MODPISEL4: DU2TRIGGEN (Bitfield-Mask: 0x07)
#define SCU_MODPISEL4_DU2TRIGGEN_Pos (8UL) |
SCU MODPISEL4: DU2TRIGGEN (Bit 8)
#define SCU_MODPISEL4_DU3TRIGGEN_Msk (0x70000UL) |
SCU MODPISEL4: DU3TRIGGEN (Bitfield-Mask: 0x07)
#define SCU_MODPISEL4_DU3TRIGGEN_Pos (16UL) |
SCU MODPISEL4: DU3TRIGGEN (Bit 16)
#define SCU_MODPISEL4_DU4TRIGGEN_Msk (0x7000000UL) |
SCU MODPISEL4: DU4TRIGGEN (Bitfield-Mask: 0x07)
#define SCU_MODPISEL4_DU4TRIGGEN_Pos (24UL) |
SCU MODPISEL4: DU4TRIGGEN (Bit 24)
#define SCU_MODPISEL_EXINT0IS_Msk (0x3UL) |
SCU MODPISEL: EXINT0IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL_EXINT0IS_Pos (0UL) |
SCU MODPISEL: EXINT0IS (Bit 0)
#define SCU_MODPISEL_EXINT1IS_Msk (0xcUL) |
SCU MODPISEL: EXINT1IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL_EXINT1IS_Pos (2UL) |
SCU MODPISEL: EXINT1IS (Bit 2)
#define SCU_MODPISEL_EXINT2IS_Msk (0x30UL) |
SCU MODPISEL: EXINT2IS (Bitfield-Mask: 0x03)
#define SCU_MODPISEL_EXINT2IS_Pos (4UL) |
SCU MODPISEL: EXINT2IS (Bit 4)
#define SCU_MODPISEL_SSC12_M_MTSR_OUTSEL_Msk (0x20000UL) |
SCU MODPISEL: SSC12_M_MTSR_OUTSEL (Bitfield-Mask: 0x01)
#define SCU_MODPISEL_SSC12_M_MTSR_OUTSEL_Pos (17UL) |
SCU MODPISEL: SSC12_M_MTSR_OUTSEL (Bit 17)
#define SCU_MODPISEL_SSC12_M_SCK_OUTSEL_Msk (0x10000UL) |
SCU MODPISEL: SSC12_M_SCK_OUTSEL (Bitfield-Mask: 0x01)
#define SCU_MODPISEL_SSC12_M_SCK_OUTSEL_Pos (16UL) |
SCU MODPISEL: SSC12_M_SCK_OUTSEL (Bit 16)
#define SCU_MODPISEL_SSC12_S_MRST_OUTSEL_Msk (0x40000UL) |
SCU MODPISEL: SSC12_S_MRST_OUTSEL (Bitfield-Mask: 0x01)
#define SCU_MODPISEL_SSC12_S_MRST_OUTSEL_Pos (18UL) |
SCU MODPISEL: SSC12_S_MRST_OUTSEL (Bit 18)
#define SCU_MODPISEL_U_TX_CONDIS_Msk (0x80UL) |
SCU MODPISEL: U_TX_CONDIS (Bitfield-Mask: 0x01)
#define SCU_MODPISEL_U_TX_CONDIS_Pos (7UL) |
SCU MODPISEL: U_TX_CONDIS (Bit 7)
#define SCU_MODPISEL_URIOS1_Msk (0x40UL) |
SCU MODPISEL: URIOS1 (Bitfield-Mask: 0x01)
#define SCU_MODPISEL_URIOS1_Pos (6UL) |
SCU MODPISEL: URIOS1 (Bit 6)
#define SCU_MODSUSP_ADC1_SUSP_Msk (0x400UL) |
SCU MODSUSP: ADC1_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_ADC1_SUSP_Pos (10UL) |
SCU MODSUSP: ADC1_SUSP (Bit 10)
#define SCU_MODSUSP_GPT12_SUSP_Msk (0x10UL) |
SCU MODSUSP: GPT12_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_GPT12_SUSP_Pos (4UL) |
SCU MODSUSP: GPT12_SUSP (Bit 4)
#define SCU_MODSUSP_MU_SUSP_Msk (0x200UL) |
SCU MODSUSP: MU_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_MU_SUSP_Pos (9UL) |
SCU MODSUSP: MU_SUSP (Bit 9)
#define SCU_MODSUSP_T12SUSP_Msk (0x2UL) |
SCU MODSUSP: T12SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_T12SUSP_Pos (1UL) |
SCU MODSUSP: T12SUSP (Bit 1)
#define SCU_MODSUSP_T13SUSP_Msk (0x4UL) |
SCU MODSUSP: T13SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_T13SUSP_Pos (2UL) |
SCU MODSUSP: T13SUSP (Bit 2)
#define SCU_MODSUSP_T21_SUSP_Msk (0x40UL) |
SCU MODSUSP: T21_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_T21_SUSP_Pos (6UL) |
SCU MODSUSP: T21_SUSP (Bit 6)
#define SCU_MODSUSP_T2_SUSP_Msk (0x8UL) |
SCU MODSUSP: T2_SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_T2_SUSP_Pos (3UL) |
SCU MODSUSP: T2_SUSP (Bit 3)
#define SCU_MODSUSP_WDT1SUSP_Msk (0x80UL) |
SCU MODSUSP: WDT1SUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_WDT1SUSP_Pos (7UL) |
SCU MODSUSP: WDT1SUSP (Bit 7)
#define SCU_MODSUSP_WDTSUSP_Msk (0x1UL) |
SCU MODSUSP: WDTSUSP (Bitfield-Mask: 0x01)
#define SCU_MODSUSP_WDTSUSP_Pos (0UL) |
SCU MODSUSP: WDTSUSP (Bit 0)
#define SCU_MONIEN_MON1IE_Msk (0x1UL) |
SCU MONIEN: MON1IE (Bitfield-Mask: 0x01)
#define SCU_MONIEN_MON1IE_Pos (0UL) |
SCU MONIEN: MON1IE (Bit 0)
#define SCU_MONIEN_MON2IE_Msk (0x2UL) |
SCU MONIEN: MON2IE (Bitfield-Mask: 0x01)
#define SCU_MONIEN_MON2IE_Pos (1UL) |
SCU MONIEN: MON2IE (Bit 1)
#define SCU_MONIEN_MON3IE_Msk (0x4UL) |
SCU MONIEN: MON3IE (Bitfield-Mask: 0x01)
#define SCU_MONIEN_MON3IE_Pos (2UL) |
SCU MONIEN: MON3IE (Bit 2)
#define SCU_MONIEN_MON4IE_Msk (0x8UL) |
SCU MONIEN: MON4IE (Bitfield-Mask: 0x01)
#define SCU_MONIEN_MON4IE_Pos (3UL) |
SCU MONIEN: MON4IE (Bit 3)
#define SCU_NMICON_NMIECC_Msk (0x40UL) |
SCU NMICON: NMIECC (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIECC_Pos (6UL) |
SCU NMICON: NMIECC (Bit 6)
#define SCU_NMICON_NMIMAP_Msk (0x20UL) |
SCU NMICON: NMIMAP (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIMAP_Pos (5UL) |
SCU NMICON: NMIMAP (Bit 5)
#define SCU_NMICON_NMIOT_Msk (0x8UL) |
SCU NMICON: NMIOT (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIOT_Pos (3UL) |
SCU NMICON: NMIOT (Bit 3)
#define SCU_NMICON_NMIOWD_Msk (0x10UL) |
SCU NMICON: NMIOWD (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIOWD_Pos (4UL) |
SCU NMICON: NMIOWD (Bit 4)
#define SCU_NMICON_NMISTOF_Msk (0x100UL) |
SCU NMICON: NMISTOF (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMISTOF_Pos (8UL) |
SCU NMICON: NMISTOF (Bit 8)
#define SCU_NMICON_NMISUP_Msk (0x80UL) |
SCU NMICON: NMISUP (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMISUP_Pos (7UL) |
SCU NMICON: NMISUP (Bit 7)
#define SCU_NMICON_NMIWDT_Msk (0x1UL) |
SCU NMICON: NMIWDT (Bitfield-Mask: 0x01)
#define SCU_NMICON_NMIWDT_Pos (0UL) |
SCU NMICON: NMIWDT (Bit 0)
#define SCU_NMISR_FNMIECC_Msk (0x40UL) |
SCU NMISR: FNMIECC (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIECC_Pos (6UL) |
SCU NMISR: FNMIECC (Bit 6)
#define SCU_NMISR_FNMIMAP_Msk (0x20UL) |
SCU NMISR: FNMIMAP (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIMAP_Pos (5UL) |
SCU NMISR: FNMIMAP (Bit 5)
#define SCU_NMISR_FNMIOT_Msk (0x8UL) |
SCU NMISR: FNMIOT (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIOT_Pos (3UL) |
SCU NMISR: FNMIOT (Bit 3)
#define SCU_NMISR_FNMIOWD_Msk (0x10UL) |
SCU NMISR: FNMIOWD (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIOWD_Pos (4UL) |
SCU NMISR: FNMIOWD (Bit 4)
#define SCU_NMISR_FNMISTOF_Msk (0x100UL) |
SCU NMISR: FNMISTOF (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMISTOF_Pos (8UL) |
SCU NMISR: FNMISTOF (Bit 8)
#define SCU_NMISR_FNMISUP_Msk (0x80UL) |
SCU NMISR: FNMISUP (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMISUP_Pos (7UL) |
SCU NMISR: FNMISUP (Bit 7)
#define SCU_NMISR_FNMIWDT_Msk (0x1UL) |
SCU NMISR: FNMIWDT (Bitfield-Mask: 0x01)
#define SCU_NMISR_FNMIWDT_Pos (0UL) |
SCU NMISR: FNMIWDT (Bit 0)
#define SCU_NMISRCLR_FNMIMAPC_Msk (0x20UL) |
SCU NMISRCLR: FNMIMAPC (Bitfield-Mask: 0x01)
#define SCU_NMISRCLR_FNMIMAPC_Pos (5UL) |
SCU NMISRCLR: FNMIMAPC (Bit 5)
#define SCU_NMISRCLR_FNMIOWDC_Msk (0x10UL) |
SCU NMISRCLR: FNMIOWDC (Bitfield-Mask: 0x01)
#define SCU_NMISRCLR_FNMIOWDC_Pos (4UL) |
SCU NMISRCLR: FNMIOWDC (Bit 4)
#define SCU_NMISRCLR_FNMIWDTC_Msk (0x1UL) |
SCU NMISRCLR: FNMIWDTC (Bitfield-Mask: 0x01)
#define SCU_NMISRCLR_FNMIWDTC_Pos (0UL) |
SCU NMISRCLR: FNMIWDTC (Bit 0)
#define SCU_NVM_PROT_STS_COD_LIN_PW_Msk (0x100000UL) |
SCU NVM_PROT_STS: COD_LIN_PW (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_COD_LIN_PW_Pos (20UL) |
SCU NVM_PROT_STS: COD_LIN_PW (Bit 20)
#define SCU_NVM_PROT_STS_CUS_BSL_PW_Msk (0x80000UL) |
SCU NVM_PROT_STS: CUS_BSL_PW (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_CUS_BSL_PW_Pos (19UL) |
SCU NVM_PROT_STS: CUS_BSL_PW (Bit 19)
#define SCU_NVM_PROT_STS_CUS_BSL_SIZE_Msk (0x3000000UL) |
SCU NVM_PROT_STS: CUS_BSL_SIZE (Bitfield-Mask: 0x03)
#define SCU_NVM_PROT_STS_CUS_BSL_SIZE_Pos (24UL) |
SCU NVM_PROT_STS: CUS_BSL_SIZE (Bit 24)
#define SCU_NVM_PROT_STS_DAT_LIN_PW_Msk (0x200000UL) |
SCU NVM_PROT_STS: DAT_LIN_PW (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_DAT_LIN_PW_Pos (21UL) |
SCU NVM_PROT_STS: DAT_LIN_PW (Bit 21)
#define SCU_NVM_PROT_STS_DAT_LIN_SIZE_Msk (0xc000000UL) |
SCU NVM_PROT_STS: DAT_LIN_SIZE (Bitfield-Mask: 0x03)
#define SCU_NVM_PROT_STS_DAT_LIN_SIZE_Pos (26UL) |
SCU NVM_PROT_STS: DAT_LIN_SIZE (Bit 26)
#define SCU_NVM_PROT_STS_DAT_NL_PW_Msk (0x400000UL) |
SCU NVM_PROT_STS: DAT_NL_PW (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_DAT_NL_PW_Pos (22UL) |
SCU NVM_PROT_STS: DAT_NL_PW (Bit 22)
#define SCU_NVM_PROT_STS_DIS_RDUS_Msk (0x20000UL) |
SCU NVM_PROT_STS: DIS_RDUS (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_DIS_RDUS_Pos (17UL) |
SCU NVM_PROT_STS: DIS_RDUS (Bit 17)
#define SCU_NVM_PROT_STS_DIS_RDUS_S0_Msk (0x40000UL) |
SCU NVM_PROT_STS: DIS_RDUS_S0 (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_DIS_RDUS_S0_Pos (18UL) |
SCU NVM_PROT_STS: DIS_RDUS_S0 (Bit 18)
#define SCU_NVM_PROT_STS_EN_PRG_COD_LIN_Msk (0x8UL) |
SCU NVM_PROT_STS: EN_PRG_COD_LIN (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_PRG_COD_LIN_Pos (3UL) |
SCU NVM_PROT_STS: EN_PRG_COD_LIN (Bit 3)
#define SCU_NVM_PROT_STS_EN_PRG_CUS_BSL_Msk (0x2UL) |
SCU NVM_PROT_STS: EN_PRG_CUS_BSL (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_PRG_CUS_BSL_Pos (1UL) |
SCU NVM_PROT_STS: EN_PRG_CUS_BSL (Bit 1)
#define SCU_NVM_PROT_STS_EN_PRG_DAT_LIN_Msk (0x20UL) |
SCU NVM_PROT_STS: EN_PRG_DAT_LIN (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_PRG_DAT_LIN_Pos (5UL) |
SCU NVM_PROT_STS: EN_PRG_DAT_LIN (Bit 5)
#define SCU_NVM_PROT_STS_EN_PRG_DAT_NL_Msk (0x80UL) |
SCU NVM_PROT_STS: EN_PRG_DAT_NL (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_PRG_DAT_NL_Pos (7UL) |
SCU NVM_PROT_STS: EN_PRG_DAT_NL (Bit 7)
#define SCU_NVM_PROT_STS_EN_RD_COD_LIN_Msk (0x4UL) |
SCU NVM_PROT_STS: EN_RD_COD_LIN (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_RD_COD_LIN_Pos (2UL) |
SCU NVM_PROT_STS: EN_RD_COD_LIN (Bit 2)
#define SCU_NVM_PROT_STS_EN_RD_CUS_BSL_Msk (0x1UL) |
SCU NVM_PROT_STS: EN_RD_CUS_BSL (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_RD_CUS_BSL_Pos (0UL) |
SCU NVM_PROT_STS: EN_RD_CUS_BSL (Bit 0)
#define SCU_NVM_PROT_STS_EN_RD_DAT_LIN_Msk (0x10UL) |
SCU NVM_PROT_STS: EN_RD_DAT_LIN (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_RD_DAT_LIN_Pos (4UL) |
SCU NVM_PROT_STS: EN_RD_DAT_LIN (Bit 4)
#define SCU_NVM_PROT_STS_EN_RD_DAT_NL_Msk (0x40UL) |
SCU NVM_PROT_STS: EN_RD_DAT_NL (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_RD_DAT_NL_Pos (6UL) |
SCU NVM_PROT_STS: EN_RD_DAT_NL (Bit 6)
#define SCU_NVM_PROT_STS_EN_RD_S0_Msk (0x10000UL) |
SCU NVM_PROT_STS: EN_RD_S0 (Bitfield-Mask: 0x01)
#define SCU_NVM_PROT_STS_EN_RD_S0_Pos (16UL) |
SCU NVM_PROT_STS: EN_RD_S0 (Bit 16)
#define SCU_P0_POCON0_P0_PDM0_Msk (0x7UL) |
SCU P0_POCON0: P0_PDM0 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_P0_PDM0_Pos (0UL) |
SCU P0_POCON0: P0_PDM0 (Bit 0)
#define SCU_P0_POCON0_P0_PDM1_Msk (0x70UL) |
SCU P0_POCON0: P0_PDM1 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_P0_PDM1_Pos (4UL) |
SCU P0_POCON0: P0_PDM1 (Bit 4)
#define SCU_P0_POCON0_P0_PDM2_Msk (0x700UL) |
SCU P0_POCON0: P0_PDM2 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_P0_PDM2_Pos (8UL) |
SCU P0_POCON0: P0_PDM2 (Bit 8)
#define SCU_P0_POCON0_P0_PDM3_Msk (0x7000UL) |
SCU P0_POCON0: P0_PDM3 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_P0_PDM3_Pos (12UL) |
SCU P0_POCON0: P0_PDM3 (Bit 12)
#define SCU_P0_POCON0_P0_PDM4_Msk (0x70000UL) |
SCU P0_POCON0: P0_PDM4 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_P0_PDM4_Pos (16UL) |
SCU P0_POCON0: P0_PDM4 (Bit 16)
#define SCU_P0_POCON0_P0_PDM5_Msk (0x700000UL) |
SCU P0_POCON0: P0_PDM5 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_P0_PDM5_Pos (20UL) |
SCU P0_POCON0: P0_PDM5 (Bit 20)
#define SCU_P0_POCON0_P0_PDM6_Msk (0x7000000UL) |
SCU P0_POCON0: P0_PDM6 (Bitfield-Mask: 0x07)
#define SCU_P0_POCON0_P0_PDM6_Pos (24UL) |
SCU P0_POCON0: P0_PDM6 (Bit 24)
#define SCU_P1_POCON0_P1_PDM0_Msk (0x7UL) |
SCU P1_POCON0: P1_PDM0 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON0_P1_PDM0_Pos (0UL) |
SCU P1_POCON0: P1_PDM0 (Bit 0)
#define SCU_P1_POCON0_P1_PDM1_Msk (0x70UL) |
SCU P1_POCON0: P1_PDM1 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON0_P1_PDM1_Pos (4UL) |
SCU P1_POCON0: P1_PDM1 (Bit 4)
#define SCU_P1_POCON0_P1_PDM2_Msk (0x700UL) |
SCU P1_POCON0: P1_PDM2 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON0_P1_PDM2_Pos (8UL) |
SCU P1_POCON0: P1_PDM2 (Bit 8)
#define SCU_P1_POCON0_P1_PDM4_Msk (0x70000UL) |
SCU P1_POCON0: P1_PDM4 (Bitfield-Mask: 0x07)
#define SCU_P1_POCON0_P1_PDM4_Pos (16UL) |
SCU P1_POCON0: P1_PDM4 (Bit 16)
#define SCU_PASSWD_PASS_Msk (0xf8UL) |
SCU PASSWD: PASS (Bitfield-Mask: 0x1f)
#define SCU_PASSWD_PASS_Pos (3UL) |
SCU PASSWD: PASS (Bit 3)
#define SCU_PASSWD_PROTECT_S_Msk (0x4UL) |
SCU PASSWD: PROTECT_S (Bitfield-Mask: 0x01)
#define SCU_PASSWD_PROTECT_S_Pos (2UL) |
SCU PASSWD: PROTECT_S (Bit 2)
#define SCU_PASSWD_PW_MODE_Msk (0x3UL) |
SCU PASSWD: PW_MODE (Bitfield-Mask: 0x03)
#define SCU_PASSWD_PW_MODE_Pos (0UL) |
SCU PASSWD: PW_MODE (Bit 0)
#define SCU_PMCON0_PD_Msk (0x4UL) |
SCU PMCON0: PD (Bitfield-Mask: 0x01)
#define SCU_PMCON0_PD_Pos (2UL) |
SCU PMCON0: PD (Bit 2)
#define SCU_PMCON0_SD_Msk (0x8UL) |
SCU PMCON0: SD (Bitfield-Mask: 0x01)
#define SCU_PMCON0_SD_Pos (3UL) |
SCU PMCON0: SD (Bit 3)
#define SCU_PMCON0_SL_Msk (0x2UL) |
SCU PMCON0: SL (Bitfield-Mask: 0x01)
#define SCU_PMCON0_SL_Pos (1UL) |
SCU PMCON0: SL (Bit 1)
#define SCU_PMCON_ADC1_DIS_Msk (0x1UL) |
SCU PMCON: ADC1_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON_ADC1_DIS_Pos (0UL) |
SCU PMCON: ADC1_DIS (Bit 0)
#define SCU_PMCON_CCU_DIS_Msk (0x4UL) |
SCU PMCON: CCU_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON_CCU_DIS_Pos (2UL) |
SCU PMCON: CCU_DIS (Bit 2)
#define SCU_PMCON_GPT12_DIS_Msk (0x10UL) |
SCU PMCON: GPT12_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON_GPT12_DIS_Pos (4UL) |
SCU PMCON: GPT12_DIS (Bit 4)
#define SCU_PMCON_SSC1_DIS_Msk (0x2UL) |
SCU PMCON: SSC1_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON_SSC1_DIS_Pos (1UL) |
SCU PMCON: SSC1_DIS (Bit 1)
#define SCU_PMCON_SSC2_DIS_Msk (0x100UL) |
SCU PMCON: SSC2_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON_SSC2_DIS_Pos (8UL) |
SCU PMCON: SSC2_DIS (Bit 8)
#define SCU_PMCON_T21_DIS_Msk (0x400UL) |
SCU PMCON: T21_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON_T21_DIS_Pos (10UL) |
SCU PMCON: T21_DIS (Bit 10)
#define SCU_PMCON_T2_DIS_Msk (0x8UL) |
SCU PMCON: T2_DIS (Bitfield-Mask: 0x01)
#define SCU_PMCON_T2_DIS_Pos (3UL) |
SCU PMCON: T2_DIS (Bit 3)
#define SCU_RSTCON_LOCKUP_EN_Msk (0x80UL) |
SCU RSTCON: LOCKUP_EN (Bitfield-Mask: 0x01)
#define SCU_RSTCON_LOCKUP_EN_Pos (7UL) |
SCU RSTCON: LOCKUP_EN (Bit 7)
#define SCU_RSTCON_LOCKUP_Msk (0x1UL) |
SCU RSTCON: LOCKUP (Bitfield-Mask: 0x01)
#define SCU_RSTCON_LOCKUP_Pos (0UL) |
SCU RSTCON: LOCKUP (Bit 0)
#define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_H_Msk (0xffc0000UL) |
SCU STACK_OVF_ADDR: STOF_ADDR_OFF_H (Bitfield-Mask: 0x3ff)
#define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_H_Pos (18UL) |
SCU STACK_OVF_ADDR: STOF_ADDR_OFF_H (Bit 18)
#define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_L_Msk (0xffcUL) |
SCU STACK_OVF_ADDR: STOF_ADDR_OFF_L (Bitfield-Mask: 0x3ff)
#define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_L_Pos (2UL) |
SCU STACK_OVF_ADDR: STOF_ADDR_OFF_L (Bit 2)
#define SCU_STACK_OVF_CTRL_STOF_EN_Msk (0x1UL) |
SCU STACK_OVF_CTRL: STOF_EN (Bitfield-Mask: 0x01)
#define SCU_STACK_OVF_CTRL_STOF_EN_Pos (0UL) |
SCU STACK_OVF_CTRL: STOF_EN (Bit 0)
#define SCU_STACK_OVF_STS_STOF_STS_Msk (0x1UL) |
SCU STACK_OVF_STS: STOF_STS (Bitfield-Mask: 0x01)
#define SCU_STACK_OVF_STS_STOF_STS_Pos (0UL) |
SCU STACK_OVF_STS: STOF_STS (Bit 0)
#define SCU_STACK_OVFCLR_STOF_STSC_Msk (0x1UL) |
SCU STACK_OVFCLR: STOF_STSC (Bitfield-Mask: 0x01)
#define SCU_STACK_OVFCLR_STOF_STSC_Pos (0UL) |
SCU STACK_OVFCLR: STOF_STSC (Bit 0)
#define SCU_SYS_STRTUP_STS_MRAMINITSTS_Msk (0x2UL) |
SCU SYS_STRTUP_STS: MRAMINITSTS (Bitfield-Mask: 0x01)
#define SCU_SYS_STRTUP_STS_MRAMINITSTS_Pos (1UL) |
SCU SYS_STRTUP_STS: MRAMINITSTS (Bit 1)
#define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Msk (0x4UL) |
SCU SYS_STRTUP_STS: PG100TP_CHKS_ERR (Bitfield-Mask: 0x01)
#define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Pos (2UL) |
SCU SYS_STRTUP_STS: PG100TP_CHKS_ERR (Bit 2)
#define SCU_SYSCON0_NVMCLKFAC_Msk (0x30UL) |
SCU SYSCON0: NVMCLKFAC (Bitfield-Mask: 0x03)
#define SCU_SYSCON0_NVMCLKFAC_Pos (4UL) |
SCU SYSCON0: NVMCLKFAC (Bit 4)
#define SCU_SYSCON0_SYSCLKSEL_Msk (0xc0UL) |
SCU SYSCON0: SYSCLKSEL (Bitfield-Mask: 0x03)
#define SCU_SYSCON0_SYSCLKSEL_Pos (6UL) |
SCU SYSCON0: SYSCLKSEL (Bit 6)
#define SCU_TCCR_TCC_Msk (0x3UL) |
SCU TCCR: TCC (Bitfield-Mask: 0x03)
#define SCU_TCCR_TCC_Pos (0UL) |
SCU TCCR: TCC (Bit 0)
#define SCU_VTOR_VTOR_BYP_Msk (0x3UL) |
SCU VTOR: VTOR_BYP (Bitfield-Mask: 0x03)
#define SCU_VTOR_VTOR_BYP_Pos (0UL) |
SCU VTOR: VTOR_BYP (Bit 0)
#define SCU_WAKECON_WAKEUPEN_Msk (0x1UL) |
SCU WAKECON: WAKEUPEN (Bitfield-Mask: 0x01)
#define SCU_WAKECON_WAKEUPEN_Pos (0UL) |
SCU WAKECON: WAKEUPEN (Bit 0)
#define SCU_WDT_WDT_Msk (0xffffUL) |
SCU WDT: WDT (Bitfield-Mask: 0xffff)
#define SCU_WDT_WDT_Pos (0UL) |
SCU WDT: WDT (Bit 0)
#define SCU_WDTCON_WDTEN_Msk (0x4UL) |
SCU WDTCON: WDTEN (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTEN_Pos (2UL) |
SCU WDTCON: WDTEN (Bit 2)
#define SCU_WDTCON_WDTIN_Msk (0x1UL) |
SCU WDTCON: WDTIN (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTIN_Pos (0UL) |
SCU WDTCON: WDTIN (Bit 0)
#define SCU_WDTCON_WDTPR_Msk (0x10UL) |
SCU WDTCON: WDTPR (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTPR_Pos (4UL) |
SCU WDTCON: WDTPR (Bit 4)
#define SCU_WDTCON_WDTRS_Msk (0x2UL) |
SCU WDTCON: WDTRS (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WDTRS_Pos (1UL) |
SCU WDTCON: WDTRS (Bit 1)
#define SCU_WDTCON_WINBEN_Msk (0x20UL) |
SCU WDTCON: WINBEN (Bitfield-Mask: 0x01)
#define SCU_WDTCON_WINBEN_Pos (5UL) |
SCU WDTCON: WINBEN (Bit 5)
#define SCU_WDTREL_WDTREL_Msk (0xffUL) |
SCU WDTREL: WDTREL (Bitfield-Mask: 0xff)
#define SCU_WDTREL_WDTREL_Pos (0UL) |
SCU WDTREL: WDTREL (Bit 0)
#define SCU_WDTWINB_WDTWINB_Msk (0xffUL) |
SCU WDTWINB: WDTWINB (Bitfield-Mask: 0xff)
#define SCU_WDTWINB_WDTWINB_Pos (0UL) |
SCU WDTWINB: WDTWINB (Bit 0)
#define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk (0x1UL) |
SCUPM AMCLK_CTRL: CLKWDT_PD_N (Bitfield-Mask: 0x01)
#define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos (0UL) |
SCUPM AMCLK_CTRL: CLKWDT_PD_N (Bit 0)
#define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Msk (0x3fUL) |
SCUPM AMCLK_FREQ_STS: AMCLK1_FREQ (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Pos (0UL) |
SCUPM AMCLK_FREQ_STS: AMCLK1_FREQ (Bit 0)
#define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Msk (0x3f00UL) |
SCUPM AMCLK_FREQ_STS: AMCLK2_FREQ (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Pos (8UL) |
SCUPM AMCLK_FREQ_STS: AMCLK2_FREQ (Bit 8)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk (0xc000UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos (14UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_HYS (Bit 14)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk (0x3f00UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos (8UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_LOW_TH (Bit 8)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk (0xc0UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos (6UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_HYS (Bit 6)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk (0x3fUL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos (0UL) |
SCUPM AMCLK_TH_HYS: AMCLK1_UP_TH (Bit 0)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk (0xc0000000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos (30UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_HYS (Bit 30)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk (0x3f000000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos (24UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_LOW_TH (Bit 24)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk (0xc00000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_HYS (Bitfield-Mask: 0x03)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos (22UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_HYS (Bit 22)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk (0x3f0000UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_TH (Bitfield-Mask: 0x3f)
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos (16UL) |
SCUPM AMCLK_TH_HYS: AMCLK2_UP_TH (Bit 16)
#define SCUPM_PCU_CTRL_STS_CLKLOSS_RES_SD_DIS_Msk (0x8000000UL) |
SCUPM PCU_CTRL_STS: CLKLOSS_RES_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_CLKLOSS_RES_SD_DIS_Pos (27UL) |
SCUPM PCU_CTRL_STS: CLKLOSS_RES_SD_DIS (Bit 27)
#define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk (0x2000000UL) |
SCUPM PCU_CTRL_STS: CLKLOSS_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos (25UL) |
SCUPM PCU_CTRL_STS: CLKLOSS_SD_DIS (Bit 25)
#define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk (0x4000000UL) |
SCUPM PCU_CTRL_STS: CLKWDT_RES_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos (26UL) |
SCUPM PCU_CTRL_STS: CLKWDT_RES_SD_DIS (Bit 26)
#define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk (0x2UL) |
SCUPM PCU_CTRL_STS: CLKWDT_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos (1UL) |
SCUPM PCU_CTRL_STS: CLKWDT_SD_DIS (Bit 1)
#define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk (0x80UL) |
SCUPM PCU_CTRL_STS: FAIL_PS_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos (7UL) |
SCUPM PCU_CTRL_STS: FAIL_PS_DIS (Bit 7)
#define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk (0x100UL) |
SCUPM PCU_CTRL_STS: LIN_VS_UV_SD_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos (8UL) |
SCUPM PCU_CTRL_STS: LIN_VS_UV_SD_DIS (Bit 8)
#define SCUPM_PCU_CTRL_STS_SYS_OTWARN_PS_DIS_Msk (0x1000000UL) |
SCUPM PCU_CTRL_STS: SYS_OTWARN_PS_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_SYS_OTWARN_PS_DIS_Pos (24UL) |
SCUPM PCU_CTRL_STS: SYS_OTWARN_PS_DIS (Bit 24)
#define SCUPM_PCU_CTRL_STS_SYS_VS_OV_SLM_DIS_Msk (0x4000UL) |
SCUPM PCU_CTRL_STS: SYS_VS_OV_SLM_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_SYS_VS_OV_SLM_DIS_Pos (14UL) |
SCUPM PCU_CTRL_STS: SYS_VS_OV_SLM_DIS (Bit 14)
#define SCUPM_PCU_CTRL_STS_SYS_VS_UV_SLM_DIS_Msk (0x2000UL) |
SCUPM PCU_CTRL_STS: SYS_VS_UV_SLM_DIS (Bitfield-Mask: 0x01)
#define SCUPM_PCU_CTRL_STS_SYS_VS_UV_SLM_DIS_Pos (13UL) |
SCUPM PCU_CTRL_STS: SYS_VS_UV_SLM_DIS (Bit 13)
#define SCUPM_STCALIB_STCALIB_Msk (0x3ffffffUL) |
SCUPM STCALIB: STCALIB (Bitfield-Mask: 0x3ffffff)
#define SCUPM_STCALIB_STCALIB_Pos (0UL) |
SCUPM STCALIB: STCALIB (Bit 0)
#define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Msk (0x200UL) |
SCUPM SYS_IRQ_CTRL: SYS_OT_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Pos (9UL) |
SCUPM SYS_IRQ_CTRL: SYS_OT_IE (Bit 9)
#define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Msk (0x100UL) |
SCUPM SYS_IRQ_CTRL: SYS_OTWARN_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Pos (8UL) |
SCUPM SYS_IRQ_CTRL: SYS_OTWARN_IE (Bit 8)
#define SCUPM_SYS_IRQ_CTRL_VREF1V2_OV_IE_Msk (0x2000UL) |
SCUPM SYS_IRQ_CTRL: VREF1V2_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_VREF1V2_OV_IE_Pos (13UL) |
SCUPM SYS_IRQ_CTRL: VREF1V2_OV_IE (Bit 13)
#define SCUPM_SYS_IRQ_CTRL_VREF1V2_UV_IE_Msk (0x1000UL) |
SCUPM SYS_IRQ_CTRL: VREF1V2_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IRQ_CTRL_VREF1V2_UV_IE_Pos (12UL) |
SCUPM SYS_IRQ_CTRL: VREF1V2_UV_IE (Bit 12)
#define SCUPM_SYS_IS_CLKWDT_IS_Msk (0x400UL) |
SCUPM SYS_IS: CLKWDT_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_CLKWDT_IS_Pos (10UL) |
SCUPM SYS_IS: CLKWDT_IS (Bit 10)
#define SCUPM_SYS_IS_CP_FAIL_IS_Msk (0x2UL) |
SCUPM SYS_IS: CP_FAIL_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_CP_FAIL_IS_Pos (1UL) |
SCUPM SYS_IS: CP_FAIL_IS (Bit 1)
#define SCUPM_SYS_IS_CP_FAIL_STS_Msk (0x20000UL) |
SCUPM SYS_IS: CP_FAIL_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_CP_FAIL_STS_Pos (17UL) |
SCUPM SYS_IS: CP_FAIL_STS (Bit 17)
#define SCUPM_SYS_IS_DRV_FAIL_IS_Msk (0x4UL) |
SCUPM SYS_IS: DRV_FAIL_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_DRV_FAIL_IS_Pos (2UL) |
SCUPM SYS_IS: DRV_FAIL_IS (Bit 2)
#define SCUPM_SYS_IS_DRV_FAIL_STS_Msk (0x40000UL) |
SCUPM SYS_IS: DRV_FAIL_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_DRV_FAIL_STS_Pos (18UL) |
SCUPM SYS_IS: DRV_FAIL_STS (Bit 18)
#define SCUPM_SYS_IS_HS_FAIL_IS_Msk (0x8UL) |
SCUPM SYS_IS: HS_FAIL_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_HS_FAIL_IS_Pos (3UL) |
SCUPM SYS_IS: HS_FAIL_IS (Bit 3)
#define SCUPM_SYS_IS_HS_FAIL_STS_Msk (0x80000UL) |
SCUPM SYS_IS: HS_FAIL_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_HS_FAIL_STS_Pos (19UL) |
SCUPM SYS_IS: HS_FAIL_STS (Bit 19)
#define SCUPM_SYS_IS_LIN_FAIL_IS_Msk (0x1UL) |
SCUPM SYS_IS: LIN_FAIL_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_LIN_FAIL_IS_Pos (0UL) |
SCUPM SYS_IS: LIN_FAIL_IS (Bit 0)
#define SCUPM_SYS_IS_LIN_FAIL_STS_Msk (0x10000UL) |
SCUPM SYS_IS: LIN_FAIL_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_LIN_FAIL_STS_Pos (16UL) |
SCUPM SYS_IS: LIN_FAIL_STS (Bit 16)
#define SCUPM_SYS_IS_SYS_OT_IS_Msk (0x200UL) |
SCUPM SYS_IS: SYS_OT_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_OT_IS_Pos (9UL) |
SCUPM SYS_IS: SYS_OT_IS (Bit 9)
#define SCUPM_SYS_IS_SYS_OT_STS_Msk (0x2000000UL) |
SCUPM SYS_IS: SYS_OT_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_OT_STS_Pos (25UL) |
SCUPM SYS_IS: SYS_OT_STS (Bit 25)
#define SCUPM_SYS_IS_SYS_OTWARN_IS_Msk (0x100UL) |
SCUPM SYS_IS: SYS_OTWARN_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_OTWARN_IS_Pos (8UL) |
SCUPM SYS_IS: SYS_OTWARN_IS (Bit 8)
#define SCUPM_SYS_IS_SYS_OTWARN_STS_Msk (0x1000000UL) |
SCUPM SYS_IS: SYS_OTWARN_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_OTWARN_STS_Pos (24UL) |
SCUPM SYS_IS: SYS_OTWARN_STS (Bit 24)
#define SCUPM_SYS_IS_SYS_SUPPLY_IS_Msk (0x4000UL) |
SCUPM SYS_IS: SYS_SUPPLY_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_SUPPLY_IS_Pos (14UL) |
SCUPM SYS_IS: SYS_SUPPLY_IS (Bit 14)
#define SCUPM_SYS_IS_SYS_SUPPLY_STS_Msk (0x40000000UL) |
SCUPM SYS_IS: SYS_SUPPLY_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_SYS_SUPPLY_STS_Pos (30UL) |
SCUPM SYS_IS: SYS_SUPPLY_STS (Bit 30)
#define SCUPM_SYS_IS_VREF1V2_OV_IS_Msk (0x2000UL) |
SCUPM SYS_IS: VREF1V2_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_VREF1V2_OV_IS_Pos (13UL) |
SCUPM SYS_IS: VREF1V2_OV_IS (Bit 13)
#define SCUPM_SYS_IS_VREF1V2_OV_STS_Msk (0x20000000UL) |
SCUPM SYS_IS: VREF1V2_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_VREF1V2_OV_STS_Pos (29UL) |
SCUPM SYS_IS: VREF1V2_OV_STS (Bit 29)
#define SCUPM_SYS_IS_VREF1V2_UV_IS_Msk (0x1000UL) |
SCUPM SYS_IS: VREF1V2_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_VREF1V2_UV_IS_Pos (12UL) |
SCUPM SYS_IS: VREF1V2_UV_IS (Bit 12)
#define SCUPM_SYS_IS_VREF1V2_UV_STS_Msk (0x10000000UL) |
SCUPM SYS_IS: VREF1V2_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_IS_VREF1V2_UV_STS_Pos (28UL) |
SCUPM SYS_IS: VREF1V2_UV_STS (Bit 28)
#define SCUPM_SYS_ISCLR_SYS_OT_ISC_Msk (0x200UL) |
SCUPM SYS_ISCLR: SYS_OT_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_SYS_OT_ISC_Pos (9UL) |
SCUPM SYS_ISCLR: SYS_OT_ISC (Bit 9)
#define SCUPM_SYS_ISCLR_SYS_OT_SC_Msk (0x2000000UL) |
SCUPM SYS_ISCLR: SYS_OT_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_SYS_OT_SC_Pos (25UL) |
SCUPM SYS_ISCLR: SYS_OT_SC (Bit 25)
#define SCUPM_SYS_ISCLR_SYS_OTWARN_ISC_Msk (0x100UL) |
SCUPM SYS_ISCLR: SYS_OTWARN_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_SYS_OTWARN_ISC_Pos (8UL) |
SCUPM SYS_ISCLR: SYS_OTWARN_ISC (Bit 8)
#define SCUPM_SYS_ISCLR_SYS_OTWARN_SC_Msk (0x1000000UL) |
SCUPM SYS_ISCLR: SYS_OTWARN_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_SYS_OTWARN_SC_Pos (24UL) |
SCUPM SYS_ISCLR: SYS_OTWARN_SC (Bit 24)
#define SCUPM_SYS_ISCLR_VREF1V2_OV_ISC_Msk (0x2000UL) |
SCUPM SYS_ISCLR: VREF1V2_OV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_VREF1V2_OV_ISC_Pos (13UL) |
SCUPM SYS_ISCLR: VREF1V2_OV_ISC (Bit 13)
#define SCUPM_SYS_ISCLR_VREF1V2_OV_SC_Msk (0x20000000UL) |
SCUPM SYS_ISCLR: VREF1V2_OV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_VREF1V2_OV_SC_Pos (29UL) |
SCUPM SYS_ISCLR: VREF1V2_OV_SC (Bit 29)
#define SCUPM_SYS_ISCLR_VREF1V2_UV_ISC_Msk (0x1000UL) |
SCUPM SYS_ISCLR: VREF1V2_UV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_VREF1V2_UV_ISC_Pos (12UL) |
SCUPM SYS_ISCLR: VREF1V2_UV_ISC (Bit 12)
#define SCUPM_SYS_ISCLR_VREF1V2_UV_SC_Msk (0x10000000UL) |
SCUPM SYS_ISCLR: VREF1V2_UV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_ISCLR_VREF1V2_UV_SC_Pos (28UL) |
SCUPM SYS_ISCLR: VREF1V2_UV_SC (Bit 28)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ISC_Msk (0x4000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ISC_Pos (14UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_ISC (Bit 14)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SC_Msk (0x40000000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SC_Pos (30UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_OV_SC (Bit 30)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ISC_Msk (0x40UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ISC_Pos (6UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_ISC (Bit 6)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SC_Msk (0x400000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SC_Pos (22UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD1V5_UV_SC (Bit 22)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ISC_Msk (0x1000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ISC_Pos (12UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_ISC (Bit 12)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SC_Msk (0x10000000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SC_Pos (28UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_OV_SC (Bit 28)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ISC_Msk (0x10UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ISC_Pos (4UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_ISC (Bit 4)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SC_Msk (0x100000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SC_Pos (20UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDD5V_UV_SC (Bit 20)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_ISC_Msk (0x800UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_OV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_ISC_Pos (11UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_OV_ISC (Bit 11)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_SC_Msk (0x8000000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_OV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_SC_Pos (27UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_OV_SC (Bit 27)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_ISC_Msk (0x8UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_UV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_ISC_Pos (3UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_UV_ISC (Bit 3)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_SC_Msk (0x80000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_UV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_SC_Pos (19UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VDDEXT_UV_SC (Bit 19)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ISC_Msk (0x100UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ISC_Pos (8UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_ISC (Bit 8)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SC_Msk (0x1000000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SC_Pos (24UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_OV_SC (Bit 24)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ISC_Msk (0x1UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_ISC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ISC_Pos (0UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_ISC (Bit 0)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SC_Msk (0x10000UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_SC (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SC_Pos (16UL) |
SCUPM SYS_SUPPLY_IRQ_CLR: VS_UV_SC (Bit 16)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Msk (0x4000UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Pos (14UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_OV_IE (Bit 14)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Msk (0x40UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Pos (6UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD1V5_UV_IE (Bit 6)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Msk (0x1000UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Pos (12UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_OV_IE (Bit 12)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Msk (0x10UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Pos (4UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDD5V_UV_IE (Bit 4)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_OV_IE_Msk (0x800UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDDEXT_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_OV_IE_Pos (11UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDDEXT_OV_IE (Bit 11)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_UV_IE_Msk (0x8UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDDEXT_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_UV_IE_Pos (3UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VDDEXT_UV_IE (Bit 3)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Msk (0x100UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_OV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Pos (8UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_OV_IE (Bit 8)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Msk (0x1UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_UV_IE (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Pos (0UL) |
SCUPM SYS_SUPPLY_IRQ_CTRL: VS_UV_IE (Bit 0)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Msk (0x4000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Pos (14UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_IS (Bit 14)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Msk (0x40000000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Pos (30UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_OV_STS (Bit 30)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Msk (0x40UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Pos (6UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_IS (Bit 6)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Msk (0x400000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Pos (22UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD1V5_UV_STS (Bit 22)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Msk (0x1000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Pos (12UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_IS (Bit 12)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Msk (0x10000000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Pos (28UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_OV_STS (Bit 28)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Msk (0x10UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Pos (4UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_IS (Bit 4)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Msk (0x100000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Pos (20UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDD5V_UV_STS (Bit 20)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_IS_Msk (0x800UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_IS_Pos (11UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_OV_IS (Bit 11)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_STS_Msk (0x8000000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_STS_Pos (27UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_OV_STS (Bit 27)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_IS_Msk (0x8UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_IS_Pos (3UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_UV_IS (Bit 3)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_STS_Msk (0x80000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_STS_Pos (19UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VDDEXT_UV_STS (Bit 19)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Msk (0x100UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Pos (8UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_IS (Bit 8)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Msk (0x1000000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Pos (24UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_OV_STS (Bit 24)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Msk (0x1UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_IS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Pos (0UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_IS (Bit 0)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Msk (0x10000UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_STS (Bitfield-Mask: 0x01)
#define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Pos (16UL) |
SCUPM SYS_SUPPLY_IRQ_STS: VS_UV_STS (Bit 16)
#define SCUPM_WDT1_TRIG_SOWCONF_Msk (0xc0UL) |
SCUPM WDT1_TRIG: SOWCONF (Bitfield-Mask: 0x03)
#define SCUPM_WDT1_TRIG_SOWCONF_Pos (6UL) |
SCUPM WDT1_TRIG: SOWCONF (Bit 6)
#define SCUPM_WDT1_TRIG_WDP_SEL_Msk (0x3fUL) |
SCUPM WDT1_TRIG: WDP_SEL (Bitfield-Mask: 0x3f)
#define SCUPM_WDT1_TRIG_WDP_SEL_Pos (0UL) |
SCUPM WDT1_TRIG: WDP_SEL (Bit 0)
#define SSC1_BR_BR_VALUE_Msk (0xffffUL) |
SSC1 BR: BR_VALUE (Bitfield-Mask: 0xffff)
#define SSC1_BR_BR_VALUE_Pos (0UL) |
SSC1 BR: BR_VALUE (Bit 0)
#define SSC1_CON_AREN_Msk (0x1000UL) |
SSC1 CON: AREN (Bitfield-Mask: 0x01)
#define SSC1_CON_AREN_Pos (12UL) |
SSC1 CON: AREN (Bit 12)
#define SSC1_CON_BC_Msk (0xf0000UL) |
SSC1 CON: BC (Bitfield-Mask: 0x0f)
#define SSC1_CON_BC_Pos (16UL) |
SSC1 CON: BC (Bit 16)
#define SSC1_CON_BE_Msk (0x8000000UL) |
SSC1 CON: BE (Bitfield-Mask: 0x01)
#define SSC1_CON_BE_Pos (27UL) |
SSC1 CON: BE (Bit 27)
#define SSC1_CON_BEN_Msk (0x800UL) |
SSC1 CON: BEN (Bitfield-Mask: 0x01)
#define SSC1_CON_BEN_Pos (11UL) |
SSC1 CON: BEN (Bit 11)
#define SSC1_CON_BM_Msk (0xfUL) |
SSC1 CON: BM (Bitfield-Mask: 0x0f)
#define SSC1_CON_BM_Pos (0UL) |
SSC1 CON: BM (Bit 0)
#define SSC1_CON_BSY_Msk (0x10000000UL) |
SSC1 CON: BSY (Bitfield-Mask: 0x01)
#define SSC1_CON_BSY_Pos (28UL) |
SSC1 CON: BSY (Bit 28)
#define SSC1_CON_EN_Msk (0x8000UL) |
SSC1 CON: EN (Bitfield-Mask: 0x01)
#define SSC1_CON_EN_Pos (15UL) |
SSC1 CON: EN (Bit 15)
#define SSC1_CON_HB_Msk (0x10UL) |
SSC1 CON: HB (Bitfield-Mask: 0x01)
#define SSC1_CON_HB_Pos (4UL) |
SSC1 CON: HB (Bit 4)
#define SSC1_CON_LB_Msk (0x80UL) |
SSC1 CON: LB (Bitfield-Mask: 0x01)
#define SSC1_CON_LB_Pos (7UL) |
SSC1 CON: LB (Bit 7)
#define SSC1_CON_MS_Msk (0x4000UL) |
SSC1 CON: MS (Bitfield-Mask: 0x01)
#define SSC1_CON_MS_Pos (14UL) |
SSC1 CON: MS (Bit 14)
#define SSC1_CON_PE_Msk (0x4000000UL) |
SSC1 CON: PE (Bitfield-Mask: 0x01)
#define SSC1_CON_PE_Pos (26UL) |
SSC1 CON: PE (Bit 26)
#define SSC1_CON_PEN_Msk (0x400UL) |
SSC1 CON: PEN (Bitfield-Mask: 0x01)
#define SSC1_CON_PEN_Pos (10UL) |
SSC1 CON: PEN (Bit 10)
#define SSC1_CON_PH_Msk (0x20UL) |
SSC1 CON: PH (Bitfield-Mask: 0x01)
#define SSC1_CON_PH_Pos (5UL) |
SSC1 CON: PH (Bit 5)
#define SSC1_CON_PO_Msk (0x40UL) |
SSC1 CON: PO (Bitfield-Mask: 0x01)
#define SSC1_CON_PO_Pos (6UL) |
SSC1 CON: PO (Bit 6)
#define SSC1_CON_RE_Msk (0x2000000UL) |
SSC1 CON: RE (Bitfield-Mask: 0x01)
#define SSC1_CON_RE_Pos (25UL) |
SSC1 CON: RE (Bit 25)
#define SSC1_CON_REN_Msk (0x200UL) |
SSC1 CON: REN (Bitfield-Mask: 0x01)
#define SSC1_CON_REN_Pos (9UL) |
SSC1 CON: REN (Bit 9)
#define SSC1_CON_TE_Msk (0x1000000UL) |
SSC1 CON: TE (Bitfield-Mask: 0x01)
#define SSC1_CON_TE_Pos (24UL) |
SSC1 CON: TE (Bit 24)
#define SSC1_CON_TEN_Msk (0x100UL) |
SSC1 CON: TEN (Bitfield-Mask: 0x01)
#define SSC1_CON_TEN_Pos (8UL) |
SSC1 CON: TEN (Bit 8)
#define SSC1_ISRCLR_BECLR_Msk (0x800UL) |
SSC1 ISRCLR: BECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_BECLR_Pos (11UL) |
SSC1 ISRCLR: BECLR (Bit 11)
#define SSC1_ISRCLR_PECLR_Msk (0x400UL) |
SSC1 ISRCLR: PECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_PECLR_Pos (10UL) |
SSC1 ISRCLR: PECLR (Bit 10)
#define SSC1_ISRCLR_RECLR_Msk (0x200UL) |
SSC1 ISRCLR: RECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_RECLR_Pos (9UL) |
SSC1 ISRCLR: RECLR (Bit 9)
#define SSC1_ISRCLR_TECLR_Msk (0x100UL) |
SSC1 ISRCLR: TECLR (Bitfield-Mask: 0x01)
#define SSC1_ISRCLR_TECLR_Pos (8UL) |
SSC1 ISRCLR: TECLR (Bit 8)
#define SSC1_PISEL_CIS_Msk (0x4UL) |
SSC1 PISEL: CIS (Bitfield-Mask: 0x01)
#define SSC1_PISEL_CIS_Pos (2UL) |
SSC1 PISEL: CIS (Bit 2)
#define SSC1_PISEL_GIS_Msk (0x10UL) |
SSC1 PISEL: GIS (Bitfield-Mask: 0x01)
#define SSC1_PISEL_GIS_Pos (4UL) |
SSC1 PISEL: GIS (Bit 4)
#define SSC1_PISEL_MIS_0_Msk (0x1UL) |
SSC1 PISEL: MIS_0 (Bitfield-Mask: 0x01)
#define SSC1_PISEL_MIS_0_Pos (0UL) |
SSC1 PISEL: MIS_0 (Bit 0)
#define SSC1_PISEL_MIS_1_Msk (0x8UL) |
SSC1 PISEL: MIS_1 (Bitfield-Mask: 0x01)
#define SSC1_PISEL_MIS_1_Pos (3UL) |
SSC1 PISEL: MIS_1 (Bit 3)
#define SSC1_PISEL_SIS_Msk (0x2UL) |
SSC1 PISEL: SIS (Bitfield-Mask: 0x01)
#define SSC1_PISEL_SIS_Pos (1UL) |
SSC1 PISEL: SIS (Bit 1)
#define SSC1_RB_RB_VALUE_Msk (0xffffUL) |
SSC1 RB: RB_VALUE (Bitfield-Mask: 0xffff)
#define SSC1_RB_RB_VALUE_Pos (0UL) |
SSC1 RB: RB_VALUE (Bit 0)
#define SSC1_TB_TB_VALUE_Msk (0xffffUL) |
SSC1 TB: TB_VALUE (Bitfield-Mask: 0xffff)
#define SSC1_TB_TB_VALUE_Pos (0UL) |
SSC1 TB: TB_VALUE (Bit 0)
#define SSC2_BR_BR_VALUE_Msk (0xffffUL) |
SSC2 BR: BR_VALUE (Bitfield-Mask: 0xffff)
#define SSC2_BR_BR_VALUE_Pos (0UL) |
SSC2 BR: BR_VALUE (Bit 0)
#define SSC2_CON_AREN_Msk (0x1000UL) |
SSC2 CON: AREN (Bitfield-Mask: 0x01)
#define SSC2_CON_AREN_Pos (12UL) |
SSC2 CON: AREN (Bit 12)
#define SSC2_CON_BC_Msk (0xf0000UL) |
SSC2 CON: BC (Bitfield-Mask: 0x0f)
#define SSC2_CON_BC_Pos (16UL) |
SSC2 CON: BC (Bit 16)
#define SSC2_CON_BE_Msk (0x8000000UL) |
SSC2 CON: BE (Bitfield-Mask: 0x01)
#define SSC2_CON_BE_Pos (27UL) |
SSC2 CON: BE (Bit 27)
#define SSC2_CON_BEN_Msk (0x800UL) |
SSC2 CON: BEN (Bitfield-Mask: 0x01)
#define SSC2_CON_BEN_Pos (11UL) |
SSC2 CON: BEN (Bit 11)
#define SSC2_CON_BM_Msk (0xfUL) |
SSC2 CON: BM (Bitfield-Mask: 0x0f)
#define SSC2_CON_BM_Pos (0UL) |
SSC2 CON: BM (Bit 0)
#define SSC2_CON_BSY_Msk (0x10000000UL) |
SSC2 CON: BSY (Bitfield-Mask: 0x01)
#define SSC2_CON_BSY_Pos (28UL) |
SSC2 CON: BSY (Bit 28)
#define SSC2_CON_EN_Msk (0x8000UL) |
SSC2 CON: EN (Bitfield-Mask: 0x01)
#define SSC2_CON_EN_Pos (15UL) |
SSC2 CON: EN (Bit 15)
#define SSC2_CON_HB_Msk (0x10UL) |
SSC2 CON: HB (Bitfield-Mask: 0x01)
#define SSC2_CON_HB_Pos (4UL) |
SSC2 CON: HB (Bit 4)
#define SSC2_CON_LB_Msk (0x80UL) |
SSC2 CON: LB (Bitfield-Mask: 0x01)
#define SSC2_CON_LB_Pos (7UL) |
SSC2 CON: LB (Bit 7)
#define SSC2_CON_MS_Msk (0x4000UL) |
SSC2 CON: MS (Bitfield-Mask: 0x01)
#define SSC2_CON_MS_Pos (14UL) |
SSC2 CON: MS (Bit 14)
#define SSC2_CON_PE_Msk (0x4000000UL) |
SSC2 CON: PE (Bitfield-Mask: 0x01)
#define SSC2_CON_PE_Pos (26UL) |
SSC2 CON: PE (Bit 26)
#define SSC2_CON_PEN_Msk (0x400UL) |
SSC2 CON: PEN (Bitfield-Mask: 0x01)
#define SSC2_CON_PEN_Pos (10UL) |
SSC2 CON: PEN (Bit 10)
#define SSC2_CON_PH_Msk (0x20UL) |
SSC2 CON: PH (Bitfield-Mask: 0x01)
#define SSC2_CON_PH_Pos (5UL) |
SSC2 CON: PH (Bit 5)
#define SSC2_CON_PO_Msk (0x40UL) |
SSC2 CON: PO (Bitfield-Mask: 0x01)
#define SSC2_CON_PO_Pos (6UL) |
SSC2 CON: PO (Bit 6)
#define SSC2_CON_RE_Msk (0x2000000UL) |
SSC2 CON: RE (Bitfield-Mask: 0x01)
#define SSC2_CON_RE_Pos (25UL) |
SSC2 CON: RE (Bit 25)
#define SSC2_CON_REN_Msk (0x200UL) |
SSC2 CON: REN (Bitfield-Mask: 0x01)
#define SSC2_CON_REN_Pos (9UL) |
SSC2 CON: REN (Bit 9)
#define SSC2_CON_TE_Msk (0x1000000UL) |
SSC2 CON: TE (Bitfield-Mask: 0x01)
#define SSC2_CON_TE_Pos (24UL) |
SSC2 CON: TE (Bit 24)
#define SSC2_CON_TEN_Msk (0x100UL) |
SSC2 CON: TEN (Bitfield-Mask: 0x01)
#define SSC2_CON_TEN_Pos (8UL) |
SSC2 CON: TEN (Bit 8)
#define SSC2_ISRCLR_BECLR_Msk (0x800UL) |
SSC2 ISRCLR: BECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_BECLR_Pos (11UL) |
SSC2 ISRCLR: BECLR (Bit 11)
#define SSC2_ISRCLR_PECLR_Msk (0x400UL) |
SSC2 ISRCLR: PECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_PECLR_Pos (10UL) |
SSC2 ISRCLR: PECLR (Bit 10)
#define SSC2_ISRCLR_RECLR_Msk (0x200UL) |
SSC2 ISRCLR: RECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_RECLR_Pos (9UL) |
SSC2 ISRCLR: RECLR (Bit 9)
#define SSC2_ISRCLR_TECLR_Msk (0x100UL) |
SSC2 ISRCLR: TECLR (Bitfield-Mask: 0x01)
#define SSC2_ISRCLR_TECLR_Pos (8UL) |
SSC2 ISRCLR: TECLR (Bit 8)
#define SSC2_PISEL_CIS_Msk (0x4UL) |
SSC2 PISEL: CIS (Bitfield-Mask: 0x01)
#define SSC2_PISEL_CIS_Pos (2UL) |
SSC2 PISEL: CIS (Bit 2)
#define SSC2_PISEL_GIS_Msk (0x10UL) |
SSC2 PISEL: GIS (Bitfield-Mask: 0x01)
#define SSC2_PISEL_GIS_Pos (4UL) |
SSC2 PISEL: GIS (Bit 4)
#define SSC2_PISEL_MIS_0_Msk (0x1UL) |
SSC2 PISEL: MIS_0 (Bitfield-Mask: 0x01)
#define SSC2_PISEL_MIS_0_Pos (0UL) |
SSC2 PISEL: MIS_0 (Bit 0)
#define SSC2_PISEL_MIS_1_Msk (0x8UL) |
SSC2 PISEL: MIS_1 (Bitfield-Mask: 0x01)
#define SSC2_PISEL_MIS_1_Pos (3UL) |
SSC2 PISEL: MIS_1 (Bit 3)
#define SSC2_PISEL_SIS_Msk (0x2UL) |
SSC2 PISEL: SIS (Bitfield-Mask: 0x01)
#define SSC2_PISEL_SIS_Pos (1UL) |
SSC2 PISEL: SIS (Bit 1)
#define SSC2_RB_RB_VALUE_Msk (0xffffUL) |
SSC2 RB: RB_VALUE (Bitfield-Mask: 0xffff)
#define SSC2_RB_RB_VALUE_Pos (0UL) |
SSC2 RB: RB_VALUE (Bit 0)
#define SSC2_TB_TB_VALUE_Msk (0xffffUL) |
SSC2 TB: TB_VALUE (Bitfield-Mask: 0xffff)
#define SSC2_TB_TB_VALUE_Pos (0UL) |
SSC2 TB: TB_VALUE (Bit 0)
#define TIMER21_CNT_T2H_Msk (0xff00UL) |
TIMER21 CNT: T2H (Bitfield-Mask: 0xff)
#define TIMER21_CNT_T2H_Pos (8UL) |
TIMER21 CNT: T2H (Bit 8)
#define TIMER21_CNT_T2L_Msk (0xffUL) |
TIMER21 CNT: T2L (Bitfield-Mask: 0xff)
#define TIMER21_CNT_T2L_Pos (0UL) |
TIMER21 CNT: T2L (Bit 0)
#define TIMER21_CON1_EXF2EN_Msk (0x1UL) |
TIMER21 CON1: EXF2EN (Bitfield-Mask: 0x01)
#define TIMER21_CON1_EXF2EN_Pos (0UL) |
TIMER21 CON1: EXF2EN (Bit 0)
#define TIMER21_CON1_TF2EN_Msk (0x2UL) |
TIMER21 CON1: TF2EN (Bitfield-Mask: 0x01)
#define TIMER21_CON1_TF2EN_Pos (1UL) |
TIMER21 CON1: TF2EN (Bit 1)
#define TIMER21_CON_C_T2_Msk (0x2UL) |
TIMER21 CON: C_T2 (Bitfield-Mask: 0x01)
#define TIMER21_CON_C_T2_Pos (1UL) |
TIMER21 CON: C_T2 (Bit 1)
#define TIMER21_CON_CP_RL2_Msk (0x1UL) |
TIMER21 CON: CP_RL2 (Bitfield-Mask: 0x01)
#define TIMER21_CON_CP_RL2_Pos (0UL) |
TIMER21 CON: CP_RL2 (Bit 0)
#define TIMER21_CON_EXEN2_Msk (0x8UL) |
TIMER21 CON: EXEN2 (Bitfield-Mask: 0x01)
#define TIMER21_CON_EXEN2_Pos (3UL) |
TIMER21 CON: EXEN2 (Bit 3)
#define TIMER21_CON_EXF2_Msk (0x40UL) |
TIMER21 CON: EXF2 (Bitfield-Mask: 0x01)
#define TIMER21_CON_EXF2_Pos (6UL) |
TIMER21 CON: EXF2 (Bit 6)
#define TIMER21_CON_TF2_Msk (0x80UL) |
TIMER21 CON: TF2 (Bitfield-Mask: 0x01)
#define TIMER21_CON_TF2_Pos (7UL) |
TIMER21 CON: TF2 (Bit 7)
#define TIMER21_CON_TR2_Msk (0x4UL) |
TIMER21 CON: TR2 (Bitfield-Mask: 0x01)
#define TIMER21_CON_TR2_Pos (2UL) |
TIMER21 CON: TR2 (Bit 2)
#define TIMER21_ICLR_EXF2CLR_Msk (0x40UL) |
TIMER21 ICLR: EXF2CLR (Bitfield-Mask: 0x01)
#define TIMER21_ICLR_EXF2CLR_Pos (6UL) |
TIMER21 ICLR: EXF2CLR (Bit 6)
#define TIMER21_ICLR_TF2CLR_Msk (0x80UL) |
TIMER21 ICLR: TF2CLR (Bitfield-Mask: 0x01)
#define TIMER21_ICLR_TF2CLR_Pos (7UL) |
TIMER21 ICLR: TF2CLR (Bit 7)
#define TIMER21_MOD_DCEN_Msk (0x1UL) |
TIMER21 MOD: DCEN (Bitfield-Mask: 0x01)
#define TIMER21_MOD_DCEN_Pos (0UL) |
TIMER21 MOD: DCEN (Bit 0)
#define TIMER21_MOD_EDGESEL_Msk (0x20UL) |
TIMER21 MOD: EDGESEL (Bitfield-Mask: 0x01)
#define TIMER21_MOD_EDGESEL_Pos (5UL) |
TIMER21 MOD: EDGESEL (Bit 5)
#define TIMER21_MOD_PREN_Msk (0x10UL) |
TIMER21 MOD: PREN (Bitfield-Mask: 0x01)
#define TIMER21_MOD_PREN_Pos (4UL) |
TIMER21 MOD: PREN (Bit 4)
#define TIMER21_MOD_T2PRE_Msk (0xeUL) |
TIMER21 MOD: T2PRE (Bitfield-Mask: 0x07)
#define TIMER21_MOD_T2PRE_Pos (1UL) |
TIMER21 MOD: T2PRE (Bit 1)
#define TIMER21_MOD_T2REGS_Msk (0x80UL) |
TIMER21 MOD: T2REGS (Bitfield-Mask: 0x01)
#define TIMER21_MOD_T2REGS_Pos (7UL) |
TIMER21 MOD: T2REGS (Bit 7)
#define TIMER21_MOD_T2RHEN_Msk (0x40UL) |
TIMER21 MOD: T2RHEN (Bitfield-Mask: 0x01)
#define TIMER21_MOD_T2RHEN_Pos (6UL) |
TIMER21 MOD: T2RHEN (Bit 6)
#define TIMER21_RC_RCH2_Msk (0xff00UL) |
TIMER21 RC: RCH2 (Bitfield-Mask: 0xff)
#define TIMER21_RC_RCH2_Pos (8UL) |
TIMER21 RC: RCH2 (Bit 8)
#define TIMER21_RC_RCL2_Msk (0xffUL) |
TIMER21 RC: RCL2 (Bitfield-Mask: 0xff)
#define TIMER21_RC_RCL2_Pos (0UL) |
TIMER21 RC: RCL2 (Bit 0)
#define TIMER2_CNT_T2H_Msk (0xff00UL) |
TIMER2 CNT: T2H (Bitfield-Mask: 0xff)
#define TIMER2_CNT_T2H_Pos (8UL) |
TIMER2 CNT: T2H (Bit 8)
#define TIMER2_CNT_T2L_Msk (0xffUL) |
TIMER2 CNT: T2L (Bitfield-Mask: 0xff)
#define TIMER2_CNT_T2L_Pos (0UL) |
TIMER2 CNT: T2L (Bit 0)
#define TIMER2_CON1_EXF2EN_Msk (0x1UL) |
TIMER2 CON1: EXF2EN (Bitfield-Mask: 0x01)
#define TIMER2_CON1_EXF2EN_Pos (0UL) |
TIMER2 CON1: EXF2EN (Bit 0)
#define TIMER2_CON1_TF2EN_Msk (0x2UL) |
TIMER2 CON1: TF2EN (Bitfield-Mask: 0x01)
#define TIMER2_CON1_TF2EN_Pos (1UL) |
TIMER2 CON1: TF2EN (Bit 1)
#define TIMER2_CON_C_T2_Msk (0x2UL) |
TIMER2 CON: C_T2 (Bitfield-Mask: 0x01)
#define TIMER2_CON_C_T2_Pos (1UL) |
TIMER2 CON: C_T2 (Bit 1)
#define TIMER2_CON_CP_RL2_Msk (0x1UL) |
TIMER2 CON: CP_RL2 (Bitfield-Mask: 0x01)
#define TIMER2_CON_CP_RL2_Pos (0UL) |
TIMER2 CON: CP_RL2 (Bit 0)
#define TIMER2_CON_EXEN2_Msk (0x8UL) |
TIMER2 CON: EXEN2 (Bitfield-Mask: 0x01)
#define TIMER2_CON_EXEN2_Pos (3UL) |
TIMER2 CON: EXEN2 (Bit 3)
#define TIMER2_CON_EXF2_Msk (0x40UL) |
TIMER2 CON: EXF2 (Bitfield-Mask: 0x01)
#define TIMER2_CON_EXF2_Pos (6UL) |
TIMER2 CON: EXF2 (Bit 6)
#define TIMER2_CON_TF2_Msk (0x80UL) |
TIMER2 CON: TF2 (Bitfield-Mask: 0x01)
#define TIMER2_CON_TF2_Pos (7UL) |
TIMER2 CON: TF2 (Bit 7)
#define TIMER2_CON_TR2_Msk (0x4UL) |
TIMER2 CON: TR2 (Bitfield-Mask: 0x01)
#define TIMER2_CON_TR2_Pos (2UL) |
TIMER2 CON: TR2 (Bit 2)
#define TIMER2_ICLR_EXF2CLR_Msk (0x40UL) |
TIMER2 ICLR: EXF2CLR (Bitfield-Mask: 0x01)
#define TIMER2_ICLR_EXF2CLR_Pos (6UL) |
TIMER2 ICLR: EXF2CLR (Bit 6)
#define TIMER2_ICLR_TF2CLR_Msk (0x80UL) |
TIMER2 ICLR: TF2CLR (Bitfield-Mask: 0x01)
#define TIMER2_ICLR_TF2CLR_Pos (7UL) |
TIMER2 ICLR: TF2CLR (Bit 7)
#define TIMER2_MOD_DCEN_Msk (0x1UL) |
TIMER2 MOD: DCEN (Bitfield-Mask: 0x01)
#define TIMER2_MOD_DCEN_Pos (0UL) |
TIMER2 MOD: DCEN (Bit 0)
#define TIMER2_MOD_EDGESEL_Msk (0x20UL) |
TIMER2 MOD: EDGESEL (Bitfield-Mask: 0x01)
#define TIMER2_MOD_EDGESEL_Pos (5UL) |
TIMER2 MOD: EDGESEL (Bit 5)
#define TIMER2_MOD_PREN_Msk (0x10UL) |
TIMER2 MOD: PREN (Bitfield-Mask: 0x01)
#define TIMER2_MOD_PREN_Pos (4UL) |
TIMER2 MOD: PREN (Bit 4)
#define TIMER2_MOD_T2PRE_Msk (0xeUL) |
TIMER2 MOD: T2PRE (Bitfield-Mask: 0x07)
#define TIMER2_MOD_T2PRE_Pos (1UL) |
TIMER2 MOD: T2PRE (Bit 1)
#define TIMER2_MOD_T2REGS_Msk (0x80UL) |
TIMER2 MOD: T2REGS (Bitfield-Mask: 0x01)
#define TIMER2_MOD_T2REGS_Pos (7UL) |
TIMER2 MOD: T2REGS (Bit 7)
#define TIMER2_MOD_T2RHEN_Msk (0x40UL) |
TIMER2 MOD: T2RHEN (Bitfield-Mask: 0x01)
#define TIMER2_MOD_T2RHEN_Pos (6UL) |
TIMER2 MOD: T2RHEN (Bit 6)
#define TIMER2_RC_RCH2_Msk (0xff00UL) |
TIMER2 RC: RCH2 (Bitfield-Mask: 0xff)
#define TIMER2_RC_RCH2_Pos (8UL) |
TIMER2 RC: RCH2 (Bit 8)
#define TIMER2_RC_RCL2_Msk (0xffUL) |
TIMER2 RC: RCL2 (Bitfield-Mask: 0xff)
#define TIMER2_RC_RCL2_Pos (0UL) |
TIMER2 RC: RCL2 (Bit 0)
#define UART1_SBUF_VAL_Msk (0xffUL) |
UART1 SBUF: VAL (Bitfield-Mask: 0xff)
#define UART1_SBUF_VAL_Pos (0UL) |
UART1 SBUF: VAL (Bit 0)
#define UART1_SCON_RB8_Msk (0x4UL) |
UART1 SCON: RB8 (Bitfield-Mask: 0x01)
#define UART1_SCON_RB8_Pos (2UL) |
UART1 SCON: RB8 (Bit 2)
#define UART1_SCON_REN_Msk (0x10UL) |
UART1 SCON: REN (Bitfield-Mask: 0x01)
#define UART1_SCON_REN_Pos (4UL) |
UART1 SCON: REN (Bit 4)
#define UART1_SCON_RI_Msk (0x1UL) |
UART1 SCON: RI (Bitfield-Mask: 0x01)
#define UART1_SCON_RI_Pos (0UL) |
UART1 SCON: RI (Bit 0)
#define UART1_SCON_SM0_Msk (0x80UL) |
UART1 SCON: SM0 (Bitfield-Mask: 0x01)
#define UART1_SCON_SM0_Pos (7UL) |
UART1 SCON: SM0 (Bit 7)
#define UART1_SCON_SM1_Msk (0x40UL) |
UART1 SCON: SM1 (Bitfield-Mask: 0x01)
#define UART1_SCON_SM1_Pos (6UL) |
UART1 SCON: SM1 (Bit 6)
#define UART1_SCON_SM2_Msk (0x20UL) |
UART1 SCON: SM2 (Bitfield-Mask: 0x01)
#define UART1_SCON_SM2_Pos (5UL) |
UART1 SCON: SM2 (Bit 5)
#define UART1_SCON_TB8_Msk (0x8UL) |
UART1 SCON: TB8 (Bitfield-Mask: 0x01)
#define UART1_SCON_TB8_Pos (3UL) |
UART1 SCON: TB8 (Bit 3)
#define UART1_SCON_TI_Msk (0x2UL) |
UART1 SCON: TI (Bitfield-Mask: 0x01)
#define UART1_SCON_TI_Pos (1UL) |
UART1 SCON: TI (Bit 1)
#define UART1_SCONCLR_RB8CLR_Msk (0x4UL) |
UART1 SCONCLR: RB8CLR (Bitfield-Mask: 0x01)
#define UART1_SCONCLR_RB8CLR_Pos (2UL) |
UART1 SCONCLR: RB8CLR (Bit 2)
#define UART1_SCONCLR_RICLR_Msk (0x1UL) |
UART1 SCONCLR: RICLR (Bitfield-Mask: 0x01)
#define UART1_SCONCLR_RICLR_Pos (0UL) |
UART1 SCONCLR: RICLR (Bit 0)
#define UART1_SCONCLR_TICLR_Msk (0x2UL) |
UART1 SCONCLR: TICLR (Bitfield-Mask: 0x01)
#define UART1_SCONCLR_TICLR_Pos (1UL) |
UART1 SCONCLR: TICLR (Bit 1)
#define UART2_SBUF_VAL_Msk (0xffUL) |
UART2 SBUF: VAL (Bitfield-Mask: 0xff)
#define UART2_SBUF_VAL_Pos (0UL) |
UART2 SBUF: VAL (Bit 0)
#define UART2_SCON_RB8_Msk (0x4UL) |
UART2 SCON: RB8 (Bitfield-Mask: 0x01)
#define UART2_SCON_RB8_Pos (2UL) |
UART2 SCON: RB8 (Bit 2)
#define UART2_SCON_REN_Msk (0x10UL) |
UART2 SCON: REN (Bitfield-Mask: 0x01)
#define UART2_SCON_REN_Pos (4UL) |
UART2 SCON: REN (Bit 4)
#define UART2_SCON_RI_Msk (0x1UL) |
UART2 SCON: RI (Bitfield-Mask: 0x01)
#define UART2_SCON_RI_Pos (0UL) |
UART2 SCON: RI (Bit 0)
#define UART2_SCON_SM0_Msk (0x80UL) |
UART2 SCON: SM0 (Bitfield-Mask: 0x01)
#define UART2_SCON_SM0_Pos (7UL) |
UART2 SCON: SM0 (Bit 7)
#define UART2_SCON_SM1_Msk (0x40UL) |
UART2 SCON: SM1 (Bitfield-Mask: 0x01)
#define UART2_SCON_SM1_Pos (6UL) |
UART2 SCON: SM1 (Bit 6)
#define UART2_SCON_SM2_Msk (0x20UL) |
UART2 SCON: SM2 (Bitfield-Mask: 0x01)
#define UART2_SCON_SM2_Pos (5UL) |
UART2 SCON: SM2 (Bit 5)
#define UART2_SCON_TB8_Msk (0x8UL) |
UART2 SCON: TB8 (Bitfield-Mask: 0x01)
#define UART2_SCON_TB8_Pos (3UL) |
UART2 SCON: TB8 (Bit 3)
#define UART2_SCON_TI_Msk (0x2UL) |
UART2 SCON: TI (Bitfield-Mask: 0x01)
#define UART2_SCON_TI_Pos (1UL) |
UART2 SCON: TI (Bit 1)
#define UART2_SCONCLR_RB8CLR_Msk (0x4UL) |
UART2 SCONCLR: RB8CLR (Bitfield-Mask: 0x01)
#define UART2_SCONCLR_RB8CLR_Pos (2UL) |
UART2 SCONCLR: RB8CLR (Bit 2)
#define UART2_SCONCLR_RICLR_Msk (0x1UL) |
UART2 SCONCLR: RICLR (Bitfield-Mask: 0x01)
#define UART2_SCONCLR_RICLR_Pos (0UL) |
UART2 SCONCLR: RICLR (Bit 0)
#define UART2_SCONCLR_TICLR_Msk (0x2UL) |
UART2 SCONCLR: TICLR (Bitfield-Mask: 0x01)
#define UART2_SCONCLR_TICLR_Pos (1UL) |
UART2 SCONCLR: TICLR (Bit 1)