Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields
ADC2_Type Struct Reference

Detailed Description

ADC2 (ADC2)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PD_N: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   SOS: 1
 
      __IM uint32_t   EOC: 1
 
      __IOM uint32_t   IN_MUX_SEL: 4
 
   }   bit
 
CTRL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   SQ_FB: 4
 
      __IM   uint32_t: 4
 
      __IM uint32_t   SQ_STOP: 1
 
      __IM uint32_t   EIM_ACTIVE: 1
 
      __IM uint32_t   SQx: 4
 
      __IM uint32_t   CHx: 4
 
   }   bit
 
SQ_FB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CHx_SEL: 4
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   REP: 3
 
      __IOM uint32_t   EN: 1
 
      __IOM uint32_t   SEL: 1
 
   }   bit
 
CHx_EIM
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MAX_TIME: 8
 
   }   bit
 
MAX_TIME
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALIB_EN_8_0: 9
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MCM_PD_N: 1
 
      __IM   uint32_t: 6
 
      __IM uint32_t   MCM_RDY: 1
 
      __IOM uint32_t   SAMPLE_TIME_int: 4
 
   }   bit
 
CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FILT_OUT_SEL_8_0: 9
 
   }   bit
 
CTRL4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ0: 9
 
      __IM   uint32_t: 7
 
      __IOM uint32_t   SQ1: 9
 
   }   bit
 
SQ0_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ4: 9
 
      __IM   uint32_t: 7
 
      __IOM uint32_t   SQ5: 9
 
   }   bit
 
SQ4_5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ2: 9
 
      __IM   uint32_t: 7
 
      __IOM uint32_t   SQ3: 9
 
   }   bit
 
SQ2_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ6: 9
 
      __IM   uint32_t: 7
 
      __IOM uint32_t   SQ7: 9
 
   }   bit
 
SQ6_7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ8: 9
 
   }   bit
 
SQ8_9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH0: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   GAIN_CH0: 8
 
      __IOM uint32_t   OFFS_CH1: 5
 
      __IOM uint32_t   GAIN_CH1: 8
 
   }   bit
 
CAL_CH0_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH2: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   GAIN_CH2: 8
 
      __IOM uint32_t   OFFS_CH3: 5
 
      __IOM uint32_t   GAIN_CH3: 8
 
   }   bit
 
CAL_CH2_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH4: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   GAIN_CH4: 8
 
      __IOM uint32_t   OFFS_CH5: 5
 
      __IOM uint32_t   GAIN_CH5: 8
 
   }   bit
 
CAL_CH4_5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH6: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   GAIN_CH6: 8
 
      __IOM uint32_t   OFFS_CH7: 5
 
      __IOM uint32_t   GAIN_CH7: 8
 
   }   bit
 
CAL_CH6_7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFS_CH8: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   GAIN_CH8: 8
 
   }   bit
 
CAL_CH8_9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   A_CH0: 2
 
      __IOM uint32_t   A_CH1: 2
 
      __IOM uint32_t   A_CH2: 2
 
      __IOM uint32_t   A_CH3: 2
 
      __IOM uint32_t   A_CH4: 2
 
      __IOM uint32_t   A_CH5: 2
 
      __IOM uint32_t   A_CH6: 2
 
      __IOM uint32_t   A_CH7: 2
 
      __IOM uint32_t   A_CH8: 2
 
   }   bit
 
FILTCOEFF0_8
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH0: 10
 
   }   bit
 
FILT_OUT0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH1: 10
 
   }   bit
 
FILT_OUT1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH2: 10
 
   }   bit
 
FILT_OUT2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH3: 10
 
   }   bit
 
FILT_OUT3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH4: 10
 
   }   bit
 
FILT_OUT4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH5: 10
 
   }   bit
 
FILT_OUT5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH6: 10
 
   }   bit
 
FILT_OUT6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH7: 10
 
   }   bit
 
FILT_OUT7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   OUT_CH8: 10
 
   }   bit
 
FILT_OUT8
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   UPLOEN_Ch0: 1
 
      __IOM uint32_t   UPLOEN_Ch1: 1
 
      __IOM uint32_t   UPLOEN_Ch2: 1
 
      __IOM uint32_t   UPLOEN_Ch3: 1
 
      __IOM uint32_t   UPLOEN_Ch4: 1
 
      __IOM uint32_t   UPLOEN_Ch5: 1
 
      __IOM uint32_t   UPLOEN_Ch6: 1
 
      __IOM uint32_t   UPLOEN_Ch7: 1
 
      __IOM uint32_t   UPLOEN_Ch8: 1
 
   }   bit
 
FILT_UPLO_CTRL
 
__IM uint32_t RESERVED3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   THLO_CH0: 8
 
      __IOM uint32_t   THLO_CH1: 8
 
      __IOM uint32_t   THLO_CH2: 8
 
      __IOM uint32_t   THLO_CH3: 8
 
   }   bit
 
TH0_3_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   THLO_CH4: 8
 
      __IOM uint32_t   THLO_CH5: 8
 
      __IOM uint32_t   THLO_CH6: 8
 
      __IOM uint32_t   THLO_CH7: 8
 
   }   bit
 
TH4_7_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   THLO_CH8: 8
 
   }   bit
 
TH8_11_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   THUP_CH0: 8
 
      __IOM uint32_t   THUP_CH1: 8
 
      __IOM uint32_t   THUP_CH2: 8
 
      __IOM uint32_t   THUP_CH3: 8
 
   }   bit
 
TH0_3_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   THUP_CH4: 8
 
      __IOM uint32_t   THUP_CH5: 8
 
      __IOM uint32_t   THUP_CH6: 8
 
      __IOM uint32_t   THUP_CH7: 8
 
   }   bit
 
TH4_7_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   THUP_CH8: 8
 
   }   bit
 
TH8_11_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_CH0: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_LO_CH0: 2
 
      __IOM uint32_t   CNT_LO_CH1: 2
 
      __IOM uint32_t   HYST_LO_CH1: 2
 
      __IOM uint32_t   CNT_LO_CH2: 2
 
      __IOM uint32_t   HYST_LO_CH2: 2
 
      __IOM uint32_t   CNT_LO_CH3: 2
 
      __IOM uint32_t   HYST_LO_CH3: 2
 
   }   bit
 
CNT0_3_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_CH4: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_LO_CH4: 2
 
      __IOM uint32_t   CNT_LO_CH5: 2
 
      __IOM uint32_t   HYST_LO_CH5: 2
 
      __IOM uint32_t   CNT_LO_CH6: 2
 
      __IOM uint32_t   HYST_LO_CH6: 2
 
      __IOM uint32_t   CNT_LO_CH7: 2
 
      __IOM uint32_t   HYST_LO_CH7: 2
 
   }   bit
 
CNT4_7_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_CH8: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_LO_CH8: 2
 
   }   bit
 
CNT8_11_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_CH0: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_UP_CH0: 2
 
      __IOM uint32_t   CNT_UP_CH1: 2
 
      __IOM uint32_t   HYST_UP_CH1: 2
 
      __IOM uint32_t   CNT_UP_CH2: 2
 
      __IOM uint32_t   HYST_UP_CH2: 2
 
      __IOM uint32_t   CNT_UP_CH3: 2
 
      __IOM uint32_t   HYST_UP_CH3: 2
 
   }   bit
 
CNT0_3_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_CH4: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_UP_CH4: 2
 
      __IOM uint32_t   CNT_UP_CH5: 2
 
      __IOM uint32_t   HYST_UP_CH5: 2
 
      __IOM uint32_t   CNT_UP_CH6: 2
 
      __IOM uint32_t   HYST_UP_CH6: 2
 
      __IOM uint32_t   CNT_UP_CH7: 2
 
      __IOM uint32_t   HYST_UP_CH7: 2
 
   }   bit
 
CNT4_7_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_CH8: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_UP_CH8: 2
 
   }   bit
 
CNT8_11_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MSEL_Ch0: 2
 
      __IOM uint32_t   MSEL_Ch1: 2
 
      __IOM uint32_t   MSEL_Ch2: 2
 
      __IOM uint32_t   MSEL_Ch3: 2
 
      __IOM uint32_t   MSEL_Ch4: 2
 
      __IOM uint32_t   MSEL_Ch5: 2
 
      __IOM uint32_t   MSEL_Ch6: 2
 
      __IOM uint32_t   MSEL_Ch7: 2
 
      __IOM uint32_t   MSEL_Ch8: 2
 
   }   bit
 
MMODE0_8
 
__IM uint32_t RESERVED4 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IM uint32_t   READY: 1
 
   }   bit
 
STATUS
 

Field Documentation

◆ A_CH0

__IOM uint32_t A_CH0

[1..0] Filter Coefficient A for ADC channel 0

◆ A_CH1

__IOM uint32_t A_CH1

[3..2] Filter Coefficient A for ADC channel 1

◆ A_CH2

__IOM uint32_t A_CH2

[5..4] Filter Coefficient A for ADC channel 2

◆ A_CH3

__IOM uint32_t A_CH3

[7..6] Filter Coefficient A for ADC channel 3

◆ A_CH4

__IOM uint32_t A_CH4

[9..8] Filter Coefficient A for ADC channel 4

◆ A_CH5

__IOM uint32_t A_CH5

[11..10] Filter Coefficient A for ADC channel 5

◆ A_CH6

__IOM uint32_t A_CH6

[13..12] Filter Coefficient A for ADC channel 6

◆ A_CH7

__IOM uint32_t A_CH7

[15..14] Filter Coefficient A for ADC channel 7

◆ A_CH8

__IOM uint32_t A_CH8

[17..16] Filter Coefficient A for ADC channel 8

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◆ 

union { ... } CAL_CH0_1

◆ 

union { ... } CAL_CH2_3

◆ 

union { ... } CAL_CH4_5

◆ 

union { ... } CAL_CH6_7

◆ 

union { ... } CAL_CH8_9

◆ CALIB_EN_8_0

__IOM uint32_t CALIB_EN_8_0

[8..0] Calibration Enable for Channels 8 to 0

◆ CHx

[19..16] Current active ADC2 Channel (in normal mode)

◆ 

union { ... } CHx_EIM

◆ CHx_SEL

__IOM uint32_t CHx_SEL

[3..0] Channel set for exceptional interrupt measurement (EIM)

◆ 

union { ... } CNT0_3_LOWER

◆ 

union { ... } CNT0_3_UPPER

◆ 

union { ... } CNT4_7_LOWER

◆ 

union { ... } CNT4_7_UPPER

◆ 

union { ... } CNT8_11_LOWER

◆ 

union { ... } CNT8_11_UPPER

◆ CNT_LO_CH0

__IOM uint32_t CNT_LO_CH0

[1..0] Lower timer trigger threshold channel 0

◆ CNT_LO_CH1

__IOM uint32_t CNT_LO_CH1

[9..8] Lower timer trigger threshold channel 1

◆ CNT_LO_CH2

__IOM uint32_t CNT_LO_CH2

[17..16] Lower timer trigger threshold channel 2

◆ CNT_LO_CH3

__IOM uint32_t CNT_LO_CH3

[25..24] Lower timer trigger threshold channel 3

◆ CNT_LO_CH4

__IOM uint32_t CNT_LO_CH4

[1..0] Lower timer trigger threshold channel 4

◆ CNT_LO_CH5

__IOM uint32_t CNT_LO_CH5

[9..8] Lower timer trigger threshold channel 5

◆ CNT_LO_CH6

__IOM uint32_t CNT_LO_CH6

[17..16] Lower timer trigger threshold channel 6

◆ CNT_LO_CH7

__IOM uint32_t CNT_LO_CH7

[25..24] Lower timer trigger threshold channel 7

◆ CNT_LO_CH8

__IOM uint32_t CNT_LO_CH8

[1..0] Lower timer trigger threshold channel 8

◆ CNT_UP_CH0

__IOM uint32_t CNT_UP_CH0

[1..0] Upper timer trigger threshold channel 0

◆ CNT_UP_CH1

__IOM uint32_t CNT_UP_CH1

[9..8] Upper timer trigger threshold channel 1

◆ CNT_UP_CH2

__IOM uint32_t CNT_UP_CH2

[17..16] Upper timer trigger threshold channel 2

◆ CNT_UP_CH3

__IOM uint32_t CNT_UP_CH3

[25..24] Upper timer trigger threshold channel 3

◆ CNT_UP_CH4

__IOM uint32_t CNT_UP_CH4

[1..0] Upper timer trigger threshold channel 4

◆ CNT_UP_CH5

__IOM uint32_t CNT_UP_CH5

[9..8] Upper timer trigger threshold channel 5

◆ CNT_UP_CH6

__IOM uint32_t CNT_UP_CH6

[17..16] Upper timer trigger threshold channel 6

◆ CNT_UP_CH7

__IOM uint32_t CNT_UP_CH7

[25..24] Upper timer trigger threshold channel 7

◆ CNT_UP_CH8

__IOM uint32_t CNT_UP_CH8

[1..0] Upper timer trigger threshold channel 8

◆ 

union { ... } CTRL1

◆ 

union { ... } CTRL2

◆ 

union { ... } CTRL4

◆ 

union { ... } CTRL_STS

< (@ 0x4801C000) ADC2 Structure

◆ EIM_ACTIVE

__IM uint32_t EIM_ACTIVE

[9..9] ADC2 EIM active

◆ EN

[11..11] Exceptional interrupt measurement (EIM) Trigger Event enable

◆ EOC

[3..3] ADC2 End of Conversion in software mode

◆ 

union { ... } FILT_OUT0

◆ 

union { ... } FILT_OUT1

◆ 

union { ... } FILT_OUT2

◆ 

union { ... } FILT_OUT3

◆ 

union { ... } FILT_OUT4

◆ 

union { ... } FILT_OUT5

◆ 

union { ... } FILT_OUT6

◆ 

union { ... } FILT_OUT7

◆ 

union { ... } FILT_OUT8

◆ FILT_OUT_SEL_8_0

__IOM uint32_t FILT_OUT_SEL_8_0

[8..0] Output Filter Selection for Channels 0 to 8

◆ 

union { ... } FILT_UPLO_CTRL

◆ 

union { ... } FILTCOEFF0_8

◆ GAIN_CH0

__IOM uint32_t GAIN_CH0

[15..8] Gain Calibration for channel 0

◆ GAIN_CH1

__IOM uint32_t GAIN_CH1

[31..24] Gain Calibration for channel 1

◆ GAIN_CH2

__IOM uint32_t GAIN_CH2

[15..8] Gain Calibration for channel 2

◆ GAIN_CH3

__IOM uint32_t GAIN_CH3

[31..24] Gain Calibration for channel 3

◆ GAIN_CH4

__IOM uint32_t GAIN_CH4

[15..8] Gain Calibration for channel 4

◆ GAIN_CH5

__IOM uint32_t GAIN_CH5

[31..24] Gain Calibration for channel 5

◆ GAIN_CH6

__IOM uint32_t GAIN_CH6

[15..8] Gain Calibration for channel 6

◆ GAIN_CH7

__IOM uint32_t GAIN_CH7

[31..24] Gain Calibration for channel 7

◆ GAIN_CH8

__IOM uint32_t GAIN_CH8

[15..8] Gain Calibration for channel 8

◆ HYST_LO_CH0

__IOM uint32_t HYST_LO_CH0

[4..3] Channel 0 lower hysteresis

◆ HYST_LO_CH1

__IOM uint32_t HYST_LO_CH1

[12..11] Channel 1 lower hysteresis

◆ HYST_LO_CH2

__IOM uint32_t HYST_LO_CH2

[20..19] Channel 2 lower hysteresis

◆ HYST_LO_CH3

__IOM uint32_t HYST_LO_CH3

[28..27] Channel 3 lower hysteresis

◆ HYST_LO_CH4

__IOM uint32_t HYST_LO_CH4

[4..3] Channel 4 lower hysteresis

◆ HYST_LO_CH5

__IOM uint32_t HYST_LO_CH5

[12..11] Channel 5 lower hysteresis

◆ HYST_LO_CH6

__IOM uint32_t HYST_LO_CH6

[20..19] Channel 6 lower hysteresis

◆ HYST_LO_CH7

__IOM uint32_t HYST_LO_CH7

[28..27] Channel 7 lower hysteresis

◆ HYST_LO_CH8

__IOM uint32_t HYST_LO_CH8

[4..3] Channel 8 lower hysteresis

◆ HYST_UP_CH0

__IOM uint32_t HYST_UP_CH0

[4..3] Channel 0 upper hysteresis

◆ HYST_UP_CH1

__IOM uint32_t HYST_UP_CH1

[12..11] Channel 1 upper hysteresis

◆ HYST_UP_CH2

__IOM uint32_t HYST_UP_CH2

[20..19] Channel 2 upper hysteresis

◆ HYST_UP_CH3

__IOM uint32_t HYST_UP_CH3

[28..27] Channel 3 upper hysteresis

◆ HYST_UP_CH4

__IOM uint32_t HYST_UP_CH4

[4..3] Channel 4 upper hysteresis

◆ HYST_UP_CH5

__IOM uint32_t HYST_UP_CH5

[12..11] Channel 5 upper hysteresis

◆ HYST_UP_CH6

__IOM uint32_t HYST_UP_CH6

[20..19] Channel 6 upper hysteresis

◆ HYST_UP_CH7

__IOM uint32_t HYST_UP_CH7

[28..27] Channel 7 upper hysteresis

◆ HYST_UP_CH8

__IOM uint32_t HYST_UP_CH8

[4..3] Channel 8 upper hysteresis

◆ IN_MUX_SEL

__IOM uint32_t IN_MUX_SEL

[11..8] Channel for software mode

◆ MAX_TIME [1/2]

__IOM uint32_t MAX_TIME

[7..0] Maximum Time in Software Mode

◆  [2/2]

union { ... } MAX_TIME

◆ MCM_PD_N

__IOM uint32_t MCM_PD_N

[0..0] Power Down Signal for MCM

◆ MCM_RDY

__IM uint32_t MCM_RDY

[7..7] Ready Signal for MCM after Power On or Reset

◆ 

union { ... } MMODE0_8

◆ MSEL_Ch0

__IOM uint32_t MSEL_Ch0

[1..0] Measurement mode ch 0

◆ MSEL_Ch1

__IOM uint32_t MSEL_Ch1

[3..2] Measurement mode ch 1

◆ MSEL_Ch2

__IOM uint32_t MSEL_Ch2

[5..4] Measurement mode ch 2

◆ MSEL_Ch3

__IOM uint32_t MSEL_Ch3

[7..6] Measurement mode ch 3

◆ MSEL_Ch4

__IOM uint32_t MSEL_Ch4

[9..8] Measurement mode ch 4

◆ MSEL_Ch5

__IOM uint32_t MSEL_Ch5

[11..10] Measurement mode ch 5

◆ MSEL_Ch6

__IOM uint32_t MSEL_Ch6

[13..12] Measurement mode ch 6

◆ MSEL_Ch7

__IOM uint32_t MSEL_Ch7

[15..14] Measurement mode ch 7

◆ MSEL_Ch8

__IOM uint32_t MSEL_Ch8

[17..16] Measurement mode ch 8

◆ OFFS_CH0

__IOM uint32_t OFFS_CH0

[4..0] Offset Calibration for channel 0

◆ OFFS_CH1

__IOM uint32_t OFFS_CH1

[20..16] Offset Calibration for channel 1

◆ OFFS_CH2

__IOM uint32_t OFFS_CH2

[4..0] Offset Calibration for channel 2

◆ OFFS_CH3

__IOM uint32_t OFFS_CH3

[20..16] Offset Calibration for channel 3

◆ OFFS_CH4

__IOM uint32_t OFFS_CH4

[4..0] Offset Calibration for channel 4

◆ OFFS_CH5

__IOM uint32_t OFFS_CH5

[20..16] Offset Calibration for channel 5

◆ OFFS_CH6

__IOM uint32_t OFFS_CH6

[4..0] Offset Calibration for channel 6

◆ OFFS_CH7

__IOM uint32_t OFFS_CH7

[20..16] Offset Calibration for channel 7

◆ OFFS_CH8

__IOM uint32_t OFFS_CH8

[4..0] Offset Calibration for channel 8

◆ OUT_CH0

__IM uint32_t OUT_CH0

[9..0] ADC or filter output value channel 0

◆ OUT_CH1

__IM uint32_t OUT_CH1

[9..0] ADC or filter output value channel 1

◆ OUT_CH2

__IM uint32_t OUT_CH2

[9..0] ADC or filter output value channel 2

◆ OUT_CH3

__IM uint32_t OUT_CH3

[9..0] ADC or filter output value channel 3

◆ OUT_CH4

__IM uint32_t OUT_CH4

[9..0] ADC or filter output value channel 4

◆ OUT_CH5

__IM uint32_t OUT_CH5

[9..0] ADC or filter output value channel 5

◆ OUT_CH6

__IM uint32_t OUT_CH6

[9..0] ADC or filter output value channel 6

◆ OUT_CH7

__IM uint32_t OUT_CH7

[9..0] ADC or filter output value channel 7

◆ OUT_CH8

__IM uint32_t OUT_CH8

[9..0] ADC or filter output value channel 8

◆ PD_N

[0..0] ADC2 Power Down Signal

◆ READY

__IM uint32_t READY

[1..1] HVADC Ready bit

◆ reg

(@ 0x00000000) ADC2 Control and Status Register

(@ 0x00000004) Sequencer Feedback Register

(@ 0x00000008) Channel Settings Bits for Exceptional Interrupt Measurement

(@ 0x00000010) Maximum Time for Software Mode

(@ 0x00000014) Measurement Unit Control Register 1

(@ 0x00000018) Measurement Unit Control Register 2

(@ 0x0000001C) Measurement Unit Control Register 4

(@ 0x00000020) Measurement Channel Enable Bits for Sequence 0-1

(@ 0x00000024) Measurement Channel Enable Bits for Sequence 4 - 5

(@ 0x00000028) Measurement Channel Enable Bits for Sequence 2-3

(@ 0x0000002C) Measurement Channel Enable Bits for Sequence 6 - 7

(@ 0x00000030) Measurement Channel Enable Bits for Sequence 8

(@ 0x00000034) Calibration for Channel 0 and 1

(@ 0x00000038) Calibration for Channel 2 and 3

(@ 0x0000003C) Calibration for Channel 4 and 5

(@ 0x00000040) Calibration for Channel 6 and 7

(@ 0x00000044) Calibration for Channel 8

(@ 0x00000048) Filter Coefficients ADC Channel 0-8

(@ 0x00000050) ADC or Filter Output Channel 0

(@ 0x00000054) ADC or Filter Output Channel 1

(@ 0x00000058) ADC or Filter Output Channel 2

(@ 0x0000005C) ADC or Filter Output Channel 3

(@ 0x00000060) ADC or Filter Output Channel 4

(@ 0x00000064) ADC or Filter Output Channel 5

(@ 0x00000068) ADC or Filter Output Channel 6

(@ 0x0000006C) ADC or Filter Output Channel 7

(@ 0x00000070) ADC or Filter Output Channel 8

(@ 0x00000078) Upper and Lower Threshold Filter Enable

(@ 0x00000080) Lower Comparator Trigger Level Channel 0 -3

(@ 0x00000084) Lower Comparator Trigger Level Channel 4 to 7

(@ 0x00000088) Lower Comparator Trigger Level Channel 8

(@ 0x0000008C) Upper Comparator Trigger Level Channel 0-3

(@ 0x00000090) Upper Comparator Trigger Level Channel 4 -7

(@ 0x00000094) Upper Comparator Trigger Level Channel 8

(@ 0x00000098) Lower Counter Trigger Level Channel 0 - 3

(@ 0x0000009C) Lower Counter Trigger Level Channel 4 to 7

(@ 0x000000A0) Lower Counter Trigger Level Channel 8

(@ 0x000000A4) Upper Counter Trigger Level Channel 0 - 3

(@ 0x000000A8) Upper Counter Trigger Level Channel 4 to 7

(@ 0x000000AC) Upper Counter Trigger Level Channel 8

(@ 0x000000B0) Measurement Mode of Ch 0-8

(@ 0x000000BC) ADC2 HV Status Register

◆ REP

[10..8] Repeat count for exceptional interrupt measurement (EIM)

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1

◆ RESERVED2

__IM uint32_t RESERVED2

◆ RESERVED3

__IM uint32_t RESERVED3

◆ RESERVED4

__IM uint32_t RESERVED4[2]

◆ SAMPLE_TIME_int

__IOM uint32_t SAMPLE_TIME_int

[11..8] Sample time of ADC2

◆ SEL

[12..12] Exceptional interrupt measurement (EIM) Trigger select

◆ SOS

[2..2] ADC2 Start of Sampling/Conversion (software mode)

◆ SQ0

[8..0] Sequence 0 channel enable

◆ 

union { ... } SQ0_1

◆ SQ1

[24..16] Sequence 1 channel enable

◆ SQ2

[8..0] Sequence 2 channel enable

◆ 

union { ... } SQ2_3

◆ SQ3

[24..16] Sequence 3 channel enable

◆ SQ4

[8..0] Sequence 4 channel enable

◆ 

union { ... } SQ4_5

◆ SQ5

[24..16] Sequence 5 channel enable

◆ SQ6

[8..0] Sequence 6 channel enable

◆ 

union { ... } SQ6_7

◆ SQ7

[24..16] Sequence 7 channel enable

◆ SQ8

[8..0] Sequence 8 channel enable

◆ 

union { ... } SQ8_9

◆ SQ_FB [1/2]

__IM uint32_t SQ_FB

[3..0] Current Sequence that caused software mode

◆  [2/2]

union { ... } SQ_FB

◆ SQ_STOP

__IM uint32_t SQ_STOP

[8..8] ADC2 Sequencer Stop Signal for DPP

◆ SQx

[14..11] Current active ADC2 Sequence (in normal mode)

◆ 

union { ... } STATUS

◆ 

union { ... } TH0_3_LOWER

◆ 

union { ... } TH0_3_UPPER

◆ 

union { ... } TH4_7_LOWER

◆ 

union { ... } TH4_7_UPPER

◆ 

union { ... } TH8_11_LOWER

◆ 

union { ... } TH8_11_UPPER

◆ THLO_CH0

__IOM uint32_t THLO_CH0

[7..0] Channel 0 lower trigger level

◆ THLO_CH1

__IOM uint32_t THLO_CH1

[15..8] Channel 1 lower trigger level

◆ THLO_CH2

__IOM uint32_t THLO_CH2

[23..16] Channel 2 lower trigger level

◆ THLO_CH3

__IOM uint32_t THLO_CH3

[31..24] Channel 3 lower trigger level

◆ THLO_CH4

__IOM uint32_t THLO_CH4

[7..0] Channel 4 lower trigger level

◆ THLO_CH5

__IOM uint32_t THLO_CH5

[15..8] Channel 5 lower trigger level

◆ THLO_CH6

__IOM uint32_t THLO_CH6

[23..16] Channel 6 lower trigger level

◆ THLO_CH7

__IOM uint32_t THLO_CH7

[31..24] Channel 7 lower trigger level

◆ THLO_CH8

__IOM uint32_t THLO_CH8

[7..0] Channel 8 lower trigger level

◆ THUP_CH0

__IOM uint32_t THUP_CH0

[7..0] Channel 0 upper trigger level

◆ THUP_CH1

__IOM uint32_t THUP_CH1

[15..8] Channel 1 upper trigger level

◆ THUP_CH2

__IOM uint32_t THUP_CH2

[23..16] Channel 2 upper trigger level

◆ THUP_CH3

__IOM uint32_t THUP_CH3

[31..24] Channel 3 upper trigger level

◆ THUP_CH4

__IOM uint32_t THUP_CH4

[7..0] Channel 4 upper trigger level

◆ THUP_CH5

__IOM uint32_t THUP_CH5

[15..8] Channel 5 upper trigger level

◆ THUP_CH6

__IOM uint32_t THUP_CH6

[23..16] Channel 6 upper trigger level

◆ THUP_CH7

__IOM uint32_t THUP_CH7

[31..24] Channel 7 upper trigger level

◆ THUP_CH8

__IOM uint32_t THUP_CH8

[7..0] Channel 8 upper trigger level

◆ uint32_t

__IM uint32_t

◆ UPLOEN_Ch0

__IOM uint32_t UPLOEN_Ch0

[0..0] Upper and lower threshold IIR filter enable ch 0

◆ UPLOEN_Ch1

__IOM uint32_t UPLOEN_Ch1

[1..1] Upper and lower threshold IIR filter enable ch 1

◆ UPLOEN_Ch2

__IOM uint32_t UPLOEN_Ch2

[2..2] Upper and lower threshold IIR filter enable ch 2

◆ UPLOEN_Ch3

__IOM uint32_t UPLOEN_Ch3

[3..3] Upper and lower threshold IIR filter enable ch 3

◆ UPLOEN_Ch4

__IOM uint32_t UPLOEN_Ch4

[4..4] Upper and lower threshold IIR filter enable ch 4

◆ UPLOEN_Ch5

__IOM uint32_t UPLOEN_Ch5

[5..5] Upper and lower threshold IIR filter enable ch 5

◆ UPLOEN_Ch6

__IOM uint32_t UPLOEN_Ch6

[6..6] Upper and lower threshold IIR filter enable ch 6

◆ UPLOEN_Ch7

__IOM uint32_t UPLOEN_Ch7

[7..7] Upper and lower threshold IIR filter enable ch 7

◆ UPLOEN_Ch8

__IOM uint32_t UPLOEN_Ch8

[8..8] Upper and lower threshold IIR filter enable ch 8


The documentation for this struct was generated from the following file: