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Infineon MOTIX™ MCU TLE985x Device Family SDK
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PMU (PMU)
#include <tle985x.h>
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
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struct { ... } bit |
struct { ... } bit |
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struct { ... } bit |
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struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
struct { ... } bit |
union { ... } CNF_RST_TFB |
union { ... } CNF_WAKE_FILTER |
[16..16] GPIO0_0 input for cycle sense enable
[16..16] GPIO1_0 input for cycle sense enable
[17..17] GPIO0_1 input for cycle sense enable
[17..17] GPIO1_1 input for cycle sense enable
[18..18] GPIO0_2 input for cycle sense enable
[18..18] GPIO1_2 input for cycle sense enable
[20..20] GPIO0_4 input for cycle sense enable
[20..20] GPIO1_4 input for cycle sense enable
union { ... } DRV_CTRL |
[1..1] Enables the reduction of the VDDC regulator output to 0.9 V during Stop-Mode
[8..8] Port 0_0 Wake-up on Falling Edge enable
[8..8] Port 1_0 Wake-up on Falling Edge enable
[9..9] Port 0_1 Wake-up on Falling Edge enable
[9..9] Port 1_1 Wake-up on Falling Edge enable
[10..10] Port 0_2 Wake-up on Falling Edge enable
[10..10] Port 1_2 Wake-up on Falling Edge enable
[12..12] Port 0_4 Wake-up on Falling Edge enable
[12..12] Port 1_4 Wake-up on Falling Edge enable
[5..5] Wake-up after any Fail, which is a logical OR combination of PMU_OT, VDDEXT_OT, VDDEXT_UV
[2..2] Wake-up via GPIO0 which is a logical OR combination of all Wake_STS_GPIO0 bits
[3..3] Wake-up via GPIO1 which is a logical OR combination of all Wake_STS_GPIO1 bits
[6..6] Wake-up via GPIO2 which is a logical OR combination of all Wake_STS_GPIO2 bits
union { ... } GPIO_WAKE_STATUS |
union { ... } GPUDATA0to3 |
union { ... } GPUDATA4to7 |
union { ... } GPUDATA8to11 |
union { ... } HIGHSIDE_CTRL |
union { ... } LIN_WAKE_EN |
union { ... } MON_CNF1 |
union { ... } MON_CNF2 |
union { ... } OT_CTRL |
union { ... } PORCFG |
(@ 0x00000000) Main wake status register
(@ 0x00000004) GPIO Port wake status register
(@ 0x00000008) Voltage Reg Status Register
(@ 0x0000000C) VDDEXT Control
(@ 0x00000010) Reset Status Register
(@ 0x00000020) PMU Sleep Behavior Register
(@ 0x00000024) PMU Bridge Driver Control
(@ 0x00000034) Settings Monitor
(@ 0x00000038) Settings Monitor
(@ 0x00000050) LIN Wake Enable
(@ 0x00000054) Overtemperature Control Register
(@ 0x0000005C) Highside Control Register
(@ 0x0000006C) Reset Blind Time Register
(@ 0x00000070) WFS System Fail Register
(@ 0x000000AC) PMU Wake-up Timing Register
(@ 0x000000B4) POR Reset Configuration Register
(@ 0x000000BC) Wake Configuration GPIO Port 0 Register
(@ 0x000000C0) General Purpose User DATA0to3
(@ 0x000000C4) General Purpose User DATA4to7
(@ 0x000000C8) General Purpose User DATA8to11
(@ 0x000000CC) Wake Configuration GPIO Port 1 Register
union { ... } RESET_STS |
[0..0] Port 0_0 Wake-up on Rising Edge enable
[0..0] Port 1_0 Wake-up on Rising Edge enable
[1..1] Port 0_1 Wake-up on Rising Edge enable
[1..1] Port 1_1 Wake-up on Rising Edge enable
[2..2] Port 0_2 Wake-up on Rising Edge enable
[2..2] Port 1_2 Wake-up on Rising Edge enable
[4..4] Port 0_4 Wake-up on Rising Edge enable
[4..4] Port 1_4 Wake-up on Rising Edge enable
union { ... } SLEEP |
union { ... } SUPPLY_STS |
[0..0] Flag which indicates a reset caused by a System Fail reported in the corresponding Fail Register
__IM uint32_t |
union { ... } VDDEXT_CTRL |
[2..2] Enabling of VDDEXT Supply status information as interrupt source
union { ... } WAKE_CNF_GPIO0 |
union { ... } WAKE_CNF_GPIO1 |
union { ... } WAKE_STATUS |
< (@ 0x50004000) PMU Structure
union { ... } WFS |