Revision History
Version | Date | Comment |
V1.0.3 | 2019-09-03 | Added separate XML file for Half-Bridge Devices (TLE9850/51) and removed HB2 for these devices |
| | Added note '- not applicable for TLE9852QX' for CSA |
V1.0.2 | 2019-08-29 | Corrected default values of BDRV_CP_CTRL.DRVx_VCPLO_SDEN, BDRV Clock Divider Filter Clock Divider |
| | Corrected value of LP_CLK for Charge Pump Clock calculation |
V1.0.1 | 2019-06-11 | Removed spinboxes for ADC1.CAL_CHx_y as these registers are initialized by the BootROM |
V1.0.0 | 2019-02-11 | openmarket release |
| | CCU6 channel passive state default set to fit to bridge driver (CC6x passive state before compare, COUT6x passive state after compare) |
| | BG_CLK added |
| | CCU6 to BDRV default assignment updated |
V0.1.2 | 2018-10-17 | ADC1 gain and offset calibration channels added |
| | HS.PWMSRCSEL.HS1_SRC_SEL added |
| | PMU.HIGHSIDE_CTRL.HS1_CYC_EN added |
V0.1.1 | 2018-10-03 | ADC1 channel 10/11 removed as they are n/a |
| | SCU.CMCON1.K1DIV removed |
| | SCU.CMCON1.CLKREL removed |
| | TIMER2: T2IN default value changed |
| | ADC1: DPP/ADC clock divider added, sample time calc. fixed |
| | ADC1: ADC1.CLK replaced by ADC1.FADCI |
V0.1.0 | 2018-09-20 | ADC1: SSCx lockon removed |
V0.0.9 | 2018-09-19 | ADC1: Postprocessing interrupt selection corrected |
V0.0.8 | 2018-08-28 | SSC and LIN user interface improved |
| | T2 and T21 input selection corrected |
| | BDRV: charge sequencer default values corrected |
V0.0.7 | 2018-08-03 | CSA user interface improved |
V0.0.6 | 2018-08-02 | UART and PORT user interface improved |
V0.0.5 | 2018-07-16 | BDRV settings extended |