Infineon MOTIX™ MCU TLE985x Device Family SDK
int.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2018-2023, Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
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16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
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19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** TS T&S **
45 ** BG Blandine Guillot **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.2.0: 2018-02-13, TS: Initial version of revision history **
52 ** V0.2.1: 2019-01-28, TS: __STATIC_INLINE changed to INLINE **
53 ** Doxygen update **
54 ** Revision history moved from int.c to int.h **
55 ** NMI Mask macros added to meet MISRA 2012 **
56 ** EXINTx Mask macros added to meet MISRA 2012 **
57 ** V0.2.2: 2020-03-02, BG: Updated revision history format **
58 ** V0.2.3: 2022-01-21, JO: EP-934: Updated copyright and branding **
59 ** V0.3.0: 2023-06-30, JO: EP-655: Removed PLL loss of lock interrupt **
60 ** V0.3.1: 2023-08-28, JO: EP-435: Removed ARMCC v6 compiler warnings **
61 *******************************************************************************/
62 
63 #ifndef INT_H
64 #define INT_H
65 
66 /*******************************************************************************
67 ** Includes **
68 *******************************************************************************/
69 #include "tle985x.h"
70 #include "types.h"
71 #include "sfr_access.h"
72 
73 /*******************************************************************************
74 ** Global Macro Definitions **
75 *******************************************************************************/
77 #define NMI_WDT (1u << 0u)
79 #define NMI_OT (1u << 3u)
81 #define NMI_OWT (1u << 4u)
83 #define NMI_MAP (1u << 5u)
85 #define NMI_ECC (1u << 6u)
87 #define NMI_SUP (1u << 7u)
89 #define NMI_STOF (1u << 8u)
90 
92 #define SCU_EXICON0_EXINT0_RE_Pos (0UL)
94 #define SCU_EXICON0_EXINT0_RE_Msk (0x01UL)
96 #define SCU_EXICON0_EXINT0_FE_Pos (1UL)
98 #define SCU_EXICON0_EXINT0_FE_Msk (0x02UL)
100 #define SCU_EXICON0_EXINT1_RE_Pos (2UL)
102 #define SCU_EXICON0_EXINT1_RE_Msk (0x04UL)
104 #define SCU_EXICON0_EXINT1_FE_Pos (3UL)
106 #define SCU_EXICON0_EXINT1_FE_Msk (0x08UL)
108 #define SCU_EXICON0_EXINT2_RE_Pos (4UL)
110 #define SCU_EXICON0_EXINT2_RE_Msk (0x10UL)
112 #define SCU_EXICON0_EXINT2_FE_Pos (5UL)
114 #define SCU_EXICON0_EXINT2_FE_Msk (0x20UL)
115 
117 #define SCU_NMISR_Msk (0x1FBu)
119 #define SCU_NMICLR_Msk (0x33u)
120 
121 /*******************************************************************************
122 ** Global Function Declarations **
123 *******************************************************************************/
128 void INT_Init(void);
129 
130 /*******************************************************************************
131 ** Inline Function Declarations **
132 *******************************************************************************/
145 INLINE void Global_Int_En(void);
146 
159 INLINE void Global_Int_Dis(void);
160 
183 
207 
230 
254 
271 
290 
309 
328 
348 
367 
387 
406 
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484 
504 
523 
543 
562 
581 
600 
619 
638 
657 
681 INLINE void NMI_WDT_Int_En(void);
682 
707 INLINE void NMI_WDT_Int_Dis(void);
708 
730 INLINE void NMI_ECC_Int_En(void);
731 
754 INLINE void NMI_ECC_Int_Dis(void);
755 
773 INLINE void NMI_MAP_Int_En(void);
774 
793 INLINE void NMI_MAP_Int_Dis(void);
794 
815 INLINE void NMI_SUP_Int_En(void);
816 
838 INLINE void NMI_SUP_Int_Dis(void);
839 
857 INLINE void NMI_OWD_Int_En(void);
858 
877 INLINE void NMI_OWD_Int_Dis(void);
878 
899 INLINE void NMI_OT_Int_En(void);
900 
922 INLINE void NMI_OT_Int_Dis(void);
923 
945 INLINE void NMI_STOF_Int_En(void);
946 
969 INLINE void NMI_STOF_Int_Dis(void);
970 
994 INLINE void NMI_WDT_Int_Clr(void);
995 
1013 INLINE void NMI_OWD_Int_Clr(void);
1014 
1032 INLINE void NMI_MAP_Int_Clr(void);
1033 
1055 INLINE void NMI_STOF_En(void);
1056 
1079 INLINE void NMI_STOF_Dis(void);
1080 
1102 INLINE void NMI_STOF_Int_Clr(void);
1103 
1116 INLINE void Int_PORT2_Pend_Set(void);
1117 
1130 INLINE void Int_MON_Pend_Set(void);
1131 
1144 INLINE void Int_DU_Pend_Set(void);
1145 
1158 INLINE void Int_OPA_Pend_Set(void);
1159 
1172 INLINE void Int_HS_Pend_Set(void);
1173 
1186 INLINE void Int_BDRV_Pend_Set(void);
1187 
1200 INLINE void Int_CP_Pend_Set(void);
1201 
1214 INLINE void Int_MATHDIV_Pend_Set(void);
1215 
1228 INLINE void Int_WAKEUP_Pend_Set(void);
1229 
1242 INLINE void Int_EXINT1_Pend_Set(void);
1243 
1256 INLINE void Int_EXINT0_Pend_Set(void);
1257 
1270 INLINE void Int_UART2_Pend_Set(void);
1271 
1284 INLINE void Int_UART1_Pend_Set(void);
1285 
1298 INLINE void Int_SSC2_Pend_Set(void);
1299 
1312 INLINE void Int_SSC1_Pend_Set(void);
1313 
1326 INLINE void Int_CCU6SR3_Pend_Set(void);
1327 
1340 INLINE void Int_CCU6SR2_Pend_Set(void);
1341 
1354 INLINE void Int_CCU6SR1_Pend_Set(void);
1355 
1368 INLINE void Int_CCU6SR0_Pend_Set(void);
1369 
1382 INLINE void Int_ADC1_Pend_Set(void);
1383 
1396 INLINE void Int_ADC2_Pend_Set(void);
1397 
1410 INLINE void Int_GPT2_Pend_Set(void);
1411 
1424 INLINE void Int_GPT1_Pend_Set(void);
1425 
1438 INLINE void Int_PORT2_Pend_Clr(void);
1439 
1452 INLINE void Int_MON_Pend_Clr(void);
1453 
1466 INLINE void Int_DU_Pend_Clr(void);
1467 
1480 INLINE void Int_OPA_Pend_Clr(void);
1481 
1494 INLINE void Int_HS_Pend_Clr(void);
1495 
1508 INLINE void Int_BDRV_Pend_Clr(void);
1509 
1522 INLINE void Int_CP_Pend_Clr(void);
1523 
1536 INLINE void Int_MATHDIV_Pend_Clr(void);
1537 
1550 INLINE void Int_WAKEUP_Pend_Clr(void);
1551 
1564 INLINE void Int_EXINT1_Pend_Clr(void);
1565 
1578 INLINE void Int_EXINT0_Pend_Clr(void);
1579 
1592 INLINE void Int_UART2_Pend_Clr(void);
1593 
1606 INLINE void Int_UART1_Pend_Clr(void);
1607 
1620 INLINE void Int_SSC2_Pend_Clr(void);
1621 
1634 INLINE void Int_SSC1_Pend_Clr(void);
1635 
1648 INLINE void Int_CCU6SR3_Pend_Clr(void);
1649 
1662 INLINE void Int_CCU6SR2_Pend_Clr(void);
1663 
1676 INLINE void Int_CCU6SR1_Pend_Clr(void);
1677 
1690 INLINE void Int_CCU6SR0_Pend_Clr(void);
1691 
1704 INLINE void Int_ADC1_Pend_Clr(void);
1705 
1718 INLINE void Int_ADC2_Pend_Clr(void);
1719 
1732 INLINE void Int_GPT2_Pend_Clr(void);
1733 
1746 INLINE void Int_GPT1_Pend_Clr(void);
1747 
1760 INLINE void NMI_Pend_Set(void);
1761 
1774 INLINE void PENDSV_Pend_Set(void);
1775 
1788 INLINE void PENDSV_Pend_Clr(void);
1789 
1802 INLINE void SysTick_Pend_Set(void);
1803 
1816 INLINE void SysTick_Pend_Clr(void);
1817 
1835 
1850 INLINE void INT_Clr_NMI_Status(uint8 Flags);
1851 
1864 INLINE void INT_Enable_Global_Int(void);
1865 
1878 INLINE void INT_Disable_Global_Int(void);
1879 
1880 /*******************************************************************************
1881 ** Inline Function Definitions **
1882 *******************************************************************************/
1884 {
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2372 
2374 {
2375  return(u16_Field_Rd32(&SCU->NMISR.reg, (uint8)SCU_NMISR_FNMIWDT_Pos, SCU_NMISR_Msk));
2376 }
2377 
2379 {
2380  Field_Wrt32(&SCU->NMISRCLR.reg, (uint8)SCU_NMISRCLR_FNMIWDTC_Pos, SCU_NMICLR_Msk, Flags);
2381 }
2382 
2384 {
2385  Global_Int_En();
2386 }
2387 
2389 {
2390  Global_Int_Dis();
2391 }
2392 
2393 #endif
#define CPU
Definition: tle985x.h:6269
#define SCU
Definition: tle985x.h:6277
#define CPU_NVIC_ICPR_Int_ADC2_Msk
Definition: tle985x.h:8587
#define CPU_NVIC_ISPR_Int_EXINT1_Pos
Definition: tle985x.h:8710
#define CPU_ICSR_PENDSTCLR_Msk
Definition: tle985x.h:8491
#define CPU_NVIC_ISPR_Int_CCU6SR3_Pos
Definition: tle985x.h:8722
#define CPU_NVIC_ICPR_Int_CCU6SR2_Msk
Definition: tle985x.h:8579
#define CPU_NVIC_ISPR_Int_MON_Pos
Definition: tle985x.h:8694
#define SCU_EDCSCLR_RDBEC_Pos
Definition: tle985x.h:9884
#define SCU_IRCON0CLR_EXINT0FC_Msk
Definition: tle985x.h:9986
#define CPU_NVIC_ICPR_Int_SSC1_Pos
Definition: tle985x.h:8574
#define CPU_NVIC_ICPR_Int_BDRV_Pos
Definition: tle985x.h:8556
#define CPU_NVIC_ISPR_Int_ADC2_Msk
Definition: tle985x.h:8733
#define SCU_STACK_OVF_CTRL_STOF_EN_Msk
Definition: tle985x.h:10361
#define SCU_IRCON0CLR_EXINT0RC_Msk
Definition: tle985x.h:9988
#define SCU_NMICON_NMISTOF_Msk
Definition: tle985x.h:10226
#define CPU_NVIC_ICPR_Int_DU_Msk
Definition: tle985x.h:8551
#define SCU_NMISR_FNMIWDT_Pos
Definition: tle985x.h:10252
#define SCU_EDCSCLR_NVMDBEC_Msk
Definition: tle985x.h:9883
#define CPU_NVIC_ICPR_Int_EXINT0_Pos
Definition: tle985x.h:8566
#define CPU_NVIC_ISPR_Int_CCU6SR2_Msk
Definition: tle985x.h:8725
#define CPU_NVIC_ISPR_Int_CP_Pos
Definition: tle985x.h:8704
#define SCU_NMISRCLR_FNMIWDTC_Msk
Definition: tle985x.h:10260
#define SCU_NMICON_NMIMAP_Pos
Definition: tle985x.h:10231
#define SCU_STACK_OVFCLR_STOF_STSC_Msk
Definition: tle985x.h:10367
#define SCU_NMICON_NMIOWD_Msk
Definition: tle985x.h:10234
#define SCU_STACK_OVF_CTRL_STOF_EN_Pos
Definition: tle985x.h:10360
#define CPU_NVIC_ICPR_Int_ADC1_Pos
Definition: tle985x.h:8584
#define SCU_IRCON0CLR_EXINT2RC_Pos
Definition: tle985x.h:9979
#define CPU_NVIC_ICPR_Int_UART2_Pos
Definition: tle985x.h:8568
#define CPU_NVIC_ICPR_Int_GPT2_Pos
Definition: tle985x.h:8588
#define CPU_ICSR_PENDSTSET_Pos
Definition: tle985x.h:8488
#define SCU_IRCON0CLR_EXINT1FC_Pos
Definition: tle985x.h:9981
#define SCU_IRCON0CLR_EXINT1RC_Pos
Definition: tle985x.h:9983
#define CPU_NVIC_ICPR_Int_MATHDIV_Pos
Definition: tle985x.h:8560
#define CPU_NVIC_ICPR_Int_GPT1_Pos
Definition: tle985x.h:8590
#define CPU_NVIC_ISPR_Int_PORT2_Msk
Definition: tle985x.h:8693
#define CPU_NVIC_ISPR_Int_UART2_Msk
Definition: tle985x.h:8715
#define SCU_EDCSCLR_RSBEC_Msk
Definition: tle985x.h:9881
#define CPU_NVIC_ICPR_Int_UART1_Msk
Definition: tle985x.h:8571
#define CPU_NVIC_ICPR_Int_MATHDIV_Msk
Definition: tle985x.h:8561
#define CPU_NVIC_ISPR_Int_EXINT0_Msk
Definition: tle985x.h:8713
#define CPU_NVIC_ISPR_Int_HS_Pos
Definition: tle985x.h:8700
#define CPU_NVIC_ISPR_Int_EXINT1_Msk
Definition: tle985x.h:8711
#define CPU_NVIC_ICPR_Int_CCU6SR2_Pos
Definition: tle985x.h:8578
#define CPU_NVIC_ISPR_Int_HS_Msk
Definition: tle985x.h:8701
#define CPU_NVIC_ISPR_Int_ADC1_Msk
Definition: tle985x.h:8731
#define CPU_NVIC_ISPR_Int_CCU6SR1_Pos
Definition: tle985x.h:8726
#define SCU_NMISRCLR_FNMIMAPC_Msk
Definition: tle985x.h:10256
#define SCU_IRCON0CLR_EXINT0RC_Pos
Definition: tle985x.h:9987
#define SCU_IRCON0CLR_EXINT1RC_Msk
Definition: tle985x.h:9984
#define CPU_NVIC_ISPR_Int_PORT2_Pos
Definition: tle985x.h:8692
#define CPU_NVIC_ICPR_Int_CCU6SR3_Msk
Definition: tle985x.h:8577
#define SCU_IRCON0CLR_EXINT2RC_Msk
Definition: tle985x.h:9980
#define CPU_NVIC_ICPR_Int_HS_Pos
Definition: tle985x.h:8554
#define SCU_EDCCON_NVMIE_Pos
Definition: tle985x.h:9875
#define SCU_IRCON0CLR_EXINT2FC_Pos
Definition: tle985x.h:9977
#define CPU_NVIC_ICPR_Int_EXINT1_Msk
Definition: tle985x.h:8565
#define SCU_NMISRCLR_FNMIWDTC_Pos
Definition: tle985x.h:10259
#define CPU_NVIC_ISPR_Int_BDRV_Pos
Definition: tle985x.h:8702
#define CPU_ICSR_NMIPENDSET_Msk
Definition: tle985x.h:8483
#define CPU_NVIC_ISPR_Int_ADC1_Pos
Definition: tle985x.h:8730
#define SCU_EDCCON_RIE_Msk
Definition: tle985x.h:9878
#define SCU_EDCSCLR_RSBEC_Pos
Definition: tle985x.h:9880
#define CPU_NVIC_ISPR_Int_MATHDIV_Msk
Definition: tle985x.h:8707
#define SCU_NMISRCLR_FNMIMAPC_Pos
Definition: tle985x.h:10255
#define CPU_NVIC_ISPR_Int_DU_Pos
Definition: tle985x.h:8696
#define CPU_ICSR_PENDSTCLR_Pos
Definition: tle985x.h:8490
#define CPU_NVIC_ISPR_Int_CCU6SR1_Msk
Definition: tle985x.h:8727
#define CPU_NVIC_ISPR_Int_BDRV_Msk
Definition: tle985x.h:8703
#define SCU_IRCON0CLR_EXINT1FC_Msk
Definition: tle985x.h:9982
#define CPU_ICSR_NMIPENDSET_Pos
Definition: tle985x.h:8482
#define SCU_NMICON_NMISUP_Msk
Definition: tle985x.h:10228
#define SCU_NMICON_NMIOWD_Pos
Definition: tle985x.h:10233
#define SCU_NMICON_NMIOT_Pos
Definition: tle985x.h:10235
#define SCU_NMICON_NMIECC_Msk
Definition: tle985x.h:10230
#define CPU_NVIC_ISPR_Int_CCU6SR0_Msk
Definition: tle985x.h:8729
#define SCU_NMISRCLR_FNMIOWDC_Msk
Definition: tle985x.h:10258
#define CPU_ICSR_PENDSTSET_Msk
Definition: tle985x.h:8489
#define CPU_NVIC_ICPR_Int_DU_Pos
Definition: tle985x.h:8550
#define CPU_NVIC_ISPR_Int_GPT1_Pos
Definition: tle985x.h:8736
#define CPU_NVIC_ICPR_Int_CCU6SR3_Pos
Definition: tle985x.h:8576
#define SCU_IRCON0CLR_EXINT2FC_Msk
Definition: tle985x.h:9978
#define SCU_NMICON_NMISTOF_Pos
Definition: tle985x.h:10225
#define SCU_NMICON_NMISUP_Pos
Definition: tle985x.h:10227
#define CPU_NVIC_ICPR_Int_WAKEUP_Msk
Definition: tle985x.h:8563
#define CPU_NVIC_ISPR_Int_SSC2_Msk
Definition: tle985x.h:8719
#define CPU_NVIC_ICPR_Int_SSC2_Msk
Definition: tle985x.h:8573
#define SCU_EDCSCLR_RDBEC_Msk
Definition: tle985x.h:9885
#define CPU_NVIC_ISPR_Int_OPA_Pos
Definition: tle985x.h:8698
#define CPU_NVIC_ISPR_Int_SSC1_Msk
Definition: tle985x.h:8721
#define CPU_NVIC_ISPR_Int_CP_Msk
Definition: tle985x.h:8705
#define CPU_NVIC_ICPR_Int_UART2_Msk
Definition: tle985x.h:8569
#define SCU_STACK_OVFCLR_STOF_STSC_Pos
Definition: tle985x.h:10366
#define CPU_NVIC_ISPR_Int_CCU6SR2_Pos
Definition: tle985x.h:8724
#define CPU_NVIC_ICPR_Int_PORT2_Pos
Definition: tle985x.h:8546
#define CPU_NVIC_ICPR_Int_SSC1_Msk
Definition: tle985x.h:8575
#define CPU_NVIC_ISPR_Int_UART1_Msk
Definition: tle985x.h:8717
#define SCU_IRCON0CLR_EXINT0FC_Pos
Definition: tle985x.h:9985
#define SCU_NMICON_NMIWDT_Msk
Definition: tle985x.h:10238
#define CPU_NVIC_ICPR_Int_MON_Pos
Definition: tle985x.h:8548
#define CPU_NVIC_ISPR_Int_WAKEUP_Msk
Definition: tle985x.h:8709
#define CPU_NVIC_ICPR_Int_CP_Pos
Definition: tle985x.h:8558
#define SCU_EDCCON_NVMIE_Msk
Definition: tle985x.h:9876
#define CPU_NVIC_ISPR_Int_DU_Msk
Definition: tle985x.h:8697
#define CPU_NVIC_ICPR_Int_CCU6SR1_Pos
Definition: tle985x.h:8580
#define SCU_IEN0_EA_Pos
Definition: tle985x.h:9961
#define CPU_NVIC_ISPR_Int_ADC2_Pos
Definition: tle985x.h:8732
#define CPU_NVIC_ISPR_Int_EXINT0_Pos
Definition: tle985x.h:8712
#define CPU_NVIC_ISPR_Int_MATHDIV_Pos
Definition: tle985x.h:8706
#define CPU_NVIC_ISPR_Int_GPT2_Pos
Definition: tle985x.h:8734
#define CPU_NVIC_ICPR_Int_PORT2_Msk
Definition: tle985x.h:8547
#define SCU_NMICON_NMIWDT_Pos
Definition: tle985x.h:10237
#define CPU_ICSR_PENDSVSET_Msk
Definition: tle985x.h:8485
#define SCU_EDCCON_RIE_Pos
Definition: tle985x.h:9877
#define CPU_NVIC_ICPR_Int_OPA_Msk
Definition: tle985x.h:8553
#define CPU_NVIC_ICPR_Int_BDRV_Msk
Definition: tle985x.h:8557
#define CPU_NVIC_ICPR_Int_CCU6SR1_Msk
Definition: tle985x.h:8581
#define CPU_NVIC_ICPR_Int_GPT1_Msk
Definition: tle985x.h:8591
#define CPU_NVIC_ISPR_Int_WAKEUP_Pos
Definition: tle985x.h:8708
#define CPU_NVIC_ICPR_Int_OPA_Pos
Definition: tle985x.h:8552
#define CPU_NVIC_ICPR_Int_SSC2_Pos
Definition: tle985x.h:8572
#define SCU_NMISRCLR_FNMIOWDC_Pos
Definition: tle985x.h:10257
#define CPU_NVIC_ICPR_Int_CCU6SR0_Pos
Definition: tle985x.h:8582
#define CPU_NVIC_ICPR_Int_EXINT0_Msk
Definition: tle985x.h:8567
#define CPU_NVIC_ICPR_Int_UART1_Pos
Definition: tle985x.h:8570
#define CPU_NVIC_ISPR_Int_MON_Msk
Definition: tle985x.h:8695
#define CPU_ICSR_PENDSVSET_Pos
Definition: tle985x.h:8484
#define CPU_NVIC_ISPR_Int_OPA_Msk
Definition: tle985x.h:8699
#define CPU_NVIC_ICPR_Int_GPT2_Msk
Definition: tle985x.h:8589
#define CPU_NVIC_ICPR_Int_HS_Msk
Definition: tle985x.h:8555
#define CPU_NVIC_ICPR_Int_CCU6SR0_Msk
Definition: tle985x.h:8583
#define CPU_NVIC_ISPR_Int_UART1_Pos
Definition: tle985x.h:8716
#define CPU_NVIC_ISPR_Int_CCU6SR0_Pos
Definition: tle985x.h:8728
#define CPU_NVIC_ICPR_Int_EXINT1_Pos
Definition: tle985x.h:8564
#define CPU_NVIC_ISPR_Int_CCU6SR3_Msk
Definition: tle985x.h:8723
#define CPU_NVIC_ICPR_Int_CP_Msk
Definition: tle985x.h:8559
#define CPU_NVIC_ISPR_Int_SSC2_Pos
Definition: tle985x.h:8718
#define SCU_EDCSCLR_NVMDBEC_Pos
Definition: tle985x.h:9882
#define SCU_NMICON_NMIOT_Msk
Definition: tle985x.h:10236
#define CPU_ICSR_PENDSVCLR_Msk
Definition: tle985x.h:8487
#define CPU_ICSR_PENDSVCLR_Pos
Definition: tle985x.h:8486
#define CPU_NVIC_ISPR_Int_SSC1_Pos
Definition: tle985x.h:8720
#define CPU_NVIC_ISPR_Int_GPT1_Msk
Definition: tle985x.h:8737
#define CPU_NVIC_ICPR_Int_WAKEUP_Pos
Definition: tle985x.h:8562
#define SCU_NMICON_NMIECC_Pos
Definition: tle985x.h:10229
#define SCU_IEN0_EA_Msk
Definition: tle985x.h:9962
#define CPU_NVIC_ISPR_Int_GPT2_Msk
Definition: tle985x.h:8735
#define CPU_NVIC_ICPR_Int_ADC1_Msk
Definition: tle985x.h:8585
#define SCU_NMICON_NMIMAP_Msk
Definition: tle985x.h:10232
#define CPU_NVIC_ISPR_Int_UART2_Pos
Definition: tle985x.h:8714
#define CPU_NVIC_ICPR_Int_ADC2_Pos
Definition: tle985x.h:8586
#define CPU_NVIC_ICPR_Int_MON_Msk
Definition: tle985x.h:8549
INLINE void EXINT2_Falling_Edge_Int_En(void)
Enables External Interrupt 2x on falling edge.
Definition: int.h:1978
INLINE void Int_MON_Pend_Set(void)
Sets Interrupt Pending for MONx.
Definition: int.h:2123
INLINE void Int_HS_Pend_Clr(void)
Clears Interrupt Pending for High-Side Switch.
Definition: int.h:2253
#define SCU_EXICON0_EXINT0_RE_Msk
External Interrupt 0 Rising Edge Bit Mask.
Definition: int.h:94
INLINE void Int_DU_Pend_Clr(void)
Clears Interrupt Pending for Differential Unit.
Definition: int.h:2243
INLINE void Int_CCU6SR3_Pend_Set(void)
Sets Interrupt Pending for CCU6 SR3.
Definition: int.h:2193
INLINE void Int_EXINT0_Pend_Clr(void)
Clears Interrupt Pending for EXINT0.
Definition: int.h:2283
INLINE void EXINT0_Falling_Edge_Int_Clr(void)
Clears Interrupt Flag for External Interrupt 0x on falling edge.
Definition: int.h:1993
INLINE void INT_Enable_Global_Int(void)
Enables the global interrupt IEN0.EA.
Definition: int.h:2383
INLINE void PENDSV_Pend_Set(void)
Sets PENDSV Pending.
Definition: int.h:2353
INLINE void NMI_STOF_En(void)
Enables Stack Overflow.
Definition: int.h:2103
INLINE void NMI_MAP_Int_Dis(void)
Disables NVM Map Error NMI.
Definition: int.h:2043
INLINE void NMI_WDT_Int_Dis(void)
Disables Watchdog Timer NMI.
Definition: int.h:2023
INLINE void Int_UART2_Pend_Clr(void)
Clears Interrupt Pending for UART2.
Definition: int.h:2288
INLINE void Int_EXINT1_Pend_Clr(void)
Clears Interrupt Pending for EXINT1.
Definition: int.h:2278
#define SCU_EXICON0_EXINT0_FE_Pos
External Interrupt 0 Falling Edge Bit Position.
Definition: int.h:96
INLINE void Int_SSC1_Pend_Set(void)
Sets Interrupt Pending for SSC1.
Definition: int.h:2188
INLINE void EXINT1_Rising_Edge_Int_Clr(void)
Clears Interrupt Flag for External Interrupt 1x on rising edge.
Definition: int.h:1998
INLINE void Int_CCU6SR1_Pend_Clr(void)
Clears Interrupt Pending for CCU6 SR1.
Definition: int.h:2318
INLINE void ECC_NVM_DoubleBit_Int_En(void)
Enables NVM Double Bit ECC Error Interrupt.
Definition: int.h:1903
INLINE void Int_OPA_Pend_Clr(void)
Clears Interrupt Pending for Current Sense Amplifier.
Definition: int.h:2248
INLINE void EXINT1_Rising_Edge_Int_Dis(void)
Disables External Interrupt 1x on rising edge.
Definition: int.h:1953
INLINE void NMI_OT_Int_En(void)
Enables NMI OT.
Definition: int.h:2068
INLINE void Int_GPT2_Pend_Set(void)
Sets Interrupt Pending for GPT2.
Definition: int.h:2223
#define SCU_EXICON0_EXINT2_FE_Msk
External Interrupt 2 Falling Edge Bit Mask.
Definition: int.h:114
INLINE void Global_Int_En(void)
Enables Global Interrupt (Pending interrupt requests are not blocked from the core).
Definition: int.h:1883
INLINE void EXINT0_Rising_Edge_Int_En(void)
Enables External Interrupt 0x on rising edge.
Definition: int.h:1928
#define SCU_EXICON0_EXINT1_FE_Msk
External Interrupt 1 Falling Edge Bit Mask.
Definition: int.h:106
#define SCU_EXICON0_EXINT1_RE_Msk
External Interrupt 1 Rising Edge Bit Mask.
Definition: int.h:102
INLINE void Int_MATHDIV_Pend_Set(void)
Sets Interrupt Pending for Math Divider.
Definition: int.h:2153
#define SCU_EXICON0_EXINT1_RE_Pos
External Interrupt 1 Rising Edge Bit Position.
Definition: int.h:100
INLINE void ECC_NVM_DoubleBit_Int_Clr(void)
Clears NVM Double Bit ECC Error Interrupt flag.
Definition: int.h:1923
INLINE void Int_CCU6SR2_Pend_Set(void)
Sets Interrupt Pending for CCU6 SR2.
Definition: int.h:2198
INLINE void Int_CP_Pend_Set(void)
Sets Interrupt Pending for Charge Pump.
Definition: int.h:2148
INLINE void EXINT0_Rising_Edge_Int_Clr(void)
Clears Interrupt Flag for External Interrupt 0x on rising edge.
Definition: int.h:1988
INLINE void Int_DU_Pend_Set(void)
Sets Interrupt Pending for Differential Unit.
Definition: int.h:2128
INLINE void Int_EXINT1_Pend_Set(void)
Sets Interrupt Pending for EXINT1.
Definition: int.h:2163
INLINE void ECC_RAM_SingleBit_Int_Clr(void)
Clears RAM Single Bit Error Status.
Definition: int.h:1913
#define SCU_NMISR_Msk
NMI Status Read Bit Mask.
Definition: int.h:117
INLINE void EXINT2_Rising_Edge_Int_Clr(void)
Clears Interrupt Flag for External Interrupt 2x on rising edge.
Definition: int.h:2008
INLINE void EXINT1_Falling_Edge_Int_En(void)
Enables External Interrupt 1x on falling edge.
Definition: int.h:1958
INLINE void NMI_SUP_Int_Dis(void)
Disables Supply Prewarning NMI.
Definition: int.h:2053
INLINE void NMI_WDT_Int_En(void)
Enables Watchdog Timer NMI.
Definition: int.h:2018
#define SCU_EXICON0_EXINT2_RE_Pos
External Interrupt 2 Rising Edge Bit Position.
Definition: int.h:108
INLINE void Int_BDRV_Pend_Clr(void)
Clears Interrupt Pending for Bridge Driver.
Definition: int.h:2258
INLINE void NMI_STOF_Int_En(void)
Enables Stack Overflow NMI.
Definition: int.h:2078
INLINE void Int_ADC2_Pend_Set(void)
Sets Interrupt Pending for ADC2.
Definition: int.h:2218
INLINE void NMI_WDT_Int_Clr(void)
Clears Watchdog Timer NMI Flag.
Definition: int.h:2088
INLINE void Int_UART1_Pend_Set(void)
Sets Interrupt Pending for UART1.
Definition: int.h:2178
INLINE void EXINT2_Rising_Edge_Int_En(void)
Enables External Interrupt 2x on rising edge.
Definition: int.h:1968
INLINE void ECC_RAM_DoubleBit_Int_Clr(void)
Clears RAM Double Bit ECC Error Interrupt flag.
Definition: int.h:1918
INLINE void SysTick_Pend_Clr(void)
Clears SysTick Exception Pending Status.
Definition: int.h:2368
void INT_Init(void)
Initializes the Interrupt module.
INLINE void Int_ADC1_Pend_Clr(void)
Clears Interrupt Pending for ADC1.
Definition: int.h:2328
INLINE void NMI_OT_Int_Dis(void)
Disables NMI OT.
Definition: int.h:2073
INLINE void PENDSV_Pend_Clr(void)
Clears PENDSV Pending Status.
Definition: int.h:2358
INLINE void ECC_RAM_DoubleBit_Int_En(void)
Enables RAM Double Bit ECC Error Interrupt.
Definition: int.h:1893
INLINE void NMI_STOF_Int_Dis(void)
Disables Stack Overflow NMI.
Definition: int.h:2083
INLINE void NMI_Pend_Set(void)
Sets NMI Pending.
Definition: int.h:2348
INLINE void Int_CCU6SR3_Pend_Clr(void)
Clears Interrupt Pending for CCU6 SR3.
Definition: int.h:2308
INLINE void Int_CCU6SR0_Pend_Set(void)
Sets Interrupt Pending for CCU6 SR0.
Definition: int.h:2208
INLINE void SysTick_Pend_Set(void)
Sets SysTick Exception Pending.
Definition: int.h:2363
#define SCU_EXICON0_EXINT0_FE_Msk
External Interrupt 0 Falling Edge Bit Mask.
Definition: int.h:98
INLINE void NMI_OWD_Int_Clr(void)
Clears Oscillator Watchdog NMI Flag.
Definition: int.h:2093
INLINE void NMI_OWD_Int_En(void)
Enables Oscillator Watchdog NMI.
Definition: int.h:2058
INLINE void Int_CCU6SR2_Pend_Clr(void)
Clears Interrupt Pending for CCU6 SR2.
Definition: int.h:2313
INLINE void EXINT2_Falling_Edge_Int_Clr(void)
Clears Interrupt Flag for External Interrupt 2x on falling edge.
Definition: int.h:2013
INLINE void Global_Int_Dis(void)
Disables Global Interrupt (All pending interrupt requests,except NMI, are blocked from the core).
Definition: int.h:1888
INLINE void NMI_ECC_Int_En(void)
Enables ECC Error NMI.
Definition: int.h:2028
INLINE void EXINT0_Rising_Edge_Int_Dis(void)
Disables External Interrupt 0x on rising edge.
Definition: int.h:1933
INLINE void Int_CCU6SR0_Pend_Clr(void)
Clears Interrupt Pending for CCU6 SR0.
Definition: int.h:2323
INLINE void EXINT1_Rising_Edge_Int_En(void)
Enables External Interrupt 1x on rising edge.
Definition: int.h:1948
INLINE void Int_ADC2_Pend_Clr(void)
Clears Interrupt Pending for ADC2.
Definition: int.h:2333
INLINE void Int_BDRV_Pend_Set(void)
Sets Interrupt Pending for Bridge Driver.
Definition: int.h:2143
INLINE void NMI_MAP_Int_En(void)
Enables NVM Map Error NMI.
Definition: int.h:2038
INLINE void Int_SSC2_Pend_Clr(void)
Clears Interrupt Pending for SSC2.
Definition: int.h:2298
INLINE void NMI_OWD_Int_Dis(void)
Disables Oscillator Watchdog NMI.
Definition: int.h:2063
INLINE void NMI_STOF_Int_Clr(void)
Clears Stack Overflow status.
Definition: int.h:2113
INLINE uint16 INT_Get_NMI_Status(void)
Reads out the NMI Status.
Definition: int.h:2373
INLINE void EXINT1_Falling_Edge_Int_Dis(void)
Disables External Interrupt 1x on falling edge.
Definition: int.h:1963
INLINE void NMI_MAP_Int_Clr(void)
Clears NVM Map Error NMI Flag.
Definition: int.h:2098
INLINE void Int_SSC2_Pend_Set(void)
Sets Interrupt Pending for SSC2.
Definition: int.h:2183
INLINE void Int_GPT1_Pend_Set(void)
Sets Interrupt Pending for GPT1.
Definition: int.h:2228
INLINE void Int_MATHDIV_Pend_Clr(void)
Clears Interrupt Pending for Math Divider.
Definition: int.h:2268
INLINE void NMI_STOF_Dis(void)
Disables Stack Overflow.
Definition: int.h:2108
INLINE void EXINT2_Rising_Edge_Int_Dis(void)
Disables External Interrupt 2x on rising edge.
Definition: int.h:1973
#define SCU_NMICLR_Msk
NMI Clear Bit Mask.
Definition: int.h:119
#define SCU_EXICON0_EXINT1_FE_Pos
External Interrupt 1 Falling Edge Bit Position.
Definition: int.h:104
INLINE void Int_OPA_Pend_Set(void)
Sets Interrupt Pending for Current Sense Amplifier.
Definition: int.h:2133
INLINE void Int_WAKEUP_Pend_Clr(void)
Clears Interrupt Pending for WAKEUP.
Definition: int.h:2273
#define SCU_EXICON0_EXINT2_FE_Pos
External Interrupt 2 Falling Edge Bit Position.
Definition: int.h:112
INLINE void Int_GPT1_Pend_Clr(void)
Clears Interrupt Pending Status for GPT1.
Definition: int.h:2343
INLINE void Int_EXINT0_Pend_Set(void)
Sets Interrupt Pending for EXINT0.
Definition: int.h:2168
INLINE void Int_PORT2_Pend_Clr(void)
Clears Interrupt Pending for PORT2.
Definition: int.h:2233
INLINE void ECC_RAM_DoubleBit_Int_Dis(void)
Disables RAM Double Bit ECC Error Interrupt.
Definition: int.h:1898
INLINE void EXINT0_Falling_Edge_Int_En(void)
Enables External Interrupt 0x on falling edge.
Definition: int.h:1938
INLINE void Int_HS_Pend_Set(void)
Sets Interrupt Pending for High-Side Switch.
Definition: int.h:2138
INLINE void EXINT0_Falling_Edge_Int_Dis(void)
Disables External Interrupt 0x on falling edge.
Definition: int.h:1943
INLINE void Int_PORT2_Pend_Set(void)
Sets Interrupt Pending for PORT2.
Definition: int.h:2118
#define SCU_EXICON0_EXINT2_RE_Msk
External Interrupt 2 Rising Edge Bit Mask.
Definition: int.h:110
INLINE void NMI_ECC_Int_Dis(void)
Disables ECC Error NMI.
Definition: int.h:2033
INLINE void Int_GPT2_Pend_Clr(void)
Clears Interrupt Pending for GPT2.
Definition: int.h:2338
INLINE void Int_ADC1_Pend_Set(void)
Sets Interrupt Pending for ADC1.
Definition: int.h:2213
INLINE void Int_SSC1_Pend_Clr(void)
Clears Interrupt Pending for SSC1.
Definition: int.h:2303
INLINE void Int_WAKEUP_Pend_Set(void)
Sets Interrupt Pending for WAKEUP.
Definition: int.h:2158
INLINE void Int_MON_Pend_Clr(void)
Clears Interrupt Pending for MONx.
Definition: int.h:2238
INLINE void ECC_NVM_DoubleBit_Int_Dis(void)
Disables NVM Double Bit ECC Error Interrupt.
Definition: int.h:1908
INLINE void Int_UART1_Pend_Clr(void)
Clears Interrupt Pending for UART1.
Definition: int.h:2293
INLINE void Int_CP_Pend_Clr(void)
Clears Interrupt Pending for Charge Pump.
Definition: int.h:2263
INLINE void EXINT1_Falling_Edge_Int_Clr(void)
Clears Interrupt Flag for External Interrupt 1x on falling edge.
Definition: int.h:2003
INLINE void Int_UART2_Pend_Set(void)
Sets Interrupt Pending for UART2.
Definition: int.h:2173
INLINE void Int_CCU6SR1_Pend_Set(void)
Sets Interrupt Pending for CCU6 SR1.
Definition: int.h:2203
INLINE void NMI_SUP_Int_En(void)
Enables Supply Prewarning NMI.
Definition: int.h:2048
INLINE void EXINT2_Falling_Edge_Int_Dis(void)
Disables External Interrupt 2x on falling edge.
Definition: int.h:1983
INLINE void INT_Disable_Global_Int(void)
Disables the global interrupt IEN0.EA.
Definition: int.h:2388
#define SCU_EXICON0_EXINT0_RE_Pos
External Interrupt 0 Rising Edge Bit Position.
Definition: int.h:92
INLINE void INT_Clr_NMI_Status(uint8 Flags)
Clears the NMI Status flags.
Definition: int.h:2378
SFR low level access library.
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:448
INLINE void Field_Wrt32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:358
INLINE void Field_Mod32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:378
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154