137 #define __CM0_REV 0x0000U
138 #define __NVIC_PRIO_BITS 2
139 #define __Vendor_SysTickConfig 0
140 #define __MPU_PRESENT 0
141 #define __FPU_PRESENT 0
146 #include "core_cm0.h"
159 #ifdef UNIT_TESTING_LV2
161 #define __IM volatile
169 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6000000)
170 #pragma clang diagnostic push
171 #pragma clang diagnostic ignored "-Wpadded"
172 #pragma clang diagnostic ignored "-Wcovered-switch-default"
173 #pragma clang diagnostic ignored "-Wself-assign"
2721 __IOM uint16_t CCS : 16;
2730 __IOM uint16_t CCS : 16;
2739 __IOM uint16_t CCS : 16;
2800 __IM uint16_t CCV : 16;
2809 __IM uint16_t CCV : 16;
2818 __IM uint16_t CCV : 16;
3172 __IOM uint32_t Int_GPT1 : 1;
3173 __IOM uint32_t Int_GPT2 : 1;
3174 __IOM uint32_t Int_ADC2 : 1;
3175 __IOM uint32_t Int_ADC1 : 1;
3176 __IOM uint32_t Int_CCU6SR0 : 1;
3177 __IOM uint32_t Int_CCU6SR1 : 1;
3178 __IOM uint32_t Int_CCU6SR2 : 1;
3179 __IOM uint32_t Int_CCU6SR3 : 1;
3180 __IOM uint32_t Int_SSC1 : 1;
3181 __IOM uint32_t Int_SSC2 : 1;
3182 __IOM uint32_t Int_UART1 : 1;
3183 __IOM uint32_t Int_UART2 : 1;
3184 __IOM uint32_t Int_EXINT0 : 1;
3185 __IOM uint32_t Int_EXINT1 : 1;
3186 __IOM uint32_t Int_WAKEUP : 1;
3187 __IOM uint32_t Int_MATHDIV : 1;
3189 __IOM uint32_t Int_CP : 1;
3190 __IOM uint32_t Int_BDRV : 1;
3191 __IOM uint32_t Int_HS : 1;
3192 __IOM uint32_t Int_OPA : 1;
3193 __IOM uint32_t Int_DU : 1;
3194 __IOM uint32_t Int_MON : 1;
3195 __IOM uint32_t Int_PORT2 : 1;
3204 __IOM uint32_t Int_GPT1 : 1;
3205 __IOM uint32_t Int_GPT2 : 1;
3206 __IOM uint32_t Int_ADC2 : 1;
3207 __IOM uint32_t Int_ADC1 : 1;
3208 __IOM uint32_t Int_CCU6SR0 : 1;
3209 __IOM uint32_t Int_CCU6SR1 : 1;
3210 __IOM uint32_t Int_CCU6SR2 : 1;
3211 __IOM uint32_t Int_CCU6SR3 : 1;
3212 __IOM uint32_t Int_SSC1 : 1;
3213 __IOM uint32_t Int_SSC2 : 1;
3214 __IOM uint32_t Int_UART1 : 1;
3215 __IOM uint32_t Int_UART2 : 1;
3216 __IOM uint32_t Int_EXINT0 : 1;
3217 __IOM uint32_t Int_EXINT1 : 1;
3218 __IOM uint32_t Int_WAKEUP : 1;
3219 __IOM uint32_t Int_MATHDIV : 1;
3221 __IOM uint32_t Int_CP : 1;
3222 __IOM uint32_t Int_BDRV : 1;
3223 __IOM uint32_t Int_HS : 1;
3224 __IOM uint32_t Int_OPA : 1;
3225 __IOM uint32_t Int_DU : 1;
3226 __IOM uint32_t Int_MON : 1;
3227 __IOM uint32_t Int_PORT2 : 1;
3236 __IOM uint32_t Int_GPT1 : 1;
3237 __IOM uint32_t Int_GPT2 : 1;
3238 __IOM uint32_t Int_ADC2 : 1;
3239 __IOM uint32_t Int_ADC1 : 1;
3240 __IOM uint32_t Int_CCU6SR0 : 1;
3241 __IOM uint32_t Int_CCU6SR1 : 1;
3242 __IOM uint32_t Int_CCU6SR2 : 1;
3243 __IOM uint32_t Int_CCU6SR3 : 1;
3244 __IOM uint32_t Int_SSC1 : 1;
3245 __IOM uint32_t Int_SSC2 : 1;
3246 __IOM uint32_t Int_UART1 : 1;
3247 __IOM uint32_t Int_UART2 : 1;
3248 __IOM uint32_t Int_EXINT0 : 1;
3249 __IOM uint32_t Int_EXINT1 : 1;
3250 __IOM uint32_t Int_WAKEUP : 1;
3251 __IOM uint32_t Int_MATHDIV : 1;
3253 __IOM uint32_t Int_CP : 1;
3254 __IOM uint32_t Int_BDRV : 1;
3255 __IOM uint32_t Int_HS : 1;
3256 __IOM uint32_t Int_OPA : 1;
3257 __IOM uint32_t Int_DU : 1;
3258 __IOM uint32_t Int_MON : 1;
3259 __IOM uint32_t Int_PORT2 : 1;
3896 __IOM uint32_t VAL : 32;
3912 __IM uint32_t VAL : 32;
4076 __IM uint32_t VDDEXT_OT : 1;
4337 __IOM uint32_t RI_0 : 1;
4338 __IOM uint32_t RI_1 : 1;
4339 __IOM uint32_t RI_2 : 1;
4341 __IOM uint32_t RI_4 : 1;
4343 __IOM uint32_t FA_0 : 1;
4344 __IOM uint32_t FA_1 : 1;
4345 __IOM uint32_t FA_2 : 1;
4347 __IOM uint32_t FA_4 : 1;
4349 __IOM uint32_t CYC_0 : 1;
4350 __IOM uint32_t CYC_1 : 1;
4351 __IOM uint32_t CYC_2 : 1;
4353 __IOM uint32_t CYC_4 : 1;
4401 __IOM uint32_t PP0 : 1;
4402 __IOM uint32_t PP1 : 1;
4403 __IOM uint32_t PP2 : 1;
4404 __IOM uint32_t PP3 : 1;
4405 __IOM uint32_t PP4 : 1;
4406 __IOM uint32_t PP5 : 1;
4427 __IOM uint32_t PP0 : 1;
4428 __IOM uint32_t PP1 : 1;
4429 __IOM uint32_t PP2 : 1;
4430 __IOM uint32_t PP3 : 1;
4431 __IOM uint32_t PP4 : 1;
4432 __IOM uint32_t PP5 : 1;
4440 __IOM uint32_t PP0 : 1;
4441 __IOM uint32_t PP1 : 1;
4442 __IOM uint32_t PP2 : 1;
4443 __IOM uint32_t PP3 : 1;
4444 __IOM uint32_t PP4 : 1;
4445 __IOM uint32_t PP5 : 1;
4453 __IOM uint32_t PP0 : 1;
4454 __IOM uint32_t PP1 : 1;
4455 __IOM uint32_t PP2 : 1;
4456 __IOM uint32_t PP3 : 1;
4457 __IOM uint32_t PP4 : 1;
4458 __IOM uint32_t PP5 : 1;
4466 __IOM uint32_t PP0 : 1;
4467 __IOM uint32_t PP1 : 1;
4468 __IOM uint32_t PP2 : 1;
4469 __IOM uint32_t PP3 : 1;
4470 __IOM uint32_t PP4 : 1;
4471 __IOM uint32_t PP5 : 1;
4479 __IOM uint32_t PP0 : 1;
4480 __IOM uint32_t PP1 : 1;
4481 __IOM uint32_t PP2 : 1;
4482 __IOM uint32_t PP3 : 1;
4483 __IOM uint32_t PP4 : 1;
4484 __IOM uint32_t PP5 : 1;
4493 __IOM uint32_t PP0 : 1;
4494 __IOM uint32_t PP1 : 1;
4495 __IOM uint32_t PP2 : 1;
4497 __IOM uint32_t PP4 : 1;
4499 __IM uint32_t PP0_STS : 1;
4501 __IM uint32_t PP1_STS : 1;
4503 __IM uint32_t PP2_STS : 1;
4506 __IM uint32_t PP4_STS : 1;
4515 __IOM uint32_t PP0 : 1;
4516 __IOM uint32_t PP1 : 1;
4517 __IOM uint32_t PP2 : 1;
4519 __IOM uint32_t PP4 : 1;
4521 __IOM uint32_t PP0_INEN : 1;
4523 __IOM uint32_t PP1_INEN : 1;
4525 __IOM uint32_t PP2_INEN : 1;
4528 __IOM uint32_t PP4_INEN : 1;
4537 __IOM uint32_t PP0 : 1;
4538 __IOM uint32_t PP1 : 1;
4539 __IOM uint32_t PP2 : 1;
4541 __IOM uint32_t PP4 : 1;
4549 __IOM uint32_t PP0 : 1;
4550 __IOM uint32_t PP1 : 1;
4551 __IOM uint32_t PP2 : 1;
4553 __IOM uint32_t PP4 : 1;
4561 __IOM uint32_t PP0 : 1;
4562 __IOM uint32_t PP1 : 1;
4563 __IOM uint32_t PP2 : 1;
4565 __IOM uint32_t PP4 : 1;
4573 __IOM uint32_t PP0 : 1;
4574 __IOM uint32_t PP1 : 1;
4575 __IOM uint32_t PP2 : 1;
4577 __IOM uint32_t PP4 : 1;
4585 __IOM uint32_t PP0 : 1;
4586 __IOM uint32_t PP1 : 1;
4587 __IOM uint32_t PP2 : 1;
4589 __IOM uint32_t PP4 : 1;
4598 __IOM uint32_t PP0 : 1;
4599 __IOM uint32_t PP1 : 1;
4600 __IOM uint32_t PP2 : 1;
4601 __IOM uint32_t PP3 : 1;
4611 __IOM uint32_t PP0 : 1;
4612 __IOM uint32_t PP1 : 1;
4613 __IOM uint32_t PP2 : 1;
4614 __IOM uint32_t PP3 : 1;
4616 __IOM uint32_t PP7 : 1;
4625 __IOM uint32_t PP0 : 1;
4626 __IOM uint32_t PP1 : 1;
4627 __IOM uint32_t PP2 : 1;
4628 __IOM uint32_t PP3 : 1;
4630 __IOM uint32_t PP7 : 1;
4638 __IOM uint32_t PP0 : 1;
4639 __IOM uint32_t PP1 : 1;
4640 __IOM uint32_t PP2 : 1;
4641 __IOM uint32_t PP3 : 1;
4643 __IOM uint32_t PP7 : 1;
5673 } SYS_SUPPLY_IRQ_STS;
5693 } SYS_SUPPLY_IRQ_CTRL;
5727 } SYS_SUPPLY_IRQ_CLR;
6231 #define ADC1_BASE 0x40004000UL
6232 #define ADC2_BASE 0x4801C000UL
6233 #define BDRV_BASE 0x40034000UL
6234 #define CCU6_BASE 0x4000C000UL
6235 #define CPU_BASE 0xE000E000UL
6236 #define GPT12E_BASE 0x40010000UL
6237 #define HS_BASE 0x40024000UL
6238 #define LIN_BASE 0x4801E000UL
6239 #define MATH_BASE 0x48013000UL
6240 #define MF_BASE 0x48018000UL
6241 #define PMU_BASE 0x50004000UL
6242 #define PORT_BASE 0x48028000UL
6243 #define SCU_BASE 0x50005000UL
6244 #define SCUPM_BASE 0x50006000UL
6245 #define SSC1_BASE 0x48024000UL
6246 #define SSC2_BASE 0x48026000UL
6247 #define TIMER2_BASE 0x48004000UL
6248 #define TIMER21_BASE 0x48005000UL
6249 #define UART1_BASE 0x48020000UL
6250 #define UART2_BASE 0x48022000UL
6264 #ifndef UNIT_TESTING_LV2
6265 #define ADC1 ((ADC1_Type*) ADC1_BASE)
6266 #define ADC2 ((ADC2_Type*) ADC2_BASE)
6267 #define BDRV ((BDRV_Type*) BDRV_BASE)
6268 #define CCU6 ((CCU6_Type*) CCU6_BASE)
6269 #define CPU ((CPU_Type*) CPU_BASE)
6270 #define GPT12E ((GPT12E_Type*) GPT12E_BASE)
6271 #define HS ((HS_Type*) HS_BASE)
6272 #define LIN ((LIN_Type*) LIN_BASE)
6273 #define MATH ((MATH_Type*) MATH_BASE)
6274 #define MF ((MF_Type*) MF_BASE)
6275 #define PMU ((PMU_Type*) PMU_BASE)
6276 #define PORT ((PORT_Type*) PORT_BASE)
6277 #define SCU ((SCU_Type*) SCU_BASE)
6278 #define SCUPM ((SCUPM_Type*) SCUPM_BASE)
6279 #define SSC1 ((SSC1_Type*) SSC1_BASE)
6280 #define SSC2 ((SSC2_Type*) SSC2_BASE)
6281 #define TIMER2 ((TIMER2_Type*) TIMER2_BASE)
6282 #define TIMER21 ((TIMER21_Type*) TIMER21_BASE)
6283 #define UART1 ((UART1_Type*) UART1_BASE)
6284 #define UART2 ((UART2_Type*) UART2_BASE)
6327 #define ADC1_CAL_CH0_1_CALGAIN_CH1_Pos (24UL)
6328 #define ADC1_CAL_CH0_1_CALGAIN_CH1_Msk (0xff000000UL)
6329 #define ADC1_CAL_CH0_1_CALOFFS_CH1_Pos (16UL)
6330 #define ADC1_CAL_CH0_1_CALOFFS_CH1_Msk (0x1f0000UL)
6331 #define ADC1_CAL_CH0_1_CALGAIN_CH0_Pos (8UL)
6332 #define ADC1_CAL_CH0_1_CALGAIN_CH0_Msk (0xff00UL)
6333 #define ADC1_CAL_CH0_1_CALOFFS_CH0_Pos (0UL)
6334 #define ADC1_CAL_CH0_1_CALOFFS_CH0_Msk (0x1fUL)
6336 #define ADC1_CAL_CH10_11_CALGAIN_CH11_Pos (24UL)
6337 #define ADC1_CAL_CH10_11_CALGAIN_CH11_Msk (0xff000000UL)
6338 #define ADC1_CAL_CH10_11_CALOFFS_CH11_Pos (16UL)
6339 #define ADC1_CAL_CH10_11_CALOFFS_CH11_Msk (0x1f0000UL)
6340 #define ADC1_CAL_CH10_11_CALGAIN_CH10_Pos (8UL)
6341 #define ADC1_CAL_CH10_11_CALGAIN_CH10_Msk (0xff00UL)
6342 #define ADC1_CAL_CH10_11_CALOFFS_CH10_Pos (0UL)
6343 #define ADC1_CAL_CH10_11_CALOFFS_CH10_Msk (0x1fUL)
6345 #define ADC1_CAL_CH12_13_CALGAIN_CH13_Pos (24UL)
6346 #define ADC1_CAL_CH12_13_CALGAIN_CH13_Msk (0xff000000UL)
6347 #define ADC1_CAL_CH12_13_CALOFFS_CH13_Pos (16UL)
6348 #define ADC1_CAL_CH12_13_CALOFFS_CH13_Msk (0x1f0000UL)
6349 #define ADC1_CAL_CH12_13_CALGAIN_CH12_Pos (8UL)
6350 #define ADC1_CAL_CH12_13_CALGAIN_CH12_Msk (0xff00UL)
6351 #define ADC1_CAL_CH12_13_CALOFFS_CH12_Pos (0UL)
6352 #define ADC1_CAL_CH12_13_CALOFFS_CH12_Msk (0x1fUL)
6354 #define ADC1_CAL_CH2_3_CALGAIN_CH3_Pos (24UL)
6355 #define ADC1_CAL_CH2_3_CALGAIN_CH3_Msk (0xff000000UL)
6356 #define ADC1_CAL_CH2_3_CALOFFS_CH3_Pos (16UL)
6357 #define ADC1_CAL_CH2_3_CALOFFS_CH3_Msk (0x1f0000UL)
6358 #define ADC1_CAL_CH2_3_CALGAIN_CH2_Pos (8UL)
6359 #define ADC1_CAL_CH2_3_CALGAIN_CH2_Msk (0xff00UL)
6360 #define ADC1_CAL_CH2_3_CALOFFS_CH2_Pos (0UL)
6361 #define ADC1_CAL_CH2_3_CALOFFS_CH2_Msk (0x1fUL)
6363 #define ADC1_CAL_CH4_5_CALGAIN_CH5_Pos (24UL)
6364 #define ADC1_CAL_CH4_5_CALGAIN_CH5_Msk (0xff000000UL)
6365 #define ADC1_CAL_CH4_5_CALOFFS_CH5_Pos (16UL)
6366 #define ADC1_CAL_CH4_5_CALOFFS_CH5_Msk (0x1f0000UL)
6367 #define ADC1_CAL_CH4_5_CALGAIN_CH4_Pos (8UL)
6368 #define ADC1_CAL_CH4_5_CALGAIN_CH4_Msk (0xff00UL)
6369 #define ADC1_CAL_CH4_5_CALOFFS_CH4_Pos (0UL)
6370 #define ADC1_CAL_CH4_5_CALOFFS_CH4_Msk (0x1fUL)
6372 #define ADC1_CAL_CH6_7_CALGAIN_CH7_Pos (24UL)
6373 #define ADC1_CAL_CH6_7_CALGAIN_CH7_Msk (0xff000000UL)
6374 #define ADC1_CAL_CH6_7_CALOFFS_CH7_Pos (16UL)
6375 #define ADC1_CAL_CH6_7_CALOFFS_CH7_Msk (0x1f0000UL)
6376 #define ADC1_CAL_CH6_7_CALGAIN_CH6_Pos (8UL)
6377 #define ADC1_CAL_CH6_7_CALGAIN_CH6_Msk (0xff00UL)
6378 #define ADC1_CAL_CH6_7_CALOFFS_CH6_Pos (0UL)
6379 #define ADC1_CAL_CH6_7_CALOFFS_CH6_Msk (0x1fUL)
6381 #define ADC1_CAL_CH8_9_CALGAIN_CH9_Pos (24UL)
6382 #define ADC1_CAL_CH8_9_CALGAIN_CH9_Msk (0xff000000UL)
6383 #define ADC1_CAL_CH8_9_CALOFFS_CH9_Pos (16UL)
6384 #define ADC1_CAL_CH8_9_CALOFFS_CH9_Msk (0x1f0000UL)
6385 #define ADC1_CAL_CH8_9_CALGAIN_CH8_Pos (8UL)
6386 #define ADC1_CAL_CH8_9_CALGAIN_CH8_Msk (0xff00UL)
6387 #define ADC1_CAL_CH8_9_CALOFFS_CH8_Pos (0UL)
6388 #define ADC1_CAL_CH8_9_CALOFFS_CH8_Msk (0x1fUL)
6390 #define ADC1_CHx_EIM_ADC1_EIM_TRIG_SEL_Pos (16UL)
6391 #define ADC1_CHx_EIM_ADC1_EIM_TRIG_SEL_Msk (0x70000UL)
6392 #define ADC1_CHx_EIM_EIM_EN_Pos (11UL)
6393 #define ADC1_CHx_EIM_EIM_EN_Msk (0x800UL)
6394 #define ADC1_CHx_EIM_EIM_REP_Pos (8UL)
6395 #define ADC1_CHx_EIM_EIM_REP_Msk (0x700UL)
6396 #define ADC1_CHx_EIM_EIM_CHx_Pos (0UL)
6397 #define ADC1_CHx_EIM_EIM_CHx_Msk (0xfUL)
6399 #define ADC1_CHx_ESM_ESM_STS_Pos (31UL)
6400 #define ADC1_CHx_ESM_ESM_STS_Msk (0x80000000UL)
6401 #define ADC1_CHx_ESM_ESM_EN_Pos (30UL)
6402 #define ADC1_CHx_ESM_ESM_EN_Msk (0x40000000UL)
6403 #define ADC1_CHx_ESM_ADC1_ESM_TRIG_SEL_Pos (16UL)
6404 #define ADC1_CHx_ESM_ADC1_ESM_TRIG_SEL_Msk (0x70000UL)
6405 #define ADC1_CHx_ESM_ESM_0_Pos (0UL)
6406 #define ADC1_CHx_ESM_ESM_0_Msk (0x3fffUL)
6408 #define ADC1_CNT0_3_LOWER_HYST_LO_PP3_Pos (27UL)
6409 #define ADC1_CNT0_3_LOWER_HYST_LO_PP3_Msk (0x18000000UL)
6410 #define ADC1_CNT0_3_LOWER_CNT_LO_PP3_Pos (24UL)
6411 #define ADC1_CNT0_3_LOWER_CNT_LO_PP3_Msk (0x3000000UL)
6412 #define ADC1_CNT0_3_LOWER_HYST_LO_PP2_Pos (19UL)
6413 #define ADC1_CNT0_3_LOWER_HYST_LO_PP2_Msk (0x180000UL)
6414 #define ADC1_CNT0_3_LOWER_CNT_LO_PP2_Pos (16UL)
6415 #define ADC1_CNT0_3_LOWER_CNT_LO_PP2_Msk (0x30000UL)
6416 #define ADC1_CNT0_3_LOWER_HYST_LO_PP1_Pos (11UL)
6417 #define ADC1_CNT0_3_LOWER_HYST_LO_PP1_Msk (0x1800UL)
6418 #define ADC1_CNT0_3_LOWER_CNT_LO_PP1_Pos (8UL)
6419 #define ADC1_CNT0_3_LOWER_CNT_LO_PP1_Msk (0x300UL)
6420 #define ADC1_CNT0_3_LOWER_HYST_LO_PP0_Pos (3UL)
6421 #define ADC1_CNT0_3_LOWER_HYST_LO_PP0_Msk (0x18UL)
6422 #define ADC1_CNT0_3_LOWER_CNT_LO_PP0_Pos (0UL)
6423 #define ADC1_CNT0_3_LOWER_CNT_LO_PP0_Msk (0x3UL)
6425 #define ADC1_CNT0_3_UPPER_HYST_UP_PP3_Pos (27UL)
6426 #define ADC1_CNT0_3_UPPER_HYST_UP_PP3_Msk (0x18000000UL)
6427 #define ADC1_CNT0_3_UPPER_CNT_UP_PP3_Pos (24UL)
6428 #define ADC1_CNT0_3_UPPER_CNT_UP_PP3_Msk (0x3000000UL)
6429 #define ADC1_CNT0_3_UPPER_HYST_UP_PP2_Pos (19UL)
6430 #define ADC1_CNT0_3_UPPER_HYST_UP_PP2_Msk (0x180000UL)
6431 #define ADC1_CNT0_3_UPPER_CNT_UP_PP2_Pos (16UL)
6432 #define ADC1_CNT0_3_UPPER_CNT_UP_PP2_Msk (0x30000UL)
6433 #define ADC1_CNT0_3_UPPER_HYST_UP_PP1_Pos (11UL)
6434 #define ADC1_CNT0_3_UPPER_HYST_UP_PP1_Msk (0x1800UL)
6435 #define ADC1_CNT0_3_UPPER_CNT_UP_PP1_Pos (8UL)
6436 #define ADC1_CNT0_3_UPPER_CNT_UP_PP1_Msk (0x300UL)
6437 #define ADC1_CNT0_3_UPPER_HYST_UP_PP0_Pos (3UL)
6438 #define ADC1_CNT0_3_UPPER_HYST_UP_PP0_Msk (0x18UL)
6439 #define ADC1_CNT0_3_UPPER_CNT_UP_PP0_Pos (0UL)
6440 #define ADC1_CNT0_3_UPPER_CNT_UP_PP0_Msk (0x3UL)
6442 #define ADC1_CNT4_7_LOWER_HYST_LO_PP7_Pos (27UL)
6443 #define ADC1_CNT4_7_LOWER_HYST_LO_PP7_Msk (0x18000000UL)
6444 #define ADC1_CNT4_7_LOWER_CNT_LO_PP7_Pos (24UL)
6445 #define ADC1_CNT4_7_LOWER_CNT_LO_PP7_Msk (0x3000000UL)
6446 #define ADC1_CNT4_7_LOWER_HYST_LO_PP6_Pos (19UL)
6447 #define ADC1_CNT4_7_LOWER_HYST_LO_PP6_Msk (0x180000UL)
6448 #define ADC1_CNT4_7_LOWER_CNT_LO_PP6_Pos (16UL)
6449 #define ADC1_CNT4_7_LOWER_CNT_LO_PP6_Msk (0x30000UL)
6450 #define ADC1_CNT4_7_LOWER_HYST_LO_PP5_Pos (11UL)
6451 #define ADC1_CNT4_7_LOWER_HYST_LO_PP5_Msk (0x1800UL)
6452 #define ADC1_CNT4_7_LOWER_CNT_LO_PP5_Pos (8UL)
6453 #define ADC1_CNT4_7_LOWER_CNT_LO_PP5_Msk (0x300UL)
6454 #define ADC1_CNT4_7_LOWER_HYST_LO_PP4_Pos (3UL)
6455 #define ADC1_CNT4_7_LOWER_HYST_LO_PP4_Msk (0x18UL)
6456 #define ADC1_CNT4_7_LOWER_CNT_LO_PP4_Pos (0UL)
6457 #define ADC1_CNT4_7_LOWER_CNT_LO_PP4_Msk (0x3UL)
6459 #define ADC1_CNT4_7_UPPER_HYST_UP_PP7_Pos (27UL)
6460 #define ADC1_CNT4_7_UPPER_HYST_UP_PP7_Msk (0x18000000UL)
6461 #define ADC1_CNT4_7_UPPER_CNT_UP_PP7_Pos (24UL)
6462 #define ADC1_CNT4_7_UPPER_CNT_UP_PP7_Msk (0x3000000UL)
6463 #define ADC1_CNT4_7_UPPER_HYST_UP_PP6_Pos (19UL)
6464 #define ADC1_CNT4_7_UPPER_HYST_UP_PP6_Msk (0x180000UL)
6465 #define ADC1_CNT4_7_UPPER_CNT_UP_PP6_Pos (16UL)
6466 #define ADC1_CNT4_7_UPPER_CNT_UP_PP6_Msk (0x30000UL)
6467 #define ADC1_CNT4_7_UPPER_HYST_UP_PP5_Pos (11UL)
6468 #define ADC1_CNT4_7_UPPER_HYST_UP_PP5_Msk (0x1800UL)
6469 #define ADC1_CNT4_7_UPPER_CNT_UP_PP5_Pos (8UL)
6470 #define ADC1_CNT4_7_UPPER_CNT_UP_PP5_Msk (0x300UL)
6471 #define ADC1_CNT4_7_UPPER_HYST_UP_PP4_Pos (3UL)
6472 #define ADC1_CNT4_7_UPPER_HYST_UP_PP4_Msk (0x18UL)
6473 #define ADC1_CNT4_7_UPPER_CNT_UP_PP4_Pos (0UL)
6474 #define ADC1_CNT4_7_UPPER_CNT_UP_PP4_Msk (0x3UL)
6476 #define ADC1_CTRL2_CAL_EN_Pos (0UL)
6477 #define ADC1_CTRL2_CAL_EN_Msk (0x3fffUL)
6479 #define ADC1_CTRL3_SAMPLE_TIME_LVCH_Pos (16UL)
6480 #define ADC1_CTRL3_SAMPLE_TIME_LVCH_Msk (0xf0000UL)
6481 #define ADC1_CTRL3_SAMPLE_TIME_HVCH_Pos (8UL)
6482 #define ADC1_CTRL3_SAMPLE_TIME_HVCH_Msk (0x1f00UL)
6483 #define ADC1_CTRL3_MCM_RDY_Pos (7UL)
6484 #define ADC1_CTRL3_MCM_RDY_Msk (0x80UL)
6485 #define ADC1_CTRL3_EoC_FAIL_Pos (6UL)
6486 #define ADC1_CTRL3_EoC_FAIL_Msk (0x40UL)
6487 #define ADC1_CTRL3_EoC_FAIL_CLR_Pos (4UL)
6488 #define ADC1_CTRL3_EoC_FAIL_CLR_Msk (0x10UL)
6489 #define ADC1_CTRL3_SW_MODE_Pos (1UL)
6490 #define ADC1_CTRL3_SW_MODE_Msk (0x2UL)
6491 #define ADC1_CTRL3_MCM_PD_N_Pos (0UL)
6492 #define ADC1_CTRL3_MCM_PD_N_Msk (0x1UL)
6494 #define ADC1_CTRL5_FILT_OUT_SEL_13_0_Pos (0UL)
6495 #define ADC1_CTRL5_FILT_OUT_SEL_13_0_Msk (0x3fffUL)
6497 #define ADC1_CTRL_STS_STRTUP_DIS_Pos (18UL)
6498 #define ADC1_CTRL_STS_STRTUP_DIS_Msk (0x40000UL)
6499 #define ADC1_CTRL_STS_SW_CH_SEL_Pos (8UL)
6500 #define ADC1_CTRL_STS_SW_CH_SEL_Msk (0xf00UL)
6501 #define ADC1_CTRL_STS_EOC_Pos (7UL)
6502 #define ADC1_CTRL_STS_EOC_Msk (0x80UL)
6503 #define ADC1_CTRL_STS_CAL_SIGN_Pos (5UL)
6504 #define ADC1_CTRL_STS_CAL_SIGN_Msk (0x20UL)
6505 #define ADC1_CTRL_STS_READY_Pos (4UL)
6506 #define ADC1_CTRL_STS_READY_Msk (0x10UL)
6507 #define ADC1_CTRL_STS_SOS_Pos (2UL)
6508 #define ADC1_CTRL_STS_SOS_Msk (0x4UL)
6509 #define ADC1_CTRL_STS_SOOC_Pos (1UL)
6510 #define ADC1_CTRL_STS_SOOC_Msk (0x2UL)
6511 #define ADC1_CTRL_STS_PD_N_Pos (0UL)
6512 #define ADC1_CTRL_STS_PD_N_Msk (0x1UL)
6514 #define ADC1_DCHCNT1_4_LOWER_HYST_LO_DCH1_Pos (3UL)
6515 #define ADC1_DCHCNT1_4_LOWER_HYST_LO_DCH1_Msk (0x18UL)
6516 #define ADC1_DCHCNT1_4_LOWER_CNT_LO_DCH1_Pos (0UL)
6517 #define ADC1_DCHCNT1_4_LOWER_CNT_LO_DCH1_Msk (0x3UL)
6519 #define ADC1_DCHCNT1_4_UPPER_HYST_UP_DCH1_Pos (3UL)
6520 #define ADC1_DCHCNT1_4_UPPER_HYST_UP_DCH1_Msk (0x18UL)
6521 #define ADC1_DCHCNT1_4_UPPER_CNT_UP_DCH1_Pos (0UL)
6522 #define ADC1_DCHCNT1_4_UPPER_CNT_UP_DCH1_Msk (0x3UL)
6524 #define ADC1_DCHTH1_4_LOWER_DCH1_LOW_Pos (0UL)
6525 #define ADC1_DCHTH1_4_LOWER_DCH1_LOW_Msk (0xffUL)
6527 #define ADC1_DCHTH1_4_UPPER_DCH1_UP_Pos (0UL)
6528 #define ADC1_DCHTH1_4_UPPER_DCH1_UP_Msk (0xffUL)
6530 #define ADC1_DIFFCH_OUT1_DOF1_Pos (18UL)
6531 #define ADC1_DIFFCH_OUT1_DOF1_Msk (0x40000UL)
6532 #define ADC1_DIFFCH_OUT1_DVF1_Pos (17UL)
6533 #define ADC1_DIFFCH_OUT1_DVF1_Msk (0x20000UL)
6534 #define ADC1_DIFFCH_OUT1_DWFR1_Pos (16UL)
6535 #define ADC1_DIFFCH_OUT1_DWFR1_Msk (0x10000UL)
6536 #define ADC1_DIFFCH_OUT1_DCH1_Pos (0UL)
6537 #define ADC1_DIFFCH_OUT1_DCH1_Msk (0xfffUL)
6539 #define ADC1_DUIN_SEL_DU1RES_NEG_Pos (4UL)
6540 #define ADC1_DUIN_SEL_DU1RES_NEG_Msk (0x10UL)
6541 #define ADC1_DUIN_SEL_DU1_EN_Pos (0UL)
6542 #define ADC1_DUIN_SEL_DU1_EN_Msk (0x1UL)
6544 #define ADC1_FILT_OUT0_OF0_Pos (18UL)
6545 #define ADC1_FILT_OUT0_OF0_Msk (0x40000UL)
6546 #define ADC1_FILT_OUT0_VF0_Pos (17UL)
6547 #define ADC1_FILT_OUT0_VF0_Msk (0x20000UL)
6548 #define ADC1_FILT_OUT0_WFR0_Pos (16UL)
6549 #define ADC1_FILT_OUT0_WFR0_Msk (0x10000UL)
6550 #define ADC1_FILT_OUT0_FILT_OUT_CH0_Pos (0UL)
6551 #define ADC1_FILT_OUT0_FILT_OUT_CH0_Msk (0xfffUL)
6553 #define ADC1_FILT_OUT1_OF1_Pos (18UL)
6554 #define ADC1_FILT_OUT1_OF1_Msk (0x40000UL)
6555 #define ADC1_FILT_OUT1_VF1_Pos (17UL)
6556 #define ADC1_FILT_OUT1_VF1_Msk (0x20000UL)
6557 #define ADC1_FILT_OUT1_WFR1_Pos (16UL)
6558 #define ADC1_FILT_OUT1_WFR1_Msk (0x10000UL)
6559 #define ADC1_FILT_OUT1_FILT_OUT_CH1_Pos (0UL)
6560 #define ADC1_FILT_OUT1_FILT_OUT_CH1_Msk (0xfffUL)
6562 #define ADC1_FILT_OUT10_OF10_Pos (18UL)
6563 #define ADC1_FILT_OUT10_OF10_Msk (0x40000UL)
6564 #define ADC1_FILT_OUT10_VF10_Pos (17UL)
6565 #define ADC1_FILT_OUT10_VF10_Msk (0x20000UL)
6566 #define ADC1_FILT_OUT10_WFR10_Pos (16UL)
6567 #define ADC1_FILT_OUT10_WFR10_Msk (0x10000UL)
6568 #define ADC1_FILT_OUT10_FILT_OUT_CH10_Pos (0UL)
6569 #define ADC1_FILT_OUT10_FILT_OUT_CH10_Msk (0xfffUL)
6571 #define ADC1_FILT_OUT11_OF11_Pos (18UL)
6572 #define ADC1_FILT_OUT11_OF11_Msk (0x40000UL)
6573 #define ADC1_FILT_OUT11_VF11_Pos (17UL)
6574 #define ADC1_FILT_OUT11_VF11_Msk (0x20000UL)
6575 #define ADC1_FILT_OUT11_WFR11_Pos (16UL)
6576 #define ADC1_FILT_OUT11_WFR11_Msk (0x10000UL)
6577 #define ADC1_FILT_OUT11_FILT_OUT_CH11_Pos (0UL)
6578 #define ADC1_FILT_OUT11_FILT_OUT_CH11_Msk (0xfffUL)
6580 #define ADC1_FILT_OUT12_OF12_Pos (18UL)
6581 #define ADC1_FILT_OUT12_OF12_Msk (0x40000UL)
6582 #define ADC1_FILT_OUT12_VF12_Pos (17UL)
6583 #define ADC1_FILT_OUT12_VF12_Msk (0x20000UL)
6584 #define ADC1_FILT_OUT12_WFR12_Pos (16UL)
6585 #define ADC1_FILT_OUT12_WFR12_Msk (0x10000UL)
6586 #define ADC1_FILT_OUT12_FILT_OUT_CH12_Pos (0UL)
6587 #define ADC1_FILT_OUT12_FILT_OUT_CH12_Msk (0xfffUL)
6589 #define ADC1_FILT_OUT13_OF13_Pos (18UL)
6590 #define ADC1_FILT_OUT13_OF13_Msk (0x40000UL)
6591 #define ADC1_FILT_OUT13_VF13_Pos (17UL)
6592 #define ADC1_FILT_OUT13_VF13_Msk (0x20000UL)
6593 #define ADC1_FILT_OUT13_WFR13_Pos (16UL)
6594 #define ADC1_FILT_OUT13_WFR13_Msk (0x10000UL)
6595 #define ADC1_FILT_OUT13_FILT_OUT_CH13_Pos (0UL)
6596 #define ADC1_FILT_OUT13_FILT_OUT_CH13_Msk (0xfffUL)
6598 #define ADC1_FILT_OUT2_OF2_Pos (18UL)
6599 #define ADC1_FILT_OUT2_OF2_Msk (0x40000UL)
6600 #define ADC1_FILT_OUT2_VF2_Pos (17UL)
6601 #define ADC1_FILT_OUT2_VF2_Msk (0x20000UL)
6602 #define ADC1_FILT_OUT2_WFR2_Pos (16UL)
6603 #define ADC1_FILT_OUT2_WFR2_Msk (0x10000UL)
6604 #define ADC1_FILT_OUT2_FILT_OUT_CH2_Pos (0UL)
6605 #define ADC1_FILT_OUT2_FILT_OUT_CH2_Msk (0xfffUL)
6607 #define ADC1_FILT_OUT3_OF3_Pos (18UL)
6608 #define ADC1_FILT_OUT3_OF3_Msk (0x40000UL)
6609 #define ADC1_FILT_OUT3_VF3_Pos (17UL)
6610 #define ADC1_FILT_OUT3_VF3_Msk (0x20000UL)
6611 #define ADC1_FILT_OUT3_WFR3_Pos (16UL)
6612 #define ADC1_FILT_OUT3_WFR3_Msk (0x10000UL)
6613 #define ADC1_FILT_OUT3_FILT_OUT_CH3_Pos (0UL)
6614 #define ADC1_FILT_OUT3_FILT_OUT_CH3_Msk (0xfffUL)
6616 #define ADC1_FILT_OUT4_OF4_Pos (18UL)
6617 #define ADC1_FILT_OUT4_OF4_Msk (0x40000UL)
6618 #define ADC1_FILT_OUT4_VF4_Pos (17UL)
6619 #define ADC1_FILT_OUT4_VF4_Msk (0x20000UL)
6620 #define ADC1_FILT_OUT4_WFR4_Pos (16UL)
6621 #define ADC1_FILT_OUT4_WFR4_Msk (0x10000UL)
6622 #define ADC1_FILT_OUT4_FILT_OUT_CH4_Pos (0UL)
6623 #define ADC1_FILT_OUT4_FILT_OUT_CH4_Msk (0xfffUL)
6625 #define ADC1_FILT_OUT5_OF5_Pos (18UL)
6626 #define ADC1_FILT_OUT5_OF5_Msk (0x40000UL)
6627 #define ADC1_FILT_OUT5_VF5_Pos (17UL)
6628 #define ADC1_FILT_OUT5_VF5_Msk (0x20000UL)
6629 #define ADC1_FILT_OUT5_WFR5_Pos (16UL)
6630 #define ADC1_FILT_OUT5_WFR5_Msk (0x10000UL)
6631 #define ADC1_FILT_OUT5_FILT_OUT_CH5_Pos (0UL)
6632 #define ADC1_FILT_OUT5_FILT_OUT_CH5_Msk (0xfffUL)
6634 #define ADC1_FILT_OUT6_OF6_Pos (18UL)
6635 #define ADC1_FILT_OUT6_OF6_Msk (0x40000UL)
6636 #define ADC1_FILT_OUT6_VF6_Pos (17UL)
6637 #define ADC1_FILT_OUT6_VF6_Msk (0x20000UL)
6638 #define ADC1_FILT_OUT6_WFR6_Pos (16UL)
6639 #define ADC1_FILT_OUT6_WFR6_Msk (0x10000UL)
6640 #define ADC1_FILT_OUT6_FILT_OUT_CH6_Pos (0UL)
6641 #define ADC1_FILT_OUT6_FILT_OUT_CH6_Msk (0xfffUL)
6643 #define ADC1_FILT_OUT7_OF7_Pos (18UL)
6644 #define ADC1_FILT_OUT7_OF7_Msk (0x40000UL)
6645 #define ADC1_FILT_OUT7_VF7_Pos (17UL)
6646 #define ADC1_FILT_OUT7_VF7_Msk (0x20000UL)
6647 #define ADC1_FILT_OUT7_WFR7_Pos (16UL)
6648 #define ADC1_FILT_OUT7_WFR7_Msk (0x10000UL)
6649 #define ADC1_FILT_OUT7_FILT_OUT_CH7_Pos (0UL)
6650 #define ADC1_FILT_OUT7_FILT_OUT_CH7_Msk (0xfffUL)
6652 #define ADC1_FILT_OUT8_OF8_Pos (18UL)
6653 #define ADC1_FILT_OUT8_OF8_Msk (0x40000UL)
6654 #define ADC1_FILT_OUT8_VF8_Pos (17UL)
6655 #define ADC1_FILT_OUT8_VF8_Msk (0x20000UL)
6656 #define ADC1_FILT_OUT8_WFR8_Pos (16UL)
6657 #define ADC1_FILT_OUT8_WFR8_Msk (0x10000UL)
6658 #define ADC1_FILT_OUT8_FILT_OUT_CH8_Pos (0UL)
6659 #define ADC1_FILT_OUT8_FILT_OUT_CH8_Msk (0xfffUL)
6661 #define ADC1_FILT_OUT9_OF9_Pos (18UL)
6662 #define ADC1_FILT_OUT9_OF9_Msk (0x40000UL)
6663 #define ADC1_FILT_OUT9_VF9_Pos (17UL)
6664 #define ADC1_FILT_OUT9_VF9_Msk (0x20000UL)
6665 #define ADC1_FILT_OUT9_WFR9_Pos (16UL)
6666 #define ADC1_FILT_OUT9_WFR9_Msk (0x10000UL)
6667 #define ADC1_FILT_OUT9_FILT_OUT_CH9_Pos (0UL)
6668 #define ADC1_FILT_OUT9_FILT_OUT_CH9_Msk (0xfffUL)
6670 #define ADC1_FILT_OUTEIM_OF_EIM_Pos (18UL)
6671 #define ADC1_FILT_OUTEIM_OF_EIM_Msk (0x40000UL)
6672 #define ADC1_FILT_OUTEIM_VF_EIM_Pos (17UL)
6673 #define ADC1_FILT_OUTEIM_VF_EIM_Msk (0x20000UL)
6674 #define ADC1_FILT_OUTEIM_WFR_EIM_Pos (16UL)
6675 #define ADC1_FILT_OUTEIM_WFR_EIM_Msk (0x10000UL)
6676 #define ADC1_FILT_OUTEIM_FILT_OUT_EIM_Pos (0UL)
6677 #define ADC1_FILT_OUTEIM_FILT_OUT_EIM_Msk (0xfffUL)
6679 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH7_EN_Pos (7UL)
6680 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH7_EN_Msk (0x80UL)
6681 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH6_EN_Pos (6UL)
6682 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH6_EN_Msk (0x40UL)
6683 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH5_EN_Pos (5UL)
6684 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH5_EN_Msk (0x20UL)
6685 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH4_EN_Pos (4UL)
6686 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH4_EN_Msk (0x10UL)
6687 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH3_EN_Pos (3UL)
6688 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH3_EN_Msk (0x8UL)
6689 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH2_EN_Pos (2UL)
6690 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH2_EN_Msk (0x4UL)
6691 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH1_EN_Pos (1UL)
6692 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH1_EN_Msk (0x2UL)
6693 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH0_EN_Pos (0UL)
6694 #define ADC1_FILT_UPLO_CTRL_FUL_PP_CH0_EN_Msk (0x1UL)
6696 #define ADC1_FILTCOEFF0_13_CH13_Pos (26UL)
6697 #define ADC1_FILTCOEFF0_13_CH13_Msk (0xc000000UL)
6698 #define ADC1_FILTCOEFF0_13_CH12_Pos (24UL)
6699 #define ADC1_FILTCOEFF0_13_CH12_Msk (0x3000000UL)
6700 #define ADC1_FILTCOEFF0_13_CH11_Pos (22UL)
6701 #define ADC1_FILTCOEFF0_13_CH11_Msk (0xc00000UL)
6702 #define ADC1_FILTCOEFF0_13_CH10_Pos (20UL)
6703 #define ADC1_FILTCOEFF0_13_CH10_Msk (0x300000UL)
6704 #define ADC1_FILTCOEFF0_13_CH9_Pos (18UL)
6705 #define ADC1_FILTCOEFF0_13_CH9_Msk (0xc0000UL)
6706 #define ADC1_FILTCOEFF0_13_CH8_Pos (16UL)
6707 #define ADC1_FILTCOEFF0_13_CH8_Msk (0x30000UL)
6708 #define ADC1_FILTCOEFF0_13_CH7_Pos (14UL)
6709 #define ADC1_FILTCOEFF0_13_CH7_Msk (0xc000UL)
6710 #define ADC1_FILTCOEFF0_13_CH6_Pos (12UL)
6711 #define ADC1_FILTCOEFF0_13_CH6_Msk (0x3000UL)
6712 #define ADC1_FILTCOEFF0_13_CH5_Pos (10UL)
6713 #define ADC1_FILTCOEFF0_13_CH5_Msk (0xc00UL)
6714 #define ADC1_FILTCOEFF0_13_CH4_Pos (8UL)
6715 #define ADC1_FILTCOEFF0_13_CH4_Msk (0x300UL)
6716 #define ADC1_FILTCOEFF0_13_CH3_Pos (6UL)
6717 #define ADC1_FILTCOEFF0_13_CH3_Msk (0xc0UL)
6718 #define ADC1_FILTCOEFF0_13_CH2_Pos (4UL)
6719 #define ADC1_FILTCOEFF0_13_CH2_Msk (0x30UL)
6720 #define ADC1_FILTCOEFF0_13_CH1_Pos (2UL)
6721 #define ADC1_FILTCOEFF0_13_CH1_Msk (0xcUL)
6722 #define ADC1_FILTCOEFF0_13_CH0_Pos (0UL)
6723 #define ADC1_FILTCOEFF0_13_CH0_Msk (0x3UL)
6725 #define ADC1_IRQCLR_1_DU1UP_ISC_Pos (25UL)
6726 #define ADC1_IRQCLR_1_DU1UP_ISC_Msk (0x2000000UL)
6727 #define ADC1_IRQCLR_1_DU1LO_ISC_Pos (24UL)
6728 #define ADC1_IRQCLR_1_DU1LO_ISC_Msk (0x1000000UL)
6729 #define ADC1_IRQCLR_1_ESM_ISC_Pos (17UL)
6730 #define ADC1_IRQCLR_1_ESM_ISC_Msk (0x20000UL)
6731 #define ADC1_IRQCLR_1_EIM_ISC_Pos (16UL)
6732 #define ADC1_IRQCLR_1_EIM_ISC_Msk (0x10000UL)
6733 #define ADC1_IRQCLR_1_IIR_CH13_ISC_Pos (13UL)
6734 #define ADC1_IRQCLR_1_IIR_CH13_ISC_Msk (0x2000UL)
6735 #define ADC1_IRQCLR_1_IIR_CH12_ISC_Pos (12UL)
6736 #define ADC1_IRQCLR_1_IIR_CH12_ISC_Msk (0x1000UL)
6737 #define ADC1_IRQCLR_1_IIR_CH11_ISC_Pos (11UL)
6738 #define ADC1_IRQCLR_1_IIR_CH11_ISC_Msk (0x800UL)
6739 #define ADC1_IRQCLR_1_IIR_CH10_ISC_Pos (10UL)
6740 #define ADC1_IRQCLR_1_IIR_CH10_ISC_Msk (0x400UL)
6741 #define ADC1_IRQCLR_1_IIR_CH9_ISC_Pos (9UL)
6742 #define ADC1_IRQCLR_1_IIR_CH9_ISC_Msk (0x200UL)
6743 #define ADC1_IRQCLR_1_IIR_CH8_ISC_Pos (8UL)
6744 #define ADC1_IRQCLR_1_IIR_CH8_ISC_Msk (0x100UL)
6745 #define ADC1_IRQCLR_1_IIR_CH7_ISC_Pos (7UL)
6746 #define ADC1_IRQCLR_1_IIR_CH7_ISC_Msk (0x80UL)
6747 #define ADC1_IRQCLR_1_IIR_CH6_ISC_Pos (6UL)
6748 #define ADC1_IRQCLR_1_IIR_CH6_ISC_Msk (0x40UL)
6749 #define ADC1_IRQCLR_1_IIR_CH5_ISC_Pos (5UL)
6750 #define ADC1_IRQCLR_1_IIR_CH5_ISC_Msk (0x20UL)
6751 #define ADC1_IRQCLR_1_IIR_CH4_ISC_Pos (4UL)
6752 #define ADC1_IRQCLR_1_IIR_CH4_ISC_Msk (0x10UL)
6753 #define ADC1_IRQCLR_1_IIR_CH3_ISC_Pos (3UL)
6754 #define ADC1_IRQCLR_1_IIR_CH3_ISC_Msk (0x8UL)
6755 #define ADC1_IRQCLR_1_IIR_CH2_ISC_Pos (2UL)
6756 #define ADC1_IRQCLR_1_IIR_CH2_ISC_Msk (0x4UL)
6757 #define ADC1_IRQCLR_1_VS_ISC_Pos (1UL)
6758 #define ADC1_IRQCLR_1_VS_ISC_Msk (0x2UL)
6759 #define ADC1_IRQCLR_1_IIR_CH0_ISC_Pos (0UL)
6760 #define ADC1_IRQCLR_1_IIR_CH0_ISC_Msk (0x1UL)
6762 #define ADC1_IRQCLR_2_PP_CH7_UP_ISC_Pos (23UL)
6763 #define ADC1_IRQCLR_2_PP_CH7_UP_ISC_Msk (0x800000UL)
6764 #define ADC1_IRQCLR_2_PP_CH6_UP_ISC_Pos (22UL)
6765 #define ADC1_IRQCLR_2_PP_CH6_UP_ISC_Msk (0x400000UL)
6766 #define ADC1_IRQCLR_2_PP_CH5_UP_ISC_Pos (21UL)
6767 #define ADC1_IRQCLR_2_PP_CH5_UP_ISC_Msk (0x200000UL)
6768 #define ADC1_IRQCLR_2_PP_CH4_UP_ISC_Pos (20UL)
6769 #define ADC1_IRQCLR_2_PP_CH4_UP_ISC_Msk (0x100000UL)
6770 #define ADC1_IRQCLR_2_PP_CH3_UP_ISC_Pos (19UL)
6771 #define ADC1_IRQCLR_2_PP_CH3_UP_ISC_Msk (0x80000UL)
6772 #define ADC1_IRQCLR_2_PP_CH2_UP_ISC_Pos (18UL)
6773 #define ADC1_IRQCLR_2_PP_CH2_UP_ISC_Msk (0x40000UL)
6774 #define ADC1_IRQCLR_2_VS_UP_ISC_Pos (17UL)
6775 #define ADC1_IRQCLR_2_VS_UP_ISC_Msk (0x20000UL)
6776 #define ADC1_IRQCLR_2_PP_CH0_UP_ISC_Pos (16UL)
6777 #define ADC1_IRQCLR_2_PP_CH0_UP_ISC_Msk (0x10000UL)
6778 #define ADC1_IRQCLR_2_PP_CH7_LO_ISC_Pos (7UL)
6779 #define ADC1_IRQCLR_2_PP_CH7_LO_ISC_Msk (0x80UL)
6780 #define ADC1_IRQCLR_2_PP_CH6_LO_ISC_Pos (6UL)
6781 #define ADC1_IRQCLR_2_PP_CH6_LO_ISC_Msk (0x40UL)
6782 #define ADC1_IRQCLR_2_PP_CH5_LO_ISC_Pos (5UL)
6783 #define ADC1_IRQCLR_2_PP_CH5_LO_ISC_Msk (0x20UL)
6784 #define ADC1_IRQCLR_2_PP_CH4_LO_ISC_Pos (4UL)
6785 #define ADC1_IRQCLR_2_PP_CH4_LO_ISC_Msk (0x10UL)
6786 #define ADC1_IRQCLR_2_PP_CH3_LO_ISC_Pos (3UL)
6787 #define ADC1_IRQCLR_2_PP_CH3_LO_ISC_Msk (0x8UL)
6788 #define ADC1_IRQCLR_2_PP_CH2_LO_ISC_Pos (2UL)
6789 #define ADC1_IRQCLR_2_PP_CH2_LO_ISC_Msk (0x4UL)
6790 #define ADC1_IRQCLR_2_VS_LO_ISC_Pos (1UL)
6791 #define ADC1_IRQCLR_2_VS_LO_ISC_Msk (0x2UL)
6792 #define ADC1_IRQCLR_2_PP_CH0_LO_ISC_Pos (0UL)
6793 #define ADC1_IRQCLR_2_PP_CH0_LO_ISC_Msk (0x1UL)
6795 #define ADC1_IRQEN_1_DU1UP_IEN_Pos (25UL)
6796 #define ADC1_IRQEN_1_DU1UP_IEN_Msk (0x2000000UL)
6797 #define ADC1_IRQEN_1_DU1LO_IEN_Pos (24UL)
6798 #define ADC1_IRQEN_1_DU1LO_IEN_Msk (0x1000000UL)
6799 #define ADC1_IRQEN_1_ESM_IEN_Pos (17UL)
6800 #define ADC1_IRQEN_1_ESM_IEN_Msk (0x20000UL)
6801 #define ADC1_IRQEN_1_EIM_IEN_Pos (16UL)
6802 #define ADC1_IRQEN_1_EIM_IEN_Msk (0x10000UL)
6803 #define ADC1_IRQEN_1_IIR_CH13_IEN_Pos (13UL)
6804 #define ADC1_IRQEN_1_IIR_CH13_IEN_Msk (0x2000UL)
6805 #define ADC1_IRQEN_1_IIR_CH12_IEN_Pos (12UL)
6806 #define ADC1_IRQEN_1_IIR_CH12_IEN_Msk (0x1000UL)
6807 #define ADC1_IRQEN_1_IIR_CH11_IEN_Pos (11UL)
6808 #define ADC1_IRQEN_1_IIR_CH11_IEN_Msk (0x800UL)
6809 #define ADC1_IRQEN_1_IIR_CH10_IEN_Pos (10UL)
6810 #define ADC1_IRQEN_1_IIR_CH10_IEN_Msk (0x400UL)
6811 #define ADC1_IRQEN_1_IIR_CH9_IEN_Pos (9UL)
6812 #define ADC1_IRQEN_1_IIR_CH9_IEN_Msk (0x200UL)
6813 #define ADC1_IRQEN_1_IIR_CH8_IEN_Pos (8UL)
6814 #define ADC1_IRQEN_1_IIR_CH8_IEN_Msk (0x100UL)
6815 #define ADC1_IRQEN_1_IIR_CH7_IEN_Pos (7UL)
6816 #define ADC1_IRQEN_1_IIR_CH7_IEN_Msk (0x80UL)
6817 #define ADC1_IRQEN_1_IIR_CH6_IEN_Pos (6UL)
6818 #define ADC1_IRQEN_1_IIR_CH6_IEN_Msk (0x40UL)
6819 #define ADC1_IRQEN_1_IIR_CH5_IEN_Pos (5UL)
6820 #define ADC1_IRQEN_1_IIR_CH5_IEN_Msk (0x20UL)
6821 #define ADC1_IRQEN_1_IIR_CH4_IEN_Pos (4UL)
6822 #define ADC1_IRQEN_1_IIR_CH4_IEN_Msk (0x10UL)
6823 #define ADC1_IRQEN_1_IIR_CH3_IEN_Pos (3UL)
6824 #define ADC1_IRQEN_1_IIR_CH3_IEN_Msk (0x8UL)
6825 #define ADC1_IRQEN_1_IIR_CH2_IEN_Pos (2UL)
6826 #define ADC1_IRQEN_1_IIR_CH2_IEN_Msk (0x4UL)
6827 #define ADC1_IRQEN_1_VS_IEN_Pos (1UL)
6828 #define ADC1_IRQEN_1_VS_IEN_Msk (0x2UL)
6829 #define ADC1_IRQEN_1_IIR_CH0_IEN_Pos (0UL)
6830 #define ADC1_IRQEN_1_IIR_CH0_IEN_Msk (0x1UL)
6832 #define ADC1_IRQEN_2_PP_CH7_UP_IEN_Pos (23UL)
6833 #define ADC1_IRQEN_2_PP_CH7_UP_IEN_Msk (0x800000UL)
6834 #define ADC1_IRQEN_2_PP_CH6_UP_IEN_Pos (22UL)
6835 #define ADC1_IRQEN_2_PP_CH6_UP_IEN_Msk (0x400000UL)
6836 #define ADC1_IRQEN_2_PP_CH5_UP_IEN_Pos (21UL)
6837 #define ADC1_IRQEN_2_PP_CH5_UP_IEN_Msk (0x200000UL)
6838 #define ADC1_IRQEN_2_PP_CH4_UP_IEN_Pos (20UL)
6839 #define ADC1_IRQEN_2_PP_CH4_UP_IEN_Msk (0x100000UL)
6840 #define ADC1_IRQEN_2_PP_CH3_UP_IEN_Pos (19UL)
6841 #define ADC1_IRQEN_2_PP_CH3_UP_IEN_Msk (0x80000UL)
6842 #define ADC1_IRQEN_2_PP_CH2_UP_IEN_Pos (18UL)
6843 #define ADC1_IRQEN_2_PP_CH2_UP_IEN_Msk (0x40000UL)
6844 #define ADC1_IRQEN_2_VS_UP_IEN_Pos (17UL)
6845 #define ADC1_IRQEN_2_VS_UP_IEN_Msk (0x20000UL)
6846 #define ADC1_IRQEN_2_PP_CH0_UP_IEN_Pos (16UL)
6847 #define ADC1_IRQEN_2_PP_CH0_UP_IEN_Msk (0x10000UL)
6848 #define ADC1_IRQEN_2_PP_CH7_LO_IEN_Pos (7UL)
6849 #define ADC1_IRQEN_2_PP_CH7_LO_IEN_Msk (0x80UL)
6850 #define ADC1_IRQEN_2_PP_CH6_LO_IEN_Pos (6UL)
6851 #define ADC1_IRQEN_2_PP_CH6_LO_IEN_Msk (0x40UL)
6852 #define ADC1_IRQEN_2_PP_CH5_LO_IEN_Pos (5UL)
6853 #define ADC1_IRQEN_2_PP_CH5_LO_IEN_Msk (0x20UL)
6854 #define ADC1_IRQEN_2_PP_CH4_LO_IEN_Pos (4UL)
6855 #define ADC1_IRQEN_2_PP_CH4_LO_IEN_Msk (0x10UL)
6856 #define ADC1_IRQEN_2_PP_CH3_LO_IEN_Pos (3UL)
6857 #define ADC1_IRQEN_2_PP_CH3_LO_IEN_Msk (0x8UL)
6858 #define ADC1_IRQEN_2_PP_CH2_LO_IEN_Pos (2UL)
6859 #define ADC1_IRQEN_2_PP_CH2_LO_IEN_Msk (0x4UL)
6860 #define ADC1_IRQEN_2_VS_LO_IEN_Pos (1UL)
6861 #define ADC1_IRQEN_2_VS_LO_IEN_Msk (0x2UL)
6862 #define ADC1_IRQEN_2_PP_CH0_LO_IEN_Pos (0UL)
6863 #define ADC1_IRQEN_2_PP_CH0_LO_IEN_Msk (0x1UL)
6865 #define ADC1_IRQS_1_DU1UP_IS_Pos (25UL)
6866 #define ADC1_IRQS_1_DU1UP_IS_Msk (0x2000000UL)
6867 #define ADC1_IRQS_1_DU1LO_IS_Pos (24UL)
6868 #define ADC1_IRQS_1_DU1LO_IS_Msk (0x1000000UL)
6869 #define ADC1_IRQS_1_ESM_IS_Pos (17UL)
6870 #define ADC1_IRQS_1_ESM_IS_Msk (0x20000UL)
6871 #define ADC1_IRQS_1_EIM_IS_Pos (16UL)
6872 #define ADC1_IRQS_1_EIM_IS_Msk (0x10000UL)
6873 #define ADC1_IRQS_1_IIR_CH13_IS_Pos (13UL)
6874 #define ADC1_IRQS_1_IIR_CH13_IS_Msk (0x2000UL)
6875 #define ADC1_IRQS_1_IIR_CH12_IS_Pos (12UL)
6876 #define ADC1_IRQS_1_IIR_CH12_IS_Msk (0x1000UL)
6877 #define ADC1_IRQS_1_IIR_CH11_IS_Pos (11UL)
6878 #define ADC1_IRQS_1_IIR_CH11_IS_Msk (0x800UL)
6879 #define ADC1_IRQS_1_IIR_CH10_IS_Pos (10UL)
6880 #define ADC1_IRQS_1_IIR_CH10_IS_Msk (0x400UL)
6881 #define ADC1_IRQS_1_IIR_CH9_IS_Pos (9UL)
6882 #define ADC1_IRQS_1_IIR_CH9_IS_Msk (0x200UL)
6883 #define ADC1_IRQS_1_IIR_CH8_IS_Pos (8UL)
6884 #define ADC1_IRQS_1_IIR_CH8_IS_Msk (0x100UL)
6885 #define ADC1_IRQS_1_IIR_CH7_IS_Pos (7UL)
6886 #define ADC1_IRQS_1_IIR_CH7_IS_Msk (0x80UL)
6887 #define ADC1_IRQS_1_IIR_CH6_IS_Pos (6UL)
6888 #define ADC1_IRQS_1_IIR_CH6_IS_Msk (0x40UL)
6889 #define ADC1_IRQS_1_IIR_CH5_IS_Pos (5UL)
6890 #define ADC1_IRQS_1_IIR_CH5_IS_Msk (0x20UL)
6891 #define ADC1_IRQS_1_IIR_CH4_IS_Pos (4UL)
6892 #define ADC1_IRQS_1_IIR_CH4_IS_Msk (0x10UL)
6893 #define ADC1_IRQS_1_IIR_CH3_IS_Pos (3UL)
6894 #define ADC1_IRQS_1_IIR_CH3_IS_Msk (0x8UL)
6895 #define ADC1_IRQS_1_IIR_CH2_IS_Pos (2UL)
6896 #define ADC1_IRQS_1_IIR_CH2_IS_Msk (0x4UL)
6897 #define ADC1_IRQS_1_VS_IS_Pos (1UL)
6898 #define ADC1_IRQS_1_VS_IS_Msk (0x2UL)
6899 #define ADC1_IRQS_1_IIR_CH0_IS_Pos (0UL)
6900 #define ADC1_IRQS_1_IIR_CH0_IS_Msk (0x1UL)
6902 #define ADC1_IRQS_2_PP_CH7_UP_IS_Pos (23UL)
6903 #define ADC1_IRQS_2_PP_CH7_UP_IS_Msk (0x800000UL)
6904 #define ADC1_IRQS_2_PP_CH6_UP_IS_Pos (22UL)
6905 #define ADC1_IRQS_2_PP_CH6_UP_IS_Msk (0x400000UL)
6906 #define ADC1_IRQS_2_PP_CH5_UP_IS_Pos (21UL)
6907 #define ADC1_IRQS_2_PP_CH5_UP_IS_Msk (0x200000UL)
6908 #define ADC1_IRQS_2_PP_CH4_UP_IS_Pos (20UL)
6909 #define ADC1_IRQS_2_PP_CH4_UP_IS_Msk (0x100000UL)
6910 #define ADC1_IRQS_2_PP_CH3_UP_IS_Pos (19UL)
6911 #define ADC1_IRQS_2_PP_CH3_UP_IS_Msk (0x80000UL)
6912 #define ADC1_IRQS_2_PP_CH2_UP_IS_Pos (18UL)
6913 #define ADC1_IRQS_2_PP_CH2_UP_IS_Msk (0x40000UL)
6914 #define ADC1_IRQS_2_VS_UP_IS_Pos (17UL)
6915 #define ADC1_IRQS_2_VS_UP_IS_Msk (0x20000UL)
6916 #define ADC1_IRQS_2_PP_CH0_UP_IS_Pos (16UL)
6917 #define ADC1_IRQS_2_PP_CH0_UP_IS_Msk (0x10000UL)
6918 #define ADC1_IRQS_2_PP_CH7_LO_IS_Pos (7UL)
6919 #define ADC1_IRQS_2_PP_CH7_LO_IS_Msk (0x80UL)
6920 #define ADC1_IRQS_2_PP_CH6_LO_IS_Pos (6UL)
6921 #define ADC1_IRQS_2_PP_CH6_LO_IS_Msk (0x40UL)
6922 #define ADC1_IRQS_2_PP_CH5_LO_IS_Pos (5UL)
6923 #define ADC1_IRQS_2_PP_CH5_LO_IS_Msk (0x20UL)
6924 #define ADC1_IRQS_2_PP_CH4_LO_IS_Pos (4UL)
6925 #define ADC1_IRQS_2_PP_CH4_LO_IS_Msk (0x10UL)
6926 #define ADC1_IRQS_2_PP_CH3_LO_IS_Pos (3UL)
6927 #define ADC1_IRQS_2_PP_CH3_LO_IS_Msk (0x8UL)
6928 #define ADC1_IRQS_2_PP_CH2_LO_IS_Pos (2UL)
6929 #define ADC1_IRQS_2_PP_CH2_LO_IS_Msk (0x4UL)
6930 #define ADC1_IRQS_2_VS_LO_IS_Pos (1UL)
6931 #define ADC1_IRQS_2_VS_LO_IS_Msk (0x2UL)
6932 #define ADC1_IRQS_2_PP_CH0_LO_IS_Pos (0UL)
6933 #define ADC1_IRQS_2_PP_CH0_LO_IS_Msk (0x1UL)
6935 #define ADC1_MAX_TIME_MAX_TIME_Pos (0UL)
6936 #define ADC1_MAX_TIME_MAX_TIME_Msk (0xffUL)
6938 #define ADC1_MMODE0_7_MMODE_D1_Pos (24UL)
6939 #define ADC1_MMODE0_7_MMODE_D1_Msk (0x3000000UL)
6940 #define ADC1_MMODE0_7_MMODE_7_Pos (14UL)
6941 #define ADC1_MMODE0_7_MMODE_7_Msk (0xc000UL)
6942 #define ADC1_MMODE0_7_MMODE_6_Pos (12UL)
6943 #define ADC1_MMODE0_7_MMODE_6_Msk (0x3000UL)
6944 #define ADC1_MMODE0_7_MMODE_5_Pos (10UL)
6945 #define ADC1_MMODE0_7_MMODE_5_Msk (0xc00UL)
6946 #define ADC1_MMODE0_7_MMODE_4_Pos (8UL)
6947 #define ADC1_MMODE0_7_MMODE_4_Msk (0x300UL)
6948 #define ADC1_MMODE0_7_MMODE_3_Pos (6UL)
6949 #define ADC1_MMODE0_7_MMODE_3_Msk (0xc0UL)
6950 #define ADC1_MMODE0_7_MMODE_2_Pos (4UL)
6951 #define ADC1_MMODE0_7_MMODE_2_Msk (0x30UL)
6952 #define ADC1_MMODE0_7_MMODE_1_Pos (2UL)
6953 #define ADC1_MMODE0_7_MMODE_1_Msk (0xcUL)
6954 #define ADC1_MMODE0_7_MMODE_0_Pos (0UL)
6955 #define ADC1_MMODE0_7_MMODE_0_Msk (0x3UL)
6957 #define ADC1_OFFSETCALIB_OFFSET_DAC_Pos (8UL)
6958 #define ADC1_OFFSETCALIB_OFFSET_DAC_Msk (0x1f00UL)
6959 #define ADC1_OFFSETCALIB_OFFSET_SHIFT_Pos (0UL)
6960 #define ADC1_OFFSETCALIB_OFFSET_SHIFT_Msk (0x7UL)
6962 #define ADC1_PP_MAP0_3_EN_PP_MAP3_Pos (31UL)
6963 #define ADC1_PP_MAP0_3_EN_PP_MAP3_Msk (0x80000000UL)
6964 #define ADC1_PP_MAP0_3_RESET_PP_MAP3_Pos (30UL)
6965 #define ADC1_PP_MAP0_3_RESET_PP_MAP3_Msk (0x40000000UL)
6966 #define ADC1_PP_MAP0_3_PP_MAP3_Pos (24UL)
6967 #define ADC1_PP_MAP0_3_PP_MAP3_Msk (0xf000000UL)
6968 #define ADC1_PP_MAP0_3_EN_PP_MAP2_Pos (23UL)
6969 #define ADC1_PP_MAP0_3_EN_PP_MAP2_Msk (0x800000UL)
6970 #define ADC1_PP_MAP0_3_RESET_PP_MAP2_Pos (22UL)
6971 #define ADC1_PP_MAP0_3_RESET_PP_MAP2_Msk (0x400000UL)
6972 #define ADC1_PP_MAP0_3_PP_MAP2_Pos (16UL)
6973 #define ADC1_PP_MAP0_3_PP_MAP2_Msk (0xf0000UL)
6974 #define ADC1_PP_MAP0_3_EN_PP_MAP1_Pos (15UL)
6975 #define ADC1_PP_MAP0_3_EN_PP_MAP1_Msk (0x8000UL)
6976 #define ADC1_PP_MAP0_3_RESET_PP_MAP1_Pos (14UL)
6977 #define ADC1_PP_MAP0_3_RESET_PP_MAP1_Msk (0x4000UL)
6978 #define ADC1_PP_MAP0_3_EN_PP_MAP0_Pos (7UL)
6979 #define ADC1_PP_MAP0_3_EN_PP_MAP0_Msk (0x80UL)
6980 #define ADC1_PP_MAP0_3_RESET_PP_MAP0_Pos (6UL)
6981 #define ADC1_PP_MAP0_3_RESET_PP_MAP0_Msk (0x40UL)
6983 #define ADC1_PP_MAP4_7_EN_PP_MAP7_Pos (31UL)
6984 #define ADC1_PP_MAP4_7_EN_PP_MAP7_Msk (0x80000000UL)
6985 #define ADC1_PP_MAP4_7_RESET_PP_MAP7_Pos (30UL)
6986 #define ADC1_PP_MAP4_7_RESET_PP_MAP7_Msk (0x40000000UL)
6987 #define ADC1_PP_MAP4_7_PP_MAP7_Pos (24UL)
6988 #define ADC1_PP_MAP4_7_PP_MAP7_Msk (0xf000000UL)
6989 #define ADC1_PP_MAP4_7_EN_PP_MAP6_Pos (23UL)
6990 #define ADC1_PP_MAP4_7_EN_PP_MAP6_Msk (0x800000UL)
6991 #define ADC1_PP_MAP4_7_RESET_PP_MAP6_Pos (22UL)
6992 #define ADC1_PP_MAP4_7_RESET_PP_MAP6_Msk (0x400000UL)
6993 #define ADC1_PP_MAP4_7_PP_MAP6_Pos (16UL)
6994 #define ADC1_PP_MAP4_7_PP_MAP6_Msk (0xf0000UL)
6995 #define ADC1_PP_MAP4_7_EN_PP_MAP5_Pos (15UL)
6996 #define ADC1_PP_MAP4_7_EN_PP_MAP5_Msk (0x8000UL)
6997 #define ADC1_PP_MAP4_7_RESET_PP_MAP5_Pos (14UL)
6998 #define ADC1_PP_MAP4_7_RESET_PP_MAP5_Msk (0x4000UL)
6999 #define ADC1_PP_MAP4_7_PP_MAP5_Pos (8UL)
7000 #define ADC1_PP_MAP4_7_PP_MAP5_Msk (0xf00UL)
7001 #define ADC1_PP_MAP4_7_EN_PP_MAP4_Pos (7UL)
7002 #define ADC1_PP_MAP4_7_EN_PP_MAP4_Msk (0x80UL)
7003 #define ADC1_PP_MAP4_7_RESET_PP_MAP4_Pos (6UL)
7004 #define ADC1_PP_MAP4_7_RESET_PP_MAP4_Msk (0x40UL)
7005 #define ADC1_PP_MAP4_7_PP_MAP4_Pos (0UL)
7006 #define ADC1_PP_MAP4_7_PP_MAP4_Msk (0xfUL)
7008 #define ADC1_SQ0_1_SQ1_Pos (16UL)
7009 #define ADC1_SQ0_1_SQ1_Msk (0x3fff0000UL)
7010 #define ADC1_SQ0_1_SQ0_Pos (0UL)
7011 #define ADC1_SQ0_1_SQ0_Msk (0x3fffUL)
7013 #define ADC1_SQ10_11_SQ11_Pos (16UL)
7014 #define ADC1_SQ10_11_SQ11_Msk (0x3fff0000UL)
7015 #define ADC1_SQ10_11_SQ10_Pos (0UL)
7016 #define ADC1_SQ10_11_SQ10_Msk (0x3fffUL)
7018 #define ADC1_SQ12_13_SQ13_Pos (16UL)
7019 #define ADC1_SQ12_13_SQ13_Msk (0x3fff0000UL)
7020 #define ADC1_SQ12_13_SQ12_Pos (0UL)
7021 #define ADC1_SQ12_13_SQ12_Msk (0x3fffUL)
7023 #define ADC1_SQ2_3_SQ3_Pos (16UL)
7024 #define ADC1_SQ2_3_SQ3_Msk (0x3fff0000UL)
7025 #define ADC1_SQ2_3_SQ2_Pos (0UL)
7026 #define ADC1_SQ2_3_SQ2_Msk (0x3fffUL)
7028 #define ADC1_SQ4_5_SQ5_Pos (16UL)
7029 #define ADC1_SQ4_5_SQ5_Msk (0x3fff0000UL)
7030 #define ADC1_SQ4_5_SQ4_Pos (0UL)
7031 #define ADC1_SQ4_5_SQ4_Msk (0x3fffUL)
7033 #define ADC1_SQ6_7_SQ7_Pos (16UL)
7034 #define ADC1_SQ6_7_SQ7_Msk (0x3fff0000UL)
7035 #define ADC1_SQ6_7_SQ6_Pos (0UL)
7036 #define ADC1_SQ6_7_SQ6_Msk (0x3fffUL)
7038 #define ADC1_SQ8_9_SQ9_Pos (16UL)
7039 #define ADC1_SQ8_9_SQ9_Msk (0x3fff0000UL)
7040 #define ADC1_SQ8_9_SQ8_Pos (0UL)
7041 #define ADC1_SQ8_9_SQ8_Msk (0x3fffUL)
7043 #define ADC1_SQ_CH_MAP_SQ_CH12_MAP_Pos (12UL)
7044 #define ADC1_SQ_CH_MAP_SQ_CH12_MAP_Msk (0x1000UL)
7045 #define ADC1_SQ_CH_MAP_SQ_CH6_MAP_Pos (6UL)
7046 #define ADC1_SQ_CH_MAP_SQ_CH6_MAP_Msk (0x40UL)
7047 #define ADC1_SQ_CH_MAP_SQ_CH5_MAP_Pos (5UL)
7048 #define ADC1_SQ_CH_MAP_SQ_CH5_MAP_Msk (0x20UL)
7050 #define ADC1_SQ_FB_CHx_Pos (16UL)
7051 #define ADC1_SQ_FB_CHx_Msk (0xf0000UL)
7052 #define ADC1_SQ_FB_SQx_Pos (11UL)
7053 #define ADC1_SQ_FB_SQx_Msk (0x7800UL)
7054 #define ADC1_SQ_FB_ESM_ACTIVE_Pos (10UL)
7055 #define ADC1_SQ_FB_ESM_ACTIVE_Msk (0x400UL)
7056 #define ADC1_SQ_FB_EIM_ACTIVE_Pos (9UL)
7057 #define ADC1_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
7058 #define ADC1_SQ_FB_SQ_STOP_Pos (8UL)
7059 #define ADC1_SQ_FB_SQ_STOP_Msk (0x100UL)
7060 #define ADC1_SQ_FB_SQ_FB_Pos (0UL)
7061 #define ADC1_SQ_FB_SQ_FB_Msk (0x1fUL)
7063 #define ADC1_STATUS_SD_FEEDB_ON_Pos (31UL)
7064 #define ADC1_STATUS_SD_FEEDB_ON_Msk (0x80000000UL)
7065 #define ADC1_STATUS_SOC_JITTER_Pos (16UL)
7066 #define ADC1_STATUS_SOC_JITTER_Msk (0x30000UL)
7067 #define ADC1_STATUS_DAC_IN_Pos (0UL)
7068 #define ADC1_STATUS_DAC_IN_Msk (0x7UL)
7070 #define ADC1_STS_1_DU1UP_STS_Pos (25UL)
7071 #define ADC1_STS_1_DU1UP_STS_Msk (0x2000000UL)
7072 #define ADC1_STS_1_DU1LO_STS_Pos (24UL)
7073 #define ADC1_STS_1_DU1LO_STS_Msk (0x1000000UL)
7075 #define ADC1_STS_2_PP_CH7_UP_STS_Pos (23UL)
7076 #define ADC1_STS_2_PP_CH7_UP_STS_Msk (0x800000UL)
7077 #define ADC1_STS_2_PP_CH6_UP_STS_Pos (22UL)
7078 #define ADC1_STS_2_PP_CH6_UP_STS_Msk (0x400000UL)
7079 #define ADC1_STS_2_PP_CH5_UP_STS_Pos (21UL)
7080 #define ADC1_STS_2_PP_CH5_UP_STS_Msk (0x200000UL)
7081 #define ADC1_STS_2_PP_CH4_UP_STS_Pos (20UL)
7082 #define ADC1_STS_2_PP_CH4_UP_STS_Msk (0x100000UL)
7083 #define ADC1_STS_2_PP_CH3_UP_STS_Pos (19UL)
7084 #define ADC1_STS_2_PP_CH3_UP_STS_Msk (0x80000UL)
7085 #define ADC1_STS_2_PP_CH2_UP_STS_Pos (18UL)
7086 #define ADC1_STS_2_PP_CH2_UP_STS_Msk (0x40000UL)
7087 #define ADC1_STS_2_VS_UP_STS_Pos (17UL)
7088 #define ADC1_STS_2_VS_UP_STS_Msk (0x20000UL)
7089 #define ADC1_STS_2_PP_CH0_UP_STS_Pos (16UL)
7090 #define ADC1_STS_2_PP_CH0_UP_STS_Msk (0x10000UL)
7091 #define ADC1_STS_2_PP_CH7_LO_STS_Pos (7UL)
7092 #define ADC1_STS_2_PP_CH7_LO_STS_Msk (0x80UL)
7093 #define ADC1_STS_2_PP_CH6_LO_STS_Pos (6UL)
7094 #define ADC1_STS_2_PP_CH6_LO_STS_Msk (0x40UL)
7095 #define ADC1_STS_2_PP_CH5_LO_STS_Pos (5UL)
7096 #define ADC1_STS_2_PP_CH5_LO_STS_Msk (0x20UL)
7097 #define ADC1_STS_2_PP_CH4_LO_STS_Pos (4UL)
7098 #define ADC1_STS_2_PP_CH4_LO_STS_Msk (0x10UL)
7099 #define ADC1_STS_2_PP_CH3_LO_STS_Pos (3UL)
7100 #define ADC1_STS_2_PP_CH3_LO_STS_Msk (0x8UL)
7101 #define ADC1_STS_2_PP_CH2_LO_STS_Pos (2UL)
7102 #define ADC1_STS_2_PP_CH2_LO_STS_Msk (0x4UL)
7103 #define ADC1_STS_2_VS_LO_STS_Pos (1UL)
7104 #define ADC1_STS_2_VS_LO_STS_Msk (0x2UL)
7105 #define ADC1_STS_2_PP_CH0_LO_STS_Pos (0UL)
7106 #define ADC1_STS_2_PP_CH0_LO_STS_Msk (0x1UL)
7108 #define ADC1_STSCLR_1_DU1UP_SC_Pos (25UL)
7109 #define ADC1_STSCLR_1_DU1UP_SC_Msk (0x2000000UL)
7110 #define ADC1_STSCLR_1_DU1LO_SC_Pos (24UL)
7111 #define ADC1_STSCLR_1_DU1LO_SC_Msk (0x1000000UL)
7113 #define ADC1_TH0_3_LOWER_PP_CH3_LOW_Pos (24UL)
7114 #define ADC1_TH0_3_LOWER_PP_CH3_LOW_Msk (0xff000000UL)
7115 #define ADC1_TH0_3_LOWER_PP_CH2_LOW_Pos (16UL)
7116 #define ADC1_TH0_3_LOWER_PP_CH2_LOW_Msk (0xff0000UL)
7117 #define ADC1_TH0_3_LOWER_PP_CH1_LOW_Pos (8UL)
7118 #define ADC1_TH0_3_LOWER_PP_CH1_LOW_Msk (0xff00UL)
7119 #define ADC1_TH0_3_LOWER_PP_CH0_LOW_Pos (0UL)
7120 #define ADC1_TH0_3_LOWER_PP_CH0_LOW_Msk (0xffUL)
7122 #define ADC1_TH0_3_UPPER_PP_CH3_UP_Pos (24UL)
7123 #define ADC1_TH0_3_UPPER_PP_CH3_UP_Msk (0xff000000UL)
7124 #define ADC1_TH0_3_UPPER_PP_CH2_UP_Pos (16UL)
7125 #define ADC1_TH0_3_UPPER_PP_CH2_UP_Msk (0xff0000UL)
7126 #define ADC1_TH0_3_UPPER_PP_CH1_UP_Pos (8UL)
7127 #define ADC1_TH0_3_UPPER_PP_CH1_UP_Msk (0xff00UL)
7128 #define ADC1_TH0_3_UPPER_PP_CH0_UP_Pos (0UL)
7129 #define ADC1_TH0_3_UPPER_PP_CH0_UP_Msk (0xffUL)
7131 #define ADC1_TH4_7_LOWER_PP_CH7_LOW_Pos (24UL)
7132 #define ADC1_TH4_7_LOWER_PP_CH7_LOW_Msk (0xff000000UL)
7133 #define ADC1_TH4_7_LOWER_PP_CH6_LOW_Pos (16UL)
7134 #define ADC1_TH4_7_LOWER_PP_CH6_LOW_Msk (0xff0000UL)
7135 #define ADC1_TH4_7_LOWER_PP_CH5_LOW_Pos (8UL)
7136 #define ADC1_TH4_7_LOWER_PP_CH5_LOW_Msk (0xff00UL)
7137 #define ADC1_TH4_7_LOWER_PP_CH4_LOW_Pos (0UL)
7138 #define ADC1_TH4_7_LOWER_PP_CH4_LOW_Msk (0xffUL)
7140 #define ADC1_TH4_7_UPPER_PP_CH7_UP_Pos (24UL)
7141 #define ADC1_TH4_7_UPPER_PP_CH7_UP_Msk (0xff000000UL)
7142 #define ADC1_TH4_7_UPPER_PP_CH6_UP_Pos (16UL)
7143 #define ADC1_TH4_7_UPPER_PP_CH6_UP_Msk (0xff0000UL)
7144 #define ADC1_TH4_7_UPPER_PP_CH5_UP_Pos (8UL)
7145 #define ADC1_TH4_7_UPPER_PP_CH5_UP_Msk (0xff00UL)
7146 #define ADC1_TH4_7_UPPER_PP_CH4_UP_Pos (0UL)
7147 #define ADC1_TH4_7_UPPER_PP_CH4_UP_Msk (0xffUL)
7155 #define ADC2_CAL_CH0_1_GAIN_CH1_Pos (24UL)
7156 #define ADC2_CAL_CH0_1_GAIN_CH1_Msk (0xff000000UL)
7157 #define ADC2_CAL_CH0_1_OFFS_CH1_Pos (16UL)
7158 #define ADC2_CAL_CH0_1_OFFS_CH1_Msk (0x1f0000UL)
7159 #define ADC2_CAL_CH0_1_GAIN_CH0_Pos (8UL)
7160 #define ADC2_CAL_CH0_1_GAIN_CH0_Msk (0xff00UL)
7161 #define ADC2_CAL_CH0_1_OFFS_CH0_Pos (0UL)
7162 #define ADC2_CAL_CH0_1_OFFS_CH0_Msk (0x1fUL)
7164 #define ADC2_CAL_CH2_3_GAIN_CH3_Pos (24UL)
7165 #define ADC2_CAL_CH2_3_GAIN_CH3_Msk (0xff000000UL)
7166 #define ADC2_CAL_CH2_3_OFFS_CH3_Pos (16UL)
7167 #define ADC2_CAL_CH2_3_OFFS_CH3_Msk (0x1f0000UL)
7168 #define ADC2_CAL_CH2_3_GAIN_CH2_Pos (8UL)
7169 #define ADC2_CAL_CH2_3_GAIN_CH2_Msk (0xff00UL)
7170 #define ADC2_CAL_CH2_3_OFFS_CH2_Pos (0UL)
7171 #define ADC2_CAL_CH2_3_OFFS_CH2_Msk (0x1fUL)
7173 #define ADC2_CAL_CH4_5_GAIN_CH5_Pos (24UL)
7174 #define ADC2_CAL_CH4_5_GAIN_CH5_Msk (0xff000000UL)
7175 #define ADC2_CAL_CH4_5_OFFS_CH5_Pos (16UL)
7176 #define ADC2_CAL_CH4_5_OFFS_CH5_Msk (0x1f0000UL)
7177 #define ADC2_CAL_CH4_5_GAIN_CH4_Pos (8UL)
7178 #define ADC2_CAL_CH4_5_GAIN_CH4_Msk (0xff00UL)
7179 #define ADC2_CAL_CH4_5_OFFS_CH4_Pos (0UL)
7180 #define ADC2_CAL_CH4_5_OFFS_CH4_Msk (0x1fUL)
7182 #define ADC2_CAL_CH6_7_GAIN_CH7_Pos (24UL)
7183 #define ADC2_CAL_CH6_7_GAIN_CH7_Msk (0xff000000UL)
7184 #define ADC2_CAL_CH6_7_OFFS_CH7_Pos (16UL)
7185 #define ADC2_CAL_CH6_7_OFFS_CH7_Msk (0x1f0000UL)
7186 #define ADC2_CAL_CH6_7_GAIN_CH6_Pos (8UL)
7187 #define ADC2_CAL_CH6_7_GAIN_CH6_Msk (0xff00UL)
7188 #define ADC2_CAL_CH6_7_OFFS_CH6_Pos (0UL)
7189 #define ADC2_CAL_CH6_7_OFFS_CH6_Msk (0x1fUL)
7191 #define ADC2_CAL_CH8_9_GAIN_CH8_Pos (8UL)
7192 #define ADC2_CAL_CH8_9_GAIN_CH8_Msk (0xff00UL)
7193 #define ADC2_CAL_CH8_9_OFFS_CH8_Pos (0UL)
7194 #define ADC2_CAL_CH8_9_OFFS_CH8_Msk (0x1fUL)
7196 #define ADC2_CHx_EIM_SEL_Pos (12UL)
7197 #define ADC2_CHx_EIM_SEL_Msk (0x1000UL)
7198 #define ADC2_CHx_EIM_EN_Pos (11UL)
7199 #define ADC2_CHx_EIM_EN_Msk (0x800UL)
7200 #define ADC2_CHx_EIM_REP_Pos (8UL)
7201 #define ADC2_CHx_EIM_REP_Msk (0x700UL)
7202 #define ADC2_CHx_EIM_CHx_SEL_Pos (0UL)
7203 #define ADC2_CHx_EIM_CHx_SEL_Msk (0xfUL)
7205 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Pos (27UL)
7206 #define ADC2_CNT0_3_LOWER_HYST_LO_CH3_Msk (0x18000000UL)
7207 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Pos (24UL)
7208 #define ADC2_CNT0_3_LOWER_CNT_LO_CH3_Msk (0x3000000UL)
7209 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Pos (19UL)
7210 #define ADC2_CNT0_3_LOWER_HYST_LO_CH2_Msk (0x180000UL)
7211 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Pos (16UL)
7212 #define ADC2_CNT0_3_LOWER_CNT_LO_CH2_Msk (0x30000UL)
7213 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Pos (11UL)
7214 #define ADC2_CNT0_3_LOWER_HYST_LO_CH1_Msk (0x1800UL)
7215 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Pos (8UL)
7216 #define ADC2_CNT0_3_LOWER_CNT_LO_CH1_Msk (0x300UL)
7217 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Pos (3UL)
7218 #define ADC2_CNT0_3_LOWER_HYST_LO_CH0_Msk (0x18UL)
7219 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Pos (0UL)
7220 #define ADC2_CNT0_3_LOWER_CNT_LO_CH0_Msk (0x3UL)
7222 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Pos (27UL)
7223 #define ADC2_CNT0_3_UPPER_HYST_UP_CH3_Msk (0x18000000UL)
7224 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Pos (24UL)
7225 #define ADC2_CNT0_3_UPPER_CNT_UP_CH3_Msk (0x3000000UL)
7226 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Pos (19UL)
7227 #define ADC2_CNT0_3_UPPER_HYST_UP_CH2_Msk (0x180000UL)
7228 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Pos (16UL)
7229 #define ADC2_CNT0_3_UPPER_CNT_UP_CH2_Msk (0x30000UL)
7230 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Pos (11UL)
7231 #define ADC2_CNT0_3_UPPER_HYST_UP_CH1_Msk (0x1800UL)
7232 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Pos (8UL)
7233 #define ADC2_CNT0_3_UPPER_CNT_UP_CH1_Msk (0x300UL)
7234 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Pos (3UL)
7235 #define ADC2_CNT0_3_UPPER_HYST_UP_CH0_Msk (0x18UL)
7236 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Pos (0UL)
7237 #define ADC2_CNT0_3_UPPER_CNT_UP_CH0_Msk (0x3UL)
7239 #define ADC2_CNT4_7_LOWER_HYST_LO_CH7_Pos (27UL)
7240 #define ADC2_CNT4_7_LOWER_HYST_LO_CH7_Msk (0x18000000UL)
7241 #define ADC2_CNT4_7_LOWER_CNT_LO_CH7_Pos (24UL)
7242 #define ADC2_CNT4_7_LOWER_CNT_LO_CH7_Msk (0x3000000UL)
7243 #define ADC2_CNT4_7_LOWER_HYST_LO_CH6_Pos (19UL)
7244 #define ADC2_CNT4_7_LOWER_HYST_LO_CH6_Msk (0x180000UL)
7245 #define ADC2_CNT4_7_LOWER_CNT_LO_CH6_Pos (16UL)
7246 #define ADC2_CNT4_7_LOWER_CNT_LO_CH6_Msk (0x30000UL)
7247 #define ADC2_CNT4_7_LOWER_HYST_LO_CH5_Pos (11UL)
7248 #define ADC2_CNT4_7_LOWER_HYST_LO_CH5_Msk (0x1800UL)
7249 #define ADC2_CNT4_7_LOWER_CNT_LO_CH5_Pos (8UL)
7250 #define ADC2_CNT4_7_LOWER_CNT_LO_CH5_Msk (0x300UL)
7251 #define ADC2_CNT4_7_LOWER_HYST_LO_CH4_Pos (3UL)
7252 #define ADC2_CNT4_7_LOWER_HYST_LO_CH4_Msk (0x18UL)
7253 #define ADC2_CNT4_7_LOWER_CNT_LO_CH4_Pos (0UL)
7254 #define ADC2_CNT4_7_LOWER_CNT_LO_CH4_Msk (0x3UL)
7256 #define ADC2_CNT4_7_UPPER_HYST_UP_CH7_Pos (27UL)
7257 #define ADC2_CNT4_7_UPPER_HYST_UP_CH7_Msk (0x18000000UL)
7258 #define ADC2_CNT4_7_UPPER_CNT_UP_CH7_Pos (24UL)
7259 #define ADC2_CNT4_7_UPPER_CNT_UP_CH7_Msk (0x3000000UL)
7260 #define ADC2_CNT4_7_UPPER_HYST_UP_CH6_Pos (19UL)
7261 #define ADC2_CNT4_7_UPPER_HYST_UP_CH6_Msk (0x180000UL)
7262 #define ADC2_CNT4_7_UPPER_CNT_UP_CH6_Pos (16UL)
7263 #define ADC2_CNT4_7_UPPER_CNT_UP_CH6_Msk (0x30000UL)
7264 #define ADC2_CNT4_7_UPPER_HYST_UP_CH5_Pos (11UL)
7265 #define ADC2_CNT4_7_UPPER_HYST_UP_CH5_Msk (0x1800UL)
7266 #define ADC2_CNT4_7_UPPER_CNT_UP_CH5_Pos (8UL)
7267 #define ADC2_CNT4_7_UPPER_CNT_UP_CH5_Msk (0x300UL)
7268 #define ADC2_CNT4_7_UPPER_HYST_UP_CH4_Pos (3UL)
7269 #define ADC2_CNT4_7_UPPER_HYST_UP_CH4_Msk (0x18UL)
7270 #define ADC2_CNT4_7_UPPER_CNT_UP_CH4_Pos (0UL)
7271 #define ADC2_CNT4_7_UPPER_CNT_UP_CH4_Msk (0x3UL)
7273 #define ADC2_CNT8_11_LOWER_HYST_LO_CH8_Pos (3UL)
7274 #define ADC2_CNT8_11_LOWER_HYST_LO_CH8_Msk (0x18UL)
7275 #define ADC2_CNT8_11_LOWER_CNT_LO_CH8_Pos (0UL)
7276 #define ADC2_CNT8_11_LOWER_CNT_LO_CH8_Msk (0x3UL)
7278 #define ADC2_CNT8_11_UPPER_HYST_UP_CH8_Pos (3UL)
7279 #define ADC2_CNT8_11_UPPER_HYST_UP_CH8_Msk (0x18UL)
7280 #define ADC2_CNT8_11_UPPER_CNT_UP_CH8_Pos (0UL)
7281 #define ADC2_CNT8_11_UPPER_CNT_UP_CH8_Msk (0x3UL)
7283 #define ADC2_CTRL1_CALIB_EN_8_0_Pos (0UL)
7284 #define ADC2_CTRL1_CALIB_EN_8_0_Msk (0x1ffUL)
7286 #define ADC2_CTRL2_SAMPLE_TIME_int_Pos (8UL)
7287 #define ADC2_CTRL2_SAMPLE_TIME_int_Msk (0xf00UL)
7288 #define ADC2_CTRL2_MCM_RDY_Pos (7UL)
7289 #define ADC2_CTRL2_MCM_RDY_Msk (0x80UL)
7290 #define ADC2_CTRL2_MCM_PD_N_Pos (0UL)
7291 #define ADC2_CTRL2_MCM_PD_N_Msk (0x1UL)
7293 #define ADC2_CTRL4_FILT_OUT_SEL_8_0_Pos (0UL)
7294 #define ADC2_CTRL4_FILT_OUT_SEL_8_0_Msk (0x1ffUL)
7296 #define ADC2_CTRL_STS_IN_MUX_SEL_Pos (8UL)
7297 #define ADC2_CTRL_STS_IN_MUX_SEL_Msk (0xf00UL)
7298 #define ADC2_CTRL_STS_EOC_Pos (3UL)
7299 #define ADC2_CTRL_STS_EOC_Msk (0x8UL)
7300 #define ADC2_CTRL_STS_SOS_Pos (2UL)
7301 #define ADC2_CTRL_STS_SOS_Msk (0x4UL)
7302 #define ADC2_CTRL_STS_PD_N_Pos (0UL)
7303 #define ADC2_CTRL_STS_PD_N_Msk (0x1UL)
7305 #define ADC2_FILT_OUT0_OUT_CH0_Pos (0UL)
7306 #define ADC2_FILT_OUT0_OUT_CH0_Msk (0x3ffUL)
7308 #define ADC2_FILT_OUT1_OUT_CH1_Pos (0UL)
7309 #define ADC2_FILT_OUT1_OUT_CH1_Msk (0x3ffUL)
7311 #define ADC2_FILT_OUT2_OUT_CH2_Pos (0UL)
7312 #define ADC2_FILT_OUT2_OUT_CH2_Msk (0x3ffUL)
7314 #define ADC2_FILT_OUT3_OUT_CH3_Pos (0UL)
7315 #define ADC2_FILT_OUT3_OUT_CH3_Msk (0x3ffUL)
7317 #define ADC2_FILT_OUT4_OUT_CH4_Pos (0UL)
7318 #define ADC2_FILT_OUT4_OUT_CH4_Msk (0x3ffUL)
7320 #define ADC2_FILT_OUT5_OUT_CH5_Pos (0UL)
7321 #define ADC2_FILT_OUT5_OUT_CH5_Msk (0x3ffUL)
7323 #define ADC2_FILT_OUT6_OUT_CH6_Pos (0UL)
7324 #define ADC2_FILT_OUT6_OUT_CH6_Msk (0x3ffUL)
7326 #define ADC2_FILT_OUT7_OUT_CH7_Pos (0UL)
7327 #define ADC2_FILT_OUT7_OUT_CH7_Msk (0x3ffUL)
7329 #define ADC2_FILT_OUT8_OUT_CH8_Pos (0UL)
7330 #define ADC2_FILT_OUT8_OUT_CH8_Msk (0x3ffUL)
7332 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch8_Pos (8UL)
7333 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch8_Msk (0x100UL)
7334 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch7_Pos (7UL)
7335 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch7_Msk (0x80UL)
7336 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch6_Pos (6UL)
7337 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch6_Msk (0x40UL)
7338 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch5_Pos (5UL)
7339 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch5_Msk (0x20UL)
7340 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch4_Pos (4UL)
7341 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch4_Msk (0x10UL)
7342 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch3_Pos (3UL)
7343 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch3_Msk (0x8UL)
7344 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch2_Pos (2UL)
7345 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch2_Msk (0x4UL)
7346 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch1_Pos (1UL)
7347 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch1_Msk (0x2UL)
7348 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch0_Pos (0UL)
7349 #define ADC2_FILT_UPLO_CTRL_UPLOEN_Ch0_Msk (0x1UL)
7351 #define ADC2_FILTCOEFF0_8_A_CH8_Pos (16UL)
7352 #define ADC2_FILTCOEFF0_8_A_CH8_Msk (0x30000UL)
7353 #define ADC2_FILTCOEFF0_8_A_CH7_Pos (14UL)
7354 #define ADC2_FILTCOEFF0_8_A_CH7_Msk (0xc000UL)
7355 #define ADC2_FILTCOEFF0_8_A_CH6_Pos (12UL)
7356 #define ADC2_FILTCOEFF0_8_A_CH6_Msk (0x3000UL)
7357 #define ADC2_FILTCOEFF0_8_A_CH5_Pos (10UL)
7358 #define ADC2_FILTCOEFF0_8_A_CH5_Msk (0xc00UL)
7359 #define ADC2_FILTCOEFF0_8_A_CH4_Pos (8UL)
7360 #define ADC2_FILTCOEFF0_8_A_CH4_Msk (0x300UL)
7361 #define ADC2_FILTCOEFF0_8_A_CH3_Pos (6UL)
7362 #define ADC2_FILTCOEFF0_8_A_CH3_Msk (0xc0UL)
7363 #define ADC2_FILTCOEFF0_8_A_CH2_Pos (4UL)
7364 #define ADC2_FILTCOEFF0_8_A_CH2_Msk (0x30UL)
7365 #define ADC2_FILTCOEFF0_8_A_CH1_Pos (2UL)
7366 #define ADC2_FILTCOEFF0_8_A_CH1_Msk (0xcUL)
7367 #define ADC2_FILTCOEFF0_8_A_CH0_Pos (0UL)
7368 #define ADC2_FILTCOEFF0_8_A_CH0_Msk (0x3UL)
7370 #define ADC2_MAX_TIME_MAX_TIME_Pos (0UL)
7371 #define ADC2_MAX_TIME_MAX_TIME_Msk (0xffUL)
7373 #define ADC2_MMODE0_8_MSEL_Ch8_Pos (16UL)
7374 #define ADC2_MMODE0_8_MSEL_Ch8_Msk (0x30000UL)
7375 #define ADC2_MMODE0_8_MSEL_Ch7_Pos (14UL)
7376 #define ADC2_MMODE0_8_MSEL_Ch7_Msk (0xc000UL)
7377 #define ADC2_MMODE0_8_MSEL_Ch6_Pos (12UL)
7378 #define ADC2_MMODE0_8_MSEL_Ch6_Msk (0x3000UL)
7379 #define ADC2_MMODE0_8_MSEL_Ch5_Pos (10UL)
7380 #define ADC2_MMODE0_8_MSEL_Ch5_Msk (0xc00UL)
7381 #define ADC2_MMODE0_8_MSEL_Ch4_Pos (8UL)
7382 #define ADC2_MMODE0_8_MSEL_Ch4_Msk (0x300UL)
7383 #define ADC2_MMODE0_8_MSEL_Ch3_Pos (6UL)
7384 #define ADC2_MMODE0_8_MSEL_Ch3_Msk (0xc0UL)
7385 #define ADC2_MMODE0_8_MSEL_Ch2_Pos (4UL)
7386 #define ADC2_MMODE0_8_MSEL_Ch2_Msk (0x30UL)
7387 #define ADC2_MMODE0_8_MSEL_Ch1_Pos (2UL)
7388 #define ADC2_MMODE0_8_MSEL_Ch1_Msk (0xcUL)
7389 #define ADC2_MMODE0_8_MSEL_Ch0_Pos (0UL)
7390 #define ADC2_MMODE0_8_MSEL_Ch0_Msk (0x3UL)
7392 #define ADC2_SQ0_1_SQ1_Pos (16UL)
7393 #define ADC2_SQ0_1_SQ1_Msk (0x1ff0000UL)
7394 #define ADC2_SQ0_1_SQ0_Pos (0UL)
7395 #define ADC2_SQ0_1_SQ0_Msk (0x1ffUL)
7397 #define ADC2_SQ2_3_SQ3_Pos (16UL)
7398 #define ADC2_SQ2_3_SQ3_Msk (0x1ff0000UL)
7399 #define ADC2_SQ2_3_SQ2_Pos (0UL)
7400 #define ADC2_SQ2_3_SQ2_Msk (0x1ffUL)
7402 #define ADC2_SQ4_5_SQ5_Pos (16UL)
7403 #define ADC2_SQ4_5_SQ5_Msk (0x1ff0000UL)
7404 #define ADC2_SQ4_5_SQ4_Pos (0UL)
7405 #define ADC2_SQ4_5_SQ4_Msk (0x1ffUL)
7407 #define ADC2_SQ6_7_SQ7_Pos (16UL)
7408 #define ADC2_SQ6_7_SQ7_Msk (0x1ff0000UL)
7409 #define ADC2_SQ6_7_SQ6_Pos (0UL)
7410 #define ADC2_SQ6_7_SQ6_Msk (0x1ffUL)
7412 #define ADC2_SQ8_9_SQ8_Pos (0UL)
7413 #define ADC2_SQ8_9_SQ8_Msk (0x1ffUL)
7415 #define ADC2_SQ_FB_CHx_Pos (16UL)
7416 #define ADC2_SQ_FB_CHx_Msk (0xf0000UL)
7417 #define ADC2_SQ_FB_SQx_Pos (11UL)
7418 #define ADC2_SQ_FB_SQx_Msk (0x7800UL)
7419 #define ADC2_SQ_FB_EIM_ACTIVE_Pos (9UL)
7420 #define ADC2_SQ_FB_EIM_ACTIVE_Msk (0x200UL)
7421 #define ADC2_SQ_FB_SQ_STOP_Pos (8UL)
7422 #define ADC2_SQ_FB_SQ_STOP_Msk (0x100UL)
7423 #define ADC2_SQ_FB_SQ_FB_Pos (0UL)
7424 #define ADC2_SQ_FB_SQ_FB_Msk (0xfUL)
7426 #define ADC2_STATUS_READY_Pos (1UL)
7427 #define ADC2_STATUS_READY_Msk (0x2UL)
7429 #define ADC2_TH0_3_LOWER_THLO_CH3_Pos (24UL)
7430 #define ADC2_TH0_3_LOWER_THLO_CH3_Msk (0xff000000UL)
7431 #define ADC2_TH0_3_LOWER_THLO_CH2_Pos (16UL)
7432 #define ADC2_TH0_3_LOWER_THLO_CH2_Msk (0xff0000UL)
7433 #define ADC2_TH0_3_LOWER_THLO_CH1_Pos (8UL)
7434 #define ADC2_TH0_3_LOWER_THLO_CH1_Msk (0xff00UL)
7435 #define ADC2_TH0_3_LOWER_THLO_CH0_Pos (0UL)
7436 #define ADC2_TH0_3_LOWER_THLO_CH0_Msk (0xffUL)
7438 #define ADC2_TH0_3_UPPER_THUP_CH3_Pos (24UL)
7439 #define ADC2_TH0_3_UPPER_THUP_CH3_Msk (0xff000000UL)
7440 #define ADC2_TH0_3_UPPER_THUP_CH2_Pos (16UL)
7441 #define ADC2_TH0_3_UPPER_THUP_CH2_Msk (0xff0000UL)
7442 #define ADC2_TH0_3_UPPER_THUP_CH1_Pos (8UL)
7443 #define ADC2_TH0_3_UPPER_THUP_CH1_Msk (0xff00UL)
7444 #define ADC2_TH0_3_UPPER_THUP_CH0_Pos (0UL)
7445 #define ADC2_TH0_3_UPPER_THUP_CH0_Msk (0xffUL)
7447 #define ADC2_TH4_7_LOWER_THLO_CH7_Pos (24UL)
7448 #define ADC2_TH4_7_LOWER_THLO_CH7_Msk (0xff000000UL)
7449 #define ADC2_TH4_7_LOWER_THLO_CH6_Pos (16UL)
7450 #define ADC2_TH4_7_LOWER_THLO_CH6_Msk (0xff0000UL)
7451 #define ADC2_TH4_7_LOWER_THLO_CH5_Pos (8UL)
7452 #define ADC2_TH4_7_LOWER_THLO_CH5_Msk (0xff00UL)
7453 #define ADC2_TH4_7_LOWER_THLO_CH4_Pos (0UL)
7454 #define ADC2_TH4_7_LOWER_THLO_CH4_Msk (0xffUL)
7456 #define ADC2_TH4_7_UPPER_THUP_CH7_Pos (24UL)
7457 #define ADC2_TH4_7_UPPER_THUP_CH7_Msk (0xff000000UL)
7458 #define ADC2_TH4_7_UPPER_THUP_CH6_Pos (16UL)
7459 #define ADC2_TH4_7_UPPER_THUP_CH6_Msk (0xff0000UL)
7460 #define ADC2_TH4_7_UPPER_THUP_CH5_Pos (8UL)
7461 #define ADC2_TH4_7_UPPER_THUP_CH5_Msk (0xff00UL)
7462 #define ADC2_TH4_7_UPPER_THUP_CH4_Pos (0UL)
7463 #define ADC2_TH4_7_UPPER_THUP_CH4_Msk (0xffUL)
7465 #define ADC2_TH8_11_LOWER_THLO_CH8_Pos (0UL)
7466 #define ADC2_TH8_11_LOWER_THLO_CH8_Msk (0xffUL)
7468 #define ADC2_TH8_11_UPPER_THUP_CH8_Pos (0UL)
7469 #define ADC2_TH8_11_UPPER_THUP_CH8_Msk (0xffUL)
7477 #define BDRV_ASEQC_HB2OFFHYSTEN_Pos (23UL)
7478 #define BDRV_ASEQC_HB2OFFHYSTEN_Msk (0x800000UL)
7479 #define BDRV_ASEQC_HB2ONHYSTEN_Pos (22UL)
7480 #define BDRV_ASEQC_HB2ONHYSTEN_Msk (0x400000UL)
7481 #define BDRV_ASEQC_HB2OPTOFFACT_Pos (21UL)
7482 #define BDRV_ASEQC_HB2OPTOFFACT_Msk (0x200000UL)
7483 #define BDRV_ASEQC_HB2OPTONACT_Pos (20UL)
7484 #define BDRV_ASEQC_HB2OPTONACT_Msk (0x100000UL)
7485 #define BDRV_ASEQC_HB2ASMOFFEN_Pos (17UL)
7486 #define BDRV_ASEQC_HB2ASMOFFEN_Msk (0x20000UL)
7487 #define BDRV_ASEQC_HB2ASMONEN_Pos (16UL)
7488 #define BDRV_ASEQC_HB2ASMONEN_Msk (0x10000UL)
7489 #define BDRV_ASEQC_HB1OFFHYSTEN_Pos (7UL)
7490 #define BDRV_ASEQC_HB1OFFHYSTEN_Msk (0x80UL)
7491 #define BDRV_ASEQC_HB1ONHYSTEN_Pos (6UL)
7492 #define BDRV_ASEQC_HB1ONHYSTEN_Msk (0x40UL)
7493 #define BDRV_ASEQC_HB1OPTOFFACT_Pos (5UL)
7494 #define BDRV_ASEQC_HB1OPTOFFACT_Msk (0x20UL)
7495 #define BDRV_ASEQC_HB1OPTONACT_Pos (4UL)
7496 #define BDRV_ASEQC_HB1OPTONACT_Msk (0x10UL)
7497 #define BDRV_ASEQC_HB1ASMOFFEN_Pos (1UL)
7498 #define BDRV_ASEQC_HB1ASMOFFEN_Msk (0x2UL)
7499 #define BDRV_ASEQC_HB1ASMONEN_Pos (0UL)
7500 #define BDRV_ASEQC_HB1ASMONEN_Msk (0x1UL)
7502 #define BDRV_ASEQERRCNT_HB2MFERRCNT_Pos (20UL)
7503 #define BDRV_ASEQERRCNT_HB2MFERRCNT_Msk (0x300000UL)
7504 #define BDRV_ASEQERRCNT_HB2T12ONERRCNT_Pos (18UL)
7505 #define BDRV_ASEQERRCNT_HB2T12ONERRCNT_Msk (0xc0000UL)
7506 #define BDRV_ASEQERRCNT_HB2T1OFFERRCNT_Pos (16UL)
7507 #define BDRV_ASEQERRCNT_HB2T1OFFERRCNT_Msk (0x30000UL)
7508 #define BDRV_ASEQERRCNT_HB1MFERRCNT_Pos (4UL)
7509 #define BDRV_ASEQERRCNT_HB1MFERRCNT_Msk (0x30UL)
7510 #define BDRV_ASEQERRCNT_HB1T12ONERRCNT_Pos (2UL)
7511 #define BDRV_ASEQERRCNT_HB1T12ONERRCNT_Msk (0xcUL)
7512 #define BDRV_ASEQERRCNT_HB1T1OFFERRCNT_Pos (0UL)
7513 #define BDRV_ASEQERRCNT_HB1T1OFFERRCNT_Msk (0x3UL)
7515 #define BDRV_ASEQIOFFMAX_I1OFFMAX_Pos (0UL)
7516 #define BDRV_ASEQIOFFMAX_I1OFFMAX_Msk (0x3fUL)
7518 #define BDRV_ASEQIOFFMIN_I1OFFMIN_Pos (0UL)
7519 #define BDRV_ASEQIOFFMIN_I1OFFMIN_Msk (0x3fUL)
7521 #define BDRV_ASEQIONMAX_I1ONMAX_Pos (0UL)
7522 #define BDRV_ASEQIONMAX_I1ONMAX_Msk (0x3fUL)
7524 #define BDRV_ASEQIONMIN_I1ONMIN_Pos (0UL)
7525 #define BDRV_ASEQIONMIN_I1ONMIN_Msk (0x3fUL)
7527 #define BDRV_ASEQSTS_HB2ONMF_Pos (31UL)
7528 #define BDRV_ASEQSTS_HB2ONMF_Msk (0x80000000UL)
7529 #define BDRV_ASEQSTS_HB2OFFMF_Pos (30UL)
7530 #define BDRV_ASEQSTS_HB2OFFMF_Msk (0x40000000UL)
7531 #define BDRV_ASEQSTS_HB2I1ONMIN_Pos (23UL)
7532 #define BDRV_ASEQSTS_HB2I1ONMIN_Msk (0x800000UL)
7533 #define BDRV_ASEQSTS_HB2T12ONMIN_Pos (22UL)
7534 #define BDRV_ASEQSTS_HB2T12ONMIN_Msk (0x400000UL)
7535 #define BDRV_ASEQSTS_HB2I1ONMAX_Pos (21UL)
7536 #define BDRV_ASEQSTS_HB2I1ONMAX_Msk (0x200000UL)
7537 #define BDRV_ASEQSTS_HB2T12ONMAX_Pos (20UL)
7538 #define BDRV_ASEQSTS_HB2T12ONMAX_Msk (0x100000UL)
7539 #define BDRV_ASEQSTS_HB2I1OFFMIN_Pos (19UL)
7540 #define BDRV_ASEQSTS_HB2I1OFFMIN_Msk (0x80000UL)
7541 #define BDRV_ASEQSTS_HB2T1OFFMIN_Pos (18UL)
7542 #define BDRV_ASEQSTS_HB2T1OFFMIN_Msk (0x40000UL)
7543 #define BDRV_ASEQSTS_HB2I1OFFMAX_Pos (17UL)
7544 #define BDRV_ASEQSTS_HB2I1OFFMAX_Msk (0x20000UL)
7545 #define BDRV_ASEQSTS_HB2T1OFFMAX_Pos (16UL)
7546 #define BDRV_ASEQSTS_HB2T1OFFMAX_Msk (0x10000UL)
7547 #define BDRV_ASEQSTS_HB1ONMF_Pos (15UL)
7548 #define BDRV_ASEQSTS_HB1ONMF_Msk (0x8000UL)
7549 #define BDRV_ASEQSTS_HB1OFFMF_Pos (14UL)
7550 #define BDRV_ASEQSTS_HB1OFFMF_Msk (0x4000UL)
7551 #define BDRV_ASEQSTS_HB1I1ONMIN_Pos (7UL)
7552 #define BDRV_ASEQSTS_HB1I1ONMIN_Msk (0x80UL)
7553 #define BDRV_ASEQSTS_HB1T12ONMIN_Pos (6UL)
7554 #define BDRV_ASEQSTS_HB1T12ONMIN_Msk (0x40UL)
7555 #define BDRV_ASEQSTS_HB1I1ONMAX_Pos (5UL)
7556 #define BDRV_ASEQSTS_HB1I1ONMAX_Msk (0x20UL)
7557 #define BDRV_ASEQSTS_HB1T12ONMAX_Pos (4UL)
7558 #define BDRV_ASEQSTS_HB1T12ONMAX_Msk (0x10UL)
7559 #define BDRV_ASEQSTS_HB1I1OFFMIN_Pos (3UL)
7560 #define BDRV_ASEQSTS_HB1I1OFFMIN_Msk (0x8UL)
7561 #define BDRV_ASEQSTS_HB1T1OFFMIN_Pos (2UL)
7562 #define BDRV_ASEQSTS_HB1T1OFFMIN_Msk (0x4UL)
7563 #define BDRV_ASEQSTS_HB1I1OFFMAX_Pos (1UL)
7564 #define BDRV_ASEQSTS_HB1I1OFFMAX_Msk (0x2UL)
7565 #define BDRV_ASEQSTS_HB1T1OFFMAX_Pos (0UL)
7566 #define BDRV_ASEQSTS_HB1T1OFFMAX_Msk (0x1UL)
7568 #define BDRV_CP_CLK_CTRL_CPCLKDIS_SET_Pos (16UL)
7569 #define BDRV_CP_CLK_CTRL_CPCLKDIS_SET_Msk (0x10000UL)
7570 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Pos (15UL)
7571 #define BDRV_CP_CLK_CTRL_CPCLK_EN_Msk (0x8000UL)
7572 #define BDRV_CP_CLK_CTRL_F_CP_Pos (13UL)
7573 #define BDRV_CP_CLK_CTRL_F_CP_Msk (0x6000UL)
7574 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Pos (8UL)
7575 #define BDRV_CP_CLK_CTRL_DITH_UPPER_Msk (0x1f00UL)
7576 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Pos (0UL)
7577 #define BDRV_CP_CLK_CTRL_DITH_LOWER_Msk (0x1fUL)
7579 #define BDRV_CP_CTRL_CP_STAGE_SEL_Pos (29UL)
7580 #define BDRV_CP_CTRL_CP_STAGE_SEL_Msk (0x60000000UL)
7581 #define BDRV_CP_CTRL_VCP14_15V_SEL_Pos (28UL)
7582 #define BDRV_CP_CTRL_VCP14_15V_SEL_Msk (0x10000000UL)
7583 #define BDRV_CP_CTRL_VTHVCP_TRIM_Pos (26UL)
7584 #define BDRV_CP_CTRL_VTHVCP_TRIM_Msk (0xc000000UL)
7585 #define BDRV_CP_CTRL_VCP9V_SET_Pos (25UL)
7586 #define BDRV_CP_CTRL_VCP9V_SET_Msk (0x2000000UL)
7587 #define BDRV_CP_CTRL_CPLOPWRM_EN_Pos (24UL)
7588 #define BDRV_CP_CTRL_CPLOPWRM_EN_Msk (0x1000000UL)
7589 #define BDRV_CP_CTRL_DRVx_VSDUP_DIS_Pos (22UL)
7590 #define BDRV_CP_CTRL_DRVx_VSDUP_DIS_Msk (0x400000UL)
7591 #define BDRV_CP_CTRL_DRVx_VSDLO_DIS_Pos (20UL)
7592 #define BDRV_CP_CTRL_DRVx_VSDLO_DIS_Msk (0x100000UL)
7593 #define BDRV_CP_CTRL_DRVx_VCPUP_DIS_Pos (18UL)
7594 #define BDRV_CP_CTRL_DRVx_VCPUP_DIS_Msk (0x40000UL)
7595 #define BDRV_CP_CTRL_DRVx_VCPLO_SDEN_Pos (17UL)
7596 #define BDRV_CP_CTRL_DRVx_VCPLO_SDEN_Msk (0x20000UL)
7597 #define BDRV_CP_CTRL_DRVx_VCPLO_DIS_Pos (16UL)
7598 #define BDRV_CP_CTRL_DRVx_VCPLO_DIS_Msk (0x10000UL)
7599 #define BDRV_CP_CTRL_CP_RDY_EN_Pos (2UL)
7600 #define BDRV_CP_CTRL_CP_RDY_EN_Msk (0x4UL)
7601 #define BDRV_CP_CTRL_CP_EN_Pos (0UL)
7602 #define BDRV_CP_CTRL_CP_EN_Msk (0x1UL)
7604 #define BDRV_CP_IRQCLR_VSD_UPTH_SC_Pos (31UL)
7605 #define BDRV_CP_IRQCLR_VSD_UPTH_SC_Msk (0x80000000UL)
7606 #define BDRV_CP_IRQCLR_VSD_LOTH_SC_Pos (29UL)
7607 #define BDRV_CP_IRQCLR_VSD_LOTH_SC_Msk (0x20000000UL)
7608 #define BDRV_CP_IRQCLR_VCP_UPTH_SC_Pos (27UL)
7609 #define BDRV_CP_IRQCLR_VCP_UPTH_SC_Msk (0x8000000UL)
7610 #define BDRV_CP_IRQCLR_VCP_LOTH1_SC_Pos (25UL)
7611 #define BDRV_CP_IRQCLR_VCP_LOTH1_SC_Msk (0x2000000UL)
7612 #define BDRV_CP_IRQCLR_VCP_OTSD_SC_Pos (20UL)
7613 #define BDRV_CP_IRQCLR_VCP_OTSD_SC_Msk (0x100000UL)
7614 #define BDRV_CP_IRQCLR_VCP_OTW_SC_Pos (16UL)
7615 #define BDRV_CP_IRQCLR_VCP_OTW_SC_Msk (0x10000UL)
7616 #define BDRV_CP_IRQCLR_VSD_UPTH_ISC_Pos (15UL)
7617 #define BDRV_CP_IRQCLR_VSD_UPTH_ISC_Msk (0x8000UL)
7618 #define BDRV_CP_IRQCLR_VSD_LOTH_ISC_Pos (13UL)
7619 #define BDRV_CP_IRQCLR_VSD_LOTH_ISC_Msk (0x2000UL)
7620 #define BDRV_CP_IRQCLR_VCP_UPTH_ISC_Pos (11UL)
7621 #define BDRV_CP_IRQCLR_VCP_UPTH_ISC_Msk (0x800UL)
7622 #define BDRV_CP_IRQCLR_VCP_LOTH1_ISC_Pos (9UL)
7623 #define BDRV_CP_IRQCLR_VCP_LOTH1_ISC_Msk (0x200UL)
7624 #define BDRV_CP_IRQCLR_VCP_OTSD_ISC_Pos (4UL)
7625 #define BDRV_CP_IRQCLR_VCP_OTSD_ISC_Msk (0x10UL)
7626 #define BDRV_CP_IRQCLR_VCP_OTW_ISC_Pos (0UL)
7627 #define BDRV_CP_IRQCLR_VCP_OTW_ISC_Msk (0x1UL)
7629 #define BDRV_CP_IRQEN_VSD_UPTH_IEN_Pos (15UL)
7630 #define BDRV_CP_IRQEN_VSD_UPTH_IEN_Msk (0x8000UL)
7631 #define BDRV_CP_IRQEN_VSD_LOTH_IEN_Pos (13UL)
7632 #define BDRV_CP_IRQEN_VSD_LOTH_IEN_Msk (0x2000UL)
7633 #define BDRV_CP_IRQEN_VCP_UPTH_IEN_Pos (11UL)
7634 #define BDRV_CP_IRQEN_VCP_UPTH_IEN_Msk (0x800UL)
7635 #define BDRV_CP_IRQEN_VCP_LOTH1_IEN_Pos (9UL)
7636 #define BDRV_CP_IRQEN_VCP_LOTH1_IEN_Msk (0x200UL)
7637 #define BDRV_CP_IRQEN_VCP_OTSD_IEN_Pos (4UL)
7638 #define BDRV_CP_IRQEN_VCP_OTSD_IEN_Msk (0x10UL)
7639 #define BDRV_CP_IRQEN_VCP_OTW_IEN_Pos (0UL)
7640 #define BDRV_CP_IRQEN_VCP_OTW_IEN_Msk (0x1UL)
7642 #define BDRV_CP_IRQS_VSD_UPTH_STS_Pos (31UL)
7643 #define BDRV_CP_IRQS_VSD_UPTH_STS_Msk (0x80000000UL)
7644 #define BDRV_CP_IRQS_VSD_LOTH_STS_Pos (29UL)
7645 #define BDRV_CP_IRQS_VSD_LOTH_STS_Msk (0x20000000UL)
7646 #define BDRV_CP_IRQS_VCP_UPTH_STS_Pos (27UL)
7647 #define BDRV_CP_IRQS_VCP_UPTH_STS_Msk (0x8000000UL)
7648 #define BDRV_CP_IRQS_VCP_LOTH1_STS_Pos (25UL)
7649 #define BDRV_CP_IRQS_VCP_LOTH1_STS_Msk (0x2000000UL)
7650 #define BDRV_CP_IRQS_VCP_OTSD_STS_Pos (20UL)
7651 #define BDRV_CP_IRQS_VCP_OTSD_STS_Msk (0x100000UL)
7652 #define BDRV_CP_IRQS_VCP_OTW_STS_Pos (16UL)
7653 #define BDRV_CP_IRQS_VCP_OTW_STS_Msk (0x10000UL)
7654 #define BDRV_CP_IRQS_VSD_UPTH_IS_Pos (15UL)
7655 #define BDRV_CP_IRQS_VSD_UPTH_IS_Msk (0x8000UL)
7656 #define BDRV_CP_IRQS_VSD_LOTH_IS_Pos (13UL)
7657 #define BDRV_CP_IRQS_VSD_LOTH_IS_Msk (0x2000UL)
7658 #define BDRV_CP_IRQS_VCP_UPTH_IS_Pos (11UL)
7659 #define BDRV_CP_IRQS_VCP_UPTH_IS_Msk (0x800UL)
7660 #define BDRV_CP_IRQS_VCP_LOTH1_IS_Pos (9UL)
7661 #define BDRV_CP_IRQS_VCP_LOTH1_IS_Msk (0x200UL)
7662 #define BDRV_CP_IRQS_VCP_OTSD_IS_Pos (4UL)
7663 #define BDRV_CP_IRQS_VCP_OTSD_IS_Msk (0x10UL)
7664 #define BDRV_CP_IRQS_VCP_OTW_IS_Pos (0UL)
7665 #define BDRV_CP_IRQS_VCP_OTW_IS_Msk (0x1UL)
7667 #define BDRV_CTRL1_HS2_OC_DIS_Pos (31UL)
7668 #define BDRV_CTRL1_HS2_OC_DIS_Msk (0x80000000UL)
7669 #define BDRV_CTRL1_HS2_SUPERR_STS_Pos (29UL)
7670 #define BDRV_CTRL1_HS2_SUPERR_STS_Msk (0x20000000UL)
7671 #define BDRV_CTRL1_HS2_DCS_EN_Pos (27UL)
7672 #define BDRV_CTRL1_HS2_DCS_EN_Msk (0x8000000UL)
7673 #define BDRV_CTRL1_HS2_ON_Pos (26UL)
7674 #define BDRV_CTRL1_HS2_ON_Msk (0x4000000UL)
7675 #define BDRV_CTRL1_HS2_PWM_Pos (25UL)
7676 #define BDRV_CTRL1_HS2_PWM_Msk (0x2000000UL)
7677 #define BDRV_CTRL1_HS2_EN_Pos (24UL)
7678 #define BDRV_CTRL1_HS2_EN_Msk (0x1000000UL)
7679 #define BDRV_CTRL1_HS1_OC_DIS_Pos (23UL)
7680 #define BDRV_CTRL1_HS1_OC_DIS_Msk (0x800000UL)
7681 #define BDRV_CTRL1_HS1_SUPERR_STS_Pos (21UL)
7682 #define BDRV_CTRL1_HS1_SUPERR_STS_Msk (0x200000UL)
7683 #define BDRV_CTRL1_HS1_DCS_EN_Pos (19UL)
7684 #define BDRV_CTRL1_HS1_DCS_EN_Msk (0x80000UL)
7685 #define BDRV_CTRL1_HS1_ON_Pos (18UL)
7686 #define BDRV_CTRL1_HS1_ON_Msk (0x40000UL)
7687 #define BDRV_CTRL1_HS1_PWM_Pos (17UL)
7688 #define BDRV_CTRL1_HS1_PWM_Msk (0x20000UL)
7689 #define BDRV_CTRL1_HS1_EN_Pos (16UL)
7690 #define BDRV_CTRL1_HS1_EN_Msk (0x10000UL)
7691 #define BDRV_CTRL1_LS2_OC_DIS_Pos (15UL)
7692 #define BDRV_CTRL1_LS2_OC_DIS_Msk (0x8000UL)
7693 #define BDRV_CTRL1_LS2_SUPERR_STS_Pos (13UL)
7694 #define BDRV_CTRL1_LS2_SUPERR_STS_Msk (0x2000UL)
7695 #define BDRV_CTRL1_LS2_ON_Pos (10UL)
7696 #define BDRV_CTRL1_LS2_ON_Msk (0x400UL)
7697 #define BDRV_CTRL1_LS2_PWM_Pos (9UL)
7698 #define BDRV_CTRL1_LS2_PWM_Msk (0x200UL)
7699 #define BDRV_CTRL1_LS2_EN_Pos (8UL)
7700 #define BDRV_CTRL1_LS2_EN_Msk (0x100UL)
7701 #define BDRV_CTRL1_LS1_OC_DIS_Pos (7UL)
7702 #define BDRV_CTRL1_LS1_OC_DIS_Msk (0x80UL)
7703 #define BDRV_CTRL1_LS1_SUPERR_STS_Pos (5UL)
7704 #define BDRV_CTRL1_LS1_SUPERR_STS_Msk (0x20UL)
7705 #define BDRV_CTRL1_LS1_ON_Pos (2UL)
7706 #define BDRV_CTRL1_LS1_ON_Msk (0x4UL)
7707 #define BDRV_CTRL1_LS1_PWM_Pos (1UL)
7708 #define BDRV_CTRL1_LS1_PWM_Msk (0x2UL)
7709 #define BDRV_CTRL1_LS1_EN_Pos (0UL)
7710 #define BDRV_CTRL1_LS1_EN_Msk (0x1UL)
7712 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Pos (31UL)
7713 #define BDRV_CTRL2_DLY_DIAG_DIRSEL_Msk (0x80000000UL)
7714 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Pos (28UL)
7715 #define BDRV_CTRL2_DLY_DIAG_CHSEL_Msk (0x70000000UL)
7716 #define BDRV_CTRL2_DLY_DIAG_STS_Pos (27UL)
7717 #define BDRV_CTRL2_DLY_DIAG_STS_Msk (0x8000000UL)
7718 #define BDRV_CTRL2_DLY_DIAG_SCLR_Pos (26UL)
7719 #define BDRV_CTRL2_DLY_DIAG_SCLR_Msk (0x4000000UL)
7720 #define BDRV_CTRL2_DLY_DIAG_TIM_Pos (16UL)
7721 #define BDRV_CTRL2_DLY_DIAG_TIM_Msk (0x3ff0000UL)
7722 #define BDRV_CTRL2_HB2OFFSEQCNF_Pos (3UL)
7723 #define BDRV_CTRL2_HB2OFFSEQCNF_Msk (0x8UL)
7724 #define BDRV_CTRL2_HB1OFFSEQCNF_Pos (2UL)
7725 #define BDRV_CTRL2_HB1OFFSEQCNF_Msk (0x4UL)
7726 #define BDRV_CTRL2_HB2ONSEQCNF_Pos (1UL)
7727 #define BDRV_CTRL2_HB2ONSEQCNF_Msk (0x2UL)
7728 #define BDRV_CTRL2_HB1ONSEQCNF_Pos (0UL)
7729 #define BDRV_CTRL2_HB1ONSEQCNF_Msk (0x1UL)
7731 #define BDRV_CTRL3_DRV_CCP_DIS_Pos (30UL)
7732 #define BDRV_CTRL3_DRV_CCP_DIS_Msk (0x40000000UL)
7733 #define BDRV_CTRL3_DRV_CCP_TMUL_Pos (28UL)
7734 #define BDRV_CTRL3_DRV_CCP_TMUL_Msk (0x30000000UL)
7735 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Pos (24UL)
7736 #define BDRV_CTRL3_DRV_CCP_TIMSEL_Msk (0x3000000UL)
7737 #define BDRV_CTRL3_DSMONVTH_Pos (16UL)
7738 #define BDRV_CTRL3_DSMONVTH_Msk (0x70000UL)
7740 #define BDRV_DCTRIM_DRVx_COMPENS_LS_Pos (16UL)
7741 #define BDRV_DCTRIM_DRVx_COMPENS_LS_Msk (0x70000UL)
7742 #define BDRV_DCTRIM_DRVx_COMPENS_HS_Pos (8UL)
7743 #define BDRV_DCTRIM_DRVx_COMPENS_HS_Msk (0x700UL)
7745 #define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_CLR_Pos (31UL)
7746 #define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_CLR_Msk (0x80000000UL)
7747 #define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_Pos (30UL)
7748 #define BDRV_HB1ASEQOFFVAL_HB1_OFFVALVF_Msk (0x40000000UL)
7749 #define BDRV_HB1ASEQOFFVAL_HB1_T2MERR_Pos (22UL)
7750 #define BDRV_HB1ASEQOFFVAL_HB1_T2MERR_Msk (0x400000UL)
7751 #define BDRV_HB1ASEQOFFVAL_HB1_T2OFFCNT_Pos (16UL)
7752 #define BDRV_HB1ASEQOFFVAL_HB1_T2OFFCNT_Msk (0x3f0000UL)
7753 #define BDRV_HB1ASEQOFFVAL_HB1_I1OFFVAL_Pos (8UL)
7754 #define BDRV_HB1ASEQOFFVAL_HB1_I1OFFVAL_Msk (0x3f00UL)
7755 #define BDRV_HB1ASEQOFFVAL_HB1_T1OFFCNT_Pos (0UL)
7756 #define BDRV_HB1ASEQOFFVAL_HB1_T1OFFCNT_Msk (0xffUL)
7758 #define BDRV_HB1ASEQONVAL_HB1_ONVALVF_CLR_Pos (31UL)
7759 #define BDRV_HB1ASEQONVAL_HB1_ONVALVF_CLR_Msk (0x80000000UL)
7760 #define BDRV_HB1ASEQONVAL_HB1_ONVALVF_Pos (30UL)
7761 #define BDRV_HB1ASEQONVAL_HB1_ONVALVF_Msk (0x40000000UL)
7762 #define BDRV_HB1ASEQONVAL_HB1_T3MERR_Pos (22UL)
7763 #define BDRV_HB1ASEQONVAL_HB1_T3MERR_Msk (0x400000UL)
7764 #define BDRV_HB1ASEQONVAL_HB1_T3ONCNT_Pos (16UL)
7765 #define BDRV_HB1ASEQONVAL_HB1_T3ONCNT_Msk (0x3f0000UL)
7766 #define BDRV_HB1ASEQONVAL_HB1_I1ONVAL_Pos (8UL)
7767 #define BDRV_HB1ASEQONVAL_HB1_I1ONVAL_Msk (0x3f00UL)
7768 #define BDRV_HB1ASEQONVAL_HB1_T12ONCNT_Pos (0UL)
7769 #define BDRV_HB1ASEQONVAL_HB1_T12ONCNT_Msk (0xffUL)
7771 #define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_CLR_Pos (31UL)
7772 #define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_CLR_Msk (0x80000000UL)
7773 #define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_Pos (30UL)
7774 #define BDRV_HB2ASEQOFFVAL_HB2_OFFVALVF_Msk (0x40000000UL)
7775 #define BDRV_HB2ASEQOFFVAL_HB2_T2MERR_Pos (22UL)
7776 #define BDRV_HB2ASEQOFFVAL_HB2_T2MERR_Msk (0x400000UL)
7777 #define BDRV_HB2ASEQOFFVAL_HB2_T2OFFCNT_Pos (16UL)
7778 #define BDRV_HB2ASEQOFFVAL_HB2_T2OFFCNT_Msk (0x3f0000UL)
7779 #define BDRV_HB2ASEQOFFVAL_HB2_I1OFFVAL_Pos (8UL)
7780 #define BDRV_HB2ASEQOFFVAL_HB2_I1OFFVAL_Msk (0x3f00UL)
7781 #define BDRV_HB2ASEQOFFVAL_HB2_T1OFFCNT_Pos (0UL)
7782 #define BDRV_HB2ASEQOFFVAL_HB2_T1OFFCNT_Msk (0xffUL)
7784 #define BDRV_HB2ASEQONVAL_HB2_ONVALVF_CLR_Pos (31UL)
7785 #define BDRV_HB2ASEQONVAL_HB2_ONVALVF_CLR_Msk (0x80000000UL)
7786 #define BDRV_HB2ASEQONVAL_HB2_ONVALVF_Pos (30UL)
7787 #define BDRV_HB2ASEQONVAL_HB2_ONVALVF_Msk (0x40000000UL)
7788 #define BDRV_HB2ASEQONVAL_HB2_T3MERR_Pos (22UL)
7789 #define BDRV_HB2ASEQONVAL_HB2_T3MERR_Msk (0x400000UL)
7790 #define BDRV_HB2ASEQONVAL_HB2_T3ONCNT_Pos (16UL)
7791 #define BDRV_HB2ASEQONVAL_HB2_T3ONCNT_Msk (0x3f0000UL)
7792 #define BDRV_HB2ASEQONVAL_HB2_I1ONVAL_Pos (8UL)
7793 #define BDRV_HB2ASEQONVAL_HB2_I1ONVAL_Msk (0x3f00UL)
7794 #define BDRV_HB2ASEQONVAL_HB2_T12ONCNT_Pos (0UL)
7795 #define BDRV_HB2ASEQONVAL_HB2_T12ONCNT_Msk (0xffUL)
7797 #define BDRV_IGATECLMPOFFC_HB2AF_ICLMPOFF_Pos (24UL)
7798 #define BDRV_IGATECLMPOFFC_HB2AF_ICLMPOFF_Msk (0x3f000000UL)
7799 #define BDRV_IGATECLMPOFFC_HB1AF_ICLMPOFF_Pos (16UL)
7800 #define BDRV_IGATECLMPOFFC_HB1AF_ICLMPOFF_Msk (0x3f0000UL)
7801 #define BDRV_IGATECLMPOFFC_HB2_ICLMPOFF_Pos (8UL)
7802 #define BDRV_IGATECLMPOFFC_HB2_ICLMPOFF_Msk (0x3f00UL)
7803 #define BDRV_IGATECLMPOFFC_HB1_ICLMPOFF_Pos (0UL)
7804 #define BDRV_IGATECLMPOFFC_HB1_ICLMPOFF_Msk (0x3fUL)
7806 #define BDRV_IGATECLMPONC_HB2AF_ICLMPON_Pos (24UL)
7807 #define BDRV_IGATECLMPONC_HB2AF_ICLMPON_Msk (0x3f000000UL)
7808 #define BDRV_IGATECLMPONC_HB1AF_ICLMPON_Pos (16UL)
7809 #define BDRV_IGATECLMPONC_HB1AF_ICLMPON_Msk (0x3f0000UL)
7810 #define BDRV_IGATECLMPONC_HB2_ICLMPON_Pos (8UL)
7811 #define BDRV_IGATECLMPONC_HB2_ICLMPON_Msk (0x3f00UL)
7812 #define BDRV_IGATECLMPONC_HB1_ICLMPON_Pos (0UL)
7813 #define BDRV_IGATECLMPONC_HB1_ICLMPON_Msk (0x3fUL)
7815 #define BDRV_IRQCLR_SEQ_ERR_ISC_Pos (31UL)
7816 #define BDRV_IRQCLR_SEQ_ERR_ISC_Msk (0x80000000UL)
7817 #define BDRV_IRQCLR_HS2_OC_ISC_Pos (30UL)
7818 #define BDRV_IRQCLR_HS2_OC_ISC_Msk (0x40000000UL)
7819 #define BDRV_IRQCLR_HS2_DS_SC_Pos (29UL)
7820 #define BDRV_IRQCLR_HS2_DS_SC_Msk (0x20000000UL)
7821 #define BDRV_IRQCLR_HS2_DS_ISC_Pos (28UL)
7822 #define BDRV_IRQCLR_HS2_DS_ISC_Msk (0x10000000UL)
7823 #define BDRV_IRQCLR_HS1_OC_ISC_Pos (22UL)
7824 #define BDRV_IRQCLR_HS1_OC_ISC_Msk (0x400000UL)
7825 #define BDRV_IRQCLR_HS1_DS_SC_Pos (21UL)
7826 #define BDRV_IRQCLR_HS1_DS_SC_Msk (0x200000UL)
7827 #define BDRV_IRQCLR_HS1_DS_ISC_Pos (20UL)
7828 #define BDRV_IRQCLR_HS1_DS_ISC_Msk (0x100000UL)
7829 #define BDRV_IRQCLR_LS2_OC_ISC_Pos (14UL)
7830 #define BDRV_IRQCLR_LS2_OC_ISC_Msk (0x4000UL)
7831 #define BDRV_IRQCLR_LS2_DS_SC_Pos (13UL)
7832 #define BDRV_IRQCLR_LS2_DS_SC_Msk (0x2000UL)
7833 #define BDRV_IRQCLR_LS2_DS_ISC_Pos (12UL)
7834 #define BDRV_IRQCLR_LS2_DS_ISC_Msk (0x1000UL)
7835 #define BDRV_IRQCLR_LS1_OC_ISC_Pos (6UL)
7836 #define BDRV_IRQCLR_LS1_OC_ISC_Msk (0x40UL)
7837 #define BDRV_IRQCLR_LS1_DS_SC_Pos (5UL)
7838 #define BDRV_IRQCLR_LS1_DS_SC_Msk (0x20UL)
7839 #define BDRV_IRQCLR_LS1_DS_ISC_Pos (4UL)
7840 #define BDRV_IRQCLR_LS1_DS_ISC_Msk (0x10UL)
7841 #define BDRV_IRQCLR_HB2_ASEQ_ISC_Pos (1UL)
7842 #define BDRV_IRQCLR_HB2_ASEQ_ISC_Msk (0x2UL)
7843 #define BDRV_IRQCLR_HB1_ASEQ_ISC_Pos (0UL)
7844 #define BDRV_IRQCLR_HB1_ASEQ_ISC_Msk (0x1UL)
7846 #define BDRV_IRQEN_SEQ_ERR_IEN_Pos (31UL)
7847 #define BDRV_IRQEN_SEQ_ERR_IEN_Msk (0x80000000UL)
7848 #define BDRV_IRQEN_HS2_OC_IEN_Pos (30UL)
7849 #define BDRV_IRQEN_HS2_OC_IEN_Msk (0x40000000UL)
7850 #define BDRV_IRQEN_HS2_DS_IEN_Pos (28UL)
7851 #define BDRV_IRQEN_HS2_DS_IEN_Msk (0x10000000UL)
7852 #define BDRV_IRQEN_HS1_OC_IEN_Pos (22UL)
7853 #define BDRV_IRQEN_HS1_OC_IEN_Msk (0x400000UL)
7854 #define BDRV_IRQEN_HS1_DS_IEN_Pos (20UL)
7855 #define BDRV_IRQEN_HS1_DS_IEN_Msk (0x100000UL)
7856 #define BDRV_IRQEN_LS2_OC_IEN_Pos (14UL)
7857 #define BDRV_IRQEN_LS2_OC_IEN_Msk (0x4000UL)
7858 #define BDRV_IRQEN_LS2_DS_IEN_Pos (12UL)
7859 #define BDRV_IRQEN_LS2_DS_IEN_Msk (0x1000UL)
7860 #define BDRV_IRQEN_LS1_OC_IEN_Pos (6UL)
7861 #define BDRV_IRQEN_LS1_OC_IEN_Msk (0x40UL)
7862 #define BDRV_IRQEN_LS1_DS_IEN_Pos (4UL)
7863 #define BDRV_IRQEN_LS1_DS_IEN_Msk (0x10UL)
7864 #define BDRV_IRQEN_HB2_ASEQ_IEN_Pos (1UL)
7865 #define BDRV_IRQEN_HB2_ASEQ_IEN_Msk (0x2UL)
7866 #define BDRV_IRQEN_HB1_ASEQ_IEN_Pos (0UL)
7867 #define BDRV_IRQEN_HB1_ASEQ_IEN_Msk (0x1UL)
7869 #define BDRV_IRQS_SEQ_ERR_IS_Pos (31UL)
7870 #define BDRV_IRQS_SEQ_ERR_IS_Msk (0x80000000UL)
7871 #define BDRV_IRQS_HS2_OC_IS_Pos (30UL)
7872 #define BDRV_IRQS_HS2_OC_IS_Msk (0x40000000UL)
7873 #define BDRV_IRQS_HS2_DS_STS_Pos (29UL)
7874 #define BDRV_IRQS_HS2_DS_STS_Msk (0x20000000UL)
7875 #define BDRV_IRQS_HS2_DS_IS_Pos (28UL)
7876 #define BDRV_IRQS_HS2_DS_IS_Msk (0x10000000UL)
7877 #define BDRV_IRQS_HS1_OC_IS_Pos (22UL)
7878 #define BDRV_IRQS_HS1_OC_IS_Msk (0x400000UL)
7879 #define BDRV_IRQS_HS1_DS_STS_Pos (21UL)
7880 #define BDRV_IRQS_HS1_DS_STS_Msk (0x200000UL)
7881 #define BDRV_IRQS_HS1_DS_IS_Pos (20UL)
7882 #define BDRV_IRQS_HS1_DS_IS_Msk (0x100000UL)
7883 #define BDRV_IRQS_LS2_OC_IS_Pos (14UL)
7884 #define BDRV_IRQS_LS2_OC_IS_Msk (0x4000UL)
7885 #define BDRV_IRQS_LS2_DS_STS_Pos (13UL)
7886 #define BDRV_IRQS_LS2_DS_STS_Msk (0x2000UL)
7887 #define BDRV_IRQS_LS2_DS_IS_Pos (12UL)
7888 #define BDRV_IRQS_LS2_DS_IS_Msk (0x1000UL)
7889 #define BDRV_IRQS_LS1_OC_IS_Pos (6UL)
7890 #define BDRV_IRQS_LS1_OC_IS_Msk (0x40UL)
7891 #define BDRV_IRQS_LS1_DS_STS_Pos (5UL)
7892 #define BDRV_IRQS_LS1_DS_STS_Msk (0x20UL)
7893 #define BDRV_IRQS_LS1_DS_IS_Pos (4UL)
7894 #define BDRV_IRQS_LS1_DS_IS_Msk (0x10UL)
7895 #define BDRV_IRQS_HB2_ASEQ_IS_Pos (1UL)
7896 #define BDRV_IRQS_HB2_ASEQ_IS_Msk (0x2UL)
7897 #define BDRV_IRQS_HB1_ASEQ_IS_Pos (0UL)
7898 #define BDRV_IRQS_HB1_ASEQ_IS_Msk (0x1UL)
7900 #define BDRV_OFFASEQTMAX_T1OFFMAX_Pos (0UL)
7901 #define BDRV_OFFASEQTMAX_T1OFFMAX_Msk (0xffUL)
7903 #define BDRV_OFFASEQTMIN_HB2T1OFFADDDLY_Pos (12UL)
7904 #define BDRV_OFFASEQTMIN_HB2T1OFFADDDLY_Msk (0xf000UL)
7905 #define BDRV_OFFASEQTMIN_HB1T1OFFADDDLY_Pos (8UL)
7906 #define BDRV_OFFASEQTMIN_HB1T1OFFADDDLY_Msk (0xf00UL)
7907 #define BDRV_OFFASEQTMIN_T1OFFMIN_Pos (0UL)
7908 #define BDRV_OFFASEQTMIN_T1OFFMIN_Msk (0xffUL)
7910 #define BDRV_OFFSEQHB1IC_HB1_I4OFF_Pos (24UL)
7911 #define BDRV_OFFSEQHB1IC_HB1_I4OFF_Msk (0x3f000000UL)
7912 #define BDRV_OFFSEQHB1IC_HB1_I3OFF_Pos (16UL)
7913 #define BDRV_OFFSEQHB1IC_HB1_I3OFF_Msk (0x3f0000UL)
7914 #define BDRV_OFFSEQHB1IC_HB1_I2OFF_Pos (8UL)
7915 #define BDRV_OFFSEQHB1IC_HB1_I2OFF_Msk (0x3f00UL)
7916 #define BDRV_OFFSEQHB1IC_HB1_I1OFF_Pos (0UL)
7917 #define BDRV_OFFSEQHB1IC_HB1_I1OFF_Msk (0x3fUL)
7919 #define BDRV_OFFSEQHB1TC_HB1_T4OFF_Pos (24UL)
7920 #define BDRV_OFFSEQHB1TC_HB1_T4OFF_Msk (0xff000000UL)
7921 #define BDRV_OFFSEQHB1TC_HB1_T3OFF_Pos (16UL)
7922 #define BDRV_OFFSEQHB1TC_HB1_T3OFF_Msk (0x3f0000UL)
7923 #define BDRV_OFFSEQHB1TC_HB1_T2OFF_Pos (8UL)
7924 #define BDRV_OFFSEQHB1TC_HB1_T2OFF_Msk (0x3f00UL)
7925 #define BDRV_OFFSEQHB1TC_HB1_T1OFF_Pos (0UL)
7926 #define BDRV_OFFSEQHB1TC_HB1_T1OFF_Msk (0xffUL)
7928 #define BDRV_OFFSEQHB2IC_HB2_I4OFF_Pos (24UL)
7929 #define BDRV_OFFSEQHB2IC_HB2_I4OFF_Msk (0x3f000000UL)
7930 #define BDRV_OFFSEQHB2IC_HB2_I3OFF_Pos (16UL)
7931 #define BDRV_OFFSEQHB2IC_HB2_I3OFF_Msk (0x3f0000UL)
7932 #define BDRV_OFFSEQHB2IC_HB2_I2OFF_Pos (8UL)
7933 #define BDRV_OFFSEQHB2IC_HB2_I2OFF_Msk (0x3f00UL)
7934 #define BDRV_OFFSEQHB2IC_HB2_I1OFF_Pos (0UL)
7935 #define BDRV_OFFSEQHB2IC_HB2_I1OFF_Msk (0x3fUL)
7937 #define BDRV_OFFSEQHB2TC_HB2_T4OFF_Pos (24UL)
7938 #define BDRV_OFFSEQHB2TC_HB2_T4OFF_Msk (0xff000000UL)
7939 #define BDRV_OFFSEQHB2TC_HB2_T3OFF_Pos (16UL)
7940 #define BDRV_OFFSEQHB2TC_HB2_T3OFF_Msk (0x3f0000UL)
7941 #define BDRV_OFFSEQHB2TC_HB2_T2OFF_Pos (8UL)
7942 #define BDRV_OFFSEQHB2TC_HB2_T2OFF_Msk (0x3f00UL)
7943 #define BDRV_OFFSEQHB2TC_HB2_T1OFF_Pos (0UL)
7944 #define BDRV_OFFSEQHB2TC_HB2_T1OFF_Msk (0xffUL)
7946 #define BDRV_ONASEQTMAX_T12ONMAX_Pos (0UL)
7947 #define BDRV_ONASEQTMAX_T12ONMAX_Msk (0xffUL)
7949 #define BDRV_ONASEQTMIN_T12ONMIN_Pos (0UL)
7950 #define BDRV_ONASEQTMIN_T12ONMIN_Msk (0xffUL)
7952 #define BDRV_ONSEQHB1IC_HB1_I4ON_Pos (24UL)
7953 #define BDRV_ONSEQHB1IC_HB1_I4ON_Msk (0x3f000000UL)
7954 #define BDRV_ONSEQHB1IC_HB1_I3ON_Pos (16UL)
7955 #define BDRV_ONSEQHB1IC_HB1_I3ON_Msk (0x3f0000UL)
7956 #define BDRV_ONSEQHB1IC_HB1_I2ON_Pos (8UL)
7957 #define BDRV_ONSEQHB1IC_HB1_I2ON_Msk (0x3f00UL)
7958 #define BDRV_ONSEQHB1IC_HB1_I1ON_Pos (0UL)
7959 #define BDRV_ONSEQHB1IC_HB1_I1ON_Msk (0x3fUL)
7961 #define BDRV_ONSEQHB1TC_HB1_T4ON_Pos (24UL)
7962 #define BDRV_ONSEQHB1TC_HB1_T4ON_Msk (0xff000000UL)
7963 #define BDRV_ONSEQHB1TC_HB1_T3ON_Pos (16UL)
7964 #define BDRV_ONSEQHB1TC_HB1_T3ON_Msk (0x3f0000UL)
7965 #define BDRV_ONSEQHB1TC_HB1_T2ON_Pos (8UL)
7966 #define BDRV_ONSEQHB1TC_HB1_T2ON_Msk (0x3f00UL)
7967 #define BDRV_ONSEQHB1TC_HB1_T1ON_Pos (0UL)
7968 #define BDRV_ONSEQHB1TC_HB1_T1ON_Msk (0xffUL)
7970 #define BDRV_ONSEQHB2IC_HB2_I4ON_Pos (24UL)
7971 #define BDRV_ONSEQHB2IC_HB2_I4ON_Msk (0x3f000000UL)
7972 #define BDRV_ONSEQHB2IC_HB2_I3ON_Pos (16UL)
7973 #define BDRV_ONSEQHB2IC_HB2_I3ON_Msk (0x3f0000UL)
7974 #define BDRV_ONSEQHB2IC_HB2_I2ON_Pos (8UL)
7975 #define BDRV_ONSEQHB2IC_HB2_I2ON_Msk (0x3f00UL)
7976 #define BDRV_ONSEQHB2IC_HB2_I1ON_Pos (0UL)
7977 #define BDRV_ONSEQHB2IC_HB2_I1ON_Msk (0x3fUL)
7979 #define BDRV_ONSEQHB2TC_HB2_T4ON_Pos (24UL)
7980 #define BDRV_ONSEQHB2TC_HB2_T4ON_Msk (0xff000000UL)
7981 #define BDRV_ONSEQHB2TC_HB2_T3ON_Pos (16UL)
7982 #define BDRV_ONSEQHB2TC_HB2_T3ON_Msk (0x3f0000UL)
7983 #define BDRV_ONSEQHB2TC_HB2_T2ON_Pos (8UL)
7984 #define BDRV_ONSEQHB2TC_HB2_T2ON_Msk (0x3f00UL)
7985 #define BDRV_ONSEQHB2TC_HB2_T1ON_Pos (0UL)
7986 #define BDRV_ONSEQHB2TC_HB2_T1ON_Msk (0xffUL)
7988 #define BDRV_PWMSRCSEL_HS2_SRC_SEL_Pos (19UL)
7989 #define BDRV_PWMSRCSEL_HS2_SRC_SEL_Msk (0x180000UL)
7990 #define BDRV_PWMSRCSEL_HS1_SRC_SEL_Pos (16UL)
7991 #define BDRV_PWMSRCSEL_HS1_SRC_SEL_Msk (0x30000UL)
7992 #define BDRV_PWMSRCSEL_LS2_SRC_SEL_Pos (3UL)
7993 #define BDRV_PWMSRCSEL_LS2_SRC_SEL_Msk (0x18UL)
7994 #define BDRV_PWMSRCSEL_LS1_SRC_SEL_Pos (0UL)
7995 #define BDRV_PWMSRCSEL_LS1_SRC_SEL_Msk (0x3UL)
7997 #define BDRV_SEQAFHB1CD_HB1AF_TDICLMPON_Pos (8UL)
7998 #define BDRV_SEQAFHB1CD_HB1AF_TDICLMPON_Msk (0xff00UL)
7999 #define BDRV_SEQAFHB1CD_HB1AF_TDICLMPOFF_Pos (0UL)
8000 #define BDRV_SEQAFHB1CD_HB1AF_TDICLMPOFF_Msk (0xffUL)
8002 #define BDRV_SEQAFHB1IC_HB1AF_ION_Pos (16UL)
8003 #define BDRV_SEQAFHB1IC_HB1AF_ION_Msk (0x3f0000UL)
8004 #define BDRV_SEQAFHB1IC_HB1AF_IOFF_Pos (0UL)
8005 #define BDRV_SEQAFHB1IC_HB1AF_IOFF_Msk (0x3fUL)
8007 #define BDRV_SEQAFHB2CD_HB2AF_TDICLMPON_Pos (8UL)
8008 #define BDRV_SEQAFHB2CD_HB2AF_TDICLMPON_Msk (0xff00UL)
8009 #define BDRV_SEQAFHB2CD_HB2AF_TDICLMPOFF_Pos (0UL)
8010 #define BDRV_SEQAFHB2CD_HB2AF_TDICLMPOFF_Msk (0xffUL)
8012 #define BDRV_SEQAFHB2IC_HB2AF_ION_Pos (16UL)
8013 #define BDRV_SEQAFHB2IC_HB2AF_ION_Msk (0x3f0000UL)
8014 #define BDRV_SEQAFHB2IC_HB2AF_IOFF_Pos (0UL)
8015 #define BDRV_SEQAFHB2IC_HB2AF_IOFF_Msk (0x3fUL)
8017 #define BDRV_SEQMAP_HB2_SEQMAP_Pos (2UL)
8018 #define BDRV_SEQMAP_HB2_SEQMAP_Msk (0x4UL)
8019 #define BDRV_SEQMAP_HB1_SEQMAP_Pos (0UL)
8020 #define BDRV_SEQMAP_HB1_SEQMAP_Msk (0x1UL)
8022 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Pos (28UL)
8023 #define BDRV_TRIM_DRVx_CPLOW_TFILT_SEL_Msk (0x30000000UL)
8024 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Pos (25UL)
8025 #define BDRV_TRIM_DRVx_HS2DRV_OCSDN_DIS_Msk (0x2000000UL)
8026 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Pos (24UL)
8027 #define BDRV_TRIM_DRVx_HS1DRV_OCSDN_DIS_Msk (0x1000000UL)
8028 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Pos (21UL)
8029 #define BDRV_TRIM_DRVx_HS2DRV_FDISCHG_DIS_Msk (0x200000UL)
8030 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Pos (20UL)
8031 #define BDRV_TRIM_DRVx_HS1DRV_FDISCHG_DIS_Msk (0x100000UL)
8032 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Pos (18UL)
8033 #define BDRV_TRIM_DRVx_HSDRV_DS_TFILT_SEL_Msk (0xc0000UL)
8034 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Pos (15UL)
8035 #define BDRV_TRIM_DRVx_LS2DRV_OCSDN_DIS_Msk (0x8000UL)
8036 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Pos (14UL)
8037 #define BDRV_TRIM_DRVx_LS1DRV_OCSDN_DIS_Msk (0x4000UL)
8038 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Pos (11UL)
8039 #define BDRV_TRIM_DRVx_LS2DRV_FDISCHG_DIS_Msk (0x800UL)
8040 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Pos (10UL)
8041 #define BDRV_TRIM_DRVx_LS1DRV_FDISCHG_DIS_Msk (0x400UL)
8042 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Pos (8UL)
8043 #define BDRV_TRIM_DRVx_LSDRV_DS_TFILT_SEL_Msk (0x300UL)
8044 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Pos (0UL)
8045 #define BDRV_TRIM_DRVx_LS_HS_BT_TFILT_SEL_Msk (0x3UL)
8053 #define CCU6_CC60R_CCV_Pos (0UL)
8054 #define CCU6_CC60R_CCV_Msk (0xffffUL)
8056 #define CCU6_CC60SR_CCS_Pos (0UL)
8057 #define CCU6_CC60SR_CCS_Msk (0xffffUL)
8059 #define CCU6_CC61R_CCV_Pos (0UL)
8060 #define CCU6_CC61R_CCV_Msk (0xffffUL)
8062 #define CCU6_CC61SR_CCS_Pos (0UL)
8063 #define CCU6_CC61SR_CCS_Msk (0xffffUL)
8065 #define CCU6_CC62R_CCV_Pos (0UL)
8066 #define CCU6_CC62R_CCV_Msk (0xffffUL)
8068 #define CCU6_CC62SR_CCS_Pos (0UL)
8069 #define CCU6_CC62SR_CCS_Msk (0xffffUL)
8071 #define CCU6_CC63R_CCV_Pos (0UL)
8072 #define CCU6_CC63R_CCV_Msk (0xffffUL)
8074 #define CCU6_CC63SR_CCS_Pos (0UL)
8075 #define CCU6_CC63SR_CCS_Msk (0xffffUL)
8077 #define CCU6_CMPMODIF_MCC63R_Pos (14UL)
8078 #define CCU6_CMPMODIF_MCC63R_Msk (0x4000UL)
8079 #define CCU6_CMPMODIF_MCC62R_Pos (10UL)
8080 #define CCU6_CMPMODIF_MCC62R_Msk (0x400UL)
8081 #define CCU6_CMPMODIF_MCC61R_Pos (9UL)
8082 #define CCU6_CMPMODIF_MCC61R_Msk (0x200UL)
8083 #define CCU6_CMPMODIF_MCC60R_Pos (8UL)
8084 #define CCU6_CMPMODIF_MCC60R_Msk (0x100UL)
8085 #define CCU6_CMPMODIF_MCC63S_Pos (6UL)
8086 #define CCU6_CMPMODIF_MCC63S_Msk (0x40UL)
8087 #define CCU6_CMPMODIF_MCC62S_Pos (2UL)
8088 #define CCU6_CMPMODIF_MCC62S_Msk (0x4UL)
8089 #define CCU6_CMPMODIF_MCC61S_Pos (1UL)
8090 #define CCU6_CMPMODIF_MCC61S_Msk (0x2UL)
8091 #define CCU6_CMPMODIF_MCC60S_Pos (0UL)
8092 #define CCU6_CMPMODIF_MCC60S_Msk (0x1UL)
8094 #define CCU6_CMPSTAT_T13IM_Pos (15UL)
8095 #define CCU6_CMPSTAT_T13IM_Msk (0x8000UL)
8096 #define CCU6_CMPSTAT_COUT63PS_Pos (14UL)
8097 #define CCU6_CMPSTAT_COUT63PS_Msk (0x4000UL)
8098 #define CCU6_CMPSTAT_COUT62PS_Pos (13UL)
8099 #define CCU6_CMPSTAT_COUT62PS_Msk (0x2000UL)
8100 #define CCU6_CMPSTAT_CC62PS_Pos (12UL)
8101 #define CCU6_CMPSTAT_CC62PS_Msk (0x1000UL)
8102 #define CCU6_CMPSTAT_COUT61PS_Pos (11UL)
8103 #define CCU6_CMPSTAT_COUT61PS_Msk (0x800UL)
8104 #define CCU6_CMPSTAT_CC61PS_Pos (10UL)
8105 #define CCU6_CMPSTAT_CC61PS_Msk (0x400UL)
8106 #define CCU6_CMPSTAT_COUT60PS_Pos (9UL)
8107 #define CCU6_CMPSTAT_COUT60PS_Msk (0x200UL)
8108 #define CCU6_CMPSTAT_CC60PS_Pos (8UL)
8109 #define CCU6_CMPSTAT_CC60PS_Msk (0x100UL)
8110 #define CCU6_CMPSTAT_CC63ST_Pos (6UL)
8111 #define CCU6_CMPSTAT_CC63ST_Msk (0x40UL)
8112 #define CCU6_CMPSTAT_CCPOS2_Pos (5UL)
8113 #define CCU6_CMPSTAT_CCPOS2_Msk (0x20UL)
8114 #define CCU6_CMPSTAT_CCPOS1_Pos (4UL)
8115 #define CCU6_CMPSTAT_CCPOS1_Msk (0x10UL)
8116 #define CCU6_CMPSTAT_CCPOS0_Pos (3UL)
8117 #define CCU6_CMPSTAT_CCPOS0_Msk (0x8UL)
8118 #define CCU6_CMPSTAT_CC62ST_Pos (2UL)
8119 #define CCU6_CMPSTAT_CC62ST_Msk (0x4UL)
8120 #define CCU6_CMPSTAT_CC61ST_Pos (1UL)
8121 #define CCU6_CMPSTAT_CC61ST_Msk (0x2UL)
8122 #define CCU6_CMPSTAT_CC60ST_Pos (0UL)
8123 #define CCU6_CMPSTAT_CC60ST_Msk (0x1UL)
8125 #define CCU6_IEN_ENSTR_Pos (15UL)
8126 #define CCU6_IEN_ENSTR_Msk (0x8000UL)
8127 #define CCU6_IEN_ENIDLE_Pos (14UL)
8128 #define CCU6_IEN_ENIDLE_Msk (0x4000UL)
8129 #define CCU6_IEN_ENWHE_Pos (13UL)
8130 #define CCU6_IEN_ENWHE_Msk (0x2000UL)
8131 #define CCU6_IEN_ENCHE_Pos (12UL)
8132 #define CCU6_IEN_ENCHE_Msk (0x1000UL)
8133 #define CCU6_IEN_ENTRPF_Pos (10UL)
8134 #define CCU6_IEN_ENTRPF_Msk (0x400UL)
8135 #define CCU6_IEN_ENT13PM_Pos (9UL)
8136 #define CCU6_IEN_ENT13PM_Msk (0x200UL)
8137 #define CCU6_IEN_ENT13CM_Pos (8UL)
8138 #define CCU6_IEN_ENT13CM_Msk (0x100UL)
8139 #define CCU6_IEN_ENT12PM_Pos (7UL)
8140 #define CCU6_IEN_ENT12PM_Msk (0x80UL)
8141 #define CCU6_IEN_ENT12OM_Pos (6UL)
8142 #define CCU6_IEN_ENT12OM_Msk (0x40UL)
8143 #define CCU6_IEN_ENCC62F_Pos (5UL)
8144 #define CCU6_IEN_ENCC62F_Msk (0x20UL)
8145 #define CCU6_IEN_ENCC62R_Pos (4UL)
8146 #define CCU6_IEN_ENCC62R_Msk (0x10UL)
8147 #define CCU6_IEN_ENCC61F_Pos (3UL)
8148 #define CCU6_IEN_ENCC61F_Msk (0x8UL)
8149 #define CCU6_IEN_ENCC61R_Pos (2UL)
8150 #define CCU6_IEN_ENCC61R_Msk (0x4UL)
8151 #define CCU6_IEN_ENCC60F_Pos (1UL)
8152 #define CCU6_IEN_ENCC60F_Msk (0x2UL)
8153 #define CCU6_IEN_ENCC60R_Pos (0UL)
8154 #define CCU6_IEN_ENCC60R_Msk (0x1UL)
8156 #define CCU6_INP_INPT13_Pos (12UL)
8157 #define CCU6_INP_INPT13_Msk (0x3000UL)
8158 #define CCU6_INP_INPT12_Pos (10UL)
8159 #define CCU6_INP_INPT12_Msk (0xc00UL)
8160 #define CCU6_INP_INPERR_Pos (8UL)
8161 #define CCU6_INP_INPERR_Msk (0x300UL)
8162 #define CCU6_INP_INPCHE_Pos (6UL)
8163 #define CCU6_INP_INPCHE_Msk (0xc0UL)
8164 #define CCU6_INP_INPCC62_Pos (4UL)
8165 #define CCU6_INP_INPCC62_Msk (0x30UL)
8166 #define CCU6_INP_INPCC61_Pos (2UL)
8167 #define CCU6_INP_INPCC61_Msk (0xcUL)
8168 #define CCU6_INP_INPCC60_Pos (0UL)
8169 #define CCU6_INP_INPCC60_Msk (0x3UL)
8171 #define CCU6_IS_STR_Pos (15UL)
8172 #define CCU6_IS_STR_Msk (0x8000UL)
8173 #define CCU6_IS_IDLE_Pos (14UL)
8174 #define CCU6_IS_IDLE_Msk (0x4000UL)
8175 #define CCU6_IS_WHE_Pos (13UL)
8176 #define CCU6_IS_WHE_Msk (0x2000UL)
8177 #define CCU6_IS_CHE_Pos (12UL)
8178 #define CCU6_IS_CHE_Msk (0x1000UL)
8179 #define CCU6_IS_TRPS_Pos (11UL)
8180 #define CCU6_IS_TRPS_Msk (0x800UL)
8181 #define CCU6_IS_TRPF_Pos (10UL)
8182 #define CCU6_IS_TRPF_Msk (0x400UL)
8183 #define CCU6_IS_T13PM_Pos (9UL)
8184 #define CCU6_IS_T13PM_Msk (0x200UL)
8185 #define CCU6_IS_T13CM_Pos (8UL)
8186 #define CCU6_IS_T13CM_Msk (0x100UL)
8187 #define CCU6_IS_T12PM_Pos (7UL)
8188 #define CCU6_IS_T12PM_Msk (0x80UL)
8189 #define CCU6_IS_T12OM_Pos (6UL)
8190 #define CCU6_IS_T12OM_Msk (0x40UL)
8191 #define CCU6_IS_ICC62F_Pos (5UL)
8192 #define CCU6_IS_ICC62F_Msk (0x20UL)
8193 #define CCU6_IS_ICC62R_Pos (4UL)
8194 #define CCU6_IS_ICC62R_Msk (0x10UL)
8195 #define CCU6_IS_ICC61F_Pos (3UL)
8196 #define CCU6_IS_ICC61F_Msk (0x8UL)
8197 #define CCU6_IS_ICC61R_Pos (2UL)
8198 #define CCU6_IS_ICC61R_Msk (0x4UL)
8199 #define CCU6_IS_ICC60F_Pos (1UL)
8200 #define CCU6_IS_ICC60F_Msk (0x2UL)
8201 #define CCU6_IS_ICC60R_Pos (0UL)
8202 #define CCU6_IS_ICC60R_Msk (0x1UL)
8204 #define CCU6_ISR_RSTR_Pos (15UL)
8205 #define CCU6_ISR_RSTR_Msk (0x8000UL)
8206 #define CCU6_ISR_RIDLE_Pos (14UL)
8207 #define CCU6_ISR_RIDLE_Msk (0x4000UL)
8208 #define CCU6_ISR_RWHE_Pos (13UL)
8209 #define CCU6_ISR_RWHE_Msk (0x2000UL)
8210 #define CCU6_ISR_RCHE_Pos (12UL)
8211 #define CCU6_ISR_RCHE_Msk (0x1000UL)
8212 #define CCU6_ISR_RTRPF_Pos (10UL)
8213 #define CCU6_ISR_RTRPF_Msk (0x400UL)
8214 #define CCU6_ISR_RT13PM_Pos (9UL)
8215 #define CCU6_ISR_RT13PM_Msk (0x200UL)
8216 #define CCU6_ISR_RT13CM_Pos (8UL)
8217 #define CCU6_ISR_RT13CM_Msk (0x100UL)
8218 #define CCU6_ISR_RT12PM_Pos (7UL)
8219 #define CCU6_ISR_RT12PM_Msk (0x80UL)
8220 #define CCU6_ISR_RT12OM_Pos (6UL)
8221 #define CCU6_ISR_RT12OM_Msk (0x40UL)
8222 #define CCU6_ISR_RCC62F_Pos (5UL)
8223 #define CCU6_ISR_RCC62F_Msk (0x20UL)
8224 #define CCU6_ISR_RCC62R_Pos (4UL)
8225 #define CCU6_ISR_RCC62R_Msk (0x10UL)
8226 #define CCU6_ISR_RCC61F_Pos (3UL)
8227 #define CCU6_ISR_RCC61F_Msk (0x8UL)
8228 #define CCU6_ISR_RCC61R_Pos (2UL)
8229 #define CCU6_ISR_RCC61R_Msk (0x4UL)
8230 #define CCU6_ISR_RCC60F_Pos (1UL)
8231 #define CCU6_ISR_RCC60F_Msk (0x2UL)
8232 #define CCU6_ISR_RCC60R_Pos (0UL)
8233 #define CCU6_ISR_RCC60R_Msk (0x1UL)
8235 #define CCU6_ISS_SSTR_Pos (15UL)
8236 #define CCU6_ISS_SSTR_Msk (0x8000UL)
8237 #define CCU6_ISS_SIDLE_Pos (14UL)
8238 #define CCU6_ISS_SIDLE_Msk (0x4000UL)
8239 #define CCU6_ISS_SWHE_Pos (13UL)
8240 #define CCU6_ISS_SWHE_Msk (0x2000UL)
8241 #define CCU6_ISS_SCHE_Pos (12UL)
8242 #define CCU6_ISS_SCHE_Msk (0x1000UL)
8243 #define CCU6_ISS_SWHC_Pos (11UL)
8244 #define CCU6_ISS_SWHC_Msk (0x800UL)
8245 #define CCU6_ISS_STRPF_Pos (10UL)
8246 #define CCU6_ISS_STRPF_Msk (0x400UL)
8247 #define CCU6_ISS_ST13PM_Pos (9UL)
8248 #define CCU6_ISS_ST13PM_Msk (0x200UL)
8249 #define CCU6_ISS_ST13CM_Pos (8UL)
8250 #define CCU6_ISS_ST13CM_Msk (0x100UL)
8251 #define CCU6_ISS_ST12PM_Pos (7UL)
8252 #define CCU6_ISS_ST12PM_Msk (0x80UL)
8253 #define CCU6_ISS_ST12OM_Pos (6UL)
8254 #define CCU6_ISS_ST12OM_Msk (0x40UL)
8255 #define CCU6_ISS_SCC62F_Pos (5UL)
8256 #define CCU6_ISS_SCC62F_Msk (0x20UL)
8257 #define CCU6_ISS_SCC62R_Pos (4UL)
8258 #define CCU6_ISS_SCC62R_Msk (0x10UL)
8259 #define CCU6_ISS_SCC61F_Pos (3UL)
8260 #define CCU6_ISS_SCC61F_Msk (0x8UL)
8261 #define CCU6_ISS_SCC61R_Pos (2UL)
8262 #define CCU6_ISS_SCC61R_Msk (0x4UL)
8263 #define CCU6_ISS_SCC60F_Pos (1UL)
8264 #define CCU6_ISS_SCC60F_Msk (0x2UL)
8265 #define CCU6_ISS_SCC60R_Pos (0UL)
8266 #define CCU6_ISS_SCC60R_Msk (0x1UL)
8268 #define CCU6_MCMCTR_STE13U_Pos (10UL)
8269 #define CCU6_MCMCTR_STE13U_Msk (0x400UL)
8270 #define CCU6_MCMCTR_STE12D_Pos (9UL)
8271 #define CCU6_MCMCTR_STE12D_Msk (0x200UL)
8272 #define CCU6_MCMCTR_STE12U_Pos (8UL)
8273 #define CCU6_MCMCTR_STE12U_Msk (0x100UL)
8274 #define CCU6_MCMCTR_SWSYN_Pos (4UL)
8275 #define CCU6_MCMCTR_SWSYN_Msk (0x30UL)
8276 #define CCU6_MCMCTR_SWSEL_Pos (0UL)
8277 #define CCU6_MCMCTR_SWSEL_Msk (0x7UL)
8279 #define CCU6_MCMOUT_CURH_Pos (11UL)
8280 #define CCU6_MCMOUT_CURH_Msk (0x3800UL)
8281 #define CCU6_MCMOUT_EXPH_Pos (8UL)
8282 #define CCU6_MCMOUT_EXPH_Msk (0x700UL)
8283 #define CCU6_MCMOUT_R_Pos (6UL)
8284 #define CCU6_MCMOUT_R_Msk (0x40UL)
8285 #define CCU6_MCMOUT_MCMP_Pos (0UL)
8286 #define CCU6_MCMOUT_MCMP_Msk (0x3fUL)
8288 #define CCU6_MCMOUTS_STRHP_Pos (15UL)
8289 #define CCU6_MCMOUTS_STRHP_Msk (0x8000UL)
8290 #define CCU6_MCMOUTS_CURHS_Pos (11UL)
8291 #define CCU6_MCMOUTS_CURHS_Msk (0x3800UL)
8292 #define CCU6_MCMOUTS_EXPHS_Pos (8UL)
8293 #define CCU6_MCMOUTS_EXPHS_Msk (0x700UL)
8294 #define CCU6_MCMOUTS_STRMCM_Pos (7UL)
8295 #define CCU6_MCMOUTS_STRMCM_Msk (0x80UL)
8296 #define CCU6_MCMOUTS_MCMPS_Pos (0UL)
8297 #define CCU6_MCMOUTS_MCMPS_Msk (0x3fUL)
8299 #define CCU6_MODCTR_ECT13O_Pos (15UL)
8300 #define CCU6_MODCTR_ECT13O_Msk (0x8000UL)
8301 #define CCU6_MODCTR_T13MODEN_Pos (8UL)
8302 #define CCU6_MODCTR_T13MODEN_Msk (0x3f00UL)
8303 #define CCU6_MODCTR_MCMEN_Pos (7UL)
8304 #define CCU6_MODCTR_MCMEN_Msk (0x80UL)
8305 #define CCU6_MODCTR_T12MODEN_Pos (0UL)
8306 #define CCU6_MODCTR_T12MODEN_Msk (0x3fUL)
8308 #define CCU6_PISEL0_IST12HR_Pos (14UL)
8309 #define CCU6_PISEL0_IST12HR_Msk (0xc000UL)
8310 #define CCU6_PISEL0_ISPOS2_Pos (12UL)
8311 #define CCU6_PISEL0_ISPOS2_Msk (0x3000UL)
8312 #define CCU6_PISEL0_ISPOS1_Pos (10UL)
8313 #define CCU6_PISEL0_ISPOS1_Msk (0xc00UL)
8314 #define CCU6_PISEL0_ISPOS0_Pos (8UL)
8315 #define CCU6_PISEL0_ISPOS0_Msk (0x300UL)
8316 #define CCU6_PISEL0_ISTRP_Pos (6UL)
8317 #define CCU6_PISEL0_ISTRP_Msk (0xc0UL)
8318 #define CCU6_PISEL0_ISCC62_Pos (4UL)
8319 #define CCU6_PISEL0_ISCC62_Msk (0x30UL)
8320 #define CCU6_PISEL0_ISCC61_Pos (2UL)
8321 #define CCU6_PISEL0_ISCC61_Msk (0xcUL)
8322 #define CCU6_PISEL0_ISCC60_Pos (0UL)
8323 #define CCU6_PISEL0_ISCC60_Msk (0x3UL)
8325 #define CCU6_PISEL2_T13EXT_Pos (7UL)
8326 #define CCU6_PISEL2_T13EXT_Msk (0x80UL)
8327 #define CCU6_PISEL2_T12EXT_Pos (6UL)
8328 #define CCU6_PISEL2_T12EXT_Msk (0x40UL)
8329 #define CCU6_PISEL2_ISCNT13_Pos (4UL)
8330 #define CCU6_PISEL2_ISCNT13_Msk (0x30UL)
8331 #define CCU6_PISEL2_ISCNT12_Pos (2UL)
8332 #define CCU6_PISEL2_ISCNT12_Msk (0xcUL)
8333 #define CCU6_PISEL2_IST13HR_Pos (0UL)
8334 #define CCU6_PISEL2_IST13HR_Msk (0x3UL)
8336 #define CCU6_PSLR_PSL63_Pos (7UL)
8337 #define CCU6_PSLR_PSL63_Msk (0x80UL)
8338 #define CCU6_PSLR_PSL_Pos (0UL)
8339 #define CCU6_PSLR_PSL_Msk (0x3fUL)
8341 #define CCU6_T12_T12CV_Pos (0UL)
8342 #define CCU6_T12_T12CV_Msk (0xffffUL)
8344 #define CCU6_T12DTC_DTR2_Pos (14UL)
8345 #define CCU6_T12DTC_DTR2_Msk (0x4000UL)
8346 #define CCU6_T12DTC_DTR1_Pos (13UL)
8347 #define CCU6_T12DTC_DTR1_Msk (0x2000UL)
8348 #define CCU6_T12DTC_DTR0_Pos (12UL)
8349 #define CCU6_T12DTC_DTR0_Msk (0x1000UL)
8350 #define CCU6_T12DTC_DTE2_Pos (10UL)
8351 #define CCU6_T12DTC_DTE2_Msk (0x400UL)
8352 #define CCU6_T12DTC_DTE1_Pos (9UL)
8353 #define CCU6_T12DTC_DTE1_Msk (0x200UL)
8354 #define CCU6_T12DTC_DTE0_Pos (8UL)
8355 #define CCU6_T12DTC_DTE0_Msk (0x100UL)
8356 #define CCU6_T12DTC_DTM_Pos (0UL)
8357 #define CCU6_T12DTC_DTM_Msk (0xffUL)
8359 #define CCU6_T12MSEL_DBYP_Pos (15UL)
8360 #define CCU6_T12MSEL_DBYP_Msk (0x8000UL)
8361 #define CCU6_T12MSEL_HSYNC_Pos (12UL)
8362 #define CCU6_T12MSEL_HSYNC_Msk (0x7000UL)
8363 #define CCU6_T12MSEL_MSEL62_Pos (8UL)
8364 #define CCU6_T12MSEL_MSEL62_Msk (0xf00UL)
8365 #define CCU6_T12MSEL_MSEL61_Pos (4UL)
8366 #define CCU6_T12MSEL_MSEL61_Msk (0xf0UL)
8367 #define CCU6_T12MSEL_MSEL60_Pos (0UL)
8368 #define CCU6_T12MSEL_MSEL60_Msk (0xfUL)
8370 #define CCU6_T12PR_T12PV_Pos (0UL)
8371 #define CCU6_T12PR_T12PV_Msk (0xffffUL)
8373 #define CCU6_T13_T13CV_Pos (0UL)
8374 #define CCU6_T13_T13CV_Msk (0xffffUL)
8376 #define CCU6_T13PR_T13PV_Pos (0UL)
8377 #define CCU6_T13PR_T13PV_Msk (0xffffUL)
8379 #define CCU6_TCTR0_STE13_Pos (13UL)
8380 #define CCU6_TCTR0_STE13_Msk (0x2000UL)
8381 #define CCU6_TCTR0_T13R_Pos (12UL)
8382 #define CCU6_TCTR0_T13R_Msk (0x1000UL)
8383 #define CCU6_TCTR0_T13PRE_Pos (11UL)
8384 #define CCU6_TCTR0_T13PRE_Msk (0x800UL)
8385 #define CCU6_TCTR0_T13CLK_Pos (8UL)
8386 #define CCU6_TCTR0_T13CLK_Msk (0x700UL)
8387 #define CCU6_TCTR0_CTM_Pos (7UL)
8388 #define CCU6_TCTR0_CTM_Msk (0x80UL)
8389 #define CCU6_TCTR0_CDIR_Pos (6UL)
8390 #define CCU6_TCTR0_CDIR_Msk (0x40UL)
8391 #define CCU6_TCTR0_STE12_Pos (5UL)
8392 #define CCU6_TCTR0_STE12_Msk (0x20UL)
8393 #define CCU6_TCTR0_T12R_Pos (4UL)
8394 #define CCU6_TCTR0_T12R_Msk (0x10UL)
8395 #define CCU6_TCTR0_T12PRE_Pos (3UL)
8396 #define CCU6_TCTR0_T12PRE_Msk (0x8UL)
8397 #define CCU6_TCTR0_T12CLK_Pos (0UL)
8398 #define CCU6_TCTR0_T12CLK_Msk (0x7UL)
8400 #define CCU6_TCTR2_T13RSEL_Pos (10UL)
8401 #define CCU6_TCTR2_T13RSEL_Msk (0xc00UL)
8402 #define CCU6_TCTR2_T12RSEL_Pos (8UL)
8403 #define CCU6_TCTR2_T12RSEL_Msk (0x300UL)
8404 #define CCU6_TCTR2_T13TED_Pos (5UL)
8405 #define CCU6_TCTR2_T13TED_Msk (0x60UL)
8406 #define CCU6_TCTR2_T13TEC_Pos (2UL)
8407 #define CCU6_TCTR2_T13TEC_Msk (0x1cUL)
8408 #define CCU6_TCTR2_T13SSC_Pos (1UL)
8409 #define CCU6_TCTR2_T13SSC_Msk (0x2UL)
8410 #define CCU6_TCTR2_T12SSC_Pos (0UL)
8411 #define CCU6_TCTR2_T12SSC_Msk (0x1UL)
8413 #define CCU6_TCTR4_T13STD_Pos (15UL)
8414 #define CCU6_TCTR4_T13STD_Msk (0x8000UL)
8415 #define CCU6_TCTR4_T13STR_Pos (14UL)
8416 #define CCU6_TCTR4_T13STR_Msk (0x4000UL)
8417 #define CCU6_TCTR4_T13CNT_Pos (13UL)
8418 #define CCU6_TCTR4_T13CNT_Msk (0x2000UL)
8419 #define CCU6_TCTR4_T13RES_Pos (10UL)
8420 #define CCU6_TCTR4_T13RES_Msk (0x400UL)
8421 #define CCU6_TCTR4_T13RS_Pos (9UL)
8422 #define CCU6_TCTR4_T13RS_Msk (0x200UL)
8423 #define CCU6_TCTR4_T13RR_Pos (8UL)
8424 #define CCU6_TCTR4_T13RR_Msk (0x100UL)
8425 #define CCU6_TCTR4_T12STD_Pos (7UL)
8426 #define CCU6_TCTR4_T12STD_Msk (0x80UL)
8427 #define CCU6_TCTR4_T12STR_Pos (6UL)
8428 #define CCU6_TCTR4_T12STR_Msk (0x40UL)
8429 #define CCU6_TCTR4_T12CNT_Pos (5UL)
8430 #define CCU6_TCTR4_T12CNT_Msk (0x20UL)
8431 #define CCU6_TCTR4_DTRES_Pos (3UL)
8432 #define CCU6_TCTR4_DTRES_Msk (0x8UL)
8433 #define CCU6_TCTR4_T12RES_Pos (2UL)
8434 #define CCU6_TCTR4_T12RES_Msk (0x4UL)
8435 #define CCU6_TCTR4_T12RS_Pos (1UL)
8436 #define CCU6_TCTR4_T12RS_Msk (0x2UL)
8437 #define CCU6_TCTR4_T12RR_Pos (0UL)
8438 #define CCU6_TCTR4_T12RR_Msk (0x1UL)
8440 #define CCU6_TRPCTR_TRPPEN_Pos (15UL)
8441 #define CCU6_TRPCTR_TRPPEN_Msk (0x8000UL)
8442 #define CCU6_TRPCTR_TRPEN13_Pos (14UL)
8443 #define CCU6_TRPCTR_TRPEN13_Msk (0x4000UL)
8444 #define CCU6_TRPCTR_TRPEN_Pos (8UL)
8445 #define CCU6_TRPCTR_TRPEN_Msk (0x3f00UL)
8446 #define CCU6_TRPCTR_TRPM2_Pos (2UL)
8447 #define CCU6_TRPCTR_TRPM2_Msk (0x4UL)
8448 #define CCU6_TRPCTR_TRPM10_Pos (0UL)
8449 #define CCU6_TRPCTR_TRPM10_Msk (0x3UL)
8457 #define CPU_AIRCR_VECTKEY_Pos (16UL)
8458 #define CPU_AIRCR_VECTKEY_Msk (0xffff0000UL)
8459 #define CPU_AIRCR_ENDIANNESS_Pos (15UL)
8460 #define CPU_AIRCR_ENDIANNESS_Msk (0x8000UL)
8461 #define CPU_AIRCR_SYSRESETREQ_Pos (2UL)
8462 #define CPU_AIRCR_SYSRESETREQ_Msk (0x4UL)
8463 #define CPU_AIRCR_VECTCLRACTIVE_Pos (1UL)
8464 #define CPU_AIRCR_VECTCLRACTIVE_Msk (0x2UL)
8466 #define CPU_CCR_STKALIGN_Pos (9UL)
8467 #define CPU_CCR_STKALIGN_Msk (0x200UL)
8468 #define CPU_CCR_UNALIGN_TRP_Pos (3UL)
8469 #define CPU_CCR_UNALIGN_TRP_Msk (0x8UL)
8471 #define CPU_CPUID_IMPLEMENTER_Pos (24UL)
8472 #define CPU_CPUID_IMPLEMENTER_Msk (0xff000000UL)
8473 #define CPU_CPUID_VARIANT_Pos (20UL)
8474 #define CPU_CPUID_VARIANT_Msk (0xf00000UL)
8475 #define CPU_CPUID_CONSTANT_Pos (16UL)
8476 #define CPU_CPUID_CONSTANT_Msk (0xf0000UL)
8477 #define CPU_CPUID_PARTNO_Pos (4UL)
8478 #define CPU_CPUID_PARTNO_Msk (0xfff0UL)
8479 #define CPU_CPUID_REVISION_Pos (0UL)
8480 #define CPU_CPUID_REVISION_Msk (0xfUL)
8482 #define CPU_ICSR_NMIPENDSET_Pos (31UL)
8483 #define CPU_ICSR_NMIPENDSET_Msk (0x80000000UL)
8484 #define CPU_ICSR_PENDSVSET_Pos (28UL)
8485 #define CPU_ICSR_PENDSVSET_Msk (0x10000000UL)
8486 #define CPU_ICSR_PENDSVCLR_Pos (27UL)
8487 #define CPU_ICSR_PENDSVCLR_Msk (0x8000000UL)
8488 #define CPU_ICSR_PENDSTSET_Pos (26UL)
8489 #define CPU_ICSR_PENDSTSET_Msk (0x4000000UL)
8490 #define CPU_ICSR_PENDSTCLR_Pos (25UL)
8491 #define CPU_ICSR_PENDSTCLR_Msk (0x2000000UL)
8492 #define CPU_ICSR_ISRPENDING_Pos (22UL)
8493 #define CPU_ICSR_ISRPENDING_Msk (0x400000UL)
8494 #define CPU_ICSR_VECTPENDING_Pos (12UL)
8495 #define CPU_ICSR_VECTPENDING_Msk (0x3f000UL)
8496 #define CPU_ICSR_VECTACTIVE_Pos (0UL)
8497 #define CPU_ICSR_VECTACTIVE_Msk (0x3fUL)
8499 #define CPU_NVIC_ICER_Int_PORT2_Pos (23UL)
8500 #define CPU_NVIC_ICER_Int_PORT2_Msk (0x800000UL)
8501 #define CPU_NVIC_ICER_Int_MON_Pos (22UL)
8502 #define CPU_NVIC_ICER_Int_MON_Msk (0x400000UL)
8503 #define CPU_NVIC_ICER_Int_DU_Pos (21UL)
8504 #define CPU_NVIC_ICER_Int_DU_Msk (0x200000UL)
8505 #define CPU_NVIC_ICER_Int_OPA_Pos (20UL)
8506 #define CPU_NVIC_ICER_Int_OPA_Msk (0x100000UL)
8507 #define CPU_NVIC_ICER_Int_HS_Pos (19UL)
8508 #define CPU_NVIC_ICER_Int_HS_Msk (0x80000UL)
8509 #define CPU_NVIC_ICER_Int_BDRV_Pos (18UL)
8510 #define CPU_NVIC_ICER_Int_BDRV_Msk (0x40000UL)
8511 #define CPU_NVIC_ICER_Int_CP_Pos (17UL)
8512 #define CPU_NVIC_ICER_Int_CP_Msk (0x20000UL)
8513 #define CPU_NVIC_ICER_Int_MATHDIV_Pos (15UL)
8514 #define CPU_NVIC_ICER_Int_MATHDIV_Msk (0x8000UL)
8515 #define CPU_NVIC_ICER_Int_WAKEUP_Pos (14UL)
8516 #define CPU_NVIC_ICER_Int_WAKEUP_Msk (0x4000UL)
8517 #define CPU_NVIC_ICER_Int_EXINT1_Pos (13UL)
8518 #define CPU_NVIC_ICER_Int_EXINT1_Msk (0x2000UL)
8519 #define CPU_NVIC_ICER_Int_EXINT0_Pos (12UL)
8520 #define CPU_NVIC_ICER_Int_EXINT0_Msk (0x1000UL)
8521 #define CPU_NVIC_ICER_Int_UART2_Pos (11UL)
8522 #define CPU_NVIC_ICER_Int_UART2_Msk (0x800UL)
8523 #define CPU_NVIC_ICER_Int_UART1_Pos (10UL)
8524 #define CPU_NVIC_ICER_Int_UART1_Msk (0x400UL)
8525 #define CPU_NVIC_ICER_Int_SSC2_Pos (9UL)
8526 #define CPU_NVIC_ICER_Int_SSC2_Msk (0x200UL)
8527 #define CPU_NVIC_ICER_Int_SSC1_Pos (8UL)
8528 #define CPU_NVIC_ICER_Int_SSC1_Msk (0x100UL)
8529 #define CPU_NVIC_ICER_Int_CCU6SR3_Pos (7UL)
8530 #define CPU_NVIC_ICER_Int_CCU6SR3_Msk (0x80UL)
8531 #define CPU_NVIC_ICER_Int_CCU6SR2_Pos (6UL)
8532 #define CPU_NVIC_ICER_Int_CCU6SR2_Msk (0x40UL)
8533 #define CPU_NVIC_ICER_Int_CCU6SR1_Pos (5UL)
8534 #define CPU_NVIC_ICER_Int_CCU6SR1_Msk (0x20UL)
8535 #define CPU_NVIC_ICER_Int_CCU6SR0_Pos (4UL)
8536 #define CPU_NVIC_ICER_Int_CCU6SR0_Msk (0x10UL)
8537 #define CPU_NVIC_ICER_Int_ADC1_Pos (3UL)
8538 #define CPU_NVIC_ICER_Int_ADC1_Msk (0x8UL)
8539 #define CPU_NVIC_ICER_Int_ADC2_Pos (2UL)
8540 #define CPU_NVIC_ICER_Int_ADC2_Msk (0x4UL)
8541 #define CPU_NVIC_ICER_Int_GPT2_Pos (1UL)
8542 #define CPU_NVIC_ICER_Int_GPT2_Msk (0x2UL)
8543 #define CPU_NVIC_ICER_Int_GPT1_Pos (0UL)
8544 #define CPU_NVIC_ICER_Int_GPT1_Msk (0x1UL)
8546 #define CPU_NVIC_ICPR_Int_PORT2_Pos (23UL)
8547 #define CPU_NVIC_ICPR_Int_PORT2_Msk (0x800000UL)
8548 #define CPU_NVIC_ICPR_Int_MON_Pos (22UL)
8549 #define CPU_NVIC_ICPR_Int_MON_Msk (0x400000UL)
8550 #define CPU_NVIC_ICPR_Int_DU_Pos (21UL)
8551 #define CPU_NVIC_ICPR_Int_DU_Msk (0x200000UL)
8552 #define CPU_NVIC_ICPR_Int_OPA_Pos (20UL)
8553 #define CPU_NVIC_ICPR_Int_OPA_Msk (0x100000UL)
8554 #define CPU_NVIC_ICPR_Int_HS_Pos (19UL)
8555 #define CPU_NVIC_ICPR_Int_HS_Msk (0x80000UL)
8556 #define CPU_NVIC_ICPR_Int_BDRV_Pos (18UL)
8557 #define CPU_NVIC_ICPR_Int_BDRV_Msk (0x40000UL)
8558 #define CPU_NVIC_ICPR_Int_CP_Pos (17UL)
8559 #define CPU_NVIC_ICPR_Int_CP_Msk (0x20000UL)
8560 #define CPU_NVIC_ICPR_Int_MATHDIV_Pos (15UL)
8561 #define CPU_NVIC_ICPR_Int_MATHDIV_Msk (0x8000UL)
8562 #define CPU_NVIC_ICPR_Int_WAKEUP_Pos (14UL)
8563 #define CPU_NVIC_ICPR_Int_WAKEUP_Msk (0x4000UL)
8564 #define CPU_NVIC_ICPR_Int_EXINT1_Pos (13UL)
8565 #define CPU_NVIC_ICPR_Int_EXINT1_Msk (0x2000UL)
8566 #define CPU_NVIC_ICPR_Int_EXINT0_Pos (12UL)
8567 #define CPU_NVIC_ICPR_Int_EXINT0_Msk (0x1000UL)
8568 #define CPU_NVIC_ICPR_Int_UART2_Pos (11UL)
8569 #define CPU_NVIC_ICPR_Int_UART2_Msk (0x800UL)
8570 #define CPU_NVIC_ICPR_Int_UART1_Pos (10UL)
8571 #define CPU_NVIC_ICPR_Int_UART1_Msk (0x400UL)
8572 #define CPU_NVIC_ICPR_Int_SSC2_Pos (9UL)
8573 #define CPU_NVIC_ICPR_Int_SSC2_Msk (0x200UL)
8574 #define CPU_NVIC_ICPR_Int_SSC1_Pos (8UL)
8575 #define CPU_NVIC_ICPR_Int_SSC1_Msk (0x100UL)
8576 #define CPU_NVIC_ICPR_Int_CCU6SR3_Pos (7UL)
8577 #define CPU_NVIC_ICPR_Int_CCU6SR3_Msk (0x80UL)
8578 #define CPU_NVIC_ICPR_Int_CCU6SR2_Pos (6UL)
8579 #define CPU_NVIC_ICPR_Int_CCU6SR2_Msk (0x40UL)
8580 #define CPU_NVIC_ICPR_Int_CCU6SR1_Pos (5UL)
8581 #define CPU_NVIC_ICPR_Int_CCU6SR1_Msk (0x20UL)
8582 #define CPU_NVIC_ICPR_Int_CCU6SR0_Pos (4UL)
8583 #define CPU_NVIC_ICPR_Int_CCU6SR0_Msk (0x10UL)
8584 #define CPU_NVIC_ICPR_Int_ADC1_Pos (3UL)
8585 #define CPU_NVIC_ICPR_Int_ADC1_Msk (0x8UL)
8586 #define CPU_NVIC_ICPR_Int_ADC2_Pos (2UL)
8587 #define CPU_NVIC_ICPR_Int_ADC2_Msk (0x4UL)
8588 #define CPU_NVIC_ICPR_Int_GPT2_Pos (1UL)
8589 #define CPU_NVIC_ICPR_Int_GPT2_Msk (0x2UL)
8590 #define CPU_NVIC_ICPR_Int_GPT1_Pos (0UL)
8591 #define CPU_NVIC_ICPR_Int_GPT1_Msk (0x1UL)
8593 #define CPU_NVIC_IPR0_PRI_ADC1_Pos (30UL)
8594 #define CPU_NVIC_IPR0_PRI_ADC1_Msk (0xc0000000UL)
8595 #define CPU_NVIC_IPR0_PRI_ADC2_Pos (22UL)
8596 #define CPU_NVIC_IPR0_PRI_ADC2_Msk (0xc00000UL)
8597 #define CPU_NVIC_IPR0_PRI_GPT2_Pos (14UL)
8598 #define CPU_NVIC_IPR0_PRI_GPT2_Msk (0xc000UL)
8599 #define CPU_NVIC_IPR0_PRI_GPT1_Pos (6UL)
8600 #define CPU_NVIC_IPR0_PRI_GPT1_Msk (0xc0UL)
8602 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Pos (30UL)
8603 #define CPU_NVIC_IPR1_PRI_CCU6SR3_Msk (0xc0000000UL)
8604 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Pos (22UL)
8605 #define CPU_NVIC_IPR1_PRI_CCU6SR2_Msk (0xc00000UL)
8606 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Pos (14UL)
8607 #define CPU_NVIC_IPR1_PRI_CCU6SR1_Msk (0xc000UL)
8608 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Pos (6UL)
8609 #define CPU_NVIC_IPR1_PRI_CCU6SR0_Msk (0xc0UL)
8611 #define CPU_NVIC_IPR2_PRI_UART2_Pos (30UL)
8612 #define CPU_NVIC_IPR2_PRI_UART2_Msk (0xc0000000UL)
8613 #define CPU_NVIC_IPR2_PRI_UART1_Pos (22UL)
8614 #define CPU_NVIC_IPR2_PRI_UART1_Msk (0xc00000UL)
8615 #define CPU_NVIC_IPR2_PRI_SSC2_Pos (14UL)
8616 #define CPU_NVIC_IPR2_PRI_SSC2_Msk (0xc000UL)
8617 #define CPU_NVIC_IPR2_PRI_SSC1_Pos (6UL)
8618 #define CPU_NVIC_IPR2_PRI_SSC1_Msk (0xc0UL)
8620 #define CPU_NVIC_IPR3_PRI_MATHDIV_Pos (30UL)
8621 #define CPU_NVIC_IPR3_PRI_MATHDIV_Msk (0xc0000000UL)
8622 #define CPU_NVIC_IPR3_PRI_WAKEUP_Pos (22UL)
8623 #define CPU_NVIC_IPR3_PRI_WAKEUP_Msk (0xc00000UL)
8624 #define CPU_NVIC_IPR3_PRI_EXINT1_Pos (14UL)
8625 #define CPU_NVIC_IPR3_PRI_EXINT1_Msk (0xc000UL)
8626 #define CPU_NVIC_IPR3_PRI_EXINT0_Pos (6UL)
8627 #define CPU_NVIC_IPR3_PRI_EXINT0_Msk (0xc0UL)
8629 #define CPU_NVIC_IPR4_PRI_HS_Pos (30UL)
8630 #define CPU_NVIC_IPR4_PRI_HS_Msk (0xc0000000UL)
8631 #define CPU_NVIC_IPR4_PRI_BDRV_Pos (22UL)
8632 #define CPU_NVIC_IPR4_PRI_BDRV_Msk (0xc00000UL)
8633 #define CPU_NVIC_IPR4_PRI_CP_Pos (14UL)
8634 #define CPU_NVIC_IPR4_PRI_CP_Msk (0xc000UL)
8636 #define CPU_NVIC_IPR5_PRI_PORT2_Pos (30UL)
8637 #define CPU_NVIC_IPR5_PRI_PORT2_Msk (0xc0000000UL)
8638 #define CPU_NVIC_IPR5_PRI_MON_Pos (22UL)
8639 #define CPU_NVIC_IPR5_PRI_MON_Msk (0xc00000UL)
8640 #define CPU_NVIC_IPR5_PRI_DU_Pos (14UL)
8641 #define CPU_NVIC_IPR5_PRI_DU_Msk (0xc000UL)
8642 #define CPU_NVIC_IPR5_PRI_OPA_Pos (6UL)
8643 #define CPU_NVIC_IPR5_PRI_OPA_Msk (0xc0UL)
8645 #define CPU_NVIC_ISER_Int_PORT2_Pos (23UL)
8646 #define CPU_NVIC_ISER_Int_PORT2_Msk (0x800000UL)
8647 #define CPU_NVIC_ISER_Int_MON_Pos (22UL)
8648 #define CPU_NVIC_ISER_Int_MON_Msk (0x400000UL)
8649 #define CPU_NVIC_ISER_Int_DU_Pos (21UL)
8650 #define CPU_NVIC_ISER_Int_DU_Msk (0x200000UL)
8651 #define CPU_NVIC_ISER_Int_OPA_Pos (20UL)
8652 #define CPU_NVIC_ISER_Int_OPA_Msk (0x100000UL)
8653 #define CPU_NVIC_ISER_Int_HS_Pos (19UL)
8654 #define CPU_NVIC_ISER_Int_HS_Msk (0x80000UL)
8655 #define CPU_NVIC_ISER_Int_BDRV_Pos (18UL)
8656 #define CPU_NVIC_ISER_Int_BDRV_Msk (0x40000UL)
8657 #define CPU_NVIC_ISER_Int_CP_Pos (17UL)
8658 #define CPU_NVIC_ISER_Int_CP_Msk (0x20000UL)
8659 #define CPU_NVIC_ISER_Int_MATHDIV_Pos (15UL)
8660 #define CPU_NVIC_ISER_Int_MATHDIV_Msk (0x8000UL)
8661 #define CPU_NVIC_ISER_Int_WAKEUP_Pos (14UL)
8662 #define CPU_NVIC_ISER_Int_WAKEUP_Msk (0x4000UL)
8663 #define CPU_NVIC_ISER_Int_EXINT1_Pos (13UL)
8664 #define CPU_NVIC_ISER_Int_EXINT1_Msk (0x2000UL)
8665 #define CPU_NVIC_ISER_Int_EXINT0_Pos (12UL)
8666 #define CPU_NVIC_ISER_Int_EXINT0_Msk (0x1000UL)
8667 #define CPU_NVIC_ISER_Int_UART2_Pos (11UL)
8668 #define CPU_NVIC_ISER_Int_UART2_Msk (0x800UL)
8669 #define CPU_NVIC_ISER_Int_UART1_Pos (10UL)
8670 #define CPU_NVIC_ISER_Int_UART1_Msk (0x400UL)
8671 #define CPU_NVIC_ISER_Int_SSC2_Pos (9UL)
8672 #define CPU_NVIC_ISER_Int_SSC2_Msk (0x200UL)
8673 #define CPU_NVIC_ISER_Int_SSC1_Pos (8UL)
8674 #define CPU_NVIC_ISER_Int_SSC1_Msk (0x100UL)
8675 #define CPU_NVIC_ISER_Int_CCU6SR3_Pos (7UL)
8676 #define CPU_NVIC_ISER_Int_CCU6SR3_Msk (0x80UL)
8677 #define CPU_NVIC_ISER_Int_CCU6SR2_Pos (6UL)
8678 #define CPU_NVIC_ISER_Int_CCU6SR2_Msk (0x40UL)
8679 #define CPU_NVIC_ISER_Int_CCU6SR1_Pos (5UL)
8680 #define CPU_NVIC_ISER_Int_CCU6SR1_Msk (0x20UL)
8681 #define CPU_NVIC_ISER_Int_CCU6SR0_Pos (4UL)
8682 #define CPU_NVIC_ISER_Int_CCU6SR0_Msk (0x10UL)
8683 #define CPU_NVIC_ISER_Int_ADC1_Pos (3UL)
8684 #define CPU_NVIC_ISER_Int_ADC1_Msk (0x8UL)
8685 #define CPU_NVIC_ISER_Int_ADC2_Pos (2UL)
8686 #define CPU_NVIC_ISER_Int_ADC2_Msk (0x4UL)
8687 #define CPU_NVIC_ISER_Int_GPT2_Pos (1UL)
8688 #define CPU_NVIC_ISER_Int_GPT2_Msk (0x2UL)
8689 #define CPU_NVIC_ISER_Int_GPT1_Pos (0UL)
8690 #define CPU_NVIC_ISER_Int_GPT1_Msk (0x1UL)
8692 #define CPU_NVIC_ISPR_Int_PORT2_Pos (23UL)
8693 #define CPU_NVIC_ISPR_Int_PORT2_Msk (0x800000UL)
8694 #define CPU_NVIC_ISPR_Int_MON_Pos (22UL)
8695 #define CPU_NVIC_ISPR_Int_MON_Msk (0x400000UL)
8696 #define CPU_NVIC_ISPR_Int_DU_Pos (21UL)
8697 #define CPU_NVIC_ISPR_Int_DU_Msk (0x200000UL)
8698 #define CPU_NVIC_ISPR_Int_OPA_Pos (20UL)
8699 #define CPU_NVIC_ISPR_Int_OPA_Msk (0x100000UL)
8700 #define CPU_NVIC_ISPR_Int_HS_Pos (19UL)
8701 #define CPU_NVIC_ISPR_Int_HS_Msk (0x80000UL)
8702 #define CPU_NVIC_ISPR_Int_BDRV_Pos (18UL)
8703 #define CPU_NVIC_ISPR_Int_BDRV_Msk (0x40000UL)
8704 #define CPU_NVIC_ISPR_Int_CP_Pos (17UL)
8705 #define CPU_NVIC_ISPR_Int_CP_Msk (0x20000UL)
8706 #define CPU_NVIC_ISPR_Int_MATHDIV_Pos (15UL)
8707 #define CPU_NVIC_ISPR_Int_MATHDIV_Msk (0x8000UL)
8708 #define CPU_NVIC_ISPR_Int_WAKEUP_Pos (14UL)
8709 #define CPU_NVIC_ISPR_Int_WAKEUP_Msk (0x4000UL)
8710 #define CPU_NVIC_ISPR_Int_EXINT1_Pos (13UL)
8711 #define CPU_NVIC_ISPR_Int_EXINT1_Msk (0x2000UL)
8712 #define CPU_NVIC_ISPR_Int_EXINT0_Pos (12UL)
8713 #define CPU_NVIC_ISPR_Int_EXINT0_Msk (0x1000UL)
8714 #define CPU_NVIC_ISPR_Int_UART2_Pos (11UL)
8715 #define CPU_NVIC_ISPR_Int_UART2_Msk (0x800UL)
8716 #define CPU_NVIC_ISPR_Int_UART1_Pos (10UL)
8717 #define CPU_NVIC_ISPR_Int_UART1_Msk (0x400UL)
8718 #define CPU_NVIC_ISPR_Int_SSC2_Pos (9UL)
8719 #define CPU_NVIC_ISPR_Int_SSC2_Msk (0x200UL)
8720 #define CPU_NVIC_ISPR_Int_SSC1_Pos (8UL)
8721 #define CPU_NVIC_ISPR_Int_SSC1_Msk (0x100UL)
8722 #define CPU_NVIC_ISPR_Int_CCU6SR3_Pos (7UL)
8723 #define CPU_NVIC_ISPR_Int_CCU6SR3_Msk (0x80UL)
8724 #define CPU_NVIC_ISPR_Int_CCU6SR2_Pos (6UL)
8725 #define CPU_NVIC_ISPR_Int_CCU6SR2_Msk (0x40UL)
8726 #define CPU_NVIC_ISPR_Int_CCU6SR1_Pos (5UL)
8727 #define CPU_NVIC_ISPR_Int_CCU6SR1_Msk (0x20UL)
8728 #define CPU_NVIC_ISPR_Int_CCU6SR0_Pos (4UL)
8729 #define CPU_NVIC_ISPR_Int_CCU6SR0_Msk (0x10UL)
8730 #define CPU_NVIC_ISPR_Int_ADC1_Pos (3UL)
8731 #define CPU_NVIC_ISPR_Int_ADC1_Msk (0x8UL)
8732 #define CPU_NVIC_ISPR_Int_ADC2_Pos (2UL)
8733 #define CPU_NVIC_ISPR_Int_ADC2_Msk (0x4UL)
8734 #define CPU_NVIC_ISPR_Int_GPT2_Pos (1UL)
8735 #define CPU_NVIC_ISPR_Int_GPT2_Msk (0x2UL)
8736 #define CPU_NVIC_ISPR_Int_GPT1_Pos (0UL)
8737 #define CPU_NVIC_ISPR_Int_GPT1_Msk (0x1UL)
8739 #define CPU_SCR_SEVONPEND_Pos (4UL)
8740 #define CPU_SCR_SEVONPEND_Msk (0x10UL)
8741 #define CPU_SCR_SLEEPDEEP_Pos (2UL)
8742 #define CPU_SCR_SLEEPDEEP_Msk (0x4UL)
8743 #define CPU_SCR_SLEEPONEXIT_Pos (1UL)
8744 #define CPU_SCR_SLEEPONEXIT_Msk (0x2UL)
8746 #define CPU_SHCSR_SVCALLPENDED_Pos (15UL)
8747 #define CPU_SHCSR_SVCALLPENDED_Msk (0x8000UL)
8749 #define CPU_SHPR2_PRI_11_Pos (30UL)
8750 #define CPU_SHPR2_PRI_11_Msk (0xc0000000UL)
8752 #define CPU_SHPR3_PRI_15_Pos (30UL)
8753 #define CPU_SHPR3_PRI_15_Msk (0xc0000000UL)
8754 #define CPU_SHPR3_PRI_14_Pos (22UL)
8755 #define CPU_SHPR3_PRI_14_Msk (0xc00000UL)
8757 #define CPU_SYSTICK_CALIB_NOREF_Pos (31UL)
8758 #define CPU_SYSTICK_CALIB_NOREF_Msk (0x80000000UL)
8759 #define CPU_SYSTICK_CALIB_SKEW_Pos (30UL)
8760 #define CPU_SYSTICK_CALIB_SKEW_Msk (0x40000000UL)
8761 #define CPU_SYSTICK_CALIB_TENMS_Pos (0UL)
8762 #define CPU_SYSTICK_CALIB_TENMS_Msk (0xffffffUL)
8764 #define CPU_SYSTICK_CSR_COUNTFLAG_Pos (16UL)
8765 #define CPU_SYSTICK_CSR_COUNTFLAG_Msk (0x10000UL)
8766 #define CPU_SYSTICK_CSR_CLKSOURCE_Pos (2UL)
8767 #define CPU_SYSTICK_CSR_CLKSOURCE_Msk (0x4UL)
8768 #define CPU_SYSTICK_CSR_TICKINT_Pos (1UL)
8769 #define CPU_SYSTICK_CSR_TICKINT_Msk (0x2UL)
8770 #define CPU_SYSTICK_CSR_ENABLE_Pos (0UL)
8771 #define CPU_SYSTICK_CSR_ENABLE_Msk (0x1UL)
8773 #define CPU_SYSTICK_CVR_CURRENT_Pos (0UL)
8774 #define CPU_SYSTICK_CVR_CURRENT_Msk (0xffffffUL)
8776 #define CPU_SYSTICK_RVR_RELOAD_Pos (0UL)
8777 #define CPU_SYSTICK_RVR_RELOAD_Msk (0xffffffUL)
8785 #define GPT12E_CAPREL_CAPREL_Pos (0UL)
8786 #define GPT12E_CAPREL_CAPREL_Msk (0xffffUL)
8788 #define GPT12E_ID_MOD_TYPE_Pos (8UL)
8789 #define GPT12E_ID_MOD_TYPE_Msk (0xff00UL)
8790 #define GPT12E_ID_MOD_REV_Pos (0UL)
8791 #define GPT12E_ID_MOD_REV_Msk (0xffUL)
8793 #define GPT12E_PISEL_ISCAPIN_Pos (14UL)
8794 #define GPT12E_PISEL_ISCAPIN_Msk (0xc000UL)
8795 #define GPT12E_PISEL_IST6EUD_Pos (13UL)
8796 #define GPT12E_PISEL_IST6EUD_Msk (0x2000UL)
8797 #define GPT12E_PISEL_IST6IN_Pos (12UL)
8798 #define GPT12E_PISEL_IST6IN_Msk (0x1000UL)
8799 #define GPT12E_PISEL_IST5EUD_Pos (11UL)
8800 #define GPT12E_PISEL_IST5EUD_Msk (0x800UL)
8801 #define GPT12E_PISEL_IST5IN_Pos (10UL)
8802 #define GPT12E_PISEL_IST5IN_Msk (0x400UL)
8803 #define GPT12E_PISEL_IST4EUD_Pos (8UL)
8804 #define GPT12E_PISEL_IST4EUD_Msk (0x300UL)
8805 #define GPT12E_PISEL_IST4IN_Pos (6UL)
8806 #define GPT12E_PISEL_IST4IN_Msk (0xc0UL)
8807 #define GPT12E_PISEL_IST3EUD_Pos (4UL)
8808 #define GPT12E_PISEL_IST3EUD_Msk (0x30UL)
8809 #define GPT12E_PISEL_IST3IN_Pos (2UL)
8810 #define GPT12E_PISEL_IST3IN_Msk (0xcUL)
8811 #define GPT12E_PISEL_IST2EUD_Pos (1UL)
8812 #define GPT12E_PISEL_IST2EUD_Msk (0x2UL)
8813 #define GPT12E_PISEL_IST2IN_Pos (0UL)
8814 #define GPT12E_PISEL_IST2IN_Msk (0x1UL)
8816 #define GPT12E_T2_T2_Pos (0UL)
8817 #define GPT12E_T2_T2_Msk (0xffffUL)
8819 #define GPT12E_T2CON_T2DIR_Pos (15UL)
8820 #define GPT12E_T2CON_T2DIR_Msk (0x8000UL)
8821 #define GPT12E_T2CON_T2CHDIR_Pos (14UL)
8822 #define GPT12E_T2CON_T2CHDIR_Msk (0x4000UL)
8823 #define GPT12E_T2CON_T2EDGE_Pos (13UL)
8824 #define GPT12E_T2CON_T2EDGE_Msk (0x2000UL)
8825 #define GPT12E_T2CON_T2IRIDIS_Pos (12UL)
8826 #define GPT12E_T2CON_T2IRIDIS_Msk (0x1000UL)
8827 #define GPT12E_T2CON_T2RC_Pos (9UL)
8828 #define GPT12E_T2CON_T2RC_Msk (0x200UL)
8829 #define GPT12E_T2CON_T2UDE_Pos (8UL)
8830 #define GPT12E_T2CON_T2UDE_Msk (0x100UL)
8831 #define GPT12E_T2CON_T2UD_Pos (7UL)
8832 #define GPT12E_T2CON_T2UD_Msk (0x80UL)
8833 #define GPT12E_T2CON_T2R_Pos (6UL)
8834 #define GPT12E_T2CON_T2R_Msk (0x40UL)
8835 #define GPT12E_T2CON_T2M_Pos (3UL)
8836 #define GPT12E_T2CON_T2M_Msk (0x38UL)
8837 #define GPT12E_T2CON_T2I_Pos (0UL)
8838 #define GPT12E_T2CON_T2I_Msk (0x7UL)
8840 #define GPT12E_T3_T3_Pos (0UL)
8841 #define GPT12E_T3_T3_Msk (0xffffUL)
8843 #define GPT12E_T3CON_T3DIR_Pos (15UL)
8844 #define GPT12E_T3CON_T3DIR_Msk (0x8000UL)
8845 #define GPT12E_T3CON_T3CHDIR_Pos (14UL)
8846 #define GPT12E_T3CON_T3CHDIR_Msk (0x4000UL)
8847 #define GPT12E_T3CON_T3EDGE_Pos (13UL)
8848 #define GPT12E_T3CON_T3EDGE_Msk (0x2000UL)
8849 #define GPT12E_T3CON_BPS1_Pos (11UL)
8850 #define GPT12E_T3CON_BPS1_Msk (0x1800UL)
8851 #define GPT12E_T3CON_T3OTL_Pos (10UL)
8852 #define GPT12E_T3CON_T3OTL_Msk (0x400UL)
8853 #define GPT12E_T3CON_T3OE_Pos (9UL)
8854 #define GPT12E_T3CON_T3OE_Msk (0x200UL)
8855 #define GPT12E_T3CON_T3UDE_Pos (8UL)
8856 #define GPT12E_T3CON_T3UDE_Msk (0x100UL)
8857 #define GPT12E_T3CON_T3UD_Pos (7UL)
8858 #define GPT12E_T3CON_T3UD_Msk (0x80UL)
8859 #define GPT12E_T3CON_T3R_Pos (6UL)
8860 #define GPT12E_T3CON_T3R_Msk (0x40UL)
8861 #define GPT12E_T3CON_T3M_Pos (3UL)
8862 #define GPT12E_T3CON_T3M_Msk (0x38UL)
8863 #define GPT12E_T3CON_T3I_Pos (0UL)
8864 #define GPT12E_T3CON_T3I_Msk (0x7UL)
8866 #define GPT12E_T4_T4_Pos (0UL)
8867 #define GPT12E_T4_T4_Msk (0xffffUL)
8869 #define GPT12E_T4CON_T4RDIR_Pos (15UL)
8870 #define GPT12E_T4CON_T4RDIR_Msk (0x8000UL)
8871 #define GPT12E_T4CON_T4CHDIR_Pos (14UL)
8872 #define GPT12E_T4CON_T4CHDIR_Msk (0x4000UL)
8873 #define GPT12E_T4CON_T4EDGE_Pos (13UL)
8874 #define GPT12E_T4CON_T4EDGE_Msk (0x2000UL)
8875 #define GPT12E_T4CON_T4IRDIS_Pos (12UL)
8876 #define GPT12E_T4CON_T4IRDIS_Msk (0x1000UL)
8877 #define GPT12E_T4CON_CLRT3EN_Pos (11UL)
8878 #define GPT12E_T4CON_CLRT3EN_Msk (0x800UL)
8879 #define GPT12E_T4CON_CLRT2EN_Pos (10UL)
8880 #define GPT12E_T4CON_CLRT2EN_Msk (0x400UL)
8881 #define GPT12E_T4CON_T4RC_Pos (9UL)
8882 #define GPT12E_T4CON_T4RC_Msk (0x200UL)
8883 #define GPT12E_T4CON_T4UDE_Pos (8UL)
8884 #define GPT12E_T4CON_T4UDE_Msk (0x100UL)
8885 #define GPT12E_T4CON_T4UD_Pos (7UL)
8886 #define GPT12E_T4CON_T4UD_Msk (0x80UL)
8887 #define GPT12E_T4CON_T4R_Pos (6UL)
8888 #define GPT12E_T4CON_T4R_Msk (0x40UL)
8889 #define GPT12E_T4CON_T4M_Pos (3UL)
8890 #define GPT12E_T4CON_T4M_Msk (0x38UL)
8891 #define GPT12E_T4CON_T4I_Pos (0UL)
8892 #define GPT12E_T4CON_T4I_Msk (0x7UL)
8894 #define GPT12E_T5_T5_Pos (0UL)
8895 #define GPT12E_T5_T5_Msk (0xffffUL)
8897 #define GPT12E_T5CON_T5SC_Pos (15UL)
8898 #define GPT12E_T5CON_T5SC_Msk (0x8000UL)
8899 #define GPT12E_T5CON_T5CLR_Pos (14UL)
8900 #define GPT12E_T5CON_T5CLR_Msk (0x4000UL)
8901 #define GPT12E_T5CON_CI_Pos (12UL)
8902 #define GPT12E_T5CON_CI_Msk (0x3000UL)
8903 #define GPT12E_T5CON_CT3_Pos (10UL)
8904 #define GPT12E_T5CON_CT3_Msk (0x400UL)
8905 #define GPT12E_T5CON_T5RC_Pos (9UL)
8906 #define GPT12E_T5CON_T5RC_Msk (0x200UL)
8907 #define GPT12E_T5CON_T5UDE_Pos (8UL)
8908 #define GPT12E_T5CON_T5UDE_Msk (0x100UL)
8909 #define GPT12E_T5CON_T5UD_Pos (7UL)
8910 #define GPT12E_T5CON_T5UD_Msk (0x80UL)
8911 #define GPT12E_T5CON_T5R_Pos (6UL)
8912 #define GPT12E_T5CON_T5R_Msk (0x40UL)
8913 #define GPT12E_T5CON_T5M_Pos (3UL)
8914 #define GPT12E_T5CON_T5M_Msk (0x18UL)
8915 #define GPT12E_T5CON_T5I_Pos (0UL)
8916 #define GPT12E_T5CON_T5I_Msk (0x7UL)
8918 #define GPT12E_T6_T6_Pos (0UL)
8919 #define GPT12E_T6_T6_Msk (0xffffUL)
8921 #define GPT12E_T6CON_T6SR_Pos (15UL)
8922 #define GPT12E_T6CON_T6SR_Msk (0x8000UL)
8923 #define GPT12E_T6CON_T6CLR_Pos (14UL)
8924 #define GPT12E_T6CON_T6CLR_Msk (0x4000UL)
8925 #define GPT12E_T6CON_BPS2_Pos (11UL)
8926 #define GPT12E_T6CON_BPS2_Msk (0x1800UL)
8927 #define GPT12E_T6CON_T6OTL_Pos (10UL)
8928 #define GPT12E_T6CON_T6OTL_Msk (0x400UL)
8929 #define GPT12E_T6CON_T6OE_Pos (9UL)
8930 #define GPT12E_T6CON_T6OE_Msk (0x200UL)
8931 #define GPT12E_T6CON_T6UDE_Pos (8UL)
8932 #define GPT12E_T6CON_T6UDE_Msk (0x100UL)
8933 #define GPT12E_T6CON_T6UD_Pos (7UL)
8934 #define GPT12E_T6CON_T6UD_Msk (0x80UL)
8935 #define GPT12E_T6CON_T6R_Pos (6UL)
8936 #define GPT12E_T6CON_T6R_Msk (0x40UL)
8937 #define GPT12E_T6CON_T6M_Pos (3UL)
8938 #define GPT12E_T6CON_T6M_Msk (0x38UL)
8939 #define GPT12E_T6CON_T6I_Pos (0UL)
8940 #define GPT12E_T6CON_T6I_Msk (0x7UL)
8948 #define HS_CTRL_HS1_OC_SEL_Pos (12UL)
8949 #define HS_CTRL_HS1_OC_SEL_Msk (0x3000UL)
8950 #define HS_CTRL_HS1_SR_CTRL_SEL_Pos (8UL)
8951 #define HS_CTRL_HS1_SR_CTRL_SEL_Msk (0x300UL)
8952 #define HS_CTRL_HS1_OL_EN_Pos (3UL)
8953 #define HS_CTRL_HS1_OL_EN_Msk (0x8UL)
8954 #define HS_CTRL_HS1_ON_Pos (2UL)
8955 #define HS_CTRL_HS1_ON_Msk (0x4UL)
8956 #define HS_CTRL_HS1_PWM_Pos (1UL)
8957 #define HS_CTRL_HS1_PWM_Msk (0x2UL)
8958 #define HS_CTRL_HS1_EN_Pos (0UL)
8959 #define HS_CTRL_HS1_EN_Msk (0x1UL)
8961 #define HS_IRQCLR_HS1_OL_SC_Pos (14UL)
8962 #define HS_IRQCLR_HS1_OL_SC_Msk (0x4000UL)
8963 #define HS_IRQCLR_HS1_OT_SC_Pos (13UL)
8964 #define HS_IRQCLR_HS1_OT_SC_Msk (0x2000UL)
8965 #define HS_IRQCLR_HS1_OC_ISC_Pos (7UL)
8966 #define HS_IRQCLR_HS1_OC_ISC_Msk (0x80UL)
8967 #define HS_IRQCLR_HS1_OL_ISC_Pos (6UL)
8968 #define HS_IRQCLR_HS1_OL_ISC_Msk (0x40UL)
8969 #define HS_IRQCLR_HS1_OT_ISC_Pos (5UL)
8970 #define HS_IRQCLR_HS1_OT_ISC_Msk (0x20UL)
8972 #define HS_IRQEN_HS1_OC_IEN_Pos (7UL)
8973 #define HS_IRQEN_HS1_OC_IEN_Msk (0x80UL)
8974 #define HS_IRQEN_HS1_OL_IEN_Pos (6UL)
8975 #define HS_IRQEN_HS1_OL_IEN_Msk (0x40UL)
8976 #define HS_IRQEN_HS1_OT_IEN_Pos (5UL)
8977 #define HS_IRQEN_HS1_OT_IEN_Msk (0x20UL)
8979 #define HS_IRQS_HS1_OL_STS_Pos (14UL)
8980 #define HS_IRQS_HS1_OL_STS_Msk (0x4000UL)
8981 #define HS_IRQS_HS1_OT_STS_Pos (13UL)
8982 #define HS_IRQS_HS1_OT_STS_Msk (0x2000UL)
8983 #define HS_IRQS_HS1_OC_IS_Pos (7UL)
8984 #define HS_IRQS_HS1_OC_IS_Msk (0x80UL)
8985 #define HS_IRQS_HS1_OL_IS_Pos (6UL)
8986 #define HS_IRQS_HS1_OL_IS_Msk (0x40UL)
8987 #define HS_IRQS_HS1_OT_IS_Pos (5UL)
8988 #define HS_IRQS_HS1_OT_IS_Msk (0x20UL)
8990 #define HS_PWMSRCSEL_HS1_SRC_SEL_Pos (3UL)
8991 #define HS_PWMSRCSEL_HS1_SRC_SEL_Msk (0x38UL)
8993 #define HS_TRIM_HS1_OC_OT_BTFILT_SEL_Pos (8UL)
8994 #define HS_TRIM_HS1_OC_OT_BTFILT_SEL_Msk (0x300UL)
8995 #define HS_TRIM_HS1_OL_BTFILT_SEL_Pos (0UL)
8996 #define HS_TRIM_HS1_OL_BTFILT_SEL_Msk (0x3UL)
9004 #define LIN_CTRL_HV_MODE_Pos (21UL)
9005 #define LIN_CTRL_HV_MODE_Msk (0x200000UL)
9006 #define LIN_CTRL_FB_SM3_Pos (15UL)
9007 #define LIN_CTRL_FB_SM3_Msk (0x8000UL)
9008 #define LIN_CTRL_FB_SM2_Pos (14UL)
9009 #define LIN_CTRL_FB_SM2_Msk (0x4000UL)
9010 #define LIN_CTRL_FB_SM1_Pos (13UL)
9011 #define LIN_CTRL_FB_SM1_Msk (0x2000UL)
9012 #define LIN_CTRL_SM_Pos (11UL)
9013 #define LIN_CTRL_SM_Msk (0x1800UL)
9014 #define LIN_CTRL_RXD_Pos (10UL)
9015 #define LIN_CTRL_RXD_Msk (0x400UL)
9016 #define LIN_CTRL_TXD_Pos (9UL)
9017 #define LIN_CTRL_TXD_Msk (0x200UL)
9018 #define LIN_CTRL_MODE_FB_Pos (4UL)
9019 #define LIN_CTRL_MODE_FB_Msk (0x70UL)
9020 #define LIN_CTRL_MODE_Pos (1UL)
9021 #define LIN_CTRL_MODE_Msk (0x6UL)
9022 #define LIN_CTRL_EN_Pos (0UL)
9023 #define LIN_CTRL_EN_Msk (0x1UL)
9025 #define LIN_IRQCLR_TXD_TMOUT_SC_Pos (11UL)
9026 #define LIN_IRQCLR_TXD_TMOUT_SC_Msk (0x800UL)
9027 #define LIN_IRQCLR_OT_SC_Pos (9UL)
9028 #define LIN_IRQCLR_OT_SC_Msk (0x200UL)
9029 #define LIN_IRQCLR_M_SM_ERR_SC_Pos (8UL)
9030 #define LIN_IRQCLR_M_SM_ERR_SC_Msk (0x100UL)
9031 #define LIN_IRQCLR_TXD_TMOUT_ISC_Pos (6UL)
9032 #define LIN_IRQCLR_TXD_TMOUT_ISC_Msk (0x40UL)
9033 #define LIN_IRQCLR_OC_ISC_Pos (5UL)
9034 #define LIN_IRQCLR_OC_ISC_Msk (0x20UL)
9035 #define LIN_IRQCLR_OT_ISC_Pos (4UL)
9036 #define LIN_IRQCLR_OT_ISC_Msk (0x10UL)
9037 #define LIN_IRQCLR_M_SM_ERR_ISC_Pos (3UL)
9038 #define LIN_IRQCLR_M_SM_ERR_ISC_Msk (0x8UL)
9040 #define LIN_IRQEN_TXD_TMOUT_IEN_Pos (6UL)
9041 #define LIN_IRQEN_TXD_TMOUT_IEN_Msk (0x40UL)
9042 #define LIN_IRQEN_OC_IEN_Pos (5UL)
9043 #define LIN_IRQEN_OC_IEN_Msk (0x20UL)
9044 #define LIN_IRQEN_OT_IEN_Pos (4UL)
9045 #define LIN_IRQEN_OT_IEN_Msk (0x10UL)
9046 #define LIN_IRQEN_M_SM_ERR_IEN_Pos (3UL)
9047 #define LIN_IRQEN_M_SM_ERR_IEN_Msk (0x8UL)
9049 #define LIN_IRQS_TXD_TMOUT_STS_Pos (11UL)
9050 #define LIN_IRQS_TXD_TMOUT_STS_Msk (0x800UL)
9051 #define LIN_IRQS_OT_STS_Pos (9UL)
9052 #define LIN_IRQS_OT_STS_Msk (0x200UL)
9053 #define LIN_IRQS_M_SM_ERR_STS_Pos (8UL)
9054 #define LIN_IRQS_M_SM_ERR_STS_Msk (0x100UL)
9055 #define LIN_IRQS_TXD_TMOUT_IS_Pos (6UL)
9056 #define LIN_IRQS_TXD_TMOUT_IS_Msk (0x40UL)
9057 #define LIN_IRQS_OC_IS_Pos (5UL)
9058 #define LIN_IRQS_OC_IS_Msk (0x20UL)
9059 #define LIN_IRQS_OT_IS_Pos (4UL)
9060 #define LIN_IRQS_OT_IS_Msk (0x10UL)
9061 #define LIN_IRQS_M_SM_ERR_IS_Pos (3UL)
9062 #define LIN_IRQS_M_SM_ERR_IS_Msk (0x8UL)
9070 #define MATH_DIVCON_DVSSRC_Pos (24UL)
9071 #define MATH_DIVCON_DVSSRC_Msk (0x1f000000UL)
9072 #define MATH_DIVCON_DVDSLC_Pos (16UL)
9073 #define MATH_DIVCON_DVDSLC_Msk (0x1f0000UL)
9074 #define MATH_DIVCON_QSDIR_Pos (15UL)
9075 #define MATH_DIVCON_QSDIR_Msk (0x8000UL)
9076 #define MATH_DIVCON_QSCNT_Pos (8UL)
9077 #define MATH_DIVCON_QSCNT_Msk (0x1f00UL)
9078 #define MATH_DIVCON_DIVMODE_Pos (3UL)
9079 #define MATH_DIVCON_DIVMODE_Msk (0x18UL)
9080 #define MATH_DIVCON_USIGN_Pos (2UL)
9081 #define MATH_DIVCON_USIGN_Msk (0x4UL)
9082 #define MATH_DIVCON_STMODE_Pos (1UL)
9083 #define MATH_DIVCON_STMODE_Msk (0x2UL)
9084 #define MATH_DIVCON_ST_Pos (0UL)
9085 #define MATH_DIVCON_ST_Msk (0x1UL)
9087 #define MATH_DIVST_BSY_Pos (0UL)
9088 #define MATH_DIVST_BSY_Msk (0x1UL)
9090 #define MATH_DVD_VAL_Pos (0UL)
9091 #define MATH_DVD_VAL_Msk (0xffffffffUL)
9093 #define MATH_DVS_VAL_Pos (0UL)
9094 #define MATH_DVS_VAL_Msk (0xffffffffUL)
9096 #define MATH_EVFCR_DIVERRC_Pos (1UL)
9097 #define MATH_EVFCR_DIVERRC_Msk (0x2UL)
9098 #define MATH_EVFCR_DIVEOCC_Pos (0UL)
9099 #define MATH_EVFCR_DIVEOCC_Msk (0x1UL)
9101 #define MATH_EVFR_DIVERR_Pos (1UL)
9102 #define MATH_EVFR_DIVERR_Msk (0x2UL)
9103 #define MATH_EVFR_DIVEOC_Pos (0UL)
9104 #define MATH_EVFR_DIVEOC_Msk (0x1UL)
9106 #define MATH_EVIER_DIVERRIEN_Pos (1UL)
9107 #define MATH_EVIER_DIVERRIEN_Msk (0x2UL)
9108 #define MATH_EVIER_DIVEOCIEN_Pos (0UL)
9109 #define MATH_EVIER_DIVEOCIEN_Msk (0x1UL)
9111 #define MATH_EVSFR_DIVERRS_Pos (1UL)
9112 #define MATH_EVSFR_DIVERRS_Msk (0x2UL)
9113 #define MATH_EVSFR_DIVEOCS_Pos (0UL)
9114 #define MATH_EVSFR_DIVEOCS_Msk (0x1UL)
9116 #define MATH_GLBCON_MATH_EN_Pos (31UL)
9117 #define MATH_GLBCON_MATH_EN_Msk (0x80000000UL)
9118 #define MATH_GLBCON_SUSCFG_Pos (16UL)
9119 #define MATH_GLBCON_SUSCFG_Msk (0x30000UL)
9120 #define MATH_GLBCON_DVSRC_Pos (3UL)
9121 #define MATH_GLBCON_DVSRC_Msk (0x18UL)
9122 #define MATH_GLBCON_DVDRC_Pos (0UL)
9123 #define MATH_GLBCON_DVDRC_Msk (0x3UL)
9125 #define MATH_MATH_ID_MOD_NUMBER_Pos (16UL)
9126 #define MATH_MATH_ID_MOD_NUMBER_Msk (0xffff0000UL)
9127 #define MATH_MATH_ID_MOD_TYPE_Pos (8UL)
9128 #define MATH_MATH_ID_MOD_TYPE_Msk (0xff00UL)
9129 #define MATH_MATH_ID_MOD_REV_Pos (0UL)
9130 #define MATH_MATH_ID_MOD_REV_Msk (0xffUL)
9132 #define MATH_QUOT_VAL_Pos (0UL)
9133 #define MATH_QUOT_VAL_Msk (0xffffffffUL)
9135 #define MATH_RMD_VAL_Pos (0UL)
9136 #define MATH_RMD_VAL_Msk (0xffffffffUL)
9144 #define MF_CSA_CTRL_CSA_VZERO_Pos (8UL)
9145 #define MF_CSA_CTRL_CSA_VZERO_Msk (0x100UL)
9146 #define MF_CSA_CTRL_CSA_MI_EN_Pos (4UL)
9147 #define MF_CSA_CTRL_CSA_MI_EN_Msk (0x10UL)
9148 #define MF_CSA_CTRL_CSA_GAIN_Pos (1UL)
9149 #define MF_CSA_CTRL_CSA_GAIN_Msk (0x6UL)
9150 #define MF_CSA_CTRL_CSA_EN_Pos (0UL)
9151 #define MF_CSA_CTRL_CSA_EN_Msk (0x1UL)
9153 #define MF_REF1_STS_VREF1V2_UPTHWARN_STS_Pos (5UL)
9154 #define MF_REF1_STS_VREF1V2_UPTHWARN_STS_Msk (0x20UL)
9155 #define MF_REF1_STS_VREF1V2_LOTHWARN_STS_Pos (4UL)
9156 #define MF_REF1_STS_VREF1V2_LOTHWARN_STS_Msk (0x10UL)
9164 #define PMU_CNF_RST_TFB_RST_TFB_Pos (0UL)
9165 #define PMU_CNF_RST_TFB_RST_TFB_Msk (0x3UL)
9167 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Pos (2UL)
9168 #define PMU_CNF_WAKE_FILTER_CNF_GPIO_FT_Msk (0xcUL)
9169 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Pos (1UL)
9170 #define PMU_CNF_WAKE_FILTER_CNF_MON_FT_Msk (0x2UL)
9171 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Pos (0UL)
9172 #define PMU_CNF_WAKE_FILTER_CNF_LIN_FT_Msk (0x1UL)
9174 #define PMU_DRV_CTRL_CNF_OFF_Pos (6UL)
9175 #define PMU_DRV_CTRL_CNF_OFF_Msk (0xc0UL)
9176 #define PMU_DRV_CTRL_CNF_ON_Pos (4UL)
9177 #define PMU_DRV_CTRL_CNF_ON_Msk (0x30UL)
9178 #define PMU_DRV_CTRL_GL2_HOLD_ON_Pos (3UL)
9179 #define PMU_DRV_CTRL_GL2_HOLD_ON_Msk (0x8UL)
9180 #define PMU_DRV_CTRL_GL2_CYC_ON_Pos (2UL)
9181 #define PMU_DRV_CTRL_GL2_CYC_ON_Msk (0x4UL)
9182 #define PMU_DRV_CTRL_GL1_HOLD_ON_Pos (1UL)
9183 #define PMU_DRV_CTRL_GL1_HOLD_ON_Msk (0x2UL)
9184 #define PMU_DRV_CTRL_GL1_CYC_ON_Pos (0UL)
9185 #define PMU_DRV_CTRL_GL1_CYC_ON_Msk (0x1UL)
9187 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_4_Pos (12UL)
9188 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_4_Msk (0x1000UL)
9189 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_2_Pos (10UL)
9190 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_2_Msk (0x400UL)
9191 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_1_Pos (9UL)
9192 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_1_Msk (0x200UL)
9193 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_0_Pos (8UL)
9194 #define PMU_GPIO_WAKE_STATUS_GPIO1_STS_0_Msk (0x100UL)
9195 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_5_Pos (5UL)
9196 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_5_Msk (0x20UL)
9197 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_4_Pos (4UL)
9198 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_4_Msk (0x10UL)
9199 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_3_Pos (3UL)
9200 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_3_Msk (0x8UL)
9201 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_2_Pos (2UL)
9202 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_2_Msk (0x4UL)
9203 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_1_Pos (1UL)
9204 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_1_Msk (0x2UL)
9205 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_0_Pos (0UL)
9206 #define PMU_GPIO_WAKE_STATUS_GPIO0_STS_0_Msk (0x1UL)
9208 #define PMU_GPUDATA0to3_DATA3_Pos (24UL)
9209 #define PMU_GPUDATA0to3_DATA3_Msk (0xff000000UL)
9210 #define PMU_GPUDATA0to3_DATA2_Pos (16UL)
9211 #define PMU_GPUDATA0to3_DATA2_Msk (0xff0000UL)
9212 #define PMU_GPUDATA0to3_DATA1_Pos (8UL)
9213 #define PMU_GPUDATA0to3_DATA1_Msk (0xff00UL)
9214 #define PMU_GPUDATA0to3_DATA0_Pos (0UL)
9215 #define PMU_GPUDATA0to3_DATA0_Msk (0xffUL)
9217 #define PMU_GPUDATA4to7_DATA7_Pos (24UL)
9218 #define PMU_GPUDATA4to7_DATA7_Msk (0xff000000UL)
9219 #define PMU_GPUDATA4to7_DATA6_Pos (16UL)
9220 #define PMU_GPUDATA4to7_DATA6_Msk (0xff0000UL)
9221 #define PMU_GPUDATA4to7_DATA5_Pos (8UL)
9222 #define PMU_GPUDATA4to7_DATA5_Msk (0xff00UL)
9223 #define PMU_GPUDATA4to7_DATA4_Pos (0UL)
9224 #define PMU_GPUDATA4to7_DATA4_Msk (0xffUL)
9226 #define PMU_GPUDATA8to11_DATA11_Pos (24UL)
9227 #define PMU_GPUDATA8to11_DATA11_Msk (0xff000000UL)
9228 #define PMU_GPUDATA8to11_DATA10_Pos (16UL)
9229 #define PMU_GPUDATA8to11_DATA10_Msk (0xff0000UL)
9230 #define PMU_GPUDATA8to11_DATA9_Pos (8UL)
9231 #define PMU_GPUDATA8to11_DATA9_Msk (0xff00UL)
9232 #define PMU_GPUDATA8to11_DATA8_Pos (0UL)
9233 #define PMU_GPUDATA8to11_DATA8_Msk (0xffUL)
9235 #define PMU_HIGHSIDE_CTRL_SPARE_Pos (10UL)
9236 #define PMU_HIGHSIDE_CTRL_SPARE_Msk (0x400UL)
9237 #define PMU_HIGHSIDE_CTRL_HS1_CYC_EN_Pos (2UL)
9238 #define PMU_HIGHSIDE_CTRL_HS1_CYC_EN_Msk (0x4UL)
9240 #define PMU_LIN_WAKE_EN_LIN_WAKE_EN_Pos (7UL)
9241 #define PMU_LIN_WAKE_EN_LIN_WAKE_EN_Msk (0x80UL)
9243 #define PMU_MON_CNF1_MON4_STS_Pos (31UL)
9244 #define PMU_MON_CNF1_MON4_STS_Msk (0x80000000UL)
9245 #define PMU_MON_CNF1_MON4_NSLEEP_SPARE_Pos (30UL)
9246 #define PMU_MON_CNF1_MON4_NSLEEP_SPARE_Msk (0x40000000UL)
9247 #define PMU_MON_CNF1_MON4_PU_Pos (29UL)
9248 #define PMU_MON_CNF1_MON4_PU_Msk (0x20000000UL)
9249 #define PMU_MON_CNF1_MON4_PD_Pos (28UL)
9250 #define PMU_MON_CNF1_MON4_PD_Msk (0x10000000UL)
9251 #define PMU_MON_CNF1_MON4_CYC_Pos (27UL)
9252 #define PMU_MON_CNF1_MON4_CYC_Msk (0x8000000UL)
9253 #define PMU_MON_CNF1_MON4_RISE_Pos (26UL)
9254 #define PMU_MON_CNF1_MON4_RISE_Msk (0x4000000UL)
9255 #define PMU_MON_CNF1_MON4_FALL_Pos (25UL)
9256 #define PMU_MON_CNF1_MON4_FALL_Msk (0x2000000UL)
9257 #define PMU_MON_CNF1_MON4_EN_Pos (24UL)
9258 #define PMU_MON_CNF1_MON4_EN_Msk (0x1000000UL)
9259 #define PMU_MON_CNF1_MON3_STS_Pos (23UL)
9260 #define PMU_MON_CNF1_MON3_STS_Msk (0x800000UL)
9261 #define PMU_MON_CNF1_MON3_NSLEEP_SPARE_Pos (22UL)
9262 #define PMU_MON_CNF1_MON3_NSLEEP_SPARE_Msk (0x400000UL)
9263 #define PMU_MON_CNF1_MON3_PU_Pos (21UL)
9264 #define PMU_MON_CNF1_MON3_PU_Msk (0x200000UL)
9265 #define PMU_MON_CNF1_MON3_PD_Pos (20UL)
9266 #define PMU_MON_CNF1_MON3_PD_Msk (0x100000UL)
9267 #define PMU_MON_CNF1_MON3_CYC_Pos (19UL)
9268 #define PMU_MON_CNF1_MON3_CYC_Msk (0x80000UL)
9269 #define PMU_MON_CNF1_MON3_RISE_Pos (18UL)
9270 #define PMU_MON_CNF1_MON3_RISE_Msk (0x40000UL)
9271 #define PMU_MON_CNF1_MON3_FALL_Pos (17UL)
9272 #define PMU_MON_CNF1_MON3_FALL_Msk (0x20000UL)
9273 #define PMU_MON_CNF1_MON3_EN_Pos (16UL)
9274 #define PMU_MON_CNF1_MON3_EN_Msk (0x10000UL)
9275 #define PMU_MON_CNF1_MON2_STS_Pos (15UL)
9276 #define PMU_MON_CNF1_MON2_STS_Msk (0x8000UL)
9277 #define PMU_MON_CNF1_MON2_NSLEEP_SPARE_Pos (14UL)
9278 #define PMU_MON_CNF1_MON2_NSLEEP_SPARE_Msk (0x4000UL)
9279 #define PMU_MON_CNF1_MON2_PU_Pos (13UL)
9280 #define PMU_MON_CNF1_MON2_PU_Msk (0x2000UL)
9281 #define PMU_MON_CNF1_MON2_PD_Pos (12UL)
9282 #define PMU_MON_CNF1_MON2_PD_Msk (0x1000UL)
9283 #define PMU_MON_CNF1_MON2_CYC_Pos (11UL)
9284 #define PMU_MON_CNF1_MON2_CYC_Msk (0x800UL)
9285 #define PMU_MON_CNF1_MON2_RISE_Pos (10UL)
9286 #define PMU_MON_CNF1_MON2_RISE_Msk (0x400UL)
9287 #define PMU_MON_CNF1_MON2_FALL_Pos (9UL)
9288 #define PMU_MON_CNF1_MON2_FALL_Msk (0x200UL)
9289 #define PMU_MON_CNF1_MON2_EN_Pos (8UL)
9290 #define PMU_MON_CNF1_MON2_EN_Msk (0x100UL)
9291 #define PMU_MON_CNF1_MON1_STS_Pos (7UL)
9292 #define PMU_MON_CNF1_MON1_STS_Msk (0x80UL)
9293 #define PMU_MON_CNF1_MON1_NSLEEP_SPARE_Pos (6UL)
9294 #define PMU_MON_CNF1_MON1_NSLEEP_SPARE_Msk (0x40UL)
9295 #define PMU_MON_CNF1_MON1_PU_Pos (5UL)
9296 #define PMU_MON_CNF1_MON1_PU_Msk (0x20UL)
9297 #define PMU_MON_CNF1_MON1_PD_Pos (4UL)
9298 #define PMU_MON_CNF1_MON1_PD_Msk (0x10UL)
9299 #define PMU_MON_CNF1_MON1_CYC_Pos (3UL)
9300 #define PMU_MON_CNF1_MON1_CYC_Msk (0x8UL)
9301 #define PMU_MON_CNF1_MON1_RISE_Pos (2UL)
9302 #define PMU_MON_CNF1_MON1_RISE_Msk (0x4UL)
9303 #define PMU_MON_CNF1_MON1_FALL_Pos (1UL)
9304 #define PMU_MON_CNF1_MON1_FALL_Msk (0x2UL)
9305 #define PMU_MON_CNF1_MON1_EN_Pos (0UL)
9306 #define PMU_MON_CNF1_MON1_EN_Msk (0x1UL)
9308 #define PMU_MON_CNF2_MON5_STS_Pos (7UL)
9309 #define PMU_MON_CNF2_MON5_STS_Msk (0x80UL)
9310 #define PMU_MON_CNF2_MON5_NSLEEP_SPARE_Pos (6UL)
9311 #define PMU_MON_CNF2_MON5_NSLEEP_SPARE_Msk (0x40UL)
9312 #define PMU_MON_CNF2_MON5_PU_Pos (5UL)
9313 #define PMU_MON_CNF2_MON5_PU_Msk (0x20UL)
9314 #define PMU_MON_CNF2_MON5_PD_Pos (4UL)
9315 #define PMU_MON_CNF2_MON5_PD_Msk (0x10UL)
9316 #define PMU_MON_CNF2_MON5_CYC_Pos (3UL)
9317 #define PMU_MON_CNF2_MON5_CYC_Msk (0x8UL)
9318 #define PMU_MON_CNF2_MON5_RISE_Pos (2UL)
9319 #define PMU_MON_CNF2_MON5_RISE_Msk (0x4UL)
9320 #define PMU_MON_CNF2_MON5_FALL_Pos (1UL)
9321 #define PMU_MON_CNF2_MON5_FALL_Msk (0x2UL)
9322 #define PMU_MON_CNF2_MON5_EN_Pos (0UL)
9323 #define PMU_MON_CNF2_MON5_EN_Msk (0x1UL)
9325 #define PMU_OT_CTRL_PMU_OT_EN_Pos (7UL)
9326 #define PMU_OT_CTRL_PMU_OT_EN_Msk (0x80UL)
9327 #define PMU_OT_CTRL_PMU_OT_WAKE_EN_Pos (6UL)
9328 #define PMU_OT_CTRL_PMU_OT_WAKE_EN_Msk (0x40UL)
9329 #define PMU_OT_CTRL_PMU_OT_INT_EN_Pos (5UL)
9330 #define PMU_OT_CTRL_PMU_OT_INT_EN_Msk (0x20UL)
9331 #define PMU_OT_CTRL_PMU_OT_TH_CNF_Pos (0UL)
9332 #define PMU_OT_CTRL_PMU_OT_TH_CNF_Msk (0xfUL)
9334 #define PMU_PORCFG_CNF_FILT_Pos (0UL)
9335 #define PMU_PORCFG_CNF_FILT_Msk (0x3UL)
9337 #define PMU_RESET_STS_LOCKUP_Pos (10UL)
9338 #define PMU_RESET_STS_LOCKUP_Msk (0x400UL)
9339 #define PMU_RESET_STS_PMU_SOFT_Pos (9UL)
9340 #define PMU_RESET_STS_PMU_SOFT_Msk (0x200UL)
9341 #define PMU_RESET_STS_PMU_IntWDT_Pos (8UL)
9342 #define PMU_RESET_STS_PMU_IntWDT_Msk (0x100UL)
9343 #define PMU_RESET_STS_PMU_VS_POR_Pos (7UL)
9344 #define PMU_RESET_STS_PMU_VS_POR_Msk (0x80UL)
9345 #define PMU_RESET_STS_PMU_PIN_Pos (6UL)
9346 #define PMU_RESET_STS_PMU_PIN_Msk (0x40UL)
9347 #define PMU_RESET_STS_PMU_ExtWDT_Pos (5UL)
9348 #define PMU_RESET_STS_PMU_ExtWDT_Msk (0x20UL)
9349 #define PMU_RESET_STS_PMU_ClkWDT_Pos (4UL)
9350 #define PMU_RESET_STS_PMU_ClkWDT_Msk (0x10UL)
9351 #define PMU_RESET_STS_PMU_LPR_Pos (3UL)
9352 #define PMU_RESET_STS_PMU_LPR_Msk (0x8UL)
9353 #define PMU_RESET_STS_PMU_SleepEX_Pos (2UL)
9354 #define PMU_RESET_STS_PMU_SleepEX_Msk (0x4UL)
9355 #define PMU_RESET_STS_PMU_WAKE_Pos (1UL)
9356 #define PMU_RESET_STS_PMU_WAKE_Msk (0x2UL)
9357 #define PMU_RESET_STS_SYS_FAIL_Pos (0UL)
9358 #define PMU_RESET_STS_SYS_FAIL_Msk (0x1UL)
9360 #define PMU_SLEEP_CYC_SENSE_S_DEL_Pos (24UL)
9361 #define PMU_SLEEP_CYC_SENSE_S_DEL_Msk (0x7000000UL)
9362 #define PMU_SLEEP_CYC_WAKE_E01_Pos (20UL)
9363 #define PMU_SLEEP_CYC_WAKE_E01_Msk (0x300000UL)
9364 #define PMU_SLEEP_CYC_WAKE_M03_Pos (16UL)
9365 #define PMU_SLEEP_CYC_WAKE_M03_Msk (0xf0000UL)
9366 #define PMU_SLEEP_CYC_SENSE_E01_Pos (12UL)
9367 #define PMU_SLEEP_CYC_SENSE_E01_Msk (0x3000UL)
9368 #define PMU_SLEEP_CYC_SENSE_M03_Pos (8UL)
9369 #define PMU_SLEEP_CYC_SENSE_M03_Msk (0xf00UL)
9370 #define PMU_SLEEP_CYC_SENSE_EN_Pos (3UL)
9371 #define PMU_SLEEP_CYC_SENSE_EN_Msk (0x8UL)
9372 #define PMU_SLEEP_CYC_WAKE_EN_Pos (2UL)
9373 #define PMU_SLEEP_CYC_WAKE_EN_Msk (0x4UL)
9374 #define PMU_SLEEP_EN_0V9_N_Pos (1UL)
9375 #define PMU_SLEEP_EN_0V9_N_Msk (0x2UL)
9376 #define PMU_SLEEP_WAKE_W_RST_Pos (0UL)
9377 #define PMU_SLEEP_WAKE_W_RST_Msk (0x1UL)
9379 #define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_SC_Pos (13UL)
9380 #define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_SC_Msk (0x2000UL)
9381 #define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_SC_Pos (12UL)
9382 #define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_SC_Msk (0x1000UL)
9383 #define PMU_SUPPLY_STS_PMU_OVERTEMP_SC_Pos (11UL)
9384 #define PMU_SUPPLY_STS_PMU_OVERTEMP_SC_Msk (0x800UL)
9385 #define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_SC_Pos (9UL)
9386 #define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_SC_Msk (0x200UL)
9387 #define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_SC_Pos (8UL)
9388 #define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_SC_Msk (0x100UL)
9389 #define PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos (6UL)
9390 #define PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk (0x40UL)
9391 #define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Pos (5UL)
9392 #define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_Msk (0x20UL)
9393 #define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Pos (4UL)
9394 #define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_Msk (0x10UL)
9395 #define PMU_SUPPLY_STS_PMU_OVERTEMP_Pos (3UL)
9396 #define PMU_SUPPLY_STS_PMU_OVERTEMP_Msk (0x8UL)
9397 #define PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos (2UL)
9398 #define PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk (0x4UL)
9399 #define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Pos (1UL)
9400 #define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_Msk (0x2UL)
9401 #define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Pos (0UL)
9402 #define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_Msk (0x1UL)
9404 #define PMU_VDDEXT_CTRL_VDDEXT_OT_SC_Pos (13UL)
9405 #define PMU_VDDEXT_CTRL_VDDEXT_OT_SC_Msk (0x2000UL)
9406 #define PMU_VDDEXT_CTRL_VDDEXT_UV_ISC_Pos (12UL)
9407 #define PMU_VDDEXT_CTRL_VDDEXT_UV_ISC_Msk (0x1000UL)
9408 #define PMU_VDDEXT_CTRL_VDDEXT_OT_ISC_Pos (11UL)
9409 #define PMU_VDDEXT_CTRL_VDDEXT_OT_ISC_Msk (0x800UL)
9410 #define PMU_VDDEXT_CTRL_VDDEXT_STABLE_Pos (7UL)
9411 #define PMU_VDDEXT_CTRL_VDDEXT_STABLE_Msk (0x80UL)
9412 #define PMU_VDDEXT_CTRL_VDDEXT_OT_Pos (6UL)
9413 #define PMU_VDDEXT_CTRL_VDDEXT_OT_Msk (0x40UL)
9414 #define PMU_VDDEXT_CTRL_VDDEXT_OT_STS_Pos (5UL)
9415 #define PMU_VDDEXT_CTRL_VDDEXT_OT_STS_Msk (0x20UL)
9416 #define PMU_VDDEXT_CTRL_VDDEXT_UV_IS_Pos (4UL)
9417 #define PMU_VDDEXT_CTRL_VDDEXT_UV_IS_Msk (0x10UL)
9418 #define PMU_VDDEXT_CTRL_VDDEXT_OT_IS_Pos (3UL)
9419 #define PMU_VDDEXT_CTRL_VDDEXT_OT_IS_Msk (0x8UL)
9420 #define PMU_VDDEXT_CTRL_VDDEXT_FAIL_EN_Pos (2UL)
9421 #define PMU_VDDEXT_CTRL_VDDEXT_FAIL_EN_Msk (0x4UL)
9422 #define PMU_VDDEXT_CTRL_VDDEXT_CYC_EN_Pos (1UL)
9423 #define PMU_VDDEXT_CTRL_VDDEXT_CYC_EN_Msk (0x2UL)
9424 #define PMU_VDDEXT_CTRL_VDDEXT_ENABLE_Pos (0UL)
9425 #define PMU_VDDEXT_CTRL_VDDEXT_ENABLE_Msk (0x1UL)
9427 #define PMU_WAKE_CNF_GPIO0_CYC_5_Pos (21UL)
9428 #define PMU_WAKE_CNF_GPIO0_CYC_5_Msk (0x200000UL)
9429 #define PMU_WAKE_CNF_GPIO0_CYC_4_Pos (20UL)
9430 #define PMU_WAKE_CNF_GPIO0_CYC_4_Msk (0x100000UL)
9431 #define PMU_WAKE_CNF_GPIO0_CYC_3_Pos (19UL)
9432 #define PMU_WAKE_CNF_GPIO0_CYC_3_Msk (0x80000UL)
9433 #define PMU_WAKE_CNF_GPIO0_CYC_2_Pos (18UL)
9434 #define PMU_WAKE_CNF_GPIO0_CYC_2_Msk (0x40000UL)
9435 #define PMU_WAKE_CNF_GPIO0_CYC_1_Pos (17UL)
9436 #define PMU_WAKE_CNF_GPIO0_CYC_1_Msk (0x20000UL)
9437 #define PMU_WAKE_CNF_GPIO0_CYC_0_Pos (16UL)
9438 #define PMU_WAKE_CNF_GPIO0_CYC_0_Msk (0x10000UL)
9439 #define PMU_WAKE_CNF_GPIO0_FA_5_Pos (13UL)
9440 #define PMU_WAKE_CNF_GPIO0_FA_5_Msk (0x2000UL)
9441 #define PMU_WAKE_CNF_GPIO0_FA_4_Pos (12UL)
9442 #define PMU_WAKE_CNF_GPIO0_FA_4_Msk (0x1000UL)
9443 #define PMU_WAKE_CNF_GPIO0_FA_3_Pos (11UL)
9444 #define PMU_WAKE_CNF_GPIO0_FA_3_Msk (0x800UL)
9445 #define PMU_WAKE_CNF_GPIO0_FA_2_Pos (10UL)
9446 #define PMU_WAKE_CNF_GPIO0_FA_2_Msk (0x400UL)
9447 #define PMU_WAKE_CNF_GPIO0_FA_1_Pos (9UL)
9448 #define PMU_WAKE_CNF_GPIO0_FA_1_Msk (0x200UL)
9449 #define PMU_WAKE_CNF_GPIO0_FA_0_Pos (8UL)
9450 #define PMU_WAKE_CNF_GPIO0_FA_0_Msk (0x100UL)
9451 #define PMU_WAKE_CNF_GPIO0_RI_5_Pos (5UL)
9452 #define PMU_WAKE_CNF_GPIO0_RI_5_Msk (0x20UL)
9453 #define PMU_WAKE_CNF_GPIO0_RI_4_Pos (4UL)
9454 #define PMU_WAKE_CNF_GPIO0_RI_4_Msk (0x10UL)
9455 #define PMU_WAKE_CNF_GPIO0_RI_3_Pos (3UL)
9456 #define PMU_WAKE_CNF_GPIO0_RI_3_Msk (0x8UL)
9457 #define PMU_WAKE_CNF_GPIO0_RI_2_Pos (2UL)
9458 #define PMU_WAKE_CNF_GPIO0_RI_2_Msk (0x4UL)
9459 #define PMU_WAKE_CNF_GPIO0_RI_1_Pos (1UL)
9460 #define PMU_WAKE_CNF_GPIO0_RI_1_Msk (0x2UL)
9461 #define PMU_WAKE_CNF_GPIO0_RI_0_Pos (0UL)
9462 #define PMU_WAKE_CNF_GPIO0_RI_0_Msk (0x1UL)
9464 #define PMU_WAKE_CNF_GPIO1_CYC_4_Pos (20UL)
9465 #define PMU_WAKE_CNF_GPIO1_CYC_4_Msk (0x100000UL)
9466 #define PMU_WAKE_CNF_GPIO1_CYC_2_Pos (18UL)
9467 #define PMU_WAKE_CNF_GPIO1_CYC_2_Msk (0x40000UL)
9468 #define PMU_WAKE_CNF_GPIO1_CYC_1_Pos (17UL)
9469 #define PMU_WAKE_CNF_GPIO1_CYC_1_Msk (0x20000UL)
9470 #define PMU_WAKE_CNF_GPIO1_CYC_0_Pos (16UL)
9471 #define PMU_WAKE_CNF_GPIO1_CYC_0_Msk (0x10000UL)
9472 #define PMU_WAKE_CNF_GPIO1_FA_4_Pos (12UL)
9473 #define PMU_WAKE_CNF_GPIO1_FA_4_Msk (0x1000UL)
9474 #define PMU_WAKE_CNF_GPIO1_FA_2_Pos (10UL)
9475 #define PMU_WAKE_CNF_GPIO1_FA_2_Msk (0x400UL)
9476 #define PMU_WAKE_CNF_GPIO1_FA_1_Pos (9UL)
9477 #define PMU_WAKE_CNF_GPIO1_FA_1_Msk (0x200UL)
9478 #define PMU_WAKE_CNF_GPIO1_FA_0_Pos (8UL)
9479 #define PMU_WAKE_CNF_GPIO1_FA_0_Msk (0x100UL)
9480 #define PMU_WAKE_CNF_GPIO1_RI_4_Pos (4UL)
9481 #define PMU_WAKE_CNF_GPIO1_RI_4_Msk (0x10UL)
9482 #define PMU_WAKE_CNF_GPIO1_RI_2_Pos (2UL)
9483 #define PMU_WAKE_CNF_GPIO1_RI_2_Msk (0x4UL)
9484 #define PMU_WAKE_CNF_GPIO1_RI_1_Pos (1UL)
9485 #define PMU_WAKE_CNF_GPIO1_RI_1_Msk (0x2UL)
9486 #define PMU_WAKE_CNF_GPIO1_RI_0_Pos (0UL)
9487 #define PMU_WAKE_CNF_GPIO1_RI_0_Msk (0x1UL)
9489 #define PMU_WAKE_STATUS_VDDEXT_UV_Pos (18UL)
9490 #define PMU_WAKE_STATUS_VDDEXT_UV_Msk (0x40000UL)
9491 #define PMU_WAKE_STATUS_VDDEXT_OT_Pos (17UL)
9492 #define PMU_WAKE_STATUS_VDDEXT_OT_Msk (0x20000UL)
9493 #define PMU_WAKE_STATUS_PMU_OT_Pos (16UL)
9494 #define PMU_WAKE_STATUS_PMU_OT_Msk (0x10000UL)
9495 #define PMU_WAKE_STATUS_MON5_WAKE_STS_Pos (12UL)
9496 #define PMU_WAKE_STATUS_MON5_WAKE_STS_Msk (0x1000UL)
9497 #define PMU_WAKE_STATUS_MON4_WAKE_STS_Pos (11UL)
9498 #define PMU_WAKE_STATUS_MON4_WAKE_STS_Msk (0x800UL)
9499 #define PMU_WAKE_STATUS_MON3_WAKE_STS_Pos (10UL)
9500 #define PMU_WAKE_STATUS_MON3_WAKE_STS_Msk (0x400UL)
9501 #define PMU_WAKE_STATUS_MON2_WAKE_STS_Pos (9UL)
9502 #define PMU_WAKE_STATUS_MON2_WAKE_STS_Msk (0x200UL)
9503 #define PMU_WAKE_STATUS_MON1_WAKE_STS_Pos (8UL)
9504 #define PMU_WAKE_STATUS_MON1_WAKE_STS_Msk (0x100UL)
9505 #define PMU_WAKE_STATUS_GPIO2_Pos (6UL)
9506 #define PMU_WAKE_STATUS_GPIO2_Msk (0x40UL)
9507 #define PMU_WAKE_STATUS_FAIL_Pos (5UL)
9508 #define PMU_WAKE_STATUS_FAIL_Msk (0x20UL)
9509 #define PMU_WAKE_STATUS_CYC_WAKE_Pos (4UL)
9510 #define PMU_WAKE_STATUS_CYC_WAKE_Msk (0x10UL)
9511 #define PMU_WAKE_STATUS_GPIO1_Pos (3UL)
9512 #define PMU_WAKE_STATUS_GPIO1_Msk (0x8UL)
9513 #define PMU_WAKE_STATUS_GPIO0_Pos (2UL)
9514 #define PMU_WAKE_STATUS_GPIO0_Msk (0x4UL)
9515 #define PMU_WAKE_STATUS_MON_Pos (1UL)
9516 #define PMU_WAKE_STATUS_MON_Msk (0x2UL)
9517 #define PMU_WAKE_STATUS_LIN_WAKE_Pos (0UL)
9518 #define PMU_WAKE_STATUS_LIN_WAKE_Msk (0x1UL)
9520 #define PMU_WFS_PMU_OT_FAIL_Pos (8UL)
9521 #define PMU_WFS_PMU_OT_FAIL_Msk (0x100UL)
9522 #define PMU_WFS_LP_CLKWD_Pos (7UL)
9523 #define PMU_WFS_LP_CLKWD_Msk (0x80UL)
9524 #define PMU_WFS_WDT1_SEQ_FAIL_Pos (6UL)
9525 #define PMU_WFS_WDT1_SEQ_FAIL_Msk (0x40UL)
9526 #define PMU_WFS_SYS_OT_Pos (5UL)
9527 #define PMU_WFS_SYS_OT_Msk (0x20UL)
9528 #define PMU_WFS_SYS_CLK_WDT_Pos (4UL)
9529 #define PMU_WFS_SYS_CLK_WDT_Msk (0x10UL)
9530 #define PMU_WFS_PMU_5V_OVL_Pos (3UL)
9531 #define PMU_WFS_PMU_5V_OVL_Msk (0x8UL)
9532 #define PMU_WFS_PMU_1V5_OVL_Pos (2UL)
9533 #define PMU_WFS_PMU_1V5_OVL_Msk (0x4UL)
9534 #define PMU_WFS_SUPP_TMOUT_Pos (1UL)
9535 #define PMU_WFS_SUPP_TMOUT_Msk (0x2UL)
9536 #define PMU_WFS_SUPP_SHORT_Pos (0UL)
9537 #define PMU_WFS_SUPP_SHORT_Msk (0x1UL)
9545 #define PORT_P0_ALTSEL0_PP5_Pos (5UL)
9546 #define PORT_P0_ALTSEL0_PP5_Msk (0x20UL)
9547 #define PORT_P0_ALTSEL0_PP4_Pos (4UL)
9548 #define PORT_P0_ALTSEL0_PP4_Msk (0x10UL)
9549 #define PORT_P0_ALTSEL0_PP3_Pos (3UL)
9550 #define PORT_P0_ALTSEL0_PP3_Msk (0x8UL)
9551 #define PORT_P0_ALTSEL0_PP2_Pos (2UL)
9552 #define PORT_P0_ALTSEL0_PP2_Msk (0x4UL)
9553 #define PORT_P0_ALTSEL0_PP1_Pos (1UL)
9554 #define PORT_P0_ALTSEL0_PP1_Msk (0x2UL)
9555 #define PORT_P0_ALTSEL0_PP0_Pos (0UL)
9556 #define PORT_P0_ALTSEL0_PP0_Msk (0x1UL)
9558 #define PORT_P0_ALTSEL1_PP5_Pos (5UL)
9559 #define PORT_P0_ALTSEL1_PP5_Msk (0x20UL)
9560 #define PORT_P0_ALTSEL1_PP4_Pos (4UL)
9561 #define PORT_P0_ALTSEL1_PP4_Msk (0x10UL)
9562 #define PORT_P0_ALTSEL1_PP3_Pos (3UL)
9563 #define PORT_P0_ALTSEL1_PP3_Msk (0x8UL)
9564 #define PORT_P0_ALTSEL1_PP2_Pos (2UL)
9565 #define PORT_P0_ALTSEL1_PP2_Msk (0x4UL)
9566 #define PORT_P0_ALTSEL1_PP1_Pos (1UL)
9567 #define PORT_P0_ALTSEL1_PP1_Msk (0x2UL)
9568 #define PORT_P0_ALTSEL1_PP0_Pos (0UL)
9569 #define PORT_P0_ALTSEL1_PP0_Msk (0x1UL)
9571 #define PORT_P0_DATA_PP5_STS_Pos (21UL)
9572 #define PORT_P0_DATA_PP5_STS_Msk (0x200000UL)
9573 #define PORT_P0_DATA_PP4_STS_Pos (20UL)
9574 #define PORT_P0_DATA_PP4_STS_Msk (0x100000UL)
9575 #define PORT_P0_DATA_PP3_STS_Pos (19UL)
9576 #define PORT_P0_DATA_PP3_STS_Msk (0x80000UL)
9577 #define PORT_P0_DATA_PP2_STS_Pos (18UL)
9578 #define PORT_P0_DATA_PP2_STS_Msk (0x40000UL)
9579 #define PORT_P0_DATA_PP1_STS_Pos (17UL)
9580 #define PORT_P0_DATA_PP1_STS_Msk (0x20000UL)
9581 #define PORT_P0_DATA_PP0_STS_Pos (16UL)
9582 #define PORT_P0_DATA_PP0_STS_Msk (0x10000UL)
9583 #define PORT_P0_DATA_PP5_Pos (5UL)
9584 #define PORT_P0_DATA_PP5_Msk (0x20UL)
9585 #define PORT_P0_DATA_PP4_Pos (4UL)
9586 #define PORT_P0_DATA_PP4_Msk (0x10UL)
9587 #define PORT_P0_DATA_PP3_Pos (3UL)
9588 #define PORT_P0_DATA_PP3_Msk (0x8UL)
9589 #define PORT_P0_DATA_PP2_Pos (2UL)
9590 #define PORT_P0_DATA_PP2_Msk (0x4UL)
9591 #define PORT_P0_DATA_PP1_Pos (1UL)
9592 #define PORT_P0_DATA_PP1_Msk (0x2UL)
9593 #define PORT_P0_DATA_PP0_Pos (0UL)
9594 #define PORT_P0_DATA_PP0_Msk (0x1UL)
9596 #define PORT_P0_DIR_PP5_INEN_Pos (21UL)
9597 #define PORT_P0_DIR_PP5_INEN_Msk (0x200000UL)
9598 #define PORT_P0_DIR_PP4_INEN_Pos (20UL)
9599 #define PORT_P0_DIR_PP4_INEN_Msk (0x100000UL)
9600 #define PORT_P0_DIR_PP3_INEN_Pos (19UL)
9601 #define PORT_P0_DIR_PP3_INEN_Msk (0x80000UL)
9602 #define PORT_P0_DIR_PP2_INEN_Pos (18UL)
9603 #define PORT_P0_DIR_PP2_INEN_Msk (0x40000UL)
9604 #define PORT_P0_DIR_PP1_INEN_Pos (17UL)
9605 #define PORT_P0_DIR_PP1_INEN_Msk (0x20000UL)
9606 #define PORT_P0_DIR_PP0_INEN_Pos (16UL)
9607 #define PORT_P0_DIR_PP0_INEN_Msk (0x10000UL)
9608 #define PORT_P0_DIR_PP5_Pos (5UL)
9609 #define PORT_P0_DIR_PP5_Msk (0x20UL)
9610 #define PORT_P0_DIR_PP4_Pos (4UL)
9611 #define PORT_P0_DIR_PP4_Msk (0x10UL)
9612 #define PORT_P0_DIR_PP3_Pos (3UL)
9613 #define PORT_P0_DIR_PP3_Msk (0x8UL)
9614 #define PORT_P0_DIR_PP2_Pos (2UL)
9615 #define PORT_P0_DIR_PP2_Msk (0x4UL)
9616 #define PORT_P0_DIR_PP1_Pos (1UL)
9617 #define PORT_P0_DIR_PP1_Msk (0x2UL)
9618 #define PORT_P0_DIR_PP0_Pos (0UL)
9619 #define PORT_P0_DIR_PP0_Msk (0x1UL)
9621 #define PORT_P0_OD_PP5_Pos (5UL)
9622 #define PORT_P0_OD_PP5_Msk (0x20UL)
9623 #define PORT_P0_OD_PP4_Pos (4UL)
9624 #define PORT_P0_OD_PP4_Msk (0x10UL)
9625 #define PORT_P0_OD_PP3_Pos (3UL)
9626 #define PORT_P0_OD_PP3_Msk (0x8UL)
9627 #define PORT_P0_OD_PP2_Pos (2UL)
9628 #define PORT_P0_OD_PP2_Msk (0x4UL)
9629 #define PORT_P0_OD_PP1_Pos (1UL)
9630 #define PORT_P0_OD_PP1_Msk (0x2UL)
9631 #define PORT_P0_OD_PP0_Pos (0UL)
9632 #define PORT_P0_OD_PP0_Msk (0x1UL)
9634 #define PORT_P0_PUDEN_PP5_Pos (5UL)
9635 #define PORT_P0_PUDEN_PP5_Msk (0x20UL)
9636 #define PORT_P0_PUDEN_PP4_Pos (4UL)
9637 #define PORT_P0_PUDEN_PP4_Msk (0x10UL)
9638 #define PORT_P0_PUDEN_PP3_Pos (3UL)
9639 #define PORT_P0_PUDEN_PP3_Msk (0x8UL)
9640 #define PORT_P0_PUDEN_PP2_Pos (2UL)
9641 #define PORT_P0_PUDEN_PP2_Msk (0x4UL)
9642 #define PORT_P0_PUDEN_PP1_Pos (1UL)
9643 #define PORT_P0_PUDEN_PP1_Msk (0x2UL)
9644 #define PORT_P0_PUDEN_PP0_Pos (0UL)
9645 #define PORT_P0_PUDEN_PP0_Msk (0x1UL)
9647 #define PORT_P0_PUDSEL_PP5_Pos (5UL)
9648 #define PORT_P0_PUDSEL_PP5_Msk (0x20UL)
9649 #define PORT_P0_PUDSEL_PP4_Pos (4UL)
9650 #define PORT_P0_PUDSEL_PP4_Msk (0x10UL)
9651 #define PORT_P0_PUDSEL_PP3_Pos (3UL)
9652 #define PORT_P0_PUDSEL_PP3_Msk (0x8UL)
9653 #define PORT_P0_PUDSEL_PP2_Pos (2UL)
9654 #define PORT_P0_PUDSEL_PP2_Msk (0x4UL)
9655 #define PORT_P0_PUDSEL_PP1_Pos (1UL)
9656 #define PORT_P0_PUDSEL_PP1_Msk (0x2UL)
9657 #define PORT_P0_PUDSEL_PP0_Pos (0UL)
9658 #define PORT_P0_PUDSEL_PP0_Msk (0x1UL)
9660 #define PORT_P1_ALTSEL0_PP4_Pos (4UL)
9661 #define PORT_P1_ALTSEL0_PP4_Msk (0x10UL)
9662 #define PORT_P1_ALTSEL0_PP2_Pos (2UL)
9663 #define PORT_P1_ALTSEL0_PP2_Msk (0x4UL)
9664 #define PORT_P1_ALTSEL0_PP1_Pos (1UL)
9665 #define PORT_P1_ALTSEL0_PP1_Msk (0x2UL)
9666 #define PORT_P1_ALTSEL0_PP0_Pos (0UL)
9667 #define PORT_P1_ALTSEL0_PP0_Msk (0x1UL)
9669 #define PORT_P1_ALTSEL1_PP4_Pos (4UL)
9670 #define PORT_P1_ALTSEL1_PP4_Msk (0x10UL)
9671 #define PORT_P1_ALTSEL1_PP2_Pos (2UL)
9672 #define PORT_P1_ALTSEL1_PP2_Msk (0x4UL)
9673 #define PORT_P1_ALTSEL1_PP1_Pos (1UL)
9674 #define PORT_P1_ALTSEL1_PP1_Msk (0x2UL)
9675 #define PORT_P1_ALTSEL1_PP0_Pos (0UL)
9676 #define PORT_P1_ALTSEL1_PP0_Msk (0x1UL)
9678 #define PORT_P1_DATA_PP4_STS_Pos (20UL)
9679 #define PORT_P1_DATA_PP4_STS_Msk (0x100000UL)
9680 #define PORT_P1_DATA_PP2_STS_Pos (18UL)
9681 #define PORT_P1_DATA_PP2_STS_Msk (0x40000UL)
9682 #define PORT_P1_DATA_PP1_STS_Pos (17UL)
9683 #define PORT_P1_DATA_PP1_STS_Msk (0x20000UL)
9684 #define PORT_P1_DATA_PP0_STS_Pos (16UL)
9685 #define PORT_P1_DATA_PP0_STS_Msk (0x10000UL)
9686 #define PORT_P1_DATA_PP4_Pos (4UL)
9687 #define PORT_P1_DATA_PP4_Msk (0x10UL)
9688 #define PORT_P1_DATA_PP2_Pos (2UL)
9689 #define PORT_P1_DATA_PP2_Msk (0x4UL)
9690 #define PORT_P1_DATA_PP1_Pos (1UL)
9691 #define PORT_P1_DATA_PP1_Msk (0x2UL)
9692 #define PORT_P1_DATA_PP0_Pos (0UL)
9693 #define PORT_P1_DATA_PP0_Msk (0x1UL)
9695 #define PORT_P1_DIR_PP4_INEN_Pos (20UL)
9696 #define PORT_P1_DIR_PP4_INEN_Msk (0x100000UL)
9697 #define PORT_P1_DIR_PP2_INEN_Pos (18UL)
9698 #define PORT_P1_DIR_PP2_INEN_Msk (0x40000UL)
9699 #define PORT_P1_DIR_PP1_INEN_Pos (17UL)
9700 #define PORT_P1_DIR_PP1_INEN_Msk (0x20000UL)
9701 #define PORT_P1_DIR_PP0_INEN_Pos (16UL)
9702 #define PORT_P1_DIR_PP0_INEN_Msk (0x10000UL)
9703 #define PORT_P1_DIR_PP4_Pos (4UL)
9704 #define PORT_P1_DIR_PP4_Msk (0x10UL)
9705 #define PORT_P1_DIR_PP2_Pos (2UL)
9706 #define PORT_P1_DIR_PP2_Msk (0x4UL)
9707 #define PORT_P1_DIR_PP1_Pos (1UL)
9708 #define PORT_P1_DIR_PP1_Msk (0x2UL)
9709 #define PORT_P1_DIR_PP0_Pos (0UL)
9710 #define PORT_P1_DIR_PP0_Msk (0x1UL)
9712 #define PORT_P1_OD_PP4_Pos (4UL)
9713 #define PORT_P1_OD_PP4_Msk (0x10UL)
9714 #define PORT_P1_OD_PP2_Pos (2UL)
9715 #define PORT_P1_OD_PP2_Msk (0x4UL)
9716 #define PORT_P1_OD_PP1_Pos (1UL)
9717 #define PORT_P1_OD_PP1_Msk (0x2UL)
9718 #define PORT_P1_OD_PP0_Pos (0UL)
9719 #define PORT_P1_OD_PP0_Msk (0x1UL)
9721 #define PORT_P1_PUDEN_PP4_Pos (4UL)
9722 #define PORT_P1_PUDEN_PP4_Msk (0x10UL)
9723 #define PORT_P1_PUDEN_PP2_Pos (2UL)
9724 #define PORT_P1_PUDEN_PP2_Msk (0x4UL)
9725 #define PORT_P1_PUDEN_PP1_Pos (1UL)
9726 #define PORT_P1_PUDEN_PP1_Msk (0x2UL)
9727 #define PORT_P1_PUDEN_PP0_Pos (0UL)
9728 #define PORT_P1_PUDEN_PP0_Msk (0x1UL)
9730 #define PORT_P1_PUDSEL_PP4_Pos (4UL)
9731 #define PORT_P1_PUDSEL_PP4_Msk (0x10UL)
9732 #define PORT_P1_PUDSEL_PP2_Pos (2UL)
9733 #define PORT_P1_PUDSEL_PP2_Msk (0x4UL)
9734 #define PORT_P1_PUDSEL_PP1_Pos (1UL)
9735 #define PORT_P1_PUDSEL_PP1_Msk (0x2UL)
9736 #define PORT_P1_PUDSEL_PP0_Pos (0UL)
9737 #define PORT_P1_PUDSEL_PP0_Msk (0x1UL)
9739 #define PORT_P2_DATA_PP7_Pos (7UL)
9740 #define PORT_P2_DATA_PP7_Msk (0x80UL)
9741 #define PORT_P2_DATA_PP3_Pos (3UL)
9742 #define PORT_P2_DATA_PP3_Msk (0x8UL)
9743 #define PORT_P2_DATA_PP2_Pos (2UL)
9744 #define PORT_P2_DATA_PP2_Msk (0x4UL)
9745 #define PORT_P2_DATA_PP1_Pos (1UL)
9746 #define PORT_P2_DATA_PP1_Msk (0x2UL)
9747 #define PORT_P2_DATA_PP0_Pos (0UL)
9748 #define PORT_P2_DATA_PP0_Msk (0x1UL)
9750 #define PORT_P2_DIR_PP7_Pos (7UL)
9751 #define PORT_P2_DIR_PP7_Msk (0x80UL)
9752 #define PORT_P2_DIR_PP3_Pos (3UL)
9753 #define PORT_P2_DIR_PP3_Msk (0x8UL)
9754 #define PORT_P2_DIR_PP2_Pos (2UL)
9755 #define PORT_P2_DIR_PP2_Msk (0x4UL)
9756 #define PORT_P2_DIR_PP1_Pos (1UL)
9757 #define PORT_P2_DIR_PP1_Msk (0x2UL)
9758 #define PORT_P2_DIR_PP0_Pos (0UL)
9759 #define PORT_P2_DIR_PP0_Msk (0x1UL)
9761 #define PORT_P2_PUDEN_PP7_Pos (7UL)
9762 #define PORT_P2_PUDEN_PP7_Msk (0x80UL)
9763 #define PORT_P2_PUDEN_PP3_Pos (3UL)
9764 #define PORT_P2_PUDEN_PP3_Msk (0x8UL)
9765 #define PORT_P2_PUDEN_PP2_Pos (2UL)
9766 #define PORT_P2_PUDEN_PP2_Msk (0x4UL)
9767 #define PORT_P2_PUDEN_PP1_Pos (1UL)
9768 #define PORT_P2_PUDEN_PP1_Msk (0x2UL)
9769 #define PORT_P2_PUDEN_PP0_Pos (0UL)
9770 #define PORT_P2_PUDEN_PP0_Msk (0x1UL)
9772 #define PORT_P2_PUDSEL_PP7_Pos (7UL)
9773 #define PORT_P2_PUDSEL_PP7_Msk (0x80UL)
9774 #define PORT_P2_PUDSEL_PP3_Pos (3UL)
9775 #define PORT_P2_PUDSEL_PP3_Msk (0x8UL)
9776 #define PORT_P2_PUDSEL_PP2_Pos (2UL)
9777 #define PORT_P2_PUDSEL_PP2_Msk (0x4UL)
9778 #define PORT_P2_PUDSEL_PP1_Pos (1UL)
9779 #define PORT_P2_PUDSEL_PP1_Msk (0x2UL)
9780 #define PORT_P2_PUDSEL_PP0_Pos (0UL)
9781 #define PORT_P2_PUDSEL_PP0_Msk (0x1UL)
9789 #define SCU_ADC1_CLK_DPP1_CLK_DIV_Pos (8UL)
9790 #define SCU_ADC1_CLK_DPP1_CLK_DIV_Msk (0x300UL)
9791 #define SCU_ADC1_CLK_ADC1_CLK_DIV_Pos (0UL)
9792 #define SCU_ADC1_CLK_ADC1_CLK_DIV_Msk (0xfUL)
9794 #define SCU_APCLK_CPCLK_DIV_Pos (29UL)
9795 #define SCU_APCLK_CPCLK_DIV_Msk (0x20000000UL)
9796 #define SCU_APCLK_CPCLK_SEL_Pos (28UL)
9797 #define SCU_APCLK_CPCLK_SEL_Msk (0x10000000UL)
9798 #define SCU_APCLK_BGCLK_DIV_Pos (25UL)
9799 #define SCU_APCLK_BGCLK_DIV_Msk (0x2000000UL)
9800 #define SCU_APCLK_BGCLK_SEL_Pos (24UL)
9801 #define SCU_APCLK_BGCLK_SEL_Msk (0x1000000UL)
9802 #define SCU_APCLK_APCLK2FAC_Pos (8UL)
9803 #define SCU_APCLK_APCLK2FAC_Msk (0x1f00UL)
9804 #define SCU_APCLK_APCLK1FAC_Pos (0UL)
9805 #define SCU_APCLK_APCLK1FAC_Msk (0x3UL)
9807 #define SCU_APCLK_CTRL_CLKWDT_IE_Pos (8UL)
9808 #define SCU_APCLK_CTRL_CLKWDT_IE_Msk (0x100UL)
9809 #define SCU_APCLK_CTRL_APCLK_SET_Pos (0UL)
9810 #define SCU_APCLK_CTRL_APCLK_SET_Msk (0x1UL)
9812 #define SCU_APCLK_SCLR_APCLK3SCLR_Pos (16UL)
9813 #define SCU_APCLK_SCLR_APCLK3SCLR_Msk (0x10000UL)
9814 #define SCU_APCLK_SCLR_APCLK2SCLR_Pos (8UL)
9815 #define SCU_APCLK_SCLR_APCLK2SCLR_Msk (0x100UL)
9816 #define SCU_APCLK_SCLR_APCLK1SCLR_Pos (0UL)
9817 #define SCU_APCLK_SCLR_APCLK1SCLR_Msk (0x1UL)
9819 #define SCU_APCLK_STS_BRDRV_CLK_ERR_STS_Pos (20UL)
9820 #define SCU_APCLK_STS_BRDRV_CLK_ERR_STS_Msk (0x100000UL)
9821 #define SCU_APCLK_STS_APCLK3STS_Pos (16UL)
9822 #define SCU_APCLK_STS_APCLK3STS_Msk (0x10000UL)
9823 #define SCU_APCLK_STS_APCLK2STS_Pos (8UL)
9824 #define SCU_APCLK_STS_APCLK2STS_Msk (0x300UL)
9825 #define SCU_APCLK_STS_APCLK_ERR_STS_Pos (4UL)
9826 #define SCU_APCLK_STS_APCLK_ERR_STS_Msk (0x10UL)
9827 #define SCU_APCLK_STS_APCLK1STS_Pos (0UL)
9828 #define SCU_APCLK_STS_APCLK1STS_Msk (0x3UL)
9830 #define SCU_BCON1_BR1_PRE_Pos (1UL)
9831 #define SCU_BCON1_BR1_PRE_Msk (0xeUL)
9832 #define SCU_BCON1_BR1_R_Pos (0UL)
9833 #define SCU_BCON1_BR1_R_Msk (0x1UL)
9835 #define SCU_BCON2_BR2_PRE_Pos (1UL)
9836 #define SCU_BCON2_BR2_PRE_Msk (0xeUL)
9837 #define SCU_BCON2_BR2_R_Pos (0UL)
9838 #define SCU_BCON2_BR2_R_Msk (0x1UL)
9840 #define SCU_BG1_BG1_TIM_VALUE_Pos (16UL)
9841 #define SCU_BG1_BG1_TIM_VALUE_Msk (0x7ff0000UL)
9842 #define SCU_BG1_BG1_BR_VALUE_Pos (0UL)
9843 #define SCU_BG1_BG1_BR_VALUE_Msk (0x7ffUL)
9845 #define SCU_BG2_BG2_TIM_VALUE_Pos (16UL)
9846 #define SCU_BG2_BG2_TIM_VALUE_Msk (0x7ff0000UL)
9847 #define SCU_BG2_BG2_BR_VALUE_Pos (0UL)
9848 #define SCU_BG2_BG2_BR_VALUE_Msk (0x7ffUL)
9850 #define SCU_BGL1_BG1_FD_SEL_Pos (0UL)
9851 #define SCU_BGL1_BG1_FD_SEL_Msk (0x1fUL)
9853 #define SCU_BGL2_BG2_FD_SEL_Pos (0UL)
9854 #define SCU_BGL2_BG2_FD_SEL_Msk (0x1fUL)
9856 #define SCU_BRDRV_CLK_BRDRV_TFILT_DIV_Pos (8UL)
9857 #define SCU_BRDRV_CLK_BRDRV_TFILT_DIV_Msk (0x1f00UL)
9858 #define SCU_BRDRV_CLK_BRDRV_CLK_DIV_Pos (0UL)
9859 #define SCU_BRDRV_CLK_BRDRV_CLK_DIV_Msk (0x3UL)
9861 #define SCU_CMCON2_PBA0CLKREL_Pos (0UL)
9862 #define SCU_CMCON2_PBA0CLKREL_Msk (0x1UL)
9864 #define SCU_COCON_EN_Pos (7UL)
9865 #define SCU_COCON_EN_Msk (0x80UL)
9866 #define SCU_COCON_COUTS1_Pos (6UL)
9867 #define SCU_COCON_COUTS1_Msk (0x40UL)
9868 #define SCU_COCON_TLEN_Pos (5UL)
9869 #define SCU_COCON_TLEN_Msk (0x20UL)
9870 #define SCU_COCON_COUTS0_Pos (4UL)
9871 #define SCU_COCON_COUTS0_Msk (0x10UL)
9872 #define SCU_COCON_COREL_Pos (0UL)
9873 #define SCU_COCON_COREL_Msk (0xfUL)
9875 #define SCU_EDCCON_NVMIE_Pos (2UL)
9876 #define SCU_EDCCON_NVMIE_Msk (0x4UL)
9877 #define SCU_EDCCON_RIE_Pos (0UL)
9878 #define SCU_EDCCON_RIE_Msk (0x1UL)
9880 #define SCU_EDCSCLR_RSBEC_Pos (4UL)
9881 #define SCU_EDCSCLR_RSBEC_Msk (0x10UL)
9882 #define SCU_EDCSCLR_NVMDBEC_Pos (2UL)
9883 #define SCU_EDCSCLR_NVMDBEC_Msk (0x4UL)
9884 #define SCU_EDCSCLR_RDBEC_Pos (0UL)
9885 #define SCU_EDCSCLR_RDBEC_Msk (0x1UL)
9887 #define SCU_EDCSTAT_RSBE_Pos (4UL)
9888 #define SCU_EDCSTAT_RSBE_Msk (0x10UL)
9889 #define SCU_EDCSTAT_NVMDBE_Pos (2UL)
9890 #define SCU_EDCSTAT_NVMDBE_Msk (0x4UL)
9891 #define SCU_EDCSTAT_RDBE_Pos (0UL)
9892 #define SCU_EDCSTAT_RDBE_Msk (0x1UL)
9894 #define SCU_EXICON0_EXINT2_Pos (4UL)
9895 #define SCU_EXICON0_EXINT2_Msk (0x30UL)
9896 #define SCU_EXICON0_EXINT1_Pos (2UL)
9897 #define SCU_EXICON0_EXINT1_Msk (0xcUL)
9898 #define SCU_EXICON0_EXINT0_Pos (0UL)
9899 #define SCU_EXICON0_EXINT0_Msk (0x3UL)
9901 #define SCU_EXICON1_MON4_Pos (6UL)
9902 #define SCU_EXICON1_MON4_Msk (0xc0UL)
9903 #define SCU_EXICON1_MON3_Pos (4UL)
9904 #define SCU_EXICON1_MON3_Msk (0x30UL)
9905 #define SCU_EXICON1_MON2_Pos (2UL)
9906 #define SCU_EXICON1_MON2_Msk (0xcUL)
9907 #define SCU_EXICON1_MON1_Pos (0UL)
9908 #define SCU_EXICON1_MON1_Msk (0x3UL)
9910 #define SCU_GPT12ICLR_GPT12CRC_Pos (5UL)
9911 #define SCU_GPT12ICLR_GPT12CRC_Msk (0x20UL)
9912 #define SCU_GPT12ICLR_GPT2T6C_Pos (4UL)
9913 #define SCU_GPT12ICLR_GPT2T6C_Msk (0x10UL)
9914 #define SCU_GPT12ICLR_GPT2T5C_Pos (3UL)
9915 #define SCU_GPT12ICLR_GPT2T5C_Msk (0x8UL)
9916 #define SCU_GPT12ICLR_GPT1T4C_Pos (2UL)
9917 #define SCU_GPT12ICLR_GPT1T4C_Msk (0x4UL)
9918 #define SCU_GPT12ICLR_GPT1T3C_Pos (1UL)
9919 #define SCU_GPT12ICLR_GPT1T3C_Msk (0x2UL)
9920 #define SCU_GPT12ICLR_GPT1T2C_Pos (0UL)
9921 #define SCU_GPT12ICLR_GPT1T2C_Msk (0x1UL)
9923 #define SCU_GPT12IEN_CRIE_Pos (5UL)
9924 #define SCU_GPT12IEN_CRIE_Msk (0x20UL)
9925 #define SCU_GPT12IEN_T6IE_Pos (4UL)
9926 #define SCU_GPT12IEN_T6IE_Msk (0x10UL)
9927 #define SCU_GPT12IEN_T5IE_Pos (3UL)
9928 #define SCU_GPT12IEN_T5IE_Msk (0x8UL)
9929 #define SCU_GPT12IEN_T4IE_Pos (2UL)
9930 #define SCU_GPT12IEN_T4IE_Msk (0x4UL)
9931 #define SCU_GPT12IEN_T3IE_Pos (1UL)
9932 #define SCU_GPT12IEN_T3IE_Msk (0x2UL)
9933 #define SCU_GPT12IEN_T2IE_Pos (0UL)
9934 #define SCU_GPT12IEN_T2IE_Msk (0x1UL)
9936 #define SCU_GPT12IRC_GPT12CR_Pos (5UL)
9937 #define SCU_GPT12IRC_GPT12CR_Msk (0x20UL)
9938 #define SCU_GPT12IRC_GPT2T6_Pos (4UL)
9939 #define SCU_GPT12IRC_GPT2T6_Msk (0x10UL)
9940 #define SCU_GPT12IRC_GPT2T5_Pos (3UL)
9941 #define SCU_GPT12IRC_GPT2T5_Msk (0x8UL)
9942 #define SCU_GPT12IRC_GPT1T4_Pos (2UL)
9943 #define SCU_GPT12IRC_GPT1T4_Msk (0x4UL)
9944 #define SCU_GPT12IRC_GPT1T3_Pos (1UL)
9945 #define SCU_GPT12IRC_GPT1T3_Msk (0x2UL)
9946 #define SCU_GPT12IRC_GPT1T2_Pos (0UL)
9947 #define SCU_GPT12IRC_GPT1T2_Msk (0x1UL)
9949 #define SCU_GPT12PISEL_GPT12_SEL_Pos (5UL)
9950 #define SCU_GPT12PISEL_GPT12_SEL_Msk (0x20UL)
9951 #define SCU_GPT12PISEL_TRIG_CONF_Pos (4UL)
9952 #define SCU_GPT12PISEL_TRIG_CONF_Msk (0x10UL)
9953 #define SCU_GPT12PISEL_GPT12_Pos (0UL)
9954 #define SCU_GPT12PISEL_GPT12_Msk (0xfUL)
9956 #define SCU_ID_PRODID_Pos (3UL)
9957 #define SCU_ID_PRODID_Msk (0xf8UL)
9958 #define SCU_ID_VERID_Pos (0UL)
9959 #define SCU_ID_VERID_Msk (0x7UL)
9961 #define SCU_IEN0_EA_Pos (31UL)
9962 #define SCU_IEN0_EA_Msk (0x80000000UL)
9964 #define SCU_IRCON0_EXINT2F_Pos (5UL)
9965 #define SCU_IRCON0_EXINT2F_Msk (0x20UL)
9966 #define SCU_IRCON0_EXINT2R_Pos (4UL)
9967 #define SCU_IRCON0_EXINT2R_Msk (0x10UL)
9968 #define SCU_IRCON0_EXINT1F_Pos (3UL)
9969 #define SCU_IRCON0_EXINT1F_Msk (0x8UL)
9970 #define SCU_IRCON0_EXINT1R_Pos (2UL)
9971 #define SCU_IRCON0_EXINT1R_Msk (0x4UL)
9972 #define SCU_IRCON0_EXINT0F_Pos (1UL)
9973 #define SCU_IRCON0_EXINT0F_Msk (0x2UL)
9974 #define SCU_IRCON0_EXINT0R_Pos (0UL)
9975 #define SCU_IRCON0_EXINT0R_Msk (0x1UL)
9977 #define SCU_IRCON0CLR_EXINT2FC_Pos (5UL)
9978 #define SCU_IRCON0CLR_EXINT2FC_Msk (0x20UL)
9979 #define SCU_IRCON0CLR_EXINT2RC_Pos (4UL)
9980 #define SCU_IRCON0CLR_EXINT2RC_Msk (0x10UL)
9981 #define SCU_IRCON0CLR_EXINT1FC_Pos (3UL)
9982 #define SCU_IRCON0CLR_EXINT1FC_Msk (0x8UL)
9983 #define SCU_IRCON0CLR_EXINT1RC_Pos (2UL)
9984 #define SCU_IRCON0CLR_EXINT1RC_Msk (0x4UL)
9985 #define SCU_IRCON0CLR_EXINT0FC_Pos (1UL)
9986 #define SCU_IRCON0CLR_EXINT0FC_Msk (0x2UL)
9987 #define SCU_IRCON0CLR_EXINT0RC_Pos (0UL)
9988 #define SCU_IRCON0CLR_EXINT0RC_Msk (0x1UL)
9990 #define SCU_IRCON1_MON4F_Pos (7UL)
9991 #define SCU_IRCON1_MON4F_Msk (0x80UL)
9992 #define SCU_IRCON1_MON4R_Pos (6UL)
9993 #define SCU_IRCON1_MON4R_Msk (0x40UL)
9994 #define SCU_IRCON1_MON3F_Pos (5UL)
9995 #define SCU_IRCON1_MON3F_Msk (0x20UL)
9996 #define SCU_IRCON1_MON3R_Pos (4UL)
9997 #define SCU_IRCON1_MON3R_Msk (0x10UL)
9998 #define SCU_IRCON1_MON2F_Pos (3UL)
9999 #define SCU_IRCON1_MON2F_Msk (0x8UL)
10000 #define SCU_IRCON1_MON2R_Pos (2UL)
10001 #define SCU_IRCON1_MON2R_Msk (0x4UL)
10002 #define SCU_IRCON1_MON1F_Pos (1UL)
10003 #define SCU_IRCON1_MON1F_Msk (0x2UL)
10004 #define SCU_IRCON1_MON1R_Pos (0UL)
10005 #define SCU_IRCON1_MON1R_Msk (0x1UL)
10007 #define SCU_IRCON1CLR_MON4FC_Pos (7UL)
10008 #define SCU_IRCON1CLR_MON4FC_Msk (0x80UL)
10009 #define SCU_IRCON1CLR_MON4RC_Pos (6UL)
10010 #define SCU_IRCON1CLR_MON4RC_Msk (0x40UL)
10011 #define SCU_IRCON1CLR_MON3FC_Pos (5UL)
10012 #define SCU_IRCON1CLR_MON3FC_Msk (0x20UL)
10013 #define SCU_IRCON1CLR_MON3RC_Pos (4UL)
10014 #define SCU_IRCON1CLR_MON3RC_Msk (0x10UL)
10015 #define SCU_IRCON1CLR_MON2FC_Pos (3UL)
10016 #define SCU_IRCON1CLR_MON2FC_Msk (0x8UL)
10017 #define SCU_IRCON1CLR_MON2RC_Pos (2UL)
10018 #define SCU_IRCON1CLR_MON2RC_Msk (0x4UL)
10019 #define SCU_IRCON1CLR_MON1FC_Pos (1UL)
10020 #define SCU_IRCON1CLR_MON1FC_Msk (0x2UL)
10021 #define SCU_IRCON1CLR_MON1RC_Pos (0UL)
10022 #define SCU_IRCON1CLR_MON1RC_Msk (0x1UL)
10024 #define SCU_IRCON2_RIR1_Pos (2UL)
10025 #define SCU_IRCON2_RIR1_Msk (0x4UL)
10026 #define SCU_IRCON2_TIR1_Pos (1UL)
10027 #define SCU_IRCON2_TIR1_Msk (0x2UL)
10028 #define SCU_IRCON2_EIR1_Pos (0UL)
10029 #define SCU_IRCON2_EIR1_Msk (0x1UL)
10031 #define SCU_IRCON2CLR_RIR1C_Pos (2UL)
10032 #define SCU_IRCON2CLR_RIR1C_Msk (0x4UL)
10033 #define SCU_IRCON2CLR_TIR1C_Pos (1UL)
10034 #define SCU_IRCON2CLR_TIR1C_Msk (0x2UL)
10035 #define SCU_IRCON2CLR_EIR1C_Pos (0UL)
10036 #define SCU_IRCON2CLR_EIR1C_Msk (0x1UL)
10038 #define SCU_IRCON3_RIR2_Pos (2UL)
10039 #define SCU_IRCON3_RIR2_Msk (0x4UL)
10040 #define SCU_IRCON3_TIR2_Pos (1UL)
10041 #define SCU_IRCON3_TIR2_Msk (0x2UL)
10042 #define SCU_IRCON3_EIR2_Pos (0UL)
10043 #define SCU_IRCON3_EIR2_Msk (0x1UL)
10045 #define SCU_IRCON3CLR_RIR2C_Pos (2UL)
10046 #define SCU_IRCON3CLR_RIR2C_Msk (0x4UL)
10047 #define SCU_IRCON3CLR_TIR2C_Pos (1UL)
10048 #define SCU_IRCON3CLR_TIR2C_Msk (0x2UL)
10049 #define SCU_IRCON3CLR_EIR2C_Pos (0UL)
10050 #define SCU_IRCON3CLR_EIR2C_Msk (0x1UL)
10052 #define SCU_IRCON4_CCU6SR3_Pos (20UL)
10053 #define SCU_IRCON4_CCU6SR3_Msk (0x100000UL)
10054 #define SCU_IRCON4_CCU6SR2_Pos (16UL)
10055 #define SCU_IRCON4_CCU6SR2_Msk (0x10000UL)
10056 #define SCU_IRCON4_CCU6SR1_Pos (4UL)
10057 #define SCU_IRCON4_CCU6SR1_Msk (0x10UL)
10058 #define SCU_IRCON4_CCU6SR0_Pos (0UL)
10059 #define SCU_IRCON4_CCU6SR0_Msk (0x1UL)
10061 #define SCU_IRCON4CLR_CCU6SR3C_Pos (20UL)
10062 #define SCU_IRCON4CLR_CCU6SR3C_Msk (0x100000UL)
10063 #define SCU_IRCON4CLR_CCU6SR2C_Pos (16UL)
10064 #define SCU_IRCON4CLR_CCU6SR2C_Msk (0x10000UL)
10065 #define SCU_IRCON4CLR_CCU6SR1C_Pos (4UL)
10066 #define SCU_IRCON4CLR_CCU6SR1C_Msk (0x10UL)
10067 #define SCU_IRCON4CLR_CCU6SR0C_Pos (0UL)
10068 #define SCU_IRCON4CLR_CCU6SR0C_Msk (0x1UL)
10070 #define SCU_IRCON5_WAKEUP_Pos (0UL)
10071 #define SCU_IRCON5_WAKEUP_Msk (0x1UL)
10073 #define SCU_IRCON5CLR_WAKEUPC_Pos (0UL)
10074 #define SCU_IRCON5CLR_WAKEUPC_Msk (0x1UL)
10076 #define SCU_LINSCLR_ERRSYNC_Pos (5UL)
10077 #define SCU_LINSCLR_ERRSYNC_Msk (0x20UL)
10078 #define SCU_LINSCLR_EOFSYNC_Pos (4UL)
10079 #define SCU_LINSCLR_EOFSYNC_Msk (0x10UL)
10080 #define SCU_LINSCLR_BRKC_Pos (3UL)
10081 #define SCU_LINSCLR_BRKC_Msk (0x8UL)
10083 #define SCU_LINST_SYNEN_Pos (6UL)
10084 #define SCU_LINST_SYNEN_Msk (0x40UL)
10085 #define SCU_LINST_ERRSYN_Pos (5UL)
10086 #define SCU_LINST_ERRSYN_Msk (0x20UL)
10087 #define SCU_LINST_EOFSYN_Pos (4UL)
10088 #define SCU_LINST_EOFSYN_Msk (0x10UL)
10089 #define SCU_LINST_BRK_Pos (3UL)
10090 #define SCU_LINST_BRK_Msk (0x8UL)
10091 #define SCU_LINST_BGSEL_Pos (1UL)
10092 #define SCU_LINST_BGSEL_Msk (0x6UL)
10093 #define SCU_LINST_BRDIS_Pos (0UL)
10094 #define SCU_LINST_BRDIS_Msk (0x1UL)
10096 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Pos (4UL)
10097 #define SCU_MEM_ACC_STS_ROM_PROT_ERR_Msk (0x10UL)
10098 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Pos (3UL)
10099 #define SCU_MEM_ACC_STS_NVM_SFR_ADDR_ERR_Msk (0x8UL)
10100 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Pos (2UL)
10101 #define SCU_MEM_ACC_STS_NVM_SFR_PROT_ERR_Msk (0x4UL)
10102 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Pos (1UL)
10103 #define SCU_MEM_ACC_STS_NVM_ADDR_ERR_Msk (0x2UL)
10104 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Pos (0UL)
10105 #define SCU_MEM_ACC_STS_NVM_PROT_ERR_Msk (0x1UL)
10107 #define SCU_MEMSTAT_RAM_TEST_MODE_Pos (22UL)
10108 #define SCU_MEMSTAT_RAM_TEST_MODE_Msk (0x400000UL)
10109 #define SCU_MEMSTAT_RAM_VAL_KEYS_Pos (20UL)
10110 #define SCU_MEMSTAT_RAM_VAL_KEYS_Msk (0x300000UL)
10111 #define SCU_MEMSTAT_NVM_DATA_MODE_Pos (18UL)
10112 #define SCU_MEMSTAT_NVM_DATA_MODE_Msk (0x40000UL)
10113 #define SCU_MEMSTAT_NVM_VAL_KEYS_Pos (16UL)
10114 #define SCU_MEMSTAT_NVM_VAL_KEYS_Msk (0x30000UL)
10115 #define SCU_MEMSTAT_SASTATUS_Pos (6UL)
10116 #define SCU_MEMSTAT_SASTATUS_Msk (0xc0UL)
10117 #define SCU_MEMSTAT_SECTORINFO_Pos (0UL)
10118 #define SCU_MEMSTAT_SECTORINFO_Msk (0x3fUL)
10120 #define SCU_MODIEN1_RIREN2_Pos (10UL)
10121 #define SCU_MODIEN1_RIREN2_Msk (0x400UL)
10122 #define SCU_MODIEN1_TIREN2_Pos (9UL)
10123 #define SCU_MODIEN1_TIREN2_Msk (0x200UL)
10124 #define SCU_MODIEN1_EIREN2_Pos (8UL)
10125 #define SCU_MODIEN1_EIREN2_Msk (0x100UL)
10126 #define SCU_MODIEN1_RIREN1_Pos (2UL)
10127 #define SCU_MODIEN1_RIREN1_Msk (0x4UL)
10128 #define SCU_MODIEN1_TIREN1_Pos (1UL)
10129 #define SCU_MODIEN1_TIREN1_Msk (0x2UL)
10130 #define SCU_MODIEN1_EIREN1_Pos (0UL)
10131 #define SCU_MODIEN1_EIREN1_Msk (0x1UL)
10133 #define SCU_MODIEN2_TIEN2_Pos (7UL)
10134 #define SCU_MODIEN2_TIEN2_Msk (0x80UL)
10135 #define SCU_MODIEN2_RIEN2_Pos (6UL)
10136 #define SCU_MODIEN2_RIEN2_Msk (0x40UL)
10137 #define SCU_MODIEN2_EXINT2_EN_Pos (5UL)
10138 #define SCU_MODIEN2_EXINT2_EN_Msk (0x20UL)
10139 #define SCU_MODIEN2_TIEN1_Pos (1UL)
10140 #define SCU_MODIEN2_TIEN1_Msk (0x2UL)
10141 #define SCU_MODIEN2_RIEN1_Pos (0UL)
10142 #define SCU_MODIEN2_RIEN1_Msk (0x1UL)
10144 #define SCU_MODIEN3_IE0_Pos (0UL)
10145 #define SCU_MODIEN3_IE0_Msk (0x1UL)
10147 #define SCU_MODIEN4_IE1_Pos (0UL)
10148 #define SCU_MODIEN4_IE1_Msk (0x1UL)
10150 #define SCU_MODPISEL_SSC12_S_MRST_OUTSEL_Pos (18UL)
10151 #define SCU_MODPISEL_SSC12_S_MRST_OUTSEL_Msk (0x40000UL)
10152 #define SCU_MODPISEL_SSC12_M_MTSR_OUTSEL_Pos (17UL)
10153 #define SCU_MODPISEL_SSC12_M_MTSR_OUTSEL_Msk (0x20000UL)
10154 #define SCU_MODPISEL_SSC12_M_SCK_OUTSEL_Pos (16UL)
10155 #define SCU_MODPISEL_SSC12_M_SCK_OUTSEL_Msk (0x10000UL)
10156 #define SCU_MODPISEL_U_TX_CONDIS_Pos (7UL)
10157 #define SCU_MODPISEL_U_TX_CONDIS_Msk (0x80UL)
10158 #define SCU_MODPISEL_URIOS1_Pos (6UL)
10159 #define SCU_MODPISEL_URIOS1_Msk (0x40UL)
10160 #define SCU_MODPISEL_EXINT2IS_Pos (4UL)
10161 #define SCU_MODPISEL_EXINT2IS_Msk (0x30UL)
10162 #define SCU_MODPISEL_EXINT1IS_Pos (2UL)
10163 #define SCU_MODPISEL_EXINT1IS_Msk (0xcUL)
10164 #define SCU_MODPISEL_EXINT0IS_Pos (0UL)
10165 #define SCU_MODPISEL_EXINT0IS_Msk (0x3UL)
10167 #define SCU_MODPISEL1_T21EXCON_Pos (7UL)
10168 #define SCU_MODPISEL1_T21EXCON_Msk (0x80UL)
10169 #define SCU_MODPISEL1_T2EXCON_Pos (6UL)
10170 #define SCU_MODPISEL1_T2EXCON_Msk (0x40UL)
10172 #define SCU_MODPISEL2_T21EXISCNF_Pos (10UL)
10173 #define SCU_MODPISEL2_T21EXISCNF_Msk (0xc00UL)
10174 #define SCU_MODPISEL2_T2EXISCNF_Pos (8UL)
10175 #define SCU_MODPISEL2_T2EXISCNF_Msk (0x300UL)
10176 #define SCU_MODPISEL2_T21EXIS_Pos (6UL)
10177 #define SCU_MODPISEL2_T21EXIS_Msk (0xc0UL)
10178 #define SCU_MODPISEL2_T2EXIS_Pos (4UL)
10179 #define SCU_MODPISEL2_T2EXIS_Msk (0x30UL)
10180 #define SCU_MODPISEL2_T21IS_Pos (2UL)
10181 #define SCU_MODPISEL2_T21IS_Msk (0xcUL)
10182 #define SCU_MODPISEL2_T2IS_Pos (0UL)
10183 #define SCU_MODPISEL2_T2IS_Msk (0x3UL)
10185 #define SCU_MODPISEL3_URIOS2_Pos (6UL)
10186 #define SCU_MODPISEL3_URIOS2_Msk (0x40UL)
10188 #define SCU_MODPISEL4_DU4TRIGGEN_Pos (24UL)
10189 #define SCU_MODPISEL4_DU4TRIGGEN_Msk (0x7000000UL)
10190 #define SCU_MODPISEL4_DU3TRIGGEN_Pos (16UL)
10191 #define SCU_MODPISEL4_DU3TRIGGEN_Msk (0x70000UL)
10192 #define SCU_MODPISEL4_DU2TRIGGEN_Pos (8UL)
10193 #define SCU_MODPISEL4_DU2TRIGGEN_Msk (0x700UL)
10194 #define SCU_MODPISEL4_DU1TRIGGEN_Pos (0UL)
10195 #define SCU_MODPISEL4_DU1TRIGGEN_Msk (0x7UL)
10197 #define SCU_MODSUSP_ADC1_SUSP_Pos (10UL)
10198 #define SCU_MODSUSP_ADC1_SUSP_Msk (0x400UL)
10199 #define SCU_MODSUSP_MU_SUSP_Pos (9UL)
10200 #define SCU_MODSUSP_MU_SUSP_Msk (0x200UL)
10201 #define SCU_MODSUSP_WDT1SUSP_Pos (7UL)
10202 #define SCU_MODSUSP_WDT1SUSP_Msk (0x80UL)
10203 #define SCU_MODSUSP_T21_SUSP_Pos (6UL)
10204 #define SCU_MODSUSP_T21_SUSP_Msk (0x40UL)
10205 #define SCU_MODSUSP_GPT12_SUSP_Pos (4UL)
10206 #define SCU_MODSUSP_GPT12_SUSP_Msk (0x10UL)
10207 #define SCU_MODSUSP_T2_SUSP_Pos (3UL)
10208 #define SCU_MODSUSP_T2_SUSP_Msk (0x8UL)
10209 #define SCU_MODSUSP_T13SUSP_Pos (2UL)
10210 #define SCU_MODSUSP_T13SUSP_Msk (0x4UL)
10211 #define SCU_MODSUSP_T12SUSP_Pos (1UL)
10212 #define SCU_MODSUSP_T12SUSP_Msk (0x2UL)
10213 #define SCU_MODSUSP_WDTSUSP_Pos (0UL)
10214 #define SCU_MODSUSP_WDTSUSP_Msk (0x1UL)
10216 #define SCU_MONIEN_MON4IE_Pos (3UL)
10217 #define SCU_MONIEN_MON4IE_Msk (0x8UL)
10218 #define SCU_MONIEN_MON3IE_Pos (2UL)
10219 #define SCU_MONIEN_MON3IE_Msk (0x4UL)
10220 #define SCU_MONIEN_MON2IE_Pos (1UL)
10221 #define SCU_MONIEN_MON2IE_Msk (0x2UL)
10222 #define SCU_MONIEN_MON1IE_Pos (0UL)
10223 #define SCU_MONIEN_MON1IE_Msk (0x1UL)
10225 #define SCU_NMICON_NMISTOF_Pos (8UL)
10226 #define SCU_NMICON_NMISTOF_Msk (0x100UL)
10227 #define SCU_NMICON_NMISUP_Pos (7UL)
10228 #define SCU_NMICON_NMISUP_Msk (0x80UL)
10229 #define SCU_NMICON_NMIECC_Pos (6UL)
10230 #define SCU_NMICON_NMIECC_Msk (0x40UL)
10231 #define SCU_NMICON_NMIMAP_Pos (5UL)
10232 #define SCU_NMICON_NMIMAP_Msk (0x20UL)
10233 #define SCU_NMICON_NMIOWD_Pos (4UL)
10234 #define SCU_NMICON_NMIOWD_Msk (0x10UL)
10235 #define SCU_NMICON_NMIOT_Pos (3UL)
10236 #define SCU_NMICON_NMIOT_Msk (0x8UL)
10237 #define SCU_NMICON_NMIWDT_Pos (0UL)
10238 #define SCU_NMICON_NMIWDT_Msk (0x1UL)
10240 #define SCU_NMISR_FNMISTOF_Pos (8UL)
10241 #define SCU_NMISR_FNMISTOF_Msk (0x100UL)
10242 #define SCU_NMISR_FNMISUP_Pos (7UL)
10243 #define SCU_NMISR_FNMISUP_Msk (0x80UL)
10244 #define SCU_NMISR_FNMIECC_Pos (6UL)
10245 #define SCU_NMISR_FNMIECC_Msk (0x40UL)
10246 #define SCU_NMISR_FNMIMAP_Pos (5UL)
10247 #define SCU_NMISR_FNMIMAP_Msk (0x20UL)
10248 #define SCU_NMISR_FNMIOWD_Pos (4UL)
10249 #define SCU_NMISR_FNMIOWD_Msk (0x10UL)
10250 #define SCU_NMISR_FNMIOT_Pos (3UL)
10251 #define SCU_NMISR_FNMIOT_Msk (0x8UL)
10252 #define SCU_NMISR_FNMIWDT_Pos (0UL)
10253 #define SCU_NMISR_FNMIWDT_Msk (0x1UL)
10255 #define SCU_NMISRCLR_FNMIMAPC_Pos (5UL)
10256 #define SCU_NMISRCLR_FNMIMAPC_Msk (0x20UL)
10257 #define SCU_NMISRCLR_FNMIOWDC_Pos (4UL)
10258 #define SCU_NMISRCLR_FNMIOWDC_Msk (0x10UL)
10259 #define SCU_NMISRCLR_FNMIWDTC_Pos (0UL)
10260 #define SCU_NMISRCLR_FNMIWDTC_Msk (0x1UL)
10262 #define SCU_NVM_PROT_STS_DAT_LIN_SIZE_Pos (26UL)
10263 #define SCU_NVM_PROT_STS_DAT_LIN_SIZE_Msk (0xc000000UL)
10264 #define SCU_NVM_PROT_STS_CUS_BSL_SIZE_Pos (24UL)
10265 #define SCU_NVM_PROT_STS_CUS_BSL_SIZE_Msk (0x3000000UL)
10266 #define SCU_NVM_PROT_STS_DAT_NL_PW_Pos (22UL)
10267 #define SCU_NVM_PROT_STS_DAT_NL_PW_Msk (0x400000UL)
10268 #define SCU_NVM_PROT_STS_DAT_LIN_PW_Pos (21UL)
10269 #define SCU_NVM_PROT_STS_DAT_LIN_PW_Msk (0x200000UL)
10270 #define SCU_NVM_PROT_STS_COD_LIN_PW_Pos (20UL)
10271 #define SCU_NVM_PROT_STS_COD_LIN_PW_Msk (0x100000UL)
10272 #define SCU_NVM_PROT_STS_CUS_BSL_PW_Pos (19UL)
10273 #define SCU_NVM_PROT_STS_CUS_BSL_PW_Msk (0x80000UL)
10274 #define SCU_NVM_PROT_STS_DIS_RDUS_S0_Pos (18UL)
10275 #define SCU_NVM_PROT_STS_DIS_RDUS_S0_Msk (0x40000UL)
10276 #define SCU_NVM_PROT_STS_DIS_RDUS_Pos (17UL)
10277 #define SCU_NVM_PROT_STS_DIS_RDUS_Msk (0x20000UL)
10278 #define SCU_NVM_PROT_STS_EN_RD_S0_Pos (16UL)
10279 #define SCU_NVM_PROT_STS_EN_RD_S0_Msk (0x10000UL)
10280 #define SCU_NVM_PROT_STS_EN_PRG_DAT_NL_Pos (7UL)
10281 #define SCU_NVM_PROT_STS_EN_PRG_DAT_NL_Msk (0x80UL)
10282 #define SCU_NVM_PROT_STS_EN_RD_DAT_NL_Pos (6UL)
10283 #define SCU_NVM_PROT_STS_EN_RD_DAT_NL_Msk (0x40UL)
10284 #define SCU_NVM_PROT_STS_EN_PRG_DAT_LIN_Pos (5UL)
10285 #define SCU_NVM_PROT_STS_EN_PRG_DAT_LIN_Msk (0x20UL)
10286 #define SCU_NVM_PROT_STS_EN_RD_DAT_LIN_Pos (4UL)
10287 #define SCU_NVM_PROT_STS_EN_RD_DAT_LIN_Msk (0x10UL)
10288 #define SCU_NVM_PROT_STS_EN_PRG_COD_LIN_Pos (3UL)
10289 #define SCU_NVM_PROT_STS_EN_PRG_COD_LIN_Msk (0x8UL)
10290 #define SCU_NVM_PROT_STS_EN_RD_COD_LIN_Pos (2UL)
10291 #define SCU_NVM_PROT_STS_EN_RD_COD_LIN_Msk (0x4UL)
10292 #define SCU_NVM_PROT_STS_EN_PRG_CUS_BSL_Pos (1UL)
10293 #define SCU_NVM_PROT_STS_EN_PRG_CUS_BSL_Msk (0x2UL)
10294 #define SCU_NVM_PROT_STS_EN_RD_CUS_BSL_Pos (0UL)
10295 #define SCU_NVM_PROT_STS_EN_RD_CUS_BSL_Msk (0x1UL)
10297 #define SCU_P0_POCON0_P0_PDM6_Pos (24UL)
10298 #define SCU_P0_POCON0_P0_PDM6_Msk (0x7000000UL)
10299 #define SCU_P0_POCON0_P0_PDM5_Pos (20UL)
10300 #define SCU_P0_POCON0_P0_PDM5_Msk (0x700000UL)
10301 #define SCU_P0_POCON0_P0_PDM4_Pos (16UL)
10302 #define SCU_P0_POCON0_P0_PDM4_Msk (0x70000UL)
10303 #define SCU_P0_POCON0_P0_PDM3_Pos (12UL)
10304 #define SCU_P0_POCON0_P0_PDM3_Msk (0x7000UL)
10305 #define SCU_P0_POCON0_P0_PDM2_Pos (8UL)
10306 #define SCU_P0_POCON0_P0_PDM2_Msk (0x700UL)
10307 #define SCU_P0_POCON0_P0_PDM1_Pos (4UL)
10308 #define SCU_P0_POCON0_P0_PDM1_Msk (0x70UL)
10309 #define SCU_P0_POCON0_P0_PDM0_Pos (0UL)
10310 #define SCU_P0_POCON0_P0_PDM0_Msk (0x7UL)
10312 #define SCU_P1_POCON0_P1_PDM4_Pos (16UL)
10313 #define SCU_P1_POCON0_P1_PDM4_Msk (0x70000UL)
10314 #define SCU_P1_POCON0_P1_PDM2_Pos (8UL)
10315 #define SCU_P1_POCON0_P1_PDM2_Msk (0x700UL)
10316 #define SCU_P1_POCON0_P1_PDM1_Pos (4UL)
10317 #define SCU_P1_POCON0_P1_PDM1_Msk (0x70UL)
10318 #define SCU_P1_POCON0_P1_PDM0_Pos (0UL)
10319 #define SCU_P1_POCON0_P1_PDM0_Msk (0x7UL)
10321 #define SCU_PASSWD_PASS_Pos (3UL)
10322 #define SCU_PASSWD_PASS_Msk (0xf8UL)
10323 #define SCU_PASSWD_PROTECT_S_Pos (2UL)
10324 #define SCU_PASSWD_PROTECT_S_Msk (0x4UL)
10325 #define SCU_PASSWD_PW_MODE_Pos (0UL)
10326 #define SCU_PASSWD_PW_MODE_Msk (0x3UL)
10328 #define SCU_PMCON_T21_DIS_Pos (10UL)
10329 #define SCU_PMCON_T21_DIS_Msk (0x400UL)
10330 #define SCU_PMCON_SSC2_DIS_Pos (8UL)
10331 #define SCU_PMCON_SSC2_DIS_Msk (0x100UL)
10332 #define SCU_PMCON_GPT12_DIS_Pos (4UL)
10333 #define SCU_PMCON_GPT12_DIS_Msk (0x10UL)
10334 #define SCU_PMCON_T2_DIS_Pos (3UL)
10335 #define SCU_PMCON_T2_DIS_Msk (0x8UL)
10336 #define SCU_PMCON_CCU_DIS_Pos (2UL)
10337 #define SCU_PMCON_CCU_DIS_Msk (0x4UL)
10338 #define SCU_PMCON_SSC1_DIS_Pos (1UL)
10339 #define SCU_PMCON_SSC1_DIS_Msk (0x2UL)
10340 #define SCU_PMCON_ADC1_DIS_Pos (0UL)
10341 #define SCU_PMCON_ADC1_DIS_Msk (0x1UL)
10343 #define SCU_PMCON0_SD_Pos (3UL)
10344 #define SCU_PMCON0_SD_Msk (0x8UL)
10345 #define SCU_PMCON0_PD_Pos (2UL)
10346 #define SCU_PMCON0_PD_Msk (0x4UL)
10347 #define SCU_PMCON0_SL_Pos (1UL)
10348 #define SCU_PMCON0_SL_Msk (0x2UL)
10350 #define SCU_RSTCON_LOCKUP_EN_Pos (7UL)
10351 #define SCU_RSTCON_LOCKUP_EN_Msk (0x80UL)
10352 #define SCU_RSTCON_LOCKUP_Pos (0UL)
10353 #define SCU_RSTCON_LOCKUP_Msk (0x1UL)
10355 #define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_H_Pos (18UL)
10356 #define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_H_Msk (0xffc0000UL)
10357 #define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_L_Pos (2UL)
10358 #define SCU_STACK_OVF_ADDR_STOF_ADDR_OFF_L_Msk (0xffcUL)
10360 #define SCU_STACK_OVF_CTRL_STOF_EN_Pos (0UL)
10361 #define SCU_STACK_OVF_CTRL_STOF_EN_Msk (0x1UL)
10363 #define SCU_STACK_OVF_STS_STOF_STS_Pos (0UL)
10364 #define SCU_STACK_OVF_STS_STOF_STS_Msk (0x1UL)
10366 #define SCU_STACK_OVFCLR_STOF_STSC_Pos (0UL)
10367 #define SCU_STACK_OVFCLR_STOF_STSC_Msk (0x1UL)
10369 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Pos (2UL)
10370 #define SCU_SYS_STRTUP_STS_PG100TP_CHKS_ERR_Msk (0x4UL)
10371 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Pos (1UL)
10372 #define SCU_SYS_STRTUP_STS_MRAMINITSTS_Msk (0x2UL)
10374 #define SCU_SYSCON0_SYSCLKSEL_Pos (6UL)
10375 #define SCU_SYSCON0_SYSCLKSEL_Msk (0xc0UL)
10376 #define SCU_SYSCON0_NVMCLKFAC_Pos (4UL)
10377 #define SCU_SYSCON0_NVMCLKFAC_Msk (0x30UL)
10379 #define SCU_TCCR_TCC_Pos (0UL)
10380 #define SCU_TCCR_TCC_Msk (0x3UL)
10382 #define SCU_VTOR_VTOR_BYP_Pos (0UL)
10383 #define SCU_VTOR_VTOR_BYP_Msk (0x3UL)
10385 #define SCU_WAKECON_WAKEUPEN_Pos (0UL)
10386 #define SCU_WAKECON_WAKEUPEN_Msk (0x1UL)
10388 #define SCU_WDT_WDT_Pos (0UL)
10389 #define SCU_WDT_WDT_Msk (0xffffUL)
10391 #define SCU_WDTCON_WINBEN_Pos (5UL)
10392 #define SCU_WDTCON_WINBEN_Msk (0x20UL)
10393 #define SCU_WDTCON_WDTPR_Pos (4UL)
10394 #define SCU_WDTCON_WDTPR_Msk (0x10UL)
10395 #define SCU_WDTCON_WDTEN_Pos (2UL)
10396 #define SCU_WDTCON_WDTEN_Msk (0x4UL)
10397 #define SCU_WDTCON_WDTRS_Pos (1UL)
10398 #define SCU_WDTCON_WDTRS_Msk (0x2UL)
10399 #define SCU_WDTCON_WDTIN_Pos (0UL)
10400 #define SCU_WDTCON_WDTIN_Msk (0x1UL)
10402 #define SCU_WDTREL_WDTREL_Pos (0UL)
10403 #define SCU_WDTREL_WDTREL_Msk (0xffUL)
10405 #define SCU_WDTWINB_WDTWINB_Pos (0UL)
10406 #define SCU_WDTWINB_WDTWINB_Msk (0xffUL)
10414 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos (0UL)
10415 #define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk (0x1UL)
10417 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Pos (8UL)
10418 #define SCUPM_AMCLK_FREQ_STS_AMCLK2_FREQ_Msk (0x3f00UL)
10419 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Pos (0UL)
10420 #define SCUPM_AMCLK_FREQ_STS_AMCLK1_FREQ_Msk (0x3fUL)
10422 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos (30UL)
10423 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk (0xc0000000UL)
10424 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos (24UL)
10425 #define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk (0x3f000000UL)
10426 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos (22UL)
10427 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk (0xc00000UL)
10428 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos (16UL)
10429 #define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk (0x3f0000UL)
10430 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos (14UL)
10431 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk (0xc000UL)
10432 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos (8UL)
10433 #define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk (0x3f00UL)
10434 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos (6UL)
10435 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk (0xc0UL)
10436 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos (0UL)
10437 #define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk (0x3fUL)
10439 #define SCUPM_PCU_CTRL_STS_CLKLOSS_RES_SD_DIS_Pos (27UL)
10440 #define SCUPM_PCU_CTRL_STS_CLKLOSS_RES_SD_DIS_Msk (0x8000000UL)
10441 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos (26UL)
10442 #define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk (0x4000000UL)
10443 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos (25UL)
10444 #define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk (0x2000000UL)
10445 #define SCUPM_PCU_CTRL_STS_SYS_OTWARN_PS_DIS_Pos (24UL)
10446 #define SCUPM_PCU_CTRL_STS_SYS_OTWARN_PS_DIS_Msk (0x1000000UL)
10447 #define SCUPM_PCU_CTRL_STS_SYS_VS_OV_SLM_DIS_Pos (14UL)
10448 #define SCUPM_PCU_CTRL_STS_SYS_VS_OV_SLM_DIS_Msk (0x4000UL)
10449 #define SCUPM_PCU_CTRL_STS_SYS_VS_UV_SLM_DIS_Pos (13UL)
10450 #define SCUPM_PCU_CTRL_STS_SYS_VS_UV_SLM_DIS_Msk (0x2000UL)
10451 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos (8UL)
10452 #define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk (0x100UL)
10453 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos (7UL)
10454 #define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk (0x80UL)
10455 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos (1UL)
10456 #define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk (0x2UL)
10458 #define SCUPM_STCALIB_STCALIB_Pos (0UL)
10459 #define SCUPM_STCALIB_STCALIB_Msk (0x3ffffffUL)
10461 #define SCUPM_SYS_IRQ_CTRL_VREF1V2_OV_IE_Pos (13UL)
10462 #define SCUPM_SYS_IRQ_CTRL_VREF1V2_OV_IE_Msk (0x2000UL)
10463 #define SCUPM_SYS_IRQ_CTRL_VREF1V2_UV_IE_Pos (12UL)
10464 #define SCUPM_SYS_IRQ_CTRL_VREF1V2_UV_IE_Msk (0x1000UL)
10465 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Pos (9UL)
10466 #define SCUPM_SYS_IRQ_CTRL_SYS_OT_IE_Msk (0x200UL)
10467 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Pos (8UL)
10468 #define SCUPM_SYS_IRQ_CTRL_SYS_OTWARN_IE_Msk (0x100UL)
10470 #define SCUPM_SYS_IS_SYS_SUPPLY_STS_Pos (30UL)
10471 #define SCUPM_SYS_IS_SYS_SUPPLY_STS_Msk (0x40000000UL)
10472 #define SCUPM_SYS_IS_VREF1V2_OV_STS_Pos (29UL)
10473 #define SCUPM_SYS_IS_VREF1V2_OV_STS_Msk (0x20000000UL)
10474 #define SCUPM_SYS_IS_VREF1V2_UV_STS_Pos (28UL)
10475 #define SCUPM_SYS_IS_VREF1V2_UV_STS_Msk (0x10000000UL)
10476 #define SCUPM_SYS_IS_SYS_OT_STS_Pos (25UL)
10477 #define SCUPM_SYS_IS_SYS_OT_STS_Msk (0x2000000UL)
10478 #define SCUPM_SYS_IS_SYS_OTWARN_STS_Pos (24UL)
10479 #define SCUPM_SYS_IS_SYS_OTWARN_STS_Msk (0x1000000UL)
10480 #define SCUPM_SYS_IS_HS_FAIL_STS_Pos (19UL)
10481 #define SCUPM_SYS_IS_HS_FAIL_STS_Msk (0x80000UL)
10482 #define SCUPM_SYS_IS_DRV_FAIL_STS_Pos (18UL)
10483 #define SCUPM_SYS_IS_DRV_FAIL_STS_Msk (0x40000UL)
10484 #define SCUPM_SYS_IS_CP_FAIL_STS_Pos (17UL)
10485 #define SCUPM_SYS_IS_CP_FAIL_STS_Msk (0x20000UL)
10486 #define SCUPM_SYS_IS_LIN_FAIL_STS_Pos (16UL)
10487 #define SCUPM_SYS_IS_LIN_FAIL_STS_Msk (0x10000UL)
10488 #define SCUPM_SYS_IS_SYS_SUPPLY_IS_Pos (14UL)
10489 #define SCUPM_SYS_IS_SYS_SUPPLY_IS_Msk (0x4000UL)
10490 #define SCUPM_SYS_IS_VREF1V2_OV_IS_Pos (13UL)
10491 #define SCUPM_SYS_IS_VREF1V2_OV_IS_Msk (0x2000UL)
10492 #define SCUPM_SYS_IS_VREF1V2_UV_IS_Pos (12UL)
10493 #define SCUPM_SYS_IS_VREF1V2_UV_IS_Msk (0x1000UL)
10494 #define SCUPM_SYS_IS_CLKWDT_IS_Pos (10UL)
10495 #define SCUPM_SYS_IS_CLKWDT_IS_Msk (0x400UL)
10496 #define SCUPM_SYS_IS_SYS_OT_IS_Pos (9UL)
10497 #define SCUPM_SYS_IS_SYS_OT_IS_Msk (0x200UL)
10498 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Pos (8UL)
10499 #define SCUPM_SYS_IS_SYS_OTWARN_IS_Msk (0x100UL)
10500 #define SCUPM_SYS_IS_HS_FAIL_IS_Pos (3UL)
10501 #define SCUPM_SYS_IS_HS_FAIL_IS_Msk (0x8UL)
10502 #define SCUPM_SYS_IS_DRV_FAIL_IS_Pos (2UL)
10503 #define SCUPM_SYS_IS_DRV_FAIL_IS_Msk (0x4UL)
10504 #define SCUPM_SYS_IS_CP_FAIL_IS_Pos (1UL)
10505 #define SCUPM_SYS_IS_CP_FAIL_IS_Msk (0x2UL)
10506 #define SCUPM_SYS_IS_LIN_FAIL_IS_Pos (0UL)
10507 #define SCUPM_SYS_IS_LIN_FAIL_IS_Msk (0x1UL)
10509 #define SCUPM_SYS_ISCLR_VREF1V2_OV_SC_Pos (29UL)
10510 #define SCUPM_SYS_ISCLR_VREF1V2_OV_SC_Msk (0x20000000UL)
10511 #define SCUPM_SYS_ISCLR_VREF1V2_UV_SC_Pos (28UL)
10512 #define SCUPM_SYS_ISCLR_VREF1V2_UV_SC_Msk (0x10000000UL)
10513 #define SCUPM_SYS_ISCLR_SYS_OT_SC_Pos (25UL)
10514 #define SCUPM_SYS_ISCLR_SYS_OT_SC_Msk (0x2000000UL)
10515 #define SCUPM_SYS_ISCLR_SYS_OTWARN_SC_Pos (24UL)
10516 #define SCUPM_SYS_ISCLR_SYS_OTWARN_SC_Msk (0x1000000UL)
10517 #define SCUPM_SYS_ISCLR_VREF1V2_OV_ISC_Pos (13UL)
10518 #define SCUPM_SYS_ISCLR_VREF1V2_OV_ISC_Msk (0x2000UL)
10519 #define SCUPM_SYS_ISCLR_VREF1V2_UV_ISC_Pos (12UL)
10520 #define SCUPM_SYS_ISCLR_VREF1V2_UV_ISC_Msk (0x1000UL)
10521 #define SCUPM_SYS_ISCLR_SYS_OT_ISC_Pos (9UL)
10522 #define SCUPM_SYS_ISCLR_SYS_OT_ISC_Msk (0x200UL)
10523 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ISC_Pos (8UL)
10524 #define SCUPM_SYS_ISCLR_SYS_OTWARN_ISC_Msk (0x100UL)
10526 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SC_Pos (30UL)
10527 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_SC_Msk (0x40000000UL)
10528 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SC_Pos (28UL)
10529 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_SC_Msk (0x10000000UL)
10530 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_SC_Pos (27UL)
10531 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_SC_Msk (0x8000000UL)
10532 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SC_Pos (24UL)
10533 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_SC_Msk (0x1000000UL)
10534 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SC_Pos (22UL)
10535 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_SC_Msk (0x400000UL)
10536 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SC_Pos (20UL)
10537 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_SC_Msk (0x100000UL)
10538 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_SC_Pos (19UL)
10539 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_SC_Msk (0x80000UL)
10540 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SC_Pos (16UL)
10541 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_SC_Msk (0x10000UL)
10542 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ISC_Pos (14UL)
10543 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_OV_ISC_Msk (0x4000UL)
10544 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ISC_Pos (12UL)
10545 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_OV_ISC_Msk (0x1000UL)
10546 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_ISC_Pos (11UL)
10547 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_OV_ISC_Msk (0x800UL)
10548 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ISC_Pos (8UL)
10549 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_OV_ISC_Msk (0x100UL)
10550 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ISC_Pos (6UL)
10551 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD1V5_UV_ISC_Msk (0x40UL)
10552 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ISC_Pos (4UL)
10553 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDD5V_UV_ISC_Msk (0x10UL)
10554 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_ISC_Pos (3UL)
10555 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VDDEXT_UV_ISC_Msk (0x8UL)
10556 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ISC_Pos (0UL)
10557 #define SCUPM_SYS_SUPPLY_IRQ_CLR_VS_UV_ISC_Msk (0x1UL)
10559 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Pos (14UL)
10560 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_OV_IE_Msk (0x4000UL)
10561 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Pos (12UL)
10562 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_OV_IE_Msk (0x1000UL)
10563 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_OV_IE_Pos (11UL)
10564 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_OV_IE_Msk (0x800UL)
10565 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Pos (8UL)
10566 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_OV_IE_Msk (0x100UL)
10567 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Pos (6UL)
10568 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD1V5_UV_IE_Msk (0x40UL)
10569 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Pos (4UL)
10570 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDD5V_UV_IE_Msk (0x10UL)
10571 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_UV_IE_Pos (3UL)
10572 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VDDEXT_UV_IE_Msk (0x8UL)
10573 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Pos (0UL)
10574 #define SCUPM_SYS_SUPPLY_IRQ_CTRL_VS_UV_IE_Msk (0x1UL)
10576 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Pos (30UL)
10577 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_STS_Msk (0x40000000UL)
10578 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Pos (28UL)
10579 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_STS_Msk (0x10000000UL)
10580 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_STS_Pos (27UL)
10581 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_STS_Msk (0x8000000UL)
10582 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Pos (24UL)
10583 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_STS_Msk (0x1000000UL)
10584 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Pos (22UL)
10585 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_STS_Msk (0x400000UL)
10586 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Pos (20UL)
10587 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_STS_Msk (0x100000UL)
10588 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_STS_Pos (19UL)
10589 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_STS_Msk (0x80000UL)
10590 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Pos (16UL)
10591 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_STS_Msk (0x10000UL)
10592 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Pos (14UL)
10593 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_OV_IS_Msk (0x4000UL)
10594 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Pos (12UL)
10595 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_OV_IS_Msk (0x1000UL)
10596 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_IS_Pos (11UL)
10597 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_OV_IS_Msk (0x800UL)
10598 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Pos (8UL)
10599 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_OV_IS_Msk (0x100UL)
10600 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Pos (6UL)
10601 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD1V5_UV_IS_Msk (0x40UL)
10602 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Pos (4UL)
10603 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDD5V_UV_IS_Msk (0x10UL)
10604 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_IS_Pos (3UL)
10605 #define SCUPM_SYS_SUPPLY_IRQ_STS_VDDEXT_UV_IS_Msk (0x8UL)
10606 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Pos (0UL)
10607 #define SCUPM_SYS_SUPPLY_IRQ_STS_VS_UV_IS_Msk (0x1UL)
10609 #define SCUPM_WDT1_TRIG_SOWCONF_Pos (6UL)
10610 #define SCUPM_WDT1_TRIG_SOWCONF_Msk (0xc0UL)
10611 #define SCUPM_WDT1_TRIG_WDP_SEL_Pos (0UL)
10612 #define SCUPM_WDT1_TRIG_WDP_SEL_Msk (0x3fUL)
10620 #define SSC1_BR_BR_VALUE_Pos (0UL)
10621 #define SSC1_BR_BR_VALUE_Msk (0xffffUL)
10623 #define SSC1_CON_BSY_Pos (28UL)
10624 #define SSC1_CON_BSY_Msk (0x10000000UL)
10625 #define SSC1_CON_BE_Pos (27UL)
10626 #define SSC1_CON_BE_Msk (0x8000000UL)
10627 #define SSC1_CON_PE_Pos (26UL)
10628 #define SSC1_CON_PE_Msk (0x4000000UL)
10629 #define SSC1_CON_RE_Pos (25UL)
10630 #define SSC1_CON_RE_Msk (0x2000000UL)
10631 #define SSC1_CON_TE_Pos (24UL)
10632 #define SSC1_CON_TE_Msk (0x1000000UL)
10633 #define SSC1_CON_BC_Pos (16UL)
10634 #define SSC1_CON_BC_Msk (0xf0000UL)
10635 #define SSC1_CON_EN_Pos (15UL)
10636 #define SSC1_CON_EN_Msk (0x8000UL)
10637 #define SSC1_CON_MS_Pos (14UL)
10638 #define SSC1_CON_MS_Msk (0x4000UL)
10639 #define SSC1_CON_AREN_Pos (12UL)
10640 #define SSC1_CON_AREN_Msk (0x1000UL)
10641 #define SSC1_CON_BEN_Pos (11UL)
10642 #define SSC1_CON_BEN_Msk (0x800UL)
10643 #define SSC1_CON_PEN_Pos (10UL)
10644 #define SSC1_CON_PEN_Msk (0x400UL)
10645 #define SSC1_CON_REN_Pos (9UL)
10646 #define SSC1_CON_REN_Msk (0x200UL)
10647 #define SSC1_CON_TEN_Pos (8UL)
10648 #define SSC1_CON_TEN_Msk (0x100UL)
10649 #define SSC1_CON_LB_Pos (7UL)
10650 #define SSC1_CON_LB_Msk (0x80UL)
10651 #define SSC1_CON_PO_Pos (6UL)
10652 #define SSC1_CON_PO_Msk (0x40UL)
10653 #define SSC1_CON_PH_Pos (5UL)
10654 #define SSC1_CON_PH_Msk (0x20UL)
10655 #define SSC1_CON_HB_Pos (4UL)
10656 #define SSC1_CON_HB_Msk (0x10UL)
10657 #define SSC1_CON_BM_Pos (0UL)
10658 #define SSC1_CON_BM_Msk (0xfUL)
10660 #define SSC1_ISRCLR_BECLR_Pos (11UL)
10661 #define SSC1_ISRCLR_BECLR_Msk (0x800UL)
10662 #define SSC1_ISRCLR_PECLR_Pos (10UL)
10663 #define SSC1_ISRCLR_PECLR_Msk (0x400UL)
10664 #define SSC1_ISRCLR_RECLR_Pos (9UL)
10665 #define SSC1_ISRCLR_RECLR_Msk (0x200UL)
10666 #define SSC1_ISRCLR_TECLR_Pos (8UL)
10667 #define SSC1_ISRCLR_TECLR_Msk (0x100UL)
10669 #define SSC1_PISEL_GIS_Pos (4UL)
10670 #define SSC1_PISEL_GIS_Msk (0x10UL)
10671 #define SSC1_PISEL_MIS_1_Pos (3UL)
10672 #define SSC1_PISEL_MIS_1_Msk (0x8UL)
10673 #define SSC1_PISEL_CIS_Pos (2UL)
10674 #define SSC1_PISEL_CIS_Msk (0x4UL)
10675 #define SSC1_PISEL_SIS_Pos (1UL)
10676 #define SSC1_PISEL_SIS_Msk (0x2UL)
10677 #define SSC1_PISEL_MIS_0_Pos (0UL)
10678 #define SSC1_PISEL_MIS_0_Msk (0x1UL)
10680 #define SSC1_RB_RB_VALUE_Pos (0UL)
10681 #define SSC1_RB_RB_VALUE_Msk (0xffffUL)
10683 #define SSC1_TB_TB_VALUE_Pos (0UL)
10684 #define SSC1_TB_TB_VALUE_Msk (0xffffUL)
10692 #define SSC2_BR_BR_VALUE_Pos (0UL)
10693 #define SSC2_BR_BR_VALUE_Msk (0xffffUL)
10695 #define SSC2_CON_BSY_Pos (28UL)
10696 #define SSC2_CON_BSY_Msk (0x10000000UL)
10697 #define SSC2_CON_BE_Pos (27UL)
10698 #define SSC2_CON_BE_Msk (0x8000000UL)
10699 #define SSC2_CON_PE_Pos (26UL)
10700 #define SSC2_CON_PE_Msk (0x4000000UL)
10701 #define SSC2_CON_RE_Pos (25UL)
10702 #define SSC2_CON_RE_Msk (0x2000000UL)
10703 #define SSC2_CON_TE_Pos (24UL)
10704 #define SSC2_CON_TE_Msk (0x1000000UL)
10705 #define SSC2_CON_BC_Pos (16UL)
10706 #define SSC2_CON_BC_Msk (0xf0000UL)
10707 #define SSC2_CON_EN_Pos (15UL)
10708 #define SSC2_CON_EN_Msk (0x8000UL)
10709 #define SSC2_CON_MS_Pos (14UL)
10710 #define SSC2_CON_MS_Msk (0x4000UL)
10711 #define SSC2_CON_AREN_Pos (12UL)
10712 #define SSC2_CON_AREN_Msk (0x1000UL)
10713 #define SSC2_CON_BEN_Pos (11UL)
10714 #define SSC2_CON_BEN_Msk (0x800UL)
10715 #define SSC2_CON_PEN_Pos (10UL)
10716 #define SSC2_CON_PEN_Msk (0x400UL)
10717 #define SSC2_CON_REN_Pos (9UL)
10718 #define SSC2_CON_REN_Msk (0x200UL)
10719 #define SSC2_CON_TEN_Pos (8UL)
10720 #define SSC2_CON_TEN_Msk (0x100UL)
10721 #define SSC2_CON_LB_Pos (7UL)
10722 #define SSC2_CON_LB_Msk (0x80UL)
10723 #define SSC2_CON_PO_Pos (6UL)
10724 #define SSC2_CON_PO_Msk (0x40UL)
10725 #define SSC2_CON_PH_Pos (5UL)
10726 #define SSC2_CON_PH_Msk (0x20UL)
10727 #define SSC2_CON_HB_Pos (4UL)
10728 #define SSC2_CON_HB_Msk (0x10UL)
10729 #define SSC2_CON_BM_Pos (0UL)
10730 #define SSC2_CON_BM_Msk (0xfUL)
10732 #define SSC2_ISRCLR_BECLR_Pos (11UL)
10733 #define SSC2_ISRCLR_BECLR_Msk (0x800UL)
10734 #define SSC2_ISRCLR_PECLR_Pos (10UL)
10735 #define SSC2_ISRCLR_PECLR_Msk (0x400UL)
10736 #define SSC2_ISRCLR_RECLR_Pos (9UL)
10737 #define SSC2_ISRCLR_RECLR_Msk (0x200UL)
10738 #define SSC2_ISRCLR_TECLR_Pos (8UL)
10739 #define SSC2_ISRCLR_TECLR_Msk (0x100UL)
10741 #define SSC2_PISEL_GIS_Pos (4UL)
10742 #define SSC2_PISEL_GIS_Msk (0x10UL)
10743 #define SSC2_PISEL_MIS_1_Pos (3UL)
10744 #define SSC2_PISEL_MIS_1_Msk (0x8UL)
10745 #define SSC2_PISEL_CIS_Pos (2UL)
10746 #define SSC2_PISEL_CIS_Msk (0x4UL)
10747 #define SSC2_PISEL_SIS_Pos (1UL)
10748 #define SSC2_PISEL_SIS_Msk (0x2UL)
10749 #define SSC2_PISEL_MIS_0_Pos (0UL)
10750 #define SSC2_PISEL_MIS_0_Msk (0x1UL)
10752 #define SSC2_RB_RB_VALUE_Pos (0UL)
10753 #define SSC2_RB_RB_VALUE_Msk (0xffffUL)
10755 #define SSC2_TB_TB_VALUE_Pos (0UL)
10756 #define SSC2_TB_TB_VALUE_Msk (0xffffUL)
10764 #define TIMER2_CNT_T2H_Pos (8UL)
10765 #define TIMER2_CNT_T2H_Msk (0xff00UL)
10766 #define TIMER2_CNT_T2L_Pos (0UL)
10767 #define TIMER2_CNT_T2L_Msk (0xffUL)
10769 #define TIMER2_CON_TF2_Pos (7UL)
10770 #define TIMER2_CON_TF2_Msk (0x80UL)
10771 #define TIMER2_CON_EXF2_Pos (6UL)
10772 #define TIMER2_CON_EXF2_Msk (0x40UL)
10773 #define TIMER2_CON_EXEN2_Pos (3UL)
10774 #define TIMER2_CON_EXEN2_Msk (0x8UL)
10775 #define TIMER2_CON_TR2_Pos (2UL)
10776 #define TIMER2_CON_TR2_Msk (0x4UL)
10777 #define TIMER2_CON_C_T2_Pos (1UL)
10778 #define TIMER2_CON_C_T2_Msk (0x2UL)
10779 #define TIMER2_CON_CP_RL2_Pos (0UL)
10780 #define TIMER2_CON_CP_RL2_Msk (0x1UL)
10782 #define TIMER2_CON1_TF2EN_Pos (1UL)
10783 #define TIMER2_CON1_TF2EN_Msk (0x2UL)
10784 #define TIMER2_CON1_EXF2EN_Pos (0UL)
10785 #define TIMER2_CON1_EXF2EN_Msk (0x1UL)
10787 #define TIMER2_ICLR_TF2CLR_Pos (7UL)
10788 #define TIMER2_ICLR_TF2CLR_Msk (0x80UL)
10789 #define TIMER2_ICLR_EXF2CLR_Pos (6UL)
10790 #define TIMER2_ICLR_EXF2CLR_Msk (0x40UL)
10792 #define TIMER2_MOD_T2REGS_Pos (7UL)
10793 #define TIMER2_MOD_T2REGS_Msk (0x80UL)
10794 #define TIMER2_MOD_T2RHEN_Pos (6UL)
10795 #define TIMER2_MOD_T2RHEN_Msk (0x40UL)
10796 #define TIMER2_MOD_EDGESEL_Pos (5UL)
10797 #define TIMER2_MOD_EDGESEL_Msk (0x20UL)
10798 #define TIMER2_MOD_PREN_Pos (4UL)
10799 #define TIMER2_MOD_PREN_Msk (0x10UL)
10800 #define TIMER2_MOD_T2PRE_Pos (1UL)
10801 #define TIMER2_MOD_T2PRE_Msk (0xeUL)
10802 #define TIMER2_MOD_DCEN_Pos (0UL)
10803 #define TIMER2_MOD_DCEN_Msk (0x1UL)
10805 #define TIMER2_RC_RCH2_Pos (8UL)
10806 #define TIMER2_RC_RCH2_Msk (0xff00UL)
10807 #define TIMER2_RC_RCL2_Pos (0UL)
10808 #define TIMER2_RC_RCL2_Msk (0xffUL)
10816 #define TIMER21_CNT_T2H_Pos (8UL)
10817 #define TIMER21_CNT_T2H_Msk (0xff00UL)
10818 #define TIMER21_CNT_T2L_Pos (0UL)
10819 #define TIMER21_CNT_T2L_Msk (0xffUL)
10821 #define TIMER21_CON_TF2_Pos (7UL)
10822 #define TIMER21_CON_TF2_Msk (0x80UL)
10823 #define TIMER21_CON_EXF2_Pos (6UL)
10824 #define TIMER21_CON_EXF2_Msk (0x40UL)
10825 #define TIMER21_CON_EXEN2_Pos (3UL)
10826 #define TIMER21_CON_EXEN2_Msk (0x8UL)
10827 #define TIMER21_CON_TR2_Pos (2UL)
10828 #define TIMER21_CON_TR2_Msk (0x4UL)
10829 #define TIMER21_CON_C_T2_Pos (1UL)
10830 #define TIMER21_CON_C_T2_Msk (0x2UL)
10831 #define TIMER21_CON_CP_RL2_Pos (0UL)
10832 #define TIMER21_CON_CP_RL2_Msk (0x1UL)
10834 #define TIMER21_CON1_TF2EN_Pos (1UL)
10835 #define TIMER21_CON1_TF2EN_Msk (0x2UL)
10836 #define TIMER21_CON1_EXF2EN_Pos (0UL)
10837 #define TIMER21_CON1_EXF2EN_Msk (0x1UL)
10839 #define TIMER21_ICLR_TF2CLR_Pos (7UL)
10840 #define TIMER21_ICLR_TF2CLR_Msk (0x80UL)
10841 #define TIMER21_ICLR_EXF2CLR_Pos (6UL)
10842 #define TIMER21_ICLR_EXF2CLR_Msk (0x40UL)
10844 #define TIMER21_MOD_T2REGS_Pos (7UL)
10845 #define TIMER21_MOD_T2REGS_Msk (0x80UL)
10846 #define TIMER21_MOD_T2RHEN_Pos (6UL)
10847 #define TIMER21_MOD_T2RHEN_Msk (0x40UL)
10848 #define TIMER21_MOD_EDGESEL_Pos (5UL)
10849 #define TIMER21_MOD_EDGESEL_Msk (0x20UL)
10850 #define TIMER21_MOD_PREN_Pos (4UL)
10851 #define TIMER21_MOD_PREN_Msk (0x10UL)
10852 #define TIMER21_MOD_T2PRE_Pos (1UL)
10853 #define TIMER21_MOD_T2PRE_Msk (0xeUL)
10854 #define TIMER21_MOD_DCEN_Pos (0UL)
10855 #define TIMER21_MOD_DCEN_Msk (0x1UL)
10857 #define TIMER21_RC_RCH2_Pos (8UL)
10858 #define TIMER21_RC_RCH2_Msk (0xff00UL)
10859 #define TIMER21_RC_RCL2_Pos (0UL)
10860 #define TIMER21_RC_RCL2_Msk (0xffUL)
10868 #define UART1_SBUF_VAL_Pos (0UL)
10869 #define UART1_SBUF_VAL_Msk (0xffUL)
10871 #define UART1_SCON_SM0_Pos (7UL)
10872 #define UART1_SCON_SM0_Msk (0x80UL)
10873 #define UART1_SCON_SM1_Pos (6UL)
10874 #define UART1_SCON_SM1_Msk (0x40UL)
10875 #define UART1_SCON_SM2_Pos (5UL)
10876 #define UART1_SCON_SM2_Msk (0x20UL)
10877 #define UART1_SCON_REN_Pos (4UL)
10878 #define UART1_SCON_REN_Msk (0x10UL)
10879 #define UART1_SCON_TB8_Pos (3UL)
10880 #define UART1_SCON_TB8_Msk (0x8UL)
10881 #define UART1_SCON_RB8_Pos (2UL)
10882 #define UART1_SCON_RB8_Msk (0x4UL)
10883 #define UART1_SCON_TI_Pos (1UL)
10884 #define UART1_SCON_TI_Msk (0x2UL)
10885 #define UART1_SCON_RI_Pos (0UL)
10886 #define UART1_SCON_RI_Msk (0x1UL)
10888 #define UART1_SCONCLR_RB8CLR_Pos (2UL)
10889 #define UART1_SCONCLR_RB8CLR_Msk (0x4UL)
10890 #define UART1_SCONCLR_TICLR_Pos (1UL)
10891 #define UART1_SCONCLR_TICLR_Msk (0x2UL)
10892 #define UART1_SCONCLR_RICLR_Pos (0UL)
10893 #define UART1_SCONCLR_RICLR_Msk (0x1UL)
10901 #define UART2_SBUF_VAL_Pos (0UL)
10902 #define UART2_SBUF_VAL_Msk (0xffUL)
10904 #define UART2_SCON_SM0_Pos (7UL)
10905 #define UART2_SCON_SM0_Msk (0x80UL)
10906 #define UART2_SCON_SM1_Pos (6UL)
10907 #define UART2_SCON_SM1_Msk (0x40UL)
10908 #define UART2_SCON_SM2_Pos (5UL)
10909 #define UART2_SCON_SM2_Msk (0x20UL)
10910 #define UART2_SCON_REN_Pos (4UL)
10911 #define UART2_SCON_REN_Msk (0x10UL)
10912 #define UART2_SCON_TB8_Pos (3UL)
10913 #define UART2_SCON_TB8_Msk (0x8UL)
10914 #define UART2_SCON_RB8_Pos (2UL)
10915 #define UART2_SCON_RB8_Msk (0x4UL)
10916 #define UART2_SCON_TI_Pos (1UL)
10917 #define UART2_SCON_TI_Msk (0x2UL)
10918 #define UART2_SCON_RI_Pos (0UL)
10919 #define UART2_SCON_RI_Msk (0x1UL)
10921 #define UART2_SCONCLR_RB8CLR_Pos (2UL)
10922 #define UART2_SCONCLR_RB8CLR_Msk (0x4UL)
10923 #define UART2_SCONCLR_TICLR_Pos (1UL)
10924 #define UART2_SCONCLR_TICLR_Msk (0x2UL)
10925 #define UART2_SCONCLR_RICLR_Pos (0UL)
10926 #define UART2_SCONCLR_RICLR_Msk (0x1UL)
IRQn_Type
Definition: tle985x.h:96
@ PendSV_IRQn
Definition: tle985x.h:102
@ INTISR4_IRQn
Definition: tle985x.h:109
@ INTISR23_IRQn
Definition: tle985x.h:127
@ INTISR10_IRQn
Definition: tle985x.h:115
@ INTISR9_IRQn
Definition: tle985x.h:114
@ INTISR6_IRQn
Definition: tle985x.h:111
@ SVCall_IRQn
Definition: tle985x.h:101
@ Reset_IRQn
Definition: tle985x.h:98
@ INTISR15_IRQn
Definition: tle985x.h:120
@ INTISR14_IRQn
Definition: tle985x.h:119
@ INTISR3_IRQn
Definition: tle985x.h:108
@ INTISR11_IRQn
Definition: tle985x.h:116
@ INTISR0_IRQn
Definition: tle985x.h:105
@ INTISR1_IRQn
Definition: tle985x.h:106
@ INTISR19_IRQn
Definition: tle985x.h:123
@ SysTick_IRQn
Definition: tle985x.h:103
@ INTISR13_IRQn
Definition: tle985x.h:118
@ INTISR22_IRQn
Definition: tle985x.h:126
@ INTISR5_IRQn
Definition: tle985x.h:110
@ INTISR18_IRQn
Definition: tle985x.h:122
@ HardFault_IRQn
Definition: tle985x.h:100
@ INTISR12_IRQn
Definition: tle985x.h:117
@ INTISR17_IRQn
Definition: tle985x.h:121
@ INTISR2_IRQn
Definition: tle985x.h:107
@ NonMaskableInt_IRQn
Definition: tle985x.h:99
@ INTISR21_IRQn
Definition: tle985x.h:125
@ INTISR20_IRQn
Definition: tle985x.h:124
@ INTISR8_IRQn
Definition: tle985x.h:113
@ INTISR7_IRQn
Definition: tle985x.h:112
#define MATH
Definition: tle985x.h:6273
#define SCUPM
Definition: tle985x.h:6278
#define TIMER21
Definition: tle985x.h:6282
#define MF
Definition: tle985x.h:6274
#define PORT
Definition: tle985x.h:6276
#define GPT12E
Definition: tle985x.h:6270
#define SSC2
Definition: tle985x.h:6280
#define HS
Definition: tle985x.h:6271
#define UART2
Definition: tle985x.h:6284
#define UART1
Definition: tle985x.h:6283
#define BDRV
Definition: tle985x.h:6267
#define ADC1
Definition: tle985x.h:6265
#define CCU6
Definition: tle985x.h:6268
#define ADC2
Definition: tle985x.h:6266
#define SSC1
Definition: tle985x.h:6279
#define TIMER2
Definition: tle985x.h:6281
#define PMU
Definition: tle985x.h:6275
#define CPU
Definition: tle985x.h:6269
#define SCU
Definition: tle985x.h:6277
#define LIN
Definition: tle985x.h:6272
#define __OM
Definition: tle985x.h:153
#define __IM
Definition: tle985x.h:150
#define __IOM
Definition: tle985x.h:156
ADC1 (ADC1)
Definition: tle985x.h:196
__IOM uint32_t PP_CH5_LO_IEN
Definition: tle985x.h:1118
__IOM uint32_t PP_CH2_LOW
Definition: tle985x.h:400
__IM uint32_t RESERVED3
Definition: tle985x.h:826
__IOM uint32_t MMODE_1
Definition: tle985x.h:977
__IOM uint32_t CNT_UP_DCH1
Definition: tle985x.h:964
__IOM uint32_t STRTUP_DIS
Definition: tle985x.h:212
__IM uint32_t OF7
Definition: tle985x.h:692
__IM uint32_t PP_CH0_LO_STS
Definition: tle985x.h:1044
__IOM uint32_t IIR_CH9_IEN
Definition: tle985x.h:559
__OM uint32_t DU1UP_SC
Definition: tle985x.h:1243
__IOM uint32_t PP_CH0_UP
Definition: tle985x.h:808
__IOM uint32_t CALOFFS_CH11
Definition: tle985x.h:489
__IOM uint32_t CALGAIN_CH6
Definition: tle985x.h:462
__IM uint32_t SQ_FB
Definition: tle985x.h:220
__IOM uint32_t HYST_UP_PP7
Definition: tle985x.h:954
__IOM uint32_t HYST_LO_PP2
Definition: tle985x.h:855
__IOM uint32_t CNT_UP_PP3
Definition: tle985x.h:924
__OM uint32_t IIR_CH0_ISC
Definition: tle985x.h:577
__IM uint32_t FILT_OUT_CH3
Definition: tle985x.h:640
__IOM uint32_t CALOFFS_CH6
Definition: tle985x.h:460
__IOM uint32_t CH6
Definition: tle985x.h:506
__IOM uint32_t PP_MAP2
Definition: tle985x.h:1169
__IM uint32_t VS_LO_STS
Definition: tle985x.h:1045
__OM uint32_t IIR_CH2_ISC
Definition: tle985x.h:579
__IOM uint32_t CALOFFS_CH8
Definition: tle985x.h:473
__IOM uint32_t PP_CH7_LOW
Definition: tle985x.h:413
__OM uint32_t PP_CH6_LO_ISC
Definition: tle985x.h:1080
__IOM uint32_t FUL_PP_CH5_EN
Definition: tle985x.h:771
__IOM uint32_t CH1
Definition: tle985x.h:501
__IOM uint32_t DU1LO_IS
Definition: tle985x.h:539
__IM uint32_t VF8
Definition: tle985x.h:703
__IOM uint32_t RESET_PP_MAP4
Definition: tle985x.h:1190
__IOM uint32_t ESM_IEN
Definition: tle985x.h:566
__IOM uint32_t CALOFFS_CH0
Definition: tle985x.h:421
__IOM uint32_t FUL_PP_CH3_EN
Definition: tle985x.h:767
__IOM uint32_t PP_CH3_UP
Definition: tle985x.h:811
__IOM uint32_t CH12
Definition: tle985x.h:512
__OM uint32_t IIR_CH4_ISC
Definition: tle985x.h:581
__IM uint32_t VF12
Definition: tle985x.h:1151
__OM uint32_t PP_CH3_LO_ISC
Definition: tle985x.h:1074
__IM uint32_t OF9
Definition: tle985x.h:716
__IOM uint32_t CALOFFS_CH4
Definition: tle985x.h:447
__IOM uint32_t IIR_CH3_IEN
Definition: tle985x.h:553
__IOM uint32_t IIR_CH0_IS
Definition: tle985x.h:521
__IM uint32_t FILT_OUT_CH5
Definition: tle985x.h:664
__IOM uint32_t RESET_PP_MAP0
Definition: tle985x.h:1162
__IOM uint32_t SQ5
Definition: tle985x.h:334
__IOM uint32_t PP_CH3_UP_IS
Definition: tle985x.h:1027
__IOM uint32_t CH3
Definition: tle985x.h:503
__OM uint32_t PP_CH2_UP_ISC
Definition: tle985x.h:1089
__IOM uint32_t HYST_LO_PP7
Definition: tle985x.h:887
__OM uint32_t IIR_CH5_ISC
Definition: tle985x.h:582
__IM uint32_t FILT_OUT_CH13
Definition: tle985x.h:1279
__IOM uint32_t SAMPLE_TIME_HVCH
Definition: tle985x.h:291
__IOM uint32_t CALGAIN_CH1
Definition: tle985x.h:426
__IOM uint32_t CH7
Definition: tle985x.h:507
__IOM uint32_t PP_CH3_UP_IEN
Definition: tle985x.h:1131
__IOM uint32_t IIR_CH0_IEN
Definition: tle985x.h:550
__IOM uint32_t RESET_PP_MAP5
Definition: tle985x.h:1196
__OM uint32_t VS_ISC
Definition: tle985x.h:578
__IOM uint32_t HYST_LO_PP3
Definition: tle985x.h:860
__IOM uint32_t FUL_PP_CH0_EN
Definition: tle985x.h:761
__IOM uint32_t VS_UP_IEN
Definition: tle985x.h:1127
__IM uint32_t SQ_STOP
Definition: tle985x.h:222
__IM uint32_t OF11
Definition: tle985x.h:740
__OM uint32_t VS_UP_ISC
Definition: tle985x.h:1087
__IOM uint32_t CALGAIN_CH11
Definition: tle985x.h:491
__IM uint32_t VF6
Definition: tle985x.h:679
__IM uint32_t OF13
Definition: tle985x.h:1283
__OM uint32_t PP_CH7_UP_ISC
Definition: tle985x.h:1099
__IOM uint32_t PP_MAP3
Definition: tle985x.h:1175
__IM uint32_t VF9
Definition: tle985x.h:715
__OM uint32_t EIM_ISC
Definition: tle985x.h:592
__IOM uint32_t WFR0
Definition: tle985x.h:606
__IOM uint32_t WFR6
Definition: tle985x.h:678
__IOM uint32_t SW_CH_SEL
Definition: tle985x.h:210
__IOM uint32_t PP_CH6_UP_IEN
Definition: tle985x.h:1137
__IOM uint32_t CALOFFS_CH12
Definition: tle985x.h:1265
__IOM uint32_t VS_IEN
Definition: tle985x.h:551
__OM uint32_t PP_CH2_LO_ISC
Definition: tle985x.h:1072
__IOM uint32_t PP_CH3_LOW
Definition: tle985x.h:401
__IOM uint32_t IIR_CH7_IS
Definition: tle985x.h:528
__OM uint32_t IIR_CH6_ISC
Definition: tle985x.h:583
__OM uint32_t DU1LO_ISC
Definition: tle985x.h:595
__IOM uint32_t IIR_CH11_IEN
Definition: tle985x.h:561
__IM uint32_t PP_CH7_LO_STS
Definition: tle985x.h:1051
__IOM uint32_t PP_CH2_LO_IEN
Definition: tle985x.h:1112
__IOM uint32_t PP_CH0_LO_IS
Definition: tle985x.h:1004
__IM uint32_t VF4
Definition: tle985x.h:655
__IOM uint32_t PP_CH1_UP
Definition: tle985x.h:809
__IOM uint32_t MMODE_0
Definition: tle985x.h:976
__IM uint32_t FILT_OUT_CH10
Definition: tle985x.h:724
__IOM uint32_t HYST_UP_PP0
Definition: tle985x.h:912
__IOM uint32_t PP_CH2_UP_IEN
Definition: tle985x.h:1129
__IM uint32_t OF10
Definition: tle985x.h:728
__OM uint32_t PP_CH0_UP_ISC
Definition: tle985x.h:1085
__IOM uint32_t CALGAIN_CH9
Definition: tle985x.h:478
__IOM uint32_t PP_MAP6
Definition: tle985x.h:1199
__IOM uint32_t CH9
Definition: tle985x.h:509
__OM uint32_t PP_CH5_LO_ISC
Definition: tle985x.h:1078
__IOM uint32_t WFR5
Definition: tle985x.h:666
__IOM uint32_t SQ6
Definition: tle985x.h:343
__IM uint32_t FILT_OUT_CH8
Definition: tle985x.h:700
__OM uint32_t PP_CH7_LO_ISC
Definition: tle985x.h:1082
__IOM uint32_t PP_CH3_LO_IEN
Definition: tle985x.h:1114
__IM uint32_t PP_CH3_UP_STS
Definition: tle985x.h:1056
__IM uint32_t PP_CH2_LO_STS
Definition: tle985x.h:1046
__IOM uint32_t FUL_PP_CH7_EN
Definition: tle985x.h:775
__IOM uint32_t IIR_CH12_IEN
Definition: tle985x.h:562
__IOM uint32_t FUL_PP_CH2_EN
Definition: tle985x.h:765
__IOM uint32_t PP_CH5_UP_IS
Definition: tle985x.h:1031
__IOM uint32_t CNT_UP_PP0
Definition: tle985x.h:909
__IOM uint32_t ESM_IS
Definition: tle985x.h:537
__OM uint32_t IIR_CH10_ISC
Definition: tle985x.h:587
__IM uint32_t FILT_OUT_CH1
Definition: tle985x.h:616
__IOM uint32_t PP_MAP7
Definition: tle985x.h:1205
__IOM uint32_t SQ2
Definition: tle985x.h:321
__IOM uint32_t RESET_PP_MAP2
Definition: tle985x.h:1172
__IM uint32_t OF0
Definition: tle985x.h:608
__IOM uint32_t WFR9
Definition: tle985x.h:714
__IOM uint32_t EoC_FAIL
Definition: tle985x.h:289
__IOM uint32_t IIR_CH12_IS
Definition: tle985x.h:533
__IM uint32_t OF6
Definition: tle985x.h:680
__IOM uint32_t HYST_LO_PP1
Definition: tle985x.h:850
__IOM uint32_t IIR_CH4_IEN
Definition: tle985x.h:554
__IM uint32_t OF8
Definition: tle985x.h:704
__IOM uint32_t WFR11
Definition: tle985x.h:738
__IOM uint32_t PP_CH0_LOW
Definition: tle985x.h:398
__IOM uint32_t SQ0
Definition: tle985x.h:310
__IOM uint32_t SQ_CH6_MAP
Definition: tle985x.h:377
__OM uint32_t IIR_CH12_ISC
Definition: tle985x.h:589
__IOM uint32_t CNT_UP_PP1
Definition: tle985x.h:914
__IOM uint32_t DU1LO_IEN
Definition: tle985x.h:568
__IOM uint32_t CALGAIN_CH5
Definition: tle985x.h:452
__OM uint32_t DU1UP_ISC
Definition: tle985x.h:596
__OM uint32_t VS_LO_ISC
Definition: tle985x.h:1070
__IM uint32_t FILT_OUT_CH11
Definition: tle985x.h:736
__IOM uint32_t PP_CH5_UP_IEN
Definition: tle985x.h:1135
__OM uint32_t IIR_CH8_ISC
Definition: tle985x.h:585
__IOM uint32_t WFR2
Definition: tle985x.h:630
__IOM uint32_t DU1UP_IEN
Definition: tle985x.h:569
__IOM uint32_t DU1LO_STS
Definition: tle985x.h:1231
__IOM uint32_t SQ1
Definition: tle985x.h:312
__IM uint32_t VF2
Definition: tle985x.h:631
__IOM uint32_t EN_PP_MAP7
Definition: tle985x.h:1210
__IM uint32_t
Definition: tle985x.h:205
__IM uint32_t PP_CH3_LO_STS
Definition: tle985x.h:1047
__IOM uint32_t HYST_UP_PP2
Definition: tle985x.h:922
__IOM uint32_t MMODE_4
Definition: tle985x.h:980
__IOM uint32_t HYST_UP_PP3
Definition: tle985x.h:927
__IOM uint32_t WFR_EIM
Definition: tle985x.h:1220
__IOM uint32_t PP_CH2_UP
Definition: tle985x.h:810
__IOM uint32_t MMODE_3
Definition: tle985x.h:979
__IOM uint32_t RESET_PP_MAP1
Definition: tle985x.h:1166
__IOM uint32_t FUL_PP_CH6_EN
Definition: tle985x.h:773
__IOM uint32_t CAL_EN
Definition: tle985x.h:276
__IOM uint32_t HYST_UP_PP5
Definition: tle985x.h:944
__IOM uint32_t RESET_PP_MAP3
Definition: tle985x.h:1178
__IOM uint32_t PP_CH7_LO_IS
Definition: tle985x.h:1018
__IM uint32_t CAL_SIGN
Definition: tle985x.h:207
__IOM uint32_t CH10
Definition: tle985x.h:510
__IOM uint32_t CALGAIN_CH3
Definition: tle985x.h:439
__IM uint32_t VF11
Definition: tle985x.h:739
__IM uint32_t RESERVED7
Definition: tle985x.h:1247
__IM uint32_t FILT_OUT_CH4
Definition: tle985x.h:652
__IOM uint32_t CALOFFS_CH10
Definition: tle985x.h:486
__IOM uint32_t SQ12
Definition: tle985x.h:1254
__IOM uint32_t CNT_LO_PP5
Definition: tle985x.h:874
__IOM uint32_t PP_CH3_LO_IS
Definition: tle985x.h:1010
__OM uint32_t PP_CH5_UP_ISC
Definition: tle985x.h:1095
__IOM uint32_t ESM_EN
Definition: tle985x.h:258
__IM uint32_t CHx
Definition: tle985x.h:227
__IOM uint32_t SW_MODE
Definition: tle985x.h:285
__IOM uint32_t FILT_OUT_SEL_13_0
Definition: tle985x.h:301
__IM uint32_t VF0
Definition: tle985x.h:607
__IOM uint32_t SQ_CH5_MAP
Definition: tle985x.h:376
__IOM uint32_t CH8
Definition: tle985x.h:508
__IM uint32_t OF_EIM
Definition: tle985x.h:1222
__IOM uint32_t IIR_CH13_IS
Definition: tle985x.h:534
__IOM uint32_t CNT_LO_DCH1
Definition: tle985x.h:897
__IOM uint32_t CH5
Definition: tle985x.h:505
__IOM uint32_t PP_CH6_LO_IS
Definition: tle985x.h:1016
__IOM uint32_t RESET_PP_MAP6
Definition: tle985x.h:1202
__IOM uint32_t SAMPLE_TIME_LVCH
Definition: tle985x.h:293
__IOM uint32_t DWFR1
Definition: tle985x.h:750
__IM uint32_t OF5
Definition: tle985x.h:668
__IOM uint32_t CALGAIN_CH10
Definition: tle985x.h:488
__IM uint32_t READY
Definition: tle985x.h:206
__IOM uint32_t SOOC
Definition: tle985x.h:203
__IOM uint32_t CALOFFS_CH9
Definition: tle985x.h:476
__IOM uint32_t HYST_LO_PP5
Definition: tle985x.h:877
__IOM uint32_t IIR_CH5_IS
Definition: tle985x.h:526
__IOM uint32_t FUL_PP_CH1_EN
Definition: tle985x.h:763
__IOM uint32_t SQ13
Definition: tle985x.h:1256
__IOM uint32_t HYST_LO_DCH1
Definition: tle985x.h:900
__IM uint32_t EOC
Definition: tle985x.h:209
__IM uint32_t DCH1
Definition: tle985x.h:748
__IOM uint32_t CNT_UP_PP7
Definition: tle985x.h:951
__IOM uint32_t ESM_0
Definition: tle985x.h:252
__IM uint32_t SQx
Definition: tle985x.h:225
__IOM uint32_t ADC1_ESM_TRIG_SEL
Definition: tle985x.h:255
__IOM uint32_t CALGAIN_CH4
Definition: tle985x.h:449
__IOM uint32_t CNT_LO_PP0
Definition: tle985x.h:842
__IOM uint32_t PP_CH6_UP
Definition: tle985x.h:822
__IOM uint32_t CALGAIN_CH8
Definition: tle985x.h:475
__IOM uint32_t IIR_CH2_IS
Definition: tle985x.h:523
__IOM uint32_t HYST_LO_PP6
Definition: tle985x.h:882
__IOM uint32_t CALOFFS_CH7
Definition: tle985x.h:463
__IOM uint32_t SQ11
Definition: tle985x.h:367
__IM uint32_t OF12
Definition: tle985x.h:1152
__IOM uint32_t SQ9
Definition: tle985x.h:356
__IOM uint32_t EN_PP_MAP2
Definition: tle985x.h:1174
__IOM uint32_t EIM_CHx
Definition: tle985x.h:236
__IOM uint32_t EN_PP_MAP1
Definition: tle985x.h:1168
__IM uint32_t ESM_ACTIVE
Definition: tle985x.h:224
__IM uint32_t VF13
Definition: tle985x.h:1282
__IOM uint32_t IIR_CH3_IS
Definition: tle985x.h:524
__IOM uint32_t PP_CH7_UP
Definition: tle985x.h:823
__IOM uint32_t MMODE_5
Definition: tle985x.h:981
__OM uint32_t IIR_CH7_ISC
Definition: tle985x.h:584
__IM uint32_t OF3
Definition: tle985x.h:644
__IOM uint32_t CNT_LO_PP1
Definition: tle985x.h:847
__IOM uint32_t IIR_CH10_IEN
Definition: tle985x.h:560
__IOM uint32_t IIR_CH8_IEN
Definition: tle985x.h:558
__IOM uint32_t HYST_UP_PP6
Definition: tle985x.h:949
__IOM uint32_t PP_CH5_LOW
Definition: tle985x.h:411
__OM uint32_t PP_CH0_LO_ISC
Definition: tle985x.h:1068
__IOM uint32_t PP_CH6_LOW
Definition: tle985x.h:412
__IOM uint32_t IIR_CH10_IS
Definition: tle985x.h:531
__IOM uint32_t SQ7
Definition: tle985x.h:345
__IM uint32_t VF1
Definition: tle985x.h:619
__OM uint32_t PP_CH3_UP_ISC
Definition: tle985x.h:1091
__IOM uint32_t EN_PP_MAP4
Definition: tle985x.h:1192
__IOM uint32_t SQ10
Definition: tle985x.h:365
__IM uint32_t MCM_RDY
Definition: tle985x.h:290
__IOM uint32_t EN_PP_MAP3
Definition: tle985x.h:1180
__IOM uint32_t PP_CH4_LO_IEN
Definition: tle985x.h:1116
__IOM uint32_t PP_CH4_LOW
Definition: tle985x.h:410
__IOM uint32_t DAC_IN
Definition: tle985x.h:785
__IOM uint32_t CALOFFS_CH3
Definition: tle985x.h:437
__IM uint32_t FILT_OUT_CH6
Definition: tle985x.h:676
__IOM uint32_t WFR12
Definition: tle985x.h:1150
__IOM uint32_t SD_FEEDB_ON
Definition: tle985x.h:789
__IM uint32_t VF5
Definition: tle985x.h:667
__IM uint32_t FILT_OUT_CH7
Definition: tle985x.h:688
__IOM uint32_t VS_UP_IS
Definition: tle985x.h:1023
__IOM uint32_t PP_CH7_UP_IEN
Definition: tle985x.h:1139
__IOM uint32_t IIR_CH6_IEN
Definition: tle985x.h:556
__IOM uint32_t EIM_EN
Definition: tle985x.h:239
__IOM uint32_t PP_CH7_UP_IS
Definition: tle985x.h:1035
__OM uint32_t IIR_CH11_ISC
Definition: tle985x.h:588
__OM uint32_t PP_CH6_UP_ISC
Definition: tle985x.h:1097
__IM uint32_t VF10
Definition: tle985x.h:727
__IOM uint32_t MMODE_2
Definition: tle985x.h:978
__IM uint32_t DU1RES_NEG
Definition: tle985x.h:996
__IOM uint32_t VS_IS
Definition: tle985x.h:522
__IOM uint32_t CALGAIN_CH12
Definition: tle985x.h:1267
__IOM uint32_t WFR8
Definition: tle985x.h:702
__IOM uint32_t CALGAIN_CH2
Definition: tle985x.h:436
__IOM uint32_t CH2
Definition: tle985x.h:502
__IM uint32_t PP_CH7_UP_STS
Definition: tle985x.h:1060
__IOM uint32_t PP_MAP4
Definition: tle985x.h:1188
__IOM uint32_t IIR_CH2_IEN
Definition: tle985x.h:552
__OM uint32_t PP_CH4_UP_ISC
Definition: tle985x.h:1093
__IM uint32_t PP_CH6_LO_STS
Definition: tle985x.h:1050
__IOM uint32_t MAX_TIME
Definition: tle985x.h:268
__IOM uint32_t IIR_CH8_IS
Definition: tle985x.h:529
__IOM uint32_t HYST_UP_DCH1
Definition: tle985x.h:967
__IOM uint32_t DCH1_LOW
Definition: tle985x.h:799
__IOM uint32_t CH4
Definition: tle985x.h:504
__OM uint32_t DU1LO_SC
Definition: tle985x.h:1241
__IM uint32_t PP_CH5_LO_STS
Definition: tle985x.h:1049
__IM uint32_t FILT_OUT_CH0
Definition: tle985x.h:604
__IOM uint32_t EIM_IS
Definition: tle985x.h:536
__IM uint32_t OF4
Definition: tle985x.h:656
__IOM uint32_t DU1UP_STS
Definition: tle985x.h:1232
__OM uint32_t IIR_CH9_ISC
Definition: tle985x.h:586
__IOM uint32_t OFFSET_DAC
Definition: tle985x.h:389
__IOM uint32_t reg
Definition: tle985x.h:199
__IOM uint32_t CNT_UP_PP6
Definition: tle985x.h:946
__IOM uint32_t CALGAIN_CH0
Definition: tle985x.h:423
__IM uint32_t PP_CH0_UP_STS
Definition: tle985x.h:1053
__IOM uint32_t RESET_PP_MAP7
Definition: tle985x.h:1208
__IOM uint32_t CNT_LO_PP6
Definition: tle985x.h:879
__IM uint32_t VF7
Definition: tle985x.h:691
__IOM uint32_t VS_LO_IS
Definition: tle985x.h:1006
__IM uint32_t FILT_OUT_CH2
Definition: tle985x.h:628
__IM uint32_t RESERVED5
Definition: tle985x.h:957
__IOM uint32_t PP_CH4_LO_IS
Definition: tle985x.h:1012
__IOM uint32_t CH0
Definition: tle985x.h:500
__IOM uint32_t PP_CH0_LO_IEN
Definition: tle985x.h:1108
__IOM uint32_t PP_MAP5
Definition: tle985x.h:1193
__IOM uint32_t FUL_PP_CH4_EN
Definition: tle985x.h:769
__IOM uint32_t PP_CH5_UP
Definition: tle985x.h:821
__IOM uint32_t PD_N
Definition: tle985x.h:202
__IOM uint32_t CNT_UP_PP2
Definition: tle985x.h:919
__IOM uint32_t CNT_UP_PP5
Definition: tle985x.h:941
__IOM uint32_t EIM_REP
Definition: tle985x.h:238
__IOM uint32_t PP_CH2_LO_IS
Definition: tle985x.h:1008
__IOM uint32_t WFR4
Definition: tle985x.h:654
__IM uint32_t DVF1
Definition: tle985x.h:751
__IOM uint32_t EN_PP_MAP0
Definition: tle985x.h:1164
__IOM uint32_t PP_CH5_LO_IS
Definition: tle985x.h:1014
__IOM uint32_t IIR_CH5_IEN
Definition: tle985x.h:555
__IM uint32_t RESERVED2
Definition: tle985x.h:792
__IOM uint32_t SQ_CH12_MAP
Definition: tle985x.h:379
__IOM uint32_t HYST_UP_PP1
Definition: tle985x.h:917
__IOM uint32_t IIR_CH7_IEN
Definition: tle985x.h:557
__IOM uint32_t PP_CH7_LO_IEN
Definition: tle985x.h:1122
__IOM uint32_t WFR13
Definition: tle985x.h:1281
__IOM uint32_t CALOFFS_CH1
Definition: tle985x.h:424
__IM uint32_t RESERVED6
Definition: tle985x.h:1155
__IM uint32_t VF_EIM
Definition: tle985x.h:1221
__IM uint32_t RESERVED8
Definition: tle985x.h:1259
__IOM uint32_t CALGAIN_CH13
Definition: tle985x.h:1270
__IM uint32_t DOF1
Definition: tle985x.h:752
__IM uint32_t VS_UP_STS
Definition: tle985x.h:1054
__IM uint32_t PP_CH4_LO_STS
Definition: tle985x.h:1048
__IOM uint32_t SQ8
Definition: tle985x.h:354
__OM uint32_t IIR_CH13_ISC
Definition: tle985x.h:590
__IOM uint32_t PP_CH2_UP_IS
Definition: tle985x.h:1025
__IOM uint32_t CNT_LO_PP7
Definition: tle985x.h:884
__IOM uint32_t WFR3
Definition: tle985x.h:642
__IOM uint32_t PP_CH6_LO_IEN
Definition: tle985x.h:1120
__IOM uint32_t CH11
Definition: tle985x.h:511
__IM uint32_t PP_CH2_UP_STS
Definition: tle985x.h:1055
__IOM uint32_t EIM_IEN
Definition: tle985x.h:565
__IOM uint32_t CALOFFS_CH5
Definition: tle985x.h:450
__OM uint32_t PP_CH4_LO_ISC
Definition: tle985x.h:1076
__IOM uint32_t HYST_UP_PP4
Definition: tle985x.h:939
__IOM uint32_t VS_LO_IEN
Definition: tle985x.h:1110
__IOM uint32_t CNT_LO_PP2
Definition: tle985x.h:852
__IOM uint32_t SQ3
Definition: tle985x.h:323
__IOM uint32_t MCM_PD_N
Definition: tle985x.h:284
__IOM uint32_t MMODE_6
Definition: tle985x.h:982
__IOM uint32_t MMODE_D1
Definition: tle985x.h:985
__IOM uint32_t CNT_UP_PP4
Definition: tle985x.h:936
__IOM uint32_t DU1UP_IS
Definition: tle985x.h:541
__IOM uint32_t OFFSET_SHIFT
Definition: tle985x.h:387
__IOM uint32_t IIR_CH9_IS
Definition: tle985x.h:530
__IOM uint32_t PP_CH6_UP_IS
Definition: tle985x.h:1033
__OM uint32_t EoC_FAIL_CLR
Definition: tle985x.h:287
__IM uint32_t PP_CH4_UP_STS
Definition: tle985x.h:1057
__IOM uint32_t PP_CH1_LOW
Definition: tle985x.h:399
__IOM uint32_t CALGAIN_CH7
Definition: tle985x.h:465
__IM uint32_t OF2
Definition: tle985x.h:632
__IM uint32_t RESERVED4
Definition: tle985x.h:890
__IOM uint32_t PP_CH4_UP
Definition: tle985x.h:820
__IOM uint32_t WFR1
Definition: tle985x.h:618
__IOM uint32_t WFR10
Definition: tle985x.h:726
__IOM uint32_t IIR_CH13_IEN
Definition: tle985x.h:563
__IOM uint32_t SQ4
Definition: tle985x.h:332
__IOM uint32_t IIR_CH11_IS
Definition: tle985x.h:532
__IOM uint32_t PP_CH4_UP_IEN
Definition: tle985x.h:1133
__IOM uint32_t CALOFFS_CH13
Definition: tle985x.h:1268
__IOM uint32_t PP_CH0_UP_IEN
Definition: tle985x.h:1125
__IOM uint32_t DCH1_UP
Definition: tle985x.h:833
__IM uint32_t PP_CH5_UP_STS
Definition: tle985x.h:1058
__IOM uint32_t ADC1_EIM_TRIG_SEL
Definition: tle985x.h:242
__IOM uint32_t CALOFFS_CH2
Definition: tle985x.h:434
__IOM uint32_t PP_CH0_UP_IS
Definition: tle985x.h:1021
__IOM uint32_t SOC_JITTER
Definition: tle985x.h:787
__IOM uint32_t PP_CH4_UP_IS
Definition: tle985x.h:1029
__IOM uint32_t IIR_CH4_IS
Definition: tle985x.h:525
__IOM uint32_t SOS
Definition: tle985x.h:204
__IM uint32_t PP_CH6_UP_STS
Definition: tle985x.h:1059
__IOM uint32_t CNT_LO_PP3
Definition: tle985x.h:857
__IOM uint32_t DU1_EN
Definition: tle985x.h:994
__IOM uint32_t ESM_STS
Definition: tle985x.h:260
__IOM uint32_t EN_PP_MAP6
Definition: tle985x.h:1204
__IOM uint32_t CH13
Definition: tle985x.h:513
__IOM uint32_t EN_PP_MAP5
Definition: tle985x.h:1198
__IM uint32_t EIM_ACTIVE
Definition: tle985x.h:223
__IOM uint32_t MMODE_7
Definition: tle985x.h:983
__IOM uint32_t CNT_LO_PP4
Definition: tle985x.h:869
__IM uint32_t FILT_OUT_CH12
Definition: tle985x.h:1148
__IM uint32_t RESERVED9
Definition: tle985x.h:1273
__IM uint32_t FILT_OUT_CH9
Definition: tle985x.h:712
__IOM uint32_t WFR7
Definition: tle985x.h:690
__IM uint32_t FILT_OUT_EIM
Definition: tle985x.h:1218
__IOM uint32_t HYST_LO_PP4
Definition: tle985x.h:872
__IOM uint32_t IIR_CH6_IS
Definition: tle985x.h:527
__IM uint32_t VF3
Definition: tle985x.h:643
__IOM uint32_t HYST_LO_PP0
Definition: tle985x.h:845
__OM uint32_t IIR_CH3_ISC
Definition: tle985x.h:580
__IM uint32_t OF1
Definition: tle985x.h:620
__OM uint32_t ESM_ISC
Definition: tle985x.h:593
ADC2 (ADC2)
Definition: tle985x.h:1299
__IOM uint32_t MSEL_Ch2
Definition: tle985x.h:1775
__IM uint32_t RESERVED3
Definition: tle985x.h:1599
__IOM uint32_t HYST_UP_CH2
Definition: tle985x.h:1729
__IOM uint32_t THUP_CH7
Definition: tle985x.h:1649
__IOM uint32_t HYST_UP_CH3
Definition: tle985x.h:1733
__IOM uint32_t OFFS_CH3
Definition: tle985x.h:1452
__IM uint32_t SQ_FB
Definition: tle985x.h:1318
__IOM uint32_t OFFS_CH5
Definition: tle985x.h:1465
__IOM uint32_t GAIN_CH2
Definition: tle985x.h:1451
__IOM uint32_t HYST_UP_CH1
Definition: tle985x.h:1725
__IOM uint32_t GAIN_CH7
Definition: tle985x.h:1480
__IOM uint32_t CNT_UP_CH5
Definition: tle985x.h:1745
__IOM uint32_t IN_MUX_SEL
Definition: tle985x.h:1310
__IOM uint32_t GAIN_CH8
Definition: tle985x.h:1490
__IOM uint32_t HYST_UP_CH6
Definition: tle985x.h:1751
__IOM uint32_t MSEL_Ch6
Definition: tle985x.h:1779
__IOM uint32_t SQ5
Definition: tle985x.h:1397
__IOM uint32_t MSEL_Ch8
Definition: tle985x.h:1781
__IOM uint32_t A_CH3
Definition: tle985x.h:1501
__IOM uint32_t CHx_SEL
Definition: tle985x.h:1334
__IOM uint32_t THLO_CH4
Definition: tle985x.h:1616
__IM uint32_t SQ_STOP
Definition: tle985x.h:1320
__IOM uint32_t A_CH7
Definition: tle985x.h:1505
__IOM uint32_t THLO_CH8
Definition: tle985x.h:1627
__IOM uint32_t CNT_UP_CH6
Definition: tle985x.h:1749
__IM uint32_t OUT_CH2
Definition: tle985x.h:1531
__IOM uint32_t THUP_CH6
Definition: tle985x.h:1648
__IOM uint32_t THUP_CH1
Definition: tle985x.h:1636
__IOM uint32_t CNT_LO_CH1
Definition: tle985x.h:1669
__IOM uint32_t THUP_CH3
Definition: tle985x.h:1638
__IOM uint32_t THLO_CH2
Definition: tle985x.h:1607
__IOM uint32_t THLO_CH1
Definition: tle985x.h:1606
__IOM uint32_t THUP_CH2
Definition: tle985x.h:1637
__IOM uint32_t SEL
Definition: tle985x.h:1339
__IOM uint32_t A_CH1
Definition: tle985x.h:1499
__IOM uint32_t A_CH2
Definition: tle985x.h:1500
__IOM uint32_t THUP_CH4
Definition: tle985x.h:1646
__IOM uint32_t SQ6
Definition: tle985x.h:1417
__IOM uint32_t UPLOEN_Ch3
Definition: tle985x.h:1591
__IOM uint32_t GAIN_CH1
Definition: tle985x.h:1441
__IOM uint32_t SQ2
Definition: tle985x.h:1406
__IOM uint32_t CNT_UP_CH4
Definition: tle985x.h:1741
__IOM uint32_t MSEL_Ch5
Definition: tle985x.h:1778
__IOM uint32_t UPLOEN_Ch7
Definition: tle985x.h:1595
__IOM uint32_t SQ0
Definition: tle985x.h:1384
__IOM uint32_t THUP_CH0
Definition: tle985x.h:1635
__IOM uint32_t MSEL_Ch3
Definition: tle985x.h:1776
__IOM uint32_t CNT_UP_CH1
Definition: tle985x.h:1723
__IOM uint32_t OFFS_CH7
Definition: tle985x.h:1478
__IOM uint32_t HYST_LO_CH2
Definition: tle985x.h:1675
__IOM uint32_t SQ1
Definition: tle985x.h:1386
__IM uint32_t
Definition: tle985x.h:1306
__IOM uint32_t GAIN_CH5
Definition: tle985x.h:1467
__IOM uint32_t CNT_UP_CH3
Definition: tle985x.h:1731
__IOM uint32_t OFFS_CH2
Definition: tle985x.h:1449
__IOM uint32_t GAIN_CH4
Definition: tle985x.h:1464
__IOM uint32_t A_CH4
Definition: tle985x.h:1502
__IOM uint32_t THLO_CH0
Definition: tle985x.h:1605
__IOM uint32_t HYST_LO_CH7
Definition: tle985x.h:1701
__IM uint32_t CHx
Definition: tle985x.h:1325
__IOM uint32_t HYST_LO_CH6
Definition: tle985x.h:1697
__IOM uint32_t CNT_LO_CH6
Definition: tle985x.h:1695
__IOM uint32_t REP
Definition: tle985x.h:1336
__IM uint32_t OUT_CH4
Definition: tle985x.h:1547
__IOM uint32_t HYST_LO_CH5
Definition: tle985x.h:1693
__IOM uint32_t OFFS_CH1
Definition: tle985x.h:1439
__IM uint32_t READY
Definition: tle985x.h:1791
__IM uint32_t OUT_CH6
Definition: tle985x.h:1563
__IOM uint32_t HYST_LO_CH1
Definition: tle985x.h:1671
__IM uint32_t EOC
Definition: tle985x.h:1308
__IOM uint32_t CNT_LO_CH2
Definition: tle985x.h:1673
__IOM uint32_t A_CH8
Definition: tle985x.h:1506
__IM uint32_t SQx
Definition: tle985x.h:1323
__IOM uint32_t CNT_UP_CH0
Definition: tle985x.h:1719
__IOM uint32_t A_CH5
Definition: tle985x.h:1503
__IOM uint32_t THLO_CH5
Definition: tle985x.h:1617
__IOM uint32_t GAIN_CH0
Definition: tle985x.h:1438
__IOM uint32_t MSEL_Ch1
Definition: tle985x.h:1774
__IOM uint32_t HYST_UP_CH8
Definition: tle985x.h:1765
__IOM uint32_t SAMPLE_TIME_int
Definition: tle985x.h:1367
__IOM uint32_t CNT_LO_CH4
Definition: tle985x.h:1687
__IOM uint32_t FILT_OUT_SEL_8_0
Definition: tle985x.h:1375
__IM uint32_t OUT_CH5
Definition: tle985x.h:1555
__IOM uint32_t SQ7
Definition: tle985x.h:1419
__IOM uint32_t HYST_LO_CH4
Definition: tle985x.h:1689
__IM uint32_t MCM_RDY
Definition: tle985x.h:1366
__IOM uint32_t CNT_UP_CH8
Definition: tle985x.h:1763
__IOM uint32_t OFFS_CH6
Definition: tle985x.h:1475
__IM uint32_t RESERVED
Definition: tle985x.h:1342
__IOM uint32_t UPLOEN_Ch5
Definition: tle985x.h:1593
__IOM uint32_t UPLOEN_Ch1
Definition: tle985x.h:1589
__IOM uint32_t A_CH0
Definition: tle985x.h:1498
__IOM uint32_t UPLOEN_Ch2
Definition: tle985x.h:1590
__IOM uint32_t THLO_CH6
Definition: tle985x.h:1618
__IOM uint32_t CNT_UP_CH7
Definition: tle985x.h:1753
__IOM uint32_t MSEL_Ch0
Definition: tle985x.h:1773
__IOM uint32_t UPLOEN_Ch8
Definition: tle985x.h:1596
__IOM uint32_t THUP_CH5
Definition: tle985x.h:1647
__IOM uint32_t MAX_TIME
Definition: tle985x.h:1348
__IM uint32_t OUT_CH8
Definition: tle985x.h:1579
__IOM uint32_t reg
Definition: tle985x.h:1302
__IOM uint32_t THUP_CH8
Definition: tle985x.h:1657
__IOM uint32_t CNT_UP_CH2
Definition: tle985x.h:1727
__IM uint32_t OUT_CH7
Definition: tle985x.h:1571
__IOM uint32_t EN
Definition: tle985x.h:1337
__IOM uint32_t OFFS_CH8
Definition: tle985x.h:1488
__IOM uint32_t CNT_LO_CH5
Definition: tle985x.h:1691
__IOM uint32_t CNT_LO_CH0
Definition: tle985x.h:1665
__IOM uint32_t HYST_LO_CH0
Definition: tle985x.h:1667
__IOM uint32_t GAIN_CH3
Definition: tle985x.h:1454
__IOM uint32_t PD_N
Definition: tle985x.h:1305
__IM uint32_t OUT_CH1
Definition: tle985x.h:1523
__IM uint32_t OUT_CH3
Definition: tle985x.h:1539
__IOM uint32_t THLO_CH3
Definition: tle985x.h:1608
__IM uint32_t RESERVED2
Definition: tle985x.h:1582
__IOM uint32_t HYST_UP_CH4
Definition: tle985x.h:1743
__IOM uint32_t A_CH6
Definition: tle985x.h:1504
__IOM uint32_t SQ8
Definition: tle985x.h:1428
__IOM uint32_t CNT_LO_CH8
Definition: tle985x.h:1709
__IOM uint32_t UPLOEN_Ch4
Definition: tle985x.h:1592
__IOM uint32_t MSEL_Ch4
Definition: tle985x.h:1777
__IOM uint32_t HYST_LO_CH8
Definition: tle985x.h:1711
__IOM uint32_t CALIB_EN_8_0
Definition: tle985x.h:1356
__IOM uint32_t SQ3
Definition: tle985x.h:1408
__IOM uint32_t MCM_PD_N
Definition: tle985x.h:1364
__IOM uint32_t HYST_UP_CH7
Definition: tle985x.h:1755
__IOM uint32_t CNT_LO_CH7
Definition: tle985x.h:1699
__IOM uint32_t HYST_LO_CH3
Definition: tle985x.h:1679
__IOM uint32_t CNT_LO_CH3
Definition: tle985x.h:1677
__IM uint32_t RESERVED1
Definition: tle985x.h:1509
__IOM uint32_t MSEL_Ch7
Definition: tle985x.h:1780
__IOM uint32_t OFFS_CH0
Definition: tle985x.h:1436
__IOM uint32_t SQ4
Definition: tle985x.h:1395
__IOM uint32_t OFFS_CH4
Definition: tle985x.h:1462
__IOM uint32_t UPLOEN_Ch0
Definition: tle985x.h:1588
__IM uint32_t OUT_CH0
Definition: tle985x.h:1515
__IOM uint32_t SOS
Definition: tle985x.h:1307
__IOM uint32_t UPLOEN_Ch6
Definition: tle985x.h:1594
__IOM uint32_t HYST_UP_CH5
Definition: tle985x.h:1747
__IOM uint32_t THLO_CH7
Definition: tle985x.h:1619
__IM uint32_t EIM_ACTIVE
Definition: tle985x.h:1321
__IOM uint32_t HYST_UP_CH0
Definition: tle985x.h:1721
__IOM uint32_t GAIN_CH6
Definition: tle985x.h:1477
BDRV (BDRV)
Definition: tle985x.h:1807
__IOM uint32_t VCP_UPTH_IEN
Definition: tle985x.h:2072
__IM uint32_t HB2_I1ONVAL
Definition: tle985x.h:2447
__IOM uint32_t HB1_ASEQ_IEN
Definition: tle985x.h:2578
__IOM uint32_t LS1_PWM
Definition: tle985x.h:1814
__IM uint32_t HB1_T2OFFCNT
Definition: tle985x.h:2430
__IOM uint32_t DRVx_VCPLO_SDEN
Definition: tle985x.h:1940
__IOM uint32_t HB2_T1ON
Definition: tle985x.h:2216
__OM uint32_t VCP_OTSD_SC
Definition: tle985x.h:2050
__IOM uint32_t HB1_SEQMAP
Definition: tle985x.h:1897
__IOM uint32_t HB1_ASEQ_IS
Definition: tle985x.h:2511
__IOM uint32_t I1ONMAX
Definition: tle985x.h:2389
__IOM uint32_t HB1OPTONACT
Definition: tle985x.h:2279
__IM uint32_t HB1ONMF
Definition: tle985x.h:2314
__IOM uint32_t DITH_LOWER
Definition: tle985x.h:1959
__IOM uint32_t HB1_I3OFF
Definition: tle985x.h:2108
__IOM uint32_t HB1_ONVALVF
Definition: tle985x.h:2415
__IOM uint32_t T1OFFMIN
Definition: tle985x.h:2343
__IOM uint32_t HB1_T3OFF
Definition: tle985x.h:2089
__IOM uint32_t LS1_DS_IEN
Definition: tle985x.h:2581
__IOM uint32_t HS2_DCS_EN
Definition: tle985x.h:1838
__IOM uint32_t HB1AF_TDICLMPOFF
Definition: tle985x.h:2168
__IOM uint32_t HB2_T4ON
Definition: tle985x.h:2221
__IOM uint32_t HB2_I2ON
Definition: tle985x.h:2233
__IOM uint32_t LS2_PWM
Definition: tle985x.h:1821
__IOM uint32_t HB1AF_TDICLMPON
Definition: tle985x.h:2170
__IOM uint32_t HB2_T3ON
Definition: tle985x.h:2219
__OM uint32_t VSD_LOTH_ISC
Definition: tle985x.h:2045
__OM uint32_t HB1_ASEQ_ISC
Definition: tle985x.h:2544
__IOM uint32_t HB1ASMOFFEN
Definition: tle985x.h:2276
__IOM uint32_t LS2_DS_IS
Definition: tle985x.h:2519
__IOM uint32_t SEQ_ERR_IEN
Definition: tle985x.h:2600
__IOM uint32_t HB2AF_ICLMPON
Definition: tle985x.h:1980
__IOM uint32_t LS2_OC_DIS
Definition: tle985x.h:1826
__IOM uint32_t VSD_LOTH_STS
Definition: tle985x.h:2025
__IOM uint32_t HS1_DCS_EN
Definition: tle985x.h:1830
__IOM uint32_t HB1OPTOFFACT
Definition: tle985x.h:2280
__IOM uint32_t SEQ_ERR_IS
Definition: tle985x.h:2536
__IOM uint32_t HB2_T3OFF
Definition: tle985x.h:2184
__IOM uint32_t HB2ASMONEN
Definition: tle985x.h:2286
__IOM uint32_t I1OFFMIN
Definition: tle985x.h:2363
__IOM uint32_t HB1_ICLMPOFF
Definition: tle985x.h:1989
__IM uint32_t HB1I1OFFMIN
Definition: tle985x.h:2307
__IOM uint32_t DITH_UPPER
Definition: tle985x.h:1961
__OM uint32_t VCP_OTSD_ISC
Definition: tle985x.h:2038
__IM uint32_t HB1I1ONMAX
Definition: tle985x.h:2309
__IM uint32_t HB2I1ONMAX
Definition: tle985x.h:2320
__IOM uint32_t LS1_EN
Definition: tle985x.h:1813
__IOM uint32_t HB1_I4OFF
Definition: tle985x.h:2111
__IOM uint32_t CPLOPWRM_EN
Definition: tle985x.h:1947
__IM uint32_t HB2_T1OFFCNT
Definition: tle985x.h:2464
__IOM uint32_t VCP_UPTH_IS
Definition: tle985x.h:2012
__IOM uint32_t LS2_OC_IS
Definition: tle985x.h:2523
__IOM uint32_t LS1_OC_IEN
Definition: tle985x.h:2584
__IM uint32_t HS2_SUPERR_STS
Definition: tle985x.h:1840
__OM uint32_t LS2_DS_SC
Definition: tle985x.h:2555
__IOM uint32_t HB1AF_IOFF
Definition: tle985x.h:2155
__IOM uint32_t HB2AF_ION
Definition: tle985x.h:2253
__IM uint32_t LS2_SUPERR_STS
Definition: tle985x.h:1824
__IM uint32_t RESERVED10
Definition: tle985x.h:2493
__IOM uint32_t VSD_LOTH_IS
Definition: tle985x.h:2014
__IOM uint32_t HB1_T4ON
Definition: tle985x.h:2126
__IOM uint32_t LS2_OC_IEN
Definition: tle985x.h:2589
__IOM uint32_t HSDRV_DS_TFILT_SEL
Definition: tle985x.h:1918
__IOM uint32_t LS1DRV_OCSDN_DIS
Definition: tle985x.h:1915
__IOM uint32_t LS2DRV_OCSDN_DIS
Definition: tle985x.h:1916
__IM uint32_t HB1_T1OFFCNT
Definition: tle985x.h:2425
__IOM uint32_t HB1_T3ON
Definition: tle985x.h:2124
__IM uint32_t HS1_SUPERR_STS
Definition: tle985x.h:1832
__IM uint32_t HB1_T12ONCNT
Definition: tle985x.h:2406
__OM uint32_t VCP_LOTH1_SC
Definition: tle985x.h:2052
__IOM uint32_t HB1MFERRCNT
Definition: tle985x.h:2486
__IOM uint32_t HB2AF_TDICLMPOFF
Definition: tle985x.h:2263
__IOM uint32_t HS2_DS_STS
Definition: tle985x.h:2533
__IM uint32_t HB2I1OFFMAX
Definition: tle985x.h:2316
__IOM uint32_t VCP9V_SET
Definition: tle985x.h:1948
__IOM uint32_t VCP14_15V_SEL
Definition: tle985x.h:1950
__IOM uint32_t HB2_ONVALVF
Definition: tle985x.h:2454
__OM uint32_t VCP_UPTH_SC
Definition: tle985x.h:2054
__IOM uint32_t HB2_T1OFF
Definition: tle985x.h:2181
__IOM uint32_t HB2_I1OFF
Definition: tle985x.h:2197
__IOM uint32_t T12ONMIN
Definition: tle985x.h:2334
__IM uint32_t DLY_DIAG_TIM
Definition: tle985x.h:1855
__OM uint32_t HS1_OC_ISC
Definition: tle985x.h:2563
__IOM uint32_t DRVx_VSDUP_DIS
Definition: tle985x.h:1945
__IOM uint32_t HB2_I1ON
Definition: tle985x.h:2230
__OM uint32_t VCP_UPTH_ISC
Definition: tle985x.h:2043
__IOM uint32_t HS2DRV_FDISCHG_DIS
Definition: tle985x.h:1921
__IOM uint32_t HS1_PWM
Definition: tle985x.h:1828
__IOM uint32_t LS2_SRC_SEL
Definition: tle985x.h:1885
__IM uint32_t HB1T12ONMIN
Definition: tle985x.h:2310
__IOM uint32_t LS2DRV_FDISCHG_DIS
Definition: tle985x.h:1913
__IOM uint32_t HS2_SRC_SEL
Definition: tle985x.h:1889
__IOM uint32_t HB2OPTOFFACT
Definition: tle985x.h:2292
__IOM uint32_t HB2AF_ICLMPOFF
Definition: tle985x.h:1996
__IOM uint32_t LS2_ON
Definition: tle985x.h:1822
__OM uint32_t VSD_UPTH_SC
Definition: tle985x.h:2058
__IOM uint32_t HB1ASMONEN
Definition: tle985x.h:2275
__IOM uint32_t HB1_ICLMPON
Definition: tle985x.h:1973
__IOM uint32_t HB2_ICLMPOFF
Definition: tle985x.h:1991
__IOM uint32_t HS1_EN
Definition: tle985x.h:1827
__IOM uint32_t HB2_T4OFF
Definition: tle985x.h:2187
__IM uint32_t HB1T1OFFMIN
Definition: tle985x.h:2306
__IOM uint32_t HB2_ASEQ_IEN
Definition: tle985x.h:2579
__IOM uint32_t HB1T12ONERRCNT
Definition: tle985x.h:2485
__IOM uint32_t F_CP
Definition: tle985x.h:1962
__IM uint32_t HB2T12ONMIN
Definition: tle985x.h:2321
__IOM uint32_t DRV_CCP_TIMSEL
Definition: tle985x.h:1871
__IOM uint32_t HB2OFFSEQCNF
Definition: tle985x.h:1853
__IM uint32_t
Definition: tle985x.h:1816
__IOM uint32_t VCP_LOTH1_STS
Definition: tle985x.h:2021
__OM uint32_t DLY_DIAG_SCLR
Definition: tle985x.h:1856
__IOM uint32_t HB2_I2OFF
Definition: tle985x.h:2200
__IOM uint32_t HB2_ICLMPON
Definition: tle985x.h:1975
__IOM uint32_t HS1_ON
Definition: tle985x.h:1829
__IM uint32_t RESERVED7
Definition: tle985x.h:2243
__IOM uint32_t HB1_I1ON
Definition: tle985x.h:2135
__OM uint32_t HB2_ASEQ_ISC
Definition: tle985x.h:2545
__OM uint32_t LS1_DS_SC
Definition: tle985x.h:2549
__IOM uint32_t LS_HS_BT_TFILT_SEL
Definition: tle985x.h:1908
__OM uint32_t HB2_OFFVALVF_CLR
Definition: tle985x.h:2474
__IM uint32_t HB2I1OFFMIN
Definition: tle985x.h:2318
__IOM uint32_t HB1T1OFFADDDLY
Definition: tle985x.h:2344
__IOM uint32_t HS1_SRC_SEL
Definition: tle985x.h:1887
__IOM uint32_t VCP_OTW_IS
Definition: tle985x.h:2006
__IOM uint32_t HB1_I4ON
Definition: tle985x.h:2144
__OM uint32_t LS2_OC_ISC
Definition: tle985x.h:2557
__IOM uint32_t COMPENS_LS
Definition: tle985x.h:2502
__IOM uint32_t DLY_DIAG_DIRSEL
Definition: tle985x.h:1859
__IOM uint32_t DRV_CCP_DIS
Definition: tle985x.h:1875
__IOM uint32_t CP_STAGE_SEL
Definition: tle985x.h:1951
__IM uint32_t HB1T1OFFMAX
Definition: tle985x.h:2304
__OM uint32_t VSD_UPTH_ISC
Definition: tle985x.h:2047
__IOM uint32_t HS2_PWM
Definition: tle985x.h:1836
__IOM uint32_t HS2_EN
Definition: tle985x.h:1835
__IM uint32_t HB1_T2MERR
Definition: tle985x.h:2432
__IOM uint32_t HB2AF_IOFF
Definition: tle985x.h:2250
__IOM uint32_t HS2_ON
Definition: tle985x.h:1837
__IOM uint32_t LS1_DS_STS
Definition: tle985x.h:2516
__IOM uint32_t CPLOW_TFILT_SEL
Definition: tle985x.h:1926
__IM uint32_t HB1I1OFFMAX
Definition: tle985x.h:2305
__IOM uint32_t HB1_T1OFF
Definition: tle985x.h:2086
__IOM uint32_t HS2_DS_IS
Definition: tle985x.h:2531
__IOM uint32_t VSD_UPTH_STS
Definition: tle985x.h:2027
__IOM uint32_t HB2ONSEQCNF
Definition: tle985x.h:1851
__IM uint32_t HB1_I1ONVAL
Definition: tle985x.h:2408
__IOM uint32_t HB2_ASEQ_IS
Definition: tle985x.h:2512
__IOM uint32_t DRV_CCP_TMUL
Definition: tle985x.h:1873
__OM uint32_t VCP_OTW_SC
Definition: tle985x.h:2048
__IOM uint32_t VCP_OTSD_STS
Definition: tle985x.h:2019
__IOM uint32_t CPCLKDIS_SET
Definition: tle985x.h:1964
__IM uint32_t HB2_T2OFFCNT
Definition: tle985x.h:2469
__IOM uint32_t HB2_T2ON
Definition: tle985x.h:2217
__IOM uint32_t HS1_OC_DIS
Definition: tle985x.h:1834
__IOM uint32_t HB2_OFFVALVF
Definition: tle985x.h:2473
__IOM uint32_t VSD_LOTH_IEN
Definition: tle985x.h:2074
__IOM uint32_t CP_RDY_EN
Definition: tle985x.h:1937
__IOM uint32_t HS1_DS_STS
Definition: tle985x.h:2527
__IOM uint32_t T12ONMAX
Definition: tle985x.h:2371
__IOM uint32_t VCP_LOTH1_IEN
Definition: tle985x.h:2070
__IOM uint32_t VTHVCP_TRIM
Definition: tle985x.h:1949
__OM uint32_t HS1_DS_SC
Definition: tle985x.h:2561
__IOM uint32_t CPCLK_EN
Definition: tle985x.h:1963
__IOM uint32_t VCP_OTSD_IEN
Definition: tle985x.h:2068
__IM uint32_t HB2T1OFFMAX
Definition: tle985x.h:2315
__IOM uint32_t HS1_DS_IEN
Definition: tle985x.h:2591
__IOM uint32_t HB1_I2ON
Definition: tle985x.h:2138
__IM uint32_t DLY_DIAG_STS
Definition: tle985x.h:1857
__IOM uint32_t HB1_I2OFF
Definition: tle985x.h:2105
__IOM uint32_t I1OFFMAX
Definition: tle985x.h:2398
__IM uint32_t HB1OFFMF
Definition: tle985x.h:2313
__IOM uint32_t HB1_I1OFF
Definition: tle985x.h:2102
__IOM uint32_t HB1_T1ON
Definition: tle985x.h:2121
__IOM uint32_t LS2_DS_STS
Definition: tle985x.h:2521
__IOM uint32_t HB1OFFSEQCNF
Definition: tle985x.h:1852
__IM uint32_t RESERVED
Definition: tle985x.h:1902
__IOM uint32_t LS1_OC_DIS
Definition: tle985x.h:1819
__IOM uint32_t HB2_SEQMAP
Definition: tle985x.h:1899
__OM uint32_t HB1_ONVALVF_CLR
Definition: tle985x.h:2416
__IOM uint32_t LS1_ON
Definition: tle985x.h:1815
__IM uint32_t HB1_T3ONCNT
Definition: tle985x.h:2411
__IOM uint32_t HS2_OC_IEN
Definition: tle985x.h:2599
__IM uint32_t HB1_T3MERR
Definition: tle985x.h:2413
__IM uint32_t HB2_T3MERR
Definition: tle985x.h:2452
__IOM uint32_t HS1_OC_IEN
Definition: tle985x.h:2594
__IOM uint32_t HB1_T4OFF
Definition: tle985x.h:2092
__IOM uint32_t DLY_DIAG_CHSEL
Definition: tle985x.h:1858
__IOM uint32_t HB1AF_ION
Definition: tle985x.h:2158
__IOM uint32_t HB2ASMOFFEN
Definition: tle985x.h:2288
__IOM uint32_t HB2_I3OFF
Definition: tle985x.h:2203
__IM uint32_t LS1_SUPERR_STS
Definition: tle985x.h:1817
__OM uint32_t HS1_DS_ISC
Definition: tle985x.h:2559
__IM uint32_t HB1I1ONMIN
Definition: tle985x.h:2311
__IOM uint32_t HB1ONSEQCNF
Definition: tle985x.h:1850
__IOM uint32_t reg
Definition: tle985x.h:1810
__IOM uint32_t LS1_DS_IS
Definition: tle985x.h:2514
__OM uint32_t LS1_DS_ISC
Definition: tle985x.h:2547
__OM uint32_t HB1_OFFVALVF_CLR
Definition: tle985x.h:2435
__IOM uint32_t HB2_I4OFF
Definition: tle985x.h:2206
__IOM uint32_t HB1ONHYSTEN
Definition: tle985x.h:2281
__IOM uint32_t HS1DRV_FDISCHG_DIS
Definition: tle985x.h:1920
__IOM uint32_t LS2_DS_IEN
Definition: tle985x.h:2586
__IM uint32_t RESERVED5
Definition: tle985x.h:2148
__OM uint32_t VCP_OTW_ISC
Definition: tle985x.h:2035
__IOM uint32_t HB2AF_TDICLMPON
Definition: tle985x.h:2265
__IOM uint32_t HB2T1OFFADDDLY
Definition: tle985x.h:2345
__IOM uint32_t T1OFFMAX
Definition: tle985x.h:2380
__IM uint32_t HB1T12ONMAX
Definition: tle985x.h:2308
__IOM uint32_t HS2_DS_IEN
Definition: tle985x.h:2596
__OM uint32_t HB2_ONVALVF_CLR
Definition: tle985x.h:2455
__OM uint32_t LS2_DS_ISC
Definition: tle985x.h:2553
__IOM uint32_t COMPENS_HS
Definition: tle985x.h:2500
__IOM uint32_t I1ONMIN
Definition: tle985x.h:2354
__IOM uint32_t VCP_OTSD_IS
Definition: tle985x.h:2008
__OM uint32_t LS1_OC_ISC
Definition: tle985x.h:2551
__OM uint32_t VCP_LOTH1_ISC
Definition: tle985x.h:2041
__IM uint32_t HB2OFFMF
Definition: tle985x.h:2324
__IM uint32_t HB2_T2MERR
Definition: tle985x.h:2471
__IOM uint32_t CP_EN
Definition: tle985x.h:1935
__OM uint32_t HS2_OC_ISC
Definition: tle985x.h:2569
__IOM uint32_t HB1AF_ICLMPON
Definition: tle985x.h:1977
__IOM uint32_t DRVx_VSDLO_DIS
Definition: tle985x.h:1943
__IM uint32_t RESERVED6
Definition: tle985x.h:2174
__IOM uint32_t LS1_OC_IS
Definition: tle985x.h:2517
__IOM uint32_t HB2T1OFFERRCNT
Definition: tle985x.h:2488
__IM uint32_t RESERVED8
Definition: tle985x.h:2269
__OM uint32_t HS2_DS_SC
Definition: tle985x.h:2567
__IOM uint32_t DRVx_VCPUP_DIS
Definition: tle985x.h:1941
__IM uint32_t HB2_I1OFFVAL
Definition: tle985x.h:2466
__IM uint32_t HB2T1OFFMIN
Definition: tle985x.h:2317
__IOM uint32_t HB1_I3ON
Definition: tle985x.h:2141
__IOM uint32_t HB1AF_ICLMPOFF
Definition: tle985x.h:1993
__IOM uint32_t HB1_T2ON
Definition: tle985x.h:2122
__IOM uint32_t VSD_UPTH_IEN
Definition: tle985x.h:2076
__IOM uint32_t HB2MFERRCNT
Definition: tle985x.h:2490
__IOM uint32_t HB2ONHYSTEN
Definition: tle985x.h:2293
__IOM uint32_t HS1_OC_IS
Definition: tle985x.h:2529
__IOM uint32_t LS2_EN
Definition: tle985x.h:1820
__IOM uint32_t LS1DRV_FDISCHG_DIS
Definition: tle985x.h:1912
__IOM uint32_t HS2DRV_OCSDN_DIS
Definition: tle985x.h:1924
__IOM uint32_t HS2_OC_DIS
Definition: tle985x.h:1842
__IOM uint32_t HS2_OC_IS
Definition: tle985x.h:2535
__IOM uint32_t HB2_I3ON
Definition: tle985x.h:2236
__IOM uint32_t VCP_OTW_STS
Definition: tle985x.h:2017
__IM uint32_t RESERVED1
Definition: tle985x.h:1929
__IOM uint32_t HB2_I4ON
Definition: tle985x.h:2239
__IM uint32_t HB2I1ONMIN
Definition: tle985x.h:2322
__IOM uint32_t DSMONVTH
Definition: tle985x.h:1868
__IM uint32_t RESERVED4
Definition: tle985x.h:2079
__IOM uint32_t LS1_SRC_SEL
Definition: tle985x.h:1883
__OM uint32_t SEQ_ERR_ISC
Definition: tle985x.h:2570
__IM uint32_t HB2T12ONMAX
Definition: tle985x.h:2319
__IM uint32_t HB2_T3ONCNT
Definition: tle985x.h:2450
__IOM uint32_t VSD_UPTH_IS
Definition: tle985x.h:2016
__IOM uint32_t HS1DRV_OCSDN_DIS
Definition: tle985x.h:1923
__IOM uint32_t VCP_UPTH_STS
Definition: tle985x.h:2023
__IOM uint32_t HB2T12ONERRCNT
Definition: tle985x.h:2489
__IOM uint32_t HB2OFFHYSTEN
Definition: tle985x.h:2295
__IOM uint32_t HB1OFFHYSTEN
Definition: tle985x.h:2283
__IOM uint32_t HB1_T2OFF
Definition: tle985x.h:2087
__OM uint32_t VSD_LOTH_SC
Definition: tle985x.h:2056
__IM uint32_t HB2ONMF
Definition: tle985x.h:2325
__IOM uint32_t HB2OPTONACT
Definition: tle985x.h:2291
__IM uint32_t HB1_I1OFFVAL
Definition: tle985x.h:2427
__IOM uint32_t VCP_OTW_IEN
Definition: tle985x.h:2066
__IM uint32_t HB2_T12ONCNT
Definition: tle985x.h:2445
__IOM uint32_t HB2_T2OFF
Definition: tle985x.h:2182
__IOM uint32_t DRVx_VCPLO_DIS
Definition: tle985x.h:1939
__IOM uint32_t HB1_OFFVALVF
Definition: tle985x.h:2434
__IOM uint32_t HB1T1OFFERRCNT
Definition: tle985x.h:2484
__IOM uint32_t HS1_DS_IS
Definition: tle985x.h:2525
__IOM uint32_t VCP_LOTH1_IS
Definition: tle985x.h:2010
__IOM uint32_t LSDRV_DS_TFILT_SEL
Definition: tle985x.h:1911
__OM uint32_t HS2_DS_ISC
Definition: tle985x.h:2565
CCU6 (CCU6)
Definition: tle985x.h:2616
__IOM uint16_t T13MODEN
Definition: tle985x.h:2953
__IOM uint16_t INPCC62
Definition: tle985x.h:2872
__IOM uint16_t INPCHE
Definition: tle985x.h:2873
__IM uint16_t CC63ST
Definition: tle985x.h:3068
__IOM uint16_t ECT13O
Definition: tle985x.h:2955
__IOM uint16_t DTE2
Definition: tle985x.h:2769
__OM uint16_t MCC63R
Definition: tle985x.h:2703
__OM uint16_t RT12PM
Definition: tle985x.h:2676
__IM uint16_t CHE
Definition: tle985x.h:3003
__OM uint16_t RCHE
Definition: tle985x.h:2681
__OM uint16_t MCC62S
Definition: tle985x.h:2695
__IOM uint16_t DBYP
Definition: tle985x.h:2831
__IOM uint16_t ENCC62R
Definition: tle985x.h:2848
__IM uint16_t T13R
Definition: tle985x.h:2790
__OM uint16_t STRMCM
Definition: tle985x.h:2656
__IOM uint16_t INPCC60
Definition: tle985x.h:2870
__IOM uint16_t ENT13PM
Definition: tle985x.h:2855
__IOM uint16_t ISCC61
Definition: tle985x.h:3016
__OM uint16_t RTRPF
Definition: tle985x.h:2679
__OM uint16_t T12RS
Definition: tle985x.h:2632
__IM uint16_t T12OM
Definition: tle985x.h:2997
__IM uint16_t IDLE
Definition: tle985x.h:3005
__IM uint16_t RESERVED26
Definition: tle985x.h:3009
__IM uint16_t DTR2
Definition: tle985x.h:2773
__IOM uint16_t T12PV
Definition: tle985x.h:2748
__OM uint16_t T13STD
Definition: tle985x.h:2645
__IM uint16_t RESERVED19
Definition: tle985x.h:2903
__IOM uint16_t ISPOS2
Definition: tle985x.h:3021
__IOM uint16_t T13TEC
Definition: tle985x.h:2937
__IM uint16_t RESERVED12
Definition: tle985x.h:2794
__IOM uint16_t T13RSEL
Definition: tle985x.h:2941
__OM uint16_t MCC60S
Definition: tle985x.h:2693
__IOM uint16_t T12MODEN
Definition: tle985x.h:2950
__IOM uint16_t INPT13
Definition: tle985x.h:2876
__OM uint16_t RCC62R
Definition: tle985x.h:2673
__IM uint16_t RESERVED13
Definition: tle985x.h:2803
__IM uint16_t CCV
Definition: tle985x.h:2622
__OM uint16_t SCHE
Definition: tle985x.h:2897
__IOM uint16_t ENIDLE
Definition: tle985x.h:2860
__IOM uint16_t ISPOS1
Definition: tle985x.h:3020
__IOM uint16_t PSL
Definition: tle985x.h:2909
__IOM uint16_t TRPM10
Definition: tle985x.h:2964
__IOM uint16_t T12EXT
Definition: tle985x.h:3034
__IOM uint16_t T13CLK
Definition: tle985x.h:2788
__OM uint16_t ST12PM
Definition: tle985x.h:2892
__IOM uint16_t CC61PS
Definition: tle985x.h:3072
__OM uint16_t ST12OM
Definition: tle985x.h:2891
__OM uint16_t T12RES
Definition: tle985x.h:2633
__IM uint16_t RESERVED22
Definition: tle985x.h:2944
__OM uint16_t T12RR
Definition: tle985x.h:2631
__IOM uint16_t T12PRE
Definition: tle985x.h:2783
__IM uint16_t ICC60R
Definition: tle985x.h:2991
__IOM uint16_t HSYNC
Definition: tle985x.h:2830
__IOM uint16_t T13IM
Definition: tle985x.h:3077
__OM uint16_t SSTR
Definition: tle985x.h:2900
__OM uint16_t SCC61F
Definition: tle985x.h:2888
__IM uint16_t RESERVED8
Definition: tle985x.h:2742
__IM uint16_t STE13
Definition: tle985x.h:2791
__IOM uint16_t CTM
Definition: tle985x.h:2787
__IM uint16_t T12PM
Definition: tle985x.h:2998
__OM uint16_t MCC60R
Definition: tle985x.h:2699
__OM uint16_t SWHE
Definition: tle985x.h:2898
__IOM uint16_t DTE1
Definition: tle985x.h:2768
__OM uint16_t T13STR
Definition: tle985x.h:2644
__OM uint16_t MCC62R
Definition: tle985x.h:2701
__IOM uint16_t INPERR
Definition: tle985x.h:2874
__IM uint16_t RESERVED4
Definition: tle985x.h:2706
__OM uint16_t SCC62R
Definition: tle985x.h:2889
__OM uint16_t RCC60F
Definition: tle985x.h:2670
__IM uint16_t ICC60F
Definition: tle985x.h:2992
__IOM uint16_t DTM
Definition: tle985x.h:2766
__IM uint16_t STE12
Definition: tle985x.h:2785
__IOM uint16_t COUT60PS
Definition: tle985x.h:3071
__IOM uint16_t STE12D
Definition: tle985x.h:2925
__IOM uint16_t EXPHS
Definition: tle985x.h:2657
__IM uint16_t
Definition: tle985x.h:2635
__OM uint16_t RT12OM
Definition: tle985x.h:2675
__IOM uint16_t ISTRP
Definition: tle985x.h:3018
__OM uint16_t T13CNT
Definition: tle985x.h:2643
__IOM uint16_t ENCC60F
Definition: tle985x.h:2842
__IM uint16_t CCPOS2
Definition: tle985x.h:3067
__OM uint16_t RCC62F
Definition: tle985x.h:2674
__IOM uint16_t COUT63PS
Definition: tle985x.h:3076
__IOM uint16_t T12SSC
Definition: tle985x.h:2935
__OM uint16_t RCC60R
Definition: tle985x.h:2669
__IOM uint16_t SWSEL
Definition: tle985x.h:2920
__IM uint16_t TRPF
Definition: tle985x.h:3001
__IM uint16_t RESERVED10
Definition: tle985x.h:2760
__OM uint16_t SIDLE
Definition: tle985x.h:2899
__OM uint16_t STRPF
Definition: tle985x.h:2895
__OM uint16_t RWHE
Definition: tle985x.h:2682
__IOM uint16_t ENT12PM
Definition: tle985x.h:2853
__OM uint16_t MCC63S
Definition: tle985x.h:2697
__IOM uint16_t ENCC61F
Definition: tle985x.h:2846
__IM uint16_t RESERVED20
Definition: tle985x.h:2914
__IM uint16_t ICC62F
Definition: tle985x.h:2996
__IM uint16_t R
Definition: tle985x.h:2979
__OM uint16_t MCC61S
Definition: tle985x.h:2694
__IM uint16_t T12R
Definition: tle985x.h:2784
__IM uint16_t CCPOS0
Definition: tle985x.h:3065
__OM uint16_t ST13PM
Definition: tle985x.h:2894
__OM uint16_t SWHC
Definition: tle985x.h:2896
__IM uint16_t RESERVED28
Definition: tle985x.h:3038
__IM uint16_t RESERVED14
Definition: tle985x.h:2812
__IOM uint16_t reg
Definition: tle985x.h:2619
__IOM uint16_t MSEL60
Definition: tle985x.h:2827
__IOM uint16_t COUT62PS
Definition: tle985x.h:3075
__IM uint16_t RESERVED25
Definition: tle985x.h:2985
__IOM uint16_t ISCNT13
Definition: tle985x.h:3033
__IOM uint16_t ENWHE
Definition: tle985x.h:2859
__IM uint16_t CCPOS1
Definition: tle985x.h:3066
__IM uint16_t RESERVED30
Definition: tle985x.h:3056
__OM uint16_t T13RS
Definition: tle985x.h:2640
__OM uint16_t RSTR
Definition: tle985x.h:2684
__IM uint16_t CDIR
Definition: tle985x.h:2786
__IOM uint16_t IST13HR
Definition: tle985x.h:3031
__OM uint16_t SCC61R
Definition: tle985x.h:2887
__IM uint16_t CC62ST
Definition: tle985x.h:3064
__OM uint16_t T12STR
Definition: tle985x.h:2637
__IM uint16_t RESERVED6
Definition: tle985x.h:2724
__IM uint16_t DTR1
Definition: tle985x.h:2772
__OM uint16_t T12CNT
Definition: tle985x.h:2636
__OM uint16_t SCC60F
Definition: tle985x.h:2886
__IOM uint16_t MCMPS
Definition: tle985x.h:2654
__IOM uint16_t T12CV
Definition: tle985x.h:3044
__IOM uint16_t STE13U
Definition: tle985x.h:2926
__IOM uint16_t ENCC60R
Definition: tle985x.h:2840
__OM uint16_t RCC61F
Definition: tle985x.h:2672
__IOM uint16_t ENCC61R
Definition: tle985x.h:2844
__IOM uint16_t CC60PS
Definition: tle985x.h:3070
__IM uint16_t DTR0
Definition: tle985x.h:2771
__IOM uint16_t T13EXT
Definition: tle985x.h:3035
__IOM uint16_t IST12HR
Definition: tle985x.h:3022
__IOM uint16_t T13SSC
Definition: tle985x.h:2936
__IOM uint16_t INPCC61
Definition: tle985x.h:2871
__OM uint16_t RCC61R
Definition: tle985x.h:2671
__IM uint16_t CC60ST
Definition: tle985x.h:3062
__IOM uint16_t MCMEN
Definition: tle985x.h:2952
__IOM uint16_t ENTRPF
Definition: tle985x.h:2856
__IM uint16_t RESERVED11
Definition: tle985x.h:2776
__IOM uint16_t TRPPEN
Definition: tle985x.h:2969
__IOM uint16_t CCS
Definition: tle985x.h:2712
__IOM uint16_t ENT13CM
Definition: tle985x.h:2854
__IM uint16_t MCMP
Definition: tle985x.h:2978
__IOM uint16_t T12CLK
Definition: tle985x.h:2782
__IM uint16_t RESERVED29
Definition: tle985x.h:3047
__IOM uint16_t TRPEN13
Definition: tle985x.h:2968
__IOM uint16_t CURHS
Definition: tle985x.h:2658
__OM uint16_t ST13CM
Definition: tle985x.h:2893
__IM uint16_t CC61ST
Definition: tle985x.h:3063
__IOM uint16_t T13TED
Definition: tle985x.h:2938
__IOM uint16_t CC62PS
Definition: tle985x.h:3074
__IOM uint16_t TRPEN
Definition: tle985x.h:2967
__OM uint16_t SCC62F
Definition: tle985x.h:2890
__IOM uint16_t T13PRE
Definition: tle985x.h:2789
__IOM uint16_t ISCNT12
Definition: tle985x.h:3032
__IOM uint16_t COUT61PS
Definition: tle985x.h:3073
__IM uint16_t STR
Definition: tle985x.h:3006
__IM uint16_t RESERVED23
Definition: tle985x.h:2958
__OM uint16_t STRHP
Definition: tle985x.h:2660
__IM uint16_t RESERVED18
Definition: tle985x.h:2879
__IM uint16_t T13CM
Definition: tle985x.h:2999
__IM uint16_t T13PM
Definition: tle985x.h:3000
__IM uint16_t CURH
Definition: tle985x.h:2982
__IM uint16_t RESERVED5
Definition: tle985x.h:2715
__IOM uint16_t DTE0
Definition: tle985x.h:2767
__IM uint16_t WHE
Definition: tle985x.h:3004
__IM uint16_t RESERVED17
Definition: tle985x.h:2864
__IOM uint16_t INPT12
Definition: tle985x.h:2875
__IOM uint16_t T13PV
Definition: tle985x.h:2757
__OM uint16_t T12STD
Definition: tle985x.h:2638
__OM uint16_t DTRES
Definition: tle985x.h:2634
__OM uint16_t MCC61R
Definition: tle985x.h:2700
__OM uint16_t T13RES
Definition: tle985x.h:2641
__OM uint16_t RIDLE
Definition: tle985x.h:2683
__IM uint16_t RESERVED9
Definition: tle985x.h:2751
__IOM uint16_t T13CV
Definition: tle985x.h:3053
__IOM uint16_t ENCC62F
Definition: tle985x.h:2850
__IOM uint16_t ENCHE
Definition: tle985x.h:2858
__IM uint16_t RESERVED1
Definition: tle985x.h:2648
__IOM uint16_t ISCC60
Definition: tle985x.h:3015
__IOM uint16_t TRPM2
Definition: tle985x.h:2965
__IOM uint16_t T12RSEL
Definition: tle985x.h:2940
__OM uint16_t SCC60R
Definition: tle985x.h:2885
__OM uint16_t RT13CM
Definition: tle985x.h:2677
__IOM uint16_t ENT12OM
Definition: tle985x.h:2852
__IOM uint16_t PSL63
Definition: tle985x.h:2911
__IM uint16_t RESERVED7
Definition: tle985x.h:2733
__IM uint16_t RESERVED15
Definition: tle985x.h:2821
__IM uint16_t RESERVED3
Definition: tle985x.h:2687
__IM uint16_t RESERVED21
Definition: tle985x.h:2929
__IOM uint16_t STE12U
Definition: tle985x.h:2924
__IM uint16_t EXPH
Definition: tle985x.h:2981
__IM uint16_t RESERVED
Definition: tle985x.h:2625
__IM uint16_t ICC62R
Definition: tle985x.h:2995
__IOM uint16_t ISPOS0
Definition: tle985x.h:3019
__IOM uint16_t ISCC62
Definition: tle985x.h:3017
__IM uint16_t ICC61R
Definition: tle985x.h:2993
__IM uint16_t RESERVED2
Definition: tle985x.h:2663
__IOM uint16_t SWSYN
Definition: tle985x.h:2922
__OM uint16_t RT13PM
Definition: tle985x.h:2678
__IM uint16_t RESERVED24
Definition: tle985x.h:2972
__IM uint16_t TRPS
Definition: tle985x.h:3002
__IM uint16_t RESERVED16
Definition: tle985x.h:2834
__OM uint16_t T13RR
Definition: tle985x.h:2639
__IM uint16_t ICC61F
Definition: tle985x.h:2994
__IOM uint16_t MSEL61
Definition: tle985x.h:2828
__IOM uint16_t ENSTR
Definition: tle985x.h:2861
__IOM uint16_t MSEL62
Definition: tle985x.h:2829
CPU (CPU)
Definition: tle985x.h:3093
__IM uint32_t UNALIGN_TRP
Definition: tle985x.h:3415
__IOM uint32_t PRI_CCU6SR1
Definition: tle985x.h:3286
__OM uint32_t VECTCLRACTIVE
Definition: tle985x.h:3390
__IOM uint32_t SVCALLPENDED
Definition: tle985x.h:3447
__IOM uint32_t Int_CCU6SR2
Definition: tle985x.h:3146
__IOM uint32_t RELOAD
Definition: tle985x.h:3112
__IOM uint32_t CLKSOURCE
Definition: tle985x.h:3102
__IOM uint32_t PRI_GPT1
Definition: tle985x.h:3269
__IOM uint32_t PRI_BDRV
Definition: tle985x.h:3331
__IOM uint32_t PRI_ADC2
Definition: tle985x.h:3273
__IOM uint32_t Int_SSC1
Definition: tle985x.h:3148
__IOM uint32_t PRI_UART2
Definition: tle985x.h:3305
__IOM uint32_t PRI_DU
Definition: tle985x.h:3344
__IM uint32_t CONSTANT
Definition: tle985x.h:3359
__IOM uint32_t SLEEPONEXIT
Definition: tle985x.h:3403
__IOM uint32_t PRI_14
Definition: tle985x.h:3436
__IOM uint32_t Int_GPT2
Definition: tle985x.h:3141
__IOM uint32_t PRI_WAKEUP
Definition: tle985x.h:3318
__IOM uint32_t Int_UART2
Definition: tle985x.h:3151
__IOM uint32_t Int_BDRV
Definition: tle985x.h:3158
__IM uint32_t VECTACTIVE
Definition: tle985x.h:3369
__IOM uint32_t PRI_CP
Definition: tle985x.h:3329
__OM uint32_t PENDSTCLR
Definition: tle985x.h:3375
__IOM uint32_t PRI_EXINT0
Definition: tle985x.h:3314
__IOM uint32_t Int_SSC2
Definition: tle985x.h:3149
__IOM uint32_t PRI_PORT2
Definition: tle985x.h:3348
__IOM uint32_t PRI_11
Definition: tle985x.h:3427
__IOM uint32_t PRI_GPT2
Definition: tle985x.h:3271
__IM uint32_t COUNTFLAG
Definition: tle985x.h:3104
__IM uint32_t IMPLEMENTER
Definition: tle985x.h:3361
__IOM uint32_t PRI_15
Definition: tle985x.h:3438
__IOM uint32_t SEVONPEND
Definition: tle985x.h:3406
__IOM uint32_t Int_PORT2
Definition: tle985x.h:3163
__IOM uint32_t Int_ADC1
Definition: tle985x.h:3143
__IOM uint32_t Int_MATHDIV
Definition: tle985x.h:3155
__IOM uint32_t Int_GPT1
Definition: tle985x.h:3140
__OM uint32_t SYSRESETREQ
Definition: tle985x.h:3391
__IOM uint32_t Int_EXINT1
Definition: tle985x.h:3153
__IM uint32_t
Definition: tle985x.h:3103
__IM uint32_t RESERVED7
Definition: tle985x.h:3383
__IOM uint32_t PRI_MON
Definition: tle985x.h:3346
__IOM uint32_t ENABLE
Definition: tle985x.h:3100
__IOM uint32_t CURRENT
Definition: tle985x.h:3120
__IOM uint32_t Int_CCU6SR0
Definition: tle985x.h:3144
__IM uint32_t ISRPENDING
Definition: tle985x.h:3373
__IOM uint32_t Int_MON
Definition: tle985x.h:3162
__IOM uint32_t Int_UART1
Definition: tle985x.h:3150
__IM uint32_t TENMS
Definition: tle985x.h:3128
__IM uint32_t PARTNO
Definition: tle985x.h:3358
__IOM uint32_t PRI_CCU6SR3
Definition: tle985x.h:3290
__IOM uint32_t PRI_ADC1
Definition: tle985x.h:3275
__IOM uint32_t PRI_CCU6SR2
Definition: tle985x.h:3288
__IOM uint32_t PRI_OPA
Definition: tle985x.h:3342
__IOM uint32_t SLEEPDEEP
Definition: tle985x.h:3404
__IOM uint32_t PRI_UART1
Definition: tle985x.h:3303
__IM uint32_t STKALIGN
Definition: tle985x.h:3417
__IM uint32_t SKEW
Definition: tle985x.h:3130
__IM uint32_t REVISION
Definition: tle985x.h:3357
__IOM uint32_t PRI_CCU6SR0
Definition: tle985x.h:3284
__IOM uint32_t PRI_SSC1
Definition: tle985x.h:3299
__IOM uint32_t TICKINT
Definition: tle985x.h:3101
__IOM uint32_t reg
Definition: tle985x.h:3097
__IOM uint32_t Int_WAKEUP
Definition: tle985x.h:3154
__IOM uint32_t VECTKEY
Definition: tle985x.h:3394
__IOM uint32_t PENDSVSET
Definition: tle985x.h:3378
__IOM uint32_t PRI_SSC2
Definition: tle985x.h:3301
__IOM uint32_t Int_DU
Definition: tle985x.h:3161
__IM uint32_t ENDIANNESS
Definition: tle985x.h:3393
__IOM uint32_t NMIPENDSET
Definition: tle985x.h:3380
__IOM uint32_t Int_CCU6SR3
Definition: tle985x.h:3147
__IOM uint32_t Int_OPA
Definition: tle985x.h:3160
__IOM uint32_t Int_CP
Definition: tle985x.h:3157
__IM uint32_t NOREF
Definition: tle985x.h:3131
__IM uint32_t RESERVED8
Definition: tle985x.h:3420
__IM uint32_t VARIANT
Definition: tle985x.h:3360
__IOM uint32_t Int_EXINT0
Definition: tle985x.h:3152
__IOM uint32_t PENDSTSET
Definition: tle985x.h:3376
__IOM uint32_t Int_ADC2
Definition: tle985x.h:3142
__IOM uint32_t PRI_MATHDIV
Definition: tle985x.h:3320
__IOM uint32_t Int_CCU6SR1
Definition: tle985x.h:3145
__IM uint32_t VECTPENDING
Definition: tle985x.h:3371
__IOM uint32_t PRI_HS
Definition: tle985x.h:3333
__OM uint32_t PENDSVCLR
Definition: tle985x.h:3377
__IOM uint32_t Int_HS
Definition: tle985x.h:3159
__IOM uint32_t PRI_EXINT1
Definition: tle985x.h:3316
GPT12E (GPT12E)
Definition: tle985x.h:3463
__IOM uint32_t IST6IN
Definition: tle985x.h:3486
__IOM uint32_t T3UDE
Definition: tle985x.h:3518
__IOM uint32_t T4
Definition: tle985x.h:3612
__IOM uint32_t T5RC
Definition: tle985x.h:3557
__IOM uint32_t T2CHDIR
Definition: tle985x.h:3505
__IOM uint32_t T4UDE
Definition: tle985x.h:3536
__IM uint32_t MOD_REV
Definition: tle985x.h:3469
__IOM uint32_t T6SR
Definition: tle985x.h:3580
__IOM uint32_t IST6EUD
Definition: tle985x.h:3487
__IOM uint32_t T2R
Definition: tle985x.h:3498
__IOM uint32_t IST5IN
Definition: tle985x.h:3484
__IOM uint32_t T3I
Definition: tle985x.h:3514
__IOM uint32_t T6OE
Definition: tle985x.h:3575
__IOM uint32_t T6UD
Definition: tle985x.h:3573
__IM uint32_t T2DIR
Definition: tle985x.h:3506
__IOM uint32_t IST3IN
Definition: tle985x.h:3480
__IOM uint32_t T5UDE
Definition: tle985x.h:3556
__IOM uint32_t T6UDE
Definition: tle985x.h:3574
__IOM uint32_t T4RC
Definition: tle985x.h:3537
__IOM uint32_t T4IRDIS
Definition: tle985x.h:3540
__IOM uint32_t CT3
Definition: tle985x.h:3558
__IOM uint32_t T4EDGE
Definition: tle985x.h:3541
__IOM uint32_t IST5EUD
Definition: tle985x.h:3485
__IOM uint32_t T4M
Definition: tle985x.h:3533
__IOM uint32_t IST4IN
Definition: tle985x.h:3482
__IOM uint32_t T3R
Definition: tle985x.h:3516
__IOM uint32_t T2IRIDIS
Definition: tle985x.h:3503
__IOM uint32_t T2UDE
Definition: tle985x.h:3500
__IM uint32_t
Definition: tle985x.h:3502
__IOM uint32_t T5CLR
Definition: tle985x.h:3561
__IOM uint32_t T3OE
Definition: tle985x.h:3519
__IOM uint32_t T2M
Definition: tle985x.h:3497
__IOM uint32_t T5
Definition: tle985x.h:3620
__IOM uint32_t T2EDGE
Definition: tle985x.h:3504
__IOM uint32_t T6R
Definition: tle985x.h:3572
__IOM uint32_t T4R
Definition: tle985x.h:3534
__IM uint32_t T3DIR
Definition: tle985x.h:3524
__IOM uint32_t T3OTL
Definition: tle985x.h:3520
__IOM uint32_t T3EDGE
Definition: tle985x.h:3522
__IOM uint32_t T6M
Definition: tle985x.h:3571
__IOM uint32_t T6CLR
Definition: tle985x.h:3579
__IOM uint32_t CLRT2EN
Definition: tle985x.h:3538
__IOM uint32_t BPS2
Definition: tle985x.h:3577
__IOM uint32_t IST4EUD
Definition: tle985x.h:3483
__IOM uint32_t T2UD
Definition: tle985x.h:3499
__IM uint32_t MOD_TYPE
Definition: tle985x.h:3470
__IOM uint32_t T5UD
Definition: tle985x.h:3555
__IOM uint32_t T4CHDIR
Definition: tle985x.h:3542
__IOM uint32_t IST3EUD
Definition: tle985x.h:3481
__IOM uint32_t T2I
Definition: tle985x.h:3496
__IOM uint32_t T6
Definition: tle985x.h:3628
__IOM uint32_t T5SC
Definition: tle985x.h:3562
__IOM uint32_t BPS1
Definition: tle985x.h:3521
__IOM uint32_t reg
Definition: tle985x.h:3466
__IOM uint32_t ISCAPIN
Definition: tle985x.h:3488
__IOM uint32_t IST2EUD
Definition: tle985x.h:3479
__IOM uint32_t IST2IN
Definition: tle985x.h:3478
__IOM uint32_t T2
Definition: tle985x.h:3596
__IOM uint32_t T6OTL
Definition: tle985x.h:3576
__IOM uint32_t T5I
Definition: tle985x.h:3551
__IOM uint32_t CI
Definition: tle985x.h:3560
__IOM uint32_t T3
Definition: tle985x.h:3604
__IOM uint32_t T4UD
Definition: tle985x.h:3535
__IOM uint32_t T2RC
Definition: tle985x.h:3501
__IOM uint32_t T5M
Definition: tle985x.h:3552
__IOM uint32_t CAPREL
Definition: tle985x.h:3588
__IOM uint32_t T6I
Definition: tle985x.h:3570
__IOM uint32_t T3UD
Definition: tle985x.h:3517
__IOM uint32_t T4I
Definition: tle985x.h:3532
__IOM uint32_t T3CHDIR
Definition: tle985x.h:3523
__IOM uint32_t CLRT3EN
Definition: tle985x.h:3539
__IM uint32_t T4RDIR
Definition: tle985x.h:3543
__IOM uint32_t T5R
Definition: tle985x.h:3554
__IOM uint32_t T3M
Definition: tle985x.h:3515
HS (HS)
Definition: tle985x.h:3644
__IOM uint32_t HS1_OL_IS
Definition: tle985x.h:3668
__OM uint32_t HS1_OC_ISC
Definition: tle985x.h:3683
__IOM uint32_t HS1_PWM
Definition: tle985x.h:3652
__IOM uint32_t HS1_OT_STS
Definition: tle985x.h:3671
__IOM uint32_t HS1_OC_SEL
Definition: tle985x.h:3658
__IOM uint32_t HS1_EN
Definition: tle985x.h:3651
__IM uint32_t
Definition: tle985x.h:3655
__IOM uint32_t HS1_ON
Definition: tle985x.h:3653
__IOM uint32_t HS1_SRC_SEL
Definition: tle985x.h:3719
__IOM uint32_t HS1_OC_OT_BTFILT_SEL
Definition: tle985x.h:3708
__OM uint32_t HS1_OL_SC
Definition: tle985x.h:3686
__IM uint32_t RESERVED
Definition: tle985x.h:3645
__IOM uint32_t HS1_OC_IEN
Definition: tle985x.h:3697
__IOM uint32_t HS1_OT_IS
Definition: tle985x.h:3667
__IOM uint32_t reg
Definition: tle985x.h:3648
__OM uint32_t HS1_OT_SC
Definition: tle985x.h:3685
__IOM uint32_t HS1_OL_IEN
Definition: tle985x.h:3696
__OM uint32_t HS1_OL_ISC
Definition: tle985x.h:3682
__IM uint32_t RESERVED2
Definition: tle985x.h:3712
__IOM uint32_t HS1_OC_IS
Definition: tle985x.h:3669
__IOM uint32_t HS1_OL_BTFILT_SEL
Definition: tle985x.h:3706
__IOM uint32_t HS1_SR_CTRL_SEL
Definition: tle985x.h:3656
__IOM uint32_t HS1_OL_STS
Definition: tle985x.h:3672
__IOM uint32_t HS1_OL_EN
Definition: tle985x.h:3654
__IOM uint32_t HS1_OT_IEN
Definition: tle985x.h:3695
__OM uint32_t HS1_OT_ISC
Definition: tle985x.h:3681
LIN (LIN)
Definition: tle985x.h:3735
__IM uint32_t FB_SM2
Definition: tle985x.h:3751
__OM uint32_t M_SM_ERR_ISC
Definition: tle985x.h:3781
__OM uint32_t M_SM_ERR_SC
Definition: tle985x.h:3788
__IOM uint32_t SM
Definition: tle985x.h:3749
__IM uint32_t FB_SM1
Definition: tle985x.h:3750
__IOM uint32_t HV_MODE
Definition: tle985x.h:3754
__IOM uint32_t OC_IEN
Definition: tle985x.h:3803
__IM uint32_t MODE_FB
Definition: tle985x.h:3744
__IM uint32_t OT_STS
Definition: tle985x.h:3770
__OM uint32_t OT_SC
Definition: tle985x.h:3790
__IM uint32_t
Definition: tle985x.h:3743
__IM uint32_t TXD_TMOUT_STS
Definition: tle985x.h:3772
__IM uint32_t FB_SM3
Definition: tle985x.h:3752
__IM uint32_t OT_IS
Definition: tle985x.h:3765
__IOM uint32_t OT_IEN
Definition: tle985x.h:3802
__OM uint32_t OT_ISC
Definition: tle985x.h:3783
__IM uint32_t M_SM_ERR_IS
Definition: tle985x.h:3763
__IM uint32_t RXD
Definition: tle985x.h:3748
__IOM uint32_t TXD_TMOUT_IEN
Definition: tle985x.h:3804
__IOM uint32_t TXD
Definition: tle985x.h:3746
__IOM uint32_t M_SM_ERR_IEN
Definition: tle985x.h:3801
__OM uint32_t OC_ISC
Definition: tle985x.h:3785
__OM uint32_t TXD_TMOUT_ISC
Definition: tle985x.h:3786
__IOM uint32_t reg
Definition: tle985x.h:3738
__IOM uint32_t EN
Definition: tle985x.h:3741
__OM uint32_t TXD_TMOUT_SC
Definition: tle985x.h:3792
__IM uint32_t OC_IS
Definition: tle985x.h:3766
__IM uint32_t M_SM_ERR_STS
Definition: tle985x.h:3769
__IOM uint32_t MODE
Definition: tle985x.h:3742
__IM uint32_t TXD_TMOUT_IS
Definition: tle985x.h:3767
MATH (MATH)
Definition: tle985x.h:3820
__IOM uint32_t DIVERRIEN
Definition: tle985x.h:3852
__IM uint32_t MOD_REV
Definition: tle985x.h:3841
__IOM uint32_t DIVEOCIEN
Definition: tle985x.h:3851
__IOM uint32_t DVDSLC
Definition: tle985x.h:3936
__IM uint32_t MOD_NUMBER
Definition: tle985x.h:3843
__IOM uint32_t SUSCFG
Definition: tle985x.h:3831
__IOM uint32_t DVDRC
Definition: tle985x.h:3827
__IOM uint32_t MATH_EN
Definition: tle985x.h:3833
__IM uint32_t DIVERR
Definition: tle985x.h:3861
__IM uint32_t
Definition: tle985x.h:3828
__IM uint32_t VAL
Definition: tle985x.h:3904
__OM uint32_t DIVERRC
Definition: tle985x.h:3879
__IM uint32_t DIVEOC
Definition: tle985x.h:3860
__IM uint32_t MOD_TYPE
Definition: tle985x.h:3842
__IOM uint32_t QSDIR
Definition: tle985x.h:3935
__IOM uint32_t DVSSRC
Definition: tle985x.h:3938
__IM uint32_t RESERVED
Definition: tle985x.h:3821
__IOM uint32_t reg
Definition: tle985x.h:3824
__IOM uint32_t USIGN
Definition: tle985x.h:3930
__IM uint32_t BSY
Definition: tle985x.h:3920
__IOM uint32_t DVSRC
Definition: tle985x.h:3829
__OM uint32_t DIVERRS
Definition: tle985x.h:3870
__IOM uint32_t STMODE
Definition: tle985x.h:3929
__OM uint32_t DIVEOCC
Definition: tle985x.h:3878
__IOM uint32_t QSCNT
Definition: tle985x.h:3933
__OM uint32_t DIVEOCS
Definition: tle985x.h:3869
__IOM uint32_t ST
Definition: tle985x.h:3928
__IM uint32_t RESERVED1
Definition: tle985x.h:3882
__IOM uint32_t VAL
Definition: tle985x.h:3888
__IOM uint32_t DIVMODE
Definition: tle985x.h:3931
MF (MF)
Definition: tle985x.h:3954
__IOM uint32_t CSA_EN
Definition: tle985x.h:3960
__IM uint32_t VREF1V2_UPTHWARN_STS
Definition: tle985x.h:3977
__IOM uint32_t CSA_VZERO
Definition: tle985x.h:3965
__IM uint32_t VREF1V2_LOTHWARN_STS
Definition: tle985x.h:3975
__IM uint32_t
Definition: tle985x.h:3962
__IOM uint32_t CSA_MI_EN
Definition: tle985x.h:3963
__IOM uint32_t reg
Definition: tle985x.h:3957
__IOM uint32_t CSA_GAIN
Definition: tle985x.h:3961
PMU (PMU)
Definition: tle985x.h:3994
__IOM uint32_t DATA3
Definition: tle985x.h:4307
__IM uint32_t RESERVED3
Definition: tle985x.h:4214
__IOM uint32_t SPARE
Definition: tle985x.h:4223
__IOM uint32_t DATA1
Definition: tle985x.h:4305
__IOM uint32_t WAKE_W_RST
Definition: tle985x.h:4109
__IOM uint32_t MON3_PU
Definition: tle985x.h:4164
__IOM uint32_t MON2_FALL
Definition: tle985x.h:4152
__IOM uint32_t MON2_NSLEEP_SPARE
Definition: tle985x.h:4157
__IOM uint32_t FA_2
Definition: tle985x.h:4286
__IOM uint32_t MON1_PU
Definition: tle985x.h:4148
__IM uint32_t GPIO1_STS_2
Definition: tle985x.h:4038
__IM uint32_t GPIO2
Definition: tle985x.h:4010
__IOM uint32_t CNF_ON
Definition: tle985x.h:4133
__IM uint32_t GPIO1_STS_0
Definition: tle985x.h:4036
__IOM uint32_t CNF_MON_FT
Definition: tle985x.h:4258
__OM uint32_t PMU_5V_OVERLOAD_SC
Definition: tle985x.h:4061
__IM uint32_t PMU_1V5_OVERVOLT
Definition: tle985x.h:4048
__IOM uint32_t PMU_1V5_FAIL_EN
Definition: tle985x.h:4050
__IOM uint32_t CYC_WAKE_M03
Definition: tle985x.h:4118
__IM uint32_t MON1_STS
Definition: tle985x.h:4150
__IM uint32_t MON3_STS
Definition: tle985x.h:4166
__IOM uint32_t PMU_WAKE
Definition: tle985x.h:4091
__IOM uint32_t MON4_RISE
Definition: tle985x.h:4169
__IOM uint32_t RI_4
Definition: tle985x.h:4281
__OM uint32_t VDDEXT_UV_ISC
Definition: tle985x.h:4080
__IM uint32_t LP_CLKWD
Definition: tle985x.h:4247
__OM uint32_t VDDEXT_OT_SC
Definition: tle985x.h:4081
__IOM uint32_t DATA8
Definition: tle985x.h:4326
__IOM uint32_t MON1_EN
Definition: tle985x.h:4143
__IM uint32_t GPIO1
Definition: tle985x.h:4005
__IOM uint32_t CNF_OFF
Definition: tle985x.h:4134
__IOM uint32_t CYC_2
Definition: tle985x.h:4293
__IOM uint32_t MON2_CYC
Definition: tle985x.h:4154
__IOM uint32_t MON5_PU
Definition: tle985x.h:4187
__IOM uint32_t CYC_SENSE_M03
Definition: tle985x.h:4115
__IOM uint32_t DATA2
Definition: tle985x.h:4306
__IM uint32_t PMU_1V5_OVL
Definition: tle985x.h:4242
__IM uint32_t MON4_STS
Definition: tle985x.h:4174
__IOM uint32_t MON1_PD
Definition: tle985x.h:4147
__IM uint32_t MON2_WAKE_STS
Definition: tle985x.h:4014
__IOM uint32_t CNF_FILT
Definition: tle985x.h:4268
__IOM uint32_t MON5_CYC
Definition: tle985x.h:4185
__IOM uint32_t VDDEXT_FAIL_EN
Definition: tle985x.h:4071
__IOM uint32_t MON1_RISE
Definition: tle985x.h:4145
__IOM uint32_t CYC_WAKE_E01
Definition: tle985x.h:4119
__IOM uint32_t PMU_OT_INT_EN
Definition: tle985x.h:4209
__IM uint32_t SYS_CLK_WDT
Definition: tle985x.h:4244
__IOM uint32_t RI_3
Definition: tle985x.h:4280
__IM uint32_t PMU_OT
Definition: tle985x.h:4019
__IOM uint32_t CYC_SENSE_S_DEL
Definition: tle985x.h:4121
__IM uint32_t VDDEXT_UV_IS
Definition: tle985x.h:4074
__IOM uint32_t MON5_RISE
Definition: tle985x.h:4184
__IOM uint32_t DATA6
Definition: tle985x.h:4317
__IOM uint32_t MON1_FALL
Definition: tle985x.h:4144
__IM uint32_t SYS_OT
Definition: tle985x.h:4245
__IOM uint32_t RST_TFB
Definition: tle985x.h:4232
__IOM uint32_t MON2_EN
Definition: tle985x.h:4151
__IOM uint32_t MON1_NSLEEP_SPARE
Definition: tle985x.h:4149
__IM uint32_t PMU_5V_OVERVOLT
Definition: tle985x.h:4052
__IOM uint32_t PMU_OT_TH_CNF
Definition: tle985x.h:4207
__IOM uint32_t MON5_PD
Definition: tle985x.h:4186
__IM uint32_t VDDEXT_OT_IS
Definition: tle985x.h:4073
__IM uint32_t GPIO1_STS_4
Definition: tle985x.h:4040
__IOM uint32_t DATA5
Definition: tle985x.h:4316
__IOM uint32_t MON3_NSLEEP_SPARE
Definition: tle985x.h:4165
__IM uint32_t PMU_OVERTEMP
Definition: tle985x.h:4051
__IOM uint32_t MON5_FALL
Definition: tle985x.h:4183
__IOM uint32_t FA_4
Definition: tle985x.h:4288
__IOM uint32_t PMU_SOFT
Definition: tle985x.h:4099
__IOM uint32_t MON3_EN
Definition: tle985x.h:4159
__IM uint32_t SUPP_SHORT
Definition: tle985x.h:4240
__IOM uint32_t PMU_OT_WAKE_EN
Definition: tle985x.h:4210
__IM uint32_t MON3_WAKE_STS
Definition: tle985x.h:4015
__IM uint32_t GPIO0_STS_0
Definition: tle985x.h:4029
__IOM uint32_t MON1_CYC
Definition: tle985x.h:4146
__IOM uint32_t CYC_3
Definition: tle985x.h:4294
__IM uint32_t
Definition: tle985x.h:4012
__IM uint32_t RESERVED7
Definition: tle985x.h:4271
__IM uint32_t GPIO0_STS_5
Definition: tle985x.h:4034
__IM uint32_t SUPP_TMOUT
Definition: tle985x.h:4241
__IOM uint32_t MON4_PD
Definition: tle985x.h:4171
__IOM uint32_t MON4_NSLEEP_SPARE
Definition: tle985x.h:4173
__IOM uint32_t PMU_SleepEX
Definition: tle985x.h:4092
__OM uint32_t PMU_OVERTEMP_SC
Definition: tle985x.h:4059
__IOM uint32_t CYC_SENSE_EN
Definition: tle985x.h:4113
__IOM uint32_t PMU_IntWDT
Definition: tle985x.h:4098
__IOM uint32_t MON2_PU
Definition: tle985x.h:4156
__IM uint32_t GPIO0_STS_2
Definition: tle985x.h:4031
__IM uint32_t MON5_STS
Definition: tle985x.h:4189
__IOM uint32_t GL2_CYC_ON
Definition: tle985x.h:4131
__IOM uint32_t CNF_LIN_FT
Definition: tle985x.h:4257
__IOM uint32_t EN_0V9_N
Definition: tle985x.h:4110
__IOM uint32_t DATA7
Definition: tle985x.h:4318
__IM uint32_t LIN_WAKE
Definition: tle985x.h:4000
__IOM uint32_t GL2_HOLD_ON
Definition: tle985x.h:4132
__IM uint32_t VDDEXT_UV
Definition: tle985x.h:4021
__IOM uint32_t GL1_HOLD_ON
Definition: tle985x.h:4130
__IOM uint32_t MON3_RISE
Definition: tle985x.h:4161
__IOM uint32_t CYC_4
Definition: tle985x.h:4295
__IOM uint32_t HS1_CYC_EN
Definition: tle985x.h:4221
__IOM uint32_t RI_5
Definition: tle985x.h:4282
__IM uint32_t VDDEXT_OT_STS
Definition: tle985x.h:4075
__IOM uint32_t LOCKUP
Definition: tle985x.h:4100
__IOM uint32_t PMU_PIN
Definition: tle985x.h:4096
__IOM uint32_t MON4_EN
Definition: tle985x.h:4167
__IOM uint32_t CYC_1
Definition: tle985x.h:4292
__IOM uint32_t LIN_WAKE_EN
Definition: tle985x.h:4199
__IOM uint32_t MON4_PU
Definition: tle985x.h:4172
__IOM uint32_t MON4_CYC
Definition: tle985x.h:4170
__IOM uint32_t FA_0
Definition: tle985x.h:4284
__IOM uint32_t PMU_5V_FAIL_EN
Definition: tle985x.h:4054
__IOM uint32_t MON2_RISE
Definition: tle985x.h:4153
__IOM uint32_t PMU_VS_POR
Definition: tle985x.h:4097
__IOM uint32_t FA_5
Definition: tle985x.h:4289
__IM uint32_t FAIL
Definition: tle985x.h:4008
__IM uint32_t WDT1_SEQ_FAIL
Definition: tle985x.h:4246
__IOM uint32_t PMU_ClkWDT
Definition: tle985x.h:4094
__IOM uint32_t MON5_EN
Definition: tle985x.h:4182
__IM uint32_t VDDEXT_OT
Definition: tle985x.h:4020
__IOM uint32_t PMU_OT_EN
Definition: tle985x.h:4211
__IOM uint32_t MON5_NSLEEP_SPARE
Definition: tle985x.h:4188
__IOM uint32_t reg
Definition: tle985x.h:3997
__IOM uint32_t FA_1
Definition: tle985x.h:4285
__IOM uint32_t VDDEXT_ENABLE
Definition: tle985x.h:4069
__OM uint32_t PMU_5V_OVERVOLT_SC
Definition: tle985x.h:4060
__IOM uint32_t CYC_5
Definition: tle985x.h:4296
__OM uint32_t PMU_1V5_OVERLOAD_SC
Definition: tle985x.h:4057
__IM uint32_t MON4_WAKE_STS
Definition: tle985x.h:4016
__IOM uint32_t VDDEXT_CYC_EN
Definition: tle985x.h:4070
__IOM uint32_t MON3_FALL
Definition: tle985x.h:4160
__IM uint32_t GPIO0_STS_3
Definition: tle985x.h:4032
__OM uint32_t PMU_1V5_OVERVOLT_SC
Definition: tle985x.h:4056
__IOM uint32_t MON4_FALL
Definition: tle985x.h:4168
__IOM uint32_t MON3_PD
Definition: tle985x.h:4163
__IM uint32_t PMU_5V_OVL
Definition: tle985x.h:4243
__IM uint32_t RESERVED6
Definition: tle985x.h:4262
__IM uint32_t MON1_WAKE_STS
Definition: tle985x.h:4013
__IOM uint32_t CNF_GPIO_FT
Definition: tle985x.h:4259
__IM uint32_t GPIO0
Definition: tle985x.h:4003
__IOM uint32_t GL1_CYC_ON
Definition: tle985x.h:4129
__IM uint32_t GPIO1_STS_1
Definition: tle985x.h:4037
__IOM uint32_t CYC_WAKE_EN
Definition: tle985x.h:4112
__IM uint32_t PMU_5V_OVERLOAD
Definition: tle985x.h:4053
__IOM uint32_t CYC_SENSE_E01
Definition: tle985x.h:4116
__IM uint32_t MON
Definition: tle985x.h:4001
__IOM uint32_t MON2_PD
Definition: tle985x.h:4155
__IOM uint32_t CYC_0
Definition: tle985x.h:4291
__IM uint32_t PMU_1V5_OVERLOAD
Definition: tle985x.h:4049
__IOM uint32_t DATA10
Definition: tle985x.h:4328
__IOM uint32_t SYS_FAIL
Definition: tle985x.h:4089
__IOM uint32_t RI_0
Definition: tle985x.h:4277
__IOM uint32_t PMU_LPR
Definition: tle985x.h:4093
__IOM uint32_t FA_3
Definition: tle985x.h:4287
__IOM uint32_t MON3_CYC
Definition: tle985x.h:4162
__OM uint32_t VDDEXT_OT_ISC
Definition: tle985x.h:4079
__IM uint32_t CYC_WAKE
Definition: tle985x.h:4007
__IM uint32_t VDDEXT_STABLE
Definition: tle985x.h:4077
__IOM uint32_t DATA11
Definition: tle985x.h:4329
__IM uint32_t PMU_OT_FAIL
Definition: tle985x.h:4248
__IM uint32_t GPIO0_STS_4
Definition: tle985x.h:4033
__IOM uint32_t DATA9
Definition: tle985x.h:4327
__IOM uint32_t DATA4
Definition: tle985x.h:4315
__IOM uint32_t DATA0
Definition: tle985x.h:4304
__IM uint32_t MON2_STS
Definition: tle985x.h:4158
__IOM uint32_t PMU_ExtWDT
Definition: tle985x.h:4095
__IOM uint32_t RI_1
Definition: tle985x.h:4278
__IOM uint32_t RI_2
Definition: tle985x.h:4279
__IM uint32_t GPIO0_STS_1
Definition: tle985x.h:4030
__IM uint32_t MON5_WAKE_STS
Definition: tle985x.h:4017
PORT (PORT)
Definition: tle985x.h:4369
__IOM uint32_t PP5_INEN
Definition: tle985x.h:4418
__IM uint32_t PP3_STS
Definition: tle985x.h:4388
__IM uint32_t PP1_STS
Definition: tle985x.h:4384
__IOM uint32_t PP0
Definition: tle985x.h:4375
__IOM uint32_t PP1
Definition: tle985x.h:4376
__IOM uint32_t PP7
Definition: tle985x.h:4603
__IM uint32_t PP0_STS
Definition: tle985x.h:4382
__IOM uint32_t PP4_INEN
Definition: tle985x.h:4416
__IM uint32_t PP4_STS
Definition: tle985x.h:4390
__IM uint32_t PP2_STS
Definition: tle985x.h:4386
__IM uint32_t
Definition: tle985x.h:4381
__IOM uint32_t PP2
Definition: tle985x.h:4377
__IOM uint32_t PP3
Definition: tle985x.h:4378
__IOM uint32_t PP1_INEN
Definition: tle985x.h:4410
__IM uint32_t RESERVED
Definition: tle985x.h:4487
__IOM uint32_t PP3_INEN
Definition: tle985x.h:4414
__IOM uint32_t PP5
Definition: tle985x.h:4380
__IOM uint32_t reg
Definition: tle985x.h:4372
__IOM uint32_t PP0_INEN
Definition: tle985x.h:4408
__IOM uint32_t PP2_INEN
Definition: tle985x.h:4412
__IM uint32_t RESERVED2
Definition: tle985x.h:4619
__IM uint32_t PP5_STS
Definition: tle985x.h:4392
__IM uint32_t RESERVED1
Definition: tle985x.h:4592
__IOM uint32_t PP4
Definition: tle985x.h:4379
SCU (SCU)
Definition: tle985x.h:4659
__IM uint32_t PRODID
Definition: tle985x.h:5096
__IOM uint32_t PG100TP_CHKS_ERR
Definition: tle985x.h:4984
__IM uint32_t RESERVED3
Definition: tle985x.h:5188
__IOM uint32_t APCLK_SET
Definition: tle985x.h:4882
__IOM uint32_t T2EXIS
Definition: tle985x.h:5155
__IOM uint32_t T2IS
Definition: tle985x.h:5153
__IM uint32_t FNMIOT
Definition: tle985x.h:4740
__IOM uint32_t COUTS1
Definition: tle985x.h:5118
__IOM uint32_t BGCLK_SEL
Definition: tle985x.h:4896
__OM uint32_t TIR1C
Definition: tle985x.h:5496
__IOM uint32_t BG2_FD_SEL
Definition: tle985x.h:5066
__IOM uint32_t P1_PDM4
Definition: tle985x.h:5331
__OM uint32_t BRKC
Definition: tle985x.h:5085
__IM uint32_t RDBE
Definition: tle985x.h:5214
__IOM uint32_t T5IE
Definition: tle985x.h:5417
__IOM uint32_t T2EXISCNF
Definition: tle985x.h:5157
__OM uint32_t MON3FC
Definition: tle985x.h:5460
__IM uint32_t EN_PRG_DAT_LIN
Definition: tle985x.h:5246
__IOM uint32_t PW_MODE
Definition: tle985x.h:5104
__OM uint32_t MON2FC
Definition: tle985x.h:5458
__OM uint32_t GPT2T5C
Definition: tle985x.h:5473
__IM uint32_t EIR2
Definition: tle985x.h:4714
__IOM uint32_t BG1_FD_SEL
Definition: tle985x.h:5026
__IOM uint32_t P0_PDM1
Definition: tle985x.h:5283
__IOM uint32_t T21IS
Definition: tle985x.h:5154
__IOM uint32_t PBA0CLKREL
Definition: tle985x.h:4861
__IOM uint32_t WDTRS
Definition: tle985x.h:4870
__IOM uint32_t BR2_PRE
Definition: tle985x.h:5058
__IOM uint32_t BGSEL
Definition: tle985x.h:5045
__IM uint32_t RIR2
Definition: tle985x.h:4716
__IOM uint32_t WAKEUPEN
Definition: tle985x.h:5301
__OM uint32_t EXINT1RC
Definition: tle985x.h:5444
__IOM uint32_t T4IE
Definition: tle985x.h:5416
__IM uint32_t EN_RD_DAT_NL
Definition: tle985x.h:5247
__IM uint32_t EN_PRG_DAT_NL
Definition: tle985x.h:5248
__IOM uint32_t BR1_PRE
Definition: tle985x.h:5018
__IOM uint32_t TIREN1
Definition: tle985x.h:4807
__IOM uint32_t P0_PDM4
Definition: tle985x.h:5289
__IM uint32_t APCLK2STS
Definition: tle985x.h:4912
__IOM uint32_t P1_PDM0
Definition: tle985x.h:5325
__IOM uint32_t DU4TRIGGEN
Definition: tle985x.h:5345
__IOM uint32_t T2_SUSP
Definition: tle985x.h:5178
__IOM uint32_t MON2
Definition: tle985x.h:4796
__IOM uint32_t T21_SUSP
Definition: tle985x.h:5181
__OM uint32_t MON2RC
Definition: tle985x.h:5457
__IOM uint32_t COUTS0
Definition: tle985x.h:5116
__IOM uint32_t T21EXCON
Definition: tle985x.h:5145
__IOM uint32_t T13SUSP
Definition: tle985x.h:5177
__IM uint32_t CUS_BSL_SIZE
Definition: tle985x.h:5260
__IOM uint32_t RIEN1
Definition: tle985x.h:4820
__IM uint32_t NVM_SFR_PROT_ERR
Definition: tle985x.h:5271
__OM uint32_t APCLK1SCLR
Definition: tle985x.h:4940
__IOM uint32_t COREL
Definition: tle985x.h:5115
__IOM uint32_t IE1
Definition: tle985x.h:4841
__IM uint32_t DAT_LIN_PW
Definition: tle985x.h:5257
__IM uint32_t WAKEUP
Definition: tle985x.h:5309
__IOM uint32_t BG1_BR_VALUE
Definition: tle985x.h:5034
__OM uint32_t GPT2T6C
Definition: tle985x.h:5474
__IOM uint32_t ADC1_DIS
Definition: tle985x.h:4924
__IOM uint32_t EXINT2_EN
Definition: tle985x.h:4823
__OM uint32_t MON1FC
Definition: tle985x.h:5456
__IOM uint32_t WINBEN
Definition: tle985x.h:4874
__IOM uint32_t STOF_ADDR_OFF_L
Definition: tle985x.h:5385
__IOM uint32_t T2EXCON
Definition: tle985x.h:5144
__IM uint32_t MON3F
Definition: tle985x.h:4694
__OM uint32_t EXINT2RC
Definition: tle985x.h:5446
__IOM uint32_t NMISTOF
Definition: tle985x.h:4777
__IM uint32_t FNMIOWD
Definition: tle985x.h:4741
__IOM uint32_t TIEN1
Definition: tle985x.h:4821
__IOM uint32_t ADC1_CLK_DIV
Definition: tle985x.h:4962
__IM uint32_t CCU6SR2
Definition: tle985x.h:4728
__IOM uint32_t NMIMAP
Definition: tle985x.h:4774
__IOM uint32_t STOF_STS
Definition: tle985x.h:5395
__IM uint32_t MON1R
Definition: tle985x.h:4689
__IM uint32_t MON2R
Definition: tle985x.h:4691
__IOM uint32_t BRDIS
Definition: tle985x.h:5044
__IM uint32_t NVM_ADDR_ERR
Definition: tle985x.h:5270
__OM uint32_t FNMIWDTC
Definition: tle985x.h:4665
__IM uint32_t FNMIMAP
Definition: tle985x.h:4742
__IOM uint32_t WDTREL
Definition: tle985x.h:4992
__IM uint32_t EXINT1R
Definition: tle985x.h:4678
__IM uint32_t GPT2T6
Definition: tle985x.h:5432
__IOM uint32_t MON4
Definition: tle985x.h:4798
__IOM uint32_t SL
Definition: tle985x.h:4850
__OM uint32_t CCU6SR0C
Definition: tle985x.h:5515
__IM uint32_t CCU6SR1
Definition: tle985x.h:4726
__IOM uint32_t P0_PDM5
Definition: tle985x.h:5291
__OM uint32_t ERRSYNC
Definition: tle985x.h:5087
__IOM uint32_t GPT12_SEL
Definition: tle985x.h:5196
__IOM uint32_t MON2IE
Definition: tle985x.h:5485
__OM uint32_t MON4FC
Definition: tle985x.h:5462
__IOM uint32_t RIEN2
Definition: tle985x.h:4824
__IM uint32_t NVM_SFR_ADDR_ERR
Definition: tle985x.h:5272
__IOM uint32_t DU1TRIGGEN
Definition: tle985x.h:5339
__OM uint32_t GPT1T2C
Definition: tle985x.h:5470
__IOM uint32_t CCU_DIS
Definition: tle985x.h:4926
__IOM uint32_t MON4IE
Definition: tle985x.h:5487
__IOM uint32_t WDT1SUSP
Definition: tle985x.h:5182
__IOM uint32_t TCC
Definition: tle985x.h:5317
__IM uint32_t DAT_NL_PW
Definition: tle985x.h:5258
__IOM uint32_t URIOS1
Definition: tle985x.h:5130
__IOM uint32_t BR2_R
Definition: tle985x.h:5057
__IOM uint32_t EXINT1IS
Definition: tle985x.h:5128
__IM uint32_t EN_RD_COD_LIN
Definition: tle985x.h:5243
__OM uint32_t FNMIOWDC
Definition: tle985x.h:4667
__IOM uint32_t SYNEN
Definition: tle985x.h:5049
__OM uint32_t MON3RC
Definition: tle985x.h:5459
__IM uint32_t MON4F
Definition: tle985x.h:4696
__IOM uint32_t SASTATUS
Definition: tle985x.h:5227
__IOM uint32_t WDTIN
Definition: tle985x.h:4869
__OM uint32_t RIR1C
Definition: tle985x.h:5497
__OM uint32_t GPT1T3C
Definition: tle985x.h:5471
__IM uint32_t DIS_RDUS
Definition: tle985x.h:5251
__OM uint32_t CCU6SR2C
Definition: tle985x.h:5519
__IOM uint32_t T2IE
Definition: tle985x.h:5414
__IOM uint32_t EIREN1
Definition: tle985x.h:4806
__OM uint32_t EXINT2FC
Definition: tle985x.h:5447
__IOM uint32_t SECTORINFO
Definition: tle985x.h:5226
__OM uint32_t STOF_STSC
Definition: tle985x.h:5367
__IOM uint32_t GPT12_SUSP
Definition: tle985x.h:5179
__IM uint32_t MON3R
Definition: tle985x.h:4693
__OM uint32_t TIR2C
Definition: tle985x.h:5506
__IM uint32_t
Definition: tle985x.h:4666
__IOM uint32_t P0_PDM6
Definition: tle985x.h:5293
__IOM uint32_t BR1_R
Definition: tle985x.h:5017
__IM uint32_t GPT1T3
Definition: tle985x.h:5429
__IM uint32_t TIR2
Definition: tle985x.h:4715
__IOM uint32_t RAM_VAL_KEYS
Definition: tle985x.h:5232
__IOM uint32_t T12SUSP
Definition: tle985x.h:5176
__IM uint32_t ERRSYN
Definition: tle985x.h:5048
__IM uint32_t FNMISTOF
Definition: tle985x.h:4745
__OM uint32_t CCU6SR1C
Definition: tle985x.h:5517
__IOM uint32_t P0_PDM2
Definition: tle985x.h:5285
__IM uint32_t EOFSYN
Definition: tle985x.h:5047
__IM uint32_t GPT1T4
Definition: tle985x.h:5430
__IM uint32_t RIR1
Definition: tle985x.h:4706
__IM uint32_t APCLK3STS
Definition: tle985x.h:4914
__IM uint32_t EN_RD_DAT_LIN
Definition: tle985x.h:5245
__IM uint32_t NVM_PROT_ERR
Definition: tle985x.h:5269
__IOM uint32_t STOF_ADDR_OFF_H
Definition: tle985x.h:5387
__IOM uint32_t P0_PDM3
Definition: tle985x.h:5287
__IOM uint32_t NMIECC
Definition: tle985x.h:4775
__IOM uint32_t STOF_EN
Definition: tle985x.h:5376
__IM uint32_t APCLK1STS
Definition: tle985x.h:4908
__IM uint32_t EIR1
Definition: tle985x.h:4704
__IOM uint32_t T3IE
Definition: tle985x.h:5415
__IOM uint32_t P1_PDM1
Definition: tle985x.h:5327
__IM uint32_t NVMCLKFAC
Definition: tle985x.h:4973
__IOM uint32_t CLKWDT_IE
Definition: tle985x.h:4884
__IOM uint32_t DPP1_CLK_DIV
Definition: tle985x.h:4964
__IOM uint32_t SSC1_DIS
Definition: tle985x.h:4925
__IM uint32_t BG1_TIM_VALUE
Definition: tle985x.h:5036
__IOM uint32_t NVMIE
Definition: tle985x.h:5206
__OM uint32_t GPT12CRC
Definition: tle985x.h:5475
__IOM uint32_t WDTSUSP
Definition: tle985x.h:5175
__OM uint32_t EXINT1FC
Definition: tle985x.h:5445
__IOM uint32_t U_TX_CONDIS
Definition: tle985x.h:5131
__IM uint32_t ROM_PROT_ERR
Definition: tle985x.h:5273
__IOM uint32_t IE0
Definition: tle985x.h:4833
__IOM uint32_t T2_DIS
Definition: tle985x.h:4927
__OM uint32_t EXINT0FC
Definition: tle985x.h:5443
__IM uint32_t APCLK_ERR_STS
Definition: tle985x.h:4910
__IOM uint32_t GPT12_DIS
Definition: tle985x.h:4928
__IOM uint32_t EXINT0IS
Definition: tle985x.h:5127
__IOM uint32_t SSC2_DIS
Definition: tle985x.h:4930
__IOM uint32_t SSC12_S_MRST_OUTSEL
Definition: tle985x.h:5135
__IOM uint32_t EA
Definition: tle985x.h:4754
__IM uint32_t DIS_RDUS_S0
Definition: tle985x.h:5253
__IM uint32_t EN_RD_CUS_BSL
Definition: tle985x.h:5241
__OM uint32_t GPT1T4C
Definition: tle985x.h:5472
__IOM uint32_t EIREN2
Definition: tle985x.h:4810
__IOM uint32_t BGCLK_DIV
Definition: tle985x.h:4897
__IM uint32_t BRDRV_CLK_ERR_STS
Definition: tle985x.h:4916
__IOM uint32_t LOCKUP_EN
Definition: tle985x.h:4954
__IM uint32_t WDT
Definition: tle985x.h:5008
__IOM uint32_t BG2_BR_VALUE
Definition: tle985x.h:5074
__IOM uint32_t VTOR_BYP
Definition: tle985x.h:4762
__IOM uint32_t SYSCLKSEL
Definition: tle985x.h:4974
__IOM uint32_t RAM_TEST_MODE
Definition: tle985x.h:5233
__IOM uint32_t LOCKUP
Definition: tle985x.h:4952
__IM uint32_t PROTECT_S
Definition: tle985x.h:5105
__IOM uint32_t CRIE
Definition: tle985x.h:5419
__OM uint32_t EXINT0RC
Definition: tle985x.h:5442
__IOM uint32_t APCLK2FAC
Definition: tle985x.h:4894
__IOM uint32_t SSC12_M_SCK_OUTSEL
Definition: tle985x.h:5133
__IOM uint32_t BRDRV_TFILT_DIV
Definition: tle985x.h:5405
__OM uint32_t FNMIMAPC
Definition: tle985x.h:4668
__OM uint32_t APCLK2SCLR
Definition: tle985x.h:4942
__IOM uint32_t SD
Definition: tle985x.h:4852
__IOM uint32_t MON1
Definition: tle985x.h:4795
__IOM uint32_t EXINT0
Definition: tle985x.h:4785
__IM uint32_t CCU6SR0
Definition: tle985x.h:4724
__IOM uint32_t PASS
Definition: tle985x.h:5106
__IOM uint32_t T21EXISCNF
Definition: tle985x.h:5158
__IOM uint32_t EXINT2
Definition: tle985x.h:4787
__IOM uint32_t P0_PDM0
Definition: tle985x.h:5281
__IM uint32_t MON2F
Definition: tle985x.h:4692
__IOM uint32_t EXINT1
Definition: tle985x.h:4786
__IM uint32_t GPT2T5
Definition: tle985x.h:5431
__OM uint32_t WAKEUPC
Definition: tle985x.h:5529
__IOM uint32_t MU_SUSP
Definition: tle985x.h:5184
__IOM uint32_t reg
Definition: tle985x.h:4662
__OM uint32_t MON1RC
Definition: tle985x.h:5455
__IM uint32_t GPT12CR
Definition: tle985x.h:5433
__IOM uint32_t BRDRV_CLK_DIV
Definition: tle985x.h:5403
__OM uint32_t EIR1C
Definition: tle985x.h:5495
__IOM uint32_t WDTWINB
Definition: tle985x.h:5000
__IOM uint32_t NVM_VAL_KEYS
Definition: tle985x.h:5229
__IOM uint32_t NMIWDT
Definition: tle985x.h:4770
__IM uint32_t BG2_TIM_VALUE
Definition: tle985x.h:5076
__IOM uint32_t EN
Definition: tle985x.h:5119
__IOM uint32_t RIE
Definition: tle985x.h:5204
__IM uint32_t EXINT2F
Definition: tle985x.h:4681
__IM uint32_t FNMIWDT
Definition: tle985x.h:4738
__IM uint32_t BRK
Definition: tle985x.h:5046
__IOM uint32_t PD
Definition: tle985x.h:4851
__IOM uint32_t DU2TRIGGEN
Definition: tle985x.h:5341
__IOM uint32_t CPCLK_DIV
Definition: tle985x.h:4900
__IOM uint32_t NVM_DATA_MODE
Definition: tle985x.h:5230
__IOM uint32_t TRIG_CONF
Definition: tle985x.h:5195
__IOM uint32_t MON3IE
Definition: tle985x.h:5486
__IM uint32_t CCU6SR3
Definition: tle985x.h:4730
__IM uint32_t RSBE
Definition: tle985x.h:5218
__IOM uint32_t TIREN2
Definition: tle985x.h:4811
__IOM uint32_t MON3
Definition: tle985x.h:4797
__OM uint32_t EIR2C
Definition: tle985x.h:5505
__OM uint32_t CCU6SR3C
Definition: tle985x.h:5521
__IM uint32_t RESERVED2
Definition: tle985x.h:5109
__IOM uint32_t MRAMINITSTS
Definition: tle985x.h:4983
__IM uint32_t EXINT2R
Definition: tle985x.h:4680
__IOM uint32_t WDTEN
Definition: tle985x.h:4871
__OM uint32_t NVMDBEC
Definition: tle985x.h:5356
__IM uint32_t EXINT1F
Definition: tle985x.h:4679
__IOM uint32_t P1_PDM2
Definition: tle985x.h:5329
__IOM uint32_t T21_DIS
Definition: tle985x.h:4932
__IOM uint32_t NMIOWD
Definition: tle985x.h:4773
__IOM uint32_t APCLK1FAC
Definition: tle985x.h:4892
__IM uint32_t WDTPR
Definition: tle985x.h:4873
__IM uint32_t FNMIECC
Definition: tle985x.h:4743
__IM uint32_t EN_RD_S0
Definition: tle985x.h:5250
__IM uint32_t MON4R
Definition: tle985x.h:4695
__IOM uint32_t GPT12
Definition: tle985x.h:5194
__IOM uint32_t RIREN2
Definition: tle985x.h:4812
__IM uint32_t FNMISUP
Definition: tle985x.h:4744
__OM uint32_t RDBEC
Definition: tle985x.h:5354
__OM uint32_t MON4RC
Definition: tle985x.h:5461
__IOM uint32_t EXINT2IS
Definition: tle985x.h:5129
__IOM uint32_t TIEN2
Definition: tle985x.h:4825
__IM uint32_t DAT_LIN_SIZE
Definition: tle985x.h:5261
__IOM uint32_t CPCLK_SEL
Definition: tle985x.h:4899
__IOM uint32_t NMIOT
Definition: tle985x.h:4772
__IM uint32_t EN_PRG_CUS_BSL
Definition: tle985x.h:5242
__IOM uint32_t SSC12_M_MTSR_OUTSEL
Definition: tle985x.h:5134
__IM uint32_t RESERVED1
Definition: tle985x.h:5011
__IM uint32_t MON1F
Definition: tle985x.h:4690
__IOM uint32_t T6IE
Definition: tle985x.h:5418
__IM uint32_t VERID
Definition: tle985x.h:5095
__IM uint32_t EXINT0F
Definition: tle985x.h:4677
__IM uint32_t COD_LIN_PW
Definition: tle985x.h:5256
__IM uint32_t EXINT0R
Definition: tle985x.h:4676
__IOM uint32_t RIREN1
Definition: tle985x.h:4808
__IOM uint32_t NMISUP
Definition: tle985x.h:4776
__IM uint32_t GPT1T2
Definition: tle985x.h:5428
__OM uint32_t EOFSYNC
Definition: tle985x.h:5086
__IOM uint32_t T21EXIS
Definition: tle985x.h:5156
__OM uint32_t RIR2C
Definition: tle985x.h:5507
__IM uint32_t NVMDBE
Definition: tle985x.h:5216
__IOM uint32_t ADC1_SUSP
Definition: tle985x.h:5185
__IM uint32_t TIR1
Definition: tle985x.h:4705
__IOM uint32_t MON1IE
Definition: tle985x.h:5484
__IOM uint32_t DU3TRIGGEN
Definition: tle985x.h:5343
__OM uint32_t RSBEC
Definition: tle985x.h:5358
__IOM uint32_t TLEN
Definition: tle985x.h:5117
__IM uint32_t CUS_BSL_PW
Definition: tle985x.h:5255
__OM uint32_t APCLK3SCLR
Definition: tle985x.h:4944
__IM uint32_t EN_PRG_COD_LIN
Definition: tle985x.h:5244
__IOM uint32_t URIOS2
Definition: tle985x.h:5167
SCUPM (SCUPM)
Definition: tle985x.h:5545
__OM uint32_t VDD1V5_UV_SC
Definition: tle985x.h:5718
__IOM uint32_t SOWCONF
Definition: tle985x.h:5770
__IM uint32_t CLKWDT_IS
Definition: tle985x.h:5616
__IOM uint32_t VREF1V2_UV_IE
Definition: tle985x.h:5737
__OM uint32_t VDD1V5_UV_ISC
Definition: tle985x.h:5704
__IM uint32_t SYS_SUPPLY_STS
Definition: tle985x.h:5637
__IOM uint32_t AMCLK2_UP_TH
Definition: tle985x.h:5575
__IOM uint32_t VDDEXT_UV_IS
Definition: tle985x.h:5647
__OM uint32_t SYS_OT_SC
Definition: tle985x.h:5596
__IOM uint32_t AMCLK2_LOW_TH
Definition: tle985x.h:5577
__IM uint32_t LIN_FAIL_STS
Definition: tle985x.h:5624
__OM uint32_t VDD5V_UV_SC
Definition: tle985x.h:5716
__IM uint32_t CP_FAIL_IS
Definition: tle985x.h:5608
__IOM uint32_t AMCLK1_UP_TH
Definition: tle985x.h:5571
__IOM uint32_t VS_UV_IE
Definition: tle985x.h:5679
__IOM uint32_t VREF1V2_UV_STS
Definition: tle985x.h:5633
__OM uint32_t VDDEXT_UV_ISC
Definition: tle985x.h:5701
__IOM uint32_t VDD1V5_OV_IE
Definition: tle985x.h:5691
__IOM uint32_t VDDEXT_OV_IS
Definition: tle985x.h:5654
__IOM uint32_t CLKLOSS_RES_SD_DIS
Definition: tle985x.h:5761
__OM uint32_t VDDEXT_UV_SC
Definition: tle985x.h:5715
__IOM uint32_t FAIL_PS_DIS
Definition: tle985x.h:5750
__OM uint32_t SYS_OT_ISC
Definition: tle985x.h:5589
__IOM uint32_t SYS_OT_IE
Definition: tle985x.h:5735
__IOM uint32_t VDD1V5_UV_IE
Definition: tle985x.h:5684
__IOM uint32_t LIN_VS_UV_SD_DIS
Definition: tle985x.h:5752
__IM uint32_t AMCLK2_FREQ
Definition: tle985x.h:5554
__OM uint32_t VDD1V5_OV_ISC
Definition: tle985x.h:5711
__IOM uint32_t SYS_OTWARN_PS_DIS
Definition: tle985x.h:5757
__IM uint32_t AMCLK1_FREQ
Definition: tle985x.h:5551
__OM uint32_t VS_OV_SC
Definition: tle985x.h:5720
__OM uint32_t VREF1V2_UV_SC
Definition: tle985x.h:5598
__IOM uint32_t AMCLK1_UP_HYS
Definition: tle985x.h:5572
__IM uint32_t
Definition: tle985x.h:5553
__IOM uint32_t AMCLK2_UP_HYS
Definition: tle985x.h:5576
__IOM uint32_t CLKLOSS_SD_DIS
Definition: tle985x.h:5759
__OM uint32_t VDD5V_OV_ISC
Definition: tle985x.h:5709
__IOM uint32_t VDD5V_UV_IS
Definition: tle985x.h:5648
__IOM uint32_t VDD1V5_OV_IS
Definition: tle985x.h:5657
__IOM uint32_t WDP_SEL
Definition: tle985x.h:5769
__IOM uint32_t VDDEXT_OV_IE
Definition: tle985x.h:5688
__IOM uint32_t AMCLK1_LOW_TH
Definition: tle985x.h:5573
__OM uint32_t VREF1V2_UV_ISC
Definition: tle985x.h:5591
__OM uint32_t VDD5V_OV_SC
Definition: tle985x.h:5723
__IOM uint32_t CLKWDT_RES_SD_DIS
Definition: tle985x.h:5760
__IOM uint32_t VS_UV_STS
Definition: tle985x.h:5659
__IOM uint32_t VDD1V5_OV_STS
Definition: tle985x.h:5671
__IOM uint32_t SYS_OT_STS
Definition: tle985x.h:5631
__IOM uint32_t SYS_OTWARN_IS
Definition: tle985x.h:5612
__IOM uint32_t AMCLK2_LOW_HYS
Definition: tle985x.h:5578
__OM uint32_t SYS_OTWARN_ISC
Definition: tle985x.h:5588
__IOM uint32_t VS_UV_IS
Definition: tle985x.h:5645
__IOM uint32_t VDDEXT_UV_IE
Definition: tle985x.h:5681
__IOM uint32_t STCALIB
Definition: tle985x.h:5779
__IOM uint32_t VDD1V5_UV_STS
Definition: tle985x.h:5664
__IOM uint32_t VDD1V5_UV_IS
Definition: tle985x.h:5650
__OM uint32_t VDDEXT_OV_ISC
Definition: tle985x.h:5708
__IOM uint32_t CLKWDT_SD_DIS
Definition: tle985x.h:5748
__IOM uint32_t VDD5V_OV_STS
Definition: tle985x.h:5669
__OM uint32_t VDDEXT_OV_SC
Definition: tle985x.h:5722
__IOM uint32_t VS_OV_STS
Definition: tle985x.h:5666
__IM uint32_t RESERVED
Definition: tle985x.h:5565
__IM uint32_t DRV_FAIL_IS
Definition: tle985x.h:5609
__IOM uint32_t VDDEXT_UV_STS
Definition: tle985x.h:5661
__IM uint32_t LIN_FAIL_IS
Definition: tle985x.h:5607
__IOM uint32_t VS_OV_IS
Definition: tle985x.h:5652
__IOM uint32_t VDD5V_OV_IE
Definition: tle985x.h:5689
__IOM uint32_t reg
Definition: tle985x.h:5548
__IOM uint32_t VDD5V_UV_IE
Definition: tle985x.h:5682
__IOM uint32_t VREF1V2_OV_IE
Definition: tle985x.h:5738
__IOM uint32_t VDDEXT_OV_STS
Definition: tle985x.h:5668
__IM uint32_t DRV_FAIL_STS
Definition: tle985x.h:5626
__OM uint32_t VREF1V2_OV_SC
Definition: tle985x.h:5599
__OM uint32_t VDD1V5_OV_SC
Definition: tle985x.h:5725
__IOM uint32_t VREF1V2_UV_IS
Definition: tle985x.h:5618
__OM uint32_t VS_UV_ISC
Definition: tle985x.h:5699
__IM uint32_t RESERVED2
Definition: tle985x.h:5741
__IM uint32_t SYS_SUPPLY_IS
Definition: tle985x.h:5622
__IOM uint32_t VDD5V_UV_STS
Definition: tle985x.h:5662
__IOM uint32_t SYS_VS_OV_SLM_DIS
Definition: tle985x.h:5755
__OM uint32_t VS_OV_ISC
Definition: tle985x.h:5706
__IM uint32_t CP_FAIL_STS
Definition: tle985x.h:5625
__IOM uint32_t VS_OV_IE
Definition: tle985x.h:5686
__OM uint32_t VDD5V_UV_ISC
Definition: tle985x.h:5702
__IM uint32_t HS_FAIL_STS
Definition: tle985x.h:5627
__IOM uint32_t VREF1V2_OV_STS
Definition: tle985x.h:5635
__OM uint32_t SYS_OTWARN_SC
Definition: tle985x.h:5595
__IOM uint32_t SYS_OTWARN_STS
Definition: tle985x.h:5629
__IM uint32_t RESERVED1
Definition: tle985x.h:5581
__IOM uint32_t SYS_OT_IS
Definition: tle985x.h:5614
__OM uint32_t VREF1V2_OV_ISC
Definition: tle985x.h:5593
__IOM uint32_t AMCLK1_LOW_HYS
Definition: tle985x.h:5574
__IOM uint32_t VREF1V2_OV_IS
Definition: tle985x.h:5620
__OM uint32_t VS_UV_SC
Definition: tle985x.h:5713
__IOM uint32_t SYS_OTWARN_IE
Definition: tle985x.h:5734
__IOM uint32_t VDD5V_OV_IS
Definition: tle985x.h:5655
__IM uint32_t HS_FAIL_IS
Definition: tle985x.h:5610
__IOM uint32_t CLKWDT_PD_N
Definition: tle985x.h:5562
__IOM uint32_t SYS_VS_UV_SLM_DIS
Definition: tle985x.h:5754
SSC1 (SSC1)
Definition: tle985x.h:5795
__IOM uint32_t LB
Definition: tle985x.h:5817
__IOM uint32_t AREN
Definition: tle985x.h:5822
__OM uint32_t PECLR
Definition: tle985x.h:5867
__IM uint32_t BE
Definition: tle985x.h:5831
__IM uint32_t TE
Definition: tle985x.h:5828
__OM uint32_t BECLR
Definition: tle985x.h:5868
__IOM uint32_t BEN
Definition: tle985x.h:5821
__IOM uint32_t CIS
Definition: tle985x.h:5803
__IOM uint32_t MIS_0
Definition: tle985x.h:5801
__OM uint32_t TECLR
Definition: tle985x.h:5865
__IM uint32_t
Definition: tle985x.h:5823
__IM uint32_t RE
Definition: tle985x.h:5829
__IM uint32_t PE
Definition: tle985x.h:5830
__IOM uint32_t BM
Definition: tle985x.h:5813
__IOM uint32_t GIS
Definition: tle985x.h:5805
__OM uint32_t RECLR
Definition: tle985x.h:5866
__IOM uint32_t REN
Definition: tle985x.h:5819
__IOM uint32_t SIS
Definition: tle985x.h:5802
__IOM uint32_t TB_VALUE
Definition: tle985x.h:5840
__IOM uint32_t PO
Definition: tle985x.h:5816
__IM uint32_t RB_VALUE
Definition: tle985x.h:5848
__IOM uint32_t MS
Definition: tle985x.h:5824
__IOM uint32_t reg
Definition: tle985x.h:5798
__IOM uint32_t EN
Definition: tle985x.h:5825
__IOM uint32_t HB
Definition: tle985x.h:5814
__IOM uint32_t BR_VALUE
Definition: tle985x.h:5856
__IOM uint32_t MIS_1
Definition: tle985x.h:5804
__IM uint32_t BSY
Definition: tle985x.h:5832
__IOM uint32_t PEN
Definition: tle985x.h:5820
__IM uint32_t BC
Definition: tle985x.h:5826
__IOM uint32_t TEN
Definition: tle985x.h:5818
__IOM uint32_t PH
Definition: tle985x.h:5815
SSC2 (SSC2)
Definition: tle985x.h:5884
__IOM uint32_t LB
Definition: tle985x.h:5906
__IOM uint32_t AREN
Definition: tle985x.h:5911
__OM uint32_t PECLR
Definition: tle985x.h:5956
__IM uint32_t BE
Definition: tle985x.h:5920
__IM uint32_t TE
Definition: tle985x.h:5917
__OM uint32_t BECLR
Definition: tle985x.h:5957
__IOM uint32_t BEN
Definition: tle985x.h:5910
__IOM uint32_t CIS
Definition: tle985x.h:5892
__IOM uint32_t MIS_0
Definition: tle985x.h:5890
__OM uint32_t TECLR
Definition: tle985x.h:5954
__IM uint32_t
Definition: tle985x.h:5912
__IM uint32_t RE
Definition: tle985x.h:5918
__IM uint32_t PE
Definition: tle985x.h:5919
__IOM uint32_t BM
Definition: tle985x.h:5902
__IOM uint32_t GIS
Definition: tle985x.h:5894
__OM uint32_t RECLR
Definition: tle985x.h:5955
__IOM uint32_t REN
Definition: tle985x.h:5908
__IOM uint32_t SIS
Definition: tle985x.h:5891
__IOM uint32_t TB_VALUE
Definition: tle985x.h:5929
__IOM uint32_t PO
Definition: tle985x.h:5905
__IM uint32_t RB_VALUE
Definition: tle985x.h:5937
__IOM uint32_t MS
Definition: tle985x.h:5913
__IOM uint32_t reg
Definition: tle985x.h:5887
__IOM uint32_t EN
Definition: tle985x.h:5914
__IOM uint32_t HB
Definition: tle985x.h:5903
__IOM uint32_t BR_VALUE
Definition: tle985x.h:5945
__IOM uint32_t MIS_1
Definition: tle985x.h:5893
__IM uint32_t BSY
Definition: tle985x.h:5921
__IOM uint32_t PEN
Definition: tle985x.h:5909
__IM uint32_t BC
Definition: tle985x.h:5915
__IOM uint32_t TEN
Definition: tle985x.h:5907
__IOM uint32_t PH
Definition: tle985x.h:5904
TIMER21 (TIMER21)
Definition: tle985x.h:6053
__IOM uint32_t EDGESEL
Definition: tle985x.h:6076
__IM uint32_t EXF2
Definition: tle985x.h:6064
__IOM uint32_t T2RHEN
Definition: tle985x.h:6077
__IOM uint32_t RCH2
Definition: tle985x.h:6087
__IOM uint32_t T2H
Definition: tle985x.h:6097
__IOM uint32_t PREN
Definition: tle985x.h:6075
__IOM uint32_t T2PRE
Definition: tle985x.h:6074
__OM uint32_t TF2CLR
Definition: tle985x.h:6108
__IOM uint32_t CP_RL2
Definition: tle985x.h:6059
__IOM uint32_t RCL2
Definition: tle985x.h:6086
__IM uint32_t
Definition: tle985x.h:6063
__IOM uint32_t TF2EN
Definition: tle985x.h:6117
__IOM uint32_t T2REGS
Definition: tle985x.h:6078
__IOM uint32_t DCEN
Definition: tle985x.h:6073
__OM uint32_t EXF2CLR
Definition: tle985x.h:6107
__IOM uint32_t EXEN2
Definition: tle985x.h:6062
__IM uint32_t RESERVED
Definition: tle985x.h:6090
__IOM uint32_t EXF2EN
Definition: tle985x.h:6116
__IM uint32_t TF2
Definition: tle985x.h:6065
__IOM uint32_t reg
Definition: tle985x.h:6056
__IOM uint32_t C_T2
Definition: tle985x.h:6060
__IOM uint32_t TR2
Definition: tle985x.h:6061
__IOM uint32_t T2L
Definition: tle985x.h:6096
__IM uint32_t RESERVED1
Definition: tle985x.h:6100
TIMER2 (TIMER2)
Definition: tle985x.h:5973
__IOM uint32_t EDGESEL
Definition: tle985x.h:5996
__IM uint32_t EXF2
Definition: tle985x.h:5984
__IOM uint32_t T2RHEN
Definition: tle985x.h:5997
__IOM uint32_t RCH2
Definition: tle985x.h:6007
__IOM uint32_t T2H
Definition: tle985x.h:6017
__IOM uint32_t PREN
Definition: tle985x.h:5995
__IOM uint32_t T2PRE
Definition: tle985x.h:5994
__OM uint32_t TF2CLR
Definition: tle985x.h:6028
__IOM uint32_t CP_RL2
Definition: tle985x.h:5979
__IOM uint32_t RCL2
Definition: tle985x.h:6006
__IM uint32_t
Definition: tle985x.h:5983
__IOM uint32_t TF2EN
Definition: tle985x.h:6037
__IOM uint32_t T2REGS
Definition: tle985x.h:5998
__IOM uint32_t DCEN
Definition: tle985x.h:5993
__OM uint32_t EXF2CLR
Definition: tle985x.h:6027
__IOM uint32_t EXEN2
Definition: tle985x.h:5982
__IM uint32_t RESERVED
Definition: tle985x.h:6010
__IOM uint32_t EXF2EN
Definition: tle985x.h:6036
__IM uint32_t TF2
Definition: tle985x.h:5985
__IOM uint32_t reg
Definition: tle985x.h:5976
__IOM uint32_t C_T2
Definition: tle985x.h:5980
__IOM uint32_t TR2
Definition: tle985x.h:5981
__IOM uint32_t T2L
Definition: tle985x.h:6016
__IM uint32_t RESERVED1
Definition: tle985x.h:6020
UART1 (UART1)
Definition: tle985x.h:6133
__OM uint32_t TICLR
Definition: tle985x.h:6164
__IOM uint32_t SM2
Definition: tle985x.h:6144
__IOM uint32_t RB8
Definition: tle985x.h:6141
__IOM uint32_t SM0
Definition: tle985x.h:6147
__IOM uint32_t TB8
Definition: tle985x.h:6142
__OM uint32_t RICLR
Definition: tle985x.h:6163
__IOM uint32_t REN
Definition: tle985x.h:6143
__IOM uint32_t RI
Definition: tle985x.h:6139
__IOM uint32_t reg
Definition: tle985x.h:6136
__IOM uint32_t TI
Definition: tle985x.h:6140
__OM uint32_t RB8CLR
Definition: tle985x.h:6165
__IOM uint32_t SM1
Definition: tle985x.h:6146
__IOM uint32_t VAL
Definition: tle985x.h:6155
UART2 (UART2)
Definition: tle985x.h:6181
__OM uint32_t TICLR
Definition: tle985x.h:6212
__IOM uint32_t SM2
Definition: tle985x.h:6192
__IOM uint32_t RB8
Definition: tle985x.h:6189
__IOM uint32_t SM0
Definition: tle985x.h:6195
__IOM uint32_t TB8
Definition: tle985x.h:6190
__OM uint32_t RICLR
Definition: tle985x.h:6211
__IOM uint32_t REN
Definition: tle985x.h:6191
__IOM uint32_t RI
Definition: tle985x.h:6187
__IOM uint32_t reg
Definition: tle985x.h:6184
__IOM uint32_t TI
Definition: tle985x.h:6188
__OM uint32_t RB8CLR
Definition: tle985x.h:6213
__IOM uint32_t SM1
Definition: tle985x.h:6194
__IOM uint32_t VAL
Definition: tle985x.h:6203