Infineon MOTIX™ MCU TLE985x Device Family SDK
hs.h
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39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** TS T&S **
45 ** BG Blandine Guillot **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.2.0: 2018-02-13, TS: Initial version of revision history **
52 ** V0.2.1: 2018-10-17, TS: PWMSRCSEL initialization added **
53 ** V0.2.2: 2019-01-28, TS: __STATIC_INLINE changed to INLINE **
54 ** Doxygen update **
55 ** Revision history moved from hs.c to hs.h **
56 ** New Mask Macros added **
57 ** V0.2.3: 2020-03-02, BG: Updated revision history format **
58 ** V0.2.4: 2022-01-21, JO: EP-934: Updated copyright and branding **
59 ** V0.2.5: 2023-08-28, JO: EP-435: Removed ARMCC v6 compiler warnings **
60 *******************************************************************************/
61 
62 #ifndef HS_H
63 #define HS_H
64 
65 /*******************************************************************************
66 ** Includes **
67 *******************************************************************************/
68 #include "tle985x.h"
69 #include "types.h"
70 #include "sfr_access.h"
71 
72 /*******************************************************************************
73 ** Global Constant Declarations **
74 *******************************************************************************/
76 #define HS_IRQ_BITS 0x000000E0
77 
79 #define HS_CONF_MASK 0x0000000F
80 
81 /*******************************************************************************
82 ** Global Type Definitions **
83 *******************************************************************************/
87 typedef enum
88 {
89  Ch_HS_Off = 0u,
90  Ch_HS_En = 1u,
91  Ch_HS_PWM = 3u,
92  Ch_HS_On = 5u,
93  Ch_HS_Ol = 9u
95 
99 typedef enum
100 {
101  HS_OT_ISC = 0x00000020u,
102  HS_OL_ISC = 0x00000040u,
103  HS_OC_ISC = 0x00000080u,
104  HS_OT_SC = 0x00002000u,
105  HS_OL_SC = 0x00004000u
107 
111 typedef enum
112 {
113  HS_Int_Off = 0U,
114  HS_Int_OT = 1U,
115  HS_Int_OL = 2U,
116  HS_Int_OC = 4U
118 
119 /*******************************************************************************
120 ** Global Function Declarations **
121 *******************************************************************************/
126 void HS_Init(void);
127 
128 /*******************************************************************************
129 ** Inline Function Declarations **
130 *******************************************************************************/
150 INLINE void HS_Clr_Sts(THs_Sts Sts_Bit);
151 
171 INLINE void HS_Set_Int_Channel(THs_Int HS1_Int);
172 
187 INLINE void HS_Set_Conf(THs_HS1_Cfg HS1_Cfg);
188 
206 INLINE void HS_HS1_OT_Int_Clr(void);
207 
225 INLINE void HS_HS1_OL_Int_Clr(void);
226 
244 INLINE void HS_HS1_OC_Int_Clr(void);
245 
261 INLINE void HS_HS1_OT_SC_Clr(void);
262 
278 INLINE void HS_HS1_OL_SC_Clr(void);
279 
297 INLINE void HS_HS1_OT_Int_En(void);
298 
317 INLINE void HS_HS1_OT_Int_Dis(void);
318 
336 INLINE void HS_HS1_OL_Int_En(void);
337 
356 INLINE void HS_HS1_OL_Int_Dis(void);
357 
375 INLINE void HS_HS1_OC_Int_En(void);
376 
395 INLINE void HS_HS1_OC_Int_Dis(void);
396 
397 /*******************************************************************************
398 ** Inline Function Definitions **
399 *******************************************************************************/
401 {
402  /* set HS1_Int */
403  Field_Mod32(&HS->IRQEN.reg, (uint8)HS_IRQEN_HS1_OT_IEN_Pos, ((uint32)HS1_Int << (uint8)5), (uint32)HS1_Int);
404 
405  /* enable HS interrupt node */
407  {
409  }
410 }
411 
412 INLINE void HS_Clr_Sts(THs_Sts Sts_Bit)
413 {
414  Field_Wrt32all(&HS->IRQCLR.reg, (uint32)Sts_Bit);
415  /* add an extra clear access in order to ensure the clear of */
416  /* the status flags is executed before the status flags are read again */
417  Field_Wrt32all(&HS->IRQCLR.reg, (uint32)0);
418 }
419 
421 {
422  Field_Mod32(&HS->CTRL.reg, (uint8)HS_CTRL_HS1_EN_Pos, HS_CONF_MASK, (uint8)HS1_Cfg);
423 }
424 
426 {
428 }
429 
431 {
433 }
434 
436 {
438 }
439 
441 {
443 }
444 
446 {
448 }
449 
451 {
453 }
454 
456 {
458 }
459 
461 {
463 }
464 
466 {
468 }
469 
471 {
473 }
474 
476 {
478 }
479 
480 #endif
#define HS
Definition: tle985x.h:6271
#define CPU
Definition: tle985x.h:6269
#define HS_IRQEN_HS1_OL_IEN_Msk
Definition: tle985x.h:8975
#define HS_IRQEN_HS1_OT_IEN_Msk
Definition: tle985x.h:8977
#define HS_CTRL_HS1_EN_Pos
Definition: tle985x.h:8958
#define CPU_NVIC_ISER_Int_HS_Pos
Definition: tle985x.h:8653
#define HS_IRQEN_HS1_OL_IEN_Pos
Definition: tle985x.h:8974
#define CPU_NVIC_ISER_Int_HS_Msk
Definition: tle985x.h:8654
#define HS_IRQCLR_HS1_OL_ISC_Pos
Definition: tle985x.h:8967
#define HS_IRQCLR_HS1_OL_ISC_Msk
Definition: tle985x.h:8968
#define HS_IRQCLR_HS1_OL_SC_Pos
Definition: tle985x.h:8961
#define HS_IRQCLR_HS1_OC_ISC_Msk
Definition: tle985x.h:8966
#define HS_IRQCLR_HS1_OT_ISC_Msk
Definition: tle985x.h:8970
#define HS_IRQEN_HS1_OT_IEN_Pos
Definition: tle985x.h:8976
#define HS_IRQCLR_HS1_OL_SC_Msk
Definition: tle985x.h:8962
#define HS_IRQCLR_HS1_OT_SC_Msk
Definition: tle985x.h:8964
#define HS_IRQCLR_HS1_OC_ISC_Pos
Definition: tle985x.h:8965
#define HS_IRQEN_HS1_OC_IEN_Pos
Definition: tle985x.h:8972
#define HS_IRQEN_HS1_OC_IEN_Msk
Definition: tle985x.h:8973
#define HS_IRQCLR_HS1_OT_SC_Pos
Definition: tle985x.h:8963
#define HS_IRQCLR_HS1_OT_ISC_Pos
Definition: tle985x.h:8969
INLINE void HS_Set_Conf(THs_HS1_Cfg HS1_Cfg)
Sets the High-Side Switch in the desired state.
Definition: hs.h:420
INLINE void HS_HS1_OT_Int_Clr(void)
Clears HS1 Overtemperature interrupt flag.
Definition: hs.h:425
#define HS_IRQ_BITS
HS Interrupt Mask.
Definition: hs.h:76
INLINE void HS_HS1_OL_Int_En(void)
Enables HS1 Open Load interrupt.
Definition: hs.h:460
INLINE void HS_HS1_OL_SC_Clr(void)
Clears HS1 Open Load Status.
Definition: hs.h:445
INLINE void HS_HS1_OC_Int_Clr(void)
Clears HS1 Overcurrent interrupt flag.
Definition: hs.h:435
THs_HS1_Cfg
This enum lists the High Side channel configuration.
Definition: hs.h:88
@ Ch_HS_On
channel enabled and static on
Definition: hs.h:92
@ Ch_HS_PWM
channel enabled with PWM (CCU6 connection)
Definition: hs.h:91
@ Ch_HS_Ol
channel enabled and Open Load on
Definition: hs.h:93
@ Ch_HS_En
channel enabled
Definition: hs.h:90
@ Ch_HS_Off
channel disabled
Definition: hs.h:89
THs_Sts
This enum lists the High Side channel configuration Mask Status.
Definition: hs.h:100
@ HS_OL_ISC
Over-Load interrupt Mask
Definition: hs.h:102
@ HS_OT_SC
Over-Temperature Mask
Definition: hs.h:104
@ HS_OT_ISC
Over-Temperature interrupt Mask
Definition: hs.h:101
@ HS_OL_SC
Over-Load Mask
Definition: hs.h:105
@ HS_OC_ISC
Over-Current interrupt Mask
Definition: hs.h:103
INLINE void HS_HS1_OL_Int_Dis(void)
Disables HS1 Open Load interrupt.
Definition: hs.h:465
INLINE void HS_HS1_OT_Int_Dis(void)
Disables HS1 Overtemperature interrupt.
Definition: hs.h:455
INLINE void HS_HS1_OC_Int_Dis(void)
Disables HS1 Overcurrent interrupt.
Definition: hs.h:475
INLINE void HS_HS1_OT_Int_En(void)
Enables HS1 Overtemperature interrupt.
Definition: hs.h:450
INLINE void HS_HS1_OL_Int_Clr(void)
Clears HS1 Open Load interrupt flag.
Definition: hs.h:430
THs_Int
This enum lists the High Side channel Interrupt configuration.
Definition: hs.h:112
@ HS_Int_OL
Over-Load interrupt enable
Definition: hs.h:115
@ HS_Int_OC
Over-Current interrupt enable
Definition: hs.h:116
@ HS_Int_OT
Over-Temperature interrupt enable
Definition: hs.h:114
@ HS_Int_Off
all interrupts disable
Definition: hs.h:113
INLINE void HS_HS1_OC_Int_En(void)
Enables HS1 Overcurrent interrupt.
Definition: hs.h:470
INLINE void HS_HS1_OT_SC_Clr(void)
Clears HS1 Overtemperature Status.
Definition: hs.h:440
INLINE void HS_Clr_Sts(THs_Sts Sts_Bit)
Clears High-Side Switch individual status flags.
Definition: hs.h:412
INLINE void HS_Set_Int_Channel(THs_Int HS1_Int)
Sets High-Side Switch Interrupt Enable.
Definition: hs.h:400
void HS_Init(void)
Initializes the HS module.
#define HS_CONF_MASK
HS Interrupt Mask.
Definition: hs.h:79
SFR low level access library.
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:448
INLINE void Field_Wrt32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:358
INLINE void Field_Wrt32all(volatile uint32 *reg, uint32 val)
This function writes an 32-bit register directly, no mask/position needed.
Definition: sfr_access.h:363
INLINE void Field_Mod32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:378
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155