Infineon MOTIX™ MCU TLE985x Device Family SDK
pmu.h
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39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** TS T&S **
45 ** BG Blandine Guillot **
46 *******************************************************************************/
47 
48 /*******************************************************************************
49 ** Revision Control History **
50 ********************************************************************************
51 ** V0.2.0: 2018-02-13, TS: Initial version of revision history **
52 ** V0.2.1: 2019-01-28, TS: __STATIC_INLINE changed to INLINE **
53 ** Doxygen update **
54 ** Revision history moved from pmu.c to pmu.h **
55 ** PMU Reset Mask macro added **
56 ** PMU_VDDEXT_On function updated **
57 ** PMU_VDDEXT_OT_Int_Clr, PMU_VDDEXT_UV_Int_Clr, **
58 ** PMU_VDDEXT_OT_Clr and PMU_VDDEXT_Error_Clear **
59 ** functions updated **
60 ** V0.2.2: 2020-03-02, BG: Updated revision history format **
61 ** V0.2.3: 2022-01-21, JO: EP-934: Updated copyright and branding **
62 ** V0.2.4: 2023-08-28, JO: EP-435: Removed ARMCC v6 compiler warnings **
63 *******************************************************************************/
64 
65 #ifndef PMU_H
66 #define PMU_H
67 
68 /*******************************************************************************
69 ** Includes **
70 *******************************************************************************/
71 #include "tle985x.h"
72 #include "types.h"
73 #include "sfr_access.h"
74 
75 /*******************************************************************************
76 ** Global Macro Definitions **
77 *******************************************************************************/
79 #define PMU_RESET_STS_LOCKUP (0x0400u)
81 #define PMU_RESET_STS_PMU_SOFT (0x0200u)
83 #define PMU_RESET_STS_IntWDT (0x0100u)
85 #define PMU_RESET_STS_POR (0x0080u)
87 #define PMU_RESET_STS_PIN (0x0040u)
89 #define PMU_RESET_STS_WDT1 (0x0020u)
91 #define PMU_RESET_STS_ClkWDT (0x0010u)
93 #define PMU_RESET_STS_LPR (0x0008u)
95 #define PMU_RESET_STS_SLEEP (0x0004u)
97 #define PMU_RESET_STS_WAKE (0x0002u)
99 #define PMU_RESET_STS_SYS_FAIL (0x0001u)
100 
102 #define PMU_VDDEXT_OT_SC (0x2000u)
104 #define PMU_VDDEXT_UV_ISC (0x1000u)
106 #define PMU_VDDEXT_OT_ISC (0x0800u)
108 #define PMU_VDDEXT_STABLE (0x0080u)
110 #define PMU_VDDEXT_OVERTEMP (0x0040u)
112 #define PMU_VDDEXT_OVERTEMPST (0x0020u)
114 #define PMU_VDDEXT_UNDERVOLT (0x0010u)
116 #define PMU_VDDEXT_OVERTEMPIN (0x0008u)
118 #define PMU_VDDEXT_IE (0x0004u)
120 #define PMU_VDDEXT_CYC_EN (0x0002u)
122 #define PMU_VDDEXT_ENABLE (0x0001u)
123 
125 #define PMU_RESET_MASK (0x7FFu)
126 
127 /*******************************************************************************
128 ** Global Function Declarations **
129 *******************************************************************************/
134 void PMU_Init(void);
135 
153 bool PMU_VDDEXT_On(void);
154 
155 /*******************************************************************************
156 ** Inline Function Declarations **
157 *******************************************************************************/
175 INLINE void PMU_VDDEXT_Int_En(void);
176 
195 INLINE void PMU_VDDEXT_Int_Dis(void);
196 
214 INLINE void PMU_VDDC_Int_En(void);
215 
234 INLINE void PMU_VDDC_Int_Dis(void);
235 
253 INLINE void PMU_VDDP_Int_En(void);
254 
273 INLINE void PMU_VDDP_Int_Dis(void);
274 
291 INLINE void PMU_OT_Int_En(void);
292 
310 INLINE void PMU_OT_Int_Dis(void);
311 
329 INLINE void PMU_VDDEXT_OT_Int_Clr(void);
330 
348 INLINE void PMU_VDDEXT_UV_Int_Clr(void);
349 
362 INLINE void PMU_VDDEXT_OT_Clr(void);
363 
381 INLINE void PMU_VDDC_OV_Clr(void);
382 
400 INLINE void PMU_VDDC_OL_Clr(void);
401 
419 INLINE void PMU_VDDP_OV_Clr(void);
420 
438 INLINE void PMU_VDDP_OL_Clr(void);
439 
440 
457 INLINE void PMU_PMU_OT_Clr(void);
458 
476 INLINE void WAKEUP_Int_En(void);
477 
496 INLINE void WAKEUP_Int_Dis(void);
497 
515 INLINE void WAKEUP_Int_Clr(void);
516 
529 INLINE void PCU_CLK_Loss_Rst_En(void);
530 
543 INLINE void PCU_CLK_Loss_Rst_Dis(void);
544 
557 INLINE void PCU_CLKWDT_Rst_En(void);
558 
571 INLINE void PCU_CLKWDT_Rst_Dis(void);
572 
585 INLINE void PCU_CLK_Loss_SD_En(void);
586 
599 INLINE void PCU_CLK_Loss_SD_Dis(void);
600 
613 INLINE void PCU_SYS_OTWARN_PS_En(void);
614 
627 INLINE void PCU_SYS_OTWARN_PS_Dis(void);
628 
641 INLINE void PCU_SYS_VS_OV_SLM_En(void);
642 
655 INLINE void PCU_SYS_VS_OV_SLM_Dis(void);
656 
669 INLINE void PCU_SYS_VS_UV_SLM_En(void);
670 
683 INLINE void PCU_SYS_VS_UV_SLM_Dis(void);
684 
697 INLINE void PCU_LIN_VS_UV_SD_En(void);
698 
711 INLINE void PCU_LIN_VS_UV_SD_Dis(void);
712 
725 INLINE void PCU_FAIL_PS_En(void);
726 
739 INLINE void PCU_FAIL_PS_Dis(void);
740 
753 INLINE void PCU_CLKWDT_SD_En(void);
754 
767 INLINE void PCU_CLKWDT_SD_Dis(void);
768 
787 
803 INLINE void PMU_Clear_Reset_Status(void);
804 
823 
838 INLINE void PMU_VDDEXT_Error_Clear(uint16 ErrorFlagMask);
839 
854 INLINE void PMU_VDDEXT_Set(uint16 FlagMask);
855 
856 /*******************************************************************************
857 ** Inline Function Definitions **
858 *******************************************************************************/
860 {
862 }
863 
865 {
867 }
868 
870 {
872 }
873 
875 {
877 }
878 
880 {
882 }
883 
885 {
887 }
888 
890 {
892 }
893 
895 {
897 }
898 
900 {
902 }
903 
905 {
907 }
908 
910 {
912 }
913 
915 {
917 }
918 
920 {
922 }
923 
925 {
927 }
928 
930 {
932 }
933 
935 {
937 }
938 
940 {
942 }
943 
945 {
947 }
948 
950 {
952 }
953 
955 {
957 }
958 
960 {
962 }
963 
965 {
967 }
968 
970 {
972 }
973 
975 {
977 }
978 
980 {
982 }
983 
985 {
987 }
988 
990 {
992 }
993 
995 {
997 }
998 
1000 {
1002 }
1003 
1005 {
1007 }
1008 
1010 {
1012 }
1013 
1015 {
1017 }
1018 
1020 {
1022 }
1023 
1025 {
1027 }
1028 
1030 {
1032 }
1033 
1035 {
1037 }
1038 
1040 {
1042 }
1043 
1045 {
1047 }
1048 
1050 {
1051  Field_Clr32(&PMU->RESET_STS.reg, (uint32)PMU_RESET_MASK);
1052 }
1053 
1055 {
1057 
1059 }
1060 
1062 {
1063  Field_Clr32(&PMU->VDDEXT_CTRL.reg, (uint32)ErrorFlagMask);
1064 }
1065 
1067 {
1068  Field_Mod32(&PMU->VDDEXT_CTRL.reg, (uint8)PMU_VDDEXT_CTRL_VDDEXT_ENABLE_Pos, FlagMask, FlagMask);
1069 }
1070 
1071 #endif
#define SCUPM
Definition: tle985x.h:6278
#define PMU
Definition: tle985x.h:6275
#define SCU
Definition: tle985x.h:6277
#define SCUPM_PCU_CTRL_STS_SYS_OTWARN_PS_DIS_Msk
Definition: tle985x.h:10446
#define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Msk
Definition: tle985x.h:10452
#define PMU_VDDEXT_CTRL_VDDEXT_OT_ISC_Msk
Definition: tle985x.h:9409
#define SCU_IRCON5CLR_WAKEUPC_Msk
Definition: tle985x.h:10074
#define PMU_VDDEXT_CTRL_VDDEXT_ENABLE_Pos
Definition: tle985x.h:9424
#define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Pos
Definition: tle985x.h:10455
#define SCUPM_PCU_CTRL_STS_SYS_VS_UV_SLM_DIS_Msk
Definition: tle985x.h:10450
#define PMU_VDDEXT_CTRL_VDDEXT_UV_ISC_Pos
Definition: tle985x.h:9406
#define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Msk
Definition: tle985x.h:10442
#define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_SC_Pos
Definition: tle985x.h:9387
#define PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Msk
Definition: tle985x.h:9398
#define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Pos
Definition: tle985x.h:10443
#define PMU_RESET_STS_SYS_FAIL_Pos
Definition: tle985x.h:9357
#define PMU_VDDEXT_CTRL_VDDEXT_STABLE_Msk
Definition: tle985x.h:9411
#define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_SC_Pos
Definition: tle985x.h:9385
#define PMU_OT_CTRL_PMU_OT_INT_EN_Msk
Definition: tle985x.h:9330
#define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_SC_Msk
Definition: tle985x.h:9380
#define PMU_SUPPLY_STS_PMU_5V_OVERLOAD_SC_Pos
Definition: tle985x.h:9379
#define PMU_SUPPLY_STS_PMU_1V5_FAIL_EN_Pos
Definition: tle985x.h:9397
#define PMU_VDDEXT_CTRL_VDDEXT_OT_SC_Pos
Definition: tle985x.h:9404
#define SCUPM_PCU_CTRL_STS_LIN_VS_UV_SD_DIS_Pos
Definition: tle985x.h:10451
#define SCU_WAKECON_WAKEUPEN_Pos
Definition: tle985x.h:10385
#define SCUPM_PCU_CTRL_STS_CLKLOSS_RES_SD_DIS_Msk
Definition: tle985x.h:10440
#define PMU_SUPPLY_STS_PMU_OVERTEMP_SC_Pos
Definition: tle985x.h:9383
#define PMU_SUPPLY_STS_PMU_1V5_OVERVOLT_SC_Msk
Definition: tle985x.h:9388
#define SCU_IRCON5CLR_WAKEUPC_Pos
Definition: tle985x.h:10073
#define PMU_VDDEXT_CTRL_VDDEXT_OT_SC_Msk
Definition: tle985x.h:9405
#define PMU_VDDEXT_CTRL_VDDEXT_FAIL_EN_Pos
Definition: tle985x.h:9420
#define SCU_WAKECON_WAKEUPEN_Msk
Definition: tle985x.h:10386
#define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_SC_Pos
Definition: tle985x.h:9381
#define SCUPM_PCU_CTRL_STS_CLKWDT_SD_DIS_Msk
Definition: tle985x.h:10456
#define PMU_VDDEXT_CTRL_VDDEXT_FAIL_EN_Msk
Definition: tle985x.h:9421
#define PMU_OT_CTRL_PMU_OT_INT_EN_Pos
Definition: tle985x.h:9329
#define PMU_SUPPLY_STS_PMU_5V_OVERVOLT_SC_Msk
Definition: tle985x.h:9382
#define PMU_VDDEXT_CTRL_VDDEXT_STABLE_Pos
Definition: tle985x.h:9410
#define PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Msk
Definition: tle985x.h:9390
#define PMU_VDDEXT_CTRL_VDDEXT_UV_ISC_Msk
Definition: tle985x.h:9407
#define PMU_VDDEXT_CTRL_VDDEXT_ENABLE_Msk
Definition: tle985x.h:9425
#define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Msk
Definition: tle985x.h:10454
#define SCUPM_PCU_CTRL_STS_CLKWDT_RES_SD_DIS_Pos
Definition: tle985x.h:10441
#define SCUPM_PCU_CTRL_STS_SYS_VS_UV_SLM_DIS_Pos
Definition: tle985x.h:10449
#define PMU_SUPPLY_STS_PMU_1V5_OVERLOAD_SC_Msk
Definition: tle985x.h:9386
#define SCUPM_PCU_CTRL_STS_CLKLOSS_RES_SD_DIS_Pos
Definition: tle985x.h:10439
#define SCUPM_PCU_CTRL_STS_SYS_OTWARN_PS_DIS_Pos
Definition: tle985x.h:10445
#define SCUPM_PCU_CTRL_STS_SYS_VS_OV_SLM_DIS_Pos
Definition: tle985x.h:10447
#define PMU_SUPPLY_STS_PMU_OVERTEMP_SC_Msk
Definition: tle985x.h:9384
#define SCUPM_PCU_CTRL_STS_CLKLOSS_SD_DIS_Msk
Definition: tle985x.h:10444
#define SCUPM_PCU_CTRL_STS_SYS_VS_OV_SLM_DIS_Msk
Definition: tle985x.h:10448
#define SCUPM_PCU_CTRL_STS_FAIL_PS_DIS_Pos
Definition: tle985x.h:10453
#define PMU_SUPPLY_STS_PMU_5V_FAIL_EN_Pos
Definition: tle985x.h:9389
#define PMU_VDDEXT_CTRL_VDDEXT_OT_ISC_Pos
Definition: tle985x.h:9408
INLINE void PCU_SYS_VS_UV_SLM_Dis(void)
Disables VS Undervoltage Shutdown for peripherals.
Definition: pmu.h:1009
INLINE void PCU_CLKWDT_SD_En(void)
Enables Power Modules Clock Watchdog Shutdown.
Definition: pmu.h:1034
INLINE void PCU_SYS_VS_OV_SLM_Dis(void)
Disables VS Overvoltage Shutdown for peripherals.
Definition: pmu.h:999
INLINE void PMU_VDDEXT_UV_Int_Clr(void)
Clears VDDEXT Supply Undervoltage interrupt flag.
Definition: pmu.h:904
INLINE void PCU_SYS_OTWARN_PS_En(void)
Enables System Overtemperature Warning Power Switches Shutdown.
Definition: pmu.h:984
INLINE void PCU_SYS_OTWARN_PS_Dis(void)
Disables System Overtemperature Warning Power Switches Shutdown.
Definition: pmu.h:989
INLINE void PCU_FAIL_PS_Dis(void)
Disables LIN Tx and HS Switch off.
Definition: pmu.h:1029
INLINE void PMU_VDDP_Int_Dis(void)
Disables of VDDP status information as interrupt source.
Definition: pmu.h:884
INLINE void PCU_CLK_Loss_SD_Dis(void)
Disables System Loss of Clock Shutdown.
Definition: pmu.h:979
INLINE void PCU_SYS_VS_OV_SLM_En(void)
Enables VS Overvoltage Shutdown for peripherals.
Definition: pmu.h:994
INLINE uint8 PMU_VDDEXT_Off(void)
Switches VDDEXT off and reads the stability Status of VDDEXT.
Definition: pmu.h:1054
INLINE void PCU_CLKWDT_Rst_En(void)
Enables Clock Watchdog Reset.
Definition: pmu.h:964
#define PMU_RESET_MASK
PMU Reset Status Flag Mask.
Definition: pmu.h:125
INLINE void PMU_VDDP_Int_En(void)
Enables of VDDP status information as interrupt source.
Definition: pmu.h:879
INLINE void PMU_VDDEXT_Int_Dis(void)
Disables of VDDEXT Supply status information as interrupt source.
Definition: pmu.h:864
INLINE void PCU_LIN_VS_UV_SD_Dis(void)
Disables LIN Module VS Undervoltage Transmitter Shutdown.
Definition: pmu.h:1019
INLINE void PCU_CLKWDT_Rst_Dis(void)
Disables Clock Watchdog Reset.
Definition: pmu.h:969
INLINE void PCU_LIN_VS_UV_SD_En(void)
Enables LIN Module VS Undervoltage Transmitter Shutdown.
Definition: pmu.h:1014
INLINE void PMU_VDDEXT_Int_En(void)
Enables of VDDEXT Supply status information as interrupt source.
Definition: pmu.h:859
void PMU_Init(void)
Initializes the PMU module.
INLINE uint16 PMU_Get_Reset_Status(void)
Reads out the Reset Status register.
Definition: pmu.h:1044
INLINE void PCU_CLK_Loss_SD_En(void)
Enables System Loss of Clock Shutdown.
Definition: pmu.h:974
INLINE void PMU_Clear_Reset_Status(void)
Clears the Reset Status register.
Definition: pmu.h:1049
bool PMU_VDDEXT_On(void)
Turns VDDEXT on.
INLINE void PMU_VDDEXT_OT_Clr(void)
Clears VDDEXT Supply Overvoltage Status.
Definition: pmu.h:909
INLINE void PMU_VDDP_OL_Clr(void)
Clears Overload at VDDP regulator flag.
Definition: pmu.h:929
INLINE void PMU_VDDC_Int_Dis(void)
Disables of VDDC status information as interrupt source.
Definition: pmu.h:874
INLINE void PCU_FAIL_PS_En(void)
Enables LIN Tx and HS Switch off.
Definition: pmu.h:1024
INLINE void PMU_VDDEXT_OT_Int_Clr(void)
Clears VDDEXT Supply OverTemperature interrupt flag.
Definition: pmu.h:899
INLINE void PMU_VDDEXT_Error_Clear(uint16 ErrorFlagMask)
Clears VDDEXT Error Flags.
Definition: pmu.h:1061
INLINE void PMU_VDDC_OV_Clr(void)
Clears Overvoltage at VDDC regulator flag.
Definition: pmu.h:914
INLINE void PCU_SYS_VS_UV_SLM_En(void)
Enables VS Undervoltage Shutdown for peripherals.
Definition: pmu.h:1004
INLINE void PMU_PMU_OT_Clr(void)
Clears Overtemperature Status flag.
Definition: pmu.h:934
INLINE void PCU_CLKWDT_SD_Dis(void)
Disables Power Modules Clock Watchdog Shutdown.
Definition: pmu.h:1039
INLINE void PMU_VDDC_Int_En(void)
Enables of VDDC status information as interrupt source.
Definition: pmu.h:869
INLINE void PMU_VDDP_OV_Clr(void)
Clears Overvoltage at VDDP regulator flag.
Definition: pmu.h:924
INLINE void WAKEUP_Int_Clr(void)
Clears Wakeup Interrupt flag.
Definition: pmu.h:949
INLINE void WAKEUP_Int_En(void)
Enables Wakeup Interrupt.
Definition: pmu.h:939
INLINE void PMU_VDDC_OL_Clr(void)
Clears Overload at VDDC regulator flag.
Definition: pmu.h:919
INLINE void PMU_VDDEXT_Set(uint16 FlagMask)
Sets the given bits in the PMU->VDDEXT_CTRL register.
Definition: pmu.h:1066
INLINE void PMU_OT_Int_Dis(void)
Disables PMU Overtemperature Interrupt.
Definition: pmu.h:894
INLINE void PCU_CLK_Loss_Rst_En(void)
Enables Loss of Clock Reset.
Definition: pmu.h:954
INLINE void PMU_OT_Int_En(void)
Enables PMU Overtemperature Interrupt.
Definition: pmu.h:889
INLINE void WAKEUP_Int_Dis(void)
Disables Wakeup Interrupt.
Definition: pmu.h:944
INLINE void PCU_CLK_Loss_Rst_Dis(void)
Disables Loss of Clock Reset.
Definition: pmu.h:959
SFR low level access library.
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:448
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:423
INLINE void Field_Clr32(volatile uint32 *reg, uint32 msk)
This function clears a bit field in a 32-bit register.
Definition: sfr_access.h:408
INLINE void Field_Wrt32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:358
INLINE void Field_Mod32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:378
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155