120 #define ADC1_CH12 (12)
122 #define ADC1_CH13 (13)
125 #define ADC1_VBAT_SENSE ADC1_CH0
127 #define ADC1_VS ADC1_CH1
129 #define ADC1_MON1 ADC1_CH2
131 #define ADC1_MON2 ADC1_CH3
133 #define ADC1_MON3 ADC1_CH4
135 #define ADC1_MON4 ADC1_CH5
137 #define ADC1_P20 ADC1_CH6
139 #define ADC1_P21 ADC1_CH7
141 #define ADC1_P22 ADC1_CH8
143 #define ADC1_P23 ADC1_CH9
145 #define ADC1_P27 ADC1_CH12
147 #define ADC1_OPA ADC1_CH13
150 #define ADC1_MASK_CH0 (1u << 0u)
152 #define ADC1_MASK_CH1 (1u << 1u)
154 #define ADC1_MASK_CH2 (1u << 2u)
156 #define ADC1_MASK_CH3 (1u << 3u)
158 #define ADC1_MASK_CH4 (1u << 4u)
160 #define ADC1_MASK_CH5 (1u << 5u)
162 #define ADC1_MASK_CH6 (1u << 6u)
164 #define ADC1_MASK_CH7 (1u << 7u)
166 #define ADC1_MASK_CH8 (1u << 8u)
168 #define ADC1_MASK_CH9 (1u << 9u)
170 #define ADC1_MASK_CH12 (1u << 12u)
172 #define ADC1_MASK_CH13 (1u << 13u)
175 #define ADC1_MASK_VBAT_SENSE (ADC1_MASK_CH0)
177 #define ADC1_MASK_VS (ADC1_MASK_CH1)
179 #define ADC1_MASK_MON1 (ADC1_MASK_CH2)
181 #define ADC1_MASK_MON2 (ADC1_MASK_CH3)
183 #define ADC1_MASK_MON3 (ADC1_MASK_CH4)
185 #define ADC1_MASK_MON4 (ADC1_MASK_CH5)
187 #define ADC1_MASK_P20 (ADC1_MASK_CH6)
189 #define ADC1_MASK_P21 (ADC1_MASK_CH7)
191 #define ADC1_MASK_P22 (ADC1_MASK_CH8)
193 #define ADC1_MASK_P23 (ADC1_MASK_CH9)
195 #define ADC1_MASK_P27 (ADC1_MASK_CH12)
197 #define ADC1_MASK_OPA (ADC1_MASK_CH13)
200 #define ADC1_MMODE_0 0u
202 #define ADC1_MMODE_UV 1u
204 #define ADC1_MMODE_OV 2u
207 #define ADC1_HYST_OFF (0u)
209 #define ADC1_HYST_4 (1u)
211 #define ADC1_HYST_8 (2u)
213 #define ADC1_HYST_16 (3u)
216 #define ADC1_CNT_1 (0u)
218 #define ADC1_CNT_2 (1u)
220 #define ADC1_CNT_4 (2u)
222 #define ADC1_CNT_7 (3u)
225 #define ADC1_Soc_Clk_Jitter_0 (0u)
227 #define ADC1_Soc_Clk_Jitter_3_5 (1u)
229 #define ADC1_Soc_Clk_Jitter_5_5 (2u)
231 #define ADC1_Soc_Clk_Jitter_8 (3u)
234 #define ADC1_VREF 1.21
INLINE void ADC1_PP_Ch1_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 1 Measurement Mode.
Definition: adc1.h:6607
INLINE uint16 ADC1_P22_Result_Get(void)
Reads the converted value from the channel 8 result register.
Definition: adc1.h:6312
INLINE void ADC1_Ch9_Int_En(void)
Enables ADC1 IIR-Filter-Channel 9 Interrupt.
Definition: adc1.h:7087
INLINE bool ADC1_isEIMactive(void)
Checks Exceptional Interrupt Mode active.
Definition: adc1.h:7470
INLINE uint16 ADC1_Ch5_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:6227
INLINE void ADC1_Sequence7_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 7, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6167
INLINE void ADC1_DU1_Up_Sts_Clr(void)
Clears ADC1 Differential Unit 1 (DU1) Upper Channel Status.
Definition: adc1.h:6582
INLINE void ADC1_Ch7_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 7 Interrupt flag.
Definition: adc1.h:6952
INLINE void ADC1_PP_Ch0_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 0 Lower Trigger Level.
Definition: adc1.h:6647
TADC1_EIM_REP_CNT
This enum lists the EIM repeat count setting options.
Definition: adc1.h:257
@ ADC1_128_Meas
Definition: adc1.h:265
@ ADC1_1_Meas
Definition: adc1.h:258
@ ADC1_4_Meas
Definition: adc1.h:260
@ ADC1_2_Meas
Definition: adc1.h:259
@ ADC1_32_Meas
Definition: adc1.h:263
@ ADC1_16_Meas
Definition: adc1.h:262
@ ADC1_8_Meas
Definition: adc1.h:261
@ ADC1_64_Meas
Definition: adc1.h:264
INLINE void ADC1_Ch4_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 4 Interrupt flag.
Definition: adc1.h:6937
INLINE void ADC1_Power_On(void)
Enables the ADC1 module.
Definition: adc1.h:6042
INLINE uint16 ADC1_Ch4_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:6222
INLINE void ADC1_PP_Ch4_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 4 Upper Timer Trigger.
Definition: adc1.h:6892
INLINE void ADC1_PP_Ch7_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 7.
Definition: adc1.h:6572
INLINE void ADC1_PP_Ch7_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt.
Definition: adc1.h:7377
INLINE void ADC1_PP_Ch5_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 5 Lower Timer Trigger.
Definition: adc1.h:6852
INLINE uint16 ADC1_P23_Result_Get(void)
Reads the converted value from the channel 9 result register.
Definition: adc1.h:6317
INLINE void ADC1_Ch3_WaitForRead_Set(void)
Sets the result register channel 3 to "wait for read".
Definition: adc1.h:6362
INLINE void ADC1_Ch1_Overwrite_Set(void)
Sets the result register channel 1 to "overwrite".
Definition: adc1.h:6347
INLINE uint8 ADC1_EIM_Active_Sts(void)
Reads the active status of the Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:6097
INLINE void ADC1_PP_Ch6_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 6 Upper Hysteresis.
Definition: adc1.h:6812
INLINE void ADC1_PP_Ch5_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 5 Upper Hysteresis.
Definition: adc1.h:6807
INLINE void ADC1_PP_Ch4_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 4 Upper Trigger Level.
Definition: adc1.h:6712
INLINE uint16 ADC1_MON4_Result_Get(void)
Reads the converted value from the channel 5 result register.
Definition: adc1.h:6297
INLINE void ADC1_EIM_Int_Dis(void)
Disables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:7122
INLINE void ADC1_Ch2_WaitForRead_Set(void)
Sets the result register channel 2 to "wait for read".
Definition: adc1.h:6352
INLINE void ADC1_PP_Ch2_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt flag.
Definition: adc1.h:7182
INLINE uint8 ADC1_Sequence_Feedback_Sts(void)
Reads the Current Sequence that caused software mode.
Definition: adc1.h:6122
INLINE void ADC1_Ch5_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 5 Interrupt flag.
Definition: adc1.h:6942
INLINE void ADC1_DU1UP_Int_Dis(void)
Disables Differential Unit 1 upper Interrupt.
Definition: adc1.h:7142
INLINE void ADC1_SOOC_Set(void)
Starts an ADC1 Offset Calibration, for Software mode only.
Definition: adc1.h:6052
INLINE uint16 ADC1_Ch8_Result_Get(void)
Reads the converted value from the channel 8 result register.
Definition: adc1.h:6242
INLINE void ADC1_PP_Ch5_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 5.
Definition: adc1.h:6562
INLINE void ADC1_DU1_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Differential Unit 1 Lower Timer Trigger.
Definition: adc1.h:6867
INLINE void ADC1_PP_Ch0_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt.
Definition: adc1.h:7237
INLINE void ADC1_PP_Ch1_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 1 Upper Timer Trigger.
Definition: adc1.h:6877
INLINE void ADC1_PP_Ch7_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt flag.
Definition: adc1.h:7232
INLINE void ADC1_DU1_Dis(void)
Disables ADC1 Differential Unit 1.
Definition: adc1.h:6592
INLINE void ADC1_PP_Ch1_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt.
Definition: adc1.h:7257
INLINE void ADC1_ESM_Int_En(void)
Enables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:7127
INLINE void ADC1_DU1_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Differential Unit 1 Lower Hysteresis.
Definition: adc1.h:6777
INLINE void ADC1_PP_Ch3_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 3 Lower Hysteresis.
Definition: adc1.h:6752
INLINE void ADC1_Ch4_Int_En(void)
Enables ADC1 IIR-Filter-Channel 4 Interrupt.
Definition: adc1.h:7037
INLINE uint8 ADC1_EIM_Channel_Read(void)
Reads EIM channel for measurement.
Definition: adc1.h:6492
INLINE void ADC1_PP_Ch4_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 4.
Definition: adc1.h:6517
INLINE void ADC1_PP_Ch5_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt flag.
Definition: adc1.h:7212
INLINE void ADC1_Ch3_Int_En(void)
Enables ADC1 IIR-Filter-Channel 3 Interrupt.
Definition: adc1.h:7027
INLINE void ADC1_Ch6_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 6 Interrupt flag.
Definition: adc1.h:6947
INLINE void ADC1_PP_Ch1_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 1 Lower Hysteresis.
Definition: adc1.h:6742
INLINE void ADC1_PP_Ch6_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt.
Definition: adc1.h:7367
INLINE void ADC1_PP_Ch1_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 1 Upper Hysteresis.
Definition: adc1.h:6787
INLINE void ADC1_Sequence0_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 0, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6132
INLINE void ADC1_PP_Ch5_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt.
Definition: adc1.h:7342
INLINE uint16 ADC1_MON2_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:6287
INLINE void ADC1_PP_Ch6_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt.
Definition: adc1.h:7357
INLINE void ADC1_DU1_En(void)
Enables ADC1 Differential Unit 1.
Definition: adc1.h:6587
INLINE void ADC1_Ch5_WaitForRead_Set(void)
Sets the result register channel 5 to "wait for read".
Definition: adc1.h:6382
INLINE void ADC1_Offset_Shift_Set(uint8 value)
Sets the Value of the Offset Shift.
Definition: adc1.h:7402
INLINE void ADC1_DU1_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Differential Unit 1 Measurement Mode.
Definition: adc1.h:6642
INLINE void ADC1_Ch4_WaitForRead_Set(void)
Sets the result register channel 4 to "wait for read".
Definition: adc1.h:6372
INLINE void ADC1_DU1_WaitForRead_Set(void)
Sets the result register DU1 to "wait for read".
Definition: adc1.h:6452
uint8 ADC1_GetChResValid(uint8 channel)
Gets the 10-bit value of the ADC1 Result Register of the selected ADC1 channel and returns the validi...
#define SEQ_Mode
Mode Selection macro, Sequencer Mode.
Definition: adc1.h:92
INLINE void ADC1_Ch1_WaitForRead_Set(void)
Sets the result register channel 1 to "wait for read".
Definition: adc1.h:6342
INLINE uint8 ADC1_ESM_Active_Sts(void)
Reads the active status of the Exceptional Sequencer Measurement (ESM).
Definition: adc1.h:6102
INLINE void ADC1_Sequencer_Mode_Sel(void)
Selects ADC1 Sequencer Mode.
Definition: adc1.h:6082
INLINE void ADC1_Ch8_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 8 Interrupt flag.
Definition: adc1.h:6957
INLINE void ADC1_Sequence9_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 9, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6177
INLINE void ADC1_SetEIMChannel(uint8 channel)
Sets ADC1 EIM channel.
Definition: adc1.h:7417
INLINE void ADC1_PP_Ch3_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 3.
Definition: adc1.h:6512
INLINE void ADC1_ESM_En(void)
Enables Exceptional Sequence measurement (ESM) Trigger Event.
Definition: adc1.h:6472
INLINE void ADC1_DU1UP_Int_Clr(void)
Clears Differential Unit 1 upper Interrupt flag.
Definition: adc1.h:6987
INLINE void ADC1_PP_Ch0_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt.
Definition: adc1.h:7242
INLINE void ADC1_SetSwMode_Channel(uint8 channel)
Selects a channel for the software conversion.
Definition: adc1.h:7422
INLINE void ADC1_PP_Ch5_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 5 Lower Trigger Level.
Definition: adc1.h:6672
INLINE void ADC1_Ch7_Int_En(void)
Enables ADC1 IIR-Filter-Channel 7 Interrupt.
Definition: adc1.h:7067
INLINE void ADC1_Ch9_WaitForRead_Set(void)
Sets the result register channel 9 to "wait for read".
Definition: adc1.h:6422
INLINE void ADC1_PP_Ch4_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt flag.
Definition: adc1.h:7202
void ADC1_Init(void)
Initializes the ADC1 based on the Config Wizard configuration.
INLINE void ADC1_PP_Ch7_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 7 Upper Trigger Level.
Definition: adc1.h:6727
INLINE void ADC1_Ch7_WaitForRead_Set(void)
Sets the result register channel 7 to "wait for read".
Definition: adc1.h:6402
INLINE uint16 ADC1_Ch7_Result_Get(void)
Reads the converted value from the channel 7 result register.
Definition: adc1.h:6237
INLINE void ADC1_Ch12_WaitForRead_Set(void)
Sets the result register channel 12 to "wait for read".
Definition: adc1.h:6432
INLINE void ADC1_DU1_Lo_Sts_Clr(void)
Clears ADC1 Differential Unit 1 (DU1) Lower Channel Status.
Definition: adc1.h:6577
INLINE void ADC1_PP_Ch5_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt.
Definition: adc1.h:7337
INLINE void ADC1_PP_Ch4_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt.
Definition: adc1.h:7317
INLINE void ADC1_Ch2_Int_En(void)
Enables ADC1 IIR-Filter-Channel 2 Interrupt.
Definition: adc1.h:7017
INLINE void ADC1_Ch2_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 2 Interrupt.
Definition: adc1.h:7022
INLINE void ADC1_PP_Ch3_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 3 Measurement Mode.
Definition: adc1.h:6617
INLINE void ADC1_Ch0_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 0 Interrupt.
Definition: adc1.h:7002
INLINE void ADC1_Power_Off(void)
Disables the ADC1 module.
Definition: adc1.h:6047
INLINE void ADC1_PP_Ch2_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 2 Lower Timer Trigger.
Definition: adc1.h:6837
INLINE void ADC1_PP_Ch3_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt flag.
Definition: adc1.h:7187
INLINE void ADC1_Ch3_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 3 Interrupt.
Definition: adc1.h:7032
INLINE void ADC1_PP_Ch0_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 0 Lower Hysteresis.
Definition: adc1.h:6737
INLINE void ADC1_Ch9_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 9 Interrupt flag.
Definition: adc1.h:6962
INLINE void ADC1_Sequence6_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 6, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6162
INLINE void ADC1_PP_Ch3_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 3 Upper Trigger Level.
Definition: adc1.h:6707
INLINE void ADC1_PP_Ch4_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 4 Lower Hysteresis.
Definition: adc1.h:6757
INLINE void ADC1_Ch5_Overwrite_Set(void)
Sets the result register channel 5 to "overwrite".
Definition: adc1.h:6387
INLINE uint16 ADC1_Ch13_Result_Get(void)
Reads the converted value from the channel 13 (CSA) result register.
Definition: adc1.h:6257
INLINE void ADC1_Sequence2_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 2, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6142
INLINE uint16 ADC1_MON1_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:6282
INLINE void ADC1_PP_Ch4_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 4.
Definition: adc1.h:6557
INLINE void ADC1_PP_Ch2_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt.
Definition: adc1.h:7287
INLINE void ADC1_DU1_Up_Th_Set(uint8 trig_val)
Sets ADC1 Differential Unit 1 Upper Trigger Level.
Definition: adc1.h:6732
INLINE uint8 ADC1_Sequencer_Stop_Signal_Sts(void)
Reads the ADC1 Sequencer Stop Signal for DPP Status.
Definition: adc1.h:6117
INLINE void ADC1_PP_Ch0_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt flag.
Definition: adc1.h:7157
INLINE void ADC1_PP_Ch1_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 1 Upper Trigger Level.
Definition: adc1.h:6697
INLINE void ADC1_DU1UP_Int_En(void)
Enables Differential Unit 1 upper Interrupt.
Definition: adc1.h:7137
INLINE void ADC1_ESM_Int_Clr(void)
Clears Exceptional Sequence Measurement (ESM) flag.
Definition: adc1.h:6982
INLINE void ADC1_PP_Ch7_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt.
Definition: adc1.h:7382
INLINE void ADC1_ESM_Dis(void)
Disables Exceptional Sequence measurement (ESM) Trigger Event.
Definition: adc1.h:6477
INLINE void ADC1_Ch6_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 6 Interrupt.
Definition: adc1.h:7062
INLINE void ADC1_PP_Ch0_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 0.
Definition: adc1.h:6497
INLINE void ADC1_DU1_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Differential Unit 1 Lower Trigger Level.
Definition: adc1.h:6687
INLINE void ADC1_PP_Ch0_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt.
Definition: adc1.h:7247
INLINE void ADC1_PP_Ch4_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt flag.
Definition: adc1.h:7197
INLINE void ADC1_Ch9_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 9 Interrupt.
Definition: adc1.h:7092
INLINE void ADC1_PP_Ch6_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 6.
Definition: adc1.h:6567
INLINE void ADC1_DU1_Overwrite_Set(void)
Sets the result register DU1 to "overwrite".
Definition: adc1.h:6457
INLINE void ADC1_PP_Ch7_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt flag.
Definition: adc1.h:7227
INLINE void ADC1_ESM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Sets ADC1 ESM Trigger Selection.
Definition: adc1.h:7454
INLINE void ADC1_Ch8_WaitForRead_Set(void)
Sets the result register channel 8 to "wait for read".
Definition: adc1.h:6412
INLINE void ADC1_SW_Channel_Sel(uint8 a)
Selects a channel for the software conversion.
Definition: adc1.h:6062
INLINE void ADC1_Ch13_WaitForRead_Set(void)
Sets the result register channel 13 to "wait for read".
Definition: adc1.h:6442
INLINE void ADC1_PP_Ch6_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt flag.
Definition: adc1.h:7222
INLINE void ADC1_PP_Ch2_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 2 Upper Hysteresis.
Definition: adc1.h:6792
INLINE void ADC1_EIM_Int_Clr(void)
Clears Exceptional Interrupt Measurement (EIM) flag.
Definition: adc1.h:6977
INLINE void ADC1_PP_Ch3_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 3.
Definition: adc1.h:6552
INLINE uint16 ADC1_Ch0_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:6202
INLINE void ADC1_STRTUP_Dis(void)
Disables DPP1 Startup.
Definition: adc1.h:6077
INLINE void ADC1_Sequence12_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 12, only valid in Sequencer Mode, see ADC1_Sequencer_...
Definition: adc1.h:6192
INLINE void ADC1_PP_Ch6_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt.
Definition: adc1.h:7362
INLINE void ADC1_Ch0_Int_En(void)
Enables ADC1 IIR-Filter-Channel 0 Interrupt.
Definition: adc1.h:6997
INLINE void ADC1_PP_Ch5_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 5 Upper Timer Trigger.
Definition: adc1.h:6897
INLINE void ADC1_PP_Ch0_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 0 Upper Timer Trigger.
Definition: adc1.h:6872
INLINE void ADC1_PP_Ch0_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt flag.
Definition: adc1.h:7162
INLINE void ADC1_Ch13_Overwrite_Set(void)
Sets the result register channel 13 to "overwrite".
Definition: adc1.h:6447
INLINE void ADC1_PP_Ch3_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt flag.
Definition: adc1.h:7192
INLINE void ADC1_PP_Ch3_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt.
Definition: adc1.h:7302
INLINE void ADC1_Ch6_Int_En(void)
Enables ADC1 IIR-Filter-Channel 6 Interrupt.
Definition: adc1.h:7057
INLINE void ADC1_PP_Ch2_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt.
Definition: adc1.h:7277
INLINE void ADC1_Sequence5_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 5, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6157
INLINE void ADC1_Ch4_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 4 Interrupt.
Definition: adc1.h:7042
INLINE void ADC1_PP_Ch5_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 5 Upper Trigger Level.
Definition: adc1.h:6717
INLINE void ADC1_PP_Ch6_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 6 Lower Trigger Level.
Definition: adc1.h:6677
INLINE void ADC1_DU1LO_Int_Dis(void)
Disables Differential Unit 1 lower Interrupt.
Definition: adc1.h:7152
INLINE void ADC1_PP_Ch2_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 2 Upper Timer Trigger.
Definition: adc1.h:6882
INLINE void ADC1_Ch12_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 12 Interrupt.
Definition: adc1.h:7102
INLINE void ADC1_PP_Ch2_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 2 Measurement Mode.
Definition: adc1.h:6612
INLINE void ADC1_PP_Ch2_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt.
Definition: adc1.h:7292
INLINE void ADC1_Sequence13_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 13, only valid in Sequencer Mode, see ADC1_Sequencer_...
Definition: adc1.h:6197
INLINE void ADC1_DU1LO_Int_En(void)
Enables Differential Unit 1 lower Interrupt.
Definition: adc1.h:7147
INLINE void ADC1_PP_Ch7_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt.
Definition: adc1.h:7387
INLINE uint8 ADC1_Current_Active_Channel_Sts(void)
Reads the currently active channel status.
Definition: adc1.h:6112
INLINE void ADC1_Soc_Clk_Jitter_Set(uint8 clk)
Sets Soc Clock Jitter.
Definition: adc1.h:7412
INLINE void ADC1_PP_Ch4_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 4 Lower Trigger Level.
Definition: adc1.h:6667
INLINE void ADC1_PP_Ch0_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 0 Upper Hysteresis.
Definition: adc1.h:6782
INLINE void ADC1_PP_Ch5_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 5.
Definition: adc1.h:6522
INLINE uint16 ADC1_P20_Result_Get(void)
Reads the converted value from the channel 6 result register.
Definition: adc1.h:6302
INLINE bool ADC1_isEndOfConversion(void)
Checks EndOfConversion ready (Software Mode)
Definition: adc1.h:7459
INLINE uint16 ADC1_Ch2_Result_Get(void)
Reads the converted value from the channel 2 result register.
Definition: adc1.h:6212
INLINE void ADC1_PP_Ch7_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 7 Measurement Mode.
Definition: adc1.h:6637
INLINE void ADC1_Ch12_Int_En(void)
Enables ADC1 IIR-Filter-Channel 12 Interrupt.
Definition: adc1.h:7097
INLINE void ADC1_SOS_Set(void)
Starts an ADC1 Conversion, for Software mode only.
Definition: adc1.h:6057
INLINE uint8 ADC1_SW_Channel_Read(void)
Reads the enabled channels for the software conversion.
Definition: adc1.h:6067
INLINE void ADC1_PP_Ch1_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt.
Definition: adc1.h:7262
INLINE void ADC1_Ch3_Overwrite_Set(void)
Sets the result register channel 3 to "overwrite".
Definition: adc1.h:6367
INLINE void ADC1_Ch0_Overwrite_Set(void)
Sets the result register channel 0 to "overwrite".
Definition: adc1.h:6337
INLINE void ADC1_SW_Max_Time_Set(uint8 time)
Sets Maximum Time in Software Mode.
Definition: adc1.h:6127
INLINE uint16 ADC1_Ch12_Result_Get(void)
Reads the converted value from the channel 12 (P2.7) result register.
Definition: adc1.h:6252
INLINE void ADC1_Sequence8_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 8, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6172
INLINE uint16 ADC1_MON3_Result_Get(void)
Reads the converted value from the channel 4 result register.
Definition: adc1.h:6292
INLINE void ADC1_Ch0_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 0 Interrupt flag.
Definition: adc1.h:6917
INLINE void ADC1_EIM_Dis(void)
Disables Exceptional interrupt measurement (EIM) Trigger Event.
Definition: adc1.h:6467
#define SW_Mode
ADC1 Mode Selection macro, Software Mode.
Definition: adc1.h:90
INLINE void ADC1_PP_Ch2_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 2 Lower Hysteresis.
Definition: adc1.h:6747
INLINE void ADC1_Ch12_Overwrite_Set(void)
Sets the result register channel 12 to "overwrite".
Definition: adc1.h:6437
INLINE void ADC1_Ch7_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 7 Interrupt.
Definition: adc1.h:7072
INLINE void ADC1_PP_Ch0_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 0 Upper Trigger Level.
Definition: adc1.h:6692
bool ADC1_GetChResult(uint16 *pVar, uint8 channel)
Gets the 10-bit value of the ADC1 Result Register of the selected ADC1 channel and returns the validi...
INLINE void ADC1_PP_Ch5_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 5 Lower Hysteresis.
Definition: adc1.h:6762
INLINE void ADC1_PP_Ch6_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 6 Measurement Mode.
Definition: adc1.h:6632
INLINE void ADC1_PP_Ch1_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 1 Lower Trigger Level.
Definition: adc1.h:6652
INLINE void ADC1_PP_Ch5_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt flag.
Definition: adc1.h:7207
INLINE void ADC1_Sequence1_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 1, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6137
INLINE void ADC1_Software_Mode_Sel(void)
Selects ADC1 Software Mode, measurements are performed on user request.
Definition: adc1.h:6087
#define OVERWRITE
ADC1 Result Register macro, Overwrite Mode.
Definition: adc1.h:95
INLINE void ADC1_SetSosSwMode(uint8 channel)
Starts ADC1 Software Mode conversion.
Definition: adc1.h:7427
INLINE void ADC1_Ch8_Int_En(void)
Enables ADC1 IIR-Filter-Channel 8 Interrupt.
Definition: adc1.h:7077
INLINE void ADC1_Ch3_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 3 Interrupt flag.
Definition: adc1.h:6932
INLINE void ADC1_Sig_Del_feed_Loop_En(void)
Enables Sigma Delta Feedback Loop.
Definition: adc1.h:7407
INLINE void ADC1_PP_Ch1_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt.
Definition: adc1.h:7267
INLINE void ADC1_PP_Ch3_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 3 Lower Timer Trigger.
Definition: adc1.h:6842
INLINE void ADC1_PP_Ch4_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 4 Upper Hysteresis.
Definition: adc1.h:6802
INLINE bool ADC1_GetEocSwMode(void)
Gets ADC1 Software Mode End Of Conversion Status.
Definition: adc1.h:7433
INLINE void ADC1_Ch1_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 1 Interrupt flag.
Definition: adc1.h:6922
INLINE void ADC1_PP_Ch6_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 6 Upper Timer Trigger.
Definition: adc1.h:6902
INLINE uint8 ADC1_EOC_Sts(void)
Reads the End-of-Conversion status.
Definition: adc1.h:6092
INLINE void ADC1_PP_Ch7_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 7 Lower Timer Trigger.
Definition: adc1.h:6862
INLINE uint8 ADC1_Current_Active_Sequence_Sts(void)
Reads the currently active channel status in Sequencer Mode.
Definition: adc1.h:6107
INLINE void ADC1_PP_Ch6_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 6 Upper Trigger Level.
Definition: adc1.h:6722
INLINE uint16 ADC1_EIM_Result_Get(void)
Reads the converted value from the EIM result register.
Definition: adc1.h:6262
INLINE void ADC1_PP_Ch1_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 1 Lower Timer Trigger.
Definition: adc1.h:6832
INLINE void ADC1_DU1_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Differential Unit 1 Upper Timer Trigger.
Definition: adc1.h:6912
INLINE void ADC1_PP_Ch2_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt.
Definition: adc1.h:7282
INLINE void ADC1_PP_Ch0_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 0.
Definition: adc1.h:6537
INLINE void ADC1_STRTUP_En(void)
Enables DPP1 Startup.
Definition: adc1.h:6072
INLINE void ADC1_PP_Ch0_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 0 Measurement Mode.
Definition: adc1.h:6602
bool ADC1_GetEIMResult(uint16 *pVar)
Gets the 10-bit value of the ADC1 EIM Result Register and returns the validity info.
INLINE void ADC1_Sequence11_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 11, only valid in Sequencer Mode, see ADC1_Sequencer_...
Definition: adc1.h:6187
INLINE void ADC1_PP_Ch0_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 0 Lower Timer Trigger.
Definition: adc1.h:6827
INLINE void ADC1_PP_Ch4_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt.
Definition: adc1.h:7327
INLINE void ADC1_PP_Ch2_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 2.
Definition: adc1.h:6507
#define WFR
ADC1 Result Register macro, Wait For Read Mode.
Definition: adc1.h:97
INLINE void ADC1_PP_Ch6_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 6 Lower Hysteresis.
Definition: adc1.h:6767
INLINE bool ADC1_isESMactive(void)
Checks Exceptional Sequencer Mode active.
Definition: adc1.h:7481
INLINE void ADC1_PP_Ch6_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 6 Lower Timer Trigger.
Definition: adc1.h:6857
TADC1_TRIGG_SEL
This enum lists the trigger select options for EIM and ESM.
Definition: adc1.h:243
@ ADC1_Trigg_GPT12E_T3
Definition: adc1.h:247
@ ADC1_Trigg_CCU6_Ch3
Definition: adc1.h:245
@ ADC1_Trigg_Timer21
Definition: adc1.h:249
@ ADC1_Trigg_Timer2
Definition: adc1.h:248
@ ADC1_Trigg_GPT12E_T6
Definition: adc1.h:246
@ ADC1_Trigg_None
Definition: adc1.h:244
uint32 ADC1_GetChAttFactor(uint8 channel)
Gets ADC1 Channel Attenuator Factor multiplied by 1024.
INLINE void ADC1_Ch5_Int_En(void)
Enables ADC1 IIR-Filter-Channel 5 Interrupt.
Definition: adc1.h:7047
INLINE void ADC1_Sequence10_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 10, only valid in Sequencer Mode, see ADC1_Sequencer_...
Definition: adc1.h:6182
INLINE void ADC1_Ch2_Overwrite_Set(void)
Sets the result register channel 2 to "overwrite".
Definition: adc1.h:6357
INLINE void ADC1_Ch13_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 13 Interrupt flag.
Definition: adc1.h:6972
INLINE uint16 ADC1_Ch6_Result_Get(void)
Reads the converted value from the channel 6 result register.
Definition: adc1.h:6232
INLINE uint16 ADC1_P21_Result_Get(void)
Reads the converted value from the channel 7 result register.
Definition: adc1.h:6307
INLINE void ADC1_Ch4_Overwrite_Set(void)
Sets the result register channel 4 to "overwrite".
Definition: adc1.h:6377
INLINE void ADC1_Ch2_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 2 Interrupt flag.
Definition: adc1.h:6927
INLINE void ADC1_Ch8_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 8 Interrupt.
Definition: adc1.h:7082
INLINE void ADC1_Ch7_Overwrite_Set(void)
Sets the result register channel 7 to "overwrite".
Definition: adc1.h:6407
INLINE void ADC1_Ch13_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 13 Interrupt.
Definition: adc1.h:7112
INLINE void ADC1_Ch5_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 5 Interrupt.
Definition: adc1.h:7052
INLINE void ADC1_PP_Ch3_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 3 Upper Hysteresis.
Definition: adc1.h:6797
INLINE void ADC1_ESM_Channel_Set(uint16 mask_ch)
Sets channels in ESM sequence.
Definition: adc1.h:6487
INLINE uint16 ADC1_DU1_Result_Get(void)
Reads ADC differential 1 output value.
Definition: adc1.h:6267
INLINE void ADC1_PP_Ch5_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt.
Definition: adc1.h:7347
INLINE void ADC1_Ch1_Int_Dis(void)
Disables ADC1 IIR-Filter-Channel 1 Interrupt.
Definition: adc1.h:7012
INLINE void ADC1_Ch6_Overwrite_Set(void)
Sets the result register channel 6 to "overwrite".
Definition: adc1.h:6397
INLINE void ADC1_PP_Ch2_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 2 Lower Trigger Level.
Definition: adc1.h:6657
INLINE void ADC1_DU1LO_Int_Clr(void)
Clears Differential Unit 1 lower Interrupt flag.
Definition: adc1.h:6992
INLINE uint16 ADC1_Ch1_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:6207
INLINE void ADC1_Ch8_Overwrite_Set(void)
Sets the result register channel 8 to "overwrite".
Definition: adc1.h:6417
INLINE void ADC1_PP_Ch7_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 7 Lower Trigger Level.
Definition: adc1.h:6682
INLINE void ADC1_PP_Ch5_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 5 Measurement Mode.
Definition: adc1.h:6627
INLINE void ADC1_PP_Ch7_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 7 Upper Hysteresis.
Definition: adc1.h:6817
INLINE uint16 ADC1_Ch3_Result_Get(void)
Reads the converted value from the channel 3 result register.
Definition: adc1.h:6217
INLINE uint16 ADC1_OPA_Result_Get(void)
Reads the converted value from the channel 13 result register.
Definition: adc1.h:6327
INLINE void ADC1_Sequence4_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 4, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6152
INLINE void ADC1_Sequence3_Set(uint16 mask_ch)
Defines the channels to be measured in Sequence 3, only valid in Sequencer Mode, see ADC1_Sequencer_M...
Definition: adc1.h:6147
INLINE void ADC1_PP_Ch1_LO_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt flag.
Definition: adc1.h:7172
INLINE uint16 ADC1_VBAT_SENSE_Result_Get(void)
Reads the converted value from the channel 0 result register.
Definition: adc1.h:6272
INLINE uint16 ADC1_P27_Result_Get(void)
Reads the converted value from the channel 12 result register.
Definition: adc1.h:6322
INLINE void ADC1_EIM_Channel_Set(uint8 ch)
Sets EIM channel for measurement.
Definition: adc1.h:6482
INLINE void ADC1_PP_Ch1_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt flag.
Definition: adc1.h:7167
INLINE void ADC1_PP_Ch4_Lo_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 4 Lower Timer Trigger.
Definition: adc1.h:6847
INLINE void ADC1_EIM_Repeat_Counter_Set(TADC1_EIM_REP_CNT repcnt)
Sets ADC1 EIM Repeat Counter.
Definition: adc1.h:7449
INLINE void ADC1_EIM_Trigger_Select(TADC1_TRIGG_SEL trigsel)
Selects ADC1 EIM Trigger.
Definition: adc1.h:7444
INLINE void ADC1_PP_Ch7_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 7 Upper Timer Trigger.
Definition: adc1.h:6907
INLINE void ADC1_PP_Ch0_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt.
Definition: adc1.h:7252
INLINE void ADC1_EIM_Int_En(void)
Enables Exceptional Interrupt Measurement (EIM).
Definition: adc1.h:7117
INLINE void ADC1_PP_Ch6_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt.
Definition: adc1.h:7372
INLINE void ADC1_PP_Ch3_Up_Cnt_Set(uint8 cnt)
Sets ADC1 Post-Processing Channel 3 Upper Timer Trigger.
Definition: adc1.h:6887
INLINE void ADC1_Offset_Calib_Set(uint8 value)
Sets the Value of the Offset Calibration.
Definition: adc1.h:7397
INLINE void ADC1_Ch13_Int_En(void)
Enables ADC1 IIR-Filter-Channel 13 Interrupt.
Definition: adc1.h:7107
INLINE void ADC1_PP_Ch1_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 1.
Definition: adc1.h:6542
INLINE void ADC1_PP_Ch1_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt.
Definition: adc1.h:7272
INLINE void ADC1_PP_Ch7_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 7.
Definition: adc1.h:6532
INLINE void ADC1_Ch12_Int_Clr(void)
Clears ADC1 IIR-Filter-Channel 12 Interrupt flag.
Definition: adc1.h:6967
INLINE void ADC1_PP_Ch5_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt.
Definition: adc1.h:7352
INLINE void ADC1_ESM_Int_Dis(void)
Disables Exceptional Sequence Measurement (ESM).
Definition: adc1.h:7132
INLINE void ADC1_PP_Ch1_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 1.
Definition: adc1.h:6502
INLINE void ADC1_PP_Ch6_Filt_UpLo_En(void)
Enables Upper and Lower Threshold IIR Filter Post-Processing Channel 6.
Definition: adc1.h:6527
bool ADC1_GetChResult_mV(uint16 *pVar_mV, uint8 channel)
Gets the 10-bit value of the ADC1 Result Register of the selected ADC1 channel in Millivolt (mV) and ...
INLINE void ADC1_PP_Ch3_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt.
Definition: adc1.h:7312
INLINE uint8 ADC1_DU1_Result_Neg_Sts(void)
Reads the Differential Unit 1 Negative Result Status.
Definition: adc1.h:6597
INLINE void ADC1_DU1_Up_Hyst_Set(uint8 hyst)
Sets ADC1 Differential Unit 1 Upper Hysteresis.
Definition: adc1.h:6822
INLINE void ADC1_PP_Ch3_Lo_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 3 Lower Trigger Level.
Definition: adc1.h:6662
INLINE void ADC1_PP_Ch7_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt.
Definition: adc1.h:7392
INLINE void ADC1_PP_Ch3_LO_Int_En(void)
Enables ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt.
Definition: adc1.h:7307
INLINE uint16 ADC1_VS_Result_Get(void)
Reads the converted value from the channel 1 result register.
Definition: adc1.h:6277
INLINE void ADC1_Ch0_WaitForRead_Set(void)
Sets the result register channel 0 to "wait for read".
Definition: adc1.h:6332
INLINE void ADC1_Ch6_WaitForRead_Set(void)
Sets the result register channel 6 to "wait for read".
Definition: adc1.h:6392
INLINE void ADC1_PP_Ch4_UP_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt.
Definition: adc1.h:7322
INLINE void ADC1_PP_Ch6_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt flag.
Definition: adc1.h:7217
INLINE void ADC1_PP_Ch4_Mode_Meas_Sel(uint8 mmode)
Selects ADC1 Post-Processing Channel 4 Measurement Mode.
Definition: adc1.h:6622
INLINE void ADC1_Ch9_Overwrite_Set(void)
Sets the result register channel 9 to "overwrite".
Definition: adc1.h:6427
INLINE void ADC1_PP_Ch3_UP_Int_En(void)
Enables ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt.
Definition: adc1.h:7297
INLINE void ADC1_PP_Ch2_Filt_UpLo_Dis(void)
Disables Upper and Lower Threshold IIR Filter Post-Processing Channel 2.
Definition: adc1.h:6547
INLINE uint16 ADC1_Ch9_Result_Get(void)
Reads the converted value from the channel 9 result register.
Definition: adc1.h:6247
bool ADC1_GetEIMResult_mV(uint16 *pVar_mV)
Gets the value of the ADC1 EIM Result Register in Millivolt (mV) and returns the validity info.
INLINE void ADC1_Ch1_Int_En(void)
Enables ADC1 IIR-Filter-Channel 1 Interrupt flag.
Definition: adc1.h:7007
INLINE void ADC1_PP_Ch2_Up_Th_Set(uint8 trig_val)
Sets ADC1 Post-Processing Channel 2 Upper Trigger Level.
Definition: adc1.h:6702
INLINE void ADC1_PP_Ch2_UP_Int_Clr(void)
Clears ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt flag.
Definition: adc1.h:7177
INLINE void ADC1_PP_Ch4_LO_Int_Dis(void)
Disables ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt.
Definition: adc1.h:7332
INLINE void ADC1_PP_Ch7_Lo_Hyst_Set(uint8 hyst)
Sets ADC1 Post-Processing Channel 7 Lower Hysteresis.
Definition: adc1.h:6772
INLINE void ADC1_EIM_En(void)
Enables Exceptional interrupt measurement (EIM) Trigger Event.
Definition: adc1.h:6462
#define ADC1
Definition: tle985x.h:6265
#define ADC1_IRQCLR_1_IIR_CH5_ISC_Msk
Definition: tle985x.h:6750
#define ADC1_SQ_FB_SQx_Msk
Definition: tle985x.h:7053
#define ADC1_MMODE0_7_MMODE_0_Msk
Definition: tle985x.h:6955
#define ADC1_FILT_OUT13_WFR13_Msk
Definition: tle985x.h:6594
#define ADC1_CNT0_3_UPPER_HYST_UP_PP2_Pos
Definition: tle985x.h:6429
#define ADC1_FILT_OUT6_FILT_OUT_CH6_Msk
Definition: tle985x.h:6641
#define ADC1_IRQEN_1_IIR_CH9_IEN_Pos
Definition: tle985x.h:6811
#define ADC1_FILT_OUT0_WFR0_Pos
Definition: tle985x.h:6548
#define ADC1_IRQEN_2_PP_CH7_LO_IEN_Msk
Definition: tle985x.h:6849
#define ADC1_SQ6_7_SQ7_Msk
Definition: tle985x.h:7034
#define ADC1_IRQCLR_2_VS_LO_ISC_Msk
Definition: tle985x.h:6791
#define ADC1_IRQCLR_1_IIR_CH6_ISC_Pos
Definition: tle985x.h:6747
#define ADC1_CNT0_3_UPPER_CNT_UP_PP0_Pos
Definition: tle985x.h:6439
#define ADC1_SQ_FB_ESM_ACTIVE_Pos
Definition: tle985x.h:7054
#define ADC1_IRQEN_2_VS_LO_IEN_Pos
Definition: tle985x.h:6860
#define ADC1_FILT_OUT13_FILT_OUT_CH13_Pos
Definition: tle985x.h:6595
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH5_EN_Pos
Definition: tle985x.h:6683
#define ADC1_SQ10_11_SQ10_Msk
Definition: tle985x.h:7016
#define ADC1_FILT_OUT0_FILT_OUT_CH0_Pos
Definition: tle985x.h:6550
#define ADC1_IRQCLR_2_PP_CH7_LO_ISC_Pos
Definition: tle985x.h:6778
#define ADC1_CTRL_STS_EOC_Msk
Definition: tle985x.h:6502
#define ADC1_SQ_FB_SQ_FB_Pos
Definition: tle985x.h:7060
#define ADC1_IRQCLR_1_ESM_ISC_Pos
Definition: tle985x.h:6729
#define ADC1_MMODE0_7_MMODE_4_Pos
Definition: tle985x.h:6946
#define ADC1_CNT0_3_UPPER_HYST_UP_PP3_Msk
Definition: tle985x.h:6426
#define ADC1_FILT_OUT1_FILT_OUT_CH1_Msk
Definition: tle985x.h:6560
#define ADC1_IRQEN_2_PP_CH5_UP_IEN_Msk
Definition: tle985x.h:6837
#define ADC1_SQ2_3_SQ2_Pos
Definition: tle985x.h:7025
#define ADC1_IRQCLR_2_PP_CH6_UP_ISC_Msk
Definition: tle985x.h:6765
#define ADC1_DCHCNT1_4_LOWER_CNT_LO_DCH1_Pos
Definition: tle985x.h:6516
#define ADC1_FILT_OUT4_WFR4_Msk
Definition: tle985x.h:6621
#define ADC1_SQ_FB_SQ_FB_Msk
Definition: tle985x.h:7061
#define ADC1_CNT0_3_LOWER_CNT_LO_PP1_Msk
Definition: tle985x.h:6419
#define ADC1_TH4_7_UPPER_PP_CH5_UP_Msk
Definition: tle985x.h:7145
#define ADC1_DCHCNT1_4_UPPER_CNT_UP_DCH1_Msk
Definition: tle985x.h:6522
#define ADC1_CTRL_STS_STRTUP_DIS_Msk
Definition: tle985x.h:6498
#define ADC1_STSCLR_1_DU1UP_SC_Msk
Definition: tle985x.h:7109
#define ADC1_TH4_7_UPPER_PP_CH5_UP_Pos
Definition: tle985x.h:7144
#define ADC1_SQ10_11_SQ11_Pos
Definition: tle985x.h:7013
#define ADC1_DCHCNT1_4_UPPER_HYST_UP_DCH1_Msk
Definition: tle985x.h:6520
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH3_EN_Pos
Definition: tle985x.h:6687
#define ADC1_IRQEN_1_EIM_IEN_Msk
Definition: tle985x.h:6802
#define ADC1_FILT_OUT9_WFR9_Msk
Definition: tle985x.h:6666
#define ADC1_OFFSETCALIB_OFFSET_DAC_Pos
Definition: tle985x.h:6957
#define ADC1_CNT4_7_UPPER_CNT_UP_PP6_Msk
Definition: tle985x.h:6466
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH2_EN_Pos
Definition: tle985x.h:6689
#define ADC1_CTRL_STS_SOOC_Pos
Definition: tle985x.h:6509
#define ADC1_SQ12_13_SQ13_Msk
Definition: tle985x.h:7019
#define ADC1_FILT_OUT12_WFR12_Msk
Definition: tle985x.h:6585
#define ADC1_IRQCLR_1_DU1UP_ISC_Pos
Definition: tle985x.h:6725
#define ADC1_CNT0_3_LOWER_CNT_LO_PP3_Pos
Definition: tle985x.h:6410
#define ADC1_CNT0_3_UPPER_CNT_UP_PP1_Pos
Definition: tle985x.h:6435
#define ADC1_IRQCLR_1_IIR_CH9_ISC_Msk
Definition: tle985x.h:6742
#define ADC1_FILT_OUT6_WFR6_Pos
Definition: tle985x.h:6638
#define ADC1_IRQCLR_1_IIR_CH7_ISC_Msk
Definition: tle985x.h:6746
#define ADC1_MMODE0_7_MMODE_5_Pos
Definition: tle985x.h:6944
#define ADC1_FILT_OUT5_FILT_OUT_CH5_Pos
Definition: tle985x.h:6631
#define ADC1_CNT4_7_UPPER_HYST_UP_PP4_Pos
Definition: tle985x.h:6471
#define ADC1_DUIN_SEL_DU1RES_NEG_Msk
Definition: tle985x.h:6540
#define ADC1_TH4_7_UPPER_PP_CH6_UP_Pos
Definition: tle985x.h:7142
#define ADC1_MAX_TIME_MAX_TIME_Msk
Definition: tle985x.h:6936
#define ADC1_IRQEN_1_IIR_CH0_IEN_Msk
Definition: tle985x.h:6830
#define ADC1_IRQCLR_1_EIM_ISC_Msk
Definition: tle985x.h:6732
#define ADC1_IRQEN_1_IIR_CH4_IEN_Pos
Definition: tle985x.h:6821
#define ADC1_SQ6_7_SQ6_Msk
Definition: tle985x.h:7036
#define ADC1_CNT0_3_UPPER_HYST_UP_PP0_Msk
Definition: tle985x.h:6438
#define ADC1_CNT0_3_UPPER_HYST_UP_PP3_Pos
Definition: tle985x.h:6425
#define ADC1_IRQCLR_2_PP_CH0_UP_ISC_Pos
Definition: tle985x.h:6776
#define ADC1_MMODE0_7_MMODE_3_Msk
Definition: tle985x.h:6949
#define ADC1_FILT_OUT7_WFR7_Msk
Definition: tle985x.h:6648
#define ADC1_CNT4_7_LOWER_HYST_LO_PP5_Pos
Definition: tle985x.h:6450
#define ADC1_CNT4_7_UPPER_HYST_UP_PP5_Msk
Definition: tle985x.h:6468
#define ADC1_MMODE0_7_MMODE_1_Msk
Definition: tle985x.h:6953
#define ADC1_CNT4_7_LOWER_HYST_LO_PP4_Pos
Definition: tle985x.h:6454
#define ADC1_IRQEN_1_VS_IEN_Msk
Definition: tle985x.h:6828
#define ADC1_IRQCLR_2_PP_CH2_UP_ISC_Pos
Definition: tle985x.h:6772
#define ADC1_IRQEN_1_IIR_CH9_IEN_Msk
Definition: tle985x.h:6812
#define ADC1_FILT_OUT13_WFR13_Pos
Definition: tle985x.h:6593
#define ADC1_FILT_OUT8_WFR8_Pos
Definition: tle985x.h:6656
#define ADC1_TH4_7_LOWER_PP_CH5_LOW_Pos
Definition: tle985x.h:7135
#define ADC1_IRQCLR_2_PP_CH5_LO_ISC_Msk
Definition: tle985x.h:6783
#define ADC1_CNT4_7_LOWER_CNT_LO_PP6_Pos
Definition: tle985x.h:6448
#define ADC1_FILT_OUT6_FILT_OUT_CH6_Pos
Definition: tle985x.h:6640
#define ADC1_SQ4_5_SQ4_Pos
Definition: tle985x.h:7030
#define ADC1_IRQEN_2_PP_CH3_LO_IEN_Pos
Definition: tle985x.h:6856
#define ADC1_FILT_OUT3_FILT_OUT_CH3_Pos
Definition: tle985x.h:6613
#define ADC1_STATUS_SD_FEEDB_ON_Msk
Definition: tle985x.h:7064
#define ADC1_IRQCLR_2_VS_LO_ISC_Pos
Definition: tle985x.h:6790
#define ADC1_SQ_FB_EIM_ACTIVE_Pos
Definition: tle985x.h:7056
#define ADC1_FILT_OUT1_FILT_OUT_CH1_Pos
Definition: tle985x.h:6559
#define ADC1_DCHTH1_4_LOWER_DCH1_LOW_Pos
Definition: tle985x.h:6524
#define ADC1_CTRL3_SW_MODE_Pos
Definition: tle985x.h:6489
#define ADC1_IRQCLR_2_PP_CH7_LO_ISC_Msk
Definition: tle985x.h:6779
#define ADC1_CHx_ESM_ESM_EN_Pos
Definition: tle985x.h:6401
#define ADC1_IRQCLR_1_DU1LO_ISC_Pos
Definition: tle985x.h:6727
#define ADC1_TH4_7_LOWER_PP_CH5_LOW_Msk
Definition: tle985x.h:7136
#define ADC1_IRQCLR_2_PP_CH2_LO_ISC_Msk
Definition: tle985x.h:6789
#define ADC1_DUIN_SEL_DU1RES_NEG_Pos
Definition: tle985x.h:6539
#define ADC1_CNT0_3_LOWER_CNT_LO_PP2_Msk
Definition: tle985x.h:6415
#define ADC1_IRQCLR_2_VS_UP_ISC_Pos
Definition: tle985x.h:6774
#define ADC1_CNT4_7_LOWER_HYST_LO_PP6_Pos
Definition: tle985x.h:6446
#define ADC1_TH0_3_LOWER_PP_CH1_LOW_Pos
Definition: tle985x.h:7117
#define ADC1_SQ_FB_EIM_ACTIVE_Msk
Definition: tle985x.h:7057
#define ADC1_SQ_FB_SQx_Pos
Definition: tle985x.h:7052
#define ADC1_IRQEN_2_PP_CH6_LO_IEN_Pos
Definition: tle985x.h:6850
#define ADC1_CNT4_7_UPPER_CNT_UP_PP5_Pos
Definition: tle985x.h:6469
#define ADC1_CTRL3_SW_MODE_Msk
Definition: tle985x.h:6490
#define ADC1_CNT4_7_UPPER_CNT_UP_PP7_Msk
Definition: tle985x.h:6462
#define ADC1_CNT0_3_LOWER_HYST_LO_PP0_Pos
Definition: tle985x.h:6420
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH5_EN_Msk
Definition: tle985x.h:6684
#define ADC1_IRQCLR_2_VS_UP_ISC_Msk
Definition: tle985x.h:6775
#define ADC1_IRQCLR_2_PP_CH4_LO_ISC_Msk
Definition: tle985x.h:6785
#define ADC1_IRQEN_2_PP_CH0_LO_IEN_Msk
Definition: tle985x.h:6863
#define ADC1_TH4_7_UPPER_PP_CH7_UP_Pos
Definition: tle985x.h:7140
#define ADC1_IRQCLR_1_IIR_CH4_ISC_Pos
Definition: tle985x.h:6751
#define ADC1_CNT0_3_LOWER_CNT_LO_PP2_Pos
Definition: tle985x.h:6414
#define ADC1_STATUS_SOC_JITTER_Pos
Definition: tle985x.h:7065
#define ADC1_CNT4_7_LOWER_HYST_LO_PP6_Msk
Definition: tle985x.h:6447
#define ADC1_IRQCLR_1_IIR_CH12_ISC_Pos
Definition: tle985x.h:6735
#define ADC1_IRQEN_2_PP_CH2_UP_IEN_Msk
Definition: tle985x.h:6843
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH7_EN_Msk
Definition: tle985x.h:6680
#define ADC1_OFFSETCALIB_OFFSET_DAC_Msk
Definition: tle985x.h:6958
#define ADC1_IRQEN_1_IIR_CH3_IEN_Msk
Definition: tle985x.h:6824
#define ADC1_DCHCNT1_4_LOWER_CNT_LO_DCH1_Msk
Definition: tle985x.h:6517
#define ADC1_CNT4_7_UPPER_CNT_UP_PP4_Msk
Definition: tle985x.h:6474
#define ADC1_TH0_3_LOWER_PP_CH0_LOW_Msk
Definition: tle985x.h:7120
#define ADC1_IRQCLR_1_IIR_CH13_ISC_Msk
Definition: tle985x.h:6734
#define ADC1_IRQCLR_1_IIR_CH0_ISC_Msk
Definition: tle985x.h:6760
#define ADC1_IRQEN_2_VS_UP_IEN_Msk
Definition: tle985x.h:6845
#define ADC1_MMODE0_7_MMODE_2_Pos
Definition: tle985x.h:6950
#define ADC1_CNT4_7_UPPER_HYST_UP_PP6_Pos
Definition: tle985x.h:6463
#define ADC1_SQ8_9_SQ8_Pos
Definition: tle985x.h:7040
#define ADC1_CNT4_7_UPPER_HYST_UP_PP4_Msk
Definition: tle985x.h:6472
#define ADC1_SQ0_1_SQ1_Msk
Definition: tle985x.h:7009
#define ADC1_CHx_ESM_ESM_0_Msk
Definition: tle985x.h:6406
#define ADC1_IRQEN_2_VS_LO_IEN_Msk
Definition: tle985x.h:6861
#define ADC1_CNT0_3_LOWER_HYST_LO_PP1_Msk
Definition: tle985x.h:6417
#define ADC1_CHx_ESM_ADC1_ESM_TRIG_SEL_Pos
Definition: tle985x.h:6403
#define ADC1_FILT_OUT2_WFR2_Msk
Definition: tle985x.h:6603
#define ADC1_IRQEN_1_IIR_CH7_IEN_Pos
Definition: tle985x.h:6815
#define ADC1_CNT0_3_LOWER_HYST_LO_PP2_Pos
Definition: tle985x.h:6412
#define ADC1_IRQCLR_1_IIR_CH5_ISC_Pos
Definition: tle985x.h:6749
#define ADC1_SQ2_3_SQ3_Msk
Definition: tle985x.h:7024
#define ADC1_TH4_7_LOWER_PP_CH7_LOW_Msk
Definition: tle985x.h:7132
#define ADC1_TH0_3_LOWER_PP_CH2_LOW_Pos
Definition: tle985x.h:7115
#define ADC1_IRQEN_2_PP_CH5_LO_IEN_Pos
Definition: tle985x.h:6852
#define ADC1_CNT4_7_LOWER_CNT_LO_PP7_Pos
Definition: tle985x.h:6444
#define ADC1_CNT4_7_UPPER_HYST_UP_PP5_Pos
Definition: tle985x.h:6467
#define ADC1_TH4_7_UPPER_PP_CH7_UP_Msk
Definition: tle985x.h:7141
#define ADC1_TH0_3_UPPER_PP_CH3_UP_Msk
Definition: tle985x.h:7123
#define ADC1_FILT_OUT1_WFR1_Pos
Definition: tle985x.h:6557
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH0_EN_Pos
Definition: tle985x.h:6693
#define ADC1_CNT0_3_UPPER_CNT_UP_PP2_Msk
Definition: tle985x.h:6432
#define ADC1_FILT_OUT8_WFR8_Msk
Definition: tle985x.h:6657
#define ADC1_CNT4_7_LOWER_HYST_LO_PP7_Pos
Definition: tle985x.h:6442
#define ADC1_OFFSETCALIB_OFFSET_SHIFT_Pos
Definition: tle985x.h:6959
#define ADC1_FILT_OUT2_WFR2_Pos
Definition: tle985x.h:6602
#define ADC1_CNT4_7_UPPER_HYST_UP_PP7_Msk
Definition: tle985x.h:6460
#define ADC1_TH0_3_LOWER_PP_CH3_LOW_Msk
Definition: tle985x.h:7114
#define ADC1_SQ8_9_SQ9_Msk
Definition: tle985x.h:7039
#define ADC1_SQ6_7_SQ7_Pos
Definition: tle985x.h:7033
#define ADC1_MAX_TIME_MAX_TIME_Pos
Definition: tle985x.h:6935
#define ADC1_CTRL_STS_SW_CH_SEL_Pos
Definition: tle985x.h:6499
#define ADC1_FILT_OUT2_FILT_OUT_CH2_Pos
Definition: tle985x.h:6604
#define ADC1_FILT_OUT3_WFR3_Msk
Definition: tle985x.h:6612
#define ADC1_IRQCLR_2_PP_CH0_UP_ISC_Msk
Definition: tle985x.h:6777
#define ADC1_CHx_EIM_EIM_REP_Pos
Definition: tle985x.h:6394
#define ADC1_FILT_OUT2_FILT_OUT_CH2_Msk
Definition: tle985x.h:6605
#define ADC1_FILT_OUT9_FILT_OUT_CH9_Pos
Definition: tle985x.h:6667
#define ADC1_IRQCLR_1_IIR_CH3_ISC_Pos
Definition: tle985x.h:6753
#define ADC1_TH0_3_LOWER_PP_CH1_LOW_Msk
Definition: tle985x.h:7118
#define ADC1_FILT_OUT13_FILT_OUT_CH13_Msk
Definition: tle985x.h:6596
#define ADC1_FILT_OUT6_WFR6_Msk
Definition: tle985x.h:6639
#define ADC1_FILT_OUT4_FILT_OUT_CH4_Pos
Definition: tle985x.h:6622
#define ADC1_IRQCLR_2_PP_CH3_UP_ISC_Pos
Definition: tle985x.h:6770
#define ADC1_IRQCLR_2_PP_CH4_UP_ISC_Pos
Definition: tle985x.h:6768
#define ADC1_DCHCNT1_4_UPPER_HYST_UP_DCH1_Pos
Definition: tle985x.h:6519
#define ADC1_CNT0_3_LOWER_HYST_LO_PP0_Msk
Definition: tle985x.h:6421
#define ADC1_CHx_EIM_EIM_CHx_Msk
Definition: tle985x.h:6397
#define ADC1_DCHCNT1_4_LOWER_HYST_LO_DCH1_Msk
Definition: tle985x.h:6515
#define ADC1_TH4_7_LOWER_PP_CH4_LOW_Msk
Definition: tle985x.h:7138
#define ADC1_SQ12_13_SQ12_Msk
Definition: tle985x.h:7021
#define ADC1_IRQCLR_1_VS_ISC_Msk
Definition: tle985x.h:6758
#define ADC1_CNT4_7_UPPER_HYST_UP_PP6_Msk
Definition: tle985x.h:6464
#define ADC1_OFFSETCALIB_OFFSET_SHIFT_Msk
Definition: tle985x.h:6960
#define ADC1_CTRL_STS_PD_N_Pos
Definition: tle985x.h:6511
#define ADC1_CNT4_7_LOWER_CNT_LO_PP7_Msk
Definition: tle985x.h:6445
#define ADC1_IRQCLR_2_PP_CH7_UP_ISC_Msk
Definition: tle985x.h:6763
#define ADC1_IRQEN_1_IIR_CH8_IEN_Pos
Definition: tle985x.h:6813
#define ADC1_TH0_3_UPPER_PP_CH3_UP_Pos
Definition: tle985x.h:7122
#define ADC1_IRQEN_1_IIR_CH13_IEN_Pos
Definition: tle985x.h:6803
#define ADC1_FILT_OUT5_WFR5_Msk
Definition: tle985x.h:6630
#define ADC1_TH0_3_LOWER_PP_CH0_LOW_Pos
Definition: tle985x.h:7119
#define ADC1_IRQEN_2_PP_CH7_UP_IEN_Pos
Definition: tle985x.h:6832
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH1_EN_Pos
Definition: tle985x.h:6691
#define ADC1_FILT_OUT12_FILT_OUT_CH12_Pos
Definition: tle985x.h:6586
#define ADC1_CNT4_7_LOWER_HYST_LO_PP7_Msk
Definition: tle985x.h:6443
#define ADC1_IRQEN_2_PP_CH5_UP_IEN_Pos
Definition: tle985x.h:6836
#define ADC1_CTRL_STS_SOOC_Msk
Definition: tle985x.h:6510
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH2_EN_Msk
Definition: tle985x.h:6690
#define ADC1_CHx_EIM_ADC1_EIM_TRIG_SEL_Msk
Definition: tle985x.h:6391
#define ADC1_IRQCLR_2_PP_CH4_UP_ISC_Msk
Definition: tle985x.h:6769
#define ADC1_CHx_EIM_ADC1_EIM_TRIG_SEL_Pos
Definition: tle985x.h:6390
#define ADC1_CNT4_7_LOWER_CNT_LO_PP5_Msk
Definition: tle985x.h:6453
#define ADC1_CNT0_3_LOWER_HYST_LO_PP3_Pos
Definition: tle985x.h:6408
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH6_EN_Pos
Definition: tle985x.h:6681
#define ADC1_CNT0_3_UPPER_HYST_UP_PP0_Pos
Definition: tle985x.h:6437
#define ADC1_DCHTH1_4_UPPER_DCH1_UP_Pos
Definition: tle985x.h:6527
#define ADC1_TH0_3_UPPER_PP_CH1_UP_Pos
Definition: tle985x.h:7126
#define ADC1_CHx_ESM_ESM_EN_Msk
Definition: tle985x.h:6402
#define ADC1_DIFFCH_OUT1_DWFR1_Msk
Definition: tle985x.h:6535
#define ADC1_DCHCNT1_4_LOWER_HYST_LO_DCH1_Pos
Definition: tle985x.h:6514
#define ADC1_MMODE0_7_MMODE_D1_Pos
Definition: tle985x.h:6938
#define ADC1_IRQEN_1_DU1LO_IEN_Pos
Definition: tle985x.h:6797
#define ADC1_IRQEN_1_IIR_CH12_IEN_Msk
Definition: tle985x.h:6806
#define ADC1_IRQCLR_1_ESM_ISC_Msk
Definition: tle985x.h:6730
#define ADC1_CNT4_7_UPPER_CNT_UP_PP6_Pos
Definition: tle985x.h:6465
#define ADC1_FILT_OUT9_WFR9_Pos
Definition: tle985x.h:6665
#define ADC1_IRQCLR_2_PP_CH2_UP_ISC_Msk
Definition: tle985x.h:6773
#define ADC1_IRQCLR_1_DU1UP_ISC_Msk
Definition: tle985x.h:6726
#define ADC1_MMODE0_7_MMODE_3_Pos
Definition: tle985x.h:6948
#define ADC1_DUIN_SEL_DU1_EN_Msk
Definition: tle985x.h:6542
#define ADC1_CTRL_STS_EOC_Pos
Definition: tle985x.h:6501
#define ADC1_MMODE0_7_MMODE_5_Msk
Definition: tle985x.h:6945
#define ADC1_CNT0_3_UPPER_CNT_UP_PP0_Msk
Definition: tle985x.h:6440
#define ADC1_SQ_FB_ESM_ACTIVE_Msk
Definition: tle985x.h:7055
#define ADC1_IRQEN_1_IIR_CH6_IEN_Msk
Definition: tle985x.h:6818
#define ADC1_CHx_EIM_EIM_EN_Pos
Definition: tle985x.h:6392
#define ADC1_CHx_ESM_ADC1_ESM_TRIG_SEL_Msk
Definition: tle985x.h:6404
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH1_EN_Msk
Definition: tle985x.h:6692
#define ADC1_IRQCLR_1_IIR_CH3_ISC_Msk
Definition: tle985x.h:6754
#define ADC1_IRQEN_2_PP_CH6_LO_IEN_Msk
Definition: tle985x.h:6851
#define ADC1_IRQEN_2_PP_CH0_LO_IEN_Pos
Definition: tle985x.h:6862
#define ADC1_IRQEN_1_IIR_CH4_IEN_Msk
Definition: tle985x.h:6822
#define ADC1_SQ8_9_SQ8_Msk
Definition: tle985x.h:7041
#define ADC1_FILT_OUT7_WFR7_Pos
Definition: tle985x.h:6647
#define ADC1_CTRL_STS_STRTUP_DIS_Pos
Definition: tle985x.h:6497
#define ADC1_CNT0_3_UPPER_HYST_UP_PP2_Msk
Definition: tle985x.h:6430
#define ADC1_STATUS_SD_FEEDB_ON_Pos
Definition: tle985x.h:7063
#define ADC1_IRQCLR_1_IIR_CH9_ISC_Pos
Definition: tle985x.h:6741
#define ADC1_CNT4_7_LOWER_HYST_LO_PP5_Msk
Definition: tle985x.h:6451
#define ADC1_IRQCLR_1_IIR_CH13_ISC_Pos
Definition: tle985x.h:6733
#define ADC1_IRQEN_2_PP_CH4_UP_IEN_Msk
Definition: tle985x.h:6839
#define ADC1_SQ4_5_SQ4_Msk
Definition: tle985x.h:7031
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH4_EN_Pos
Definition: tle985x.h:6685
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH0_EN_Msk
Definition: tle985x.h:6694
#define ADC1_CNT4_7_UPPER_CNT_UP_PP5_Msk
Definition: tle985x.h:6470
#define ADC1_IRQCLR_1_EIM_ISC_Pos
Definition: tle985x.h:6731
#define ADC1_TH0_3_UPPER_PP_CH1_UP_Msk
Definition: tle985x.h:7127
#define ADC1_FILT_OUT12_WFR12_Pos
Definition: tle985x.h:6584
#define ADC1_FILT_OUT7_FILT_OUT_CH7_Msk
Definition: tle985x.h:6650
#define ADC1_IRQCLR_2_PP_CH3_UP_ISC_Msk
Definition: tle985x.h:6771
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH4_EN_Msk
Definition: tle985x.h:6686
#define ADC1_IRQEN_1_IIR_CH5_IEN_Pos
Definition: tle985x.h:6819
#define ADC1_SQ_FB_SQ_STOP_Msk
Definition: tle985x.h:7059
#define ADC1_IRQCLR_1_IIR_CH2_ISC_Msk
Definition: tle985x.h:6756
#define ADC1_IRQCLR_1_IIR_CH2_ISC_Pos
Definition: tle985x.h:6755
#define ADC1_SQ2_3_SQ3_Pos
Definition: tle985x.h:7023
#define ADC1_CNT4_7_UPPER_CNT_UP_PP4_Pos
Definition: tle985x.h:6473
#define ADC1_DIFFCH_OUT1_DWFR1_Pos
Definition: tle985x.h:6534
#define ADC1_CNT4_7_LOWER_HYST_LO_PP4_Msk
Definition: tle985x.h:6455
#define ADC1_CTRL_STS_PD_N_Msk
Definition: tle985x.h:6512
#define ADC1_SQ0_1_SQ0_Msk
Definition: tle985x.h:7011
#define ADC1_SQ_FB_CHx_Msk
Definition: tle985x.h:7051
#define ADC1_IRQEN_2_PP_CH2_LO_IEN_Pos
Definition: tle985x.h:6858
#define ADC1_IRQCLR_2_PP_CH6_UP_ISC_Pos
Definition: tle985x.h:6764
#define ADC1_CNT0_3_UPPER_HYST_UP_PP1_Msk
Definition: tle985x.h:6434
#define ADC1_CNT0_3_UPPER_HYST_UP_PP1_Pos
Definition: tle985x.h:6433
#define ADC1_SQ0_1_SQ1_Pos
Definition: tle985x.h:7008
#define ADC1_IRQCLR_2_PP_CH7_UP_ISC_Pos
Definition: tle985x.h:6762
#define ADC1_SQ4_5_SQ5_Pos
Definition: tle985x.h:7028
#define ADC1_DIFFCH_OUT1_DCH1_Msk
Definition: tle985x.h:6537
#define ADC1_FILT_OUTEIM_FILT_OUT_EIM_Msk
Definition: tle985x.h:6677
#define ADC1_IRQEN_2_VS_UP_IEN_Pos
Definition: tle985x.h:6844
#define ADC1_CNT0_3_LOWER_HYST_LO_PP1_Pos
Definition: tle985x.h:6416
#define ADC1_CNT4_7_UPPER_CNT_UP_PP7_Pos
Definition: tle985x.h:6461
#define ADC1_IRQEN_1_IIR_CH5_IEN_Msk
Definition: tle985x.h:6820
#define ADC1_IRQEN_1_IIR_CH0_IEN_Pos
Definition: tle985x.h:6829
#define ADC1_FILT_OUT3_WFR3_Pos
Definition: tle985x.h:6611
#define ADC1_CNT4_7_UPPER_HYST_UP_PP7_Pos
Definition: tle985x.h:6459
#define ADC1_SQ10_11_SQ11_Msk
Definition: tle985x.h:7014
#define ADC1_IRQEN_1_IIR_CH2_IEN_Msk
Definition: tle985x.h:6826
#define ADC1_TH4_7_LOWER_PP_CH7_LOW_Pos
Definition: tle985x.h:7131
#define ADC1_FILT_OUT4_FILT_OUT_CH4_Msk
Definition: tle985x.h:6623
#define ADC1_STSCLR_1_DU1LO_SC_Msk
Definition: tle985x.h:7111
#define ADC1_CNT0_3_UPPER_CNT_UP_PP3_Msk
Definition: tle985x.h:6428
#define ADC1_CHx_ESM_ESM_0_Pos
Definition: tle985x.h:6405
#define ADC1_MMODE0_7_MMODE_2_Msk
Definition: tle985x.h:6951
#define ADC1_IRQEN_1_IIR_CH7_IEN_Msk
Definition: tle985x.h:6816
#define ADC1_TH0_3_UPPER_PP_CH0_UP_Pos
Definition: tle985x.h:7128
#define ADC1_IRQEN_2_PP_CH3_UP_IEN_Pos
Definition: tle985x.h:6840
#define ADC1_IRQEN_1_DU1UP_IEN_Msk
Definition: tle985x.h:6796
#define ADC1_TH4_7_UPPER_PP_CH6_UP_Msk
Definition: tle985x.h:7143
#define ADC1_MMODE0_7_MMODE_4_Msk
Definition: tle985x.h:6947
#define ADC1_IRQEN_2_PP_CH6_UP_IEN_Pos
Definition: tle985x.h:6834
#define ADC1_TH4_7_LOWER_PP_CH4_LOW_Pos
Definition: tle985x.h:7137
#define ADC1_FILT_OUTEIM_FILT_OUT_EIM_Pos
Definition: tle985x.h:6676
#define ADC1_IRQCLR_1_IIR_CH8_ISC_Msk
Definition: tle985x.h:6744
#define ADC1_CNT0_3_UPPER_CNT_UP_PP3_Pos
Definition: tle985x.h:6427
#define ADC1_IRQEN_1_IIR_CH13_IEN_Msk
Definition: tle985x.h:6804
#define ADC1_TH4_7_LOWER_PP_CH6_LOW_Pos
Definition: tle985x.h:7133
#define ADC1_CNT4_7_LOWER_CNT_LO_PP5_Pos
Definition: tle985x.h:6452
#define ADC1_IRQEN_1_IIR_CH3_IEN_Pos
Definition: tle985x.h:6823
#define ADC1_DCHCNT1_4_UPPER_CNT_UP_DCH1_Pos
Definition: tle985x.h:6521
#define ADC1_CHx_EIM_EIM_EN_Msk
Definition: tle985x.h:6393
#define ADC1_IRQEN_2_PP_CH5_LO_IEN_Msk
Definition: tle985x.h:6853
#define ADC1_TH4_7_UPPER_PP_CH4_UP_Msk
Definition: tle985x.h:7147
#define ADC1_MMODE0_7_MMODE_7_Msk
Definition: tle985x.h:6941
#define ADC1_CNT0_3_UPPER_CNT_UP_PP2_Pos
Definition: tle985x.h:6431
#define ADC1_IRQEN_2_PP_CH4_UP_IEN_Pos
Definition: tle985x.h:6838
#define ADC1_FILT_OUT0_WFR0_Msk
Definition: tle985x.h:6549
#define ADC1_IRQEN_1_ESM_IEN_Pos
Definition: tle985x.h:6799
#define ADC1_STSCLR_1_DU1LO_SC_Pos
Definition: tle985x.h:7110
#define ADC1_STSCLR_1_DU1UP_SC_Pos
Definition: tle985x.h:7108
#define ADC1_FILT_OUT8_FILT_OUT_CH8_Pos
Definition: tle985x.h:6658
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH6_EN_Msk
Definition: tle985x.h:6682
#define ADC1_TH0_3_LOWER_PP_CH2_LOW_Msk
Definition: tle985x.h:7116
#define ADC1_FILT_OUT1_WFR1_Msk
Definition: tle985x.h:6558
#define ADC1_FILT_OUT4_WFR4_Pos
Definition: tle985x.h:6620
#define ADC1_IRQCLR_1_IIR_CH7_ISC_Pos
Definition: tle985x.h:6745
#define ADC1_IRQEN_1_IIR_CH8_IEN_Msk
Definition: tle985x.h:6814
#define ADC1_FILT_OUT7_FILT_OUT_CH7_Pos
Definition: tle985x.h:6649
#define ADC1_MMODE0_7_MMODE_6_Msk
Definition: tle985x.h:6943
#define ADC1_IRQEN_1_DU1LO_IEN_Msk
Definition: tle985x.h:6798
#define ADC1_IRQEN_1_DU1UP_IEN_Pos
Definition: tle985x.h:6795
#define ADC1_DCHTH1_4_UPPER_DCH1_UP_Msk
Definition: tle985x.h:6528
#define ADC1_CNT0_3_LOWER_CNT_LO_PP0_Msk
Definition: tle985x.h:6423
#define ADC1_MMODE0_7_MMODE_7_Pos
Definition: tle985x.h:6940
#define ADC1_IRQCLR_1_DU1LO_ISC_Msk
Definition: tle985x.h:6728
#define ADC1_FILT_OUT9_FILT_OUT_CH9_Msk
Definition: tle985x.h:6668
#define ADC1_STATUS_SOC_JITTER_Msk
Definition: tle985x.h:7066
#define ADC1_SQ_FB_SQ_STOP_Pos
Definition: tle985x.h:7058
#define ADC1_IRQCLR_1_IIR_CH6_ISC_Msk
Definition: tle985x.h:6748
#define ADC1_FILT_OUT5_WFR5_Pos
Definition: tle985x.h:6629
#define ADC1_CNT4_7_LOWER_CNT_LO_PP4_Pos
Definition: tle985x.h:6456
#define ADC1_CNT0_3_UPPER_CNT_UP_PP1_Msk
Definition: tle985x.h:6436
#define ADC1_IRQEN_2_PP_CH7_UP_IEN_Msk
Definition: tle985x.h:6833
#define ADC1_CNT0_3_LOWER_HYST_LO_PP2_Msk
Definition: tle985x.h:6413
#define ADC1_IRQEN_2_PP_CH2_UP_IEN_Pos
Definition: tle985x.h:6842
#define ADC1_SQ0_1_SQ0_Pos
Definition: tle985x.h:7010
#define ADC1_SQ6_7_SQ6_Pos
Definition: tle985x.h:7035
#define ADC1_IRQEN_2_PP_CH4_LO_IEN_Pos
Definition: tle985x.h:6854
#define ADC1_TH4_7_UPPER_PP_CH4_UP_Pos
Definition: tle985x.h:7146
#define ADC1_TH0_3_UPPER_PP_CH2_UP_Pos
Definition: tle985x.h:7124
#define ADC1_IRQEN_2_PP_CH2_LO_IEN_Msk
Definition: tle985x.h:6859
#define ADC1_SQ12_13_SQ13_Pos
Definition: tle985x.h:7018
#define ADC1_IRQEN_2_PP_CH0_UP_IEN_Pos
Definition: tle985x.h:6846
#define ADC1_CHx_EIM_EIM_REP_Msk
Definition: tle985x.h:6395
#define ADC1_IRQCLR_2_PP_CH2_LO_ISC_Pos
Definition: tle985x.h:6788
#define ADC1_IRQEN_2_PP_CH0_UP_IEN_Msk
Definition: tle985x.h:6847
#define ADC1_IRQCLR_1_IIR_CH0_ISC_Pos
Definition: tle985x.h:6759
#define ADC1_SQ4_5_SQ5_Msk
Definition: tle985x.h:7029
#define ADC1_TH0_3_UPPER_PP_CH0_UP_Msk
Definition: tle985x.h:7129
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH3_EN_Msk
Definition: tle985x.h:6688
#define ADC1_FILT_OUT12_FILT_OUT_CH12_Msk
Definition: tle985x.h:6587
#define ADC1_IRQCLR_2_PP_CH5_LO_ISC_Pos
Definition: tle985x.h:6782
#define ADC1_SQ_FB_CHx_Pos
Definition: tle985x.h:7050
#define ADC1_IRQCLR_2_PP_CH5_UP_ISC_Msk
Definition: tle985x.h:6767
#define ADC1_CTRL_STS_SW_CH_SEL_Msk
Definition: tle985x.h:6500
#define ADC1_MMODE0_7_MMODE_D1_Msk
Definition: tle985x.h:6939
#define ADC1_CHx_EIM_EIM_CHx_Pos
Definition: tle985x.h:6396
#define ADC1_IRQCLR_2_PP_CH3_LO_ISC_Pos
Definition: tle985x.h:6786
#define ADC1_CTRL_STS_SOS_Pos
Definition: tle985x.h:6507
#define ADC1_IRQCLR_2_PP_CH0_LO_ISC_Pos
Definition: tle985x.h:6792
#define ADC1_IRQEN_1_VS_IEN_Pos
Definition: tle985x.h:6827
#define ADC1_TH0_3_LOWER_PP_CH3_LOW_Pos
Definition: tle985x.h:7113
#define ADC1_FILT_OUT8_FILT_OUT_CH8_Msk
Definition: tle985x.h:6659
#define ADC1_CNT4_7_LOWER_CNT_LO_PP6_Msk
Definition: tle985x.h:6449
#define ADC1_SQ8_9_SQ9_Pos
Definition: tle985x.h:7038
#define ADC1_CNT0_3_LOWER_HYST_LO_PP3_Msk
Definition: tle985x.h:6409
#define ADC1_IRQEN_2_PP_CH3_LO_IEN_Msk
Definition: tle985x.h:6857
#define ADC1_IRQEN_1_IIR_CH6_IEN_Pos
Definition: tle985x.h:6817
#define ADC1_IRQCLR_1_IIR_CH4_ISC_Msk
Definition: tle985x.h:6752
#define ADC1_SQ10_11_SQ10_Pos
Definition: tle985x.h:7015
#define ADC1_IRQCLR_2_PP_CH4_LO_ISC_Pos
Definition: tle985x.h:6784
#define ADC1_CNT0_3_LOWER_CNT_LO_PP1_Pos
Definition: tle985x.h:6418
#define ADC1_TH0_3_UPPER_PP_CH2_UP_Msk
Definition: tle985x.h:7125
#define ADC1_CTRL_STS_SOS_Msk
Definition: tle985x.h:6508
#define ADC1_FILT_OUT5_FILT_OUT_CH5_Msk
Definition: tle985x.h:6632
#define ADC1_FILT_OUT3_FILT_OUT_CH3_Msk
Definition: tle985x.h:6614
#define ADC1_SQ2_3_SQ2_Msk
Definition: tle985x.h:7026
#define ADC1_IRQEN_1_IIR_CH2_IEN_Pos
Definition: tle985x.h:6825
#define ADC1_IRQCLR_1_VS_ISC_Pos
Definition: tle985x.h:6757
#define ADC1_IRQCLR_2_PP_CH3_LO_ISC_Msk
Definition: tle985x.h:6787
#define ADC1_IRQEN_1_ESM_IEN_Msk
Definition: tle985x.h:6800
#define ADC1_IRQEN_1_EIM_IEN_Pos
Definition: tle985x.h:6801
#define ADC1_IRQEN_2_PP_CH3_UP_IEN_Msk
Definition: tle985x.h:6841
#define ADC1_DUIN_SEL_DU1_EN_Pos
Definition: tle985x.h:6541
#define ADC1_IRQCLR_1_IIR_CH8_ISC_Pos
Definition: tle985x.h:6743
#define ADC1_TH4_7_LOWER_PP_CH6_LOW_Msk
Definition: tle985x.h:7134
#define ADC1_SQ12_13_SQ12_Pos
Definition: tle985x.h:7020
#define ADC1_DIFFCH_OUT1_DCH1_Pos
Definition: tle985x.h:6536
#define ADC1_IRQCLR_2_PP_CH5_UP_ISC_Pos
Definition: tle985x.h:6766
#define ADC1_DCHTH1_4_LOWER_DCH1_LOW_Msk
Definition: tle985x.h:6525
#define ADC1_IRQEN_2_PP_CH6_UP_IEN_Msk
Definition: tle985x.h:6835
#define ADC1_FILT_UPLO_CTRL_FUL_PP_CH7_EN_Pos
Definition: tle985x.h:6679
#define ADC1_MMODE0_7_MMODE_1_Pos
Definition: tle985x.h:6952
#define ADC1_MMODE0_7_MMODE_0_Pos
Definition: tle985x.h:6954
#define ADC1_FILT_OUT0_FILT_OUT_CH0_Msk
Definition: tle985x.h:6551
#define ADC1_CNT0_3_LOWER_CNT_LO_PP0_Pos
Definition: tle985x.h:6422
#define ADC1_IRQCLR_2_PP_CH0_LO_ISC_Msk
Definition: tle985x.h:6793
#define ADC1_IRQEN_1_IIR_CH12_IEN_Pos
Definition: tle985x.h:6805
#define ADC1_IRQCLR_1_IIR_CH12_ISC_Msk
Definition: tle985x.h:6736
#define ADC1_CNT0_3_LOWER_CNT_LO_PP3_Msk
Definition: tle985x.h:6411
#define ADC1_CNT4_7_LOWER_CNT_LO_PP4_Msk
Definition: tle985x.h:6457
#define ADC1_IRQEN_2_PP_CH7_LO_IEN_Pos
Definition: tle985x.h:6848
#define ADC1_IRQCLR_2_PP_CH6_LO_ISC_Msk
Definition: tle985x.h:6781
#define ADC1_MMODE0_7_MMODE_6_Pos
Definition: tle985x.h:6942
#define ADC1_IRQCLR_2_PP_CH6_LO_ISC_Pos
Definition: tle985x.h:6780
#define ADC1_IRQEN_2_PP_CH4_LO_IEN_Msk
Definition: tle985x.h:6855
SFR low level access library.
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:448
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:423
INLINE void Field_Wrt32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:358
INLINE uint8 u8_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 8-bit field of a 32-bit register.
Definition: sfr_access.h:438
INLINE void Field_Mod32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:378
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155