Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields

Detailed Description

PMU (PMU)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   LIN_WAKE: 1
 
      __IM uint32_t   MON: 1
 
      __IM uint32_t   GPIO0: 1
 
      __IM uint32_t   GPIO1: 1
 
      __IM uint32_t   CYC_WAKE: 1
 
      __IM uint32_t   FAIL: 1
 
      __IM uint32_t   GPIO2: 1
 
      __IM   uint32_t: 1
 
      __IM uint32_t   MON1_WAKE_STS: 1
 
      __IM uint32_t   MON2_WAKE_STS: 1
 
      __IM uint32_t   MON3_WAKE_STS: 1
 
      __IM uint32_t   MON4_WAKE_STS: 1
 
      __IM uint32_t   MON5_WAKE_STS: 1
 
      __IM uint32_t   PMU_OT: 1
 
      __IM uint32_t   VDDEXT_OT: 1
 
      __IM uint32_t   VDDEXT_UV: 1
 
   }   bit
 
WAKE_STATUS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   GPIO0_STS_0: 1
 
      __IM uint32_t   GPIO0_STS_1: 1
 
      __IM uint32_t   GPIO0_STS_2: 1
 
      __IM uint32_t   GPIO0_STS_3: 1
 
      __IM uint32_t   GPIO0_STS_4: 1
 
      __IM uint32_t   GPIO0_STS_5: 1
 
      __IM   uint32_t: 2
 
      __IM uint32_t   GPIO1_STS_0: 1
 
      __IM uint32_t   GPIO1_STS_1: 1
 
      __IM uint32_t   GPIO1_STS_2: 1
 
      __IM uint32_t   GPIO1_STS_4: 1
 
   }   bit
 
GPIO_WAKE_STATUS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   PMU_1V5_OVERVOLT: 1
 
      __IM uint32_t   PMU_1V5_OVERLOAD: 1
 
      __IOM uint32_t   PMU_1V5_FAIL_EN: 1
 
      __IM uint32_t   PMU_OVERTEMP: 1
 
      __IM uint32_t   PMU_5V_OVERVOLT: 1
 
      __IM uint32_t   PMU_5V_OVERLOAD: 1
 
      __IOM uint32_t   PMU_5V_FAIL_EN: 1
 
      __IM   uint32_t: 1
 
      __OM uint32_t   PMU_1V5_OVERVOLT_SC: 1
 
      __OM uint32_t   PMU_1V5_OVERLOAD_SC: 1
 
      __OM uint32_t   PMU_OVERTEMP_SC: 1
 
      __OM uint32_t   PMU_5V_OVERVOLT_SC: 1
 
      __OM uint32_t   PMU_5V_OVERLOAD_SC: 1
 
   }   bit
 
SUPPLY_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VDDEXT_ENABLE: 1
 
      __IOM uint32_t   VDDEXT_CYC_EN: 1
 
      __IOM uint32_t   VDDEXT_FAIL_EN: 1
 
      __IM uint32_t   VDDEXT_OT_IS: 1
 
      __IM uint32_t   VDDEXT_UV_IS: 1
 
      __IM uint32_t   VDDEXT_OT_STS: 1
 
      __IM uint32_t   VDDEXT_OT: 1
 
      __IM uint32_t   VDDEXT_STABLE: 1
 
      __IM   uint32_t: 3
 
      __OM uint32_t   VDDEXT_OT_ISC: 1
 
      __OM uint32_t   VDDEXT_UV_ISC: 1
 
      __OM uint32_t   VDDEXT_OT_SC: 1
 
   }   bit
 
VDDEXT_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SYS_FAIL: 1
 
      __IOM uint32_t   PMU_WAKE: 1
 
      __IOM uint32_t   PMU_SleepEX: 1
 
      __IOM uint32_t   PMU_LPR: 1
 
      __IOM uint32_t   PMU_ClkWDT: 1
 
      __IOM uint32_t   PMU_ExtWDT: 1
 
      __IOM uint32_t   PMU_PIN: 1
 
      __IOM uint32_t   PMU_VS_POR: 1
 
      __IOM uint32_t   PMU_IntWDT: 1
 
      __IOM uint32_t   PMU_SOFT: 1
 
      __IOM uint32_t   LOCKUP: 1
 
   }   bit
 
RESET_STS
 
__IM uint32_t RESERVED [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WAKE_W_RST: 1
 
      __IOM uint32_t   EN_0V9_N: 1
 
      __IOM uint32_t   CYC_WAKE_EN: 1
 
      __IOM uint32_t   CYC_SENSE_EN: 1
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   CYC_SENSE_M03: 4
 
      __IOM uint32_t   CYC_SENSE_E01: 2
 
      __IOM uint32_t   CYC_WAKE_M03: 4
 
      __IOM uint32_t   CYC_WAKE_E01: 2
 
      __IOM uint32_t   CYC_SENSE_S_DEL: 3
 
   }   bit
 
SLEEP
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   GL1_CYC_ON: 1
 
      __IOM uint32_t   GL1_HOLD_ON: 1
 
      __IOM uint32_t   GL2_CYC_ON: 1
 
      __IOM uint32_t   GL2_HOLD_ON: 1
 
      __IOM uint32_t   CNF_ON: 2
 
      __IOM uint32_t   CNF_OFF: 2
 
   }   bit
 
DRV_CTRL
 
__IM uint32_t RESERVED1 [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MON1_EN: 1
 
      __IOM uint32_t   MON1_FALL: 1
 
      __IOM uint32_t   MON1_RISE: 1
 
      __IOM uint32_t   MON1_CYC: 1
 
      __IOM uint32_t   MON1_PD: 1
 
      __IOM uint32_t   MON1_PU: 1
 
      __IOM uint32_t   MON1_NSLEEP_SPARE: 1
 
      __IM uint32_t   MON1_STS: 1
 
      __IOM uint32_t   MON2_EN: 1
 
      __IOM uint32_t   MON2_FALL: 1
 
      __IOM uint32_t   MON2_RISE: 1
 
      __IOM uint32_t   MON2_CYC: 1
 
      __IOM uint32_t   MON2_PD: 1
 
      __IOM uint32_t   MON2_PU: 1
 
      __IOM uint32_t   MON2_NSLEEP_SPARE: 1
 
      __IM uint32_t   MON2_STS: 1
 
      __IOM uint32_t   MON3_EN: 1
 
      __IOM uint32_t   MON3_FALL: 1
 
      __IOM uint32_t   MON3_RISE: 1
 
      __IOM uint32_t   MON3_CYC: 1
 
      __IOM uint32_t   MON3_PD: 1
 
      __IOM uint32_t   MON3_PU: 1
 
      __IOM uint32_t   MON3_NSLEEP_SPARE: 1
 
      __IM uint32_t   MON3_STS: 1
 
      __IOM uint32_t   MON4_EN: 1
 
      __IOM uint32_t   MON4_FALL: 1
 
      __IOM uint32_t   MON4_RISE: 1
 
      __IOM uint32_t   MON4_CYC: 1
 
      __IOM uint32_t   MON4_PD: 1
 
      __IOM uint32_t   MON4_PU: 1
 
      __IOM uint32_t   MON4_NSLEEP_SPARE: 1
 
      __IM uint32_t   MON4_STS: 1
 
   }   bit
 
MON_CNF1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MON5_EN: 1
 
      __IOM uint32_t   MON5_FALL: 1
 
      __IOM uint32_t   MON5_RISE: 1
 
      __IOM uint32_t   MON5_CYC: 1
 
      __IOM uint32_t   MON5_PD: 1
 
      __IOM uint32_t   MON5_PU: 1
 
      __IOM uint32_t   MON5_NSLEEP_SPARE: 1
 
      __IM uint32_t   MON5_STS: 1
 
   }   bit
 
MON_CNF2
 
__IM uint32_t RESERVED2 [5]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 7
 
      __IOM uint32_t   LIN_WAKE_EN: 1
 
   }   bit
 
LIN_WAKE_EN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PMU_OT_TH_CNF: 4
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PMU_OT_INT_EN: 1
 
      __IOM uint32_t   PMU_OT_WAKE_EN: 1
 
      __IOM uint32_t   PMU_OT_EN: 1
 
   }   bit
 
OT_CTRL
 
__IM uint32_t RESERVED3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 2
 
      __IOM uint32_t   HS1_CYC_EN: 1
 
      __IOM uint32_t   SPARE: 1
 
   }   bit
 
HIGHSIDE_CTRL
 
__IM uint32_t RESERVED4 [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RST_TFB: 2
 
   }   bit
 
CNF_RST_TFB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   SUPP_SHORT: 1
 
      __IM uint32_t   SUPP_TMOUT: 1
 
      __IM uint32_t   PMU_1V5_OVL: 1
 
      __IM uint32_t   PMU_5V_OVL: 1
 
      __IM uint32_t   SYS_CLK_WDT: 1
 
      __IM uint32_t   SYS_OT: 1
 
      __IM uint32_t   WDT1_SEQ_FAIL: 1
 
      __IM uint32_t   LP_CLKWD: 1
 
      __IM uint32_t   PMU_OT_FAIL: 1
 
   }   bit
 
WFS
 
__IM uint32_t RESERVED5 [14]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNF_LIN_FT: 1
 
      __IOM uint32_t   CNF_MON_FT: 1
 
      __IOM uint32_t   CNF_GPIO_FT: 2
 
   }   bit
 
CNF_WAKE_FILTER
 
__IM uint32_t RESERVED6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNF_FILT: 2
 
   }   bit
 
PORCFG
 
__IM uint32_t RESERVED7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI_0: 1
 
      __IOM uint32_t   RI_1: 1
 
      __IOM uint32_t   RI_2: 1
 
      __IOM uint32_t   RI_3: 1
 
      __IOM uint32_t   RI_4: 1
 
      __IOM uint32_t   RI_5: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   FA_0: 1
 
      __IOM uint32_t   FA_1: 1
 
      __IOM uint32_t   FA_2: 1
 
      __IOM uint32_t   FA_3: 1
 
      __IOM uint32_t   FA_4: 1
 
      __IOM uint32_t   FA_5: 1
 
      __IOM uint32_t   CYC_0: 1
 
      __IOM uint32_t   CYC_1: 1
 
      __IOM uint32_t   CYC_2: 1
 
      __IOM uint32_t   CYC_3: 1
 
      __IOM uint32_t   CYC_4: 1
 
      __IOM uint32_t   CYC_5: 1
 
   }   bit
 
WAKE_CNF_GPIO0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DATA0: 8
 
      __IOM uint32_t   DATA1: 8
 
      __IOM uint32_t   DATA2: 8
 
      __IOM uint32_t   DATA3: 8
 
   }   bit
 
GPUDATA0to3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DATA4: 8
 
      __IOM uint32_t   DATA5: 8
 
      __IOM uint32_t   DATA6: 8
 
      __IOM uint32_t   DATA7: 8
 
   }   bit
 
GPUDATA4to7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DATA8: 8
 
      __IOM uint32_t   DATA9: 8
 
      __IOM uint32_t   DATA10: 8
 
      __IOM uint32_t   DATA11: 8
 
   }   bit
 
GPUDATA8to11
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RI_0: 1
 
      __IOM uint32_t   RI_1: 1
 
      __IOM uint32_t   RI_2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   RI_4: 1
 
      __IOM uint32_t   FA_0: 1
 
      __IOM uint32_t   FA_1: 1
 
      __IOM uint32_t   FA_2: 1
 
      __IOM uint32_t   FA_4: 1
 
      __IOM uint32_t   CYC_0: 1
 
      __IOM uint32_t   CYC_1: 1
 
      __IOM uint32_t   CYC_2: 1
 
      __IOM uint32_t   CYC_4: 1
 
   }   bit
 
WAKE_CNF_GPIO1
 

Field Documentation

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◆ CNF_FILT

__IOM uint32_t CNF_FILT

[1..0] Configuration for reset filter

◆ CNF_GPIO_FT

__IOM uint32_t CNF_GPIO_FT

[3..2] Wake-up Filter time for General Purpose IO

◆ CNF_LIN_FT

__IOM uint32_t CNF_LIN_FT

[0..0] Wake-up Filter time for LIN WAKE

◆ CNF_MON_FT

__IOM uint32_t CNF_MON_FT

[1..1] Wake-up Filter time for Monitoring Inputs

◆ CNF_OFF

__IOM uint32_t CNF_OFF

[7..6] CNF_OFF Function

◆ CNF_ON

__IOM uint32_t CNF_ON

[5..4] CNF_ON Function

◆ 

union { ... } CNF_RST_TFB

◆ 

union { ... } CNF_WAKE_FILTER

◆ CYC_0

__IOM uint32_t CYC_0

[16..16] GPIO0_0 input for cycle sense enable

[16..16] GPIO1_0 input for cycle sense enable

◆ CYC_1

__IOM uint32_t CYC_1

[17..17] GPIO0_1 input for cycle sense enable

[17..17] GPIO1_1 input for cycle sense enable

◆ CYC_2

__IOM uint32_t CYC_2

[18..18] GPIO0_2 input for cycle sense enable

[18..18] GPIO1_2 input for cycle sense enable

◆ CYC_3

__IOM uint32_t CYC_3

[19..19] GPIO0_3 input for cycle sense enable

◆ CYC_4

__IOM uint32_t CYC_4

[20..20] GPIO0_4 input for cycle sense enable

[20..20] GPIO1_4 input for cycle sense enable

◆ CYC_5

__IOM uint32_t CYC_5

[21..21] GPIO0_5 input for cycle sense enable

◆ CYC_SENSE_E01

__IOM uint32_t CYC_SENSE_E01

[13..12] Exponent

◆ CYC_SENSE_EN

__IOM uint32_t CYC_SENSE_EN

[3..3] Enabling Cyclic Sense

◆ CYC_SENSE_M03

__IOM uint32_t CYC_SENSE_M03

[11..8] Mantissa

◆ CYC_SENSE_S_DEL

__IOM uint32_t CYC_SENSE_S_DEL

[26..24] Sample Delay in Cyclic Sense

◆ CYC_WAKE

__IM uint32_t CYC_WAKE

[4..4] Wake-up caused by Cyclic Wake

◆ CYC_WAKE_E01

__IOM uint32_t CYC_WAKE_E01

[21..20] Exponent

◆ CYC_WAKE_EN

__IOM uint32_t CYC_WAKE_EN

[2..2] Enabling Cyclic Wake

◆ CYC_WAKE_M03

__IOM uint32_t CYC_WAKE_M03

[19..16] Mantissa

◆ DATA0

__IOM uint32_t DATA0

[7..0] DATA0 Storage Byte

◆ DATA1

__IOM uint32_t DATA1

[15..8] DATA1 Storage Byte

◆ DATA10

__IOM uint32_t DATA10

[23..16] DATA10 Storage Byte

◆ DATA11

__IOM uint32_t DATA11

[31..24] DATA11 Storage Byte

◆ DATA2

__IOM uint32_t DATA2

[23..16] DATA2 Storage Byte

◆ DATA3

__IOM uint32_t DATA3

[31..24] DATA3 Storage Byte

◆ DATA4

__IOM uint32_t DATA4

[7..0] DATA4 Storage Byte

◆ DATA5

__IOM uint32_t DATA5

[15..8] DATA5 Storage Byte

◆ DATA6

__IOM uint32_t DATA6

[23..16] DATA6 Storage Byte

◆ DATA7

__IOM uint32_t DATA7

[31..24] DATA7 Storage Byte

◆ DATA8

__IOM uint32_t DATA8

[7..0] DATA8 Storage Byte

◆ DATA9

__IOM uint32_t DATA9

[15..8] DATA9 Storage Byte

◆ 

union { ... } DRV_CTRL

◆ EN_0V9_N

__IOM uint32_t EN_0V9_N

[1..1] Enables the reduction of the VDDC regulator output to 0.9 V during Stop-Mode

◆ FA_0

[8..8] Port 0_0 Wake-up on Falling Edge enable

[8..8] Port 1_0 Wake-up on Falling Edge enable

◆ FA_1

[9..9] Port 0_1 Wake-up on Falling Edge enable

[9..9] Port 1_1 Wake-up on Falling Edge enable

◆ FA_2

[10..10] Port 0_2 Wake-up on Falling Edge enable

[10..10] Port 1_2 Wake-up on Falling Edge enable

◆ FA_3

[11..11] Port 0_3 Wake-up on Falling Edge enable

◆ FA_4

[12..12] Port 0_4 Wake-up on Falling Edge enable

[12..12] Port 1_4 Wake-up on Falling Edge enable

◆ FA_5

[13..13] Port 0_5 Wake-up on Falling Edge enable

◆ FAIL

__IM uint32_t FAIL

[5..5] Wake-up after any Fail, which is a logical OR combination of PMU_OT, VDDEXT_OT, VDDEXT_UV

◆ GL1_CYC_ON

__IOM uint32_t GL1_CYC_ON

[0..0] GL1 Cyclic On

◆ GL1_HOLD_ON

__IOM uint32_t GL1_HOLD_ON

[1..1] GL1 Hold Mode On

◆ GL2_CYC_ON

__IOM uint32_t GL2_CYC_ON

[2..2] GL2 Cyclic On

◆ GL2_HOLD_ON

__IOM uint32_t GL2_HOLD_ON

[3..3] GL2 Hold Mode On

◆ GPIO0

__IM uint32_t GPIO0

[2..2] Wake-up via GPIO0 which is a logical OR combination of all Wake_STS_GPIO0 bits

◆ GPIO0_STS_0

__IM uint32_t GPIO0_STS_0

[0..0] Status of GPIO0_0

◆ GPIO0_STS_1

__IM uint32_t GPIO0_STS_1

[1..1] Status of GPIO0_1

◆ GPIO0_STS_2

__IM uint32_t GPIO0_STS_2

[2..2] Status of GPIO0_2

◆ GPIO0_STS_3

__IM uint32_t GPIO0_STS_3

[3..3] Status of GPIO0_3

◆ GPIO0_STS_4

__IM uint32_t GPIO0_STS_4

[4..4] Status of GPIO0_4

◆ GPIO0_STS_5

__IM uint32_t GPIO0_STS_5

[5..5] Status of GPIO0_5

◆ GPIO1

__IM uint32_t GPIO1

[3..3] Wake-up via GPIO1 which is a logical OR combination of all Wake_STS_GPIO1 bits

◆ GPIO1_STS_0

__IM uint32_t GPIO1_STS_0

[8..8] Wake GPIO1_0

◆ GPIO1_STS_1

__IM uint32_t GPIO1_STS_1

[9..9] Wake GPIO1_1

◆ GPIO1_STS_2

__IM uint32_t GPIO1_STS_2

[10..10] Wake GPIO1_2

◆ GPIO1_STS_4

__IM uint32_t GPIO1_STS_4

[12..12] Wake GPIO1_4

◆ GPIO2

__IM uint32_t GPIO2

[6..6] Wake-up via GPIO2 which is a logical OR combination of all Wake_STS_GPIO2 bits

◆ 

union { ... } GPIO_WAKE_STATUS

◆ 

union { ... } GPUDATA0to3

◆ 

union { ... } GPUDATA4to7

◆ 

union { ... } GPUDATA8to11

◆ 

union { ... } HIGHSIDE_CTRL

◆ HS1_CYC_EN

__IOM uint32_t HS1_CYC_EN

[2..2] High-Side 1 switch enable for cyclic sense

◆ LIN_WAKE

__IM uint32_t LIN_WAKE

[0..0] Wake-up via LIN- Message

◆ LIN_WAKE_EN [1/2]

__IOM uint32_t LIN_WAKE_EN

[7..7] Lin Wake enable

◆  [2/2]

union { ... } LIN_WAKE_EN

◆ LOCKUP

__IOM uint32_t LOCKUP

[10..10] Lockup-Reset Flag

◆ LP_CLKWD

__IM uint32_t LP_CLKWD

[7..7] LP_CLKWD

◆ MON

[1..1] Wake-up via MON which is a logical OR combination of all Wake_STS_MON bits

◆ MON1_CYC

__IOM uint32_t MON1_CYC

[3..3] MON1 for Cycle Sense Enable

◆ MON1_EN

__IOM uint32_t MON1_EN

[0..0] MON1 Enable

◆ MON1_FALL

__IOM uint32_t MON1_FALL

[1..1] MON1 Wake-up on Falling Edge Enable

◆ MON1_NSLEEP_SPARE

__IOM uint32_t MON1_NSLEEP_SPARE

[6..6] MON1 Sleep Bit

◆ MON1_PD

__IOM uint32_t MON1_PD

[4..4] Pull-Down Current Source for MON1 Input Enable

◆ MON1_PU

__IOM uint32_t MON1_PU

[5..5] Pull-Up Current Source for MON1 Input Enable

◆ MON1_RISE

__IOM uint32_t MON1_RISE

[2..2] MON1 Wake-up on Rising Edge Enable

◆ MON1_STS

__IM uint32_t MON1_STS

[7..7] MON1 Status Input

◆ MON1_WAKE_STS

__IM uint32_t MON1_WAKE_STS

[8..8] Status of MON1

◆ MON2_CYC

__IOM uint32_t MON2_CYC

[11..11] MON2 for Cycle Sense Enable

◆ MON2_EN

__IOM uint32_t MON2_EN

[8..8] MON2 Enable

◆ MON2_FALL

__IOM uint32_t MON2_FALL

[9..9] MON2 Wake-up on Falling Edge Enable

◆ MON2_NSLEEP_SPARE

__IOM uint32_t MON2_NSLEEP_SPARE

[14..14] MON2 Sleep Bit

◆ MON2_PD

__IOM uint32_t MON2_PD

[12..12] Pull-Down Current Source for MON2 Input Enable

◆ MON2_PU

__IOM uint32_t MON2_PU

[13..13] Pull-Up Current Source for MON2 Input Enable

◆ MON2_RISE

__IOM uint32_t MON2_RISE

[10..10] MON2 Wake-up on Rising Edge Enable

◆ MON2_STS

__IM uint32_t MON2_STS

[15..15] MON2 Status Input

◆ MON2_WAKE_STS

__IM uint32_t MON2_WAKE_STS

[9..9] Status of MON2

◆ MON3_CYC

__IOM uint32_t MON3_CYC

[19..19] MON3 for Cycle Sense Enable

◆ MON3_EN

__IOM uint32_t MON3_EN

[16..16] MON3 Enable

◆ MON3_FALL

__IOM uint32_t MON3_FALL

[17..17] MON3 Wake-up on Falling Edge Enable

◆ MON3_NSLEEP_SPARE

__IOM uint32_t MON3_NSLEEP_SPARE

[22..22] MON3 Sleep Bit

◆ MON3_PD

__IOM uint32_t MON3_PD

[20..20] Pull-Down Current Source for MON3 Input Enable

◆ MON3_PU

__IOM uint32_t MON3_PU

[21..21] Pull-Up Current Source for MON3 Input Enable

◆ MON3_RISE

__IOM uint32_t MON3_RISE

[18..18] MON3 Wake-up on Rising Edge Enable

◆ MON3_STS

__IM uint32_t MON3_STS

[23..23] MON3 Status Input

◆ MON3_WAKE_STS

__IM uint32_t MON3_WAKE_STS

[10..10] Status of MON3

◆ MON4_CYC

__IOM uint32_t MON4_CYC

[27..27] MON4 for Cycle Sense Enable

◆ MON4_EN

__IOM uint32_t MON4_EN

[24..24] MON4 Enable

◆ MON4_FALL

__IOM uint32_t MON4_FALL

[25..25] MON4 Wake-up on Falling Edge Enable

◆ MON4_NSLEEP_SPARE

__IOM uint32_t MON4_NSLEEP_SPARE

[30..30] MON4 Sleep Bit

◆ MON4_PD

__IOM uint32_t MON4_PD

[28..28] Pull-Down Current Source for MON4 Input Enable

◆ MON4_PU

__IOM uint32_t MON4_PU

[29..29] Pull-Up Current Source for MON4 Input Enable

◆ MON4_RISE

__IOM uint32_t MON4_RISE

[26..26] MON4 Wake-up on Rising Edge Enable

◆ MON4_STS

__IM uint32_t MON4_STS

[31..31] MON4 Status Input

◆ MON4_WAKE_STS

__IM uint32_t MON4_WAKE_STS

[11..11] Status of MON4

◆ MON5_CYC

__IOM uint32_t MON5_CYC

[3..3] MON5 for Cycle Sense Enable

◆ MON5_EN

__IOM uint32_t MON5_EN

[0..0] MON5 Enable

◆ MON5_FALL

__IOM uint32_t MON5_FALL

[1..1] MON5 Wake-up on Falling Edge Enable

◆ MON5_NSLEEP_SPARE

__IOM uint32_t MON5_NSLEEP_SPARE

[6..6] MON5 Sleep Bit

◆ MON5_PD

__IOM uint32_t MON5_PD

[4..4] Pull-Down Current Source for MON5 Input Enable

◆ MON5_PU

__IOM uint32_t MON5_PU

[5..5] Pull-Up Current Source for MON5 Input Enable

◆ MON5_RISE

__IOM uint32_t MON5_RISE

[2..2] MON5 Wake-up on Rising Edge Enable

◆ MON5_STS

__IM uint32_t MON5_STS

[7..7] MON5 Status Input

◆ MON5_WAKE_STS

__IM uint32_t MON5_WAKE_STS

[12..12] Status of MON5

◆ 

union { ... } MON_CNF1

◆ 

union { ... } MON_CNF2

◆ 

union { ... } OT_CTRL

◆ PMU_1V5_FAIL_EN

__IOM uint32_t PMU_1V5_FAIL_EN

[2..2] Enabling of VDDC status information as interrupt source

◆ PMU_1V5_OVERLOAD

__IM uint32_t PMU_1V5_OVERLOAD

[1..1] Overload at VDDC regulator

◆ PMU_1V5_OVERLOAD_SC

__OM uint32_t PMU_1V5_OVERLOAD_SC

[9..9] Overload at VDDC regulator Status clear

◆ PMU_1V5_OVERVOLT

__IM uint32_t PMU_1V5_OVERVOLT

[0..0] Overvoltage at VDDC regulator

◆ PMU_1V5_OVERVOLT_SC

__OM uint32_t PMU_1V5_OVERVOLT_SC

[8..8] Overvoltage at VDDC regulator Status clear

◆ PMU_1V5_OVL

__IM uint32_t PMU_1V5_OVL

[2..2] VDDC Overload Flag

◆ PMU_5V_FAIL_EN

__IOM uint32_t PMU_5V_FAIL_EN

[6..6] Enabling of VDDP status information as interrupt source

◆ PMU_5V_OVERLOAD

__IM uint32_t PMU_5V_OVERLOAD

[5..5] Overload at VDDP regulator

◆ PMU_5V_OVERLOAD_SC

__OM uint32_t PMU_5V_OVERLOAD_SC

[13..13] Overload at VDDP regulator Status clear

◆ PMU_5V_OVERVOLT

__IM uint32_t PMU_5V_OVERVOLT

[4..4] Overvoltage at VDDP regulator

◆ PMU_5V_OVERVOLT_SC

__OM uint32_t PMU_5V_OVERVOLT_SC

[12..12] Overvoltage at VDDP regulator Status clear

◆ PMU_5V_OVL

__IM uint32_t PMU_5V_OVL

[3..3] VDDP Overload Flag

◆ PMU_ClkWDT

__IOM uint32_t PMU_ClkWDT

[4..4] Clock Watchdog (CLKWDT) Reset Flag

◆ PMU_ExtWDT

__IOM uint32_t PMU_ExtWDT

[5..5] External Watchdog (WDT1) Reset Flag

◆ PMU_IntWDT

__IOM uint32_t PMU_IntWDT

[8..8] Internal Watchdog Reset Flag

◆ PMU_LPR

__IOM uint32_t PMU_LPR

[3..3] Low Priority Resets (see PMU_RST_STS2)

◆ PMU_OT

__IM uint32_t PMU_OT

[16..16] Wake PMU Overtemperature

◆ PMU_OT_EN

__IOM uint32_t PMU_OT_EN

[7..7] PMU Overtemperature Detection Enable

◆ PMU_OT_FAIL

__IM uint32_t PMU_OT_FAIL

[8..8] PMU Overtemperature Indication Flag

◆ PMU_OT_INT_EN

__IOM uint32_t PMU_OT_INT_EN

[5..5] PMU Overtemperature Interrupt Enable

◆ PMU_OT_TH_CNF

__IOM uint32_t PMU_OT_TH_CNF

[3..0] PMU Overtemperature threshold

◆ PMU_OT_WAKE_EN

__IOM uint32_t PMU_OT_WAKE_EN

[6..6] PMU Wake On Overtemperature Enable

◆ PMU_OVERTEMP

__IM uint32_t PMU_OVERTEMP

[3..3] PMU Overtemperature

◆ PMU_OVERTEMP_SC

__OM uint32_t PMU_OVERTEMP_SC

[11..11] Overtemperature Status clear

◆ PMU_PIN

__IOM uint32_t PMU_PIN

[6..6] PIN-Reset Flag

◆ PMU_SleepEX

__IOM uint32_t PMU_SleepEX

[2..2] Flag which indicates a reset caused by Sleep-Exit

◆ PMU_SOFT

__IOM uint32_t PMU_SOFT

[9..9] Soft-Reset Flag

◆ PMU_VS_POR

__IOM uint32_t PMU_VS_POR

[7..7] Power-On Reset Flag

◆ PMU_WAKE

__IOM uint32_t PMU_WAKE

[1..1] Flag which indicates a reset caused by Stop-Exit

◆ 

union { ... } PORCFG

◆ reg

(@ 0x00000000) Main wake status register

(@ 0x00000004) GPIO Port wake status register

(@ 0x00000008) Voltage Reg Status Register

(@ 0x0000000C) VDDEXT Control

(@ 0x00000010) Reset Status Register

(@ 0x00000020) PMU Sleep Behavior Register

(@ 0x00000024) PMU Bridge Driver Control

(@ 0x00000034) Settings Monitor

(@ 0x00000038) Settings Monitor

(@ 0x00000050) LIN Wake Enable

(@ 0x00000054) Overtemperature Control Register

(@ 0x0000005C) Highside Control Register

(@ 0x0000006C) Reset Blind Time Register

(@ 0x00000070) WFS System Fail Register

(@ 0x000000AC) PMU Wake-up Timing Register

(@ 0x000000B4) POR Reset Configuration Register

(@ 0x000000BC) Wake Configuration GPIO Port 0 Register

(@ 0x000000C0) General Purpose User DATA0to3

(@ 0x000000C4) General Purpose User DATA4to7

(@ 0x000000C8) General Purpose User DATA8to11

(@ 0x000000CC) Wake Configuration GPIO Port 1 Register

◆ RESERVED

__IM uint32_t RESERVED[3]

◆ RESERVED1

__IM uint32_t RESERVED1[3]

◆ RESERVED2

__IM uint32_t RESERVED2[5]

◆ RESERVED3

__IM uint32_t RESERVED3

◆ RESERVED4

__IM uint32_t RESERVED4[3]

◆ RESERVED5

__IM uint32_t RESERVED5[14]

◆ RESERVED6

__IM uint32_t RESERVED6

◆ RESERVED7

__IM uint32_t RESERVED7

◆ 

union { ... } RESET_STS

◆ RI_0

[0..0] Port 0_0 Wake-up on Rising Edge enable

[0..0] Port 1_0 Wake-up on Rising Edge enable

◆ RI_1

[1..1] Port 0_1 Wake-up on Rising Edge enable

[1..1] Port 1_1 Wake-up on Rising Edge enable

◆ RI_2

[2..2] Port 0_2 Wake-up on Rising Edge enable

[2..2] Port 1_2 Wake-up on Rising Edge enable

◆ RI_3

[3..3] Port 0_3 Wake-up on Rising Edge enable

◆ RI_4

[4..4] Port 0_4 Wake-up on Rising Edge enable

[4..4] Port 1_4 Wake-up on Rising Edge enable

◆ RI_5

[5..5] Port 0_5 Wake-up on Rising Edge enable

◆ RST_TFB

__IOM uint32_t RST_TFB

[1..0] Reset Pin Blind Time Selection Bits

◆ 

union { ... } SLEEP

◆ SPARE

__IOM uint32_t SPARE

[10..10] Spare

◆ SUPP_SHORT

__IM uint32_t SUPP_SHORT

[0..0] Supply Short

◆ SUPP_TMOUT

__IM uint32_t SUPP_TMOUT

[1..1] Supply Time Out

◆ 

union { ... } SUPPLY_STS

◆ SYS_CLK_WDT

__IM uint32_t SYS_CLK_WDT

[4..4] System Clock (fsys)Watchdog Fail

◆ SYS_FAIL

__IOM uint32_t SYS_FAIL

[0..0] Flag which indicates a reset caused by a System Fail reported in the corresponding Fail Register

◆ SYS_OT

__IM uint32_t SYS_OT

[5..5] System Overtemperature Indication Flag

◆ uint32_t

__IM uint32_t

◆ 

union { ... } VDDEXT_CTRL

◆ VDDEXT_CYC_EN

__IOM uint32_t VDDEXT_CYC_EN

[1..1] VDDEXT Supply for Cyclic Sense Enable

◆ VDDEXT_ENABLE

__IOM uint32_t VDDEXT_ENABLE

[0..0] VDDEXT Supply Enable

◆ VDDEXT_FAIL_EN

__IOM uint32_t VDDEXT_FAIL_EN

[2..2] Enabling of VDDEXT Supply status information as interrupt source

◆ VDDEXT_OT

__IM uint32_t VDDEXT_OT

[17..17] Wake VDDEXT Overtemperature

[6..6] VDDEXT Supply Overtemperature

◆ VDDEXT_OT_IS

__IM uint32_t VDDEXT_OT_IS

[3..3] VDDEXT Supply OverTemperature Interrupt Status

◆ VDDEXT_OT_ISC

__OM uint32_t VDDEXT_OT_ISC

[11..11] VDDEXT Supply Overtemperature Interrupt Status clear

◆ VDDEXT_OT_SC

__OM uint32_t VDDEXT_OT_SC

[13..13] VDDEXT Supply Overtemperature Status clear

◆ VDDEXT_OT_STS

__IM uint32_t VDDEXT_OT_STS

[5..5] VDDEXT Supply Overtemperature Status

◆ VDDEXT_STABLE

__IM uint32_t VDDEXT_STABLE

[7..7] VDDEXT Supply Stable

◆ VDDEXT_UV

__IM uint32_t VDDEXT_UV

[18..18] Wake VDDEXT Undervoltage

◆ VDDEXT_UV_IS

__IM uint32_t VDDEXT_UV_IS

[4..4] VDDEXT Supply Undervoltage Interrupt Status

◆ VDDEXT_UV_ISC

__OM uint32_t VDDEXT_UV_ISC

[12..12] VDDEXT Supply Undervoltage Interrupt Status clear

◆ 

union { ... } WAKE_CNF_GPIO0

◆ 

union { ... } WAKE_CNF_GPIO1

◆ 

union { ... } WAKE_STATUS

< (@ 0x50004000) PMU Structure

◆ WAKE_W_RST

__IOM uint32_t WAKE_W_RST

[0..0] Wake-up with reset execution

◆ WDT1_SEQ_FAIL

__IM uint32_t WDT1_SEQ_FAIL

[6..6] External Watchdog (WDT1) Sequential Fail

◆ 

union { ... } WFS

The documentation for this struct was generated from the following file: