Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields
BDRV_Type Struct Reference

Detailed Description

BDRV (BDRV)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_EN: 1
 
      __IOM uint32_t   LS1_PWM: 1
 
      __IOM uint32_t   LS1_ON: 1
 
      __IM   uint32_t: 2
 
      __IM uint32_t   LS1_SUPERR_STS: 1
 
      __IOM uint32_t   LS1_OC_DIS: 1
 
      __IOM uint32_t   LS2_EN: 1
 
      __IOM uint32_t   LS2_PWM: 1
 
      __IOM uint32_t   LS2_ON: 1
 
      __IM uint32_t   LS2_SUPERR_STS: 1
 
      __IOM uint32_t   LS2_OC_DIS: 1
 
      __IOM uint32_t   HS1_EN: 1
 
      __IOM uint32_t   HS1_PWM: 1
 
      __IOM uint32_t   HS1_ON: 1
 
      __IOM uint32_t   HS1_DCS_EN: 1
 
      __IM uint32_t   HS1_SUPERR_STS: 1
 
      __IOM uint32_t   HS1_OC_DIS: 1
 
      __IOM uint32_t   HS2_EN: 1
 
      __IOM uint32_t   HS2_PWM: 1
 
      __IOM uint32_t   HS2_ON: 1
 
      __IOM uint32_t   HS2_DCS_EN: 1
 
      __IM uint32_t   HS2_SUPERR_STS: 1
 
      __IOM uint32_t   HS2_OC_DIS: 1
 
   }   bit
 
CTRL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1ONSEQCNF: 1
 
      __IOM uint32_t   HB2ONSEQCNF: 1
 
      __IOM uint32_t   HB1OFFSEQCNF: 1
 
      __IOM uint32_t   HB2OFFSEQCNF: 1
 
      __IM   uint32_t: 12
 
      __IM uint32_t   DLY_DIAG_TIM: 10
 
      __OM uint32_t   DLY_DIAG_SCLR: 1
 
      __IM uint32_t   DLY_DIAG_STS: 1
 
      __IOM uint32_t   DLY_DIAG_CHSEL: 3
 
      __IOM uint32_t   DLY_DIAG_DIRSEL: 1
 
   }   bit
 
CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 16
 
      __IOM uint32_t   DSMONVTH: 3
 
      __IOM uint32_t   DRV_CCP_TIMSEL: 2
 
      __IOM uint32_t   DRV_CCP_TMUL: 2
 
      __IOM uint32_t   DRV_CCP_DIS: 1
 
   }   bit
 
CTRL3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS1_SRC_SEL: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   LS2_SRC_SEL: 2
 
      __IOM uint32_t   HS1_SRC_SEL: 2
 
      __IOM uint32_t   HS2_SRC_SEL: 2
 
   }   bit
 
PWMSRCSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_SEQMAP: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HB2_SEQMAP: 1
 
   }   bit
 
SEQMAP
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LS_HS_BT_TFILT_SEL: 2
 
      __IM   uint32_t: 6
 
      __IOM uint32_t   LSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   LS1DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   LS2DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   LS1DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   LS2DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   HSDRV_DS_TFILT_SEL: 2
 
      __IOM uint32_t   HS1DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   HS2DRV_FDISCHG_DIS: 1
 
      __IOM uint32_t   HS1DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   HS2DRV_OCSDN_DIS: 1
 
      __IOM uint32_t   CPLOW_TFILT_SEL: 2
 
   }   bit
 
TRIM_DRVx
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CP_EN: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   CP_RDY_EN: 1
 
      __IOM uint32_t   DRVx_VCPLO_DIS: 1
 
      __IOM uint32_t   DRVx_VCPLO_SDEN: 1
 
      __IOM uint32_t   DRVx_VCPUP_DIS: 1
 
      __IOM uint32_t   DRVx_VSDLO_DIS: 1
 
      __IOM uint32_t   DRVx_VSDUP_DIS: 1
 
      __IOM uint32_t   CPLOPWRM_EN: 1
 
      __IOM uint32_t   VCP9V_SET: 1
 
      __IOM uint32_t   VTHVCP_TRIM: 2
 
      __IOM uint32_t   VCP14_15V_SEL: 1
 
      __IOM uint32_t   CP_STAGE_SEL: 2
 
   }   bit
 
CP_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DITH_LOWER: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   DITH_UPPER: 5
 
      __IOM uint32_t   F_CP: 2
 
      __IOM uint32_t   CPCLK_EN: 1
 
      __IOM uint32_t   CPCLKDIS_SET: 1
 
   }   bit
 
CP_CLK_CTRL
 
__IM uint32_t RESERVED2 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_ICLMPON: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB2_ICLMPON: 6
 
      __IOM uint32_t   HB1AF_ICLMPON: 6
 
      __IOM uint32_t   HB2AF_ICLMPON: 6
 
   }   bit
 
IGATECLMPONC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_ICLMPOFF: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB2_ICLMPOFF: 6
 
      __IOM uint32_t   HB1AF_ICLMPOFF: 6
 
      __IOM uint32_t   HB2AF_ICLMPOFF: 6
 
   }   bit
 
IGATECLMPOFFC
 
__IM uint32_t RESERVED3 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VCP_OTW_IS: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   VCP_OTSD_IS: 1
 
      __IOM uint32_t   VCP_LOTH1_IS: 1
 
      __IOM uint32_t   VCP_UPTH_IS: 1
 
      __IOM uint32_t   VSD_LOTH_IS: 1
 
      __IOM uint32_t   VSD_UPTH_IS: 1
 
      __IOM uint32_t   VCP_OTW_STS: 1
 
      __IOM uint32_t   VCP_OTSD_STS: 1
 
      __IOM uint32_t   VCP_LOTH1_STS: 1
 
      __IOM uint32_t   VCP_UPTH_STS: 1
 
      __IOM uint32_t   VSD_LOTH_STS: 1
 
      __IOM uint32_t   VSD_UPTH_STS: 1
 
   }   bit
 
CP_IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   VCP_OTW_ISC: 1
 
      __IM   uint32_t: 3
 
      __OM uint32_t   VCP_OTSD_ISC: 1
 
      __OM uint32_t   VCP_LOTH1_ISC: 1
 
      __OM uint32_t   VCP_UPTH_ISC: 1
 
      __OM uint32_t   VSD_LOTH_ISC: 1
 
      __OM uint32_t   VSD_UPTH_ISC: 1
 
      __OM uint32_t   VCP_OTW_SC: 1
 
      __OM uint32_t   VCP_OTSD_SC: 1
 
      __OM uint32_t   VCP_LOTH1_SC: 1
 
      __OM uint32_t   VCP_UPTH_SC: 1
 
      __OM uint32_t   VSD_LOTH_SC: 1
 
      __OM uint32_t   VSD_UPTH_SC: 1
 
   }   bit
 
CP_IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VCP_OTW_IEN: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   VCP_OTSD_IEN: 1
 
      __IOM uint32_t   VCP_LOTH1_IEN: 1
 
      __IOM uint32_t   VCP_UPTH_IEN: 1
 
      __IOM uint32_t   VSD_LOTH_IEN: 1
 
      __IOM uint32_t   VSD_UPTH_IEN: 1
 
   }   bit
 
CP_IRQEN
 
__IM uint32_t RESERVED4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_T1OFF: 8
 
      __IOM uint32_t   HB1_T2OFF: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB1_T3OFF: 6
 
      __IOM uint32_t   HB1_T4OFF: 8
 
   }   bit
 
OFFSEQHB1TC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_I1OFF: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB1_I2OFF: 6
 
      __IOM uint32_t   HB1_I3OFF: 6
 
      __IOM uint32_t   HB1_I4OFF: 6
 
   }   bit
 
OFFSEQHB1IC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_T1ON: 8
 
      __IOM uint32_t   HB1_T2ON: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB1_T3ON: 6
 
      __IOM uint32_t   HB1_T4ON: 8
 
   }   bit
 
ONSEQHB1TC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_I1ON: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB1_I2ON: 6
 
      __IOM uint32_t   HB1_I3ON: 6
 
      __IOM uint32_t   HB1_I4ON: 6
 
   }   bit
 
ONSEQHB1IC
 
__IM uint32_t RESERVED5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1AF_IOFF: 6
 
      __IM   uint32_t: 10
 
      __IOM uint32_t   HB1AF_ION: 6
 
   }   bit
 
SEQAFHB1IC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1AF_TDICLMPOFF: 8
 
      __IOM uint32_t   HB1AF_TDICLMPON: 8
 
   }   bit
 
SEQAFHB1CD
 
__IM uint32_t RESERVED6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2_T1OFF: 8
 
      __IOM uint32_t   HB2_T2OFF: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB2_T3OFF: 6
 
      __IOM uint32_t   HB2_T4OFF: 8
 
   }   bit
 
OFFSEQHB2TC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2_I1OFF: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB2_I2OFF: 6
 
      __IOM uint32_t   HB2_I3OFF: 6
 
      __IOM uint32_t   HB2_I4OFF: 6
 
   }   bit
 
OFFSEQHB2IC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2_T1ON: 8
 
      __IOM uint32_t   HB2_T2ON: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB2_T3ON: 6
 
      __IOM uint32_t   HB2_T4ON: 8
 
   }   bit
 
ONSEQHB2TC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2_I1ON: 6
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB2_I2ON: 6
 
      __IOM uint32_t   HB2_I3ON: 6
 
      __IOM uint32_t   HB2_I4ON: 6
 
   }   bit
 
ONSEQHB2IC
 
__IM uint32_t RESERVED7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2AF_IOFF: 6
 
      __IM   uint32_t: 10
 
      __IOM uint32_t   HB2AF_ION: 6
 
   }   bit
 
SEQAFHB2IC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB2AF_TDICLMPOFF: 8
 
      __IOM uint32_t   HB2AF_TDICLMPON: 8
 
   }   bit
 
SEQAFHB2CD
 
__IM uint32_t RESERVED8
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1ASMONEN: 1
 
      __IOM uint32_t   HB1ASMOFFEN: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   HB1OPTONACT: 1
 
      __IOM uint32_t   HB1OPTOFFACT: 1
 
      __IOM uint32_t   HB1ONHYSTEN: 1
 
      __IOM uint32_t   HB1OFFHYSTEN: 1
 
      __IOM uint32_t   HB2ASMONEN: 1
 
      __IOM uint32_t   HB2ASMOFFEN: 1
 
      __IOM uint32_t   HB2OPTONACT: 1
 
      __IOM uint32_t   HB2OPTOFFACT: 1
 
      __IOM uint32_t   HB2ONHYSTEN: 1
 
      __IOM uint32_t   HB2OFFHYSTEN: 1
 
   }   bit
 
ASEQC
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1T1OFFMAX: 1
 
      __IM uint32_t   HB1I1OFFMAX: 1
 
      __IM uint32_t   HB1T1OFFMIN: 1
 
      __IM uint32_t   HB1I1OFFMIN: 1
 
      __IM uint32_t   HB1T12ONMAX: 1
 
      __IM uint32_t   HB1I1ONMAX: 1
 
      __IM uint32_t   HB1T12ONMIN: 1
 
      __IM uint32_t   HB1I1ONMIN: 1
 
      __IM   uint32_t: 6
 
      __IM uint32_t   HB1OFFMF: 1
 
      __IM uint32_t   HB1ONMF: 1
 
      __IM uint32_t   HB2T1OFFMAX: 1
 
      __IM uint32_t   HB2I1OFFMAX: 1
 
      __IM uint32_t   HB2T1OFFMIN: 1
 
      __IM uint32_t   HB2I1OFFMIN: 1
 
      __IM uint32_t   HB2T12ONMAX: 1
 
      __IM uint32_t   HB2I1ONMAX: 1
 
      __IM uint32_t   HB2T12ONMIN: 1
 
      __IM uint32_t   HB2I1ONMIN: 1
 
      __IM uint32_t   HB2OFFMF: 1
 
      __IM uint32_t   HB2ONMF: 1
 
   }   bit
 
ASEQSTS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T12ONMIN: 8
 
   }   bit
 
ONASEQTMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T1OFFMIN: 8
 
      __IOM uint32_t   HB1T1OFFADDDLY: 4
 
      __IOM uint32_t   HB2T1OFFADDDLY: 4
 
   }   bit
 
OFFASEQTMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1ONMIN: 6
 
   }   bit
 
ASEQIONMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1OFFMIN: 6
 
   }   bit
 
ASEQIOFFMIN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T12ONMAX: 8
 
   }   bit
 
ONASEQTMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T1OFFMAX: 8
 
   }   bit
 
OFFASEQTMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1ONMAX: 6
 
   }   bit
 
ASEQIONMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   I1OFFMAX: 6
 
   }   bit
 
ASEQIOFFMAX
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1_T12ONCNT: 8
 
      __IM uint32_t   HB1_I1ONVAL: 6
 
      __IM   uint32_t: 2
 
      __IM uint32_t   HB1_T3ONCNT: 6
 
      __IM uint32_t   HB1_T3MERR: 1
 
      __IOM uint32_t   HB1_ONVALVF: 1
 
      __OM uint32_t   HB1_ONVALVF_CLR: 1
 
   }   bit
 
HB1ASEQONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB1_T1OFFCNT: 8
 
      __IM uint32_t   HB1_I1OFFVAL: 6
 
      __IM   uint32_t: 2
 
      __IM uint32_t   HB1_T2OFFCNT: 6
 
      __IM uint32_t   HB1_T2MERR: 1
 
      __IOM uint32_t   HB1_OFFVALVF: 1
 
      __OM uint32_t   HB1_OFFVALVF_CLR: 1
 
   }   bit
 
HB1ASEQOFFVAL
 
__IM uint32_t RESERVED9 [4]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB2_T12ONCNT: 8
 
      __IM uint32_t   HB2_I1ONVAL: 6
 
      __IM   uint32_t: 2
 
      __IM uint32_t   HB2_T3ONCNT: 6
 
      __IM uint32_t   HB2_T3MERR: 1
 
      __IOM uint32_t   HB2_ONVALVF: 1
 
      __OM uint32_t   HB2_ONVALVF_CLR: 1
 
   }   bit
 
HB2ASEQONVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   HB2_T1OFFCNT: 8
 
      __IM uint32_t   HB2_I1OFFVAL: 6
 
      __IM   uint32_t: 2
 
      __IM uint32_t   HB2_T2OFFCNT: 6
 
      __IM uint32_t   HB2_T2MERR: 1
 
      __IOM uint32_t   HB2_OFFVALVF: 1
 
      __OM uint32_t   HB2_OFFVALVF_CLR: 1
 
   }   bit
 
HB2ASEQOFFVAL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1T1OFFERRCNT: 2
 
      __IOM uint32_t   HB1T12ONERRCNT: 2
 
      __IOM uint32_t   HB1MFERRCNT: 2
 
      __IM   uint32_t: 10
 
      __IOM uint32_t   HB2T1OFFERRCNT: 2
 
      __IOM uint32_t   HB2T12ONERRCNT: 2
 
      __IOM uint32_t   HB2MFERRCNT: 2
 
   }   bit
 
ASEQERRCNT
 
__IM uint32_t RESERVED10
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 8
 
      __IOM uint32_t   COMPENS_HS: 3
 
      __IOM uint32_t   COMPENS_LS: 3
 
   }   bit
 
DCTRIM_DRVx
 
__IM uint32_t RESERVED11 [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_ASEQ_IS: 1
 
      __IOM uint32_t   HB2_ASEQ_IS: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   LS1_DS_IS: 1
 
      __IOM uint32_t   LS1_DS_STS: 1
 
      __IOM uint32_t   LS1_OC_IS: 1
 
      __IOM uint32_t   LS2_DS_IS: 1
 
      __IOM uint32_t   LS2_DS_STS: 1
 
      __IOM uint32_t   LS2_OC_IS: 1
 
      __IOM uint32_t   HS1_DS_IS: 1
 
      __IOM uint32_t   HS1_DS_STS: 1
 
      __IOM uint32_t   HS1_OC_IS: 1
 
      __IOM uint32_t   HS2_DS_IS: 1
 
      __IOM uint32_t   HS2_DS_STS: 1
 
      __IOM uint32_t   HS2_OC_IS: 1
 
      __IOM uint32_t   SEQ_ERR_IS: 1
 
   }   bit
 
IRQS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   HB1_ASEQ_ISC: 1
 
      __OM uint32_t   HB2_ASEQ_ISC: 1
 
      __IM   uint32_t: 2
 
      __OM uint32_t   LS1_DS_ISC: 1
 
      __OM uint32_t   LS1_DS_SC: 1
 
      __OM uint32_t   LS1_OC_ISC: 1
 
      __OM uint32_t   LS2_DS_ISC: 1
 
      __OM uint32_t   LS2_DS_SC: 1
 
      __OM uint32_t   LS2_OC_ISC: 1
 
      __OM uint32_t   HS1_DS_ISC: 1
 
      __OM uint32_t   HS1_DS_SC: 1
 
      __OM uint32_t   HS1_OC_ISC: 1
 
      __OM uint32_t   HS2_DS_ISC: 1
 
      __OM uint32_t   HS2_DS_SC: 1
 
      __OM uint32_t   HS2_OC_ISC: 1
 
      __OM uint32_t   SEQ_ERR_ISC: 1
 
   }   bit
 
IRQCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   HB1_ASEQ_IEN: 1
 
      __IOM uint32_t   HB2_ASEQ_IEN: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   LS1_DS_IEN: 1
 
      __IOM uint32_t   LS1_OC_IEN: 1
 
      __IOM uint32_t   LS2_DS_IEN: 1
 
      __IOM uint32_t   LS2_OC_IEN: 1
 
      __IOM uint32_t   HS1_DS_IEN: 1
 
      __IOM uint32_t   HS1_OC_IEN: 1
 
      __IOM uint32_t   HS2_DS_IEN: 1
 
      __IOM uint32_t   HS2_OC_IEN: 1
 
      __IOM uint32_t   SEQ_ERR_IEN: 1
 
   }   bit
 
IRQEN
 

Field Documentation

◆ 

union { ... } ASEQC

◆ 

union { ... } ASEQERRCNT

◆ 

union { ... } ASEQIOFFMAX

◆ 

union { ... } ASEQIOFFMIN

◆ 

union { ... } ASEQIONMAX

◆ 

union { ... } ASEQIONMIN

◆ 

union { ... } ASEQSTS

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◆  [43/44]

struct { ... } bit

◆  [44/44]

struct { ... } bit

◆ COMPENS_HS

__IOM uint32_t COMPENS_HS

[10..8] Current Settings for High Side Charge Current Compensation

◆ COMPENS_LS

__IOM uint32_t COMPENS_LS

[18..16] Gain Settings for Low Side Charge Current Compensation

◆ 

union { ... } CP_CLK_CTRL

◆ 

union { ... } CP_CTRL

◆ CP_EN

__IOM uint32_t CP_EN

[0..0] Charge Pump Enable

◆ 

union { ... } CP_IRQCLR

◆ 

union { ... } CP_IRQEN

◆ 

union { ... } CP_IRQS

◆ CP_RDY_EN

__IOM uint32_t CP_RDY_EN

[2..2] Bridge Driver on Charge Pump Ready Enable

◆ CP_STAGE_SEL

__IOM uint32_t CP_STAGE_SEL

[30..29] Charge Pump Output Voltage Trimming

◆ CPCLK_EN

__IOM uint32_t CPCLK_EN

[15..15] Charge Pump Clock Enable

◆ CPCLKDIS_SET

__IOM uint32_t CPCLKDIS_SET

[16..16] Charge Pump Clock Set If Disabled

◆ CPLOPWRM_EN

__IOM uint32_t CPLOPWRM_EN

[24..24] Charge Pump Low Power Mode Enable

◆ CPLOW_TFILT_SEL

__IOM uint32_t CPLOW_TFILT_SEL

[29..28] Filter Time for Charge Pump Voltage Low Diagnosis

◆ 

union { ... } CTRL1

< (@ 0x40034000) BDRV Structure

◆ 

union { ... } CTRL2

◆ 

union { ... } CTRL3

◆ 

union { ... } DCTRIM_DRVx

◆ DITH_LOWER

__IOM uint32_t DITH_LOWER

[4..0] CP_CLK lower frequency boundary during dithering

◆ DITH_UPPER

__IOM uint32_t DITH_UPPER

[12..8] CP_CLK upper frequency boundary during dithering

◆ DLY_DIAG_CHSEL

__IOM uint32_t DLY_DIAG_CHSEL

[30..28] Ext. power diag timer channel select

◆ DLY_DIAG_DIRSEL

__IOM uint32_t DLY_DIAG_DIRSEL

[31..31] Ext. power diag timer on / off select

◆ DLY_DIAG_SCLR

__OM uint32_t DLY_DIAG_SCLR

[26..26] Ext. power diag timer valid flag clear

◆ DLY_DIAG_STS

__IM uint32_t DLY_DIAG_STS

[27..27] Ext. power diag timer valid flag

◆ DLY_DIAG_TIM

__IM uint32_t DLY_DIAG_TIM

[25..16] Ext. power diag timer result register

◆ DRV_CCP_DIS

__IOM uint32_t DRV_CCP_DIS

[30..30] Dynamic cross conduction protection Disable

◆ DRV_CCP_TIMSEL

__IOM uint32_t DRV_CCP_TIMSEL

[25..24] Minimum cross conduction protection time setting

◆ DRV_CCP_TMUL

__IOM uint32_t DRV_CCP_TMUL

[29..28] Multiplier bits for cross conduction time settings in register DRV_CCP_TIMSEL

◆ DRVx_VCPLO_DIS

__IOM uint32_t DRVx_VCPLO_DIS

[16..16] Driver On Charge Pump Low Voltage Disable

◆ DRVx_VCPLO_SDEN

__IOM uint32_t DRVx_VCPLO_SDEN

[17..17] Driver Charge Pump Low Voltage Shut-Down

◆ DRVx_VCPUP_DIS

__IOM uint32_t DRVx_VCPUP_DIS

[18..18] Driver On Charge Pump Upper Voltage Disable

◆ DRVx_VSDLO_DIS

__IOM uint32_t DRVx_VSDLO_DIS

[20..20] Driver On VSD Lower Voltage Disable

◆ DRVx_VSDUP_DIS

__IOM uint32_t DRVx_VSDUP_DIS

[22..22] Driver On VSD Upper Voltage Disable

◆ DSMONVTH

__IOM uint32_t DSMONVTH

[18..16] Voltage Threshold for Drain-Source Monitoring of external FETs

◆ F_CP

[14..13] MSB of CP_CLK divider

◆ HB1_ASEQ_IEN

__IOM uint32_t HB1_ASEQ_IEN

[0..0] Half Bridge 1 Adaptive Sequencer Interrupt Enable

◆ HB1_ASEQ_IS

__IOM uint32_t HB1_ASEQ_IS

[0..0] Half Bridge 1 Adaptive Sequencer Interrupt Status

◆ HB1_ASEQ_ISC

__OM uint32_t HB1_ASEQ_ISC

[0..0] Half Bridge 1 Adaptive Sequencer Interrupt Status Clear

◆ HB1_I1OFF

__IOM uint32_t HB1_I1OFF

[5..0] Half Bridge 1-slew rate sequencer off-phase 1 current setting

◆ HB1_I1OFFVAL

__IM uint32_t HB1_I1OFFVAL

[13..8] Half Bridge 1-slew rate sequencer off-phase 1 current setting

◆ HB1_I1ON

__IOM uint32_t HB1_I1ON

[5..0] Half Bridge 1-slew rate sequencer on-phase 1 current setting

◆ HB1_I1ONVAL

__IM uint32_t HB1_I1ONVAL

[13..8] Half Bridge 1-slew rate sequencer on-phase 1 current setting

◆ HB1_I2OFF

__IOM uint32_t HB1_I2OFF

[13..8] Half Bridge 1-slew rate sequencer-off phase 2 current setting

◆ HB1_I2ON

__IOM uint32_t HB1_I2ON

[13..8] Half Bridge 1-slew rate sequencer on-phase 2 current setting

◆ HB1_I3OFF

__IOM uint32_t HB1_I3OFF

[21..16] Half Bridge 1-slew rate sequencer off-phase 3 current setting

◆ HB1_I3ON

__IOM uint32_t HB1_I3ON

[21..16] Half Bridge 1-slew rate sequencer on-phase 3 current setting

◆ HB1_I4OFF

__IOM uint32_t HB1_I4OFF

[29..24] Half Bridge 1-slew rate sequencer off-phase 4 current setting

◆ HB1_I4ON

__IOM uint32_t HB1_I4ON

[29..24] Half Bridge 1-slew rate sequencer on-phase 4 current setting

◆ HB1_ICLMPOFF

__IOM uint32_t HB1_ICLMPOFF

[5..0] Half Bridge 1-current clamping value for OFF state

◆ HB1_ICLMPON

__IOM uint32_t HB1_ICLMPON

[5..0] Half Bridge 1-current clamping value for ON state

◆ HB1_OFFVALVF

__IOM uint32_t HB1_OFFVALVF

[30..30] Half Bridge 1-Turn off slew rate values - Valid Flag.

◆ HB1_OFFVALVF_CLR

__OM uint32_t HB1_OFFVALVF_CLR

[31..31] Half Bridge 1-Turn off slew rate values Valid Flag

  • Clear.

◆ HB1_ONVALVF

__IOM uint32_t HB1_ONVALVF

[30..30] Half Bridge 1-Turn on slew rate values - Valid Flag.

◆ HB1_ONVALVF_CLR

__OM uint32_t HB1_ONVALVF_CLR

[31..31] Half Bridge 1-Turn on slew rate values Valid Flag - Clear.

◆ HB1_SEQMAP

__IOM uint32_t HB1_SEQMAP

[0..0] Half Bridge 1 Sequencer Mapping

◆ HB1_T12ONCNT

__IM uint32_t HB1_T12ONCNT

[7..0] Half Bridge 1-Turn on slew rate-time value measured from beginning of phase 1 to end of phase 2.

◆ HB1_T1OFF

__IOM uint32_t HB1_T1OFF

[7..0] Half Bridge 1-slew rate sequencer off-phase 1 time setting

◆ HB1_T1OFFCNT

__IM uint32_t HB1_T1OFFCNT

[7..0] Half Bridge 1-Turn off slew rate-time value measured from beginning of phase 1 to end of phase 1.

◆ HB1_T1ON

__IOM uint32_t HB1_T1ON

[7..0] Half Bridge 1-slew rate sequencer on-phase 1 time setting

◆ HB1_T2MERR

__IM uint32_t HB1_T2MERR

[22..22] Half Bridge 1-T2 Measurement Error.

◆ HB1_T2OFF

__IOM uint32_t HB1_T2OFF

[13..8] Half Bridge 1-slew rate sequencer off-phase 2 time setting

◆ HB1_T2OFFCNT

__IM uint32_t HB1_T2OFFCNT

[21..16] Half Bridge 1-Turn off slew rate-time value measured from beginning of phase 2 to end of phase 2.

◆ HB1_T2ON

__IOM uint32_t HB1_T2ON

[13..8] Half Bridge 1-slew rate sequencer on-phase 2 time setting

◆ HB1_T3MERR

__IM uint32_t HB1_T3MERR

[22..22] Half Bridge 1-T3 Measurement Error.

◆ HB1_T3OFF

__IOM uint32_t HB1_T3OFF

[21..16] Half Bridge 1-slew rate sequencer off-phase 3 time setting

◆ HB1_T3ON

__IOM uint32_t HB1_T3ON

[21..16] Half Bridge 1-slew rate sequencer on-phase 3 time setting

◆ HB1_T3ONCNT

__IM uint32_t HB1_T3ONCNT

[21..16] Half Bridge 1-Turn on slew rate-time value measured from beginning of phase 3 to end of phase 3.

◆ HB1_T4OFF

__IOM uint32_t HB1_T4OFF

[31..24] Half Bridge 1-slew rate sequencer off-phase 4 time setting

◆ HB1_T4ON

__IOM uint32_t HB1_T4ON

[31..24] Half Bridge 1-slew rate sequencer on-phase 4 time setting

◆ HB1AF_ICLMPOFF

__IOM uint32_t HB1AF_ICLMPOFF

[21..16] Half Bridge 1-active freewheeling-current clamping value for OFF state

◆ HB1AF_ICLMPON

__IOM uint32_t HB1AF_ICLMPON

[21..16] Half Bridge 1-active freewheeling-current clamping value for ON state

◆ HB1AF_IOFF

__IOM uint32_t HB1AF_IOFF

[5..0] Half Bridge 1-active freewheeling-slew rate sequencer off-phase current setting

◆ HB1AF_ION

__IOM uint32_t HB1AF_ION

[21..16] Half Bridge 1-active freewheeling-slew rate sequencer on-phase current setting

◆ HB1AF_TDICLMPOFF

__IOM uint32_t HB1AF_TDICLMPOFF

[7..0] Clamping current delay during active freewheeling for switch off

◆ HB1AF_TDICLMPON

__IOM uint32_t HB1AF_TDICLMPON

[15..8] Clamping current delay during active freewheeling for switch on

◆ 

union { ... } HB1ASEQOFFVAL

◆ 

union { ... } HB1ASEQONVAL

◆ HB1ASMOFFEN

__IOM uint32_t HB1ASMOFFEN

[1..1] Half Bridge 1 Adaptive Sequencer Mode for Switch Off Enable

◆ HB1ASMONEN

__IOM uint32_t HB1ASMONEN

[0..0] Half Bridge 1 Adaptive Sequencer Mode for Switch On Enable

◆ HB1I1OFFMAX

__IM uint32_t HB1I1OFFMAX

[1..1] Half Bridge 1-I1 Off Max Value reached

◆ HB1I1OFFMIN

__IM uint32_t HB1I1OFFMIN

[3..3] Half Bridge 1-I1 Off Min Value reached

◆ HB1I1ONMAX

__IM uint32_t HB1I1ONMAX

[5..5] Half Bridge 1-I1 On Max Value reached

◆ HB1I1ONMIN

__IM uint32_t HB1I1ONMIN

[7..7] Half Bridge 1-I1 On Min Value reached

◆ HB1MFERRCNT

__IOM uint32_t HB1MFERRCNT

[5..4] Half Bridge 1-Measurement Failure Error Counter Setting

◆ HB1OFFHYSTEN

__IOM uint32_t HB1OFFHYSTEN

[7..7] Half Bridge 1 Optimizer Hysteresis for Switch Off Enable Bit

◆ HB1OFFMF

__IM uint32_t HB1OFFMF

[14..14] Half Bridge 1-Off Adaptive Mode Measurement Failure

◆ HB1OFFSEQCNF

__IOM uint32_t HB1OFFSEQCNF

[2..2] Half Bridge 1 Off Sequencer Configuration

◆ HB1ONHYSTEN

__IOM uint32_t HB1ONHYSTEN

[6..6] Half Bridge 1 Optimizer Hysteresis for Switch On Enable Bit

◆ HB1ONMF

__IM uint32_t HB1ONMF

[15..15] Half Bridge 1-On Adaptive Mode Measurement Failure

◆ HB1ONSEQCNF

__IOM uint32_t HB1ONSEQCNF

[0..0] Half Bridge 1 On Sequencer Configuration

◆ HB1OPTOFFACT

__IOM uint32_t HB1OPTOFFACT

[5..5] Half Bridge 1 Optimizer for Switch Off Active Bit

◆ HB1OPTONACT

__IOM uint32_t HB1OPTONACT

[4..4] Half Bridge 1 Optimizer for Switch On Active Bit

◆ HB1T12ONERRCNT

__IOM uint32_t HB1T12ONERRCNT

[3..2] Half Bridge 1-T12 On Error Counter Setting

◆ HB1T12ONMAX

__IM uint32_t HB1T12ONMAX

[4..4] Half Bridge 1-T12 On Max Value reached

◆ HB1T12ONMIN

__IM uint32_t HB1T12ONMIN

[6..6] Half Bridge 1-T12 On Min Value reached

◆ HB1T1OFFADDDLY

__IOM uint32_t HB1T1OFFADDDLY

[11..8] HB1 adaptive sequencer T1OFF additional delay setting.

◆ HB1T1OFFERRCNT

__IOM uint32_t HB1T1OFFERRCNT

[1..0] Half Bridge 1-T1 Off Error Counter Setting

◆ HB1T1OFFMAX

__IM uint32_t HB1T1OFFMAX

[0..0] Half Bridge 1-T1 Off Max Value reached

◆ HB1T1OFFMIN

__IM uint32_t HB1T1OFFMIN

[2..2] Half Bridge 1-T1 Off Min Value reached

◆ HB2_ASEQ_IEN

__IOM uint32_t HB2_ASEQ_IEN

[1..1] Half Bridge 2 Adaptive Sequencer Interrupt Enable

◆ HB2_ASEQ_IS

__IOM uint32_t HB2_ASEQ_IS

[1..1] Half Bridge 2 Adaptive Sequencer Interrupt Status

◆ HB2_ASEQ_ISC

__OM uint32_t HB2_ASEQ_ISC

[1..1] Half Bridge 2 Adaptive Sequencer Interrupt Status Clear

◆ HB2_I1OFF

__IOM uint32_t HB2_I1OFF

[5..0] Half Bridge 2-slew rate sequencer off-phase 1 current setting

◆ HB2_I1OFFVAL

__IM uint32_t HB2_I1OFFVAL

[13..8] Half Bridge 2-slew rate sequencer off-phase 1 current setting

◆ HB2_I1ON

__IOM uint32_t HB2_I1ON

[5..0] Half Bridge 2-slew rate sequencer on-phase 1 current setting

◆ HB2_I1ONVAL

__IM uint32_t HB2_I1ONVAL

[13..8] Half Bridge 2-slew rate sequencer on-phase 1 current setting

◆ HB2_I2OFF

__IOM uint32_t HB2_I2OFF

[13..8] Half Bridge 2-slew rate sequencer off-phase 2 current setting

◆ HB2_I2ON

__IOM uint32_t HB2_I2ON

[13..8] Half Bridge 2-slew rate sequencer on-phase 2 current setting

◆ HB2_I3OFF

__IOM uint32_t HB2_I3OFF

[21..16] Half Bridge 2-slew rate sequencer off-phase 3 current setting

◆ HB2_I3ON

__IOM uint32_t HB2_I3ON

[21..16] Half Bridge 2-slew rate sequencer on-phase 3 current setting

◆ HB2_I4OFF

__IOM uint32_t HB2_I4OFF

[29..24] Half Bridge 2-slew rate sequencer off-phase 4 current setting

◆ HB2_I4ON

__IOM uint32_t HB2_I4ON

[29..24] Half Bridge 2-slew rate sequencer on-phase 4 current setting

◆ HB2_ICLMPOFF

__IOM uint32_t HB2_ICLMPOFF

[13..8] Half Bridge 2-current clamping value for OFF state

◆ HB2_ICLMPON

__IOM uint32_t HB2_ICLMPON

[13..8] Half Bridge 2-current clamping value for ON state

◆ HB2_OFFVALVF

__IOM uint32_t HB2_OFFVALVF

[30..30] Half Bridge 2-Turn off slew rate values - Valid Flag.

◆ HB2_OFFVALVF_CLR

__OM uint32_t HB2_OFFVALVF_CLR

[31..31] Half Bridge 2-Turn off slew rate values Valid Flag

  • Clear.

◆ HB2_ONVALVF

__IOM uint32_t HB2_ONVALVF

[30..30] Half Bridge 2-Turn on slew rate values - Valid Flag.

◆ HB2_ONVALVF_CLR

__OM uint32_t HB2_ONVALVF_CLR

[31..31] Half Bridge 2-Turn on slew rate values Valid Flag - Clear.

◆ HB2_SEQMAP

__IOM uint32_t HB2_SEQMAP

[2..2] Half Bridge 2 Sequencer Mapping

◆ HB2_T12ONCNT

__IM uint32_t HB2_T12ONCNT

[7..0] Half Bridge 2-Turn on slew rate-time value measured from beginning of phase 1 to end of phase 2.

◆ HB2_T1OFF

__IOM uint32_t HB2_T1OFF

[7..0] Half Bridge 2-slew rate sequencer off-phase 1 time setting

◆ HB2_T1OFFCNT

__IM uint32_t HB2_T1OFFCNT

[7..0] Half Bridge 2-Turn off slew rate-time value measured from beginning of phase 1 to end of phase 1.

◆ HB2_T1ON

__IOM uint32_t HB2_T1ON

[7..0] Half Bridge 2-slew rate sequencer on-phase 1 time setting

◆ HB2_T2MERR

__IM uint32_t HB2_T2MERR

[22..22] Half Bridge 2-T2 Measurement Error.

◆ HB2_T2OFF

__IOM uint32_t HB2_T2OFF

[13..8] Half Bridge 2-slew rate sequencer off-phase 2 time setting

◆ HB2_T2OFFCNT

__IM uint32_t HB2_T2OFFCNT

[21..16] Half Bridge 2-Turn off slew rate-time value measured from beginning of phase 2 to end of phase 2.

◆ HB2_T2ON

__IOM uint32_t HB2_T2ON

[13..8] Half Bridge 2-slew rate sequencer on-phase 2 time setting

◆ HB2_T3MERR

__IM uint32_t HB2_T3MERR

[22..22] Half Bridge 2-T3 Measurement Error.

◆ HB2_T3OFF

__IOM uint32_t HB2_T3OFF

[21..16] Half Bridge 2-slew rate sequencer off-phase 3 time setting

◆ HB2_T3ON

__IOM uint32_t HB2_T3ON

[21..16] Half Bridge 2-slew rate sequencer on-phase 3 time setting

◆ HB2_T3ONCNT

__IM uint32_t HB2_T3ONCNT

[21..16] Half Bridge 2-Turn on slew rate-time value measured from beginning of phase 3 to end of phase 3.

◆ HB2_T4OFF

__IOM uint32_t HB2_T4OFF

[31..24] Half Bridge 2-slew rate sequencer off-phase 4 time setting

◆ HB2_T4ON

__IOM uint32_t HB2_T4ON

[31..24] Half Bridge 2-slew rate sequencer on-phase 4 time setting

◆ HB2AF_ICLMPOFF

__IOM uint32_t HB2AF_ICLMPOFF

[29..24] Half Bridge 2-active freewheeling-current clamping value for OFF state

◆ HB2AF_ICLMPON

__IOM uint32_t HB2AF_ICLMPON

[29..24] Half Bridge 2-active freewheeling-current clamping value for ON state

◆ HB2AF_IOFF

__IOM uint32_t HB2AF_IOFF

[5..0] Half Bridge 2-active freewheeling-slew rate sequencer off-phase current setting

◆ HB2AF_ION

__IOM uint32_t HB2AF_ION

[21..16] Half Bridge 2-active freewheeling-slew rate sequencer on-phase current setting

◆ HB2AF_TDICLMPOFF

__IOM uint32_t HB2AF_TDICLMPOFF

[7..0] Clamping current delay during active freewheeling for switch off

◆ HB2AF_TDICLMPON

__IOM uint32_t HB2AF_TDICLMPON

[15..8] Clamping current delay during active freewheeling for switch on

◆ 

union { ... } HB2ASEQOFFVAL

◆ 

union { ... } HB2ASEQONVAL

◆ HB2ASMOFFEN

__IOM uint32_t HB2ASMOFFEN

[17..17] Half Bridge 2 Adaptive Sequencer Mode for Switch Off Enable

◆ HB2ASMONEN

__IOM uint32_t HB2ASMONEN

[16..16] Half Bridge 2 Adaptive Sequencer Mode for Switch On Enable

◆ HB2I1OFFMAX

__IM uint32_t HB2I1OFFMAX

[17..17] Half Bridge 2-I1 Off Max Value reached

◆ HB2I1OFFMIN

__IM uint32_t HB2I1OFFMIN

[19..19] Half Bridge 2-I1 Off Min Value reached

◆ HB2I1ONMAX

__IM uint32_t HB2I1ONMAX

[21..21] Half Bridge 2-I1 On Max Value reached

◆ HB2I1ONMIN

__IM uint32_t HB2I1ONMIN

[23..23] Half Bridge 2-I1 On Min Value reached

◆ HB2MFERRCNT

__IOM uint32_t HB2MFERRCNT

[21..20] Half Bridge 2-Measurement Failure Error Counter Setting

◆ HB2OFFHYSTEN

__IOM uint32_t HB2OFFHYSTEN

[23..23] Half Bridge 2 Optimizer Hysteresis for Switch Off Enable Bit

◆ HB2OFFMF

__IM uint32_t HB2OFFMF

[30..30] Half Bridge 2- Off Adaptive Mode Measurement Failure

◆ HB2OFFSEQCNF

__IOM uint32_t HB2OFFSEQCNF

[3..3] Half Bridge 2 Off Sequencer Configuration

◆ HB2ONHYSTEN

__IOM uint32_t HB2ONHYSTEN

[22..22] Half Bridge 2 Optimizer Hysteresis for Switch On Enable Bit

◆ HB2ONMF

__IM uint32_t HB2ONMF

[31..31] Half Bridge 2- On Adaptive Mode Measurement Failure

◆ HB2ONSEQCNF

__IOM uint32_t HB2ONSEQCNF

[1..1] Half Bridge 2 On Sequencer Configuration

◆ HB2OPTOFFACT

__IOM uint32_t HB2OPTOFFACT

[21..21] Half Bridge 2 Optimizer for Switch Off Active Bit

◆ HB2OPTONACT

__IOM uint32_t HB2OPTONACT

[20..20] Half Bridge 2 Optimizer for Switch On Active Bit

◆ HB2T12ONERRCNT

__IOM uint32_t HB2T12ONERRCNT

[19..18] Half Bridge 2-T12 On Error Counter Setting

◆ HB2T12ONMAX

__IM uint32_t HB2T12ONMAX

[20..20] Half Bridge 2-T12 On Max Value reached

◆ HB2T12ONMIN

__IM uint32_t HB2T12ONMIN

[22..22] Half Bridge 2-T12 On Min Value reached

◆ HB2T1OFFADDDLY

__IOM uint32_t HB2T1OFFADDDLY

[15..12] HB2 adaptive sequencer T1OFF additional delay setting.

◆ HB2T1OFFERRCNT

__IOM uint32_t HB2T1OFFERRCNT

[17..16] Half Bridge 2-T1 Off Error Counter Setting

◆ HB2T1OFFMAX

__IM uint32_t HB2T1OFFMAX

[16..16] Half Bridge 2-T1 Off Max Value reached

◆ HB2T1OFFMIN

__IM uint32_t HB2T1OFFMIN

[18..18] Half Bridge 2-T1 Off Min Value reached

◆ HS1_DCS_EN

__IOM uint32_t HS1_DCS_EN

[19..19] High Side Driver 1 Diagnosis Current Source Enable

◆ HS1_DS_IEN

__IOM uint32_t HS1_DS_IEN

[20..20] High Side Driver 1 Drain Source Monitoring Interrupt Enable in OFF-State

◆ HS1_DS_IS

__IOM uint32_t HS1_DS_IS

[20..20] High Side Driver 1 Drain Source Monitoring Interrupt Status in OFF-State

◆ HS1_DS_ISC

__OM uint32_t HS1_DS_ISC

[20..20] High Side Driver 1 Drain Source Monitoring Interrupt Status Clear in OFF-State

◆ HS1_DS_SC

__OM uint32_t HS1_DS_SC

[21..21] High Side Driver 1 Drain Source Monitoring Status Clear in OFF-State

◆ HS1_DS_STS

__IOM uint32_t HS1_DS_STS

[21..21] High Side Driver 1 Drain Source Monitoring Status in OFF-State

◆ HS1_EN

__IOM uint32_t HS1_EN

[16..16] High Side Driver 1 Enable

◆ HS1_OC_DIS

__IOM uint32_t HS1_OC_DIS

[23..23] High Side Driver Overcurrent Shutdown Select

◆ HS1_OC_IEN

__IOM uint32_t HS1_OC_IEN

[22..22] External High Side 1 FET Over-current Interrupt Enable

◆ HS1_OC_IS

__IOM uint32_t HS1_OC_IS

[22..22] External High Side 1 FET Over-current Interrupt Status

◆ HS1_OC_ISC

__OM uint32_t HS1_OC_ISC

[22..22] External High Side 1 FET Over-current Status Clear

◆ HS1_ON

__IOM uint32_t HS1_ON

[18..18] High Side Driver 1 On

◆ HS1_PWM

__IOM uint32_t HS1_PWM

[17..17] High Side Driver 1 PWM Enable

◆ HS1_SRC_SEL

__IOM uint32_t HS1_SRC_SEL

[17..16] HS1 PWM Source Selection

◆ HS1_SUPERR_STS

__IM uint32_t HS1_SUPERR_STS

[21..21] High Side Driver 1 Supply Error Status

◆ HS1DRV_FDISCHG_DIS

__IOM uint32_t HS1DRV_FDISCHG_DIS

[20..20] High Side 1 Predriver fast discharge disable

◆ HS1DRV_OCSDN_DIS

__IOM uint32_t HS1DRV_OCSDN_DIS

[24..24] High Side 1 Predriver in overcurrent situation disable

◆ HS2_DCS_EN

__IOM uint32_t HS2_DCS_EN

[27..27] High Side Driver 2 Diagnosis Current Source Enable

◆ HS2_DS_IEN

__IOM uint32_t HS2_DS_IEN

[28..28] High Side Driver 2 Drain Source Monitoring Interrupt Enable in OFF-State

◆ HS2_DS_IS

__IOM uint32_t HS2_DS_IS

[28..28] High Side Driver 2 Drain Source Monitoring Interrupt Status in OFF-State

◆ HS2_DS_ISC

__OM uint32_t HS2_DS_ISC

[28..28] High Side Driver 2 Drain Source Monitoring Interrupt Status Clear in OFF-State

◆ HS2_DS_SC

__OM uint32_t HS2_DS_SC

[29..29] High Side Driver 2 Drain Source Monitoring Status Clear in OFF-State

◆ HS2_DS_STS

__IOM uint32_t HS2_DS_STS

[29..29] High Side Driver 2 Drain Source Monitoring Status in OFF-State

◆ HS2_EN

__IOM uint32_t HS2_EN

[24..24] High Side Driver 2 Enable

◆ HS2_OC_DIS

__IOM uint32_t HS2_OC_DIS

[31..31] High Side Driver Overcurrent Shutdown Select

◆ HS2_OC_IEN

__IOM uint32_t HS2_OC_IEN

[30..30] External High Side 2 FET Over-current Interrupt Enable

◆ HS2_OC_IS

__IOM uint32_t HS2_OC_IS

[30..30] External High Side 2 FET Over-current Interrupt Status

◆ HS2_OC_ISC

__OM uint32_t HS2_OC_ISC

[30..30] External High Side 2 FET Over-current Status Clear

◆ HS2_ON

__IOM uint32_t HS2_ON

[26..26] High Side Driver 2 On

◆ HS2_PWM

__IOM uint32_t HS2_PWM

[25..25] High Side Driver 2 PWM Enable

◆ HS2_SRC_SEL

__IOM uint32_t HS2_SRC_SEL

[20..19] HS2 PWM Source Selection

◆ HS2_SUPERR_STS

__IM uint32_t HS2_SUPERR_STS

[29..29] High Side Driver 2 Supply Error Status

◆ HS2DRV_FDISCHG_DIS

__IOM uint32_t HS2DRV_FDISCHG_DIS

[21..21] High Side 2 Predriver fast discharge disable

◆ HS2DRV_OCSDN_DIS

__IOM uint32_t HS2DRV_OCSDN_DIS

[25..25] High Side 2 Predriver in overcurrent situation disable

◆ HSDRV_DS_TFILT_SEL

__IOM uint32_t HSDRV_DS_TFILT_SEL

[19..18] Filter Time for Drain-Source Monitoring of High Side Drivers

◆ I1OFFMAX

__IOM uint32_t I1OFFMAX

[5..0] Slew rate sequencer off-phase 1 max. current setting

◆ I1OFFMIN

__IOM uint32_t I1OFFMIN

[5..0] Slew rate sequencer off-phase 1 min. current setting

◆ I1ONMAX

__IOM uint32_t I1ONMAX

[5..0] Slew rate sequencer on-phase 1 max. current setting

◆ I1ONMIN

__IOM uint32_t I1ONMIN

[5..0] Slew rate sequencer on-phase 1 min. current setting

◆ 

union { ... } IGATECLMPOFFC

◆ 

union { ... } IGATECLMPONC

◆ 

union { ... } IRQCLR

◆ 

union { ... } IRQEN

◆ 

union { ... } IRQS

◆ LS1_DS_IEN

__IOM uint32_t LS1_DS_IEN

[4..4] Low Side Driver 1 Drain Source Monitoring Interrupt Enable in OFF-State

◆ LS1_DS_IS

__IOM uint32_t LS1_DS_IS

[4..4] Low Side Driver 1 Drain Source Monitoring Interrupt Status in OFF-State

◆ LS1_DS_ISC

__OM uint32_t LS1_DS_ISC

[4..4] Low Side Driver 1 Drain Source Monitoring Interrupt Status Clear in OFF-State

◆ LS1_DS_SC

__OM uint32_t LS1_DS_SC

[5..5] Low Side Driver 1 Drain Source Monitoring Status Clear in OFF-State

◆ LS1_DS_STS

__IOM uint32_t LS1_DS_STS

[5..5] Low Side Driver 1 Drain Source Monitoring Status in OFF-State

◆ LS1_EN

__IOM uint32_t LS1_EN

[0..0] Low Side Driver 1 Enable

◆ LS1_OC_DIS

__IOM uint32_t LS1_OC_DIS

[7..7] Low Side Driver 1 Overcurrent Shutdown Select

◆ LS1_OC_IEN

__IOM uint32_t LS1_OC_IEN

[6..6] External Low Side 1 FET Over-current Interrupt Enable

◆ LS1_OC_IS

__IOM uint32_t LS1_OC_IS

[6..6] External Low Side 1 FET Over-current Interrupt Status

◆ LS1_OC_ISC

__OM uint32_t LS1_OC_ISC

[6..6] External Low Side 1 FET Over-current Status Clear

◆ LS1_ON

__IOM uint32_t LS1_ON

[2..2] Low Side Driver 1 On

◆ LS1_PWM

__IOM uint32_t LS1_PWM

[1..1] Low Side Driver 1 PWM Enable

◆ LS1_SRC_SEL

__IOM uint32_t LS1_SRC_SEL

[1..0] LS1 PWM Source Selection

◆ LS1_SUPERR_STS

__IM uint32_t LS1_SUPERR_STS

[5..5] Low Side Driver 1 Supply Error Status

◆ LS1DRV_FDISCHG_DIS

__IOM uint32_t LS1DRV_FDISCHG_DIS

[10..10] Low Side 1 Predriver fast discharge disable

◆ LS1DRV_OCSDN_DIS

__IOM uint32_t LS1DRV_OCSDN_DIS

[14..14] Low Side 1 Predriver in overcurrent situation disable

◆ LS2_DS_IEN

__IOM uint32_t LS2_DS_IEN

[12..12] Low Side Driver 2 Drain Source Monitoring Interrupt Enable in OFF-State

◆ LS2_DS_IS

__IOM uint32_t LS2_DS_IS

[12..12] Low Side Driver 2 Drain Source Monitoring Interrupt Status in OFF-State

◆ LS2_DS_ISC

__OM uint32_t LS2_DS_ISC

[12..12] Low Side Driver 2 Drain Source Monitoring Interrupt Status Clear in OFF-State

◆ LS2_DS_SC

__OM uint32_t LS2_DS_SC

[13..13] Low Side Driver 2 Drain Source Monitoring Status Clear in OFF-State

◆ LS2_DS_STS

__IOM uint32_t LS2_DS_STS

[13..13] Low Side Driver 2 Drain Source Monitoring Status in OFF-State

◆ LS2_EN

__IOM uint32_t LS2_EN

[8..8] Low Side Driver 2 Enable

◆ LS2_OC_DIS

__IOM uint32_t LS2_OC_DIS

[15..15] Low Side Driver Overcurrent Shutdown Select

◆ LS2_OC_IEN

__IOM uint32_t LS2_OC_IEN

[14..14] External Low Side 2 FET Over-current Interrupt Enable

◆ LS2_OC_IS

__IOM uint32_t LS2_OC_IS

[14..14] External Low Side 2 FET Over-current Interrupt Status

◆ LS2_OC_ISC

__OM uint32_t LS2_OC_ISC

[14..14] External Low Side 2 FET Over-current Status Clear

◆ LS2_ON

__IOM uint32_t LS2_ON

[10..10] Low Side Driver 2 On

◆ LS2_PWM

__IOM uint32_t LS2_PWM

[9..9] Low Side Driver 2 PWM Enable

◆ LS2_SRC_SEL

__IOM uint32_t LS2_SRC_SEL

[4..3] LS2 PWM Source Selection

◆ LS2_SUPERR_STS

__IM uint32_t LS2_SUPERR_STS

[13..13] Low Side Driver 2 Supply Error Status

◆ LS2DRV_FDISCHG_DIS

__IOM uint32_t LS2DRV_FDISCHG_DIS

[11..11] Low Side 2 Predriver fast discharge disable

◆ LS2DRV_OCSDN_DIS

__IOM uint32_t LS2DRV_OCSDN_DIS

[15..15] Low Side 2 Predriver in overcurrent situation disable

◆ LS_HS_BT_TFILT_SEL

__IOM uint32_t LS_HS_BT_TFILT_SEL

[1..0] Blanking Time for Drain-Source Monitoring of Low / High Side Drivers

◆ LSDRV_DS_TFILT_SEL

__IOM uint32_t LSDRV_DS_TFILT_SEL

[9..8] Filter Time for Drain-Source Monitoring of Low Side Drivers

◆ 

union { ... } OFFASEQTMAX

◆ 

union { ... } OFFASEQTMIN

◆ 

union { ... } OFFSEQHB1IC

◆ 

union { ... } OFFSEQHB1TC

◆ 

union { ... } OFFSEQHB2IC

◆ 

union { ... } OFFSEQHB2TC

◆ 

union { ... } ONASEQTMAX

◆ 

union { ... } ONASEQTMIN

◆ 

union { ... } ONSEQHB1IC

◆ 

union { ... } ONSEQHB1TC

◆ 

union { ... } ONSEQHB2IC

◆ 

union { ... } ONSEQHB2TC

◆ 

union { ... } PWMSRCSEL

◆ reg

(@ 0x00000000) H-Bridge Driver Control 1

(@ 0x00000004) H-Bridge Driver Control 2

(@ 0x00000008) H-Bridge Driver Control 3

(@ 0x0000000C) PWM Source Selection Register

(@ 0x00000010) Slewrate Sequencer Mapping Register

(@ 0x00000018) Trimming of Driver

(@ 0x00000020) Charge Pump Control and Status Register

(@ 0x00000024) Charge Pump Clock Control Register

(@ 0x00000030) Gate Current Clamping Value in ON State

(@ 0x00000034) Gate Current Clamping Value in OFF State

(@ 0x00000040) Charge Pump Status Register

(@ 0x00000044) Charge Pump Interrupt Status Clear Register

(@ 0x00000048) Charge Pump Interrupt Enable Register

(@ 0x00000050) Turn-off Slewrate Sequencer Half Bridge 1 Time Control

(@ 0x00000054) Turn-off Slewrate Sequencer Half Bridge 1 Current Control

(@ 0x00000058) Turn-on Slewrate Sequencer Half Bridge 1 Time Control

(@ 0x0000005C) Turn-on Slewrate Sequencer Half Bridge 1 Current Control

(@ 0x00000064) Slewrate Sequencer-Active Freewheeling-Half Bridge 1 Current Control

(@ 0x00000068) Slewrate Sequencer-Active Freewheeling- Half Bridge 1 Clamping Current Delay

(@ 0x00000070) Turn-off Slewrate Sequencer Half Bridge 2 Time Control

(@ 0x00000074) Turn-off Slewrate Sequencer Half Bridge 2 Current Control

(@ 0x00000078) Turn-on Slewrate Sequencer Half Bridge 2 Time Control

(@ 0x0000007C) Turn-on Slewrate Sequencer Half Bridge 2 Current Control

(@ 0x00000084) Slewrate Sequencer-Active Freewheeling- Half Bridge 2 Current Control

(@ 0x00000088) Slewrate Sequencer-Active Freewheeling- Half Bridge 2 Clamping Current Delay

(@ 0x00000090) Adaptive Slewrate Sequencer Control Register

(@ 0x00000094) Adaptive Slewrate Sequencer Status Register

(@ 0x00000098) Turn ON Adaptive Slewrate Sequencer Minimum Time Setting

(@ 0x0000009C) Turn OFF Adaptive Slewrate Sequencer Minimum Time Setting

(@ 0x000000A0) Adaptive Slewrate Sequencer On Phase Minimum Current Setting

(@ 0x000000A4) Adaptive Slewrate Sequencer Off Phase Minimum Current Setting

(@ 0x000000A8) Adaptive Slewrate On Sequencer Maximum Time Setting

(@ 0x000000AC) Adaptive Slewrate Off Sequencer Maximum Time Setting

(@ 0x000000B0) Adaptive Slewrate Sequencer On Phase Maximum Current Setting

(@ 0x000000B4) Adaptive Slewrate Sequencer Off Phase Maximum Current Setting

(@ 0x000000B8) Half Bridge 1 Adaptive Sequencer On Values

(@ 0x000000BC) Half Bridge 1 Adaptive Sequencer Off Values

(@ 0x000000D0) Half Bridge 2 Adaptive Sequencer On Values

(@ 0x000000D4) Half Bridge 2 Adaptive Sequencer Off Values

(@ 0x000000D8) Adaptive Slewrate Sequencer Error Counter Control Register

(@ 0x000000E0) Current Trimming of Driver

(@ 0x000000F0) H-Bridge Driver Interrupt Status

(@ 0x000000F4) H-Bridge Driver Interrupt Status Clear Register

(@ 0x000000F8) H-Bridge Driver Control

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1

◆ RESERVED10

__IM uint32_t RESERVED10

◆ RESERVED11

__IM uint32_t RESERVED11[3]

◆ RESERVED2

__IM uint32_t RESERVED2[2]

◆ RESERVED3

__IM uint32_t RESERVED3[2]

◆ RESERVED4

__IM uint32_t RESERVED4

◆ RESERVED5

__IM uint32_t RESERVED5

◆ RESERVED6

__IM uint32_t RESERVED6

◆ RESERVED7

__IM uint32_t RESERVED7

◆ RESERVED8

__IM uint32_t RESERVED8

◆ RESERVED9

__IM uint32_t RESERVED9[4]

◆ SEQ_ERR_IEN

__IOM uint32_t SEQ_ERR_IEN

[31..31] Driver Sequence Error Interrupt Enable

◆ SEQ_ERR_IS

__IOM uint32_t SEQ_ERR_IS

[31..31] Driver Sequence Error Interrupt Status

◆ SEQ_ERR_ISC

__OM uint32_t SEQ_ERR_ISC

[31..31] Driver Sequence Error Status Clear

◆ 

union { ... } SEQAFHB1CD

◆ 

union { ... } SEQAFHB1IC

◆ 

union { ... } SEQAFHB2CD

◆ 

union { ... } SEQAFHB2IC

◆ 

union { ... } SEQMAP

◆ T12ONMAX

__IOM uint32_t T12ONMAX

[7..0] Slew rate sequencer on-phase 12 max. time setting

◆ T12ONMIN

__IOM uint32_t T12ONMIN

[7..0] Slew rate sequencer on-phase 12 min. time setting

◆ T1OFFMAX

__IOM uint32_t T1OFFMAX

[7..0] Slew rate sequencer off-phase 1 max. time setting

◆ T1OFFMIN

__IOM uint32_t T1OFFMIN

[7..0] Slew rate sequencer off-phase 1 min. time setting

◆ 

union { ... } TRIM_DRVx

◆ uint32_t

__IM uint32_t

◆ VCP14_15V_SEL

__IOM uint32_t VCP14_15V_SEL

[28..28] Charge Pump 15V/14V Output Voltage Sel

◆ VCP9V_SET

__IOM uint32_t VCP9V_SET

[25..25] Charge Pump 9 V Output Voltage Set

◆ VCP_LOTH1_IEN

__IOM uint32_t VCP_LOTH1_IEN

[9..9] Charge Pump MU Low Interrupt Enable

◆ VCP_LOTH1_IS

__IOM uint32_t VCP_LOTH1_IS

[9..9] Charge Pump MU Low Interrupt Status

◆ VCP_LOTH1_ISC

__OM uint32_t VCP_LOTH1_ISC

[9..9] Charge Pump MU Low Interrupt Status Clear

◆ VCP_LOTH1_SC

__OM uint32_t VCP_LOTH1_SC

[25..25] Charge Pump MU Low Status Clear

◆ VCP_LOTH1_STS

__IOM uint32_t VCP_LOTH1_STS

[25..25] Charge Pump MU Low Status

◆ VCP_OTSD_IEN

__IOM uint32_t VCP_OTSD_IEN

[4..4] Charge Pump Over-temperature Shutdown Interrupt Enable

◆ VCP_OTSD_IS

__IOM uint32_t VCP_OTSD_IS

[4..4] Charge Pump Overtemperature Shutdown Interrupt Status

◆ VCP_OTSD_ISC

__OM uint32_t VCP_OTSD_ISC

[4..4] Charge Pump Over-temperature Shutdown Interrupt Status Clear

◆ VCP_OTSD_SC

__OM uint32_t VCP_OTSD_SC

[20..20] Charge Pump Over-temperature Shutdown Status Clear

◆ VCP_OTSD_STS

__IOM uint32_t VCP_OTSD_STS

[20..20] Charge Pump Overtemperature Shutdown Status

◆ VCP_OTW_IEN

__IOM uint32_t VCP_OTW_IEN

[0..0] Charge Pump Over-temperature Warning Interrupt Enable

◆ VCP_OTW_IS

__IOM uint32_t VCP_OTW_IS

[0..0] Charge Pump Overtemperature Warning Interrupt Status

◆ VCP_OTW_ISC

__OM uint32_t VCP_OTW_ISC

[0..0] Charge Pump Over-temperature Warning Interrupt Status Clear

◆ VCP_OTW_SC

__OM uint32_t VCP_OTW_SC

[16..16] Charge Pump Over-temperature Warning Status Clear

◆ VCP_OTW_STS

__IOM uint32_t VCP_OTW_STS

[16..16] Charge Pump Overtemperature Warning Status

◆ VCP_UPTH_IEN

__IOM uint32_t VCP_UPTH_IEN

[11..11] Charge Pump MU High Interrupt Enable

◆ VCP_UPTH_IS

__IOM uint32_t VCP_UPTH_IS

[11..11] Charge Pump MU High Interrupt Status

◆ VCP_UPTH_ISC

__OM uint32_t VCP_UPTH_ISC

[11..11] Charge Pump MU High Interrupt Status Clear

◆ VCP_UPTH_SC

__OM uint32_t VCP_UPTH_SC

[27..27] Charge Pump MU High Status Clear

◆ VCP_UPTH_STS

__IOM uint32_t VCP_UPTH_STS

[27..27] Charge Pump MU High Status

◆ VSD_LOTH_IEN

__IOM uint32_t VSD_LOTH_IEN

[13..13] Driver Supply MU Low Interrupt Enable

◆ VSD_LOTH_IS

__IOM uint32_t VSD_LOTH_IS

[13..13] Driver Supply MU Low Interrupt Status

◆ VSD_LOTH_ISC

__OM uint32_t VSD_LOTH_ISC

[13..13] Driver Supply MU Low Interrupt Status Clear

◆ VSD_LOTH_SC

__OM uint32_t VSD_LOTH_SC

[29..29] Driver Supply MU Low Status Clear

◆ VSD_LOTH_STS

__IOM uint32_t VSD_LOTH_STS

[29..29] Driver Supply MU Low Status

◆ VSD_UPTH_IEN

__IOM uint32_t VSD_UPTH_IEN

[15..15] Driver Supply MU High Interrupt Enable

◆ VSD_UPTH_IS

__IOM uint32_t VSD_UPTH_IS

[15..15] Driver Supply MU High Interrupt Status

◆ VSD_UPTH_ISC

__OM uint32_t VSD_UPTH_ISC

[15..15] Driver Supply MU High Interrupt Status Clear

◆ VSD_UPTH_SC

__OM uint32_t VSD_UPTH_SC

[31..31] Driver Supply MU High Status Clear

◆ VSD_UPTH_STS

__IOM uint32_t VSD_UPTH_STS

[31..31] Driver Supply MU High Status

◆ VTHVCP_TRIM

__IOM uint32_t VTHVCP_TRIM

[27..26] Charge Pump Output Voltage Trimming


The documentation for this struct was generated from the following file: