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Infineon MOTIX™ MCU TLE985x Device Family SDK
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ADC1 (ADC1)
#include <tle985x.h>
[18..16] Trigger selection for exceptional interrupt measurement (EIM)
[18..16] Trigger selection for exceptional sequence measurement (ESM)
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union { ... } CAL_CH0_1 |
union { ... } CAL_CH10_11 |
union { ... } CAL_CH12_13 |
union { ... } CAL_CH2_3 |
union { ... } CAL_CH4_5 |
union { ... } CAL_CH6_7 |
union { ... } CAL_CH8_9 |
union { ... } CHx_EIM |
union { ... } CHx_ESM |
union { ... } CNT0_3_LOWER |
union { ... } CNT0_3_UPPER |
union { ... } CNT4_7_LOWER |
union { ... } CNT4_7_UPPER |
union { ... } CTRL2 |
union { ... } CTRL3 |
union { ... } CTRL5 |
union { ... } CTRL_STS |
< (@ 0x40004000) ADC1 Structure
union { ... } DCHCNT1_4_LOWER |
union { ... } DCHCNT1_4_UPPER |
union { ... } DCHTH1_4_LOWER |
union { ... } DCHTH1_4_UPPER |
union { ... } DIFFCH_OUT1 |
union { ... } DUIN_SEL |
union { ... } FILT_OUT0 |
union { ... } FILT_OUT1 |
union { ... } FILT_OUT10 |
union { ... } FILT_OUT11 |
union { ... } FILT_OUT12 |
union { ... } FILT_OUT13 |
union { ... } FILT_OUT2 |
union { ... } FILT_OUT3 |
union { ... } FILT_OUT4 |
union { ... } FILT_OUT5 |
union { ... } FILT_OUT6 |
union { ... } FILT_OUT7 |
union { ... } FILT_OUT8 |
union { ... } FILT_OUT9 |
union { ... } FILT_OUTEIM |
union { ... } FILT_UPLO_CTRL |
union { ... } FILTCOEFF0_13 |
[0..0] Upper and lower threshold IIR filter enable Post-Processing-Channel 0
[1..1] Upper and lower threshold IIR filter enable Post-Processing-Channel 1
[2..2] Upper and lower threshold IIR filter enable Post-Processing-Channel 2
[3..3] Upper and lower threshold IIR filter enable Post-Processing-Channel 3
[4..4] Upper and lower threshold IIR filter enable Post-Processing-Channel 4
[5..5] Upper and lower threshold IIR filter enable Post-Processing-Channel 5
[6..6] Upper and lower threshold IIR filter enable Post-Processing-Channel 6
[7..7] Upper and lower threshold IIR filter enable Post-Processing-Channel 7
union { ... } IRQCLR_1 |
union { ... } IRQCLR_2 |
union { ... } IRQEN_1 |
union { ... } IRQEN_2 |
union { ... } IRQS_1 |
union { ... } IRQS_2 |
union { ... } MAX_TIME |
union { ... } MMODE0_7 |
union { ... } OFFSETCALIB |
[0..0] ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt Status Clear
[16..16] ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Enable
[16..16] ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Status
[16..16] ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Status Clear
[2..2] ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Status Clear
[18..18] ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Enable
[18..18] ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Status
[18..18] ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Status Clear
[3..3] ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt Status Clear
[19..19] ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Enable
[19..19] ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Status
[19..19] ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Status Clear
[4..4] ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt Status Clear
[20..20] ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Enable
[20..20] ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Status
[20..20] ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Status Clear
[5..5] ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt Status Clear
[21..21] ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Enable
[21..21] ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Status
[21..21] ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Status Clear
[6..6] ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt Status Clear
[22..22] ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Enable
[22..22] ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Status
[22..22] ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Status Clear
[7..7] ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Status Clear
[23..23] ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Enable
[23..23] ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Status
[23..23] ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Status Clear
union { ... } PP_MAP0_3 |
union { ... } PP_MAP4_7 |
(@ 0x00000000) ADC1 Control and Status Register
(@ 0x00000004) Sequencer Feedback Register
(@ 0x00000008) Channel Setting Bits for Exceptional Interrupt Measurement
(@ 0x0000000C) Channel Setting Bits for Exceptional Sequence Measurement
(@ 0x00000010) Maximum Time for Software Mode
(@ 0x00000014) Measurement Unit 1 Control Register 2
(@ 0x00000018) Measurement Unit 1 Control Register 3
(@ 0x0000001C) Measurement Unit 1 Control Register 5
(@ 0x00000020) Measurement Unit 1 Channel Enable Bits for Cycle 0-1
(@ 0x00000024) Measurement Unit 1 Channel Enable Bits for Cycle 2-3
(@ 0x00000028) Measurement Unit 1 Channel Enable Bits for Cycle 4-5
(@ 0x0000002C) Measurement Unit 1 Channel Enable Bits for Cycle 6-7
(@ 0x00000030) Measurement Unit 1 Channel Enable Bits for Cycle 8-9
(@ 0x00000034) Measurement Unit 1 Channel Enable Bits for Cycle 10-11
(@ 0x00000038) ADC1 Channel Mapping for Sequencer
(@ 0x0000003C) ADC1 Offset Calibration Register
(@ 0x00000040) Lower Comparator Trigger Level Post-Processing-Channel 0-3
(@ 0x00000044) Lower Comparator Trigger Level Post-Processing-Channel 4-7
(@ 0x00000048) Calibration for Channel 0 and 1
(@ 0x0000004C) Calibration for Channel 2 and 3
(@ 0x00000050) Calibration for Channel 4 and 5
(@ 0x00000054) Calibration for Channel 6 and 7
(@ 0x00000058) Calibration for Channel 8 and 9
(@ 0x0000005C) Calibration for Channel 10 and 11
(@ 0x00000060) Filter Coefficients Measurement Unit Channel 0-13
(@ 0x00000064) ADC1 Interrupt Status 1 Register
(@ 0x00000068) ADC1 Interrupt Enable 1 Register
(@ 0x0000006C) ADC1 Interrupt Status Clear 1 Register
(@ 0x00000070) ADC1 or Filter Output Channel 0
(@ 0x00000074) ADC1 or Filter Output Channel 1
(@ 0x00000078) ADC1 or Filter Output Channel 2
(@ 0x0000007C) ADC1 or Filter Output Channel 3
(@ 0x00000080) ADC1 or Filter Output Channel 4
(@ 0x00000084) ADC1 or Filter Output Channel 5
(@ 0x00000088) ADC1 or Filter Output Channel 6
(@ 0x0000008C) ADC1 or Filter Output Channel 7
(@ 0x00000090) ADC1 or Filter Output Channel 8
(@ 0x00000094) ADC1 or Filter Output Channel 9
(@ 0x00000098) ADC1 or Filter Output Channel 10
(@ 0x0000009C) ADC1 or Filter Output Channel 11
(@ 0x000000A0) ADC1 Differential Channel Output 1
(@ 0x000000B0) Upper And Lower Threshold Filter Enable
(@ 0x000000BC) ADC1 Status Register
(@ 0x000000C4) Lower Comparator Trigger Level Differential Channel 1
(@ 0x000000C8) Upper Comparator Trigger Level Post-Processing-Channel 0-3
(@ 0x000000CC) Upper Comparator Trigger Level Post-Processing-Channel 4-7
(@ 0x000000D4) Upper Comparator Trigger Level Differential Channel 1
(@ 0x000000D8) Lower Counter Trigger Level Post-Processing-Channel 0-3
(@ 0x000000DC) Lower Counter Trigger Level Post-Processing-Channel 4-7
(@ 0x000000E4) Lower Counter Trigger Level DifferentialChannel 1
(@ 0x000000E8) Upper Counter Trigger Level Post-Processing-Channel 0-3
(@ 0x000000EC) Upper Counter Trigger Level Post-Processing-Channel 4-7
(@ 0x000000F4) Upper Counter Trigger Level DifferentialChannel 1
(@ 0x000000F8) Overvoltage Measurement Mode of Post-Processing-Channel 0-7
(@ 0x000000FC) Measurement Unit 1 - Differential Unit Input Selection Register
(@ 0x00000100) ADC1 Interrupt Status 2 Register
(@ 0x00000104) ADC1 Status 2 Register
(@ 0x00000108) ADC1 Interrupt Status Clear 2 Register
(@ 0x0000010C) ADC1 Interrupt Enable 2 Register
(@ 0x00000110) ADC1 or Filter Output Channel 12
(@ 0x00000118) Post-Processing Mapping Channel 0-3
(@ 0x0000011C) Post-Processing Mapping Channel 4-7
(@ 0x00000120) ADC1 or Filter Output of EIM
(@ 0x00000124) ADC1 Status 1Register
(@ 0x00000128) ADC1 Status Clear 1 Register
(@ 0x00000130) Measurement Unit 1 Channel Enable Bits for Cycle 12-13
(@ 0x00000138) Calibration for Channel 12 and 13
(@ 0x00000140) ADC1 or Filter Output Channel 13
union { ... } SQ0_1 |
union { ... } SQ10_11 |
union { ... } SQ12_13 |
union { ... } SQ2_3 |
union { ... } SQ4_5 |
union { ... } SQ6_7 |
union { ... } SQ8_9 |
union { ... } SQ_CH_MAP |
union { ... } SQ_FB |
union { ... } STATUS |
union { ... } STS_1 |
union { ... } STS_2 |
union { ... } STSCLR_1 |
union { ... } TH0_3_LOWER |
union { ... } TH0_3_UPPER |
union { ... } TH4_7_LOWER |
union { ... } TH4_7_UPPER |
__IM uint32_t |
[1..1] ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Status Clear
[17..17] ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Status Clear