Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields
ADC1_Type Struct Reference

Detailed Description

ADC1 (ADC1)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PD_N: 1
 
      __IOM uint32_t   SOOC: 1
 
      __IOM uint32_t   SOS: 1
 
      __IM   uint32_t: 1
 
      __IM uint32_t   READY: 1
 
      __IM uint32_t   CAL_SIGN: 1
 
      __IM uint32_t   EOC: 1
 
      __IOM uint32_t   SW_CH_SEL: 4
 
      __IOM uint32_t   STRTUP_DIS: 1
 
   }   bit
 
CTRL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   SQ_FB: 5
 
      __IM   uint32_t: 3
 
      __IM uint32_t   SQ_STOP: 1
 
      __IM uint32_t   EIM_ACTIVE: 1
 
      __IM uint32_t   ESM_ACTIVE: 1
 
      __IM uint32_t   SQx: 4
 
      __IM uint32_t   CHx: 4
 
   }   bit
 
SQ_FB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EIM_CHx: 4
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   EIM_REP: 3
 
      __IOM uint32_t   EIM_EN: 1
 
      __IOM uint32_t   ADC1_EIM_TRIG_SEL: 3
 
   }   bit
 
CHx_EIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ESM_0: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   ADC1_ESM_TRIG_SEL: 3
 
      __IOM uint32_t   ESM_EN: 1
 
      __IOM uint32_t   ESM_STS: 1
 
   }   bit
 
CHx_ESM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MAX_TIME: 8
 
   }   bit
 
MAX_TIME
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CAL_EN: 14
 
   }   bit
 
CTRL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MCM_PD_N: 1
 
      __IOM uint32_t   SW_MODE: 1
 
      __IM   uint32_t: 2
 
      __OM uint32_t   EoC_FAIL_CLR: 1
 
      __IOM uint32_t   EoC_FAIL: 1
 
      __IM uint32_t   MCM_RDY: 1
 
      __IOM uint32_t   SAMPLE_TIME_HVCH: 5
 
      __IOM uint32_t   SAMPLE_TIME_LVCH: 4
 
   }   bit
 
CTRL3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FILT_OUT_SEL_13_0: 14
 
   }   bit
 
CTRL5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ0: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ1: 14
 
   }   bit
 
SQ0_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ2: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ3: 14
 
   }   bit
 
SQ2_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ4: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ5: 14
 
   }   bit
 
SQ4_5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ6: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ7: 14
 
   }   bit
 
SQ6_7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ8: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ9: 14
 
   }   bit
 
SQ8_9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ10: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ11: 14
 
   }   bit
 
SQ10_11
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 5
 
      __IOM uint32_t   SQ_CH5_MAP: 1
 
      __IOM uint32_t   SQ_CH6_MAP: 1
 
      __IOM uint32_t   SQ_CH12_MAP: 1
 
   }   bit
 
SQ_CH_MAP
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   OFFSET_SHIFT: 3
 
      __IM   uint32_t: 5
 
      __IOM uint32_t   OFFSET_DAC: 5
 
   }   bit
 
OFFSETCALIB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP_CH0_LOW: 8
 
      __IOM uint32_t   PP_CH1_LOW: 8
 
      __IOM uint32_t   PP_CH2_LOW: 8
 
      __IOM uint32_t   PP_CH3_LOW: 8
 
   }   bit
 
TH0_3_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP_CH4_LOW: 8
 
      __IOM uint32_t   PP_CH5_LOW: 8
 
      __IOM uint32_t   PP_CH6_LOW: 8
 
      __IOM uint32_t   PP_CH7_LOW: 8
 
   }   bit
 
TH4_7_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALOFFS_CH0: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CALGAIN_CH0: 8
 
      __IOM uint32_t   CALOFFS_CH1: 5
 
      __IOM uint32_t   CALGAIN_CH1: 8
 
   }   bit
 
CAL_CH0_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALOFFS_CH2: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CALGAIN_CH2: 8
 
      __IOM uint32_t   CALOFFS_CH3: 5
 
      __IOM uint32_t   CALGAIN_CH3: 8
 
   }   bit
 
CAL_CH2_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALOFFS_CH4: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CALGAIN_CH4: 8
 
      __IOM uint32_t   CALOFFS_CH5: 5
 
      __IOM uint32_t   CALGAIN_CH5: 8
 
   }   bit
 
CAL_CH4_5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALOFFS_CH6: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CALGAIN_CH6: 8
 
      __IOM uint32_t   CALOFFS_CH7: 5
 
      __IOM uint32_t   CALGAIN_CH7: 8
 
   }   bit
 
CAL_CH6_7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALOFFS_CH8: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CALGAIN_CH8: 8
 
      __IOM uint32_t   CALOFFS_CH9: 5
 
      __IOM uint32_t   CALGAIN_CH9: 8
 
   }   bit
 
CAL_CH8_9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALOFFS_CH10: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CALGAIN_CH10: 8
 
      __IOM uint32_t   CALOFFS_CH11: 5
 
      __IOM uint32_t   CALGAIN_CH11: 8
 
   }   bit
 
CAL_CH10_11
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CH0: 2
 
      __IOM uint32_t   CH1: 2
 
      __IOM uint32_t   CH2: 2
 
      __IOM uint32_t   CH3: 2
 
      __IOM uint32_t   CH4: 2
 
      __IOM uint32_t   CH5: 2
 
      __IOM uint32_t   CH6: 2
 
      __IOM uint32_t   CH7: 2
 
      __IOM uint32_t   CH8: 2
 
      __IOM uint32_t   CH9: 2
 
      __IOM uint32_t   CH10: 2
 
      __IOM uint32_t   CH11: 2
 
      __IOM uint32_t   CH12: 2
 
      __IOM uint32_t   CH13: 2
 
   }   bit
 
FILTCOEFF0_13
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IIR_CH0_IS: 1
 
      __IOM uint32_t   VS_IS: 1
 
      __IOM uint32_t   IIR_CH2_IS: 1
 
      __IOM uint32_t   IIR_CH3_IS: 1
 
      __IOM uint32_t   IIR_CH4_IS: 1
 
      __IOM uint32_t   IIR_CH5_IS: 1
 
      __IOM uint32_t   IIR_CH6_IS: 1
 
      __IOM uint32_t   IIR_CH7_IS: 1
 
      __IOM uint32_t   IIR_CH8_IS: 1
 
      __IOM uint32_t   IIR_CH9_IS: 1
 
      __IOM uint32_t   IIR_CH10_IS: 1
 
      __IOM uint32_t   IIR_CH11_IS: 1
 
      __IOM uint32_t   IIR_CH12_IS: 1
 
      __IOM uint32_t   IIR_CH13_IS: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   EIM_IS: 1
 
      __IOM uint32_t   ESM_IS: 1
 
      __IOM uint32_t   DU1LO_IS: 1
 
      __IOM uint32_t   DU1UP_IS: 1
 
   }   bit
 
IRQS_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IIR_CH0_IEN: 1
 
      __IOM uint32_t   VS_IEN: 1
 
      __IOM uint32_t   IIR_CH2_IEN: 1
 
      __IOM uint32_t   IIR_CH3_IEN: 1
 
      __IOM uint32_t   IIR_CH4_IEN: 1
 
      __IOM uint32_t   IIR_CH5_IEN: 1
 
      __IOM uint32_t   IIR_CH6_IEN: 1
 
      __IOM uint32_t   IIR_CH7_IEN: 1
 
      __IOM uint32_t   IIR_CH8_IEN: 1
 
      __IOM uint32_t   IIR_CH9_IEN: 1
 
      __IOM uint32_t   IIR_CH10_IEN: 1
 
      __IOM uint32_t   IIR_CH11_IEN: 1
 
      __IOM uint32_t   IIR_CH12_IEN: 1
 
      __IOM uint32_t   IIR_CH13_IEN: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   EIM_IEN: 1
 
      __IOM uint32_t   ESM_IEN: 1
 
      __IOM uint32_t   DU1LO_IEN: 1
 
      __IOM uint32_t   DU1UP_IEN: 1
 
   }   bit
 
IRQEN_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   IIR_CH0_ISC: 1
 
      __OM uint32_t   VS_ISC: 1
 
      __OM uint32_t   IIR_CH2_ISC: 1
 
      __OM uint32_t   IIR_CH3_ISC: 1
 
      __OM uint32_t   IIR_CH4_ISC: 1
 
      __OM uint32_t   IIR_CH5_ISC: 1
 
      __OM uint32_t   IIR_CH6_ISC: 1
 
      __OM uint32_t   IIR_CH7_ISC: 1
 
      __OM uint32_t   IIR_CH8_ISC: 1
 
      __OM uint32_t   IIR_CH9_ISC: 1
 
      __OM uint32_t   IIR_CH10_ISC: 1
 
      __OM uint32_t   IIR_CH11_ISC: 1
 
      __OM uint32_t   IIR_CH12_ISC: 1
 
      __OM uint32_t   IIR_CH13_ISC: 1
 
      __IM   uint32_t: 2
 
      __OM uint32_t   EIM_ISC: 1
 
      __OM uint32_t   ESM_ISC: 1
 
      __OM uint32_t   DU1LO_ISC: 1
 
      __OM uint32_t   DU1UP_ISC: 1
 
   }   bit
 
IRQCLR_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH0: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR0: 1
 
      __IM uint32_t   VF0: 1
 
      __IM uint32_t   OF0: 1
 
   }   bit
 
FILT_OUT0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH1: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR1: 1
 
      __IM uint32_t   VF1: 1
 
      __IM uint32_t   OF1: 1
 
   }   bit
 
FILT_OUT1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH2: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR2: 1
 
      __IM uint32_t   VF2: 1
 
      __IM uint32_t   OF2: 1
 
   }   bit
 
FILT_OUT2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH3: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR3: 1
 
      __IM uint32_t   VF3: 1
 
      __IM uint32_t   OF3: 1
 
   }   bit
 
FILT_OUT3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH4: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR4: 1
 
      __IM uint32_t   VF4: 1
 
      __IM uint32_t   OF4: 1
 
   }   bit
 
FILT_OUT4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH5: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR5: 1
 
      __IM uint32_t   VF5: 1
 
      __IM uint32_t   OF5: 1
 
   }   bit
 
FILT_OUT5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH6: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR6: 1
 
      __IM uint32_t   VF6: 1
 
      __IM uint32_t   OF6: 1
 
   }   bit
 
FILT_OUT6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH7: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR7: 1
 
      __IM uint32_t   VF7: 1
 
      __IM uint32_t   OF7: 1
 
   }   bit
 
FILT_OUT7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH8: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR8: 1
 
      __IM uint32_t   VF8: 1
 
      __IM uint32_t   OF8: 1
 
   }   bit
 
FILT_OUT8
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH9: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR9: 1
 
      __IM uint32_t   VF9: 1
 
      __IM uint32_t   OF9: 1
 
   }   bit
 
FILT_OUT9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH10: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR10: 1
 
      __IM uint32_t   VF10: 1
 
      __IM uint32_t   OF10: 1
 
   }   bit
 
FILT_OUT10
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH11: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR11: 1
 
      __IM uint32_t   VF11: 1
 
      __IM uint32_t   OF11: 1
 
   }   bit
 
FILT_OUT11
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   DCH1: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   DWFR1: 1
 
      __IM uint32_t   DVF1: 1
 
      __IM uint32_t   DOF1: 1
 
   }   bit
 
DIFFCH_OUT1
 
__IM uint32_t RESERVED [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   FUL_PP_CH0_EN: 1
 
      __IOM uint32_t   FUL_PP_CH1_EN: 1
 
      __IOM uint32_t   FUL_PP_CH2_EN: 1
 
      __IOM uint32_t   FUL_PP_CH3_EN: 1
 
      __IOM uint32_t   FUL_PP_CH4_EN: 1
 
      __IOM uint32_t   FUL_PP_CH5_EN: 1
 
      __IOM uint32_t   FUL_PP_CH6_EN: 1
 
      __IOM uint32_t   FUL_PP_CH7_EN: 1
 
   }   bit
 
FILT_UPLO_CTRL
 
__IM uint32_t RESERVED1 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DAC_IN: 3
 
      __IM   uint32_t: 13
 
      __IOM uint32_t   SOC_JITTER: 2
 
      __IOM uint32_t   SD_FEEDB_ON: 1
 
   }   bit
 
STATUS
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DCH1_LOW: 8
 
   }   bit
 
DCHTH1_4_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP_CH0_UP: 8
 
      __IOM uint32_t   PP_CH1_UP: 8
 
      __IOM uint32_t   PP_CH2_UP: 8
 
      __IOM uint32_t   PP_CH3_UP: 8
 
   }   bit
 
TH0_3_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP_CH4_UP: 8
 
      __IOM uint32_t   PP_CH5_UP: 8
 
      __IOM uint32_t   PP_CH6_UP: 8
 
      __IOM uint32_t   PP_CH7_UP: 8
 
   }   bit
 
TH4_7_UPPER
 
__IM uint32_t RESERVED3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DCH1_UP: 8
 
   }   bit
 
DCHTH1_4_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_PP0: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_LO_PP0: 2
 
      __IOM uint32_t   CNT_LO_PP1: 2
 
      __IOM uint32_t   HYST_LO_PP1: 2
 
      __IOM uint32_t   CNT_LO_PP2: 2
 
      __IOM uint32_t   HYST_LO_PP2: 2
 
      __IOM uint32_t   CNT_LO_PP3: 2
 
      __IOM uint32_t   HYST_LO_PP3: 2
 
   }   bit
 
CNT0_3_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_PP4: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_LO_PP4: 2
 
      __IOM uint32_t   CNT_LO_PP5: 2
 
      __IOM uint32_t   HYST_LO_PP5: 2
 
      __IOM uint32_t   CNT_LO_PP6: 2
 
      __IOM uint32_t   HYST_LO_PP6: 2
 
      __IOM uint32_t   CNT_LO_PP7: 2
 
      __IOM uint32_t   HYST_LO_PP7: 2
 
   }   bit
 
CNT4_7_LOWER
 
__IM uint32_t RESERVED4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_LO_DCH1: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_LO_DCH1: 2
 
   }   bit
 
DCHCNT1_4_LOWER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_PP0: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_UP_PP0: 2
 
      __IOM uint32_t   CNT_UP_PP1: 2
 
      __IOM uint32_t   HYST_UP_PP1: 2
 
      __IOM uint32_t   CNT_UP_PP2: 2
 
      __IOM uint32_t   HYST_UP_PP2: 2
 
      __IOM uint32_t   CNT_UP_PP3: 2
 
      __IOM uint32_t   HYST_UP_PP3: 2
 
   }   bit
 
CNT0_3_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_PP4: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_UP_PP4: 2
 
      __IOM uint32_t   CNT_UP_PP5: 2
 
      __IOM uint32_t   HYST_UP_PP5: 2
 
      __IOM uint32_t   CNT_UP_PP6: 2
 
      __IOM uint32_t   HYST_UP_PP6: 2
 
      __IOM uint32_t   CNT_UP_PP7: 2
 
      __IOM uint32_t   HYST_UP_PP7: 2
 
   }   bit
 
CNT4_7_UPPER
 
__IM uint32_t RESERVED5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CNT_UP_DCH1: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   HYST_UP_DCH1: 2
 
   }   bit
 
DCHCNT1_4_UPPER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MMODE_0: 2
 
      __IOM uint32_t   MMODE_1: 2
 
      __IOM uint32_t   MMODE_2: 2
 
      __IOM uint32_t   MMODE_3: 2
 
      __IOM uint32_t   MMODE_4: 2
 
      __IOM uint32_t   MMODE_5: 2
 
      __IOM uint32_t   MMODE_6: 2
 
      __IOM uint32_t   MMODE_7: 2
 
      __IM   uint32_t: 8
 
      __IOM uint32_t   MMODE_D1: 2
 
   }   bit
 
MMODE0_7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DU1_EN: 1
 
      __IM   uint32_t: 3
 
      __IM uint32_t   DU1RES_NEG: 1
 
   }   bit
 
DUIN_SEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP_CH0_LO_IS: 1
 
      __IOM uint32_t   VS_LO_IS: 1
 
      __IOM uint32_t   PP_CH2_LO_IS: 1
 
      __IOM uint32_t   PP_CH3_LO_IS: 1
 
      __IOM uint32_t   PP_CH4_LO_IS: 1
 
      __IOM uint32_t   PP_CH5_LO_IS: 1
 
      __IOM uint32_t   PP_CH6_LO_IS: 1
 
      __IOM uint32_t   PP_CH7_LO_IS: 1
 
      __IM   uint32_t: 8
 
      __IOM uint32_t   PP_CH0_UP_IS: 1
 
      __IOM uint32_t   VS_UP_IS: 1
 
      __IOM uint32_t   PP_CH2_UP_IS: 1
 
      __IOM uint32_t   PP_CH3_UP_IS: 1
 
      __IOM uint32_t   PP_CH4_UP_IS: 1
 
      __IOM uint32_t   PP_CH5_UP_IS: 1
 
      __IOM uint32_t   PP_CH6_UP_IS: 1
 
      __IOM uint32_t   PP_CH7_UP_IS: 1
 
   }   bit
 
IRQS_2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   PP_CH0_LO_STS: 1
 
      __IM uint32_t   VS_LO_STS: 1
 
      __IM uint32_t   PP_CH2_LO_STS: 1
 
      __IM uint32_t   PP_CH3_LO_STS: 1
 
      __IM uint32_t   PP_CH4_LO_STS: 1
 
      __IM uint32_t   PP_CH5_LO_STS: 1
 
      __IM uint32_t   PP_CH6_LO_STS: 1
 
      __IM uint32_t   PP_CH7_LO_STS: 1
 
      __IM   uint32_t: 8
 
      __IM uint32_t   PP_CH0_UP_STS: 1
 
      __IM uint32_t   VS_UP_STS: 1
 
      __IM uint32_t   PP_CH2_UP_STS: 1
 
      __IM uint32_t   PP_CH3_UP_STS: 1
 
      __IM uint32_t   PP_CH4_UP_STS: 1
 
      __IM uint32_t   PP_CH5_UP_STS: 1
 
      __IM uint32_t   PP_CH6_UP_STS: 1
 
      __IM uint32_t   PP_CH7_UP_STS: 1
 
   }   bit
 
STS_2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   PP_CH0_LO_ISC: 1
 
      __OM uint32_t   VS_LO_ISC: 1
 
      __OM uint32_t   PP_CH2_LO_ISC: 1
 
      __OM uint32_t   PP_CH3_LO_ISC: 1
 
      __OM uint32_t   PP_CH4_LO_ISC: 1
 
      __OM uint32_t   PP_CH5_LO_ISC: 1
 
      __OM uint32_t   PP_CH6_LO_ISC: 1
 
      __OM uint32_t   PP_CH7_LO_ISC: 1
 
      __IM   uint32_t: 8
 
      __OM uint32_t   PP_CH0_UP_ISC: 1
 
      __OM uint32_t   VS_UP_ISC: 1
 
      __OM uint32_t   PP_CH2_UP_ISC: 1
 
      __OM uint32_t   PP_CH3_UP_ISC: 1
 
      __OM uint32_t   PP_CH4_UP_ISC: 1
 
      __OM uint32_t   PP_CH5_UP_ISC: 1
 
      __OM uint32_t   PP_CH6_UP_ISC: 1
 
      __OM uint32_t   PP_CH7_UP_ISC: 1
 
   }   bit
 
IRQCLR_2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP_CH0_LO_IEN: 1
 
      __IOM uint32_t   VS_LO_IEN: 1
 
      __IOM uint32_t   PP_CH2_LO_IEN: 1
 
      __IOM uint32_t   PP_CH3_LO_IEN: 1
 
      __IOM uint32_t   PP_CH4_LO_IEN: 1
 
      __IOM uint32_t   PP_CH5_LO_IEN: 1
 
      __IOM uint32_t   PP_CH6_LO_IEN: 1
 
      __IOM uint32_t   PP_CH7_LO_IEN: 1
 
      __IM   uint32_t: 8
 
      __IOM uint32_t   PP_CH0_UP_IEN: 1
 
      __IOM uint32_t   VS_UP_IEN: 1
 
      __IOM uint32_t   PP_CH2_UP_IEN: 1
 
      __IOM uint32_t   PP_CH3_UP_IEN: 1
 
      __IOM uint32_t   PP_CH4_UP_IEN: 1
 
      __IOM uint32_t   PP_CH5_UP_IEN: 1
 
      __IOM uint32_t   PP_CH6_UP_IEN: 1
 
      __IOM uint32_t   PP_CH7_UP_IEN: 1
 
   }   bit
 
IRQEN_2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH12: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR12: 1
 
      __IM uint32_t   VF12: 1
 
      __IM uint32_t   OF12: 1
 
   }   bit
 
FILT_OUT12
 
__IM uint32_t RESERVED6
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   RESET_PP_MAP0: 1
 
      __IOM uint32_t   EN_PP_MAP0: 1
 
      __IOM uint32_t   RESET_PP_MAP1: 1
 
      __IOM uint32_t   EN_PP_MAP1: 1
 
      __IOM uint32_t   PP_MAP2: 4
 
      __IOM uint32_t   RESET_PP_MAP2: 1
 
      __IOM uint32_t   EN_PP_MAP2: 1
 
      __IOM uint32_t   PP_MAP3: 4
 
      __IOM uint32_t   RESET_PP_MAP3: 1
 
      __IOM uint32_t   EN_PP_MAP3: 1
 
   }   bit
 
PP_MAP0_3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP_MAP4: 4
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   RESET_PP_MAP4: 1
 
      __IOM uint32_t   EN_PP_MAP4: 1
 
      __IOM uint32_t   PP_MAP5: 4
 
      __IOM uint32_t   RESET_PP_MAP5: 1
 
      __IOM uint32_t   EN_PP_MAP5: 1
 
      __IOM uint32_t   PP_MAP6: 4
 
      __IOM uint32_t   RESET_PP_MAP6: 1
 
      __IOM uint32_t   EN_PP_MAP6: 1
 
      __IOM uint32_t   PP_MAP7: 4
 
      __IOM uint32_t   RESET_PP_MAP7: 1
 
      __IOM uint32_t   EN_PP_MAP7: 1
 
   }   bit
 
PP_MAP4_7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_EIM: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR_EIM: 1
 
      __IM uint32_t   VF_EIM: 1
 
      __IM uint32_t   OF_EIM: 1
 
   }   bit
 
FILT_OUTEIM
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 24
 
      __IOM uint32_t   DU1LO_STS: 1
 
      __IOM uint32_t   DU1UP_STS: 1
 
   }   bit
 
STS_1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 24
 
      __OM uint32_t   DU1LO_SC: 1
 
      __OM uint32_t   DU1UP_SC: 1
 
   }   bit
 
STSCLR_1
 
__IM uint32_t RESERVED7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SQ12: 14
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   SQ13: 14
 
   }   bit
 
SQ12_13
 
__IM uint32_t RESERVED8
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CALOFFS_CH12: 5
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   CALGAIN_CH12: 8
 
      __IOM uint32_t   CALOFFS_CH13: 5
 
      __IOM uint32_t   CALGAIN_CH13: 8
 
   }   bit
 
CAL_CH12_13
 
__IM uint32_t RESERVED9
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FILT_OUT_CH13: 12
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   WFR13: 1
 
      __IM uint32_t   VF13: 1
 
      __IM uint32_t   OF13: 1
 
   }   bit
 
FILT_OUT13
 

Field Documentation

◆ ADC1_EIM_TRIG_SEL

__IOM uint32_t ADC1_EIM_TRIG_SEL

[18..16] Trigger selection for exceptional interrupt measurement (EIM)

◆ ADC1_ESM_TRIG_SEL

__IOM uint32_t ADC1_ESM_TRIG_SEL

[18..16] Trigger selection for exceptional sequence measurement (ESM)

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◆ 

union { ... } CAL_CH0_1

◆ 

union { ... } CAL_CH10_11

◆ 

union { ... } CAL_CH12_13

◆ 

union { ... } CAL_CH2_3

◆ 

union { ... } CAL_CH4_5

◆ 

union { ... } CAL_CH6_7

◆ 

union { ... } CAL_CH8_9

◆ CAL_EN

__IOM uint32_t CAL_EN

[13..0] Calibration Enable for Channels 0 to 13

◆ CAL_SIGN

__IM uint32_t CAL_SIGN

[5..5] Output of Comparator to Steer Gain / Offset calibration

◆ CALGAIN_CH0

__IOM uint32_t CALGAIN_CH0

[15..8] Gain Calibration for channel 0

◆ CALGAIN_CH1

__IOM uint32_t CALGAIN_CH1

[31..24] Gain Calibration for channel 1

◆ CALGAIN_CH10

__IOM uint32_t CALGAIN_CH10

[15..8] Gain Calibration for channel 10

◆ CALGAIN_CH11

__IOM uint32_t CALGAIN_CH11

[31..24] Gain Calibration for channel 11

◆ CALGAIN_CH12

__IOM uint32_t CALGAIN_CH12

[15..8] Gain Calibration for channel 12

◆ CALGAIN_CH13

__IOM uint32_t CALGAIN_CH13

[31..24] Gain Calibration for channel 13

◆ CALGAIN_CH2

__IOM uint32_t CALGAIN_CH2

[15..8] Gain Calibration for channel 2

◆ CALGAIN_CH3

__IOM uint32_t CALGAIN_CH3

[31..24] Gain Calibration for channel 3

◆ CALGAIN_CH4

__IOM uint32_t CALGAIN_CH4

[15..8] Gain Calibration for channel 4

◆ CALGAIN_CH5

__IOM uint32_t CALGAIN_CH5

[31..24] Gain Calibration for channel 5

◆ CALGAIN_CH6

__IOM uint32_t CALGAIN_CH6

[15..8] Gain Calibration for channel 6

◆ CALGAIN_CH7

__IOM uint32_t CALGAIN_CH7

[31..24] Gain Calibration for channel 7

◆ CALGAIN_CH8

__IOM uint32_t CALGAIN_CH8

[15..8] Gain Calibration for channel 8

◆ CALGAIN_CH9

__IOM uint32_t CALGAIN_CH9

[31..24] Gain Calibration for channel 9

◆ CALOFFS_CH0

__IOM uint32_t CALOFFS_CH0

[4..0] Offset Calibration for channel 0

◆ CALOFFS_CH1

__IOM uint32_t CALOFFS_CH1

[20..16] Offset Calibration for channel 1

◆ CALOFFS_CH10

__IOM uint32_t CALOFFS_CH10

[4..0] Offset Calibration for channel 10

◆ CALOFFS_CH11

__IOM uint32_t CALOFFS_CH11

[20..16] Offset Calibration for channel 11

◆ CALOFFS_CH12

__IOM uint32_t CALOFFS_CH12

[4..0] Offset Calibration for channel 12

◆ CALOFFS_CH13

__IOM uint32_t CALOFFS_CH13

[20..16] Offset Calibration for channel 13

◆ CALOFFS_CH2

__IOM uint32_t CALOFFS_CH2

[4..0] Offset Calibration for channel 2

◆ CALOFFS_CH3

__IOM uint32_t CALOFFS_CH3

[20..16] Offset Calibration for channel 3

◆ CALOFFS_CH4

__IOM uint32_t CALOFFS_CH4

[4..0] Offset Calibration for channel 4

◆ CALOFFS_CH5

__IOM uint32_t CALOFFS_CH5

[20..16] Offset Calibration for channel 5

◆ CALOFFS_CH6

__IOM uint32_t CALOFFS_CH6

[4..0] Offset Calibration for channel 6

◆ CALOFFS_CH7

__IOM uint32_t CALOFFS_CH7

[20..16] Offset Calibration for channel 7

◆ CALOFFS_CH8

__IOM uint32_t CALOFFS_CH8

[4..0] Offset Calibration for channel 8

◆ CALOFFS_CH9

__IOM uint32_t CALOFFS_CH9

[20..16] Offset Calibration for channel 9

◆ CH0

[1..0] Filter Coefficients ADC channel 0

◆ CH1

[3..2] Filter Coefficients ADC channel 1

◆ CH10

[21..20] Filter Coefficients ADC channel 10

◆ CH11

[23..22] Filter Coefficients ADC channel 11

◆ CH12

[25..24] Filter Coefficients ADC channel 12

◆ CH13

[27..26] Filter Coefficients ADC channel 13

◆ CH2

[5..4] Filter Coefficients ADC channel 2

◆ CH3

[7..6] Filter Coefficients ADC channel 3

◆ CH4

[9..8] Filter Coefficients ADC channel 4

◆ CH5

[11..10] Filter Coefficients ADC channel 5

◆ CH6

[13..12] Filter Coefficients ADC channel 6

◆ CH7

[15..14] Filter Coefficients ADC channel 7

◆ CH8

[17..16] Filter Coefficients ADC channel 8

◆ CH9

[19..18] Filter Coefficients ADC channel 9

◆ CHx

[19..16] Current ADC1 Channel

◆ 

union { ... } CHx_EIM

◆ 

union { ... } CHx_ESM

◆ 

union { ... } CNT0_3_LOWER

◆ 

union { ... } CNT0_3_UPPER

◆ 

union { ... } CNT4_7_LOWER

◆ 

union { ... } CNT4_7_UPPER

◆ CNT_LO_DCH1

__IOM uint32_t CNT_LO_DCH1

[1..0] Lower timer trigger threshold Post-Processing-Channel 4

◆ CNT_LO_PP0

__IOM uint32_t CNT_LO_PP0

[1..0] Lower timer trigger threshold Post-Processing-Channel 0

◆ CNT_LO_PP1

__IOM uint32_t CNT_LO_PP1

[9..8] Lower timer trigger threshold Post-Processing-Channel 1

◆ CNT_LO_PP2

__IOM uint32_t CNT_LO_PP2

[17..16] Lower timer trigger threshold Post-Processing-Channel 2

◆ CNT_LO_PP3

__IOM uint32_t CNT_LO_PP3

[25..24] Lower timer trigger threshold Post-Processing-Channel 3

◆ CNT_LO_PP4

__IOM uint32_t CNT_LO_PP4

[1..0] Lower timer trigger threshold Post-Processing-Channel 4

◆ CNT_LO_PP5

__IOM uint32_t CNT_LO_PP5

[9..8] Lower timer trigger threshold Post-Processing-Channel 5

◆ CNT_LO_PP6

__IOM uint32_t CNT_LO_PP6

[17..16] Lower timer trigger threshold Post-Processing-Channel 6

◆ CNT_LO_PP7

__IOM uint32_t CNT_LO_PP7

[25..24] Lower timer trigger threshold Post-Processing-Channel 7

◆ CNT_UP_DCH1

__IOM uint32_t CNT_UP_DCH1

[1..0] Upper timer trigger threshold Post-Processing-Channel 4

◆ CNT_UP_PP0

__IOM uint32_t CNT_UP_PP0

[1..0] Upper timer trigger threshold Post-Processing-Channel 0

◆ CNT_UP_PP1

__IOM uint32_t CNT_UP_PP1

[9..8] Upper timer trigger threshold Post-Processing-Channel 1

◆ CNT_UP_PP2

__IOM uint32_t CNT_UP_PP2

[17..16] Upper timer trigger threshold Post-Processing-Channel 2

◆ CNT_UP_PP3

__IOM uint32_t CNT_UP_PP3

[25..24] Upper timer trigger threshold Post-Processing-Channel 3

◆ CNT_UP_PP4

__IOM uint32_t CNT_UP_PP4

[1..0] Upper timer trigger threshold Post-Processing-Channel 4

◆ CNT_UP_PP5

__IOM uint32_t CNT_UP_PP5

[9..8] Upper timer trigger threshold Post-Processing-Channel 5

◆ CNT_UP_PP6

__IOM uint32_t CNT_UP_PP6

[17..16] Upper timer trigger threshold Post-Processing-Channel 6

◆ CNT_UP_PP7

__IOM uint32_t CNT_UP_PP7

[25..24] Upper timer trigger threshold Post-Processing-Channel 7

◆ 

union { ... } CTRL2

◆ 

union { ... } CTRL3

◆ 

union { ... } CTRL5

◆ 

union { ... } CTRL_STS

< (@ 0x40004000) ADC1 Structure

◆ DAC_IN

__IOM uint32_t DAC_IN

[2..0] Programs the 2-bit DAC for functional test

◆ DCH1

__IM uint32_t DCH1

[11..0] ADC differential output value 1

◆ DCH1_LOW

__IOM uint32_t DCH1_LOW

[7..0] Differential Channel 1 lower trigger level

◆ DCH1_UP

__IOM uint32_t DCH1_UP

[7..0] Differential Channel 1 upper trigger level

◆ 

union { ... } DCHCNT1_4_LOWER

◆ 

union { ... } DCHCNT1_4_UPPER

◆ 

union { ... } DCHTH1_4_LOWER

◆ 

union { ... } DCHTH1_4_UPPER

◆ 

union { ... } DIFFCH_OUT1

◆ DOF1

__IM uint32_t DOF1

[18..18] Overrun Flag

◆ DU1_EN

__IOM uint32_t DU1_EN

[0..0] Differential Unit 1 enable

◆ DU1LO_IEN

__IOM uint32_t DU1LO_IEN

[24..24] Differential Unit 1 lower Interrupt Enable

◆ DU1LO_IS

__IOM uint32_t DU1LO_IS

[24..24] ADC1 Differential Unit 1 (DU1) lower Channel Interrupt Status

◆ DU1LO_ISC

__OM uint32_t DU1LO_ISC

[24..24] Differential Unit 1 lower Interrupt Status Clear

◆ DU1LO_SC

__OM uint32_t DU1LO_SC

[24..24] ADC1 Differential Unit 1 (DU1) lower Channel Status Clear

◆ DU1LO_STS

__IOM uint32_t DU1LO_STS

[24..24] ADC1 Differential Unit 1 (DU1) lower Channel Status

◆ DU1RES_NEG

__IM uint32_t DU1RES_NEG

[4..4] Differential Unit 1 result negative

◆ DU1UP_IEN

__IOM uint32_t DU1UP_IEN

[25..25] Differential Unit 1 upper Interrupt Enable

◆ DU1UP_IS

__IOM uint32_t DU1UP_IS

[25..25] ADC1 Differential Unit 1 (DU1) upper Channel Interrupt Status

◆ DU1UP_ISC

__OM uint32_t DU1UP_ISC

[25..25] Differential Unit 1 lower Interrupt Status Clear

◆ DU1UP_SC

__OM uint32_t DU1UP_SC

[25..25] ADC1 Differential Unit 1 (DU1) upper Channel Status Clear

◆ DU1UP_STS

__IOM uint32_t DU1UP_STS

[25..25] ADC1 Differential Unit 1 (DU1) upper Channel Status

◆ 

union { ... } DUIN_SEL

◆ DVF1

__IM uint32_t DVF1

[17..17] Valid Flag

◆ DWFR1

__IOM uint32_t DWFR1

[16..16] Wait for Read Mode

◆ EIM_ACTIVE

__IM uint32_t EIM_ACTIVE

[9..9] ADC1 EIM active

◆ EIM_CHx

__IOM uint32_t EIM_CHx

[3..0] Channel set for exceptional interrupt measurement (EIM)

◆ EIM_EN

__IOM uint32_t EIM_EN

[11..11] Exceptional interrupt measurement (EIM) Trigger Event enable

◆ EIM_IEN

__IOM uint32_t EIM_IEN

[16..16] Exceptional Interrupt Measurement (EIM) Interrupt Enable

◆ EIM_IS

__IOM uint32_t EIM_IS

[16..16] Exceptional Interrupt Measurement (EIM) Status

◆ EIM_ISC

__OM uint32_t EIM_ISC

[16..16] Exceptional Interrupt Measurement (EIM) Status Clear

◆ EIM_REP

__IOM uint32_t EIM_REP

[10..8] Repeat count for exceptional interrupt measurement (EIM)

◆ EN_PP_MAP0

__IOM uint32_t EN_PP_MAP0

[7..7] Mapping Enable for Post-Processing-Channel 0

◆ EN_PP_MAP1

__IOM uint32_t EN_PP_MAP1

[15..15] Mapping Enable for Post-Processing-Channel 1

◆ EN_PP_MAP2

__IOM uint32_t EN_PP_MAP2

[23..23] Mapping Enable for Post-Processing-Channel 2

◆ EN_PP_MAP3

__IOM uint32_t EN_PP_MAP3

[31..31] Mapping Enable for Post-Processing-Channel 3

◆ EN_PP_MAP4

__IOM uint32_t EN_PP_MAP4

[7..7] Mapping Enable for Post-Processing-Channel 4

◆ EN_PP_MAP5

__IOM uint32_t EN_PP_MAP5

[15..15] Mapping Enable for Post-Processing-Channel 5

◆ EN_PP_MAP6

__IOM uint32_t EN_PP_MAP6

[23..23] Mapping Enable for Post-Processing-Channel 6

◆ EN_PP_MAP7

__IOM uint32_t EN_PP_MAP7

[31..31] Mapping Enable for Post-Processing-Channel 7

◆ EOC

[7..7] ADC1 End of Conversion (software mode)

◆ EoC_FAIL

__IOM uint32_t EoC_FAIL

[6..6] Fail of ADC End of Conversion Signal

◆ EoC_FAIL_CLR

__OM uint32_t EoC_FAIL_CLR

[4..4] Fail of ADC End of Conversion Signal Clear

◆ ESM_0

__IOM uint32_t ESM_0

[13..0] Channel Sequence for Exceptional Sequence Measurement (ESM)

◆ ESM_ACTIVE

__IM uint32_t ESM_ACTIVE

[10..10] ADC1 ESM active

◆ ESM_EN

__IOM uint32_t ESM_EN

[30..30] Enable for Exceptional Sequence Measurement Trigger Event

◆ ESM_IEN

__IOM uint32_t ESM_IEN

[17..17] Exceptional Sequence Measurement (ESM) Interrupt Enable

◆ ESM_IS

__IOM uint32_t ESM_IS

[17..17] Exceptional Sequence Measurement (ESM) Status

◆ ESM_ISC

__OM uint32_t ESM_ISC

[17..17] Exceptional Sequence Measurement (ESM) Status Clear

◆ ESM_STS

__IOM uint32_t ESM_STS

[31..31] Exceptional Sequence Measurement is finished

◆ 

union { ... } FILT_OUT0

◆ 

union { ... } FILT_OUT1

◆ 

union { ... } FILT_OUT10

◆ 

union { ... } FILT_OUT11

◆ 

union { ... } FILT_OUT12

◆ 

union { ... } FILT_OUT13

◆ 

union { ... } FILT_OUT2

◆ 

union { ... } FILT_OUT3

◆ 

union { ... } FILT_OUT4

◆ 

union { ... } FILT_OUT5

◆ 

union { ... } FILT_OUT6

◆ 

union { ... } FILT_OUT7

◆ 

union { ... } FILT_OUT8

◆ 

union { ... } FILT_OUT9

◆ FILT_OUT_CH0

__IM uint32_t FILT_OUT_CH0

[11..0] ADC or filter output value channel 0

◆ FILT_OUT_CH1

__IM uint32_t FILT_OUT_CH1

[11..0] ADC or filter output value channel 1

◆ FILT_OUT_CH10

__IM uint32_t FILT_OUT_CH10

[11..0] ADC or filter output value channel 10

◆ FILT_OUT_CH11

__IM uint32_t FILT_OUT_CH11

[11..0] ADC or filter output value channel 11

◆ FILT_OUT_CH12

__IM uint32_t FILT_OUT_CH12

[11..0] ADC or filter output value channel 12

◆ FILT_OUT_CH13

__IM uint32_t FILT_OUT_CH13

[11..0] ADC or filter output value channel 13

◆ FILT_OUT_CH2

__IM uint32_t FILT_OUT_CH2

[11..0] ADC or filter output value channel 2

◆ FILT_OUT_CH3

__IM uint32_t FILT_OUT_CH3

[11..0] ADC or filter output value channel 3

◆ FILT_OUT_CH4

__IM uint32_t FILT_OUT_CH4

[11..0] ADC or filter output value channel 4

◆ FILT_OUT_CH5

__IM uint32_t FILT_OUT_CH5

[11..0] ADC or filter output value channel 5

◆ FILT_OUT_CH6

__IM uint32_t FILT_OUT_CH6

[11..0] ADC or filter output value channel 6

◆ FILT_OUT_CH7

__IM uint32_t FILT_OUT_CH7

[11..0] ADC or filter output value channel 7

◆ FILT_OUT_CH8

__IM uint32_t FILT_OUT_CH8

[11..0] ADC or filter output value channel 8

◆ FILT_OUT_CH9

__IM uint32_t FILT_OUT_CH9

[11..0] ADC or filter output value channel 9

◆ FILT_OUT_EIM

__IM uint32_t FILT_OUT_EIM

[11..0] ADC or filter output value for last EIM measurement

◆ FILT_OUT_SEL_13_0

__IOM uint32_t FILT_OUT_SEL_13_0

[13..0] Output Filter Selection for Channels 0 to 13

◆ 

union { ... } FILT_OUTEIM

◆ 

union { ... } FILT_UPLO_CTRL

◆ 

union { ... } FILTCOEFF0_13

◆ FUL_PP_CH0_EN

__IOM uint32_t FUL_PP_CH0_EN

[0..0] Upper and lower threshold IIR filter enable Post-Processing-Channel 0

◆ FUL_PP_CH1_EN

__IOM uint32_t FUL_PP_CH1_EN

[1..1] Upper and lower threshold IIR filter enable Post-Processing-Channel 1

◆ FUL_PP_CH2_EN

__IOM uint32_t FUL_PP_CH2_EN

[2..2] Upper and lower threshold IIR filter enable Post-Processing-Channel 2

◆ FUL_PP_CH3_EN

__IOM uint32_t FUL_PP_CH3_EN

[3..3] Upper and lower threshold IIR filter enable Post-Processing-Channel 3

◆ FUL_PP_CH4_EN

__IOM uint32_t FUL_PP_CH4_EN

[4..4] Upper and lower threshold IIR filter enable Post-Processing-Channel 4

◆ FUL_PP_CH5_EN

__IOM uint32_t FUL_PP_CH5_EN

[5..5] Upper and lower threshold IIR filter enable Post-Processing-Channel 5

◆ FUL_PP_CH6_EN

__IOM uint32_t FUL_PP_CH6_EN

[6..6] Upper and lower threshold IIR filter enable Post-Processing-Channel 6

◆ FUL_PP_CH7_EN

__IOM uint32_t FUL_PP_CH7_EN

[7..7] Upper and lower threshold IIR filter enable Post-Processing-Channel 7

◆ HYST_LO_DCH1

__IOM uint32_t HYST_LO_DCH1

[4..3] Post-Processing-Channel 4 lower hysteresis

◆ HYST_LO_PP0

__IOM uint32_t HYST_LO_PP0

[4..3] Post-Processing-Channel 0 lower hysteresis

◆ HYST_LO_PP1

__IOM uint32_t HYST_LO_PP1

[12..11] Post-Processing-Channel 1 lower hysteresis

◆ HYST_LO_PP2

__IOM uint32_t HYST_LO_PP2

[20..19] Post-Processing-Channel 2 lower hysteresis

◆ HYST_LO_PP3

__IOM uint32_t HYST_LO_PP3

[28..27] Post-Processing-Channel 3 lower hysteresis

◆ HYST_LO_PP4

__IOM uint32_t HYST_LO_PP4

[4..3] Post-Processing-Channel 4 lower hysteresis

◆ HYST_LO_PP5

__IOM uint32_t HYST_LO_PP5

[12..11] Post-Processing-Channel 5 lower hysteresis

◆ HYST_LO_PP6

__IOM uint32_t HYST_LO_PP6

[20..19] Channel 6 lower hysteresis

◆ HYST_LO_PP7

__IOM uint32_t HYST_LO_PP7

[28..27] Post-Processing-Channel 7 lower hysteresis

◆ HYST_UP_DCH1

__IOM uint32_t HYST_UP_DCH1

[4..3] Post-Processing-Channel 4 upper hysteresis

◆ HYST_UP_PP0

__IOM uint32_t HYST_UP_PP0

[4..3] Post-Processing-Channel 0 upper hysteresis

◆ HYST_UP_PP1

__IOM uint32_t HYST_UP_PP1

[12..11] Post-Processing-Channel 1 upper hysteresis

◆ HYST_UP_PP2

__IOM uint32_t HYST_UP_PP2

[20..19] Post-Processing-Channel 2 upper hysteresis

◆ HYST_UP_PP3

__IOM uint32_t HYST_UP_PP3

[28..27] Post-Processing-Channel 3 upper hysteresis

◆ HYST_UP_PP4

__IOM uint32_t HYST_UP_PP4

[4..3] Post-Processing-Channel 4 upper hysteresis

◆ HYST_UP_PP5

__IOM uint32_t HYST_UP_PP5

[12..11] Post-Processing-Channel 5 upper hysteresis

◆ HYST_UP_PP6

__IOM uint32_t HYST_UP_PP6

[20..19] Post-Processing-Channel 6 upper hysteresis

◆ HYST_UP_PP7

__IOM uint32_t HYST_UP_PP7

[28..27] Post-Processing-Channel 7 upper hysteresis

◆ IIR_CH0_IEN

__IOM uint32_t IIR_CH0_IEN

[0..0] ADC1 IIR-Filter-Channel 0 Interrupt Enable

◆ IIR_CH0_IS

__IOM uint32_t IIR_CH0_IS

[0..0] ADC1 IIR-Filter-Channel 0 Interrupt Status

◆ IIR_CH0_ISC

__OM uint32_t IIR_CH0_ISC

[0..0] ADC1 IIR-Filter-Channel 0 Interrupt Status Clear

◆ IIR_CH10_IEN

__IOM uint32_t IIR_CH10_IEN

[10..10] ADC1 IIR-Filter-Channel 10 Interrupt Enable

◆ IIR_CH10_IS

__IOM uint32_t IIR_CH10_IS

[10..10] ADC1 IIR-Filter-Channel 10 Interrupt Status

◆ IIR_CH10_ISC

__OM uint32_t IIR_CH10_ISC

[10..10] ADC1 IIR-Filter-Channel 10 Interrupt Status Clear

◆ IIR_CH11_IEN

__IOM uint32_t IIR_CH11_IEN

[11..11] ADC1 IIR-Filter-Channel 11 Interrupt Enable

◆ IIR_CH11_IS

__IOM uint32_t IIR_CH11_IS

[11..11] ADC1 IIR-Filter-Channel 11 Interrupt Status

◆ IIR_CH11_ISC

__OM uint32_t IIR_CH11_ISC

[11..11] ADC1 IIR-Filter-Channel 11 Interrupt Status Clear

◆ IIR_CH12_IEN

__IOM uint32_t IIR_CH12_IEN

[12..12] ADC1 IIR-Filter-Channel 12 Interrupt Enable

◆ IIR_CH12_IS

__IOM uint32_t IIR_CH12_IS

[12..12] ADC1 IIR-Filter-Channel 12 Interrupt Status

◆ IIR_CH12_ISC

__OM uint32_t IIR_CH12_ISC

[12..12] ADC1 IIR-Filter-Channel 12 Interrupt Status Clear

◆ IIR_CH13_IEN

__IOM uint32_t IIR_CH13_IEN

[13..13] ADC1 IIR-Filter-Channel 13 Interrupt Enable

◆ IIR_CH13_IS

__IOM uint32_t IIR_CH13_IS

[13..13] ADC1 IIR-Filter-Channel 13 Interrupt Status

◆ IIR_CH13_ISC

__OM uint32_t IIR_CH13_ISC

[13..13] ADC1 IIR-Filter-Channel 13 Interrupt Status Clear

◆ IIR_CH2_IEN

__IOM uint32_t IIR_CH2_IEN

[2..2] ADC1 IIR-Filter-Channel 2 Interrupt Enable

◆ IIR_CH2_IS

__IOM uint32_t IIR_CH2_IS

[2..2] ADC1 IIR-Filter-Channel 2 Interrupt Status

◆ IIR_CH2_ISC

__OM uint32_t IIR_CH2_ISC

[2..2] ADC1 IIR-Filter-Channel 2 Interrupt Status Clear

◆ IIR_CH3_IEN

__IOM uint32_t IIR_CH3_IEN

[3..3] ADC1 IIR-Filter-Channel 3 Interrupt Enable

◆ IIR_CH3_IS

__IOM uint32_t IIR_CH3_IS

[3..3] ADC1 IIR-Filter-Channel 3 Interrupt Status

◆ IIR_CH3_ISC

__OM uint32_t IIR_CH3_ISC

[3..3] ADC1 IIR-Filter-Channel 3 Interrupt Status Clear

◆ IIR_CH4_IEN

__IOM uint32_t IIR_CH4_IEN

[4..4] ADC1 IIR-Filter-Channel 4 Interrupt Enable

◆ IIR_CH4_IS

__IOM uint32_t IIR_CH4_IS

[4..4] ADC1 IIR-Filter-Channel 4 Interrupt Status

◆ IIR_CH4_ISC

__OM uint32_t IIR_CH4_ISC

[4..4] ADC1 IIR-Filter-Channel 4 Interrupt Status Clear

◆ IIR_CH5_IEN

__IOM uint32_t IIR_CH5_IEN

[5..5] ADC1 IIR-Filter-Channel 5 Interrupt Enable

◆ IIR_CH5_IS

__IOM uint32_t IIR_CH5_IS

[5..5] ADC1 IIR-Filter-Channel 5 Interrupt Status

◆ IIR_CH5_ISC

__OM uint32_t IIR_CH5_ISC

[5..5] ADC1 IIR-Filter-Channel 5 Interrupt Status Clear

◆ IIR_CH6_IEN

__IOM uint32_t IIR_CH6_IEN

[6..6] ADC1 IIR-Filter-Channel 6 Interrupt Enable

◆ IIR_CH6_IS

__IOM uint32_t IIR_CH6_IS

[6..6] ADC1 IIR-Filter-Channel 6 Interrupt Status

◆ IIR_CH6_ISC

__OM uint32_t IIR_CH6_ISC

[6..6] ADC1 IIR-Filter-Channel 6 Interrupt Status Clear

◆ IIR_CH7_IEN

__IOM uint32_t IIR_CH7_IEN

[7..7] ADC1 IIR-Filter-Channel 7 Interrupt Enable

◆ IIR_CH7_IS

__IOM uint32_t IIR_CH7_IS

[7..7] ADC1 IIR-Filter-Channel 7 Interrupt Status

◆ IIR_CH7_ISC

__OM uint32_t IIR_CH7_ISC

[7..7] ADC1 IIR-Filter-Channel 7 Interrupt Status Clear

◆ IIR_CH8_IEN

__IOM uint32_t IIR_CH8_IEN

[8..8] ADC1 IIR-Filter-Channel 8 Interrupt Enable

◆ IIR_CH8_IS

__IOM uint32_t IIR_CH8_IS

[8..8] ADC1 IIR-Filter-Channel 8 Interrupt Status

◆ IIR_CH8_ISC

__OM uint32_t IIR_CH8_ISC

[8..8] ADC1 IIR-Filter-Channel 8 Interrupt Status Clear

◆ IIR_CH9_IEN

__IOM uint32_t IIR_CH9_IEN

[9..9] ADC1 IIR-Filter-Channel 9 Interrupt Enable

◆ IIR_CH9_IS

__IOM uint32_t IIR_CH9_IS

[9..9] ADC1 IIR-Filter-Channel 9 Interrupt Status

◆ IIR_CH9_ISC

__OM uint32_t IIR_CH9_ISC

[9..9] ADC1 IIR-Filter-Channel 9 Interrupt Status Clear

◆ 

union { ... } IRQCLR_1

◆ 

union { ... } IRQCLR_2

◆ 

union { ... } IRQEN_1

◆ 

union { ... } IRQEN_2

◆ 

union { ... } IRQS_1

◆ 

union { ... } IRQS_2

◆ MAX_TIME [1/2]

__IOM uint32_t MAX_TIME

[7..0] Maximum Time in Software Mode

◆  [2/2]

union { ... } MAX_TIME

◆ MCM_PD_N

__IOM uint32_t MCM_PD_N

[0..0] Power Down Signal for MCM

◆ MCM_RDY

__IM uint32_t MCM_RDY

[7..7] Ready Signal for MCM after Power On or Reset

◆ 

union { ... } MMODE0_7

◆ MMODE_0

__IOM uint32_t MMODE_0

[1..0] Measurement mode Post-Processing-Channel 0

◆ MMODE_1

__IOM uint32_t MMODE_1

[3..2] Measurement mode Post-Processing-Channel 1

◆ MMODE_2

__IOM uint32_t MMODE_2

[5..4] Measurement mode Post-Processing-Channel 2

◆ MMODE_3

__IOM uint32_t MMODE_3

[7..6] Measurement mode Post-Processing-Channel 3

◆ MMODE_4

__IOM uint32_t MMODE_4

[9..8] Measurement mode Post-Processing-Channel 4

◆ MMODE_5

__IOM uint32_t MMODE_5

[11..10] Measurement mode Post-Processing-Channel 5

◆ MMODE_6

__IOM uint32_t MMODE_6

[13..12] Measurement mode Post-Processing-Channel 6

◆ MMODE_7

__IOM uint32_t MMODE_7

[15..14] Measurement mode Post-Processing-Channel 7

◆ MMODE_D1

__IOM uint32_t MMODE_D1

[25..24] Measurement mode Differential Channel 1

◆ OF0

[18..18] Overrun Flag

◆ OF1

[18..18] Overrun Flag

◆ OF10

__IM uint32_t OF10

[18..18] Overrun Flag

◆ OF11

__IM uint32_t OF11

[18..18] Overrun Flag

◆ OF12

__IM uint32_t OF12

[18..18] Overrun Flag

◆ OF13

__IM uint32_t OF13

[18..18] Overrun Flag

◆ OF2

[18..18] Overrun Flag

◆ OF3

[18..18] Overrun Flag

◆ OF4

[18..18] Overrun Flag

◆ OF5

[18..18] Overrun Flag

◆ OF6

[18..18] Overrun Flag

◆ OF7

[18..18] Overrun Flag

◆ OF8

[18..18] Overrun Flag

◆ OF9

[18..18] Overrun Flag

◆ OF_EIM

__IM uint32_t OF_EIM

[18..18] Overrun Flag

◆ OFFSET_DAC

__IOM uint32_t OFFSET_DAC

[12..8] Set the Value of the Offset Calibration DAC

◆ OFFSET_SHIFT

__IOM uint32_t OFFSET_SHIFT

[2..0] Set the Value of the Offset Shift DAC

◆ 

union { ... } OFFSETCALIB

◆ PD_N

[0..0] ADC1 Power Down Signal

◆ PP_CH0_LO_IEN

__IOM uint32_t PP_CH0_LO_IEN

[0..0] ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt Enable

◆ PP_CH0_LO_IS

__IOM uint32_t PP_CH0_LO_IS

[0..0] ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt Status

◆ PP_CH0_LO_ISC

__OM uint32_t PP_CH0_LO_ISC

[0..0] ADC1 Post-Processing-Channel 0 Lower Threshold Interrupt Status Clear

◆ PP_CH0_LO_STS

__IM uint32_t PP_CH0_LO_STS

[0..0] ADC1 Post-Processing-Channel 0 Lower Threshold Status

◆ PP_CH0_LOW

__IOM uint32_t PP_CH0_LOW

[7..0] Post-Processing-Channel 0 lower trigger level

◆ PP_CH0_UP

__IOM uint32_t PP_CH0_UP

[7..0] Post-Processing-Channel 0 upper trigger level

◆ PP_CH0_UP_IEN

__IOM uint32_t PP_CH0_UP_IEN

[16..16] ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Enable

◆ PP_CH0_UP_IS

__IOM uint32_t PP_CH0_UP_IS

[16..16] ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Status

◆ PP_CH0_UP_ISC

__OM uint32_t PP_CH0_UP_ISC

[16..16] ADC1 Post-Processing-Channel 0 Upper Threshold Interrupt Status Clear

◆ PP_CH0_UP_STS

__IM uint32_t PP_CH0_UP_STS

[16..16] ADC1 Post-Processing-Channel 0 Upper Threshold Status

◆ PP_CH1_LOW

__IOM uint32_t PP_CH1_LOW

[15..8] Post-Processing-Channel 1 lower trigger level

◆ PP_CH1_UP

__IOM uint32_t PP_CH1_UP

[15..8] Post-Processing-Channel 1 upper trigger level

◆ PP_CH2_LO_IEN

__IOM uint32_t PP_CH2_LO_IEN

[2..2] ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Enable

◆ PP_CH2_LO_IS

__IOM uint32_t PP_CH2_LO_IS

[2..2] ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Status

◆ PP_CH2_LO_ISC

__OM uint32_t PP_CH2_LO_ISC

[2..2] ADC1 Post-Processing-Channel 2 Lower Threshold Interrupt Status Clear

◆ PP_CH2_LO_STS

__IM uint32_t PP_CH2_LO_STS

[2..2] ADC1 Post-Processing-Channel 2 Lower Threshold Status

◆ PP_CH2_LOW

__IOM uint32_t PP_CH2_LOW

[23..16] Post-Processing-Channel 2 lower trigger level

◆ PP_CH2_UP

__IOM uint32_t PP_CH2_UP

[23..16] Post-Processing-Channel 2 upper trigger level

◆ PP_CH2_UP_IEN

__IOM uint32_t PP_CH2_UP_IEN

[18..18] ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Enable

◆ PP_CH2_UP_IS

__IOM uint32_t PP_CH2_UP_IS

[18..18] ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Status

◆ PP_CH2_UP_ISC

__OM uint32_t PP_CH2_UP_ISC

[18..18] ADC1 Post-Processing-Channel 2 Upper Threshold Interrupt Status Clear

◆ PP_CH2_UP_STS

__IM uint32_t PP_CH2_UP_STS

[18..18] ADC1 Post-Processing-Channel 2 Upper Threshold Status

◆ PP_CH3_LO_IEN

__IOM uint32_t PP_CH3_LO_IEN

[3..3] ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt Enable

◆ PP_CH3_LO_IS

__IOM uint32_t PP_CH3_LO_IS

[3..3] ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt Status

◆ PP_CH3_LO_ISC

__OM uint32_t PP_CH3_LO_ISC

[3..3] ADC1 Post-Processing-Channel 3 Lower Threshold Interrupt Status Clear

◆ PP_CH3_LO_STS

__IM uint32_t PP_CH3_LO_STS

[3..3] ADC1 Post-Processing-Channel 3 Lower Threshold Status

◆ PP_CH3_LOW

__IOM uint32_t PP_CH3_LOW

[31..24] Post-Processing-Channel 3 lower trigger level

◆ PP_CH3_UP

__IOM uint32_t PP_CH3_UP

[31..24] Post-Processing-Channel 3 upper trigger level

◆ PP_CH3_UP_IEN

__IOM uint32_t PP_CH3_UP_IEN

[19..19] ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Enable

◆ PP_CH3_UP_IS

__IOM uint32_t PP_CH3_UP_IS

[19..19] ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Status

◆ PP_CH3_UP_ISC

__OM uint32_t PP_CH3_UP_ISC

[19..19] ADC1 Post-Processing-Channel 3 Upper Threshold Interrupt Status Clear

◆ PP_CH3_UP_STS

__IM uint32_t PP_CH3_UP_STS

[19..19] ADC1 Post-Processing-Channel 3 Upper Threshold Status

◆ PP_CH4_LO_IEN

__IOM uint32_t PP_CH4_LO_IEN

[4..4] ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt Enable

◆ PP_CH4_LO_IS

__IOM uint32_t PP_CH4_LO_IS

[4..4] ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt Status

◆ PP_CH4_LO_ISC

__OM uint32_t PP_CH4_LO_ISC

[4..4] ADC1 Post-Processing-Channel 4 Lower Threshold Interrupt Status Clear

◆ PP_CH4_LO_STS

__IM uint32_t PP_CH4_LO_STS

[4..4] ADC1 Post-Processing-Channel 4 Lower Threshold Status

◆ PP_CH4_LOW

__IOM uint32_t PP_CH4_LOW

[7..0] Post-Processing-Channel 4 lower trigger level

◆ PP_CH4_UP

__IOM uint32_t PP_CH4_UP

[7..0] Post-Processing-Channel 4 upper trigger level

◆ PP_CH4_UP_IEN

__IOM uint32_t PP_CH4_UP_IEN

[20..20] ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Enable

◆ PP_CH4_UP_IS

__IOM uint32_t PP_CH4_UP_IS

[20..20] ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Status

◆ PP_CH4_UP_ISC

__OM uint32_t PP_CH4_UP_ISC

[20..20] ADC1 Post-Processing-Channel 4 Upper Threshold Interrupt Status Clear

◆ PP_CH4_UP_STS

__IM uint32_t PP_CH4_UP_STS

[20..20] ADC1 Post-Processing-Channel 4 Upper Threshold Status

◆ PP_CH5_LO_IEN

__IOM uint32_t PP_CH5_LO_IEN

[5..5] ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt Enable

◆ PP_CH5_LO_IS

__IOM uint32_t PP_CH5_LO_IS

[5..5] ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt Status

◆ PP_CH5_LO_ISC

__OM uint32_t PP_CH5_LO_ISC

[5..5] ADC1 Post-Processing-Channel 5 Lower Threshold Interrupt Status Clear

◆ PP_CH5_LO_STS

__IM uint32_t PP_CH5_LO_STS

[5..5] ADC1 Post-Processing-Channel 5 Lower Threshold Status

◆ PP_CH5_LOW

__IOM uint32_t PP_CH5_LOW

[15..8] Post-Processing-Channel 5 lower trigger level

◆ PP_CH5_UP

__IOM uint32_t PP_CH5_UP

[15..8] Post-Processing-Channel 5 upper trigger level

◆ PP_CH5_UP_IEN

__IOM uint32_t PP_CH5_UP_IEN

[21..21] ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Enable

◆ PP_CH5_UP_IS

__IOM uint32_t PP_CH5_UP_IS

[21..21] ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Status

◆ PP_CH5_UP_ISC

__OM uint32_t PP_CH5_UP_ISC

[21..21] ADC1 Post-Processing-Channel 5 Upper Threshold Interrupt Status Clear

◆ PP_CH5_UP_STS

__IM uint32_t PP_CH5_UP_STS

[21..21] ADC1 Post-Processing-Channel 5 Upper Threshold Status

◆ PP_CH6_LO_IEN

__IOM uint32_t PP_CH6_LO_IEN

[6..6] ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt Enable

◆ PP_CH6_LO_IS

__IOM uint32_t PP_CH6_LO_IS

[6..6] ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt Status

◆ PP_CH6_LO_ISC

__OM uint32_t PP_CH6_LO_ISC

[6..6] ADC1 Post-Processing-Channel 6 Lower Threshold Interrupt Status Clear

◆ PP_CH6_LO_STS

__IM uint32_t PP_CH6_LO_STS

[6..6] ADC1 Post-Processing-Channel 6 Lower Threshold Status

◆ PP_CH6_LOW

__IOM uint32_t PP_CH6_LOW

[23..16] Post-Processing-Channel 6 lower trigger level

◆ PP_CH6_UP

__IOM uint32_t PP_CH6_UP

[23..16] Post-Processing-Channel 6upper trigger level

◆ PP_CH6_UP_IEN

__IOM uint32_t PP_CH6_UP_IEN

[22..22] ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Enable

◆ PP_CH6_UP_IS

__IOM uint32_t PP_CH6_UP_IS

[22..22] ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Status

◆ PP_CH6_UP_ISC

__OM uint32_t PP_CH6_UP_ISC

[22..22] ADC1 Post-Processing-Channel 6 Upper Threshold Interrupt Status Clear

◆ PP_CH6_UP_STS

__IM uint32_t PP_CH6_UP_STS

[22..22] ADC1 Post-Processing-Channel 6 Upper Threshold Status

◆ PP_CH7_LO_IEN

__IOM uint32_t PP_CH7_LO_IEN

[7..7] ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Enable

◆ PP_CH7_LO_IS

__IOM uint32_t PP_CH7_LO_IS

[7..7] ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Status

◆ PP_CH7_LO_ISC

__OM uint32_t PP_CH7_LO_ISC

[7..7] ADC1 Post-Processing-Channel 7 Lower Threshold Interrupt Status Clear

◆ PP_CH7_LO_STS

__IM uint32_t PP_CH7_LO_STS

[7..7] ADC1 Post-Processing-Channel 7 Lower Threshold Status

◆ PP_CH7_LOW

__IOM uint32_t PP_CH7_LOW

[31..24] Post-Processing-Channel 7 lower trigger level

◆ PP_CH7_UP

__IOM uint32_t PP_CH7_UP

[31..24] Post-Processing-Channel 7 upper trigger level

◆ PP_CH7_UP_IEN

__IOM uint32_t PP_CH7_UP_IEN

[23..23] ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Enable

◆ PP_CH7_UP_IS

__IOM uint32_t PP_CH7_UP_IS

[23..23] ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Status

◆ PP_CH7_UP_ISC

__OM uint32_t PP_CH7_UP_ISC

[23..23] ADC1 Post-Processing-Channel 7 Upper Threshold Interrupt Status Clear

◆ PP_CH7_UP_STS

__IM uint32_t PP_CH7_UP_STS

[23..23] ADC1 Post-Processing-Channel 7 Upper Threshold Status

◆ 

union { ... } PP_MAP0_3

◆ PP_MAP2

__IOM uint32_t PP_MAP2

[19..16] Mapping of Entry Channel to Post-Processing-Channel 2

◆ PP_MAP3

__IOM uint32_t PP_MAP3

[27..24] Mapping of Entry Channel to Post-Processing-Channel 3

◆ PP_MAP4

__IOM uint32_t PP_MAP4

[3..0] Mapping of Entry Channel to Post-Processing-Channel 4

◆ 

union { ... } PP_MAP4_7

◆ PP_MAP5

__IOM uint32_t PP_MAP5

[11..8] Mapping of Entry Channel to Post-Processing-Channel 5

◆ PP_MAP6

__IOM uint32_t PP_MAP6

[19..16] Mapping of Entry Channel to Post-Processing-Channel 6

◆ PP_MAP7

__IOM uint32_t PP_MAP7

[27..24] Mapping of Entry Channel to Post-Processing-Channel 7

◆ READY

__IM uint32_t READY

[4..4] HVADC Ready bit

◆ reg

(@ 0x00000000) ADC1 Control and Status Register

(@ 0x00000004) Sequencer Feedback Register

(@ 0x00000008) Channel Setting Bits for Exceptional Interrupt Measurement

(@ 0x0000000C) Channel Setting Bits for Exceptional Sequence Measurement

(@ 0x00000010) Maximum Time for Software Mode

(@ 0x00000014) Measurement Unit 1 Control Register 2

(@ 0x00000018) Measurement Unit 1 Control Register 3

(@ 0x0000001C) Measurement Unit 1 Control Register 5

(@ 0x00000020) Measurement Unit 1 Channel Enable Bits for Cycle 0-1

(@ 0x00000024) Measurement Unit 1 Channel Enable Bits for Cycle 2-3

(@ 0x00000028) Measurement Unit 1 Channel Enable Bits for Cycle 4-5

(@ 0x0000002C) Measurement Unit 1 Channel Enable Bits for Cycle 6-7

(@ 0x00000030) Measurement Unit 1 Channel Enable Bits for Cycle 8-9

(@ 0x00000034) Measurement Unit 1 Channel Enable Bits for Cycle 10-11

(@ 0x00000038) ADC1 Channel Mapping for Sequencer

(@ 0x0000003C) ADC1 Offset Calibration Register

(@ 0x00000040) Lower Comparator Trigger Level Post-Processing-Channel 0-3

(@ 0x00000044) Lower Comparator Trigger Level Post-Processing-Channel 4-7

(@ 0x00000048) Calibration for Channel 0 and 1

(@ 0x0000004C) Calibration for Channel 2 and 3

(@ 0x00000050) Calibration for Channel 4 and 5

(@ 0x00000054) Calibration for Channel 6 and 7

(@ 0x00000058) Calibration for Channel 8 and 9

(@ 0x0000005C) Calibration for Channel 10 and 11

(@ 0x00000060) Filter Coefficients Measurement Unit Channel 0-13

(@ 0x00000064) ADC1 Interrupt Status 1 Register

(@ 0x00000068) ADC1 Interrupt Enable 1 Register

(@ 0x0000006C) ADC1 Interrupt Status Clear 1 Register

(@ 0x00000070) ADC1 or Filter Output Channel 0

(@ 0x00000074) ADC1 or Filter Output Channel 1

(@ 0x00000078) ADC1 or Filter Output Channel 2

(@ 0x0000007C) ADC1 or Filter Output Channel 3

(@ 0x00000080) ADC1 or Filter Output Channel 4

(@ 0x00000084) ADC1 or Filter Output Channel 5

(@ 0x00000088) ADC1 or Filter Output Channel 6

(@ 0x0000008C) ADC1 or Filter Output Channel 7

(@ 0x00000090) ADC1 or Filter Output Channel 8

(@ 0x00000094) ADC1 or Filter Output Channel 9

(@ 0x00000098) ADC1 or Filter Output Channel 10

(@ 0x0000009C) ADC1 or Filter Output Channel 11

(@ 0x000000A0) ADC1 Differential Channel Output 1

(@ 0x000000B0) Upper And Lower Threshold Filter Enable

(@ 0x000000BC) ADC1 Status Register

(@ 0x000000C4) Lower Comparator Trigger Level Differential Channel 1

(@ 0x000000C8) Upper Comparator Trigger Level Post-Processing-Channel 0-3

(@ 0x000000CC) Upper Comparator Trigger Level Post-Processing-Channel 4-7

(@ 0x000000D4) Upper Comparator Trigger Level Differential Channel 1

(@ 0x000000D8) Lower Counter Trigger Level Post-Processing-Channel 0-3

(@ 0x000000DC) Lower Counter Trigger Level Post-Processing-Channel 4-7

(@ 0x000000E4) Lower Counter Trigger Level DifferentialChannel 1

(@ 0x000000E8) Upper Counter Trigger Level Post-Processing-Channel 0-3

(@ 0x000000EC) Upper Counter Trigger Level Post-Processing-Channel 4-7

(@ 0x000000F4) Upper Counter Trigger Level DifferentialChannel 1

(@ 0x000000F8) Overvoltage Measurement Mode of Post-Processing-Channel 0-7

(@ 0x000000FC) Measurement Unit 1 - Differential Unit Input Selection Register

(@ 0x00000100) ADC1 Interrupt Status 2 Register

(@ 0x00000104) ADC1 Status 2 Register

(@ 0x00000108) ADC1 Interrupt Status Clear 2 Register

(@ 0x0000010C) ADC1 Interrupt Enable 2 Register

(@ 0x00000110) ADC1 or Filter Output Channel 12

(@ 0x00000118) Post-Processing Mapping Channel 0-3

(@ 0x0000011C) Post-Processing Mapping Channel 4-7

(@ 0x00000120) ADC1 or Filter Output of EIM

(@ 0x00000124) ADC1 Status 1Register

(@ 0x00000128) ADC1 Status Clear 1 Register

(@ 0x00000130) Measurement Unit 1 Channel Enable Bits for Cycle 12-13

(@ 0x00000138) Calibration for Channel 12 and 13

(@ 0x00000140) ADC1 or Filter Output Channel 13

◆ RESERVED

__IM uint32_t RESERVED[3]

◆ RESERVED1

__IM uint32_t RESERVED1[2]

◆ RESERVED2

__IM uint32_t RESERVED2

◆ RESERVED3

__IM uint32_t RESERVED3

◆ RESERVED4

__IM uint32_t RESERVED4

◆ RESERVED5

__IM uint32_t RESERVED5

◆ RESERVED6

__IM uint32_t RESERVED6

◆ RESERVED7

__IM uint32_t RESERVED7

◆ RESERVED8

__IM uint32_t RESERVED8

◆ RESERVED9

__IM uint32_t RESERVED9

◆ RESET_PP_MAP0

__IOM uint32_t RESET_PP_MAP0

[6..6] Post-Processing Reset for Mapped Post-Processing-Channel 0

◆ RESET_PP_MAP1

__IOM uint32_t RESET_PP_MAP1

[14..14] Post-Processing Reset for Mapped Post-Processing-Channel 1

◆ RESET_PP_MAP2

__IOM uint32_t RESET_PP_MAP2

[22..22] Post-Processing Reset for Mapped Post-Processing-Channel 2

◆ RESET_PP_MAP3

__IOM uint32_t RESET_PP_MAP3

[30..30] Post-Processing Reset for Mapped Post-Processing-Channel 3

◆ RESET_PP_MAP4

__IOM uint32_t RESET_PP_MAP4

[6..6] Post-Processing Reset for Mapped Post-Processing-Channel 4

◆ RESET_PP_MAP5

__IOM uint32_t RESET_PP_MAP5

[14..14] Post-Processing Reset for Mapped Post-Processing-Channel 5

◆ RESET_PP_MAP6

__IOM uint32_t RESET_PP_MAP6

[22..22] Post-Processing Reset for Mapped Post-Processing-Channel 6

◆ RESET_PP_MAP7

__IOM uint32_t RESET_PP_MAP7

[30..30] Post-Processing Reset for Mapped Post-Processing-Channel 7

◆ SAMPLE_TIME_HVCH

__IOM uint32_t SAMPLE_TIME_HVCH

[12..8] Sample time of ADC1

◆ SAMPLE_TIME_LVCH

__IOM uint32_t SAMPLE_TIME_LVCH

[19..16] Sample time of ADC1

◆ SD_FEEDB_ON

__IOM uint32_t SD_FEEDB_ON

[31..31] Sigma Delta Feedback Loop

◆ SOC_JITTER

__IOM uint32_t SOC_JITTER

[17..16] Programs Soc Clock Jitter

◆ SOOC

[1..1] ADC1 Start of Offset Calibration (software mode)

◆ SOS

[2..2] ADC1 Start of Sampling/Conversion (software mode)

◆ SQ0

[13..0] Sequence 0 channel enable

◆ 

union { ... } SQ0_1

◆ SQ1

[29..16] Sequence 1 channel enable

◆ SQ10

[13..0] Sequence 10 channel enable

◆ 

union { ... } SQ10_11

◆ SQ11

[29..16] Sequence 11 channel enable

◆ SQ12

[13..0] Sequence 12 channel enable

◆ 

union { ... } SQ12_13

◆ SQ13

[29..16] Sequence 13 channel enable

◆ SQ2

[13..0] Sequence 2 channel enable

◆ 

union { ... } SQ2_3

◆ SQ3

[29..16] Sequence 3 channel enable

◆ SQ4

[13..0] Sequence 4 channel enable

◆ 

union { ... } SQ4_5

◆ SQ5

[29..16] Sequence 5 channel enable

◆ SQ6

[13..0] Sequence 6 channel enable

◆ 

union { ... } SQ6_7

◆ SQ7

[29..16] Sequence 7 channel enable

◆ SQ8

[13..0] Sequence 8 channel enable

◆ 

union { ... } SQ8_9

◆ SQ9

[29..16] Sequence 9 channel enable

◆ SQ_CH12_MAP

__IOM uint32_t SQ_CH12_MAP

[12..12] ADC mapping to CH12

◆ SQ_CH5_MAP

__IOM uint32_t SQ_CH5_MAP

[5..5] ADC mapping to CH5

◆ SQ_CH6_MAP

__IOM uint32_t SQ_CH6_MAP

[6..6] ADC mapping to CH6

◆ 

union { ... } SQ_CH_MAP

◆ SQ_FB [1/2]

__IM uint32_t SQ_FB

[4..0] Current Sequence that caused software mode

◆  [2/2]

union { ... } SQ_FB

◆ SQ_STOP

__IM uint32_t SQ_STOP

[8..8] ADC1 Sequencer Stop Signal for DPP

◆ SQx

[14..11] Current Active ADC1 Sequence

◆ 

union { ... } STATUS

◆ STRTUP_DIS

__IOM uint32_t STRTUP_DIS

[18..18] DPP1 Startup Disable

◆ 

union { ... } STS_1

◆ 

union { ... } STS_2

◆ 

union { ... } STSCLR_1

◆ SW_CH_SEL

__IOM uint32_t SW_CH_SEL

[11..8] Channel for software mode

◆ SW_MODE

__IOM uint32_t SW_MODE

[1..1] Flag to enter SW Mode

◆ 

union { ... } TH0_3_LOWER

◆ 

union { ... } TH0_3_UPPER

◆ 

union { ... } TH4_7_LOWER

◆ 

union { ... } TH4_7_UPPER

◆ uint32_t

__IM uint32_t

◆ VF0

[17..17] Valid Flag

◆ VF1

[17..17] Valid Flag

◆ VF10

__IM uint32_t VF10

[17..17] Valid Flag

◆ VF11

__IM uint32_t VF11

[17..17] Valid Flag

◆ VF12

__IM uint32_t VF12

[17..17] Valid Flag

◆ VF13

__IM uint32_t VF13

[17..17] Valid Flag

◆ VF2

[17..17] Valid Flag

◆ VF3

[17..17] Valid Flag

◆ VF4

[17..17] Valid Flag

◆ VF5

[17..17] Valid Flag

◆ VF6

[17..17] Valid Flag

◆ VF7

[17..17] Valid Flag

◆ VF8

[17..17] Valid Flag

◆ VF9

[17..17] Valid Flag

◆ VF_EIM

__IM uint32_t VF_EIM

[17..17] Valid Flag

◆ VS_IEN

__IOM uint32_t VS_IEN

[1..1] ADC1 IIR-Filter-Channel 1 Interrupt Enable

◆ VS_IS

__IOM uint32_t VS_IS

[1..1] ADC1 IIR-Filter-Channel 1 Interrupt Status

◆ VS_ISC

__OM uint32_t VS_ISC

[1..1] ADC1 IIR-Filter-Channel 1 Interrupt Status Clear

◆ VS_LO_IEN

__IOM uint32_t VS_LO_IEN

[1..1] ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Enable

◆ VS_LO_IS

__IOM uint32_t VS_LO_IS

[1..1] ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Status

◆ VS_LO_ISC

__OM uint32_t VS_LO_ISC

[1..1] ADC1 Post-Processing-Channel 1 Lower Threshold Interrupt Status Clear

◆ VS_LO_STS

__IM uint32_t VS_LO_STS

[1..1] ADC1 Post-Processing-Channel 1 Lower Threshold Status

◆ VS_UP_IEN

__IOM uint32_t VS_UP_IEN

[17..17] ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Enable

◆ VS_UP_IS

__IOM uint32_t VS_UP_IS

[17..17] ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Status

◆ VS_UP_ISC

__OM uint32_t VS_UP_ISC

[17..17] ADC1 Post-Processing-Channel 1 Upper Threshold Interrupt Status Clear

◆ VS_UP_STS

__IM uint32_t VS_UP_STS

[17..17] ADC1 Post-Processing-Channel 1 Upper Threshold Status

◆ WFR0

[16..16] Wait for Read Mode

◆ WFR1

[16..16] Wait for Read Mode

◆ WFR10

__IOM uint32_t WFR10

[16..16] Wait for Read Mode

◆ WFR11

__IOM uint32_t WFR11

[16..16] Wait for Read Mode

◆ WFR12

__IOM uint32_t WFR12

[16..16] Wait for Read Mode

◆ WFR13

__IOM uint32_t WFR13

[16..16] Wait for Read Mode

◆ WFR2

[16..16] Wait for Read Mode

◆ WFR3

[16..16] Wait for Read Mode

◆ WFR4

[16..16] Wait for Read Mode

◆ WFR5

[16..16] Wait for Read Mode

◆ WFR6

[16..16] Wait for Read Mode

◆ WFR7

[16..16] Wait for Read Mode

◆ WFR8

[16..16] Wait for Read Mode

◆ WFR9

[16..16] Wait for Read Mode

◆ WFR_EIM

__IOM uint32_t WFR_EIM

[16..16] Wait for Read Mode


The documentation for this struct was generated from the following file: