Infineon MOTIX™ MCU TLE985x Device Family SDK
scu.h
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39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** TS T&S **
45 ** JO Julia Ott **
46 ** BG Blandine Guillot **
47 ** VO Vanessa Ongaro **
48 *******************************************************************************/
49 
50 /*******************************************************************************
51 ** Revision Control History **
52 ********************************************************************************
53 ** V0.2.0: 2018-02-13, TS: Initial version of revision history **
54 ** V0.2.1: 2018-10-17, TS: WDTREL, WDTWINB, WDTCON initialization corrected **
55 ** MODPISEL3 initialization removed **
56 ** V0.2.2: 2019-01-28, TS: __STATIC_INLINE changed to INLINE **
57 ** Doxygen update **
58 ** Revision history moved from scu.c to scu.h **
59 ** SCU_EnterSleepMode, SCU_ClkInit, **
60 ** SCU_EnterStopMode functions updated **
61 ** SCU_WDT_Start, SCU_WDT_Stop and SCU_WDT_Service **
62 ** functions added **
63 ** Added #ifndef UNIT_TESTING_LV2 condition in **
64 ** SCU_EnterSleepMode for testability **
65 ** V0.2.3: 2019-03-18, TS: SCU_Init, SCU_ClkInit and SCU_EnterStopMode **
66 ** functions updated **
67 ** SCU_WDT_Start, SCU_WDT_Stop, SCU_System_Clock_Sel**
68 ** functions updated **
69 ** VCO_BYP and OSC_DISC masks and initial values **
70 ** macros added **
71 ** V0.2.4: 2019-06-17, JO: In SCU_ClkInit: Removed setting APCLK_SET to **
72 ** zero because this register is cleared by **
73 ** Hardware, updated comment **
74 ** In SCU_Init: Removed unused initialization of **
75 ** SCU->MODPISEL3 **
76 ** In SCU_EnterSleepMode: Set LIN to sleep mode **
77 ** only if the LIN module is enabled **
78 ** V0.2.5: 2020-03-02, BG: Updated revision history format **
79 ** V0.2.6: 2020-07-30, JO: EP-426: Modified SCU_ClkInit to apply XTAL **
80 ** setting correctly (independent from compiler **
81 ** optimization) **
82 ** V0.2.7: 2020-08-10, JO: Updated function SCU_ClkInit() to use internal **
83 ** oscillator instead of PLL output if configured **
84 ** in Config Wizard (define SCU_USE_PLL) **
85 ** V0.2.8: 2020-08-10, JO: EP-429: Added function SCU_RecoverPllLossOfLock **
86 ** V0.2.9: 2020-12-04, JO: EP-635: Corrected switching to LP_CLK in **
87 ** functions SCU_ClkInit and SCU_EnterStopMode **
88 ** V0.3.0: 2021-08-24, VO: EP-825: Added clearing of GPIO_WAKE_STATUS when **
89 ** entering stop mode **
90 ** V0.3.1: 2022-01-21, JO: EP-934: Updated copyright and branding **
91 ** V0.4.0: 2023-06-30, JO: EP-655: Removed PLL and related functions, **
92 ** Updated SCU_ClkInit **
93 ** V0.4.1: 2023-08-21, BG: EP-1195: Removed warning with ARMCC V6 **
94 ** V0.4.2: 2023-08-28, JO: EP-435: Removed ARMCC v6 compiler warnings **
95 *******************************************************************************/
96 
97 #ifndef SCU_H
98 #define SCU_H
99 
100 /*******************************************************************************
101 ** Includes **
102 *******************************************************************************/
103 #include "tle985x.h"
104 #include "types.h"
105 #include "sfr_access.h"
106 #include "bootrom.h"
107 
108 /*******************************************************************************
109 ** Global Macro Definitions **
110 *******************************************************************************/
112 #define PASSWD_Open (0x98U)
114 #define PASSWD_Close (0xA8U)
115 
117 #define NVM_PASSWORD_BOOT (0U)
119 #define NVM_PASSWORD_CODE (1U)
121 #define NVM_PASSWORD_DATA (2U)
122 
124 #define PROTECTION_CLEAR (1U)
126 #define PROTECTION_SET (0U)
127 
129 #define PBA0_Div_1 (0U)
131 #define PBA0_Div_2 (1U)
132 
134 #define VCO_BYP_Msk (0x80008U)
136 #define VCO_BYP_0 (0x80000U)
138 #define OSC_DISC_Msk (0x40004U)
140 #define OSC_DISC_0 (0x40000U)
141 
142 /*******************************************************************************
143 ** Global Type Definitions **
144 *******************************************************************************/
148 typedef enum
149 {
150  Mod_ADC1 = 0x00,
151  Mod_SSC1 = 0x01,
152  Mod_CCU = 0x02,
153  Mod_Timer2 = 0x03,
154  Mod_GPT12 = 0x04,
155  Mod_SSC2 = 0x08,
156  Mod_Timer21 = 0x0A
158 
162 typedef enum
163 {
167 
171 typedef enum
172 {
176  SCU_VTOR_UCODE = 3
178 
179 /*******************************************************************************
180 ** Global Function Declarations **
181 *******************************************************************************/
186 void SCU_Init(void);
187 
192 void SCU_ClkInit(void);
193 
216 
242 void SCU_EnterStopMode(void);
243 
261 
262 /*******************************************************************************
263 ** Inline Function Declarations **
264 *******************************************************************************/
279 INLINE void SCU_Disable_Module(TScu_Mod Module);
280 
295 INLINE void SCU_Enable_Module(TScu_Mod Module);
296 
311 INLINE void SCU_WDT_Start(void);
312 
326 INLINE void SCU_WDT_Stop(void);
327 
341 INLINE void SCU_WDT_Service(void);
342 
355 INLINE void SCU_OpenPASSWD(void);
356 
369 INLINE void SCU_ClosePASSWD(void);
370 
386 
402 
420 
433 INLINE void SCU_APCLK1_Sts_Clr(void);
434 
447 INLINE void SCU_APCLK2_Sts_Clr(void);
448 
461 INLINE void SCU_APCLK3_Sts_Clr(void);
462 
475 INLINE void SCUPM_CLKWDT_PD_N_En(void);
476 
489 INLINE void SCUPM_CLKWDT_PD_N_Dis(void);
490 
506 
522 
538 
554 
570 
586 
602 
618 
631 INLINE void CPU_DeepSleep_Sel(void);
632 
646 INLINE void CPU_SleepOnExit_Sel(void);
647 
648 /*******************************************************************************
649 ** Inline Function Definitions **
650 *******************************************************************************/
652 {
653  Field_Mod32(&SCU->PMCON.reg, (uint8)Module, (uint32)1u << (uint8)Module, 1u);
654 }
655 
657 {
658  Field_Mod32(&SCU->PMCON.reg, (uint8)Module, (uint32)1u << (uint8)Module, 0u);
659 }
660 
662 {
663  SCU_OpenPASSWD();
665  SCU_ClosePASSWD();
666 }
667 
669 {
670  SCU_OpenPASSWD();
672  SCU_ClosePASSWD();
673 }
674 
676 {
678 }
679 
681 {
682  Field_Wrt32all(&SCU->PASSWD.reg, (uint8)PASSWD_Open);
683 }
684 
686 {
687  Field_Wrt32all(&SCU->PASSWD.reg, (uint8)PASSWD_Close);
688 }
689 
691 {
692  SCU_OpenPASSWD();
694  SCU_ClosePASSWD();
695 }
696 
698 {
699  SCU_OpenPASSWD();
701  SCU_ClosePASSWD();
702 }
703 
705 {
706  SCU_OpenPASSWD();
708  SCU_ClosePASSWD();
709 }
710 
712 {
714 }
715 
717 {
719 }
720 
722 {
724 }
725 
727 {
729 }
730 
732 {
734 }
735 
737 {
739 }
740 
742 {
744 }
745 
747 {
749 }
750 
752 {
754 }
755 
757 {
759 }
760 
762 {
764 }
765 
767 {
769 }
770 
772 {
774 }
775 
777 {
779 }
780 
782 {
784 }
785 
786 #endif
BootROM low level access library.
NVM_PASSWORD_SEGMENT_t
This enum defines the NVM protection password segment.
Definition: bootrom.h:203
#define SCUPM
Definition: tle985x.h:6278
#define CPU
Definition: tle985x.h:6269
#define SCU
Definition: tle985x.h:6277
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Msk
Definition: tle985x.h:10429
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Msk
Definition: tle985x.h:10425
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_TH_Pos
Definition: tle985x.h:10424
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Msk
Definition: tle985x.h:10433
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Pos
Definition: tle985x.h:10422
#define CPU_SCR_SLEEPONEXIT_Msk
Definition: tle985x.h:8744
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Pos
Definition: tle985x.h:10434
#define SCU_APCLK_SCLR_APCLK3SCLR_Msk
Definition: tle985x.h:9813
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Msk
Definition: tle985x.h:10427
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Pos
Definition: tle985x.h:10430
#define CPU_SCR_SLEEPONEXIT_Pos
Definition: tle985x.h:8743
#define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Msk
Definition: tle985x.h:10415
#define SCUPM_AMCLK_TH_HYS_AMCLK2_LOW_HYS_Msk
Definition: tle985x.h:10423
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_TH_Pos
Definition: tle985x.h:10428
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_HYS_Msk
Definition: tle985x.h:10435
#define SCU_CMCON2_PBA0CLKREL_Pos
Definition: tle985x.h:9861
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Pos
Definition: tle985x.h:10436
#define SCU_CMCON2_PBA0CLKREL_Msk
Definition: tle985x.h:9862
#define SCU_APCLK_SCLR_APCLK1SCLR_Msk
Definition: tle985x.h:9817
#define SCU_VTOR_VTOR_BYP_Pos
Definition: tle985x.h:10382
#define SCUPM_AMCLK_TH_HYS_AMCLK1_UP_TH_Msk
Definition: tle985x.h:10437
#define SCU_APCLK_SCLR_APCLK2SCLR_Pos
Definition: tle985x.h:9814
#define SCU_SYSCON0_SYSCLKSEL_Pos
Definition: tle985x.h:10374
#define SCUPM_AMCLK_TH_HYS_AMCLK2_UP_HYS_Pos
Definition: tle985x.h:10426
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_TH_Pos
Definition: tle985x.h:10432
#define SCU_APCLK_SCLR_APCLK2SCLR_Msk
Definition: tle985x.h:9815
#define SCU_WDTCON_WDTRS_Msk
Definition: tle985x.h:10398
#define SCU_VTOR_VTOR_BYP_Msk
Definition: tle985x.h:10383
#define SCUPM_AMCLK_CTRL_CLKWDT_PD_N_Pos
Definition: tle985x.h:10414
#define SCU_WDTCON_WDTEN_Pos
Definition: tle985x.h:10395
#define SCU_WDTCON_WDTEN_Msk
Definition: tle985x.h:10396
#define CPU_SCR_SLEEPDEEP_Pos
Definition: tle985x.h:8741
#define SCUPM_AMCLK_TH_HYS_AMCLK1_LOW_HYS_Msk
Definition: tle985x.h:10431
#define SCU_SYSCON0_SYSCLKSEL_Msk
Definition: tle985x.h:10375
#define SCU_APCLK_SCLR_APCLK1SCLR_Pos
Definition: tle985x.h:9816
#define SCU_WDTCON_WDTRS_Pos
Definition: tle985x.h:10397
#define CPU_SCR_SLEEPDEEP_Msk
Definition: tle985x.h:8742
#define SCU_APCLK_SCLR_APCLK3SCLR_Pos
Definition: tle985x.h:9812
INLINE void CPU_SleepOnExit_Sel(void)
Selects entering sleep or deep sleep on exit.
Definition: scu.h:781
INLINE void CPU_DeepSleep_Sel(void)
Selects low power deep sleep mode.
Definition: scu.h:776
INLINE void SCUPM_AMCLK1_UP_TH_Set(uint8 thld)
Sets Analog Module Clock 1 Upper Limit Threshold.
Definition: scu.h:736
INLINE void SCU_APCLK2_Sts_Clr(void)
Clears Analog Peripherals Clock 2 Status.
Definition: scu.h:716
TSCU_System_Clock
This enum lists the SCU System Clock Sources.
Definition: scu.h:163
@ SCU_System_Clock_LP_CLK
Definition: scu.h:164
@ SCU_System_Clock_IntOsc
Definition: scu.h:165
INLINE void SCUPM_CLKWDT_PD_N_Dis(void)
Disables Clock Watchdog.
Definition: scu.h:731
int32_t SCU_ChangeNVMProtection(NVM_PASSWORD_SEGMENT_t Protection, uint8 Action)
Sets the Write/Read Protection for the Code/Data Flash.
INLINE void SCU_Enable_Module(TScu_Mod Module)
Enables a given peripheral module.
Definition: scu.h:656
INLINE void SCUPM_AMCLK1_LOW_HYS_Set(uint8 hyst)
Sets Analog Module Clock 1 Lower Hysteresis.
Definition: scu.h:751
#define PASSWD_Close
PASSWD Phrases, PASSWD Closed.
Definition: scu.h:114
TSCU_VTOR
This enum lists the SCU Vector Table Relocation.
Definition: scu.h:172
@ SCU_VTOR_RAM
Definition: scu.h:174
@ SCU_VTOR_CBSL
Definition: scu.h:175
@ SCU_VTOR_ROM
Definition: scu.h:173
@ SCU_VTOR_UCODE
Definition: scu.h:176
void SCU_ClkInit(void)
Initializes the system clocks.
INLINE void SCU_Sel_PBA0_Clk_Div_Sel(uint8 div)
Sets PBA0 Clock Divider.
Definition: scu.h:690
INLINE void SCU_System_Clock_Sel(TSCU_System_Clock a)
Selects a System Clock.
Definition: scu.h:704
INLINE void SCUPM_AMCLK2_LOW_HYS_Set(uint8 hyst)
Sets Analog Module Clock 2 Lower Hysteresis.
Definition: scu.h:771
INLINE void SCUPM_AMCLK2_UP_HYS_Set(uint8 hyst)
Sets Analog Module Clock 2 Upper Hysteresis.
Definition: scu.h:761
TScu_Mod
This enum lists the SCU Modules Configuration.
Definition: scu.h:149
@ Mod_Timer21
Definition: scu.h:156
@ Mod_CCU
Definition: scu.h:152
@ Mod_SSC2
Definition: scu.h:155
@ Mod_GPT12
Definition: scu.h:154
@ Mod_Timer2
Definition: scu.h:153
@ Mod_SSC1
Definition: scu.h:151
@ Mod_ADC1
Definition: scu.h:150
INLINE void SCU_Disable_Module(TScu_Mod Module)
Disables a given peripheral module.
Definition: scu.h:651
INLINE void SCU_VTOR_Sel(TSCU_VTOR a)
Selects a Vector Table Bypass Mode.
Definition: scu.h:697
void SCU_Init(void)
Initializes the SCU module.
INLINE void SCU_APCLK1_Sts_Clr(void)
Clears Analog Peripherals Clock 1 Status.
Definition: scu.h:711
INLINE void SCUPM_CLKWDT_PD_N_En(void)
Enables Clock Watchdog.
Definition: scu.h:726
INLINE void SCU_WDT_Start(void)
Starts the Watchdog of SCU-DM in the Watchdog Timer Control Register The written bit is protected by ...
Definition: scu.h:661
INLINE void SCUPM_AMCLK2_UP_TH_Set(uint8 thld)
Sets Analog Module Clock 2 Upper Limit Threshold.
Definition: scu.h:756
INLINE void SCUPM_AMCLK1_UP_HYS_Set(uint8 hyst)
Sets Analog Module Clock 1 Upper Hysteresis.
Definition: scu.h:741
INLINE void SCU_WDT_Service(void)
Services the Watchdog of SCU-DM in the Watchdog Timer Control Register.
Definition: scu.h:675
INLINE void SCU_APCLK3_Sts_Clr(void)
Clears Analog Peripherals Clock 3 Status.
Definition: scu.h:721
INLINE void SCUPM_AMCLK1_LOW_TH_Set(uint8 thld)
Sets Analog Module Clock 1 Lower Limit Threshold.
Definition: scu.h:746
void SCU_EnterStopMode(void)
Sets the device into Stop Mode.
#define PASSWD_Open
PASSWD Phrases, PASSWD Opened.
Definition: scu.h:112
INLINE void SCU_OpenPASSWD(void)
Opens the bit protection by writing PASSWD_Open to the Bit Protection Register.
Definition: scu.h:680
INLINE void SCU_ClosePASSWD(void)
Closes the bit protection by writing PASSWD_Close to the Bit Protection Register.
Definition: scu.h:685
INLINE void SCUPM_AMCLK2_LOW_TH_Set(uint8 thld)
Sets Analog Module Clock 2 Lower Limit Threshold.
Definition: scu.h:766
INLINE void SCU_WDT_Stop(void)
Stops the Watchdog of SCU-DM in the Watchdog Timer Control Register The written bit is protected by t...
Definition: scu.h:668
void SCU_EnterSleepMode(void)
Sets the device into Sleep Mode.
SFR low level access library.
INLINE void Field_Wrt32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:358
INLINE void Field_Wrt32all(volatile uint32 *reg, uint32 val)
This function writes an 32-bit register directly, no mask/position needed.
Definition: sfr_access.h:363
INLINE void Field_Mod32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:378
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint32_t uint32
32 bit unsigned value
Definition: types.h:155