Infineon MOTIX™ MCU TLE985x Device Family SDK
ccu6.h
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1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2014-2022, Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** TA Thomas Albersinger **
45 ** DM Daniel Mysliwitz **
46 ** JO Julia Ott **
47 ** BG Blandine Guillot **
48 *******************************************************************************/
49 
50 /*******************************************************************************
51 ** Revision Control History **
52 ********************************************************************************
53 ** V0.1.0: 2014-04-25, ? : Initial version of revision history **
54 ** V0.2.0: 2014-04-25, TA: CCU6_Init(): use #defines from Config Wizard **
55 ** V0.2.1: 2015-02-10, DM: Individual header file added **
56 ** V0.2.2: 2015-08-27, DM: New API functions added to ccu6.h **
57 ** V0.2.3: 2017-04-11, DM: Macros for interrupt set/reset/clear added **
58 ** V0.2.4: 2017-11-08, DM: CCU6_T12_Modulation_En() fixed **
59 ** CCU6_T13_Modulation_En() fixed **
60 ** V0.2.5: 2017-11-14, DM: MISRA 2012 compliance, the following PC-Lint **
61 ** rules are deactivated: **
62 ** - Info 793: ANSI/ISO limit of 6 'significant **
63 ** characters in an external identifier **
64 ** - Info 835: A zero has been given as right **
65 ** argument to operator **
66 ** - Info 845: The left argument to operator '&' **
67 ** is certain to be 0 **
68 ** CCU6_Init(): one CCU6_T12_Str_En() replaced by **
69 ** CCU6_T13_Str_En() **
70 ** Replaced macros by INLINE functions **
71 ** Replaced register accesses within functions by **
72 ** function calls **
73 ** Replaced __STATIC_INLINE by INLINE **
74 ** V0.2.6: 2018-03-14, DM: CCU6_Ch0_Deadtime_Sts(), CCU6_Ch1_Deadtime_Sts(),**
75 ** CCU6_Ch2_Deadtime_Sts() the register access **
76 ** macro changed to Field_Rd1() **
77 ** CCU6_MASK_CC6x and CCU6_MASK_COUT6x changed due **
78 ** to MISRA 2012 **
79 ** V0.2.7: 2018-12-04, JO: Doxygen update **
80 ** Moved revision history from ccu6.c to ccu6.h **
81 ** CCU6_Passive_State_After_Compare_Sel() added **
82 ** CCU6_Ch*t_Passive_State_After_Compare_Sel() and **
83 ** CCU6_Ch*t_Passive_State_Before_Compare_Sel() **
84 ** removed **
85 ** V0.2.8: 2019-01-29, DM: CCU6_ReadHallReg() fixed **
86 ** V0.2.9: 2019-02-27, JO: CCU6_SetT13Compare changed (added range check, **
87 ** +1 instead of +10) **
88 ** V0.3.0: 2020-03-02, BG: Updated revision history format **
89 ** V0.3.1: 2022-01-21, JO: EP-934: Updated copyright and branding **
90 *******************************************************************************/
91 
92 #ifndef _CCU6_H
93 #define _CCU6_H
94 
95 /*******************************************************************************
96 ** Includes **
97 *******************************************************************************/
98 #include "tle985x.h"
99 #include "types.h"
100 #include "ccu6_defines.h"
101 #include "sfr_access.h"
102 #include "tle_variants.h"
103 
104 /*******************************************************************************
105 ** Global Macro Definitions **
106 *******************************************************************************/
108 #define CCU6_MASK_TCTR4_STOP_T12 (CCU6_TCTR4_T12RR_Msk)
110 #define CCU6_MASK_TCTR4_START_T12 (CCU6_TCTR4_T12RS_Msk)
112 #define CCU6_MASK_TCTR4_RESET_T12 (CCU6_TCTR4_T12RES_Msk)
114 #define CCU6_MASK_TCTR4_SHADOW_T12 (CCU6_TCTR4_T12STR_Msk)
116 #define CCU6_MASK_TCTR4_STOP_T13 (CCU6_TCTR4_T13RR_Msk)
118 #define CCU6_MASK_TCTR4_START_T13 (CCU6_TCTR4_T13RS_Msk)
120 #define CCU6_MASK_TCTR4_RESET_T13 (CCU6_TCTR4_T13RES_Msk)
122 #define CCU6_MASK_TCTR4_SHADOW_T13 (CCU6_TCTR4_T13STR_Msk)
123 
125 #define CCU6_MASK_MCMOUTS_SHADOW_HALL (CCU6_MCMOUTS_STRHP_Msk)
127 #define CCU6_MASK_MCMOUTS_SHADOW_OUT (CCU6_MCMOUTS_STRMCM_Msk)
128 
130 #define CCU6_MASK_CC60 ((uint16)1u << 0u)
132 #define CCU6_MASK_COUT60 ((uint16)1u << 1u)
134 #define CCU6_MASK_CC61 ((uint16)1u << 2u)
136 #define CCU6_MASK_COUT61 ((uint16)1u << 3u)
138 #define CCU6_MASK_CC62 ((uint16)1u << 4u)
140 #define CCU6_MASK_COUT62 ((uint16)1u << 5u)
141 
143 #define CCU6_MASK_Ch0t CCU6_MASK_CC60
145 #define CCU6_MASK_Ch0c CCU6_MASK_COUT60
147 #define CCU6_MASK_Ch1t CCU6_MASK_CC61
149 #define CCU6_MASK_Ch1c CCU6_MASK_COUT61
151 #define CCU6_MASK_Ch2t CCU6_MASK_CC62
153 #define CCU6_MASK_Ch2c CCU6_MASK_COUT62
154 
156 #define MCM_MASK_CCPOS0 (1u)
158 #define MCM_MASK_CCPOS1 (2u)
160 #define MCM_MASK_CCPOS2 (4u)
161 
162 
163 /*******************************************************************************
164 ** Global Type Definitions **
165 *******************************************************************************/
169 typedef enum
170 {
172  CCU6_CC60_1_P23 = 1u
174 
178 typedef enum
179 {
181  CCU6_CC61_1_P21 = 1u
183 
187 typedef enum
188 {
190  CCU6_CC62_1_P27 = 1u
192 
196 typedef enum
197 {
201  CCU6_DU1_UP_STS = 3u
203 
207 typedef enum
208 {
211  CCU6_CCPOS0_2_P20 = 2u
213 
217 typedef enum
218 {
221  CCU6_CCPOS1_2_P14 = 2u
223 
227 typedef enum
228 {
231  CCU6_CCPOS2_2_P12 = 2u
233 
237 typedef enum
238 {
241  CCU6_T12HR_2_P22 = 2u
243 
247 typedef enum
248 {
251  CCU6_T13HR_2_P20 = 2u
253 
257 typedef enum
258 {
264 
268 typedef enum
269 {
275 
279 typedef enum
280 {
282  CCU6_T12HR_H_E = 1u
284 
288 typedef enum
289 {
291  CCU6_T13HR_H_E = 1u
293 
297 typedef enum
298 {
300  CCU6_T13_CM = 1u,
301  CCU6_T13_PM = 2u,
303  CCU6_T12_PM = 4u,
304  CCU6_T12_OM = 5u,
308 
312 typedef enum
313 {
321  CCU6_Clk_Div_128 = 7
323 
327 typedef enum
328 {
336  CCU6_T13TEC_CCPOSx = 7
338 
342 typedef enum
343 {
349 
353 typedef enum
354 {
360 
364 typedef enum
365 {
371 
375 typedef enum
376 {
378  CCU6_PSL63_High = 1
380 
384 typedef enum
385 {
391  CCU6_SWSEL_T12_PM = 5
393 
397 typedef enum
398 {
402  CCU6_Node3 = 3
404 
408 typedef enum
409 {
415 
416 /*******************************************************************************
417 ** Inline Function Definitions **
418 *******************************************************************************/
432 {
434 }
435 
449 {
451 }
452 
466 {
468 }
469 
483 {
485 }
486 
502 {
504 }
505 
519 {
521 }
522 
536 {
538 }
539 
553 {
555 }
556 
570 {
572 }
573 
587 {
589 }
590 
606 {
608 }
609 
623 {
625 }
626 
640 {
642 }
643 
659 {
661 }
662 
678 {
680 }
681 
697 {
699 }
700 
716 {
718 }
719 
735 {
737 }
738 
754 {
756 }
757 
773 {
775 }
776 
793 {
795 }
796 
813 {
815 }
816 
834 {
836 }
837 
855 {
857 }
858 
875 {
877 }
878 
895 {
897 }
898 
912 {
914 }
915 
929 {
931 }
932 
948 {
950 }
951 
967 {
969 }
970 
986 {
988 }
989 
1005 {
1007 }
1008 
1026 {
1028 }
1029 
1046 {
1048 }
1049 
1068 {
1070 }
1071 
1088 {
1090 }
1091 
1109 {
1111 }
1112 
1128 {
1130 }
1131 
1149 {
1151 }
1152 
1168 {
1170 }
1171 
1189 {
1191 }
1192 
1208 {
1210 }
1211 
1229 {
1231 }
1232 
1248 {
1250 }
1251 
1265 {
1267 }
1268 
1282 {
1284 }
1285 
1299 {
1301 }
1302 
1316 {
1318 }
1319 
1333 {
1335 }
1336 
1350 {
1352 }
1353 
1372 {
1374 }
1375 
1394 {
1396 }
1397 
1416 {
1418 }
1419 
1437 {
1439 }
1440 
1456 {
1458 }
1459 
1477 {
1479 }
1480 
1496 {
1498 }
1499 
1517 {
1519 }
1520 
1536 {
1538 }
1539 
1559 {
1561 }
1562 
1582 {
1584 }
1585 
1605 {
1607 }
1608 
1628 {
1630 }
1631 
1650 {
1652 }
1653 
1672 {
1674 }
1675 
1694 {
1696 }
1697 
1705 {
1706  Field_Mod16(&CCU6->CMPSTAT.reg, (uint8)CCU6_CMPSTAT_CC60PS_Pos, (uint16)0x3F00, (uint16_t)mode);
1707  CCU6_T12_Str_En();
1708 }
1709 
1710 
1727 {
1729  CCU6_T13_Str_En();
1730 }
1731 
1748 {
1750  CCU6_T13_Str_En();
1751 }
1752 
1766 {
1768  CCU6_T13_Str_En();
1769 }
1770 
1784 {
1786  CCU6_T13_Str_En();
1787 }
1788 
1802 {
1804 }
1805 
1819 {
1821 }
1822 
1836 {
1838 }
1839 
1853 {
1855 }
1856 
1870 {
1872 }
1873 
1887 {
1889 }
1890 
1904 {
1906 }
1907 
1921 {
1923 }
1924 
1938 {
1940 }
1941 
1955 {
1957 }
1958 
1975 {
1977 }
1978 
1995 {
1997 }
1998 
2012 {
2014 }
2015 
2029 {
2031 }
2032 
2046 {
2048 }
2049 
2063 {
2065 }
2066 
2085 {
2087 }
2088 
2107 {
2109 }
2110 
2129 {
2131 }
2132 
2151 {
2153 }
2154 
2173 {
2175 }
2176 
2190 {
2192 }
2193 
2207 {
2209 }
2210 
2226 {
2228 }
2229 
2245 {
2247 }
2248 
2264 {
2266 }
2267 
2283 {
2285 }
2286 
2302 {
2304 }
2305 
2321 {
2323 }
2324 
2340 {
2342 }
2343 
2359 {
2361 }
2362 
2376 {
2378 }
2379 
2393 {
2395 }
2396 
2410 {
2412 }
2413 
2427 {
2429 }
2430 
2444 {
2446 }
2447 
2461 {
2463 }
2464 
2478 {
2480 }
2481 
2495 {
2497 }
2498 
2512 {
2514 }
2515 
2529 {
2531 }
2532 
2546 {
2548 }
2549 
2563 {
2565 }
2566 
2580 {
2582 }
2583 
2599 {
2601 }
2602 
2633 {
2634  Field_Mod16(&CCU6->CMPSTAT.reg, (uint8)CCU6_CMPSTAT_CC60PS_Pos, (uint16)0x3F00, ccu6_mask);
2635  CCU6_T12_Str_En();
2636 }
2637 
2651 {
2652  Field_Mod16(&CCU6->PSLR.reg, (uint8)0u, 0x01u, 1u);
2653 }
2654 
2668 {
2669  Field_Mod16(&CCU6->PSLR.reg, (uint8)0u, 0x01u, 0u);
2670 }
2671 
2685 {
2686  Field_Mod16(&CCU6->PSLR.reg, (uint8)1u, 0x02u, 1u);
2687 }
2688 
2702 {
2703  Field_Mod16(&CCU6->PSLR.reg, (uint8)1u, 0x02u, 0u);
2704 }
2705 
2719 {
2720  Field_Mod16(&CCU6->PSLR.reg, (uint8)2u, 0x04u, 1u);
2721 }
2722 
2736 {
2737  Field_Mod16(&CCU6->PSLR.reg, (uint8)2u, 0x04u, 0u);
2738 }
2739 
2753 {
2754  Field_Mod16(&CCU6->PSLR.reg, (uint8)3u, 0x08u, 1u);
2755 }
2756 
2770 {
2771  Field_Mod16(&CCU6->PSLR.reg, (uint8)3u, 0x08u, 0u);
2772 }
2773 
2787 {
2788  Field_Mod16(&CCU6->PSLR.reg, (uint8)4u, 0x10u, 1u);
2789 }
2790 
2804 {
2805  Field_Mod16(&CCU6->PSLR.reg, (uint8)4u, 0x10u, 0u);
2806 }
2807 
2821 {
2822  Field_Mod16(&CCU6->PSLR.reg, (uint8)5u, 0x20u, 1u);
2823 }
2824 
2838 {
2839  Field_Mod16(&CCU6->PSLR.reg, (uint8)5u, 0x20u, 0u);
2840 }
2841 
2871 {
2872  Field_Mod16(&CCU6->PSLR.reg, (uint8)CCU6_PSLR_PSL_Pos, (uint16)CCU6_PSLR_PSL_Msk, ccu6_mask);
2873 }
2874 
2890 {
2892 }
2893 
2909 {
2911 }
2912 
2926 {
2928 }
2929 
2943 {
2945 }
2946 
2962 {
2963  Field_Mod16(&CCU6->MCMOUTS.reg, (uint8)CCU6_MCMOUTS_EXPHS_Pos, (uint16)CCU6_MCMOUTS_EXPHS_Msk, mcm_mask_ccpos);
2964 }
2965 
2981 {
2982  Field_Mod16(&CCU6->MCMOUTS.reg, (uint8)CCU6_MCMOUTS_CURHS_Pos, (uint16)CCU6_MCMOUTS_CURHS_Msk, mcm_mask_ccpos);
2983 }
2984 
2998 {
3000 }
3001 
3015 {
3017 }
3018 
3036 {
3038 }
3039 
3058 {
3059  return ( u8_Field_Rd16(&CCU6->MCMOUT.reg, (uint8)CCU6_MCMOUT_R_Pos, (uint16)CCU6_MCMOUT_R_Msk) );
3060 }
3061 
3079 {
3081 }
3082 
3100 {
3102 }
3103 
3119 {
3121 }
3122 
3136 {
3138 }
3139 
3153 {
3155 }
3156 
3170 {
3172 }
3173 
3187 {
3189 }
3190 
3204 {
3206 }
3207 
3221 {
3223 }
3224 
3238 {
3240 }
3241 
3255 {
3257 }
3258 
3272 {
3274 }
3275 
3289 {
3291 }
3292 
3306 {
3308 }
3309 
3323 {
3325 }
3326 
3340 {
3342 }
3343 
3357 {
3359 }
3360 
3374 {
3376 }
3377 
3398 {
3400 }
3401 
3422 {
3424 }
3425 
3446 {
3448 }
3449 
3470 {
3472 }
3473 
3494 {
3496 }
3497 
3518 {
3520 }
3521 
3542 {
3544 }
3545 
3566 {
3568 }
3569 
3590 {
3592 }
3593 
3614 {
3616 }
3617 
3638 {
3640 }
3641 
3662 {
3664 }
3665 
3686 {
3687  return ( u1_Field_Rd16(&CCU6->IS.reg, (uint8)CCU6_IS_CHE_Pos, (uint16)CCU6_IS_CHE_Msk) );
3688 }
3689 
3710 {
3711  return ( u1_Field_Rd16(&CCU6->IS.reg, (uint8)CCU6_IS_WHE_Pos, (uint16)CCU6_IS_WHE_Msk) );
3712 }
3713 
3732 {
3734 }
3735 
3756 {
3757  return ( u1_Field_Rd16(&CCU6->IS.reg, (uint8)CCU6_IS_STR_Pos, (uint16)CCU6_IS_STR_Msk) );
3758 }
3759 
3779 {
3781 }
3782 
3802 {
3804 }
3805 
3825 {
3827 }
3828 
3848 {
3850 }
3851 
3871 {
3873 }
3874 
3894 {
3896 }
3897 
3917 {
3919 }
3920 
3940 {
3942 }
3943 
3963 {
3965 }
3966 
3986 {
3988 }
3989 
4009 {
4011 }
4012 
4026 {
4028 }
4029 
4049 {
4051 }
4052 
4072 {
4074 }
4075 
4092 {
4094 }
4095 
4115 {
4117 }
4118 
4140 {
4142 }
4143 
4165 {
4167 }
4168 
4190 {
4192 }
4193 
4215 {
4217 }
4218 
4240 {
4242 }
4243 
4265 {
4267 }
4268 
4290 {
4292 }
4293 
4312 {
4314 }
4315 
4334 {
4336 }
4337 
4356 {
4358 }
4359 
4378 {
4380 }
4381 
4400 {
4402 }
4403 
4422 {
4424 }
4425 
4444 {
4446 }
4447 
4466 {
4468 }
4469 
4488 {
4490 }
4491 
4510 {
4512 }
4513 
4532 {
4534 }
4535 
4554 {
4556 }
4557 
4576 {
4578 }
4579 
4598 {
4600 }
4601 
4620 {
4622 }
4623 
4643 {
4645 }
4646 
4665 {
4667 }
4668 
4688 {
4690 }
4691 
4710 {
4712 }
4713 
4733 {
4735 }
4736 
4755 {
4757 }
4758 
4778 {
4780 }
4781 
4800 {
4802 }
4803 
4823 {
4825 }
4826 
4845 {
4847 }
4848 
4868 {
4870 }
4871 
4890 {
4892 }
4893 
4913 {
4915 }
4916 
4935 {
4937 }
4938 
4958 {
4960 }
4961 
4980 {
4982 }
4983 
5003 {
5005 }
5006 
5025 {
5027 }
5028 
5048 {
5050 }
5051 
5070 {
5072 }
5073 
5093 {
5095 }
5096 
5115 {
5117 }
5118 
5138 {
5140 }
5141 
5160 {
5162 }
5163 
5183 {
5185 }
5186 
5205 {
5207 }
5208 
5228 {
5230 }
5231 
5232 /*******************************************************************************
5233 ** Global Function Declarations **
5234 *******************************************************************************/
5239 void CCU6_Init(void);
5240 
5241 INLINE void CCU6_StartTmr_T12(void);
5242 INLINE void CCU6_StartTmr_T13(void);
5243 INLINE void CCU6_StopTmr_T12(void);
5244 INLINE void CCU6_StopTmr_T13(void);
5245 INLINE void CCU6_EnableST_T12(void);
5246 INLINE void CCU6_EnableST_T13(void);
5253 INLINE bool CCU6_IsT13Running(void);
5254 INLINE void CCU6_SetT13Trigger(uint16 Mask);
5255 INLINE void CCU6_SetT13Compare(uint16 Compare);
5262 INLINE void CCU6_EnableInt(uint16 Mask);
5263 INLINE void CCU6_ClearIntStatus(uint16 Mask);
5264 
5265 /*******************************************************************************
5266 ** Inline Function Definitions **
5267 *******************************************************************************/
5281 {
5282  CCU6_T12_Start();
5283 }
5284 
5298 {
5299  CCU6_T13_Start();
5300 }
5301 
5315 {
5316  CCU6_T12_Stop();
5317 }
5318 
5332 {
5333  CCU6_T13_Stop();
5334 }
5335 
5349 {
5350  CCU6_T12_Str_En();
5351 }
5352 
5366 {
5367  CCU6_T13_Str_En();
5368 }
5369 
5385 {
5386  CCU6_Ch0_Value_Set(tick);
5387 }
5388 
5404 {
5405  CCU6_Ch1_Value_Set(tick);
5406 }
5407 
5423 {
5424  CCU6_Ch2_Value_Set(tick);
5425 }
5426 
5442 {
5443  CCU6_Ch3_Value_Set(tick);
5444 }
5445 
5461 {
5462  CCU6_T13_Period_Value_Set((uint16)((uint32)CCU6_T13_CLK * us));
5463 }
5464 
5480 {
5482 }
5483 
5503 {
5504  bool res = false;
5505 
5506  if (CCU6_T13_Run_Sts() == (uint8)1)
5507  {
5508  res = true;
5509  }
5510 
5511  return(res);
5512 }
5513 
5529 {
5530  /* Set trigger mask */
5531  Field_Wrt16(&CCU6->TCTR2.reg, (uint8)0, (uint16)0xFFFF, Mask);
5532 }
5533 
5549 {
5550  if(Compare < CCU6_T13_Period_Value_Get())
5551  {
5552  /* Set only the requested compare value if no period change is needed */
5553  CCU6_Ch3_Value_Set(Compare);
5554  }
5555  else
5556  {
5557  /* Period value < compare value --> increase the period value */
5558  if(Compare <= (uint16)0xFFFE)
5559  {
5560  /* Set requested compare value */
5561  CCU6_Ch3_Value_Set(Compare);
5562  /* increase period value to ensure the compare match */
5563  CCU6_T13_Period_Value_Set((Compare + 1u));
5564  }
5565  else
5566  {
5567  /* Requested value is not possible */
5568  /* Set the highest possible values that ensure a compare match*/
5569  CCU6_Ch3_Value_Set((uint16)0xFFFE);
5571  }
5572  }
5573  /* Enable shadow transfer */
5574  CCU6_T13_Str_En();
5575 }
5576 
5592 {
5593  Field_Wrt16(&CCU6->TCTR4.reg, (uint8)0, (uint16)0xFFFF, Mask);
5594 }
5595 
5613 {
5614  return (uint32)u16_Field_Rd16(&CCU6->CMPSTAT.reg, (uint8)CCU6_CMPSTAT_CCPOS0_Pos, 0x38u);
5615 }
5616 
5634 {
5635  return u16_Field_Rd16(&CCU6->MCMOUT.reg, (uint8)0, (uint16)0xFFFF);
5636 }
5637 
5653 {
5654  Field_Wrt16(&CCU6->MCMOUTS.reg, (uint8)0, (uint16)0xFFFF, Patterns);
5655 }
5656 
5672 {
5673  Field_Wrt16(&CCU6->MCMCTR.reg, (uint8)0, (uint16)0xFFFF, Mode);
5674 }
5675 
5691 {
5692  Field_Wrt16(&CCU6->MODCTR.reg, (uint8)0, (uint16)0xFFFF, Mode);
5693 }
5694 
5710 {
5711  Field_Wrt16(&CCU6->IEN.reg, (uint8)0, (uint16)0xFFFF, Mask);
5712 }
5713 
5729 {
5730  Field_Wrt16(&CCU6->ISR.reg, (uint8)0, (uint16)0xFFFF, Mask);
5731 }
5732 
5733 #endif
INLINE uint16 CCU6_T13_Period_Value_Get(void)
reads Timer T13 Period Value.
Definition: ccu6.h:1476
INLINE void CCU6_T12_Modulation_En(uint16 ccu6_mask)
enables Timer T12 Modulation Configuration
Definition: ccu6.h:2301
INLINE void CCU6_MCM_Switch_T13_PM_Set(void)
sets T13 period-match Switching Mode.
Definition: ccu6.h:3169
INLINE void CCU6_Ch3c_Passive_State_After_Compare_Set(void)
sets Passive state for COUT63 after Compare.
Definition: ccu6.h:1726
INLINE void CCU6_T12_Period_Value_Set(uint16 t12pr)
sets Timer T12 Period Value.
Definition: ccu6.h:1087
INLINE void CCU6_T13_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Timer T13 Interrupts.
Definition: ccu6.h:4264
INLINE void CCU6_T13_PM_Int_Clr(void)
clears Interrupt for T13 Period-Match Flag.
Definition: ccu6.h:4509
INLINE void CCU6_StartTmr_T12(void)
Start CCU6 Timer T12.
Definition: ccu6.h:5280
INLINE void CCU6_StartTmr_T13(void)
Start CCU6 Timer T13.
Definition: ccu6.h:5297
INLINE void CCU6_MCM_Switch_Sync_direct_Sel(void)
sets Direct Switching Synchronization.
Definition: ccu6.h:3237
INLINE void CCU6_MCM_Hall_Str_HW_En(void)
enables Shadow Transfer Request for the Hall Pattern by Hardware.
Definition: ccu6.h:3014
INLINE void CCU6_Ch2_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 2 Interrupts.
Definition: ccu6.h:4189
TCCU6_Pos2_Input
This enum lists the CCU6 ISPOS2 Inputs.
Definition: ccu6.h:228
@ CCU6_CCPOS2_0_P27
Definition: ccu6.h:229
@ CCU6_CCPOS2_2_P12
Definition: ccu6.h:231
@ CCU6_CCPOS2_1_P05
Definition: ccu6.h:230
INLINE void CCU6_CH1_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 1.
Definition: ccu6.h:4754
INLINE uint8 CCU6_Ch1_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 1 Deadtime Status.
Definition: ccu6.h:1393
INLINE void CCU6_T13_Rst(void)
resets CCU6 T13.
Definition: ccu6.h:586
INLINE void CCU6_CH2_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 2.
Definition: ccu6.h:4844
INLINE void CCU6_T13_Period_Value_Set(uint16 t13pr)
sets Timer T13 Period Value.
Definition: ccu6.h:1495
INLINE void CCU6_T12_CM_CC62_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 2.
Definition: ccu6.h:3893
INLINE void CCU6_T12_PWMMode_Set(TCCU6_PWMMode mode)
sets mode of PWM signal for Channel0/1/2 and COUT0/1/2.
Definition: ccu6.h:1704
INLINE void CCU6_T13_CM_Int_Dis(void)
disables Interrupt for T13 Compare-Match.
Definition: ccu6.h:5002
INLINE void CCU6_Ch1_CapCom_Mode_Sel(uint16 msel61)
selects CCU6 T12 CH1 Capture/Compare Mode.
Definition: ccu6.h:985
INLINE void CCU6_Passive_State_After_Compare_Sel(uint16 ccu6_mask)
Sets the passive state to "after" the compare value.
Definition: ccu6.h:2632
INLINE void CCU6_Passiv_Level_Ch3_Sel(uint16 lvl)
sets Passive State Level of Output COUT63.
Definition: ccu6.h:2889
INLINE void CCU6_Error_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Error Interrupts.
Definition: ccu6.h:4214
INLINE void CCU6_CH2_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 2.
Definition: ccu6.h:4867
INLINE void CCU6_Ch2t_Passive_Level_High_Set(void)
sets Passive High Level of CC62.
Definition: ccu6.h:2786
INLINE uint8 CCU6_T12_CM_CC60_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 0.
Definition: ccu6.h:3469
INLINE uint8 CCU6_Trap_Flag_Int_Sts(void)
reads Trap Flag Status.
Definition: ccu6.h:3637
INLINE void CCU6_CH2_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 2.
Definition: ccu6.h:4822
TCCU6_HSYNC
This enum lists the CCU6 Hall Synch Configuration.
Definition: ccu6.h:298
@ CCU6_T12_PM
Definition: ccu6.h:303
@ CCU6_T13_PM
Definition: ccu6.h:301
@ CCU6_CCPOS0x_Any_Edge
Definition: ccu6.h:299
@ CCU6_T12_OM
Definition: ccu6.h:304
@ CCU6_T12_CM_Ch1_up
Definition: ccu6.h:305
@ CCU6_HW_Hall_Sampling_Off
Definition: ccu6.h:302
@ CCU6_T13_CM
Definition: ccu6.h:300
@ CCU6_T12_CM_Ch1_down
Definition: ccu6.h:306
INLINE void CCU6_T12_Single_Shot_En(void)
enables Timer T12 Single Shot.
Definition: ccu6.h:2189
INLINE void CCU6_Ch2_CapCom_Mode_Sel(uint16 msel62)
selects CCU6 T12 CH2 Capture/Compare Mode.
Definition: ccu6.h:966
INLINE void CCU6_Ch2c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT62.
Definition: ccu6.h:2837
INLINE void CCU6_T12_Center_Aligned_Mode_En(void)
enables T12 Operating Center-aligned Mode.
Definition: ccu6.h:1954
INLINE void CCU6_CH0_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 0.
Definition: ccu6.h:4687
INLINE void CCU6_Trap_Flag_Int_Set(void)
sets Trap Flag.
Definition: ccu6.h:4008
INLINE uint32 CCU6_ReadHallReg(void)
Reads sampled Hall pattern from CCU6 CMPSTAT register.
Definition: ccu6.h:5612
INLINE void CCU6_CHE_Int_Clr(void)
clears Interrupt for Correct Hall Event flag.
Definition: ccu6.h:4553
INLINE void CCU6_MCM_PWM_Str_HW_En(void)
enables Shadow Transfer Request for MCMPS by Hardware.
Definition: ccu6.h:2942
void CCU6_Init(void)
Initializes the CCU6 module.
INLINE void CCU6_MCM_PWM_Str_SW_En(void)
enables Shadow Transfer Request for MCMPS by Software.
Definition: ccu6.h:2925
INLINE void CCU6_Hall_Correct_Int_Set(void)
sets Interrupt for Correct Hall Event flag.
Definition: ccu6.h:4048
INLINE void CCU6_T12_Ext_Input_Sel(uint16 t12ext)
selects Input of Extension for T12HR.
Definition: ccu6.h:874
INLINE void CCU6_T12_OM_Int_Set(void)
sets Interrupt for T12 One-Match Flag.
Definition: ccu6.h:3916
INLINE void CCU6_T13_Cnt_Input_Sel(uint16 iscnt13)
selects Input for T13 Counting.
Definition: ccu6.h:854
INLINE void CCU6_Trap_SW_Hall_Int_Set(void)
sets Interrupt for Trap SW Hall Event flag.
Definition: ccu6.h:4025
INLINE void CCU6_T12_CM_CC61_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 1.
Definition: ccu6.h:3801
INLINE void CCU6_Deadtime_Set(uint16 dtm)
sets CCU6 Timer T12 Deadtime.
Definition: ccu6.h:1247
TCCU6_PWMMode
This enum lists the CCU6 modulation modes for T12.
Definition: ccu6.h:409
@ CCU6_T12_ActiveRightAligned
Definition: ccu6.h:411
@ CCU6_T12_ActiveCenterAlignedInverted
Definition: ccu6.h:413
@ CCU6_T12_ActiveLeftAligned
Definition: ccu6.h:410
@ CCU6_T12_ActiveCenterAligned
Definition: ccu6.h:412
INLINE void CCU6_MCM_Str_Int_Set(void)
sets Multi-Channel Mode Shadow Transfer Interrupt flag.
Definition: ccu6.h:4114
INLINE uint16 CCU6_T12_Period_Value_Get(void)
reads Timer T12 Period Value.
Definition: ccu6.h:1067
INLINE uint8 CCU6_T12_PM_Int_Sts(void)
reads Timer T12 Period-Match Flag Status.
Definition: ccu6.h:3565
INLINE uint8 CCU6_MCM_Idle_Int_Sts(void)
reads IDLE Status.
Definition: ccu6.h:3731
INLINE void CCU6_Ch2_Deadtime_En(void)
enables CCU6 Timer T12 Channel 2 Deadtime.
Definition: ccu6.h:1298
INLINE uint16 CCU6_Ch2_Value_Get(void)
reads Channel 2 Capture/Compare Value.
Definition: ccu6.h:1188
INLINE void CCU6_CCPOS0_Input_Sel(uint16 ispos0)
selects Input for CCPOS0.
Definition: ccu6.h:734
INLINE void CCU6_T13_Inv_Mod_En(void)
enables T13 inversion for further modulation.
Definition: ccu6.h:1765
INLINE uint16 CCU6_ReadMultichannelPatterns(void)
Reads actual Hall and PWM patterns for Multi-Channel Mode.
Definition: ccu6.h:5633
INLINE void CCU6_Ch1_Input_Sel(uint16 iscc61)
selects Input for CC61.
Definition: ccu6.h:677
INLINE void CCU6_T12_CM_CC60_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 0.
Definition: ccu6.h:3778
INLINE void CCU6_CH1_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 1.
Definition: ccu6.h:4709
INLINE void CCU6_T12_OM_Int_En(void)
enables Interrupt for T12 One-Match.
Definition: ccu6.h:4889
INLINE uint8 CCU6_Ch2_CompState_Sts(void)
reads CC62 Capture/Compare State.
Definition: ccu6.h:1604
INLINE void CCU6_EnableST_T13(void)
Enable T13 Shadow Transfer.
Definition: ccu6.h:5365
INLINE void CCU6_T12_Edge_Aligned_Mode_En(void)
enables T12 Operating Edge-aligned Mode.
Definition: ccu6.h:1937
INLINE void CCU6_MCM_Switch_Sel(uint16 swsel)
selects Switching Mode.
Definition: ccu6.h:3118
INLINE uint8 CCU6_Hall_Wrong_Int_Sts(void)
reads Wrong Hall Event Status.
Definition: ccu6.h:3709
INLINE void CCU6_Trap_HW_Clr_En(void)
enables Hardware reset of the Trap Mode.
Definition: ccu6.h:2494
INLINE void CCU6_Ch0c_Passive_Level_High_Set(void)
sets Passive High Level of COUT60.
Definition: ccu6.h:2684
INLINE void CCU6_Multi_Ch_PWM_Shadow_Reg_Load(uint16 ccu6_mask)
sets Multi-Channel PWM Pattern Shadow.
Definition: ccu6.h:2908
INLINE void CCU6_CH2_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 2.
Definition: ccu6.h:4799
TCCU6_Clk_Prescaler
This enum lists the CCU6 T12/T13 Clock Prescaler divider.
Definition: ccu6.h:313
@ CCU6_Clk_Div_16
Definition: ccu6.h:318
@ CCU6_Clk_Div_64
Definition: ccu6.h:320
@ CCU6_Clk_Div_2
Definition: ccu6.h:315
@ CCU6_Clk_Div_4
Definition: ccu6.h:316
@ CCU6_Clk_Div_128
Definition: ccu6.h:321
@ CCU6_Clk_Div_1
Definition: ccu6.h:314
@ CCU6_Clk_Div_8
Definition: ccu6.h:317
@ CCU6_Clk_Div_32
Definition: ccu6.h:319
INLINE void CCU6_T13_Str_En(void)
enables T13 Shadow Transfer.
Definition: ccu6.h:622
INLINE void CCU6_T12_Modulation_Dis(uint8 ccu6_mask)
disables Timer T12 Modulation Configuration
Definition: ccu6.h:2320
INLINE uint16 CCU6_T12_Count_Value_Get(void)
reads Timer T12 Counter Value.
Definition: ccu6.h:1025
TCCU6_Ch2_Input
This enum lists the CCU6 channel 2 Inputs.
Definition: ccu6.h:188
@ CCU6_CC62_1_P27
Definition: ccu6.h:190
@ CCU6_CC62_0_P01
Definition: ccu6.h:189
INLINE void CCU6_STR_Int_Dis(void)
disables Multi-Channel Mode Shadow Transfer Interrupt.
Definition: ccu6.h:5227
INLINE void CCU6_T12_PM_Int_Set(void)
sets Interrupt for T12 Period-Match Flag.
Definition: ccu6.h:3939
INLINE void CCU6_Ch0_Input_Sel(uint16 iscc60)
selects Input for CC60.
Definition: ccu6.h:658
INLINE void CCU6_Trap_Pin_En(void)
enables the trap functionality based on the input pin CTRAP.
Definition: ccu6.h:2562
INLINE void CCU6_T12_Str_Dis(void)
disables T12 Shadow Transfer.
Definition: ccu6.h:535
INLINE uint8 CCU6_Ch0_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 0 Deadtime Status.
Definition: ccu6.h:1371
INLINE void CCU6_TRAP_Int_Dis(void)
disables Interrupt for Trap Flag.
Definition: ccu6.h:5092
INLINE uint8 CCU6_T13_CM_Int_Sts(void)
reads Timer T13 Compare-Match Flag Status.
Definition: ccu6.h:3589
INLINE uint8 CCU6_T12_Run_Sts(void)
reads Timer T12 Run Bit.
Definition: ccu6.h:2084
INLINE void CCU6_WHE_Int_Clr(void)
clears Interrupt for Wrong Hall Event flag.
Definition: ccu6.h:4575
INLINE void CCU6_Trap_T13_Dis(void)
disables The trap functionality for T13.
Definition: ccu6.h:2545
INLINE void CCU6_MCM_Idle_Int_Set(void)
sets Interrupt for IDLE flag.
Definition: ccu6.h:4091
INLINE void CCU6_CCPOS1_Input_Sel(uint16 ispos1)
selects Input for CCPOS1.
Definition: ccu6.h:753
INLINE void CCU6_T12_PM_Int_Dis(void)
disables Interrupt for T12 Period-Match.
Definition: ccu6.h:4957
INLINE void CCU6_EnableST_T12(void)
Enable T12 Shadow Transfer.
Definition: ccu6.h:5348
INLINE void CCU6_CH1_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 1.
Definition: ccu6.h:4377
INLINE void CCU6_CH0_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 0.
Definition: ccu6.h:4333
INLINE void CCU6_T13_Trig_Event_Sel(uint16 t13tec)
selects Timer T13 Trigger Event Control.
Definition: ccu6.h:2225
INLINE void CCU6_CH1_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 1.
Definition: ccu6.h:4355
TCCU6_T13HR_Input
This enum lists the CCU6 T13HR Inputs.
Definition: ccu6.h:248
@ CCU6_T13HR_0_P01
Definition: ccu6.h:249
@ CCU6_T13HR_1_P27
Definition: ccu6.h:250
@ CCU6_T13HR_2_P20
Definition: ccu6.h:251
INLINE void CCU6_T13_Ext_Run_Sel(uint16 t13rsel)
selects Timer T13 External Run.
Definition: ccu6.h:2282
INLINE uint8 CCU6_Hall_Ch1_Sts(void)
reads Sampled Hall Pattern Bit 1.
Definition: ccu6.h:1671
INLINE void CCU6_T13_PM_Int_Set(void)
sets Interrupt for T13 Period-Match Flag.
Definition: ccu6.h:3985
INLINE void CCU6_T12_CM_CC62_Int_Rise_Set(void)
sets Capture, Compare-Match Rising Edge Interrupt flag for Channel 2.
Definition: ccu6.h:3824
INLINE uint8 CCU6_Deadtime_Get(void)
reads CCU6 Timer T12 Deadtime.
Definition: ccu6.h:1228
INLINE void CCU6_T12_Ext_Run_Sel(uint16 t12rsel)
selects Timer T12 External Run.
Definition: ccu6.h:2263
INLINE uint8 CCU6_T13_PM_Int_Sts(void)
reads Timer T13 Period-Match Flag Status.
Definition: ccu6.h:3613
INLINE void CCU6_Deadtime_Rst(void)
resets CCU6 T12 Dead-Time Counter.
Definition: ccu6.h:482
INLINE void CCU6_Hall_Synchronizaion_Sel(uint16 hsync)
selects Hall Synchronization.
Definition: ccu6.h:947
INLINE void CCU6_Trap_T13_En(void)
enables the trap functionality for T13.
Definition: ccu6.h:2528
INLINE void CCU6_Ch0t_Passive_Level_High_Set(void)
sets Passive High Level of CC60.
Definition: ccu6.h:2650
INLINE void CCU6_Hall_Correct_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for CHE Interrupts.
Definition: ccu6.h:4289
INLINE void CCU6_T13_Compare_Out_En(void)
enables Compare Timer T13 Output
Definition: ccu6.h:2409
INLINE void CCU6_MCM_Switch_T12_ON_Set(void)
sets T12 one-match Switching Mode.
Definition: ccu6.h:3186
INLINE uint8 CCU6_T12_OM_Int_Sts(void)
reads Timer T12 One-Match Flag Status.
Definition: ccu6.h:3541
INLINE void CCU6_MCM_Current_Hall_Shadow_Reg_Load(uint16 mcm_mask_ccpos)
sets Current Hall Pattern Shadow of CCPOSx.
Definition: ccu6.h:2980
INLINE void CCU6_T13_Count_Value_Set(uint16 t13cv)
sets Timer T13 Counter Value.
Definition: ccu6.h:1455
INLINE void CCU6_T13_PM_Int_En(void)
enables Interrupt for T13 Period-Match.
Definition: ccu6.h:5024
INLINE uint16 CCU6_Ch1_Value_Get(void)
reads Channel 1 Capture/Compare Value.
Definition: ccu6.h:1148
INLINE void CCU6_MCM_Switch_CorrectHall_Set(void)
sets Correct Hall Switching Mode.
Definition: ccu6.h:3152
INLINE void CCU6_CCPOS2_Input_Sel(uint16 ispos2)
selects Input for CCPOS2.
Definition: ccu6.h:772
INLINE void CCU6_T12_Prescaler_En(void)
enables additional prescaler for Timer T12.
Definition: ccu6.h:2011
INLINE void CCU6_Ch2_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 2 Deadtime.
Definition: ccu6.h:1349
INLINE void CCU6_SetT12T13ControlBits(uint16 Mask)
Sets write-only control bits for T12 and/or T13 timer.
Definition: ccu6.h:5591
TCCU6_T12HR_Input
This enum lists the CCU6 T12HR Inputs.
Definition: ccu6.h:238
@ CCU6_T12HR_2_P22
Definition: ccu6.h:241
@ CCU6_T12HR_1_P21
Definition: ccu6.h:240
@ CCU6_T12HR_0_P00
Definition: ccu6.h:239
INLINE void CCU6_Trap_SW_Clr_En(void)
enables Software reset of the Trap Mode.
Definition: ccu6.h:2511
INLINE void CCU6_Ch2t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC62.
Definition: ccu6.h:2803
INLINE bool CCU6_IsT13Running(void)
reads Timer T13 Run Bit.
Definition: ccu6.h:5502
INLINE void CCU6_WHE_Int_Dis(void)
disables Interrupt for Wrong Hall Event.
Definition: ccu6.h:5182
INLINE uint8 CCU6_T12_CM_CC61_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 1.
Definition: ccu6.h:3493
INLINE void CCU6_Ch0_Deadtime_En(void)
enables CCU6 Timer T12 Channel 0 Deadtime.
Definition: ccu6.h:1264
INLINE uint8 CCU6_T13_Str_Sts(void)
reads Timer T13 Shadow Transfer Enable Bit.
Definition: ccu6.h:2172
INLINE void CCU6_Ch2_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 2 (CC62ST) by Software.
Definition: ccu6.h:1903
INLINE void CCU6_TRAP_Int_En(void)
enables Interrupt for Trap Flag.
Definition: ccu6.h:5069
INLINE void CCU6_WriteMultichannelPatterns(uint16 Patterns)
Writes Hall and/or PWM patterns for Multi-Channel Mode to shadow register.
Definition: ccu6.h:5652
INLINE void CCU6_Ch0_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 0 for CC60ST by Software.
Definition: ccu6.h:1869
INLINE void CCU6_T12_Prescaler_Dis(void)
disables additional prescaler for Timer T12.
Definition: ccu6.h:2028
INLINE void CCU6_Hall_Delay_Bypass_Dis(void)
disables Hall Delay Bypass.
Definition: ccu6.h:928
INLINE void CCU6_Ch1t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC61.
Definition: ccu6.h:2735
INLINE uint16 CCU6_T13_Count_Value_Get(void)
reads Timer T13 Counter Value.
Definition: ccu6.h:1436
TCCU6_MCM_SWSEL
This enum lists the CCU6 Multi Channel Mode Switching Selection.
Definition: ccu6.h:385
@ CCU6_SWSEL_T12_PM
Definition: ccu6.h:391
@ CCU6_SWSEL_T12_Ch1_CM
Definition: ccu6.h:390
@ CCU6_SWSEL_T13_PM
Definition: ccu6.h:388
@ CCU6_SWSEL_No_Action
Definition: ccu6.h:386
@ CCU6_SWSEL_Correct_Hall
Definition: ccu6.h:387
@ CCU6_SWSEL_T12_OM
Definition: ccu6.h:389
INLINE uint8 CCU6_MCM_Expected_Hall_Sts(void)
reads Expected Hall Pattern of CCPOSx.
Definition: ccu6.h:3078
INLINE uint8 CCU6_T12_Count_Dir_Sts(void)
reads Count Direction of Timer T12 Bit.
Definition: ccu6.h:2128
TCCU6_Pos0_Input
This enum lists the CCU6 ISPOS0 Inputs.
Definition: ccu6.h:208
@ CCU6_CCPOS0_0_P21
Definition: ccu6.h:209
@ CCU6_CCPOS0_1_P03
Definition: ccu6.h:210
@ CCU6_CCPOS0_2_P20
Definition: ccu6.h:211
INLINE uint8 CCU6_Ch0_CompState_Sts(void)
reads CC60 Capture/Compare State.
Definition: ccu6.h:1558
INLINE void CCU6_Ch0t_Passive_Level_Low_Set(void)
sets Passive Low Level of CC60.
Definition: ccu6.h:2667
INLINE void CCU6_STR_Int_Clr(void)
clears Multi-Channel Mode Shadow Transfer Interrupt flag.
Definition: ccu6.h:4597
INLINE void CCU6_Ch3c_Passive_State_Before_Compare_Set(void)
sets Passive state for COUT63 Before Compare.
Definition: ccu6.h:1747
INLINE void CCU6_T12_Str_En(void)
enables T12 Shadow Transfer.
Definition: ccu6.h:518
INLINE void CCU6_CH1_CM_F_Int_Dis(void)
disables Capture, Compare-Match Falling Edge Interrupt for Channel 1.
Definition: ccu6.h:4777
INLINE void CCU6_T13_CM_Int_En(void)
enables Interrupt for T13 Compare-Match.
Definition: ccu6.h:4979
INLINE void CCU6_LoadShadowRegister_CC62(uint16 tick)
Load Channel 2 compare value to the shadow register.
Definition: ccu6.h:5422
INLINE void CCU6_MCM_Str_T13_Up_Cnt_En(void)
enables Shadow Transfer for T13 Upcounting.
Definition: ccu6.h:3356
INLINE uint8 CCU6_T13_Run_Sts(void)
reads Timer T13 Run Bit.
Definition: ccu6.h:2150
INLINE uint8 CCU6_MCM_PWM_Str_Req_Sts(void)
reads Reminder Flag Status.
Definition: ccu6.h:3057
INLINE uint8 CCU6_Hall_Ch2_Sts(void)
reads Sampled Hall Pattern Bit 2.
Definition: ccu6.h:1693
INLINE void CCU6_MCM_Str_T12_Down_Cnt_Dis(void)
disables Shadow Transfer for T12 Downcounting.
Definition: ccu6.h:3339
INLINE void CCU6_T13_Compare_Out_Dis(void)
disables Compare Timer T13 Output
Definition: ccu6.h:2426
INLINE void CCU6_T12_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Timer T12 Interrupts.
Definition: ccu6.h:4239
INLINE void CCU6_LoadPeriodRegister_T13_Tick(uint16 tick)
Load Timer13 Period Register as Time Value.
Definition: ccu6.h:5479
INLINE void CCU6_Ch1t_Passive_Level_High_Set(void)
sets Passive High Level of CC61.
Definition: ccu6.h:2718
INLINE void CCU6_T13HR_Input_Sel(uint16 ist13hr)
selects Input for T13HR.
Definition: ccu6.h:812
INLINE void CCU6_MCM_Hall_Str_SW_En(void)
enables Shadow Transfer Request for the Hall Pattern by Software.
Definition: ccu6.h:2997
INLINE void CCU6_MCM_Switch_NoTrigger_Set(void)
sets No Trigger Switching Mode.
Definition: ccu6.h:3135
INLINE void CCU6_T12_PM_Int_En(void)
enables Interrupt for T12 Period-Match.
Definition: ccu6.h:4934
INLINE void CCU6_T13_Str_Dis(void)
disables T13 Shadow Transfer.
Definition: ccu6.h:639
INLINE void CCU6_T12_Start(void)
starts CCU6 T12.
Definition: ccu6.h:448
INLINE void CCU6_CH0_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 0.
Definition: ccu6.h:4642
TCCU6_T12_Ext_Input
This enum lists the CCU6 T12EXT Inputs(IST12HR).
Definition: ccu6.h:280
@ CCU6_T12HR_D_A
Definition: ccu6.h:281
@ CCU6_T12HR_H_E
Definition: ccu6.h:282
INLINE void CCU6_T12HR_Input_Sel(uint16 ist12hr)
selects Input for T12HR.
Definition: ccu6.h:792
INLINE void CCU6_Ch2_Value_Set(uint16 cc62sr)
sets Channel 2 Capture/Compare Value.
Definition: ccu6.h:1207
TCCU6_Ch0_Input
This enum lists the CCU6 channel 0 Inputs.
Definition: ccu6.h:170
@ CCU6_CC60_0_P04
Definition: ccu6.h:171
@ CCU6_CC60_1_P23
Definition: ccu6.h:172
INLINE void CCU6_T13_CM_Int_Clr(void)
clears Interrupt for T13 Compare-Match Flag.
Definition: ccu6.h:4487
INLINE uint16 CCU6_Ch3_Value_Get(void)
reads Channel CC63 Compare Value.
Definition: ccu6.h:1516
INLINE void CCU6_Ch0_CapCom_Mode_Sel(uint16 msel60)
selects CCU6 T12 CH0 Capture/Compare Mode.
Definition: ccu6.h:1004
INLINE void CCU6_Ch1_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 1 Deadtime.
Definition: ccu6.h:1332
TCCU6_Node_Sel
This enum lists the CCU6 Interrupt Node Select.
Definition: ccu6.h:398
@ CCU6_Node1
Definition: ccu6.h:400
@ CCU6_Node0
Definition: ccu6.h:399
@ CCU6_Node3
Definition: ccu6.h:402
@ CCU6_Node2
Definition: ccu6.h:401
TCCU6_T13ED
This enum lists the CCU6 T13 Trigger Event Direction.
Definition: ccu6.h:343
@ CCU6_T13ED_No_Action
Definition: ccu6.h:344
@ CCU6_T13ED_T12_Up
Definition: ccu6.h:345
@ CCU6_T13ED_T12_Down
Definition: ccu6.h:346
@ CCU6_T13ED_T12_UpDown
Definition: ccu6.h:347
INLINE void CCU6_CH0_CM_F_Int_En(void)
enables Capture, Compare-Match Falling Edge Interrupt for Channel 0.
Definition: ccu6.h:4664
INLINE void CCU6_Ch0_CompState_Set(void)
sets Capture/Compare Status Modification Bit 0 for (CC60ST) by Software.
Definition: ccu6.h:1801
INLINE void CCU6_T13_CM_Int_Set(void)
sets Interrupt for T13 Compare-Match Flag.
Definition: ccu6.h:3962
INLINE void CCU6_EnableInt(uint16 Mask)
Enables/disables interrupt(s).
Definition: ccu6.h:5709
INLINE void CCU6_Ch3_Value_Set(uint16 cc63sr)
sets Channel CC63 Compare Value.
Definition: ccu6.h:1535
INLINE uint8 CCU6_Ch2_Deadtime_Sts(void)
reads CCU6 Timer T12 Channel 2 Deadtime Status.
Definition: ccu6.h:1415
INLINE void CCU6_Ch1c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT61.
Definition: ccu6.h:2769
INLINE void CCU6_T12_OM_Int_Clr(void)
clears Interrupt for T12 One-Match Flag.
Definition: ccu6.h:4443
INLINE uint8 CCU6_Ch1_CompState_Sts(void)
reads CC61 Capture/Compare State.
Definition: ccu6.h:1581
TCCU6_T12RSEL
This enum lists the CCU6 T12 Run Select.
Definition: ccu6.h:354
@ CCU6_T12RSEL_T12HR_Fall
Definition: ccu6.h:357
@ CCU6_T12RSEL_T12HR_Rise
Definition: ccu6.h:356
@ CCU6_T12RSEL_Dis
Definition: ccu6.h:355
@ CCU6_T12RSEL_T12HR_Any
Definition: ccu6.h:358
INLINE void CCU6_Ch2_CompState_Set(void)
sets Capture/Compare Status Modification Bit 2 for (CC62ST) by Software.
Definition: ccu6.h:1835
INLINE void CCU6_CH1_CM_R_Int_Dis(void)
disables Capture, Compare-Match Rising Edge Interrupt for Channel 1.
Definition: ccu6.h:4732
INLINE uint8 CCU6_MCM_Current_Hall_Sts(void)
reads Current Hall Pattern of CCPOSx.
Definition: ccu6.h:3099
INLINE void CCU6_T13_PM_Int_Dis(void)
disables Interrupt for T13 Period-Match.
Definition: ccu6.h:5047
INLINE void CCU6_Trap_Channel_En(uint16 ccu6_mask)
enables the trap functionality of a corresponding output.
Definition: ccu6.h:2598
INLINE void CCU6_ConfigureGlobalModulation(uint16 Mode)
Sets global modulation control register.
Definition: ccu6.h:5690
INLINE uint16 CCU6_Ch0_Value_Get(void)
reads Channel 0 Capture/Compare Value.
Definition: ccu6.h:1108
INLINE void CCU6_SetT13Trigger(uint16 Mask)
Sets trigger event for the T13 timer.
Definition: ccu6.h:5528
INLINE void CCU6_Trap_T13_ZM_Exit_En(void)
enables T13 zero-match Trap Mode
Definition: ccu6.h:2460
INLINE void CCU6_ConfigureMultichannelModulation(uint16 Mode)
Sets Multi-Channel Mode control register.
Definition: ccu6.h:5671
INLINE void CCU6_T13_Start(void)
starts CCU6 T13.
Definition: ccu6.h:569
INLINE void CCU6_Ch0_Deadtime_Dis(void)
disables CCU6 Timer T12 Channel 0 Deadtime.
Definition: ccu6.h:1315
INLINE void CCU6_Ch1_Value_Set(uint16 cc61sr)
sets Channel 1 Capture/Compare Value.
Definition: ccu6.h:1167
INLINE void CCU6_ClearIntStatus(uint16 Mask)
Clears interrupt status bit(s).
Definition: ccu6.h:5728
INLINE void CCU6_T12_CM_CC61_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 1.
Definition: ccu6.h:3870
INLINE void CCU6_Ch3_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 3 (CC63ST) by Software.
Definition: ccu6.h:1920
INLINE void CCU6_TRAP_Int_Clr(void)
clears Trap Flag.
Definition: ccu6.h:4531
INLINE void CCU6_Trap_Asynch_Exit_En(void)
enables Trap Immediately without any synchronization to T12 or T13.
Definition: ccu6.h:2477
INLINE void CCU6_LoadPeriodRegister_T13_Time(uint32 us)
Load Timer13 Period Register as Time Value.
Definition: ccu6.h:5460
INLINE void CCU6_T13_Trig_Event_Dir_Sel(uint16 t13ted)
selects Timer T13 Trigger Event Direction.
Definition: ccu6.h:2244
INLINE void CCU6_T12_CM_CC60_Int_Fall_Set(void)
sets Capture, Compare-Match Falling Edge Interrupt flag for Channel 0.
Definition: ccu6.h:3847
TCCU6_T13_Ext_Input
This enum lists the CCU6 T13EXT Inputs(IST13HR).
Definition: ccu6.h:289
@ CCU6_T13HR_D_A
Definition: ccu6.h:290
@ CCU6_T13HR_H_E
Definition: ccu6.h:291
INLINE void CCU6_T12_Cnt(void)
counts 1 step for CCU6 T12 Event.
Definition: ccu6.h:501
INLINE uint8 CCU6_T12_Str_Sts(void)
reads Timer T12 Shadow Transfer Enable Bit.
Definition: ccu6.h:2106
INLINE void CCU6_MCM_Str_T12_Up_Cnt_Dis(void)
disables Shadow Transfer for T12 Upcounting.
Definition: ccu6.h:3305
INLINE uint8 CCU6_Hall_Correct_Int_Sts(void)
reads Correct Hall Event Status.
Definition: ccu6.h:3685
INLINE void CCU6_Ch1_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 1 Interrupts.
Definition: ccu6.h:4164
INLINE void CCU6_Trap_T12_ZM_Exit_En(void)
enables T12 zero-match Trap Mode
Definition: ccu6.h:2443
INLINE void CCU6_Passive_Level_High_Sel(uint16 ccu6_mask)
sets Compare Corresponding Outputs Passive High Level.
Definition: ccu6.h:2870
INLINE void CCU6_CH0_CM_R_Int_En(void)
enables Capture, Compare-Match Rising Edge Interrupt for Channel 0.
Definition: ccu6.h:4619
INLINE uint8 CCU6_T12_CM_CC61_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 1.
Definition: ccu6.h:3421
INLINE uint8 CCU6_MCM_PWM_Pattern_Sts(void)
reads Multi-Channel PWM Pattern.
Definition: ccu6.h:3035
INLINE void CCU6_Ch1c_Passive_Level_High_Set(void)
sets Passive High Level of COUT61.
Definition: ccu6.h:2752
INLINE void CCU6_StopTmr_T13(void)
Stops CCU6 Timer T13.
Definition: ccu6.h:5331
INLINE uint8 CCU6_T12_CM_CC62_Int_Fall_Sts(void)
reads Capture, Compare-Match Falling Edge Flag Status for Channel 2.
Definition: ccu6.h:3517
INLINE void CCU6_Ch1_Deadtime_En(void)
enables CCU6 Timer T12 Channel 1 Deadtime.
Definition: ccu6.h:1281
INLINE uint8 CCU6_Hall_Ch0_Sts(void)
reads Sampled Hall Pattern Bit 0.
Definition: ccu6.h:1649
INLINE void CCU6_CH2_CM_F_Int_Clr(void)
clears Capture, Compare-Match Falling Edge Interrupt flag for Channel 2.
Definition: ccu6.h:4421
INLINE void CCU6_MCM_Str_T12_Up_Cnt_En(void)
enables Shadow Transfer for T12 Upcounting.
Definition: ccu6.h:3288
INLINE void CCU6_Multi_Ch_Mode_En(void)
enables Multi-Channel Mode
Definition: ccu6.h:2375
INLINE void CCU6_MCM_Str_T13_Up_Cnt_Dis(void)
disables Shadow Transfer for T13 Upcounting.
Definition: ccu6.h:3373
INLINE void CCU6_T12_PM_Int_Clr(void)
clears Interrupt for T12 Period-Match Flag.
Definition: ccu6.h:4465
INLINE void CCU6_LoadShadowRegister_CC60(uint16 tick)
Load Channel 0 compare value to the shadow register.
Definition: ccu6.h:5384
INLINE void CCU6_T13_Inv_Mod_Dis(void)
disables T13 inversion for further modulation.
Definition: ccu6.h:1783
INLINE void CCU6_T12_OM_Int_Dis(void)
disables Interrupt for T12 One-Match.
Definition: ccu6.h:4912
INLINE void CCU6_MCM_Switch_Sync_T13_ZM_Sel(void)
sets T13 zero-match Switching Synchronization.
Definition: ccu6.h:3254
INLINE void CCU6_LoadShadowRegister_CC61(uint16 tick)
Load Channel 1 compare value to the shadow register.
Definition: ccu6.h:5403
INLINE void CCU6_Ch2_Input_Sel(uint16 iscc62)
selects Input for CC62.
Definition: ccu6.h:696
INLINE void CCU6_Ch3_CompState_Set(void)
sets Capture/Compare Status Modification Bit 3 for (CC63ST) by Software.
Definition: ccu6.h:1852
INLINE void CCU6_CHE_Int_En(void)
enables Interrupt for Correct Hall Event.
Definition: ccu6.h:5114
INLINE void CCU6_MCM_Str_T12_Down_Cnt_En(void)
enables Shadow Transfer for T12 Downcounting.
Definition: ccu6.h:3322
INLINE void CCU6_CHE_Int_Dis(void)
disables Interrupt for Correct Hall Event.
Definition: ccu6.h:5137
INLINE void CCU6_T13_Modulation_En(uint16 ccu6_mask)
enables Timer T13 Modulation Configuration
Definition: ccu6.h:2339
TCCU6_T13TEC
This enum lists the CCU6 T13 Trigger Event Control.
Definition: ccu6.h:328
@ CCU6_T13TEC_CCPOSx
Definition: ccu6.h:336
@ CCU6_T13TEC_T12_CM_Ch0
Definition: ccu6.h:330
@ CCU6_T13TEC_T12_PM
Definition: ccu6.h:334
@ CCU6_T13TEC_T12_CM_Chx
Definition: ccu6.h:333
@ CCU6_T13TEC_T12_CM_Ch2
Definition: ccu6.h:332
@ CCU6_T13TEC_No_Trigger
Definition: ccu6.h:329
@ CCU6_T13TEC_T12_CM_Ch1
Definition: ccu6.h:331
@ CCU6_T13TEC_T12_ZM
Definition: ccu6.h:335
INLINE void CCU6_T13_Ext_Input_Sel(uint16 t13ext)
selects Input of Extension for T13HR.
Definition: ccu6.h:894
INLINE void CCU6_Hall_Delay_Bypass_En(void)
enables Hall Delay Bypass.
Definition: ccu6.h:911
INLINE void CCU6_Hall_Wrong_Int_Set(void)
sets Interrupt for Wrong Hall Event flag.
Definition: ccu6.h:4071
INLINE void CCU6_T12_Rst(void)
resets CCU6 T12.
Definition: ccu6.h:465
INLINE void CCU6_CH0_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 0.
Definition: ccu6.h:4311
INLINE void CCU6_Ch1_CompState_Rst(void)
resets Capture/Compare Status Modification Bit 1 for CC61ST by Software.
Definition: ccu6.h:1886
INLINE uint8 CCU6_T12_CM_CC60_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 0.
Definition: ccu6.h:3397
INLINE uint8 CCU6_Ch3_CompState_Sts(void)
reads CC63 Capture/Compare State.
Definition: ccu6.h:1627
TCCU6_Ch1_Input
This enum lists the CCU6 channel 1 Inputs.
Definition: ccu6.h:179
@ CCU6_CC61_0_P10
Definition: ccu6.h:180
@ CCU6_CC61_1_P21
Definition: ccu6.h:181
TCCU6_T12_Cnt_Input
This enum lists the CCU6 ISCNT12 Inputs.
Definition: ccu6.h:258
@ CCU6_T12HR_Rising_Edge
Definition: ccu6.h:261
@ CCU6_TCTR4_T12CNT
Definition: ccu6.h:260
@ CCU6_T12_Prescaler
Definition: ccu6.h:259
@ CCU6_T12HR_Falling_Edge
Definition: ccu6.h:262
TCCU6_T13_Cnt_Input
This enum lists the CCU6 ISCNT13 Inputs.
Definition: ccu6.h:269
@ CCU6_TCTR4_T13CNT
Definition: ccu6.h:271
@ CCU6_T13HR_Falling_Edge
Definition: ccu6.h:273
@ CCU6_T13HR_Rising_Edge
Definition: ccu6.h:272
@ CCU6_T13_Prescaler
Definition: ccu6.h:270
INLINE void CCU6_T12_Single_Shot_Dis(void)
disables Timer T12 Single Shot.
Definition: ccu6.h:2206
INLINE void CCU6_T13_Prescaler_En(void)
enables additional prescaler for Timer T13.
Definition: ccu6.h:2045
INLINE void CCU6_Ch1_CompState_Set(void)
sets Capture/Compare Status Modification Bit 1 for (CC61ST) by Software.
Definition: ccu6.h:1818
INLINE void CCU6_T13_Prescaler_Dis(void)
disables additional prescaler for Timer T13.
Definition: ccu6.h:2062
INLINE void CCU6_Trap_Input_Sel(uint16 istrp)
selects Input for CTRAP.
Definition: ccu6.h:715
INLINE void CCU6_T13_Cnt(void)
counts 1 step for CCU6 T13 Event.
Definition: ccu6.h:605
INLINE void CCU6_CH2_CM_R_Int_Clr(void)
clears Capture, Compare-Match Rising Edge Interrupt flag for Channel 2.
Definition: ccu6.h:4399
INLINE void CCU6_T13_Stop(void)
stops CCU6 T13.
Definition: ccu6.h:552
INLINE void CCU6_Multi_Ch_Mode_Dis(void)
disables Multi-Channel Mode
Definition: ccu6.h:2392
INLINE void CCU6_T12_Stop(void)
stops CCU6 T12.
Definition: ccu6.h:431
INLINE uint8 CCU6_T12_CM_CC62_Int_Rise_Sts(void)
reads Capture, Compare-Match Rising Edge Flag Status for Channel 2.
Definition: ccu6.h:3445
INLINE void CCU6_Trap_Pin_Dis(void)
disables the trap functionality based on the input pin CTRAP.
Definition: ccu6.h:2579
INLINE void CCU6_Ch0_Value_Set(uint16 cc60sr)
sets Channel 0 Capture/Compare Value.
Definition: ccu6.h:1127
INLINE uint8 CCU6_MCM_Str_Int_Sts(void)
reads Multi-Channel Mode Shadow Transfer Request Status.
Definition: ccu6.h:3755
INLINE uint8 CCU6_Trap_State_Int_Sts(void)
reads Trap Status.
Definition: ccu6.h:3661
INLINE void CCU6_MCM_Expected_Hall_Shadow_Reg_Load(uint16 mcm_mask_ccpos)
sets Expected Hall Pattern Shadow of CCPOSx.
Definition: ccu6.h:2961
INLINE void CCU6_SetT13Compare(uint16 Compare)
Sets compare value for the T13 timer.
Definition: ccu6.h:5548
INLINE void CCU6_Ch0c_Passive_Level_Low_Set(void)
sets Passive Low Level of COUT60.
Definition: ccu6.h:2701
INLINE void CCU6_StopTmr_T12(void)
Stop CCU6 Timer T12.
Definition: ccu6.h:5314
TCCU6_T13RSEL
This enum lists the CCU6 T13 Run Select.
Definition: ccu6.h:365
@ CCU6_T13RSEL_Dis
Definition: ccu6.h:366
@ CCU6_T13RSEL_T13HR_Any
Definition: ccu6.h:369
@ CCU6_T13RSEL_T13HR_Fall
Definition: ccu6.h:368
@ CCU6_T13RSEL_T13HR_Rise
Definition: ccu6.h:367
INLINE void CCU6_T13_Modulation_Dis(uint16 ccu6_mask)
disables Timer T13 Modulation Configuration
Definition: ccu6.h:2358
TCCU6_Trap_Input
This enum lists the CCU6 Trap Inputs.
Definition: ccu6.h:197
@ CCU6_DU1_UP_STS
Definition: ccu6.h:201
@ CCU6_CTRAP_0_P02
Definition: ccu6.h:198
@ CCU6_CTRAP_1_P23
Definition: ccu6.h:199
@ CCU6_CTRAP_2_P22
Definition: ccu6.h:200
INLINE void CCU6_STR_Int_En(void)
enables Multi-Channel Mode Shadow Transfer Interrupt.
Definition: ccu6.h:5204
INLINE void CCU6_MCM_Switch_T12_PM_Set(void)
sets T12 period-match Switching Mode.
Definition: ccu6.h:3220
TCCU6_Pos1_Input
This enum lists the CCU6 ISPOS1 Inputs.
Definition: ccu6.h:218
@ CCU6_CCPOS1_1_P04
Definition: ccu6.h:220
@ CCU6_CCPOS1_0_P23
Definition: ccu6.h:219
@ CCU6_CCPOS1_2_P14
Definition: ccu6.h:221
INLINE void CCU6_T12_Clk_Sel(uint16 t12clk)
selects Timer T12 Input Clock.
Definition: ccu6.h:1974
INLINE void CCU6_MCM_Switch_Sync_T12_ZM_Sel(void)
sets T12 zero-match Switching Synchronization.
Definition: ccu6.h:3271
INLINE void CCU6_T12_Cnt_Input_Sel(uint16 iscnt12)
selects Input for T12 Counting.
Definition: ccu6.h:833
INLINE void CCU6_T12_Count_Value_Set(uint16 t12cv)
sets Timer T12 Counter Value.
Definition: ccu6.h:1045
TCCU6_PSL63
This enum lists the CCU6 COUT63 Passive Level.
Definition: ccu6.h:376
@ CCU6_PSL63_Low
Definition: ccu6.h:377
@ CCU6_PSL63_High
Definition: ccu6.h:378
INLINE void CCU6_T13_Clk_Sel(uint16 t13clk)
selects Timer T13 Input Clock.
Definition: ccu6.h:1994
INLINE void CCU6_MCM_Switch_T12_Ch1_CM_Set(void)
sets T12 channel1 compare-match Switching Mode.
Definition: ccu6.h:3203
INLINE void CCU6_WHE_Int_En(void)
enables Interrupt for Wrong Hall Event.
Definition: ccu6.h:5159
INLINE void CCU6_Ch2c_Passive_Level_High_Set(void)
sets Passive High Level of COUT62.
Definition: ccu6.h:2820
INLINE void CCU6_Ch0_Int_Node_Sel(uint16 srx)
selects Interrupt Node Pointer for Channel 0 Interrupts.
Definition: ccu6.h:4139
INLINE void CCU6_LoadShadowRegister_CC63(uint16 tick)
Load Channel 3 compare value to the shadow register.
Definition: ccu6.h:5441
#define CCU6
Definition: tle985x.h:6268
#define CCU6_PISEL0_ISTRP_Pos
Definition: tle985x.h:8316
#define CCU6_T12DTC_DTE2_Pos
Definition: tle985x.h:8350
#define CCU6_IS_T12PM_Msk
Definition: tle985x.h:8188
#define CCU6_INP_INPT13_Msk
Definition: tle985x.h:8157
#define CCU6_CMPSTAT_CC60ST_Pos
Definition: tle985x.h:8122
#define CCU6_ISR_RCC61F_Pos
Definition: tle985x.h:8226
#define CCU6_CC63R_CCV_Pos
Definition: tle985x.h:8071
#define CCU6_ISS_SCC60R_Msk
Definition: tle985x.h:8266
#define CCU6_TCTR4_T12STR_Msk
Definition: tle985x.h:8428
#define CCU6_TCTR4_T13RES_Msk
Definition: tle985x.h:8420
#define CCU6_CMPSTAT_CCPOS1_Msk
Definition: tle985x.h:8115
#define CCU6_T12MSEL_HSYNC_Pos
Definition: tle985x.h:8361
#define CCU6_TRPCTR_TRPM10_Pos
Definition: tle985x.h:8448
#define CCU6_TCTR4_DTRES_Msk
Definition: tle985x.h:8432
#define CCU6_CMPSTAT_T13IM_Msk
Definition: tle985x.h:8095
#define CCU6_CMPSTAT_CC61ST_Msk
Definition: tle985x.h:8121
#define CCU6_IS_IDLE_Msk
Definition: tle985x.h:8174
#define CCU6_INP_INPERR_Pos
Definition: tle985x.h:8160
#define CCU6_PISEL2_T12EXT_Pos
Definition: tle985x.h:8327
#define CCU6_CMPSTAT_COUT63PS_Msk
Definition: tle985x.h:8097
#define CCU6_PISEL0_ISTRP_Msk
Definition: tle985x.h:8317
#define CCU6_PISEL2_T13EXT_Msk
Definition: tle985x.h:8326
#define CCU6_PISEL0_ISPOS1_Pos
Definition: tle985x.h:8312
#define CCU6_ISR_RCC61F_Msk
Definition: tle985x.h:8227
#define CCU6_ISR_RT13CM_Msk
Definition: tle985x.h:8217
#define CCU6_TCTR0_STE12_Pos
Definition: tle985x.h:8391
#define CCU6_IS_TRPS_Pos
Definition: tle985x.h:8179
#define CCU6_ISS_ST12OM_Msk
Definition: tle985x.h:8254
#define CCU6_ISR_RSTR_Msk
Definition: tle985x.h:8205
#define CCU6_CMPMODIF_MCC60R_Msk
Definition: tle985x.h:8084
#define CCU6_ISS_ST13PM_Msk
Definition: tle985x.h:8248
#define CCU6_ISR_RCC62F_Msk
Definition: tle985x.h:8223
#define CCU6_IS_T12OM_Msk
Definition: tle985x.h:8190
#define CCU6_IEN_ENT12OM_Pos
Definition: tle985x.h:8141
#define CCU6_ISS_SCHE_Pos
Definition: tle985x.h:8241
#define CCU6_IEN_ENCC61F_Pos
Definition: tle985x.h:8147
#define CCU6_ISS_SIDLE_Pos
Definition: tle985x.h:8237
#define CCU6_ISR_RT13PM_Msk
Definition: tle985x.h:8215
#define CCU6_MCMCTR_SWSEL_Msk
Definition: tle985x.h:8277
#define CCU6_MCMCTR_STE12D_Pos
Definition: tle985x.h:8270
#define CCU6_CC61R_CCV_Pos
Definition: tle985x.h:8059
#define CCU6_ISR_RTRPF_Msk
Definition: tle985x.h:8213
#define CCU6_MCMOUTS_EXPHS_Pos
Definition: tle985x.h:8292
#define CCU6_IS_STR_Pos
Definition: tle985x.h:8171
#define CCU6_INP_INPCC61_Pos
Definition: tle985x.h:8166
#define CCU6_CC62R_CCV_Msk
Definition: tle985x.h:8066
#define CCU6_IS_WHE_Pos
Definition: tle985x.h:8175
#define CCU6_PISEL0_IST12HR_Msk
Definition: tle985x.h:8309
#define CCU6_PISEL0_ISCC60_Msk
Definition: tle985x.h:8323
#define CCU6_ISS_SWHE_Msk
Definition: tle985x.h:8240
#define CCU6_CMPMODIF_MCC63R_Pos
Definition: tle985x.h:8077
#define CCU6_TRPCTR_TRPM10_Msk
Definition: tle985x.h:8449
#define CCU6_INP_INPCC62_Msk
Definition: tle985x.h:8165
#define CCU6_IS_ICC60R_Pos
Definition: tle985x.h:8201
#define CCU6_ISS_SCC62F_Pos
Definition: tle985x.h:8255
#define CCU6_TCTR0_T13CLK_Pos
Definition: tle985x.h:8385
#define CCU6_ISR_RT12PM_Pos
Definition: tle985x.h:8218
#define CCU6_T12DTC_DTR1_Pos
Definition: tle985x.h:8346
#define CCU6_MODCTR_T12MODEN_Msk
Definition: tle985x.h:8306
#define CCU6_IEN_ENT12PM_Pos
Definition: tle985x.h:8139
#define CCU6_IEN_ENSTR_Msk
Definition: tle985x.h:8126
#define CCU6_PISEL2_ISCNT13_Pos
Definition: tle985x.h:8329
#define CCU6_TCTR0_T12R_Pos
Definition: tle985x.h:8393
#define CCU6_TRPCTR_TRPM2_Msk
Definition: tle985x.h:8447
#define CCU6_INP_INPERR_Msk
Definition: tle985x.h:8161
#define CCU6_CMPSTAT_CCPOS2_Pos
Definition: tle985x.h:8112
#define CCU6_IS_ICC62R_Msk
Definition: tle985x.h:8194
#define CCU6_TCTR0_STE12_Msk
Definition: tle985x.h:8392
#define CCU6_IEN_ENCC60R_Pos
Definition: tle985x.h:8153
#define CCU6_MCMOUTS_STRMCM_Msk
Definition: tle985x.h:8295
#define CCU6_IS_T13CM_Pos
Definition: tle985x.h:8185
#define CCU6_MCMCTR_STE12U_Pos
Definition: tle985x.h:8272
#define CCU6_PISEL0_ISPOS1_Msk
Definition: tle985x.h:8313
#define CCU6_TCTR0_T13PRE_Pos
Definition: tle985x.h:8383
#define CCU6_IEN_ENCC62F_Pos
Definition: tle985x.h:8143
#define CCU6_IS_STR_Msk
Definition: tle985x.h:8172
#define CCU6_TCTR4_T12RR_Pos
Definition: tle985x.h:8437
#define CCU6_ISR_RCC60F_Msk
Definition: tle985x.h:8231
#define CCU6_IEN_ENCC60R_Msk
Definition: tle985x.h:8154
#define CCU6_MCMOUT_MCMP_Pos
Definition: tle985x.h:8285
#define CCU6_MCMCTR_STE12D_Msk
Definition: tle985x.h:8271
#define CCU6_PISEL2_IST13HR_Msk
Definition: tle985x.h:8334
#define CCU6_T12DTC_DTE0_Msk
Definition: tle985x.h:8355
#define CCU6_TCTR4_T13RES_Pos
Definition: tle985x.h:8419
#define CCU6_T13_T13CV_Pos
Definition: tle985x.h:8373
#define CCU6_CMPSTAT_CC62ST_Pos
Definition: tle985x.h:8118
#define CCU6_IEN_ENTRPF_Msk
Definition: tle985x.h:8134
#define CCU6_TCTR2_T13RSEL_Msk
Definition: tle985x.h:8401
#define CCU6_IS_ICC61R_Pos
Definition: tle985x.h:8197
#define CCU6_T12MSEL_MSEL60_Msk
Definition: tle985x.h:8368
#define CCU6_TCTR2_T13TED_Pos
Definition: tle985x.h:8404
#define CCU6_TCTR4_T12STR_Pos
Definition: tle985x.h:8427
#define CCU6_T12MSEL_MSEL60_Pos
Definition: tle985x.h:8367
#define CCU6_PISEL0_ISPOS2_Pos
Definition: tle985x.h:8310
#define CCU6_CMPSTAT_CC60ST_Msk
Definition: tle985x.h:8123
#define CCU6_ISS_SCC62R_Pos
Definition: tle985x.h:8257
#define CCU6_MCMOUTS_MCMPS_Pos
Definition: tle985x.h:8296
#define CCU6_TCTR4_T13STR_Pos
Definition: tle985x.h:8415
#define CCU6_ISR_RCC60R_Msk
Definition: tle985x.h:8233
#define CCU6_TCTR0_T12PRE_Pos
Definition: tle985x.h:8395
#define CCU6_ISS_STRPF_Msk
Definition: tle985x.h:8246
#define CCU6_IS_ICC60F_Pos
Definition: tle985x.h:8199
#define CCU6_IS_WHE_Msk
Definition: tle985x.h:8176
#define CCU6_ISS_ST13PM_Pos
Definition: tle985x.h:8247
#define CCU6_PSLR_PSL63_Msk
Definition: tle985x.h:8337
#define CCU6_TCTR4_T12STD_Msk
Definition: tle985x.h:8426
#define CCU6_PSLR_PSL63_Pos
Definition: tle985x.h:8336
#define CCU6_T13PR_T13PV_Msk
Definition: tle985x.h:8377
#define CCU6_MCMOUT_R_Msk
Definition: tle985x.h:8284
#define CCU6_MCMOUT_MCMP_Msk
Definition: tle985x.h:8286
#define CCU6_CMPMODIF_MCC62S_Msk
Definition: tle985x.h:8088
#define CCU6_CMPMODIF_MCC61S_Pos
Definition: tle985x.h:8089
#define CCU6_CMPMODIF_MCC60S_Msk
Definition: tle985x.h:8092
#define CCU6_T12_T12CV_Pos
Definition: tle985x.h:8341
#define CCU6_ISR_RTRPF_Pos
Definition: tle985x.h:8212
#define CCU6_TRPCTR_TRPPEN_Pos
Definition: tle985x.h:8440
#define CCU6_CMPSTAT_CCPOS2_Msk
Definition: tle985x.h:8113
#define CCU6_IS_ICC61F_Pos
Definition: tle985x.h:8195
#define CCU6_MCMOUT_EXPH_Pos
Definition: tle985x.h:8281
#define CCU6_T12PR_T12PV_Pos
Definition: tle985x.h:8370
#define CCU6_ISR_RSTR_Pos
Definition: tle985x.h:8204
#define CCU6_CMPMODIF_MCC61R_Msk
Definition: tle985x.h:8082
#define CCU6_IS_T13CM_Msk
Definition: tle985x.h:8186
#define CCU6_PSLR_PSL_Pos
Definition: tle985x.h:8338
#define CCU6_IEN_ENCC60F_Pos
Definition: tle985x.h:8151
#define CCU6_TCTR2_T12RSEL_Msk
Definition: tle985x.h:8403
#define CCU6_T12DTC_DTE1_Pos
Definition: tle985x.h:8352
#define CCU6_T12DTC_DTE2_Msk
Definition: tle985x.h:8351
#define CCU6_TCTR4_T12CNT_Msk
Definition: tle985x.h:8430
#define CCU6_IEN_ENCC62R_Msk
Definition: tle985x.h:8146
#define CCU6_TCTR4_T12RS_Msk
Definition: tle985x.h:8436
#define CCU6_ISR_RT13CM_Pos
Definition: tle985x.h:8216
#define CCU6_ISS_SCC61R_Pos
Definition: tle985x.h:8261
#define CCU6_TCTR0_CTM_Msk
Definition: tle985x.h:8388
#define CCU6_TCTR0_T12R_Msk
Definition: tle985x.h:8394
#define CCU6_MCMOUT_CURH_Pos
Definition: tle985x.h:8279
#define CCU6_ISS_SIDLE_Msk
Definition: tle985x.h:8238
#define CCU6_CMPSTAT_CCPOS0_Msk
Definition: tle985x.h:8117
#define CCU6_ISS_SWHC_Pos
Definition: tle985x.h:8243
#define CCU6_PISEL0_ISPOS0_Msk
Definition: tle985x.h:8315
#define CCU6_PISEL0_ISPOS0_Pos
Definition: tle985x.h:8314
#define CCU6_ISS_SCC60F_Pos
Definition: tle985x.h:8263
#define CCU6_IEN_ENCC61R_Pos
Definition: tle985x.h:8149
#define CCU6_INP_INPCHE_Msk
Definition: tle985x.h:8163
#define CCU6_ISS_ST13CM_Pos
Definition: tle985x.h:8249
#define CCU6_IEN_ENT13CM_Msk
Definition: tle985x.h:8138
#define CCU6_TCTR0_CDIR_Pos
Definition: tle985x.h:8389
#define CCU6_TCTR4_T13CNT_Msk
Definition: tle985x.h:8418
#define CCU6_T12_T12CV_Msk
Definition: tle985x.h:8342
#define CCU6_TCTR2_T12SSC_Pos
Definition: tle985x.h:8410
#define CCU6_INP_INPT12_Pos
Definition: tle985x.h:8158
#define CCU6_TCTR0_CDIR_Msk
Definition: tle985x.h:8390
#define CCU6_ISR_RCC62R_Pos
Definition: tle985x.h:8224
#define CCU6_IS_T13PM_Msk
Definition: tle985x.h:8184
#define CCU6_MODCTR_MCMEN_Pos
Definition: tle985x.h:8303
#define CCU6_CMPSTAT_CC61ST_Pos
Definition: tle985x.h:8120
#define CCU6_INP_INPCC60_Pos
Definition: tle985x.h:8168
#define CCU6_TRPCTR_TRPM2_Pos
Definition: tle985x.h:8446
#define CCU6_TRPCTR_TRPEN_Msk
Definition: tle985x.h:8445
#define CCU6_TRPCTR_TRPEN13_Pos
Definition: tle985x.h:8442
#define CCU6_TCTR4_T13RR_Pos
Definition: tle985x.h:8423
#define CCU6_TCTR0_STE13_Msk
Definition: tle985x.h:8380
#define CCU6_TCTR0_T13CLK_Msk
Definition: tle985x.h:8386
#define CCU6_TRPCTR_TRPPEN_Msk
Definition: tle985x.h:8441
#define CCU6_TRPCTR_TRPEN13_Msk
Definition: tle985x.h:8443
#define CCU6_ISR_RWHE_Pos
Definition: tle985x.h:8208
#define CCU6_IEN_ENCC62R_Pos
Definition: tle985x.h:8145
#define CCU6_TCTR4_T12CNT_Pos
Definition: tle985x.h:8429
#define CCU6_TCTR4_T13RS_Msk
Definition: tle985x.h:8422
#define CCU6_T12DTC_DTM_Msk
Definition: tle985x.h:8357
#define CCU6_CMPMODIF_MCC63R_Msk
Definition: tle985x.h:8078
#define CCU6_IEN_ENCC60F_Msk
Definition: tle985x.h:8152
#define CCU6_TCTR4_T13RR_Msk
Definition: tle985x.h:8424
#define CCU6_T12MSEL_HSYNC_Msk
Definition: tle985x.h:8362
#define CCU6_T12MSEL_MSEL61_Msk
Definition: tle985x.h:8366
#define CCU6_TCTR0_T12PRE_Msk
Definition: tle985x.h:8396
#define CCU6_TCTR2_T13RSEL_Pos
Definition: tle985x.h:8400
#define CCU6_CMPMODIF_MCC62S_Pos
Definition: tle985x.h:8087
#define CCU6_IS_ICC60R_Msk
Definition: tle985x.h:8202
#define CCU6_CMPSTAT_CCPOS0_Pos
Definition: tle985x.h:8116
#define CCU6_ISS_SWHE_Pos
Definition: tle985x.h:8239
#define CCU6_ISR_RCC62R_Msk
Definition: tle985x.h:8225
#define CCU6_CMPMODIF_MCC60S_Pos
Definition: tle985x.h:8091
#define CCU6_T12MSEL_DBYP_Pos
Definition: tle985x.h:8359
#define CCU6_IS_ICC62R_Pos
Definition: tle985x.h:8193
#define CCU6_TCTR4_T13STD_Pos
Definition: tle985x.h:8413
#define CCU6_ISR_RCC61R_Msk
Definition: tle985x.h:8229
#define CCU6_INP_INPCHE_Pos
Definition: tle985x.h:8162
#define CCU6_CMPMODIF_MCC63S_Msk
Definition: tle985x.h:8086
#define CCU6_TCTR4_T13CNT_Pos
Definition: tle985x.h:8417
#define CCU6_CC60R_CCV_Msk
Definition: tle985x.h:8054
#define CCU6_MCMOUTS_STRHP_Msk
Definition: tle985x.h:8289
#define CCU6_INP_INPCC62_Pos
Definition: tle985x.h:8164
#define CCU6_INP_INPT12_Msk
Definition: tle985x.h:8159
#define CCU6_IS_CHE_Pos
Definition: tle985x.h:8177
#define CCU6_TCTR0_T13PRE_Msk
Definition: tle985x.h:8384
#define CCU6_CMPMODIF_MCC60R_Pos
Definition: tle985x.h:8083
#define CCU6_T12MSEL_MSEL62_Pos
Definition: tle985x.h:8363
#define CCU6_IEN_ENCHE_Msk
Definition: tle985x.h:8132
#define CCU6_TCTR4_DTRES_Pos
Definition: tle985x.h:8431
#define CCU6_TRPCTR_TRPEN_Pos
Definition: tle985x.h:8444
#define CCU6_T12MSEL_MSEL62_Msk
Definition: tle985x.h:8364
#define CCU6_CMPSTAT_CC60PS_Pos
Definition: tle985x.h:8108
#define CCU6_ISR_RT12OM_Msk
Definition: tle985x.h:8221
#define CCU6_CC62R_CCV_Pos
Definition: tle985x.h:8065
#define CCU6_PISEL0_ISCC62_Msk
Definition: tle985x.h:8319
#define CCU6_CMPSTAT_CC63ST_Pos
Definition: tle985x.h:8110
#define CCU6_CMPMODIF_MCC62R_Msk
Definition: tle985x.h:8080
#define CCU6_ISR_RCC60R_Pos
Definition: tle985x.h:8232
#define CCU6_MODCTR_T12MODEN_Pos
Definition: tle985x.h:8305
#define CCU6_MCMOUTS_CURHS_Pos
Definition: tle985x.h:8290
#define CCU6_MCMCTR_STE13U_Msk
Definition: tle985x.h:8269
#define CCU6_MODCTR_T13MODEN_Pos
Definition: tle985x.h:8301
#define CCU6_ISS_SCC61F_Pos
Definition: tle985x.h:8259
#define CCU6_MCMOUTS_MCMPS_Msk
Definition: tle985x.h:8297
#define CCU6_MODCTR_ECT13O_Pos
Definition: tle985x.h:8299
#define CCU6_CMPMODIF_MCC62R_Pos
Definition: tle985x.h:8079
#define CCU6_IEN_ENCC61R_Msk
Definition: tle985x.h:8150
#define CCU6_TCTR4_T12RS_Pos
Definition: tle985x.h:8435
#define CCU6_T12DTC_DTR0_Msk
Definition: tle985x.h:8349
#define CCU6_TCTR2_T13TED_Msk
Definition: tle985x.h:8405
#define CCU6_MCMOUTS_CURHS_Msk
Definition: tle985x.h:8291
#define CCU6_T13PR_T13PV_Pos
Definition: tle985x.h:8376
#define CCU6_PISEL2_T13EXT_Pos
Definition: tle985x.h:8325
#define CCU6_TCTR0_T12CLK_Pos
Definition: tle985x.h:8397
#define CCU6_PISEL0_ISCC62_Pos
Definition: tle985x.h:8318
#define CCU6_PSLR_PSL_Msk
Definition: tle985x.h:8339
#define CCU6_ISR_RCHE_Pos
Definition: tle985x.h:8210
#define CCU6_PISEL0_ISPOS2_Msk
Definition: tle985x.h:8311
#define CCU6_T12MSEL_MSEL61_Pos
Definition: tle985x.h:8365
#define CCU6_PISEL2_ISCNT13_Msk
Definition: tle985x.h:8330
#define CCU6_IEN_ENCC61F_Msk
Definition: tle985x.h:8148
#define CCU6_TCTR2_T13TEC_Msk
Definition: tle985x.h:8407
#define CCU6_ISR_RWHE_Msk
Definition: tle985x.h:8209
#define CCU6_TCTR0_T13R_Msk
Definition: tle985x.h:8382
#define CCU6_T12DTC_DTR1_Msk
Definition: tle985x.h:8347
#define CCU6_IEN_ENCHE_Pos
Definition: tle985x.h:8131
#define CCU6_TCTR0_T12CLK_Msk
Definition: tle985x.h:8398
#define CCU6_TCTR4_T12RES_Pos
Definition: tle985x.h:8433
#define CCU6_TCTR2_T13TEC_Pos
Definition: tle985x.h:8406
#define CCU6_MODCTR_MCMEN_Msk
Definition: tle985x.h:8304
#define CCU6_TCTR0_T13R_Pos
Definition: tle985x.h:8381
#define CCU6_PISEL2_ISCNT12_Msk
Definition: tle985x.h:8332
#define CCU6_CMPMODIF_MCC61R_Pos
Definition: tle985x.h:8081
#define CCU6_ISS_ST12PM_Msk
Definition: tle985x.h:8252
#define CCU6_IEN_ENT13PM_Msk
Definition: tle985x.h:8136
#define CCU6_IEN_ENWHE_Pos
Definition: tle985x.h:8129
#define CCU6_ISR_RCC61R_Pos
Definition: tle985x.h:8228
#define CCU6_IS_TRPF_Pos
Definition: tle985x.h:8181
#define CCU6_ISS_SCC62F_Msk
Definition: tle985x.h:8256
#define CCU6_MCMCTR_SWSYN_Msk
Definition: tle985x.h:8275
#define CCU6_T13_T13CV_Msk
Definition: tle985x.h:8374
#define CCU6_MCMOUT_R_Pos
Definition: tle985x.h:8283
#define CCU6_ISR_RT12PM_Msk
Definition: tle985x.h:8219
#define CCU6_ISS_ST12PM_Pos
Definition: tle985x.h:8251
#define CCU6_TCTR2_T12SSC_Msk
Definition: tle985x.h:8411
#define CCU6_IS_T12PM_Pos
Definition: tle985x.h:8187
#define CCU6_INP_INPT13_Pos
Definition: tle985x.h:8156
#define CCU6_IS_ICC60F_Msk
Definition: tle985x.h:8200
#define CCU6_TCTR4_T12STD_Pos
Definition: tle985x.h:8425
#define CCU6_CMPSTAT_CC62ST_Msk
Definition: tle985x.h:8119
#define CCU6_CMPSTAT_CC63ST_Msk
Definition: tle985x.h:8111
#define CCU6_IS_T13PM_Pos
Definition: tle985x.h:8183
#define CCU6_ISS_SCC60F_Msk
Definition: tle985x.h:8264
#define CCU6_TCTR2_T12RSEL_Pos
Definition: tle985x.h:8402
#define CCU6_ISR_RT13PM_Pos
Definition: tle985x.h:8214
#define CCU6_ISS_SCC62R_Msk
Definition: tle985x.h:8258
#define CCU6_MCMOUTS_EXPHS_Msk
Definition: tle985x.h:8293
#define CCU6_TCTR0_STE13_Pos
Definition: tle985x.h:8379
#define CCU6_ISS_SCHE_Msk
Definition: tle985x.h:8242
#define CCU6_MCMOUTS_STRHP_Pos
Definition: tle985x.h:8288
#define CCU6_PISEL0_ISCC61_Pos
Definition: tle985x.h:8320
#define CCU6_TCTR0_CTM_Pos
Definition: tle985x.h:8387
#define CCU6_MCMOUTS_STRMCM_Pos
Definition: tle985x.h:8294
#define CCU6_CC63R_CCV_Msk
Definition: tle985x.h:8072
#define CCU6_IS_ICC62F_Pos
Definition: tle985x.h:8191
#define CCU6_TCTR4_T12RR_Msk
Definition: tle985x.h:8438
#define CCU6_IS_TRPF_Msk
Definition: tle985x.h:8182
#define CCU6_ISS_SSTR_Msk
Definition: tle985x.h:8236
#define CCU6_CMPSTAT_COUT63PS_Pos
Definition: tle985x.h:8096
#define CCU6_MCMCTR_STE12U_Msk
Definition: tle985x.h:8273
#define CCU6_TCTR4_T13STD_Msk
Definition: tle985x.h:8414
#define CCU6_IEN_ENT13CM_Pos
Definition: tle985x.h:8137
#define CCU6_CMPSTAT_T13IM_Pos
Definition: tle985x.h:8094
#define CCU6_IS_ICC62F_Msk
Definition: tle985x.h:8192
#define CCU6_PISEL2_T12EXT_Msk
Definition: tle985x.h:8328
#define CCU6_IEN_ENTRPF_Pos
Definition: tle985x.h:8133
#define CCU6_IS_ICC61R_Msk
Definition: tle985x.h:8198
#define CCU6_IS_T12OM_Pos
Definition: tle985x.h:8189
#define CCU6_IEN_ENT13PM_Pos
Definition: tle985x.h:8135
#define CCU6_CMPMODIF_MCC63S_Pos
Definition: tle985x.h:8085
#define CCU6_MCMOUT_EXPH_Msk
Definition: tle985x.h:8282
#define CCU6_PISEL0_ISCC61_Msk
Definition: tle985x.h:8321
#define CCU6_ISS_ST12OM_Pos
Definition: tle985x.h:8253
#define CCU6_ISR_RCHE_Msk
Definition: tle985x.h:8211
#define CCU6_IEN_ENSTR_Pos
Definition: tle985x.h:8125
#define CCU6_MCMCTR_SWSEL_Pos
Definition: tle985x.h:8276
#define CCU6_TCTR4_T13RS_Pos
Definition: tle985x.h:8421
#define CCU6_ISS_SCC61F_Msk
Definition: tle985x.h:8260
#define CCU6_MCMOUT_CURH_Msk
Definition: tle985x.h:8280
#define CCU6_T12DTC_DTE1_Msk
Definition: tle985x.h:8353
#define CCU6_IS_ICC61F_Msk
Definition: tle985x.h:8196
#define CCU6_T12DTC_DTE0_Pos
Definition: tle985x.h:8354
#define CCU6_T12DTC_DTR2_Pos
Definition: tle985x.h:8344
#define CCU6_T12DTC_DTR2_Msk
Definition: tle985x.h:8345
#define CCU6_CC60R_CCV_Pos
Definition: tle985x.h:8053
#define CCU6_ISS_SCC60R_Pos
Definition: tle985x.h:8265
#define CCU6_MODCTR_T13MODEN_Msk
Definition: tle985x.h:8302
#define CCU6_PISEL2_ISCNT12_Pos
Definition: tle985x.h:8331
#define CCU6_ISR_RCC62F_Pos
Definition: tle985x.h:8222
#define CCU6_IEN_ENWHE_Msk
Definition: tle985x.h:8130
#define CCU6_T12DTC_DTM_Pos
Definition: tle985x.h:8356
#define CCU6_IEN_ENT12OM_Msk
Definition: tle985x.h:8142
#define CCU6_IEN_ENT12PM_Msk
Definition: tle985x.h:8140
#define CCU6_IS_TRPS_Msk
Definition: tle985x.h:8180
#define CCU6_T12MSEL_DBYP_Msk
Definition: tle985x.h:8360
#define CCU6_T12DTC_DTR0_Pos
Definition: tle985x.h:8348
#define CCU6_ISS_SSTR_Pos
Definition: tle985x.h:8235
#define CCU6_ISS_ST13CM_Msk
Definition: tle985x.h:8250
#define CCU6_TCTR4_T13STR_Msk
Definition: tle985x.h:8416
#define CCU6_T12PR_T12PV_Msk
Definition: tle985x.h:8371
#define CCU6_INP_INPCC60_Msk
Definition: tle985x.h:8169
#define CCU6_PISEL0_IST12HR_Pos
Definition: tle985x.h:8308
#define CCU6_CMPMODIF_MCC61S_Msk
Definition: tle985x.h:8090
#define CCU6_IS_CHE_Msk
Definition: tle985x.h:8178
#define CCU6_ISS_STRPF_Pos
Definition: tle985x.h:8245
#define CCU6_IEN_ENCC62F_Msk
Definition: tle985x.h:8144
#define CCU6_IS_IDLE_Pos
Definition: tle985x.h:8173
#define CCU6_MODCTR_ECT13O_Msk
Definition: tle985x.h:8300
#define CCU6_PISEL0_ISCC60_Pos
Definition: tle985x.h:8322
#define CCU6_ISR_RCC60F_Pos
Definition: tle985x.h:8230
#define CCU6_ISR_RT12OM_Pos
Definition: tle985x.h:8220
#define CCU6_TCTR4_T12RES_Msk
Definition: tle985x.h:8434
#define CCU6_INP_INPCC61_Msk
Definition: tle985x.h:8167
#define CCU6_PISEL2_IST13HR_Pos
Definition: tle985x.h:8333
#define CCU6_CMPSTAT_CCPOS1_Pos
Definition: tle985x.h:8114
#define CCU6_ISS_SCC61R_Msk
Definition: tle985x.h:8262
#define CCU6_MCMCTR_SWSYN_Pos
Definition: tle985x.h:8274
#define CCU6_MCMCTR_STE13U_Pos
Definition: tle985x.h:8268
#define CCU6_ISS_SWHC_Msk
Definition: tle985x.h:8244
#define CCU6_CC61R_CCV_Msk
Definition: tle985x.h:8060
SFR low level access library.
INLINE void Field_Wrt16(volatile uint16 *reg, uint8 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:353
INLINE uint8 u8_Field_Rd16(const volatile uint16 *reg, uint8 pos, uint16 msk)
This function reads a 8-bit field of a 16-bit register.
Definition: sfr_access.h:433
INLINE uint16 u16_Field_Rd16(const volatile uint16 *reg, uint8 pos, uint16 msk)
This function reads a 16-bit field of a 16-bit register.
Definition: sfr_access.h:443
INLINE void Field_Mod16(volatile uint16 *reg, uint8 pos, uint16 msk, uint16 val)
This function writes a bit field in a 16-bit register.
Definition: sfr_access.h:373
INLINE uint8 u1_Field_Rd16(const volatile uint16 *reg, uint8 pos, uint16 msk)
This function reads a 1-bit field of a 16-bit register.
Definition: sfr_access.h:418
CMSIS register HeaderFile.
Device specific memory layout defines.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155