Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields
MATH_Type Struct Reference

Detailed Description

MATH (MATH)

#include <tle985x.h>

Data Fields

__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DVDRC: 2
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   DVSRC: 2
 
      __IOM uint32_t   SUSCFG: 2
 
      __IOM uint32_t   MATH_EN: 1
 
   }   bit
 
GLBCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   MOD_REV: 8
 
      __IM uint32_t   MOD_TYPE: 8
 
      __IM uint32_t   MOD_NUMBER: 16
 
   }   bit
 
MATH_ID
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DIVEOCIEN: 1
 
      __IOM uint32_t   DIVERRIEN: 1
 
   }   bit
 
EVIER
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   DIVEOC: 1
 
      __IM uint32_t   DIVERR: 1
 
   }   bit
 
EVFR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DIVEOCS: 1
 
      __OM uint32_t   DIVERRS: 1
 
   }   bit
 
EVSFR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   DIVEOCC: 1
 
      __OM uint32_t   DIVERRC: 1
 
   }   bit
 
EVFCR
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VAL: 32
 
   }   bit
 
DVD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VAL: 32
 
   }   bit
 
DVS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   VAL: 32
 
   }   bit
 
QUOT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   VAL: 32
 
   }   bit
 
RMD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   BSY: 1
 
   }   bit
 
DIVST
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ST: 1
 
      __IOM uint32_t   STMODE: 1
 
      __IOM uint32_t   USIGN: 1
 
      __IOM uint32_t   DIVMODE: 2
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   QSCNT: 5
 
      __IOM uint32_t   QSDIR: 1
 
      __IOM uint32_t   DVDSLC: 5
 
      __IOM uint32_t   DVSSRC: 5
 
   }   bit
 
DIVCON
 

Field Documentation

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struct { ... } bit

◆ BSY

[0..0] Busy Indication

◆ 

union { ... } DIVCON

◆ DIVEOC

__IM uint32_t DIVEOC

[0..0] Divider End of Calculation Event Flag

◆ DIVEOCC

__OM uint32_t DIVEOCC

[0..0] Divider End of Calculation Event Flag Clear

◆ DIVEOCIEN

__IOM uint32_t DIVEOCIEN

[0..0] Divider End of Calculation Interrupt Enable

◆ DIVEOCS

__OM uint32_t DIVEOCS

[0..0] Divider End of Calculation Event Flag Set

◆ DIVERR

__IM uint32_t DIVERR

[1..1] Divider Error Event Flag

◆ DIVERRC

__OM uint32_t DIVERRC

[1..1] Divider Error Event Flag Clear

◆ DIVERRIEN

__IOM uint32_t DIVERRIEN

[1..1] Divider Error Interrupt Enable

◆ DIVERRS

__OM uint32_t DIVERRS

[1..1] Divider Error Event Flag Set

◆ DIVMODE

__IOM uint32_t DIVMODE

[4..3] Division Mode

◆ 

union { ... } DIVST

◆ 

union { ... } DVD

◆ DVDRC

__IOM uint32_t DVDRC

[1..0] Dividend Register Result Chaining

◆ DVDSLC

__IOM uint32_t DVDSLC

[20..16] Dividend Shift Left Count

◆ 

union { ... } DVS

◆ DVSRC

__IOM uint32_t DVSRC

[4..3] Divisor Register Result Chaining

◆ DVSSRC

__IOM uint32_t DVSSRC

[28..24] Divisor Shift Right Count

◆ 

union { ... } EVFCR

◆ 

union { ... } EVFR

◆ 

union { ... } EVIER

◆ 

union { ... } EVSFR

◆ 

union { ... } GLBCON

◆ MATH_EN

__IOM uint32_t MATH_EN

[31..31] Enable Math Module

◆ 

union { ... } MATH_ID

◆ MOD_NUMBER

__IM uint32_t MOD_NUMBER

[31..16] Module Number Value

◆ MOD_REV

__IM uint32_t MOD_REV

[7..0] Module Revision Number

◆ MOD_TYPE

__IM uint32_t MOD_TYPE

[15..8] Module Type

◆ QSCNT

__IOM uint32_t QSCNT

[12..8] Quotient Shift Count

◆ QSDIR

__IOM uint32_t QSDIR

[15..15] Quotient Shift Direction

◆ 

union { ... } QUOT

◆ reg

(@ 0x00000004) Global Control Register

(@ 0x00000008) Module Identification Register

(@ 0x0000000C) Event Interupt Enable Register

(@ 0x00000010) Event Flag Register

(@ 0x00000014) Event Flag Set Register

(@ 0x00000018) Event Flag Clear Register

(@ 0x00000020) Dividend Register

(@ 0x00000024) Divisor Register

(@ 0x00000028) Quotient Register

(@ 0x0000002C) Remainder Register

(@ 0x00000030) Divider Status Register

(@ 0x00000034) Divider Control Register

◆ RESERVED

__IM uint32_t RESERVED

< (@ 0x48013000) MATH Structure

◆ RESERVED1

__IM uint32_t RESERVED1

◆ 

union { ... } RMD

◆ ST

[0..0] Start Bit

◆ STMODE

__IOM uint32_t STMODE

[1..1] Start Mode

◆ SUSCFG

__IOM uint32_t SUSCFG

[17..16] Suspend Mode Configuration

◆ uint32_t

__IM uint32_t

◆ USIGN

__IOM uint32_t USIGN

[2..2] Unsigned Division Enable

◆ VAL [1/2]

[31..0] Dividend Value

[31..0] Divisor Value

◆ VAL [2/2]

[31..0] Quotient Value

[31..0] Remainder Value


The documentation for this struct was generated from the following file: