Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields
SSC2_Type Struct Reference

Detailed Description

SSC2 (SSC2)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MIS_0: 1
 
      __IOM uint32_t   SIS: 1
 
      __IOM uint32_t   CIS: 1
 
      __IOM uint32_t   MIS_1: 1
 
      __IOM uint32_t   GIS: 1
 
   }   bit
 
PISEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BM: 4
 
      __IOM uint32_t   HB: 1
 
      __IOM uint32_t   PH: 1
 
      __IOM uint32_t   PO: 1
 
      __IOM uint32_t   LB: 1
 
      __IOM uint32_t   TEN: 1
 
      __IOM uint32_t   REN: 1
 
      __IOM uint32_t   PEN: 1
 
      __IOM uint32_t   BEN: 1
 
      __IOM uint32_t   AREN: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   MS: 1
 
      __IOM uint32_t   EN: 1
 
      __IM uint32_t   BC: 4
 
      __IM uint32_t   TE: 1
 
      __IM uint32_t   RE: 1
 
      __IM uint32_t   PE: 1
 
      __IM uint32_t   BE: 1
 
      __IM uint32_t   BSY: 1
 
   }   bit
 
CON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TB_VALUE: 16
 
   }   bit
 
TB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   RB_VALUE: 16
 
   }   bit
 
RB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BR_VALUE: 16
 
   }   bit
 
BR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 8
 
      __OM uint32_t   TECLR: 1
 
      __OM uint32_t   RECLR: 1
 
      __OM uint32_t   PECLR: 1
 
      __OM uint32_t   BECLR: 1
 
   }   bit
 
ISRCLR
 

Field Documentation

◆ AREN

[12..12] Automatic Reset Enable

◆ BC

[19..16] Bit Count Field

◆ BE

[27..27] Baud Rate Error Flag

◆ BECLR

__OM uint32_t BECLR

[11..11] Baud Rate Error Flag Clear

◆ BEN

[11..11] Baud Rate Error Enable

◆  [1/6]

struct { ... } bit

◆  [2/6]

struct { ... } bit

◆  [3/6]

struct { ... } bit

◆  [4/6]

struct { ... } bit

◆  [5/6]

struct { ... } bit

◆  [6/6]

struct { ... } bit

◆ BM

[3..0] Data Width Selection

◆ 

union { ... } BR

◆ BR_VALUE

__IOM uint32_t BR_VALUE

[15..0] Baud Rate Timer/Reload Register Value

◆ BSY

[28..28] Busy Flag

◆ CIS

[2..2] Clock Input Select (Slave Mode only)

◆ 

union { ... } CON

◆ EN

[15..15] Enable Bit

◆ GIS

[4..4] Global SSC12 Input Select

◆ HB

[4..4] Heading Control

◆ 

union { ... } ISRCLR

◆ LB

[7..7] Loop Back Control

◆ MIS_0

__IOM uint32_t MIS_0

[0..0] Master Mode Input Select Bit 0 (Master Mode only)

◆ MIS_1

__IOM uint32_t MIS_1

[3..3] Master Mode Input Select Bit 1 (Master Mode only)

◆ MS

[14..14] Master Select

◆ PE

[26..26] Phase Error Flag

◆ PECLR

__OM uint32_t PECLR

[10..10] Phase Error Flag Clear

◆ PEN

[10..10] Phase Error Enable

◆ PH

[5..5] Clock Phase Control

◆ 

union { ... } PISEL

< (@ 0x48026000) SSC2 Structure

◆ PO

[6..6] Clock Polarity Control

◆ 

union { ... } RB

◆ RB_VALUE

__IM uint32_t RB_VALUE

[15..0] Receive Data Register Value

◆ RE

[25..25] Receive Error Flag

◆ RECLR

__OM uint32_t RECLR

[9..9] Receive Error Flag Clear

◆ reg

(@ 0x00000000) Port Input Select Register

(@ 0x00000004) Control Register

(@ 0x00000008) Transmitter Buffer Register

(@ 0x0000000C) Receiver Buffer Register

(@ 0x00000010) Baud Rate Timer Reload Register

(@ 0x00000014) Interrupt Status Register Clear

◆ REN

[9..9] Receive Error Enable

◆ SIS

[1..1] Slave Mode Input Select (Slave Mode only)

◆ 

union { ... } TB

◆ TB_VALUE

__IOM uint32_t TB_VALUE

[15..0] Transmit Data Register Value

◆ TE

[24..24] Transmit Error Flag

◆ TECLR

__OM uint32_t TECLR

[8..8] Transmit Error Flag Clear

◆ TEN

[8..8] Transmit Error Enable

◆ uint32_t

__IM uint32_t

The documentation for this struct was generated from the following file: