Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields
PORT_Type Struct Reference

Detailed Description

PORT (PORT)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP5: 1
 
      __IM   uint32_t: 10
 
      __IM uint32_t   PP0_STS: 1
 
      __IM uint32_t   PP1_STS: 1
 
      __IM uint32_t   PP2_STS: 1
 
      __IM uint32_t   PP3_STS: 1
 
      __IM uint32_t   PP4_STS: 1
 
      __IM uint32_t   PP5_STS: 1
 
   }   bit
 
P0_DATA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP5: 1
 
      __IM   uint32_t: 10
 
      __IOM uint32_t   PP0_INEN: 1
 
      __IOM uint32_t   PP1_INEN: 1
 
      __IOM uint32_t   PP2_INEN: 1
 
      __IOM uint32_t   PP3_INEN: 1
 
      __IOM uint32_t   PP4_INEN: 1
 
      __IOM uint32_t   PP5_INEN: 1
 
   }   bit
 
P0_DIR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP5: 1
 
   }   bit
 
P0_OD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP5: 1
 
   }   bit
 
P0_PUDSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP5: 1
 
   }   bit
 
P0_PUDEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP5: 1
 
   }   bit
 
P0_ALTSEL0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP5: 1
 
   }   bit
 
P0_ALTSEL1
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PP4: 1
 
      __IM uint32_t   PP0_STS: 1
 
      __IM uint32_t   PP1_STS: 1
 
      __IM uint32_t   PP2_STS: 1
 
      __IM uint32_t   PP4_STS: 1
 
   }   bit
 
P1_DATA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PP4: 1
 
      __IOM uint32_t   PP0_INEN: 1
 
      __IOM uint32_t   PP1_INEN: 1
 
      __IOM uint32_t   PP2_INEN: 1
 
      __IOM uint32_t   PP4_INEN: 1
 
   }   bit
 
P1_DIR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PP4: 1
 
   }   bit
 
P1_OD
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PP4: 1
 
   }   bit
 
P1_PUDSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PP4: 1
 
   }   bit
 
P1_PUDEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PP4: 1
 
   }   bit
 
P1_ALTSEL0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   PP4: 1
 
   }   bit
 
P1_ALTSEL1
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   PP7: 1
 
   }   bit
 
P2_DATA
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   PP7: 1
 
   }   bit
 
P2_DIR
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   PP7: 1
 
   }   bit
 
P2_PUDSEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PP0: 1
 
      __IOM uint32_t   PP1: 1
 
      __IOM uint32_t   PP2: 1
 
      __IOM uint32_t   PP3: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   PP7: 1
 
   }   bit
 
P2_PUDEN
 

Field Documentation

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union { ... } P0_ALTSEL0

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union { ... } P0_ALTSEL1

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union { ... } P0_DATA

< (@ 0x48028000) PORT Structure

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union { ... } P0_DIR

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union { ... } P0_OD

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union { ... } P0_PUDEN

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union { ... } P0_PUDSEL

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union { ... } P1_ALTSEL0

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union { ... } P1_ALTSEL1

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union { ... } P1_DATA

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union { ... } P1_DIR

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union { ... } P1_OD

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union { ... } P1_PUDEN

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union { ... } P1_PUDSEL

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union { ... } P2_DATA

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union { ... } P2_DIR

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union { ... } P2_PUDEN

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union { ... } P2_PUDSEL

◆ PP0

[0..0] Port 0 Pin 0 Data Value

[0..0] Port 0 Pin 0 Direction Control

[0..0] Port 0 Pin 0 Open Drain Mode

[0..0] Pull-Up/Pull-Down Select Port 0 Bit 0

[0..0] Pull-Up/Pull-Down Enable at Port 0 Bit 0

[0..0] See

[0..0] Port 1 Pin 0 Data Value

[0..0] Port 1 Pin 0 Direction Control

[0..0] Port 1 Pin 0 Open Drain Mode

[0..0] Pull-Up/Pull-Down Select Port 1 Bit 0

[0..0] Pull-Up/Pull-Down Enable at Port 1 Bit 0

[0..0] Port 2 Pin 0 Data Value

[0..0] Port 2 Pin 0 Driver Control

[0..0] Pull-Up/Pull-Down Select Port 2 Bit 0

[0..0] Pull-Up/Pull-Down Enable at Port 2 Bit 0

◆ PP0_INEN

__IOM uint32_t PP0_INEN

[16..16] Port 0 Pin 0 Input Schmitt Trigger enable (only valid if IO is configured as output)

[16..16] Port 1 Pin 0 Input Schmitt Trigger enable (only valid if IO is configured as output)

◆ PP0_STS

__IM uint32_t PP0_STS

[16..16] Port 0 Pin 0 Data Value (read back of Port Data when IO is configured as output)

[16..16] Port 1 Pin 0 Data Value (read back of Port Data when IO is configured as output)

◆ PP1

[1..1] Port 0 Pin 1 Data Value

[1..1] Port 0 Pin 1 Direction Control

[1..1] Port 0 Pin 1 Open Drain Mode

[1..1] Pull-Up/Pull-Down Select Port 0 Bit 1

[1..1] Pull-Up/Pull-Down Enable at Port 0 Bit 1

[1..1] See

[1..1] Port 1 Pin 1 Data Value

[1..1] Port 1 Pin 1 Direction Control

[1..1] Port 1 Pin 1 Open Drain Mode

[1..1] Pull-Up/Pull-Down Select Port 1 Bit 1

[1..1] Pull-Up/Pull-Down Enable at Port 1 Bit 1

[1..1] Port 2 Pin 1 Data Value

[1..1] Port 2 Pin 1 Driver Control

[1..1] Pull-Up/Pull-Down Select Port 2 Bit 1

[1..1] Pull-Up/Pull-Down Enable at Port 2 Bit 1

◆ PP1_INEN

__IOM uint32_t PP1_INEN

[17..17] Port 0 Pin 1 Input Schmitt Trigger enable (only valid if IO is configured as output)

[17..17] Port 1 Pin 1 Input Schmitt Trigger enable (only valid if IO is configured as output)

◆ PP1_STS

__IM uint32_t PP1_STS

[17..17] Port 0 Pin 1 Data Value (read back of Port Data when IO is configured as output)

[17..17] Port 1 Pin 1 Data Value (read back of Port Data when IO is configured as output)

◆ PP2

[2..2] Port 0 Pin 2 Data Value

[2..2] Port 0 Pin 2 Direction Control

[2..2] Port 0 Pin 2 Open Drain Mode

[2..2] Pull-Up/Pull-Down Select Port 0 Bit 2

[2..2] Pull-Up/Pull-Down Enable at Port 0 Bit 2

[2..2] See

[2..2] Port 1 Pin 2 Data Value

[2..2] Port 1 Pin 2 Direction Control

[2..2] Port 1 Pin 2 Open Drain Mode

[2..2] Pull-Up/Pull-Down Select Port 1 Bit 2

[2..2] Pull-Up/Pull-Down Enable at Port 1 Bit 2

[2..2] Port 2 Pin 2 Data Value

[2..2] Port 2 Pin 2 Driver Control

[2..2] Pull-Up/Pull-Down Select Port 2 Bit 2

[2..2] Pull-Up/Pull-Down Enable at Port 2 Bit 2

◆ PP2_INEN

__IOM uint32_t PP2_INEN

[18..18] Port 0 Pin 2 Input Schmitt Trigger enable (only valid if IO is configured as output)

[18..18] Port 1 Pin 2 Input Schmitt Trigger enable (only valid if IO is configured as output)

◆ PP2_STS

__IM uint32_t PP2_STS

[18..18] Port 0 Pin 2 Data Value (read back of Port Data when IO is configured as output)

[18..18] Port 1 Pin 2 Data Value (read back of Port Data when IO is configured as output)

◆ PP3

[3..3] Port 0 Pin 3 Data Value

[3..3] Port 0 Pin 3 Direction Control

[3..3] Port 0 Pin 3 Open Drain Mode

[3..3] Pull-Up/Pull-Down Select Port 0 Bit 3

[3..3] Pull-Up/Pull-Down Enable at Port 0 Bit 3

[3..3] See

[3..3] Port 2 Pin 3 Data Value

[3..3] Port 2 Pin 3 Driver Control

[3..3] Pull-Up/Pull-Down Select Port 2 Bit 3

[3..3] Pull-Up/Pull-Down Enable at Port 2 Bit 3

◆ PP3_INEN

__IOM uint32_t PP3_INEN

[19..19] Port 0 Pin 3 Input Schmitt Trigger enable (only valid if IO is configured as output)

◆ PP3_STS

__IM uint32_t PP3_STS

[19..19] Port 0 Pin 3 Data Value (read back of Port Data when IO is configured as output)

◆ PP4

[4..4] Port 0 Pin 4 Data Value

[4..4] Port 0 Pin 4 Direction Control

[4..4] Port 0 Pin 4 Open Drain Mode

[4..4] Pull-Up/Pull-Down Select Port 0 Bit 4

[4..4] Pull-Up/Pull-Down Enable at Port 0 Bit 4

[4..4] See

[4..4] Port 1 Pin 4 Data Value

[4..4] Port 1 Pin 4 Direction Control

[4..4] Port 1 Pin 4 Open Drain Mode

[4..4] Pull-Up/Pull-Down Select Port 1 Bit 4

[4..4] Pull-Up/Pull-Down Enable at Port 1 Bit 4

◆ PP4_INEN

__IOM uint32_t PP4_INEN

[20..20] Port 0 Pin 4 Input Schmitt Trigger enable (only valid if IO is configured as output)

[20..20] Port 1 Pin 4 Input Schmitt Trigger enable (only valid if IO is configured as output)

◆ PP4_STS

__IM uint32_t PP4_STS

[20..20] Port 0 Pin 4 Data Value (read back of Port Data when IO is configured as output)

[20..20] Port 1 Pin 4 Data Value (read back of Port Data when IO is configured as output)

◆ PP5

[5..5] Port 0 Pin 5 Data Value

[5..5] Port 0 Pin 5 Direction Control

[5..5] Port 0 Pin 5 Open Drain Mode

[5..5] Pull-Up/Pull-Down Select Port 0 Bit 5

[5..5] Pull-Up/Pull-Down Enable at Port 0 Bit 5

[5..5] See

◆ PP5_INEN

__IOM uint32_t PP5_INEN

[21..21] Port 0 Pin 5 Input Schmitt Trigger enable (only valid if IO is configured as output)

◆ PP5_STS

__IM uint32_t PP5_STS

[21..21] Port 0 Pin 5 Data Value (read back of Port Data when IO is configured as output)

◆ PP7

[7..7] Port 2 Pin 7 Data Value

[7..7] Port 2 Pin 7 Driver Control

[7..7] Pull-Up/Pull-Down Select Port 2 Bit 7

[7..7] Pull-Up/Pull-Down Enable at Port 2 Bit 7

◆ reg

(@ 0x00000000) Port 0 Data Register

(@ 0x00000004) Port 0 Direction Register

(@ 0x00000008) Port 0 Open Drain Control Register

(@ 0x0000000C) Port 0 Pull-Up/Pull-Down Select Register

(@ 0x00000010) Port 0 Pull-Up/Pull-Down Enable Register

(@ 0x00000014) Port 0 Alternate Select Register 0

(@ 0x00000018) Port 0 Alternate Select Register 1

(@ 0x00000020) Port 1 Data Register

(@ 0x00000024) Port 1 Direction Register

(@ 0x00000028) Port 1 Open Drain Control Register

(@ 0x0000002C) Port 1 Pull-Up/Pull-Down Select Register

(@ 0x00000030) Port 1 Pull-Up/Pull-Down Enable Register

(@ 0x00000034) Port 1 Alternate Select Register 0

(@ 0x00000038) Port 1 Alternate Select Register 1

(@ 0x00000040) Port 2 Data Register

(@ 0x00000044) Port 2 Direction Register

(@ 0x0000004C) Port 2 Pull-Up/Pull-Down Select Register

(@ 0x00000050) Port 2 Pull-Up/Pull-Down Enable Register

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1

◆ RESERVED2

__IM uint32_t RESERVED2

◆ uint32_t

__IM uint32_t

The documentation for this struct was generated from the following file: