Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields
SCUPM_Type Struct Reference

Detailed Description

SCUPM (SCUPM)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   AMCLK1_FREQ: 6
 
      __IM   uint32_t: 2
 
      __IM uint32_t   AMCLK2_FREQ: 6
 
   }   bit
 
AMCLK_FREQ_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CLKWDT_PD_N: 1
 
   }   bit
 
AMCLK_CTRL
 
__IM uint32_t RESERVED
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   AMCLK1_UP_TH: 6
 
      __IOM uint32_t   AMCLK1_UP_HYS: 2
 
      __IOM uint32_t   AMCLK1_LOW_TH: 6
 
      __IOM uint32_t   AMCLK1_LOW_HYS: 2
 
      __IOM uint32_t   AMCLK2_UP_TH: 6
 
      __IOM uint32_t   AMCLK2_UP_HYS: 2
 
      __IOM uint32_t   AMCLK2_LOW_TH: 6
 
      __IOM uint32_t   AMCLK2_LOW_HYS: 2
 
   }   bit
 
AMCLK_TH_HYS
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 8
 
      __OM uint32_t   SYS_OTWARN_ISC: 1
 
      __OM uint32_t   SYS_OT_ISC: 1
 
      __OM uint32_t   VREF1V2_UV_ISC: 1
 
      __OM uint32_t   VREF1V2_OV_ISC: 1
 
      __OM uint32_t   SYS_OTWARN_SC: 1
 
      __OM uint32_t   SYS_OT_SC: 1
 
      __OM uint32_t   VREF1V2_UV_SC: 1
 
      __OM uint32_t   VREF1V2_OV_SC: 1
 
   }   bit
 
SYS_ISCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   LIN_FAIL_IS: 1
 
      __IM uint32_t   CP_FAIL_IS: 1
 
      __IM uint32_t   DRV_FAIL_IS: 1
 
      __IM uint32_t   HS_FAIL_IS: 1
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   SYS_OTWARN_IS: 1
 
      __IOM uint32_t   SYS_OT_IS: 1
 
      __IM uint32_t   CLKWDT_IS: 1
 
      __IOM uint32_t   VREF1V2_UV_IS: 1
 
      __IOM uint32_t   VREF1V2_OV_IS: 1
 
      __IM uint32_t   SYS_SUPPLY_IS: 1
 
      __IM uint32_t   LIN_FAIL_STS: 1
 
      __IM uint32_t   CP_FAIL_STS: 1
 
      __IM uint32_t   DRV_FAIL_STS: 1
 
      __IM uint32_t   HS_FAIL_STS: 1
 
      __IOM uint32_t   SYS_OTWARN_STS: 1
 
      __IOM uint32_t   SYS_OT_STS: 1
 
      __IOM uint32_t   VREF1V2_UV_STS: 1
 
      __IOM uint32_t   VREF1V2_OV_STS: 1
 
      __IM uint32_t   SYS_SUPPLY_STS: 1
 
   }   bit
 
SYS_IS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VS_UV_IS: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   VDDEXT_UV_IS: 1
 
      __IOM uint32_t   VDD5V_UV_IS: 1
 
      __IOM uint32_t   VDD1V5_UV_IS: 1
 
      __IOM uint32_t   VS_OV_IS: 1
 
      __IOM uint32_t   VDDEXT_OV_IS: 1
 
      __IOM uint32_t   VDD5V_OV_IS: 1
 
      __IOM uint32_t   VDD1V5_OV_IS: 1
 
      __IOM uint32_t   VS_UV_STS: 1
 
      __IOM uint32_t   VDDEXT_UV_STS: 1
 
      __IOM uint32_t   VDD5V_UV_STS: 1
 
      __IOM uint32_t   VDD1V5_UV_STS: 1
 
      __IOM uint32_t   VS_OV_STS: 1
 
      __IOM uint32_t   VDDEXT_OV_STS: 1
 
      __IOM uint32_t   VDD5V_OV_STS: 1
 
      __IOM uint32_t   VDD1V5_OV_STS: 1
 
   }   bit
 
SYS_SUPPLY_IRQ_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VS_UV_IE: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   VDDEXT_UV_IE: 1
 
      __IOM uint32_t   VDD5V_UV_IE: 1
 
      __IOM uint32_t   VDD1V5_UV_IE: 1
 
      __IOM uint32_t   VS_OV_IE: 1
 
      __IOM uint32_t   VDDEXT_OV_IE: 1
 
      __IOM uint32_t   VDD5V_OV_IE: 1
 
      __IOM uint32_t   VDD1V5_OV_IE: 1
 
   }   bit
 
SYS_SUPPLY_IRQ_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   VS_UV_ISC: 1
 
      __IM   uint32_t: 2
 
      __OM uint32_t   VDDEXT_UV_ISC: 1
 
      __OM uint32_t   VDD5V_UV_ISC: 1
 
      __OM uint32_t   VDD1V5_UV_ISC: 1
 
      __OM uint32_t   VS_OV_ISC: 1
 
      __OM uint32_t   VDDEXT_OV_ISC: 1
 
      __OM uint32_t   VDD5V_OV_ISC: 1
 
      __OM uint32_t   VDD1V5_OV_ISC: 1
 
      __OM uint32_t   VS_UV_SC: 1
 
      __OM uint32_t   VDDEXT_UV_SC: 1
 
      __OM uint32_t   VDD5V_UV_SC: 1
 
      __OM uint32_t   VDD1V5_UV_SC: 1
 
      __OM uint32_t   VS_OV_SC: 1
 
      __OM uint32_t   VDDEXT_OV_SC: 1
 
      __OM uint32_t   VDD5V_OV_SC: 1
 
      __OM uint32_t   VDD1V5_OV_SC: 1
 
   }   bit
 
SYS_SUPPLY_IRQ_CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 8
 
      __IOM uint32_t   SYS_OTWARN_IE: 1
 
      __IOM uint32_t   SYS_OT_IE: 1
 
      __IOM uint32_t   VREF1V2_UV_IE: 1
 
      __IOM uint32_t   VREF1V2_OV_IE: 1
 
   }   bit
 
SYS_IRQ_CTRL
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IOM uint32_t   CLKWDT_SD_DIS: 1
 
      __IOM uint32_t   FAIL_PS_DIS: 1
 
      __IOM uint32_t   LIN_VS_UV_SD_DIS: 1
 
      __IOM uint32_t   SYS_VS_UV_SLM_DIS: 1
 
      __IOM uint32_t   SYS_VS_OV_SLM_DIS: 1
 
      __IOM uint32_t   SYS_OTWARN_PS_DIS: 1
 
      __IOM uint32_t   CLKLOSS_SD_DIS: 1
 
      __IOM uint32_t   CLKWDT_RES_SD_DIS: 1
 
      __IOM uint32_t   CLKLOSS_RES_SD_DIS: 1
 
   }   bit
 
PCU_CTRL_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDP_SEL: 6
 
      __IOM uint32_t   SOWCONF: 2
 
   }   bit
 
WDT1_TRIG
 
__IM uint32_t RESERVED3 [13]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STCALIB: 26
 
   }   bit
 
STCALIB
 

Field Documentation

◆ AMCLK1_FREQ

__IM uint32_t AMCLK1_FREQ

[5..0] Current frequency of Analog Module Clock System Clock (MI_CLK)

◆ AMCLK1_LOW_HYS

__IOM uint32_t AMCLK1_LOW_HYS

[15..14] Analog Module Clock 1 (MI_CLK) Lower Hysteresis

◆ AMCLK1_LOW_TH

__IOM uint32_t AMCLK1_LOW_TH

[13..8] Analog Module Clock 1 (MI_CLK) Lower Limit Threshold

◆ AMCLK1_UP_HYS

__IOM uint32_t AMCLK1_UP_HYS

[7..6] Analog Module Clock 1 (MI_CLK) Upper Hysteresis

◆ AMCLK1_UP_TH

__IOM uint32_t AMCLK1_UP_TH

[5..0] Analog Module Clock 1 (MI_CLK) Upper Limit Threshold

◆ AMCLK2_FREQ

__IM uint32_t AMCLK2_FREQ

[13..8] Current frequency of Analog Module Clock 2 (TFILT_CLK)

◆ AMCLK2_LOW_HYS

__IOM uint32_t AMCLK2_LOW_HYS

[31..30] Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis

◆ AMCLK2_LOW_TH

__IOM uint32_t AMCLK2_LOW_TH

[29..24] Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold

◆ AMCLK2_UP_HYS

__IOM uint32_t AMCLK2_UP_HYS

[23..22] Analog Module Clock 2 (TFILT_CLK) Upper Hysteresis

◆ AMCLK2_UP_TH

__IOM uint32_t AMCLK2_UP_TH

[21..16] Analog Module Clock 2 (TFILT_CLK) Upper Limit Threshold

◆ 

union { ... } AMCLK_CTRL

◆ 

union { ... } AMCLK_FREQ_STS

< (@ 0x50006000) SCUPM Structure

◆ 

union { ... } AMCLK_TH_HYS

◆  [1/12]

struct { ... } bit

◆  [2/12]

struct { ... } bit

◆  [3/12]

struct { ... } bit

◆  [4/12]

struct { ... } bit

◆  [5/12]

struct { ... } bit

◆  [6/12]

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◆  [7/12]

struct { ... } bit

◆  [8/12]

struct { ... } bit

◆  [9/12]

struct { ... } bit

◆  [10/12]

struct { ... } bit

◆  [11/12]

struct { ... } bit

◆  [12/12]

struct { ... } bit

◆ CLKLOSS_RES_SD_DIS

__IOM uint32_t CLKLOSS_RES_SD_DIS

[27..27] Loss of Clock Reset Disable

◆ CLKLOSS_SD_DIS

__IOM uint32_t CLKLOSS_SD_DIS

[25..25] System Loss of Clock Shutdown Disable (AMCLK3)

◆ CLKWDT_IS

__IM uint32_t CLKWDT_IS

[10..10] Clock Watchdog Interrupt Status

◆ CLKWDT_PD_N

__IOM uint32_t CLKWDT_PD_N

[0..0] Clock Watchdog Powerdown

◆ CLKWDT_RES_SD_DIS

__IOM uint32_t CLKWDT_RES_SD_DIS

[26..26] Clock Watchdog Reset Disable

◆ CLKWDT_SD_DIS

__IOM uint32_t CLKWDT_SD_DIS

[1..1] Power Modules Clock Watchdog Shutdown Disable

◆ CP_FAIL_IS

__IM uint32_t CP_FAIL_IS

[1..1] Charge Pump Fail Interrupt Status

◆ CP_FAIL_STS

__IM uint32_t CP_FAIL_STS

[17..17] Charge Pump Fail Status

◆ DRV_FAIL_IS

__IM uint32_t DRV_FAIL_IS

[2..2] Gate Driver Fail Interrupt Status

◆ DRV_FAIL_STS

__IM uint32_t DRV_FAIL_STS

[18..18] Gate Driver Fail Status

◆ FAIL_PS_DIS

__IOM uint32_t FAIL_PS_DIS

[7..7] Disable LIN Tx and HS and because of Overtemperature Warning or VS OV/UV

◆ HS_FAIL_IS

__IM uint32_t HS_FAIL_IS

[3..3] High Side Driver Fail Interrupt Status

◆ HS_FAIL_STS

__IM uint32_t HS_FAIL_STS

[19..19] High Side Driver Fail Status

◆ LIN_FAIL_IS

__IM uint32_t LIN_FAIL_IS

[0..0] LIN Fail Interrupt Status

◆ LIN_FAIL_STS

__IM uint32_t LIN_FAIL_STS

[16..16] LIN Fail Status

◆ LIN_VS_UV_SD_DIS

__IOM uint32_t LIN_VS_UV_SD_DIS

[8..8] LIN Module VS Undervoltage Transmitter Shutdown

◆ 

union { ... } PCU_CTRL_STS

◆ reg

(@ 0x00000000) Analog Module Clock Frequency Status Register

(@ 0x00000004) Analog Module Clock Control Register

(@ 0x0000000C) Analog Module Clock Limit Register

(@ 0x00000014) System Interrupt Status Clear Register

(@ 0x00000018) System Interrupt Status Register

(@ 0x0000001C) System Supply Interrupt Status Register

(@ 0x00000020) System Supply Interrupt Control Register

(@ 0x00000024) System Supply Interrupt Status Clear Register

(@ 0x00000028) System Interrupt Control Register

(@ 0x00000030) Power Control Unit Control Status Register

(@ 0x00000034) WDT1 Watchdog Control Register

(@ 0x0000006C) System Tick Calibration Register

◆ RESERVED

__IM uint32_t RESERVED

◆ RESERVED1

__IM uint32_t RESERVED1

◆ RESERVED2

__IM uint32_t RESERVED2

◆ RESERVED3

__IM uint32_t RESERVED3[13]

◆ SOWCONF

__IOM uint32_t SOWCONF

[7..6] Short Open Window Configuration

◆ STCALIB [1/2]

__IOM uint32_t STCALIB

[25..0] System Tick Calibration

◆  [2/2]

union { ... } STCALIB

◆ 

union { ... } SYS_IRQ_CTRL

◆ 

union { ... } SYS_IS

◆ 

union { ... } SYS_ISCLR

◆ SYS_OT_IE

__IOM uint32_t SYS_OT_IE

[9..9] System Overtemperature Shutdown Interrupt Enable

◆ SYS_OT_IS

__IOM uint32_t SYS_OT_IS

[9..9] System Overtemperature Shutdown (ADC2, Channel 8) interrupt status

◆ SYS_OT_ISC

__OM uint32_t SYS_OT_ISC

[9..9] System Overtemperature Shutdown Interrupt Status Clear

◆ SYS_OT_SC

__OM uint32_t SYS_OT_SC

[25..25] System Overtemperature Shutdown Status Clear

◆ SYS_OT_STS

__IOM uint32_t SYS_OT_STS

[25..25] System Overtemperature Shutdown (ADC2, Channel 6) status

◆ SYS_OTWARN_IE

__IOM uint32_t SYS_OTWARN_IE

[8..8] System Overtemperature Prewarning Interrupt Enable

◆ SYS_OTWARN_IS

__IOM uint32_t SYS_OTWARN_IS

[8..8] System Overtemperature Prewarning (ADC2, Channel 8) interrupt status

◆ SYS_OTWARN_ISC

__OM uint32_t SYS_OTWARN_ISC

[8..8] System Overtemperature Prewarning Interrupt Status Clear

◆ SYS_OTWARN_PS_DIS

__IOM uint32_t SYS_OTWARN_PS_DIS

[24..24] System Overtemperature Warning Power Switches Shutdown Disable

◆ SYS_OTWARN_SC

__OM uint32_t SYS_OTWARN_SC

[24..24] System Overtemperature Prewarning Status Clear

◆ SYS_OTWARN_STS

__IOM uint32_t SYS_OTWARN_STS

[24..24] System Overtemperature Prewarning (ADC2, Channel 6) status

◆ 

union { ... } SYS_SUPPLY_IRQ_CLR

◆ 

union { ... } SYS_SUPPLY_IRQ_CTRL

◆ 

union { ... } SYS_SUPPLY_IRQ_STS

◆ SYS_SUPPLY_IS

__IM uint32_t SYS_SUPPLY_IS

[14..14] System Supply Interrupt Status

◆ SYS_SUPPLY_STS

__IM uint32_t SYS_SUPPLY_STS

[30..30] System Supply Status

◆ SYS_VS_OV_SLM_DIS

__IOM uint32_t SYS_VS_OV_SLM_DIS

[14..14] VS Overvoltage Shutdown for Peripherals Disable

◆ SYS_VS_UV_SLM_DIS

__IOM uint32_t SYS_VS_UV_SLM_DIS

[13..13] VS Undervoltage Shutdown for Peripherals Disable

◆ uint32_t

__IM uint32_t

◆ VDD1V5_OV_IE

__IOM uint32_t VDD1V5_OV_IE

[14..14] VDDC Overvoltage Interrupt Enable

◆ VDD1V5_OV_IS

__IOM uint32_t VDD1V5_OV_IS

[14..14] VDDC Overvoltage Interrupt Status (ADC2 channel 6)

◆ VDD1V5_OV_ISC

__OM uint32_t VDD1V5_OV_ISC

[14..14] VDDC Overvoltage Interrupt Status clear

◆ VDD1V5_OV_SC

__OM uint32_t VDD1V5_OV_SC

[30..30] VDDC Overvoltage Status clear

◆ VDD1V5_OV_STS

__IOM uint32_t VDD1V5_OV_STS

[30..30] VDDC Overvoltage Status (ADC2 channel 6)

◆ VDD1V5_UV_IE

__IOM uint32_t VDD1V5_UV_IE

[6..6] VDDC Undervoltage Interrupt Enable

◆ VDD1V5_UV_IS

__IOM uint32_t VDD1V5_UV_IS

[6..6] VDDC Undervoltage Interrupt Status (ADC2 channel 6)

◆ VDD1V5_UV_ISC

__OM uint32_t VDD1V5_UV_ISC

[6..6] VDDC Undervoltage Interrupt Status clear

◆ VDD1V5_UV_SC

__OM uint32_t VDD1V5_UV_SC

[22..22] VDDC Undervoltage Status clear

◆ VDD1V5_UV_STS

__IOM uint32_t VDD1V5_UV_STS

[22..22] VDDC Undervoltage Status (ADC2 channel 6)

◆ VDD5V_OV_IE

__IOM uint32_t VDD5V_OV_IE

[12..12] VDDP Overvoltage Interrupt Enable

◆ VDD5V_OV_IS

__IOM uint32_t VDD5V_OV_IS

[12..12] VDDP Overvoltage Interrupt Status (ADC2 channel 4)

◆ VDD5V_OV_ISC

__OM uint32_t VDD5V_OV_ISC

[12..12] VDDP Overvoltage Interrupt Status clear

◆ VDD5V_OV_SC

__OM uint32_t VDD5V_OV_SC

[28..28] VDDP Overvoltage Status clear

◆ VDD5V_OV_STS

__IOM uint32_t VDD5V_OV_STS

[28..28] VDDP Overvoltage Status (ADC2 channel 4)

◆ VDD5V_UV_IE

__IOM uint32_t VDD5V_UV_IE

[4..4] VDDP Undervoltage Interrupt Enable

◆ VDD5V_UV_IS

__IOM uint32_t VDD5V_UV_IS

[4..4] VDDP Undervoltage Interrupt Status (ADC2 channel 4)

◆ VDD5V_UV_ISC

__OM uint32_t VDD5V_UV_ISC

[4..4] VDDP Undervoltage Interrupt Status clear

◆ VDD5V_UV_SC

__OM uint32_t VDD5V_UV_SC

[20..20] VDDP Undervoltage Status clear

◆ VDD5V_UV_STS

__IOM uint32_t VDD5V_UV_STS

[20..20] VDDP Undervoltage Status (ADC2 channel 4)

◆ VDDEXT_OV_IE

__IOM uint32_t VDDEXT_OV_IE

[11..11] VDDEXT Overvoltage Interrupt Enable

◆ VDDEXT_OV_IS

__IOM uint32_t VDDEXT_OV_IS

[11..11] VDDEXT Overvoltage Interrupt Status (ADC2 channel 3)

◆ VDDEXT_OV_ISC

__OM uint32_t VDDEXT_OV_ISC

[11..11] VDDEXT Overvoltage Interrupt Status clear

◆ VDDEXT_OV_SC

__OM uint32_t VDDEXT_OV_SC

[27..27] VDDEXT Overvoltage Status clear

◆ VDDEXT_OV_STS

__IOM uint32_t VDDEXT_OV_STS

[27..27] VDDEXT Overvoltage Status (ADC2 channel 3)

◆ VDDEXT_UV_IE

__IOM uint32_t VDDEXT_UV_IE

[3..3] VDDEXT Undervoltage Interrupt Enable

◆ VDDEXT_UV_IS

__IOM uint32_t VDDEXT_UV_IS

[3..3] VDDEXT Undervoltage Interrupt Status (ADC2 channel 3)

◆ VDDEXT_UV_ISC

__OM uint32_t VDDEXT_UV_ISC

[3..3] VDDEXT Undervoltage Interrupt Status clear

◆ VDDEXT_UV_SC

__OM uint32_t VDDEXT_UV_SC

[19..19] VDDEXT Undervoltage Status clear

◆ VDDEXT_UV_STS

__IOM uint32_t VDDEXT_UV_STS

[19..19] VDDEXT Undervoltage Status (ADC2 channel 3)

◆ VREF1V2_OV_IE

__IOM uint32_t VREF1V2_OV_IE

[13..13] 8 Bit ADC2 Reference Overvoltage Interrupt Enable

◆ VREF1V2_OV_IS

__IOM uint32_t VREF1V2_OV_IS

[13..13] 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status

◆ VREF1V2_OV_ISC

__OM uint32_t VREF1V2_OV_ISC

[13..13] 8 Bit ADC2 Reference Overvoltage Interrupt Status Clear

◆ VREF1V2_OV_SC

__OM uint32_t VREF1V2_OV_SC

[29..29] 8 Bit ADC2 Reference Overvoltage Status Clear

◆ VREF1V2_OV_STS

__IOM uint32_t VREF1V2_OV_STS

[29..29] 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status

◆ VREF1V2_UV_IE

__IOM uint32_t VREF1V2_UV_IE

[12..12] 8 Bit ADC2 Reference Undervoltage Interrupt Enable

◆ VREF1V2_UV_IS

__IOM uint32_t VREF1V2_UV_IS

[12..12] 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status

◆ VREF1V2_UV_ISC

__OM uint32_t VREF1V2_UV_ISC

[12..12] 8 Bit ADC2 Reference Undervoltage Interrupt Status Clear

◆ VREF1V2_UV_SC

__OM uint32_t VREF1V2_UV_SC

[28..28] 8 Bit ADC2 Reference Undervoltage Status Clear

◆ VREF1V2_UV_STS

__IOM uint32_t VREF1V2_UV_STS

[28..28] 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrstatus

◆ VS_OV_IE

__IOM uint32_t VS_OV_IE

[8..8] VS Overvoltage Interrupt Enable

◆ VS_OV_IS

__IOM uint32_t VS_OV_IS

[8..8] VS Overvoltage Interrupt Status (ADC2 channel 0)

◆ VS_OV_ISC

__OM uint32_t VS_OV_ISC

[8..8] VS Overvoltage Interrupt Status clear

◆ VS_OV_SC

__OM uint32_t VS_OV_SC

[24..24] VS Overvoltage Status clear

◆ VS_OV_STS

__IOM uint32_t VS_OV_STS

[24..24] VS Overvoltage Status (ADC2 channel 0)

◆ VS_UV_IE

__IOM uint32_t VS_UV_IE

[0..0] VS Undervoltage Interrupt Enable

◆ VS_UV_IS

__IOM uint32_t VS_UV_IS

[0..0] VS Undervoltage Interrupt Status (ADC2 channel 0)

◆ VS_UV_ISC

__OM uint32_t VS_UV_ISC

[0..0] VS Undervoltage Interrupt Status clear

◆ VS_UV_SC

__OM uint32_t VS_UV_SC

[16..16] VS Undervoltage Status clear

◆ VS_UV_STS

__IOM uint32_t VS_UV_STS

[16..16] VS Undervoltage Status (ADC2 channel 0)

◆ WDP_SEL

__IOM uint32_t WDP_SEL

[5..0] Watchdog Period Selection and trigger

◆ 

union { ... } WDT1_TRIG

The documentation for this struct was generated from the following file: