Infineon MOTIX™ MCU TLE985x Device Family SDK
Macros | Enumerations
Configuration_of_CMSIS

Detailed Description

Collaboration diagram for Configuration_of_CMSIS:

Macros

#define __CM0_REV   0x0000U
 
#define __NVIC_PRIO_BITS   2
 
#define __Vendor_SysTickConfig   0
 
#define __MPU_PRESENT   0
 
#define __FPU_PRESENT   0
 

Enumerations

enum  IRQn_Type {
  Reset_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , SVCall_IRQn = -5 ,
  PendSV_IRQn = -2 , SysTick_IRQn = -1 , INTISR0_IRQn = 0 , INTISR1_IRQn = 1 ,
  INTISR2_IRQn = 2 , INTISR3_IRQn = 3 , INTISR4_IRQn = 4 , INTISR5_IRQn = 5 ,
  INTISR6_IRQn = 6 , INTISR7_IRQn = 7 , INTISR8_IRQn = 8 , INTISR9_IRQn = 9 ,
  INTISR10_IRQn = 10 , INTISR11_IRQn = 11 , INTISR12_IRQn = 12 , INTISR13_IRQn = 13 ,
  INTISR14_IRQn = 14 , INTISR15_IRQn = 15 , INTISR17_IRQn = 17 , INTISR18_IRQn = 18 ,
  INTISR19_IRQn = 19 , INTISR20_IRQn = 20 , INTISR21_IRQn = 21 , INTISR22_IRQn = 22 ,
  INTISR23_IRQn = 23
}
 

Macro Definition Documentation

◆ __CM0_REV

#define __CM0_REV   0x0000U

CM0 Core Revision

◆ __FPU_PRESENT

#define __FPU_PRESENT   0

FPU present or not

◆ __MPU_PRESENT

#define __MPU_PRESENT   0

MPU present or not

◆ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS   2

Number of Bits used for Priority Levels

◆ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

Enumeration Type Documentation

◆ IRQn_Type

enum IRQn_Type
Enumerator
Reset_IRQn 

-15 Reset Vector, invoked on Power up and warm reset

NonMaskableInt_IRQn 

-14 Non maskable Interrupt, cannot be stopped or preempted

HardFault_IRQn 

-13 Hard Fault, all classes of Fault

SVCall_IRQn 

-5 System Service Call via SVC instruction

PendSV_IRQn 

-2 Pendable request for system service

SysTick_IRQn 

-1 System Tick Timer

INTISR0_IRQn 

0 Interrupt node 0: GPT1 Block

INTISR1_IRQn 

1 Interrupt node 1: GPT2 Block

INTISR2_IRQn 

2 Interrupt node 2: ADC2, Timer3

INTISR3_IRQn 

3 Interrupt node 3: ADC1

INTISR4_IRQn 

4 Interrupt node 4: CCU6 node0

INTISR5_IRQn 

5 Interrupt node 5: CCU6 node1

INTISR6_IRQn 

6 Interrupt node 6: CCU6 node2

INTISR7_IRQn 

7 Interrupt node 7: CCU6 node3

INTISR8_IRQn 

8 Interrupt node 8: SSC1

INTISR9_IRQn 

9 Interrupt node 9: SSC2

INTISR10_IRQn 

10 Interrupt node 10: UART1(ASC,LIN), Timer2

INTISR11_IRQn 

11 Interrupt node 11: UART2, Timer21

INTISR12_IRQn 

12 Interrupt node 12: EINT0

INTISR13_IRQn 

13 Interrupt node 13: EINT1

INTISR14_IRQn 

14 Interrupt node 14: Wakeup

INTISR15_IRQn 

15 Interrupt node 15: Math Div

INTISR17_IRQn 

17 Interrupt node 17: BDRV LS1, OC, OT, OL

INTISR18_IRQn 

18 Interrupt node 18: BDRV LS2, OC, OT, OL

INTISR19_IRQn 

19 Interrupt node 19: BDRV HS1, OC, OT, OL

INTISR20_IRQn 

20 Interrupt node 20: BDRV HS2, OC, OT, OL

INTISR21_IRQn 

21 Interrupt node 21: Differential Unit

INTISR22_IRQn 

22 Interrupt node 22: MONx

INTISR23_IRQn 

23 Interrupt node 23: Port 2.x (ADC1)