Infineon MOTIX™ MCU TLE985x Device Family SDK
bdrv.h
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1 /*
2  ***********************************************************************************************************************
3  *
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25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** TS T&S **
45 ** KC Kay Claussen **
46 ** JO Julia Ott **
47 ** BG Blandine Guillot **
48 ** VO Vanessa Ongaro **
49 *******************************************************************************/
50 
51 /*******************************************************************************
52 ** Revision Control History **
53 ********************************************************************************
54 ** V0.2.0: 2018-02-13, TS: Initial version of revision history **
55 ** V0.2.1: 2018-07-30, KC: Registers added to BDRV_Init() **
56 ** V0.2.2: 2018-10-22, TS: BRDRV_CLK Register Initialization added **
57 ** V0.2.3: 2019-01-28, TS: __STATIC_INLINE changed to INLINE **
58 ** Doxygen update **
59 ** Revision history moved from bdrv.c to bdrv.h **
60 ** BDRV_Diag_OpenLoad function updated **
61 ** BDRV_Off_Diagnosis and BDRV_Set_DSM_Threshold **
62 ** functions added **
63 ** New Mask macros used **
64 ** V0.2.4: 2019-06-13, JO: Corrected value of define BDRV_IRQ_CLR_BITS from **
65 ** 0xF0707070 to 0xF0707073 to clear all interrupts **
66 ** In BDRV_Init: Set APCLK_SET after modifying **
67 ** SCU->BRDRV_CLK.reg to apply clock changes **
68 ** V0.2.5: 2019-08-30, AP: In BDRV_Init: Keep the bootrom value for **
69 ** Charge Pump Output Voltage Trimming **
70 ** V0.2.6: 2019-09-03, JO: Removed the functions for H-Bridge if a **
71 ** Half-Bridge device is selected **
72 ** V0.2.7: 2020-03-02, BG: Updated revision history format **
73 ** V0.2.8: 2020-08-12, JO: EP-444: Added initialization of adaptive **
74 ** sequencer registers **
75 ** V0.2.9: 2022-01-21, JO: EP-934: Updated copyright and branding **
76 ** V0.3.0: 2023-07-19, VO: EP-1450: Removed interrupt funcs for VCP_LOTH2 **
77 ** V0.3.1: 2023-08-28, JO: EP-435: Removed ARMCC v6 compiler warnings **
78 *******************************************************************************/
79 
80 #ifndef _BDR_H
81 #define _BDR_H
82 
83 /*******************************************************************************
84 ** Includes **
85 *******************************************************************************/
86 #include "tle985x.h"
87 #include "types.h"
88 #include "sfr_access.h"
89 #include "tle_variants.h"
90 
91 /*******************************************************************************
92 ** Global Constant Declarations **
93 *******************************************************************************/
95 #define BDRV_IRQ_EN_BITS 0xD0505050u
96 
98 #define BDRV_IRQ_CLR_BITS 0xF0707073u
99 
101 #define BDRV_COMP_BITS 0x70700u
102 
104 #define BDRV_DS_STS_BITS 0x20202020
105 
106 /*******************************************************************************
107 ** Global Type Definitions **
108 *******************************************************************************/
112  typedef enum
113  {
114  Ch_LS_Off = 0u,
115  Ch_LS_En = 1u,
116  Ch_LS_PWM = 3u,
117  Ch_LS_On = 5u
119 
123 typedef enum
124 {
125  Ch_Off = 0u,
126  Ch_En = 1u,
127  Ch_PWM = 3u,
128  Ch_On = 5u,
129  Ch_DCS = 9u
131 
135 typedef enum
136 {
137  LS1 = 0u,
138  LS2 = 1u,
139  HS1 = 2u,
140  HS2 = 3u
142 
143 #define BDRV_LS1_DS_ISC BDRV_IRQCLR_LS1_DS_ISC_Msk
144 #define BDRV_LS1_DS_SC BDRV_IRQCLR_LS1_DS_SC_Msk
145 #define BDRV_LS1_OC_ISC BDRV_IRQCLR_LS1_OC_ISC_Msk
146 #define BDRV_HS1_DS_ISC BDRV_IRQCLR_HS1_DS_ISC_Msk
147 #define BDRV_HS1_DS_SC BDRV_IRQCLR_HS1_DS_SC_Msk
148 #define BDRV_HS1_OC_ISC BDRV_IRQCLR_HS1_OC_ISC_Msk
151 #ifdef UC_FEATURE_HB2
152 #define BDRV_LS2_DS_ISC BDRV_IRQCLR_LS2_DS_ISC_Msk
153 #define BDRV_LS2_DS_SC BDRV_IRQCLR_LS2_DS_SC_Msk
154 #define BDRV_LS2_OC_ISC BDRV_IRQCLR_LS2_OC_ISC_Msk
155 #define BDRV_HS2_DS_ISC BDRV_IRQCLR_HS2_DS_ISC_Msk
156 #define BDRV_HS2_DS_SC BDRV_IRQCLR_HS2_DS_SC_Msk
157 #define BDRV_HS2_OC_ISC BDRV_IRQCLR_HS2_OC_ISC_Msk
158 #endif
159 
160 #define BDRV_SEQ_ERR_ISC BDRV_IRQCLR_SEQ_ERR_ISC_Msk
165 typedef enum
166 {
167  Ch_Ok = 0u,
169  Ch_Short_to_VBat = 2u
171 
175 typedef struct
176 {
181 
185 typedef enum
186 {
187  Int_Off = 0U,
188  Int_DS = 1U,
189  Int_OC = 2U,
190  Int_DS_OC = 3U
192 
196 typedef enum
197 {
205  Threshold_1_75_V = 7U
207 
208 /*******************************************************************************
209 ** Global Function Declarations **
210 *******************************************************************************/
215 void BDRV_Init(void);
216 
217 
218 #ifdef UC_FEATURE_HB2
238  TBdrv_Ch_Cfg HS1_Cfg,
239  TBdrv_Ch_LS_Cfg LS2_Cfg,
240  TBdrv_Ch_Cfg HS2_Cfg);
241 #else
257 void BDRV_Set_Bridge(TBdrv_Ch_LS_Cfg LS1_Cfg,
258  TBdrv_Ch_Cfg HS1_Cfg);
259 #endif
275 void BDRV_Set_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Cfg Ch_Cfg);
276 
291 void BDRV_Clr_Sts(uint32 Sts_Bit);
292 
309 
325 
341 void BDRV_Set_Channel_Comp(uint8 gain_hs, uint8 gain_ls);
342 
343 #ifdef UC_FEATURE_HB2
366 #endif
367 
368 #ifdef UC_FEATURE_HB2
392 #endif
393 
394 /*******************************************************************************
395 ** Inline Function Declarations **
396 *******************************************************************************/
414 INLINE void BDRV_SEQ_ERR_Int_Clr(void);
415 
416 #ifdef UC_FEATURE_HB2
434 INLINE void BDRV_HS2_OC_Int_Clr(void);
435 
451 INLINE void BDRV_HS2_DS_SC_Clr(void);
452 
471 INLINE void BDRV_HS2_DS_Int_Clr(void);
472 #endif
473 
491 INLINE void BDRV_HS1_OC_Int_Clr(void);
492 
508 INLINE void BDRV_HS1_DS_SC_Clr(void);
509 
527 INLINE void BDRV_HS1_DS_Int_Clr(void);
528 
529 #ifdef UC_FEATURE_HB2
547 INLINE void BDRV_LS2_OC_Int_Clr(void);
548 
564 INLINE void BDRV_LS2_DS_SC_Clr(void);
565 
583 INLINE void BDRV_LS2_DS_Int_Clr(void);
584 #endif
585 
603 INLINE void BDRV_LS1_OC_Int_Clr(void);
604 
620 INLINE void BDRV_LS1_DS_SC_Clr(void);
621 
639 INLINE void BDRV_LS1_DS_Int_Clr(void);
640 
658 INLINE void BDRV_SEQ_ERR_Int_En(void);
659 
678 INLINE void BDRV_SEQ_ERR_Int_Dis(void);
679 
697 INLINE void BDRV_HS1_OC_Int_En(void);
698 
717 INLINE void BDRV_HS1_OC_Int_Dis(void);
718 
736 INLINE void BDRV_LS1_OC_Int_En(void);
737 
756 INLINE void BDRV_LS1_OC_Int_Dis(void);
757 
758 #ifdef UC_FEATURE_HB2
776 INLINE void BDRV_HS2_OC_Int_En(void);
777 
796 INLINE void BDRV_HS2_OC_Int_Dis(void);
797 
815 INLINE void BDRV_LS2_OC_Int_En(void);
816 
835 INLINE void BDRV_LS2_OC_Int_Dis(void);
836 #endif
837 
855 INLINE void BDRV_HS1_DS_Int_En(void);
856 
875 INLINE void BDRV_HS1_DS_Int_Dis(void);
876 
894 INLINE void BDRV_LS1_DS_Int_En(void);
895 
914 INLINE void BDRV_LS1_DS_Int_Dis(void);
915 
916 #ifdef UC_FEATURE_HB2
934 INLINE void BDRV_HS2_DS_Int_En(void);
935 
954 INLINE void BDRV_HS2_DS_Int_Dis(void);
955 
973 INLINE void BDRV_LS2_DS_Int_En(void);
974 
993 INLINE void BDRV_LS2_DS_Int_Dis(void);
994 #endif
995 
996 /*******************************************************************************
997 ** Inline Function Definitions **
998 *******************************************************************************/
1000 {
1002 }
1003 
1004 #ifdef UC_FEATURE_HB2
1006 {
1008 }
1009 
1011 {
1013 }
1014 
1016 {
1018 }
1019 #endif
1020 
1022 {
1024 }
1025 
1027 {
1029 }
1030 
1032 {
1034 }
1035 
1036 #ifdef UC_FEATURE_HB2
1038 {
1040 }
1041 
1043 {
1045 }
1046 
1048 {
1050 }
1051 #endif
1052 
1054 {
1056 }
1057 
1059 {
1061 }
1062 
1064 {
1066 }
1067 
1069 {
1071 }
1072 
1074 {
1076 }
1077 
1079 {
1081 }
1082 
1084 {
1086 }
1087 
1089 {
1091 }
1092 
1094 {
1096 }
1097 
1098 #ifdef UC_FEATURE_HB2
1100 {
1102 }
1103 
1105 {
1107 }
1108 
1110 {
1112 }
1113 
1115 {
1117 }
1118 #endif
1119 
1121 {
1123 }
1124 
1126 {
1128 }
1129 
1131 {
1133 }
1134 
1136 {
1138 }
1139 
1140 #ifdef UC_FEATURE_HB2
1142 {
1144 }
1145 
1147 {
1149 }
1150 
1152 {
1154 }
1155 
1157 {
1159 }
1160 #endif
1161 
1162 #endif
INLINE void BDRV_SEQ_ERR_Int_En(void)
Enables Driver Sequence Error interrupt.
Definition: bdrv.h:1068
bool BDRV_Diag_OpenLoad(void)
Detects whether a motor is connected.
INLINE void BDRV_LS1_OC_Int_Dis(void)
Disables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:1093
INLINE void BDRV_LS1_DS_Int_Dis(void)
Disables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1135
INLINE void BDRV_LS1_OC_Int_En(void)
Enables External Low Side 1 FET Over-current interrupt.
Definition: bdrv.h:1088
TBdrv_DSM_Threshold
This enum lists the Drain-Source Voltage Threshold.
Definition: bdrv.h:197
@ Threshold_0_75_V
Threshold 3 for VDS at 0.75 V.
Definition: bdrv.h:201
@ Threshold_0_50_V
Threshold 2 for VDS at 0.50 V.
Definition: bdrv.h:200
@ Threshold_0_125_V
Threshold 0 for VDS at 0.125 V.
Definition: bdrv.h:198
@ Threshold_1_75_V
Threshold 7 for VDS at 1.75 V.
Definition: bdrv.h:205
@ Threshold_1_00_V
Threshold 4 for VDS at 1.00 V.
Definition: bdrv.h:202
@ Threshold_1_50_V
Threshold 6 for VDS at 1.50 V.
Definition: bdrv.h:204
@ Threshold_1_25_V
Threshold 5 for VDS at 1.25 V.
Definition: bdrv.h:203
@ Threshold_0_25_V
Threshold 1 for VDS at 0.25 V.
Definition: bdrv.h:199
INLINE void BDRV_LS2_OC_Int_Clr(void)
Clears External Low Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:1037
void BDRV_Clr_Sts(uint32 Sts_Bit)
Clears individual status flags and interrupt status flags of the BridgeDriver.
INLINE void BDRV_LS2_DS_Int_Clr(void)
Clears Low Side Driver 2 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:1047
INLINE void BDRV_HS2_OC_Int_Dis(void)
Disables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:1104
INLINE void BDRV_HS2_DS_Int_En(void)
Enables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1141
void BDRV_Set_Int_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Int Ch_Int)
Sets Interrupt Enable for the individual MOSFETs.
TBdrv_Ch_LS_Cfg
This enum lists the Bridge Driver Low Side channel configuration.
Definition: bdrv.h:113
@ Ch_LS_Off
channel disabled
Definition: bdrv.h:114
@ Ch_LS_PWM
channel enabled with PWM (CCU6 connection)
Definition: bdrv.h:116
@ Ch_LS_En
channel enabled
Definition: bdrv.h:115
@ Ch_LS_On
channel enabled and static on
Definition: bdrv.h:117
INLINE void BDRV_HS1_DS_SC_Clr(void)
Clears High Side Driver 1 Drain Source Monitoring status flag in OFF-State.
Definition: bdrv.h:1026
INLINE void BDRV_HS2_DS_SC_Clr(void)
Clears High Side Driver 2 Drain Source Monitoring status flag in OFF-State.
Definition: bdrv.h:1010
INLINE void BDRV_HS2_OC_Int_Clr(void)
Clears External High Side 2 FET Over-current interrupt flag.
Definition: bdrv.h:1005
TBDRV_Off_Diag BDRV_Off_Diagnosis(void)
Off-diagnosis.
TBdrv_Ch_Int
This enum lists the Bridge Driver channel Interrupt configuration.
Definition: bdrv.h:186
@ Int_DS
Drain-Source interrupt enable
Definition: bdrv.h:188
@ Int_Off
all interrupts disable
Definition: bdrv.h:187
@ Int_OC
Over-Current interrupt enable
Definition: bdrv.h:189
@ Int_DS_OC
Drain-Source and Over-Current interrupt enable.
Definition: bdrv.h:190
INLINE void BDRV_HS1_OC_Int_En(void)
Enables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:1078
INLINE void BDRV_LS1_DS_Int_Clr(void)
Clears Low Side Driver 1 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:1063
INLINE void BDRV_HS2_DS_Int_Clr(void)
Clears High Side Driver 2 Drain Source Monitoring status flag in OFF-State.
Definition: bdrv.h:1015
INLINE void BDRV_LS2_OC_Int_Dis(void)
Disables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:1114
void BDRV_Set_Channel(TBdrv_Ch BDRV_Ch, TBdrv_Ch_Cfg Ch_Cfg)
sets an individual driver of the BridgeDriver in the desired state
INLINE void BDRV_LS1_DS_SC_Clr(void)
Clears Low Side Driver 1 Drain Source Monitoring status flag in OFF-State.
Definition: bdrv.h:1058
void BDRV_Set_Channel_Comp(uint8 gain_hs, uint8 gain_ls)
Sets Gain for Low/High Side Charge Current Compensation.
INLINE void BDRV_SEQ_ERR_Int_Clr(void)
Clears Driver Sequence Error interrupt flag.
Definition: bdrv.h:999
INLINE void BDRV_HS1_DS_Int_En(void)
Enables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1120
INLINE void BDRV_LS2_DS_SC_Clr(void)
Clears Low Side Driver 2 Drain Source Monitoring status flag in OFF-State.
Definition: bdrv.h:1042
INLINE void BDRV_LS1_OC_Int_Clr(void)
Clears External Low Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:1053
INLINE void BDRV_LS2_OC_Int_En(void)
Enables External Low Side 2 FET Over-current interrupt.
Definition: bdrv.h:1109
INLINE void BDRV_LS2_DS_Int_Dis(void)
Disables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1156
INLINE void BDRV_LS1_DS_Int_En(void)
Enables Low Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1130
INLINE void BDRV_HS2_OC_Int_En(void)
Enables External High Side 2 FET Over-current interrupt.
Definition: bdrv.h:1099
INLINE void BDRV_LS2_DS_Int_En(void)
Enables Low Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1151
TBDRV_Off_Diag_Sts
This enum lists the Bridge Driver Off Diagnosis Status configuration.
Definition: bdrv.h:166
@ Ch_Ok
Definition: bdrv.h:167
@ Ch_Short_to_Gnd
Definition: bdrv.h:168
@ Ch_Short_to_VBat
Definition: bdrv.h:169
TBdrv_Ch
This enum lists the Bridge Driver channel configuration.
Definition: bdrv.h:136
@ HS2
Phase2 High Side MOSFET.
Definition: bdrv.h:140
@ HS1
Phase1 High Side MOSFET.
Definition: bdrv.h:139
@ LS2
Phase2 Low Side MOSFET
Definition: bdrv.h:138
@ LS1
Phase1 Low Side MOSFET
Definition: bdrv.h:137
void BDRV_Set_DSM_Threshold(TBdrv_DSM_Threshold BDRV_Threshold)
Sets the Voltage Threshold for Drain-Source Monitoring of external FETs.
INLINE void BDRV_HS1_OC_Int_Dis(void)
Disables External High Side 1 FET Over-current interrupt.
Definition: bdrv.h:1083
INLINE void BDRV_SEQ_ERR_Int_Dis(void)
Disables Driver Sequence Error interrupt.
Definition: bdrv.h:1073
INLINE void BDRV_HS1_OC_Int_Clr(void)
Clears External High Side 1 FET Over-current interrupt flag.
Definition: bdrv.h:1021
TBdrv_Ch_Cfg
This enum lists the Bridge Driver High Side channel configuration.
Definition: bdrv.h:124
@ Ch_On
channel enabled and static on
Definition: bdrv.h:128
@ Ch_DCS
channel enabled with Diag.-Current Source (only for HS1/HS2)
Definition: bdrv.h:129
@ Ch_Off
channel disabled
Definition: bdrv.h:125
@ Ch_En
channel enabled
Definition: bdrv.h:126
@ Ch_PWM
channel enabled with PWM (CCU6 connection)
Definition: bdrv.h:127
void BDRV_Init(void)
Initializes the BridgeDriver based on the Config Wizard configuration.
INLINE void BDRV_HS1_DS_Int_Clr(void)
Clears High Side Driver 1 Drain Source Monitoring interrupt flag in OFF-State.
Definition: bdrv.h:1031
INLINE void BDRV_HS1_DS_Int_Dis(void)
Disables High Side Driver 1 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1125
INLINE void BDRV_HS2_DS_Int_Dis(void)
Disables High Side Driver 2 Drain Source Monitoring interrupt in OFF-State.
Definition: bdrv.h:1146
void BDRV_Set_Bridge(TBdrv_Ch_LS_Cfg LS1_Cfg, TBdrv_Ch_Cfg HS1_Cfg, TBdrv_Ch_LS_Cfg LS2_Cfg, TBdrv_Ch_Cfg HS2_Cfg)
Sets the bridge in the desired state. For each of the four drivers the state can be defined.
#define BDRV
Definition: tle985x.h:6267
#define BDRV_IRQEN_HS2_DS_IEN_Msk
Definition: tle985x.h:7851
#define BDRV_IRQEN_HS1_OC_IEN_Pos
Definition: tle985x.h:7852
#define BDRV_IRQCLR_HS1_DS_SC_Pos
Definition: tle985x.h:7825
#define BDRV_IRQCLR_SEQ_ERR_ISC_Pos
Definition: tle985x.h:7815
#define BDRV_IRQCLR_HS1_DS_ISC_Msk
Definition: tle985x.h:7828
#define BDRV_IRQCLR_HS2_DS_SC_Msk
Definition: tle985x.h:7820
#define BDRV_IRQCLR_LS2_OC_ISC_Pos
Definition: tle985x.h:7829
#define BDRV_IRQCLR_LS1_DS_SC_Msk
Definition: tle985x.h:7838
#define BDRV_IRQCLR_LS2_DS_SC_Msk
Definition: tle985x.h:7832
#define BDRV_IRQCLR_SEQ_ERR_ISC_Msk
Definition: tle985x.h:7816
#define BDRV_IRQCLR_LS1_DS_ISC_Pos
Definition: tle985x.h:7839
#define BDRV_IRQEN_LS2_DS_IEN_Pos
Definition: tle985x.h:7858
#define BDRV_IRQCLR_HS1_OC_ISC_Msk
Definition: tle985x.h:7824
#define BDRV_IRQEN_HS1_OC_IEN_Msk
Definition: tle985x.h:7853
#define BDRV_IRQCLR_LS1_DS_SC_Pos
Definition: tle985x.h:7837
#define BDRV_IRQCLR_HS1_DS_SC_Msk
Definition: tle985x.h:7826
#define BDRV_IRQCLR_HS2_OC_ISC_Pos
Definition: tle985x.h:7817
#define BDRV_IRQEN_LS1_DS_IEN_Msk
Definition: tle985x.h:7863
#define BDRV_IRQCLR_LS1_DS_ISC_Msk
Definition: tle985x.h:7840
#define BDRV_IRQCLR_HS2_DS_ISC_Pos
Definition: tle985x.h:7821
#define BDRV_IRQCLR_LS1_OC_ISC_Pos
Definition: tle985x.h:7835
#define BDRV_IRQCLR_HS2_OC_ISC_Msk
Definition: tle985x.h:7818
#define BDRV_IRQEN_SEQ_ERR_IEN_Pos
Definition: tle985x.h:7846
#define BDRV_IRQCLR_LS2_DS_ISC_Pos
Definition: tle985x.h:7833
#define BDRV_IRQEN_LS1_OC_IEN_Pos
Definition: tle985x.h:7860
#define BDRV_IRQEN_LS2_OC_IEN_Msk
Definition: tle985x.h:7857
#define BDRV_IRQEN_HS2_DS_IEN_Pos
Definition: tle985x.h:7850
#define BDRV_IRQEN_HS2_OC_IEN_Msk
Definition: tle985x.h:7849
#define BDRV_IRQCLR_LS2_DS_ISC_Msk
Definition: tle985x.h:7834
#define BDRV_IRQCLR_HS1_OC_ISC_Pos
Definition: tle985x.h:7823
#define BDRV_IRQEN_LS1_OC_IEN_Msk
Definition: tle985x.h:7861
#define BDRV_IRQCLR_LS2_DS_SC_Pos
Definition: tle985x.h:7831
#define BDRV_IRQEN_HS2_OC_IEN_Pos
Definition: tle985x.h:7848
#define BDRV_IRQEN_SEQ_ERR_IEN_Msk
Definition: tle985x.h:7847
#define BDRV_IRQEN_HS1_DS_IEN_Pos
Definition: tle985x.h:7854
#define BDRV_IRQEN_LS2_OC_IEN_Pos
Definition: tle985x.h:7856
#define BDRV_IRQCLR_HS2_DS_ISC_Msk
Definition: tle985x.h:7822
#define BDRV_IRQEN_LS1_DS_IEN_Pos
Definition: tle985x.h:7862
#define BDRV_IRQCLR_LS1_OC_ISC_Msk
Definition: tle985x.h:7836
#define BDRV_IRQCLR_HS1_DS_ISC_Pos
Definition: tle985x.h:7827
#define BDRV_IRQCLR_HS2_DS_SC_Pos
Definition: tle985x.h:7819
#define BDRV_IRQEN_HS1_DS_IEN_Msk
Definition: tle985x.h:7855
#define BDRV_IRQCLR_LS2_OC_ISC_Msk
Definition: tle985x.h:7830
#define BDRV_IRQEN_LS2_DS_IEN_Msk
Definition: tle985x.h:7859
SFR low level access library.
INLINE void Field_Wrt32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:358
INLINE void Field_Mod32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:378
This struct lists the Bridge Driver Off Diagnosis Status Phases configuration.
Definition: bdrv.h:176
TBDRV_Off_Diag_Sts Phase1
Definition: bdrv.h:178
bool GlobFailSts
Definition: bdrv.h:177
TBDRV_Off_Diag_Sts Phase2
Definition: bdrv.h:179
CMSIS register HeaderFile.
Device specific memory layout defines.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint32_t uint32
32 bit unsigned value
Definition: types.h:155