Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields

Detailed Description

CPU (CPU)

#include <tle985x.h>

Data Fields

__IM uint32_t RESERVED [4]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ENABLE: 1
 
      __IOM uint32_t   TICKINT: 1
 
      __IOM uint32_t   CLKSOURCE: 1
 
      __IM   uint32_t: 13
 
      __IM uint32_t   COUNTFLAG: 1
 
   }   bit
 
SYSTICK_CSR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RELOAD: 24
 
   }   bit
 
SYSTICK_RVR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   CURRENT: 24
 
   }   bit
 
SYSTICK_CVR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   TENMS: 24
 
      __IM   uint32_t: 6
 
      __IM uint32_t   SKEW: 1
 
      __IM uint32_t   NOREF: 1
 
   }   bit
 
SYSTICK_CALIB
 
__IM uint32_t RESERVED1 [56]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_WAKEUP: 1
 
      __IOM uint32_t   Int_MATHDIV: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   Int_CP: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_HS: 1
 
      __IOM uint32_t   Int_OPA: 1
 
      __IOM uint32_t   Int_DU: 1
 
      __IOM uint32_t   Int_MON: 1
 
      __IOM uint32_t   Int_PORT2: 1
 
   }   bit
 
NVIC_ISER
 
__IM uint32_t RESERVED2 [31]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_WAKEUP: 1
 
      __IOM uint32_t   Int_MATHDIV: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   Int_CP: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_HS: 1
 
      __IOM uint32_t   Int_OPA: 1
 
      __IOM uint32_t   Int_DU: 1
 
      __IOM uint32_t   Int_MON: 1
 
      __IOM uint32_t   Int_PORT2: 1
 
   }   bit
 
NVIC_ICER
 
__IM uint32_t RESERVED3 [31]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_WAKEUP: 1
 
      __IOM uint32_t   Int_MATHDIV: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   Int_CP: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_HS: 1
 
      __IOM uint32_t   Int_OPA: 1
 
      __IOM uint32_t   Int_DU: 1
 
      __IOM uint32_t   Int_MON: 1
 
      __IOM uint32_t   Int_PORT2: 1
 
   }   bit
 
NVIC_ISPR
 
__IM uint32_t RESERVED4 [31]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   Int_GPT1: 1
 
      __IOM uint32_t   Int_GPT2: 1
 
      __IOM uint32_t   Int_ADC2: 1
 
      __IOM uint32_t   Int_ADC1: 1
 
      __IOM uint32_t   Int_CCU6SR0: 1
 
      __IOM uint32_t   Int_CCU6SR1: 1
 
      __IOM uint32_t   Int_CCU6SR2: 1
 
      __IOM uint32_t   Int_CCU6SR3: 1
 
      __IOM uint32_t   Int_SSC1: 1
 
      __IOM uint32_t   Int_SSC2: 1
 
      __IOM uint32_t   Int_UART1: 1
 
      __IOM uint32_t   Int_UART2: 1
 
      __IOM uint32_t   Int_EXINT0: 1
 
      __IOM uint32_t   Int_EXINT1: 1
 
      __IOM uint32_t   Int_WAKEUP: 1
 
      __IOM uint32_t   Int_MATHDIV: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   Int_CP: 1
 
      __IOM uint32_t   Int_BDRV: 1
 
      __IOM uint32_t   Int_HS: 1
 
      __IOM uint32_t   Int_OPA: 1
 
      __IOM uint32_t   Int_DU: 1
 
      __IOM uint32_t   Int_MON: 1
 
      __IOM uint32_t   Int_PORT2: 1
 
   }   bit
 
NVIC_ICPR
 
__IM uint32_t RESERVED5 [95]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   PRI_GPT1: 2
 
      __IOM uint32_t   PRI_GPT2: 2
 
      __IOM uint32_t   PRI_ADC2: 2
 
      __IOM uint32_t   PRI_ADC1: 2
 
   }   bit
 
NVIC_IPR0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   PRI_CCU6SR0: 2
 
      __IOM uint32_t   PRI_CCU6SR1: 2
 
      __IOM uint32_t   PRI_CCU6SR2: 2
 
      __IOM uint32_t   PRI_CCU6SR3: 2
 
   }   bit
 
NVIC_IPR1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   PRI_SSC1: 2
 
      __IOM uint32_t   PRI_SSC2: 2
 
      __IOM uint32_t   PRI_UART1: 2
 
      __IOM uint32_t   PRI_UART2: 2
 
   }   bit
 
NVIC_IPR2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   PRI_EXINT0: 2
 
      __IOM uint32_t   PRI_EXINT1: 2
 
      __IOM uint32_t   PRI_WAKEUP: 2
 
      __IOM uint32_t   PRI_MATHDIV: 2
 
   }   bit
 
NVIC_IPR3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 14
 
      __IOM uint32_t   PRI_CP: 2
 
      __IOM uint32_t   PRI_BDRV: 2
 
      __IOM uint32_t   PRI_HS: 2
 
   }   bit
 
NVIC_IPR4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   PRI_OPA: 2
 
      __IOM uint32_t   PRI_DU: 2
 
      __IOM uint32_t   PRI_MON: 2
 
      __IOM uint32_t   PRI_PORT2: 2
 
   }   bit
 
NVIC_IPR5
 
__IM uint32_t RESERVED6 [570]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   REVISION: 4
 
      __IM uint32_t   PARTNO: 12
 
      __IM uint32_t   CONSTANT: 4
 
      __IM uint32_t   VARIANT: 4
 
      __IM uint32_t   IMPLEMENTER: 8
 
   }   bit
 
CPUID
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   VECTACTIVE: 6
 
      __IM   uint32_t: 6
 
      __IM uint32_t   VECTPENDING: 6
 
      __IM uint32_t   ISRPENDING: 1
 
      __OM uint32_t   PENDSTCLR: 1
 
      __IOM uint32_t   PENDSTSET: 1
 
      __OM uint32_t   PENDSVCLR: 1
 
      __IOM uint32_t   PENDSVSET: 1
 
      __IOM uint32_t   NMIPENDSET: 1
 
   }   bit
 
ICSR
 
__IM uint32_t RESERVED7
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __OM uint32_t   VECTCLRACTIVE: 1
 
      __OM uint32_t   SYSRESETREQ: 1
 
      __IM uint32_t   ENDIANNESS: 1
 
      __IOM uint32_t   VECTKEY: 16
 
   }   bit
 
AIRCR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IOM uint32_t   SLEEPONEXIT: 1
 
      __IOM uint32_t   SLEEPDEEP: 1
 
      __IOM uint32_t   SEVONPEND: 1
 
   }   bit
 
SCR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 3
 
      __IM uint32_t   UNALIGN_TRP: 1
 
      __IM uint32_t   STKALIGN: 1
 
   }   bit
 
CCR
 
__IM uint32_t RESERVED8
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 30
 
      __IOM uint32_t   PRI_11: 2
 
   }   bit
 
SHPR2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 22
 
      __IOM uint32_t   PRI_14: 2
 
      __IOM uint32_t   PRI_15: 2
 
   }   bit
 
SHPR3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 15
 
      __IOM uint32_t   SVCALLPENDED: 1
 
   }   bit
 
SHCSR
 

Field Documentation

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union { ... } AIRCR

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struct { ... } bit

◆  [22/22]

struct { ... } bit

◆ 

union { ... } CCR

◆ CLKSOURCE

__IOM uint32_t CLKSOURCE

[2..2] CLK Source

◆ CONSTANT

__IM uint32_t CONSTANT

[19..16] Constant

◆ COUNTFLAG

__IM uint32_t COUNTFLAG

[16..16] Count Flag

◆ 

union { ... } CPUID

◆ CURRENT

__IOM uint32_t CURRENT

[23..0] Current

◆ ENABLE

__IOM uint32_t ENABLE

[0..0] Enable

◆ ENDIANNESS

__IM uint32_t ENDIANNESS

[15..15] Data Endianness

◆ 

union { ... } ICSR

◆ IMPLEMENTER

__IM uint32_t IMPLEMENTER

[31..24] Implementer Code

◆ Int_ADC1

__IOM uint32_t Int_ADC1

[3..3] Interrupt Set for ADC1

[3..3] Interrupt Clear for ADC1

[3..3] Interrupt Set Pending for ADC1

[3..3] Interrupt Clear Pending for ADC1

◆ Int_ADC2

__IOM uint32_t Int_ADC2

[2..2] Interrupt Set for MU, ADC2

[2..2] Interrupt Clear for MU, ADC2

[2..2] Interrupt Set Pending for MU, ADC2

[2..2] Interrupt Clear Pending for MU, ADC2

◆ Int_BDRV

__IOM uint32_t Int_BDRV

[18..18] Interrupt Set for Bridge Driver

[18..18] Interrupt Clear for Bridge Driver

[18..18] Interrupt Set Pending for Bridge Driver

[18..18] Interrupt Clear Pending for Bridge Driver

◆ Int_CCU6SR0

__IOM uint32_t Int_CCU6SR0

[4..4] Interrupt Set for CCU6 SR0

[4..4] Interrupt Clear for CCU6 SR0

[4..4] Interrupt Set Pending for CCU6 SR0

[4..4] Interrupt Clear Pending for CCU6 SR0

◆ Int_CCU6SR1

__IOM uint32_t Int_CCU6SR1

[5..5] Interrupt Set for CCU6 SR1

[5..5] Interrupt Clear for CCU6 SR1

[5..5] Interrupt Set Pending for CCU6 SR1

[5..5] Interrupt Clear Pending for CCU6 SR1

◆ Int_CCU6SR2

__IOM uint32_t Int_CCU6SR2

[6..6] Interrupt Set for CCU6 SR2

[6..6] Interrupt Clear for CCU6 SR2

[6..6] Interrupt Set Pending for CCU6 SR2

[6..6] Interrupt Clear Pending for CCU6 SR2

◆ Int_CCU6SR3

__IOM uint32_t Int_CCU6SR3

[7..7] Interrupt Set for CCU6 SR3

[7..7] Interrupt Clear for CCU6 SR3

[7..7] Interrupt Set Pending for CCU6 SR3

[7..7] Interrupt Clear Pending for CCU6 SR3

◆ Int_CP

__IOM uint32_t Int_CP

[17..17] Interrupt Set for Charge Pump

[17..17] Interrupt Clear for Charge Pump

[17..17] Interrupt Set Pending for Charge Pump

[17..17] Interrupt Clear Pending for Charge Pump

◆ Int_DU

__IOM uint32_t Int_DU

[21..21] Interrupt Set for Differential Unit

[21..21] Interrupt Clear for Differential Unit

[21..21] Interrupt Set Pending for Differential Unit

[21..21] Interrupt Clear Pending for Differential Unit

◆ Int_EXINT0

__IOM uint32_t Int_EXINT0

[12..12] Interrupt Set for External Int 0

[12..12] Interrupt Clear for External Int 0

[12..12] Interrupt Set Pending for External Int 0

[12..12] Interrupt Clear Pending for External Int 0

◆ Int_EXINT1

__IOM uint32_t Int_EXINT1

[13..13] Interrupt Set for External Int 1

[13..13] Interrupt Clear for External Int 1

[13..13] Interrupt Set Pending for External Int 1

[13..13] Interrupt Clear Pending for External Int 1

◆ Int_GPT1

__IOM uint32_t Int_GPT1

[0..0] Interrupt Set for GPT1

[0..0] Interrupt Clear for GPT1

[0..0] Interrupt Set Pending for GPT1

[0..0] Interrupt Clear Pending for GPT1

◆ Int_GPT2

__IOM uint32_t Int_GPT2

[1..1] Interrupt Set for GPT2

[1..1] Interrupt Clear for GPT2

[1..1] Interrupt Set Pending for GPT2

[1..1] Interrupt Clear Pending for GPT2

◆ Int_HS

__IOM uint32_t Int_HS

[19..19] Interrupt Set for High-Side Switch

[19..19] Interrupt Clear for High-Side Switch

[19..19] Interrupt Set Pending for High-Side Switch

[19..19] Interrupt Clear Pending for High-Side Switch

◆ Int_MATHDIV

__IOM uint32_t Int_MATHDIV

[15..15] Interrupt Set for Math Divider

[15..15] Interrupt Clear for Math Divider

[15..15] Interrupt Set Pending for Math Divider

[15..15] Interrupt Clear Pending for Math Divider

◆ Int_MON

__IOM uint32_t Int_MON

[22..22] Interrupt Set for MON

[22..22] Interrupt Clear for MON

[22..22] Interrupt Set Pending for MON

[22..22] Interrupt Clear Pending for MON

◆ Int_OPA

__IOM uint32_t Int_OPA

[20..20] Interrupt Set for Current Sense Amplifier

[20..20] Interrupt Clear for Current Sense Amplifier

[20..20] Interrupt Set Pending for Current Sense Amplifier

[20..20] Interrupt Clear Pending for Current Sense Amplifier

◆ Int_PORT2

__IOM uint32_t Int_PORT2

[23..23] Interrupt Set for PORT2

[23..23] Interrupt Clear for PORT2

[23..23] Interrupt Set Pending for PORT2

[23..23] Interrupt Clear Pending for PORT2

◆ Int_SSC1

__IOM uint32_t Int_SSC1

[8..8] Interrupt Set for SSC1

[8..8] Interrupt Clear for SSC1

[8..8] Interrupt Set Pending for SSC1

[8..8] Interrupt Clear Pending for SSC1

◆ Int_SSC2

__IOM uint32_t Int_SSC2

[9..9] Interrupt Set for SSC2

[9..9] Interrupt Clear for SSC2

[9..9] Interrupt Set Pending for SSC2

[9..9] Interrupt Clear Pending for SSC2

◆ Int_UART1

__IOM uint32_t Int_UART1

[10..10] Interrupt Set for UART1

[10..10] Interrupt Clear for UART1

[10..10] Interrupt Set Pending for UART1

[10..10] Interrupt Clear Pending for UART1

◆ Int_UART2

__IOM uint32_t Int_UART2

[11..11] Interrupt Set for UART2

[11..11] Interrupt Clear for UART2

[11..11] Interrupt Set Pending for UART2

[11..11] Interrupt Clear Pending for UART2

◆ Int_WAKEUP

__IOM uint32_t Int_WAKEUP

[14..14] Interrupt Set for WAKEUP

[14..14] Interrupt Clear for WAKEUP

[14..14] Interrupt Set Pending for WAKEUP

[14..14] Interrupt Clear Pending for WAKEUP

◆ ISRPENDING

__IM uint32_t ISRPENDING

[22..22] Interrupt Pending Flag

◆ NMIPENDSET

__IOM uint32_t NMIPENDSET

[31..31] NMI Set Pending

◆ NOREF

__IM uint32_t NOREF

[31..31] No Reference Clock

◆ 

union { ... } NVIC_ICER

◆ 

union { ... } NVIC_ICPR

◆ 

union { ... } NVIC_IPR0

◆ 

union { ... } NVIC_IPR1

◆ 

union { ... } NVIC_IPR2

◆ 

union { ... } NVIC_IPR3

◆ 

union { ... } NVIC_IPR4

◆ 

union { ... } NVIC_IPR5

◆ 

union { ... } NVIC_ISER

◆ 

union { ... } NVIC_ISPR

◆ PARTNO

__IM uint32_t PARTNO

[15..4] Part Number

◆ PENDSTCLR

__OM uint32_t PENDSTCLR

[25..25] SysTick Exception Clear Pending

◆ PENDSTSET

__IOM uint32_t PENDSTSET

[26..26] SysTick Exception Set Pending

◆ PENDSVCLR

__OM uint32_t PENDSVCLR

[27..27] PENDSV Clear Pending

◆ PENDSVSET

__IOM uint32_t PENDSVSET

[28..28] PENDSV Set Pending

◆ PRI_11

__IOM uint32_t PRI_11

[31..30] Priority of System Handler 11, SVCall

◆ PRI_14

__IOM uint32_t PRI_14

[23..22] Priority of System Handler 14, PendSV

◆ PRI_15

__IOM uint32_t PRI_15

[31..30] Priority of System Handler 15, SysTick

◆ PRI_ADC1

__IOM uint32_t PRI_ADC1

[31..30] Priority for ADC1

◆ PRI_ADC2

__IOM uint32_t PRI_ADC2

[23..22] Priority for MU, ADC2

◆ PRI_BDRV

__IOM uint32_t PRI_BDRV

[23..22] Priority for Bridge Driver

◆ PRI_CCU6SR0

__IOM uint32_t PRI_CCU6SR0

[7..6] Priority for CCU6 SR0

◆ PRI_CCU6SR1

__IOM uint32_t PRI_CCU6SR1

[15..14] Priority for CCU6 SR1

◆ PRI_CCU6SR2

__IOM uint32_t PRI_CCU6SR2

[23..22] Priority for CCU6 SR2

◆ PRI_CCU6SR3

__IOM uint32_t PRI_CCU6SR3

[31..30] Priority for CCU6 SR3

◆ PRI_CP

__IOM uint32_t PRI_CP

[15..14] Priority for Charge Pump

◆ PRI_DU

__IOM uint32_t PRI_DU

[15..14] Priority for Differential Unit

◆ PRI_EXINT0

__IOM uint32_t PRI_EXINT0

[7..6] Priority for External Int 0

◆ PRI_EXINT1

__IOM uint32_t PRI_EXINT1

[15..14] Priority for External Int 1

◆ PRI_GPT1

__IOM uint32_t PRI_GPT1

[7..6] Priority for GPT1

◆ PRI_GPT2

__IOM uint32_t PRI_GPT2

[15..14] Priority for GPT2

◆ PRI_HS

__IOM uint32_t PRI_HS

[31..30] Priority for High-Side Switch

◆ PRI_MATHDIV

__IOM uint32_t PRI_MATHDIV

[31..30] Priority for Math Divider

◆ PRI_MON

__IOM uint32_t PRI_MON

[23..22] Priority for MON

◆ PRI_OPA

__IOM uint32_t PRI_OPA

[7..6] Priority for Current Sense Amplifier

◆ PRI_PORT2

__IOM uint32_t PRI_PORT2

[31..30] Priority for PORT2

◆ PRI_SSC1

__IOM uint32_t PRI_SSC1

[7..6] Priority for SSC1

◆ PRI_SSC2

__IOM uint32_t PRI_SSC2

[15..14] Priority for SSC2

◆ PRI_UART1

__IOM uint32_t PRI_UART1

[23..22] Priority for UART1

◆ PRI_UART2

__IOM uint32_t PRI_UART2

[31..30] Priority for UART2

◆ PRI_WAKEUP

__IOM uint32_t PRI_WAKEUP

[23..22] Priority for WAKEUP

◆ reg

(@ 0x00000010) SysTick Control and Status Register

(@ 0x00000014) SysTick Reload Value Register

(@ 0x00000018) SysTick Current Value Register

(@ 0x0000001C) SysTick Calibration Value Register

(@ 0x00000100) Interrupt Set-Enable

(@ 0x00000180) Interrupt Clear-Enable

(@ 0x00000200) Interrupt Set-Pending

(@ 0x00000280) Interrupt Clear-Pending

(@ 0x00000400) Interrupt Priority

(@ 0x00000404) Interrupt Priority

(@ 0x00000408) Interrupt Priority

(@ 0x0000040C) Interrupt Priority

(@ 0x00000410) Interrupt Priority

(@ 0x00000414) Interrupt Priority

(@ 0x00000D00) CPU ID Base Register

(@ 0x00000D04) Interrupt Control and State Register

(@ 0x00000D0C) Application Interrupt/Reset Control Register

(@ 0x00000D10) System Control Register

(@ 0x00000D14) Configuration Control Register

(@ 0x00000D1C) System Handler Priority Register 2

(@ 0x00000D20) System Handler Priority Register 3

(@ 0x00000D24) System Handler Control and State Register

◆ RELOAD

__IOM uint32_t RELOAD

[23..0] Reload

◆ RESERVED

__IM uint32_t RESERVED[4]

< (@ 0xE000E000) CPU Structure

◆ RESERVED1

__IM uint32_t RESERVED1[56]

◆ RESERVED2

__IM uint32_t RESERVED2[31]

◆ RESERVED3

__IM uint32_t RESERVED3[31]

◆ RESERVED4

__IM uint32_t RESERVED4[31]

◆ RESERVED5

__IM uint32_t RESERVED5[95]

◆ RESERVED6

__IM uint32_t RESERVED6[570]

◆ RESERVED7

__IM uint32_t RESERVED7

◆ RESERVED8

__IM uint32_t RESERVED8

◆ REVISION

__IM uint32_t REVISION

[3..0] Revision Number

◆ 

union { ... } SCR

◆ SEVONPEND

__IOM uint32_t SEVONPEND

[4..4] SEVONPEND

◆ 

union { ... } SHCSR

◆ 

union { ... } SHPR2

◆ 

union { ... } SHPR3

◆ SKEW

__IM uint32_t SKEW

[30..30] Skew

◆ SLEEPDEEP

__IOM uint32_t SLEEPDEEP

[2..2] Sleep Deep

◆ SLEEPONEXIT

__IOM uint32_t SLEEPONEXIT

[1..1] Sleep on Exit

◆ STKALIGN

__IM uint32_t STKALIGN

[9..9] STKALIGN

◆ SVCALLPENDED

__IOM uint32_t SVCALLPENDED

[15..15] SVCALLPENDED

◆ SYSRESETREQ

__OM uint32_t SYSRESETREQ

[2..2] System Reset Request

◆ 

union { ... } SYSTICK_CALIB

◆ 

union { ... } SYSTICK_CSR

◆ 

union { ... } SYSTICK_CVR

◆ 

union { ... } SYSTICK_RVR

◆ TENMS

__IM uint32_t TENMS

[23..0] Tenms

◆ TICKINT

__IOM uint32_t TICKINT

[1..1] TICKINT

◆ uint32_t

__IM uint32_t

◆ UNALIGN_TRP

__IM uint32_t UNALIGN_TRP

[3..3] UNALIGN_TRP

◆ VARIANT

__IM uint32_t VARIANT

[23..20] Variant Number

◆ VECTACTIVE

__IM uint32_t VECTACTIVE

[5..0] VECTACTIVE

◆ VECTCLRACTIVE

__OM uint32_t VECTCLRACTIVE

[1..1] VECTCLRACTIVE

◆ VECTKEY

__IOM uint32_t VECTKEY

[31..16] Vector Key

◆ VECTPENDING

__IM uint32_t VECTPENDING

[17..12] VECTPENDING


The documentation for this struct was generated from the following file: