Infineon MOTIX™ MCU TLE985x Device Family SDK
gpt12e.h
Go to the documentation of this file.
1 /*
2  ***********************************************************************************************************************
3  *
4  * Copyright (c) 2018-2022, Infineon Technologies AG
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
8  * following conditions are met:
9  *
10  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
11  * disclaimer.
12  *
13  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
14  * following disclaimer in the documentation and/or other materials provided with the distribution.
15  *
16  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
17  * products derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  **********************************************************************************************************************/
39 /*******************************************************************************
40 ** Author(s) Identity **
41 ********************************************************************************
42 ** Initials Name **
43 ** ---------------------------------------------------------------------------**
44 ** TS T&S **
45 ** BG Blandine Guillot **
46 ** JO Julia Ott **
47 *******************************************************************************/
48 
49 /*******************************************************************************
50 ** Revision Control History **
51 ********************************************************************************
52 ** V0.2.0: 2018-02-13, TS: Initial version of revision history **
53 ** V0.2.1: 2019-01-28, TS: __STATIC_INLINE changed to INLINE **
54 ** Doxygen update **
55 ** Revision history moved from gpt12e.c to gpt12e.h **
56 ** V0.2.2: 2020-03-02, BG: Updated revision history format **
57 ** V0.2.3: 2020-03-02, JO: EP-435: Removed ARMCC v6 compiler warnings **
58 ** V0.2.4: 2022-01-21, JO: EP-934: Updated copyright and branding **
59 *******************************************************************************/
60 
61 #ifndef GPT12E_H
62 #define GPT12E_H
63 
64 /*******************************************************************************
65 ** Includes **
66 *******************************************************************************/
67 #include "tle985x.h"
68 #include "types.h"
69 #include "sfr_access.h"
70 
71 /*******************************************************************************
72 ** Global Type Definitions **
73 *******************************************************************************/
77 typedef enum
78 {
82  GPT1_fSYS_Div_32 = 2u
84 
88 typedef enum
89 {
101  GPT12E_CCU6_ANY_CHx = 11u
103 
107 typedef enum
108 {
110  GPT12E_T2INB_P14 = 1u
112 
116 typedef enum
117 {
119  GPT12E_T2EUDB_P23 = 1u
121 
125 typedef enum
126 {
130  GPT12E_T3IND_P23 = 3u
132 
136 typedef enum
137 {
141  GPT12E_T3EUDD_P03 = 3u
143 
147 typedef enum
148 {
154 
158 typedef enum
159 {
163  GPT12E_T4EUDD_P21 = 3u
165 
169 typedef enum
170 {
174  GPT2_fSYS_Div_16 = 2u
176 
180 typedef enum
181 {
183  GPT12E_T5INB_P11 = 1u
185 
189 typedef enum
190 {
192  GPT12E_T5EUDB_P20 = 1u
194 
198 typedef enum
199 {
201  GPT12E_T6INB_COUT61 = 1u
203 
207 typedef enum
208 {
210  GPT12E_T6EUDB_P22 = 1u
212 
216 typedef enum
217 {
223 
227 typedef enum
228 {
236  GPT_Clk_Div_128 = 7
238 
239 /*******************************************************************************
240 ** Global Function Declarations **
241 *******************************************************************************/
246 void GPT12E_Init(void);
247 
267 bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us);
268 
288 bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us);
289 
290 /*******************************************************************************
291 ** Inline Function Declarations **
292 *******************************************************************************/
308 
326 
342 
356 
370 
384 
398 
412 
426 
440 
454 
471 
488 
503 
518 
533 
548 
563 
578 
593 
608 
623 
638 
653 
668 
683 
698 
713 
728 
743 
758 
773 
788 
803 
818 
833 
848 
863 
878 
893 
908 
923 
938 
952 INLINE void GPT12E_T2_Start(void);
953 
967 INLINE void GPT12E_T2_Stop(void);
968 
983 
998 
1012 INLINE void GPT12E_T2_DownCount_Sel(void);
1013 
1027 INLINE void GPT12E_T2_UpCount_Sel(void);
1028 
1042 
1057 
1072 
1087 
1107 
1125 
1145 
1163 
1181 
1197 
1215 
1232 
1245 INLINE void GPT12E_T3_Mode_Timer_Sel(void);
1246 
1260 
1274 
1288 
1302 
1316 
1333 
1350 
1365 
1380 
1395 
1410 
1425 
1440 
1455 
1470 
1483 INLINE void GPT12E_T3_Start(void);
1484 
1497 INLINE void GPT12E_T3_Stop(void);
1498 
1511 INLINE void GPT12E_T3_Output_En(void);
1512 
1525 INLINE void GPT12E_T3_Output_Dis(void);
1526 
1540 INLINE void GPT12E_T3_Output_Set(void);
1541 
1555 INLINE void GPT12E_T3_Output_Rst(void);
1556 
1570 INLINE void GPT12E_T3_DownCount_Sel(void);
1571 
1585 INLINE void GPT12E_T3_UpCount_Sel(void);
1586 
1600 
1615 
1630 
1645 
1665 
1683 
1703 
1721 
1739 
1755 
1773 
1790 
1803 INLINE void GPT12E_T4_Mode_Timer_Sel(void);
1804 
1818 
1832 
1846 
1860 
1874 
1888 
1902 
1919 
1936 
1951 
1966 
1981 
1996 
2011 
2026 
2041 
2056 
2071 
2086 
2101 
2116 
2131 
2146 
2161 
2176 
2191 
2206 
2221 
2236 
2251 
2266 
2281 
2296 
2311 
2326 
2341 
2356 
2371 
2385 INLINE void GPT12E_T4_Start(void);
2386 
2400 INLINE void GPT12E_T4_Stop(void);
2401 
2415 INLINE void GPT12E_T4_Start_by_T3_En(void);
2416 
2431 
2445 INLINE void GPT12E_T4_DownCount_Sel(void);
2446 
2460 INLINE void GPT12E_T4_UpCount_Sel(void);
2461 
2475 
2490 
2505 
2520 
2535 INLINE void GPT12E_T4_Clr_T2_En(void);
2536 
2549 INLINE void GPT12E_T4_Clr_T2_Dis(void);
2550 
2565 INLINE void GPT12E_T4_Clr_T3_En(void);
2566 
2579 INLINE void GPT12E_T4_Clr_T3_Dis(void);
2580 
2600 
2618 
2638 
2656 
2674 
2690 
2708 
2725 
2741 
2759 
2772 INLINE void GPT12E_T5_Mode_Timer_Sel(void);
2773 
2787 
2801 
2815 
2832 
2849 
2864 
2879 
2894 
2909 
2924 
2939 
2954 
2969 
2984 
2997 INLINE void GPT12E_T5_Capture_En(void);
2998 
3011 INLINE void GPT12E_T5_Capture_Dis(void);
3012 
3027 
3043 
3059 
3075 
3091 
3106 
3122 
3138 
3154 
3170 
3185 
3200 
3219 
3233 INLINE void GPT12E_T5_Start(void);
3234 
3248 INLINE void GPT12E_T5_Stop(void);
3249 
3264 
3278 INLINE void GPT12E_T5_Start_by_T6_En(void);
3279 
3293 INLINE void GPT12E_T5_DownCount_Sel(void);
3294 
3308 INLINE void GPT12E_T5_UpCount_Sel(void);
3309 
3323 
3338 
3356 
3372 
3390 
3407 
3420 INLINE void GPT12E_T6_Mode_Timer_Sel(void);
3421 
3435 
3449 
3463 
3480 
3497 
3512 
3527 
3542 
3557 
3570 INLINE void GPT12E_T6_Reload_En(void);
3571 
3584 INLINE void GPT12E_T6_Reload_Dis(void);
3585 
3602 
3617 
3632 
3645 INLINE void GPT12E_T6_Start(void);
3646 
3659 INLINE void GPT12E_T6_Stop(void);
3660 
3673 INLINE void GPT12E_T6_Output_En(void);
3674 
3687 INLINE void GPT12E_T6_Output_Dis(void);
3688 
3702 INLINE void GPT12E_T6_Output_Set(void);
3703 
3717 INLINE void GPT12E_T6_Output_Rst(void);
3718 
3732 INLINE void GPT12E_T6_DownCount_Sel(void);
3733 
3747 INLINE void GPT12E_T6_UpCount_Sel(void);
3748 
3762 
3777 
3795 
3811 
3829 
3846 
3865 
3887 
3909 
3931 
3953 
3975 
3997 
4016 INLINE void GPT12E_T2_Int_Clr(void);
4017 
4036 INLINE void GPT12E_T3_Int_Clr(void);
4037 
4056 INLINE void GPT12E_T4_Int_Clr(void);
4057 
4076 INLINE void GPT12E_T5_Int_Clr(void);
4077 
4096 INLINE void GPT12E_T6_Int_Clr(void);
4097 
4116 INLINE void GPT12E_CapRel_Int_Clr(void);
4117 
4136 INLINE void GPT12E_T2_Int_En(void);
4137 
4156 INLINE void GPT12E_T2_Int_Dis(void);
4157 
4176 INLINE void GPT12E_T3_Int_En(void);
4177 
4196 INLINE void GPT12E_T3_Int_Dis(void);
4197 
4216 INLINE void GPT12E_T4_Int_En(void);
4217 
4236 INLINE void GPT12E_T4_Int_Dis(void);
4237 
4256 INLINE void GPT12E_T5_Int_En(void);
4257 
4276 INLINE void GPT12E_T5_Int_Dis(void);
4277 
4296 INLINE void GPT12E_T6_Int_En(void);
4297 
4316 INLINE void GPT12E_T6_Int_Dis(void);
4317 
4336 INLINE void GPT12E_CapRel_Int_En(void);
4337 
4356 INLINE void GPT12E_CapRel_Int_Dis(void);
4357 
4358 
4359 /*******************************************************************************
4360 ** Inline Function Definitions **
4361 *******************************************************************************/
4363 {
4365 }
4366 
4368 {
4370 }
4371 
4373 {
4375 }
4376 
4378 {
4380 }
4381 
4383 {
4385 }
4386 
4388 {
4390 }
4391 
4393 {
4395 }
4396 
4398 {
4400 }
4401 
4403 {
4405 }
4406 
4408 {
4410 }
4411 
4413 {
4415 }
4416 
4418 {
4420 }
4421 
4423 {
4425 }
4426 
4428 {
4429  Field_Mod32(&GPT12E->T2CON.reg, (uint8)2u, 4u, 0u);
4430 }
4431 
4433 {
4434  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 1u);
4435 }
4436 
4438 {
4439  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 0u);
4440 }
4441 
4443 {
4444  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 1u);
4445 }
4446 
4448 {
4449  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 0u);
4450 }
4451 
4453 {
4454  Field_Mod32(&GPT12E->T2CON.reg, (uint8)2u, 4u, 1u);
4455 }
4456 
4458 {
4459  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 1u);
4460 }
4461 
4463 {
4464  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 0u);
4465 }
4466 
4468 {
4469  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 1u);
4470 }
4471 
4473 {
4474  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 0u);
4475 }
4476 
4478 {
4479  Field_Mod32(&GPT12E->T2CON.reg, (uint8)2u, 4u, 0u);
4480 }
4481 
4483 {
4484  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 1u);
4485 }
4486 
4488 {
4489  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 0u);
4490 }
4491 
4493 {
4494  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 1u);
4495 }
4496 
4498 {
4499  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 0u);
4500 }
4501 
4503 {
4504  Field_Mod32(&GPT12E->T2CON.reg, (uint8)2u, 4u, 0u);
4505 }
4506 
4508 {
4509  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 1u);
4510 }
4511 
4513 {
4514  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 0u);
4515 }
4516 
4518 {
4519  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 1u);
4520 }
4521 
4523 {
4524  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 0u);
4525 }
4526 
4528 {
4529  Field_Mod32(&GPT12E->T2CON.reg, (uint8)2u, 4u, 1u);
4530 }
4531 
4533 {
4534  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 1u);
4535 }
4536 
4538 {
4539  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 0u);
4540 }
4541 
4543 {
4544  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 1u);
4545 }
4546 
4548 {
4549  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 0u);
4550 }
4551 
4553 {
4554  Field_Mod32(&GPT12E->T2CON.reg, (uint8)2u, 4u, 0u);
4555 }
4556 
4558 {
4559  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 1u);
4560 }
4561 
4563 {
4564  Field_Mod32(&GPT12E->T2CON.reg, (uint8)0u, 1u, 0u);
4565 }
4566 
4568 {
4569  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 1u);
4570 }
4571 
4573 {
4574  Field_Mod32(&GPT12E->T2CON.reg, (uint8)1u, 2u, 0u);
4575 }
4576 
4578 {
4580 }
4581 
4583 {
4585 }
4586 
4588 {
4590 }
4591 
4593 {
4595 }
4596 
4598 {
4600 }
4601 
4603 {
4605 }
4606 
4608 {
4610 }
4611 
4613 {
4615 }
4616 
4618 {
4620 }
4621 
4623 {
4625 }
4626 
4628 {
4630 }
4631 
4633 {
4635 }
4636 
4638 {
4640 }
4641 
4643 {
4645 }
4646 
4648 {
4650 }
4651 
4653 {
4655 }
4656 
4658 {
4660 }
4661 
4663 {
4665 }
4666 
4668 {
4670 }
4671 
4673 {
4675 }
4676 
4678 {
4680 }
4681 
4683 {
4685 }
4686 
4688 {
4690 }
4691 
4693 {
4695 }
4696 
4698 {
4700 }
4701 
4703 {
4705 }
4706 
4708 {
4709  Field_Mod32(&GPT12E->T3CON.reg, (uint8)0u, 1u, 1u);
4710 }
4711 
4713 {
4714  Field_Mod32(&GPT12E->T3CON.reg, (uint8)0u, 1u, 0u);
4715 }
4716 
4718 {
4719  Field_Mod32(&GPT12E->T3CON.reg, (uint8)1u, 2u, 1u);
4720 }
4721 
4723 {
4724  Field_Mod32(&GPT12E->T3CON.reg, (uint8)1u, 2u, 0u);
4725 }
4726 
4728 {
4729  Field_Mod32(&GPT12E->T3CON.reg, (uint8)0u, 1u, 1u);
4730 }
4731 
4733 {
4734  Field_Mod32(&GPT12E->T3CON.reg, (uint8)0u, 1u, 0u);
4735 }
4736 
4738 {
4739  Field_Mod32(&GPT12E->T3CON.reg, (uint8)1u, 2u, 1u);
4740 }
4741 
4743 {
4744  Field_Mod32(&GPT12E->T3CON.reg, (uint8)1u, 2u, 0u);
4745 }
4746 
4748 {
4750 }
4751 
4753 {
4755 }
4756 
4758 {
4760 }
4761 
4763 {
4765 }
4766 
4768 {
4770 }
4771 
4773 {
4775 }
4776 
4778 {
4780 }
4781 
4783 {
4785 }
4786 
4788 {
4790 }
4791 
4793 {
4795 }
4796 
4798 {
4800 }
4801 
4803 {
4805 }
4806 
4808 {
4810 }
4811 
4813 {
4815 }
4816 
4818 {
4820 }
4821 
4823 {
4825 }
4826 
4828 {
4830 }
4831 
4833 {
4835 }
4836 
4838 {
4840 }
4841 
4843 {
4845 }
4846 
4848 {
4850 }
4851 
4853 {
4855 }
4856 
4858 {
4860 }
4861 
4863 {
4865 }
4866 
4868 {
4870 }
4871 
4873 {
4875 }
4876 
4878 {
4880 }
4881 
4883 {
4885 }
4886 
4888 {
4890 }
4891 
4893 {
4895 }
4896 
4898 {
4899  Field_Mod32(&GPT12E->T4CON.reg, (uint8)2u, 4u, 0u);
4900 }
4901 
4903 {
4904  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 1u);
4905 }
4906 
4908 {
4909  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 0u);
4910 }
4911 
4913 {
4914  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 1u);
4915 }
4916 
4918 {
4919  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 0u);
4920 }
4921 
4923 {
4924  Field_Mod32(&GPT12E->T4CON.reg, (uint8)2u, 4u, 1u);
4925 }
4926 
4928 {
4929  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 1u);
4930 }
4931 
4933 {
4934  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 0u);
4935 }
4936 
4938 {
4939  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 1u);
4940 }
4941 
4943 {
4944  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 0u);
4945 }
4946 
4948 {
4949  Field_Mod32(&GPT12E->T4CON.reg, (uint8)2u, 4u, 0u);
4950 }
4951 
4953 {
4954  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 1u);
4955 }
4956 
4958 {
4959  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 0u);
4960 }
4961 
4963 {
4964  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 1u);
4965 }
4966 
4968 {
4969  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 0u);
4970 }
4971 
4973 {
4974  Field_Mod32(&GPT12E->T4CON.reg, (uint8)2u, 4u, 0u);
4975 }
4976 
4978 {
4979  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 1u);
4980 }
4981 
4983 {
4984  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 0u);
4985 }
4986 
4988 {
4989  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 1u);
4990 }
4991 
4993 {
4994  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 0u);
4995 }
4996 
4998 {
4999  Field_Mod32(&GPT12E->T4CON.reg, (uint8)2u, 4u, 1u);
5000 }
5001 
5003 {
5004  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 1u);
5005 }
5006 
5008 {
5009  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 0u);
5010 }
5011 
5013 {
5014  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 1u);
5015 }
5016 
5018 {
5019  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 0u);
5020 }
5021 
5023 {
5024  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 1u);
5025 }
5026 
5028 {
5029  Field_Mod32(&GPT12E->T4CON.reg, (uint8)0u, 1u, 0u);
5030 }
5031 
5033 {
5034  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 1u);
5035 }
5036 
5038 {
5039  Field_Mod32(&GPT12E->T4CON.reg, (uint8)1u, 2u, 0u);
5040 }
5041 
5043 {
5045 }
5046 
5048 {
5050 }
5051 
5053 {
5055 }
5056 
5058 {
5060 }
5061 
5063 {
5065 }
5066 
5068 {
5070 }
5071 
5073 {
5075 }
5076 
5078 {
5080 }
5081 
5083 {
5085 }
5086 
5088 {
5090 }
5091 
5093 {
5095 }
5096 
5098 {
5100 }
5101 
5103 {
5105 }
5106 
5108 {
5110 }
5111 
5113 {
5115 }
5116 
5118 {
5120 }
5121 
5123 {
5125 }
5126 
5128 {
5130 }
5131 
5133 {
5135 }
5136 
5138 {
5140 }
5141 
5143 {
5145 }
5146 
5148 {
5150 }
5151 
5153 {
5155 }
5156 
5158 {
5160 }
5161 
5163 {
5165 }
5166 
5168 {
5170 }
5171 
5173 {
5175 }
5176 
5178 {
5180 }
5181 
5183 {
5185 }
5186 
5188 {
5190 }
5191 
5193 {
5194  Field_Mod32(&GPT12E->T5CON.reg, (uint8)2u, 4u, 0u);
5195 }
5196 
5198 {
5199  Field_Mod32(&GPT12E->T5CON.reg, (uint8)0u, 1u, 1u);
5200 }
5201 
5203 {
5204  Field_Mod32(&GPT12E->T5CON.reg, (uint8)1u, 2u, 1u);
5205 }
5206 
5208 {
5209  Field_Mod32(&GPT12E->T5CON.reg, (uint8)0u, 3u, 3u);
5210 }
5211 
5213 {
5214  Field_Mod32(&GPT12E->T5CON.reg, (uint8)2u, 4u, 1u);
5215 }
5216 
5218 {
5219  Field_Mod32(&GPT12E->T5CON.reg, (uint8)0u, 1u, 1u);
5220 }
5221 
5223 {
5224  Field_Mod32(&GPT12E->T5CON.reg, (uint8)0u, 1u, 0u);
5225 }
5226 
5228 {
5229  Field_Mod32(&GPT12E->T5CON.reg, (uint8)1u, 2u, 1u);
5230 }
5231 
5233 {
5234  Field_Mod32(&GPT12E->T5CON.reg, (uint8)1u, 2u, 0u);
5235 }
5236 
5238 {
5240 }
5241 
5243 {
5245 }
5246 
5248 {
5250 }
5251 
5253 {
5254  Field_Mod32(&GPT12E->T5CON.reg, (uint8)12u, ((uint32)1u << 12u), 1u);
5255 }
5256 
5258 {
5259  Field_Mod32(&GPT12E->T5CON.reg, (uint8)12u, ((uint32)1u << 12u), 0u);
5260 }
5261 
5263 {
5264  Field_Mod32(&GPT12E->T5CON.reg, (uint8)13u, ((uint32)1u << 13u), 1u);
5265 }
5266 
5268 {
5269  Field_Mod32(&GPT12E->T5CON.reg, (uint8)13u, ((uint32)1u << 13u), 0u);
5270 }
5271 
5273 {
5275 }
5276 
5278 {
5279  Field_Mod32(&GPT12E->T5CON.reg, (uint8)12u, ((uint32)1u << 12u), 1u);
5280 }
5281 
5283 {
5284  Field_Mod32(&GPT12E->T5CON.reg, (uint8)12u, ((uint32)1u << 12u), 0u);
5285 }
5286 
5288 {
5289  Field_Mod32(&GPT12E->T5CON.reg, (uint8)13u, ((uint32)1u << 13u), 1u);
5290 }
5291 
5293 {
5294  Field_Mod32(&GPT12E->T5CON.reg, (uint8)13u, ((uint32)1u << 13u), 0u);
5295 }
5296 
5298 {
5300 }
5301 
5303 {
5305 }
5306 
5308 {
5310 }
5311 
5313 {
5315 }
5316 
5318 {
5320 }
5321 
5323 {
5325 }
5326 
5328 {
5330 }
5331 
5333 {
5335 }
5336 
5338 {
5340 }
5341 
5343 {
5345 }
5346 
5348 {
5350 }
5351 
5353 {
5355 }
5356 
5358 {
5360 }
5361 
5363 {
5365 }
5366 
5368 {
5370 }
5371 
5373 {
5375 }
5376 
5378 {
5380 }
5381 
5383 {
5385 }
5386 
5388 {
5390 }
5391 
5393 {
5395 }
5396 
5398 {
5400 }
5401 
5403 {
5404  Field_Mod32(&GPT12E->T6CON.reg, (uint8)2u, 4u, 0u);
5405 }
5406 
5408 {
5409  Field_Mod32(&GPT12E->T6CON.reg, (uint8)0u, 1u, 1u);
5410 }
5411 
5413 {
5414  Field_Mod32(&GPT12E->T6CON.reg, (uint8)1u, 2u, 1u);
5415 }
5416 
5418 {
5419  Field_Mod32(&GPT12E->T6CON.reg, (uint8)0u, 3u, 3u);
5420 }
5421 
5423 {
5425 }
5426 
5428 {
5430 }
5431 
5433 {
5435 }
5436 
5438 {
5440 }
5441 
5443 {
5445 }
5446 
5448 {
5450 }
5451 
5453 {
5455 }
5456 
5458 {
5460 }
5461 
5463 {
5465 }
5466 
5468 {
5470 }
5471 
5473 {
5475 }
5476 
5478 {
5480 }
5481 
5483 {
5485 }
5486 
5488 {
5490 }
5491 
5493 {
5495 }
5496 
5498 {
5500 }
5501 
5503 {
5505 }
5506 
5508 {
5510 }
5511 
5513 {
5515 }
5516 
5518 {
5520 }
5521 
5523 {
5525 }
5526 
5528 {
5530 }
5531 
5533 {
5535 }
5536 
5538 {
5540 }
5541 
5543 {
5545 }
5546 
5548 {
5550 }
5551 
5553 {
5555 }
5556 
5558 {
5560 }
5561 
5563 {
5565 }
5566 
5568 {
5570 }
5571 
5573 {
5575 }
5576 
5578 {
5580 }
5581 
5583 {
5585 }
5586 
5588 {
5590 }
5591 
5593 {
5595 }
5596 
5598 {
5600 }
5601 
5603 {
5605 }
5606 
5608 {
5610 }
5611 
5613 {
5615 }
5616 
5618 {
5620 }
5621 
5623 {
5625 }
5626 
5628 {
5630 }
5631 
5633 {
5635 }
5636 
5638 {
5640 }
5641 
5642 #endif
INLINE void GPT12E_T3_Int_Clr(void)
Clears GPT Module 1 Timer 3 interrupt flag.
Definition: gpt12e.h:5557
TGPT12E_T5IN
This enum lists the GPT12E T5INx Inputs.
Definition: gpt12e.h:181
@ GPT12E_T5INA_P05
Definition: gpt12e.h:182
@ GPT12E_T5INB_P11
Definition: gpt12e.h:183
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_En(void)
Enables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:4467
INLINE void GPT12E_T2_Mode_Gated_Timer_Clk_Prescaler_Sel(uint8 t2i)
Selects T2 Gated Timer Mode Parameter.
Definition: gpt12e.h:4422
INLINE void GPT12E_T4_Mode_Counter_Input_T4In_Sel(void)
Selects T4In as T4 Counter Mode Input.
Definition: gpt12e.h:4897
INLINE void GPT12E_T6_Mode_Timer_Sel(void)
Selects T6 Timer Mode.
Definition: gpt12e.h:5372
INLINE void GPT12E_T2_Mode_IncEnc_Input_Sel(void)
Selects T2 Incremental Interface Mode Input.
Definition: gpt12e.h:4552
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_Dis(void)
Disables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:4547
INLINE void GPT12E_T4_T4EUD_Sel(TGPT12E_T4EUD ist4eud)
Selects Input for T4EUD.
Definition: gpt12e.h:5147
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_Dis(void)
Disables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:4462
INLINE void GPT12E_T2_Int_En(void)
Enables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:5582
INLINE void GPT12E_T4_Mode_IncEnc_DownCount_RotDir_Sel(void)
Selects Timer T4 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:5082
void GPT12E_Init(void)
Initializes the GPT12E module.
INLINE void GPT12E_T4_T4In_Sel(TGPT12E_T4IN ist4in)
Selects Input for T4IN.
Definition: gpt12e.h:5142
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_En(void)
Enables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:4952
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_Dis(void)
Disables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:4512
INLINE void GPT12E_T4_Mode_IncEnc_Rot_Sel(void)
Selects T4 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:4877
INLINE void GPT12E_T4_Mode_Counter_Input_T3Out_Sel(void)
Selects T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:4922
INLINE void GPT12E_T2_DownCount_Sel(void)
Selects Timer T2 counts down.
Definition: gpt12e.h:4597
INLINE void GPT12E_T4_Mode_Capture_Sel(void)
Selects T4 Capture Mode.
Definition: gpt12e.h:4872
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_Dis(void)
Disables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:4487
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_En(void)
Enables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:4532
INLINE void GPT12E_T5_Capture_En(void)
Enables T5 Capture Mode.
Definition: gpt12e.h:5237
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_En(void)
Enables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:5032
INLINE void GPT12E_T2_Mode_Timer_Sel(void)
Selects T2 Timer Mode.
Definition: gpt12e.h:4377
INLINE uint8 GPT12E_T2_Int_Sts(void)
Reads GPT Module 1 Timer 2 interrupt Status.
Definition: gpt12e.h:5522
INLINE void GPT12E_T5_Capture_Trig_T3In_T3EUD_Sel(void)
Selects T3In and/or T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:5272
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T3Out_En(void)
Enables Falling Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:4542
INLINE uint8 GPT12E_T6_Int_Sts(void)
Reads GPT Module 2 Timer 6 interrupt Status.
Definition: gpt12e.h:5542
INLINE void GPT12E_T4_Clr_T2_En(void)
Enables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:5092
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_En(void)
Enables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:4987
INLINE void GPT12E_T6_Output_Set(void)
Sets Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:5467
INLINE void GPT12E_T6_Start(void)
Starts Timer T6.
Definition: gpt12e.h:5447
INLINE void GPT12E_T2_Mode_Gated_Timer_High_Sel(void)
Selects T2 Gated high Mode.
Definition: gpt12e.h:4392
INLINE uint8 GPT12E_T2_Mode_IncEnc_Dir_Change_Sts(void)
Reads Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:4637
TGPT12E_T4EUD
This enum lists the GPT12E T4EUDx Inputs.
Definition: gpt12e.h:159
@ GPT12E_T4EUDC_P27
Definition: gpt12e.h:162
@ GPT12E_T4EUDA_P03
Definition: gpt12e.h:160
@ GPT12E_T4EUDB_P10
Definition: gpt12e.h:161
@ GPT12E_T4EUDD_P21
Definition: gpt12e.h:163
INLINE uint8 GPT12E_T3_Int_Sts(void)
Reads GPT Module 1 Timer 3 interrupt Status.
Definition: gpt12e.h:5527
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_Dis(void)
Disables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:5222
INLINE void GPT12E_T6_Reload_Value_Set(uint16 rl)
Sets Current T6 Reload Value.
Definition: gpt12e.h:5432
TGPT12E_T3EUD
This enum lists the GPT12E T3EUDx Inputs.
Definition: gpt12e.h:137
@ GPT12E_T3EUDD_P03
Definition: gpt12e.h:141
@ GPT12E_T3EUDA_P04
Definition: gpt12e.h:138
@ GPT12E_T3EUDC_P11
Definition: gpt12e.h:140
@ GPT12E_T3EUDB_P27
Definition: gpt12e.h:139
INLINE void GPT12E_T3_UpCount_Sel(void)
Selects Timer T3 counts up.
Definition: gpt12e.h:4782
INLINE void GPT12E_T3_Output_Rst(void)
Clears Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:4772
INLINE void GPT12E_T4_Mode_Timer_Sel(void)
Selects T4 Timer Mode.
Definition: gpt12e.h:4847
INLINE void GPT12E_T4_Clr_T3_En(void)
Enables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:5102
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_En(void)
Enables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:5252
INLINE void GPT12E_CapRel_Int_Clr(void)
Clears GPT Module 1 Capture Reload interrupt flag.
Definition: gpt12e.h:5577
INLINE uint16 GPT12E_T5_Capture_Value_Get(void)
Reads Current T5 Capture Value.
Definition: gpt12e.h:5307
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_Dis(void)
Disables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:4932
INLINE void GPT12E_T6_Stop(void)
Stops Timer T6.
Definition: gpt12e.h:5452
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Sel(void)
Selects T4 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:4882
INLINE void GPT12E_T2_Mode_IncEnc_Rot_Sel(void)
Selects T2 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:4407
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_Dis(void)
Disables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:4982
INLINE void GPT12E_T4_Mode_Gated_Timer_High_Sel(void)
Selects T4 Gated high Mode.
Definition: gpt12e.h:4862
INLINE void GPT12E_T4_Start(void)
Starts Timer T4.
Definition: gpt12e.h:5042
TGPT2_Clk_Prescaler
This enum lists the GPT2 Timer Prescaler.
Definition: gpt12e.h:170
@ GPT2_fSYS_Div_16
Definition: gpt12e.h:174
@ GPT2_fSYS_Div_2
Definition: gpt12e.h:171
@ GPT2_fSYS_Div_4
Definition: gpt12e.h:172
@ GPT2_fSYS_Div_8
Definition: gpt12e.h:173
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_Dis(void)
Disables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:5292
TGPT12E_Mode_Timer_Prescaler
This enum lists the GPT12E Timer Prescaler.
Definition: gpt12e.h:228
@ GPT_Clk_Div_2
Definition: gpt12e.h:230
@ GPT_Clk_Div_16
Definition: gpt12e.h:233
@ GPT_Clk_Div_64
Definition: gpt12e.h:235
@ GPT_Clk_Div_8
Definition: gpt12e.h:232
@ GPT_Clk_Div_32
Definition: gpt12e.h:234
@ GPT_Clk_Div_1
Definition: gpt12e.h:229
@ GPT_Clk_Div_128
Definition: gpt12e.h:236
@ GPT_Clk_Div_4
Definition: gpt12e.h:231
INLINE void GPT12E_T6_T6In_Sel(TGPT12E_T6IN ist6in)
Selects Input for T6IN.
Definition: gpt12e.h:5507
INLINE void GPT12E_T6_Mode_Gated_Timer_High_Sel(void)
Selects T6 Gated high Mode.
Definition: gpt12e.h:5387
INLINE void GPT12E_T4_Stop(void)
Stops Timer T4.
Definition: gpt12e.h:5047
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Detect_Clr(void)
Clears Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:4632
INLINE void GPT12E_T2_Mode_Reload_Sel(void)
Selects T2 Reload Mode.
Definition: gpt12e.h:4397
INLINE void GPT12E_T6_On_Capture_Cleared_En(void)
Enables clearing T6 on a Capture Event.
Definition: gpt12e.h:5437
INLINE void GPT12E_T3_Mode_Timer_Sel(void)
Selects T3 Timer Mode.
Definition: gpt12e.h:4667
INLINE void GPT12E_T4_Mode_Reload_Input_T4In_Sel(void)
Selects T4In as T4 Reload Mode Input.
Definition: gpt12e.h:4972
INLINE void GPT12E_T5_Int_Dis(void)
Disables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:5617
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_En(void)
Enables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:4442
INLINE void GPT12E_T6_Mode_Counter_Input_Rising_T6In_Sel(void)
Selects Rising Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:5407
INLINE void GPT12E_T2_Value_Set(uint16 t2)
Sets Timer T2 Value.
Definition: gpt12e.h:4652
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_Dis(void)
Disables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:4732
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_Dis(void)
Disables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:5282
INLINE void GPT12E_T3_Mode_IncEnc_Dir_Change_Clr(void)
Clears Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:4822
INLINE void GPT12E_T4_Mode_Counter_Sel(void)
Selects T4 Counter Mode.
Definition: gpt12e.h:4852
INLINE void GPT12E_T3_T4_CCU6_Sel(TGPT12E_CCU6_SEL gpt)
Selects GPT12 TIN3B/TIN4D Input.
Definition: gpt12e.h:4372
INLINE void GPT12E_T5_T5EUD_Sel(TGPT12E_T5EUD ist5eud)
Selects Input for T5EUD.
Definition: gpt12e.h:5367
INLINE void GPT12E_T3_Int_En(void)
Enables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:5592
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_En(void)
Enables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:4902
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_En(void)
Enables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:4937
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_Dis(void)
Disables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:4917
INLINE uint8 GPT12E_T5_Int_Sts(void)
Reads GPT Module 2 Timer 5 interrupt Status.
Definition: gpt12e.h:5537
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_En(void)
Enables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:5002
INLINE void GPT12E_T3_UpDownCount_Ext_Dis(void)
Disables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:4792
INLINE void GPT12E_T3_Output_Set(void)
Sets Timer T3 Overflow Toggle Latch.
Definition: gpt12e.h:4767
INLINE void GPT12E_T6_UpCount_Sel(void)
Selects Timer T6 counts up.
Definition: gpt12e.h:5482
INLINE void GPT12E_T6_Reload_En(void)
Enables T6 Reload Mode.
Definition: gpt12e.h:5422
TGPT12E_T2EUD
This enum lists the GPT12E T2EUDx Inputs.
Definition: gpt12e.h:117
@ GPT12E_T2EUDA_P02
Definition: gpt12e.h:118
@ GPT12E_T2EUDB_P23
Definition: gpt12e.h:119
INLINE void GPT12E_T4_Start_by_T3_Dis(void)
Disables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:5057
TGPT12E_CCU6_SEL
This enum lists the GPT12E CCU6 Selection.
Definition: gpt12e.h:89
@ GPT12E_CCU6_T12_CM_CH1
Definition: gpt12e.h:96
@ GPT12E_CCU6_T13_PM
Definition: gpt12e.h:98
@ GPT12E_CCU6_T13_CM
Definition: gpt12e.h:100
@ GPT12E_CCU6_T13_ZM
Definition: gpt12e.h:99
@ GPT12E_CCU6_CH1
Definition: gpt12e.h:91
@ GPT12E_CCU6_ANY_CHx
Definition: gpt12e.h:101
@ GPT12E_CCU6_T12_CM_CH0
Definition: gpt12e.h:95
@ GPT12E_CCU6_CH0
Definition: gpt12e.h:90
@ GPT12E_CCU6_CH2
Definition: gpt12e.h:92
@ GPT12E_CCU6_T12_ZM
Definition: gpt12e.h:93
@ GPT12E_CCU6_T12_PM
Definition: gpt12e.h:94
@ GPT12E_CCU6_T12_CM_CH2
Definition: gpt12e.h:97
INLINE void GPT12E_T2_Start_by_T3_Dis(void)
Disables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:4592
INLINE void GPT12E_T3_Mode_Gated_Timer_Clk_Prescaler_Sel(uint8 t3i)
Selects T3 Gated Timer Mode Parameter.
Definition: gpt12e.h:4702
bool GPT12E_T6_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T6 to be reloaded by CAPREL.
INLINE void GPT12E_T6_UpDownCount_Ext_En(void)
Enables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:5487
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_En(void)
Enables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:4517
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T4In_En(void)
Enables Falling Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:4912
INLINE uint16 GPT12E_T4_Value_Get(void)
Reads Timer T4 Value.
Definition: gpt12e.h:5132
INLINE void GPT12E_T6_Int_Dis(void)
Disables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5627
INLINE void GPT12E_T2_Mode_Capture_Input_T2In_Sel(void)
Selects T2In as T2 Capture Mode Input.
Definition: gpt12e.h:4477
INLINE void GPT12E_T2_UpDownCount_Ext_Dis(void)
Disables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:4612
INLINE void GPT12E_T2_Mode_Gated_Timer_Low_Sel(void)
Selects T2 Gated low Mode.
Definition: gpt12e.h:4387
INLINE uint8 GPT12E_T3_Mode_IncEnc_Dir_Change_Sts(void)
Reads Timer T3 Incremental Interface Direction Change.
Definition: gpt12e.h:4817
INLINE void GPT12E_T3_Mode_IncEnc_DownCount_RotDir_Sel(void)
Selects Timer T3 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:4797
INLINE void GPT12E_T3_Value_Set(uint16 t3)
Sets Timer T3 Value.
Definition: gpt12e.h:4832
INLINE void GPT12E_T3_DownCount_Sel(void)
Selects Timer T3 counts down.
Definition: gpt12e.h:4777
INLINE void GPT12E_T4_DownCount_Sel(void)
Selects Timer T4 counts down.
Definition: gpt12e.h:5062
INLINE void GPT12E_T2_Stop(void)
Stops Timer T2.
Definition: gpt12e.h:4582
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_En(void)
Enables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:4707
INLINE void GPT12E_T6_Int_En(void)
Enables GPT Module 2 Timer 6 interrupt.
Definition: gpt12e.h:5622
INLINE void GPT12E_T5_Mode_Counter_Sel(void)
Selects T5 Counter Mode.
Definition: gpt12e.h:5167
INLINE void GPT12E_T6_Mode_Counter_Input_T6In_Sel(void)
Selects T6In as T6 Counter Mode Input.
Definition: gpt12e.h:5402
INLINE void GPT12E_T5_Mode_Gated_Timer_High_Sel(void)
Selects T5 Gated high Mode.
Definition: gpt12e.h:5177
INLINE void GPT12E_T4_Int_Clr(void)
Clears GPT Module 1 Timer 4 interrupt flag.
Definition: gpt12e.h:5562
INLINE void GPT12E_T3_Mode_Gated_Timer_Low_Sel(void)
Selects T3 Gated low Mode.
Definition: gpt12e.h:4677
TGPT12E_T2IN
This enum lists the GPT12E T2INx Inputs.
Definition: gpt12e.h:108
@ GPT12E_T2INA_P12
Definition: gpt12e.h:109
@ GPT12E_T2INB_P14
Definition: gpt12e.h:110
INLINE void GPT12E_T5_Capture_Dis(void)
Disables T5 Capture Mode.
Definition: gpt12e.h:5242
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_En(void)
Enables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:4717
INLINE void GPT12E_T3_Output_En(void)
Enables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:4757
INLINE void GPT12E_T2_Mode_IncEnc_DownCount_RotDir_Sel(void)
Selects Timer T2 Incremental Interface Rotation Detection Mode counts down.
Definition: gpt12e.h:4617
INLINE uint16 GPT12E_T6_Value_Get(void)
Reads Timer T6 Value.
Definition: gpt12e.h:5497
INLINE void GPT12E_T2_Int_Clr(void)
Clears GPT Module 1 Timer 2 interrupt flag.
Definition: gpt12e.h:5552
INLINE void GPT12E_T3_T3EUD_Sel(TGPT12E_T3EUD ist3eud)
Selects Input for T3EUD.
Definition: gpt12e.h:4842
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T6Out_En(void)
Enables Rising Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:5217
INLINE void GPT12E_T6_Mode_Counter_Input_Any_T6In_Sel(void)
Selects Any Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:5417
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_Dis(void)
Disables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:5232
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_En(void)
Enables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:5012
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_En(void)
Enables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:4492
bool GPT12E_T3_Interval_Timer_Setup(uint32 timer_interval_us)
Initializes the T3 to be reloaded by T2.
INLINE void GPT12E_T5_Cleared_On_Capture_Dis(void)
Disables clearing T5 on a Capture Event.
Definition: gpt12e.h:5302
INLINE void GPT12E_T3_Mode_Gated_Timer_High_Sel(void)
Selects T3 Gated high Mode.
Definition: gpt12e.h:4682
INLINE void GPT12E_T5_Mode_Counter_Input_T5In_Sel(void)
Selects T5In as T5 Counter Mode Input.
Definition: gpt12e.h:5192
INLINE void GPT12E_GPT2_Clk_Prescaler_Sel(TGPT2_Clk_Prescaler bps2)
Selects GPT2 Block Prescaler.
Definition: gpt12e.h:5152
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_En(void)
Enables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:4737
INLINE void GPT12E_T5_UpDownCount_Ext_Dis(void)
Disables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:5347
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T4In_En(void)
Enables Rising Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:4977
INLINE uint8 GPT12E_GPT1_Clk_Prescaler_Get(void)
Reads GPT1 Clock Prescaler.
Definition: gpt12e.h:4367
INLINE void GPT12E_T6_Output_En(void)
Enables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:5457
INLINE void GPT12E_T4_UpDownCount_Ext_En(void)
Enables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:5072
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_En(void)
Enables Rising or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:4567
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_Dis(void)
Disables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:4437
INLINE void GPT12E_T3_Mode_Counter_Input_Rising_T3In_Dis(void)
Disables Rising Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:4712
INLINE void GPT12E_T6_Mode_Timer_Clk_Prescaler_Sel(uint8 t6i)
Selects T6 Timer Mode Parameter.
Definition: gpt12e.h:5392
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T2In_Dis(void)
Disables Falling Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:4447
INLINE void GPT12E_T5_Mode_Counter_Input_Any_T5In_Sel(void)
Selects Any Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:5207
INLINE void GPT12E_T4_Mode_Counter_Input_Falling_T3Out_Dis(void)
Disables Falling Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:4942
INLINE void GPT12E_T3_Mode_IncEnc_Rot_Sel(void)
Selects T3 Incremental Interface -Rotation Detection- Mode.
Definition: gpt12e.h:4687
INLINE void GPT12E_T5_Mode_Counter_Input_Rising_T5In_Sel(void)
Selects Rising Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:5197
INLINE void GPT12E_T4_Mode_Reload_Sel(void)
Selects T4 Reload Mode.
Definition: gpt12e.h:4867
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_En(void)
Enables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:4557
INLINE void GPT12E_T5_Capture_Trig_Rising_CapIn_Dis(void)
Disables Rising Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:5257
INLINE uint8 GPT12E_CapRel_Int_Sts(void)
Reads GPT Module 1 Capture Reload interrupt Status.
Definition: gpt12e.h:5547
INLINE void GPT12E_T2_T2In_Sel(TGPT12E_T2IN ist2in)
Selects Input for T2IN.
Definition: gpt12e.h:4657
INLINE void GPT12E_GPT1_Clk_Prescaler_Sel(TGPT1_Clk_Prescaler bps1)
Selects GPT1 Clock Prescaler.
Definition: gpt12e.h:4362
TGPT1_Clk_Prescaler
This enum lists the GPT1 Timer Prescaler.
Definition: gpt12e.h:78
@ GPT1_fSYS_Div_32
Definition: gpt12e.h:82
@ GPT1_fSYS_Div_16
Definition: gpt12e.h:81
@ GPT1_fSYS_Div_4
Definition: gpt12e.h:79
@ GPT1_fSYS_Div_8
Definition: gpt12e.h:80
INLINE void GPT12E_T5_Stop(void)
Stops Timer T5.
Definition: gpt12e.h:5317
INLINE void GPT12E_T4_Start_by_T3_En(void)
Enables controlling Timer T4 by the run bit T3R of core timer T3.
Definition: gpt12e.h:5052
INLINE void GPT12E_T6_On_Capture_Cleared_Dis(void)
Disables clearing T6 on a Capture Event.
Definition: gpt12e.h:5442
INLINE void GPT12E_T5_Int_En(void)
Enables GPT Module 2 Timer 5 interrupt.
Definition: gpt12e.h:5612
INLINE uint16 GPT12E_T5_Value_Get(void)
Reads Timer T5 Value.
Definition: gpt12e.h:5352
TGPT12E_T6IN
This enum lists the GPT12E T6INx Inputs.
Definition: gpt12e.h:199
@ GPT12E_T6INA_CC61
Definition: gpt12e.h:200
@ GPT12E_T6INB_COUT61
Definition: gpt12e.h:201
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T2In_En(void)
Enables Rising Edge on T2In as T2 Counter Mode Input.
Definition: gpt12e.h:4432
INLINE void GPT12E_T6_Int_Clr(void)
Clears GPT Module 2 Timer 6 interrupt flag.
Definition: gpt12e.h:5572
INLINE void GPT12E_T5_Start_by_T6_En(void)
Enables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:5327
INLINE void GPT12E_T4_Value_Set(uint16 t4)
Sets Timer T4 Value.
Definition: gpt12e.h:5137
INLINE void GPT12E_T6_Output_Rst(void)
Clears Timer T6 Overflow Toggle Latch.
Definition: gpt12e.h:5472
INLINE void GPT12E_T5_Capture_Trig_Any_T3In_En(void)
Enables Any Edge on T3In as T5 Capture Mode Input.
Definition: gpt12e.h:5277
INLINE void GPT12E_T5_Start_by_T6_Dis(void)
Disables controlling Timer T5 by the run bit T6R of core timer T6.
Definition: gpt12e.h:5322
INLINE void GPT12E_T4_Mode_Capture_Input_T4In_Sel(void)
Selects T4In as T4 Capture Mode Input.
Definition: gpt12e.h:4947
INLINE void GPT12E_T2_UpCount_Sel(void)
Selects Timer T2 counts up.
Definition: gpt12e.h:4602
INLINE void GPT12E_T4_Int_En(void)
Enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:5602
INLINE uint16 GPT12E_T2_Value_Get(void)
Reads Timer T2 Value.
Definition: gpt12e.h:4647
INLINE void GPT12E_T2_Mode_Capture_Input_Falling_T2In_Dis(void)
Disables Falling Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:4497
INLINE void GPT12E_T5_UpDownCount_Ext_En(void)
Enables controlling Count direction by external input (T5EUD).
Definition: gpt12e.h:5342
INLINE void GPT12E_T4_Mode_Gated_Timer_Low_Sel(void)
Selects T4 Gated low Mode.
Definition: gpt12e.h:4857
INLINE void GPT12E_T5_Mode_Gated_Timer_Low_Sel(void)
Selects T5 Gated low Mode.
Definition: gpt12e.h:5172
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T3Out_Dis(void)
Disables Rising Edge on T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:4537
INLINE void GPT12E_T4_Mode_Reload_Input_T3Out_Sel(void)
Selects T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:4997
INLINE void GPT12E_CapRel_Int_Dis(void)
Disables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5637
INLINE void GPT12E_T2_Mode_IncEnc_UpCount_RotDir_Sel(void)
Selects Timer T2 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:4622
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_Dis(void)
Disables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:5027
INLINE void GPT12E_T6_Mode_Gated_Timer_Low_Sel(void)
Selects T6 Gated low Mode.
Definition: gpt12e.h:5382
INLINE void GPT12E_T2_Mode_Reload_Input_Falling_T2In_Dis(void)
Disables Falling Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:4522
INLINE void GPT12E_T5_Int_Clr(void)
Clears GPT Module 2 Timer 5 interrupt flag.
Definition: gpt12e.h:5567
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3EUD_Dis(void)
Disables Falling or Falling Edge on T3EUD as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:5037
INLINE void GPT12E_T2_Start_by_T3_En(void)
Enables controlling Timer T2 by the run bit T3R of core timer T3.
Definition: gpt12e.h:4587
INLINE void GPT12E_T6_Mode_Gated_Timer_Clk_Prescaler_Sel(uint8 t6i)
Selects T6 Gated Timer Mode Parameter.
Definition: gpt12e.h:5397
TGPT12E_CAPIN
This enum lists the GPT12E CAPINx Inputs.
Definition: gpt12e.h:217
@ GPT12E_CAPIND_T2_T3_T4_READ
Definition: gpt12e.h:221
@ GPT12E_CAPINA_P01
Definition: gpt12e.h:218
@ GPT12E_CAPINC_T3_READ
Definition: gpt12e.h:220
@ GPT12E_CAPINB_P03
Definition: gpt12e.h:219
INLINE void GPT12E_T2_T2EUD_Sel(TGPT12E_T2EUD ist2eud)
Selects Input for T2EUD.
Definition: gpt12e.h:4662
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_En(void)
Enables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:4962
INLINE void GPT12E_T6_UpDownCount_Ext_Dis(void)
Disables controlling Count direction by external input (T6EUD).
Definition: gpt12e.h:5492
TGPT12E_T4IN
This enum lists the GPT12E T4INx Inputs.
Definition: gpt12e.h:148
@ GPT12E_T4INB_CCU6_CH0
Definition: gpt12e.h:150
@ GPT12E_T4IND_CCU6_SEL
Definition: gpt12e.h:152
@ GPT12E_T4INC_P01
Definition: gpt12e.h:151
@ GPT12E_T4INA_P00
Definition: gpt12e.h:149
INLINE void GPT12E_T2_Mode_Reload_Input_T3Out_Sel(void)
Selects T3OTL as T2 Reload Mode Input.
Definition: gpt12e.h:4527
INLINE void GPT12E_T6_Reload_Dis(void)
Disables T6 Reload Mode.
Definition: gpt12e.h:5427
INLINE void GPT12E_T2_Mode_Capture_Input_Rising_T2In_En(void)
Enables Rising Edge on T2In as T2 Capture Mode Input.
Definition: gpt12e.h:4482
INLINE void GPT12E_T2_Mode_Counter_Input_Falling_T3Out_Dis(void)
Disables Falling Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:4472
INLINE void GPT12E_T6_Mode_Counter_Input_Falling_T6In_Sel(void)
Selects Falling Edge on T6In as T6 Counter Mode Input.
Definition: gpt12e.h:5412
INLINE void GPT12E_T6_Mode_Counter_Sel(void)
Selects T6 Counter Mode.
Definition: gpt12e.h:5377
INLINE void GPT12E_T4_Clr_T3_Dis(void)
Disables the automatic clearing of timer T3 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:5107
INLINE void GPT12E_T4_UpDownCount_Ext_Dis(void)
Disables controlling Count direction by external input (T4EUD).
Definition: gpt12e.h:5077
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T5In_Sel(void)
Selects Falling Edge on T5In as T5 Counter Mode Input.
Definition: gpt12e.h:5202
INLINE void GPT12E_T2_Mode_Reload_Input_T2In_Sel(void)
Selects T2In as T2 Reload Mode Input.
Definition: gpt12e.h:4502
INLINE void GPT12E_T5_Mode_Timer_Sel(void)
Selects T5 Timer Mode.
Definition: gpt12e.h:5162
INLINE void GPT12E_T5_Mode_Counter_Input_T6Out_Sel(void)
Selects T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:5212
INLINE void GPT12E_T2_Mode_Counter_Sel(void)
Selects T2 Counter Mode.
Definition: gpt12e.h:4382
INLINE void GPT12E_T2_Mode_Timer_Clk_Prescaler_Sel(uint8 t2i)
Selects T2 Timer Mode Parameter.
Definition: gpt12e.h:4417
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_Dis(void)
Disables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:5267
INLINE void GPT12E_T5_T5In_Sel(TGPT12E_T5IN ist5in)
Selects Input for T2IN.
Definition: gpt12e.h:5362
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T3Out_En(void)
Enables Rising Edge on T3OTL as T4 Counter Mode Input.
Definition: gpt12e.h:4927
INLINE void GPT12E_T2_UpDownCount_Ext_En(void)
Enables controlling Count direction by external input (T2EUD).
Definition: gpt12e.h:4607
INLINE void GPT12E_T4_Mode_Capture_Input_Falling_T4In_Dis(void)
Disables Falling Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:4967
INLINE void GPT12E_CapRel_CAPIn_Sel(TGPT12E_CAPIN iscapin)
Selects CAPIN.
Definition: gpt12e.h:5517
INLINE void GPT12E_T6_T6EUD_Sel(TGPT12E_T6EUD ist6eud)
Selects Input for T6EUD.
Definition: gpt12e.h:5512
INLINE void GPT12E_T3_Int_Dis(void)
Disables GPT Module 1 Timer 3 interrupt.
Definition: gpt12e.h:5597
INLINE void GPT12E_T4_Mode_IncEnc_Dir_Change_Clr(void)
Clears Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:5127
INLINE uint16 GPT12E_T3_Value_Get(void)
Reads Timer T3 Value.
Definition: gpt12e.h:4827
INLINE void GPT12E_T4_Int_Dis(void)
Enables GPT Module 1 Timer 4 interrupt.
Definition: gpt12e.h:5607
INLINE void GPT12E_T5_Start(void)
Starts Timer T5.
Definition: gpt12e.h:5312
INLINE void GPT12E_T5_Mode_Timer_Clk_Prescaler_Sel(uint8 t5i)
Selects T5 Timer Mode Parameter.
Definition: gpt12e.h:5182
INLINE void GPT12E_T4_Mode_IncEnc_Any_T3In_En(void)
Enables Rising or Falling Edge on T3In as T4 Incremental Interface Mode Input.
Definition: gpt12e.h:5022
INLINE uint8 GPT12E_T3_Mode_IncEnc_Edge_Detect_Sts(void)
Reads Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:4807
INLINE void GPT12E_T5_Mode_Counter_Input_Falling_T6Out_En(void)
Enables Falling Edge on T6OTL as T5 Counter Mode Input.
Definition: gpt12e.h:5227
INLINE void GPT12E_T5_DownCount_Sel(void)
Selects Timer T5 counts down.
Definition: gpt12e.h:5332
INLINE void GPT12E_T5_Value_Set(uint16 t5)
Sets Timer T5 Value.
Definition: gpt12e.h:5357
INLINE void GPT12E_T5_Cleared_On_Capture_En(void)
Enables clearing T5 on a Capture Event.
Definition: gpt12e.h:5297
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Detect_Clr(void)
Clears Timer T3 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:4812
INLINE void GPT12E_T3_Mode_IncEnc_UpCount_RotDir_Sel(void)
Selects Timer T3 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:4802
INLINE void GPT12E_T6_Value_Set(uint16 t6)
Sets Timer T6 Value.
Definition: gpt12e.h:5502
INLINE void GPT12E_T2_Mode_IncEnc_Dir_Change_Clr(void)
Clears Timer T2 Incremental Interface Direction Change.
Definition: gpt12e.h:4642
INLINE void GPT12E_CapRel_Int_En(void)
Enables GPT Module 1 Capture Reload interrupt.
Definition: gpt12e.h:5632
INLINE void GPT12E_T4_Mode_Counter_Input_Rising_T4In_Dis(void)
Disables Rising Edge on T4In as T4 Counter Mode Input.
Definition: gpt12e.h:4907
INLINE void GPT12E_T2_Mode_Capture_Sel(void)
Selects T2 Capture Mode.
Definition: gpt12e.h:4402
INLINE void GPT12E_T4_Mode_IncEnc_Edge_Detect_Clr(void)
Clears Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:5117
INLINE void GPT12E_T3_Mode_Counter_Sel(void)
Selects T3 Counter Mode.
Definition: gpt12e.h:4672
INLINE void GPT12E_T2_Start(void)
Starts Timer T2.
Definition: gpt12e.h:4577
INLINE void GPT12E_T4_Mode_IncEnc_UpCount_RotDir_Sel(void)
Selects Timer T4 Incremental Interface Rotation Detection Mode counts up.
Definition: gpt12e.h:5087
INLINE void GPT12E_T2_Int_Dis(void)
Disables GPT Module 1 Timer 2 interrupt.
Definition: gpt12e.h:5587
TGPT12E_T6EUD
This enum lists the GPT12E T6EUDx Inputs.
Definition: gpt12e.h:208
@ GPT12E_T6EUDB_P22
Definition: gpt12e.h:210
@ GPT12E_T6EUDA_P11
Definition: gpt12e.h:209
INLINE void GPT12E_T2_Mode_Counter_Input_T3Out_Sel(void)
Selects T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:4452
INLINE uint8 GPT12E_T2_Mode_IncEnc_Edge_Detect_Sts(void)
Reads Timer T2 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:4627
INLINE void GPT12E_T3_T3In_Sel(TGPT12E_T3IN ist3in)
Selects Input for T3IN.
Definition: gpt12e.h:4837
INLINE void GPT12E_T2_Mode_Counter_Input_Rising_T3Out_En(void)
Enables Rising Edge on T3OTL as T2 Counter Mode Input.
Definition: gpt12e.h:4457
INLINE void GPT12E_T4_Mode_Timer_Clk_Prescaler_Sel(uint8 t4i)
Selects T4 Timer Mode Parameter.
Definition: gpt12e.h:4887
INLINE void GPT12E_T2_Mode_Reload_Input_Rising_T2In_En(void)
Enables Rising Edge on T2In as T2 Reload Mode Input.
Definition: gpt12e.h:4507
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3In_Dis(void)
Disables Rising or Falling Edge on T3In as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:4562
INLINE uint8 GPT12E_T4_Mode_IncEnc_Edge_Detect_Sts(void)
Reads Timer T4 Incremental Interface Edge Detection Counting.
Definition: gpt12e.h:5112
INLINE void GPT12E_T6_Output_Dis(void)
Disables Timer T6 Overflow/Underflow Output.
Definition: gpt12e.h:5462
INLINE void GPT12E_T4_Mode_Capture_Input_Rising_T4In_Dis(void)
Disables Rising Edge on T4In as T4 Capture Mode Input.
Definition: gpt12e.h:4957
INLINE void GPT12E_T5_Capture_Trig_Any_T3EUD_En(void)
Enables Any Edge on T3EUD as T5 Capture Mode Input.
Definition: gpt12e.h:5287
TGPT12E_T5EUD
This enum lists the GPT12E T5EUDx Inputs.
Definition: gpt12e.h:190
@ GPT12E_T5EUDA_P14
Definition: gpt12e.h:191
@ GPT12E_T5EUDB_P20
Definition: gpt12e.h:192
INLINE void GPT12E_T4_Mode_Gated_Timer_Clk_Prescaler_Sel(uint8 t4i)
Selects T4 Gated Timer Mode Parameter.
Definition: gpt12e.h:4892
INLINE uint8 GPT12E_T4_Mode_IncEnc_Dir_Change_Sts(void)
Reads Timer T4 Incremental Interface Direction Change.
Definition: gpt12e.h:5122
INLINE void GPT12E_T3_Output_Dis(void)
Disables Timer T3 Overflow/Underflow Output.
Definition: gpt12e.h:4762
INLINE void GPT12E_T5_Capture_Trig_Falling_CapIn_En(void)
Enables Falling Edge on CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:5262
INLINE void GPT12E_T2_Mode_IncEnc_Any_T3EUD_Dis(void)
Disables Rising or Falling Edge on T3EUD as T2 Incremental Interface Mode Input.
Definition: gpt12e.h:4572
INLINE void GPT12E_T4_Mode_Reload_Input_Rising_T3Out_Dis(void)
Disables Rising Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:5007
INLINE void GPT12E_T5_Mode_Gated_Timer_Clk_Prescaler_Sel(uint8 t5i)
Selects T5 Gated Timer Mode Parameter.
Definition: gpt12e.h:5187
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T4In_Dis(void)
Disables Falling Edge on T4In as T4 Reload Mode Input.
Definition: gpt12e.h:4992
INLINE void GPT12E_T3_UpDownCount_Ext_En(void)
Enables controlling Count direction by external input (T3EUD).
Definition: gpt12e.h:4787
INLINE void GPT12E_T4_UpCount_Sel(void)
Selects Timer T4 counts up.
Definition: gpt12e.h:5067
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3In_En(void)
Enables Rising or Falling Edge on T3In as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:4727
INLINE void GPT12E_T3_Mode_Timer_Clk_Prescaler_Sel(uint8 t3i)
Selects T3 Timer Mode Parameter.
Definition: gpt12e.h:4697
INLINE void GPT12E_T4_Clr_T2_Dis(void)
Disables the automatic clearing of timer T2 upon a falling edge of the selected T4EUD input.
Definition: gpt12e.h:5097
INLINE void GPT12E_T4_Mode_Reload_Input_Falling_T3Out_Dis(void)
Disables Falling Edge on T3OTL as T4 Reload Mode Input.
Definition: gpt12e.h:5017
INLINE void GPT12E_T3_Start(void)
Starts Timer T3.
Definition: gpt12e.h:4747
INLINE void GPT12E_T5_Capture_Trig_CapIn_Sel(void)
Selects CapIn as T5 Capture Mode Input.
Definition: gpt12e.h:5247
INLINE void GPT12E_T3_Mode_IncEnc_Any_T3EUD_Dis(void)
Disables Falling or Falling Edge on T3EUD as T3 Incremental Interface Mode Input.
Definition: gpt12e.h:4742
INLINE void GPT12E_T3_Mode_Counter_Input_Falling_T3In_Dis(void)
Disables Falling Edge on T3In as T3 Counter Mode Input.
Definition: gpt12e.h:4722
INLINE void GPT12E_T3_Stop(void)
Stops Timer T3.
Definition: gpt12e.h:4752
INLINE void GPT12E_T2_Mode_Counter_Input_T2In_Sel(void)
Selects T2In as T2 Counter Mode Input.
Definition: gpt12e.h:4427
TGPT12E_T3IN
This enum lists the GPT12E T3INx Inputs.
Definition: gpt12e.h:126
@ GPT12E_T3INC_P10
Definition: gpt12e.h:129
@ GPT12E_T3INA_CCU6_CH0
Definition: gpt12e.h:127
@ GPT12E_T3IND_P23
Definition: gpt12e.h:130
@ GPT12E_T3INB_CCU6_SEL
Definition: gpt12e.h:128
INLINE uint8 GPT12E_GPT2_Clk_Prescaler_Get(void)
Reads GPT2 Block Prescaler.
Definition: gpt12e.h:5157
INLINE void GPT12E_T6_DownCount_Sel(void)
Selects Timer T6 counts down.
Definition: gpt12e.h:5477
INLINE void GPT12E_T2_Mode_IncEnc_Edge_Sel(void)
Selects T2 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:4412
INLINE uint8 GPT12E_T4_Int_Sts(void)
Reads GPT Module 1 Timer 4 interrupt Status.
Definition: gpt12e.h:5532
INLINE void GPT12E_T3_Mode_IncEnc_Edge_Sel(void)
Selects T3 Incremental Interface -Edge Detection- Mode.
Definition: gpt12e.h:4692
INLINE void GPT12E_T5_UpCount_Sel(void)
Selects Timer T5 counts up.
Definition: gpt12e.h:5337
#define GPT12E
Definition: tle985x.h:6270
#define SCU
Definition: tle985x.h:6277
#define GPT12E_PISEL_IST5EUD_Msk
Definition: tle985x.h:8800
#define GPT12E_T6CON_T6UD_Pos
Definition: tle985x.h:8933
#define GPT12E_T6_T6_Pos
Definition: tle985x.h:8918
#define GPT12E_T6CON_T6UDE_Pos
Definition: tle985x.h:8931
#define GPT12E_PISEL_IST4IN_Msk
Definition: tle985x.h:8806
#define GPT12E_T2CON_T2EDGE_Msk
Definition: tle985x.h:8824
#define GPT12E_PISEL_IST3EUD_Pos
Definition: tle985x.h:8807
#define GPT12E_T4CON_T4CHDIR_Pos
Definition: tle985x.h:8871
#define GPT12E_T2CON_T2UD_Pos
Definition: tle985x.h:8831
#define SCU_GPT12IEN_T5IE_Msk
Definition: tle985x.h:9928
#define GPT12E_PISEL_IST4EUD_Pos
Definition: tle985x.h:8803
#define SCU_GPT12ICLR_GPT2T6C_Pos
Definition: tle985x.h:9912
#define SCU_GPT12IRC_GPT12CR_Msk
Definition: tle985x.h:9937
#define GPT12E_T3CON_T3OTL_Pos
Definition: tle985x.h:8851
#define GPT12E_PISEL_ISCAPIN_Msk
Definition: tle985x.h:8794
#define GPT12E_T5CON_T5UD_Msk
Definition: tle985x.h:8910
#define GPT12E_CAPREL_CAPREL_Pos
Definition: tle985x.h:8785
#define GPT12E_T3CON_T3UD_Pos
Definition: tle985x.h:8857
#define GPT12E_T5CON_T5I_Msk
Definition: tle985x.h:8916
#define SCU_GPT12ICLR_GPT2T6C_Msk
Definition: tle985x.h:9913
#define SCU_GPT12IRC_GPT1T3_Msk
Definition: tle985x.h:9945
#define GPT12E_T3CON_T3EDGE_Pos
Definition: tle985x.h:8847
#define SCU_GPT12IEN_T3IE_Pos
Definition: tle985x.h:9931
#define GPT12E_T3CON_T3UDE_Pos
Definition: tle985x.h:8855
#define GPT12E_T2_T2_Msk
Definition: tle985x.h:8817
#define SCU_GPT12IRC_GPT12CR_Pos
Definition: tle985x.h:9936
#define GPT12E_T3CON_T3DIR_Pos
Definition: tle985x.h:8843
#define GPT12E_T4_T4_Pos
Definition: tle985x.h:8866
#define GPT12E_T3CON_BPS1_Msk
Definition: tle985x.h:8850
#define GPT12E_T2CON_T2I_Pos
Definition: tle985x.h:8837
#define GPT12E_T4CON_T4EDGE_Msk
Definition: tle985x.h:8874
#define GPT12E_PISEL_IST4EUD_Msk
Definition: tle985x.h:8804
#define SCU_GPT12IEN_CRIE_Pos
Definition: tle985x.h:9923
#define SCU_GPT12IRC_GPT2T5_Pos
Definition: tle985x.h:9940
#define GPT12E_T6CON_T6CLR_Msk
Definition: tle985x.h:8924
#define SCU_GPT12PISEL_GPT12_Msk
Definition: tle985x.h:9954
#define GPT12E_T3CON_T3OE_Pos
Definition: tle985x.h:8853
#define GPT12E_T4CON_T4RC_Pos
Definition: tle985x.h:8881
#define GPT12E_T6CON_BPS2_Pos
Definition: tle985x.h:8925
#define GPT12E_T6CON_T6CLR_Pos
Definition: tle985x.h:8923
#define GPT12E_T3CON_BPS1_Pos
Definition: tle985x.h:8849
#define GPT12E_PISEL_IST6IN_Msk
Definition: tle985x.h:8798
#define GPT12E_T3CON_T3OTL_Msk
Definition: tle985x.h:8852
#define GPT12E_PISEL_IST3IN_Pos
Definition: tle985x.h:8809
#define GPT12E_PISEL_ISCAPIN_Pos
Definition: tle985x.h:8793
#define GPT12E_T3_T3_Msk
Definition: tle985x.h:8841
#define GPT12E_T3CON_T3UD_Msk
Definition: tle985x.h:8858
#define GPT12E_T4CON_T4UDE_Msk
Definition: tle985x.h:8884
#define GPT12E_T3CON_T3DIR_Msk
Definition: tle985x.h:8844
#define GPT12E_T4CON_T4M_Pos
Definition: tle985x.h:8889
#define GPT12E_T3CON_T3I_Pos
Definition: tle985x.h:8863
#define GPT12E_T2CON_T2UD_Msk
Definition: tle985x.h:8832
#define GPT12E_T3CON_T3M_Pos
Definition: tle985x.h:8861
#define GPT12E_T4CON_CLRT3EN_Pos
Definition: tle985x.h:8877
#define GPT12E_T3CON_T3CHDIR_Msk
Definition: tle985x.h:8846
#define SCU_GPT12IEN_T2IE_Pos
Definition: tle985x.h:9933
#define SCU_GPT12IEN_T3IE_Msk
Definition: tle985x.h:9932
#define GPT12E_T4CON_T4UD_Msk
Definition: tle985x.h:8886
#define SCU_GPT12ICLR_GPT1T4C_Pos
Definition: tle985x.h:9916
#define SCU_GPT12PISEL_GPT12_Pos
Definition: tle985x.h:9953
#define GPT12E_T2CON_T2RC_Msk
Definition: tle985x.h:8828
#define GPT12E_T2CON_T2R_Msk
Definition: tle985x.h:8834
#define GPT12E_T2CON_T2DIR_Pos
Definition: tle985x.h:8819
#define GPT12E_T4CON_CLRT2EN_Pos
Definition: tle985x.h:8879
#define GPT12E_T5CON_T5M_Pos
Definition: tle985x.h:8913
#define SCU_GPT12ICLR_GPT1T2C_Msk
Definition: tle985x.h:9921
#define SCU_GPT12ICLR_GPT12CRC_Pos
Definition: tle985x.h:9910
#define GPT12E_PISEL_IST6IN_Pos
Definition: tle985x.h:8797
#define GPT12E_T3_T3_Pos
Definition: tle985x.h:8840
#define GPT12E_PISEL_IST5IN_Msk
Definition: tle985x.h:8802
#define SCU_GPT12IRC_GPT2T5_Msk
Definition: tle985x.h:9941
#define GPT12E_T5CON_T5RC_Pos
Definition: tle985x.h:8905
#define SCU_GPT12IEN_T4IE_Msk
Definition: tle985x.h:9930
#define GPT12E_PISEL_IST4IN_Pos
Definition: tle985x.h:8805
#define SCU_GPT12ICLR_GPT1T3C_Msk
Definition: tle985x.h:9919
#define SCU_GPT12IRC_GPT1T4_Pos
Definition: tle985x.h:9942
#define GPT12E_PISEL_IST2EUD_Msk
Definition: tle985x.h:8812
#define SCU_GPT12ICLR_GPT1T2C_Pos
Definition: tle985x.h:9920
#define GPT12E_T5CON_T5I_Pos
Definition: tle985x.h:8915
#define GPT12E_T4CON_T4RDIR_Pos
Definition: tle985x.h:8869
#define GPT12E_PISEL_IST3EUD_Msk
Definition: tle985x.h:8808
#define GPT12E_T6CON_T6OE_Pos
Definition: tle985x.h:8929
#define GPT12E_T5CON_T5CLR_Pos
Definition: tle985x.h:8899
#define GPT12E_PISEL_IST6EUD_Pos
Definition: tle985x.h:8795
#define GPT12E_T6CON_T6UDE_Msk
Definition: tle985x.h:8932
#define GPT12E_T2CON_T2DIR_Msk
Definition: tle985x.h:8820
#define GPT12E_T6CON_T6R_Msk
Definition: tle985x.h:8936
#define GPT12E_T5CON_T5M_Msk
Definition: tle985x.h:8914
#define GPT12E_T3CON_T3M_Msk
Definition: tle985x.h:8862
#define GPT12E_T3CON_T3CHDIR_Pos
Definition: tle985x.h:8845
#define SCU_GPT12ICLR_GPT12CRC_Msk
Definition: tle985x.h:9911
#define GPT12E_T6CON_T6R_Pos
Definition: tle985x.h:8935
#define GPT12E_T6CON_T6M_Pos
Definition: tle985x.h:8937
#define GPT12E_T5CON_T5CLR_Msk
Definition: tle985x.h:8900
#define GPT12E_T3CON_T3R_Pos
Definition: tle985x.h:8859
#define GPT12E_T6CON_T6I_Msk
Definition: tle985x.h:8940
#define SCU_GPT12IEN_T6IE_Pos
Definition: tle985x.h:9925
#define GPT12E_T6CON_T6UD_Msk
Definition: tle985x.h:8934
#define GPT12E_T4CON_T4EDGE_Pos
Definition: tle985x.h:8873
#define GPT12E_T4_T4_Msk
Definition: tle985x.h:8867
#define GPT12E_T2CON_T2UDE_Pos
Definition: tle985x.h:8829
#define GPT12E_T5CON_T5SC_Pos
Definition: tle985x.h:8897
#define GPT12E_PISEL_IST2IN_Pos
Definition: tle985x.h:8813
#define GPT12E_PISEL_IST2IN_Msk
Definition: tle985x.h:8814
#define GPT12E_T4CON_T4R_Pos
Definition: tle985x.h:8887
#define GPT12E_T5CON_CT3_Msk
Definition: tle985x.h:8904
#define GPT12E_T3CON_T3EDGE_Msk
Definition: tle985x.h:8848
#define SCU_GPT12IRC_GPT1T2_Pos
Definition: tle985x.h:9946
#define GPT12E_T4CON_T4RDIR_Msk
Definition: tle985x.h:8870
#define SCU_GPT12IEN_T4IE_Pos
Definition: tle985x.h:9929
#define GPT12E_T2CON_T2I_Msk
Definition: tle985x.h:8838
#define GPT12E_T6CON_T6SR_Msk
Definition: tle985x.h:8922
#define GPT12E_T6CON_T6OTL_Pos
Definition: tle985x.h:8927
#define SCU_GPT12IRC_GPT1T4_Msk
Definition: tle985x.h:9943
#define GPT12E_T2CON_T2CHDIR_Msk
Definition: tle985x.h:8822
#define GPT12E_T6CON_T6M_Msk
Definition: tle985x.h:8938
#define GPT12E_PISEL_IST6EUD_Msk
Definition: tle985x.h:8796
#define SCU_GPT12ICLR_GPT1T4C_Msk
Definition: tle985x.h:9917
#define SCU_GPT12IRC_GPT2T6_Pos
Definition: tle985x.h:9938
#define SCU_GPT12ICLR_GPT1T3C_Pos
Definition: tle985x.h:9918
#define GPT12E_T3CON_T3I_Msk
Definition: tle985x.h:8864
#define GPT12E_CAPREL_CAPREL_Msk
Definition: tle985x.h:8786
#define GPT12E_T5CON_T5UDE_Msk
Definition: tle985x.h:8908
#define SCU_GPT12IRC_GPT1T3_Pos
Definition: tle985x.h:9944
#define GPT12E_PISEL_IST2EUD_Pos
Definition: tle985x.h:8811
#define GPT12E_PISEL_IST5IN_Pos
Definition: tle985x.h:8801
#define SCU_GPT12IRC_GPT1T2_Msk
Definition: tle985x.h:9947
#define GPT12E_T2CON_T2EDGE_Pos
Definition: tle985x.h:8823
#define GPT12E_T4CON_T4UD_Pos
Definition: tle985x.h:8885
#define GPT12E_T2CON_T2CHDIR_Pos
Definition: tle985x.h:8821
#define GPT12E_T5_T5_Msk
Definition: tle985x.h:8895
#define GPT12E_T4CON_T4I_Pos
Definition: tle985x.h:8891
#define GPT12E_T5CON_T5UD_Pos
Definition: tle985x.h:8909
#define GPT12E_PISEL_IST5EUD_Pos
Definition: tle985x.h:8799
#define GPT12E_T2_T2_Pos
Definition: tle985x.h:8816
#define GPT12E_T3CON_T3R_Msk
Definition: tle985x.h:8860
#define GPT12E_T4CON_CLRT2EN_Msk
Definition: tle985x.h:8880
#define GPT12E_T3CON_T3OE_Msk
Definition: tle985x.h:8854
#define GPT12E_T5CON_T5R_Pos
Definition: tle985x.h:8911
#define SCU_GPT12ICLR_GPT2T5C_Msk
Definition: tle985x.h:9915
#define GPT12E_T4CON_CLRT3EN_Msk
Definition: tle985x.h:8878
#define GPT12E_T5_T5_Pos
Definition: tle985x.h:8894
#define GPT12E_T6CON_T6I_Pos
Definition: tle985x.h:8939
#define GPT12E_T6_T6_Msk
Definition: tle985x.h:8919
#define SCU_GPT12IEN_T5IE_Pos
Definition: tle985x.h:9927
#define SCU_GPT12IEN_T6IE_Msk
Definition: tle985x.h:9926
#define GPT12E_T5CON_T5RC_Msk
Definition: tle985x.h:8906
#define GPT12E_T5CON_T5R_Msk
Definition: tle985x.h:8912
#define GPT12E_T4CON_T4M_Msk
Definition: tle985x.h:8890
#define GPT12E_T5CON_T5SC_Msk
Definition: tle985x.h:8898
#define GPT12E_T4CON_T4I_Msk
Definition: tle985x.h:8892
#define GPT12E_T5CON_T5UDE_Pos
Definition: tle985x.h:8907
#define GPT12E_T2CON_T2R_Pos
Definition: tle985x.h:8833
#define GPT12E_T3CON_T3UDE_Msk
Definition: tle985x.h:8856
#define GPT12E_T4CON_T4UDE_Pos
Definition: tle985x.h:8883
#define SCU_GPT12IRC_GPT2T6_Msk
Definition: tle985x.h:9939
#define GPT12E_T2CON_T2M_Pos
Definition: tle985x.h:8835
#define GPT12E_T4CON_T4CHDIR_Msk
Definition: tle985x.h:8872
#define SCU_GPT12IEN_T2IE_Msk
Definition: tle985x.h:9934
#define GPT12E_T6CON_BPS2_Msk
Definition: tle985x.h:8926
#define GPT12E_PISEL_IST3IN_Msk
Definition: tle985x.h:8810
#define SCU_GPT12IEN_CRIE_Msk
Definition: tle985x.h:9924
#define GPT12E_T2CON_T2RC_Pos
Definition: tle985x.h:8827
#define GPT12E_T6CON_T6OTL_Msk
Definition: tle985x.h:8928
#define GPT12E_T6CON_T6SR_Pos
Definition: tle985x.h:8921
#define GPT12E_T4CON_T4RC_Msk
Definition: tle985x.h:8882
#define GPT12E_T2CON_T2UDE_Msk
Definition: tle985x.h:8830
#define GPT12E_T5CON_CT3_Pos
Definition: tle985x.h:8903
#define GPT12E_T6CON_T6OE_Msk
Definition: tle985x.h:8930
#define GPT12E_T4CON_T4R_Msk
Definition: tle985x.h:8888
#define SCU_GPT12ICLR_GPT2T5C_Pos
Definition: tle985x.h:9914
#define GPT12E_T2CON_T2M_Msk
Definition: tle985x.h:8836
SFR low level access library.
INLINE uint16 u16_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 16-bit field of a 32-bit register.
Definition: sfr_access.h:448
INLINE uint8 u1_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 1-bit field of a 32-bit register.
Definition: sfr_access.h:423
INLINE void Field_Wrt32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:358
INLINE uint8 u8_Field_Rd32(const volatile uint32 *reg, uint8 pos, uint32 msk)
This function reads a 8-bit field of a 32-bit register.
Definition: sfr_access.h:438
INLINE void Field_Mod32(volatile uint32 *reg, uint8 pos, uint32 msk, uint32 val)
This function writes a bit field in a 32-bit register.
Definition: sfr_access.h:378
CMSIS register HeaderFile.
General type declarations.
#define INLINE
Definition: types.h:145
uint8_t uint8
8 bit unsigned value
Definition: types.h:153
uint16_t uint16
16 bit unsigned value
Definition: types.h:154
uint32_t uint32
32 bit unsigned value
Definition: types.h:155