Infineon MOTIX™ MCU TLE985x Device Family SDK
Data Fields

Detailed Description

SCU (SCU)

#include <tle985x.h>

Data Fields

union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   FNMIWDTC: 1
 
      __IM   uint32_t: 3
 
      __OM uint32_t   FNMIOWDC: 1
 
      __OM uint32_t   FNMIMAPC: 1
 
   }   bit
 
NMISRCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   EXINT0R: 1
 
      __IM uint32_t   EXINT0F: 1
 
      __IM uint32_t   EXINT1R: 1
 
      __IM uint32_t   EXINT1F: 1
 
      __IM uint32_t   EXINT2R: 1
 
      __IM uint32_t   EXINT2F: 1
 
   }   bit
 
IRCON0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   MON1R: 1
 
      __IM uint32_t   MON1F: 1
 
      __IM uint32_t   MON2R: 1
 
      __IM uint32_t   MON2F: 1
 
      __IM uint32_t   MON3R: 1
 
      __IM uint32_t   MON3F: 1
 
      __IM uint32_t   MON4R: 1
 
      __IM uint32_t   MON4F: 1
 
   }   bit
 
IRCON1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   EIR1: 1
 
      __IM uint32_t   TIR1: 1
 
      __IM uint32_t   RIR1: 1
 
   }   bit
 
IRCON2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   EIR2: 1
 
      __IM uint32_t   TIR2: 1
 
      __IM uint32_t   RIR2: 1
 
   }   bit
 
IRCON3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   CCU6SR0: 1
 
      __IM   uint32_t: 3
 
      __IM uint32_t   CCU6SR1: 1
 
      __IM uint32_t   CCU6SR2: 1
 
      __IM uint32_t   CCU6SR3: 1
 
   }   bit
 
IRCON4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   FNMIWDT: 1
 
      __IM   uint32_t: 2
 
      __IM uint32_t   FNMIOT: 1
 
      __IM uint32_t   FNMIOWD: 1
 
      __IM uint32_t   FNMIMAP: 1
 
      __IM uint32_t   FNMIECC: 1
 
      __IM uint32_t   FNMISUP: 1
 
      __IM uint32_t   FNMISTOF: 1
 
   }   bit
 
NMISR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 31
 
      __IOM uint32_t   EA: 1
 
   }   bit
 
IEN0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   VTOR_BYP: 2
 
   }   bit
 
VTOR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   NMIWDT: 1
 
      __IM   uint32_t: 2
 
      __IOM uint32_t   NMIOT: 1
 
      __IOM uint32_t   NMIOWD: 1
 
      __IOM uint32_t   NMIMAP: 1
 
      __IOM uint32_t   NMIECC: 1
 
      __IOM uint32_t   NMISUP: 1
 
      __IOM uint32_t   NMISTOF: 1
 
   }   bit
 
NMICON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EXINT0: 2
 
      __IOM uint32_t   EXINT1: 2
 
      __IOM uint32_t   EXINT2: 2
 
   }   bit
 
EXICON0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MON1: 2
 
      __IOM uint32_t   MON2: 2
 
      __IOM uint32_t   MON3: 2
 
      __IOM uint32_t   MON4: 2
 
   }   bit
 
EXICON1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EIREN1: 1
 
      __IOM uint32_t   TIREN1: 1
 
      __IOM uint32_t   RIREN1: 1
 
      __IM   uint32_t: 5
 
      __IOM uint32_t   EIREN2: 1
 
      __IOM uint32_t   TIREN2: 1
 
      __IOM uint32_t   RIREN2: 1
 
   }   bit
 
MODIEN1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RIEN1: 1
 
      __IOM uint32_t   TIEN1: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   EXINT2_EN: 1
 
      __IOM uint32_t   RIEN2: 1
 
      __IOM uint32_t   TIEN2: 1
 
   }   bit
 
MODIEN2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IE0: 1
 
   }   bit
 
MODIEN3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   IE1: 1
 
   }   bit
 
MODIEN4
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IOM uint32_t   SL: 1
 
      __IOM uint32_t   PD: 1
 
      __IOM uint32_t   SD: 1
 
   }   bit
 
PMCON0
 
__IM uint32_t RESERVED [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PBA0CLKREL: 1
 
   }   bit
 
CMCON2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTIN: 1
 
      __IOM uint32_t   WDTRS: 1
 
      __IOM uint32_t   WDTEN: 1
 
      __IM   uint32_t: 1
 
      __IM uint32_t   WDTPR: 1
 
      __IOM uint32_t   WINBEN: 1
 
   }   bit
 
WDTCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   APCLK_SET: 1
 
      __IM   uint32_t: 7
 
      __IOM uint32_t   CLKWDT_IE: 1
 
   }   bit
 
APCLK_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   APCLK1FAC: 2
 
      __IM   uint32_t: 6
 
      __IOM uint32_t   APCLK2FAC: 5
 
      __IOM uint32_t   BGCLK_SEL: 1
 
      __IOM uint32_t   BGCLK_DIV: 1
 
      __IOM uint32_t   CPCLK_SEL: 1
 
      __IOM uint32_t   CPCLK_DIV: 1
 
   }   bit
 
APCLK
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   APCLK1STS: 2
 
      __IM   uint32_t: 2
 
      __IM uint32_t   APCLK_ERR_STS: 1
 
      __IM uint32_t   APCLK2STS: 2
 
      __IM uint32_t   APCLK3STS: 1
 
      __IM uint32_t   BRDRV_CLK_ERR_STS: 1
 
   }   bit
 
APCLK_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ADC1_DIS: 1
 
      __IOM uint32_t   SSC1_DIS: 1
 
      __IOM uint32_t   CCU_DIS: 1
 
      __IOM uint32_t   T2_DIS: 1
 
      __IOM uint32_t   GPT12_DIS: 1
 
      __IM   uint32_t: 3
 
      __IOM uint32_t   SSC2_DIS: 1
 
      __IOM uint32_t   T21_DIS: 1
 
   }   bit
 
PMCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   APCLK1SCLR: 1
 
      __IM   uint32_t: 7
 
      __OM uint32_t   APCLK2SCLR: 1
 
      __OM uint32_t   APCLK3SCLR: 1
 
   }   bit
 
APCLK_SCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   LOCKUP: 1
 
      __IM   uint32_t: 6
 
      __IOM uint32_t   LOCKUP_EN: 1
 
   }   bit
 
RSTCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   ADC1_CLK_DIV: 4
 
      __IM   uint32_t: 4
 
      __IOM uint32_t   DPP1_CLK_DIV: 2
 
   }   bit
 
ADC1_CLK
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 4
 
      __IM uint32_t   NVMCLKFAC: 2
 
      __IOM uint32_t   SYSCLKSEL: 2
 
   }   bit
 
SYSCON0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 1
 
      __IOM uint32_t   MRAMINITSTS: 1
 
      __IOM uint32_t   PG100TP_CHKS_ERR: 1
 
   }   bit
 
SYS_STRTUP_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTREL: 8
 
   }   bit
 
WDTREL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTWINB: 8
 
   }   bit
 
WDTWINB
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   WDT: 16
 
   }   bit
 
WDT
 
__IM uint32_t RESERVED1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BR1_R: 1
 
      __IOM uint32_t   BR1_PRE: 3
 
   }   bit
 
BCON1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BG1_FD_SEL: 5
 
   }   bit
 
BGL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BG1_BR_VALUE: 11
 
      __IM   uint32_t: 5
 
      __IM uint32_t   BG1_TIM_VALUE: 11
 
   }   bit
 
BG1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BRDIS: 1
 
      __IOM uint32_t   BGSEL: 2
 
      __IM uint32_t   BRK: 1
 
      __IM uint32_t   EOFSYN: 1
 
      __IM uint32_t   ERRSYN: 1
 
      __IOM uint32_t   SYNEN: 1
 
   }   bit
 
LINST
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BR2_R: 1
 
      __IOM uint32_t   BR2_PRE: 3
 
   }   bit
 
BCON2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BG2_FD_SEL: 5
 
   }   bit
 
BGL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BG2_BR_VALUE: 11
 
      __IM   uint32_t: 5
 
      __IM uint32_t   BG2_TIM_VALUE: 11
 
   }   bit
 
BG2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 3
 
      __OM uint32_t   BRKC: 1
 
      __OM uint32_t   EOFSYNC: 1
 
      __OM uint32_t   ERRSYNC: 1
 
   }   bit
 
LINSCLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   VERID: 3
 
      __IM uint32_t   PRODID: 5
 
   }   bit
 
ID
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   PW_MODE: 2
 
      __IM uint32_t   PROTECT_S: 1
 
      __IOM uint32_t   PASS: 5
 
   }   bit
 
PASSWD
 
__IM uint32_t RESERVED2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   COREL: 4
 
      __IOM uint32_t   COUTS0: 1
 
      __IOM uint32_t   TLEN: 1
 
      __IOM uint32_t   COUTS1: 1
 
      __IOM uint32_t   EN: 1
 
   }   bit
 
COCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   EXINT0IS: 2
 
      __IOM uint32_t   EXINT1IS: 2
 
      __IOM uint32_t   EXINT2IS: 2
 
      __IOM uint32_t   URIOS1: 1
 
      __IOM uint32_t   U_TX_CONDIS: 1
 
      __IM   uint32_t: 8
 
      __IOM uint32_t   SSC12_M_SCK_OUTSEL: 1
 
      __IOM uint32_t   SSC12_M_MTSR_OUTSEL: 1
 
      __IOM uint32_t   SSC12_S_MRST_OUTSEL: 1
 
   }   bit
 
MODPISEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   T2EXCON: 1
 
      __IOM uint32_t   T21EXCON: 1
 
   }   bit
 
MODPISEL1
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T2IS: 2
 
      __IOM uint32_t   T21IS: 2
 
      __IOM uint32_t   T2EXIS: 2
 
      __IOM uint32_t   T21EXIS: 2
 
      __IOM uint32_t   T2EXISCNF: 2
 
      __IOM uint32_t   T21EXISCNF: 2
 
   }   bit
 
MODPISEL2
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 6
 
      __IOM uint32_t   URIOS2: 1
 
   }   bit
 
MODPISEL3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WDTSUSP: 1
 
      __IOM uint32_t   T12SUSP: 1
 
      __IOM uint32_t   T13SUSP: 1
 
      __IOM uint32_t   T2_SUSP: 1
 
      __IOM uint32_t   GPT12_SUSP: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   T21_SUSP: 1
 
      __IOM uint32_t   WDT1SUSP: 1
 
      __IOM uint32_t   MU_SUSP: 1
 
      __IOM uint32_t   ADC1_SUSP: 1
 
   }   bit
 
MODSUSP
 
__IM uint32_t RESERVED3
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   GPT12: 4
 
      __IOM uint32_t   TRIG_CONF: 1
 
      __IOM uint32_t   GPT12_SEL: 1
 
   }   bit
 
GPT12PISEL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   RIE: 1
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   NVMIE: 1
 
   }   bit
 
EDCCON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   RDBE: 1
 
      __IM   uint32_t: 1
 
      __IM uint32_t   NVMDBE: 1
 
      __IM uint32_t   RSBE: 1
 
   }   bit
 
EDCSTAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   SECTORINFO: 6
 
      __IOM uint32_t   SASTATUS: 2
 
      __IM   uint32_t: 8
 
      __IOM uint32_t   NVM_VAL_KEYS: 2
 
      __IOM uint32_t   NVM_DATA_MODE: 1
 
      __IOM uint32_t   RAM_VAL_KEYS: 2
 
      __IOM uint32_t   RAM_TEST_MODE: 1
 
   }   bit
 
MEMSTAT
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   EN_RD_CUS_BSL: 1
 
      __IM uint32_t   EN_PRG_CUS_BSL: 1
 
      __IM uint32_t   EN_RD_COD_LIN: 1
 
      __IM uint32_t   EN_PRG_COD_LIN: 1
 
      __IM uint32_t   EN_RD_DAT_LIN: 1
 
      __IM uint32_t   EN_PRG_DAT_LIN: 1
 
      __IM uint32_t   EN_RD_DAT_NL: 1
 
      __IM uint32_t   EN_PRG_DAT_NL: 1
 
      __IM   uint32_t: 8
 
      __IM uint32_t   EN_RD_S0: 1
 
      __IM uint32_t   DIS_RDUS: 1
 
      __IM uint32_t   DIS_RDUS_S0: 1
 
      __IM uint32_t   CUS_BSL_PW: 1
 
      __IM uint32_t   COD_LIN_PW: 1
 
      __IM uint32_t   DAT_LIN_PW: 1
 
      __IM uint32_t   DAT_NL_PW: 1
 
      __IM uint32_t   CUS_BSL_SIZE: 2
 
      __IM uint32_t   DAT_LIN_SIZE: 2
 
   }   bit
 
NVM_PROT_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   NVM_PROT_ERR: 1
 
      __IM uint32_t   NVM_ADDR_ERR: 1
 
      __IM uint32_t   NVM_SFR_PROT_ERR: 1
 
      __IM uint32_t   NVM_SFR_ADDR_ERR: 1
 
      __IM uint32_t   ROM_PROT_ERR: 1
 
   }   bit
 
MEM_ACC_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   P0_PDM0: 3
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   P0_PDM1: 3
 
      __IOM uint32_t   P0_PDM2: 3
 
      __IOM uint32_t   P0_PDM3: 3
 
      __IOM uint32_t   P0_PDM4: 3
 
      __IOM uint32_t   P0_PDM5: 3
 
      __IOM uint32_t   P0_PDM6: 3
 
   }   bit
 
P0_POCON0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   WAKEUPEN: 1
 
   }   bit
 
WAKECON
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   WAKEUP: 1
 
   }   bit
 
IRCON5
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   TCC: 2
 
   }   bit
 
TCCR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   P1_PDM0: 3
 
      __IM   uint32_t: 1
 
      __IOM uint32_t   P1_PDM1: 3
 
      __IOM uint32_t   P1_PDM2: 3
 
      __IOM uint32_t   P1_PDM4: 3
 
   }   bit
 
P1_POCON0
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   DU1TRIGGEN: 3
 
      __IM   uint32_t: 5
 
      __IOM uint32_t   DU2TRIGGEN: 3
 
      __IOM uint32_t   DU3TRIGGEN: 3
 
      __IOM uint32_t   DU4TRIGGEN: 3
 
   }   bit
 
MODPISEL4
 
__IM uint32_t RESERVED4 [3]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   RDBEC: 1
 
      __IM   uint32_t: 1
 
      __OM uint32_t   NVMDBEC: 1
 
      __OM uint32_t   RSBEC: 1
 
   }   bit
 
EDCSCLR
 
__IM uint32_t RESERVED5 [7]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   STOF_STSC: 1
 
   }   bit
 
STACK_OVFCLR
 
__IM uint32_t RESERVED6 [5]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STOF_EN: 1
 
   }   bit
 
STACK_OVF_CTRL
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM   uint32_t: 2
 
      __IOM uint32_t   STOF_ADDR_OFF_L: 10
 
      __IOM uint32_t   STOF_ADDR_OFF_H: 10
 
   }   bit
 
STACK_OVF_ADDR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   STOF_STS: 1
 
   }   bit
 
STACK_OVF_STS
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   BRDRV_CLK_DIV: 2
 
      __IM   uint32_t: 6
 
      __IOM uint32_t   BRDRV_TFILT_DIV: 5
 
   }   bit
 
BRDRV_CLK
 
__IM uint32_t RESERVED7 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   T2IE: 1
 
      __IOM uint32_t   T3IE: 1
 
      __IOM uint32_t   T4IE: 1
 
      __IOM uint32_t   T5IE: 1
 
      __IOM uint32_t   T6IE: 1
 
      __IOM uint32_t   CRIE: 1
 
   }   bit
 
GPT12IEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IM uint32_t   GPT1T2: 1
 
      __IM uint32_t   GPT1T3: 1
 
      __IM uint32_t   GPT1T4: 1
 
      __IM uint32_t   GPT2T5: 1
 
      __IM uint32_t   GPT2T6: 1
 
      __IM uint32_t   GPT12CR: 1
 
   }   bit
 
GPT12IRC
 
__IM uint32_t RESERVED8 [5]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   EXINT0RC: 1
 
      __OM uint32_t   EXINT0FC: 1
 
      __OM uint32_t   EXINT1RC: 1
 
      __OM uint32_t   EXINT1FC: 1
 
      __OM uint32_t   EXINT2RC: 1
 
      __OM uint32_t   EXINT2FC: 1
 
   }   bit
 
IRCON0CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   MON1RC: 1
 
      __OM uint32_t   MON1FC: 1
 
      __OM uint32_t   MON2RC: 1
 
      __OM uint32_t   MON2FC: 1
 
      __OM uint32_t   MON3RC: 1
 
      __OM uint32_t   MON3FC: 1
 
      __OM uint32_t   MON4RC: 1
 
      __OM uint32_t   MON4FC: 1
 
   }   bit
 
IRCON1CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   GPT1T2C: 1
 
      __OM uint32_t   GPT1T3C: 1
 
      __OM uint32_t   GPT1T4C: 1
 
      __OM uint32_t   GPT2T5C: 1
 
      __OM uint32_t   GPT2T6C: 1
 
      __OM uint32_t   GPT12CRC: 1
 
   }   bit
 
GPT12ICLR
 
__IM uint32_t RESERVED9 [2]
 
union {
   __IOM uint32_t   reg
 
   struct {
      __IOM uint32_t   MON1IE: 1
 
      __IOM uint32_t   MON2IE: 1
 
      __IOM uint32_t   MON3IE: 1
 
      __IOM uint32_t   MON4IE: 1
 
   }   bit
 
MONIEN
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   EIR1C: 1
 
      __OM uint32_t   TIR1C: 1
 
      __OM uint32_t   RIR1C: 1
 
   }   bit
 
IRCON2CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   EIR2C: 1
 
      __OM uint32_t   TIR2C: 1
 
      __OM uint32_t   RIR2C: 1
 
   }   bit
 
IRCON3CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   CCU6SR0C: 1
 
      __IM   uint32_t: 3
 
      __OM uint32_t   CCU6SR1C: 1
 
      __OM uint32_t   CCU6SR2C: 1
 
      __OM uint32_t   CCU6SR3C: 1
 
   }   bit
 
IRCON4CLR
 
union {
   __IOM uint32_t   reg
 
   struct {
      __OM uint32_t   WAKEUPC: 1
 
   }   bit
 
IRCON5CLR
 

Field Documentation

◆ 

union { ... } ADC1_CLK

◆ ADC1_CLK_DIV

__IOM uint32_t ADC1_CLK_DIV

[3..0] ADC1 Clock divider

◆ ADC1_DIS

__IOM uint32_t ADC1_DIS

[0..0] ADC1 Disable Request. Active high.

◆ ADC1_SUSP

__IOM uint32_t ADC1_SUSP

[10..10] ADC1 Unit Debug Suspend Bit

◆ 

union { ... } APCLK

◆ APCLK1FAC

__IOM uint32_t APCLK1FAC

[1..0] Analog Module Clock Factor

◆ APCLK1SCLR

__OM uint32_t APCLK1SCLR

[0..0] Analog Peripherals Clock Status Clear

◆ APCLK1STS

__IM uint32_t APCLK1STS

[1..0] Analog Peripherals Clock Status

◆ APCLK2FAC

__IOM uint32_t APCLK2FAC

[12..8] Slow Down Clock Divider for TFILT_CLK Generation

◆ APCLK2SCLR

__OM uint32_t APCLK2SCLR

[8..8] Analog Peripherals Clock Status Clear

◆ APCLK2STS

__IM uint32_t APCLK2STS

[9..8] Analog Peripherals Clock Status

◆ APCLK3SCLR

__OM uint32_t APCLK3SCLR

[16..16] Analog Peripherals Clock 3 Status Clear

◆ APCLK3STS

__IM uint32_t APCLK3STS

[16..16] Loss of Clock Status

◆ 

union { ... } APCLK_CTRL

◆ APCLK_ERR_STS

__IM uint32_t APCLK_ERR_STS

[4..4] APCLK Error Status

◆ 

union { ... } APCLK_SCLR

◆ APCLK_SET

__IOM uint32_t APCLK_SET

[0..0] Set and Overtake Flag for Clock Settings

◆ 

union { ... } APCLK_STS

◆ 

union { ... } BCON1

◆ 

union { ... } BCON2

◆ 

union { ... } BG1

◆ BG1_BR_VALUE

__IOM uint32_t BG1_BR_VALUE

[10..0] Baud Rate Reload Value

◆ BG1_FD_SEL

__IOM uint32_t BG1_FD_SEL

[4..0] Fractional Divider Selection

◆ BG1_TIM_VALUE

__IM uint32_t BG1_TIM_VALUE

[26..16] Baud Rate Timer Value

◆ 

union { ... } BG2

◆ BG2_BR_VALUE

__IOM uint32_t BG2_BR_VALUE

[10..0] Baud Rate Reload Value

◆ BG2_FD_SEL

__IOM uint32_t BG2_FD_SEL

[4..0] Fractional Divider Selection

◆ BG2_TIM_VALUE

__IM uint32_t BG2_TIM_VALUE

[26..16] Baud Rate Timer Value

◆ BGCLK_DIV

__IOM uint32_t BGCLK_DIV

[25..25] Bandgap Clock Divider

◆ BGCLK_SEL

__IOM uint32_t BGCLK_SEL

[24..24] Bandgap Clock Selection

◆ 

union { ... } BGL1

◆ 

union { ... } BGL2

◆ BGSEL

__IOM uint32_t BGSEL

[2..1] Baud Rate Select for Detection

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◆ BR1_PRE

__IOM uint32_t BR1_PRE

[3..1] Prescaler Bit

◆ BR1_R

__IOM uint32_t BR1_R

[0..0] Baud Rate Generator Run Control Bit

◆ BR2_PRE

__IOM uint32_t BR2_PRE

[3..1] Prescaler Bit

◆ BR2_R

__IOM uint32_t BR2_R

[0..0] Baud Rate Generator Run Control Bit

◆ BRDIS

__IOM uint32_t BRDIS

[0..0] Baud Rate Detection Disable

◆ 

union { ... } BRDRV_CLK

◆ BRDRV_CLK_DIV

__IOM uint32_t BRDRV_CLK_DIV

[1..0] Analog Module Clock Factorf

◆ BRDRV_CLK_ERR_STS

__IM uint32_t BRDRV_CLK_ERR_STS

[20..20] BRDRV CLK Error Status

◆ BRDRV_TFILT_DIV

__IOM uint32_t BRDRV_TFILT_DIV

[12..8] Slow Down Clock Divider for TFILT_CLK Generation

◆ BRK

[3..3] Break Field Flag

◆ BRKC

__OM uint32_t BRKC

[3..3] Break Field Flag Clear

◆ CCU6SR0

__IM uint32_t CCU6SR0

[0..0] Interrupt Flag 1 for CCU6

◆ CCU6SR0C

__OM uint32_t CCU6SR0C

[0..0] Interrupt Flag 1 for CCU6

◆ CCU6SR1

__IM uint32_t CCU6SR1

[4..4] Interrupt Flag 1 for CCU6

◆ CCU6SR1C

__OM uint32_t CCU6SR1C

[4..4] Interrupt Flag 1 for CCU6

◆ CCU6SR2

__IM uint32_t CCU6SR2

[16..16] Interrupt Flag 1 for CCU6

◆ CCU6SR2C

__OM uint32_t CCU6SR2C

[16..16] Interrupt Flag 1 for CCU6

◆ CCU6SR3

__IM uint32_t CCU6SR3

[20..20] Interrupt Flag 1 for CCU6

◆ CCU6SR3C

__OM uint32_t CCU6SR3C

[20..20] Interrupt Flag 1 for CCU6

◆ CCU_DIS

__IOM uint32_t CCU_DIS

[2..2] CCU Disable Request. Active high.

◆ CLKWDT_IE

__IOM uint32_t CLKWDT_IE

[8..8] Clock Watchdog Interrupt Enable

◆ 

union { ... } CMCON2

◆ 

union { ... } COCON

◆ COD_LIN_PW

__IM uint32_t COD_LIN_PW

[20..20] Status of Linear Region Password / Protection

◆ COREL

__IOM uint32_t COREL

[3..0] Clock Output Divider

◆ COUTS0

__IOM uint32_t COUTS0

[4..4] Clock Out Source Select Bit 0

◆ COUTS1

__IOM uint32_t COUTS1

[6..6] Clock Out Source Select Bit 1

◆ CPCLK_DIV

__IOM uint32_t CPCLK_DIV

[29..29] Charge Pump Clock Divider

◆ CPCLK_SEL

__IOM uint32_t CPCLK_SEL

[28..28] Charge Pump Clock Selection

◆ CRIE

[5..5] General Purpose Timer 12 Capture and Reload Interrupt Enable

◆ CUS_BSL_PW

__IM uint32_t CUS_BSL_PW

[19..19] Status of CBSL Region Password / Protection

◆ CUS_BSL_SIZE

__IM uint32_t CUS_BSL_SIZE

[25..24] CBSL Region Size Definition

◆ DAT_LIN_PW

__IM uint32_t DAT_LIN_PW

[21..21] Status of Data linear Region Password / Protection

◆ DAT_LIN_SIZE

__IM uint32_t DAT_LIN_SIZE

[27..26] Data linear Region Size Definition

◆ DAT_NL_PW

__IM uint32_t DAT_NL_PW

[22..22] Status of Non-Linear Region Password / Protection

◆ DIS_RDUS

__IM uint32_t DIS_RDUS

[17..17] Configuration of NVM Read Protection for Sector 1...n with EN_RD_* = 0

◆ DIS_RDUS_S0

__IM uint32_t DIS_RDUS_S0

[18..18] Configuration of NVM Read Protection for Sector 0 with EN_RD_S0 = 0

◆ DPP1_CLK_DIV

__IOM uint32_t DPP1_CLK_DIV

[9..8] ADC1 Post processing clock divider

◆ DU1TRIGGEN

__IOM uint32_t DU1TRIGGEN

[2..0] Differential Unit Trigger Enable

◆ DU2TRIGGEN

__IOM uint32_t DU2TRIGGEN

[10..8] Differential Unit Trigger Enable

◆ DU3TRIGGEN

__IOM uint32_t DU3TRIGGEN

[18..16] Differential Unit Trigger Enable

◆ DU4TRIGGEN

__IOM uint32_t DU4TRIGGEN

[26..24] Differential Unit Trigger Enable

◆ EA

[31..31] Global Interrupt Mask

◆ 

union { ... } EDCCON

◆ 

union { ... } EDCSCLR

◆ 

union { ... } EDCSTAT

◆ EIR1

__IM uint32_t EIR1

[0..0] Error Interrupt Flag for SSC1

◆ EIR1C

__OM uint32_t EIR1C

[0..0] Error Interrupt Flag for SSC1

◆ EIR2

__IM uint32_t EIR2

[0..0] Error Interrupt Flag for SSC2

◆ EIR2C

__OM uint32_t EIR2C

[0..0] Error Interrupt Flag for SSC2

◆ EIREN1

__IOM uint32_t EIREN1

[0..0] SSC 1 Error Interrupt Enable

◆ EIREN2

__IOM uint32_t EIREN2

[8..8] SSC 2 Error Interrupt Enable

◆ EN

[7..7] CLKOUT Enable

◆ EN_PRG_COD_LIN

__IM uint32_t EN_PRG_COD_LIN

[3..3] NVM Protection of Data in Linear Code Sectors

◆ EN_PRG_CUS_BSL

__IM uint32_t EN_PRG_CUS_BSL

[1..1] NVM Protection of Data in Customer BSL Region

◆ EN_PRG_DAT_LIN

__IM uint32_t EN_PRG_DAT_LIN

[5..5] NVM Protection of Data in Linear Data Sectors

◆ EN_PRG_DAT_NL

__IM uint32_t EN_PRG_DAT_NL

[7..7] NVM Protection of Data in Non-Linear Data Sectors

◆ EN_RD_COD_LIN

__IM uint32_t EN_RD_COD_LIN

[2..2] NVM Read Protection of Data in Linear Code Sectors

◆ EN_RD_CUS_BSL

__IM uint32_t EN_RD_CUS_BSL

[0..0] NVM Read Protection of Data in Customer BSL Region

◆ EN_RD_DAT_LIN

__IM uint32_t EN_RD_DAT_LIN

[4..4] NVM Read Protection of Data in Linear Data Sectors

◆ EN_RD_DAT_NL

__IM uint32_t EN_RD_DAT_NL

[6..6] NVM Read Protection of Data in Non-Linear Data Sectors

◆ EN_RD_S0

__IM uint32_t EN_RD_S0

[16..16] NVM Read Protection for Sector 0

◆ EOFSYN

__IM uint32_t EOFSYN

[4..4] End of SYN Byte Interrupt Flag

◆ EOFSYNC

__OM uint32_t EOFSYNC

[4..4] End of SYN Byte Interrupt Flag Clear

◆ ERRSYN

__IM uint32_t ERRSYN

[5..5] SYN Byte Error Interrupt Flag

◆ ERRSYNC

__OM uint32_t ERRSYNC

[5..5] SYN Byte Error Interrupt Flag

◆ 

union { ... } EXICON0

◆ 

union { ... } EXICON1

◆ EXINT0

__IOM uint32_t EXINT0

[1..0] External Interrupt 0 Trigger Select

◆ EXINT0F

__IM uint32_t EXINT0F

[1..1] Interrupt Flag for External Interrupt 0x on falling edge

◆ EXINT0FC

__OM uint32_t EXINT0FC

[1..1] Interrupt Flag for External Interrupt 0x on falling edge

◆ EXINT0IS

__IOM uint32_t EXINT0IS

[1..0] External Interrupt 0 Input Select

◆ EXINT0R

__IM uint32_t EXINT0R

[0..0] Interrupt Flag for External Interrupt 0x on rising edge

◆ EXINT0RC

__OM uint32_t EXINT0RC

[0..0] Interrupt Flag for External Interrupt 0x on rising edge

◆ EXINT1

__IOM uint32_t EXINT1

[3..2] External Interrupt 1 Trigger Select

◆ EXINT1F

__IM uint32_t EXINT1F

[3..3] Interrupt Flag for External Interrupt 1x on falling edge

◆ EXINT1FC

__OM uint32_t EXINT1FC

[3..3] Interrupt Flag for External Interrupt 1x on falling edge

◆ EXINT1IS

__IOM uint32_t EXINT1IS

[3..2] External Interrupt 1 Input Select

◆ EXINT1R

__IM uint32_t EXINT1R

[2..2] Interrupt Flag for External Interrupt 1x on rising edge

◆ EXINT1RC

__OM uint32_t EXINT1RC

[2..2] Interrupt Flag for External Interrupt 1x on rising edge

◆ EXINT2

__IOM uint32_t EXINT2

[5..4] External Interrupt 2 Trigger Select

◆ EXINT2_EN

__IOM uint32_t EXINT2_EN

[5..5] External Interrupt 2 Enable

◆ EXINT2F

__IM uint32_t EXINT2F

[5..5] Interrupt Flag for External Interrupt 2x on falling edge

◆ EXINT2FC

__OM uint32_t EXINT2FC

[5..5] Interrupt Flag for External Interrupt 2x on falling edge

◆ EXINT2IS

__IOM uint32_t EXINT2IS

[5..4] External Interrupt 2 Input Select

◆ EXINT2R

__IM uint32_t EXINT2R

[4..4] Interrupt Flag for External Interrupt 2x on rising edge

◆ EXINT2RC

__OM uint32_t EXINT2RC

[4..4] Interrupt Flag for External Interrupt 2x on rising edge

◆ FNMIECC

__IM uint32_t FNMIECC

[6..6] ECC Error NMI Flag

◆ FNMIMAP

__IM uint32_t FNMIMAP

[5..5] NVM Map Error NMI Flag

◆ FNMIMAPC

__OM uint32_t FNMIMAPC

[5..5] NVM Map Error NMI Flag

◆ FNMIOT

__IM uint32_t FNMIOT

[3..3] Overtemperature NMI Flag

◆ FNMIOWD

__IM uint32_t FNMIOWD

[4..4] Oscillator Watchdog NMI Flag

◆ FNMIOWDC

__OM uint32_t FNMIOWDC

[4..4] Oscillator Watchdog NMI Flag

◆ FNMISTOF

__IM uint32_t FNMISTOF

[8..8] Stack Overflow NMI Flag

◆ FNMISUP

__IM uint32_t FNMISUP

[7..7] Supply Prewarning NMI Flag

◆ FNMIWDT

__IM uint32_t FNMIWDT

[0..0] Watchdog Timer NMI Flag

◆ FNMIWDTC

__OM uint32_t FNMIWDTC

[0..0] Watchdog Timer NMI Flag

◆ GPT12

__IOM uint32_t GPT12

[3..0] GPT12 TIN3B / TIN4D Input Select

◆ GPT12_DIS

__IOM uint32_t GPT12_DIS

[4..4] General Purpose Timer 12 Disable Request. Active high.

◆ GPT12_SEL

__IOM uint32_t GPT12_SEL

[5..5] CCU6 Trigger Configuration.

◆ GPT12_SUSP

__IOM uint32_t GPT12_SUSP

[4..4] GPT12 Debug Suspend Bit

◆ GPT12CR

__IM uint32_t GPT12CR

[5..5] GPT Module 1 Capture Reload Interrupt Status

◆ GPT12CRC

__OM uint32_t GPT12CRC

[5..5] GPT Module 1 Capture Reload Interrupt Status

◆ 

union { ... } GPT12ICLR

◆ 

union { ... } GPT12IEN

◆ 

union { ... } GPT12IRC

◆ 

union { ... } GPT12PISEL

◆ GPT1T2

__IM uint32_t GPT1T2

[0..0] GPT Module 1 Timer 2 Interrupt Status

◆ GPT1T2C

__OM uint32_t GPT1T2C

[0..0] GPT Module 1 Timer 2 Interrupt Status

◆ GPT1T3

__IM uint32_t GPT1T3

[1..1] GPT Module 1 Timer3 Interrupt Status

◆ GPT1T3C

__OM uint32_t GPT1T3C

[1..1] GPT Module 1 Timer3 Interrupt Status

◆ GPT1T4

__IM uint32_t GPT1T4

[2..2] GPT Module 1 Timer4 Interrupt Status

◆ GPT1T4C

__OM uint32_t GPT1T4C

[2..2] GPT Module 1 Timer4 Interrupt Status

◆ GPT2T5

__IM uint32_t GPT2T5

[3..3] GPT Module 2 Timer5 Interrupt Status

◆ GPT2T5C

__OM uint32_t GPT2T5C

[3..3] GPT Module 2 Timer5 Interrupt Status

◆ GPT2T6

__IM uint32_t GPT2T6

[4..4] GPT Module 2Timer6 Interrupt Status

◆ GPT2T6C

__OM uint32_t GPT2T6C

[4..4] GPT Module 2Timer6 Interrupt Status

◆ 

union { ... } ID

◆ IE0

[0..0] External Interrupt Enable

◆ IE1

[0..0] External Interrupt Enable

◆ 

union { ... } IEN0

◆ 

union { ... } IRCON0

◆ 

union { ... } IRCON0CLR

◆ 

union { ... } IRCON1

◆ 

union { ... } IRCON1CLR

◆ 

union { ... } IRCON2

◆ 

union { ... } IRCON2CLR

◆ 

union { ... } IRCON3

◆ 

union { ... } IRCON3CLR

◆ 

union { ... } IRCON4

◆ 

union { ... } IRCON4CLR

◆ 

union { ... } IRCON5

◆ 

union { ... } IRCON5CLR

◆ 

union { ... } LINSCLR

◆ 

union { ... } LINST

◆ LOCKUP

__IOM uint32_t LOCKUP

[0..0] Lockup Flag

◆ LOCKUP_EN

__IOM uint32_t LOCKUP_EN

[7..7] Lockup Reset Enable Flag

◆ 

union { ... } MEM_ACC_STS

◆ 

union { ... } MEMSTAT

◆ 

union { ... } MODIEN1

◆ 

union { ... } MODIEN2

◆ 

union { ... } MODIEN3

◆ 

union { ... } MODIEN4

◆ 

union { ... } MODPISEL

◆ 

union { ... } MODPISEL1

◆ 

union { ... } MODPISEL2

◆ 

union { ... } MODPISEL3

◆ 

union { ... } MODPISEL4

◆ 

union { ... } MODSUSP

◆ MON1

[1..0] MON1 Input Trigger Select

◆ MON1F

__IM uint32_t MON1F

[1..1] Interrupt Flag for MON1x on falling edge

◆ MON1FC

__OM uint32_t MON1FC

[1..1] Interrupt Flag for MON1x on falling edge

◆ MON1IE

__IOM uint32_t MON1IE

[0..0] MON 1 Interrupt Enable

◆ MON1R

__IM uint32_t MON1R

[0..0] Interrupt Flag for MON1x on rising edge

◆ MON1RC

__OM uint32_t MON1RC

[0..0] Interrupt Flag for MON1x on rising edge

◆ MON2

[3..2] MON2 Input Trigger Select

◆ MON2F

__IM uint32_t MON2F

[3..3] Interrupt Flag for MON2x on falling edge

◆ MON2FC

__OM uint32_t MON2FC

[3..3] Interrupt Flag for MON2x on falling edge

◆ MON2IE

__IOM uint32_t MON2IE

[1..1] MON 2 Interrupt Enable

◆ MON2R

__IM uint32_t MON2R

[2..2] Interrupt Flag for MON2x on rising edge

◆ MON2RC

__OM uint32_t MON2RC

[2..2] Interrupt Flag for MON2x on rising edge

◆ MON3

[5..4] MON3 Input Trigger Select

◆ MON3F

__IM uint32_t MON3F

[5..5] Interrupt Flag for MON3x on falling edge

◆ MON3FC

__OM uint32_t MON3FC

[5..5] Interrupt Flag for MON3x on falling edge

◆ MON3IE

__IOM uint32_t MON3IE

[2..2] MON 3 Interrupt Enable

◆ MON3R

__IM uint32_t MON3R

[4..4] Interrupt Flag for MON3x on rising edge

◆ MON3RC

__OM uint32_t MON3RC

[4..4] Interrupt Flag for MON3x on rising edge

◆ MON4

[7..6] MON4 Input Trigger Select

◆ MON4F

__IM uint32_t MON4F

[7..7] Interrupt Flag for MON4x on falling edge

◆ MON4FC

__OM uint32_t MON4FC

[7..7] Interrupt Flag for MON4x on falling edge

◆ MON4IE

__IOM uint32_t MON4IE

[3..3] MON 4 Interrupt Enable

◆ MON4R

__IM uint32_t MON4R

[6..6] Interrupt Flag for MON4x on rising edge

◆ MON4RC

__OM uint32_t MON4RC

[6..6] Interrupt Flag for MON4x on rising edge

◆ 

union { ... } MONIEN

◆ MRAMINITSTS

__IOM uint32_t MRAMINITSTS

[1..1] Map RAM Initialisation Status

◆ MU_SUSP

__IOM uint32_t MU_SUSP

[9..9] Measurement Unit Debug Suspend Bit

◆ 

union { ... } NMICON

◆ NMIECC

__IOM uint32_t NMIECC

[6..6] ECC Error NMI Enable

◆ NMIMAP

__IOM uint32_t NMIMAP

[5..5] NVM Map Error NMI Enable

◆ NMIOT

__IOM uint32_t NMIOT

[3..3] NMI OT Enable

◆ NMIOWD

__IOM uint32_t NMIOWD

[4..4] Oscillator Watchdog NMI Enable

◆ 

union { ... } NMISR

◆ 

union { ... } NMISRCLR

< (@ 0x50005000) SCU Structure

◆ NMISTOF

__IOM uint32_t NMISTOF

[8..8] Stack Overflow NMI Enable

◆ NMISUP

__IOM uint32_t NMISUP

[7..7] Supply Prewarning NMI Enable

◆ NMIWDT

__IOM uint32_t NMIWDT

[0..0] Watchdog Timer NMI Enable

◆ NVM_ADDR_ERR

__IM uint32_t NVM_ADDR_ERR

[1..1] NVM Address Protection

◆ NVM_DATA_MODE

__IOM uint32_t NVM_DATA_MODE

[18..18] NVM Data Mode

◆ NVM_PROT_ERR

__IM uint32_t NVM_PROT_ERR

[0..0] NVM Access Protection

◆ 

union { ... } NVM_PROT_STS

◆ NVM_SFR_ADDR_ERR

__IM uint32_t NVM_SFR_ADDR_ERR

[3..3] NVM SFR Address Protection

◆ NVM_SFR_PROT_ERR

__IM uint32_t NVM_SFR_PROT_ERR

[2..2] NVM SFR Access Protection

◆ NVM_VAL_KEYS

__IOM uint32_t NVM_VAL_KEYS

[17..16] NVM valid keys

◆ NVMCLKFAC

__IM uint32_t NVMCLKFAC

[5..4] NVM Access Clock Factor

◆ NVMDBE

__IM uint32_t NVMDBE

[2..2] NVM Double Bit Error

◆ NVMDBEC

__OM uint32_t NVMDBEC

[2..2] NVM Double Bit Error Clear

◆ NVMIE

__IOM uint32_t NVMIE

[2..2] NVM Double Bit ECC Error Interrupt Enable

◆ P0_PDM0

__IOM uint32_t P0_PDM0

[2..0] P0.0 Port Driver Mode

◆ P0_PDM1

__IOM uint32_t P0_PDM1

[6..4] P0.1 Port Driver Mode

◆ P0_PDM2

__IOM uint32_t P0_PDM2

[10..8] P0.2 Port Driver Mode

◆ P0_PDM3

__IOM uint32_t P0_PDM3

[14..12] P0.3 Port Driver Mode

◆ P0_PDM4

__IOM uint32_t P0_PDM4

[18..16] P0.4 Port Driver Mode

◆ P0_PDM5

__IOM uint32_t P0_PDM5

[22..20] P0.5 Port Driver Mode

◆ P0_PDM6

__IOM uint32_t P0_PDM6

[26..24] P0.6 Port Driver Mode

◆ 

union { ... } P0_POCON0

◆ P1_PDM0

__IOM uint32_t P1_PDM0

[2..0] P1.0 Port Driver Mode

◆ P1_PDM1

__IOM uint32_t P1_PDM1

[6..4] P1.1 Port Driver Mode

◆ P1_PDM2

__IOM uint32_t P1_PDM2

[10..8] P1.2 Port Driver Mode

◆ P1_PDM4

__IOM uint32_t P1_PDM4

[18..16] P1.4 Port Driver Mode

◆ 

union { ... } P1_POCON0

◆ PASS

[7..3] Password Bits

◆ 

union { ... } PASSWD

◆ PBA0CLKREL

__IOM uint32_t PBA0CLKREL

[0..0] PBA0 Clock Divider

◆ PD

[2..2] Power Down Mode Enable. Active High.

◆ PG100TP_CHKS_ERR

__IOM uint32_t PG100TP_CHKS_ERR

[2..2] 100 TP Page Checksum Error

◆ 

union { ... } PMCON

◆ 

union { ... } PMCON0

◆ PRODID

__IM uint32_t PRODID

[7..3] Product ID

◆ PROTECT_S

__IM uint32_t PROTECT_S

[2..2] Bit-Protection Signal Status Bit

◆ PW_MODE

__IOM uint32_t PW_MODE

[1..0] Bit-Protection Scheme Control Bit

◆ RAM_TEST_MODE

__IOM uint32_t RAM_TEST_MODE

[22..22] RAM Data Mode

◆ RAM_VAL_KEYS

__IOM uint32_t RAM_VAL_KEYS

[21..20] RAM valid keys

◆ RDBE

__IM uint32_t RDBE

[0..0] RAM Double Bit Error

◆ RDBEC

__OM uint32_t RDBEC

[0..0] RAM Double Bit Error Clear

◆ reg

(@ 0x00000000) NMI Status Clear Register

(@ 0x00000004) Interrupt Request Register 0

(@ 0x00000008) Interrupt Request Register 1

(@ 0x0000000C) Interrupt Request Register 2

(@ 0x00000010) Interrupt Request Register 3

(@ 0x00000014) Interrupt Request Register 4

(@ 0x00000018) NMI Status Register

(@ 0x0000001C) Interrupt Enable Register 0

(@ 0x00000020) Vector Table Reallocation Register

(@ 0x00000024) NMI Control Register

(@ 0x00000028) External Interrupt Control Register 0

(@ 0x0000002C) External Interrupt Control Register 1

(@ 0x00000030) Peripheral Interrupt Enable Register 1

(@ 0x00000034) Peripheral Interrupt Enable Register 2

(@ 0x00000038) Peripheral Interrupt Enable Register 3

(@ 0x0000003C) Peripheral Interrupt Enable Register 4

(@ 0x00000040) Power Mode Control Register 0

(@ 0x0000004C) Clock Control Register 2

(@ 0x00000050) Watchdog Timer Control Register

(@ 0x00000054) Analog Peripheral Clock Control Register

(@ 0x00000058) Analog Peripheral Clock Register

(@ 0x0000005C) Analog Peripheral Clock Status Register

(@ 0x00000060) Peripheral Management Control Register

(@ 0x00000064) Analog Peripheral Clock Status Clear Register

(@ 0x00000068) Reset Control Register

(@ 0x0000006C) ADC1 Peripheral Clock Register

(@ 0x00000070) System Control Register 0

(@ 0x00000074) System Startup Status Register

(@ 0x00000078) Watchdog Timer Reload Register

(@ 0x0000007C) Watchdog Window-Boundary Count

(@ 0x00000080) Watchdog Timer

(@ 0x00000088) Baud Rate Control Register 1

(@ 0x0000008C) Baud Rate Timer/Reload Register, Low Byte 1

(@ 0x00000090) Baud Rate Timer/Reload Register

(@ 0x00000094) LIN Status Register

(@ 0x00000098) Baud Rate Control Register 2

(@ 0x0000009C) Baud Rate Timer/Reload Register, Low Byte 2

(@ 0x000000A0) Baud Rate Timer/Reload Register

(@ 0x000000A4) LIN Status Clear Register

(@ 0x000000A8) Identity Register

(@ 0x000000AC) Password Register

(@ 0x000000B4) Clock Output Control Register

(@ 0x000000B8) Peripheral Input Select Register

(@ 0x000000BC) Peripheral Input Select Register 1

(@ 0x000000C0) Peripheral Input Select Register 2

(@ 0x000000C4) Peripheral Input Select Register 3

(@ 0x000000C8) Module Suspend Control Register

(@ 0x000000D0) GPT12 Peripheral Input Select Register

(@ 0x000000D4) Error Detection and Correction Control Register

(@ 0x000000D8) Error Detection and Correction Status Register

(@ 0x000000DC) Memory Status Register

(@ 0x000000E0) NVM Protection Status Register

(@ 0x000000E4) Memory Access Status Register

(@ 0x000000E8) Port Output Control Register

(@ 0x000000EC) Wakeup Interrupt Control Register

(@ 0x000000F0) Interrupt Request Register 5

(@ 0x000000F4) Temperature Compensation Control Register

(@ 0x000000F8) Port Output Control Register

(@ 0x000000FC) Peripheral Input Select Register 4

(@ 0x0000010C) Error Detection and Correction Status Clear Register

(@ 0x0000012C) Stack Overflow Status Clear Register

(@ 0x00000144) Stack Overflow Control Register

(@ 0x00000148) Stack Overflow Control Register

(@ 0x0000014C) Stack Overflow Status Register

(@ 0x00000150) ADC1 Peripheral Clock Register

(@ 0x0000015C) General Purpose Timer 12 Interrupt Enable Register

(@ 0x00000160) Timer and Counter Control/Status Register

(@ 0x00000178) Interrupt Request 0 Clear Register

(@ 0x0000017C) Interrupt Request 1 Clear Register

(@ 0x00000180) Timer and Counter Control/Status Clear Register

(@ 0x0000018C) Monitoring Input Interrupt Enable Register

(@ 0x00000190) Interrupt Request 2 Clear Register

(@ 0x00000194) Interrupt Request 3 Clear Register

(@ 0x00000198) Interrupt Request 4 Clear Register

(@ 0x0000019C) Interrupt Request 5 Clear Register

◆ RESERVED

__IM uint32_t RESERVED[2]

◆ RESERVED1

__IM uint32_t RESERVED1

◆ RESERVED2

__IM uint32_t RESERVED2

◆ RESERVED3

__IM uint32_t RESERVED3

◆ RESERVED4

__IM uint32_t RESERVED4[3]

◆ RESERVED5

__IM uint32_t RESERVED5[7]

◆ RESERVED6

__IM uint32_t RESERVED6[5]

◆ RESERVED7

__IM uint32_t RESERVED7[2]

◆ RESERVED8

__IM uint32_t RESERVED8[5]

◆ RESERVED9

__IM uint32_t RESERVED9[2]

◆ RIE

[0..0] RAM Double Bit ECC Error Interrupt Enable

◆ RIEN1

__IOM uint32_t RIEN1

[0..0] UART 1 Receive Interrupt Enable

◆ RIEN2

__IOM uint32_t RIEN2

[6..6] UART 2 Receive Interrupt Enable

◆ RIR1

__IM uint32_t RIR1

[2..2] Receive Interrupt Flag for SSC1

◆ RIR1C

__OM uint32_t RIR1C

[2..2] Receive Interrupt Flag for SSC1

◆ RIR2

__IM uint32_t RIR2

[2..2] Receive Interrupt Flag for SSC2

◆ RIR2C

__OM uint32_t RIR2C

[2..2] Receive Interrupt Flag for SSC2

◆ RIREN1

__IOM uint32_t RIREN1

[2..2] SSC 1 Receive Interrupt Enable

◆ RIREN2

__IOM uint32_t RIREN2

[10..10] SSC 2 Receive Interrupt Enable

◆ ROM_PROT_ERR

__IM uint32_t ROM_PROT_ERR

[4..4] ROM Access Protection

◆ RSBE

__IM uint32_t RSBE

[4..4] RAM Single Bit Error

◆ RSBEC

__OM uint32_t RSBEC

[4..4] RAM Single Bit Error Clear

◆ 

union { ... } RSTCON

◆ SASTATUS

__IOM uint32_t SASTATUS

[7..6] Service Algorithm Status

◆ SD

[3..3] Slow Down Mode Enable. Active High.

◆ SECTORINFO

__IOM uint32_t SECTORINFO

[5..0] Sector Information

◆ SL

[1..1] Sleep Mode Enable. Active High.

◆ SSC12_M_MTSR_OUTSEL

__IOM uint32_t SSC12_M_MTSR_OUTSEL

[17..17] Output selection for SSC12_M_MTSR

◆ SSC12_M_SCK_OUTSEL

__IOM uint32_t SSC12_M_SCK_OUTSEL

[16..16] Output selection for SSC12_M_SCK

◆ SSC12_S_MRST_OUTSEL

__IOM uint32_t SSC12_S_MRST_OUTSEL

[18..18] Output selection for SSC12_S_MRST

◆ SSC1_DIS

__IOM uint32_t SSC1_DIS

[1..1] SSC Disable Request. Active high.

◆ SSC2_DIS

__IOM uint32_t SSC2_DIS

[8..8] SSC Disable Request. Active high.

◆ 

union { ... } STACK_OVF_ADDR

◆ 

union { ... } STACK_OVF_CTRL

◆ 

union { ... } STACK_OVF_STS

◆ 

union { ... } STACK_OVFCLR

◆ STOF_ADDR_OFF_H

__IOM uint32_t STOF_ADDR_OFF_H

[27..18] Stack Overflow High Address Offset

◆ STOF_ADDR_OFF_L

__IOM uint32_t STOF_ADDR_OFF_L

[11..2] Stack Overflow Low Address Offset

◆ STOF_EN

__IOM uint32_t STOF_EN

[0..0] Stack Overflow Enable

◆ STOF_STS

__IOM uint32_t STOF_STS

[0..0] Stack Overflow Status

◆ STOF_STSC

__OM uint32_t STOF_STSC

[0..0] Clear Stack Overflow Status

◆ SYNEN

__IOM uint32_t SYNEN

[6..6] End of SYN Byte and SYN Byte Error Interrupts Enable

◆ 

union { ... } SYS_STRTUP_STS

◆ SYSCLKSEL

__IOM uint32_t SYSCLKSEL

[7..6] System Clock Select

◆ 

union { ... } SYSCON0

◆ T12SUSP

__IOM uint32_t T12SUSP

[1..1] Timer 12 Debug Suspend Bit

◆ T13SUSP

__IOM uint32_t T13SUSP

[2..2] Timer 13 Debug Suspend Bit

◆ T21_DIS

__IOM uint32_t T21_DIS

[10..10] T21 Disable Request. Active high.

◆ T21_SUSP

__IOM uint32_t T21_SUSP

[6..6] Timer21 Debug Suspend Bit

◆ T21EXCON

__IOM uint32_t T21EXCON

[7..7] Timer 21 External Input Control

◆ T21EXIS

__IOM uint32_t T21EXIS

[7..6] Timer 21 External Input Select

◆ T21EXISCNF

__IOM uint32_t T21EXISCNF

[11..10] Timer 21 External Input Select Configuration

◆ T21IS

__IOM uint32_t T21IS

[3..2] Timer 21 Input Select

◆ T2_DIS

__IOM uint32_t T2_DIS

[3..3] T2 Disable Request. Active high.

◆ T2_SUSP

__IOM uint32_t T2_SUSP

[3..3] Timer2 Debug Suspend Bit

◆ T2EXCON

__IOM uint32_t T2EXCON

[6..6] Timer 2 External Input Control

◆ T2EXIS

__IOM uint32_t T2EXIS

[5..4] Timer 2 External Input Select

◆ T2EXISCNF

__IOM uint32_t T2EXISCNF

[9..8] Timer 2 External Input Select Configuration

◆ T2IE

[0..0] General Purpose Timer 12 T2 Interrupt Enable

◆ T2IS

[1..0] Timer 2 Input Select

◆ T3IE

[1..1] General Purpose Timer 12 T3 Interrupt Enable

◆ T4IE

[2..2] General Purpose Timer 12 T4 Interrupt Enable

◆ T5IE

[3..3] General Purpose Timer 12 T5 Interrupt Enable

◆ T6IE

[4..4] General Purpose Timer 12 T6 Interrupt Enable

◆ TCC

[1..0] Temperature Compensation Control

◆ 

union { ... } TCCR

◆ TIEN1

__IOM uint32_t TIEN1

[1..1] UART 1 Transmit Interrupt Enable

◆ TIEN2

__IOM uint32_t TIEN2

[7..7] UART 2 Transmit Interrupt Enable

◆ TIR1

__IM uint32_t TIR1

[1..1] Transmit Interrupt Flag for SSC1

◆ TIR1C

__OM uint32_t TIR1C

[1..1] Transmit Interrupt Flag for SSC1

◆ TIR2

__IM uint32_t TIR2

[1..1] Transmit Interrupt Flag for SSC2

◆ TIR2C

__OM uint32_t TIR2C

[1..1] Transmit Interrupt Flag for SSC2

◆ TIREN1

__IOM uint32_t TIREN1

[1..1] SSC 1 Transmit Interrupt Enable

◆ TIREN2

__IOM uint32_t TIREN2

[9..9] SSC 2 Transmit Interrupt Enable

◆ TLEN

[5..5] Toggle Latch Enable

◆ TRIG_CONF

__IOM uint32_t TRIG_CONF

[4..4] CCU6 Trigger Configuration.

◆ U_TX_CONDIS

__IOM uint32_t U_TX_CONDIS

[7..7] UART1 TxD Connection Disable

◆ uint32_t

__IM uint32_t

◆ URIOS1

__IOM uint32_t URIOS1

[6..6] UART1 Input/Output Select

◆ URIOS2

__IOM uint32_t URIOS2

[6..6] UART2 Input/Output Select

◆ VERID

__IM uint32_t VERID

[2..0] Version ID

◆ 

union { ... } VTOR

◆ VTOR_BYP

__IOM uint32_t VTOR_BYP

[1..0] Vector Table Bypass Mode

◆ 

union { ... } WAKECON

◆ WAKEUP

__IM uint32_t WAKEUP

[0..0] Interrupt Flag for Wakeup

◆ WAKEUPC

__OM uint32_t WAKEUPC

[0..0] Clear Flag for Wakeup Interrupt

◆ WAKEUPEN

__IOM uint32_t WAKEUPEN

[0..0] Wakeup Interrupt Enable

◆ WDT [1/2]

[15..0] Watchdog Timer Current Value

◆  [2/2]

union { ... } WDT

◆ WDT1SUSP

__IOM uint32_t WDT1SUSP

[7..7] Watchdog Timer 1 Debug Suspend Bit

◆ 

union { ... } WDTCON

◆ WDTEN

__IOM uint32_t WDTEN

[2..2] WDT Enable

◆ WDTIN

__IOM uint32_t WDTIN

[0..0] Watchdog Timer Input Frequency Selection

◆ WDTPR

__IM uint32_t WDTPR

[4..4] Watchdog Prewarning Mode Flag

◆ WDTREL [1/2]

__IOM uint32_t WDTREL

[7..0] Watchdog Timer Reload Value

◆  [2/2]

union { ... } WDTREL

◆ WDTRS

__IOM uint32_t WDTRS

[1..1] WDT Refresh Start

◆ WDTSUSP

__IOM uint32_t WDTSUSP

[0..0] SCU Watchdog Timer Debug Suspend Bit

◆ WDTWINB [1/2]

__IOM uint32_t WDTWINB

[7..0] Watchdog Window-Boundary Count Value

◆  [2/2]

union { ... } WDTWINB

◆ WINBEN

__IOM uint32_t WINBEN

[5..5] Watchdog Window-Boundary Enable


The documentation for this struct was generated from the following file: