Overview

The TRAVEO™ T2G Cluster 4M Lite Kit belongs to the TRAVEO™ Cluster 2D graphics family, featuring the TRAVEO™ T2G CYT3DL device as the MCU and an onboard EZ-USB™ FX3 with a USB Type-C connector for streaming RGB graphics data packets to a PC screen. This kit is primarily designed to evaluate the functions and features of the CYT3DL series microcontroller.

To use code from the BSP, simply include a reference to cybsp.h.

Features

Kit Features:

CYT3DLBBHS 4MB Flash 272-pin BGA device
Programming interface (Arm® Standard JTAG, Cortex® Debug + ETM with Arm® ETM Mictor)
Reset control with manual reset switch and voltage supervision
One 512-Mbit external Semper SPI NOR Flash that provides a fast, expandable memory for data and code
One 64-Mbit external Hyperram that provides a fast, expandable memory for data
KitProg3 on-board SWD programmer/debugger, USB-UART and USB-I2C bridge functionality
A Shield2Go connector interface and a MikroBUS connector interface
Two user LEDs, one user button, and a reset button for the T2G-C-2D device
A potentiometer which can be used to simulate analog sensor output
A mode button and a mode LED for KitProg3

Kit Contents:

T2G-C-2D evaluation board
USB Type-A to Micro-B cable
Quick start guide (printed on the kit package)
See Peripheral driver library (PDL) library

BSP Configuration

The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the bsp.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.

Components:

Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.

Defines:

CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
CY_USING_HAL - This define, enabled by default in some BSPs, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers. Newer BSPs pull in the v3.x HAL, which enables itself via its own makefile, so CY_USING_HAL is not present.
CYBSP_CUSTOM_SYSCLK_PM_CALLBACK - This define, disabled by default, causes the BSP to skip registering its default SysClk Power Management callback, if any, and instead to invoke the application-defined function cybsp_register_custom_sysclk_pm_callback to register an application-specific callback.

Clock Configuration

Clock	Source	Output Frequency
FLL	IMO	100.0 MHz
PLL	ECO	160.0 MHz
CLK_HF0	CLK_PATH6	100 MHz
CLK_HF1	CLK_PATH1	240 MHz
CLK_HF2	CLK_PATH7	100 MHz
CLK_HF3	CLK_PATH6	100 MHz
CLK_HF4	CLK_PATH7	50 MHz
CLK_HF5	CLK_PATH2	200 MHz
CLK_HF6	CLK_PATH2	200 MHz
CLK_HF7	CLK_PATH2	200 MHz
CLK_HF8	CLK_PATH3	264 MHz
CLK_HF9	CLK_PATH3	264 MHz
CLK_HF10	CLK_PATH4	200 MHz
CLK_HF11	CLK_PATH5	224 MHz
CLK_HF12	CLK_PATH8	160 MHz
CLK_HF13	CLK_PATH9	0 MHz

Power Configuration

System Idle Power Mode: Deep Sleep
VDDA Voltage: 3300 mV
VDDD Voltage: 3300 mV

See the BSP Setttings for additional board specific configuration settings.

API Reference Manual

The KIT_T2G_C-2D-4M_LITE Board Support Package provides a set of APIs to configure, initialize and use the board resources.

See the BSP API Reference Manual for the complete list of the provided interfaces.