ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
GP Timer 1 Static Configuration

Macros

#define TMR1_CFG_COUNT_UP   (0u)
 
#define TMR1_CFG_MODE   (1u)
 
#define TMR1_CFG_PRESCALE_FACTOR   (0u)
 
#define TMR1_CFG_CLOCK_SOURCE   (0u)
 
#define TMR1_CFG_LOAD_VALUE   (0x23E7u)
 
#define TMR1_CFG_ASYNC_LOAD_VALUE   (0x23E7u)
 
#define TMR1_CFG_ENABLE_RELOADING   (0u)
 
#define TMR1_CFG_ENABLE_SYNC_BYPASS   (0u)
 
#define TMR1_CFG_ENABLE_EVENT_CAPTURE   (1u)
 
#define TMR1_CFG_ENABLE_PRESCALE_RESET   (0u)
 
#define TMR1_CFG_EVENT_CAPTURE   (28u)
 
#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE   (1u)
 
#define TMR1_CFG_PWM0_IDLE_STATE   (1u)
 
#define TMR1_CFG_PWM0_MATCH_VALUE   (0x08F9u)
 

Detailed Description

Macro Definition Documentation

◆ TMR1_CFG_COUNT_UP

#define TMR1_CFG_COUNT_UP   (0u)

Count up or down. Used to control whether the timer increments (counts up) or decrements (counts down) the Up/Down counter, it can be set to
0 - Timer is set to count down.
1 - Timer is set to count up.

Definition at line 170 of file adi_tmr_config.h.

◆ TMR1_CFG_MODE

#define TMR1_CFG_MODE   (1u)

Timer mode. Used to control whether the timer runs in periodic or free running mode, it can be set to
0 - Timer is in free running mode.
1 - Timer is in periodic mode.

Definition at line 177 of file adi_tmr_config.h.

◆ TMR1_CFG_PRESCALE_FACTOR

#define TMR1_CFG_PRESCALE_FACTOR   (0u)

Prescale factor. Controls the prescaler division factor to the timer's selected clock. It can be set to
0 - source_clock/[1 or 4]
1 - source_clock/16
2 - source_clock/64
3 - source_clock/256

Definition at line 187 of file adi_tmr_config.h.

◆ TMR1_CFG_CLOCK_SOURCE

#define TMR1_CFG_CLOCK_SOURCE   (0u)

Timer clock source. Used to select a timer clock from the four available clock sources, it can be set to
0 - Select PCLK
1 - Select HFOSC
2 - Select LFOSC
3 - Select LFXTAL

Definition at line 196 of file adi_tmr_config.h.

◆ TMR1_CFG_LOAD_VALUE

#define TMR1_CFG_LOAD_VALUE   (0x23E7u)

Timer load value. The Up/Down counter is periodically loaded with this value if periodic mode is selected. LOAD writes during Up/Down counter timeout events are delayed until the event has passed. It can be set to any value from 0 to 65535.

Definition at line 203 of file adi_tmr_config.h.

◆ TMR1_CFG_ASYNC_LOAD_VALUE

#define TMR1_CFG_ASYNC_LOAD_VALUE   (0x23E7u)

Timer asynchronous load value. The Up/Down counter is periodically loaded with this value if periodic mode is selected. Writing Asynchronous Load value takes advantage of having the timer run on PCLK by bypassing clock synchronization logic otherwise required. It can be set to any value from 0 to 65535.

Definition at line 211 of file adi_tmr_config.h.

◆ TMR1_CFG_ENABLE_RELOADING

#define TMR1_CFG_ENABLE_RELOADING   (0u)

Reload control. This allows the user to select whether the Up/Down counter should be reset only on a timeout event or also when interrupt is cleared. It can be set to
0 - Up/down counter is only reset on a time out event.
1 - Resets the up/down counter when the interrupt is cleared.

Definition at line 218 of file adi_tmr_config.h.

◆ TMR1_CFG_ENABLE_SYNC_BYPASS

#define TMR1_CFG_ENABLE_SYNC_BYPASS   (0u)

Enable or disable Synchronization bypass
0 - Disable Synchronization bypass.
1 - Enable Synchronization bypass.

Definition at line 224 of file adi_tmr_config.h.

◆ TMR1_CFG_ENABLE_EVENT_CAPTURE

#define TMR1_CFG_ENABLE_EVENT_CAPTURE   (1u)

Enable or disable event capture. It can be set to
0 - Disable event capturing.
1 - Enable event capturing.

Definition at line 235 of file adi_tmr_config.h.

◆ TMR1_CFG_ENABLE_PRESCALE_RESET

#define TMR1_CFG_ENABLE_PRESCALE_RESET   (0u)

Enable or disable prescale reset
0 - Disable rescale reset.
1 - Enable rescale reset.

Definition at line 241 of file adi_tmr_config.h.

◆ TMR1_CFG_EVENT_CAPTURE

#define TMR1_CFG_EVENT_CAPTURE   (28u)

Event to be captured. One of the selected 40 events associated with a general purpose time can be captured. It can be set to a value of 0 - 39. Please refer hardware reference manual to know which events can be captured by a particular GP timer.

Definition at line 251 of file adi_tmr_config.h.

◆ TMR1_CFG_ENABLE_PWM0_MATCH_MODE

#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE   (1u)

Timer PWM Enable Match. This will control PWM operation mode of the timer. Toggle mode provides a 50% duty cycle and match mode provides a configurable duty cycle by using the match value. This value can be set to
0 - PWM in toggle mode.
1 - PWM in match mode.

Definition at line 265 of file adi_tmr_config.h.

◆ TMR1_CFG_PWM0_IDLE_STATE

#define TMR1_CFG_PWM0_IDLE_STATE   (1u)

Timer PWM Idle state. This will control PWM idle state. It can be set to
0 - PWM idles low.
1 - PWM idles high.

Definition at line 272 of file adi_tmr_config.h.

◆ TMR1_CFG_PWM0_MATCH_VALUE

#define TMR1_CFG_PWM0_MATCH_VALUE   (0x08F9u)

PWM Match value. The value is used when the PWM is operating in match mode. The PWM output is asserted when the Up/Down counter is equal to this match value. PWM output is deasserted again when a timeout event occurs. If the match value is never reached, or occurs simultaneous to a timeout event, the PWM output remains idle. It can be any value from 0 to 65535.

Definition at line 281 of file adi_tmr_config.h.