ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
Static Configuration

Macros

#define ADI_I2C_CFG_MCTL_MXMITDEC   (0)
 
#define ADI_I2C_CFG_MCTL_IENCMP   (1)
 
#define ADI_I2C_CFG_MCTL_IENACK   (1)
 
#define ADI_I2C_CFG_MCTL_IENALOST   (1)
 
#define ADI_I2C_CFG_MCTL_STRETCHSCL   (0)
 
#define ADI_I2C_CFG_MCTL_LOOPBACK   (0)
 
#define ADI_I2C_CFG_MCTL_COMPLETE   (0)
 
#define ADI_I2C_CFG_MCTL_MASEN   (0)
 
#define ADI_I2C_CFG_MCTL_BUSCLR   (1)
 
#define ADI_I2C_CFG_MCTL_STOPBUSCLR   (1)
 
#define ADI_I2C_CFG_DIV_HIGH   (25)
 
#define ADI_I2C_CFG_DIV_LOW   (31)
 
#define ADI_I2C_CFG_SHCTL_RST   (0)
 
#define ADI_I2C_CFG_TCTL_FILTEROFF   (0)
 
#define ADI_I2C_CFG_TCTL_THDATIN   (1)
 
#define ADI_I2C_CFG_ASTRETCH_MST   (0)
 
#define ADI_I2C_CFG_SLAVE_ADDRESS   (0x50)
 

Detailed Description

Macro Definition Documentation

◆ ADI_I2C_CFG_MCTL_MXMITDEC

#define ADI_I2C_CFG_MCTL_MXMITDEC   (0)

Master control register TX FIFO decrement control bit.
1 - Decrement master TX FIFO status when a byte has been fully serialized.
0 - Decrement master TX FIFO status when a byte is unloaded from the TX FIFO, but not yet serialized on the bus.

Definition at line 30 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_IENCMP

#define ADI_I2C_CFG_MCTL_IENCMP   (1)

Master control register STOP condition interrupt enable.
1 - Enable completion interrupt when a STOP condition is detected.
0 - Disable completion interrupt when a STOP condition is detected.

Definition at line 35 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_IENACK

#define ADI_I2C_CFG_MCTL_IENACK   (1)

Master control register NACK (NotACKnowledge) interrupt enable.
1 - Enable NACK interrupt when an acknowledge is not received.
0 - Disable NACK interrupt when an acknowledge is not received.

Definition at line 40 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_IENALOST

#define ADI_I2C_CFG_MCTL_IENALOST   (1)

Master control register ALOST (Arbitration LOST) interrupt enable.
1 - Enable ALOST interrupt when bus arbitration is lost.
0 - Disable ALOST interrupt when bus arbitration is lost.

Definition at line 45 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_STRETCHSCL

#define ADI_I2C_CFG_MCTL_STRETCHSCL   (0)

Master control register clock stretch enable.
1 - Enable clock stretch by slave device.
0 - Disable clock stretch by slave device.

Definition at line 50 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_LOOPBACK

#define ADI_I2C_CFG_MCTL_LOOPBACK   (0)

Master control register internal loopback enable.
1 - Enable internal looping of SCL and SDA outputs onto their corresponding inputs.
0 - Disable internal looping of SCL and SDA outputs onto their corresponding inputs.

Definition at line 55 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_COMPLETE

#define ADI_I2C_CFG_MCTL_COMPLETE   (0)

Master control register start condition back-off disable.
1 - Enables controller to compete for bus ownership even if another device is driving a START condition.
0 - Disables controller to compete for bus ownership even if another device is driving a START condition.

Definition at line 60 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_MASEN

#define ADI_I2C_CFG_MCTL_MASEN   (0)

Master control register device enable.
1 - Enable controller as a Master device.
0 - Disables controller as a Master device.

Definition at line 65 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_BUSCLR

#define ADI_I2C_CFG_MCTL_BUSCLR   (1)

Master control register busclear enable.
1-Enable busclear bit for generating extra nine clock cycles when I2C bus hangs 0-Disable busclear bit.

Definition at line 70 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_MCTL_STOPBUSCLR

#define ADI_I2C_CFG_MCTL_STOPBUSCLR   (1)

Master control register stopbusclear enable.
1-Enable stopbusclear bit for stopping the master to generate extra clock cycles when SDA release 0-Disable stopbusclear bit.

Definition at line 75 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_DIV_HIGH

#define ADI_I2C_CFG_DIV_HIGH   (25)

Standard Clock divider Clock-HI settings. Assuming a 26 MHz core clock, the following settings will be useful:

  • For STANDARD (100 kHz) rate, use: HI= 25, LO= 31.
  • For FAST (400 kHz) rate, use: HI=123, LO=129.

    Note
    The clock high setting varies with pull-up loading, board layout, slew-rate, etc., so exact settings are somewhat empirical. The clock high counter does not start until a logic high transition is sensed on the clock line, so variability in this logic transaction will alter the effective clock rate. This results from the internal clock-stretch hardware feature supporting a slave slow device that may hold off the master by holding the clock line low.
    See also
    ADI_I2C_CFG_DIV_LOW

Definition at line 96 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_DIV_LOW

#define ADI_I2C_CFG_DIV_LOW   (31)

Standard Clock divider Clock-LO setting

See also
ADI_I2C_CFG_DIV_HIGH

Definition at line 102 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_SHCTL_RST

#define ADI_I2C_CFG_SHCTL_RST   (0)

Shared control reset START/STOP detect circuit.
1 - Reset the SCL and SDA synchronizers, START/STOP detect logic, and LINEBUSY detect logic.
0 - Do nothing.

Definition at line 107 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_TCTL_FILTEROFF

#define ADI_I2C_CFG_TCTL_FILTEROFF   (0)

Timing control filter disable.
1 - Disable digital input clock filter.
0 - Enable digital input clock filter (1 PCLK).

Definition at line 112 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_TCTL_THDATIN

#define ADI_I2C_CFG_TCTL_THDATIN   (1)

Timing control data input hold time requirement to recognize START/STOP condition (5-bit max).
Value - Minimum data input hold time count in units of PCLK period. (Value = Thd/PCLK-period)

Definition at line 116 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_ASTRETCH_MST

#define ADI_I2C_CFG_ASTRETCH_MST   (0)

Master automatic stretch mode duration (4-bit), e.g., (in binary):

  • 0b0000 - No SCL clock stretching.
  • 0b0001 - Timeout after hold SCL LOW 2^1 = 2 bit-times.
  • 0b0010 - Timeout after hold SCL LOW 2^2 = 4 bit-times.
  • ...
  • 0b1110 - Timeout after hold SCL LOW 2^14 = 16,384 bit-times.
  • 0b1111 - Hold SCL LOW with no timeout.

    Where "bit-time" is computed by CLKDIV values and incoming UCLK (see HRM).

Definition at line 127 of file adi_i2c_config.h.

◆ ADI_I2C_CFG_SLAVE_ADDRESS

#define ADI_I2C_CFG_SLAVE_ADDRESS   (0x50)

Unformatted, 7-bit max width I2C "7-bit Addressing" slave device address value (unshifted and excluding R/W direction bit).
For example, the value:
0x50 - Is the "raw" (unencoded) slave address for the "Aardvark Activity Board" ATMEL AT24C02 I2C slave EEPROM device.
It is encoded (upshifted by one and ORed with R/W direction bit) on the I2C bus as:

  • 0xA0 for write operations, or
  • 0xA1 for read operations

Definition at line 135 of file adi_i2c_config.h.