ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_spi_def.h
1 
13 #ifndef ADI_SPI_DEF_H_
14 #define ADI_SPI_DEF_H_
15 
16 
17 
18 #include <drivers/spi/adi_spi.h>
19 
20 #define ADI_SPI_NUM_INSTANCES (3u)
21 #define ADI_SPI_FIFO_SIZE (8u)
22 #define ADI_SPI_IRQ_PARAM (7u)
23 
24 /* Macro mapping from ADuCM4x50 to ADuCM302x */
25 #if defined(__ADUCM302x__)
26 #define DMA_SPIH_TX_Int_Handler(void) DMA_SPI2_TX_Int_Handler(void)
27 #define DMA_SPIH_RX_Int_Handler(void) DMA_SPI2_RX_Int_Handler(void)
28 #endif
29 
32 /*
33  *****************************************************************************
34  * SPI Bitrate Initializer. Sets a default serial clockrate for the SPI channel.
35  *****************************************************************************/
36 /* #define ADI_SPI_BITRATE_INITIALIZER 4000000 // 4MHz default bitrate */
37 #define ADI_SPI_BITRATE_INITIALIZER 250000u /* depends on processor */
38 
39 /*
40  *****************************************************************************
41  * SPI0/SPI1 Control Register Initializer. This macro configures default
42  * settings for the SPI configuration control register when operated in Master-mode.
43  *****************************************************************************/
44 /* SPI master DMA mode control configuration */
45 #define ADI_SPI_MASTERCON_INITIALIZER BITM_SPI_CTL_MASEN
46 
47 /*
48  *****************************************************************************
49  * SPI0/SPI1 Control Register Initializer. This macro configures default
50  * settings for the SPI configuration control register when operated in Slave-mode.
51  *****************************************************************************/
52  #define ADI_SPI_SLAVECON_INITIALIZER BITM_SPI_CTL_OEN \
53  | BITM_SPI_CTL_ZEN \
54  | BITM_SPI_CTL_SPIEN
55 
56 /* 16-bit DMA... (two-byte size and increment) */
57 #define ADI_DMA_DATA_WIDTH ADI_DMA_WIDTH_2_BYTE
58 #define ADI_DMA_DATA_INCREMENT ADI_DMA_INCR_HALFWORD
66 typedef struct ADI_SPI_CONFIG
67 {
68  uint16_t SPI_CTL;
69  uint16_t SPI_DIV;
70 } ADI_SPI_CFG_TYPE;
71 
74 typedef struct __ADI_SPI_DEVICE_INFO
75 {
76  const uint16_t dmaTxIrqNumber; /* DMA channel ID-Tx */
77  const uint16_t dmaTxChannelNumber; /* Tx */
78  const uint16_t dmaRxIrqNumber; /* DMA channel ID-Rx */
79  const uint16_t dmaRxChannelNumber; /* DMA channel ID-Rx */
80  volatile ADI_SPI_TypeDef *pSpiRegs; /* Base address of the SPI registers */
81  const IRQn_Type eIRQn; /* IRQn */
82  ADI_SPI_HANDLE hDevice; /* SPI handle */
83 }ADI_SPI_DEVICE_INFO;
84 
85 
87 typedef struct __ADI_SPI_DEV_DATA_TYPE
88 {
89 
90  /* device attributes */
91  volatile ADI_SPI_TypeDef *pSpi;
92  ADI_SPI_DEVICE_INFO *pDevInfo;
93 
94  /* Callback and Callback parameters */
95  ADI_CALLBACK pfCallback;
96  void * pCBParam;
97  /* The last recorded SPI event */
98  uint32_t HWErrors;
100  uint8_t* pTxBuffer;
101  uint8_t* pRxBuffer;
102  uint16_t TxRemaining;
103  uint16_t RxRemaining;
104  uint8_t TxIncrement;
105  uint8_t RxIncrement;
107  volatile bool bTransferComplete;
109  bool bDmaMode;
110  bool bRdCtlMode; /* Use half duplex read control feature */
111  bool bBlockingMode;
112  ADI_SPI_CHIP_SELECT ChipSelect;
114  SEM_VAR_DECLR
115 } ADI_SPI_DEV_DATA_TYPE;
116 
117 
118 
121 #endif /* ADI_SPI_DEF_H__ */
122 
struct __ADI_SPI_DEV_DATA_TYPE * ADI_SPI_HANDLE
Definition: adi_spi.h:150
ADI_SPI_CHIP_SELECT
Definition: adi_spi.h:134