ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_spi_data.c
1 
13 #ifndef _ADI_SPI_DATA_C_
14 #define _ADI_SPI_DATA_C_
15 
18 #include "adi_spi_def.h"
19 #include "adi_spi_config.h"
20 #include <drivers/dma/adi_dma.h>
21 
22 /* Stores the information about the specific device */
23 static ADI_SPI_DEVICE_INFO spi_device_info [ADI_SPI_NUM_INSTANCES]=
24 {
25  {
26  DMA0_CH4_DONE_IRQn,
27  SPI0_TX_CHANn,
28  DMA0_CH5_DONE_IRQn,
29  SPI0_RX_CHANn,
30  (volatile ADI_SPI_TypeDef *)pADI_SPI0,
31  SPI0_EVT_IRQn,
32  NULL
33  },
34  {
35  DMA0_CH6_DONE_IRQn,
36  SPI1_TX_CHANn,
37  DMA0_CH7_DONE_IRQn,
38  SPI1_RX_CHANn,
39  (volatile ADI_SPI_TypeDef *)pADI_SPI1,
40  SPI1_EVT_IRQn,
41  NULL
42  },
43 
44  {
45  DMA0_CH0_DONE_IRQn,
46  SPI2_TX_CHANn,
47  DMA0_CH1_DONE_IRQn,
48  SPI2_RX_CHANn,
49  (volatile ADI_SPI_TypeDef *)pADI_SPI2,
50  SPI2_EVT_IRQn,
51  NULL
52  }
53 };
54 
55 /* SPI Application configuration array */
56 static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] =
57 {
58  /* Initialize SPI0 Instance configuration. */
59  {
60  /**** SPI_CFG register configuration *** */
61  (( ADI_SPI0_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) |
62  ( ADI_SPI0_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) |
63  ( ADI_SPI0_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) |
64  ( ADI_SPI0_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) |
65  ( ADI_SPI0_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) |
66  ( ADI_SPI0_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) |
67  ( ADI_SPI0_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) |
68  ( ADI_SPI0_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) |
69  ( ADI_SPI0_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) |
70  ( ADI_SPI0_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) |
71  ( ADI_SPI0_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) |
72  ( ADI_SPI0_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) |
73  ( ADI_SPI0_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) |
74  ( ADI_SPI0_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )),
75 
76  /**** SPI_DIV buad rate selection register *** */
78  << BITP_SPI_DIV_VALUE )
79  },
80  /* Initialize SPI1 Instance configuration. */
81  {
82  /**** SPI_CFG register configuration *** */
83  (( ADI_SPI1_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) |
84  ( ADI_SPI1_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) |
85  ( ADI_SPI1_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) |
86  ( ADI_SPI1_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) |
87  ( ADI_SPI1_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) |
88  ( ADI_SPI1_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) |
89  ( ADI_SPI1_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) |
90  ( ADI_SPI1_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) |
91  ( ADI_SPI1_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) |
92  ( ADI_SPI1_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) |
93  ( ADI_SPI1_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) |
94  ( ADI_SPI1_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) |
95  ( ADI_SPI1_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) |
96  ( ADI_SPI1_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )),
97 
98  /**** SPI_DIV buad rate selection register *** */
100  << BITP_SPI_DIV_VALUE )
101  },
102  /* Initialize SPI2 Instance configuration. */
103  {
104  /**** SPI_CFG register configuration *** */
105  (( ADI_SPI2_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) |
106  ( ADI_SPI2_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) |
107  ( ADI_SPI2_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) |
108  ( ADI_SPI2_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) |
109  ( ADI_SPI2_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) |
110  ( ADI_SPI2_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) |
111  ( ADI_SPI2_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) |
112  ( ADI_SPI2_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) |
113  ( ADI_SPI2_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) |
114  ( ADI_SPI2_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) |
115  ( ADI_SPI2_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) |
116  ( ADI_SPI2_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) |
117  ( ADI_SPI2_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) |
118  ( ADI_SPI2_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )),
119 
120  /**** SPI_DIV buad rate selection register *** */
121  (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\
122  << BITP_SPI_DIV_VALUE )
123  }
124 };
125 
128 #endif /* _ADI_SPI_DATA_C_ */
#define ADI_SPI2_CFG_ENABLE
#define ADI_SPI1_CFG_RX_OVERFLOW
#define ADI_SPI0_CFG_TRANSFER_INITIATE
#define ADI_SPI2_CFG_WIRED_OR
#define ADI_SPI1_CFG_CONTINUOUS
#define ADI_SPI1_CFG_CSERR_RESET
#define ADI_SPI1_CFG_WIRED_OR
#define ADI_SPI0_CFG_MISO_ENABLE
#define ADI_SPI1_CFG_BIT_RATE
#define ADI_SPI1_CFG_TX_FLUSH
#define ADI_CFG_SYSTEM_CLOCK_HZ
#define ADI_SPI2_CFG_BIT_RATE
#define ADI_SPI0_CFG_LOOPBACK
#define ADI_SPI2_CFG_TX_FLUSH
#define ADI_SPI0_CFG_LSB_MSB
#define ADI_SPI1_CFG_MISO_ENABLE
#define ADI_SPI2_CFG_RX_OVERFLOW
#define ADI_SPI1_CFG_CLK_PHASE
#define ADI_SPI0_CFG_CONTINUOUS
#define ADI_SPI0_CFG_CLK_POLARITY
#define ADI_SPI0_CFG_RX_OVERFLOW
#define ADI_SPI0_CFG_WIRED_OR
#define ADI_SPI1_CFG_CLK_POLARITY
#define ADI_SPI1_CFG_ENABLE
#define ADI_SPI0_CFG_ENABLE
#define ADI_SPI1_CFG_TRANSFER_INITIATE
#define ADI_SPI0_CFG_BIT_RATE
#define ADI_SPI1_CFG_LSB_MSB
#define ADI_SPI0_CFG_CSERR_RESET
#define ADI_SPI2_CFG_TRANSFER_INITIATE
#define ADI_SPI2_CFG_MISO_ENABLE
#define ADI_SPI0_CFG_TX_FLUSH
#define ADI_SPI1_CFG_RX_FLUSH
#define ADI_SPI1_CFG_LOOPBACK
#define ADI_SPI2_CFG_LOOPBACK
#define ADI_SPI2_CFG_CSERR_RESET
#define ADI_SPI0_CFG_RX_FLUSH
#define ADI_SPI0_CFG_CLK_PHASE
#define ADI_SPI2_CFG_CONTINUOUS
#define ADI_SPI2_CFG_CLK_PHASE
#define ADI_SPI2_CFG_CLK_POLARITY
#define ADI_SPI2_CFG_LSB_MSB
#define ADI_SPI0_CFG_TX_UNDERFLOW
#define ADI_SPI2_CFG_TX_UNDERFLOW
#define ADI_SPI1_CFG_TX_UNDERFLOW
#define ADI_SPI2_CFG_RX_FLUSH