ADuCM4x50 Device Drivers API Reference Manual
Release 4.0.0.0
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Macros | |
#define | ADI_I2C_CFG_MCTL_MXMITDEC (0) |
#define | ADI_I2C_CFG_MCTL_IENCMP (1) |
#define | ADI_I2C_CFG_MCTL_IENACK (1) |
#define | ADI_I2C_CFG_MCTL_IENALOST (1) |
#define | ADI_I2C_CFG_MCTL_STRETCHSCL (0) |
#define | ADI_I2C_CFG_MCTL_LOOPBACK (0) |
#define | ADI_I2C_CFG_MCTL_COMPLETE (0) |
#define | ADI_I2C_CFG_MCTL_MASEN (0) |
#define | ADI_I2C_CFG_MCTL_BUSCLR (1) |
#define | ADI_I2C_CFG_MCTL_STOPBUSCLR (1) |
#define | ADI_I2C_CFG_DIV_HIGH (25) |
#define | ADI_I2C_CFG_DIV_LOW (31) |
#define | ADI_I2C_CFG_SHCTL_RST (0) |
#define | ADI_I2C_CFG_TCTL_FILTEROFF (0) |
#define | ADI_I2C_CFG_TCTL_THDATIN (1) |
#define | ADI_I2C_CFG_ASTRETCH_MST (0) |
#define | ADI_I2C_CFG_SLAVE_ADDRESS (0x50) |
#define ADI_I2C_CFG_MCTL_MXMITDEC (0) |
Master control register TX FIFO decrement control bit.
1 - Decrement master TX FIFO status when a byte has been fully serialized.
0 - Decrement master TX FIFO status when a byte is unloaded from the TX FIFO, but not yet serialized on the bus.
Definition at line 30 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_IENCMP (1) |
Master control register STOP condition interrupt enable.
1 - Enable completion interrupt when a STOP condition is detected.
0 - Disable completion interrupt when a STOP condition is detected.
Definition at line 35 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_IENACK (1) |
Master control register NACK (NotACKnowledge) interrupt enable.
1 - Enable NACK interrupt when an acknowledge is not received.
0 - Disable NACK interrupt when an acknowledge is not received.
Definition at line 40 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_IENALOST (1) |
Master control register ALOST (Arbitration LOST) interrupt enable.
1 - Enable ALOST interrupt when bus arbitration is lost.
0 - Disable ALOST interrupt when bus arbitration is lost.
Definition at line 45 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_STRETCHSCL (0) |
Master control register clock stretch enable.
1 - Enable clock stretch by slave device.
0 - Disable clock stretch by slave device.
Definition at line 50 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_LOOPBACK (0) |
Master control register internal loopback enable.
1 - Enable internal looping of SCL and SDA outputs onto their corresponding inputs.
0 - Disable internal looping of SCL and SDA outputs onto their corresponding inputs.
Definition at line 55 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_COMPLETE (0) |
Master control register start condition back-off disable.
1 - Enables controller to compete for bus ownership even if another device is driving a START condition.
0 - Disables controller to compete for bus ownership even if another device is driving a START condition.
Definition at line 60 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_MASEN (0) |
Master control register device enable.
1 - Enable controller as a Master device.
0 - Disables controller as a Master device.
Definition at line 65 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_BUSCLR (1) |
Master control register busclear enable.
1-Enable busclear bit for generating extra nine clock cycles when I2C bus hangs 0-Disable busclear bit.
Definition at line 70 of file adi_i2c_config.h.
#define ADI_I2C_CFG_MCTL_STOPBUSCLR (1) |
Master control register stopbusclear enable.
1-Enable stopbusclear bit for stopping the master to generate extra clock cycles when SDA release 0-Disable stopbusclear bit.
Definition at line 75 of file adi_i2c_config.h.
#define ADI_I2C_CFG_DIV_HIGH (25) |
Standard Clock divider Clock-HI settings. Assuming a 26 MHz core clock, the following settings will be useful:
Definition at line 96 of file adi_i2c_config.h.
#define ADI_I2C_CFG_DIV_LOW (31) |
Standard Clock divider Clock-LO setting
Definition at line 102 of file adi_i2c_config.h.
#define ADI_I2C_CFG_SHCTL_RST (0) |
Shared control reset START/STOP detect circuit.
1 - Reset the SCL and SDA synchronizers, START/STOP detect logic, and LINEBUSY detect logic.
0 - Do nothing.
Definition at line 107 of file adi_i2c_config.h.
#define ADI_I2C_CFG_TCTL_FILTEROFF (0) |
Timing control filter disable.
1 - Disable digital input clock filter.
0 - Enable digital input clock filter (1 PCLK).
Definition at line 112 of file adi_i2c_config.h.
#define ADI_I2C_CFG_TCTL_THDATIN (1) |
Timing control data input hold time requirement to recognize START/STOP condition (5-bit max).
Value - Minimum data input hold time count in units of PCLK period. (Value = Thd/PCLK-period)
Definition at line 116 of file adi_i2c_config.h.
#define ADI_I2C_CFG_ASTRETCH_MST (0) |
Master automatic stretch mode duration (4-bit), e.g., (in binary):
Definition at line 127 of file adi_i2c_config.h.
#define ADI_I2C_CFG_SLAVE_ADDRESS (0x50) |
Unformatted, 7-bit max width I2C "7-bit Addressing" slave device address value (unshifted and excluding R/W direction bit).
For example, the value:
0x50 - Is the "raw" (unencoded) slave address for the "Aardvark Activity Board" ATMEL AT24C02 I2C slave EEPROM device.
It is encoded (upshifted by one and ORed with R/W direction bit) on the I2C bus as:
Definition at line 135 of file adi_i2c_config.h.