ADuCM4x50 Device Drivers API Reference Manual
Release 4.0.0.0
adi_rtc_config.h
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#ifndef ADI_RTC_CONFIG_H__
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#define ADI_RTC_CONFIG_H__
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#include <adi_global_config.h>
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#define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1
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/*
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===================================================================
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------------------------RTC-0 CONFIGURATION MACRO-----------------
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===================================================================
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*/
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#define RTC0_CFG_ENABLE_ALARM 0
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#define RTC0_CFG_ENABLE_ALARM_INTERRUPT 0
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#define RTC0_CFG_ENABLE_TRIM 0
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#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT 0
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#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT 0
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#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT 0
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#define RTC0_CFG_COUNT_VALUE 0
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#define RTC0_CFG_COUNT_VALUE_0 0
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#define RTC0_CFG_COUNT_VALUE_1 0
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#define RTC0_CFG_ALARM_VALUE_0 0
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#define RTC0_CFG_ALARM_VALUE_1 0
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#define RTC0_CFG_TRIM_INTERVAL 0
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#define RTC0_CFG_POW2_TRIM_INTERVAL 0
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#define RTC0_CFG_TRIM_OPERATION 0
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#define RTC0_CFG_TRIM_VALUE 0
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#define RTC0_SS3_SMPONRE 0
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#define RTC0_SS3_SMPONFE 0
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#define RTC0_SS2_SMPONFE 0
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#define RTC0_SS1_SMPONRE 0
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#define RTC0_SS1_SMPONFE 0
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#define RTC0_SS2_GPIN1SEL 0x4
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#define RTC0_SS2_GPIN0SEL 0x3
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#define RTC0_SS1_GPIN2SEL 0x2
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#define RTC0_SS1_GPIN1SEL 0x1
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#define RTC0_SS1_GPIN0SEL 0x0
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#define RTC0_SS3_GPIN2SEL 0x0
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#define RTC0_SS3_GPIN1SEL 0x7
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#define RTC0_SS3_GPIN0SEL 0x6
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#define RTC0_SS2_GPIN2SEL 0x5
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#define RTC0_SS3_DIFFOUT 0
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#define RTC0_SS1_DIFFOUT 0
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/*
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===================================================================
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------------------------RTC-1 CONFIGURATION MACRO-----------------
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===================================================================
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*/
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#define RTC1_CFG_ENABLE_ALARM 0
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#define RTC1_CFG_ENABLE_ALARM_INTERRUPT 0
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#define RTC1_CFG_ENABLE_TRIM 0
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#define RTC1_CFG_ENABLE_MOD60_ALARM 0
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#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD 0
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#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT 0
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#define RTC1_CFG_ENABLE_ISO_INTERRUPT 0
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#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT 0
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#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT 0
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#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT 0
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#define RTC1_CFG_ENABLE_COUNT_INTERRUPT 0
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#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT 0
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#define RTC1_CFG_ENABLE_TRIM_INTERRUPT 0
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#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT 0
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#define RTC1_CFG_PRESCALE 0
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#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT 0
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#define RTC1_CFG_COUNT_VALUE_0 0
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#define RTC1_CFG_COUNT_VALUE_1 0
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#define RTC1_CFG_ALARM_VALUE_0 0
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#define RTC1_CFG_ALARM_VALUE_1 0
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#define RTC1_CFG_ALARM_VALUE_2 0
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#define RTC1_CFG_TRIM_INTERVAL 0
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#define RTC1_CFG_POW2_TRIM_INTERVAL 0
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#define RTC1_CFG_TRIM_OPERATION 0
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#define RTC1_CFG_TRIM_VALUE 0
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#define RTC1_CFG_IC0_ENABLE 0
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#define RTC1_CFG_IC2_ENABLE 0
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#define RTC1_CFG_IC3_ENABLE 0
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#define RTC1_CFG_IC4_ENABLE 0
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#define RTC1_CFG_SS1_ENABLE 0
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#define RTC1_CFG_SS2_ENABLE 0
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#define RTC1_CFG_SS3_ENABLE 0
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#define RTC1_CFG_SS4_ENABLE 0
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#define RTC1_CFG_IC0_INT_ENABLE 0
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#define RTC1_CFG_IC2_INT_ENABLE 0
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#define RTC1_CFG_IC3_INT_ENABLE 0
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#define RTC1_CFG_IC4_INT_ENABLE 0
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#define RTC1_CFG_IC_OVER_WRITE_ENABLE 0
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#define RTC1_CFG_IC0_EDGE_POLARITY 0
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#define RTC1_CFG_IC2_EDGE_POLARITY 0
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#define RTC1_CFG_IC3_EDGE_POLARITY 0
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#define RTC1_CFG_IC4_EDGE_POLARITY 0
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#define RTC1_CFG_SS1_INT_ENABLE 0
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#define RTC1_CFG_SS2_INT_ENABLE 0
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#define RTC1_CFG_SS3_INT_ENABLE 0
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#define RTC1_CFG_SS4_INT_ENABLE 0
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#define RTC1_CFG_SS1_MASK_ENABLE 0
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#define RTC1_CFG_SS2_MASK_ENABLE 0
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#define RTC1_CFG_SS3_MASK_ENABLE 0
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#define RTC1_CFG_SS4_MASK_ENABLE 0
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#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE 0
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#if defined(__ADUCM4x50__)
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#define RTC1_CFG_SS2_AUTO_RELOADING_ENABLE 0
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#define RTC1_CFG_SS3_AUTO_RELOADING_ENABLE 0
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#endif
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#define RTC1_CFG_SS1_MASK_VALUE 0
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#if defined(__ADUCM4x50__)
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#define RTC1_CFG_SS2_MASK_VALUE 0
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#define RTC1_CFG_SS3_MASK_VALUE 0
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#define RTC1_CFG_SS4_MASK_VALUE 0
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#endif
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#if defined(__ADUCM302x__)
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#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE 32768/2
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#endif
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#define RTC_CFG_SS1_VALUE 32768/2
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#if defined(__ADUCM4x50__)
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#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH 32768/2
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#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW 32768/2
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#define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH 32768/2
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#define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW 32768/2
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#define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH 32768/2
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#define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW 32768/2
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#endif
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#define RTC1_SS2_GPIN1SEL 0x4
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#define RTC1_SS2_GPIN0SEL 0x3
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#define RTC1_SS1_GPIN2SEL 0x2
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#define RTC1_SS1_GPIN1SEL 0x1
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#define RTC1_SS1_GPIN0SEL 0x0
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#define RTC1_SS3_GPIN2SEL 0x0
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#define RTC1_SS3_GPIN1SEL 0x7
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#define RTC1_SS3_GPIN0SEL 0x6
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#define RTC1_SS2_GPIN2SEL 0x5
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#define RTC1_SS3_DIFFOUT 0
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#define RTC1_SS1_DIFFOUT 0
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#define RTC1_CFG_CR5SSS_OC1SMPEN 0
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#define RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN 0
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#define RTC1_CFG_CR5SSS_OC2SMPEN 0
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#define RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN 0
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#define RTC1_CFG_CR5SSS_OC3SMPEN 0
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#define RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN 0
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#define RTC1_CFG_CR6SSS_OC1SMPONFE 0
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#define RTC1_CFG_CR6SSS_OC1SMPONRE 0
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#define RTC1_CFG_CR6SSS_OC2SMPONFE 0
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#define RTC1_CFG_CR6SSS_OC2SMPONRE 0
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#define RTC1_CFG_CR6SSS_OC3SMPONFE 0
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#define RTC1_CFG_CR6SSS_OC3SMPONRE 0
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#define RTC1_CFG_CR7SSS_OC1SMPEXP 0
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#define RTC1_CFG_CR7SSS_OC1SMPPTRN 0
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#define RTC1_CFG_CR7SSS_OC2SMPEXP 0
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#define RTC1_CFG_CR7SSS_OC2SMPPTRN 0
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#define RTC1_CFG_CR7SSS_OC3SMPEXP 0
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#define RTC1_CFG_CR7SSS_OC3SMPPTRN 0
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#define RTC1_CFG_GPMUX0_OC1GPIN0SEL 0
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#define RTC1_CFG_GPMUX0_OC1GPIN1SEL 1
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#define RTC1_CFG_GPMUX0_OC1GPIN2SEL 2
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#define RTC1_CFG_GPMUX0_OC2GPIN0SEL 3
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#define RTC1_CFG_GPMUX0_OC2GPIN1SEL 4
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#define RTC1_CFG_GPMUX1_OC2GPIN2SEL 5
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#define RTC1_CFG_GPMUX1_OC3GPIN0SEL 6
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#define RTC1_CFG_GPMUX1_OC3GPIN1SEL 7
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#define RTC1_CFG_GPMUX1_OC3GPIN2SEL 0
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#define RTC1_CFG_GPMUX1_OC1DIFFOUT 0
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#define RTC1_CFG_GPMUX1_OC3DIFFOUT 0
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#endif
/* ADI_RTC_CONFIG_H__ */
Include
config
adi_rtc_config.h
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