ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_tmr_data.c
1 
13 #ifndef ADI_TMR_DATA
14 #define ADI_TMR_DATA
15 
16 
17 #include <stdlib.h>
18 #include <adi_tmr_config.h>
19 #include <drivers/tmr/adi_tmr.h>
20 
21 /* Macro mapping from ADuCM4x50 to ADuCM302x */
22 #if defined(__ADUCM302x__)
23 #define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN
24 #define PWM0CTL PWMCTL
25 #define PWM0MATCH PWMMATCH
26 #define BITM_TMR_RGB_STAT_BUSY BITM_TMR_STAT_BUSY
27 #define BITM_TMR_RGB_CTL_EVTEN BITM_TMR_CTL_EVTEN
28 #define BITM_TMR_RGB_CTL_RSTEN BITM_TMR_CTL_RSTEN
29 #define BITP_TMR_RGB_CTL_RSTEN BITP_TMR_CTL_RSTEN
30 #define BITP_TMR_RGB_CTL_EVTEN BITP_TMR_CTL_EVTEN
31 #define BITP_TMR_RGB_CTL_PRE BITP_TMR_CTL_PRE
32 #define BITP_TMR_RGB_CTL_CLK BITP_TMR_CTL_CLK
33 #define BITP_TMR_RGB_CTL_MODE BITP_TMR_CTL_MODE
34 #define BITP_TMR_RGB_CTL_UP BITP_TMR_CTL_UP
35 #define BITP_TMR_RGB_CTL_RLD BITP_TMR_CTL_RLD
36 #define BITP_TMR_RGB_CTL_SYNCBYP BITP_TMR_CTL_SYNCBYP
37 #define BITP_TMR_RGB_PWM0CTL_IDLESTATE BITP_TMR_PWMCTL_IDLESTATE
38 #define BITP_TMR_RGB_PWM0CTL_MATCH BITP_TMR_PWMCTL_MATCH
39 #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
40 #define BITM_TMR_RGB_STAT_PDOK BITM_TMR_STAT_PDOK
41 #define BITM_TMR_RGB_STAT_TIMEOUT BITM_TMR_STAT_TIMEOUT
42 #define BITM_TMR_RGB_STAT_CAPTURE BITM_TMR_STAT_CAPTURE
43 #define BITM_TMR_RGB_CLRINT_EVTCAPT BITM_TMR_CLRINT_EVTCAPT
44 #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
45 #define BITM_TMR_RGB_CTL_RLD BITM_TMR_CTL_RLD
46 #endif /*__ADUCM302x__*/
47 
48 /* CTL register static configuration */
49 static uint16_t aTimerCtlConfig[] =
50 {
51  (TMR0_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
52  (TMR0_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
53  (TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
54  (TMR0_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
55  (TMR0_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
56  (TMR0_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
57  (TMR0_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
58  (TMR0_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
59 
60  (TMR1_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
61  (TMR1_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
62  (TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
63  (TMR1_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
64  (TMR1_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
65  (TMR1_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
66  (TMR1_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
67  (TMR1_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
68 
69  (TMR2_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
70  (TMR2_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
71  (TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
72  (TMR2_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
73  (TMR2_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
74  (TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
75  (TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
76  (TMR2_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
77 
78 #if defined(__ADUCM4x50__)
79  (TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
80  (TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
81  (TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
82  (TMR3_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
83  (TMR3_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
84  (TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
85  (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
86  (TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
87 #endif
88 };
89 
90 /* LOAD register static configuration */
91 static uint16_t aTimerLoadConfig[] =
92 {
96 #if defined(__ADUCM4x50__)
98 #endif
99 };
100 
101 /* Asynchronous LOAD static configuraton */
102 static uint16_t aTimerALoadConfig[] =
103 {
107 #if defined(__ADUCM4x50__)
109 #endif
110 };
111 
112 /* EVENTSELECT static configuration */
113 #if defined(__ADUCM4x50__)
114 static uint16_t aTimerEventConfig[] =
115 {
120 };
121 #endif
122 
123 /* PWM CTL static configuration */
124 static uint16_t aTimerPwmCtlConfig[] =
125 {
126  (TMR0_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
127  (TMR0_CFG_ENABLE_PWM0_MATCH_MODE << BITP_TMR_RGB_PWM0CTL_MATCH),
128 
129  (TMR1_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
130  (TMR1_CFG_ENABLE_PWM0_MATCH_MODE << BITP_TMR_RGB_PWM0CTL_MATCH),
131 
132  (TMR2_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
133  (TMR2_CFG_ENABLE_PWM0_MATCH_MODE << BITP_TMR_RGB_PWM0CTL_MATCH),
134 
135 #if defined(__ADUCM4x50__)
136  (TMR3_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
137  (TMR3_CFG_ENABLE_PWM0_MATCH_MODE << BITP_TMR_RGB_PWM0CTL_MATCH),
138 
139  (TMR3_CFG_PWM1_IDLE_STATE << BITP_TMR_RGB_PWM1CTL_IDLESTATE) |
140  (TMR3_CFG_ENABLE_PWM1_MATCH_MODE << BITP_TMR_RGB_PWM1CTL_MATCH),
141 
142  (TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) |
143  (TMR3_CFG_ENABLE_PWM2_MATCH_MODE << BITP_TMR_RGB_PWM2CTL_MATCH),
144 #endif
145 };
146 
147 /* PWM MATCH static configuration */
148 static uint16_t aTimerPwmMatchConfig[] = {
152 #if defined(__ADUCM4x50__)
156 #endif
157 };
158 
159 
160 #endif /* ADI_TMR_DATA */
#define TMR2_CFG_MODE
#define TMR0_CFG_PWM0_MATCH_VALUE
#define TMR2_CFG_LOAD_VALUE
#define TMR2_CFG_ENABLE_PRESCALE_RESET
#define TMR0_CFG_MODE
#define TMR3_CFG_ENABLE_RELOADING
#define TMR3_CFG_ENABLE_PWM1_MATCH_MODE
#define TMR0_CFG_ENABLE_RELOADING
#define TMR3_CFG_PWM0_IDLE_STATE
#define TMR2_CFG_ENABLE_SYNC_BYPASS
#define TMR3_CFG_COUNT_UP
#define TMR3_CFG_ASYNC_LOAD_VALUE
#define TMR3_CFG_ENABLE_PRESCALE_RESET
#define TMR3_CFG_EVENT_CAPTURE
#define TMR1_CFG_LOAD_VALUE
#define TMR0_CFG_PWM0_IDLE_STATE
#define TMR1_CFG_PRESCALE_FACTOR
#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE
#define TMR2_CFG_COUNT_UP
#define TMR0_CFG_ENABLE_SYNC_BYPASS
#define TMR1_CFG_PWM0_MATCH_VALUE
#define TMR1_CFG_CLOCK_SOURCE
#define TMR1_CFG_ENABLE_RELOADING
#define TMR2_CFG_ENABLE_RELOADING
#define TMR2_CFG_PRESCALE_FACTOR
#define TMR3_CFG_PWM0_MATCH_VALUE
#define TMR1_CFG_EVENT_CAPTURE
#define TMR0_CFG_CLOCK_SOURCE
#define TMR1_CFG_PWM0_IDLE_STATE
#define TMR1_CFG_ENABLE_SYNC_BYPASS
#define TMR3_CFG_PWM2_IDLE_STATE
#define TMR0_CFG_ENABLE_PWM0_MATCH_MODE
#define TMR1_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_CLOCK_SOURCE
#define TMR2_CFG_PWM0_MATCH_VALUE
#define TMR3_CFG_PRESCALE_FACTOR
#define TMR3_CFG_ENABLE_EVENT_CAPTURE
#define TMR1_CFG_ENABLE_EVENT_CAPTURE
#define TMR3_CFG_ENABLE_SYNC_BYPASS
#define TMR2_CFG_PWM0_IDLE_STATE
#define TMR3_CFG_MODE
#define TMR3_CFG_PWM1_IDLE_STATE
#define TMR1_CFG_COUNT_UP
#define TMR1_CFG_ENABLE_PRESCALE_RESET
#define TMR0_CFG_COUNT_UP
#define TMR0_CFG_LOAD_VALUE
#define TMR0_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_ENABLE_EVENT_CAPTURE
#define TMR0_CFG_ENABLE_EVENT_CAPTURE
#define TMR3_CFG_ENABLE_PWM2_MATCH_MODE
#define TMR1_CFG_MODE
#define TMR3_CFG_LOAD_VALUE
#define TMR0_CFG_EVENT_CAPTURE
#define TMR2_CFG_ENABLE_PWM0_MATCH_MODE
#define TMR3_CFG_PWM2_MATCH_VALUE
#define TMR3_CFG_PWM1_MATCH_VALUE
#define TMR0_CFG_PRESCALE_FACTOR
#define TMR2_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_EVENT_CAPTURE
#define TMR0_CFG_ENABLE_PRESCALE_RESET
#define TMR3_CFG_CLOCK_SOURCE
#define TMR3_CFG_ENABLE_PWM0_MATCH_MODE