25 #include <adi_callback.h> 26 #include <adi_pwr_config.h> 27 #include <rtos_map/adi_rtos_map.h> 28 #include <drivers/pwr/adi_pwr.h> 29 #include "adi_pwr_def.h" 30 #include <drivers/gpio/adi_gpio.h> 46 #pragma diag_suppress=Pm011,Pm073,Pm050,Pm140,Pm143,Pm057 56 extern uint32_t lfClock;
59 extern uint32_t hfClock;
60 extern uint32_t gpioClock;
62 static ADI_CALLBACK gpfCallbackFunction;
63 static void *gpPowcbParam = NULL;
64 static uint32_t gnLowPowerIntOccFlag = 0u;
80 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
82 pADI_CLKG0_OSC->CTL = OSCCTRL_CONFIG_VALUE;
84 gpfCallbackFunction = NULL;
85 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
88 pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_HFOSC_EN;
91 while ((pADI_CLKG0_OSC->CTL & (1U << BITP_CLKG_OSC_CTL_HFOSC_OK)) == 0u)
96 pADI_CLKG0_CLK->CTL0 &= ~(BITM_CLKG_CLK_CTL0_CLKMUX);
99 pADI_CLKG0_CLK->CTL0 = CLOCK_CTL0_CONFIG_VALUE;
100 pADI_CLKG0_CLK->CTL1 = CLOCK_CTL1_CONFIG_VALUE;
102 #if defined(__ADUCM4x50__) 103 pADI_CLKG0_CLK->CTL2 = CLOCK_CTL2_CONFIG_VALUE;
106 pADI_CLKG0_CLK->CTL3 = CLOCK_CTL3_CONFIG_VALUE;
108 pADI_CLKG0_CLK->CTL5 = CLOCK_CTL5_CONFIG_VALUE;
113 pADI_PMG0->IEN = PWM_INTERRUPT_CONFIG;
114 pADI_PMG0->PWRMOD = PWM_PWRMOD_CONFIG;
115 pADI_PMG0->CTL1 = PWM_HPBUCK_CONTROL;
119 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
120 pADI_CLKG0_OSC->CTL &= ~BITM_CLKG_OSC_CTL_HFX_EN;
122 NVIC_EnableIRQ(PMG0_VREG_OVR_IRQn);
123 NVIC_EnableIRQ(PMG0_BATT_RANGE_IRQn);
125 NVIC_EnableIRQ(CLKG_XTAL_OSC_EVT_IRQn);
126 NVIC_EnableIRQ(CLKG_PLL_EVT_IRQn);
167 const ADI_CALLBACK pfCallback,
173 if(pfCallback == NULL)
179 gpfCallbackFunction = pfCallback;
180 gpPowcbParam = pcbParam;
199 if(ExtClkFreq > MAXIMUM_EXT_CLOCK)
204 gpioClock = ExtClkFreq;
222 ADI_INT_STATUS_ALLOC();
231 #if defined(__ADUCM4x50__) 245 ADI_ENTER_CRITICAL_REGION();
246 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_PLL_IPSEL);
248 pADI_CLKG0_CLK->CTL0 = tmp;
249 ADI_EXIT_CRITICAL_REGION();
269 ADI_INT_STATUS_ALLOC();
288 ADI_ENTER_CRITICAL_REGION();
290 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
291 tmp = (pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFCLK_MUX);
293 pADI_CLKG0_OSC->CTL = tmp;
295 ADI_EXIT_CRITICAL_REGION();
317 ADI_INT_STATUS_ALLOC();
335 ADI_ENTER_CRITICAL_REGION();
337 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_RCLKMUX);
339 pADI_CLKG0_CLK->CTL0 = tmp;
341 ADI_EXIT_CRITICAL_REGION();
361 ADI_INT_STATUS_ALLOC();
379 ADI_ENTER_CRITICAL_REGION();
381 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKMUX);
383 pADI_CLKG0_CLK->CTL0 = tmp;
385 ADI_EXIT_CRITICAL_REGION();
411 if(pExtClock == NULL)
416 *pExtClock = gpioClock;
441 if ((0u == hfClock) || (0u == lfClock))
455 nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
460 nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
472 *pClock = (src/nDiv);
494 ADI_INT_STATUS_ALLOC();
496 mask = (uint16_t)eClockGate;
498 ADI_ENTER_CRITICAL_REGION();
501 if (bEnable ==
true) {
504 pADI_CLKG0_CLK->CTL5 &= ~mask;
507 pADI_CLKG0_CLK->CTL5 |= mask;
511 ADI_EXIT_CRITICAL_REGION();
538 ADI_INT_STATUS_ALLOC();
549 if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
555 pdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
562 if ((pdiv % hdiv) != 0u)
568 mask = BITM_CLKG_CLK_CTL1_HCLKDIVCNT;
569 value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
576 if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
583 hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
589 if ((pdiv % hdiv) != 0u)
594 mask = BITM_CLKG_CLK_CTL1_PCLKDIVCNT;
595 value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
601 if ((nDiv > ACLK_MAX_DIV_VALUE) || (nDiv < ACLK_MIN_DIV_VALUE))
608 hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
614 if ((pdiv % hdiv) != 0u)
620 mask = BITM_CLKG_CLK_CTL1_ACLKDIVCNT;
621 value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
630 ADI_ENTER_CRITICAL_REGION();
634 tmp = pADI_CLKG0_CLK->CTL1;
637 pADI_CLKG0_CLK->CTL1 = tmp;
640 ADI_EXIT_CRITICAL_REGION();
664 volatile uint32_t *pReg = NULL;
666 ADI_INT_STATUS_ALLOC();
676 val = (1u << BITP_CLKG_OSC_CTL_HFX_EN);
677 pReg = &pADI_CLKG0_OSC->CTL;
678 nMask = BITM_CLKG_OSC_CTL_HFX_OK;
682 val = (1u << BITP_CLKG_OSC_CTL_LFX_EN);
683 pReg = &pADI_CLKG0_OSC->CTL;
684 nMask = BITM_CLKG_OSC_CTL_LFX_OK;
688 val = (1u << BITP_CLKG_OSC_CTL_HFOSC_EN);
689 pReg = &pADI_CLKG0_OSC->CTL;
690 nMask = BITM_CLKG_OSC_CTL_HFOSC_OK;
694 val = (1u << BITP_CLKG_CLK_CTL3_SPLLEN);
695 pReg = &pADI_CLKG0_CLK->CTL3;
696 nMask = BITM_CLKG_CLK_CTL3_SPLLEN;
699 #if (ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO == 1) 718 ADI_ENTER_CRITICAL_REGION();
720 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
727 uint32_t read_status;
729 read_status = ((*pREG_CLKG0_CLK_STAT0 & BITM_CLKG_CLK_STAT0_SPLL)>>BITP_CLKG_CLK_STAT0_SPLL);
730 }
while (read_status != 1u);
738 ADI_EXIT_CRITICAL_REGION();
740 if((nMask !=0u) && (bEnable ==
true))
742 while(0u== (pADI_CLKG0_OSC->CTL & nMask)){}
765 uint32_t val = pADI_CLKG0_OSC->CTL;
779 if ((val & BITM_CLKG_OSC_CTL_HFOSC_EN) != 0u)
782 if ((val & BITM_CLKG_OSC_CTL_HFOSC_OK) != 0u)
794 if ((val & BITM_CLKG_OSC_CTL_HFX_EN) != 0u)
797 if ((val & BITM_CLKG_OSC_CTL_HFX_OK) != 0u)
809 if ((val & BITM_CLKG_OSC_CTL_LFX_EN) != 0u)
812 if ((val & BITM_CLKG_OSC_CTL_LFX_OK) != 0u)
825 if ((val & BITM_CLKG_OSC_CTL_LFOSC_OK) != 0u)
861 ADI_INT_STATUS_ALLOC();
862 volatile uint32_t *pReg = NULL;
867 #if defined(__ADUCM4x50__) 870 pReg = &pADI_CLKG0_OSC->CTL;
876 pReg = &pADI_CLKG0_OSC->CTL;
881 pReg = &pADI_CLKG0_CLK->CTL0;
886 pReg = &pADI_CLKG0_CLK->CTL0;
891 pReg = &pADI_CLKG0_CLK->CTL3;
898 ADI_ENTER_CRITICAL_REGION();
904 tmp |= (uint32_t)eIrq;
908 tmp &= ~((uint32_t)eIrq);
912 if(pReg == &pADI_CLKG0_OSC->CTL)
914 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
918 ADI_EXIT_CRITICAL_REGION();
944 uint32_t val, cfg = 0u;
945 uint8_t nTempDivFactor = nDivFactor, nTempMulFactor = nMulFactor;
946 ADI_INT_STATUS_ALLOC();
950 if (((nMulFactor & ~0x3Fu) != 0u) || ((nDivFactor & ~0x3Fu) != 0u))
956 if((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX) ==
963 if(nTempDivFactor < MINIMUM_PLL_DIVIDER)
965 nTempDivFactor = MINIMUM_PLL_DIVIDER;
967 if(nTempMulFactor < MINIMUM_PLL_MULTIPLIER)
969 nTempMulFactor = MINIMUM_PLL_MULTIPLIER;
972 cfg = (((uint32_t)nTempDivFactor) << BITP_CLKG_CLK_CTL3_SPLLMSEL)|( ((uint32_t) nTempMulFactor) << BITP_CLKG_CLK_CTL3_SPLLNSEL);
976 cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLDIV2);
980 cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLMUL2);
984 ADI_ENTER_CRITICAL_REGION();
986 val = pADI_CLKG0_CLK->CTL3;
987 val &= ~( BITM_CLKG_CLK_CTL3_SPLLMUL2 | BITM_CLKG_CLK_CTL3_SPLLMSEL | BITM_CLKG_CLK_CTL3_SPLLDIV2 | BITM_CLKG_CLK_CTL3_SPLLNSEL);
989 pADI_CLKG0_CLK->CTL3 = val;
992 ADI_EXIT_CRITICAL_REGION();
1014 ADI_INT_STATUS_ALLOC();
1023 ADI_ENTER_CRITICAL_REGION();
1026 pADI_PMG0->IEN |= (uint32_t)eIrq;
1030 pADI_PMG0->IEN &= ~(uint32_t)(eIrq);
1032 ADI_EXIT_CRITICAL_REGION();
1052 volatile uint32_t nDelay = 0xFFFFFFu;
1056 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1058 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_EN);
1062 if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
1074 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1076 pADI_CLKG0_OSC->CTL |= (BITM_CLKG_OSC_CTL_LFX_BYP);
1081 if(((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK)== BITM_CLKG_OSC_CTL_LFX_OK))
1098 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1100 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_BYP);
1104 if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
1122 #if defined(__ADUCM4x50__) 1136 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1140 pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_AUTSW_EN;
1144 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_AUTSW_EN);
1166 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1170 pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN;
1174 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN);
1201 tmp = (pADI_CLKG0_CLK->CTL2 & ~BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
1202 tmp |= ((uint32_t) eDivFactor << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
1203 pADI_CLKG0_CLK->CTL2 = tmp;
1233 pADI_CLKG0_CLK->CTL2 |= BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN;
1237 pADI_CLKG0_CLK->CTL2 &= ~(BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN);
1261 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKOUT);
1262 tmp |= ((uint32_t)eClockOutput << BITP_CLKG_CLK_CTL0_CLKOUT);
1263 pADI_CLKG0_CLK->CTL0 = tmp;
1283 pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE;
1287 pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE);
1309 pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LD_MODE;
1313 pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LD_MODE);
1333 pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCKEN;
1337 pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCKEN);
1372 tmp = (pADI_PMG0->IEN & ~BITM_PMG_IEN_RANGEBAT);
1373 tmp |= ((uint32_t)eRange << BITP_PMG_IEN_RANGEBAT);
1374 pADI_PMG0->IEN = tmp;
1384 void PLL_Int_Handler(
void)
1391 uint32_t nStatus = (pADI_CLKG0_CLK->STAT0 &
1392 (BITM_CLKG_CLK_STAT0_SPLLUNLK | BITM_CLKG_CLK_STAT0_SPLLLK));
1395 if(gpfCallbackFunction != NULL)
1397 if((nStatus & BITM_CLKG_CLK_STAT0_SPLLUNLK ) != 0u)
1402 else if((nStatus & BITM_CLKG_CLK_STAT0_SPLLLK) != 0u)
1414 pADI_CLKG0_CLK->STAT0 = nStatus;
1422 void Crystal_osc_Int_Handler(
void)
1429 uint32_t nClkStatus = (pADI_CLKG0_CLK->STAT0 &
1430 (BITM_CLKG_CLK_STAT0_HFXTALNOK |
1431 BITM_CLKG_CLK_STAT0_HFXTALOK |
1432 BITM_CLKG_CLK_STAT0_LFXTALOK |
1433 BITM_CLKG_CLK_STAT0_LFXTALNOK));
1434 #if defined(__ADUCM4x50__) 1436 uint32_t nOscStatus = (pADI_CLKG0_OSC->CTL & (BITM_CLKG_OSC_CTL_LFX_FAIL_STA |
1437 BITM_CLKG_OSC_CTL_ROOT_FAIL_STA |
1438 BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA |
1439 BITM_CLKG_OSC_CTL_LFX_AUTSW_STA ));
1442 uint32_t nEvent = 0u;
1445 if(gpfCallbackFunction != NULL)
1448 if(nClkStatus != 0u)
1456 if(nEvent != 0u) { gpfCallbackFunction( gpPowcbParam, nEvent, (
void *)0u); }
1459 #if defined(__ADUCM4x50__) 1461 else if(nOscStatus != 0u)
1464 if( (nOscStatus & BITM_CLKG_OSC_CTL_LFX_FAIL_STA) != 0u)
1470 if((nOscStatus & BITM_CLKG_OSC_CTL_LFX_AUTSW_STA) != 0u)
1477 else if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_FAIL_STA) != 0u)
1483 if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA) != 0u)
1502 if(nClkStatus != 0u)
1504 pADI_CLKG0_CLK->STAT0 = nClkStatus;
1506 #if defined(__ADUCM4x50__) 1507 else if(nOscStatus != 0u)
1510 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1513 pADI_CLKG0_OSC->CTL |= nOscStatus;
1527 void Battery_Voltage_Int_Handler(
void)
1530 uint32_t nStatus = pADI_PMG0->PSM_STAT;
1532 if ((nStatus & BITM_PMG_PSM_STAT_VBATUNDR) != 0u)
1534 if(gpfCallbackFunction != NULL)
1536 gpfCallbackFunction( gpPowcbParam, (uint32_t)nStatus, (
void *)0);
1538 pADI_PMG0->PSM_STAT |= (BITM_PMG_PSM_STAT_VBATUNDR);
1546 void Vreg_over_Int_Handler(
void)
1549 uint32_t nStatus = pADI_PMG0->PSM_STAT;
1551 if(gpfCallbackFunction != NULL)
1553 if ((nStatus & BITM_PMG_PSM_STAT_VREGOVR) != 0u)
1557 if ((nStatus & BITM_PMG_PSM_STAT_VREGUNDR) != 0u)
1562 pADI_PMG0->PSM_STAT |= (nStatus &(BITM_PMG_PSM_STAT_VREGOVR | BITM_PMG_PSM_STAT_VREGUNDR));
1688 uint32_t
volatile * pnInterruptOccurred,
1689 const uint8_t PriorityMask
1692 uint32_t savedPriority;
1693 uint32_t scrSetBits = 0u;
1694 uint32_t scrClrBits = 0u;
1696 uint32_t savedDMA_STAT;
1697 ADI_INT_STATUS_ALLOC();
1702 if ((PriorityMask & ~((1u << __NVIC_PRIO_BITS) - 1u)) != 0u)
1710 if(NULL == pnInterruptOccurred) {
1711 scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk;
1714 pnInterruptOccurred = &gnLowPowerIntOccFlag;
1718 switch (PowerMode) {
1724 scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
1728 scrSetBits |= BITM_NVIC_INTCON0_SLEEPDEEP;
1734 scrSetBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
1743 ADI_ENTER_CRITICAL_REGION();
1747 pADI_PMG0->PWRKEY = ADI_PMG_KEY;
1750 pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode );
1754 SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits);
1757 savedPriority = __get_BASEPRI();
1768 savedWDT = pADI_WDT0->CTL;
1771 savedDMA_STAT = pADI_DMA0->STAT;
1774 __set_BASEPRI((uint32_t)PriorityMask << (8u -__NVIC_PRIO_BITS));
1777 while (0u == *pnInterruptOccurred) {
1793 ADI_EXIT_CRITICAL_REGION();
1795 ADI_ENTER_CRITICAL_REGION();
1801 (*pnInterruptOccurred)--;
1804 __set_BASEPRI(savedPriority);
1807 pADI_WDT0->CTL = savedWDT;
1810 if (savedDMA_STAT & BITM_DMA_STAT_MEN) {
1811 pADI_DMA0->CFG = BITM_DMA_CFG_MEN;
1815 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
1819 ADI_EXIT_CRITICAL_REGION();
1841 ADI_INT_STATUS_ALLOC();
1847 if (NULL == pnInterruptOccurred) {
1849 pnInterruptOccurred = &gnLowPowerIntOccFlag;
1852 ADI_ENTER_CRITICAL_REGION();
1855 pADI_PMG0->PWRMOD &= (uint32_t) (~BITM_PMG_PWRMOD_MODE);
1858 SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT_Msk | SCB_SCR_SLEEPDEEP_Msk);
1861 ADI_EXIT_CRITICAL_REGION();
1865 (*pnInterruptOccurred)++;
ADI_PWR_RESULT adi_pwr_SetClockDivider(const ADI_CLOCK_ID eClockId, const uint16_t nDiv)
Sets the clock divide factor for an individual clock group.
ADI_PWR_RESULT adi_pwr_SetVoltageRange(const ADI_PWR_VOLTAGE_RANGE eRange)
To Monitor voltage range of battery.
ADI_PWR_RESULT adi_pwr_SetPLLClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets the input clock source for PLL multiplexer.
ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode(const ADI_PWR_HPBUCK_LD_MODE eLoadMode)
Set the HP Buck load mode.
void SystemCoreClockUpdate(void)
Update the clock.
ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(const ADI_PWR_PMG_IRQ eIrq, const bool bEnable)
Enable/Disable the power management interrupt.
ADI_PWR_RESULT adi_pwr_UpdateCoreClock(void)
Updates the internal SystemCoreClock variable with current core Clock retrieved from cpu registers.
ADI_PWR_RESULT adi_pwr_SetGPIOClockOutput(const ADI_CLOCK_OUTPUT_ID eClockOutput)
Set the clock output through the GPIO.
ADI_PWR_RESULT adi_pwr_EnableHPBuck(const bool bEnable)
Enables or disables the HP Buck.
ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode(const bool bEnable)
Enable or disable the HPBuck Low Power mode. The HPBUCK Low Power mode can be selected,...
ADI_PWR_RESULT adi_pwr_SetPll(uint8_t nDivFactor, const uint8_t nMulFactor, const bool bDiv2, const bool bMul2)
Program PLL frequency.
ADI_PWR_RESULT adi_pwr_EnableClockSource(const ADI_CLOCK_SOURCE_ID eClockSource, const bool bEnable)
To Enable/disable clock sources.
ADI_PWR_RESULT adi_pwr_EnterLowPowerMode(const ADI_PWR_POWER_MODE PowerMode, uint32_t volatile *pnInterruptOccurred, const uint8_t PriorityMask)
Puts the processor into given low power mode.
ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(uint32_t volatile *pnInterruptOccurred)
ADI_PWR_RESULT adi_pwr_GetExtClkFreq(uint32_t *pExtClock)
Gets the system external clock frequency. Gets the clock frequency of the source connected to the ext...
ADI_GPIO_RESULT adi_gpio_InputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
Enables/Disables the Input Drivers for GPIO Pin(s)
ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(const ADI_PWR_CLOCK_IRQ eIrq, const bool bEnable)
Enable/Disable the clock interrupt to monitor status of LFXTAL, HFXTAL and PLL.
ADI_PWR_RESULT adi_pwr_RegisterCallback(const ADI_CALLBACK pfCallback, void *pcbParam)
Registers or unregister the callback function.
ADI_PWR_RESULT adi_pwr_EnableClock(const ADI_CLOCK_GATE eClockGate, const bool bEnable)
Enable/disable individual peripheral clocks.
ADI_GPIO_RESULT adi_gpio_PullUpEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
Enables/Disables the Pull-Up for GPIO Pin(s)
ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass(const bool bEnable)
Enable/disable LFXTAL bypass mode.
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
ADI_PWR_RESULT adi_pwr_SetExtClkFreq(const uint32_t ExtClkFreq)
Sets the system external clock frequency.
ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch(const bool bEnable)
To enable/disable auto switching of root clock to HFOSC upon detection of Root clock failure....
ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor(const ADI_PWR_HFOSC_DIV eDivFactor)
Sets the HF Oscillator divide factor.
ADI_PWR_RESULT adi_pwr_SetRootClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets the source for the root clock multiplexer.
ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1(const bool bEnable)
Enable or disable the HF oscillator automatic divide by 1 during wakeup from Flexi mode.
ADI_PWR_RESULT adi_pwr_SetRefClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets clock source for the Reference clock multiplexer.
ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(ADI_PWR_WAKEUP_STATUS *peStatus)
Function to retrieve the wakeup from shut down mode status.
ADI_PWR_RESULT adi_pwr_GetClockStatus(const ADI_CLOCK_SOURCE_ID eClockSource, ADI_CLOCK_SOURCE_STATUS *peStatus)
Return the status of a clock source.
ADI_PWR_RESULT adi_pwr_Init(void)
ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch(const bool bEnable)
Enable/Disable the LFXTAL Fail Auto switch. Enables/Disable automatic Switching of the LF Mux to LF O...
ADI_PWR_RESULT adi_pwr_SetLFClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets the input clock for low frequency clock multiplexer.