18 #include <adi_tmr_config.h> 19 #include <drivers/tmr/adi_tmr.h> 22 #if defined(__ADUCM302x__) 23 #define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN 24 #define PWM0CTL PWMCTL 25 #define PWM0MATCH PWMMATCH 26 #define BITM_TMR_RGB_STAT_BUSY BITM_TMR_STAT_BUSY 27 #define BITM_TMR_RGB_CTL_EVTEN BITM_TMR_CTL_EVTEN 28 #define BITM_TMR_RGB_CTL_RSTEN BITM_TMR_CTL_RSTEN 29 #define BITP_TMR_RGB_CTL_RSTEN BITP_TMR_CTL_RSTEN 30 #define BITP_TMR_RGB_CTL_EVTEN BITP_TMR_CTL_EVTEN 31 #define BITP_TMR_RGB_CTL_PRE BITP_TMR_CTL_PRE 32 #define BITP_TMR_RGB_CTL_CLK BITP_TMR_CTL_CLK 33 #define BITP_TMR_RGB_CTL_MODE BITP_TMR_CTL_MODE 34 #define BITP_TMR_RGB_CTL_UP BITP_TMR_CTL_UP 35 #define BITP_TMR_RGB_CTL_RLD BITP_TMR_CTL_RLD 36 #define BITP_TMR_RGB_CTL_SYNCBYP BITP_TMR_CTL_SYNCBYP 37 #define BITP_TMR_RGB_PWM0CTL_IDLESTATE BITP_TMR_PWMCTL_IDLESTATE 38 #define BITP_TMR_RGB_PWM0CTL_MATCH BITP_TMR_PWMCTL_MATCH 39 #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT 40 #define BITM_TMR_RGB_STAT_PDOK BITM_TMR_STAT_PDOK 41 #define BITM_TMR_RGB_STAT_TIMEOUT BITM_TMR_STAT_TIMEOUT 42 #define BITM_TMR_RGB_STAT_CAPTURE BITM_TMR_STAT_CAPTURE 43 #define BITM_TMR_RGB_CLRINT_EVTCAPT BITM_TMR_CLRINT_EVTCAPT 44 #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT 45 #define BITM_TMR_RGB_CTL_RLD BITM_TMR_CTL_RLD 49 static uint16_t aTimerCtlConfig[] =
78 #if defined(__ADUCM4x50__) 91 static uint16_t aTimerLoadConfig[] =
96 #if defined(__ADUCM4x50__) 102 static uint16_t aTimerALoadConfig[] =
107 #if defined(__ADUCM4x50__) 113 #if defined(__ADUCM4x50__) 114 static uint16_t aTimerEventConfig[] =
124 static uint16_t aTimerPwmCtlConfig[] =
135 #if defined(__ADUCM4x50__) 148 static uint16_t aTimerPwmMatchConfig[] = {
152 #if defined(__ADUCM4x50__)
#define TMR0_CFG_PWM0_MATCH_VALUE
#define TMR2_CFG_LOAD_VALUE
#define TMR2_CFG_ENABLE_PRESCALE_RESET
#define TMR3_CFG_ENABLE_RELOADING
#define TMR3_CFG_ENABLE_PWM1_MATCH_MODE
#define TMR0_CFG_ENABLE_RELOADING
#define TMR3_CFG_PWM0_IDLE_STATE
#define TMR2_CFG_ENABLE_SYNC_BYPASS
#define TMR3_CFG_COUNT_UP
#define TMR3_CFG_ASYNC_LOAD_VALUE
#define TMR3_CFG_ENABLE_PRESCALE_RESET
#define TMR3_CFG_EVENT_CAPTURE
#define TMR1_CFG_LOAD_VALUE
#define TMR0_CFG_PWM0_IDLE_STATE
#define TMR1_CFG_PRESCALE_FACTOR
#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE
#define TMR2_CFG_COUNT_UP
#define TMR0_CFG_ENABLE_SYNC_BYPASS
#define TMR1_CFG_PWM0_MATCH_VALUE
#define TMR1_CFG_CLOCK_SOURCE
#define TMR1_CFG_ENABLE_RELOADING
#define TMR2_CFG_ENABLE_RELOADING
#define TMR2_CFG_PRESCALE_FACTOR
#define TMR3_CFG_PWM0_MATCH_VALUE
#define TMR1_CFG_EVENT_CAPTURE
#define TMR0_CFG_CLOCK_SOURCE
#define TMR1_CFG_PWM0_IDLE_STATE
#define TMR1_CFG_ENABLE_SYNC_BYPASS
#define TMR3_CFG_PWM2_IDLE_STATE
#define TMR0_CFG_ENABLE_PWM0_MATCH_MODE
#define TMR1_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_CLOCK_SOURCE
#define TMR2_CFG_PWM0_MATCH_VALUE
#define TMR3_CFG_PRESCALE_FACTOR
#define TMR3_CFG_ENABLE_EVENT_CAPTURE
#define TMR1_CFG_ENABLE_EVENT_CAPTURE
#define TMR3_CFG_ENABLE_SYNC_BYPASS
#define TMR2_CFG_PWM0_IDLE_STATE
#define TMR3_CFG_PWM1_IDLE_STATE
#define TMR1_CFG_COUNT_UP
#define TMR1_CFG_ENABLE_PRESCALE_RESET
#define TMR0_CFG_COUNT_UP
#define TMR0_CFG_LOAD_VALUE
#define TMR0_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_ENABLE_EVENT_CAPTURE
#define TMR0_CFG_ENABLE_EVENT_CAPTURE
#define TMR3_CFG_ENABLE_PWM2_MATCH_MODE
#define TMR3_CFG_LOAD_VALUE
#define TMR0_CFG_EVENT_CAPTURE
#define TMR2_CFG_ENABLE_PWM0_MATCH_MODE
#define TMR3_CFG_PWM2_MATCH_VALUE
#define TMR3_CFG_PWM1_MATCH_VALUE
#define TMR0_CFG_PRESCALE_FACTOR
#define TMR2_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_EVENT_CAPTURE
#define TMR0_CFG_ENABLE_PRESCALE_RESET
#define TMR3_CFG_CLOCK_SOURCE
#define TMR3_CFG_ENABLE_PWM0_MATCH_MODE