15 #ifndef ADI_RTC_DATA_C_ 16 #define ADI_RTC_DATA_C_ 19 #include "adi_rtc_def.h" 21 static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] =
24 (ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL
27 (ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL,
32 static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
67 #if defined(__ADUCM302x__) 69 #elif defined(__ADUCM4x50__) 134 #if defined(__ADUCM4x50__) 153 #elif defined(__ADUCM302x__) 162 #error RTC driver not ported to this processor 168 #if defined(__ADUCM302x__) 169 RTC1_CFG_SS1_AUTO_RELOAD_VALUE,
170 #elif defined(__ADUCM4x50__) 171 #if !defined(RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH) ||!defined(RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW)\ 172 ||!defined(RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH)||!defined(RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW)\ 173 ||!defined(RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH)||!defined(RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW) 174 #error "update Autoreload register macro in adi_rtc_config.h to the latest version" 186 #if !defined( RTC1_CFG_CR5SSS_OC1SMPEN )||!defined(RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN )\ 187 ||!defined( RTC1_CFG_CR5SSS_OC2SMPEN )||!defined( RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN )\ 188 ||!defined(RTC1_CFG_CR5SSS_OC3SMPEN )||!defined( RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN ) 189 #error "update CR5SSS register macro in adi_rtc_config.h to the latest version" 199 #if !defined(RTC1_CFG_CR6SSS_OC1SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC1SMPONRE )\ 200 ||!defined( RTC1_CFG_CR6SSS_OC2SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC2SMPONRE )\ 201 ||!defined(RTC1_CFG_CR6SSS_OC3SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC3SMPONRE ) 202 #error "update CR6SSS register macro in adi_rtc_config.h to the latest version" 212 #if !defined(RTC1_CFG_CR7SSS_OC1SMPEXP )||!defined(RTC1_CFG_CR7SSS_OC1SMPPTRN )\ 213 ||!defined( RTC1_CFG_CR7SSS_OC2SMPEXP )||!defined(RTC1_CFG_CR7SSS_OC2SMPPTRN )\ 214 ||!defined(RTC1_CFG_CR7SSS_OC3SMPEXP )||!defined( RTC1_CFG_CR7SSS_OC3SMPPTRN ) 215 #error "update CR7SSS register macro in adi_rtc_config.h to the latest version" 225 #if !defined(RTC1_CFG_GPMUX0_OC1GPIN0SEL)||!defined(RTC1_CFG_GPMUX0_OC1GPIN1SEL )\ 226 ||!defined(RTC1_CFG_GPMUX0_OC1GPIN2SEL)||!defined(RTC1_CFG_GPMUX0_OC2GPIN0SEL )\ 227 ||!defined(RTC1_CFG_GPMUX0_OC2GPIN1SEL) 228 #error "update GPMUX0 register macro in adi_rtc_config.h to the latest version" 237 #if !defined(RTC1_CFG_GPMUX1_OC2GPIN2SEL )||!defined(RTC1_CFG_GPMUX1_OC3GPIN0SEL )\ 238 ||!defined(RTC1_CFG_GPMUX1_OC3GPIN1SEL )||!defined(RTC1_CFG_GPMUX1_OC3GPIN2SEL )\ 239 ||!defined(RTC1_CFG_GPMUX1_OC1DIFFOUT)||!defined( RTC1_CFG_GPMUX1_OC3DIFFOUT ) 240 #error "update GPMUX1 register macro in adi_rtc_config.h to the latest version" #define RTC1_CFG_GPMUX0_OC1GPIN2SEL
#define RTC1_CFG_SS2_AUTO_RELOADING_ENABLE
#define RTC1_CFG_IC4_EDGE_POLARITY
#define RTC1_CFG_SS2_MASK_ENABLE
#define RTC1_CFG_CR5SSS_OC1SMPEN
#define RTC1_CFG_GPMUX0_OC1GPIN0SEL
#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT
#define RTC1_CFG_ENABLE_ALARM
#define RTC1_CFG_ENABLE_ALARM_INTERRUPT
#define RTC1_CFG_SS3_ENABLE
#define RTC1_CFG_ENABLE_TRIM
#define RTC1_CFG_CR7SSS_OC1SMPPTRN
#define RTC0_CFG_ENABLE_ALARM_INTERRUPT
#define RTC1_CFG_IC0_INT_ENABLE
#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD
#define RTC1_CFG_CR7SSS_OC1SMPEXP
#define RTC1_CFG_TRIM_INTERVAL
#define RTC0_CFG_ENABLE_ALARM
#define RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN
#define RTC1_CFG_IC3_ENABLE
#define RTC1_CFG_SS3_MASK_ENABLE
#define RTC1_CFG_GPMUX0_OC2GPIN0SEL
#define RTC1_CFG_CR6SSS_OC3SMPONRE
#define RTC1_CFG_IC4_INT_ENABLE
#define RTC1_CFG_ENABLE_ISO_INTERRUPT
#define RTC0_CFG_TRIM_INTERVAL
#define RTC1_CFG_ALARM_VALUE_1
#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE
#define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH
#define RTC1_CFG_GPMUX0_OC2GPIN1SEL
#define RTC1_CFG_TRIM_OPERATION
#define RTC1_CFG_GPMUX1_OC3GPIN0SEL
#define RTC1_CFG_ENABLE_MOD60_ALARM
#define RTC1_CFG_CR5SSS_OC3SMPEN
#define RTC1_CFG_SS1_ENABLE
#define RTC1_CFG_SS4_INT_ENABLE
#define RTC0_CFG_ENABLE_TRIM
#define RTC1_CFG_IC0_ENABLE
#define RTC1_CFG_CR5SSS_OC2SMPEN
#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT
#define RTC1_CFG_GPMUX0_OC1GPIN1SEL
#define RTC1_CFG_ALARM_VALUE_2
#define RTC1_CFG_IC2_ENABLE
#define RTC1_CFG_IC3_INT_ENABLE
#define RTC1_CFG_ENABLE_COUNT_INTERRUPT
#define RTC0_CFG_TRIM_OPERATION
#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT
#define RTC1_CFG_SS4_MASK_ENABLE
#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW
#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT
#define RTC1_CFG_CR7SSS_OC2SMPPTRN
#define RTC1_CFG_COUNT_VALUE_0
#define RTC1_CFG_SS1_MASK_ENABLE
#define RTC1_CFG_CR6SSS_OC3SMPONFE
#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT
#define RTC1_CFG_GPMUX1_OC3GPIN2SEL
#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT
#define RTC1_CFG_ALARM_VALUE_0
#define RTC0_CFG_COUNT_VALUE_0
#define RTC1_CFG_CR6SSS_OC2SMPONFE
#define RTC1_CFG_SS2_ENABLE
#define RTC0_CFG_ALARM_VALUE_1
#define RTC1_CFG_SS4_ENABLE
#define RTC1_CFG_IC2_INT_ENABLE
#define RTC1_CFG_IC3_EDGE_POLARITY
#define RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN
#define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW
#define RTC1_CFG_POW2_TRIM_INTERVAL
#define RTC0_CFG_ALARM_VALUE_0
#define RTC1_CFG_IC0_EDGE_POLARITY
#define RTC1_CFG_CR7SSS_OC3SMPEXP
#define RTC1_CFG_TRIM_VALUE
#define RTC1_CFG_GPMUX1_OC3GPIN1SEL
#define RTC1_CFG_IC_OVER_WRITE_ENABLE
#define RTC1_CFG_SS2_INT_ENABLE
#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT
#define RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN
#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT
#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT
#define RTC0_CFG_COUNT_VALUE_1
#define RTC1_CFG_PRESCALE
#define RTC1_CFG_SS3_AUTO_RELOADING_ENABLE
#define RTC1_CFG_COUNT_VALUE_1
#define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW
#define RTC1_CFG_CR7SSS_OC3SMPPTRN
#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT
#define RTC1_CFG_GPMUX1_OC2GPIN2SEL
#define RTC0_CFG_TRIM_VALUE
#define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH
#define RTC1_CFG_CR7SSS_OC2SMPEXP
#define RTC1_CFG_IC2_EDGE_POLARITY
#define RTC1_CFG_ENABLE_TRIM_INTERRUPT
#define RTC0_CFG_POW2_TRIM_INTERVAL
#define RTC1_CFG_CR6SSS_OC2SMPONRE
#define RTC1_CFG_IC4_ENABLE
#define RTC1_CFG_SS3_INT_ENABLE
#define RTC1_CFG_SS1_INT_ENABLE
#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH
#define RTC1_CFG_GPMUX1_OC1DIFFOUT
#define RTC1_CFG_SS1_MASK_VALUE
#define RTC1_CFG_GPMUX1_OC3DIFFOUT
#define RTC1_CFG_CR6SSS_OC1SMPONFE
#define RTC1_CFG_CR6SSS_OC1SMPONRE