26 #include <drivers/uart/adi_uart.h> 27 #include <drivers/dma/adi_dma.h> 28 #include "adi_uart_def.h" 29 #include <adi_cyclecount.h> 61 #pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm008,Pm026 70 static ADI_UART_DEVICE_INFO uart_device_info[ ] =
77 (IRQn_Type)INTR_UART0_EVT,
81 #if defined (__ADUCM4x50__) 87 (IRQn_Type)INTR_UART1_EVT,
94 static const ADI_UART_CONFIG gUARTCfg[ ] =
110 ((uint32_t)BITM_UART_FBR_FBEN)),
130 #if defined (__ADUCM4x50__) 145 ((uint32_t)BITM_UART_FBR_FBEN)),
168 static const uint8_t sFifoTriggers[] = {1u, 4u, 8u, 14u};
173 #define ADI_UART_NUM_DEVICES (sizeof(uart_device_info)/sizeof(ADI_UART_DEVICE_INFO)) 177 extern void UART0_Int_Handler(
void);
178 extern void UART1_Int_Handler(
void);
179 extern void DMA_UART0_TX_Int_Handler(
void);
180 extern void DMA_UART0_RX_Int_Handler(
void);
182 #if defined (__ADUCM4x50__) 183 extern void DMA_UART1_TX_Int_Handler(
void);
184 extern void DMA_UART1_RX_Int_Handler(
void);
188 static void RxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg);
189 static void RxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
193 ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelRx->pFillBuffer->pNextBuffer;
194 uint32_t nEvent = 0u;
209 if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA ==
true))
211 hDevice->nHwError |= nEvent;
212 pNextBuff->bInUse =
false;
216 hDevice->nHwError |= nEvent;
220 static void TxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg);
221 static void TxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
225 ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelTx->pFillBuffer->pNextBuffer;
226 uint32_t nEvent = 0u;
240 if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA ==
true))
242 hDevice->nHwError |= nEvent;
243 pNextBuff->bInUse =
false;
248 hDevice->nHwError |= nEvent;
285 uint32_t
const nDeviceNum,
288 uint32_t
const nMemSize,
292 uint16_t regFifoTrig = 0u;
305 if(uart_device_info[nDeviceNum].hDevice != NULL)
317 assert(nMemSize == (
sizeof(ADI_UART_DEVICE) +
sizeof(ADI_UART_DATA_CHANNEL)));
327 assert(nMemSize == (
sizeof(ADI_UART_DEVICE) + (
sizeof(ADI_UART_DATA_CHANNEL)*2u)));
340 memset(pMemory, 0, nMemSize);
343 hDevice->pUartInfo = &uart_device_info[nDeviceNum];
348 hDevice->pUARTRegs = uart_device_info[nDeviceNum].pUartRegs;
351 hDevice->eDirection = eDirection;
357 pMemory = ((uint8_t *)pMemory +(
sizeof(ADI_UART_DEVICE)));
365 hDevice->pChannelTx = (ADI_UART_DATA_CHANNEL *)pMemory;
371 hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
372 hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
373 hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
380 hDevice->pChannelTx->pfSubmitBuffer = &uart_submittxbuffer;
382 hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1];
383 hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0];
395 pMemory = ((uint8_t *)pMemory +
sizeof(ADI_UART_DATA_CHANNEL));
400 hDevice->pChannelRx = (ADI_UART_DATA_CHANNEL *)pMemory;
406 hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
407 hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
408 hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
414 hDevice->pChannelRx->pfSubmitBuffer = &uart_submitrxbuffer;
416 hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1];
417 hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0];
428 uart_init(hDevice, nDeviceNum);
433 hDevice->bRxFifoEn = ((hDevice->pUARTRegs->FCR & BITM_UART_FCR_FIFOEN) > 0u);
434 regFifoTrig = ((hDevice->pUARTRegs->FCR & BITM_UART_FCR_RFTRIG) >> BITP_UART_FCR_RFTRIG);
436 hDevice->nRxFifoTrig = sFifoTriggers[regFifoTrig];
442 uart_device_info[nDeviceNum].hDevice = hDevice;
446 NVIC_ClearPendingIRQ(hDevice->pUartInfo->eIRQn);
447 NVIC_EnableIRQ(hDevice->pUartInfo->eIRQn);
450 NVIC_EnableIRQ(hDevice->pUartInfo->eDMATx);
451 NVIC_EnableIRQ(hDevice->pUartInfo->eDMARx);
492 if(((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) ||
493 ((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL)) ||
494 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL)) ||
495 (hDevice->bAutobaudInProgress ==
true))
502 hDevice->pUARTRegs->IEN = 0x00U;
505 NVIC_DisableIRQ(hDevice->pUartInfo->eDMARx);
506 NVIC_DisableIRQ(hDevice->pUartInfo->eDMATx);
509 NVIC_DisableIRQ(hDevice->pUartInfo->eIRQn);
524 hDevice->pUartInfo->hDevice = NULL;
565 uint32_t
const nBufSize,
590 if(hDevice->bAutobaudInProgress ==
true)
612 if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
619 if(nBufSize > DMA_TRANSFER_LIMIT)
621 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 625 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) && (ADI_UART_DMA_EXTENSION_ENABLE == 1) 626 if(hDevice->pChannelTx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
631 for(uint32_t cnt = 0u; cnt < (nBufSize-1u); cnt++)
633 if((pBuffer1[cnt].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT)
640 if((pBuffer1[nBufSize-1u].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_BASIC)
651 hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer;
654 hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize;
657 hDevice->pChannelTx->pFreeBuffer->nRemDoneTransfers = nBufSize;
662 hDevice->pChannelTx->pFreeBuffer->nIndex = 0U;
665 hDevice->pChannelTx->pFreeBuffer->bInUse =
true;
668 hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA;
671 hDevice->pChannelTx->bIsPrimNext =
true;
674 hDevice->pChannelTx->nFreeDescriptor = 2U;
679 pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
680 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 682 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
686 if(hDevice->pChannelTx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_INVALID)
688 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
691 if (nBufSize > DMA_TRANSFER_LIMIT)
694 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PING_PONG;
697 if (hDevice->pChannelTx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
704 hDevice->pChannelTx->pFreeBuffer->nCount = 4u * nBufSize;
707 hDevice->pChannelTx->pFreeBuffer->nRemDoneTransfers = 4u * nBufSize;
717 hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
728 hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
745 static void uart_submittxbuffer(
747 ADI_UART_BUFF_INFO *
const pBuffer
754 pADI_DMA0->SRCADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaTxChannelNum;
757 pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaTxChannelNum;
760 pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
763 pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMASRCEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
765 pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMADSTEND = (uint32_t)&hDevice->pUARTRegs->TX;
767 pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMACDC = ((uint32_t)
ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
770 (0u << DMA_BITP_CTL_R_POWER) |
771 ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) |
772 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
779 ADI_UART_DATA_CHANNEL* pChannel = hDevice->pChannelTx;
782 uint16_t nTransactions = 0;
791 uint32_t dstAddr = 0;
793 while(pBuffer->nCount > 0 && pChannel->nFreeDescriptor > 0)
795 if(pBuffer->nCount < 2*DMA_TRANSFER_LIMIT)
797 if(pBuffer->nCount > DMA_TRANSFER_LIMIT)
799 nTransactions = pBuffer->nCount/2;
803 nTransactions = pBuffer->nCount;
808 nTransactions = DMA_TRANSFER_LIMIT;
811 if (pChannel->bIsPrimNext)
814 pCCD = &pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum];
815 pChannel->bIsPrimNext =
false;
820 pCCD = &pAlternateCCD[hDevice->pUartInfo->dmaTxChannelNum];
821 pChannel->bIsPrimNext =
true;
825 pChannel->nFreeDescriptor--;
827 if (pBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
833 ((nTransactions-1) << DMA_BITP_CTL_N_MINUS_1) |
834 (pBuffer->nDmaMode<< DMA_BITP_CTL_CYCLE_CTL);
836 dstAddr = (uint32_t)&pAlternateCCD[hDevice->pUartInfo->dmaTxChannelNum].RESERVED;
845 ((nTransactions-1) << DMA_BITP_CTL_N_MINUS_1) |
846 (pBuffer->nDmaMode<< DMA_BITP_CTL_CYCLE_CTL);
848 dstAddr = (uint32_t)&hDevice->pUARTRegs->TX;
853 srcInc = 1u << ((nCfg & DMA_BITM_CTL_SRC_INC) >> DMA_BITP_CTL_SRC_INC);
856 pCCD->
DMASRCEND = (uint32_t)pBuffer->pStartAddress + ((nTransactions-1) + pBuffer->nIndex) * srcInc;
863 pBuffer->nCount -= nTransactions;
864 pBuffer->nIndex += nTransactions;
870 ADI_INT_STATUS_ALLOC();
871 ADI_ENTER_CRITICAL_REGION();
873 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAT);
874 ADI_EXIT_CRITICAL_REGION();
881 ADI_INT_STATUS_ALLOC();
882 ADI_ENTER_CRITICAL_REGION();
884 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ETBEI);
885 ADI_EXIT_CRITICAL_REGION();
926 uint32_t
const nBufSize,
951 if(hDevice->bAutobaudInProgress ==
true)
974 if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
983 if(nBufSize > DMA_TRANSFER_LIMIT)
985 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 990 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) && (ADI_UART_DMA_EXTENSION_ENABLE == 1) 991 if(hDevice->pChannelRx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
996 for(uint32_t cnt = 0u; cnt < (nBufSize-1u); cnt++)
998 if((pBuffer1[cnt].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT)
1005 if((pBuffer1[nBufSize-1u].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_BASIC)
1018 hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer;
1021 hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize;
1024 hDevice->pChannelRx->pFreeBuffer->nRemDoneTransfers = nBufSize;
1029 hDevice->pChannelRx->pFreeBuffer->nIndex = 0U;
1032 hDevice->pChannelRx->pFreeBuffer->bInUse =
true;
1035 hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA;
1038 hDevice->pChannelRx->bIsPrimNext =
true;
1041 hDevice->pChannelRx->nFreeDescriptor = 2;
1046 pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
1048 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 1050 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
1053 if(hDevice->pChannelRx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_INVALID)
1055 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
1058 if(nBufSize > DMA_TRANSFER_LIMIT)
1061 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PING_PONG;
1064 if(hDevice->pChannelRx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
1071 hDevice->pChannelRx->pFreeBuffer->nCount = 4u * nBufSize;
1074 hDevice->pChannelRx->pFreeBuffer->nRemDoneTransfers = 4u * nBufSize;
1084 hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
1096 hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
1113 static void uart_submitrxbuffer(
1115 ADI_UART_BUFF_INFO *
const pBuffer
1122 pADI_DMA0->DSTADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaRxChannelNum;
1125 pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaRxChannelNum;
1128 pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
1132 pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMASRCEND = (uint32_t)&hDevice->pUARTRegs->RX;
1134 pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMADSTEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
1136 pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMACDC = (uint32_t)(
ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_DST_INC) |
1139 (0u << DMA_BITP_CTL_R_POWER) |
1140 ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) |
1141 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1147 ADI_UART_DATA_CHANNEL* pChannel = hDevice->pChannelRx;
1150 uint16_t nTransactions = 0;
1156 uint32_t srcInc = 0;
1159 uint32_t dstInc = 0;
1162 uint32_t dstAddr = 0;
1165 uint32_t srcAddr = 0;
1167 while (pBuffer->nCount > 0 && pChannel->nFreeDescriptor > 0)
1169 if(pBuffer->nCount < 2*DMA_TRANSFER_LIMIT)
1171 if(pBuffer->nCount > DMA_TRANSFER_LIMIT)
1173 nTransactions = pBuffer->nCount/2;
1177 nTransactions = pBuffer->nCount;
1182 nTransactions = DMA_TRANSFER_LIMIT;
1185 if(pChannel->bIsPrimNext)
1188 pCCD= &pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum];
1189 pChannel->bIsPrimNext =
false;
1194 pCCD= &pAlternateCCD[hDevice->pUartInfo->dmaRxChannelNum];
1195 pChannel->bIsPrimNext =
true;
1199 pChannel->nFreeDescriptor--;
1201 if (pBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
1207 ((nTransactions-1) << DMA_BITP_CTL_N_MINUS_1) |
1208 (pBuffer->nDmaMode<< DMA_BITP_CTL_CYCLE_CTL);
1211 srcInc = 1u << ((nCfg & DMA_BITM_CTL_SRC_INC) >> DMA_BITP_CTL_SRC_INC);
1213 srcAddr = (uint32_t)pBuffer->pStartAddress + ((nTransactions-1) + pBuffer->nIndex) * srcInc;
1214 dstAddr = (uint32_t)&pAlternateCCD[hDevice->pUartInfo->dmaRxChannelNum].RESERVED;
1224 ((nTransactions-1) << DMA_BITP_CTL_N_MINUS_1) |
1225 (pBuffer->nDmaMode<< DMA_BITP_CTL_CYCLE_CTL);
1228 dstInc = 1u << ((nCfg & DMA_BITM_CTL_DST_INC) >> DMA_BITP_CTL_DST_INC);
1230 srcAddr = (uint32_t)&hDevice->pUARTRegs->RX;
1231 dstAddr = (uint32_t)pBuffer->pStartAddress + ((nTransactions-1) + pBuffer->nIndex) * dstInc;
1243 pBuffer->nCount -= nTransactions;
1244 pBuffer->nIndex += nTransactions;
1249 ADI_INT_STATUS_ALLOC();
1250 ADI_ENTER_CRITICAL_REGION();
1252 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAR);
1253 ADI_EXIT_CRITICAL_REGION();
1260 ADI_INT_STATUS_ALLOC();
1261 ADI_ENTER_CRITICAL_REGION();
1263 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
1264 ADI_EXIT_CRITICAL_REGION();
1296 void **
const ppBuffer,
1310 if(hDevice->pChannelTx->pActiveBuffer->pStartAddress == NULL)
1323 return(uart_getbuffer(hDevice, hDevice->pChannelTx, ppBuffer, pHwError));
1354 void **
const ppBuffer,
1368 if(hDevice->pChannelRx->pActiveBuffer->pStartAddress == NULL)
1381 return(uart_getbuffer(hDevice, hDevice->pChannelRx, ppBuffer, pHwError));
1403 ADI_UART_DATA_CHANNEL *pChannel,
1417 *ppBuffer = pChannel->pActiveBuffer->pStartAddress;
1420 pChannel->pActiveBuffer->pStartAddress = NULL;
1426 pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
1431 if(pChannel->pActiveBuffer->pStartAddress == NULL)
1437 if(hDevice->nHwError != 0u)
1440 *pHwError = hDevice->nHwError;
1443 hDevice->nHwError = 0u;
1492 void *
const pBuffer,
1493 uint32_t
const nBufSize,
1519 if(hDevice->bAutobaudInProgress ==
true)
1541 if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
1548 if(nBufSize > DMA_TRANSFER_LIMIT)
1550 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 1554 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) || (ADI_UART_DMA_EXTENSION_ENABLE == 1) 1555 if(hDevice->pChannelTx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
1560 for(uint32_t cnt = 0u; cnt < (nBufSize-1u); cnt++)
1562 if((pBuffer1[cnt].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT)
1569 if((pBuffer1[nBufSize-1u].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_BASIC)
1583 hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer;
1586 hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize;
1589 hDevice->pChannelTx->pFreeBuffer->nRemDoneTransfers = nBufSize;
1594 hDevice->pChannelTx->pFreeBuffer->nIndex = 0U;
1597 hDevice->pChannelTx->pFreeBuffer->bInUse =
true;
1600 hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA;
1603 hDevice->pChannelTx->bIsPrimNext =
true;
1606 hDevice->pChannelTx->nFreeDescriptor = 2U;
1611 pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
1612 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 1614 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
1617 if(hDevice->pChannelTx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_INVALID)
1619 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
1621 if (nBufSize > DMA_TRANSFER_LIMIT)
1624 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PING_PONG;
1627 if (hDevice->pChannelTx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
1634 hDevice->pChannelTx->pFreeBuffer->nCount = 4u * nBufSize;
1637 hDevice->pChannelTx->pFreeBuffer->nRemDoneTransfers = 4u * nBufSize;
1648 hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
1650 hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
1653 return(uart_PendForBuffer(hDevice, hDevice->pChannelTx, pHwError));
1692 void *
const pBuffer,
1693 uint32_t
const nBufSize,
1719 if(hDevice->bAutobaudInProgress ==
true)
1741 if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
1748 if(nBufSize > DMA_TRANSFER_LIMIT)
1750 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 1754 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) && (ADI_UART_DMA_EXTENSION_ENABLE == 1) 1755 if(hDevice->pChannelRx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
1760 for(uint32_t cnt = 0u; cnt < (nBufSize-1u); cnt++)
1762 if((pBuffer1[cnt].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT)
1769 if((pBuffer1[nBufSize-1u].DMACDC & DMA_BITM_CTL_CYCLE_CTL) != DMA_ENUM_CTL_CYCLE_CTL_BASIC)
1788 hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer;
1791 hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize;
1794 hDevice->pChannelRx->pFreeBuffer->nRemDoneTransfers = nBufSize;
1799 hDevice->pChannelRx->pFreeBuffer->nIndex = 0U;
1802 hDevice->pChannelRx->pFreeBuffer->bInUse =
true;
1805 hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA;
1808 hDevice->pChannelRx->bIsPrimNext =
true;
1811 hDevice->pChannelRx->nFreeDescriptor = 2;
1816 pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
1817 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 1819 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
1822 if(hDevice->pChannelRx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_INVALID)
1824 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
1827 if(nBufSize > DMA_TRANSFER_LIMIT)
1830 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PING_PONG;
1832 if(hDevice->pChannelRx->pFreeBuffer->nDmaMode == DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI)
1839 hDevice->pChannelRx->pFreeBuffer->nCount = 4u * nBufSize;
1842 hDevice->pChannelRx->pFreeBuffer->nRemDoneTransfers = 4u * nBufSize;
1854 hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
1856 hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
1859 return(uart_PendForBuffer(hDevice, hDevice->pChannelRx, pHwError));
1898 if(hDevice->bAutobaudInProgress ==
true)
1916 *pRX = hDevice->pUARTRegs->RX;
1938 ADI_UART_DATA_CHANNEL *pChannel,
1947 pChannel->pActiveBuffer->pStartAddress = NULL;
1954 pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
1959 if(pChannel->pActiveBuffer->pStartAddress == NULL)
1965 if(hDevice->nHwError != 0u)
1968 *pHwError = hDevice->nHwError;
1971 hDevice->nHwError = 0u;
2002 bool *
const pbAvailable
2021 *pbAvailable =
false;
2027 if (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)
2032 if (hDevice->pChannelTx->pActiveBuffer->bInUse ==
false)
2034 *pbAvailable =
true;
2058 bool *
const pbAvailable
2077 *pbAvailable =
false;
2083 if(hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)
2088 if (hDevice->pChannelRx->pActiveBuffer->bInUse ==
false)
2090 *pbAvailable =
true;
2117 bool *
const pbComplete
2129 *pbComplete =
false;
2134 if((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) == BITM_UART_LSR_TEMT)
2159 const ADI_CALLBACK pfCallback,
2160 void *
const pCBParam
2172 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
2173 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
2174 (hDevice->bAutobaudInProgress ==
true))
2181 hDevice->pfCallback = pfCallback;
2184 hDevice->pCBParam = pCBParam;
2223 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
2224 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
2225 (hDevice->bAutobaudInProgress ==
true))
2232 uint16_t nDataCfg = hDevice->pUARTRegs->LCR & (uint16_t)(~(BITM_UART_LCR_WLS |BITM_UART_LCR_STOP |BITM_UART_LCR_PEN));
2235 nDataCfg |= (uint16_t)(((uint16_t)((uint16_t)eWordLength |(uint16_t)eStopBits) |(uint16_t)eParity));
2238 hDevice->pUARTRegs->LCR = nDataCfg;
2272 uint16_t
const nDivC,
2273 uint8_t
const nDivM,
2274 uint16_t
const nDivN,
2286 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
2287 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
2293 if( (nDivM < 1u) || (nDivM > 3u)|| (nDivN > 2047u ) || (nOSR > 3u))
2301 hDevice->pUARTRegs->DIV = nDivC;
2302 hDevice->pUARTRegs->FBR = (uint16_t)((uint16_t)nDivN | (uint16_t)((uint16_t)nDivM <<BITP_UART_FBR_DIVM)) | (uint16_t)BITM_UART_FBR_FBEN;
2303 hDevice->pUARTRegs->LCR2 = nOSR;
2336 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) && (ADI_UART_DMA_EXTENSION_ENABLE == 1) 2362 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
2366 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PING_PONG;
2370 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI;
2374 hDevice->pChannelTx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
2410 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) && (ADI_UART_DMA_EXTENSION_ENABLE == 1) 2436 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
2440 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PING_PONG;
2444 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI;
2448 hDevice->pChannelRx->pFreeBuffer->nDmaMode = DMA_ENUM_CTL_CYCLE_CTL_BASIC;
2478 uint32_t *pnBaudRate,
2479 uint32_t *pAutobaudError
2491 if(pnBaudRate == NULL)
2502 if(hDevice->nAutobaudError != 0u)
2505 *pAutobaudError = hDevice->nAutobaudError;
2508 hDevice->nAutobaudError = 0u;
2514 *pnBaudRate = hDevice->nBaudRate;
2548 bool const bAutobaudCallbackMode
2560 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
2561 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
2574 hDevice->pUARTRegs->ACR |=(BITM_UART_ACR_ABE | BITM_UART_ACR_DNIEN | BITM_UART_ACR_TOIEN |(1u << 4u) | (3u << 8u));
2577 hDevice->nBaudRate = 0u;
2580 hDevice->bAutobaudInProgress =
true;
2583 hDevice->bAutobaudCallbackMode = bAutobaudCallbackMode;
2588 hDevice->bAutobaudInProgress =
false;
2591 hDevice->pUARTRegs->ACR &= (uint16_t)~(BITM_UART_ACR_ABE |
2592 BITM_UART_ACR_DNIEN |
2593 BITM_UART_ACR_TOIEN );
2596 hDevice->nBaudRate = 0u;
2636 hDevice->pUARTRegs->LCR |= BITM_UART_LCR_BRK;
2641 hDevice->pUARTRegs->LCR &= (uint16_t)~(BITM_UART_LCR_BRK);
2675 hDevice->pUARTRegs->MCR |= (BITM_UART_MCR_LOOPBACK);
2680 hDevice->pUARTRegs->MCR &= (uint16_t)~(BITM_UART_MCR_LOOPBACK);
2711 hDevice->pUARTRegs->FCR &= (uint16_t)~BITM_UART_FCR_RFTRIG;
2714 hDevice->pUARTRegs->FCR |= (uint16_t)eTriglevel;
2717 hDevice->nRxFifoTrig = sFifoTriggers[eTriglevel >> BITP_UART_FCR_RFTRIG];
2749 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_FIFOEN;
2753 ADI_INT_STATUS_ALLOC();
2754 ADI_ENTER_CRITICAL_REGION();
2755 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
2756 ADI_EXIT_CRITICAL_REGION();
2758 hDevice->bRxFifoEn =
true;
2764 hDevice->pUARTRegs->FCR &= (uint16_t)~(BITM_UART_FCR_FIFOEN);
2766 hDevice->bRxFifoEn =
false;
2797 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR;
2827 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR;
2860 ADI_INT_STATUS_ALLOC();
2861 ADI_ENTER_CRITICAL_REGION();
2863 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI | BITM_UART_IEN_EDMAR);
2864 ADI_EXIT_CRITICAL_REGION();
2867 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR;
2873 memset(hDevice->pChannelRx->PingPong,0, sizeof (hDevice->pChannelRx->PingPong));
2875 hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1];
2876 hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0];
2879 hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
2880 hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
2881 hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
2884 hDevice->pUARTRegs->RX;
2914 ADI_INT_STATUS_ALLOC();
2915 ADI_ENTER_CRITICAL_REGION();
2917 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
2918 ADI_EXIT_CRITICAL_REGION();
2921 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR;
2927 memset(hDevice->pChannelTx->PingPong,0, sizeof (hDevice->pChannelTx->PingPong));
2929 hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1];
2930 hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0];
2933 hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
2934 hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
2935 hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
2942 void UART0_Int_Handler(
void)
2946 Common_Uart_Interrupt_Handler(hDevice);
2947 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2954 #if defined (__ADUCM4x50__) 2956 void UART1_Int_Handler(
void)
2960 Common_Uart_Interrupt_Handler(hDevice);
2961 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2971 switch(hDevice->pUARTRegs->IIR & BITM_UART_IIR_STAT )
2976 case ENUM_UART_IIR_STAT_ETBEI:
2977 uart_TxDataHandler(hDevice);
2983 case ENUM_UART_IIR_STAT_RFTOI:
2986 uart_RxDataHandler(hDevice, hDevice->pUARTRegs->RFC);
2990 case ENUM_UART_IIR_STAT_ERBFI:
2992 uart_RxDataHandler(hDevice, hDevice->nRxFifoTrig);
2996 case ENUM_UART_IIR_STAT_RLSI:
2999 uint32_t nEvent = 0u;
3002 uint16_t nStatus = hDevice->pUARTRegs->LSR;
3005 if((BITM_UART_LSR_BI & nStatus) == BITM_UART_LSR_BI)
3010 hDevice->pUARTRegs->RX;
3019 else if((BITM_UART_LSR_FE & nStatus) == BITM_UART_LSR_FE)
3022 #if !defined(ADI_UART_DRAIN_RX_BUFFER) || (0==ADI_UART_DRAIN_RX_BUFFER) 3031 if((BITM_UART_LSR_PE & nStatus) == BITM_UART_LSR_PE)
3036 if((BITM_UART_LSR_OE & nStatus) == BITM_UART_LSR_OE)
3045 if((nEvent != 0u) && (hDevice->bAutobaudInProgress ==
false))
3050 hDevice->nHwError |= nEvent;
3059 case ENUM_UART_IIR_STAT_EDSSI:
3061 #if (ADI_UART_CFG_ENABLE_AUTOBAUD == 1) 3063 uint32_t nEvent = 0u;
3066 uint16_t nStatus = hDevice->pUARTRegs->ASRL & 0xFu;
3069 uint16_t acr = (hDevice->pUARTRegs->ACR & BITM_UART_ACR_ABE);
3072 if((nStatus != 0u) && (acr != 0u))
3084 nCount = (uint32_t)hDevice->pUARTRegs->ASRH << 12u;
3087 nCount |= (uint32_t)hDevice->pUARTRegs->ASRL >> 4u;
3090 if((nStatus & BITM_UART_ASRL_DONE) == BITM_UART_ASRL_DONE)
3095 if ((hDevice->pUARTRegs->FBR & 0x8000u) == 0x8000u)
3099 uint32_t nDivNSubtractor = 2048u;
3102 uint16_t nDivC = 1u;
3105 if(nCount < (8u << 3u))
3107 nDivN = ((nCount << 9u) / 8u) - nDivNSubtractor;
3111 else if(nCount < (8u << 4u))
3113 nDivN = ((nCount << 8u) / 8u) - nDivNSubtractor;
3118 else if(nCount < (8u << 5u))
3120 nDivN = ((nCount << 7u) / 8u) - nDivNSubtractor;
3127 nDivC = (uint16_t) (nCount / 32u / 8u);
3128 nDivN = ((nCount << 6u) / (8u * nDivC)) - nDivNSubtractor;
3144 hDevice->nBaudRate = ((nClock * 8u) / nCount);
3149 hDevice->nBaudRate = ((nClock * 8u) / nCount);
3156 if((hDevice->pfCallback != NULL) && (hDevice->bAutobaudCallbackMode ==
true))
3163 if((nStatus & BITM_UART_ASRL_BRKTO) == BITM_UART_ASRL_BRKTO)
3168 if((nStatus & BITM_UART_ASRL_NSETO) == BITM_UART_ASRL_NSETO)
3173 if((nStatus & BITM_UART_ASRL_NEETO) == BITM_UART_ASRL_NEETO)
3187 hDevice->nAutobaudError = nEvent;
3193 hDevice->pUARTRegs->RX;
3197 hDevice->pUARTRegs->ACR &=(uint16_t)~( BITM_UART_ACR_ABE |
3198 BITM_UART_ACR_DNIEN |
3199 BITM_UART_ACR_TOIEN );
3201 hDevice->bAutobaudInProgress =
false;
3210 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) && (ADI_UART_DMA_EXTENSION_ENABLE == 1) 3214 pChannel->nFreeDescriptor++;
3216 if(pChannel->pFillBuffer->nRemDoneTransfers > DMA_TRANSFER_LIMIT)
3218 pChannel->pFillBuffer->nRemDoneTransfers -= DMA_TRANSFER_LIMIT;
3222 pChannel->pFillBuffer->nRemDoneTransfers = 0;
3226 if(pChannel->pFillBuffer->nCount > 0)
3229 pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer);
3233 if(pChannel->pFillBuffer->nRemDoneTransfers ==0)
3236 uart_ManageProcessedBuffer(hDevice, pChannel, eEvent);
3243 void DMA_UART0_TX_Int_Handler(
void)
3247 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 3252 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 3258 void DMA_UART0_RX_Int_Handler(
void)
3262 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 3267 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 3273 #if defined(__ADUCM4x50__) 3275 void DMA_UART1_TX_Int_Handler(
void)
3279 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 3284 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 3290 void DMA_UART1_RX_Int_Handler(
void)
3294 #if !defined(ADI_UART_DMA_EXTENSION_ENABLE) || (0 == ADI_UART_DMA_EXTENSION_ENABLE) 3299 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 3312 static void uart_RxDataHandler(
ADI_UART_HANDLE hDevice, uint8_t nBytes)
3314 ADI_UART_BUFF_INFO *pFillBuffer = hDevice->pChannelRx->pFillBuffer;
3317 volatile uint8_t *pNextData = (uint8_t *)pFillBuffer->pStartAddress;
3319 bool activeBufferAvailable = ( (pNextData != NULL)
3320 && (pFillBuffer->bInUse ==
true)
3323 if(activeBufferAvailable)
3326 #if !defined(ADI_UART_DRAIN_RX_BUFFER) || (0==ADI_UART_DRAIN_RX_BUFFER) 3331 while ( (nBytes-- > 0)
3332 && (pFillBuffer->nIndex < pFillBuffer->nCount)
3338 pNextData[pFillBuffer->nIndex] = (uint8_t) hDevice->pUARTRegs->RX;
3341 pFillBuffer->nIndex++;
3349 if(pFillBuffer->nIndex == pFillBuffer->nCount)
3351 uart_ManageProcessedBuffer( hDevice, hDevice->pChannelRx
3364 while (activeBufferAvailable)
3367 nBytes = hDevice->pUARTRegs->RFC;
3375 if (pFillBuffer->nIndex)
3377 uart_ManageProcessedBuffer(hDevice,
3378 hDevice->pChannelRx,
3389 pNextData[pFillBuffer->nIndex] = hDevice->pUARTRegs->RX;
3392 pFillBuffer->nIndex++;
3395 if (pFillBuffer->nIndex == pFillBuffer->nCount)
3398 uart_ManageProcessedBuffer(hDevice,
3399 hDevice->pChannelRx,
3403 pFillBuffer = hDevice->pChannelRx->pFillBuffer;
3404 pNextData = (uint8_t *)pFillBuffer->pStartAddress;
3407 activeBufferAvailable = ( (pNextData != NULL)
3408 && (pFillBuffer->bInUse ==
true)
3411 if (!activeBufferAvailable)
3428 if (hDevice->pfCallback != NULL)
3430 hDevice->pfCallback( hDevice->pCBParam
3439 if( (pFillBuffer->pStartAddress == NULL)
3440 && (pFillBuffer->bInUse ==
false)
3443 hDevice->pUARTRegs->RX;
3458 volatile uint8_t *pNextData;
3461 if((hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelTx->pFillBuffer->bInUse ==
true))
3464 pNextData = (uint8_t *)hDevice->pChannelTx->pFillBuffer->pStartAddress;
3467 hDevice->pUARTRegs->TX = (uint16_t)pNextData[hDevice->pChannelTx->pFillBuffer->nIndex];
3470 hDevice->pChannelTx->pFillBuffer->nIndex++;
3475 if(hDevice->pChannelTx->pFillBuffer->nIndex >= hDevice->pChannelTx->pFillBuffer->nCount)
3504 pChannel->pFillBuffer->bInUse =
false;
3505 pChannel->pFillBuffer = pChannel->pFillBuffer->pNextBuffer;
3514 bool startNextTransaction = pChannel->pFillBuffer->bInUse;
3521 ADI_INT_STATUS_ALLOC();
3522 ADI_ENTER_CRITICAL_REGION();
3527 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
3534 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_EDMAR);
3536 if (hDevice->bRxFifoEn !=
true)
3540 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI);
3544 ADI_EXIT_CRITICAL_REGION();
3557 uint32_t nEvent = hDevice->nHwError;
3558 hDevice->nHwError = 0u;
3560 uint32_t *pBuffer = pChannel->pActiveBuffer->pStartAddress;
3562 #if !defined(ADI_UART_DRAIN_RX_BUFFER) || (0==ADI_UART_DRAIN_RX_BUFFER) 3563 void *pBuffArg = (
void*) pBuffer;
3565 ADI_UART_RX_BUFFER_INFO rxBuffInfo = { (
void*)pBuffer, pChannel->pActiveBuffer->nCount, pChannel->pActiveBuffer->nIndex };
3566 void *pBuffArg = (
void*) &rxBuffInfo;
3576 pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
3582 if(pChannel->pActiveBuffer->pStartAddress == NULL)
3593 hDevice->pfCallback(hDevice->pCBParam, (uint32_t)eEvent, pBuffArg);
3606 while( ((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) ||(hDevice->pUARTRegs->TFC != 0u))
3614 if( pChannel->pActiveBuffer->pNextBuffer->pStartAddress==NULL)
3629 if(startNextTransaction)
3631 pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer);
3647 ADI_UART_CONFIG
const* pUARTCfg = &gUARTCfg[nDeviceNum];
3650 hDevice->pUARTRegs->LCR = pUARTCfg->LCR;
3653 hDevice->pUARTRegs->DIV = pUARTCfg->DIV;
3656 hDevice->pUARTRegs->FBR = pUARTCfg->FBR;
3659 hDevice->pUARTRegs->LCR2 = pUARTCfg->LCR2;
3662 hDevice->pUARTRegs->FCR = pUARTCfg->FCR;
3665 hDevice->pUARTRegs->RSC = pUARTCfg->RSC;
3668 hDevice->pUARTRegs->IEN = pUARTCfg->IEN;
3691 if((hDevice == uart_device_info[i].hDevice) && (hDevice != NULL))
3712 #if defined(ADI_UART_DMA_EXTENSION_ENABLE) && (ADI_UART_DMA_EXTENSION_ENABLE == 1) #define ADI_UART0_CFG_DIVC
ADI_DMA_RESULT adi_dma_RegisterCallback(DMA_CHANn_TypeDef const eChannelID, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register a call-back function for a DMA channel.
ADI_UART_RESULT adi_uart_SetTxDmaMode(ADI_UART_HANDLE const hDevice, ADI_DMA_MODE const eMode)
Set the DMA Mode of the UART Tx Channel.
#define ADI_UART1_CFG_STOP_BIT
#define ADI_UART0_CFG_ENABLE_STICKY_PARITY
#define ADI_CYCLECOUNT_STORE(id)
#define ADI_UART1_CFG_DIVC
ADI_UART_RESULT adi_uart_Close(ADI_UART_HANDLE const hDevice)
Uninitialize the memory for the specified UART instance.
#define ADI_CYCLECOUNT_ISR_UART
ADI_UART_RESULT adi_uart_SetConfiguration(ADI_UART_HANDLE const hDevice, ADI_UART_PARITY const eParity, ADI_UART_STOPBITS const eStopBits, ADI_UART_WORDLEN const eWordLength)
Configuration of UART data.
#define ADI_UART0_CFG_TRIG_LEVEL
#define ADI_UART1_CFG_ENABLE_PARITY
#define ADI_UART0_CFG_WORD_LENGTH
ADI_UART_RESULT adi_uart_IsRxBufferAvailable(ADI_UART_HANDLE const hDevice, bool *const pbAvailable)
Peek function to know if a filled buffer is available.
#define ADI_UART0_CFG_DEASSERTION
#define ADI_UART0_CFG_DIVN
#define ADI_UART0_CFG_PARITY_SELECTION
#define ADI_UART_NUM_DEVICES
#define ADI_UART1_CFG_DISABLE_RX
#define ADI_UART1_CFG_OSR
#define ADI_UART0_CFG_STOP_BIT
ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel(ADI_UART_HANDLE const hDevice, ADI_UART_TRIG_LEVEL const eTriglevel)
Sets the RX FIFO trigger level. This will be the amount of data in the FIFO that will trigger an inte...
ADI_UART_RESULT adi_uart_GetRxBuffer(ADI_UART_HANDLE const hDevice, void **const ppBuffer, uint32_t *pHwError)
Transfer buffer ownership from the device back to the API if the data receive has completed....
#define ADI_UART1_CFG_ENABLE_STICKY_PARITY
ADI_UART_RESULT adi_uart_FlushTxFifo(ADI_UART_CONST_HANDLE const hDevice)
To flush the TX FIFO.
ADI_UART_RESULT adi_uart_SubmitTxBuffer(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA)
Submit a "filled" buffer for transmitting data in ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING....
ADI_UART_RESULT adi_uart_RegisterCallback(ADI_UART_HANDLE const hDevice, const ADI_CALLBACK pfCallback, void *const pCBParam)
Registering a callback function.
#define ADI_UART0_CFG_OSR
ADI_UART_RESULT adi_uart_FlushRxChannel(ADI_UART_CONST_HANDLE const hDevice)
Flush the Rx channel and disable interrupts. This will stop any buffers in flight and clear out any d...
ADI_UART_RESULT adi_uart_FlushTxChannel(ADI_UART_CONST_HANDLE const hDevice)
Flush the Tx channel and disable interrupts.This will stop any buffers in flight and clear out any da...
ADI_UART_RESULT adi_uart_SetRxDmaMode(ADI_UART_HANDLE const hDevice, ADI_DMA_MODE const eMode)
Set the DMA Mode of the UART Rx Channel.
#define ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT
#define ADI_CYCLECOUNT_ISR_DMA_UART_RX
#define ADI_UART1_CFG_DEASSERTION
ADI_UART_RESULT adi_uart_EnableFifo(ADI_UART_HANDLE const hDevice, bool const bEnable)
Enables internal FIFO as to work in 16550 mode. This helps to minimize system overhead and maximize s...
ADI_UART_RESULT adi_uart_GetTxBuffer(ADI_UART_HANDLE const hDevice, void **const ppBuffer, uint32_t *pHwError)
Transfer buffer ownership from the device back to the API if the data transmit has completed....
#define ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT
ADI_UART_RESULT adi_uart_SubmitRxBuffer(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA)
Submit an empty buffer for receiving the data in ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING....
#define ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT
#define ADI_UART0_CFG_DISABLE_RX
ADI_UART_RESULT adi_uart_Write(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA, uint32_t *pHwError)
Submit the buffer for transmitting the data in ADI_UART_DATA_TRANSFER_MODE_BLOCKING....
#define ADI_UART0_CFG_HOLD_TX
#define ADI_UART_BIDIR_MEMORY_SIZE
ADI_UART_RESULT adi_uart_FlushRxFifo(ADI_UART_CONST_HANDLE const hDevice)
Flush the RX FIFO.
ADI_UART_RESULT adi_uart_ForceTxBreak(ADI_UART_HANDLE const hDevice, bool const bEnable)
Forces the UART to send out a break signal.
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
ADI_UART_RESULT adi_uart_Read(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA, uint32_t *pHwError)
Submit the buffer for reading the data in ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function...
ADI_UART_RESULT adi_uart_EnableLoopBack(ADI_UART_HANDLE const hDevice, bool const bEnable)
Enable/Disable the loopback for the specified UART device.
#define ADI_UART1_CFG_SOUT_POLARITY
ADI_UART_RESULT adi_uart_IsTxBufferAvailable(ADI_UART_HANDLE const hDevice, bool *const pbAvailable)
Peek function to know if an empty buffer is avilable.
#define ADI_UART1_CFG_DIVN
#define ADI_UART1_CFG_TRIG_LEVEL
struct _ADI_UART_DEVICE * ADI_UART_HANDLE
#define ADI_CYCLECOUNT_ISR_DMA_UART_TX
#define ADI_UART1_CFG_PARITY_SELECTION
ADI_UART_RESULT adi_uart_Open(uint32_t const nDeviceNum, ADI_UART_DIRECTION const eDirection, void *pMemory, uint32_t const nMemSize, ADI_UART_HANDLE *const phDevice)
Initialization function for the UART device.
#define ADI_UART1_CFG_HOLD_TX
#define ADI_UART0_CFG_DIVM
ADI_UART_RESULT adi_uart_GetRX(ADI_UART_HANDLE const hDevice, uint8_t *const pRX)
Read the UART receive buffer register regardless of an error. This mode of reading a byte is done wit...
#define ADI_UART1_CFG_WORD_LENGTH
#define ADI_UART_DMA_EXTENSION_ENABLE
const struct _ADI_UART_DEVICE * ADI_UART_CONST_HANDLE
void adi_dma_Init(void)
Initialize the DMA peripheral.
#define ADI_UART1_CFG_ENABLE_FIFO
#define ADI_UART0_CFG_ENABLE_FIFO
ADI_UART_RESULT adi_uart_IsTxComplete(ADI_UART_HANDLE const hDevice, bool *const pbComplete)
Function to let the API know if all the data had been drained from the Tx shift registers.
ADI_UART_RESULT adi_uart_ConfigBaudRate(ADI_UART_HANDLE const hDevice, uint16_t const nDivC, uint8_t const nDivM, uint16_t const nDivN, uint8_t const nOSR)
Set baudrate by configuring the fractional dividors.
ADI_UART_RESULT adi_uart_EnableAutobaud(ADI_UART_HANDLE const hDevice, bool const bEnable, bool const bAutobaudCallbackMode)
Enable/Disable UART autobaud detection as well as configures the device for autobaud detection.
#define ADI_UART1_CFG_DIVM
#define ADI_UART0_CFG_SOUT_POLARITY
ADI_UART_RESULT adi_uart_GetBaudRate(ADI_UART_HANDLE const hDevice, uint32_t *pnBaudRate, uint32_t *pAutobaudError)
Get the baudrate of the UART device instance. This is used in the scenario when a callback has not be...
#define ADI_UART_UNIDIR_MEMORY_SIZE
#define ADI_UART0_CFG_ENABLE_PARITY
#define ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT