59 #include <adi_processor.h> 64 #include <drivers/flash/adi_flash.h> 91 #pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm026 95 #include "adi_flash_data.c" 102 #define ASSERT(X) assert(X) 108 #define CLR_BITS(REG, BITS) ((REG) &= ~(BITS)) 109 #define SET_BITS(REG, BITS) ((REG) |= (BITS)) 116 if ( (fee_device_info[0].hDevice == (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL) ) {
125 static void BusyWait (
ADI_FEE_HANDLE const hDevice, uint32_t
const status);
126 static void BusyWait (
ADI_FEE_HANDLE const hDevice, uint32_t
const status)
128 while ((hDevice->pDev->STAT & status) != 0u) {}
132 static void dmaCallback(
void *pCBParam, uint32_t Event,
void *pArg);
133 static void dmaCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
155 if (0u != hDevice->pfCallback) {
156 hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, (
void*)NULL);
209 if (fee_device_info[nDeviceNum].hDevice != NULL) {
213 if ((pMemory == NULL) || (phDevice == NULL)) {
231 fee_device_info[nDeviceNum].hDevice = (ADI_FEE_DEV_DATA_TYPE *)pMemory;
237 memset(pMemory, 0, nMemorySize);
241 hDevice->pDevInfo = &fee_device_info[nDeviceNum];
248 hDevice->pDev = fee_device_info[nDeviceNum].pDev;
251 hDevice->pDevInfo->pConfig = (ADI_FEE_CONFIG*)&gConfigInfo[nDeviceNum];
257 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
260 hDevice->pDev->IEN = hDevice->pDevInfo->pConfig->eccIrqEnables;
261 hDevice->pDev->TIME_PARAM0 = hDevice->pDevInfo->pConfig->param0;
262 hDevice->pDev->TIME_PARAM1 = hDevice->pDevInfo->pConfig->param1;
263 hDevice->pDev->ABORT_EN_LO = hDevice->pDevInfo->pConfig->abortEnableLo;
264 hDevice->pDev->ABORT_EN_HI = hDevice->pDevInfo->pConfig->abortEnableHi;
265 hDevice->pDev->ECC_CFG = hDevice->pDevInfo->pConfig->eccConfig;
268 CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
271 hDevice->pDev->KEY = 0u;
286 NVIC_EnableIRQ(hDevice->pDevInfo->pioIrqNum);
287 NVIC_EnableIRQ(hDevice->pDevInfo->dmaIrqNum);
316 if (
true != IsDeviceHandle(hDevice)) {
327 if (fee_device_info[dev].hDevice == hDevice)
329 fee_device_info[dev].hDevice = NULL;
335 NVIC_DisableIRQ(hDevice->pDevInfo->pioIrqNum);
336 NVIC_DisableIRQ(hDevice->pDevInfo->dmaIrqNum);
341 #if defined (__ADUCM4x50__) 355 if (
true != IsDeviceHandle(hDevice)) {
360 *pREG_FLCC0_KEY = ENUM_FLCC_KEY_USERKEY;
363 *pREG_FLCC0_TIME_PARAM1 |= ((((uint32_t)numWaitStates) << BITP_FLCC_TIME_PARAM1_WAITSTATES) & BITM_FLCC_TIME_PARAM1_WAITSTATES);
366 while (((*pREG_FLCC0_TIME_PARAM1 & BITM_FLCC_TIME_PARAM1_CURWAITSTATES) != (1u << BITP_FLCC_TIME_PARAM1_CURWAITSTATES))){}
410 if (
true != IsDeviceHandle(hDevice)) {
415 if (
true == hDevice->bTransferInProgress) {
421 hDevice->pfCallback = pfCallback;
422 hDevice->pCBParam = pCBParam;
467 if (
true != IsDeviceHandle(hDevice)) {
472 if (
true == hDevice->bTransferInProgress) {
479 if ( (nPageNumStart > nPageNumEnd)
487 for (page = nPageNumStart; page <= nPageNumEnd; page++)
490 BusyWait(hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
496 result = SendCommand (hDevice, ENUM_FLCC_CMD_ERASEPAGE);
507 *pHwErrors = hDevice->feeError;
508 if (0u != hDevice->feeError) {
545 if (
true != IsDeviceHandle(hDevice)) {
550 if (
true == hDevice->bTransferInProgress) {
556 result = SendCommand (hDevice, ENUM_FLCC_CMD_MASSERASE);
562 *pHwErrors = hDevice->feeError;
563 if (0u != hDevice->feeError) {
611 if (
true != IsDeviceHandle(hDevice)) {
616 if (
true == hDevice->bTransferInProgress) {
621 if ( (((uint32_t)pTransaction->
pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->
pWriteData) & 0x3u) != 0u) )
627 if ((pTransaction->
nSize & 0x7u) != 0u) {
631 if (
true == pTransaction->
bUseDma) {
633 if (DMA_TRANSFER_LIMIT < (pTransaction->
nSize /
sizeof(uint32_t))) {
640 hDevice->bSubmitCalled =
false;
643 hDevice->pNextWriteAddress = pTransaction->
pWriteAddr;
644 hDevice->pNextReadAddress = pTransaction->
pWriteData;
645 hDevice->nRemainingBytes = pTransaction->
nSize;
646 hDevice->bUseDma = pTransaction->
bUseDma;
649 result = InitiateTransfer (hDevice);
655 if (0u != hDevice->dmaError) {
656 return hDevice->dmaError;
660 *pHwErrors = hDevice->feeError;
661 if (0u != hDevice->feeError) {
667 if (hDevice->nRemainingBytes != 0u) {
710 if (
true != IsDeviceHandle(hDevice)) {
715 if (
true == hDevice->bTransferInProgress) {
720 if ( (((uint32_t)pTransaction->
pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->
pWriteData) & 0x3u) != 0u) )
726 if ((pTransaction->
nSize & 0x7u) != 0u) {
730 if (
true == pTransaction->
bUseDma) {
732 if (DMA_TRANSFER_LIMIT < (pTransaction->
nSize /
sizeof(uint32_t))) {
739 hDevice->bSubmitCalled =
true;
742 hDevice->pNextWriteAddress = pTransaction->
pWriteAddr;
743 hDevice->pNextReadAddress = pTransaction->
pWriteData;
744 hDevice->nRemainingBytes = pTransaction->
nSize;
745 hDevice->bUseDma = pTransaction->
bUseDma;
748 result = InitiateTransfer (hDevice);
777 if (
true != IsDeviceHandle(hDevice)) {
781 if (pbCompletionState == NULL) {
787 if (
false == hDevice->bSubmitCalled) {
791 if (
true == hDevice->bTransferInProgress) {
792 *pbCompletionState =
false;
794 *pbCompletionState =
true;
832 if (
true != IsDeviceHandle(hDevice)) {
838 if (
false == hDevice->bSubmitCalled) {
846 if (0u != hDevice->dmaError) {
847 return hDevice->dmaError;
851 *pHwErrors = hDevice->feeError;
852 if (0u != hDevice->feeError) {
858 if ((0u != hDevice->nRemainingBytes) || (
true == hDevice->bTransferInProgress)) {
891 if (
true != IsDeviceHandle(hDevice)) {
895 if ( (pnPageNum == NULL)
931 if (
true != IsDeviceHandle(hDevice)) {
935 if ( (pnBlockNum == NULL)
985 if (
true != IsDeviceHandle(hDevice)) {
990 if (
true == hDevice->bTransferInProgress) {
994 if ( (pSigResult == NULL)
995 || (nStartPage > nEndPage)
1005 BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
1012 result = SendCommand(hDevice, ENUM_FLCC_CMD_SIGN);
1019 *pSigResult = hDevice->pDev->SIGNATURE;
1025 *pHwErrors = hDevice->feeError;
1026 if (0u != hDevice->feeError) {
1068 if (
true != IsDeviceHandle(hDevice)) {
1073 if (
true == hDevice->bTransferInProgress) {
1083 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
1084 CLR_BITS (hDevice->pDev->WRPROT, 1u << nBlockNum);
1085 hDevice->pDev->KEY = 0u;
1114 if (
true != IsDeviceHandle(hDevice)) {
1119 if (
true == hDevice->bTransferInProgress) {
1125 if (
true == bSleep) {
1126 result = SendCommand (hDevice, ENUM_FLCC_CMD_SLEEP);
1128 result = SendCommand (hDevice, ENUM_FLCC_CMD_IDLE);
1158 if (
true != IsDeviceHandle(hDevice)) {
1164 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
1165 hDevice->pDev->CMD = ENUM_FLCC_CMD_ABORT;
1166 hDevice->pDev->KEY = 0u;
1194 if (
true != IsDeviceHandle(hDevice)) {
1198 if (pnAddress == NULL) {
1206 *pnAddress = hDevice->pDev->WR_ABORT_ADDR;
1243 if (
true != IsDeviceHandle(hDevice)) {
1248 if (
true == hDevice->bTransferInProgress) {
1258 CLR_BITS (hDevice->pDev->ECC_CFG, (BITM_FLCC_ECC_CFG_PTR | BITM_FLCC_ECC_CFG_INFOEN));
1261 hDevice->pDev->ECC_CFG |= (nRelAddress & BITM_FLCC_ECC_CFG_PTR);
1264 if (
true == bInfoECCEnable) {
1265 SET_BITS (hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_INFOEN);
1299 if (
true != IsDeviceHandle(hDevice)) {
1304 if (
true == hDevice->bTransferInProgress) {
1310 if (
true == bEnable) {
1311 SET_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN);
1313 CLR_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN);
1353 if (
true != IsDeviceHandle(hDevice)) {
1358 if (
true == hDevice->bTransferInProgress) {
1377 nBitMask = BITM_FLCC_IEN_ECC_ERROR;
1378 nBitPos = BITP_FLCC_IEN_ECC_ERROR;
1380 #if defined (__ADUCM4x50__) 1382 nBitMask = BITM_FLCC_IEN_ECC_CORRECT;
1383 nBitPos = BITP_FLCC_IEN_ECC_CORRECT;
1388 CLR_BITS (hDevice->pDev->IEN, nBitMask);
1391 SET_BITS (hDevice->pDev->IEN, ((uint32_t)eResponse) << nBitPos);
1420 if (
true != IsDeviceHandle(hDevice)) {
1424 if (pnAddress == NULL) {
1430 *pnAddress = hDevice->pDev->ECC_ADDR;
1458 if (
true != IsDeviceHandle(hDevice)) {
1462 if (pnNumCorrections == NULL) {
1468 *pnNumCorrections = (hDevice->pDev->STAT & BITM_FLCC_STAT_ECCERRCNT) >> BITP_FLCC_STAT_ECCERRCNT;
1482 BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
1487 hDevice->pDev->STAT = BITM_FLCC_STAT_CMDCOMP;
1490 SET_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
1493 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
1494 hDevice->pDev->CMD = cmd;
1495 hDevice->pDev->KEY = 0u;
1510 if (0u != hDevice->nRemainingBytes) {
1513 SET_BITS (hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
1516 hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
1517 hDevice->pNextWriteAddress += 2;
1520 hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress;
1521 hDevice->pNextReadAddress++;
1522 hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress;
1523 hDevice->pNextReadAddress++;
1524 hDevice->nRemainingBytes -=
sizeof(uint64_t);
1527 hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE;
1542 if (0u != hDevice->nRemainingBytes) {
1545 uint16_t chan = hDevice->pDevInfo->dmaChanNum;
1548 pADI_DMA0->SRCADDR_CLR = 1u << chan;
1549 pADI_DMA0->DSTADDR_CLR = 1u << chan;
1552 pADI_DMA0->EN_SET = 1u << chan;
1555 pADI_DMA0->RMSK_CLR = 1u << chan;
1558 pADI_DMA0->ALT_CLR = 1u << chan;
1567 pCCD->
DMASRCEND = (uint32_t)hDevice->pNextReadAddress + hDevice->nRemainingBytes -
sizeof(uint32_t);
1570 pCCD->
DMADSTEND = (uint32_t)&hDevice->pDev->KH_DATA1;
1573 hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
1581 | (uint32_t)((hDevice->nRemainingBytes/
sizeof(uint32_t) - 1u) << DMA_BITP_CTL_N_MINUS_1)
1582 | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) );
1585 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
1586 SET_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
1587 hDevice->pDev->KEY = 0u;
1605 if (
true == hDevice->bTransferInProgress)
1611 BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY);
1614 hDevice->feeError = 0u;
1618 hDevice->bTransferInProgress =
true;
1621 CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
1624 hDevice->pDev->STAT = BITM_FLCC_STAT_WRALCOMP | BITM_FLCC_STAT_CMDCOMP | BITM_FLCC_STAT_CMDFAIL;
1627 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
1628 CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
1629 hDevice->pDev->KEY = 0u;
1632 if (
true == hDevice->bUseDma) {
1633 result = InitiateDmaTransfer(hDevice);
1635 result = InitiatePioTransfer(hDevice);
1646 void Flash0_Int_Handler(
void)
1652 bool bError =
false;
1659 if (hDevice == NULL) {
1665 hDevice->FlashStatusCopy = hDevice->pDev->STAT;
1666 hDevice->pDev->STAT = hDevice->FlashStatusCopy;
1669 hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy);
1670 if (0u != hDevice->feeError) {
1675 if (
false == bError) {
1677 if (0u != (BITM_FLCC_STAT_WRALCOMP & hDevice->FlashStatusCopy)) {
1682 if (0u != hDevice->nRemainingBytes) {
1685 hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
1686 hDevice->pNextWriteAddress += 2;
1689 hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress;
1690 hDevice->pNextReadAddress++;
1691 hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress;
1692 hDevice->pNextReadAddress++;
1693 hDevice->nRemainingBytes -=
sizeof(uint64_t);
1696 hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE;
1702 BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY);
1708 }
else if (0u != (BITM_FLCC_STAT_CMDCOMP & hDevice->FlashStatusCopy)) {
1726 if (
true == bPost) {
1729 CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
1732 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
1733 CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
1734 hDevice->pDev->KEY = 0u;
1737 hDevice->bTransferInProgress =
false;
1740 if (0u != hDevice->pfCallback) {
1741 if (
false == bError) {
1759 void DMA_FLASH0_Int_Handler (
void)
1769 hDevice->FlashStatusCopy = hDevice->pDev->STAT;
1770 hDevice->pDev->STAT = hDevice->FlashStatusCopy;
1773 hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy);
1776 hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
1777 CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
1778 hDevice->pDev->KEY = 0u;
1781 hDevice->nRemainingBytes = 0u;
1784 hDevice->bTransferInProgress =
false;
1787 if (0u != hDevice->pfCallback) {
1790 if ((0u == hDevice->feeError) && (0u == hDevice->dmaError)) {
1794 }
else if (0u == hDevice->feeError) {
1798 }
else if (0u == hDevice->dmaError) {
1800 hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, NULL);
ADI_FEE_RESULT adi_fee_GetBuffer(ADI_FEE_HANDLE const hDevice, uint32_t *const pHwErrors)
Blocking mode call to await transaction completion.
ADI_FEE_RESULT adi_fee_IsBufferAvailable(ADI_FEE_HANDLE const hDevice, bool *const pbCompletionState)
Non-blocking check if a write transaction complete.
ADI_DMA_RESULT adi_dma_RegisterCallback(DMA_CHANn_TypeDef const eChannelID, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register a call-back function for a DMA channel.
ADI_FEE_RESULT adi_fee_GetECCCorrections(ADI_FEE_HANDLE const hDevice, uint32_t *const pnNumCorrections)
Get the number of 1-bit error corrections.
ADI_FEE_RESULT adi_fee_MassErase(ADI_FEE_HANDLE const hDevice, uint32_t *const pHwErrors)
Erase the entire flash user space memory. This is a blocking call.
ADI_FEE_RESULT adi_fee_GetBlockNumber(ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t *const pnBlockNum)
Get the zero-based (16kB) block number within which a flash address resides.
ADI_FEE_RESULT adi_fee_GetECCErrAddr(ADI_FEE_HANDLE const hDevice, uint32_t *const pnAddress)
Get the address for which the ECC event is detected.
#define ADI_FEE_MEMORY_SIZE
ADI_FEE_RESULT adi_fee_GetAbortAddr(ADI_FEE_HANDLE const hDevice, uint32_t *const pnAddress)
Get the address of recently aborted write command.
ADI_FEE_RESULT adi_fee_Sleep(ADI_FEE_HANDLE const hDevice, bool const bSleep)
Sleep or awake the flash controller. This is a blocking call.
#define FEE_MAX_NUM_BLOCKS
ADI_FEE_RESULT adi_fee_ConfigECC(ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable)
Configure ECC start page and enablement.
struct __ADI_FEE_DEV_DATA_TYPE * ADI_FEE_HANDLE
ADI_FEE_RESULT adi_fee_Open(uint32_t const nDeviceNum, void *const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE *const phDevice)
Open the flash controller.
ADI_FEE_RESULT adi_fee_ConfigECCEvents(ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse)
Confifure ECC event response.
ADI_FEE_RESULT adi_fee_WriteProtectBlock(ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum)
Set write protection on an (16kB) block.
ADI_FEE_RESULT adi_fee_Write(ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION *const pTransaction, uint32_t *const pHwErrors)
Perform a blocking flash data write operation.
ADI_FEE_RESULT adi_fee_EnableECC(ADI_FEE_HANDLE const hDevice, bool const bEnable)
Enable/Disable user space ECC for the device.
ADI_FEE_RESULT adi_fee_ConfigureWaitStates(ADI_FEE_HANDLE const hDevice, uint8_t numWaitStates)
Configure the flash wait states.
ADI_FEE_RESULT adi_fee_RegisterCallback(ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register an application-defined callback function.
ADI_FEE_RESULT adi_fee_SubmitBuffer(ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION *const pTransaction)
Submit a non-blocking flash data write operation for background processing.
void adi_dma_Init(void)
Initialize the DMA peripheral.
#define ADI_FEE_NUM_INSTANCES
ADI_FEE_RESULT adi_fee_GetPageNumber(ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t *const pnPageNum)
Get the zero-based (2kB) page number within which a flash address resides.
ADI_FEE_RESULT adi_fee_Abort(ADI_FEE_HANDLE const hDevice)
Forcefully ABORT an ongoing flash operation. This is a blocking call.
ADI_FEE_RESULT adi_fee_VerifySignature(ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t *const pSigResult, uint32_t *const pHwErrors)
Generate the CRC signature for a range of flash data page(s). This is a blocking call.
#define FEE_MAX_NUM_PAGES
ADI_FEE_RESULT adi_fee_PageErase(ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t *const pHwErrors)
Erase the given range of (2kB) page(s) within the flash user space memory. This is a blocking call.
ADI_FEE_RESULT adi_fee_Close(ADI_FEE_HANDLE const hDevice)
Close the flash controller.