ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_rtc_data.c
1 
15 #ifndef ADI_RTC_DATA_C_
16 #define ADI_RTC_DATA_C_
17 
18 #include <stdlib.h>
19 #include "adi_rtc_def.h"
20 
21 static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] =
22 {
23  {
24  (ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL
25  },
26  {
27  (ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL,
28  }
29 };
30 
31 
32 static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
33 {
34  /* RTC0 */
35  {
36  /* CR0 */
37  RTC0_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN |
38  RTC0_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN |
39  RTC0_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN |
40  RTC0_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN |
41  RTC0_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN |
42  RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN ,
43  /* CR1 */
44  0,
45  /* CNT0 */
47  /* CNT1 */
49  /* ALM0 */
51  /* ALM1 */
53  /* ALM2 */
54  0,
55  /* TRIM */
56  RTC0_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN |
57  RTC0_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL |
58  RTC0_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD |
59  RTC0_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE,
60  0, /* CR2IC */
61  0, /* CR3SS */
62  0, /* CR4SS */
63  0, /* SSMSK */
64  0, /* SS1 */
65 
66 
67 #if defined(__ADUCM302x__)
68  0, /* SS1ARL (RTC1 only) */
69 #elif defined(__ADUCM4x50__)
70  0, /* SS1LOWDUR (RTC1 only) */
71  0, /* SS1HIGHDUR (RTC1 only) */
72  0, /* SS2LOWDUR (RTC1 only) */
73  0, /* SS2HIGHDUR (RTC1 only) */
74  0, /* SS3LOWDUR (RTC1 only) */
75  0, /* SS3HIGHDUR (RTC1 only) */
76  0, /* CR5SSS (RTC1 only) */
77  0, /* CR6SSS (RTC1 only) */
78  0, /* CR7SSS (RTC1 only) */
79 #endif
80  0, /* GPMUX0 */
81  0 /* GPMUX1 */
82  },
83  /* RTC-1 */
84  {
85  /* CR0 */
86  RTC1_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN |
87  RTC1_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN |
88  RTC1_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN |
89  RTC1_CFG_ENABLE_MOD60_ALARM << BITP_RTC_CR0_MOD60ALMEN |
90  RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD << BITP_RTC_CR0_MOD60ALM |
91  RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT << BITP_RTC_CR0_MOD60ALMINTEN |
92  RTC1_CFG_ENABLE_ISO_INTERRUPT << BITP_RTC_CR0_ISOINTEN |
93  RTC1_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN |
94  RTC1_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN |
95  RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN ,
96  /* CR1 */
97  RTC1_CFG_ENABLE_COUNT_INTERRUPT << BITP_RTC_CR1_CNTINTEN |
98  RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT << BITP_RTC_CR1_PSINTEN |
99  RTC1_CFG_ENABLE_TRIM_INTERRUPT << BITP_RTC_CR1_TRMINTEN |
100  RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTROLLINTEN |
101  RTC1_CFG_PRESCALE << BITP_RTC_CR1_PRESCALE2EXP |
102  RTC1_CFG_CNT_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTMOD60ROLLINTEN ,
103  /* CNT0 */
105  /* CNT1 */
107 
108  /* ALM[123] */
112 
113  /* TRIM */
114  RTC1_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN |
115  RTC1_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL |
116  RTC1_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD |
117  RTC1_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE,
118 
119  /* CR2IC */
120  RTC1_CFG_IC0_ENABLE << BITP_RTC_CR2IC_IC0EN |
121  RTC1_CFG_IC2_ENABLE << BITP_RTC_CR2IC_IC2EN |
122  RTC1_CFG_IC3_ENABLE << BITP_RTC_CR2IC_IC3EN |
123  RTC1_CFG_IC4_ENABLE << BITP_RTC_CR2IC_IC4EN |
124  RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC0IRQEN |
125  RTC1_CFG_IC2_INT_ENABLE << BITP_RTC_CR2IC_IC2IRQEN |
126  RTC1_CFG_IC3_INT_ENABLE << BITP_RTC_CR2IC_IC3IRQEN |
127  RTC1_CFG_IC4_INT_ENABLE << BITP_RTC_CR2IC_IC4IRQEN |
128  RTC1_CFG_IC0_EDGE_POLARITY << BITP_RTC_CR2IC_IC0LH |
129  RTC1_CFG_IC2_EDGE_POLARITY << BITP_RTC_CR2IC_IC2LH |
130  RTC1_CFG_IC3_EDGE_POLARITY << BITP_RTC_CR2IC_IC3LH |
131  RTC1_CFG_IC4_EDGE_POLARITY << BITP_RTC_CR2IC_IC4LH |
132  RTC1_CFG_IC_OVER_WRITE_ENABLE << BITP_RTC_CR2IC_ICOWUSEN,
133 
134 #if defined(__ADUCM4x50__)
135  /* CR3SS */
136  RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN |
137  RTC1_CFG_SS2_ENABLE << BITP_RTC_CR3SS_SS2EN |
138  RTC1_CFG_SS3_ENABLE << BITP_RTC_CR3SS_SS3EN |
139  RTC1_CFG_SS4_ENABLE << BITP_RTC_CR3SS_SS4EN |
140  RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN |
141  RTC1_CFG_SS2_INT_ENABLE << BITP_RTC_CR3SS_SS2IRQEN |
142  RTC1_CFG_SS3_INT_ENABLE << BITP_RTC_CR3SS_SS3IRQEN |
143  RTC1_CFG_SS4_INT_ENABLE << BITP_RTC_CR3SS_SS4IRQEN,
144 
145  /* CR4SS */
146  RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN |
147  RTC1_CFG_SS2_MASK_ENABLE << BITP_RTC_CR4SS_SS2MSKEN |
148  RTC1_CFG_SS3_MASK_ENABLE << BITP_RTC_CR4SS_SS3MSKEN |
149  RTC1_CFG_SS4_MASK_ENABLE << BITP_RTC_CR4SS_SS4MSKEN |
150  RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN |
151  RTC1_CFG_SS2_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS2ARLEN |
152  RTC1_CFG_SS3_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS3ARLEN,
153 #elif defined(__ADUCM302x__)
154  /* CR3SS */
155  RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN |
156  RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN |
157 
158  /* CR4SS */
159  RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN |
160  RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN,
161 #else
162 #error RTC driver not ported to this processor
163 #endif
164  /* SSMSK */
166 
167  /* SS1 */
168 #if defined(__ADUCM302x__)
169  RTC1_CFG_SS1_AUTO_RELOAD_VALUE,
170 #elif defined(__ADUCM4x50__)
171 #if !defined(RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH) ||!defined(RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW)\
172  ||!defined(RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH)||!defined(RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW)\
173  ||!defined(RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH)||!defined(RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW)
174 #error "update Autoreload register macro in adi_rtc_config.h to the latest version"
175 #else
178 
181 
184 #endif
185 /* RTC-1 static configuration macros added for 3.2.0 version */
186 #if !defined( RTC1_CFG_CR5SSS_OC1SMPEN )||!defined(RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN )\
187  ||!defined( RTC1_CFG_CR5SSS_OC2SMPEN )||!defined( RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN )\
188  ||!defined(RTC1_CFG_CR5SSS_OC3SMPEN )||!defined( RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN )
189 #error "update CR5SSS register macro in adi_rtc_config.h to the latest version"
190 #else
191  /* CR5SSS */
192  RTC1_CFG_CR5SSS_OC1SMPEN << BITP_RTC_CR5SSS_SS1SMPEN |
193  RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN << BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN |
194  RTC1_CFG_CR5SSS_OC2SMPEN << BITP_RTC_CR5SSS_SS2SMPEN |
195  RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN << BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN |
196  RTC1_CFG_CR5SSS_OC3SMPEN << BITP_RTC_CR5SSS_SS3SMPEN |
197  RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN << BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN,
198 #endif
199 #if !defined(RTC1_CFG_CR6SSS_OC1SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC1SMPONRE )\
200  ||!defined( RTC1_CFG_CR6SSS_OC2SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC2SMPONRE )\
201  ||!defined(RTC1_CFG_CR6SSS_OC3SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC3SMPONRE )
202 #error "update CR6SSS register macro in adi_rtc_config.h to the latest version"
203 #else
204  /* CR6SSS */
205  RTC1_CFG_CR6SSS_OC1SMPONFE << BITP_RTC_CR6SSS_SS1SMPONFE |
206  RTC1_CFG_CR6SSS_OC1SMPONRE << BITP_RTC_CR6SSS_SS1SMPONRE |
207  RTC1_CFG_CR6SSS_OC2SMPONFE << BITP_RTC_CR6SSS_SS2SMPONFE |
208  RTC1_CFG_CR6SSS_OC2SMPONRE << BITP_RTC_CR6SSS_SS2SMPONRE |
209  RTC1_CFG_CR6SSS_OC3SMPONFE << BITP_RTC_CR6SSS_SS3SMPONFE |
210  RTC1_CFG_CR6SSS_OC3SMPONRE << BITP_RTC_CR6SSS_SS3SMPONRE,
211 #endif
212 #if !defined(RTC1_CFG_CR7SSS_OC1SMPEXP )||!defined(RTC1_CFG_CR7SSS_OC1SMPPTRN )\
213  ||!defined( RTC1_CFG_CR7SSS_OC2SMPEXP )||!defined(RTC1_CFG_CR7SSS_OC2SMPPTRN )\
214  ||!defined(RTC1_CFG_CR7SSS_OC3SMPEXP )||!defined( RTC1_CFG_CR7SSS_OC3SMPPTRN )
215 #error "update CR7SSS register macro in adi_rtc_config.h to the latest version"
216 #else
217  /* CR7SSS */
218  RTC1_CFG_CR7SSS_OC1SMPEXP << BITP_RTC_CR7SSS_SS1SMPEXP |
219  RTC1_CFG_CR7SSS_OC1SMPPTRN << BITP_RTC_CR7SSS_SS1SMPPTRN |
220  RTC1_CFG_CR7SSS_OC2SMPEXP << BITP_RTC_CR7SSS_SS2SMPEXP |
221  RTC1_CFG_CR7SSS_OC2SMPPTRN << BITP_RTC_CR7SSS_SS2SMPPTRN |
222  RTC1_CFG_CR7SSS_OC3SMPEXP << BITP_RTC_CR7SSS_SS3SMPEXP |
223  RTC1_CFG_CR7SSS_OC3SMPPTRN << BITP_RTC_CR7SSS_SS3SMPPTRN,
224 #endif
225 #if !defined(RTC1_CFG_GPMUX0_OC1GPIN0SEL)||!defined(RTC1_CFG_GPMUX0_OC1GPIN1SEL )\
226  ||!defined(RTC1_CFG_GPMUX0_OC1GPIN2SEL)||!defined(RTC1_CFG_GPMUX0_OC2GPIN0SEL )\
227  ||!defined(RTC1_CFG_GPMUX0_OC2GPIN1SEL)
228 #error "update GPMUX0 register macro in adi_rtc_config.h to the latest version"
229 #else
230  /* GPMUX0 */
231  RTC1_CFG_GPMUX0_OC1GPIN0SEL << BITP_RTC_GPMUX0_SS1GPIN0SEL |
232  RTC1_CFG_GPMUX0_OC1GPIN1SEL << BITP_RTC_GPMUX0_SS1GPIN1SEL |
233  RTC1_CFG_GPMUX0_OC1GPIN2SEL << BITP_RTC_GPMUX0_SS1GPIN2SEL |
234  RTC1_CFG_GPMUX0_OC2GPIN0SEL << BITP_RTC_GPMUX0_SS2GPIN0SEL |
235  RTC1_CFG_GPMUX0_OC2GPIN1SEL << BITP_RTC_GPMUX0_SS2GPIN1SEL,
236 #endif
237 #if !defined(RTC1_CFG_GPMUX1_OC2GPIN2SEL )||!defined(RTC1_CFG_GPMUX1_OC3GPIN0SEL )\
238  ||!defined(RTC1_CFG_GPMUX1_OC3GPIN1SEL )||!defined(RTC1_CFG_GPMUX1_OC3GPIN2SEL )\
239  ||!defined(RTC1_CFG_GPMUX1_OC1DIFFOUT)||!defined( RTC1_CFG_GPMUX1_OC3DIFFOUT )
240 #error "update GPMUX1 register macro in adi_rtc_config.h to the latest version"
241 #else
242  /* GPMUX1 */
243  RTC1_CFG_GPMUX1_OC2GPIN2SEL << BITP_RTC_GPMUX1_SS2GPIN2SEL |
244  RTC1_CFG_GPMUX1_OC3GPIN0SEL << BITP_RTC_GPMUX1_SS3GPIN0SEL |
245  RTC1_CFG_GPMUX1_OC3GPIN1SEL << BITP_RTC_GPMUX1_SS3GPIN1SEL |
246  RTC1_CFG_GPMUX1_OC3GPIN2SEL << BITP_RTC_GPMUX1_SS3GPIN2SEL |
247  RTC1_CFG_GPMUX1_OC1DIFFOUT << BITP_RTC_GPMUX1_SS1DIFFOUT |
248  RTC1_CFG_GPMUX1_OC3DIFFOUT << BITP_RTC_GPMUX1_SS3DIFFOUT,
249 #endif
250 #endif
251  }
252 
253 };
254 
255 #endif
256 
#define RTC1_CFG_GPMUX0_OC1GPIN2SEL
#define RTC1_CFG_SS2_AUTO_RELOADING_ENABLE
#define RTC1_CFG_IC4_EDGE_POLARITY
#define RTC1_CFG_SS2_MASK_ENABLE
#define RTC1_CFG_CR5SSS_OC1SMPEN
#define RTC1_CFG_GPMUX0_OC1GPIN0SEL
#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT
#define RTC1_CFG_ENABLE_ALARM
#define RTC1_CFG_ENABLE_ALARM_INTERRUPT
#define RTC1_CFG_SS3_ENABLE
#define RTC1_CFG_ENABLE_TRIM
#define RTC1_CFG_CR7SSS_OC1SMPPTRN
#define RTC0_CFG_ENABLE_ALARM_INTERRUPT
#define RTC1_CFG_IC0_INT_ENABLE
#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD
#define RTC1_CFG_CR7SSS_OC1SMPEXP
#define RTC1_CFG_TRIM_INTERVAL
#define RTC0_CFG_ENABLE_ALARM
#define RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN
#define RTC1_CFG_IC3_ENABLE
#define RTC1_CFG_SS3_MASK_ENABLE
#define RTC1_CFG_GPMUX0_OC2GPIN0SEL
#define RTC1_CFG_CR6SSS_OC3SMPONRE
#define RTC1_CFG_IC4_INT_ENABLE
#define RTC1_CFG_ENABLE_ISO_INTERRUPT
#define RTC0_CFG_TRIM_INTERVAL
#define RTC1_CFG_ALARM_VALUE_1
#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE
#define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH
#define RTC1_CFG_GPMUX0_OC2GPIN1SEL
#define RTC1_CFG_TRIM_OPERATION
#define RTC1_CFG_GPMUX1_OC3GPIN0SEL
#define RTC1_CFG_ENABLE_MOD60_ALARM
#define RTC1_CFG_CR5SSS_OC3SMPEN
#define RTC1_CFG_SS1_ENABLE
#define RTC1_CFG_SS4_INT_ENABLE
#define RTC0_CFG_ENABLE_TRIM
#define RTC1_CFG_IC0_ENABLE
#define RTC1_CFG_CR5SSS_OC2SMPEN
#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT
#define RTC1_CFG_GPMUX0_OC1GPIN1SEL
#define RTC1_CFG_ALARM_VALUE_2
#define RTC1_CFG_IC2_ENABLE
#define RTC1_CFG_IC3_INT_ENABLE
#define RTC1_CFG_ENABLE_COUNT_INTERRUPT
#define RTC0_CFG_TRIM_OPERATION
#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT
#define RTC1_CFG_SS4_MASK_ENABLE
#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW
#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT
#define RTC1_CFG_CR7SSS_OC2SMPPTRN
#define RTC1_CFG_COUNT_VALUE_0
#define RTC1_CFG_SS1_MASK_ENABLE
#define RTC1_CFG_CR6SSS_OC3SMPONFE
#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT
#define RTC1_CFG_GPMUX1_OC3GPIN2SEL
#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT
#define RTC1_CFG_ALARM_VALUE_0
#define RTC0_CFG_COUNT_VALUE_0
#define RTC1_CFG_CR6SSS_OC2SMPONFE
#define RTC1_CFG_SS2_ENABLE
#define RTC0_CFG_ALARM_VALUE_1
#define RTC1_CFG_SS4_ENABLE
#define RTC1_CFG_IC2_INT_ENABLE
#define RTC1_CFG_IC3_EDGE_POLARITY
#define RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN
#define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW
#define RTC1_CFG_POW2_TRIM_INTERVAL
#define RTC0_CFG_ALARM_VALUE_0
#define RTC1_CFG_IC0_EDGE_POLARITY
#define RTC1_CFG_CR7SSS_OC3SMPEXP
#define RTC1_CFG_TRIM_VALUE
#define RTC1_CFG_GPMUX1_OC3GPIN1SEL
#define RTC1_CFG_IC_OVER_WRITE_ENABLE
#define RTC1_CFG_SS2_INT_ENABLE
#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT
#define RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN
#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT
#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT
#define RTC0_CFG_COUNT_VALUE_1
#define RTC1_CFG_PRESCALE
#define RTC1_CFG_SS3_AUTO_RELOADING_ENABLE
#define RTC1_CFG_COUNT_VALUE_1
#define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW
#define RTC1_CFG_CR7SSS_OC3SMPPTRN
#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT
#define RTC1_CFG_GPMUX1_OC2GPIN2SEL
#define RTC0_CFG_TRIM_VALUE
#define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH
#define RTC1_CFG_CR7SSS_OC2SMPEXP
#define RTC1_CFG_IC2_EDGE_POLARITY
#define RTC1_CFG_ENABLE_TRIM_INTERRUPT
#define RTC0_CFG_POW2_TRIM_INTERVAL
#define RTC1_CFG_CR6SSS_OC2SMPONRE
#define RTC1_CFG_IC4_ENABLE
#define RTC1_CFG_SS3_INT_ENABLE
#define RTC1_CFG_SS1_INT_ENABLE
#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH
#define RTC1_CFG_GPMUX1_OC1DIFFOUT
#define RTC1_CFG_SS1_MASK_VALUE
#define RTC1_CFG_GPMUX1_OC3DIFFOUT
#define RTC1_CFG_CR6SSS_OC1SMPONFE
#define RTC1_CFG_CR6SSS_OC1SMPONRE