ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_pwr_def.h
1 
13 #ifndef ADI_PWR_DEF_H
14 #define ADI_PWR_DEF_H
15 
16  /*Power control register access key */
17 #define ADI_PMG_KEY (0x4859u)
18 
19  /*Osc control register access key */
20 #define ADI_OSC_KEY (0xCB14u)
21 
22  /*HCLK/PCLK minimum Divider value */
23 #define CLOCK_MIN_DIV_VALUE (0x1u)
24 
25  /*HCLK/PCLK maximum Divider value */
26 #define CLOCK_MAX_DIV_VALUE (32u)
27 
28  /*ADC Clock minimum Divider value */
29 #define ACLK_MIN_DIV_VALUE (0x1u)
30 
31  /*ADC Clock maximum Divider value */
32 #define ACLK_MAX_DIV_VALUE (511u)
33 
34 /* Minimum divider for PLL */
35 #define MINIMUM_PLL_DIVIDER (0x02u)
36 
37 /* Minimum multiplier for PLL */
38 #define MINIMUM_PLL_MULTIPLIER (0x08u)
39 
40 /* Maximum external clock */
41 #define MAXIMUM_EXT_CLOCK (26000000u)
42 
43 /* Macro mapping from ADuCM4x50 to ADuCM302x */
44 #if defined(__ADUCM302x__)
45 
46 #define BITM_CLKG_OSC_CTL_HFOSC_EN BITM_CLKG_OSC_CTL_HFOSCEN
47 #define BITP_CLKG_OSC_CTL_HFOSC_OK BITP_CLKG_OSC_CTL_HFOSCOK
48 #define BITM_CLKG_OSC_CTL_HFX_EN BITM_CLKG_OSC_CTL_HFXTALEN
49 #define BITM_CLKG_CLK_CTL0_PLL_IPSEL BITM_CLKG_CLK_CTL0_SPLLIPSEL
50 #define BITP_CLKG_CLK_CTL0_PLL_IPSEL BITP_CLKG_CLK_CTL0_SPLLIPSEL
51 #define BITM_CLKG_OSC_CTL_LFCLK_MUX BITM_CLKG_OSC_CTL_LFCLKMUX
52 #define BITP_CLKG_OSC_CTL_LFCLK_MUX BITP_CLKG_OSC_CTL_LFCLKMUX
53 #define BITP_CLKG_OSC_CTL_HFX_EN BITP_CLKG_OSC_CTL_HFXTALEN
54 #define BITM_CLKG_OSC_CTL_HFX_OK BITM_CLKG_OSC_CTL_HFXTALOK
55 #define BITP_CLKG_OSC_CTL_LFX_EN BITP_CLKG_OSC_CTL_LFXTALEN
56 #define BITM_CLKG_OSC_CTL_LFX_EN BITM_CLKG_OSC_CTL_LFXTALEN
57 #define BITM_CLKG_OSC_CTL_LFX_OK BITM_CLKG_OSC_CTL_LFXTALOK
58 #define BITP_CLKG_OSC_CTL_HFOSC_EN BITP_CLKG_OSC_CTL_HFOSCEN
59 #define BITM_CLKG_OSC_CTL_HFOSC_OK BITM_CLKG_OSC_CTL_HFOSCOK
60 #define BITM_CLKG_OSC_CTL_LFOSC_OK BITM_CLKG_OSC_CTL_LFOSCOK
61 #define BITM_CLKG_OSC_CTL_LFX_BYP BITM_CLKG_OSC_CTL_LFXTAL_BYPASS
62 
63 #endif /* __ADUCM302x__ */
64 
65 #if defined(__ADUCM4x50__)
66  /* Default osc control register value
67  * LFXTAL ROBUST MODE has to be enabled (system clock anomaly)
68  * LFXTAL ROBUST LOAD has to be 0b11 (system clock anomaly)
69  */
70 #define OSCCTRL_CONFIG_VALUE \
71  ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLK_MUX | \
72  (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSC_EN | \
73  (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFX_EN | \
74  (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFX_EN | \
75  (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFX_MON_EN | \
76  (uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN | \
77  (uint32_t) 1 << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN | \
78  (uint32_t) 3 << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD | \
79  (uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE << BITP_CLKG_OSC_CTL_ROOT_MON_EN | \
80  (uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN )
81 #else
82 
83  /* Default osc control register value */
84 #define OSCCTRL_CONFIG_VALUE \
85  ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLKMUX | \
86  (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSCEN | \
87  (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFXTALEN | \
88  (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFXTALEN | \
89  (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFXTAL_MON_EN )
90 #endif /* __ADUCM4x50__ */
91 
92 #if defined(__ADUCM4x50__)
93  /* Default clock control register-0 value */
94 #define CLOCK_CTL0_CONFIG_VALUE \
95  ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \
96  (uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT << BITP_CLKG_CLK_CTL0_CLKOUT | \
97  (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \
98  (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_PLL_IPSEL | \
99  (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \
100  (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE )
101 #else
102 /* Default clock control register-0 value */
103 #define CLOCK_CTL0_CONFIG_VALUE \
104  ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \
105  (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \
106  (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_SPLLIPSEL | \
107  (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \
108  (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE )
109 #endif
110 
111  /* Default clock control register-1 value */
112 #define CLOCK_CTL1_CONFIG_VALUE \
113  ( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_HCLKDIVCNT | \
114  (uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_PCLKDIVCNT | \
115  (uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_ACLKDIVCNT )
116 
117 #if defined(__ADUCM4x50__)
118 /* Default clock control register-2 value */
119 #define CLOCK_CTL2_CONFIG_VALUE \
120  ( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1 << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN | \
121  (uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL )
122 
123 #endif /* __ADUCM4x50__ */
124 
125  /* Default clock control register-3 value */
126 #define CLOCK_CTL3_CONFIG_VALUE \
127  ( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR << BITP_CLKG_CLK_CTL3_SPLLNSEL | \
128  (uint32_t) ADI_PWR_SPLL_ENABLE_DIV2 << BITP_CLKG_CLK_CTL3_SPLLDIV2 | \
129  (uint32_t) ADI_PWR_SPLL_ENABLE << BITP_CLKG_CLK_CTL3_SPLLEN | \
130  (uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL3_SPLLIE | \
131  (uint32_t) ADI_PWR_SPLL_DIV_FACTOR << BITP_CLKG_CLK_CTL3_SPLLMSEL | \
132  (uint32_t) ADI_PWR_SPLL_ENABLE_MUL2 << BITP_CLKG_CLK_CTL3_SPLLMUL2 )
133 
134 #if defined(__ADUCM4x50__)
135  /* Default clock control register-5 value */
136 #define CLOCK_CTL5_CONFIG_VALUE \
137  ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \
138  (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \
139  (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \
140  (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \
141  (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \
142  (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF | \
143  (uint32_t) ADI_PWR_TIMER_RGB_ENABLE << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF )
144 #else
145  /* Default clock control register-5 value */
146 #define CLOCK_CTL5_CONFIG_VALUE \
147  ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \
148  (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \
149  (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \
150  (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \
151  (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \
152  (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF )
153 #endif
154 
155 /* Default configuration for Power supply monitor Interrupt Enable Register */
156 #define PWM_INTERRUPT_CONFIG \
157  ( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT << BITP_PMG_IEN_VBAT | \
158  (uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGUNDR | \
159  (uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGOVR | \
160  (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT << BITP_PMG_IEN_IENBAT | \
161  (uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT << BITP_PMG_IEN_RANGEBAT )
162 
163  /* Default configuration for Power Mode Register */
164  #define PWM_PWRMOD_CONFIG \
165  ( (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING << BITP_PMG_PWRMOD_MONVBATN )
166 
167 #if defined(__ADUCM4x50__)
168 /* Default configuration for HP Buck Control register */
169 #define PWM_HPBUCK_CONTROL \
170  ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN | \
171  (uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE << BITP_PMG_CTL1_HPBUCK_LD_MODE | \
172  (uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE )
173 #else
174 /* Default configuration for HP Buck Control register */
175 #define PWM_HPBUCK_CONTROL \
176  ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN )
177 #endif
178 
179  /*Selecting HFOSC as input for generating root clock*/
180 #define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX)
181 
182  /*Selecting HFXTAL as input for generating root clock*/
183 #define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX)
184 
185  /*Selecting SPLL as input for generating root clock*/
186 #define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX)
187 
188  /*Selecting GPIO as input for generating root clock*/
189 #define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX)
190 
191 /* Interrupt handler for the battery voltage interrupt */
192 void Battery_Voltage_Int_Handler(void);
193 /* Interrupt handler for the VREG under/over voltage interrupt */
194 void Vreg_over_Int_Handler(void);
195 /* Interrupt handler for PLL interrupts. */
196 void PLL_Int_Handler(void);
197 /*Interrupt handler for oscillator interrupts.*/
198 void Crystal_osc_Int_Handler(void);
199 
200 #endif /* ADI_PWR_DEF_H */
201 
202 
203 /*
204 ** EOF
205 */