ADuCM4x50 Device Drivers API Reference Manual
Release 4.0.0.0
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Macros | |
#define | ADI_SPI1_MASTER_MODE (1u) |
#define | ADI_SPI1_CFG_BIT_RATE (2000000u) |
#define | ADI_SPI1_CFG_ENABLE (0u) |
#define | ADI_SPI1_CFG_CLK_PHASE (0u) |
#define | ADI_SPI1_CFG_CLK_POLARITY (0u) |
#define | ADI_SPI1_CFG_WIRED_OR (0u) |
#define | ADI_SPI1_CFG_LSB_MSB (0u) |
#define | ADI_SPI1_CFG_TRANSFER_INITIATE (0u) |
#define | ADI_SPI1_CFG_TX_UNDERFLOW (0u) |
#define | ADI_SPI1_CFG_RX_OVERFLOW (0u) |
#define | ADI_SPI1_CFG_MISO_ENABLE (0u) |
#define | ADI_SPI1_CFG_LOOPBACK (0u) |
#define | ADI_SPI1_CFG_CONTINUOUS (0u) |
#define | ADI_SPI1_CFG_RX_FLUSH (0u) |
#define | ADI_SPI1_CFG_TX_FLUSH (0u) |
#define | ADI_SPI1_CFG_CSERR_RESET (0u) |
#define | ADI_SPI1_CFG_CLK_DIV (0u) |
#define | ADI_SPI1_CFG_HFM (0u) |
#define | ADI_SPI1_CFG_CS_ERR (0u) |
#define | ADI_SPI1_CFG_CS_IRQ |
#define ADI_SPI1_MASTER_MODE (1u) |
If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0.
Definition at line 196 of file adi_spi_config.h.
#define ADI_SPI1_CFG_BIT_RATE (2000000u) |
Set this macro to the SPI1 bit rate in hertz
Definition at line 199 of file adi_spi_config.h.
#define ADI_SPI1_CFG_ENABLE (0u) |
SPI1 enable
SPI configuration register: Bit[0]
1 - Enable SPI
0 - Disable SPI
Definition at line 205 of file adi_spi_config.h.
#define ADI_SPI1_CFG_CLK_PHASE (0u) |
SPI1 clock phase mode
SPI configuration register: Bit[2]
1 - Serial clock pulses at the beginning of each serial bit transfer.
0 - Serial clock pulses at the end of each serial bit transfer.
Definition at line 211 of file adi_spi_config.h.
#define ADI_SPI1_CFG_CLK_POLARITY (0u) |
SPI1 clock polarity
SPI configuration register: Bit[3]
1 - Serial clock idles high.
0 - Serial clock idles low.
Definition at line 221 of file adi_spi_config.h.
#define ADI_SPI1_CFG_WIRED_OR (0u) |
SPI1 wired OR mode
SPI configuration register: Bit[4]
1 - Enables open circuit output enable.
0 - Normal output levels.
Definition at line 228 of file adi_spi_config.h.
#define ADI_SPI1_CFG_LSB_MSB (0u) |
SPI1 LSB/MSB
SPI configuration register: Bit[5]
1 - MSB transmitted first.
0 - LSB transmitted first.
Definition at line 235 of file adi_spi_config.h.
#define ADI_SPI1_CFG_TRANSFER_INITIATE (0u) |
SPI1 transfer initiate
SPI configuration register: Bit[6]
1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.
0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.
Definition at line 242 of file adi_spi_config.h.
#define ADI_SPI1_CFG_TX_UNDERFLOW (0u) |
SPI1 Tx FIFO transfers zeros or last bit upon underflow
SPI configuration register: Bit[7]
1 - Tx FIFO sends zeros upon underflow.
0 - Tx FIFO repeats last bit upon underflow.
Definition at line 249 of file adi_spi_config.h.
#define ADI_SPI1_CFG_RX_OVERFLOW (0u) |
SPI1 Rx FIFO overflows with received data or data is discarded
SPI configuration register: Bit[8]
1 - Rx FIFO receives data upon overflow.
0 - Rx FIFO discards received data upon overflow.
Definition at line 256 of file adi_spi_config.h.
#define ADI_SPI1_CFG_MISO_ENABLE (0u) |
SPI1 slave mode MISO enable
SPI configuration register: Bit[9]
1 - MISO operates as normal in slave mode.
0 - MISO is disabled in slave mode.
Definition at line 263 of file adi_spi_config.h.
#define ADI_SPI1_CFG_LOOPBACK (0u) |
SPI1 internal loopback enable
SPI configuration register: Bit[10]
1 - MISO and MOSI is loopbacked internally.
0 - MISO and MOSI operates normally.
Definition at line 270 of file adi_spi_config.h.
#define ADI_SPI1_CFG_CONTINUOUS (0u) |
SPI1 transfer and interrupt mode
SPI configuration register: Bit[11]
1 - SPI continuous transfers in which CS remains asserted until Tx is empty.
0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.
Definition at line 276 of file adi_spi_config.h.
#define ADI_SPI1_CFG_RX_FLUSH (0u) |
SPI1 Rx FIFO flush enable
SPI configuration register: Bit[12]
1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.
0 - Rx FIFO flush is disabled.
Definition at line 282 of file adi_spi_config.h.
#define ADI_SPI1_CFG_TX_FLUSH (0u) |
SPI1 Tx FIFO flush enable
SPI configuration register: Bit[13]
1 - Tx FIFO is flushed.
0 - Tx FIFO flush is disabled.
Definition at line 289 of file adi_spi_config.h.
#define ADI_SPI1_CFG_CSERR_RESET (0u) |
Reset Mode for CSERR.
SPI1 configuration register: Bit[14]
0 - To continue from where it stopped. SPI can receive the remaining bits when CS gets asserted and Cortex has to ignore the CSERR interrupt.
1 - To enable resetting the bit counter and reset if there is a CS error condition and the Cortex is expected to clear the SPI_EN bit.
Definition at line 299 of file adi_spi_config.h.
#define ADI_SPI1_CFG_CLK_DIV (0u) |
SPI1 clock divide
SPI baud rate selection register: Bit[0:5]
Value between 0-63 that is used to divide the UCLK to generate the SPI serial clock.
Definition at line 306 of file adi_spi_config.h.
#define ADI_SPI1_CFG_HFM (0u) |
SPI1 high frequency mode
SPI baud rate selection register: Bit[6]
1 - High frequency mode enabled.
0 - High frequency mode disabled.
Definition at line 313 of file adi_spi_config.h.
#define ADI_SPI1_CFG_CS_ERR (0u) |
SPI1 reset mode for CSERR
SPI baud rate selection register: Bit[7]
1 - clear bit counter on CS error.
0 - do not clear bit counter on CS error.
Definition at line 320 of file adi_spi_config.h.
#define ADI_SPI1_CFG_CS_IRQ |
SPI1 CS interrupt
SPI baud rate selection register: Bit[8]
1 - In continuous mode, generate interrupt on CS.
0 - In continuous mode, do not generate interrupt on CS.
Definition at line 327 of file adi_spi_config.h.