ADuCM4x50 Device Drivers API Reference Manual
Release 4.0.0.0
adi_dma.h
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#ifndef ADI_DMA__H__
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#define ADI_DMA__H__
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#include <adi_callback.h>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
/* __cplusplus */
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/*============= D E F I N E S =============*/
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/*============= D A T A T Y P E S =============*/
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typedef
enum
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{
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ADI_DMA_INCR_1_BYTE
= 0x00u,
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ADI_DMA_INCR_2_BYTE
= 0x01u,
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ADI_DMA_INCR_4_BYTE
= 0x02u,
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ADI_DMA_INCR_NONE
= 0x03u,
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ADI_DMA_DECR_1_BYTE
= 0x10u,
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ADI_DMA_DECR_2_BYTE
= 0x11u,
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ADI_DMA_DECR_4_BYTE
= 0x12u
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}
ADI_DMA_INCR_TYPE
;
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typedef
enum
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{
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ADI_DMA_EVENT_BUFFER_PROCESSED
,
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ADI_DMA_EVENT_ERR_BUS
,
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ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR
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}
ADI_DMA_EVENT
;
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typedef
enum
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{
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ADI_DMA_WIDTH_1_BYTE
= 0x0,
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ADI_DMA_WIDTH_2_BYTE
= 0x1,
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ADI_DMA_WIDTH_4_BYTE
= 0x2
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}
ADI_DMA_WIDTH_TYPE
;
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typedef
enum
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{
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ADI_DMA_RPOWER_1
= 0,
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ADI_DMA_RPOWER_2
,
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ADI_DMA_RPOWER_4
,
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ADI_DMA_RPOWER_8
,
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ADI_DMA_RPOWER_16
,
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ADI_DMA_RPOWER_32
,
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ADI_DMA_RPOWER_64
,
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ADI_DMA_RPOWER_128
,
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ADI_DMA_RPOWER_256
,
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ADI_DMA_RPOWER_512
,
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ADI_DMA_RPOWER_1024
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}
ADI_DMA_RPOWER
;
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typedef
enum
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{
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ADI_DMA_MODE_INVALID
,
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ADI_DMA_MODE_BASIC
,
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ADI_DMA_MODE_AUTO
,
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ADI_DMA_MODE_PING_PONG
,
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ADI_DMA_MODE_MSG
,
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ADI_DMA_MODE_PSG
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}
ADI_DMA_MODE
;
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typedef
enum
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{
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ADI_DMA_PRIORITY_DEFAULT
= 0,
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ADI_DMA_PRIORITY_HIGH
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}
ADI_DMA_PRIORITY
;
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typedef
enum
{
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ADI_DMA_SUCCESS
,
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ADI_DMA_ERR_NOT_INITIALIZED
,
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ADI_DMA_ERR_INVALID_PARAMETER
,
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}
ADI_DMA_RESULT
;
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typedef
enum
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{
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SPI2_TX_CHANn = 0,
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SPI2_RX_CHANn = 1,
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SPORT0A_CHANn = 2,
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SPORT0B_CHANn = 3,
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SPI0_TX_CHANn = 4,
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SPI0_RX_CHANn = 5,
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SPI1_TX_CHANn = 6,
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SPI1_RX_CHANn = 7,
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UART0_TX_CHANn = 8,
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UART0_RX_CHANn = 9,
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I2CS_TX_CHANn = 10,
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I2CS_RX_CHANn = 11,
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I2CM_CHANn = 12,
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AES0_IN_CHANn = 13,
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AES0_OUT_CHANn = 14,
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FLASH_CHANn = 15,
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SIP0_CHANn = 16,
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SIP1_CHANn = 17,
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SIP2_CHANn = 18,
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SIP3_CHANn = 19,
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SIP4_CHANn = 20,
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SIP5_CHANn = 21,
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SIP6_CHANn = 22,
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SIP7_CHANn = 23,
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ADC0_CHANn = 24,
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#if defined(__ADUCM4x50__)
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UART1_TX_CHANn = 25,
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UART1_RX_CHANn = 26,
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#endif
/* __ADUCM4x50__ */
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NUM_DMA_CHANNELSn = 27
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} DMA_CHANn_TypeDef;
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typedef
struct
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{
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__IO uint32_t
DMASRCEND
;
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__IO uint32_t
DMADSTEND
;
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__IO uint32_t
DMACDC
;
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uint32_t RESERVED;
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}
ADI_DCC_TypeDef
;
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/* Bit Position for DMA Descriptor Control */
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#define DMA_BITP_CTL_DST_INC (30u)
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#define DMA_BITP_CTL_SRC_INC (26u)
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#define DMA_BITP_CTL_SRC_SIZE (24u)
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#define DMA_BITP_CTL_R_POWER (14u)
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#define DMA_BITP_CTL_N_MINUS_1 (4u)
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#define DMA_BITP_CTL_CYCLE_CTL (0u)
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/* Bit Mask for DMA Descriptor Control */
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#define DMA_BITM_CTL_DST_INC ((0x00000003u) << DMA_BITP_CTL_DST_INC)
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#define DMA_BITM_CTL_SRC_INC ((0x00000003u) << DMA_BITP_CTL_SRC_INC)
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#define DMA_BITM_CTL_SRC_SIZE ((0x00000003u) << DMA_BITP_CTL_SRC_SIZE)
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#define DMA_BITM_CTL_R_POWER ((0x0000000Fu) << DMA_BITP_CTL_R_POWER)
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#define DMA_BITM_CTL_N_MINUS_1 ((0x000003FFu) << DMA_BITP_CTL_N_MINUS_1)
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#define DMA_BITM_CTL_CYCLE_CTL ((0x00000007u) << DMA_BITP_CTL_CYCLE_CTL)
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/* Enum for the DMA Descriptor Cycle Control */
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#define DMA_ENUM_CTL_CYCLE_CTL_INVALID (0u)
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#define DMA_ENUM_CTL_CYCLE_CTL_BASIC (1u)
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#define DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ (2u)
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#define DMA_ENUM_CTL_CYCLE_CTL_PING_PONG (3u)
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#define DMA_ENUM_CTL_CYCLE_CTL_MSG_PRI (4u)
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#define DMA_ENUM_CTL_CYCLE_CTL_MSG_ALT (5u)
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#define DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI (6u)
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#define DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT (7u)
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#define DMA_BITM_INCR_TYPE_DECR (0x10u)
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#define DMA_BITM_OCTL_SRC_DECR (0x01u)
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#define DMA_BITM_OCTL_DST_DECR (0x02u)
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#define DMA_BITM_OCTL_SRC_INCR (0x04u)
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#define DMA_BITM_OCTL_DST_INCR (0x08u)
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#define DMA_TRANSFER_LIMIT (1024u)
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/* pointer to the primary CCD array */
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extern
ADI_DCC_TypeDef
*
const
pPrimaryCCD;
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/* pointer to the alternate CCD array */
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extern
ADI_DCC_TypeDef
*
const
pAlternateCCD;
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/*========== DMA API DECLARATIONS ==========*/
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/* Initialize the DMA and enable it */
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extern
void
adi_dma_Init
(
void
);
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/* Force a DMA re-initialization */
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extern
void
adi_dma_ReInit
(
void
);
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/* Enable/Disable the DMA */
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extern
void
adi_dma_Enable
(
const
bool
enable);
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extern
ADI_DMA_RESULT
adi_dma_RegisterCallback
(
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DMA_CHANn_TypeDef
const
eChannelID,
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ADI_CALLBACK
const
pfCallback,
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void
*
const
pCBParam
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);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* include guard */
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/*
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** EOF
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*/
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ADI_DMA_RPOWER_16
Definition:
adi_dma.h:87
ADI_DMA_INCR_2_BYTE
Definition:
adi_dma.h:46
adi_dma_RegisterCallback
ADI_DMA_RESULT adi_dma_RegisterCallback(DMA_CHANn_TypeDef const eChannelID, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register a call-back function for a DMA channel.
Definition:
adi_dma.c:232
ADI_DMA_RPOWER_8
Definition:
adi_dma.h:86
ADI_DMA_RPOWER_512
Definition:
adi_dma.h:92
ADI_DMA_MODE_MSG
Definition:
adi_dma.h:106
ADI_DCC_TypeDef::DMASRCEND
__IO uint32_t DMASRCEND
Definition:
adi_dma.h:176
ADI_DMA_RPOWER_32
Definition:
adi_dma.h:88
adi_dma_Enable
void adi_dma_Enable(const bool enable)
Enable/Disable the DMA.
Definition:
adi_dma.c:206
ADI_DMA_PRIORITY
ADI_DMA_PRIORITY
Definition:
adi_dma.h:114
ADI_DMA_EVENT_BUFFER_PROCESSED
Definition:
adi_dma.h:61
ADI_DMA_RPOWER_1
Definition:
adi_dma.h:83
ADI_DMA_RPOWER_256
Definition:
adi_dma.h:91
ADI_DMA_DECR_2_BYTE
Definition:
adi_dma.h:51
ADI_DMA_INCR_1_BYTE
Definition:
adi_dma.h:45
ADI_DMA_SUCCESS
Definition:
adi_dma.h:125
adi_dma_ReInit
void adi_dma_ReInit(void)
Force a DMA re-initialization.
Definition:
adi_dma.c:193
ADI_DMA_RPOWER
ADI_DMA_RPOWER
Definition:
adi_dma.h:81
ADI_DMA_RPOWER_4
Definition:
adi_dma.h:85
ADI_DMA_MODE_AUTO
Definition:
adi_dma.h:104
ADI_DMA_INCR_4_BYTE
Definition:
adi_dma.h:47
ADI_DMA_DECR_1_BYTE
Definition:
adi_dma.h:50
ADI_DMA_RPOWER_64
Definition:
adi_dma.h:89
ADI_DMA_WIDTH_4_BYTE
Definition:
adi_dma.h:74
ADI_DMA_WIDTH_2_BYTE
Definition:
adi_dma.h:73
ADI_DMA_MODE
ADI_DMA_MODE
Definition:
adi_dma.h:100
ADI_DMA_PRIORITY_DEFAULT
Definition:
adi_dma.h:116
ADI_DMA_WIDTH_1_BYTE
Definition:
adi_dma.h:72
ADI_DMA_ERR_NOT_INITIALIZED
Definition:
adi_dma.h:126
ADI_DMA_MODE_INVALID
Definition:
adi_dma.h:102
ADI_DMA_DECR_4_BYTE
Definition:
adi_dma.h:52
ADI_DMA_EVENT
ADI_DMA_EVENT
Definition:
adi_dma.h:59
ADI_DMA_WIDTH_TYPE
ADI_DMA_WIDTH_TYPE
Definition:
adi_dma.h:70
ADI_DMA_INCR_TYPE
ADI_DMA_INCR_TYPE
Definition:
adi_dma.h:43
ADI_DCC_TypeDef::DMADSTEND
__IO uint32_t DMADSTEND
Definition:
adi_dma.h:177
ADI_DMA_ERR_INVALID_PARAMETER
Definition:
adi_dma.h:127
ADI_DCC_TypeDef
Definition:
adi_dma.h:174
ADI_DMA_MODE_PSG
Definition:
adi_dma.h:107
ADI_DMA_MODE_BASIC
Definition:
adi_dma.h:103
ADI_DMA_PRIORITY_HIGH
Definition:
adi_dma.h:117
ADI_DMA_RPOWER_2
Definition:
adi_dma.h:84
ADI_DCC_TypeDef::DMACDC
__IO uint32_t DMACDC
Definition:
adi_dma.h:178
adi_dma_Init
void adi_dma_Init(void)
Initialize the DMA peripheral.
Definition:
adi_dma.c:155
ADI_DMA_RPOWER_128
Definition:
adi_dma.h:90
ADI_DMA_EVENT_ERR_BUS
Definition:
adi_dma.h:62
ADI_DMA_INCR_NONE
Definition:
adi_dma.h:48
ADI_DMA_RESULT
ADI_DMA_RESULT
Definition:
adi_dma.h:124
ADI_DMA_RPOWER_1024
Definition:
adi_dma.h:93
ADI_DMA_MODE_PING_PONG
Definition:
adi_dma.h:105
ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR
Definition:
adi_dma.h:63
Include
drivers
dma
adi_dma.h
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