ADuCM4x50 Device Drivers API Reference Manual
Release 4.0.0.0
adi_pwr_def.h
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#ifndef ADI_PWR_DEF_H
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#define ADI_PWR_DEF_H
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/*Power control register access key */
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#define ADI_PMG_KEY (0x4859u)
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/*Osc control register access key */
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#define ADI_OSC_KEY (0xCB14u)
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/*HCLK/PCLK minimum Divider value */
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#define CLOCK_MIN_DIV_VALUE (0x1u)
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/*HCLK/PCLK maximum Divider value */
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#define CLOCK_MAX_DIV_VALUE (32u)
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/*ADC Clock minimum Divider value */
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#define ACLK_MIN_DIV_VALUE (0x1u)
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/*ADC Clock maximum Divider value */
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#define ACLK_MAX_DIV_VALUE (511u)
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/* Minimum divider for PLL */
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#define MINIMUM_PLL_DIVIDER (0x02u)
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/* Minimum multiplier for PLL */
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#define MINIMUM_PLL_MULTIPLIER (0x08u)
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/* Maximum external clock */
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#define MAXIMUM_EXT_CLOCK (26000000u)
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/* Macro mapping from ADuCM4x50 to ADuCM302x */
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#if defined(__ADUCM302x__)
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#define BITM_CLKG_OSC_CTL_HFOSC_EN BITM_CLKG_OSC_CTL_HFOSCEN
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#define BITP_CLKG_OSC_CTL_HFOSC_OK BITP_CLKG_OSC_CTL_HFOSCOK
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#define BITM_CLKG_OSC_CTL_HFX_EN BITM_CLKG_OSC_CTL_HFXTALEN
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#define BITM_CLKG_CLK_CTL0_PLL_IPSEL BITM_CLKG_CLK_CTL0_SPLLIPSEL
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#define BITP_CLKG_CLK_CTL0_PLL_IPSEL BITP_CLKG_CLK_CTL0_SPLLIPSEL
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#define BITM_CLKG_OSC_CTL_LFCLK_MUX BITM_CLKG_OSC_CTL_LFCLKMUX
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#define BITP_CLKG_OSC_CTL_LFCLK_MUX BITP_CLKG_OSC_CTL_LFCLKMUX
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#define BITP_CLKG_OSC_CTL_HFX_EN BITP_CLKG_OSC_CTL_HFXTALEN
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#define BITM_CLKG_OSC_CTL_HFX_OK BITM_CLKG_OSC_CTL_HFXTALOK
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#define BITP_CLKG_OSC_CTL_LFX_EN BITP_CLKG_OSC_CTL_LFXTALEN
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#define BITM_CLKG_OSC_CTL_LFX_EN BITM_CLKG_OSC_CTL_LFXTALEN
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#define BITM_CLKG_OSC_CTL_LFX_OK BITM_CLKG_OSC_CTL_LFXTALOK
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#define BITP_CLKG_OSC_CTL_HFOSC_EN BITP_CLKG_OSC_CTL_HFOSCEN
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#define BITM_CLKG_OSC_CTL_HFOSC_OK BITM_CLKG_OSC_CTL_HFOSCOK
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#define BITM_CLKG_OSC_CTL_LFOSC_OK BITM_CLKG_OSC_CTL_LFOSCOK
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#define BITM_CLKG_OSC_CTL_LFX_BYP BITM_CLKG_OSC_CTL_LFXTAL_BYPASS
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#endif
/* __ADUCM302x__ */
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#if defined(__ADUCM4x50__)
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/* Default osc control register value
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* LFXTAL ROBUST MODE has to be enabled (system clock anomaly)
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* LFXTAL ROBUST LOAD has to be 0b11 (system clock anomaly)
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*/
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#define OSCCTRL_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLK_MUX | \
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(uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSC_EN | \
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(uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFX_EN | \
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(uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFX_EN | \
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(uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFX_MON_EN | \
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(uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN | \
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(uint32_t) 1 << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN | \
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(uint32_t) 3 << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD | \
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(uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE << BITP_CLKG_OSC_CTL_ROOT_MON_EN | \
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(uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN )
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#else
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/* Default osc control register value */
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#define OSCCTRL_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLKMUX | \
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(uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSCEN | \
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(uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFXTALEN | \
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(uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFXTALEN | \
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(uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFXTAL_MON_EN )
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#endif
/* __ADUCM4x50__ */
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#if defined(__ADUCM4x50__)
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/* Default clock control register-0 value */
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#define CLOCK_CTL0_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \
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(uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT << BITP_CLKG_CLK_CTL0_CLKOUT | \
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(uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \
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(uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_PLL_IPSEL | \
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(uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \
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(uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE )
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#else
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/* Default clock control register-0 value */
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#define CLOCK_CTL0_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \
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(uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \
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(uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_SPLLIPSEL | \
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(uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \
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(uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE )
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#endif
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/* Default clock control register-1 value */
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#define CLOCK_CTL1_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_HCLKDIVCNT | \
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(uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_PCLKDIVCNT | \
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(uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_ACLKDIVCNT )
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#if defined(__ADUCM4x50__)
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/* Default clock control register-2 value */
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#define CLOCK_CTL2_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1 << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN | \
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(uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL )
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#endif
/* __ADUCM4x50__ */
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/* Default clock control register-3 value */
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#define CLOCK_CTL3_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR << BITP_CLKG_CLK_CTL3_SPLLNSEL | \
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(uint32_t) ADI_PWR_SPLL_ENABLE_DIV2 << BITP_CLKG_CLK_CTL3_SPLLDIV2 | \
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(uint32_t) ADI_PWR_SPLL_ENABLE << BITP_CLKG_CLK_CTL3_SPLLEN | \
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(uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL3_SPLLIE | \
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(uint32_t) ADI_PWR_SPLL_DIV_FACTOR << BITP_CLKG_CLK_CTL3_SPLLMSEL | \
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(uint32_t) ADI_PWR_SPLL_ENABLE_MUL2 << BITP_CLKG_CLK_CTL3_SPLLMUL2 )
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#if defined(__ADUCM4x50__)
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/* Default clock control register-5 value */
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#define CLOCK_CTL5_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \
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(uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \
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(uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \
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(uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \
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(uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \
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(uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF | \
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(uint32_t) ADI_PWR_TIMER_RGB_ENABLE << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF )
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#else
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/* Default clock control register-5 value */
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#define CLOCK_CTL5_CONFIG_VALUE \
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( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \
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(uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \
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(uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \
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(uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \
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(uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \
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(uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF )
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#endif
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/* Default configuration for Power supply monitor Interrupt Enable Register */
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#define PWM_INTERRUPT_CONFIG \
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( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT << BITP_PMG_IEN_VBAT | \
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(uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGUNDR | \
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(uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGOVR | \
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(uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT << BITP_PMG_IEN_IENBAT | \
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(uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT << BITP_PMG_IEN_RANGEBAT )
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/* Default configuration for Power Mode Register */
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#define PWM_PWRMOD_CONFIG \
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( (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING << BITP_PMG_PWRMOD_MONVBATN )
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#if defined(__ADUCM4x50__)
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/* Default configuration for HP Buck Control register */
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#define PWM_HPBUCK_CONTROL \
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( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN | \
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(uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE << BITP_PMG_CTL1_HPBUCK_LD_MODE | \
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(uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE )
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#else
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/* Default configuration for HP Buck Control register */
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#define PWM_HPBUCK_CONTROL \
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( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN )
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#endif
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/*Selecting HFOSC as input for generating root clock*/
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#define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX)
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/*Selecting HFXTAL as input for generating root clock*/
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#define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX)
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/*Selecting SPLL as input for generating root clock*/
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#define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX)
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/*Selecting GPIO as input for generating root clock*/
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#define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX)
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/* Interrupt handler for the battery voltage interrupt */
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void
Battery_Voltage_Int_Handler(
void
);
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/* Interrupt handler for the VREG under/over voltage interrupt */
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void
Vreg_over_Int_Handler(
void
);
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/* Interrupt handler for PLL interrupts. */
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void
PLL_Int_Handler(
void
);
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/*Interrupt handler for oscillator interrupts.*/
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void
Crystal_osc_Int_Handler(
void
);
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#endif
/* ADI_PWR_DEF_H */
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/*
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** EOF
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*/
Source
drivers
pwr
adi_pwr_def.h
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