40 #include <adi_processor.h> 46 #include <drivers/spi/adi_spi.h> 47 #include <drivers/pwr/adi_pwr.h> 48 #include <drivers/general/adi_drivers_general.h> 49 #include <adi_callback.h> 50 #include <rtos_map/adi_rtos_map.h> 51 #include "adi_spi_config.h" 52 #include <adi_cyclecount.h> 85 #pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm143,Pm152,Pm140,Pm031 89 #include "adi_spi_data.c" 94 #define ADI_SPI_VALIDATE_HANDLE(h) ((spi_device_info[0].hDevice != (h)) && (spi_device_info[1].hDevice != (h)) && (spi_device_info[2].hDevice != (h))) 101 static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD);
103 static void TxDmaErrorCallback (
void *pCBParam, uint32_t Event,
void *pArg);
104 static void RxDmaErrorCallback (
void *pCBParam, uint32_t Event,
void *pArg);
108 void SPI0_Int_Handler(
void);
109 void SPI1_Int_Handler(
void);
110 void SPI2_Int_Handler(
void);
111 void DMA_SPI0_TX_Int_Handler(
void);
112 void DMA_SPI0_RX_Int_Handler(
void);
113 void DMA_SPI1_TX_Int_Handler(
void);
114 void DMA_SPI1_RX_Int_Handler(
void);
115 void DMA_SPIH_TX_Int_Handler(
void);
116 void DMA_SPIH_RX_Int_Handler(
void);
156 uint32_t nMemorySize,
162 if (nDeviceNum >= ADI_SPI_NUM_INSTANCES)
167 if (nMemorySize !=
sizeof(
struct __ADI_SPI_DEV_DATA_TYPE))
172 if( spi_device_info[nDeviceNum].hDevice != NULL )
194 memset(pDevMemory,0,nMemorySize);
195 hDevice->pDevInfo = &spi_device_info[nDeviceNum];
196 spi_device_info[nDeviceNum].hDevice = (ADI_SPI_DEV_DATA_TYPE *)pDevMemory;
204 hDevice->pSpi = spi_device_info[nDeviceNum].pSpiRegs;
210 ADI_SPI_CFG_TYPE
const* pSPICfg = &gSPICfg[nDeviceNum];
211 hDevice->pSpi->CTL = pSPICfg->SPI_CTL;
212 hDevice->pSpi->DIV = pSPICfg->SPI_DIV;
216 hDevice->pSpi->CTL |= BITM_SPI_CTL_SPIEN;
255 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
264 NVIC_DisableIRQ(hDevice->pDevInfo->eIRQn);
271 hDevice->pDevInfo->hDevice = NULL;
292 if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
298 hDevice->pfCallback = pfCallback;
299 hDevice->pCBParam = pCBParam;
341 if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
345 if (nMode > ADI_SPI_IRQ_PARAM) {
351 uint16_t ien = hDevice->pSpi->IEN;
352 ien = ien & (uint16_t)~BITM_SPI_IEN_IRQMODE;
353 ien = ien | (nMode & BITM_SPI_IEN_IRQMODE);
354 hDevice->pSpi->IEN = ien;
381 if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
388 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
390 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
415 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
423 hDevice->pSpi->CTL |= (BITM_SPI_CTL_LOOPBACK);
425 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_LOOPBACK;
450 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
456 ADI_INT_STATUS_ALLOC();
457 ADI_ENTER_CRITICAL_REGION();
459 hDevice->pSpi->CTL |= (ADI_SPI_MASTERCON_INITIALIZER);
461 hDevice->pSpi->CNT = 0u;
462 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_MASEN;
463 hDevice->pSpi->CTL |= (ADI_SPI_SLAVECON_INITIALIZER);
465 ADI_EXIT_CRITICAL_REGION();
493 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
501 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RXOF);
503 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_RXOF;
531 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
538 hDevice->pSpi->CTL |= (BITM_SPI_CTL_ZEN);
540 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_ZEN;
571 uint32_t incoming_clock;
575 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
587 if ((2U * Hertz) > incoming_clock)
593 Div = (uint16_t) ((incoming_clock / Hertz) >> 1U) - 1U;
596 if (Div != (Div & BITM_SPI_DIV_VALUE))
602 hDevice->pSpi->DIV = Div;
628 uint32_t incoming_clock;
633 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
638 Div = hDevice->pSpi->DIV;
646 *pnBitrate= (incoming_clock / (Div + 1U)) >> 1U;
684 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
691 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPOL);
693 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPOL;
719 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
725 hDevice->ChipSelect = eChipSelect;
763 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
770 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPHA);
772 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPHA;
807 hDevice->bBlockingMode =
true;
809 hDevice->bBlockingMode =
false;
847 volatile uint16_t nStatus;
850 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
874 hDevice->bDmaMode = pXfr->
bDMA;
875 hDevice->bRdCtlMode = pXfr->
bRD_CTL;
876 hDevice->bTransferComplete =
false;
895 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH);
911 if( hDevice->bDmaMode==
true ) {
917 hDevice->pSpi->IEN &= (uint16_t)~(BITM_SPI_IEN_XFRDONE);
921 uint16_t activeInterrupts = BITM_SPI_IEN_XFRDONE;
923 if( hDevice->TxRemaining ) {
924 activeInterrupts |= BITM_SPI_IEN_TXUNDR;
927 if( hDevice->RxRemaining ) {
928 activeInterrupts |= BITM_SPI_IEN_RXOVR;
931 hDevice->pSpi->IEN |= activeInterrupts;
939 if( hDevice->RxRemaining == 0u) {
940 hDevice->pSpi->CTL |= ( BITM_SPI_CTL_TIM );
946 nStatus = hDevice->pSpi->STAT;
947 hDevice->pSpi->STAT = nStatus;
950 hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN);
953 hDevice->pSpi->CS_CTL = hDevice->ChipSelect;
955 StartTransaction(hDevice, pXfr);
959 if (hDevice->bBlockingMode ==
true)
979 if( (hDevice->bDmaMode ==
true) && (hDevice->bRdCtlMode ==
true) && (pXfr->
ReceiverBytes == 1u))
982 hDevice->bDmaMode =
false;
985 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
986 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
989 hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
996 uint16_t dmaFlags = 0u;
998 if( hDevice->bDmaMode ==
true)
1000 dmaFlags = BITM_SPI_DMA_EN;
1005 uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
1008 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
1011 pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
1014 pADI_DMA0->EN_SET = 1U << TxChanNum;
1017 pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
1020 pADI_DMA0->ALT_CLR = 1U << TxChanNum;
1023 if( (sz & 1U) != 0u )
1030 pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->
pTransmitter + (sz - 2U));
1032 pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX;
1034 pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)
ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
1037 ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
1038 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1040 dmaFlags |= (BITM_SPI_DMA_TXEN);
1047 uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
1048 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
1051 pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
1054 pADI_DMA0->EN_SET = 1U << RxChanNum;
1057 pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
1060 pADI_DMA0->ALT_CLR = 1U << RxChanNum;
1062 if( (sz & 1U) != 0u )
1069 pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX;
1071 pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->
pReceiver + (sz - 2U));
1076 ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
1077 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1079 dmaFlags |= (BITM_SPI_DMA_RXEN );
1093 hDevice->pSpi->RD_CTL = 0u;
1094 if( hDevice->bRdCtlMode)
1099 uint32_t nBytes = hDevice->TxRemaining - 1U;
1102 hDevice->pSpi->RD_CTL &= (uint16_t)~((uint16_t)(BITM_SPI_RD_CTL_TXBYTES << BITP_SPI_RD_CTL_TXBYTES));
1104 hDevice->pSpi->RD_CTL |= (uint16_t)( (uint16_t)(nBytes << BITP_SPI_RD_CTL_TXBYTES) |
1105 (uint16_t)(1 << BITP_SPI_RD_CTL_CMDEN));
1108 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
1111 hDevice->pSpi->CNT = hDevice->RxRemaining;
1116 if(hDevice->RxRemaining == 0u)
1119 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH);
1121 else if(hDevice->TxRemaining == 0u)
1124 hDevice->pSpi->CTL |= (BITM_SPI_CTL_TFLUSH);
1133 nCount = hDevice->RxRemaining > hDevice->TxRemaining ? hDevice->RxRemaining : hDevice->TxRemaining;
1135 hDevice->pSpi->CNT = (uint16_t)nCount;
1139 if( hDevice->bDmaMode ==
false)
1143 if( hDevice->pTxBuffer != NULL)
1147 while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
1150 hDevice->pSpi->TX = *hDevice->pTxBuffer;
1152 hDevice->pTxBuffer += hDevice->TxIncrement;
1154 hDevice->TxRemaining--;
1161 hDevice->pSpi->DMA |= dmaFlags;
1164 #if defined(ADI_SPI_MASTER_TIM_FOR_DMA) && (ADI_SPI_MASTER_TIM_FOR_DMA != 0u) 1166 hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM;
1170 for( uint16_t numberOfLoops = 0u; numberOfLoops < 100u; numberOfLoops++)
1174 volatile uint16_t nFifoStatus = hDevice->pSpi->FIFO_STAT;
1176 uint16_t bytesInTxFifo = ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX);
1177 if( bytesInTxFifo != 0u)
1187 if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
1189 uint16_t
byte ADI_UNUSED_ATTRIBUTE = hDevice->pSpi->RX;
1193 NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
1215 uint32_t *
const pHWErrors
1219 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
1227 *pHWErrors = hDevice->HWErrors;
1251 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
1257 *bComplete = hDevice->bTransferComplete;
1293 volatile uint16_t ADI_UNUSED_ATTRIBUTE byte;
1294 uint32_t nCount = 0u;
1297 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
1331 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
1332 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
1335 hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1337 hDevice->bTransferComplete =
false;
1344 hDevice->bDmaMode = pXfr->
bDMA;
1345 hDevice->bRdCtlMode = pXfr->
bRD_CTL;
1350 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH | BITM_SPI_CTL_CON);
1351 if( hDevice->TxRemaining == 0u )
1354 hDevice->pSpi->CTL |= BITM_SPI_CTL_TFLUSH;
1356 if( hDevice->RxRemaining == 0u )
1359 hDevice->pSpi->CTL |= BITM_SPI_CTL_RFLUSH;
1362 if( hDevice->bDmaMode !=
true) {
1363 hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM;
1368 hDevice->pSpi->CNT = (uint16_t) hDevice->TxRemaining > hDevice->RxRemaining ? hDevice->TxRemaining : hDevice->RxRemaining;
1370 uint16_t nDMAFlags = 0u;
1372 if( hDevice->bDmaMode ==
true)
1377 uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
1380 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
1383 pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
1386 pADI_DMA0->EN_SET = 1U << TxChanNum;
1389 pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
1392 pADI_DMA0->ALT_CLR = 1U << TxChanNum;
1395 if( (sz & 1U) != 0u )
1402 pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->
pTransmitter + (sz - 2U));
1404 pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX;
1406 pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)
ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
1409 ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
1410 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1412 nDMAFlags |= (BITM_SPI_DMA_TXEN);
1419 uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
1420 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
1423 pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
1426 pADI_DMA0->EN_SET = 1U << RxChanNum;
1429 pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
1432 pADI_DMA0->ALT_CLR = 1U << RxChanNum;
1434 if( (sz & 1U) != 0u )
1441 pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX;
1443 pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->
pReceiver + (sz - 2U));
1448 ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
1449 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1451 nDMAFlags |= (BITM_SPI_DMA_RXEN );
1457 hDevice->pSpi->IEN &= (uint16_t)~BITM_SPI_IEN_XFRDONE;
1459 if( hDevice->bDmaMode ==
false) {
1461 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
1466 uint16_t activeInterrupts = 0u;
1468 if( hDevice->TxRemaining ) {
1469 activeInterrupts |= BITM_SPI_IEN_TXUNDR;
1472 if( hDevice->RxRemaining ) {
1473 activeInterrupts |= BITM_SPI_IEN_RXOVR;
1475 hDevice->pSpi->IEN |= activeInterrupts;
1478 while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
1481 hDevice->pSpi->TX = *hDevice->pTxBuffer;
1483 hDevice->pTxBuffer += hDevice->TxIncrement;
1485 hDevice->TxRemaining--;
1491 hDevice->pSpi->DMA |= (uint16_t)(BITM_SPI_DMA_EN | nDMAFlags);
1494 if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
1496 byte = hDevice->pSpi->RX;
1498 NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
1500 if (hDevice->bBlockingMode ==
true)
1539 hDevice->bBlockingMode =
true;
1541 hDevice->bBlockingMode =
false;
1564 static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD)
1566 uint16_t nFifoStatus;
1567 uint16_t writableBytes;
1568 uint16_t readableBytes;
1569 bool terminate =
false;
1572 uint16_t nErrorStatus = pDD->pSpi->STAT;
1574 uint16_t nErrorStatusMsk = 0u;
1578 pDD->pSpi->STAT = nErrorStatus;
1579 nFifoStatus = pDD->pSpi->FIFO_STAT;
1582 #if !defined(ADI_SPI_TRAP_RXOVR) || (ADI_SPI_TRAP_RXOVR!=0) 1583 nErrorStatusMsk |= BITM_SPI_STAT_RXOVR;
1586 #if !defined(ADI_SPI_TRAP_TXUNDR) || (ADI_SPI_TRAP_TXUNDR!=0) 1587 nErrorStatusMsk |= BITM_SPI_STAT_TXUNDR;
1590 if(0u != (nErrorStatusMsk & nErrorStatus)) {
1592 if(BITM_SPI_STAT_TXUNDR == (BITM_SPI_STAT_TXUNDR & nErrorStatus)) {
1595 if( BITM_SPI_STAT_RXOVR == (BITM_SPI_STAT_RXOVR & nErrorStatus)) {
1604 writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX);
1606 readableBytes = ((BITM_SPI_FIFO_STAT_RX & nFifoStatus) >> BITP_SPI_FIFO_STAT_RX);
1609 while ((writableBytes != 0u) && (pDD->TxRemaining != 0u))
1611 pDD->pSpi->TX = *pDD->pTxBuffer;
1612 pDD->pTxBuffer += pDD->TxIncrement;
1621 if( (pDD->bRdCtlMode==
false) || (pDD->TxRemaining==0u) )
1624 while ((readableBytes != 0u) &&(pDD->RxRemaining != 0u))
1626 *pDD->pRxBuffer = (uint8_t) pDD->pSpi->RX;
1627 pDD->pRxBuffer += pDD->RxIncrement;
1639 if( (pDD->RxRemaining == 0u) && (pDD->TxRemaining == 0u))
1641 if( BITM_SPI_CTL_MASEN == (pDD->pSpi->CTL & BITM_SPI_CTL_MASEN ))
1648 if((BITM_SPI_STAT_XFRDONE == (nErrorStatus & BITM_SPI_STAT_XFRDONE)) ||
1649 (BITM_SPI_STAT_XFRDONE == (pDD->pSpi->STAT & BITM_SPI_STAT_XFRDONE)) )
1655 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN);
1662 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN);
1676 pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);
1677 pDD->bTransferComplete =
true;
1678 NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
1681 nErrorStatus = pDD->pSpi->STAT;
1682 pDD->pSpi->STAT = nErrorStatus;
1685 if(NULL != pDD->pfCallback ){
1686 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1694 #if defined(ADI_CYCLECOUNT_SPI_ISR_ENABLED) && (ADI_CYCLECOUNT_SPI_ISR_ENABLED == 1u) 1702 static void RxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
1721 if(NULL != hDevice->pfCallback ){
1722 hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL);
1732 static void TxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
1751 if(NULL != hDevice->pfCallback ){
1752 hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL);
1768 void SPI0_Int_Handler(
void) {
1770 common_SPI_Int_Handler(spi_device_info[0].hDevice );
1782 void SPI1_Int_Handler(
void) {
1784 common_SPI_Int_Handler(spi_device_info[1].hDevice);
1795 void SPI2_Int_Handler(
void) {
1797 common_SPI_Int_Handler(spi_device_info[2].hDevice );
1813 static void common_spi_DMA_Tx(
ADI_SPI_HANDLE pDD,
const int masterMode)
1815 pDD->TxRemaining = 0u;
1816 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_TXEN);
1817 if (0u == pDD->RxRemaining)
1827 pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
1829 pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);
1832 if(NULL != pDD->pfCallback ){
1833 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1843 static void common_spi_DMA_Rx(
ADI_SPI_HANDLE pDD,
const int masterMode)
1845 pDD->RxRemaining = 0u;
1846 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_RXEN);
1849 pDD->pSpi->CTL |= (uint16_t)(BITM_SPI_CTL_RFLUSH);
1851 if (0u == pDD->TxRemaining)
1861 pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
1863 pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);
1864 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN);
1867 pDD->bTransferComplete =
true;
1868 NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
1869 if(NULL != pDD->pfCallback ){
1870 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1881 void DMA_SPI0_TX_Int_Handler(
void)
1888 void DMA_SPI0_RX_Int_Handler(
void)
1895 void DMA_SPI1_TX_Int_Handler(
void)
1903 void DMA_SPI1_RX_Int_Handler(
void)
1910 void DMA_SPIH_TX_Int_Handler(
void)
1917 void DMA_SPIH_RX_Int_Handler(
void)
ADI_SPI_RESULT adi_spi_SetTransmitUnderflow(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the SPI transmit FIFO underflow mode.
ADI_DMA_RESULT adi_dma_RegisterCallback(DMA_CHANn_TypeDef const eChannelID, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register a call-back function for a DMA channel.
ADI_SPI_RESULT adi_spi_GetBuffer(ADI_SPI_HANDLE const hDevice, uint32_t *const pHWErrors)
Block until the SPI transaction is complete.
#define ADI_CYCLECOUNT_STORE(id)
ADI_SPI_RESULT adi_spi_SlaveReadWrite(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Slave-Mode transaction in "Blocking mode".This function returns only af...
uint16_t TransmitterBytes
ADI_SPI_RESULT adi_spi_SetClockPhase(ADI_SPI_HANDLE const hDevice, const bool bFlag)
Set the clock phase.
#define ADI_CYCLECOUNT_ISR_SPI
ADI_SPI_RESULT adi_spi_SetContinuousMode(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the continuous transfer mode.
ADI_SPI_RESULT adi_spi_Open(uint32_t nDeviceNum, void *pDevMemory, uint32_t nMemorySize, ADI_SPI_HANDLE *const phDevice)
Initialize and allocate an SPI device for use in Master Mode.
ADI_SPI_RESULT adi_spi_Close(ADI_SPI_HANDLE const hDevice)
Uninitialize and deallocate an SPI device.
ADI_SPI_RESULT adi_spi_isBufferAvailable(ADI_SPI_CONST_HANDLE const hDevice, bool *const bComplete)
Get the SPI transaction completion status.
ADI_SPI_RESULT adi_spi_SetChipSelect(ADI_SPI_HANDLE const hDevice, const ADI_SPI_CHIP_SELECT eChipSelect)
Set the chip select.
ADI_SPI_RESULT adi_spi_SetLoopback(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the internal loopback mode.
ADI_SPI_RESULT adi_spi_GetBitrate(ADI_SPI_CONST_HANDLE const hDevice, uint32_t *const pnBitrate)
Get the SPI serial clock frequency.
ADI_SPI_RESULT adi_spi_RegisterCallback(ADI_SPI_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register or unregister the callback.
#define ADI_SPI2_MASTER_MODE
ADI_SPI_RESULT adi_spi_SetClockPolarity(ADI_SPI_HANDLE const hDevice, const bool bFlag)
Set the clock polarity.
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
ADI_SPI_RESULT adi_spi_SetIrqmode(ADI_SPI_CONST_HANDLE const hDevice, const uint8_t nMode)
Set the IRQ mode.
ADI_SPI_RESULT adi_spi_SetReceiveOverflow(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the SPI receive FIFO overflow mode.
ADI_SPI_RESULT adi_spi_MasterReadWrite(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Master-Mode transaction in "Blocking mode".This function returns only a...
struct __ADI_SPI_DEV_DATA_TYPE * ADI_SPI_HANDLE
ADI_SPI_RESULT adi_spi_SetMasterMode(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set SPI Master-Mode operation.
#define ADI_SPI0_MASTER_MODE
void adi_dma_Init(void)
Initialize the DMA peripheral.
const struct __ADI_SPI_DEV_DATA_TYPE * ADI_SPI_CONST_HANDLE
ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Slave-Mode transaction.
ADI_SPI_RESULT adi_spi_SetBitrate(ADI_SPI_CONST_HANDLE const hDevice, const uint32_t Hertz)
Set the SPI serial clock frequency.
ADI_SPI_RESULT adi_spi_MasterSubmitBuffer(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Master-Mode transaction.
#define ADI_SPI1_MASTER_MODE