47 #include "system_ADuCM4050.h" 48 #include <adi_callback.h> 49 #include <adi_processor.h> 50 #include <rtos_map/adi_rtos_map.h> 63 #pragma diag_suppress=Pm073,Pm143,Pm140 79 uint32_t lfClock = 0u;
83 uint32_t hfClock = 0u;
86 uint32_t gpioClock = 0u;
87 extern void* __Vectors[];
93 #if defined (__CC_ARM) 94 __attribute__ ((at(0x00000180u)))
95 __attribute__ ((weak))
96 #elif defined (__GNUC__) 97 __attribute__ ((used,section(
".security_options")))
98 __attribute__ ((weak))
99 #elif defined (__ICCARM__) 100 #pragma location=".security_options" 104 const ADI_ADUCM4X50_SECURITY_OPTIONS adi_aducm4x50_security_options
106 { 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu },
108 #if defined (__ICCARM__) 141 uint32_t val, nDivisor, nMulfactor, div2, mul2;
154 switch (pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) {
156 case HFMUX_INTERNAL_OSC_VAL:
160 case HFMUX_EXTERNAL_XTAL_VAL:
164 case HFMUX_SYSTEM_SPLL_VAL:
166 if ((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_PLL_IPSEL) != 0u) {
175 nMulfactor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLNSEL) >> BITP_CLKG_CLK_CTL3_SPLLNSEL;
177 nDivisor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL) >> BITP_CLKG_CLK_CTL3_SPLLMSEL;
180 mul2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2) >> BITP_CLKG_CLK_CTL3_SPLLMUL2;
182 div2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2) >> BITP_CLKG_CLK_CTL3_SPLLDIV2;
184 val = ((val << mul2) * nMulfactor / nDivisor) >> div2;
200 #ifdef __ARMCC_VERSION 202 #pragma import(__use_no_semihosting_swi) 218 #define ADI_NUM_EXCEPTIONS 16 219 #define LENGTHOF_IVT (NVIC_INTS + ADI_NUM_EXCEPTIONS) 220 #define RELOCATION_ADDRESS (0x20000000) 223 #if defined (__ICCARM__) 225 SECTION_PLACE(KEEP_VAR(__no_init uint32_t __relocated_vector_table[LENGTHOF_IVT]), RELOCATION_ADDRESS);
227 #warning "Relocated Interupt Vector Tables are not supported in this toolchain" 242 #if defined(ADI_FLCC_ENABLE_BUS_ERR) && (ADI_FLCC_ENABLE_BUS_ERR != 0) 244 *pREG_FLCC0_IEN |= ENUM_FLCC_IEN_BUS_ERR_ERR;
263 #if defined(ADI_SRAM_PARITY_ENABLE) && (ADI_SRAM_PARITY_ENABLE != 0) 265 pADI_PMG0_TST->SRAM_CTL |= (BITM_PMG_TST_SRAM_CTL_PENBNK0 |
266 BITM_PMG_TST_SRAM_CTL_PENBNK1 |
267 BITM_PMG_TST_SRAM_CTL_PENBNK2 |
268 BITM_PMG_TST_SRAM_CTL_PENBNK3 |
269 BITM_PMG_TST_SRAM_CTL_PENBNK4 |
270 BITM_PMG_TST_SRAM_CTL_PENBNK5 |
271 BITM_PMG_TST_SRAM_CTL_PENBNK6 |
272 BITM_PMG_TST_SRAM_CTL_PENBNK7);
283 IntStatus = __get_PRIMASK();
288 for (i = 0u; i < LENGTHOF_IVT; i++)
290 __relocated_vector_table[i] = (uint32_t )__Vectors[i];
292 SCB->VTOR = (uint32_t) &__relocated_vector_table;
295 SCB->VTOR = (uint32_t) &__Vectors;
302 SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk |
303 SCB_SHCSR_BUSFAULTENA_Msk |
304 SCB_SHCSR_MEMFAULTENA_Msk ;
308 SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
311 #if (__FPU_PRESENT == 1u) && (__FPU_USED == 1u) 318 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));
325 __set_PRIMASK(IntStatus);
327 #ifdef ADI_MAX_IRQ_PRIORITY 342 pADI_FLCC0_CACHE->KEY = CACHE_CONTROLLER_KEY;
343 if( bEnable ==
true )
345 pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN;
349 pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN;
375 uint32_t retainBits = 0u;
401 retainBits |= BITM_PMG_SRAMRET_RET1;
404 retainBits |= BITM_PMG_SRAMRET_RET2;
407 retainBits |= BITM_PMG_SRAMRET_RET3;
410 retainBits |= BITM_PMG_SRAMRET_RET4;
418 pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY;
420 pADI_PMG0->SRAMRET |= retainBits;
423 pADI_PMG0->SRAMRET &= ~(retainBits);
445 #ifdef ADI_MAX_IRQ_PRIORITY 446 uint32_t prio = (uint32_t)ADI_MAX_IRQ_PRIORITY;
448 uint32_t prio = (uint32_t)0u;
453 for(uint8_t irq = 0u; irq < NVIC_INTS; irq++) {
454 NVIC_SetPriority((IRQn_Type)irq, prio);
void SystemInit(void)
Sets up the microcontroller system. Initializes the System and updates the relocate vector table.
void SystemCoreClockUpdate(void)
Update the clock.
void adi_system_EnableCache(bool bEnable)
Enables or disables the cache.
void adi_system_SetGlobalIrqPriority(void)
This function sets the priority for all IRQ interrupts to the value defined by ADI_MAX_IRQ_PRIORITY (...
ADI_SYS_RESULT adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable)
This enables/disable SRAM retention during the hibernation.