ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_rtc.c
1 
23 #if defined(__ADUCM302x__)
24 #define BITP_CLKG_OSC_CTL_LFX_FAIL_STA BITP_CLKG_OSC_CTL_LFX_FAIL_STAT
25 #endif /* __ADUCM302x__ */
26 
27 #if defined ( __ADSPGCC__ )
28 #define UNUSED __attribute__ ((unused))
29 #else
30 #define UNUSED
31 #endif
32 
33 #include <stdlib.h> /* for 'NULL" definition */
34 #include <assert.h>
35 #include <string.h>
36 #include <rtos_map/adi_rtos_map.h>
37 
38 
39 
40 #ifdef __ICCARM__
41 /*
42 * IAR MISRA C 2004 error suppressions.
43 *
44 * Pm011 (rule 6.3): Types which specify sign and size should be used
45 * We use bool which is accepted by MISRA but the toolchain does not accept it
46 *
47 * Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
48 * This isn't a header as such.
49 *
50 * Pm073 (rule 14.7): a function should have a single point of exit
51 * Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
52 * Multiple returns are used for error handling.
53 *
54 * Pm050 (rule 14.2): a null statement shall only occur on a line by itself
55 * Needed for null expansion of ADI_INSTALL_HANDLER and others.
56 *
57 * Pm109 (rule 20.12): the time handling functions of library <time.h> shall not be used
58 * Pm150 (rule 20.2): the names of standard library macros, objects and function shall not be reused
59 * Needed to implement the <time.h> functions here.
60 *
61 * Pm129 (rule 12.7): bitwise operations shall not be performed on signed integer types
62 * The rule makes an exception for valid expressions.
63 *
64 * Pm029: this bitwise operation is in a boolean context - logical operators should not be confused with bitwise operators
65 * The rule is suppressed as the bitwise and logical operators are being used correctly and are not being confused
66 *
67 * Pm126: if the bitwise operators ~ and << are applied to an operand of underlying type 'unsigned char' or 'unsigned short', the result shall be immediately cast to the underlying type of the operand
68 * The behaviour as described is correct
69 *
70 * Pm031: bitwise operations shall not be performed on signed integer types
71 * Device drivers often require bit banging on MMRs that are defined as signed
72 
73 */
74 #pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm050,Pm109,Pm150,Pm140,Pm129,Pm029,Pm126,Pm031
75 #endif /* __ICCARM__ */
76 
79 #include <drivers/rtc/adi_rtc.h>
80 
81 
87 #if defined(_RTE_)
88 
93 #include <RTE_Components.h>
94 
95 #endif
96 
97 #include "adi_rtc_data.c"
98 
99 #define RTC_SNAPSHOT_KEY (0x7627u)
100 #define RTC_FRZCNT_KEY (0x9376u)
101 
102 /* Data structure to manage snapshots */
103 struct adi_rtc_snapshots
104 {
105  uint16_t snapshot0; /* snap shot for register COUNT0 */
106  uint16_t snapshot1; /* snap shot for register COUNT1 */
107  uint16_t snapshot2; /* snap shot for register COUNT2 */
108 };
109 
110 #if defined(__ADUCM302x__)
111 #define BITP_RTC_SSMSK_SS1MSK BITP_RTC_SSMSK_SSMSK
112 #endif /* __ADUCM302x__ */
113 
114 #if defined(__ADUCM4x50__)
115 
119 #ifndef ADUCM4050_SI_REV
120 #define ADUCM4050_SI_REV (1)
121 #endif
122 
126 #ifndef WA_21000023
127 #define WA_21000023 (1)
128 #endif
129 
130 /* Data structures used to manage the enabling of all RTC interrupts */
131 static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u, cr5ocs = 0u;
132 
133 struct xxx
134 {
135  uint16_t *cr;
136  uint16_t bitPositionl;
137 }
138 
139 Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] =
140 {
141  { &cr0, BITP_RTC_CR0_ALMINTEN },
142  { &cr0, BITP_RTC_CR0_MOD60ALMINTEN },
143  { &cr0, BITP_RTC_CR0_ISOINTEN },
144  { &cr0, BITP_RTC_CR0_WPNDERRINTEN },
145  { &cr0, BITP_RTC_CR0_WSYNCINTEN },
146  { &cr0, BITP_RTC_CR0_WPNDINTEN },
147  { &cr1, BITP_RTC_CR1_CNTINTEN },
148  { &cr1, BITP_RTC_CR1_PSINTEN },
149  { &cr1, BITP_RTC_CR1_TRMINTEN },
150  { &cr1, BITP_RTC_CR1_CNTROLLINTEN },
151  { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN },
152  { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN },
153  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
154  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
155  { &cr3oc, BITP_RTC_CR3SS_SS4IRQEN },
156  { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN },
157  { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN },
158  { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN },
159  { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN },
160  { &cr2ic, BITP_CLKG_OSC_CTL_LFX_FAIL_STA },
161  { &cr3oc, BITM_RTC_CR3SS_SS4FEIRQEN},
162  { &cr3oc, BITM_RTC_CR3SS_SS3FEIRQEN},
163  { &cr3oc, BITM_RTC_CR3SS_SS2FEIRQEN},
164  { &cr3oc, BITM_RTC_CR3SS_SS1FEIRQEN},
165  { &cr4oc, BITP_RTC_CR4SS_SS4MSKEN},
166  { &cr4oc, BITP_RTC_CR4SS_SS3MSKEN},
167  { &cr4oc, BITP_RTC_CR4SS_SS2MSKEN},
168  { &cr4oc, BITP_RTC_CR4SS_SS1MSKEN},
169  { &cr5ocs, BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN},
170  { &cr5ocs, BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN},
171  { &cr5ocs, BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN}
172 
173 };
174 
175 #elif defined(__ADUCM302x__)
176 
177 /* Data structures used to manage the enabling of all RTC interrupts */
178 static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u;
179 
180 struct xxx
181 {
182  uint16_t *cr;
183  uint16_t bitPositionl;
184 }
185 
186 Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] =
187 {
188  { &cr0, BITP_RTC_CR0_ALMINTEN },
189  { &cr0, BITP_RTC_CR0_MOD60ALMINTEN },
190  { &cr0, BITP_RTC_CR0_ISOINTEN },
191  { &cr0, BITP_RTC_CR0_WPNDERRINTEN },
192  { &cr0, BITP_RTC_CR0_WSYNCINTEN },
193  { &cr0, BITP_RTC_CR0_WPNDINTEN },
194  { &cr1, BITP_RTC_CR1_CNTINTEN },
195  { &cr1, BITP_RTC_CR1_PSINTEN },
196  { &cr1, BITP_RTC_CR1_TRMINTEN },
197  { &cr1, BITP_RTC_CR1_CNTROLLINTEN },
198  { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN },
199  { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN },
200  { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN },
201  { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN },
202  { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN },
203  { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN },
204 };
205 #else
206 #error RTC is not ported for this processor
207 #endif
208 
209 
210 /* Forward prototypes */
211 void RTC0_Int_Handler(void);
212 void RTC1_Int_Handler(void);
213 static ADI_RTC_RESULT adi_rtc_GetCoherentCounterValues(ADI_RTC_HANDLE const hDevice, struct adi_rtc_snapshots *pSnapshots);
214 
215 
216 
217 #ifdef ADI_DEBUG
218 static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice)
219 {
220  /* Return code */
222  uint32_t i;
223  for(i = 0u; i < ADI_RTC_NUM_INSTANCE; i++)
224  {
225  if(aRTCDeviceInfo[i].hDevice == pInDevice)
226  {
227  return(ADI_RTC_SUCCESS);
228  }
229  }
230  return (nResult);
231 }
232 #endif
233 
267  uint32_t DeviceNumber,
268  void *pDeviceMemory,
269  uint32_t MemorySize,
270  ADI_RTC_HANDLE *phDevice
271  )
272 {
273  ADI_RTC_DEVICE *pDevice = pDeviceMemory;
274 
275  /* store a bad handle in case of failure */
276  *phDevice = (ADI_RTC_HANDLE) NULL;
277 
278 #ifdef ADI_DEBUG
279  if ( DeviceNumber >= ADI_RTC_NUM_INSTANCE)
280  {
281  return (ADI_RTC_INVALID_INSTANCE);
282  }
283  assert(ADI_RTC_MEMORY_SIZE == sizeof(ADI_RTC_DEVICE));
284  if (aRTCDeviceInfo[DeviceNumber].hDevice != NULL)
285  {
286  return (ADI_RTC_IN_USE);
287  }
288  if(MemorySize < ADI_RTC_MEMORY_SIZE)
289  {
290  return(ADI_RTC_FAILURE);
291  }
292 #endif
293 
294  /* clear the memory used to store RTC instance data */
295  memset(pDeviceMemory,0,MemorySize);
296  /* initialize device data entries */
297  pDevice->pRTCRegs = aRTCDeviceInfo[DeviceNumber].pRTCRegs;
298 
299  /* Disable all mainstream RTC operations:
300  * - wait for CR0 to be writable
301  * - clear CR0 to disable all the operations
302  * - wait for CR1 to be writable
303  * - clear CR1 to disable all the operations
304  * - Wait till writes to Control Registers CR0 and CR1 take effect
305  */
306  ALWAYS_PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
307  pDevice->pRTCRegs->CR0 = 0u;
308  ALWAYS_PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
309  pDevice->pRTCRegs->CR1 = 0u;
310  ALWAYS_SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
311  ALWAYS_SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)
312 
313  /* Clear every interrupt bit in SR0:
314  * - Wait for SR0 to be writable
315  * - Write every interrupt bit in SR0 (Write-One-To-Clear)
316  * - Wait till write to SR0 takes effect
317  */
318  ALWAYS_PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0)
319  pDevice->pRTCRegs->SR0 = ADI_RTC_IRQ_SOURCE_MASK_SR0;
320  ALWAYS_SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0)
321 
322  /* Clear every interrupt bit in SR2:
323  * - Write every interrupt bit in SR2 (Write-One-To-Clear)
324  */
325  if(pDevice->pRTCRegs == pADI_RTC1)
326  {
327  pDevice->pRTCRegs->SR2 = ADI_RTC1_IRQ_SOURCE_MASK_SR2;
328  }
329  else
330  {
331  pDevice->pRTCRegs->SR2 = ADI_RTC0_IRQ_SOURCE_MASK_SR2;
332  }
333 
334  /* Clear every interrupt bit in SR3:
335  * - Wait for SR3 to be writable
336  * - Write every interrupt bit in SR3 (Write-One-To-Clear)
337  * - Wait till write to SR3 takes effect
338  */
339  ALWAYS_PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSR3)
340  pDevice->pRTCRegs->SR3 = ADI_RTC_IRQ_SOURCE_MASK_SR3;
341  ALWAYS_SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSR3)
342 
343  /* Clear every interrupt bit in CNT0 and CNT1:
344  * - Wait for CNT0 to be writable
345  * - Clear every interrupt bit in CNT0
346  * - Wait for CNT1 to be writable
347  * - Clear every interrupt bit in CNT1
348  * - Wait till writes to CNT0 and CNT1 take effect
349  */
350  ALWAYS_PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
351  pDevice->pRTCRegs->CNT0 = 0u;
352  pDevice->pRTCRegs->CNT1 = 0u;
353  ALWAYS_SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1))
354 
355  /* local pointer to instance data */
356  aRTCDeviceInfo[DeviceNumber].hDevice = pDevice;
357  pDevice->pDeviceInfo = &aRTCDeviceInfo[DeviceNumber];
358 
359  /* Use static configuration to initialize the RTC */
360  rtc_init(pDevice,&aRTCConfig[DeviceNumber]);
361 
362  /* store handle at application handle pointer */
363  *phDevice = pDevice;
364  pDevice->eIRQn = aRTCDeviceInfo[DeviceNumber].eIRQn;
365  /* Enable RTC interrupts in NVIC */
366  NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
367 
368  return ADI_RTC_SUCCESS; /* initialized */
369 }
370 
371 
386 {
387  ADI_RTC_DEVICE *pDevice = hDevice;
388 
389 #ifdef ADI_DEBUG
390  ADI_RTC_RESULT eResult;
391  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
392  {
393  return eResult;
394  }
395 #endif
396 
397  /* uninitialize */
398  NVIC_DisableIRQ( pDevice->eIRQn);
399 
400  pDevice->pRTCRegs = NULL;
401  pDevice->pfCallback = NULL;
402  pDevice->pCBParam = NULL;
403  pDevice->cbWatch = 0u;
404 
405  pDevice->pDeviceInfo->hDevice = NULL;
406  return ADI_RTC_SUCCESS;
407 }
408 
409 
410 /*************************************************************************************************
411 **************************************************************************************************
412 **************************************** ENABLE APIS *******************************************
413 **************************************************************************************************
414 *************************************************************************************************/
415 
416 
448 {
449  ADI_RTC_DEVICE *pDevice = hDevice;
450 #ifdef ADI_DEBUG
451  ADI_RTC_RESULT eResult;
452  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
453  {
454  return eResult;
455  }
456 #endif
457 
458  /* Wait till previously posted write to Control Register to complete */
459  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
460 
461  ADI_INT_STATUS_ALLOC();
462  ADI_ENTER_CRITICAL_REGION();
463  /* set/clear RTC alarm enable */
464  if (bEnable)
465  {
466  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_ALMEN;
467  }
468  else
469  {
470  pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_ALMEN);
471  }
472  ADI_EXIT_CRITICAL_REGION();
473 
474  /* Wait till write to Control Register to take effect */
475  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
476 
477  return ADI_RTC_SUCCESS;
478 }
479 
511 {
512  ADI_RTC_DEVICE *pDevice = hDevice;
513 #ifdef ADI_DEBUG
514  ADI_RTC_RESULT eResult;
515  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
516  {
517  return eResult;
518  }
519  /* Mod-60 Alarm is present only in RTC-1 */
520  if(pDevice->pRTCRegs == pADI_RTC0)
521  {
523  }
524 
525 #endif
526 
527  /* Wait till previously posted write to Control Register to complete */
528  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
529 
530  ADI_INT_STATUS_ALLOC();
531  ADI_ENTER_CRITICAL_REGION();
532  /* set/clear RTC alarm enable */
533  if (bEnable)
534  {
535  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_MOD60ALMEN;
536  }
537  else
538  {
539  pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_MOD60ALMEN);
540  }
541  ADI_EXIT_CRITICAL_REGION();
542 
543  /* Wait till write to Control Register to take effect */
544  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
545 
546  return ADI_RTC_SUCCESS;
547 }
548 
572 ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable)
573 {
574  ADI_RTC_DEVICE *pDevice = hDevice;
575 
576 #ifdef ADI_DEBUG
577  ADI_RTC_RESULT eResult;
578  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
579  {
580  return eResult;
581  }
582 #endif
583 
584  /* Wait till previously posted write to Control Register to complete */
585  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
586 
587 
588  ADI_INT_STATUS_ALLOC();
589  ADI_ENTER_CRITICAL_REGION();
590  /* set/clear RTC device enable */
591  if (bEnable)
592  {
593  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_CNTEN;
594  }
595  else
596  {
597  pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_CNTEN);
598  }
599  ADI_EXIT_CRITICAL_REGION();
600 
601  /* Wait till write to Control Register to take effect */
602  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
603 
604  return ADI_RTC_SUCCESS;
605 }
606 
607 
633 {
634  ADI_RTC_DEVICE *pDevice = hDevice;
635 
636 #ifdef ADI_DEBUG
637  ADI_RTC_RESULT eResult;
638  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
639  {
640  return eResult;
641  }
642  if( (pDevice->pRTCRegs == pADI_RTC0) &&(((uint16_t)((ADI_RTC_MOD60ALM_INT | ADI_RTC_ISO_DONE_INT|
646  )) & (uint16_t)Interrupts) != 0u))
647  {
648  return(ADI_RTC_INVALID_PARAM);
649  }
650 
651  assert(sizeof(Interrupt_Details)/sizeof(Interrupt_Details[0]) == ADI_RTC_NUM_INTERRUPTS);
652 #endif
653 
654  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
655  PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
656 
657  uint8_t ndx = 0u;
658  cr0 = 0u; cr1 = 0u; cr3oc = 0u; cr4oc = 0u; cr2ic = 0u;
659 
660 #if defined(__ADUCM4x50__)
661  cr5ocs = 0u;
662 #endif /* __ADUCM4x50__ */
663 
664  while( Interrupts )
665  {
666  if( 0u != (Interrupts & 1u) )
667  {
668  uint16_t *cr = Interrupt_Details[ndx].cr;
669  uint16_t enableBitPosition = Interrupt_Details[ndx].bitPositionl;
670  *cr = *cr | (1u << enableBitPosition);
671  }
672  Interrupts >>= 1;
673  ndx++;
674  }
675  /* set/clear interrupt enable bit(s) in control register */
676  if (bEnable)
677  {
678  pDevice->pRTCRegs->CR0 |= cr0;
679  pDevice->pRTCRegs->CR1 |= cr1;
680  pDevice->pRTCRegs->CR3SS |= cr3oc;
681  pDevice->pRTCRegs->CR4SS |= cr4oc;
682  pDevice->pRTCRegs->CR2IC |= cr2ic;
683 
684 #if defined(__ADUCM4x50__)
685  pDevice->pRTCRegs->CR5SSS |= cr5ocs;
686 #endif /* __ADUCM4x50__ */
687  }
688  else
689  {
690  pDevice->pRTCRegs->CR0 &= ~cr0;
691  pDevice->pRTCRegs->CR1 &= ~cr1;
692  pDevice->pRTCRegs->CR3SS &= ~cr3oc;
693  pDevice->pRTCRegs->CR4SS &= ~cr4oc;
694  pDevice->pRTCRegs->CR2IC &= ~cr2ic;
695 #if defined(__ADUCM4x50__)
696  pDevice->pRTCRegs->CR5SSS &= ~cr5ocs;
697 #endif /* __ADUCM4x50__ */
698  }
699  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
700  SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)
701  return ADI_RTC_SUCCESS;
702 }
703 
704 
731 ADI_RTC_RESULT adi_rtc_EnableTrim (ADI_RTC_HANDLE const hDevice, bool bEnable)
732 {
733  ADI_RTC_DEVICE *pDevice = hDevice;
734 
735 #ifdef ADI_DEBUG
736  ADI_RTC_RESULT eResult;
737  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
738  {
739  return eResult;
740  }
741 #endif
742  /* Wait till previously posted write to Control Register to complete */
743  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
744 
745  ADI_INT_STATUS_ALLOC();
746  ADI_ENTER_CRITICAL_REGION();
747  /* set/clear trim enable bit(s) in control register */
748  if (bEnable)
749  {
750  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_TRMEN;
751  }
752  else
753  {
754  pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_TRMEN);
755  }
756  ADI_EXIT_CRITICAL_REGION();
757 
758  /* Wait till write to Control Register to take effect */
759  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
760 
761  return ADI_RTC_SUCCESS;
762 }
778 {
779  ADI_RTC_DEVICE *pDevice = hDevice;
780 
781 #ifdef ADI_DEBUG
782  ADI_RTC_RESULT eResult;
783  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
784  {
785  return eResult;
786  }
787 #endif
788  /* Wait till previously posted write to Control Register to complete */
789  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
790 
791  ADI_INT_STATUS_ALLOC();
792  ADI_ENTER_CRITICAL_REGION();
793  /* set/clear trim input capture enable for specified channel*/
794  if (bEnable)
795  {
796  pDevice->pRTCRegs->CR2IC |=(uint16_t)eInpChannel;
797  }
798  else
799  {
800  pDevice->pRTCRegs->CR2IC &= (uint16_t)(~(uint16_t)eInpChannel);
801  }
802  ADI_EXIT_CRITICAL_REGION();
803 
804  /* Wait till write to Control Register to take effect */
805  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)
806 
807  return ADI_RTC_SUCCESS;
808 }
809 
824 {
825  ADI_RTC_DEVICE *pDevice = hDevice;
826 
827 #ifdef ADI_DEBUG
828  ADI_RTC_RESULT eResult;
829  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
830  {
831  return eResult;
832  }
833 #endif
834  /* Wait till previously posted write to Control Register to complete */
835  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
836 
837  ADI_INT_STATUS_ALLOC();
838  ADI_ENTER_CRITICAL_REGION();
839  /* set/clear trim input capture enable for specified channel*/
840  if (bEnable)
841  {
842  pDevice->pRTCRegs->CR2IC |= BITM_RTC_CR2IC_ICOWUSEN;
843  }
844  else
845  {
846  pDevice->pRTCRegs->CR2IC &= (uint16_t)~BITM_RTC_CR2IC_ICOWUSEN;
847  }
848  ADI_EXIT_CRITICAL_REGION();
849 
850  /* Wait till write to Control Register to take effect */
851  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)
852 
853  return ADI_RTC_SUCCESS;
854 }
855 
871 {
872  ADI_RTC_DEVICE *pDevice = hDevice;
873  uint32_t nInpChannel = (uint16_t)eInpChannel;
874 
875 #ifdef ADI_DEBUG
876  ADI_RTC_RESULT eResult;
877  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
878  {
879  return eResult;
880  }
881 #endif
882  /* Wait till previously posted write to Control Register to complete */
883  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
884 
885  ADI_INT_STATUS_ALLOC();
886  ADI_ENTER_CRITICAL_REGION();
887  /* set/clear trim input capture enable for specified channel*/
888  if (bEnable)
889  {
890  pDevice->pRTCRegs->CR2IC |= (uint16_t)(nInpChannel << BITP_RTC_CR2IC_IC0LH);
891  }
892  else
893  {
894  pDevice->pRTCRegs->CR2IC &= (uint16_t)~(nInpChannel << BITP_RTC_CR2IC_IC0LH);
895  }
896  ADI_EXIT_CRITICAL_REGION();
897 
898  /* Wait till write to Control Register to take effect */
899  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)
900 
901  return ADI_RTC_SUCCESS;
902 }
918 {
919  ADI_RTC_DEVICE *pDevice = hDevice;
920 
921 #ifdef ADI_DEBUG
922  ADI_RTC_RESULT eResult;
923  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
924  {
925  return eResult;
926  }
927 #endif
928  /* Wait till previously posted write to Control Register to complete */
929  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR3SS)
930 
931  ADI_INT_STATUS_ALLOC();
932  ADI_ENTER_CRITICAL_REGION();
933  /* set/clear Sensor Strobe enable for specified channel*/
934  if (bEnable)
935  {
936  pDevice->pRTCRegs->CR3SS |=(uint16_t)eSSChannel;
937  }
938  else
939  {
940  pDevice->pRTCRegs->CR3SS &= (uint16_t)(~(uint16_t)eSSChannel);
941  }
942  ADI_EXIT_CRITICAL_REGION();
943 
944  /* Wait till write to Control Register to take effect */
945  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR3SS)
946 
947  return ADI_RTC_SUCCESS;
948 }
949 
965 {
966  ADI_RTC_DEVICE *pDevice = hDevice;
967 
968 #ifdef ADI_DEBUG
969  ADI_RTC_RESULT eResult;
970  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
971  {
972  return eResult;
973  }
974 #endif
975  /* Wait till previously posted write to Control Register to complete */
976  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR4SS)
977 
978  ADI_INT_STATUS_ALLOC();
979  ADI_ENTER_CRITICAL_REGION();
980  /* set/clear auto reload enable options */
981  /* Note that channel 4 does not have this feature */
982  if (bEnable)
983  {
984  switch( eSSChannel)
985  {
987  pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS1ARLEN;
988  break;
989 #if defined(__ADUCM4x50__)
991  pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS2ARLEN;
992  break;
994  pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS3ARLEN;
995  break;
996 #endif /* __ADUCM4x50__ */
997  default:
998  return ADI_RTC_FAILURE;
999  }
1000 
1001  }
1002  else
1003  {
1004  switch( eSSChannel)
1005  {
1006  case ADI_RTC_SS_CHANNEL_1:
1007  pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS1ARLEN;
1008  break;
1009 #if defined(__ADUCM4x50__)
1010  case ADI_RTC_SS_CHANNEL_2:
1011  pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS2ARLEN;
1012  break;
1013  case ADI_RTC_SS_CHANNEL_3:
1014  pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS3ARLEN;
1015  break;
1016 #endif /* __ADUCM4x50__ */
1017  default:
1018  return ADI_RTC_FAILURE;
1019  }
1020  }
1021  ADI_EXIT_CRITICAL_REGION();
1022 
1023  /* Wait till write to Control Register to take effect */
1024  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)
1025 
1026  return ADI_RTC_SUCCESS;
1027 }
1028 #if defined(__ADUCM302x__)
1029 
1044  ADI_RTC_SS_CHANNEL eSSChannel,
1045  uint16_t nValue)
1046 #elif defined(__ADUCM4x50__)
1047 
1063  ADI_RTC_SS_CHANNEL eSSChannel,
1064  uint16_t nLowValue,
1065  uint16_t nHighValue)
1066 #endif
1067 {
1068  ADI_RTC_DEVICE *pDevice = hDevice;
1069 
1070 #ifdef ADI_DEBUG
1071  ADI_RTC_RESULT eResult;
1072  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1073  {
1074  return eResult;
1075  }
1076 #endif
1077 
1078  switch( eSSChannel )
1079  {
1080  case ADI_RTC_SS_CHANNEL_1:
1081  /* Wait till previously posted write to Control Register to complete */
1082  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
1083 #if defined(__ADUCM4x50__)
1084  pDevice->pRTCRegs->SS1LOWDUR = nLowValue;
1085  pDevice->pRTCRegs->SS1HIGHDUR= nHighValue;
1086 #else
1087  pDevice->pRTCRegs->SS1ARL = nValue;
1088 #endif
1089  /* Wait till write to Control Register to take effect */
1090  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)
1091  break;
1092 #if defined(__ADUCM4x50__)
1093  case ADI_RTC_SS_CHANNEL_2:
1094  /* Wait till previously posted write to Control Register to complete */
1095  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
1096  pDevice->pRTCRegs->SS2LOWDUR = nLowValue;
1097  pDevice->pRTCRegs->SS2HIGHDUR= nHighValue;
1098  /* Wait till write to Control Register to take effect */
1099  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)
1100  break;
1101 
1102  case ADI_RTC_SS_CHANNEL_3:
1103  /* Wait till previously posted write to Control Register to complete */
1104  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
1105  pDevice->pRTCRegs->SS3LOWDUR = nLowValue;
1106  pDevice->pRTCRegs->SS3HIGHDUR= nHighValue;
1107  /* Wait till write to Control Register to take effect */
1108  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)
1109  break;
1110 
1111 #endif /* __ADUCM4x50__ */
1112 
1113  default:
1114  return ADI_RTC_FAILURE;
1115 
1116  }
1117 
1118  return ADI_RTC_SUCCESS;
1119 }
1135 {
1136  ADI_RTC_DEVICE *pDevice = hDevice;
1137 
1138 #ifdef ADI_DEBUG
1139  ADI_RTC_RESULT eResult;
1140  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1141  {
1142  return eResult;
1143  }
1144 #endif
1145  /* Wait till previously posted write to Control Register to complete */
1146  PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDCR4SS)
1147 
1148  ADI_INT_STATUS_ALLOC();
1149  ADI_ENTER_CRITICAL_REGION();
1150  /* set/clear auto reload enable options */
1151  if (bEnable)
1152  {
1153  pDevice->pRTCRegs->CR4SS |= (uint16_t)eSSChannel;
1154  }
1155  else
1156  {
1157  pDevice->pRTCRegs->CR4SS &= (uint16_t)~(uint16_t)eSSChannel;
1158  }
1159  ADI_EXIT_CRITICAL_REGION();
1160 
1161  /* Wait till write to Control Register to take effect */
1162  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)
1163 
1164  return ADI_RTC_SUCCESS;
1165 }
1166 
1180 {
1181  ADI_RTC_DEVICE *pDevice = hDevice;
1182  uint16_t MaskPos = 0u;
1183 
1184 #ifdef ADI_DEBUG
1185  ADI_RTC_RESULT eResult;
1186  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1187  {
1188  return eResult;
1189  }
1190 #endif
1191 
1192  switch( eSSChannel )
1193  {
1194  case ADI_RTC_SS_CHANNEL_1:
1195  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS1MSK;
1196  break;
1197 #if defined(__ADUCM4x50__)
1198  case ADI_RTC_SS_CHANNEL_2:
1199  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS2MSK;
1200  break;
1201 
1202  case ADI_RTC_SS_CHANNEL_3:
1203  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS3MSK;
1204  break;
1205 
1206  case ADI_RTC_SS_CHANNEL_4:
1207  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS4MSK;
1208  break;
1209 #endif /* __ADUCM4x50__ */
1210  default:
1211  return ADI_RTC_INVALID_CHANNEL;
1212  }
1213 
1214  /* Wait till previously posted write to Control Register to complete */
1215  PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDSSMSK)
1216 
1217  /*Set mask setting for sensor strobe channel*/
1218  pDevice->pRTCRegs->SSMSK |= ((uint16_t)nMask & 0xFu) << MaskPos;
1219 
1220  /* Wait till write to Control Register to take effect */
1221  SYNC_AFTER_WRITE(SR4, BITM_RTC_SR4_WSYNCSSMSK)
1222 
1223  return ADI_RTC_SUCCESS;
1224 }
1225 
1226 /*************************************************************************************************
1227 **************************************************************************************************
1228 ****************************************** GET APIS ******************************************
1229 **************************************************************************************************
1230 *************************************************************************************************/
1231 
1232 
1250 {
1251  ADI_RTC_DEVICE *pDevice = hDevice;
1252  uint32_t nAlarm;
1253 #ifdef ADI_DEBUG
1254  ADI_RTC_RESULT eResult;
1255  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1256  {
1257  return eResult;
1258  }
1259 #endif
1260 
1261  /* Wait till previously posted write to Control Register to complete */
1262  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
1263 
1264  /* disable interrupts during paired read */
1265  NVIC_DisableIRQ(pDevice->eIRQn);
1266  nAlarm =(uint32_t) pDevice->pRTCRegs->ALM1 << 16u;
1267  nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
1268  NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
1269 
1270  *pAlarm = nAlarm;
1271 
1272  return ADI_RTC_SUCCESS;
1273 }
1291 {
1292  ADI_RTC_DEVICE *pDevice = hDevice;
1293  uint32_t nAlarm,nTemp;
1294  uint16_t nPreScale;
1295  float fFraction;
1296 #ifdef ADI_DEBUG
1297  ADI_RTC_RESULT eResult;
1298  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1299  {
1300  return eResult;
1301  }
1302 #endif
1303 
1304  /* Wait till previously posted write to Control Register to complete */
1305  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
1306  nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
1307  /* disable interrupts during paired read */
1308  NVIC_DisableIRQ(pDevice->eIRQn);
1309  nAlarm = (uint32_t)pDevice->pRTCRegs->ALM1 << 16u;
1310  nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
1311  NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
1312  nTemp = 1lu<<nPreScale;
1313  fFraction = (float)pDevice->pRTCRegs->ALM2 /(float)(nTemp);
1314 
1315  *pAlarm = (float)nAlarm+fFraction;
1316 
1317  return ADI_RTC_SUCCESS;
1318 }
1319 
1320 
1338 ADI_RTC_RESULT adi_rtc_GetAlarmRegs(ADI_RTC_HANDLE hDevice, uint16_t *pAlarm0,uint16_t *pAlarm1,uint16_t *pAlarm2)
1339 {
1340  ADI_RTC_DEVICE *pDevice = hDevice;
1342 
1343 #ifdef ADI_DEBUG
1344  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1345  {
1346  return eResult;
1347  }
1348 #endif
1349 
1350  /* Wait till previously posted write to Control Register to complete */
1351  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
1352 
1353  /* disable interrupts during paired read */
1354  NVIC_DisableIRQ(pDevice->eIRQn);
1355  *pAlarm0= pDevice->pRTCRegs->ALM0;
1356  *pAlarm1= pDevice->pRTCRegs->ALM1;
1357  *pAlarm2= pDevice->pRTCRegs->ALM2;
1358  NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
1359 
1360  return eResult;
1361 }
1362 
1363 
1383 {
1384  ADI_RTC_DEVICE *pDevice = hDevice;
1385 
1386 #ifdef ADI_DEBUG
1387  ADI_RTC_RESULT eResult;
1388  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1389  {
1390  return eResult;
1391  }
1392 #endif
1393  /* Wait till previously posted write to Control Register to complete */
1394  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
1395 
1396  switch(eRegister)
1397  {
1399  *pControl = pDevice->pRTCRegs->CR0;
1400  break;
1402  *pControl = pDevice->pRTCRegs->CR1;
1403  break;
1404  default:
1405  return(ADI_RTC_FAILURE);
1406  }
1407  return ADI_RTC_SUCCESS;
1408 }
1409 
1410 
1430 ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount)
1431 {
1432  struct adi_rtc_snapshots snapshots;
1433  ADI_RTC_RESULT eResult;
1434 
1435 #ifdef ADI_DEBUG
1436  if((eResult = ValidateHandle(hDevice)) != ADI_RTC_SUCCESS)
1437  {
1438  return eResult;
1439  }
1440 #endif
1441 
1442  eResult = adi_rtc_GetCoherentCounterValues(hDevice, &snapshots);
1443 
1444  /* snapshots maps to the chosen valid sample or to 0 */
1445  *pCount = (((uint32_t)snapshots.snapshot1) << 16u) | snapshots.snapshot0; /* combine RTC_CNT1 and RTC_CNT0 */
1446 
1447  return eResult;
1448 }
1466 ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount)
1467 {
1468  struct adi_rtc_snapshots snapshots;
1469  ADI_RTC_RESULT eResult;
1470  uint32_t nCount,nTemp;
1471  uint16_t nPrescale;
1472  ADI_RTC_DEVICE *pDevice = hDevice;
1473  float fFraction;
1474 
1475 #ifdef ADI_DEBUG
1476  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1477  {
1478  return eResult;
1479  }
1480 #endif
1481 
1482  eResult = adi_rtc_GetCoherentCounterValues(hDevice, &snapshots);
1483 
1484  nPrescale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
1485  nCount = (((uint32_t)snapshots.snapshot1) << 16u) | snapshots.snapshot0; /* combine RTC_CNT1 and RTC_CNT0 */
1486  nTemp = (1lu<<nPrescale);
1487  fFraction = ((float)snapshots.snapshot2)/((float)nTemp);
1488  *pfCount = ((float)nCount) + fFraction;
1489 
1490  return eResult;
1491 }
1510 ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount)
1511 {
1512  ADI_RTC_RESULT eResult;
1513  struct adi_rtc_snapshots snapshots;
1514 
1515 #ifdef ADI_DEBUG
1516  ADI_RTC_DEVICE *pDevice = hDevice;
1517 
1518  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1519  {
1520  return eResult;
1521  }
1522 #endif
1523 
1524  eResult = adi_rtc_GetCoherentCounterValues(hDevice, &snapshots);
1525 
1526  *pnCount = (((uint32_t)snapshots.snapshot1) << 16u) | snapshots.snapshot0; /* combine RTC_CNT1 and RTC_CNT0 */
1527  *pfCount = (uint32_t)snapshots.snapshot2;
1528 
1529  return eResult;
1530 }
1531 
1564 {
1565  ADI_RTC_DEVICE *pDevice = hDevice;
1566  uint32_t nInterrupt = 0u;
1567 #ifdef ADI_DEBUG
1568  ADI_RTC_RESULT eResult;
1569  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1570  {
1571  return eResult;
1572  }
1573 #endif
1574 
1575  /* Read SR0 interrupts bits (mask out unused bits) and store the bits in the first byte, the LSB */
1576  nInterrupt = ((((uint32_t)pDevice->pRTCRegs->SR0) & ADI_RTC_IRQ_SOURCE_MASK_SR0) << ADI_RTC_IRQ_SOURCE_OFFSET_SR0);
1577 
1578  /* Read SR3 interrupts bits (mask out unused bits) and store the bits in the third and fourth bytes */
1579  nInterrupt |= ((((uint32_t)pDevice->pRTCRegs->SR3) & ADI_RTC_IRQ_SOURCE_MASK_SR3) << ADI_RTC_IRQ_SOURCE_OFFSET_SR3);
1580 
1581  /* For SR2, take RTC0 and RTC1 specific interrupts into account, mask out unused bits and store the value in the second byte */
1582  if( pDevice->pRTCRegs == pADI_RTC1)
1583  {
1584  nInterrupt |= ((((uint32_t)pDevice->pRTCRegs->SR2) & ADI_RTC1_IRQ_SOURCE_MASK_SR2) << ADI_RTC_IRQ_SOURCE_OFFSET_SR2);
1585  }else{
1586  nInterrupt |= ((((uint32_t)pDevice->pRTCRegs->SR2) & ADI_RTC0_IRQ_SOURCE_MASK_SR2) << ADI_RTC_IRQ_SOURCE_OFFSET_SR2);
1587  }
1588 
1589  /* store the value in the out parameter */
1590  *pStatus = (ADI_RTC_INT_TYPE)nInterrupt;
1591  return ADI_RTC_SUCCESS;
1592 }
1593 
1594 
1595 
1630 {
1631  ADI_RTC_DEVICE *pDevice = hDevice;
1632  uint32_t nStatus;
1633 
1634 #ifdef ADI_DEBUG
1635 
1636  /* This ADI_DEBUG macro-guarded code section checks that the bits set in the input parameter
1637  * Status are valid bits, mapped to interrupt bits in the SR0, SR2 and SR3 registers */
1638 
1639  ADI_RTC_RESULT eResult;
1640  uint32_t validInput = ( (((uint32_t) ADI_RTC_IRQ_SOURCE_MASK_SR0) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR0))
1641  | (((uint32_t) ADI_RTC_IRQ_SOURCE_MASK_SR3) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR3))
1642  );
1643 
1644  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1645  {
1646  return eResult;
1647  }
1648 
1649  /* Take RTC0 and RTC1 specific interrupts into account when defining valid inputs */
1650  if( pDevice->pRTCRegs == pADI_RTC1)
1651  {
1652  /* RTC1: SR2 and SR3 registers also have RTC1 specific interrupts bits */
1653  validInput |= (((uint32_t) ADI_RTC1_IRQ_SOURCE_MASK_SR2) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR2));
1654  }else{
1655  /* RTC0: SR2 register also has RTC0 specific interrupts bits */
1656  validInput |= (((uint32_t) ADI_RTC0_IRQ_SOURCE_MASK_SR2) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR2));
1657  }
1658 
1659  /* At least one of the possible interrupt bits must be set in Status (else there are no bits to clear...) */
1660  if ((((uint32_t)Status) & validInput) == 0u)
1661  {
1662  return ADI_RTC_INVALID_PARAM;
1663  }
1664 #endif
1665 
1666  /* Wait till previously posted write to Control Register to complete */
1667  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0)
1668 
1669  /* get the interrupt bits to clear in SR0 */
1670  nStatus = ((uint32_t)ADI_RTC_IRQ_SOURCE_MASK_SR0) & (((uint32_t) Status) >> ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR0));
1671 
1672  /* and write them in SR0 */
1673  pDevice->pRTCRegs->SR0 |= (uint16_t) nStatus;
1674 
1675  /* Wait till write to Control Register to take effect */
1676  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0)
1677 
1678  /* get the interrupt bits to clear in SR2 (these bits are RTC0 and RTC1 specific) */
1679  nStatus = ((uint32_t) Status) >> ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR2);
1680  if(pDevice->pRTCRegs == pADI_RTC1)
1681  {
1682  /* RTC1 specific interrupt bits in SR2 */
1683  nStatus &= ((uint32_t) ADI_RTC1_IRQ_SOURCE_MASK_SR2);
1684  }else{
1685  /* RTC0 specific interrupt bits in SR2 */
1686  nStatus &= ((uint32_t) ADI_RTC0_IRQ_SOURCE_MASK_SR2);
1687  }
1688  /* and write them in SR2 */
1689  pDevice->pRTCRegs->SR2 |= (uint16_t) nStatus;
1690 
1691  /* get the interrupt bits to clear in SR3 */
1692  nStatus = ((uint32_t)ADI_RTC_IRQ_SOURCE_MASK_SR3) & (((uint32_t) Status) >> ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR3));
1693 
1694  /* and write them in SR3 */
1695  pDevice->pRTCRegs->SR3 |= (uint16_t) nStatus;
1696 
1697  return ADI_RTC_SUCCESS;
1698 }
1699 
1700 
1722 {
1723  ADI_RTC_DEVICE *pDevice = hDevice;
1724 #ifdef ADI_DEBUG
1725  ADI_RTC_RESULT eResult;
1726  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1727  {
1728  return eResult;
1729  }
1730  if(peTrim == NULL)
1731  {
1732  return( ADI_RTC_INVALID_PARAM);
1733  }
1734 #endif
1735 
1736  /* Wait till previously posted write to couunt Register to complete */
1737  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM);
1738 
1739  *peTrim =(ADI_RTC_TRIM_VALUE)(pDevice->pRTCRegs->TRM & BITM_RTC_TRM_VALUE);
1740 
1741  return ADI_RTC_SUCCESS;
1742 }
1761 {
1762  ADI_RTC_DEVICE *pDevice = hDevice;
1763 
1764 #ifdef ADI_DEBUG
1765  ADI_RTC_RESULT eResult;
1766  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1767  {
1768  return eResult;
1769  }
1770 #endif
1771  switch( eSSChannel )
1772  {
1773  case ADI_RTC_SS_CHANNEL_1:
1774  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
1775  *pValue = pDevice->pRTCRegs->SS1;
1776  break;
1777 #if defined(__ADUCM4x50__)
1778  case ADI_RTC_SS_CHANNEL_2:
1779  /* Wait till previously posted write to Control Register to complete */
1780  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
1781  *pValue = pDevice->pRTCRegs->SS2;
1782  break;
1783 
1784  case ADI_RTC_SS_CHANNEL_3:
1785  /* Wait till previously posted write to Control Register to complete */
1786  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
1787  *pValue = pDevice->pRTCRegs->SS3;
1788  break;
1789 
1790  case ADI_RTC_SS_CHANNEL_4:
1791  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
1792  *pValue = pDevice->pRTCRegs->SS4;
1793  break;
1794 #endif /* __ADUCM4x50__ */
1795  default:
1796  return ADI_RTC_FAILURE;
1797  }
1798 
1799 
1800 
1801  return ADI_RTC_SUCCESS;
1802 }
1821 {
1822  ADI_RTC_DEVICE *pDevice = hDevice;
1823 #ifdef ADI_DEBUG
1824  ADI_RTC_RESULT eResult;
1825  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1826  {
1827  return eResult;
1828  }
1829 #endif
1830 
1831  switch( eSSChannel )
1832  {
1833  case ADI_RTC_SS_CHANNEL_1:
1834  /* Wait till previously posted write to Control Register to complete */
1835  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
1836  pDevice->pRTCRegs->SS1 = nValue;
1837  /* Wait till write to Control Register to take effect */
1838  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)
1839  break;
1840 
1841 #if defined(__ADUCM4x50__)
1842  case ADI_RTC_SS_CHANNEL_2:
1843  /* Wait till previously posted write to Control Register to complete */
1844  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
1845  pDevice->pRTCRegs->SS2 = nValue;
1846  /* Wait till write to Control Register to take effect */
1847  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)
1848  break;
1849 
1850  case ADI_RTC_SS_CHANNEL_3:
1851  /* Wait till previously posted write to Control Register to complete */
1852  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
1853  pDevice->pRTCRegs->SS3 = nValue;
1854  /* Wait till write to Control Register to take effect */
1855  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)
1856  break;
1857 
1858  case ADI_RTC_SS_CHANNEL_4:
1859  /* Wait till previously posted write to Control Register to complete */
1860  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
1861  pDevice->pRTCRegs->SS4 = nValue;
1862  /* Wait till write to Control Register to take effect */
1863  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4)
1864  break;
1865 #endif /* __ADUCM4x50__ */
1866  default:
1867  return ADI_RTC_FAILURE;
1868  }
1869 
1870  return ADI_RTC_SUCCESS;
1871 }
1872 
1902  ADI_RTC_INPUT_CHANNEL eChannel,
1903  uint16_t *pSnap0,
1904  uint16_t *pSnap1,
1905  uint16_t *pSnap2)
1906 {
1907  ADI_RTC_DEVICE *pDevice = hDevice;
1909 #ifdef ADI_DEBUG
1910  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1911  {
1912  return eResult;
1913  }
1914 #endif
1915  switch(eChannel)
1916  {
1918  *pSnap0=pDevice->pRTCRegs->SNAP0;
1919  *pSnap1=pDevice->pRTCRegs->SNAP1;
1920  *pSnap2=pDevice->pRTCRegs->SNAP2;
1921  break;
1923  *pSnap2= pDevice->pRTCRegs->IC2;
1924  *pSnap0 = *pSnap1 = 0u;
1925  break;
1927  *pSnap2= pDevice->pRTCRegs->IC3;
1928  *pSnap0 = *pSnap1 = 0u;
1929  break;
1931  *pSnap2= pDevice->pRTCRegs->IC4;
1932  *pSnap0 = *pSnap1 = 0u;
1933  break;
1934  default:
1935  eResult = ADI_RTC_INVALID_CHANNEL;
1936  break;
1937  }
1938  return(eResult);
1939 }
1962 {
1963  ADI_RTC_DEVICE *pDevice = hDevice;
1965 
1966 #ifdef ADI_DEBUG
1967  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1968  {
1969  return eResult;
1970  }
1971 #endif
1972  switch(eChannel)
1973  {
1975  *pValue = pDevice->pRTCRegs->IC2;
1976  break;
1978  *pValue = pDevice->pRTCRegs->IC3;
1979  break;
1980 
1982  *pValue = pDevice->pRTCRegs->IC4;
1983  break;
1984  default:
1985  eResult = ADI_RTC_INVALID_CHANNEL;
1986  break;
1987  }
1988  return(eResult);
1989 }
2011 ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction)
2012 {
2013  ADI_RTC_DEVICE *pDevice = hDevice;
2014  ADI_RTC_RESULT eResult = ADI_RTC_SUCCESS;
2015 
2016 #ifdef ADI_DEBUG
2017  if((eResult = ValidateHandle(hDevice)) != ADI_RTC_SUCCESS)
2018  {
2019  return eResult;
2020  }
2021 
2022  if((NULL == pValue) || (NULL == pFraction) || (ADI_RTC_INPUT_CHANNEL_0 != eChannel))
2023  {
2024  return (ADI_RTC_INVALID_PARAM);
2025  }
2026 #endif
2027 
2028  *pFraction = pDevice->pRTCRegs->SNAP2;
2029  *pValue = (uint32_t)pDevice->pRTCRegs->SNAP1 << 16u;
2030  *pValue |= (uint32_t)pDevice->pRTCRegs->SNAP0;
2031 
2032  return(eResult);
2033 }
2034 
2035 
2077 {
2078  ADI_RTC_DEVICE *pDevice = hDevice;
2079  uint16_t nPendBits;
2080 #ifdef ADI_DEBUG
2081  ADI_RTC_RESULT eResult;
2082  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2083  {
2084  return eResult;
2085  }
2086 #endif
2087  /* get the value */
2088  nPendBits = pDevice->pRTCRegs->SR1 & ADI_RTC_WRITE_STATUS_MASK;
2089  *pPendBits = (ADI_RTC_WRITE_STATUS)nPendBits;
2090 
2091  return ADI_RTC_SUCCESS;
2092 }
2093 
2094 
2136 {
2137  ADI_RTC_DEVICE *pDevice = hDevice;
2138  uint16_t nSyncBits;
2139 #ifdef ADI_DEBUG
2140  ADI_RTC_RESULT eResult;
2141  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2142  {
2143  return eResult;
2144  }
2145 #endif
2146  /* Wait till previously posted write to couunt Register to complete */
2147  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0);
2148 
2149  /* get the value */
2150  nSyncBits = pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK;
2151  *pSyncBits = (ADI_RTC_WRITE_STATUS)nSyncBits;
2152 
2153  return ADI_RTC_SUCCESS;
2154 }
2155 
2156 
2168 ADI_RTC_RESULT adi_rtc_GetISOENB (ADI_RTC_HANDLE const hDevice, uint16_t *pValue)
2169 {
2170  ADI_RTC_DEVICE *pDevice = hDevice;
2171 #ifdef ADI_DEBUG
2172  ADI_RTC_RESULT eResult;
2173  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2174  {
2175  return eResult;
2176  }
2177 #endif
2178 
2179  *pValue = (pDevice->pRTCRegs->SR0 & BITM_RTC_SR0_ISOENB) >> BITP_RTC_SR0_ISOENB;
2180 
2181  return ADI_RTC_SUCCESS;
2182 }
2183 
2184 
2185 /*************************************************************************************************
2186 **************************************************************************************************
2187 ****************************************** SET APIS ******************************************
2188 **************************************************************************************************
2189 *************************************************************************************************/
2190 
2191 
2213 ADI_RTC_RESULT adi_rtc_SetAlarm (ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
2214 {
2215  ADI_RTC_DEVICE *pDevice = hDevice;
2216 #ifdef ADI_DEBUG
2217  ADI_RTC_RESULT eResult;
2218  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2219  {
2220  return eResult;
2221  }
2222 #endif
2223 
2224  /* Wait till previously posted write to Alram Register to complete */
2225  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2226 
2227  ADI_INT_STATUS_ALLOC();
2228  ADI_ENTER_CRITICAL_REGION();
2229  /* RTC hardware insures paired write, so no need to disable interrupts */
2230  pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
2231  pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
2232  pDevice->pRTCRegs->ALM2 = 0u;
2233  ADI_EXIT_CRITICAL_REGION();
2234 
2235  /* Wait till write to Control Register to take effect */
2236  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2237  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2238 
2239  return ADI_RTC_SUCCESS;
2240 }
2241 
2265 ADI_RTC_RESULT adi_rtc_SetAlarmRegs (ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0,uint16_t nAlarm1,uint16_t nAlarm2)
2266 {
2267  ADI_RTC_DEVICE *pDevice = hDevice;
2269 
2270 #ifdef ADI_DEBUG
2271 
2272  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2273  {
2274  return eResult;
2275  }
2276 #endif
2277 
2278  /* Wait till previously posted write to Alarm Register to complete */
2279  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2280 
2281  ADI_INT_STATUS_ALLOC();
2282  ADI_ENTER_CRITICAL_REGION();
2283  /* RTC hardware insures paired write, so no need to disable interrupts */
2284  pDevice->pRTCRegs->ALM0 = nAlarm0;
2285  pDevice->pRTCRegs->ALM1 = nAlarm1;
2286  pDevice->pRTCRegs->ALM2 = nAlarm2;
2287  ADI_EXIT_CRITICAL_REGION();
2288 
2289  /* Wait till write to Control Register to take effect */
2290  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2291  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2292 
2293  return eResult;
2294 }
2295 
2321 ADI_RTC_RESULT adi_rtc_SetAlarmAsync (ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
2322 {
2323  ADI_RTC_DEVICE *pDevice = hDevice;
2324 #ifdef ADI_DEBUG
2325  ADI_RTC_RESULT eResult;
2326  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2327  {
2328  return eResult;
2329  }
2330 #endif
2331 
2332  /* Wait till previously posted write to Alram Register to complete */
2333  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2334 
2335  ADI_INT_STATUS_ALLOC();
2336  ADI_ENTER_CRITICAL_REGION();
2337  /* RTC hardware insures paired write, so no need to disable interrupts */
2338  pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
2339  pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
2340  pDevice->pRTCRegs->ALM2 = 0u;
2341  ADI_EXIT_CRITICAL_REGION();
2342 
2343  return ADI_RTC_SUCCESS;
2344 }
2345 
2371 ADI_RTC_RESULT adi_rtc_SetAlarmRegsAsync (ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0,uint16_t nAlarm1,uint16_t nAlarm2)
2372 {
2373  ADI_RTC_DEVICE *pDevice = hDevice;
2375 
2376 #ifdef ADI_DEBUG
2377 
2378  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2379  {
2380  return eResult;
2381  }
2382 #endif
2383 
2384  /* Wait till previously posted write to Alarm Register to complete */
2385  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2386 
2387  ADI_INT_STATUS_ALLOC();
2388  ADI_ENTER_CRITICAL_REGION();
2389  /* RTC hardware insures paired write, so no need to disable interrupts */
2390  pDevice->pRTCRegs->ALM0 = nAlarm0;
2391  pDevice->pRTCRegs->ALM1 = nAlarm1;
2392  pDevice->pRTCRegs->ALM2 = nAlarm2;
2393  ADI_EXIT_CRITICAL_REGION();
2394 
2395  return eResult;
2396 }
2397 
2420 {
2421  ADI_RTC_DEVICE *pDevice = hDevice;
2422 #ifdef ADI_DEBUG
2423  ADI_RTC_RESULT eResult;
2424  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2425  {
2426  return eResult;
2427  }
2428 #endif
2429 
2430  /* Wait till write to Control Register to take effect */
2431  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2432  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2433 
2434  return ADI_RTC_SUCCESS;
2435 }
2436 
2455 ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const hDevice, uint8_t nPreScale )
2456 {
2457  ADI_RTC_DEVICE *pDevice = hDevice;
2458  uint16_t nTemp;
2459 #ifdef ADI_DEBUG
2460  ADI_RTC_RESULT eResult;
2461  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2462  {
2463  return eResult;
2464  }
2465  /* Pre scale is invalid for RTC0 */
2466  if(pDevice->pRTCRegs == pADI_RTC0)
2467  {
2469  }
2470 #endif
2471  PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
2472  ADI_INT_STATUS_ALLOC();
2473  ADI_ENTER_CRITICAL_REGION();
2474  /* RTC hardware insures paired write, so no need to disable interrupts */
2475  /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
2476  nTemp = pDevice->pRTCRegs->CR1 & (uint16_t)~BITM_RTC_CR1_PRESCALE2EXP;
2477  nTemp |= (uint16_t)((uint16_t)nPreScale << BITP_RTC_CR1_PRESCALE2EXP);
2478  pDevice->pRTCRegs->CR1 = nTemp;
2479  ADI_EXIT_CRITICAL_REGION();
2480 
2481  SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)
2482  return ADI_RTC_SUCCESS;
2483 }
2503 {
2504  ADI_RTC_DEVICE *pDevice = hDevice;
2505  uint16_t nTemp;
2506 #ifdef ADI_DEBUG
2507  ADI_RTC_RESULT eResult;
2508  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2509  {
2510  return eResult;
2511  }
2512 
2513  /* Mod60 Alarm is valid only in RTC-1 */
2514  if(pDevice->pRTCRegs == pADI_RTC0)
2515  {
2517  }
2518 
2519 #endif
2520 
2521  /* Wait till previously posted write to Control Register to complete */
2522  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
2523 
2524  ADI_INT_STATUS_ALLOC();
2525  ADI_ENTER_CRITICAL_REGION();
2526  /* RTC hardware insures paired write, so no need to disable interrupts */
2527  /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
2528  nTemp = pDevice->pRTCRegs->CR0 & BITM_RTC_CR0_MOD60ALM;
2529  nTemp |= (uint16_t)((uint16_t)nPeriod << BITP_RTC_CR0_MOD60ALM);
2530  pDevice->pRTCRegs->CR0 = nTemp;
2531  ADI_EXIT_CRITICAL_REGION();
2532  /* Wait till write to Control Register to take effect */
2533  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
2534 
2535  return ADI_RTC_SUCCESS;
2536 }
2559 {
2560  ADI_RTC_DEVICE *pDevice = hDevice;
2561  uint32_t nAlarm = (uint32_t)fAlarm,nTemp;
2562  uint16_t nPreScale;
2563  float fFraction;
2564 #ifdef ADI_DEBUG
2565  ADI_RTC_RESULT eResult;
2566  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2567  {
2568  return eResult;
2569  }
2570  /* Only 1Hz clocking is supported in RTC-0.So no fractional Alarm. */
2571  if(pDevice->pRTCRegs == pADI_RTC0)
2572  {
2574  }
2575 
2576 #endif
2577 
2578  /* Wait till previously posted write to Alarm Register to complete */
2579  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2580  nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
2581  ADI_INT_STATUS_ALLOC();
2582  ADI_ENTER_CRITICAL_REGION();
2583  /* RTC hardware insures paired write, so no need to disable interrupts */
2584  /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
2585  pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
2586  pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
2587  nTemp = 1lu<<nPreScale;
2588  fFraction = (fAlarm - (float)nAlarm) *(float)(nTemp);
2589  pDevice->pRTCRegs->ALM2 = (uint16_t)(fFraction);
2590  ADI_EXIT_CRITICAL_REGION();
2591  /* Wait till write to Alarm Register to take effect */
2592  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2593  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2594 
2595  return ADI_RTC_SUCCESS;
2596 }
2597 
2620 {
2621  ADI_RTC_DEVICE *pDevice = hDevice;
2622 
2623 #ifdef ADI_DEBUG
2624  ADI_RTC_RESULT eResult;
2625  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2626  {
2627  return eResult;
2628  }
2629 #endif
2630  /* Wait till previously posted write to Control Register to complete */
2631  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
2632 
2633  switch(eRegister)
2634  {
2636  pDevice->pRTCRegs->CR0 = (uint16_t)Control;
2637  break;
2639  pDevice->pRTCRegs->CR1 = (uint16_t)Control;
2640  break;
2641  default:
2642  return(ADI_RTC_FAILURE);
2643  }
2644  /* Wait till write to Control Register to take effect */
2645  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
2646 
2647  return ADI_RTC_SUCCESS;
2648 
2649 }
2650 
2668  ADI_RTC_HANDLE const hDevice,
2669  ADI_CALLBACK const pfCallback,
2670  void *const pCBparam
2671  )
2672 
2673 {
2674  ADI_RTC_DEVICE *pDevice = hDevice;
2675 
2676 #ifdef ADI_DEBUG
2677  ADI_RTC_RESULT eResult;
2678  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2679  {
2680  return eResult;
2681  }
2682 #endif
2683 
2684 #if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
2685  /* pause on pending writes to CR to avoid data loss */
2686  while((pDevice->pRTCRegs->SR1 & (uint32_t)ADI_RTC_WRITE_STATUS_CONTROL0)!=0u)
2687  {
2688  }
2689 #endif
2690  /* Store the address of the callback function */
2691  pDevice->pfCallback = pfCallback;
2692  /* Store the call back parameter */
2693  pDevice->pCBParam = pCBparam;
2694 
2695  return ADI_RTC_SUCCESS;
2696 
2697 }
2698 
2719 ADI_RTC_RESULT adi_rtc_SetCount (ADI_RTC_HANDLE const hDevice, uint32_t nCount)
2720 {
2721  ADI_RTC_DEVICE *pDevice = hDevice;
2722 
2723 #ifdef ADI_DEBUG
2724  ADI_RTC_RESULT eResult;
2725  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2726  {
2727  return eResult;
2728  }
2729 #endif
2730 
2731 #if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
2732  /* pause on pending writes to CR to avoid data loss */
2733  while((pDevice->pRTCRegs->SR1 & (uint32_t)(ADI_RTC_WRITE_STATUS_COUNT0 | ADI_RTC_WRITE_STATUS_COUNT1)) !=0u)
2734  {
2735 
2736  }
2737 #endif
2738 
2739  /* Wait till previously posted write to count Register to complete */
2740  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
2741 
2742  ADI_INT_STATUS_ALLOC();
2743  ADI_ENTER_CRITICAL_REGION();
2744  /* RTC hardware insures paired write, so no need to disable interrupts */
2745  pDevice->pRTCRegs->CNT0 = (uint16_t)nCount;
2746  pDevice->pRTCRegs->CNT1 = (uint16_t)(nCount >> 16);
2747  ADI_EXIT_CRITICAL_REGION();
2748 
2749  /* Wait till write to count Register to take effect */
2750  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1))
2751 
2752  return ADI_RTC_SUCCESS;
2753 }
2754 
2755 
2777 ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command)
2778 {
2779  ADI_RTC_DEVICE *pDevice = hDevice;
2780 
2781 #ifdef ADI_DEBUG
2782  ADI_RTC_RESULT eResult;
2783  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2784  {
2785  return eResult;
2786  }
2787 #endif
2788  /* set the command */
2789  pDevice->pRTCRegs->GWY = Command;
2790  return ADI_RTC_SUCCESS;
2791 }
2792 
2793 
2794 
2820 {
2821  ADI_RTC_DEVICE *pDevice = hDevice;
2822  uint32_t trm = (uint32_t)eInterval | (uint32_t)eTrimValue | (uint32_t)eOperation;
2823 
2824 #ifdef ADI_DEBUG
2825  ADI_RTC_RESULT eResult;
2826  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2827  {
2828  return eResult;
2829  }
2830 
2831 #endif
2832 
2833  /* Wait till previously posted write to Control Register to complete */
2834  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM)
2835 
2836  pDevice->pRTCRegs->TRM = (uint16_t)trm;
2837 
2838  /* Wait till write to Control Register to take effect */
2839  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCTRM)
2840 
2841  return ADI_RTC_SUCCESS;
2842 }
2843 
2844 
2845 /*************************************************************************************************
2846 **************************************************************************************************
2847 ************************************ SYNCHRONIZATION API *************************************
2848 **************************************************************************************************
2849 *************************************************************************************************/
2850 
2851 
2868 {
2869  ADI_RTC_DEVICE *pDevice = hDevice;
2870 #ifdef ADI_DEBUG
2871  ADI_RTC_RESULT eResult;
2872  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2873  {
2874  return eResult;
2875  }
2876 
2877 #endif
2878 
2879  /* forced block until all SYNC bits are set (ignore bSafe) */
2880  while (ADI_RTC_WRITE_STATUS_MASK != (pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK))
2881  {
2882 
2883  }
2884 
2885  return ADI_RTC_SUCCESS;
2886 }
2887 
2888 
2891 /*
2892  * @brief Initializes the device using static configuration
2893  *
2894  * @param[in] pDevice Pointer to RTC device .
2895  pConfig Pointer to static configuration device structure.
2896  *
2897 */
2898 
2899 static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig)
2900 {
2901  /* Control register -0 which controls all main stream activity of RTC0 */
2902  ALWAYS_PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
2903  pDevice->pRTCRegs->CR0 = pConfig->CR0;
2904 
2905  /* Control register -1 which is granularity of RTC control register */
2906  ALWAYS_PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
2907  pDevice->pRTCRegs->CR1 = pConfig->CR1;
2908 
2909  /*CNT0 contains the lower 16 bits of the RTC counter */
2910  /*CNT1 contains the upper 16 bits of the RTC counter */
2911  ALWAYS_PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
2912  pDevice->pRTCRegs->CNT0 = pConfig->CNT0;
2913  pDevice->pRTCRegs->CNT1 = pConfig->CNT1;
2914 
2915  /* ALM0 contains the lower 16 bits of the Alarm register */
2916  /* ALM1 contains the upper 16 bits of the Alarm register */
2917  ALWAYS_PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2918  pDevice->pRTCRegs->ALM0 = pConfig->ALM0;
2919  pDevice->pRTCRegs->ALM1 = pConfig->ALM1;
2920 
2921  /* ALM2 contains the fractional part of the Alarm register */
2922  ALWAYS_PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDALM2MIR)
2923  pDevice->pRTCRegs->ALM2 = pConfig->ALM2;
2924 
2925  /* Set Input capture/sensor strobe registers only for RTC1 */
2926  if(pDevice->pRTCRegs == pADI_RTC1)
2927  {
2928  ALWAYS_PEND_BEFORE_WRITE(SR5,(BITM_RTC_SR5_WPENDCR2IC|BITM_RTC_SR5_WPENDCR3SS|BITM_RTC_SR5_WPENDCR4SS|BITM_RTC_SR5_WPENDSSMSK|BITM_RTC_SR5_WPENDSS1))
2929  pDevice->pRTCRegs->CR2IC = pConfig->CR2IC;
2930  pDevice->pRTCRegs->CR3SS = pConfig->CR3SS;
2931  pDevice->pRTCRegs->CR4SS = pConfig->CR4SS;
2932  pDevice->pRTCRegs->SSMSK = pConfig->SSMSK;
2933  pDevice->pRTCRegs->SS1 = pConfig->SS1;
2934 #if defined(__ADUCM4x50__)
2935  ALWAYS_PEND_BEFORE_WRITE(SR9,(BITM_RTC_SR9_WPENDCR5SSS|BITM_RTC_SR9_WPENDCR6SSS|BITM_RTC_SR9_WPENDCR7SSS|BITM_RTC_SR9_WPENDGPMUX0|BITM_RTC_SR9_WPENDGPMUX1))
2936  pDevice->pRTCRegs->CR5SSS = pConfig->CR5SSS;
2937  pDevice->pRTCRegs->CR6SSS = pConfig->CR6SSS;
2938  pDevice->pRTCRegs->CR7SSS = pConfig->CR7SSS;
2939  pDevice->pRTCRegs->GPMUX0 = pConfig->GPMUX0;
2940  pDevice->pRTCRegs->GPMUX1 = pConfig->GPMUX1;
2941 #endif /* __ADUCM4x50__ */
2942  }
2943  ALWAYS_SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCR0|BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1|BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2944  ALWAYS_SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCCR1MIR|BITM_RTC_SR2_WSYNCALM2MIR))
2945  ALWAYS_SYNC_AFTER_WRITE(SR4,(BITM_RTC_SR4_WSYNCCR2IC|BITM_RTC_SR4_WSYNCCR3SS|BITM_RTC_SR4_WSYNCCR4SS|BITM_RTC_SR4_WSYNCSSMSK|BITM_RTC_SR4_WSYNCSS1))
2946 #if defined(__ADUCM4x50__)
2947  ALWAYS_SYNC_AFTER_WRITE(SR8,(BITM_RTC_SR8_WSYNCCR5SSS|BITM_RTC_SR8_WSYNCCR6SSS|BITM_RTC_SR8_WSYNCCR7SSS|BITM_RTC_SR8_WSYNCGPMUX0|BITM_RTC_SR8_WSYNCGPMUX1))
2948 #endif
2949 }
2950 
2951 
2952 
2954 void RTC0_Int_Handler(void)
2955 {
2956  ISR_PROLOG();
2957  uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
2958  uint32_t fired = 0u, enables = 0u;
2959  ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[0].hDevice;
2960 
2961  /* determine qualified interrupt source(s) */
2962  /* need to test each interrupt source and whether it is enabled before notifying */
2963  /* because each source is latched regardless of whether it is enabled or not :-( */
2964 
2965  /* CR0 SR0 */
2966  enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0;
2967  nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_IRQ_SOURCE_MASK_SR0;
2968  if( nIntSrc0 && enables )
2969  {
2970  if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
2971  {
2972  fired |= ADI_RTC_MOD60ALM_INT;
2973  }
2974  if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
2975  {
2976  fired |= ADI_RTC_ALARM_INT;
2977  }
2978  if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
2979  {
2980  fired |= ADI_RTC_ISO_DONE_INT;
2981  }
2982  if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
2983  {
2984  fired |= ADI_RTC_WRITE_PEND_INT;
2985  }
2986  if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
2987  {
2988  fired |= ADI_RTC_WRITE_SYNC_INT;
2989  }
2990  if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
2991  {
2992  fired |= ADI_RTC_WRITE_PENDERR_INT;
2993  }
2994  }
2995 
2996  /* CR1 SR2 */
2997  enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1;
2998  nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC0_IRQ_SOURCE_MASK_SR2;
2999  if( nIntSrc2 && enables )
3000  {
3001  if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
3002  {
3003  fired |= ADI_RTC_COUNT_ROLLOVER_INT;
3004  }
3005  if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
3006  {
3007  fired |= ADI_RTC_TRIM_INT;
3008  }
3009  if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
3010  {
3011  fired |= ADI_RTC_PSI_INT;
3012  }
3013  if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
3014  {
3015  fired |= ADI_RTC_COUNT_INT;
3016  }
3017  }
3018 
3019  /* CR3OC, CR2IC SR3*/
3020  enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR3SS;
3021  nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_IRQ_SOURCE_MASK_SR3;
3022  if( nIntSrc3 && enables )
3023  {
3024 #if defined(__ADUCM4x50__)
3025  if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
3026  {
3028  }
3029  if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
3030  {
3032  }
3033  if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
3034  {
3036  }
3037 #endif /* __ADUCM4x50__ */
3038 
3039  if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
3040  {
3042  }
3043 
3044 #if defined(__ADUCM4x50__)
3045  if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
3046  {
3047  fired |= ADI_RTC_RTCSS4_FE_INT;
3048  }
3049  if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
3050  {
3051  fired |= ADI_RTC_RTCSS3_FE_INT;
3052  }
3053  if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
3054  {
3055  fired |= ADI_RTC_RTCSS2_FE_INT;
3056  }
3057  if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
3058  {
3059  fired |= ADI_RTC_RTCSS1_FE_INT;
3060  }
3061 #endif /* __ADUCM4x50__ */
3062  }
3063  enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR2IC;
3064  if( nIntSrc3 && enables )
3065  {
3066  if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
3067  {
3069  }
3070  if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
3071  {
3073  }
3074  if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
3075  {
3077  }
3078  if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
3079  {
3081  }
3082  }
3083 
3084 
3085  if (pDevice->pfCallback != NULL) {
3086 
3087  /* forward to the user if he is watching this interrupt */
3088  /* pass the "fired" value as the event. argument param is not used */
3089  if ( fired)
3090  {
3091  pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
3092  }
3093  }
3094 
3095  /* Write 1 to clear the interrupts */
3096  pDevice->pRTCRegs->SR0 = nIntSrc0;
3097  pDevice->pRTCRegs->SR2 = nIntSrc2;
3098  pDevice->pRTCRegs->SR3 = nIntSrc3;
3099  ISR_EPILOG();
3100 }
3101 
3103 void RTC1_Int_Handler(void)
3104 {
3105  ISR_PROLOG();
3106  uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
3107  uint32_t fired = 0u, enables = 0u;
3108  ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[1].hDevice;
3109 
3110  /* determine qualified interrupt source(s) */
3111  /* need to test each interrupt source and whether it is enabled before notifying */
3112  /* because each source is latched regardless of whether it is enabled or not :-( */
3113 
3114  /* CR0 SR0 */
3115  enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0;
3116  nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_IRQ_SOURCE_MASK_SR0;
3117  if( nIntSrc0 && enables )
3118  {
3119  if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
3120  {
3121  fired |= ADI_RTC_MOD60ALM_INT;
3122  }
3123  if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
3124  {
3125  fired |= ADI_RTC_ALARM_INT;
3126  }
3127  if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
3128  {
3129  fired |= ADI_RTC_ISO_DONE_INT;
3130  }
3131  if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
3132  {
3133  fired |= ADI_RTC_WRITE_PEND_INT;
3134  }
3135  if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
3136  {
3137  fired |= ADI_RTC_WRITE_SYNC_INT;
3138  }
3139  if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
3140  {
3141  fired |= ADI_RTC_WRITE_PENDERR_INT;
3142  }
3143  }
3144 
3145  /* CR1 SR2 */
3146  enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1;
3147  nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC1_IRQ_SOURCE_MASK_SR2;
3148  if( nIntSrc2 && enables )
3149  {
3150  if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT))
3151  {
3152  fired |= ADI_RTC_MOD60_ROLLOVER_INT;
3153  }
3154  if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
3155  {
3156  fired |= ADI_RTC_COUNT_ROLLOVER_INT;
3157  }
3158  if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
3159  {
3160  fired |= ADI_RTC_TRIM_INT;
3161  }
3162  if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
3163  {
3164  fired |= ADI_RTC_PSI_INT;
3165  }
3166  if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
3167  {
3168  fired |= ADI_RTC_COUNT_INT;
3169  }
3170  }
3171 
3172  /* CR3OC, CR2IC SR3*/
3173  enables = pDevice->pRTCRegs->CR3SS & (uint32_t)ADI_RTC_INT_ENA_MASK_CR3SS;
3174  nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_IRQ_SOURCE_MASK_SR3;
3175  if( nIntSrc3 && enables )
3176  {
3177 #if defined(__ADUCM4x50__)
3178  if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
3179  {
3181  }
3182  if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
3183  {
3185  }
3186  if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
3187  {
3189  }
3190 #endif /* __ADUCM4x50__ */
3191  if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
3192  {
3194  }
3195 #if defined(__ADUCM4x50__)
3196  if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
3197  {
3198  fired |= ADI_RTC_RTCSS4_FE_INT;
3199  }
3200  if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
3201  {
3202  fired |= ADI_RTC_RTCSS3_FE_INT;
3203  }
3204  if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
3205  {
3206  fired |= ADI_RTC_RTCSS2_FE_INT;
3207  }
3208  if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
3209  {
3210  fired |= ADI_RTC_RTCSS1_FE_INT;
3211  }
3212 #endif /* __ADUCM4x50__ */
3213  }
3214  enables = pDevice->pRTCRegs->CR2IC & (uint32_t)ADI_RTC_INT_ENA_MASK_CR2IC;
3215  if( nIntSrc3 && enables )
3216  {
3217  if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
3218  {
3220  }
3221  if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
3222  {
3224  }
3225  if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
3226  {
3228  }
3229  if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
3230  {
3232  }
3233  }
3234 
3235  if (pDevice->pfCallback != NULL) {
3236 
3237  /* forward to the user if he is watching this interrupt */
3238  /* pass the "fired" value as the event. argument param is not used */
3239  if ( fired)
3240  {
3241  pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
3242  }
3243  }
3244 
3245  /* Write 1 to clear the interrupts */
3246  pDevice->pRTCRegs->SR0 |= nIntSrc0;
3247  pDevice->pRTCRegs->SR2 |= nIntSrc2;
3248  pDevice->pRTCRegs->SR3 |= nIntSrc3;
3249 
3250  ISR_EPILOG();
3251 }
3252 
3253 #ifndef ADI_TIME_WA_21000023
3254 
3255 /* set this value to non-0 to time snapshots */
3256 #define ADI_TIME_WA_21000023 (0)
3257 
3258 #endif
3259 
3260 /* variable storing the number of cycles needed to read snapshots */
3261 uint32_t cycleCountId_WA_21000023 = 0u;
3262 
3263 #if defined(ADUCM4050_SI_REV) && (ADUCM4050_SI_REV==0) && (WA_21000023!=0)
3264 
3265 /* number of snapshots to take for WA 21000023 */
3266 #define ADI_WA_21000023_SAMPLES_NUMBER (3u)
3267 
3268 #define ADI_RTC_PRESCALE_POS (5u)
3269 
3270 /* bits 8-5 in RTC_CR1 */
3271 #define ADI_RTC_PRESCALE_MSK (0x01E0u)
3272 
3273 
3274 /* Get coherent values for the three RTC counters: COUNT0, COUNT1, COUNT2
3275  * Read the current 47-bit RTC count value and write it to the address provided
3276  * by parameter pCount.
3277  *
3278  * This version implements a software work around for anomaly 21000026.
3279  * Multiple snapshots are taken and a valid value is selected. If no values
3280  * can be marked as valid, the counter value reads the last value read and
3281  * return ADI_RTC_FAILURE.
3282  *
3283  * This version is should be used with ADuCM4x50 silicon revision 0.0.
3284  * It can be used with any ADuCM302xand any ADuCM4x50 though.
3285  *
3286  * WARNING: Using SNAPn registers means this version is unsafe to use with RTC1
3287  * Input Capture channel 0 as it's not possible to share the SNAPn
3288  * registers without taking the risk of overwriting the snap shots
3289  * values or use snap shots taken earlier.
3290  */
3291 static ADI_RTC_RESULT adi_rtc_GetCoherentCounterValues(ADI_RTC_HANDLE const hDevice, struct adi_rtc_snapshots *pSnapshots)
3292 {
3293  ADI_RTC_RESULT eResult = ADI_RTC_SUCCESS;
3294 #if (0!=ADI_TIME_WA_21000023)
3295  uint32_t cycStart; /* cycle count value before snapshots */
3296  uint32_t cycEnd; /* cycle count value after snapshots */
3297 #endif
3298 
3299  /* snapshots samples */
3300  struct adi_rtc_snapshots snapshots[ADI_WA_21000023_SAMPLES_NUMBER];
3301  uint64_t samples[ADI_WA_21000023_SAMPLES_NUMBER]; /* 64-bit samples */
3302  uint16_t rtc_cr1; /* used to access RTC register CR1 */
3303  uint64_t prescale = 0u; /* RTC_CR1.PRESCALE as 64-bit (use 0 for RTC0) */
3304  uint64_t mask; /* to clear invalid bits from COUNT2, as 64-bit */
3305  size_t i;
3306  size_t selectedSample = 2u; /* selected sample is the most recent one by default */
3307  ADI_RTC_DEVICE *pDevice = hDevice;
3308 
3309 #ifdef ADI_DEBUG
3310  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
3311  {
3312  return eResult;
3313  }
3314 #endif
3315 
3316  /* Wait till previously posted write to count Register to complete */
3317  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
3318 
3319  /* disable interrupts when reading RTC counter registers */
3320  ADI_INT_STATUS_ALLOC();
3321  ADI_ENTER_CRITICAL_REGION();
3322 
3323 #if (0!=ADI_TIME_WA_21000023)
3324  cycStart = DWT->CYCCNT;
3325 #endif
3326 
3327  /* Take a snapshot using the RTC_SNAPSHOT_KEY command and then
3328  * - read RTC_CNT0 snapshot value,
3329  * - read RTC_CNT1 snapshot value and
3330  * - read RTC_CNT2 snapshot value
3331  */
3332  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3333  snapshots[0].snapshot0 = pDevice->pRTCRegs->SNAP0;
3334  snapshots[0].snapshot1 = pDevice->pRTCRegs->SNAP1;
3335  snapshots[0].snapshot2 = pDevice->pRTCRegs->SNAP2;
3336 
3337  /* Take a snapshot using the RTC_SNAPSHOT_KEY command and then
3338  * - read RTC_CNT0 snapshot value,
3339  * - read RTC_CNT1 snapshot value and
3340  * - read RTC_CNT2 snapshot value
3341  */
3342  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3343  snapshots[1].snapshot0 = pDevice->pRTCRegs->SNAP0;
3344  snapshots[1].snapshot1 = pDevice->pRTCRegs->SNAP1;
3345  snapshots[1].snapshot2 = pDevice->pRTCRegs->SNAP2;
3346 
3347  /* Take a snapshot using the RTC_SNAPSHOT_KEY command and then
3348  * - read RTC_CNT0 snapshot value,
3349  * - read RTC_CNT1 snapshot value and
3350  * - read RTC_CNT2 snapshot value
3351  */
3352  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3353  snapshots[2].snapshot0 = pDevice->pRTCRegs->SNAP0;
3354  snapshots[2].snapshot1 = pDevice->pRTCRegs->SNAP1;
3355  snapshots[2].snapshot2 = pDevice->pRTCRegs->SNAP2;
3356 
3357 #if (0!=ADI_TIME_WA_21000023)
3358  cycEnd = DWT->CYCCNT;
3359 #endif
3360 
3361  /* read RTC_CR1 register */
3362  rtc_cr1 = pDevice->pRTCRegs->CR1;
3363 
3364  /* enable interrupts */
3365  ADI_EXIT_CRITICAL_REGION();
3366 
3367 
3368  /* If RTC is
3369  *
3370  * - RTC0
3371  * Keep prescale value to 0 as COUNT2/SNAP2 are to be ignored.
3372  *
3373  * - RTC1
3374  * Extract the prescale information from RTC_CR1:
3375  * this defines the number of valid bits in COUNT2 (between 0 and 15)
3376  */
3377  if (aRTCDeviceInfo[0].pRTCRegs != pDevice->pRTCRegs)
3378  {
3379  /* RTC1: get the prescale value, CR1 is a 16-bit register, prescale a 64-bit value */
3380  prescale = (rtc_cr1 & ADI_RTC_PRESCALE_MSK) >> ADI_RTC_PRESCALE_POS;
3381  }
3382  // prescale and mask are 64bit value: shift and subtraction must be 64-bit operations
3383  mask = (1llu << prescale) - 1llu;
3384 
3385 
3386  /* Create formatted counter values, between 32-bit and 47-bit long,
3387  * and store them in 64-bit data.
3388  */
3389  for (i=0u; i<ADI_WA_21000023_SAMPLES_NUMBER; i++)
3390  {
3391  samples[i] = ( ( (((uint64_t) snapshots[i].snapshot1) << (uint64_t) 16u)
3392  | ((uint64_t) snapshots[i].snapshot0)
3393  ) << prescale
3394  )
3395  | (((uint64_t) snapshots[i].snapshot2) & mask)
3396  ;
3397  }
3398 
3399 
3400  /* A sample is valid if
3401  * - it's equal to one of its previous samples, or
3402  * - it's equal to one of its previous samples plus one.
3403  *
3404  * If samples[2] is valid then use snapshots[2]
3405  * else if samples[1] is valid then use snapshots[1]
3406  * else there are no valid samples: use snapshots[2]
3407  * and return an error code
3408  */
3409  if ( (! ((samples[2] == samples[1]) || (samples[2] == (samples[1] + 1llu))))
3410  && (! ((samples[2] == samples[0]) || (samples[2] == (samples[0] + 1llu))))
3411  )
3412  {
3413  /* sample[2] is not valid */
3414 
3415  if ((samples[1] == samples[0]) || (samples[1] == (samples[0] + 1llu)))
3416  {
3417  /* sample[1] is valid */
3418  selectedSample = 1u; /* map snapshots to snapshots[1]*/
3419  }
3420  else
3421  {
3422  /* there are no valid samples!!!
3423  * The most recent value will be used by default.
3424  */
3425  eResult = ADI_RTC_FAILURE;
3426  }
3427  }
3428 
3429 #if (0!=ADI_TIME_WA_21000023)
3430 
3431  /* If timing the access to snapshots is required, use the two cycle number
3432  * to create a number of cycles needed to execute the accesses.
3433  * The implementation take into account cases when cycEnd overflows.
3434  * (Time to execute these accesses is too small to get cycEnd overflowing
3435  * more than once.)
3436  */
3437  if (cycStart < cycEnd)
3438  {
3439  cycleCountId_WA_21000023 = cycEnd - cycStart;
3440  }
3441  else
3442  {
3443  cycleCountId_WA_21000023 = 0xFFFFFFFFu - cycStart + cycEnd;
3444  }
3445 
3446 #endif
3447 
3448  /* use the selected sample as the RTC counter value to return */
3449  *pSnapshots = snapshots[selectedSample];
3450 
3451  return eResult;
3452 }
3453 
3454 
3455 #else /* defined(ADUCM4050_SI_REV) && (ADUCM4050_SI_REV==0) && (WA_21000023!=0) */
3456 
3457 /* Get coherent values for the three RTC counters: COUNT0, COUNT1, COUNT2
3458  * Read the current 47-bit RTC count value and write it to the address provided
3459  * by parameter pCount.
3460  *
3461  * This version doesn't implements a software work around for anomaly 21000026.
3462  * It's aimed at any ADuCM302x silicon revision and ADuCM4x50 silicon revision
3463  * 0.1 and beyond. For ADuCM4x50 silicon revision 0.0, it is recommended to use
3464  * the version with a work around.
3465  */
3466 static ADI_RTC_RESULT adi_rtc_GetCoherentCounterValues(ADI_RTC_HANDLE const hDevice, struct adi_rtc_snapshots *pSnapshots)
3467 {
3468  ADI_RTC_DEVICE *pDevice = hDevice;
3469  struct adi_rtc_snapshots snapshots;
3470 #if (0!=ADI_TIME_WA_21000023)
3471  uint32_t cycStart; /* cycle count value before snapshots */
3472  uint32_t cycEnd; /* cycle count value after snapshots */
3473 #endif
3474 
3475 #ifdef ADI_DEBUG
3476  ADI_RTC_RESULT eResult;
3477 
3478  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
3479  {
3480  return eResult;
3481  }
3482 #endif
3483 
3484  /* Wait till previously posted write to count Register to complete */
3485  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
3486 
3487  /* disable interrupts when reading RTC snapshots registers */
3488  ADI_INT_STATUS_ALLOC();
3489  ADI_ENTER_CRITICAL_REGION();
3490 
3491 #if (0!=ADI_TIME_WA_21000023)
3492  cycStart = DWT->CYCCNT;
3493 #endif
3494 
3495  /* get a snaphsot of RTC_CNTn registers, then
3496  * - read RTC_CNT0 snapshot value,
3497  * - read RTC_CNT1 snapshot value and
3498  * - read RTC_CNT2 snapshot value
3499  */
3500  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3501  snapshots.snapshot0 = pDevice->pRTCRegs->SNAP0;
3502  snapshots.snapshot1 = pDevice->pRTCRegs->SNAP1;
3503  snapshots.snapshot2 = pDevice->pRTCRegs->SNAP2;
3504 
3505 #if (0!=ADI_TIME_WA_21000023)
3506  cycEnd = DWT->CYCCNT;
3507 #endif
3508 
3509  /* enable interrupts */
3510  ADI_EXIT_CRITICAL_REGION();
3511 
3512 #if (0!=ADI_TIME_WA_21000023)
3513 
3514  /* If timing the access to snapshots is required, use the two cycle numbers
3515  * to create a number of cycles needed to execute the accesses.
3516  * The implementation take into account cases when cycEnd overflows.
3517  * (Time to execute these accesses is too small to get cycEnd overflowing
3518  * more than once.)
3519  */
3520  if (cycStart < cycEnd)
3521  {
3522  cycleCountId_WA_21000023 = cycEnd - cycStart;
3523  }
3524  else
3525  {
3526  cycleCountId_WA_21000023 = 0xFFFFFFFFu - cycStart + cycEnd;
3527  }
3528 
3529 #endif
3530 
3531  *pSnapshots = snapshots;
3532 
3533  return ADI_RTC_SUCCESS;
3534 }
3535 
3536 #endif /* defined(ADUCM4050_SI_REV) && (ADUCM4050_SI_REV==0) && (WA_21000023!=0) */
3537 
3540 /* @} */
#define ADI_RTC_SENSOR_STROBE_CH4_INT
Definition: adi_rtc.h:134
#define ADI_RTC_RTCSS2_FE_INT
Definition: adi_rtc.h:124
ADI_RTC_RESULT adi_rtc_ClearInterruptStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Status)
Clear an RTC interrupt status bit(s).
Definition: adi_rtc.c:1629
#define ADI_RTC_INPUT_CAPTURE_CH4_INT
Definition: adi_rtc.h:117
ADI_RTC_RESULT adi_rtc_GetInputCaptureValueEx(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pSnap0, uint16_t *pSnap1, uint16_t *pSnap2)
Get input capture value for specified input channel.
Definition: adi_rtc.c:1901
#define ADI_RTC_RTCSS3_FE_INT
Definition: adi_rtc.h:123
#define ADI_RTC_WRITE_PEND_INT
Definition: adi_rtc.h:107
ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount)
Get current RTC count value.
Definition: adi_rtc.c:1430
#define ADI_RTC_SENSOR_STROBE_CH1_INT
Definition: adi_rtc.h:113
ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue)
Set Sensor Strobe value for the given Sensor Strobe channel.
Definition: adi_rtc.c:1820
ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command)
Set an RTC gateway command.
Definition: adi_rtc.c:2777
#define ADI_RTC_IRQ_SOURCE_MASK_SR0
Definition: adi_rtc.h:46
ADI_RTC_RESULT adi_rtc_Close(ADI_RTC_HANDLE const hDevice)
Uninitialize and deallocate an RTC device.
Definition: adi_rtc.c:385
#define ADI_RTC_IRQ_SOURCE_OFFSET_SR2
Definition: adi_rtc.h:49
#define ADI_RTC_SENSOR_STROBE_CH3_INT
Definition: adi_rtc.h:133
#define ADI_RTC_IRQ_SOURCE_OFFSET_SR3
Definition: adi_rtc.h:57
ADI_RTC_RESULT adi_rtc_SetAlarm(ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
Set a new RTC alarm value.
Definition: adi_rtc.c:2213
#define ADI_RTC_RTCSS4_FE_INT
Definition: adi_rtc.h:122
ADI_RTC_RESULT adi_rtc_GetTrim(ADI_RTC_HANDLE hDevice, ADI_RTC_TRIM_VALUE *peTrim)
Get current RTC clock trim value.
Definition: adi_rtc.c:1721
uint32_t ADI_RTC_INT_TYPE
Definition: adi_rtc.h:100
ADI_RTC_RESULT adi_rtc_GetInterruptStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE *pStatus)
Get current RTC interrupt source status.
Definition: adi_rtc.c:1563
#define ADI_RTC_ISO_DONE_INT
Definition: adi_rtc.h:104
ADI_RTC_RESULT adi_rtc_SetAlarmRegsAsync(ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0, uint16_t nAlarm1, uint16_t nAlarm2)
Set a new RTC alarm value for RTC ALM0, ALM1 and ALM2 Registers without waiting for synchronization.
Definition: adi_rtc.c:2371
ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites(ADI_RTC_HANDLE const hDevice)
Force synchronization of all pending writes.
Definition: adi_rtc.c:2867
void * ADI_RTC_HANDLE
Definition: adi_rtc.h:40
ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pValue)
Get input capture value for specified input channel.
Definition: adi_rtc.c:1961
#define ADI_RTC_INPUT_CAPTURE_CH0_INT
Definition: adi_rtc.h:114
#define ADI_RTC0_IRQ_SOURCE_MASK_SR2
Definition: adi_rtc.h:52
#define ADI_RTC_SENSOR_STROBE_CH2_INT
Definition: adi_rtc.h:132
#define ADI_RTC_ALARM_INT
Definition: adi_rtc.h:102
ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t *pValue)
Get Sensor Strobe value for the given Sensor Strobe channel.
Definition: adi_rtc.c:1760
ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount)
Get current RTC count value of all registers.
Definition: adi_rtc.c:1510
ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pSyncBits)
Get current RTC posted write synchronization status.
Definition: adi_rtc.c:2135
ADI_RTC_RESULT adi_rtc_SyncAlarm(ADI_RTC_HANDLE const hDevice)
Sync after writing RTC alarm registers.
Definition: adi_rtc.c:2419
ADI_RTC_RESULT adi_rtc_SetTrim(ADI_RTC_HANDLE const hDevice, ADI_RTC_TRIM_INTERVAL eInterval, ADI_RTC_TRIM_VALUE eTrimValue, ADI_RTC_TRIM_POLARITY eOperation)
Set a new RTC trim value.
Definition: adi_rtc.c:2819
ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount)
Get current RTC count value with fraction.
Definition: adi_rtc.c:1466
ADI_RTC_RESULT adi_rtc_Open(uint32_t DeviceNumber, void *pDeviceMemory, uint32_t MemorySize, ADI_RTC_HANDLE *phDevice)
RTC Initialization.
Definition: adi_rtc.c:266
#define ADI_RTC_INPUT_CAPTURE_CH2_INT
Definition: adi_rtc.h:115
ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nLowValue, uint16_t nHighValue)
Set auto reload value for the given Sensor Strobe channel.
Definition: adi_rtc.c:1062
#define ADI_RTC_IRQ_SOURCE_MASK_SR3
Definition: adi_rtc.h:63
ADI_RTC_WRITE_STATUS
Definition: adi_rtc.h:147
ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const hDevice, uint8_t nPreScale)
Set Prescale. This is power of 2 division factor for the RTC base clock.
Definition: adi_rtc.c:2455
#define ADI_RTC1_IRQ_SOURCE_MASK_SR2
Definition: adi_rtc.h:54
ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable MOD60 RTC alarm.
Definition: adi_rtc.c:510
#define ADI_RTC_MOD60ALM_INT
Definition: adi_rtc.h:103
ADI_RTC_RESULT adi_rtc_GetAlarmEx(ADI_RTC_HANDLE hDevice, float *pAlarm)
Get current RTC alarm value with fractional part also.
Definition: adi_rtc.c:1290
ADI_RTC_RESULT adi_rtc_EnableTrim(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable RTC automatic clock trimming.
Definition: adi_rtc.c:731
#define ADI_RTC_COUNT_INT
Definition: adi_rtc.h:108
ADI_RTC_RESULT adi_rtc_GetAlarmRegs(ADI_RTC_HANDLE hDevice, uint16_t *pAlarm0, uint16_t *pAlarm1, uint16_t *pAlarm2)
Get current RTC alarm value from RTC Alarm register.
Definition: adi_rtc.c:1338
ADI_RTC_RESULT adi_rtc_RegisterCallback(ADI_RTC_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBparam)
Registers a Callback function with the RTC device driver. The registered call back function will be c...
Definition: adi_rtc.c:2667
ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
Set input capture polarity for the specified channel.
Definition: adi_rtc.c:870
#define ADI_RTC_INPUT_CAPTURE_CH3_INT
Definition: adi_rtc.h:116
#define ADI_RTC_NUM_INTERRUPTS
Definition: adi_rtc.h:138
ADI_RTC_RESULT adi_rtc_SetAlarmAsync(ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
Set a new RTC alarm value without waiting for synchronization.
Definition: adi_rtc.c:2321
ADI_RTC_RESULT adi_rtc_GetControl(ADI_RTC_HANDLE hDevice, ADI_RTC_CONTROL_REGISTER eRegister, uint32_t *pControl)
Get current RTC control register value.
Definition: adi_rtc.c:1382
#define ADI_RTC_IRQ_SOURCE_OFFSET_SR0
Definition: adi_rtc.h:43
#define ADI_RTC_WRITE_PENDERR_INT
Definition: adi_rtc.h:105
ADI_RTC_RESULT adi_rtc_EnableInputCapture(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
Enable input capture for the specified channel.
Definition: adi_rtc.c:777
ADI_RTC_RESULT adi_rtc_SetAlarmEx(ADI_RTC_HANDLE const hDevice, float fAlarm)
Set a new RTC alarm value with fractional value.
Definition: adi_rtc.c:2558
#define ADI_RTC_MOD60_ROLLOVER_INT
Definition: adi_rtc.h:112
ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable RTC device.
Definition: adi_rtc.c:572
ADI_RTC_RESULT adi_rtc_EnableAlarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable RTC alarm.
Definition: adi_rtc.c:447
ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint8_t nMask)
To set channel mask for the given Sensor Strobe channel.
Definition: adi_rtc.c:1179
ADI_RTC_RESULT adi_rtc_SetControlRegister(ADI_RTC_HANDLE const hDevice, ADI_RTC_CONTROL_REGISTER eRegister, uint32_t Control)
Set a new RTC control register value.
Definition: adi_rtc.c:2619
#define ADI_RTC_COUNT_ROLLOVER_INT
Definition: adi_rtc.h:111
ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction)
Read RTC snapshot registers values.
Definition: adi_rtc.c:2011
ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
Enable output for the specified Sensor Strobe Channel.
Definition: adi_rtc.c:917
ADI_RTC_TRIM_INTERVAL
Definition: adi_rtc.h:169
#define ADI_RTC_RTCSS1_FE_INT
Definition: adi_rtc.h:125
ADI_RTC_RESULT adi_rtc_EnableAutoReload(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
Enable auto reload for given Sensor Strobe Channel.
Definition: adi_rtc.c:964
ADI_RTC_RESULT adi_rtc_GetAlarm(ADI_RTC_HANDLE hDevice, uint32_t *pAlarm)
Get current RTC alarm value.
Definition: adi_rtc.c:1249
#define ADI_RTC_TRIM_INT
Definition: adi_rtc.h:110
ADI_RTC_RESULT
Definition: adi_rtc.h:69
ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
Enable or disable thermometer-code masking for the given Sensor Strobe Channel.
Definition: adi_rtc.c:1134
#define ADI_RTC_PSI_INT
Definition: adi_rtc.h:109
#define ADI_RTC_MEMORY_SIZE
Definition: adi_rtc.h:34
ADI_RTC_RESULT adi_rtc_GetWritePendStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pPendBits)
Get current RTC posted write pending status.
Definition: adi_rtc.c:2076
ADI_RTC_INPUT_CHANNEL
Definition: adi_rtc.h:209
ADI_RTC_TRIM_VALUE
Definition: adi_rtc.h:253
ADI_RTC_RESULT adi_rtc_GetISOENB(ADI_RTC_HANDLE const hDevice, uint16_t *pValue)
Get the value of the ISOENB bit.
Definition: adi_rtc.c:2168
ADI_RTC_RESULT adi_rtc_SetCount(ADI_RTC_HANDLE const hDevice, uint32_t nCount)
Set a new RTC count value.
Definition: adi_rtc.c:2719
ADI_RTC_TRIM_POLARITY
Definition: adi_rtc.h:242
ADI_RTC_SS_CHANNEL
Definition: adi_rtc.h:225
ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(ADI_RTC_HANDLE const hDevice, uint8_t nPeriod)
Set the modulo-60 alarm value. This positions a periodic (repeating) alarm interrupt from the RTC at ...
Definition: adi_rtc.c:2502
ADI_RTC_CONTROL_REGISTER
Definition: adi_rtc.h:276
ADI_RTC_RESULT adi_rtc_SetAlarmRegs(ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0, uint16_t nAlarm1, uint16_t nAlarm2)
Set a new RTC alarm value for RTC ALM0,ALM1 and ALM2 Register.
Definition: adi_rtc.c:2265
ADI_RTC_RESULT adi_rtc_EnableInterrupts(ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Interrupts, bool bEnable)
Manage interrupt enable/disable in the RTC and NVIC controller.
Definition: adi_rtc.c:632
#define ADI_RTC_WRITE_SYNC_INT
Definition: adi_rtc.h:106
ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels.
Definition: adi_rtc.c:823