ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_tmr_config.h
1 
13 #ifndef ADI_TMR_CONFIG_H
14 #define ADI_TMR_CONFIG_H
15 
16 #include <adi_processor.h>
17 #include <adi_global_config.h>
18 
24 /*************************************************************
25  GP Timer 0 Configuration
26  *************************************************************/
27 
39 #define TMR0_CFG_COUNT_UP (0u)
40 
46 #define TMR0_CFG_MODE (1u)
47 
56 #define TMR0_CFG_PRESCALE_FACTOR (0u)
57 
65 #define TMR0_CFG_CLOCK_SOURCE (0u)
66 
72 #define TMR0_CFG_LOAD_VALUE (0x8F9Cu)
73 
80 #define TMR0_CFG_ASYNC_LOAD_VALUE (0x8F9Cu)
81 
87 #define TMR0_CFG_ENABLE_RELOADING (0u)
88 
93 #define TMR0_CFG_ENABLE_SYNC_BYPASS (0u)
94 
95 /*************************************************************
96  GP Timer 0 Event Configuration
97  *************************************************************/
98 
103 #define TMR0_CFG_ENABLE_EVENT_CAPTURE (1u)
104 
109 #define TMR0_CFG_ENABLE_PRESCALE_RESET (0u)
110 
116 #if defined(__ADUCM302x__)
117 #define TMR0_CFG_EVENT_CAPTURE (9u)
118 #elif defined(__ADUCM4x50__)
119 #define TMR0_CFG_EVENT_CAPTURE (27u)
120 #else
121 #error TMR is not ported for this processor
122 #endif
123 
124 /*************************************************************
125  GP Timer 0 PWM0 Configuration
126  *************************************************************/
127 
134 #define TMR0_CFG_ENABLE_PWM0_MATCH_MODE (1u)
135 
136 
141 #define TMR0_CFG_PWM0_IDLE_STATE (1u)
142 
143 
150 #define TMR0_CFG_PWM0_MATCH_VALUE (0x0E5Cu)
151 
155 /*************************************************************
156  GP Timer 1 Configuration
157  *************************************************************/
158 
170 #define TMR1_CFG_COUNT_UP (0u)
171 
177 #define TMR1_CFG_MODE (1u)
178 
187 #define TMR1_CFG_PRESCALE_FACTOR (0u)
188 
196 #define TMR1_CFG_CLOCK_SOURCE (0u)
197 
203 #define TMR1_CFG_LOAD_VALUE (0x23E7u)
204 
211 #define TMR1_CFG_ASYNC_LOAD_VALUE (0x23E7u)
212 
218 #define TMR1_CFG_ENABLE_RELOADING (0u)
219 
224 #define TMR1_CFG_ENABLE_SYNC_BYPASS (0u)
225 
226 
227 /*************************************************************
228  GP Timer 1 Event Configuration
229  *************************************************************/
230 
235 #define TMR1_CFG_ENABLE_EVENT_CAPTURE (1u)
236 
241 #define TMR1_CFG_ENABLE_PRESCALE_RESET (0u)
242 
248 #if defined(__ADUCM302x__)
249 #define TMR1_CFG_EVENT_CAPTURE (15u)
250 #elif defined(__ADUCM4x50__)
251 #define TMR1_CFG_EVENT_CAPTURE (28u)
252 #else
253 #error TMR is not ported for this processor
254 #endif
255 /*************************************************************
256  GP Timer 1 PWM0 Configuration
257  *************************************************************/
258 
265 #define TMR1_CFG_ENABLE_PWM0_MATCH_MODE (1u)
266 
267 
272 #define TMR1_CFG_PWM0_IDLE_STATE (1u)
273 
274 
281 #define TMR1_CFG_PWM0_MATCH_VALUE (0x08F9u)
282 
285 /*************************************************************
286  GP Timer 2 Configuration
287  *************************************************************/
288 
300 #define TMR2_CFG_COUNT_UP (0u)
301 
307 #define TMR2_CFG_MODE (1u)
308 
317 #define TMR2_CFG_PRESCALE_FACTOR (0u)
318 
326 #define TMR2_CFG_CLOCK_SOURCE (0u)
327 
333 #define TMR2_CFG_LOAD_VALUE (0x0E5Cu)
334 
341 #define TMR2_CFG_ASYNC_LOAD_VALUE (0x0E5Cu)
342 
348 #define TMR2_CFG_ENABLE_RELOADING (0u)
349 
354 #define TMR2_CFG_ENABLE_SYNC_BYPASS (0u)
355 
356 /*************************************************************
357  GP Timer 2 Event Configuration
358  *************************************************************/
359 
364 #define TMR2_CFG_ENABLE_EVENT_CAPTURE (1u)
365 
370 #define TMR2_CFG_ENABLE_PRESCALE_RESET (0u)
371 
377 #if defined(__ADUCM302x__)
378 #define TMR2_CFG_EVENT_CAPTURE (6u)
379 #elif defined(__ADUCM4x50__)
380 #define TMR2_CFG_EVENT_CAPTURE (27u)
381 #else
382 #error TMR is not ported for this processor
383 #endif
384 /*************************************************************
385  GP Timer 2 PWM0 Configuration
386  *************************************************************/
387 
394 #define TMR2_CFG_ENABLE_PWM0_MATCH_MODE (1u)
395 
396 
401 #define TMR2_CFG_PWM0_IDLE_STATE (1u)
402 
403 
410 #define TMR2_CFG_PWM0_MATCH_VALUE (0x02DFu)
411 
414 #if defined(__ADUCM4x50__)
415 /*************************************************************
416  RGB Timer Configuration
417  *************************************************************/
418 
430 #define TMR3_CFG_COUNT_UP (0u)
431 
437 #define TMR3_CFG_MODE (1u)
438 
447 #define TMR3_CFG_PRESCALE_FACTOR (0u)
448 
456 #define TMR3_CFG_CLOCK_SOURCE (0u)
457 
463 #define TMR3_CFG_LOAD_VALUE (0x47CEu)
464 
471 #define TMR3_CFG_ASYNC_LOAD_VALUE (0x47CEu)
472 
478 #define TMR3_CFG_ENABLE_RELOADING (0u)
479 
484 #define TMR3_CFG_ENABLE_SYNC_BYPASS (0u)
485 
486 /*************************************************************
487  RGB Timer Event Configuration
488  *************************************************************/
489 
494 #define TMR3_CFG_ENABLE_EVENT_CAPTURE (1u)
495 
500 #define TMR3_CFG_ENABLE_PRESCALE_RESET (0u)
501 
507 #define TMR3_CFG_EVENT_CAPTURE (28u)
508 
509 /*************************************************************
510  RGB Timer PWM0 Configuration
511  *************************************************************/
512 
519 #define TMR3_CFG_ENABLE_PWM0_MATCH_MODE (1u)
520 
521 
526 #define TMR3_CFG_PWM0_IDLE_STATE (1u)
527 
528 
535 #define TMR3_CFG_PWM0_MATCH_VALUE (0x23E7u)
536 
537 /*************************************************************
538  RGB Timer PWM1 Configuration
539  *************************************************************/
540 
547 #define TMR3_CFG_ENABLE_PWM1_MATCH_MODE (0u)
548 
549 
554 #define TMR3_CFG_PWM1_IDLE_STATE (0u)
555 
556 
563 #define TMR3_CFG_PWM1_MATCH_VALUE (0u)
564 
565 /*************************************************************
566  RGB Timer PWM2 Configuration
567  *************************************************************/
568 
575 #define TMR3_CFG_ENABLE_PWM2_MATCH_MODE (0u)
576 
577 
582 #define TMR3_CFG_PWM2_IDLE_STATE (0u)
583 
584 
591 #define TMR3_CFG_PWM2_MATCH_VALUE (0u)
592 
594 #endif
595 
596 /*************************************************************
597  GP Timer 0 Macro Validation
598 **************************************************************/
599 
600 #if TMR0_CFG_COUNT_UP > 1u
601 #error "Invalid configuration"
602 #endif
603 
604 #if TMR0_CFG_MODE > 1u
605 #error "Invalid configuration"
606 #endif
607 
608 #if TMR0_CFG_PRESCALE_FACTOR > 3u
609 #error "Invalid configuration"
610 #endif
611 
612 #if TMR0_CFG_CLOCK_SOURCE > 3u
613 #error "Invalid configuration"
614 #endif
615 
616 #if TMR0_CFG_LOAD_VALUE > 0xFFFFu
617 #error "Invalid configuration"
618 #endif
619 
620 #if TMR0_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
621 #error "Invalid configuration"
622 #endif
623 
624 #if TMR0_CFG_ENABLE_RELOADING > 1u
625 #error "Invalid configuration"
626 #endif
627 
628 #if TMR0_CFG_ENABLE_SYNC_BYPASS > 1u
629 #error "Invalid configuration"
630 #endif
631 
632 #if TMR0_CFG_ENABLE_PRESCALE_RESET > 1u
633 #error "Invalid configuration"
634 #endif
635 
636 #if TMR0_CFG_ENABLE_EVENT_CAPTURE > 1u
637 #error "Invalid configuration"
638 #endif
639 
640 #if defined(__ADUCM302x__)
641 #if TMR0_CFG_EVENT_CAPTURE > 15u
642 #error "Invalid configuration"
643 #endif
644 #elif defined(__ADUCM4x50__)
645 #if TMR0_CFG_EVENT_CAPTURE > 39u
646 #error "Invalid configuration"
647 #endif
648 #else
649 #error TMR is not ported for this processor
650 #endif
651 
652 #if TMR0_CFG_ENABLE_PWM0_MATCH_MODE > 1u
653 #error "Invalid configuration"
654 #endif
655 
656 #if TMR0_CFG_PWM0_IDLE_STATE > 1u
657 #error "Invalid configuration"
658 #endif
659 
660 #if TMR0_CFG_PWM0_MATCH_VALUE > 0xFFFFu
661 #error "Invalid configuration"
662 #endif
663 
664 /*************************************************************
665  GP Timer 1 Macro Validation
666 **************************************************************/
667 
668 #if TMR1_CFG_COUNT_UP > 1u
669 #error "Invalid configuration"
670 #endif
671 
672 #if TMR1_CFG_MODE > 1u
673 #error "Invalid configuration"
674 #endif
675 
676 #if TMR1_CFG_PRESCALE_FACTOR > 3u
677 #error "Invalid configuration"
678 #endif
679 
680 #if TMR1_CFG_CLOCK_SOURCE > 3u
681 #error "Invalid configuration"
682 #endif
683 
684 #if TMR1_CFG_LOAD_VALUE > 0xFFFFu
685 #error "Invalid configuration"
686 #endif
687 
688 #if TMR1_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
689 #error "Invalid configuration"
690 #endif
691 
692 #if TMR1_CFG_ENABLE_RELOADING > 1u
693 #error "Invalid configuration"
694 #endif
695 
696 #if TMR1_CFG_ENABLE_SYNC_BYPASS > 1u
697 #error "Invalid configuration"
698 #endif
699 
700 #if TMR1_CFG_ENABLE_PRESCALE_RESET > 1u
701 #error "Invalid configuration"
702 #endif
703 
704 #if TMR1_CFG_ENABLE_EVENT_CAPTURE > 1u
705 #error "Invalid configuration"
706 #endif
707 
708 #if defined(__ADUCM302x__)
709 #if TMR1_CFG_EVENT_CAPTURE > 15u
710 #error "Invalid configuration"
711 #endif
712 #elif defined(__ADUCM4x50__)
713 #if TMR1_CFG_EVENT_CAPTURE > 39u
714 #error "Invalid configuration"
715 #endif
716 #else
717 #error TMR is not ported for this processor
718 #endif
719 
720 #if TMR1_CFG_ENABLE_PWM0_MATCH_MODE > 1u
721 #error "Invalid configuration"
722 #endif
723 
724 #if TMR1_CFG_PWM0_IDLE_STATE > 1u
725 #error "Invalid configuration"
726 #endif
727 
728 #if TMR1_CFG_PWM0_MATCH_VALUE > 0xFFFFu
729 #error "Invalid configuration"
730 #endif
731 
732 /*************************************************************
733  GP Timer 2 Macro Validation
734 **************************************************************/
735 
736 #if TMR2_CFG_COUNT_UP > 1u
737 #error "Invalid configuration"
738 #endif
739 
740 #if TMR2_CFG_MODE > 1u
741 #error "Invalid configuration"
742 #endif
743 
744 #if TMR2_CFG_PRESCALE_FACTOR > 3u
745 #error "Invalid configuration"
746 #endif
747 
748 #if TMR2_CFG_CLOCK_SOURCE > 3u
749 #error "Invalid configuration"
750 #endif
751 
752 #if TMR2_CFG_LOAD_VALUE > 0xFFFFu
753 #error "Invalid configuration"
754 #endif
755 
756 #if TMR2_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
757 #error "Invalid configuration"
758 #endif
759 
760 #if TMR2_CFG_ENABLE_RELOADING > 1u
761 #error "Invalid configuration"
762 #endif
763 
764 #if TMR2_CFG_ENABLE_SYNC_BYPASS > 1u
765 #error "Invalid configuration"
766 #endif
767 
768 #if TMR2_CFG_ENABLE_PRESCALE_RESET > 1u
769 #error "Invalid configuration"
770 #endif
771 
772 #if TMR2_CFG_ENABLE_EVENT_CAPTURE > 1u
773 #error "Invalid configuration"
774 #endif
775 
776 #if defined(__ADUCM302x__)
777 #if TMR2_CFG_EVENT_CAPTURE > 15u
778 #error "Invalid configuration"
779 #endif
780 #elif defined(__ADUCM4x50__)
781 #if TMR2_CFG_EVENT_CAPTURE > 39u
782 #error "Invalid configuration"
783 #endif
784 #else
785 #error TMR is not ported for this processor
786 #endif
787 
788 #if TMR2_CFG_ENABLE_PWM0_MATCH_MODE > 1u
789 #error "Invalid configuration"
790 #endif
791 
792 #if TMR2_CFG_PWM0_IDLE_STATE > 1u
793 #error "Invalid configuration"
794 #endif
795 
796 #if TMR2_CFG_PWM0_MATCH_VALUE > 0xFFFFu
797 #error "Invalid configuration"
798 #endif
799 
800 #if defined(__ADUCM4x50__)
801 /*************************************************************
802  RGB Timer Macro Validation
803 **************************************************************/
804 #if TMR3_CFG_COUNT_UP > 1u
805 #error "Invalid configuration"
806 #endif
807 
808 #if TMR3_CFG_MODE > 1u
809 #error "Invalid configuration"
810 #endif
811 
812 #if TMR3_CFG_PRESCALE_FACTOR > 3u
813 #error "Invalid configuration"
814 #endif
815 
816 #if TMR3_CFG_CLOCK_SOURCE > 3u
817 #error "Invalid configuration"
818 #endif
819 
820 #if TMR3_CFG_LOAD_VALUE > 0xFFFFu
821 #error "Invalid configuration"
822 #endif
823 
824 #if TMR3_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
825 #error "Invalid configuration"
826 #endif
827 
828 #if TMR3_CFG_ENABLE_RELOADING > 1u
829 #error "Invalid configuration"
830 #endif
831 
832 #if TMR3_CFG_ENABLE_SYNC_BYPASS > 1u
833 #error "Invalid configuration"
834 #endif
835 
836 #if TMR3_CFG_ENABLE_PRESCALE_RESET > 1u
837 #error "Invalid configuration"
838 #endif
839 
840 #if TMR3_CFG_ENABLE_EVENT_CAPTURE > 1u
841 #error "Invalid configuration"
842 #endif
843 
844 #if TMR3_CFG_EVENT_CAPTURE > 39u
845 #error "Invalid configuration"
846 #endif
847 
848 #if TMR3_CFG_ENABLE_PWM0_MATCH_MODE > 1u
849 #error "Invalid configuration"
850 #endif
851 
852 #if TMR3_CFG_PWM0_IDLE_STATE > 1u
853 #error "Invalid configuration"
854 #endif
855 
856 #if TMR3_CFG_PWM0_MATCH_VALUE > 0xFFFFu
857 #error "Invalid configuration"
858 #endif
859 
860 #if TMR3_CFG_ENABLE_PWM1_MATCH_MODE > 1u
861 #error "Invalid configuration"
862 #endif
863 
864 #if TMR3_CFG_PWM1_IDLE_STATE > 1u
865 #error "Invalid configuration"
866 #endif
867 
868 #if TMR3_CFG_PWM1_MATCH_VALUE > 0xFFFFu
869 #error "Invalid configuration"
870 #endif
871 
872 #if TMR3_CFG_ENABLE_PWM2_MATCH_MODE > 1u
873 #error "Invalid configuration"
874 #endif
875 
876 #if TMR3_CFG_PWM2_IDLE_STATE > 1u
877 #error "Invalid configuration"
878 #endif
879 
880 #if TMR3_CFG_PWM2_MATCH_VALUE > 0xFFFFu
881 #error "Invalid configuration"
882 #endif
883 
884 #endif
885 
888 #endif /* ADI_TMR_CONFIG_H */