ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_rtc_config.h
1 
15 #ifndef ADI_RTC_CONFIG_H__
16 #define ADI_RTC_CONFIG_H__
17 #include <adi_global_config.h>
18 
30 #define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1
31 
32 
38 /*
39 ===================================================================
40  ------------------------RTC-0 CONFIGURATION MACRO-----------------
41 ===================================================================
42 */
44 #define RTC0_CFG_ENABLE_ALARM 0
45 
47 #define RTC0_CFG_ENABLE_ALARM_INTERRUPT 0
48 
50 #define RTC0_CFG_ENABLE_TRIM 0
51 
53 #define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT 0
54 
56 #define RTC0_CFG_ENABLE_WSYNC_INTERRUPT 0
57 
59 #define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT 0
60 
62 #define RTC0_CFG_COUNT_VALUE 0
63 
65 #define RTC0_CFG_COUNT_VALUE_0 0
66 
68 #define RTC0_CFG_COUNT_VALUE_1 0
69 
71 #define RTC0_CFG_ALARM_VALUE_0 0
72 
74 #define RTC0_CFG_ALARM_VALUE_1 0
75 
77 #define RTC0_CFG_TRIM_INTERVAL 0
78 
80 #define RTC0_CFG_POW2_TRIM_INTERVAL 0
81 
83 #define RTC0_CFG_TRIM_OPERATION 0
84 
86 #define RTC0_CFG_TRIM_VALUE 0
87 
96 #define RTC0_SS3_SMPONRE 0
97 
106 #define RTC0_SS3_SMPONFE 0
107 
108 #define RTC0_SS2_SMPONFE 0
109 
110 #define RTC0_SS1_SMPONRE 0
111 
112 #define RTC0_SS1_SMPONFE 0
113 
114 
121 #define RTC0_SS2_GPIN1SEL 0x4
122 
123 #define RTC0_SS2_GPIN0SEL 0x3
124 
125 #define RTC0_SS1_GPIN2SEL 0x2
126 
127 #define RTC0_SS1_GPIN1SEL 0x1
128 
129 #define RTC0_SS1_GPIN0SEL 0x0
130 
131 #define RTC0_SS3_GPIN2SEL 0x0
132 
133 #define RTC0_SS3_GPIN1SEL 0x7
134 
135 #define RTC0_SS3_GPIN0SEL 0x6
136 
137 #define RTC0_SS2_GPIN2SEL 0x5
138 
144 #define RTC0_SS3_DIFFOUT 0
145 
150 #define RTC0_SS1_DIFFOUT 0
151 
152 
153 
156 /*
157 ===================================================================
158  ------------------------RTC-1 CONFIGURATION MACRO-----------------
159 ===================================================================
160 */
161 
170 #define RTC1_CFG_ENABLE_ALARM 0
171 
173 #define RTC1_CFG_ENABLE_ALARM_INTERRUPT 0
174 
176 #define RTC1_CFG_ENABLE_TRIM 0
177 
179 #define RTC1_CFG_ENABLE_MOD60_ALARM 0
180 
182 #define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD 0
183 
185 #define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT 0
186 
188 #define RTC1_CFG_ENABLE_ISO_INTERRUPT 0
189 
191 #define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT 0
192 
194 #define RTC1_CFG_ENABLE_WSYNC_INTERRUPT 0
195 
197 #define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT 0
198 
200 #define RTC1_CFG_ENABLE_COUNT_INTERRUPT 0
201 
203 #define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT 0
204 
206 #define RTC1_CFG_ENABLE_TRIM_INTERRUPT 0
207 
209 #define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT 0
210 
212 #define RTC1_CFG_PRESCALE 0
213 
215 #define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT 0
216 
218 #define RTC1_CFG_COUNT_VALUE_0 0
219 
221 #define RTC1_CFG_COUNT_VALUE_1 0
222 
224 #define RTC1_CFG_ALARM_VALUE_0 0
225 
227 #define RTC1_CFG_ALARM_VALUE_1 0
228 
230 #define RTC1_CFG_ALARM_VALUE_2 0
231 
233 #define RTC1_CFG_TRIM_INTERVAL 0
234 
236 #define RTC1_CFG_POW2_TRIM_INTERVAL 0
237 
239 #define RTC1_CFG_TRIM_OPERATION 0
240 
242 #define RTC1_CFG_TRIM_VALUE 0
243 
245 #define RTC1_CFG_IC0_ENABLE 0
246 
248 #define RTC1_CFG_IC2_ENABLE 0
249 
251 #define RTC1_CFG_IC3_ENABLE 0
252 
254 #define RTC1_CFG_IC4_ENABLE 0
255 
257 #define RTC1_CFG_SS1_ENABLE 0
258 
259 #define RTC1_CFG_SS2_ENABLE 0
260 
261 #define RTC1_CFG_SS3_ENABLE 0
262 
263 #define RTC1_CFG_SS4_ENABLE 0
264 
266 #define RTC1_CFG_IC0_INT_ENABLE 0
267 
269 #define RTC1_CFG_IC2_INT_ENABLE 0
270 
272 #define RTC1_CFG_IC3_INT_ENABLE 0
273 
275 #define RTC1_CFG_IC4_INT_ENABLE 0
276 
278 #define RTC1_CFG_IC_OVER_WRITE_ENABLE 0
279 
281 #define RTC1_CFG_IC0_EDGE_POLARITY 0
282 
284 #define RTC1_CFG_IC2_EDGE_POLARITY 0
285 
287 #define RTC1_CFG_IC3_EDGE_POLARITY 0
288 
290 #define RTC1_CFG_IC4_EDGE_POLARITY 0
291 
293 #define RTC1_CFG_SS1_INT_ENABLE 0
294 
295 #define RTC1_CFG_SS2_INT_ENABLE 0
296 
297 #define RTC1_CFG_SS3_INT_ENABLE 0
298 
299 #define RTC1_CFG_SS4_INT_ENABLE 0
300 
302 #define RTC1_CFG_SS1_MASK_ENABLE 0
303 
304 #define RTC1_CFG_SS2_MASK_ENABLE 0
305 
306 #define RTC1_CFG_SS3_MASK_ENABLE 0
307 
308 #define RTC1_CFG_SS4_MASK_ENABLE 0
309 
311 #define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE 0
312 
313 #if defined(__ADUCM4x50__)
314 
315 #define RTC1_CFG_SS2_AUTO_RELOADING_ENABLE 0
316 
317 #define RTC1_CFG_SS3_AUTO_RELOADING_ENABLE 0
318 #endif
319 
321 #define RTC1_CFG_SS1_MASK_VALUE 0
322 
323 #if defined(__ADUCM4x50__)
324 
325 #define RTC1_CFG_SS2_MASK_VALUE 0
326 
327 #define RTC1_CFG_SS3_MASK_VALUE 0
328 
329 #define RTC1_CFG_SS4_MASK_VALUE 0
330 #endif
331 
332 #if defined(__ADUCM302x__)
333 
334 #define RTC1_CFG_SS1_AUTO_RELOAD_VALUE 32768/2
335 #endif
336 
338 #define RTC_CFG_SS1_VALUE 32768/2
339 
340 #if defined(__ADUCM4x50__)
341 
342 #define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH 32768/2
343 
344 #define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW 32768/2
345 
347 #define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH 32768/2
348 
349 #define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW 32768/2
350 
352 #define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH 32768/2
353 
354 #define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW 32768/2
355 #endif
356 
363 #define RTC1_SS2_GPIN1SEL 0x4
364 
365 #define RTC1_SS2_GPIN0SEL 0x3
366 
367 #define RTC1_SS1_GPIN2SEL 0x2
368 
369 #define RTC1_SS1_GPIN1SEL 0x1
370 
371 #define RTC1_SS1_GPIN0SEL 0x0
372 
373 #define RTC1_SS3_GPIN2SEL 0x0
374 
375 #define RTC1_SS3_GPIN1SEL 0x7
376 
377 #define RTC1_SS3_GPIN0SEL 0x6
378 
379 #define RTC1_SS2_GPIN2SEL 0x5
380 
386 #define RTC1_SS3_DIFFOUT 0
387 
392 #define RTC1_SS1_DIFFOUT 0
393 
395 #define RTC1_CFG_CR5SSS_OC1SMPEN 0
396 
398 #define RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN 0
399 
401 #define RTC1_CFG_CR5SSS_OC2SMPEN 0
402 
404 #define RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN 0
405 
407 #define RTC1_CFG_CR5SSS_OC3SMPEN 0
408 
410 #define RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN 0
411 
413 #define RTC1_CFG_CR6SSS_OC1SMPONFE 0
414 
416 #define RTC1_CFG_CR6SSS_OC1SMPONRE 0
417 
419 #define RTC1_CFG_CR6SSS_OC2SMPONFE 0
420 
422 #define RTC1_CFG_CR6SSS_OC2SMPONRE 0
423 
425 #define RTC1_CFG_CR6SSS_OC3SMPONFE 0
426 
428 #define RTC1_CFG_CR6SSS_OC3SMPONRE 0
429 
431 #define RTC1_CFG_CR7SSS_OC1SMPEXP 0
432 
434 #define RTC1_CFG_CR7SSS_OC1SMPPTRN 0
435 
437 #define RTC1_CFG_CR7SSS_OC2SMPEXP 0
438 
440 #define RTC1_CFG_CR7SSS_OC2SMPPTRN 0
441 
443 #define RTC1_CFG_CR7SSS_OC3SMPEXP 0
444 
446 #define RTC1_CFG_CR7SSS_OC3SMPPTRN 0
447 
449 #define RTC1_CFG_GPMUX0_OC1GPIN0SEL 0
450 
452 #define RTC1_CFG_GPMUX0_OC1GPIN1SEL 1
453 
455 #define RTC1_CFG_GPMUX0_OC1GPIN2SEL 2
456 
458 #define RTC1_CFG_GPMUX0_OC2GPIN0SEL 3
459 
461 #define RTC1_CFG_GPMUX0_OC2GPIN1SEL 4
462 
464 #define RTC1_CFG_GPMUX1_OC2GPIN2SEL 5
465 
467 #define RTC1_CFG_GPMUX1_OC3GPIN0SEL 6
468 
470 #define RTC1_CFG_GPMUX1_OC3GPIN1SEL 7
471 
473 #define RTC1_CFG_GPMUX1_OC3GPIN2SEL 0
474 
476 #define RTC1_CFG_GPMUX1_OC1DIFFOUT 0
477 
479 #define RTC1_CFG_GPMUX1_OC3DIFFOUT 0
480 
481 
485 #endif /* ADI_RTC_CONFIG_H__ */