ADuCM4x50 Device Drivers API Reference Manual  Release 4.0.0.0
adi_adc.c
1 
25 #ifndef ADI_ADC_C
26 
27 #define ADI_ADC_C
28 
29 /*============= I N C L U D E S =============*/
30 
31 
32 /* Header file with definitions specific to ADC driver implementation */
33 
34 /*============= A D C I M P L E M E N T A T I O N S O U R C E F I L E S =============*/
35 #include <drivers/adc/adi_adc.h>
36 #include <adi_processor.h>
37 #include <assert.h>
38 #include <string.h>
39 #include <drivers/pwr/adi_pwr.h>
40 #include <adi_adc_config.h>
41 #include <rtos_map/adi_rtos_map.h>
42 
43 #ifdef __ICCARM__
44 /*
45 * IAR MISRA C 2004 error suppressions.
46 *
47 * Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
48 * This isn't a header as such.
49 *
50 * Pm073 (rule 14.7): a function should have a single point of exit
51 * Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
52 * Multiple returns are used for error handling.
53 *
54 * Pm050 (rule 14.2): a null statement shall only occur on a line by itself
55 * Needed for null expansion of ADI_INSTALL_HANDLER and others.
56 *
57 * Pm088 (rule 17.4): pointer arithmetic should not be used.
58 * Relying on pointer arithmetic for buffer handling.
59 *
60 * Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
61 * The rule makes an exception for memory-mapped register accesses.
62 *
63 * Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type
64 * Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
65 
66 */
67 #pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm152
68 #endif /* __ICCARM__ */
69 
70 #include "adi_adc_def.h"
71 #include "adi_adc_data.c"
72 
73 /*============== D E F I N E S ===============*/
74 #ifdef ADI_DEBUG
75 #define ADI_ADC_INVALID_HANDLE(h) (AdcDevInfo[0].hDevice != (h))
76 #endif
77 
78 /* Specify the maximum acquisition time, based on the width of the SAMPTIME field. */
79 #define ADI_MAX_ACQUISITION_TIME (((uint32_t)BITM_ADC_CNV_TIME_SAMPTIME << BITP_ADC_CNV_TIME_SAMPTIME) + 1u)
80 
81 /* The 12bit maximum sample value */
82 #define ADI_ADC_SAMPLE_MAX ((uint16_t)(4095u))
83 
84 /*============= C O D E =============*/
85 
86 /*============= D E B U G F U N C T I O N P R O T O T Y P E S =============*/
87 
88 /* Override "weak" default binding in startup_*.c */
90 #if defined(__ADUCM302x__)
91 extern void ADC_Int_Handler(void);
92 #else
93 extern void ADC0_Int_Handler(void);
94 #endif
95 
96 /* macro definition for ADuCM3029 */
97 #if defined(__ADUCM302x__)
98 #define BITM_ADC_CFG_VREFVBAT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* VRef VBAT */
99 #endif
100 
101 extern void DMA_ADC0_Int_Handler (void);
102 
105 /* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */
106 /*============= L O C A L F U N C T I O N S P R O T O T Y P E S =============*/
107 static uint16_t ReadOutReg(uint32_t nChannelNum);
108 
109 /* ADC management functions, based on transfer method */
110 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
111 static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
112 #else
113 static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
114 #endif
115 
116 /* Channel helper functions */
117 static uint32_t GetNumChannels(uint32_t nChannels);
118 static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel);
119 
120 /* Buffer management functions */
121 static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice);
122 static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice);
123 static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels);
124 
125 /* Internal configuration functions */
126 static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable);
127 static void StaticConfiguration(ADI_ADC_DEVICE *pDevice);
128 
131 /*============= P U B L I C F U N C T I O N S =============*/
132 
149  uint32_t nDeviceNum,
150  void *pMemory,
151  uint32_t nMemorySize,
152  ADI_ADC_HANDLE *phDevice)
153 {
154  ADI_INT_STATUS_ALLOC();
155  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)pMemory;
156 
157 #ifdef ADI_DEBUG
158  if (nDeviceNum > (sizeof (AdcDevInfo)/sizeof(AdcDevInfo[0])))
159  {
161  }
162 
163  if (nMemorySize < ADI_ADC_MEMORY_SIZE)
164  {
166  }
167 
168  if (AdcDevInfo[nDeviceNum].hDevice != NULL)
169  {
170  return ADI_ADC_IN_USE;
171  }
172 
173  assert (ADI_ADC_MEMORY_SIZE >= sizeof (ADI_ADC_DEVICE));
174 #endif /* ADI_DEBUG */
175 
176  memset (pMemory, 0, nMemorySize);
177 
178  ADI_ENTER_CRITICAL_REGION();
179  AdcDevInfo[nDeviceNum].hDevice = (ADI_ADC_HANDLE)pDevice;
180  pDevice->pReg = AdcDevInfo[nDeviceNum].pReg;
181  ADI_EXIT_CRITICAL_REGION();
182 
183  /* Reset the ADC */
184  pDevice->pReg->CFG = BITM_ADC_CFG_RST;
185 
186  /* Enable the IRQs */
187  NVIC_ClearPendingIRQ(ADC0_EVT_IRQn);
188  NVIC_EnableIRQ(ADC0_EVT_IRQn);
189 
190  /* Initialize the registers to known value */
191  pDevice->pReg->IRQ_EN = BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE;
192 
193  /* Do the static configuration */
194  StaticConfiguration(pDevice);
195 
196  /* Create a semaphore for buffer management */
197  SEM_CREATE(pDevice, "ADC Sem", ADI_ADC_ERR_RTOS);
198 
199  /* Set the default FIFO Manage function */
200 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
201  pDevice->pfManageFifo = DmaFIFOManage;
202  /* Make sure the DMA controller and its SRAM based descriptors are initialized */
203  adi_dma_Init();
204 #else
205  pDevice->pfManageFifo = InterruptFIFOManage;
206 #endif
207 
208  /* Return the device handle back to the application */
209  *phDevice = AdcDevInfo[nDeviceNum].hDevice;
210 
211  return ADI_ADC_SUCCESS;
212 }
213 
214 
225 {
226  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
227  ADI_ADC_RESULT eResult;
228 
229 #ifdef ADI_DEBUG
230  if (pDevice == NULL)
231  {
233  }
234 #endif /* ADI_DEBUG */
235 
236  /* Power down the device */
237  if ((eResult = adi_adc_PowerUp (hDevice, false)) != ADI_ADC_SUCCESS) {
238  return eResult;
239  }
240 
241  /* Disable the IRQ */
242  pDevice->pReg->IRQ_EN = 0u;
243 
244  /* Clear the conversion cfg register to stop any transaction */
245  pDevice->pReg->CNV_CFG = 0u;
246 
247 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
248  /* Close the DMA if configured */
249  NVIC_DisableIRQ(DMA0_CH24_DONE_IRQn);
250 #endif /* ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 */
251 
252  /* Disable the ADC interrupt */
253  NVIC_DisableIRQ(ADC0_EVT_IRQn);
254 
255  /* Destroy the semaphore */
256  SEM_DELETE(pDevice, ADI_ADC_ERR_RTOS);
257 
258  /* Finally, zero the device */
259  AdcDevInfo[0].hDevice = (NULL);
260 
261  return ADI_ADC_SUCCESS;
262 }
263 
264 
279 {
280  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
281  uint32_t nClock = 0u;
282  uint16_t nCount = 0u;
284 
285 #ifdef ADI_DEBUG
286  if (pDevice == NULL)
287  {
289  }
290 #endif /* ADI_DEBUG */
291 
292  if (bPowerUp == true)
293  {
294  if (IS_NOT_IN_ANY_STATE(ADC_STATUS_POWERED_UP))
295  {
297  {
298  /* We need the cycles equivelent of 20us entered here, based on the PCLK
299  * clock. nClock is the frequency of the PCLK, 50000 is the equivalent frequency of 20us
300  * e.g. 26,000,000Hz, 0.00002s produces 520 cycles.*/
301  nCount = (uint16_t)(nClock / 50000u);
302 
303  /* Powering up ADC */
304  pDevice->pReg->CFG |= BITM_ADC_CFG_PWRUP;
305 
306  /* Set ADC_PWRUP.WAIT bits for the new count */
307  pDevice->pReg->PWRUP = (uint16_t)(((uint32_t)nCount << BITP_ADC_PWRUP_WAIT) & BITM_ADC_PWRUP_WAIT);
308 
309  SET_STATE(ADC_STATUS_POWERED_UP);
310  }
311  else
312  {
313  eResult = ADI_ADC_BAD_SYS_CLOCK;
314  }
315  }
316  }
317  else
318  {
319  if (IS_IN_STATE(ADC_STATUS_POWERED_UP))
320  {
321  /* If the ADC system is up then disable the ADC subsystem */
322  if ( IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN) )
323  {
324  eResult = adi_adc_EnableADCSubSystem (hDevice, false);
325  if (eResult != ADI_ADC_SUCCESS)
326  {
327  return eResult;
328  }
329  }
330 
331  /* Powering down ADC */
332  pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_PWRUP));
333  CLR_STATE(ADC_STATUS_POWERED_UP);
334  }
335  }
336 
337  return eResult;
338 }
339 
340 
359  ADI_ADC_HANDLE hDevice,
360  ADI_CALLBACK pfCallback,
361  void *pCBParam)
362 {
363  ADI_INT_STATUS_ALLOC();
364 
365  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
366 
367 #ifdef ADI_DEBUG
368  if (pDevice == NULL)
369  {
371  }
372 
373  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
374  {
376  }
377 
378 #endif /* ADI_DEBUG */
379 
380  ADI_ENTER_CRITICAL_REGION();
381  pDevice->pfCallback = pfCallback;
382  pDevice->pCBParam = pCBParam;
383  ADI_EXIT_CRITICAL_REGION();
384 
385  return ADI_ADC_SUCCESS;
386 }
387 
408  ADI_ADC_HANDLE hDevice,
409  bool bEnable)
410 {
411  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
412 
413 #ifdef ADI_DEBUG
414  if (pDevice == NULL)
415  {
417  }
418 
419  if (IS_NOT_IN_STATE(ADC_STATUS_POWERED_UP))
420  {
422  }
423 
424  if (bEnable == true) {
425  if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
427  }
428  } else {
429  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
431  }
432  }
433 #endif /* ADI_DEBUG */
434 
435  if (bEnable == true)
436  {
437  pDevice->pReg->CFG |= BITM_ADC_CFG_EN;
438  SET_STATE(ADC_STATUS_SUB_SYSTEM_EN);
439  }
440  else
441  {
442  pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_EN);
443  CLR_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_SUB_SYSTEM_READY);
444  }
445 
446  return ADI_ADC_SUCCESS;
447 }
448 
449 
470  ADI_ADC_HANDLE hDevice,
471  bool *pbReady
472 )
473 {
474  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
475 
476 #ifdef ADI_DEBUG
477  if (pDevice == NULL)
478  {
480  }
481 
482  if (pbReady == NULL)
483  {
484  return ADI_ADC_NULL_POINTER;
485  }
486 
487  if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN))
488  {
490  }
491 #endif /* ADI_DEBUG */
492 
493  if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_READY))
494  {
495  *pbReady = true;
496  }
497  else
498  {
499  *pbReady = false;
500  }
501  return ADI_ADC_SUCCESS;
502 }
503 
522  ADI_ADC_HANDLE hDevice,
523  ADI_ADC_VREF_SRC eVrefSrc)
524 {
526  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
527 
528 #ifdef ADI_DEBUG
529  if (pDevice == NULL)
530  {
532  }
533 
534  if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN))
535  {
537  }
538 #endif /* ADI_DEBUG */
539 
540  pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL | BITM_ADC_CFG_VREFVBAT));
541 
542  switch (eVrefSrc)
543  {
545  pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
546  break;
547 
549  pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN;
550  break;
551 
553  pDevice->pReg->CFG |= BITM_ADC_CFG_VREFVBAT;
554  break;
555 
557  break;
558 
559  default:
560  eResult = ADI_ADC_INVALID_PARAMETER;
561  break;
562  }
563 
564  return eResult;
565 }
566 
567 
584  ADI_ADC_HANDLE hDevice,
585  bool bEnable)
586 {
587  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
588 
589 #ifdef ADI_DEBUG
590  if (pDevice == NULL)
591  {
593  }
594 #endif /* ADI_DEBUG */
595 
596  if (bEnable == true)
597  {
598  pDevice->pReg->CFG |= BITM_ADC_CFG_SINKEN;
599  }
600  else
601  {
602  pDevice->pReg->CFG &= (uint16_t)~(BITM_ADC_CFG_SINKEN);
603  }
604 
605  return ADI_ADC_SUCCESS;
606 }
607 
608 
623 {
624  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
625 
626 #ifdef ADI_DEBUG
627  if (pDevice == NULL)
628  {
630  }
631 
632  /* Calibration cannot be done when ADC is processing the buffers */
633  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN))
634  {
636  }
637 
638 #endif /* ADI_DEBUG */
639 
640  /* Clear the calibration done state */
641  CLR_STATE(ADC_STATUS_CALIBRATION_DONE);
642 
643  /* Clear ADC_STAT.CALDONE */
644  pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
645 
646  /* Set the state as calibration enabled. This state will be cleared when we get the
647  calibration done interrupt. */
648  SET_STATE(ADC_STATUS_CALIBRATION_EN);
649 
650  /* Start ADC calibration */
651  pDevice->pReg->CFG |= BITM_ADC_CFG_STARTCAL;
652 
653  return ADI_ADC_SUCCESS;
654 }
655 
671  ADI_ADC_HANDLE hDevice,
672  bool *pbCalibrationDone)
673 {
674  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
675 
676 #ifdef ADI_DEBUG
677  if (pDevice == NULL)
678  {
680  }
681 
682  if (pbCalibrationDone == NULL)
683  {
684  return ADI_ADC_NULL_POINTER;
685  }
686 #endif /* ADI_DEBUG */
687 
688  /* The driver will check whether the driver is set to calibration done state. This state will
689  * be set in the driver when the calibration done interrupt is received by the driver
690  */
691  if (IS_IN_STATE(ADC_STATUS_CALIBRATION_DONE))
692  {
693  *pbCalibrationDone = true;
694  }
695  else
696  {
697  *pbCalibrationDone = false;
698  }
699 
700  return ADI_ADC_SUCCESS;
701 }
702 
703 
704 
723  ADI_ADC_HANDLE hDevice,
724  uint32_t nAcqTimeInAClkCycles
725  )
726 {
727  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
728  uint16_t nCnvTime;
729 
730 #ifdef ADI_DEBUG
731  if (pDevice == NULL)
732  {
734  }
735 
736  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
737  {
739  }
740 
741  /* A valid range is 1u to the width of the SAMPTIME field + 1. */
742  if ((nAcqTimeInAClkCycles == 0u) || (nAcqTimeInAClkCycles > (ADI_MAX_ACQUISITION_TIME)))
743  {
745  }
746 
747 #endif /* ADI_DEBUG */
748 
749  /* Acquisition phase is (ADC_CNV_TIME.SAMPTIME + 1) ACLK cycles */
750  nCnvTime = pDevice->pReg->CNV_TIME;
751  nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_SAMPTIME);
752  nCnvTime |= (uint16_t)((nAcqTimeInAClkCycles - ((uint32_t)1u)) << BITP_ADC_CNV_TIME_SAMPTIME);
753  pDevice->pReg->CNV_TIME = nCnvTime;
754 
755  return ADI_ADC_SUCCESS;
756 }
757 
771  ADI_ADC_HANDLE hDevice,
772  uint32_t nDelayInAClkCycles)
773 {
774  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
775  uint16_t nCnvTime;
776 
777 #ifdef ADI_DEBUG
778  if (pDevice == NULL)
779  {
781  }
782 
783  if (nDelayInAClkCycles > (BITM_ADC_CNV_TIME_DLY >> BITP_ADC_CNV_TIME_DLY))
784  {
786  }
787 #endif /* ADI_DEBUG */
788 
789  nCnvTime = pDevice->pReg->CNV_TIME;
790  nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_DLY);
791  nCnvTime |= (uint16_t)(nDelayInAClkCycles << BITP_ADC_CNV_TIME_DLY);
792  pDevice->pReg->CNV_TIME = nCnvTime;
793 
794  return ADI_ADC_SUCCESS;
795 }
796 
813  ADI_ADC_HANDLE hDevice,
814  ADI_ADC_RESOLUTION eResolution)
815 {
816  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
817  uint16_t nFactor;
818 
819 #ifdef ADI_DEBUG
820  if (pDevice == NULL)
821  {
823  }
824  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
825  {
827  }
828  if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN) && (eResolution != ADI_ADC_RESOLUTION_12_BIT))
829  {
830  return ADI_ADC_INVALID_STATE;
831  }
832 #endif /* ADI_DEBUG */
833 
834  switch (eResolution)
835  {
837  pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_OS);
838  if (IS_NOT_IN_STATE(ADC_STATUS_AVGERAGING_EN)) {
839  pDevice->pReg->AVG_CFG = 0u;
840  }
841  CLR_STATE(ADC_STATUS_OVERSAMPLING_EN);
842  break;
843 
848  /* factor = 0x02 for 13-bit
849  0x08 for 14-bit
850  0x20 for 15-bit
851  0x80 for 16-bit */
852  nFactor = (uint16_t)1u << (((uint16_t)eResolution * 2u) - ((uint16_t)1u));
853  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN
854  | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
855  SET_STATE(ADC_STATUS_OVERSAMPLING_EN);
856 
857  break;
858 
859  default:
861  }
862 
863  return ADI_ADC_SUCCESS;
864 }
865 
881  ADI_ADC_HANDLE hDevice,
882  uint16_t nAveragingSamples
883  )
884 {
885  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
886  uint16_t nFactor;
887 
888 #ifdef ADI_DEBUG
889  if (pDevice == NULL)
890  {
892  }
893 
894  if ((nAveragingSamples == 0u) || (nAveragingSamples > 256u)
895  /* Or nAveragingSamples is not a power of 2 */
896  || ((nAveragingSamples & (nAveragingSamples - 1u)) != 0u))
897  {
899  }
900  if (IS_IN_STATE(ADC_STATUS_OVERSAMPLING_EN))
901  {
902  return ADI_ADC_INVALID_STATE;
903  }
904 #endif /* ADI_DEBUG */
905 
906  /* Disable averaging */
907  if (nAveragingSamples == 1u)
908  {
909  pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_EN);
910  CLR_STATE(ADC_STATUS_AVGERAGING_EN);
911  }
912  else
913  {
914  nFactor = nAveragingSamples >> 1;
915  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_EN | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
916  SET_STATE(ADC_STATUS_AVGERAGING_EN);
917  }
918 
919  return ADI_ADC_SUCCESS;
920 }
921 
939  ADI_ADC_HANDLE hDevice,
940  ADI_ADC_CHANNEL eChannel,
941  bool bEnable,
942  uint16_t nLowLimit
943  )
944 {
945  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
946  static volatile uint16_t* pRegister[4] = {
947  pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO
948  };
949  int32_t nChannelNum = 0;
950 
951 #ifdef ADI_DEBUG
952  if (pDevice == NULL)
953  {
955  }
956  if ((nLowLimit > (BITM_ADC_LIM0_LO_VALUE >> BITP_ADC_LIM0_LO_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
957  {
959  }
960 #endif /* ADI_DEBUG */
961 
962  nChannelNum = nGetChannelNumber(eChannel);
963 
964  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
965  if (bEnable == true) {
966 
967  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_LO_VALUE)) |
968  (uint16_t)(nLowLimit << BITP_ADC_LIM0_LO_VALUE);
969 
970  /* Now enable this channel comparitor - unused until the comparitor is enabled */
971  pDevice->ComparitorLo |= (1u << nChannelNum);
972  }
973  else {
974  pDevice->ComparitorLo &= ~(1u << nChannelNum);
975  }
976  }
977 
978  return ADI_ADC_SUCCESS;
979 }
980 
998  ADI_ADC_HANDLE hDevice,
999  ADI_ADC_CHANNEL eChannel,
1000  bool bEnable,
1001  uint16_t nHighLimit)
1002 {
1003  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1004  static volatile uint16_t* pRegister[4] = {
1005  pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI
1006  };
1007  int32_t nChannelNum = 0;
1008 
1009 #ifdef ADI_DEBUG
1010  if (pDevice == NULL)
1011  {
1013  }
1014  if ((nHighLimit > (BITM_ADC_LIM0_HI_VALUE >> BITP_ADC_LIM0_HI_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
1015  {
1017  }
1018 #endif /* ADI_DEBUG */
1019 
1020  nChannelNum = nGetChannelNumber(eChannel);
1021 
1022  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
1023  if (bEnable == true) {
1024  /* Set the given high value - only relevant if the limit is enabled. */
1025  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_HI_VALUE))
1026  | (uint16_t)(nHighLimit << BITP_ADC_LIM0_HI_VALUE);
1027 
1028  /* Now enable this channel comparitor - unused until the comparitor is enabled */
1029  pDevice->ComparitorHi |= (1u << nChannelNum);
1030  }
1031  else {
1032  pDevice->ComparitorHi &= ~(1u << nChannelNum);
1033  }
1034  }
1035  return ADI_ADC_SUCCESS;
1036 }
1037 
1055  ADI_ADC_HANDLE hDevice,
1056  ADI_ADC_CHANNEL eChannel,
1057  bool bEnable,
1058  uint16_t nHysteresis)
1059 {
1060  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1061  static volatile uint16_t* pRegister[4] = {
1062  pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
1063  };
1064  int32_t nChannelNum = 0;
1065 
1066 #ifdef ADI_DEBUG
1067  if (pDevice == NULL)
1068  {
1070  }
1071  if ((nHysteresis > (BITM_ADC_HYS0_VALUE >> BITP_ADC_HYS0_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
1072  {
1074  }
1075 #endif /* ADI_DEBUG */
1076 
1077  nChannelNum = nGetChannelNumber(eChannel);
1078 
1079  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
1080  if (bEnable == true) {
1081  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_VALUE))
1082  | (uint16_t)(nHysteresis << BITP_ADC_HYS0_VALUE);
1083 
1084  /* Now enable this channel hysteresis - unused until the comparitor is enabled */
1085  pDevice->ComparitorHys |= (1u << nChannelNum);
1086  }
1087  else {
1088  pDevice->ComparitorHys &= ~(1u << nChannelNum);
1089  }
1090  }
1091 
1092  return ADI_ADC_SUCCESS;
1093 }
1094 
1110  ADI_ADC_HANDLE hDevice,
1111  ADI_ADC_CHANNEL eChannel,
1112  uint32_t nNumMonitorCycles)
1113 {
1114  #ifdef ADI_DEBUG
1115  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1116 #endif /* ADI_DEBUG */
1117 
1118  static volatile uint16_t* pRegister[4] = {
1119  pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
1120  };
1121  int32_t nChannelNum = 0;
1122 
1123 #ifdef ADI_DEBUG
1124  if (pDevice == NULL)
1125  {
1127  }
1128  if ((nNumMonitorCycles > (BITM_ADC_HYS0_MONCYC >> BITP_ADC_HYS0_MONCYC)) || (nChannelNum < 0) || (nChannelNum > 3))
1129  {
1131  }
1132 #endif /* ADI_DEBUG */
1133 
1134  nChannelNum = nGetChannelNumber(eChannel);
1135 
1136  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
1137  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_MONCYC))
1138  | (uint16_t)(nNumMonitorCycles << BITP_ADC_HYS0_MONCYC);
1139  }
1140  return ADI_ADC_SUCCESS;
1141 }
1142 
1143 
1144 
1162  ADI_ADC_HANDLE hDevice,
1163  bool bEnableComparator
1164 )
1165 {
1166  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1167 #ifdef ADI_DEBUG
1168  if (pDevice == NULL)
1169  {
1171  }
1172 
1173  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN))
1174  {
1175  return ADI_ADC_INVALID_SEQUENCE;
1176  }
1177 
1178  if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN | ADC_STATUS_OVERSAMPLING_EN))
1179  {
1180  return ADI_ADC_INVALID_STATE;
1181  }
1182 
1183  if (pDevice->pfCallback == NULL) {
1185  }
1186 
1187  if (bEnableComparator == true) {
1188  if((pDevice->ComparitorHi | pDevice->ComparitorLo) == 0u) {
1189  return ADI_ADC_INVALID_STATE;
1190  }
1191  }
1192 #endif /* ADI_DEBUG */
1193 
1194  EnableComparator(pDevice, bEnableComparator);
1195 
1196  return ADI_ADC_SUCCESS;
1197 }
1198 
1217  ADI_ADC_HANDLE hDevice,
1218  ADI_ADC_BUFFER* pBuffer
1219 )
1220 {
1221  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1222  uint32_t nNumChannels = 0u;
1223 
1224  ADC_INT_BUFFER* pIntBuffer;
1225 
1226 #ifdef ADI_DEBUG
1227  if (pDevice == NULL)
1228  {
1230  }
1231  if (pBuffer == NULL) {
1232  return ADI_ADC_NULL_POINTER;
1233  }
1234  if ((pBuffer->nChannels == 0u) || (pBuffer->pDataBuffer == NULL) || (pBuffer->nNumConversionPasses == 0u))
1235  {
1236  return ADI_ADC_INVALID_BUFFER;
1237  }
1238 #endif /* ADI_DEBUG */
1239 
1240  nNumChannels = GetNumChannels(pBuffer->nChannels);
1241 
1242  pIntBuffer = &pDevice->s_Buffer;
1243 
1244  pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
1245  pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
1246  if (pBuffer->nNumConversionPasses == 1u)
1247  {
1248  pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
1249  }
1250  pIntBuffer->pUserBuffer = pBuffer;
1251  pIntBuffer->pCurDataBuffer = pBuffer->pDataBuffer;
1252  pIntBuffer->nNumSamplesRemaining = nNumChannels * pBuffer->nNumConversionPasses;
1253  pIntBuffer->nChannels = pBuffer->nChannels;
1254 
1255  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
1256 
1257  return ADI_ADC_SUCCESS;
1258 }
1259 
1280  ADI_ADC_HANDLE hDevice,
1281  ADI_ADC_BUFFER **ppBuffer)
1282 {
1283  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1284  ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
1285 
1286 #ifdef ADI_DEBUG
1287  if (pDevice == NULL)
1288  {
1290  }
1291  if (ppBuffer == NULL) {
1292  return ADI_ADC_NULL_POINTER;
1293  }
1294  if (pDevice->pfCallback != NULL) {
1296  }
1297  if (IS_NOT_IN_STATE(ADC_STATUS_NON_BLOCKING_EN)) {
1298  return ADI_ADC_INVALID_SEQUENCE;
1299  }
1300 #endif /* ADI_DEBUG */
1301 
1302  if (pDevice->s_Buffer.pUserBuffer == NULL) {
1303  return ADI_ADC_INVALID_STATE;
1304  }
1305 
1306  /* Wait for read completion */
1307  SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);
1308 
1309  if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
1310  eADCresult = ADI_ADC_BUFFER_OVERFLOW;
1311  }
1312  *ppBuffer = pDevice->s_Buffer.pUserBuffer;
1313  pDevice->s_Buffer.pUserBuffer = NULL;
1314  CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
1315 
1316  return eADCresult;
1317 }
1318 
1334  ADI_ADC_HANDLE hDevice,
1335  bool bEnable)
1336 {
1337  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1338 
1339 #ifdef ADI_DEBUG
1340  if (pDevice == NULL)
1341  {
1343  }
1344 
1345  if (IS_IN_ANY_STATE(ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
1346  return ADI_ADC_INVALID_STATE;
1347  }
1348 #endif /* ADI_DEBUG */
1349 
1350  if (bEnable == true) {
1351  /* Set the driver to be in non-blocking mode */
1352  SET_STATE(ADC_STATUS_NON_BLOCKING_EN);
1353 
1354  /* Enable the IRQs */
1355  NVIC_EnableIRQ(ADC0_EVT_IRQn);
1356 
1357  /* Try to submit possible number of buffers */
1358  InitBufferProcessing(pDevice);
1359  } else {
1360  /* Disble the IRQs */
1361  NVIC_DisableIRQ(ADC0_EVT_IRQn);
1362 
1363  /* Abort any transaction if present */
1364  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ABORT);
1365 
1366  CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
1367  }
1368 
1369  return ADI_ADC_SUCCESS;
1370 }
1371 
1372 
1389  ADI_ADC_HANDLE hDevice,
1390  bool *pbIsBufferAvailable)
1391 {
1392  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1393 #ifdef ADI_DEBUG
1394  if (pDevice == NULL)
1395  {
1397  }
1398  if (pbIsBufferAvailable == NULL)
1399  {
1400  return ADI_ADC_NULL_POINTER;
1401  }
1402  if (pDevice->pfCallback != NULL) {
1404  }
1405 #endif /* ADI_DEBUG */
1406 
1407  if(IS_IN_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS))
1408  {
1409  *pbIsBufferAvailable = false;
1410  }
1411  else
1412  {
1413  *pbIsBufferAvailable = true;
1414  }
1415 
1416  return ADI_ADC_SUCCESS;
1417 }
1418 
1419 
1449  ADI_ADC_HANDLE hDevice,
1450  uint32_t nChannels,
1451  uint32_t nNumConversionPasses,
1452  void *pBuffer,
1453  uint32_t nBuffLength)
1454 {
1455  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1456  uint32_t nNumChannels = 0u;
1457  ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
1458 
1459  ADC_INT_BUFFER* pIntBuffer;
1460 
1461 #ifdef ADI_DEBUG
1462  if (pDevice == NULL)
1463  {
1465  }
1466  if ((nChannels == 0u) || (nNumConversionPasses == 0u) || (pBuffer == NULL))
1467  {
1469  }
1470  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
1471  {
1472  return ADI_ADC_INVALID_SEQUENCE;
1473  }
1474 #endif /* ADI_DEBUG */
1475 
1476  nNumChannels = GetNumChannels(nChannels);
1477 
1478  if (nBuffLength < ((nNumChannels * sizeof(uint16_t)) * nNumConversionPasses))
1479  {
1481  }
1482 
1483  /* Clear ADC status */
1484  pDevice->pReg->STAT = 0xFFFFu;
1485 
1486  /* Set the driver to be in blocking mode */
1487  SET_STATE(ADC_STATUS_BLOCKING_EN);
1488 
1489  /* Get the buffer */
1490  pIntBuffer = &pDevice->s_Buffer;
1491 
1492  pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
1493  if (nNumConversionPasses == 1u) {
1494  pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
1495  }
1496 
1497  pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
1498  pIntBuffer->pUserBuffer = NULL;
1499  pIntBuffer->pCurDataBuffer = pBuffer;
1500  pIntBuffer->nNumSamplesRemaining = nNumChannels * nNumConversionPasses;
1501  pIntBuffer->nChannels = nChannels;
1502 
1503  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
1504 
1505  InitBufferProcessing(pDevice);
1506 
1507  /* Wait for read completion */
1508  SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);
1509 
1510  if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
1511  eADCresult = ADI_ADC_BUFFER_OVERFLOW;
1512  }
1513 
1514  /* Driver is no longer in blocking mode */
1515  CLR_STATE(ADC_STATUS_BLOCKING_EN);
1516 
1517  /* Enable the IRQs */
1518  NVIC_DisableIRQ(ADC0_EVT_IRQn);
1519 
1520  return eADCresult;
1521 }
1522 
1537 {
1538  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1539 
1540 #ifdef ADI_DEBUG
1541  if (NULL == pDevice)
1542  {
1544  }
1545 #endif /* ADI_DEBUG */
1546 
1547  NVIC_ClearPendingIRQ(ADC0_EVT_IRQn);
1548 
1549  if (bEnable)
1550  {
1551  /* Enable the IRQ */
1552  pDevice->pReg->IRQ_EN = (BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE);
1553  /* Enable the ADC interrupt */
1554  NVIC_EnableIRQ(ADC0_EVT_IRQn);
1555  }
1556  else
1557  {
1558  /* Disable the IRQ */
1559  pDevice->pReg->IRQ_EN = 0u;
1560  /* Disable the ADC interrupt */
1561  NVIC_DisableIRQ(ADC0_EVT_IRQn);
1562  }
1563  return ADI_ADC_SUCCESS;
1564 }
1565 
1586  ADI_ADC_HANDLE hDevice,
1587  uint32_t nRefVoltage,
1588  uint32_t *pnBatVoltage)
1589 {
1590  ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
1591  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1592  uint16_t nConvTimeBackup;
1593  uint16_t nAvgCfgBackup;
1594  uint32_t nAdcValue = 0u;
1595  uint32_t nClock = 0u;
1596  uint32_t nACLKDIVCNT;
1597 
1598 #ifdef ADI_DEBUG
1599  if (pDevice == NULL)
1600  {
1602  }
1603  if (pnBatVoltage == NULL)
1604  {
1605  return ADI_ADC_NULL_POINTER;
1606  }
1607 
1608  if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
1609  return ADI_ADC_INVALID_SEQUENCE;
1610  }
1611 
1612  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
1613  return ADI_ADC_INVALID_SEQUENCE;
1614  }
1615 #endif /* ADI_DEBUG */
1616 
1618  {
1619  /* Take the backup of registers that need to be changed */
1620  nConvTimeBackup = pDevice->pReg->CNV_TIME;
1621  nAvgCfgBackup = pDevice->pReg->AVG_CFG;
1622 
1623  /* Set the required value in the registers. */
1624  nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
1625 
1626  /* Calculate the number of cycles required for conversion.
1627  * The conversion time required is 500ns = 2000000Hz
1628  */
1629  nClock = nClock/nACLKDIVCNT; /* nClock = ACLK frequency Hz */
1630  pDevice->pReg->CNV_TIME = (uint16_t)((nClock/2000000u) + ((uint16_t)1u));
1631  pDevice->pReg->AVG_CFG = 0u;
1632 
1633  /* Clear the battery done status */
1634  pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
1635 
1636  /* Clear the battery done state */
1637  CLR_STATE(ADC_STATUS_BATTERY_DONE);
1638 
1639  /* Set the registers */
1640  pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_BAT);
1641 
1642  /* Wait for the Battery done status */
1643  while (IS_NOT_IN_STATE(ADC_STATUS_BATTERY_DONE)) { ; }
1644 
1645  /* Clear the conversion register */
1646  pDevice->pReg->CNV_CFG = 0u;
1647 
1648  /* Restore the changed registers */
1649  pDevice->pReg->CNV_TIME = nConvTimeBackup;
1650  pDevice->pReg->AVG_CFG = nAvgCfgBackup;
1651 
1652  /* Calculate the battery voltage */
1653 
1654  /* From HRM: converting ADC result to battery voltage, following calculations should be done:
1655  * VBAT = 4 * (adc_out) * Vref / (2^12 - 1) */
1656  nAdcValue = pDevice->pReg->BAT_OUT;
1657  *pnBatVoltage = (4u * nAdcValue * nRefVoltage) / ADI_ADC_SAMPLE_MAX;
1658  }
1659  else
1660  {
1661  eResult = ADI_ADC_BAD_SYS_CLOCK;
1662  }
1663 
1664  return eResult;
1665 }
1679  ADI_ADC_HANDLE hDevice,
1680  bool bEnable)
1681 {
1682  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1683 
1684 #ifdef ADI_DEBUG
1685  if (pDevice == NULL)
1686  {
1688  }
1689 #endif /* ADI_DEBUG */
1690 
1691  if (bEnable == true)
1692  {
1693  pDevice->pReg->CFG |= (uint16_t)BITM_ADC_CFG_TMPEN;
1694  SET_STATE(ADC_STATUS_TEMP_SENSOR_EN);
1695  }
1696  else
1697  {
1698  pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_TMPEN);
1699  CLR_STATE(ADC_STATUS_TEMP_SENSOR_EN);
1700  }
1701 
1702  return ADI_ADC_SUCCESS;
1703 }
1704 
1705 
1730  ADI_ADC_HANDLE hDevice,
1731  uint32_t nRefVoltage,
1732  int32_t* pnTemperature
1733  )
1734 {
1735  ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
1736  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1737  uint16_t nConvTimeBackup;
1738  uint16_t nAvgCfgBackup;
1739  uint32_t nAdcTmpValue = 0u;
1740  uint32_t nAdcTmp2Value = 0u;
1741  uint32_t nClock = 0u;
1742  uint32_t nACLKDIVCNT;
1743  uint32_t nCnvTime;
1744 
1745 #ifdef ADI_DEBUG
1746  if (pDevice == NULL)
1747  {
1749  }
1750  if (pnTemperature == NULL)
1751  {
1752  return ADI_ADC_NULL_POINTER;
1753  }
1754 
1755  if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_TEMP_SENSOR_EN))
1756  {
1757  return ADI_ADC_INVALID_SEQUENCE;
1758  }
1759 
1760  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
1761  {
1762  return ADI_ADC_INVALID_SEQUENCE;
1763  }
1764 #endif
1765 
1766 
1768  {
1769  /* Calculate the conversion time */
1770  nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
1771  nCnvTime = ((nClock / nACLKDIVCNT) / (uint16_t)15385u) + 1u; /* 65us acquisition time required = 15385Hz sample */
1772 
1773  #ifdef ADI_DEBUG
1774  if (nCnvTime >= 256u) {
1775  return ADI_ADC_INVALID_STATE;
1776  }
1777  #endif
1778  /* Take the backup of registers that need to be changed */
1779  nConvTimeBackup = pDevice->pReg->CNV_TIME;
1780  nAvgCfgBackup = pDevice->pReg->AVG_CFG;
1781 
1782  /* Set the required value in the registers. */
1783 
1784  pDevice->pReg->CNV_TIME = (uint16_t)((nCnvTime << BITP_ADC_CNV_TIME_SAMPTIME) & BITM_ADC_CNV_TIME_SAMPTIME);
1785  pDevice->pReg->AVG_CFG = 0u;
1786 
1787  /* Clear the temperature done status */
1788  pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE | BITM_ADC_STAT_TMP2DONE;
1789 
1790  /* Clear the temperature done state */
1791  CLR_STATE(ADC_STATUS_TMP_DONE | ADC_STATUS_TMP2_DONE);
1792 
1793  /* Sample Tmp register */
1794  pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP);
1795  while (IS_NOT_IN_STATE(ADC_STATUS_TMP_DONE)) { ; }
1796  nAdcTmpValue = pDevice->pReg->TMP_OUT;
1797  pDevice->pReg->CNV_CFG = 0u;
1798 
1799 
1800  /* Sample Tmp2 register */
1801  pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP2);
1802  while (IS_NOT_IN_STATE(ADC_STATUS_TMP2_DONE)) { ; }
1803  pDevice->pReg->CNV_CFG = 0u;
1804  nAdcTmp2Value = pDevice->pReg->TMP2_OUT;
1805 
1806  /* Restore the changed registers */
1807  pDevice->pReg->CNV_TIME = nConvTimeBackup;
1808  pDevice->pReg->AVG_CFG = nAvgCfgBackup;
1809 
1810  /* Calculate the temperature voltage.
1811  * From the HRM: Temperature can be calculated as:
1812  *
1813  * T(^0 C)= code1/(code2+RG*code1)*Rvirtualreference/(ideal_sensitivity )-273.15
1814  *
1815  * Some of these values are constants, and some have been read from registers.
1816  * The above formula, when populated with variables and constants, would look like this:
1817  * T(^0 C)= (nAdcTmpValue/(nAdcTmp2Value + nTempRG * nAdcTmpValue)) * (1.2256/1.2411e-3)) -273.15
1818  */
1819  {
1820  uint32_t nRVirRefByIdealSensitivity = 2070960834u; /* 1.2256/1.2411e-3 in 11.21 format */
1821 
1822  uint32_t nTempRG = 19380u; /* 1.1829 in 2.14 format */
1823  uint32_t nTmp2 = ((nAdcTmp2Value << 14u) + (nTempRG * nAdcTmpValue)); /* in 14.14 format */
1824 
1825  uint32_t nOffsetPart = (335544320u/nRefVoltage); /* (1.25 in 4.28 format / ReferenceVoltage(16.16)) = Result in format *.12 */
1826  uint32_t nOffset = (161u * nOffsetPart); /* 12.12 format */
1827 
1828  uint32_t nTmp3 = ((nAdcTmpValue << 12) - nOffset) << 8u; /* Format 12.20 */
1829  uint32_t nRatio = (nTmp3/(nTmp2 >> 10u)); /* nTmp2 resolution reduced by 10 to 14.4 and the result resolution is 0.16 */
1830  uint32_t nTemp = (nRatio * (nRVirRefByIdealSensitivity >> 16u)) >> 5u; /* Temperature in degree kelvin in 16.16 format */
1831 
1832  int32_t iTemp = (int32_t)nTemp - ((int32_t)17901158); /* Subtract 273.15 (in 16.16) to get the temperature in degree celcius */
1833  *pnTemperature = iTemp;
1834  }
1835  }
1836  else
1837  {
1838  eResult = ADI_ADC_BAD_SYS_CLOCK;
1839  }
1840 
1841  return eResult;
1842 }
1843 
1844 
1847 /*========== S T A T I C F U N C T I O N S ==========*/
1848 /* Read the output register for the given channel number */
1849 static uint16_t ReadOutReg(uint32_t nChannelNum)
1850 {
1851  const volatile uint16_t* pOutRegister = pREG_ADC0_CH0_OUT;
1852  pOutRegister += nChannelNum*2u;
1853  return *pOutRegister;
1854 }
1855 
1856 /* Init buffer processing */
1857 static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice)
1858 {
1859  uint32_t nCnvReg = ((uint32_t)(pDevice->pReg->CNV_CFG) & BITM_ADC_CNV_CFG_DMAEN);
1860  ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
1861 
1862  if (IS_NOT_IN_ANY_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS))
1863  {
1864  /* Clear conversion done flags */
1865  pDevice->pReg->STAT = 0xFFFFu;
1866 
1867  /* Clear the overflow and alert register */
1868  pDevice->pReg->OVF = 0xFFFFu;
1869  }
1870 
1871  /* Calculate the conversion register value for the given configuration */
1872  nCnvReg |= pIntBuffer->nChannels;
1873  if ((uint16_t)(pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN) != 0u) {
1874  nCnvReg |= BITM_ADC_CNV_CFG_AUTOMODE;
1875  }
1876  if ((pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN) != 0u) {
1877  nCnvReg |= BITM_ADC_CNV_CFG_SINGLE;
1878  } else {
1879  nCnvReg |= BITM_ADC_CNV_CFG_MULTI;
1880  }
1881 
1882  SET_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
1883 
1884  pDevice->pReg->CNV_CFG |= (uint16_t)nCnvReg;
1885 
1886  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ENABLED);
1887 
1888  return true;
1889 }
1890 
1891 
1892 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
1893 /* DMA Callback Handler */
1894 void DMA_ADC0_Int_Handler (void)
1895 {
1896  ISR_PROLOG();
1897  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
1898 
1899  DmaFIFOManage(pDevice, ADC_FIFO_MODE_DMA_BUFFER_PROCESS);
1900 
1901  ISR_EPILOG();
1902 }
1903 
1904 static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
1905 {
1906  uint16_t nCount = 0u;
1907  uint16_t chanNum = ADC0_CHANn;
1908  uint16_t IRQ_Backup;
1909 
1910  ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
1911 
1912  if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
1913  /* If there is nothing active... */
1914  if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
1915  /* ...it's something leftover, so cleanup. */
1916  uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
1917  FlushFifo(pDevice, (uint32_t)nStat);
1918  pDevice->pReg->STAT = nStat;
1919  }
1920  }
1921  else {
1922  switch (eFifoMode)
1923  {
1924  case ADC_FIFO_MODE_INIT:
1925 
1926  /* Enable the interrupt for the given DMA */
1927  NVIC_EnableIRQ(DMA0_CH24_DONE_IRQn);
1928 
1929  pADI_DMA0->SRCADDR_CLR = 1U << chanNum;
1930 
1931  /* Enable the channel */
1932  pADI_DMA0->EN_SET = 1U << chanNum;
1933 
1934  /* Enables peripheral to generate DMA requests. */
1935  pADI_DMA0->RMSK_CLR = 1U << chanNum;
1936 
1937  /* Set the primary as the current DMA descriptor */
1938  pADI_DMA0->ALT_CLR = 1U << chanNum; /* Should be default */
1939 
1940  /* Setup the DMA registers */
1941  nCount = (uint16_t)pIntBuffer->nNumSamplesRemaining;
1942 
1943  /* Point to the end of the DMA source */
1944  pPrimaryCCD[chanNum].DMASRCEND = (uint32_t)(&(pDevice->pReg->DMA_OUT));
1945 
1946  /* Point to the end of the DMA write-to destination */
1947  pPrimaryCCD[chanNum].DMADSTEND = (uint32_t)((void*)pIntBuffer->pCurDataBuffer) + ((nCount * 2u) - 1u);
1948 
1949  /* Configure the DMA itself */
1950  pPrimaryCCD[chanNum].DMACDC = ((ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | /* Increment destination address */
1951  (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | /* Don't increment the source address */
1952  ((uint32_t)ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | /* 16bit transfers */
1953  ((nCount - (uint32_t)1U)<< DMA_BITP_CTL_N_MINUS_1) | /* Data size? */
1954  (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) | /* Basic only */
1955  ((uint32_t)ADI_DMA_RPOWER_1 << DMA_BITP_CTL_R_POWER)); /* Arbitration */
1956 
1957  /* Enable DMA */
1958  pDevice->pReg->CNV_CFG |= BITM_ADC_CNV_CFG_DMAEN;
1959  break;
1960 
1961  case ADC_FIFO_MODE_ENABLED:
1962  break;
1963 
1964  case ADC_FIFO_MODE_INTERRUPT_PROCESS:
1965  /* Clear the status registers */
1966  pDevice->pReg->STAT = (pDevice->pReg->STAT & 0x00FFu);
1967  break;
1968 
1969  case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
1970  pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
1971  break;
1972 
1973  case ADC_FIFO_MODE_DMA_BUFFER_PROCESS:
1974  pIntBuffer->nNumSamplesRemaining = 0u;
1975  ManageFifoCompletion(pDevice);
1976  break;
1977 
1978  case ADC_FIFO_MODE_ABORT:
1979 
1980  /* Take backup of IRQ */
1981  IRQ_Backup = pDevice->pReg->IRQ_EN;
1982 
1983  /* Disable the IRQ */
1984  pDevice->pReg->IRQ_EN = 0u;
1985 
1986  /* Clear the conversion cfg register to stop any transaction */
1987  pDevice->pReg->CNV_CFG = 0u;
1988 
1989  /* Disable the DMA channel */
1990  pADI_DMA0->EN_CLR = 1U << chanNum;
1991 
1992  /* Clear the status bits */
1993  pDevice->pReg->STAT = 0xFFFFu;
1994 
1995  /* Clear the sampling in progress state */
1996  CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
1997 
1998  /* Read and flush all the buffers */
1999  FlushFifo(pDevice, 0x00FFu);
2000 
2001  /* Restore the IRQ */
2002  pDevice->pReg->IRQ_EN = IRQ_Backup;
2003 
2004  break;
2005 
2006  default:
2007  break;
2008  }
2009  }
2010 
2011  return ADI_ADC_SUCCESS;
2012 }
2013 #else /* else ADI_ADC_ENABLE_MULTI_ACQUIRE == 0 */
2014 
2015 static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
2016 {
2017  ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
2018 
2019  if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
2020  if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
2021  uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
2022  FlushFifo(pDevice, (uint32_t)nStat);
2023  pDevice->pReg->STAT = nStat;
2024  }
2025  return ADI_ADC_SUCCESS;
2026  }
2027 
2028  switch (eFifoMode)
2029  {
2030  case ADC_FIFO_MODE_INIT:
2031  {
2032  /* Enable the conversion done and overflow interrupt */
2033  pDevice->ActData.nCurChannel = 0u;
2034  }
2035  break;
2036 
2037  case ADC_FIFO_MODE_ENABLED:
2038  break;
2039 
2040  case ADC_FIFO_MODE_INTERRUPT_PROCESS:
2041  {
2042  while (pIntBuffer->nNumSamplesRemaining > 0u) {
2043  uint32_t nConvStatus = ((uint32_t)pDevice->pReg->STAT & (uint32_t)0x00FFu);
2044  if ((nConvStatus & 0x00FFu) == 0u)
2045  {
2046  break;
2047  }
2048 
2049  uint32_t nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
2050  while ((nCurChannelBitM & nConvStatus) == 0u) {
2051  pDevice->ActData.nCurChannel++;
2052  if (pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
2053  pDevice->ActData.nCurChannel = 0u;
2054  }
2055  nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
2056  }
2057 
2058  assert ((pIntBuffer->nChannels & ((uint32_t)1u << pDevice->ActData.nCurChannel)) != 0u);
2059 
2060  *pIntBuffer->pCurDataBuffer = ReadOutReg( pDevice->ActData.nCurChannel);
2061  pIntBuffer->pCurDataBuffer++;
2062 
2063 
2064  pDevice->pReg->STAT = (uint16_t)nCurChannelBitM;
2065  pIntBuffer->nNumSamplesRemaining -= 1u;
2066 
2067  pDevice->ActData.nCurChannel += 1u;
2068  if ( pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
2069  pDevice->ActData.nCurChannel = 0u;
2070  }
2071  }
2072 
2073  if (pIntBuffer->nNumSamplesRemaining == 0u) {
2074  ManageFifoCompletion(pDevice);
2075  }
2076  }
2077  break;
2078 
2079  case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
2080  {
2081  pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
2082  }
2083  break;
2084 
2085  case ADC_FIFO_MODE_ABORT:
2086  {
2087  uint16_t IRQ_Backup;
2088 
2089  /* Take backup of IRQ */
2090  IRQ_Backup = pDevice->pReg->IRQ_EN;
2091 
2092  /* Disable the IRQ */
2093  pDevice->pReg->IRQ_EN = 0u;
2094 
2095  /* Clear the conversion cfg register to stop any transaction */
2096  pDevice->pReg->CNV_CFG = 0u;
2097 
2098  /* Clear the status bits */
2099  pDevice->pReg->STAT = 0xFFFFu;
2100 
2101  /* Clear the sampling in progress state */
2102  CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
2103 
2104  /* Read and flush all the buffers */
2105  FlushFifo(pDevice, 0x00FFu);
2106 
2107  /* Restore the IRQ */
2108  pDevice->pReg->IRQ_EN = IRQ_Backup;
2109  }
2110  break;
2111 
2112  default:
2113  break;
2114  }
2115 
2116  return ADI_ADC_SUCCESS;
2117 }
2118 #endif
2119 
2120 static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels)
2121 {
2122  uint32_t x;
2123  for (x = 0u; x < 8u; x++) {
2124  if ((nChannels & ((uint32_t)1u << x)) != 0u) {
2125  ReadOutReg(x);
2126  }
2127  }
2128 }
2129 
2130 
2131 /* Called when a transfer is complete */
2132 static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice)
2133 {
2134  /* Clear the conversion configuration */
2135  pDevice->pReg->CNV_CFG = 0u;
2136  CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
2137 
2138  SEM_POST(pDevice);
2139 }
2140 
2141 
2142 /* Internal function to extract the number of channels
2143  * in a 32bit word. */
2144 static uint32_t GetNumChannels(uint32_t nChannels)
2145 {
2146  uint32_t n = nChannels & 0x000000FFu;
2147 
2148  n = (n & 0x00000055u) + ((n >> 1u) & 0x00000055u);
2149  n = (n & 0x00000033u) + ((n >> 2u) & 0x00000033u);
2150  n = (n + (n >> 4u)) & (0x0000000Fu);
2151 
2152  return n;
2153 }
2154 
2155 /* Returns the channel number based on the ADI_ADC_CHANNEL type.
2156  * i.e. ADI_ADC_CHANNEL1 returns 1. */
2157 static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel)
2158 {
2159  int32_t retVal = 0;
2160  uint32_t nChannel = (uint32_t)eChannel & 0x000000FFu;
2161 
2162  if ((nChannel & (nChannel - (uint32_t)1u)) != 0u) {
2163  return -1;
2164  }
2165  if ((nChannel & 0x000000AAu) != 0u) { retVal += 1; }
2166  if ((nChannel & 0x000000CCu) != 0u) { retVal += 2; }
2167  if ((nChannel & 0x000000F0u) != 0u) { retVal += 4; }
2168 
2169  return retVal;
2170 }
2171 
2172 /* Internal function to set static configuration options. */
2173 static void StaticConfiguration(ADI_ADC_DEVICE *pDevice)
2174 {
2175  uint16_t nCfgReg = 0u;
2176 
2177  /* Configure the resolution */
2178 #if ADI_ADC_CFG_RESOLUTION == 12
2179  pDevice->pReg->AVG_CFG = 0u;
2180 #else
2181 
2182 #if ADI_ADC_CFG_RESOLUTION == 13
2183  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0002u << BITP_ADC_AVG_CFG_FACTOR);
2184 #elif ADI_ADC_CFG_RESOLUTION == 14
2185  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0008u << BITP_ADC_AVG_CFG_FACTOR);
2186 #elif ADI_ADC_CFG_RESOLUTION == 15
2187  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0020u << BITP_ADC_AVG_CFG_FACTOR);
2188 #elif ADI_ADC_CFG_RESOLUTION == 16
2189  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0080u << BITP_ADC_AVG_CFG_FACTOR);
2190 #else
2191 #error "Invalid Resolution"
2192 #endif
2193 
2194  SET_STATE(ADC_STATUS_OVERSAMPLING_EN);
2195 #endif
2196 
2197  /* Configure the VREF */
2198 #if ADI_ADC_CFG_VREF == 0 /* 1.25V Internal Reference*/
2199  nCfgReg |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
2200 #elif ADI_ADC_CFG_VREF == 1 /* 2.5V Internal Reference */
2201  nCfgReg |= BITM_ADC_CFG_REFBUFEN;
2202 #elif ADI_ADC_CFG_VREF == 2 /* Battery Voltage */
2203  nCfgReg |= BITM_ADC_CFG_VREFVBAT;
2204 #endif
2205 
2206  pDevice->pReg->CFG = nCfgReg;
2207 
2208 #if ADI_ADC_ENABLE_STATIC_COMPARATOR == 1
2209  /* High limit registers */
2210 #if ADI_ADC_COMPARATOR_AIN0_HI_EN == 1
2211  pDevice->pReg->LIM0_HI = ADI_ADC_COMPARATOR_AIN0_HI_VAL;
2212  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_0;
2213 #endif
2214 #if ADI_ADC_COMPARATOR_AIN1_HI_EN == 1
2215  pDevice->pReg->LIM1_HI = ADI_ADC_COMPARATOR_AIN1_HI_VAL;
2216  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_1;
2217 #endif
2218 #if ADI_ADC_COMPARATOR_AIN2_HI_EN == 1
2219  pDevice->pReg->LIM2_HI = ADI_ADC_COMPARATOR_AIN2_HI_VAL;
2220  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_2;
2221 #endif
2222 #if ADI_ADC_COMPARATOR_AIN3_HI_EN == 1
2223  pDevice->pReg->LIM3_HI = ADI_ADC_COMPARATOR_AIN3_HI_VAL;
2224  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_3;
2225 #endif
2226  /* Low limit registers */
2227 #if ADI_ADC_COMPARATOR_AIN0_LO_EN == 1
2228  pDevice->pReg->LIM0_LO = (uint16_t)ADI_ADC_COMPARATOR_AIN0_LO_VAL;
2229  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_0;
2230 #endif
2231 #if ADI_ADC_COMPARATOR_AIN1_LO_EN == 1
2232  pDevice->pReg->LIM1_LO = ADI_ADC_COMPARATOR_AIN1_LO_VAL;
2233  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_1;
2234 #endif
2235 #if ADI_ADC_COMPARATOR_AIN2_LO_EN == 1
2236  pDevice->pReg->LIM2_LO = ADI_ADC_COMPARATOR_AIN2_LO_VAL;
2237  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_2;
2238 #endif
2239 #if ADI_ADC_COMPARATOR_AIN3_LO_EN == 1
2240  pDevice->pReg->LIM3_LO = ADI_ADC_COMPARATOR_AIN3_LO_VAL;
2241  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_3;
2242 #endif
2243 
2244  /* Hysteresis registers */
2245 #if ADI_ADC_COMPARATOR_AIN0_HYS_EN == 1
2246  pDevice->pReg->HYS0 = (uint16_t)(ADI_ADC_COMPARATOR_AIN0_HYS_VAL | (ADI_ADC_COMPARATOR_AIN0_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2247  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_0;
2248 #endif
2249 #if ADI_ADC_COMPARATOR_AIN1_HYS_EN == 1
2250  pDevice->pReg->HYS1 = (ADI_ADC_COMPARATOR_AIN1_HYS_VAL | (ADI_ADC_COMPARATOR_AIN1_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2251  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_1;
2252 #endif
2253 #if ADI_ADC_COMPARATOR_AIN2_HYS_EN == 1
2254  pDevice->pReg->HYS2 = (ADI_ADC_COMPARATOR_AIN2_HYS_VAL | (ADI_ADC_COMPARATOR_AIN2_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2255  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_2;
2256 #endif
2257 #if ADI_ADC_COMPARATOR_AIN3_HYS_EN == 1
2258  pDevice->pReg->HYS3 = (ADI_ADC_COMPARATOR_AIN3_HYS_VAL | (ADI_ADC_COMPARATOR_AIN3_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2259  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_3;
2260 #endif
2261 #endif
2262 
2263 }
2264 
2265 /* Internal function to enable the comparitor for previously-configured channels
2266  * Does not set the limits, only enables.
2267 */
2268 static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable)
2269 {
2270  uint32_t x;
2271  uint16_t nCnvCfg = 0u;
2272  volatile uint16_t* pLO_Register[4] = {pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO};
2273  volatile uint16_t* pHI_Register[4] = {pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI};
2274  volatile uint16_t* pHYS_Register[4] = {pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3};
2275 
2276  if (bEnable == true)
2277  {
2278  /* Loop round all the channels enabling each part if required. */
2279  for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
2280  if((pDevice->ComparitorHi & (1u << x)) > 0u) {
2281  *pHI_Register[x] |= BITM_ADC_LIM0_HI_EN;
2282  }
2283  if((pDevice->ComparitorLo & (1u << x)) > 0u) {
2284  *pLO_Register[x] |= BITM_ADC_LIM0_LO_EN;
2285  }
2286  if((pDevice->ComparitorHys & (1u << x)) > 0u) {
2287  *pHYS_Register[x] |= BITM_ADC_HYS0_EN;
2288  }
2289  }
2290  nCnvCfg = (uint16_t)((uint16_t)pDevice->ComparitorHi | (uint16_t)pDevice->ComparitorLo);
2291 
2292  pDevice->pReg->IRQ_EN &= (uint16_t)(~BITM_ADC_IRQ_EN_CNVDONE);
2293  pDevice->pReg->CNV_CFG = (uint16_t)nCnvCfg | (uint16_t)(BITM_ADC_CNV_CFG_MULTI | BITM_ADC_CNV_CFG_AUTOMODE);
2294  SET_STATE(ADC_STATUS_COMPARATOR_EN);
2295  }
2296  else {
2297  /* Loop round disabling all. */
2298  for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
2299  *pHI_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_HI_EN));
2300  *pLO_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_LO_EN));
2301  *pHYS_Register[x] &= (uint16_t)(~(BITM_ADC_HYS0_EN));
2302  }
2303  pDevice->pReg->CNV_CFG = 0u;
2304  pDevice->pReg->STAT = pDevice->pReg->STAT & 0x00FFu;
2305  CLR_STATE(ADC_STATUS_COMPARATOR_EN);
2306  pDevice->pReg->IRQ_EN |= BITM_ADC_IRQ_EN_CNVDONE;
2307  }
2308 }
2309 
2310 
2311 /* In Handler handles the following cases:
2312  * ADI_ADC_EVENT_ADC_READY
2313  * ADI_ADC_EVENT_CALIBRATION_DONE
2314  * ADC_STATUS_BATTERY_DONE
2315  * ADC_STATUS_TMP_DONE
2316  * ADC_STATUS_TMP2_DONE
2317  * ADI_ADC_EVENT_HIGH_LIMIT_CROSSED
2318  * ADI_ADC_EVENT_LOW_LIMIT_CROSSED
2319 */
2320 #if defined(__ADUCM302x__)
2321 void ADC_Int_Handler(void)
2322 #else
2323 void ADC0_Int_Handler(void)
2324 #endif
2325 {
2326  ADI_ADC_DEVICE *pDevice;
2327  ISR_PROLOG();
2328 
2329  pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
2330 
2331  if ((pDevice->pReg->STAT & 0x00FFu) != 0u) {
2332  if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
2333  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_PROCESS);
2334  } else {
2335  pDevice->pReg->STAT = pDevice->pReg->STAT & (0x00FFu);
2336  }
2337  }
2338  if ((uint16_t)(pDevice->pReg->STAT & 0xFF00u) != 0u) {
2339  if ((pDevice->pReg->STAT & BITM_ADC_STAT_RDY) != 0u) {
2340  SET_STATE(ADC_STATUS_SUB_SYSTEM_READY);
2341  pDevice->pReg->STAT = BITM_ADC_STAT_RDY;
2342  if (pDevice->pfCallback != NULL) {
2343  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_ADC_READY, NULL);
2344  }
2345  }
2346  if ((pDevice->pReg->STAT & BITM_ADC_STAT_CALDONE) != 0u) {
2347  SET_STATE(ADC_STATUS_CALIBRATION_DONE);
2348  pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
2349  if (pDevice->pfCallback != NULL) {
2350  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_CALIBRATION_DONE, NULL);
2351  }
2352  }
2353  if ((pDevice->pReg->STAT & BITM_ADC_STAT_BATDONE) != 0u) {
2354  SET_STATE(ADC_STATUS_BATTERY_DONE);
2355  pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
2356  }
2357 
2358  if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMPDONE) != 0u) {
2359  SET_STATE(ADC_STATUS_TMP_DONE);
2360  pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE;
2361  }
2362 
2363  if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMP2DONE) != 0u) {
2364  SET_STATE(ADC_STATUS_TMP2_DONE);
2365  pDevice->pReg->STAT = BITM_ADC_STAT_TMP2DONE;
2366  }
2367  }
2368  if (pDevice->pReg->OVF) {
2369  uint16_t nOvrFlowValue = pDevice->pReg->OVF;
2370  if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
2371  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_OVERFLOW);
2372  }
2373  pDevice->pReg->OVF = nOvrFlowValue;
2374  }
2375  if (pDevice->pReg->ALERT) {
2376  uint32_t nAlertValue = pDevice->pReg->ALERT;
2377  uint32_t channel;
2378  if (IS_IN_STATE(ADC_STATUS_COMPARATOR_EN) && (pDevice->pfCallback != NULL)) {
2379  for (channel = 0u; channel < (NUM_ADC_COMPARATOR_CHANNELS); channel++) {
2380  /* Alert bit positions: hi limits are 0b01,
2381  * lo limit alerts are 0b10.
2382  */
2383  if((nAlertValue & (1u << (2u * channel))) > 0u) {
2384  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, (void*)channel);
2385  }
2386  if((nAlertValue & (1u << ((2u * channel) + ((uint32_t)1u)))) > 0u)
2387  {
2388  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_LOW_LIMIT_CROSSED, (void*)channel);
2389  }
2390  }
2391  }
2392  pDevice->pReg->ALERT = (uint16_t)nAlertValue;
2393  }
2394  ISR_EPILOG();
2395 }
2396 
2397 
2400 #endif /* ADI_ADC_C */
2401 
2402 /*****/
2403 
#define ADI_ADC_COMPARATOR_AIN1_LO_VAL
ADI_ADC_RESULT adi_adc_Close(ADI_ADC_HANDLE hDevice)
Close the given device instance.
Definition: adi_adc.c:224
ADI_ADC_RESULT adi_adc_SetLowLimit(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, bool bEnable, uint16_t nLowLimit)
Configure low limit for an ADC channel when it is used as a digital comparator.
Definition: adi_adc.c:938
ADI_ADC_RESULT adi_adc_IsCalibrationDone(ADI_ADC_HANDLE hDevice, bool *pbCalibrationDone)
Returns the status of the calibration which was initiated.
Definition: adi_adc.c:670
ADI_ADC_RESULT adi_adc_EnableIRQ(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable/Disable ADC Interrupts.
Definition: adi_adc.c:1536
ADI_ADC_RESULT adi_adc_EnableTemperatureSensor(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable or disable the temperature sensor.
Definition: adi_adc.c:1678
ADI_ADC_RESULT adi_adc_EnableAveraging(ADI_ADC_HANDLE hDevice, uint16_t nAveragingSamples)
Enable Averaging for all ADC channels.
Definition: adi_adc.c:880
#define ADI_ADC_COMPARATOR_AIN1_HI_VAL
#define ADI_ADC_CHANNEL_0
Definition: adi_adc.h:92
#define ADI_ADC_COMPARATOR_AIN2_LO_VAL
ADI_ADC_RESULT adi_adc_SetHysteresis(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, bool bEnable, uint16_t nHysteresis)
Configure hysteresis for an ADC channel when it's used as a digital comparator.
Definition: adi_adc.c:1054
uint32_t ADI_ADC_CHANNEL
Definition: adi_adc.h:87
ADI_ADC_RESULT adi_adc_ReadChannels(ADI_ADC_HANDLE hDevice, uint32_t nChannels, uint32_t nNumConversionPasses, void *pBuffer, uint32_t nBuffLength)
Sample the given channels for the given number of conversion passes and put it into the given buffer....
Definition: adi_adc.c:1448
#define ADI_ADC_COMPARATOR_AIN3_HYS_CYC
ADI_ADC_RESULT adi_adc_SinkEnable(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable/Disable Current Sink.
Definition: adi_adc.c:583
ADI_ADC_RESULT adi_adc_Open(uint32_t nDeviceNum, void *pMemory, uint32_t nMemorySize, ADI_ADC_HANDLE *phDevice)
Opens an ADC device instance.
Definition: adi_adc.c:148
#define ADI_ADC_COMPARATOR_AIN1_HYS_VAL
ADI_ADC_RESULT adi_adc_SetDelayTime(ADI_ADC_HANDLE hDevice, uint32_t nDelayInAClkCycles)
Set the delay time of ADC in ADC cycles for multi iteration mode.
Definition: adi_adc.c:770
ADI_ADC_RESULT adi_adc_EnableADCSubSystem(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable/Disables the ADC Subsystem.
Definition: adi_adc.c:407
#define ADI_ADC_COMPARATOR_AIN0_HYS_CYC
ADI_ADC_RESULT adi_adc_SetNumMonitorCycles(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, uint32_t nNumMonitorCycles)
Configure number of monitor cycles for an ADC channel when it's used as a digital comparator.
Definition: adi_adc.c:1109
#define ADI_ADC_CHANNEL_3
Definition: adi_adc.h:95
ADI_ADC_VREF_SRC
Definition: adi_adc.h:64
ADI_ADC_RESULT adi_adc_PowerUp(ADI_ADC_HANDLE hDevice, bool bPowerUp)
Power up ADC.
Definition: adi_adc.c:278
#define ADI_ADC_COMPARATOR_AIN0_LO_VAL
ADI_ADC_RESULT adi_adc_GetBuffer(ADI_ADC_HANDLE hDevice, ADI_ADC_BUFFER **ppBuffer)
Get a processed buffer from the ADC Driver. This function is a blocking call and will only return onc...
Definition: adi_adc.c:1279
ADI_ADC_RESULT adi_adc_GetBatteryVoltage(ADI_ADC_HANDLE hDevice, uint32_t nRefVoltage, uint32_t *pnBatVoltage)
Returns the battery voltage.
Definition: adi_adc.c:1585
ADI_ADC_RESULT adi_adc_SetHighLimit(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, bool bEnable, uint16_t nHighLimit)
Configure high limit for an ADC channel when it's used as a digital comparator.
Definition: adi_adc.c:997
void * pDataBuffer
Definition: adi_adc.h:116
#define ADI_ADC_COMPARATOR_AIN2_HYS_CYC
#define ADI_ADC_COMPARATOR_AIN3_HYS_VAL
#define ADI_ADC_COMPARATOR_AIN3_HI_VAL
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
Definition: adi_pwr.c:435
#define ADI_ADC_MEMORY_SIZE
Definition: adi_adc.h:34
ADI_ADC_RESULT adi_adc_IsBufferAvailable(ADI_ADC_HANDLE hDevice, bool *pbIsBufferAvailable)
This function return whether a filled buffer is available to be returned to the user....
Definition: adi_adc.c:1388
uint32_t nNumConversionPasses
Definition: adi_adc.h:126
#define ADI_ADC_CHANNEL_1
Definition: adi_adc.h:93
#define ADI_ADC_COMPARATOR_AIN0_HI_VAL
#define ADI_ADC_COMPARATOR_AIN2_HI_VAL
#define ADI_ADC_COMPARATOR_AIN3_LO_VAL
#define ADI_ADC_COMPARATOR_AIN1_HYS_CYC
ADI_ADC_RESULT adi_adc_SetAcquisitionTime(ADI_ADC_HANDLE hDevice, uint32_t nAcqTimeInAClkCycles)
Set the acquisition time of ADC in ADC clock cycles.
Definition: adi_adc.c:722
ADI_ADC_RESULT adi_adc_SetResolution(ADI_ADC_HANDLE hDevice, ADI_ADC_RESOLUTION eResolution)
Set the resolution of ADC. he default resolution of ADC is 12-bit and the ADC increases the resolutio...
Definition: adi_adc.c:812
ADI_ADC_RESULT adi_adc_SubmitBuffer(ADI_ADC_HANDLE hDevice, ADI_ADC_BUFFER *pBuffer)
Submit the ADC buffer for processing to the ADC Module.
Definition: adi_adc.c:1216
ADI_ADC_RESULT adi_adc_Enable(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable/Disable ADC for sampling.
Definition: adi_adc.c:1333
#define ADI_ADC_COMPARATOR_AIN0_HYS_VAL
ADI_ADC_RESULT adi_adc_IsReady(ADI_ADC_HANDLE hDevice, bool *pbReady)
Returns whether the ADC Subsystem is ready.
Definition: adi_adc.c:469
ADI_ADC_RESULT adi_adc_GetTemperature(ADI_ADC_HANDLE hDevice, uint32_t nRefVoltage, int32_t *pnTemperature)
Return the temperature in fixed point format in degree Celcius.
Definition: adi_adc.c:1729
void adi_dma_Init(void)
Initialize the DMA peripheral.
Definition: adi_dma.c:155
uint32_t nChannels
Definition: adi_adc.h:115
struct __ADI_ADC_DEVICE * ADI_ADC_HANDLE
Definition: adi_adc.h:131
ADI_ADC_RESULT adi_adc_RegisterCallback(ADI_ADC_HANDLE hDevice, ADI_CALLBACK pfCallback, void *pCBParam)
Registering a callback function.
Definition: adi_adc.c:358
#define ADI_ADC_COMPARATOR_AIN2_HYS_VAL
ADI_ADC_RESULT adi_adc_EnableDigitalComparator(ADI_ADC_HANDLE hDevice, bool bEnableComparator)
Enable/Disable digital comparator for the given channel(s)
Definition: adi_adc.c:1161
ADI_ADC_RESULT
Definition: adi_adc.h:41
#define ADI_ADC_CHANNEL_2
Definition: adi_adc.h:94
ADI_ADC_RESULT adi_adc_SetVrefSource(ADI_ADC_HANDLE hDevice, ADI_ADC_VREF_SRC eVrefSrc)
Set the Voltage Reference source.
Definition: adi_adc.c:521
ADI_ADC_RESOLUTION
Definition: adi_adc.h:75
ADI_ADC_RESULT adi_adc_StartCalibration(ADI_ADC_HANDLE hDevice)
Start the ADC calibration.
Definition: adi_adc.c:622