ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_pwr_def.h
1 /*
2  *****************************************************************************
3  * @file: adi_pwr_def.h
4  * @brief: Definitions for the system clock and power management.
5  *-----------------------------------------------------------------------------
6  *
7  * Copyright (c) 2016-2017 Analog Devices, Inc.
8  *
9  * All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without modification,
12  * are permitted provided that the following conditions are met:
13  * - Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  * - Redistributions in binary form must reproduce the above copyright notice,
16  * this list of conditions and the following disclaimer in the documentation
17  * and/or other materials provided with the distribution.
18  * - Modified versions of the software must be conspicuously marked as such.
19  * - This software is licensed solely and exclusively for use with processors
20  * manufactured by or for Analog Devices, Inc.
21  * - This software may not be combined or merged with other code in any manner
22  * that would cause the software to become subject to terms and conditions
23  * which differ from those listed here.
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25  * contributors may be used to endorse or promote products derived
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31  *
32  * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
33  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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43  *
44  *****************************************************************************/
45 
46 #ifndef ADI_PWR_DEF_H
47 #define ADI_PWR_DEF_H
48 
49  /*Power control register access key */
50 #define ADI_PMG_KEY (0x4859u)
51 
52  /*Osc control register access key */
53 #define ADI_OSC_KEY (0xCB14u)
54 
55  /*HCLK/PCLK minimum Divider value */
56 #define CLOCK_MIN_DIV_VALUE (0x1u)
57 
58  /*HCLK/PCLK maximum Divider value */
59 #define CLOCK_MAX_DIV_VALUE (32u)
60 
61  /*ADC Clock minimum Divider value */
62 #define ACLK_MIN_DIV_VALUE (0x1u)
63 
64  /*ADC Clock maximum Divider value */
65 #define ACLK_MAX_DIV_VALUE (511u)
66 
67 /* Minimum divider for PLL */
68 #define MINIMUM_PLL_DIVIDER (0x02u)
69 
70 /* Minimum multiplier for PLL */
71 #define MINIMUM_PLL_MULTIPLIER (0x08u)
72 
73 /* Maximum external clock */
74 #define MAXIMUM_EXT_CLOCK (26000000u)
75 
76 /* Macro mapping from ADuCM4x50 to ADuCM302x */
77 #if defined(__ADUCM302x__)
78 
79 #define BITM_CLKG_OSC_CTL_HFOSC_EN BITM_CLKG_OSC_CTL_HFOSCEN
80 #define BITP_CLKG_OSC_CTL_HFOSC_OK BITP_CLKG_OSC_CTL_HFOSCOK
81 #define BITM_CLKG_OSC_CTL_HFX_EN BITM_CLKG_OSC_CTL_LFXTALEN
82 #define BITM_CLKG_CLK_CTL0_PLL_IPSEL BITM_CLKG_CLK_CTL0_SPLLIPSEL
83 #define BITP_CLKG_CLK_CTL0_PLL_IPSEL BITP_CLKG_CLK_CTL0_SPLLIPSEL
84 #define BITM_CLKG_OSC_CTL_LFCLK_MUX BITM_CLKG_OSC_CTL_LFCLKMUX
85 #define BITP_CLKG_OSC_CTL_LFCLK_MUX BITP_CLKG_OSC_CTL_LFCLKMUX
86 #define BITP_CLKG_OSC_CTL_HFX_EN BITP_CLKG_OSC_CTL_HFXTALEN
87 #define BITM_CLKG_OSC_CTL_HFX_OK BITM_CLKG_OSC_CTL_HFXTALOK
88 #define BITP_CLKG_OSC_CTL_LFX_EN BITP_CLKG_OSC_CTL_LFXTALEN
89 #define BITM_CLKG_OSC_CTL_LFX_EN BITM_CLKG_OSC_CTL_LFXTALEN
90 #define BITM_CLKG_OSC_CTL_LFX_OK BITM_CLKG_OSC_CTL_LFXTALOK
91 #define BITP_CLKG_OSC_CTL_HFOSC_EN BITP_CLKG_OSC_CTL_HFOSCEN
92 #define BITM_CLKG_OSC_CTL_HFOSC_OK BITM_CLKG_OSC_CTL_HFOSCOK
93 #define BITM_CLKG_OSC_CTL_LFOSC_OK BITM_CLKG_OSC_CTL_LFOSCOK
94 #define BITM_CLKG_OSC_CTL_LFX_BYP BITM_CLKG_OSC_CTL_LFXTAL_BYPASS
95 
96 #endif /* __ADUCM302x__ */
97 
98 #if defined(__ADUCM4x50__)
99  /* Default osc control register value
100  * LFXTAL ROBUST MODE has to be enabled (system clock anomaly)
101  * LFXTAL ROBUST LOAD has to be 0b11 (system clock anomaly)
102  */
103 #define OSCCTRL_CONFIG_VALUE \
104  ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLK_MUX | \
105  (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSC_EN | \
106  (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFX_EN | \
107  (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFX_EN | \
108  (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFX_MON_EN | \
109  (uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN | \
110  (uint32_t) 1 << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN | \
111  (uint32_t) 3 << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD | \
112  (uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE << BITP_CLKG_OSC_CTL_ROOT_MON_EN | \
113  (uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN )
114 #else
115 
116  /* Default osc control register value */
117 #define OSCCTRL_CONFIG_VALUE \
118  ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLKMUX | \
119  (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSCEN | \
120  (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFXTALEN | \
121  (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFXTALEN | \
122  (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFXTAL_MON_EN )
123 #endif /* __ADUCM4x50__ */
124 
125 #if defined(__ADUCM4x50__)
126  /* Default clock control register-0 value */
127 #define CLOCK_CTL0_CONFIG_VALUE \
128  ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \
129  (uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT << BITP_CLKG_CLK_CTL0_CLKOUT | \
130  (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \
131  (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_PLL_IPSEL | \
132  (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \
133  (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE )
134 #else
135 /* Default clock control register-0 value */
136 #define CLOCK_CTL0_CONFIG_VALUE \
137  ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \
138  (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \
139  (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_SPLLIPSEL | \
140  (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \
141  (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE )
142 #endif
143 
144  /* Default clock control register-1 value */
145 #define CLOCK_CTL1_CONFIG_VALUE \
146  ( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_HCLKDIVCNT | \
147  (uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_PCLKDIVCNT | \
148  (uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_ACLKDIVCNT )
149 
150 #if defined(__ADUCM4x50__)
151 /* Default clock control register-2 value */
152 #define CLOCK_CTL2_CONFIG_VALUE \
153  ( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1 << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN | \
154  (uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL )
155 
156 #endif /* __ADUCM4x50__ */
157 
158  /* Default clock control register-3 value */
159 #define CLOCK_CTL3_CONFIG_VALUE \
160  ( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR << BITP_CLKG_CLK_CTL3_SPLLNSEL | \
161  (uint32_t) ADI_PWR_SPLL_ENABLE_DIV2 << BITP_CLKG_CLK_CTL3_SPLLDIV2 | \
162  (uint32_t) ADI_PWR_SPLL_ENABLE << BITP_CLKG_CLK_CTL3_SPLLEN | \
163  (uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL3_SPLLIE | \
164  (uint32_t) ADI_PWR_SPLL_DIV_FACTOR << BITP_CLKG_CLK_CTL3_SPLLMSEL | \
165  (uint32_t) ADI_PWR_SPLL_ENABLE_MUL2 << BITP_CLKG_CLK_CTL3_SPLLMUL2 )
166 
167 #if defined(__ADUCM4x50__)
168  /* Default clock control register-5 value */
169 #define CLOCK_CTL5_CONFIG_VALUE \
170  ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \
171  (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \
172  (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \
173  (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \
174  (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \
175  (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF | \
176  (uint32_t) ADI_PWR_TIMER_RGB_ENABLE << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF )
177 #else
178  /* Default clock control register-5 value */
179 #define CLOCK_CTL5_CONFIG_VALUE \
180  ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \
181  (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \
182  (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \
183  (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \
184  (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \
185  (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF )
186 #endif
187 
188 /* Default configuration for Power supply monitor Interrupt Enable Register */
189 #define PWM_INTERRUPT_CONFIG \
190  ( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT << BITP_PMG_IEN_VBAT | \
191  (uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGUNDR | \
192  (uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGOVR | \
193  (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT << BITP_PMG_IEN_IENBAT | \
194  (uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT << BITP_PMG_IEN_RANGEBAT )
195 
196  /* Default configuration for Power Mode Register */
197  #define PWM_PWRMOD_CONFIG \
198  ( (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING << BITP_PMG_PWRMOD_MONVBATN )
199 
200 #if defined(__ADUCM4x50__)
201 /* Default configuration for HP Buck Control register */
202 #define PWM_HPBUCK_CONTROL \
203  ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN | \
204  (uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE << BITP_PMG_CTL1_HPBUCK_LD_MODE | \
205  (uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE )
206 #else
207 /* Default configuration for HP Buck Control register */
208 #define PWM_HPBUCK_CONTROL \
209  ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN )
210 #endif
211 
212  /*Selecting HFOSC as input for generating root clock*/
213 #define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX)
214 
215  /*Selecting HFXTAL as input for generating root clock*/
216 #define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX)
217 
218  /*Selecting SPLL as input for generating root clock*/
219 #define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX)
220 
221  /*Selecting GPIO as input for generating root clock*/
222 #define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX)
223 
224 /* Interrupt handler for the battery voltage interrupt */
225 void Battery_Voltage_Int_Handler(void);
226 /* Interrupt handler for the VREG under/over voltage interrupt */
227 void Vreg_over_Int_Handler(void);
228 /* Interrupt handler for PLL interrupts. */
229 void PLL_Int_Handler(void);
230 /*Interrupt handler for oscillator interrupts.*/
231 void Crystal_osc_Int_Handler(void);
232 
233 #endif /* ADI_PWR_DEF_H */
234 
235 
236 /*
237 ** EOF
238 */