ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
system_ADuCM3027.c
1 
13 /* Copyright (c) 2012 ARM LIMITED
14 
15  All rights reserved.
16  Redistribution and use in source and binary forms, with or without
17  modification, are permitted provided that the following conditions are met:
18  - Redistributions of source code must retain the above copyright
19  notice, this list of conditions and the following disclaimer.
20  - Redistributions in binary form must reproduce the above copyright
21  notice, this list of conditions and the following disclaimer in the
22  documentation and/or other materials provided with the distribution.
23  - Neither the name of ARM nor the names of its contributors may be used
24  to endorse or promote products derived from this software without
25  specific prior written permission.
26  *
27  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
31  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  POSSIBILITY OF SUCH DAMAGE.
38 
39  Portions Copyright (c) 2018 Analog Devices, Inc.
40  ---------------------------------------------------------------------------*/
41 
46 #include <stdint.h>
47 #include "system_ADuCM3027.h"
48 #include <adi_callback.h>
49 #include <adi_processor.h>
50 #include <rtos_map/adi_rtos_map.h>
51 
52 #ifdef __ICCARM__
53 /*
54 * IAR MISRA C 2004 error suppressions.
55 *
56 * Pm073 (rule 14.7): a function should have a single point of exit.
57 * Pm143 (rule 14.7): a function should have a single point of exit at the end of the function.
58 * Multiple returns are used for error handling.
59 *
60 * Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
61 * The rule makes an exception for memory-mapped register accesses.
62 */
63 #pragma diag_suppress=Pm073,Pm143,Pm140
64 #endif /* __ICCARM__ */
65 
66 
69 /*----------------------------------------------------------------------------
70  DEFINES
71  *----------------------------------------------------------------------------*/
72 
73 /* To enable the cache. Please note that linker description file need to
74  have appropriate memory mapping. */
75 /* #define ENABLE_CACHE */
76 
77 
78 #ifdef ADI_DEBUG
79 
81 uint32_t lfClock = 0u;
82 #endif
83 
85 uint32_t hfClock = 0u;
86 
88 uint32_t gpioClock = 0u;
89 #ifdef RELOCATE_IVT
90 extern void* __Vectors[];
91 #else
92 extern uint32_t __Vectors[];
93 #endif
94 
95 /*----------------------------------------------------------------------------
96  Security options
97  *----------------------------------------------------------------------------*/
98 
99 #if defined (__CC_ARM)
100  __attribute__ ((at(0x00000180u)))
101 #elif defined (__GNUC__)
102  __attribute__ ((section(".security_options")))
103 #elif defined (__ICCARM__)
104  #pragma location=".security_options"
105  __root
106  __weak
107 #endif /* __ICCARM__ */
108 const ADI_ADUCM302X_SECURITY_OPTIONS adi_aducm302x_security_options
109  = {
110  { 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu },
111  0xA79C3203u,
112  127u,
113  0xFFFFFFFFu,
114  0xFFFFFFFFu,
115 };
116 
120 /*----------------------------------------------------------------------------
121  Clock Variable definitions
122  *----------------------------------------------------------------------------*/
123 
125 uint32_t SystemCoreClock = 0u;
126 
127 /*----------------------------------------------------------------------------
128  Clock functions
129  *----------------------------------------------------------------------------*/
130 
140 {
141  uint32_t val, nDivisor, nMulfactor, div2, mul2;
142 
143 #ifdef ADI_DEBUG
144  /* "lfclock" is only used during debug checks... */
145  /* LF clock is always 32k, whether osc or xtal */
146  lfClock = __LFCLK; /* for beep, wdt and lcd */
147  if (lfClock == 0u)
148  {
149  while (1) {}
150  }
151 #endif
152  /* Update Core Clock sources */
153  /* update the HF clock */
154  switch (pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) {
155 
156  case HFMUX_INTERNAL_OSC_VAL:
157  hfClock = __HFOSC;
158  break;
159 
160  case HFMUX_EXTERNAL_XTAL_VAL:
161  hfClock = __HFXTAL;
162  break;
163 
164  case HFMUX_SYSTEM_SPLL_VAL:
165  /* Calculate System PLL output frequency */
166  if ((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_SPLLIPSEL) != 0u) {
167  /* PLL input from HFXTAL */
168  val = __HFXTAL;
169  } else {
170  /* PLL input from HFOSC */
171  val = __HFOSC;
172  }
173 
174  /* PLL NSEL multiplier */
175  nMulfactor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLNSEL) >> BITP_CLKG_CLK_CTL3_SPLLNSEL;
176  /* PLL MSEL divider */
177  nDivisor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL) >> BITP_CLKG_CLK_CTL3_SPLLMSEL;
178 
179  /* PLL NSEL multiplier */
180  mul2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2) >> BITP_CLKG_CLK_CTL3_SPLLMUL2;
181  /* PLL MSEL divider */
182  div2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2) >> BITP_CLKG_CLK_CTL3_SPLLDIV2;
183 
184  val = ((val << mul2) * nMulfactor / nDivisor) >> div2;
185 
186  hfClock = val;
187  break;
188 
189  case HFMUX_GPIO_VAL:
190  hfClock = gpioClock;
191  break;
192 
193  default:
194  return;
195  } /* end switch */
196 
197  SystemCoreClock = hfClock;
198  }
199 
200 #ifdef __ARMCC_VERSION
201 /* We want a warning if semi-hosting libraries are used. */
202 #pragma import(__use_no_semihosting_swi)
203 #endif
204 
205 #ifdef RELOCATE_IVT
206 
218 #define ADI_NUM_EXCEPTIONS 16
219 #define LENGTHOF_IVT (NVIC_INTS + ADI_NUM_EXCEPTIONS)
220 #define RELOCATION_ADDRESS (0x20000000)
221 
222 /* Relocatable vector table is only supported in IAR */
223 #if defined (__ICCARM__)
224 /* reserve no-init aligned IVT space at top of RAM */
225 SECTION_PLACE(KEEP_VAR(__no_init uint32_t __relocated_vector_table[LENGTHOF_IVT]), RELOCATION_ADDRESS);
226 #else
227 #warning "Relocated Interupt Vector Tables are not supported in this toolchain"
228 #endif
229 #endif
230 
238 void SystemInit (void)
239 {
240  uint32_t IntStatus;
241 
242  /* Enable Bank0 and 1 SRAM retention. */
244 
245 
246  /* To enable the instruction cache. */
247 #ifdef ENABLE_CACHE
248  adi_system_EnableCache(true);
249 #endif
250 
251  /* Switch the Interrupt Vector Table Offset Register
252  * (VTOR) to point to the relocated IVT in SRAM.
253  */
254 
255  /* Because SystemInit must not use global variables, the following
256  * interrupt disabling code should not be replaced with critical region
257  * code which uses global variables.
258  */
259  IntStatus = __get_PRIMASK();
260  __disable_irq();
261 #ifdef RELOCATE_IVT
262  /* Copy the IVT (avoid use of memcpy here so it does not become locked into flash). */
263  size_t i;
264  for (i = 0u; i < LENGTHOF_IVT; i++)
265  {
266  __relocated_vector_table[i] = (uint32_t )__Vectors[i];
267  }
268  SCB->VTOR = (uint32_t) &__relocated_vector_table;
269 #else
270  /* Set the vector table address */
271  SCB->VTOR = (uint32_t) &__Vectors;
272 #endif /* RELOCATE_IVT */
273 
274  /* Set all three (USGFAULTENA, BUSFAULTENA, and MEMFAULTENA) fault enable bits
275  * in the System Control Block, System Handler Control and State Register
276  * otherwise these faults are handled as hard faults.
277  */
278  SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk |
279  SCB_SHCSR_BUSFAULTENA_Msk |
280  SCB_SHCSR_MEMFAULTENA_Msk ;
281 
282  /* Flush instruction and data pipelines to insure assertion of new settings. */
283  __ISB();
284  __DSB();
285 
286  __set_PRIMASK(IntStatus);
287 }
288 
299 void adi_system_EnableCache(bool bEnable)
300 {
301  pADI_FLCC0_CACHE->KEY = CACHE_CONTROLLER_KEY;
302 
303  if(bEnable == true)
304  {
305  pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN;
306  }
307  else
308  {
309  pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN;
310  }
311 }
312 
313 
327 uint32_t adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable)
328 {
329 #ifdef ADI_DEBUG
330  if((eBank != ADI_SRAM_BANK_1) && (eBank != ADI_SRAM_BANK_2))
331  {
332  return 1u;
333  }
334 
335 #endif
336  pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY;
337  if(bEnable == true)
338  {
339  pADI_PMG0->SRAMRET |= (uint32_t)eBank>>1;
340  }
341  else
342  {
343  pADI_PMG0->SRAMRET &= ~((uint32_t)eBank >> 1);
344  }
345 
346  return 0u;
347 }
348 
void SystemInit(void)
Sets up the microcontroller system. Initializes the System and updates the relocate vector table...
void SystemCoreClockUpdate(void)
Updates the variable SystemCoreClock and must be called whenever the core clock is changed during pro...
void adi_system_EnableCache(bool bEnable)
This enables or disables the cache.
uint32_t SystemCoreClock
#define ADI_SRAM_BANK_2
#define CACHE_CONTROLLER_KEY
uint32_t adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable)
This enables/disable SRAM retention during the hibernation.
#define PWRKEY_VALUE_KEY
#define ADI_SRAM_BANK_1
uint32_t ADI_SRAM_BANK