ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_tmr_config.h
1 
46 #ifndef ADI_TMR_CONFIG_H
47 #define ADI_TMR_CONFIG_H
48 
49 #include <adi_processor.h>
50 #include <adi_global_config.h>
51 
57 /*************************************************************
58  GP Timer 0 Configuration
59  *************************************************************/
60 
72 #define TMR0_CFG_COUNT_UP (0u)
73 
79 #define TMR0_CFG_MODE (1u)
80 
89 #define TMR0_CFG_PRESCALE_FACTOR (0u)
90 
98 #define TMR0_CFG_CLOCK_SOURCE (0u)
99 
105 #define TMR0_CFG_LOAD_VALUE (0x8F9Cu)
106 
113 #define TMR0_CFG_ASYNC_LOAD_VALUE (0x8F9Cu)
114 
120 #define TMR0_CFG_ENABLE_RELOADING (0u)
121 
126 #define TMR0_CFG_ENABLE_SYNC_BYPASS (0u)
127 
128 /*************************************************************
129  GP Timer 0 Event Configuration
130  *************************************************************/
131 
136 #define TMR0_CFG_ENABLE_EVENT_CAPTURE (1u)
137 
142 #define TMR0_CFG_ENABLE_PRESCALE_RESET (0u)
143 
149 #if defined(__ADUCM302x__)
150 #define TMR0_CFG_EVENT_CAPTURE (9u)
151 #elif defined(__ADUCM4x50__)
152 #define TMR0_CFG_EVENT_CAPTURE (27u)
153 #else
154 #error TMR is not ported for this processor
155 #endif
156 
157 /*************************************************************
158  GP Timer 0 PWM0 Configuration
159  *************************************************************/
160 
167 #define TMR0_CFG_ENABLE_PWM0_MATCH_MODE (1u)
168 
169 
174 #define TMR0_CFG_PWM0_IDLE_STATE (1u)
175 
176 
183 #define TMR0_CFG_PWM0_MATCH_VALUE (0x0E5Cu)
184 
188 /*************************************************************
189  GP Timer 1 Configuration
190  *************************************************************/
191 
203 #define TMR1_CFG_COUNT_UP (0u)
204 
210 #define TMR1_CFG_MODE (1u)
211 
220 #define TMR1_CFG_PRESCALE_FACTOR (0u)
221 
229 #define TMR1_CFG_CLOCK_SOURCE (0u)
230 
236 #define TMR1_CFG_LOAD_VALUE (0x23E7u)
237 
244 #define TMR1_CFG_ASYNC_LOAD_VALUE (0x23E7u)
245 
251 #define TMR1_CFG_ENABLE_RELOADING (0u)
252 
257 #define TMR1_CFG_ENABLE_SYNC_BYPASS (0u)
258 
259 
260 /*************************************************************
261  GP Timer 1 Event Configuration
262  *************************************************************/
263 
268 #define TMR1_CFG_ENABLE_EVENT_CAPTURE (1u)
269 
274 #define TMR1_CFG_ENABLE_PRESCALE_RESET (0u)
275 
281 #if defined(__ADUCM302x__)
282 #define TMR1_CFG_EVENT_CAPTURE (15u)
283 #elif defined(__ADUCM4x50__)
284 #define TMR1_CFG_EVENT_CAPTURE (28u)
285 #else
286 #error TMR is not ported for this processor
287 #endif
288 /*************************************************************
289  GP Timer 1 PWM0 Configuration
290  *************************************************************/
291 
298 #define TMR1_CFG_ENABLE_PWM0_MATCH_MODE (1u)
299 
300 
305 #define TMR1_CFG_PWM0_IDLE_STATE (1u)
306 
307 
314 #define TMR1_CFG_PWM0_MATCH_VALUE (0x08F9u)
315 
318 /*************************************************************
319  GP Timer 2 Configuration
320  *************************************************************/
321 
333 #define TMR2_CFG_COUNT_UP (0u)
334 
340 #define TMR2_CFG_MODE (1u)
341 
350 #define TMR2_CFG_PRESCALE_FACTOR (0u)
351 
359 #define TMR2_CFG_CLOCK_SOURCE (0u)
360 
366 #define TMR2_CFG_LOAD_VALUE (0x0E5Cu)
367 
374 #define TMR2_CFG_ASYNC_LOAD_VALUE (0x0E5Cu)
375 
381 #define TMR2_CFG_ENABLE_RELOADING (0u)
382 
387 #define TMR2_CFG_ENABLE_SYNC_BYPASS (0u)
388 
389 /*************************************************************
390  GP Timer 2 Event Configuration
391  *************************************************************/
392 
397 #define TMR2_CFG_ENABLE_EVENT_CAPTURE (1u)
398 
403 #define TMR2_CFG_ENABLE_PRESCALE_RESET (0u)
404 
410 #if defined(__ADUCM302x__)
411 #define TMR2_CFG_EVENT_CAPTURE (6u)
412 #elif defined(__ADUCM4x50__)
413 #define TMR2_CFG_EVENT_CAPTURE (27u)
414 #else
415 #error TMR is not ported for this processor
416 #endif
417 /*************************************************************
418  GP Timer 2 PWM0 Configuration
419  *************************************************************/
420 
427 #define TMR2_CFG_ENABLE_PWM0_MATCH_MODE (1u)
428 
429 
434 #define TMR2_CFG_PWM0_IDLE_STATE (1u)
435 
436 
443 #define TMR2_CFG_PWM0_MATCH_VALUE (0x02DFu)
444 
447 #if defined(__ADUCM4x50__)
448 /*************************************************************
449  RGB Timer Configuration
450  *************************************************************/
451 
463 #define TMR3_CFG_COUNT_UP (0u)
464 
470 #define TMR3_CFG_MODE (1u)
471 
480 #define TMR3_CFG_PRESCALE_FACTOR (0u)
481 
489 #define TMR3_CFG_CLOCK_SOURCE (0u)
490 
496 #define TMR3_CFG_LOAD_VALUE (0x47CEu)
497 
504 #define TMR3_CFG_ASYNC_LOAD_VALUE (0x47CEu)
505 
511 #define TMR3_CFG_ENABLE_RELOADING (0u)
512 
517 #define TMR3_CFG_ENABLE_SYNC_BYPASS (0u)
518 
519 /*************************************************************
520  RGB Timer Event Configuration
521  *************************************************************/
522 
527 #define TMR3_CFG_ENABLE_EVENT_CAPTURE (1u)
528 
533 #define TMR3_CFG_ENABLE_PRESCALE_RESET (0u)
534 
540 #define TMR3_CFG_EVENT_CAPTURE (28u)
541 
542 /*************************************************************
543  RGB Timer PWM0 Configuration
544  *************************************************************/
545 
552 #define TMR3_CFG_ENABLE_PWM0_MATCH_MODE (1u)
553 
554 
559 #define TMR3_CFG_PWM0_IDLE_STATE (1u)
560 
561 
568 #define TMR3_CFG_PWM0_MATCH_VALUE (0x23E7u)
569 
570 /*************************************************************
571  RGB Timer PWM1 Configuration
572  *************************************************************/
573 
580 #define TMR3_CFG_ENABLE_PWM1_MATCH_MODE (0u)
581 
582 
587 #define TMR3_CFG_PWM1_IDLE_STATE (0u)
588 
589 
596 #define TMR3_CFG_PWM1_MATCH_VALUE (0u)
597 
598 /*************************************************************
599  RGB Timer PWM2 Configuration
600  *************************************************************/
601 
608 #define TMR3_CFG_ENABLE_PWM2_MATCH_MODE (0u)
609 
610 
615 #define TMR3_CFG_PWM2_IDLE_STATE (0u)
616 
617 
624 #define TMR3_CFG_PWM2_MATCH_VALUE (0u)
625 
627 #endif
628 
629 /*************************************************************
630  GP Timer 0 Macro Validation
631 **************************************************************/
632 
633 #if TMR0_CFG_COUNT_UP > 1u
634 #error "Invalid configuration"
635 #endif
636 
637 #if TMR0_CFG_MODE > 1u
638 #error "Invalid configuration"
639 #endif
640 
641 #if TMR0_CFG_PRESCALE_FACTOR > 3u
642 #error "Invalid configuration"
643 #endif
644 
645 #if TMR0_CFG_CLOCK_SOURCE > 3u
646 #error "Invalid configuration"
647 #endif
648 
649 #if TMR0_CFG_LOAD_VALUE > 0xFFFFu
650 #error "Invalid configuration"
651 #endif
652 
653 #if TMR0_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
654 #error "Invalid configuration"
655 #endif
656 
657 #if TMR0_CFG_ENABLE_RELOADING > 1u
658 #error "Invalid configuration"
659 #endif
660 
661 #if TMR0_CFG_ENABLE_SYNC_BYPASS > 1u
662 #error "Invalid configuration"
663 #endif
664 
665 #if TMR0_CFG_ENABLE_PRESCALE_RESET > 1u
666 #error "Invalid configuration"
667 #endif
668 
669 #if TMR0_CFG_ENABLE_EVENT_CAPTURE > 1u
670 #error "Invalid configuration"
671 #endif
672 
673 #if defined(__ADUCM302x__)
674 #if TMR0_CFG_EVENT_CAPTURE > 15u
675 #error "Invalid configuration"
676 #endif
677 #elif defined(__ADUCM4x50__)
678 #if TMR0_CFG_EVENT_CAPTURE > 39u
679 #error "Invalid configuration"
680 #endif
681 #else
682 #error TMR is not ported for this processor
683 #endif
684 
685 #if TMR0_CFG_ENABLE_PWM0_MATCH_MODE > 1u
686 #error "Invalid configuration"
687 #endif
688 
689 #if TMR0_CFG_PWM0_IDLE_STATE > 1u
690 #error "Invalid configuration"
691 #endif
692 
693 #if TMR0_CFG_PWM0_MATCH_VALUE > 0xFFFFu
694 #error "Invalid configuration"
695 #endif
696 
697 /*************************************************************
698  GP Timer 1 Macro Validation
699 **************************************************************/
700 
701 #if TMR1_CFG_COUNT_UP > 1u
702 #error "Invalid configuration"
703 #endif
704 
705 #if TMR1_CFG_MODE > 1u
706 #error "Invalid configuration"
707 #endif
708 
709 #if TMR1_CFG_PRESCALE_FACTOR > 3u
710 #error "Invalid configuration"
711 #endif
712 
713 #if TMR1_CFG_CLOCK_SOURCE > 3u
714 #error "Invalid configuration"
715 #endif
716 
717 #if TMR1_CFG_LOAD_VALUE > 0xFFFFu
718 #error "Invalid configuration"
719 #endif
720 
721 #if TMR1_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
722 #error "Invalid configuration"
723 #endif
724 
725 #if TMR1_CFG_ENABLE_RELOADING > 1u
726 #error "Invalid configuration"
727 #endif
728 
729 #if TMR1_CFG_ENABLE_SYNC_BYPASS > 1u
730 #error "Invalid configuration"
731 #endif
732 
733 #if TMR1_CFG_ENABLE_PRESCALE_RESET > 1u
734 #error "Invalid configuration"
735 #endif
736 
737 #if TMR1_CFG_ENABLE_EVENT_CAPTURE > 1u
738 #error "Invalid configuration"
739 #endif
740 
741 #if defined(__ADUCM302x__)
742 #if TMR1_CFG_EVENT_CAPTURE > 15u
743 #error "Invalid configuration"
744 #endif
745 #elif defined(__ADUCM4x50__)
746 #if TMR1_CFG_EVENT_CAPTURE > 39u
747 #error "Invalid configuration"
748 #endif
749 #else
750 #error TMR is not ported for this processor
751 #endif
752 
753 #if TMR1_CFG_ENABLE_PWM0_MATCH_MODE > 1u
754 #error "Invalid configuration"
755 #endif
756 
757 #if TMR1_CFG_PWM0_IDLE_STATE > 1u
758 #error "Invalid configuration"
759 #endif
760 
761 #if TMR1_CFG_PWM0_MATCH_VALUE > 0xFFFFu
762 #error "Invalid configuration"
763 #endif
764 
765 /*************************************************************
766  GP Timer 2 Macro Validation
767 **************************************************************/
768 
769 #if TMR2_CFG_COUNT_UP > 1u
770 #error "Invalid configuration"
771 #endif
772 
773 #if TMR2_CFG_MODE > 1u
774 #error "Invalid configuration"
775 #endif
776 
777 #if TMR2_CFG_PRESCALE_FACTOR > 3u
778 #error "Invalid configuration"
779 #endif
780 
781 #if TMR2_CFG_CLOCK_SOURCE > 3u
782 #error "Invalid configuration"
783 #endif
784 
785 #if TMR2_CFG_LOAD_VALUE > 0xFFFFu
786 #error "Invalid configuration"
787 #endif
788 
789 #if TMR2_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
790 #error "Invalid configuration"
791 #endif
792 
793 #if TMR2_CFG_ENABLE_RELOADING > 1u
794 #error "Invalid configuration"
795 #endif
796 
797 #if TMR2_CFG_ENABLE_SYNC_BYPASS > 1u
798 #error "Invalid configuration"
799 #endif
800 
801 #if TMR2_CFG_ENABLE_PRESCALE_RESET > 1u
802 #error "Invalid configuration"
803 #endif
804 
805 #if TMR2_CFG_ENABLE_EVENT_CAPTURE > 1u
806 #error "Invalid configuration"
807 #endif
808 
809 #if defined(__ADUCM302x__)
810 #if TMR2_CFG_EVENT_CAPTURE > 15u
811 #error "Invalid configuration"
812 #endif
813 #elif defined(__ADUCM4x50__)
814 #if TMR2_CFG_EVENT_CAPTURE > 39u
815 #error "Invalid configuration"
816 #endif
817 #else
818 #error TMR is not ported for this processor
819 #endif
820 
821 #if TMR2_CFG_ENABLE_PWM0_MATCH_MODE > 1u
822 #error "Invalid configuration"
823 #endif
824 
825 #if TMR2_CFG_PWM0_IDLE_STATE > 1u
826 #error "Invalid configuration"
827 #endif
828 
829 #if TMR2_CFG_PWM0_MATCH_VALUE > 0xFFFFu
830 #error "Invalid configuration"
831 #endif
832 
833 #if defined(__ADUCM4x50__)
834 /*************************************************************
835  RGB Timer Macro Validation
836 **************************************************************/
837 #if TMR3_CFG_COUNT_UP > 1u
838 #error "Invalid configuration"
839 #endif
840 
841 #if TMR3_CFG_MODE > 1u
842 #error "Invalid configuration"
843 #endif
844 
845 #if TMR3_CFG_PRESCALE_FACTOR > 3u
846 #error "Invalid configuration"
847 #endif
848 
849 #if TMR3_CFG_CLOCK_SOURCE > 3u
850 #error "Invalid configuration"
851 #endif
852 
853 #if TMR3_CFG_LOAD_VALUE > 0xFFFFu
854 #error "Invalid configuration"
855 #endif
856 
857 #if TMR3_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
858 #error "Invalid configuration"
859 #endif
860 
861 #if TMR3_CFG_ENABLE_RELOADING > 1u
862 #error "Invalid configuration"
863 #endif
864 
865 #if TMR3_CFG_ENABLE_SYNC_BYPASS > 1u
866 #error "Invalid configuration"
867 #endif
868 
869 #if TMR3_CFG_ENABLE_PRESCALE_RESET > 1u
870 #error "Invalid configuration"
871 #endif
872 
873 #if TMR3_CFG_ENABLE_EVENT_CAPTURE > 1u
874 #error "Invalid configuration"
875 #endif
876 
877 #if TMR3_CFG_EVENT_CAPTURE > 39u
878 #error "Invalid configuration"
879 #endif
880 
881 #if TMR3_CFG_ENABLE_PWM0_MATCH_MODE > 1u
882 #error "Invalid configuration"
883 #endif
884 
885 #if TMR3_CFG_PWM0_IDLE_STATE > 1u
886 #error "Invalid configuration"
887 #endif
888 
889 #if TMR3_CFG_PWM0_MATCH_VALUE > 0xFFFFu
890 #error "Invalid configuration"
891 #endif
892 
893 #if TMR3_CFG_ENABLE_PWM1_MATCH_MODE > 1u
894 #error "Invalid configuration"
895 #endif
896 
897 #if TMR3_CFG_PWM1_IDLE_STATE > 1u
898 #error "Invalid configuration"
899 #endif
900 
901 #if TMR3_CFG_PWM1_MATCH_VALUE > 0xFFFFu
902 #error "Invalid configuration"
903 #endif
904 
905 #if TMR3_CFG_ENABLE_PWM2_MATCH_MODE > 1u
906 #error "Invalid configuration"
907 #endif
908 
909 #if TMR3_CFG_PWM2_IDLE_STATE > 1u
910 #error "Invalid configuration"
911 #endif
912 
913 #if TMR3_CFG_PWM2_MATCH_VALUE > 0xFFFFu
914 #error "Invalid configuration"
915 #endif
916 
917 #endif
918 
921 #endif /* ADI_TMR_CONFIG_H */