ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_pwr_config.h
1 /*
2  *****************************************************************************
3  @file: adi_pwr_config.h
4  @brief: Configuration options for PWR driver.
5  This is specific to the PWR driver and will be included by the source file.
6  It is not required for the application to include this header file.
7  -----------------------------------------------------------------------------
8 
9 Copyright (c) 2016-2017 Analog Devices, Inc.
10 
11 All rights reserved.
12 
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright notice,
16  this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright notice,
18  this list of conditions and the following disclaimer in the documentation
19  and/or other materials provided with the distribution.
20  - Modified versions of the software must be conspicuously marked as such.
21  - This software is licensed solely and exclusively for use with processors
22  manufactured by or for Analog Devices, Inc.
23  - This software may not be combined or merged with other code in any manner
24  that would cause the software to become subject to terms and conditions
25  which differ from those listed here.
26  - Neither the name of Analog Devices, Inc. nor the names of its
27  contributors may be used to endorse or promote products derived
28  from this software without specific prior written permission.
29  - The use of this software may or may not infringe the patent rights of one
30  or more patent holders. This license does not release you from the
31  requirement that you obtain separate licenses from these patent holders
32  to use this software.
33 
34 THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
35 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
36 TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
37 NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
38 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
39 (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
40 PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
41 OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
43 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
44 EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 
46 *****************************************************************************/
47 
48 #ifndef ADI_PWR_CONFIG_H
49 #define ADI_PWR_CONFIG_H
50 #include <adi_global_config.h>
51 #ifdef __ICCARM__
52 /* IAR MISRA C 2004 error suppressions.
53 *
54 * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
55 * The YODA-generated headers rely on more. The IAR compiler supports that.
56 */
57 #pragma diag_suppress=Pm009
58 #endif /* __ICCARM__ */
59 
70 #define ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO 0
71 
72 /*-------------------------------------------------------------------------------
73  Set of MACROs for configuring the clock
74 --------------------------------------------------------------------------------*/
75 /* Oscillator Control Register */
76 
82 #define ADI_PWR_LF_CLOCK_MUX 0
83 
84 
90 #define ADI_PWR_HFOSC_CLOCK_ENABLE 1
91 
98 #define ADI_PWR_LFXTAL_CLOCK_ENABLE 0
99 
105 #define ADI_PWR_HFXTAL_CLOCK_ENABLE 0
106 
114 #define ADI_PWR_LFXTAL_CLOCK_MON_ENABLE 0
115 
123 #define ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE 0
124 
132 #define ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE 0
133 
134 
141 #define ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE 0
142 
143 
144 /********** Miscellaneous clock setting register CTL0 *************/
145 
154 #define ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX 0
155 
177 #define ADI_PWR_GPIO_CLOCK_OUT_SELECT 0
178 
186 #define ADI_PWR_INPUT_TO_RCLK_MUX 0
187 
195 #define ADI_PWR_INPUT_TO_SPLL_MUX 0
196 
202 #define ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE 0
203 
209 #define ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE 0
210 
211 
212 
213 /********** Clock divider register CTL1 ***************/
214 
219 #define ADI_PWR_HCLK_DIVIDE_COUNT 4
220 
225 #define ADI_PWR_PCLK_DIVIDE_COUNT 4
226 
231 #define ADI_PWR_ACLK_DIVIDE_COUNT 16
232 
233 
234 
235 /************* HF Oscillator divide clock select register CTL2 ***********/
236 
251 #define ADI_PWR_HFOSC_AUTO_DIV_BY_1 0
252 
264 #define ADI_PWR_HFOSC_DIVIDE_SELECT 0
265 
266 
267 
268 /****** System PLL Register CTL3 *****/
274 #define ADI_PWR_SPLL_MUL_FACTOR 26
275 
282 #define ADI_PWR_SPLL_ENABLE_DIV2 0
283 
289 #define ADI_PWR_SPLL_ENABLE 0
290 
296 #define ADI_PWR_SPLL_INTERRUPT_ENABLE 0
297 
303 #define ADI_PWR_SPLL_DIV_FACTOR 13
304 
310 #define ADI_PWR_SPLL_ENABLE_MUL2 0
311 
312 
313 /********** User Clock Gating Control CTL5 ********************/
314 
320 #define ADI_PWR_GPT0_CLOCK_ENABLE 1
321 
327 #define ADI_PWR_GPT1_CLOCK_ENABLE 1
328 
333 #define ADI_PWR_GPT2_CLOCK_ENABLE 1
334 
342 #define ADI_PWR_I2C_CLOCK_ENABLE 1
343 
351 #define ADI_PWR_GPIO_CLOCK_ENABLE 1
352 
353 
361 #define ADI_PWR_PCLK_ENABLE 0
362 
370 #define ADI_PWR_TIMER_RGB_ENABLE 1
371 
372 /*-------------------------------------------------------------------------------
373  Set of macros for configuring the power management module
374 --------------------------------------------------------------------------------*/
375 
376 /********* Interrupt enable register IEN ********/
377 
383 #define ADI_PWR_ENABLE_VBAT_INTERRUPT 0
384 
390 #define ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT 0
391 
397 #define ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT 0
398 
404 #define ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT 0
405 
412 #define ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT 0
413 
414 /********* HP Buck control register CTL1 ********/
420 #define ADI_PWR_HP_BUCK_ENABLE 0
421 
431 #define ADI_PWR_HP_BUCK_LOAD_MODE 0
432 
443 #define ADI_PWR_HP_BUCK_LOW_POWER_MODE 0
444 
445 
446 /********* Power mode register ********/
447 
455 #define ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING 0
456 
457 
458 /*******************************************************************************
459  M A C R O V A L I D A T I O N
460 *******************************************************************************/
461 
462 #if ( ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO > 1 )
463 #error "Invalid configuration set for ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO"
464 #endif
465 
466 #if ( ADI_PWR_LF_CLOCK_MUX > 1 )
467 #error "Invalid configuration set for ADI_PWR_LF_CLOCK_MUX"
468 #endif
469 
470 #if ( ADI_PWR_HFOSC_CLOCK_ENABLE > 1 )
471 #error "Invalid configuration set for ADI_PWR_HFOSC_CLOCK_ENABLE"
472 #endif
473 
474 #if ( ADI_PWR_LFXTAL_CLOCK_ENABLE > 1 )
475 #error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_ENABLE"
476 #endif
477 
478 #if ( ADI_PWR_HFXTAL_CLOCK_ENABLE > 1 )
479 #error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_ENABLE"
480 #endif
481 
482 #if ( ADI_PWR_LFXTAL_CLOCK_MON_ENABLE > 1 )
483 #error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_MON_ENABLE"
484 #endif
485 
486 #if ( ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE > 1 )
487 #error "Invalid configuration set for ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE"
488 #endif
489 
490 #if ( ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE > 1 )
491 #error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE"
492 #endif
493 
494 #if ( ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT > 3 )
495 #error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT"
496 #endif
497 
498 #if ( ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE > 1 )
499 #error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE"
500 #endif
501 
502 #if ( ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE > 1 )
503 #error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE"
504 #endif
505 
506 #if ( ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX > 3 )
507 #error "Invalid configuration set for ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX"
508 #endif
509 
510 #if ( ADI_PWR_GPIO_CLOCK_OUT_SELECT > 15 )
511 #error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_OUT_SELECT"
512 #endif
513 
514 #if ( ADI_PWR_INPUT_TO_RCLK_MUX > 3 )
515 #error "Invalid configuration set for ADI_PWR_INPUT_TO_RCLK_MUX"
516 #endif
517 
518 #if ( ADI_PWR_INPUT_TO_SPLL_MUX > 3 )
519 #error "Invalid configuration set for ADI_PWR_INPUT_TO_SPLL_MUX"
520 #endif
521 
522 #if ( ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE > 1 )
523 #error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE"
524 #endif
525 
526 #if ( ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE > 1 )
527 #error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE"
528 #endif
529 
530 #if ( ADI_PWR_HCLK_DIVIDE_COUNT > 63 )
531 #error "Invalid configuration set for ADI_PWR_HCLK_DIVIDE_COUNT"
532 #endif
533 
534 #if ( ADI_PWR_PCLK_DIVIDE_COUNT > 63 )
535 #error "Invalid configuration set for ADI_PWR_PCLK_DIVIDE_COUNT"
536 #endif
537 
538 #if ( ADI_PWR_ACLK_DIVIDE_COUNT > 63 )
539 #error "Invalid configuration set for ADI_PWR_ACLK_DIVIDE_COUNT"
540 #endif
541 
542 #if ( ADI_PWR_HFOSC_AUTO_DIV_BY_1 > 1 )
543 #error "Invalid configuration set for ADI_PWR_HFOSC_AUTO_DIV_BY_1"
544 #endif
545 
546 #if ( ADI_PWR_HFOSC_DIVIDE_SELECT > 5 )
547 #error "Invalid configuration set for ADI_PWR_HFOSC_DIVIDE_SELECT"
548 #endif
549 
550 #if ( ADI_PWR_SPLL_MUL_FACTOR < 8 || ADI_PWR_SPLL_MUL_FACTOR > 31 )
551 #error "Invalid configuration set for ADI_PWR_SPLL_MUL_FACTOR"
552 #endif
553 
554 #if ( ADI_PWR_SPLL_ENABLE_DIV2 > 1 )
555 #error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_DIV2"
556 #endif
557 
558 #if ( ADI_PWR_SPLL_ENABLE > 1 )
559 #error "Invalid configuration set for ADI_PWR_SPLL_ENABLE"
560 #endif
561 
562 #if ( ADI_PWR_SPLL_INTERRUPT_ENABLE > 1 )
563 #error "Invalid configuration set for ADI_PWR_SPLL_INTERRUPT_ENABLE"
564 #endif
565 
566 #if ( ADI_PWR_SPLL_DIV_FACTOR < 2 || ADI_PWR_SPLL_DIV_FACTOR > 15 )
567 #error "Invalid configuration set for ADI_PWR_SPLL_DIV_FACTOR"
568 #endif
569 
570 #if ( ADI_PWR_SPLL_ENABLE_MUL2 > 1 )
571 #error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_MUL2"
572 #endif
573 
574 #if ( ADI_PWR_GPT0_CLOCK_ENABLE > 1 )
575 #error "Invalid configuration set for ADI_PWR_GPT0_CLOCK_ENABLE"
576 #endif
577 
578 #if ( ADI_PWR_GPT1_CLOCK_ENABLE > 1 )
579 #error "Invalid configuration set for ADI_PWR_GPT1_CLOCK_ENABLE"
580 #endif
581 
582 #if ( ADI_PWR_GPT2_CLOCK_ENABLE > 1 )
583 #error "Invalid configuration set for ADI_PWR_GPT2_CLOCK_ENABLE"
584 #endif
585 
586 #if ( ADI_PWR_I2C_CLOCK_ENABLE > 1 )
587 #error "Invalid configuration set for ADI_PWR_I2C_CLOCK_ENABLE"
588 #endif
589 
590 #if ( ADI_PWR_GPIO_CLOCK_ENABLE > 1 )
591 #error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_ENABLE"
592 #endif
593 
594 #if ( ADI_PWR_PCLK_ENABLE > 1 )
595 #error "Invalid configuration set for ADI_PWR_PCLK_ENABLE"
596 #endif
597 
598 #if ( ADI_PWR_TIMER_RGB_ENABLE > 1 )
599 #error "Invalid configuration set for ADI_PWR_TIMER_RGB_ENABLE"
600 #endif
601 
602 #if ( ADI_PWR_ENABLE_VBAT_INTERRUPT > 1 )
603 #error "Invalid configuration set for ADI_PWR_ENABLE_VBAT_INTERRUPT"
604 #endif
605 
606 #if ( ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT > 1 )
607 #error "Invalid configuration set for ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT"
608 #endif
609 
610 #if ( ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT > 1 )
611 #error "Invalid configuration set for ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT"
612 #endif
613 
614 #if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT > 1 )
615 #error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT"
616 #endif
617 
618 #if ( ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT > 2 )
619 #error "Invalid configuration set for ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT"
620 #endif
621 
622 #if ( ADI_PWR_HP_BUCK_ENABLE > 1 )
623 #error "Invalid configuration set for ADI_PWR_HP_BUCK_ENABLE"
624 #endif
625 
626 #if ( ADI_PWR_HP_BUCK_LOAD_MODE > 1 )
627 #error "Invalid configuration set for ADI_PWR_HP_BUCK_LOAD_MODE"
628 #endif
629 
630 #if ( ADI_PWR_HP_BUCK_LOW_POWER_MODE > 1 )
631 #error "Invalid configuration set for ADI_PWR_HP_BUCK_LOW_POWER_MODE"
632 #endif
633 
634 #if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING > 1 )
635 #error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING"
636 #endif
637 
638 
639 
642 #ifdef __ICCARM__
643 #pragma diag_default=Pm009
644 #endif /* __ICCARM__ */
645 
646 #endif /* ADI_PWR_CONFIG_H */