70 #include <adi_processor.h> 76 #include <drivers/spi/adi_spi.h> 77 #include <drivers/pwr/adi_pwr.h> 78 #include <drivers/general/adi_drivers_general.h> 79 #include <adi_callback.h> 80 #include <rtos_map/adi_rtos_map.h> 81 #include "adi_spi_config.h" 82 #include <adi_cyclecount.h> 115 #pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm143,Pm152,Pm140,Pm031 119 #include "adi_spi_data.c" 124 #define ADI_SPI_VALIDATE_HANDLE(h) ((spi_device_info[0].hDevice != (h)) && (spi_device_info[1].hDevice != (h)) && (spi_device_info[2].hDevice != (h))) 131 static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD);
133 static void TxDmaErrorCallback (
void *pCBParam, uint32_t Event,
void *pArg);
134 static void RxDmaErrorCallback (
void *pCBParam, uint32_t Event,
void *pArg);
138 void SPI0_Int_Handler(
void);
139 void SPI1_Int_Handler(
void);
140 void SPI2_Int_Handler(
void);
141 void DMA_SPI0_TX_Int_Handler(
void);
142 void DMA_SPI0_RX_Int_Handler(
void);
143 void DMA_SPI1_TX_Int_Handler(
void);
144 void DMA_SPI1_RX_Int_Handler(
void);
145 void DMA_SPIH_TX_Int_Handler(
void);
146 void DMA_SPIH_RX_Int_Handler(
void);
186 uint32_t nMemorySize,
192 if (nDeviceNum >= ADI_SPI_NUM_INSTANCES)
197 if (nMemorySize !=
sizeof(
struct __ADI_SPI_DEV_DATA_TYPE))
202 if( spi_device_info[nDeviceNum].hDevice != NULL )
224 memset(pDevMemory,0,nMemorySize);
225 hDevice->pDevInfo = &spi_device_info[nDeviceNum];
226 spi_device_info[nDeviceNum].hDevice = (ADI_SPI_DEV_DATA_TYPE *)pDevMemory;
234 hDevice->pSpi = spi_device_info[nDeviceNum].pSpiRegs;
240 ADI_SPI_CFG_TYPE
const* pSPICfg = &gSPICfg[nDeviceNum];
241 hDevice->pSpi->CTL = pSPICfg->SPI_CTL;
242 hDevice->pSpi->DIV = pSPICfg->SPI_DIV;
246 hDevice->pSpi->CTL |= BITM_SPI_CTL_SPIEN;
285 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
294 NVIC_DisableIRQ(hDevice->pDevInfo->eIRQn);
301 hDevice->pDevInfo->hDevice = NULL;
322 if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
328 hDevice->pfCallback = pfCallback;
329 hDevice->pCBParam = pCBParam;
371 if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
375 if (nMode > ADI_SPI_IRQ_PARAM) {
381 uint16_t ien = hDevice->pSpi->IEN;
382 ien = ien & (uint16_t)~BITM_SPI_IEN_IRQMODE;
383 ien = ien | (nMode & BITM_SPI_IEN_IRQMODE);
384 hDevice->pSpi->IEN = ien;
411 if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
418 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
420 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
445 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
453 hDevice->pSpi->CTL |= (BITM_SPI_CTL_LOOPBACK);
455 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_LOOPBACK;
480 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
486 ADI_INT_STATUS_ALLOC();
487 ADI_ENTER_CRITICAL_REGION();
489 hDevice->pSpi->CTL |= (ADI_SPI_MASTERCON_INITIALIZER);
491 hDevice->pSpi->CNT = 0u;
492 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_MASEN;
493 hDevice->pSpi->CTL |= (ADI_SPI_SLAVECON_INITIALIZER);
495 ADI_EXIT_CRITICAL_REGION();
523 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
531 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RXOF);
533 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_RXOF;
561 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
568 hDevice->pSpi->CTL |= (BITM_SPI_CTL_ZEN);
570 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_ZEN;
601 uint32_t incoming_clock;
605 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
617 if ((2U * Hertz) > incoming_clock)
623 Div = (uint16_t) ((incoming_clock / Hertz) >> 1U) - 1U;
626 if (Div != (Div & BITM_SPI_DIV_VALUE))
632 hDevice->pSpi->DIV = Div;
658 uint32_t incoming_clock;
663 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
668 Div = hDevice->pSpi->DIV;
676 *pnBitrate= (incoming_clock / (Div + 1U)) >> 1U;
714 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
721 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPOL);
723 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPOL;
749 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
755 hDevice->ChipSelect = eChipSelect;
793 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
800 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPHA);
802 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPHA;
837 hDevice->bBlockingMode =
true;
839 hDevice->bBlockingMode =
false;
877 volatile uint16_t nStatus;
880 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
904 hDevice->bDmaMode = pXfr->
bDMA;
905 hDevice->bRdCtlMode = pXfr->
bRD_CTL;
906 hDevice->bTransferComplete =
false;
925 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH);
941 if( hDevice->bDmaMode==
true ) {
944 if( hDevice->RxRemaining != 0u) {
945 hDevice->pSpi->IEN &= (uint16_t)~(BITM_SPI_IEN_XFRDONE);
947 hDevice->pSpi->IEN |= (BITM_SPI_IEN_XFRDONE);
953 uint16_t activeInterrupts = BITM_SPI_IEN_XFRDONE;
955 if( hDevice->TxRemaining ) {
956 activeInterrupts |= BITM_SPI_IEN_TXUNDR;
959 if( hDevice->RxRemaining ) {
960 activeInterrupts |= BITM_SPI_IEN_RXOVR;
963 hDevice->pSpi->IEN |= activeInterrupts;
971 if( hDevice->RxRemaining == 0u) {
972 hDevice->pSpi->CTL |= ( BITM_SPI_CTL_TIM );
978 nStatus = hDevice->pSpi->STAT;
979 hDevice->pSpi->STAT = nStatus;
982 hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN);
985 hDevice->pSpi->CS_CTL = hDevice->ChipSelect;
987 StartTransaction(hDevice, pXfr);
991 if (hDevice->bBlockingMode ==
true)
1011 if( (hDevice->bDmaMode ==
true) && (hDevice->bRdCtlMode ==
true) && (pXfr->
ReceiverBytes == 1u))
1014 hDevice->bDmaMode =
false;
1017 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
1018 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
1021 hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1028 uint16_t dmaFlags = 0u;
1030 if( hDevice->bDmaMode ==
true)
1032 dmaFlags = BITM_SPI_DMA_EN;
1037 uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
1040 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
1043 pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
1046 pADI_DMA0->EN_SET = 1U << TxChanNum;
1049 pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
1052 pADI_DMA0->ALT_CLR = 1U << TxChanNum;
1055 if( (sz & 1U) != 0u )
1062 pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->
pTransmitter + (sz - 2U));
1064 pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX;
1066 pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)
ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
1069 ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
1070 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1072 dmaFlags |= (BITM_SPI_DMA_TXEN);
1079 uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
1080 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
1083 pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
1086 pADI_DMA0->EN_SET = 1U << RxChanNum;
1089 pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
1092 pADI_DMA0->ALT_CLR = 1U << RxChanNum;
1094 if( (sz & 1U) != 0u )
1101 pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX;
1103 pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->
pReceiver + (sz - 2U));
1108 ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
1109 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1111 dmaFlags |= (BITM_SPI_DMA_RXEN );
1125 hDevice->pSpi->RD_CTL = 0u;
1126 if( hDevice->bRdCtlMode)
1131 uint32_t nBytes = hDevice->TxRemaining - 1U;
1134 hDevice->pSpi->RD_CTL &= (uint16_t)~((uint16_t)(BITM_SPI_RD_CTL_TXBYTES << BITP_SPI_RD_CTL_TXBYTES));
1136 hDevice->pSpi->RD_CTL |= (uint16_t)( (uint16_t)(nBytes << BITP_SPI_RD_CTL_TXBYTES) |
1137 (uint16_t)(1 << BITP_SPI_RD_CTL_CMDEN));
1140 hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
1143 hDevice->pSpi->CNT = hDevice->RxRemaining;
1148 if(hDevice->RxRemaining == 0u)
1151 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH);
1153 else if(hDevice->TxRemaining == 0u)
1156 hDevice->pSpi->CTL |= (BITM_SPI_CTL_TFLUSH);
1165 nCount = hDevice->RxRemaining > hDevice->TxRemaining ? hDevice->RxRemaining : hDevice->TxRemaining;
1167 hDevice->pSpi->CNT = (uint16_t)nCount;
1171 if( hDevice->bDmaMode ==
false)
1175 if( hDevice->pTxBuffer != NULL)
1179 while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
1182 hDevice->pSpi->TX = *hDevice->pTxBuffer;
1184 hDevice->pTxBuffer += hDevice->TxIncrement;
1186 hDevice->TxRemaining--;
1193 hDevice->pSpi->DMA |= dmaFlags;
1196 #if defined(ADI_SPI_MASTER_TIM_FOR_DMA) && (ADI_SPI_MASTER_TIM_FOR_DMA != 0u) 1198 hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM;
1202 for( uint16_t numberOfLoops = 0u; numberOfLoops < 100u; numberOfLoops++)
1206 volatile uint16_t nFifoStatus = hDevice->pSpi->FIFO_STAT;
1208 uint16_t writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX);
1209 if( writableBytes != 0u)
1218 if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
1220 uint16_t byte ADI_UNUSED_ATTRIBUTE = hDevice->pSpi->RX;
1224 NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
1246 uint32_t *
const pHWErrors
1250 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
1258 *pHWErrors = hDevice->HWErrors;
1282 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
1288 *bComplete = hDevice->bTransferComplete;
1324 volatile uint16_t ADI_UNUSED_ATTRIBUTE byte;
1325 uint32_t nCount = 0u;
1328 if (ADI_SPI_VALIDATE_HANDLE(hDevice))
1362 hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
1363 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
1366 hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1368 hDevice->bTransferComplete =
false;
1375 hDevice->bDmaMode = pXfr->
bDMA;
1376 hDevice->bRdCtlMode = pXfr->
bRD_CTL;
1381 hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH | BITM_SPI_CTL_CON);
1382 if( hDevice->TxRemaining == 0u )
1385 hDevice->pSpi->CTL |= BITM_SPI_CTL_TFLUSH;
1387 if( hDevice->RxRemaining == 0u )
1390 hDevice->pSpi->CTL |= BITM_SPI_CTL_RFLUSH;
1393 if( hDevice->bDmaMode !=
true) {
1394 hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM;
1399 hDevice->pSpi->CNT = (uint16_t) hDevice->TxRemaining > hDevice->RxRemaining ? hDevice->TxRemaining : hDevice->RxRemaining;
1401 uint16_t nDMAFlags = 0u;
1403 if( hDevice->bDmaMode ==
true)
1408 uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
1411 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
1414 pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
1417 pADI_DMA0->EN_SET = 1U << TxChanNum;
1420 pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
1423 pADI_DMA0->ALT_CLR = 1U << TxChanNum;
1426 if( (sz & 1U) != 0u )
1433 pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->
pTransmitter + (sz - 2U));
1435 pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX;
1437 pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)
ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
1440 ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
1441 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1443 nDMAFlags |= (BITM_SPI_DMA_TXEN);
1450 uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
1451 NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
1454 pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
1457 pADI_DMA0->EN_SET = 1U << RxChanNum;
1460 pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
1463 pADI_DMA0->ALT_CLR = 1U << RxChanNum;
1465 if( (sz & 1U) != 0u )
1472 pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX;
1474 pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->
pReceiver + (sz - 2U));
1479 ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
1480 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
1482 nDMAFlags |= (BITM_SPI_DMA_RXEN );
1488 hDevice->pSpi->IEN &= (uint16_t)~BITM_SPI_IEN_XFRDONE;
1490 if( hDevice->bDmaMode ==
false) {
1492 hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
1497 uint16_t activeInterrupts = 0u;
1499 if( hDevice->TxRemaining ) {
1500 activeInterrupts |= BITM_SPI_IEN_TXUNDR;
1503 if( hDevice->RxRemaining ) {
1504 activeInterrupts |= BITM_SPI_IEN_RXOVR;
1506 hDevice->pSpi->IEN |= activeInterrupts;
1509 while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
1512 hDevice->pSpi->TX = *hDevice->pTxBuffer;
1514 hDevice->pTxBuffer += hDevice->TxIncrement;
1516 hDevice->TxRemaining--;
1522 hDevice->pSpi->DMA |= (uint16_t)(BITM_SPI_DMA_EN | nDMAFlags);
1525 if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
1527 byte = hDevice->pSpi->RX;
1529 NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
1531 if (hDevice->bBlockingMode ==
true)
1570 hDevice->bBlockingMode =
true;
1572 hDevice->bBlockingMode =
false;
1595 static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD)
1598 uint16_t nFifoStatus;
1599 uint16_t writableBytes;
1600 uint16_t readableBytes;
1601 bool terminate =
false;
1604 uint16_t nErrorStatus = pDD->pSpi->STAT;
1608 pDD->pSpi->STAT = nErrorStatus;
1609 nFifoStatus = pDD->pSpi->FIFO_STAT;
1612 if(0u != ((BITM_SPI_STAT_RXOVR | BITM_SPI_STAT_TXUNDR) & nErrorStatus)) {
1614 if(BITM_SPI_STAT_TXUNDR == (BITM_SPI_STAT_TXUNDR & nErrorStatus)) {
1617 if( BITM_SPI_STAT_RXOVR == (BITM_SPI_STAT_RXOVR & nErrorStatus)) {
1626 writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX);
1628 readableBytes = ((BITM_SPI_FIFO_STAT_RX & nFifoStatus) >> BITP_SPI_FIFO_STAT_RX);
1631 while ((writableBytes != 0u) && (pDD->TxRemaining != 0u))
1633 pDD->pSpi->TX = *pDD->pTxBuffer;
1634 pDD->pTxBuffer += pDD->TxIncrement;
1643 if( (pDD->bRdCtlMode==
false) || (pDD->TxRemaining==0u) )
1646 while ((readableBytes != 0u) &&(pDD->RxRemaining != 0u))
1648 *pDD->pRxBuffer = (uint8_t) pDD->pSpi->RX;
1649 pDD->pRxBuffer += pDD->RxIncrement;
1661 if( (pDD->RxRemaining == 0u) && (pDD->TxRemaining == 0u))
1663 if( BITM_SPI_CTL_MASEN == (pDD->pSpi->CTL & BITM_SPI_CTL_MASEN ))
1670 if((BITM_SPI_STAT_XFRDONE == (nErrorStatus & BITM_SPI_STAT_XFRDONE)) ||
1671 (BITM_SPI_STAT_XFRDONE == (pDD->pSpi->STAT & BITM_SPI_STAT_XFRDONE)) )
1692 pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);
1693 pDD->bTransferComplete =
true;
1694 NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
1697 nErrorStatus = pDD->pSpi->STAT;
1698 pDD->pSpi->STAT = nErrorStatus;
1701 if(NULL != pDD->pfCallback ){
1702 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1710 #if defined(ADI_CYCLECOUNT_SPI_ISR_ENABLED) && (ADI_CYCLECOUNT_SPI_ISR_ENABLED == 1u) 1718 static void RxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
1737 if(NULL != hDevice->pfCallback ){
1738 hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL);
1748 static void TxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
1767 if(NULL != hDevice->pfCallback ){
1768 hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL);
1784 void SPI0_Int_Handler(
void) {
1786 common_SPI_Int_Handler(spi_device_info[0].hDevice );
1798 void SPI1_Int_Handler(
void) {
1800 common_SPI_Int_Handler(spi_device_info[1].hDevice);
1811 void SPI2_Int_Handler(
void) {
1813 common_SPI_Int_Handler(spi_device_info[2].hDevice );
1830 #if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==1u) 1831 void DMA_SPI0_TX_Int_Handler(
void)
1835 pDD->TxRemaining = 0u;
1840 void DMA_SPI0_RX_Int_Handler(
void)
1844 pDD->RxRemaining = 0u;
1846 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1849 pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
1853 #if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==0u) 1855 void DMA_SPI0_TX_Int_Handler(
void)
1859 pDD->TxRemaining = 0u;
1860 if( pDD->RxRemaining == 0)
1863 if(NULL != pDD->pfCallback ){
1864 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1873 void DMA_SPI0_RX_Int_Handler(
void)
1877 pDD->RxRemaining = 0u;
1879 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1880 pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);
1881 pDD->bTransferComplete =
true;
1882 NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
1885 if(NULL != pDD->pfCallback ){
1886 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1899 #if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==1u) 1901 void DMA_SPI1_TX_Int_Handler(
void)
1905 pDD->TxRemaining = 0u;
1909 void DMA_SPI1_RX_Int_Handler(
void)
1913 pDD->RxRemaining = 0u;
1915 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1918 pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
1924 #if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==0u) 1926 void DMA_SPI1_TX_Int_Handler(
void)
1930 pDD->TxRemaining = 0u;
1931 if( pDD->RxRemaining == 0)
1934 if(NULL != pDD->pfCallback ){
1935 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1946 void DMA_SPI1_RX_Int_Handler(
void)
1950 pDD->RxRemaining = 0u;
1952 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1953 pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);
1954 pDD->bTransferComplete =
true;
1955 NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
1958 if(NULL != pDD->pfCallback ){
1959 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
1970 #if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==1u) 1973 void DMA_SPIH_TX_Int_Handler(
void)
1977 pDD->TxRemaining = 0u;
1981 void DMA_SPIH_RX_Int_Handler(
void)
1985 pDD->RxRemaining = 0u;
1987 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
1990 pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
1994 #if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==0u) 1997 void DMA_SPIH_TX_Int_Handler(
void)
2001 pDD->TxRemaining = 0u;
2002 if( pDD->RxRemaining == 0)
2005 if(NULL != pDD->pfCallback ){
2006 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
2016 void DMA_SPIH_RX_Int_Handler(
void)
2020 pDD->RxRemaining = 0u;
2022 pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
2023 pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);
2024 pDD->bTransferComplete =
true;
2025 NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
2028 if(NULL != pDD->pfCallback ){
2029 pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
ADI_SPI_RESULT adi_spi_SetTransmitUnderflow(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the SPI transmit FIFO underflow mode.
ADI_DMA_RESULT adi_dma_RegisterCallback(DMA_CHANn_TypeDef const eChannelID, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register a call-back function for a DMA channel.
ADI_SPI_RESULT adi_spi_GetBuffer(ADI_SPI_HANDLE const hDevice, uint32_t *const pHWErrors)
Block until the SPI transaction is complete.
#define ADI_CYCLECOUNT_STORE(id)
ADI_SPI_RESULT adi_spi_SlaveReadWrite(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Slave-Mode transaction in "Blocking mode".This function returns only af...
uint16_t TransmitterBytes
ADI_SPI_RESULT adi_spi_SetClockPhase(ADI_SPI_HANDLE const hDevice, const bool bFlag)
Set the clock phase.
#define ADI_CYCLECOUNT_ISR_SPI
ADI_SPI_RESULT adi_spi_SetContinuousMode(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the continuous transfer mode.
ADI_SPI_RESULT adi_spi_Open(uint32_t nDeviceNum, void *pDevMemory, uint32_t nMemorySize, ADI_SPI_HANDLE *const phDevice)
Initialize and allocate an SPI device for use in Master Mode.
ADI_SPI_RESULT adi_spi_Close(ADI_SPI_HANDLE const hDevice)
Uninitialize and deallocate an SPI device.
ADI_SPI_RESULT adi_spi_isBufferAvailable(ADI_SPI_CONST_HANDLE const hDevice, bool *const bComplete)
Get the SPI transaction completion status.
ADI_SPI_RESULT adi_spi_SetChipSelect(ADI_SPI_HANDLE const hDevice, const ADI_SPI_CHIP_SELECT eChipSelect)
Set the chip select.
ADI_SPI_RESULT adi_spi_SetLoopback(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the internal loopback mode.
ADI_SPI_RESULT adi_spi_GetBitrate(ADI_SPI_CONST_HANDLE const hDevice, uint32_t *const pnBitrate)
Get the SPI serial clock frequency.
ADI_SPI_RESULT adi_spi_RegisterCallback(ADI_SPI_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register or unregister the callback.
ADI_SPI_RESULT adi_spi_SetClockPolarity(ADI_SPI_HANDLE const hDevice, const bool bFlag)
Set the clock polarity.
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
ADI_SPI_RESULT adi_spi_SetIrqmode(ADI_SPI_CONST_HANDLE const hDevice, const uint8_t nMode)
Set the IRQ mode.
ADI_SPI_RESULT adi_spi_SetReceiveOverflow(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set the SPI receive FIFO overflow mode.
ADI_SPI_RESULT adi_spi_MasterReadWrite(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Master-Mode transaction in "Blocking mode".This function returns only a...
struct __ADI_SPI_DEV_DATA_TYPE * ADI_SPI_HANDLE
ADI_SPI_RESULT adi_spi_SetMasterMode(ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
Set SPI Master-Mode operation.
void adi_dma_Init(void)
Initialize the DMA peripheral.
const struct __ADI_SPI_DEV_DATA_TYPE * ADI_SPI_CONST_HANDLE
ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Slave-Mode transaction.
ADI_SPI_RESULT adi_spi_SetBitrate(ADI_SPI_CONST_HANDLE const hDevice, const uint32_t Hertz)
Set the SPI serial clock frequency.
ADI_SPI_RESULT adi_spi_MasterSubmitBuffer(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER *const pXfr)
Submit data buffers for SPI Master-Mode transaction.