57 #include <drivers/uart/adi_uart.h> 58 #include <drivers/dma/adi_dma.h> 59 #include "adi_uart_def.h" 60 #include <adi_cyclecount.h> 92 #pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm008,Pm026 101 static ADI_UART_DEVICE_INFO uart_device_info[ ] =
108 (IRQn_Type)INTR_UART0_EVT,
112 #
if defined (__ADUCM4x50__)
118 (IRQn_Type)INTR_UART1_EVT,
125 static const ADI_UART_CONFIG gUARTCfg[ ] =
141 ((uint32_t)BITM_UART_FBR_FBEN)),
161 #if defined (__ADUCM4x50__) 176 ((uint32_t)BITM_UART_FBR_FBEN)),
199 static const uint8_t sFifoTriggers[] = {1u, 4u, 8u, 14u};
204 #define ADI_UART_NUM_DEVICES (sizeof(uart_device_info)/sizeof(ADI_UART_DEVICE_INFO)) 208 extern void UART0_Int_Handler(
void);
209 extern void UART1_Int_Handler(
void);
210 extern void DMA_UART0_TX_Int_Handler(
void);
211 extern void DMA_UART0_RX_Int_Handler(
void);
213 #if defined (__ADUCM4x50__) 214 extern void DMA_UART1_TX_Int_Handler(
void);
215 extern void DMA_UART1_RX_Int_Handler(
void);
219 static void RxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg);
220 static void RxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
224 ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelRx->pFillBuffer->pNextBuffer;
225 uint32_t nEvent = 0u;
240 if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA ==
true))
242 hDevice->nHwError |= nEvent;
243 pNextBuff->bInUse =
false;
247 hDevice->nHwError |= nEvent;
251 static void TxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg);
252 static void TxDmaErrorCallback(
void *pCBParam, uint32_t Event,
void *pArg) {
256 ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelTx->pFillBuffer->pNextBuffer;
257 uint32_t nEvent = 0u;
271 if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA ==
true))
273 hDevice->nHwError |= nEvent;
274 pNextBuff->bInUse =
false;
279 hDevice->nHwError |= nEvent;
316 uint32_t
const nDeviceNum,
319 uint32_t
const nMemSize,
323 uint16_t regFifoTrig = 0u;
336 if(uart_device_info[nDeviceNum].hDevice != NULL)
348 assert(nMemSize == (
sizeof(ADI_UART_DEVICE) +
sizeof(ADI_UART_DATA_CHANNEL)));
358 assert(nMemSize == (
sizeof(ADI_UART_DEVICE) + (
sizeof(ADI_UART_DATA_CHANNEL)*2u)));
371 memset(pMemory, 0, nMemSize);
375 hDevice->pUartInfo = &uart_device_info[nDeviceNum];
380 hDevice->pUARTRegs = uart_device_info[nDeviceNum].pUartRegs;
383 hDevice->eDirection = eDirection;
389 pMemory = ((uint8_t *)pMemory +(
sizeof(ADI_UART_DEVICE)));
397 hDevice->pChannelTx = (ADI_UART_DATA_CHANNEL *)pMemory;
400 hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
403 hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
404 hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
405 hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
412 hDevice->pChannelTx->pfSubmitBuffer = &uart_submittxbuffer;
414 hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1];
415 hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0];
427 pMemory = ((uint8_t *)pMemory +
sizeof(ADI_UART_DATA_CHANNEL));
432 hDevice->pChannelRx = (ADI_UART_DATA_CHANNEL *)pMemory;
435 hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
438 hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
439 hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
440 hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
446 hDevice->pChannelRx->pfSubmitBuffer = &uart_submitrxbuffer;
448 hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1];
449 hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0];
460 uart_init(hDevice, nDeviceNum);
465 hDevice->bRxFifoEn = ((hDevice->pUARTRegs->FCR & BITM_UART_FCR_FIFOEN) > 0u);
466 regFifoTrig = ((hDevice->pUARTRegs->FCR & BITM_UART_FCR_RFTRIG) >> BITP_UART_FCR_RFTRIG);
468 hDevice->nRxFifoTrig = sFifoTriggers[regFifoTrig];
474 uart_device_info[nDeviceNum].hDevice = hDevice;
478 NVIC_ClearPendingIRQ(hDevice->pUartInfo->eIRQn);
479 NVIC_EnableIRQ(hDevice->pUartInfo->eIRQn);
482 NVIC_EnableIRQ(hDevice->pUartInfo->eDMATx);
483 NVIC_EnableIRQ(hDevice->pUartInfo->eDMARx);
524 if(((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) ||
525 ((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL)) ||
526 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL)) ||
527 (hDevice->bAutobaudInProgress ==
true))
534 hDevice->pUARTRegs->IEN = 0x00U;
537 NVIC_DisableIRQ(hDevice->pUartInfo->eDMARx);
538 NVIC_DisableIRQ(hDevice->pUartInfo->eDMATx);
541 NVIC_DisableIRQ(hDevice->pUartInfo->eIRQn);
556 hDevice->pUartInfo->hDevice = NULL;
597 uint32_t
const nBufSize,
622 if(hDevice->bAutobaudInProgress ==
true)
644 if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
650 if((bDMA ==
true) && (nBufSize > DMA_TRANSFER_LIMIT))
658 hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer;
661 hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize;
666 hDevice->pChannelTx->pFreeBuffer->nIndex = 0U;
669 hDevice->pChannelTx->pFreeBuffer->bInUse =
true;
672 hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA;
680 hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
688 if (hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE)
691 hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
708 static void uart_submittxbuffer(
710 ADI_UART_BUFF_INFO *
const pBuffer
717 pADI_DMA0->SRCADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaTxChannelNum;
720 pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaTxChannelNum;
723 pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
726 pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
729 pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMASRCEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
731 pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMADSTEND = (uint32_t)&hDevice->pUARTRegs->TX;
733 pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMACDC = ((uint32_t)
ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
736 (0u << DMA_BITP_CTL_R_POWER) |
737 ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) |
738 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
740 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAT);
746 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ETBEI);
787 uint32_t
const nBufSize,
812 if(hDevice->bAutobaudInProgress ==
true)
835 if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
841 if((bDMA ==
true) && (nBufSize > DMA_TRANSFER_LIMIT))
849 hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer;
852 hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize;
857 hDevice->pChannelRx->pFreeBuffer->nIndex = 0U;
860 hDevice->pChannelRx->pFreeBuffer->bInUse =
true;
863 hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA;
871 hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
880 if (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE)
883 hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
900 static void uart_submitrxbuffer(
902 ADI_UART_BUFF_INFO *
const pBuffer
911 pADI_DMA0->DSTADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaRxChannelNum;
914 pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaRxChannelNum;
917 pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
920 pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
923 pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMASRCEND = (uint32_t)&hDevice->pUARTRegs->RX;
925 pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMADSTEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
927 pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMACDC = (uint32_t)(
ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_DST_INC) |
930 (0u << DMA_BITP_CTL_R_POWER) |
931 ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) |
932 (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
934 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAR);
940 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
972 void **
const ppBuffer,
986 if(hDevice->pChannelTx->pActiveBuffer->pStartAddress == NULL)
999 return(uart_getbuffer(hDevice, hDevice->pChannelTx, ppBuffer, pHwError));
1030 void **
const ppBuffer,
1044 if(hDevice->pChannelRx->pActiveBuffer->pStartAddress == NULL)
1057 return(uart_getbuffer(hDevice, hDevice->pChannelRx, ppBuffer, pHwError));
1079 ADI_UART_DATA_CHANNEL *pChannel,
1093 *ppBuffer = pChannel->pActiveBuffer->pStartAddress;
1096 pChannel->pActiveBuffer->pStartAddress = NULL;
1102 pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
1107 if(pChannel->pActiveBuffer->pStartAddress == NULL)
1109 pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
1113 if(hDevice->nHwError != 0u)
1116 *pHwError = hDevice->nHwError;
1119 hDevice->nHwError = 0u;
1168 void *
const pBuffer,
1169 uint32_t
const nBufSize,
1195 if(hDevice->bAutobaudInProgress ==
true)
1217 if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
1223 if((bDMA ==
true) && (nBufSize > DMA_TRANSFER_LIMIT))
1234 hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer;
1237 hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize;
1242 hDevice->pChannelTx->pFreeBuffer->nIndex = 0U;
1245 hDevice->pChannelTx->pFreeBuffer->bInUse =
true;
1248 hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA;
1256 hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
1258 hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
1261 return(uart_PendForBuffer(hDevice, hDevice->pChannelTx, pHwError));
1300 void *
const pBuffer,
1301 uint32_t
const nBufSize,
1327 if(hDevice->bAutobaudInProgress ==
true)
1349 if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
1355 if((bDMA ==
true) && (nBufSize > DMA_TRANSFER_LIMIT))
1369 hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer;
1372 hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize;
1377 hDevice->pChannelRx->pFreeBuffer->nIndex = 0U;
1380 hDevice->pChannelRx->pFreeBuffer->bInUse =
true;
1383 hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA;
1392 hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
1394 hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
1397 return(uart_PendForBuffer(hDevice, hDevice->pChannelRx, pHwError));
1418 ADI_UART_DATA_CHANNEL *pChannel,
1427 pChannel->pActiveBuffer->pStartAddress = NULL;
1434 pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
1439 if(pChannel->pActiveBuffer->pStartAddress == NULL)
1441 pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
1445 if(hDevice->nHwError != 0u)
1448 *pHwError = hDevice->nHwError;
1451 hDevice->nHwError = 0u;
1483 bool *
const pbAvailable
1502 *pbAvailable =
false;
1508 if (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)
1513 if (hDevice->pChannelTx->pActiveBuffer->bInUse ==
false)
1515 *pbAvailable =
true;
1539 bool *
const pbAvailable
1558 *pbAvailable =
false;
1564 if(hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)
1569 if (hDevice->pChannelRx->pActiveBuffer->bInUse ==
false)
1571 *pbAvailable =
true;
1598 bool *
const pbComplete
1610 *pbComplete =
false;
1615 if((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) == BITM_UART_LSR_TEMT)
1640 const ADI_CALLBACK pfCallback,
1641 void *
const pCBParam
1653 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
1654 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
1655 (hDevice->bAutobaudInProgress ==
true))
1662 hDevice->pfCallback = pfCallback;
1665 hDevice->pCBParam = pCBParam;
1704 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
1705 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
1706 (hDevice->bAutobaudInProgress ==
true))
1713 uint16_t nDataCfg = hDevice->pUARTRegs->LCR & (uint16_t)(~(BITM_UART_LCR_WLS |BITM_UART_LCR_STOP |BITM_UART_LCR_PEN));
1716 nDataCfg |= (uint16_t)(((uint16_t)((uint16_t)eWordLength |(uint16_t)eStopBits) |(uint16_t)eParity));
1719 hDevice->pUARTRegs->LCR = nDataCfg;
1753 uint16_t
const nDivC,
1754 uint8_t
const nDivM,
1755 uint16_t
const nDivN,
1767 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
1768 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
1774 if( (nDivM < 1u) || (nDivM > 3u)|| (nDivN > 2047u ) || (nOSR > 3u))
1782 hDevice->pUARTRegs->DIV = nDivC;
1783 hDevice->pUARTRegs->FBR = (uint16_t)((uint16_t)nDivN | (uint16_t)((uint16_t)nDivM <<BITP_UART_FBR_DIVM)) | (uint16_t)BITM_UART_FBR_FBEN;
1784 hDevice->pUARTRegs->LCR2 = nOSR;
1811 uint32_t *pnBaudRate,
1812 uint32_t *pAutobaudError
1824 if(pnBaudRate == NULL)
1835 if(hDevice->nAutobaudError != 0u)
1838 *pAutobaudError = hDevice->nAutobaudError;
1841 hDevice->nAutobaudError = 0u;
1847 *pnBaudRate = hDevice->nBaudRate;
1881 bool const bAutobaudCallbackMode
1893 if(((hDevice->eDirection !=
ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
1894 ((hDevice->eDirection !=
ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
1907 hDevice->pUARTRegs->ACR |=(BITM_UART_ACR_ABE | BITM_UART_ACR_DNIEN | BITM_UART_ACR_TOIEN |(1u << 4u) | (3u << 8u));
1910 hDevice->nBaudRate = 0u;
1913 hDevice->bAutobaudInProgress =
true;
1916 hDevice->bAutobaudCallbackMode = bAutobaudCallbackMode;
1921 hDevice->bAutobaudInProgress =
false;
1924 hDevice->pUARTRegs->ACR |= (uint16_t)(~(uint32_t)BITM_UART_ACR_ABE | ~(uint32_t)BITM_UART_ACR_DNIEN | ~(uint32_t)BITM_UART_ACR_TOIEN);
1927 hDevice->nBaudRate = 0u;
1967 hDevice->pUARTRegs->LCR |= BITM_UART_LCR_BRK;
1972 hDevice->pUARTRegs->LCR &= (uint16_t)~(BITM_UART_LCR_BRK);
2006 hDevice->pUARTRegs->MCR |= (BITM_UART_MCR_LOOPBACK);
2011 hDevice->pUARTRegs->MCR &= (uint16_t)~(BITM_UART_MCR_LOOPBACK);
2042 hDevice->pUARTRegs->FCR &= (uint16_t)~BITM_UART_FCR_RFTRIG;
2045 hDevice->pUARTRegs->FCR |= (uint16_t)eTriglevel;
2048 hDevice->nRxFifoTrig = sFifoTriggers[eTriglevel >> BITP_UART_FCR_RFTRIG];
2080 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_FIFOEN;
2081 hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
2083 hDevice->bRxFifoEn =
true;
2089 hDevice->pUARTRegs->FCR &= (uint16_t)~(BITM_UART_FCR_FIFOEN);
2091 hDevice->bRxFifoEn =
false;
2122 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR;
2152 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR;
2184 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI | BITM_UART_IEN_EDMAR);
2187 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR;
2190 hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
2193 memset(hDevice->pChannelRx->PingPong,0, sizeof (hDevice->pChannelRx->PingPong));
2195 hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1];
2196 hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0];
2199 hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
2200 hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
2201 hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
2204 hDevice->pUARTRegs->RX;
2233 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
2236 hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR;
2239 memset(hDevice->pChannelTx->PingPong,0, sizeof (hDevice->pChannelTx->PingPong));
2241 hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1];
2242 hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0];
2245 hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
2246 hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
2247 hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
2255 void UART0_Int_Handler(
void)
2259 Common_Uart_Interrupt_Handler(hDevice);
2260 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2267 #if defined (__ADUCM4x50__) 2269 void UART1_Int_Handler(
void)
2273 Common_Uart_Interrupt_Handler(hDevice);
2274 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2284 switch(hDevice->pUARTRegs->IIR & BITM_UART_IIR_STAT )
2289 case ENUM_UART_IIR_STAT_ETBEI:
2290 uart_TxDataHandler(hDevice);
2296 case ENUM_UART_IIR_STAT_RFTOI:
2299 uart_RxDataHandler(hDevice, hDevice->pUARTRegs->RFC);
2303 case ENUM_UART_IIR_STAT_ERBFI:
2305 uart_RxDataHandler(hDevice, hDevice->nRxFifoTrig);
2309 case ENUM_UART_IIR_STAT_RLSI:
2312 uint32_t nEvent = 0u;
2315 uint16_t nStatus = hDevice->pUARTRegs->LSR;
2318 if((BITM_UART_LSR_BI & nStatus) == BITM_UART_LSR_BI)
2323 hDevice->pUARTRegs->RX;
2332 else if((BITM_UART_LSR_FE & nStatus) == BITM_UART_LSR_FE)
2342 if((BITM_UART_LSR_PE & nStatus) == BITM_UART_LSR_PE)
2347 if((BITM_UART_LSR_OE & nStatus) == BITM_UART_LSR_OE)
2356 if((nEvent != 0u) && (hDevice->bAutobaudInProgress ==
false))
2361 hDevice->nHwError |= nEvent;
2368 case ENUM_UART_IIR_STAT_EDSSI:
2370 #if (ADI_UART_CFG_ENABLE_AUTOBAUD == 1) 2372 uint32_t nEvent = 0u;
2375 uint16_t nStatus = hDevice->pUARTRegs->ASRL & 0xFu;
2378 uint16_t acr = (hDevice->pUARTRegs->ACR & BITM_UART_ACR_ABE);
2381 if((nStatus != 0u) && (acr != 0u))
2393 nCount = (uint32_t)hDevice->pUARTRegs->ASRH << 12u;
2396 nCount |= (uint32_t)hDevice->pUARTRegs->ASRL >> 4u;
2399 if((nStatus & BITM_UART_ASRL_DONE) == BITM_UART_ASRL_DONE)
2404 if ((hDevice->pUARTRegs->FBR & 0x8000u) == 0x8000u)
2408 uint32_t nDivNSubtractor = 2048u;
2411 uint16_t nDivC = 1u;
2414 if(nCount < (8u << 3u))
2416 nDivN = ((nCount << 9u) / 8u) - nDivNSubtractor;
2420 else if(nCount < (8u << 4u))
2422 nDivN = ((nCount << 8u) / 8u) - nDivNSubtractor;
2427 else if(nCount < (8u << 5u))
2429 nDivN = ((nCount << 7u) / 8u) - nDivNSubtractor;
2436 nDivC = (uint16_t) (nCount / 32u / 8u);
2437 nDivN = ((nCount << 6u) / (8u * nDivC)) - nDivNSubtractor;
2453 hDevice->nBaudRate = ((nClock * 8u) / nCount);
2458 hDevice->nBaudRate = ((nClock * 8u) / nCount);
2465 if((hDevice->pfCallback != NULL) && (hDevice->bAutobaudCallbackMode ==
true))
2472 if((nStatus & BITM_UART_ASRL_BRKTO) == BITM_UART_ASRL_BRKTO)
2477 if((nStatus & BITM_UART_ASRL_NSETO) == BITM_UART_ASRL_NSETO)
2482 if((nStatus & BITM_UART_ASRL_NEETO) == BITM_UART_ASRL_NEETO)
2496 hDevice->nAutobaudError = nEvent;
2502 hDevice->pUARTRegs->RX;
2506 hDevice->pUARTRegs->ACR &=(uint16_t)~( BITM_UART_ACR_ABE |
2507 BITM_UART_ACR_DNIEN |
2508 BITM_UART_ACR_TOIEN );
2510 hDevice->bAutobaudInProgress =
false;
2521 void DMA_UART0_TX_Int_Handler(
void)
2526 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2532 void DMA_UART0_RX_Int_Handler(
void)
2537 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2543 #if defined(__ADUCM4x50__) 2545 void DMA_UART1_TX_Int_Handler(
void)
2550 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2556 void DMA_UART1_RX_Int_Handler(
void)
2561 #if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) 2574 static void uart_RxDataHandler(
ADI_UART_HANDLE hDevice, uint8_t nBytes)
2576 ADI_UART_BUFF_INFO *pFillBuffer = hDevice->pChannelRx->pFillBuffer;
2579 volatile uint8_t *pNextData = (uint8_t *)pFillBuffer->pStartAddress;
2581 bool activeBufferAvailable = ( (pNextData != NULL)
2582 && (pFillBuffer->bInUse ==
true)
2585 if(activeBufferAvailable)
2588 #if !defined(ADI_UART_DRAIN_RX_BUFFER) || (0==ADI_UART_DRAIN_RX_BUFFER) 2593 while ( (nBytes-- > 0)
2594 && (pFillBuffer->nIndex < pFillBuffer->nCount)
2600 pNextData[pFillBuffer->nIndex] = (uint8_t) hDevice->pUARTRegs->RX;
2603 pFillBuffer->nIndex++;
2611 if(pFillBuffer->nIndex == pFillBuffer->nCount)
2613 uart_ManageProcessedBuffer( hDevice, hDevice->pChannelRx
2626 while (activeBufferAvailable)
2629 nBytes = hDevice->pUARTRegs->RFC;
2640 pNextData[pFillBuffer->nIndex] = hDevice->pUARTRegs->RX;
2643 pFillBuffer->nIndex++;
2646 if (pFillBuffer->nIndex == pFillBuffer->nCount)
2649 uart_ManageProcessedBuffer(hDevice,
2650 hDevice->pChannelRx,
2654 pFillBuffer = hDevice->pChannelRx->pFillBuffer;
2655 pNextData = (uint8_t *)pFillBuffer->pStartAddress;
2658 activeBufferAvailable = ( (pNextData != NULL)
2659 && (pFillBuffer->bInUse ==
true)
2662 if (!activeBufferAvailable)
2679 if (hDevice->pfCallback != NULL)
2681 hDevice->pfCallback( hDevice->pCBParam
2690 if( (pFillBuffer->pStartAddress == NULL)
2691 && (pFillBuffer->bInUse ==
false)
2694 hDevice->pUARTRegs->RX;
2709 volatile uint8_t *pNextData;
2712 if((hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelTx->pFillBuffer->bInUse ==
true))
2715 pNextData = (uint8_t *)hDevice->pChannelTx->pFillBuffer->pStartAddress;
2718 hDevice->pUARTRegs->TX = (uint16_t)pNextData[hDevice->pChannelTx->pFillBuffer->nIndex];
2721 hDevice->pChannelTx->pFillBuffer->nIndex++;
2726 if(hDevice->pChannelTx->pFillBuffer->nIndex >= hDevice->pChannelTx->pFillBuffer->nCount)
2751 pChannel->pFillBuffer->bInUse =
false;
2753 pChannel->pFillBuffer = pChannel->pFillBuffer->pNextBuffer;
2758 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
2765 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_EDMAR);
2767 if (hDevice->bRxFifoEn !=
true)
2771 hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI);
2779 uint32_t nEvent = hDevice->nHwError;
2780 hDevice->nHwError = 0u;
2782 uint32_t *pBuffer = pChannel->pActiveBuffer->pStartAddress;
2785 pChannel->pActiveBuffer->pStartAddress = NULL;
2791 pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
2797 if(pChannel->pActiveBuffer->pStartAddress == NULL)
2799 pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
2808 hDevice->pfCallback(hDevice->pCBParam, (uint32_t)eEvent, (
void*)pBuffer);
2821 while( ((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) ||(hDevice->pUARTRegs->TFC != 0u))
2829 if( pChannel->pActiveBuffer->pNextBuffer->pStartAddress==NULL)
2831 pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
2844 if(pChannel->pFillBuffer->bInUse ==
true)
2846 pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer);
2862 ADI_UART_CONFIG
const* pUARTCfg = &gUARTCfg[nDeviceNum];
2865 hDevice->pUARTRegs->LCR = pUARTCfg->LCR;
2868 hDevice->pUARTRegs->DIV = pUARTCfg->DIV;
2871 hDevice->pUARTRegs->FBR = pUARTCfg->FBR;
2874 hDevice->pUARTRegs->LCR2 = pUARTCfg->LCR2;
2877 hDevice->pUARTRegs->FCR = pUARTCfg->FCR;
2880 hDevice->pUARTRegs->RSC = pUARTCfg->RSC;
2883 hDevice->pUARTRegs->IEN = pUARTCfg->IEN;
2906 if((hDevice == uart_device_info[i].hDevice) && (hDevice != NULL))
#define ADI_UART0_CFG_DIVC
ADI_DMA_RESULT adi_dma_RegisterCallback(DMA_CHANn_TypeDef const eChannelID, ADI_CALLBACK const pfCallback, void *const pCBParam)
Register a call-back function for a DMA channel.
#define ADI_UART1_CFG_STOP_BIT
#define ADI_UART0_CFG_ENABLE_STICKY_PARITY
#define ADI_CYCLECOUNT_STORE(id)
#define ADI_UART1_CFG_DIVC
ADI_UART_RESULT adi_uart_Close(ADI_UART_HANDLE const hDevice)
Uninitialize the memory for the specified UART instance.
#define ADI_CYCLECOUNT_ISR_UART
ADI_UART_RESULT adi_uart_SetConfiguration(ADI_UART_HANDLE const hDevice, ADI_UART_PARITY const eParity, ADI_UART_STOPBITS const eStopBits, ADI_UART_WORDLEN const eWordLength)
Configuration of UART data.
#define ADI_UART0_CFG_TRIG_LEVEL
#define ADI_UART1_CFG_ENABLE_PARITY
#define ADI_UART0_CFG_WORD_LENGTH
ADI_UART_RESULT adi_uart_IsRxBufferAvailable(ADI_UART_HANDLE const hDevice, bool *const pbAvailable)
Peek function to know if a filled buffer is available.
#define ADI_UART0_CFG_DEASSERTION
#define ADI_UART0_CFG_DIVN
#define ADI_UART0_CFG_PARITY_SELECTION
#define ADI_UART_NUM_DEVICES
#define ADI_UART1_CFG_DISABLE_RX
#define ADI_UART1_CFG_OSR
#define ADI_UART0_CFG_STOP_BIT
ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel(ADI_UART_HANDLE const hDevice, ADI_UART_TRIG_LEVEL const eTriglevel)
Sets the RX FIFO trigger level. This will be the amount of data in the FIFO that will trigger an inte...
ADI_UART_RESULT adi_uart_GetRxBuffer(ADI_UART_HANDLE const hDevice, void **const ppBuffer, uint32_t *pHwError)
Transfer buffer ownership from the device back to the API if the data receive has completed...
#define ADI_UART1_CFG_ENABLE_STICKY_PARITY
ADI_UART_RESULT adi_uart_FlushTxFifo(ADI_UART_CONST_HANDLE const hDevice)
To flush the TX FIFO.
ADI_UART_RESULT adi_uart_SubmitTxBuffer(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA)
Submit a "filled" buffer for transmitting data in ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This function sets up the apropriate interrupts associated with the transaction and marks the buffer as submitted.
ADI_UART_RESULT adi_uart_RegisterCallback(ADI_UART_HANDLE const hDevice, const ADI_CALLBACK pfCallback, void *const pCBParam)
Registering a callback function.
#define ADI_UART0_CFG_OSR
ADI_UART_RESULT adi_uart_FlushRxChannel(ADI_UART_CONST_HANDLE const hDevice)
Flush the Rx channel and disable interrupts. This will stop any buffers in flight and clear out any d...
ADI_UART_RESULT adi_uart_FlushTxChannel(ADI_UART_CONST_HANDLE const hDevice)
Flush the Tx channel and disable interrupts.This will stop any buffers in flight and clear out any da...
#define ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT
#define ADI_CYCLECOUNT_ISR_DMA_UART_RX
#define ADI_UART1_CFG_DEASSERTION
ADI_UART_RESULT adi_uart_EnableFifo(ADI_UART_HANDLE const hDevice, bool const bEnable)
Enables internal FIFO as to work in 16550 mode. This helps to minimize system overhead and maximize s...
ADI_UART_RESULT adi_uart_GetTxBuffer(ADI_UART_HANDLE const hDevice, void **const ppBuffer, uint32_t *pHwError)
Transfer buffer ownership from the device back to the API if the data transmit has completed...
#define ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT
ADI_UART_RESULT adi_uart_SubmitRxBuffer(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA)
Submit an empty buffer for receiving the data in ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This will set up the Rx channel for notification on incoming data using either the DMA or UART interrupts, as well as mark the buffer as submitted.
#define ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT
#define ADI_UART0_CFG_DISABLE_RX
ADI_UART_RESULT adi_uart_Write(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA, uint32_t *pHwError)
Submit the buffer for transmitting the data in ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function will not return until the entire buffer is transmitted. Returns error if this function is called when device is operating in ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. i.e Function "adi_uart_SubmitTxBuffer()" is called and the transfer is not yet complete.
#define ADI_UART0_CFG_HOLD_TX
#define ADI_UART_BIDIR_MEMORY_SIZE
ADI_UART_RESULT adi_uart_FlushRxFifo(ADI_UART_CONST_HANDLE const hDevice)
Flush the RX FIFO.
ADI_UART_RESULT adi_uart_ForceTxBreak(ADI_UART_HANDLE const hDevice, bool const bEnable)
Forces the UART to send out a break signal.
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
ADI_UART_RESULT adi_uart_Read(ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t const nBufSize, bool const bDMA, uint32_t *pHwError)
Submit the buffer for reading the data in ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function...
ADI_UART_RESULT adi_uart_EnableLoopBack(ADI_UART_HANDLE const hDevice, bool const bEnable)
Enable/Disable the loopback for the specified UART device.
#define ADI_UART1_CFG_SOUT_POLARITY
ADI_UART_RESULT adi_uart_IsTxBufferAvailable(ADI_UART_HANDLE const hDevice, bool *const pbAvailable)
Peek function to know if an empty buffer is avilable.
#define ADI_UART1_CFG_DIVN
#define ADI_UART1_CFG_TRIG_LEVEL
struct _ADI_UART_DEVICE * ADI_UART_HANDLE
#define ADI_CYCLECOUNT_ISR_DMA_UART_TX
#define ADI_UART1_CFG_PARITY_SELECTION
ADI_UART_RESULT adi_uart_Open(uint32_t const nDeviceNum, ADI_UART_DIRECTION const eDirection, void *pMemory, uint32_t const nMemSize, ADI_UART_HANDLE *const phDevice)
Initialization function for the UART device.
#define ADI_UART1_CFG_HOLD_TX
#define ADI_UART0_CFG_DIVM
#define ADI_UART1_CFG_WORD_LENGTH
const struct _ADI_UART_DEVICE * ADI_UART_CONST_HANDLE
void adi_dma_Init(void)
Initialize the DMA peripheral.
#define ADI_UART1_CFG_ENABLE_FIFO
#define ADI_UART0_CFG_ENABLE_FIFO
ADI_UART_RESULT adi_uart_IsTxComplete(ADI_UART_HANDLE const hDevice, bool *const pbComplete)
Function to let the API know if all the data had been drained from the Tx shift registers.
ADI_UART_RESULT adi_uart_ConfigBaudRate(ADI_UART_HANDLE const hDevice, uint16_t const nDivC, uint8_t const nDivM, uint16_t const nDivN, uint8_t const nOSR)
Set baudrate by configuring the fractional dividors.
ADI_UART_RESULT adi_uart_EnableAutobaud(ADI_UART_HANDLE const hDevice, bool const bEnable, bool const bAutobaudCallbackMode)
Enable/Disable UART autobaud detection as well as configures the device for autobaud detection...
#define ADI_UART1_CFG_DIVM
#define ADI_UART0_CFG_SOUT_POLARITY
ADI_UART_RESULT adi_uart_GetBaudRate(ADI_UART_HANDLE const hDevice, uint32_t *pnBaudRate, uint32_t *pAutobaudError)
Get the baudrate of the UART device instance. This is used in the scenario when a callback has not be...
#define ADI_UART_UNIDIR_MEMORY_SIZE
#define ADI_UART0_CFG_ENABLE_PARITY
#define ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT