ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_spi_data.c
1 /*
2  *****************************************************************************
3  * @file: adi_spi_data.c
4  * @brief: Data declaration for SPORT Device Driver
5  *****************************************************************************
6 
7 Copyright (c) 2016 Analog Devices, Inc.
8 
9 All rights reserved.
10 
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13  - Redistributions of source code must retain the above copyright notice,
14  this list of conditions and the following disclaimer.
15  - Redistributions in binary form must reproduce the above copyright notice,
16  this list of conditions and the following disclaimer in the documentation
17  and/or other materials provided with the distribution.
18  - Modified versions of the software must be conspicuously marked as such.
19  - This software is licensed solely and exclusively for use with processors
20  manufactured by or for Analog Devices, Inc.
21  - This software may not be combined or merged with other code in any manner
22  that would cause the software to become subject to terms and conditions
23  which differ from those listed here.
24  - Neither the name of Analog Devices, Inc. nor the names of its
25  contributors may be used to endorse or promote products derived
26  from this software without specific prior written permission.
27  - The use of this software may or may not infringe the patent rights of one
28  or more patent holders. This license does not release you from the
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30  to use this software.
31 
32 THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
33 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
34 INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
36 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
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42 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 POSSIBILITY OF SUCH DAMAGE.
44 
45 *****************************************************************************/
46 
47 #ifndef _ADI_SPI_DATA_C_
48 #define _ADI_SPI_DATA_C_
49 
52 #include "adi_spi_def.h"
53 #include "adi_spi_config.h"
54 #include <drivers/dma/adi_dma.h>
55 
56 /* Stores the information about the specific device */
57 static ADI_SPI_DEVICE_INFO spi_device_info [ADI_SPI_NUM_INSTANCES]=
58 {
59  {
60  DMA0_CH4_DONE_IRQn,
61  SPI0_TX_CHANn,
62  DMA0_CH5_DONE_IRQn,
63  SPI0_RX_CHANn,
64  (volatile ADI_SPI_TypeDef *)pADI_SPI0,
65  SPI0_EVT_IRQn,
66  NULL
67  },
68  {
69  DMA0_CH6_DONE_IRQn,
70  SPI1_TX_CHANn,
71  DMA0_CH7_DONE_IRQn,
72  SPI1_RX_CHANn,
73  (volatile ADI_SPI_TypeDef *)pADI_SPI1,
74  SPI1_EVT_IRQn,
75  NULL
76  },
77 
78  {
79  DMA0_CH0_DONE_IRQn,
80  SPI2_TX_CHANn,
81  DMA0_CH1_DONE_IRQn,
82  SPI2_RX_CHANn,
83  (volatile ADI_SPI_TypeDef *)pADI_SPI2,
84  SPI2_EVT_IRQn,
85  NULL
86  }
87 };
88 
89 /* SPI Application configuration array */
90 static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] =
91 {
92  /* Initialize SPI0 Instance configuration. */
93  {
94  /**** SPI_CFG register configuration *** */
95  (( ADI_SPI0_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) |
96  ( ADI_SPI0_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) |
97  ( ADI_SPI0_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) |
98  ( ADI_SPI0_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) |
99  ( ADI_SPI0_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) |
100  ( ADI_SPI0_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) |
101  ( ADI_SPI0_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) |
102  ( ADI_SPI0_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) |
103  ( ADI_SPI0_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) |
104  ( ADI_SPI0_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) |
105  ( ADI_SPI0_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) |
106  ( ADI_SPI0_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) |
107  ( ADI_SPI0_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) |
108  ( ADI_SPI0_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )),
109 
110  /**** SPI_DIV buad rate selection register *** */
111  (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\
112  << BITP_SPI_DIV_VALUE )
113  },
114  /* Initialize SPI1 Instance configuration. */
115  {
116  /**** SPI_CFG register configuration *** */
117  (( ADI_SPI1_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) |
118  ( ADI_SPI1_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) |
119  ( ADI_SPI1_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) |
120  ( ADI_SPI1_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) |
121  ( ADI_SPI1_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) |
122  ( ADI_SPI1_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) |
123  ( ADI_SPI1_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) |
124  ( ADI_SPI1_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) |
125  ( ADI_SPI1_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) |
126  ( ADI_SPI1_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) |
127  ( ADI_SPI1_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) |
128  ( ADI_SPI1_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) |
129  ( ADI_SPI1_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) |
130  ( ADI_SPI1_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )),
131 
132  /**** SPI_DIV buad rate selection register *** */
133  (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\
134  << BITP_SPI_DIV_VALUE )
135  },
136  /* Initialize SPI2 Instance configuration. */
137  {
138  /**** SPI_CFG register configuration *** */
139  (( ADI_SPI2_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) |
140  ( ADI_SPI2_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) |
141  ( ADI_SPI2_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) |
142  ( ADI_SPI2_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) |
143  ( ADI_SPI2_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) |
144  ( ADI_SPI2_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) |
145  ( ADI_SPI2_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) |
146  ( ADI_SPI2_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) |
147  ( ADI_SPI2_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) |
148  ( ADI_SPI2_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) |
149  ( ADI_SPI2_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) |
150  ( ADI_SPI2_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) |
151  ( ADI_SPI2_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) |
152  ( ADI_SPI2_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )),
153 
154  /**** SPI_DIV buad rate selection register *** */
155  (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\
156  << BITP_SPI_DIV_VALUE )
157  }
158 };
159 
162 #endif /* _ADI_SPI_DATA_C_ */
#define ADI_SPI2_CFG_ENABLE
#define ADI_SPI1_CFG_RX_OVERFLOW
#define ADI_SPI0_CFG_TRANSFER_INITIATE
#define ADI_SPI2_CFG_WIRED_OR
#define ADI_SPI1_CFG_CONTINUOUS
#define ADI_SPI1_CFG_CSERR_RESET
#define ADI_SPI1_CFG_WIRED_OR
#define ADI_SPI0_CFG_MISO_ENABLE
#define ADI_SPI1_CFG_BIT_RATE
#define ADI_SPI1_CFG_TX_FLUSH
#define ADI_CFG_SYSTEM_CLOCK_HZ
#define ADI_SPI2_CFG_BIT_RATE
#define ADI_SPI0_CFG_LOOPBACK
#define ADI_SPI2_CFG_TX_FLUSH
#define ADI_SPI0_CFG_LSB_MSB
#define ADI_SPI1_CFG_MISO_ENABLE
#define ADI_SPI2_CFG_RX_OVERFLOW
#define ADI_SPI1_CFG_CLK_PHASE
#define ADI_SPI0_CFG_CONTINUOUS
#define ADI_SPI0_CFG_CLK_POLARITY
#define ADI_SPI0_CFG_RX_OVERFLOW
#define ADI_SPI0_CFG_WIRED_OR
#define ADI_SPI1_CFG_CLK_POLARITY
#define ADI_SPI1_CFG_ENABLE
#define ADI_SPI0_CFG_ENABLE
#define ADI_SPI1_CFG_TRANSFER_INITIATE
#define ADI_SPI0_CFG_BIT_RATE
#define ADI_SPI1_CFG_LSB_MSB
#define ADI_SPI0_CFG_CSERR_RESET
#define ADI_SPI2_CFG_TRANSFER_INITIATE
#define ADI_SPI2_CFG_MISO_ENABLE
#define ADI_SPI0_CFG_TX_FLUSH
#define ADI_SPI1_CFG_RX_FLUSH
#define ADI_SPI1_CFG_LOOPBACK
#define ADI_SPI2_CFG_LOOPBACK
#define ADI_SPI2_CFG_CSERR_RESET
#define ADI_SPI0_CFG_RX_FLUSH
#define ADI_SPI0_CFG_CLK_PHASE
#define ADI_SPI2_CFG_CONTINUOUS
#define ADI_SPI2_CFG_CLK_PHASE
#define ADI_SPI2_CFG_CLK_POLARITY
#define ADI_SPI2_CFG_LSB_MSB
#define ADI_SPI0_CFG_TX_UNDERFLOW
#define ADI_SPI2_CFG_TX_UNDERFLOW
#define ADI_SPI1_CFG_TX_UNDERFLOW
#define ADI_SPI2_CFG_RX_FLUSH