ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_flash_def.h
1 
46 #ifndef ADI_FLASH_DEF_H
47 #define ADI_FLASH_DEF_H
48 
51 #include <drivers/dma/adi_dma.h>
52 #include <adi_flash_config.h>
53 
54 #include <drivers/flash/adi_flash.h>
55 
56 /* fixed number of flash controllers */
57 #define ADI_FEE_NUM_INSTANCES (1u)
58 
59 #if defined (__ADUCM4x50__)
60 /* STATUS register error mask */
61 #define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_ACCESS_MODE \
62  | BITM_FLCC_STAT_CACHESRAMPERR \
63  | BITM_FLCC_STAT_ECCDCODE \
64  | BITM_FLCC_STAT_ECCINFOSIGN \
65  | BITM_FLCC_STAT_SIGNERR \
66  | BITM_FLCC_STAT_OVERLAP \
67  | BITM_FLCC_STAT_ECCRDERR \
68  | BITM_FLCC_STAT_ECCERRCMD \
69  | BITM_FLCC_STAT_SLEEPING \
70  | BITM_FLCC_STAT_CMDFAIL)
71 #elif defined (__ADUCM302x__)
72 #define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_CACHESRAMPERR \
73  | BITM_FLCC_STAT_ECCDCODE \
74  | BITM_FLCC_STAT_ECCINFOSIGN \
75  | BITM_FLCC_STAT_SIGNERR \
76  | BITM_FLCC_STAT_OVERLAP \
77  | BITM_FLCC_STAT_ECCRDERR \
78  | BITM_FLCC_STAT_ECCERRCMD \
79  | BITM_FLCC_STAT_SLEEPING \
80  | BITM_FLCC_STAT_CMDFAIL)
81 #endif
82 
83 #if defined(__ECC__)
84 #define ALIGN
85 #define ALIGN4 _Pragma("align(4)")
86 #elif defined(__ICCARM__)
87 #define ALIGN _Pragma("pack()")
88 #define ALIGN4 _Pragma("pack(4)")
89 #elif defined (__GNUC__)
90 #define ALIGN _Pragma("pack()")
91 #define ALIGN4 _Pragma("pack(4)")
92 #endif
93 
94 /* Flash Size and Page/Block macros:
95  512kB total user space, broken up as
96  256-pages, 2kB/page
97  32-blocks, 16kB/block
98  8 pages/block
99 */
100 #if defined (__ADUCM4x50__)
101 #define FEE_FLASH_SIZE (0x80000u) /* 512kB total */
102 #define FEE_BLOCK_SHIFT (14u) /* 16kB block size */
103 
104 #elif defined (__ADUCM302x__)
105 #define FEE_FLASH_SIZE (0x40000u) /* 256kB total */
106 #define FEE_BLOCK_SHIFT (13u) /* 8kB block size */
107 #else
108 #error Flash driver is not ported to this processor
109 #endif
110 
111 #define FEE_PAGE_SHIFT (11u) /* 2kB page size */
112 #define FEE_MAX_NUM_PAGES (FEE_FLASH_SIZE >> FEE_PAGE_SHIFT) /* max number of pages */
113 #define FEE_MAX_NUM_BLOCKS (FEE_FLASH_SIZE >> FEE_BLOCK_SHIFT) /* max number of blocks (32) */
114 
115 #if (ADI_FEE_CFG_ECC_START_PAGE >= FEE_MAX_NUM_PAGES)
116 #error "ADI_FEE_CFG_ECC_START_PAGE range is invalid"
117 #endif
118 
119 
120 /* INTERNAL DRIVER STATIC FUNCTION PROTOTYPES */
121 
122 /* Send a command to the flash controller, but does no pend on it... */
123 static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd);
124 
125 /* generic transfer initiator... dispatches to InitiatePioTransfer() or InitiateDmaTransfer() */
126 static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice);
127 
128 /* PIO initiator */
129 static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice);
130 
131 /* DMA initiator */
132 static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice);
133 
134 /* interrupt handlers */
135 void Flash0_Int_Handler(void);
136 void DMA_FLASH0_Int_Handler (void);
137 
138 /* INTERNAL DRIVER DATATYPES */
139 
140 /*
141  *****************************************************************************
142  * FEE Configuration structure.
143  *****************************************************************************/
144 typedef struct __ADI_FEE_CONFIG {
145  uint32_t eccIrqEnables; /* ECC interrupt enables. */
146  uint32_t param0; /* TIME_PARAM0 register. */
147  uint32_t param1; /* TIME_PARAM1 register. */
148  uint32_t abortEnableLo; /* Lower interrupt abort enables (IRQs 0-31). */
149  uint32_t abortEnableHi; /* Upper interrupt abort enables (IRQs 32-63.) */
150  uint32_t eccConfig; /* ECC_CFG register. */
151 } ADI_FEE_CONFIG;
152 
153 
154 /* Flash physical device instance data */
155 typedef struct __ADI_FEE_DEVICE_INFO {
156 
157  ADI_FLCC_TypeDef *pDev; /* Pointer to the physical controller. */
158  IRQn_Type pioIrqNum; /* The flash controller PIO interrupt number. */
159  IRQn_Type dmaIrqNum; /* The flash controller DMA interrupt number. */
160  DMA_CHANn_TypeDef dmaChanNum; /* The flash controller DMA channel number. */
161  ADI_FEE_CONFIG *pConfig; /* Pointer to user config info. */
162  ADI_FEE_HANDLE hDevice; /* Pointer the device memory (supplied by the application). */
163 
164 } ADI_FEE_DEVICE_INFO;
165 
166 
167 /* Flash driver instance data structure */
168 typedef struct __ADI_FEE_DEV_DATA_TYPE {
169 
170  /* make sure to synchronize ANY size changes with ADI_FLASH_MEMORY_SIZE macro in adi_flash.h */
171 
172  /* NOTE: "volatile" storage class on all interrupt-modified valuables */
173 
174  /* device attributes */
175  ADI_FLCC_TypeDef *pDev; /* Pointer top physical flash controller. */
176  ADI_FEE_DEVICE_INFO *pDevInfo; /* Pointer to hardware device attributes. */
177 
178  /* callback info */
179  ADI_CALLBACK pfCallback; /* Registered callback function address. */
180  void *pCBParam; /* Registered callback user parameter. */
181 
182  /* internal driver state variables */
183  bool bUseDma; /* DMA control flag (from user). */
184  bool bSubmitCalled; /* Flag to identify if a buffer was "submitted". */
185  volatile uint32_t FlashStatusCopy; /* Clop of latest flash status register. */
186  volatile uint32_t feeError; /* Flash error collector. */
187  volatile ADI_FEE_RESULT dmaError; /* DMA error collector. */
188  volatile bool bTransferInProgress; /* Flag indicating if a transfer is in progress. */
189 
190  /* data info */
191  volatile uint32_t *pNextWriteAddress; /* Pointer to next write data in flash space. */
192  volatile uint32_t *pNextReadAddress; /* Pointer to next read data in user buffer. */
193  volatile uint32_t nRemainingBytes; /* Number of remaining bytes still to transfer. */
194 
195  SEM_VAR_DECLR /* Blocking object: "Semaphore" for rtos, "bLowPowerExitFlag" for non-rtos. */
196 
197 } ADI_FEE_DEV_DATA_TYPE;
198 
201 #endif /* ADI_FLASH_DEF_H */
struct __ADI_FEE_DEV_DATA_TYPE * ADI_FEE_HANDLE
Definition: adi_flash.h:91
ADI_FEE_RESULT
Definition: adi_flash.h:68