ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
Static Configuration

Macros

#define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL   (0u)
 
#define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL   (1u)
 
#define ADI_CFG_SPORT0A_LSB_FIRST   (0u)
 
#define ADI_CFG_SPORT0A_SERIAL_WLEN   (32u)
 
#define ADI_CFG_SPORT0A_INTERNAL_CLK   (1u)
 
#define ADI_CFG_SPORT0A_OPERATION_MODE   (0u)
 
#define ADI_CFG_SPORT0A_CLOCK_EDGE   (0u)
 
#define ADI_CFG_SPORT0A_FS_REQUIRED   (1u)
 
#define ADI_CFG_SPORT0A_INTERNAL_FS   (0u)
 
#define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS   (0u)
 
#define ADI_CFG_SPORT0A_ACTIVE_LOW_FS   (0u)
 
#define ADI_CFG_SPORT0A_LATE_FS   (0u)
 
#define ADI_CFG_SPORT0A_ENABLE_PACKING   (0u)
 
#define ADI_CFG_SPORT0A_FS_ERROR_OPERATION   (1u)
 
#define ADI_CFG_SPORT0A_GATED_CLOCK   (0u)
 
#define ADI_CFG_SPORT0A_CLOCK_DIVISOR   (2u)
 
#define ADI_CFG_SPORT0A_FS_DIVISOR   (0x40u)
 
#define ADI_CFG_SPORT0A_CONVT_FS_DURATION   (1u)
 
#define ADI_CFG_SPORT0A_CONVT_POLARITY   (0u)
 
#define ADI_CFG_SPORT0A_CONVT_WIDTH   (1u)
 
#define ADI_CFG_SPORT0B_LSB_FIRST   (0u)
 
#define ADI_CFG_SPORT0B_SERIAL_WLEN   (32u)
 
#define ADI_CFG_SPORT0B_INTERNAL_CLK   (1u)
 
#define ADI_CFG_SPORT0B_OPERATION_MODE   (0u)
 
#define ADI_CFG_SPORT0B_CLOCK_EDGE   (0u)
 
#define ADI_CFG_SPORT0B_FS_REQUIRED   (1u)
 
#define ADI_CFG_SPORT0B_INTERNAL_FS   (1u)
 
#define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS   (0u)
 
#define ADI_CFG_SPORT0B_ACTIVE_LOW_FS   (0u)
 
#define ADI_CFG_SPORT0B_LATE_FS   (0u)
 
#define ADI_CFG_SPORT0B_ENABLE_PACKING   (0u)
 
#define ADI_CFG_SPORT0B_FS_ERROR_OPERATION   (1u)
 
#define ADI_CFG_SPORT0B_GATED_CLOCK   (0u)
 
#define ADI_CFG_SPORT0B_CLOCK_DIVISOR   (2u)
 
#define ADI_CFG_SPORT0B_FS_DIVISOR   (0x40u)
 
#define ADI_CFG_SPORT0B_CONVT_FS_DURATION   (1u)
 
#define ADI_CFG_SPORT0B_CONVT_POLARITY   (0u)
 
#define ADI_CFG_SPORT0B_CONVT_WIDTH   (1u)
 

Detailed Description

Macro Definition Documentation

◆ ADI_CFG_SPORT0A_ENABLE_FSMUXSEL

#define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL   (0u)

Frame Sync Multiplexer Select.
0 - Disable frame sync multiplexing
1 - Enable frame sync multiplexing.

Definition at line 61 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_ENABLE_CKMUXSEL

#define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL   (1u)

Clock Multiplexer Select.
0 - Disable serial clock multiplexing
1 - Enable serial clock multiplexing.

Definition at line 68 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_LSB_FIRST

#define ADI_CFG_SPORT0A_LSB_FIRST   (0u)

Least-Significant Bit First.
0 - MSB first sent/received.
1 - LSB first sent/received.

Definition at line 75 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_SERIAL_WLEN

#define ADI_CFG_SPORT0A_SERIAL_WLEN   (32u)

Serial Word Length in bits.
1 - 32 - SPORT word length

Definition at line 82 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_INTERNAL_CLK

#define ADI_CFG_SPORT0A_INTERNAL_CLK   (1u)

Internal Clock.
0 - External clock.
1 - Internal clock.

Definition at line 90 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_OPERATION_MODE

#define ADI_CFG_SPORT0A_OPERATION_MODE   (0u)

Operation Mode
0 - DSP standard.
1 - Timer_enable mode.

Definition at line 97 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_CLOCK_EDGE

#define ADI_CFG_SPORT0A_CLOCK_EDGE   (0u)

Clock Rising Edge
0 - Clock falling edge
1 - Clock rising edge.

Definition at line 105 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_FS_REQUIRED

#define ADI_CFG_SPORT0A_FS_REQUIRED   (1u)

Frame Sync Required
0 - No frame sync required
1 - Frame sync required.

Definition at line 112 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_INTERNAL_FS

#define ADI_CFG_SPORT0A_INTERNAL_FS   (0u)

Internal Frame Sync
0 - External frame sync
1 - Internal frame sync

Definition at line 119 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS

#define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS   (0u)

Data-Independent Frame Sync
0 - Data-dependent frame sync
1 - Data-independent frame

Definition at line 127 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_ACTIVE_LOW_FS

#define ADI_CFG_SPORT0A_ACTIVE_LOW_FS   (0u)

Active-Low Frame Sync
0 - Active high frame sync
1 - Active low frame sync

Definition at line 134 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_LATE_FS

#define ADI_CFG_SPORT0A_LATE_FS   (0u)

Late Frame Sync
0 - Early frame sync
1 - Late frame sync

Definition at line 141 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_ENABLE_PACKING

#define ADI_CFG_SPORT0A_ENABLE_PACKING   (0u)

Enable Packing
0 - Disable
1 - 8-bit packing enable
2 - 16-bit packing enable

Definition at line 149 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_FS_ERROR_OPERATION

#define ADI_CFG_SPORT0A_FS_ERROR_OPERATION   (1u)

Frame Sync Error Operation 0 - Flag the Frame Sync error
1 - When frame Sync error occurs, discard the receive data

Definition at line 156 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_GATED_CLOCK

#define ADI_CFG_SPORT0A_GATED_CLOCK   (0u)

Enabling Gated Clock
0 - Disable Gated Clock
1 - Enable Gated Clock

Definition at line 163 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_CLOCK_DIVISOR

#define ADI_CFG_SPORT0A_CLOCK_DIVISOR   (2u)

Serial Clock divisor.
0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial clock (ACLK) from the processor system clock (PCLK).

Definition at line 170 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_FS_DIVISOR

#define ADI_CFG_SPORT0A_FS_DIVISOR   (0x40u)

Frame Sync Divisor.
0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock cycles that the half SPORT counts before generating a frame sync pulse.

Definition at line 177 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_CONVT_FS_DURATION

#define ADI_CFG_SPORT0A_CONVT_FS_DURATION   (1u)

CONVT to FS duration.
0 - 128 - Specify the value of the number of clocks which would be programmed corresponding to the desired time duration from assertion of CONVT signal to Frame sync signal

Definition at line 186 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_CONVT_POLARITY

#define ADI_CFG_SPORT0A_CONVT_POLARITY   (0u)

Polarity of the Convt signal.
0 - Active High Polarity
1 - Active low Polarity

Definition at line 193 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0A_CONVT_WIDTH

#define ADI_CFG_SPORT0A_CONVT_WIDTH   (1u)

CONVT signal width.
0 - 15 - Specify the value of the number of serial clocks for which CONVT signal should be active

Definition at line 201 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_LSB_FIRST

#define ADI_CFG_SPORT0B_LSB_FIRST   (0u)

Least-Significant Bit First.
0 - MSB first sent/received.
1 - LSB first sent/received.

Definition at line 217 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_SERIAL_WLEN

#define ADI_CFG_SPORT0B_SERIAL_WLEN   (32u)

Serial Word Length in bits.
1 - 32 - SPORT word length

Definition at line 224 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_INTERNAL_CLK

#define ADI_CFG_SPORT0B_INTERNAL_CLK   (1u)

Internal Clock.
0 - External clock.
1 - Internal clock.

Definition at line 232 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_OPERATION_MODE

#define ADI_CFG_SPORT0B_OPERATION_MODE   (0u)

Operation Mode
0 - DSP standard.
1 - Timer_enable mode.

Definition at line 239 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_CLOCK_EDGE

#define ADI_CFG_SPORT0B_CLOCK_EDGE   (0u)

Clock Rising Edge
0 - Clock falling edge
1 - Clock rising edge.

Definition at line 247 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_FS_REQUIRED

#define ADI_CFG_SPORT0B_FS_REQUIRED   (1u)

Frame Sync Required
0 - No frame sync required
1 - Frame sync required.

Definition at line 254 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_INTERNAL_FS

#define ADI_CFG_SPORT0B_INTERNAL_FS   (1u)

Internal Frame Sync
0 - External frame sync
1 - Internal frame sync

Definition at line 261 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS

#define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS   (0u)

Data-Independent Frame Sync
0 - Data-dependent frame sync
1 - Data-independent frame

Definition at line 269 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_ACTIVE_LOW_FS

#define ADI_CFG_SPORT0B_ACTIVE_LOW_FS   (0u)

Active-Low Frame Sync
0 - Active high frame sync
1 - Active low frame sync

Definition at line 276 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_LATE_FS

#define ADI_CFG_SPORT0B_LATE_FS   (0u)

Late Frame Sync
0 - Early frame sync
1 - Late frame sync

Definition at line 283 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_ENABLE_PACKING

#define ADI_CFG_SPORT0B_ENABLE_PACKING   (0u)

Enable Packing
0 - Disable
1 - 8-bit packing enable
2 - 16-bit packing enable

Definition at line 291 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_FS_ERROR_OPERATION

#define ADI_CFG_SPORT0B_FS_ERROR_OPERATION   (1u)

Frame Sync Error Operation
0 - Flag the Frame Sync error
1 - When frame Sync error occurs, discard the receive data

Definition at line 298 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_GATED_CLOCK

#define ADI_CFG_SPORT0B_GATED_CLOCK   (0u)

Enabling Gated Clock
0 - Disable Gated Clock
1 - Enable Gated Clock

Definition at line 305 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_CLOCK_DIVISOR

#define ADI_CFG_SPORT0B_CLOCK_DIVISOR   (2u)

Serial Clock divisor.
0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial clock (ACLK) from the processor system clock (PCLK).

Definition at line 312 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_FS_DIVISOR

#define ADI_CFG_SPORT0B_FS_DIVISOR   (0x40u)

Frame Sync Divisor.
0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock cycles that the half SPORT counts before generating a frame sync pulse.

Definition at line 319 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_CONVT_FS_DURATION

#define ADI_CFG_SPORT0B_CONVT_FS_DURATION   (1u)

CONVT to FS duration.
0 - 128 - Specify the value of the number of clocks which would be programmed corresponding to the desired time duration from assertion of CONVT signal to Frame sync signal

Definition at line 328 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_CONVT_POLARITY

#define ADI_CFG_SPORT0B_CONVT_POLARITY   (0u)

Polarity of the Convt signal.
0 - Active High Polarity
1 - Active low Polarity

Definition at line 335 of file adi_sport_config.h.

◆ ADI_CFG_SPORT0B_CONVT_WIDTH

#define ADI_CFG_SPORT0B_CONVT_WIDTH   (1u)

CONVT signal width.
0-15 - Specify the value of the number of serial clocks for which CONVT signal should be active

Definition at line 343 of file adi_sport_config.h.