57 #include <adi_callback.h> 58 #include <adi_pwr_config.h> 59 #include <rtos_map/adi_rtos_map.h> 60 #include <drivers/pwr/adi_pwr.h> 61 #include "adi_pwr_def.h" 62 #include <drivers/gpio/adi_gpio.h> 78 #pragma diag_suppress=Pm011,Pm073,Pm050,Pm140,Pm143,Pm057 88 extern uint32_t lfClock;
91 extern uint32_t hfClock;
92 extern uint32_t gpioClock;
94 static ADI_CALLBACK gpfCallbackFunction;
95 static void *gpPowcbParam = NULL;
96 static uint32_t gnLowPowerIntOccFlag = 0u;
112 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
114 pADI_CLKG0_OSC->CTL = OSCCTRL_CONFIG_VALUE;
116 gpfCallbackFunction = NULL;
117 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
120 pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_HFOSC_EN;
123 while ((pADI_CLKG0_OSC->CTL & (1U << BITP_CLKG_OSC_CTL_HFOSC_OK)) == 0u)
128 pADI_CLKG0_CLK->CTL0 &= ~(BITM_CLKG_CLK_CTL0_CLKMUX);
131 pADI_CLKG0_CLK->CTL0 = CLOCK_CTL0_CONFIG_VALUE;
132 pADI_CLKG0_CLK->CTL1 = CLOCK_CTL1_CONFIG_VALUE;
134 #if defined(__ADUCM4x50__) 135 pADI_CLKG0_CLK->CTL2 = CLOCK_CTL2_CONFIG_VALUE;
138 pADI_CLKG0_CLK->CTL3 = CLOCK_CTL3_CONFIG_VALUE;
140 pADI_CLKG0_CLK->CTL5 = CLOCK_CTL5_CONFIG_VALUE;
145 pADI_PMG0->IEN = PWM_INTERRUPT_CONFIG;
146 pADI_PMG0->PWRMOD = PWM_PWRMOD_CONFIG;
147 pADI_PMG0->CTL1 = PWM_HPBUCK_CONTROL;
151 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
152 pADI_CLKG0_OSC->CTL &= ~BITM_CLKG_OSC_CTL_HFX_EN;
154 NVIC_EnableIRQ(PMG0_VREG_OVR_IRQn);
155 NVIC_EnableIRQ(PMG0_BATT_RANGE_IRQn);
157 NVIC_EnableIRQ(CLKG_XTAL_OSC_EVT_IRQn);
158 NVIC_EnableIRQ(CLKG_PLL_EVT_IRQn);
199 const ADI_CALLBACK pfCallback,
205 if(pfCallback == NULL)
211 gpfCallbackFunction = pfCallback;
212 gpPowcbParam = pcbParam;
231 if(ExtClkFreq > MAXIMUM_EXT_CLOCK)
236 gpioClock = ExtClkFreq;
254 ADI_INT_STATUS_ALLOC();
263 #if defined(__ADUCM4x50__) 264 case ADI_CLOCK_MUX_SPLL_GPIO:
277 ADI_ENTER_CRITICAL_REGION();
278 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_PLL_IPSEL);
280 pADI_CLKG0_CLK->CTL0 = tmp;
281 ADI_EXIT_CRITICAL_REGION();
301 ADI_INT_STATUS_ALLOC();
320 ADI_ENTER_CRITICAL_REGION();
322 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
323 tmp = (pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFCLK_MUX);
325 pADI_CLKG0_OSC->CTL = tmp;
327 ADI_EXIT_CRITICAL_REGION();
349 ADI_INT_STATUS_ALLOC();
367 ADI_ENTER_CRITICAL_REGION();
369 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_RCLKMUX);
371 pADI_CLKG0_CLK->CTL0 = tmp;
373 ADI_EXIT_CRITICAL_REGION();
393 ADI_INT_STATUS_ALLOC();
411 ADI_ENTER_CRITICAL_REGION();
413 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKMUX);
415 pADI_CLKG0_CLK->CTL0 = tmp;
417 ADI_EXIT_CRITICAL_REGION();
443 if(pExtClock == NULL)
448 *pExtClock = gpioClock;
473 if ((0u == hfClock) || (0u == lfClock))
487 nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
492 nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
504 *pClock = (src/nDiv);
526 ADI_INT_STATUS_ALLOC();
528 mask = (uint16_t)eClockGate;
530 ADI_ENTER_CRITICAL_REGION();
533 if (bEnable ==
true) {
536 pADI_CLKG0_CLK->CTL5 &= ~mask;
539 pADI_CLKG0_CLK->CTL5 |= mask;
543 ADI_EXIT_CRITICAL_REGION();
570 ADI_INT_STATUS_ALLOC();
581 if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
587 pdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
594 if ((pdiv % hdiv) != 0u)
600 mask = BITM_CLKG_CLK_CTL1_HCLKDIVCNT;
601 value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
608 if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
615 hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
621 if ((pdiv % hdiv) != 0u)
626 mask = BITM_CLKG_CLK_CTL1_PCLKDIVCNT;
627 value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
633 if ((nDiv > ACLK_MAX_DIV_VALUE) || (nDiv < ACLK_MIN_DIV_VALUE))
640 hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
646 if ((pdiv % hdiv) != 0u)
652 mask = BITM_CLKG_CLK_CTL1_ACLKDIVCNT;
653 value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
662 ADI_ENTER_CRITICAL_REGION();
666 tmp = pADI_CLKG0_CLK->CTL1;
669 pADI_CLKG0_CLK->CTL1 = tmp;
672 ADI_EXIT_CRITICAL_REGION();
696 volatile uint32_t *pReg = NULL;
698 ADI_INT_STATUS_ALLOC();
708 val = (1u << BITP_CLKG_OSC_CTL_HFX_EN);
709 pReg = &pADI_CLKG0_OSC->CTL;
710 nMask = BITM_CLKG_OSC_CTL_HFX_OK;
714 val = (1u << BITP_CLKG_OSC_CTL_LFX_EN);
715 pReg = &pADI_CLKG0_OSC->CTL;
716 nMask = BITM_CLKG_OSC_CTL_LFX_OK;
720 val = (1u << BITP_CLKG_OSC_CTL_HFOSC_EN);
721 pReg = &pADI_CLKG0_OSC->CTL;
722 nMask = BITM_CLKG_OSC_CTL_HFOSC_OK;
726 val = (1u << BITP_CLKG_CLK_CTL3_SPLLEN);
727 pReg = &pADI_CLKG0_CLK->CTL3;
728 nMask = BITM_CLKG_CLK_CTL3_SPLLEN;
731 #if (ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO == 1) 749 ADI_ENTER_CRITICAL_REGION();
751 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
758 uint32_t read_status;
760 read_status = ((*pREG_CLKG0_CLK_STAT0 & BITM_CLKG_CLK_STAT0_SPLL)>>BITP_CLKG_CLK_STAT0_SPLL);
761 }
while (read_status != 1u);
769 ADI_EXIT_CRITICAL_REGION();
771 if((nMask !=0u) && (bEnable ==
true))
773 while(0u== (pADI_CLKG0_OSC->CTL & nMask)){}
796 uint32_t val = pADI_CLKG0_OSC->CTL;
810 if ((val & BITM_CLKG_OSC_CTL_HFOSC_EN) != 0u)
813 if ((val & BITM_CLKG_OSC_CTL_HFOSC_OK) != 0u)
825 if ((val & BITM_CLKG_OSC_CTL_HFX_EN) != 0u)
828 if ((val & BITM_CLKG_OSC_CTL_HFX_OK) != 0u)
840 if ((val & BITM_CLKG_OSC_CTL_LFX_EN) != 0u)
843 if ((val & BITM_CLKG_OSC_CTL_LFX_OK) != 0u)
856 if ((val & BITM_CLKG_OSC_CTL_LFOSC_OK) != 0u)
892 ADI_INT_STATUS_ALLOC();
893 volatile uint32_t *pReg = NULL;
898 #if defined(__ADUCM4x50__) 900 case ADI_PWR_ROOT_CLOCK_MON_IEN:
901 pReg = &pADI_CLKG0_OSC->CTL;
907 pReg = &pADI_CLKG0_OSC->CTL;
912 pReg = &pADI_CLKG0_CLK->CTL0;
917 pReg = &pADI_CLKG0_CLK->CTL0;
922 pReg = &pADI_CLKG0_CLK->CTL3;
929 ADI_ENTER_CRITICAL_REGION();
935 tmp |= (uint32_t)eIrq;
939 tmp &= ~((uint32_t)eIrq);
943 if(pReg == &pADI_CLKG0_OSC->CTL)
945 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
949 ADI_EXIT_CRITICAL_REGION();
975 uint32_t val, cfg = 0u;
976 uint8_t nTempDivFactor = nDivFactor, nTempMulFactor = nMulFactor;
977 ADI_INT_STATUS_ALLOC();
981 if (((nMulFactor & ~0x3Fu) != 0u) || ((nDivFactor & ~0x3Fu) != 0u))
987 if((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX) ==
994 if(nTempDivFactor < MINIMUM_PLL_DIVIDER)
996 nTempDivFactor = MINIMUM_PLL_DIVIDER;
998 if(nTempMulFactor < MINIMUM_PLL_MULTIPLIER)
1000 nTempMulFactor = MINIMUM_PLL_MULTIPLIER;
1003 cfg = (((uint32_t)nTempDivFactor) << BITP_CLKG_CLK_CTL3_SPLLMSEL)|( ((uint32_t) nTempMulFactor) << BITP_CLKG_CLK_CTL3_SPLLNSEL);
1007 cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLDIV2);
1011 cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLMUL2);
1015 ADI_ENTER_CRITICAL_REGION();
1017 val = pADI_CLKG0_CLK->CTL3;
1018 val &= ~( BITM_CLKG_CLK_CTL3_SPLLMUL2 | BITM_CLKG_CLK_CTL3_SPLLMSEL | BITM_CLKG_CLK_CTL3_SPLLDIV2 | BITM_CLKG_CLK_CTL3_SPLLNSEL);
1020 pADI_CLKG0_CLK->CTL3 = val;
1023 ADI_EXIT_CRITICAL_REGION();
1045 ADI_INT_STATUS_ALLOC();
1054 ADI_ENTER_CRITICAL_REGION();
1057 pADI_PMG0->IEN |= (uint32_t)eIrq;
1061 pADI_PMG0->IEN &= ~(uint32_t)(eIrq);
1063 ADI_EXIT_CRITICAL_REGION();
1083 volatile uint32_t nDelay = 0xFFFFFFu;
1087 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1089 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_EN);
1093 if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
1105 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1107 pADI_CLKG0_OSC->CTL |= (BITM_CLKG_OSC_CTL_LFX_BYP);
1112 if(((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK)== BITM_CLKG_OSC_CTL_LFX_OK))
1129 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1131 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_BYP);
1135 if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
1153 #if defined(__ADUCM4x50__) 1164 ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch(
const bool bEnable )
1167 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1171 pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_AUTSW_EN;
1175 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_AUTSW_EN);
1194 ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch(
const bool bEnable )
1197 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1201 pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN;
1205 pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN);
1228 ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor(
const ADI_PWR_HFOSC_DIV eDivFactor )
1232 tmp = (pADI_CLKG0_CLK->CTL2 & ~BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
1233 tmp |= ((uint32_t) eDivFactor << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
1234 pADI_CLKG0_CLK->CTL2 = tmp;
1260 ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1(
const bool bEnable )
1264 pADI_CLKG0_CLK->CTL2 |= BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN;
1268 pADI_CLKG0_CLK->CTL2 &= ~(BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN);
1292 tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKOUT);
1293 tmp |= ((uint32_t)eClockOutput << BITP_CLKG_CLK_CTL0_CLKOUT);
1294 pADI_CLKG0_CLK->CTL0 = tmp;
1310 ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode(
const bool bEnable )
1314 pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE;
1318 pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE);
1336 ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode(
const ADI_PWR_HPBUCK_LD_MODE eLoadMode )
1338 if(eLoadMode == ADI_PWR_HPBUCK_LD_MODE_HIGH)
1340 pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LD_MODE;
1344 pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LD_MODE);
1364 pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCKEN;
1368 pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCKEN);
1403 tmp = (pADI_PMG0->IEN & ~BITM_PMG_IEN_RANGEBAT);
1404 tmp |= ((uint32_t)eRange << BITP_PMG_IEN_RANGEBAT);
1405 pADI_PMG0->IEN = tmp;
1415 void PLL_Int_Handler(
void)
1422 uint32_t nStatus = (pADI_CLKG0_CLK->STAT0 &
1423 (BITM_CLKG_CLK_STAT0_SPLLUNLK | BITM_CLKG_CLK_STAT0_SPLLLK));
1426 if(gpfCallbackFunction != NULL)
1428 if((nStatus & BITM_CLKG_CLK_STAT0_SPLLUNLK ) != 0u)
1433 else if((nStatus & BITM_CLKG_CLK_STAT0_SPLLLK) != 0u)
1445 pADI_CLKG0_CLK->STAT0 = nStatus;
1453 void Crystal_osc_Int_Handler(
void)
1460 uint32_t nClkStatus = (pADI_CLKG0_CLK->STAT0 &
1461 (BITM_CLKG_CLK_STAT0_HFXTALNOK |
1462 BITM_CLKG_CLK_STAT0_HFXTALOK |
1463 BITM_CLKG_CLK_STAT0_LFXTALOK |
1464 BITM_CLKG_CLK_STAT0_LFXTALNOK));
1465 #if defined(__ADUCM4x50__) 1467 uint32_t nOscStatus = (pADI_CLKG0_OSC->CTL & (BITM_CLKG_OSC_CTL_LFX_FAIL_STA |
1468 BITM_CLKG_OSC_CTL_ROOT_FAIL_STA |
1469 BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA |
1470 BITM_CLKG_OSC_CTL_LFX_AUTSW_STA ));
1473 uint32_t nEvent = 0u;
1476 if(gpfCallbackFunction != NULL)
1479 if(nClkStatus != 0u)
1487 if(nEvent != 0u) { gpfCallbackFunction( gpPowcbParam, nEvent, (
void *)0u); }
1490 #if defined(__ADUCM4x50__) 1492 else if(nOscStatus != 0u)
1495 if( (nOscStatus & BITM_CLKG_OSC_CTL_LFX_FAIL_STA) != 0u)
1498 gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, (
void *)0u);
1501 if((nOscStatus & BITM_CLKG_OSC_CTL_LFX_AUTSW_STA) != 0u)
1504 gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, (
void *)0u);
1508 else if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_FAIL_STA) != 0u)
1511 gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, (
void *)0u);
1514 if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA) != 0u)
1517 gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, (
void *)0u);
1533 if(nClkStatus != 0u)
1535 pADI_CLKG0_CLK->STAT0 = nClkStatus;
1537 #if defined(__ADUCM4x50__) 1538 else if(nOscStatus != 0u)
1541 pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
1544 pADI_CLKG0_OSC->CTL |= nOscStatus;
1558 void Battery_Voltage_Int_Handler(
void)
1561 uint32_t nStatus = pADI_PMG0->PSM_STAT;
1563 if ((nStatus & BITM_PMG_PSM_STAT_VBATUNDR) != 0u)
1565 if(gpfCallbackFunction != NULL)
1567 gpfCallbackFunction( gpPowcbParam, (uint32_t)nStatus, (
void *)0);
1569 pADI_PMG0->PSM_STAT |= (BITM_PMG_PSM_STAT_VBATUNDR);
1577 void Vreg_over_Int_Handler(
void)
1580 uint32_t nStatus = pADI_PMG0->PSM_STAT;
1582 if(gpfCallbackFunction != NULL)
1584 if ((nStatus & BITM_PMG_PSM_STAT_VREGOVR) != 0u)
1588 if ((nStatus & BITM_PMG_PSM_STAT_VREGUNDR) != 0u)
1593 pADI_PMG0->PSM_STAT |= (nStatus &(BITM_PMG_PSM_STAT_VREGOVR | BITM_PMG_PSM_STAT_VREGUNDR));
1719 uint32_t
volatile * pnInterruptOccurred,
1720 const uint8_t PriorityMask
1723 uint32_t savedPriority;
1724 uint32_t scrSetBits = 0u;
1725 uint32_t scrClrBits = 0u;
1727 ADI_INT_STATUS_ALLOC();
1732 if ((PriorityMask & ~((1u << __NVIC_PRIO_BITS) - 1u)) != 0u)
1740 if(NULL == pnInterruptOccurred) {
1741 scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk;
1744 pnInterruptOccurred = &gnLowPowerIntOccFlag;
1748 switch (PowerMode) {
1754 scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
1758 scrSetBits |= BITM_NVIC_INTCON0_SLEEPDEEP;
1764 scrSetBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
1773 ADI_ENTER_CRITICAL_REGION();
1777 pADI_PMG0->PWRKEY = ADI_PMG_KEY;
1780 pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode );
1784 SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits);
1787 savedPriority = __get_BASEPRI();
1798 savedWDT = pADI_WDT0->CTL;
1801 __set_BASEPRI((uint32_t)PriorityMask << (8u -__NVIC_PRIO_BITS));
1804 while (0u == *pnInterruptOccurred) {
1820 ADI_EXIT_CRITICAL_REGION();
1822 ADI_ENTER_CRITICAL_REGION();
1828 (*pnInterruptOccurred)--;
1831 __set_BASEPRI(savedPriority);
1834 pADI_WDT0->CTL = savedWDT;
1837 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
1841 ADI_EXIT_CRITICAL_REGION();
1863 ADI_INT_STATUS_ALLOC();
1869 if (NULL == pnInterruptOccurred) {
1871 pnInterruptOccurred = &gnLowPowerIntOccFlag;
1874 ADI_ENTER_CRITICAL_REGION();
1876 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
1879 ADI_EXIT_CRITICAL_REGION();
1883 (*pnInterruptOccurred)++;
ADI_PWR_RESULT adi_pwr_SetClockDivider(const ADI_CLOCK_ID eClockId, const uint16_t nDiv)
Sets the clock divide factor for an individual clock group.
ADI_PWR_RESULT adi_pwr_SetVoltageRange(const ADI_PWR_VOLTAGE_RANGE eRange)
To Monitor voltage range of battery.
ADI_PWR_RESULT adi_pwr_SetPLLClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets the input clock source for PLL multiplexer.
void SystemCoreClockUpdate(void)
Updates the variable SystemCoreClock and must be called whenever the core clock is changed during pro...
ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(const ADI_PWR_PMG_IRQ eIrq, const bool bEnable)
Enable/Disable the power management interrupt.
ADI_PWR_RESULT adi_pwr_UpdateCoreClock(void)
Updates the internal SystemCoreClock variable with current core Clock retrieved from cpu registers...
ADI_PWR_RESULT adi_pwr_EnableHPBuck(const bool bEnable)
Enables or disables the HP Buck.
ADI_PWR_RESULT adi_pwr_SetPll(uint8_t nDivFactor, const uint8_t nMulFactor, const bool bDiv2, const bool bMul2)
Program PLL frequency.
ADI_PWR_RESULT adi_pwr_EnableClockSource(const ADI_CLOCK_SOURCE_ID eClockSource, const bool bEnable)
To Enable/disable clock sources.
ADI_PWR_RESULT adi_pwr_EnterLowPowerMode(const ADI_PWR_POWER_MODE PowerMode, uint32_t volatile *pnInterruptOccurred, const uint8_t PriorityMask)
Puts the processor into given low power mode.
ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(uint32_t volatile *pnInterruptOccurred)
ADI_PWR_RESULT adi_pwr_GetExtClkFreq(uint32_t *pExtClock)
Gets the system external clock frequency. Gets the clock frequency of the source connected to the ext...
ADI_GPIO_RESULT adi_gpio_InputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
Enables/Disables the Input Drivers for GPIO Pin(s)
ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(const ADI_PWR_CLOCK_IRQ eIrq, const bool bEnable)
Enable/Disable the clock interrupt to monitor status of LFXTAL, HFXTAL and PLL.
ADI_PWR_RESULT adi_pwr_RegisterCallback(const ADI_CALLBACK pfCallback, void *pcbParam)
Registers or unregister the callback function.
ADI_PWR_RESULT adi_pwr_EnableClock(const ADI_CLOCK_GATE eClockGate, const bool bEnable)
Enable/disable individual peripheral clocks.
ADI_GPIO_RESULT adi_gpio_PullUpEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
Enables/Disables the Pull-Up for GPIO Pin(s)
ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass(const bool bEnable)
Enable/disable LFXTAL bypass mode.
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
ADI_PWR_RESULT adi_pwr_SetExtClkFreq(const uint32_t ExtClkFreq)
Sets the system external clock frequency.
ADI_PWR_RESULT adi_pwr_SetRootClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets the source for the root clock multiplexer.
ADI_PWR_RESULT adi_pwr_SetRefClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets clock source for the Reference clock multiplexer.
ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(ADI_PWR_WAKEUP_STATUS *peStatus)
Function to retrieve the wakeup from shut down mode status.
ADI_PWR_RESULT adi_pwr_GetClockStatus(const ADI_CLOCK_SOURCE_ID eClockSource, ADI_CLOCK_SOURCE_STATUS *peStatus)
Return the status of a clock source.
ADI_PWR_RESULT adi_pwr_Init(void)
ADI_PWR_RESULT adi_pwr_SetLFClockMux(const ADI_CLOCK_MUX_ID eClockID)
Sets the input clock for low frequency clock multiplexer.