ADuCM302x Device Drivers API Reference Manual
Release 3.1.2.0
|
#define ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO 0 |
Enable the code to support input clock through the GPIO pin 0 - No support for input clock through the GPIO pin. 1 - Support for input clock through the GPIO pin.
Definition at line 70 of file adi_pwr_config.h.
#define ADI_PWR_LF_CLOCK_MUX 0 |
32 KHz clock select mux. This clock connects to beeper, RTC.
0 - Internal 32 KHz oscillator is selected.
1 - External 32 KHz crystal is selected..
Definition at line 82 of file adi_pwr_config.h.
#define ADI_PWR_HFOSC_CLOCK_ENABLE 1 |
High frequency internal oscillator enable
0 - The HFOSC oscillator is disabled and placed in a low power state
1 - The HFOSC oscillator is enabled.
Definition at line 90 of file adi_pwr_config.h.
#define ADI_PWR_LFXTAL_CLOCK_ENABLE 0 |
Low frequency external oscillator enable and placed in a low power state
0 - The LFXTAL oscillator is disabled
1 - The LFXTAL oscillator is enabled.
Definition at line 98 of file adi_pwr_config.h.
#define ADI_PWR_HFXTAL_CLOCK_ENABLE 0 |
High frequency external oscillator enable
0 - The HFXTAL oscillator is disabled and placed in a low power state
1 - The HFXTAL oscillator is enabled.
Definition at line 105 of file adi_pwr_config.h.
#define ADI_PWR_LFXTAL_CLOCK_MON_ENABLE 0 |
Low frequency external clock fail interrupt enable
0 - The LFXTAL clock monitor and clock fail interrupt disabled
1 - The LFXTAL clock monitor and clock fail interrupt enabled.
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 114 of file adi_pwr_config.h.
#define ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE 0 |
Automatic switching of the LF Mux to LF Oscillator on LFXTAL failure.
0 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure
1 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure.
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 123 of file adi_pwr_config.h.
#define ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE 0 |
Root clock monitor and Clock Fail interrupt enable. 0 - Disable Root Clock Monitor and Clock Fail interrupt.
1 - Enable Root Clock Monitor and Clock Fail interrupt.
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 132 of file adi_pwr_config.h.
#define ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE 0 |
Enable Auto switch to High Frequency Oscillator (HFOSC) when Root Clock Fails. 0 - Disable Automatic switching of the Root Clock.
1 - Enable Automatic switching of the Root Clock.
Definition at line 141 of file adi_pwr_config.h.
#define ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX 0 |
Selecting the input clock for Root Clock mux. Determines which single shared clock source is used by the PCLK, and HCLK dividers.
0 - HFOSC High frequency internal oscillator
1 - HFXTAL High frequency external oscillator
2 - SPLL Output of System PLL is selected
3 - External GPIO port is selected
Definition at line 154 of file adi_pwr_config.h.
#define ADI_PWR_GPIO_CLOCK_OUT_SELECT 0 |
GPIO clock out select. Selects the clock to be routed to the GPIO clock out pin.
0 - Root Clock (ROOT_CLK)
1 - Low Frequency Clock (LF_CLK)
2 - ADC Clock (ACLK)
3 - HCLK_BUS
4 - HCLK_CORE
5 - Peripheral Clock (PCLK) 6 - Reference Clock for Flash controller timer (RCLK)
7 - Mux of HFOSC, HFXTAL clock (RHP_CLK)
8 - GP Timer 0 clock (GPT0_CLK)
9 - GP Timer 1 clock (GPT1_CLK)
10 - Peripherals operating at HCLK (HCLK_P)
11 - PLL Clock out (PCLK)
12 - RTC0 Clock
13 - HP Buck Clock (HPBUCK_CLK)
14 - HP Buck Non overlap clock
15 - RTC1 generated clock
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 177 of file adi_pwr_config.h.
#define ADI_PWR_INPUT_TO_RCLK_MUX 0 |
Flash reference clock and HPBUCK clock source mux.
0 - sourcing from HFOSC (High frequency internal oscillator)
2 - sourcing from external HFXTAL( High frequency external oscillator 26M Hz )
3 - sourcing from external HFXTAL( High frequency external oscillator 16M Hz )
Definition at line 186 of file adi_pwr_config.h.
#define ADI_PWR_INPUT_TO_SPLL_MUX 0 |
Selecting the input clock for the system PLL clock.
0 - sourcing from HFOSC (High frequency internal oscillator)
1 - sourcing from HFXTAL(High frequency external oscillator)
2 - GPIO Input clock.
3 - GPIO Input clock.
Definition at line 195 of file adi_pwr_config.h.
#define ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE 0 |
External Low frequency crystal interrupt enable.
0 - Disable the interrupt for LF clock
1 - Enable the interrupt for LF clock
Definition at line 202 of file adi_pwr_config.h.
#define ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE 0 |
External Hight frequency crystal interrupt enable.
0 - Disable the interrupt for HFXTAL clock
1 - Enable the interrupt for HFXTAL clock
Definition at line 209 of file adi_pwr_config.h.
#define ADI_PWR_HCLK_DIVIDE_COUNT 4 |
HCLK divide count.Determines the HCLK rate based on the following equation: HCLK = ROOT_CLK/HCLKDIVCNT. 0 - 63 is valid range.
Definition at line 219 of file adi_pwr_config.h.
#define ADI_PWR_PCLK_DIVIDE_COUNT 4 |
PCLK divide count.Determines the PCLK rate based on the following equation: PCLK = ROOT_CLK/PCLKDIVCNT. 0 - 63 is valid range.
Definition at line 225 of file adi_pwr_config.h.
#define ADI_PWR_ACLK_DIVIDE_COUNT 16 |
ACLK divide count.Determines the ACLK rate based on the following equation: ACLK = ROOT_CLK/ACLKDIVCNT. 0 - 63 is valid range.
Definition at line 231 of file adi_pwr_config.h.
#define ADI_PWR_HFOSC_AUTO_DIV_BY_1 0 |
HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode.
When enabled enabled (Set to 1), the frequency undivided 26MHz HF oscillator clock itself will be used during the wake up. The undivided HFOSC clock is selected automatically by clearing the HFOSCDIVCLKSEL register content to 0, which selects the HFOSC/1 clock.This updated divided by 1 clock selection will remain same until the new divider value is written to this register.
When disabled (Set to 0), this fast wake up feature will be disabled and the HFOSCDIVCLKSEL register will remain unchanged during the wakeup.
0 - Auto select HFOSC/1 clock during wakeup from Flexi mode is disable.
1 - Auto select HFOSC/1 clock during wakeup from Flexi mode is enabled.
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 251 of file adi_pwr_config.h.
#define ADI_PWR_HFOSC_DIVIDE_SELECT 0 |
HF Oscillator divide select. 0 - HFOSC/1.
1 - HFOSC/2.
2 - HFOSC/4.
3 - HFOSC/8.
4 - HFOSC/16.
5 - HFOSC/32.
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 264 of file adi_pwr_config.h.
#define ADI_PWR_SPLL_MUL_FACTOR 26 |
System PLL N multiplier(SPLL_NSEL). Sets the N value used to obtain the multiplication factor N/M of the PLL. 8 - 31 is valid range.
Definition at line 274 of file adi_pwr_config.h.
#define ADI_PWR_SPLL_ENABLE_DIV2 0 |
System PLL division by 2. Controls if an optional divide by two is placed on the PLL output.
0 - The System PLL is not divided. Its output frequency equals that selected by the N/M ratio
1 - The System PLL is divided by two. Its output frequency equals that selected by the N/M ratio with an additional divide by 2
Definition at line 282 of file adi_pwr_config.h.
#define ADI_PWR_SPLL_ENABLE 0 |
System PLL enable. Controls if the PLL should be enabled or placed in its low power state.
0 - The system PLL is disabled and is in its power down state
1 - The system PLL is enabled.
Definition at line 289 of file adi_pwr_config.h.
#define ADI_PWR_SPLL_INTERRUPT_ENABLE 0 |
System PLL interrupt enable.Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt generated.
0 - Disable the SPLL interrupt generation
1 - Enable the SPLL interrupt generation
Definition at line 296 of file adi_pwr_config.h.
#define ADI_PWR_SPLL_DIV_FACTOR 13 |
System PLL M Divider(SPLL_MSEL). Sets the M value used to obtain the multiplication factor N/M of the PLL. 2 - 15 is valid range.
Definition at line 303 of file adi_pwr_config.h.
#define ADI_PWR_SPLL_ENABLE_MUL2 0 |
system PLL multiply by 2. This bit is used to configure if the VCO clock frequency should be multiplied by 2 or 1.
0 - The System PLL is multiplied by 1.
1 - The System PLL is multiplied by 2.
Definition at line 310 of file adi_pwr_config.h.
#define ADI_PWR_GPT0_CLOCK_ENABLE 1 |
This can be used to enable/disable clock to GPT0.
0 - Disable the clock to GPT0
1 - Enable the clock to GPT0
Definition at line 320 of file adi_pwr_config.h.
#define ADI_PWR_GPT1_CLOCK_ENABLE 1 |
This can be used to enable/disable clock to GPT1.
0 - Disable the clock to GPT1
1 - Enable the clock to GPT1
Definition at line 327 of file adi_pwr_config.h.
#define ADI_PWR_GPT2_CLOCK_ENABLE 1 |
This can be used to enable/disable clock to GPT2.
0 - Disable the clock to GPT2
1 - Enable the clock to GPT2
Definition at line 333 of file adi_pwr_config.h.
#define ADI_PWR_I2C_CLOCK_ENABLE 1 |
This can be used to enable/disable clock to I2C.
0 - Disable the clock to I2C
1 - Enable the clock to I2C
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 342 of file adi_pwr_config.h.
#define ADI_PWR_GPIO_CLOCK_ENABLE 1 |
This can be used to enable/disable clock to GPIO.
0 - Disable the clock to GPIO
1 - Enable the clock to GPIO
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 351 of file adi_pwr_config.h.
#define ADI_PWR_PCLK_ENABLE 0 |
This can be used to enable/disable all clocks connected to peripherals.
0 - Disable the Clock supply to peripherals
1 - Enable the Clock supply to peripherals
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 361 of file adi_pwr_config.h.
#define ADI_PWR_TIMER_RGB_ENABLE 1 |
This can be used to enable/disable clocks to Timer RGB.
0 - Disable the Clock supply to Timer RGB
1 - Enable the Clock supply to Timer RGB
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 370 of file adi_pwr_config.h.
#define ADI_PWR_ENABLE_VBAT_INTERRUPT 0 |
Enabling the interrupt if the Battery voltage falls below 1.8V.
0 - Disable Battery voltage interrupt
1 - Enable Battery voltage interrupt.
Definition at line 383 of file adi_pwr_config.h.
#define ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT 0 |
Enabling the interrupt for under VREG voltage (i.e less than 1V).
0 - Disable VREG under voltage interrupt
1 - Enable VREG under voltage interrupt.
Definition at line 390 of file adi_pwr_config.h.
#define ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT 0 |
Enabling the interrupt for over VREG voltage (i.e above than 1.32V).
0 - Disable VREG over voltage interrupt
1 - Enable VREG over voltage interrupt.
Definition at line 397 of file adi_pwr_config.h.
#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT 0 |
Enabling the interrupt for Battery range.
0 - Disable battery voltage range interrupt
1 - Enable battery voltage range interrupt
Definition at line 404 of file adi_pwr_config.h.
#define ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT 0 |
Battery voltage range for generating the interrupt.
0 - Configure to generate interrupt if VBAT > 2.75V
1 - Configure to generate interrupt if VBAT is between 2.75 and 1.6V
2 - Configure to generate interrupt if VBAT is between 2.3V and 1.6V
Definition at line 412 of file adi_pwr_config.h.
#define ADI_PWR_HP_BUCK_ENABLE 0 |
Enable or disable HP Buck.
0 - Disable HP Buck. 1 - Enable HP Buck.
Definition at line 420 of file adi_pwr_config.h.
#define ADI_PWR_HP_BUCK_LOAD_MODE 0 |
HP Buck Load mode.
0 - HP Buck low load mode. Can be set when the system is running at less than 26 Mhz.
1 - HP Buck High load mode. Can be set when the system is running at more than 26 Mh.
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 431 of file adi_pwr_config.h.
#define ADI_PWR_HP_BUCK_LOW_POWER_MODE 0 |
HP Buck low power mode.
The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode and low power modules such as Timer, Beeper only are enabled
0 - HPBUCK Low power mode is disabled.
1 - HPBUCK Low power mode is enabled.
Note: This feature is available only in ADuCM4x50 processor.
Definition at line 443 of file adi_pwr_config.h.
#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING 0 |
Enable or disable monitoring battery voltage (VBAT) during HIBERNATE Mode.
0 - Battery voltage monitoring is enabled. 1 - Battery voltage monitoring is disabled.
By default battery voltage monitoring during hibernate is enabled.
Definition at line 455 of file adi_pwr_config.h.