ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_spi_def.h
1 
45 #ifndef ADI_SPI_DEF_H_
46 #define ADI_SPI_DEF_H_
47 
48 
49 
50 #include <drivers/spi/adi_spi.h>
51 
52 #define ADI_SPI_NUM_INSTANCES (3u)
53 #define ADI_SPI_FIFO_SIZE (8u)
54 #define ADI_SPI_IRQ_PARAM (7u)
55 
56 /* Macro mapping from ADuCM4x50 to ADuCM302x */
57 #if defined(__ADUCM302x__)
58 #define DMA_SPIH_TX_Int_Handler(void) DMA_SPI2_TX_Int_Handler(void)
59 #define DMA_SPIH_RX_Int_Handler(void) DMA_SPI2_RX_Int_Handler(void)
60 #endif
61 
64 /*
65  *****************************************************************************
66  * SPI Bitrate Initializer. Sets a default serial clockrate for the SPI channel.
67  *****************************************************************************/
68 /* #define ADI_SPI_BITRATE_INITIALIZER 4000000 // 4MHz default bitrate */
69 #define ADI_SPI_BITRATE_INITIALIZER 250000u /* depends on processor */
70 
71 /*
72  *****************************************************************************
73  * SPI0/SPI1 Control Register Initializer. This macro configures default
74  * settings for the SPI configuration control register when operated in Master-mode.
75  *****************************************************************************/
76 /* SPI master DMA mode control configuration */
77 #define ADI_SPI_MASTERCON_INITIALIZER BITM_SPI_CTL_MASEN
78 
79 /*
80  *****************************************************************************
81  * SPI0/SPI1 Control Register Initializer. This macro configures default
82  * settings for the SPI configuration control register when operated in Slave-mode.
83  *****************************************************************************/
84  #define ADI_SPI_SLAVECON_INITIALIZER BITM_SPI_CTL_OEN \
85  | BITM_SPI_CTL_ZEN \
86  | BITM_SPI_CTL_SPIEN
87 
88 /* 16-bit DMA... (two-byte size and increment) */
89 #define ADI_DMA_DATA_WIDTH ADI_DMA_WIDTH_2_BYTE
90 #define ADI_DMA_DATA_INCREMENT ADI_DMA_INCR_HALFWORD
98 typedef struct ADI_SPI_CONFIG
99 {
100  uint16_t SPI_CTL;
101  uint16_t SPI_DIV;
102 } ADI_SPI_CFG_TYPE;
103 
106 typedef struct __ADI_SPI_DEVICE_INFO
107 {
108  const uint16_t dmaTxIrqNumber; /* DMA channel ID-Tx */
109  const uint16_t dmaTxChannelNumber; /* Tx */
110  const uint16_t dmaRxIrqNumber; /* DMA channel ID-Rx */
111  const uint16_t dmaRxChannelNumber; /* DMA channel ID-Rx */
112  volatile ADI_SPI_TypeDef *pSpiRegs; /* Base address of the SPI registers */
113  const IRQn_Type eIRQn; /* IRQn */
114  ADI_SPI_HANDLE hDevice; /* SPI handle */
115 }ADI_SPI_DEVICE_INFO;
116 
117 
119 typedef struct __ADI_SPI_DEV_DATA_TYPE
120 {
121 
122  /* device attributes */
123  volatile ADI_SPI_TypeDef *pSpi;
124  ADI_SPI_DEVICE_INFO *pDevInfo;
125 
126  /* Callback and Callback parameters */
127  ADI_CALLBACK pfCallback;
128  void * pCBParam;
129  /* The last recorded SPI event */
130  uint32_t HWErrors;
132  uint8_t* pTxBuffer;
133  uint8_t* pRxBuffer;
134  uint16_t TxRemaining;
135  uint16_t RxRemaining;
136  uint8_t TxIncrement;
137  uint8_t RxIncrement;
139  volatile bool bTransferComplete;
141  bool bDmaMode;
142  bool bRdCtlMode; /* Use half duplex read control feature */
143  bool bBlockingMode;
144  ADI_SPI_CHIP_SELECT ChipSelect;
146  SEM_VAR_DECLR
147 } ADI_SPI_DEV_DATA_TYPE;
148 
149 
150 
153 #endif /* ADI_SPI_DEF_H__ */
154 
struct __ADI_SPI_DEV_DATA_TYPE * ADI_SPI_HANDLE
Definition: adi_spi.h:181
ADI_SPI_CHIP_SELECT
Definition: adi_spi.h:165