47 #include "system_ADuCM3029.h" 48 #include <adi_callback.h> 49 #include <adi_processor.h> 50 #include <rtos_map/adi_rtos_map.h> 63 #pragma diag_suppress=Pm073,Pm143,Pm140 81 uint32_t lfClock = 0u;
85 uint32_t hfClock = 0u;
88 uint32_t gpioClock = 0u;
90 extern void* __Vectors[];
92 extern uint32_t __Vectors[];
99 #if defined (__CC_ARM) 100 __attribute__ ((at(0x00000180u)))
101 #elif defined (__GNUC__) 102 __attribute__ ((section(
".security_options")))
103 #elif defined (__ICCARM__) 104 #pragma location=".security_options" 108 const ADI_ADUCM302X_SECURITY_OPTIONS adi_aducm302x_security_options
110 { 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu },
141 uint32_t val, nDivisor, nMulfactor, div2, mul2;
154 switch (pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) {
156 case HFMUX_INTERNAL_OSC_VAL:
160 case HFMUX_EXTERNAL_XTAL_VAL:
164 case HFMUX_SYSTEM_SPLL_VAL:
166 if ((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_SPLLIPSEL) != 0u) {
175 nMulfactor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLNSEL) >> BITP_CLKG_CLK_CTL3_SPLLNSEL;
177 nDivisor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL) >> BITP_CLKG_CLK_CTL3_SPLLMSEL;
180 mul2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2) >> BITP_CLKG_CLK_CTL3_SPLLMUL2;
182 div2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2) >> BITP_CLKG_CLK_CTL3_SPLLDIV2;
184 val = ((val << mul2) * nMulfactor / nDivisor) >> div2;
197 SystemCoreClock = hfClock;
200 #ifdef __ARMCC_VERSION 202 #pragma import(__use_no_semihosting_swi) 218 #define ADI_NUM_EXCEPTIONS 16 219 #define LENGTHOF_IVT (NVIC_INTS + ADI_NUM_EXCEPTIONS) 220 #define RELOCATION_ADDRESS (0x20000000) 223 #if defined (__ICCARM__) 225 SECTION_PLACE(KEEP_VAR(__no_init uint32_t __relocated_vector_table[LENGTHOF_IVT]), RELOCATION_ADDRESS);
227 #warning "Relocated Interupt Vector Tables are not supported in this toolchain" 259 IntStatus = __get_PRIMASK();
264 for (i = 0u; i < LENGTHOF_IVT; i++)
266 __relocated_vector_table[i] = (uint32_t )__Vectors[i];
268 SCB->VTOR = (uint32_t) &__relocated_vector_table;
271 SCB->VTOR = (uint32_t) &__Vectors;
278 SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk |
279 SCB_SHCSR_BUSFAULTENA_Msk |
280 SCB_SHCSR_MEMFAULTENA_Msk ;
286 __set_PRIMASK(IntStatus);
288 #ifdef ADI_MAX_IRQ_PRIORITY 309 pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN;
313 pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN;
344 pADI_PMG0->SRAMRET |= (uint32_t)eBank>>1;
348 pADI_PMG0->SRAMRET &= ~((uint32_t)eBank >> 1);
370 #ifdef ADI_MAX_IRQ_PRIORITY 371 uint32_t prio = (uint32_t)ADI_MAX_IRQ_PRIORITY;
373 uint32_t prio = (uint32_t)0u;
378 for(uint8_t irq = 0u; irq <
NVIC_INTS; irq++) {
379 NVIC_SetPriority((IRQn_Type)irq, prio);
void SystemInit(void)
Sets up the microcontroller system. Initializes the System and updates the relocate vector table...
void SystemCoreClockUpdate(void)
Updates the variable SystemCoreClock and must be called whenever the core clock is changed during pro...
void adi_system_EnableCache(bool bEnable)
This enables or disables the cache.
void adi_system_SetGlobalIrqPriority(void)
This function sets the priority for all IRQ interrupts to the value defined by ADI_MAX_IRQ_PRIORITY (...
#define CACHE_CONTROLLER_KEY
uint32_t adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable)
This enables/disable SRAM retention during the hibernation.