ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_adc.c
1 
56 #ifndef ADI_ADC_C
57 
58 #define ADI_ADC_C
59 
60 /*============= I N C L U D E S =============*/
61 
62 
63 /* Header file with definitions specific to ADC driver implementation */
64 
65 /*============= A D C I M P L E M E N T A T I O N S O U R C E F I L E S =============*/
66 #include <drivers/adc/adi_adc.h>
67 #include <adi_processor.h>
68 #include <assert.h>
69 #include <string.h>
70 #include <drivers/pwr/adi_pwr.h>
71 #include <adi_adc_config.h>
72 #include <rtos_map/adi_rtos_map.h>
73 
74 #ifdef __ICCARM__
75 /*
76 * IAR MISRA C 2004 error suppressions.
77 *
78 * Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
79 * This isn't a header as such.
80 *
81 * Pm073 (rule 14.7): a function should have a single point of exit
82 * Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
83 * Multiple returns are used for error handling.
84 *
85 * Pm050 (rule 14.2): a null statement shall only occur on a line by itself
86 * Needed for null expansion of ADI_INSTALL_HANDLER and others.
87 *
88 * Pm088 (rule 17.4): pointer arithmetic should not be used.
89 * Relying on pointer arithmetic for buffer handling.
90 *
91 * Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
92 * The rule makes an exception for memory-mapped register accesses.
93 *
94 * Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type
95 * Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
96 
97 */
98 #pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm152
99 #endif /* __ICCARM__ */
100 
101 #include "adi_adc_def.h"
102 #include "adi_adc_data.c"
103 
104 /*============== D E F I N E S ===============*/
105 #ifdef ADI_DEBUG
106 #define ADI_ADC_INVALID_HANDLE(h) (AdcDevInfo[0].hDevice != (h))
107 #endif
108 
109 /* Specify the maximum acquisition time, based on the width of the SAMPTIME field. */
110 #define ADI_MAX_ACQUISITION_TIME (((uint32_t)BITM_ADC_CNV_TIME_SAMPTIME << BITP_ADC_CNV_TIME_SAMPTIME) + 1u)
111 
112 /* The 12bit maximum sample value */
113 #define ADI_ADC_SAMPLE_MAX ((uint16_t)(4095u))
114 
115 /*============= C O D E =============*/
116 
117 /*============= D E B U G F U N C T I O N P R O T O T Y P E S =============*/
118 
119 /* Override "weak" default binding in startup_*.c */
121 #if defined(__ADUCM302x__)
122 extern void ADC_Int_Handler(void);
123 #else
124 extern void ADC0_Int_Handler(void);
125 #endif
126 
127 /* macro definition for ADuCM3029 */
128 #if defined(__ADUCM302x__)
129 #define BITM_ADC_CFG_VREFVBAT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* VRef VBAT */
130 #endif
131 
132 extern void DMA_ADC0_Int_Handler (void);
133 
136 /* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */
137 /*============= L O C A L F U N C T I O N S P R O T O T Y P E S =============*/
138 static uint16_t ReadOutReg(uint32_t nChannelNum);
139 
140 /* ADC management functions, based on transfer method */
141 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
142 static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
143 #else
144 static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
145 #endif
146 
147 /* Channel helper functions */
148 static uint32_t GetNumChannels(uint32_t nChannels);
149 static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel);
150 
151 /* Buffer management functions */
152 static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice);
153 static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice);
154 static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels);
155 
156 /* Internal configuration functions */
157 static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable);
158 static void StaticConfiguration(ADI_ADC_DEVICE *pDevice);
159 
162 /*============= P U B L I C F U N C T I O N S =============*/
163 
180  uint32_t nDeviceNum,
181  void *pMemory,
182  uint32_t nMemorySize,
183  ADI_ADC_HANDLE *phDevice)
184 {
185  ADI_INT_STATUS_ALLOC();
186  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)pMemory;
187 
188 #ifdef ADI_DEBUG
189  if (nDeviceNum > (sizeof (AdcDevInfo)/sizeof(AdcDevInfo[0])))
190  {
192  }
193 
194  if (nMemorySize < ADI_ADC_MEMORY_SIZE)
195  {
197  }
198 
199  if (AdcDevInfo[nDeviceNum].hDevice != NULL)
200  {
201  return ADI_ADC_IN_USE;
202  }
203 
204  assert (ADI_ADC_MEMORY_SIZE >= sizeof (ADI_ADC_DEVICE));
205 #endif /* ADI_DEBUG */
206 
207  memset (pMemory, 0, nMemorySize);
208 
209  ADI_ENTER_CRITICAL_REGION();
210  AdcDevInfo[nDeviceNum].hDevice = (ADI_ADC_HANDLE)pDevice;
211  pDevice->pReg = AdcDevInfo[nDeviceNum].pReg;
212  ADI_EXIT_CRITICAL_REGION();
213 
214  /* Reset the ADC */
215  pDevice->pReg->CFG = BITM_ADC_CFG_RST;
216 
217  /* Enable the IRQs */
218  NVIC_ClearPendingIRQ(ADC0_EVT_IRQn);
219  NVIC_EnableIRQ(ADC0_EVT_IRQn);
220 
221  /* Initialize the registers to known value */
222  pDevice->pReg->IRQ_EN = BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE;
223 
224  /* Do the static configuration */
225  StaticConfiguration(pDevice);
226 
227  /* Create a semaphore for buffer management */
228  SEM_CREATE(pDevice, "ADC Sem", ADI_ADC_ERR_RTOS);
229 
230  /* Set the default FIFO Manage function */
231 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
232  pDevice->pfManageFifo = DmaFIFOManage;
233  /* Make sure the DMA controller and its SRAM based descriptors are initialized */
234  adi_dma_Init();
235 #else
236  pDevice->pfManageFifo = InterruptFIFOManage;
237 #endif
238 
239  /* Return the device handle back to the application */
240  *phDevice = AdcDevInfo[nDeviceNum].hDevice;
241 
242  return ADI_ADC_SUCCESS;
243 }
244 
245 
256 {
257  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
258  ADI_ADC_RESULT eResult;
259 
260 #ifdef ADI_DEBUG
261  if (pDevice == NULL)
262  {
264  }
265 #endif /* ADI_DEBUG */
266 
267  /* Power down the device */
268  if ((eResult = adi_adc_PowerUp (hDevice, false)) != ADI_ADC_SUCCESS) {
269  return eResult;
270  }
271 
272  /* Disable the IRQ */
273  pDevice->pReg->IRQ_EN = 0u;
274 
275  /* Clear the conversion cfg register to stop any transaction */
276  pDevice->pReg->CNV_CFG = 0u;
277 
278 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
279  /* Close the DMA if configured */
280  NVIC_DisableIRQ(DMA0_CH24_DONE_IRQn);
281 #endif /* ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 */
282 
283  /* Disable the ADC interrupt */
284  NVIC_DisableIRQ(ADC0_EVT_IRQn);
285 
286  /* Destroy the semaphore */
287  SEM_DELETE(pDevice, ADI_ADC_ERR_RTOS);
288 
289  /* Finally, zero the device */
290  AdcDevInfo[0].hDevice = (NULL);
291 
292  return ADI_ADC_SUCCESS;
293 }
294 
295 
310 {
311  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
312  uint32_t nClock = 0u;
313  uint16_t nCount = 0u;
315 
316 #ifdef ADI_DEBUG
317  if (pDevice == NULL)
318  {
320  }
321 #endif /* ADI_DEBUG */
322 
323  if (bPowerUp == true)
324  {
325  if (IS_NOT_IN_ANY_STATE(ADC_STATUS_POWERED_UP))
326  {
328  {
329  /* We need the cycles equivelent of 20us entered here, based on the PCLK
330  * clock. nClock is the frequency of the PCLK, 50000 is the equivalent frequency of 20us
331  * e.g. 26,000,000Hz, 0.00002s produces 520 cycles.*/
332  nCount = (uint16_t)(nClock / 50000u);
333 
334  /* Powering up ADC */
335  pDevice->pReg->CFG |= BITM_ADC_CFG_PWRUP;
336 
337  /* Set ADC_PWRUP.WAIT bits for the new count */
338  pDevice->pReg->PWRUP = (uint16_t)(((uint32_t)nCount << BITP_ADC_PWRUP_WAIT) & BITM_ADC_PWRUP_WAIT);
339 
340  SET_STATE(ADC_STATUS_POWERED_UP);
341  }
342  else
343  {
344  eResult = ADI_ADC_BAD_SYS_CLOCK;
345  }
346  }
347  }
348  else
349  {
350  if (IS_IN_STATE(ADC_STATUS_POWERED_UP))
351  {
352  /* If the ADC system is up then disable the ADC subsystem */
353  if ( IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN) )
354  {
355  eResult = adi_adc_EnableADCSubSystem (hDevice, false);
356  if (eResult != ADI_ADC_SUCCESS)
357  {
358  return eResult;
359  }
360  }
361 
362  /* Powering down ADC */
363  pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_PWRUP));
364  CLR_STATE(ADC_STATUS_POWERED_UP);
365  }
366  }
367 
368  return eResult;
369 }
370 
371 
390  ADI_ADC_HANDLE hDevice,
391  ADI_CALLBACK pfCallback,
392  void *pCBParam)
393 {
394  ADI_INT_STATUS_ALLOC();
395 
396  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
397 
398 #ifdef ADI_DEBUG
399  if (pDevice == NULL)
400  {
402  }
403 
404  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
405  {
407  }
408 
409 #endif /* ADI_DEBUG */
410 
411  ADI_ENTER_CRITICAL_REGION();
412  pDevice->pfCallback = pfCallback;
413  pDevice->pCBParam = pCBParam;
414  ADI_EXIT_CRITICAL_REGION();
415 
416  return ADI_ADC_SUCCESS;
417 }
418 
439  ADI_ADC_HANDLE hDevice,
440  bool bEnable)
441 {
442  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
443 
444 #ifdef ADI_DEBUG
445  if (pDevice == NULL)
446  {
448  }
449 
450  if (IS_NOT_IN_STATE(ADC_STATUS_POWERED_UP))
451  {
453  }
454 
455  if (bEnable == true) {
456  if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
458  }
459  } else {
460  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
462  }
463  }
464 #endif /* ADI_DEBUG */
465 
466  if (bEnable == true)
467  {
468  pDevice->pReg->CFG |= BITM_ADC_CFG_EN;
469  SET_STATE(ADC_STATUS_SUB_SYSTEM_EN);
470  }
471  else
472  {
473  pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_EN);
474  CLR_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_SUB_SYSTEM_READY);
475  }
476 
477  return ADI_ADC_SUCCESS;
478 }
479 
480 
501  ADI_ADC_HANDLE hDevice,
502  bool *pbReady
503 )
504 {
505  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
506 
507 #ifdef ADI_DEBUG
508  if (pDevice == NULL)
509  {
511  }
512 
513  if (pbReady == NULL)
514  {
515  return ADI_ADC_NULL_POINTER;
516  }
517 
518  if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN))
519  {
521  }
522 #endif /* ADI_DEBUG */
523 
524  if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_READY))
525  {
526  *pbReady = true;
527  }
528  else
529  {
530  *pbReady = false;
531  }
532  return ADI_ADC_SUCCESS;
533 }
534 
553  ADI_ADC_HANDLE hDevice,
554  ADI_ADC_VREF_SRC eVrefSrc)
555 {
557  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
558 
559 #ifdef ADI_DEBUG
560  if (pDevice == NULL)
561  {
563  }
564 
565  if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN))
566  {
568  }
569 #endif /* ADI_DEBUG */
570 
571  pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL | BITM_ADC_CFG_VREFVBAT));
572 
573  switch (eVrefSrc)
574  {
576  pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
577  break;
578 
580  pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN;
581  break;
582 
584  pDevice->pReg->CFG |= BITM_ADC_CFG_VREFVBAT;
585  break;
586 
588  break;
589 
590  default:
591  eResult = ADI_ADC_INVALID_PARAMETER;
592  break;
593  }
594 
595  return eResult;
596 }
597 
598 
615  ADI_ADC_HANDLE hDevice,
616  bool bEnable)
617 {
618  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
619 
620 #ifdef ADI_DEBUG
621  if (pDevice == NULL)
622  {
624  }
625 #endif /* ADI_DEBUG */
626 
627  if (bEnable == true)
628  {
629  pDevice->pReg->CFG |= BITM_ADC_CFG_SINKEN;
630  }
631  else
632  {
633  pDevice->pReg->CFG &= (uint16_t)~(BITM_ADC_CFG_SINKEN);
634  }
635 
636  return ADI_ADC_SUCCESS;
637 }
638 
639 
654 {
655  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
656 
657 #ifdef ADI_DEBUG
658  if (pDevice == NULL)
659  {
661  }
662 
663  /* Calibration cannot be done when ADC is processing the buffers */
664  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN))
665  {
667  }
668 
669 #endif /* ADI_DEBUG */
670 
671  /* Clear the calibration done state */
672  CLR_STATE(ADC_STATUS_CALIBRATION_DONE);
673 
674  /* Clear ADC_STAT.CALDONE */
675  pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
676 
677  /* Set the state as calibration enabled. This state will be cleared when we get the
678  calibration done interrupt. */
679  SET_STATE(ADC_STATUS_CALIBRATION_EN);
680 
681  /* Start ADC calibration */
682  pDevice->pReg->CFG |= BITM_ADC_CFG_STARTCAL;
683 
684  return ADI_ADC_SUCCESS;
685 }
686 
702  ADI_ADC_HANDLE hDevice,
703  bool *pbCalibrationDone)
704 {
705  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
706 
707 #ifdef ADI_DEBUG
708  if (pDevice == NULL)
709  {
711  }
712 
713  if (pbCalibrationDone == NULL)
714  {
715  return ADI_ADC_NULL_POINTER;
716  }
717 #endif /* ADI_DEBUG */
718 
719  /* The driver will check whether the driver is set to calibration done state. This state will
720  * be set in the driver when the calibration done interrupt is received by the driver
721  */
722  if (IS_IN_STATE(ADC_STATUS_CALIBRATION_DONE))
723  {
724  *pbCalibrationDone = true;
725  }
726  else
727  {
728  *pbCalibrationDone = false;
729  }
730 
731  return ADI_ADC_SUCCESS;
732 }
733 
734 
735 
754  ADI_ADC_HANDLE hDevice,
755  uint32_t nAcqTimeInAClkCycles
756  )
757 {
758  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
759  uint16_t nCnvTime;
760 
761 #ifdef ADI_DEBUG
762  if (pDevice == NULL)
763  {
765  }
766 
767  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
768  {
770  }
771 
772  /* A valid range is 1u to the width of the SAMPTIME field + 1. */
773  if ((nAcqTimeInAClkCycles == 0u) || (nAcqTimeInAClkCycles > (ADI_MAX_ACQUISITION_TIME)))
774  {
776  }
777 
778 #endif /* ADI_DEBUG */
779 
780  /* Acquisition phase is (ADC_CNV_TIME.SAMPTIME + 1) ACLK cycles */
781  nCnvTime = pDevice->pReg->CNV_TIME;
782  nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_SAMPTIME);
783  nCnvTime |= (uint16_t)((nAcqTimeInAClkCycles - ((uint32_t)1u)) << BITP_ADC_CNV_TIME_SAMPTIME);
784  pDevice->pReg->CNV_TIME = nCnvTime;
785 
786  return ADI_ADC_SUCCESS;
787 }
788 
802  ADI_ADC_HANDLE hDevice,
803  uint32_t nDelayInAClkCycles)
804 {
805  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
806  uint16_t nCnvTime;
807 
808 #ifdef ADI_DEBUG
809  if (pDevice == NULL)
810  {
812  }
813 
814  if (nDelayInAClkCycles > (BITM_ADC_CNV_TIME_DLY >> BITP_ADC_CNV_TIME_DLY))
815  {
817  }
818 #endif /* ADI_DEBUG */
819 
820  nCnvTime = pDevice->pReg->CNV_TIME;
821  nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_DLY);
822  nCnvTime |= (uint16_t)(nDelayInAClkCycles << BITP_ADC_CNV_TIME_DLY);
823  pDevice->pReg->CNV_TIME = nCnvTime;
824 
825  return ADI_ADC_SUCCESS;
826 }
827 
844  ADI_ADC_HANDLE hDevice,
845  ADI_ADC_RESOLUTION eResolution)
846 {
847  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
848  uint16_t nFactor;
849 
850 #ifdef ADI_DEBUG
851  if (pDevice == NULL)
852  {
854  }
855  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
856  {
858  }
859  if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN) && (eResolution != ADI_ADC_RESOLUTION_12_BIT))
860  {
861  return ADI_ADC_INVALID_STATE;
862  }
863 #endif /* ADI_DEBUG */
864 
865  switch (eResolution)
866  {
868  pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_OS);
869  if (IS_NOT_IN_STATE(ADC_STATUS_AVGERAGING_EN)) {
870  pDevice->pReg->AVG_CFG = 0u;
871  }
872  CLR_STATE(ADC_STATUS_OVERSAMPLING_EN);
873  break;
874 
879  /* factor = 0x02 for 13-bit
880  0x08 for 14-bit
881  0x20 for 15-bit
882  0x80 for 16-bit */
883  nFactor = (uint16_t)1u << (((uint16_t)eResolution * 2u) - ((uint16_t)1u));
884  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN
885  | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
886  SET_STATE(ADC_STATUS_OVERSAMPLING_EN);
887 
888  break;
889 
890  default:
892  }
893 
894  return ADI_ADC_SUCCESS;
895 }
896 
912  ADI_ADC_HANDLE hDevice,
913  uint16_t nAveragingSamples
914  )
915 {
916  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
917  uint16_t nFactor;
918 
919 #ifdef ADI_DEBUG
920  if (pDevice == NULL)
921  {
923  }
924 
925  if ((nAveragingSamples == 0u) || (nAveragingSamples > 256u)
926  /* Or nAveragingSamples is not a power of 2 */
927  || ((nAveragingSamples & (nAveragingSamples - 1u)) != 0u))
928  {
930  }
931  if (IS_IN_STATE(ADC_STATUS_OVERSAMPLING_EN))
932  {
933  return ADI_ADC_INVALID_STATE;
934  }
935 #endif /* ADI_DEBUG */
936 
937  /* Disable averaging */
938  if (nAveragingSamples == 1u)
939  {
940  pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_EN);
941  CLR_STATE(ADC_STATUS_AVGERAGING_EN);
942  }
943  else
944  {
945  nFactor = nAveragingSamples >> 1;
946  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_EN | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
947  SET_STATE(ADC_STATUS_AVGERAGING_EN);
948  }
949 
950  return ADI_ADC_SUCCESS;
951 }
952 
970  ADI_ADC_HANDLE hDevice,
971  ADI_ADC_CHANNEL eChannel,
972  bool bEnable,
973  uint16_t nLowLimit
974  )
975 {
976  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
977  static volatile uint16_t* pRegister[4] = {
978  pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO
979  };
980  int32_t nChannelNum = 0;
981 
982 #ifdef ADI_DEBUG
983  if (pDevice == NULL)
984  {
986  }
987  if ((nLowLimit > (BITM_ADC_LIM0_LO_VALUE >> BITP_ADC_LIM0_LO_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
988  {
990  }
991 #endif /* ADI_DEBUG */
992 
993  nChannelNum = nGetChannelNumber(eChannel);
994 
995  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
996  if (bEnable == true) {
997 
998  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_LO_VALUE)) |
999  (uint16_t)(nLowLimit << BITP_ADC_LIM0_LO_VALUE);
1000 
1001  /* Now enable this channel comparitor - unused until the comparitor is enabled */
1002  pDevice->ComparitorLo |= (1u << nChannelNum);
1003  }
1004  else {
1005  pDevice->ComparitorLo &= ~(1u << nChannelNum);
1006  }
1007  }
1008 
1009  return ADI_ADC_SUCCESS;
1010 }
1011 
1029  ADI_ADC_HANDLE hDevice,
1030  ADI_ADC_CHANNEL eChannel,
1031  bool bEnable,
1032  uint16_t nHighLimit)
1033 {
1034  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1035  static volatile uint16_t* pRegister[4] = {
1036  pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI
1037  };
1038  int32_t nChannelNum = 0;
1039 
1040 #ifdef ADI_DEBUG
1041  if (pDevice == NULL)
1042  {
1044  }
1045  if ((nHighLimit > (BITM_ADC_LIM0_HI_VALUE >> BITP_ADC_LIM0_HI_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
1046  {
1048  }
1049 #endif /* ADI_DEBUG */
1050 
1051  nChannelNum = nGetChannelNumber(eChannel);
1052 
1053  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
1054  if (bEnable == true) {
1055  /* Set the given high value - only relevant if the limit is enabled. */
1056  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_HI_VALUE))
1057  | (uint16_t)(nHighLimit << BITP_ADC_LIM0_HI_VALUE);
1058 
1059  /* Now enable this channel comparitor - unused until the comparitor is enabled */
1060  pDevice->ComparitorHi |= (1u << nChannelNum);
1061  }
1062  else {
1063  pDevice->ComparitorHi &= ~(1u << nChannelNum);
1064  }
1065  }
1066  return ADI_ADC_SUCCESS;
1067 }
1068 
1086  ADI_ADC_HANDLE hDevice,
1087  ADI_ADC_CHANNEL eChannel,
1088  bool bEnable,
1089  uint16_t nHysteresis)
1090 {
1091  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1092  static volatile uint16_t* pRegister[4] = {
1093  pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
1094  };
1095  int32_t nChannelNum = 0;
1096 
1097 #ifdef ADI_DEBUG
1098  if (pDevice == NULL)
1099  {
1101  }
1102  if ((nHysteresis > (BITM_ADC_HYS0_VALUE >> BITP_ADC_HYS0_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
1103  {
1105  }
1106 #endif /* ADI_DEBUG */
1107 
1108  nChannelNum = nGetChannelNumber(eChannel);
1109 
1110  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
1111  if (bEnable == true) {
1112  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_VALUE))
1113  | (uint16_t)(nHysteresis << BITP_ADC_HYS0_VALUE);
1114 
1115  /* Now enable this channel hysteresis - unused until the comparitor is enabled */
1116  pDevice->ComparitorHys |= (1u << nChannelNum);
1117  }
1118  else {
1119  pDevice->ComparitorHys &= ~(1u << nChannelNum);
1120  }
1121  }
1122 
1123  return ADI_ADC_SUCCESS;
1124 }
1125 
1141  ADI_ADC_HANDLE hDevice,
1142  ADI_ADC_CHANNEL eChannel,
1143  uint32_t nNumMonitorCycles)
1144 {
1145  #ifdef ADI_DEBUG
1146  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1147 #endif /* ADI_DEBUG */
1148 
1149  static volatile uint16_t* pRegister[4] = {
1150  pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
1151  };
1152  int32_t nChannelNum = 0;
1153 
1154 #ifdef ADI_DEBUG
1155  if (pDevice == NULL)
1156  {
1158  }
1159  if ((nNumMonitorCycles > (BITM_ADC_HYS0_MONCYC >> BITP_ADC_HYS0_MONCYC)) || (nChannelNum < 0) || (nChannelNum > 3))
1160  {
1162  }
1163 #endif /* ADI_DEBUG */
1164 
1165  nChannelNum = nGetChannelNumber(eChannel);
1166 
1167  if((nChannelNum >= 0) && (nChannelNum <= 3)) {
1168  *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_MONCYC))
1169  | (uint16_t)(nNumMonitorCycles << BITP_ADC_HYS0_MONCYC);
1170  }
1171  return ADI_ADC_SUCCESS;
1172 }
1173 
1174 
1175 
1193  ADI_ADC_HANDLE hDevice,
1194  bool bEnableComparator
1195 )
1196 {
1197  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1198 #ifdef ADI_DEBUG
1199  if (pDevice == NULL)
1200  {
1202  }
1203 
1204  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN))
1205  {
1206  return ADI_ADC_INVALID_SEQUENCE;
1207  }
1208 
1209  if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN | ADC_STATUS_OVERSAMPLING_EN))
1210  {
1211  return ADI_ADC_INVALID_STATE;
1212  }
1213 
1214  if (pDevice->pfCallback == NULL) {
1216  }
1217 
1218  if (bEnableComparator == true) {
1219  if((pDevice->ComparitorHi | pDevice->ComparitorLo) == 0u) {
1220  return ADI_ADC_INVALID_STATE;
1221  }
1222  }
1223 #endif /* ADI_DEBUG */
1224 
1225  EnableComparator(pDevice, bEnableComparator);
1226 
1227  return ADI_ADC_SUCCESS;
1228 }
1229 
1248  ADI_ADC_HANDLE hDevice,
1249  ADI_ADC_BUFFER* pBuffer
1250 )
1251 {
1252  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1253  uint32_t nNumChannels = 0u;
1254 
1255  ADC_INT_BUFFER* pIntBuffer;
1256 
1257 #ifdef ADI_DEBUG
1258  if (pDevice == NULL)
1259  {
1261  }
1262  if (pBuffer == NULL) {
1263  return ADI_ADC_NULL_POINTER;
1264  }
1265  if ((pBuffer->nChannels == 0u) || (pBuffer->pDataBuffer == NULL) || (pBuffer->nNumConversionPasses == 0u))
1266  {
1267  return ADI_ADC_INVALID_BUFFER;
1268  }
1269 #endif /* ADI_DEBUG */
1270 
1271  nNumChannels = GetNumChannels(pBuffer->nChannels);
1272 
1273  pIntBuffer = &pDevice->s_Buffer;
1274 
1275  pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
1276  pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
1277  if (pBuffer->nNumConversionPasses == 1u)
1278  {
1279  pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
1280  }
1281  pIntBuffer->pUserBuffer = pBuffer;
1282  pIntBuffer->pCurDataBuffer = pBuffer->pDataBuffer;
1283  pIntBuffer->nNumSamplesRemaining = nNumChannels * pBuffer->nNumConversionPasses;
1284  pIntBuffer->nChannels = pBuffer->nChannels;
1285 
1286  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
1287 
1288  return ADI_ADC_SUCCESS;
1289 }
1290 
1311  ADI_ADC_HANDLE hDevice,
1312  ADI_ADC_BUFFER **ppBuffer)
1313 {
1314  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1315  ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
1316 
1317 #ifdef ADI_DEBUG
1318  if (pDevice == NULL)
1319  {
1321  }
1322  if (ppBuffer == NULL) {
1323  return ADI_ADC_NULL_POINTER;
1324  }
1325  if (pDevice->pfCallback != NULL) {
1327  }
1328  if (IS_NOT_IN_STATE(ADC_STATUS_NON_BLOCKING_EN)) {
1329  return ADI_ADC_INVALID_SEQUENCE;
1330  }
1331 #endif /* ADI_DEBUG */
1332 
1333  if (pDevice->s_Buffer.pUserBuffer == NULL) {
1334  return ADI_ADC_INVALID_STATE;
1335  }
1336 
1337  /* Wait for read completion */
1338  SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);
1339 
1340  if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
1341  eADCresult = ADI_ADC_BUFFER_OVERFLOW;
1342  }
1343  *ppBuffer = pDevice->s_Buffer.pUserBuffer;
1344  pDevice->s_Buffer.pUserBuffer = NULL;
1345  CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
1346 
1347  return eADCresult;
1348 }
1349 
1365  ADI_ADC_HANDLE hDevice,
1366  bool bEnable)
1367 {
1368  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1369 
1370 #ifdef ADI_DEBUG
1371  if (pDevice == NULL)
1372  {
1374  }
1375 
1376  if (IS_IN_ANY_STATE(ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
1377  return ADI_ADC_INVALID_STATE;
1378  }
1379 #endif /* ADI_DEBUG */
1380 
1381  if (bEnable == true) {
1382  /* Set the driver to be in non-blocking mode */
1383  SET_STATE(ADC_STATUS_NON_BLOCKING_EN);
1384 
1385  /* Enable the IRQs */
1386  NVIC_EnableIRQ(ADC0_EVT_IRQn);
1387 
1388  /* Try to submit possible number of buffers */
1389  InitBufferProcessing(pDevice);
1390  } else {
1391  /* Disble the IRQs */
1392  NVIC_DisableIRQ(ADC0_EVT_IRQn);
1393 
1394  /* Abort any transaction if present */
1395  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ABORT);
1396 
1397  CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
1398  }
1399 
1400  return ADI_ADC_SUCCESS;
1401 }
1402 
1403 
1420  ADI_ADC_HANDLE hDevice,
1421  bool *pbIsBufferAvailable)
1422 {
1423  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1424 #ifdef ADI_DEBUG
1425  if (pDevice == NULL)
1426  {
1428  }
1429  if (pbIsBufferAvailable == NULL)
1430  {
1431  return ADI_ADC_NULL_POINTER;
1432  }
1433  if (pDevice->pfCallback != NULL) {
1435  }
1436 #endif /* ADI_DEBUG */
1437 
1438  if(IS_IN_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS))
1439  {
1440  *pbIsBufferAvailable = false;
1441  }
1442  else
1443  {
1444  *pbIsBufferAvailable = true;
1445  }
1446 
1447  return ADI_ADC_SUCCESS;
1448 }
1449 
1450 
1480  ADI_ADC_HANDLE hDevice,
1481  uint32_t nChannels,
1482  uint32_t nNumConversionPasses,
1483  void *pBuffer,
1484  uint32_t nBuffLength)
1485 {
1486  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1487  uint32_t nNumChannels = 0u;
1488  ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
1489 
1490  ADC_INT_BUFFER* pIntBuffer;
1491 
1492 #ifdef ADI_DEBUG
1493  if (pDevice == NULL)
1494  {
1496  }
1497  if ((nChannels == 0u) || (nNumConversionPasses == 0u) || (pBuffer == NULL))
1498  {
1500  }
1501  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
1502  {
1503  return ADI_ADC_INVALID_SEQUENCE;
1504  }
1505 #endif /* ADI_DEBUG */
1506 
1507  nNumChannels = GetNumChannels(nChannels);
1508 
1509  if (nBuffLength < ((nNumChannels * sizeof(uint16_t)) * nNumConversionPasses))
1510  {
1512  }
1513 
1514  /* Clear ADC status */
1515  pDevice->pReg->STAT = 0xFFFFu;
1516 
1517  /* Set the driver to be in blocking mode */
1518  SET_STATE(ADC_STATUS_BLOCKING_EN);
1519 
1520  /* Get the buffer */
1521  pIntBuffer = &pDevice->s_Buffer;
1522 
1523  pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
1524  if (nNumConversionPasses == 1u) {
1525  pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
1526  }
1527 
1528  pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
1529  pIntBuffer->pUserBuffer = NULL;
1530  pIntBuffer->pCurDataBuffer = pBuffer;
1531  pIntBuffer->nNumSamplesRemaining = nNumChannels * nNumConversionPasses;
1532  pIntBuffer->nChannels = nChannels;
1533 
1534  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
1535 
1536  InitBufferProcessing(pDevice);
1537 
1538  /* Wait for read completion */
1539  SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);
1540 
1541  if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
1542  eADCresult = ADI_ADC_BUFFER_OVERFLOW;
1543  }
1544 
1545  /* Driver is no longer in blocking mode */
1546  CLR_STATE(ADC_STATUS_BLOCKING_EN);
1547 
1548  /* Enable the IRQs */
1549  NVIC_DisableIRQ(ADC0_EVT_IRQn);
1550 
1551  return eADCresult;
1552 }
1553 
1554 
1575  ADI_ADC_HANDLE hDevice,
1576  uint32_t nRefVoltage,
1577  uint32_t *pnBatVoltage)
1578 {
1579  ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
1580  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1581  uint16_t nConvTimeBackup;
1582  uint16_t nAvgCfgBackup;
1583  uint32_t nAdcValue = 0u;
1584  uint32_t nClock = 0u;
1585  uint32_t nACLKDIVCNT;
1586 
1587 #ifdef ADI_DEBUG
1588  if (pDevice == NULL)
1589  {
1591  }
1592  if (pnBatVoltage == NULL)
1593  {
1594  return ADI_ADC_NULL_POINTER;
1595  }
1596 
1597  if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
1598  return ADI_ADC_INVALID_SEQUENCE;
1599  }
1600 
1601  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
1602  return ADI_ADC_INVALID_SEQUENCE;
1603  }
1604 #endif /* ADI_DEBUG */
1605 
1607  {
1608  /* Take the backup of registers that need to be changed */
1609  nConvTimeBackup = pDevice->pReg->CNV_TIME;
1610  nAvgCfgBackup = pDevice->pReg->AVG_CFG;
1611 
1612  /* Set the required value in the registers. */
1613  nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
1614 
1615  /* Calculate the number of cycles required for conversion.
1616  * The conversion time required is 500ns = 2000000Hz
1617  */
1618  nClock = nClock/nACLKDIVCNT; /* nClock = ACLK frequency Hz */
1619  pDevice->pReg->CNV_TIME = (uint16_t)((nClock/2000000u) + ((uint16_t)1u));
1620  pDevice->pReg->AVG_CFG = 0u;
1621 
1622  /* Clear the battery done status */
1623  pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
1624 
1625  /* Clear the battery done state */
1626  CLR_STATE(ADC_STATUS_BATTERY_DONE);
1627 
1628  /* Set the registers */
1629  pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_BAT);
1630 
1631  /* Wait for the Battery done status */
1632  while (IS_NOT_IN_STATE(ADC_STATUS_BATTERY_DONE)) { ; }
1633 
1634  /* Clear the conversion register */
1635  pDevice->pReg->CNV_CFG = 0u;
1636 
1637  /* Restore the changed registers */
1638  pDevice->pReg->CNV_TIME = nConvTimeBackup;
1639  pDevice->pReg->AVG_CFG = nAvgCfgBackup;
1640 
1641  /* Calculate the battery voltage */
1642 
1643  /* From HRM: converting ADC result to battery voltage, following calculations should be done:
1644  * VBAT = 4 * (adc_out) * Vref / (2^12 - 1) */
1645  nAdcValue = pDevice->pReg->BAT_OUT;
1646  *pnBatVoltage = (4u * nAdcValue * nRefVoltage) / ADI_ADC_SAMPLE_MAX;
1647  }
1648  else
1649  {
1650  eResult = ADI_ADC_BAD_SYS_CLOCK;
1651  }
1652 
1653  return eResult;
1654 }
1668  ADI_ADC_HANDLE hDevice,
1669  bool bEnable)
1670 {
1671  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1672 
1673 #ifdef ADI_DEBUG
1674  if (pDevice == NULL)
1675  {
1677  }
1678 #endif /* ADI_DEBUG */
1679 
1680  if (bEnable == true)
1681  {
1682  pDevice->pReg->CFG |= (uint16_t)BITM_ADC_CFG_TMPEN;
1683  SET_STATE(ADC_STATUS_TEMP_SENSOR_EN);
1684  }
1685  else
1686  {
1687  pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_TMPEN);
1688  CLR_STATE(ADC_STATUS_TEMP_SENSOR_EN);
1689  }
1690 
1691  return ADI_ADC_SUCCESS;
1692 }
1693 
1694 
1719  ADI_ADC_HANDLE hDevice,
1720  uint32_t nRefVoltage,
1721  int32_t* pnTemperature
1722  )
1723 {
1724  ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
1725  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
1726  uint16_t nConvTimeBackup;
1727  uint16_t nAvgCfgBackup;
1728  uint32_t nAdcTmpValue = 0u;
1729  uint32_t nAdcTmp2Value = 0u;
1730  uint32_t nClock = 0u;
1731  uint32_t nACLKDIVCNT;
1732  uint32_t nCnvTime;
1733 
1734 #ifdef ADI_DEBUG
1735  if (pDevice == NULL)
1736  {
1738  }
1739  if (pnTemperature == NULL)
1740  {
1741  return ADI_ADC_NULL_POINTER;
1742  }
1743 
1744  if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_TEMP_SENSOR_EN))
1745  {
1746  return ADI_ADC_INVALID_SEQUENCE;
1747  }
1748 
1749  if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
1750  {
1751  return ADI_ADC_INVALID_SEQUENCE;
1752  }
1753 #endif
1754 
1755 
1757  {
1758  /* Calculate the conversion time */
1759  nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
1760  nCnvTime = ((nClock / nACLKDIVCNT) / (uint16_t)15385u) + 1u; /* 65us acquisition time required = 15385Hz sample */
1761 
1762  #ifdef ADI_DEBUG
1763  if (nCnvTime >= 256u) {
1764  return ADI_ADC_INVALID_STATE;
1765  }
1766  #endif
1767  /* Take the backup of registers that need to be changed */
1768  nConvTimeBackup = pDevice->pReg->CNV_TIME;
1769  nAvgCfgBackup = pDevice->pReg->AVG_CFG;
1770 
1771  /* Set the required value in the registers. */
1772 
1773  pDevice->pReg->CNV_TIME = (uint16_t)((nCnvTime << BITP_ADC_CNV_TIME_SAMPTIME) & BITM_ADC_CNV_TIME_SAMPTIME);
1774  pDevice->pReg->AVG_CFG = 0u;
1775 
1776  /* Clear the temperature done status */
1777  pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE | BITM_ADC_STAT_TMP2DONE;
1778 
1779  /* Clear the temperature done state */
1780  CLR_STATE(ADC_STATUS_TMP_DONE | ADC_STATUS_TMP2_DONE);
1781 
1782  /* Sample Tmp register */
1783  pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP);
1784  while (IS_NOT_IN_STATE(ADC_STATUS_TMP_DONE)) { ; }
1785  nAdcTmpValue = pDevice->pReg->TMP_OUT;
1786  pDevice->pReg->CNV_CFG = 0u;
1787 
1788 
1789  /* Sample Tmp2 register */
1790  pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP2);
1791  while (IS_NOT_IN_STATE(ADC_STATUS_TMP2_DONE)) { ; }
1792  pDevice->pReg->CNV_CFG = 0u;
1793  nAdcTmp2Value = pDevice->pReg->TMP2_OUT;
1794 
1795  /* Restore the changed registers */
1796  pDevice->pReg->CNV_TIME = nConvTimeBackup;
1797  pDevice->pReg->AVG_CFG = nAvgCfgBackup;
1798 
1799  /* Calculate the temperature voltage.
1800  * From the HRM: Temperature can be calculated as:
1801  *
1802  * T(^0 C)= code1/(code2+RG*code1)*Rvirtualreference/(ideal_sensitivity )-273.15
1803  *
1804  * Some of these values are constants, and some have been read from registers.
1805  * The above formula, when populated with variables and constants, would look like this:
1806  * T(^0 C)= (nAdcTmpValue/(nAdcTmp2Value + nTempRG * nAdcTmpValue)) * (1.2256/1.2411e-3)) -273.15
1807  */
1808  {
1809  uint32_t nRVirRefByIdealSensitivity = 2070960834u; /* 1.2256/1.2411e-3 in 11.21 format */
1810 
1811  uint32_t nTempRG = 19380u; /* 1.1829 in 2.14 format */
1812  uint32_t nTmp2 = ((nAdcTmp2Value << 14u) + (nTempRG * nAdcTmpValue)); /* in 14.14 format */
1813 
1814  uint32_t nOffsetPart = (335544320u/nRefVoltage); /* (1.25 in 4.28 format / ReferenceVoltage(16.16)) = Result in format *.12 */
1815  uint32_t nOffset = (161u * nOffsetPart); /* 12.12 format */
1816 
1817  uint32_t nTmp3 = ((nAdcTmpValue << 12) - nOffset) << 8u; /* Format 12.20 */
1818  uint32_t nRatio = (nTmp3/(nTmp2 >> 10u)); /* nTmp2 resolution reduced by 10 to 14.4 and the result resolution is 0.16 */
1819  uint32_t nTemp = (nRatio * (nRVirRefByIdealSensitivity >> 16u)) >> 5u; /* Temperature in degree kelvin in 16.16 format */
1820 
1821  int32_t iTemp = (int32_t)nTemp - ((int32_t)17901158); /* Subtract 273.15 (in 16.16) to get the temperature in degree celcius */
1822  *pnTemperature = iTemp;
1823  }
1824  }
1825  else
1826  {
1827  eResult = ADI_ADC_BAD_SYS_CLOCK;
1828  }
1829 
1830  return eResult;
1831 }
1832 
1833 
1836 /*========== S T A T I C F U N C T I O N S ==========*/
1837 /* Read the output register for the given channel number */
1838 static uint16_t ReadOutReg(uint32_t nChannelNum)
1839 {
1840  const volatile uint16_t* pOutRegister = pREG_ADC0_CH0_OUT;
1841  pOutRegister += nChannelNum*2u;
1842  return *pOutRegister;
1843 }
1844 
1845 /* Init buffer processing */
1846 static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice)
1847 {
1848  uint32_t nCnvReg = ((uint32_t)(pDevice->pReg->CNV_CFG) & BITM_ADC_CNV_CFG_DMAEN);
1849  ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
1850 
1851  if (IS_NOT_IN_ANY_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS))
1852  {
1853  /* Clear conversion done flags */
1854  pDevice->pReg->STAT = 0xFFFFu;
1855 
1856  /* Clear the overflow and alert register */
1857  pDevice->pReg->OVF = 0xFFFFu;
1858  }
1859 
1860  /* Calculate the conversion register value for the given configuration */
1861  nCnvReg |= pIntBuffer->nChannels;
1862  if ((uint16_t)(pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN) != 0u) {
1863  nCnvReg |= BITM_ADC_CNV_CFG_AUTOMODE;
1864  }
1865  if ((pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN) != 0u) {
1866  nCnvReg |= BITM_ADC_CNV_CFG_SINGLE;
1867  } else {
1868  nCnvReg |= BITM_ADC_CNV_CFG_MULTI;
1869  }
1870 
1871  SET_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
1872 
1873  pDevice->pReg->CNV_CFG |= (uint16_t)nCnvReg;
1874 
1875  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ENABLED);
1876 
1877  return true;
1878 }
1879 
1880 
1881 #if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
1882 /* DMA Callback Handler */
1883 void DMA_ADC0_Int_Handler (void)
1884 {
1885  ISR_PROLOG();
1886  ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
1887 
1888  DmaFIFOManage(pDevice, ADC_FIFO_MODE_DMA_BUFFER_PROCESS);
1889 
1890  ISR_EPILOG();
1891 }
1892 
1893 static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
1894 {
1895  uint16_t nCount = 0u;
1896  uint16_t chanNum = ADC0_CHANn;
1897  uint16_t IRQ_Backup;
1898 
1899  ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
1900 
1901  if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
1902  /* If there is nothing active... */
1903  if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
1904  /* ...it's something leftover, so cleanup. */
1905  uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
1906  FlushFifo(pDevice, (uint32_t)nStat);
1907  pDevice->pReg->STAT = nStat;
1908  }
1909  }
1910  else {
1911  switch (eFifoMode)
1912  {
1913  case ADC_FIFO_MODE_INIT:
1914 
1915  /* Enable the interrupt for the given DMA */
1916  NVIC_EnableIRQ(DMA0_CH24_DONE_IRQn);
1917 
1918  pADI_DMA0->SRCADDR_CLR = 1U << chanNum;
1919 
1920  /* Enable the channel */
1921  pADI_DMA0->EN_SET = 1U << chanNum;
1922 
1923  /* Enables peripheral to generate DMA requests. */
1924  pADI_DMA0->RMSK_CLR = 1U << chanNum;
1925 
1926  /* Set the primary as the current DMA descriptor */
1927  pADI_DMA0->ALT_CLR = 1U << chanNum; /* Should be default */
1928 
1929  /* Setup the DMA registers */
1930  nCount = (uint16_t)pIntBuffer->nNumSamplesRemaining;
1931 
1932  /* Point to the end of the DMA source */
1933  pPrimaryCCD[chanNum].DMASRCEND = (uint32_t)(&(pDevice->pReg->DMA_OUT));
1934 
1935  /* Point to the end of the DMA write-to destination */
1936  pPrimaryCCD[chanNum].DMADSTEND = (uint32_t)((void*)pIntBuffer->pCurDataBuffer) + ((nCount * 2u) - 1u);
1937 
1938  /* Configure the DMA itself */
1939  pPrimaryCCD[chanNum].DMACDC = ((ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | /* Increment destination address */
1940  (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | /* Don't increment the source address */
1941  ((uint32_t)ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | /* 16bit transfers */
1942  ((nCount - (uint32_t)1U)<< DMA_BITP_CTL_N_MINUS_1) | /* Data size? */
1943  (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) | /* Basic only */
1944  ((uint32_t)ADI_DMA_RPOWER_1 << DMA_BITP_CTL_R_POWER)); /* Arbitration */
1945 
1946  /* Enable DMA */
1947  pDevice->pReg->CNV_CFG |= BITM_ADC_CNV_CFG_DMAEN;
1948  break;
1949 
1950  case ADC_FIFO_MODE_ENABLED:
1951  break;
1952 
1953  case ADC_FIFO_MODE_INTERRUPT_PROCESS:
1954  /* Clear the status registers */
1955  pDevice->pReg->STAT = (pDevice->pReg->STAT & 0x00FFu);
1956  break;
1957 
1958  case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
1959  pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
1960  break;
1961 
1962  case ADC_FIFO_MODE_DMA_BUFFER_PROCESS:
1963  pIntBuffer->nNumSamplesRemaining = 0u;
1964  ManageFifoCompletion(pDevice);
1965  break;
1966 
1967  case ADC_FIFO_MODE_ABORT:
1968 
1969  /* Take backup of IRQ */
1970  IRQ_Backup = pDevice->pReg->IRQ_EN;
1971 
1972  /* Disable the IRQ */
1973  pDevice->pReg->IRQ_EN = 0u;
1974 
1975  /* Clear the conversion cfg register to stop any transaction */
1976  pDevice->pReg->CNV_CFG = 0u;
1977 
1978  /* Disable the DMA channel */
1979  pADI_DMA0->EN_CLR = 1U << chanNum;
1980 
1981  /* Clear the status bits */
1982  pDevice->pReg->STAT = pDevice->pReg->STAT;
1983 
1984  /* Clear the sampling in progress state */
1985  CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
1986 
1987  /* Read and flush all the buffers */
1988  FlushFifo(pDevice, 0x00FFu);
1989 
1990  /* Restore the IRQ */
1991  pDevice->pReg->IRQ_EN = IRQ_Backup;
1992 
1993  break;
1994 
1995  default:
1996  break;
1997  }
1998  }
1999 
2000  return ADI_ADC_SUCCESS;
2001 }
2002 #else /* else ADI_ADC_ENABLE_MULTI_ACQUIRE == 0 */
2003 
2004 static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
2005 {
2006  ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
2007 
2008  if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
2009  if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
2010  uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
2011  FlushFifo(pDevice, (uint32_t)nStat);
2012  pDevice->pReg->STAT = nStat;
2013  }
2014  return ADI_ADC_SUCCESS;
2015  }
2016 
2017  switch (eFifoMode)
2018  {
2019  case ADC_FIFO_MODE_INIT:
2020  {
2021  /* Enable the conversion done and overflow interrupt */
2022  pDevice->ActData.nCurChannel = 0u;
2023  }
2024  break;
2025 
2026  case ADC_FIFO_MODE_ENABLED:
2027  break;
2028 
2029  case ADC_FIFO_MODE_INTERRUPT_PROCESS:
2030  {
2031  while (pIntBuffer->nNumSamplesRemaining > 0u) {
2032  uint32_t nConvStatus = ((uint32_t)pDevice->pReg->STAT & (uint32_t)0x00FFu);
2033  if ((nConvStatus & 0x00FFu) == 0u)
2034  {
2035  break;
2036  }
2037 
2038  uint32_t nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
2039  while ((nCurChannelBitM & nConvStatus) == 0u) {
2040  pDevice->ActData.nCurChannel++;
2041  if (pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
2042  pDevice->ActData.nCurChannel = 0u;
2043  }
2044  nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
2045  }
2046 
2047  assert ((pIntBuffer->nChannels & ((uint32_t)1u << pDevice->ActData.nCurChannel)) != 0u);
2048 
2049  *pIntBuffer->pCurDataBuffer = ReadOutReg( pDevice->ActData.nCurChannel);
2050  pIntBuffer->pCurDataBuffer++;
2051 
2052 
2053  pDevice->pReg->STAT = (uint16_t)nCurChannelBitM;
2054  pIntBuffer->nNumSamplesRemaining -= 1u;
2055 
2056  pDevice->ActData.nCurChannel += 1u;
2057  if ( pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
2058  pDevice->ActData.nCurChannel = 0u;
2059  }
2060  }
2061 
2062  if (pIntBuffer->nNumSamplesRemaining == 0u) {
2063  ManageFifoCompletion(pDevice);
2064  }
2065  }
2066  break;
2067 
2068  case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
2069  {
2070  pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
2071  }
2072  break;
2073 
2074  case ADC_FIFO_MODE_ABORT:
2075  {
2076  uint16_t IRQ_Backup;
2077 
2078  /* Take backup of IRQ */
2079  IRQ_Backup = pDevice->pReg->IRQ_EN;
2080 
2081  /* Disable the IRQ */
2082  pDevice->pReg->IRQ_EN = 0u;
2083 
2084  /* Clear the conversion cfg register to stop any transaction */
2085  pDevice->pReg->CNV_CFG = 0u;
2086 
2087  /* Clear the status bits */
2088  pDevice->pReg->STAT = pDevice->pReg->STAT;
2089 
2090  /* Clear the sampling in progress state */
2091  CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
2092 
2093  /* Read and flush all the buffers */
2094  FlushFifo(pDevice, 0x00FFu);
2095 
2096  /* Restore the IRQ */
2097  pDevice->pReg->IRQ_EN = IRQ_Backup;
2098  }
2099  break;
2100 
2101  default:
2102  break;
2103  }
2104 
2105  return ADI_ADC_SUCCESS;
2106 }
2107 #endif
2108 
2109 static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels)
2110 {
2111  uint32_t x;
2112  for (x = 0u; x < 8u; x++) {
2113  if ((nChannels & ((uint32_t)1u << x)) != 0u) {
2114  ReadOutReg(x);
2115  }
2116  }
2117 }
2118 
2119 
2120 /* Called when a transfer is complete */
2121 static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice)
2122 {
2123  /* Clear the conversion configuration */
2124  pDevice->pReg->CNV_CFG = 0u;
2125  CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
2126 
2127  SEM_POST(pDevice);
2128 }
2129 
2130 
2131 /* Internal function to extract the number of channels
2132  * in a 32bit word. */
2133 static uint32_t GetNumChannels(uint32_t nChannels)
2134 {
2135  uint32_t n = nChannels & 0x000000FFu;
2136 
2137  n = (n & 0x00000055u) + ((n >> 1u) & 0x00000055u);
2138  n = (n & 0x00000033u) + ((n >> 2u) & 0x00000033u);
2139  n = (n + (n >> 4u)) & (0x0000000Fu);
2140 
2141  return n;
2142 }
2143 
2144 /* Returns the channel number based on the ADI_ADC_CHANNEL type.
2145  * i.e. ADI_ADC_CHANNEL1 returns 1. */
2146 static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel)
2147 {
2148  int32_t retVal = 0;
2149  uint32_t nChannel = (uint32_t)eChannel & 0x000000FFu;
2150 
2151  if ((nChannel & (nChannel - (uint32_t)1u)) != 0u) {
2152  return -1;
2153  }
2154  if ((nChannel & 0x000000AAu) != 0u) { retVal += 1; }
2155  if ((nChannel & 0x000000CCu) != 0u) { retVal += 2; }
2156  if ((nChannel & 0x000000F0u) != 0u) { retVal += 4; }
2157 
2158  return retVal;
2159 }
2160 
2161 /* Internal function to set static configuration options. */
2162 static void StaticConfiguration(ADI_ADC_DEVICE *pDevice)
2163 {
2164  uint16_t nCfgReg = 0u;
2165 
2166  /* Configure the resolution */
2167 #if ADI_ADC_CFG_RESOLUTION == 12
2168  pDevice->pReg->AVG_CFG = 0u;
2169 #else
2170 
2171 #if ADI_ADC_CFG_RESOLUTION == 13
2172  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0002u << BITP_ADC_AVG_CFG_FACTOR);
2173 #elif ADI_ADC_CFG_RESOLUTION == 14
2174  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0008u << BITP_ADC_AVG_CFG_FACTOR);
2175 #elif ADI_ADC_CFG_RESOLUTION == 15
2176  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0020u << BITP_ADC_AVG_CFG_FACTOR);
2177 #elif ADI_ADC_CFG_RESOLUTION == 16
2178  pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0080u << BITP_ADC_AVG_CFG_FACTOR);
2179 #else
2180 #error "Invalid Resolution"
2181 #endif
2182 
2183  SET_STATE(ADC_STATUS_OVERSAMPLING_EN);
2184 #endif
2185 
2186  /* Configure the VREF */
2187 #if ADI_ADC_CFG_VREF == 0 /* 1.25V Internal Reference*/
2188  nCfgReg |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
2189 #elif ADI_ADC_CFG_VREF == 1 /* 2.5V Internal Reference */
2190  nCfgReg |= BITM_ADC_CFG_REFBUFEN;
2191 #elif ADI_ADC_CFG_VREF == 2 /* Battery Voltage */
2192  nCfgReg |= BITM_ADC_CFG_VREFVBAT;
2193 #endif
2194 
2195  pDevice->pReg->CFG = nCfgReg;
2196 
2197 #if ADI_ADC_ENABLE_STATIC_COMPARATOR == 1
2198  /* High limit registers */
2199 #if ADI_ADC_COMPARATOR_AIN0_HI_EN == 1
2200  pDevice->pReg->LIM0_HI = ADI_ADC_COMPARATOR_AIN0_HI_VAL;
2201  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_0;
2202 #endif
2203 #if ADI_ADC_COMPARATOR_AIN1_HI_EN == 1
2204  pDevice->pReg->LIM1_HI = ADI_ADC_COMPARATOR_AIN1_HI_VAL;
2205  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_1;
2206 #endif
2207 #if ADI_ADC_COMPARATOR_AIN2_HI_EN == 1
2208  pDevice->pReg->LIM2_HI = ADI_ADC_COMPARATOR_AIN2_HI_VAL;
2209  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_2;
2210 #endif
2211 #if ADI_ADC_COMPARATOR_AIN3_HI_EN == 1
2212  pDevice->pReg->LIM3_HI = ADI_ADC_COMPARATOR_AIN3_HI_VAL;
2213  pDevice->ComparitorHi |= ADI_ADC_CHANNEL_3;
2214 #endif
2215  /* Low limit registers */
2216 #if ADI_ADC_COMPARATOR_AIN0_LO_EN == 1
2217  pDevice->pReg->LIM0_LO = (uint16_t)ADI_ADC_COMPARATOR_AIN0_LO_VAL;
2218  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_0;
2219 #endif
2220 #if ADI_ADC_COMPARATOR_AIN1_LO_EN == 1
2221  pDevice->pReg->LIM1_LO = ADI_ADC_COMPARATOR_AIN1_LO_VAL;
2222  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_1;
2223 #endif
2224 #if ADI_ADC_COMPARATOR_AIN2_LO_EN == 1
2225  pDevice->pReg->LIM2_LO = ADI_ADC_COMPARATOR_AIN2_LO_VAL;
2226  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_2;
2227 #endif
2228 #if ADI_ADC_COMPARATOR_AIN3_LO_EN == 1
2229  pDevice->pReg->LIM3_LO = ADI_ADC_COMPARATOR_AIN3_LO_VAL;
2230  pDevice->ComparitorLo |= ADI_ADC_CHANNEL_3;
2231 #endif
2232 
2233  /* Hysteresis registers */
2234 #if ADI_ADC_COMPARATOR_AIN0_HYS_EN == 1
2235  pDevice->pReg->HYS0 = (uint16_t)(ADI_ADC_COMPARATOR_AIN0_HYS_VAL | (ADI_ADC_COMPARATOR_AIN0_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2236  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_0;
2237 #endif
2238 #if ADI_ADC_COMPARATOR_AIN1_HYS_EN == 1
2239  pDevice->pReg->HYS1 = (ADI_ADC_COMPARATOR_AIN1_HYS_VAL | (ADI_ADC_COMPARATOR_AIN1_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2240  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_1;
2241 #endif
2242 #if ADI_ADC_COMPARATOR_AIN2_HYS_EN == 1
2243  pDevice->pReg->HYS2 = (ADI_ADC_COMPARATOR_AIN2_HYS_VAL | (ADI_ADC_COMPARATOR_AIN2_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2244  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_2;
2245 #endif
2246 #if ADI_ADC_COMPARATOR_AIN3_HYS_EN == 1
2247  pDevice->pReg->HYS3 = (ADI_ADC_COMPARATOR_AIN3_HYS_VAL | (ADI_ADC_COMPARATOR_AIN3_HYS_CYC << BITP_ADC_HYS0_MONCYC));
2248  pDevice->ComparitorHys |= ADI_ADC_CHANNEL_3;
2249 #endif
2250 #endif
2251 
2252 }
2253 
2254 /* Internal function to enable the comparitor for previously-configured channels
2255  * Does not set the limits, only enables.
2256 */
2257 static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable)
2258 {
2259  uint32_t x;
2260  uint16_t nCnvCfg = 0u;
2261  volatile uint16_t* pLO_Register[4] = {pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO};
2262  volatile uint16_t* pHI_Register[4] = {pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI};
2263  volatile uint16_t* pHYS_Register[4] = {pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3};
2264 
2265  if (bEnable == true)
2266  {
2267  /* Loop round all the channels enabling each part if required. */
2268  for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
2269  if((pDevice->ComparitorHi & (1u << x)) > 0u) {
2270  *pHI_Register[x] |= BITM_ADC_LIM0_HI_EN;
2271  }
2272  if((pDevice->ComparitorLo & (1u << x)) > 0u) {
2273  *pLO_Register[x] |= BITM_ADC_LIM0_LO_EN;
2274  }
2275  if((pDevice->ComparitorHys & (1u << x)) > 0u) {
2276  *pHYS_Register[x] |= BITM_ADC_HYS0_EN;
2277  }
2278  }
2279  nCnvCfg = (uint16_t)((uint16_t)pDevice->ComparitorHi | (uint16_t)pDevice->ComparitorLo);
2280 
2281  pDevice->pReg->IRQ_EN &= (uint16_t)(~BITM_ADC_IRQ_EN_CNVDONE);
2282  pDevice->pReg->CNV_CFG = (uint16_t)nCnvCfg | (uint16_t)(BITM_ADC_CNV_CFG_MULTI | BITM_ADC_CNV_CFG_AUTOMODE);
2283  SET_STATE(ADC_STATUS_COMPARATOR_EN);
2284  }
2285  else {
2286  /* Loop round disabling all. */
2287  for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
2288  *pHI_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_HI_EN));
2289  *pLO_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_LO_EN));
2290  *pHYS_Register[x] &= (uint16_t)(~(BITM_ADC_HYS0_EN));
2291  }
2292  pDevice->pReg->CNV_CFG = 0u;
2293  pDevice->pReg->STAT = pDevice->pReg->STAT & 0x00FFu;
2294  CLR_STATE(ADC_STATUS_COMPARATOR_EN);
2295  pDevice->pReg->IRQ_EN |= BITM_ADC_IRQ_EN_CNVDONE;
2296  }
2297 }
2298 
2299 
2300 /* In Handler handles the following cases:
2301  * ADI_ADC_EVENT_ADC_READY
2302  * ADI_ADC_EVENT_CALIBRATION_DONE
2303  * ADC_STATUS_BATTERY_DONE
2304  * ADC_STATUS_TMP_DONE
2305  * ADC_STATUS_TMP2_DONE
2306  * ADI_ADC_EVENT_HIGH_LIMIT_CROSSED
2307  * ADI_ADC_EVENT_LOW_LIMIT_CROSSED
2308 */
2309 #if defined(__ADUCM302x__)
2310 void ADC_Int_Handler(void)
2311 #else
2312 void ADC0_Int_Handler(void)
2313 #endif
2314 {
2315  ADI_ADC_DEVICE *pDevice;
2316  ISR_PROLOG();
2317 
2318  pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
2319 
2320  if ((pDevice->pReg->STAT & 0x00FFu) != 0u) {
2321  if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
2322  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_PROCESS);
2323  } else {
2324  pDevice->pReg->STAT = pDevice->pReg->STAT & (0x00FFu);
2325  }
2326  }
2327  if ((uint16_t)(pDevice->pReg->STAT & 0xFF00u) != 0u) {
2328  if ((pDevice->pReg->STAT & BITM_ADC_STAT_RDY) != 0u) {
2329  SET_STATE(ADC_STATUS_SUB_SYSTEM_READY);
2330  pDevice->pReg->STAT = BITM_ADC_STAT_RDY;
2331  if (pDevice->pfCallback != NULL) {
2332  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_ADC_READY, NULL);
2333  }
2334  }
2335  if ((pDevice->pReg->STAT & BITM_ADC_STAT_CALDONE) != 0u) {
2336  SET_STATE(ADC_STATUS_CALIBRATION_DONE);
2337  pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
2338  if (pDevice->pfCallback != NULL) {
2339  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_CALIBRATION_DONE, NULL);
2340  }
2341  }
2342  if ((pDevice->pReg->STAT & BITM_ADC_STAT_BATDONE) != 0u) {
2343  SET_STATE(ADC_STATUS_BATTERY_DONE);
2344  pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
2345  }
2346 
2347  if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMPDONE) != 0u) {
2348  SET_STATE(ADC_STATUS_TMP_DONE);
2349  pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE;
2350  }
2351 
2352  if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMP2DONE) != 0u) {
2353  SET_STATE(ADC_STATUS_TMP2_DONE);
2354  pDevice->pReg->STAT = BITM_ADC_STAT_TMP2DONE;
2355  }
2356  }
2357  if (pDevice->pReg->OVF) {
2358  uint16_t nOvrFlowValue = pDevice->pReg->OVF;
2359  if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
2360  pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_OVERFLOW);
2361  }
2362  pDevice->pReg->OVF = nOvrFlowValue;
2363  }
2364  if (pDevice->pReg->ALERT) {
2365  uint32_t nAlertValue = pDevice->pReg->ALERT;
2366  uint32_t channel;
2367  if (IS_IN_STATE(ADC_STATUS_COMPARATOR_EN) && (pDevice->pfCallback != NULL)) {
2368  for (channel = 0u; channel < (NUM_ADC_COMPARATOR_CHANNELS); channel++) {
2369  /* Alert bit positions: hi limits are 0b01,
2370  * lo limit alerts are 0b10.
2371  */
2372  if((nAlertValue & (1u << (2u * channel))) > 0u) {
2373  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, (void*)channel);
2374  }
2375  if((nAlertValue & (1u << ((2u * channel) + ((uint32_t)1u)))) > 0u)
2376  {
2377  pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_LOW_LIMIT_CROSSED, (void*)channel);
2378  }
2379  }
2380  }
2381  pDevice->pReg->ALERT = (uint16_t)nAlertValue;
2382  }
2383  ISR_EPILOG();
2384 }
2385 
2386 
2389 #endif /* ADI_ADC_C */
2390 
2391 /*****/
2392 
#define ADI_ADC_COMPARATOR_AIN1_LO_VAL
ADI_ADC_RESULT adi_adc_Close(ADI_ADC_HANDLE hDevice)
Close the given device instance.
Definition: adi_adc.c:255
ADI_ADC_RESULT adi_adc_SetLowLimit(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, bool bEnable, uint16_t nLowLimit)
Configure low limit for an ADC channel when it is used as a digital comparator.
Definition: adi_adc.c:969
ADI_ADC_RESULT adi_adc_IsCalibrationDone(ADI_ADC_HANDLE hDevice, bool *pbCalibrationDone)
Returns the status of the calibration which was initiated.
Definition: adi_adc.c:701
ADI_ADC_RESULT adi_adc_EnableTemperatureSensor(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable or disable the temperature sensor.
Definition: adi_adc.c:1667
ADI_ADC_RESULT adi_adc_EnableAveraging(ADI_ADC_HANDLE hDevice, uint16_t nAveragingSamples)
Enable Averaging for all ADC channels.
Definition: adi_adc.c:911
#define ADI_ADC_COMPARATOR_AIN1_HI_VAL
#define ADI_ADC_CHANNEL_0
Definition: adi_adc.h:124
#define ADI_ADC_COMPARATOR_AIN2_LO_VAL
ADI_ADC_RESULT adi_adc_SetHysteresis(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, bool bEnable, uint16_t nHysteresis)
Configure hysteresis for an ADC channel when it&#39;s used as a digital comparator.
Definition: adi_adc.c:1085
uint32_t ADI_ADC_CHANNEL
Definition: adi_adc.h:119
ADI_ADC_RESULT adi_adc_ReadChannels(ADI_ADC_HANDLE hDevice, uint32_t nChannels, uint32_t nNumConversionPasses, void *pBuffer, uint32_t nBuffLength)
Sample the given channels for the given number of conversion passes and put it into the given buffer...
Definition: adi_adc.c:1479
#define ADI_ADC_COMPARATOR_AIN3_HYS_CYC
ADI_ADC_RESULT adi_adc_SinkEnable(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable/Disable Current Sink.
Definition: adi_adc.c:614
ADI_ADC_RESULT adi_adc_Open(uint32_t nDeviceNum, void *pMemory, uint32_t nMemorySize, ADI_ADC_HANDLE *phDevice)
Opens an ADC device instance.
Definition: adi_adc.c:179
#define ADI_ADC_COMPARATOR_AIN1_HYS_VAL
ADI_ADC_RESULT adi_adc_SetDelayTime(ADI_ADC_HANDLE hDevice, uint32_t nDelayInAClkCycles)
Set the delay time of ADC in ADC cycles for multi iteration mode.
Definition: adi_adc.c:801
ADI_ADC_RESULT adi_adc_EnableADCSubSystem(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable/Disables the ADC Subsystem.
Definition: adi_adc.c:438
#define ADI_ADC_COMPARATOR_AIN0_HYS_CYC
ADI_ADC_RESULT adi_adc_SetNumMonitorCycles(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, uint32_t nNumMonitorCycles)
Configure number of monitor cycles for an ADC channel when it&#39;s used as a digital comparator...
Definition: adi_adc.c:1140
#define ADI_ADC_CHANNEL_3
Definition: adi_adc.h:127
ADI_ADC_VREF_SRC
Definition: adi_adc.h:96
ADI_ADC_RESULT adi_adc_PowerUp(ADI_ADC_HANDLE hDevice, bool bPowerUp)
Power up ADC.
Definition: adi_adc.c:309
#define ADI_ADC_COMPARATOR_AIN0_LO_VAL
ADI_ADC_RESULT adi_adc_GetBuffer(ADI_ADC_HANDLE hDevice, ADI_ADC_BUFFER **ppBuffer)
Get a processed buffer from the ADC Driver. This function is a blocking call and will only return onc...
Definition: adi_adc.c:1310
ADI_ADC_RESULT adi_adc_GetBatteryVoltage(ADI_ADC_HANDLE hDevice, uint32_t nRefVoltage, uint32_t *pnBatVoltage)
Returns the battery voltage.
Definition: adi_adc.c:1574
ADI_ADC_RESULT adi_adc_SetHighLimit(ADI_ADC_HANDLE hDevice, ADI_ADC_CHANNEL eChannel, bool bEnable, uint16_t nHighLimit)
Configure high limit for an ADC channel when it&#39;s used as a digital comparator.
Definition: adi_adc.c:1028
void * pDataBuffer
Definition: adi_adc.h:148
#define ADI_ADC_COMPARATOR_AIN2_HYS_CYC
#define ADI_ADC_COMPARATOR_AIN3_HYS_VAL
#define ADI_ADC_COMPARATOR_AIN3_HI_VAL
ADI_PWR_RESULT adi_pwr_GetClockFrequency(const ADI_CLOCK_ID eClockId, uint32_t *pClock)
Get the frequency of the given clock. Obtain individual peripheral clock frequencies.
Definition: adi_pwr.c:467
#define ADI_ADC_MEMORY_SIZE
Definition: adi_adc.h:66
ADI_ADC_RESULT adi_adc_IsBufferAvailable(ADI_ADC_HANDLE hDevice, bool *pbIsBufferAvailable)
This function return whether a filled buffer is available to be returned to the user. If this function return true, then a call to adi_adc_GetBuffer will not block.
Definition: adi_adc.c:1419
uint32_t nNumConversionPasses
Definition: adi_adc.h:158
#define ADI_ADC_CHANNEL_1
Definition: adi_adc.h:125
#define ADI_ADC_COMPARATOR_AIN0_HI_VAL
#define ADI_ADC_COMPARATOR_AIN2_HI_VAL
#define ADI_ADC_COMPARATOR_AIN3_LO_VAL
#define ADI_ADC_COMPARATOR_AIN1_HYS_CYC
ADI_ADC_RESULT adi_adc_SetAcquisitionTime(ADI_ADC_HANDLE hDevice, uint32_t nAcqTimeInAClkCycles)
Set the acquisition time of ADC in ADC clock cycles.
Definition: adi_adc.c:753
ADI_ADC_RESULT adi_adc_SetResolution(ADI_ADC_HANDLE hDevice, ADI_ADC_RESOLUTION eResolution)
Set the resolution of ADC. he default resolution of ADC is 12-bit and the ADC increases the resolutio...
Definition: adi_adc.c:843
ADI_ADC_RESULT adi_adc_SubmitBuffer(ADI_ADC_HANDLE hDevice, ADI_ADC_BUFFER *pBuffer)
Submit the ADC buffer for processing to the ADC Module.
Definition: adi_adc.c:1247
ADI_ADC_RESULT adi_adc_Enable(ADI_ADC_HANDLE hDevice, bool bEnable)
Enable/Disable ADC for sampling.
Definition: adi_adc.c:1364
#define ADI_ADC_COMPARATOR_AIN0_HYS_VAL
ADI_ADC_RESULT adi_adc_IsReady(ADI_ADC_HANDLE hDevice, bool *pbReady)
Returns whether the ADC Subsystem is ready.
Definition: adi_adc.c:500
ADI_ADC_RESULT adi_adc_GetTemperature(ADI_ADC_HANDLE hDevice, uint32_t nRefVoltage, int32_t *pnTemperature)
Return the temperature in fixed point format in degree Celcius.
Definition: adi_adc.c:1718
void adi_dma_Init(void)
Initialize the DMA peripheral.
Definition: adi_dma.c:175
uint32_t nChannels
Definition: adi_adc.h:147
struct __ADI_ADC_DEVICE * ADI_ADC_HANDLE
Definition: adi_adc.h:163
ADI_ADC_RESULT adi_adc_RegisterCallback(ADI_ADC_HANDLE hDevice, ADI_CALLBACK pfCallback, void *pCBParam)
Registering a callback function.
Definition: adi_adc.c:389
#define ADI_ADC_COMPARATOR_AIN2_HYS_VAL
ADI_ADC_RESULT adi_adc_EnableDigitalComparator(ADI_ADC_HANDLE hDevice, bool bEnableComparator)
Enable/Disable digital comparator for the given channel(s)
Definition: adi_adc.c:1192
ADI_ADC_RESULT
Definition: adi_adc.h:73
#define ADI_ADC_CHANNEL_2
Definition: adi_adc.h:126
ADI_ADC_RESULT adi_adc_SetVrefSource(ADI_ADC_HANDLE hDevice, ADI_ADC_VREF_SRC eVrefSrc)
Set the Voltage Reference source.
Definition: adi_adc.c:552
ADI_ADC_RESOLUTION
Definition: adi_adc.h:107
ADI_ADC_RESULT adi_adc_StartCalibration(ADI_ADC_HANDLE hDevice)
Start the ADC calibration.
Definition: adi_adc.c:653