ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_tmr_data.c
1 
46 #ifndef ADI_TMR_DATA
47 #define ADI_TMR_DATA
48 
49 
50 #include <stdlib.h>
51 #include <adi_tmr_config.h>
52 #include <drivers/tmr/adi_tmr.h>
53 
54 /* Macro mapping from ADuCM4x50 to ADuCM302x */
55 #if defined(__ADUCM302x__)
56 #define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN
57 #define PWM0CTL PWMCTL
58 #define PWM0MATCH PWMMATCH
59 #define BITM_TMR_RGB_STAT_BUSY BITM_TMR_STAT_BUSY
60 #define BITM_TMR_RGB_CTL_EVTEN BITM_TMR_CTL_EVTEN
61 #define BITM_TMR_RGB_CTL_RSTEN BITM_TMR_CTL_RSTEN
62 #define BITP_TMR_RGB_CTL_RSTEN BITP_TMR_CTL_RSTEN
63 #define BITP_TMR_RGB_CTL_EVTEN BITP_TMR_CTL_EVTEN
64 #define BITP_TMR_RGB_CTL_PRE BITP_TMR_CTL_PRE
65 #define BITP_TMR_RGB_CTL_CLK BITP_TMR_CTL_CLK
66 #define BITP_TMR_RGB_CTL_MODE BITP_TMR_CTL_MODE
67 #define BITP_TMR_RGB_CTL_UP BITP_TMR_CTL_UP
68 #define BITP_TMR_RGB_CTL_RLD BITP_TMR_CTL_RLD
69 #define BITP_TMR_RGB_CTL_SYNCBYP BITP_TMR_CTL_SYNCBYP
70 #define BITP_TMR_RGB_PWM0CTL_IDLESTATE BITP_TMR_PWMCTL_IDLESTATE
71 #define BITP_TMR_RGB_PWM0CTL_MATCH BITP_TMR_PWMCTL_MATCH
72 #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
73 #define BITM_TMR_RGB_STAT_PDOK BITM_TMR_STAT_PDOK
74 #define BITM_TMR_RGB_STAT_TIMEOUT BITM_TMR_STAT_TIMEOUT
75 #define BITM_TMR_RGB_STAT_CAPTURE BITM_TMR_STAT_CAPTURE
76 #define BITM_TMR_RGB_CLRINT_EVTCAPT BITM_TMR_CLRINT_EVTCAPT
77 #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
78 #define BITM_TMR_RGB_CTL_RLD BITM_TMR_CTL_RLD
79 #endif /*__ADUCM302x__*/
80 
81 /* CTL register static configuration */
82 static uint16_t aTimerCtlConfig[] =
83 {
84  (TMR0_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
85  (TMR0_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
86  (TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
87  (TMR0_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
88  (TMR0_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
89  (TMR0_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
90  (TMR0_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
91  (TMR0_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
92 
93  (TMR1_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
94  (TMR1_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
95  (TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
96  (TMR1_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
97  (TMR1_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
98  (TMR1_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
99  (TMR1_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
100  (TMR1_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
101 
102  (TMR2_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
103  (TMR2_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
104  (TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
105  (TMR2_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
106  (TMR2_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
107  (TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
108  (TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
109  (TMR2_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
110 
111 #if defined(__ADUCM4x50__)
112  (TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
113  (TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
114  (TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
115  (TMR3_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
116  (TMR3_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
117  (TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
118  (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
119  (TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
120 #endif
121 };
122 
123 /* LOAD register static configuration */
124 static uint16_t aTimerLoadConfig[] =
125 {
129 #if defined(__ADUCM4x50__)
130  TMR3_CFG_LOAD_VALUE,
131 #endif
132 };
133 
134 /* Asynchronous LOAD static configuraton */
135 static uint16_t aTimerALoadConfig[] =
136 {
140 #if defined(__ADUCM4x50__)
141  TMR3_CFG_ASYNC_LOAD_VALUE,
142 #endif
143 };
144 
145 /* EVENTSELECT static configuration */
146 #if defined(__ADUCM4x50__)
147 static uint16_t aTimerEventConfig[] =
148 {
152  TMR3_CFG_EVENT_CAPTURE,
153 };
154 #endif
155 
156 /* PWM CTL static configuration */
157 static uint16_t aTimerPwmCtlConfig[] =
158 {
159  (TMR0_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
160  (TMR0_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
161 
162  (TMR1_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
163  (TMR1_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
164 
165  (TMR2_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
166  (TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
167 
168 #if defined(__ADUCM4x50__)
169  (TMR3_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
170  (TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
171 
172  (TMR3_CFG_PWM1_IDLE_STATE << BITP_TMR_RGB_PWM1CTL_IDLESTATE) |
173  (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH),
174 
175  (TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) |
176  (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH),
177 #endif
178 };
179 
180 /* PWM MATCH static configuration */
181 static uint16_t aTimerPwmMatchConfig[] = {
185 #if defined(__ADUCM4x50__)
186  TMR3_CFG_PWM0_MATCH_VALUE,
187  TMR3_CFG_PWM1_MATCH_VALUE,
188  TMR3_CFG_PWM2_MATCH_VALUE
189 #endif
190 };
191 
192 
193 #endif /* ADI_TMR_DATA */
#define TMR2_CFG_MODE
#define TMR0_CFG_PWM0_MATCH_VALUE
#define TMR2_CFG_LOAD_VALUE
#define TMR2_CFG_ENABLE_PRESCALE_RESET
#define TMR0_CFG_MODE
#define TMR0_CFG_ENABLE_RELOADING
#define TMR2_CFG_ENABLE_SYNC_BYPASS
#define TMR1_CFG_LOAD_VALUE
#define TMR0_CFG_PWM0_IDLE_STATE
#define TMR1_CFG_PRESCALE_FACTOR
#define TMR2_CFG_COUNT_UP
#define TMR0_CFG_ENABLE_SYNC_BYPASS
#define TMR1_CFG_PWM0_MATCH_VALUE
#define TMR1_CFG_CLOCK_SOURCE
#define TMR1_CFG_ENABLE_RELOADING
#define TMR2_CFG_ENABLE_RELOADING
#define TMR2_CFG_PRESCALE_FACTOR
#define TMR1_CFG_EVENT_CAPTURE
#define TMR0_CFG_CLOCK_SOURCE
#define TMR1_CFG_PWM0_IDLE_STATE
#define TMR1_CFG_ENABLE_SYNC_BYPASS
#define TMR1_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_CLOCK_SOURCE
#define TMR2_CFG_PWM0_MATCH_VALUE
#define TMR1_CFG_ENABLE_EVENT_CAPTURE
#define TMR2_CFG_PWM0_IDLE_STATE
#define TMR1_CFG_COUNT_UP
#define TMR1_CFG_ENABLE_PRESCALE_RESET
#define TMR0_CFG_COUNT_UP
#define TMR0_CFG_LOAD_VALUE
#define TMR0_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_ENABLE_EVENT_CAPTURE
#define TMR0_CFG_ENABLE_EVENT_CAPTURE
#define TMR1_CFG_MODE
#define TMR0_CFG_EVENT_CAPTURE
#define TMR0_CFG_PRESCALE_FACTOR
#define TMR2_CFG_ASYNC_LOAD_VALUE
#define TMR2_CFG_EVENT_CAPTURE
#define TMR0_CFG_ENABLE_PRESCALE_RESET