ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_rtc_data.c
1 
49 #ifndef ADI_RTC_DATA_C_
50 #define ADI_RTC_DATA_C_
51 
52 #include <stdlib.h>
53 #include "adi_rtc_def.h"
54 
55 static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] =
56 {
57  {
58  (ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL
59  },
60  {
61  (ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL,
62  }
63 };
64 
65 
66 static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
67 {
68  /* RTC0 */
69  {
70  /* CR0 */
71  RTC0_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN |
72  RTC0_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN |
73  RTC0_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN |
74  RTC0_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN |
75  RTC0_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN |
76  RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN ,
77  /* CR1 */
78  0,
79  /* CNT0 */
81  /* CNT1 */
83  /* ALM0 */
85  /* ALM1 */
87  /* ALM2 */
88  0,
89  /* TRIM */
90  RTC0_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN |
91  RTC0_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL |
92  RTC0_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD |
93  RTC0_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE,
94  0, /* CR2IC */
95  0, /* CR3SS */
96  0, /* CR4SS */
97  0, /* SSMSK */
98  0, /* SS1 */
99 
100 
101 #if defined(__ADUCM302x__)
102  0, /* SS1ARL (RTC1 only) */
103 #elif defined(__ADUCM4x50__)
104  0, /* SS1LOWDUR (RTC1 only) */
105  0, /* SS1HIGHDUR (RTC1 only) */
106  0, /* SS2LOWDUR (RTC1 only) */
107  0, /* SS2HIGHDUR (RTC1 only) */
108  0, /* SS3LOWDUR (RTC1 only) */
109  0, /* SS3HIGHDUR (RTC1 only) */
110  0, /* CR5SSS (RTC1 only) */
111  0, /* CR6SSS (RTC1 only) */
112  0, /* CR7SSS (RTC1 only) */
113 #endif
114  0, /* GPMUX0 */
115  0 /* GPMUX1 */
116  },
117  /* RTC-1 */
118  {
119  /* CR0 */
120  RTC1_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN |
121  RTC1_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN |
122  RTC1_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN |
123  RTC1_CFG_ENABLE_MOD60_ALARM << BITP_RTC_CR0_MOD60ALMEN |
124  RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD << BITP_RTC_CR0_MOD60ALM |
125  RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT << BITP_RTC_CR0_MOD60ALMINTEN |
126  RTC1_CFG_ENABLE_ISO_INTERRUPT << BITP_RTC_CR0_ISOINTEN |
127  RTC1_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN |
128  RTC1_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN |
129  RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN ,
130  /* CR1 */
131  RTC1_CFG_ENABLE_COUNT_INTERRUPT << BITP_RTC_CR1_CNTINTEN |
132  RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT << BITP_RTC_CR1_PSINTEN |
133  RTC1_CFG_ENABLE_TRIM_INTERRUPT << BITP_RTC_CR1_TRMINTEN |
134  RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTROLLINTEN |
135  RTC1_CFG_PRESCALE << BITP_RTC_CR1_PRESCALE2EXP |
136  RTC1_CFG_CNT_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTMOD60ROLLINTEN ,
137  /* CNT0 */
139  /* CNT1 */
141 
142  /* ALM[123] */
146 
147  /* TRIM */
148  RTC1_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN |
149  RTC1_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL |
150  RTC1_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD |
151  RTC1_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE,
152 
153  /* CR2IC */
154  RTC1_CFG_IC0_ENABLE << BITP_RTC_CR2IC_IC0EN |
155  RTC1_CFG_IC2_ENABLE << BITP_RTC_CR2IC_IC2EN |
156  RTC1_CFG_IC3_ENABLE << BITP_RTC_CR2IC_IC3EN |
157  RTC1_CFG_IC4_ENABLE << BITP_RTC_CR2IC_IC4EN |
158  RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC0IRQEN |
159  RTC1_CFG_IC2_INT_ENABLE << BITP_RTC_CR2IC_IC2IRQEN |
160  RTC1_CFG_IC3_INT_ENABLE << BITP_RTC_CR2IC_IC3IRQEN |
161  RTC1_CFG_IC4_INT_ENABLE << BITP_RTC_CR2IC_IC4IRQEN |
162  RTC1_CFG_IC0_EDGE_POLARITY << BITP_RTC_CR2IC_IC0LH |
163  RTC1_CFG_IC2_EDGE_POLARITY << BITP_RTC_CR2IC_IC2LH |
164  RTC1_CFG_IC3_EDGE_POLARITY << BITP_RTC_CR2IC_IC3LH |
165  RTC1_CFG_IC4_EDGE_POLARITY << BITP_RTC_CR2IC_IC4LH |
166  RTC1_CFG_IC_OVER_WRITE_ENABLE << BITP_RTC_CR2IC_ICOWUSEN,
167 
168 #if defined(__ADUCM4x50__)
169  /* CR3SS */
170  RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN |
171  RTC1_CFG_SS2_ENABLE << BITP_RTC_CR3SS_SS2EN |
172  RTC1_CFG_SS3_ENABLE << BITP_RTC_CR3SS_SS3EN |
173  RTC1_CFG_SS4_ENABLE << BITP_RTC_CR3SS_SS4EN |
174  RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN |
175  RTC1_CFG_SS2_INT_ENABLE << BITP_RTC_CR3SS_SS2IRQEN |
176  RTC1_CFG_SS3_INT_ENABLE << BITP_RTC_CR3SS_SS3IRQEN |
177  RTC1_CFG_SS4_INT_ENABLE << BITP_RTC_CR3SS_SS4IRQEN,
178 
179  /* CR4SS */
180  RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN |
181  RTC1_CFG_SS2_MASK_ENABLE << BITP_RTC_CR4SS_SS2MSKEN |
182  RTC1_CFG_SS3_MASK_ENABLE << BITP_RTC_CR4SS_SS3MSKEN |
183  RTC1_CFG_SS4_MASK_ENABLE << BITP_RTC_CR4SS_SS4MSKEN |
184  RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN |
185  RTC1_CFG_SS2_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS2ARLEN |
186  RTC1_CFG_SS3_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS3ARLEN,
187 #elif defined(__ADUCM302x__)
188  /* CR3SS */
189  RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN |
190  RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN |
191 
192  /* CR4SS */
193  RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN |
194  RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN,
195 #else
196 #error RTC driver not ported to this processor
197 #endif
198  /* SSMSK */
200 
201  /* SS1 */
202 #if defined(__ADUCM302x__)
204 #elif defined(__ADUCM4x50__)
205 #if !defined(RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH) ||!defined(RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW)\
206  ||!defined(RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH)||!defined(RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW)\
207  ||!defined(RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH)||!defined(RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW)
208 #error "update Autoreload register macro in adi_rtc_config.h to the latest version"
209 #else
210  RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH,
211  RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW,
212 
213  RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH,
214  RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW,
215 
216  RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH,
217  RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW ,
218 #endif
219 /* RTC-1 static configuration macros added for 3.2.0 version */
220 #if !defined( RTC1_CFG_CR5SSS_OC1SMPEN )||!defined(RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN )\
221  ||!defined( RTC1_CFG_CR5SSS_OC2SMPEN )||!defined( RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN )\
222  ||!defined(RTC1_CFG_CR5SSS_OC3SMPEN )||!defined( RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN )
223 #error "update CR5SSS register macro in adi_rtc_config.h to the latest version"
224 #else
225  /* CR5SSS */
226  RTC1_CFG_CR5SSS_OC1SMPEN << BITP_RTC_CR5SSS_SS1SMPEN |
227  RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN << BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN |
228  RTC1_CFG_CR5SSS_OC2SMPEN << BITP_RTC_CR5SSS_SS2SMPEN |
229  RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN << BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN |
230  RTC1_CFG_CR5SSS_OC3SMPEN << BITP_RTC_CR5SSS_SS3SMPEN |
231  RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN << BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN,
232 #endif
233 #if !defined(RTC1_CFG_CR6SSS_OC1SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC1SMPONRE )\
234  ||!defined( RTC1_CFG_CR6SSS_OC2SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC2SMPONRE )\
235  ||!defined(RTC1_CFG_CR6SSS_OC3SMPONFE)||!defined(RTC1_CFG_CR6SSS_OC3SMPONRE )
236 #error "update CR6SSS register macro in adi_rtc_config.h to the latest version"
237 #else
238  /* CR6SSS */
239  RTC1_CFG_CR6SSS_OC1SMPONFE << BITP_RTC_CR6SSS_SS1SMPONFE |
240  RTC1_CFG_CR6SSS_OC1SMPONRE << BITP_RTC_CR6SSS_SS1SMPONRE |
241  RTC1_CFG_CR6SSS_OC2SMPONFE << BITP_RTC_CR6SSS_SS2SMPONFE |
242  RTC1_CFG_CR6SSS_OC2SMPONRE << BITP_RTC_CR6SSS_SS2SMPONRE |
243  RTC1_CFG_CR6SSS_OC3SMPONFE << BITP_RTC_CR6SSS_SS3SMPONFE |
244  RTC1_CFG_CR6SSS_OC3SMPONRE << BITP_RTC_CR6SSS_SS3SMPONRE,
245 #endif
246 #if !defined(RTC1_CFG_CR7SSS_OC1SMPEXP )||!defined(RTC1_CFG_CR7SSS_OC1SMPPTRN )\
247  ||!defined( RTC1_CFG_CR7SSS_OC2SMPEXP )||!defined(RTC1_CFG_CR7SSS_OC2SMPPTRN )\
248  ||!defined(RTC1_CFG_CR7SSS_OC3SMPEXP )||!defined( RTC1_CFG_CR7SSS_OC3SMPPTRN )
249 #error "update CR7SSS register macro in adi_rtc_config.h to the latest version"
250 #else
251  /* CR7SSS */
252  RTC1_CFG_CR7SSS_OC1SMPEXP << BITP_RTC_CR7SSS_SS1SMPEXP |
253  RTC1_CFG_CR7SSS_OC1SMPPTRN << BITP_RTC_CR7SSS_SS1SMPPTRN |
254  RTC1_CFG_CR7SSS_OC2SMPEXP << BITP_RTC_CR7SSS_SS2SMPEXP |
255  RTC1_CFG_CR7SSS_OC2SMPPTRN << BITP_RTC_CR7SSS_SS2SMPPTRN |
256  RTC1_CFG_CR7SSS_OC3SMPEXP << BITP_RTC_CR7SSS_SS3SMPEXP |
257  RTC1_CFG_CR7SSS_OC3SMPPTRN << BITP_RTC_CR7SSS_SS3SMPPTRN,
258 #endif
259 #if !defined(RTC1_CFG_GPMUX0_OC1GPIN0SEL)||!defined(RTC1_CFG_GPMUX0_OC1GPIN1SEL )\
260  ||!defined(RTC1_CFG_GPMUX0_OC1GPIN2SEL)||!defined(RTC1_CFG_GPMUX0_OC2GPIN0SEL )\
261  ||!defined(RTC1_CFG_GPMUX0_OC2GPIN1SEL)
262 #error "update GPMUX0 register macro in adi_rtc_config.h to the latest version"
263 #else
264  /* GPMUX0 */
265  RTC1_CFG_GPMUX0_OC1GPIN0SEL << BITP_RTC_GPMUX0_SS1GPIN0SEL |
266  RTC1_CFG_GPMUX0_OC1GPIN1SEL << BITP_RTC_GPMUX0_SS1GPIN1SEL |
267  RTC1_CFG_GPMUX0_OC1GPIN2SEL << BITP_RTC_GPMUX0_SS1GPIN2SEL |
268  RTC1_CFG_GPMUX0_OC2GPIN0SEL << BITP_RTC_GPMUX0_SS2GPIN0SEL |
269  RTC1_CFG_GPMUX0_OC2GPIN1SEL << BITP_RTC_GPMUX0_SS2GPIN1SEL,
270 #endif
271 #if !defined(RTC1_CFG_GPMUX1_OC2GPIN2SEL )||!defined(RTC1_CFG_GPMUX1_OC3GPIN0SEL )\
272  ||!defined(RTC1_CFG_GPMUX1_OC3GPIN1SEL )||!defined(RTC1_CFG_GPMUX1_OC3GPIN2SEL )\
273  ||!defined(RTC1_CFG_GPMUX1_OC1DIFFOUT)||!defined( RTC1_CFG_GPMUX1_OC3DIFFOUT )
274 #error "update GPMUX1 register macro in adi_rtc_config.h to the latest version"
275 #else
276  /* GPMUX1 */
277  RTC1_CFG_GPMUX1_OC2GPIN2SEL << BITP_RTC_GPMUX1_SS2GPIN2SEL |
278  RTC1_CFG_GPMUX1_OC3GPIN0SEL << BITP_RTC_GPMUX1_SS3GPIN0SEL |
279  RTC1_CFG_GPMUX1_OC3GPIN1SEL << BITP_RTC_GPMUX1_SS3GPIN1SEL |
280  RTC1_CFG_GPMUX1_OC3GPIN2SEL << BITP_RTC_GPMUX1_SS3GPIN2SEL |
281  RTC1_CFG_GPMUX1_OC1DIFFOUT << BITP_RTC_GPMUX1_SS1DIFFOUT |
282  RTC1_CFG_GPMUX1_OC3DIFFOUT << BITP_RTC_GPMUX1_SS3DIFFOUT,
283 #endif
284 #endif
285  }
286 
287 };
288 
289 #endif
290 
#define RTC1_CFG_GPMUX0_OC1GPIN2SEL
#define RTC1_CFG_IC4_EDGE_POLARITY
#define RTC1_CFG_SS2_MASK_ENABLE
#define RTC1_CFG_CR5SSS_OC1SMPEN
#define RTC1_CFG_GPMUX0_OC1GPIN0SEL
#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT
#define RTC1_CFG_ENABLE_ALARM
#define RTC1_CFG_ENABLE_ALARM_INTERRUPT
#define RTC1_CFG_SS3_ENABLE
#define RTC1_CFG_ENABLE_TRIM
#define RTC1_CFG_CR7SSS_OC1SMPPTRN
#define RTC0_CFG_ENABLE_ALARM_INTERRUPT
#define RTC1_CFG_IC0_INT_ENABLE
#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD
#define RTC1_CFG_CR7SSS_OC1SMPEXP
#define RTC1_CFG_TRIM_INTERVAL
#define RTC0_CFG_ENABLE_ALARM
#define RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN
#define RTC1_CFG_IC3_ENABLE
#define RTC1_CFG_SS3_MASK_ENABLE
#define RTC1_CFG_GPMUX0_OC2GPIN0SEL
#define RTC1_CFG_CR6SSS_OC3SMPONRE
#define RTC1_CFG_IC4_INT_ENABLE
#define RTC1_CFG_ENABLE_ISO_INTERRUPT
#define RTC0_CFG_TRIM_INTERVAL
#define RTC1_CFG_ALARM_VALUE_1
#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE
#define RTC1_CFG_GPMUX0_OC2GPIN1SEL
#define RTC1_CFG_TRIM_OPERATION
#define RTC1_CFG_GPMUX1_OC3GPIN0SEL
#define RTC1_CFG_ENABLE_MOD60_ALARM
#define RTC1_CFG_CR5SSS_OC3SMPEN
#define RTC1_CFG_SS1_ENABLE
#define RTC1_CFG_SS4_INT_ENABLE
#define RTC0_CFG_ENABLE_TRIM
#define RTC1_CFG_IC0_ENABLE
#define RTC1_CFG_CR5SSS_OC2SMPEN
#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT
#define RTC1_CFG_GPMUX0_OC1GPIN1SEL
#define RTC1_CFG_ALARM_VALUE_2
#define RTC1_CFG_IC2_ENABLE
#define RTC1_CFG_IC3_INT_ENABLE
#define RTC1_CFG_ENABLE_COUNT_INTERRUPT
#define RTC0_CFG_TRIM_OPERATION
#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT
#define RTC1_CFG_SS4_MASK_ENABLE
#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT
#define RTC1_CFG_CR7SSS_OC2SMPPTRN
#define RTC1_CFG_COUNT_VALUE_0
#define RTC1_CFG_SS1_MASK_ENABLE
#define RTC1_CFG_CR6SSS_OC3SMPONFE
#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT
#define RTC1_CFG_GPMUX1_OC3GPIN2SEL
#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT
#define RTC1_CFG_ALARM_VALUE_0
#define RTC0_CFG_COUNT_VALUE_0
#define RTC1_CFG_CR6SSS_OC2SMPONFE
#define RTC1_CFG_SS2_ENABLE
#define RTC0_CFG_ALARM_VALUE_1
#define RTC1_CFG_SS4_ENABLE
#define RTC1_CFG_IC2_INT_ENABLE
#define RTC1_CFG_IC3_EDGE_POLARITY
#define RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN
#define RTC1_CFG_POW2_TRIM_INTERVAL
#define RTC0_CFG_ALARM_VALUE_0
#define RTC1_CFG_IC0_EDGE_POLARITY
#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE
#define RTC1_CFG_CR7SSS_OC3SMPEXP
#define RTC1_CFG_TRIM_VALUE
#define RTC1_CFG_GPMUX1_OC3GPIN1SEL
#define RTC1_CFG_IC_OVER_WRITE_ENABLE
#define RTC1_CFG_SS2_INT_ENABLE
#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT
#define RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN
#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT
#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT
#define RTC0_CFG_COUNT_VALUE_1
#define RTC1_CFG_PRESCALE
#define RTC1_CFG_COUNT_VALUE_1
#define RTC1_CFG_CR7SSS_OC3SMPPTRN
#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT
#define RTC1_CFG_GPMUX1_OC2GPIN2SEL
#define RTC0_CFG_TRIM_VALUE
#define RTC1_CFG_CR7SSS_OC2SMPEXP
#define RTC1_CFG_IC2_EDGE_POLARITY
#define RTC1_CFG_ENABLE_TRIM_INTERRUPT
#define RTC0_CFG_POW2_TRIM_INTERVAL
#define RTC1_CFG_CR6SSS_OC2SMPONRE
#define RTC1_CFG_IC4_ENABLE
#define RTC1_CFG_SS3_INT_ENABLE
#define RTC1_CFG_SS1_INT_ENABLE
#define RTC1_CFG_GPMUX1_OC1DIFFOUT
#define RTC1_CFG_SS1_MASK_VALUE
#define RTC1_CFG_GPMUX1_OC3DIFFOUT
#define RTC1_CFG_CR6SSS_OC1SMPONFE
#define RTC1_CFG_CR6SSS_OC1SMPONRE