ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_rtc.c
1 
58 #if defined(__ADUCM302x__)
59 #define BITP_CLKG_OSC_CTL_LFX_FAIL_STA BITP_CLKG_OSC_CTL_LFX_FAIL_STAT
60 #endif /* __ADUCM302x__ */
61 
62 #if defined ( __ADSPGCC__ )
63 #define UNUSED __attribute__ ((unused))
64 #else
65 #define UNUSED
66 #endif
67 
68 #include <stdlib.h> /* for 'NULL" definition */
69 #include <assert.h>
70 #include <string.h>
71 #include <rtos_map/adi_rtos_map.h>
72 
73 
74 
75 #ifdef __ICCARM__
76 /*
77 * IAR MISRA C 2004 error suppressions.
78 *
79 * Pm011 (rule 6.3): Types which specify sign and size should be used
80 * We use bool which is accepted by MISRA but the toolchain does not accept it
81 *
82 * Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
83 * This isn't a header as such.
84 *
85 * Pm073 (rule 14.7): a function should have a single point of exit
86 * Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
87 * Multiple returns are used for error handling.
88 *
89 * Pm050 (rule 14.2): a null statement shall only occur on a line by itself
90 * Needed for null expansion of ADI_INSTALL_HANDLER and others.
91 *
92 * Pm109 (rule 20.12): the time handling functions of library <time.h> shall not be used
93 * Pm150 (rule 20.2): the names of standard library macros, objects and function shall not be reused
94 * Needed to implement the <time.h> functions here.
95 *
96 * Pm129 (rule 12.7): bitwise operations shall not be performed on signed integer types
97 * The rule makes an exception for valid expressions.
98 *
99 * Pm029: this bitwise operation is in a boolean context - logical operators should not be confused with bitwise operators
100 * The rule is suppressed as the bitwise and logical operators are being used correctly and are not being confused
101 *
102 * Pm126: if the bitwise operators ~ and << are applied to an operand of underlying type 'unsigned char' or 'unsigned short', the result shall be immediately cast to the underlying type of the operand
103 * The behaviour as described is correct
104 *
105 * Pm031: bitwise operations shall not be performed on signed integer types
106 * Device drivers often require bit banging on MMRs that are defined as signed
107 
108 */
109 #pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm050,Pm109,Pm150,Pm140,Pm129,Pm029,Pm126,Pm031
110 #endif /* __ICCARM__ */
111 
114 #include <drivers/rtc/adi_rtc.h>
115 
116 
122 #if defined(_RTE_)
123 
128 #include <RTE_Components.h>
129 
130 #endif
131 
132 #include "adi_rtc_data.c"
133 
134 #define RTC_SNAPSHOT_KEY (0x7627u)
135 #define RTC_FRZCNT_KEY (0x9376u)
136 
137 /* Data structure to manage snapshots */
138 struct adi_rtc_snapshots
139 {
140  uint16_t snapshot0; /* snap shot for register COUNT0 */
141  uint16_t snapshot1; /* snap shot for register COUNT1 */
142  uint16_t snapshot2; /* snap shot for register COUNT2 */
143 };
144 
145 #if defined(__ADUCM302x__)
146 #define BITP_RTC_SSMSK_SS1MSK BITP_RTC_SSMSK_SSMSK
147 #endif /* __ADUCM302x__ */
148 
149 #if defined(__ADUCM4x50__)
150 
154 #ifndef ADUCM4050_SI_REV
155 #define ADUCM4050_SI_REV (1)
156 #endif
157 
161 #ifndef WA_21000023
162 #define WA_21000023 (1)
163 #endif
164 
165 /* Data structures used to manage the enabling of all RTC interrupts */
166 static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u, cr5ocs = 0u;
167 
168 struct xxx
169 {
170  uint16_t *cr;
171  uint16_t bitPositionl;
172 }
173 
174 Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] =
175 {
176  { &cr0, BITP_RTC_CR0_ALMINTEN },
177  { &cr0, BITP_RTC_CR0_MOD60ALMINTEN },
178  { &cr0, BITP_RTC_CR0_ISOINTEN },
179  { &cr0, BITP_RTC_CR0_WPNDERRINTEN },
180  { &cr0, BITP_RTC_CR0_WSYNCINTEN },
181  { &cr0, BITP_RTC_CR0_WPNDINTEN },
182  { &cr1, BITP_RTC_CR1_CNTINTEN },
183  { &cr1, BITP_RTC_CR1_PSINTEN },
184  { &cr1, BITP_RTC_CR1_TRMINTEN },
185  { &cr1, BITP_RTC_CR1_CNTROLLINTEN },
186  { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN },
187  { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN },
188  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
189  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
190  { &cr3oc, BITP_RTC_CR3SS_SS4IRQEN },
191  { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN },
192  { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN },
193  { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN },
194  { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN },
195  { &cr2ic, BITP_CLKG_OSC_CTL_LFX_FAIL_STA },
196  { &cr3oc, BITM_RTC_CR3SS_SS4FEIRQEN},
197  { &cr3oc, BITM_RTC_CR3SS_SS3FEIRQEN},
198  { &cr3oc, BITM_RTC_CR3SS_SS2FEIRQEN},
199  { &cr3oc, BITM_RTC_CR3SS_SS1FEIRQEN},
200  { &cr4oc, BITP_RTC_CR4SS_SS4MSKEN},
201  { &cr4oc, BITP_RTC_CR4SS_SS3MSKEN},
202  { &cr4oc, BITP_RTC_CR4SS_SS2MSKEN},
203  { &cr4oc, BITP_RTC_CR4SS_SS1MSKEN},
204  { &cr5ocs, BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN},
205  { &cr5ocs, BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN},
206  { &cr5ocs, BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN}
207 
208 };
209 
210 #elif defined(__ADUCM302x__)
211 
212 /* Data structures used to manage the enabling of all RTC interrupts */
213 static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u;
214 
215 struct xxx
216 {
217  uint16_t *cr;
218  uint16_t bitPositionl;
219 }
220 
221 Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] =
222 {
223  { &cr0, BITP_RTC_CR0_ALMINTEN },
224  { &cr0, BITP_RTC_CR0_MOD60ALMINTEN },
225  { &cr0, BITP_RTC_CR0_ISOINTEN },
226  { &cr0, BITP_RTC_CR0_WPNDERRINTEN },
227  { &cr0, BITP_RTC_CR0_WSYNCINTEN },
228  { &cr0, BITP_RTC_CR0_WPNDINTEN },
229  { &cr1, BITP_RTC_CR1_CNTINTEN },
230  { &cr1, BITP_RTC_CR1_PSINTEN },
231  { &cr1, BITP_RTC_CR1_TRMINTEN },
232  { &cr1, BITP_RTC_CR1_CNTROLLINTEN },
233  { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN },
234  { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN },
235  { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN },
236  { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN },
237  { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN },
238  { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN },
239 };
240 #else
241 #error RTC is not ported for this processor
242 #endif
243 
244 
245 /* Forward prototypes */
246 void RTC0_Int_Handler(void);
247 void RTC1_Int_Handler(void);
248 static ADI_RTC_RESULT adi_rtc_GetCoherentCounterValues(ADI_RTC_HANDLE const hDevice, struct adi_rtc_snapshots *pSnapshots);
249 
250 
251 
252 #ifdef ADI_DEBUG
253 static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice)
254 {
255  /* Return code */
257  uint32_t i;
258  for(i = 0u; i < ADI_RTC_NUM_INSTANCE; i++)
259  {
260  if(aRTCDeviceInfo[i].hDevice == pInDevice)
261  {
262  return(ADI_RTC_SUCCESS);
263  }
264  }
265  return (nResult);
266 }
267 #endif
268 
302  uint32_t DeviceNumber,
303  void *pDeviceMemory,
304  uint32_t MemorySize,
305  ADI_RTC_HANDLE *phDevice
306  )
307 {
308  ADI_RTC_DEVICE *pDevice = pDeviceMemory;
309 
310  /* store a bad handle in case of failure */
311  *phDevice = (ADI_RTC_HANDLE) NULL;
312 
313 #ifdef ADI_DEBUG
314  if ( DeviceNumber >= ADI_RTC_NUM_INSTANCE)
315  {
316  return (ADI_RTC_INVALID_INSTANCE);
317  }
318  assert(ADI_RTC_MEMORY_SIZE == sizeof(ADI_RTC_DEVICE));
319  if (aRTCDeviceInfo[DeviceNumber].hDevice != NULL)
320  {
321  return (ADI_RTC_IN_USE);
322  }
323  if(MemorySize < ADI_RTC_MEMORY_SIZE)
324  {
325  return(ADI_RTC_FAILURE);
326  }
327 #endif
328 
329  /* clear the memory used to store RTC instance data */
330  memset(pDeviceMemory,0,MemorySize);
331  /* initialize device data entries */
332  pDevice->pRTCRegs = aRTCDeviceInfo[DeviceNumber].pRTCRegs;
333 
334  /* Disable all mainstream RTC operations:
335  * - wait for CR0 to be writable
336  * - clear CR0 to disable all the operations
337  * - wait for CR1 to be writable
338  * - clear CR1 to disable all the operations
339  * - Wait till writes to Control Registers CR0 and CR1 take effect
340  */
341  ALWAYS_PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
342  pDevice->pRTCRegs->CR0 = 0u;
343  ALWAYS_PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
344  pDevice->pRTCRegs->CR1 = 0u;
345  ALWAYS_SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
346  ALWAYS_SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)
347 
348  /* Clear every interrupt bit in SR0:
349  * - Wait for SR0 to be writable
350  * - Write every interrupt bit in SR0 (Write-One-To-Clear)
351  * - Wait till write to SR0 takes effect
352  */
353  ALWAYS_PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0)
354  pDevice->pRTCRegs->SR0 = ADI_RTC_IRQ_SOURCE_MASK_SR0;
355  ALWAYS_SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0)
356 
357  /* Clear every interrupt bit in CNT0 and CNT1:
358  * - Wait for CNT0 to be writable
359  * - Clear every interrupt bit in CNT0
360  * - Wait for CNT1 to be writable
361  * - Clear every interrupt bit in CNT1
362  * - Wait till writes to CNT0 and CNT1 take effect
363  */
364  ALWAYS_PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
365  pDevice->pRTCRegs->CNT0 = 0u;
366  pDevice->pRTCRegs->CNT1 = 0u;
367  ALWAYS_SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1))
368 
369  /* local pointer to instance data */
370  aRTCDeviceInfo[DeviceNumber].hDevice = pDevice;
371  pDevice->pDeviceInfo = &aRTCDeviceInfo[DeviceNumber];
372 
373  /* Use static configuration to initialize the RTC */
374  rtc_init(pDevice,&aRTCConfig[DeviceNumber]);
375 
376  /* store handle at application handle pointer */
377  *phDevice = pDevice;
378  pDevice->eIRQn = aRTCDeviceInfo[DeviceNumber].eIRQn;
379  /* Enable RTC interrupts in NVIC */
380  NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
381 
382  return ADI_RTC_SUCCESS; /* initialized */
383 }
384 
385 
400 {
401  ADI_RTC_DEVICE *pDevice = hDevice;
402 
403 #ifdef ADI_DEBUG
404  ADI_RTC_RESULT eResult;
405  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
406  {
407  return eResult;
408  }
409 #endif
410 
411  /* uninitialize */
412  NVIC_DisableIRQ( pDevice->eIRQn);
413 
414  pDevice->pRTCRegs = NULL;
415  pDevice->pfCallback = NULL;
416  pDevice->pCBParam = NULL;
417  pDevice->cbWatch = 0u;
418 
419  pDevice->pDeviceInfo->hDevice = NULL;
420  return ADI_RTC_SUCCESS;
421 }
422 
423 
424 /*************************************************************************************************
425 **************************************************************************************************
426 **************************************** ENABLE APIS *******************************************
427 **************************************************************************************************
428 *************************************************************************************************/
429 
430 
462 {
463  ADI_RTC_DEVICE *pDevice = hDevice;
464 #ifdef ADI_DEBUG
465  ADI_RTC_RESULT eResult;
466  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
467  {
468  return eResult;
469  }
470 #endif
471 
472  /* Wait till previously posted write to Control Register to complete */
473  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
474 
475  ADI_INT_STATUS_ALLOC();
476  ADI_ENTER_CRITICAL_REGION();
477  /* set/clear RTC alarm enable */
478  if (bEnable)
479  {
480  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_ALMEN;
481  }
482  else
483  {
484  pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_ALMEN);
485  }
486  ADI_EXIT_CRITICAL_REGION();
487 
488  /* Wait till write to Control Register to take effect */
489  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
490 
491  return ADI_RTC_SUCCESS;
492 }
493 
525 {
526  ADI_RTC_DEVICE *pDevice = hDevice;
527 #ifdef ADI_DEBUG
528  ADI_RTC_RESULT eResult;
529  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
530  {
531  return eResult;
532  }
533  /* Mod-60 Alarm is present only in RTC-1 */
534  if(pDevice->pRTCRegs == pADI_RTC0)
535  {
537  }
538 
539 #endif
540 
541  /* Wait till previously posted write to Control Register to complete */
542  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
543 
544  ADI_INT_STATUS_ALLOC();
545  ADI_ENTER_CRITICAL_REGION();
546  /* set/clear RTC alarm enable */
547  if (bEnable)
548  {
549  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_MOD60ALMEN;
550  }
551  else
552  {
553  pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_MOD60ALMEN);
554  }
555  ADI_EXIT_CRITICAL_REGION();
556 
557  /* Wait till write to Control Register to take effect */
558  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
559 
560  return ADI_RTC_SUCCESS;
561 }
562 
586 ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable)
587 {
588  ADI_RTC_DEVICE *pDevice = hDevice;
589 
590 #ifdef ADI_DEBUG
591  ADI_RTC_RESULT eResult;
592  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
593  {
594  return eResult;
595  }
596 #endif
597 
598  /* Wait till previously posted write to Control Register to complete */
599  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
600 
601 
602  ADI_INT_STATUS_ALLOC();
603  ADI_ENTER_CRITICAL_REGION();
604  /* set/clear RTC device enable */
605  if (bEnable)
606  {
607  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_CNTEN;
608  }
609  else
610  {
611  pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_CNTEN);
612  }
613  ADI_EXIT_CRITICAL_REGION();
614 
615  /* Wait till write to Control Register to take effect */
616  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
617 
618  return ADI_RTC_SUCCESS;
619 }
620 
621 
647 {
648  ADI_RTC_DEVICE *pDevice = hDevice;
649 
650 #ifdef ADI_DEBUG
651  ADI_RTC_RESULT eResult;
652  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
653  {
654  return eResult;
655  }
656  if( (pDevice->pRTCRegs == pADI_RTC0) &&(((uint16_t)((ADI_RTC_MOD60ALM_INT | ADI_RTC_ISO_DONE_INT|
660  )) & (uint16_t)Interrupts) != 0u))
661  {
662  return(ADI_RTC_INVALID_PARAM);
663  }
664 
665  assert(sizeof(Interrupt_Details)/sizeof(Interrupt_Details[0]) == ADI_RTC_NUM_INTERRUPTS);
666 #endif
667 
668  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
669  PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
670 
671  uint8_t ndx = 0u;
672  cr0 = 0u; cr1 = 0u; cr3oc = 0u; cr4oc = 0u; cr2ic = 0u;
673 
674 #if defined(__ADUCM4x50__)
675  cr5ocs = 0u;
676 #endif /* __ADUCM4x50__ */
677 
678  while( Interrupts )
679  {
680  if( 0u != (Interrupts & 1u) )
681  {
682  uint16_t *cr = Interrupt_Details[ndx].cr;
683  uint16_t enableBitPosition = Interrupt_Details[ndx].bitPositionl;
684  *cr = *cr | (1u << enableBitPosition);
685  }
686  Interrupts >>= 1;
687  ndx++;
688  }
689  /* set/clear interrupt enable bit(s) in control register */
690  if (bEnable)
691  {
692  pDevice->pRTCRegs->CR0 |= cr0;
693  pDevice->pRTCRegs->CR1 |= cr1;
694  pDevice->pRTCRegs->CR3SS |= cr3oc;
695  pDevice->pRTCRegs->CR4SS |= cr4oc;
696  pDevice->pRTCRegs->CR2IC |= cr2ic;
697 
698 #if defined(__ADUCM4x50__)
699  pDevice->pRTCRegs->CR5SSS |= cr5ocs;
700 #endif /* __ADUCM4x50__ */
701  }
702  else
703  {
704  pDevice->pRTCRegs->CR0 &= ~cr0;
705  pDevice->pRTCRegs->CR1 &= ~cr1;
706  pDevice->pRTCRegs->CR3SS &= ~cr3oc;
707  pDevice->pRTCRegs->CR4SS &= ~cr4oc;
708  pDevice->pRTCRegs->CR2IC &= ~cr2ic;
709 #if defined(__ADUCM4x50__)
710  pDevice->pRTCRegs->CR5SSS &= ~cr5ocs;
711 #endif /* __ADUCM4x50__ */
712  }
713  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
714  SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)
715  return ADI_RTC_SUCCESS;
716 }
717 
718 
745 ADI_RTC_RESULT adi_rtc_EnableTrim (ADI_RTC_HANDLE const hDevice, bool bEnable)
746 {
747  ADI_RTC_DEVICE *pDevice = hDevice;
748 
749 #ifdef ADI_DEBUG
750  ADI_RTC_RESULT eResult;
751  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
752  {
753  return eResult;
754  }
755 #endif
756  /* Wait till previously posted write to Control Register to complete */
757  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
758 
759  ADI_INT_STATUS_ALLOC();
760  ADI_ENTER_CRITICAL_REGION();
761  /* set/clear trim enable bit(s) in control register */
762  if (bEnable)
763  {
764  pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_TRMEN;
765  }
766  else
767  {
768  pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_TRMEN);
769  }
770  ADI_EXIT_CRITICAL_REGION();
771 
772  /* Wait till write to Control Register to take effect */
773  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
774 
775  return ADI_RTC_SUCCESS;
776 }
792 {
793  ADI_RTC_DEVICE *pDevice = hDevice;
794 
795 #ifdef ADI_DEBUG
796  ADI_RTC_RESULT eResult;
797  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
798  {
799  return eResult;
800  }
801 #endif
802  /* Wait till previously posted write to Control Register to complete */
803  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
804 
805  ADI_INT_STATUS_ALLOC();
806  ADI_ENTER_CRITICAL_REGION();
807  /* set/clear trim input capture enable for specified channel*/
808  if (bEnable)
809  {
810  pDevice->pRTCRegs->CR2IC |=(uint16_t)eInpChannel;
811  }
812  else
813  {
814  pDevice->pRTCRegs->CR2IC &= (uint16_t)(~(uint16_t)eInpChannel);
815  }
816  ADI_EXIT_CRITICAL_REGION();
817 
818  /* Wait till write to Control Register to take effect */
819  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)
820 
821  return ADI_RTC_SUCCESS;
822 }
823 
838 {
839  ADI_RTC_DEVICE *pDevice = hDevice;
840 
841 #ifdef ADI_DEBUG
842  ADI_RTC_RESULT eResult;
843  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
844  {
845  return eResult;
846  }
847 #endif
848  /* Wait till previously posted write to Control Register to complete */
849  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
850 
851  ADI_INT_STATUS_ALLOC();
852  ADI_ENTER_CRITICAL_REGION();
853  /* set/clear trim input capture enable for specified channel*/
854  if (bEnable)
855  {
856  pDevice->pRTCRegs->CR2IC |= BITM_RTC_CR2IC_ICOWUSEN;
857  }
858  else
859  {
860  pDevice->pRTCRegs->CR2IC &= (uint16_t)~BITM_RTC_CR2IC_ICOWUSEN;
861  }
862  ADI_EXIT_CRITICAL_REGION();
863 
864  /* Wait till write to Control Register to take effect */
865  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)
866 
867  return ADI_RTC_SUCCESS;
868 }
869 
885 {
886  ADI_RTC_DEVICE *pDevice = hDevice;
887  uint32_t nInpChannel = (uint16_t)eInpChannel;
888 
889 #ifdef ADI_DEBUG
890  ADI_RTC_RESULT eResult;
891  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
892  {
893  return eResult;
894  }
895 #endif
896  /* Wait till previously posted write to Control Register to complete */
897  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
898 
899  ADI_INT_STATUS_ALLOC();
900  ADI_ENTER_CRITICAL_REGION();
901  /* set/clear trim input capture enable for specified channel*/
902  if (bEnable)
903  {
904  pDevice->pRTCRegs->CR2IC |= (uint16_t)(nInpChannel << BITP_RTC_CR2IC_IC0LH);
905  }
906  else
907  {
908  pDevice->pRTCRegs->CR2IC &= (uint16_t)~(nInpChannel << BITP_RTC_CR2IC_IC0LH);
909  }
910  ADI_EXIT_CRITICAL_REGION();
911 
912  /* Wait till write to Control Register to take effect */
913  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)
914 
915  return ADI_RTC_SUCCESS;
916 }
932 {
933  ADI_RTC_DEVICE *pDevice = hDevice;
934 
935 #ifdef ADI_DEBUG
936  ADI_RTC_RESULT eResult;
937  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
938  {
939  return eResult;
940  }
941 #endif
942  /* Wait till previously posted write to Control Register to complete */
943  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR3SS)
944 
945  ADI_INT_STATUS_ALLOC();
946  ADI_ENTER_CRITICAL_REGION();
947  /* set/clear Sensor Strobe enable for specified channel*/
948  if (bEnable)
949  {
950  pDevice->pRTCRegs->CR3SS |=(uint16_t)eSSChannel;
951  }
952  else
953  {
954  pDevice->pRTCRegs->CR3SS &= (uint16_t)(~(uint16_t)eSSChannel);
955  }
956  ADI_EXIT_CRITICAL_REGION();
957 
958  /* Wait till write to Control Register to take effect */
959  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR3SS)
960 
961  return ADI_RTC_SUCCESS;
962 }
963 
979 {
980  ADI_RTC_DEVICE *pDevice = hDevice;
981 
982 #ifdef ADI_DEBUG
983  ADI_RTC_RESULT eResult;
984  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
985  {
986  return eResult;
987  }
988 #endif
989  /* Wait till previously posted write to Control Register to complete */
990  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR4SS)
991 
992  ADI_INT_STATUS_ALLOC();
993  ADI_ENTER_CRITICAL_REGION();
994  /* set/clear auto reload enable options */
995  /* Note that channel 4 does not have this feature */
996  if (bEnable)
997  {
998  switch( eSSChannel)
999  {
1000  case ADI_RTC_SS_CHANNEL_1:
1001  pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS1ARLEN;
1002  break;
1003 #if defined(__ADUCM4x50__)
1004  case ADI_RTC_SS_CHANNEL_2:
1005  pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS2ARLEN;
1006  break;
1007  case ADI_RTC_SS_CHANNEL_3:
1008  pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS3ARLEN;
1009  break;
1010 #endif /* __ADUCM4x50__ */
1011  default:
1012  return ADI_RTC_FAILURE;
1013  }
1014 
1015  }
1016  else
1017  {
1018  switch( eSSChannel)
1019  {
1020  case ADI_RTC_SS_CHANNEL_1:
1021  pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS1ARLEN;
1022  break;
1023 #if defined(__ADUCM4x50__)
1024  case ADI_RTC_SS_CHANNEL_2:
1025  pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS2ARLEN;
1026  break;
1027  case ADI_RTC_SS_CHANNEL_3:
1028  pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS3ARLEN;
1029  break;
1030 #endif /* __ADUCM4x50__ */
1031  default:
1032  return ADI_RTC_FAILURE;
1033  }
1034  }
1035  ADI_EXIT_CRITICAL_REGION();
1036 
1037  /* Wait till write to Control Register to take effect */
1038  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)
1039 
1040  return ADI_RTC_SUCCESS;
1041 }
1042 #if defined(__ADUCM302x__)
1043 
1058  ADI_RTC_SS_CHANNEL eSSChannel,
1059  uint16_t nValue)
1060 #elif defined(__ADUCM4x50__)
1061 
1077  ADI_RTC_SS_CHANNEL eSSChannel,
1078  uint16_t nLowValue,
1079  uint16_t nHighValue)
1080 #endif
1081 {
1082  ADI_RTC_DEVICE *pDevice = hDevice;
1083 
1084 #ifdef ADI_DEBUG
1085  ADI_RTC_RESULT eResult;
1086  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1087  {
1088  return eResult;
1089  }
1090 #endif
1091 
1092  switch( eSSChannel )
1093  {
1094  case ADI_RTC_SS_CHANNEL_1:
1095  /* Wait till previously posted write to Control Register to complete */
1096  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
1097 #if defined(__ADUCM4x50__)
1098  pDevice->pRTCRegs->SS1LOWDUR = nLowValue;
1099  pDevice->pRTCRegs->SS1HIGHDUR= nHighValue;
1100 #else
1101  pDevice->pRTCRegs->SS1ARL = nValue;
1102 #endif
1103  /* Wait till write to Control Register to take effect */
1104  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)
1105  break;
1106 #if defined(__ADUCM4x50__)
1107  case ADI_RTC_SS_CHANNEL_2:
1108  /* Wait till previously posted write to Control Register to complete */
1109  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
1110  pDevice->pRTCRegs->SS2LOWDUR = nLowValue;
1111  pDevice->pRTCRegs->SS2HIGHDUR= nHighValue;
1112  /* Wait till write to Control Register to take effect */
1113  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)
1114  break;
1115 
1116  case ADI_RTC_SS_CHANNEL_3:
1117  /* Wait till previously posted write to Control Register to complete */
1118  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
1119  pDevice->pRTCRegs->SS3LOWDUR = nLowValue;
1120  pDevice->pRTCRegs->SS3HIGHDUR= nHighValue;
1121  /* Wait till write to Control Register to take effect */
1122  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)
1123  break;
1124 
1125 #endif /* __ADUCM4x50__ */
1126 
1127  default:
1128  return ADI_RTC_FAILURE;
1129 
1130  }
1131 
1132  return ADI_RTC_SUCCESS;
1133 }
1149 {
1150  ADI_RTC_DEVICE *pDevice = hDevice;
1151 
1152 #ifdef ADI_DEBUG
1153  ADI_RTC_RESULT eResult;
1154  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1155  {
1156  return eResult;
1157  }
1158 #endif
1159  /* Wait till previously posted write to Control Register to complete */
1160  PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDCR4SS)
1161 
1162  ADI_INT_STATUS_ALLOC();
1163  ADI_ENTER_CRITICAL_REGION();
1164  /* set/clear auto reload enable options */
1165  if (bEnable)
1166  {
1167  pDevice->pRTCRegs->CR4SS |= (uint16_t)eSSChannel;
1168  }
1169  else
1170  {
1171  pDevice->pRTCRegs->CR4SS &= (uint16_t)~(uint16_t)eSSChannel;
1172  }
1173  ADI_EXIT_CRITICAL_REGION();
1174 
1175  /* Wait till write to Control Register to take effect */
1176  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)
1177 
1178  return ADI_RTC_SUCCESS;
1179 }
1180 
1194 {
1195  ADI_RTC_DEVICE *pDevice = hDevice;
1196  uint16_t MaskPos = 0u;
1197 
1198 #ifdef ADI_DEBUG
1199  ADI_RTC_RESULT eResult;
1200  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1201  {
1202  return eResult;
1203  }
1204 #endif
1205 
1206  switch( eSSChannel )
1207  {
1208  case ADI_RTC_SS_CHANNEL_1:
1209  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS1MSK;
1210  break;
1211 #if defined(__ADUCM4x50__)
1212  case ADI_RTC_SS_CHANNEL_2:
1213  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS2MSK;
1214  break;
1215 
1216  case ADI_RTC_SS_CHANNEL_3:
1217  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS3MSK;
1218  break;
1219 
1220  case ADI_RTC_SS_CHANNEL_4:
1221  MaskPos = (uint16_t)BITP_RTC_SSMSK_SS4MSK;
1222  break;
1223 #endif /* __ADUCM4x50__ */
1224  default:
1225  return ADI_RTC_INVALID_CHANNEL;
1226  }
1227 
1228  /* Wait till previously posted write to Control Register to complete */
1229  PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDSSMSK)
1230 
1231  /*Set mask setting for sensor strobe channel*/
1232  pDevice->pRTCRegs->SSMSK |= ((uint16_t)nMask & 0xFu) << MaskPos;
1233 
1234  /* Wait till write to Control Register to take effect */
1235  SYNC_AFTER_WRITE(SR4, BITM_RTC_SR4_WSYNCSSMSK)
1236 
1237  return ADI_RTC_SUCCESS;
1238 }
1239 
1240 /*************************************************************************************************
1241 **************************************************************************************************
1242 ****************************************** GET APIS ******************************************
1243 **************************************************************************************************
1244 *************************************************************************************************/
1245 
1246 
1264 {
1265  ADI_RTC_DEVICE *pDevice = hDevice;
1266  uint32_t nAlarm;
1267 #ifdef ADI_DEBUG
1268  ADI_RTC_RESULT eResult;
1269  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1270  {
1271  return eResult;
1272  }
1273 #endif
1274 
1275  /* Wait till previously posted write to Control Register to complete */
1276  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
1277 
1278  /* disable interrupts during paired read */
1279  NVIC_DisableIRQ(pDevice->eIRQn);
1280  nAlarm =(uint32_t) pDevice->pRTCRegs->ALM1 << 16u;
1281  nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
1282  NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
1283 
1284  *pAlarm = nAlarm;
1285 
1286  return ADI_RTC_SUCCESS;
1287 }
1305 {
1306  ADI_RTC_DEVICE *pDevice = hDevice;
1307  uint32_t nAlarm,nTemp;
1308  uint16_t nPreScale;
1309  float fFraction;
1310 #ifdef ADI_DEBUG
1311  ADI_RTC_RESULT eResult;
1312  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1313  {
1314  return eResult;
1315  }
1316 #endif
1317 
1318  /* Wait till previously posted write to Control Register to complete */
1319  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
1320  nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
1321  /* disable interrupts during paired read */
1322  NVIC_DisableIRQ(pDevice->eIRQn);
1323  nAlarm = (uint32_t)pDevice->pRTCRegs->ALM1 << 16u;
1324  nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
1325  NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
1326  nTemp = 1lu<<nPreScale;
1327  fFraction = (float)pDevice->pRTCRegs->ALM2 /(float)(nTemp);
1328 
1329  *pAlarm = (float)nAlarm+fFraction;
1330 
1331  return ADI_RTC_SUCCESS;
1332 }
1333 
1334 
1352 ADI_RTC_RESULT adi_rtc_GetAlarmRegs(ADI_RTC_HANDLE hDevice, uint16_t *pAlarm0,uint16_t *pAlarm1,uint16_t *pAlarm2)
1353 {
1354  ADI_RTC_DEVICE *pDevice = hDevice;
1356 
1357 #ifdef ADI_DEBUG
1358  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1359  {
1360  return eResult;
1361  }
1362 #endif
1363 
1364  /* Wait till previously posted write to Control Register to complete */
1365  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
1366 
1367  /* disable interrupts during paired read */
1368  NVIC_DisableIRQ(pDevice->eIRQn);
1369  *pAlarm0= pDevice->pRTCRegs->ALM0;
1370  *pAlarm1= pDevice->pRTCRegs->ALM1;
1371  *pAlarm2= pDevice->pRTCRegs->ALM2;
1372  NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
1373 
1374  return eResult;
1375 }
1376 
1377 
1397 {
1398  ADI_RTC_DEVICE *pDevice = hDevice;
1399 
1400 #ifdef ADI_DEBUG
1401  ADI_RTC_RESULT eResult;
1402  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1403  {
1404  return eResult;
1405  }
1406 #endif
1407  /* Wait till previously posted write to Control Register to complete */
1408  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
1409 
1410  switch(eRegister)
1411  {
1413  *pControl = pDevice->pRTCRegs->CR0;
1414  break;
1416  *pControl = pDevice->pRTCRegs->CR1;
1417  break;
1418  default:
1419  return(ADI_RTC_FAILURE);
1420  }
1421  return ADI_RTC_SUCCESS;
1422 }
1423 
1424 
1444 ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount)
1445 {
1446  struct adi_rtc_snapshots snapshots;
1447  ADI_RTC_RESULT eResult;
1448 
1449 #ifdef ADI_DEBUG
1450  if((eResult = ValidateHandle(hDevice)) != ADI_RTC_SUCCESS)
1451  {
1452  return eResult;
1453  }
1454 #endif
1455 
1456  eResult = adi_rtc_GetCoherentCounterValues(hDevice, &snapshots);
1457 
1458  /* snapshots maps to the chosen valid sample or to 0 */
1459  *pCount = (((uint32_t)snapshots.snapshot1) << 16u) | snapshots.snapshot0; /* combine RTC_CNT1 and RTC_CNT0 */
1460 
1461  return eResult;
1462 }
1480 ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount)
1481 {
1482  struct adi_rtc_snapshots snapshots;
1483  ADI_RTC_RESULT eResult;
1484  uint32_t nCount,nTemp;
1485  uint16_t nPrescale;
1486  ADI_RTC_DEVICE *pDevice = hDevice;
1487  float fFraction;
1488 
1489 #ifdef ADI_DEBUG
1490  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1491  {
1492  return eResult;
1493  }
1494 #endif
1495 
1496  eResult = adi_rtc_GetCoherentCounterValues(hDevice, &snapshots);
1497 
1498  nPrescale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
1499  nCount = (((uint32_t)snapshots.snapshot1) << 16u) | snapshots.snapshot0; /* combine RTC_CNT1 and RTC_CNT0 */
1500  nTemp = (1lu<<nPrescale);
1501  fFraction = ((float)snapshots.snapshot2)/((float)nTemp);
1502  *pfCount = ((float)nCount) + fFraction;
1503 
1504  return eResult;
1505 }
1524 ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount)
1525 {
1526  ADI_RTC_RESULT eResult;
1527  struct adi_rtc_snapshots snapshots;
1528 
1529 #ifdef ADI_DEBUG
1530  ADI_RTC_DEVICE *pDevice = hDevice;
1531 
1532  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1533  {
1534  return eResult;
1535  }
1536 #endif
1537 
1538  eResult = adi_rtc_GetCoherentCounterValues(hDevice, &snapshots);
1539 
1540  *pnCount = (((uint32_t)snapshots.snapshot1) << 16u) | snapshots.snapshot0; /* combine RTC_CNT1 and RTC_CNT0 */
1541  *pfCount = (uint32_t)snapshots.snapshot2;
1542 
1543  return eResult;
1544 }
1545 
1578 {
1579  ADI_RTC_DEVICE *pDevice = hDevice;
1580  uint32_t nInterrupt = 0u;
1581 #ifdef ADI_DEBUG
1582  ADI_RTC_RESULT eResult;
1583  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1584  {
1585  return eResult;
1586  }
1587 #endif
1588 
1589  /* Read SR0 interrupts bits (mask out unused bits) and store the bits in the first byte, the LSB */
1590  nInterrupt = ((((uint32_t)pDevice->pRTCRegs->SR0) & ADI_RTC_IRQ_SOURCE_MASK_SR0) << ADI_RTC_IRQ_SOURCE_OFFSET_SR0);
1591 
1592  /* Read SR3 interrupts bits (mask out unused bits) and store the bits in the third and fourth bytes */
1593  nInterrupt |= ((((uint32_t)pDevice->pRTCRegs->SR3) & ADI_RTC_IRQ_SOURCE_MASK_SR3) << ADI_RTC_IRQ_SOURCE_OFFSET_SR3);
1594 
1595  /* For SR2, take RTC0 and RTC1 specific interrupts into account, mask out unused bits and store the value in the second byte */
1596  if( pDevice->pRTCRegs == pADI_RTC1)
1597  {
1598  nInterrupt |= ((((uint32_t)pDevice->pRTCRegs->SR2) & ADI_RTC1_IRQ_SOURCE_MASK_SR2) << ADI_RTC_IRQ_SOURCE_OFFSET_SR2);
1599  }else{
1600  nInterrupt |= ((((uint32_t)pDevice->pRTCRegs->SR2) & ADI_RTC0_IRQ_SOURCE_MASK_SR2) << ADI_RTC_IRQ_SOURCE_OFFSET_SR2);
1601  }
1602 
1603  /* store the value in the out parameter */
1604  *pStatus = (ADI_RTC_INT_TYPE)nInterrupt;
1605  return ADI_RTC_SUCCESS;
1606 }
1607 
1608 
1609 
1644 {
1645  ADI_RTC_DEVICE *pDevice = hDevice;
1646  uint32_t nStatus;
1647 
1648 #ifdef ADI_DEBUG
1649 
1650  /* This ADI_DEBUG macro-guarded code section checks that the bits set in the input parameter
1651  * Status are valid bits, mapped to interrupt bits in the SR0, SR2 and SR3 registers */
1652 
1653  ADI_RTC_RESULT eResult;
1654  uint32_t validInput = ( (((uint32_t) ADI_RTC_IRQ_SOURCE_MASK_SR0) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR0))
1655  | (((uint32_t) ADI_RTC_IRQ_SOURCE_MASK_SR3) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR3))
1656  );
1657 
1658  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1659  {
1660  return eResult;
1661  }
1662 
1663  /* Take RTC0 and RTC1 specific interrupts into account when defining valid inputs */
1664  if( pDevice->pRTCRegs == pADI_RTC1)
1665  {
1666  /* RTC1: SR2 and SR3 registers also have RTC1 specific interrupts bits */
1667  validInput |= (((uint32_t) ADI_RTC1_IRQ_SOURCE_MASK_SR2) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR2));
1668  }else{
1669  /* RTC0: SR2 register also has RTC0 specific interrupts bits */
1670  validInput |= (((uint32_t) ADI_RTC0_IRQ_SOURCE_MASK_SR2) << ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR2));
1671  }
1672 
1673  /* At least one of the possible interrupt bits must be set in Status (else there are no bits to clear...) */
1674  if ((((uint32_t)Status) & validInput) == 0u)
1675  {
1676  return ADI_RTC_INVALID_PARAM;
1677  }
1678 #endif
1679 
1680  /* Wait till previously posted write to Control Register to complete */
1681  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0)
1682 
1683  /* get the interrupt bits to clear in SR0 */
1684  nStatus = ((uint32_t)ADI_RTC_IRQ_SOURCE_MASK_SR0) & (((uint32_t) Status) >> ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR0));
1685 
1686  /* and write them in SR0 */
1687  pDevice->pRTCRegs->SR0 |= (uint16_t) nStatus;
1688 
1689  /* Wait till write to Control Register to take effect */
1690  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0)
1691 
1692  /* get the interrupt bits to clear in SR2 (these bits are RTC0 and RTC1 specific) */
1693  nStatus = ((uint32_t) Status) >> ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR2);
1694  if(pDevice->pRTCRegs == pADI_RTC1)
1695  {
1696  /* RTC1 specific interrupt bits in SR2 */
1697  nStatus &= ((uint32_t) ADI_RTC1_IRQ_SOURCE_MASK_SR2);
1698  }else{
1699  /* RTC0 specific interrupt bits in SR2 */
1700  nStatus &= ((uint32_t) ADI_RTC0_IRQ_SOURCE_MASK_SR2);
1701  }
1702  /* and write them in SR2 */
1703  pDevice->pRTCRegs->SR2 |= (uint16_t) nStatus;
1704 
1705  /* get the interrupt bits to clear in SR3 */
1706  nStatus = ((uint32_t)ADI_RTC_IRQ_SOURCE_MASK_SR3) & (((uint32_t) Status) >> ((uint32_t) ADI_RTC_IRQ_SOURCE_OFFSET_SR3));
1707 
1708  /* and write them in SR3 */
1709  pDevice->pRTCRegs->SR3 |= (uint16_t) nStatus;
1710 
1711  return ADI_RTC_SUCCESS;
1712 }
1713 
1714 
1736 {
1737  ADI_RTC_DEVICE *pDevice = hDevice;
1738 #ifdef ADI_DEBUG
1739  ADI_RTC_RESULT eResult;
1740  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1741  {
1742  return eResult;
1743  }
1744  if(peTrim == NULL)
1745  {
1746  return( ADI_RTC_INVALID_PARAM);
1747  }
1748 #endif
1749 
1750  /* Wait till previously posted write to couunt Register to complete */
1751  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM);
1752 
1753  *peTrim =(ADI_RTC_TRIM_VALUE)(pDevice->pRTCRegs->TRM & BITM_RTC_TRM_VALUE);
1754 
1755  return ADI_RTC_SUCCESS;
1756 }
1775 {
1776  ADI_RTC_DEVICE *pDevice = hDevice;
1777 
1778 #ifdef ADI_DEBUG
1779  ADI_RTC_RESULT eResult;
1780  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1781  {
1782  return eResult;
1783  }
1784 #endif
1785  switch( eSSChannel )
1786  {
1787  case ADI_RTC_SS_CHANNEL_1:
1788  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
1789  *pValue = pDevice->pRTCRegs->SS1;
1790  break;
1791 #if defined(__ADUCM4x50__)
1792  case ADI_RTC_SS_CHANNEL_2:
1793  /* Wait till previously posted write to Control Register to complete */
1794  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
1795  *pValue = pDevice->pRTCRegs->SS2;
1796  break;
1797 
1798  case ADI_RTC_SS_CHANNEL_3:
1799  /* Wait till previously posted write to Control Register to complete */
1800  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
1801  *pValue = pDevice->pRTCRegs->SS3;
1802  break;
1803 
1804  case ADI_RTC_SS_CHANNEL_4:
1805  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
1806  *pValue = pDevice->pRTCRegs->SS4;
1807  break;
1808 #endif /* __ADUCM4x50__ */
1809  default:
1810  return ADI_RTC_FAILURE;
1811  }
1812 
1813 
1814 
1815  return ADI_RTC_SUCCESS;
1816 }
1835 {
1836  ADI_RTC_DEVICE *pDevice = hDevice;
1837 #ifdef ADI_DEBUG
1838  ADI_RTC_RESULT eResult;
1839  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1840  {
1841  return eResult;
1842  }
1843 #endif
1844 
1845  switch( eSSChannel )
1846  {
1847  case ADI_RTC_SS_CHANNEL_1:
1848  /* Wait till previously posted write to Control Register to complete */
1849  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
1850  pDevice->pRTCRegs->SS1 = nValue;
1851  /* Wait till write to Control Register to take effect */
1852  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)
1853  break;
1854 
1855 #if defined(__ADUCM4x50__)
1856  case ADI_RTC_SS_CHANNEL_2:
1857  /* Wait till previously posted write to Control Register to complete */
1858  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
1859  pDevice->pRTCRegs->SS2 = nValue;
1860  /* Wait till write to Control Register to take effect */
1861  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)
1862  break;
1863 
1864  case ADI_RTC_SS_CHANNEL_3:
1865  /* Wait till previously posted write to Control Register to complete */
1866  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
1867  pDevice->pRTCRegs->SS3 = nValue;
1868  /* Wait till write to Control Register to take effect */
1869  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)
1870  break;
1871 
1872  case ADI_RTC_SS_CHANNEL_4:
1873  /* Wait till previously posted write to Control Register to complete */
1874  PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
1875  pDevice->pRTCRegs->SS4 = nValue;
1876  /* Wait till write to Control Register to take effect */
1877  SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4)
1878  break;
1879 #endif /* __ADUCM4x50__ */
1880  default:
1881  return ADI_RTC_FAILURE;
1882  }
1883 
1884  return ADI_RTC_SUCCESS;
1885 }
1886 
1916  ADI_RTC_INPUT_CHANNEL eChannel,
1917  uint16_t *pSnap0,
1918  uint16_t *pSnap1,
1919  uint16_t *pSnap2)
1920 {
1921  ADI_RTC_DEVICE *pDevice = hDevice;
1923 #ifdef ADI_DEBUG
1924  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1925  {
1926  return eResult;
1927  }
1928 #endif
1929  switch(eChannel)
1930  {
1932  *pSnap0=pDevice->pRTCRegs->SNAP0;
1933  *pSnap1=pDevice->pRTCRegs->SNAP1;
1934  *pSnap2=pDevice->pRTCRegs->SNAP2;
1935  break;
1937  *pSnap2= pDevice->pRTCRegs->IC2;
1938  *pSnap0 = *pSnap1 = 0u;
1939  break;
1941  *pSnap2= pDevice->pRTCRegs->IC3;
1942  *pSnap0 = *pSnap1 = 0u;
1943  break;
1945  *pSnap2= pDevice->pRTCRegs->IC4;
1946  *pSnap0 = *pSnap1 = 0u;
1947  break;
1948  default:
1949  eResult = ADI_RTC_INVALID_CHANNEL;
1950  break;
1951  }
1952  return(eResult);
1953 }
1976 {
1977  ADI_RTC_DEVICE *pDevice = hDevice;
1979 
1980 #ifdef ADI_DEBUG
1981  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
1982  {
1983  return eResult;
1984  }
1985 #endif
1986  switch(eChannel)
1987  {
1989  *pValue = pDevice->pRTCRegs->IC2;
1990  break;
1992  *pValue = pDevice->pRTCRegs->IC3;
1993  break;
1994 
1996  *pValue = pDevice->pRTCRegs->IC4;
1997  break;
1998  default:
1999  eResult = ADI_RTC_INVALID_CHANNEL;
2000  break;
2001  }
2002  return(eResult);
2003 }
2025 ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction)
2026 {
2027  ADI_RTC_DEVICE *pDevice = hDevice;
2028  ADI_RTC_RESULT eResult = ADI_RTC_SUCCESS;
2029 
2030 #ifdef ADI_DEBUG
2031  if((eResult = ValidateHandle(hDevice)) != ADI_RTC_SUCCESS)
2032  {
2033  return eResult;
2034  }
2035 
2036  if((NULL == pValue) || (NULL == pFraction) || (ADI_RTC_INPUT_CHANNEL_0 != eChannel))
2037  {
2038  return (ADI_RTC_INVALID_PARAM);
2039  }
2040 #endif
2041 
2042  *pFraction = pDevice->pRTCRegs->SNAP2;
2043  *pValue = (uint32_t)pDevice->pRTCRegs->SNAP1 << 16u;
2044  *pValue |= (uint32_t)pDevice->pRTCRegs->SNAP0;
2045 
2046  return(eResult);
2047 }
2048 
2049 
2091 {
2092  ADI_RTC_DEVICE *pDevice = hDevice;
2093  uint16_t nPendBits;
2094 #ifdef ADI_DEBUG
2095  ADI_RTC_RESULT eResult;
2096  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2097  {
2098  return eResult;
2099  }
2100 #endif
2101  /* get the value */
2102  nPendBits = pDevice->pRTCRegs->SR1 & ADI_RTC_WRITE_STATUS_MASK;
2103  *pPendBits = (ADI_RTC_WRITE_STATUS)nPendBits;
2104 
2105  return ADI_RTC_SUCCESS;
2106 }
2107 
2108 
2150 {
2151  ADI_RTC_DEVICE *pDevice = hDevice;
2152  uint16_t nSyncBits;
2153 #ifdef ADI_DEBUG
2154  ADI_RTC_RESULT eResult;
2155  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2156  {
2157  return eResult;
2158  }
2159 #endif
2160  /* Wait till previously posted write to couunt Register to complete */
2161  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0);
2162 
2163  /* get the value */
2164  nSyncBits = pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK;
2165  *pSyncBits = (ADI_RTC_WRITE_STATUS)nSyncBits;
2166 
2167  return ADI_RTC_SUCCESS;
2168 }
2169 
2170 
2171 /*************************************************************************************************
2172 **************************************************************************************************
2173 ****************************************** SET APIS ******************************************
2174 **************************************************************************************************
2175 *************************************************************************************************/
2176 
2177 
2199 ADI_RTC_RESULT adi_rtc_SetAlarm (ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
2200 {
2201  ADI_RTC_DEVICE *pDevice = hDevice;
2202 #ifdef ADI_DEBUG
2203  ADI_RTC_RESULT eResult;
2204  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2205  {
2206  return eResult;
2207  }
2208 #endif
2209 
2210  /* Wait till previously posted write to Alram Register to complete */
2211  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2212 
2213  ADI_INT_STATUS_ALLOC();
2214  ADI_ENTER_CRITICAL_REGION();
2215  /* RTC hardware insures paired write, so no need to disable interrupts */
2216  pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
2217  pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
2218  pDevice->pRTCRegs->ALM2 = 0u;
2219  ADI_EXIT_CRITICAL_REGION();
2220 
2221  /* Wait till write to Control Register to take effect */
2222  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2223  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2224 
2225  return ADI_RTC_SUCCESS;
2226 }
2227 
2251 ADI_RTC_RESULT adi_rtc_SetAlarmRegs (ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0,uint16_t nAlarm1,uint16_t nAlarm2)
2252 {
2253  ADI_RTC_DEVICE *pDevice = hDevice;
2255 
2256 #ifdef ADI_DEBUG
2257 
2258  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2259  {
2260  return eResult;
2261  }
2262 #endif
2263 
2264  /* Wait till previously posted write to Alarm Register to complete */
2265  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2266 
2267  ADI_INT_STATUS_ALLOC();
2268  ADI_ENTER_CRITICAL_REGION();
2269  /* RTC hardware insures paired write, so no need to disable interrupts */
2270  pDevice->pRTCRegs->ALM0 = nAlarm0;
2271  pDevice->pRTCRegs->ALM1 = nAlarm1;
2272  pDevice->pRTCRegs->ALM2 = nAlarm2;
2273  ADI_EXIT_CRITICAL_REGION();
2274 
2275  /* Wait till write to Control Register to take effect */
2276  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2277  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2278 
2279  return eResult;
2280 }
2281 
2307 ADI_RTC_RESULT adi_rtc_SetAlarmAsync (ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
2308 {
2309  ADI_RTC_DEVICE *pDevice = hDevice;
2310 #ifdef ADI_DEBUG
2311  ADI_RTC_RESULT eResult;
2312  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2313  {
2314  return eResult;
2315  }
2316 #endif
2317 
2318  /* Wait till previously posted write to Alram Register to complete */
2319  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2320 
2321  ADI_INT_STATUS_ALLOC();
2322  ADI_ENTER_CRITICAL_REGION();
2323  /* RTC hardware insures paired write, so no need to disable interrupts */
2324  pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
2325  pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
2326  pDevice->pRTCRegs->ALM2 = 0u;
2327  ADI_EXIT_CRITICAL_REGION();
2328 
2329  return ADI_RTC_SUCCESS;
2330 }
2331 
2357 ADI_RTC_RESULT adi_rtc_SetAlarmRegsAsync (ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0,uint16_t nAlarm1,uint16_t nAlarm2)
2358 {
2359  ADI_RTC_DEVICE *pDevice = hDevice;
2361 
2362 #ifdef ADI_DEBUG
2363 
2364  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2365  {
2366  return eResult;
2367  }
2368 #endif
2369 
2370  /* Wait till previously posted write to Alarm Register to complete */
2371  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2372 
2373  ADI_INT_STATUS_ALLOC();
2374  ADI_ENTER_CRITICAL_REGION();
2375  /* RTC hardware insures paired write, so no need to disable interrupts */
2376  pDevice->pRTCRegs->ALM0 = nAlarm0;
2377  pDevice->pRTCRegs->ALM1 = nAlarm1;
2378  pDevice->pRTCRegs->ALM2 = nAlarm2;
2379  ADI_EXIT_CRITICAL_REGION();
2380 
2381  return eResult;
2382 }
2383 
2407 {
2408  ADI_RTC_DEVICE *pDevice = hDevice;
2409 #ifdef ADI_DEBUG
2410  ADI_RTC_RESULT eResult;
2411  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2412  {
2413  return eResult;
2414  }
2415 #endif
2416 
2417  /* Wait till write to Control Register to take effect */
2418  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2419  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2420 
2421  return ADI_RTC_SUCCESS;
2422 }
2423 
2442 ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const hDevice, uint8_t nPreScale )
2443 {
2444  ADI_RTC_DEVICE *pDevice = hDevice;
2445  uint16_t nTemp;
2446 #ifdef ADI_DEBUG
2447  ADI_RTC_RESULT eResult;
2448  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2449  {
2450  return eResult;
2451  }
2452  /* Pre scale is invalid for RTC0 */
2453  if(pDevice->pRTCRegs == pADI_RTC0)
2454  {
2456  }
2457 #endif
2458  PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
2459  ADI_INT_STATUS_ALLOC();
2460  ADI_ENTER_CRITICAL_REGION();
2461  /* RTC hardware insures paired write, so no need to disable interrupts */
2462  /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
2463  nTemp = pDevice->pRTCRegs->CR1 & (uint16_t)~BITM_RTC_CR1_PRESCALE2EXP;
2464  nTemp |= (uint16_t)((uint16_t)nPreScale << BITP_RTC_CR1_PRESCALE2EXP);
2465  pDevice->pRTCRegs->CR1 = nTemp;
2466  ADI_EXIT_CRITICAL_REGION();
2467 
2468  SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)
2469  return ADI_RTC_SUCCESS;
2470 }
2489 {
2490  ADI_RTC_DEVICE *pDevice = hDevice;
2491  uint16_t nTemp;
2492 #ifdef ADI_DEBUG
2493  ADI_RTC_RESULT eResult;
2494  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2495  {
2496  return eResult;
2497  }
2498 
2499  /* Mod60 Alarm is valid only in RTC-1 */
2500  if(pDevice->pRTCRegs == pADI_RTC0)
2501  {
2503  }
2504 
2505 #endif
2506 
2507  /* Wait till previously posted write to Control Register to complete */
2508  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
2509 
2510  ADI_INT_STATUS_ALLOC();
2511  ADI_ENTER_CRITICAL_REGION();
2512  /* RTC hardware insures paired write, so no need to disable interrupts */
2513  /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
2514  nTemp = pDevice->pRTCRegs->CR0 & BITM_RTC_CR0_MOD60ALM;
2515  nTemp |= (uint16_t)((uint16_t)nPeriod << BITP_RTC_CR0_MOD60ALM);
2516  pDevice->pRTCRegs->CR0 = nTemp;
2517  ADI_EXIT_CRITICAL_REGION();
2518  /* Wait till write to Control Register to take effect */
2519  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
2520 
2521  return ADI_RTC_SUCCESS;
2522 }
2545 {
2546  ADI_RTC_DEVICE *pDevice = hDevice;
2547  uint32_t nAlarm = (uint32_t)fAlarm,nTemp;
2548  uint16_t nPreScale;
2549  float fFraction;
2550 #ifdef ADI_DEBUG
2551  ADI_RTC_RESULT eResult;
2552  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2553  {
2554  return eResult;
2555  }
2556  /* Only 1Hz clocking is supported in RTC-0.So no fractional Alarm. */
2557  if(pDevice->pRTCRegs == pADI_RTC0)
2558  {
2560  }
2561 
2562 #endif
2563 
2564  /* Wait till previously posted write to Alarm Register to complete */
2565  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2566  nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
2567  ADI_INT_STATUS_ALLOC();
2568  ADI_ENTER_CRITICAL_REGION();
2569  /* RTC hardware insures paired write, so no need to disable interrupts */
2570  /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
2571  pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
2572  pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
2573  nTemp = 1lu<<nPreScale;
2574  fFraction = (fAlarm - (float)nAlarm) *(float)(nTemp);
2575  pDevice->pRTCRegs->ALM2 = (uint16_t)(fFraction);
2576  ADI_EXIT_CRITICAL_REGION();
2577  /* Wait till write to Alarm Register to take effect */
2578  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2579  SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCALM2MIR))
2580 
2581  return ADI_RTC_SUCCESS;
2582 }
2583 
2606 {
2607  ADI_RTC_DEVICE *pDevice = hDevice;
2608 
2609 #ifdef ADI_DEBUG
2610  ADI_RTC_RESULT eResult;
2611  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2612  {
2613  return eResult;
2614  }
2615 #endif
2616  /* Wait till previously posted write to Control Register to complete */
2617  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
2618 
2619  switch(eRegister)
2620  {
2622  pDevice->pRTCRegs->CR0 = (uint16_t)Control;
2623  break;
2625  pDevice->pRTCRegs->CR1 = (uint16_t)Control;
2626  break;
2627  default:
2628  return(ADI_RTC_FAILURE);
2629  }
2630  /* Wait till write to Control Register to take effect */
2631  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)
2632 
2633  return ADI_RTC_SUCCESS;
2634 
2635 }
2636 
2654  ADI_RTC_HANDLE const hDevice,
2655  ADI_CALLBACK const pfCallback,
2656  void *const pCBparam
2657  )
2658 
2659 {
2660  ADI_RTC_DEVICE *pDevice = hDevice;
2661 
2662 #ifdef ADI_DEBUG
2663  ADI_RTC_RESULT eResult;
2664  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2665  {
2666  return eResult;
2667  }
2668 #endif
2669 
2670 #if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
2671  /* pause on pending writes to CR to avoid data loss */
2672  while((pDevice->pRTCRegs->SR1 & (uint32_t)ADI_RTC_WRITE_STATUS_CONTROL0)!=0u)
2673  {
2674  }
2675 #endif
2676  /* Store the address of the callback function */
2677  pDevice->pfCallback = pfCallback;
2678  /* Store the call back parameter */
2679  pDevice->pCBParam = pCBparam;
2680 
2681  return ADI_RTC_SUCCESS;
2682 
2683 }
2684 
2705 ADI_RTC_RESULT adi_rtc_SetCount (ADI_RTC_HANDLE const hDevice, uint32_t nCount)
2706 {
2707  ADI_RTC_DEVICE *pDevice = hDevice;
2708 
2709 #ifdef ADI_DEBUG
2710  ADI_RTC_RESULT eResult;
2711  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2712  {
2713  return eResult;
2714  }
2715 #endif
2716 
2717 #if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
2718  /* pause on pending writes to CR to avoid data loss */
2719  while((pDevice->pRTCRegs->SR1 & (uint32_t)(ADI_RTC_WRITE_STATUS_COUNT0 | ADI_RTC_WRITE_STATUS_COUNT1)) !=0u)
2720  {
2721 
2722  }
2723 #endif
2724 
2725  /* Wait till previously posted write to count Register to complete */
2726  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
2727 
2728  ADI_INT_STATUS_ALLOC();
2729  ADI_ENTER_CRITICAL_REGION();
2730  /* RTC hardware insures paired write, so no need to disable interrupts */
2731  pDevice->pRTCRegs->CNT0 = (uint16_t)nCount;
2732  pDevice->pRTCRegs->CNT1 = (uint16_t)(nCount >> 16);
2733  ADI_EXIT_CRITICAL_REGION();
2734 
2735  /* Wait till write to count Register to take effect */
2736  SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1))
2737 
2738  return ADI_RTC_SUCCESS;
2739 }
2740 
2741 
2763 ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command)
2764 {
2765  ADI_RTC_DEVICE *pDevice = hDevice;
2766 
2767 #ifdef ADI_DEBUG
2768  ADI_RTC_RESULT eResult;
2769  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2770  {
2771  return eResult;
2772  }
2773 #endif
2774  /* set the command */
2775  pDevice->pRTCRegs->GWY = Command;
2776  return ADI_RTC_SUCCESS;
2777 }
2778 
2779 
2780 
2806 {
2807  ADI_RTC_DEVICE *pDevice = hDevice;
2808  uint32_t trm = (uint32_t)eInterval | (uint32_t)eTrimValue | (uint32_t)eOperation;
2809 
2810 #ifdef ADI_DEBUG
2811  ADI_RTC_RESULT eResult;
2812  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2813  {
2814  return eResult;
2815  }
2816 
2817 #endif
2818 
2819  /* Wait till previously posted write to Control Register to complete */
2820  PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM)
2821 
2822  pDevice->pRTCRegs->TRM = (uint16_t)trm;
2823 
2824  /* Wait till write to Control Register to take effect */
2825  SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCTRM)
2826 
2827  return ADI_RTC_SUCCESS;
2828 }
2829 
2830 
2831 /*************************************************************************************************
2832 **************************************************************************************************
2833 ************************************ SYNCHRONIZATION API *************************************
2834 **************************************************************************************************
2835 *************************************************************************************************/
2836 
2837 
2854 {
2855  ADI_RTC_DEVICE *pDevice = hDevice;
2856 #ifdef ADI_DEBUG
2857  ADI_RTC_RESULT eResult;
2858  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
2859  {
2860  return eResult;
2861  }
2862 
2863 #endif
2864 
2865  /* forced block until all SYNC bits are set (ignore bSafe) */
2866  while (ADI_RTC_WRITE_STATUS_MASK != (pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK))
2867  {
2868 
2869  }
2870 
2871  return ADI_RTC_SUCCESS;
2872 }
2873 
2874 
2877 /*
2878  * @brief Initializes the device using static configuration
2879  *
2880  * @param[in] pDevice Pointer to RTC device .
2881  pConfig Pointer to static configuration device structure.
2882  *
2883 */
2884 
2885 static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig)
2886 {
2887  /* Control register -0 which controls all main stream activity of RTC0 */
2888  ALWAYS_PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
2889  pDevice->pRTCRegs->CR0 = pConfig->CR0;
2890 
2891  /* Control register -1 which is granularity of RTC control register */
2892  ALWAYS_PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
2893  pDevice->pRTCRegs->CR1 = pConfig->CR1;
2894 
2895  /*CNT0 contains the lower 16 bits of the RTC counter */
2896  /*CNT1 contains the upper 16 bits of the RTC counter */
2897  ALWAYS_PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
2898  pDevice->pRTCRegs->CNT0 = pConfig->CNT0;
2899  pDevice->pRTCRegs->CNT1 = pConfig->CNT1;
2900 
2901  /* ALM0 contains the lower 16 bits of the Alarm register */
2902  /* ALM1 contains the upper 16 bits of the Alarm register */
2903  ALWAYS_PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
2904  pDevice->pRTCRegs->ALM0 = pConfig->ALM0;
2905  pDevice->pRTCRegs->ALM1 = pConfig->ALM1;
2906 
2907  /* ALM2 contains the fractional part of the Alarm register */
2908  ALWAYS_PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDALM2MIR)
2909  pDevice->pRTCRegs->ALM2 = pConfig->ALM2;
2910 
2911  /* Set Input capture/sensor strobe registers only for RTC1 */
2912  if(pDevice->pRTCRegs == pADI_RTC1)
2913  {
2914  ALWAYS_PEND_BEFORE_WRITE(SR5,(BITM_RTC_SR5_WPENDCR2IC|BITM_RTC_SR5_WPENDCR3SS|BITM_RTC_SR5_WPENDCR4SS|BITM_RTC_SR5_WPENDSSMSK|BITM_RTC_SR5_WPENDSS1))
2915  pDevice->pRTCRegs->CR2IC = pConfig->CR2IC;
2916  pDevice->pRTCRegs->CR3SS = pConfig->CR3SS;
2917  pDevice->pRTCRegs->CR4SS = pConfig->CR4SS;
2918  pDevice->pRTCRegs->SSMSK = pConfig->SSMSK;
2919  pDevice->pRTCRegs->SS1 = pConfig->SS1;
2920 #if defined(__ADUCM4x50__)
2921  ALWAYS_PEND_BEFORE_WRITE(SR9,(BITM_RTC_SR9_WPENDCR5SSS|BITM_RTC_SR9_WPENDCR6SSS|BITM_RTC_SR9_WPENDCR7SSS|BITM_RTC_SR9_WPENDGPMUX0|BITM_RTC_SR9_WPENDGPMUX1))
2922  pDevice->pRTCRegs->CR5SSS = pConfig->CR5SSS;
2923  pDevice->pRTCRegs->CR6SSS = pConfig->CR6SSS;
2924  pDevice->pRTCRegs->CR7SSS = pConfig->CR7SSS;
2925  pDevice->pRTCRegs->GPMUX0 = pConfig->GPMUX0;
2926  pDevice->pRTCRegs->GPMUX1 = pConfig->GPMUX1;
2927 #endif /* __ADUCM4x50__ */
2928  }
2929  ALWAYS_SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCR0|BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1|BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))
2930  ALWAYS_SYNC_AFTER_WRITE(SR2,(BITM_RTC_SR2_WSYNCCR1MIR|BITM_RTC_SR2_WSYNCALM2MIR))
2931  ALWAYS_SYNC_AFTER_WRITE(SR4,(BITM_RTC_SR4_WSYNCCR2IC|BITM_RTC_SR4_WSYNCCR3SS|BITM_RTC_SR4_WSYNCCR4SS|BITM_RTC_SR4_WSYNCSSMSK|BITM_RTC_SR4_WSYNCSS1))
2932 #if defined(__ADUCM4x50__)
2933  ALWAYS_SYNC_AFTER_WRITE(SR8,(BITM_RTC_SR8_WSYNCCR5SSS|BITM_RTC_SR8_WSYNCCR6SSS|BITM_RTC_SR8_WSYNCCR7SSS|BITM_RTC_SR8_WSYNCGPMUX0|BITM_RTC_SR8_WSYNCGPMUX1))
2934 #endif
2935 }
2936 
2937 
2938 
2940 void RTC0_Int_Handler(void)
2941 {
2942  ISR_PROLOG();
2943  uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
2944  uint32_t fired = 0u, enables = 0u;
2945  ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[0].hDevice;
2946 
2947  /* determine qualified interrupt source(s) */
2948  /* need to test each interrupt source and whether it is enabled before notifying */
2949  /* because each source is latched regardless of whether it is enabled or not :-( */
2950 
2951  /* CR0 SR0 */
2952  enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0;
2953  nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_IRQ_SOURCE_MASK_SR0;
2954  if( nIntSrc0 && enables )
2955  {
2956  if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
2957  {
2958  fired |= ADI_RTC_MOD60ALM_INT;
2959  }
2960  if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
2961  {
2962  fired |= ADI_RTC_ALARM_INT;
2963  }
2964  if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
2965  {
2966  fired |= ADI_RTC_ISO_DONE_INT;
2967  }
2968  if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
2969  {
2970  fired |= ADI_RTC_WRITE_PEND_INT;
2971  }
2972  if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
2973  {
2974  fired |= ADI_RTC_WRITE_SYNC_INT;
2975  }
2976  if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
2977  {
2978  fired |= ADI_RTC_WRITE_PENDERR_INT;
2979  }
2980  }
2981 
2982  /* CR1 SR2 */
2983  enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1;
2984  nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC0_IRQ_SOURCE_MASK_SR2;
2985  if( nIntSrc2 && enables )
2986  {
2987  if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
2988  {
2989  fired |= ADI_RTC_COUNT_ROLLOVER_INT;
2990  }
2991  if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
2992  {
2993  fired |= ADI_RTC_TRIM_INT;
2994  }
2995  if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
2996  {
2997  fired |= ADI_RTC_PSI_INT;
2998  }
2999  if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
3000  {
3001  fired |= ADI_RTC_COUNT_INT;
3002  }
3003  }
3004 
3005  /* CR3OC, CR2IC SR3*/
3006  enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR3SS;
3007  nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_IRQ_SOURCE_MASK_SR3;
3008  if( nIntSrc3 && enables )
3009  {
3010 #if defined(__ADUCM4x50__)
3011  if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
3012  {
3013  fired |= ADI_RTC_SENSOR_STROBE_CH4_INT;
3014  }
3015  if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
3016  {
3017  fired |= ADI_RTC_SENSOR_STROBE_CH3_INT;
3018  }
3019  if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
3020  {
3021  fired |= ADI_RTC_SENSOR_STROBE_CH2_INT;
3022  }
3023 #endif /* __ADUCM4x50__ */
3024 
3025  if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
3026  {
3028  }
3029 
3030 #if defined(__ADUCM4x50__)
3031  if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
3032  {
3033  fired |= ADI_RTC_RTCSS4_FE_INT;
3034  }
3035  if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
3036  {
3037  fired |= ADI_RTC_RTCSS3_FE_INT;
3038  }
3039  if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
3040  {
3041  fired |= ADI_RTC_RTCSS2_FE_INT;
3042  }
3043  if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
3044  {
3045  fired |= ADI_RTC_RTCSS1_FE_INT;
3046  }
3047 #endif /* __ADUCM4x50__ */
3048  }
3049  enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR2IC;
3050  if( nIntSrc3 && enables )
3051  {
3052  if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
3053  {
3055  }
3056  if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
3057  {
3059  }
3060  if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
3061  {
3063  }
3064  if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
3065  {
3067  }
3068  }
3069 
3070 
3071  if (pDevice->pfCallback != NULL) {
3072 
3073  /* forward to the user if he is watching this interrupt */
3074  /* pass the "fired" value as the event. argument param is not used */
3075  if ( fired)
3076  {
3077  pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
3078  }
3079  }
3080 
3081  /* Write 1 to clear the interrupts */
3082  pDevice->pRTCRegs->SR0 |= nIntSrc0;
3083  pDevice->pRTCRegs->SR2 |= nIntSrc2;
3084  pDevice->pRTCRegs->SR3 |= nIntSrc3;
3085  ISR_EPILOG();
3086 }
3087 
3089 void RTC1_Int_Handler(void)
3090 {
3091  ISR_PROLOG();
3092  uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
3093  uint32_t fired = 0u, enables = 0u;
3094  ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[1].hDevice;
3095 
3096  /* determine qualified interrupt source(s) */
3097  /* need to test each interrupt source and whether it is enabled before notifying */
3098  /* because each source is latched regardless of whether it is enabled or not :-( */
3099 
3100  /* CR0 SR0 */
3101  enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0;
3102  nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_IRQ_SOURCE_MASK_SR0;
3103  if( nIntSrc0 && enables )
3104  {
3105  if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
3106  {
3107  fired |= ADI_RTC_MOD60ALM_INT;
3108  }
3109  if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
3110  {
3111  fired |= ADI_RTC_ALARM_INT;
3112  }
3113  if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
3114  {
3115  fired |= ADI_RTC_ISO_DONE_INT;
3116  }
3117  if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
3118  {
3119  fired |= ADI_RTC_WRITE_PEND_INT;
3120  }
3121  if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
3122  {
3123  fired |= ADI_RTC_WRITE_SYNC_INT;
3124  }
3125  if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
3126  {
3127  fired |= ADI_RTC_WRITE_PENDERR_INT;
3128  }
3129  }
3130 
3131  /* CR1 SR2 */
3132  enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1;
3133  nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC1_IRQ_SOURCE_MASK_SR2;
3134  if( nIntSrc2 && enables )
3135  {
3136  if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT))
3137  {
3138  fired |= ADI_RTC_MOD60_ROLLOVER_INT;
3139  }
3140  if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
3141  {
3142  fired |= ADI_RTC_COUNT_ROLLOVER_INT;
3143  }
3144  if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
3145  {
3146  fired |= ADI_RTC_TRIM_INT;
3147  }
3148  if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
3149  {
3150  fired |= ADI_RTC_PSI_INT;
3151  }
3152  if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
3153  {
3154  fired |= ADI_RTC_COUNT_INT;
3155  }
3156  }
3157 
3158  /* CR3OC, CR2IC SR3*/
3159  enables = pDevice->pRTCRegs->CR3SS & (uint32_t)ADI_RTC_INT_ENA_MASK_CR3SS;
3160  nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_IRQ_SOURCE_MASK_SR3;
3161  if( nIntSrc3 && enables )
3162  {
3163 #if defined(__ADUCM4x50__)
3164  if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
3165  {
3166  fired |= ADI_RTC_SENSOR_STROBE_CH4_INT;
3167  }
3168  if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
3169  {
3170  fired |= ADI_RTC_SENSOR_STROBE_CH3_INT;
3171  }
3172  if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
3173  {
3174  fired |= ADI_RTC_SENSOR_STROBE_CH2_INT;
3175  }
3176 #endif /* __ADUCM4x50__ */
3177  if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
3178  {
3180  }
3181 #if defined(__ADUCM4x50__)
3182  if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
3183  {
3184  fired |= ADI_RTC_RTCSS4_FE_INT;
3185  }
3186  if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
3187  {
3188  fired |= ADI_RTC_RTCSS3_FE_INT;
3189  }
3190  if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
3191  {
3192  fired |= ADI_RTC_RTCSS2_FE_INT;
3193  }
3194  if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
3195  {
3196  fired |= ADI_RTC_RTCSS1_FE_INT;
3197  }
3198 #endif /* __ADUCM4x50__ */
3199  }
3200  enables = pDevice->pRTCRegs->CR2IC & (uint32_t)ADI_RTC_INT_ENA_MASK_CR2IC;
3201  if( nIntSrc3 && enables )
3202  {
3203  if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
3204  {
3206  }
3207  if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
3208  {
3210  }
3211  if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
3212  {
3214  }
3215  if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
3216  {
3218  }
3219  }
3220 
3221  if (pDevice->pfCallback != NULL) {
3222 
3223  /* forward to the user if he is watching this interrupt */
3224  /* pass the "fired" value as the event. argument param is not used */
3225  if ( fired)
3226  {
3227  pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
3228  }
3229  }
3230 
3231  /* Write 1 to clear the interrupts */
3232  pDevice->pRTCRegs->SR0 |= nIntSrc0;
3233  pDevice->pRTCRegs->SR2 |= nIntSrc2;
3234  pDevice->pRTCRegs->SR3 |= nIntSrc3;
3235 
3236  ISR_EPILOG();
3237 }
3238 
3239 #ifndef ADI_TIME_WA_21000023
3240 
3241 /* set this value to non-0 to time snapshots */
3242 #define ADI_TIME_WA_21000023 (0)
3243 
3244 #endif
3245 
3246 /* variable storing the number of cycles needed to read snapshots */
3247 uint32_t cycleCountId_WA_21000023 = 0u;
3248 
3249 #if defined(ADUCM4050_SI_REV) && (ADUCM4050_SI_REV==0) && (WA_21000023!=0)
3250 
3251 /* number of snapshots to take for WA 21000023 */
3252 #define ADI_WA_21000023_SAMPLES_NUMBER (3u)
3253 
3254 #define ADI_RTC_PRESCALE_POS (5u)
3255 
3256 /* bits 8-5 in RTC_CR1 */
3257 #define ADI_RTC_PRESCALE_MSK (0x01E0u)
3258 
3259 
3260 /* Get coherent values for the three RTC counters: COUNT0, COUNT1, COUNT2
3261  * Read the current 47-bit RTC count value and write it to the address provided
3262  * by parameter pCount.
3263  *
3264  * This version implements a software work around for anomaly 21000026.
3265  * Multiple snapshots are taken and a valid value is selected. If no values
3266  * can be marked as valid, the counter value reads the last value read and
3267  * return ADI_RTC_FAILURE.
3268  *
3269  * This version is should be used with ADuCM4x50 silicon revision 0.0.
3270  * It can be used with any ADuCM302xand any ADuCM4x50 though.
3271  *
3272  * WARNING: Using SNAPn registers means this version is unsafe to use with RTC1
3273  * Input Capture channel 0 as it's not possible to share the SNAPn
3274  * registers without taking the risk of overwriting the snap shots
3275  * values or use snap shots taken earlier.
3276  */
3277 static ADI_RTC_RESULT adi_rtc_GetCoherentCounterValues(ADI_RTC_HANDLE const hDevice, struct adi_rtc_snapshots *pSnapshots)
3278 {
3279  ADI_RTC_RESULT eResult = ADI_RTC_SUCCESS;
3280 #if (0!=ADI_TIME_WA_21000023)
3281  uint32_t cycStart; /* cycle count value before snapshots */
3282  uint32_t cycEnd; /* cycle count value after snapshots */
3283 #endif
3284 
3285  /* snapshots samples */
3286  struct adi_rtc_snapshots snapshots[ADI_WA_21000023_SAMPLES_NUMBER];
3287  uint64_t samples[ADI_WA_21000023_SAMPLES_NUMBER]; /* 64-bit samples */
3288  uint16_t rtc_cr1; /* used to access RTC register CR1 */
3289  uint64_t prescale = 0u; /* RTC_CR1.PRESCALE as 64-bit (use 0 for RTC0) */
3290  uint64_t mask; /* to clear invalid bits from COUNT2, as 64-bit */
3291  size_t i;
3292  size_t selectedSample = 2u; /* selected sample is the most recent one by default */
3293  ADI_RTC_DEVICE *pDevice = hDevice;
3294 
3295 #ifdef ADI_DEBUG
3296  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
3297  {
3298  return eResult;
3299  }
3300 #endif
3301 
3302  /* Wait till previously posted write to count Register to complete */
3303  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
3304 
3305  /* disable interrupts when reading RTC counter registers */
3306  ADI_INT_STATUS_ALLOC();
3307  ADI_ENTER_CRITICAL_REGION();
3308 
3309 #if (0!=ADI_TIME_WA_21000023)
3310  cycStart = DWT->CYCCNT;
3311 #endif
3312 
3313  /* Take a snapshot using the RTC_SNAPSHOT_KEY command and then
3314  * - read RTC_CNT0 snapshot value,
3315  * - read RTC_CNT1 snapshot value and
3316  * - read RTC_CNT2 snapshot value
3317  */
3318  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3319  snapshots[0].snapshot0 = pDevice->pRTCRegs->SNAP0;
3320  snapshots[0].snapshot1 = pDevice->pRTCRegs->SNAP1;
3321  snapshots[0].snapshot2 = pDevice->pRTCRegs->SNAP2;
3322 
3323  /* Take a snapshot using the RTC_SNAPSHOT_KEY command and then
3324  * - read RTC_CNT0 snapshot value,
3325  * - read RTC_CNT1 snapshot value and
3326  * - read RTC_CNT2 snapshot value
3327  */
3328  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3329  snapshots[1].snapshot0 = pDevice->pRTCRegs->SNAP0;
3330  snapshots[1].snapshot1 = pDevice->pRTCRegs->SNAP1;
3331  snapshots[1].snapshot2 = pDevice->pRTCRegs->SNAP2;
3332 
3333  /* Take a snapshot using the RTC_SNAPSHOT_KEY command and then
3334  * - read RTC_CNT0 snapshot value,
3335  * - read RTC_CNT1 snapshot value and
3336  * - read RTC_CNT2 snapshot value
3337  */
3338  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3339  snapshots[2].snapshot0 = pDevice->pRTCRegs->SNAP0;
3340  snapshots[2].snapshot1 = pDevice->pRTCRegs->SNAP1;
3341  snapshots[2].snapshot2 = pDevice->pRTCRegs->SNAP2;
3342 
3343 #if (0!=ADI_TIME_WA_21000023)
3344  cycEnd = DWT->CYCCNT;
3345 #endif
3346 
3347  /* read RTC_CR1 register */
3348  rtc_cr1 = pDevice->pRTCRegs->CR1;
3349 
3350  /* enable interrupts */
3351  ADI_EXIT_CRITICAL_REGION();
3352 
3353 
3354  /* If RTC is
3355  *
3356  * - RTC0
3357  * Keep prescale value to 0 as COUNT2/SNAP2 are to be ignored.
3358  *
3359  * - RTC1
3360  * Extract the prescale information from RTC_CR1:
3361  * this defines the number of valid bits in COUNT2 (between 0 and 15)
3362  */
3363  if (aRTCDeviceInfo[0].pRTCRegs != pDevice->pRTCRegs)
3364  {
3365  /* RTC1: get the prescale value */
3366  prescale = (rtc_cr1 & ADI_RTC_PRESCALE_MSK) >> ADI_RTC_PRESCALE_POS;
3367  }
3368  mask = (1u << prescale) - 1u;
3369 
3370 
3371  /* Create formatted counter values, between 32-bit and 47-bit long,
3372  * and store them in 64-bit data.
3373  */
3374  for (i=0u; i<ADI_WA_21000023_SAMPLES_NUMBER; i++)
3375  {
3376  samples[i] = ( ( (((uint64_t) snapshots[i].snapshot1) << (uint64_t) 16u)
3377  | ((uint64_t) snapshots[i].snapshot0)
3378  ) << prescale
3379  )
3380  | (((uint64_t) snapshots[i].snapshot2) & mask)
3381  ;
3382  }
3383 
3384 
3385  /* A sample is valid if
3386  * - it's equal to one of its previous samples, or
3387  * - it's equal to one of its previous samples plus one.
3388  *
3389  * If samples[2] is valid then use snapshots[2]
3390  * else if samples[1] is valid then use snapshots[1]
3391  * else there are no valid samples: use snapshots[2]
3392  * and return an error code
3393  */
3394  if ( (! ((samples[2] == samples[1]) || (samples[2] == (samples[1] + 1u))))
3395  && (! ((samples[2] == samples[0]) || (samples[2] == (samples[0] + 1u))))
3396  )
3397  {
3398  /* sample[2] is not valid */
3399 
3400  if ((samples[1] == samples[0]) || (samples[1] == (samples[0] + 1u)))
3401  {
3402  /* sample[1] is valid */
3403  selectedSample = 1u; /* map snapshots to snapshots[1]*/
3404  }
3405  else
3406  {
3407  /* there are no valid samples!!!
3408  * The most recent value will be used by default.
3409  */
3410  eResult = ADI_RTC_FAILURE;
3411  }
3412  }
3413 
3414 #if (0!=ADI_TIME_WA_21000023)
3415 
3416  /* If timing the access to snapshots is required, use the two cycle number
3417  * to create a number of cycles needed to execute the accesses.
3418  * The implementation take into account cases when cycEnd overflows.
3419  * (Time to execute these accesses is too small to get cycEnd overflowing
3420  * more than once.)
3421  */
3422  if (cycStart < cycEnd)
3423  {
3424  cycleCountId_WA_21000023 = cycEnd - cycStart;
3425  }
3426  else
3427  {
3428  cycleCountId_WA_21000023 = 0xFFFFFFFFu - cycStart + cycEnd;
3429  }
3430 
3431 #endif
3432 
3433  /* use the selected sample as the RTC counter value to return */
3434  *pSnapshots = snapshots[selectedSample];
3435 
3436  return eResult;
3437 }
3438 
3439 
3440 #else /* defined(ADUCM4050_SI_REV) && (ADUCM4050_SI_REV==0) && (WA_21000023!=0) */
3441 
3442 /* Get coherent values for the three RTC counters: COUNT0, COUNT1, COUNT2
3443  * Read the current 47-bit RTC count value and write it to the address provided
3444  * by parameter pCount.
3445  *
3446  * This version doesn't implements a software work around for anomaly 21000026.
3447  * It's aimed at any ADuCM302x silicon revision and ADuCM4x50 silicon revision
3448  * 0.1 and beyond. For ADuCM4x50 silicon revision 0.0, it is recommended to use
3449  * the version with a work around.
3450  */
3451 static ADI_RTC_RESULT adi_rtc_GetCoherentCounterValues(ADI_RTC_HANDLE const hDevice, struct adi_rtc_snapshots *pSnapshots)
3452 {
3453  ADI_RTC_DEVICE *pDevice = hDevice;
3454  struct adi_rtc_snapshots snapshots;
3455 #if (0!=ADI_TIME_WA_21000023)
3456  uint32_t cycStart; /* cycle count value before snapshots */
3457  uint32_t cycEnd; /* cycle count value after snapshots */
3458 #endif
3459 
3460 #ifdef ADI_DEBUG
3461  ADI_RTC_RESULT eResult;
3462 
3463  if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
3464  {
3465  return eResult;
3466  }
3467 #endif
3468 
3469  /* Wait till previously posted write to count Register to complete */
3470  PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
3471 
3472  /* disable interrupts when reading RTC snapshots registers */
3473  ADI_INT_STATUS_ALLOC();
3474  ADI_ENTER_CRITICAL_REGION();
3475 
3476 #if (0!=ADI_TIME_WA_21000023)
3477  cycStart = DWT->CYCCNT;
3478 #endif
3479 
3480  /* get a snaphsot of RTC_CNTn registers, then
3481  * - read RTC_CNT0 snapshot value,
3482  * - read RTC_CNT1 snapshot value and
3483  * - read RTC_CNT2 snapshot value
3484  */
3485  pDevice->pRTCRegs->GWY = RTC_SNAPSHOT_KEY;
3486  snapshots.snapshot0 = pDevice->pRTCRegs->SNAP0;
3487  snapshots.snapshot1 = pDevice->pRTCRegs->SNAP1;
3488  snapshots.snapshot2 = pDevice->pRTCRegs->SNAP2;
3489 
3490 #if (0!=ADI_TIME_WA_21000023)
3491  cycEnd = DWT->CYCCNT;
3492 #endif
3493 
3494  /* enable interrupts */
3495  ADI_EXIT_CRITICAL_REGION();
3496 
3497 #if (0!=ADI_TIME_WA_21000023)
3498 
3499  /* If timing the access to snapshots is required, use the two cycle numbers
3500  * to create a number of cycles needed to execute the accesses.
3501  * The implementation take into account cases when cycEnd overflows.
3502  * (Time to execute these accesses is too small to get cycEnd overflowing
3503  * more than once.)
3504  */
3505  if (cycStart < cycEnd)
3506  {
3507  cycleCountId_WA_21000023 = cycEnd - cycStart;
3508  }
3509  else
3510  {
3511  cycleCountId_WA_21000023 = 0xFFFFFFFFu - cycStart + cycEnd;
3512  }
3513 
3514 #endif
3515 
3516  *pSnapshots = snapshots;
3517 
3518  return ADI_RTC_SUCCESS;
3519 }
3520 
3521 #endif /* defined(ADUCM4050_SI_REV) && (ADUCM4050_SI_REV==0) && (WA_21000023!=0) */
3522 
3525 /* @} */
ADI_RTC_RESULT adi_rtc_ClearInterruptStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Status)
Clear an RTC interrupt status bit(s).
Definition: adi_rtc.c:1643
#define ADI_RTC_INPUT_CAPTURE_CH4_INT
Definition: adi_rtc.h:151
ADI_RTC_RESULT adi_rtc_GetInputCaptureValueEx(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pSnap0, uint16_t *pSnap1, uint16_t *pSnap2)
Get input capture value for specified input channel.
Definition: adi_rtc.c:1915
ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue)
Set auto reload value for the given Sensor Strobe channel.
Definition: adi_rtc.c:1057
#define ADI_RTC_WRITE_PEND_INT
Definition: adi_rtc.h:141
ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount)
Get current RTC count value.
Definition: adi_rtc.c:1444
#define ADI_RTC_SENSOR_STROBE_CH1_INT
Definition: adi_rtc.h:147
ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue)
Set Sensor Strobe value for the given Sensor Strobe channel.
Definition: adi_rtc.c:1834
ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command)
Set an RTC gateway command.
Definition: adi_rtc.c:2763
#define ADI_RTC_IRQ_SOURCE_MASK_SR0
Definition: adi_rtc.h:80
ADI_RTC_RESULT adi_rtc_Close(ADI_RTC_HANDLE const hDevice)
Uninitialize and deallocate an RTC device.
Definition: adi_rtc.c:399
#define ADI_RTC_IRQ_SOURCE_OFFSET_SR2
Definition: adi_rtc.h:83
#define ADI_RTC_IRQ_SOURCE_OFFSET_SR3
Definition: adi_rtc.h:91
ADI_RTC_RESULT adi_rtc_SetAlarm(ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
Set a new RTC alarm value.
Definition: adi_rtc.c:2199
ADI_RTC_RESULT adi_rtc_GetTrim(ADI_RTC_HANDLE hDevice, ADI_RTC_TRIM_VALUE *peTrim)
Get current RTC clock trim value.
Definition: adi_rtc.c:1735
uint32_t ADI_RTC_INT_TYPE
Definition: adi_rtc.h:134
ADI_RTC_RESULT adi_rtc_GetInterruptStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE *pStatus)
Get current RTC interrupt source status.
Definition: adi_rtc.c:1577
#define ADI_RTC_ISO_DONE_INT
Definition: adi_rtc.h:138
ADI_RTC_RESULT adi_rtc_SetAlarmRegsAsync(ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0, uint16_t nAlarm1, uint16_t nAlarm2)
Set a new RTC alarm value for RTC ALM0, ALM1 and ALM2 Registers without waiting for synchronization...
Definition: adi_rtc.c:2357
ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites(ADI_RTC_HANDLE const hDevice)
Force synchronization of all pending writes.
Definition: adi_rtc.c:2853
void * ADI_RTC_HANDLE
Definition: adi_rtc.h:74
ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pValue)
Get input capture value for specified input channel.
Definition: adi_rtc.c:1975
#define ADI_RTC_INPUT_CAPTURE_CH0_INT
Definition: adi_rtc.h:148
#define ADI_RTC0_IRQ_SOURCE_MASK_SR2
Definition: adi_rtc.h:86
#define ADI_RTC_ALARM_INT
Definition: adi_rtc.h:136
ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t *pValue)
Get Sensor Strobe value for the given Sensor Strobe channel.
Definition: adi_rtc.c:1774
ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount)
Get current RTC count value of all registers.
Definition: adi_rtc.c:1524
ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pSyncBits)
Get current RTC posted write synchronization status.
Definition: adi_rtc.c:2149
ADI_RTC_RESULT adi_rtc_SyncAlarm(ADI_RTC_HANDLE const hDevice)
Sync after writing RTC alarm registers.
Definition: adi_rtc.c:2406
ADI_RTC_RESULT adi_rtc_SetTrim(ADI_RTC_HANDLE const hDevice, ADI_RTC_TRIM_INTERVAL eInterval, ADI_RTC_TRIM_VALUE eTrimValue, ADI_RTC_TRIM_POLARITY eOperation)
Set a new RTC trim value.
Definition: adi_rtc.c:2805
ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount)
Get current RTC count value with fraction.
Definition: adi_rtc.c:1480
ADI_RTC_RESULT adi_rtc_Open(uint32_t DeviceNumber, void *pDeviceMemory, uint32_t MemorySize, ADI_RTC_HANDLE *phDevice)
RTC Initialization.
Definition: adi_rtc.c:301
#define ADI_RTC_INPUT_CAPTURE_CH2_INT
Definition: adi_rtc.h:149
#define ADI_RTC_IRQ_SOURCE_MASK_SR3
Definition: adi_rtc.h:95
ADI_RTC_WRITE_STATUS
Definition: adi_rtc.h:181
ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const hDevice, uint8_t nPreScale)
Set Prescale. This is power of 2 division factor for the RTC base clock.
Definition: adi_rtc.c:2442
#define ADI_RTC1_IRQ_SOURCE_MASK_SR2
Definition: adi_rtc.h:88
ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable MOD60 RTC alarm.
Definition: adi_rtc.c:524
#define ADI_RTC_MOD60ALM_INT
Definition: adi_rtc.h:137
ADI_RTC_RESULT adi_rtc_GetAlarmEx(ADI_RTC_HANDLE hDevice, float *pAlarm)
Get current RTC alarm value with fractional part also.
Definition: adi_rtc.c:1304
ADI_RTC_RESULT adi_rtc_EnableTrim(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable RTC automatic clock trimming.
Definition: adi_rtc.c:745
#define ADI_RTC_COUNT_INT
Definition: adi_rtc.h:142
ADI_RTC_RESULT adi_rtc_GetAlarmRegs(ADI_RTC_HANDLE hDevice, uint16_t *pAlarm0, uint16_t *pAlarm1, uint16_t *pAlarm2)
Get current RTC alarm value from RTC Alarm register.
Definition: adi_rtc.c:1352
ADI_RTC_RESULT adi_rtc_RegisterCallback(ADI_RTC_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBparam)
Registers a Callback function with the RTC device driver. The registered call back function will be c...
Definition: adi_rtc.c:2653
ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
Set input capture polarity for the specified channel.
Definition: adi_rtc.c:884
#define ADI_RTC_INPUT_CAPTURE_CH3_INT
Definition: adi_rtc.h:150
#define ADI_RTC_NUM_INTERRUPTS
Definition: adi_rtc.h:174
ADI_RTC_RESULT adi_rtc_SetAlarmAsync(ADI_RTC_HANDLE const hDevice, uint32_t nAlarm)
Set a new RTC alarm value without waiting for synchronization.
Definition: adi_rtc.c:2307
ADI_RTC_RESULT adi_rtc_GetControl(ADI_RTC_HANDLE hDevice, ADI_RTC_CONTROL_REGISTER eRegister, uint32_t *pControl)
Get current RTC control register value.
Definition: adi_rtc.c:1396
#define ADI_RTC_IRQ_SOURCE_OFFSET_SR0
Definition: adi_rtc.h:77
#define ADI_RTC_WRITE_PENDERR_INT
Definition: adi_rtc.h:139
ADI_RTC_RESULT adi_rtc_EnableInputCapture(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
Enable input capture for the specified channel.
Definition: adi_rtc.c:791
ADI_RTC_RESULT adi_rtc_SetAlarmEx(ADI_RTC_HANDLE const hDevice, float fAlarm)
Set a new RTC alarm value with fractional value.
Definition: adi_rtc.c:2544
#define ADI_RTC_MOD60_ROLLOVER_INT
Definition: adi_rtc.h:146
ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable RTC device.
Definition: adi_rtc.c:586
ADI_RTC_RESULT adi_rtc_EnableAlarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable RTC alarm.
Definition: adi_rtc.c:461
ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint8_t nMask)
To set channel mask for the given Sensor Strobe channel.
Definition: adi_rtc.c:1193
ADI_RTC_RESULT adi_rtc_SetControlRegister(ADI_RTC_HANDLE const hDevice, ADI_RTC_CONTROL_REGISTER eRegister, uint32_t Control)
Set a new RTC control register value.
Definition: adi_rtc.c:2605
#define ADI_RTC_COUNT_ROLLOVER_INT
Definition: adi_rtc.h:145
ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice, ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction)
Read RTC snapshot registers values.
Definition: adi_rtc.c:2025
ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
Enable output for the specified Sensor Strobe Channel.
Definition: adi_rtc.c:931
ADI_RTC_TRIM_INTERVAL
Definition: adi_rtc.h:203
ADI_RTC_RESULT adi_rtc_EnableAutoReload(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
Enable auto reload for given Sensor Strobe Channel.
Definition: adi_rtc.c:978
ADI_RTC_RESULT adi_rtc_GetAlarm(ADI_RTC_HANDLE hDevice, uint32_t *pAlarm)
Get current RTC alarm value.
Definition: adi_rtc.c:1263
#define ADI_RTC_TRIM_INT
Definition: adi_rtc.h:144
ADI_RTC_RESULT
Definition: adi_rtc.h:103
ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
Enable or disable thermometer-code masking for the given Sensor Strobe Channel.
Definition: adi_rtc.c:1148
#define ADI_RTC_PSI_INT
Definition: adi_rtc.h:143
#define ADI_RTC_MEMORY_SIZE
Definition: adi_rtc.h:68
ADI_RTC_RESULT adi_rtc_GetWritePendStatus(ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pPendBits)
Get current RTC posted write pending status.
Definition: adi_rtc.c:2090
ADI_RTC_INPUT_CHANNEL
Definition: adi_rtc.h:243
ADI_RTC_TRIM_VALUE
Definition: adi_rtc.h:287
ADI_RTC_RESULT adi_rtc_SetCount(ADI_RTC_HANDLE const hDevice, uint32_t nCount)
Set a new RTC count value.
Definition: adi_rtc.c:2705
ADI_RTC_TRIM_POLARITY
Definition: adi_rtc.h:276
ADI_RTC_SS_CHANNEL
Definition: adi_rtc.h:259
ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(ADI_RTC_HANDLE const hDevice, uint8_t nPeriod)
Set the pre-scale. This is power of 2 division factor for the RTC base clock.
Definition: adi_rtc.c:2488
ADI_RTC_CONTROL_REGISTER
Definition: adi_rtc.h:310
ADI_RTC_RESULT adi_rtc_SetAlarmRegs(ADI_RTC_HANDLE const hDevice, uint16_t nAlarm0, uint16_t nAlarm1, uint16_t nAlarm2)
Set a new RTC alarm value for RTC ALM0,ALM1 and ALM2 Register.
Definition: adi_rtc.c:2251
ADI_RTC_RESULT adi_rtc_EnableInterrupts(ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Interrupts, bool bEnable)
Manage interrupt enable/disable in the RTC and NVIC controller.
Definition: adi_rtc.c:646
#define ADI_RTC_WRITE_SYNC_INT
Definition: adi_rtc.h:140
ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot(ADI_RTC_HANDLE const hDevice, bool bEnable)
Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels.
Definition: adi_rtc.c:837