ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
adi_rtc_config.h
1 
50 #ifndef ADI_RTC_CONFIG_H__
51 #define ADI_RTC_CONFIG_H__
52 #include <adi_global_config.h>
53 
65 #define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1
66 
67 
73 /*
74 ===================================================================
75  ------------------------RTC-0 CONFIGURATION MACRO-----------------
76 ===================================================================
77 */
79 #define RTC0_CFG_ENABLE_ALARM 0
80 
82 #define RTC0_CFG_ENABLE_ALARM_INTERRUPT 0
83 
85 #define RTC0_CFG_ENABLE_TRIM 0
86 
88 #define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT 0
89 
91 #define RTC0_CFG_ENABLE_WSYNC_INTERRUPT 0
92 
94 #define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT 0
95 
97 #define RTC0_CFG_COUNT_VALUE 0
98 
100 #define RTC0_CFG_COUNT_VALUE_0 0
101 
103 #define RTC0_CFG_COUNT_VALUE_1 0
104 
106 #define RTC0_CFG_ALARM_VALUE_0 0
107 
109 #define RTC0_CFG_ALARM_VALUE_1 0
110 
112 #define RTC0_CFG_TRIM_INTERVAL 0
113 
115 #define RTC0_CFG_POW2_TRIM_INTERVAL 0
116 
118 #define RTC0_CFG_TRIM_OPERATION 0
119 
121 #define RTC0_CFG_TRIM_VALUE 0
122 
131 #define RTC0_SS3_SMPONRE 0
132 
141 #define RTC0_SS3_SMPONFE 0
142 
143 #define RTC0_SS2_SMPONFE 0
144 
145 #define RTC0_SS1_SMPONRE 0
146 
147 #define RTC0_SS1_SMPONFE 0
148 
149 
156 #define RTC0_SS2_GPIN1SEL 0x4
157 
158 #define RTC0_SS2_GPIN0SEL 0x3
159 
160 #define RTC0_SS1_GPIN2SEL 0x2
161 
162 #define RTC0_SS1_GPIN1SEL 0x1
163 
164 #define RTC0_SS1_GPIN0SEL 0x0
165 
166 #define RTC0_SS3_GPIN2SEL 0x0
167 
168 #define RTC0_SS3_GPIN1SEL 0x7
169 
170 #define RTC0_SS3_GPIN0SEL 0x6
171 
172 #define RTC0_SS2_GPIN2SEL 0x5
173 
179 #define RTC0_SS3_DIFFOUT 0
180 
185 #define RTC0_SS1_DIFFOUT 0
186 
187 
188 
191 /*
192 ===================================================================
193  ------------------------RTC-1 CONFIGURATION MACRO-----------------
194 ===================================================================
195 */
196 
205 #define RTC1_CFG_ENABLE_ALARM 0
206 
208 #define RTC1_CFG_ENABLE_ALARM_INTERRUPT 0
209 
211 #define RTC1_CFG_ENABLE_TRIM 0
212 
214 #define RTC1_CFG_ENABLE_MOD60_ALARM 0
215 
217 #define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD 0
218 
220 #define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT 0
221 
223 #define RTC1_CFG_ENABLE_ISO_INTERRUPT 0
224 
226 #define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT 0
227 
229 #define RTC1_CFG_ENABLE_WSYNC_INTERRUPT 0
230 
232 #define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT 0
233 
235 #define RTC1_CFG_ENABLE_COUNT_INTERRUPT 0
236 
238 #define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT 0
239 
241 #define RTC1_CFG_ENABLE_TRIM_INTERRUPT 0
242 
244 #define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT 0
245 
247 #define RTC1_CFG_PRESCALE 0
248 
250 #define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT 0
251 
253 #define RTC1_CFG_COUNT_VALUE_0 0
254 
256 #define RTC1_CFG_COUNT_VALUE_1 0
257 
259 #define RTC1_CFG_ALARM_VALUE_0 0
260 
262 #define RTC1_CFG_ALARM_VALUE_1 0
263 
265 #define RTC1_CFG_ALARM_VALUE_2 0
266 
268 #define RTC1_CFG_TRIM_INTERVAL 0
269 
271 #define RTC1_CFG_POW2_TRIM_INTERVAL 0
272 
274 #define RTC1_CFG_TRIM_OPERATION 0
275 
277 #define RTC1_CFG_TRIM_VALUE 0
278 
280 #define RTC1_CFG_IC0_ENABLE 0
281 
283 #define RTC1_CFG_IC2_ENABLE 0
284 
286 #define RTC1_CFG_IC3_ENABLE 0
287 
289 #define RTC1_CFG_IC4_ENABLE 0
290 
292 #define RTC1_CFG_SS1_ENABLE 0
293 
294 #define RTC1_CFG_SS2_ENABLE 0
295 
296 #define RTC1_CFG_SS3_ENABLE 0
297 
298 #define RTC1_CFG_SS4_ENABLE 0
299 
301 #define RTC1_CFG_IC0_INT_ENABLE 0
302 
304 #define RTC1_CFG_IC2_INT_ENABLE 0
305 
307 #define RTC1_CFG_IC3_INT_ENABLE 0
308 
310 #define RTC1_CFG_IC4_INT_ENABLE 0
311 
313 #define RTC1_CFG_IC_OVER_WRITE_ENABLE 0
314 
316 #define RTC1_CFG_IC0_EDGE_POLARITY 0
317 
319 #define RTC1_CFG_IC2_EDGE_POLARITY 0
320 
322 #define RTC1_CFG_IC3_EDGE_POLARITY 0
323 
325 #define RTC1_CFG_IC4_EDGE_POLARITY 0
326 
328 #define RTC1_CFG_SS1_INT_ENABLE 0
329 
330 #define RTC1_CFG_SS2_INT_ENABLE 0
331 
332 #define RTC1_CFG_SS3_INT_ENABLE 0
333 
334 #define RTC1_CFG_SS4_INT_ENABLE 0
335 
337 #define RTC1_CFG_SS1_MASK_ENABLE 0
338 
339 #define RTC1_CFG_SS2_MASK_ENABLE 0
340 
341 #define RTC1_CFG_SS3_MASK_ENABLE 0
342 
343 #define RTC1_CFG_SS4_MASK_ENABLE 0
344 
346 #define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE 0
347 
349 #if defined(__ADUCM4x50__)
350 #define RTC1_CFG_SS2_AUTO_RELOADING_ENABLE 0
351 #define RTC1_CFG_SS3_AUTO_RELOADING_ENABLE 0
352 #endif
353 
355 #define RTC1_CFG_SS1_MASK_VALUE 0
356 
358 #if defined(__ADUCM4x50__)
359 #define RTC1_CFG_SS2_MASK_VALUE 0
360 #define RTC1_CFG_SS3_MASK_VALUE 0
361 #define RTC1_CFG_SS4_MASK_VALUE 0
362 #endif
363 
365 #if defined(__ADUCM302x__)
366 #define RTC1_CFG_SS1_AUTO_RELOAD_VALUE 32768/2
367 #endif
368 
369 /*value for Sensor Strobe channel 1*/
370 #define RTC_CFG_SS1_VALUE 32768/2
371 
373 #if defined(__ADUCM4x50__)
374 #define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_HIGH 32768/2
375 #define RTC1_CFG_SS1_AUTO_RELOAD_VALUE_LOW 32768/2
376 
377 #define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_HIGH 32768/2
378 #define RTC1_CFG_SS2_AUTO_RELOAD_VALUE_LOW 32768/2
379 
380 #define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_HIGH 32768/2
381 #define RTC1_CFG_SS3_AUTO_RELOAD_VALUE_LOW 32768/2
382 #endif
383 
390 #define RTC1_SS2_GPIN1SEL 0x4
391 
392 #define RTC1_SS2_GPIN0SEL 0x3
393 
394 #define RTC1_SS1_GPIN2SEL 0x2
395 
396 #define RTC1_SS1_GPIN1SEL 0x1
397 
398 #define RTC1_SS1_GPIN0SEL 0x0
399 
400 #define RTC1_SS3_GPIN2SEL 0x0
401 
402 #define RTC1_SS3_GPIN1SEL 0x7
403 
404 #define RTC1_SS3_GPIN0SEL 0x6
405 
406 #define RTC1_SS2_GPIN2SEL 0x5
407 
413 #define RTC1_SS3_DIFFOUT 0
414 
419 #define RTC1_SS1_DIFFOUT 0
420 
422 #define RTC1_CFG_CR5SSS_OC1SMPEN 0
423 
425 #define RTC1_CFG_CR5SSS_OC1SMPMTCHIRQEN 0
426 
428 #define RTC1_CFG_CR5SSS_OC2SMPEN 0
429 
431 #define RTC1_CFG_CR5SSS_OC2SMPMTCHIRQEN 0
432 
434 #define RTC1_CFG_CR5SSS_OC3SMPEN 0
435 
437 #define RTC1_CFG_CR5SSS_OC3SMPMTCHIRQEN 0
438 
440 #define RTC1_CFG_CR6SSS_OC1SMPONFE 0
441 
443 #define RTC1_CFG_CR6SSS_OC1SMPONRE 0
444 
446 #define RTC1_CFG_CR6SSS_OC2SMPONFE 0
447 
449 #define RTC1_CFG_CR6SSS_OC2SMPONRE 0
450 
452 #define RTC1_CFG_CR6SSS_OC3SMPONFE 0
453 
455 #define RTC1_CFG_CR6SSS_OC3SMPONRE 0
456 
458 #define RTC1_CFG_CR7SSS_OC1SMPEXP 0
459 
461 #define RTC1_CFG_CR7SSS_OC1SMPPTRN 0
462 
464 #define RTC1_CFG_CR7SSS_OC2SMPEXP 0
465 
467 #define RTC1_CFG_CR7SSS_OC2SMPPTRN 0
468 
470 #define RTC1_CFG_CR7SSS_OC3SMPEXP 0
471 
473 #define RTC1_CFG_CR7SSS_OC3SMPPTRN 0
474 
476 #define RTC1_CFG_GPMUX0_OC1GPIN0SEL 0
477 
479 #define RTC1_CFG_GPMUX0_OC1GPIN1SEL 1
480 
482 #define RTC1_CFG_GPMUX0_OC1GPIN2SEL 2
483 
485 #define RTC1_CFG_GPMUX0_OC2GPIN0SEL 3
486 
488 #define RTC1_CFG_GPMUX0_OC2GPIN1SEL 4
489 
491 #define RTC1_CFG_GPMUX1_OC2GPIN2SEL 5
492 
494 #define RTC1_CFG_GPMUX1_OC3GPIN0SEL 6
495 
497 #define RTC1_CFG_GPMUX1_OC3GPIN1SEL 7
498 
500 #define RTC1_CFG_GPMUX1_OC3GPIN2SEL 0
501 
503 #define RTC1_CFG_GPMUX1_OC1DIFFOUT 0
504 
506 #define RTC1_CFG_GPMUX1_OC3DIFFOUT 0
507 
508 
512 #endif /* ADI_RTC_CONFIG_H__ */