ADuCM302x Device Drivers API Reference Manual  Release 3.1.2.0
Static Configuration

Macros

#define ADI_FEE_CFG_ECC_ERROR_RESPONSE   (1u)
 
#define ADI_FEE_CFG_PARAM0_TNVH1   (0xbu)
 
#define ADI_FEE_CFG_PARAM0_TERASE   (0x9u)
 
#define ADI_FEE_CFG_PARAM0_TRCV   (0x9u)
 
#define ADI_FEE_CFG_PARAM0_TNVH   (0x5u)
 
#define ADI_FEE_CFG_PARAM0_TPROG   (0x5u)
 
#define ADI_FEE_CFG_PARAM0_TPGS   (0x9u)
 
#define ADI_FEE_CFG_PARAM0_TNVS   (0x5u)
 
#define ADI_FEE_CFG_PARAM0_CLKDIV   (0x0u)
 
#define ADI_FEE_CFG_PARAM1_TWK   (0x4u)
 
#define ADI_FEE_CFG_ABORT_EN_LO   (0x0u)
 
#define ADI_FEE_CFG_ABORT_EN_HI   (0x0u)
 
#define ADI_FEE_CFG_ECC_START_PAGE   (0u)
 
#define ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE   (1u)
 
#define ADI_FEE_CFG_ENABLE_ECC   (1u)
 

Detailed Description

Macro Definition Documentation

◆ ADI_FEE_CFG_ECC_ERROR_RESPONSE

#define ADI_FEE_CFG_ECC_ERROR_RESPONSE   (1u)

Configure a response to the 2-bit ECC ERROR events (in IEN).

  • 0 Do not generate a response to ECC Error Events.
  • 1 Generate Bus Errors in response to ECC Error Events.
  • 2 Generate IRQs in response to ECC Error Events.

Definition at line 69 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_TNVH1

#define ADI_FEE_CFG_PARAM0_TNVH1   (0xbu)

Configure a response to the 1-bit ECC CORRECTION events (in IEN).

  • 0 Do not generate a response to ECC correction Events.
  • 1 Generate Bus Errors in response to ECC correction Events.
  • 2 Generate IRQs in response to ECC correction Events.

Configure flash non-volatile mass erase hold time.
Upper 4-bits of 11-bit value.
(Lower bits are hard-coded to 0x14.)
Hardware default value is 0xb.

Definition at line 92 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_TERASE

#define ADI_FEE_CFG_PARAM0_TERASE   (0x9u)

Configure flash erase time.
Upper 4-bits of 19-bit value.
(Lower bits are hard-coded to 0x7370.)
Hardware default value is 0x8.

Definition at line 100 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_TRCV

#define ADI_FEE_CFG_PARAM0_TRCV   (0x9u)

Configure flash recovery time.
Upper 4-bits of 8-bit value.
(Lower bits are hard-coded to 0x2.)
Hardware default value is 0x9.

Definition at line 108 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_TNVH

#define ADI_FEE_CFG_PARAM0_TNVH   (0x5u)

Configure flash non-volatile hold time.
Upper 4-bits of 8-bit value.
(Lower bits are hard-coded to 0x1.)
Hardware default value is 0x5.

Definition at line 116 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_TPROG

#define ADI_FEE_CFG_PARAM0_TPROG   (0x5u)

Configure flash program time.
Upper 4-bits of 10-bit value.
(Lower bits are hard-coded to 0x7.)
Hardware default value is 0x0.

Definition at line 125 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_TPGS

#define ADI_FEE_CFG_PARAM0_TPGS   (0x9u)

Configure flash NVSTR-to-program setup time.
Upper 4-bits of 8-bit value.
(Lower bits are hard-coded to 0x2.)
Hardware default value is 0x9.

Definition at line 137 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_TNVS

#define ADI_FEE_CFG_PARAM0_TNVS   (0x5u)

Configure flash program/erase-to-NVSTR setup time.
Upper 4-bits of 8-bit value.
(Lower bits are hard-coded to 0x1.)
Hardware default value is 0x5.

Definition at line 145 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM0_CLKDIV

#define ADI_FEE_CFG_PARAM0_CLKDIV   (0x0u)

Configure flash reference clock divide-by-2 setting.
All timing parameters are referenced to this parameter.

  • 0 Reference clock is not divided.
  • 1 Reference clock is divided by 2.
    Hardware default value is 0x0.

Definition at line 154 of file adi_flash_config.h.

◆ ADI_FEE_CFG_PARAM1_TWK

#define ADI_FEE_CFG_PARAM1_TWK   (0x4u)

Configure flash read access wait states.
Number of 3-bit read access wait states to use.
Maximum allowed value is 0x4.
Hardware default value is 0x0.

Configure flash sleep mode wake-up time.
Upper 4-bits of 8-bit value.
(Lower bits are hard-coded to 0xb.)
Hardware default value is 0x4.

Definition at line 177 of file adi_flash_config.h.

◆ ADI_FEE_CFG_ABORT_EN_LO

#define ADI_FEE_CFG_ABORT_EN_LO   (0x0u)

Configure lower (0-31) flash system interrupt abort enables.
Allows system interrupts to abort an ongoing flash command.
Only 64 system interrupts are supported.
Lower interrupts (0-31) are encoded in ADI_FEE_CFG_ABORT_EN_LO,

  • 0 Corresponding interrupt is prevented from aborting flash command.
  • 1 Corresponding interrupt is allowed to abort flash command.
    Hardware default value is 0x0.

Definition at line 193 of file adi_flash_config.h.

◆ ADI_FEE_CFG_ABORT_EN_HI

#define ADI_FEE_CFG_ABORT_EN_HI   (0x0u)

Configure upper (32-63) flash system interrupt abort enables.
Allows system interrupts to abort an ongoing flash command.
Only 64 system interrupts are supported.
Upper interrupts (32-63) are encoded in ADI_FEE_CFG_ABORT_EN_HI.

  • 0 Corresponding interrupt is prevented from aborting flash command.
  • 1 Corresponding interrupt is allowed to abort flash command.
    Hardware default value is 0x0.

Definition at line 204 of file adi_flash_config.h.

◆ ADI_FEE_CFG_ECC_START_PAGE

#define ADI_FEE_CFG_ECC_START_PAGE   (0u)

ECC Start Page Pointer (in ECC_CFG).

Definition at line 214 of file adi_flash_config.h.

◆ ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE

#define ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE   (1u)

Enable/Disable ECC for info space (in ECC_CFG).

  • 1 Enable Info Space.
  • 0 Disable Info Space.

Definition at line 221 of file adi_flash_config.h.

◆ ADI_FEE_CFG_ENABLE_ECC

#define ADI_FEE_CFG_ENABLE_ECC   (1u)

Enable/Disable ECC (in ECC_CFG).

  • 1 Enable ECC.
  • 0 Disable ECC.

Definition at line 228 of file adi_flash_config.h.