93 denominator = baudrate;
95 bdr = numerator / n / denominator - 1;
97 USART1x->BDR = ( uint16_t )( bdr & 0xffff );
115 if( USART1x == NULL )
121 if( USART1x == ( USART1n_Type* )USART10 )
130 if( USART1x == ( USART1n_Type* )USART11 )
138 #if 0 // not supported 139 if( USART1x == ( USART1n_Type* )USART12 )
147 #if 0 // not supported 148 if( USART1x == ( USART1n_Type* )USART13 )
161 | ( ( USART1n_Config->
Mode & 0x3 ) << USART1n_CR1_USTnMS_Pos )
162 | ( ( USART1n_Config->
Parity & 0x3 ) << USART1n_CR1_USTnP_Pos )
163 | ( ( USART1n_Config->
Databits & 0x7 ) << USART1n_CR1_USTnS_Pos )
164 | ( ( USART1n_Config->
Order & 0x1 ) << USART1n_CR1_ORDn_Pos )
165 | ( ( USART1n_Config->
ACK & 0x1 ) << USART1n_CR1_CPOLn_Pos )
166 | ( ( USART1n_Config->
Edge & 0x3 ) << USART1n_CR1_CPHAn_Pos )
167 | ( 1 << USART1n_CR1_TXEn_Pos )
168 | ( 1 << USART1n_CR1_RXEn_Pos )
173 USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnSB_Pos );
174 USART1x->CR2 |= ( ( USART1n_Config->
Stopbits & 0x1 ) << USART1n_CR2_USTnSB_Pos );
175 USART1x->CR2 &= ~( 1 << USART1n_CR2_FXCHn_Pos );
198 if( USART1x == NULL )
204 if( USART1x == ( USART1n_Type* )USART10 )
213 if( USART1x == ( USART1n_Type* )USART11 )
221 #if 0 // not supported 222 if( USART1x == ( USART1n_Type* )USART12 )
230 #if 0 // not supported 231 if( USART1x == ( USART1n_Type* )USART13 )
255 if( USART1n_Config == NULL )
282 if( USART1n_Config == NULL )
296 #if 0 // CPOLn : 0, CPHAn : 0 (X) 301 #if 1 // CPOLn : 0, CPHAn : 1 (O) 306 #if 0 // CPOLn : 1, CPHAn : 0 (X) 311 #if 0 // CPOLn : 1, CPHAn : 1 (O) 332 if( USART1n_Config == NULL )
346 #if 1 // CPOLn : 0, CPHAn : 0 (X) 351 #if 0 // CPOLn : 0, CPHAn : 1 (O) 356 #if 0 // CPOLn : 1, CPHAn : 0 (X) 361 #if 0 // CPOLn : 1, CPHAn : 1 (O) 390 if( USART1x == NULL )
395 switch( USART1n_IntCfg )
398 tmp = USART1n_IER_WAKEINT_EN;
401 tmp = USART1n_IER_RXCINT_EN;
404 tmp = USART1n_IER_TXCINT_EN;
407 tmp = USART1n_IER_DR_EN;
417 USART1x->CR1 &= ~( tmp & USART1n_IER_BITMASK );
450 if( USART1x == NULL )
458 tmp = USART1n_CR2_USTnRX8;
461 tmp = USART1n_CR2_USTnTX8;
464 tmp = USART1n_CR2_USTnSB;
467 tmp = USART1n_CR2_FXCHn;
470 tmp = USART1n_CR2_USTnSSEN;
473 tmp = USART1n_CR2_DISSCKn;
476 tmp = USART1n_CR2_LOOPSn;
479 tmp = USART1n_CR2_MASTERn;
482 tmp = USART1n_CR2_DBLSn;
485 tmp = USART1n_CR2_USTnEN;
497 USART1x->CR2 &= ~( tmp & USART1n_CR2_BITMASK );
515 if( USART1x == NULL )
522 USART1x->CR2 |= ( 1 << USART1n_CR2_USTnEN_Pos );
526 USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnEN_Pos );
545 if( USART1x == NULL )
553 tmp = USART1n_SR_WAKE;
556 tmp = USART1n_SR_RXC;
559 tmp = USART1n_SR_TXC;
562 tmp = USART1n_SR_DRE;
582 return ( ( USART1x->ST ) & USART1n_SR_BITMASK );
594 if( USART1x->ST & USART1n_SR_DRE )
616 if( USART1x == NULL )
657 uint32_t bToSend, bSent, timeOut;
658 uint8_t* pChar = txbuf;
673 timeOut = USART1n_BLOCKING_TIMEOUT;
674 while( !( USART1x->ST & USART1n_SR_TXC ) )
704 if( !( USART1x->ST & USART1n_SR_DRE ) )
741 uint32_t bToRecv, bRecv, timeOut;
742 uint8_t* pChar = rxbuf;
754 timeOut = USART1n_BLOCKING_TIMEOUT;
755 while( !( USART1x->ST & USART1n_SR_RXC ) )
785 if( !( USART1x->ST & USART1n_SR_RXC ) )
uint8_t HAL_USART_GetStatus(USART1n_Type *USART1x)
Get current value of Line Status register in USART peripheral.
HAL_Status_Type HAL_USART_DeInit(USART1n_Type *USART1x)
Deinitialize the USART1n peripheral registers to their default reset values.
static void usart_set_divisors(USART1n_Type *USART1x, uint32_t mode, uint32_t baudrate)
Determines best dividers to get a target clock rate.
HAL_Status_Type HAL_USART_UART_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
USART1n_PARITY_BIT_Type Parity
uint32_t USART1n_BaseClock
USART1n_SPI_ORDER_Type Order
FlagStatus HAL_USART_CheckBusy(USART1n_Type *USART1x)
Check whether if USART is busy or not.
HAL_Status_Type HAL_USART_SPI_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
Contains all macro definitions and function prototypes support for scu firmware library on A31R71x.
HAL_Status_Type HAL_USART_DataControlConfig(USART1n_Type *USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState)
Configure Data Control mode for USART peripheral.
HAL_Status_Type HAL_USART_TransmitByte(USART1n_Type *USART1x, uint8_t Data)
Transmit a single data through USART peripheral.
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.
USART1n_DATA_BIT_Type Databits
HAL_Status_Type HAL_USART_USRT_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
uint32_t HAL_USART_Transmit(USART1n_Type *USART1x, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Send a block of data via USART peripheral.
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.
USART1n_STOP_BIT_Type Stopbits
Contains all macro definitions and function prototypes support for usart1n firmware library on A31R71...
HAL_Status_Type HAL_USART_Init(USART1n_Type *USART1x, USART1n_CFG_Type *USART1n_Config)
Initialize the USART1n peripheral with the specified parameters.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_USART_Enable(USART1n_Type *USART1x, FunctionalState state)
USART1n enable control.
uint32_t HAL_USART_Receive(USART1n_Type *USART1x, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Receive a block of data via USART peripheral.
HAL_Status_Type HAL_USART_ConfigInterrupt(USART1n_Type *USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState)
Configure the interrupt source of selected USART1n peripheral.