A31R71x F/W Packages  1.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31R71x_hal_usart1n.c
Go to the documentation of this file.
1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31R71x_hal_scu.h"
41 #include "A31R71x_hal_usart1n.h"
42 
43 //******************************************************************************
44 // Variable
45 //******************************************************************************
46 
48 
49 /* Public Functions --------------------------------------------------------- */
50 //******************************************************************************
51 // Function
52 //******************************************************************************
53 
54 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
67 static void usart_set_divisors( USART1n_Type* USART1x, uint32_t mode, uint32_t baudrate )
68 {
69  uint32_t numerator;
70  uint32_t denominator;
71  uint32_t n;
72  uint32_t bdr;
73 
74  if( mode == USART1n_UART_MODE )
75  {
76  // baudrate = PCLK / (16 * (bdr + 1))
77  // bdr = (PCLK / (16 * baudrate)) - 1
78  n = 16;
79  }
80  else
81  {
82  // baudrate = PCLK / (2 * (bdr + 1))
83  // bdr = (PCLK / (2 * baudrate)) - 1
84  n = 2;
85  }
86 
87  //--------------------------------------
88  // numerator & denominator
89  //
90  // bdr = USART1n_BaseClock / n / baudrate - 1
91  //--------------------------------------
92  numerator = USART1n_BaseClock;
93  denominator = baudrate;
94 
95  bdr = numerator / n / denominator - 1;
96 
97  USART1x->BDR = ( uint16_t )( bdr & 0xffff );
98 }
99 
100 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
110 HAL_Status_Type HAL_USART_Init( USART1n_Type* USART1x, USART1n_CFG_Type* USART1n_Config )
111 {
112  uint32_t tmp;
113 
114  /* Check USART handle */
115  if( USART1x == NULL )
116  {
117  return HAL_ERROR;
118  }
119 
120 #if 1 // supported
121  if( USART1x == ( USART1n_Type* )USART10 )
122  {
123  // Set up peripheral clock for USART10 module
124  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Enable );
126  }
127 #endif
128 
129 #if 1 // supported
130  if( USART1x == ( USART1n_Type* )USART11 )
131  {
132  // Set up peripheral clock for USART11 module
133  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Enable );
135  }
136 #endif
137 
138 #if 0 // not supported
139  if( USART1x == ( USART1n_Type* )USART12 )
140  {
141  // Set up peripheral clock for USART12 module
142  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Enable );
144  }
145 #endif
146 
147 #if 0 // not supported
148  if( USART1x == ( USART1n_Type* )USART13 )
149  {
150  // Set up peripheral clock for USART13 module
151  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Enable );
153  }
154 #endif
155 
156  USART1n_BaseClock = SystemPeriClock;
157 
158  usart_set_divisors( USART1x, USART1n_Config->Mode, USART1n_Config->Baudrate );
159 
160  tmp = 0
161  | ( ( USART1n_Config->Mode & 0x3 ) << USART1n_CR1_USTnMS_Pos )
162  | ( ( USART1n_Config->Parity & 0x3 ) << USART1n_CR1_USTnP_Pos )
163  | ( ( USART1n_Config->Databits & 0x7 ) << USART1n_CR1_USTnS_Pos )
164  | ( ( USART1n_Config->Order & 0x1 ) << USART1n_CR1_ORDn_Pos )
165  | ( ( USART1n_Config->ACK & 0x1 ) << USART1n_CR1_CPOLn_Pos )
166  | ( ( USART1n_Config->Edge & 0x3 ) << USART1n_CR1_CPHAn_Pos )
167  | ( 1 << USART1n_CR1_TXEn_Pos ) // Tx Enable
168  | ( 1 << USART1n_CR1_RXEn_Pos ) // Rx Enable
169  ;
170 
171  USART1x->CR1 = tmp;
172 
173  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnSB_Pos ); // USTnSB reset
174  USART1x->CR2 |= ( ( USART1n_Config->Stopbits & 0x1 ) << USART1n_CR2_USTnSB_Pos ); // USTnSB
175  USART1x->CR2 &= ~( 1 << USART1n_CR2_FXCHn_Pos ); // FXCHn reset
176  //USART1x->CR2 |= (1<<USART1n_CR2_FXCHn_Pos); // FXCHn
177 
179 
180  // dummy read
181  HAL_USART_ReceiveByte( USART1x );
182  HAL_USART_ReceiveByte( USART1x );
183 
184  return HAL_OK;
185 }
186 
187 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
195 HAL_Status_Type HAL_USART_DeInit( USART1n_Type* USART1x )
196 {
197  /* Check USART handle */
198  if( USART1x == NULL )
199  {
200  return HAL_ERROR;
201  }
202 
203 #if 1 // supported
204  if( USART1x == ( USART1n_Type* )USART10 )
205  {
206  // Set up peripheral clock for USART10 module
208  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Disable );
209  }
210 #endif
211 
212 #if 1 // supported
213  if( USART1x == ( USART1n_Type* )USART11 )
214  {
215  // Set up peripheral clock for USART11 module
217  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Disable );
218  }
219 #endif
220 
221 #if 0 // not supported
222  if( USART1x == ( USART1n_Type* )USART12 )
223  {
224  // Set up peripheral clock for USART12 module
226  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Disable );
227  }
228 #endif
229 
230 #if 0 // not supported
231  if( USART1x == ( USART1n_Type* )USART13 )
232  {
233  // Set up peripheral clock for USART13 module
235  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Disable );
236  }
237 #endif
238 
239  return HAL_OK;
240 }
241 
242 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
253 {
254  /* Check USART1n_Config */
255  if( USART1n_Config == NULL )
256  {
257  return HAL_ERROR;
258  }
259 
260  USART1n_Config->Mode = USART1n_UART_MODE;
261  USART1n_Config->Baudrate = 38400;
262  USART1n_Config->Databits = USART1n_DATA_BIT_8;
263  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
264  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
265 
266  return HAL_OK;
267 }
268 
269 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
280 {
281  /* Check USART1n_Config */
282  if( USART1n_Config == NULL )
283  {
284  return HAL_ERROR;
285  }
286 
287  USART1n_Config->Mode = USART1n_USRT_MODE;
288  USART1n_Config->Baudrate = 38400;
289  USART1n_Config->Databits = USART1n_DATA_BIT_8;
290  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
291  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
292 
293  // only SPI & Sync. Mode
294  USART1n_Config->Order = USART1n_SPI_LSB;
295 
296 #if 0 // CPOLn : 0, CPHAn : 0 (X)
297  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
298  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
299 #endif
300 
301 #if 1 // CPOLn : 0, CPHAn : 1 (O)
302  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
303  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
304 #endif
305 
306 #if 0 // CPOLn : 1, CPHAn : 0 (X)
307  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
308  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
309 #endif
310 
311 #if 0 // CPOLn : 1, CPHAn : 1 (O)
312  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
313  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
314 #endif
315 
316  return HAL_OK;
317 }
318 
319 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
330 {
331  /* Check USART1n_Config */
332  if( USART1n_Config == NULL )
333  {
334  return HAL_ERROR;
335  }
336 
337  USART1n_Config->Mode = USART1n_SPI_MODE;
338  USART1n_Config->Baudrate = 38400;
339  USART1n_Config->Databits = USART1n_DATA_BIT_8;
340  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
341  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
342 
343  // only SPI & Sync. Mode
344  USART1n_Config->Order = USART1n_SPI_LSB;
345 
346 #if 1 // CPOLn : 0, CPHAn : 0 (X)
347  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
348  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
349 #endif
350 
351 #if 0 // CPOLn : 0, CPHAn : 1 (O)
352  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
353  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
354 #endif
355 
356 #if 0 // CPOLn : 1, CPHAn : 0 (X)
357  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
358  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
359 #endif
360 
361 #if 0 // CPOLn : 1, CPHAn : 1 (O)
362  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
363  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
364 #endif
365 
366  return HAL_OK;
367 }
368 
369 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
385 HAL_Status_Type HAL_USART_ConfigInterrupt( USART1n_Type* USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState )
386 {
387  uint32_t tmp = 0;
388 
389  /* Check USART handle */
390  if( USART1x == NULL )
391  {
392  return HAL_ERROR;
393  }
394 
395  switch( USART1n_IntCfg )
396  {
397  case USART1n_INTCFG_WAKE :
398  tmp = USART1n_IER_WAKEINT_EN;
399  break;
400  case USART1n_INTCFG_RXC:
401  tmp = USART1n_IER_RXCINT_EN;
402  break;
403  case USART1n_INTCFG_TXC:
404  tmp = USART1n_IER_TXCINT_EN;
405  break;
406  case USART1n_INTCFG_DR:
407  tmp = USART1n_IER_DR_EN;
408  break;
409  }
410 
411  if( NewState == ENABLE )
412  {
413  USART1x->CR1 |= tmp;
414  }
415  else
416  {
417  USART1x->CR1 &= ~( tmp & USART1n_IER_BITMASK );
418  }
419 
420  return HAL_OK;
421 }
422 
423 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
446 {
447  uint16_t tmp = 0;
448 
449  /* Check USART handle */
450  if( USART1x == NULL )
451  {
452  return HAL_ERROR;
453  }
454 
455  switch( Mode )
456  {
458  tmp = USART1n_CR2_USTnRX8;
459  break;
461  tmp = USART1n_CR2_USTnTX8;
462  break;
464  tmp = USART1n_CR2_USTnSB;
465  break;
467  tmp = USART1n_CR2_FXCHn;
468  break;
470  tmp = USART1n_CR2_USTnSSEN;
471  break;
473  tmp = USART1n_CR2_DISSCKn;
474  break;
476  tmp = USART1n_CR2_LOOPSn;
477  break;
479  tmp = USART1n_CR2_MASTERn;
480  break;
482  tmp = USART1n_CR2_DBLSn;
483  break;
485  tmp = USART1n_CR2_USTnEN;
486  break;
487  default:
488  break;
489  }
490 
491  if( NewState == ENABLE )
492  {
493  USART1x->CR2 |= tmp;
494  }
495  else
496  {
497  USART1x->CR2 &= ~( tmp & USART1n_CR2_BITMASK );
498  }
499 
500  return HAL_OK;
501 }
502 
503 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
512 HAL_Status_Type HAL_USART_Enable( USART1n_Type* USART1x, FunctionalState state )
513 {
514  /* Check USART handle */
515  if( USART1x == NULL )
516  {
517  return HAL_ERROR;
518  }
519 
520  if( state == ENABLE )
521  {
522  USART1x->CR2 |= ( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
523  }
524  else
525  {
526  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
527  }
528 
529  return HAL_OK;
530 }
531 
532 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
541 {
542  uint32_t tmp;
543 
544  /* Check USART handle */
545  if( USART1x == NULL )
546  {
547  return HAL_ERROR;
548  }
549 
550  switch( Status )
551  {
552  case USART1n_STATUS_WAKE:
553  tmp = USART1n_SR_WAKE;
554  break;
555  case USART1n_STATUS_RXC:
556  tmp = USART1n_SR_RXC;
557  break;
558  case USART1n_STATUS_TXC:
559  tmp = USART1n_SR_TXC;
560  break;
561  case USART1n_STATUS_DRE:
562  tmp = USART1n_SR_DRE;
563  break;
564  default:
565  return HAL_ERROR;
566  }
567 
568  USART1x->ST = tmp;
569 
570  return HAL_OK;
571 }
572 
573 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
580 uint8_t HAL_USART_GetStatus( USART1n_Type* USART1x )
581 {
582  return ( ( USART1x->ST ) & USART1n_SR_BITMASK );
583 }
584 
585 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
592 FlagStatus HAL_USART_CheckBusy( USART1n_Type* USART1x )
593 {
594  if( USART1x->ST & USART1n_SR_DRE )
595  {
596  return RESET;
597  }
598  else
599  {
600  return SET;
601  }
602 }
603 
604 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
613 HAL_Status_Type HAL_USART_TransmitByte( USART1n_Type* USART1x, uint8_t Data )
614 {
615  /* Check USART handle */
616  if( USART1x == NULL )
617  {
618  return HAL_ERROR;
619  }
620 
621  USART1x->DR = Data;
622 
623  return HAL_OK;
624 }
625 
626 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
633 uint8_t HAL_USART_ReceiveByte( USART1n_Type* USART1x )
634 {
635  return USART1x->DR;
636 }
637 
638 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
655 uint32_t HAL_USART_Transmit( USART1n_Type* USART1x, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
656 {
657  uint32_t bToSend, bSent, timeOut;
658  uint8_t* pChar = txbuf;
659 
660  // init counter
661  bToSend = buflen;
662  bSent = 0;
663 
664  // Blocking Mode
665  if( flag == BLOCKING )
666  {
667  while( bToSend )
668  {
669  // send byte
670  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
671 
672  // wait until tx data register is empty with timeout
673  timeOut = USART1n_BLOCKING_TIMEOUT;
674  while( !( USART1x->ST & USART1n_SR_TXC ) )
675  {
676  if( timeOut == 0 )
677  {
678  break;
679  }
680  timeOut--;
681  }
682 
683  // if timeout
684  if( timeOut == 0 )
685  {
686  break;
687  }
688 
689  // clear flag
691 
692  // update counter
693  bToSend--;
694  bSent++;
695  }
696  }
697 
698  // Non-Blocking Mode
699  else
700  {
701  while( bToSend )
702  {
703  // if tx data register is not empty
704  if( !( USART1x->ST & USART1n_SR_DRE ) )
705  {
706  break;
707  }
708 
709  // send byte
710  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
711 
712  // update counter
713  bToSend--;
714  bSent++;
715  }
716  }
717 
718  // return
719  return bSent;
720 }
721 
722 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
739 uint32_t HAL_USART_Receive( USART1n_Type* USART1x, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
740 {
741  uint32_t bToRecv, bRecv, timeOut;
742  uint8_t* pChar = rxbuf;
743 
744  // init counter
745  bToRecv = buflen;
746  bRecv = 0;
747 
748  // Blocking Mode
749  if( flag == BLOCKING )
750  {
751  while( bToRecv )
752  {
753  // wait until data are received with timeout
754  timeOut = USART1n_BLOCKING_TIMEOUT;
755  while( !( USART1x->ST & USART1n_SR_RXC ) )
756  {
757  if( timeOut == 0 )
758  {
759  break;
760  }
761  timeOut--;
762  }
763 
764  // if timeout
765  if( timeOut == 0 )
766  {
767  break;
768  }
769 
770  // receive byte
771  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
772 
773  // update counter
774  bToRecv--;
775  bRecv++;
776  }
777  }
778 
779  // Non-Blocking Mode
780  else
781  {
782  while( bToRecv )
783  {
784  // if no data were received
785  if( !( USART1x->ST & USART1n_SR_RXC ) )
786  {
787  break;
788  }
789 
790  // receive byte
791  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
792 
793  // update counter
794  bToRecv--;
795  bRecv++;
796  }
797  }
798 
799  // return
800  return bRecv;
801 }
802 
HAL_Status_Type
uint8_t HAL_USART_GetStatus(USART1n_Type *USART1x)
Get current value of Line Status register in USART peripheral.
HAL_Status_Type HAL_USART_DeInit(USART1n_Type *USART1x)
Deinitialize the USART1n peripheral registers to their default reset values.
static void usart_set_divisors(USART1n_Type *USART1x, uint32_t mode, uint32_t baudrate)
Determines best dividers to get a target clock rate.
HAL_Status_Type HAL_USART_UART_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
USART1n_EDGE_Type Edge
FunctionalState
USART1n_PARITY_BIT_Type Parity
uint32_t USART1n_BaseClock
USART1n_SPI_ORDER_Type Order
FlagStatus HAL_USART_CheckBusy(USART1n_Type *USART1x)
Check whether if USART is busy or not.
HAL_Status_Type HAL_USART_SPI_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
Contains all macro definitions and function prototypes support for scu firmware library on A31R71x.
USART1n_OPMODE_Type Mode
HAL_Status_Type HAL_USART_DataControlConfig(USART1n_Type *USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState)
Configure Data Control mode for USART peripheral.
USART1n_INT_Type
USART1n_CONTROL_Type
HAL_Status_Type HAL_USART_TransmitByte(USART1n_Type *USART1x, uint8_t Data)
Transmit a single data through USART peripheral.
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
HAL_Status_Type HAL_USART_USRT_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
uint32_t HAL_USART_Transmit(USART1n_Type *USART1x, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Send a block of data via USART peripheral.
USART1n_STATUS_Type
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.
USART1n_STOP_BIT_Type Stopbits
Contains all macro definitions and function prototypes support for usart1n firmware library on A31R71...
HAL_Status_Type HAL_USART_Init(USART1n_Type *USART1x, USART1n_CFG_Type *USART1n_Config)
Initialize the USART1n peripheral with the specified parameters.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_USART_Enable(USART1n_Type *USART1x, FunctionalState state)
USART1n enable control.
uint32_t HAL_USART_Receive(USART1n_Type *USART1x, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Receive a block of data via USART peripheral.
TRANSFER_BLOCK_Type
HAL_Status_Type HAL_USART_ConfigInterrupt(USART1n_Type *USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState)
Configure the interrupt source of selected USART1n peripheral.