A31R71x F/W Packages  1.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
Functions
A31R71x_hal_scu.h File Reference

Contains all macro definitions and function prototypes support for scu firmware library on A31R71x. More...

Go to the source code of this file.

Functions

uint32_t HAL_SCU_ResetSourceStatus (void)
 Get Reset Source Status. More...
 
void HAL_SCU_SetNMI (uint32_t u32NmiCon)
 Set Non-Maskable Interrupt(NMI) Source Selection Register. More...
 
void HAL_SCU_SoftwareReset_Config (void)
 Check whether system reset ok or not. Generate s/w reset if a weak reset. More...
 
void HAL_SCU_SetWakupData (uint32_t u32Data)
 Set Wake-Up Timer Data. More...
 
void HAL_SCU_HIRCTRM_ClockConfig (uint32_t u32Ind)
 Change fine trim value of HIRC by one step. More...
 
void HAL_SCU_WDTRCTRM_ClockConfig (uint32_t u32Ind)
 Change fine trim value of WDTRC by one step. More...
 
void HAL_SCU_ClockMonitoring (uint32_t u32Acts, uint32_t u32Target)
 Configure Clock Monitoring. More...
 
void HAL_SCU_ClockMonitoring_Disable (void)
 Disable Clock Monitoring. More...
 
void HAL_SCU_ClockSource_Config (uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
 Set Clock Source, HIRC Frequency, and type of XMOSC. More...
 
void HAL_SCU_ClockSource_Enable (uint32_t u32ClkSrc, uint32_t u32HircDiv)
 Enable Clock Source. More...
 
void HAL_SCU_ClockSource_Disable (uint32_t u32ClkSrc)
 Disable Clock Source. More...
 
void HAL_SCU_SystemClockChange (uint32_t u32Target)
 Change System Clock. More...
 
void HAL_SCU_MainXtal_PinConfig (uint32_t u32XtalFilter)
 Set XMOSC Pins for x-tal. More...
 
void HAL_SCU_SubXtal_PinConfig (void)
 Set XSOSC Pins for x-tal. More...
 
void HAL_SCU_SystemClockDivider (uint32_t u32Div02, uint32_t u32Div13)
 Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick Timer and PCLK. More...
 
void HAL_SCU_CLKO_PinConfig (void)
 Set CLKO Pin for Clock Output. More...
 
void HAL_SCU_ClockOutput (uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
 Set Configuration for Clock Output. More...
 
void HAL_SCU_Peripheral_ClockConfig (uint32_t u32PeriClk1, uint32_t u32PeriClk2)
 Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b". More...
 
void HAL_SCU_Peripheral_EnableClock1 (uint32_t u32PeriClk1, uint32_t Ind)
 Set Each Peripheral Clock. More...
 
void HAL_SCU_Peripheral_EnableClock2 (uint32_t u32PeriClk2, uint32_t u32Ind)
 Set Each Peripheral Clock. More...
 
void HAL_SCU_Peripheral_ResetConfig (uint32_t u32PeriRst1, uint32_t u32PeriRst2)
 Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b". More...
 
void HAL_SCU_Peripheral_SetReset1 (uint32_t u32EachPeri1)
 Set/Reset Each Peripheral Block Reset of PPRST1 Register. More...
 
void HAL_SCU_Peripheral_SetReset2 (uint32_t u32EachPeri2)
 Set/Reset Each Peripheral Block Reset of PPRST2 Register. More...
 
void HAL_SCU_Peripheral_ClockSelection (uint32_t u32Peri, uint32_t u32ClkSrc)
 Peripheral Clock Selection of PPCLKSR Register. More...
 

Detailed Description

Contains all macro definitions and function prototypes support for scu firmware library on A31R71x.

Version
1.00
Date
2020-05-29
Author
ABOV Application Team

Copyright(C) 2019, ABOV Semiconductor All rights reserved.

ABOV Disclaimer

IMPORTANT NOTICE ? PLEASE READ CAREFULLY ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders. Purchasers are entirely responsible for the choice, selection, and use of ABOV products and ABOV assumes no liability for application assistance or the design of purchasers' products. No license, express or implied, to any intellectual property rights is granted by ABOV herein. ABOV disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications. ABOV and the ABOV logo are trademarks of ABOV. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces the information previously supplied in any former versions of this document. 2020 ABOV Semiconductor All rights reserved

Definition in file A31R71x_hal_scu.h.

Function Documentation

◆ HAL_SCU_CLKO_PinConfig()

void HAL_SCU_CLKO_PinConfig ( void  )

Set CLKO Pin for Clock Output.

Returns
None

This function sets selected pin's alternative for CLKO.

Definition at line 401 of file A31R71x_hal_scu.c.

402 {
403  PF->AFSR1 &= 0xFFF0FFFF; // PF4 VREG 0: CLKO 1: VREG 2: ---- 3: ---- 4: ----
404  PF->PUPD &= 0xFFFCFFuL; // PF4 VREG 0: Disable Pull-Up/Down 1: Enable Pull-Up 2: Enable Pull-Down
405  PF->MOD &= 0xFFFCFFuL; // PF4 VREG 0: Input Mode 1: Output Mode 2: Alternative Function Mode
406  PF->MOD |= 0x0200uL; // PF4 VREG 0: Input Mode 1: Output Mode 2: Alternative Function Mode
407 }

◆ HAL_SCU_ClockMonitoring()

void HAL_SCU_ClockMonitoring ( uint32_t  u32Acts,
uint32_t  u32Target 
)

Configure Clock Monitoring.

Parameters
[in]u32ActsClock Monitoring Action Selection
  • MACTS_FlagChk, MACTS_RstGen, MACTS_SysClkChg
[in]u32TargetClock Monitoring Target Selection
  • MONCS_MCLK, MONCS_HIRC, MONCS_XMOSC, MONCS_XSOSC
Returns
None

This function checks whether the target clock oscillates.

Definition at line 207 of file A31R71x_hal_scu.c.

208 {
209  if( SCUCG->CLKSRCR_b.WDTRCEN == 0 )
210  {
211  SCUCG->CLKSRCR = SCUCG->CLKSRCR
212  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
213  | CLKSRCR_WDTRCEN; // The WDTRC should be enabled to use clock monitoring
214  }
215  SCUCG->CMONCR = ( 0x3uL << 2 ) | u32Acts | u32Target; // Clear MONFLAG and NMINTFG, Set Monitoring Target and Monitoring Action
216  SCUCG->CMONCR_b.MONEN = 1; // Clock Monitoring Enable
217 }

◆ HAL_SCU_ClockMonitoring_Disable()

void HAL_SCU_ClockMonitoring_Disable ( void  )

Disable Clock Monitoring.

Returns
None

This function disables clock monitoring. Before disabling the ¡°clock monitoring¡± function, you need to take step to clear the MACTS[1:0] bits of SCU_CMONCR register to ¡°00b¡±.

Definition at line 226 of file A31R71x_hal_scu.c.

227 {
228  SCUCG->CMONCR_b.MACTS = 0; // Clear MACTS bits first
229  SCUCG->CMONCR_b.MONEN = 0; // Disable clock monitoring function
230 }

◆ HAL_SCU_ClockOutput()

void HAL_SCU_ClockOutput ( uint32_t  u32ClkSrc,
uint32_t  u32Level,
uint32_t  u32Div 
)

Set Configuration for Clock Output.

Parameters
[in]u32ClkSrcClock to output
  • CLKOS_MCLK, CLKOS_WDTRC, CLKOS_HIRC, CLKOS_HCLK, CLKOS_PCLK
[in]u32LevelClock Output Polarity when Disable
  • POLSEL_Low, POLSEL_High
[in]u32DivOutput Clock Divide
  • CLKODIV_SelectedClock1, CLKODIV_SelectedClock2
  • CLKODIV_SelectedClock4, CLKODIV_SelectedClock8
  • CLKODIV_SelectedClock16, CLKODIV_SelectedClock32
  • CLKODIV_SelectedClock64, CLKODIV_SelectedClock128
Returns
None

This function sets clock output related configuration.

Definition at line 426 of file A31R71x_hal_scu.c.

427 {
428  SCUCG->CLKOCR = 0
429  | ( 1 << SCUCG_CLKOCR_CLKOEN_Pos ) // CLKO Enable
430  | u32Level // 0: Low Level 1: High Level
431  | u32Div // 0: div_1 1: div_2 2: div_4 3: div_8 4: div_16 5: div_32 6: div_64 7: div_128
432  | u32ClkSrc // 0: MCLK 1: WDTRC 2: HIRC 3: HCLK 4: PCLK
433  ;
434 }

◆ HAL_SCU_ClockSource_Config()

void HAL_SCU_ClockSource_Config ( uint32_t  u32FreIRC,
uint32_t  u32TypeXM,
uint32_t  u32ClkSrc 
)

Set Clock Source, HIRC Frequency, and type of XMOSC.

Parameters
[in]u32FreIRCHIRC Frequency Selection
  • HIRCSEL_HIRC1, HIRCSEL_HIRC2, HIRCSEL_HIRC4, HIRCSEL_HIRC8
[in]u32TypeXMMain Oscillator Type and Frequency Range Selection
  • XMFRNG_Xtal, XMFRNG_Clock
[in]u32ClkSrcClock Source
  • CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
Returns
None

This function sets clock source, HIRC frequency, and x-tal type of XMOSC. If target clock source is one of XMOSC and XSOSC, the x-tal pins should be set as alternative before this function call. To set alternative for x-tal, Use HAL_SCU_MainXtal_PinConfig() and HAL_SCU_SubXtal_PinConfig() functions.

Definition at line 249 of file A31R71x_hal_scu.c.

250 {
251  uint32_t tmp;
252 
253  tmp = SCUCG->CLKSRCR & 0x0000000F;
254  tmp |= ( ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
255  | u32FreIRC // HIRC Frequency
256  | u32TypeXM // XMOSC type: x-tal or external clock
257  | u32ClkSrc );
258  SCUCG->CLKSRCR = tmp;
259 }

◆ HAL_SCU_ClockSource_Disable()

void HAL_SCU_ClockSource_Disable ( uint32_t  u32ClkSrc)

Disable Clock Source.

Parameters
[in]u32ClkSrcClock Source
  • CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
Returns
None

This function is used to disable original source after system clock change.

[Example]
// disable XMOSC, SXOSC
HAL_SCU_ClockSource_Disable( CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN );

Definition at line 312 of file A31R71x_hal_scu.c.

313 {
314  uint32_t tmp;
315 
316  tmp = SCUCG->CLKSRCR & 0x0000FFFF;
317  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
318  tmp &= ~u32ClkSrc;
319  SCUCG->CLKSRCR = tmp;
320 }

◆ HAL_SCU_ClockSource_Enable()

void HAL_SCU_ClockSource_Enable ( uint32_t  u32ClkSrc,
uint32_t  u32HircDiv 
)

Enable Clock Source.

Parameters
[in]u32ClkSrcClock Source
  • CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
[in]u32HircDivHIRC Frequency Selection
  • HIRCSEL_HIRC1, HIRCSEL_HIRC2, HIRCSEL_HIRC4, HIRCSEL_HIRC8
Returns
None

This function is used to enable original source after system clock change.

[Example]
// eable HIRC, XMOSC, SXOSC, WDTRC and select HIRCSEL_HIRC1(40MHz HIRC)
HAL_SCU_ClockSource_Enable( CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN | CLKSRCR_WDTRCEN, HIRCSEL_HIRC1 );

Definition at line 278 of file A31R71x_hal_scu.c.

279 {
280 #if 0 // before bug fix
281  uint32_t tmp;
282 
283  tmp = SCUCG->CLKSRCR & 0x0000FFFF; // 0x00000fff°¡ ¿ÇÀ» µí...
284  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
285  tmp |= u32ClkSrc;
286  tmp |= u32HircDiv;
287  SCUCG->CLKSRCR = tmp;
288 #else // after bug fix
289  SCUCG->CLKSRCR = SCUCG->CLKSRCR
290  & ~( SCUCG_CLKSRCR_WTIDKY_Msk | SCUCG_CLKSRCR_HIRCSEL_Msk )
291  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
292  | u32HircDiv
293  | u32ClkSrc
294  ;
295 #endif
296 }

◆ HAL_SCU_HIRCTRM_ClockConfig()

void HAL_SCU_HIRCTRM_ClockConfig ( uint32_t  u32Ind)

Change fine trim value of HIRC by one step.

Parameters
[in]u32IndIndicator for +/- one step
  • HIRC_UP_ONESTEP, HIRC_DOWN_ONESTEP
Returns
None

This function changes fine trim value by one step. If the u32Ind is HIRC_UP_ONESTEP, HIRC frequency is changed up by about 140kHz. If the u32Ind is HIRC_DOWN_ONESTEP, HIRC frequency is changed down by about 140kHz.

Definition at line 108 of file A31R71x_hal_scu.c.

109 {
110  uint32_t tmp, ntrim;
111 
112  tmp = ( SCUCC->HIRCTRM ) & 0x001fuL; // Read current fine trim value of HIRC
113  if( u32Ind == HIRC_UP_ONESTEP ) // Increment by one step(about 140kHz)
114  {
115  if( tmp != 0x0f )
116  {
117  tmp++;
118  }
119  }
120  else // Decrement by one step(about 140kHz)
121  {
122  if( tmp != 0x10 )
123  {
124  tmp--;
125  }
126  }
127  tmp &= 0x1f; // Fine trim value is only 5-bits
128  tmp |= ( ( SCUCC->HIRCTRM ) & 0x00E0uL ); // Read Coarse trim value
129  ntrim = ( tmp << 8 ) ^ 0x0000FF00; // Make write complement key
130  SCUCC->HIRCTRM = ( ( uint32_t )SCUCC_HIRCTRM_WTIDKY_Value << SCUCC_HIRCTRM_WTIDKY_Pos ) // Write new HIRC trim value with write ID and complement key
131  | ntrim
132  | tmp;
133 }

◆ HAL_SCU_MainXtal_PinConfig()

void HAL_SCU_MainXtal_PinConfig ( uint32_t  u32XtalFilter)

Set XMOSC Pins for x-tal.

Parameters
[in]u32XtalFilterthe filter of x-tal frequency
  • XRNS_LE4p5MHz, XRNS_LE6p5MHz, XRNS_LE8p5MHz
  • XRNS_LE10p5MHz, XRNS_LE12p5MHz, XRNS_LE16p5MHz
Returns
None

This function sets PF[1:0]'s alternative for x-tal of XMOSC.

Definition at line 331 of file A31R71x_hal_scu.c.

332 {
333  PF->AFSR1 &= 0xFFFFFF00; // PF[1:0]: XIN/XOUT
334  PF->PUPD &= 0xFFFFF0uL; // PF[1:0]: Pull-up/down resistors Disable
335  PF->MOD &= 0xFFFFF0uL;
336  PF->MOD |= 0x000AuL; // PF[1:0]: Alternative Function
337  SCUCG->XTFLSR = ( ( uint32_t )SCUCG_XTFLSR_WTIDKY_Value << SCUCG_XTFLSR_WTIDKY_Pos ) // Write ID
338  | u32XtalFilter; // x-tal filter value
339 }

◆ HAL_SCU_Peripheral_ClockConfig()

void HAL_SCU_Peripheral_ClockConfig ( uint32_t  u32PeriClk1,
uint32_t  u32PeriClk2 
)

Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".

Parameters
[in]u32PeriClk1Values for TIMER20 ~ TIMER21, TIMER10 ~ TIMER15, PA ~ PF
[in]u32PeriClk2Values for the Others Peripheral
Returns
None

This function sets the peripheral clock. A peripheral works properly during the corresponding bit is set to "1b".

Definition at line 446 of file A31R71x_hal_scu.c.

447 {
448  SCUCG->PPCLKEN1 = u32PeriClk1; // Set peripheral clock of timers and ports
449  SCUCG->PPCLKEN2 = u32PeriClk2; // Set peripheral clock of the others
450 }

◆ HAL_SCU_Peripheral_ClockSelection()

void HAL_SCU_Peripheral_ClockSelection ( uint32_t  u32Peri,
uint32_t  u32ClkSrc 
)

Peripheral Clock Selection of PPCLKSR Register.

Parameters
[in]u32PeriPeripheral Selection
  • PPCLKSR_T20CLK, PPCLKSR_LCDCLK, PPCLKSR_WTCLK, PPCLKSR_WDTCLK
[in]u32ClkSrcPeripheral Clock Selection
  • PPCLKSR_T20CLK: T20CLK_XSOSC, T20CLK_PCLK
  • PPCLKSR_LCDCLK: LCDCLK_DividedMCLK, LCDCLK_XSOSC, LCDCLK_WDTRC
  • PPCLKSR_WTCLK: WTCLK_DividedMCLK, WTCLK_XSOSC, WTCLK_WDTRC
  • PPCLKSR_WDTCLK: WDTCLK_WDTRC, WDTCLK_PCLK

This function resets each peripheral block.

Definition at line 580 of file A31R71x_hal_scu.c.

581 {
582  SCUCG->PPCLKSR &= ~u32Peri;
583  SCUCG->PPCLKSR |= u32ClkSrc;
584 }

◆ HAL_SCU_Peripheral_EnableClock1()

void HAL_SCU_Peripheral_EnableClock1 ( uint32_t  u32PeriClk1,
uint32_t  Ind 
)

Set Each Peripheral Clock.

Parameters
[in]u32PeriClk1PeriClk1
  • PPCLKEN1_T20CLKE ~ PPCLKEN1_T21CLKE
  • PPCLKEN1_T10CLKE ~ PPCLKEN1_T15CLKE, PPCLKEN1_PACLKE ~ PPCLKEN1_PFCLKE
[in]IndEnable/Disable Peripheral Clock.
  • PPxCLKE_Disable, PPxCLKE_Enable
Returns
None

This function sets each peripheral clock of timers and Ports.

Definition at line 464 of file A31R71x_hal_scu.c.

465 {
466  if( Ind )
467  {
468  SCUCG->PPCLKEN1 |= u32PeriClk1; // Enable a peripheral clock of timers and ports
469  }
470  else
471  {
472  SCUCG->PPCLKEN1 &= ~u32PeriClk1; // Disable a peripheral clock of timers and ports
473  }
474 }

Referenced by HAL_TIMER1n_DeInit(), and HAL_TIMER1n_Init().

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◆ HAL_SCU_Peripheral_EnableClock2()

void HAL_SCU_Peripheral_EnableClock2 ( uint32_t  u32PeriClk2,
uint32_t  u32Ind 
)

Set Each Peripheral Clock.

Parameters
[in]u32PeriClk2PeriClk2
  • PPCLKEN2_FMCLKE, PPCLKEN2_LVICLKE, PPCLKEN2_WDTCLKE, PPCLKEN2_WTCLKE
  • PPCLKEN2_LCDCLKE, PPCLKEN2_CRCLKE, PPCLKEN2_ADCLKE, PPCLKEN2_I2C1CLKE
  • PPCLKEN2_UT1CLKE, PPCLKEN2_UST10CLKE ~ PPCLKEN2_UST11CLKE
[in]u32IndEnable/Disable Peripheral Clock.
  • PPxCLKE_Disable, PPxCLKE_Enable
Returns
None

This function sets each peripheral clock of the others.

Definition at line 489 of file A31R71x_hal_scu.c.

490 {
491  if( u32Ind )
492  {
493  SCUCG->PPCLKEN2 |= u32PeriClk2; // Enable a peripheral clock of others
494  }
495  else
496  {
497  SCUCG->PPCLKEN2 &= ~u32PeriClk2; // Disable a peripheral clock of others
498  }
499 }

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_LCD_Init(), HAL_LVI_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WDT_Init(), and HAL_WT_Init().

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◆ HAL_SCU_Peripheral_ResetConfig()

void HAL_SCU_Peripheral_ResetConfig ( uint32_t  u32PeriRst1,
uint32_t  u32PeriRst2 
)

Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".

Parameters
[in]u32PeriRst1Values for TIMER20 ~ TIMER21, TIMER10 ~ TIMER15, PA ~ PF
[in]u32PeriRst2Values for the Others Peripheral
Returns
None

This function reset peripheral block during the corresponding bit is set to "1b". After reset of a block, the corresponding bit should be cleared to "0b" for operation.

Definition at line 511 of file A31R71x_hal_scu.c.

512 {
513  uint32_t i;
514 
515  SCUCG->PPRST1 = u32PeriRst1; // Reset peripheral block of timers and ports if the corresponding bit is "1b"
516  SCUCG->PPRST2 = u32PeriRst2; // Reset peripheral block of the others
517  for( i = 0 ; i < 10 ; i++ )
518  {
519  NOP();
520  }
521  SCUCG->PPRST1 = 0x0uL; // Clear the peripheral reset bits
522  SCUCG->PPRST2 = 0x0uL;
523 }

◆ HAL_SCU_Peripheral_SetReset1()

void HAL_SCU_Peripheral_SetReset1 ( uint32_t  u32EachPeri1)

Set/Reset Each Peripheral Block Reset of PPRST1 Register.

Parameters
[in]u32EachPeri1Peri1
  • PPRST1_T20RST ~ PPRST1_T21RST
  • PPRST1_T10RST ~ PPRST1_T15RST, PPRST1_PARST ~ PPRST1_PFRST

This function resets each peripheral block.

Definition at line 533 of file A31R71x_hal_scu.c.

534 {
535  uint32_t i;
536 
537  SCUCG->PPRST1 = u32EachPeri1; // Reset a peripheral block
538  for( i = 0 ; i < 10 ; i++ )
539  {
540  NOP();
541  }
542  SCUCG->PPRST1 = 0; // Clear the peripheral reset bit
543 }

◆ HAL_SCU_Peripheral_SetReset2()

void HAL_SCU_Peripheral_SetReset2 ( uint32_t  u32EachPeri2)

Set/Reset Each Peripheral Block Reset of PPRST2 Register.

Parameters
[in]u32EachPeri2Peri2
  • PPRST2_FMCRST, PPRST2_LVIRST, PPRST2_WTRST, PPRST2_LCDRST
  • PPRST2_CRRST, PPRST2_ADRST, PPRST2_I2C1RST, PPRST2_UT1RST
  • PPRST2_UST10RST ~ PPRST2_UST11RST

This function resets each peripheral block.

Definition at line 554 of file A31R71x_hal_scu.c.

555 {
556  uint32_t i;
557 
558  SCUCG->PPRST2 = u32EachPeri2; // Reset a peripheral block
559  for( i = 0 ; i < 10 ; i++ )
560  {
561  NOP();
562  }
563  SCUCG->PPRST2 = 0; // Clear the peripheral reset bit
564 }

Referenced by HAL_CRC_DeInit(), HAL_I2C_Init(), HAL_UART_DeInit(), HAL_USART_DeInit(), and HAL_USART_Init().

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◆ HAL_SCU_ResetSourceStatus()

uint32_t HAL_SCU_ResetSourceStatus ( void  )

Get Reset Source Status.

Returns
Reset Source

This function gets reset source status and clear the register.

Definition at line 52 of file A31R71x_hal_scu.c.

53 {
54  uint32_t tmp;
55 
56  tmp = SCUCC->RSTSSR; // Get reset source status
57  SCUCC->RSTSSR = 0x3FuL; // Clear all reset source status
58  return tmp;
59 }

◆ HAL_SCU_SetNMI()

void HAL_SCU_SetNMI ( uint32_t  u32NmiCon)

Set Non-Maskable Interrupt(NMI) Source Selection Register.

Parameters
[in]u32NmiConValues for NMISRCR register
Returns
None

This function sets NMISRCR register.

Definition at line 68 of file A31R71x_hal_scu.c.

69 {
70  SCUCC->NMISRCR = u32NmiCon;
71 }

◆ HAL_SCU_SetWakupData()

void HAL_SCU_SetWakupData ( uint32_t  u32Data)

Set Wake-Up Timer Data.

Parameters
[in]u32Data
Returns
None

This function sets wake-up timer data to wait for release of deep sleep mode. Its value should be set to be at least more than 150usec.

Definition at line 93 of file A31R71x_hal_scu.c.

94 {
95  SCUCC->WUTDR = u32Data; // On HCLK=40MHz, (150us x 40)/32 = 187.5. So, the data should be more than 187
96 }

◆ HAL_SCU_SoftwareReset_Config()

void HAL_SCU_SoftwareReset_Config ( void  )

Check whether system reset ok or not. Generate s/w reset if a weak reset.

Returns
None

This function checks system reset validation and Generate s/w reset if a weak reset.

Definition at line 78 of file A31R71x_hal_scu.c.

79 {
80  if( SCUCC->SRSTVR_b.VALID != 0x55 )
81  {
82  SCUCC_GenSwRst(); // Generate S/W reset on invalid reset
83  }
84 }

◆ HAL_SCU_SubXtal_PinConfig()

void HAL_SCU_SubXtal_PinConfig ( void  )

Set XSOSC Pins for x-tal.

Returns
None

This function sets PF[3:2]'s alternative for x-tal of XSOSC.

Definition at line 346 of file A31R71x_hal_scu.c.

347 {
348  PF->AFSR1 &= 0xFFFF00FF; // PF[3:2]: SXIN/SXOUT
349  PF->PUPD &= 0xFFFF0FuL; // PF[3:2]: Pull-up/down resistors Disable
350  PF->MOD &= 0xFFFF0FuL;
351  PF->MOD |= 0x00A0uL; // PF[3:2]: Alternative Function
352 }

◆ HAL_SCU_SystemClockChange()

void HAL_SCU_SystemClockChange ( uint32_t  u32Target)

Change System Clock.

Parameters
[in]u32TargetTarget Clock
  • MCLKSEL_HIRC, MCLKSEL_XMOSC, MCLKSEL_XSOSC, MCLKSEL_WDTRC
Returns
None

This function changes system clock to target source.

Definition at line 362 of file A31R71x_hal_scu.c.

363 {
364  SCUCG->SCCR = ( SCUCG_SCCR_WTIDKY_Value << SCUCG_SCCR_WTIDKY_Pos ) // Write ID
365  | u32Target; // Target Clock Source
366 }

◆ HAL_SCU_SystemClockDivider()

void HAL_SCU_SystemClockDivider ( uint32_t  u32Div02,
uint32_t  u32Div13 
)

Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick Timer and PCLK.

Parameters
[in]u32Div02Values for Divider 0 and 2
  • Clock Divide for HCLK (Divider 0)
    • HDIV_MCLK16, HDIV_MCLK8, HDIV_MCLK4, HDIV_MCLK2, HDIV_MCLK1
  • Clock Divide for Watch Timer and LCD Driver (Divider 2)
    • WLDIV_MCLK64, WLDIV_MCLK128, WLDIV_MCLK256, WLDIV_MCLK512, WLDIV_MCLK1024
[in]u32Div13Values for Divider 1 and 3
  • Clock Divide for PCLK (Divider 1)
    • PDIV_HCLK1, PDIV_HCLK2, PDIV_HCLK4, PDIV_HCLK8
  • Clock Divide for SysTick Timer (Divider 3)
    • SYSTDIV_HCLK1, SYSTDIV_HCLK2, SYSTDIV_HCLK4, SYSTDIV_HCLK8
Returns
None

This function changes system clock to target source.

Definition at line 385 of file A31R71x_hal_scu.c.

386 {
387  // Divider 0 for HCLK: 000/001/010/011/100: MCLK is divided by 16/8/4/2/1
388  // Divider 2 for WT and LCD Driver: 000/001/010/011/100: MCLK is divided by 64/128/256/512/1024
389  SCUCG->SCDIVR1 = u32Div02;
390 
391  // Divider 1 for PCLK: 00/01/10/11: HCLK is divided by 1/2/4/8
392  // Divider 3 for SysTick Timer: 00/01/10/11: HCLK is divided by 1/2/4/8
393  SCUCG->SCDIVR2 = u32Div13;
394 }

◆ HAL_SCU_WDTRCTRM_ClockConfig()

void HAL_SCU_WDTRCTRM_ClockConfig ( uint32_t  u32Ind)

Change fine trim value of WDTRC by one step.

Parameters
[in]u32IndIndicator for +/- one step
  • WDTRC_UP_ONESTEP, WDTRC_DOWN_ONESTEP
Returns
None

This function changes fine trim value by one step. If the u32Ind is WDTRC_UP_ONESTEP, WDTRC frequency is changed up by about 1.1kHz. If the u32Ind is WDTRC_DOWN_ONESTEP, WDTRC frequency is changed down by about 1.1kHz.

Definition at line 145 of file A31R71x_hal_scu.c.

146 {
147  uint32_t ctmp, ftmp, ntrim;
148 
149  ftmp = ( SCUCC->WDTRCTRM ) & 0x0007uL; // Read current fine trim value of WDTRC
150  ctmp = ( SCUCC->WDTRCTRM ) & 0x00F0uL; // Read current coarse trim value of WDTRC
151  if( u32Ind == WDTRC_UP_ONESTEP ) // Increment by one step(about 1.1kHz)
152  {
153  ftmp++;
154  ftmp &= 0x07uL; // Fine trim value is only 3-bits
155  if( ftmp == 0x04 )
156  {
157  if( ctmp != 0x70 )
158  {
159  ctmp += 0x10uL;
160  }
161  else
162  {
163  ftmp = 0x03uL;
164  }
165  }
166  }
167  else // Decrement by one step(about 1.1kHz)
168  {
169  ftmp--;
170  ftmp &= 0x07uL; // Fine trim value is only 3-bits
171  if( ftmp == 0x03 )
172  {
173  if( ctmp != 0x80 )
174  {
175  ctmp -= 0x10uL;
176  }
177  else
178  {
179  ftmp = 0x04uL;
180  }
181  }
182  }
183  ctmp &= 0x00f0uL; // Coarse trim value is only 4-bits
184  ctmp |= ftmp;
185  ntrim = ( ctmp << 8 ) ^ 0x0000FF00; // Make write complement key
186  SCUCC->WDTRCTRM = ( SCUCC_WDTRCTRM_WTIDKY_Value << SCUCC_WDTRCTRM_WTIDKY_Pos ) // Write new WDTRC trim value with write ID and complement key
187  | ntrim
188  | ctmp;
189 }