A31R71x F/W Packages  1.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
Data Structures | Enumerations | Functions
A31R71x_hal_usart1n.h File Reference

Contains all macro definitions and function prototypes support for usart1n firmware library on A31R71x. More...

Go to the source code of this file.

Data Structures

struct  USART1n_CFG_Type
 

Enumerations

enum  USART1n_OPMODE_Type { USART1n_UART_MODE = 0, USART1n_USRT_MODE, USART1n_SPI_MODE = 3 }
 
enum  USART1n_SPI_ORDER_Type { USART1n_SPI_LSB = 0, USART1n_SPI_MSB }
 
enum  USART1n_ACK_Type { USART1n_SPI_TX_RISING = 0, USART1n_SPI_TX_FALLING }
 
enum  USART1n_EDGE_Type { USART1n_SPI_TX_LEADEDGE_SAMPLE = 0, USART1n_SPI_TX_LEADEDGE_SETUP }
 
enum  USART1n_DATA_BIT_Type {
  USART1n_DATA_BIT_5 = 0, USART1n_DATA_BIT_6, USART1n_DATA_BIT_7, USART1n_DATA_BIT_8,
  USART1n_DATA_BIT_9 = 7
}
 
enum  USART1n_STOP_BIT_Type { USART1n_STOP_BIT_1 = 0, USART1n_STOP_BIT_2 }
 
enum  USART1n_PARITY_BIT_Type { USART1n_PARITY_BIT_NONE = 0, USART1n_PARITY_BIT_EVEN = 2, USART1n_PARITY_BIT_ODD = 3 }
 
enum  USART1n_CONTROL_Type {
  USART1n_CONTROL_USTRX8 = 0, USART1n_CONTROL_USTTX8, USART1n_CONTROL_USTSB, USART1n_CONTROL_FXCH,
  USART1n_CONTROL_USTSSEN, USART1n_CONTROL_DISSCK, USART1n_CONTROL_LOOPS, USART1n_CONTROL_MASTER,
  USART1n_CONTROL_DBLS, USART1n_CONTROL_USTEN
}
 
enum  USART1n_STATUS_Type {
  USART1n_STATUS_PE = 0, USART1n_STATUS_FE, USART1n_STATUS_DOR, USART1n_STATUS_WAKE,
  USART1n_STATUS_RXC, USART1n_STATUS_TXC, USART1n_STATUS_DRE
}
 
enum  USART1n_INT_Type { USART1n_INTCFG_WAKE = 0, USART1n_INTCFG_RXC, USART1n_INTCFG_TXC, USART1n_INTCFG_DR }
 

Functions

HAL_Status_Type HAL_USART_Init (USART1n_Type *USART1x, USART1n_CFG_Type *USART1n_Config)
 Initialize the USART1n peripheral with the specified parameters. More...
 
HAL_Status_Type HAL_USART_DeInit (USART1n_Type *USART1x)
 Deinitialize the USART1n peripheral registers to their default reset values. More...
 
HAL_Status_Type HAL_USART_UART_Mode_Config (USART1n_CFG_Type *USART1n_Config)
 Fills each USART1n_Config member with its default value: More...
 
HAL_Status_Type HAL_USART_USRT_Mode_Config (USART1n_CFG_Type *USART1n_Config)
 Fills each USART1n_Config member with its default value: More...
 
HAL_Status_Type HAL_USART_SPI_Mode_Config (USART1n_CFG_Type *USART1n_Config)
 Fills each USART1n_Config member with its default value: More...
 
HAL_Status_Type HAL_USART_ConfigInterrupt (USART1n_Type *USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState)
 Configure the interrupt source of selected USART1n peripheral. More...
 
HAL_Status_Type HAL_USART_DataControlConfig (USART1n_Type *USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState)
 Configure Data Control mode for USART peripheral. More...
 
HAL_Status_Type HAL_USART_Enable (USART1n_Type *USART1x, FunctionalState state)
 USART1n enable control. More...
 
HAL_Status_Type HAL_USART_ClearStatus (USART1n_Type *USART1x, USART1n_STATUS_Type Status)
 Clear Status register in USART peripheral. More...
 
uint8_t HAL_USART_GetStatus (USART1n_Type *USART1x)
 Get current value of Line Status register in USART peripheral. More...
 
FlagStatus HAL_USART_CheckBusy (USART1n_Type *USART1x)
 Check whether if USART is busy or not. More...
 
HAL_Status_Type HAL_USART_TransmitByte (USART1n_Type *USART1x, uint8_t Data)
 Transmit a single data through USART peripheral. More...
 
uint8_t HAL_USART_ReceiveByte (USART1n_Type *USART1x)
 Receive a single data from USART peripheral. More...
 
uint32_t HAL_USART_Transmit (USART1n_Type *USART1x, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
 Send a block of data via USART peripheral. More...
 
uint32_t HAL_USART_Receive (USART1n_Type *USART1x, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
 Receive a block of data via USART peripheral. More...
 

Detailed Description

Contains all macro definitions and function prototypes support for usart1n firmware library on A31R71x.

Version
1.00
Date
2020-05-29
Author
ABOV Application Team

Copyright(C) 2019, ABOV Semiconductor All rights reserved.

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Definition in file A31R71x_hal_usart1n.h.

Enumeration Type Documentation

◆ USART1n_ACK_Type

Enumerator
USART1n_SPI_TX_RISING 

Txd Change : Rising / Rxd Change : Falling

USART1n_SPI_TX_FALLING 

Txd Change : Falling / Rxd Change : Rising

Definition at line 111 of file A31R71x_hal_usart1n.h.

◆ USART1n_CONTROL_Type

USART Data Control type definition

Enumerator
USART1n_CONTROL_USTRX8 
USART1n_CONTROL_USTTX8 
USART1n_CONTROL_USTSB 
USART1n_CONTROL_FXCH 
USART1n_CONTROL_USTSSEN 
USART1n_CONTROL_DISSCK 
USART1n_CONTROL_LOOPS 
USART1n_CONTROL_MASTER 
USART1n_CONTROL_DBLS 
USART1n_CONTROL_USTEN 

Definition at line 149 of file A31R71x_hal_usart1n.h.

◆ USART1n_DATA_BIT_Type

USART1n Data Bit type definitions

Enumerator
USART1n_DATA_BIT_5 

5 Data Bits

USART1n_DATA_BIT_6 

6 Data Bits

USART1n_DATA_BIT_7 

7 Data Bits

USART1n_DATA_BIT_8 

8 Data Bits

USART1n_DATA_BIT_9 

9 Data Bits

Definition at line 124 of file A31R71x_hal_usart1n.h.

◆ USART1n_EDGE_Type

Enumerator
USART1n_SPI_TX_LEADEDGE_SAMPLE 

Leading edge : Sample / Trailing edge : Setup

USART1n_SPI_TX_LEADEDGE_SETUP 

Leading edge : Setup / Trailing edge : Sample

Definition at line 117 of file A31R71x_hal_usart1n.h.

◆ USART1n_INT_Type

Enumerator
USART1n_INTCFG_WAKE 

Wake-Up Interrupt enable

USART1n_INTCFG_RXC 

Receive Complete Interrupt enable

USART1n_INTCFG_TXC 

Transmit Complete line status interrupt enable

USART1n_INTCFG_DR 

Data Register Empty interrupt

Definition at line 174 of file A31R71x_hal_usart1n.h.

◆ USART1n_OPMODE_Type

Enumerator
USART1n_UART_MODE 

UART Mode

USART1n_USRT_MODE 

USRT Mode (Syncronous)

USART1n_SPI_MODE 

SPI Mode

Definition at line 98 of file A31R71x_hal_usart1n.h.

◆ USART1n_PARITY_BIT_Type

USART1n Parity Bit type definitions

Enumerator
USART1n_PARITY_BIT_NONE 

No parity

USART1n_PARITY_BIT_EVEN 

Even parity

USART1n_PARITY_BIT_ODD 

Odd parity

Definition at line 141 of file A31R71x_hal_usart1n.h.

◆ USART1n_SPI_ORDER_Type

Enumerator
USART1n_SPI_LSB 

SPI LSB First

USART1n_SPI_MSB 

SPI MSB First

Definition at line 105 of file A31R71x_hal_usart1n.h.

◆ USART1n_STATUS_Type

Enumerator
USART1n_STATUS_PE 
USART1n_STATUS_FE 
USART1n_STATUS_DOR 
USART1n_STATUS_WAKE 
USART1n_STATUS_RXC 
USART1n_STATUS_TXC 
USART1n_STATUS_DRE 

Definition at line 163 of file A31R71x_hal_usart1n.h.

◆ USART1n_STOP_BIT_Type

USART1n Stop Bit type definitions

Enumerator
USART1n_STOP_BIT_1 

1 Stop Bits

USART1n_STOP_BIT_2 

2 Stop Bits

Definition at line 134 of file A31R71x_hal_usart1n.h.

Function Documentation

◆ HAL_USART_CheckBusy()

FlagStatus HAL_USART_CheckBusy ( USART1n_Type *  USART1x)

Check whether if USART is busy or not.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
Returns
RESET if USART is not busy, otherwise return SET.

Definition at line 592 of file A31R71x_hal_usart1n.c.

593 {
594  if( USART1x->ST & USART1n_SR_DRE )
595  {
596  return RESET;
597  }
598  else
599  {
600  return SET;
601  }
602 }

References RESET, and SET.

◆ HAL_USART_ClearStatus()

HAL_Status_Type HAL_USART_ClearStatus ( USART1n_Type *  USART1x,
USART1n_STATUS_Type  Status 
)

Clear Status register in USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[in]Status
Returns
HAL_Status_Type

Definition at line 540 of file A31R71x_hal_usart1n.c.

541 {
542  uint32_t tmp;
543 
544  /* Check USART handle */
545  if( USART1x == NULL )
546  {
547  return HAL_ERROR;
548  }
549 
550  switch( Status )
551  {
552  case USART1n_STATUS_WAKE:
553  tmp = USART1n_SR_WAKE;
554  break;
555  case USART1n_STATUS_RXC:
556  tmp = USART1n_SR_RXC;
557  break;
558  case USART1n_STATUS_TXC:
559  tmp = USART1n_SR_TXC;
560  break;
561  case USART1n_STATUS_DRE:
562  tmp = USART1n_SR_DRE;
563  break;
564  default:
565  return HAL_ERROR;
566  }
567 
568  USART1x->ST = tmp;
569 
570  return HAL_OK;
571 }

References HAL_ERROR, HAL_OK, USART1n_STATUS_DRE, USART1n_STATUS_RXC, USART1n_STATUS_TXC, and USART1n_STATUS_WAKE.

Referenced by HAL_USART_Init(), and HAL_USART_Transmit().

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◆ HAL_USART_ConfigInterrupt()

HAL_Status_Type HAL_USART_ConfigInterrupt ( USART1n_Type *  USART1x,
USART1n_INT_Type  USART1n_IntCfg,
FunctionalState  NewState 
)

Configure the interrupt source of selected USART1n peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[in]USART1n_IntCfgSpecifies the interrupt source
  • USART1n_INTCFG_DR: DR Interrupt enable
  • USART1n_INTCFG_TXC: TXC Interrupt enable
  • USART1n_INTCFG_RXC: RXC interrupt enable
  • USART1n_INTCFG_WAKE: WAKE Interrupt enable
[in]NewStateNext State of Interrupt Operation
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 385 of file A31R71x_hal_usart1n.c.

386 {
387  uint32_t tmp = 0;
388 
389  /* Check USART handle */
390  if( USART1x == NULL )
391  {
392  return HAL_ERROR;
393  }
394 
395  switch( USART1n_IntCfg )
396  {
397  case USART1n_INTCFG_WAKE :
398  tmp = USART1n_IER_WAKEINT_EN;
399  break;
400  case USART1n_INTCFG_RXC:
401  tmp = USART1n_IER_RXCINT_EN;
402  break;
403  case USART1n_INTCFG_TXC:
404  tmp = USART1n_IER_TXCINT_EN;
405  break;
406  case USART1n_INTCFG_DR:
407  tmp = USART1n_IER_DR_EN;
408  break;
409  }
410 
411  if( NewState == ENABLE )
412  {
413  USART1x->CR1 |= tmp;
414  }
415  else
416  {
417  USART1x->CR1 &= ~( tmp & USART1n_IER_BITMASK );
418  }
419 
420  return HAL_OK;
421 }

References ENABLE, HAL_ERROR, HAL_OK, USART1n_INTCFG_DR, USART1n_INTCFG_RXC, USART1n_INTCFG_TXC, and USART1n_INTCFG_WAKE.

◆ HAL_USART_DataControlConfig()

HAL_Status_Type HAL_USART_DataControlConfig ( USART1n_Type *  USART1x,
USART1n_CONTROL_Type  Mode,
FunctionalState  NewState 
)

Configure Data Control mode for USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[in]ModeData Control Mode
  • USART1n_CONTROL_USTEN: Activate USARTn Block by supplying.
  • USART1n_CONTROL_DBLS: Selects receiver sampling rate. (only UART mode)
  • USART1n_CONTROL_MASTER: Selects master or slave in SPIn or Synchronous mode and controls the direction of SCKn pin.
  • USART1n_CONTROL_LOOPS: Control the Loop Back mode of USARTn for test mode.
  • USART1n_CONTROL_DISSCK: In synchronous mode operation, selects the waveform of SCKn output.
  • USART1n_CONTROL_USTSSEN: This bit controls the SSn pin operation. (only SPI mode)
  • USART1n_CONTROL_FXCH: SPIn port function exchange control bit. (only SPI mode)
  • USART1n_CONTROL_USTSB: Selects the length of stop bit in Asynchronous or Synchronous mode.
  • USART1n_CONTROL_USTTX8: The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USARTn_DR register.
  • USART1n_CONTROL_USTRX8: The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)
[in]NewStateNext State of Functional Operation
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 445 of file A31R71x_hal_usart1n.c.

446 {
447  uint16_t tmp = 0;
448 
449  /* Check USART handle */
450  if( USART1x == NULL )
451  {
452  return HAL_ERROR;
453  }
454 
455  switch( Mode )
456  {
458  tmp = USART1n_CR2_USTnRX8;
459  break;
461  tmp = USART1n_CR2_USTnTX8;
462  break;
464  tmp = USART1n_CR2_USTnSB;
465  break;
467  tmp = USART1n_CR2_FXCHn;
468  break;
470  tmp = USART1n_CR2_USTnSSEN;
471  break;
473  tmp = USART1n_CR2_DISSCKn;
474  break;
476  tmp = USART1n_CR2_LOOPSn;
477  break;
479  tmp = USART1n_CR2_MASTERn;
480  break;
482  tmp = USART1n_CR2_DBLSn;
483  break;
485  tmp = USART1n_CR2_USTnEN;
486  break;
487  default:
488  break;
489  }
490 
491  if( NewState == ENABLE )
492  {
493  USART1x->CR2 |= tmp;
494  }
495  else
496  {
497  USART1x->CR2 &= ~( tmp & USART1n_CR2_BITMASK );
498  }
499 
500  return HAL_OK;
501 }

References ENABLE, HAL_ERROR, HAL_OK, USART1n_CONTROL_DBLS, USART1n_CONTROL_DISSCK, USART1n_CONTROL_FXCH, USART1n_CONTROL_LOOPS, USART1n_CONTROL_MASTER, USART1n_CONTROL_USTEN, USART1n_CONTROL_USTRX8, USART1n_CONTROL_USTSB, USART1n_CONTROL_USTSSEN, and USART1n_CONTROL_USTTX8.

◆ HAL_USART_DeInit()

HAL_Status_Type HAL_USART_DeInit ( USART1n_Type *  USART1x)

Deinitialize the USART1n peripheral registers to their default reset values.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
Returns
HAL_Status_Type

Definition at line 195 of file A31R71x_hal_usart1n.c.

196 {
197  /* Check USART handle */
198  if( USART1x == NULL )
199  {
200  return HAL_ERROR;
201  }
202 
203 #if 1 // supported
204  if( USART1x == ( USART1n_Type* )USART10 )
205  {
206  // Set up peripheral clock for USART10 module
208  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Disable );
209  }
210 #endif
211 
212 #if 1 // supported
213  if( USART1x == ( USART1n_Type* )USART11 )
214  {
215  // Set up peripheral clock for USART11 module
217  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Disable );
218  }
219 #endif
220 
221 #if 0 // not supported
222  if( USART1x == ( USART1n_Type* )USART12 )
223  {
224  // Set up peripheral clock for USART12 module
226  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Disable );
227  }
228 #endif
229 
230 #if 0 // not supported
231  if( USART1x == ( USART1n_Type* )USART13 )
232  {
233  // Set up peripheral clock for USART13 module
235  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Disable );
236  }
237 #endif
238 
239  return HAL_OK;
240 }
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.

References HAL_ERROR, HAL_OK, HAL_SCU_Peripheral_EnableClock2(), and HAL_SCU_Peripheral_SetReset2().

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◆ HAL_USART_Enable()

HAL_Status_Type HAL_USART_Enable ( USART1n_Type *  USART1x,
FunctionalState  state 
)

USART1n enable control.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[in]state
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 512 of file A31R71x_hal_usart1n.c.

513 {
514  /* Check USART handle */
515  if( USART1x == NULL )
516  {
517  return HAL_ERROR;
518  }
519 
520  if( state == ENABLE )
521  {
522  USART1x->CR2 |= ( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
523  }
524  else
525  {
526  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
527  }
528 
529  return HAL_OK;
530 }

References ENABLE, HAL_ERROR, and HAL_OK.

◆ HAL_USART_GetStatus()

uint8_t HAL_USART_GetStatus ( USART1n_Type *  USART1x)

Get current value of Line Status register in USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
Returns
Current value of Status register in USART peripheral.

Definition at line 580 of file A31R71x_hal_usart1n.c.

581 {
582  return ( ( USART1x->ST ) & USART1n_SR_BITMASK );
583 }

◆ HAL_USART_Init()

HAL_Status_Type HAL_USART_Init ( USART1n_Type *  USART1x,
USART1n_CFG_Type USART1n_Config 
)

Initialize the USART1n peripheral with the specified parameters.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[in]USART1n_ConfigPointer to a USART1n_CFG_Type structure that contains the configuration information for the specified peripheral.
Returns
HAL_Status_Type

Definition at line 110 of file A31R71x_hal_usart1n.c.

111 {
112  uint32_t tmp;
113 
114  /* Check USART handle */
115  if( USART1x == NULL )
116  {
117  return HAL_ERROR;
118  }
119 
120 #if 1 // supported
121  if( USART1x == ( USART1n_Type* )USART10 )
122  {
123  // Set up peripheral clock for USART10 module
124  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Enable );
126  }
127 #endif
128 
129 #if 1 // supported
130  if( USART1x == ( USART1n_Type* )USART11 )
131  {
132  // Set up peripheral clock for USART11 module
133  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Enable );
135  }
136 #endif
137 
138 #if 0 // not supported
139  if( USART1x == ( USART1n_Type* )USART12 )
140  {
141  // Set up peripheral clock for USART12 module
142  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Enable );
144  }
145 #endif
146 
147 #if 0 // not supported
148  if( USART1x == ( USART1n_Type* )USART13 )
149  {
150  // Set up peripheral clock for USART13 module
151  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Enable );
153  }
154 #endif
155 
156  USART1n_BaseClock = SystemPeriClock;
157 
158  usart_set_divisors( USART1x, USART1n_Config->Mode, USART1n_Config->Baudrate );
159 
160  tmp = 0
161  | ( ( USART1n_Config->Mode & 0x3 ) << USART1n_CR1_USTnMS_Pos )
162  | ( ( USART1n_Config->Parity & 0x3 ) << USART1n_CR1_USTnP_Pos )
163  | ( ( USART1n_Config->Databits & 0x7 ) << USART1n_CR1_USTnS_Pos )
164  | ( ( USART1n_Config->Order & 0x1 ) << USART1n_CR1_ORDn_Pos )
165  | ( ( USART1n_Config->ACK & 0x1 ) << USART1n_CR1_CPOLn_Pos )
166  | ( ( USART1n_Config->Edge & 0x3 ) << USART1n_CR1_CPHAn_Pos )
167  | ( 1 << USART1n_CR1_TXEn_Pos ) // Tx Enable
168  | ( 1 << USART1n_CR1_RXEn_Pos ) // Rx Enable
169  ;
170 
171  USART1x->CR1 = tmp;
172 
173  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnSB_Pos ); // USTnSB reset
174  USART1x->CR2 |= ( ( USART1n_Config->Stopbits & 0x1 ) << USART1n_CR2_USTnSB_Pos ); // USTnSB
175  USART1x->CR2 &= ~( 1 << USART1n_CR2_FXCHn_Pos ); // FXCHn reset
176  //USART1x->CR2 |= (1<<USART1n_CR2_FXCHn_Pos); // FXCHn
177 
179 
180  // dummy read
181  HAL_USART_ReceiveByte( USART1x );
182  HAL_USART_ReceiveByte( USART1x );
183 
184  return HAL_OK;
185 }
static void usart_set_divisors(USART1n_Type *USART1x, uint32_t mode, uint32_t baudrate)
Determines best dividers to get a target clock rate.
USART1n_EDGE_Type Edge
USART1n_PARITY_BIT_Type Parity
uint32_t USART1n_BaseClock
USART1n_SPI_ORDER_Type Order
USART1n_OPMODE_Type Mode
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.
USART1n_STOP_BIT_Type Stopbits
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.

References USART1n_CFG_Type::ACK, USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, USART1n_CFG_Type::Edge, HAL_ERROR, HAL_OK, HAL_SCU_Peripheral_EnableClock2(), HAL_SCU_Peripheral_SetReset2(), HAL_USART_ClearStatus(), HAL_USART_ReceiveByte(), USART1n_CFG_Type::Mode, USART1n_CFG_Type::Order, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_BaseClock, USART1n_STATUS_TXC, and usart_set_divisors().

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◆ HAL_USART_Receive()

uint32_t HAL_USART_Receive ( USART1n_Type *  USART1x,
uint8_t *  rxbuf,
uint32_t  buflen,
TRANSFER_BLOCK_Type  flag 
)

Receive a block of data via USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[out]rxbufPointer to Received buffer
[in]buflenLength of Received buffer
[in]flagFlag mode
  • NONE_BLOCKING
  • BLOCKING
Returns
Number of bytes received
Note
when using USART in BLOCKING mode, a time-out condition is used via defined symbol USART_BLOCKING_TIMEOUT.

Definition at line 739 of file A31R71x_hal_usart1n.c.

740 {
741  uint32_t bToRecv, bRecv, timeOut;
742  uint8_t* pChar = rxbuf;
743 
744  // init counter
745  bToRecv = buflen;
746  bRecv = 0;
747 
748  // Blocking Mode
749  if( flag == BLOCKING )
750  {
751  while( bToRecv )
752  {
753  // wait until data are received with timeout
754  timeOut = USART1n_BLOCKING_TIMEOUT;
755  while( !( USART1x->ST & USART1n_SR_RXC ) )
756  {
757  if( timeOut == 0 )
758  {
759  break;
760  }
761  timeOut--;
762  }
763 
764  // if timeout
765  if( timeOut == 0 )
766  {
767  break;
768  }
769 
770  // receive byte
771  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
772 
773  // update counter
774  bToRecv--;
775  bRecv++;
776  }
777  }
778 
779  // Non-Blocking Mode
780  else
781  {
782  while( bToRecv )
783  {
784  // if no data were received
785  if( !( USART1x->ST & USART1n_SR_RXC ) )
786  {
787  break;
788  }
789 
790  // receive byte
791  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
792 
793  // update counter
794  bToRecv--;
795  bRecv++;
796  }
797  }
798 
799  // return
800  return bRecv;
801 }
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.

References BLOCKING, and HAL_USART_ReceiveByte().

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◆ HAL_USART_ReceiveByte()

uint8_t HAL_USART_ReceiveByte ( USART1n_Type *  USART1x)

Receive a single data from USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
Returns
Data received

Definition at line 633 of file A31R71x_hal_usart1n.c.

634 {
635  return USART1x->DR;
636 }

Referenced by HAL_USART_Init(), and HAL_USART_Receive().

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◆ HAL_USART_SPI_Mode_Config()

HAL_Status_Type HAL_USART_SPI_Mode_Config ( USART1n_CFG_Type USART1n_Config)

Fills each USART1n_Config member with its default value:

  • 38400 bps
  • 8 Data Bit
  • No Parity Bit
  • 1 Stop Bit
    Parameters
    [out]USART1n_ConfigPointer to a USART1n_CFG_Type structure which will be initialized.
    Returns
    HAL_Status_Type

Definition at line 329 of file A31R71x_hal_usart1n.c.

330 {
331  /* Check USART1n_Config */
332  if( USART1n_Config == NULL )
333  {
334  return HAL_ERROR;
335  }
336 
337  USART1n_Config->Mode = USART1n_SPI_MODE;
338  USART1n_Config->Baudrate = 38400;
339  USART1n_Config->Databits = USART1n_DATA_BIT_8;
340  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
341  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
342 
343  // only SPI & Sync. Mode
344  USART1n_Config->Order = USART1n_SPI_LSB;
345 
346 #if 1 // CPOLn : 0, CPHAn : 0 (X)
347  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
348  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
349 #endif
350 
351 #if 0 // CPOLn : 0, CPHAn : 1 (O)
352  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
353  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
354 #endif
355 
356 #if 0 // CPOLn : 1, CPHAn : 0 (X)
357  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
358  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
359 #endif
360 
361 #if 0 // CPOLn : 1, CPHAn : 1 (O)
362  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
363  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
364 #endif
365 
366  return HAL_OK;
367 }
USART1n_EDGE_Type Edge
USART1n_PARITY_BIT_Type Parity
USART1n_SPI_ORDER_Type Order
USART1n_OPMODE_Type Mode
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
USART1n_STOP_BIT_Type Stopbits

References USART1n_CFG_Type::ACK, USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, USART1n_CFG_Type::Edge, HAL_ERROR, HAL_OK, USART1n_CFG_Type::Mode, USART1n_CFG_Type::Order, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_DATA_BIT_8, USART1n_PARITY_BIT_NONE, USART1n_SPI_LSB, USART1n_SPI_MODE, USART1n_SPI_TX_FALLING, USART1n_SPI_TX_LEADEDGE_SAMPLE, USART1n_SPI_TX_LEADEDGE_SETUP, USART1n_SPI_TX_RISING, and USART1n_STOP_BIT_1.

◆ HAL_USART_Transmit()

uint32_t HAL_USART_Transmit ( USART1n_Type *  USART1x,
uint8_t *  txbuf,
uint32_t  buflen,
TRANSFER_BLOCK_Type  flag 
)

Send a block of data via USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[in]txbufPointer to Transmit buffer
[in]buflenLength of Transmit buffer
[in]flagFlag used in USART transfer
  • NONE_BLOCKING
  • BLOCKING
Returns
Number of bytes sent.
Note
when using USART in BLOCKING mode, a time-out condition is used via defined symbol USART_BLOCKING_TIMEOUT.

Definition at line 655 of file A31R71x_hal_usart1n.c.

656 {
657  uint32_t bToSend, bSent, timeOut;
658  uint8_t* pChar = txbuf;
659 
660  // init counter
661  bToSend = buflen;
662  bSent = 0;
663 
664  // Blocking Mode
665  if( flag == BLOCKING )
666  {
667  while( bToSend )
668  {
669  // send byte
670  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
671 
672  // wait until tx data register is empty with timeout
673  timeOut = USART1n_BLOCKING_TIMEOUT;
674  while( !( USART1x->ST & USART1n_SR_TXC ) )
675  {
676  if( timeOut == 0 )
677  {
678  break;
679  }
680  timeOut--;
681  }
682 
683  // if timeout
684  if( timeOut == 0 )
685  {
686  break;
687  }
688 
689  // clear flag
691 
692  // update counter
693  bToSend--;
694  bSent++;
695  }
696  }
697 
698  // Non-Blocking Mode
699  else
700  {
701  while( bToSend )
702  {
703  // if tx data register is not empty
704  if( !( USART1x->ST & USART1n_SR_DRE ) )
705  {
706  break;
707  }
708 
709  // send byte
710  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
711 
712  // update counter
713  bToSend--;
714  bSent++;
715  }
716  }
717 
718  // return
719  return bSent;
720 }
HAL_Status_Type HAL_USART_TransmitByte(USART1n_Type *USART1x, uint8_t Data)
Transmit a single data through USART peripheral.
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.

References BLOCKING, HAL_USART_ClearStatus(), HAL_USART_TransmitByte(), and USART1n_STATUS_TXC.

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◆ HAL_USART_TransmitByte()

HAL_Status_Type HAL_USART_TransmitByte ( USART1n_Type *  USART1x,
uint8_t  Data 
)

Transmit a single data through USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10 ~ USART11
[in]DataData to transmit (must be 8-bit long)
Returns
HAL_Status_Type

Definition at line 613 of file A31R71x_hal_usart1n.c.

614 {
615  /* Check USART handle */
616  if( USART1x == NULL )
617  {
618  return HAL_ERROR;
619  }
620 
621  USART1x->DR = Data;
622 
623  return HAL_OK;
624 }

References HAL_ERROR, and HAL_OK.

Referenced by HAL_USART_Transmit().

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◆ HAL_USART_UART_Mode_Config()

HAL_Status_Type HAL_USART_UART_Mode_Config ( USART1n_CFG_Type USART1n_Config)

Fills each USART1n_Config member with its default value:

  • 38400 bps
  • 8 Data Bit
  • No Parity Bit
  • 1 Stop Bit
    Parameters
    [out]USART1n_ConfigPointer to a USART1n_CFG_Type structure which will be initialized.
    Returns
    HAL_Status_Type

Definition at line 252 of file A31R71x_hal_usart1n.c.

253 {
254  /* Check USART1n_Config */
255  if( USART1n_Config == NULL )
256  {
257  return HAL_ERROR;
258  }
259 
260  USART1n_Config->Mode = USART1n_UART_MODE;
261  USART1n_Config->Baudrate = 38400;
262  USART1n_Config->Databits = USART1n_DATA_BIT_8;
263  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
264  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
265 
266  return HAL_OK;
267 }
USART1n_PARITY_BIT_Type Parity
USART1n_OPMODE_Type Mode
USART1n_DATA_BIT_Type Databits
USART1n_STOP_BIT_Type Stopbits

References USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, HAL_ERROR, HAL_OK, USART1n_CFG_Type::Mode, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_DATA_BIT_8, USART1n_PARITY_BIT_NONE, USART1n_STOP_BIT_1, and USART1n_UART_MODE.

◆ HAL_USART_USRT_Mode_Config()

HAL_Status_Type HAL_USART_USRT_Mode_Config ( USART1n_CFG_Type USART1n_Config)

Fills each USART1n_Config member with its default value:

  • 38400 bps
  • 8 Data Bit
  • No Parity Bit
  • 1 Stop Bit
    Parameters
    [out]USART1n_ConfigPointer to a USART1n_CFG_Type structure which will be initialized.
    Returns
    HAL_Status_Type

Definition at line 279 of file A31R71x_hal_usart1n.c.

280 {
281  /* Check USART1n_Config */
282  if( USART1n_Config == NULL )
283  {
284  return HAL_ERROR;
285  }
286 
287  USART1n_Config->Mode = USART1n_USRT_MODE;
288  USART1n_Config->Baudrate = 38400;
289  USART1n_Config->Databits = USART1n_DATA_BIT_8;
290  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
291  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
292 
293  // only SPI & Sync. Mode
294  USART1n_Config->Order = USART1n_SPI_LSB;
295 
296 #if 0 // CPOLn : 0, CPHAn : 0 (X)
297  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
298  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
299 #endif
300 
301 #if 1 // CPOLn : 0, CPHAn : 1 (O)
302  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
303  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
304 #endif
305 
306 #if 0 // CPOLn : 1, CPHAn : 0 (X)
307  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
308  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
309 #endif
310 
311 #if 0 // CPOLn : 1, CPHAn : 1 (O)
312  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
313  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
314 #endif
315 
316  return HAL_OK;
317 }
USART1n_EDGE_Type Edge
USART1n_PARITY_BIT_Type Parity
USART1n_SPI_ORDER_Type Order
USART1n_OPMODE_Type Mode
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
USART1n_STOP_BIT_Type Stopbits

References USART1n_CFG_Type::ACK, USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, USART1n_CFG_Type::Edge, HAL_ERROR, HAL_OK, USART1n_CFG_Type::Mode, USART1n_CFG_Type::Order, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_DATA_BIT_8, USART1n_PARITY_BIT_NONE, USART1n_SPI_LSB, USART1n_SPI_TX_FALLING, USART1n_SPI_TX_LEADEDGE_SAMPLE, USART1n_SPI_TX_LEADEDGE_SETUP, USART1n_SPI_TX_RISING, USART1n_STOP_BIT_1, and USART1n_USRT_MODE.