A31R71x F/W Packages  1.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31R71x_hal_scu.c
Go to the documentation of this file.
1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31R71x_hal_scu.h"
41 
42 /* Public Functions --------------------------------------------------------- */
43 //******************************************************************************
44 // Function
45 //******************************************************************************
46 
47 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
52 uint32_t HAL_SCU_ResetSourceStatus( void )
53 {
54  uint32_t tmp;
55 
56  tmp = SCUCC->RSTSSR; // Get reset source status
57  SCUCC->RSTSSR = 0x3FuL; // Clear all reset source status
58  return tmp;
59 }
60 
61 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
68 void HAL_SCU_SetNMI( uint32_t u32NmiCon )
69 {
70  SCUCC->NMISRCR = u32NmiCon;
71 }
72 
73 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
79 {
80  if( SCUCC->SRSTVR_b.VALID != 0x55 )
81  {
82  SCUCC_GenSwRst(); // Generate S/W reset on invalid reset
83  }
84 }
85 
86 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
93 void HAL_SCU_SetWakupData( uint32_t u32Data )
94 {
95  SCUCC->WUTDR = u32Data; // On HCLK=40MHz, (150us x 40)/32 = 187.5. So, the data should be more than 187
96 }
97 
98 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
108 void HAL_SCU_HIRCTRM_ClockConfig( uint32_t u32Ind )
109 {
110  uint32_t tmp, ntrim;
111 
112  tmp = ( SCUCC->HIRCTRM ) & 0x001fuL; // Read current fine trim value of HIRC
113  if( u32Ind == HIRC_UP_ONESTEP ) // Increment by one step(about 140kHz)
114  {
115  if( tmp != 0x0f )
116  {
117  tmp++;
118  }
119  }
120  else // Decrement by one step(about 140kHz)
121  {
122  if( tmp != 0x10 )
123  {
124  tmp--;
125  }
126  }
127  tmp &= 0x1f; // Fine trim value is only 5-bits
128  tmp |= ( ( SCUCC->HIRCTRM ) & 0x00E0uL ); // Read Coarse trim value
129  ntrim = ( tmp << 8 ) ^ 0x0000FF00; // Make write complement key
130  SCUCC->HIRCTRM = ( ( uint32_t )SCUCC_HIRCTRM_WTIDKY_Value << SCUCC_HIRCTRM_WTIDKY_Pos ) // Write new HIRC trim value with write ID and complement key
131  | ntrim
132  | tmp;
133 }
134 
135 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
145 void HAL_SCU_WDTRCTRM_ClockConfig( uint32_t u32Ind )
146 {
147  uint32_t ctmp, ftmp, ntrim;
148 
149  ftmp = ( SCUCC->WDTRCTRM ) & 0x0007uL; // Read current fine trim value of WDTRC
150  ctmp = ( SCUCC->WDTRCTRM ) & 0x00F0uL; // Read current coarse trim value of WDTRC
151  if( u32Ind == WDTRC_UP_ONESTEP ) // Increment by one step(about 1.1kHz)
152  {
153  ftmp++;
154  ftmp &= 0x07uL; // Fine trim value is only 3-bits
155  if( ftmp == 0x04 )
156  {
157  if( ctmp != 0x70 )
158  {
159  ctmp += 0x10uL;
160  }
161  else
162  {
163  ftmp = 0x03uL;
164  }
165  }
166  }
167  else // Decrement by one step(about 1.1kHz)
168  {
169  ftmp--;
170  ftmp &= 0x07uL; // Fine trim value is only 3-bits
171  if( ftmp == 0x03 )
172  {
173  if( ctmp != 0x80 )
174  {
175  ctmp -= 0x10uL;
176  }
177  else
178  {
179  ftmp = 0x04uL;
180  }
181  }
182  }
183  ctmp &= 0x00f0uL; // Coarse trim value is only 4-bits
184  ctmp |= ftmp;
185  ntrim = ( ctmp << 8 ) ^ 0x0000FF00; // Make write complement key
186  SCUCC->WDTRCTRM = ( SCUCC_WDTRCTRM_WTIDKY_Value << SCUCC_WDTRCTRM_WTIDKY_Pos ) // Write new WDTRC trim value with write ID and complement key
187  | ntrim
188  | ctmp;
189 }
190 
191 /* Public Functions --------------------------------------------------------- */
192 //******************************************************************************
193 // Function
194 //******************************************************************************
195 
196 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
207 void HAL_SCU_ClockMonitoring( uint32_t u32Acts, uint32_t u32Target )
208 {
209  if( SCUCG->CLKSRCR_b.WDTRCEN == 0 )
210  {
211  SCUCG->CLKSRCR = SCUCG->CLKSRCR
212  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
213  | CLKSRCR_WDTRCEN; // The WDTRC should be enabled to use clock monitoring
214  }
215  SCUCG->CMONCR = ( 0x3uL << 2 ) | u32Acts | u32Target; // Clear MONFLAG and NMINTFG, Set Monitoring Target and Monitoring Action
216  SCUCG->CMONCR_b.MONEN = 1; // Clock Monitoring Enable
217 }
218 
219 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
227 {
228  SCUCG->CMONCR_b.MACTS = 0; // Clear MACTS bits first
229  SCUCG->CMONCR_b.MONEN = 0; // Disable clock monitoring function
230 }
231 
232 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
249 void HAL_SCU_ClockSource_Config( uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc )
250 {
251  uint32_t tmp;
252 
253  tmp = SCUCG->CLKSRCR & 0x0000000F;
254  tmp |= ( ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
255  | u32FreIRC // HIRC Frequency
256  | u32TypeXM // XMOSC type: x-tal or external clock
257  | u32ClkSrc );
258  SCUCG->CLKSRCR = tmp;
259 }
260 
261 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
278 void HAL_SCU_ClockSource_Enable( uint32_t u32ClkSrc, uint32_t u32HircDiv )
279 {
280 #if 0 // before bug fix
281  uint32_t tmp;
282 
283  tmp = SCUCG->CLKSRCR & 0x0000FFFF; // 0x00000fff°¡ ¿ÇÀ» µí...
284  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
285  tmp |= u32ClkSrc;
286  tmp |= u32HircDiv;
287  SCUCG->CLKSRCR = tmp;
288 #else // after bug fix
289  SCUCG->CLKSRCR = SCUCG->CLKSRCR
290  & ~( SCUCG_CLKSRCR_WTIDKY_Msk | SCUCG_CLKSRCR_HIRCSEL_Msk )
291  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
292  | u32HircDiv
293  | u32ClkSrc
294  ;
295 #endif
296 }
297 
298 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
312 void HAL_SCU_ClockSource_Disable( uint32_t u32ClkSrc )
313 {
314  uint32_t tmp;
315 
316  tmp = SCUCG->CLKSRCR & 0x0000FFFF;
317  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
318  tmp &= ~u32ClkSrc;
319  SCUCG->CLKSRCR = tmp;
320 }
321 
322 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
331 void HAL_SCU_MainXtal_PinConfig( uint32_t u32XtalFilter )
332 {
333  PF->AFSR1 &= 0xFFFFFF00; // PF[1:0]: XIN/XOUT
334  PF->PUPD &= 0xFFFFF0uL; // PF[1:0]: Pull-up/down resistors Disable
335  PF->MOD &= 0xFFFFF0uL;
336  PF->MOD |= 0x000AuL; // PF[1:0]: Alternative Function
337  SCUCG->XTFLSR = ( ( uint32_t )SCUCG_XTFLSR_WTIDKY_Value << SCUCG_XTFLSR_WTIDKY_Pos ) // Write ID
338  | u32XtalFilter; // x-tal filter value
339 }
340 
341 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
347 {
348  PF->AFSR1 &= 0xFFFF00FF; // PF[3:2]: SXIN/SXOUT
349  PF->PUPD &= 0xFFFF0FuL; // PF[3:2]: Pull-up/down resistors Disable
350  PF->MOD &= 0xFFFF0FuL;
351  PF->MOD |= 0x00A0uL; // PF[3:2]: Alternative Function
352 }
353 
354 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
362 void HAL_SCU_SystemClockChange( uint32_t u32Target )
363 {
364  SCUCG->SCCR = ( SCUCG_SCCR_WTIDKY_Value << SCUCG_SCCR_WTIDKY_Pos ) // Write ID
365  | u32Target; // Target Clock Source
366 }
367 
368 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
385 void HAL_SCU_SystemClockDivider( uint32_t u32Div02, uint32_t u32Div13 )
386 {
387  // Divider 0 for HCLK: 000/001/010/011/100: MCLK is divided by 16/8/4/2/1
388  // Divider 2 for WT and LCD Driver: 000/001/010/011/100: MCLK is divided by 64/128/256/512/1024
389  SCUCG->SCDIVR1 = u32Div02;
390 
391  // Divider 1 for PCLK: 00/01/10/11: HCLK is divided by 1/2/4/8
392  // Divider 3 for SysTick Timer: 00/01/10/11: HCLK is divided by 1/2/4/8
393  SCUCG->SCDIVR2 = u32Div13;
394 }
395 
396 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
402 {
403  PF->AFSR1 &= 0xFFF0FFFF; // PF4 VREG 0: CLKO 1: VREG 2: ---- 3: ---- 4: ----
404  PF->PUPD &= 0xFFFCFFuL; // PF4 VREG 0: Disable Pull-Up/Down 1: Enable Pull-Up 2: Enable Pull-Down
405  PF->MOD &= 0xFFFCFFuL; // PF4 VREG 0: Input Mode 1: Output Mode 2: Alternative Function Mode
406  PF->MOD |= 0x0200uL; // PF4 VREG 0: Input Mode 1: Output Mode 2: Alternative Function Mode
407 }
408 
409 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
426 void HAL_SCU_ClockOutput( uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div )
427 {
428  SCUCG->CLKOCR = 0
429  | ( 1 << SCUCG_CLKOCR_CLKOEN_Pos ) // CLKO Enable
430  | u32Level // 0: Low Level 1: High Level
431  | u32Div // 0: div_1 1: div_2 2: div_4 3: div_8 4: div_16 5: div_32 6: div_64 7: div_128
432  | u32ClkSrc // 0: MCLK 1: WDTRC 2: HIRC 3: HCLK 4: PCLK
433  ;
434 }
435 
436 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
446 void HAL_SCU_Peripheral_ClockConfig( uint32_t u32PeriClk1, uint32_t u32PeriClk2 )
447 {
448  SCUCG->PPCLKEN1 = u32PeriClk1; // Set peripheral clock of timers and ports
449  SCUCG->PPCLKEN2 = u32PeriClk2; // Set peripheral clock of the others
450 }
451 
452 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
464 void HAL_SCU_Peripheral_EnableClock1( uint32_t u32PeriClk1, uint32_t Ind )
465 {
466  if( Ind )
467  {
468  SCUCG->PPCLKEN1 |= u32PeriClk1; // Enable a peripheral clock of timers and ports
469  }
470  else
471  {
472  SCUCG->PPCLKEN1 &= ~u32PeriClk1; // Disable a peripheral clock of timers and ports
473  }
474 }
475 
476 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
489 void HAL_SCU_Peripheral_EnableClock2( uint32_t u32PeriClk2, uint32_t u32Ind )
490 {
491  if( u32Ind )
492  {
493  SCUCG->PPCLKEN2 |= u32PeriClk2; // Enable a peripheral clock of others
494  }
495  else
496  {
497  SCUCG->PPCLKEN2 &= ~u32PeriClk2; // Disable a peripheral clock of others
498  }
499 }
500 
501 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
511 void HAL_SCU_Peripheral_ResetConfig( uint32_t u32PeriRst1, uint32_t u32PeriRst2 )
512 {
513  uint32_t i;
514 
515  SCUCG->PPRST1 = u32PeriRst1; // Reset peripheral block of timers and ports if the corresponding bit is "1b"
516  SCUCG->PPRST2 = u32PeriRst2; // Reset peripheral block of the others
517  for( i = 0 ; i < 10 ; i++ )
518  {
519  NOP();
520  }
521  SCUCG->PPRST1 = 0x0uL; // Clear the peripheral reset bits
522  SCUCG->PPRST2 = 0x0uL;
523 }
524 
525 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
533 void HAL_SCU_Peripheral_SetReset1( uint32_t u32EachPeri1 )
534 {
535  uint32_t i;
536 
537  SCUCG->PPRST1 = u32EachPeri1; // Reset a peripheral block
538  for( i = 0 ; i < 10 ; i++ )
539  {
540  NOP();
541  }
542  SCUCG->PPRST1 = 0; // Clear the peripheral reset bit
543 }
544 
545 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
554 void HAL_SCU_Peripheral_SetReset2( uint32_t u32EachPeri2 )
555 {
556  uint32_t i;
557 
558  SCUCG->PPRST2 = u32EachPeri2; // Reset a peripheral block
559  for( i = 0 ; i < 10 ; i++ )
560  {
561  NOP();
562  }
563  SCUCG->PPRST2 = 0; // Clear the peripheral reset bit
564 }
565 
566 
567 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
580 void HAL_SCU_Peripheral_ClockSelection( uint32_t u32Peri, uint32_t u32ClkSrc )
581 {
582  SCUCG->PPCLKSR &= ~u32Peri;
583  SCUCG->PPCLKSR |= u32ClkSrc;
584 }
585 
void HAL_SCU_SetNMI(uint32_t u32NmiCon)
Set Non-Maskable Interrupt(NMI) Source Selection Register.
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_ClockMonitoring_Disable(void)
Disable Clock Monitoring.
void HAL_SCU_SoftwareReset_Config(void)
Check whether system reset ok or not. Generate s/w reset if a weak reset.
void HAL_SCU_SubXtal_PinConfig(void)
Set XSOSC Pins for x-tal.
Contains all macro definitions and function prototypes support for scu firmware library on A31R71x.
void HAL_SCU_ClockSource_Config(uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
Set Clock Source, HIRC Frequency, and type of XMOSC.
void HAL_SCU_ClockOutput(uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
Set Configuration for Clock Output.
void HAL_SCU_ClockSource_Disable(uint32_t u32ClkSrc)
Disable Clock Source.
void HAL_SCU_WDTRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of WDTRC by one step.
void HAL_SCU_CLKO_PinConfig(void)
Set CLKO Pin for Clock Output.
void HAL_SCU_ClockSource_Enable(uint32_t u32ClkSrc, uint32_t u32HircDiv)
Enable Clock Source.
void HAL_SCU_Peripheral_ClockConfig(uint32_t u32PeriClk1, uint32_t u32PeriClk2)
Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".
void HAL_SCU_ClockMonitoring(uint32_t u32Acts, uint32_t u32Target)
Configure Clock Monitoring.
void HAL_SCU_MainXtal_PinConfig(uint32_t u32XtalFilter)
Set XMOSC Pins for x-tal.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_SetWakupData(uint32_t u32Data)
Set Wake-Up Timer Data.
void HAL_SCU_HIRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of HIRC by one step.
void HAL_SCU_Peripheral_ClockSelection(uint32_t u32Peri, uint32_t u32ClkSrc)
Peripheral Clock Selection of PPCLKSR Register.
void HAL_SCU_SystemClockDivider(uint32_t u32Div02, uint32_t u32Div13)
Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick T...
uint32_t HAL_SCU_ResetSourceStatus(void)
Get Reset Source Status.
void HAL_SCU_Peripheral_SetReset1(uint32_t u32EachPeri1)
Set/Reset Each Peripheral Block Reset of PPRST1 Register.
void HAL_SCU_SystemClockChange(uint32_t u32Target)
Change System Clock.
void HAL_SCU_Peripheral_ResetConfig(uint32_t u32PeriRst1, uint32_t u32PeriRst2)
Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".