50 #define TIMER1n_DISABLE (0x0uL << 15) 51 #define TIMER1n_ENABLE (0x1uL << 15) 54 #define TIMER1n_CLKINT (0x0uL << 14) 55 #define TIMER1n_CLKEXT (0x1uL << 14) 58 #define TIMER1n_CNTM (0x0uL << 12) 59 #define TIMER1n_CAPM (0x1uL << 12) 60 #define TIMER1n_PPGONEM (0x2uL << 12) 61 #define TIMER1n_PPGREM (0x3uL << 12) 64 #define TIMER1n_FEDGE (0x0uL << 11) 65 #define TIMER1n_REDGE (0x1uL << 11) 68 #define TIMER1n_STHIGH (0x0uL << 8) 69 #define TIMER1n_STLOW (0x1uL << 8) 72 #define TIMER1n_CAPFALL (0x0uL << 6) 73 #define TIMER1n_CAPRISE (0x1uL << 6) 74 #define TIMER1n_CAPBOTH (0x2uL << 6) 77 #define TIMER1n_MATINTEN (0x1uL << 5) 78 #define TIMER1n_MATINTDIS (0x0uL << 5) 81 #define TIMER1n_CAPINTEN (0x1uL << 4) 82 #define TIMER1n_CAPINTDIS (0x0uL << 4) 84 #define TIMER1n_PRS_MASK 0x0FFF 185 #define TIMER1n_EN( TIMER1x ) (TIMER1x->CR_b.T1nEN = 1) 186 #define TIMER1n_DIS( TIMER1x ) (TIMER1x->CR_b.T1nEN = 0) 194 #define TIMER1n_ConCnt( TIMER1x ) (TIMER1x->CR_b.T1nPAU = 0) 195 #define TIMER1n_TempPau( TIMER1x ) (TIMER1x->CR_b.T1nPAU = 1) 203 #define TIMER1n_ClrCnt( TIMER1x ) (TIMER1x->CR_b.T1nCLR = 1) 211 #define TIMER1n_GetCnt( TIMER1x ) (TIMER1x->CNT) 221 #define TIMER1n_SetAData( TIMER1x, u32AData ) (TIMER1x->ADR = u32AData) 231 #define TIMER1n_SetBData( TIMER1x, u32BData ) (TIMER1x->BDR = u32BData) 239 #define TIMER1n_GetCapData( TIMER1x ) (TIMER1x->CAPDR) 247 #define T1nMaInt_GetFg( TIMER1x ) (TIMER1x->CR_b.T1nMIFLAG) 255 #define T1nMaInt_ClrFg( TIMER1x ) (TIMER1x->CR_b.T1nMIFLAG = 1) 263 #define T1nCapInt_GetFg( TIMER1x ) (TIMER1x->CR_b.T1nCIFLAG) 271 #define T1nCapInt_ClrFg( TIMER1x ) (TIMER1x->CR_b.T1nCIFLAG = 1) 277 #define TIMER1n_CR_CKSEL_MASK (TIMER1n_CR_T1nCLK_Msk) 278 #define TIMER1n_CR_CKSEL_SET( n ) (n << TIMER1n_CR_T1nCLK_Pos) 280 #define TIMER1n_CR_MODE_MASK (TIMER1n_CR_T1nMS_Msk) 281 #define TIMER1n_CR_MODE_SET( n ) (n << TIMER1n_CR_T1nMS_Pos) 283 #define TIMER1n_CR_ECE_MASK (TIMER1n_CR_T1nECE_Msk) 284 #define TIMER1n_CR_ECE_SET( n ) (n << TIMER1n_CR_T1nECE_Pos) 286 #define TIMER1n_CR_STARTLVL_MASK (TIMER1n_CR_T1nOPOL_Msk) 287 #define TIMER1n_CR_STARTLVL_SET( n ) (n << TIMER1n_CR_T1nOPOL_Pos) 289 #define TIMER1n_CR_CPOL_MASK (TIMER1n_CR_T1nCPOL_Msk) 290 #define TIMER1n_CR_CPOL_SET( n ) (n << TIMER1n_CR_T1nCPOL_Pos)
HAL_Status_Type HAL_TIMER1n_SetRegister(TIMER1n_Type *TIMER1x, uint32_t u32T1nSet, uint32_t u32T1nClk)
Set TIMER1n CR/PREDR Registers.
HAL_Status_Type HAL_TIMER1n_ConfigInterrupt(TIMER1n_Type *TIMER1x, TIMER1n_INT_Type TIMER1n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
HAL_Status_Type HAL_TIMER1n_Cmd(TIMER1n_Type *TIMER1x, FunctionalState NewState)
Start/Stop Timer/Counter device.
HAL_Status_Type HAL_TIMER1n_DeInit(TIMER1n_Type *TIMER1x)
Close Timer/Counter device.
HAL_Status_Type HAL_TIMER1n_Init(TIMER1n_Type *TIMER1x, TIMER1n_MODE_OPT TimerCounterMode, void *TIMER1n_Config)
Initialize the TIMER1n peripheral with the specified parameters.
Contains the ABOV typedefs for C standard types. It is intended to be used in ISO C conforming develo...
struct TIMER1n_PWMCFG_Type TIMER1n_ONESHOTCFG_Type