57 SCUCC->RSTSSR = 0x3FuL;
70 SCUCC->NMISRCR = u32NmiCon;
80 if( SCUCC->SRSTVR_b.VALID != 0x55 )
95 SCUCC->WUTDR = u32Data;
112 tmp = ( SCUCC->HIRCTRM ) & 0x001fuL;
113 if( u32Ind == HIRC_UP_ONESTEP )
128 tmp |= ( ( SCUCC->HIRCTRM ) & 0x00E0uL );
129 ntrim = ( tmp << 8 ) ^ 0x0000FF00;
130 SCUCC->HIRCTRM = ( ( uint32_t )SCUCC_HIRCTRM_WTIDKY_Value << SCUCC_HIRCTRM_WTIDKY_Pos )
147 uint32_t ctmp, ftmp, ntrim;
149 ftmp = ( SCUCC->WDTRCTRM ) & 0x0007uL;
150 ctmp = ( SCUCC->WDTRCTRM ) & 0x00F0uL;
151 if( u32Ind == WDTRC_UP_ONESTEP )
185 ntrim = ( ctmp << 8 ) ^ 0x0000FF00;
186 SCUCC->WDTRCTRM = ( SCUCC_WDTRCTRM_WTIDKY_Value << SCUCC_WDTRCTRM_WTIDKY_Pos )
209 if( SCUCG->CLKSRCR_b.WDTRCEN == 0 )
211 SCUCG->CLKSRCR = SCUCG->CLKSRCR
212 | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
215 SCUCG->CMONCR = ( 0x3uL << 2 ) | u32Acts | u32Target;
216 SCUCG->CMONCR_b.MONEN = 1;
228 SCUCG->CMONCR_b.MACTS = 0;
229 SCUCG->CMONCR_b.MONEN = 0;
253 tmp = SCUCG->CLKSRCR & 0x0000000F;
254 tmp |= ( ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
258 SCUCG->CLKSRCR = tmp;
280 #if 0 // before bug fix 283 tmp = SCUCG->CLKSRCR & 0x0000FFFF;
284 tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos );
287 SCUCG->CLKSRCR = tmp;
288 #else // after bug fix 289 SCUCG->CLKSRCR = SCUCG->CLKSRCR
290 & ~( SCUCG_CLKSRCR_WTIDKY_Msk | SCUCG_CLKSRCR_HIRCSEL_Msk )
291 | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
316 tmp = SCUCG->CLKSRCR & 0x0000FFFF;
317 tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos );
319 SCUCG->CLKSRCR = tmp;
333 PF->AFSR1 &= 0xFFFFFF00;
334 PF->PUPD &= 0xFFFFF0uL;
335 PF->MOD &= 0xFFFFF0uL;
337 SCUCG->XTFLSR = ( ( uint32_t )SCUCG_XTFLSR_WTIDKY_Value << SCUCG_XTFLSR_WTIDKY_Pos )
348 PF->AFSR1 &= 0xFFFF00FF;
349 PF->PUPD &= 0xFFFF0FuL;
350 PF->MOD &= 0xFFFF0FuL;
364 SCUCG->SCCR = ( SCUCG_SCCR_WTIDKY_Value << SCUCG_SCCR_WTIDKY_Pos )
389 SCUCG->SCDIVR1 = u32Div02;
393 SCUCG->SCDIVR2 = u32Div13;
403 PF->AFSR1 &= 0xFFF0FFFF;
404 PF->PUPD &= 0xFFFCFFuL;
405 PF->MOD &= 0xFFFCFFuL;
429 | ( 1 << SCUCG_CLKOCR_CLKOEN_Pos )
448 SCUCG->PPCLKEN1 = u32PeriClk1;
449 SCUCG->PPCLKEN2 = u32PeriClk2;
468 SCUCG->PPCLKEN1 |= u32PeriClk1;
472 SCUCG->PPCLKEN1 &= ~u32PeriClk1;
493 SCUCG->PPCLKEN2 |= u32PeriClk2;
497 SCUCG->PPCLKEN2 &= ~u32PeriClk2;
515 SCUCG->PPRST1 = u32PeriRst1;
516 SCUCG->PPRST2 = u32PeriRst2;
517 for( i = 0 ; i < 10 ; i++ )
521 SCUCG->PPRST1 = 0x0uL;
522 SCUCG->PPRST2 = 0x0uL;
537 SCUCG->PPRST1 = u32EachPeri1;
538 for( i = 0 ; i < 10 ; i++ )
558 SCUCG->PPRST2 = u32EachPeri2;
559 for( i = 0 ; i < 10 ; i++ )
582 SCUCG->PPCLKSR &= ~u32Peri;
583 SCUCG->PPCLKSR |= u32ClkSrc;
void HAL_SCU_SetNMI(uint32_t u32NmiCon)
Set Non-Maskable Interrupt(NMI) Source Selection Register.
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_ClockMonitoring_Disable(void)
Disable Clock Monitoring.
void HAL_SCU_SoftwareReset_Config(void)
Check whether system reset ok or not. Generate s/w reset if a weak reset.
void HAL_SCU_SubXtal_PinConfig(void)
Set XSOSC Pins for x-tal.
Contains all macro definitions and function prototypes support for scu firmware library on A31R71x.
void HAL_SCU_ClockSource_Config(uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
Set Clock Source, HIRC Frequency, and type of XMOSC.
void HAL_SCU_ClockOutput(uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
Set Configuration for Clock Output.
void HAL_SCU_ClockSource_Disable(uint32_t u32ClkSrc)
Disable Clock Source.
void HAL_SCU_WDTRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of WDTRC by one step.
void HAL_SCU_CLKO_PinConfig(void)
Set CLKO Pin for Clock Output.
void HAL_SCU_ClockSource_Enable(uint32_t u32ClkSrc, uint32_t u32HircDiv)
Enable Clock Source.
void HAL_SCU_Peripheral_ClockConfig(uint32_t u32PeriClk1, uint32_t u32PeriClk2)
Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".
void HAL_SCU_ClockMonitoring(uint32_t u32Acts, uint32_t u32Target)
Configure Clock Monitoring.
void HAL_SCU_MainXtal_PinConfig(uint32_t u32XtalFilter)
Set XMOSC Pins for x-tal.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_SetWakupData(uint32_t u32Data)
Set Wake-Up Timer Data.
void HAL_SCU_HIRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of HIRC by one step.
void HAL_SCU_Peripheral_ClockSelection(uint32_t u32Peri, uint32_t u32ClkSrc)
Peripheral Clock Selection of PPCLKSR Register.
void HAL_SCU_SystemClockDivider(uint32_t u32Div02, uint32_t u32Div13)
Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick T...
uint32_t HAL_SCU_ResetSourceStatus(void)
Get Reset Source Status.
void HAL_SCU_Peripheral_SetReset1(uint32_t u32EachPeri1)
Set/Reset Each Peripheral Block Reset of PPRST1 Register.
void HAL_SCU_SystemClockChange(uint32_t u32Target)
Change System Clock.
void HAL_SCU_Peripheral_ResetConfig(uint32_t u32PeriRst1, uint32_t u32PeriRst2)
Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".