A31R71x F/W Packages  1.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31R71x_hal_timer1n.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31R71x_hal_scu.h"
41 #include "A31R71x_hal_timer1n.h"
42 
43 /* Public Functions --------------------------------------------------------- */
44 //******************************************************************************
45 // Function
46 //******************************************************************************
47 
48 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
66 HAL_Status_Type HAL_TIMER1n_Init( TIMER1n_Type* TIMER1x, TIMER1n_MODE_OPT TimerCounterMode, void* TIMER1n_Config )
67 {
68  TIMER1n_PERIODICCFG_Type* pTimeCfg;
69  TIMER1n_PWMCFG_Type* pPwmOneshotCfg;
70  TIMER1n_CAPTURECFG_Type* pCaptureCfg;
71  uint16_t reg_val16;
72 
73  /* Check TIMER1 handle */
74  if( TIMER1x == NULL )
75  {
76  return HAL_ERROR;
77  }
78 
79 #if 1 // supported
80  if( TIMER1x == ( TIMER1n_Type* )TIMER10 )
81  {
82  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T10CLKE, PPxCLKE_Enable );
83  }
84 #endif
85 
86 #if 1 // supported
87  if( TIMER1x == ( TIMER1n_Type* )TIMER11 )
88  {
89  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T11CLKE, PPxCLKE_Enable );
90  }
91 #endif
92 
93 #if 1 // supported
94  if( TIMER1x == ( TIMER1n_Type* )TIMER12 )
95  {
96  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T12CLKE, PPxCLKE_Enable );
97  }
98 #endif
99 
100 #if 1 // supported
101  if( TIMER1x == ( TIMER1n_Type* )TIMER13 )
102  {
103  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T13CLKE, PPxCLKE_Enable );
104  }
105 #endif
106 
107 #if 1 // supported
108  if( TIMER1x == ( TIMER1n_Type* )TIMER14 )
109  {
110  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T14CLKE, PPxCLKE_Enable );
111  }
112 #endif
113 
114 #if 1 // supported
115  if( TIMER1x == ( TIMER1n_Type* )TIMER15 )
116  {
117  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T15CLKE, PPxCLKE_Enable );
118  }
119 #endif
120 
121 #if 0 // not supported
122  if( TIMER1x == ( TIMER1n_Type* )TIMER16 )
123  {
124  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T16CLKE, PPxCLKE_Enable );
125  }
126 #endif
127 
128  if( TimerCounterMode == TIMER1n_PERIODIC_MODE )
129  {
130  pTimeCfg = ( TIMER1n_PERIODICCFG_Type* )TIMER1n_Config;
131 
132  reg_val16 = 0
133  | TIMER1n_CR_CKSEL_SET( pTimeCfg->CkSel )
134  | TIMER1n_CR_MODE_SET( TimerCounterMode )
135  | TIMER1n_CR_STARTLVL_SET( pTimeCfg->StartLevel )
136  ;
137  if( pTimeCfg->CkSel == 1 )
138  {
139  reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pTimeCfg->ECE );
140  }
141  TIMER1x->CR = reg_val16;
142 
143  TIMER1x->PREDR = ( ( pTimeCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
144  TIMER1x->ADR = pTimeCfg->ADR;
145  }
146  else if( ( TimerCounterMode == TIMER1n_PWM_MODE ) || ( TimerCounterMode == TIMER1n_ONESHOT_MODE ) )
147  {
148  pPwmOneshotCfg = ( TIMER1n_PWMCFG_Type* )TIMER1n_Config;
149 
150  reg_val16 = 0
151  | TIMER1n_CR_CKSEL_SET( pPwmOneshotCfg->CkSel )
152  | TIMER1n_CR_MODE_SET( TimerCounterMode )
153  | TIMER1n_CR_STARTLVL_SET( pPwmOneshotCfg->StartLevel )
154  ;
155  if( pPwmOneshotCfg->CkSel == 1 )
156  {
157  reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pPwmOneshotCfg->ECE );
158  }
159  TIMER1x->CR = reg_val16;
160 
161  TIMER1x->PREDR = ( ( pPwmOneshotCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
162  TIMER1x->ADR = pPwmOneshotCfg->ADR;
163  TIMER1x->BDR = pPwmOneshotCfg->BDR;
164  }
165  else if( TimerCounterMode == TIMER1n_CAPTURE_MODE )
166  {
167  pCaptureCfg = ( TIMER1n_CAPTURECFG_Type* )TIMER1n_Config;
168 
169  reg_val16 = 0
170  | TIMER1n_CR_CKSEL_SET( pCaptureCfg->CkSel )
171  | TIMER1n_CR_MODE_SET( TimerCounterMode )
172  | TIMER1n_CR_CPOL_SET( pCaptureCfg->ClrMode )
173  ;
174  if( pCaptureCfg->CkSel == 1 )
175  {
176  reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pCaptureCfg->ECE );
177  }
178  TIMER1x->CR = reg_val16;
179 
180  TIMER1x->PREDR = ( ( pCaptureCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
181  TIMER1x->ADR = pCaptureCfg->ADR;
182  }
183  TIMER1x->CR |= 0x1; // timer counter clear
184 
185  return HAL_OK;
186 }
187 
188 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
195 HAL_Status_Type HAL_TIMER1n_DeInit( TIMER1n_Type* TIMER1x )
196 {
197  /* Check TIMER1 handle */
198  if( TIMER1x == NULL )
199  {
200  return HAL_ERROR;
201  }
202 
203  // Disable timer/counter
204  TIMER1x->CR = 0x00;
205 
206 #if 1 // supported
207  if( TIMER1x == ( TIMER1n_Type* )TIMER10 )
208  {
209  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T10CLKE, PPxCLKE_Disable );
210  }
211 #endif
212 
213 #if 1 // supported
214  if( TIMER1x == ( TIMER1n_Type* )TIMER11 )
215  {
216  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T11CLKE, PPxCLKE_Disable );
217  }
218 #endif
219 
220 #if 1 // supported
221  if( TIMER1x == ( TIMER1n_Type* )TIMER12 )
222  {
223  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T12CLKE, PPxCLKE_Disable );
224  }
225 #endif
226 
227 #if 1 // supported
228  if( TIMER1x == ( TIMER1n_Type* )TIMER13 )
229  {
230  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T13CLKE, PPxCLKE_Disable );
231  }
232 #endif
233 
234 #if 1 // supported
235  if( TIMER1x == ( TIMER1n_Type* )TIMER14 )
236  {
237  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T14CLKE, PPxCLKE_Disable );
238  }
239 #endif
240 
241 #if 1 // supported
242  if( TIMER1x == ( TIMER1n_Type* )TIMER15 )
243  {
244  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T15CLKE, PPxCLKE_Disable );
245  }
246 #endif
247 
248 #if 0 // not supported
249  if( TIMER1x == ( TIMER1n_Type* )TIMER16 )
250  {
251  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T16CLKE, PPxCLKE_Disable );
252  }
253 #endif
254 
255  return HAL_OK;
256 }
257 
258 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
272 HAL_Status_Type HAL_TIMER1n_ConfigInterrupt( TIMER1n_Type* TIMER1x, TIMER1n_INT_Type TIMER1n_IntCfg, FunctionalState NewState )
273 {
274  uint8_t tmp;
275 
276  /* Check TIMER1 handle */
277  if( TIMER1x == NULL )
278  {
279  return HAL_ERROR;
280  }
281 
282  switch( TIMER1n_IntCfg )
283  {
284  case TIMER1n_INTCFG_MIE:
285  tmp = TIMER1n_MATINTEN;
286  break;
287  case TIMER1n_INTCFG_CIE:
288  tmp = TIMER1n_CAPINTEN;
289  break;
290  }
291 
292  if( NewState == ENABLE )
293  {
294  TIMER1x->CR |= tmp;
295  }
296  else
297  {
298  TIMER1x->CR &= ( ~tmp );
299  }
300 
301  return HAL_OK;
302 }
303 
304 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
314 HAL_Status_Type HAL_TIMER1n_Cmd( TIMER1n_Type* TIMER1x, FunctionalState NewState )
315 {
316  /* Check TIMER1 handle */
317  if( TIMER1x == NULL )
318  {
319  return HAL_ERROR;
320  }
321 
322  if( NewState == ENABLE )
323  {
324  TIMER1x->CR |= TIMER1n_ENABLE;
325  }
326  else
327  {
328  TIMER1x->CR &= ~TIMER1n_ENABLE;
329  }
330 
331  return HAL_OK;
332 }
333 
334 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
347 HAL_Status_Type HAL_TIMER1n_SetRegister( TIMER1n_Type* TIMER1x, uint32_t u32T1nSet, uint32_t u32T1nClk )
348 {
349  /* Check TIMER1 handle */
350  if( TIMER1x == NULL )
351  {
352  return HAL_ERROR;
353  }
354 
355  TIMER1x->CR = u32T1nSet; // Setting TIMER1n Control Register
356 
357  TIMER1x->PREDR = u32T1nClk; // Setting TIMER1n Prescaler data
358 
359  return HAL_OK;
360 }
361 
HAL_Status_Type
HAL_Status_Type HAL_TIMER1n_Cmd(TIMER1n_Type *TIMER1x, FunctionalState NewState)
Start/Stop Timer/Counter device.
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_TIMER1n_Init(TIMER1n_Type *TIMER1x, TIMER1n_MODE_OPT TimerCounterMode, void *TIMER1n_Config)
Initialize the TIMER1n peripheral with the specified parameters.
FunctionalState
TIMER1n_INT_Type
Contains all macro definitions and function prototypes support for scu firmware library on A31R71x.
Contains all macro definitions and function prototypes support for timer1n firmware library on A31R71...
TIMER1n_MODE_OPT
HAL_Status_Type HAL_TIMER1n_DeInit(TIMER1n_Type *TIMER1x)
Close Timer/Counter device.
HAL_Status_Type HAL_TIMER1n_SetRegister(TIMER1n_Type *TIMER1x, uint32_t u32T1nSet, uint32_t u32T1nClk)
Set TIMER1n CR/PREDR Registers.
HAL_Status_Type HAL_TIMER1n_ConfigInterrupt(TIMER1n_Type *TIMER1x, TIMER1n_INT_Type TIMER1n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.