A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31L12x_hal_scu.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31L12x_hal_scu.h"
41 
42 /* Public Functions --------------------------------------------------------- */
43 //******************************************************************************
44 // Function
45 //******************************************************************************
46 
47 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
52 uint32_t HAL_SCU_ResetSourceStatus( void )
53 {
54  uint32_t tmp;
55 
56  tmp = SCUCC->RSTSSR; // Get reset source status
57 #if 0 // before bug fix
58  SCUCC->RSTSSR = 0x3FuL; // Clear all reset source status
59 #else // after bug fix
60  SCUCC->RSTSSR = 0x7fuL; // Clear all reset source status
61 #endif
62  return tmp;
63 }
64 
65 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
72 void HAL_SCU_SetNMI( uint32_t u32NmiCon )
73 {
74  SCUCC->NMISRCR = u32NmiCon;
75 }
76 
77 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
83 {
84  if( SCUCC->SRSTVR_b.VALID != 0x55 )
85  {
86  SCUCC_GenSwRst(); // Generate S/W reset on invalid reset
87  }
88 }
89 
90 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
98 void HAL_SCU_SetWakupData( uint32_t u32Data )
99 {
100  SCUCC->WUTDR = u32Data;
101 }
102 
103 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
113 void HAL_SCU_HIRCTRM_ClockConfig( uint32_t u32Ind )
114 {
115  uint32_t tmp, ntrim;
116 
117  tmp = ( SCUCC->HIRCTRM ) & 0x001fuL; // Read current fine trim value of HIRC
118  if( u32Ind == HIRC_UP_ONESTEP ) // Increment by one step(about 140kHz)
119  {
120  if( tmp != 0x0f )
121  {
122  tmp++;
123  }
124  }
125  else // Decrement by one step(about 140kHz)
126  {
127  if( tmp != 0x10 )
128  {
129  tmp--;
130  }
131  }
132  tmp &= 0x1f; // Fine trim value is only 5-bits
133  tmp |= ( ( SCUCC->HIRCTRM ) & 0x00E0uL ); // Read Coarse trim value
134  ntrim = ( tmp << 8 ) ^ 0x0000FF00; // Make write complement key
135  SCUCC->HIRCTRM = ( ( uint32_t )SCUCC_HIRCTRM_WTIDKY_Value << SCUCC_HIRCTRM_WTIDKY_Pos ) // Write new HIRC trim value with write ID and complement key
136  | ntrim
137  | tmp;
138 }
139 
140 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
150 void HAL_SCU_WDTRCTRM_ClockConfig( uint32_t u32Ind )
151 {
152  uint32_t ctmp, ftmp, ntrim;
153 
154  ftmp = ( SCUCC->WDTRCTRM ) & 0x0007uL; // Read current fine trim value of WDTRC
155  ctmp = ( SCUCC->WDTRCTRM ) & 0x00F0uL; // Read current coarse trim value of WDTRC
156  if( u32Ind == WDTRC_UP_ONESTEP ) // Increment by one step(about 1.1kHz)
157  {
158  ftmp++;
159  ftmp &= 0x07uL; // Fine trim value is only 3-bits
160  if( ftmp == 0x04 )
161  {
162  if( ctmp != 0x70 )
163  {
164  ctmp += 0x10uL;
165  }
166  else
167  {
168  ftmp = 0x03uL;
169  }
170  }
171  }
172  else // Decrement by one step(about 1.1kHz)
173  {
174  ftmp--;
175  ftmp &= 0x07uL; // Fine trim value is only 3-bits
176  if( ftmp == 0x03 )
177  {
178  if( ctmp != 0x80 )
179  {
180  ctmp -= 0x10uL;
181  }
182  else
183  {
184  ftmp = 0x04uL;
185  }
186  }
187  }
188  ctmp &= 0x00f0uL; // Coarse trim value is only 4-bits
189  ctmp |= ftmp;
190  ntrim = ( ctmp << 8 ) ^ 0x0000FF00; // Make write complement key
191  SCUCC->WDTRCTRM = ( SCUCC_WDTRCTRM_WTIDKY_Value << SCUCC_WDTRCTRM_WTIDKY_Pos ) // Write new WDTRC trim value with write ID and complement key
192  | ntrim
193  | ctmp;
194 }
195 
196 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
207 void HAL_SCU_ClockMonitoring( uint32_t u32Acts, uint32_t u32Target )
208 {
209  if( SCUCG->CLKSRCR_b.WDTRCEN == 0 )
210  {
211  SCUCG->CLKSRCR = SCUCG->CLKSRCR
212  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
213  | CLKSRCR_WDTRCEN; // The WDTRC should be enabled to use clock monitoring
214  }
215  SCUCG->CMONCR = ( 0x3uL << 2 ) | u32Acts | u32Target; // Clear MONFLAG and NMINTFG, Set Monitoring Target and Monitoring Action
216  SCUCG->CMONCR_b.MONEN = 1; // Clock Monitoring Enable
217 }
218 
219 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
227 {
228  SCUCG->CMONCR_b.MACTS = 0; // Clear MACTS bits first
229  SCUCG->CMONCR_b.MONEN = 0; // Disable clock monitoring function
230 }
231 
232 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
249 void HAL_SCU_ClockSource_Config( uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc )
250 {
251  uint32_t tmp;
252 
253  tmp = SCUCG->CLKSRCR & 0x0000000F;
254  tmp |= ( ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
255  | u32FreIRC // HIRC Frequency
256  | u32TypeXM // XMOSC type: x-tal or external clock
257  | u32ClkSrc );
258  SCUCG->CLKSRCR = tmp;
259 }
260 
261 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
278 void HAL_SCU_ClockSource_Enable( uint32_t u32ClkSrc, uint32_t u32HircDiv )
279 {
280 #if 0 // before bug fix
281  uint32_t tmp;
282 
283  tmp = SCUCG->CLKSRCR & 0x0000ffff; // 0x00000fff°¡ ¿ÇÀ» µí...
284  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
285  tmp |= u32ClkSrc;
286  tmp |= u32HircDiv;
287  SCUCG->CLKSRCR = tmp;
288 #else // after bug fix
289  SCUCG->CLKSRCR = SCUCG->CLKSRCR
290  & ~( SCUCG_CLKSRCR_WTIDKY_Msk | SCUCG_CLKSRCR_HIRCSEL_Msk )
291  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
292  | u32HircDiv
293  | u32ClkSrc
294  ;
295 #endif
296 }
297 
298 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
312 void HAL_SCU_ClockSource_Disable( uint32_t u32ClkSrc )
313 {
314  uint32_t tmp;
315 
316  tmp = SCUCG->CLKSRCR & 0x0000ffff;
317  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
318  tmp &= ~u32ClkSrc;
319  SCUCG->CLKSRCR = tmp;
320 }
321 
322 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
328 {
329  PE->AFSR1 &= 0xffff00ffuL; // PE[3:2]: XOUT/XIN
330  PE->PUPD &= 0xffffff0fuL; // PE[3:2]: Pull-up/down resistors Disable
331  PE->MOD &= 0xffffff0fuL;
332  PE->MOD |= 0x000000a0uL; // PE[3:2]: Alternative Function
333 }
334 
335 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
341 {
342  PE->AFSR1 &= 0xffffff00uL; // PE[1:0]: SXOUT/SXIN
343  PE->PUPD &= 0xfffffff0uL; // PE[1:0]: Pull-up/down resistors Disable
344  PE->MOD &= 0xfffffff0uL;
345  PE->MOD |= 0x0000000auL; // PE[1:0]: Alternative Function
346 }
347 
348 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
356 void HAL_SCU_SystemClockChange( uint32_t u32Target )
357 {
358  SCUCG->SCCR = ( SCUCG_SCCR_WTIDKY_Value << SCUCG_SCCR_WTIDKY_Pos ) // Write ID
359  | u32Target; // Target Clock Source
360 }
361 
362 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
379 void HAL_SCU_SystemClockDivider( uint32_t u32Div02, uint32_t u32Div13 )
380 {
381  // Divider 0 for HCLK: 000/001/010/011/100: MCLK is divided by 16/8/4/2/1
382  // Divider 2 for RTCC and LCD Driver: 000/001/010/011/100: MCLK is divided by 64/128/256/512/1024
383  SCUCG->SCDIVR1 = u32Div02;
384 
385  // Divider 1 for PCLK: 00/01/10/11: HCLK is divided by 1/2/4/8
386  // Divider 3 for SysTick Timer: 00/01/10/11: HCLK is divided by 1/2/4/8
387  SCUCG->SCDIVR2 = u32Div13;
388 }
389 
390 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
401 void HAL_SCU_CLKO_PinConfig( Pn_Type* Px, uint8_t pin_no )
402 {
403  bitsp( Px->MOD, pin_no * 2, 2, 2 ); // PC0 CLKO 0: Input Mode 1: Output Mode 2: Alternative Function Mode
404  if( pin_no < 8 )
405  {
406  bitsp( Px->AFSR1, pin_no * 4, 4, 0 ); // PC0 CLKO 0: CLKO 1: ---- 2: ---- 3: ---- 4: SC0IN 5: ---- 6: ---- 7: COM0
407  }
408  else
409  {
410  pin_no -= 8;
411  bitsp( Px->AFSR2, pin_no * 4, 4, 0 ); // PC1 CLKO 0: CLKO 1: ---- 2: TXD0 3: ---- 4: SC0PWR 5: ---- 6: ---- 7: COM1
412  }
413  bitsp( Px->PUPD, pin_no * 2, 2, 0 ); // PC0 CLKO 0: Push-Pull Output 1: Open-Drain Output
414 }
415 
416 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
433 void HAL_SCU_ClockOutput( uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div )
434 {
435  SCUCG->CLKOCR = 0
436  | ( 1 << SCUCG_CLKOCR_CLKOEN_Pos ) // CLKO Enable
437  | u32Level // 0: Low Level 1: High Level
438  | u32Div // 0: div_1 1: div_2 2: div_4 3: div_8 4: div_16 5: div_32 6: div_64 7: div_128
439  | u32ClkSrc // 0: MCLK 1: WDTRC 2: HIRC 3: HCLK 4: PCLK
440  ;
441 }
442 
443 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
453 void HAL_SCU_Peripheral_ClockConfig( uint32_t u32PeriClk1, uint32_t u32PeriClk2 )
454 {
455  SCUCG->PPCLKEN1 = u32PeriClk1; // Set peripheral clock of timers and ports
456  SCUCG->PPCLKEN2 = u32PeriClk2; // Set peripheral clock of the others
457 }
458 
459 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
471 void HAL_SCU_Peripheral_EnableClock1( uint32_t u32PeriClk1, uint32_t Ind )
472 {
473  if( Ind )
474  {
475  SCUCG->PPCLKEN1 |= u32PeriClk1; // Enable a peripheral clock of timers and ports
476  }
477  else
478  {
479  SCUCG->PPCLKEN1 &= ~u32PeriClk1; // Disable a peripheral clock of timers and ports
480  }
481 }
482 
483 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
499 void HAL_SCU_Peripheral_EnableClock2( uint32_t u32PeriClk2, uint32_t u32Ind )
500 {
501  if( u32Ind )
502  {
503  SCUCG->PPCLKEN2 |= u32PeriClk2; // Enable a peripheral clock of others
504  }
505  else
506  {
507  SCUCG->PPCLKEN2 &= ~u32PeriClk2; // Disable a peripheral clock of others
508  }
509 }
510 
511 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
521 void HAL_SCU_Peripheral_ResetConfig( uint32_t u32PeriRst1, uint32_t u32PeriRst2 )
522 {
523  uint32_t i;
524 
525  SCUCG->PPRST1 = u32PeriRst1; // Reset peripheral block of timers and ports if the corresponding bit is "1b"
526  SCUCG->PPRST2 = u32PeriRst2; // Reset peripheral block of the others
527  for( i = 0 ; i < 10 ; i++ )
528  {
529  NOP();
530  }
531  SCUCG->PPRST1 = 0x0uL; // Clear the peripheral reset bits
532  SCUCG->PPRST2 = 0x0uL;
533 }
534 
535 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
543 void HAL_SCU_Peripheral_SetReset1( uint32_t u32EachPeri1 )
544 {
545  uint32_t i;
546 
547  SCUCG->PPRST1 = u32EachPeri1; // Reset a peripheral block
548  for( i = 0 ; i < 10 ; i++ )
549  {
550  NOP();
551  }
552  SCUCG->PPRST1 = 0; // Clear the peripheral reset bit
553 }
554 
555 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
565 void HAL_SCU_Peripheral_SetReset2( uint32_t u32EachPeri2 )
566 {
567  uint32_t i;
568 
569  SCUCG->PPRST2 = u32EachPeri2; // Reset a peripheral block
570  for( i = 0 ; i < 10 ; i++ )
571  {
572  NOP();
573  }
574  SCUCG->PPRST2 = 0; // Clear the peripheral reset bit
575 }
576 
577 
578 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
592 void HAL_SCU_Peripheral_ClockSelection( uint32_t u32Peri, uint32_t u32ClkSrc )
593 {
594  SCUCG->PPCLKSR &= ~u32Peri;
595  SCUCG->PPCLKSR |= u32ClkSrc;
596 }
597 
void HAL_SCU_CLKO_PinConfig(Pn_Type *Px, uint8_t pin_no)
Set CLKO Pin for Clock Output.
void HAL_SCU_HIRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of HIRC by one step.
void HAL_SCU_SoftwareReset_Config(void)
Check whether system reset ok or not. Generate s/w reset if a weak reset.
void HAL_SCU_SetWakupData(uint32_t u32Data)
Set Wake-Up Timer Data.
uint32_t HAL_SCU_ResetSourceStatus(void)
Get Reset Source Status.
void HAL_SCU_SubXtal_PinConfig(void)
Set XSOSC Pins for x-tal.
void HAL_SCU_ClockOutput(uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
Set Configuration for Clock Output.
void HAL_SCU_SetNMI(uint32_t u32NmiCon)
Set Non-Maskable Interrupt(NMI) Source Selection Register.
void HAL_SCU_Peripheral_ClockSelection(uint32_t u32Peri, uint32_t u32ClkSrc)
Peripheral Clock Selection of PPCLKSR Register.
void HAL_SCU_WDTRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of WDTRC by one step.
void HAL_SCU_ClockSource_Enable(uint32_t u32ClkSrc, uint32_t u32HircDiv)
Enable Clock Source.
void HAL_SCU_ClockMonitoring(uint32_t u32Acts, uint32_t u32Target)
Configure Clock Monitoring.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_ClockSource_Disable(uint32_t u32ClkSrc)
Disable Clock Source.
void HAL_SCU_SystemClockDivider(uint32_t u32Div02, uint32_t u32Div13)
Set System Clock Dividers, SCDIVR1 for RTCC and LCD Driver in case of using MCLK, SCDIVR2 for SysTick...
void HAL_SCU_Peripheral_SetReset1(uint32_t u32EachPeri1)
Set/Reset Each Peripheral Block Reset of PPRST1 Register.
void HAL_SCU_SystemClockChange(uint32_t u32Target)
Change System Clock.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
void HAL_SCU_MainXtal_PinConfig(void)
Set XMOSC Pins for x-tal.
void HAL_SCU_Peripheral_ResetConfig(uint32_t u32PeriRst1, uint32_t u32PeriRst2)
Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".
void HAL_SCU_Peripheral_ClockConfig(uint32_t u32PeriClk1, uint32_t u32PeriClk2)
Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".
void HAL_SCU_ClockSource_Config(uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
Set Clock Source, HIRC Frequency, and type of XMOSC.
Contains all macro definitions and function prototypes support for scu firmware library on A31L12x.
void HAL_SCU_ClockMonitoring_Disable(void)
Disable Clock Monitoring.