A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31L12x_hal_timer4n.c
Go to the documentation of this file.
1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31L12x_hal_scu.h"
41 #include "A31L12x_hal_timer4n.h"
42 
43 /* Public Functions --------------------------------------------------------- */
44 //******************************************************************************
45 // Function
46 //******************************************************************************
47 
48 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
65 HAL_Status_Type HAL_TIMER4n_Init( TIMER4n_Type* TIMER4x, TIMER4n_MODE_OPT TimerCounterMode, void* TIMER4n_Config )
66 {
67  TIMER4n_PERIODICCFG_Type* pTimeCfg;
68  TIMER4n_CAPTURECFG_Type* pCaptureCfg;
69  uint32_t reg_val32;
70 
71  /* Check TIMER4 handle */
72  if( TIMER4x == NULL )
73  {
74  return HAL_ERROR;
75  }
76 
77 #if 1 // supported
78  if( TIMER4x == ( TIMER4n_Type* )TIMER40 )
79  {
80  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T40CLKE, PPxCLKE_Enable );
81  }
82 #endif
83 
84 #if 1 // supported
85  if( TIMER4x == ( TIMER4n_Type* )TIMER41 )
86  {
87  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T41CLKE, PPxCLKE_Enable );
88  }
89 #endif
90 
91 #if 1 // supported
92  if( TIMER4x == ( TIMER4n_Type* )TIMER42 )
93  {
94  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T42CLKE, PPxCLKE_Enable );
95  }
96 #endif
97 
98 #if 1 // supported
99  if( TIMER4x == ( TIMER4n_Type* )TIMER43 )
100  {
101  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T43CLKE, PPxCLKE_Enable );
102  }
103 #endif
104 
105  if( ( TimerCounterMode == TIMER4n_PERIODIC_MODE ) || ( TimerCounterMode == TIMER4n_ONESHOT_MODE ) || ( TimerCounterMode == TIMER4n_BACKTOBACK_MODE ) )
106  {
107  pTimeCfg = ( TIMER4n_PERIODICCFG_Type* )TIMER4n_Config;
108 
109  reg_val32 = 0
110  | TIMER4n_CR_CKSEL_SET( pTimeCfg->CkSel )
111  | TIMER4n_CR_MODE_SET( TimerCounterMode )
112  ;
113  if( pTimeCfg->CkSel == 1 )
114  {
115  reg_val32 = reg_val32 | TIMER4n_CR_ECE_SET( pTimeCfg->ECE );
116  }
117  TIMER4x->CR = reg_val32;
118 
119  reg_val32 = 0
120  | TIMER4n_OUTCR_POLB_SET( pTimeCfg->OutBStartLevel )
121  | TIMER4n_OUTCR_POLA_SET( pTimeCfg->OutAStartLevel )
122  | TIMER4n_OUTCR_BOE_SET( pTimeCfg->OutBEnable )
123  | TIMER4n_OUTCR_AOE_SET( pTimeCfg->OutAEnable )
124  ;
125  TIMER4x->OUTCR = reg_val32;
126 
127  TIMER4x->PREDR = ( pTimeCfg->Prescaler & TIMER4n_PRS_MASK );
128  TIMER4x->ADR = pTimeCfg->ADR;
129  TIMER4x->BDR = pTimeCfg->BDR;
130  TIMER4x->PDR = pTimeCfg->PDR;
131  }
132  else if( TimerCounterMode == TIMER4n_CAPTURE_MODE )
133  {
134  pCaptureCfg = ( TIMER4n_CAPTURECFG_Type* )TIMER4n_Config;
135 
136  reg_val32 = 0
137  | TIMER4n_CR_CKSEL_SET( pCaptureCfg->CkSel )
138  | TIMER4n_CR_MODE_SET( TimerCounterMode )
139  | TIMER4n_CR_INPOL_SET( pCaptureCfg->ClrMode )
140  ;
141  if( pCaptureCfg->CkSel == 1 )
142  {
143  reg_val32 = reg_val32 | TIMER4n_CR_ECE_SET( pCaptureCfg->ECE );
144  }
145  TIMER4x->CR = reg_val32;
146 
147  TIMER4x->PREDR = ( pCaptureCfg->Prescaler & TIMER4n_PRS_MASK );
148  TIMER4x->PDR = pCaptureCfg->PDR;
149  }
150  TIMER4n_ClrCnt( TIMER4x ); // timer counter clear
151 
152  return HAL_OK;
153 }
154 
155 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
162 HAL_Status_Type HAL_TIMER4n_DeInit( TIMER4n_Type* TIMER4x )
163 {
164  /* Check TIMER4 handle */
165  if( TIMER4x == NULL )
166  {
167  return HAL_ERROR;
168  }
169 
170  // Disable timer/counter
171  TIMER4x->CR = 0x00;
172 
173 #if 1 // supported
174  if( TIMER4x == ( TIMER4n_Type* )TIMER40 )
175  {
176  HAL_SCU_Peripheral_SetReset1( 1 << SCUCG_PPRST1_T40RST_Pos );
177  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T40CLKE, PPxCLKE_Disable );
178  }
179 #endif
180 
181 #if 1 // supported
182  if( TIMER4x == ( TIMER4n_Type* )TIMER41 )
183  {
184  HAL_SCU_Peripheral_SetReset1( 1 << SCUCG_PPRST1_T41RST_Pos );
185  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T41CLKE, PPxCLKE_Disable );
186  }
187 #endif
188 
189 #if 1 // supported
190  if( TIMER4x == ( TIMER4n_Type* )TIMER42 )
191  {
192  HAL_SCU_Peripheral_SetReset1( 1 << SCUCG_PPRST1_T42RST_Pos );
193  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T42CLKE, PPxCLKE_Disable );
194  }
195 #endif
196 
197 #if 1 // supported
198  if( TIMER4x == ( TIMER4n_Type* )TIMER43 )
199  {
200  HAL_SCU_Peripheral_SetReset1( 1 << SCUCG_PPRST1_T43RST_Pos );
201  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T43CLKE, PPxCLKE_Disable );
202  }
203 #endif
204 
205  return HAL_OK;
206 }
207 
208 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
222 HAL_Status_Type HAL_TIMER4n_ConfigInterrupt( TIMER4n_Type* TIMER4x, TIMER4n_INT_Type TIMER4n_IntCfg, FunctionalState NewState )
223 {
224  uint16_t tmp;
225 
226  /* Check TIMER4 handle */
227  if( TIMER4x == NULL )
228  {
229  return HAL_ERROR;
230  }
231 
232  switch( TIMER4n_IntCfg )
233  {
234  case TIMER4n_INTCFG_PMIE:
235  tmp = TIMER4n_INT_PMIEN;
236  break;
237  case TIMER4n_INTCFG_CIE:
238  tmp = TIMER4n_INT_CIEN;
239  break;
240  }
241 
242  if( NewState == ENABLE )
243  {
244  TIMER4x->INTCR |= tmp;
245  }
246  else
247  {
248  TIMER4x->INTCR &= ( ~tmp );
249  }
250 
251  return HAL_OK;
252 }
253 
254 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
264 HAL_Status_Type HAL_TIMER4n_Cmd( TIMER4n_Type* TIMER4x, FunctionalState NewState )
265 {
266  /* Check TIMER4 handle */
267  if( TIMER4x == NULL )
268  {
269  return HAL_ERROR;
270  }
271 
272  if( NewState == ENABLE )
273  {
274  TIMER4x->CR |= TIMER4n_ENABLE;
275  }
276  else
277  {
278  TIMER4x->CR &= ~TIMER4n_ENABLE;
279  }
280 
281  return HAL_OK;
282 }
283 
284 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
297 HAL_Status_Type HAL_TIMER4n_SetRegister( TIMER4n_Type* TIMER4x, uint32_t u32T4nSet, uint32_t u32T4nClk )
298 {
299  /* Check TIMER4 handle */
300  if( TIMER4x == NULL )
301  {
302  return HAL_ERROR;
303  }
304 
305  TIMER4x->CR = u32T4nSet; // Setting TIMER4n Control Register
306 
307  TIMER4x->PREDR = u32T4nClk; // Setting TIMER4n Prescaler data
308 
309  return HAL_OK;
310 }
311 
HAL_Status_Type HAL_TIMER4n_Cmd(TIMER4n_Type *TIMER4x, FunctionalState NewState)
Start/Stop Timer/Counter device.
Contains all macro definitions and function prototypes support for timer4n firmware library on A31L12...
HAL_Status_Type
TIMER4n_MODE_OPT
HAL_Status_Type HAL_TIMER4n_ConfigInterrupt(TIMER4n_Type *TIMER4x, TIMER4n_INT_Type TIMER4n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
HAL_Status_Type HAL_TIMER4n_DeInit(TIMER4n_Type *TIMER4x)
Close Timer/Counter device.
HAL_Status_Type HAL_TIMER4n_Init(TIMER4n_Type *TIMER4x, TIMER4n_MODE_OPT TimerCounterMode, void *TIMER4n_Config)
Initialize the TIMER4n peripheral with the specified parameters.
TIMER4n_INT_Type
FunctionalState
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_TIMER4n_SetRegister(TIMER4n_Type *TIMER4x, uint32_t u32T4nSet, uint32_t u32T4nClk)
Set TIMER4n CR/PREDR Registers.
Contains all macro definitions and function prototypes support for scu firmware library on A31L12x.
void HAL_SCU_Peripheral_SetReset1(uint32_t u32EachPeri1)
Set/Reset Each Peripheral Block Reset of PPRST1 Register.