A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31L12x_hal_usart1n.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31L12x_hal_scu.h"
41 #include "A31L12x_hal_usart1n.h"
42 
43 //******************************************************************************
44 // Variable
45 //******************************************************************************
46 
48 
49 /* Public Functions --------------------------------------------------------- */
50 //******************************************************************************
51 // Function
52 //******************************************************************************
53 
54 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
67 static void usart_set_divisors( USART1n_Type* USART1x, uint32_t mode, uint32_t baudrate )
68 {
69  uint32_t numerator;
70  uint32_t denominator;
71  uint32_t n;
72  uint32_t bdr;
73 
74  if( mode == USART1n_UART_MODE )
75  {
76  // baudrate = PCLK / (16 * (bdr + 1))
77  // bdr = (PCLK / (16 * baudrate)) - 1
78  n = 16;
79  }
80  else
81  {
82  // baudrate = PCLK / (2 * (bdr + 1))
83  // bdr = (PCLK / (2 * baudrate)) - 1
84  n = 2;
85  }
86 
87  //--------------------------------------
88  // numerator & denominator
89  //
90  // bdr = USART1n_BaseClock / n / baudrate - 1
91  //--------------------------------------
92  numerator = USART1n_BaseClock;
93  denominator = baudrate;
94 
95  bdr = numerator / n / denominator - 1;
96 
97  USART1x->BDR = ( uint16_t )( bdr & 0xffff );
98 }
99 
100 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
110 HAL_Status_Type HAL_USART_Init( USART1n_Type* USART1x, USART1n_CFG_Type* USART1n_Config )
111 {
112  uint32_t tmp;
113 
114  /* Check USART handle */
115  if( USART1x == NULL )
116  {
117  return HAL_ERROR;
118  }
119 
120 #if 1 // supported
121  if( USART1x == ( USART1n_Type* )USART10 )
122  {
123  // Set up peripheral clock for USART10 module
124  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Enable );
126  }
127 #endif
128 
129 #if 0 // not supported
130  if( USART1x == ( USART1n_Type* )USART11 )
131  {
132  // Set up peripheral clock for USART11 module
133  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Enable );
135  }
136 #endif
137 
138 #if 0 // not supported
139  if( USART1x == ( USART1n_Type* )USART12 )
140  {
141  // Set up peripheral clock for USART12 module
142  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Enable );
144  }
145 #endif
146 
147 #if 0 // not supported
148  if( USART1x == ( USART1n_Type* )USART13 )
149  {
150  // Set up peripheral clock for USART13 module
151  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Enable );
153  }
154 #endif
155 
156  USART1n_BaseClock = SystemPeriClock;
157 
158  usart_set_divisors( USART1x, USART1n_Config->Mode, USART1n_Config->Baudrate );
159 
160  tmp = 0
161  | ( ( USART1n_Config->Mode & 0x3 ) << USART1n_CR1_USTnMS_Pos )
162  | ( ( USART1n_Config->Parity & 0x3 ) << USART1n_CR1_USTnP_Pos )
163  | ( ( USART1n_Config->Databits & 0x7 ) << USART1n_CR1_USTnS_Pos )
164  | ( ( USART1n_Config->Order & 0x1 ) << USART1n_CR1_ORDn_Pos )
165  | ( ( USART1n_Config->ACK & 0x1 ) << USART1n_CR1_CPOLn_Pos )
166  | ( ( USART1n_Config->Edge & 0x3 ) << USART1n_CR1_CPHAn_Pos )
167  | ( 1 << USART1n_CR1_TXEn_Pos ) // Tx Enable
168  | ( 1 << USART1n_CR1_RXEn_Pos ) // Rx Enable
169  ;
170 
171  USART1x->CR1 = tmp;
172 
173  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnSB_Pos ); // USTnSB reset
174  USART1x->CR2 |= ( ( USART1n_Config->Stopbits & 0x1 ) << USART1n_CR2_USTnSB_Pos ); // USTnSB
175  USART1x->CR2 &= ~( 1 << USART1n_CR2_FXCHn_Pos ); // FXCHn reset
176  //USART1x->CR2 |= (1<<USART1n_CR2_FXCHn_Pos); // FXCHn
177 
179 
180  // dummy read
181  HAL_USART_ReceiveByte( USART1x );
182  HAL_USART_ReceiveByte( USART1x );
183 
184  return HAL_OK;
185 }
186 
187 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
195 HAL_Status_Type HAL_USART_DeInit( USART1n_Type* USART1x )
196 {
197  /* Check USART handle */
198  if( USART1x == NULL )
199  {
200  return HAL_ERROR;
201  }
202 
203 #if 1 // supported
204  if( USART1x == ( USART1n_Type* )USART10 )
205  {
206  // Set up peripheral clock for USART10 module
208  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Disable );
209  }
210 #endif
211 
212 #if 0 // not supported
213  if( USART1x == ( USART1n_Type* )USART11 )
214  {
215  // Set up peripheral clock for USART11 module
217  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Disable );
218  }
219 #endif
220 
221 #if 0 // not supported
222  if( USART1x == ( USART1n_Type* )USART12 )
223  {
224  // Set up peripheral clock for USART12 module
226  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Disable );
227  }
228 #endif
229 
230 #if 0 // not supported
231  if( USART1x == ( USART1n_Type* )USART13 )
232  {
233  // Set up peripheral clock for USART13 module
235  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Disable );
236  }
237 #endif
238 
239  return HAL_OK;
240 }
241 
242 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
253 {
254  /* Check USART1n_Config */
255  if( USART1n_Config == NULL )
256  {
257  return HAL_ERROR;
258  }
259 
260  USART1n_Config->Mode = USART1n_UART_MODE;
261  USART1n_Config->Baudrate = 38400;
262  USART1n_Config->Databits = USART1n_DATA_BIT_8;
263  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
264  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
265 
266  return HAL_OK;
267 }
268 
269 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
280 {
281  /* Check USART1n_Config */
282  if( USART1n_Config == NULL )
283  {
284  return HAL_ERROR;
285  }
286 
287  USART1n_Config->Mode = USART1n_USRT_MODE;
288  USART1n_Config->Baudrate = 38400;
289  USART1n_Config->Databits = USART1n_DATA_BIT_8;
290  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
291  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
292 
293  // only SPI & Sync. Mode
294  USART1n_Config->Order = USART1n_SPI_LSB;
295 
296 #if 0 // CPOLn : 0, CPHAn : 0 (X)
297  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
298  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
299 #endif
300 
301 #if 1 // CPOLn : 0, CPHAn : 1 (O)
302  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
303  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
304 #endif
305 
306 #if 0 // CPOLn : 1, CPHAn : 0 (X)
307  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
308  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
309 #endif
310 
311 #if 0 // CPOLn : 1, CPHAn : 1 (O)
312  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
313  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
314 #endif
315 
316  return HAL_OK;
317 }
318 
319 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
330 {
331  /* Check USART1n_Config */
332  if( USART1n_Config == NULL )
333  {
334  return HAL_ERROR;
335  }
336 
337  USART1n_Config->Mode = USART1n_SPI_MODE;
338  USART1n_Config->Baudrate = 38400;
339  USART1n_Config->Databits = USART1n_DATA_BIT_8;
340  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
341  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
342 
343  // only SPI & Sync. Mode
344  USART1n_Config->Order = USART1n_SPI_LSB;
345 
346 #if 1 // CPOLn : 0, CPHAn : 0 (X)
347  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
348  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
349 #endif
350 
351 #if 0 // CPOLn : 0, CPHAn : 1 (O)
352  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
353  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
354 #endif
355 
356 #if 0 // CPOLn : 1, CPHAn : 0 (X)
357  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
358  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
359 #endif
360 
361 #if 0 // CPOLn : 1, CPHAn : 1 (O)
362  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
363  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
364 #endif
365 
366  return HAL_OK;
367 }
368 
369 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
387 HAL_Status_Type HAL_USART_ConfigInterrupt( USART1n_Type* USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState )
388 {
389  uint32_t tmp = 0;
390 
391  /* Check USART handle */
392  if( USART1x == NULL )
393  {
394  return HAL_ERROR;
395  }
396 
397  if( USART1n_IntCfg <= USART1n_INTCFG_DR )
398  {
399  // get mask
400  switch( USART1n_IntCfg )
401  {
402  case USART1n_INTCFG_WAKE:
403  tmp = USART1n_CR1_WAKEIEn_Msk;
404  break;
405  case USART1n_INTCFG_RXC:
406  tmp = USART1n_CR1_RXCIEn_Msk;
407  break;
408  case USART1n_INTCFG_TXC:
409  tmp = USART1n_CR1_TXCIEn_Msk;
410  break;
411  case USART1n_INTCFG_DR:
412  tmp = USART1n_CR1_DRIEn_Msk;
413  break;
414  }
415 
416  // enable/disable
417  if( NewState == ENABLE )
418  {
419  USART1x->CR1 |= tmp;
420  }
421  else
422  {
423  USART1x->CR1 &= ~tmp;
424  }
425  }
426 
427  if( USART1n_IntCfg >= USART1n_INTCFG_RCD )
428  {
429  // get mask
430  switch( USART1n_IntCfg )
431  {
432  case USART1n_INTCFG_RCD:
433  tmp = USART1n_CR3_RCDIEn_Msk;
434  break;
435  case USART1n_INTCFG_RTO:
436  tmp = USART1n_CR3_RTOIEn_Msk;
437  break;
438  }
439 
440  // enable/disable
441  if( NewState == ENABLE )
442  {
443  USART1x->CR3 |= tmp;
444  }
445  else
446  {
447  USART1x->CR3 &= ~tmp;
448  }
449  }
450 
451  return HAL_OK;
452 }
453 
454 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
479 {
480  uint16_t tmp = 0;
481 
482  /* Check USART handle */
483  if( USART1x == NULL )
484  {
485  return HAL_ERROR;
486  }
487 
488  if( Mode <= USART1n_CONTROL_USTEN )
489  {
490  switch( Mode )
491  {
493  tmp = USART1n_CR2_USTnRX8;
494  break;
496  tmp = USART1n_CR2_USTnTX8;
497  break;
499  tmp = USART1n_CR2_USTnSB;
500  break;
502  tmp = USART1n_CR2_FXCHn;
503  break;
505  tmp = USART1n_CR2_USTnSSEN;
506  break;
508  tmp = USART1n_CR2_DISSCKn;
509  break;
511  tmp = USART1n_CR2_LOOPSn;
512  break;
514  tmp = USART1n_CR2_MASTERn;
515  break;
517  tmp = USART1n_CR2_DBLSn;
518  break;
520  tmp = USART1n_CR2_USTnEN;
521  break;
522  }
523 
524  if( NewState == ENABLE )
525  {
526  USART1x->CR2 |= tmp;
527  }
528  else
529  {
530  USART1x->CR2 &= ~( tmp & USART1n_CR2_BITMASK );
531  }
532  }
533 
534  if( Mode >= USART1n_CONTROL_RCDEN )
535  {
536  switch( Mode )
537  {
539  tmp = USART1n_CR3_RCDIEn_Msk;
540  break;
542  tmp = USART1n_CR3_RTOENn_Msk;
543  break;
544  }
545 
546  if( NewState == ENABLE )
547  {
548  USART1x->CR3 |= tmp;
549  }
550  else
551  {
552  USART1x->CR3 &= ~tmp;
553  }
554  }
555 
556  return HAL_OK;
557 }
558 
559 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
568 HAL_Status_Type HAL_USART_Enable( USART1n_Type* USART1x, FunctionalState state )
569 {
570  /* Check USART handle */
571  if( USART1x == NULL )
572  {
573  return HAL_ERROR;
574  }
575 
576  if( state == ENABLE )
577  {
578  USART1x->CR2 |= ( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
579  }
580  else
581  {
582  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
583  }
584 
585  return HAL_OK;
586 }
587 
588 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
597 {
598  uint32_t tmp;
599 
600  /* Check USART handle */
601  if( USART1x == NULL )
602  {
603  return HAL_ERROR;
604  }
605 
606  if( Status <= USART1n_STATUS_DRE )
607  {
608  switch( Status )
609  {
610  case USART1n_STATUS_WAKE:
611  tmp = USART1n_SR_WAKE;
612  break;
613  case USART1n_STATUS_RXC:
614  tmp = USART1n_SR_RXC;
615  break;
616  case USART1n_STATUS_TXC:
617  tmp = USART1n_SR_TXC;
618  break;
619  case USART1n_STATUS_DRE:
620  tmp = USART1n_SR_DRE;
621  break;
622  default:
623  return HAL_ERROR;
624  }
625 
626  USART1x->ST = tmp;
627  }
628 
629  if( Status >= USART1n_STATUS_RCD )
630  {
631  switch( Status )
632  {
633  case USART1n_STATUS_RCD:
634  tmp = USART1n_CR3_RCDnIFLAG_Msk;
635  break;
636  case USART1n_STATUS_RTO:
637  tmp = USART1n_CR3_RTOnIFLAG_Msk;
638  break;
639  default:
640  return HAL_ERROR;
641  }
642 
643  USART1x->CR3 = tmp;
644  }
645 
646  return HAL_OK;
647 }
648 
649 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
656 uint8_t HAL_USART_GetStatus( USART1n_Type* USART1x )
657 {
658  return ( ( USART1x->ST ) & USART1n_SR_BITMASK );
659 }
660 
661 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
668 uint8_t HAL_USART_GetStatusRTORCD( USART1n_Type* USART1x )
669 {
670  return ( USART1x->CR3 & ( USART1n_CR3_RCDnIFLAG_Msk | USART1n_CR3_RTOnIFLAG_Msk ) );
671 }
672 
673 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
680 FlagStatus HAL_USART_CheckBusy( USART1n_Type* USART1x )
681 {
682  if( USART1x->ST & USART1n_SR_DRE )
683  {
684  return RESET;
685  }
686  else
687  {
688  return SET;
689  }
690 }
691 
692 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
701 HAL_Status_Type HAL_USART_TransmitByte( USART1n_Type* USART1x, uint8_t Data )
702 {
703  /* Check USART handle */
704  if( USART1x == NULL )
705  {
706  return HAL_ERROR;
707  }
708 
709  USART1x->TDR = Data;
710 
711  return HAL_OK;
712 }
713 
714 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
721 uint8_t HAL_USART_ReceiveByte( USART1n_Type* USART1x )
722 {
723  return USART1x->RDR;
724 }
725 
726 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
743 uint32_t HAL_USART_Transmit( USART1n_Type* USART1x, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
744 {
745  uint32_t bToSend, bSent, timeOut;
746  uint8_t* pChar = txbuf;
747 
748  // init counter
749  bToSend = buflen;
750  bSent = 0;
751 
752  // Blocking Mode
753  if( flag == BLOCKING )
754  {
755  while( bToSend )
756  {
757  // send byte
758  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
759 
760  // wait until tx data register is empty with timeout
761  timeOut = USART1n_BLOCKING_TIMEOUT;
762  while( !( USART1x->ST & USART1n_SR_TXC ) )
763  {
764  if( timeOut == 0 )
765  {
766  break;
767  }
768  timeOut--;
769  }
770 
771  // if timeout
772  if( timeOut == 0 )
773  {
774  break;
775  }
776 
777  // clear flag
779 
780  // update counter
781  bToSend--;
782  bSent++;
783  }
784  }
785 
786  // Non-Blocking Mode
787  else
788  {
789  while( bToSend )
790  {
791  // if tx data register is not empty
792  if( !( USART1x->ST & USART1n_SR_DRE ) )
793  {
794  break;
795  }
796 
797  // send byte
798  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
799 
800  // update counter
801  bToSend--;
802  bSent++;
803  }
804  }
805 
806  // return
807  return bSent;
808 }
809 
810 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
827 uint32_t HAL_USART_Receive( USART1n_Type* USART1x, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
828 {
829  uint32_t bToRecv, bRecv, timeOut;
830  uint8_t* pChar = rxbuf;
831 
832  // init counter
833  bToRecv = buflen;
834  bRecv = 0;
835 
836  // Blocking Mode
837  if( flag == BLOCKING )
838  {
839  while( bToRecv )
840  {
841  // wait until data are received with timeout
842  timeOut = USART1n_BLOCKING_TIMEOUT;
843  while( !( USART1x->ST & USART1n_SR_RXC ) )
844  {
845  if( timeOut == 0 )
846  {
847  break;
848  }
849  timeOut--;
850  }
851 
852  // if timeout
853  if( timeOut == 0 )
854  {
855  break;
856  }
857 
858  // receive byte
859  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
860 
861  // update counter
862  bToRecv--;
863  bRecv++;
864  }
865  }
866 
867  // Non-Blocking Mode
868  else
869  {
870  while( bToRecv )
871  {
872  // if no data were received
873  if( !( USART1x->ST & USART1n_SR_RXC ) )
874  {
875  break;
876  }
877 
878  // receive byte
879  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
880 
881  // update counter
882  bRecv++;
883  bToRecv--;
884  }
885  }
886 
887  // return
888  return bRecv;
889 }
890 
Contains all macro definitions and function prototypes support for usart1n firmware library on A31L12...
HAL_Status_Type HAL_USART_UART_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
USART1n_EDGE_Type Edge
HAL_Status_Type HAL_USART_ConfigInterrupt(USART1n_Type *USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState)
Configure the interrupt source of selected USART1n peripheral.
FlagStatus HAL_USART_CheckBusy(USART1n_Type *USART1x)
Check whether if USART is busy or not.
USART1n_PARITY_BIT_Type Parity
HAL_Status_Type HAL_USART_DataControlConfig(USART1n_Type *USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState)
Configure Data Control mode for USART peripheral.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
USART1n_SPI_ORDER_Type Order
HAL_Status_Type
USART1n_OPMODE_Type Mode
uint8_t HAL_USART_GetStatusRTORCD(USART1n_Type *USART1x)
Get the RTO/RCD interrupt flag of selected USART1n peripheral.
uint32_t HAL_USART_Transmit(USART1n_Type *USART1x, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Send a block of data via USART peripheral.
HAL_Status_Type HAL_USART_TransmitByte(USART1n_Type *USART1x, uint8_t Data)
Transmit a single data through USART peripheral.
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
uint32_t USART1n_BaseClock
FunctionalState
TRANSFER_BLOCK_Type
HAL_Status_Type HAL_USART_Enable(USART1n_Type *USART1x, FunctionalState state)
USART1n enable control.
HAL_Status_Type HAL_USART_Init(USART1n_Type *USART1x, USART1n_CFG_Type *USART1n_Config)
Initialize the USART1n peripheral with the specified parameters.
uint8_t HAL_USART_GetStatus(USART1n_Type *USART1x)
Get current value of Line Status register in USART peripheral.
USART1n_STOP_BIT_Type Stopbits
USART1n_STATUS_Type
HAL_Status_Type HAL_USART_SPI_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
uint32_t HAL_USART_Receive(USART1n_Type *USART1x, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Receive a block of data via USART peripheral.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
HAL_Status_Type HAL_USART_USRT_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART1n_Config member with its default value:
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.
static void usart_set_divisors(USART1n_Type *USART1x, uint32_t mode, uint32_t baudrate)
Determines best dividers to get a target clock rate.
Contains all macro definitions and function prototypes support for scu firmware library on A31L12x.
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.
USART1n_INT_Type
HAL_Status_Type HAL_USART_DeInit(USART1n_Type *USART1x)
Deinitialize the USART1n peripheral registers to their default reset values.
USART1n_CONTROL_Type