48 #define I2Cn_BLOCKING_TIMEOUT (0x000FFFFFUL) 97 if( I2Cx == ( I2Cn_Type* )I2C0 )
104 if( I2Cx == ( I2Cn_Type* )I2C1 )
110 #if 0 // not supported 111 if( I2Cx == ( I2Cn_Type* )I2C2 )
134 if( ( I2Cx->CR & I2Cn_CR_I2CnIFLAG_Msk ) != 0 )
171 else if( ( tmp ) & 0x20 )
199 if( ( I2Cx->CR & I2Cn_CR_I2CnIFLAG_Msk ) != 0 )
236 else if( tmp & 0x20 )
268 if( I2Cx == ( I2Cn_Type* )I2C0 )
271 SCUCG->PPCLKEN2_b.I2C0CLKE = 1;
277 if( I2Cx == ( I2Cn_Type* )I2C1 )
280 SCUCG->PPCLKEN2_b.I2C1CLKE = 1;
285 #if 0 // not supported 286 if( I2Cx == ( I2Cn_Type* )I2C2 )
289 SCUCG->PPCLKEN2_b.I2C2CLKE = 1;
294 I2Cx->CR_b.I2CnEN = 1;
295 I2Cx->CR_b.I2CnIEN = 1;
297 #if 0 // before bug fix 298 I2Cx->SCLR = ( SystemPeriClock / clockrate - 4 ) / 8;
299 I2Cx->SCHR = ( SystemPeriClock / clockrate - 4 ) / 8;
300 #else // after bug fix 301 I2Cx->SCLR = ( SystemPeriClock / clockrate - 6 ) / 8;
302 I2Cx->SCHR = ( SystemPeriClock / clockrate - 6 ) / 8;
306 I2Cx->CR_b.ACKnEN = 1;
330 if( I2Cx == ( I2Cn_Type* )I2C0 )
333 SCUCG->PPCLKEN2_b.I2C0CLKE = 0;
338 if( I2Cx == ( I2Cn_Type* )I2C1 )
341 SCUCG->PPCLKEN2_b.I2C1CLKE = 0;
345 #if 0 // not supported 346 if( I2Cx == ( I2Cn_Type* )I2C2 )
349 SCUCG->PPCLKEN2_b.I2C2CLKE = 0;
377 if( I2Cx == ( I2Cn_Type* )I2C0 )
379 NVIC_ClearPendingIRQ( I2C0_IRQn );
380 NVIC_EnableIRQ( I2C0_IRQn );
385 if( I2Cx == ( I2Cn_Type* )I2C1 )
387 NVIC_ClearPendingIRQ( I2C1_IRQn );
388 NVIC_EnableIRQ( I2C1_IRQn );
392 #if 0 // not supported 393 if( I2Cx == ( I2Cn_Type* )I2C2 )
395 NVIC_ClearPendingIRQ( I2C2_IRQn );
396 NVIC_EnableIRQ( I2C2_IRQn );
403 if( I2Cx == ( I2Cn_Type* )I2C0 )
405 NVIC_DisableIRQ( I2C0_IRQn );
410 if( I2Cx == ( I2Cn_Type* )I2C1 )
412 NVIC_DisableIRQ( I2C1_IRQn );
416 #if 0 // not supported 417 if( I2Cx == ( I2Cn_Type* )I2C2 )
419 NVIC_DisableIRQ( I2C2_IRQn );
447 I2Cx->SAR1 = ( ( ( uint32_t )( SlaveAddr_7bit << 1 ) ) | ( ( GeneralCallState ==
ENABLE ) ? 0x01 : 0x00 ) ) & I2Cn_SLA_BITMASK;
472 I2Cx->SAR2 = ( ( ( uint32_t )( SlaveAddr_7bit << 1 ) ) | ( ( GeneralCallState ==
ENABLE ) ? 0x01 : 0x00 ) ) & I2Cn_SLA_BITMASK;
487 uint32_t retval, tmp;
506 uint32_t retval, tmp;
567 I2Cx->DR = ( ( txrx_setup->
sl_addr7bit << 1 ) | 0x01 );
570 I2Cx->CR |= ( 1 << 0 );
591 I2Cx->CR_b.ACKnEN = 0;
615 I2Cx->CR_b.ACKnEN = 0;
751 while( I2Cx->ST & 0x04 );
764 I2Cx->CR |= ( 1 << 0 );
766 if( ( Ret != TRANS_MODE ) )
769 I2Cx->CR |= ( 1 << 1 );
792 if( ( Ret != TRANS_DATA ) )
795 I2Cx->CR |= ( 1 << 1 );
812 I2Cx->CR |= ( 1 << 1 );
836 I2Cx->DR = ( ( TransferCfg->
sl_addr7bit << 1 ) | 0x01 );
837 I2Cx->CR |= ( 1 << 0 );
840 if( ( Ret != RECEIVE_MODE ) )
843 I2Cx->CR |= ( 1 << 1 );
864 if( ( Ret != RECEIVE_DATA ) )
867 I2Cx->CR |= ( 1 << 1 );
882 I2Cx->CR &= ~( 1 << 3 );
887 if( ( Ret != RECEIVE_DATA ) )
890 I2Cx->CR |= ( 1 << 1 );
911 I2Cx->CR |= ( 1 << 1 );
946 I2Cx->DR = ( ( TransferCfg->
sl_addr7bit << 1 ) | 0x01 );
948 I2Cx->CR |= ( 1 << 0 );
1140 while( I2Cx->ST & 0x04 );
1156 I2Cx->CR |= ( 1 << 0 );
1158 if( ( Ret != TRANS_MODE ) )
1161 I2Cx->CR |= ( 1 << 1 );
1177 if( TxDMACx->IESR_b.TRCIFGn == 1 )
1180 TxDMACx->IESR = TxDMACx->IESR
1181 & ~DMACn_IESR_TRERIFGn_Msk
1182 | DMACn_IESR_TRCIFGn_Msk
1189 I2Cx->CR |= ( 1 << 1 );
1207 if( TxDMACx->IESR_b.TRERIFGn == 1 )
1210 TxDMACx->IESR = TxDMACx->IESR
1211 & ~DMACn_IESR_TRCIFGn_Msk
1212 | DMACn_IESR_TRERIFGn_Msk
1216 I2Cx->CR |= ( 1 << 1 );
1242 I2Cx->CR &= ~( 1 << 3 );
1249 I2Cx->DR = ( ( TransferCfg->
sl_addr7bit << 1 ) | 0x01 );
1250 I2Cx->CR |= ( 1 << 0 );
1253 if( ( Ret != RECEIVE_MODE ) )
1256 I2Cx->CR |= ( 1 << 1 );
1272 if( RxDMACx->IESR_b.TRCIFGn == 1 )
1275 RxDMACx->IESR = RxDMACx->IESR
1276 & ~DMACn_IESR_TRERIFGn_Msk
1277 | DMACn_IESR_TRCIFGn_Msk
1284 I2Cx->CR &= ~( 1 << 3 );
1293 if( RxDMACx->IESR_b.TRCIFGn == 1 )
1296 RxDMACx->IESR = RxDMACx->IESR
1297 & ~DMACn_IESR_TRERIFGn_Msk
1298 | DMACn_IESR_TRCIFGn_Msk
1306 if( RxDMACx->IESR_b.TRERIFGn == 1 )
1309 RxDMACx->IESR = RxDMACx->IESR
1310 & ~DMACn_IESR_TRCIFGn_Msk
1311 | DMACn_IESR_TRERIFGn_Msk
1315 I2Cx->CR |= ( 1 << 1 );
1334 if( RxDMACx->IESR_b.TRERIFGn == 1 )
1337 RxDMACx->IESR = RxDMACx->IESR
1338 & ~DMACn_IESR_TRCIFGn_Msk
1339 | DMACn_IESR_TRERIFGn_Msk
1343 I2Cx->CR |= ( 1 << 1 );
1357 I2Cx->CR |= ( 1 << 1 );
1412 if( ( Ret == RECEIVE_MODE ) || ( Ret == RECEIVE_DATA ) )
1428 if( ( Ret == TRANS_MODE ) || ( Ret == TRANS_DATA ) )
HAL_Status_Type HAL_I2C_Slave_SetAddress2(I2Cn_Type *I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState)
Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStr...
Status HAL_I2C_MasterTransferData(I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Transmit and Receive data in master mode.
HAL_Status_Type HAL_I2C_Init(I2Cn_Type *I2Cx, uint32_t clockrate)
Initialize the I2Cn peripheral with the specified parameters.
HAL_Status_Type HAL_DMAC_Setup(DMACn_Type *DMACx, uint32_t MAR, uint16_t TRANSCNT)
Enable the transfer.
Status HAL_I2C_MasterTransmit_DMA(I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt, DMACn_Type *TxDMACx, DMACn_Type *RxDMACx)
Transmit an array of bytes in Master mode by DMA.
int32_t I2Cn_SWait(I2Cn_Type *I2Cx)
wait and return status in slave mode
Status HAL_I2C_Master_Transmit(I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Transmit an array of bytes in Master mode.
Status HAL_I2C_MasterTransferData_DMA(I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt, DMACn_Type *TxDMACx, DMACn_Type *RxDMACx)
Transmit and Receive data in master mode by DMA.
static Bool I2Cn_SlaveComplete[I2Cn_MAX]
int32_t I2Cn_getNum(I2Cn_Type *I2Cx)
Convert from I2C peripheral to number.
Status HAL_I2C_SlaveTransferData(I2Cn_Type *I2Cx, I2Cn_S_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Receive and Transmit data in slave mode.
static I2Cn_CFG_Type i2cdat[I2Cn_MAX]
I2Cn driver data.
I2Cn_M_SETUP_Type txrx_setup_master
Status HAL_I2C_SlaveReceive_DMA(I2Cn_Type *I2Cx, I2Cn_S_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt, DMACn_Type *TxDMACx, DMACn_Type *RxDMACx)
Receive an array of bytes in Slave mode by DMA.
static Bool I2Cn_MasterComplete[I2Cn_MAX]
Contains all macro definitions and function prototypes support for i2cn firmware library on A31L12x.
I2Cn_S_SETUP_Type txrx_setup_slave
Contains all macro definitions and function prototypes support for dmacn firmware library on A31L12x.
Status HAL_I2C_SlaveTransferData_DMA(I2Cn_Type *I2Cx, I2Cn_S_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt, DMACn_Type *TxDMACx, DMACn_Type *RxDMACx)
Receive and Transmit data in slave mode by DMA.
uint32_t HAL_I2C_Slave_GetState(I2Cn_Type *I2Cx)
Get Status of Slave Transfer.
HAL_Status_Type HAL_I2C_Slave_IRQHandler_IT(I2Cn_Type *I2Cx)
General Slave Interrupt handler for I2C peripheral.
Status HAL_I2C_Master_Receive(I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Receive an array of bytes in Master mode.
HAL_Status_Type HAL_I2C_ConfigInterrupt(I2Cn_Type *I2Cx, Bool NewState)
Enable/Disable interrupt for I2C peripheral.
Status HAL_I2C_Slave_Receive(I2Cn_Type *I2Cx, I2Cn_S_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Receive an array of bytes in Slave mode.
HAL_Status_Type HAL_I2C_Master_IRQHandler_IT(I2Cn_Type *I2Cx)
General Master Interrupt handler for I2C peripheral.
int32_t I2Cn_MWait(I2Cn_Type *I2Cx)
wait and return status in master mode
HAL_Status_Type HAL_I2C_Slave_SetAddress1(I2Cn_Type *I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState)
Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStr...
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
uint32_t HAL_I2C_Master_GetState(I2Cn_Type *I2Cx)
Get Status of Master Transfer.
HAL_Status_Type HAL_I2C_DeInit(I2Cn_Type *I2Cx)
Deinitialize the I2Cn peripheral registers to their default reset values.
Contains all macro definitions and function prototypes support for scu firmware library on A31L12x.