A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
Data Structures | Enumerations | Functions
A31L12x_hal_usart1n.h File Reference

Contains all macro definitions and function prototypes support for usart1n firmware library on A31L12x. More...

Go to the source code of this file.

Data Structures

struct  USART1n_CFG_Type
 

Enumerations

enum  USART1n_OPMODE_Type { USART1n_UART_MODE = 0, USART1n_USRT_MODE, USART1n_SPI_MODE = 3 }
 
enum  USART1n_SPI_ORDER_Type { USART1n_SPI_LSB = 0, USART1n_SPI_MSB }
 
enum  USART1n_ACK_Type { USART1n_SPI_TX_RISING = 0, USART1n_SPI_TX_FALLING }
 
enum  USART1n_EDGE_Type { USART1n_SPI_TX_LEADEDGE_SAMPLE = 0, USART1n_SPI_TX_LEADEDGE_SETUP }
 
enum  USART1n_DATA_BIT_Type {
  USART1n_DATA_BIT_5 = 0, USART1n_DATA_BIT_6, USART1n_DATA_BIT_7, USART1n_DATA_BIT_8,
  USART1n_DATA_BIT_9 = 7
}
 
enum  USART1n_STOP_BIT_Type { USART1n_STOP_BIT_1 = 0, USART1n_STOP_BIT_2 }
 
enum  USART1n_PARITY_BIT_Type { USART1n_PARITY_BIT_NONE = 0, USART1n_PARITY_BIT_EVEN = 2, USART1n_PARITY_BIT_ODD = 3 }
 
enum  USART1n_CONTROL_Type {
  USART1n_CONTROL_USTRX8 = 0, USART1n_CONTROL_USTTX8, USART1n_CONTROL_USTSB, USART1n_CONTROL_FXCH,
  USART1n_CONTROL_USTSSEN, USART1n_CONTROL_DISSCK, USART1n_CONTROL_LOOPS, USART1n_CONTROL_MASTER,
  USART1n_CONTROL_DBLS, USART1n_CONTROL_USTEN, USART1n_CONTROL_RCDEN, USART1n_CONTROL_RTOEN
}
 
enum  USART1n_STATUS_Type {
  USART1n_STATUS_PE = 0, USART1n_STATUS_FE, USART1n_STATUS_DOR, USART1n_STATUS_WAKE,
  USART1n_STATUS_RXC, USART1n_STATUS_TXC, USART1n_STATUS_DRE, USART1n_STATUS_RCD,
  USART1n_STATUS_RTO
}
 
enum  USART1n_INT_Type {
  USART1n_INTCFG_WAKE = 0, USART1n_INTCFG_RXC, USART1n_INTCFG_TXC, USART1n_INTCFG_DR,
  USART1n_INTCFG_RCD, USART1n_INTCFG_RTO
}
 

Functions

HAL_Status_Type HAL_USART_Init (USART1n_Type *USART1x, USART1n_CFG_Type *USART1n_Config)
 Initialize the USART1n peripheral with the specified parameters. More...
 
HAL_Status_Type HAL_USART_DeInit (USART1n_Type *USART1x)
 Deinitialize the USART1n peripheral registers to their default reset values. More...
 
HAL_Status_Type HAL_USART_UART_Mode_Config (USART1n_CFG_Type *USART1n_Config)
 Fills each USART1n_Config member with its default value: More...
 
HAL_Status_Type HAL_USART_USRT_Mode_Config (USART1n_CFG_Type *USART1n_Config)
 Fills each USART1n_Config member with its default value: More...
 
HAL_Status_Type HAL_USART_SPI_Mode_Config (USART1n_CFG_Type *USART1n_Config)
 Fills each USART1n_Config member with its default value: More...
 
HAL_Status_Type HAL_USART_ConfigInterrupt (USART1n_Type *USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState)
 Configure the interrupt source of selected USART1n peripheral. More...
 
HAL_Status_Type HAL_USART_DataControlConfig (USART1n_Type *USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState)
 Configure Data Control mode for USART peripheral. More...
 
HAL_Status_Type HAL_USART_Enable (USART1n_Type *USART1x, FunctionalState state)
 USART1n enable control. More...
 
HAL_Status_Type HAL_USART_ClearStatus (USART1n_Type *USART1x, USART1n_STATUS_Type Status)
 Clear Status register in USART peripheral. More...
 
uint8_t HAL_USART_GetStatus (USART1n_Type *USART1x)
 Get current value of Line Status register in USART peripheral. More...
 
uint8_t HAL_USART_GetStatusRTORCD (USART1n_Type *USART1x)
 Get the RTO/RCD interrupt flag of selected USART1n peripheral. More...
 
FlagStatus HAL_USART_CheckBusy (USART1n_Type *USART1x)
 Check whether if USART is busy or not. More...
 
HAL_Status_Type HAL_USART_TransmitByte (USART1n_Type *USART1x, uint8_t Data)
 Transmit a single data through USART peripheral. More...
 
uint8_t HAL_USART_ReceiveByte (USART1n_Type *USART1x)
 Receive a single data from USART peripheral. More...
 
uint32_t HAL_USART_Transmit (USART1n_Type *USART1x, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
 Send a block of data via USART peripheral. More...
 
uint32_t HAL_USART_Receive (USART1n_Type *USART1x, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
 Receive a block of data via USART peripheral. More...
 

Detailed Description

Contains all macro definitions and function prototypes support for usart1n firmware library on A31L12x.

Version
1.00
Date
2020-05-29
Author
ABOV Application Team

Copyright(C) 2019, ABOV Semiconductor All rights reserved.

ABOV Disclaimer

IMPORTANT NOTICE ? PLEASE READ CAREFULLY ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders. Purchasers are entirely responsible for the choice, selection, and use of ABOV products and ABOV assumes no liability for application assistance or the design of purchasers' products. No license, express or implied, to any intellectual property rights is granted by ABOV herein. ABOV disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications. ABOV and the ABOV logo are trademarks of ABOV. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces the information previously supplied in any former versions of this document. 2020 ABOV Semiconductor All rights reserved

Definition in file A31L12x_hal_usart1n.h.

Enumeration Type Documentation

◆ USART1n_ACK_Type

Enumerator
USART1n_SPI_TX_RISING 

Txd Change : Rising / Rxd Change : Falling

USART1n_SPI_TX_FALLING 

Txd Change : Falling / Rxd Change : Rising

Definition at line 111 of file A31L12x_hal_usart1n.h.

◆ USART1n_CONTROL_Type

USART Data Control type definition

Enumerator
USART1n_CONTROL_USTRX8 
USART1n_CONTROL_USTTX8 
USART1n_CONTROL_USTSB 
USART1n_CONTROL_FXCH 
USART1n_CONTROL_USTSSEN 
USART1n_CONTROL_DISSCK 
USART1n_CONTROL_LOOPS 
USART1n_CONTROL_MASTER 
USART1n_CONTROL_DBLS 
USART1n_CONTROL_USTEN 
USART1n_CONTROL_RCDEN 
USART1n_CONTROL_RTOEN 

Definition at line 149 of file A31L12x_hal_usart1n.h.

◆ USART1n_DATA_BIT_Type

USART1n Data Bit type definitions

Enumerator
USART1n_DATA_BIT_5 

5 Data Bits

USART1n_DATA_BIT_6 

6 Data Bits

USART1n_DATA_BIT_7 

7 Data Bits

USART1n_DATA_BIT_8 

8 Data Bits

USART1n_DATA_BIT_9 

9 Data Bits

Definition at line 124 of file A31L12x_hal_usart1n.h.

◆ USART1n_EDGE_Type

Enumerator
USART1n_SPI_TX_LEADEDGE_SAMPLE 

Leading edge : Sample / Trailing edge : Setup

USART1n_SPI_TX_LEADEDGE_SETUP 

Leading edge : Setup / Trailing edge : Sample

Definition at line 117 of file A31L12x_hal_usart1n.h.

◆ USART1n_INT_Type

Enumerator
USART1n_INTCFG_WAKE 
USART1n_INTCFG_RXC 
USART1n_INTCFG_TXC 
USART1n_INTCFG_DR 
USART1n_INTCFG_RCD 
USART1n_INTCFG_RTO 

Definition at line 180 of file A31L12x_hal_usart1n.h.

◆ USART1n_OPMODE_Type

Enumerator
USART1n_UART_MODE 

UART Mode

USART1n_USRT_MODE 

USRT Mode (Syncronous)

USART1n_SPI_MODE 

SPI Mode

Definition at line 98 of file A31L12x_hal_usart1n.h.

◆ USART1n_PARITY_BIT_Type

USART1n Parity Bit type definitions

Enumerator
USART1n_PARITY_BIT_NONE 

No parity

USART1n_PARITY_BIT_EVEN 

Even parity

USART1n_PARITY_BIT_ODD 

Odd parity

Definition at line 141 of file A31L12x_hal_usart1n.h.

◆ USART1n_SPI_ORDER_Type

Enumerator
USART1n_SPI_LSB 

SPI LSB First

USART1n_SPI_MSB 

SPI MSB First

Definition at line 105 of file A31L12x_hal_usart1n.h.

◆ USART1n_STATUS_Type

Enumerator
USART1n_STATUS_PE 
USART1n_STATUS_FE 
USART1n_STATUS_DOR 
USART1n_STATUS_WAKE 
USART1n_STATUS_RXC 
USART1n_STATUS_TXC 
USART1n_STATUS_DRE 
USART1n_STATUS_RCD 
USART1n_STATUS_RTO 

Definition at line 166 of file A31L12x_hal_usart1n.h.

◆ USART1n_STOP_BIT_Type

USART1n Stop Bit type definitions

Enumerator
USART1n_STOP_BIT_1 

1 Stop Bits

USART1n_STOP_BIT_2 

2 Stop Bits

Definition at line 134 of file A31L12x_hal_usart1n.h.

Function Documentation

◆ HAL_USART_CheckBusy()

FlagStatus HAL_USART_CheckBusy ( USART1n_Type *  USART1x)

Check whether if USART is busy or not.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
Returns
RESET if USART is not busy, otherwise return SET.

Definition at line 680 of file A31L12x_hal_usart1n.c.

681 {
682  if( USART1x->ST & USART1n_SR_DRE )
683  {
684  return RESET;
685  }
686  else
687  {
688  return SET;
689  }
690 }

References RESET, and SET.

◆ HAL_USART_ClearStatus()

HAL_Status_Type HAL_USART_ClearStatus ( USART1n_Type *  USART1x,
USART1n_STATUS_Type  Status 
)

Clear Status register in USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[in]Status
Returns
HAL_Status_Type

Definition at line 596 of file A31L12x_hal_usart1n.c.

597 {
598  uint32_t tmp;
599 
600  /* Check USART handle */
601  if( USART1x == NULL )
602  {
603  return HAL_ERROR;
604  }
605 
606  if( Status <= USART1n_STATUS_DRE )
607  {
608  switch( Status )
609  {
610  case USART1n_STATUS_WAKE:
611  tmp = USART1n_SR_WAKE;
612  break;
613  case USART1n_STATUS_RXC:
614  tmp = USART1n_SR_RXC;
615  break;
616  case USART1n_STATUS_TXC:
617  tmp = USART1n_SR_TXC;
618  break;
619  case USART1n_STATUS_DRE:
620  tmp = USART1n_SR_DRE;
621  break;
622  default:
623  return HAL_ERROR;
624  }
625 
626  USART1x->ST = tmp;
627  }
628 
629  if( Status >= USART1n_STATUS_RCD )
630  {
631  switch( Status )
632  {
633  case USART1n_STATUS_RCD:
634  tmp = USART1n_CR3_RCDnIFLAG_Msk;
635  break;
636  case USART1n_STATUS_RTO:
637  tmp = USART1n_CR3_RTOnIFLAG_Msk;
638  break;
639  default:
640  return HAL_ERROR;
641  }
642 
643  USART1x->CR3 = tmp;
644  }
645 
646  return HAL_OK;
647 }

References HAL_ERROR, HAL_OK, USART1n_STATUS_DRE, USART1n_STATUS_RCD, USART1n_STATUS_RTO, USART1n_STATUS_RXC, USART1n_STATUS_TXC, and USART1n_STATUS_WAKE.

Referenced by HAL_USART_Init(), and HAL_USART_Transmit().

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◆ HAL_USART_ConfigInterrupt()

HAL_Status_Type HAL_USART_ConfigInterrupt ( USART1n_Type *  USART1x,
USART1n_INT_Type  USART1n_IntCfg,
FunctionalState  NewState 
)

Configure the interrupt source of selected USART1n peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[in]USART1n_IntCfgSpecifies the interrupt source
  • USART1n_INTCFG_WAKE
  • USART1n_INTCFG_RXC
  • USART1n_INTCFG_TXC
  • USART1n_INTCFG_DR
  • USART1n_INTCFG_RCD
  • USART1n_INTCFG_RTO
[in]NewStateNext State of Interrupt Operation
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 387 of file A31L12x_hal_usart1n.c.

388 {
389  uint32_t tmp = 0;
390 
391  /* Check USART handle */
392  if( USART1x == NULL )
393  {
394  return HAL_ERROR;
395  }
396 
397  if( USART1n_IntCfg <= USART1n_INTCFG_DR )
398  {
399  // get mask
400  switch( USART1n_IntCfg )
401  {
402  case USART1n_INTCFG_WAKE:
403  tmp = USART1n_CR1_WAKEIEn_Msk;
404  break;
405  case USART1n_INTCFG_RXC:
406  tmp = USART1n_CR1_RXCIEn_Msk;
407  break;
408  case USART1n_INTCFG_TXC:
409  tmp = USART1n_CR1_TXCIEn_Msk;
410  break;
411  case USART1n_INTCFG_DR:
412  tmp = USART1n_CR1_DRIEn_Msk;
413  break;
414  }
415 
416  // enable/disable
417  if( NewState == ENABLE )
418  {
419  USART1x->CR1 |= tmp;
420  }
421  else
422  {
423  USART1x->CR1 &= ~tmp;
424  }
425  }
426 
427  if( USART1n_IntCfg >= USART1n_INTCFG_RCD )
428  {
429  // get mask
430  switch( USART1n_IntCfg )
431  {
432  case USART1n_INTCFG_RCD:
433  tmp = USART1n_CR3_RCDIEn_Msk;
434  break;
435  case USART1n_INTCFG_RTO:
436  tmp = USART1n_CR3_RTOIEn_Msk;
437  break;
438  }
439 
440  // enable/disable
441  if( NewState == ENABLE )
442  {
443  USART1x->CR3 |= tmp;
444  }
445  else
446  {
447  USART1x->CR3 &= ~tmp;
448  }
449  }
450 
451  return HAL_OK;
452 }

References ENABLE, HAL_ERROR, HAL_OK, USART1n_INTCFG_DR, USART1n_INTCFG_RCD, USART1n_INTCFG_RTO, USART1n_INTCFG_RXC, USART1n_INTCFG_TXC, and USART1n_INTCFG_WAKE.

◆ HAL_USART_DataControlConfig()

HAL_Status_Type HAL_USART_DataControlConfig ( USART1n_Type *  USART1x,
USART1n_CONTROL_Type  Mode,
FunctionalState  NewState 
)

Configure Data Control mode for USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[in]ModeData Control Mode
  • USART1n_CONTROL_USTEN: Activate USARTn Block by supplying.
  • USART1n_CONTROL_DBLS: Selects receiver sampling rate. (only UART mode)
  • USART1n_CONTROL_MASTER: Selects master or slave in SPIn or Synchronous mode and controls the direction of SCKn pin.
  • USART1n_CONTROL_LOOPS: Control the Loop Back mode of USARTn for test mode.
  • USART1n_CONTROL_DISSCK: In synchronous mode operation, selects the waveform of SCKn output.
  • USART1n_CONTROL_USTSSEN: This bit controls the SSn pin operation. (only SPI mode)
  • USART1n_CONTROL_FXCH: SPIn port function exchange control bit. (only SPI mode)
  • USART1n_CONTROL_USTSB: Selects the length of stop bit in Asynchronous or Synchronous mode.
  • USART1n_CONTROL_USTTX8: The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USARTn_DR register.
  • USART1n_CONTROL_USTRX8: The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)
  • USART1n_CONTROL_RCDEN: Receive Character Detection Function Enable
  • USART1n_CONTROL_RTOEN: Receive Time Out Function Enable
[in]NewStateNext State of Functional Operation
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 478 of file A31L12x_hal_usart1n.c.

479 {
480  uint16_t tmp = 0;
481 
482  /* Check USART handle */
483  if( USART1x == NULL )
484  {
485  return HAL_ERROR;
486  }
487 
488  if( Mode <= USART1n_CONTROL_USTEN )
489  {
490  switch( Mode )
491  {
493  tmp = USART1n_CR2_USTnRX8;
494  break;
496  tmp = USART1n_CR2_USTnTX8;
497  break;
499  tmp = USART1n_CR2_USTnSB;
500  break;
502  tmp = USART1n_CR2_FXCHn;
503  break;
505  tmp = USART1n_CR2_USTnSSEN;
506  break;
508  tmp = USART1n_CR2_DISSCKn;
509  break;
511  tmp = USART1n_CR2_LOOPSn;
512  break;
514  tmp = USART1n_CR2_MASTERn;
515  break;
517  tmp = USART1n_CR2_DBLSn;
518  break;
520  tmp = USART1n_CR2_USTnEN;
521  break;
522  }
523 
524  if( NewState == ENABLE )
525  {
526  USART1x->CR2 |= tmp;
527  }
528  else
529  {
530  USART1x->CR2 &= ~( tmp & USART1n_CR2_BITMASK );
531  }
532  }
533 
534  if( Mode >= USART1n_CONTROL_RCDEN )
535  {
536  switch( Mode )
537  {
539  tmp = USART1n_CR3_RCDIEn_Msk;
540  break;
542  tmp = USART1n_CR3_RTOENn_Msk;
543  break;
544  }
545 
546  if( NewState == ENABLE )
547  {
548  USART1x->CR3 |= tmp;
549  }
550  else
551  {
552  USART1x->CR3 &= ~tmp;
553  }
554  }
555 
556  return HAL_OK;
557 }

References ENABLE, HAL_ERROR, HAL_OK, USART1n_CONTROL_DBLS, USART1n_CONTROL_DISSCK, USART1n_CONTROL_FXCH, USART1n_CONTROL_LOOPS, USART1n_CONTROL_MASTER, USART1n_CONTROL_RCDEN, USART1n_CONTROL_RTOEN, USART1n_CONTROL_USTEN, USART1n_CONTROL_USTRX8, USART1n_CONTROL_USTSB, USART1n_CONTROL_USTSSEN, and USART1n_CONTROL_USTTX8.

◆ HAL_USART_DeInit()

HAL_Status_Type HAL_USART_DeInit ( USART1n_Type *  USART1x)

Deinitialize the USART1n peripheral registers to their default reset values.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
Returns
HAL_Status_Type

Definition at line 195 of file A31L12x_hal_usart1n.c.

196 {
197  /* Check USART handle */
198  if( USART1x == NULL )
199  {
200  return HAL_ERROR;
201  }
202 
203 #if 1 // supported
204  if( USART1x == ( USART1n_Type* )USART10 )
205  {
206  // Set up peripheral clock for USART10 module
208  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Disable );
209  }
210 #endif
211 
212 #if 0 // not supported
213  if( USART1x == ( USART1n_Type* )USART11 )
214  {
215  // Set up peripheral clock for USART11 module
217  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Disable );
218  }
219 #endif
220 
221 #if 0 // not supported
222  if( USART1x == ( USART1n_Type* )USART12 )
223  {
224  // Set up peripheral clock for USART12 module
226  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Disable );
227  }
228 #endif
229 
230 #if 0 // not supported
231  if( USART1x == ( USART1n_Type* )USART13 )
232  {
233  // Set up peripheral clock for USART13 module
235  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Disable );
236  }
237 #endif
238 
239  return HAL_OK;
240 }
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.

References HAL_ERROR, HAL_OK, HAL_SCU_Peripheral_EnableClock2(), and HAL_SCU_Peripheral_SetReset2().

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◆ HAL_USART_Enable()

HAL_Status_Type HAL_USART_Enable ( USART1n_Type *  USART1x,
FunctionalState  state 
)

USART1n enable control.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[in]state
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 568 of file A31L12x_hal_usart1n.c.

569 {
570  /* Check USART handle */
571  if( USART1x == NULL )
572  {
573  return HAL_ERROR;
574  }
575 
576  if( state == ENABLE )
577  {
578  USART1x->CR2 |= ( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
579  }
580  else
581  {
582  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
583  }
584 
585  return HAL_OK;
586 }

References ENABLE, HAL_ERROR, and HAL_OK.

◆ HAL_USART_GetStatus()

uint8_t HAL_USART_GetStatus ( USART1n_Type *  USART1x)

Get current value of Line Status register in USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
Returns
Current value of Status register in USART peripheral.

Definition at line 656 of file A31L12x_hal_usart1n.c.

657 {
658  return ( ( USART1x->ST ) & USART1n_SR_BITMASK );
659 }

◆ HAL_USART_GetStatusRTORCD()

uint8_t HAL_USART_GetStatusRTORCD ( USART1n_Type *  USART1x)

Get the RTO/RCD interrupt flag of selected USART1n peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
Returns
Current RTO/RCD interrupt flag

Definition at line 668 of file A31L12x_hal_usart1n.c.

669 {
670  return ( USART1x->CR3 & ( USART1n_CR3_RCDnIFLAG_Msk | USART1n_CR3_RTOnIFLAG_Msk ) );
671 }

◆ HAL_USART_Init()

HAL_Status_Type HAL_USART_Init ( USART1n_Type *  USART1x,
USART1n_CFG_Type USART1n_Config 
)

Initialize the USART1n peripheral with the specified parameters.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[in]USART1n_ConfigPointer to a USART1n_CFG_Type structure that contains the configuration information for the specified peripheral.
Returns
HAL_Status_Type

Definition at line 110 of file A31L12x_hal_usart1n.c.

111 {
112  uint32_t tmp;
113 
114  /* Check USART handle */
115  if( USART1x == NULL )
116  {
117  return HAL_ERROR;
118  }
119 
120 #if 1 // supported
121  if( USART1x == ( USART1n_Type* )USART10 )
122  {
123  // Set up peripheral clock for USART10 module
124  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Enable );
126  }
127 #endif
128 
129 #if 0 // not supported
130  if( USART1x == ( USART1n_Type* )USART11 )
131  {
132  // Set up peripheral clock for USART11 module
133  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Enable );
135  }
136 #endif
137 
138 #if 0 // not supported
139  if( USART1x == ( USART1n_Type* )USART12 )
140  {
141  // Set up peripheral clock for USART12 module
142  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Enable );
144  }
145 #endif
146 
147 #if 0 // not supported
148  if( USART1x == ( USART1n_Type* )USART13 )
149  {
150  // Set up peripheral clock for USART13 module
151  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Enable );
153  }
154 #endif
155 
156  USART1n_BaseClock = SystemPeriClock;
157 
158  usart_set_divisors( USART1x, USART1n_Config->Mode, USART1n_Config->Baudrate );
159 
160  tmp = 0
161  | ( ( USART1n_Config->Mode & 0x3 ) << USART1n_CR1_USTnMS_Pos )
162  | ( ( USART1n_Config->Parity & 0x3 ) << USART1n_CR1_USTnP_Pos )
163  | ( ( USART1n_Config->Databits & 0x7 ) << USART1n_CR1_USTnS_Pos )
164  | ( ( USART1n_Config->Order & 0x1 ) << USART1n_CR1_ORDn_Pos )
165  | ( ( USART1n_Config->ACK & 0x1 ) << USART1n_CR1_CPOLn_Pos )
166  | ( ( USART1n_Config->Edge & 0x3 ) << USART1n_CR1_CPHAn_Pos )
167  | ( 1 << USART1n_CR1_TXEn_Pos ) // Tx Enable
168  | ( 1 << USART1n_CR1_RXEn_Pos ) // Rx Enable
169  ;
170 
171  USART1x->CR1 = tmp;
172 
173  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnSB_Pos ); // USTnSB reset
174  USART1x->CR2 |= ( ( USART1n_Config->Stopbits & 0x1 ) << USART1n_CR2_USTnSB_Pos ); // USTnSB
175  USART1x->CR2 &= ~( 1 << USART1n_CR2_FXCHn_Pos ); // FXCHn reset
176  //USART1x->CR2 |= (1<<USART1n_CR2_FXCHn_Pos); // FXCHn
177 
179 
180  // dummy read
181  HAL_USART_ReceiveByte( USART1x );
182  HAL_USART_ReceiveByte( USART1x );
183 
184  return HAL_OK;
185 }
USART1n_EDGE_Type Edge
USART1n_PARITY_BIT_Type Parity
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
USART1n_SPI_ORDER_Type Order
USART1n_OPMODE_Type Mode
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
uint32_t USART1n_BaseClock
USART1n_STOP_BIT_Type Stopbits
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.
static void usart_set_divisors(USART1n_Type *USART1x, uint32_t mode, uint32_t baudrate)
Determines best dividers to get a target clock rate.
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.

References USART1n_CFG_Type::ACK, USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, USART1n_CFG_Type::Edge, HAL_ERROR, HAL_OK, HAL_SCU_Peripheral_EnableClock2(), HAL_SCU_Peripheral_SetReset2(), HAL_USART_ClearStatus(), HAL_USART_ReceiveByte(), USART1n_CFG_Type::Mode, USART1n_CFG_Type::Order, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_BaseClock, USART1n_STATUS_TXC, and usart_set_divisors().

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◆ HAL_USART_Receive()

uint32_t HAL_USART_Receive ( USART1n_Type *  USART1x,
uint8_t *  rxbuf,
uint32_t  buflen,
TRANSFER_BLOCK_Type  flag 
)

Receive a block of data via USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[out]rxbufPointer to Received buffer
[in]buflenLength of Received buffer
[in]flagFlag mode
  • NONE_BLOCKING
  • BLOCKING
Returns
Number of bytes received
Note
when using USART in BLOCKING mode, a time-out condition is used via defined symbol USART_BLOCKING_TIMEOUT.

Definition at line 827 of file A31L12x_hal_usart1n.c.

828 {
829  uint32_t bToRecv, bRecv, timeOut;
830  uint8_t* pChar = rxbuf;
831 
832  // init counter
833  bToRecv = buflen;
834  bRecv = 0;
835 
836  // Blocking Mode
837  if( flag == BLOCKING )
838  {
839  while( bToRecv )
840  {
841  // wait until data are received with timeout
842  timeOut = USART1n_BLOCKING_TIMEOUT;
843  while( !( USART1x->ST & USART1n_SR_RXC ) )
844  {
845  if( timeOut == 0 )
846  {
847  break;
848  }
849  timeOut--;
850  }
851 
852  // if timeout
853  if( timeOut == 0 )
854  {
855  break;
856  }
857 
858  // receive byte
859  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
860 
861  // update counter
862  bToRecv--;
863  bRecv++;
864  }
865  }
866 
867  // Non-Blocking Mode
868  else
869  {
870  while( bToRecv )
871  {
872  // if no data were received
873  if( !( USART1x->ST & USART1n_SR_RXC ) )
874  {
875  break;
876  }
877 
878  // receive byte
879  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
880 
881  // update counter
882  bRecv++;
883  bToRecv--;
884  }
885  }
886 
887  // return
888  return bRecv;
889 }
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.

References BLOCKING, and HAL_USART_ReceiveByte().

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◆ HAL_USART_ReceiveByte()

uint8_t HAL_USART_ReceiveByte ( USART1n_Type *  USART1x)

Receive a single data from USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
Returns
Data received

Definition at line 721 of file A31L12x_hal_usart1n.c.

722 {
723  return USART1x->RDR;
724 }

Referenced by HAL_USART_Init(), and HAL_USART_Receive().

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◆ HAL_USART_SPI_Mode_Config()

HAL_Status_Type HAL_USART_SPI_Mode_Config ( USART1n_CFG_Type USART1n_Config)

Fills each USART1n_Config member with its default value:

  • 38400 bps
  • 8 Data Bit
  • No Parity Bit
  • 1 Stop Bit
    Parameters
    [out]USART1n_ConfigPointer to a USART1n_CFG_Type structure which will be initialized.
    Returns
    HAL_Status_Type

Definition at line 329 of file A31L12x_hal_usart1n.c.

330 {
331  /* Check USART1n_Config */
332  if( USART1n_Config == NULL )
333  {
334  return HAL_ERROR;
335  }
336 
337  USART1n_Config->Mode = USART1n_SPI_MODE;
338  USART1n_Config->Baudrate = 38400;
339  USART1n_Config->Databits = USART1n_DATA_BIT_8;
340  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
341  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
342 
343  // only SPI & Sync. Mode
344  USART1n_Config->Order = USART1n_SPI_LSB;
345 
346 #if 1 // CPOLn : 0, CPHAn : 0 (X)
347  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
348  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
349 #endif
350 
351 #if 0 // CPOLn : 0, CPHAn : 1 (O)
352  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
353  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
354 #endif
355 
356 #if 0 // CPOLn : 1, CPHAn : 0 (X)
357  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
358  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
359 #endif
360 
361 #if 0 // CPOLn : 1, CPHAn : 1 (O)
362  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
363  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
364 #endif
365 
366  return HAL_OK;
367 }
USART1n_EDGE_Type Edge
USART1n_PARITY_BIT_Type Parity
USART1n_SPI_ORDER_Type Order
USART1n_OPMODE_Type Mode
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
USART1n_STOP_BIT_Type Stopbits

References USART1n_CFG_Type::ACK, USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, USART1n_CFG_Type::Edge, HAL_ERROR, HAL_OK, USART1n_CFG_Type::Mode, USART1n_CFG_Type::Order, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_DATA_BIT_8, USART1n_PARITY_BIT_NONE, USART1n_SPI_LSB, USART1n_SPI_MODE, USART1n_SPI_TX_FALLING, USART1n_SPI_TX_LEADEDGE_SAMPLE, USART1n_SPI_TX_LEADEDGE_SETUP, USART1n_SPI_TX_RISING, and USART1n_STOP_BIT_1.

◆ HAL_USART_Transmit()

uint32_t HAL_USART_Transmit ( USART1n_Type *  USART1x,
uint8_t *  txbuf,
uint32_t  buflen,
TRANSFER_BLOCK_Type  flag 
)

Send a block of data via USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[in]txbufPointer to Transmit buffer
[in]buflenLength of Transmit buffer
[in]flagFlag used in USART transfer
  • NONE_BLOCKING
  • BLOCKING
Returns
Number of bytes sent.
Note
when using USART in BLOCKING mode, a time-out condition is used via defined symbol USART_BLOCKING_TIMEOUT.

Definition at line 743 of file A31L12x_hal_usart1n.c.

744 {
745  uint32_t bToSend, bSent, timeOut;
746  uint8_t* pChar = txbuf;
747 
748  // init counter
749  bToSend = buflen;
750  bSent = 0;
751 
752  // Blocking Mode
753  if( flag == BLOCKING )
754  {
755  while( bToSend )
756  {
757  // send byte
758  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
759 
760  // wait until tx data register is empty with timeout
761  timeOut = USART1n_BLOCKING_TIMEOUT;
762  while( !( USART1x->ST & USART1n_SR_TXC ) )
763  {
764  if( timeOut == 0 )
765  {
766  break;
767  }
768  timeOut--;
769  }
770 
771  // if timeout
772  if( timeOut == 0 )
773  {
774  break;
775  }
776 
777  // clear flag
779 
780  // update counter
781  bToSend--;
782  bSent++;
783  }
784  }
785 
786  // Non-Blocking Mode
787  else
788  {
789  while( bToSend )
790  {
791  // if tx data register is not empty
792  if( !( USART1x->ST & USART1n_SR_DRE ) )
793  {
794  break;
795  }
796 
797  // send byte
798  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
799 
800  // update counter
801  bToSend--;
802  bSent++;
803  }
804  }
805 
806  // return
807  return bSent;
808 }
HAL_Status_Type HAL_USART_TransmitByte(USART1n_Type *USART1x, uint8_t Data)
Transmit a single data through USART peripheral.
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.

References BLOCKING, HAL_USART_ClearStatus(), HAL_USART_TransmitByte(), and USART1n_STATUS_TXC.

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◆ HAL_USART_TransmitByte()

HAL_Status_Type HAL_USART_TransmitByte ( USART1n_Type *  USART1x,
uint8_t  Data 
)

Transmit a single data through USART peripheral.

Parameters
[in]USART1xPointer to the target USART1
  • USART10
[in]DataData to transmit (must be 8-bit long)
Returns
HAL_Status_Type

Definition at line 701 of file A31L12x_hal_usart1n.c.

702 {
703  /* Check USART handle */
704  if( USART1x == NULL )
705  {
706  return HAL_ERROR;
707  }
708 
709  USART1x->TDR = Data;
710 
711  return HAL_OK;
712 }

References HAL_ERROR, and HAL_OK.

Referenced by HAL_USART_Transmit().

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◆ HAL_USART_UART_Mode_Config()

HAL_Status_Type HAL_USART_UART_Mode_Config ( USART1n_CFG_Type USART1n_Config)

Fills each USART1n_Config member with its default value:

  • 38400 bps
  • 8 Data Bit
  • No Parity Bit
  • 1 Stop Bit
    Parameters
    [out]USART1n_ConfigPointer to a USART1n_CFG_Type structure which will be initialized.
    Returns
    HAL_Status_Type

Definition at line 252 of file A31L12x_hal_usart1n.c.

253 {
254  /* Check USART1n_Config */
255  if( USART1n_Config == NULL )
256  {
257  return HAL_ERROR;
258  }
259 
260  USART1n_Config->Mode = USART1n_UART_MODE;
261  USART1n_Config->Baudrate = 38400;
262  USART1n_Config->Databits = USART1n_DATA_BIT_8;
263  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
264  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
265 
266  return HAL_OK;
267 }
USART1n_PARITY_BIT_Type Parity
USART1n_OPMODE_Type Mode
USART1n_DATA_BIT_Type Databits
USART1n_STOP_BIT_Type Stopbits

References USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, HAL_ERROR, HAL_OK, USART1n_CFG_Type::Mode, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_DATA_BIT_8, USART1n_PARITY_BIT_NONE, USART1n_STOP_BIT_1, and USART1n_UART_MODE.

◆ HAL_USART_USRT_Mode_Config()

HAL_Status_Type HAL_USART_USRT_Mode_Config ( USART1n_CFG_Type USART1n_Config)

Fills each USART1n_Config member with its default value:

  • 38400 bps
  • 8 Data Bit
  • No Parity Bit
  • 1 Stop Bit
    Parameters
    [out]USART1n_ConfigPointer to a USART1n_CFG_Type structure which will be initialized.
    Returns
    HAL_Status_Type

Definition at line 279 of file A31L12x_hal_usart1n.c.

280 {
281  /* Check USART1n_Config */
282  if( USART1n_Config == NULL )
283  {
284  return HAL_ERROR;
285  }
286 
287  USART1n_Config->Mode = USART1n_USRT_MODE;
288  USART1n_Config->Baudrate = 38400;
289  USART1n_Config->Databits = USART1n_DATA_BIT_8;
290  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
291  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
292 
293  // only SPI & Sync. Mode
294  USART1n_Config->Order = USART1n_SPI_LSB;
295 
296 #if 0 // CPOLn : 0, CPHAn : 0 (X)
297  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
298  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
299 #endif
300 
301 #if 1 // CPOLn : 0, CPHAn : 1 (O)
302  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
303  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
304 #endif
305 
306 #if 0 // CPOLn : 1, CPHAn : 0 (X)
307  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
308  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
309 #endif
310 
311 #if 0 // CPOLn : 1, CPHAn : 1 (O)
312  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
313  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
314 #endif
315 
316  return HAL_OK;
317 }
USART1n_EDGE_Type Edge
USART1n_PARITY_BIT_Type Parity
USART1n_SPI_ORDER_Type Order
USART1n_OPMODE_Type Mode
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
USART1n_STOP_BIT_Type Stopbits

References USART1n_CFG_Type::ACK, USART1n_CFG_Type::Baudrate, USART1n_CFG_Type::Databits, USART1n_CFG_Type::Edge, HAL_ERROR, HAL_OK, USART1n_CFG_Type::Mode, USART1n_CFG_Type::Order, USART1n_CFG_Type::Parity, USART1n_CFG_Type::Stopbits, USART1n_DATA_BIT_8, USART1n_PARITY_BIT_NONE, USART1n_SPI_LSB, USART1n_SPI_TX_FALLING, USART1n_SPI_TX_LEADEDGE_SAMPLE, USART1n_SPI_TX_LEADEDGE_SETUP, USART1n_SPI_TX_RISING, USART1n_STOP_BIT_1, and USART1n_USRT_MODE.