A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
Functions
A31L12x_hal_scu.c File Reference

Contains all functions support for scu firmware library on A31L12x. More...

Go to the source code of this file.

Functions

uint32_t HAL_SCU_ResetSourceStatus (void)
 Get Reset Source Status. More...
 
void HAL_SCU_SetNMI (uint32_t u32NmiCon)
 Set Non-Maskable Interrupt(NMI) Source Selection Register. More...
 
void HAL_SCU_SoftwareReset_Config (void)
 Check whether system reset ok or not. Generate s/w reset if a weak reset. More...
 
void HAL_SCU_SetWakupData (uint32_t u32Data)
 Set Wake-Up Timer Data. More...
 
void HAL_SCU_HIRCTRM_ClockConfig (uint32_t u32Ind)
 Change fine trim value of HIRC by one step. More...
 
void HAL_SCU_WDTRCTRM_ClockConfig (uint32_t u32Ind)
 Change fine trim value of WDTRC by one step. More...
 
void HAL_SCU_ClockMonitoring (uint32_t u32Acts, uint32_t u32Target)
 Configure Clock Monitoring. More...
 
void HAL_SCU_ClockMonitoring_Disable (void)
 Disable Clock Monitoring. More...
 
void HAL_SCU_ClockSource_Config (uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
 Set Clock Source, HIRC Frequency, and type of XMOSC. More...
 
void HAL_SCU_ClockSource_Enable (uint32_t u32ClkSrc, uint32_t u32HircDiv)
 Enable Clock Source. More...
 
void HAL_SCU_ClockSource_Disable (uint32_t u32ClkSrc)
 Disable Clock Source. More...
 
void HAL_SCU_MainXtal_PinConfig (void)
 Set XMOSC Pins for x-tal. More...
 
void HAL_SCU_SubXtal_PinConfig (void)
 Set XSOSC Pins for x-tal. More...
 
void HAL_SCU_SystemClockChange (uint32_t u32Target)
 Change System Clock. More...
 
void HAL_SCU_SystemClockDivider (uint32_t u32Div02, uint32_t u32Div13)
 Set System Clock Dividers, SCDIVR1 for RTCC and LCD Driver in case of using MCLK, SCDIVR2 for SysTick Timer and PCLK. More...
 
void HAL_SCU_CLKO_PinConfig (Pn_Type *Px, uint8_t pin_no)
 Set CLKO Pin for Clock Output. More...
 
void HAL_SCU_ClockOutput (uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
 Set Configuration for Clock Output. More...
 
void HAL_SCU_Peripheral_ClockConfig (uint32_t u32PeriClk1, uint32_t u32PeriClk2)
 Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b". More...
 
void HAL_SCU_Peripheral_EnableClock1 (uint32_t u32PeriClk1, uint32_t Ind)
 Set Each Peripheral Clock. More...
 
void HAL_SCU_Peripheral_EnableClock2 (uint32_t u32PeriClk2, uint32_t u32Ind)
 Set Each Peripheral Clock. More...
 
void HAL_SCU_Peripheral_ResetConfig (uint32_t u32PeriRst1, uint32_t u32PeriRst2)
 Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b". More...
 
void HAL_SCU_Peripheral_SetReset1 (uint32_t u32EachPeri1)
 Set/Reset Each Peripheral Block Reset of PPRST1 Register. More...
 
void HAL_SCU_Peripheral_SetReset2 (uint32_t u32EachPeri2)
 Set/Reset Each Peripheral Block Reset of PPRST2 Register. More...
 
void HAL_SCU_Peripheral_ClockSelection (uint32_t u32Peri, uint32_t u32ClkSrc)
 Peripheral Clock Selection of PPCLKSR Register. More...
 

Detailed Description

Contains all functions support for scu firmware library on A31L12x.

Version
1.00
Date
2020-05-29
Author
ABOV Application Team

Copyright(C) 2019, ABOV Semiconductor All rights reserved.

ABOV Disclaimer

IMPORTANT NOTICE ? PLEASE READ CAREFULLY ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders. Purchasers are entirely responsible for the choice, selection, and use of ABOV products and ABOV assumes no liability for application assistance or the design of purchasers' products. No license, express or implied, to any intellectual property rights is granted by ABOV herein. ABOV disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications. ABOV and the ABOV logo are trademarks of ABOV. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces the information previously supplied in any former versions of this document. 2020 ABOV Semiconductor All rights reserved

Definition in file A31L12x_hal_scu.c.

Function Documentation

◆ HAL_SCU_CLKO_PinConfig()

void HAL_SCU_CLKO_PinConfig ( Pn_Type *  Px,
uint8_t  pin_no 
)

Set CLKO Pin for Clock Output.

Parameters
[in]PxPointer to the target
  • PC only
[in]pin_noPin Number
  • 0 ~ 1
Returns
None

This function sets selected pin's alternative for CLKO.

Definition at line 401 of file A31L12x_hal_scu.c.

402 {
403  bitsp( Px->MOD, pin_no * 2, 2, 2 ); // PC0 CLKO 0: Input Mode 1: Output Mode 2: Alternative Function Mode
404  if( pin_no < 8 )
405  {
406  bitsp( Px->AFSR1, pin_no * 4, 4, 0 ); // PC0 CLKO 0: CLKO 1: ---- 2: ---- 3: ---- 4: SC0IN 5: ---- 6: ---- 7: COM0
407  }
408  else
409  {
410  pin_no -= 8;
411  bitsp( Px->AFSR2, pin_no * 4, 4, 0 ); // PC1 CLKO 0: CLKO 1: ---- 2: TXD0 3: ---- 4: SC0PWR 5: ---- 6: ---- 7: COM1
412  }
413  bitsp( Px->PUPD, pin_no * 2, 2, 0 ); // PC0 CLKO 0: Push-Pull Output 1: Open-Drain Output
414 }

◆ HAL_SCU_ClockMonitoring()

void HAL_SCU_ClockMonitoring ( uint32_t  u32Acts,
uint32_t  u32Target 
)

Configure Clock Monitoring.

Parameters
[in]u32ActsClock Monitoring Action Selection
  • MACTS_FlagChk, MACTS_RstGen, MACTS_SysClkChg
[in]u32TargetClock Monitoring Target Selection
  • MONCS_MCLK, MONCS_HIRC, MONCS_XMOSC, MONCS_XSOSC
Returns
None

This function checks whether the target clock oscillates.

Definition at line 207 of file A31L12x_hal_scu.c.

208 {
209  if( SCUCG->CLKSRCR_b.WDTRCEN == 0 )
210  {
211  SCUCG->CLKSRCR = SCUCG->CLKSRCR
212  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
213  | CLKSRCR_WDTRCEN; // The WDTRC should be enabled to use clock monitoring
214  }
215  SCUCG->CMONCR = ( 0x3uL << 2 ) | u32Acts | u32Target; // Clear MONFLAG and NMINTFG, Set Monitoring Target and Monitoring Action
216  SCUCG->CMONCR_b.MONEN = 1; // Clock Monitoring Enable
217 }

◆ HAL_SCU_ClockMonitoring_Disable()

void HAL_SCU_ClockMonitoring_Disable ( void  )

Disable Clock Monitoring.

Returns
None

This function disables clock monitoring. Before disabling the ¡°clock monitoring¡± function, you need to take step to clear the MACTS[1:0] bits of SCU_CMONCR register to ¡°00b¡±.

Definition at line 226 of file A31L12x_hal_scu.c.

227 {
228  SCUCG->CMONCR_b.MACTS = 0; // Clear MACTS bits first
229  SCUCG->CMONCR_b.MONEN = 0; // Disable clock monitoring function
230 }

◆ HAL_SCU_ClockOutput()

void HAL_SCU_ClockOutput ( uint32_t  u32ClkSrc,
uint32_t  u32Level,
uint32_t  u32Div 
)

Set Configuration for Clock Output.

Parameters
[in]u32ClkSrcClock to output
  • CLKOS_MCLK, CLKOS_WDTRC, CLKOS_HIRC, CLKOS_HCLK, CLKOS_PCLK
[in]u32LevelClock Output Polarity when Disable
  • POLSEL_Low, POLSEL_High
[in]u32DivOutput Clock Divide
  • CLKODIV_SelectedClock1, CLKODIV_SelectedClock2
  • CLKODIV_SelectedClock4, CLKODIV_SelectedClock8
  • CLKODIV_SelectedClock16, CLKODIV_SelectedClock32
  • CLKODIV_SelectedClock64, CLKODIV_SelectedClock128
Returns
None

This function sets clock output related configuration.

Definition at line 433 of file A31L12x_hal_scu.c.

434 {
435  SCUCG->CLKOCR = 0
436  | ( 1 << SCUCG_CLKOCR_CLKOEN_Pos ) // CLKO Enable
437  | u32Level // 0: Low Level 1: High Level
438  | u32Div // 0: div_1 1: div_2 2: div_4 3: div_8 4: div_16 5: div_32 6: div_64 7: div_128
439  | u32ClkSrc // 0: MCLK 1: WDTRC 2: HIRC 3: HCLK 4: PCLK
440  ;
441 }

◆ HAL_SCU_ClockSource_Config()

void HAL_SCU_ClockSource_Config ( uint32_t  u32FreIRC,
uint32_t  u32TypeXM,
uint32_t  u32ClkSrc 
)

Set Clock Source, HIRC Frequency, and type of XMOSC.

Parameters
[in]u32FreIRCHIRC Frequency Selection
  • HIRCSEL_HIRC1, HIRCSEL_HIRC2, HIRCSEL_HIRC4, HIRCSEL_HIRC8
[in]u32TypeXMMain Oscillator Type and Frequency Range Selection
  • XMFRNG_Xtal, XMFRNG_Clock
[in]u32ClkSrcClock Source
  • CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
Returns
None

This function sets clock source, HIRC frequency, and x-tal type of XMOSC. If target clock source is one of XMOSC and XSOSC, the x-tal pins should be set as alternative before this function call. To set alternative for x-tal, Use HAL_SCU_MainXtal_PinConfig() and HAL_SCU_SubXtal_PinConfig() functions.

Definition at line 249 of file A31L12x_hal_scu.c.

250 {
251  uint32_t tmp;
252 
253  tmp = SCUCG->CLKSRCR & 0x0000000F;
254  tmp |= ( ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
255  | u32FreIRC // HIRC Frequency
256  | u32TypeXM // XMOSC type: x-tal or external clock
257  | u32ClkSrc );
258  SCUCG->CLKSRCR = tmp;
259 }

◆ HAL_SCU_ClockSource_Disable()

void HAL_SCU_ClockSource_Disable ( uint32_t  u32ClkSrc)

Disable Clock Source.

Parameters
[in]u32ClkSrcClock Source
  • CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
Returns
None

This function is used to disable original source after system clock change.

[Example]
// disable XMOSC, SXOSC
HAL_SCU_ClockSource_Disable( CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN );

Definition at line 312 of file A31L12x_hal_scu.c.

313 {
314  uint32_t tmp;
315 
316  tmp = SCUCG->CLKSRCR & 0x0000ffff;
317  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
318  tmp &= ~u32ClkSrc;
319  SCUCG->CLKSRCR = tmp;
320 }

◆ HAL_SCU_ClockSource_Enable()

void HAL_SCU_ClockSource_Enable ( uint32_t  u32ClkSrc,
uint32_t  u32HircDiv 
)

Enable Clock Source.

Parameters
[in]u32ClkSrcClock Source
  • CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
[in]u32HircDivHIRC Frequency Selection
  • HIRCSEL_HIRC1, HIRCSEL_HIRC2, HIRCSEL_HIRC4, HIRCSEL_HIRC8
Returns
None

This function is used to enable original source after system clock change.

[Example]
// eable HIRC, XMOSC, SXOSC, WDTRC and select HIRCSEL_HIRC1(32MHz HIRC)
HAL_SCU_ClockSource_Enable( CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN | CLKSRCR_WDTRCEN, HIRCSEL_HIRC1 );

Definition at line 278 of file A31L12x_hal_scu.c.

279 {
280 #if 0 // before bug fix
281  uint32_t tmp;
282 
283  tmp = SCUCG->CLKSRCR & 0x0000ffff; // 0x00000fff°¡ ¿ÇÀ» µí...
284  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
285  tmp |= u32ClkSrc;
286  tmp |= u32HircDiv;
287  SCUCG->CLKSRCR = tmp;
288 #else // after bug fix
289  SCUCG->CLKSRCR = SCUCG->CLKSRCR
290  & ~( SCUCG_CLKSRCR_WTIDKY_Msk | SCUCG_CLKSRCR_HIRCSEL_Msk )
291  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
292  | u32HircDiv
293  | u32ClkSrc
294  ;
295 #endif
296 }

◆ HAL_SCU_HIRCTRM_ClockConfig()

void HAL_SCU_HIRCTRM_ClockConfig ( uint32_t  u32Ind)

Change fine trim value of HIRC by one step.

Parameters
[in]u32IndIndicator for +/- one step
  • HIRC_UP_ONESTEP, HIRC_DOWN_ONESTEP
Returns
None

This function changes fine trim value by one step. If the u32Ind is HIRC_UP_ONESTEP, HIRC frequency is changed up by about 140kHz. If the u32Ind is HIRC_DOWN_ONESTEP, HIRC frequency is changed down by about 140kHz.

Definition at line 113 of file A31L12x_hal_scu.c.

114 {
115  uint32_t tmp, ntrim;
116 
117  tmp = ( SCUCC->HIRCTRM ) & 0x001fuL; // Read current fine trim value of HIRC
118  if( u32Ind == HIRC_UP_ONESTEP ) // Increment by one step(about 140kHz)
119  {
120  if( tmp != 0x0f )
121  {
122  tmp++;
123  }
124  }
125  else // Decrement by one step(about 140kHz)
126  {
127  if( tmp != 0x10 )
128  {
129  tmp--;
130  }
131  }
132  tmp &= 0x1f; // Fine trim value is only 5-bits
133  tmp |= ( ( SCUCC->HIRCTRM ) & 0x00E0uL ); // Read Coarse trim value
134  ntrim = ( tmp << 8 ) ^ 0x0000FF00; // Make write complement key
135  SCUCC->HIRCTRM = ( ( uint32_t )SCUCC_HIRCTRM_WTIDKY_Value << SCUCC_HIRCTRM_WTIDKY_Pos ) // Write new HIRC trim value with write ID and complement key
136  | ntrim
137  | tmp;
138 }

◆ HAL_SCU_MainXtal_PinConfig()

void HAL_SCU_MainXtal_PinConfig ( void  )

Set XMOSC Pins for x-tal.

Returns
None

This function sets PE[3:2]'s alternative for x-tal of XMOSC.

Definition at line 327 of file A31L12x_hal_scu.c.

328 {
329  PE->AFSR1 &= 0xffff00ffuL; // PE[3:2]: XOUT/XIN
330  PE->PUPD &= 0xffffff0fuL; // PE[3:2]: Pull-up/down resistors Disable
331  PE->MOD &= 0xffffff0fuL;
332  PE->MOD |= 0x000000a0uL; // PE[3:2]: Alternative Function
333 }

◆ HAL_SCU_Peripheral_ClockConfig()

void HAL_SCU_Peripheral_ClockConfig ( uint32_t  u32PeriClk1,
uint32_t  u32PeriClk2 
)

Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".

Parameters
[in]u32PeriClk1Values for TIMER50, TIMER40 ~ TIMER43, PA ~ PF
[in]u32PeriClk2Values for the Others Peripheral
Returns
None

This function sets the peripheral clock. A peripheral works properly during the corresponding bit is set to "1b".

Definition at line 453 of file A31L12x_hal_scu.c.

454 {
455  SCUCG->PPCLKEN1 = u32PeriClk1; // Set peripheral clock of timers and ports
456  SCUCG->PPCLKEN2 = u32PeriClk2; // Set peripheral clock of the others
457 }

◆ HAL_SCU_Peripheral_ClockSelection()

void HAL_SCU_Peripheral_ClockSelection ( uint32_t  u32Peri,
uint32_t  u32ClkSrc 
)

Peripheral Clock Selection of PPCLKSR Register.

Parameters
[in]u32PeriPeripheral Selection
  • PPCLKSR_T50CLK, PPCLKSR_LPUTCLK, PPCLKSR_RTCCLK, PPCLKSR_LCDCLK, PPCLKSR_WDTCLK
[in]u32ClkSrcPeripheral Clock Selection
  • PPCLKSR_T50CLK: T50CLK_PCLK, T50CLK_WDTRC, T50CLK_HIRC, T50CLK_XSOSC
  • PPCLKSR_LPUTCLK: LPUTCLK_PCLK, LPUTCLK_HIRC, LPUTCLK_XSOSC
  • PPCLKSR_RTCCLK: RTCCLK_LowLevel, RTCCLK_XSOSC, RTCCLK_WDTRC, RTCCLK_DividedMCLK
  • PPCLKSR_LCDCLK: LCDCLK_DividedMCLK, LCDCLK_XSOSC, LCDCLK_WDTRC
  • PPCLKSR_WDTCLK: WDTCLK_WDTRC, WDTCLK_PCLK

This function resets each peripheral block.

Definition at line 592 of file A31L12x_hal_scu.c.

593 {
594  SCUCG->PPCLKSR &= ~u32Peri;
595  SCUCG->PPCLKSR |= u32ClkSrc;
596 }

◆ HAL_SCU_Peripheral_EnableClock1()

void HAL_SCU_Peripheral_EnableClock1 ( uint32_t  u32PeriClk1,
uint32_t  Ind 
)

Set Each Peripheral Clock.

Parameters
[in]u32PeriClk1PeriClk1
  • PPCLKEN1_T50CLKE, PPCLKEN1_T40CLKE ~ PPCLKEN1_T43CLKE
  • PPCLKEN1_PACLKE ~ PPCLKEN1_PFCLKE
[in]IndEnable/Disable Peripheral Clock.
  • PPxCLKE_Disable, PPxCLKE_Enable
Returns
None

This function sets each peripheral clock of timers and Ports.

Definition at line 471 of file A31L12x_hal_scu.c.

472 {
473  if( Ind )
474  {
475  SCUCG->PPCLKEN1 |= u32PeriClk1; // Enable a peripheral clock of timers and ports
476  }
477  else
478  {
479  SCUCG->PPCLKEN1 &= ~u32PeriClk1; // Disable a peripheral clock of timers and ports
480  }
481 }

Referenced by HAL_TIMER4n_DeInit(), and HAL_TIMER4n_Init().

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◆ HAL_SCU_Peripheral_EnableClock2()

void HAL_SCU_Peripheral_EnableClock2 ( uint32_t  u32PeriClk2,
uint32_t  u32Ind 
)

Set Each Peripheral Clock.

Parameters
[in]u32PeriClk2PeriClk2
  • PPCLKEN2_DMACLKE, PPCLKEN2_CMP0CLKE ~ PPCLKEN2_CMP1CLKE
  • PPCLKEN2_SC0CLKE ~ PPCLKEN2_SC1CLKE, PPCLKEN2_SPI0CLKE ~ PPCLKEN2_SPI1CLKE
  • PPCLKEN2_FMCLKE, PPCLKEN2_LVICLKE, PPCLKEN2_WDTCLKE, PPCLKEN2_LPUTCLKE
  • PPCLKEN2_LCDCLKE, PPCLKEN2_CRCLKE, PPCLKEN2_RTCCLKE, PPCLKEN2_ADCLKE
  • PPCLKEN2_I2C0CLKE ~ PPCLKEN2_I2C1CLKE
  • PPCLKEN2_UT0CLKE ~ PPCLKEN2_UT1CLKE, PPCLKEN2_UST10CLKE
[in]u32IndEnable/Disable Peripheral Clock.
  • PPxCLKE_Disable, PPxCLKE_Enable
Returns
None

This function sets each peripheral clock of the others.

Definition at line 499 of file A31L12x_hal_scu.c.

500 {
501  if( u32Ind )
502  {
503  SCUCG->PPCLKEN2 |= u32PeriClk2; // Enable a peripheral clock of others
504  }
505  else
506  {
507  SCUCG->PPCLKEN2 &= ~u32PeriClk2; // Disable a peripheral clock of others
508  }
509 }

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_COMP_Deinit(), HAL_COMP_Init(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_LCD_Init(), HAL_LPUART_DeInit(), HAL_LPUART_Init(), HAL_LVI_Init(), HAL_RTCC_DeInit(), HAL_RTCC_Init(), HAL_SC_DeInit(), HAL_SC_Init(), HAL_SPIn_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WDT_Init(), and SPIn_DeInit().

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◆ HAL_SCU_Peripheral_ResetConfig()

void HAL_SCU_Peripheral_ResetConfig ( uint32_t  u32PeriRst1,
uint32_t  u32PeriRst2 
)

Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".

Parameters
[in]u32PeriRst1Values for TIMER50, TIMER40 ~ TIMER43, PA ~ PF
[in]u32PeriRst2Values for the Others Peripheral
Returns
None

This function reset peripheral block during the corresponding bit is set to "1b". After reset of a block, the corresponding bit should be cleared to "0b" for operation.

Definition at line 521 of file A31L12x_hal_scu.c.

522 {
523  uint32_t i;
524 
525  SCUCG->PPRST1 = u32PeriRst1; // Reset peripheral block of timers and ports if the corresponding bit is "1b"
526  SCUCG->PPRST2 = u32PeriRst2; // Reset peripheral block of the others
527  for( i = 0 ; i < 10 ; i++ )
528  {
529  NOP();
530  }
531  SCUCG->PPRST1 = 0x0uL; // Clear the peripheral reset bits
532  SCUCG->PPRST2 = 0x0uL;
533 }

◆ HAL_SCU_Peripheral_SetReset1()

void HAL_SCU_Peripheral_SetReset1 ( uint32_t  u32EachPeri1)

Set/Reset Each Peripheral Block Reset of PPRST1 Register.

Parameters
[in]u32EachPeri1Peri1
  • PPRST1_T50RST, PPRST1_T40RST ~ PPRST1_T43RST
  • PPRST1_PARST ~ PPRST1_PFRST

This function resets each peripheral block.

Definition at line 543 of file A31L12x_hal_scu.c.

544 {
545  uint32_t i;
546 
547  SCUCG->PPRST1 = u32EachPeri1; // Reset a peripheral block
548  for( i = 0 ; i < 10 ; i++ )
549  {
550  NOP();
551  }
552  SCUCG->PPRST1 = 0; // Clear the peripheral reset bit
553 }

Referenced by HAL_TIMER4n_DeInit().

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◆ HAL_SCU_Peripheral_SetReset2()

void HAL_SCU_Peripheral_SetReset2 ( uint32_t  u32EachPeri2)

Set/Reset Each Peripheral Block Reset of PPRST2 Register.

Parameters
[in]u32EachPeri2Peri2
  • PPRST2_DMARST, PPRST2_CMP0RST ~ PPRST2_CMP1RST, PPRST2_SC0RST ~ PPRST2_SC1RST
  • PPRST2_SPI0RST ~ PPRST2_SPI1RST, PPRST2_FMCRST, PPRST2_LVIRST, PPRST2_LPUTRST
  • PPRST2_LCDRST, PPRST2_CRRST, PPRST2_RTCRST, PPRST2_ADRST
  • PPRST2_I2C0RST ~ PPRST2_I2C1RST, PPRST2_UT0RST ~ PPRST2_UT1RST, PPRST2_UST10RST

This function resets each peripheral block.

Definition at line 565 of file A31L12x_hal_scu.c.

566 {
567  uint32_t i;
568 
569  SCUCG->PPRST2 = u32EachPeri2; // Reset a peripheral block
570  for( i = 0 ; i < 10 ; i++ )
571  {
572  NOP();
573  }
574  SCUCG->PPRST2 = 0; // Clear the peripheral reset bit
575 }

Referenced by HAL_COMP_Deinit(), HAL_COMP_Init(), HAL_CRC_DeInit(), HAL_I2C_Init(), HAL_LPUART_DeInit(), HAL_LPUART_Init(), HAL_RTCC_DeInit(), HAL_SC_DeInit(), HAL_SC_Init(), HAL_SPIn_Init(), HAL_UART_DeInit(), HAL_USART_DeInit(), HAL_USART_Init(), and SPIn_DeInit().

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◆ HAL_SCU_ResetSourceStatus()

uint32_t HAL_SCU_ResetSourceStatus ( void  )

Get Reset Source Status.

Returns
Reset Source

This function gets reset source status and clear the register.

Definition at line 52 of file A31L12x_hal_scu.c.

53 {
54  uint32_t tmp;
55 
56  tmp = SCUCC->RSTSSR; // Get reset source status
57 #if 0 // before bug fix
58  SCUCC->RSTSSR = 0x3FuL; // Clear all reset source status
59 #else // after bug fix
60  SCUCC->RSTSSR = 0x7fuL; // Clear all reset source status
61 #endif
62  return tmp;
63 }

◆ HAL_SCU_SetNMI()

void HAL_SCU_SetNMI ( uint32_t  u32NmiCon)

Set Non-Maskable Interrupt(NMI) Source Selection Register.

Parameters
[in]u32NmiConValues for NMISRCR register
Returns
None

This function sets NMISRCR register.

Definition at line 72 of file A31L12x_hal_scu.c.

73 {
74  SCUCC->NMISRCR = u32NmiCon;
75 }

◆ HAL_SCU_SetWakupData()

void HAL_SCU_SetWakupData ( uint32_t  u32Data)

Set Wake-Up Timer Data.

Parameters
[in]u32Data
Returns
None

This function sets wake-up timer data to wait for release of deep sleep mode.

Note
1. When HIRC is system clock, its value should be set to be at least more than 4us.
  1. When WDTRC is system clock, its value should be set to be at least more than 100us.

Definition at line 98 of file A31L12x_hal_scu.c.

99 {
100  SCUCC->WUTDR = u32Data;
101 }

◆ HAL_SCU_SoftwareReset_Config()

void HAL_SCU_SoftwareReset_Config ( void  )

Check whether system reset ok or not. Generate s/w reset if a weak reset.

Returns
None

This function checks system reset validation and Generate s/w reset if a weak reset.

Definition at line 82 of file A31L12x_hal_scu.c.

83 {
84  if( SCUCC->SRSTVR_b.VALID != 0x55 )
85  {
86  SCUCC_GenSwRst(); // Generate S/W reset on invalid reset
87  }
88 }

◆ HAL_SCU_SubXtal_PinConfig()

void HAL_SCU_SubXtal_PinConfig ( void  )

Set XSOSC Pins for x-tal.

Returns
None

This function sets PE[1:0]'s alternative for x-tal of XSOSC.

Definition at line 340 of file A31L12x_hal_scu.c.

341 {
342  PE->AFSR1 &= 0xffffff00uL; // PE[1:0]: SXOUT/SXIN
343  PE->PUPD &= 0xfffffff0uL; // PE[1:0]: Pull-up/down resistors Disable
344  PE->MOD &= 0xfffffff0uL;
345  PE->MOD |= 0x0000000auL; // PE[1:0]: Alternative Function
346 }

◆ HAL_SCU_SystemClockChange()

void HAL_SCU_SystemClockChange ( uint32_t  u32Target)

Change System Clock.

Parameters
[in]u32TargetTarget Clock
  • MCLKSEL_HIRC, MCLKSEL_XMOSC, MCLKSEL_XSOSC, MCLKSEL_WDTRC
Returns
None

This function changes system clock to target source.

Definition at line 356 of file A31L12x_hal_scu.c.

357 {
358  SCUCG->SCCR = ( SCUCG_SCCR_WTIDKY_Value << SCUCG_SCCR_WTIDKY_Pos ) // Write ID
359  | u32Target; // Target Clock Source
360 }

◆ HAL_SCU_SystemClockDivider()

void HAL_SCU_SystemClockDivider ( uint32_t  u32Div02,
uint32_t  u32Div13 
)

Set System Clock Dividers, SCDIVR1 for RTCC and LCD Driver in case of using MCLK, SCDIVR2 for SysTick Timer and PCLK.

Parameters
[in]u32Div02Values for Divider 0 and 2
  • Clock Divide for HCLK (Divider 0)
    • HDIV_MCLK16, HDIV_MCLK8, HDIV_MCLK4, HDIV_MCLK2, HDIV_MCLK1
  • Clock Divide for RTCC and LCD Driver (Divider 2)
    • WLDIV_MCLK64, WLDIV_MCLK128, WLDIV_MCLK256, WLDIV_MCLK512, WLDIV_MCLK1024
[in]u32Div13Values for Divider 1 and 3
  • Clock Divide for PCLK (Divider 1)
    • PDIV_HCLK1, PDIV_HCLK2, PDIV_HCLK4, PDIV_HCLK8
  • Clock Divide for SysTick Timer (Divider 3)
    • SYSTDIV_HCLK1, SYSTDIV_HCLK2, SYSTDIV_HCLK4, SYSTDIV_HCLK8
Returns
None

This function changes system clock to target source.

Definition at line 379 of file A31L12x_hal_scu.c.

380 {
381  // Divider 0 for HCLK: 000/001/010/011/100: MCLK is divided by 16/8/4/2/1
382  // Divider 2 for RTCC and LCD Driver: 000/001/010/011/100: MCLK is divided by 64/128/256/512/1024
383  SCUCG->SCDIVR1 = u32Div02;
384 
385  // Divider 1 for PCLK: 00/01/10/11: HCLK is divided by 1/2/4/8
386  // Divider 3 for SysTick Timer: 00/01/10/11: HCLK is divided by 1/2/4/8
387  SCUCG->SCDIVR2 = u32Div13;
388 }

◆ HAL_SCU_WDTRCTRM_ClockConfig()

void HAL_SCU_WDTRCTRM_ClockConfig ( uint32_t  u32Ind)

Change fine trim value of WDTRC by one step.

Parameters
[in]u32IndIndicator for +/- one step
  • WDTRC_UP_ONESTEP, WDTRC_DOWN_ONESTEP
Returns
None

This function changes fine trim value by one step. If the u32Ind is WDTRC_UP_ONESTEP, WDTRC frequency is changed up by about 1.1kHz. If the u32Ind is WDTRC_DOWN_ONESTEP, WDTRC frequency is changed down by about 1.1kHz.

Definition at line 150 of file A31L12x_hal_scu.c.

151 {
152  uint32_t ctmp, ftmp, ntrim;
153 
154  ftmp = ( SCUCC->WDTRCTRM ) & 0x0007uL; // Read current fine trim value of WDTRC
155  ctmp = ( SCUCC->WDTRCTRM ) & 0x00F0uL; // Read current coarse trim value of WDTRC
156  if( u32Ind == WDTRC_UP_ONESTEP ) // Increment by one step(about 1.1kHz)
157  {
158  ftmp++;
159  ftmp &= 0x07uL; // Fine trim value is only 3-bits
160  if( ftmp == 0x04 )
161  {
162  if( ctmp != 0x70 )
163  {
164  ctmp += 0x10uL;
165  }
166  else
167  {
168  ftmp = 0x03uL;
169  }
170  }
171  }
172  else // Decrement by one step(about 1.1kHz)
173  {
174  ftmp--;
175  ftmp &= 0x07uL; // Fine trim value is only 3-bits
176  if( ftmp == 0x03 )
177  {
178  if( ctmp != 0x80 )
179  {
180  ctmp -= 0x10uL;
181  }
182  else
183  {
184  ftmp = 0x04uL;
185  }
186  }
187  }
188  ctmp &= 0x00f0uL; // Coarse trim value is only 4-bits
189  ctmp |= ftmp;
190  ntrim = ( ctmp << 8 ) ^ 0x0000FF00; // Make write complement key
191  SCUCC->WDTRCTRM = ( SCUCC_WDTRCTRM_WTIDKY_Value << SCUCC_WDTRCTRM_WTIDKY_Pos ) // Write new WDTRC trim value with write ID and complement key
192  | ntrim
193  | ctmp;
194 }