A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31L12x_hal_timer5n.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31L12x_hal_timer5n.h"
41 
42 /* Public Functions --------------------------------------------------------- */
43 //******************************************************************************
44 // Function
45 //******************************************************************************
46 
47 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
58 HAL_Status_Type HAL_TIMER5n_Init( TIMER5n_Type* TIMER5x, TIMER5n_CFG_Type* TIMER5n_Config )
59 {
60  /* Check TIMER5 handle */
61  if( TIMER5x == NULL )
62  {
63  return HAL_ERROR;
64  }
65 
66 #if 1 // supported
67  if( TIMER5x == ( TIMER5n_Type* )TIMER50 )
68  {
69  // enable peripheral clock
70  SCUCG->PPCLKEN1_b.T50CLKE = 1;
71  }
72 #endif
73 
74 #if 0 // not supported
75  if( TIMER5x == ( TIMER5n_Type* )TIMER51 )
76  {
77  // enable peripheral clock
78  SCUCG->PPCLKEN1_b.T51CLKE = 1;
79  }
80 #endif
81 
82  // CR
83  TIMER5x->CR = 0
84  | ( TIMER5n_Config->T5nMS << TIMER5n_CR_T5nMS_Pos )
85  | ( TIMER5n_Config->T5nCLK << TIMER5n_CR_T5nCLK_Pos )
86  | ( TIMER5n_Config->T5nECE << TIMER5n_CR_T5nECE_Pos )
87  | ( TIMER5n_Config->T5nINSEL << TIMER5n_CR_T5nINSEL_Pos )
88  | ( TIMER5n_Config->T5nINPOL << TIMER5n_CR_T5nINPOL_Pos )
89  | ( TIMER5n_Config->T5nOPOL << TIMER5n_CR_T5nOPOL_Pos )
90  ;
91 
92  // ADR & BDR
93  TIMER5x->ADR = TIMER5n_Config->ADR;
94  TIMER5x->BDR = TIMER5n_Config->BDR;
95 
96  // PREDR
97  TIMER5x->PREDR_b.PRED = TIMER5n_Config->Prescaler;
98 
99  // clear counter and prescaler
100  HAL_TIMER5n_ClearCounter( TIMER5x );
101 
102  return HAL_OK;
103 }
104 
105 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
112 HAL_Status_Type HAL_TIMER5n_DeInit( TIMER5n_Type* TIMER5x )
113 {
114  /* Check TIMER5 handle */
115  if( TIMER5x == NULL )
116  {
117  return HAL_ERROR;
118  }
119 
120  // Disable timer/counter
121  TIMER5x->CR_b.T5nEN = 0;
122 
123 #if 1 // supported
124  if( TIMER5x == ( TIMER5n_Type* )TIMER50 )
125  {
126  // disable peripheral clock
127  SCUCG->PPCLKEN1_b.T50CLKE = 0;
128  }
129 #endif
130 
131 #if 0 // not supported
132  if( TIMER5x == ( TIMER5n_Type* )TIMER51 )
133  {
134  // disable peripheral clock
135  SCUCG->PPCLKEN1_b.T51CLKE = 0;
136  }
137 #endif
138 
139  return HAL_OK;
140 }
141 
142 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
156 HAL_Status_Type HAL_TIMER5n_ConfigInterrupt( TIMER5n_Type* TIMER5x, TIMER5n_INT_Type TIMER5n_IntCfg, FunctionalState NewState )
157 {
158  /* Check TIMER5 handle */
159  if( TIMER5x == NULL )
160  {
161  return HAL_ERROR;
162  }
163 
164  switch( TIMER5n_IntCfg )
165  {
167  if( NewState == ENABLE )
168  {
169  TIMER5x->CR_b.T5nMIEN = 1;
170  }
171  else if( NewState == DISABLE )
172  {
173  TIMER5x->CR_b.T5nMIEN = 0;
174  }
175  break;
177  if( NewState == ENABLE )
178  {
179  TIMER5x->CR_b.T5nCIEN = 1;
180  }
181  else if( NewState == DISABLE )
182  {
183  TIMER5x->CR_b.T5nCIEN = 0;
184  }
185  break;
186  }
187 
188  return HAL_OK;
189 }
190 
191 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
201 HAL_Status_Type HAL_TIMER5n_Cmd( TIMER5n_Type* TIMER5x, FunctionalState NewState )
202 {
203  /* Check TIMER5 handle */
204  if( TIMER5x == NULL )
205  {
206  return HAL_ERROR;
207  }
208 
209  if( NewState == ENABLE )
210  {
211  TIMER5x->CR_b.T5nEN = TIMER5n_CR_T5nEN_Enable;
212  }
213  else
214  {
215  TIMER5x->CR_b.T5nEN = TIMER5n_CR_T5nEN_Disable;
216  }
217 
218  return HAL_OK;
219 }
220 
221 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
229 {
230  /* Check TIMER5 handle */
231  if( TIMER5x == NULL )
232  {
233  return HAL_ERROR;
234  }
235 
236  TIMER5x->CR_b.T5nCLR = TIMER5n_CR_T5nCLR_Clear;
237 
238  return HAL_OK;
239 }
240 
241 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
253 HAL_Status_Type HAL_TIMER5n_UpdateCountValue( TIMER5n_Type* TIMER5x, uint8_t CountCh, uint16_t Value )
254 {
255  /* Check TIMER5 handle */
256  if( TIMER5x == NULL )
257  {
258  return HAL_ERROR;
259  }
260 
261  switch( CountCh )
262  {
263  case 0:
264  TIMER5x->ADR = Value;
265  break;
266  case 1:
267  TIMER5x->BDR = Value;
268  break;
269  }
270 
271  return HAL_OK;
272 }
273 
274 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
283 HAL_Status_Type HAL_TIMER5n_ClearStatus( TIMER5n_Type* TIMER5x, uint32_t mask )
284 {
285  /* Check TIMER5 handle */
286  if( TIMER5x == NULL )
287  {
288  return HAL_ERROR;
289  }
290 
291  TIMER5x->CR = TIMER5x->CR
292  & ~TIMER5n_CR_T5nMIFLAG_Msk
293  & ~TIMER5n_CR_T5nCIFLAG_Msk
294  & ~TIMER5n_CR_T5nCLIFLAG_Msk
295  | mask
296  ;
297 
298  return HAL_OK;
299 }
300 
301 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
308 uint8_t HAL_TIMER5n_GetStatus( TIMER5n_Type* TIMER5x )
309 {
310  return TIMER5x->CR;
311 }
312 
313 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
320 uint16_t HAL_TIMER5n_GetCaptureData( TIMER5n_Type* TIMER5x )
321 {
322  return TIMER5x->CAPDR;
323 }
324 
TIMER5n_CR_T5nCLK_Enum T5nCLK
HAL_Status_Type HAL_TIMER5n_DeInit(TIMER5n_Type *TIMER5x)
Close Timer/Counter device.
TIMER5n_CR_T5nINSEL_Enum T5nINSEL
HAL_Status_Type HAL_TIMER5n_Init(TIMER5n_Type *TIMER5x, TIMER5n_CFG_Type *TIMER5n_Config)
Initialize the TIMER5n peripheral with the specified parameters.
HAL_Status_Type HAL_TIMER5n_UpdateCountValue(TIMER5n_Type *TIMER5x, uint8_t CountCh, uint16_t Value)
Update value.
HAL_Status_Type HAL_TIMER5n_ClearCounter(TIMER5n_Type *TIMER5x)
Clear Counter and Prescaler.
HAL_Status_Type HAL_TIMER5n_ConfigInterrupt(TIMER5n_Type *TIMER5x, TIMER5n_INT_Type TIMER5n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
HAL_Status_Type HAL_TIMER5n_ClearStatus(TIMER5n_Type *TIMER5x, uint32_t mask)
Clear Timer Status.
HAL_Status_Type
TIMER5n_INT_Type
HAL_Status_Type HAL_TIMER5n_Cmd(TIMER5n_Type *TIMER5x, FunctionalState NewState)
Start/Stop Timer/Counter device.
TIMER5n_CR_T5nECE_Enum T5nECE
TIMER5n_CR_T5nINPOL_Enum T5nINPOL
uint16_t HAL_TIMER5n_GetCaptureData(TIMER5n_Type *TIMER5x)
Read value of capture register in timer/counter device.
TIMER5n_CR_T5nMS_Enum T5nMS
FunctionalState
Contains all macro definitions and function prototypes support for timer5n firmware library on A31L12...
TIMER5n_CR_T5nOPOL_Enum T5nOPOL
uint8_t HAL_TIMER5n_GetStatus(TIMER5n_Type *TIMER5x)
Get Timer Status.