A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31L12x_hal_crc.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31L12x_hal_crc.h"
41 #include "A31L12x_hal_scu.h"
42 
43 /* Public Functions --------------------------------------------------------- */
44 //******************************************************************************
45 // Function
46 //******************************************************************************
47 
48 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
54 {
55  // enable peripheral clock
56  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_CRCLKE, PPxCLKE_Enable );
57 
58  // return
59  return HAL_OK;
60 }
61 
62 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
68 {
69  // reset peripheral and disable peripheral clock
70  HAL_SCU_Peripheral_SetReset2( PPRST2_CRRST );
71  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_CRCLKE, PPxCLKE_Disable );
72 
73  // return
74  return HAL_OK;
75 }
76 
77 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
90 HAL_Status_Type HAL_CRC_SetAddress( uint32_t u32SAdr, uint32_t u32EAdr, uint32_t u32IniD )
91 {
92  SCUCG->PPCLKEN2_b.CRCLKE = 1; // CRC/Checksum Clock Enable
93 
94  CRC->SADR = u32SAdr; // Set start address
95  CRC->EADR = u32EAdr; // Set end address
96  CRC->INIT = u32IniD; // Set initial data for CRC/Checksum
97 
98  return HAL_OK;
99 }
100 
101 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
129 uint32_t HAL_CRC_ConfigAutoMode( uint32_t MDSEL, uint32_t u32POLY, uint32_t u32FirstBit, uint32_t InputDataSize, uint32_t InputDataComplement )
130 {
131  uint32_t imgPRIMASK;
132 
133  if( SystemCoreClock > 20000000uL )
134  {
135  SCUCG->SCDIVR1_b.HDIV = 3; // HCLK should be less than or equal to 20MHz during CRC/Checksum auto mode
136  }
137 
138  CRC->CR = 0
139  | RLTCLR_Init // CRC/Checksum Result Data Register (CRC_RLT) Initialization
140  | MODS_AutoMode // User/Auto Mode Selection
141  | MDSEL // CRC/Checksum Selection
142  | u32POLY // Polynomial Selection (CRC only)
143  | SARINC_Disable // CRC/Checksum Start Address Auto Increment Control (User mode only)
144  | u32FirstBit // First Shifted-in Selection (CRC only)
145  | InputDataSize // Input Data Size Selection
146  | InputDataComplement // Input Data Complement
147  ;
148 
149  imgPRIMASK = __get_PRIMASK(); // backup PRIMASK (current global interrupt configuration)
150  DI(); // disable global interrupt
151  CRCRun();
152  while( ChkCRCFinish() ) {} // Check if CRC/Checksum finishes or not
153  __set_PRIMASK( imgPRIMASK ); // restore PRIMASK
154 
155  SCUCG->PPCLKEN2_b.CRCLKE = 0; // CRC/Checksum Clock Disable
156 
157  if( SystemCoreClock > 20000000uL )
158  {
159  SCUCG->SCDIVR1_b.HDIV = 4; // HCLK should be set with original frequency
160  }
161 
162  // return
163  if( MDSEL == MDSEL_Checksum )
164  {
165  return ( CRC->RLT & 0xffffffff );
166  }
167  else
168  {
169  switch( u32POLY )
170  {
171  case POLYS_CRC8:
172  return ( CRC->RLT & 0xff );
173 
174  case POLYS_CRC16:
175  case POLYS_CRC16_CCITT:
176  return ( CRC->RLT & 0xffff );
177 
178  case POLYS_CRC32:
179  default:
180  return ( CRC->RLT & 0xffffffff );
181  }
182  }
183 }
184 
185 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
217 HAL_Status_Type HAL_CRC_ConfigUserMode( uint32_t MDSEL, uint32_t u32POLY, uint32_t u32AdrInc, uint32_t u32FirstBit, uint32_t InputDataSize, uint32_t InputDataComplement )
218 {
219  CRC->CR = 0
220  | RLTCLR_Init // CRC/Checksum Result Data Register (CRC_RLT) Initialization
221  | MODS_UserMode // User/Auto Mode Selection
222  | MDSEL // CRC/Checksum Selection
223  | u32POLY // Polynomial Selection (CRC only)
224  | u32AdrInc // CRC/Checksum Start Address Auto Increment Control (User mode only)
225  | u32FirstBit // First Shifted-in Selection (CRC only)
226  | InputDataSize // Input Data Size Selection
227  | InputDataComplement // Input Data Complement
228  ;
229  CRCRun();
230 
231  return HAL_OK;
232 }
233 
234 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
244 uint32_t HAL_CRC_UserInput( uint32_t u32Input )
245 {
246  uint32_t u32Result = 0x8a290000uL;
247  uint32_t CRC_EADR;
248 
249  CRC_InData( u32Input );
250  CRC_EADR = CRC->EADR;
251  if( ( !ChkCRCFinish() ) || ( CRC->SADR > CRC_EADR ) ) // "Auto"/"User" Increment of Start Address
252  {
253  CRCStop(); // Stop forcingly on User Increment of Start Address
254  SCUCG->PPCLKEN2_b.CRCLKE = 0; // CRC/Checksum Clock Disable
255  u32Result = ( CRC->RLT & 0xffff );
256  }
257 
258  return u32Result;
259 }
260 
uint32_t HAL_CRC_ConfigAutoMode(uint32_t MDSEL, uint32_t u32POLY, uint32_t u32FirstBit, uint32_t InputDataSize, uint32_t InputDataComplement)
CRC/Checksum Auto Mode Start and Result.
HAL_Status_Type HAL_CRC_ConfigUserMode(uint32_t MDSEL, uint32_t u32POLY, uint32_t u32AdrInc, uint32_t u32FirstBit, uint32_t InputDataSize, uint32_t InputDataComplement)
CRC/Checksum User Mode Start.
HAL_Status_Type HAL_CRC_SetAddress(uint32_t u32SAdr, uint32_t u32EAdr, uint32_t u32IniD)
Set CRC/Checksum Address.
Contains all macro definitions and function prototypes support for crc firmware library on A31L12x.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
HAL_Status_Type
uint32_t HAL_CRC_UserInput(uint32_t u32Input)
CRC/Checksum Input on User Mode.
HAL_Status_Type HAL_CRC_DeInit(void)
DeInitialize CRC peripheral.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
Contains all macro definitions and function prototypes support for scu firmware library on A31L12x.
HAL_Status_Type HAL_CRC_Init(void)
Initialize CRC/Checksum peripheral.