A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31L12x_hal_timer4n.h
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1 /***************************************************************************//****************************************************************************/
34 
35 #ifndef _TIMER4n_H_
36 #define _TIMER4n_H_
37 
38 #include "A31L12x.h"
39 #include "A31L12x_hal_aa_types.h"
40 
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 
45 //******************************************************************************
46 // Constant
47 //******************************************************************************
48 
49 //========== TIMER4n_CR ========================================
50 
51 //---------- TIMER4n Output Force Level En/Disable Definition ----------
52 #define TIMER4n_FRCDIS (0x0uL << TIMER4n_CR_T4nFRCEN_Pos)
53 #define TIMER4n_FRCEN (0x1uL << TIMER4n_CR_T4nFRCEN_Pos)
54 
55 //---------- TIMER4n Force Input Selection Definition ----------
56 #define TIMER4n_FRCS_T40 (0x0uL << TIMER4n_CR_T4nFRCS_Pos)
57 #define TIMER4n_FRCS_T41 (0x1uL << TIMER4n_CR_T4nFRCS_Pos)
58 #define TIMER4n_FRCS_T42 (0x2uL << TIMER4n_CR_T4nFRCS_Pos)
59 #define TIMER4n_FRCS_T43 (0x3uL << TIMER4n_CR_T4nFRCS_Pos)
60 
61 //---------- TIMER4n Counter Sharing En/Disable Definition ----------
62 #define TIMER4n_CNTSHDIS (0x0uL << TIMER4n_CR_CNTSHEN_Pos)
63 #define TIMER4n_CNTSHEN (0x1uL << TIMER4n_CR_CNTSHEN_Pos)
64 
65 //---------- TIMER4n Counter Sharing Selection Definition ----------
66 #define TIMER4n_CNTSH_T40 (0x0uL << TIMER4n_CR_CNTSH_Pos)
67 #define TIMER4n_CNTSH_T41 (0x1uL << TIMER4n_CR_CNTSH_Pos)
68 #define TIMER4n_CNTSH_T42 (0x2uL << TIMER4n_CR_CNTSH_Pos)
69 #define TIMER4n_CNTSH_T43 (0x3uL << TIMER4n_CR_CNTSH_Pos)
70 
71 //---------- TIMER4n Enable/Disable Definition ----------
72 #define TIMER4n_DISABLE (0x0uL << TIMER4n_CR_T4nEN_Pos)
73 #define TIMER4n_ENABLE (0x1uL << TIMER4n_CR_T4nEN_Pos)
74 
75 //---------- TIMER4n Clock Selection Definition ----------
76 #define TIMER4n_CLKINT (0x0uL << TIMER4n_CR_T4nCLK_Pos)
77 #define TIMER4n_CLKEXT (0x1uL << TIMER4n_CR_T4nCLK_Pos)
78 
79 //---------- TIMER4n Mode Selection Definition ----------
80 #define TIMER4n_INVM (0x0uL << TIMER4n_CR_T4nMS_Pos)
81 #define TIMER4n_CAPM (0x1uL << TIMER4n_CR_T4nMS_Pos)
82 #define TIMER4n_BTOB (0x2uL << TIMER4n_CR_T4nMS_Pos)
83 #define TIMER4n_OSINVM (0x3uL << TIMER4n_CR_T4nMS_Pos)
84 
85 //---------- TIMER4n External Clock Edge Selection Definition ----------
86 #define TIMER4n_FEDGE (0x0uL << TIMER4n_CR_T4nECE_Pos)
87 #define TIMER4n_REDGE (0x1uL << TIMER4n_CR_T4nECE_Pos)
88 
89 //---------- TIMER4n Output Pair Selection Definition ----------
90 #define TIMER4n_NO_OPAIR (0x0uL << TIMER4n_CR_T4nOPAIR_Pos)
91 #define TIMER4n_OPAIR (0x1uL << TIMER4n_CR_T4nOPAIR_Pos)
92 
93 //---------- TIMER4n Delay Time Insert En/Disable Definition ----------
94 #define TIMER4n_DLYDIS (0x0uL << TIMER4n_CR_DLYEN_Pos)
95 #define TIMER4n_DLYEN (0x1uL << TIMER4n_CR_DLYEN_Pos)
96 
97 //---------- TIMER4n Delay Timer Insertion Position Definition ----------
98 #define TIMER4n_INSFRONT (0x0uL << TIMER4n_CR_DLYPOS_Pos)
99 #define TIMER4n_INSBACK (0x1uL << TIMER4n_CR_DLYPOS_Pos)
100 
101 //---------- TIMER4n Data Reload Time Selection Definition ----------
102 #define TIMER4n_UPWRITE (0x0uL << TIMER4n_CR_UPDT_Pos)
103 #define TIMER4n_UPMATCH (0x1uL << TIMER4n_CR_UPDT_Pos)
104 #define TIMER4n_UPBOTTOM (0x2uL << TIMER4n_CR_UPDT_Pos)
105 
106 //---------- TIMER4n Input Capture/ˇ±Force levelˇ± Polarity Selection Definition ----------
107 #define TIMER4n_INPOL_FALL (0x0uL << TIMER4n_CR_T4nINPOL_Pos)
108 #define TIMER4n_INPOL_RISE (0x1uL << TIMER4n_CR_T4nINPOL_Pos)
109 #define TIMER4n_INPOL_BOTH (0x2uL << TIMER4n_CR_T4nINPOL_Pos)
110 
111 //========== TIMER4n_OUTCR ========================================
112 
113 //---------- TIMER4n T4nOUTB Output Polarity Selection Definition ----------
114 #define TIMER4n_OUT_POLBLOW (0x0uL << TIMER4n_OUTCR_POLB_Pos)
115 #define TIMER4n_OUT_POLBHIGH (0x1uL << TIMER4n_OUTCR_POLB_Pos)
116 
117 //---------- TIMER4n T4nOUTA Output Polarity Selection Definition ----------
118 #define TIMER4n_OUT_POLALOW (0x0uL << TIMER4n_OUTCR_POLA_Pos)
119 #define TIMER4n_OUT_POLAHIGH (0x1uL << TIMER4n_OUTCR_POLA_Pos)
120 
121 //---------- TIMER4n T4nOUTB Output En/Disable Definition ----------
122 #define TIMER4n_OUT_BOEDIS (0x0uL << TIMER4n_OUTCR_T4nBOE_Pos)
123 #define TIMER4n_OUT_BOEEN (0x1uL << TIMER4n_OUTCR_T4nBOE_Pos)
124 
125 //---------- TIMER4n T4nOUTA Output En/Disable Definition ----------
126 #define TIMER4n_OUT_AOEDIS (0x0uL << TIMER4n_OUTCR_T4nAOE_Pos)
127 #define TIMER4n_OUT_AOEEN (0x1uL << TIMER4n_OUTCR_T4nAOE_Pos)
128 
129 //---------- TIMER4n T4nOUTB Output When Disable ----------
130 #define TIMER4n_OUT_LVLBLOW (0x0uL << TIMER4n_OUTCR_LVLB_Pos)
131 #define TIMER4n_OUT_LVLBHIGH (0x1uL << TIMER4n_OUTCR_LVLB_Pos)
132 
133 //---------- TIMER4n T4nOUTA Output When Disable ----------
134 #define TIMER4n_OUT_LVLALOW (0x0uL << TIMER4n_OUTCR_LVLA_Pos)
135 #define TIMER4n_OUT_LVLAHIGH (0x1uL << TIMER4n_OUTCR_LVLA_Pos)
136 
137 //========== TIMER4n_INTCR ========================================
138 
139 //---------- TIMER4n Output Force Level Interrupt EN/Disable Definition ----------
140 #define TIMER4n_INT_FRCIDIS (0x0uL << TIMER4n_INTCR_T4nFRCIEN_Pos)
141 #define TIMER4n_INT_FRCIEN (0x1uL << TIMER4n_INTCR_T4nFRCIEN_Pos)
142 
143 //---------- TIMER4n Capture Interrupt EN/Disable Definition ----------
144 #define TIMER4n_INT_CIDIS (0x0uL << TIMER4n_INTCR_T4nCIEN_Pos)
145 #define TIMER4n_INT_CIEN (0x1uL << TIMER4n_INTCR_T4nCIEN_Pos)
146 
147 //---------- TIMER4n Bottom Interrupt EN/Disable Definition ----------
148 #define TIMER4n_INT_BTIDIS (0x0uL << TIMER4n_INTCR_T4nBTIEN_Pos)
149 #define TIMER4n_INT_BTIEN (0x1uL << TIMER4n_INTCR_T4nBTIEN_Pos)
150 
151 //---------- TIMER4n Period Match Interrupt EN/Disable Definition ----------
152 #define TIMER4n_INT_PMIDIS (0x0uL << TIMER4n_INTCR_T4nPMIEN_Pos)
153 #define TIMER4n_INT_PMIEN (0x1uL << TIMER4n_INTCR_T4nPMIEN_Pos)
154 
155 //---------- TIMER4n B Match Interrupt EN/Disable Definition ----------
156 #define TIMER4n_INT_BMIDIS (0x0uL << TIMER4n_INTCR_T4nBMIEN_Pos)
157 #define TIMER4n_INT_BMIENUP (0x1uL << TIMER4n_INTCR_T4nBMIEN_Pos)
158 #define TIMER4n_INT_BMIENDOWN (0x2uL << TIMER4n_INTCR_T4nBMIEN_Pos)
159 #define TIMER4n_INT_BMIENBOTH (0x3uL << TIMER4n_INTCR_T4nBMIEN_Pos)
160 
161 //---------- TIMER4n A Match Interrupt EN/Disable Definition ----------
162 #define TIMER4n_INT_AMIDIS (0x0uL << TIMER4n_INTCR_T4nAMIEN_Pos)
163 #define TIMER4n_INT_AMIENUP (0x1uL << TIMER4n_INTCR_T4nAMIEN_Pos)
164 #define TIMER4n_INT_AMIENDOWN (0x2uL << TIMER4n_INTCR_T4nAMIEN_Pos)
165 #define TIMER4n_INT_AMIENBOTH (0x3uL << TIMER4n_INTCR_T4nAMIEN_Pos)
166 
167 //========== TIMER4n_ADTCR ========================================
168 
169 //---------- TIMER4n Bottom for A/DC Trigger Signal Generator EN/Disable Definition ----------
170 #define TIMER4n_ADT_BTTGDIS (0x0uL << TIMER4n_ADTCR_T4nBTTG_Pos)
171 #define TIMER4n_ADT_BTTGEN (0x1uL << TIMER4n_ADTCR_T4nBTTG_Pos)
172 
173 //---------- TIMER4n Period Match for A/DC Trigger Signal Generator EN/Disable Definition ----------
174 #define TIMER4n_ADT_PMTGDIS (0x0uL << TIMER4n_ADTCR_T4nPMTG_Pos)
175 #define TIMER4n_ADT_PMTGEN (0x1uL << TIMER4n_ADTCR_T4nPMTG_Pos)
176 
177 //---------- TIMER4n B-ch Match for A/DC Trigger Signal Generator EN/Disable Definition ----------
178 #define TIMER4n_ADT_BMTGDIS (0x0uL << TIMER4n_ADTCR_T4nBMTG_Pos)
179 #define TIMER4n_ADT_BMTGENUP (0x1uL << TIMER4n_ADTCR_T4nBMTG_Pos)
180 #define TIMER4n_ADT_BMTGENDOWN (0x2uL << TIMER4n_ADTCR_T4nBMTG_Pos)
181 #define TIMER4n_ADT_BMTGENBOTH (0x3uL << TIMER4n_ADTCR_T4nBMTG_Pos)
182 
183 //---------- TIMER4n A-ch Match for A/DC Trigger Signal Generator EN/Disable Definition ----------
184 #define TIMER4n_ADT_AMTGDIS (0x0uL << TIMER4n_ADTCR_T4nAMTG_Pos)
185 #define TIMER4n_ADT_AMTGENUP (0x1uL << TIMER4n_ADTCR_T4nAMTG_Pos)
186 #define TIMER4n_ADT_AMTGENDOWN (0x2uL << TIMER4n_ADTCR_T4nAMTG_Pos)
187 #define TIMER4n_ADT_AMTGENBOTH (0x3uL << TIMER4n_ADTCR_T4nAMTG_Pos)
188 
189 #define TIMER4n_PRS_MASK 0x0FFF
190 
191 //******************************************************************************
192 // Type
193 //******************************************************************************
194 
195 //==============================================================================
196 // Enumeration
197 //==============================================================================
198 
201 typedef enum
202 {
206 
207 typedef enum
208 {
214 
215 typedef enum
216 {
222 
224 typedef enum
225 {
229 
230 typedef enum
231 {
235 
236 typedef enum
237 {
241 
242 typedef enum
243 {
247 
249 typedef enum
250 {
254 
255 //==============================================================================
256 // Structure
257 //==============================================================================
258 
260 typedef struct
261 {
262  uint16_t PDR;
263  uint16_t ADR;
264  uint16_t BDR;
265  uint16_t Prescaler;
266  uint8_t OutBStartLevel;
269  uint8_t OutAStartLevel;
272  uint8_t OutBEnable;
273  uint8_t OutAEnable;
275  uint8_t CkSel;
278  uint8_t ECE;
280 
282 typedef struct
283 {
284  uint16_t PDR;
285  uint16_t Prescaler;
286  uint8_t ClrMode;
287  uint8_t CkSel;
288  uint8_t ECE;
290 
291 //******************************************************************************
292 // Macro
293 //******************************************************************************
294 
295 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
301 #define TIMER4n_EN( TIMER4x ) (TIMER4x->CR_b.T4nEN = 1)
302 #define TIMER4n_DIS( TIMER4x ) (TIMER4x->CR_b.T4nEN = 0)
303 
304 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
310 #define TIMER4n_ConCnt( TIMER4x ) (TIMER4x->CR_b.T4nPAU = 0)
311 #define TIMER4n_TempPau( TIMER4x ) (TIMER4x->CR_b.T4nPAU = 1)
312 
313 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
319 #define TIMER4n_ClrCnt( TIMER4x ) (TIMER4x->CR_b.T4nCLR = 1)
320 
321 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
327 #define TIMER4n_GetCnt( TIMER4x ) (TIMER4x->CNT)
328 
329 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
337 #define TIMER4n_SetPData( TIMER4x, u32PData ) (TIMER4x->PDR = u32PData)
338 
339 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
347 #define TIMER4n_SetAData( TIMER4x, u32AData ) (TIMER4x->ADR = u32AData)
348 
349 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
357 #define TIMER4n_SetBData( TIMER4x, u32BData ) (TIMER4x->BDR = u32BData)
358 
359 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
365 #define TIMER4n_GetCapData( TIMER4x ) (TIMER4x->CAPDR)
366 
367 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
375 #define TIMER4n_SetPresData( TIMER4x, u32PresData ) (TIMER4x->PREDR = u32PresData)
376 
377 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
385 #define TIMER4n_SetDelayData( TIMER4x, u32DelayData ) (TIMER4x->DLY = u32DelayData)
386 
387 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
393 #define T4nFRCInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nFRCIFLAG)
394 
395 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
401 #define T4nFRCInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nFRCIFLAG = 1)
402 
403 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
409 #define T4nCapInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nCIFLAG)
410 
411 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
417 #define T4nCapInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nCIFLAG = 1)
418 
419 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
425 #define T4nBTInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBTIFLAG)
426 
427 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
433 #define T4nBTInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBTIFLAG = 1)
434 
435 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
441 #define T4nPMInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nPMIFLAG)
442 
443 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
449 #define T4nPMInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nPMIFLAG = 1)
450 
451 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
457 #define T4nBMInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBMIFLAG)
458 
459 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
465 #define T4nBMInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBMIFLAG = 1)
466 
467 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
473 #define T4nAMInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nAMIFLAG)
474 
475 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
481 #define T4nAMInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nAMIFLAG = 1)
482 
483 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
486 
487 #define TIMER4n_CR_CKSEL_MASK (TIMER4n_CR_T4nCLK_Msk)
488 #define TIMER4n_CR_CKSEL_SET( n ) (n << TIMER4n_CR_T4nCLK_Pos)
489 
490 #define TIMER4n_CR_MODE_MASK (TIMER4n_CR_T4nMS_Msk)
491 #define TIMER4n_CR_MODE_SET( n ) (n << TIMER4n_CR_T4nMS_Pos)
492 
493 #define TIMER4n_CR_INPOL_MASK (TIMER4n_CR_T4nINPOL_Msk)
494 #define TIMER4n_CR_INPOL_SET( n ) (n << TIMER4n_CR_T4nINPOL_Pos)
495 
496 #define TIMER4n_CR_ECE_MASK (TIMER4n_CR_T4nECE_Msk)
497 #define TIMER4n_CR_ECE_SET( n ) (n << TIMER4n_CR_T4nECE_Pos)
498 
499 #define TIMER4n_OUTCR_POLB_MASK (TIMER4n_OUTCR_POLB_Msk)
500 #define TIMER4n_OUTCR_POLB_SET( n ) (n << TIMER4n_OUTCR_POLB_Pos)
501 
502 #define TIMER4n_OUTCR_POLA_MASK (TIMER4n_OUTCR_POLA_Msk)
503 #define TIMER4n_OUTCR_POLA_SET( n ) (n << TIMER4n_OUTCR_POLA_Pos)
504 
505 #define TIMER4n_OUTCR_BOE_MASK (TIMER4n_OUTCR_T4nBOE_Msk)
506 #define TIMER4n_OUTCR_BOE_SET( n ) (n << TIMER4n_OUTCR_T4nBOE_Pos)
507 
508 #define TIMER4n_OUTCR_AOE_MASK (TIMER4n_OUTCR_T4nAOE_Msk)
509 #define TIMER4n_OUTCR_AOE_SET( n ) (n << TIMER4n_OUTCR_T4nAOE_Pos)
510 
511 #define TIMER4n_OUTCR_LVLB_MASK (TIMER4n_OUTCR_LVLB_Msk)
512 #define TIMER4n_OUTCR_LVLB_SET( n ) (n << TIMER4n_OUTCR_LVLB_Pos)
513 
514 #define TIMER4n_OUTCR_LVLA_MASK (TIMER4n_OUTCR_LVLA_Msk)
515 #define TIMER4n_OUTCR_LVLA_SET( n ) (n << TIMER4n_OUTCR_LVLA_Pos)
516 
517 //******************************************************************************
518 // Function
519 //******************************************************************************
520 
521 HAL_Status_Type HAL_TIMER4n_Init( TIMER4n_Type* TIMER4x, TIMER4n_MODE_OPT TimerCounterMode, void* TIMER4n_Config );
522 HAL_Status_Type HAL_TIMER4n_DeInit( TIMER4n_Type* TIMER4x );
523 
524 HAL_Status_Type HAL_TIMER4n_ConfigInterrupt( TIMER4n_Type* TIMER4x, TIMER4n_INT_Type TIMER4n_IntCfg, FunctionalState NewState );
525 HAL_Status_Type HAL_TIMER4n_Cmd( TIMER4n_Type* TIMER4x, FunctionalState NewState );
526 HAL_Status_Type HAL_TIMER4n_SetRegister( TIMER4n_Type* TIMER4x, uint32_t u32T4nSet, uint32_t u32T4nClk );
527 
528 #ifdef __cplusplus
529 }
530 #endif
531 
532 #endif /* _TIMER4n_H_ */
533 
Contains the ABOV typedefs for C standard types. It is intended to be used in ISO C conforming develo...
TIMER4n_OUTA_ENABLE_OPT
struct TIMER4n_PERIODICCFG_Type TIMER4n_ONESHOTCFG_Type
HAL_Status_Type
HAL_Status_Type HAL_TIMER4n_Init(TIMER4n_Type *TIMER4x, TIMER4n_MODE_OPT TimerCounterMode, void *TIMER4n_Config)
Initialize the TIMER4n peripheral with the specified parameters.
TIMER4n_MODE_OPT
HAL_Status_Type HAL_TIMER4n_DeInit(TIMER4n_Type *TIMER4x)
Close Timer/Counter device.
TIMER4n_OUTA_STARTLVL_OPT
TIMER4n_CLR_MODE_OPT
HAL_Status_Type HAL_TIMER4n_Cmd(TIMER4n_Type *TIMER4x, FunctionalState NewState)
Start/Stop Timer/Counter device.
TIMER4n_OUTB_ENABLE_OPT
TIMER4n_CKSEL_MODE_OPT
TIMER4n_INT_Type
FunctionalState
HAL_Status_Type HAL_TIMER4n_SetRegister(TIMER4n_Type *TIMER4x, uint32_t u32T4nSet, uint32_t u32T4nClk)
Set TIMER4n CR/PREDR Registers.
HAL_Status_Type HAL_TIMER4n_ConfigInterrupt(TIMER4n_Type *TIMER4x, TIMER4n_INT_Type TIMER4n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
TIMER4n_OUTB_STARTLVL_OPT