52 #define TIMER4n_FRCDIS (0x0uL << TIMER4n_CR_T4nFRCEN_Pos) 53 #define TIMER4n_FRCEN (0x1uL << TIMER4n_CR_T4nFRCEN_Pos) 56 #define TIMER4n_FRCS_T40 (0x0uL << TIMER4n_CR_T4nFRCS_Pos) 57 #define TIMER4n_FRCS_T41 (0x1uL << TIMER4n_CR_T4nFRCS_Pos) 58 #define TIMER4n_FRCS_T42 (0x2uL << TIMER4n_CR_T4nFRCS_Pos) 59 #define TIMER4n_FRCS_T43 (0x3uL << TIMER4n_CR_T4nFRCS_Pos) 62 #define TIMER4n_CNTSHDIS (0x0uL << TIMER4n_CR_CNTSHEN_Pos) 63 #define TIMER4n_CNTSHEN (0x1uL << TIMER4n_CR_CNTSHEN_Pos) 66 #define TIMER4n_CNTSH_T40 (0x0uL << TIMER4n_CR_CNTSH_Pos) 67 #define TIMER4n_CNTSH_T41 (0x1uL << TIMER4n_CR_CNTSH_Pos) 68 #define TIMER4n_CNTSH_T42 (0x2uL << TIMER4n_CR_CNTSH_Pos) 69 #define TIMER4n_CNTSH_T43 (0x3uL << TIMER4n_CR_CNTSH_Pos) 72 #define TIMER4n_DISABLE (0x0uL << TIMER4n_CR_T4nEN_Pos) 73 #define TIMER4n_ENABLE (0x1uL << TIMER4n_CR_T4nEN_Pos) 76 #define TIMER4n_CLKINT (0x0uL << TIMER4n_CR_T4nCLK_Pos) 77 #define TIMER4n_CLKEXT (0x1uL << TIMER4n_CR_T4nCLK_Pos) 80 #define TIMER4n_INVM (0x0uL << TIMER4n_CR_T4nMS_Pos) 81 #define TIMER4n_CAPM (0x1uL << TIMER4n_CR_T4nMS_Pos) 82 #define TIMER4n_BTOB (0x2uL << TIMER4n_CR_T4nMS_Pos) 83 #define TIMER4n_OSINVM (0x3uL << TIMER4n_CR_T4nMS_Pos) 86 #define TIMER4n_FEDGE (0x0uL << TIMER4n_CR_T4nECE_Pos) 87 #define TIMER4n_REDGE (0x1uL << TIMER4n_CR_T4nECE_Pos) 90 #define TIMER4n_NO_OPAIR (0x0uL << TIMER4n_CR_T4nOPAIR_Pos) 91 #define TIMER4n_OPAIR (0x1uL << TIMER4n_CR_T4nOPAIR_Pos) 94 #define TIMER4n_DLYDIS (0x0uL << TIMER4n_CR_DLYEN_Pos) 95 #define TIMER4n_DLYEN (0x1uL << TIMER4n_CR_DLYEN_Pos) 98 #define TIMER4n_INSFRONT (0x0uL << TIMER4n_CR_DLYPOS_Pos) 99 #define TIMER4n_INSBACK (0x1uL << TIMER4n_CR_DLYPOS_Pos) 102 #define TIMER4n_UPWRITE (0x0uL << TIMER4n_CR_UPDT_Pos) 103 #define TIMER4n_UPMATCH (0x1uL << TIMER4n_CR_UPDT_Pos) 104 #define TIMER4n_UPBOTTOM (0x2uL << TIMER4n_CR_UPDT_Pos) 107 #define TIMER4n_INPOL_FALL (0x0uL << TIMER4n_CR_T4nINPOL_Pos) 108 #define TIMER4n_INPOL_RISE (0x1uL << TIMER4n_CR_T4nINPOL_Pos) 109 #define TIMER4n_INPOL_BOTH (0x2uL << TIMER4n_CR_T4nINPOL_Pos) 114 #define TIMER4n_OUT_POLBLOW (0x0uL << TIMER4n_OUTCR_POLB_Pos) 115 #define TIMER4n_OUT_POLBHIGH (0x1uL << TIMER4n_OUTCR_POLB_Pos) 118 #define TIMER4n_OUT_POLALOW (0x0uL << TIMER4n_OUTCR_POLA_Pos) 119 #define TIMER4n_OUT_POLAHIGH (0x1uL << TIMER4n_OUTCR_POLA_Pos) 122 #define TIMER4n_OUT_BOEDIS (0x0uL << TIMER4n_OUTCR_T4nBOE_Pos) 123 #define TIMER4n_OUT_BOEEN (0x1uL << TIMER4n_OUTCR_T4nBOE_Pos) 126 #define TIMER4n_OUT_AOEDIS (0x0uL << TIMER4n_OUTCR_T4nAOE_Pos) 127 #define TIMER4n_OUT_AOEEN (0x1uL << TIMER4n_OUTCR_T4nAOE_Pos) 130 #define TIMER4n_OUT_LVLBLOW (0x0uL << TIMER4n_OUTCR_LVLB_Pos) 131 #define TIMER4n_OUT_LVLBHIGH (0x1uL << TIMER4n_OUTCR_LVLB_Pos) 134 #define TIMER4n_OUT_LVLALOW (0x0uL << TIMER4n_OUTCR_LVLA_Pos) 135 #define TIMER4n_OUT_LVLAHIGH (0x1uL << TIMER4n_OUTCR_LVLA_Pos) 140 #define TIMER4n_INT_FRCIDIS (0x0uL << TIMER4n_INTCR_T4nFRCIEN_Pos) 141 #define TIMER4n_INT_FRCIEN (0x1uL << TIMER4n_INTCR_T4nFRCIEN_Pos) 144 #define TIMER4n_INT_CIDIS (0x0uL << TIMER4n_INTCR_T4nCIEN_Pos) 145 #define TIMER4n_INT_CIEN (0x1uL << TIMER4n_INTCR_T4nCIEN_Pos) 148 #define TIMER4n_INT_BTIDIS (0x0uL << TIMER4n_INTCR_T4nBTIEN_Pos) 149 #define TIMER4n_INT_BTIEN (0x1uL << TIMER4n_INTCR_T4nBTIEN_Pos) 152 #define TIMER4n_INT_PMIDIS (0x0uL << TIMER4n_INTCR_T4nPMIEN_Pos) 153 #define TIMER4n_INT_PMIEN (0x1uL << TIMER4n_INTCR_T4nPMIEN_Pos) 156 #define TIMER4n_INT_BMIDIS (0x0uL << TIMER4n_INTCR_T4nBMIEN_Pos) 157 #define TIMER4n_INT_BMIENUP (0x1uL << TIMER4n_INTCR_T4nBMIEN_Pos) 158 #define TIMER4n_INT_BMIENDOWN (0x2uL << TIMER4n_INTCR_T4nBMIEN_Pos) 159 #define TIMER4n_INT_BMIENBOTH (0x3uL << TIMER4n_INTCR_T4nBMIEN_Pos) 162 #define TIMER4n_INT_AMIDIS (0x0uL << TIMER4n_INTCR_T4nAMIEN_Pos) 163 #define TIMER4n_INT_AMIENUP (0x1uL << TIMER4n_INTCR_T4nAMIEN_Pos) 164 #define TIMER4n_INT_AMIENDOWN (0x2uL << TIMER4n_INTCR_T4nAMIEN_Pos) 165 #define TIMER4n_INT_AMIENBOTH (0x3uL << TIMER4n_INTCR_T4nAMIEN_Pos) 170 #define TIMER4n_ADT_BTTGDIS (0x0uL << TIMER4n_ADTCR_T4nBTTG_Pos) 171 #define TIMER4n_ADT_BTTGEN (0x1uL << TIMER4n_ADTCR_T4nBTTG_Pos) 174 #define TIMER4n_ADT_PMTGDIS (0x0uL << TIMER4n_ADTCR_T4nPMTG_Pos) 175 #define TIMER4n_ADT_PMTGEN (0x1uL << TIMER4n_ADTCR_T4nPMTG_Pos) 178 #define TIMER4n_ADT_BMTGDIS (0x0uL << TIMER4n_ADTCR_T4nBMTG_Pos) 179 #define TIMER4n_ADT_BMTGENUP (0x1uL << TIMER4n_ADTCR_T4nBMTG_Pos) 180 #define TIMER4n_ADT_BMTGENDOWN (0x2uL << TIMER4n_ADTCR_T4nBMTG_Pos) 181 #define TIMER4n_ADT_BMTGENBOTH (0x3uL << TIMER4n_ADTCR_T4nBMTG_Pos) 184 #define TIMER4n_ADT_AMTGDIS (0x0uL << TIMER4n_ADTCR_T4nAMTG_Pos) 185 #define TIMER4n_ADT_AMTGENUP (0x1uL << TIMER4n_ADTCR_T4nAMTG_Pos) 186 #define TIMER4n_ADT_AMTGENDOWN (0x2uL << TIMER4n_ADTCR_T4nAMTG_Pos) 187 #define TIMER4n_ADT_AMTGENBOTH (0x3uL << TIMER4n_ADTCR_T4nAMTG_Pos) 189 #define TIMER4n_PRS_MASK 0x0FFF 301 #define TIMER4n_EN( TIMER4x ) (TIMER4x->CR_b.T4nEN = 1) 302 #define TIMER4n_DIS( TIMER4x ) (TIMER4x->CR_b.T4nEN = 0) 310 #define TIMER4n_ConCnt( TIMER4x ) (TIMER4x->CR_b.T4nPAU = 0) 311 #define TIMER4n_TempPau( TIMER4x ) (TIMER4x->CR_b.T4nPAU = 1) 319 #define TIMER4n_ClrCnt( TIMER4x ) (TIMER4x->CR_b.T4nCLR = 1) 327 #define TIMER4n_GetCnt( TIMER4x ) (TIMER4x->CNT) 337 #define TIMER4n_SetPData( TIMER4x, u32PData ) (TIMER4x->PDR = u32PData) 347 #define TIMER4n_SetAData( TIMER4x, u32AData ) (TIMER4x->ADR = u32AData) 357 #define TIMER4n_SetBData( TIMER4x, u32BData ) (TIMER4x->BDR = u32BData) 365 #define TIMER4n_GetCapData( TIMER4x ) (TIMER4x->CAPDR) 375 #define TIMER4n_SetPresData( TIMER4x, u32PresData ) (TIMER4x->PREDR = u32PresData) 385 #define TIMER4n_SetDelayData( TIMER4x, u32DelayData ) (TIMER4x->DLY = u32DelayData) 393 #define T4nFRCInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nFRCIFLAG) 401 #define T4nFRCInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nFRCIFLAG = 1) 409 #define T4nCapInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nCIFLAG) 417 #define T4nCapInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nCIFLAG = 1) 425 #define T4nBTInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBTIFLAG) 433 #define T4nBTInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBTIFLAG = 1) 441 #define T4nPMInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nPMIFLAG) 449 #define T4nPMInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nPMIFLAG = 1) 457 #define T4nBMInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBMIFLAG) 465 #define T4nBMInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nBMIFLAG = 1) 473 #define T4nAMInt_GetFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nAMIFLAG) 481 #define T4nAMInt_ClrFg( TIMER4x ) (TIMER4x->INTFLAG_b.T4nAMIFLAG = 1) 487 #define TIMER4n_CR_CKSEL_MASK (TIMER4n_CR_T4nCLK_Msk) 488 #define TIMER4n_CR_CKSEL_SET( n ) (n << TIMER4n_CR_T4nCLK_Pos) 490 #define TIMER4n_CR_MODE_MASK (TIMER4n_CR_T4nMS_Msk) 491 #define TIMER4n_CR_MODE_SET( n ) (n << TIMER4n_CR_T4nMS_Pos) 493 #define TIMER4n_CR_INPOL_MASK (TIMER4n_CR_T4nINPOL_Msk) 494 #define TIMER4n_CR_INPOL_SET( n ) (n << TIMER4n_CR_T4nINPOL_Pos) 496 #define TIMER4n_CR_ECE_MASK (TIMER4n_CR_T4nECE_Msk) 497 #define TIMER4n_CR_ECE_SET( n ) (n << TIMER4n_CR_T4nECE_Pos) 499 #define TIMER4n_OUTCR_POLB_MASK (TIMER4n_OUTCR_POLB_Msk) 500 #define TIMER4n_OUTCR_POLB_SET( n ) (n << TIMER4n_OUTCR_POLB_Pos) 502 #define TIMER4n_OUTCR_POLA_MASK (TIMER4n_OUTCR_POLA_Msk) 503 #define TIMER4n_OUTCR_POLA_SET( n ) (n << TIMER4n_OUTCR_POLA_Pos) 505 #define TIMER4n_OUTCR_BOE_MASK (TIMER4n_OUTCR_T4nBOE_Msk) 506 #define TIMER4n_OUTCR_BOE_SET( n ) (n << TIMER4n_OUTCR_T4nBOE_Pos) 508 #define TIMER4n_OUTCR_AOE_MASK (TIMER4n_OUTCR_T4nAOE_Msk) 509 #define TIMER4n_OUTCR_AOE_SET( n ) (n << TIMER4n_OUTCR_T4nAOE_Pos) 511 #define TIMER4n_OUTCR_LVLB_MASK (TIMER4n_OUTCR_LVLB_Msk) 512 #define TIMER4n_OUTCR_LVLB_SET( n ) (n << TIMER4n_OUTCR_LVLB_Pos) 514 #define TIMER4n_OUTCR_LVLA_MASK (TIMER4n_OUTCR_LVLA_Msk) 515 #define TIMER4n_OUTCR_LVLA_SET( n ) (n << TIMER4n_OUTCR_LVLA_Pos)
Contains the ABOV typedefs for C standard types. It is intended to be used in ISO C conforming develo...
struct TIMER4n_PERIODICCFG_Type TIMER4n_ONESHOTCFG_Type
HAL_Status_Type HAL_TIMER4n_Init(TIMER4n_Type *TIMER4x, TIMER4n_MODE_OPT TimerCounterMode, void *TIMER4n_Config)
Initialize the TIMER4n peripheral with the specified parameters.
HAL_Status_Type HAL_TIMER4n_DeInit(TIMER4n_Type *TIMER4x)
Close Timer/Counter device.
TIMER4n_OUTA_STARTLVL_OPT
HAL_Status_Type HAL_TIMER4n_Cmd(TIMER4n_Type *TIMER4x, FunctionalState NewState)
Start/Stop Timer/Counter device.
HAL_Status_Type HAL_TIMER4n_SetRegister(TIMER4n_Type *TIMER4x, uint32_t u32T4nSet, uint32_t u32T4nClk)
Set TIMER4n CR/PREDR Registers.
HAL_Status_Type HAL_TIMER4n_ConfigInterrupt(TIMER4n_Type *TIMER4x, TIMER4n_INT_Type TIMER4n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
TIMER4n_OUTB_STARTLVL_OPT