A31L12x F/W Packages  1.4.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31L12x_hal_lpuart.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31L12x_hal_lpuart.h"
41 #include "A31L12x_hal_scu.h"
42 
43 /* Public Functions --------------------------------------------------------- */
44 //******************************************************************************
45 // Function
46 //******************************************************************************
47 
48 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
54 static void lpuart_set_divisors( LPUART_CFG_Type* LPUART_Config )
55 {
56  uint32_t numerator;
57  uint32_t denominator;
58  uint32_t n;
59  uint32_t bdr;
60 
61  switch( LPUART_Config->OverSampling )
62  {
63  case LPUART_OVRS_16:
64  n = 16;
65  break;
66  case LPUART_OVRS_8:
67  n = 8;
68  break;
69  case LPUART_OVRS_1:
70  n = 1;
71  break;
72  }
73 
74  //--------------------------------------
75  // numerator & denominator
76  //
77  // bdr = LPUART_BaseClock / n / baudrate - 1
78  //--------------------------------------
79  numerator = LPUART_Config->BaseClock;
80  denominator = LPUART_Config->Baudrate;
81 
82  bdr = numerator / n / denominator - 1;
83 
84  LPUART->BDR = ( uint16_t )( bdr & 0xffff );
85 }
86 
87 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
95 {
96  /* Check LPUART_Config */
97  if( LPUART_Config == NULL )
98  {
99  return HAL_ERROR;
100  }
101 
102  // enable peripheral clock and reset peripheral
103  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_LPUTCLKE, PPxCLKE_Enable );
104  HAL_SCU_Peripheral_SetReset2( PPRST2_LPUTRST );
105 
106  lpuart_set_divisors( LPUART_Config );
107 
108  LPUART->CR1 = 0
109  | ( LPUART_Config->OverSampling << LPUART_CR1_OVRS_Pos )
110  | ( LPUART_Config->DataBit << LPUART_CR1_DLEN_Pos )
111  | ( LPUART_Config->ParityBit << LPUART_CR1_PSEL_Pos )
112  | ( LPUART_Config->StopBit << LPUART_CR1_STOPB_Pos )
113  | ( 1 << LPUART_CR1_TXE_Pos )
114  | ( 1 << LPUART_CR1_RXE_Pos )
115  ;
116 
117  // dummy read
120 
121  return HAL_OK;
122 }
123 
124 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
130 {
131  // reset peripheral and disable peripheral clock
132  HAL_SCU_Peripheral_SetReset2( PPRST2_LPUTRST );
133  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_LPUTCLKE, PPxCLKE_Disable );
134 
135  return HAL_OK;
136 }
137 
138 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
149 {
150  /* Check LPUART_Config */
151  if( LPUART_Config == NULL )
152  {
153  return HAL_ERROR;
154  }
155 
156  LPUART_Config->BaseClock = SystemPeriClock;
157  LPUART_Config->Baudrate = 38400;
158 
159  LPUART_Config->OverSampling = LPUART_OVRS_16;
160 
161  LPUART_Config->DataBit = LPUART_DATA_BIT_8;
162  LPUART_Config->ParityBit = LPUART_PARITY_BIT_NONE;
163  LPUART_Config->StopBit = LPUART_STOP_BIT_1;
164 
165  return HAL_OK;
166 }
167 
168 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
183 {
184  uint32_t mask;
185 
186  // get mask
187  switch( LPUART_IntCfg )
188  {
190  mask = LPUART_IER_RXCIEN_Msk;
191  break;
193  mask = LPUART_IER_TXCIEN_Msk;
194  break;
196  mask = LPUART_IER_SBDIEN_Msk;
197  break;
199  mask = LPUART_IER_RTOIEN_Msk;
200  break;
202  mask = LPUART_IER_RCDIEN_Msk;
203  break;
204 
205  default:
206  return HAL_ERROR;
207  }
208 
209  // enable/disable
210  if( NewState == ENABLE )
211  {
212  LPUART->IER |= mask;
213  }
214  else
215  {
216  LPUART->IER &= ~mask;
217  }
218 
219  return HAL_OK;
220 }
221 
222 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
245 {
246  uint32_t mask;
247 
248  // CR1
249  if( Mode <= LPUART_CONTROL_LPUEN )
250  {
251  // get mask
252  switch( Mode )
253  {
254  case LPUART_CONTROL_PEN:
255  mask = LPUART_CR1_PEN_Msk;
256  break;
258  mask = LPUART_CR1_STKPEN_Msk;
259  break;
260  case LPUART_CONTROL_PSEL:
261  mask = LPUART_CR1_PSEL_Msk;
262  break;
264  mask = LPUART_CR1_STOPB_Msk;
265  break;
267  mask = LPUART_CR1_HDCOM_Msk;
268  break;
269  case LPUART_CONTROL_TXE:
270  mask = LPUART_CR1_TXE_Msk;
271  break;
272  case LPUART_CONTROL_RXE:
273  mask = LPUART_CR1_RXE_Msk;
274  break;
276  mask = LPUART_CR1_WAKEN_Msk;
277  break;
279  mask = LPUART_CR1_LPUEN_Msk;
280  break;
281 
282  default:
283  return HAL_ERROR;
284  }
285 
286  // enable/disable
287  if( NewState == ENABLE )
288  {
289  LPUART->CR1 |= mask;
290  }
291  else
292  {
293  LPUART->CR1 &= ~mask;
294  }
295  }
296 
297  // CR2
298  if( Mode >= LPUART_CONTROL_DEPOL )
299  {
300  // get mask
301  switch( Mode )
302  {
304  mask = LPUART_CR2_DEPOL_Msk;
305  break;
307  mask = LPUART_CR2_DEPEN_Msk;
308  break;
310  mask = LPUART_CR2_RCDEN_Msk;
311  break;
313  mask = LPUART_CR2_RTOEN_Msk;
314  break;
315 
316  default:
317  return HAL_ERROR;
318  }
319 
320  // enable/disable
321  if( NewState == ENABLE )
322  {
323  LPUART->CR2 |= mask;
324  }
325  else
326  {
327  LPUART->CR2 &= ~mask;
328  }
329  }
330 
331  return HAL_OK;
332 }
333 
334 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
341 {
342  LPUART->CR1_b.LPUEN = state;
343 
344  return HAL_OK;
345 }
346 
347 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
362 {
363  uint32_t reg;
364 
365  reg = LPUART->IFSR;
366 
367  switch( Status )
368  {
370  reg |= LPUART_IFSR_RXCIFLAG_Msk;
371  break;
373  reg |= LPUART_IFSR_TXCIFLAG_Msk;
374  break;
376  reg |= LPUART_IFSR_SBDIFLAG_Msk;
377  break;
379  reg |= LPUART_IFSR_RTOIFLAG_Msk;
380  break;
382  reg |= LPUART_IFSR_RCDIFLAG_Msk;
383  break;
385  reg |= LPUART_IFSR_RXBUSY_Msk;
386  break;
387  case LPUART_STATUS_PE:
388  reg |= LPUART_IFSR_PE_Msk;
389  break;
390  case LPUART_STATUS_FE:
391  reg |= LPUART_IFSR_FE_Msk;
392  break;
393  case LPUART_STATUS_DOR:
394  reg |= LPUART_IFSR_DOR_Msk;
395  break;
396  default:
397  return HAL_ERROR;
398  }
399 
400  LPUART->IFSR = reg;
401 
402  return HAL_OK;
403 }
404 
405 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
409 uint8_t HAL_LPUART_GetStatus( void )
410 {
411  return LPUART->IFSR;
412 }
413 
414 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
421 {
422  LPUART->TDR = Data;
423 
424  return HAL_OK;
425 }
426 
427 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
431 uint8_t HAL_LPUART_ReceiveByte( void )
432 {
433  return LPUART->RDR;
434 }
435 
436 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
450 uint32_t HAL_LPUART_Transmit( uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
451 {
452  uint32_t bToSend, bSent, timeOut;
453  uint8_t* pChar = txbuf;
454 
455  // init counter
456  bToSend = buflen;
457  bSent = 0;
458 
459  // Blocking Mode
460  if( flag == BLOCKING )
461  {
462  while( bToSend )
463  {
464  // send byte
465  HAL_LPUART_TransmitByte( *pChar++ );
466 
467  // wait until tx data register is empty with timeout
468  timeOut = LPUART_BLOCKING_TIMEOUT;
469  while( !( LPUART->IFSR & LPUART_IFSR_TXCIFLAG_Msk ) )
470  {
471  if( timeOut == 0 )
472  {
473  break;
474  }
475  timeOut--;
476  }
477 
478  // if timeout
479  if( timeOut == 0 )
480  {
481  break;
482  }
483 
484  // clear flag
486 
487  // update counter
488  bToSend--;
489  bSent++;
490  }
491  }
492 
493  // Non-Blocking Mode
494  else
495  {
496  while( bToSend )
497  {
498  // if tx data register is not empty
499  if( !( LPUART->IFSR & LPUART_IFSR_TXCIFLAG_Msk ) )
500  {
501  break;
502  }
503 
504  // send byte
505  HAL_LPUART_TransmitByte( *pChar++ );
506 
507  // update counter
508  bToSend--;
509  bSent++;
510  }
511  }
512 
513  // return
514  return bSent;
515 }
516 
517 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
531 uint32_t HAL_LPUART_Receive( uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
532 {
533  uint32_t bToRecv, bRecv, timeOut;
534  uint8_t* pChar = rxbuf;
535 
536  // init counter
537  bToRecv = buflen;
538  bRecv = 0;
539 
540  // Blocking Mode
541  if( flag == BLOCKING )
542  {
543  while( bToRecv )
544  {
545  // wait until data are received with timeout
546  timeOut = LPUART_BLOCKING_TIMEOUT;
547  while( !( LPUART->IFSR & LPUART_IFSR_RXCIFLAG_Msk ) )
548  {
549  if( timeOut == 0 )
550  {
551  break;
552  }
553  timeOut--;
554  }
555 
556  // if timeout
557  if( timeOut == 0 )
558  {
559  break;
560  }
561 
562  // receive byte
563  ( *pChar++ ) = HAL_LPUART_ReceiveByte();
564 
565  // update counter
566  bToRecv--;
567  bRecv++;
568  }
569  }
570 
571  // Non-Blocking Mode
572  else
573  {
574  while( bToRecv )
575  {
576  // if no data were received
577  if( !( LPUART->IFSR & LPUART_IFSR_RXCIFLAG_Msk ) )
578  {
579  break;
580  }
581 
582  // receive byte
583  ( *pChar++ ) = HAL_LPUART_ReceiveByte();
584 
585  // update counter
586  bRecv++;
587  bToRecv--;
588  }
589  }
590 
591  // return
592  return bRecv;
593 }
594 
LPUART_OVER_SAMPLING_Type OverSampling
uint8_t HAL_LPUART_ReceiveByte(void)
Receive a single data from USART peripheral.
HAL_Status_Type HAL_LPUART_ConfigInterrupt(LPUART_INT_Type LPUART_IntCfg, FunctionalState NewState)
Configure the interrupt source of selected LPUART peripheral.
HAL_Status_Type HAL_LPUART_DeInit(void)
Deinitialize the LPUART peripheral registers to their default reset values.
LPUART_STATUS_Type
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_LPUART_Init(LPUART_CFG_Type *LPUART_Config)
Initialize the LPUART peripheral with the specified parameters.
HAL_Status_Type HAL_LPUART_DataControlConfig(LPUART_CONTROL_Type Mode, FunctionalState NewState)
Configure Data Control mode for LPUART peripheral.
HAL_Status_Type
HAL_Status_Type HAL_LPUART_Enable(FunctionalState state)
LPUART enable control.
HAL_Status_Type HAL_LPUART_ClearStatus(LPUART_STATUS_Type Status)
This function clears Interrupt Flag and Status Register.
LPUART_INT_Type
uint32_t HAL_LPUART_Receive(uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Receive a block of data via LPUART peripheral.
uint32_t HAL_LPUART_Transmit(uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Send a block of data via LPUART peripheral.
Contains all macro definitions and function prototypes support for lpuart firmware library on A31L12x...
LPUART_STOP_BIT_Type StopBit
FunctionalState
TRANSFER_BLOCK_Type
LPUART_PARITY_BIT_Type ParityBit
HAL_Status_Type HAL_LPUART_ConfigStructInit(LPUART_CFG_Type *LPUART_Config)
Fills each LPUART_Config member with its default value:
uint8_t HAL_LPUART_GetStatus(void)
This function returns the current value of Interrupt Flag and Status Register.
static void lpuart_set_divisors(LPUART_CFG_Type *LPUART_Config)
Determines best dividers to get a target clock rate.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
LPUART_DATA_BIT_Type DataBit
Contains all macro definitions and function prototypes support for scu firmware library on A31L12x.
HAL_Status_Type HAL_LPUART_TransmitByte(uint8_t Data)
Transmit a single data through USART peripheral.
LPUART_CONTROL_Type