A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G11x_hal_crc.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31G11x_hal_crc.h"
41 #include "A31G11x_hal_scu.h"
42 
43 /* Public Functions --------------------------------------------------------- */
44 //******************************************************************************
45 // Function
46 //******************************************************************************
47 
48 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
54 {
55  // enable peripheral clock
56  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_CRCLKE, PPxCLKE_Enable );
57 
58  // return
59  return HAL_OK;
60 }
61 
62 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
68 {
69  // reset peripheral and disable peripheral clock
70  HAL_SCU_Peripheral_SetReset2( PPRST2_CRRST );
71  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_CRCLKE, PPxCLKE_Disable );
72 
73  // return
74  return HAL_OK;
75 }
76 
77 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
90 HAL_Status_Type HAL_CRC_SetAddress( uint32_t u32SAdr, uint32_t u32EAdr, uint32_t u32IniD )
91 {
92  SCUCG->PPCLKEN2_b.CRCLKE = 1; // CRC/Checksum Clock Enable
93 
94  CRC->SADR = u32SAdr; // Set start address
95  CRC->EADR = u32EAdr; // Set end address
96  CRC->INIT = u32IniD; // Set initial data for CRC/Checksum
97 
98  return HAL_OK;
99 }
100 
101 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
118 uint32_t HAL_CRC_ConfigAutoMode( uint32_t u32SEL, uint32_t u32POLY, uint32_t u32FirstBit )
119 {
120  uint32_t imgPRIMASK;
121 
122  if( SystemCoreClock > 20000000uL )
123  {
124  SCUCG->SCDIVR1_b.HDIV = 3; // HCLK should be less than or equal to 20MHz during CRC/Checksum auto mode
125  }
126 
127  CRC->CR = 0
128  | ( 0x1uL << CRC_CR_RLTCLR_Pos ) // CRC/Checksum Result Data Register (CRC_RLT) Initialization
129  | MODS_AutoMode // User/Auto Mode Selection
130  | u32SEL // CRC/Checksum Selection
131  | u32POLY // Polynomial Selection (CRC only)
132  | CRC_NOINC // CRC/Checksum Start Address Auto Increment Control (User mode only)
133  | u32FirstBit; // First Shifted-in Selection (CRC only)
134 
135  imgPRIMASK = __get_PRIMASK(); // backup PRIMASK (current global interrupt configuration)
136  DI(); // disable global interrupt
137  CRCRun();
138  while( ChkCRCFinish() ) {} // Check if CRC/Checksum finishes or not
139  __set_PRIMASK( imgPRIMASK ); // restore PRIMASK
140 
141  SCUCG->PPCLKEN2_b.CRCLKE = 0; // CRC/Checksum Clock Disable
142 
143  if( SystemCoreClock > 20000000uL )
144  {
145  SCUCG->SCDIVR1_b.HDIV = 4; // HCLK should be set with original frequency
146  }
147 
148  return ( CRC->RLT & 0xffff );
149 }
150 
151 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
172 HAL_Status_Type HAL_CRC_ConfigUserMode( uint32_t u32SEL, uint32_t u32POLY, uint32_t u32AdrInc, uint32_t u32FirstBit )
173 {
174  CRC->CR = 0
175  | ( 0x1uL << CRC_CR_RLTCLR_Pos ) // CRC/Checksum Result Data Register (CRC_RLT) Initialization
176  | MODS_UserMode // User/Auto Mode Selection
177  | u32SEL // CRC/Checksum Selection
178  | u32POLY // Polynomial Selection (CRC only)
179  | u32AdrInc // CRC/Checksum Start Address Auto Increment Control (User mode only)
180  | u32FirstBit; // First Shifted-in Selection (CRC only)
181  CRCRun();
182 
183  return HAL_OK;
184 }
185 
186 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
196 uint32_t HAL_CRC_UserInput( uint32_t u32Input )
197 {
198  uint32_t u32Result = 0x8a290000uL;
199  uint32_t CRC_EADR;
200 
201  CRC_InData( u32Input );
202  CRC_EADR = CRC->EADR;
203  if( ( !ChkCRCFinish() ) || ( CRC->SADR > CRC_EADR ) ) // "Auto"/"User" Increment of Start Address
204  {
205  CRCStop(); // Stop forcingly on User Increment of Start Address
206  SCUCG->PPCLKEN2_b.CRCLKE = 0; // CRC/Checksum Clock Disable
207  u32Result = ( CRC->RLT & 0xffff );
208  }
209 
210  return u32Result;
211 }
212 
HAL_Status_Type HAL_CRC_ConfigUserMode(uint32_t u32SEL, uint32_t u32POLY, uint32_t u32AdrInc, uint32_t u32FirstBit)
CRC/Checksum User Mode Start.
HAL_Status_Type
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
Contains all macro definitions and function prototypes support for crc firmware library on A31G11x.
uint32_t HAL_CRC_UserInput(uint32_t u32Input)
CRC/Checksum Input on User Mode.
HAL_Status_Type HAL_CRC_SetAddress(uint32_t u32SAdr, uint32_t u32EAdr, uint32_t u32IniD)
Set CRC/Checksum Address.
uint32_t HAL_CRC_ConfigAutoMode(uint32_t u32SEL, uint32_t u32POLY, uint32_t u32FirstBit)
CRC/Checksum Auto Mode Start and Result.
HAL_Status_Type HAL_CRC_Init(void)
Initialize CRC/Checksum peripheral.
HAL_Status_Type HAL_CRC_DeInit(void)
DeInitialize CRC peripheral.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
Contains all macro definitions and function prototypes support for scu firmware library on A31G11x.