A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G11x_hal_usart1n.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31G11x_hal_scu.h"
41 #include "A31G11x_hal_usart1n.h"
42 
43 //******************************************************************************
44 // Variable
45 //******************************************************************************
46 
48 
49 /* Public Functions --------------------------------------------------------- */
50 //******************************************************************************
51 // Function
52 //******************************************************************************
53 
54 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
67 static void usart_set_divisors( USART1n_Type* USART1x, uint32_t mode, uint32_t baudrate )
68 {
69  uint32_t numerator;
70  uint32_t denominator;
71  uint32_t n;
72  uint32_t bdr;
73 
74  if( mode == USART1n_UART_MODE )
75  {
76  // baudrate = PCLK / (16 * (bdr + 1))
77  // bdr = (PCLK / (16 * baudrate)) - 1
78  n = 16;
79  }
80  else
81  {
82  // baudrate = PCLK / (2 * (bdr + 1))
83  // bdr = (PCLK / (2 * baudrate)) - 1
84  n = 2;
85  }
86 
87  //--------------------------------------
88  // numerator & denominator
89  //
90  // bdr = USART1n_BaseClock / n / baudrate - 1
91  //--------------------------------------
92  numerator = USART1n_BaseClock;
93  denominator = baudrate;
94 
95  bdr = numerator / n / denominator - 1;
96 
97  USART1x->BDR = ( uint16_t )( bdr & 0xffff );
98 }
99 
100 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
110 HAL_Status_Type HAL_USART_Init( USART1n_Type* USART1x, USART1n_CFG_Type* USART1n_Config )
111 {
112  uint32_t tmp;
113 
114  /* Check USART handle */
115  if( USART1x == NULL )
116  {
117  return HAL_ERROR;
118  }
119 
120 #if 1 // supported
121  if( USART1x == ( USART1n_Type* )USART10 )
122  {
123  /* Set up peripheral clock for USART10 module */
124  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Enable );
126  }
127 #endif
128 
129 #if 1 // supported
130  if( USART1x == ( USART1n_Type* )USART11 )
131  {
132  /* Set up peripheral clock for USART11 module */
133  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Enable );
135  }
136 #endif
137 
138 #if 0 // not supported
139  if( USART1x == ( USART1n_Type* )USART12 )
140  {
141  /* Set up peripheral clock for USART12 module */
142  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Enable );
144  }
145 #endif
146 
147 #if 0 // not supported
148  if( USART1x == ( USART1n_Type* )USART13 )
149  {
150  /* Set up peripheral clock for USART13 module */
151  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Enable );
153  }
154 #endif
155 
156  USART1n_BaseClock = SystemPeriClock;
157 
158  usart_set_divisors( USART1x, USART1n_Config->Mode, USART1n_Config->Baudrate );
159 
160  tmp = 0
161  | ( ( USART1n_Config->Mode & 0x3 ) << USART1n_CR1_USTnMS_Pos )
162  | ( ( USART1n_Config->Parity & 0x3 ) << USART1n_CR1_USTnP_Pos )
163  | ( ( USART1n_Config->Databits & 0x7 ) << USART1n_CR1_USTnS_Pos )
164  | ( ( USART1n_Config->Order & 0x1 ) << USART1n_CR1_ORDn_Pos )
165  | ( ( USART1n_Config->ACK & 0x1 ) << USART1n_CR1_CPOLn_Pos )
166  | ( ( USART1n_Config->Edge & 0x3 ) << USART1n_CR1_CPHAn_Pos )
167  | ( 1 << USART1n_CR1_TXEn_Pos ) // Tx Enable
168  | ( 1 << USART1n_CR1_RXEn_Pos ) // Rx Enable
169  ;
170 
171  USART1x->CR1 = tmp;
172 
173  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnSB_Pos ); // USTnSB reset
174  USART1x->CR2 |= ( ( USART1n_Config->Stopbits & 0x1 ) << USART1n_CR2_USTnSB_Pos ); // USTnSB
175  USART1x->CR2 &= ~( 1 << USART1n_CR2_FXCHn_Pos ); // FXCHn reset
176  // USART1x->CR2 |= (1<<USART1n_CR2_FXCHn_Pos); // FXCHn
177 
179 
180  // Dummy Read
181  tmp = HAL_USART_ReceiveByte( USART1x );
182  tmp = HAL_USART_ReceiveByte( USART1x );
183 
184  return HAL_OK;
185 }
186 
187 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
194 HAL_Status_Type HAL_USART_DeInit( USART1n_Type* USART1x )
195 {
196  /* Check USART handle */
197  if( USART1x == NULL )
198  {
199  return HAL_ERROR;
200  }
201 
202 #if 1 // supported
203  if( USART1x == ( USART1n_Type* )USART10 )
204  {
205  /* Set up peripheral clock for USART10 module */
207  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Disable );
208  }
209 #endif
210 
211 #if 1 // supported
212  if( USART1x == ( USART1n_Type* )USART11 )
213  {
214  /* Set up peripheral clock for USART11 module */
216  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Disable );
217  }
218 #endif
219 
220 #if 0 // not supported
221  if( USART1x == ( USART1n_Type* )USART12 )
222  {
223  /* Set up peripheral clock for USART12 module */
225  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Disable );
226  }
227 #endif
228 
229 #if 0 // not supported
230  if( USART1x == ( USART1n_Type* )USART13 )
231  {
232  /* Set up peripheral clock for USART13 module */
234  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Disable );
235  }
236 #endif
237 
238  return HAL_OK;
239 }
240 
241 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
252 {
253  /* Check USART1n_Config */
254  if( USART1n_Config == NULL )
255  {
256  return HAL_ERROR;
257  }
258 
259  USART1n_Config->Mode = USART1n_UART_MODE;
260  USART1n_Config->Baudrate = 38400;
261  USART1n_Config->Databits = USART1n_DATA_BIT_8;
262  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
263  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
264 
265  return HAL_OK;
266 }
267 
268 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
279 {
280  /* Check USART1n_Config */
281  if( USART1n_Config == NULL )
282  {
283  return HAL_ERROR;
284  }
285 
286  USART1n_Config->Mode = USART1n_USRT_MODE;
287  USART1n_Config->Baudrate = 38400;
288  USART1n_Config->Databits = USART1n_DATA_BIT_8;
289  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
290  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
291 
292  //only SPI & Sync. Mode
293  USART1n_Config->Order = USART1n_SPI_LSB;
294 #if 0 // CPOLn : 0, CPHAn : 0 (X)
295  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
296  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
297 #endif
298 #if 1 // CPOLn : 0, CPHAn : 1 (O)
299  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
300  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
301 #endif
302 
303 #if 0 // CPOLn : 1, CPHAn : 0 (X)
304  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
305  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
306 #endif
307 
308 #if 0 // CPOLn : 1, CPHAn : 1 (O)
309  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
310  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
311 #endif
312 
313  return HAL_OK;
314 }
315 
316 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
327 {
328  /* Check USART1n_Config */
329  if( USART1n_Config == NULL )
330  {
331  return HAL_ERROR;
332  }
333 
334  USART1n_Config->Mode = USART1n_SPI_MODE;
335  USART1n_Config->Baudrate = 38400;
336  USART1n_Config->Databits = USART1n_DATA_BIT_8;
337  USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
338  USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
339 
340  //only SPI & Sync. Mode
341  USART1n_Config->Order = USART1n_SPI_LSB;
342 #if 1 // CPOLn : 0, CPHAn : 0 (X)
343  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
344  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
345 #endif
346 #if 0 // CPOLn : 0, CPHAn : 1 (O)
347  USART1n_Config->ACK = USART1n_SPI_TX_RISING;
348  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
349 #endif
350 
351 #if 0 // CPOLn : 1, CPHAn : 0 (X)
352  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
353  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
354 #endif
355 
356 #if 0 // CPOLn : 1, CPHAn : 1 (O)
357  USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
358  USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
359 #endif
360 
361  return HAL_OK;
362 }
363 
364 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
380 HAL_Status_Type HAL_USART_ConfigInterrupt( USART1n_Type* USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState )
381 {
382  uint32_t tmp = 0;
383 
384  /* Check USART handle */
385  if( USART1x == NULL )
386  {
387  return HAL_ERROR;
388  }
389 
390  switch( USART1n_IntCfg )
391  {
392  case USART1n_INTCFG_WAKE :
393  tmp = USART1n_IER_WAKEINT_EN;
394  break;
395  case USART1n_INTCFG_RXC:
396  tmp = USART1n_IER_RXCINT_EN;
397  break;
398  case USART1n_INTCFG_TXC:
399  tmp = USART1n_IER_TXCINT_EN;
400  break;
401  case USART1n_INTCFG_DR:
402  tmp = USART1n_IER_DR_EN;
403  break;
404  }
405 
406  if( NewState == ENABLE )
407  {
408  USART1x->CR1 |= tmp;
409  }
410  else
411  {
412  USART1x->CR1 &= ~( tmp & USART1n_IER_BITMASK );
413  }
414 
415  return HAL_OK;
416 }
417 
418 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
441 {
442  uint16_t tmp = 0;
443 
444  /* Check USART handle */
445  if( USART1x == NULL )
446  {
447  return HAL_ERROR;
448  }
449 
450  switch( Mode )
451  {
453  tmp = USART1n_CR2_USTnRX8;
454  break;
456  tmp = USART1n_CR2_USTnTX8;
457  break;
459  tmp = USART1n_CR2_USTnSB;
460  break;
462  tmp = USART1n_CR2_FXCHn;
463  break;
465  tmp = USART1n_CR2_USTnSSEN;
466  break;
468  tmp = USART1n_CR2_DISSCKn;
469  break;
471  tmp = USART1n_CR2_LOOPSn;
472  break;
474  tmp = USART1n_CR2_MASTERn;
475  break;
477  tmp = USART1n_CR2_DBLSn;
478  break;
480  tmp = USART1n_CR2_USTnEN;
481  break;
482  default:
483  break;
484  }
485 
486  if( NewState == ENABLE )
487  {
488  USART1x->CR2 |= tmp;
489  }
490  else
491  {
492  USART1x->CR2 &= ~( tmp & USART1n_CR2_BITMASK );
493  }
494 
495  return HAL_OK;
496 }
497 
498 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
507 HAL_Status_Type HAL_USART_Enable( USART1n_Type* USART1x, FunctionalState state )
508 {
509  /* Check USART handle */
510  if( USART1x == NULL )
511  {
512  return HAL_ERROR;
513  }
514 
515  if( state == ENABLE )
516  {
517  USART1x->CR2 |= ( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
518  }
519  else
520  {
521  USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnEN_Pos ); // USTnEN
522  }
523 
524  return HAL_OK;
525 }
526 
527 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
536 {
537  uint32_t tmp;
538 
539  /* Check USART handle */
540  if( USART1x == NULL )
541  {
542  return HAL_ERROR;
543  }
544 
545  switch( Status )
546  {
547  case USART1n_STATUS_WAKE:
548  tmp = USART1n_SR_WAKE;
549  break;
550  case USART1n_STATUS_RXC:
551  tmp = USART1n_SR_RXC;
552  break;
553  case USART1n_STATUS_TXC:
554  tmp = USART1n_SR_TXC;
555  break;
556  case USART1n_STATUS_DRE:
557  tmp = USART1n_SR_DRE;
558  break;
559  default:
560  return HAL_ERROR;
561  }
562 
563  USART1x->ST = tmp;
564 
565  return HAL_OK;
566 }
567 
568 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
575 uint8_t HAL_USART_GetStatus( USART1n_Type* USART1x )
576 {
577  return ( ( USART1x->ST ) & USART1n_SR_BITMASK );
578 }
579 
580 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
587 FlagStatus HAL_USART_CheckBusy( USART1n_Type* USART1x )
588 {
589  if( USART1x->ST & USART1n_SR_DRE )
590  {
591  return RESET;
592  }
593  else
594  {
595  return SET;
596  }
597 }
598 
599 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
608 HAL_Status_Type HAL_USART_TransmitByte( USART1n_Type* USART1x, uint8_t Data )
609 {
610  /* Check USART handle */
611  if( USART1x == NULL )
612  {
613  return HAL_ERROR;
614  }
615 
616  USART1x->DR = Data;
617 
618  return HAL_OK;
619 }
620 
621 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
628 uint8_t HAL_USART_ReceiveByte( USART1n_Type* USART1x )
629 {
630  return USART1x->DR;
631 }
632 
633 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
650 uint32_t HAL_USART_Transmit( USART1n_Type* USART1x, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
651 {
652  uint32_t bToSend, bSent, timeOut;
653  uint8_t* pChar = txbuf;
654 
655  bToSend = buflen;
656 
657  // blocking mode
658 
659  if( flag == BLOCKING )
660  {
661  bSent = 0;
662  while( bToSend )
663  {
664 
665  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
666 
667  timeOut = USART1n_BLOCKING_TIMEOUT;
668  // Wait for THR empty with timeout
669  while( !( USART1x->ST & USART1n_SR_TXC ) )
670  {
671  if( timeOut == 0 )
672  {
673  break;
674  }
675  timeOut--;
676  }
677  // Time out!
678  if( timeOut == 0 )
679  {
680  break;
681  }
683  bToSend--;
684  bSent++;
685  }
686  }
687 
688  // Non-Blocking Mode
689  else
690  {
691  bSent = 0;
692  while( bToSend )
693  {
694  if( !( USART1x->ST & USART1n_SR_DRE ) )
695  {
696  break;
697  }
698  HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
699  bToSend--;
700  bSent++;
701  }
702  }
703 
704  return bSent;
705 }
706 
707 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
724 uint32_t HAL_USART_Receive( USART1n_Type* USART1x, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
725 {
726  uint32_t bToRecv, bRecv, timeOut;
727  uint8_t* pChar = rxbuf;
728 
729  bToRecv = buflen;
730 
731  // Blocking Mode
732  if( flag == BLOCKING )
733  {
734  bRecv = 0;
735  while( bToRecv )
736  {
737  timeOut = USART1n_BLOCKING_TIMEOUT;
738  while( !( USART1x->ST & USART1n_SR_RXC ) )
739  {
740  if( timeOut == 0 )
741  {
742  break;
743  }
744  timeOut--;
745  }
746  // Time out!
747 
748  if( timeOut == 0 )
749  {
750  break;
751  }
752  // Get data from the buffer
753  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
754 
755  bToRecv--;
756  bRecv++;
757  }
758  }
759 
760  // Non-Blocking Mode
761  else
762  {
763  bRecv = 0;
764  while( bToRecv )
765  {
766  if( !( USART1x->ST & USART1n_SR_RXC ) )
767  {
768  break;
769  }
770  else
771  {
772  ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
773  bRecv++;
774  bToRecv--;
775  }
776  }
777  }
778 
779  return bRecv;
780 }
781 
HAL_Status_Type
USART1n_STATUS_Type
uint8_t HAL_USART_ReceiveByte(USART1n_Type *USART1x)
Receive a single data from USART peripheral.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_USART_DataControlConfig(USART1n_Type *USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState)
Configure Data Control mode for USART peripheral.
USART1n_EDGE_Type Edge
USART1n_PARITY_BIT_Type Parity
USART1n_SPI_ORDER_Type Order
HAL_Status_Type HAL_USART_ClearStatus(USART1n_Type *USART1x, USART1n_STATUS_Type Status)
Clear Status register in USART peripheral.
USART1n_OPMODE_Type Mode
HAL_Status_Type HAL_USART_SPI_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART_InitStruct member with its default value:
HAL_Status_Type HAL_USART_TransmitByte(USART1n_Type *USART1x, uint8_t Data)
Transmit a single data through USART peripheral.
HAL_Status_Type HAL_USART_DeInit(USART1n_Type *USART1x)
Deinitialize the USART1n peripheral registers to their default reset values.
uint8_t HAL_USART_GetStatus(USART1n_Type *USART1x)
Get current value of Line Status register in USART peripheral.
uint32_t HAL_USART_Transmit(USART1n_Type *USART1x, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Send a block of data via USART peripheral.
uint32_t HAL_USART_Receive(USART1n_Type *USART1x, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Receive a block of data via USART peripheral.
FunctionalState
uint32_t USART1n_BaseClock
HAL_Status_Type HAL_USART_ConfigInterrupt(USART1n_Type *USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
HAL_Status_Type HAL_USART_UART_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART_InitStruct member with its default value:
USART1n_ACK_Type ACK
USART1n_DATA_BIT_Type Databits
HAL_Status_Type HAL_USART_USRT_Mode_Config(USART1n_CFG_Type *USART1n_Config)
Fills each USART_InitStruct member with its default value:
USART1n_CONTROL_Type
FlagStatus HAL_USART_CheckBusy(USART1n_Type *USART1x)
Check whether if USART is busy or not.
USART1n_STOP_BIT_Type Stopbits
Contains all macro definitions and function prototypes support for usart1n firmware library on A31G11...
HAL_Status_Type HAL_USART_Enable(USART1n_Type *USART1x, FunctionalState state)
USART1n enable control.
USART1n_INT_Type
static void usart_set_divisors(USART1n_Type *USART1x, uint32_t mode, uint32_t baudrate)
Determines best dividers to get a target clock rate.
TRANSFER_BLOCK_Type
HAL_Status_Type HAL_USART_Init(USART1n_Type *USART1x, USART1n_CFG_Type *USART1n_Config)
Initialize the USART1n peripheral with the specified parameters.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
Contains all macro definitions and function prototypes support for scu firmware library on A31G11x.