A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G11x_hal_timer3n.h
Go to the documentation of this file.
1 /***************************************************************************//****************************************************************************/
34 
35 #ifndef _TIMER3n_H_
36 #define _TIMER3n_H_
37 
38 #include "A31G11x.h"
39 #include "A31G11x_hal_aa_types.h"
40 
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 
45 //******************************************************************************
46 // Constant
47 //******************************************************************************
48 
49 //========== TIMER3n_CR ========================================
50 
51 //---------- TIMER3n Enable/Disable Definition ----------
52 #define TIMER3n_DISABLE (0x0uL << TIMER3n_CR_T3nEN_Pos)
53 #define TIMER3n_ENABLE (0x1uL << TIMER3n_CR_T3nEN_Pos)
54 
55 //---------- TIMER3n Clock Selection Definition ----------
56 #define TIMER3n_CLKINT (0x0uL << TIMER3n_CR_T3nCLK_Pos)
57 #define TIMER3n_CLKEXT (0x1uL << TIMER3n_CR_T3nCLK_Pos)
58 
59 //---------- TIMER3n Mode Selection Definition ----------
60 #define TIMER3n_INVM (0x0uL << TIMER3n_CR_T3nMS_Pos)
61 #define TIMER3n_CAPM (0x1uL << TIMER3n_CR_T3nMS_Pos)
62 #define TIMER3n_BTOB (0x2uL << TIMER3n_CR_T3nMS_Pos)
63 
64 //---------- TIMER3n External Clock Edge Selection Definition ----------
65 #define TIMER3n_FEDGE (0x0uL << TIMER3n_CR_T3nECE_Pos)
66 #define TIMER3n_REDGE (0x1uL << TIMER3n_CR_T3nECE_Pos)
67 
68 //---------- TIMER3n Output Mode Selection Definition ----------
69 #define TIMER3n_6CHMOD (0x0uL << TIMER3n_CR_FORCA_Pos)
70 #define TIMER3n_FORAMOD (0x1uL << TIMER3n_CR_FORCA_Pos)
71 
72 //---------- TIMER3n Delay Time Insert En/Disable Definition ----------
73 #define TIMER3n_DLYINSDIS (0x0uL << TIMER3n_CR_DLYEN_Pos)
74 #define TIMER3n_DLYINSEN (0x1uL << TIMER3n_CR_DLYEN_Pos)
75 
76 //---------- TIMER3n Delay Timer Insertion Position Definition ----------
77 #define TIMER3n_INSFRONT (0x0uL << TIMER3n_CR_DLYPOS_Pos)
78 #define TIMER3n_INSBACK (0x1uL << TIMER3n_CR_DLYPOS_Pos)
79 
80 //---------- TIMER3n Capture Polarity Selection Definition ----------
81 #define TIMER3n_CAPFALL (0x0uL << TIMER3n_CR_T3nCPOL_Pos)
82 #define TIMER3n_CAPRISE (0x1uL << TIMER3n_CR_T3nCPOL_Pos)
83 #define TIMER3n_CAPBOTH (0x2uL << TIMER3n_CR_T3nCPOL_Pos)
84 
85 //---------- TIMER3n Data Reload Time Selection Definition ----------
86 #define TIMER3n_UPWRITE (0x0uL << TIMER3n_CR_UPDT_Pos)
87 #define TIMER3n_UPMATCH (0x1uL << TIMER3n_CR_UPDT_Pos)
88 #define TIMER3n_UPBOTTOM (0x2uL << TIMER3n_CR_UPDT_Pos)
89 
90 //---------- TIMER3n Period Match Interrupt Occurrence Selection Definition ----------
91 #define TIMER3n_E1PERIOD (0x00uL << TIMER3n_CR_PMOC_Pos)
92 #define TIMER3n_E2PERIOD (0x01uL << TIMER3n_CR_PMOC_Pos)
93 #define TIMER3n_E3PERIOD (0x02uL << TIMER3n_CR_PMOC_Pos)
94 #define TIMER3n_E4PERIOD (0x03uL << TIMER3n_CR_PMOC_Pos)
95 #define TIMER3n_E5PERIOD (0x04uL << TIMER3n_CR_PMOC_Pos)
96 #define TIMER3n_E6PERIOD (0x05uL << TIMER3n_CR_PMOC_Pos)
97 #define TIMER3n_E7PERIOD (0x06uL << TIMER3n_CR_PMOC_Pos)
98 #define TIMER3n_E8PERIOD (0x07uL << TIMER3n_CR_PMOC_Pos)
99 
100 //========== TIMER3n_OUTCR ========================================
101 
102 //---------- TIMER3n PWM30xB Output Polarity Selection Definition ----------
103 #define TIMER3n_OUT_BPOLOW (0x0uL << TIMER3n_OUTCR_POLB_Pos)
104 #define TIMER3n_OUT_BPOHIGH (0x1uL << TIMER3n_OUTCR_POLB_Pos)
105 
106 //---------- TIMER3n PWM30xA Output Polarity Selection Definition ----------
107 #define TIMER3n_OUT_APOLOW (0x0uL << TIMER3n_OUTCR_POLA_Pos)
108 #define TIMER3n_OUT_APOHIGH (0x1uL << TIMER3n_OUTCR_POLA_Pos)
109 
110 //---------- TIMER3n PWM30AB Output En/Disable Definition ----------
111 #define TIMER3n_OUT_PWMABDIS (0x0uL << TIMER3n_OUTCR_PABOE_Pos)
112 #define TIMER3n_OUT_PWMABEN (0x1uL << TIMER3n_OUTCR_PABOE_Pos)
113 
114 //---------- TIMER3n PWM30BB Output En/Disable Definition ----------
115 #define TIMER3n_OUT_PWMBBDIS (0x0uL << TIMER3n_OUTCR_PBBOE_Pos)
116 #define TIMER3n_OUT_PWMBBEN (0x1uL << TIMER3n_OUTCR_PBBOE_Pos)
117 
118 //---------- TIMER3n PWM30CB Output En/Disable Definition ----------
119 #define TIMER3n_OUT_PWMCBDIS (0x0uL << TIMER3n_OUTCR_PCBOE_Pos)
120 #define TIMER3n_OUT_PWMCBEN (0x1uL << TIMER3n_OUTCR_PCBOE_Pos)
121 
122 //---------- TIMER3n PWM30AA Output En/Disable Definition ----------
123 #define TIMER3n_OUT_PWMAADIS (0x0uL << TIMER3n_OUTCR_PAAOE_Pos)
124 #define TIMER3n_OUT_PWMAAEN (0x1uL << TIMER3n_OUTCR_PAAOE_Pos)
125 
126 //---------- TIMER3n PWM30BA Output En/Disable Definition ----------
127 #define TIMER3n_OUT_PWMBADIS (0x0uL << TIMER3n_OUTCR_PBAOE_Pos)
128 #define TIMER3n_OUT_PWMBAEN (0x1uL << TIMER3n_OUTCR_PBAOE_Pos)
129 
130 //---------- TIMER3n PWM30CA Output En/Disable Definition ----------
131 #define TIMER3n_OUT_PWMCADIS (0x0uL << TIMER3n_OUTCR_PCAOE_Pos)
132 #define TIMER3n_OUT_PWMCAEN (0x1uL << TIMER3n_OUTCR_PCAOE_Pos)
133 
134 //---------- TIMER3n PWM30AB Output When Disable ----------
135 #define TIMER3n_OUT_ABLOW (0x0uL << TIMER3n_OUTCR_LVLAB_Pos)
136 #define TIMER3n_OUT_ABHIGH (0x1uL << TIMER3n_OUTCR_LVLAB_Pos)
137 
138 //---------- TIMER3n PWM30BB Output When Disable ----------
139 #define TIMER3n_OUT_BBLOW (0x0uL << TIMER3n_OUTCR_LVLBB_Pos)
140 #define TIMER3n_OUT_BBHIGH (0x1uL << TIMER3n_OUTCR_LVLBB_Pos)
141 
142 //---------- TIMER3n PWM30CB Output When Disable ----------
143 #define TIMER3n_OUT_CBLOW (0x0uL << TIMER3n_OUTCR_LVLCB_Pos)
144 #define TIMER3n_OUT_CBHIGH (0x1uL << TIMER3n_OUTCR_LVLCB_Pos)
145 
146 //---------- TIMER3n PWM30AA Output When Disable ----------
147 #define TIMER3n_OUT_AALOW (0x0uL << TIMER3n_OUTCR_LVLAA_Pos)
148 #define TIMER3n_OUT_AAHIGH (0x1uL << TIMER3n_OUTCR_LVLAA_Pos)
149 
150 //---------- TIMER3n PWM30BA Output When Disable ----------
151 #define TIMER3n_OUT_BALOW (0x0uL << TIMER3n_OUTCR_LVLBA_Pos)
152 #define TIMER3n_OUT_BAHIGH (0x1uL << TIMER3n_OUTCR_LVLBA_Pos)
153 
154 //---------- TIMER3n PWM30CA Output When Disable ----------
155 #define TIMER3n_OUT_CALOW (0x0uL << TIMER3n_OUTCR_LVLCA_Pos)
156 #define TIMER3n_OUT_CAHIGH (0x1uL << TIMER3n_OUTCR_LVLCA_Pos)
157 
158 //========== TIMER3n_INTCR ========================================
159 
160 //---------- TIMER3n High-Impedance Interrupt EN/Disable Definition ----------
161 #define TIMER3n_INT_HIZDIS (0x0uL << TIMER3n_INTCR_HIZIEN_Pos)
162 #define TIMER3n_INT_HIZEN (0x1uL << TIMER3n_INTCR_HIZIEN_Pos)
163 
164 //---------- TIMER3n Capture Interrupt EN/Disable Definition ----------
165 #define TIMER3n_INT_CAPDIS (0x0uL << TIMER3n_INTCR_T3nCIEN_Pos)
166 #define TIMER3n_INT_CAPEN (0x1uL << TIMER3n_INTCR_T3nCIEN_Pos)
167 
168 //---------- TIMER3n Bottom Interrupt EN/Disable Definition ----------
169 #define TIMER3n_INT_BOTDIS (0x0uL << TIMER3n_INTCR_T3nBTIEN_Pos)
170 #define TIMER3n_INT_BOTEN (0x1uL << TIMER3n_INTCR_T3nBTIEN_Pos)
171 
172 //---------- TIMER3n Period Match Interrupt EN/Disable Definition ----------
173 #define TIMER3n_INT_PMATDIS (0x0uL << TIMER3n_INTCR_T3nPMIEN_Pos)
174 #define TIMER3n_INT_PMATEN (0x1uL << TIMER3n_INTCR_T3nPMIEN_Pos)
175 
176 //---------- TIMER3n A Match Interrupt EN/Disable Definition ----------
177 #define TIMER3n_INT_AMATDIS (0x0uL << TIMER3n_INTCR_T3nAMIEN_Pos)
178 #define TIMER3n_INT_AMATEN (0x1uL << TIMER3n_INTCR_T3nAMIEN_Pos)
179 
180 //---------- TIMER3n B Match Interrupt EN/Disable Definition ----------
181 #define TIMER3n_INT_BMATDIS (0x0uL << TIMER3n_INTCR_T3nBMIEN_Pos)
182 #define TIMER3n_INT_BMATEN (0x1uL << TIMER3n_INTCR_T3nBMIEN_Pos)
183 
184 //---------- TIMER3n C Match Interrupt EN/Disable Definition ----------
185 #define TIMER3n_INT_CMATDIS (0x0uL << TIMER3n_INTCR_T3nCMIEN_Pos)
186 #define TIMER3n_INT_CMATEN (0x1uL << TIMER3n_INTCR_T3nCMIEN_Pos)
187 
188 //========== TIMER3n_HIZCR ========================================
189 
190 //---------- TIMER3n PWM Output High-Impedance En/Disable Definition ----------
191 #define TIMER3n_HIZ_DISABLE (0x0uL << TIMER3n_HIZCR_HIZEN_Pos)
192 #define TIMER3n_HIZ_ENABLE (0x1uL << TIMER3n_HIZCR_HIZEN_Pos)
193 
194 //---------- TIMER3n High-Impedance(BLNK) Edge Definition ----------
195 #define TIMER3n_HIZ_BLNKFALL (0x0uL << TIMER3n_HIZCR_HEDGE_Pos)
196 #define TIMER3n_HIZ_BLNKRISE (0x1uL << TIMER3n_HIZCR_HEDGE_Pos)
197 
198 //========== TIMER3n_ADTCR ========================================
199 
200 //---------- TIMER3n Bottom for A/DC Trigger Signal Generator EN/Disable Definition ----------
201 #define TIMER3n_ADT_BTTGDIS (0x0uL << TIMER3n_ADTCR_T3nBTTG_Pos)
202 #define TIMER3n_ADT_BTTGEN (0x1uL << TIMER3n_ADTCR_T3nBTTG_Pos)
203 
204 //---------- TIMER3n Period Match for A/DC Trigger Signal Generator EN/Disable Definition ----------
205 #define TIMER3n_ADT_PMTGDIS (0x0uL << TIMER3n_ADTCR_T3nPMTG_Pos)
206 #define TIMER3n_ADT_PMTGEN (0x1uL << TIMER3n_ADTCR_T3nPMTG_Pos)
207 
208 //---------- TIMER3n A-ch Match for A/DC Trigger Signal Generator EN/Disable Definition ----------
209 #define TIMER3n_ADT_AMTGDIS (0x0uL << TIMER3n_ADTCR_T3nAMTG_Pos)
210 #define TIMER3n_ADT_AMTGEN (0x1uL << TIMER3n_ADTCR_T3nAMTG_Pos)
211 
212 //---------- TIMER3n B-ch Match for A/DC Trigger Signal Generator EN/Disable Definition ----------
213 #define TIMER3n_ADT_BMTGDIS (0x0uL << TIMER3n_ADTCR_T3nBMTG_Pos)
214 #define TIMER3n_ADT_BMTGEN (0x1uL << TIMER3n_ADTCR_T3nBMTG_Pos)
215 
216 //---------- TIMER3n C-ch Match for A/DC Trigger Signal Generator EN/Disable Definition ----------
217 #define TIMER3n_ADT_CMTGDIS (0x0uL << TIMER3n_ADTCR_T3nCMTG_Pos)
218 #define TIMER3n_ADT_CMTGEN (0x1uL << TIMER3n_ADTCR_T3nCMTG_Pos)
219 
220 //******************************************************************************
221 // Type
222 //******************************************************************************
223 
224 //==============================================================================
225 // Structure
226 //==============================================================================
227 
228 typedef struct
229 {
230  // TIMER3n.CR
231  TIMER3n_CR_T3nMS_Enum T3nMS; // TIMER3n Operation Mode Selection
232  TIMER3n_CR_T3nCLK_Enum T3nCLK; // TIMER3n Clock Selection
233  TIMER3n_CR_T3nECE_Enum T3nECE; // TIMER3n External Clock Edge Selection
234  TIMER3n_CR_T3nCPOL_Enum T3nCPOL; // TIMER3n Capture Polarity Selection
235 
236  // TIMER3n.PDR
237  uint16_t PDR;
238 
239  // TIMER3n.ADR
240  uint16_t ADR;
241 
242  // TIMER3n.BDR
243  uint16_t BDR;
244 
245  // TIMER3n.CDR
246  uint16_t CDR;
247 
248  // TIMER3n.PREDR
249  uint16_t Prescaler;
251 
252 //******************************************************************************
253 // Macro
254 //******************************************************************************
255 
256 // Control
257 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
261 #define TIMER3n_EN() (TIMER30->CR_b.T3nEN = 1)
262 #define TIMER3n_DIS() (TIMER30->CR_b.T3nEN = 0)
263 #define TIMER3n_EnableTimer( TIMER3x ) (TIMER3x->CR_b.T3nEN = 1)
264 #define TIMER3n_DisableTimer( TIMER3x ) (TIMER3x->CR_b.T3nEN = 0)
265 
266 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
270 #define TIMER3n_ClrCnt() (TIMER30->CR_b.T3nCLR = 1)
271 #define TIMER3n_ClearCounter( TIMER3x ) (TIMER3x->CR_b.T3nCLR = 1)
272 
273 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
277 #define TIMER3n_GetCnt() (TIMER30->CNT)
278 
279 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
283 #define TIMER3n_SetPMOC( u32PMOC ) (TIMER30->CR_b.PMOC = u32PMOC)
284 
285 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
289 #define TIMER3n_HIZEN() (TIMER30->HIZCR_b.T3nEN = 1)
290 #define TIMER3n_HIZDIS() (TIMER30->HIZCR_b.T3nEN = 0)
291 
292 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
296 #define TIMER3n_SetHIZSW() (TIMER30->HIZCR_b.HIZSW = 1)
297 
298 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
302 #define TIMER3n_ClrHIZ() (TIMER30->HIZCR_b.HIZCLR = 1)
303 
304 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
308 #define TIMER3n_GetHIZStaus() (TIMER30->HIZCR_b.HIZSTA)
309 
310 // Set & Get Data Register
311 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
317 #define TIMER3n_SetPeData( u32PData ) (TIMER30->PDR = u32PData)
318 
319 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
325 #define TIMER3n_SetAData( u32AData ) (TIMER30->ADR = u32AData)
326 
327 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
333 #define TIMER3n_SetBData( u32BData ) (TIMER30->BDR = u32BData)
334 
335 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
341 #define TIMER3n_SetCData( u32CData ) (TIMER30->CDR = u32CData)
342 
343 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
347 #define TIMER3n_GetCapData() (TIMER30->CAPDR)
348 #define TIMER3n_GetCaptureData( TIMER3x ) (TIMER3x->CAPDR)
349 
350 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
356 #define TIMER3n_SetDelayData( u32DelayData ) (TIMER30->DLY = u32DelayData)
357 
358 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
364 #define TIMER3n_SetADTData( u32ADTData ) (TIMER30->ADTDR = u32ADTData)
365 
366 // Get & Clear Interrupt Flag
367 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
371 #define TIMER3n_AllInt_GetFg() (TIMER30->INTFLAG)
372 
373 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
377 #define TIMER3n_CMaInt_GetFg() (TIMER30->INTFLAG_b.T30CMIFLAG)
378 
379 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
383 #define TIMER3n_BMaInt_GetFg() (TIMER30->INTFLAG_b.T30BMIFLAG)
384 
385 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
389 #define TIMER3n_AchMaInt_GetFg() (TIMER30->INTFLAG_b.T30AMIFLAG)
390 
391 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
395 #define TIMER3n_PeMaInt_GetFg() (TIMER30->INTFLAG_b.T30PMIFLAG)
396 
397 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
401 #define TIMER3n_BotMaInt_GetFg() (TIMER30->INTFLAG_b.T30BTIFLAG)
402 
403 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
407 #define TIMER3n_CapInt_GetFg() (TIMER30->INTFLAG_b.T30CIFLAG)
408 
409 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
413 #define TIMER3n_HIZInt_GetFg() (TIMER30->INTFLAG_b.HIZIFLAG)
414 
415 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
419 #define TIMER3n_AllInt_ClrFg() (TIMER30->INTFLAG = 0x7F)
420 
421 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
425 #define TIMER3n_CchMaInt_ClrFg() (TIMER30->INTFLAG_b.T30CMIFLAG = 1)
426 
427 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
431 #define TIMER3n_BchMaInt_ClrFg() (TIMER30->INTFLAG_b.T30BMIFLAG = 1)
432 
433 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
437 #define TIMER3n_AchMaInt_ClrFg() (TIMER30->INTFLAG_b.T30AMIFLAG = 1)
438 
439 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
443 #define TIMER3n_PeMaInt_ClrFg() (TIMER30->INTFLAG_b.T30PMIFLAG = 1)
444 
445 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
449 #define TIMER3n_BotMaInt_ClrFg() (TIMER30->INTFLAG_b.T30BTIFLAG = 1)
450 
451 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
455 #define TIMER3n_CapInt_ClrFg() (TIMER30->INTFLAG_b.T30CIFLAG = 1)
456 
457 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
461 #define TIMER3n_HIZInt_ClrFg() (TIMER30->INTFLAG_b.HIZIFLAG = 1)
462 
463 //******************************************************************************
464 // Function
465 //******************************************************************************
466 
467 HAL_Status_Type HAL_TIMER3n_Init( TIMER3n_Type* TIMER3x, TIMER3n_CFG_Type* TIMER3n_Config );
468 HAL_Status_Type HAL_TIMER3n_DeInit( TIMER3n_Type* TIMER3x );
469 
470 HAL_Status_Type HAL_TIMER3n_ConfigInterrupt( TIMER3n_Type* TIMER3x, uint32_t NewState, uint32_t TIMER3n_IntCfg );
471 HAL_Status_Type HAL_TIMER3n_MPWMCmd( TIMER3n_Type* TIMER3x, uint32_t updatedata, uint32_t intcount );
472 HAL_Status_Type HAL_TIMER3n_Start( TIMER3n_Type* TIMER3x, uint32_t NewState );
473 HAL_Status_Type HAL_TIMER3n_OutputCtrl( TIMER3n_Type* TIMER3x, uint32_t NewState, uint32_t pwmApol, uint32_t pwmBpol );
474 HAL_Status_Type HAL_TIMER3n_ClockPrescaler( TIMER3n_Type* TIMER3x, uint32_t prescale );
475 HAL_Status_Type HAL_TIMER3n_SetPeriod( TIMER3n_Type* TIMER3x, uint32_t period );
476 HAL_Status_Type HAL_TIMER3n_SetADuty( TIMER3n_Type* TIMER3x, uint32_t aduty );
477 HAL_Status_Type HAL_TIMER3n_SetBDuty( TIMER3n_Type* TIMER3x, uint32_t bduty );
478 HAL_Status_Type HAL_TIMER3n_SetCDuty( TIMER3n_Type* TIMER3x, uint32_t cduty );
479 HAL_Status_Type HAL_TIMER3n_SetDelayTime( TIMER3n_Type* TIMER3x, uint32_t dten, uint32_t dtpos, uint32_t clkdata );
480 HAL_Status_Type HAL_TIMER3n_SetHizReg( TIMER3n_Type* TIMER3x, uint32_t u32T30HizSet );
481 HAL_Status_Type HAL_TIMER3n_SetADCTrigger( TIMER3n_Type* TIMER3x, uint32_t u32triggerpoint, uint32_t u32triggertime );
482 HAL_Status_Type HAL_TIMER3n_ClearStatus_IT( TIMER3n_Type* TIMER3x, uint32_t TIMER3n_IntCfg );
483 uint32_t HAL_TIMER3n_GetStatus_IT( TIMER3n_Type* TIMER3x );
484 
485 #ifdef __cplusplus
486 }
487 #endif
488 
489 #endif /* _TIMER3n_H_ */
490 
HAL_Status_Type
HAL_Status_Type HAL_TIMER3n_ConfigInterrupt(TIMER3n_Type *TIMER3x, uint32_t NewState, uint32_t TIMER3n_IntCfg)
Interrupt Control Register.
HAL_Status_Type HAL_TIMER3n_ClearStatus_IT(TIMER3n_Type *TIMER3x, uint32_t TIMER3n_IntCfg)
Interrupt Flag Clear.
Contains the ABOV typedefs for C standard types. It is intended to be used in ISO C conforming develo...
HAL_Status_Type HAL_TIMER3n_SetBDuty(TIMER3n_Type *TIMER3x, uint32_t bduty)
Set duty B data.
HAL_Status_Type HAL_TIMER3n_Init(TIMER3n_Type *TIMER3x, TIMER3n_CFG_Type *TIMER3n_Config)
Initialize the TIMER3n peripheral with the specified parameters.
HAL_Status_Type HAL_TIMER3n_Start(TIMER3n_Type *TIMER3x, uint32_t NewState)
Enable or Disable PWM start.
HAL_Status_Type HAL_TIMER3n_DeInit(TIMER3n_Type *TIMER3x)
Close Timer/Counter device.
HAL_Status_Type HAL_TIMER3n_SetADCTrigger(TIMER3n_Type *TIMER3x, uint32_t u32triggerpoint, uint32_t u32triggertime)
Set ADC Tirgger Source & Timing.
HAL_Status_Type HAL_TIMER3n_SetDelayTime(TIMER3n_Type *TIMER3x, uint32_t dten, uint32_t dtpos, uint32_t clkdata)
Set dead time (delay time)
HAL_Status_Type HAL_TIMER3n_MPWMCmd(TIMER3n_Type *TIMER3x, uint32_t updatedata, uint32_t intcount)
TIMER3n PWM Mode Setting (Initial : Back to Back Mode, Internal Clock, 6channel Mode)
HAL_Status_Type HAL_TIMER3n_ClockPrescaler(TIMER3n_Type *TIMER3x, uint32_t prescale)
Set Prescaler data.
HAL_Status_Type HAL_TIMER3n_OutputCtrl(TIMER3n_Type *TIMER3x, uint32_t NewState, uint32_t pwmApol, uint32_t pwmBpol)
PWM Output Port Control Register (Initial : 6channel enable, output low)
TIMER3n_CR_T3nCPOL_Enum T3nCPOL
HAL_Status_Type HAL_TIMER3n_SetPeriod(TIMER3n_Type *TIMER3x, uint32_t period)
Set period data.
TIMER3n_CR_T3nMS_Enum T3nMS
TIMER3n_CR_T3nCLK_Enum T3nCLK
HAL_Status_Type HAL_TIMER3n_SetCDuty(TIMER3n_Type *TIMER3x, uint32_t cduty)
Set duty C data.
HAL_Status_Type HAL_TIMER3n_SetHizReg(TIMER3n_Type *TIMER3x, uint32_t u32T30HizSet)
Set HIZCR Register.
TIMER3n_CR_T3nECE_Enum T3nECE
uint32_t HAL_TIMER3n_GetStatus_IT(TIMER3n_Type *TIMER3x)
Get Interrupt Flag.
HAL_Status_Type HAL_TIMER3n_SetADuty(TIMER3n_Type *TIMER3x, uint32_t aduty)
Set duty A data.