A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G11x_hal_scu.h
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1 /***************************************************************************//****************************************************************************/
34 
35 #ifndef _SCU_H_
36 #define _SCU_H_
37 
38 #include "A31G11x.h"
39 #include "A31G11x_hal_aa_types.h"
40 
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 
45 //******************************************************************************
46 // Constant
47 //******************************************************************************
48 
49 // Boot Pin Function Selection Control
50 /*
51 #define B_INCLUDE_RSTB 2
52 #define B_POR_ONLY 3
53 */
54 #define BFIND_PORorEXTR SCUCC_BTPSCR_BFIND_PORorEXTR
55 #define BFIND_POR SCUCC_BTPSCR_BFIND_POR
56 
57 // HIRC Fine Trim One Step Change Control
58 #define HIRC_UP_ONESTEP 0
59 #define HIRC_DOWN_ONESTEP 1
60 
61 // WDTRC Fine Trim One Step Change Control
62 #define WDTRC_UP_ONESTEP 0
63 #define WDTRC_DOWN_ONESTEP 1
64 
65 
66 // MCLK Selection Control
67 /*
68 #define SCU_HIRC (0x0uL << 0)
69 #define SCU_XMOSC (0x1uL << 0)
70 #define SCU_XSOSC (0x2uL << 0)
71 #define SCU_WDTRC (0x3uL << 0)
72 */
73 #define MCLKSEL_HIRC (SCUCG_SCCR_MCLKSEL_HIRC << SCUCG_SCCR_MCLKSEL_Pos)
74 #define MCLKSEL_XMOSC (SCUCG_SCCR_MCLKSEL_XMOSC << SCUCG_SCCR_MCLKSEL_Pos)
75 #define MCLKSEL_XSOSC (SCUCG_SCCR_MCLKSEL_XSOSC << SCUCG_SCCR_MCLKSEL_Pos)
76 #define MCLKSEL_WDTRC (SCUCG_SCCR_MCLKSEL_WDTRC << SCUCG_SCCR_MCLKSEL_Pos)
77 
78 // HIRC Selection Control
79 /*
80 #define HIRC_40M (0x0uL << 12)
81 #define HIRC_20M (0x1uL << 12)
82 #define HIRC_10M (0x2uL << 12)
83 #define HIRC_5M (0x3uL << 12)
84 */
85 #define HIRCSEL_HIRC1 (SCUCG_CLKSRCR_HIRCSEL_HIRC1 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 40MHz HIRC
86 #define HIRCSEL_HIRC2 (SCUCG_CLKSRCR_HIRCSEL_HIRC2 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 20MHz HIRC
87 #define HIRCSEL_HIRC4 (SCUCG_CLKSRCR_HIRCSEL_HIRC4 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 10MHz HIRC
88 #define HIRCSEL_HIRC8 (SCUCG_CLKSRCR_HIRCSEL_HIRC8 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 5MHz HIRC
89 
90 // XMFRNG Selection Control
91 /*
92 #define XTAL_XM (0x0uL << 8)
93 #define EXT_XM (0x1uL << 8)
94 */
95 #define XMFRNG_Xtal (SCUCG_CLKSRCR_XMFRNG_Xtal << SCUCG_CLKSRCR_XMFRNG_Pos)
96 #define XMFRNG_Clock (SCUCG_CLKSRCR_XMFRNG_Clock << SCUCG_CLKSRCR_XMFRNG_Pos)
97 
98 // System Clock Source Enable Control
99 /*
100 #define EN_XSOSC (0x1uL << 0)
101 #define EN_XMOSC (0x1uL << 1)
102 #define EN_HIRC (0x1uL << 2)
103 #define EN_WDTRC (0x1uL << 3)
104 */
105 #define CLKSRCR_WDTRCEN (0x1uL << SCUCG_CLKSRCR_WDTRCEN_Pos)
106 #define CLKSRCR_HIRCEN (0x1uL << SCUCG_CLKSRCR_HIRCEN_Pos)
107 #define CLKSRCR_XMOSCEN (0x1uL << SCUCG_CLKSRCR_XMOSCEN_Pos)
108 #define CLKSRCR_XSOSCEN (0x1uL << SCUCG_CLKSRCR_XSOSCEN_Pos)
109 
110 // WT & LCD Clock Divider Selection Control (Divider 2)
111 /*
112 #define MCLK_64 0
113 #define MCLK_128 1
114 #define MCLK_256 2
115 #define MCLK_512 3
116 #define MCLK_1024 4
117 */
118 #define WLDIV_MCLK64 (SCUCG_SCDIVR1_WLDIV_MCLK64 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/64
119 #define WLDIV_MCLK128 (SCUCG_SCDIVR1_WLDIV_MCLK128 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/128
120 #define WLDIV_MCLK256 (SCUCG_SCDIVR1_WLDIV_MCLK256 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/256
121 #define WLDIV_MCLK512 (SCUCG_SCDIVR1_WLDIV_MCLK512 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/512
122 #define WLDIV_MCLK1024 (SCUCG_SCDIVR1_WLDIV_MCLK1024 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/1024
123 
124 // HCLK Divider Selection Control (Divider 0)
125 /*
126 #define MCLK_16 0
127 #define MCLK_8 1
128 #define MCLK_4 2
129 #define MCLK_2 3
130 #define MCLK_1 4
131 */
132 #define HDIV_MCLK16 (SCUCG_SCDIVR1_HDIV_MCLK16 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/16
133 #define HDIV_MCLK8 (SCUCG_SCDIVR1_HDIV_MCLK8 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/8
134 #define HDIV_MCLK4 (SCUCG_SCDIVR1_HDIV_MCLK4 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/4
135 #define HDIV_MCLK2 (SCUCG_SCDIVR1_HDIV_MCLK2 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/2
136 #define HDIV_MCLK1 (SCUCG_SCDIVR1_HDIV_MCLK1 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/1
137 
138 // SysTick Timer Clock Divider Selection Control (Divider 3)
139 /*
140 #define SCU_HCLK_1 0
141 #define SCU_HCLK_2 1
142 #define SCU_HCLK_4 2
143 #define SCU_HCLK_8 3
144 */
145 #define SYSTDIV_HCLK1 (SCUCG_SCDIVR2_SYSTDIV_HCLK1 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/1
146 #define SYSTDIV_HCLK2 (SCUCG_SCDIVR2_SYSTDIV_HCLK2 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/2
147 #define SYSTDIV_HCLK4 (SCUCG_SCDIVR2_SYSTDIV_HCLK4 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/4
148 #define SYSTDIV_HCLK8 (SCUCG_SCDIVR2_SYSTDIV_HCLK8 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/8
149 
150 // PCLK Divider Selection Control (Divider 1)
151 #define PDIV_HCLK1 (SCUCG_SCDIVR2_PDIV_HCLK1 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/1
152 #define PDIV_HCLK2 (SCUCG_SCDIVR2_PDIV_HCLK2 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/2
153 #define PDIV_HCLK4 (SCUCG_SCDIVR2_PDIV_HCLK4 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/4
154 #define PDIV_HCLK8 (SCUCG_SCDIVR2_PDIV_HCLK8 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/8
155 
156 // Clock Output Enable/Disable Control
157 /*
158 #define DIS_CLKOUT 0
159 #define EN_CLKOUT 1
160 */
161 #define CLKOEN_Disable SCUCG_CLKOCR_CLKOEN_Disable
162 #define CLKOEN_Enable SCUCG_CLKOCR_CLKOEN_Enable
163 
164 // Clock Output Polarity Selection Control
165 /*
166 #define POL_L (0x0uL << 6)
167 #define POL_H (0x1uL << 6)
168 */
169 #define POLSEL_Low (SCUCG_CLKOCR_POLSEL_Low << SCUCG_CLKOCR_POLSEL_Pos) // Low level during disable
170 #define POLSEL_High (SCUCG_CLKOCR_POLSEL_High << SCUCG_CLKOCR_POLSEL_Pos) // High level during disable
171 
172 // Clock Output Divider Selection Control
173 /*
174 #define CLKODIV_1 (0x0uL << 3)
175 #define CLKODIV_2 (0x1uL << 3)
176 #define CLKODIV_4 (0x2uL << 3)
177 #define CLKODIV_8 (0x3uL << 3)
178 #define CLKODIV_16 (0x4uL << 3)
179 #define CLKODIV_32 (0x5uL << 3)
180 #define CLKODIV_64 (0x6uL << 3)
181 #define CLKODIV_128 (0x7uL << 3)
182 */
183 #define CLKODIV_SelectedClock1 (SCUCG_CLKOCR_CLKODIV_SelectedClock1 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/1
184 #define CLKODIV_SelectedClock2 (SCUCG_CLKOCR_CLKODIV_SelectedClock2 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/2
185 #define CLKODIV_SelectedClock4 (SCUCG_CLKOCR_CLKODIV_SelectedClock4 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/4
186 #define CLKODIV_SelectedClock8 (SCUCG_CLKOCR_CLKODIV_SelectedClock8 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/8
187 #define CLKODIV_SelectedClock16 (SCUCG_CLKOCR_CLKODIV_SelectedClock16 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/16
188 #define CLKODIV_SelectedClock32 (SCUCG_CLKOCR_CLKODIV_SelectedClock32 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/32
189 #define CLKODIV_SelectedClock64 (SCUCG_CLKOCR_CLKODIV_SelectedClock64 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/64
190 #define CLKODIV_SelectedClock128 (SCUCG_CLKOCR_CLKODIV_SelectedClock128 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/128
191 
192 // Clock Output Target Selection Control
193 /*
194 #define MCLK_OUT (0x0uL << 0)
195 #define WDTRC_OUT (0x1uL << 0)
196 #define HIRC_OUT (0x2uL << 0)
197 #define HCLK_OUT (0x3uL << 0)
198 #define PCLK_OUT (0x4uL << 0)
199 */
200 #define CLKOS_MCLK (SCUCG_CLKOCR_CLKOS_MCLK << SCUCG_CLKOCR_CLKOS_Pos)
201 #define CLKOS_WDTRC (SCUCG_CLKOCR_CLKOS_WDTRC << SCUCG_CLKOCR_CLKOS_Pos)
202 #define CLKOS_HIRC (SCUCG_CLKOCR_CLKOS_HIRC << SCUCG_CLKOCR_CLKOS_Pos)
203 #define CLKOS_HCLK (SCUCG_CLKOCR_CLKOS_HCLK << SCUCG_CLKOCR_CLKOS_Pos)
204 #define CLKOS_PCLK (SCUCG_CLKOCR_CLKOS_PCLK << SCUCG_CLKOCR_CLKOS_Pos)
205 
206 // Clock Monitoring Action Selection Control
207 /*
208 #define FLAG_CHK_M (0x0uL << 5)
209 #define RST_GEN_M (0x1uL << 5)
210 #define SYS_CHG_M (0x2uL << 5)
211 */
212 #define MACTS_FlagChk (SCUCG_CMONCR_MACTS_FlagChk << SCUCG_CMONCR_MACTS_Pos)
213 #define MACTS_RstGen (SCUCG_CMONCR_MACTS_RstGen << SCUCG_CMONCR_MACTS_Pos)
214 #define MACTS_SysClkChg (SCUCG_CMONCR_MACTS_SysClkChg << SCUCG_CMONCR_MACTS_Pos)
215 
216 // Clock Monitoring Target Selection Control
217 /*
218 #define MCLK_MON (0x0uL << 0)
219 #define HIRC_MON (0x1uL << 0)
220 #define XMOSC_MON (0x2uL << 0)
221 #define XSOSC_MON (0x3uL << 0)
222 */
223 #define MONCS_MCLK (SCUCG_CMONCR_MONCS_MCLK << SCUCG_CMONCR_MONCS_Pos)
224 #define MONCS_HIRC (SCUCG_CMONCR_MONCS_HIRC << SCUCG_CMONCR_MONCS_Pos)
225 #define MONCS_XMOSC (SCUCG_CMONCR_MONCS_XMOSC << SCUCG_CMONCR_MONCS_Pos)
226 #define MONCS_XSOSC (SCUCG_CMONCR_MONCS_XSOSC << SCUCG_CMONCR_MONCS_Pos)
227 
228 // Peripheral Clock Enable Control 1
229 /*
230 #define PERI_PA (0x1uL << 0)
231 #define PERI_PB (0x1uL << 1)
232 #define PERI_PC (0x1uL << 2)
233 #define PERI_PD (0x1uL << 3)
234 #define PERI_PE (0x1uL << 4)
235 #define PERI_PF (0x1uL << 5)
236 #define PERI_T10 (0x1uL << 16)
237 #define PERI_T11 (0x1uL << 17)
238 #define PERI_T12 (0x1uL << 18)
239 #define PERI_T30 (0x1uL << 19)
240 #define PERI_T20 (0x1uL << 20)
241 #define PERI_T21 (0x1uL << 21)
242 */
243 #define PPCLKEN1_T21CLKE (0x1uL << SCUCG_PPCLKEN1_T21CLKE_Pos)
244 #define PPCLKEN1_T20CLKE (0x1uL << SCUCG_PPCLKEN1_T20CLKE_Pos)
245 #define PPCLKEN1_T30CLKE (0x1uL << SCUCG_PPCLKEN1_T30CLKE_Pos)
246 #define PPCLKEN1_T12CLKE (0x1uL << SCUCG_PPCLKEN1_T12CLKE_Pos)
247 #define PPCLKEN1_T11CLKE (0x1uL << SCUCG_PPCLKEN1_T11CLKE_Pos)
248 #define PPCLKEN1_T10CLKE (0x1uL << SCUCG_PPCLKEN1_T10CLKE_Pos)
249 #define PPCLKEN1_PFCLKE (0x1uL << SCUCG_PPCLKEN1_PFCLKE_Pos)
250 #define PPCLKEN1_PECLKE (0x1uL << SCUCG_PPCLKEN1_PECLKE_Pos)
251 #define PPCLKEN1_PDCLKE (0x1uL << SCUCG_PPCLKEN1_PDCLKE_Pos)
252 #define PPCLKEN1_PCCLKE (0x1uL << SCUCG_PPCLKEN1_PCCLKE_Pos)
253 #define PPCLKEN1_PBCLKE (0x1uL << SCUCG_PPCLKEN1_PBCLKE_Pos)
254 #define PPCLKEN1_PACLKE (0x1uL << SCUCG_PPCLKEN1_PACLKE_Pos)
255 
256 // Peripheral Clock Enable Control 2
257 /*
258 #define PERI_UST10 (0x1uL << 0)
259 #define PERI_UST11 (0x1uL << 1)
260 #define PERI_UT0 (0x1uL << 2)
261 #define PERI_UT1 (0x1uL << 3)
262 #define PERI_I2C0 (0x1uL << 6)
263 #define PERI_I2C1 (0x1uL << 7)
264 #define PERI_ADC (0x1uL << 10)
265 #define PERI_CRC (0x1uL << 12)
266 #define PERI_LCD (0x1uL << 13)
267 #define PERI_WT (0x1uL << 16)
268 #define PERI_WDT (0x1uL << 17)
269 #define PERI_LVI (0x1uL << 18)
270 #define PERI_FMC (0x1uL << 19)
271 */
272 #define PPCLKEN2_FMCLKE (0x1uL << SCUCG_PPCLKEN2_FMCLKE_Pos)
273 #define PPCLKEN2_LVICLKE (0x1uL << SCUCG_PPCLKEN2_LVICLKE_Pos)
274 #define PPCLKEN2_WDTCLKE (0x1uL << SCUCG_PPCLKEN2_WDTCLKE_Pos)
275 #define PPCLKEN2_WTCLKE (0x1uL << SCUCG_PPCLKEN2_WTCLKE_Pos)
276 #define PPCLKEN2_LCDCLKE (0x1uL << SCUCG_PPCLKEN2_LCDCLKE_Pos)
277 #define PPCLKEN2_CRCLKE (0x1uL << SCUCG_PPCLKEN2_CRCLKE_Pos)
278 #define PPCLKEN2_ADCLKE (0x1uL << SCUCG_PPCLKEN2_ADCLKE_Pos)
279 #define PPCLKEN2_I2C1CLKE (0x1uL << SCUCG_PPCLKEN2_I2C1CLKE_Pos)
280 #define PPCLKEN2_I2C0CLKE (0x1uL << SCUCG_PPCLKEN2_I2C0CLKE_Pos)
281 #define PPCLKEN2_UT1CLKE (0x1uL << SCUCG_PPCLKEN2_UT1CLKE_Pos)
282 #define PPCLKEN2_UT0CLKE (0x1uL << SCUCG_PPCLKEN2_UT0CLKE_Pos)
283 #define PPCLKEN2_UST11CLKE (0x1uL << SCUCG_PPCLKEN2_UST11CLKE_Pos)
284 #define PPCLKEN2_UST10CLKE (0x1uL << SCUCG_PPCLKEN2_UST10CLKE_Pos)
285 
286 // Peripheral Clock Enable/Disable Control
287 /*
288 #define DIS_PERICLK 0
289 #define EN_PERICLK 1
290 */
291 #define PPxCLKE_Disable SCUCG_PPCLKEN1_PACLKE_Disable
292 #define PPxCLKE_Enable SCUCG_PPCLKEN1_PACLKE_Enable
293 
294 // Timer/Counter 20 Clock Selecion Control
295 /*
296 #define SCUCG_T20CLK (SCUCG_PPCLKSR_T20CLK_Msk)
297 #define SCUCG_T20CLK_XSOSC (0x0uL << SCUCG_PPCLKSR_T20CLK_Pos)
298 #define SCUCG_T20CLK_PCLK (0x1uL << SCUCG_PPCLKSR_T20CLK_Pos)
299 */
300 #define PPCLKSR_T20CLK (SCUCG_PPCLKSR_T20CLK_Msk)
301 #define T20CLK_XSOSC (SCUCG_PPCLKSR_T20CLK_XSOSC << SCUCG_PPCLKSR_T20CLK_Pos)
302 #define T20CLK_PCLK (SCUCG_PPCLKSR_T20CLK_PCLK << SCUCG_PPCLKSR_T20CLK_Pos)
303 
304 // Timer/Counter 30 Clock Selection Control
305 /*
306 #define SCUCG_T30CLK (SCUCG_PPCLKSR_T30CLK_Msk)
307 #define SCUCG_T30CLK_MCLK (0x0uL << SCUCG_PPCLKSR_T30CLK_Pos)
308 #define SCUCG_T30CLK_PCLK (0x1uL << SCUCG_PPCLKSR_T30CLK_Pos)
309 */
310 #define PPCLKSR_T30CLK (SCUCG_PPCLKSR_T30CLK_Msk)
311 #define T30CLK_MCLK (SCUCG_PPCLKSR_T30CLK_MCLK << SCUCG_PPCLKSR_T30CLK_Pos)
312 #define T30CLK_PCLK (SCUCG_PPCLKSR_T30CLK_PCLK << SCUCG_PPCLKSR_T30CLK_Pos)
313 
314 // LCD Driver Clock Selection Control
315 /*
316 #define SCUCG_LCDCLK (SCUCG_PPCLKSR_LCDCLK_Msk)
317 #define SCUCG_LCDCLK_MCLK (0x0uL << SCUCG_PPCLKSR_LCDCLK_Pos)
318 #define SCUCG_LCDCLK_XSOSC (0x1uL << SCUCG_PPCLKSR_LCDCLK_Pos)
319 #define SCUCG_LCDCLK_WDTRC (0x2uL << SCUCG_PPCLKSR_LCDCLK_Pos)
320 */
321 #define PPCLKSR_LCDCLK (SCUCG_PPCLKSR_LCDCLK_Msk)
322 #define LCDCLK_DividedMCLK (SCUCG_PPCLKSR_LCDCLK_DividedMCLK << SCUCG_PPCLKSR_LCDCLK_Pos)
323 #define LCDCLK_XSOSC (SCUCG_PPCLKSR_LCDCLK_XSOSC << SCUCG_PPCLKSR_LCDCLK_Pos)
324 #define LCDCLK_WDTRC (SCUCG_PPCLKSR_LCDCLK_WDTRC << SCUCG_PPCLKSR_LCDCLK_Pos)
325 
326 // Watch Timer Clock Selection Control
327 /*
328 #define SCUCG_WTCLK (SCUCG_PPCLKSR_WTCLK_Msk)
329 #define SCUCG_WTCLK_MCLK (0x0uL << SCUCG_PPCLKSR_WTCLK_Pos)
330 #define SCUCG_WTCLK_XSOSC (0x1uL << SCUCG_PPCLKSR_WTCLK_Pos)
331 #define SCUCG_WTCLK_WDTRC (0x2uL << SCUCG_PPCLKSR_WTCLK_Pos)
332 */
333 #define PPCLKSR_WTCLK (SCUCG_PPCLKSR_WTCLK_Msk)
334 #define WTCLK_DividedMCLK (SCUCG_PPCLKSR_WTCLK_DividedMCLK << SCUCG_PPCLKSR_WTCLK_Pos)
335 #define WTCLK_XSOSC (SCUCG_PPCLKSR_WTCLK_XSOSC << SCUCG_PPCLKSR_WTCLK_Pos)
336 #define WTCLK_WDTRC (SCUCG_PPCLKSR_WTCLK_WDTRC << SCUCG_PPCLKSR_WTCLK_Pos)
337 
338 // Watch-Dog Timer Clock Selection Control
339 /*
340 #define SCUCG_WDTCLK (SCUCG_PPCLKSR_WDTCLK_Msk)
341 #define SCUCG_WDTCLK_WDTRC (0x0uL << SCUCG_PPCLKSR_WDTCLK_Pos)
342 #define SCUCG_WDTCLK_PCLK (0x1uL << SCUCG_PPCLKSR_WDTCLK_Pos)
343 */
344 #define PPCLKSR_WDTCLK (SCUCG_PPCLKSR_WDTCLK_Msk)
345 #define WDTCLK_WDTRC (SCUCG_PPCLKSR_WDTCLK_WDTRC << SCUCG_PPCLKSR_WDTCLK_Pos)
346 #define WDTCLK_PCLK (SCUCG_PPCLKSR_WDTCLK_PCLK << SCUCG_PPCLKSR_WDTCLK_Pos)
347 
348 // Peripheral Reset Control 1
349 #define PPRST1_T21RST (0x1uL << SCUCG_PPRST1_T21RST_Pos)
350 #define PPRST1_T20RST (0x1uL << SCUCG_PPRST1_T20RST_Pos)
351 #define PPRST1_T30RST (0x1uL << SCUCG_PPRST1_T30RST_Pos)
352 #define PPRST1_T12RST (0x1uL << SCUCG_PPRST1_T12RST_Pos)
353 #define PPRST1_T11RST (0x1uL << SCUCG_PPRST1_T11RST_Pos)
354 #define PPRST1_T10RST (0x1uL << SCUCG_PPRST1_T10RST_Pos)
355 #define PPRST1_PFRST (0x1uL << SCUCG_PPRST1_PFRST_Pos)
356 #define PPRST1_PERST (0x1uL << SCUCG_PPRST1_PERST_Pos)
357 #define PPRST1_PDRST (0x1uL << SCUCG_PPRST1_PDRST_Pos)
358 #define PPRST1_PCRST (0x1uL << SCUCG_PPRST1_PCRST_Pos)
359 #define PPRST1_PBRST (0x1uL << SCUCG_PPRST1_PBRST_Pos)
360 #define PPRST1_PARST (0x1uL << SCUCG_PPRST1_PARST_Pos)
361 
362 // Peripheral Reset Control 2
363 #define PPRST2_FMCRST (0x1uL << SCUCG_PPRST2_FMCRST_Pos)
364 #define PPRST2_LVIRST (0x1uL << SCUCG_PPRST2_LVIRST_Pos)
365 #define PPRST2_WTRST (0x1uL << SCUCG_PPRST2_WTRST_Pos)
366 #define PPRST2_LCDRST (0x1uL << SCUCG_PPRST2_LCDRST_Pos)
367 #define PPRST2_CRRST (0x1uL << SCUCG_PPRST2_CRRST_Pos)
368 #define PPRST2_ADRST (0x1uL << SCUCG_PPRST2_ADRST_Pos)
369 #define PPRST2_I2C1RST (0x1uL << SCUCG_PPRST2_I2C1RST_Pos)
370 #define PPRST2_I2C0RST (0x1uL << SCUCG_PPRST2_I2C0RST_Pos)
371 #define PPRST2_UT1RST (0x1uL << SCUCG_PPRST2_UT1RST_Pos)
372 #define PPRST2_UT0RST (0x1uL << SCUCG_PPRST2_UT0RST_Pos)
373 #define PPRST2_UST11RST (0x1uL << SCUCG_PPRST2_UST11RST_Pos)
374 #define PPRST2_UST10RST (0x1uL << SCUCG_PPRST2_UST10RST_Pos)
375 
376 // External Main Oscillator Filter Selection Control
377 /*
378 #define XTAL_4DOT5MHZ (0x0 << 0)
379 #define XTAL_6DOT5MHZ (0x1 << 0)
380 #define XTAL_8DOT5MHZ (0x2 << 0)
381 #define XTAL_10DOT5MHZ (0x3 << 0)
382 #define XTAL_12DOT5MHZ (0x4 << 0)
383 #define XTAL_16DOT5MHZ (0x5 << 0)
384 */
385 #define XRNS_LE4p5MHz (SCUCG_XTFLSR_XRNS_LE4p5MHz << SCUCG_XTFLSR_XRNS_Pos) // x-tal LE 4.5MHz
386 #define XRNS_LE6p5MHz (SCUCG_XTFLSR_XRNS_LE6p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 4.5MHz GT x-tal LE 6.5MHz
387 #define XRNS_LE8p5MHz (SCUCG_XTFLSR_XRNS_LE8p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 6.5MHz GT x-tal LE 8.5MHz
388 #define XRNS_LE10p5MHz (SCUCG_XTFLSR_XRNS_LE10p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 8.5MHz GT x-tal LE 10.5MHz
389 #define XRNS_LE12p5MHz (SCUCG_XTFLSR_XRNS_LE12p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 10.5MHz GT x-tal LE 12.5MHz
390 #define XRNS_LE16p5MHz (SCUCG_XTFLSR_XRNS_LE16p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 12.5MHz GT x-tal LE 16.5MHz
391 
392 //******************************************************************************
393 // Macro
394 //******************************************************************************
395 
396 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
400 #define SCUCC_GetVendorID() (SCUCC->VENDORID)
401 #define SCUCC_GetChipID() (SCUCC->CHIPID)
402 #define SCUCC_GetRevNo() (SCUCC->REVNR)
403 
404 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
411 #define SCUCC_SetBtFnc(rst_src) (SCUCC->BTPSCR_b.BFIND = rst_src)
412 
413 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
417 #define SCUCC_GetBtPinSt() (SCUCC->BTPSCR_b.BTPSTA)
418 
419 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
423 #define SCUCC_EnNMI() (SCUCC->NMISRCR_b.NMICON = 1)
424 #define SCUCC_DisNMI() (SCUCC->NMISRCR_b.NMICON = 0)
425 
426 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
430 #define SCUCC_GenSwRst() (SCUCC->SWRSTR = ((uint32_t)SCUCC_SWRSTR_WTIDKY_Value << SCUCC_SWRSTR_WTIDKY_Pos) | 0x2DuL)
431 
432 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
436 #define SCUCC_EnWutInt() (SCUCC->WUTCR_b.WUTIEN = 1)
437 #define SCUCC_DisWutInt() (SCUCC->WUTCR_b.WUTIEN = 0)
438 
439 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
443 #define SCUCC_GetWutFlag() (SCUCC->WUTCR_b.WUTIFLAG)
444 #define SCUCC_ClrWutFlag() (SCUCC->WUTCR_b.WUTIFLAG = 1)
445 
446 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
450 #define SCUCC_ReloadWut() (SCUCC->WUTCR_b.CNTRLD = 1)
451 
452 
453 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
462 #define SCUCG_SetHCLK( scu_hdiv ) (SCUCG->SCDIVR1_b.HDIV = scu_hdiv)
463 #define SCUCG_SetPCLK( scu_pdiv ) (SCUCG->SCDIVR2_b.PDIV = scu_pdiv)
464 #define SCUCG_SetWtLcd( scu_wldiv ) (SCUCG->SCDIVR1_b.WLDIV = scu_wldiv)
465 #define SCUCG_SetSysTick( scu_systdiv ) (SCUCG->SCDIVR2_b.SYSTDIV = scu_systdiv)
466 
467 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
473 #define SCUCG_SetClkOutReg( u32Clko ) (SCUCG->CLKOCR = u32Clko)
474 
475 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
479 #define SCUCG_GetMonFlag() (SCUCG->CMONCR_b.MONFLAG)
480 
481 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
487 #define SCUCG_SetT20ClkSrc( clk ) (SCUCG->PPCLKSR_b.T20CLK = clk)
488 
489 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
495 #define SCUCG_SetT30ClkSrc( clk ) (SCUCG->PPCLKSR_b.T30CLK = clk)
496 
497 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
503 #define SCUCG_SetLcdClk( clk ) (SCUCG->PPCLKSR_b.LCDCLK = clk)
504 
505 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
511 #define SCUCG_SetWtClk( clk ) (SCUCG->PPCLKSR_b.WTCLK = clk)
512 
513 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
519 #define SCUCG_SetWdtClk( clk ) (SCUCG->PPCLKSR_b.WDTCLK = clk)
520 
521 //******************************************************************************
522 // Function
523 //******************************************************************************
524 
525 uint32_t HAL_SCU_ResetSourceStatus( void );
526 void HAL_SCU_SetNMI( uint32_t u32NmiCon );
527 void HAL_SCU_SoftwareReset_Config( void );
528 void HAL_SCU_SetWakupData( uint32_t u32Data );
529 void HAL_SCU_HIRCTRM_ClockConfig( uint32_t u32Ind );
530 void HAL_SCU_WDTRCTRM_ClockConfig( uint32_t u32Ind );
531 
532 
533 void HAL_SCU_ClockMonitoring( uint32_t u32Acts, uint32_t u32Target );
535 void HAL_SCU_ClockSource_Config( uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc );
536 void HAL_SCU_ClockSource_Enable( uint32_t u32ClkSrc, uint32_t u32HircDiv );
537 void HAL_SCU_ClockSource_Disable( uint32_t u32ClkSrc );
538 void HAL_SCU_SystemClockChange( uint32_t u32Target );
539 void HAL_SCU_MainXtal_PinConfig( uint32_t u32XtalFilter );
540 void HAL_SCU_SubXtal_PinConfig( void );
541 void HAL_SCU_SystemClockDivider( uint32_t u32Div02, uint32_t u32Div13 );
542 void HAL_SCU_CLKO_PinConfig( void );
543 void HAL_SCU_ClockOutput( uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div );
544 void HAL_SCU_Peripheral_ClockConfig( uint32_t u32PeriClk1, uint32_t u32PeriClk2 );
545 void HAL_SCU_Peripheral_EnableClock1( uint32_t u32PeriClk1, uint32_t Ind );
546 void HAL_SCU_Peripheral_EnableClock2( uint32_t u32PeriClk2, uint32_t u32Ind );
547 void HAL_SCU_Peripheral_ResetConfig( uint32_t u32PeriRst1, uint32_t u32PeriRst2 );
548 void HAL_SCU_Peripheral_SetReset1( uint32_t u32EachPeri1 );
549 void HAL_SCU_Peripheral_SetReset2( uint32_t u32EachPeri2 );
550 void HAL_SCU_Peripheral_ClockSelection( uint32_t u32Peri, uint32_t u32ClkSrc );
551 
552 #ifdef __cplusplus
553 }
554 #endif
555 
556 #endif /* _SCU_H_ */
557 
void HAL_SCU_ClockSource_Enable(uint32_t u32ClkSrc, uint32_t u32HircDiv)
Enable Clock Source.
void HAL_SCU_SubXtal_PinConfig(void)
Set XSOSC Pins for x-tal.
void HAL_SCU_ClockMonitoring_Disable(void)
Disable Clock Monitoring.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_Peripheral_SetReset1(uint32_t u32EachPeri1)
Set/Reset Each Peripheral Block Reset of PPRST1 Register.
Contains the ABOV typedefs for C standard types. It is intended to be used in ISO C conforming develo...
void HAL_SCU_SetWakupData(uint32_t u32Data)
Set Wake-Up Timer Data.
void HAL_SCU_SoftwareReset_Config(void)
Check whether system reset ok or not. Generate s/w reset if a weak reset.
void HAL_SCU_HIRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of HIRC by one step.
void HAL_SCU_ClockOutput(uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
Set Configuration for Clock Output.
uint32_t HAL_SCU_ResetSourceStatus(void)
Get Reset Source Status.
void HAL_SCU_MainXtal_PinConfig(uint32_t u32XtalFilter)
Set XMOSC Pins for x-tal.
void HAL_SCU_Peripheral_ClockConfig(uint32_t u32PeriClk1, uint32_t u32PeriClk2)
Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".
void HAL_SCU_SystemClockDivider(uint32_t u32Div02, uint32_t u32Div13)
Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick T...
void HAL_SCU_ClockSource_Disable(uint32_t u32ClkSrc)
Disable Clock Source.
void HAL_SCU_Peripheral_ClockSelection(uint32_t u32Peri, uint32_t u32ClkSrc)
Peripheral Clock Selection of PPCLKSR Register.
void HAL_SCU_SetNMI(uint32_t u32NmiCon)
Set Non-Maskable Interrupt(NMI) Source Selection Register.
void HAL_SCU_CLKO_PinConfig(void)
Set CLKO Pin for Clock Output.
void HAL_SCU_ClockSource_Config(uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
Set Clock Source, HIRC Frequency, and type of XMOSC.
void HAL_SCU_ClockMonitoring(uint32_t u32Acts, uint32_t u32Target)
Configure Clock Monitoring.
void HAL_SCU_SystemClockChange(uint32_t u32Target)
Change System Clock.
void HAL_SCU_Peripheral_ResetConfig(uint32_t u32PeriRst1, uint32_t u32PeriRst2)
Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_WDTRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of WDTRC by one step.