A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G11x_hal_scu.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31G11x_hal_scu.h"
41 
42 /* Public Functions --------------------------------------------------------- */
43 //******************************************************************************
44 // Function
45 //******************************************************************************
46 
47 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
52 uint32_t HAL_SCU_ResetSourceStatus( void )
53 {
54  uint32_t tmp;
55 
56  tmp = SCUCC->RSTSSR; // Get reset source status
57  SCUCC->RSTSSR = 0x3FuL; // Clear all reset source status
58  return tmp;
59 }
60 
61 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
68 void HAL_SCU_SetNMI( uint32_t u32NmiCon )
69 {
70  SCUCC->NMISRCR = u32NmiCon;
71 }
72 
73 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
79 {
80  if( SCUCC->SRSTVR_b.VALID != 0x55 )
81  {
82  SCUCC_GenSwRst(); // Generate S/W reset on invalid reset
83  }
84 }
85 
86 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
93 void HAL_SCU_SetWakupData( uint32_t u32Data )
94 {
95  SCUCC->WUTDR = u32Data; // On HCLK=40MHz, (150us x 40)/32 = 187.5. So, the data should be more than 187
96 }
97 
98 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
108 void HAL_SCU_HIRCTRM_ClockConfig( uint32_t u32Ind )
109 {
110  uint32_t tmp, ntrim;
111 
112  tmp = ( SCUCC->HIRCTRM ) & 0x001fuL; // Read current fine trim value of HIRC
113  if( u32Ind == HIRC_UP_ONESTEP ) // Increment by one step(about 140kHz)
114  {
115  if( tmp != 0x0f )
116  {
117  tmp++;
118  }
119  }
120  else // Decrement by one step(about 140kHz)
121  {
122  if( tmp != 0x10 )
123  {
124  tmp--;
125  }
126  }
127  tmp &= 0x1f; // Fine trim value is only 5-bits
128  tmp |= ( ( SCUCC->HIRCTRM ) & 0x00E0uL ); // Read Coarse trim value
129  ntrim = ( tmp << 8 ) ^ 0x0000FF00; // Make write complement key
130  SCUCC->HIRCTRM = ( ( uint32_t )SCUCC_HIRCTRM_WTIDKY_Value << SCUCC_HIRCTRM_WTIDKY_Pos ) // Write new HIRC trim value with write ID and complement key
131  | ntrim
132  | tmp;
133 }
134 
135 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
145 void HAL_SCU_WDTRCTRM_ClockConfig( uint32_t u32Ind )
146 {
147  uint32_t ctmp, ftmp, ntrim;
148 
149  ftmp = ( SCUCC->WDTRCTRM ) & 0x0007uL; // Read current fine trim value of WDTRC
150  ctmp = ( SCUCC->WDTRCTRM ) & 0x00F0uL; // Read current coarse trim value of WDTRC
151  if( u32Ind == WDTRC_UP_ONESTEP ) // Increment by one step(about 1.1kHz)
152  {
153  ftmp++;
154  ftmp &= 0x07uL; // Fine trim value is only 3-bits
155  if( ftmp == 0x04 )
156  {
157  if( ctmp != 0x70 )
158  {
159  ctmp += 0x10uL;
160  }
161  else
162  {
163  ftmp = 0x03uL;
164  }
165  }
166  }
167  else // Decrement by one step(about 1.1kHz)
168  {
169  ftmp--;
170  ftmp &= 0x07uL; // Fine trim value is only 3-bits
171  if( ftmp == 0x03 )
172  {
173  if( ctmp != 0x80 )
174  {
175  ctmp -= 0x10uL;
176  }
177  else
178  {
179  ftmp = 0x04uL;
180  }
181  }
182  }
183  ctmp &= 0x00f0uL; // Coarse trim value is only 4-bits
184  ctmp |= ftmp;
185  ntrim = ( ctmp << 8 ) ^ 0x0000FF00; // Make write complement key
186  SCUCC->WDTRCTRM = ( SCUCC_WDTRCTRM_WTIDKY_Value << SCUCC_WDTRCTRM_WTIDKY_Pos ) // Write new WDTRC trim value with write ID and complement key
187  | ntrim
188  | ctmp;
189 }
190 
191 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
202 void HAL_SCU_ClockMonitoring( uint32_t u32Acts, uint32_t u32Target )
203 {
204  if( SCUCG->CLKSRCR_b.WDTRCEN == 0 )
205  {
206  SCUCG->CLKSRCR = SCUCG->CLKSRCR
207  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
208  | CLKSRCR_WDTRCEN; // The WDTRC should be enabled to use clock monitoring
209  }
210  SCUCG->CMONCR = ( 0x3uL << 2 ) | u32Acts | u32Target; // Clear MONFLAG and NMINTFG, Set Monitoring Target and Monitoring Action
211  SCUCG->CMONCR_b.MONEN = 1; // Clock Monitoring Enable
212 }
213 
214 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
222 {
223  SCUCG->CMONCR_b.MACTS = 0; // Clear MACTS bits first
224  SCUCG->CMONCR_b.MONEN = 0; // Disable clock monitoring function
225 }
226 
227 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
244 void HAL_SCU_ClockSource_Config( uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc )
245 {
246  uint32_t tmp;
247 
248  tmp = SCUCG->CLKSRCR & 0x0000000F;
249  tmp |= ( ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
250  | u32FreIRC // HIRC Frequency
251  | u32TypeXM // XMOSC type: x-tal or external clock
252  | u32ClkSrc );
253  SCUCG->CLKSRCR = tmp;
254 }
255 
256 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
273 void HAL_SCU_ClockSource_Enable( uint32_t u32ClkSrc, uint32_t u32HircDiv )
274 {
275 #if 0 // before bug fix
276  uint32_t tmp;
277 
278  tmp = SCUCG->CLKSRCR & 0x0000FFFF; // 0x00000fff°¡ ¿ÇÀ» µí...
279  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
280  tmp |= u32ClkSrc;
281  tmp |= u32HircDiv;
282  SCUCG->CLKSRCR = tmp;
283 #else // after bug fix
284  SCUCG->CLKSRCR = SCUCG->CLKSRCR
285  & ~( SCUCG_CLKSRCR_WTIDKY_Msk | SCUCG_CLKSRCR_HIRCSEL_Msk )
286  | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ) // Write ID
287  | u32HircDiv
288  | u32ClkSrc
289  ;
290 #endif
291 }
292 
293 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
307 void HAL_SCU_ClockSource_Disable( uint32_t u32ClkSrc )
308 {
309  uint32_t tmp;
310 
311  tmp = SCUCG->CLKSRCR & 0x0000FFFF;
312  tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos ); // Write ID
313  tmp &= ~u32ClkSrc;
314  SCUCG->CLKSRCR = tmp;
315 }
316 
317 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
326 void HAL_SCU_MainXtal_PinConfig( uint32_t u32XtalFilter )
327 {
328  PF->AFSR1 &= 0xFFFFFF00; // PF[1:0]: XIN/XOUT
329  PF->PUPD &= 0xFFF0; // PF[1:0]: Pull-up/down resistors Disable
330  PF->MOD &= 0xFFF0uL;
331  PF->MOD |= 0x000AuL; // PF[1:0]: Alternative Function
332  SCUCG->XTFLSR = ( ( uint32_t )SCUCG_XTFLSR_WTIDKY_Value << SCUCG_XTFLSR_WTIDKY_Pos ) // Write ID
333  | u32XtalFilter; // x-tal filter value
334 }
335 
336 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
342 {
343  PF->AFSR1 &= 0xFFFF00FF; // PF[3:2]: SXIN/SXOUT
344  PF->PUPD &= 0xFF0F; // PF[3:2]: Pull-up/down resistors Disable
345  PF->MOD &= 0xFF0FuL;
346  PF->MOD |= 0x00A0uL; // PF[3:2]: Alternative Function
347 }
348 
349 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
357 void HAL_SCU_SystemClockChange( uint32_t u32Target )
358 {
359  SCUCG->SCCR = ( SCUCG_SCCR_WTIDKY_Value << SCUCG_SCCR_WTIDKY_Pos ) // Write ID
360  | u32Target; // Target Clock Source
361 }
362 
363 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
380 void HAL_SCU_SystemClockDivider( uint32_t u32Div02, uint32_t u32Div13 )
381 {
382  // Divider 0 for HCLK: 000/001/010/011/100: MCLK is divided by 16/8/4/2/1
383  // Divider 2 for WT and LCD Driver: 000/001/010/011/100: MCLK is divided by 64/128/256/512/1024
384  SCUCG->SCDIVR1 = u32Div02;
385 
386  // Divider 1 for PCLK: 00/01/10/11: HCLK is divided by 1/2/4/8
387  // Divider 3 for SysTick Timer: 00/01/10/11: HCLK is divided by 1/2/4/8
388  SCUCG->SCDIVR2 = u32Div13;
389 }
390 
391 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
397 {
398  PF->AFSR1 &= 0xFFF0FFFF; // PF4 CLKO 0: CLKO 1: ---- 2: ---- 3: ---- 4: ----
399  PF->PUPD &= 0xFCFF; // PF4 CLKO 0: Disable Pull-Up/Down 1: Enable Pull-Up 2: Enable Pull-Down
400  PF->MOD &= 0xFCFFuL; // PF4 CLKO 0: Input Mode 1: Output Mode 2: Alternative Function Mode
401  PF->MOD |= 0x0200uL; // PF4 CLKO 0: Input Mode 1: Output Mode 2: Alternative Function Mode
402 }
403 
404 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
421 void HAL_SCU_ClockOutput( uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div )
422 {
423  SCUCG->CLKOCR = 0
424  | ( 1 << SCUCG_CLKOCR_CLKOEN_Pos ) // CLKO Enable
425  | u32Level // 0: Low Level 1: High Level
426  | u32Div // 0: div_1 1: div_2 2: div_4 3: div_8 4: div_16 5: div_32 6: div_64 7: div_128
427  | u32ClkSrc // 0: MCLK 1: WDTRC 2: HIRC 3: HCLK 4: PCLK
428  ;
429 }
430 
431 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
441 void HAL_SCU_Peripheral_ClockConfig( uint32_t u32PeriClk1, uint32_t u32PeriClk2 )
442 {
443  SCUCG->PPCLKEN1 = u32PeriClk1; // Set peripheral clock of timers and ports
444  SCUCG->PPCLKEN2 = u32PeriClk2; // Set peripheral clock of the others
445 }
446 
447 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
459 void HAL_SCU_Peripheral_EnableClock1( uint32_t u32PeriClk1, uint32_t Ind )
460 {
461  if( Ind )
462  {
463  SCUCG->PPCLKEN1 |= u32PeriClk1; // Enable a peripheral clock of timers and ports
464  }
465  else
466  {
467  SCUCG->PPCLKEN1 &= ~u32PeriClk1; // Disable a peripheral clock of timers and ports
468  }
469 }
470 
471 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
485 void HAL_SCU_Peripheral_EnableClock2( uint32_t u32PeriClk2, uint32_t u32Ind )
486 {
487  if( u32Ind )
488  {
489  SCUCG->PPCLKEN2 |= u32PeriClk2; // Enable a peripheral clock of others
490  }
491  else
492  {
493  SCUCG->PPCLKEN2 &= ~u32PeriClk2; // Disable a peripheral clock of others
494  }
495 }
496 
497 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
507 void HAL_SCU_Peripheral_ResetConfig( uint32_t u32PeriRst1, uint32_t u32PeriRst2 )
508 {
509  uint32_t i;
510 
511  SCUCG->PPRST1 = u32PeriRst1; // Reset peripheral block of timers and ports if the corresponding bit is "1b"
512  SCUCG->PPRST2 = u32PeriRst2; // Reset peripheral block of the others
513  for( i = 0 ; i < 10 ; i++ )
514  {
515  NOP();
516  }
517  SCUCG->PPRST1 = 0x0uL; // Clear the peripheral reset bits
518  SCUCG->PPRST2 = 0x0uL;
519 }
520 
521 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
529 void HAL_SCU_Peripheral_SetReset1( uint32_t u32EachPeri1 )
530 {
531  uint32_t i;
532 
533  SCUCG->PPRST1 = u32EachPeri1; // Reset a peripheral block
534  for( i = 0 ; i < 10 ; i++ )
535  {
536  NOP();
537  }
538  SCUCG->PPRST1 = 0; // Clear the peripheral reset bit
539 }
540 
541 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
550 void HAL_SCU_Peripheral_SetReset2( uint32_t u32EachPeri2 )
551 {
552  uint32_t i;
553 
554  SCUCG->PPRST2 = u32EachPeri2; // Reset a peripheral block
555  for( i = 0 ; i < 10 ; i++ )
556  {
557  NOP();
558  }
559  SCUCG->PPRST2 = 0; // Clear the peripheral reset bit
560 }
561 
562 
563 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
577 void HAL_SCU_Peripheral_ClockSelection( uint32_t u32Peri, uint32_t u32ClkSrc )
578 {
579  SCUCG->PPCLKSR &= ~u32Peri;
580  SCUCG->PPCLKSR |= u32ClkSrc;
581 }
582 
void HAL_SCU_SoftwareReset_Config(void)
Check whether system reset ok or not. Generate s/w reset if a weak reset.
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
void HAL_SCU_SetWakupData(uint32_t u32Data)
Set Wake-Up Timer Data.
void HAL_SCU_SystemClockChange(uint32_t u32Target)
Change System Clock.
void HAL_SCU_ClockSource_Config(uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
Set Clock Source, HIRC Frequency, and type of XMOSC.
void HAL_SCU_Peripheral_ResetConfig(uint32_t u32PeriRst1, uint32_t u32PeriRst2)
Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".
void HAL_SCU_SetNMI(uint32_t u32NmiCon)
Set Non-Maskable Interrupt(NMI) Source Selection Register.
void HAL_SCU_WDTRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of WDTRC by one step.
void HAL_SCU_SubXtal_PinConfig(void)
Set XSOSC Pins for x-tal.
void HAL_SCU_ClockSource_Disable(uint32_t u32ClkSrc)
Disable Clock Source.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_ClockOutput(uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
Set Configuration for Clock Output.
void HAL_SCU_ClockMonitoring(uint32_t u32Acts, uint32_t u32Target)
Configure Clock Monitoring.
void HAL_SCU_MainXtal_PinConfig(uint32_t u32XtalFilter)
Set XMOSC Pins for x-tal.
void HAL_SCU_CLKO_PinConfig(void)
Set CLKO Pin for Clock Output.
void HAL_SCU_Peripheral_ClockSelection(uint32_t u32Peri, uint32_t u32ClkSrc)
Peripheral Clock Selection of PPCLKSR Register.
uint32_t HAL_SCU_ResetSourceStatus(void)
Get Reset Source Status.
void HAL_SCU_ClockSource_Enable(uint32_t u32ClkSrc, uint32_t u32HircDiv)
Enable Clock Source.
void HAL_SCU_HIRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of HIRC by one step.
void HAL_SCU_SystemClockDivider(uint32_t u32Div02, uint32_t u32Div13)
Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick T...
void HAL_SCU_Peripheral_SetReset1(uint32_t u32EachPeri1)
Set/Reset Each Peripheral Block Reset of PPRST1 Register.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_Peripheral_ClockConfig(uint32_t u32PeriClk1, uint32_t u32PeriClk2)
Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".
void HAL_SCU_ClockMonitoring_Disable(void)
Disable Clock Monitoring.
Contains all macro definitions and function prototypes support for scu firmware library on A31G11x.