54 #define BFIND_PORorEXTR SCUCC_BTPSCR_BFIND_PORorEXTR 55 #define BFIND_POR SCUCC_BTPSCR_BFIND_POR 58 #define HIRC_UP_ONESTEP 0 59 #define HIRC_DOWN_ONESTEP 1 62 #define WDTRC_UP_ONESTEP 0 63 #define WDTRC_DOWN_ONESTEP 1 73 #define MCLKSEL_HIRC (SCUCG_SCCR_MCLKSEL_HIRC << SCUCG_SCCR_MCLKSEL_Pos) 74 #define MCLKSEL_XMOSC (SCUCG_SCCR_MCLKSEL_XMOSC << SCUCG_SCCR_MCLKSEL_Pos) 75 #define MCLKSEL_XSOSC (SCUCG_SCCR_MCLKSEL_XSOSC << SCUCG_SCCR_MCLKSEL_Pos) 76 #define MCLKSEL_WDTRC (SCUCG_SCCR_MCLKSEL_WDTRC << SCUCG_SCCR_MCLKSEL_Pos) 85 #define HIRCSEL_HIRC1 (SCUCG_CLKSRCR_HIRCSEL_HIRC1 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 40MHz HIRC 86 #define HIRCSEL_HIRC2 (SCUCG_CLKSRCR_HIRCSEL_HIRC2 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 20MHz HIRC 87 #define HIRCSEL_HIRC4 (SCUCG_CLKSRCR_HIRCSEL_HIRC4 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 10MHz HIRC 88 #define HIRCSEL_HIRC8 (SCUCG_CLKSRCR_HIRCSEL_HIRC8 << SCUCG_CLKSRCR_HIRCSEL_Pos) // 5MHz HIRC 95 #define XMFRNG_Xtal (SCUCG_CLKSRCR_XMFRNG_Xtal << SCUCG_CLKSRCR_XMFRNG_Pos) 96 #define XMFRNG_Clock (SCUCG_CLKSRCR_XMFRNG_Clock << SCUCG_CLKSRCR_XMFRNG_Pos) 105 #define CLKSRCR_WDTRCEN (0x1uL << SCUCG_CLKSRCR_WDTRCEN_Pos) 106 #define CLKSRCR_HIRCEN (0x1uL << SCUCG_CLKSRCR_HIRCEN_Pos) 107 #define CLKSRCR_XMOSCEN (0x1uL << SCUCG_CLKSRCR_XMOSCEN_Pos) 108 #define CLKSRCR_XSOSCEN (0x1uL << SCUCG_CLKSRCR_XSOSCEN_Pos) 118 #define WLDIV_MCLK64 (SCUCG_SCDIVR1_WLDIV_MCLK64 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/64 119 #define WLDIV_MCLK128 (SCUCG_SCDIVR1_WLDIV_MCLK128 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/128 120 #define WLDIV_MCLK256 (SCUCG_SCDIVR1_WLDIV_MCLK256 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/256 121 #define WLDIV_MCLK512 (SCUCG_SCDIVR1_WLDIV_MCLK512 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/512 122 #define WLDIV_MCLK1024 (SCUCG_SCDIVR1_WLDIV_MCLK1024 << SCUCG_SCDIVR1_WLDIV_Pos) // MCLK/1024 132 #define HDIV_MCLK16 (SCUCG_SCDIVR1_HDIV_MCLK16 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/16 133 #define HDIV_MCLK8 (SCUCG_SCDIVR1_HDIV_MCLK8 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/8 134 #define HDIV_MCLK4 (SCUCG_SCDIVR1_HDIV_MCLK4 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/4 135 #define HDIV_MCLK2 (SCUCG_SCDIVR1_HDIV_MCLK2 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/2 136 #define HDIV_MCLK1 (SCUCG_SCDIVR1_HDIV_MCLK1 << SCUCG_SCDIVR1_HDIV_Pos) // MCLK/1 145 #define SYSTDIV_HCLK1 (SCUCG_SCDIVR2_SYSTDIV_HCLK1 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/1 146 #define SYSTDIV_HCLK2 (SCUCG_SCDIVR2_SYSTDIV_HCLK2 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/2 147 #define SYSTDIV_HCLK4 (SCUCG_SCDIVR2_SYSTDIV_HCLK4 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/4 148 #define SYSTDIV_HCLK8 (SCUCG_SCDIVR2_SYSTDIV_HCLK8 << SCUCG_SCDIVR2_SYSTDIV_Pos) // HCLK/8 151 #define PDIV_HCLK1 (SCUCG_SCDIVR2_PDIV_HCLK1 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/1 152 #define PDIV_HCLK2 (SCUCG_SCDIVR2_PDIV_HCLK2 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/2 153 #define PDIV_HCLK4 (SCUCG_SCDIVR2_PDIV_HCLK4 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/4 154 #define PDIV_HCLK8 (SCUCG_SCDIVR2_PDIV_HCLK8 << SCUCG_SCDIVR2_PDIV_Pos) // HCLK/8 161 #define CLKOEN_Disable SCUCG_CLKOCR_CLKOEN_Disable 162 #define CLKOEN_Enable SCUCG_CLKOCR_CLKOEN_Enable 169 #define POLSEL_Low (SCUCG_CLKOCR_POLSEL_Low << SCUCG_CLKOCR_POLSEL_Pos) // Low level during disable 170 #define POLSEL_High (SCUCG_CLKOCR_POLSEL_High << SCUCG_CLKOCR_POLSEL_Pos) // High level during disable 183 #define CLKODIV_SelectedClock1 (SCUCG_CLKOCR_CLKODIV_SelectedClock1 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/1 184 #define CLKODIV_SelectedClock2 (SCUCG_CLKOCR_CLKODIV_SelectedClock2 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/2 185 #define CLKODIV_SelectedClock4 (SCUCG_CLKOCR_CLKODIV_SelectedClock4 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/4 186 #define CLKODIV_SelectedClock8 (SCUCG_CLKOCR_CLKODIV_SelectedClock8 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/8 187 #define CLKODIV_SelectedClock16 (SCUCG_CLKOCR_CLKODIV_SelectedClock16 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/16 188 #define CLKODIV_SelectedClock32 (SCUCG_CLKOCR_CLKODIV_SelectedClock32 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/32 189 #define CLKODIV_SelectedClock64 (SCUCG_CLKOCR_CLKODIV_SelectedClock64 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/64 190 #define CLKODIV_SelectedClock128 (SCUCG_CLKOCR_CLKODIV_SelectedClock128 << SCUCG_CLKOCR_CLKODIV_Pos) // Selected Clock/128 200 #define CLKOS_MCLK (SCUCG_CLKOCR_CLKOS_MCLK << SCUCG_CLKOCR_CLKOS_Pos) 201 #define CLKOS_WDTRC (SCUCG_CLKOCR_CLKOS_WDTRC << SCUCG_CLKOCR_CLKOS_Pos) 202 #define CLKOS_HIRC (SCUCG_CLKOCR_CLKOS_HIRC << SCUCG_CLKOCR_CLKOS_Pos) 203 #define CLKOS_HCLK (SCUCG_CLKOCR_CLKOS_HCLK << SCUCG_CLKOCR_CLKOS_Pos) 204 #define CLKOS_PCLK (SCUCG_CLKOCR_CLKOS_PCLK << SCUCG_CLKOCR_CLKOS_Pos) 212 #define MACTS_FlagChk (SCUCG_CMONCR_MACTS_FlagChk << SCUCG_CMONCR_MACTS_Pos) 213 #define MACTS_RstGen (SCUCG_CMONCR_MACTS_RstGen << SCUCG_CMONCR_MACTS_Pos) 214 #define MACTS_SysClkChg (SCUCG_CMONCR_MACTS_SysClkChg << SCUCG_CMONCR_MACTS_Pos) 223 #define MONCS_MCLK (SCUCG_CMONCR_MONCS_MCLK << SCUCG_CMONCR_MONCS_Pos) 224 #define MONCS_HIRC (SCUCG_CMONCR_MONCS_HIRC << SCUCG_CMONCR_MONCS_Pos) 225 #define MONCS_XMOSC (SCUCG_CMONCR_MONCS_XMOSC << SCUCG_CMONCR_MONCS_Pos) 226 #define MONCS_XSOSC (SCUCG_CMONCR_MONCS_XSOSC << SCUCG_CMONCR_MONCS_Pos) 247 #define PPCLKEN1_T21CLKE (0x1uL << SCUCG_PPCLKEN1_T21CLKE_Pos) 248 #define PPCLKEN1_T20CLKE (0x1uL << SCUCG_PPCLKEN1_T20CLKE_Pos) 249 #define PPCLKEN1_T30CLKE (0x1uL << SCUCG_PPCLKEN1_T30CLKE_Pos) 250 #define PPCLKEN1_T12CLKE (0x1uL << SCUCG_PPCLKEN1_T12CLKE_Pos) 251 #define PPCLKEN1_T11CLKE (0x1uL << SCUCG_PPCLKEN1_T11CLKE_Pos) 252 #define PPCLKEN1_T10CLKE (0x1uL << SCUCG_PPCLKEN1_T10CLKE_Pos) 253 #define PPCLKEN1_T16CLKE (0x1uL << SCUCG_PPCLKEN1_T16CLKE_Pos) 254 #define PPCLKEN1_T15CLKE (0x1uL << SCUCG_PPCLKEN1_T15CLKE_Pos) 255 #define PPCLKEN1_T14CLKE (0x1uL << SCUCG_PPCLKEN1_T14CLKE_Pos) 256 #define PPCLKEN1_T13CLKE (0x1uL << SCUCG_PPCLKEN1_T13CLKE_Pos) 257 #define PPCLKEN1_PFCLKE (0x1uL << SCUCG_PPCLKEN1_PFCLKE_Pos) 258 #define PPCLKEN1_PECLKE (0x1uL << SCUCG_PPCLKEN1_PECLKE_Pos) 259 #define PPCLKEN1_PDCLKE (0x1uL << SCUCG_PPCLKEN1_PDCLKE_Pos) 260 #define PPCLKEN1_PCCLKE (0x1uL << SCUCG_PPCLKEN1_PCCLKE_Pos) 261 #define PPCLKEN1_PBCLKE (0x1uL << SCUCG_PPCLKEN1_PBCLKE_Pos) 262 #define PPCLKEN1_PACLKE (0x1uL << SCUCG_PPCLKEN1_PACLKE_Pos) 283 #define PPCLKEN2_FMCLKE (0x1uL << SCUCG_PPCLKEN2_FMCLKE_Pos) 284 #define PPCLKEN2_LVICLKE (0x1uL << SCUCG_PPCLKEN2_LVICLKE_Pos) 285 #define PPCLKEN2_WDTCLKE (0x1uL << SCUCG_PPCLKEN2_WDTCLKE_Pos) 286 #define PPCLKEN2_WTCLKE (0x1uL << SCUCG_PPCLKEN2_WTCLKE_Pos) 287 #define PPCLKEN2_LCDCLKE (0x1uL << SCUCG_PPCLKEN2_LCDCLKE_Pos) 288 #define PPCLKEN2_CRCLKE (0x1uL << SCUCG_PPCLKEN2_CRCLKE_Pos) 289 #define PPCLKEN2_ADCLKE (0x1uL << SCUCG_PPCLKEN2_ADCLKE_Pos) 290 #define PPCLKEN2_I2C2CLKE (0x1uL << SCUCG_PPCLKEN2_I2C2CLKE_Pos) 291 #define PPCLKEN2_I2C1CLKE (0x1uL << SCUCG_PPCLKEN2_I2C1CLKE_Pos) 292 #define PPCLKEN2_I2C0CLKE (0x1uL << SCUCG_PPCLKEN2_I2C0CLKE_Pos) 293 #define PPCLKEN2_UST13CLKE (0x1uL << SCUCG_PPCLKEN2_UST13CLKE_Pos) 294 #define PPCLKEN2_UST12CLKE (0x1uL << SCUCG_PPCLKEN2_UST12CLKE_Pos) 295 #define PPCLKEN2_UT1CLKE (0x1uL << SCUCG_PPCLKEN2_UT1CLKE_Pos) 296 #define PPCLKEN2_UT0CLKE (0x1uL << SCUCG_PPCLKEN2_UT0CLKE_Pos) 297 #define PPCLKEN2_UST11CLKE (0x1uL << SCUCG_PPCLKEN2_UST11CLKE_Pos) 298 #define PPCLKEN2_UST10CLKE (0x1uL << SCUCG_PPCLKEN2_UST10CLKE_Pos) 305 #define PPxCLKE_Disable SCUCG_PPCLKEN1_PACLKE_Disable 306 #define PPxCLKE_Enable SCUCG_PPCLKEN1_PACLKE_Enable 314 #define PPCLKSR_T20CLK (SCUCG_PPCLKSR_T20CLK_Msk) 315 #define T20CLK_XSOSC (SCUCG_PPCLKSR_T20CLK_XSOSC << SCUCG_PPCLKSR_T20CLK_Pos) 316 #define T20CLK_PCLK (SCUCG_PPCLKSR_T20CLK_PCLK << SCUCG_PPCLKSR_T20CLK_Pos) 324 #define PPCLKSR_T30CLK (SCUCG_PPCLKSR_T30CLK_Msk) 325 #define T30CLK_MCLK (SCUCG_PPCLKSR_T30CLK_MCLK << SCUCG_PPCLKSR_T30CLK_Pos) 326 #define T30CLK_PCLK (SCUCG_PPCLKSR_T30CLK_PCLK << SCUCG_PPCLKSR_T30CLK_Pos) 335 #define PPCLKSR_LCDCLK (SCUCG_PPCLKSR_LCDCLK_Msk) 336 #define LCDCLK_DividedMCLK (SCUCG_PPCLKSR_LCDCLK_DividedMCLK << SCUCG_PPCLKSR_LCDCLK_Pos) 337 #define LCDCLK_XSOSC (SCUCG_PPCLKSR_LCDCLK_XSOSC << SCUCG_PPCLKSR_LCDCLK_Pos) 338 #define LCDCLK_WDTRC (SCUCG_PPCLKSR_LCDCLK_WDTRC << SCUCG_PPCLKSR_LCDCLK_Pos) 347 #define PPCLKSR_WTCLK (SCUCG_PPCLKSR_WTCLK_Msk) 348 #define WTCLK_DividedMCLK (SCUCG_PPCLKSR_WTCLK_DividedMCLK << SCUCG_PPCLKSR_WTCLK_Pos) 349 #define WTCLK_XSOSC (SCUCG_PPCLKSR_WTCLK_XSOSC << SCUCG_PPCLKSR_WTCLK_Pos) 350 #define WTCLK_WDTRC (SCUCG_PPCLKSR_WTCLK_WDTRC << SCUCG_PPCLKSR_WTCLK_Pos) 358 #define PPCLKSR_WDTCLK (SCUCG_PPCLKSR_WDTCLK_Msk) 359 #define WDTCLK_WDTRC (SCUCG_PPCLKSR_WDTCLK_WDTRC << SCUCG_PPCLKSR_WDTCLK_Pos) 360 #define WDTCLK_PCLK (SCUCG_PPCLKSR_WDTCLK_PCLK << SCUCG_PPCLKSR_WDTCLK_Pos) 363 #define PPRST1_T21RST (0x1uL << SCUCG_PPRST1_T21RST_Pos) 364 #define PPRST1_T20RST (0x1uL << SCUCG_PPRST1_T20RST_Pos) 365 #define PPRST1_T30RST (0x1uL << SCUCG_PPRST1_T30RST_Pos) 366 #define PPRST1_T12RST (0x1uL << SCUCG_PPRST1_T12RST_Pos) 367 #define PPRST1_T11RST (0x1uL << SCUCG_PPRST1_T11RST_Pos) 368 #define PPRST1_T10RST (0x1uL << SCUCG_PPRST1_T10RST_Pos) 369 #define PPRST1_T16RST (0x1uL << SCUCG_PPRST1_T16RST_Pos) 370 #define PPRST1_T15RST (0x1uL << SCUCG_PPRST1_T15RST_Pos) 371 #define PPRST1_T14RST (0x1uL << SCUCG_PPRST1_T14RST_Pos) 372 #define PPRST1_T13RST (0x1uL << SCUCG_PPRST1_T13RST_Pos) 373 #define PPRST1_PFRST (0x1uL << SCUCG_PPRST1_PFRST_Pos) 374 #define PPRST1_PERST (0x1uL << SCUCG_PPRST1_PERST_Pos) 375 #define PPRST1_PDRST (0x1uL << SCUCG_PPRST1_PDRST_Pos) 376 #define PPRST1_PCRST (0x1uL << SCUCG_PPRST1_PCRST_Pos) 377 #define PPRST1_PBRST (0x1uL << SCUCG_PPRST1_PBRST_Pos) 378 #define PPRST1_PARST (0x1uL << SCUCG_PPRST1_PARST_Pos) 381 #define PPRST2_FMCRST (0x1uL << SCUCG_PPRST2_FMCRST_Pos) 382 #define PPRST2_LVIRST (0x1uL << SCUCG_PPRST2_LVIRST_Pos) 383 #define PPRST2_WTRST (0x1uL << SCUCG_PPRST2_WTRST_Pos) 384 #define PPRST2_LCDRST (0x1uL << SCUCG_PPRST2_LCDRST_Pos) 385 #define PPRST2_CRRST (0x1uL << SCUCG_PPRST2_CRRST_Pos) 386 #define PPRST2_ADRST (0x1uL << SCUCG_PPRST2_ADRST_Pos) 387 #define PPRST2_I2C2RST (0x1uL << SCUCG_PPRST2_I2C2RST_Pos) 388 #define PPRST2_I2C1RST (0x1uL << SCUCG_PPRST2_I2C1RST_Pos) 389 #define PPRST2_I2C0RST (0x1uL << SCUCG_PPRST2_I2C0RST_Pos) 390 #define PPRST2_UST13RST (0x1uL << SCUCG_PPRST2_UST13RST_Pos) 391 #define PPRST2_UST12RST (0x1uL << SCUCG_PPRST2_UST12RST_Pos) 392 #define PPRST2_UT1RST (0x1uL << SCUCG_PPRST2_UT1RST_Pos) 393 #define PPRST2_UT0RST (0x1uL << SCUCG_PPRST2_UT0RST_Pos) 394 #define PPRST2_UST11RST (0x1uL << SCUCG_PPRST2_UST11RST_Pos) 395 #define PPRST2_UST10RST (0x1uL << SCUCG_PPRST2_UST10RST_Pos) 406 #define XRNS_LE4p5MHz (SCUCG_XTFLSR_XRNS_LE4p5MHz << SCUCG_XTFLSR_XRNS_Pos) // x-tal LE 4.5MHz 407 #define XRNS_LE6p5MHz (SCUCG_XTFLSR_XRNS_LE6p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 4.5MHz GT x-tal LE 6.5MHz 408 #define XRNS_LE8p5MHz (SCUCG_XTFLSR_XRNS_LE8p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 6.5MHz GT x-tal LE 8.5MHz 409 #define XRNS_LE10p5MHz (SCUCG_XTFLSR_XRNS_LE10p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 8.5MHz GT x-tal LE 10.5MHz 410 #define XRNS_LE12p5MHz (SCUCG_XTFLSR_XRNS_LE12p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 10.5MHz GT x-tal LE 12.5MHz 411 #define XRNS_LE16p5MHz (SCUCG_XTFLSR_XRNS_LE16p5MHz << SCUCG_XTFLSR_XRNS_Pos) // 12.5MHz GT x-tal LE 16.5MHz 421 #define SCUCC_GetVendorID() (SCUCC->VENDORID) 422 #define SCUCC_GetChipID() (SCUCC->CHIPID) 423 #define SCUCC_GetRevNo() (SCUCC->REVNR) 432 #define SCUCC_SetBtFnc(rst_src) (SCUCC->BTPSCR_b.BFIND = rst_src) 438 #define SCUCC_GetBtPinSt() (SCUCC->BTPSCR_b.BTPSTA) 444 #define SCUCC_EnNMI() (SCUCC->NMISRCR_b.NMICON = 1) 445 #define SCUCC_DisNMI() (SCUCC->NMISRCR_b.NMICON = 0) 451 #define SCUCC_GenSwRst() (SCUCC->SWRSTR = ((uint32_t)SCUCC_SWRSTR_WTIDKY_Value << SCUCC_SWRSTR_WTIDKY_Pos) | 0x2DuL) 457 #define SCUCC_EnWutInt() (SCUCC->WUTCR_b.WUTIEN = 1) 458 #define SCUCC_DisWutInt() (SCUCC->WUTCR_b.WUTIEN = 0) 464 #define SCUCC_GetWutFlag() (SCUCC->WUTCR_b.WUTIFLAG) 465 #define SCUCC_ClrWutFlag() (SCUCC->WUTCR_b.WUTIFLAG = 1) 471 #define SCUCC_ReloadWut() (SCUCC->WUTCR_b.CNTRLD = 1) 483 #define SCUCG_SetHCLK( scu_hdiv ) (SCUCG->SCDIVR1_b.HDIV = scu_hdiv) 484 #define SCUCG_SetPCLK( scu_pdiv ) (SCUCG->SCDIVR2_b.PDIV = scu_pdiv) 485 #define SCUCG_SetWtLcd( scu_wldiv ) (SCUCG->SCDIVR1_b.WLDIV = scu_wldiv) 486 #define SCUCG_SetSysTick( scu_systdiv ) (SCUCG->SCDIVR2_b.SYSTDIV = scu_systdiv) 494 #define SCUCG_SetClkOutReg( u32Clko ) (SCUCG->CLKOCR = u32Clko) 500 #define SCUCG_GetMonFlag() (SCUCG->CMONCR_b.MONFLAG) 508 #define SCUCG_SetT20ClkSrc( clk ) (SCUCG->PPCLKSR_b.T20CLK = clk) 516 #define SCUCG_SetT30ClkSrc( clk ) (SCUCG->PPCLKSR_b.T30CLK = clk) 524 #define SCUCG_SetLcdClk( clk ) (SCUCG->PPCLKSR_b.LCDCLK = clk) 532 #define SCUCG_SetWtClk( clk ) (SCUCG->PPCLKSR_b.WTCLK = clk) 540 #define SCUCG_SetWdtClk( clk ) (SCUCG->PPCLKSR_b.WDTCLK = clk) void HAL_SCU_ClockMonitoring_Disable(void)
Disable Clock Monitoring.
void HAL_SCU_ClockOutput(uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div)
Set Configuration for Clock Output.
Contains the ABOV typedefs for C standard types. It is intended to be used in ISO C conforming develo...
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_SetWakupData(uint32_t u32Data)
Set Wake-Up Timer Data.
void HAL_SCU_SoftwareReset_Config(void)
Check whether system reset ok or not. Generate s/w reset if a weak reset.
void HAL_SCU_SystemClockDivider(uint32_t u32Div02, uint32_t u32Div13)
Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick T...
void HAL_SCU_Peripheral_ClockSelection(uint32_t u32Peri, uint32_t u32ClkSrc)
Peripheral Clock Selection of PPCLKSR Register.
void HAL_SCU_SystemClockChange(uint32_t u32Target)
Change System Clock.
void HAL_SCU_HIRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of HIRC by one step.
void HAL_SCU_ClockSource_Config(uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc)
Set Clock Source, HIRC Frequency, and type of XMOSC.
void HAL_SCU_Peripheral_ResetConfig(uint32_t u32PeriRst1, uint32_t u32PeriRst2)
Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".
void HAL_SCU_Peripheral_ClockConfig(uint32_t u32PeriClk1, uint32_t u32PeriClk2)
Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".
void HAL_SCU_ClockSource_Enable(uint32_t u32ClkSrc, uint32_t u32HircDiv)
Enable Clock Source.
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
void HAL_SCU_ClockMonitoring(uint32_t u32Acts, uint32_t u32Target)
Configure Clock Monitoring.
void HAL_SCU_SetNMI(uint32_t u32NmiCon)
Set Non-Maskable Interrupt(NMI) Source Selection Register.
void HAL_SCU_ClockSource_Disable(uint32_t u32ClkSrc)
Disable Clock Source.
void HAL_SCU_CLKO_PinConfig(void)
Set CLKO Pin for Clock Output.
void HAL_SCU_SubXtal_PinConfig(void)
Set XSOSC Pins for x-tal.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
void HAL_SCU_MainXtal_PinConfig(uint32_t u32XtalFilter)
Set XMOSC Pins for x-tal.
uint32_t HAL_SCU_ResetSourceStatus(void)
Get Reset Source Status.
void HAL_SCU_WDTRCTRM_ClockConfig(uint32_t u32Ind)
Change fine trim value of WDTRC by one step.
void HAL_SCU_Peripheral_SetReset1(uint32_t u32EachPeri1)
Set/Reset Each Peripheral Block Reset of PPRST1 Register.