A31G12x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G12x_hal_timer1n.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31G12x_hal_scu.h"
41 #include "A31G12x_hal_timer1n.h"
42 
43 /* Public Functions --------------------------------------------------------- */
44 //******************************************************************************
45 // Function
46 //******************************************************************************
47 
48 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
65 HAL_Status_Type HAL_TIMER1n_Init( TIMER1n_Type* TIMER1x, TIMER1n_MODE_OPT TimerCounterMode, void* TIMER1n_Config )
66 {
67  TIMER1n_PERIODICCFG_Type* pTimeCfg;
68  TIMER1n_PWMCFG_Type* pPwmOneshotCfg;
69  TIMER1n_CAPTURECFG_Type* pCaptureCfg;
70  uint16_t reg_val16;
71 
72  /* Check TIMER1 handle */
73  if( TIMER1x == NULL )
74  {
75  return HAL_ERROR;
76  }
77 
78 #if 1 // supported
79  if( TIMER1x == ( TIMER1n_Type* )TIMER10 )
80  {
81  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T10CLKE, PPxCLKE_Enable );
82  }
83 #endif
84 
85 #if 1 // supported
86  if( TIMER1x == ( TIMER1n_Type* )TIMER11 )
87  {
88  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T11CLKE, PPxCLKE_Enable );
89  }
90 #endif
91 
92 #if 1 // supported
93  if( TIMER1x == ( TIMER1n_Type* )TIMER12 )
94  {
95  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T12CLKE, PPxCLKE_Enable );
96  }
97 #endif
98 
99 #if 1 // supported
100  if( TIMER1x == ( TIMER1n_Type* )TIMER13 )
101  {
102  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T13CLKE, PPxCLKE_Enable );
103  }
104 #endif
105 
106 #if 1 // supported
107  if( TIMER1x == ( TIMER1n_Type* )TIMER14 )
108  {
109  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T14CLKE, PPxCLKE_Enable );
110  }
111 #endif
112 
113 #if 1 // supported
114  if( TIMER1x == ( TIMER1n_Type* )TIMER15 )
115  {
116  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T15CLKE, PPxCLKE_Enable );
117  }
118 #endif
119 
120 #if 1 // supported
121  if( TIMER1x == ( TIMER1n_Type* )TIMER16 )
122  {
123  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T16CLKE, PPxCLKE_Enable );
124  }
125 #endif
126 
127  if( TimerCounterMode == TIMER1n_PERIODIC_MODE )
128  {
129  pTimeCfg = ( TIMER1n_PERIODICCFG_Type* )TIMER1n_Config;
130 
131  reg_val16 = 0
132  | TIMER1n_CR_CKSEL_SET( pTimeCfg->CkSel )
133  | TIMER1n_CR_MODE_SET( TimerCounterMode )
134  | TIMER1n_CR_STARTLVL_SET( pTimeCfg->StartLevel )
135  ;
136  if( pTimeCfg->CkSel == 1 )
137  {
138  reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pTimeCfg->ECE );
139  }
140  TIMER1x->CR = reg_val16;
141 
142  TIMER1x->PREDR = ( ( pTimeCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
143  TIMER1x->ADR = pTimeCfg->ADR;
144  }
145  else if( ( TimerCounterMode == TIMER1n_PWM_MODE ) || ( TimerCounterMode == TIMER1n_ONESHOT_MODE ) )
146  {
147  pPwmOneshotCfg = ( TIMER1n_PWMCFG_Type* )TIMER1n_Config;
148 
149  reg_val16 = 0
150  | TIMER1n_CR_CKSEL_SET( pPwmOneshotCfg->CkSel )
151  | TIMER1n_CR_MODE_SET( TimerCounterMode )
152  | TIMER1n_CR_STARTLVL_SET( pPwmOneshotCfg->StartLevel )
153  ;
154  if( pPwmOneshotCfg->CkSel == 1 )
155  {
156  reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pPwmOneshotCfg->ECE );
157  }
158  TIMER1x->CR = reg_val16;
159 
160  TIMER1x->PREDR = ( ( pPwmOneshotCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
161  TIMER1x->ADR = pPwmOneshotCfg->ADR;
162  TIMER1x->BDR = pPwmOneshotCfg->BDR;
163  }
164  else if( TimerCounterMode == TIMER1n_CAPTURE_MODE )
165  {
166  pCaptureCfg = ( TIMER1n_CAPTURECFG_Type* )TIMER1n_Config;
167 
168  reg_val16 = 0
169  | TIMER1n_CR_CKSEL_SET( pCaptureCfg->CkSel )
170  | TIMER1n_CR_MODE_SET( TimerCounterMode )
171  | TIMER1n_CR_CPOL_SET( pCaptureCfg->ClrMode )
172  ;
173  if( pCaptureCfg->CkSel == 1 )
174  {
175  reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pCaptureCfg->ECE );
176  }
177  TIMER1x->CR = reg_val16;
178 
179  TIMER1x->PREDR = ( ( pCaptureCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
180  TIMER1x->ADR = pCaptureCfg->ADR;
181  }
182  TIMER1x->CR |= 0x1; // timer counter clear
183 
184  return HAL_OK;
185 }
186 
187 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
194 HAL_Status_Type HAL_TIMER1n_DeInit( TIMER1n_Type* TIMER1x )
195 {
196  /* Check TIMER1 handle */
197  if( TIMER1x == NULL )
198  {
199  return HAL_ERROR;
200  }
201 
202  // Disable timer/counter
203  TIMER1x->CR = 0x00;
204 
205 #if 1 // supported
206  if( TIMER1x == ( TIMER1n_Type* )TIMER10 )
207  {
208  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T10CLKE, PPxCLKE_Disable );
209  }
210 #endif
211 
212 #if 1 // supported
213  if( TIMER1x == ( TIMER1n_Type* )TIMER11 )
214  {
215  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T11CLKE, PPxCLKE_Disable );
216  }
217 #endif
218 
219 #if 1 // supported
220  if( TIMER1x == ( TIMER1n_Type* )TIMER12 )
221  {
222  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T12CLKE, PPxCLKE_Disable );
223  }
224 #endif
225 
226 #if 1 // supported
227  if( TIMER1x == ( TIMER1n_Type* )TIMER13 )
228  {
229  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T13CLKE, PPxCLKE_Disable );
230  }
231 #endif
232 
233 #if 1 // supported
234  if( TIMER1x == ( TIMER1n_Type* )TIMER14 )
235  {
236  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T14CLKE, PPxCLKE_Disable );
237  }
238 #endif
239 
240 #if 1 // supported
241  if( TIMER1x == ( TIMER1n_Type* )TIMER15 )
242  {
243  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T15CLKE, PPxCLKE_Disable );
244  }
245 #endif
246 
247 #if 1 // supported
248  if( TIMER1x == ( TIMER1n_Type* )TIMER16 )
249  {
250  HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T16CLKE, PPxCLKE_Disable );
251  }
252 #endif
253 
254  return HAL_OK;
255 }
256 
257 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
271 HAL_Status_Type HAL_TIMER1n_ConfigInterrupt( TIMER1n_Type* TIMER1x, TIMER1n_INT_Type TIMER1n_IntCfg, FunctionalState NewState )
272 {
273  uint8_t tmp;
274 
275  /* Check TIMER1 handle */
276  if( TIMER1x == NULL )
277  {
278  return HAL_ERROR;
279  }
280 
281  switch( TIMER1n_IntCfg )
282  {
283  case TIMER1n_INTCFG_MIE:
284  tmp = TIMER1n_MATINTEN;
285  break;
286  case TIMER1n_INTCFG_CIE:
287  tmp = TIMER1n_CAPINTEN;
288  break;
289  }
290 
291  if( NewState == ENABLE )
292  {
293  TIMER1x->CR |= tmp;
294  }
295  else
296  {
297  TIMER1x->CR &= ( ~tmp );
298  }
299 
300  return HAL_OK;
301 }
302 
303 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
313 HAL_Status_Type HAL_TIMER1n_Cmd( TIMER1n_Type* TIMER1x, FunctionalState NewState )
314 {
315  /* Check TIMER1 handle */
316  if( TIMER1x == NULL )
317  {
318  return HAL_ERROR;
319  }
320 
321  if( NewState == ENABLE )
322  {
323  TIMER1x->CR |= TIMER1n_ENABLE;
324  }
325  else
326  {
327  TIMER1x->CR &= ~TIMER1n_ENABLE;
328  }
329 
330  return HAL_OK;
331 }
332 
333 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
346 HAL_Status_Type HAL_TIMER1n_SetRegister( TIMER1n_Type* TIMER1x, uint32_t u32T1nSet, uint32_t u32T1nClk )
347 {
348  /* Check TIMER1 handle */
349  if( TIMER1x == NULL )
350  {
351  return HAL_ERROR;
352  }
353 
354  TIMER1x->CR = u32T1nSet; // Setting TIMER1n Control Register
355 
356  TIMER1x->PREDR = u32T1nClk; // Setting TIMER1n Prescaler data
357 
358  return HAL_OK;
359 }
360 
HAL_Status_Type HAL_TIMER1n_Cmd(TIMER1n_Type *TIMER1x, FunctionalState NewState)
Start/Stop Timer/Counter device.
HAL_Status_Type
HAL_Status_Type HAL_TIMER1n_SetRegister(TIMER1n_Type *TIMER1x, uint32_t u32T1nSet, uint32_t u32T1nClk)
Set TIMER1n CR/PREDR Registers.
HAL_Status_Type HAL_TIMER1n_ConfigInterrupt(TIMER1n_Type *TIMER1x, TIMER1n_INT_Type TIMER1n_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
TIMER1n_INT_Type
Contains all macro definitions and function prototypes support for timer1n firmware library on A31G12...
HAL_Status_Type HAL_TIMER1n_DeInit(TIMER1n_Type *TIMER1x)
Close Timer/Counter device.
HAL_Status_Type HAL_TIMER1n_Init(TIMER1n_Type *TIMER1x, TIMER1n_MODE_OPT TimerCounterMode, void *TIMER1n_Config)
Initialize the TIMER1n peripheral with the specified parameters.
TIMER1n_MODE_OPT
FunctionalState
void HAL_SCU_Peripheral_EnableClock1(uint32_t u32PeriClk1, uint32_t Ind)
Set Each Peripheral Clock.
Contains all macro definitions and function prototypes support for scu firmware library on A31G12x.