A31G12x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
Data Structures | Enumerations | Functions | Variables
A31G12x_hal_uartn.h File Reference

Contains all macro definitions and function prototypes support for uartn firmware library on A31G12x. More...

Go to the source code of this file.

Data Structures

struct  UARTn_CFG_Type
 

Enumerations

enum  UARTn_DATA_BIT_Type { UARTn_DATA_BIT_5 = 0, UARTn_DATA_BIT_6, UARTn_DATA_BIT_7, UARTn_DATA_BIT_8 }
 
enum  UARTn_STOP_BIT_Type { UARTn_STOP_BIT_1 = 0, UARTn_STOP_BIT_2 }
 
enum  UARTn_PARITY_BIT_Type {
  UARTn_PARITY_BIT_NONE = 0, UARTn_PARITY_BIT_ODD, UARTn_PARITY_BIT_EVEN, UARTn_PARITY_BIT_SP_1,
  UARTn_PARITY_BIT_SP_0
}
 
enum  UARTn_INT_Type { UARTn_INTCFG_RBR = 0, UARTn_INTCFG_THRE, UARTn_INTCFG_RLS, UARTn_INTCFG_TXE }
 
enum  UARTn_DATA_CONTROL_Type { UARTn_DATA_CONTROL_LOOPBACK = 0, UARTn_DATA_CONTROL_RXINV, UARTn_DATA_CONTROL_TXINV, UARTn_DATA_CONTROL_RTXINV }
 

Functions

HAL_Status_Type HAL_UART_Init (UARTn_Type *UARTx, UARTn_CFG_Type *UARTn_Config)
 Initialize the UARTn peripheral with the specified parameters. More...
 
HAL_Status_Type HAL_UART_DeInit (UARTn_Type *UARTx)
 Deinitialize the UARTn peripheral registers to their default reset values. More...
 
HAL_Status_Type HAL_UART_ConfigStructInit (UARTn_CFG_Type *UARTn_Config)
 Fills each UARTn_Config member with its default value: More...
 
HAL_Status_Type HAL_UART_ConfigInterrupt (UARTn_Type *UARTx, UARTn_INT_Type UARTn_IntCfg, FunctionalState NewState)
 Configure the peripheral interrupt. More...
 
HAL_Status_Type HAL_UART_DataControlConfig (UARTn_Type *UARTx, UARTn_DATA_CONTROL_Type Mode, FunctionalState NewState)
 Configure Data Control mode for UART peripheral. More...
 
HAL_Status_Type HAL_UART_IFDelayConfig (UARTn_Type *UARTx, uint8_t waitval)
 Configure inter-frame delay time for UART peripheral. More...
 
HAL_Status_Type HAL_UART_ForceBreak (UARTn_Type *UARTx)
 Force BREAK character on UART line, output pin UARTn TXD is forced to logic 0. More...
 
uint8_t HAL_UART_GetLineStatus (UARTn_Type *UARTx)
 This function returns the current value of Line Status Register. More...
 
FlagStatus HAL_UART_CheckBusy (UARTn_Type *UARTx)
 Check whether if UART is busy or not. More...
 
HAL_Status_Type HAL_UART_TransmitByte (UARTn_Type *UARTx, uint8_t Data)
 Transmit a single data through UART peripheral. More...
 
uint8_t HAL_UART_ReceiveByte (UARTn_Type *UARTx)
 Receive a single data from UART peripheral. More...
 
uint32_t HAL_UART_Transmit (UARTn_Type *UARTx, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
 Send a block of data via UART peripheral. More...
 
uint32_t HAL_UART_Receive (UARTn_Type *UARTx, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
 Receive a block of data via UART peripheral. More...
 

Variables

char InData [80]
 
int InFlag
 
int InCount
 

Detailed Description

Contains all macro definitions and function prototypes support for uartn firmware library on A31G12x.

Version
1.00
Date
2020-05-29
Author
ABOV Application Team

Copyright(C) 2019, ABOV Semiconductor All rights reserved.

ABOV Disclaimer

IMPORTANT NOTICE ? PLEASE READ CAREFULLY ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders. Purchasers are entirely responsible for the choice, selection, and use of ABOV products and ABOV assumes no liability for application assistance or the design of purchasers' products. No license, express or implied, to any intellectual property rights is granted by ABOV herein. ABOV disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications. ABOV and the ABOV logo are trademarks of ABOV. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces the information previously supplied in any former versions of this document. 2020 ABOV Semiconductor All rights reserved

Definition in file A31G12x_hal_uartn.h.

Enumeration Type Documentation

◆ UARTn_DATA_BIT_Type

UARTn Data Bit type definitions

Enumerator
UARTn_DATA_BIT_5 

5 Data Bits

UARTn_DATA_BIT_6 

6 Data Bits

UARTn_DATA_BIT_7 

7 Data Bits

UARTn_DATA_BIT_8 

8 Data Bits

Definition at line 120 of file A31G12x_hal_uartn.h.

◆ UARTn_DATA_CONTROL_Type

UARTn Data Control type definition

Enumerator
UARTn_DATA_CONTROL_LOOPBACK 

Loop back mode select

UARTn_DATA_CONTROL_RXINV 
UARTn_DATA_CONTROL_TXINV 
UARTn_DATA_CONTROL_RTXINV 

Definition at line 155 of file A31G12x_hal_uartn.h.

◆ UARTn_INT_Type

UARTn Interrupt Type definitions

Enumerator
UARTn_INTCFG_RBR 

RBR Interrupt enable

UARTn_INTCFG_THRE 

THR Interrupt enable

UARTn_INTCFG_RLS 

RX line status interrupt enable

UARTn_INTCFG_TXE 

TXE interrupt

Definition at line 146 of file A31G12x_hal_uartn.h.

◆ UARTn_PARITY_BIT_Type

UARTn Parity Bit type definitions

Enumerator
UARTn_PARITY_BIT_NONE 

No parity

UARTn_PARITY_BIT_ODD 

Odd parity

UARTn_PARITY_BIT_EVEN 

Even parity

UARTn_PARITY_BIT_SP_1 

Forced "1" stick parity

UARTn_PARITY_BIT_SP_0 

Forced "0" stick parity

Definition at line 136 of file A31G12x_hal_uartn.h.

◆ UARTn_STOP_BIT_Type

UARTn Stop Bit type definitions

Enumerator
UARTn_STOP_BIT_1 

1 Stop Bits

UARTn_STOP_BIT_2 

2 Stop Bits

Definition at line 129 of file A31G12x_hal_uartn.h.

Function Documentation

◆ HAL_UART_CheckBusy()

FlagStatus HAL_UART_CheckBusy ( UARTn_Type *  UARTx)

Check whether if UART is busy or not.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
Returns
RESET if UART is not busy, otherwise return SET.

Definition at line 461 of file A31G12x_hal_uartn.c.

462 {
463  if( UARTx->LSR & UARTn_LSR_TEMT )
464  {
465  return RESET;
466  }
467  else
468  {
469  return SET;
470  }
471 }

References RESET, and SET.

Referenced by fputc().

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◆ HAL_UART_ConfigInterrupt()

HAL_Status_Type HAL_UART_ConfigInterrupt ( UARTn_Type *  UARTx,
UARTn_INT_Type  UARTn_IntCfg,
FunctionalState  NewState 
)

Configure the peripheral interrupt.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
[in]UARTn_IntCfgSpecifies the interrupt flag
  • UARTn_INTCFG_RBR: RBR Interrupt enable
  • UARTn_INTCFG_THRE: THR Interrupt enable
  • UARTn_INTCFG_RLS: RX line status interrupt enable
  • UARTn_INTCFG_DRX: THR Interrupt enable
  • UARTn_INTCFG_DTX: RX line status interrupt enable
[in]NewStateNext State of Interrupt Operation
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 297 of file A31G12x_hal_uartn.c.

298 {
299  uint32_t tmp;
300 
301  /* Check UART handle */
302  if( UARTx == NULL )
303  {
304  return HAL_ERROR;
305  }
306 
307  switch( UARTn_IntCfg )
308  {
309  case UARTn_INTCFG_RBR:
310  tmp = UARTn_IER_RBRINT_EN;
311  break;
312  case UARTn_INTCFG_THRE:
313  tmp = UARTn_IER_THREINT_EN;
314  break;
315  case UARTn_INTCFG_RLS:
316  tmp = UARTn_IER_RLSINT_EN;
317  break;
318  case UARTn_INTCFG_TXE:
319  tmp = UARTn_IER_TXE_EN;
320  break;
321  }
322 
323  if( NewState == ENABLE )
324  {
325  UARTx->IER |= tmp;
326  }
327  else
328  {
329  UARTx->IER &= ( ~tmp ) & UARTn_IER_BITMASK;
330  }
331 
332  return HAL_OK;
333 }

References ENABLE, HAL_ERROR, HAL_OK, UARTn_INTCFG_RBR, UARTn_INTCFG_RLS, UARTn_INTCFG_THRE, and UARTn_INTCFG_TXE.

◆ HAL_UART_ConfigStructInit()

HAL_Status_Type HAL_UART_ConfigStructInit ( UARTn_CFG_Type UARTn_Config)

Fills each UARTn_Config member with its default value:

  • 38400 bps
  • 8 Data Bit
  • No Parity Bit
  • 1 Stop Bit
    Parameters
    [out]UARTn_ConfigPointer to a UARTn_CFG_Type structure which will be initialized.
    Returns
    HAL_Status_Type

Definition at line 264 of file A31G12x_hal_uartn.c.

265 {
266  /* Check UARTn_Config */
267  if( UARTn_Config == NULL )
268  {
269  return HAL_ERROR;
270  }
271 
272  UARTn_Config->Baudrate = 38400;
273  UARTn_Config->Databits = UARTn_DATA_BIT_8;
274  UARTn_Config->Parity = UARTn_PARITY_BIT_NONE;
275  UARTn_Config->Stopbits = UARTn_STOP_BIT_1;
276 
277  return HAL_OK;
278 }
UARTn_DATA_BIT_Type Databits
UARTn_PARITY_BIT_Type Parity
UARTn_STOP_BIT_Type Stopbits

References UARTn_CFG_Type::Baudrate, UARTn_CFG_Type::Databits, HAL_ERROR, HAL_OK, UARTn_CFG_Type::Parity, UARTn_CFG_Type::Stopbits, UARTn_DATA_BIT_8, UARTn_PARITY_BIT_NONE, and UARTn_STOP_BIT_1.

Referenced by debug_frmwrk_init().

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◆ HAL_UART_DataControlConfig()

HAL_Status_Type HAL_UART_DataControlConfig ( UARTn_Type *  UARTx,
UARTn_DATA_CONTROL_Type  Mode,
FunctionalState  NewState 
)

Configure Data Control mode for UART peripheral.

Parameters
[in]UARTxPointer to the target UART
[in]ModeData Control Mode
  • UARTn_DATA_CONTROL_LOOPBACK: Loop back mode.
  • UARTn_DATA_CONTROL_RXINV: RX Data inversion mode.
  • UARTn_DATA_CONTROL_TXINV: TX Data inversion mode.
  • UARTn_DATA_CONTROL_RTXINV: TX RX Data inversion mode.
[in]NewStateNext State of Functional Operation
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 350 of file A31G12x_hal_uartn.c.

351 {
352  uint8_t tmp;
353 
354  /* Check UART handle */
355  if( UARTx == NULL )
356  {
357  return HAL_ERROR;
358  }
359 
360  switch( Mode )
361  {
363  tmp = UARTn_DCR_LBON;
364  break;
366  tmp = UARTn_DCR_RXINV;
367  break;
369  tmp = UARTn_DCR_TXINV;
370  break;
372  tmp = UARTn_DCR_RXINV | UARTn_DCR_TXINV;
373  break;
374  default:
375  break;
376  }
377 
378  if( NewState == ENABLE )
379  {
380  UARTx->DCR |= tmp;
381  }
382  else
383  {
384  UARTx->DCR &= ( ~tmp ) & UARTn_DCR_BITMASK;
385  }
386 
387  return HAL_OK;
388 }

References ENABLE, HAL_ERROR, HAL_OK, UARTn_DATA_CONTROL_LOOPBACK, UARTn_DATA_CONTROL_RTXINV, UARTn_DATA_CONTROL_RXINV, and UARTn_DATA_CONTROL_TXINV.

◆ HAL_UART_DeInit()

HAL_Status_Type HAL_UART_DeInit ( UARTn_Type *  UARTx)

Deinitialize the UARTn peripheral registers to their default reset values.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
Returns
HAL_Status_Type

Definition at line 225 of file A31G12x_hal_uartn.c.

226 {
227  /* Check UART handle */
228  if( UARTx == NULL )
229  {
230  return HAL_ERROR;
231  }
232 
233 #if 1 // supported
234  if( UARTx == ( UARTn_Type* )UART0 )
235  {
236  /* Set up peripheral clock for UART0 module */
238  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT0CLKE, PPxCLKE_Disable );
239  }
240 #endif
241 
242 #if 1 // supported
243  if( UARTx == ( UARTn_Type* )UART1 )
244  {
245  /* Set up peripheral clock for UART1 module */
247  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT1CLKE, PPxCLKE_Disable );
248  }
249 #endif
250 
251  return HAL_OK;
252 }
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.

References HAL_ERROR, HAL_OK, HAL_SCU_Peripheral_EnableClock2(), and HAL_SCU_Peripheral_SetReset2().

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◆ HAL_UART_ForceBreak()

HAL_Status_Type HAL_UART_ForceBreak ( UARTn_Type *  UARTx)

Force BREAK character on UART line, output pin UARTn TXD is forced to logic 0.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
Returns
HAL_Status_Type

Definition at line 422 of file A31G12x_hal_uartn.c.

423 {
424  /* Check UART handle */
425  if( UARTx == NULL )
426  {
427  return HAL_ERROR;
428  }
429 
430  UARTx->LCR |= UARTn_LCR_BREAK_EN;
431 
432  return HAL_OK;
433 }

References HAL_ERROR, and HAL_OK.

◆ HAL_UART_GetLineStatus()

uint8_t HAL_UART_GetLineStatus ( UARTn_Type *  UARTx)

This function returns the current value of Line Status Register.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
Returns
Current value of Line Status register in UART peripheral.
Note
The return value of this function must be ANDed with each member in UART_LS_Type enumeration to determine current flag status corresponding to each Line status type. Because some flags in Line Status register will be cleared after reading, the next reading Line Status register could not be correct. So this function used to read Line status register in one time only, then the return value used to check all flags.

Definition at line 449 of file A31G12x_hal_uartn.c.

450 {
451  return ( ( UARTx->LSR ) & UARTn_LSR_BITMASK );
452 }

◆ HAL_UART_IFDelayConfig()

HAL_Status_Type HAL_UART_IFDelayConfig ( UARTn_Type *  UARTx,
uint8_t  waitval 
)

Configure inter-frame delay time for UART peripheral.

Parameters
[in]UARTxPointer to the target UART
[in]waitvalinter-frame delay time: 1 bit time unit (0~7)
Returns
HAL_Status_Type

Definition at line 398 of file A31G12x_hal_uartn.c.

399 {
400  /* Check UART handle */
401  if( UARTx == NULL )
402  {
403  return HAL_ERROR;
404  }
405 
406  if( waitval < 8 )
407  {
408  UARTx->IDTR = waitval;
409  }
410 
411  return HAL_OK;
412 }

References HAL_ERROR, and HAL_OK.

◆ HAL_UART_Init()

HAL_Status_Type HAL_UART_Init ( UARTn_Type *  UARTx,
UARTn_CFG_Type UARTn_Config 
)

Initialize the UARTn peripheral with the specified parameters.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
[in]UARTn_ConfigPointer to a UARTn_CFG_Type structure that contains the configuration information for the specified peripheral.
Returns
HAL_Status_Type

Definition at line 103 of file A31G12x_hal_uartn.c.

104 {
105  uint8_t tmp;
106 
107  /* Check UART handle */
108  if( UARTx == NULL )
109  {
110  return HAL_ERROR;
111  }
112 
113 #if 1 // supported
114  if( UARTx == ( UARTn_Type* )UART0 )
115  {
116  /* Set up peripheral clock for UART0 module */
117  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT0CLKE, PPxCLKE_Enable );
118  }
119 #endif
120 
121 #if 1 // supported
122  if( UARTx == ( UARTn_Type* )UART1 )
123  {
124  /* Set up peripheral clock for UART1 module */
125  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT1CLKE, PPxCLKE_Enable );
126  }
127 #endif
128 
129  // Dummy reading
130  while( UARTx->LSR & UARTn_LSR_RDR )
131  {
132  tmp = UARTx->RBR;
133  }
134  // Wait for current transmit complete
135  while( !( UARTx->LSR & UARTn_LSR_THRE ) );
136 
137  // Disable interrupt
138  UARTx->IER = 0;
139  // Set LCR, DCR to default state
140  UARTx->LCR = 0;
141  UARTx->DCR = 0;
142  // Dummy reading
143  tmp = UARTx->LSR;
144  tmp = UARTx->IIR;
145 
146  // uart clock set
147  // SCU->MCCR7 &=0xffff0000;
148  // SCU->MCCR7 |=((4<<8)|(2)); // MCLK
149  UARTn_BaseClock = SystemPeriClock;
150 
151  // Set Line Control register ----------------------------
152  uart_set_divisors( UARTx, ( UARTn_Config->Baudrate ) );
153 
154  tmp = ( UARTx->LCR & UARTn_LCR_BREAK_EN ) & UARTn_LCR_BITMASK;
155 
156  switch( UARTn_Config->Databits )
157  {
158  case UARTn_DATA_BIT_5:
159  tmp |= UARTn_LCR_WLEN5;
160  break;
161  case UARTn_DATA_BIT_6:
162  tmp |= UARTn_LCR_WLEN6;
163  break;
164  case UARTn_DATA_BIT_7:
165  tmp |= UARTn_LCR_WLEN7;
166  break;
167  case UARTn_DATA_BIT_8:
168  default:
169  tmp |= UARTn_LCR_WLEN8;
170  break;
171  }
172 
173  if( UARTn_Config->Parity == UARTn_PARITY_BIT_NONE )
174  {
175  // Do nothing...
176  }
177  else
178  {
179  tmp |= UARTn_LCR_PARITY_EN;
180  switch( UARTn_Config->Parity )
181  {
183  tmp |= UARTn_LCR_PARITY_ODD;
184  break;
185 
187  tmp |= UARTn_LCR_PARITY_EVEN;
188  break;
189 
191  tmp |= UARTn_LCR_PARITY_F_1;
192  break;
193 
195  tmp |= UARTn_LCR_PARITY_F_0;
196  break;
197  default:
198  break;
199  }
200  }
201 
202  switch( UARTn_Config->Stopbits )
203  {
204  case UARTn_STOP_BIT_2:
205  tmp |= UARTn_LCR_STOPBIT_SEL;
206  break;
207  case UARTn_STOP_BIT_1:
208  default:
209  // Do no thing
210  break;
211  }
212 
213  UARTx->LCR = ( uint8_t )( tmp & UARTn_LCR_BITMASK );
214 
215  return HAL_OK;
216 }
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
static uint32_t UARTn_BaseClock
UARTn_DATA_BIT_Type Databits
static void uart_set_divisors(UARTn_Type *UARTx, uint32_t baudrate)
Determines best dividers to get a target clock rate.
UARTn_PARITY_BIT_Type Parity
UARTn_STOP_BIT_Type Stopbits

References UARTn_CFG_Type::Baudrate, UARTn_CFG_Type::Databits, HAL_ERROR, HAL_OK, HAL_SCU_Peripheral_EnableClock2(), UARTn_CFG_Type::Parity, UARTn_CFG_Type::Stopbits, uart_set_divisors(), UARTn_BaseClock, UARTn_DATA_BIT_5, UARTn_DATA_BIT_6, UARTn_DATA_BIT_7, UARTn_DATA_BIT_8, UARTn_PARITY_BIT_EVEN, UARTn_PARITY_BIT_NONE, UARTn_PARITY_BIT_ODD, UARTn_PARITY_BIT_SP_0, UARTn_PARITY_BIT_SP_1, UARTn_STOP_BIT_1, and UARTn_STOP_BIT_2.

Referenced by debug_frmwrk_init().

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◆ HAL_UART_Receive()

uint32_t HAL_UART_Receive ( UARTn_Type *  UARTx,
uint8_t *  rxbuf,
uint32_t  buflen,
TRANSFER_BLOCK_Type  flag 
)

Receive a block of data via UART peripheral.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
[out]rxbufPointer to Received buffer
[in]buflenLength of Received buffer
[in]flagFlag mode
  • NONE_BLOCKING
  • BLOCKING
Returns
Number of bytes received
Note
when using UART in BLOCKING mode, a time-out condition is used via defined symbol UARTn_BLOCKING_TIMEOUT.

Definition at line 608 of file A31G12x_hal_uartn.c.

609 {
610  uint32_t bToRecv, bRecv, timeOut;
611  uint8_t* pChar = rxbuf;
612 
613  // init counter
614  bToRecv = buflen;
615  bRecv = 0;
616 
617  // Blocking Mode
618  if( flag == BLOCKING )
619  {
620  while( bToRecv )
621  {
622  // wait until data are received with timeout
623  timeOut = UARTn_BLOCKING_TIMEOUT;
624  while( !( UARTx->LSR & UARTn_LSR_RDR ) )
625  {
626  if( timeOut == 0 )
627  {
628  break;
629  }
630  timeOut--;
631  }
632 
633  // if timeout
634  if( timeOut == 0 )
635  {
636  break;
637  }
638 
639  // receive byte
640  ( *pChar++ ) = HAL_UART_ReceiveByte( UARTx );
641 
642  // update counter
643  bToRecv--;
644  bRecv++;
645  }
646  }
647 
648  // Non-Blocking Mode
649  else
650  {
651  while( bToRecv )
652  {
653  // if no data were received
654  if( !( UARTx->LSR & UARTn_LSR_RDR ) )
655  {
656  break;
657  }
658 
659  // receive byte
660  ( *pChar++ ) = HAL_UART_ReceiveByte( UARTx );
661 
662  // update counter
663  bToRecv--;
664  bRecv++;
665  }
666  }
667 
668  // return
669  return bRecv;
670 }
uint8_t HAL_UART_ReceiveByte(UARTn_Type *UARTx)
Receive a single data from UART peripheral.

References BLOCKING, and HAL_UART_ReceiveByte().

Referenced by UARTGetChar().

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◆ HAL_UART_ReceiveByte()

uint8_t HAL_UART_ReceiveByte ( UARTn_Type *  UARTx)

Receive a single data from UART peripheral.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
Returns
Data received

Definition at line 502 of file A31G12x_hal_uartn.c.

503 {
504  return UARTx->RBR;
505 }

Referenced by HAL_UART_Receive(), and UARTGetCh().

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◆ HAL_UART_Transmit()

uint32_t HAL_UART_Transmit ( UARTn_Type *  UARTx,
uint8_t *  txbuf,
uint32_t  buflen,
TRANSFER_BLOCK_Type  flag 
)

Send a block of data via UART peripheral.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
[in]txbufPointer to Transmit buffer
[in]buflenLength of Transmit buffer
[in]flagFlag used in UART transfer
  • NONE_BLOCKING
  • BLOCKING
Returns
Number of bytes sent.
Note
when using UART in BLOCKING mode, a time-out condition is used via defined symbol UARTn_BLOCKING_TIMEOUT.

Definition at line 524 of file A31G12x_hal_uartn.c.

525 {
526  uint32_t bToSend, bSent, timeOut;
527  uint8_t* pChar = txbuf;
528 
529  // init counter
530  bToSend = buflen;
531  bSent = 0;
532 
533  // Blocking Mode
534  if( flag == BLOCKING )
535  {
536  while( bToSend )
537  {
538  // wait until tx data register is empty with timeout
539  timeOut = UARTn_BLOCKING_TIMEOUT;
540  while( !( UARTx->LSR & UARTn_LSR_THRE ) )
541  {
542  if( timeOut == 0 )
543  {
544  break;
545  }
546  timeOut--;
547  }
548 
549  // if timeout
550  if( timeOut == 0 )
551  {
552  break;
553  }
554 
555  // send byte
556  HAL_UART_TransmitByte( UARTx, ( *pChar++ ) );
557 
558  // update counter
559  bToSend--;
560  bSent++;
561  }
562 
563  // wait until previous transmission is complete
564  while( UARTx->LSR_b.TEMT == 0 ); // Polling Only
565  }
566 
567  // Non-Blocking Mode
568  else
569  {
570  while( bToSend )
571  {
572  // if tx data register is not empty
573  if( !( UARTx->LSR & UARTn_LSR_THRE ) )
574  {
575  break;
576  }
577 
578  // send byte
579  HAL_UART_TransmitByte( UARTx, ( *pChar++ ) );
580 
581  // update counter
582  bToSend--;
583  bSent++;
584  }
585  }
586 
587  // return
588  return bSent;
589 }
HAL_Status_Type HAL_UART_TransmitByte(UARTn_Type *UARTx, uint8_t Data)
Transmit a single data through UART peripheral.

References BLOCKING, and HAL_UART_TransmitByte().

Referenced by UARTPutChar().

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◆ HAL_UART_TransmitByte()

HAL_Status_Type HAL_UART_TransmitByte ( UARTn_Type *  UARTx,
uint8_t  Data 
)

Transmit a single data through UART peripheral.

Parameters
[in]UARTxPointer to the target UART
  • UART0 ~ UART1
[in]DataData to transmit (must be 8-bit long)
Returns
HAL_Status_Type

Definition at line 482 of file A31G12x_hal_uartn.c.

483 {
484  /* Check UART handle */
485  if( UARTx == NULL )
486  {
487  return HAL_ERROR;
488  }
489 
490  UARTx->THR = Data;
491 
492  return HAL_OK;
493 }

References HAL_ERROR, and HAL_OK.

Referenced by fputc(), and HAL_UART_Transmit().

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Variable Documentation

◆ InCount

int InCount

Definition at line 51 of file A31G12x_hal_uartn.c.

Referenced by getstring().

◆ InData

char InData[80]

Definition at line 49 of file A31G12x_hal_uartn.c.

Referenced by getstring().

◆ InFlag

int InFlag

Definition at line 50 of file A31G12x_hal_uartn.c.

Referenced by getstring().