A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
Data Structures | Functions | Variables
A31G11x_hal_i2cn.c File Reference

Contains all functions support for i2cn firmware library on A31G11x. More...

Go to the source code of this file.

Data Structures

struct  I2Cn_CFG_Type
 

Functions

int32_t I2Cn_getNum (I2Cn_Type *I2Cx)
 Convert from I2C peripheral to number. More...
 
int32_t I2Cn_MWait (I2Cn_Type *I2Cx)
 wait and return status in master mode More...
 
int32_t I2Cn_SWait (I2Cn_Type *I2Cx)
 wait and return status in slave mode More...
 
HAL_Status_Type HAL_I2C_Init (I2Cn_Type *I2Cx, uint32_t clockrate)
 Initialize the I2Cn peripheral with the specified parameters. More...
 
HAL_Status_Type HAL_I2C_DeInit (I2Cn_Type *I2Cx)
 Deinitialize the I2Cn peripheral registers to their default reset values. More...
 
HAL_Status_Type HAL_I2C_ConfigInterrupt (I2Cn_Type *I2Cx, Bool NewState)
 Enable/Disable interrupt for I2C peripheral. More...
 
HAL_Status_Type HAL_I2C_Slave_SetAddress1 (I2Cn_Type *I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState)
 Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct. More...
 
HAL_Status_Type HAL_I2C_Slave_SetAddress2 (I2Cn_Type *I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState)
 Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct. More...
 
uint32_t HAL_I2C_Master_GetState (I2Cn_Type *I2Cx)
 Get Status of Master Transfer. More...
 
uint32_t HAL_I2C_Slave_GetState (I2Cn_Type *I2Cx)
 Get Status of Slave Transfer. More...
 
HAL_Status_Type HAL_I2C_Master_IRQHandler_IT (I2Cn_Type *I2Cx)
 General Master Interrupt handler for I2C peripheral. More...
 
HAL_Status_Type HAL_I2C_Slave_IRQHandler_IT (I2Cn_Type *I2Cx)
 General Slave Interrupt handler for I2C peripheral. More...
 
Status HAL_I2C_MasterTransferData (I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
 Transmit and Receive data in master mode. More...
 
Status HAL_I2C_SlaveTransferData (I2Cn_Type *I2Cx, I2Cn_S_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
 Receive and Transmit data in slave mode. More...
 
Status HAL_I2C_Master_Transmit (I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
 Transmit an array of bytes in Master mode. More...
 
Status HAL_I2C_Master_Receive (I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
 Receive an array of bytes in Master mode. More...
 
Status HAL_I2C_Slave_Receive (I2Cn_Type *I2Cx, I2Cn_S_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
 Receive an array of bytes in Slave mode. More...
 

Variables

static I2Cn_CFG_Type i2cdat [I2Cn_MAX]
 I2Cn driver data. More...
 
static Bool I2Cn_MasterComplete [I2Cn_MAX]
 
static Bool I2Cn_SlaveComplete [I2Cn_MAX]
 

Detailed Description

Contains all functions support for i2cn firmware library on A31G11x.

Version
1.00
Date
2020-05-29
Author
ABOV Application Team

Copyright(C) 2019, ABOV Semiconductor All rights reserved.

ABOV Disclaimer

IMPORTANT NOTICE ? PLEASE READ CAREFULLY ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders. Purchasers are entirely responsible for the choice, selection, and use of ABOV products and ABOV assumes no liability for application assistance or the design of purchasers' products. No license, express or implied, to any intellectual property rights is granted by ABOV herein. ABOV disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications. ABOV and the ABOV logo are trademarks of ABOV. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces the information previously supplied in any former versions of this document. 2020 ABOV Semiconductor All rights reserved

Definition in file A31G11x_hal_i2cn.c.

Function Documentation

◆ HAL_I2C_ConfigInterrupt()

HAL_Status_Type HAL_I2C_ConfigInterrupt ( I2Cn_Type *  I2Cx,
Bool  NewState 
)

Enable/Disable interrupt for I2C peripheral.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]NewStateNext State of Interrupt Operation
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 366 of file A31G11x_hal_i2cn.c.

367 {
368  /* Check I2C handle */
369  if( I2Cx == NULL )
370  {
371  return HAL_ERROR;
372  }
373 
374  if( NewState )
375  {
376 #if 1 // supported
377  if( I2Cx == ( I2Cn_Type* )I2C0 )
378  {
379  NVIC_ClearPendingIRQ( I2C0_IRQn );
380  NVIC_EnableIRQ( I2C0_IRQn );
381  }
382 #endif
383 
384 #if 1 // supported
385  if( I2Cx == ( I2Cn_Type* )I2C1 )
386  {
387  NVIC_ClearPendingIRQ( I2C1_IRQn );
388  NVIC_EnableIRQ( I2C1_IRQn );
389  }
390 #endif
391 
392 #if 0 // not supported
393  if( I2Cx == ( I2Cn_Type* )I2C2 )
394  {
395  NVIC_ClearPendingIRQ( I2C2_IRQn );
396  NVIC_EnableIRQ( I2C2_IRQn );
397  }
398 #endif
399  }
400  else
401  {
402 #if 1 // supported
403  if( I2Cx == ( I2Cn_Type* )I2C0 )
404  {
405  NVIC_DisableIRQ( I2C0_IRQn );
406  }
407 #endif
408 
409 #if 1 // supported
410  if( I2Cx == ( I2Cn_Type* )I2C1 )
411  {
412  NVIC_DisableIRQ( I2C1_IRQn );
413  }
414 #endif
415 
416 #if 0 // not supported
417  if( I2Cx == ( I2Cn_Type* )I2C2 )
418  {
419  NVIC_DisableIRQ( I2C2_IRQn );
420  }
421 #endif
422  }
423 
424  return HAL_OK;
425 }

References HAL_ERROR, and HAL_OK.

Referenced by HAL_I2C_Master_IRQHandler_IT(), HAL_I2C_MasterTransferData(), HAL_I2C_Slave_IRQHandler_IT(), and HAL_I2C_SlaveTransferData().

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◆ HAL_I2C_DeInit()

HAL_Status_Type HAL_I2C_DeInit ( I2Cn_Type *  I2Cx)

Deinitialize the I2Cn peripheral registers to their default reset values.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
HAL_Status_Type

Definition at line 318 of file A31G11x_hal_i2cn.c.

319 {
320  /* Check I2C handle */
321  if( I2Cx == NULL )
322  {
323  return HAL_ERROR;
324  }
325 
326  /* Disable I2C control */
327  I2Cx->CR = 0; // I2C Block Disable
328 
329 #if 1 // supported
330  if( I2Cx == ( I2Cn_Type* )I2C0 )
331  {
332  /* Set up clock for I2C0 module */
333  SCUCG->PPCLKEN2_b.I2C0CLKE = 0;
334  }
335 #endif
336 
337 #if 1 // supported
338  if( I2Cx == ( I2Cn_Type* )I2C1 )
339  {
340  /* Set up clock for I2C1 module */
341  SCUCG->PPCLKEN2_b.I2C1CLKE = 0;
342  }
343 #endif
344 
345 #if 0 // not supported
346  if( I2Cx == ( I2Cn_Type* )I2C2 )
347  {
348  /* Set up clock for I2C2 module */
349  SCUCG->PPCLKEN2_b.I2C2CLKE = 0;
350  }
351 #endif
352 
353  return HAL_OK;
354 }

References HAL_ERROR, and HAL_OK.

◆ HAL_I2C_Init()

HAL_Status_Type HAL_I2C_Init ( I2Cn_Type *  I2Cx,
uint32_t  clockrate 
)

Initialize the I2Cn peripheral with the specified parameters.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]clockrateTarget Clock Rate (Hz)
Returns
HAL_Status_Type

Definition at line 259 of file A31G11x_hal_i2cn.c.

260 {
261  /* Check I2C handle */
262  if( I2Cx == NULL )
263  {
264  return HAL_ERROR;
265  }
266 
267 #if 1 // supported
268  if( I2Cx == ( I2Cn_Type* )I2C0 )
269  {
270  /* Set up clock for I2C0 module */
271  SCUCG->PPCLKEN2_b.I2C0CLKE = 1;
273  }
274 #endif
275 
276 #if 1 // supported
277  if( I2Cx == ( I2Cn_Type* )I2C1 )
278  {
279  /* Set up clock for I2C1 module */
280  SCUCG->PPCLKEN2_b.I2C1CLKE = 1;
282  }
283 #endif
284 
285 #if 0 // not supported
286  if( I2Cx == ( I2Cn_Type* )I2C2 )
287  {
288  /* Set up clock for I2C2 module */
289  SCUCG->PPCLKEN2_b.I2C2CLKE = 1;
291  }
292 #endif
293 
294  I2Cx->CR_b.I2CnEN = 1; // I2C Block Active
295  I2Cx->CR_b.I2CnIEN = 1; // I2C Interrupt Enable
296 
297 
298  I2Cx->SCLR = ( SystemPeriClock / clockrate - 4 ) / 8; // freq = PCLK / ((4*SCLL+2) + (4*SCLH+2))
299  I2Cx->SCHR = ( SystemPeriClock / clockrate - 4 ) / 8; // ex) 100k = 10M / ((4*12+2) + (4*12+2)), if PCLK : 10MHz
300 
301 
302 
303 
304  I2Cx->SDHR = 1; // default value 1
305 
306  I2Cx->CR_b.ACKnEN = 1; // ACK Signal Enable
307 
308  return HAL_OK;
309 }
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.

References HAL_ERROR, HAL_OK, and HAL_SCU_Peripheral_SetReset2().

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◆ HAL_I2C_Master_GetState()

uint32_t HAL_I2C_Master_GetState ( I2Cn_Type *  I2Cx)

Get Status of Master Transfer.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
Status of Master Transfer
  • TRUE, FALSE

Definition at line 485 of file A31G11x_hal_i2cn.c.

486 {
487  uint32_t retval, tmp;
488 
489  tmp = I2Cn_getNum( I2Cx );
490  retval = I2Cn_MasterComplete[tmp];
491  I2Cn_MasterComplete[tmp] = FALSE;
492 
493  return retval;
494 }
int32_t I2Cn_getNum(I2Cn_Type *I2Cx)
Convert from I2C peripheral to number.
static Bool I2Cn_MasterComplete[I2Cn_MAX]

References FALSE, I2Cn_getNum(), and I2Cn_MasterComplete.

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◆ HAL_I2C_Master_IRQHandler_IT()

HAL_Status_Type HAL_I2C_Master_IRQHandler_IT ( I2Cn_Type *  I2Cx)

General Master Interrupt handler for I2C peripheral.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
HAL_Status_Type

Definition at line 522 of file A31G11x_hal_i2cn.c.

523 {
524  int32_t tmp;
525  I2Cn_M_SETUP_Type* txrx_setup;
526  uint32_t status;
527 
528  /* Check I2C handle */
529  if( I2Cx == NULL )
530  {
531  return HAL_ERROR;
532  }
533 
534  tmp = I2Cn_getNum( I2Cx );
535  txrx_setup = ( I2Cn_M_SETUP_Type* )&i2cdat[tmp].txrx_setup_master;
536 
537  status = I2Cx->ST;
538 
539  switch( status )
540  {
541  case 0x87: // transmit mode - addr ACK
542  if( txrx_setup->tx_count < txrx_setup->tx_length )
543  {
544  I2Cx->DR = txrx_setup->tx_data[txrx_setup->tx_count];
545  txrx_setup->tx_count++;
546  }
547  else
548  {
549  I2Cx->CR = 0
550  | ( 1 << 7 ) // Enable I2C Block
551  | ( 1 << 5 ) // Interrupt Enable
552  | ( 1 << 1 ); // STOP
553  }
554  break;
555 
556  case 0x47: // transmit mode - data ACK
557  if( txrx_setup->tx_count < txrx_setup->tx_length )
558  {
559  I2Cx->DR = txrx_setup->tx_data[txrx_setup->tx_count];
560  txrx_setup->tx_count++;
561  }
562  else
563  {
564  if( txrx_setup->rx_count < txrx_setup->rx_length )
565  {
566  // load slave address and rw flag (SLA+RnW)
567  I2Cx->DR = ( ( txrx_setup->sl_addr7bit << 1 ) | 0x01 );
568 
569  // generate start condition
570  I2Cx->CR |= ( 1 << 0 ); // reSTART
571  }
572  else
573  {
574  I2Cx->CR = 0
575  | ( 1 << 7 ) // Enable I2C Block
576  | ( 1 << 5 ) // Interrupt Enable
577  | ( 1 << 1 ); // STOP
578  }
579  }
580  break;
581 
582  case 0x85: // receive mode - addr ACK
583  if( txrx_setup->rx_count < txrx_setup->rx_length )
584  {
585  if( ( txrx_setup->rx_length > 1 ) && ( txrx_setup->rx_count < ( txrx_setup->rx_length - 1 ) ) )
586  {
587  NOP();
588  }
589  else
590  {
591  I2Cx->CR_b.ACKnEN = 0; // disable ACKEN
592  }
593  }
594  else
595  {
596  I2Cx->CR = 0
597  | ( 1 << 7 ) // Enable I2C Block
598  | ( 1 << 5 ) // Interrupt Enable
599  | ( 1 << 1 ); // STOP
600  }
601  break;
602 
603  case 0x45: // receive mode - data ACK
604  if( txrx_setup->rx_count < txrx_setup->rx_length )
605  {
606  txrx_setup->rx_data[txrx_setup->rx_count] = I2Cx->DR;
607  txrx_setup->rx_count++;
608 
609  if( ( txrx_setup->rx_length > 1 ) && ( txrx_setup->rx_count < ( txrx_setup->rx_length - 1 ) ) )
610  {
611  NOP();
612  }
613  else
614  {
615  I2Cx->CR_b.ACKnEN = 0; // disable ACKEN
616  }
617  }
618  break;
619 
620  case 0x44: // receive mode - data NOACK
621  if( txrx_setup->rx_count < txrx_setup->rx_length )
622  {
623  txrx_setup->rx_data[txrx_setup->rx_count] = I2Cx->DR;
624  txrx_setup->rx_count++;
625 
626  I2Cx->CR = 0
627  | ( 1 << 7 ) // Enable I2C Block
628  | ( 1 << 5 ) // Interrupt Enable
629  | ( 1 << 1 ); // STOP
630  }
631  break;
632 
633  case 0x20: // receive mode
634  case 0x22: // transmit mode - stop receive
635  I2Cx->CR = 0
636  | ( 1 << 7 ) // Enable I2C Block
637  | ( 1 << 5 ) // Interrupt Enable
638  | ( 1 << 3 ); // ACK Signal Enable
639  goto s_int_end;
640 
641  default:
642  if( status & 0x08 ) // mastership lost
643  {
644 
645  }
646  break;
647  }
648 
649  I2Cx->ST = 0xff; // flag clear and SCL go to HIGH
650  return HAL_OK;
651 
652 s_int_end:
653 
654  I2Cx->ST = 0xff; // flag clear and SCL go to HIGH
655 
656  // Disable interrupt
658 
659  I2Cn_MasterComplete[tmp] = TRUE;
660 
661  return HAL_OK;
662 }
static I2Cn_CFG_Type i2cdat[I2Cn_MAX]
I2Cn driver data.
int32_t I2Cn_getNum(I2Cn_Type *I2Cx)
Convert from I2C peripheral to number.
static Bool I2Cn_MasterComplete[I2Cn_MAX]
HAL_Status_Type HAL_I2C_ConfigInterrupt(I2Cn_Type *I2Cx, Bool NewState)
Enable/Disable interrupt for I2C peripheral.

References FALSE, HAL_ERROR, HAL_I2C_ConfigInterrupt(), HAL_OK, i2cdat, I2Cn_getNum(), I2Cn_MasterComplete, I2Cn_M_SETUP_Type::rx_count, I2Cn_M_SETUP_Type::rx_data, I2Cn_M_SETUP_Type::rx_length, I2Cn_M_SETUP_Type::sl_addr7bit, TRUE, I2Cn_M_SETUP_Type::tx_count, I2Cn_M_SETUP_Type::tx_data, and I2Cn_M_SETUP_Type::tx_length.

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◆ HAL_I2C_Master_Receive()

Status HAL_I2C_Master_Receive ( I2Cn_Type *  I2Cx,
I2Cn_M_SETUP_Type TransferCfg,
I2Cn_TRANSFER_OPT_Type  Opt 
)

Receive an array of bytes in Master mode.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]TransferCfgPointer to a I2Cn_M_SETUP_Type structure that contains specified information about the configuration for master transfer.
[in]OptI2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
Returns
Result
  • SUCCESS, ERROR

Definition at line 1078 of file A31G11x_hal_i2cn.c.

1079 {
1080  TransferCfg->tx_data = NULL;
1081  TransferCfg->tx_length = 0;
1082  TransferCfg->tx_count = 0;
1083  TransferCfg->rx_count = 0;
1084 
1085  return HAL_I2C_MasterTransferData( I2Cx, TransferCfg, Opt );
1086 }
Status HAL_I2C_MasterTransferData(I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Transmit and Receive data in master mode.

References HAL_I2C_MasterTransferData(), I2Cn_M_SETUP_Type::rx_count, I2Cn_M_SETUP_Type::tx_count, I2Cn_M_SETUP_Type::tx_data, and I2Cn_M_SETUP_Type::tx_length.

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◆ HAL_I2C_Master_Transmit()

Status HAL_I2C_Master_Transmit ( I2Cn_Type *  I2Cx,
I2Cn_M_SETUP_Type TransferCfg,
I2Cn_TRANSFER_OPT_Type  Opt 
)

Transmit an array of bytes in Master mode.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]TransferCfgPointer to a I2Cn_M_SETUP_Type structure that contains specified information about the configuration for master transfer.
[in]OptI2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
Returns
Result
  • SUCCESS, ERROR

Definition at line 1055 of file A31G11x_hal_i2cn.c.

1056 {
1057  TransferCfg->rx_data = NULL;
1058  TransferCfg->rx_length = 0;
1059  TransferCfg->tx_count = 0;
1060  TransferCfg->rx_count = 0;
1061 
1062  return HAL_I2C_MasterTransferData( I2Cx, TransferCfg, Opt );
1063 }
Status HAL_I2C_MasterTransferData(I2Cn_Type *I2Cx, I2Cn_M_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Transmit and Receive data in master mode.

References HAL_I2C_MasterTransferData(), I2Cn_M_SETUP_Type::rx_count, I2Cn_M_SETUP_Type::rx_data, I2Cn_M_SETUP_Type::rx_length, and I2Cn_M_SETUP_Type::tx_count.

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◆ HAL_I2C_MasterTransferData()

Status HAL_I2C_MasterTransferData ( I2Cn_Type *  I2Cx,
I2Cn_M_SETUP_Type TransferCfg,
I2Cn_TRANSFER_OPT_Type  Opt 
)

Transmit and Receive data in master mode.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]TransferCfgPointer to a I2Cn_M_SETUP_Type structure that contains specified information about the configuration for master transfer.
[in]OptI2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
Returns
Result
  • SUCCESS, ERROR

Definition at line 741 of file A31G11x_hal_i2cn.c.

742 {
743  int32_t tmp;
744  uint32_t exitflag;
745  int32_t Ret;
746 
747  // Reset I2C setup value to default state
748  TransferCfg->tx_count = 0;
749  TransferCfg->rx_count = 0;
750 
751  while( I2Cx->ST & 0x04 ); // busy check
752 
753  if( Opt == I2Cn_TRANSFER_POLLING )
754  {
755  // init count
756  TransferCfg->tx_count = 0;
757  TransferCfg->rx_count = 0;
758 
759  // tx transfer
760  if( TransferCfg->tx_count < TransferCfg->tx_length )
761  {
762  // generate start condition
763  I2Cx->DR = ( TransferCfg->sl_addr7bit << 1 ); // load slave address and write flag (SLA+RnW)
764  I2Cx->CR |= ( 1 << 0 ); // START
765  Ret = I2Cn_MWait( I2Cx );
766  if( ( Ret != TRANS_MODE ) )
767  {
768  // generate stop condition
769  I2Cx->CR |= ( 1 << 1 ); // STOP
770  I2Cn_MWait( I2Cx );
771  I2Cx->ST = 0xFF;
772  I2Cx->CR = 0
773  | ( 1 << 7 ) // I2C Block Enable
774  | ( 1 << 5 ) // Interrupt Enable
775  | ( 1 << 3 ); // ACK Signal Enable
776 
777  // return
778  return ERROR;
779  }
780 
781  // tx data
782  exitflag = 1;
783  while( exitflag )
784  {
785  if( TransferCfg->tx_count < TransferCfg->tx_length )
786  {
787  // tx byte
788  I2Cx->DR = TransferCfg->tx_data[TransferCfg->tx_count];
789  TransferCfg->tx_count++;
790  I2Cx->ST = 0xFF;
791  Ret = I2Cn_MWait( I2Cx );
792  if( ( Ret != TRANS_DATA ) )
793  {
794  // generate stop condition
795  I2Cx->CR |= ( 1 << 1 ); // STOP
796  I2Cn_MWait( I2Cx );
797  I2Cx->ST = 0xFF;
798  I2Cx->CR = 0
799  | ( 1 << 7 ) // I2C Block Enable
800  | ( 1 << 5 ) // Interrupt Enable
801  | ( 1 << 3 ); // ACK Signal Enable
802 
803  // return
804  return ERROR;
805  }
806  }
807  else
808  {
809  if( TransferCfg->rx_count >= TransferCfg->rx_length )
810  {
811  // generate stop condition
812  I2Cx->CR |= ( 1 << 1 ); // STOP
813  I2Cx->ST = 0xFF;
814  I2Cn_MWait( I2Cx );
815  I2Cx->ST = 0xFF;
816  I2Cx->CR = 0
817  | ( 1 << 7 ) // I2C Block Enable
818  | ( 1 << 5 ) // Interrupt Enable
819  | ( 1 << 3 ); // ACK Signal Enable
820 
821  // return
822  return SUCCESS;
823  }
824  else
825  {
826  exitflag = 0;
827  }
828  }
829  }
830  }
831 
832  // rx transfer
833  if( TransferCfg->rx_count < TransferCfg->rx_length )
834  {
835  // generate start condition
836  I2Cx->DR = ( ( TransferCfg->sl_addr7bit << 1 ) | 0x01 ); // load slave address and read flag (SLA+RnW)
837  I2Cx->CR |= ( 1 << 0 ); // START
838  I2Cx->ST = 0xFF;
839  Ret = I2Cn_MWait( I2Cx );
840  if( ( Ret != RECEIVE_MODE ) )
841  {
842  // generate stop condition
843  I2Cx->CR |= ( 1 << 1 ); // STOP
844  I2Cn_MWait( I2Cx );
845  I2Cx->ST = 0xFF;
846  I2Cx->CR = 0
847  | ( 1 << 7 ) // I2C Block Enable
848  | ( 1 << 5 ) // Interrupt Enable
849  | ( 1 << 3 ); // ACK Signal Enable
850 
851  // return
852  return ERROR;
853  }
854 
855  // rx data
856  exitflag = 1;
857  while( exitflag )
858  {
859  if( ( TransferCfg->rx_length > 1 ) && ( TransferCfg->rx_count < ( TransferCfg->rx_length - 1 ) ) )
860  {
861  // rx byte
862  I2Cx->ST = 0xFF;
863  Ret = I2Cn_MWait( I2Cx );
864  if( ( Ret != RECEIVE_DATA ) )
865  {
866  // generate stop condition
867  I2Cx->CR |= ( 1 << 1 ); // STOP
868  I2Cn_MWait( I2Cx );
869  I2Cx->ST = 0xFF;
870  I2Cx->CR = 0
871  | ( 1 << 7 ) // I2C Block Enable
872  | ( 1 << 5 ) // Interrupt Enable
873  | ( 1 << 3 ); // ACK Signal Enable
874 
875  // return
876  return ERROR;
877  }
878  }
879  else // the next byte is the last byte, send NACK instead.
880  {
881  // generate nack
882  I2Cx->CR &= ~( 1 << 3 ); // ACK Signal Disable
883 
884  // rx byte
885  I2Cx->ST = 0xFF;
886  Ret = I2Cn_MWait( I2Cx );
887  if( ( Ret != RECEIVE_DATA ) )
888  {
889  // generate stop condition
890  I2Cx->CR |= ( 1 << 1 ); // STOP
891  I2Cn_MWait( I2Cx );
892  I2Cx->CR = 0
893  | ( 1 << 7 ) // I2C Block Enable
894  | ( 1 << 5 ) // Interrupt Enable
895  | ( 1 << 3 ); // ACK Signal Enable
896 
897  // return
898  return ERROR;
899  }
900  }
901  TransferCfg->rx_data[TransferCfg->rx_count] = I2Cx->DR;
902  TransferCfg->rx_count++;
903  if( TransferCfg->rx_count == TransferCfg->rx_length )
904  {
905  exitflag = 0;
906  // commented by kth return SUCCESS;
907  }
908  }
909 
910  // generate stop condition
911  I2Cx->CR |= ( 1 << 1 ); // STOP
912  I2Cx->ST = 0xFF;
913  I2Cn_MWait( I2Cx );
914  I2Cx->ST = 0xFF;
915  I2Cx->CR = 0
916  | ( 1 << 7 ) // I2C Block Enable
917  | ( 1 << 5 ) // Interrupt Enable
918  | ( 1 << 3 ); // ACK Signal Enable
919 
920  // return
921  return SUCCESS;
922  }
923  }
924  else if( Opt == I2Cn_TRANSFER_INTERRUPT )
925  {
926  // clear flag
927  tmp = I2Cn_getNum( I2Cx );
928  I2Cn_MasterComplete[tmp] = FALSE;
929 
930  // Setup tx_rx data, callback and interrupt handler
931  i2cdat[tmp].txrx_setup_master = *TransferCfg;
932 
933  // Set direction phase, write first
934  i2cdat[tmp].dir = 0;
935 
936  // enable interrupt
937  HAL_I2C_ConfigInterrupt( I2Cx, TRUE );
938 
939  // generate start condition
940  if( TransferCfg->tx_count < TransferCfg->tx_length )
941  {
942  I2Cx->DR = ( TransferCfg->sl_addr7bit << 1 ); // load slave address and write flag (SLA+RnW)
943  }
944  else if( TransferCfg->rx_count < TransferCfg->rx_length )
945  {
946  I2Cx->DR = ( ( TransferCfg->sl_addr7bit << 1 ) | 0x01 ); // load slave address and read flag (SLA+RnW)
947  }
948  I2Cx->CR |= ( 1 << 0 ); // START
949 
950  // return
951  return SUCCESS;
952  }
953 
954  // return
955  return ERROR;
956 }
static I2Cn_CFG_Type i2cdat[I2Cn_MAX]
I2Cn driver data.
I2Cn_M_SETUP_Type txrx_setup_master
int32_t I2Cn_MWait(I2Cn_Type *I2Cx)
wait and return status in master mode
int32_t I2Cn_getNum(I2Cn_Type *I2Cx)
Convert from I2C peripheral to number.
static Bool I2Cn_MasterComplete[I2Cn_MAX]
HAL_Status_Type HAL_I2C_ConfigInterrupt(I2Cn_Type *I2Cx, Bool NewState)
Enable/Disable interrupt for I2C peripheral.

References I2Cn_CFG_Type::dir, ERROR, FALSE, HAL_I2C_ConfigInterrupt(), i2cdat, I2Cn_getNum(), I2Cn_MasterComplete, I2Cn_MWait(), I2Cn_TRANSFER_INTERRUPT, I2Cn_TRANSFER_POLLING, I2Cn_M_SETUP_Type::rx_count, I2Cn_M_SETUP_Type::rx_data, I2Cn_M_SETUP_Type::rx_length, I2Cn_M_SETUP_Type::sl_addr7bit, SUCCESS, TRUE, I2Cn_M_SETUP_Type::tx_count, I2Cn_M_SETUP_Type::tx_data, I2Cn_M_SETUP_Type::tx_length, and I2Cn_CFG_Type::txrx_setup_master.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Master_Transmit().

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◆ HAL_I2C_Slave_GetState()

uint32_t HAL_I2C_Slave_GetState ( I2Cn_Type *  I2Cx)

Get Status of Slave Transfer.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
Status of Slave Transfer
  • TRUE, FALSE

Definition at line 504 of file A31G11x_hal_i2cn.c.

505 {
506  uint32_t retval, tmp;
507 
508  tmp = I2Cn_getNum( I2Cx );
509  retval = I2Cn_SlaveComplete[tmp];
510  I2Cn_SlaveComplete[tmp] = FALSE;
511 
512  return retval;
513 }
static Bool I2Cn_SlaveComplete[I2Cn_MAX]
int32_t I2Cn_getNum(I2Cn_Type *I2Cx)
Convert from I2C peripheral to number.

References FALSE, I2Cn_getNum(), and I2Cn_SlaveComplete.

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◆ HAL_I2C_Slave_IRQHandler_IT()

HAL_Status_Type HAL_I2C_Slave_IRQHandler_IT ( I2Cn_Type *  I2Cx)

General Slave Interrupt handler for I2C peripheral.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
HAL_Status_Type

Definition at line 671 of file A31G11x_hal_i2cn.c.

672 {
673  int32_t tmp;
674  I2Cn_S_SETUP_Type* txrx_setup;
675  uint32_t status;
676 
677  /* Check I2C handle */
678  if( I2Cx == NULL )
679  {
680  return HAL_ERROR;
681  }
682 
683  tmp = I2Cn_getNum( I2Cx );
684  txrx_setup = ( I2Cn_S_SETUP_Type* )&i2cdat[tmp].txrx_setup_slave;
685 
686  status = I2Cx->ST;
687  switch( status )
688  {
689  case 0x15: // receive mode - slave select + ACK
690  case 0x45: // receive mode - data ACK
691  if( ( txrx_setup->rx_count < txrx_setup->rx_length ) && ( txrx_setup->rx_data != NULL ) )
692  {
693  txrx_setup->rx_data[txrx_setup->rx_count] = I2Cx->DR;
694  txrx_setup->rx_count++;
695  }
696  break;
697 
698  case 0x20: // receive mode
699  case 0x22: // transmit mode - stop receive
700  goto s_int_end;
701 
702  case 0x17: // transmit mode - slave select + ACK
703  case 0x46: // transmit mode - data NOACK
704  case 0x47: // transmit mode - data ACK
705  if( ( txrx_setup->tx_count < txrx_setup->tx_length ) && ( txrx_setup->tx_data != NULL ) )
706  {
707  I2Cx->DR = txrx_setup->tx_data[txrx_setup->tx_count];
708  txrx_setup->tx_count++;
709  }
710  break;
711  }
712 
713  I2Cx->ST = 0xff; // flag clear and SCL go to HIGH
714  return HAL_OK;
715 
716 s_int_end:
717 
718  I2Cx->ST = 0xff; // flag clear and SCL go to HIGH
719 
720  // Disable interrupt
722 
723  I2Cn_SlaveComplete[tmp] = TRUE;
724 
725  return HAL_OK;
726 }
static I2Cn_CFG_Type i2cdat[I2Cn_MAX]
I2Cn driver data.
static Bool I2Cn_SlaveComplete[I2Cn_MAX]
int32_t I2Cn_getNum(I2Cn_Type *I2Cx)
Convert from I2C peripheral to number.
HAL_Status_Type HAL_I2C_ConfigInterrupt(I2Cn_Type *I2Cx, Bool NewState)
Enable/Disable interrupt for I2C peripheral.

References FALSE, HAL_ERROR, HAL_I2C_ConfigInterrupt(), HAL_OK, i2cdat, I2Cn_getNum(), I2Cn_SlaveComplete, I2Cn_S_SETUP_Type::rx_count, I2Cn_S_SETUP_Type::rx_data, I2Cn_S_SETUP_Type::rx_length, TRUE, I2Cn_S_SETUP_Type::tx_count, I2Cn_S_SETUP_Type::tx_data, and I2Cn_S_SETUP_Type::tx_length.

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◆ HAL_I2C_Slave_Receive()

Status HAL_I2C_Slave_Receive ( I2Cn_Type *  I2Cx,
I2Cn_S_SETUP_Type TransferCfg,
I2Cn_TRANSFER_OPT_Type  Opt 
)

Receive an array of bytes in Slave mode.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]TransferCfgPointer to a I2Cn_S_SETUP_Type structure that contains specified information about the configuration for slave transfer.
[in]OptI2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
Returns
Result
  • SUCCESS, ERROR

Definition at line 1101 of file A31G11x_hal_i2cn.c.

1102 {
1103  TransferCfg->tx_data = NULL;
1104  TransferCfg->tx_length = 0;
1105  TransferCfg->tx_count = 0;
1106  TransferCfg->rx_count = 0;
1107 
1108  return HAL_I2C_SlaveTransferData( I2Cx, TransferCfg, Opt );
1109 }
Status HAL_I2C_SlaveTransferData(I2Cn_Type *I2Cx, I2Cn_S_SETUP_Type *TransferCfg, I2Cn_TRANSFER_OPT_Type Opt)
Receive and Transmit data in slave mode.

References HAL_I2C_SlaveTransferData(), I2Cn_S_SETUP_Type::rx_count, I2Cn_S_SETUP_Type::tx_count, I2Cn_S_SETUP_Type::tx_data, and I2Cn_S_SETUP_Type::tx_length.

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◆ HAL_I2C_Slave_SetAddress1()

HAL_Status_Type HAL_I2C_Slave_SetAddress1 ( I2Cn_Type *  I2Cx,
uint8_t  SlaveAddr_7bit,
uint8_t  GeneralCallState 
)

Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]SlaveAddr_7bitown slave address
[in]GeneralCallState
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 439 of file A31G11x_hal_i2cn.c.

440 {
441  /* Check I2C handle */
442  if( I2Cx == NULL )
443  {
444  return HAL_ERROR;
445  }
446 
447  I2Cx->SAR1 = ( ( ( uint32_t )( SlaveAddr_7bit << 1 ) ) | ( ( GeneralCallState == ENABLE ) ? 0x01 : 0x00 ) ) & I2Cn_SLA_BITMASK;
448 
449  return HAL_OK;
450 }

References ENABLE, HAL_ERROR, and HAL_OK.

◆ HAL_I2C_Slave_SetAddress2()

HAL_Status_Type HAL_I2C_Slave_SetAddress2 ( I2Cn_Type *  I2Cx,
uint8_t  SlaveAddr_7bit,
uint8_t  GeneralCallState 
)

Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]SlaveAddr_7bitown slave address
[in]GeneralCallState
  • ENABLE, DISABLE
Returns
HAL_Status_Type

Definition at line 464 of file A31G11x_hal_i2cn.c.

465 {
466  /* Check I2C handle */
467  if( I2Cx == NULL )
468  {
469  return HAL_ERROR;
470  }
471 
472  I2Cx->SAR2 = ( ( ( uint32_t )( SlaveAddr_7bit << 1 ) ) | ( ( GeneralCallState == ENABLE ) ? 0x01 : 0x00 ) ) & I2Cn_SLA_BITMASK;
473 
474  return HAL_OK;
475 }

References ENABLE, HAL_ERROR, and HAL_OK.

◆ HAL_I2C_SlaveTransferData()

Status HAL_I2C_SlaveTransferData ( I2Cn_Type *  I2Cx,
I2Cn_S_SETUP_Type TransferCfg,
I2Cn_TRANSFER_OPT_Type  Opt 
)

Receive and Transmit data in slave mode.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
[in]TransferCfgPointer to a I2Cn_S_SETUP_Type structure that contains specified information about the configuration for master transfer.
[in]OptI2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
Returns
Result
  • SUCCESS, ERROR

Definition at line 971 of file A31G11x_hal_i2cn.c.

972 {
973  int32_t tmp;
974  int32_t Ret;
975 
976  // Reset I2C setup value to default state
977  TransferCfg->tx_count = 0;
978  TransferCfg->rx_count = 0;
979 
980  // Polling option
981  if( Opt == I2Cn_TRANSFER_POLLING )
982  {
983  while( 1 )
984  {
985  Ret = I2Cn_SWait( I2Cx ); // Start
986  switch( Ret )
987  {
988  case RECEIVE_MODE:
989  case RECEIVE_DATA:
990  if( ( TransferCfg->rx_count < TransferCfg->rx_length ) && ( TransferCfg->rx_data != NULL ) )
991  {
992  TransferCfg->rx_data[TransferCfg->rx_count] = I2Cx->DR;
993  TransferCfg->rx_count++;
994  }
995  break;
996  case TRANS_MODE:
997  case TRANS_DATA:
998  if( ( TransferCfg->tx_count < TransferCfg->tx_length ) && ( TransferCfg->tx_data != NULL ) )
999  {
1000  I2Cx->DR = TransferCfg->tx_data[TransferCfg->tx_count];
1001  TransferCfg->tx_count++;
1002  }
1003  break;
1004  case STOP_DECT:
1005  goto s_end_stage;
1006  case 0:
1007  break;
1008  default:
1009  goto s_error;
1010  }
1011  }
1012 
1013 s_end_stage:
1014  I2Cx->ST = 0xFF;
1015  return SUCCESS;
1016 
1017 s_error:
1018  I2Cx->ST = 0xFF;
1019  return ERROR;
1020  }
1021 
1022  else if( Opt == I2Cn_TRANSFER_INTERRUPT )
1023  {
1024  tmp = I2Cn_getNum( I2Cx );
1025  I2Cn_SlaveComplete[tmp] = FALSE;
1026 
1027  // Setup tx_rx data, callback and interrupt handler
1028  i2cdat[tmp].txrx_setup_slave = *TransferCfg;
1029 
1030  // Set direction phase, read first
1031  i2cdat[tmp].dir = 1;
1032 
1033  HAL_I2C_ConfigInterrupt( I2Cx, TRUE );
1034 
1035  return SUCCESS;
1036  }
1037 
1038  // return
1039  return ERROR;
1040 }
static I2Cn_CFG_Type i2cdat[I2Cn_MAX]
I2Cn driver data.
static Bool I2Cn_SlaveComplete[I2Cn_MAX]
I2Cn_S_SETUP_Type txrx_setup_slave
int32_t I2Cn_getNum(I2Cn_Type *I2Cx)
Convert from I2C peripheral to number.
int32_t I2Cn_SWait(I2Cn_Type *I2Cx)
wait and return status in slave mode
HAL_Status_Type HAL_I2C_ConfigInterrupt(I2Cn_Type *I2Cx, Bool NewState)
Enable/Disable interrupt for I2C peripheral.

References I2Cn_CFG_Type::dir, ERROR, FALSE, HAL_I2C_ConfigInterrupt(), i2cdat, I2Cn_getNum(), I2Cn_SlaveComplete, I2Cn_SWait(), I2Cn_TRANSFER_INTERRUPT, I2Cn_TRANSFER_POLLING, I2Cn_S_SETUP_Type::rx_count, I2Cn_S_SETUP_Type::rx_data, I2Cn_S_SETUP_Type::rx_length, SUCCESS, TRUE, I2Cn_S_SETUP_Type::tx_count, I2Cn_S_SETUP_Type::tx_data, I2Cn_S_SETUP_Type::tx_length, and I2Cn_CFG_Type::txrx_setup_slave.

Referenced by HAL_I2C_Slave_Receive().

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◆ I2Cn_getNum()

int32_t I2Cn_getNum ( I2Cn_Type *  I2Cx)

Convert from I2C peripheral to number.

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
I2C number or error code, could be:
  • 0: I2C0
  • 1: I2C1
  • (-1): Error

Definition at line 94 of file A31G11x_hal_i2cn.c.

95 {
96 #if 1 // supported
97  if( I2Cx == ( I2Cn_Type* )I2C0 )
98  {
99  return 0;
100  }
101 #endif
102 
103 #if 1 // supported
104  if( I2Cx == ( I2Cn_Type* )I2C1 )
105  {
106  return 1;
107  }
108 #endif
109 
110 #if 0 // not supported
111  if( I2Cx == ( I2Cn_Type* )I2C2 )
112  {
113  return 2;
114  }
115 #endif
116 
117  return -1;
118 }

Referenced by HAL_I2C_Master_GetState(), HAL_I2C_Master_IRQHandler_IT(), HAL_I2C_MasterTransferData(), HAL_I2C_Slave_GetState(), HAL_I2C_Slave_IRQHandler_IT(), and HAL_I2C_SlaveTransferData().

◆ I2Cn_MWait()

int32_t I2Cn_MWait ( I2Cn_Type *  I2Cx)

wait and return status in master mode

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
Status

Definition at line 127 of file A31G11x_hal_i2cn.c.

128 {
129  uint32_t tmp;
130  int32_t ret = 0;
131 
132  while( 1 ) // Interrupt Status Check
133  {
134  if( ( I2Cx->CR & I2Cn_CR_I2CnIFLAG_Msk ) != 0 )
135  {
136  break;
137  }
138  }
139 
140  tmp = I2Cx->ST;
141  I2Cx->ST = 0xFF;
142 
143  switch( tmp )
144  {
145  // Transmitter mode
146  case 0x87:
147  ret = TRANS_MODE;
148  break;
149 
150  // Receive mode
151  case 0x85:
152  ret = RECEIVE_MODE;
153  break;
154 
155  // Transed Data
156  case 0x47:
157  ret = TRANS_DATA;
158  break;
159 
160  // Received Data
161  case 0x44:
162  case 0x45:
163  ret = RECEIVE_DATA;
164  break;
165 
166  default:
167  if( ( tmp ) & 0x08 )
168  {
169  ret = LOST_BUS; // lost
170  }
171  else if( ( tmp ) & 0x20 )
172  {
173  ret = STOP_DECT; // stop
174  }
175  else
176  {
177  ret = -1;
178  }
179  break;
180  }
181 
182  return ret;
183 }

Referenced by HAL_I2C_MasterTransferData().

◆ I2Cn_SWait()

int32_t I2Cn_SWait ( I2Cn_Type *  I2Cx)

wait and return status in slave mode

Parameters
[in]I2CxPointer to the target I2C
  • I2C0 ~ I2C1
Returns
Status

Definition at line 192 of file A31G11x_hal_i2cn.c.

193 {
194  uint32_t tmp;
195  int32_t ret = 0;
196 
197  while( 1 ) // Interrupt Status Check
198  {
199  if( ( I2Cx->CR & I2Cn_CR_I2CnIFLAG_Msk ) != 0 )
200  {
201  break;
202  }
203  }
204 
205  tmp = I2Cx->ST;
206  I2Cx->ST = 0xFF;
207 
208  switch( tmp )
209  {
210  // Receive mode
211  case 0x15:
212  case 0x95:
213  ret = RECEIVE_MODE;
214  break;
215 
216  // Transmitter mode
217  case 0x17:
218  case 0x97:
219  ret = TRANS_MODE;
220  break;
221 
222  // Received Data
223  case 0x45:
224  ret = RECEIVE_DATA;
225  break;
226 
227  // Transed Data
228  case 0x47:
229  ret = TRANS_DATA;
230  break;
231  default:
232  if( tmp & 0x08 )
233  {
234  ret = LOST_BUS; // lost
235  }
236  else if( tmp & 0x20 )
237  {
238  ret = STOP_DECT; // stop
239  }
240  else
241  {
242  ret = -1;
243  }
244  break;
245  }
246 
247  return ret;
248 }

Referenced by HAL_I2C_SlaveTransferData().

Variable Documentation

◆ i2cdat

I2Cn_CFG_Type i2cdat[I2Cn_MAX]
static

◆ I2Cn_MasterComplete

Bool I2Cn_MasterComplete[I2Cn_MAX]
static

◆ I2Cn_SlaveComplete

Bool I2Cn_SlaveComplete[I2Cn_MAX]
static