A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G11x_hal_uartn.c
Go to the documentation of this file.
1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31G11x_hal_scu.h"
41 #include "A31G11x_hal_uartn.h"
42 
43 //******************************************************************************
44 // Variable
45 //******************************************************************************
46 
47 static uint32_t UARTn_BaseClock;
48 
49 char InData[80];
50 int InFlag;
51 int InCount;
52 
53 /* Public Functions --------------------------------------------------------- */
54 //******************************************************************************
55 // Function
56 //******************************************************************************
57 
58 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
67 static void uart_set_divisors( UARTn_Type* UARTx, uint32_t baudrate )
68 {
69  uint32_t numerator;
70  uint32_t denominator;
71  uint32_t bdr, bfr;
72  uint32_t fd;
73 
74  //--------------------------------------
75  // bdr = UARTn_BaseClock / (16 * baudrate * 2)
76  //--------------------------------------
77  numerator = UARTn_BaseClock;
78  denominator = 16 * baudrate * 2;
79  bdr = numerator / denominator;
80 
81  //--------------------------------------
82  // fd = numerator - bdr * denominator
83  // bfr = (numerator / denominator - bdr) * 256
84  // = (numerator - bdr * denominator) * 256 / denominator
85  // = fd * 256 / denominator
86  //--------------------------------------
87  fd = numerator - bdr * denominator;
88  bfr = ( fd * 256 ) / denominator;
89  UARTx->BDR = ( uint16_t )( bdr & 0xffff );
90  UARTx->BFR = ( uint8_t )( bfr & 0xff );
91 }
92 
93 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
103 HAL_Status_Type HAL_UART_Init( UARTn_Type* UARTx, UARTn_CFG_Type* UARTn_Config )
104 {
105  uint8_t tmp;
106 
107  /* Check UART handle */
108  if( UARTx == NULL )
109  {
110  return HAL_ERROR;
111  }
112 
113 #if 1 // supported
114  if( UARTx == ( UARTn_Type* )UART0 )
115  {
116  /* Set up peripheral clock for UART0 module */
117  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT0CLKE, PPxCLKE_Enable );
118  }
119 #endif
120 
121 #if 1 // supported
122  if( UARTx == ( UARTn_Type* )UART1 )
123  {
124  /* Set up peripheral clock for UART1 module */
125  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT1CLKE, PPxCLKE_Enable );
126  }
127 #endif
128 
129  // Dummy reading
130  while( UARTx->LSR & UARTn_LSR_RDR )
131  {
132  tmp = UARTx->RBR;
133  }
134  // Wait for current transmit complete
135  while( !( UARTx->LSR & UARTn_LSR_THRE ) );
136 
137  // Disable interrupt
138  UARTx->IER = 0;
139  // Set LCR, DCR to default state
140  UARTx->LCR = 0;
141  UARTx->DCR = 0;
142  // Dummy reading
143  tmp = UARTx->LSR;
144  tmp = UARTx->IIR;
145 
146  // uart clock set
147  // SCU->MCCR7 &=0xffff0000;
148  // SCU->MCCR7 |=((4<<8)|(2)); // MCLK
149  UARTn_BaseClock = SystemPeriClock;
150 
151  // Set Line Control register ----------------------------
152  uart_set_divisors( UARTx, ( UARTn_Config->Baudrate ) );
153 
154  tmp = ( UARTx->LCR & UARTn_LCR_BREAK_EN ) & UARTn_LCR_BITMASK;
155 
156  switch( UARTn_Config->Databits )
157  {
158  case UARTn_DATA_BIT_5:
159  tmp |= UARTn_LCR_WLEN5;
160  break;
161  case UARTn_DATA_BIT_6:
162  tmp |= UARTn_LCR_WLEN6;
163  break;
164  case UARTn_DATA_BIT_7:
165  tmp |= UARTn_LCR_WLEN7;
166  break;
167  case UARTn_DATA_BIT_8:
168  default:
169  tmp |= UARTn_LCR_WLEN8;
170  break;
171  }
172 
173  if( UARTn_Config->Parity == UARTn_PARITY_BIT_NONE )
174  {
175  // Do nothing...
176  }
177  else
178  {
179  tmp |= UARTn_LCR_PARITY_EN;
180  switch( UARTn_Config->Parity )
181  {
183  tmp |= UARTn_LCR_PARITY_ODD;
184  break;
185 
187  tmp |= UARTn_LCR_PARITY_EVEN;
188  break;
189 
191  tmp |= UARTn_LCR_PARITY_F_1;
192  break;
193 
195  tmp |= UARTn_LCR_PARITY_F_0;
196  break;
197  default:
198  break;
199  }
200  }
201 
202  switch( UARTn_Config->Stopbits )
203  {
204  case UARTn_STOP_BIT_2:
205  tmp |= UARTn_LCR_STOPBIT_SEL;
206  break;
207  case UARTn_STOP_BIT_1:
208  default:
209  // Do no thing
210  break;
211  }
212 
213  UARTx->LCR = ( uint8_t )( tmp & UARTn_LCR_BITMASK );
214 
215  return HAL_OK;
216 }
217 
218 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
225 HAL_Status_Type HAL_UART_DeInit( UARTn_Type* UARTx )
226 {
227  /* Check UART handle */
228  if( UARTx == NULL )
229  {
230  return HAL_ERROR;
231  }
232 
233 #if 1 // supported
234  if( UARTx == ( UARTn_Type* )UART0 )
235  {
236  /* Set up peripheral clock for UART0 module */
238  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT0CLKE, PPxCLKE_Disable );
239  }
240 #endif
241 
242 #if 1 // supported
243  if( UARTx == ( UARTn_Type* )UART1 )
244  {
245  /* Set up peripheral clock for UART1 module */
247  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT1CLKE, PPxCLKE_Disable );
248  }
249 #endif
250 
251  return HAL_OK;
252 }
253 
254 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
265 {
266  /* Check UARTn_Config */
267  if( UARTn_Config == NULL )
268  {
269  return HAL_ERROR;
270  }
271 
272  UARTn_Config->Baudrate = 38400;
273  UARTn_Config->Databits = UARTn_DATA_BIT_8;
274  UARTn_Config->Parity = UARTn_PARITY_BIT_NONE;
275  UARTn_Config->Stopbits = UARTn_STOP_BIT_1;
276 
277  return HAL_OK;
278 }
279 
280 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
297 HAL_Status_Type HAL_UART_ConfigInterrupt( UARTn_Type* UARTx, UARTn_INT_Type UARTn_IntCfg, FunctionalState NewState )
298 {
299  uint32_t tmp;
300 
301  /* Check UART handle */
302  if( UARTx == NULL )
303  {
304  return HAL_ERROR;
305  }
306 
307  switch( UARTn_IntCfg )
308  {
309  case UARTn_INTCFG_RBR:
310  tmp = UARTn_IER_RBRINT_EN;
311  break;
312  case UARTn_INTCFG_THRE:
313  tmp = UARTn_IER_THREINT_EN;
314  break;
315  case UARTn_INTCFG_RLS:
316  tmp = UARTn_IER_RLSINT_EN;
317  break;
318  case UARTn_INTCFG_TXE:
319  tmp = UARTn_IER_TXE_EN;
320  break;
321  }
322 
323  if( NewState == ENABLE )
324  {
325  UARTx->IER |= tmp;
326  }
327  else
328  {
329  UARTx->IER &= ( ~tmp ) & UARTn_IER_BITMASK;
330  }
331 
332  return HAL_OK;
333 }
334 
335 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
351 {
352  uint8_t tmp;
353 
354  /* Check UART handle */
355  if( UARTx == NULL )
356  {
357  return HAL_ERROR;
358  }
359 
360  switch( Mode )
361  {
363  tmp = UARTn_DCR_LBON;
364  break;
366  tmp = UARTn_DCR_RXINV;
367  break;
369  tmp = UARTn_DCR_TXINV;
370  break;
372  tmp = UARTn_DCR_RXINV | UARTn_DCR_TXINV;
373  break;
374  default:
375  break;
376  }
377 
378  if( NewState == ENABLE )
379  {
380  UARTx->DCR |= tmp;
381  }
382  else
383  {
384  UARTx->DCR &= ( ~tmp ) & UARTn_DCR_BITMASK;
385  }
386 
387  return HAL_OK;
388 }
389 
390 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
398 HAL_Status_Type HAL_UART_IFDelayConfig( UARTn_Type* UARTx, uint8_t waitval )
399 {
400  /* Check UART handle */
401  if( UARTx == NULL )
402  {
403  return HAL_ERROR;
404  }
405 
406  if( waitval < 8 )
407  {
408  UARTx->IDTR = waitval;
409  }
410 
411  return HAL_OK;
412 }
413 
414 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
423 {
424  /* Check UART handle */
425  if( UARTx == NULL )
426  {
427  return HAL_ERROR;
428  }
429 
430  UARTx->LCR |= UARTn_LCR_BREAK_EN;
431 
432  return HAL_OK;
433 }
434 
435 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
449 uint8_t HAL_UART_GetLineStatus( UARTn_Type* UARTx )
450 {
451  return ( ( UARTx->LSR ) & UARTn_LSR_BITMASK );
452 }
453 
454 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
461 FlagStatus HAL_UART_CheckBusy( UARTn_Type* UARTx )
462 {
463  if( UARTx->LSR & UARTn_LSR_TEMT )
464  {
465  return RESET;
466  }
467  else
468  {
469  return SET;
470  }
471 }
472 
473 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
482 HAL_Status_Type HAL_UART_TransmitByte( UARTn_Type* UARTx, uint8_t Data )
483 {
484  /* Check UART handle */
485  if( UARTx == NULL )
486  {
487  return HAL_ERROR;
488  }
489 
490  UARTx->THR = Data;
491 
492  return HAL_OK;
493 }
494 
495 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
502 uint8_t HAL_UART_ReceiveByte( UARTn_Type* UARTx )
503 {
504  return UARTx->RBR;
505 }
506 
507 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
524 uint32_t HAL_UART_Transmit( UARTn_Type* UARTx, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
525 {
526  uint32_t bToSend, bSent, timeOut;
527  uint8_t* pChar = txbuf;
528 
529  // init counter
530  bToSend = buflen;
531  bSent = 0;
532 
533  // blocking mode
534  if( flag == BLOCKING )
535  {
536  while( bToSend )
537  {
538  // wait until tx data register is empty with timeout
539  timeOut = UARTn_BLOCKING_TIMEOUT;
540  while( !( UARTx->LSR & UARTn_LSR_THRE ) )
541  {
542  if( timeOut == 0 )
543  {
544  break;
545  }
546  timeOut--;
547  }
548 
549  // if timeout
550  if( timeOut == 0 )
551  {
552  break;
553  }
554 
555  // send byte
556  HAL_UART_TransmitByte( UARTx, ( *pChar++ ) );
557 
558  // update counter
559  bToSend--;
560  bSent++;
561  }
562 
563  // wait until previous transmission is complete
564  while( UARTx->LSR_b.TEMT == 0 ); // Polling Only
565  }
566 
567  // Non-Blocking Mode
568  else
569  {
570  while( bToSend )
571  {
572  // if tx data register is not empty
573  if( !( UARTx->LSR & UARTn_LSR_THRE ) )
574  {
575  break;
576  }
577 
578  // send byte
579  HAL_UART_TransmitByte( UARTx, ( *pChar++ ) );
580 
581  // update counter
582  bToSend--;
583  bSent++;
584  }
585  }
586 
587  // return
588  return bSent;
589 }
590 
591 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
608 uint32_t HAL_UART_Receive( UARTn_Type* UARTx, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
609 {
610  uint32_t bToRecv, bRecv, timeOut;
611  uint8_t* pChar = rxbuf;
612 
613  // init counter
614  bToRecv = buflen;
615  bRecv = 0;
616 
617  // Blocking Mode
618  if( flag == BLOCKING )
619  {
620  while( bToRecv )
621  {
622  // wait until data are received with timeout
623  timeOut = UARTn_BLOCKING_TIMEOUT;
624  while( !( UARTx->LSR & UARTn_LSR_RDR ) )
625  {
626  if( timeOut == 0 )
627  {
628  break;
629  }
630  timeOut--;
631  }
632 
633  // if timeout
634  if( timeOut == 0 )
635  {
636  break;
637  }
638 
639  // receive byte
640  ( *pChar++ ) = HAL_UART_ReceiveByte( UARTx );
641 
642  // update counter
643  bToRecv--;
644  bRecv++;
645  }
646  }
647 
648  // Non-Blocking Mode
649  else
650  {
651  while( bToRecv )
652  {
653  // if no data were received
654  if( !( UARTx->LSR & UARTn_LSR_RDR ) )
655  {
656  break;
657  }
658 
659  // receive byte
660  ( *pChar++ ) = HAL_UART_ReceiveByte( UARTx );
661 
662  // update counter
663  bToRecv--;
664  bRecv++;
665  }
666  }
667 
668  // return
669  return bRecv;
670 }
671 
FlagStatus HAL_UART_CheckBusy(UARTn_Type *UARTx)
Check whether if UART is busy or not.
HAL_Status_Type
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_UART_ConfigInterrupt(UARTn_Type *UARTx, UARTn_INT_Type UARTn_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
UARTn_INT_Type
HAL_Status_Type HAL_UART_IFDelayConfig(UARTn_Type *UARTx, uint8_t waitval)
Configure inter-frame delay time for UART peripheral.
char InData[80]
HAL_Status_Type HAL_UART_DeInit(UARTn_Type *UARTx)
Deinitialize the UARTn peripheral registers to their default reset values.
Contains all macro definitions and function prototypes support for uartn firmware library on A31G11x.
static uint32_t UARTn_BaseClock
int InCount
uint8_t HAL_UART_GetLineStatus(UARTn_Type *UARTx)
This function returns the current value of Line Status Register.
UARTn_DATA_BIT_Type Databits
UARTn_DATA_CONTROL_Type
FunctionalState
uint32_t HAL_UART_Receive(UARTn_Type *UARTx, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Receive a block of data via UART peripheral.
HAL_Status_Type HAL_UART_ConfigStructInit(UARTn_CFG_Type *UARTn_Config)
Fills each UARTn_Config member with its default value:
uint8_t HAL_UART_ReceiveByte(UARTn_Type *UARTx)
Receive a single data from UART peripheral.
static void uart_set_divisors(UARTn_Type *UARTx, uint32_t baudrate)
Determines best dividers to get a target clock rate.
HAL_Status_Type HAL_UART_DataControlConfig(UARTn_Type *UARTx, UARTn_DATA_CONTROL_Type Mode, FunctionalState NewState)
Configure Data Control mode for UART peripheral.
UARTn_PARITY_BIT_Type Parity
UARTn_STOP_BIT_Type Stopbits
HAL_Status_Type HAL_UART_Init(UARTn_Type *UARTx, UARTn_CFG_Type *UARTn_Config)
Initialize the UARTn peripheral with the specified parameters.
int InFlag
TRANSFER_BLOCK_Type
uint32_t HAL_UART_Transmit(UARTn_Type *UARTx, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
Send a block of data via UART peripheral.
HAL_Status_Type HAL_UART_TransmitByte(UARTn_Type *UARTx, uint8_t Data)
Transmit a single data through UART peripheral.
void HAL_SCU_Peripheral_SetReset2(uint32_t u32EachPeri2)
Set/Reset Each Peripheral Block Reset of PPRST2 Register.
HAL_Status_Type HAL_UART_ForceBreak(UARTn_Type *UARTx)
Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0.
Contains all macro definitions and function prototypes support for scu firmware library on A31G11x.