52 #define TIMER3n_DISABLE (0x0uL << TIMER3n_CR_T3nEN_Pos) 53 #define TIMER3n_ENABLE (0x1uL << TIMER3n_CR_T3nEN_Pos) 56 #define TIMER3n_CLKINT (0x0uL << TIMER3n_CR_T3nCLK_Pos) 57 #define TIMER3n_CLKEXT (0x1uL << TIMER3n_CR_T3nCLK_Pos) 60 #define TIMER3n_INVM (0x0uL << TIMER3n_CR_T3nMS_Pos) 61 #define TIMER3n_CAPM (0x1uL << TIMER3n_CR_T3nMS_Pos) 62 #define TIMER3n_BTOB (0x2uL << TIMER3n_CR_T3nMS_Pos) 65 #define TIMER3n_FEDGE (0x0uL << TIMER3n_CR_T3nECE_Pos) 66 #define TIMER3n_REDGE (0x1uL << TIMER3n_CR_T3nECE_Pos) 69 #define TIMER3n_6CHMOD (0x0uL << TIMER3n_CR_FORCA_Pos) 70 #define TIMER3n_FORAMOD (0x1uL << TIMER3n_CR_FORCA_Pos) 73 #define TIMER3n_DLYINSDIS (0x0uL << TIMER3n_CR_DLYEN_Pos) 74 #define TIMER3n_DLYINSEN (0x1uL << TIMER3n_CR_DLYEN_Pos) 77 #define TIMER3n_INSFRONT (0x0uL << TIMER3n_CR_DLYPOS_Pos) 78 #define TIMER3n_INSBACK (0x1uL << TIMER3n_CR_DLYPOS_Pos) 81 #define TIMER3n_CAPFALL (0x0uL << TIMER3n_CR_T3nCPOL_Pos) 82 #define TIMER3n_CAPRISE (0x1uL << TIMER3n_CR_T3nCPOL_Pos) 83 #define TIMER3n_CAPBOTH (0x2uL << TIMER3n_CR_T3nCPOL_Pos) 86 #define TIMER3n_UPWRITE (0x0uL << TIMER3n_CR_UPDT_Pos) 87 #define TIMER3n_UPMATCH (0x1uL << TIMER3n_CR_UPDT_Pos) 88 #define TIMER3n_UPBOTTOM (0x2uL << TIMER3n_CR_UPDT_Pos) 91 #define TIMER3n_E1PERIOD (0x00uL << TIMER3n_CR_PMOC_Pos) 92 #define TIMER3n_E2PERIOD (0x01uL << TIMER3n_CR_PMOC_Pos) 93 #define TIMER3n_E3PERIOD (0x02uL << TIMER3n_CR_PMOC_Pos) 94 #define TIMER3n_E4PERIOD (0x03uL << TIMER3n_CR_PMOC_Pos) 95 #define TIMER3n_E5PERIOD (0x04uL << TIMER3n_CR_PMOC_Pos) 96 #define TIMER3n_E6PERIOD (0x05uL << TIMER3n_CR_PMOC_Pos) 97 #define TIMER3n_E7PERIOD (0x06uL << TIMER3n_CR_PMOC_Pos) 98 #define TIMER3n_E8PERIOD (0x07uL << TIMER3n_CR_PMOC_Pos) 103 #define TIMER3n_OUT_BPOLOW (0x0uL << TIMER3n_OUTCR_POLB_Pos) 104 #define TIMER3n_OUT_BPOHIGH (0x1uL << TIMER3n_OUTCR_POLB_Pos) 107 #define TIMER3n_OUT_APOLOW (0x0uL << TIMER3n_OUTCR_POLA_Pos) 108 #define TIMER3n_OUT_APOHIGH (0x1uL << TIMER3n_OUTCR_POLA_Pos) 111 #define TIMER3n_OUT_PWMABDIS (0x0uL << TIMER3n_OUTCR_PABOE_Pos) 112 #define TIMER3n_OUT_PWMABEN (0x1uL << TIMER3n_OUTCR_PABOE_Pos) 115 #define TIMER3n_OUT_PWMBBDIS (0x0uL << TIMER3n_OUTCR_PBBOE_Pos) 116 #define TIMER3n_OUT_PWMBBEN (0x1uL << TIMER3n_OUTCR_PBBOE_Pos) 119 #define TIMER3n_OUT_PWMCBDIS (0x0uL << TIMER3n_OUTCR_PCBOE_Pos) 120 #define TIMER3n_OUT_PWMCBEN (0x1uL << TIMER3n_OUTCR_PCBOE_Pos) 123 #define TIMER3n_OUT_PWMAADIS (0x0uL << TIMER3n_OUTCR_PAAOE_Pos) 124 #define TIMER3n_OUT_PWMAAEN (0x1uL << TIMER3n_OUTCR_PAAOE_Pos) 127 #define TIMER3n_OUT_PWMBADIS (0x0uL << TIMER3n_OUTCR_PBAOE_Pos) 128 #define TIMER3n_OUT_PWMBAEN (0x1uL << TIMER3n_OUTCR_PBAOE_Pos) 131 #define TIMER3n_OUT_PWMCADIS (0x0uL << TIMER3n_OUTCR_PCAOE_Pos) 132 #define TIMER3n_OUT_PWMCAEN (0x1uL << TIMER3n_OUTCR_PCAOE_Pos) 135 #define TIMER3n_OUT_ABLOW (0x0uL << TIMER3n_OUTCR_LVLAB_Pos) 136 #define TIMER3n_OUT_ABHIGH (0x1uL << TIMER3n_OUTCR_LVLAB_Pos) 139 #define TIMER3n_OUT_BBLOW (0x0uL << TIMER3n_OUTCR_LVLBB_Pos) 140 #define TIMER3n_OUT_BBHIGH (0x1uL << TIMER3n_OUTCR_LVLBB_Pos) 143 #define TIMER3n_OUT_CBLOW (0x0uL << TIMER3n_OUTCR_LVLCB_Pos) 144 #define TIMER3n_OUT_CBHIGH (0x1uL << TIMER3n_OUTCR_LVLCB_Pos) 147 #define TIMER3n_OUT_AALOW (0x0uL << TIMER3n_OUTCR_LVLAA_Pos) 148 #define TIMER3n_OUT_AAHIGH (0x1uL << TIMER3n_OUTCR_LVLAA_Pos) 151 #define TIMER3n_OUT_BALOW (0x0uL << TIMER3n_OUTCR_LVLBA_Pos) 152 #define TIMER3n_OUT_BAHIGH (0x1uL << TIMER3n_OUTCR_LVLBA_Pos) 155 #define TIMER3n_OUT_CALOW (0x0uL << TIMER3n_OUTCR_LVLCA_Pos) 156 #define TIMER3n_OUT_CAHIGH (0x1uL << TIMER3n_OUTCR_LVLCA_Pos) 161 #define TIMER3n_INT_HIZDIS (0x0uL << TIMER3n_INTCR_HIZIEN_Pos) 162 #define TIMER3n_INT_HIZEN (0x1uL << TIMER3n_INTCR_HIZIEN_Pos) 165 #define TIMER3n_INT_CAPDIS (0x0uL << TIMER3n_INTCR_T3nCIEN_Pos) 166 #define TIMER3n_INT_CAPEN (0x1uL << TIMER3n_INTCR_T3nCIEN_Pos) 169 #define TIMER3n_INT_BOTDIS (0x0uL << TIMER3n_INTCR_T3nBTIEN_Pos) 170 #define TIMER3n_INT_BOTEN (0x1uL << TIMER3n_INTCR_T3nBTIEN_Pos) 173 #define TIMER3n_INT_PMATDIS (0x0uL << TIMER3n_INTCR_T3nPMIEN_Pos) 174 #define TIMER3n_INT_PMATEN (0x1uL << TIMER3n_INTCR_T3nPMIEN_Pos) 177 #define TIMER3n_INT_AMATDIS (0x0uL << TIMER3n_INTCR_T3nAMIEN_Pos) 178 #define TIMER3n_INT_AMATEN (0x1uL << TIMER3n_INTCR_T3nAMIEN_Pos) 181 #define TIMER3n_INT_BMATDIS (0x0uL << TIMER3n_INTCR_T3nBMIEN_Pos) 182 #define TIMER3n_INT_BMATEN (0x1uL << TIMER3n_INTCR_T3nBMIEN_Pos) 185 #define TIMER3n_INT_CMATDIS (0x0uL << TIMER3n_INTCR_T3nCMIEN_Pos) 186 #define TIMER3n_INT_CMATEN (0x1uL << TIMER3n_INTCR_T3nCMIEN_Pos) 191 #define TIMER3n_HIZ_DISABLE (0x0uL << TIMER3n_HIZCR_HIZEN_Pos) 192 #define TIMER3n_HIZ_ENABLE (0x1uL << TIMER3n_HIZCR_HIZEN_Pos) 195 #define TIMER3n_HIZ_BLNKFALL (0x0uL << TIMER3n_HIZCR_HEDGE_Pos) 196 #define TIMER3n_HIZ_BLNKRISE (0x1uL << TIMER3n_HIZCR_HEDGE_Pos) 201 #define TIMER3n_ADT_BTTGDIS (0x0uL << TIMER3n_ADTCR_T3nBTTG_Pos) 202 #define TIMER3n_ADT_BTTGEN (0x1uL << TIMER3n_ADTCR_T3nBTTG_Pos) 205 #define TIMER3n_ADT_PMTGDIS (0x0uL << TIMER3n_ADTCR_T3nPMTG_Pos) 206 #define TIMER3n_ADT_PMTGEN (0x1uL << TIMER3n_ADTCR_T3nPMTG_Pos) 209 #define TIMER3n_ADT_AMTGDIS (0x0uL << TIMER3n_ADTCR_T3nAMTG_Pos) 210 #define TIMER3n_ADT_AMTGEN (0x1uL << TIMER3n_ADTCR_T3nAMTG_Pos) 213 #define TIMER3n_ADT_BMTGDIS (0x0uL << TIMER3n_ADTCR_T3nBMTG_Pos) 214 #define TIMER3n_ADT_BMTGEN (0x1uL << TIMER3n_ADTCR_T3nBMTG_Pos) 217 #define TIMER3n_ADT_CMTGDIS (0x0uL << TIMER3n_ADTCR_T3nCMTG_Pos) 218 #define TIMER3n_ADT_CMTGEN (0x1uL << TIMER3n_ADTCR_T3nCMTG_Pos) 261 #define TIMER3n_EN() (TIMER30->CR_b.T3nEN = 1) 262 #define TIMER3n_DIS() (TIMER30->CR_b.T3nEN = 0) 263 #define TIMER3n_EnableTimer( TIMER3x ) (TIMER3x->CR_b.T3nEN = 1) 264 #define TIMER3n_DisableTimer( TIMER3x ) (TIMER3x->CR_b.T3nEN = 0) 270 #define TIMER3n_ClrCnt() (TIMER30->CR_b.T3nCLR = 1) 271 #define TIMER3n_ClearCounter( TIMER3x ) (TIMER3x->CR_b.T3nCLR = 1) 277 #define TIMER3n_GetCnt() (TIMER30->CNT) 283 #define TIMER3n_SetPMOC( u32PMOC ) (TIMER30->CR_b.PMOC = u32PMOC) 289 #define TIMER3n_HIZEN() (TIMER30->HIZCR_b.T3nEN = 1) 290 #define TIMER3n_HIZDIS() (TIMER30->HIZCR_b.T3nEN = 0) 296 #define TIMER3n_SetHIZSW() (TIMER30->HIZCR_b.HIZSW = 1) 302 #define TIMER3n_ClrHIZ() (TIMER30->HIZCR_b.HIZCLR = 1) 308 #define TIMER3n_GetHIZStaus() (TIMER30->HIZCR_b.HIZSTA) 317 #define TIMER3n_SetPeData( u32PData ) (TIMER30->PDR = u32PData) 325 #define TIMER3n_SetAData( u32AData ) (TIMER30->ADR = u32AData) 333 #define TIMER3n_SetBData( u32BData ) (TIMER30->BDR = u32BData) 341 #define TIMER3n_SetCData( u32CData ) (TIMER30->CDR = u32CData) 347 #define TIMER3n_GetCapData() (TIMER30->CAPDR) 348 #define TIMER3n_GetCaptureData( TIMER3x ) (TIMER3x->CAPDR) 356 #define TIMER3n_SetDelayData( u32DelayData ) (TIMER30->DLY = u32DelayData) 364 #define TIMER3n_SetADTData( u32ADTData ) (TIMER30->ADTDR = u32ADTData) 371 #define TIMER3n_AllInt_GetFg() (TIMER30->INTFLAG) 377 #define TIMER3n_CMaInt_GetFg() (TIMER30->INTFLAG_b.T30CMIFLAG) 383 #define TIMER3n_BMaInt_GetFg() (TIMER30->INTFLAG_b.T30BMIFLAG) 389 #define TIMER3n_AchMaInt_GetFg() (TIMER30->INTFLAG_b.T30AMIFLAG) 395 #define TIMER3n_PeMaInt_GetFg() (TIMER30->INTFLAG_b.T30PMIFLAG) 401 #define TIMER3n_BotMaInt_GetFg() (TIMER30->INTFLAG_b.T30BTIFLAG) 407 #define TIMER3n_CapInt_GetFg() (TIMER30->INTFLAG_b.T30CIFLAG) 413 #define TIMER3n_HIZInt_GetFg() (TIMER30->INTFLAG_b.HIZIFLAG) 419 #define TIMER3n_AllInt_ClrFg() (TIMER30->INTFLAG = 0x7F) 425 #define TIMER3n_CchMaInt_ClrFg() (TIMER30->INTFLAG_b.T30CMIFLAG = 1) 431 #define TIMER3n_BchMaInt_ClrFg() (TIMER30->INTFLAG_b.T30BMIFLAG = 1) 437 #define TIMER3n_AchMaInt_ClrFg() (TIMER30->INTFLAG_b.T30AMIFLAG = 1) 443 #define TIMER3n_PeMaInt_ClrFg() (TIMER30->INTFLAG_b.T30PMIFLAG = 1) 449 #define TIMER3n_BotMaInt_ClrFg() (TIMER30->INTFLAG_b.T30BTIFLAG = 1) 455 #define TIMER3n_CapInt_ClrFg() (TIMER30->INTFLAG_b.T30CIFLAG = 1) 461 #define TIMER3n_HIZInt_ClrFg() (TIMER30->INTFLAG_b.HIZIFLAG = 1)
HAL_Status_Type HAL_TIMER3n_ConfigInterrupt(TIMER3n_Type *TIMER3x, uint32_t NewState, uint32_t TIMER3n_IntCfg)
Interrupt Control Register.
HAL_Status_Type HAL_TIMER3n_ClearStatus_IT(TIMER3n_Type *TIMER3x, uint32_t TIMER3n_IntCfg)
Interrupt Flag Clear.
Contains the ABOV typedefs for C standard types. It is intended to be used in ISO C conforming develo...
HAL_Status_Type HAL_TIMER3n_SetBDuty(TIMER3n_Type *TIMER3x, uint32_t bduty)
Set duty B data.
HAL_Status_Type HAL_TIMER3n_Init(TIMER3n_Type *TIMER3x, TIMER3n_CFG_Type *TIMER3n_Config)
Initialize the TIMER3n peripheral with the specified parameters.
HAL_Status_Type HAL_TIMER3n_Start(TIMER3n_Type *TIMER3x, uint32_t NewState)
Enable or Disable PWM start.
HAL_Status_Type HAL_TIMER3n_DeInit(TIMER3n_Type *TIMER3x)
Close Timer/Counter device.
HAL_Status_Type HAL_TIMER3n_SetADCTrigger(TIMER3n_Type *TIMER3x, uint32_t u32triggerpoint, uint32_t u32triggertime)
Set ADC Tirgger Source & Timing.
HAL_Status_Type HAL_TIMER3n_SetDelayTime(TIMER3n_Type *TIMER3x, uint32_t dten, uint32_t dtpos, uint32_t clkdata)
Set dead time (delay time)
HAL_Status_Type HAL_TIMER3n_MPWMCmd(TIMER3n_Type *TIMER3x, uint32_t updatedata, uint32_t intcount)
TIMER3n PWM Mode Setting (Initial : Back to Back Mode, Internal Clock, 6channel Mode)
HAL_Status_Type HAL_TIMER3n_ClockPrescaler(TIMER3n_Type *TIMER3x, uint32_t prescale)
Set Prescaler data.
HAL_Status_Type HAL_TIMER3n_OutputCtrl(TIMER3n_Type *TIMER3x, uint32_t NewState, uint32_t pwmApol, uint32_t pwmBpol)
PWM Output Port Control Register (Initial : 6channel enable, output low)
TIMER3n_CR_T3nCPOL_Enum T3nCPOL
HAL_Status_Type HAL_TIMER3n_SetPeriod(TIMER3n_Type *TIMER3x, uint32_t period)
Set period data.
TIMER3n_CR_T3nMS_Enum T3nMS
TIMER3n_CR_T3nCLK_Enum T3nCLK
HAL_Status_Type HAL_TIMER3n_SetCDuty(TIMER3n_Type *TIMER3x, uint32_t cduty)
Set duty C data.
HAL_Status_Type HAL_TIMER3n_SetHizReg(TIMER3n_Type *TIMER3x, uint32_t u32T30HizSet)
Set HIZCR Register.
TIMER3n_CR_T3nECE_Enum T3nECE
uint32_t HAL_TIMER3n_GetStatus_IT(TIMER3n_Type *TIMER3x)
Get Interrupt Flag.
HAL_Status_Type HAL_TIMER3n_SetADuty(TIMER3n_Type *TIMER3x, uint32_t aduty)
Set duty A data.