A31G11x F/W Packages  2.5.0
ABOV Cortex-M0+ Core based MCUs Integrated Driver
A31G11x_hal_wdt.c
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1 /***************************************************************************//****************************************************************************/
34 
35 /* Includes ----------------------------------------------------------------- */
36 //******************************************************************************
37 // Include
38 //******************************************************************************
39 
40 #include "A31G11x_hal_wdt.h"
41 #include "A31G11x_hal_scu.h"
42 
43 /* Public Functions --------------------------------------------------------- */
44 //******************************************************************************
45 // Function
46 //******************************************************************************
47 
48 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
56 {
57  uint32_t reg_val = 0;
58 
59  /* Check WDT_Config */
60  if( WDT_Config == NULL )
61  {
62  return HAL_ERROR;
63  }
64 
65  // enable peripheral clock
66  HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_WDTCLKE, PPxCLKE_Enable );
67 
68  WDT->DR = ( WDT_Config->wdtTmrConst & 0x00FFFFFF );
69  WDT->WINDR = ( WDT_Config->wdtWTmrConst & 0x00FFFFFF );
70  reg_val = WDT_Config->wdtClkDiv;
71  if( WDT_Config->wdtResetEn == ENABLE )
72  {
73  reg_val &= ~( 0x3f << WDT_CR_RSTEN_Pos );
74  }
75  else
76  {
77  reg_val |= ( 0x25 << WDT_CR_RSTEN_Pos );
78  }
79  WDT->CR = ( 0x5A69 << WDT_CR_WTIDKY_Pos ) | ( 0x1a << WDT_CR_CNTEN_Pos ) | reg_val; // /w Write Identification Key
80 
81  // return
82  return HAL_OK;
83 }
84 
85 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
91 {
92  WDT->CR = 0
93  | ( 0x5A69 << WDT_CR_WTIDKY_Pos ) // Write Identification Key
94  | ( 0x25 << WDT_CR_RSTEN_Pos ) // Disable watch-dog timer reset
95  | ( 0x1A << WDT_CR_CNTEN_Pos ) // Disable watch-dog timer counter
96  ;
97 
98  // return
99  return HAL_OK;
100 }
101 
102 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
114 {
115 #if 0 // before bug fix
116  uint32_t reg_val = 0;
117  uint32_t tmp = 0;
118 
119  reg_val = ( WDT->CR & 0xFFFF );
120 
121  switch( WDT_IntCfg )
122  {
123  case WDT_INTCFG_UNFIEN:
124  tmp = WDT_CR_UNFIEN;
125  break;
126  case WDT_INTCFG_WINMIEN:
127  tmp = WDT_CR_WINMIEN;
128  break;
129  }
130 
131  if( NewState == ENABLE )
132  {
133  reg_val |= ( tmp & WDT_INTERRUPT_BITMASK );
134  }
135  else
136  {
137  reg_val &= ( ( ~tmp ) & WDT_INTERRUPT_BITMASK ); // reg_val &= ~tmp;°¡ ¿ÇÀ» µí...
138  }
139 
140  WDT->CR = ( 0x5A69 << WDT_CR_WTIDKY_Pos ) | reg_val; // Write Identification Key 0x5A69
141 #else // after bug fix
142  uint32_t reg_val = 0;
143  uint32_t mask = 0;
144 
145  switch( WDT_IntCfg )
146  {
147  case WDT_INTCFG_UNFIEN:
148  mask = WDT_CR_UNFIEN_Msk;
149  break;
150  case WDT_INTCFG_WINMIEN:
151  mask = WDT_CR_WINMIEN_Msk;
152  break;
153  }
154 
155  reg_val = WDT->CR
156  & ~( WDT_CR_WTIDKY_Msk )
157  | ( ( uint32_t )WDT_CR_WTIDKY_Value << WDT_CR_WTIDKY_Pos )
158  ;
159  if( NewState == ENABLE )
160  {
161  reg_val |= mask;
162  }
163  else
164  {
165  reg_val &= ~mask;
166  }
167 
168  WDT->CR = reg_val;
169 #endif
170 
171  return HAL_OK;
172 }
173 
174 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
180 {
181  WDT->CNTR = 0x6a;
182 
183  return HAL_OK;
184 }
185 
186 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
194 {
195  uint32_t tmp_reg;
196 
197  tmp_reg = WDT->CR & 0xFFFF;
198  tmp_reg |= ( 0x1a << WDT_CR_CNTEN_Pos ); // Disable watch-dog timer counter
199 
200  if( ctrl == ENABLE )
201  {
202  tmp_reg &= ~( 0x3f << WDT_CR_CNTEN_Pos ); // Enable watch-dog timer counter,
203  }
204 
205  WDT->CR = ( 0x5A69 << WDT_CR_WTIDKY_Pos ) | tmp_reg; // Write Identification Key 0x5A69
206 
207  return HAL_OK;
208 }
209 
210 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
218 {
219  WDT->SR = clrbit;
220 
221  return HAL_OK;
222 }
223 
224 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
229 uint32_t HAL_WDT_GetStatus( void )
230 {
231  return WDT->SR;
232 }
233 
234 /*-------------------------------------------------------------------------*//*-------------------------------------------------------------------------*/
239 uint32_t HAL_WDT_GetCurrentCount( void )
240 {
241  return WDT->CNT;
242 }
243 
HAL_Status_Type HAL_WDT_DeInit(void)
Deinitialize WDT.
HAL_Status_Type
uint8_t wdtResetEn
HAL_Status_Type HAL_WDT_Start(FunctionalState ctrl)
Enable WDT activity.
void HAL_SCU_Peripheral_EnableClock2(uint32_t u32PeriClk2, uint32_t u32Ind)
Set Each Peripheral Clock.
HAL_Status_Type HAL_WDT_ConfigInterrupt(WDT_INT_Type WDT_IntCfg, FunctionalState NewState)
Configure the peripheral interrupt.
uint16_t wdtClkDiv
Contains all macro definitions and function prototypes support for wdt firmware library on A31G11x.
FunctionalState
HAL_Status_Type HAL_WDT_ReloadTimeCounter(void)
Reload WDT counter.
HAL_Status_Type HAL_WDT_ClearStatus(uint32_t clrbit)
Clear the timer status register of WDT.
HAL_Status_Type HAL_WDT_Init(WDT_CFG_Type *WDT_Config)
Initialize the WDT peripheral with the specified parameters.
WDT_INT_Type
uint32_t HAL_WDT_GetCurrentCount(void)
Get the current value of WDT.
uint32_t wdtTmrConst
uint32_t wdtWTmrConst
uint32_t HAL_WDT_GetStatus(void)
Get the timer status register of WDT.
Contains all macro definitions and function prototypes support for scu firmware library on A31G11x.